aboutsummaryrefslogtreecommitdiffstats
path: root/test/CodeGen/XCore/ashr.ll
diff options
context:
space:
mode:
authorRichard Osborne <richard@xmos.com>2009-10-08 15:38:17 +0000
committerRichard Osborne <richard@xmos.com>2009-10-08 15:38:17 +0000
commitc96c8e0e81f81e2b02be94d2f1957dcfdf659d62 (patch)
treec9eace957480757a7ccf7806d66e0c122113944b /test/CodeGen/XCore/ashr.ll
parent80ed255843980b774af7c8d979730df8b6d2bbaf (diff)
downloadexternal_llvm-c96c8e0e81f81e2b02be94d2f1957dcfdf659d62.zip
external_llvm-c96c8e0e81f81e2b02be94d2f1957dcfdf659d62.tar.gz
external_llvm-c96c8e0e81f81e2b02be94d2f1957dcfdf659d62.tar.bz2
Add some peepholes for signed comparisons using ashr X, X, 32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83549 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/XCore/ashr.ll')
-rw-r--r--test/CodeGen/XCore/ashr.ll76
1 files changed, 76 insertions, 0 deletions
diff --git a/test/CodeGen/XCore/ashr.ll b/test/CodeGen/XCore/ashr.ll
new file mode 100644
index 0000000..d585e8b
--- /dev/null
+++ b/test/CodeGen/XCore/ashr.ll
@@ -0,0 +1,76 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+define i32 @ashr(i32 %a, i32 %b) {
+ %1 = ashr i32 %a, %b
+ ret i32 %1
+}
+; CHECK: ashr:
+; CHECK-NEXT: ashr r0, r0, r1
+
+define i32 @ashri1(i32 %a) {
+ %1 = ashr i32 %a, 24
+ ret i32 %1
+}
+; CHECK: ashri1:
+; CHECK-NEXT: ashr r0, r0, 24
+
+define i32 @ashri2(i32 %a) {
+ %1 = ashr i32 %a, 31
+ ret i32 %1
+}
+; CHECK: ashri2:
+; CHECK-NEXT: ashr r0, r0, 32
+
+define i32 @f1(i32 %a) {
+ %1 = icmp slt i32 %a, 0
+ br i1 %1, label %less, label %not_less
+less:
+ ret i32 10
+not_less:
+ ret i32 17
+}
+; CHECK: f1:
+; CHECK-NEXT: ashr r0, r0, 32
+; CHECK-NEXT: bf r0
+
+define i32 @f2(i32 %a) {
+ %1 = icmp sge i32 %a, 0
+ br i1 %1, label %greater, label %not_greater
+greater:
+ ret i32 10
+not_greater:
+ ret i32 17
+}
+; CHECK: f2:
+; CHECK-NEXT: ashr r0, r0, 32
+; CHECK-NEXT: bt r0
+
+define i32 @f3(i32 %a) {
+ %1 = icmp slt i32 %a, 0
+ %2 = select i1 %1, i32 10, i32 17
+ ret i32 %2
+}
+; CHECK: f3:
+; CHECK-NEXT: ashr r1, r0, 32
+; CHECK-NEXT: ldc r0, 10
+; CHECK-NEXT: bt r1
+; CHECK: ldc r0, 17
+
+define i32 @f4(i32 %a) {
+ %1 = icmp sge i32 %a, 0
+ %2 = select i1 %1, i32 10, i32 17
+ ret i32 %2
+}
+; CHECK: f4:
+; CHECK-NEXT: ashr r1, r0, 32
+; CHECK-NEXT: ldc r0, 17
+; CHECK-NEXT: bt r1
+; CHECK: ldc r0, 10
+
+define i32 @f5(i32 %a) {
+ %1 = icmp sge i32 %a, 0
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+; CHECK: f5:
+; CHECK-NEXT: ashr r0, r0, 32
+; CHECK-NEXT: eq r0, r0, 0