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| author | Andrew Trick <atrick@apple.com> | 2012-11-12 19:28:57 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-11-12 19:28:57 +0000 |
| commit | ae692f2baedf53504af2715993b166950e185a55 (patch) | |
| tree | 02610907bc6cdff18150f1c67341c8c7eaf68e6b /test/CodeGen | |
| parent | 95d8afc5f2898b59240b0c0cd78d6f54140a91b8 (diff) | |
| download | external_llvm-ae692f2baedf53504af2715993b166950e185a55.zip external_llvm-ae692f2baedf53504af2715993b166950e185a55.tar.gz external_llvm-ae692f2baedf53504af2715993b166950e185a55.tar.bz2 | |
misched: Infrastructure for weak DAG edges.
This adds support for weak DAG edges to the general scheduling
infrastructure in preparation for MachineScheduler support for
heuristics based on weak edges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167738 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen')
| -rw-r--r-- | test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll index b05ec63..ca0964a 100644 --- a/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll +++ b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll @@ -13,6 +13,7 @@ ; CHECK-NOT: ch SU ; CHECK: ch SU(2): Latency=1 ; CHECK-NOT: ch SU +; CHECK: Successors: ; CHECK: ** List Scheduling ; CHECK: SU(2){{.*}}STR{{.*}} ; CHECK-NOT: ch SU @@ -22,6 +23,7 @@ ; CHECK-NOT: ch SU ; CHECK: ch SU(2): Latency=1 ; CHECK-NOT: ch SU +; CHECK: Successors: define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind { entry: store volatile i32 65540, i32* %p1, align 4, !tbaa !0 |