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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-29 18:47:24 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-29 18:47:24 +0000 |
| commit | 2c6363a62df95b74468d9a561bbcb9edddeb3507 (patch) | |
| tree | 64e1dafa4afce7a9ed628ab455eac1a215f5d5b0 /test/MC/ARM/basic-arm-instructions.s | |
| parent | ea2429896a9f4cf3176bf69e83d107f214630ec1 (diff) | |
| download | external_llvm-2c6363a62df95b74468d9a561bbcb9edddeb3507.zip external_llvm-2c6363a62df95b74468d9a561bbcb9edddeb3507.tar.gz external_llvm-2c6363a62df95b74468d9a561bbcb9edddeb3507.tar.bz2 | |
ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/ARM/basic-arm-instructions.s')
| -rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 872341f..1a27198 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -1169,6 +1169,56 @@ Lforward: @------------------------------------------------------------------------------ +@ RFE +@------------------------------------------------------------------------------ + rfeda r2 + rfedb r3 + rfeia r5 + rfeib r6 + + rfeda r4! + rfedb r7! + rfeia r9! + rfeib r8! + + rfefa r2 + rfeea r3 + rfefd r5 + rfeed r6 + + rfefa r4! + rfeea r7! + rfefd r9! + rfeed r8! + + rfe r1 + rfe r1! + +@ CHECK: rfeda r2 @ encoding: [0x00,0x0a,0x12,0xf8] +@ CHECK: rfedb r3 @ encoding: [0x00,0x0a,0x13,0xf9] +@ CHECK: rfeia r5 @ encoding: [0x00,0x0a,0x95,0xf8] +@ CHECK: rfeib r6 @ encoding: [0x00,0x0a,0x96,0xf9] + +@ CHECK: rfeda r4! @ encoding: [0x00,0x0a,0x34,0xf8] +@ CHECK: rfedb r7! @ encoding: [0x00,0x0a,0x37,0xf9] +@ CHECK: rfeia r9! @ encoding: [0x00,0x0a,0xb9,0xf8] +@ CHECK: rfeib r8! @ encoding: [0x00,0x0a,0xb8,0xf9] + +@ CHECK: rfeda r2 @ encoding: [0x00,0x0a,0x12,0xf8] +@ CHECK: rfedb r3 @ encoding: [0x00,0x0a,0x13,0xf9] +@ CHECK: rfeia r5 @ encoding: [0x00,0x0a,0x95,0xf8] +@ CHECK: rfeib r6 @ encoding: [0x00,0x0a,0x96,0xf9] + +@ CHECK: rfeda r4! @ encoding: [0x00,0x0a,0x34,0xf8] +@ CHECK: rfedb r7! @ encoding: [0x00,0x0a,0x37,0xf9] +@ CHECK: rfeia r9! @ encoding: [0x00,0x0a,0xb9,0xf8] +@ CHECK: rfeib r8! @ encoding: [0x00,0x0a,0xb8,0xf9] + +@ CHECK: rfeia r1 @ encoding: [0x00,0x0a,0x91,0xf8] +@ CHECK: rfeia r1! @ encoding: [0x00,0x0a,0xb1,0xf8] + + +@------------------------------------------------------------------------------ @ RSB @------------------------------------------------------------------------------ rsb r4, r5, #0xf000 |