| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Update aosp/master LLVM for rebase to r230699. | Stephen Hines | 2015-03-23 | 1 | -6/+592 |
| * | Update to LLVM 3.5a. | Stephen Hines | 2014-04-24 | 1 | -3/+18 |
| * | [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as... | Artyom Skrobov | 2013-11-08 | 1 | -12/+12 |
| * | Make ARM hint ranges consistent, and add tests for these ranges | Artyom Skrobov | 2013-10-23 | 1 | -2/+2 |
| * | [ARM] Introduce the 'sevl' instruction in ARMv8. | Joey Gouly | 2013-10-01 | 1 | -0/+2 |
| * | Fix signed overflow in when computing encodings for ADR instructions | Mihai Popa | 2013-08-13 | 1 | -1/+2 |
| * | Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc ins... | Mihai Popa | 2013-08-06 | 1 | -6/+2 |
| * | [ARMAsmParser] Sort the ARM register lists based on the encoding value, not the | Chad Rosier | 2013-07-01 | 1 | -20/+20 |
| * | ARM: Fix pseudo-instructions for SRS (Store Return State). | Tilmann Scheller | 2013-06-28 | 1 | -14/+14 |
| * | Improve the compression of the tablegen DiffLists by introducing a new sort | Chad Rosier | 2013-06-27 | 1 | -18/+18 |
| * | ARM: fix more cases where predication may or may not be allowed | Tim Northover | 2013-06-26 | 1 | -0/+12 |
| * | This reverts r155000. | Joey Gouly | 2013-06-20 | 1 | -0/+2 |
| * | Change the arm assembler to support this from the v7c spec: | Kevin Enderby | 2013-06-18 | 1 | -0/+2 |
| * | ARM: ISB cannot be passed the same options as DMB | Amaury de la Vieuville | 2013-06-10 | 1 | -0/+4 |
| * | This is a simple patch that changes RRX and RRXS to accept all registers as o... | Mihai Popa | 2013-06-05 | 1 | -0/+24 |
| * | ARM: permit upper-case BE/LE on setend instruction | Tim Northover | 2013-05-31 | 1 | -0/+4 |
| * | The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instruction... | Mihai Popa | 2013-05-13 | 1 | -3/+11 |
| * | ARM: Fix encoding of hint instruction for Thumb. | Quentin Colombet | 2013-04-26 | 1 | -2/+0 |
| * | Fix treatment of ARM unallocated hint instructions. | Quentin Colombet | 2013-04-17 | 1 | -1/+1 |
| * | ARM: Correct printing of pre-indexed operands. | Quentin Colombet | 2013-04-12 | 1 | -1/+1 |
| * | ARM: Make "SMC" instructions conditional on new TrustZone architecture feature. | Tim Northover | 2013-04-10 | 1 | -9/+0 |
| * | ARM: permit full range of valid ADR immediates. | Tim Northover | 2013-02-27 | 1 | -0/+4 |
| * | ARM: Convenience aliases for 'srs*' instructions. | Jim Grosbach | 2013-02-23 | 1 | -0/+43 |
| * | Fix #13138, a bug around ARM instruction DSB encoding and decoding issue. | Jiangning Liu | 2012-08-02 | 1 | -0/+74 |
| * | Fix #13241, a bug around shift immediate operand for ARM instruction ADR. | Jiangning Liu | 2012-08-02 | 1 | -0/+8 |
| * | Prevent ARM assembler from losing a right shift by #32 applied to a register | Richard Barton | 2012-07-09 | 1 | -0/+33 |
| * | Teach assembler to handle capitalised operation values for DSB instructions | Richard Barton | 2012-06-27 | 1 | -0/+6 |
| * | ARM: Define generic HINT instruction. | Jim Grosbach | 2012-06-18 | 1 | -7/+19 |
| * | Specify cpu to unbreak tests. | Evan Cheng | 2012-04-26 | 1 | -1/+1 |
| * | Ensure conditional BL instructions for ARM are given the fixup fixup_arm_cond... | James Molloy | 2012-03-30 | 1 | -1/+4 |
| * | ARM assembly 'cmp lr, #0' should not encode using 'cmn'. | Jim Grosbach | 2012-03-29 | 1 | -0/+2 |
| * | ARM BL/BLX instruction fixups should use relocations. | Jim Grosbach | 2012-02-27 | 1 | -2/+2 |
| * | ARM assembly shifts by zero should be plain 'mov' instructions. | Jim Grosbach | 2011-12-20 | 1 | -0/+17 |
| * | ARM/Thumb2 'cmp rn, #imm' alias to cmn. | Jim Grosbach | 2011-12-14 | 1 | -0/+2 |
| * | ARM LDM/STM system instruction variants. | Jim Grosbach | 2011-12-13 | 1 | -0/+6 |
| * | ARM pre-UAL NEG mnemonic for convenience when porting old code. | Jim Grosbach | 2011-12-13 | 1 | -0/+8 |
| * | ARM assembly aliases for BIC<-->AND (immediate). | Jim Grosbach | 2011-12-09 | 1 | -0/+2 |
| * | ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm". | Jim Grosbach | 2011-12-08 | 1 | -1/+6 |
| * | ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands. | Jim Grosbach | 2011-12-07 | 1 | -0/+2 |
| * | ARM mode 'mul' operand ordering tweak. | Jim Grosbach | 2011-12-06 | 1 | -1/+0 |
| * | Generalize the fixup info for ARM mode. | Jim Grosbach | 2011-11-16 | 1 | -2/+2 |
| * | ARM assembly parsing two operand forms for shift instructions. | Jim Grosbach | 2011-11-15 | 1 | -0/+8 |
| * | ARM assembly parsing for two-operand form of 'mul' instruction. | Jim Grosbach | 2011-11-15 | 1 | -0/+2 |
| * | ARM assembly parsing for LSR/LSL/ROR(immediate). | Jim Grosbach | 2011-11-10 | 1 | -2/+33 |
| * | ARM assembly parsing for ASR(immediate). | Jim Grosbach | 2011-11-10 | 1 | -1/+8 |
| * | Revert r142618, r142622, and r142624, which were based on an incorrect readin... | Owen Anderson | 2011-10-20 | 1 | -18/+18 |
| * | Fix tests for corrected MSR encodings. | Owen Anderson | 2011-10-20 | 1 | -18/+18 |
| * | ARM encoding tests for STC. | Jim Grosbach | 2011-10-12 | 1 | -0/+85 |
| * | ARM parsing and encoding for the <option> form of LDC/STC instructions. | Jim Grosbach | 2011-10-12 | 1 | -0/+4 |
| * | ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions. | Jim Grosbach | 2011-10-11 | 1 | -0/+81 |
