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| author | Stephen Hines <srhines@google.com> | 2014-12-01 14:51:49 -0800 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-12-02 16:08:10 -0800 |
| commit | 37ed9c199ca639565f6ce88105f9e39e898d82d0 (patch) | |
| tree | 8fb36d3910e3ee4c4e1b7422f4f017108efc52f5 /test/MC/ARM | |
| parent | d2327b22152ced7bc46dc629fc908959e8a52d03 (diff) | |
| download | external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.zip external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.gz external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.bz2 | |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
Diffstat (limited to 'test/MC/ARM')
37 files changed, 1430 insertions, 470 deletions
diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s index a4b6bda..a4c100e 100644 --- a/test/MC/ARM/arm_instructions.s +++ b/test/MC/ARM/arm_instructions.s @@ -1,6 +1,6 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s \ @ RUN: | FileCheck %s -check-prefix=ALL -@ RUN: llvm-mc -mcpu=cortex-a9-mp -triple armv7-unknown-nacl -show-encoding %s \ +@ RUN: llvm-mc -mcpu=cortex-a9 -triple armv7-unknown-nacl -show-encoding %s \ @ RUN: | FileCheck %s -check-prefix=NACL @ RUN: llvm-mc -mcpu=cortex-a8 -mattr=+nacl-trap -triple armv7 -show-encoding %s \ @ RUN: | FileCheck %s -check-prefix=NACL diff --git a/test/MC/ARM/coff-debugging-secrel.ll b/test/MC/ARM/coff-debugging-secrel.ll index f37b19e..0e5c8e6 100644 --- a/test/MC/ARM/coff-debugging-secrel.ll +++ b/test/MC/ARM/coff-debugging-secrel.ll @@ -17,16 +17,16 @@ entry: !llvm.module.flags = !{!9, !10} !0 = metadata !{i32 1, i32 0, metadata !1, null} -!1 = metadata !{i32 786478, metadata !2, metadata !3, metadata !"function", metadata !"function", metadata !"", i32 1, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void ()* @function, null, null, metadata !6, i32 1} ; [ DW_TAG_subprogram ], [line 1], [def], [function] +!1 = metadata !{metadata !"0x2e\00function\00function\00\001\000\001\000\006\000\000\001", metadata !2, metadata !3, metadata !4, null, void ()* @function, null, null, metadata !6} ; [ DW_TAG_subprogram ], [line 1], [def], [function] !2 = metadata !{metadata !"/Users/compnerd/work/llvm/test/MC/ARM/reduced.c", metadata !"/Users/compnerd/work/llvm"} -!3 = metadata !{i32 786473, metadata !2} ; [ DW_TAG_file_type] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c] -!4 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ], [line 0, size 0, align 0, offset 0] [from ] +!3 = metadata !{metadata !"0x29", metadata !2} ; [ DW_TAG_file_type] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c] +!4 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !5, null, null, null} ; [ DW_TAG_subroutine_type ], [line 0, size 0, align 0, offset 0] [from ] !5 = metadata !{null} !6 = metadata !{} -!7 = metadata !{i32 786449, metadata !2, i32 12, metadata !"clang version 3.5.0", i1 false, metadata !"", i32 0, metadata !6, metadata !6, metadata !8, metadata !6, metadata !6, metadata !"", i32 1} ; [ DW_TAG_compile_unit ] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c] [DW_LANG_C99] +!7 = metadata !{metadata !"0x11\0012\00clang version 3.5.0\000\00\000\00\001", metadata !2, metadata !6, metadata !6, metadata !8, metadata !6, metadata !6} ; [ DW_TAG_compile_unit ] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c] [DW_LANG_C99] !8 = metadata !{metadata !1} !9 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} -!10 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} +!10 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} ; CHECK-ITANIUM: Relocations [ ; CHECK-ITANIUM: Section {{.*}} .debug_info { @@ -42,8 +42,10 @@ entry: ; CHECK-MSVC: Relocations [ ; CHECK-MSVC: Section {{.*}} .debug$S { -; CHECK-MSVC: 0xC IMAGE_REL_ARM_SECREL function -; CHECK-MSVC: 0x10 IMAGE_REL_ARM_SECTION function +; CHECK-MSVC: 0x2C IMAGE_REL_ARM_SECREL function +; CHECK-MSVC: 0x30 IMAGE_REL_ARM_SECTION function +; CHECK-MSVC: 0x48 IMAGE_REL_ARM_SECREL function +; CHECK-MSVC: 0x4C IMAGE_REL_ARM_SECTION function ; CHECK-MSVC: } ; CHECK-MSVC: ] diff --git a/test/MC/ARM/coff-file.s b/test/MC/ARM/coff-file.s index f0dd29a..d3f26f4 100644 --- a/test/MC/ARM/coff-file.s +++ b/test/MC/ARM/coff-file.s @@ -21,7 +21,7 @@ // CHECK-SCN: Symbols [ // CHECK-SCN: Symbol { // CHECK-SCN: Name: .file -// CHECK-SCN: Section: (65534) +// CHECK-SCN: Section: IMAGE_SYM_DEBUG (-2) // CHECK-SCN: StorageClass: File // CHECK-SCN: AuxFileRecord { // CHECK-SCN: FileName: null-padded.asm @@ -29,7 +29,7 @@ // CHECK-SCN: } // CHECK-SCN: Symbol { // CHECK-SCN: Name: .file -// CHECK-SCN: Section: (65534) +// CHECK-SCN: Section: IMAGE_SYM_DEBUG (-2) // CHECK-SCN: StorageClass: File // CHECK-SCN: AuxFileRecord { // CHECK-SCN: FileName: eighteen-chars.asm @@ -37,7 +37,7 @@ // CHECK-SCN: } // CHECK-SCN: Symbol { // CHECK-SCN: Name: .file -// CHECK-SCN: Section: (65534) +// CHECK-SCN: Section: IMAGE_SYM_DEBUG (-2) // CHECK-SCN: StorageClass: File // CHECK-SCN: AuxFileRecord { // CHECK-SCN: FileName: multiple-auxiliary-entries.asm diff --git a/test/MC/ARM/coproc-diag.s b/test/MC/ARM/coproc-diag.s new file mode 100644 index 0000000..c96f2db --- /dev/null +++ b/test/MC/ARM/coproc-diag.s @@ -0,0 +1,10 @@ +# Special test to make sure we don't error on VFP co-proc access +@ RUN: llvm-mc -triple=armv5 < %s | FileCheck %s +@ RUN: llvm-mc -triple=armv6 < %s | FileCheck %s + + @ p10 and p11 are reserved for NEON, but accessible on v5/v6 + ldc p10, cr0, [r0], {0x20} + ldc2 p11, cr0, [r0], {0x21} + ldcl p11, cr0, [r0], {0x20} + +@ CHECK-NOT: error: invalid operand for instruction diff --git a/test/MC/ARM/cps.s b/test/MC/ARM/cps.s new file mode 100644 index 0000000..a848b22 --- /dev/null +++ b/test/MC/ARM/cps.s @@ -0,0 +1,17 @@ +@ RUN: llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF + + cpsie f + cpsie i, #3 + cps #0 + +@ CHECK: cpsie f @ encoding: [0x61,0xb6] +@ CHECK: cpsie i, #3 @ encoding: [0xaf,0xf3,0x43,0x85] +@ CHECK: cps #0 @ encoding: [0xaf,0xf3,0x00,0x81] + +@ UNDEF-DAG: cpsie f @ encoding: [0x61,0xb6] +@ UNDEF-DAG: error: instruction requires: +@ UNDEF-DAG: error: instruction 'cps' requires effect for M-class diff --git a/test/MC/ARM/d16.s b/test/MC/ARM/d16.s new file mode 100644 index 0000000..aa549a3 --- /dev/null +++ b/test/MC/ARM/d16.s @@ -0,0 +1,24 @@ +@ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+vfp4,-d16 2>&1 | FileCheck %s --check-prefix=D32 +@ RUN: not llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+vfp4,+d16 2>&1 | FileCheck %s --check-prefix=D16 + +@ D32-NOT: error: + +@ D16: invalid operand for instruction +@ D16-NEXT: vadd.f64 d1, d2, d16 +vadd.f64 d1, d2, d16 + +@ D16: invalid operand for instruction +@ D16-NEXT: vadd.f64 d1, d17, d6 +vadd.f64 d1, d17, d6 + +@ D16: invalid operand for instruction +@ D16-NEXT: vadd.f64 d19, d7, d6 +vadd.f64 d19, d7, d6 + +@ D16: invalid operand for instruction +@ D16-NEXT: vcvt.f64.f32 d22, s4 +vcvt.f64.f32 d22, s4 + +@ D16: invalid operand for instruction +@ D16-NEXT: vcvt.f32.f64 s26, d30 +vcvt.f32.f64 s26, d30 diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s index 88c5fb5..6b9574b 100644 --- a/test/MC/ARM/diagnostics.s +++ b/test/MC/ARM/diagnostics.s @@ -491,3 +491,133 @@ foo2: @ CHECK-ERRORS: ^ @ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16 @ CHECK-ERRORS: ^ + + str r0, [r0, #4]! + str r0, [r0, r1]! + str r0, [r0], #4 + str r0, [r0], r1 + strh r0, [r0, #2]! + strh r0, [r0, r1]! + strh r0, [r0], #2 + strh r0, [r0], r1 + strb r0, [r0, #1]! + strb r0, [r0, r1]! + strb r0, [r0], #1 + strb r0, [r0], r1 +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: str r0, [r0, #4]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: str r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: str r0, [r0], #4 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: str r0, [r0], r1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strh r0, [r0, #2]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strh r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strh r0, [r0], #2 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strh r0, [r0], r1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strb r0, [r0, #1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strb r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strb r0, [r0], #1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: source register and base register can't be identical +@ CHECK-ERRORS: strb r0, [r0], r1 +@ CHECK-ERRORS: ^ + + ldr r0, [r0, #4]! + ldr r0, [r0, r1]! + ldr r0, [r0], #4 + ldr r0, [r0], r1 + ldrh r0, [r0, #2]! + ldrh r0, [r0, r1]! + ldrh r0, [r0], #2 + ldrh r0, [r0], r1 + ldrsh r0, [r0, #2]! + ldrsh r0, [r0, r1]! + ldrsh r0, [r0], #2 + ldrsh r0, [r0], r1 + ldrb r0, [r0, #1]! + ldrb r0, [r0, r1]! + ldrb r0, [r0], #1 + ldrb r0, [r0], r1 + ldrsb r0, [r0, #1]! + ldrsb r0, [r0, r1]! + ldrsb r0, [r0], #1 + ldrsb r0, [r0], r1 +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldr r0, [r0, #4]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldr r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldr r0, [r0], #4 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldr r0, [r0], r1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrh r0, [r0, #2]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrh r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrh r0, [r0], #2 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrh r0, [r0], r1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsh r0, [r0, #2]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsh r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsh r0, [r0], #2 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsh r0, [r0], r1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrb r0, [r0, #1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrb r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrb r0, [r0], #1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrb r0, [r0], r1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsb r0, [r0, #1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsb r0, [r0, r1]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsb r0, [r0], #1 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: destination register and base register can't be identical +@ CHECK-ERRORS: ldrsb r0, [r0], r1 +@ CHECK-ERRORS: ^ diff --git a/test/MC/ARM/directive-arch_extension-crc.s b/test/MC/ARM/directive-arch_extension-crc.s index 9e4deda..1359b1f 100644 --- a/test/MC/ARM/directive-arch_extension-crc.s +++ b/test/MC/ARM/directive-arch_extension-crc.s @@ -37,21 +37,21 @@ crc: nocrc: crc32b r0, r1, r2 @ CHECK-V7: error: instruction requires: crc armv8 -@ CHECK-V8: error: instruction requires: crc arm-mode +@ CHECK-V8: error: instruction requires: crc crc32h r0, r1, r2 @ CHECK-V7: error: instruction requires: crc armv8 -@ CHECK-V8: error: instruction requires: crc arm-mode +@ CHECK-V8: error: instruction requires: crc crc32w r0, r1, r2 @ CHECK-V7: error: instruction requires: crc armv8 -@ CHECK-V8: error: instruction requires: crc arm-mode +@ CHECK-V8: error: instruction requires: crc crc32cb r0, r1, r2 @ CHECK-V7: error: instruction requires: crc armv8 -@ CHECK-V8: error: instruction requires: crc arm-mode +@ CHECK-V8: error: instruction requires: crc crc32ch r0, r1, r2 @ CHECK-V7: error: instruction requires: crc armv8 -@ CHECK-V8: error: instruction requires: crc arm-mode +@ CHECK-V8: error: instruction requires: crc crc32cw r0, r1, r2 @ CHECK-V7: error: instruction requires: crc armv8 -@ CHECK-V8: error: instruction requires: crc arm-mode +@ CHECK-V8: error: instruction requires: crc diff --git a/test/MC/ARM/directive-arch_extension-fp.s b/test/MC/ARM/directive-arch_extension-fp.s index 0327dd7..f2b4dc2 100644 --- a/test/MC/ARM/directive-arch_extension-fp.s +++ b/test/MC/ARM/directive-arch_extension-fp.s @@ -1,11 +1,11 @@ @ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V7 +@ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK @ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V8 +@ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK @ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V7 +@ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK @ RUN: not llvm-mc -triple thumbv8-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V8 +@ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK .syntax unified @@ -153,192 +153,131 @@ fp: .type nofp,%function nofp: vmrs r0, mvfr2 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselgt.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselge.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vseleq.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselvs.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vmaxnm.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vminnm.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselgt.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselge.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vseleq.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselvs.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vmaxnm.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vminnm.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtb.f64.f16 d0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtb.f16.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtt.f64.f16 d0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtt.f16.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f32 s0, s1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f64 d0, d1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f32 s0, s1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f64 d0, d1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f32 s0, s1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f64 d0, d1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 diff --git a/test/MC/ARM/directive-arch_extension-idiv.s b/test/MC/ARM/directive-arch_extension-idiv.s index c63bbfb..88614ea 100644 --- a/test/MC/ARM/directive-arch_extension-idiv.s +++ b/test/MC/ARM/directive-arch_extension-idiv.s @@ -43,11 +43,11 @@ noidiv: udiv r0, r1, r2 @ CHECK-ARMv6: error: instruction requires: divide in ARM @ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode -@ CHECK-ARMv7: error: instruction requires: divide in ARM arm-mode +@ CHECK-ARMv7: error: instruction requires: divide in ARM @ CHECK-THUMBv7: error: instruction requires: divide in THUMB sdiv r0, r1, r2 @ CHECK-ARMv6: error: instruction requires: divide in ARM @ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode -@ CHECK-ARMv7: error: instruction requires: divide in ARM arm-mode +@ CHECK-ARMv7: error: instruction requires: divide in ARM @ CHECK-THUMBv7: error: instruction requires: divide in THUMB diff --git a/test/MC/ARM/directive-arch_extension-mode-switch.s b/test/MC/ARM/directive-arch_extension-mode-switch.s new file mode 100644 index 0000000..7e4159f --- /dev/null +++ b/test/MC/ARM/directive-arch_extension-mode-switch.s @@ -0,0 +1,17 @@ +@ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null %s 2>&1 | FileCheck %s + +@ Ensure that a mode switch does not revert the architectural features that were +@ alternated explicitly. + + .syntax unified + + .arch_extension noidiv + + .arm + udiv r0, r0, r1 +@ CHECK: instruction requires: divide in ARM + + .thumb + udiv r0, r0, r1 +@ CHECK: instruction requires: divide in THUMB + diff --git a/test/MC/ARM/directive-arch_extension-simd.s b/test/MC/ARM/directive-arch_extension-simd.s index c9dbf21..14359c6 100644 --- a/test/MC/ARM/directive-arch_extension-simd.s +++ b/test/MC/ARM/directive-arch_extension-simd.s @@ -1,11 +1,11 @@ @ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V7 +@ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK @ RUN: not llvm-mc -triple armv8-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V8 +@ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK @ RUN: not llvm-mc -triple thumbv7-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V7 +@ RUN: | FileCheck %s -check-prefix CHECK-V7 -check-prefix CHECK @ RUN: not llvm-mc -triple thumbv8-eabi -filetype asm -o /dev/null 2>&1 %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-V8 +@ RUN: | FileCheck %s -check-prefix CHECK-V8 -check-prefix CHECK .syntax unified @@ -125,151 +125,103 @@ simd: .type nosimd,%function nosimd: vmaxnm.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vminnm.f32 s0, s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vmaxnm.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vminnm.f64 d0, d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.s32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.u32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.s32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.u32.f64 s0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f32 s0, s1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f64 d0, d1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f32 s0, s1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f64 d0, d1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f32 s0, s1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f64 d0, d1 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f32.f32 s0, s0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f64.f64 d0, d0 -@ CHECK-V7: error: instruction requires: FPARMv8 -@ CHECK-V8: error: instruction requires: double precision VFP FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 diff --git a/test/MC/ARM/directive-arch_extension-toggle.s b/test/MC/ARM/directive-arch_extension-toggle.s new file mode 100644 index 0000000..c3fb901 --- /dev/null +++ b/test/MC/ARM/directive-arch_extension-toggle.s @@ -0,0 +1,8 @@ +@ RUN: llvm-mc -triple armv7-eabi -mattr hwdiv -filetype asm -o /dev/null %s + + .syntax unified + .thumb + + udiv r0, r1, r2 + .arch_extension idiv + udiv r0, r1, r2 diff --git a/test/MC/ARM/directive-eabi_attribute-2.s b/test/MC/ARM/directive-eabi_attribute-2.s deleted file mode 100644 index 8f00ac8..0000000 --- a/test/MC/ARM/directive-eabi_attribute-2.s +++ /dev/null @@ -1,98 +0,0 @@ -@ RUN: llvm-mc -triple armv7-elf -filetype asm -o - %s | FileCheck %s - - .syntax unified - .thumb - - .eabi_attribute Tag_CPU_raw_name, "Cortex-A9" -@ CHECK: .eabi_attribute 4, "Cortex-A9" - .eabi_attribute Tag_CPU_name, "cortex-a9" -@ CHECK: .cpu cortex-a9 - .eabi_attribute Tag_CPU_arch, 10 -@ CHECK: .eabi_attribute 6, 10 - .eabi_attribute Tag_CPU_arch_profile, 'A' -@ CHECK: .eabi_attribute 7, 65 - .eabi_attribute Tag_ARM_ISA_use, 0 -@ CHECK: .eabi_attribute 8, 0 - .eabi_attribute Tag_THUMB_ISA_use, 2 -@ CHECK: .eabi_attribute 9, 2 - .eabi_attribute Tag_FP_arch, 3 -@ CHECK: .eabi_attribute 10, 3 - .eabi_attribute Tag_WMMX_arch, 0 -@ CHECK: .eabi_attribute 11, 0 - .eabi_attribute Tag_Advanced_SIMD_arch, 1 -@ CHECK: .eabi_attribute 12, 1 - .eabi_attribute Tag_PCS_config, 2 -@ CHECK: .eabi_attribute 13, 2 - .eabi_attribute Tag_ABI_PCS_R9_use, 0 -@ CHECK: .eabi_attribute 14, 0 - .eabi_attribute Tag_ABI_PCS_RW_data, 0 -@ CHECK: .eabi_attribute 15, 0 - .eabi_attribute Tag_ABI_PCS_RO_data, 0 -@ CHECK: .eabi_attribute 16, 0 - .eabi_attribute Tag_ABI_PCS_GOT_use, 0 -@ CHECK: .eabi_attribute 17, 0 - .eabi_attribute Tag_ABI_PCS_wchar_t, 4 -@ CHECK: .eabi_attribute 18, 4 - .eabi_attribute Tag_ABI_FP_rounding, 1 -@ CHECK: .eabi_attribute 19, 1 - .eabi_attribute Tag_ABI_FP_denormal, 2 -@ CHECK: .eabi_attribute 20, 2 - .eabi_attribute Tag_ABI_FP_exceptions, 1 -@ CHECK: .eabi_attribute 21, 1 - .eabi_attribute Tag_ABI_FP_user_exceptions, 1 -@ CHECK: .eabi_attribute 22, 1 - .eabi_attribute Tag_ABI_FP_number_model, 3 -@ CHECK: .eabi_attribute 23, 3 - .eabi_attribute Tag_ABI_align_needed, 1 -@ CHECK: .eabi_attribute 24, 1 - .eabi_attribute Tag_ABI_align_preserved, 2 -@ CHECK: .eabi_attribute 25, 2 - .eabi_attribute Tag_ABI_enum_size, 3 -@ CHECK: .eabi_attribute 26, 3 - .eabi_attribute Tag_ABI_HardFP_use, 0 -@ CHECK: .eabi_attribute 27, 0 - .eabi_attribute Tag_ABI_VFP_args, 1 -@ CHECK: .eabi_attribute 28, 1 - .eabi_attribute Tag_ABI_WMMX_args, 0 -@ CHECK: .eabi_attribute 29, 0 - .eabi_attribute Tag_ABI_FP_optimization_goals, 1 -@ CHECK: .eabi_attribute 31, 1 - .eabi_attribute Tag_compatibility, 1 -@ CHECK: .eabi_attribute 32, 1 - .eabi_attribute Tag_compatibility, 1, "aeabi" -@ CHECK: .eabi_attribute 32, 1, "aeabi" - .eabi_attribute Tag_CPU_unaligned_access, 0 -@ CHECK: .eabi_attribute 34, 0 - .eabi_attribute Tag_FP_HP_extension, 0 -@ CHECK: .eabi_attribute 36, 0 - .eabi_attribute Tag_ABI_FP_16bit_format, 0 -@ CHECK: .eabi_attribute 38, 0 - .eabi_attribute Tag_MPextension_use, 0 -@ CHECK: .eabi_attribute 42, 0 - .eabi_attribute Tag_DIV_use, 0 -@ CHECK: .eabi_attribute 44, 0 - .eabi_attribute Tag_nodefaults, 0 -@ CHECK: .eabi_attribute 64, 0 - .eabi_attribute Tag_also_compatible_with, "gnu" -@ CHECK: .eabi_attribute 65, "gnu" - .eabi_attribute Tag_T2EE_use, 0 -@ CHECK: .eabi_attribute 66, 0 - .eabi_attribute Tag_conformance, "2.09" -@ CHECK: .eabi_attribute 67, "2.09" - .eabi_attribute Tag_Virtualization_use, 0 -@ CHECK: .eabi_attribute 68, 0 - -@ ===--- Compatibility Checks ---=== - - .eabi_attribute Tag_ABI_align8_needed, 1 -@ CHECK: .eabi_attribute 24, 1 - .eabi_attribute Tag_ABI_align8_preserved, 2 -@ CHECK: .eabi_attribute 25, 2 - -@ ===--- GNU AS Compatibility Checks ---=== - - .eabi_attribute 2 * 2 + 1, "cortex-a9" -@ CHECK: .cpu cortex-a9 - .eabi_attribute 2 * 2 + 2, 5 * 2 -@ CHECK: .eabi_attribute 6, 10 - diff --git a/test/MC/ARM/directive-eabi_attribute.s b/test/MC/ARM/directive-eabi_attribute.s index c060b80..e2f1f9b 100644 --- a/test/MC/ARM/directive-eabi_attribute.s +++ b/test/MC/ARM/directive-eabi_attribute.s @@ -1,56 +1,247 @@ +@ RUN: llvm-mc -triple armv7-elf -filetype asm -o - %s | FileCheck %s @ RUN: llvm-mc < %s -triple armv7-unknown-linux-gnueabi -filetype=obj -o - \ -@ RUN: | llvm-readobj -s -sd | FileCheck %s - -@ CHECK: Name: .ARM.attribute -@ CHECK: SectionData ( - -@ <format-version> -@ CHECK: 41 - -@ <section-length> -@ CHECK: 250000 00 - -@ <vendor-name> "aeabi\0" -@ CHECK: 616561 626900 - -@ <file-tag> -@ CHECK: 01 - -@ <size> -@ CHECK: 1B000000 - -@ <attribute>* - - .eabi_attribute 6, 10 -@ CHECK: 060A - - .eabi_attribute 7, 65 -@ CHECK: 0741 - - .eabi_attribute 8, 1 -@ CHECK: 0801 - - .eabi_attribute 9, 2 -@ CHECK: 0902 - - .eabi_attribute 10, 3 -@ CHECK: 0A03 - - .eabi_attribute 12, 1 -@ CHECK: 0C01 - - .eabi_attribute 20, 1 -@ CHECK: 1401 - - .eabi_attribute 21, 1 -@ CHECK: 1501 - - .eabi_attribute 23, 3 -@ CHECK: 1703 - - .eabi_attribute 24, 1 -@ CHECK: 1801 - - .eabi_attribute 25, 1 -@ CHECK: 1901 -@ CHECK: ) +@ RUN: | llvm-readobj -arm-attributes | FileCheck %s --check-prefix=CHECK-OBJ + + .syntax unified + .thumb + + .eabi_attribute Tag_CPU_raw_name, "Cortex-A9" +@ CHECK: .eabi_attribute 4, "Cortex-A9" +@ CHECK-OBJ: Tag: 4 +@ CHECK-OBJ-NEXT: TagName: CPU_raw_name +@ CHECK-OBJ-NEXT: Value: CORTEX-A9 + .eabi_attribute Tag_CPU_name, "cortex-a9" +@ CHECK: .cpu cortex-a9 +@ CHECK-OBJ: Tag: 5 +@ CHECK-OBJ-NEXT: TagName: CPU_name +@ CHECK-OBJ-NEXT: Value: CORTEX-A9 + .eabi_attribute Tag_CPU_arch, 10 +@ CHECK: .eabi_attribute 6, 10 +@ CHECK-OBJ: Tag: 6 +@ CHECK-OBJ-NEXT: Value: 10 +@ CHECK-OBJ-NEXT: TagName: CPU_arch +@ CHECK-OBJ-NEXT: Description: ARM v7 + .eabi_attribute Tag_CPU_arch_profile, 'A' +@ CHECK: .eabi_attribute 7, 65 +@ CHECK-OBJ: Tag: 7 +@ CHECK-OBJ-NEXT: Value: 65 +@ CHECK-OBJ-NEXT: TagName: CPU_arch_profile +@ CHECK-OBJ-NEXT: Description: Application + .eabi_attribute Tag_ARM_ISA_use, 0 +@ CHECK: .eabi_attribute 8, 0 +@ CHECK-OBJ: Tag: 8 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ARM_ISA_use +@ CHECK-OBJ-NEXT: Description: Not Permitted + .eabi_attribute Tag_THUMB_ISA_use, 2 +@ CHECK: .eabi_attribute 9, 2 +@ CHECK-OBJ: Tag: 9 +@ CHECK-OBJ-NEXT: Value: 2 +@ CHECK-OBJ-NEXT: TagName: THUMB_ISA_use +@ CHECK-OBJ-NEXT: Description: Thumb-2 + .eabi_attribute Tag_FP_arch, 3 +@ CHECK: .eabi_attribute 10, 3 +@ CHECK-OBJ: Tag: 10 +@ CHECK-OBJ-NEXT: Value: 3 +@ CHECK-OBJ-NEXT: TagName: FP_arch +@ CHECK-OBJ-NEXT: Description: VFPv3 + .eabi_attribute Tag_WMMX_arch, 0 +@ CHECK: .eabi_attribute 11, 0 +@ CHECK-OBJ: Tag: 11 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: WMMX_arch +@ CHECK-OBJ-NEXT: Description: Not Permitted + .eabi_attribute Tag_Advanced_SIMD_arch, 1 +@ CHECK: .eabi_attribute 12, 1 +@ CHECK-OBJ: Tag: 12 +@ CHECK-OBJ-NEXT: Value: 1 +@ CHECK-OBJ-NEXT: TagName: Advanced_SIMD_arch +@ CHECK-OBJ-NEXT: Description: NEONv1 + .eabi_attribute Tag_PCS_config, 2 +@ CHECK: .eabi_attribute 13, 2 +@ CHECK-OBJ: Tag: 13 +@ CHECK-OBJ-NEXT: Value: 2 +@ CHECK-OBJ-NEXT: TagName: PCS_config +@ CHECK-OBJ-NEXT: Description: Linux Application + .eabi_attribute Tag_ABI_PCS_R9_use, 0 +@ CHECK: .eabi_attribute 14, 0 +@ CHECK-OBJ: Tag: 14 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ABI_PCS_R9_use +@ CHECK-OBJ-NEXT: Description: v6 + .eabi_attribute Tag_ABI_PCS_RW_data, 0 +@ CHECK: .eabi_attribute 15, 0 +@ CHECK-OBJ: Tag: 15 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ABI_PCS_RW_data +@ CHECK-OBJ-NEXT: Description: Absolute + .eabi_attribute Tag_ABI_PCS_RO_data, 0 +@ CHECK: .eabi_attribute 16, 0 +@ CHECK-OBJ: Tag: 16 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ABI_PCS_RO_data +@ CHECK-OBJ-NEXT: Description: Absolute + .eabi_attribute Tag_ABI_PCS_GOT_use, 0 +@ CHECK: .eabi_attribute 17, 0 +@ CHECK-OBJ: Tag: 17 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ABI_PCS_GOT_use +@ CHECK-OBJ-NEXT: Description: Not Permitted + .eabi_attribute Tag_ABI_PCS_wchar_t, 4 +@ CHECK: .eabi_attribute 18, 4 +@ CHECK-OBJ: Tag: 18 +@ CHECK-OBJ-NEXT: Value: 4 +@ CHECK-OBJ-NEXT: TagName: ABI_PCS_wchar_t +@ CHECK-OBJ-NEXT: Description: 4-byte + .eabi_attribute Tag_ABI_FP_rounding, 1 +@ CHECK: .eabi_attribute 19, 1 +@ CHECK-OBJ: Tag: 19 +@ CHECK-OBJ-NEXT: Value: 1 +@ CHECK-OBJ-NEXT: TagName: ABI_FP_rounding +@ CHECK-OBJ-NEXT: Description: Runtime + .eabi_attribute Tag_ABI_FP_denormal, 2 +@ CHECK: .eabi_attribute 20, 2 +@ CHECK-OBJ: Tag: 20 +@ CHECK-OBJ-NEXT: Value: 2 +@ CHECK-OBJ-NEXT: TagName: ABI_FP_denormal +@ CHECK-OBJ-NEXT: Description: Sign Only + .eabi_attribute Tag_ABI_FP_exceptions, 1 +@ CHECK: .eabi_attribute 21, 1 +@ CHECK-OBJ: Tag: 21 +@ CHECK-OBJ-NEXT: Value: 1 +@ CHECK-OBJ-NEXT: TagName: ABI_FP_exceptions +@ CHECK-OBJ-NEXT: Description: IEEE-754 + .eabi_attribute Tag_ABI_FP_user_exceptions, 1 +@ CHECK: .eabi_attribute 22, 1 +@ CHECK-OBJ: Tag: 22 +@ CHECK-OBJ-NEXT: Value: 1 +@ CHECK-OBJ-NEXT: TagName: ABI_FP_user_exceptions +@ CHECK-OBJ-NEXT: Description: IEEE-754 + .eabi_attribute Tag_ABI_FP_number_model, 3 +@ CHECK: .eabi_attribute 23, 3 +@ CHECK-OBJ: Tag: 23 +@ CHECK-OBJ-NEXT: Value: 3 +@ CHECK-OBJ-NEXT: TagName: ABI_FP_number_model +@ CHECK-OBJ-NEXT: Description: IEEE-754 + .eabi_attribute Tag_ABI_align_needed, 1 +@ CHECK: .eabi_attribute 24, 1 +@ CHECK-OBJ: Tag: 24 +@ CHECK-OBJ-NEXT: Value: 1 +@ CHECK-OBJ-NEXT: TagName: ABI_align_needed +@ CHECK-OBJ-NEXT: Description: 8-byte alignment + .eabi_attribute Tag_ABI_align_preserved, 2 +@ CHECK: .eabi_attribute 25, 2 +@ CHECK-OBJ: Tag: 25 +@ CHECK-OBJ-NEXT: Value: 2 +@ CHECK-OBJ-NEXT: TagName: ABI_align_preserved +@ CHECK-OBJ-NEXT: Description: 8-byte data and code alignment + .eabi_attribute Tag_ABI_enum_size, 3 +@ CHECK: .eabi_attribute 26, 3 +@ CHECK-OBJ: Tag: 26 +@ CHECK-OBJ-NEXT: Value: 3 +@ CHECK-OBJ-NEXT: TagName: ABI_enum_size +@ CHECK-OBJ-NEXT: Description: External Int32 + .eabi_attribute Tag_ABI_HardFP_use, 0 +@ CHECK: .eabi_attribute 27, 0 +@ CHECK-OBJ: Tag: 27 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ABI_HardFP_use +@ CHECK-OBJ-NEXT: Description: Tag_FP_arch + .eabi_attribute Tag_ABI_VFP_args, 1 +@ CHECK: .eabi_attribute 28, 1 +@ CHECK-OBJ: Tag: 28 +@ CHECK-OBJ-NEXT: Value: 1 +@ CHECK-OBJ-NEXT: TagName: ABI_VFP_args +@ CHECK-OBJ-NEXT: Description: AAPCS VFP + .eabi_attribute Tag_ABI_WMMX_args, 0 +@ CHECK: .eabi_attribute 29, 0 +@ CHECK-OBJ: Tag: 29 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ABI_WMMX_args +@ CHECK-OBJ-NEXT: Description: AAPCS + .eabi_attribute Tag_ABI_FP_optimization_goals, 1 +@ CHECK: .eabi_attribute 31, 1 +@ CHECK-OBJ: Tag: 31 +@ CHECK-OBJ-NEXT: Value: 1 +@ CHECK-OBJ-NEXT: TagName: ABI_FP_optimization_goals +@ CHECK-OBJ-NEXT: Description: Speed + .eabi_attribute Tag_compatibility, 1 +@ CHECK: .eabi_attribute 32, 1 + .eabi_attribute Tag_compatibility, 1, "aeabi" +@ CHECK: .eabi_attribute 32, 1, "aeabi" +@ CHECK-OBJ: Tag: 32 +@ CHECK-OBJ-NEXT: Value: 1, AEABI +@ CHECK-OBJ-NEXT: TagName: compatibility +@ CHECK-OBJ-NEXT: Description: AEABI Conformant + .eabi_attribute Tag_CPU_unaligned_access, 0 +@ CHECK: .eabi_attribute 34, 0 +@ CHECK-OBJ: Tag: 34 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: CPU_unaligned_access +@ CHECK-OBJ-NEXT: Description: Not Permitted + .eabi_attribute Tag_FP_HP_extension, 0 +@ CHECK: .eabi_attribute 36, 0 +@ CHECK-OBJ: Tag: 36 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: FP_HP_extension +@ CHECK-OBJ-NEXT: Description: If Available + .eabi_attribute Tag_ABI_FP_16bit_format, 0 +@ CHECK: .eabi_attribute 38, 0 +@ CHECK-OBJ: Tag: 38 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: ABI_FP_16bit_format +@ CHECK-OBJ-NEXT: Description: Not Permitte + .eabi_attribute Tag_MPextension_use, 0 +@ CHECK: .eabi_attribute 42, 0 +@ CHECK-OBJ: Tag: 42 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: MPextension_use +@ CHECK-OBJ-NEXT: Description: Not Permitted + .eabi_attribute Tag_DIV_use, 0 +@ CHECK: .eabi_attribute 44, 0 +@ CHECK-OBJ: Tag: 44 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: DIV_use +@ CHECK-OBJ-NEXT: Description: If Available + .eabi_attribute Tag_nodefaults, 0 +@ CHECK: .eabi_attribute 64, 0 +@ CHECK-OBJ: Tag: 64 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: nodefaults +@ CHECK-OBJ-NEXT: Description: Unspecified Tags UNDEFINED + .eabi_attribute Tag_also_compatible_with, "gnu" +@ CHECK: .eabi_attribute 65, "gnu" +@ CHECK-OBJ: Tag: 65 +@ CHECK-OBJ-NEXT: TagName: also_compatible_with +@ CHECK-OBJ-NEXT: Value: GNU + .eabi_attribute Tag_T2EE_use, 0 +@ CHECK: .eabi_attribute 66, 0 +@ CHECK-OBJ: Tag: 66 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: T2EE_use +@ CHECK-OBJ-NEXT: Description: Not Permitted + .eabi_attribute Tag_conformance, "2.09" +@ CHECK: .eabi_attribute 67, "2.09" +@ CHECK-OBJ: Tag: 67 +@ CHECK-OBJ-NEXT: TagName: conformance +@ CHECK-OBJ-NEXT: Value: 2.09 + .eabi_attribute Tag_Virtualization_use, 0 +@ CHECK: .eabi_attribute 68, 0 +@ CHECK-OBJ: Tag: 68 +@ CHECK-OBJ-NEXT: Value: 0 +@ CHECK-OBJ-NEXT: TagName: Virtualization_use +@ CHECK-OBJ-NEXT: Description: Not Permitted + +@ ===--- Compatibility Checks ---=== + + .eabi_attribute Tag_ABI_align8_needed, 1 +@ CHECK: .eabi_attribute 24, 1 + .eabi_attribute Tag_ABI_align8_preserved, 2 +@ CHECK: .eabi_attribute 25, 2 + +@ ===--- GNU AS Compatibility Checks ---=== + + .eabi_attribute 2 * 2 + 1, "cortex-a9" +@ CHECK: .cpu cortex-a9 + .eabi_attribute 2 * 2 + 2, 5 * 2 +@ CHECK: .eabi_attribute 6, 10 diff --git a/test/MC/ARM/directive-fpu-instrs.s b/test/MC/ARM/directive-fpu-instrs.s new file mode 100644 index 0000000..ec97a77 --- /dev/null +++ b/test/MC/ARM/directive-fpu-instrs.s @@ -0,0 +1,16 @@ +// RUN: llvm-mc -triple armv7-unknown-linux-gnueabi -mattr=+vfp3,-neon %s + +.fpu neon +VAND d3, d5, d5 +vldr d21, [r7, #296] + +@ .thumb should not disable the prior .fpu neon +.thumb + +vmov q4, q11 @ v4si +str r6, [r7, #264] +mov r6, r5 +vldr d21, [r7, #296] +add r9, r7, #216 + +fstmfdd sp!, {d8, d9, d10, d11, d12, d13, d14, d15} diff --git a/test/MC/ARM/directive-thumb_func.s b/test/MC/ARM/directive-thumb_func.s new file mode 100644 index 0000000..f82e0d1 --- /dev/null +++ b/test/MC/ARM/directive-thumb_func.s @@ -0,0 +1,22 @@ +@ RUN: not llvm-mc -triple armv7-eabi -filetype asm -o /dev/null %s 2>&1 \ +@ RUN: | FileCheck %s -check-prefix CHECK-EABI + +@ NOTE: this test ensures that both forms are accepted for MachO +@ RUN: llvm-mc -triple armv7-darwin -filetype asm -o /dev/null %s + + .syntax unified + + .thumb_func +no_suffix: + bx lr + + .thumb_func suffix +suffix: + bx lr + +// CHECK-EABI: error: unexpected token in directive +// CHECK-EABI: .thumb_func suffix +// CHECK-EABI: ^ + +// CHECK-EABI-NOT: error: invalid instruction + diff --git a/test/MC/ARM/directive-unsupported.s b/test/MC/ARM/directive-unsupported.s new file mode 100644 index 0000000..0b1f9ba --- /dev/null +++ b/test/MC/ARM/directive-unsupported.s @@ -0,0 +1,68 @@ +@ RUN: not llvm-mc -triple thumbv7-windows -filetype asm -o /dev/null %s 2>&1 \ +@ RUN: | FileCheck %s + +@ RUN: not llvm-mc -triple armv7-darwin -filetype asm -o /dev/null %s 2>&1 \ +@ RUN: | FileCheck %s + + .syntax unified + + .arch armv7 + +// CHECK: error: unknown directive +// CHECK: .arch armv7 +// CHECK: ^ + + .cpu cortex-a7 + +// CHECK: error: unknown directive +// CHECK: .cpu cortex-a7 +// CHECK: ^ + + .fpu neon + +// CHECK: error: unknown directive +// CHECK: .fpu neon +// CHECK: ^ + + .eabi_attribute 0, 0 + +// CHECK: error: unknown directive +// CHECK: .eabi_attribute 0, 0 +// CHECK: ^ + + .inst 0xdefe + +// CHECK: error: unknown directive +// CHECK: .inst 0xdefe +// CHECK: ^ + + .inst.n 0xdefe + +// CHECK: error: unknown directive +// CHECK: .inst.n 0xdefe +// CHECK: ^ + + .inst.w 0xdefe + +// CHECK: error: unknown directive +// CHECK: .inst.w 0xdefe +// CHECK: ^ + + .object_arch armv7 + +// CHECK: error: unknown directive +// CHECK: .object_arch armv7 +// CHECK: ^ + + .tlsdescseq undefined + +// CHECK: error: unknown directive +// CHECK: .tlsdescseq undefined +// CHECK: ^ + + .fnstart + +// CHECK: error: unknown directive +// CHECK: .fnstart +// CHECK: ^ + diff --git a/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s b/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s new file mode 100644 index 0000000..5bf8fbd --- /dev/null +++ b/test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s @@ -0,0 +1,66 @@ +// RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp -dwarf-version 2 2>&1 | FileCheck -check-prefix MESSAGES %s +// RUN: llvm-dwarfdump %t | FileCheck -check-prefix DWARF %s +// RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s + + .section .text, "ax" +a: + mov r0, r0 + + .section foo, "ax" +b: + mov r1, r1 + +// MESSAGES: warning: DWARF2 only supports one section per compilation unit + +// DWARF: .debug_abbrev contents: +// DWARF: Abbrev table for offset: 0x00000000 +// DWARF: [1] DW_TAG_compile_unit DW_CHILDREN_yes +// DWARF: DW_AT_stmt_list DW_FORM_data4 +// DWARF: DW_AT_low_pc DW_FORM_addr +// DWARF: DW_AT_high_pc DW_FORM_addr +// DWARF: DW_AT_name DW_FORM_string +// DWARF: DW_AT_comp_dir DW_FORM_string +// DWARF: DW_AT_producer DW_FORM_string +// DWARF: DW_AT_language DW_FORM_data2 + +// DWARF: .debug_info contents: +// DWARF: 0x{{[0-9a-f]+}}: DW_TAG_compile_unit [1] +// CHECK-NOT-DWARF: DW_TAG_ +// DWARF: DW_AT_low_pc [DW_FORM_addr] (0x0000000000000000) +// DWARF: DW_AT_high_pc [DW_FORM_addr] (0x0000000000000004) + +// DWARF: 0x{{[0-9a-f]+}}: DW_TAG_label [2] * +// DWARF-NEXT: DW_AT_name [DW_FORM_string] ("a") + + +// DWARF: .debug_aranges contents: +// DWARF-NEXT: Address Range Header: length = 0x00000024, version = 0x0002, cu_offset = 0x00000000, addr_size = 0x04, seg_size = 0x00 +// DWARF-NEXT: [0x00000000 - 0x00000004) +// DWARF-NEXT: [0x00000000 - 0x00000004) + +// DWARF: .debug_line contents: +// DWARF: 0x0000000000000000 7 0 1 0 0 is_stmt +// DWARF-NEXT: 0x0000000000000004 7 0 1 0 0 is_stmt end_sequence +// DWARF: 0x0000000000000000 11 0 1 0 0 is_stmt +// DWARF-NEXT: 0x0000000000000004 11 0 1 0 0 is_stmt end_sequence + + +// DWARF: .debug_ranges contents: +// DWARF-NOT: {{0-9a-f}} +// DWARF: .debug_pubnames contents: + + +// RELOC: RELOCATION RECORDS FOR [.rel.debug_info]: +// RELOC-NEXT: 00000006 R_ARM_ABS32 .debug_abbrev +// RELOC-NEXT: 0000000c R_ARM_ABS32 .debug_line +// RELOC-NEXT: R_ARM_ABS32 .text +// RELOC-NEXT: R_ARM_ABS32 .text +// RELOC-NEXT: R_ARM_ABS32 .text +// RELOC-NEXT: R_ARM_ABS32 foo + +// RELOC-NOT: RELOCATION RECORDS FOR [.rel.debug_ranges]: + +// RELOC: RELOCATION RECORDS FOR [.rel.debug_aranges]: +// RELOC-NEXT: 00000006 R_ARM_ABS32 .debug_info +// RELOC-NEXT: 00000010 R_ARM_ABS32 .text +// RELOC-NEXT: 00000018 R_ARM_ABS32 foo diff --git a/test/MC/ARM/dwarf-asm-multiple-sections.s b/test/MC/ARM/dwarf-asm-multiple-sections.s index ed1b89e..0eb8bab 100644 --- a/test/MC/ARM/dwarf-asm-multiple-sections.s +++ b/test/MC/ARM/dwarf-asm-multiple-sections.s @@ -1,7 +1,7 @@ // RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp // RUN: llvm-dwarfdump %t | FileCheck -check-prefix DWARF %s // RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s -// RUN: not llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 2 2>&1 | FileCheck -check-prefix VERSION %s +// RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 2 2>&1 | FileCheck -check-prefix VERSION %s // RUN: not llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 1 2>&1 | FileCheck -check-prefix DWARF1 %s // RUN: not llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 5 2>&1 | FileCheck -check-prefix DWARF5 %s .section .text, "ax" @@ -25,7 +25,7 @@ b: // DWARF: .debug_info contents: // DWARF: 0x{{[0-9a-f]+}}: DW_TAG_compile_unit [1] // CHECK-NOT-DWARF: DW_TAG_ -// DWARF: DW_AT_ranges [DW_FORM_data4] (0x00000000) +// DWARF: DW_AT_ranges [DW_FORM_data4] (0x00000000 // DWARF: 0x{{[0-9a-f]+}}: DW_TAG_label [2] * // DWARF-NEXT: DW_AT_name [DW_FORM_string] ("a") @@ -73,7 +73,7 @@ b: // RELOC-NEXT: 00000018 R_ARM_ABS32 foo -// VERSION: {{.*}} error: DWARF2 only supports one section per compilation unit +// VERSION: {{.*}} warning: DWARF2 only supports one section per compilation unit // DWARF1: Dwarf version 1 is not supported. // DWARF5: Dwarf version 5 is not supported. diff --git a/test/MC/ARM/ldr-pseudo-darwin.s b/test/MC/ARM/ldr-pseudo-darwin.s index a77f6d5..f04f533 100644 --- a/test/MC/ARM/ldr-pseudo-darwin.s +++ b/test/MC/ARM/ldr-pseudo-darwin.s @@ -156,35 +156,38 @@ f15: @ Constant Pools @ @ CHECK: .section __TEXT,b,regular,pure_instructions -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp0: @ CHECK: .long 65537 @ CHECK: .end_data_region @ CHECK: .section __TEXT,c,regular,pure_instructions -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp1: @ CHECK: .long 65538 +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp2: @ CHECK: .long 65539 @ CHECK: .end_data_region @ CHECK: .section __TEXT,d,regular,pure_instructions -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp3: @ CHECK: .long 65540 +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp4: @ CHECK: .long 65540 @ CHECK: .end_data_region @ CHECK: .section __TEXT,e,regular,pure_instructions -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp5: @ CHECK: .long 65542 +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp6: @ CHECK: .long 65543 @ CHECK: .end_data_region @@ -193,49 +196,52 @@ f15: @ CHECK-NOT: .section __TEXT,f,regular,pure_instructions @ CHECK: .section __TEXT,g,regular,pure_instructions -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp7: @ CHECK: .long foo @ CHECK: .end_data_region @ CHECK: .section __TEXT,h,regular,pure_instructions -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp8: @ CHECK: .long f5 @ CHECK: .end_data_region @ CHECK: .section __TEXT,i,regular,pure_instructions -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp9: @ CHECK: .long f12 @ CHECK: .end_data_region @ CHECK: .section __TEXT,j,regular,pure_instructions -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp10: @ CHECK: .long 257 +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp11: @ CHECK: .long bar @ CHECK: .end_data_region @ CHECK: .section __TEXT,k,regular,pure_instructions -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp12: @ CHECK: .long 65544 +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp13: @ CHECK: .long baz @ CHECK: .end_data_region @ CHECK: .section __TEXT,l,regular,pure_instructions -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp14: @ CHECK: .long 65545 +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp15: @ CHECK: .long bar+4 @ CHECK: .end_data_region diff --git a/test/MC/ARM/ltorg-darwin.s b/test/MC/ARM/ltorg-darwin.s index de6b7e9..3402f40 100644 --- a/test/MC/ARM/ltorg-darwin.s +++ b/test/MC/ARM/ltorg-darwin.s @@ -19,8 +19,8 @@ f2: b f3 .ltorg @ constant pool -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp0: @ CHECK: .long 65537 @ CHECK: .end_data_region @@ -41,8 +41,8 @@ f4: b f5 .ltorg @ constant pool -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp1: @ CHECK: .long 65538 @ CHECK: .end_data_region @@ -57,8 +57,8 @@ f5: b f6 .ltorg @ constant pool -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp2: @ CHECK: .long 65539 @ CHECK: .end_data_region @@ -92,8 +92,8 @@ f9: b f10 .ltorg @ constant pool -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp3: @ CHECK: .long bar @ CHECK: .end_data_region @@ -114,8 +114,8 @@ f11: b f12 .ltorg @ constant pool -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp4: @ CHECK: .long 65540 @ CHECK: .end_data_region @@ -141,8 +141,8 @@ f13: @ should have a non-empty constant pool at end of this section @ CHECK: .section __TEXT,e,regular,pure_instructions @ constant pool -@ CHECK: .align 2 @ CHECK: .data_region +@ CHECK: .align 2 @ CHECK-LABEL: Ltmp5: @ CHECK: .long 65541 @ CHECK: .end_data_region diff --git a/test/MC/ARM/move-banked-regs.s b/test/MC/ARM/move-banked-regs.s new file mode 100644 index 0000000..3fac846 --- /dev/null +++ b/test/MC/ARM/move-banked-regs.s @@ -0,0 +1,220 @@ +@ RUN: llvm-mc -triple armv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-ARM +@ RUN: llvm-mc -triple thumbv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-THUMB + + mrs r2, r8_usr + mrs r3, r9_usr + mrs r5, r10_usr + mrs r7, r11_usr + mrs r11, r12_usr + mrs r1, sp_usr + mrs r2, lr_usr +@ CHECK-ARM: mrs r2, r8_usr @ encoding: [0x00,0x22,0x20,0xe1] +@ CHECK-ARM: mrs r3, r9_usr @ encoding: [0x00,0x32,0x21,0xe1] +@ CHECK-ARM: mrs r5, r10_usr @ encoding: [0x00,0x52,0x22,0xe1] +@ CHECK-ARM: mrs r7, r11_usr @ encoding: [0x00,0x72,0x23,0xe1] +@ CHECK-ARM: mrs r11, r12_usr @ encoding: [0x00,0xb2,0x24,0xe1] +@ CHECK-ARM: mrs r1, sp_usr @ encoding: [0x00,0x12,0x25,0xe1] +@ CHECK-ARM: mrs r2, lr_usr @ encoding: [0x00,0x22,0x26,0xe1] +@ CHECK-THUMB: mrs r2, r8_usr @ encoding: [0xe0,0xf3,0x20,0x82] +@ CHECK-THUMB: mrs r3, r9_usr @ encoding: [0xe1,0xf3,0x20,0x83] +@ CHECK-THUMB: mrs r5, r10_usr @ encoding: [0xe2,0xf3,0x20,0x85] +@ CHECK-THUMB: mrs r7, r11_usr @ encoding: [0xe3,0xf3,0x20,0x87] +@ CHECK-THUMB: mrs r11, r12_usr @ encoding: [0xe4,0xf3,0x20,0x8b] +@ CHECK-THUMB: mrs r1, sp_usr @ encoding: [0xe5,0xf3,0x20,0x81] +@ CHECK-THUMB: mrs r2, lr_usr @ encoding: [0xe6,0xf3,0x20,0x82] + + mrs r2, r8_fiq + mrs r3, r9_fiq + mrs r5, r10_fiq + mrs r7, r11_fiq + mrs r11, r12_fiq + mrs r1, sp_fiq + mrs r2, lr_fiq + mrs r3, spsr_fiq +@ CHECK-ARM: mrs r2, r8_fiq @ encoding: [0x00,0x22,0x28,0xe1] +@ CHECK-ARM: mrs r3, r9_fiq @ encoding: [0x00,0x32,0x29,0xe1] +@ CHECK-ARM: mrs r5, r10_fiq @ encoding: [0x00,0x52,0x2a,0xe1] +@ CHECK-ARM: mrs r7, r11_fiq @ encoding: [0x00,0x72,0x2b,0xe1] +@ CHECK-ARM: mrs r11, r12_fiq @ encoding: [0x00,0xb2,0x2c,0xe1] +@ CHECK-ARM: mrs r1, sp_fiq @ encoding: [0x00,0x12,0x2d,0xe1] +@ CHECK-ARM: mrs r2, lr_fiq @ encoding: [0x00,0x22,0x2e,0xe1] +@ CHECK-ARM: mrs r3, SPSR_fiq @ encoding: [0x00,0x32,0x6e,0xe1] +@ CHECK-THUMB: mrs r2, r8_fiq @ encoding: [0xe8,0xf3,0x20,0x82] +@ CHECK-THUMB: mrs r3, r9_fiq @ encoding: [0xe9,0xf3,0x20,0x83] +@ CHECK-THUMB: mrs r5, r10_fiq @ encoding: [0xea,0xf3,0x20,0x85] +@ CHECK-THUMB: mrs r7, r11_fiq @ encoding: [0xeb,0xf3,0x20,0x87] +@ CHECK-THUMB: mrs r11, r12_fiq @ encoding: [0xec,0xf3,0x20,0x8b] +@ CHECK-THUMB: mrs r1, sp_fiq @ encoding: [0xed,0xf3,0x20,0x81] +@ CHECK-THUMB: mrs r2, lr_fiq @ encoding: [0xee,0xf3,0x20,0x82] +@ CHECK-THUMB: mrs r3, SPSR_fiq @ encoding: [0xfe,0xf3,0x20,0x83] + + mrs r4, lr_irq + mrs r9, sp_irq + mrs r1, spsr_irq +@ CHECK-ARM: mrs r4, lr_irq @ encoding: [0x00,0x43,0x20,0xe1] +@ CHECK-ARM: mrs r9, sp_irq @ encoding: [0x00,0x93,0x21,0xe1] +@ CHECK-ARM: mrs r1, SPSR_irq @ encoding: [0x00,0x13,0x60,0xe1] +@ CHECK-THUMB: mrs r4, lr_irq @ encoding: [0xe0,0xf3,0x30,0x84] +@ CHECK-THUMB: mrs r9, sp_irq @ encoding: [0xe1,0xf3,0x30,0x89] +@ CHECK-THUMB: mrs r1, SPSR_irq @ encoding: [0xf0,0xf3,0x30,0x81] + + mrs r1, lr_svc + mrs r3, sp_svc + mrs r5, spsr_svc +@ CHECK-ARM: mrs r1, lr_svc @ encoding: [0x00,0x13,0x22,0xe1] +@ CHECK-ARM: mrs r3, sp_svc @ encoding: [0x00,0x33,0x23,0xe1] +@ CHECK-ARM: mrs r5, SPSR_svc @ encoding: [0x00,0x53,0x62,0xe1] +@ CHECK-THUMB: mrs r1, lr_svc @ encoding: [0xe2,0xf3,0x30,0x81] +@ CHECK-THUMB: mrs r3, sp_svc @ encoding: [0xe3,0xf3,0x30,0x83] +@ CHECK-THUMB: mrs r5, SPSR_svc @ encoding: [0xf2,0xf3,0x30,0x85] + + mrs r5, lr_abt + mrs r7, sp_abt + mrs r9, spsr_abt +@ CHECK-ARM: mrs r5, lr_abt @ encoding: [0x00,0x53,0x24,0xe1] +@ CHECK-ARM: mrs r7, sp_abt @ encoding: [0x00,0x73,0x25,0xe1] +@ CHECK-ARM: mrs r9, SPSR_abt @ encoding: [0x00,0x93,0x64,0xe1] +@ CHECK-THUMB: mrs r5, lr_abt @ encoding: [0xe4,0xf3,0x30,0x85] +@ CHECK-THUMB: mrs r7, sp_abt @ encoding: [0xe5,0xf3,0x30,0x87] +@ CHECK-THUMB: mrs r9, SPSR_abt @ encoding: [0xf4,0xf3,0x30,0x89] + + mrs r9, lr_und + mrs r11, sp_und + mrs r12, spsr_und +@ CHECK-ARM: mrs r9, lr_und @ encoding: [0x00,0x93,0x26,0xe1] +@ CHECK-ARM: mrs r11, sp_und @ encoding: [0x00,0xb3,0x27,0xe1] +@ CHECK-ARM: mrs r12, SPSR_und @ encoding: [0x00,0xc3,0x66,0xe1] +@ CHECK-THUMB: mrs r9, lr_und @ encoding: [0xe6,0xf3,0x30,0x89] +@ CHECK-THUMB: mrs r11, sp_und @ encoding: [0xe7,0xf3,0x30,0x8b] +@ CHECK-THUMB: mrs r12, SPSR_und @ encoding: [0xf6,0xf3,0x30,0x8c] + + + mrs r2, lr_mon + mrs r4, sp_mon + mrs r6, spsr_mon +@ CHECK-ARM: mrs r2, lr_mon @ encoding: [0x00,0x23,0x2c,0xe1] +@ CHECK-ARM: mrs r4, sp_mon @ encoding: [0x00,0x43,0x2d,0xe1] +@ CHECK-ARM: mrs r6, SPSR_mon @ encoding: [0x00,0x63,0x6c,0xe1] +@ CHECK-THUMB: mrs r2, lr_mon @ encoding: [0xec,0xf3,0x30,0x82] +@ CHECK-THUMB: mrs r4, sp_mon @ encoding: [0xed,0xf3,0x30,0x84] +@ CHECK-THUMB: mrs r6, SPSR_mon @ encoding: [0xfc,0xf3,0x30,0x86] + + + mrs r6, elr_hyp + mrs r8, sp_hyp + mrs r10, spsr_hyp +@ CHECK-ARM: mrs r6, elr_hyp @ encoding: [0x00,0x63,0x2e,0xe1] +@ CHECK-ARM: mrs r8, sp_hyp @ encoding: [0x00,0x83,0x2f,0xe1] +@ CHECK-ARM: mrs r10, SPSR_hyp @ encoding: [0x00,0xa3,0x6e,0xe1] +@ CHECK-THUMB: mrs r6, elr_hyp @ encoding: [0xee,0xf3,0x30,0x86] +@ CHECK-THUMB: mrs r8, sp_hyp @ encoding: [0xef,0xf3,0x30,0x88] +@ CHECK-THUMB: mrs r10, SPSR_hyp @ encoding: [0xfe,0xf3,0x30,0x8a] + + + msr r8_usr, r2 + msr r9_usr, r3 + msr r10_usr, r5 + msr r11_usr, r7 + msr r12_usr, r11 + msr sp_usr, r1 + msr lr_usr, r2 +@ CHECK-ARM: msr r8_usr, r2 @ encoding: [0x02,0xf2,0x20,0xe1] +@ CHECK-ARM: msr r9_usr, r3 @ encoding: [0x03,0xf2,0x21,0xe1] +@ CHECK-ARM: msr r10_usr, r5 @ encoding: [0x05,0xf2,0x22,0xe1] +@ CHECK-ARM: msr r11_usr, r7 @ encoding: [0x07,0xf2,0x23,0xe1] +@ CHECK-ARM: msr r12_usr, r11 @ encoding: [0x0b,0xf2,0x24,0xe1] +@ CHECK-ARM: msr sp_usr, r1 @ encoding: [0x01,0xf2,0x25,0xe1] +@ CHECK-ARM: msr lr_usr, r2 @ encoding: [0x02,0xf2,0x26,0xe1] +@ CHECK-THUMB: msr r8_usr, r2 @ encoding: [0x82,0xf3,0x20,0x80] +@ CHECK-THUMB: msr r9_usr, r3 @ encoding: [0x83,0xf3,0x20,0x81] +@ CHECK-THUMB: msr r10_usr, r5 @ encoding: [0x85,0xf3,0x20,0x82] +@ CHECK-THUMB: msr r11_usr, r7 @ encoding: [0x87,0xf3,0x20,0x83] +@ CHECK-THUMB: msr r12_usr, r11 @ encoding: [0x8b,0xf3,0x20,0x84] +@ CHECK-THUMB: msr sp_usr, r1 @ encoding: [0x81,0xf3,0x20,0x85] +@ CHECK-THUMB: msr lr_usr, r2 @ encoding: [0x82,0xf3,0x20,0x86] + + msr r8_fiq, r2 + msr r9_fiq, r3 + msr r10_fiq, r5 + msr r11_fiq, r7 + msr r12_fiq, r11 + msr sp_fiq, r1 + msr lr_fiq, r2 + msr spsr_fiq, r3 +@ CHECK-ARM: msr r8_fiq, r2 @ encoding: [0x02,0xf2,0x28,0xe1] +@ CHECK-ARM: msr r9_fiq, r3 @ encoding: [0x03,0xf2,0x29,0xe1] +@ CHECK-ARM: msr r10_fiq, r5 @ encoding: [0x05,0xf2,0x2a,0xe1] +@ CHECK-ARM: msr r11_fiq, r7 @ encoding: [0x07,0xf2,0x2b,0xe1] +@ CHECK-ARM: msr r12_fiq, r11 @ encoding: [0x0b,0xf2,0x2c,0xe1] +@ CHECK-ARM: msr sp_fiq, r1 @ encoding: [0x01,0xf2,0x2d,0xe1] +@ CHECK-ARM: msr lr_fiq, r2 @ encoding: [0x02,0xf2,0x2e,0xe1] +@ CHECK-ARM: msr SPSR_fiq, r3 @ encoding: [0x03,0xf2,0x6e,0xe1] +@ CHECK-THUMB: msr r8_fiq, r2 @ encoding: [0x82,0xf3,0x20,0x88] +@ CHECK-THUMB: msr r9_fiq, r3 @ encoding: [0x83,0xf3,0x20,0x89] +@ CHECK-THUMB: msr r10_fiq, r5 @ encoding: [0x85,0xf3,0x20,0x8a] +@ CHECK-THUMB: msr r11_fiq, r7 @ encoding: [0x87,0xf3,0x20,0x8b] +@ CHECK-THUMB: msr r12_fiq, r11 @ encoding: [0x8b,0xf3,0x20,0x8c] +@ CHECK-THUMB: msr sp_fiq, r1 @ encoding: [0x81,0xf3,0x20,0x8d] +@ CHECK-THUMB: msr lr_fiq, r2 @ encoding: [0x82,0xf3,0x20,0x8e] +@ CHECK-THUMB: msr SPSR_fiq, r3 @ encoding: [0x93,0xf3,0x20,0x8e] + + msr lr_irq, r4 + msr sp_irq, r9 + msr spsr_irq, r11 +@ CHECK-ARM: msr lr_irq, r4 @ encoding: [0x04,0xf3,0x20,0xe1] +@ CHECK-ARM: msr sp_irq, r9 @ encoding: [0x09,0xf3,0x21,0xe1] +@ CHECK-ARM: msr SPSR_irq, r11 @ encoding: [0x0b,0xf3,0x60,0xe1] +@ CHECK-THUMB: msr lr_irq, r4 @ encoding: [0x84,0xf3,0x30,0x80] +@ CHECK-THUMB: msr sp_irq, r9 @ encoding: [0x89,0xf3,0x30,0x81] +@ CHECK-THUMB: msr SPSR_irq, r11 @ encoding: [0x9b,0xf3,0x30,0x80] + + msr lr_svc, r1 + msr sp_svc, r3 + msr spsr_svc, r5 +@ CHECK-ARM: msr lr_svc, r1 @ encoding: [0x01,0xf3,0x22,0xe1] +@ CHECK-ARM: msr sp_svc, r3 @ encoding: [0x03,0xf3,0x23,0xe1] +@ CHECK-ARM: msr SPSR_svc, r5 @ encoding: [0x05,0xf3,0x62,0xe1] +@ CHECK-THUMB: msr lr_svc, r1 @ encoding: [0x81,0xf3,0x30,0x82] +@ CHECK-THUMB: msr sp_svc, r3 @ encoding: [0x83,0xf3,0x30,0x83] +@ CHECK-THUMB: msr SPSR_svc, r5 @ encoding: [0x95,0xf3,0x30,0x82] + + msr lr_abt, r5 + msr sp_abt, r7 + msr spsr_abt, r9 +@ CHECK-ARM: msr lr_abt, r5 @ encoding: [0x05,0xf3,0x24,0xe1] +@ CHECK-ARM: msr sp_abt, r7 @ encoding: [0x07,0xf3,0x25,0xe1] +@ CHECK-ARM: msr SPSR_abt, r9 @ encoding: [0x09,0xf3,0x64,0xe1] +@ CHECK-THUMB: msr lr_abt, r5 @ encoding: [0x85,0xf3,0x30,0x84] +@ CHECK-THUMB: msr sp_abt, r7 @ encoding: [0x87,0xf3,0x30,0x85] +@ CHECK-THUMB: msr SPSR_abt, r9 @ encoding: [0x99,0xf3,0x30,0x84] + + msr lr_und, r9 + msr sp_und, r11 + msr spsr_und, r12 +@ CHECK-ARM: msr lr_und, r9 @ encoding: [0x09,0xf3,0x26,0xe1] +@ CHECK-ARM: msr sp_und, r11 @ encoding: [0x0b,0xf3,0x27,0xe1] +@ CHECK-ARM: msr SPSR_und, r12 @ encoding: [0x0c,0xf3,0x66,0xe1] +@ CHECK-THUMB: msr lr_und, r9 @ encoding: [0x89,0xf3,0x30,0x86] +@ CHECK-THUMB: msr sp_und, r11 @ encoding: [0x8b,0xf3,0x30,0x87] +@ CHECK-THUMB: msr SPSR_und, r12 @ encoding: [0x9c,0xf3,0x30,0x86] + + + msr lr_mon, r2 + msr sp_mon, r4 + msr spsr_mon, r6 +@ CHECK-ARM: msr lr_mon, r2 @ encoding: [0x02,0xf3,0x2c,0xe1] +@ CHECK-ARM: msr sp_mon, r4 @ encoding: [0x04,0xf3,0x2d,0xe1] +@ CHECK-ARM: msr SPSR_mon, r6 @ encoding: [0x06,0xf3,0x6c,0xe1] +@ CHECK-THUMB: msr lr_mon, r2 @ encoding: [0x82,0xf3,0x30,0x8c] +@ CHECK-THUMB: msr sp_mon, r4 @ encoding: [0x84,0xf3,0x30,0x8d] +@ CHECK-THUMB: msr SPSR_mon, r6 @ encoding: [0x96,0xf3,0x30,0x8c] + + msr elr_hyp, r6 + msr sp_hyp, r8 + msr spsr_hyp, r10 +@ CHECK-ARM: msr elr_hyp, r6 @ encoding: [0x06,0xf3,0x2e,0xe1] +@ CHECK-ARM: msr sp_hyp, r8 @ encoding: [0x08,0xf3,0x2f,0xe1] +@ CHECK-ARM: msr SPSR_hyp, r10 @ encoding: [0x0a,0xf3,0x6e,0xe1] +@ CHECK-THUMB: msr elr_hyp, r6 @ encoding: [0x86,0xf3,0x30,0x8e] +@ CHECK-THUMB: msr sp_hyp, r8 @ encoding: [0x88,0xf3,0x30,0x8f] +@ CHECK-THUMB: msr SPSR_hyp, r10 @ encoding: [0x9a,0xf3,0x30,0x8e] diff --git a/test/MC/ARM/neon-bitwise-encoding.s b/test/MC/ARM/neon-bitwise-encoding.s index 8c72288..d142dba 100644 --- a/test/MC/ARM/neon-bitwise-encoding.s +++ b/test/MC/ARM/neon-bitwise-encoding.s @@ -29,18 +29,63 @@ vbic d16, d17, d16 vbic q8, q8, q9 + vbic q10, q11 + vbic d9, d1 + vbic.i16 d16, #0xFF00 + vbic.i16 q8, #0xFF00 + vbic.i16 d16, #0x00FF + vbic.i16 q8, #0x00FF vbic.i32 d16, #0xFF000000 - vbic.i32 q8, #0xFF000000 - vbic q10, q11 - vbic d9, d1 + vbic.i32 q8, #0xFF000000 + vbic.i32 d16, #0x00FF0000 + vbic.i32 q8, #0x00FF0000 + vbic.i32 d16, #0x0000FF00 + vbic.i32 q8, #0x0000FF00 + vbic.i32 d16, #0x000000FF + vbic.i32 q8, #0x000000FF @ CHECK: vbic d16, d17, d16 @ encoding: [0xb0,0x01,0x51,0xf2] @ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2] -@ CHECK: vbic.i32 d16, #0xff000000 @ encoding: [0x3f,0x07,0xc7,0xf3] -@ CHECK: vbic.i32 q8, #0xff000000 @ encoding: [0x7f,0x07,0xc7,0xf3] @ CHECK: vbic q10, q10, q11 @ encoding: [0xf6,0x41,0x54,0xf2] @ CHECK: vbic d9, d9, d1 @ encoding: [0x11,0x91,0x19,0xf2] - +@ CHECK: vbic.i16 d16, #0xff00 @ encoding: [0x3f,0x0b,0xc7,0xf3] +@ CHECK: vbic.i16 q8, #0xff00 @ encoding: [0x7f,0x0b,0xc7,0xf3] +@ CHECK: vbic.i16 d16, #0xff @ encoding: [0x3f,0x09,0xc7,0xf3] +@ CHECK: vbic.i16 q8, #0xff @ encoding: [0x7f,0x09,0xc7,0xf3] +@ CHECK: vbic.i32 d16, #0xff000000 @ encoding: [0x3f,0x07,0xc7,0xf3] +@ CHECK: vbic.i32 q8, #0xff000000 @ encoding: [0x7f,0x07,0xc7,0xf3] +@ CHECK: vbic.i32 d16, #0xff0000 @ encoding: [0x3f,0x05,0xc7,0xf3] +@ CHECK: vbic.i32 q8, #0xff0000 @ encoding: [0x7f,0x05,0xc7,0xf3] +@ CHECK: vbic.i32 d16, #0xff00 @ encoding: [0x3f,0x03,0xc7,0xf3] +@ CHECK: vbic.i32 q8, #0xff00 @ encoding: [0x7f,0x03,0xc7,0xf3] +@ CHECK: vbic.i32 d16, #0xff @ encoding: [0x3f,0x01,0xc7,0xf3] +@ CHECK: vbic.i32 q8, #0xff @ encoding: [0x7f,0x01,0xc7,0xf3] + + vand.i16 d10, #0xff03 + vand.i16 q10, #0xff03 + vand.i16 d10, #0x03ff + vand.i16 q10, #0x03ff + vand.i32 d10, #0x03ffffff + vand.i32 q10, #0x03ffffff + vand.i32 d10, #0xff03ffff + vand.i32 q10, #0xff03ffff + vand.i32 d10, #0xffff03ff + vand.i32 q10, #0xffff03ff + vand.i32 d10, #0xffffff03 + vand.i32 q10, #0xffffff03 + +@ CHECK: vbic.i16 d10, #0xfc @ encoding: [0x3c,0xa9,0x87,0xf3] +@ CHECK: vbic.i16 q10, #0xfc @ encoding: [0x7c,0x49,0xc7,0xf3] +@ CHECK: vbic.i16 d10, #0xfc00 @ encoding: [0x3c,0xab,0x87,0xf3] +@ CHECK: vbic.i16 q10, #0xfc00 @ encoding: [0x7c,0x4b,0xc7,0xf3] +@ CHECK: vbic.i32 d10, #0xfc000000 @ encoding: [0x3c,0xa7,0x87,0xf3] +@ CHECK: vbic.i32 q10, #0xfc000000 @ encoding: [0x7c,0x47,0xc7,0xf3] +@ CHECK: vbic.i32 d10, #0xfc0000 @ encoding: [0x3c,0xa5,0x87,0xf3] +@ CHECK: vbic.i32 q10, #0xfc0000 @ encoding: [0x7c,0x45,0xc7,0xf3] +@ CHECK: vbic.i32 d10, #0xfc00 @ encoding: [0x3c,0xa3,0x87,0xf3] +@ CHECK: vbic.i32 q10, #0xfc00 @ encoding: [0x7c,0x43,0xc7,0xf3] +@ CHECK: vbic.i32 d10, #0xfc @ encoding: [0x3c,0xa1,0x87,0xf3] +@ CHECK: vbic.i32 q10, #0xfc @ encoding: [0x7c,0x41,0xc7,0xf3] vorn d16, d17, d16 vorn q8, q8, q9 diff --git a/test/MC/ARM/neon-mov-vfp.s b/test/MC/ARM/neon-mov-vfp.s new file mode 100644 index 0000000..6ee6bfd --- /dev/null +++ b/test/MC/ARM/neon-mov-vfp.s @@ -0,0 +1,32 @@ +@ RUN: not llvm-mc -mcpu=cortex-a8 -triple armv7-unknown-unknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK +@ RUN: not llvm-mc -mcpu=cortex-a8 -triple thumbv7-unknown-unknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK +@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-unknown-unknown -show-encoding -mattr=+neon < %s 2>&1 | FileCheck %s --check-prefix=NEON --check-prefix=CHECK +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7-unknown-unknown -show-encoding -mattr=+neon < %s 2>&1 | FileCheck %s --check-prefix=NEON --check-prefix=CHECK + +@ The 32-bit variants of the NEON scalar move instructions are also available +@ to any core with VFPv2 + +@ CHECK-DAG: vmov.32 d13[0], r6 @ encoding: +@ CHECK-DAG: vmov.32 d17[1], r9 @ encoding: +vmov.32 d13[0], r6 +vmov.32 d17[1], r9 + +@ VFP-DAG: error: instruction requires: NEON +@ VFP-DAG: error: instruction requires: NEON +@ NEON-DAG: vmov.8 d22[5], r2 @ encoding: +@ NEON-DAG: vmov.16 d3[2], r4 @ encoding: +vmov.8 d22[5], r2 +vmov.16 d3[2], r4 + +@ CHECK-DAG: vmov.32 r6, d13[0] @ encoding: +@ CHECK-DAG: vmov.32 r9, d17[1] @ encoding: +vmov.32 r6, d13[0] +vmov.32 r9, d17[1] + +@ VFP-DAG: error: instruction requires: NEON +@ VFP-DAG: error: instruction requires: NEON +@ NEON-DAG: vmov.s8 r2, d22[5] @ encoding: +@ NEON-DAG: vmov.u16 r4, d3[2] @ encoding: +vmov.s8 r2, d22[5] +vmov.u16 r4, d3[2] + diff --git a/test/MC/ARM/symbol-variants.s b/test/MC/ARM/symbol-variants.s index a10fe50..af1bc07 100644 --- a/test/MC/ARM/symbol-variants.s +++ b/test/MC/ARM/symbol-variants.s @@ -19,8 +19,8 @@ @ plt bl f04(PLT) bl f05(plt) -@ARM: 10 R_ARM_PLT32 f04 -@ARM: 14 R_ARM_PLT32 f05 +@ARM: 10 R_ARM_CALL f04 +@ARM: 14 R_ARM_CALL f05 @THUMB: 10 R_ARM_THM_CALL f04 @THUMB: 14 R_ARM_THM_CALL f05 diff --git a/test/MC/ARM/thumb-diagnostics.s b/test/MC/ARM/thumb-diagnostics.s index 19d17c2..2a79132 100644 --- a/test/MC/ARM/thumb-diagnostics.s +++ b/test/MC/ARM/thumb-diagnostics.s @@ -2,6 +2,8 @@ @ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s @ RUN: not llvm-mc -triple=thumbv5-apple-darwin < %s 2> %t @ RUN: FileCheck --check-prefix=CHECK-ERRORS-V5 < %t %s +@ RUN: not llvm-mc -triple=thumbv7m < %s 2> %t +@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V7M < %t %s @ RUN: not llvm-mc -triple=thumbv8 < %s 2> %t @ RUN: FileCheck --check-prefix=CHECK-ERRORS-V8 < %t %s @@ -59,6 +61,13 @@ error: invalid operand for instruction ldm r2!, {r2, r3, r4} ldm r2!, {r2, r3, r4, r10} ldmdb r2!, {r2, r3, r4} + ldm r0, {r2, sp} + ldmia r0, {r2-r3, sp} + ldmia r0!, {r2-r3, sp} + ldmfd r2, {r1, r3-r6, sp} + ldmfd r2!, {r1, r3-r6, sp} + ldmdb r1, {r2, r3, sp} + ldmdb r1!, {r2, r3, sp} @ CHECK-ERRORS: error: registers must be in range r0-r7 @ CHECK-ERRORS: ldm r2!, {r5, r8} @ CHECK-ERRORS: ^ @@ -74,6 +83,27 @@ error: invalid operand for instruction @ CHECK-ERRORS-V8: error: writeback register not allowed in register list @ CHECK-ERRORS-V8: ldmdb r2!, {r2, r3, r4} @ CHECK-ERRORS-V8: ^ +@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: ldm r0, {r2, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: ldmia r0, {r2-r3, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: ldmia r0!, {r2-r3, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: ldmfd r2, {r1, r3-r6, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: ldmfd r2!, {r1, r3-r6, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: ldmdb r1, {r2, r3, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: ldmdb r1!, {r2, r3, sp} +@ CHECK-ERRORS-V7M: ^ @ Invalid writeback and register lists for PUSH/POP pop {r1, r2, r10} @@ -91,6 +121,10 @@ error: invalid operand for instruction stm r1!, {r2, r9} stm r2!, {r2, r9} stmdb r2!, {r0, r2} + stm r1!, {r2, sp} + stmia r4!, {r0-r3, sp} + stmdb r1, {r2, r3, sp} + stmdb r1!, {r2, r3, sp} @ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: stm r1, {r2, r6} @ CHECK-ERRORS: ^ @@ -103,6 +137,18 @@ error: invalid operand for instruction @ CHECK-ERRORS-V8: error: writeback register not allowed in register list @ CHECK-ERRORS-V8: stmdb r2!, {r0, r2} @ CHECK-ERRORS-V8: ^ +@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: stm r1!, {r2, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: stmia r4!, {r0-r3, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: stmdb r1, {r2, r3, sp} +@ CHECK-ERRORS-V7M: ^ +@ CHECK-ERRORS-V7M: error: SP not allowed in register list +@ CHECK-ERRORS-V7M: stmdb r1!, {r2, r3, sp} +@ CHECK-ERRORS-V7M: ^ @ Out of range immediates for LSL instruction. lsls r4, r5, #-1 @@ -218,3 +264,14 @@ error: invalid operand for instruction ldr r4, [pc, #-12] @ CHECK-ERRORS: error: instruction requires: thumb2 +@------------------------------------------------------------------------------ +@ STC2{L}/LDC2{L} - requires thumb2 +@------------------------------------------------------------------------------ + stc2 p0, c8, [r1, #4] + stc2l p6, c2, [r7, #4] + ldc2 p0, c8, [r1, #4] + ldc2l p6, c2, [r7, #4] +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction diff --git a/test/MC/ARM/thumb-not-mclass.s b/test/MC/ARM/thumb-not-mclass.s new file mode 100644 index 0000000..fec545e --- /dev/null +++ b/test/MC/ARM/thumb-not-mclass.s @@ -0,0 +1,26 @@ +@ RUN: not llvm-mc -triple=thumbv7m-apple-darwin -show-encoding < %s 2> %t +@ RUN: FileCheck < %t %s +@ RUN: not llvm-mc -triple=thumbv6m -show-encoding < %s 2> %t +@ RUN: FileCheck < %t %s + .syntax unified + .globl _func + +@ Check that the assembler rejects thumb instructions that are not valid +@ on mclass. + +@------------------------------------------------------------------------------ +@ BLX (immediate) +@------------------------------------------------------------------------------ + blx _baz + +@ CHECK: error: instruction requires: !armv*m + +@------------------------------------------------------------------------------ +@ SETEND +@------------------------------------------------------------------------------ + + setend be + setend le + +@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid operand for instruction diff --git a/test/MC/ARM/thumb2-bxj.s b/test/MC/ARM/thumb2-bxj.s new file mode 100644 index 0000000..e60d1a4 --- /dev/null +++ b/test/MC/ARM/thumb2-bxj.s @@ -0,0 +1,10 @@ +@ RUN: llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF +@ RUN: not llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF + + bxj r2 + +@ CHECK: bxj r2 @ encoding: [0xc2,0xf3,0x00,0x8f] +@ UNDEF: error: instruction requires: arm-mode diff --git a/test/MC/ARM/thumb2-exception-return-mclass.s b/test/MC/ARM/thumb2-exception-return-mclass.s new file mode 100644 index 0000000..21669b0 --- /dev/null +++ b/test/MC/ARM/thumb2-exception-return-mclass.s @@ -0,0 +1,15 @@ +# RUN: not llvm-mc -triple thumbv7m -assemble < %s 2>&1 | FileCheck %s + + .text + +# CHECK: instruction requires: !armv*m +# CHECK-NEXT: srsdb sp, #7 + srsdb sp, #7 + +# CHECK: instruction requires: !armv*m +# CHECK-NEXT: rfeia r6 + rfeia r6 + +# CHECK: instruction requires: !armv*m +# CHECK-NEXT: subs pc, lr, #42 + subs pc, lr, #42 diff --git a/test/MC/ARM/thumb2-ldrb-ldrh.s b/test/MC/ARM/thumb2-ldrb-ldrh.s new file mode 100644 index 0000000..8c97987 --- /dev/null +++ b/test/MC/ARM/thumb2-ldrb-ldrh.s @@ -0,0 +1,51 @@ +@ RUN: not llvm-mc -triple thumbv7a-none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK +@ RUN: not llvm-mc -triple thumbv7m-none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK + +@ Thumb2 LDRS?[BH] are not valid when Rt == PC (these encodings are used for +@ preload hints). +@ We don't check the actual error messages here as they are currently not very +@ helpful, see http://llvm.org/bugs/show_bug.cgi?id=21066. + +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: + ldrb pc, [r0, #10] + ldrb.w pc, [r1, #10] + ldrb pc, [r2, #-5] + ldrb pc, [pc, #7] + ldrb.w pc, [pc, #7] + +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: + ldrsb pc, [r3, #10] + ldrsb.w pc, [r4, #10] + ldrsb pc, [r5, #-5] + ldrsb pc, [pc, #7] + ldrsb.w pc, [pc, #7] + +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: + ldrh pc, [r6, #10] + ldrh.w pc, [r7, #10] + ldrh pc, [r8, #-5] + ldrh pc, [pc, #7] + ldrh.w pc, [pc, #7] + +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: +@ CHECK: error: + ldrsh pc, [r9, #10] + ldrsh.w pc, [r10, #10] + ldrsh pc, [r11, #-5] + ldrsh pc, [pc, #7] + ldrsh.w pc, [pc, #7] diff --git a/test/MC/ARM/thumb2-ldrexd-strexd.s b/test/MC/ARM/thumb2-ldrexd-strexd.s new file mode 100644 index 0000000..3ffb0cb --- /dev/null +++ b/test/MC/ARM/thumb2-ldrexd-strexd.s @@ -0,0 +1,14 @@ +@ RUN: llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s | FileCheck %s +@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF + + ldrexd r0, r1, [r2] + strexd r3, r4, r5, [r6] + +@ CHECK: ldrexd r0, r1, [r2] @ encoding: [0xd2,0xe8,0x7f,0x01] +@ CHECK: strexd r3, r4, r5, [r6] @ encoding: [0xc6,0xe8,0x73,0x45] + +@ UNDEF: error: instruction requires: !armv*m +@ UNDEF: error: instruction requires: !armv*m diff --git a/test/MC/ARM/thumb2-mclass.s b/test/MC/ARM/thumb2-mclass.s index d9c96df..331ecc1 100644 --- a/test/MC/ARM/thumb2-mclass.s +++ b/test/MC/ARM/thumb2-mclass.s @@ -1,7 +1,7 @@ -@ RUN: llvm-mc -triple=thumbv7m-apple-darwin -show-encoding < %s | FileCheck %s -@ RUN: llvm-mc -triple=thumbv6m -show-encoding < %s | FileCheck %s +@ RUN: llvm-mc -triple=thumbv6m -show-encoding < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V6M %s +@ RUN: llvm-mc -triple=thumbv7m -show-encoding < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s + .syntax unified - .globl _func @ Check that the assembler can handle the documented syntax from the ARM ARM. @ These tests test instruction encodings specific to v6m & v7m (FeatureMClass). @@ -40,20 +40,12 @@ msr apsr, r0 msr apsr_nzcvq, r0 - msr apsr_g, r0 - msr apsr_nzcvqg, r0 msr iapsr, r0 msr iapsr_nzcvq, r0 - msr iapsr_g, r0 - msr iapsr_nzcvqg, r0 msr eapsr, r0 msr eapsr_nzcvq, r0 - msr eapsr_g, r0 - msr eapsr_nzcvqg, r0 msr xpsr, r0 msr xpsr_nzcvq, r0 - msr xpsr_g, r0 - msr xpsr_nzcvqg, r0 msr ipsr, r0 msr epsr, r0 msr iepsr, r0 @@ -62,22 +54,22 @@ msr primask, r0 msr control, r0 -@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88] -@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88] -@ CHECK: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84] -@ CHECK: msr apsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x00,0x8c] -@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88] -@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88] -@ CHECK: msr iapsr_g, r0 @ encoding: [0x80,0xf3,0x01,0x84] -@ CHECK: msr iapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x01,0x8c] -@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88] -@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88] -@ CHECK: msr eapsr_g, r0 @ encoding: [0x80,0xf3,0x02,0x84] -@ CHECK: msr eapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x02,0x8c] -@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88] -@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88] -@ CHECK: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84] -@ CHECK: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c] +@ CHECK-V6M: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88] +@ CHECK-V6M: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88] +@ CHECK-V6M: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88] +@ CHECK-V6M: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88] +@ CHECK-V6M: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88] +@ CHECK-V6M: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88] +@ CHECK-V6M: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88] +@ CHECK-V6M: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88] +@ CHECK-V7M: msr apsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x00,0x88] +@ CHECK-V7M: msr apsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x00,0x88] +@ CHECK-V7M: msr iapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x01,0x88] +@ CHECK-V7M: msr iapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x01,0x88] +@ CHECK-V7M: msr eapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x02,0x88] +@ CHECK-V7M: msr eapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x02,0x88] +@ CHECK-V7M: msr xpsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x03,0x88] +@ CHECK-V7M: msr xpsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x03,0x88] @ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88] @ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x88] @ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x88] diff --git a/test/MC/ARM/thumb_rewrites.s b/test/MC/ARM/thumb_rewrites.s new file mode 100644 index 0000000..c9d625e --- /dev/null +++ b/test/MC/ARM/thumb_rewrites.s @@ -0,0 +1,52 @@ +@ RUN: llvm-mc -triple thumbv6m -show-encoding < %s | FileCheck %s + + adds r0, r0, #8 +@ CHECK: adds r0, #8 @ encoding: [0x08,0x30] + + adds r0, r0, r0 +@ CHECK: adds r0, r0, r0 @ encoding: [0x00,0x18] + + add r0, r0, r8 +@ CHECK: add r0, r8 @ encoding: [0x40,0x44] + + add sp, sp, r0 +@ CHECK: add sp, r0 @ encoding: [0x85,0x44] + + add r0, r0, r1 +@ CHECK: add r0, r1 @ encoding: [0x08,0x44] + + add r2, r2, r3 +@ CHECK: add r2, r3 @ encoding: [0x1a,0x44] + + subs r0, r0, r0 +@ CHECK: subs r0, r0, r0 @ encoding: [0x00,0x1a] + + ands r0, r0, r1 +@ CHECK: ands r0, r1 @ encoding: [0x08,0x40] + + eors r0, r0, r1 +@ CHECK: eors r0, r1 @ encoding: [0x48,0x40] + + lsls r0, r0, r1 +@ CHECK: lsls r0, r1 @ encoding: [0x88,0x40] + + lsrs r0, r0, r1 +@ CHECK: lsrs r0, r1 @ encoding: [0xc8,0x40] + + asrs r0, r0, r1 +@ CHECK: asrs r0, r1 @ encoding: [0x08,0x41] + + adcs r0, r0, r1 +@ CHECK: adcs r0, r1 @ encoding: [0x48,0x41] + + sbcs r0, r0, r1 +@ CHECK: sbcs r0, r1 @ encoding: [0x88,0x41] + + rors r0, r0, r1 +@ CHECK: rors r0, r1 @ encoding: [0xc8,0x41] + + orrs r0, r0, r1 +@ CHECK: orrs r0, r1 @ encoding: [0x08,0x43] + + bics r0, r0, r1 +@ CHECK: bics r0, r1 @ encoding: [0x88,0x43] diff --git a/test/MC/ARM/thumbv7em.s b/test/MC/ARM/thumbv7em.s new file mode 100644 index 0000000..53ebff2 --- /dev/null +++ b/test/MC/ARM/thumbv7em.s @@ -0,0 +1,53 @@ +@ RUN: llvm-mc -triple=thumbv7em -show-encoding < %s | FileCheck %s +@ RUN: not llvm-mc -triple=thumbv7m -show-encoding 2>&1 < %s | FileCheck --check-prefix=CHECK-V7M %s + + .syntax unified + +@ Check that the assembler can handle the documented syntax from the ARM ARM. +@ These tests test instruction encodings specific to ARMv7E-M. + +@------------------------------------------------------------------------------ +@ MSR +@------------------------------------------------------------------------------ + + msr apsr_g, r0 + msr apsr_nzcvqg, r0 + msr iapsr_g, r0 + msr iapsr_nzcvqg, r0 + msr eapsr_g, r0 + msr eapsr_nzcvqg, r0 + msr xpsr_g, r0 + msr xpsr_nzcvqg, r0 + +@ CHECK: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84] +@ CHECK: msr apsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x00,0x8c] +@ CHECK: msr iapsr_g, r0 @ encoding: [0x80,0xf3,0x01,0x84] +@ CHECK: msr iapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x01,0x8c] +@ CHECK: msr eapsr_g, r0 @ encoding: [0x80,0xf3,0x02,0x84] +@ CHECK: msr eapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x02,0x8c] +@ CHECK: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84] +@ CHECK: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c] +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr apsr_g, r0 +@ CHECK-V7M-NEXT: ^ +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr apsr_nzcvqg, r0 +@ CHECK-V7M-NEXT: ^ +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr iapsr_g, r0 +@ CHECK-V7M-NEXT: ^ +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr iapsr_nzcvqg, r0 +@ CHECK-V7M-NEXT: ^ +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr eapsr_g, r0 +@ CHECK-V7M-NEXT: ^ +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr eapsr_nzcvqg, r0 +@ CHECK-V7M-NEXT: ^ +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr xpsr_g, r0 +@ CHECK-V7M-NEXT: ^ +@ CHECK-V7M: error: invalid operand for instruction +@ CHECK-V7M-NEXT: msr xpsr_nzcvqg, r0 +@ CHECK-V7M-NEXT: ^ diff --git a/test/MC/ARM/vfp4.s b/test/MC/ARM/vfp4.s index 8b1b0e0..1563b5a 100644 --- a/test/MC/ARM/vfp4.s +++ b/test/MC/ARM/vfp4.s @@ -6,7 +6,7 @@ @ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee] @ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b] -@ THUMB_V7EM-ERRORS: error: instruction requires: double precision VFP +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfma.f64 d16, d18, d17 vfma.f64 d16, d18, d17 @@ -17,7 +17,7 @@ vfma.f32 s2, s4, s0 @ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2] @ THUMB: vfma.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0c] -@ THUMB_V7EM-ERRORS: error: instruction requires: NEON +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfma.f32 d16, d18, d17 vfma.f32 d16, d18, d17 @@ -29,7 +29,7 @@ vfma.f32 q2, q4, q0 @ ARM: vfnma.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xd2,0xee] @ THUMB: vfnma.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xe1,0x0b] -@ THUMB_V7EM-ERRORS: error: instruction requires: double precision VFP +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfnma.f64 d16, d18, d17 vfnma.f64 d16, d18, d17 @@ -40,7 +40,7 @@ vfnma.f32 s2, s4, s0 @ ARM: vfms.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xe2,0xee] @ THUMB: vfms.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xe1,0x0b] -@ THUMB_V7EM-ERRORS: error: instruction requires: double precision VFP +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfms.f64 d16, d18, d17 vfms.f64 d16, d18, d17 @@ -51,7 +51,7 @@ vfms.f32 s2, s4, s0 @ ARM: vfms.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x62,0xf2] @ THUMB: vfms.f32 d16, d18, d17 @ encoding: [0x62,0xef,0xb1,0x0c] -@ THUMB_V7EM-ERRORS: error: instruction requires: NEON +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfms.f32 d16, d18, d17 vfms.f32 d16, d18, d17 @@ -63,7 +63,7 @@ vfms.f32 q2, q4, q0 @ ARM: vfnms.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xd2,0xee] @ THUMB: vfnms.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xa1,0x0b] -@ THUMB_V7EM-ERRORS: error: instruction requires: double precision VFP +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfnms.f64 d16, d18, d17 vfnms.f64 d16, d18, d17 diff --git a/test/MC/ARM/vorr-vbic-illegal-cases.s b/test/MC/ARM/vorr-vbic-illegal-cases.s index 16ab6b5..673098a 100644 --- a/test/MC/ARM/vorr-vbic-illegal-cases.s +++ b/test/MC/ARM/vorr-vbic-illegal-cases.s @@ -1,6 +1,13 @@ @ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s .text + vorr.i32 d2, #0xffffffff + vorr.i32 q2, #0xffffffff + vorr.i32 d2, #0xabababab + vorr.i32 q2, #0xabababab + vorr.i16 q2, #0xabab + vorr.i16 q2, #0xabab + @ CHECK: error: invalid operand for instruction @ CHECK: vorr.i32 d2, #0xffffffff @ CHECK: error: invalid operand for instruction @@ -14,6 +21,13 @@ @ CHECK: error: invalid operand for instruction @ CHECK: vorr.i16 q2, #0xabab + vbic.i32 d2, #0xffffffff + vbic.i32 q2, #0xffffffff + vbic.i32 d2, #0xabababab + vbic.i32 q2, #0xabababab + vbic.i16 d2, #0xabab + vbic.i16 q2, #0xabab + @ CHECK: error: invalid operand for instruction @ CHECK: vbic.i32 d2, #0xffffffff @ CHECK: error: invalid operand for instruction @@ -27,16 +41,25 @@ @ CHECK: error: invalid operand for instruction @ CHECK: vbic.i16 q2, #0xabab - vorr.i32 d2, #0xffffffff - vorr.i32 q2, #0xffffffff - vorr.i32 d2, #0xabababab - vorr.i32 q2, #0xabababab - vorr.i16 q2, #0xabab - vorr.i16 q2, #0xabab + vbic.i32 d2, #0x03ffffff + vbic.i32 q2, #0x03ffff + vbic.i32 d2, #0x03ff + vbic.i32 d2, #0xff00ff + vbic.i16 d2, #0x03ff + vbic.i16 q2, #0xf0f0 + vbic.i16 q2, #0xf0f0f0 - vbic.i32 d2, #0xffffffff - vbic.i32 q2, #0xffffffff - vbic.i32 d2, #0xabababab - vbic.i32 q2, #0xabababab - vbic.i16 d2, #0xabab - vbic.i16 q2, #0xabab +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i32 d2, #0x03ffffff +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i32 q2, #0x03ffff +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i32 d2, #0x03ff +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i32 d2, #0xff00ff +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i16 d2, #0x03ff +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i16 q2, #0xf0f0 +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i16 q2, #0xf0f0f0 |