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| author | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
| commit | dce4a407a24b04eebc6a376f8e62b41aaa7b071f (patch) | |
| tree | dcebc53f2b182f145a2e659393bf9a0472cedf23 /test/MC/Disassembler | |
| parent | 220b921aed042f9e520c26cffd8282a94c66c3d5 (diff) | |
| download | external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.zip external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.gz external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.bz2 | |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
Diffstat (limited to 'test/MC/Disassembler')
51 files changed, 2418 insertions, 1483 deletions
diff --git a/test/MC/Disassembler/AArch64/a64-ignored-fields.txt b/test/MC/Disassembler/AArch64/a64-ignored-fields.txt index 799ecdf..1860bf6 100644 --- a/test/MC/Disassembler/AArch64/a64-ignored-fields.txt +++ b/test/MC/Disassembler/AArch64/a64-ignored-fields.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s # The "Rm" bits are ignored, but the canonical representation has them filled # with 0s. This is what we should produce even if the input bit-pattern had diff --git a/test/MC/Disassembler/ARM64/advsimd.txt b/test/MC/Disassembler/AArch64/arm64-advsimd.txt index 486dd16..cceee67 100644 --- a/test/MC/Disassembler/ARM64/advsimd.txt +++ b/test/MC/Disassembler/AArch64/arm64-advsimd.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple arm64-apple-darwin -output-asm-variant=1 --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 --disassemble < %s | FileCheck %s 0x00 0xb8 0x20 0x0e 0x00 0xb8 0x20 0x4e @@ -124,10 +124,10 @@ # CHECK: smov.s x3, v2[2] # CHECK: smov.s x3, v2[2] -# CHECK: umov.s w3, v2[2] -# CHECK: umov.s w3, v2[2] -# CHECK: umov.d x3, v2[1] -# CHECK: umov.d x3, v2[1] +# CHECK: mov.s w3, v2[2] +# CHECK: mov.s w3, v2[2] +# CHECK: mov.d x3, v2[1] +# CHECK: mov.d x3, v2[1] 0xa2 0x1c 0x18 0x4e 0xa2 0x1c 0x0c 0x4e @@ -320,14 +320,14 @@ 0x00 0x1c 0x60 0x2e 0x00 0x1c 0x20 0x2e 0x00 0x1c 0xe0 0x0e -0x00 0x1c 0xa0 0x0e +0x00 0x1c 0xa1 0x0e # CHECK: bif.8b v0, v0, v0 # CHECK: bit.8b v0, v0, v0 # CHECK: bsl.8b v0, v0, v0 # CHECK: eor.8b v0, v0, v0 # CHECK: orn.8b v0, v0, v0 -# CHECK: orr.8b v0, v0, v0 +# CHECK: orr.8b v0, v0, v1 0x00 0x68 0x20 0x0e 0x00 0x68 0x20 0x4e @@ -445,7 +445,7 @@ # CHECK: frsqrte.2s v0, v0 # CHECK: fsqrt.2s v0, v0 # CHECK: neg.8b v0, v0 -# CHECK: not.8b v0, v0 +# CHECK: mvn.8b v0, v0 # CHECK: rbit.8b v0, v0 # CHECK: rev16.8b v0, v0 # CHECK: rev32.8b v0, v0 @@ -535,18 +535,18 @@ 0x20 0x54 0x00 0x2f 0x20 0x74 0x00 0x2f -# CHECK: bic.2s v0, #1 -# CHECK: bic.2s v0, #1, lsl #8 -# CHECK: bic.2s v0, #1, lsl #16 -# CHECK: bic.2s v0, #1, lsl #24 +# CHECK: bic.2s v0, #0x1 +# CHECK: bic.2s v0, #0x1, lsl #8 +# CHECK: bic.2s v0, #0x1, lsl #16 +# CHECK: bic.2s v0, #0x1, lsl #24 0x20 0x94 0x00 0x2f 0x20 0x94 0x00 0x2f 0x20 0xb4 0x00 0x2f -# CHECK: bic.4h v0, #1 -# CHECK: bic.4h v0, #1 -# FIXME: bic.4h v0, #1, lsl #8 +# CHECK: bic.4h v0, #0x1 +# CHECK: bic.4h v0, #0x1 +# FIXME: bic.4h v0, #0x1, lsl #8 # 'bic.4h' should be selected over "fcvtnu.2s v0, v1, #0" 0x20 0x14 0x00 0x6f @@ -554,43 +554,43 @@ 0x20 0x54 0x00 0x6f 0x20 0x74 0x00 0x6f -# CHECK: bic.4s v0, #1 -# CHECK: bic.4s v0, #1, lsl #8 -# CHECK: bic.4s v0, #1, lsl #16 -# CHECK: bic.4s v0, #1, lsl #24 +# CHECK: bic.4s v0, #0x1 +# CHECK: bic.4s v0, #0x1, lsl #8 +# CHECK: bic.4s v0, #0x1, lsl #16 +# CHECK: bic.4s v0, #0x1, lsl #24 0x20 0x94 0x00 0x6f 0x20 0xb4 0x00 0x6f -# CHECK: bic.8h v0, #1 -# FIXME: bic.8h v0, #1, lsl #8 +# CHECK: bic.8h v0, #0x1 +# FIXME: bic.8h v0, #0x1, lsl #8 # "bic.8h" should be selected over "fcvtnu.4s v0, v1, #0" 0x00 0xf4 0x02 0x6f -# CHECK: fmov.2d v0, #1.250000e-01 +# CHECK: fmov.2d v0, #0.12500000 0x00 0xf4 0x02 0x0f 0x00 0xf4 0x02 0x4f -# CHECK: fmov.2s v0, #1.250000e-01 -# CHECK: fmov.4s v0, #1.250000e-01 +# CHECK: fmov.2s v0, #0.12500000 +# CHECK: fmov.4s v0, #0.12500000 0x20 0x14 0x00 0x0f 0x20 0x34 0x00 0x0f 0x20 0x54 0x00 0x0f 0x20 0x74 0x00 0x0f -# CHECK: orr.2s v0, #1 -# CHECK: orr.2s v0, #1, lsl #8 -# CHECK: orr.2s v0, #1, lsl #16 -# CHECK: orr.2s v0, #1, lsl #24 +# CHECK: orr.2s v0, #0x1 +# CHECK: orr.2s v0, #0x1, lsl #8 +# CHECK: orr.2s v0, #0x1, lsl #16 +# CHECK: orr.2s v0, #0x1, lsl #24 0x20 0x94 0x00 0x0f 0x20 0xb4 0x00 0x0f -# CHECK: orr.4h v0, #1 -# FIXME: orr.4h v0, #1, lsl #8 +# CHECK: orr.4h v0, #0x1 +# FIXME: orr.4h v0, #0x1, lsl #8 # 'orr.4h' should be selected over "fcvtns.2s v0, v1, #0" 0x20 0x14 0x00 0x4f @@ -598,17 +598,16 @@ 0x20 0x54 0x00 0x4f 0x20 0x74 0x00 0x4f -# CHECK: orr.4s v0, #1 -# CHECK: orr.4s v0, #1, lsl #8 -# CHECK: orr.4s v0, #1, lsl #16 -# CHECK: orr.4s v0, #1, lsl #24 +# CHECK: orr.4s v0, #0x1 +# CHECK: orr.4s v0, #0x1, lsl #8 +# CHECK: orr.4s v0, #0x1, lsl #16 +# CHECK: orr.4s v0, #0x1, lsl #24 0x20 0x94 0x00 0x4f 0x20 0xb4 0x00 0x4f -# CHECK: orr.8h v0, #1 -# FIXME: orr.8h v0, #1, lsl #8 -# "orr.8h" should be selected over "fcvtns.4s v0, v1, #0" +# CHECK: orr.8h v0, #0x1 +# CHECK: orr.8h v0, #0x1, lsl #8 0x21 0x70 0x40 0x0c 0x42 0xa0 0x40 0x4c @@ -618,6 +617,7 @@ 0x0a 0x68 0x40 0x4c 0x2d 0xac 0x40 0x0c 0x4f 0x7c 0x40 0x4c +0xe0 0x03 0x40 0x0d # CHECK: ld1.8b { v1 }, [x1] # CHECK: ld1.16b { v2, v3 }, [x2] @@ -627,6 +627,7 @@ # CHECK: ld1.4s { v10, v11, v12 }, [x0] # CHECK: ld1.1d { v13, v14 }, [x1] # CHECK: ld1.2d { v15 }, [x2] +# CHECK: ld1.b { v0 }[0], [sp] 0x41 0x70 0xdf 0x0c 0x41 0xa0 0xdf 0x0c @@ -1443,82 +1444,82 @@ # CHECK: movi d0, #0x000000000000ff # CHECK: movi.2d v0, #0x000000000000ff -# CHECK: movi.8b v0, #1 -# CHECK: movi.16b v0, #1 +# CHECK: movi.8b v0, #0x1 +# CHECK: movi.16b v0, #0x1 0x20 0x04 0x00 0x0f 0x20 0x24 0x00 0x0f 0x20 0x44 0x00 0x0f 0x20 0x64 0x00 0x0f -# CHECK: movi.2s v0, #1 -# CHECK: movi.2s v0, #1, lsl #8 -# CHECK: movi.2s v0, #1, lsl #16 -# CHECK: movi.2s v0, #1, lsl #24 +# CHECK: movi.2s v0, #0x1 +# CHECK: movi.2s v0, #0x1, lsl #8 +# CHECK: movi.2s v0, #0x1, lsl #16 +# CHECK: movi.2s v0, #0x1, lsl #24 0x20 0x04 0x00 0x4f 0x20 0x24 0x00 0x4f 0x20 0x44 0x00 0x4f 0x20 0x64 0x00 0x4f -# CHECK: movi.4s v0, #1 -# CHECK: movi.4s v0, #1, lsl #8 -# CHECK: movi.4s v0, #1, lsl #16 -# CHECK: movi.4s v0, #1, lsl #24 +# CHECK: movi.4s v0, #0x1 +# CHECK: movi.4s v0, #0x1, lsl #8 +# CHECK: movi.4s v0, #0x1, lsl #16 +# CHECK: movi.4s v0, #0x1, lsl #24 0x20 0x84 0x00 0x0f 0x20 0xa4 0x00 0x0f -# CHECK: movi.4h v0, #1 -# CHECK: movi.4h v0, #1, lsl #8 +# CHECK: movi.4h v0, #0x1 +# CHECK: movi.4h v0, #0x1, lsl #8 0x20 0x84 0x00 0x4f 0x20 0xa4 0x00 0x4f -# CHECK: movi.8h v0, #1 -# CHECK: movi.8h v0, #1, lsl #8 +# CHECK: movi.8h v0, #0x1 +# CHECK: movi.8h v0, #0x1, lsl #8 0x20 0x04 0x00 0x2f 0x20 0x24 0x00 0x2f 0x20 0x44 0x00 0x2f 0x20 0x64 0x00 0x2f -# CHECK: mvni.2s v0, #1 -# CHECK: mvni.2s v0, #1, lsl #8 -# CHECK: mvni.2s v0, #1, lsl #16 -# CHECK: mvni.2s v0, #1, lsl #24 +# CHECK: mvni.2s v0, #0x1 +# CHECK: mvni.2s v0, #0x1, lsl #8 +# CHECK: mvni.2s v0, #0x1, lsl #16 +# CHECK: mvni.2s v0, #0x1, lsl #24 0x20 0x04 0x00 0x6f 0x20 0x24 0x00 0x6f 0x20 0x44 0x00 0x6f 0x20 0x64 0x00 0x6f -# CHECK: mvni.4s v0, #1 -# CHECK: mvni.4s v0, #1, lsl #8 -# CHECK: mvni.4s v0, #1, lsl #16 -# CHECK: mvni.4s v0, #1, lsl #24 +# CHECK: mvni.4s v0, #0x1 +# CHECK: mvni.4s v0, #0x1, lsl #8 +# CHECK: mvni.4s v0, #0x1, lsl #16 +# CHECK: mvni.4s v0, #0x1, lsl #24 0x20 0x84 0x00 0x2f 0x20 0xa4 0x00 0x2f -# CHECK: mvni.4h v0, #1 -# CHECK: mvni.4h v0, #1, lsl #8 +# CHECK: mvni.4h v0, #0x1 +# CHECK: mvni.4h v0, #0x1, lsl #8 0x20 0x84 0x00 0x6f 0x20 0xa4 0x00 0x6f -# CHECK: mvni.8h v0, #1 -# CHECK: mvni.8h v0, #1, lsl #8 +# CHECK: mvni.8h v0, #0x1 +# CHECK: mvni.8h v0, #0x1, lsl #8 0x20 0xc4 0x00 0x2f 0x20 0xd4 0x00 0x2f 0x20 0xc4 0x00 0x6f 0x20 0xd4 0x00 0x6f -# CHECK: mvni.2s v0, #1, msl #8 -# CHECK: mvni.2s v0, #1, msl #16 -# CHECK: mvni.4s v0, #1, msl #8 -# CHECK: mvni.4s v0, #1, msl #16 +# CHECK: mvni.2s v0, #0x1, msl #8 +# CHECK: mvni.2s v0, #0x1, msl #16 +# CHECK: mvni.4s v0, #0x1, msl #8 +# CHECK: mvni.4s v0, #0x1, msl #16 0x00 0x88 0x21 0x2e 0x00 0x98 0x21 0x2e diff --git a/test/MC/Disassembler/ARM64/arithmetic.txt b/test/MC/Disassembler/AArch64/arm64-arithmetic.txt index 3981219..bd870ed 100644 --- a/test/MC/Disassembler/ARM64/arithmetic.txt +++ b/test/MC/Disassembler/AArch64/arm64-arithmetic.txt @@ -40,8 +40,8 @@ 0x83 0x00 0x40 0x91 0xff 0x83 0x00 0x91 -# CHECK: add w3, w4, #4194304 -# CHECK: add x3, x4, #4194304 +# CHECK: add w3, w4, #1024, lsl #12 +# CHECK: add x3, x4, #1024, lsl #12 # CHECK: add x3, x4, #0, lsl #12 # CHECK: add sp, sp, #32 @@ -49,11 +49,13 @@ 0x83 0x00 0x50 0x31 0x83 0x00 0x10 0xb1 0x83 0x00 0x50 0xb1 +0xff 0x83 0x00 0xb1 # CHECK: adds w3, w4, #1024 -# CHECK: adds w3, w4, #4194304 +# CHECK: adds w3, w4, #1024, lsl #12 # CHECK: adds x3, x4, #1024 -# CHECK: adds x3, x4, #4194304 +# CHECK: adds x3, x4, #1024, lsl #12 +# CHECK: cmn sp, #32 0x83 0x00 0x10 0x51 0x83 0x00 0x50 0x51 @@ -62,20 +64,22 @@ 0xff 0x83 0x00 0xd1 # CHECK: sub w3, w4, #1024 -# CHECK: sub w3, w4, #4194304 +# CHECK: sub w3, w4, #1024, lsl #12 # CHECK: sub x3, x4, #1024 -# CHECK: sub x3, x4, #4194304 +# CHECK: sub x3, x4, #1024, lsl #12 # CHECK: sub sp, sp, #32 0x83 0x00 0x10 0x71 0x83 0x00 0x50 0x71 0x83 0x00 0x10 0xf1 0x83 0x00 0x50 0xf1 +0xff 0x83 0x00 0xf1 # CHECK: subs w3, w4, #1024 -# CHECK: subs w3, w4, #4194304 +# CHECK: subs w3, w4, #1024, lsl #12 # CHECK: subs x3, x4, #1024 -# CHECK: subs x3, x4, #4194304 +# CHECK: subs x3, x4, #1024, lsl #12 +# CHECK: cmp sp, #32 #==---------------------------------------------------------------------------== # Add/Subtract register with (optional) shift @@ -85,72 +89,72 @@ 0xac 0x01 0x0e 0x8b 0xac 0x31 0x0e 0x0b 0xac 0x31 0x0e 0x8b -0xac 0xa9 0x4e 0x0b -0xac 0xa9 0x4e 0x8b -0xac 0x9d 0x8e 0x0b +0xac 0x29 0x4e 0x0b +0xac 0x29 0x4e 0x8b +0xac 0x1d 0x8e 0x0b 0xac 0x9d 0x8e 0x8b # CHECK: add w12, w13, w14 # CHECK: add x12, x13, x14 # CHECK: add w12, w13, w14, lsl #12 # CHECK: add x12, x13, x14, lsl #12 -# CHECK: add w12, w13, w14, lsr #42 -# CHECK: add x12, x13, x14, lsr #42 -# CHECK: add w12, w13, w14, asr #39 +# CHECK: add w12, w13, w14, lsr #10 +# CHECK: add x12, x13, x14, lsr #10 +# CHECK: add w12, w13, w14, asr #7 # CHECK: add x12, x13, x14, asr #39 0xac 0x01 0x0e 0x4b 0xac 0x01 0x0e 0xcb 0xac 0x31 0x0e 0x4b 0xac 0x31 0x0e 0xcb -0xac 0xa9 0x4e 0x4b -0xac 0xa9 0x4e 0xcb -0xac 0x9d 0x8e 0x4b +0xac 0x29 0x4e 0x4b +0xac 0x29 0x4e 0xcb +0xac 0x1d 0x8e 0x4b 0xac 0x9d 0x8e 0xcb # CHECK: sub w12, w13, w14 # CHECK: sub x12, x13, x14 # CHECK: sub w12, w13, w14, lsl #12 # CHECK: sub x12, x13, x14, lsl #12 -# CHECK: sub w12, w13, w14, lsr #42 -# CHECK: sub x12, x13, x14, lsr #42 -# CHECK: sub w12, w13, w14, asr #39 +# CHECK: sub w12, w13, w14, lsr #10 +# CHECK: sub x12, x13, x14, lsr #10 +# CHECK: sub w12, w13, w14, asr #7 # CHECK: sub x12, x13, x14, asr #39 0xac 0x01 0x0e 0x2b 0xac 0x01 0x0e 0xab 0xac 0x31 0x0e 0x2b 0xac 0x31 0x0e 0xab -0xac 0xa9 0x4e 0x2b -0xac 0xa9 0x4e 0xab -0xac 0x9d 0x8e 0x2b +0xac 0x29 0x4e 0x2b +0xac 0x29 0x4e 0xab +0xac 0x1d 0x8e 0x2b 0xac 0x9d 0x8e 0xab # CHECK: adds w12, w13, w14 # CHECK: adds x12, x13, x14 # CHECK: adds w12, w13, w14, lsl #12 # CHECK: adds x12, x13, x14, lsl #12 -# CHECK: adds w12, w13, w14, lsr #42 -# CHECK: adds x12, x13, x14, lsr #42 -# CHECK: adds w12, w13, w14, asr #39 +# CHECK: adds w12, w13, w14, lsr #10 +# CHECK: adds x12, x13, x14, lsr #10 +# CHECK: adds w12, w13, w14, asr #7 # CHECK: adds x12, x13, x14, asr #39 0xac 0x01 0x0e 0x6b 0xac 0x01 0x0e 0xeb 0xac 0x31 0x0e 0x6b 0xac 0x31 0x0e 0xeb -0xac 0xa9 0x4e 0x6b -0xac 0xa9 0x4e 0xeb -0xac 0x9d 0x8e 0x6b +0xac 0x29 0x4e 0x6b +0xac 0x29 0x4e 0xeb +0xac 0x1d 0x8e 0x6b 0xac 0x9d 0x8e 0xeb # CHECK: subs w12, w13, w14 # CHECK: subs x12, x13, x14 # CHECK: subs w12, w13, w14, lsl #12 # CHECK: subs x12, x13, x14, lsl #12 -# CHECK: subs w12, w13, w14, lsr #42 -# CHECK: subs x12, x13, x14, lsr #42 -# CHECK: subs w12, w13, w14, asr #39 +# CHECK: subs w12, w13, w14, lsr #10 +# CHECK: subs x12, x13, x14, lsr #10 +# CHECK: subs w12, w13, w14, asr #7 # CHECK: subs x12, x13, x14, asr #39 #==---------------------------------------------------------------------------== @@ -168,7 +172,7 @@ # CHECK: add w1, w2, w3, uxtb # CHECK: add w1, w2, w3, uxth -# CHECK: add w1, w2, w3, uxtw +# CHECK: add w1, w2, w3 # CHECK: add w1, w2, w3, uxtx # CHECK: add w1, w2, w3, sxtb # CHECK: add w1, w2, w3, sxth @@ -210,7 +214,7 @@ # CHECK: sub w1, w2, w3, uxtb # CHECK: sub w1, w2, w3, uxth -# CHECK: sub w1, w2, w3, uxtw +# CHECK: sub w1, w2, w3 # CHECK: sub w1, w2, w3, uxtx # CHECK: sub w1, w2, w3, sxtb # CHECK: sub w1, w2, w3, sxth @@ -252,7 +256,7 @@ # CHECK: adds w1, w2, w3, uxtb # CHECK: adds w1, w2, w3, uxth -# CHECK: adds w1, w2, w3, uxtw +# CHECK: adds w1, w2, w3 # CHECK: adds w1, w2, w3, uxtx # CHECK: adds w1, w2, w3, sxtb # CHECK: adds w1, w2, w3, sxth @@ -290,7 +294,7 @@ # CHECK: subs w1, w2, w3, uxtb # CHECK: subs w1, w2, w3, uxth -# CHECK: subs w1, w2, w3, uxtw +# CHECK: subs w1, w2, w3 # CHECK: subs w1, w2, w3, uxtx # CHECK: subs w1, w2, w3, sxtb # CHECK: subs w1, w2, w3, sxth @@ -364,21 +368,21 @@ #==---------------------------------------------------------------------------== 0x41 0x28 0xc3 0x1a -# CHECK: asrv w1, w2, w3 +# CHECK: asr w1, w2, w3 0x41 0x28 0xc3 0x9a -# CHECK: asrv x1, x2, x3 +# CHECK: asr x1, x2, x3 0x41 0x20 0xc3 0x1a -# CHECK: lslv w1, w2, w3 +# CHECK: lsl w1, w2, w3 0x41 0x20 0xc3 0x9a -# CHECK: lslv x1, x2, x3 +# CHECK: lsl x1, x2, x3 0x41 0x24 0xc3 0x1a -# CHECK: lsrv w1, w2, w3 +# CHECK: lsr w1, w2, w3 0x41 0x24 0xc3 0x9a -# CHECK: lsrv x1, x2, x3 +# CHECK: lsr x1, x2, x3 0x41 0x2c 0xc3 0x1a -# CHECK: rorv w1, w2, w3 +# CHECK: ror w1, w2, w3 0x41 0x2c 0xc3 0x9a -# CHECK: rorv x1, x2, x3 +# CHECK: ror x1, x2, x3 #==---------------------------------------------------------------------------== # One operand instructions @@ -448,30 +452,30 @@ 0x20 0x00 0xa0 0x52 0x20 0x00 0xa0 0xd2 -# CHECK: movz w0, #1 -# CHECK: movz x0, #1 -# CHECK: movz w0, #1, lsl #16 -# CHECK: movz x0, #1, lsl #16 +# CHECK: movz w0, #0x1 +# CHECK: movz x0, #0x1 +# CHECK: movz w0, #0x1, lsl #16 +# CHECK: movz x0, #0x1, lsl #16 0x40 0x00 0x80 0x12 0x40 0x00 0x80 0x92 0x40 0x00 0xa0 0x12 0x40 0x00 0xa0 0x92 -# CHECK: movn w0, #2 -# CHECK: movn x0, #2 -# CHECK: movn w0, #2, lsl #16 -# CHECK: movn x0, #2, lsl #16 +# CHECK: movn w0, #0x2 +# CHECK: movn x0, #0x2 +# CHECK: movn w0, #0x2, lsl #16 +# CHECK: movn x0, #0x2, lsl #16 0x20 0x00 0x80 0x72 0x20 0x00 0x80 0xf2 0x20 0x00 0xa0 0x72 0x20 0x00 0xa0 0xf2 -# CHECK: movk w0, #1 -# CHECK: movk x0, #1 -# CHECK: movk w0, #1, lsl #16 -# CHECK: movk x0, #1, lsl #16 +# CHECK: movk w0, #0x1 +# CHECK: movk x0, #0x1 +# CHECK: movk w0, #0x1, lsl #16 +# CHECK: movk x0, #0x1, lsl #16 #==---------------------------------------------------------------------------== # Conditionally set flags instructions diff --git a/test/MC/Disassembler/AArch64/arm64-basic-a64-undefined.txt b/test/MC/Disassembler/AArch64/arm64-basic-a64-undefined.txt new file mode 100644 index 0000000..0e15af6 --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-basic-a64-undefined.txt @@ -0,0 +1,31 @@ +# These spawn another process so they're rather expensive. Not many. + +# LDR/STR: undefined if option field is 10x or 00x. +# RUN: echo "0x00 0x08 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x88 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s + +# Instructions notionally in the add/sub (extended register) sheet, but with +# invalid shift amount or "opt" field. +# RUN: echo "0x00 0x10 0xa0 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x10 0x60 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x14 0x20 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# MOVK with sf == 0 and hw<1> == 1 is unallocated. +# RUN: echo "0x00 0x00 0xc0 0x72" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'. +# RUN: echo "0x00 0x00 0xc0 0xeb" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x80 0x80 0x6b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# UBFM is undefined when s == 0 and imms<5> or immr<5> is 1. +# RUN: echo "0x00 0x80 0x00 0x53" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# EXT on vectors of i8 must have imm<3> = 0. +# RUN: echo "0x00 0x40 0x00 0x2e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# SCVTF on fixed point W-registers is undefined if scale<5> == 0. +# Same with FCVTZS and FCVTZU. +# RUN: echo "0x00 0x00 0x02 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x00 0x18 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM64/bitfield.txt b/test/MC/Disassembler/AArch64/arm64-bitfield.txt index 99e7af1..d620cb3 100644 --- a/test/MC/Disassembler/ARM64/bitfield.txt +++ b/test/MC/Disassembler/AArch64/arm64-bitfield.txt @@ -11,12 +11,12 @@ 0x41 0x3c 0x01 0x53 0x41 0x3c 0x41 0xd3 -# CHECK: bfm w1, w2, #1, #15 -# CHECK: bfm x1, x2, #1, #15 -# CHECK: sbfm w1, w2, #1, #15 -# CHECK: sbfm x1, x2, #1, #15 -# CHECK: ubfm w1, w2, #1, #15 -# CHECK: ubfm x1, x2, #1, #15 +# CHECK: bfxil w1, w2, #1, #15 +# CHECK: bfxil x1, x2, #1, #15 +# CHECK: sbfx w1, w2, #1, #15 +# CHECK: sbfx x1, x2, #1, #15 +# CHECK: ubfx w1, w2, #1, #15 +# CHECK: ubfx x1, x2, #1, #15 #==---------------------------------------------------------------------------== # 5.4.5 Extract (immediate) diff --git a/test/MC/Disassembler/ARM64/branch.txt b/test/MC/Disassembler/AArch64/arm64-branch.txt index c5b254b..6af1ad8 100644 --- a/test/MC/Disassembler/ARM64/branch.txt +++ b/test/MC/Disassembler/AArch64/arm64-branch.txt @@ -24,21 +24,21 @@ #----------------------------------------------------------------------------- 0x20 0x00 0x20 0xd4 -# CHECK: brk #1 +# CHECK: brk #0x1 0x41 0x00 0xa0 0xd4 -# CHECK: dcps1 #2 +# CHECK: dcps1 #0x2 0x62 0x00 0xa0 0xd4 -# CHECK: dcps2 #3 +# CHECK: dcps2 #0x3 0x83 0x00 0xa0 0xd4 -# CHECK: dcps3 #4 +# CHECK: dcps3 #0x4 0xa0 0x00 0x40 0xd4 -# CHECK: hlt #5 +# CHECK: hlt #0x5 0xc2 0x00 0x00 0xd4 -# CHECK: hvc #6 +# CHECK: hvc #0x6 0xe3 0x00 0x00 0xd4 -# CHECK: smc #7 +# CHECK: smc #0x7 0x01 0x01 0x00 0xd4 -# CHECK: svc #8 +# CHECK: svc #0x8 #----------------------------------------------------------------------------- # PC-relative branches (both positive and negative displacement) diff --git a/test/MC/Disassembler/AArch64/arm64-canonical-form.txt b/test/MC/Disassembler/AArch64/arm64-canonical-form.txt new file mode 100644 index 0000000..1c94b13 --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-canonical-form.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon --disassemble < %s | FileCheck %s + +0x00 0x08 0x00 0xc8 + +# CHECK: stxr w0, x0, [x0] + +0x00 0x00 0x40 0x9b + +# CHECK: smulh x0, x0, x0 + +0x08 0x20 0x21 0x1e + +# CHECK: fcmp s0, #0.0 + +0x1f 0x00 0x00 0x11 + +# CHECK: mov wsp, w0 + +0x00 0x7c 0x00 0x13 + +# CHECK: asr w0, w0, #0 diff --git a/test/MC/Disassembler/ARM64/crc32.txt b/test/MC/Disassembler/AArch64/arm64-crc32.txt index ef0a26e..51717ee 100644 --- a/test/MC/Disassembler/ARM64/crc32.txt +++ b/test/MC/Disassembler/AArch64/arm64-crc32.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=arm64 -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+crc -disassemble < %s | FileCheck %s # CHECK: crc32b w5, w7, w20 # CHECK: crc32h w28, wzr, w30 diff --git a/test/MC/Disassembler/ARM64/crypto.txt b/test/MC/Disassembler/AArch64/arm64-crypto.txt index e163b2c..b905b92 100644 --- a/test/MC/Disassembler/ARM64/crypto.txt +++ b/test/MC/Disassembler/AArch64/arm64-crypto.txt @@ -1,5 +1,5 @@ -# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s -# RUN: llvm-mc -triple arm64-apple-darwin -output-asm-variant=1 --disassemble < %s | FileCheck %s --check-prefix=CHECK-APPLE +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 --disassemble < %s | FileCheck %s --check-prefix=CHECK-APPLE 0x20 0x48 0x28 0x4e 0x20 0x58 0x28 0x4e diff --git a/test/MC/Disassembler/ARM64/invalid-logical.txt b/test/MC/Disassembler/AArch64/arm64-invalid-logical.txt index 8a4ecb6..8a4ecb6 100644 --- a/test/MC/Disassembler/ARM64/invalid-logical.txt +++ b/test/MC/Disassembler/AArch64/arm64-invalid-logical.txt diff --git a/test/MC/Disassembler/ARM64/logical.txt b/test/MC/Disassembler/AArch64/arm64-logical.txt index 29db8cb..e3cb3eb 100644 --- a/test/MC/Disassembler/ARM64/logical.txt +++ b/test/MC/Disassembler/AArch64/arm64-logical.txt @@ -13,6 +13,7 @@ 0x00 0x00 0x40 0xf2 0x41 0x0c 0x00 0x72 0x41 0x0c 0x40 0xf2 +0x5f 0x0c 0x40 0xf2 # CHECK: and w0, w0, #0x1 # CHECK: and x0, x0, #0x1 @@ -23,18 +24,23 @@ # CHECK: ands x0, x0, #0x1 # CHECK: ands w1, w2, #0xf # CHECK: ands x1, x2, #0xf +# CHECK: tst x2, #0xf 0x41 0x00 0x12 0x52 0x41 0x00 0x71 0xd2 +0x5f 0x00 0x71 0xd2 # CHECK: eor w1, w2, #0x4000 # CHECK: eor x1, x2, #0x8000 +# CHECK: eor sp, x2, #0x8000 0x41 0x00 0x12 0x32 0x41 0x00 0x71 0xb2 +0x5f 0x00 0x71 0xb2 # CHECK: orr w1, w2, #0x4000 # CHECK: orr x1, x2, #0x8000 +# CHECK: orr sp, x2, #0x8000 #==---------------------------------------------------------------------------== # 5.5.3 Logical (shifted register) diff --git a/test/MC/Disassembler/ARM64/memory.txt b/test/MC/Disassembler/AArch64/arm64-memory.txt index 031bfa6..54556a1 100644 --- a/test/MC/Disassembler/ARM64/memory.txt +++ b/test/MC/Disassembler/AArch64/arm64-memory.txt @@ -83,6 +83,8 @@ 0x64 0x00 0x00 0x39 0x85 0x50 0x00 0x39 0xe2 0x43 0x00 0x79 + 0x00 0xe8 0x20 0x38 + 0x00 0x48 0x20 0x38 # CHECK: str x4, [x3] # CHECK: str x2, [sp, #32] @@ -95,6 +97,8 @@ # CHECK: strb w4, [x3] # CHECK: strb w5, [x4, #20] # CHECK: strh w2, [sp, #32] +# CHECK: strb w0, [x0, x0, sxtx] +# CHECK: strb w0, [x0, w0, uxtw] #----------------------------------------------------------------------------- # Unscaled immediate loads and stores @@ -210,8 +214,8 @@ 0x08 0x8c 0x40 0xfc 0x09 0x0c 0xc1 0x3c -# CHECK: ldr fp, [x7, #8]! -# CHECK: ldr lr, [x7, #8]! +# CHECK: ldr x29, [x7, #8]! +# CHECK: ldr x30, [x7, #8]! # CHECK: ldr b5, [x0, #1]! # CHECK: ldr h6, [x0, #2]! # CHECK: ldr s7, [x0, #4]! @@ -226,8 +230,8 @@ 0x08 0x8c 0x1f 0xfc 0x09 0x0c 0x9f 0x3c -# CHECK: str lr, [x7, #-8]! -# CHECK: str fp, [x7, #-8]! +# CHECK: str x30, [x7, #-8]! +# CHECK: str x29, [x7, #-8]! # CHECK: str b5, [x0, #-1]! # CHECK: str h6, [x0, #-2]! # CHECK: str s7, [x0, #-4]! @@ -246,8 +250,8 @@ 0x08 0x84 0x1f 0xfc 0x09 0x04 0x9f 0x3c -# CHECK: str lr, [x7], #-8 -# CHECK: str fp, [x7], #-8 +# CHECK: str x30, [x7], #-8 +# CHECK: str x29, [x7], #-8 # CHECK: str b5, [x0], #-1 # CHECK: str h6, [x0], #-2 # CHECK: str s7, [x0], #-4 @@ -262,8 +266,8 @@ 0x08 0x84 0x40 0xfc 0x09 0x04 0xc1 0x3c -# CHECK: ldr fp, [x7], #8 -# CHECK: ldr lr, [x7], #8 +# CHECK: ldr x29, [x7], #8 +# CHECK: ldr x30, [x7], #8 # CHECK: ldr b5, [x0], #1 # CHECK: ldr h6, [x0], #2 # CHECK: ldr s7, [x0], #4 @@ -416,15 +420,17 @@ # CHECK: ldr q1, [x1, x2] # CHECK: ldr q1, [x1, x2, lsl #4] + 0x00 0x48 0x20 0x7c 0xe1 0x6b 0x23 0xfc 0xe1 0x5b 0x23 0xfc 0xe1 0x6b 0xa3 0x3c 0xe1 0x5b 0xa3 0x3c +# CHECK: str h0, [x0, w0, uxtw] # CHECK: str d1, [sp, x3] -# CHECK: str d1, [sp, x3, uxtw #3] +# CHECK: str d1, [sp, w3, uxtw #3] # CHECK: str q1, [sp, x3] -# CHECK: str q1, [sp, x3, uxtw #4] +# CHECK: str q1, [sp, w3, uxtw #4] #----------------------------------------------------------------------------- # Load/Store exclusive diff --git a/test/MC/Disassembler/AArch64/arm64-non-apple-fmov.txt b/test/MC/Disassembler/AArch64/arm64-non-apple-fmov.txt new file mode 100644 index 0000000..75cb95c --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-non-apple-fmov.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc -triple arm64 -mattr=neon -disassemble < %s | FileCheck %s + +0x00 0x00 0xae 0x9e +0x00 0x00 0xaf 0x9e + +# CHECK: fmov x0, v0.d[1] +# CHECK: fmov v0.d[1], x0 diff --git a/test/MC/Disassembler/ARM64/scalar-fp.txt b/test/MC/Disassembler/AArch64/arm64-scalar-fp.txt index b242df5..f139700 100644 --- a/test/MC/Disassembler/ARM64/scalar-fp.txt +++ b/test/MC/Disassembler/AArch64/arm64-scalar-fp.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon --disassemble -output-asm-variant=1 < %s | FileCheck %s #----------------------------------------------------------------------------- # Floating-point arithmetic @@ -184,10 +184,10 @@ 0x01 0xf0 0x7b 0x1e 0x01 0xf0 0x6b 0x1e -# CHECK: fmov s1, #1.250000e-01 -# CHECK: fmov d1, #1.250000e-01 -# CHECK: fmov d1, #-4.843750e-01 -# CHECK: fmov d1, #4.843750e-01 +# CHECK: fmov s1, #0.12500000 +# CHECK: fmov d1, #0.12500000 +# CHECK: fmov d1, #-0.48437500 +# CHECK: fmov d1, #0.48437500 0x41 0x40 0x20 0x1e 0x41 0x40 0x60 0x1e diff --git a/test/MC/Disassembler/ARM64/system.txt b/test/MC/Disassembler/AArch64/arm64-system.txt index cefa635..9027a60 100644 --- a/test/MC/Disassembler/ARM64/system.txt +++ b/test/MC/Disassembler/AArch64/arm64-system.txt @@ -26,10 +26,14 @@ # CHECK: clrex #10 0xdf 0x3f 0x03 0xd5 # CHECK: isb{{$}} + 0xdf 0x31 0x03 0xd5 +# CHECK: isb #1 0xbf 0x33 0x03 0xd5 # CHECK: dmb osh 0x9f 0x37 0x03 0xd5 # CHECK: dsb nsh + 0x3f 0x76 0x08 0xd5 +# CHECK: dc ivac #----------------------------------------------------------------------------- # Generic system instructions @@ -38,19 +42,19 @@ 0xe7 0x6a 0x0f 0xd5 0xf4 0x3f 0x2e 0xd5 0xbf 0x40 0x00 0xd5 - 0x00 0x00 0x10 0xd5 - 0x00 0x00 0x30 0xd5 + 0x00 0xb0 0x18 0xd5 + 0x00 0xb0 0x38 0xd5 # CHECK: sys #2, c0, c5, #7 # CHECK: sys #7, c6, c10, #7, x7 # CHECK: sysl x20, #6, c3, c15, #7 -# CHECK: msr SPSel, #0 -# CHECK: msr S2_0_C0_C0_0, x0 -# CHECK: mrs x0, S2_0_C0_C0_0 +# CHECK: msr SPSEL, #0 +# CHECK: msr S3_0_C11_C0_0, x0 +# CHECK: mrs x0, S3_0_C11_C0_0 0x40 0xc0 0x1e 0xd5 - 0x40 0xc0 0x1a 0xd5 - 0x40 0xc0 0x19 0xd5 + 0x40 0xc0 0x1c 0xd5 + 0x40 0xc0 0x18 0xd5 # CHECK: msr RMR_EL3, x0 # CHECK: msr RMR_EL2, x0 diff --git a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt index 40926b1..397a39e 100644 --- a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # Add/sub (immediate) @@ -187,7 +188,7 @@ # CHECK: sub w3, w5, w7 # CHECK: sub wzr, w3, w5 -# CHECK: sub w20, wzr, w4 +# CHECK: {{sub w20, wzr, w4|neg w20, w4}} # CHECK: sub w4, w6, wzr # CHECK: sub w11, w13, w15 # CHECK: sub w9, w3, wzr, lsl #10 @@ -214,7 +215,7 @@ # CHECK: sub x3, x5, x7 # CHECK: sub xzr, x3, x5 -# CHECK: sub x20, xzr, x4 +# CHECK: {{sub x20, xzr, x4|neg x20, x4}} # CHECK: sub x4, x6, xzr # CHECK: sub x11, x13, x15 # CHECK: sub x9, x3, xzr, lsl #10 @@ -241,7 +242,7 @@ # CHECK: subs w3, w5, w7 # CHECK: cmp w3, w5 -# CHECK: subs w20, wzr, w4 +# CHECK: {{subs w20, wzr, w4|negs w20, w4}} # CHECK: subs w4, w6, wzr # CHECK: subs w11, w13, w15 # CHECK: subs w9, w3, wzr, lsl #10 @@ -268,7 +269,7 @@ # CHECK: subs x3, x5, x7 # CHECK: cmp x3, x5 -# CHECK: subs x20, xzr, x4 +# CHECK: {{subs x20, xzr, x4|negs x20, x4}} # CHECK: subs x4, x6, xzr # CHECK: subs x11, x13, x15 # CHECK: subs x9, x3, xzr, lsl #10 @@ -393,18 +394,18 @@ 0x9f 0xde 0x95 0xeb 0xdf 0xfe 0x97 0xeb -# CHECK: sub w29, wzr, w30 -# CHECK: sub w30, wzr, wzr -# CHECK: sub wzr, wzr, w0 -# CHECK: sub w28, wzr, w27 -# CHECK: sub w26, wzr, w25, lsl #29 -# CHECK: sub w24, wzr, w23, lsl #31 -# CHECK: sub w22, wzr, w21, lsr #0 -# CHECK: sub w20, wzr, w19, lsr #1 -# CHECK: sub w18, wzr, w17, lsr #31 -# CHECK: sub w16, wzr, w15, asr #0 -# CHECK: sub w14, wzr, w13, asr #12 -# CHECK: sub w12, wzr, w11, asr #31 +# CHECK: {{sub w29, wzr|neg w29}}, w30 +# CHECK: {{sub w30, wzr|neg w30}}, wzr +# CHECK: {{sub wzr, wzr|neg wzr}}, w0 +# CHECK: {{sub w28, wzr|neg w28}}, w27 +# CHECK: {{sub w26, wzr|neg w26}}, w25, lsl #29 +# CHECK: {{sub w24, wzr|neg w24}}, w23, lsl #31 +# CHECK: {{sub w22, wzr|neg w22}}, w21, lsr #0 +# CHECK: {{sub w20, wzr|neg w20}}, w19, lsr #1 +# CHECK: {{sub w18, wzr|neg w18}}, w17, lsr #31 +# CHECK: {{sub w16, wzr|neg w16}}, w15, asr #0 +# CHECK: {{sub w14, wzr|neg w14}}, w13, asr #12 +# CHECK: {{sub w12, wzr|neg w12}}, w11, asr #31 0xfd 0x3 0x1e 0x4b 0xfe 0x3 0x1f 0x4b 0xff 0x3 0x0 0x4b @@ -418,18 +419,18 @@ 0xee 0x33 0x8d 0x4b 0xec 0x7f 0x8b 0x4b -# CHECK: sub x29, xzr, x30 -# CHECK: sub x30, xzr, xzr -# CHECK: sub xzr, xzr, x0 -# CHECK: sub x28, xzr, x27 -# CHECK: sub x26, xzr, x25, lsl #29 -# CHECK: sub x24, xzr, x23, lsl #31 -# CHECK: sub x22, xzr, x21, lsr #0 -# CHECK: sub x20, xzr, x19, lsr #1 -# CHECK: sub x18, xzr, x17, lsr #31 -# CHECK: sub x16, xzr, x15, asr #0 -# CHECK: sub x14, xzr, x13, asr #12 -# CHECK: sub x12, xzr, x11, asr #31 +# CHECK: {{sub x29, xzr|neg x29}}, x30 +# CHECK: {{sub x30, xzr|neg x30}}, xzr +# CHECK: {{sub xzr, xzr|neg xzr}}, x0 +# CHECK: {{sub x28, xzr|neg x28}}, x27 +# CHECK: {{sub x26, xzr|neg x26}}, x25, lsl #29 +# CHECK: {{sub x24, xzr|neg x24}}, x23, lsl #31 +# CHECK: {{sub x22, xzr|neg x22}}, x21, lsr #0 +# CHECK: {{sub x20, xzr|neg x20}}, x19, lsr #1 +# CHECK: {{sub x18, xzr|neg x18}}, x17, lsr #31 +# CHECK: {{sub x16, xzr|neg x16}}, x15, asr #0 +# CHECK: {{sub x14, xzr|neg x14}}, x13, asr #12 +# CHECK: {{sub x12, xzr|neg x12}}, x11, asr #31 0xfd 0x3 0x1e 0xcb 0xfe 0x3 0x1f 0xcb 0xff 0x3 0x0 0xcb @@ -443,18 +444,18 @@ 0xee 0x33 0x8d 0xcb 0xec 0x7f 0x8b 0xcb -# CHECK: subs w29, wzr, w30 -# CHECK: subs w30, wzr, wzr +# CHECK: {{subs w29, wzr|negs w29}}, w30 +# CHECK: {{subs w30, wzr|negs w30}}, wzr # CHECK: cmp wzr, w0 -# CHECK: subs w28, wzr, w27 -# CHECK: subs w26, wzr, w25, lsl #29 -# CHECK: subs w24, wzr, w23, lsl #31 -# CHECK: subs w22, wzr, w21, lsr #0 -# CHECK: subs w20, wzr, w19, lsr #1 -# CHECK: subs w18, wzr, w17, lsr #31 -# CHECK: subs w16, wzr, w15, asr #0 -# CHECK: subs w14, wzr, w13, asr #12 -# CHECK: subs w12, wzr, w11, asr #31 +# CHECK: {{subs w28, wzr|negs w28}}, w27 +# CHECK: {{subs w26, wzr|negs w26}}, w25, lsl #29 +# CHECK: {{subs w24, wzr|negs w24}}, w23, lsl #31 +# CHECK: {{subs w22, wzr|negs w22}}, w21, lsr #0 +# CHECK: {{subs w20, wzr|negs w20}}, w19, lsr #1 +# CHECK: {{subs w18, wzr|negs w18}}, w17, lsr #31 +# CHECK: {{subs w16, wzr|negs w16}}, w15, asr #0 +# CHECK: {{subs w14, wzr|negs w14}}, w13, asr #12 +# CHECK: {{subs w12, wzr|negs w12}}, w11, asr #31 0xfd 0x3 0x1e 0x6b 0xfe 0x3 0x1f 0x6b 0xff 0x3 0x0 0x6b @@ -468,18 +469,18 @@ 0xee 0x33 0x8d 0x6b 0xec 0x7f 0x8b 0x6b -# CHECK: subs x29, xzr, x30 -# CHECK: subs x30, xzr, xzr +# CHECK: {{subs x29, xzr|negs x29}}, x30 +# CHECK: {{subs x30, xzr|negs x30}}, xzr # CHECK: cmp xzr, x0 -# CHECK: subs x28, xzr, x27 -# CHECK: subs x26, xzr, x25, lsl #29 -# CHECK: subs x24, xzr, x23, lsl #31 -# CHECK: subs x22, xzr, x21, lsr #0 -# CHECK: subs x20, xzr, x19, lsr #1 -# CHECK: subs x18, xzr, x17, lsr #31 -# CHECK: subs x16, xzr, x15, asr #0 -# CHECK: subs x14, xzr, x13, asr #12 -# CHECK: subs x12, xzr, x11, asr #31 +# CHECK: {{subs x28, xzr|negs x28}}, x27 +# CHECK: {{subs x26, xzr|negs x26}}, x25, lsl #29 +# CHECK: {{subs x24, xzr|negs x24}}, x23, lsl #31 +# CHECK: {{subs x22, xzr|negs x22}}, x21, lsr #0 +# CHECK: {{subs x20, xzr|negs x20}}, x19, lsr #1 +# CHECK: {{subs x18, xzr|negs x18}}, x17, lsr #31 +# CHECK: {{subs x16, xzr|negs x16}}, x15, asr #0 +# CHECK: {{subs x14, xzr|negs x14}}, x13, asr #12 +# CHECK: {{subs x12, xzr|negs x12}}, x11, asr #31 0xfd 0x3 0x1e 0xeb 0xfe 0x3 0x1f 0xeb 0xff 0x3 0x0 0xeb @@ -940,21 +941,21 @@ 0xe5 0x27 0x86 0xda 0x7 0x35 0x9f 0xda -# CHECK: csinc w3, wzr, wzr, ne -# CHECK: csinc x9, xzr, xzr, mi -# CHECK: csinv w20, wzr, wzr, eq -# CHECK: csinv x30, xzr, xzr, lt +# CHECK: cset w3, eq +# CHECK: cset x9, pl +# CHECK: csetm w20, ne +# CHECK: csetm x30, ge 0xe3 0x17 0x9f 0x1a 0xe9 0x47 0x9f 0x9a 0xf4 0x3 0x9f 0x5a 0xfe 0xb3 0x9f 0xda -# CHECK: csinc w3, w5, w5, le -# CHECK: csinc wzr, w4, w4, gt -# CHECK: csinc w9, wzr, wzr, ge -# CHECK: csinc x3, x5, x5, le -# CHECK: csinc xzr, x4, x4, gt -# CHECK: csinc x9, xzr, xzr, ge +# CHECK: cinc w3, w5, gt +# CHECK: cinc wzr, w4, le +# CHECK: cset w9, lt +# CHECK: cinc x3, x5, gt +# CHECK: cinc xzr, x4, le +# CHECK: cset x9, lt 0xa3 0xd4 0x85 0x1a 0x9f 0xc4 0x84 0x1a 0xe9 0xa7 0x9f 0x1a @@ -962,12 +963,12 @@ 0x9f 0xc4 0x84 0x9a 0xe9 0xa7 0x9f 0x9a -# CHECK: csinv w3, w5, w5, le -# CHECK: csinv wzr, w4, w4, gt -# CHECK: csinv w9, wzr, wzr, ge -# CHECK: csinv x3, x5, x5, le -# CHECK: csinv xzr, x4, x4, gt -# CHECK: csinv x9, xzr, xzr, ge +# CHECK: cinv w3, w5, gt +# CHECK: cinv wzr, w4, le +# CHECK: csetm w9, lt +# CHECK: cinv x3, x5, gt +# CHECK: cinv xzr, x4, le +# CHECK: csetm x9, lt 0xa3 0xd0 0x85 0x5a 0x9f 0xc0 0x84 0x5a 0xe9 0xa3 0x9f 0x5a @@ -975,12 +976,12 @@ 0x9f 0xc0 0x84 0xda 0xe9 0xa3 0x9f 0xda -# CHECK: csneg w3, w5, w5, le -# CHECK: csneg wzr, w4, w4, gt -# CHECK: csneg w9, wzr, wzr, ge -# CHECK: csneg x3, x5, x5, le -# CHECK: csneg xzr, x4, x4, gt -# CHECK: csneg x9, xzr, xzr, ge +# CHECK: cneg w3, w5, gt +# CHECK: cneg wzr, w4, le +# CHECK: cneg w9, wzr, lt +# CHECK: cneg x3, x5, gt +# CHECK: cneg xzr, x4, le +# CHECK: cneg x9, xzr, lt 0xa3 0xd4 0x85 0x5a 0x9f 0xc4 0x84 0x5a 0xe9 0xa7 0x9f 0x5a @@ -1243,22 +1244,22 @@ #------------------------------------------------------------------------------ # CHECK: svc #0 -# CHECK: svc #65535 +# CHECK: svc #{{65535|0xffff}} 0x1 0x0 0x0 0xd4 0xe1 0xff 0x1f 0xd4 -# CHECK: hvc #1 -# CHECK: smc #12000 -# CHECK: brk #12 -# CHECK: hlt #123 +# CHECK: hvc #{{1|0x1}} +# CHECK: smc #{{12000|0x2ee0}} +# CHECK: brk #{{12|0xc}} +# CHECK: hlt #{{123|0x7b}} 0x22 0x0 0x0 0xd4 0x3 0xdc 0x5 0xd4 0x80 0x1 0x20 0xd4 0x60 0xf 0x40 0xd4 -# CHECK: dcps1 #42 -# CHECK: dcps2 #9 -# CHECK: dcps3 #1000 +# CHECK: dcps1 #{{42|0x2a}} +# CHECK: dcps2 #{{9|0x9}} +# CHECK: dcps3 #{{1000|0x3e8}} 0x41 0x5 0xa0 0xd4 0x22 0x1 0xa0 0xd4 0x3 0x7d 0xa0 0xd4 @@ -1284,9 +1285,9 @@ 0xa3 0x3c 0xc7 0x93 0xab 0xfd 0xd1 0x93 -# CHECK: extr x19, x23, x23, #24 -# CHECK: extr x29, xzr, xzr, #63 -# CHECK: extr w9, w13, w13, #31 +# CHECK: ror x19, x23, #24 +# CHECK: ror x29, xzr, #63 +# CHECK: ror w9, w13, #31 0xf3 0x62 0xd7 0x93 0xfd 0xff 0xdf 0x93 0xa9 0x7d 0x8d 0x13 @@ -2353,23 +2354,23 @@ 0xec 0xff 0xbf 0x3d # CHECK: prfm pldl1keep, [sp, #8] -# CHECK: prfm pldl1strm, [x3, #0] +# CHECK: prfm pldl1strm, [x3{{(, #0)?}}] # CHECK: prfm pldl2keep, [x5, #16] -# CHECK: prfm pldl2strm, [x2, #0] -# CHECK: prfm pldl3keep, [x5, #0] -# CHECK: prfm pldl3strm, [x6, #0] +# CHECK: prfm pldl2strm, [x2{{(, #0)?}}] +# CHECK: prfm pldl3keep, [x5{{(, #0)?}}] +# CHECK: prfm pldl3strm, [x6{{(, #0)?}}] # CHECK: prfm plil1keep, [sp, #8] -# CHECK: prfm plil1strm, [x3, #0] +# CHECK: prfm plil1strm, [x3{{(, #0)?}}] # CHECK: prfm plil2keep, [x5, #16] -# CHECK: prfm plil2strm, [x2, #0] -# CHECK: prfm plil3keep, [x5, #0] -# CHECK: prfm plil3strm, [x6, #0] +# CHECK: prfm plil2strm, [x2{{(, #0)?}}] +# CHECK: prfm plil3keep, [x5{{(, #0)?}}] +# CHECK: prfm plil3strm, [x6{{(, #0)?}}] # CHECK: prfm pstl1keep, [sp, #8] -# CHECK: prfm pstl1strm, [x3, #0] +# CHECK: prfm pstl1strm, [x3{{(, #0)?}}] # CHECK: prfm pstl2keep, [x5, #16] -# CHECK: prfm pstl2strm, [x2, #0] -# CHECK: prfm pstl3keep, [x5, #0] -# CHECK: prfm pstl3strm, [x6, #0] +# CHECK: prfm pstl2strm, [x2{{(, #0)?}}] +# CHECK: prfm pstl3keep, [x5{{(, #0)?}}] +# CHECK: prfm pstl3strm, [x6{{(, #0)?}}] 0xe0 0x07 0x80 0xf9 0x61 0x00 0x80 0xf9 0xa2 0x08 0x80 0xf9 @@ -2722,15 +2723,15 @@ 0xff 0xc7 0x0 0x52 0x30 0xc6 0x1 0x52 -# CHECK: ands wzr, w18, #0xcccccccc +# CHECK: {{ands wzr,|tst}} w18, #0xcccccccc # CHECK: ands w19, w20, #0x33333333 # CHECK: ands w21, w22, #0x99999999 0x5f 0xe6 0x2 0x72 0x93 0xe6 0x0 0x72 0xd5 0xe6 0x1 0x72 -# CHECK: ands wzr, w3, #0xaaaaaaaa -# CHECK: ands wzr, wzr, #0x55555555 +# CHECK: {{ands wzr,|tst}} w3, #0xaaaaaaaa +# CHECK: {{ands wzr,|tst}} wzr, #0x55555555 0x7f 0xf0 0x1 0x72 0xff 0xf3 0x0 0x72 @@ -2762,15 +2763,15 @@ 0xff 0xc7 0x0 0xd2 0x30 0xc6 0x1 0xd2 -# CHECK: ands xzr, x18, #0xcccccccccccccccc +# CHECK: {{ands xzr,|tst}} x18, #0xcccccccccccccccc # CHECK: ands x19, x20, #0x3333333333333333 # CHECK: ands x21, x22, #0x9999999999999999 0x5f 0xe6 0x2 0xf2 0x93 0xe6 0x0 0xf2 0xd5 0xe6 0x1 0xf2 -# CHECK: ands xzr, x3, #0xaaaaaaaaaaaaaaaa -# CHECK: ands xzr, xzr, #0x5555555555555555 +# CHECK: {{ands xzr,|tst}} x3, #0xaaaaaaaaaaaaaaaa +# CHECK: {{ands xzr,|tst}} xzr, #0x5555555555555555 0x7f 0xf0 0x1 0xf2 0xff 0xf3 0x0 0xf2 @@ -2858,15 +2859,15 @@ # limitation in InstAlias. Lots of the "mov[nz]" instructions should # be "mov". -# CHECK: movz w1, #65535 +# CHECK: movz w1, #{{65535|0xffff}} # CHECK: movz w2, #0, lsl #16 -# CHECK: movn w2, #1234 +# CHECK: movn w2, #{{1234|0x4d2}} 0xe1 0xff 0x9f 0x52 0x2 0x0 0xa0 0x52 0x42 0x9a 0x80 0x12 -# CHECK: movz x2, #1234, lsl #32 -# CHECK: movk xzr, #4321, lsl #48 +# CHECK: movz x2, #{{1234|0x4d2}}, lsl #32 +# CHECK: movk xzr, #{{4321|0x10e1}}, lsl #48 0x42 0x9a 0xc0 0xd2 0x3f 0x1c 0xe2 0xf2 @@ -2906,7 +2907,7 @@ #------------------------------------------------------------------------------ # CHECK: nop -# CHECK: hint #127 +# CHECK: hint #{{127|0x7f}} # CHECK: nop # CHECK: yield # CHECK: wfe @@ -2998,9 +2999,9 @@ 0xdf 0x3f 0x3 0xd5 0xdf 0x3c 0x3 0xd5 -# CHECK: msr spsel, #0 -# CHECK: msr daifset, #15 -# CHECK: msr daifclr, #12 +# CHECK: msr {{spsel|SPSEL}}, #0 +# CHECK: msr {{daifset|DAIFSET}}, #15 +# CHECK: msr {{daifclr|DAIFCLR}}, #12 0xbf 0x40 0x0 0xd5 0xdf 0x4f 0x3 0xd5 0xff 0x4c 0x3 0xd5 @@ -3014,21 +3015,21 @@ 0xe9 0x59 0x2f 0xd5 0x41 0xff 0x28 0xd5 -# CHECK: sys #0, c7, c1, #0, xzr -# CHECK: sys #0, c7, c5, #0, xzr -# CHECK: sys #3, c7, c5, #1, x9 +# CHECK: {{sys #0, c7, c1, #0|ic ialluis}} +# CHECK: {{sys #0, c7, c5, #0|ic iallu}} +# CHECK: {{sys #3, c7, c5, #1|ic ivau}}, x9 0x1f 0x71 0x8 0xd5 0x1f 0x75 0x8 0xd5 0x29 0x75 0xb 0xd5 -# CHECK: sys #3, c7, c4, #1, x12 -# CHECK: sys #0, c7, c6, #1, xzr -# CHECK: sys #0, c7, c6, #2, x2 -# CHECK: sys #3, c7, c10, #1, x9 -# CHECK: sys #0, c7, c10, #2, x10 -# CHECK: sys #3, c7, c11, #1, x0 -# CHECK: sys #3, c7, c14, #1, x3 -# CHECK: sys #0, c7, c14, #2, x30 +# CHECK: {{sys #3, c7, c4, #1|dc zva}}, x12 +# CHECK: {{sys #0, c7, c6, #1|dc ivac}} +# CHECK: {{sys #0, c7, c6, #2|dc isw}}, x2 +# CHECK: {{sys #3, c7, c10, #1|dc cvac}}, x9 +# CHECK: {{sys #0, c7, c10, #2|dc csw}}, x10 +# CHECK: {{sys #3, c7, c11, #1|dc cvau}}, x0 +# CHECK: {{sys #3, c7, c14, #1|dc civac}}, x3 +# CHECK: {{sys #0, c7, c14, #2|dc cisw}}, x30 0x2c 0x74 0xb 0xd5 0x3f 0x76 0x8 0xd5 0x42 0x76 0x8 0xd5 @@ -3039,559 +3040,559 @@ 0x5e 0x7e 0x8 0xd5 -# CHECK: msr teecr32_el1, x12 -# CHECK: msr osdtrrx_el1, x12 -# CHECK: msr mdccint_el1, x12 -# CHECK: msr mdscr_el1, x12 -# CHECK: msr osdtrtx_el1, x12 -# CHECK: msr dbgdtr_el0, x12 -# CHECK: msr dbgdtrtx_el0, x12 -# CHECK: msr oseccr_el1, x12 -# CHECK: msr dbgvcr32_el2, x12 -# CHECK: msr dbgbvr0_el1, x12 -# CHECK: msr dbgbvr1_el1, x12 -# CHECK: msr dbgbvr2_el1, x12 -# CHECK: msr dbgbvr3_el1, x12 -# CHECK: msr dbgbvr4_el1, x12 -# CHECK: msr dbgbvr5_el1, x12 -# CHECK: msr dbgbvr6_el1, x12 -# CHECK: msr dbgbvr7_el1, x12 -# CHECK: msr dbgbvr8_el1, x12 -# CHECK: msr dbgbvr9_el1, x12 -# CHECK: msr dbgbvr10_el1, x12 -# CHECK: msr dbgbvr11_el1, x12 -# CHECK: msr dbgbvr12_el1, x12 -# CHECK: msr dbgbvr13_el1, x12 -# CHECK: msr dbgbvr14_el1, x12 -# CHECK: msr dbgbvr15_el1, x12 -# CHECK: msr dbgbcr0_el1, x12 -# CHECK: msr dbgbcr1_el1, x12 -# CHECK: msr dbgbcr2_el1, x12 -# CHECK: msr dbgbcr3_el1, x12 -# CHECK: msr dbgbcr4_el1, x12 -# CHECK: msr dbgbcr5_el1, x12 -# CHECK: msr dbgbcr6_el1, x12 -# CHECK: msr dbgbcr7_el1, x12 -# CHECK: msr dbgbcr8_el1, x12 -# CHECK: msr dbgbcr9_el1, x12 -# CHECK: msr dbgbcr10_el1, x12 -# CHECK: msr dbgbcr11_el1, x12 -# CHECK: msr dbgbcr12_el1, x12 -# CHECK: msr dbgbcr13_el1, x12 -# CHECK: msr dbgbcr14_el1, x12 -# CHECK: msr dbgbcr15_el1, x12 -# CHECK: msr dbgwvr0_el1, x12 -# CHECK: msr dbgwvr1_el1, x12 -# CHECK: msr dbgwvr2_el1, x12 -# CHECK: msr dbgwvr3_el1, x12 -# CHECK: msr dbgwvr4_el1, x12 -# CHECK: msr dbgwvr5_el1, x12 -# CHECK: msr dbgwvr6_el1, x12 -# CHECK: msr dbgwvr7_el1, x12 -# CHECK: msr dbgwvr8_el1, x12 -# CHECK: msr dbgwvr9_el1, x12 -# CHECK: msr dbgwvr10_el1, x12 -# CHECK: msr dbgwvr11_el1, x12 -# CHECK: msr dbgwvr12_el1, x12 -# CHECK: msr dbgwvr13_el1, x12 -# CHECK: msr dbgwvr14_el1, x12 -# CHECK: msr dbgwvr15_el1, x12 -# CHECK: msr dbgwcr0_el1, x12 -# CHECK: msr dbgwcr1_el1, x12 -# CHECK: msr dbgwcr2_el1, x12 -# CHECK: msr dbgwcr3_el1, x12 -# CHECK: msr dbgwcr4_el1, x12 -# CHECK: msr dbgwcr5_el1, x12 -# CHECK: msr dbgwcr6_el1, x12 -# CHECK: msr dbgwcr7_el1, x12 -# CHECK: msr dbgwcr8_el1, x12 -# CHECK: msr dbgwcr9_el1, x12 -# CHECK: msr dbgwcr10_el1, x12 -# CHECK: msr dbgwcr11_el1, x12 -# CHECK: msr dbgwcr12_el1, x12 -# CHECK: msr dbgwcr13_el1, x12 -# CHECK: msr dbgwcr14_el1, x12 -# CHECK: msr dbgwcr15_el1, x12 -# CHECK: msr teehbr32_el1, x12 -# CHECK: msr oslar_el1, x12 -# CHECK: msr osdlr_el1, x12 -# CHECK: msr dbgprcr_el1, x12 -# CHECK: msr dbgclaimset_el1, x12 -# CHECK: msr dbgclaimclr_el1, x12 -# CHECK: msr csselr_el1, x12 -# CHECK: msr vpidr_el2, x12 -# CHECK: msr vmpidr_el2, x12 -# CHECK: msr sctlr_el1, x12 -# CHECK: msr sctlr_el2, x12 -# CHECK: msr sctlr_el3, x12 -# CHECK: msr actlr_el1, x12 -# CHECK: msr actlr_el2, x12 -# CHECK: msr actlr_el3, x12 -# CHECK: msr cpacr_el1, x12 -# CHECK: msr hcr_el2, x12 -# CHECK: msr scr_el3, x12 -# CHECK: msr mdcr_el2, x12 -# CHECK: msr sder32_el3, x12 -# CHECK: msr cptr_el2, x12 -# CHECK: msr cptr_el3, x12 -# CHECK: msr hstr_el2, x12 -# CHECK: msr hacr_el2, x12 -# CHECK: msr mdcr_el3, x12 -# CHECK: msr ttbr0_el1, x12 -# CHECK: msr ttbr0_el2, x12 -# CHECK: msr ttbr0_el3, x12 -# CHECK: msr ttbr1_el1, x12 -# CHECK: msr tcr_el1, x12 -# CHECK: msr tcr_el2, x12 -# CHECK: msr tcr_el3, x12 -# CHECK: msr vttbr_el2, x12 -# CHECK: msr vtcr_el2, x12 -# CHECK: msr dacr32_el2, x12 -# CHECK: msr spsr_el1, x12 -# CHECK: msr spsr_el2, x12 -# CHECK: msr spsr_el3, x12 -# CHECK: msr elr_el1, x12 -# CHECK: msr elr_el2, x12 -# CHECK: msr elr_el3, x12 -# CHECK: msr sp_el0, x12 -# CHECK: msr sp_el1, x12 -# CHECK: msr sp_el2, x12 -# CHECK: msr spsel, x12 -# CHECK: msr nzcv, x12 -# CHECK: msr daif, x12 -# CHECK: msr currentel, x12 -# CHECK: msr spsr_irq, x12 -# CHECK: msr spsr_abt, x12 -# CHECK: msr spsr_und, x12 -# CHECK: msr spsr_fiq, x12 -# CHECK: msr fpcr, x12 -# CHECK: msr fpsr, x12 -# CHECK: msr dspsr_el0, x12 -# CHECK: msr dlr_el0, x12 -# CHECK: msr ifsr32_el2, x12 -# CHECK: msr afsr0_el1, x12 -# CHECK: msr afsr0_el2, x12 -# CHECK: msr afsr0_el3, x12 -# CHECK: msr afsr1_el1, x12 -# CHECK: msr afsr1_el2, x12 -# CHECK: msr afsr1_el3, x12 -# CHECK: msr esr_el1, x12 -# CHECK: msr esr_el2, x12 -# CHECK: msr esr_el3, x12 -# CHECK: msr fpexc32_el2, x12 -# CHECK: msr far_el1, x12 -# CHECK: msr far_el2, x12 -# CHECK: msr far_el3, x12 -# CHECK: msr hpfar_el2, x12 -# CHECK: msr par_el1, x12 -# CHECK: msr pmcr_el0, x12 -# CHECK: msr pmcntenset_el0, x12 -# CHECK: msr pmcntenclr_el0, x12 -# CHECK: msr pmovsclr_el0, x12 -# CHECK: msr pmselr_el0, x12 -# CHECK: msr pmccntr_el0, x12 -# CHECK: msr pmxevtyper_el0, x12 -# CHECK: msr pmxevcntr_el0, x12 -# CHECK: msr pmuserenr_el0, x12 -# CHECK: msr pmintenset_el1, x12 -# CHECK: msr pmintenclr_el1, x12 -# CHECK: msr pmovsset_el0, x12 -# CHECK: msr mair_el1, x12 -# CHECK: msr mair_el2, x12 -# CHECK: msr mair_el3, x12 -# CHECK: msr amair_el1, x12 -# CHECK: msr amair_el2, x12 -# CHECK: msr amair_el3, x12 -# CHECK: msr vbar_el1, x12 -# CHECK: msr vbar_el2, x12 -# CHECK: msr vbar_el3, x12 -# CHECK: msr rmr_el1, x12 -# CHECK: msr rmr_el2, x12 -# CHECK: msr rmr_el3, x12 -# CHECK: msr tpidr_el0, x12 -# CHECK: msr tpidr_el2, x12 -# CHECK: msr tpidr_el3, x12 -# CHECK: msr tpidrro_el0, x12 -# CHECK: msr tpidr_el1, x12 -# CHECK: msr cntfrq_el0, x12 -# CHECK: msr cntvoff_el2, x12 -# CHECK: msr cntkctl_el1, x12 -# CHECK: msr cnthctl_el2, x12 -# CHECK: msr cntp_tval_el0, x12 -# CHECK: msr cnthp_tval_el2, x12 -# CHECK: msr cntps_tval_el1, x12 -# CHECK: msr cntp_ctl_el0, x12 -# CHECK: msr cnthp_ctl_el2, x12 -# CHECK: msr cntps_ctl_el1, x12 -# CHECK: msr cntp_cval_el0, x12 -# CHECK: msr cnthp_cval_el2, x12 -# CHECK: msr cntps_cval_el1, x12 -# CHECK: msr cntv_tval_el0, x12 -# CHECK: msr cntv_ctl_el0, x12 -# CHECK: msr cntv_cval_el0, x12 -# CHECK: msr pmevcntr0_el0, x12 -# CHECK: msr pmevcntr1_el0, x12 -# CHECK: msr pmevcntr2_el0, x12 -# CHECK: msr pmevcntr3_el0, x12 -# CHECK: msr pmevcntr4_el0, x12 -# CHECK: msr pmevcntr5_el0, x12 -# CHECK: msr pmevcntr6_el0, x12 -# CHECK: msr pmevcntr7_el0, x12 -# CHECK: msr pmevcntr8_el0, x12 -# CHECK: msr pmevcntr9_el0, x12 -# CHECK: msr pmevcntr10_el0, x12 -# CHECK: msr pmevcntr11_el0, x12 -# CHECK: msr pmevcntr12_el0, x12 -# CHECK: msr pmevcntr13_el0, x12 -# CHECK: msr pmevcntr14_el0, x12 -# CHECK: msr pmevcntr15_el0, x12 -# CHECK: msr pmevcntr16_el0, x12 -# CHECK: msr pmevcntr17_el0, x12 -# CHECK: msr pmevcntr18_el0, x12 -# CHECK: msr pmevcntr19_el0, x12 -# CHECK: msr pmevcntr20_el0, x12 -# CHECK: msr pmevcntr21_el0, x12 -# CHECK: msr pmevcntr22_el0, x12 -# CHECK: msr pmevcntr23_el0, x12 -# CHECK: msr pmevcntr24_el0, x12 -# CHECK: msr pmevcntr25_el0, x12 -# CHECK: msr pmevcntr26_el0, x12 -# CHECK: msr pmevcntr27_el0, x12 -# CHECK: msr pmevcntr28_el0, x12 -# CHECK: msr pmevcntr29_el0, x12 -# CHECK: msr pmevcntr30_el0, x12 -# CHECK: msr pmccfiltr_el0, x12 -# CHECK: msr pmevtyper0_el0, x12 -# CHECK: msr pmevtyper1_el0, x12 -# CHECK: msr pmevtyper2_el0, x12 -# CHECK: msr pmevtyper3_el0, x12 -# CHECK: msr pmevtyper4_el0, x12 -# CHECK: msr pmevtyper5_el0, x12 -# CHECK: msr pmevtyper6_el0, x12 -# CHECK: msr pmevtyper7_el0, x12 -# CHECK: msr pmevtyper8_el0, x12 -# CHECK: msr pmevtyper9_el0, x12 -# CHECK: msr pmevtyper10_el0, x12 -# CHECK: msr pmevtyper11_el0, x12 -# CHECK: msr pmevtyper12_el0, x12 -# CHECK: msr pmevtyper13_el0, x12 -# CHECK: msr pmevtyper14_el0, x12 -# CHECK: msr pmevtyper15_el0, x12 -# CHECK: msr pmevtyper16_el0, x12 -# CHECK: msr pmevtyper17_el0, x12 -# CHECK: msr pmevtyper18_el0, x12 -# CHECK: msr pmevtyper19_el0, x12 -# CHECK: msr pmevtyper20_el0, x12 -# CHECK: msr pmevtyper21_el0, x12 -# CHECK: msr pmevtyper22_el0, x12 -# CHECK: msr pmevtyper23_el0, x12 -# CHECK: msr pmevtyper24_el0, x12 -# CHECK: msr pmevtyper25_el0, x12 -# CHECK: msr pmevtyper26_el0, x12 -# CHECK: msr pmevtyper27_el0, x12 -# CHECK: msr pmevtyper28_el0, x12 -# CHECK: msr pmevtyper29_el0, x12 -# CHECK: msr pmevtyper30_el0, x12 -# CHECK: mrs x9, teecr32_el1 -# CHECK: mrs x9, osdtrrx_el1 -# CHECK: mrs x9, mdccsr_el0 -# CHECK: mrs x9, mdccint_el1 -# CHECK: mrs x9, mdscr_el1 -# CHECK: mrs x9, osdtrtx_el1 -# CHECK: mrs x9, dbgdtr_el0 -# CHECK: mrs x9, dbgdtrrx_el0 -# CHECK: mrs x9, oseccr_el1 -# CHECK: mrs x9, dbgvcr32_el2 -# CHECK: mrs x9, dbgbvr0_el1 -# CHECK: mrs x9, dbgbvr1_el1 -# CHECK: mrs x9, dbgbvr2_el1 -# CHECK: mrs x9, dbgbvr3_el1 -# CHECK: mrs x9, dbgbvr4_el1 -# CHECK: mrs x9, dbgbvr5_el1 -# CHECK: mrs x9, dbgbvr6_el1 -# CHECK: mrs x9, dbgbvr7_el1 -# CHECK: mrs x9, dbgbvr8_el1 -# CHECK: mrs x9, dbgbvr9_el1 -# CHECK: mrs x9, dbgbvr10_el1 -# CHECK: mrs x9, dbgbvr11_el1 -# CHECK: mrs x9, dbgbvr12_el1 -# CHECK: mrs x9, dbgbvr13_el1 -# CHECK: mrs x9, dbgbvr14_el1 -# CHECK: mrs x9, dbgbvr15_el1 -# CHECK: mrs x9, dbgbcr0_el1 -# CHECK: mrs x9, dbgbcr1_el1 -# CHECK: mrs x9, dbgbcr2_el1 -# CHECK: mrs x9, dbgbcr3_el1 -# CHECK: mrs x9, dbgbcr4_el1 -# CHECK: mrs x9, dbgbcr5_el1 -# CHECK: mrs x9, dbgbcr6_el1 -# CHECK: mrs x9, dbgbcr7_el1 -# CHECK: mrs x9, dbgbcr8_el1 -# CHECK: mrs x9, dbgbcr9_el1 -# CHECK: mrs x9, dbgbcr10_el1 -# CHECK: mrs x9, dbgbcr11_el1 -# CHECK: mrs x9, dbgbcr12_el1 -# CHECK: mrs x9, dbgbcr13_el1 -# CHECK: mrs x9, dbgbcr14_el1 -# CHECK: mrs x9, dbgbcr15_el1 -# CHECK: mrs x9, dbgwvr0_el1 -# CHECK: mrs x9, dbgwvr1_el1 -# CHECK: mrs x9, dbgwvr2_el1 -# CHECK: mrs x9, dbgwvr3_el1 -# CHECK: mrs x9, dbgwvr4_el1 -# CHECK: mrs x9, dbgwvr5_el1 -# CHECK: mrs x9, dbgwvr6_el1 -# CHECK: mrs x9, dbgwvr7_el1 -# CHECK: mrs x9, dbgwvr8_el1 -# CHECK: mrs x9, dbgwvr9_el1 -# CHECK: mrs x9, dbgwvr10_el1 -# CHECK: mrs x9, dbgwvr11_el1 -# CHECK: mrs x9, dbgwvr12_el1 -# CHECK: mrs x9, dbgwvr13_el1 -# CHECK: mrs x9, dbgwvr14_el1 -# CHECK: mrs x9, dbgwvr15_el1 -# CHECK: mrs x9, dbgwcr0_el1 -# CHECK: mrs x9, dbgwcr1_el1 -# CHECK: mrs x9, dbgwcr2_el1 -# CHECK: mrs x9, dbgwcr3_el1 -# CHECK: mrs x9, dbgwcr4_el1 -# CHECK: mrs x9, dbgwcr5_el1 -# CHECK: mrs x9, dbgwcr6_el1 -# CHECK: mrs x9, dbgwcr7_el1 -# CHECK: mrs x9, dbgwcr8_el1 -# CHECK: mrs x9, dbgwcr9_el1 -# CHECK: mrs x9, dbgwcr10_el1 -# CHECK: mrs x9, dbgwcr11_el1 -# CHECK: mrs x9, dbgwcr12_el1 -# CHECK: mrs x9, dbgwcr13_el1 -# CHECK: mrs x9, dbgwcr14_el1 -# CHECK: mrs x9, dbgwcr15_el1 -# CHECK: mrs x9, mdrar_el1 -# CHECK: mrs x9, teehbr32_el1 -# CHECK: mrs x9, oslsr_el1 -# CHECK: mrs x9, osdlr_el1 -# CHECK: mrs x9, dbgprcr_el1 -# CHECK: mrs x9, dbgclaimset_el1 -# CHECK: mrs x9, dbgclaimclr_el1 -# CHECK: mrs x9, dbgauthstatus_el1 -# CHECK: mrs x9, midr_el1 -# CHECK: mrs x9, ccsidr_el1 -# CHECK: mrs x9, csselr_el1 -# CHECK: mrs x9, vpidr_el2 -# CHECK: mrs x9, clidr_el1 -# CHECK: mrs x9, ctr_el0 -# CHECK: mrs x9, mpidr_el1 -# CHECK: mrs x9, vmpidr_el2 -# CHECK: mrs x9, revidr_el1 -# CHECK: mrs x9, aidr_el1 -# CHECK: mrs x9, dczid_el0 -# CHECK: mrs x9, id_pfr0_el1 -# CHECK: mrs x9, id_pfr1_el1 -# CHECK: mrs x9, id_dfr0_el1 -# CHECK: mrs x9, id_afr0_el1 -# CHECK: mrs x9, id_mmfr0_el1 -# CHECK: mrs x9, id_mmfr1_el1 -# CHECK: mrs x9, id_mmfr2_el1 -# CHECK: mrs x9, id_mmfr3_el1 -# CHECK: mrs x9, id_isar0_el1 -# CHECK: mrs x9, id_isar1_el1 -# CHECK: mrs x9, id_isar2_el1 -# CHECK: mrs x9, id_isar3_el1 -# CHECK: mrs x9, id_isar4_el1 -# CHECK: mrs x9, id_isar5_el1 -# CHECK: mrs x9, mvfr0_el1 -# CHECK: mrs x9, mvfr1_el1 -# CHECK: mrs x9, mvfr2_el1 -# CHECK: mrs x9, id_aa64pfr0_el1 -# CHECK: mrs x9, id_aa64pfr1_el1 -# CHECK: mrs x9, id_aa64dfr0_el1 -# CHECK: mrs x9, id_aa64dfr1_el1 -# CHECK: mrs x9, id_aa64afr0_el1 -# CHECK: mrs x9, id_aa64afr1_el1 -# CHECK: mrs x9, id_aa64isar0_el1 -# CHECK: mrs x9, id_aa64isar1_el1 -# CHECK: mrs x9, id_aa64mmfr0_el1 -# CHECK: mrs x9, id_aa64mmfr1_el1 -# CHECK: mrs x9, sctlr_el1 -# CHECK: mrs x9, sctlr_el2 -# CHECK: mrs x9, sctlr_el3 -# CHECK: mrs x9, actlr_el1 -# CHECK: mrs x9, actlr_el2 -# CHECK: mrs x9, actlr_el3 -# CHECK: mrs x9, cpacr_el1 -# CHECK: mrs x9, hcr_el2 -# CHECK: mrs x9, scr_el3 -# CHECK: mrs x9, mdcr_el2 -# CHECK: mrs x9, sder32_el3 -# CHECK: mrs x9, cptr_el2 -# CHECK: mrs x9, cptr_el3 -# CHECK: mrs x9, hstr_el2 -# CHECK: mrs x9, hacr_el2 -# CHECK: mrs x9, mdcr_el3 -# CHECK: mrs x9, ttbr0_el1 -# CHECK: mrs x9, ttbr0_el2 -# CHECK: mrs x9, ttbr0_el3 -# CHECK: mrs x9, ttbr1_el1 -# CHECK: mrs x9, tcr_el1 -# CHECK: mrs x9, tcr_el2 -# CHECK: mrs x9, tcr_el3 -# CHECK: mrs x9, vttbr_el2 -# CHECK: mrs x9, vtcr_el2 -# CHECK: mrs x9, dacr32_el2 -# CHECK: mrs x9, spsr_el1 -# CHECK: mrs x9, spsr_el2 -# CHECK: mrs x9, spsr_el3 -# CHECK: mrs x9, elr_el1 -# CHECK: mrs x9, elr_el2 -# CHECK: mrs x9, elr_el3 -# CHECK: mrs x9, sp_el0 -# CHECK: mrs x9, sp_el1 -# CHECK: mrs x9, sp_el2 -# CHECK: mrs x9, spsel -# CHECK: mrs x9, nzcv -# CHECK: mrs x9, daif -# CHECK: mrs x9, currentel -# CHECK: mrs x9, spsr_irq -# CHECK: mrs x9, spsr_abt -# CHECK: mrs x9, spsr_und -# CHECK: mrs x9, spsr_fiq -# CHECK: mrs x9, fpcr -# CHECK: mrs x9, fpsr -# CHECK: mrs x9, dspsr_el0 -# CHECK: mrs x9, dlr_el0 -# CHECK: mrs x9, ifsr32_el2 -# CHECK: mrs x9, afsr0_el1 -# CHECK: mrs x9, afsr0_el2 -# CHECK: mrs x9, afsr0_el3 -# CHECK: mrs x9, afsr1_el1 -# CHECK: mrs x9, afsr1_el2 -# CHECK: mrs x9, afsr1_el3 -# CHECK: mrs x9, esr_el1 -# CHECK: mrs x9, esr_el2 -# CHECK: mrs x9, esr_el3 -# CHECK: mrs x9, fpexc32_el2 -# CHECK: mrs x9, far_el1 -# CHECK: mrs x9, far_el2 -# CHECK: mrs x9, far_el3 -# CHECK: mrs x9, hpfar_el2 -# CHECK: mrs x9, par_el1 -# CHECK: mrs x9, pmcr_el0 -# CHECK: mrs x9, pmcntenset_el0 -# CHECK: mrs x9, pmcntenclr_el0 -# CHECK: mrs x9, pmovsclr_el0 -# CHECK: mrs x9, pmselr_el0 -# CHECK: mrs x9, pmceid0_el0 -# CHECK: mrs x9, pmceid1_el0 -# CHECK: mrs x9, pmccntr_el0 -# CHECK: mrs x9, pmxevtyper_el0 -# CHECK: mrs x9, pmxevcntr_el0 -# CHECK: mrs x9, pmuserenr_el0 -# CHECK: mrs x9, pmintenset_el1 -# CHECK: mrs x9, pmintenclr_el1 -# CHECK: mrs x9, pmovsset_el0 -# CHECK: mrs x9, mair_el1 -# CHECK: mrs x9, mair_el2 -# CHECK: mrs x9, mair_el3 -# CHECK: mrs x9, amair_el1 -# CHECK: mrs x9, amair_el2 -# CHECK: mrs x9, amair_el3 -# CHECK: mrs x9, vbar_el1 -# CHECK: mrs x9, vbar_el2 -# CHECK: mrs x9, vbar_el3 -# CHECK: mrs x9, rvbar_el1 -# CHECK: mrs x9, rvbar_el2 -# CHECK: mrs x9, rvbar_el3 -# CHECK: mrs x9, rmr_el1 -# CHECK: mrs x9, rmr_el2 -# CHECK: mrs x9, rmr_el3 -# CHECK: mrs x9, isr_el1 -# CHECK: mrs x9, contextidr_el1 -# CHECK: mrs x9, tpidr_el0 -# CHECK: mrs x9, tpidr_el2 -# CHECK: mrs x9, tpidr_el3 -# CHECK: mrs x9, tpidrro_el0 -# CHECK: mrs x9, tpidr_el1 -# CHECK: mrs x9, cntfrq_el0 -# CHECK: mrs x9, cntpct_el0 -# CHECK: mrs x9, cntvct_el0 -# CHECK: mrs x9, cntvoff_el2 -# CHECK: mrs x9, cntkctl_el1 -# CHECK: mrs x9, cnthctl_el2 -# CHECK: mrs x9, cntp_tval_el0 -# CHECK: mrs x9, cnthp_tval_el2 -# CHECK: mrs x9, cntps_tval_el1 -# CHECK: mrs x9, cntp_ctl_el0 -# CHECK: mrs x9, cnthp_ctl_el2 -# CHECK: mrs x9, cntps_ctl_el1 -# CHECK: mrs x9, cntp_cval_el0 -# CHECK: mrs x9, cnthp_cval_el2 -# CHECK: mrs x9, cntps_cval_el1 -# CHECK: mrs x9, cntv_tval_el0 -# CHECK: mrs x9, cntv_ctl_el0 -# CHECK: mrs x9, cntv_cval_el0 -# CHECK: mrs x9, pmevcntr0_el0 -# CHECK: mrs x9, pmevcntr1_el0 -# CHECK: mrs x9, pmevcntr2_el0 -# CHECK: mrs x9, pmevcntr3_el0 -# CHECK: mrs x9, pmevcntr4_el0 -# CHECK: mrs x9, pmevcntr5_el0 -# CHECK: mrs x9, pmevcntr6_el0 -# CHECK: mrs x9, pmevcntr7_el0 -# CHECK: mrs x9, pmevcntr8_el0 -# CHECK: mrs x9, pmevcntr9_el0 -# CHECK: mrs x9, pmevcntr10_el0 -# CHECK: mrs x9, pmevcntr11_el0 -# CHECK: mrs x9, pmevcntr12_el0 -# CHECK: mrs x9, pmevcntr13_el0 -# CHECK: mrs x9, pmevcntr14_el0 -# CHECK: mrs x9, pmevcntr15_el0 -# CHECK: mrs x9, pmevcntr16_el0 -# CHECK: mrs x9, pmevcntr17_el0 -# CHECK: mrs x9, pmevcntr18_el0 -# CHECK: mrs x9, pmevcntr19_el0 -# CHECK: mrs x9, pmevcntr20_el0 -# CHECK: mrs x9, pmevcntr21_el0 -# CHECK: mrs x9, pmevcntr22_el0 -# CHECK: mrs x9, pmevcntr23_el0 -# CHECK: mrs x9, pmevcntr24_el0 -# CHECK: mrs x9, pmevcntr25_el0 -# CHECK: mrs x9, pmevcntr26_el0 -# CHECK: mrs x9, pmevcntr27_el0 -# CHECK: mrs x9, pmevcntr28_el0 -# CHECK: mrs x9, pmevcntr29_el0 -# CHECK: mrs x9, pmevcntr30_el0 -# CHECK: mrs x9, pmccfiltr_el0 -# CHECK: mrs x9, pmevtyper0_el0 -# CHECK: mrs x9, pmevtyper1_el0 -# CHECK: mrs x9, pmevtyper2_el0 -# CHECK: mrs x9, pmevtyper3_el0 -# CHECK: mrs x9, pmevtyper4_el0 -# CHECK: mrs x9, pmevtyper5_el0 -# CHECK: mrs x9, pmevtyper6_el0 -# CHECK: mrs x9, pmevtyper7_el0 -# CHECK: mrs x9, pmevtyper8_el0 -# CHECK: mrs x9, pmevtyper9_el0 -# CHECK: mrs x9, pmevtyper10_el0 -# CHECK: mrs x9, pmevtyper11_el0 -# CHECK: mrs x9, pmevtyper12_el0 -# CHECK: mrs x9, pmevtyper13_el0 -# CHECK: mrs x9, pmevtyper14_el0 -# CHECK: mrs x9, pmevtyper15_el0 -# CHECK: mrs x9, pmevtyper16_el0 -# CHECK: mrs x9, pmevtyper17_el0 -# CHECK: mrs x9, pmevtyper18_el0 -# CHECK: mrs x9, pmevtyper19_el0 -# CHECK: mrs x9, pmevtyper20_el0 -# CHECK: mrs x9, pmevtyper21_el0 -# CHECK: mrs x9, pmevtyper22_el0 -# CHECK: mrs x9, pmevtyper23_el0 -# CHECK: mrs x9, pmevtyper24_el0 -# CHECK: mrs x9, pmevtyper25_el0 -# CHECK: mrs x9, pmevtyper26_el0 -# CHECK: mrs x9, pmevtyper27_el0 -# CHECK: mrs x9, pmevtyper28_el0 -# CHECK: mrs x9, pmevtyper29_el0 -# CHECK: mrs x9, pmevtyper30_el0 +# CHECK: msr {{teecr32_el1|TEECR32_EL1}}, x12 +# CHECK: msr {{osdtrrx_el1|OSDTRRX_EL1}}, x12 +# CHECK: msr {{mdccint_el1|MDCCINT_EL1}}, x12 +# CHECK: msr {{mdscr_el1|MDSCR_EL1}}, x12 +# CHECK: msr {{osdtrtx_el1|OSDTRTX_EL1}}, x12 +# CHECK: msr {{dbgdtr_el0|DBGDTR_EL0}}, x12 +# CHECK: msr {{dbgdtrtx_el0|DBGDTRTX_EL0}}, x12 +# CHECK: msr {{oseccr_el1|OSECCR_EL1}}, x12 +# CHECK: msr {{dbgvcr32_el2|DBGVCR32_EL2}}, x12 +# CHECK: msr {{dbgbvr0_el1|DBGBVR0_EL1}}, x12 +# CHECK: msr {{dbgbvr1_el1|DBGBVR1_EL1}}, x12 +# CHECK: msr {{dbgbvr2_el1|DBGBVR2_EL1}}, x12 +# CHECK: msr {{dbgbvr3_el1|DBGBVR3_EL1}}, x12 +# CHECK: msr {{dbgbvr4_el1|DBGBVR4_EL1}}, x12 +# CHECK: msr {{dbgbvr5_el1|DBGBVR5_EL1}}, x12 +# CHECK: msr {{dbgbvr6_el1|DBGBVR6_EL1}}, x12 +# CHECK: msr {{dbgbvr7_el1|DBGBVR7_EL1}}, x12 +# CHECK: msr {{dbgbvr8_el1|DBGBVR8_EL1}}, x12 +# CHECK: msr {{dbgbvr9_el1|DBGBVR9_EL1}}, x12 +# CHECK: msr {{dbgbvr10_el1|DBGBVR10_EL1}}, x12 +# CHECK: msr {{dbgbvr11_el1|DBGBVR11_EL1}}, x12 +# CHECK: msr {{dbgbvr12_el1|DBGBVR12_EL1}}, x12 +# CHECK: msr {{dbgbvr13_el1|DBGBVR13_EL1}}, x12 +# CHECK: msr {{dbgbvr14_el1|DBGBVR14_EL1}}, x12 +# CHECK: msr {{dbgbvr15_el1|DBGBVR15_EL1}}, x12 +# CHECK: msr {{dbgbcr0_el1|DBGBCR0_EL1}}, x12 +# CHECK: msr {{dbgbcr1_el1|DBGBCR1_EL1}}, x12 +# CHECK: msr {{dbgbcr2_el1|DBGBCR2_EL1}}, x12 +# CHECK: msr {{dbgbcr3_el1|DBGBCR3_EL1}}, x12 +# CHECK: msr {{dbgbcr4_el1|DBGBCR4_EL1}}, x12 +# CHECK: msr {{dbgbcr5_el1|DBGBCR5_EL1}}, x12 +# CHECK: msr {{dbgbcr6_el1|DBGBCR6_EL1}}, x12 +# CHECK: msr {{dbgbcr7_el1|DBGBCR7_EL1}}, x12 +# CHECK: msr {{dbgbcr8_el1|DBGBCR8_EL1}}, x12 +# CHECK: msr {{dbgbcr9_el1|DBGBCR9_EL1}}, x12 +# CHECK: msr {{dbgbcr10_el1|DBGBCR10_EL1}}, x12 +# CHECK: msr {{dbgbcr11_el1|DBGBCR11_EL1}}, x12 +# CHECK: msr {{dbgbcr12_el1|DBGBCR12_EL1}}, x12 +# CHECK: msr {{dbgbcr13_el1|DBGBCR13_EL1}}, x12 +# CHECK: msr {{dbgbcr14_el1|DBGBCR14_EL1}}, x12 +# CHECK: msr {{dbgbcr15_el1|DBGBCR15_EL1}}, x12 +# CHECK: msr {{dbgwvr0_el1|DBGWVR0_EL1}}, x12 +# CHECK: msr {{dbgwvr1_el1|DBGWVR1_EL1}}, x12 +# CHECK: msr {{dbgwvr2_el1|DBGWVR2_EL1}}, x12 +# CHECK: msr {{dbgwvr3_el1|DBGWVR3_EL1}}, x12 +# CHECK: msr {{dbgwvr4_el1|DBGWVR4_EL1}}, x12 +# CHECK: msr {{dbgwvr5_el1|DBGWVR5_EL1}}, x12 +# CHECK: msr {{dbgwvr6_el1|DBGWVR6_EL1}}, x12 +# CHECK: msr {{dbgwvr7_el1|DBGWVR7_EL1}}, x12 +# CHECK: msr {{dbgwvr8_el1|DBGWVR8_EL1}}, x12 +# CHECK: msr {{dbgwvr9_el1|DBGWVR9_EL1}}, x12 +# CHECK: msr {{dbgwvr10_el1|DBGWVR10_EL1}}, x12 +# CHECK: msr {{dbgwvr11_el1|DBGWVR11_EL1}}, x12 +# CHECK: msr {{dbgwvr12_el1|DBGWVR12_EL1}}, x12 +# CHECK: msr {{dbgwvr13_el1|DBGWVR13_EL1}}, x12 +# CHECK: msr {{dbgwvr14_el1|DBGWVR14_EL1}}, x12 +# CHECK: msr {{dbgwvr15_el1|DBGWVR15_EL1}}, x12 +# CHECK: msr {{dbgwcr0_el1|DBGWCR0_EL1}}, x12 +# CHECK: msr {{dbgwcr1_el1|DBGWCR1_EL1}}, x12 +# CHECK: msr {{dbgwcr2_el1|DBGWCR2_EL1}}, x12 +# CHECK: msr {{dbgwcr3_el1|DBGWCR3_EL1}}, x12 +# CHECK: msr {{dbgwcr4_el1|DBGWCR4_EL1}}, x12 +# CHECK: msr {{dbgwcr5_el1|DBGWCR5_EL1}}, x12 +# CHECK: msr {{dbgwcr6_el1|DBGWCR6_EL1}}, x12 +# CHECK: msr {{dbgwcr7_el1|DBGWCR7_EL1}}, x12 +# CHECK: msr {{dbgwcr8_el1|DBGWCR8_EL1}}, x12 +# CHECK: msr {{dbgwcr9_el1|DBGWCR9_EL1}}, x12 +# CHECK: msr {{dbgwcr10_el1|DBGWCR10_EL1}}, x12 +# CHECK: msr {{dbgwcr11_el1|DBGWCR11_EL1}}, x12 +# CHECK: msr {{dbgwcr12_el1|DBGWCR12_EL1}}, x12 +# CHECK: msr {{dbgwcr13_el1|DBGWCR13_EL1}}, x12 +# CHECK: msr {{dbgwcr14_el1|DBGWCR14_EL1}}, x12 +# CHECK: msr {{dbgwcr15_el1|DBGWCR15_EL1}}, x12 +# CHECK: msr {{teehbr32_el1|TEEHBR32_EL1}}, x12 +# CHECK: msr {{oslar_el1|OSLAR_EL1}}, x12 +# CHECK: msr {{osdlr_el1|OSDLR_EL1}}, x12 +# CHECK: msr {{dbgprcr_el1|DBGPRCR_EL1}}, x12 +# CHECK: msr {{dbgclaimset_el1|DBGCLAIMSET_EL1}}, x12 +# CHECK: msr {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}, x12 +# CHECK: msr {{csselr_el1|CSSELR_EL1}}, x12 +# CHECK: msr {{vpidr_el2|VPIDR_EL2}}, x12 +# CHECK: msr {{vmpidr_el2|VMPIDR_EL2}}, x12 +# CHECK: msr {{sctlr_el1|SCTLR_EL1}}, x12 +# CHECK: msr {{sctlr_el2|SCTLR_EL2}}, x12 +# CHECK: msr {{sctlr_el3|SCTLR_EL3}}, x12 +# CHECK: msr {{actlr_el1|ACTLR_EL1}}, x12 +# CHECK: msr {{actlr_el2|ACTLR_EL2}}, x12 +# CHECK: msr {{actlr_el3|ACTLR_EL3}}, x12 +# CHECK: msr {{cpacr_el1|CPACR_EL1}}, x12 +# CHECK: msr {{hcr_el2|HCR_EL2}}, x12 +# CHECK: msr {{scr_el3|SCR_EL3}}, x12 +# CHECK: msr {{mdcr_el2|MDCR_EL2}}, x12 +# CHECK: msr {{sder32_el3|SDER32_EL3}}, x12 +# CHECK: msr {{cptr_el2|CPTR_EL2}}, x12 +# CHECK: msr {{cptr_el3|CPTR_EL3}}, x12 +# CHECK: msr {{hstr_el2|HSTR_EL2}}, x12 +# CHECK: msr {{hacr_el2|HACR_EL2}}, x12 +# CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12 +# CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12 +# CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12 +# CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12 +# CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12 +# CHECK: msr {{tcr_el1|TCR_EL1}}, x12 +# CHECK: msr {{tcr_el2|TCR_EL2}}, x12 +# CHECK: msr {{tcr_el3|TCR_EL3}}, x12 +# CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12 +# CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12 +# CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12 +# CHECK: msr {{spsr_el1|SPSR_EL1}}, x12 +# CHECK: msr {{spsr_el2|SPSR_EL2}}, x12 +# CHECK: msr {{spsr_el3|SPSR_EL3}}, x12 +# CHECK: msr {{elr_el1|ELR_EL1}}, x12 +# CHECK: msr {{elr_el2|ELR_EL2}}, x12 +# CHECK: msr {{elr_el3|ELR_EL3}}, x12 +# CHECK: msr {{sp_el0|SP_EL0}}, x12 +# CHECK: msr {{sp_el1|SP_EL1}}, x12 +# CHECK: msr {{sp_el2|SP_EL2}}, x12 +# CHECK: msr {{spsel|SPSEL}}, x12 +# CHECK: msr {{nzcv|NZCV}}, x12 +# CHECK: msr {{daif|DAIF}}, x12 +# CHECK: msr {{currentel|CURRENTEL}}, x12 +# CHECK: msr {{spsr_irq|SPSR_IRQ}}, x12 +# CHECK: msr {{spsr_abt|SPSR_ABT}}, x12 +# CHECK: msr {{spsr_und|SPSR_UND}}, x12 +# CHECK: msr {{spsr_fiq|SPSR_FIQ}}, x12 +# CHECK: msr {{fpcr|FPCR}}, x12 +# CHECK: msr {{fpsr|FPSR}}, x12 +# CHECK: msr {{dspsr_el0|DSPSR_EL0}}, x12 +# CHECK: msr {{dlr_el0|DLR_EL0}}, x12 +# CHECK: msr {{ifsr32_el2|IFSR32_EL2}}, x12 +# CHECK: msr {{afsr0_el1|AFSR0_EL1}}, x12 +# CHECK: msr {{afsr0_el2|AFSR0_EL2}}, x12 +# CHECK: msr {{afsr0_el3|AFSR0_EL3}}, x12 +# CHECK: msr {{afsr1_el1|AFSR1_EL1}}, x12 +# CHECK: msr {{afsr1_el2|AFSR1_EL2}}, x12 +# CHECK: msr {{afsr1_el3|AFSR1_EL3}}, x12 +# CHECK: msr {{esr_el1|ESR_EL1}}, x12 +# CHECK: msr {{esr_el2|ESR_EL2}}, x12 +# CHECK: msr {{esr_el3|ESR_EL3}}, x12 +# CHECK: msr {{fpexc32_el2|FPEXC32_EL2}}, x12 +# CHECK: msr {{far_el1|FAR_EL1}}, x12 +# CHECK: msr {{far_el2|FAR_EL2}}, x12 +# CHECK: msr {{far_el3|FAR_EL3}}, x12 +# CHECK: msr {{hpfar_el2|HPFAR_EL2}}, x12 +# CHECK: msr {{par_el1|PAR_EL1}}, x12 +# CHECK: msr {{pmcr_el0|PMCR_EL0}}, x12 +# CHECK: msr {{pmcntenset_el0|PMCNTENSET_EL0}}, x12 +# CHECK: msr {{pmcntenclr_el0|PMCNTENCLR_EL0}}, x12 +# CHECK: msr {{pmovsclr_el0|PMOVSCLR_EL0}}, x12 +# CHECK: msr {{pmselr_el0|PMSELR_EL0}}, x12 +# CHECK: msr {{pmccntr_el0|PMCCNTR_EL0}}, x12 +# CHECK: msr {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12 +# CHECK: msr {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12 +# CHECK: msr {{pmuserenr_el0|PMUSERENR_EL0}}, x12 +# CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12 +# CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12 +# CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12 +# CHECK: msr {{mair_el1|MAIR_EL1}}, x12 +# CHECK: msr {{mair_el2|MAIR_EL2}}, x12 +# CHECK: msr {{mair_el3|MAIR_EL3}}, x12 +# CHECK: msr {{amair_el1|AMAIR_EL1}}, x12 +# CHECK: msr {{amair_el2|AMAIR_EL2}}, x12 +# CHECK: msr {{amair_el3|AMAIR_EL3}}, x12 +# CHECK: msr {{vbar_el1|VBAR_EL1}}, x12 +# CHECK: msr {{vbar_el2|VBAR_EL2}}, x12 +# CHECK: msr {{vbar_el3|VBAR_EL3}}, x12 +# CHECK: msr {{rmr_el1|RMR_EL1}}, x12 +# CHECK: msr {{rmr_el2|RMR_EL2}}, x12 +# CHECK: msr {{rmr_el3|RMR_EL3}}, x12 +# CHECK: msr {{tpidr_el0|TPIDR_EL0}}, x12 +# CHECK: msr {{tpidr_el2|TPIDR_EL2}}, x12 +# CHECK: msr {{tpidr_el3|TPIDR_EL3}}, x12 +# CHECK: msr {{tpidrro_el0|TPIDRRO_EL0}}, x12 +# CHECK: msr {{tpidr_el1|TPIDR_EL1}}, x12 +# CHECK: msr {{cntfrq_el0|CNTFRQ_EL0}}, x12 +# CHECK: msr {{cntvoff_el2|CNTVOFF_EL2}}, x12 +# CHECK: msr {{cntkctl_el1|CNTKCTL_EL1}}, x12 +# CHECK: msr {{cnthctl_el2|CNTHCTL_EL2}}, x12 +# CHECK: msr {{cntp_tval_el0|CNTP_TVAL_EL0}}, x12 +# CHECK: msr {{cnthp_tval_el2|CNTHP_TVAL_EL2}}, x12 +# CHECK: msr {{cntps_tval_el1|CNTPS_TVAL_EL1}}, x12 +# CHECK: msr {{cntp_ctl_el0|CNTP_CTL_EL0}}, x12 +# CHECK: msr {{cnthp_ctl_el2|CNTHP_CTL_EL2}}, x12 +# CHECK: msr {{cntps_ctl_el1|CNTPS_CTL_EL1}}, x12 +# CHECK: msr {{cntp_cval_el0|CNTP_CVAL_EL0}}, x12 +# CHECK: msr {{cnthp_cval_el2|CNTHP_CVAL_EL2}}, x12 +# CHECK: msr {{cntps_cval_el1|CNTPS_CVAL_EL1}}, x12 +# CHECK: msr {{cntv_tval_el0|CNTV_TVAL_EL0}}, x12 +# CHECK: msr {{cntv_ctl_el0|CNTV_CTL_EL0}}, x12 +# CHECK: msr {{cntv_cval_el0|CNTV_CVAL_EL0}}, x12 +# CHECK: msr {{pmevcntr0_el0|PMEVCNTR0_EL0}}, x12 +# CHECK: msr {{pmevcntr1_el0|PMEVCNTR1_EL0}}, x12 +# CHECK: msr {{pmevcntr2_el0|PMEVCNTR2_EL0}}, x12 +# CHECK: msr {{pmevcntr3_el0|PMEVCNTR3_EL0}}, x12 +# CHECK: msr {{pmevcntr4_el0|PMEVCNTR4_EL0}}, x12 +# CHECK: msr {{pmevcntr5_el0|PMEVCNTR5_EL0}}, x12 +# CHECK: msr {{pmevcntr6_el0|PMEVCNTR6_EL0}}, x12 +# CHECK: msr {{pmevcntr7_el0|PMEVCNTR7_EL0}}, x12 +# CHECK: msr {{pmevcntr8_el0|PMEVCNTR8_EL0}}, x12 +# CHECK: msr {{pmevcntr9_el0|PMEVCNTR9_EL0}}, x12 +# CHECK: msr {{pmevcntr10_el0|PMEVCNTR10_EL0}}, x12 +# CHECK: msr {{pmevcntr11_el0|PMEVCNTR11_EL0}}, x12 +# CHECK: msr {{pmevcntr12_el0|PMEVCNTR12_EL0}}, x12 +# CHECK: msr {{pmevcntr13_el0|PMEVCNTR13_EL0}}, x12 +# CHECK: msr {{pmevcntr14_el0|PMEVCNTR14_EL0}}, x12 +# CHECK: msr {{pmevcntr15_el0|PMEVCNTR15_EL0}}, x12 +# CHECK: msr {{pmevcntr16_el0|PMEVCNTR16_EL0}}, x12 +# CHECK: msr {{pmevcntr17_el0|PMEVCNTR17_EL0}}, x12 +# CHECK: msr {{pmevcntr18_el0|PMEVCNTR18_EL0}}, x12 +# CHECK: msr {{pmevcntr19_el0|PMEVCNTR19_EL0}}, x12 +# CHECK: msr {{pmevcntr20_el0|PMEVCNTR20_EL0}}, x12 +# CHECK: msr {{pmevcntr21_el0|PMEVCNTR21_EL0}}, x12 +# CHECK: msr {{pmevcntr22_el0|PMEVCNTR22_EL0}}, x12 +# CHECK: msr {{pmevcntr23_el0|PMEVCNTR23_EL0}}, x12 +# CHECK: msr {{pmevcntr24_el0|PMEVCNTR24_EL0}}, x12 +# CHECK: msr {{pmevcntr25_el0|PMEVCNTR25_EL0}}, x12 +# CHECK: msr {{pmevcntr26_el0|PMEVCNTR26_EL0}}, x12 +# CHECK: msr {{pmevcntr27_el0|PMEVCNTR27_EL0}}, x12 +# CHECK: msr {{pmevcntr28_el0|PMEVCNTR28_EL0}}, x12 +# CHECK: msr {{pmevcntr29_el0|PMEVCNTR29_EL0}}, x12 +# CHECK: msr {{pmevcntr30_el0|PMEVCNTR30_EL0}}, x12 +# CHECK: msr {{pmccfiltr_el0|PMCCFILTR_EL0}}, x12 +# CHECK: msr {{pmevtyper0_el0|PMEVTYPER0_EL0}}, x12 +# CHECK: msr {{pmevtyper1_el0|PMEVTYPER1_EL0}}, x12 +# CHECK: msr {{pmevtyper2_el0|PMEVTYPER2_EL0}}, x12 +# CHECK: msr {{pmevtyper3_el0|PMEVTYPER3_EL0}}, x12 +# CHECK: msr {{pmevtyper4_el0|PMEVTYPER4_EL0}}, x12 +# CHECK: msr {{pmevtyper5_el0|PMEVTYPER5_EL0}}, x12 +# CHECK: msr {{pmevtyper6_el0|PMEVTYPER6_EL0}}, x12 +# CHECK: msr {{pmevtyper7_el0|PMEVTYPER7_EL0}}, x12 +# CHECK: msr {{pmevtyper8_el0|PMEVTYPER8_EL0}}, x12 +# CHECK: msr {{pmevtyper9_el0|PMEVTYPER9_EL0}}, x12 +# CHECK: msr {{pmevtyper10_el0|PMEVTYPER10_EL0}}, x12 +# CHECK: msr {{pmevtyper11_el0|PMEVTYPER11_EL0}}, x12 +# CHECK: msr {{pmevtyper12_el0|PMEVTYPER12_EL0}}, x12 +# CHECK: msr {{pmevtyper13_el0|PMEVTYPER13_EL0}}, x12 +# CHECK: msr {{pmevtyper14_el0|PMEVTYPER14_EL0}}, x12 +# CHECK: msr {{pmevtyper15_el0|PMEVTYPER15_EL0}}, x12 +# CHECK: msr {{pmevtyper16_el0|PMEVTYPER16_EL0}}, x12 +# CHECK: msr {{pmevtyper17_el0|PMEVTYPER17_EL0}}, x12 +# CHECK: msr {{pmevtyper18_el0|PMEVTYPER18_EL0}}, x12 +# CHECK: msr {{pmevtyper19_el0|PMEVTYPER19_EL0}}, x12 +# CHECK: msr {{pmevtyper20_el0|PMEVTYPER20_EL0}}, x12 +# CHECK: msr {{pmevtyper21_el0|PMEVTYPER21_EL0}}, x12 +# CHECK: msr {{pmevtyper22_el0|PMEVTYPER22_EL0}}, x12 +# CHECK: msr {{pmevtyper23_el0|PMEVTYPER23_EL0}}, x12 +# CHECK: msr {{pmevtyper24_el0|PMEVTYPER24_EL0}}, x12 +# CHECK: msr {{pmevtyper25_el0|PMEVTYPER25_EL0}}, x12 +# CHECK: msr {{pmevtyper26_el0|PMEVTYPER26_EL0}}, x12 +# CHECK: msr {{pmevtyper27_el0|PMEVTYPER27_EL0}}, x12 +# CHECK: msr {{pmevtyper28_el0|PMEVTYPER28_EL0}}, x12 +# CHECK: msr {{pmevtyper29_el0|PMEVTYPER29_EL0}}, x12 +# CHECK: msr {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12 +# CHECK: mrs x9, {{teecr32_el1|TEECR32_EL1}} +# CHECK: mrs x9, {{osdtrrx_el1|OSDTRRX_EL1}} +# CHECK: mrs x9, {{mdccsr_el0|MDCCSR_EL0}} +# CHECK: mrs x9, {{mdccint_el1|MDCCINT_EL1}} +# CHECK: mrs x9, {{mdscr_el1|MDSCR_EL1}} +# CHECK: mrs x9, {{osdtrtx_el1|OSDTRTX_EL1}} +# CHECK: mrs x9, {{dbgdtr_el0|DBGDTR_EL0}} +# CHECK: mrs x9, {{dbgdtrrx_el0|DBGDTRRX_EL0}} +# CHECK: mrs x9, {{oseccr_el1|OSECCR_EL1}} +# CHECK: mrs x9, {{dbgvcr32_el2|DBGVCR32_EL2}} +# CHECK: mrs x9, {{dbgbvr0_el1|DBGBVR0_EL1}} +# CHECK: mrs x9, {{dbgbvr1_el1|DBGBVR1_EL1}} +# CHECK: mrs x9, {{dbgbvr2_el1|DBGBVR2_EL1}} +# CHECK: mrs x9, {{dbgbvr3_el1|DBGBVR3_EL1}} +# CHECK: mrs x9, {{dbgbvr4_el1|DBGBVR4_EL1}} +# CHECK: mrs x9, {{dbgbvr5_el1|DBGBVR5_EL1}} +# CHECK: mrs x9, {{dbgbvr6_el1|DBGBVR6_EL1}} +# CHECK: mrs x9, {{dbgbvr7_el1|DBGBVR7_EL1}} +# CHECK: mrs x9, {{dbgbvr8_el1|DBGBVR8_EL1}} +# CHECK: mrs x9, {{dbgbvr9_el1|DBGBVR9_EL1}} +# CHECK: mrs x9, {{dbgbvr10_el1|DBGBVR10_EL1}} +# CHECK: mrs x9, {{dbgbvr11_el1|DBGBVR11_EL1}} +# CHECK: mrs x9, {{dbgbvr12_el1|DBGBVR12_EL1}} +# CHECK: mrs x9, {{dbgbvr13_el1|DBGBVR13_EL1}} +# CHECK: mrs x9, {{dbgbvr14_el1|DBGBVR14_EL1}} +# CHECK: mrs x9, {{dbgbvr15_el1|DBGBVR15_EL1}} +# CHECK: mrs x9, {{dbgbcr0_el1|DBGBCR0_EL1}} +# CHECK: mrs x9, {{dbgbcr1_el1|DBGBCR1_EL1}} +# CHECK: mrs x9, {{dbgbcr2_el1|DBGBCR2_EL1}} +# CHECK: mrs x9, {{dbgbcr3_el1|DBGBCR3_EL1}} +# CHECK: mrs x9, {{dbgbcr4_el1|DBGBCR4_EL1}} +# CHECK: mrs x9, {{dbgbcr5_el1|DBGBCR5_EL1}} +# CHECK: mrs x9, {{dbgbcr6_el1|DBGBCR6_EL1}} +# CHECK: mrs x9, {{dbgbcr7_el1|DBGBCR7_EL1}} +# CHECK: mrs x9, {{dbgbcr8_el1|DBGBCR8_EL1}} +# CHECK: mrs x9, {{dbgbcr9_el1|DBGBCR9_EL1}} +# CHECK: mrs x9, {{dbgbcr10_el1|DBGBCR10_EL1}} +# CHECK: mrs x9, {{dbgbcr11_el1|DBGBCR11_EL1}} +# CHECK: mrs x9, {{dbgbcr12_el1|DBGBCR12_EL1}} +# CHECK: mrs x9, {{dbgbcr13_el1|DBGBCR13_EL1}} +# CHECK: mrs x9, {{dbgbcr14_el1|DBGBCR14_EL1}} +# CHECK: mrs x9, {{dbgbcr15_el1|DBGBCR15_EL1}} +# CHECK: mrs x9, {{dbgwvr0_el1|DBGWVR0_EL1}} +# CHECK: mrs x9, {{dbgwvr1_el1|DBGWVR1_EL1}} +# CHECK: mrs x9, {{dbgwvr2_el1|DBGWVR2_EL1}} +# CHECK: mrs x9, {{dbgwvr3_el1|DBGWVR3_EL1}} +# CHECK: mrs x9, {{dbgwvr4_el1|DBGWVR4_EL1}} +# CHECK: mrs x9, {{dbgwvr5_el1|DBGWVR5_EL1}} +# CHECK: mrs x9, {{dbgwvr6_el1|DBGWVR6_EL1}} +# CHECK: mrs x9, {{dbgwvr7_el1|DBGWVR7_EL1}} +# CHECK: mrs x9, {{dbgwvr8_el1|DBGWVR8_EL1}} +# CHECK: mrs x9, {{dbgwvr9_el1|DBGWVR9_EL1}} +# CHECK: mrs x9, {{dbgwvr10_el1|DBGWVR10_EL1}} +# CHECK: mrs x9, {{dbgwvr11_el1|DBGWVR11_EL1}} +# CHECK: mrs x9, {{dbgwvr12_el1|DBGWVR12_EL1}} +# CHECK: mrs x9, {{dbgwvr13_el1|DBGWVR13_EL1}} +# CHECK: mrs x9, {{dbgwvr14_el1|DBGWVR14_EL1}} +# CHECK: mrs x9, {{dbgwvr15_el1|DBGWVR15_EL1}} +# CHECK: mrs x9, {{dbgwcr0_el1|DBGWCR0_EL1}} +# CHECK: mrs x9, {{dbgwcr1_el1|DBGWCR1_EL1}} +# CHECK: mrs x9, {{dbgwcr2_el1|DBGWCR2_EL1}} +# CHECK: mrs x9, {{dbgwcr3_el1|DBGWCR3_EL1}} +# CHECK: mrs x9, {{dbgwcr4_el1|DBGWCR4_EL1}} +# CHECK: mrs x9, {{dbgwcr5_el1|DBGWCR5_EL1}} +# CHECK: mrs x9, {{dbgwcr6_el1|DBGWCR6_EL1}} +# CHECK: mrs x9, {{dbgwcr7_el1|DBGWCR7_EL1}} +# CHECK: mrs x9, {{dbgwcr8_el1|DBGWCR8_EL1}} +# CHECK: mrs x9, {{dbgwcr9_el1|DBGWCR9_EL1}} +# CHECK: mrs x9, {{dbgwcr10_el1|DBGWCR10_EL1}} +# CHECK: mrs x9, {{dbgwcr11_el1|DBGWCR11_EL1}} +# CHECK: mrs x9, {{dbgwcr12_el1|DBGWCR12_EL1}} +# CHECK: mrs x9, {{dbgwcr13_el1|DBGWCR13_EL1}} +# CHECK: mrs x9, {{dbgwcr14_el1|DBGWCR14_EL1}} +# CHECK: mrs x9, {{dbgwcr15_el1|DBGWCR15_EL1}} +# CHECK: mrs x9, {{mdrar_el1|MDRAR_EL1}} +# CHECK: mrs x9, {{teehbr32_el1|TEEHBR32_EL1}} +# CHECK: mrs x9, {{oslsr_el1|OSLSR_EL1}} +# CHECK: mrs x9, {{osdlr_el1|OSDLR_EL1}} +# CHECK: mrs x9, {{dbgprcr_el1|DBGPRCR_EL1}} +# CHECK: mrs x9, {{dbgclaimset_el1|DBGCLAIMSET_EL1}} +# CHECK: mrs x9, {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}} +# CHECK: mrs x9, {{dbgauthstatus_el1|DBGAUTHSTATUS_EL1}} +# CHECK: mrs x9, {{midr_el1|MIDR_EL1}} +# CHECK: mrs x9, {{ccsidr_el1|CCSIDR_EL1}} +# CHECK: mrs x9, {{csselr_el1|CSSELR_EL1}} +# CHECK: mrs x9, {{vpidr_el2|VPIDR_EL2}} +# CHECK: mrs x9, {{clidr_el1|CLIDR_EL1}} +# CHECK: mrs x9, {{ctr_el0|CTR_EL0}} +# CHECK: mrs x9, {{mpidr_el1|MPIDR_EL1}} +# CHECK: mrs x9, {{vmpidr_el2|VMPIDR_EL2}} +# CHECK: mrs x9, {{revidr_el1|REVIDR_EL1}} +# CHECK: mrs x9, {{aidr_el1|AIDR_EL1}} +# CHECK: mrs x9, {{dczid_el0|DCZID_EL0}} +# CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}} +# CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}} +# CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}} +# CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}} +# CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}} +# CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}} +# CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}} +# CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}} +# CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}} +# CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}} +# CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}} +# CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}} +# CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}} +# CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}} +# CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}} +# CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}} +# CHECK: mrs x9, {{mvfr2_el1|MVFR2_EL1}} +# CHECK: mrs x9, {{id_aa64pfr0_el1|ID_AA64PFR0_EL1}} +# CHECK: mrs x9, {{id_aa64pfr1_el1|ID_AA64PFR1_EL1}} +# CHECK: mrs x9, {{id_aa64dfr0_el1|ID_AA64DFR0_EL1}} +# CHECK: mrs x9, {{id_aa64dfr1_el1|ID_AA64DFR1_EL1}} +# CHECK: mrs x9, {{id_aa64afr0_el1|ID_AA64AFR0_EL1}} +# CHECK: mrs x9, {{id_aa64afr1_el1|ID_AA64AFR1_EL1}} +# CHECK: mrs x9, {{id_aa64isar0_el1|ID_AA64ISAR0_EL1}} +# CHECK: mrs x9, {{id_aa64isar1_el1|ID_AA64ISAR1_EL1}} +# CHECK: mrs x9, {{id_aa64mmfr0_el1|ID_AA64MMFR0_EL1}} +# CHECK: mrs x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}} +# CHECK: mrs x9, {{sctlr_el1|SCTLR_EL1}} +# CHECK: mrs x9, {{sctlr_el2|SCTLR_EL2}} +# CHECK: mrs x9, {{sctlr_el3|SCTLR_EL3}} +# CHECK: mrs x9, {{actlr_el1|ACTLR_EL1}} +# CHECK: mrs x9, {{actlr_el2|ACTLR_EL2}} +# CHECK: mrs x9, {{actlr_el3|ACTLR_EL3}} +# CHECK: mrs x9, {{cpacr_el1|CPACR_EL1}} +# CHECK: mrs x9, {{hcr_el2|HCR_EL2}} +# CHECK: mrs x9, {{scr_el3|SCR_EL3}} +# CHECK: mrs x9, {{mdcr_el2|MDCR_EL2}} +# CHECK: mrs x9, {{sder32_el3|SDER32_EL3}} +# CHECK: mrs x9, {{cptr_el2|CPTR_EL2}} +# CHECK: mrs x9, {{cptr_el3|CPTR_EL3}} +# CHECK: mrs x9, {{hstr_el2|HSTR_EL2}} +# CHECK: mrs x9, {{hacr_el2|HACR_EL2}} +# CHECK: mrs x9, {{mdcr_el3|MDCR_EL3}} +# CHECK: mrs x9, {{ttbr0_el1|TTBR0_EL1}} +# CHECK: mrs x9, {{ttbr0_el2|TTBR0_EL2}} +# CHECK: mrs x9, {{ttbr0_el3|TTBR0_EL3}} +# CHECK: mrs x9, {{ttbr1_el1|TTBR1_EL1}} +# CHECK: mrs x9, {{tcr_el1|TCR_EL1}} +# CHECK: mrs x9, {{tcr_el2|TCR_EL2}} +# CHECK: mrs x9, {{tcr_el3|TCR_EL3}} +# CHECK: mrs x9, {{vttbr_el2|VTTBR_EL2}} +# CHECK: mrs x9, {{vtcr_el2|VTCR_EL2}} +# CHECK: mrs x9, {{dacr32_el2|DACR32_EL2}} +# CHECK: mrs x9, {{spsr_el1|SPSR_EL1}} +# CHECK: mrs x9, {{spsr_el2|SPSR_EL2}} +# CHECK: mrs x9, {{spsr_el3|SPSR_EL3}} +# CHECK: mrs x9, {{elr_el1|ELR_EL1}} +# CHECK: mrs x9, {{elr_el2|ELR_EL2}} +# CHECK: mrs x9, {{elr_el3|ELR_EL3}} +# CHECK: mrs x9, {{sp_el0|SP_EL0}} +# CHECK: mrs x9, {{sp_el1|SP_EL1}} +# CHECK: mrs x9, {{sp_el2|SP_EL2}} +# CHECK: mrs x9, {{spsel|SPSEL}} +# CHECK: mrs x9, {{nzcv|NZCV}} +# CHECK: mrs x9, {{daif|DAIF}} +# CHECK: mrs x9, {{currentel|CURRENTEL}} +# CHECK: mrs x9, {{spsr_irq|SPSR_IRQ}} +# CHECK: mrs x9, {{spsr_abt|SPSR_ABT}} +# CHECK: mrs x9, {{spsr_und|SPSR_UND}} +# CHECK: mrs x9, {{spsr_fiq|SPSR_FIQ}} +# CHECK: mrs x9, {{fpcr|FPCR}} +# CHECK: mrs x9, {{fpsr|FPSR}} +# CHECK: mrs x9, {{dspsr_el0|DSPSR_EL0}} +# CHECK: mrs x9, {{dlr_el0|DLR_EL0}} +# CHECK: mrs x9, {{ifsr32_el2|IFSR32_EL2}} +# CHECK: mrs x9, {{afsr0_el1|AFSR0_EL1}} +# CHECK: mrs x9, {{afsr0_el2|AFSR0_EL2}} +# CHECK: mrs x9, {{afsr0_el3|AFSR0_EL3}} +# CHECK: mrs x9, {{afsr1_el1|AFSR1_EL1}} +# CHECK: mrs x9, {{afsr1_el2|AFSR1_EL2}} +# CHECK: mrs x9, {{afsr1_el3|AFSR1_EL3}} +# CHECK: mrs x9, {{esr_el1|ESR_EL1}} +# CHECK: mrs x9, {{esr_el2|ESR_EL2}} +# CHECK: mrs x9, {{esr_el3|ESR_EL3}} +# CHECK: mrs x9, {{fpexc32_el2|FPEXC32_EL2}} +# CHECK: mrs x9, {{far_el1|FAR_EL1}} +# CHECK: mrs x9, {{far_el2|FAR_EL2}} +# CHECK: mrs x9, {{far_el3|FAR_EL3}} +# CHECK: mrs x9, {{hpfar_el2|HPFAR_EL2}} +# CHECK: mrs x9, {{par_el1|PAR_EL1}} +# CHECK: mrs x9, {{pmcr_el0|PMCR_EL0}} +# CHECK: mrs x9, {{pmcntenset_el0|PMCNTENSET_EL0}} +# CHECK: mrs x9, {{pmcntenclr_el0|PMCNTENCLR_EL0}} +# CHECK: mrs x9, {{pmovsclr_el0|PMOVSCLR_EL0}} +# CHECK: mrs x9, {{pmselr_el0|PMSELR_EL0}} +# CHECK: mrs x9, {{pmceid0_el0|PMCEID0_EL0}} +# CHECK: mrs x9, {{pmceid1_el0|PMCEID1_EL0}} +# CHECK: mrs x9, {{pmccntr_el0|PMCCNTR_EL0}} +# CHECK: mrs x9, {{pmxevtyper_el0|PMXEVTYPER_EL0}} +# CHECK: mrs x9, {{pmxevcntr_el0|PMXEVCNTR_EL0}} +# CHECK: mrs x9, {{pmuserenr_el0|PMUSERENR_EL0}} +# CHECK: mrs x9, {{pmintenset_el1|PMINTENSET_EL1}} +# CHECK: mrs x9, {{pmintenclr_el1|PMINTENCLR_EL1}} +# CHECK: mrs x9, {{pmovsset_el0|PMOVSSET_EL0}} +# CHECK: mrs x9, {{mair_el1|MAIR_EL1}} +# CHECK: mrs x9, {{mair_el2|MAIR_EL2}} +# CHECK: mrs x9, {{mair_el3|MAIR_EL3}} +# CHECK: mrs x9, {{amair_el1|AMAIR_EL1}} +# CHECK: mrs x9, {{amair_el2|AMAIR_EL2}} +# CHECK: mrs x9, {{amair_el3|AMAIR_EL3}} +# CHECK: mrs x9, {{vbar_el1|VBAR_EL1}} +# CHECK: mrs x9, {{vbar_el2|VBAR_EL2}} +# CHECK: mrs x9, {{vbar_el3|VBAR_EL3}} +# CHECK: mrs x9, {{rvbar_el1|RVBAR_EL1}} +# CHECK: mrs x9, {{rvbar_el2|RVBAR_EL2}} +# CHECK: mrs x9, {{rvbar_el3|RVBAR_EL3}} +# CHECK: mrs x9, {{rmr_el1|RMR_EL1}} +# CHECK: mrs x9, {{rmr_el2|RMR_EL2}} +# CHECK: mrs x9, {{rmr_el3|RMR_EL3}} +# CHECK: mrs x9, {{isr_el1|ISR_EL1}} +# CHECK: mrs x9, {{contextidr_el1|CONTEXTIDR_EL1}} +# CHECK: mrs x9, {{tpidr_el0|TPIDR_EL0}} +# CHECK: mrs x9, {{tpidr_el2|TPIDR_EL2}} +# CHECK: mrs x9, {{tpidr_el3|TPIDR_EL3}} +# CHECK: mrs x9, {{tpidrro_el0|TPIDRRO_EL0}} +# CHECK: mrs x9, {{tpidr_el1|TPIDR_EL1}} +# CHECK: mrs x9, {{cntfrq_el0|CNTFRQ_EL0}} +# CHECK: mrs x9, {{cntpct_el0|CNTPCT_EL0}} +# CHECK: mrs x9, {{cntvct_el0|CNTVCT_EL0}} +# CHECK: mrs x9, {{cntvoff_el2|CNTVOFF_EL2}} +# CHECK: mrs x9, {{cntkctl_el1|CNTKCTL_EL1}} +# CHECK: mrs x9, {{cnthctl_el2|CNTHCTL_EL2}} +# CHECK: mrs x9, {{cntp_tval_el0|CNTP_TVAL_EL0}} +# CHECK: mrs x9, {{cnthp_tval_el2|CNTHP_TVAL_EL2}} +# CHECK: mrs x9, {{cntps_tval_el1|CNTPS_TVAL_EL1}} +# CHECK: mrs x9, {{cntp_ctl_el0|CNTP_CTL_EL0}} +# CHECK: mrs x9, {{cnthp_ctl_el2|CNTHP_CTL_EL2}} +# CHECK: mrs x9, {{cntps_ctl_el1|CNTPS_CTL_EL1}} +# CHECK: mrs x9, {{cntp_cval_el0|CNTP_CVAL_EL0}} +# CHECK: mrs x9, {{cnthp_cval_el2|CNTHP_CVAL_EL2}} +# CHECK: mrs x9, {{cntps_cval_el1|CNTPS_CVAL_EL1}} +# CHECK: mrs x9, {{cntv_tval_el0|CNTV_TVAL_EL0}} +# CHECK: mrs x9, {{cntv_ctl_el0|CNTV_CTL_EL0}} +# CHECK: mrs x9, {{cntv_cval_el0|CNTV_CVAL_EL0}} +# CHECK: mrs x9, {{pmevcntr0_el0|PMEVCNTR0_EL0}} +# CHECK: mrs x9, {{pmevcntr1_el0|PMEVCNTR1_EL0}} +# CHECK: mrs x9, {{pmevcntr2_el0|PMEVCNTR2_EL0}} +# CHECK: mrs x9, {{pmevcntr3_el0|PMEVCNTR3_EL0}} +# CHECK: mrs x9, {{pmevcntr4_el0|PMEVCNTR4_EL0}} +# CHECK: mrs x9, {{pmevcntr5_el0|PMEVCNTR5_EL0}} +# CHECK: mrs x9, {{pmevcntr6_el0|PMEVCNTR6_EL0}} +# CHECK: mrs x9, {{pmevcntr7_el0|PMEVCNTR7_EL0}} +# CHECK: mrs x9, {{pmevcntr8_el0|PMEVCNTR8_EL0}} +# CHECK: mrs x9, {{pmevcntr9_el0|PMEVCNTR9_EL0}} +# CHECK: mrs x9, {{pmevcntr10_el0|PMEVCNTR10_EL0}} +# CHECK: mrs x9, {{pmevcntr11_el0|PMEVCNTR11_EL0}} +# CHECK: mrs x9, {{pmevcntr12_el0|PMEVCNTR12_EL0}} +# CHECK: mrs x9, {{pmevcntr13_el0|PMEVCNTR13_EL0}} +# CHECK: mrs x9, {{pmevcntr14_el0|PMEVCNTR14_EL0}} +# CHECK: mrs x9, {{pmevcntr15_el0|PMEVCNTR15_EL0}} +# CHECK: mrs x9, {{pmevcntr16_el0|PMEVCNTR16_EL0}} +# CHECK: mrs x9, {{pmevcntr17_el0|PMEVCNTR17_EL0}} +# CHECK: mrs x9, {{pmevcntr18_el0|PMEVCNTR18_EL0}} +# CHECK: mrs x9, {{pmevcntr19_el0|PMEVCNTR19_EL0}} +# CHECK: mrs x9, {{pmevcntr20_el0|PMEVCNTR20_EL0}} +# CHECK: mrs x9, {{pmevcntr21_el0|PMEVCNTR21_EL0}} +# CHECK: mrs x9, {{pmevcntr22_el0|PMEVCNTR22_EL0}} +# CHECK: mrs x9, {{pmevcntr23_el0|PMEVCNTR23_EL0}} +# CHECK: mrs x9, {{pmevcntr24_el0|PMEVCNTR24_EL0}} +# CHECK: mrs x9, {{pmevcntr25_el0|PMEVCNTR25_EL0}} +# CHECK: mrs x9, {{pmevcntr26_el0|PMEVCNTR26_EL0}} +# CHECK: mrs x9, {{pmevcntr27_el0|PMEVCNTR27_EL0}} +# CHECK: mrs x9, {{pmevcntr28_el0|PMEVCNTR28_EL0}} +# CHECK: mrs x9, {{pmevcntr29_el0|PMEVCNTR29_EL0}} +# CHECK: mrs x9, {{pmevcntr30_el0|PMEVCNTR30_EL0}} +# CHECK: mrs x9, {{pmccfiltr_el0|PMCCFILTR_EL0}} +# CHECK: mrs x9, {{pmevtyper0_el0|PMEVTYPER0_EL0}} +# CHECK: mrs x9, {{pmevtyper1_el0|PMEVTYPER1_EL0}} +# CHECK: mrs x9, {{pmevtyper2_el0|PMEVTYPER2_EL0}} +# CHECK: mrs x9, {{pmevtyper3_el0|PMEVTYPER3_EL0}} +# CHECK: mrs x9, {{pmevtyper4_el0|PMEVTYPER4_EL0}} +# CHECK: mrs x9, {{pmevtyper5_el0|PMEVTYPER5_EL0}} +# CHECK: mrs x9, {{pmevtyper6_el0|PMEVTYPER6_EL0}} +# CHECK: mrs x9, {{pmevtyper7_el0|PMEVTYPER7_EL0}} +# CHECK: mrs x9, {{pmevtyper8_el0|PMEVTYPER8_EL0}} +# CHECK: mrs x9, {{pmevtyper9_el0|PMEVTYPER9_EL0}} +# CHECK: mrs x9, {{pmevtyper10_el0|PMEVTYPER10_EL0}} +# CHECK: mrs x9, {{pmevtyper11_el0|PMEVTYPER11_EL0}} +# CHECK: mrs x9, {{pmevtyper12_el0|PMEVTYPER12_EL0}} +# CHECK: mrs x9, {{pmevtyper13_el0|PMEVTYPER13_EL0}} +# CHECK: mrs x9, {{pmevtyper14_el0|PMEVTYPER14_EL0}} +# CHECK: mrs x9, {{pmevtyper15_el0|PMEVTYPER15_EL0}} +# CHECK: mrs x9, {{pmevtyper16_el0|PMEVTYPER16_EL0}} +# CHECK: mrs x9, {{pmevtyper17_el0|PMEVTYPER17_EL0}} +# CHECK: mrs x9, {{pmevtyper18_el0|PMEVTYPER18_EL0}} +# CHECK: mrs x9, {{pmevtyper19_el0|PMEVTYPER19_EL0}} +# CHECK: mrs x9, {{pmevtyper20_el0|PMEVTYPER20_EL0}} +# CHECK: mrs x9, {{pmevtyper21_el0|PMEVTYPER21_EL0}} +# CHECK: mrs x9, {{pmevtyper22_el0|PMEVTYPER22_EL0}} +# CHECK: mrs x9, {{pmevtyper23_el0|PMEVTYPER23_EL0}} +# CHECK: mrs x9, {{pmevtyper24_el0|PMEVTYPER24_EL0}} +# CHECK: mrs x9, {{pmevtyper25_el0|PMEVTYPER25_EL0}} +# CHECK: mrs x9, {{pmevtyper26_el0|PMEVTYPER26_EL0}} +# CHECK: mrs x9, {{pmevtyper27_el0|PMEVTYPER27_EL0}} +# CHECK: mrs x9, {{pmevtyper28_el0|PMEVTYPER28_EL0}} +# CHECK: mrs x9, {{pmevtyper29_el0|PMEVTYPER29_EL0}} +# CHECK: mrs x9, {{pmevtyper30_el0|PMEVTYPER30_EL0}} 0xc 0x0 0x12 0xd5 0x4c 0x0 0x10 0xd5 @@ -4147,10 +4148,10 @@ 0xa9 0xef 0x3b 0xd5 0xc9 0xef 0x3b 0xd5 -# CHECK: mrs x12, s3_7_c15_c1_5 -# CHECK: mrs x13, s3_2_c11_c15_7 -# CHECK: msr s3_0_c15_c0_0, x12 -# CHECK: msr s3_7_c11_c13_7, x5 +# CHECK: mrs x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}} +# CHECK: mrs x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}} +# CHECK: msr {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12 +# CHECK: msr {{s3_7_c11_c13_7|S3_7_C11_C13_7}}, x5 0xac 0xf1 0x3f 0xd5 0xed 0xbf 0x3a 0xd5 0x0c 0xf0 0x18 0xd5 diff --git a/test/MC/Disassembler/AArch64/basic-a64-undefined.txt b/test/MC/Disassembler/AArch64/basic-a64-undefined.txt index a17579c..968a454 100644 --- a/test/MC/Disassembler/AArch64/basic-a64-undefined.txt +++ b/test/MC/Disassembler/AArch64/basic-a64-undefined.txt @@ -1,43 +1,66 @@ -# These spawn another process so they're rather expensive. Not many. +# RUN: not llvm-mc -disassemble -triple=aarch64 %s 2> %t +# RUN: FileCheck %s < %t +# RUN: not llvm-mc -disassemble -triple=arm64 %s 2> %t +# RUN: FileCheck %s < %t # Instructions notionally in the add/sub (extended register) sheet, but with # invalid shift amount or "opt" field. -# RUN: echo "0x00 0x10 0xa0 0x0b" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x00 0x10 0x60 0x0b" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x00 0x14 0x20 0x0b" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0x00 0x10 0xa0 0x0b] +[0x00 0x10 0x60 0x0b] +[0x00 0x14 0x20 0x0b] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding # Instructions notionally in the add/sub (immediate) sheet, but with # invalid "shift" field. -# RUN: echo "0xdf 0x3 0x80 0x91" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0xed 0x8e 0xc4 0x31" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x62 0xfc 0xbf 0x11" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x3 0xff 0xff 0x91" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0xdf 0x3 0x80 0x91] +[0xed 0x8e 0xc4 0x31] +[0x62 0xfc 0xbf 0x11] +[0x3 0xff 0xff 0x91] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding # Instructions notionally in the load/store (unsigned immediate) sheet. # Only unallocated (int-register) variants are: opc=0b11, size=0b10, 0b11 -# RUN: echo "0xd7 0xfc 0xff 0xb9" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0xd7 0xfc 0xcf 0xf9" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0xd7 0xfc 0xff 0xb9] +[0xd7 0xfc 0xcf 0xf9] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding # Instructions notionally in the floating-point <-> fixed-point conversion # Scale field is 64-<imm> and <imm> should be 1-32 for a 32-bit int register. -# RUN: echo "0x23 0x01 0x18 0x1e" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x23 0x25 0x42 0x1e" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0x23 0x01 0x18 0x1e] +[0x23 0x25 0x42 0x1e] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding # Instructions notionally in the logical (shifted register) sheet, but with out # of range shift: w-registers can only have 0-31. -# RUN: echo "0x00 0x80 0x00 0x0a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0x00 0x80 0x00 0x0a] +# CHECK: invalid instruction encoding # Instructions notionally in the move wide (immediate) sheet, but with out # of range shift: w-registers can only have 0 or 16. -# RUN: echo "0x00 0x00 0xc0 0x12" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x12 0x34 0xe0 0x52" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s - -# Data-processing instructions are undefined when S=1 and for the 0b0000111 value in opcode:sf -# RUN: echo "0x00 0x00 0xc0 0x5f" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x56 0x0c 0xc0 0x5a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0x00 0x00 0xc0 0x12] +[0x12 0x34 0xe0 0x52] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding -# Data-processing instructions (2 source) are undefined for a value of 0001xx:0:x or 0011xx:0:x for opcode:S:sf -# RUN: echo "0x00 0x30 0xc1 0x1a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x00 0x10 0xc1 0x1a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +# Data-processing instructions are undefined when S=1 and for the 0b0000111 +# value in opcode:sf +[0x00 0x00 0xc0 0x5f] +[0x56 0x0c 0xc0 0x5a] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding +# Data-processing instructions (2 source) are undefined for a value of +# 0001xx:0:x or 0011xx:0:x for opcode:S:sf +[0x00 0x30 0xc1 0x1a] +[0x00 0x10 0xc1 0x1a] +# CHECK: invalid instruction encoding # CHECK: invalid instruction encoding + + diff --git a/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt b/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt index 5363863..2fccccb 100644 --- a/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt +++ b/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s #------------------------------------------------------------------------------ # Load-store exclusive diff --git a/test/MC/Disassembler/AArch64/gicv3-regs.txt b/test/MC/Disassembler/AArch64/gicv3-regs.txt index 4351f64..851e83d 100644 --- a/test/MC/Disassembler/AArch64/gicv3-regs.txt +++ b/test/MC/Disassembler/AArch64/gicv3-regs.txt @@ -1,222 +1,223 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-none-linux-gnu -disassemble < %s | FileCheck %s 0x8 0xcc 0x38 0xd5 -# CHECK: mrs x8, icc_iar1_el1 +# CHECK: mrs x8, {{icc_iar1_el1|ICC_IAR1_EL1}} 0x1a 0xc8 0x38 0xd5 -# CHECK: mrs x26, icc_iar0_el1 +# CHECK: mrs x26, {{icc_iar0_el1|ICC_IAR0_EL1}} 0x42 0xcc 0x38 0xd5 -# CHECK: mrs x2, icc_hppir1_el1 +# CHECK: mrs x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}} 0x51 0xc8 0x38 0xd5 -# CHECK: mrs x17, icc_hppir0_el1 +# CHECK: mrs x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}} 0x7d 0xcb 0x38 0xd5 -# CHECK: mrs x29, icc_rpr_el1 +# CHECK: mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}} 0x24 0xcb 0x3c 0xd5 -# CHECK: mrs x4, ich_vtr_el2 +# CHECK: mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}} 0x78 0xcb 0x3c 0xd5 -# CHECK: mrs x24, ich_eisr_el2 +# CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}} 0xa9 0xcb 0x3c 0xd5 -# CHECK: mrs x9, ich_elsr_el2 +# CHECK: mrs x9, {{ich_elsr_el2|ICH_ELSR_EL2}} 0x78 0xcc 0x38 0xd5 -# CHECK: mrs x24, icc_bpr1_el1 +# CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}} 0x6e 0xc8 0x38 0xd5 -# CHECK: mrs x14, icc_bpr0_el1 +# CHECK: mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}} 0x13 0x46 0x38 0xd5 -# CHECK: mrs x19, icc_pmr_el1 +# CHECK: mrs x19, {{icc_pmr_el1|ICC_PMR_EL1}} 0x97 0xcc 0x38 0xd5 -# CHECK: mrs x23, icc_ctlr_el1 +# CHECK: mrs x23, {{icc_ctlr_el1|ICC_CTLR_EL1}} 0x94 0xcc 0x3e 0xd5 -# CHECK: mrs x20, icc_ctlr_el3 +# CHECK: mrs x20, {{icc_ctlr_el3|ICC_CTLR_EL3}} 0xbc 0xcc 0x38 0xd5 -# CHECK: mrs x28, icc_sre_el1 +# CHECK: mrs x28, {{icc_sre_el1|ICC_SRE_EL1}} 0xb9 0xc9 0x3c 0xd5 -# CHECK: mrs x25, icc_sre_el2 +# CHECK: mrs x25, {{icc_sre_el2|ICC_SRE_EL2}} 0xa8 0xcc 0x3e 0xd5 -# CHECK: mrs x8, icc_sre_el3 +# CHECK: mrs x8, {{icc_sre_el3|ICC_SRE_EL3}} 0xd6 0xcc 0x38 0xd5 -# CHECK: mrs x22, icc_igrpen0_el1 +# CHECK: mrs x22, {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}} 0xe5 0xcc 0x38 0xd5 -# CHECK: mrs x5, icc_igrpen1_el1 +# CHECK: mrs x5, {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}} 0xe7 0xcc 0x3e 0xd5 -# CHECK: mrs x7, icc_igrpen1_el3 +# CHECK: mrs x7, {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}} 0x16 0xcd 0x38 0xd5 -# CHECK: mrs x22, icc_seien_el1 +# CHECK: mrs x22, {{icc_seien_el1|ICC_SEIEN_EL1}} 0x84 0xc8 0x38 0xd5 -# CHECK: mrs x4, icc_ap0r0_el1 +# CHECK: mrs x4, {{icc_ap0r0_el1|ICC_AP0R0_EL1}} 0xab 0xc8 0x38 0xd5 -# CHECK: mrs x11, icc_ap0r1_el1 +# CHECK: mrs x11, {{icc_ap0r1_el1|ICC_AP0R1_EL1}} 0xdb 0xc8 0x38 0xd5 -# CHECK: mrs x27, icc_ap0r2_el1 +# CHECK: mrs x27, {{icc_ap0r2_el1|ICC_AP0R2_EL1}} 0xf5 0xc8 0x38 0xd5 -# CHECK: mrs x21, icc_ap0r3_el1 +# CHECK: mrs x21, {{icc_ap0r3_el1|ICC_AP0R3_EL1}} 0x2 0xc9 0x38 0xd5 -# CHECK: mrs x2, icc_ap1r0_el1 +# CHECK: mrs x2, {{icc_ap1r0_el1|ICC_AP1R0_EL1}} 0x35 0xc9 0x38 0xd5 -# CHECK: mrs x21, icc_ap1r1_el1 +# CHECK: mrs x21, {{icc_ap1r1_el1|ICC_AP1R1_EL1}} 0x4a 0xc9 0x38 0xd5 -# CHECK: mrs x10, icc_ap1r2_el1 +# CHECK: mrs x10, {{icc_ap1r2_el1|ICC_AP1R2_EL1}} 0x7b 0xc9 0x38 0xd5 -# CHECK: mrs x27, icc_ap1r3_el1 +# CHECK: mrs x27, {{icc_ap1r3_el1|ICC_AP1R3_EL1}} 0x14 0xc8 0x3c 0xd5 -# CHECK: mrs x20, ich_ap0r0_el2 +# CHECK: mrs x20, {{ich_ap0r0_el2|ICH_AP0R0_EL2}} 0x35 0xc8 0x3c 0xd5 -# CHECK: mrs x21, ich_ap0r1_el2 +# CHECK: mrs x21, {{ich_ap0r1_el2|ICH_AP0R1_EL2}} 0x45 0xc8 0x3c 0xd5 -# CHECK: mrs x5, ich_ap0r2_el2 +# CHECK: mrs x5, {{ich_ap0r2_el2|ICH_AP0R2_EL2}} 0x64 0xc8 0x3c 0xd5 -# CHECK: mrs x4, ich_ap0r3_el2 +# CHECK: mrs x4, {{ich_ap0r3_el2|ICH_AP0R3_EL2}} 0xf 0xc9 0x3c 0xd5 -# CHECK: mrs x15, ich_ap1r0_el2 +# CHECK: mrs x15, {{ich_ap1r0_el2|ICH_AP1R0_EL2}} 0x2c 0xc9 0x3c 0xd5 -# CHECK: mrs x12, ich_ap1r1_el2 +# CHECK: mrs x12, {{ich_ap1r1_el2|ICH_AP1R1_EL2}} 0x5b 0xc9 0x3c 0xd5 -# CHECK: mrs x27, ich_ap1r2_el2 +# CHECK: mrs x27, {{ich_ap1r2_el2|ICH_AP1R2_EL2}} 0x74 0xc9 0x3c 0xd5 -# CHECK: mrs x20, ich_ap1r3_el2 +# CHECK: mrs x20, {{ich_ap1r3_el2|ICH_AP1R3_EL2}} 0xa 0xcb 0x3c 0xd5 -# CHECK: mrs x10, ich_hcr_el2 +# CHECK: mrs x10, {{ich_hcr_el2|ICH_HCR_EL2}} 0x5b 0xcb 0x3c 0xd5 -# CHECK: mrs x27, ich_misr_el2 +# CHECK: mrs x27, {{ich_misr_el2|ICH_MISR_EL2}} 0xe6 0xcb 0x3c 0xd5 -# CHECK: mrs x6, ich_vmcr_el2 +# CHECK: mrs x6, {{ich_vmcr_el2|ICH_VMCR_EL2}} 0x93 0xc9 0x3c 0xd5 -# CHECK: mrs x19, ich_vseir_el2 +# CHECK: mrs x19, {{ich_vseir_el2|ICH_VSEIR_EL2}} 0x3 0xcc 0x3c 0xd5 -# CHECK: mrs x3, ich_lr0_el2 +# CHECK: mrs x3, {{ich_lr0_el2|ICH_LR0_EL2}} 0x21 0xcc 0x3c 0xd5 -# CHECK: mrs x1, ich_lr1_el2 +# CHECK: mrs x1, {{ich_lr1_el2|ICH_LR1_EL2}} 0x56 0xcc 0x3c 0xd5 -# CHECK: mrs x22, ich_lr2_el2 +# CHECK: mrs x22, {{ich_lr2_el2|ICH_LR2_EL2}} 0x75 0xcc 0x3c 0xd5 -# CHECK: mrs x21, ich_lr3_el2 +# CHECK: mrs x21, {{ich_lr3_el2|ICH_LR3_EL2}} 0x86 0xcc 0x3c 0xd5 -# CHECK: mrs x6, ich_lr4_el2 +# CHECK: mrs x6, {{ich_lr4_el2|ICH_LR4_EL2}} 0xaa 0xcc 0x3c 0xd5 -# CHECK: mrs x10, ich_lr5_el2 +# CHECK: mrs x10, {{ich_lr5_el2|ICH_LR5_EL2}} 0xcb 0xcc 0x3c 0xd5 -# CHECK: mrs x11, ich_lr6_el2 +# CHECK: mrs x11, {{ich_lr6_el2|ICH_LR6_EL2}} 0xec 0xcc 0x3c 0xd5 -# CHECK: mrs x12, ich_lr7_el2 +# CHECK: mrs x12, {{ich_lr7_el2|ICH_LR7_EL2}} 0x0 0xcd 0x3c 0xd5 -# CHECK: mrs x0, ich_lr8_el2 +# CHECK: mrs x0, {{ich_lr8_el2|ICH_LR8_EL2}} 0x35 0xcd 0x3c 0xd5 -# CHECK: mrs x21, ich_lr9_el2 +# CHECK: mrs x21, {{ich_lr9_el2|ICH_LR9_EL2}} 0x4d 0xcd 0x3c 0xd5 -# CHECK: mrs x13, ich_lr10_el2 +# CHECK: mrs x13, {{ich_lr10_el2|ICH_LR10_EL2}} 0x7a 0xcd 0x3c 0xd5 -# CHECK: mrs x26, ich_lr11_el2 +# CHECK: mrs x26, {{ich_lr11_el2|ICH_LR11_EL2}} 0x81 0xcd 0x3c 0xd5 -# CHECK: mrs x1, ich_lr12_el2 +# CHECK: mrs x1, {{ich_lr12_el2|ICH_LR12_EL2}} 0xa8 0xcd 0x3c 0xd5 -# CHECK: mrs x8, ich_lr13_el2 +# CHECK: mrs x8, {{ich_lr13_el2|ICH_LR13_EL2}} 0xc2 0xcd 0x3c 0xd5 -# CHECK: mrs x2, ich_lr14_el2 +# CHECK: mrs x2, {{ich_lr14_el2|ICH_LR14_EL2}} 0xe8 0xcd 0x3c 0xd5 -# CHECK: mrs x8, ich_lr15_el2 +# CHECK: mrs x8, {{ich_lr15_el2|ICH_LR15_EL2}} 0x3b 0xcc 0x18 0xd5 -# CHECK: msr icc_eoir1_el1, x27 +# CHECK: msr {{icc_eoir1_el1|ICC_EOIR1_EL1}}, x27 0x25 0xc8 0x18 0xd5 -# CHECK: msr icc_eoir0_el1, x5 +# CHECK: msr {{icc_eoir0_el1|ICC_EOIR0_EL1}}, x5 0x2d 0xcb 0x18 0xd5 -# CHECK: msr icc_dir_el1, x13 +# CHECK: msr {{icc_dir_el1|ICC_DIR_EL1}}, x13 0xb5 0xcb 0x18 0xd5 -# CHECK: msr icc_sgi1r_el1, x21 +# CHECK: msr {{icc_sgi1r_el1|ICC_SGI1R_EL1}}, x21 0xd9 0xcb 0x18 0xd5 -# CHECK: msr icc_asgi1r_el1, x25 +# CHECK: msr {{icc_asgi1r_el1|ICC_ASGI1R_EL1}}, x25 0xfc 0xcb 0x18 0xd5 -# CHECK: msr icc_sgi0r_el1, x28 +# CHECK: msr {{icc_sgi0r_el1|ICC_SGI0R_EL1}}, x28 0x67 0xcc 0x18 0xd5 -# CHECK: msr icc_bpr1_el1, x7 +# CHECK: msr {{icc_bpr1_el1|ICC_BPR1_EL1}}, x7 0x69 0xc8 0x18 0xd5 -# CHECK: msr icc_bpr0_el1, x9 +# CHECK: msr {{icc_bpr0_el1|ICC_BPR0_EL1}}, x9 0x1d 0x46 0x18 0xd5 -# CHECK: msr icc_pmr_el1, x29 +# CHECK: msr {{icc_pmr_el1|ICC_PMR_EL1}}, x29 0x98 0xcc 0x18 0xd5 -# CHECK: msr icc_ctlr_el1, x24 +# CHECK: msr {{icc_ctlr_el1|ICC_CTLR_EL1}}, x24 0x80 0xcc 0x1e 0xd5 -# CHECK: msr icc_ctlr_el3, x0 +# CHECK: msr {{icc_ctlr_el3|ICC_CTLR_EL3}}, x0 0xa2 0xcc 0x18 0xd5 -# CHECK: msr icc_sre_el1, x2 +# CHECK: msr {{icc_sre_el1|ICC_SRE_EL1}}, x2 0xa5 0xc9 0x1c 0xd5 -# CHECK: msr icc_sre_el2, x5 +# CHECK: msr {{icc_sre_el2|ICC_SRE_EL2}}, x5 0xaa 0xcc 0x1e 0xd5 -# CHECK: msr icc_sre_el3, x10 +# CHECK: msr {{icc_sre_el3|ICC_SRE_EL3}}, x10 0xd6 0xcc 0x18 0xd5 -# CHECK: msr icc_igrpen0_el1, x22 +# CHECK: msr {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x22 0xeb 0xcc 0x18 0xd5 -# CHECK: msr icc_igrpen1_el1, x11 +# CHECK: msr {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}, x11 0xe8 0xcc 0x1e 0xd5 -# CHECK: msr icc_igrpen1_el3, x8 +# CHECK: msr {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}, x8 0x4 0xcd 0x18 0xd5 -# CHECK: msr icc_seien_el1, x4 +# CHECK: msr {{icc_seien_el1|ICC_SEIEN_EL1}}, x4 0x9b 0xc8 0x18 0xd5 -# CHECK: msr icc_ap0r0_el1, x27 +# CHECK: msr {{icc_ap0r0_el1|ICC_AP0R0_EL1}}, x27 0xa5 0xc8 0x18 0xd5 -# CHECK: msr icc_ap0r1_el1, x5 +# CHECK: msr {{icc_ap0r1_el1|ICC_AP0R1_EL1}}, x5 0xd4 0xc8 0x18 0xd5 -# CHECK: msr icc_ap0r2_el1, x20 +# CHECK: msr {{icc_ap0r2_el1|ICC_AP0R2_EL1}}, x20 0xe0 0xc8 0x18 0xd5 -# CHECK: msr icc_ap0r3_el1, x0 +# CHECK: msr {{icc_ap0r3_el1|ICC_AP0R3_EL1}}, x0 0x2 0xc9 0x18 0xd5 -# CHECK: msr icc_ap1r0_el1, x2 +# CHECK: msr {{icc_ap1r0_el1|ICC_AP1R0_EL1}}, x2 0x3d 0xc9 0x18 0xd5 -# CHECK: msr icc_ap1r1_el1, x29 +# CHECK: msr {{icc_ap1r1_el1|ICC_AP1R1_EL1}}, x29 0x57 0xc9 0x18 0xd5 -# CHECK: msr icc_ap1r2_el1, x23 +# CHECK: msr {{icc_ap1r2_el1|ICC_AP1R2_EL1}}, x23 0x6b 0xc9 0x18 0xd5 -# CHECK: msr icc_ap1r3_el1, x11 +# CHECK: msr {{icc_ap1r3_el1|ICC_AP1R3_EL1}}, x11 0x2 0xc8 0x1c 0xd5 -# CHECK: msr ich_ap0r0_el2, x2 +# CHECK: msr {{ich_ap0r0_el2|ICH_AP0R0_EL2}}, x2 0x3b 0xc8 0x1c 0xd5 -# CHECK: msr ich_ap0r1_el2, x27 +# CHECK: msr {{ich_ap0r1_el2|ICH_AP0R1_EL2}}, x27 0x47 0xc8 0x1c 0xd5 -# CHECK: msr ich_ap0r2_el2, x7 +# CHECK: msr {{ich_ap0r2_el2|ICH_AP0R2_EL2}}, x7 0x61 0xc8 0x1c 0xd5 -# CHECK: msr ich_ap0r3_el2, x1 +# CHECK: msr {{ich_ap0r3_el2|ICH_AP0R3_EL2}}, x1 0x7 0xc9 0x1c 0xd5 -# CHECK: msr ich_ap1r0_el2, x7 +# CHECK: msr {{ich_ap1r0_el2|ICH_AP1R0_EL2}}, x7 0x2c 0xc9 0x1c 0xd5 -# CHECK: msr ich_ap1r1_el2, x12 +# CHECK: msr {{ich_ap1r1_el2|ICH_AP1R1_EL2}}, x12 0x4e 0xc9 0x1c 0xd5 -# CHECK: msr ich_ap1r2_el2, x14 +# CHECK: msr {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x14 0x6d 0xc9 0x1c 0xd5 -# CHECK: msr ich_ap1r3_el2, x13 +# CHECK: msr {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x13 0x1 0xcb 0x1c 0xd5 -# CHECK: msr ich_hcr_el2, x1 +# CHECK: msr {{ich_hcr_el2|ICH_HCR_EL2}}, x1 0x4a 0xcb 0x1c 0xd5 -# CHECK: msr ich_misr_el2, x10 +# CHECK: msr {{ich_misr_el2|ICH_MISR_EL2}}, x10 0xf8 0xcb 0x1c 0xd5 -# CHECK: msr ich_vmcr_el2, x24 +# CHECK: msr {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24 0x9d 0xc9 0x1c 0xd5 -# CHECK: msr ich_vseir_el2, x29 +# CHECK: msr {{ich_vseir_el2|ICH_VSEIR_EL2}}, x29 0x1a 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr0_el2, x26 +# CHECK: msr {{ich_lr0_el2|ICH_LR0_EL2}}, x26 0x29 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr1_el2, x9 +# CHECK: msr {{ich_lr1_el2|ICH_LR1_EL2}}, x9 0x52 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr2_el2, x18 +# CHECK: msr {{ich_lr2_el2|ICH_LR2_EL2}}, x18 0x7a 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr3_el2, x26 +# CHECK: msr {{ich_lr3_el2|ICH_LR3_EL2}}, x26 0x96 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr4_el2, x22 +# CHECK: msr {{ich_lr4_el2|ICH_LR4_EL2}}, x22 0xba 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr5_el2, x26 +# CHECK: msr {{ich_lr5_el2|ICH_LR5_EL2}}, x26 0xdb 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr6_el2, x27 +# CHECK: msr {{ich_lr6_el2|ICH_LR6_EL2}}, x27 0xe8 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr7_el2, x8 +# CHECK: msr {{ich_lr7_el2|ICH_LR7_EL2}}, x8 0x11 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr8_el2, x17 +# CHECK: msr {{ich_lr8_el2|ICH_LR8_EL2}}, x17 0x33 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr9_el2, x19 +# CHECK: msr {{ich_lr9_el2|ICH_LR9_EL2}}, x19 0x51 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr10_el2, x17 +# CHECK: msr {{ich_lr10_el2|ICH_LR10_EL2}}, x17 0x65 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr11_el2, x5 +# CHECK: msr {{ich_lr11_el2|ICH_LR11_EL2}}, x5 0x9d 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr12_el2, x29 +# CHECK: msr {{ich_lr12_el2|ICH_LR12_EL2}}, x29 0xa2 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr13_el2, x2 +# CHECK: msr {{ich_lr13_el2|ICH_LR13_EL2}}, x2 0xcd 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr14_el2, x13 +# CHECK: msr {{ich_lr14_el2|ICH_LR14_EL2}}, x13 0xfb 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr15_el2, x27 +# CHECK: msr {{ich_lr15_el2|ICH_LR15_EL2}}, x27 diff --git a/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt b/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt index 7ff495f..3c443a9 100644 --- a/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt +++ b/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=arm64 -disassemble < %s 2>&1 | FileCheck %s # Stores are OK. 0xe0 0x83 0x00 0xa9 diff --git a/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt b/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt index 637ebdb..6ba33ad 100644 --- a/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt +++ b/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s # None of these instructions should be classified as unpredictable: diff --git a/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt b/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt index f52d37f..1915340 100644 --- a/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt +++ b/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s # None of these instructions should be classified as unpredictable: diff --git a/test/MC/Disassembler/AArch64/lit.local.cfg b/test/MC/Disassembler/AArch64/lit.local.cfg index 9a66a00..2c423d1 100644 --- a/test/MC/Disassembler/AArch64/lit.local.cfg +++ b/test/MC/Disassembler/AArch64/lit.local.cfg @@ -1,4 +1,4 @@ targets = set(config.root.targets_to_build.split()) -if not 'AArch64' in targets: +if 'AArch64' not in targets: config.unsupported = True diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt index 863730a..3590668 100644 --- a/test/MC/Disassembler/AArch64/neon-instructions.txt +++ b/test/MC/Disassembler/AArch64/neon-instructions.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # Vector Integer Add/Sub @@ -87,7 +88,7 @@ # Vector Bitwise OR - immedidate #------------------------------------------------------------------------------ # CHECK: movi v31.4s, #0xff, lsl #24 -# CHECK: mvni v0.2s, #0x0 +# CHECK: mvni v0.2s, #{{0x0|0}} # CHECK: bic v15.4h, #0xf, lsl #8 # CHECK: orr v16.8h, #0x1f 0xff 0x67 0x07 0x4f @@ -132,10 +133,8 @@ # Vector Move - register #------------------------------------------------------------------------------ -# FIXME: these should print as "mov", but TableGen can't handle it. - -# CHECK: orr v1.16b, v15.16b, v15.16b -# CHECK: orr v25.8b, v4.8b, v4.8b +# CHECK: mov v1.16b, v15.16b +# CHECK: mov v25.8b, v4.8b 0xe1 0x1d 0xaf 0x4e 0x99 0x1c 0xa4 0x0e @@ -246,31 +245,31 @@ #---------------------------------------------------------------------- # Vector Compare Mask Equal to Zero (Integer) #---------------------------------------------------------------------- -# CHECK: cmeq v31.16b, v15.16b, #0x0 +# CHECK: cmeq v31.16b, v15.16b, #{{0x0|0}} 0xff 0x99 0x20 0x4e #---------------------------------------------------------------------- # Vector Compare Mask Greater Than or Equal to Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmge v3.8b, v15.8b, #0x0 +# CHECK: cmge v3.8b, v15.8b, #{{0x0|0}} 0xe3 0x89 0x20 0x2e #---------------------------------------------------------------------- # Vector Compare Mask Greater Than Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmgt v22.2s, v9.2s, #0x0 +# CHECK: cmgt v22.2s, v9.2s, #{{0x0|0}} 0x36 0x89 0xa0 0x0e #---------------------------------------------------------------------- # Vector Compare Mask Less Than or Equal To Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmle v5.2d, v14.2d, #0x0 +# CHECK: cmle v5.2d, v14.2d, #{{0x0|0}} 0xc5 0x99 0xe0 0x6e #---------------------------------------------------------------------- # Vector Compare Mask Less Than Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmlt v13.8h, v11.8h, #0x0 +# CHECK: cmlt v13.8h, v11.8h, #{{0x0|0}} 0x6d 0xa9 0x60 0x4e #---------------------------------------------------------------------- @@ -1559,7 +1558,7 @@ #---------------------------------------------------------------------- # Scalar Compare Bitwise Equal To Zero #---------------------------------------------------------------------- -# CHECK: cmeq d20, d21, #0x0 +# CHECK: cmeq d20, d21, #{{0x0|0}} 0xb4,0x9a,0xe0,0x5e #---------------------------------------------------------------------- @@ -1578,7 +1577,7 @@ #---------------------------------------------------------------------- # Scalar Compare Signed Greather Than Or Equal To Zero #---------------------------------------------------------------------- -# CHECK: cmge d20, d21, #0x0 +# CHECK: cmge d20, d21, #{{0x0|0}} 0xb4,0x8a,0xe0,0x7e #---------------------------------------------------------------------- @@ -1596,19 +1595,19 @@ #---------------------------------------------------------------------- # Scalar Compare Signed Greater Than Zero #---------------------------------------------------------------------- -# CHECK: cmgt d20, d21, #0x0 +# CHECK: cmgt d20, d21, #{{0x0|0}} 0xb4,0x8a,0xe0,0x5e #---------------------------------------------------------------------- # Scalar Compare Signed Less Than Or Equal To Zero #---------------------------------------------------------------------- -# CHECK: cmle d20, d21, #0x0 +# CHECK: cmle d20, d21, #{{0x0|0}} 0xb4,0x9a,0xe0,0x7e #---------------------------------------------------------------------- # Scalar Compare Less Than Zero #---------------------------------------------------------------------- -# CHECK: cmlt d20, d21, #0x0 +# CHECK: cmlt d20, d21, #{{0x0|0}} 0xb4,0xaa,0xe0,0x5e #---------------------------------------------------------------------- @@ -2008,34 +2007,34 @@ #---------------------------------------------------------------------- # Vector load/store multiple N-element structure #---------------------------------------------------------------------- -# CHECK: ld1 {v0.16b}, [x0] -# CHECK: ld1 {v15.8h, v16.8h}, [x15] -# CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp] -# CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +# CHECK: ld1 { v0.16b }, [x0] +# CHECK: ld1 { v15.8h, v16.8h }, [x15] +# CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp] +# CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] 0x00,0x70,0x40,0x4c 0xef,0xa5,0x40,0x4c 0xff,0x6b,0x40,0x4c 0x00,0x2c,0x40,0x4c -# CHECK: ld2 {v0.8b, v1.8b}, [x0] -# CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15] -# CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +# CHECK: ld2 { v0.8b, v1.8b }, [x0] +# CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15] +# CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] 0x00,0x80,0x40,0x0c 0xef,0x45,0x40,0x0c 0xff,0x0b,0x40,0x0c -# CHECK: st1 {v0.16b}, [x0] -# CHECK: st1 {v15.8h, v16.8h}, [x15] -# CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp] -# CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +# CHECK: st1 { v0.16b }, [x0] +# CHECK: st1 { v15.8h, v16.8h }, [x15] +# CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp] +# CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] 0x00,0x70,0x00,0x4c 0xef,0xa5,0x00,0x4c 0xff,0x6b,0x00,0x4c 0x00,0x2c,0x00,0x4c -# CHECK: st2 {v0.8b, v1.8b}, [x0] -# CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15] -# CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +# CHECK: st2 { v0.8b, v1.8b }, [x0] +# CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15] +# CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] 0x00,0x80,0x00,0x0c 0xef,0x45,0x00,0x0c 0xff,0x0b,0x00,0x0c @@ -2043,35 +2042,35 @@ #---------------------------------------------------------------------- # Vector load/store multiple N-element structure (post-index) #---------------------------------------------------------------------- -# CHECK: ld1 {v15.8h}, [x15], x2 -# CHECK: ld1 {v31.4s, v0.4s}, [sp], #32 -# CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 -# CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +# CHECK: ld1 { v15.8h }, [x15], x2 +# CHECK: ld1 { v31.4s, v0.4s }, [sp], #32 +# CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +# CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 0xef,0x75,0xc2,0x4c 0xff,0xab,0xdf,0x4c 0x00,0x6c,0xdf,0x4c 0x00,0x20,0xc3,0x0c -# CHECK: ld2 {v0.16b, v1.16b}, [x0], x1 -# CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 -# CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +# CHECK: ld2 { v0.16b, v1.16b }, [x0], x1 +# CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2 +# CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 0x00,0x80,0xc1,0x4c 0xef,0x45,0xc2,0x4c 0xff,0x0b,0xdf,0x4c -# CHECK: st1 {v15.8h}, [x15], x2 -# CHECK: st1 {v31.4s, v0.4s}, [sp], #32 -# CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 -# CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +# CHECK: st1 { v15.8h }, [x15], x2 +# CHECK: st1 { v31.4s, v0.4s }, [sp], #32 +# CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +# CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 0xef,0x75,0x82,0x4c 0xff,0xab,0x9f,0x4c 0x00,0x6c,0x9f,0x4c 0x00,0x20,0x83,0x0c -# CHECK: st2 {v0.16b, v1.16b}, [x0], x1 -# CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 -# CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +# CHECK: st2 { v0.16b, v1.16b }, [x0], x1 +# CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15], x2 +# CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 0x00,0x80,0x81,0x4c 0xef,0x45,0x82,0x4c 0xff,0x0b,0x9f,0x4c @@ -2080,14 +2079,14 @@ # Vector load single N-element structure to all lane of N # consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1r {v0.16b}, [x0] -# CHECK: ld1r {v15.8h}, [x15] -# CHECK: ld2r {v31.4s, v0.4s}, [sp] -# CHECK: ld2r {v0.2d, v1.2d}, [x0] -# CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0] -# CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15] -# CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] -# CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp] +# CHECK: ld1r { v0.16b }, [x0] +# CHECK: ld1r { v15.8h }, [x15] +# CHECK: ld2r { v31.4s, v0.4s }, [sp] +# CHECK: ld2r { v0.2d, v1.2d }, [x0] +# CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0] +# CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15] +# CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] +# CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp] 0x00,0xc0,0x40,0x4d 0xef,0xc5,0x40,0x4d 0xff,0xcb,0x60,0x4d @@ -2101,14 +2100,14 @@ # Vector load/store single N-element structure to/from one lane of N # consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1 {v0.b}[9], [x0] -# CHECK: ld2 {v15.h, v16.h}[7], [x15] -# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp] -# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] -# CHECK: st1 {v0.d}[1], [x0] -# CHECK: st2 {v31.s, v0.s}[3], [sp] -# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15] -# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] +# CHECK: ld1 { v0.b }[9], [x0] +# CHECK: ld2 { v15.h, v16.h }[7], [x15] +# CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp] +# CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] +# CHECK: st1 { v0.d }[1], [x0] +# CHECK: st2 { v31.s, v0.s }[3], [sp] +# CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15] +# CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] 0x00,0x04,0x40,0x4d 0xef,0x59,0x60,0x4d 0xff,0xb3,0x40,0x4d @@ -2122,14 +2121,14 @@ # Post-index of vector load single N-element structure to all lane of N # consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1r {v0.16b}, [x0], #1 -# CHECK: ld1r {v15.8h}, [x15], #2 -# CHECK: ld2r {v31.4s, v0.4s}, [sp], #8 -# CHECK: ld2r {v0.2d, v1.2d}, [x0], #16 -# CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3 -# CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6 -# CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30 -# CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7 +# CHECK: ld1r { v0.16b }, [x0], #1 +# CHECK: ld1r { v15.8h }, [x15], #2 +# CHECK: ld2r { v31.4s, v0.4s }, [sp], #8 +# CHECK: ld2r { v0.2d, v1.2d }, [x0], #16 +# CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3 +# CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6 +# CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30 +# CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7 0x00,0xc0,0xdf,0x4d 0xef,0xc5,0xdf,0x4d 0xff,0xcb,0xff,0x4d @@ -2143,15 +2142,15 @@ # Post-index of vector load/store single N-element structure to/from # one lane of N consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1 {v0.b}[9], [x0], #1 -# CHECK: ld2 {v15.h, v16.h}[7], [x15], #4 -# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3 -# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 -# CHECK: ld4 {v0.h, v1.h, v2.h, v3.h}[7], [x0], x0 -# CHECK: st1 {v0.d}[1], [x0], #8 -# CHECK: st2 {v31.s, v0.s}[3], [sp], #8 -# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6 -# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 +# CHECK: ld1 { v0.b }[9], [x0], #1 +# CHECK: ld2 { v15.h, v16.h }[7], [x15], #4 +# CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp], x3 +# CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 +# CHECK: ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0 +# CHECK: st1 { v0.d }[1], [x0], #8 +# CHECK: st2 { v31.s, v0.s }[3], [sp], #8 +# CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15], #6 +# CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 0x00,0x04,0xdf,0x4d 0xef,0x59,0xff,0x4d 0xff,0xb3,0xc3,0x4d @@ -2167,8 +2166,8 @@ #---------------------------------------------------------------------- 0x20,0x18,0x02,0x2e 0x20,0x18,0x02,0x6e -# CHECK: ext v0.8b, v1.8b, v2.8b, #0x3 -# CHECK: ext v0.16b, v1.16b, v2.16b, #0x3 +# CHECK: ext v0.8b, v1.8b, v2.8b, #{{0x3|3}} +# CHECK: ext v0.16b, v1.16b, v2.16b, #{{0x3|3}} #---------------------------------------------------------------------- # unzip with 3 same vectors to get primary result @@ -2481,10 +2480,10 @@ #---------------------------------------------------------------------- #Duplicate element (scalar) #---------------------------------------------------------------------- -# CHECK: dup b0, v0.b[15] -# CHECK: dup h2, v31.h[5] -# CHECK: dup s17, v2.s[2] -# CHECK: dup d6, v12.d[1] +# CHECK: {{dup|mov}} b0, v0.b[15] +# CHECK: {{dup|mov}} h2, v31.h[5] +# CHECK: {{dup|mov}} s17, v2.s[2] +# CHECK: {{dup|mov}} d6, v12.d[1] 0x00 0x04 0x1f 0x5e 0xe2 0x07 0x16 0x5e 0x51 0x04 0x14 0x5e @@ -2497,37 +2496,37 @@ 0xf0,0x23,0x02,0x0e 0x20,0x40,0x02,0x0e 0xf0,0x62,0x02,0x0e -# CHECK: tbl v0.8b, {v1.16b}, v2.8b -# CHECK: tbl v16.8b, {v31.16b, v0.16b}, v2.8b -# CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b -# CHECK: tbl v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b +# CHECK: tbl v0.8b, { v1.16b }, v2.8b +# CHECK: tbl v16.8b, { v31.16b, v0.16b }, v2.8b +# CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b +# CHECK: tbl v16.8b, { v23.16b, v24.16b, v25.16b, v26.16b }, v2.8b 0x20,0x00,0x02,0x4e 0xf0,0x23,0x02,0x4e 0x20,0x40,0x02,0x4e 0xe0,0x63,0x02,0x4e -# CHECK: tbl v0.16b, {v1.16b}, v2.16b -# CHECK: tbl v16.16b, {v31.16b, v0.16b}, v2.16b -# CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b -# CHECK: tbl v0.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b +# CHECK: tbl v0.16b, { v1.16b }, v2.16b +# CHECK: tbl v16.16b, { v31.16b, v0.16b }, v2.16b +# CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b +# CHECK: tbl v0.16b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.16b 0x20,0x10,0x02,0x0e 0xf0,0x33,0x02,0x0e 0x20,0x50,0x02,0x0e 0xf0,0x72,0x02,0x0e -# CHECK: tbx v0.8b, {v1.16b}, v2.8b -# CHECK: tbx v16.8b, {v31.16b, v0.16b}, v2.8b -# CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b -# CHECK: tbx v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b +# CHECK: tbx v0.8b, { v1.16b }, v2.8b +# CHECK: tbx v16.8b, { v31.16b, v0.16b }, v2.8b +# CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b +# CHECK: tbx v16.8b, { v23.16b, v24.16b, v25.16b, v26.16b }, v2.8b 0x20,0x10,0x02,0x4e 0xf0,0x33,0x02,0x4e 0x20,0x50,0x02,0x4e 0xf0,0x73,0x02,0x4e -# CHECK: tbx v0.16b, {v1.16b}, v2.16b -# CHECK: tbx v16.16b, {v31.16b, v0.16b}, v2.16b -# CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b -# CHECK: tbx v16.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b +# CHECK: tbx v0.16b, { v1.16b }, v2.16b +# CHECK: tbx v16.16b, { v31.16b, v0.16b }, v2.16b +# CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b +# CHECK: tbx v16.16b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.16b #---------------------------------------------------------------------- # Scalar Floating-point Convert To Lower Precision Narrow, Rounding To diff --git a/test/MC/Disassembler/AArch64/trace-regs.txt b/test/MC/Disassembler/AArch64/trace-regs.txt index 10c5937..43171e3 100644 --- a/test/MC/Disassembler/AArch64/trace-regs.txt +++ b/test/MC/Disassembler/AArch64/trace-regs.txt @@ -1,736 +1,737 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-none-linux-gnu -disassemble < %s | FileCheck %s 0x8 0x3 0x31 0xd5 -# CHECK: mrs x8, trcstatr +# CHECK: mrs x8, {{trcstatr|TRCSTATR}} 0xc9 0x0 0x31 0xd5 -# CHECK: mrs x9, trcidr8 +# CHECK: mrs x9, {{trcidr8|TRCIDR8}} 0xcb 0x1 0x31 0xd5 -# CHECK: mrs x11, trcidr9 +# CHECK: mrs x11, {{trcidr9|TRCIDR9}} 0xd9 0x2 0x31 0xd5 -# CHECK: mrs x25, trcidr10 +# CHECK: mrs x25, {{trcidr10|TRCIDR10}} 0xc7 0x3 0x31 0xd5 -# CHECK: mrs x7, trcidr11 +# CHECK: mrs x7, {{trcidr11|TRCIDR11}} 0xc7 0x4 0x31 0xd5 -# CHECK: mrs x7, trcidr12 +# CHECK: mrs x7, {{trcidr12|TRCIDR12}} 0xc6 0x5 0x31 0xd5 -# CHECK: mrs x6, trcidr13 +# CHECK: mrs x6, {{trcidr13|TRCIDR13}} 0xfb 0x8 0x31 0xd5 -# CHECK: mrs x27, trcidr0 +# CHECK: mrs x27, {{trcidr0|TRCIDR0}} 0xfd 0x9 0x31 0xd5 -# CHECK: mrs x29, trcidr1 +# CHECK: mrs x29, {{trcidr1|TRCIDR1}} 0xe4 0xa 0x31 0xd5 -# CHECK: mrs x4, trcidr2 +# CHECK: mrs x4, {{trcidr2|TRCIDR2}} 0xe8 0xb 0x31 0xd5 -# CHECK: mrs x8, trcidr3 +# CHECK: mrs x8, {{trcidr3|TRCIDR3}} 0xef 0xc 0x31 0xd5 -# CHECK: mrs x15, trcidr4 +# CHECK: mrs x15, {{trcidr4|TRCIDR4}} 0xf4 0xd 0x31 0xd5 -# CHECK: mrs x20, trcidr5 +# CHECK: mrs x20, {{trcidr5|TRCIDR5}} 0xe6 0xe 0x31 0xd5 -# CHECK: mrs x6, trcidr6 +# CHECK: mrs x6, {{trcidr6|TRCIDR6}} 0xe6 0xf 0x31 0xd5 -# CHECK: mrs x6, trcidr7 +# CHECK: mrs x6, {{trcidr7|TRCIDR7}} 0x98 0x11 0x31 0xd5 -# CHECK: mrs x24, trcoslsr +# CHECK: mrs x24, {{trcoslsr|TRCOSLSR}} 0x92 0x15 0x31 0xd5 -# CHECK: mrs x18, trcpdsr +# CHECK: mrs x18, {{trcpdsr|TRCPDSR}} 0xdc 0x7a 0x31 0xd5 -# CHECK: mrs x28, trcdevaff0 +# CHECK: mrs x28, {{trcdevaff0|TRCDEVAFF0}} 0xc5 0x7b 0x31 0xd5 -# CHECK: mrs x5, trcdevaff1 +# CHECK: mrs x5, {{trcdevaff1|TRCDEVAFF1}} 0xc5 0x7d 0x31 0xd5 -# CHECK: mrs x5, trclsr +# CHECK: mrs x5, {{trclsr|TRCLSR}} 0xcb 0x7e 0x31 0xd5 -# CHECK: mrs x11, trcauthstatus +# CHECK: mrs x11, {{trcauthstatus|TRCAUTHSTATUS}} 0xcd 0x7f 0x31 0xd5 -# CHECK: mrs x13, trcdevarch +# CHECK: mrs x13, {{trcdevarch|TRCDEVARCH}} 0xf2 0x72 0x31 0xd5 -# CHECK: mrs x18, trcdevid +# CHECK: mrs x18, {{trcdevid|TRCDEVID}} 0xf6 0x73 0x31 0xd5 -# CHECK: mrs x22, trcdevtype +# CHECK: mrs x22, {{trcdevtype|TRCDEVTYPE}} 0xee 0x74 0x31 0xd5 -# CHECK: mrs x14, trcpidr4 +# CHECK: mrs x14, {{trcpidr4|TRCPIDR4}} 0xe5 0x75 0x31 0xd5 -# CHECK: mrs x5, trcpidr5 +# CHECK: mrs x5, {{trcpidr5|TRCPIDR5}} 0xe5 0x76 0x31 0xd5 -# CHECK: mrs x5, trcpidr6 +# CHECK: mrs x5, {{trcpidr6|TRCPIDR6}} 0xe9 0x77 0x31 0xd5 -# CHECK: mrs x9, trcpidr7 +# CHECK: mrs x9, {{trcpidr7|TRCPIDR7}} 0xef 0x78 0x31 0xd5 -# CHECK: mrs x15, trcpidr0 +# CHECK: mrs x15, {{trcpidr0|TRCPIDR0}} 0xe6 0x79 0x31 0xd5 -# CHECK: mrs x6, trcpidr1 +# CHECK: mrs x6, {{trcpidr1|TRCPIDR1}} 0xeb 0x7a 0x31 0xd5 -# CHECK: mrs x11, trcpidr2 +# CHECK: mrs x11, {{trcpidr2|TRCPIDR2}} 0xf4 0x7b 0x31 0xd5 -# CHECK: mrs x20, trcpidr3 +# CHECK: mrs x20, {{trcpidr3|TRCPIDR3}} 0xf1 0x7c 0x31 0xd5 -# CHECK: mrs x17, trccidr0 +# CHECK: mrs x17, {{trccidr0|TRCCIDR0}} 0xe2 0x7d 0x31 0xd5 -# CHECK: mrs x2, trccidr1 +# CHECK: mrs x2, {{trccidr1|TRCCIDR1}} 0xf4 0x7e 0x31 0xd5 -# CHECK: mrs x20, trccidr2 +# CHECK: mrs x20, {{trccidr2|TRCCIDR2}} 0xe4 0x7f 0x31 0xd5 -# CHECK: mrs x4, trccidr3 +# CHECK: mrs x4, {{trccidr3|TRCCIDR3}} 0xb 0x1 0x31 0xd5 -# CHECK: mrs x11, trcprgctlr +# CHECK: mrs x11, {{trcprgctlr|TRCPRGCTLR}} 0x17 0x2 0x31 0xd5 -# CHECK: mrs x23, trcprocselr +# CHECK: mrs x23, {{trcprocselr|TRCPROCSELR}} 0xd 0x4 0x31 0xd5 -# CHECK: mrs x13, trcconfigr +# CHECK: mrs x13, {{trcconfigr|TRCCONFIGR}} 0x17 0x6 0x31 0xd5 -# CHECK: mrs x23, trcauxctlr +# CHECK: mrs x23, {{trcauxctlr|TRCAUXCTLR}} 0x9 0x8 0x31 0xd5 -# CHECK: mrs x9, trceventctl0r +# CHECK: mrs x9, {{trceventctl0r|TRCEVENTCTL0R}} 0x10 0x9 0x31 0xd5 -# CHECK: mrs x16, trceventctl1r +# CHECK: mrs x16, {{trceventctl1r|TRCEVENTCTL1R}} 0x4 0xb 0x31 0xd5 -# CHECK: mrs x4, trcstallctlr +# CHECK: mrs x4, {{trcstallctlr|TRCSTALLCTLR}} 0xe 0xc 0x31 0xd5 -# CHECK: mrs x14, trctsctlr +# CHECK: mrs x14, {{trctsctlr|TRCTSCTLR}} 0x18 0xd 0x31 0xd5 -# CHECK: mrs x24, trcsyncpr +# CHECK: mrs x24, {{trcsyncpr|TRCSYNCPR}} 0x1c 0xe 0x31 0xd5 -# CHECK: mrs x28, trcccctlr +# CHECK: mrs x28, {{trcccctlr|TRCCCCTLR}} 0xf 0xf 0x31 0xd5 -# CHECK: mrs x15, trcbbctlr +# CHECK: mrs x15, {{trcbbctlr|TRCBBCTLR}} 0x21 0x0 0x31 0xd5 -# CHECK: mrs x1, trctraceidr +# CHECK: mrs x1, {{trctraceidr|TRCTRACEIDR}} 0x34 0x1 0x31 0xd5 -# CHECK: mrs x20, trcqctlr +# CHECK: mrs x20, {{trcqctlr|TRCQCTLR}} 0x42 0x0 0x31 0xd5 -# CHECK: mrs x2, trcvictlr +# CHECK: mrs x2, {{trcvictlr|TRCVICTLR}} 0x4c 0x1 0x31 0xd5 -# CHECK: mrs x12, trcviiectlr +# CHECK: mrs x12, {{trcviiectlr|TRCVIIECTLR}} 0x50 0x2 0x31 0xd5 -# CHECK: mrs x16, trcvissctlr +# CHECK: mrs x16, {{trcvissctlr|TRCVISSCTLR}} 0x48 0x3 0x31 0xd5 -# CHECK: mrs x8, trcvipcssctlr +# CHECK: mrs x8, {{trcvipcssctlr|TRCVIPCSSCTLR}} 0x5b 0x8 0x31 0xd5 -# CHECK: mrs x27, trcvdctlr +# CHECK: mrs x27, {{trcvdctlr|TRCVDCTLR}} 0x49 0x9 0x31 0xd5 -# CHECK: mrs x9, trcvdsacctlr +# CHECK: mrs x9, {{trcvdsacctlr|TRCVDSACCTLR}} 0x40 0xa 0x31 0xd5 -# CHECK: mrs x0, trcvdarcctlr +# CHECK: mrs x0, {{trcvdarcctlr|TRCVDARCCTLR}} 0x8d 0x0 0x31 0xd5 -# CHECK: mrs x13, trcseqevr0 +# CHECK: mrs x13, {{trcseqevr0|TRCSEQEVR0}} 0x8b 0x1 0x31 0xd5 -# CHECK: mrs x11, trcseqevr1 +# CHECK: mrs x11, {{trcseqevr1|TRCSEQEVR1}} 0x9a 0x2 0x31 0xd5 -# CHECK: mrs x26, trcseqevr2 +# CHECK: mrs x26, {{trcseqevr2|TRCSEQEVR2}} 0x8e 0x6 0x31 0xd5 -# CHECK: mrs x14, trcseqrstevr +# CHECK: mrs x14, {{trcseqrstevr|TRCSEQRSTEVR}} 0x84 0x7 0x31 0xd5 -# CHECK: mrs x4, trcseqstr +# CHECK: mrs x4, {{trcseqstr|TRCSEQSTR}} 0x91 0x8 0x31 0xd5 -# CHECK: mrs x17, trcextinselr +# CHECK: mrs x17, {{trcextinselr|TRCEXTINSELR}} 0xb5 0x0 0x31 0xd5 -# CHECK: mrs x21, trccntrldvr0 +# CHECK: mrs x21, {{trccntrldvr0|TRCCNTRLDVR0}} 0xaa 0x1 0x31 0xd5 -# CHECK: mrs x10, trccntrldvr1 +# CHECK: mrs x10, {{trccntrldvr1|TRCCNTRLDVR1}} 0xb4 0x2 0x31 0xd5 -# CHECK: mrs x20, trccntrldvr2 +# CHECK: mrs x20, {{trccntrldvr2|TRCCNTRLDVR2}} 0xa5 0x3 0x31 0xd5 -# CHECK: mrs x5, trccntrldvr3 +# CHECK: mrs x5, {{trccntrldvr3|TRCCNTRLDVR3}} 0xb1 0x4 0x31 0xd5 -# CHECK: mrs x17, trccntctlr0 +# CHECK: mrs x17, {{trccntctlr0|TRCCNTCTLR0}} 0xa1 0x5 0x31 0xd5 -# CHECK: mrs x1, trccntctlr1 +# CHECK: mrs x1, {{trccntctlr1|TRCCNTCTLR1}} 0xb1 0x6 0x31 0xd5 -# CHECK: mrs x17, trccntctlr2 +# CHECK: mrs x17, {{trccntctlr2|TRCCNTCTLR2}} 0xa6 0x7 0x31 0xd5 -# CHECK: mrs x6, trccntctlr3 +# CHECK: mrs x6, {{trccntctlr3|TRCCNTCTLR3}} 0xbc 0x8 0x31 0xd5 -# CHECK: mrs x28, trccntvr0 +# CHECK: mrs x28, {{trccntvr0|TRCCNTVR0}} 0xb7 0x9 0x31 0xd5 -# CHECK: mrs x23, trccntvr1 +# CHECK: mrs x23, {{trccntvr1|TRCCNTVR1}} 0xa9 0xa 0x31 0xd5 -# CHECK: mrs x9, trccntvr2 +# CHECK: mrs x9, {{trccntvr2|TRCCNTVR2}} 0xa6 0xb 0x31 0xd5 -# CHECK: mrs x6, trccntvr3 +# CHECK: mrs x6, {{trccntvr3|TRCCNTVR3}} 0xf8 0x0 0x31 0xd5 -# CHECK: mrs x24, trcimspec0 +# CHECK: mrs x24, {{trcimspec0|TRCIMSPEC0}} 0xf8 0x1 0x31 0xd5 -# CHECK: mrs x24, trcimspec1 +# CHECK: mrs x24, {{trcimspec1|TRCIMSPEC1}} 0xef 0x2 0x31 0xd5 -# CHECK: mrs x15, trcimspec2 +# CHECK: mrs x15, {{trcimspec2|TRCIMSPEC2}} 0xea 0x3 0x31 0xd5 -# CHECK: mrs x10, trcimspec3 +# CHECK: mrs x10, {{trcimspec3|TRCIMSPEC3}} 0xfd 0x4 0x31 0xd5 -# CHECK: mrs x29, trcimspec4 +# CHECK: mrs x29, {{trcimspec4|TRCIMSPEC4}} 0xf2 0x5 0x31 0xd5 -# CHECK: mrs x18, trcimspec5 +# CHECK: mrs x18, {{trcimspec5|TRCIMSPEC5}} 0xfd 0x6 0x31 0xd5 -# CHECK: mrs x29, trcimspec6 +# CHECK: mrs x29, {{trcimspec6|TRCIMSPEC6}} 0xe2 0x7 0x31 0xd5 -# CHECK: mrs x2, trcimspec7 +# CHECK: mrs x2, {{trcimspec7|TRCIMSPEC7}} 0x8 0x12 0x31 0xd5 -# CHECK: mrs x8, trcrsctlr2 +# CHECK: mrs x8, {{trcrsctlr2|TRCRSCTLR2}} 0x0 0x13 0x31 0xd5 -# CHECK: mrs x0, trcrsctlr3 +# CHECK: mrs x0, {{trcrsctlr3|TRCRSCTLR3}} 0xc 0x14 0x31 0xd5 -# CHECK: mrs x12, trcrsctlr4 +# CHECK: mrs x12, {{trcrsctlr4|TRCRSCTLR4}} 0x1a 0x15 0x31 0xd5 -# CHECK: mrs x26, trcrsctlr5 +# CHECK: mrs x26, {{trcrsctlr5|TRCRSCTLR5}} 0x1d 0x16 0x31 0xd5 -# CHECK: mrs x29, trcrsctlr6 +# CHECK: mrs x29, {{trcrsctlr6|TRCRSCTLR6}} 0x11 0x17 0x31 0xd5 -# CHECK: mrs x17, trcrsctlr7 +# CHECK: mrs x17, {{trcrsctlr7|TRCRSCTLR7}} 0x0 0x18 0x31 0xd5 -# CHECK: mrs x0, trcrsctlr8 +# CHECK: mrs x0, {{trcrsctlr8|TRCRSCTLR8}} 0x1 0x19 0x31 0xd5 -# CHECK: mrs x1, trcrsctlr9 +# CHECK: mrs x1, {{trcrsctlr9|TRCRSCTLR9}} 0x11 0x1a 0x31 0xd5 -# CHECK: mrs x17, trcrsctlr10 +# CHECK: mrs x17, {{trcrsctlr10|TRCRSCTLR10}} 0x15 0x1b 0x31 0xd5 -# CHECK: mrs x21, trcrsctlr11 +# CHECK: mrs x21, {{trcrsctlr11|TRCRSCTLR11}} 0x1 0x1c 0x31 0xd5 -# CHECK: mrs x1, trcrsctlr12 +# CHECK: mrs x1, {{trcrsctlr12|TRCRSCTLR12}} 0x8 0x1d 0x31 0xd5 -# CHECK: mrs x8, trcrsctlr13 +# CHECK: mrs x8, {{trcrsctlr13|TRCRSCTLR13}} 0x18 0x1e 0x31 0xd5 -# CHECK: mrs x24, trcrsctlr14 +# CHECK: mrs x24, {{trcrsctlr14|TRCRSCTLR14}} 0x0 0x1f 0x31 0xd5 -# CHECK: mrs x0, trcrsctlr15 +# CHECK: mrs x0, {{trcrsctlr15|TRCRSCTLR15}} 0x22 0x10 0x31 0xd5 -# CHECK: mrs x2, trcrsctlr16 +# CHECK: mrs x2, {{trcrsctlr16|TRCRSCTLR16}} 0x3d 0x11 0x31 0xd5 -# CHECK: mrs x29, trcrsctlr17 +# CHECK: mrs x29, {{trcrsctlr17|TRCRSCTLR17}} 0x36 0x12 0x31 0xd5 -# CHECK: mrs x22, trcrsctlr18 +# CHECK: mrs x22, {{trcrsctlr18|TRCRSCTLR18}} 0x26 0x13 0x31 0xd5 -# CHECK: mrs x6, trcrsctlr19 +# CHECK: mrs x6, {{trcrsctlr19|TRCRSCTLR19}} 0x3a 0x14 0x31 0xd5 -# CHECK: mrs x26, trcrsctlr20 +# CHECK: mrs x26, {{trcrsctlr20|TRCRSCTLR20}} 0x3a 0x15 0x31 0xd5 -# CHECK: mrs x26, trcrsctlr21 +# CHECK: mrs x26, {{trcrsctlr21|TRCRSCTLR21}} 0x24 0x16 0x31 0xd5 -# CHECK: mrs x4, trcrsctlr22 +# CHECK: mrs x4, {{trcrsctlr22|TRCRSCTLR22}} 0x2c 0x17 0x31 0xd5 -# CHECK: mrs x12, trcrsctlr23 +# CHECK: mrs x12, {{trcrsctlr23|TRCRSCTLR23}} 0x21 0x18 0x31 0xd5 -# CHECK: mrs x1, trcrsctlr24 +# CHECK: mrs x1, {{trcrsctlr24|TRCRSCTLR24}} 0x20 0x19 0x31 0xd5 -# CHECK: mrs x0, trcrsctlr25 +# CHECK: mrs x0, {{trcrsctlr25|TRCRSCTLR25}} 0x31 0x1a 0x31 0xd5 -# CHECK: mrs x17, trcrsctlr26 +# CHECK: mrs x17, {{trcrsctlr26|TRCRSCTLR26}} 0x28 0x1b 0x31 0xd5 -# CHECK: mrs x8, trcrsctlr27 +# CHECK: mrs x8, {{trcrsctlr27|TRCRSCTLR27}} 0x2a 0x1c 0x31 0xd5 -# CHECK: mrs x10, trcrsctlr28 +# CHECK: mrs x10, {{trcrsctlr28|TRCRSCTLR28}} 0x39 0x1d 0x31 0xd5 -# CHECK: mrs x25, trcrsctlr29 +# CHECK: mrs x25, {{trcrsctlr29|TRCRSCTLR29}} 0x2c 0x1e 0x31 0xd5 -# CHECK: mrs x12, trcrsctlr30 +# CHECK: mrs x12, {{trcrsctlr30|TRCRSCTLR30}} 0x2b 0x1f 0x31 0xd5 -# CHECK: mrs x11, trcrsctlr31 +# CHECK: mrs x11, {{trcrsctlr31|TRCRSCTLR31}} 0x52 0x10 0x31 0xd5 -# CHECK: mrs x18, trcssccr0 +# CHECK: mrs x18, {{trcssccr0|TRCSSCCR0}} 0x4c 0x11 0x31 0xd5 -# CHECK: mrs x12, trcssccr1 +# CHECK: mrs x12, {{trcssccr1|TRCSSCCR1}} 0x43 0x12 0x31 0xd5 -# CHECK: mrs x3, trcssccr2 +# CHECK: mrs x3, {{trcssccr2|TRCSSCCR2}} 0x42 0x13 0x31 0xd5 -# CHECK: mrs x2, trcssccr3 +# CHECK: mrs x2, {{trcssccr3|TRCSSCCR3}} 0x55 0x14 0x31 0xd5 -# CHECK: mrs x21, trcssccr4 +# CHECK: mrs x21, {{trcssccr4|TRCSSCCR4}} 0x4a 0x15 0x31 0xd5 -# CHECK: mrs x10, trcssccr5 +# CHECK: mrs x10, {{trcssccr5|TRCSSCCR5}} 0x56 0x16 0x31 0xd5 -# CHECK: mrs x22, trcssccr6 +# CHECK: mrs x22, {{trcssccr6|TRCSSCCR6}} 0x57 0x17 0x31 0xd5 -# CHECK: mrs x23, trcssccr7 +# CHECK: mrs x23, {{trcssccr7|TRCSSCCR7}} 0x57 0x18 0x31 0xd5 -# CHECK: mrs x23, trcsscsr0 +# CHECK: mrs x23, {{trcsscsr0|TRCSSCSR0}} 0x53 0x19 0x31 0xd5 -# CHECK: mrs x19, trcsscsr1 +# CHECK: mrs x19, {{trcsscsr1|TRCSSCSR1}} 0x59 0x1a 0x31 0xd5 -# CHECK: mrs x25, trcsscsr2 +# CHECK: mrs x25, {{trcsscsr2|TRCSSCSR2}} 0x51 0x1b 0x31 0xd5 -# CHECK: mrs x17, trcsscsr3 +# CHECK: mrs x17, {{trcsscsr3|TRCSSCSR3}} 0x53 0x1c 0x31 0xd5 -# CHECK: mrs x19, trcsscsr4 +# CHECK: mrs x19, {{trcsscsr4|TRCSSCSR4}} 0x4b 0x1d 0x31 0xd5 -# CHECK: mrs x11, trcsscsr5 +# CHECK: mrs x11, {{trcsscsr5|TRCSSCSR5}} 0x45 0x1e 0x31 0xd5 -# CHECK: mrs x5, trcsscsr6 +# CHECK: mrs x5, {{trcsscsr6|TRCSSCSR6}} 0x49 0x1f 0x31 0xd5 -# CHECK: mrs x9, trcsscsr7 +# CHECK: mrs x9, {{trcsscsr7|TRCSSCSR7}} 0x9a 0x14 0x31 0xd5 -# CHECK: mrs x26, trcpdcr +# CHECK: mrs x26, {{trcpdcr|TRCPDCR}} 0x8 0x20 0x31 0xd5 -# CHECK: mrs x8, trcacvr0 +# CHECK: mrs x8, {{trcacvr0|TRCACVR0}} 0xf 0x22 0x31 0xd5 -# CHECK: mrs x15, trcacvr1 +# CHECK: mrs x15, {{trcacvr1|TRCACVR1}} 0x13 0x24 0x31 0xd5 -# CHECK: mrs x19, trcacvr2 +# CHECK: mrs x19, {{trcacvr2|TRCACVR2}} 0x8 0x26 0x31 0xd5 -# CHECK: mrs x8, trcacvr3 +# CHECK: mrs x8, {{trcacvr3|TRCACVR3}} 0x1c 0x28 0x31 0xd5 -# CHECK: mrs x28, trcacvr4 +# CHECK: mrs x28, {{trcacvr4|TRCACVR4}} 0x3 0x2a 0x31 0xd5 -# CHECK: mrs x3, trcacvr5 +# CHECK: mrs x3, {{trcacvr5|TRCACVR5}} 0x19 0x2c 0x31 0xd5 -# CHECK: mrs x25, trcacvr6 +# CHECK: mrs x25, {{trcacvr6|TRCACVR6}} 0x18 0x2e 0x31 0xd5 -# CHECK: mrs x24, trcacvr7 +# CHECK: mrs x24, {{trcacvr7|TRCACVR7}} 0x26 0x20 0x31 0xd5 -# CHECK: mrs x6, trcacvr8 +# CHECK: mrs x6, {{trcacvr8|TRCACVR8}} 0x23 0x22 0x31 0xd5 -# CHECK: mrs x3, trcacvr9 +# CHECK: mrs x3, {{trcacvr9|TRCACVR9}} 0x38 0x24 0x31 0xd5 -# CHECK: mrs x24, trcacvr10 +# CHECK: mrs x24, {{trcacvr10|TRCACVR10}} 0x23 0x26 0x31 0xd5 -# CHECK: mrs x3, trcacvr11 +# CHECK: mrs x3, {{trcacvr11|TRCACVR11}} 0x2c 0x28 0x31 0xd5 -# CHECK: mrs x12, trcacvr12 +# CHECK: mrs x12, {{trcacvr12|TRCACVR12}} 0x29 0x2a 0x31 0xd5 -# CHECK: mrs x9, trcacvr13 +# CHECK: mrs x9, {{trcacvr13|TRCACVR13}} 0x2e 0x2c 0x31 0xd5 -# CHECK: mrs x14, trcacvr14 +# CHECK: mrs x14, {{trcacvr14|TRCACVR14}} 0x23 0x2e 0x31 0xd5 -# CHECK: mrs x3, trcacvr15 +# CHECK: mrs x3, {{trcacvr15|TRCACVR15}} 0x55 0x20 0x31 0xd5 -# CHECK: mrs x21, trcacatr0 +# CHECK: mrs x21, {{trcacatr0|TRCACATR0}} 0x5a 0x22 0x31 0xd5 -# CHECK: mrs x26, trcacatr1 +# CHECK: mrs x26, {{trcacatr1|TRCACATR1}} 0x48 0x24 0x31 0xd5 -# CHECK: mrs x8, trcacatr2 +# CHECK: mrs x8, {{trcacatr2|TRCACATR2}} 0x56 0x26 0x31 0xd5 -# CHECK: mrs x22, trcacatr3 +# CHECK: mrs x22, {{trcacatr3|TRCACATR3}} 0x46 0x28 0x31 0xd5 -# CHECK: mrs x6, trcacatr4 +# CHECK: mrs x6, {{trcacatr4|TRCACATR4}} 0x5d 0x2a 0x31 0xd5 -# CHECK: mrs x29, trcacatr5 +# CHECK: mrs x29, {{trcacatr5|TRCACATR5}} 0x45 0x2c 0x31 0xd5 -# CHECK: mrs x5, trcacatr6 +# CHECK: mrs x5, {{trcacatr6|TRCACATR6}} 0x52 0x2e 0x31 0xd5 -# CHECK: mrs x18, trcacatr7 +# CHECK: mrs x18, {{trcacatr7|TRCACATR7}} 0x62 0x20 0x31 0xd5 -# CHECK: mrs x2, trcacatr8 +# CHECK: mrs x2, {{trcacatr8|TRCACATR8}} 0x73 0x22 0x31 0xd5 -# CHECK: mrs x19, trcacatr9 +# CHECK: mrs x19, {{trcacatr9|TRCACATR9}} 0x6d 0x24 0x31 0xd5 -# CHECK: mrs x13, trcacatr10 +# CHECK: mrs x13, {{trcacatr10|TRCACATR10}} 0x79 0x26 0x31 0xd5 -# CHECK: mrs x25, trcacatr11 +# CHECK: mrs x25, {{trcacatr11|TRCACATR11}} 0x72 0x28 0x31 0xd5 -# CHECK: mrs x18, trcacatr12 +# CHECK: mrs x18, {{trcacatr12|TRCACATR12}} 0x7d 0x2a 0x31 0xd5 -# CHECK: mrs x29, trcacatr13 +# CHECK: mrs x29, {{trcacatr13|TRCACATR13}} 0x69 0x2c 0x31 0xd5 -# CHECK: mrs x9, trcacatr14 +# CHECK: mrs x9, {{trcacatr14|TRCACATR14}} 0x72 0x2e 0x31 0xd5 -# CHECK: mrs x18, trcacatr15 +# CHECK: mrs x18, {{trcacatr15|TRCACATR15}} 0x9d 0x20 0x31 0xd5 -# CHECK: mrs x29, trcdvcvr0 +# CHECK: mrs x29, {{trcdvcvr0|TRCDVCVR0}} 0x8f 0x24 0x31 0xd5 -# CHECK: mrs x15, trcdvcvr1 +# CHECK: mrs x15, {{trcdvcvr1|TRCDVCVR1}} 0x8f 0x28 0x31 0xd5 -# CHECK: mrs x15, trcdvcvr2 +# CHECK: mrs x15, {{trcdvcvr2|TRCDVCVR2}} 0x8f 0x2c 0x31 0xd5 -# CHECK: mrs x15, trcdvcvr3 +# CHECK: mrs x15, {{trcdvcvr3|TRCDVCVR3}} 0xb3 0x20 0x31 0xd5 -# CHECK: mrs x19, trcdvcvr4 +# CHECK: mrs x19, {{trcdvcvr4|TRCDVCVR4}} 0xb6 0x24 0x31 0xd5 -# CHECK: mrs x22, trcdvcvr5 +# CHECK: mrs x22, {{trcdvcvr5|TRCDVCVR5}} 0xbb 0x28 0x31 0xd5 -# CHECK: mrs x27, trcdvcvr6 +# CHECK: mrs x27, {{trcdvcvr6|TRCDVCVR6}} 0xa1 0x2c 0x31 0xd5 -# CHECK: mrs x1, trcdvcvr7 +# CHECK: mrs x1, {{trcdvcvr7|TRCDVCVR7}} 0xdd 0x20 0x31 0xd5 -# CHECK: mrs x29, trcdvcmr0 +# CHECK: mrs x29, {{trcdvcmr0|TRCDVCMR0}} 0xc9 0x24 0x31 0xd5 -# CHECK: mrs x9, trcdvcmr1 +# CHECK: mrs x9, {{trcdvcmr1|TRCDVCMR1}} 0xc1 0x28 0x31 0xd5 -# CHECK: mrs x1, trcdvcmr2 +# CHECK: mrs x1, {{trcdvcmr2|TRCDVCMR2}} 0xc2 0x2c 0x31 0xd5 -# CHECK: mrs x2, trcdvcmr3 +# CHECK: mrs x2, {{trcdvcmr3|TRCDVCMR3}} 0xe5 0x20 0x31 0xd5 -# CHECK: mrs x5, trcdvcmr4 +# CHECK: mrs x5, {{trcdvcmr4|TRCDVCMR4}} 0xf5 0x24 0x31 0xd5 -# CHECK: mrs x21, trcdvcmr5 +# CHECK: mrs x21, {{trcdvcmr5|TRCDVCMR5}} 0xe5 0x28 0x31 0xd5 -# CHECK: mrs x5, trcdvcmr6 +# CHECK: mrs x5, {{trcdvcmr6|TRCDVCMR6}} 0xe1 0x2c 0x31 0xd5 -# CHECK: mrs x1, trcdvcmr7 +# CHECK: mrs x1, {{trcdvcmr7|TRCDVCMR7}} 0x15 0x30 0x31 0xd5 -# CHECK: mrs x21, trccidcvr0 +# CHECK: mrs x21, {{trccidcvr0|TRCCIDCVR0}} 0x18 0x32 0x31 0xd5 -# CHECK: mrs x24, trccidcvr1 +# CHECK: mrs x24, {{trccidcvr1|TRCCIDCVR1}} 0x18 0x34 0x31 0xd5 -# CHECK: mrs x24, trccidcvr2 +# CHECK: mrs x24, {{trccidcvr2|TRCCIDCVR2}} 0xc 0x36 0x31 0xd5 -# CHECK: mrs x12, trccidcvr3 +# CHECK: mrs x12, {{trccidcvr3|TRCCIDCVR3}} 0xa 0x38 0x31 0xd5 -# CHECK: mrs x10, trccidcvr4 +# CHECK: mrs x10, {{trccidcvr4|TRCCIDCVR4}} 0x9 0x3a 0x31 0xd5 -# CHECK: mrs x9, trccidcvr5 +# CHECK: mrs x9, {{trccidcvr5|TRCCIDCVR5}} 0x6 0x3c 0x31 0xd5 -# CHECK: mrs x6, trccidcvr6 +# CHECK: mrs x6, {{trccidcvr6|TRCCIDCVR6}} 0x14 0x3e 0x31 0xd5 -# CHECK: mrs x20, trccidcvr7 +# CHECK: mrs x20, {{trccidcvr7|TRCCIDCVR7}} 0x34 0x30 0x31 0xd5 -# CHECK: mrs x20, trcvmidcvr0 +# CHECK: mrs x20, {{trcvmidcvr0|TRCVMIDCVR0}} 0x34 0x32 0x31 0xd5 -# CHECK: mrs x20, trcvmidcvr1 +# CHECK: mrs x20, {{trcvmidcvr1|TRCVMIDCVR1}} 0x3a 0x34 0x31 0xd5 -# CHECK: mrs x26, trcvmidcvr2 +# CHECK: mrs x26, {{trcvmidcvr2|TRCVMIDCVR2}} 0x21 0x36 0x31 0xd5 -# CHECK: mrs x1, trcvmidcvr3 +# CHECK: mrs x1, {{trcvmidcvr3|TRCVMIDCVR3}} 0x2e 0x38 0x31 0xd5 -# CHECK: mrs x14, trcvmidcvr4 +# CHECK: mrs x14, {{trcvmidcvr4|TRCVMIDCVR4}} 0x3b 0x3a 0x31 0xd5 -# CHECK: mrs x27, trcvmidcvr5 +# CHECK: mrs x27, {{trcvmidcvr5|TRCVMIDCVR5}} 0x3d 0x3c 0x31 0xd5 -# CHECK: mrs x29, trcvmidcvr6 +# CHECK: mrs x29, {{trcvmidcvr6|TRCVMIDCVR6}} 0x31 0x3e 0x31 0xd5 -# CHECK: mrs x17, trcvmidcvr7 +# CHECK: mrs x17, {{trcvmidcvr7|TRCVMIDCVR7}} 0x4a 0x30 0x31 0xd5 -# CHECK: mrs x10, trccidcctlr0 +# CHECK: mrs x10, {{trccidcctlr0|TRCCIDCCTLR0}} 0x44 0x31 0x31 0xd5 -# CHECK: mrs x4, trccidcctlr1 +# CHECK: mrs x4, {{trccidcctlr1|TRCCIDCCTLR1}} 0x49 0x32 0x31 0xd5 -# CHECK: mrs x9, trcvmidcctlr0 +# CHECK: mrs x9, {{trcvmidcctlr0|TRCVMIDCCTLR0}} 0x4b 0x33 0x31 0xd5 -# CHECK: mrs x11, trcvmidcctlr1 +# CHECK: mrs x11, {{trcvmidcctlr1|TRCVMIDCCTLR1}} 0x96 0x70 0x31 0xd5 -# CHECK: mrs x22, trcitctrl +# CHECK: mrs x22, {{trcitctrl|TRCITCTRL}} 0xd7 0x78 0x31 0xd5 -# CHECK: mrs x23, trcclaimset +# CHECK: mrs x23, {{trcclaimset|TRCCLAIMSET}} 0xce 0x79 0x31 0xd5 -# CHECK: mrs x14, trcclaimclr +# CHECK: mrs x14, {{trcclaimclr|TRCCLAIMCLR}} 0x9c 0x10 0x11 0xd5 -# CHECK: msr trcoslar, x28 +# CHECK: msr {{trcoslar|TRCOSLAR}}, x28 0xce 0x7c 0x11 0xd5 -# CHECK: msr trclar, x14 +# CHECK: msr {{trclar|TRCLAR}}, x14 0xa 0x1 0x11 0xd5 -# CHECK: msr trcprgctlr, x10 +# CHECK: msr {{trcprgctlr|TRCPRGCTLR}}, x10 0x1b 0x2 0x11 0xd5 -# CHECK: msr trcprocselr, x27 +# CHECK: msr {{trcprocselr|TRCPROCSELR}}, x27 0x18 0x4 0x11 0xd5 -# CHECK: msr trcconfigr, x24 +# CHECK: msr {{trcconfigr|TRCCONFIGR}}, x24 0x8 0x6 0x11 0xd5 -# CHECK: msr trcauxctlr, x8 +# CHECK: msr {{trcauxctlr|TRCAUXCTLR}}, x8 0x10 0x8 0x11 0xd5 -# CHECK: msr trceventctl0r, x16 +# CHECK: msr {{trceventctl0r|TRCEVENTCTL0R}}, x16 0x1b 0x9 0x11 0xd5 -# CHECK: msr trceventctl1r, x27 +# CHECK: msr {{trceventctl1r|TRCEVENTCTL1R}}, x27 0x1a 0xb 0x11 0xd5 -# CHECK: msr trcstallctlr, x26 +# CHECK: msr {{trcstallctlr|TRCSTALLCTLR}}, x26 0x0 0xc 0x11 0xd5 -# CHECK: msr trctsctlr, x0 +# CHECK: msr {{trctsctlr|TRCTSCTLR}}, x0 0xe 0xd 0x11 0xd5 -# CHECK: msr trcsyncpr, x14 +# CHECK: msr {{trcsyncpr|TRCSYNCPR}}, x14 0x8 0xe 0x11 0xd5 -# CHECK: msr trcccctlr, x8 +# CHECK: msr {{trcccctlr|TRCCCCTLR}}, x8 0x6 0xf 0x11 0xd5 -# CHECK: msr trcbbctlr, x6 +# CHECK: msr {{trcbbctlr|TRCBBCTLR}}, x6 0x37 0x0 0x11 0xd5 -# CHECK: msr trctraceidr, x23 +# CHECK: msr {{trctraceidr|TRCTRACEIDR}}, x23 0x25 0x1 0x11 0xd5 -# CHECK: msr trcqctlr, x5 +# CHECK: msr {{trcqctlr|TRCQCTLR}}, x5 0x40 0x0 0x11 0xd5 -# CHECK: msr trcvictlr, x0 +# CHECK: msr {{trcvictlr|TRCVICTLR}}, x0 0x40 0x1 0x11 0xd5 -# CHECK: msr trcviiectlr, x0 +# CHECK: msr {{trcviiectlr|TRCVIIECTLR}}, x0 0x41 0x2 0x11 0xd5 -# CHECK: msr trcvissctlr, x1 +# CHECK: msr {{trcvissctlr|TRCVISSCTLR}}, x1 0x40 0x3 0x11 0xd5 -# CHECK: msr trcvipcssctlr, x0 +# CHECK: msr {{trcvipcssctlr|TRCVIPCSSCTLR}}, x0 0x47 0x8 0x11 0xd5 -# CHECK: msr trcvdctlr, x7 +# CHECK: msr {{trcvdctlr|TRCVDCTLR}}, x7 0x52 0x9 0x11 0xd5 -# CHECK: msr trcvdsacctlr, x18 +# CHECK: msr {{trcvdsacctlr|TRCVDSACCTLR}}, x18 0x58 0xa 0x11 0xd5 -# CHECK: msr trcvdarcctlr, x24 +# CHECK: msr {{trcvdarcctlr|TRCVDARCCTLR}}, x24 0x9c 0x0 0x11 0xd5 -# CHECK: msr trcseqevr0, x28 +# CHECK: msr {{trcseqevr0|TRCSEQEVR0}}, x28 0x95 0x1 0x11 0xd5 -# CHECK: msr trcseqevr1, x21 +# CHECK: msr {{trcseqevr1|TRCSEQEVR1}}, x21 0x90 0x2 0x11 0xd5 -# CHECK: msr trcseqevr2, x16 +# CHECK: msr {{trcseqevr2|TRCSEQEVR2}}, x16 0x90 0x6 0x11 0xd5 -# CHECK: msr trcseqrstevr, x16 +# CHECK: msr {{trcseqrstevr|TRCSEQRSTEVR}}, x16 0x99 0x7 0x11 0xd5 -# CHECK: msr trcseqstr, x25 +# CHECK: msr {{trcseqstr|TRCSEQSTR}}, x25 0x9d 0x8 0x11 0xd5 -# CHECK: msr trcextinselr, x29 +# CHECK: msr {{trcextinselr|TRCEXTINSELR}}, x29 0xb4 0x0 0x11 0xd5 -# CHECK: msr trccntrldvr0, x20 +# CHECK: msr {{trccntrldvr0|TRCCNTRLDVR0}}, x20 0xb4 0x1 0x11 0xd5 -# CHECK: msr trccntrldvr1, x20 +# CHECK: msr {{trccntrldvr1|TRCCNTRLDVR1}}, x20 0xb6 0x2 0x11 0xd5 -# CHECK: msr trccntrldvr2, x22 +# CHECK: msr {{trccntrldvr2|TRCCNTRLDVR2}}, x22 0xac 0x3 0x11 0xd5 -# CHECK: msr trccntrldvr3, x12 +# CHECK: msr {{trccntrldvr3|TRCCNTRLDVR3}}, x12 0xb4 0x4 0x11 0xd5 -# CHECK: msr trccntctlr0, x20 +# CHECK: msr {{trccntctlr0|TRCCNTCTLR0}}, x20 0xa4 0x5 0x11 0xd5 -# CHECK: msr trccntctlr1, x4 +# CHECK: msr {{trccntctlr1|TRCCNTCTLR1}}, x4 0xa8 0x6 0x11 0xd5 -# CHECK: msr trccntctlr2, x8 +# CHECK: msr {{trccntctlr2|TRCCNTCTLR2}}, x8 0xb0 0x7 0x11 0xd5 -# CHECK: msr trccntctlr3, x16 +# CHECK: msr {{trccntctlr3|TRCCNTCTLR3}}, x16 0xa5 0x8 0x11 0xd5 -# CHECK: msr trccntvr0, x5 +# CHECK: msr {{trccntvr0|TRCCNTVR0}}, x5 0xbb 0x9 0x11 0xd5 -# CHECK: msr trccntvr1, x27 +# CHECK: msr {{trccntvr1|TRCCNTVR1}}, x27 0xb5 0xa 0x11 0xd5 -# CHECK: msr trccntvr2, x21 +# CHECK: msr {{trccntvr2|TRCCNTVR2}}, x21 0xa8 0xb 0x11 0xd5 -# CHECK: msr trccntvr3, x8 +# CHECK: msr {{trccntvr3|TRCCNTVR3}}, x8 0xe6 0x0 0x11 0xd5 -# CHECK: msr trcimspec0, x6 +# CHECK: msr {{trcimspec0|TRCIMSPEC0}}, x6 0xfb 0x1 0x11 0xd5 -# CHECK: msr trcimspec1, x27 +# CHECK: msr {{trcimspec1|TRCIMSPEC1}}, x27 0xf7 0x2 0x11 0xd5 -# CHECK: msr trcimspec2, x23 +# CHECK: msr {{trcimspec2|TRCIMSPEC2}}, x23 0xef 0x3 0x11 0xd5 -# CHECK: msr trcimspec3, x15 +# CHECK: msr {{trcimspec3|TRCIMSPEC3}}, x15 0xed 0x4 0x11 0xd5 -# CHECK: msr trcimspec4, x13 +# CHECK: msr {{trcimspec4|TRCIMSPEC4}}, x13 0xf9 0x5 0x11 0xd5 -# CHECK: msr trcimspec5, x25 +# CHECK: msr {{trcimspec5|TRCIMSPEC5}}, x25 0xf3 0x6 0x11 0xd5 -# CHECK: msr trcimspec6, x19 +# CHECK: msr {{trcimspec6|TRCIMSPEC6}}, x19 0xfb 0x7 0x11 0xd5 -# CHECK: msr trcimspec7, x27 +# CHECK: msr {{trcimspec7|TRCIMSPEC7}}, x27 0x4 0x12 0x11 0xd5 -# CHECK: msr trcrsctlr2, x4 +# CHECK: msr {{trcrsctlr2|TRCRSCTLR2}}, x4 0x0 0x13 0x11 0xd5 -# CHECK: msr trcrsctlr3, x0 +# CHECK: msr {{trcrsctlr3|TRCRSCTLR3}}, x0 0x15 0x14 0x11 0xd5 -# CHECK: msr trcrsctlr4, x21 +# CHECK: msr {{trcrsctlr4|TRCRSCTLR4}}, x21 0x8 0x15 0x11 0xd5 -# CHECK: msr trcrsctlr5, x8 +# CHECK: msr {{trcrsctlr5|TRCRSCTLR5}}, x8 0x14 0x16 0x11 0xd5 -# CHECK: msr trcrsctlr6, x20 +# CHECK: msr {{trcrsctlr6|TRCRSCTLR6}}, x20 0xb 0x17 0x11 0xd5 -# CHECK: msr trcrsctlr7, x11 +# CHECK: msr {{trcrsctlr7|TRCRSCTLR7}}, x11 0x12 0x18 0x11 0xd5 -# CHECK: msr trcrsctlr8, x18 +# CHECK: msr {{trcrsctlr8|TRCRSCTLR8}}, x18 0x18 0x19 0x11 0xd5 -# CHECK: msr trcrsctlr9, x24 +# CHECK: msr {{trcrsctlr9|TRCRSCTLR9}}, x24 0xf 0x1a 0x11 0xd5 -# CHECK: msr trcrsctlr10, x15 +# CHECK: msr {{trcrsctlr10|TRCRSCTLR10}}, x15 0x15 0x1b 0x11 0xd5 -# CHECK: msr trcrsctlr11, x21 +# CHECK: msr {{trcrsctlr11|TRCRSCTLR11}}, x21 0x4 0x1c 0x11 0xd5 -# CHECK: msr trcrsctlr12, x4 +# CHECK: msr {{trcrsctlr12|TRCRSCTLR12}}, x4 0x1c 0x1d 0x11 0xd5 -# CHECK: msr trcrsctlr13, x28 +# CHECK: msr {{trcrsctlr13|TRCRSCTLR13}}, x28 0x3 0x1e 0x11 0xd5 -# CHECK: msr trcrsctlr14, x3 +# CHECK: msr {{trcrsctlr14|TRCRSCTLR14}}, x3 0x14 0x1f 0x11 0xd5 -# CHECK: msr trcrsctlr15, x20 +# CHECK: msr {{trcrsctlr15|TRCRSCTLR15}}, x20 0x2c 0x10 0x11 0xd5 -# CHECK: msr trcrsctlr16, x12 +# CHECK: msr {{trcrsctlr16|TRCRSCTLR16}}, x12 0x31 0x11 0x11 0xd5 -# CHECK: msr trcrsctlr17, x17 +# CHECK: msr {{trcrsctlr17|TRCRSCTLR17}}, x17 0x2a 0x12 0x11 0xd5 -# CHECK: msr trcrsctlr18, x10 +# CHECK: msr {{trcrsctlr18|TRCRSCTLR18}}, x10 0x2b 0x13 0x11 0xd5 -# CHECK: msr trcrsctlr19, x11 +# CHECK: msr {{trcrsctlr19|TRCRSCTLR19}}, x11 0x23 0x14 0x11 0xd5 -# CHECK: msr trcrsctlr20, x3 +# CHECK: msr {{trcrsctlr20|TRCRSCTLR20}}, x3 0x32 0x15 0x11 0xd5 -# CHECK: msr trcrsctlr21, x18 +# CHECK: msr {{trcrsctlr21|TRCRSCTLR21}}, x18 0x3a 0x16 0x11 0xd5 -# CHECK: msr trcrsctlr22, x26 +# CHECK: msr {{trcrsctlr22|TRCRSCTLR22}}, x26 0x25 0x17 0x11 0xd5 -# CHECK: msr trcrsctlr23, x5 +# CHECK: msr {{trcrsctlr23|TRCRSCTLR23}}, x5 0x39 0x18 0x11 0xd5 -# CHECK: msr trcrsctlr24, x25 +# CHECK: msr {{trcrsctlr24|TRCRSCTLR24}}, x25 0x25 0x19 0x11 0xd5 -# CHECK: msr trcrsctlr25, x5 +# CHECK: msr {{trcrsctlr25|TRCRSCTLR25}}, x5 0x24 0x1a 0x11 0xd5 -# CHECK: msr trcrsctlr26, x4 +# CHECK: msr {{trcrsctlr26|TRCRSCTLR26}}, x4 0x34 0x1b 0x11 0xd5 -# CHECK: msr trcrsctlr27, x20 +# CHECK: msr {{trcrsctlr27|TRCRSCTLR27}}, x20 0x25 0x1c 0x11 0xd5 -# CHECK: msr trcrsctlr28, x5 +# CHECK: msr {{trcrsctlr28|TRCRSCTLR28}}, x5 0x2a 0x1d 0x11 0xd5 -# CHECK: msr trcrsctlr29, x10 +# CHECK: msr {{trcrsctlr29|TRCRSCTLR29}}, x10 0x38 0x1e 0x11 0xd5 -# CHECK: msr trcrsctlr30, x24 +# CHECK: msr {{trcrsctlr30|TRCRSCTLR30}}, x24 0x34 0x1f 0x11 0xd5 -# CHECK: msr trcrsctlr31, x20 +# CHECK: msr {{trcrsctlr31|TRCRSCTLR31}}, x20 0x57 0x10 0x11 0xd5 -# CHECK: msr trcssccr0, x23 +# CHECK: msr {{trcssccr0|TRCSSCCR0}}, x23 0x5b 0x11 0x11 0xd5 -# CHECK: msr trcssccr1, x27 +# CHECK: msr {{trcssccr1|TRCSSCCR1}}, x27 0x5b 0x12 0x11 0xd5 -# CHECK: msr trcssccr2, x27 +# CHECK: msr {{trcssccr2|TRCSSCCR2}}, x27 0x46 0x13 0x11 0xd5 -# CHECK: msr trcssccr3, x6 +# CHECK: msr {{trcssccr3|TRCSSCCR3}}, x6 0x43 0x14 0x11 0xd5 -# CHECK: msr trcssccr4, x3 +# CHECK: msr {{trcssccr4|TRCSSCCR4}}, x3 0x4c 0x15 0x11 0xd5 -# CHECK: msr trcssccr5, x12 +# CHECK: msr {{trcssccr5|TRCSSCCR5}}, x12 0x47 0x16 0x11 0xd5 -# CHECK: msr trcssccr6, x7 +# CHECK: msr {{trcssccr6|TRCSSCCR6}}, x7 0x46 0x17 0x11 0xd5 -# CHECK: msr trcssccr7, x6 +# CHECK: msr {{trcssccr7|TRCSSCCR7}}, x6 0x54 0x18 0x11 0xd5 -# CHECK: msr trcsscsr0, x20 +# CHECK: msr {{trcsscsr0|TRCSSCSR0}}, x20 0x51 0x19 0x11 0xd5 -# CHECK: msr trcsscsr1, x17 +# CHECK: msr {{trcsscsr1|TRCSSCSR1}}, x17 0x4b 0x1a 0x11 0xd5 -# CHECK: msr trcsscsr2, x11 +# CHECK: msr {{trcsscsr2|TRCSSCSR2}}, x11 0x44 0x1b 0x11 0xd5 -# CHECK: msr trcsscsr3, x4 +# CHECK: msr {{trcsscsr3|TRCSSCSR3}}, x4 0x4e 0x1c 0x11 0xd5 -# CHECK: msr trcsscsr4, x14 +# CHECK: msr {{trcsscsr4|TRCSSCSR4}}, x14 0x56 0x1d 0x11 0xd5 -# CHECK: msr trcsscsr5, x22 +# CHECK: msr {{trcsscsr5|TRCSSCSR5}}, x22 0x43 0x1e 0x11 0xd5 -# CHECK: msr trcsscsr6, x3 +# CHECK: msr {{trcsscsr6|TRCSSCSR6}}, x3 0x4b 0x1f 0x11 0xd5 -# CHECK: msr trcsscsr7, x11 +# CHECK: msr {{trcsscsr7|TRCSSCSR7}}, x11 0x83 0x14 0x11 0xd5 -# CHECK: msr trcpdcr, x3 +# CHECK: msr {{trcpdcr|TRCPDCR}}, x3 0x6 0x20 0x11 0xd5 -# CHECK: msr trcacvr0, x6 +# CHECK: msr {{trcacvr0|TRCACVR0}}, x6 0x14 0x22 0x11 0xd5 -# CHECK: msr trcacvr1, x20 +# CHECK: msr {{trcacvr1|TRCACVR1}}, x20 0x19 0x24 0x11 0xd5 -# CHECK: msr trcacvr2, x25 +# CHECK: msr {{trcacvr2|TRCACVR2}}, x25 0x1 0x26 0x11 0xd5 -# CHECK: msr trcacvr3, x1 +# CHECK: msr {{trcacvr3|TRCACVR3}}, x1 0x1c 0x28 0x11 0xd5 -# CHECK: msr trcacvr4, x28 +# CHECK: msr {{trcacvr4|TRCACVR4}}, x28 0xf 0x2a 0x11 0xd5 -# CHECK: msr trcacvr5, x15 +# CHECK: msr {{trcacvr5|TRCACVR5}}, x15 0x19 0x2c 0x11 0xd5 -# CHECK: msr trcacvr6, x25 +# CHECK: msr {{trcacvr6|TRCACVR6}}, x25 0xc 0x2e 0x11 0xd5 -# CHECK: msr trcacvr7, x12 +# CHECK: msr {{trcacvr7|TRCACVR7}}, x12 0x25 0x20 0x11 0xd5 -# CHECK: msr trcacvr8, x5 +# CHECK: msr {{trcacvr8|TRCACVR8}}, x5 0x39 0x22 0x11 0xd5 -# CHECK: msr trcacvr9, x25 +# CHECK: msr {{trcacvr9|TRCACVR9}}, x25 0x2d 0x24 0x11 0xd5 -# CHECK: msr trcacvr10, x13 +# CHECK: msr {{trcacvr10|TRCACVR10}}, x13 0x2a 0x26 0x11 0xd5 -# CHECK: msr trcacvr11, x10 +# CHECK: msr {{trcacvr11|TRCACVR11}}, x10 0x33 0x28 0x11 0xd5 -# CHECK: msr trcacvr12, x19 +# CHECK: msr {{trcacvr12|TRCACVR12}}, x19 0x2a 0x2a 0x11 0xd5 -# CHECK: msr trcacvr13, x10 +# CHECK: msr {{trcacvr13|TRCACVR13}}, x10 0x33 0x2c 0x11 0xd5 -# CHECK: msr trcacvr14, x19 +# CHECK: msr {{trcacvr14|TRCACVR14}}, x19 0x22 0x2e 0x11 0xd5 -# CHECK: msr trcacvr15, x2 +# CHECK: msr {{trcacvr15|TRCACVR15}}, x2 0x4f 0x20 0x11 0xd5 -# CHECK: msr trcacatr0, x15 +# CHECK: msr {{trcacatr0|TRCACATR0}}, x15 0x4d 0x22 0x11 0xd5 -# CHECK: msr trcacatr1, x13 +# CHECK: msr {{trcacatr1|TRCACATR1}}, x13 0x48 0x24 0x11 0xd5 -# CHECK: msr trcacatr2, x8 +# CHECK: msr {{trcacatr2|TRCACATR2}}, x8 0x41 0x26 0x11 0xd5 -# CHECK: msr trcacatr3, x1 +# CHECK: msr {{trcacatr3|TRCACATR3}}, x1 0x4b 0x28 0x11 0xd5 -# CHECK: msr trcacatr4, x11 +# CHECK: msr {{trcacatr4|TRCACATR4}}, x11 0x48 0x2a 0x11 0xd5 -# CHECK: msr trcacatr5, x8 +# CHECK: msr {{trcacatr5|TRCACATR5}}, x8 0x58 0x2c 0x11 0xd5 -# CHECK: msr trcacatr6, x24 +# CHECK: msr {{trcacatr6|TRCACATR6}}, x24 0x46 0x2e 0x11 0xd5 -# CHECK: msr trcacatr7, x6 +# CHECK: msr {{trcacatr7|TRCACATR7}}, x6 0x77 0x20 0x11 0xd5 -# CHECK: msr trcacatr8, x23 +# CHECK: msr {{trcacatr8|TRCACATR8}}, x23 0x65 0x22 0x11 0xd5 -# CHECK: msr trcacatr9, x5 +# CHECK: msr {{trcacatr9|TRCACATR9}}, x5 0x6b 0x24 0x11 0xd5 -# CHECK: msr trcacatr10, x11 +# CHECK: msr {{trcacatr10|TRCACATR10}}, x11 0x6b 0x26 0x11 0xd5 -# CHECK: msr trcacatr11, x11 +# CHECK: msr {{trcacatr11|TRCACATR11}}, x11 0x63 0x28 0x11 0xd5 -# CHECK: msr trcacatr12, x3 +# CHECK: msr {{trcacatr12|TRCACATR12}}, x3 0x7c 0x2a 0x11 0xd5 -# CHECK: msr trcacatr13, x28 +# CHECK: msr {{trcacatr13|TRCACATR13}}, x28 0x79 0x2c 0x11 0xd5 -# CHECK: msr trcacatr14, x25 +# CHECK: msr {{trcacatr14|TRCACATR14}}, x25 0x64 0x2e 0x11 0xd5 -# CHECK: msr trcacatr15, x4 +# CHECK: msr {{trcacatr15|TRCACATR15}}, x4 0x86 0x20 0x11 0xd5 -# CHECK: msr trcdvcvr0, x6 +# CHECK: msr {{trcdvcvr0|TRCDVCVR0}}, x6 0x83 0x24 0x11 0xd5 -# CHECK: msr trcdvcvr1, x3 +# CHECK: msr {{trcdvcvr1|TRCDVCVR1}}, x3 0x85 0x28 0x11 0xd5 -# CHECK: msr trcdvcvr2, x5 +# CHECK: msr {{trcdvcvr2|TRCDVCVR2}}, x5 0x8b 0x2c 0x11 0xd5 -# CHECK: msr trcdvcvr3, x11 +# CHECK: msr {{trcdvcvr3|TRCDVCVR3}}, x11 0xa9 0x20 0x11 0xd5 -# CHECK: msr trcdvcvr4, x9 +# CHECK: msr {{trcdvcvr4|TRCDVCVR4}}, x9 0xae 0x24 0x11 0xd5 -# CHECK: msr trcdvcvr5, x14 +# CHECK: msr {{trcdvcvr5|TRCDVCVR5}}, x14 0xaa 0x28 0x11 0xd5 -# CHECK: msr trcdvcvr6, x10 +# CHECK: msr {{trcdvcvr6|TRCDVCVR6}}, x10 0xac 0x2c 0x11 0xd5 -# CHECK: msr trcdvcvr7, x12 +# CHECK: msr {{trcdvcvr7|TRCDVCVR7}}, x12 0xc8 0x20 0x11 0xd5 -# CHECK: msr trcdvcmr0, x8 +# CHECK: msr {{trcdvcmr0|TRCDVCMR0}}, x8 0xc8 0x24 0x11 0xd5 -# CHECK: msr trcdvcmr1, x8 +# CHECK: msr {{trcdvcmr1|TRCDVCMR1}}, x8 0xd6 0x28 0x11 0xd5 -# CHECK: msr trcdvcmr2, x22 +# CHECK: msr {{trcdvcmr2|TRCDVCMR2}}, x22 0xd6 0x2c 0x11 0xd5 -# CHECK: msr trcdvcmr3, x22 +# CHECK: msr {{trcdvcmr3|TRCDVCMR3}}, x22 0xe5 0x20 0x11 0xd5 -# CHECK: msr trcdvcmr4, x5 +# CHECK: msr {{trcdvcmr4|TRCDVCMR4}}, x5 0xf0 0x24 0x11 0xd5 -# CHECK: msr trcdvcmr5, x16 +# CHECK: msr {{trcdvcmr5|TRCDVCMR5}}, x16 0xfb 0x28 0x11 0xd5 -# CHECK: msr trcdvcmr6, x27 +# CHECK: msr {{trcdvcmr6|TRCDVCMR6}}, x27 0xf5 0x2c 0x11 0xd5 -# CHECK: msr trcdvcmr7, x21 +# CHECK: msr {{trcdvcmr7|TRCDVCMR7}}, x21 0x8 0x30 0x11 0xd5 -# CHECK: msr trccidcvr0, x8 +# CHECK: msr {{trccidcvr0|TRCCIDCVR0}}, x8 0x6 0x32 0x11 0xd5 -# CHECK: msr trccidcvr1, x6 +# CHECK: msr {{trccidcvr1|TRCCIDCVR1}}, x6 0x9 0x34 0x11 0xd5 -# CHECK: msr trccidcvr2, x9 +# CHECK: msr {{trccidcvr2|TRCCIDCVR2}}, x9 0x8 0x36 0x11 0xd5 -# CHECK: msr trccidcvr3, x8 +# CHECK: msr {{trccidcvr3|TRCCIDCVR3}}, x8 0x3 0x38 0x11 0xd5 -# CHECK: msr trccidcvr4, x3 +# CHECK: msr {{trccidcvr4|TRCCIDCVR4}}, x3 0x15 0x3a 0x11 0xd5 -# CHECK: msr trccidcvr5, x21 +# CHECK: msr {{trccidcvr5|TRCCIDCVR5}}, x21 0xc 0x3c 0x11 0xd5 -# CHECK: msr trccidcvr6, x12 +# CHECK: msr {{trccidcvr6|TRCCIDCVR6}}, x12 0x7 0x3e 0x11 0xd5 -# CHECK: msr trccidcvr7, x7 +# CHECK: msr {{trccidcvr7|TRCCIDCVR7}}, x7 0x24 0x30 0x11 0xd5 -# CHECK: msr trcvmidcvr0, x4 +# CHECK: msr {{trcvmidcvr0|TRCVMIDCVR0}}, x4 0x23 0x32 0x11 0xd5 -# CHECK: msr trcvmidcvr1, x3 +# CHECK: msr {{trcvmidcvr1|TRCVMIDCVR1}}, x3 0x29 0x34 0x11 0xd5 -# CHECK: msr trcvmidcvr2, x9 +# CHECK: msr {{trcvmidcvr2|TRCVMIDCVR2}}, x9 0x31 0x36 0x11 0xd5 -# CHECK: msr trcvmidcvr3, x17 +# CHECK: msr {{trcvmidcvr3|TRCVMIDCVR3}}, x17 0x2e 0x38 0x11 0xd5 -# CHECK: msr trcvmidcvr4, x14 +# CHECK: msr {{trcvmidcvr4|TRCVMIDCVR4}}, x14 0x2c 0x3a 0x11 0xd5 -# CHECK: msr trcvmidcvr5, x12 +# CHECK: msr {{trcvmidcvr5|TRCVMIDCVR5}}, x12 0x2a 0x3c 0x11 0xd5 -# CHECK: msr trcvmidcvr6, x10 +# CHECK: msr {{trcvmidcvr6|TRCVMIDCVR6}}, x10 0x23 0x3e 0x11 0xd5 -# CHECK: msr trcvmidcvr7, x3 +# CHECK: msr {{trcvmidcvr7|TRCVMIDCVR7}}, x3 0x4e 0x30 0x11 0xd5 -# CHECK: msr trccidcctlr0, x14 +# CHECK: msr {{trccidcctlr0|TRCCIDCCTLR0}}, x14 0x56 0x31 0x11 0xd5 -# CHECK: msr trccidcctlr1, x22 +# CHECK: msr {{trccidcctlr1|TRCCIDCCTLR1}}, x22 0x48 0x32 0x11 0xd5 -# CHECK: msr trcvmidcctlr0, x8 +# CHECK: msr {{trcvmidcctlr0|TRCVMIDCCTLR0}}, x8 0x4f 0x33 0x11 0xd5 -# CHECK: msr trcvmidcctlr1, x15 +# CHECK: msr {{trcvmidcctlr1|TRCVMIDCCTLR1}}, x15 0x81 0x70 0x11 0xd5 -# CHECK: msr trcitctrl, x1 +# CHECK: msr {{trcitctrl|TRCITCTRL}}, x1 0xc7 0x78 0x11 0xd5 -# CHECK: msr trcclaimset, x7 +# CHECK: msr {{trcclaimset|TRCCLAIMSET}}, x7 0xdd 0x79 0x11 0xd5 -# CHECK: msr trcclaimclr, x29 +# CHECK: msr {{trcclaimclr|TRCCLAIMCLR}}, x29 diff --git a/test/MC/Disassembler/ARM/invalid-thumbv7.txt b/test/MC/Disassembler/ARM/invalid-thumbv7.txt index 2c84b8a..5257633 100644 --- a/test/MC/Disassembler/ARM/invalid-thumbv7.txt +++ b/test/MC/Disassembler/ARM/invalid-thumbv7.txt @@ -21,17 +21,6 @@ # CHECK: warning: invalid instruction encoding # CHECK-NEXT: [0xaf 0xf7 0x44 0x8b] -# Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# if cond = '1110' then UNDEFINED -[0x6f 0xde] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0x6f 0xde] - #------------------------------------------------------------------------------ # Undefined encoding for it #------------------------------------------------------------------------------ @@ -249,34 +238,6 @@ # CHECK-NEXT: [0xe4 0xe9 0x02 0x46] #------------------------------------------------------------------------------ -# Undefined encodings for NEON/VFP instructions with invalid predicate bits -#------------------------------------------------------------------------------ - -# VABS -[0x40 0xde 0x00 0x0a] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0x40 0xde 0x00 0x0a] - - -# VMLA -[0xf0 0xde 0xe0 0x0b] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0xf0 0xde 0xe0 0x0b] - -# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110) - -# VMOV -[0x00 0xde 0x10 0x0b] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0x00 0xde 0x10 0x0b] - -# VDUP -[0xff 0xde 0xf0 0xfb] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0xff 0xde 0xf0 0xfb] - - -#------------------------------------------------------------------------------ # Undefined encodings for NEON vld instructions #------------------------------------------------------------------------------ diff --git a/test/MC/Disassembler/ARM64/lit.local.cfg b/test/MC/Disassembler/ARM64/lit.local.cfg deleted file mode 100644 index 46a9468..0000000 --- a/test/MC/Disassembler/ARM64/lit.local.cfg +++ /dev/null @@ -1,5 +0,0 @@ -config.suffixes = ['.txt'] - -targets = set(config.root.targets_to_build.split()) -if not 'ARM64' in targets: - config.unsupported = True diff --git a/test/MC/Disassembler/Mips/mips32r6.txt b/test/MC/Disassembler/Mips/mips32r6.txt new file mode 100644 index 0000000..adbcd99 --- /dev/null +++ b/test/MC/Disassembler/Mips/mips32r6.txt @@ -0,0 +1,116 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 | FileCheck %s + +0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 +0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2 +0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 +0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 +0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 +0xe8 0x37 0x96 0xb8 # CHECK: balc 14572256 +0xc8 0x37 0x96 0xb8 # CHECK: bc 14572256 + +# FIXME: Don't check the immediate on these for the moment, the encode/decode +# functions are not inverses of eachother. +# The immediate should be 4 but the disassembler currently emits 8 +0x45 0x20 0x00 0x01 # CHECK: bc1eqz $f0, +0x45 0x3f 0x00 0x01 # CHECK: bc1eqz $f31, +0x45 0xa0 0x00 0x01 # CHECK: bc1nez $f0, +0x45 0xbf 0x00 0x01 # CHECK: bc1nez $f31, +# FIXME: Don't check the immediate on these for the moment, the encode/decode +# functions are not inverses of eachother. +# The immediate should be 8 but the disassembler currently emits 12 +0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, +0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, +0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, +0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, + +0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256 +# FIXME: Don't check the immediate on the bcczal's for the moment, the +# encode/decode functions are not inverses of eachother. +0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, +0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 +0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, +0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 +0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, +0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 +0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256 +0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 256 +0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, +0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256 +0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, +0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256 +0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 +0x18 0x02 0x01 0x4d # CHECK: blezalc $2, +0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 +0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4 +0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4 +0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4 +0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4 +0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4 +0x46 0x84 0x18 0x80 # CHECK: cmp.f.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x80 # CHECK: cmp.f.d $f2, $f3, $f4 +0x46 0x84 0x18 0x81 # CHECK: cmp.un.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4 +0x46 0x84 0x18 0x82 # CHECK: cmp.eq.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x82 # CHECK: cmp.eq.d $f2, $f3, $f4 +0x46 0x84 0x18 0x83 # CHECK: cmp.ueq.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4 +0x46 0x84 0x18 0x84 # CHECK: cmp.olt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x84 # CHECK: cmp.olt.d $f2, $f3, $f4 +0x46 0x84 0x18 0x85 # CHECK: cmp.ult.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4 +0x46 0x84 0x18 0x86 # CHECK: cmp.ole.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x86 # CHECK: cmp.ole.d $f2, $f3, $f4 +0x46 0x84 0x18 0x87 # CHECK: cmp.ule.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4 +0x46 0x84 0x18 0x88 # CHECK: cmp.sf.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x88 # CHECK: cmp.sf.d $f2, $f3, $f4 +0x46 0x84 0x18 0x89 # CHECK: cmp.ngle.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x89 # CHECK: cmp.ngle.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8a # CHECK: cmp.seq.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8b # CHECK: cmp.ngl.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8b # CHECK: cmp.ngl.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8c # CHECK: cmp.lt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8c # CHECK: cmp.lt.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8d # CHECK: cmp.nge.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8d # CHECK: cmp.nge.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8e # CHECK: cmp.le.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8e # CHECK: cmp.le.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8f # CHECK: cmp.ngt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8f # CHECK: cmp.ngt.d $f2, $f3, $f4 +0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4 +0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4 +# 0xf8 0x05 0x01 0x00 # CHECK-TODO: jialc $5, 256 +# 0xd8 0x05 0x01 0x00 # CHECK-TODO: jic $5, 256 +0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268 +0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 +0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4 +0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4 +0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4 +0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4 +0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4 +0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4 +0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 +0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 +0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 +0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 +0x46 0x22 0x08 0x10 # CHECK: sel.d $f0, $f1, $f2 +0x46 0x02 0x08 0x10 # CHECK: sel.s $f0, $f1, $f2 +0x00 0x64 0x10 0x35 # CHECK: seleqz $2, $3, $4 +0x00 0x64 0x10 0x37 # CHECK: selnez $2, $3, $4 +0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4 +0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4 +0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4 +0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4 +0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4 +0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4 +0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4 +0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4 +0x46 0x00 0x20 0x9a # CHECK: rint.s $f2, $f4 +0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4 +0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4 +0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4 diff --git a/test/MC/Disassembler/Mips/mips64r6.txt b/test/MC/Disassembler/Mips/mips64r6.txt new file mode 100644 index 0000000..f5bb14e --- /dev/null +++ b/test/MC/Disassembler/Mips/mips64r6.txt @@ -0,0 +1,129 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips64r6 | FileCheck %s + +0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 +0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2 +0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 +0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 +0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 +0xe8 0x37 0x96 0xb8 # CHECK: balc 14572256 +0xc8 0x37 0x96 0xb8 # CHECK: bc 14572256 + +# FIXME: Don't check the immediate on these for the moment, the encode/decode +# functions are not inverses of eachother. +# The immediate should be 4 but the disassembler currently emits 8 +0x45 0x20 0x00 0x01 # CHECK: bc1eqz $f0, +0x45 0x3f 0x00 0x01 # CHECK: bc1eqz $f31, +0x45 0xa0 0x00 0x01 # CHECK: bc1nez $f0, +0x45 0xbf 0x00 0x01 # CHECK: bc1nez $f31, +# FIXME: Don't check the immediate on these for the moment, the encode/decode +# functions are not inverses of eachother. +# The immediate should be 8 but the disassembler currently emits 12 +0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, +0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, +0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, +0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, + +0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256 +# FIXME: Don't check the immediate on the bcczal's for the moment, the +# encode/decode functions are not inverses of eachother. +0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, +0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 +0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, +0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 +0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, +0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 +0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256 +0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 256 +0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, +0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256 +0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, +0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256 +0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 +0x18 0x02 0x01 0x4d # CHECK: blezalc $2, +0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 +0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4 +0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4 +0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4 +0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4 +0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4 +0x46 0x84 0x18 0x80 # CHECK: cmp.f.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x80 # CHECK: cmp.f.d $f2, $f3, $f4 +0x46 0x84 0x18 0x81 # CHECK: cmp.un.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4 +0x46 0x84 0x18 0x82 # CHECK: cmp.eq.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x82 # CHECK: cmp.eq.d $f2, $f3, $f4 +0x46 0x84 0x18 0x83 # CHECK: cmp.ueq.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4 +0x46 0x84 0x18 0x84 # CHECK: cmp.olt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x84 # CHECK: cmp.olt.d $f2, $f3, $f4 +0x46 0x84 0x18 0x85 # CHECK: cmp.ult.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4 +0x46 0x84 0x18 0x86 # CHECK: cmp.ole.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x86 # CHECK: cmp.ole.d $f2, $f3, $f4 +0x46 0x84 0x18 0x87 # CHECK: cmp.ule.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4 +0x46 0x84 0x18 0x88 # CHECK: cmp.sf.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x88 # CHECK: cmp.sf.d $f2, $f3, $f4 +0x46 0x84 0x18 0x89 # CHECK: cmp.ngle.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x89 # CHECK: cmp.ngle.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8a # CHECK: cmp.seq.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8b # CHECK: cmp.ngl.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8b # CHECK: cmp.ngl.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8c # CHECK: cmp.lt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8c # CHECK: cmp.lt.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8d # CHECK: cmp.nge.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8d # CHECK: cmp.nge.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8e # CHECK: cmp.le.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8e # CHECK: cmp.le.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8f # CHECK: cmp.ngt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8f # CHECK: cmp.ngt.d $f2, $f3, $f4 +0x7c 0x43 0x23 0x64 # CHECK: dalign $4, $2, $3, 5 +0x74 0x62 0x12 0x34 # CHECK: daui $3, $2, 4660 +0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136 +0x04 0x7e 0xab 0xcd # CHECK: dati $3, -21555 +0x7c 0x02 0x20 0x24 # CHECK: dbitswap $4, $2 +0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4 +0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4 +# 0xf8 0x05 0x01 0x00 # CHECK-TODO: jialc $5, 256 +# 0xd8 0x05 0x01 0x00 # CHECK-TODO: jic $5, 256 +0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268 +0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 +0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4 +0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4 +0x00 0x64 0x10 0x9e # CHECK: ddiv $2, $3, $4 +0x00 0x64 0x10 0x9f # CHECK: ddivu $2, $3, $4 +0x00 0x64 0x10 0xde # CHECK: dmod $2, $3, $4 +0x00 0x64 0x10 0xdf # CHECK: dmodu $2, $3, $4 +0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4 +0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4 +0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4 +0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4 +0x00 0x64 0x10 0xb8 # CHECK: dmul $2, $3, $4 +0x00 0x64 0x10 0xf8 # CHECK: dmuh $2, $3, $4 +0x00 0x64 0x10 0xb9 # CHECK: dmulu $2, $3, $4 +0x00 0x64 0x10 0xf9 # CHECK: dmuhu $2, $3, $4 +0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 +0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 +0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 +0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 +0x46 0x22 0x08 0x10 # CHECK: sel.d $f0, $f1, $f2 +0x46 0x02 0x08 0x10 # CHECK: sel.s $f0, $f1, $f2 +0x00 0x64 0x10 0x35 # CHECK: seleqz $2, $3, $4 +0x00 0x64 0x10 0x37 # CHECK: selnez $2, $3, $4 +0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4 +0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4 +0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4 +0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4 +0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4 +0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4 +0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4 +0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4 +0x46 0x00 0x20 0x9a # CHECK: rint.s $f2, $f4 +0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4 +0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4 +0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4 diff --git a/test/MC/Disassembler/Mips/msa/test_2r.txt b/test/MC/Disassembler/Mips/msa/test_2r.txt new file mode 100644 index 0000000..7faa13c --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_2r.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x7b 0x00 0x4f 0x9e # CHECK: fill.b $w30, $9 +0x7b 0x01 0xbf 0xde # CHECK: fill.h $w31, $23 +0x7b 0x02 0xc4 0x1e # CHECK: fill.w $w16, $24 +0x7b 0x08 0x05 0x5e # CHECK: nloc.b $w21, $w0 +0x7b 0x09 0xfc 0x9e # CHECK: nloc.h $w18, $w31 +0x7b 0x0a 0xb8 0x9e # CHECK: nloc.w $w2, $w23 +0x7b 0x0b 0x51 0x1e # CHECK: nloc.d $w4, $w10 +0x7b 0x0c 0x17 0xde # CHECK: nlzc.b $w31, $w2 +0x7b 0x0d 0xb6 0xde # CHECK: nlzc.h $w27, $w22 +0x7b 0x0e 0xea 0x9e # CHECK: nlzc.w $w10, $w29 +0x7b 0x0f 0x4e 0x5e # CHECK: nlzc.d $w25, $w9 +0x7b 0x04 0x95 0x1e # CHECK: pcnt.b $w20, $w18 +0x7b 0x05 0x40 0x1e # CHECK: pcnt.h $w0, $w8 +0x7b 0x06 0x4d 0xde # CHECK: pcnt.w $w23, $w9 +0x7b 0x07 0xc5 0x5e # CHECK: pcnt.d $w21, $w24 diff --git a/test/MC/Disassembler/Mips/msa/test_2r_msa64.txt b/test/MC/Disassembler/Mips/msa/test_2r_msa64.txt new file mode 100644 index 0000000..f212390 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_2r_msa64.txt @@ -0,0 +1,3 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r2 -mattr=+msa | FileCheck %s + +0x7b 0x03 0x4e 0xde # CHECK: fill.d $w27, $9 diff --git a/test/MC/Disassembler/Mips/msa/test_2rf.txt b/test/MC/Disassembler/Mips/msa/test_2rf.txt new file mode 100644 index 0000000..e004f11 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_2rf.txt @@ -0,0 +1,34 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x7b 0x20 0x66 0x9e # CHECK: fclass.w $w26, $w12 +0x7b 0x21 0x8e 0x1e # CHECK: fclass.d $w24, $w17 +0x7b 0x30 0x02 0x1e # CHECK: fexupl.w $w8, $w0 +0x7b 0x31 0xec 0x5e # CHECK: fexupl.d $w17, $w29 +0x7b 0x32 0x23 0x5e # CHECK: fexupr.w $w13, $w4 +0x7b 0x33 0x11 0x5e # CHECK: fexupr.d $w5, $w2 +0x7b 0x3c 0xed 0x1e # CHECK: ffint_s.w $w20, $w29 +0x7b 0x3d 0x7b 0x1e # CHECK: ffint_s.d $w12, $w15 +0x7b 0x3e 0xd9 0xde # CHECK: ffint_u.w $w7, $w27 +0x7b 0x3f 0x84 0xde # CHECK: ffint_u.d $w19, $w16 +0x7b 0x34 0x6f 0xde # CHECK: ffql.w $w31, $w13 +0x7b 0x35 0x6b 0x1e # CHECK: ffql.d $w12, $w13 +0x7b 0x36 0xf6 0xde # CHECK: ffqr.w $w27, $w30 +0x7b 0x37 0x7f 0x9e # CHECK: ffqr.d $w30, $w15 +0x7b 0x2e 0xfe 0x5e # CHECK: flog2.w $w25, $w31 +0x7b 0x2f 0x54 0x9e # CHECK: flog2.d $w18, $w10 +0x7b 0x2c 0x79 0xde # CHECK: frint.w $w7, $w15 +0x7b 0x2d 0xb5 0x5e # CHECK: frint.d $w21, $w22 +0x7b 0x2a 0x04 0xde # CHECK: frcp.w $w19, $w0 +0x7b 0x2b 0x71 0x1e # CHECK: frcp.d $w4, $w14 +0x7b 0x28 0x8b 0x1e # CHECK: frsqrt.w $w12, $w17 +0x7b 0x29 0x5d 0xde # CHECK: frsqrt.d $w23, $w11 +0x7b 0x26 0x58 0x1e # CHECK: fsqrt.w $w0, $w11 +0x7b 0x27 0x63 0xde # CHECK: fsqrt.d $w15, $w12 +0x7b 0x38 0x2f 0x9e # CHECK: ftint_s.w $w30, $w5 +0x7b 0x39 0xb9 0x5e # CHECK: ftint_s.d $w5, $w23 +0x7b 0x3a 0x75 0x1e # CHECK: ftint_u.w $w20, $w14 +0x7b 0x3b 0xad 0xde # CHECK: ftint_u.d $w23, $w21 +0x7b 0x22 0x8f 0x5e # CHECK: ftrunc_s.w $w29, $w17 +0x7b 0x23 0xdb 0x1e # CHECK: ftrunc_s.d $w12, $w27 +0x7b 0x24 0x7c 0x5e # CHECK: ftrunc_u.w $w17, $w15 +0x7b 0x25 0xd9 0x5e # CHECK: ftrunc_u.d $w5, $w27 diff --git a/test/MC/Disassembler/Mips/msa/test_3r.txt b/test/MC/Disassembler/Mips/msa/test_3r.txt new file mode 100644 index 0000000..2ef3a89 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_3r.txt @@ -0,0 +1,244 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x78 0x04 0x4e 0x90 # CHECK: add_a.b $w26, $w9, $w4 +0x78 0x3f 0xdd 0xd0 # CHECK: add_a.h $w23, $w27, $w31 +0x78 0x56 0x32 0xd0 # CHECK: add_a.w $w11, $w6, $w22 +0x78 0x60 0x51 0x90 # CHECK: add_a.d $w6, $w10, $w0 +0x78 0x93 0xc4 0xd0 # CHECK: adds_a.b $w19, $w24, $w19 +0x78 0xa4 0x36 0x50 # CHECK: adds_a.h $w25, $w6, $w4 +0x78 0xdb 0x8e 0x50 # CHECK: adds_a.w $w25, $w17, $w27 +0x78 0xfa 0x93 0xd0 # CHECK: adds_a.d $w15, $w18, $w26 +0x79 0x13 0x5f 0x50 # CHECK: adds_s.b $w29, $w11, $w19 +0x79 0x3a 0xb9 0x50 # CHECK: adds_s.h $w5, $w23, $w26 +0x79 0x4d 0x74 0x10 # CHECK: adds_s.w $w16, $w14, $w13 +0x79 0x7c 0x70 0x90 # CHECK: adds_s.d $w2, $w14, $w28 +0x79 0x8e 0x88 0xd0 # CHECK: adds_u.b $w3, $w17, $w14 +0x79 0xa4 0xf2 0x90 # CHECK: adds_u.h $w10, $w30, $w4 +0x79 0xd4 0x93 0xd0 # CHECK: adds_u.w $w15, $w18, $w20 +0x79 0xe9 0x57 0x90 # CHECK: adds_u.d $w30, $w10, $w9 +0x78 0x15 0xa6 0x0e # CHECK: addv.b $w24, $w20, $w21 +0x78 0x3b 0x69 0x0e # CHECK: addv.h $w4, $w13, $w27 +0x78 0x4e 0x5c 0xce # CHECK: addv.w $w19, $w11, $w14 +0x78 0x7f 0xa8 0x8e # CHECK: addv.d $w2, $w21, $w31 +0x7a 0x03 0x85 0xd1 # CHECK: asub_s.b $w23, $w16, $w3 +0x7a 0x39 0x8d 0x91 # CHECK: asub_s.h $w22, $w17, $w25 +0x7a 0x49 0x0e 0x11 # CHECK: asub_s.w $w24, $w1, $w9 +0x7a 0x6c 0x63 0x51 # CHECK: asub_s.d $w13, $w12, $w12 +0x7a 0x8b 0xea 0x91 # CHECK: asub_u.b $w10, $w29, $w11 +0x7a 0xaf 0x4c 0x91 # CHECK: asub_u.h $w18, $w9, $w15 +0x7a 0xdf 0x9a 0x91 # CHECK: asub_u.w $w10, $w19, $w31 +0x7a 0xe0 0x54 0x51 # CHECK: asub_u.d $w17, $w10, $w0 +0x7a 0x01 0x28 0x90 # CHECK: ave_s.b $w2, $w5, $w1 +0x7a 0x29 0x9c 0x10 # CHECK: ave_s.h $w16, $w19, $w9 +0x7a 0x45 0xfc 0x50 # CHECK: ave_s.w $w17, $w31, $w5 +0x7a 0x6a 0xce 0xd0 # CHECK: ave_s.d $w27, $w25, $w10 +0x7a 0x89 0x9c 0x10 # CHECK: ave_u.b $w16, $w19, $w9 +0x7a 0xab 0xe7 0x10 # CHECK: ave_u.h $w28, $w28, $w11 +0x7a 0xcb 0x62 0xd0 # CHECK: ave_u.w $w11, $w12, $w11 +0x7a 0xfc 0x9f 0x90 # CHECK: ave_u.d $w30, $w19, $w28 +0x7b 0x02 0x86 0x90 # CHECK: aver_s.b $w26, $w16, $w2 +0x7b 0x3b 0xdf 0xd0 # CHECK: aver_s.h $w31, $w27, $w27 +0x7b 0x59 0x97 0x10 # CHECK: aver_s.w $w28, $w18, $w25 +0x7b 0x7b 0xaf 0x50 # CHECK: aver_s.d $w29, $w21, $w27 +0x7b 0x83 0xd7 0x50 # CHECK: aver_u.b $w29, $w26, $w3 +0x7b 0xa9 0x94 0x90 # CHECK: aver_u.h $w18, $w18, $w9 +0x7b 0xdd 0xcc 0x50 # CHECK: aver_u.w $w17, $w25, $w29 +0x7b 0xf3 0xb5 0x90 # CHECK: aver_u.d $w22, $w22, $w19 +0x79 0x9d 0x78 0x8d # CHECK: bclr.b $w2, $w15, $w29 +0x79 0xbc 0xac 0x0d # CHECK: bclr.h $w16, $w21, $w28 +0x79 0xc9 0x14 0xcd # CHECK: bclr.w $w19, $w2, $w9 +0x79 0xe4 0xfe 0xcd # CHECK: bclr.d $w27, $w31, $w4 +0x7b 0x18 0x81 0x4d # CHECK: binsl.b $w5, $w16, $w24 +0x7b 0x2a 0x2f 0x8d # CHECK: binsl.h $w30, $w5, $w10 +0x7b 0x4d 0x7b 0x8d # CHECK: binsl.w $w14, $w15, $w13 +0x7b 0x6c 0xa5 0xcd # CHECK: binsl.d $w23, $w20, $w12 +0x7b 0x82 0x5d 0x8d # CHECK: binsr.b $w22, $w11, $w2 +0x7b 0xa6 0xd0 0x0d # CHECK: binsr.h $w0, $w26, $w6 +0x7b 0xdc 0x1e 0x8d # CHECK: binsr.w $w26, $w3, $w28 +0x7b 0xf5 0x00 0x0d # CHECK: binsr.d $w0, $w0, $w21 +0x7a 0x98 0x58 0x0d # CHECK: bneg.b $w0, $w11, $w24 +0x7a 0xa4 0x87 0x0d # CHECK: bneg.h $w28, $w16, $w4 +0x7a 0xd3 0xd0 0xcd # CHECK: bneg.w $w3, $w26, $w19 +0x7a 0xef 0xeb 0x4d # CHECK: bneg.d $w13, $w29, $w15 +0x7a 0x1f 0x2f 0xcd # CHECK: bset.b $w31, $w5, $w31 +0x7a 0x26 0x63 0x8d # CHECK: bset.h $w14, $w12, $w6 +0x7a 0x4c 0x4f 0xcd # CHECK: bset.w $w31, $w9, $w12 +0x7a 0x65 0xb1 0x4d # CHECK: bset.d $w5, $w22, $w5 +0x78 0x12 0xff 0xcf # CHECK: ceq.b $w31, $w31, $w18 +0x78 0x29 0xda 0x8f # CHECK: ceq.h $w10, $w27, $w9 +0x78 0x4e 0x2a 0x4f # CHECK: ceq.w $w9, $w5, $w14 +0x78 0x60 0x89 0x4f # CHECK: ceq.d $w5, $w17, $w0 +0x7a 0x09 0x25 0xcf # CHECK: cle_s.b $w23, $w4, $w9 +0x7a 0x33 0xdd 0x8f # CHECK: cle_s.h $w22, $w27, $w19 +0x7a 0x4a 0xd7 0x8f # CHECK: cle_s.w $w30, $w26, $w10 +0x7a 0x6a 0x2c 0x8f # CHECK: cle_s.d $w18, $w5, $w10 +0x7a 0x80 0xc8 0x4f # CHECK: cle_u.b $w1, $w25, $w0 +0x7a 0xbd 0x01 0xcf # CHECK: cle_u.h $w7, $w0, $w29 +0x7a 0xc1 0x96 0x4f # CHECK: cle_u.w $w25, $w18, $w1 +0x7a 0xfe 0x01 0x8f # CHECK: cle_u.d $w6, $w0, $w30 +0x79 0x15 0x16 0x4f # CHECK: clt_s.b $w25, $w2, $w21 +0x79 0x29 0x98 0x8f # CHECK: clt_s.h $w2, $w19, $w9 +0x79 0x50 0x45 0xcf # CHECK: clt_s.w $w23, $w8, $w16 +0x79 0x6c 0xf1 0xcf # CHECK: clt_s.d $w7, $w30, $w12 +0x79 0x8d 0xf8 0x8f # CHECK: clt_u.b $w2, $w31, $w13 +0x79 0xb7 0xfc 0x0f # CHECK: clt_u.h $w16, $w31, $w23 +0x79 0xc9 0xc0 0xcf # CHECK: clt_u.w $w3, $w24, $w9 +0x79 0xe1 0x01 0xcf # CHECK: clt_u.d $w7, $w0, $w1 +0x7a 0x12 0x1f 0x52 # CHECK: div_s.b $w29, $w3, $w18 +0x7a 0x2d 0x84 0x52 # CHECK: div_s.h $w17, $w16, $w13 +0x7a 0x5e 0xc9 0x12 # CHECK: div_s.w $w4, $w25, $w30 +0x7a 0x74 0x4f 0xd2 # CHECK: div_s.d $w31, $w9, $w20 +0x7a 0x8a 0xe9 0x92 # CHECK: div_u.b $w6, $w29, $w10 +0x7a 0xae 0xae 0x12 # CHECK: div_u.h $w24, $w21, $w14 +0x7a 0xd9 0x77 0x52 # CHECK: div_u.w $w29, $w14, $w25 +0x7a 0xf5 0x0f 0xd2 # CHECK: div_u.d $w31, $w1, $w21 +0x78 0x39 0xb5 0xd3 # CHECK: dotp_s.h $w23, $w22, $w25 +0x78 0x45 0x75 0x13 # CHECK: dotp_s.w $w20, $w14, $w5 +0x78 0x76 0x14 0x53 # CHECK: dotp_s.d $w17, $w2, $w22 +0x78 0xa6 0x13 0x53 # CHECK: dotp_u.h $w13, $w2, $w6 +0x78 0xd5 0xb3 0xd3 # CHECK: dotp_u.w $w15, $w22, $w21 +0x78 0xfa 0x81 0x13 # CHECK: dotp_u.d $w4, $w16, $w26 +0x79 0x36 0xe0 0x53 # CHECK: dpadd_s.h $w1, $w28, $w22 +0x79 0x4c 0x0a 0x93 # CHECK: dpadd_s.w $w10, $w1, $w12 +0x79 0x7b 0xa8 0xd3 # CHECK: dpadd_s.d $w3, $w21, $w27 +0x79 0xb4 0x2c 0x53 # CHECK: dpadd_u.h $w17, $w5, $w20 +0x79 0xd0 0x46 0x13 # CHECK: dpadd_u.w $w24, $w8, $w16 +0x79 0xf0 0xeb 0xd3 # CHECK: dpadd_u.d $w15, $w29, $w16 +0x7a 0x2c 0x59 0x13 # CHECK: dpsub_s.h $w4, $w11, $w12 +0x7a 0x46 0x39 0x13 # CHECK: dpsub_s.w $w4, $w7, $w6 +0x7a 0x7c 0x67 0xd3 # CHECK: dpsub_s.d $w31, $w12, $w28 +0x7a 0xb1 0xc9 0x13 # CHECK: dpsub_u.h $w4, $w25, $w17 +0x7a 0xd0 0xcc 0xd3 # CHECK: dpsub_u.w $w19, $w25, $w16 +0x7a 0xfa 0x51 0xd3 # CHECK: dpsub_u.d $w7, $w10, $w26 +0x7a 0x22 0xc7 0x15 # CHECK: hadd_s.h $w28, $w24, $w2 +0x7a 0x4b 0x8e 0x15 # CHECK: hadd_s.w $w24, $w17, $w11 +0x7a 0x74 0x7c 0x55 # CHECK: hadd_s.d $w17, $w15, $w20 +0x7a 0xb1 0xeb 0x15 # CHECK: hadd_u.h $w12, $w29, $w17 +0x7a 0xc6 0x2a 0x55 # CHECK: hadd_u.w $w9, $w5, $w6 +0x7a 0xe6 0xa0 0x55 # CHECK: hadd_u.d $w1, $w20, $w6 +0x7b 0x3d 0x74 0x15 # CHECK: hsub_s.h $w16, $w14, $w29 +0x7b 0x4b 0x6a 0x55 # CHECK: hsub_s.w $w9, $w13, $w11 +0x7b 0x6e 0x97 0x95 # CHECK: hsub_s.d $w30, $w18, $w14 +0x7b 0xae 0x61 0xd5 # CHECK: hsub_u.h $w7, $w12, $w14 +0x7b 0xc5 0x2d 0x55 # CHECK: hsub_u.w $w21, $w5, $w5 +0x7b 0xff 0x62 0xd5 # CHECK: hsub_u.d $w11, $w12, $w31 +0x7b 0x1e 0x84 0x94 # CHECK: ilvev.b $w18, $w16, $w30 +0x7b 0x2d 0x03 0x94 # CHECK: ilvev.h $w14, $w0, $w13 +0x7b 0x56 0xcb 0x14 # CHECK: ilvev.w $w12, $w25, $w22 +0x7b 0x63 0xdf 0x94 # CHECK: ilvev.d $w30, $w27, $w3 +0x7a 0x15 0x1f 0x54 # CHECK: ilvl.b $w29, $w3, $w21 +0x7a 0x31 0x56 0xd4 # CHECK: ilvl.h $w27, $w10, $w17 +0x7a 0x40 0x09 0x94 # CHECK: ilvl.w $w6, $w1, $w0 +0x7a 0x78 0x80 0xd4 # CHECK: ilvl.d $w3, $w16, $w24 +0x7b 0x94 0x2a 0xd4 # CHECK: ilvod.b $w11, $w5, $w20 +0x7b 0xbf 0x6c 0x94 # CHECK: ilvod.h $w18, $w13, $w31 +0x7b 0xd8 0x87 0x54 # CHECK: ilvod.w $w29, $w16, $w24 +0x7b 0xfd 0x65 0x94 # CHECK: ilvod.d $w22, $w12, $w29 +0x7a 0x86 0xf1 0x14 # CHECK: ilvr.b $w4, $w30, $w6 +0x7a 0xbd 0x9f 0x14 # CHECK: ilvr.h $w28, $w19, $w29 +0x7a 0xd5 0xa4 0x94 # CHECK: ilvr.w $w18, $w20, $w21 +0x7a 0xec 0xf5 0xd4 # CHECK: ilvr.d $w23, $w30, $w12 +0x78 0x9d 0xfc 0x52 # CHECK: maddv.b $w17, $w31, $w29 +0x78 0xa9 0xc1 0xd2 # CHECK: maddv.h $w7, $w24, $w9 +0x78 0xd4 0xb5 0x92 # CHECK: maddv.w $w22, $w22, $w20 +0x78 0xf4 0xd7 0x92 # CHECK: maddv.d $w30, $w26, $w20 +0x7b 0x17 0x5d 0xce # CHECK: max_a.b $w23, $w11, $w23 +0x7b 0x3e 0x2d 0x0e # CHECK: max_a.h $w20, $w5, $w30 +0x7b 0x5e 0x91 0xce # CHECK: max_a.w $w7, $w18, $w30 +0x7b 0x7f 0x42 0x0e # CHECK: max_a.d $w8, $w8, $w31 +0x79 0x13 0x0a 0x8e # CHECK: max_s.b $w10, $w1, $w19 +0x79 0x31 0xeb 0xce # CHECK: max_s.h $w15, $w29, $w17 +0x79 0x4e 0xeb 0xce # CHECK: max_s.w $w15, $w29, $w14 +0x79 0x63 0xc6 0x4e # CHECK: max_s.d $w25, $w24, $w3 +0x79 0x85 0xc3 0x0e # CHECK: max_u.b $w12, $w24, $w5 +0x79 0xa7 0x31 0x4e # CHECK: max_u.h $w5, $w6, $w7 +0x79 0xc7 0x24 0x0e # CHECK: max_u.w $w16, $w4, $w7 +0x79 0xf8 0x66 0x8e # CHECK: max_u.d $w26, $w12, $w24 +0x7b 0x81 0xd1 0x0e # CHECK: min_a.b $w4, $w26, $w1 +0x7b 0xbf 0x6b 0x0e # CHECK: min_a.h $w12, $w13, $w31 +0x7b 0xc0 0xa7 0x0e # CHECK: min_a.w $w28, $w20, $w0 +0x7b 0xf3 0xa3 0x0e # CHECK: min_a.d $w12, $w20, $w19 +0x7a 0x0e 0x1c 0xce # CHECK: min_s.b $w19, $w3, $w14 +0x7a 0x28 0xae 0xce # CHECK: min_s.h $w27, $w21, $w8 +0x7a 0x5e 0x70 0x0e # CHECK: min_s.w $w0, $w14, $w30 +0x7a 0x75 0x41 0x8e # CHECK: min_s.d $w6, $w8, $w21 +0x7a 0x88 0xd5 0x8e # CHECK: min_u.b $w22, $w26, $w8 +0x7a 0xac 0xd9 0xce # CHECK: min_u.h $w7, $w27, $w12 +0x7a 0xce 0xa2 0x0e # CHECK: min_u.w $w8, $w20, $w14 +0x7a 0xef 0x76 0x8e # CHECK: min_u.d $w26, $w14, $w15 +0x7b 0x1a 0x0c 0x92 # CHECK: mod_s.b $w18, $w1, $w26 +0x7b 0x3c 0xf7 0xd2 # CHECK: mod_s.h $w31, $w30, $w28 +0x7b 0x4d 0x30 0x92 # CHECK: mod_s.w $w2, $w6, $w13 +0x7b 0x76 0xdd 0x52 # CHECK: mod_s.d $w21, $w27, $w22 +0x7b 0x8d 0x3c 0x12 # CHECK: mod_u.b $w16, $w7, $w13 +0x7b 0xa7 0x46 0x12 # CHECK: mod_u.h $w24, $w8, $w7 +0x7b 0xd1 0x17 0x92 # CHECK: mod_u.w $w30, $w2, $w17 +0x7b 0xf9 0x17 0xd2 # CHECK: mod_u.d $w31, $w2, $w25 +0x79 0x0c 0x2b 0x92 # CHECK: msubv.b $w14, $w5, $w12 +0x79 0x3e 0x39 0x92 # CHECK: msubv.h $w6, $w7, $w30 +0x79 0x55 0x13 0x52 # CHECK: msubv.w $w13, $w2, $w21 +0x79 0x7b 0x74 0x12 # CHECK: msubv.d $w16, $w14, $w27 +0x78 0x0d 0x1d 0x12 # CHECK: mulv.b $w20, $w3, $w13 +0x78 0x2e 0xd6 0xd2 # CHECK: mulv.h $w27, $w26, $w14 +0x78 0x43 0xea 0x92 # CHECK: mulv.w $w10, $w29, $w3 +0x78 0x7d 0x99 0xd2 # CHECK: mulv.d $w7, $w19, $w29 +0x79 0x07 0xd9 0x54 # CHECK: pckev.b $w5, $w27, $w7 +0x79 0x3b 0x20 0x54 # CHECK: pckev.h $w1, $w4, $w27 +0x79 0x40 0xa7 0x94 # CHECK: pckev.w $w30, $w20, $w0 +0x79 0x6f 0x09 0x94 # CHECK: pckev.d $w6, $w1, $w15 +0x79 0x9e 0xe4 0x94 # CHECK: pckod.b $w18, $w28, $w30 +0x79 0xa8 0x2e 0x94 # CHECK: pckod.h $w26, $w5, $w8 +0x79 0xc2 0x22 0x54 # CHECK: pckod.w $w9, $w4, $w2 +0x79 0xf4 0xb7 0x94 # CHECK: pckod.d $w30, $w22, $w20 +0x78 0x0c 0xb9 0x54 # CHECK: sld.b $w5, $w23[$12] +0x78 0x23 0xb8 0x54 # CHECK: sld.h $w1, $w23[$3] +0x78 0x49 0x45 0x14 # CHECK: sld.w $w20, $w8[$9] +0x78 0x7e 0xb9 0xd4 # CHECK: sld.d $w7, $w23[$fp] +0x78 0x11 0x00 0xcd # CHECK: sll.b $w3, $w0, $w17 +0x78 0x23 0xdc 0x4d # CHECK: sll.h $w17, $w27, $w3 +0x78 0x46 0x3c 0x0d # CHECK: sll.w $w16, $w7, $w6 +0x78 0x7a 0x02 0x4d # CHECK: sll.d $w9, $w0, $w26 +0x78 0x81 0x0f 0x14 # CHECK: splat.b $w28, $w1[$1] +0x78 0xab 0x58 0x94 # CHECK: splat.h $w2, $w11[$11] +0x78 0xcb 0x05 0x94 # CHECK: splat.w $w22, $w0[$11] +0x78 0xe2 0x00 0x14 # CHECK: splat.d $w0, $w0[$2] +0x78 0x91 0x27 0x0d # CHECK: sra.b $w28, $w4, $w17 +0x78 0xa3 0x4b 0x4d # CHECK: sra.h $w13, $w9, $w3 +0x78 0xd3 0xae 0xcd # CHECK: sra.w $w27, $w21, $w19 +0x78 0xf7 0x47 0x8d # CHECK: sra.d $w30, $w8, $w23 +0x78 0x92 0x94 0xd5 # CHECK: srar.b $w19, $w18, $w18 +0x78 0xa8 0xb9 0xd5 # CHECK: srar.h $w7, $w23, $w8 +0x78 0xc2 0x60 0x55 # CHECK: srar.w $w1, $w12, $w2 +0x78 0xee 0x3d 0x55 # CHECK: srar.d $w21, $w7, $w14 +0x79 0x13 0x1b 0x0d # CHECK: srl.b $w12, $w3, $w19 +0x79 0x34 0xfd 0xcd # CHECK: srl.h $w23, $w31, $w20 +0x79 0x4b 0xdc 0x8d # CHECK: srl.w $w18, $w27, $w11 +0x79 0x7a 0x60 0xcd # CHECK: srl.d $w3, $w12, $w26 +0x79 0x0b 0xab 0xd5 # CHECK: srlr.b $w15, $w21, $w11 +0x79 0x33 0x6d 0x55 # CHECK: srlr.h $w21, $w13, $w19 +0x79 0x43 0xf1 0x95 # CHECK: srlr.w $w6, $w30, $w3 +0x79 0x6e 0x10 0x55 # CHECK: srlr.d $w1, $w2, $w14 +0x78 0x01 0x7e 0x51 # CHECK: subs_s.b $w25, $w15, $w1 +0x78 0x36 0xcf 0x11 # CHECK: subs_s.h $w28, $w25, $w22 +0x78 0x55 0x62 0x91 # CHECK: subs_s.w $w10, $w12, $w21 +0x78 0x72 0xa1 0x11 # CHECK: subs_s.d $w4, $w20, $w18 +0x78 0x99 0x35 0x51 # CHECK: subs_u.b $w21, $w6, $w25 +0x78 0xa7 0x50 0xd1 # CHECK: subs_u.h $w3, $w10, $w7 +0x78 0xca 0x7a 0x51 # CHECK: subs_u.w $w9, $w15, $w10 +0x78 0xea 0x99 0xd1 # CHECK: subs_u.d $w7, $w19, $w10 +0x79 0x0c 0x39 0x91 # CHECK: subsus_u.b $w6, $w7, $w12 +0x79 0x33 0xe9 0x91 # CHECK: subsus_u.h $w6, $w29, $w19 +0x79 0x47 0x79 0xd1 # CHECK: subsus_u.w $w7, $w15, $w7 +0x79 0x6f 0x1a 0x51 # CHECK: subsus_u.d $w9, $w3, $w15 +0x79 0x9f 0x1d 0x91 # CHECK: subsuu_s.b $w22, $w3, $w31 +0x79 0xb6 0xbc 0xd1 # CHECK: subsuu_s.h $w19, $w23, $w22 +0x79 0xcd 0x52 0x51 # CHECK: subsuu_s.w $w9, $w10, $w13 +0x79 0xe0 0x31 0x51 # CHECK: subsuu_s.d $w5, $w6, $w0 +0x78 0x93 0x69 0x8e # CHECK: subv.b $w6, $w13, $w19 +0x78 0xac 0xc9 0x0e # CHECK: subv.h $w4, $w25, $w12 +0x78 0xcb 0xde 0xce # CHECK: subv.w $w27, $w27, $w11 +0x78 0xea 0xc2 0x4e # CHECK: subv.d $w9, $w24, $w10 +0x78 0x05 0x80 0xd5 # CHECK: vshf.b $w3, $w16, $w5 +0x78 0x28 0x9d 0x15 # CHECK: vshf.h $w20, $w19, $w8 +0x78 0x59 0xf4 0x15 # CHECK: vshf.w $w16, $w30, $w25 +0x78 0x6f 0x5c 0xd5 # CHECK: vshf.d $w19, $w11, $w15 diff --git a/test/MC/Disassembler/Mips/msa/test_3rf.txt b/test/MC/Disassembler/Mips/msa/test_3rf.txt new file mode 100644 index 0000000..3b7b07c --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_3rf.txt @@ -0,0 +1,84 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x78 0x1c 0x9f 0x1b # CHECK: fadd.w $w28, $w19, $w28 +0x78 0x3d 0x13 0x5b # CHECK: fadd.d $w13, $w2, $w29 +0x78 0x19 0x5b 0x9a # CHECK: fcaf.w $w14, $w11, $w25 +0x78 0x33 0x08 0x5a # CHECK: fcaf.d $w1, $w1, $w19 +0x78 0x90 0xb8 0x5a # CHECK: fceq.w $w1, $w23, $w16 +0x78 0xb0 0x40 0x1a # CHECK: fceq.d $w0, $w8, $w16 +0x79 0x98 0x4c 0x1a # CHECK: fcle.w $w16, $w9, $w24 +0x79 0xa1 0x76 0xda # CHECK: fcle.d $w27, $w14, $w1 +0x79 0x08 0x47 0x1a # CHECK: fclt.w $w28, $w8, $w8 +0x79 0x2b 0xcf 0x9a # CHECK: fclt.d $w30, $w25, $w11 +0x78 0xd7 0x90 0x9c # CHECK: fcne.w $w2, $w18, $w23 +0x78 0xef 0xa3 0x9c # CHECK: fcne.d $w14, $w20, $w15 +0x78 0x59 0x92 0x9c # CHECK: fcor.w $w10, $w18, $w25 +0x78 0x6b 0xcc 0x5c # CHECK: fcor.d $w17, $w25, $w11 +0x78 0xd5 0x13 0x9a # CHECK: fcueq.w $w14, $w2, $w21 +0x78 0xe7 0x1f 0x5a # CHECK: fcueq.d $w29, $w3, $w7 +0x79 0xc3 0x2c 0x5a # CHECK: fcule.w $w17, $w5, $w3 +0x79 0xfe 0x0f 0xda # CHECK: fcule.d $w31, $w1, $w30 +0x79 0x49 0xc9 0x9a # CHECK: fcult.w $w6, $w25, $w9 +0x79 0x71 0x46 0xda # CHECK: fcult.d $w27, $w8, $w17 +0x78 0x48 0xa1 0x1a # CHECK: fcun.w $w4, $w20, $w8 +0x78 0x63 0x5f 0x5a # CHECK: fcun.d $w29, $w11, $w3 +0x78 0x93 0x93 0x5c # CHECK: fcune.w $w13, $w18, $w19 +0x78 0xb5 0xd4 0x1c # CHECK: fcune.d $w16, $w26, $w21 +0x78 0xc2 0xc3 0x5b # CHECK: fdiv.w $w13, $w24, $w2 +0x78 0xf9 0x24 0xdb # CHECK: fdiv.d $w19, $w4, $w25 +0x7a 0x10 0x02 0x1b # CHECK: fexdo.h $w8, $w0, $w16 +0x7a 0x3b 0x68 0x1b # CHECK: fexdo.w $w0, $w13, $w27 +0x79 0xc3 0x04 0x5b # CHECK: fexp2.w $w17, $w0, $w3 +0x79 0xea 0x05 0x9b # CHECK: fexp2.d $w22, $w0, $w10 +0x79 0x17 0x37 0x5b # CHECK: fmadd.w $w29, $w6, $w23 +0x79 0x35 0xe2 0xdb # CHECK: fmadd.d $w11, $w28, $w21 +0x7b 0x8d 0xb8 0x1b # CHECK: fmax.w $w0, $w23, $w13 +0x7b 0xa8 0x96 0x9b # CHECK: fmax.d $w26, $w18, $w8 +0x7b 0xca 0x82 0x9b # CHECK: fmax_a.w $w10, $w16, $w10 +0x7b 0xf6 0x4f 0x9b # CHECK: fmax_a.d $w30, $w9, $w22 +0x7b 0x1e 0x0e 0x1b # CHECK: fmin.w $w24, $w1, $w30 +0x7b 0x2a 0xde 0xdb # CHECK: fmin.d $w27, $w27, $w10 +0x7b 0x54 0xea 0x9b # CHECK: fmin_a.w $w10, $w29, $w20 +0x7b 0x78 0xf3 0x5b # CHECK: fmin_a.d $w13, $w30, $w24 +0x79 0x40 0xcc 0x5b # CHECK: fmsub.w $w17, $w25, $w0 +0x79 0x70 0x92 0x1b # CHECK: fmsub.d $w8, $w18, $w16 +0x78 0x8f 0x78 0xdb # CHECK: fmul.w $w3, $w15, $w15 +0x78 0xaa 0xf2 0x5b # CHECK: fmul.d $w9, $w30, $w10 +0x7a 0x0a 0x2e 0x5a # CHECK: fsaf.w $w25, $w5, $w10 +0x7a 0x3d 0x1e 0x5a # CHECK: fsaf.d $w25, $w3, $w29 +0x7a 0x8d 0x8a 0xda # CHECK: fseq.w $w11, $w17, $w13 +0x7a 0xbf 0x07 0x5a # CHECK: fseq.d $w29, $w0, $w31 +0x7b 0x9f 0xff 0x9a # CHECK: fsle.w $w30, $w31, $w31 +0x7b 0xb8 0xbc 0x9a # CHECK: fsle.d $w18, $w23, $w24 +0x7b 0x06 0x2b 0x1a # CHECK: fslt.w $w12, $w5, $w6 +0x7b 0x35 0xd4 0x1a # CHECK: fslt.d $w16, $w26, $w21 +0x7a 0xcc 0x0f 0x9c # CHECK: fsne.w $w30, $w1, $w12 +0x7a 0xf7 0x6b 0x9c # CHECK: fsne.d $w14, $w13, $w23 +0x7a 0x5b 0x6e 0xdc # CHECK: fsor.w $w27, $w13, $w27 +0x7a 0x6b 0xc3 0x1c # CHECK: fsor.d $w12, $w24, $w11 +0x78 0x41 0xd7 0xdb # CHECK: fsub.w $w31, $w26, $w1 +0x78 0x7b 0x8c 0xdb # CHECK: fsub.d $w19, $w17, $w27 +0x7a 0xd9 0xc4 0x1a # CHECK: fsueq.w $w16, $w24, $w25 +0x7a 0xee 0x74 0x9a # CHECK: fsueq.d $w18, $w14, $w14 +0x7b 0xcd 0xf5 0xda # CHECK: fsule.w $w23, $w30, $w13 +0x7b 0xfa 0x58 0x9a # CHECK: fsule.d $w2, $w11, $w26 +0x7b 0x56 0xd2 0xda # CHECK: fsult.w $w11, $w26, $w22 +0x7b 0x7e 0xb9 0x9a # CHECK: fsult.d $w6, $w23, $w30 +0x7a 0x5c 0x90 0xda # CHECK: fsun.w $w3, $w18, $w28 +0x7a 0x73 0x5c 0x9a # CHECK: fsun.d $w18, $w11, $w19 +0x7a 0x82 0xfc 0x1c # CHECK: fsune.w $w16, $w31, $w2 +0x7a 0xb1 0xd0 0xdc # CHECK: fsune.d $w3, $w26, $w17 +0x7a 0x98 0x24 0x1b # CHECK: ftq.h $w16, $w4, $w24 +0x7a 0xb9 0x29 0x5b # CHECK: ftq.w $w5, $w5, $w25 +0x79 0x4a 0xa4 0x1c # CHECK: madd_q.h $w16, $w20, $w10 +0x79 0x69 0x17 0x1c # CHECK: madd_q.w $w28, $w2, $w9 +0x7b 0x49 0x92 0x1c # CHECK: maddr_q.h $w8, $w18, $w9 +0x7b 0x70 0x67 0x5c # CHECK: maddr_q.w $w29, $w12, $w16 +0x79 0x8a 0xd6 0x1c # CHECK: msub_q.h $w24, $w26, $w10 +0x79 0xbc 0xf3 0x5c # CHECK: msub_q.w $w13, $w30, $w28 +0x7b 0x8b 0xab 0x1c # CHECK: msubr_q.h $w12, $w21, $w11 +0x7b 0xb4 0x70 0x5c # CHECK: msubr_q.w $w1, $w14, $w20 +0x79 0x1e 0x81 0x9c # CHECK: mul_q.h $w6, $w16, $w30 +0x79 0x24 0x0c 0x1c # CHECK: mul_q.w $w16, $w1, $w4 +0x7b 0x13 0xa1 0x9c # CHECK: mulr_q.h $w6, $w20, $w19 +0x7b 0x34 0x0e 0xdc # CHECK: mulr_q.w $w27, $w1, $w20 diff --git a/test/MC/Disassembler/Mips/msa/test_bit.txt b/test/MC/Disassembler/Mips/msa/test_bit.txt new file mode 100644 index 0000000..422d71e --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_bit.txt @@ -0,0 +1,50 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x79 0xf2 0xf5 0x49 # CHECK: bclri.b $w21, $w30, 2 +0x79 0xe0 0xae 0x09 # CHECK: bclri.h $w24, $w21, 0 +0x79 0xc3 0xf5 0xc9 # CHECK: bclri.w $w23, $w30, 3 +0x79 0x80 0x5a 0x49 # CHECK: bclri.d $w9, $w11, 0 +0x7b 0x71 0x66 0x49 # CHECK: binsli.b $w25, $w12, 1 +0x7b 0x60 0xb5 0x49 # CHECK: binsli.h $w21, $w22, 0 +0x7b 0x40 0x25 0x89 # CHECK: binsli.w $w22, $w4, 0 +0x7b 0x06 0x11 0x89 # CHECK: binsli.d $w6, $w2, 6 +0x7b 0xf0 0x9b 0xc9 # CHECK: binsri.b $w15, $w19, 0 +0x7b 0xe1 0xf2 0x09 # CHECK: binsri.h $w8, $w30, 1 +0x7b 0xc5 0x98 0x89 # CHECK: binsri.w $w2, $w19, 5 +0x7b 0x81 0xa4 0x89 # CHECK: binsri.d $w18, $w20, 1 +0x7a 0xf0 0x9e 0x09 # CHECK: bnegi.b $w24, $w19, 0 +0x7a 0xe3 0x5f 0x09 # CHECK: bnegi.h $w28, $w11, 3 +0x7a 0xc5 0xd8 0x49 # CHECK: bnegi.w $w1, $w27, 5 +0x7a 0x81 0xa9 0x09 # CHECK: bnegi.d $w4, $w21, 1 +0x7a 0x70 0x44 0x89 # CHECK: bseti.b $w18, $w8, 0 +0x7a 0x62 0x76 0x09 # CHECK: bseti.h $w24, $w14, 2 +0x7a 0x44 0x92 0x49 # CHECK: bseti.w $w9, $w18, 4 +0x7a 0x01 0x79 0xc9 # CHECK: bseti.d $w7, $w15, 1 +0x78 0x72 0xff 0xca # CHECK: sat_s.b $w31, $w31, 2 +0x78 0x60 0x9c 0xca # CHECK: sat_s.h $w19, $w19, 0 +0x78 0x40 0xec 0xca # CHECK: sat_s.w $w19, $w29, 0 +0x78 0x00 0xb2 0xca # CHECK: sat_s.d $w11, $w22, 0 +0x78 0xf3 0x68 0x4a # CHECK: sat_u.b $w1, $w13, 3 +0x78 0xe4 0xc7 0x8a # CHECK: sat_u.h $w30, $w24, 4 +0x78 0xc0 0x6f 0xca # CHECK: sat_u.w $w31, $w13, 0 +0x78 0x85 0x87 0x4a # CHECK: sat_u.d $w29, $w16, 5 +0x78 0x71 0x55 0xc9 # CHECK: slli.b $w23, $w10, 1 +0x78 0x61 0x92 0x49 # CHECK: slli.h $w9, $w18, 1 +0x78 0x44 0xea 0xc9 # CHECK: slli.w $w11, $w29, 4 +0x78 0x01 0xa6 0x49 # CHECK: slli.d $w25, $w20, 1 +0x78 0xf1 0xee 0x09 # CHECK: srai.b $w24, $w29, 1 +0x78 0xe0 0x30 0x49 # CHECK: srai.h $w1, $w6, 0 +0x78 0xc1 0xd1 0xc9 # CHECK: srai.w $w7, $w26, 1 +0x78 0x83 0xcd 0x09 # CHECK: srai.d $w20, $w25, 3 +0x79 0x70 0xc9 0x4a # CHECK: srari.b $w5, $w25, 0 +0x79 0x64 0x31 0xca # CHECK: srari.h $w7, $w6, 4 +0x79 0x45 0x5c 0x4a # CHECK: srari.w $w17, $w11, 5 +0x79 0x05 0xcd 0x4a # CHECK: srari.d $w21, $w25, 5 +0x79 0x72 0x00 0x89 # CHECK: srli.b $w2, $w0, 2 +0x79 0x62 0xff 0xc9 # CHECK: srli.h $w31, $w31, 2 +0x79 0x44 0x49 0x49 # CHECK: srli.w $w5, $w9, 4 +0x79 0x05 0xd6 0xc9 # CHECK: srli.d $w27, $w26, 5 +0x79 0xf0 0x1c 0x8a # CHECK: srlri.b $w18, $w3, 0 +0x79 0xe3 0x10 0x4a # CHECK: srlri.h $w1, $w2, 3 +0x79 0xc2 0xb2 0xca # CHECK: srlri.w $w11, $w22, 2 +0x79 0x86 0x56 0x0a # CHECK: srlri.d $w24, $w10, 6 diff --git a/test/MC/Disassembler/Mips/msa/test_ctrlregs.txt b/test/MC/Disassembler/Mips/msa/test_ctrlregs.txt new file mode 100644 index 0000000..fb5b0be --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_ctrlregs.txt @@ -0,0 +1,35 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x78 0x7e 0x00 0x59 # CHECK: cfcmsa $1, $0 +0x78 0x7e 0x00 0x59 # CHECK: cfcmsa $1, $0 +0x78 0x7e 0x08 0x99 # CHECK: cfcmsa $2, $1 +0x78 0x7e 0x08 0x99 # CHECK: cfcmsa $2, $1 +0x78 0x7e 0x10 0xd9 # CHECK: cfcmsa $3, $2 +0x78 0x7e 0x10 0xd9 # CHECK: cfcmsa $3, $2 +0x78 0x7e 0x19 0x19 # CHECK: cfcmsa $4, $3 +0x78 0x7e 0x19 0x19 # CHECK: cfcmsa $4, $3 +0x78 0x7e 0x21 0x59 # CHECK: cfcmsa $5, $4 +0x78 0x7e 0x21 0x59 # CHECK: cfcmsa $5, $4 +0x78 0x7e 0x29 0x99 # CHECK: cfcmsa $6, $5 +0x78 0x7e 0x29 0x99 # CHECK: cfcmsa $6, $5 +0x78 0x7e 0x31 0xd9 # CHECK: cfcmsa $7, $6 +0x78 0x7e 0x31 0xd9 # CHECK: cfcmsa $7, $6 +0x78 0x7e 0x3a 0x19 # CHECK: cfcmsa $8, $7 +0x78 0x7e 0x3a 0x19 # CHECK: cfcmsa $8, $7 + +0x78 0x3e 0x08 0x19 # CHECK: ctcmsa $0, $1 +0x78 0x3e 0x08 0x19 # CHECK: ctcmsa $0, $1 +0x78 0x3e 0x10 0x59 # CHECK: ctcmsa $1, $2 +0x78 0x3e 0x10 0x59 # CHECK: ctcmsa $1, $2 +0x78 0x3e 0x18 0x99 # CHECK: ctcmsa $2, $3 +0x78 0x3e 0x18 0x99 # CHECK: ctcmsa $2, $3 +0x78 0x3e 0x20 0xd9 # CHECK: ctcmsa $3, $4 +0x78 0x3e 0x20 0xd9 # CHECK: ctcmsa $3, $4 +0x78 0x3e 0x29 0x19 # CHECK: ctcmsa $4, $5 +0x78 0x3e 0x29 0x19 # CHECK: ctcmsa $4, $5 +0x78 0x3e 0x31 0x59 # CHECK: ctcmsa $5, $6 +0x78 0x3e 0x31 0x59 # CHECK: ctcmsa $5, $6 +0x78 0x3e 0x39 0x99 # CHECK: ctcmsa $6, $7 +0x78 0x3e 0x39 0x99 # CHECK: ctcmsa $6, $7 +0x78 0x3e 0x41 0xd9 # CHECK: ctcmsa $7, $8 +0x78 0x3e 0x41 0xd9 # CHECK: ctcmsa $7, $8 diff --git a/test/MC/Disassembler/Mips/msa/test_dlsa.txt b/test/MC/Disassembler/Mips/msa/test_dlsa.txt new file mode 100644 index 0000000..2a1d90b --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_dlsa.txt @@ -0,0 +1,6 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r2 -mattr=+msa | FileCheck %s + +0x01 0x2a 0x40 0x15 # CHECK: dlsa $8, $9, $10, 1 +0x01 0x2a 0x40 0x55 # CHECK: dlsa $8, $9, $10, 2 +0x01 0x2a 0x40 0x95 # CHECK: dlsa $8, $9, $10, 3 +0x01 0x2a 0x40 0xd5 # CHECK: dlsa $8, $9, $10, 4 diff --git a/test/MC/Disassembler/Mips/msa/test_elm.txt b/test/MC/Disassembler/Mips/msa/test_elm.txt new file mode 100644 index 0000000..832587b --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_elm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x78 0x82 0x43 0x59 # CHECK: copy_s.b $13, $w8[2] +0x78 0xa0 0xc8 0x59 # CHECK: copy_s.h $1, $w25[0] +0x78 0xb1 0x2d 0x99 # CHECK: copy_s.w $22, $w5[1] +0x78 0xc4 0xa5 0x99 # CHECK: copy_u.b $22, $w20[4] +0x78 0xe0 0x25 0x19 # CHECK: copy_u.h $20, $w4[0] +0x78 0xf2 0x6f 0x99 # CHECK: copy_u.w $fp, $w13[2] +0x78 0x04 0xe8 0x19 # CHECK: sldi.b $w0, $w29[4] +0x78 0x20 0x8a 0x19 # CHECK: sldi.h $w8, $w17[0] +0x78 0x32 0xdd 0x19 # CHECK: sldi.w $w20, $w27[2] +0x78 0x38 0x61 0x19 # CHECK: sldi.d $w4, $w12[0] +0x78 0x42 0x1e 0x59 # CHECK: splati.b $w25, $w3[2] +0x78 0x61 0xe6 0x19 # CHECK: splati.h $w24, $w28[1] +0x78 0x70 0x93 0x59 # CHECK: splati.w $w13, $w18[0] +0x78 0x78 0x0f 0x19 # CHECK: splati.d $w28, $w1[0] +0x78 0xbe 0xc5 0xd9 # CHECK: move.v $w23, $w24 diff --git a/test/MC/Disassembler/Mips/msa/test_elm_insert.txt b/test/MC/Disassembler/Mips/msa/test_elm_insert.txt new file mode 100644 index 0000000..605d495 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_elm_insert.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x79 0x03 0xed 0xd9 # CHECK: insert.b $w23[3], $sp +0x79 0x22 0x2d 0x19 # CHECK: insert.h $w20[2], $5 +0x79 0x32 0x7a 0x19 # CHECK: insert.w $w8[2], $15 diff --git a/test/MC/Disassembler/Mips/msa/test_elm_insert_msa64.txt b/test/MC/Disassembler/Mips/msa/test_elm_insert_msa64.txt new file mode 100644 index 0000000..62920f3 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_elm_insert_msa64.txt @@ -0,0 +1,3 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r2 -mattr=+msa | FileCheck %s + +0x79 0x39 0xe8 0x59 # CHECK: insert.d $w1[1], $sp diff --git a/test/MC/Disassembler/Mips/msa/test_elm_insve.txt b/test/MC/Disassembler/Mips/msa/test_elm_insve.txt new file mode 100644 index 0000000..c5c3ba0 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_elm_insve.txt @@ -0,0 +1,6 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x79 0x43 0x4e 0x59 # CHECK: insve.b $w25[3], $w9[0] +0x79 0x62 0x16 0x19 # CHECK: insve.h $w24[2], $w2[0] +0x79 0x72 0x68 0x19 # CHECK: insve.w $w0[2], $w13[0] +0x79 0x78 0x90 0xd9 # CHECK: insve.d $w3[0], $w18[0] diff --git a/test/MC/Disassembler/Mips/msa/test_elm_msa64.txt b/test/MC/Disassembler/Mips/msa/test_elm_msa64.txt new file mode 100644 index 0000000..70c831a --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_elm_msa64.txt @@ -0,0 +1,6 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r2 -mattr=+msa | FileCheck %s + +# CHECK: copy_s.d $19, $w31[0] +0x78 0xb8 0xfc 0xd9 +# CHECK: copy_u.d $18, $w29[1] +0x78 0xf9 0xec 0x99 diff --git a/test/MC/Disassembler/Mips/msa/test_i10.txt b/test/MC/Disassembler/Mips/msa/test_i10.txt new file mode 100644 index 0000000..ac95d88 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_i10.txt @@ -0,0 +1,6 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32 -mattr=+msa | FileCheck %s + +0x7b 0x06 0x32 0x07 # CHECK: ldi.b $w8, 198 +0x7b 0x29 0xcd 0x07 # CHECK: ldi.h $w20, 313 +0x7b 0x4f 0x66 0x07 # CHECK: ldi.w $w24, 492 +0x7b 0x7a 0x66 0xc7 # CHECK: ldi.d $w27, 844 diff --git a/test/MC/Disassembler/Mips/msa/test_i5.txt b/test/MC/Disassembler/Mips/msa/test_i5.txt new file mode 100644 index 0000000..bf5bc51 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_i5.txt @@ -0,0 +1,46 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32 -mattr=+msa | FileCheck %s + +0x78 0x1e 0xf8 0xc6 # CHECK: addvi.b $w3, $w31, 30 +0x78 0x3a 0x6e 0x06 # CHECK: addvi.h $w24, $w13, 26 +0x78 0x5a 0xa6 0x86 # CHECK: addvi.w $w26, $w20, 26 +0x78 0x75 0x0c 0x06 # CHECK: addvi.d $w16, $w1, 21 +0x78 0x18 0xae 0x07 # CHECK: ceqi.b $w24, $w21, 24 +0x78 0x22 0x7f 0xc7 # CHECK: ceqi.h $w31, $w15, 2 +0x78 0x5f 0x0b 0x07 # CHECK: ceqi.w $w12, $w1, 31 +0x78 0x67 0xb6 0x07 # CHECK: ceqi.d $w24, $w22, 7 +0x7a 0x01 0x83 0x07 # CHECK: clei_s.b $w12, $w16, 1 +0x7a 0x37 0x50 0x87 # CHECK: clei_s.h $w2, $w10, 23 +0x7a 0x56 0x59 0x07 # CHECK: clei_s.w $w4, $w11, 22 +0x7a 0x76 0xe8 0x07 # CHECK: clei_s.d $w0, $w29, 22 +0x7a 0x83 0x8d 0x47 # CHECK: clei_u.b $w21, $w17, 3 +0x7a 0xb1 0x3f 0x47 # CHECK: clei_u.h $w29, $w7, 17 +0x7a 0xc2 0x08 0x47 # CHECK: clei_u.w $w1, $w1, 2 +0x7a 0xfd 0xde 0xc7 # CHECK: clei_u.d $w27, $w27, 29 +0x79 0x19 0x6c 0xc7 # CHECK: clti_s.b $w19, $w13, 25 +0x79 0x34 0x53 0xc7 # CHECK: clti_s.h $w15, $w10, 20 +0x79 0x4b 0x63 0x07 # CHECK: clti_s.w $w12, $w12, 11 +0x79 0x71 0xa7 0x47 # CHECK: clti_s.d $w29, $w20, 17 +0x79 0x9d 0x4b 0x87 # CHECK: clti_u.b $w14, $w9, 29 +0x79 0xb9 0xce 0x07 # CHECK: clti_u.h $w24, $w25, 25 +0x79 0xd6 0x08 0x47 # CHECK: clti_u.w $w1, $w1, 22 +0x79 0xe1 0xcd 0x47 # CHECK: clti_u.d $w21, $w25, 1 +0x79 0x01 0xad 0x86 # CHECK: maxi_s.b $w22, $w21, 1 +0x79 0x38 0x2f 0x46 # CHECK: maxi_s.h $w29, $w5, 24 +0x79 0x54 0x50 0x46 # CHECK: maxi_s.w $w1, $w10, 20 +0x79 0x70 0xeb 0x46 # CHECK: maxi_s.d $w13, $w29, 16 +0x79 0x8c 0x05 0x06 # CHECK: maxi_u.b $w20, $w0, 12 +0x79 0xa3 0x70 0x46 # CHECK: maxi_u.h $w1, $w14, 3 +0x79 0xcb 0xb6 0xc6 # CHECK: maxi_u.w $w27, $w22, 11 +0x79 0xe4 0x36 0x86 # CHECK: maxi_u.d $w26, $w6, 4 +0x7a 0x01 0x09 0x06 # CHECK: mini_s.b $w4, $w1, 1 +0x7a 0x37 0xde 0xc6 # CHECK: mini_s.h $w27, $w27, 23 +0x7a 0x49 0x5f 0x06 # CHECK: mini_s.w $w28, $w11, 9 +0x7a 0x6a 0x52 0xc6 # CHECK: mini_s.d $w11, $w10, 10 +0x7a 0x9b 0xbc 0x86 # CHECK: mini_u.b $w18, $w23, 27 +0x7a 0xb2 0xd1 0xc6 # CHECK: mini_u.h $w7, $w26, 18 +0x7a 0xda 0x62 0xc6 # CHECK: mini_u.w $w11, $w12, 26 +0x7a 0xe2 0x7a 0xc6 # CHECK: mini_u.d $w11, $w15, 2 +0x78 0x93 0xa6 0x06 # CHECK: subvi.b $w24, $w20, 19 +0x78 0xa4 0x9a 0xc6 # CHECK: subvi.h $w11, $w19, 4 +0x78 0xcb 0x53 0x06 # CHECK: subvi.w $w12, $w10, 11 +0x78 0xe7 0x84 0xc6 # CHECK: subvi.d $w19, $w16, 7 diff --git a/test/MC/Disassembler/Mips/msa/test_i8.txt b/test/MC/Disassembler/Mips/msa/test_i8.txt new file mode 100644 index 0000000..e08c39b --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_i8.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32 -mattr=+msa | FileCheck %s + +0x78 0x30 0xe8 0x80 # CHECK: andi.b $w2, $w29, 48 +0x78 0x7e 0xb1 0x81 # CHECK: bmnzi.b $w6, $w22, 126 +0x79 0x58 0x0e 0xc1 # CHECK: bmzi.b $w27, $w1, 88 +0x7a 0xbd 0x1f 0x41 # CHECK: bseli.b $w29, $w3, 189 +0x7a 0x38 0x88 0x40 # CHECK: nori.b $w1, $w17, 56 +0x79 0x87 0xa6 0x80 # CHECK: ori.b $w26, $w20, 135 +0x78 0x69 0xf4 0xc2 # CHECK: shf.b $w19, $w30, 105 +0x79 0x4c 0x44 0x42 # CHECK: shf.h $w17, $w8, 76 +0x7a 0x5d 0x1b 0x82 # CHECK: shf.w $w14, $w3, 93 +0x7b 0x14 0x54 0x00 # CHECK: xori.b $w16, $w10, 20 diff --git a/test/MC/Disassembler/Mips/msa/test_lsa.txt b/test/MC/Disassembler/Mips/msa/test_lsa.txt new file mode 100644 index 0000000..c3e950b --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_lsa.txt @@ -0,0 +1,6 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x01 0x2a 0x40 0x05 # CHECK: lsa $8, $9, $10, 1 +0x01 0x2a 0x40 0x45 # CHECK: lsa $8, $9, $10, 2 +0x01 0x2a 0x40 0x85 # CHECK: lsa $8, $9, $10, 3 +0x01 0x2a 0x40 0xc5 # CHECK: lsa $8, $9, $10, 4 diff --git a/test/MC/Disassembler/Mips/msa/test_mi10.txt b/test/MC/Disassembler/Mips/msa/test_mi10.txt new file mode 100644 index 0000000..b75b49e --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_mi10.txt @@ -0,0 +1,28 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32 -mattr=+msa | FileCheck %s + +0x7a 0x00 0x08 0x20 # CHECK: ld.b $w0, -512($1) +0x78 0x00 0x10 0x60 # CHECK: ld.b $w1, 0($2) +0x79 0xff 0x18 0xa0 # CHECK: ld.b $w2, 511($3) + +0x7a 0x00 0x20 0xe1 # CHECK: ld.h $w3, -1024($4) +0x7b 0x00 0x29 0x21 # CHECK: ld.h $w4, -512($5) +0x78 0x00 0x31 0x61 # CHECK: ld.h $w5, 0($6) +0x79 0x00 0x39 0xa1 # CHECK: ld.h $w6, 512($7) +0x79 0xff 0x41 0xe1 # CHECK: ld.h $w7, 1022($8) + +0x7a 0x00 0x4a 0x22 # CHECK: ld.w $w8, -2048($9) +0x7b 0x00 0x52 0x62 # CHECK: ld.w $w9, -1024($10) +0x7b 0x80 0x5a 0xa2 # CHECK: ld.w $w10, -512($11) +0x78 0x80 0x62 0xe2 # CHECK: ld.w $w11, 512($12) +0x79 0x00 0x6b 0x22 # CHECK: ld.w $w12, 1024($13) +0x79 0xff 0x73 0x62 # CHECK: ld.w $w13, 2044($14) + +0x7a 0x00 0x7b 0xa3 # CHECK: ld.d $w14, -4096($15) +0x7b 0x00 0x83 0xe3 # CHECK: ld.d $w15, -2048($16) +0x7b 0x80 0x8c 0x23 # CHECK: ld.d $w16, -1024($17) +0x7b 0xc0 0x94 0x63 # CHECK: ld.d $w17, -512($18) +0x78 0x00 0x9c 0xa3 # CHECK: ld.d $w18, 0($19) +0x78 0x40 0xa4 0xe3 # CHECK: ld.d $w19, 512($20) +0x78 0x80 0xad 0x23 # CHECK: ld.d $w20, 1024($21) +0x79 0x00 0xb5 0x63 # CHECK: ld.d $w21, 2048($22) +0x79 0xff 0xbd 0xa3 # CHECK: ld.d $w22, 4088($23) diff --git a/test/MC/Disassembler/Mips/msa/test_vec.txt b/test/MC/Disassembler/Mips/msa/test_vec.txt new file mode 100644 index 0000000..eff984f --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_vec.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32 -mattr=+msa | FileCheck %s + +0x78 0x1b 0xa6 0x5e # CHECK: and.v $w25, $w20, $w27 +0x78 0x87 0x34 0x5e # CHECK: bmnz.v $w17, $w6, $w7 +0x78 0xa9 0x88 0xde # CHECK: bmz.v $w3, $w17, $w9 +0x78 0xce 0x02 0x1e # CHECK: bsel.v $w8, $w0, $w14 +0x78 0x40 0xf9 0xde # CHECK: nor.v $w7, $w31, $w0 +0x78 0x3e 0xd6 0x1e # CHECK: or.v $w24, $w26, $w30 +0x78 0x6f 0xd9 0xde # CHECK: xor.v $w7, $w27, $w15 diff --git a/test/MC/Disassembler/Sparc/sparc-fp.txt b/test/MC/Disassembler/Sparc/sparc-fp.txt index b279da8..b8a5017 100644 --- a/test/MC/Disassembler/Sparc/sparc-fp.txt +++ b/test/MC/Disassembler/Sparc/sparc-fp.txt @@ -120,13 +120,13 @@ # CHECK: fdivq %f0, %f4, %f8 0x91 0xa0 0x09 0xe4 -# CHECK: fcmps %fcc0, %f0, %f4 +# CHECK: fcmps %f0, %f4 0x81 0xa8 0x0a 0x24 -# CHECK: fcmpd %fcc0, %f0, %f4 +# CHECK: fcmpd %f0, %f4 0x81 0xa8 0x0a 0x44 -# CHECK: fcmpq %fcc0, %f0, %f4 +# CHECK: fcmpq %f0, %f4 0x81 0xa8 0x0a 0x64 # CHECK: fxtos %f0, %f4 diff --git a/test/MC/Disassembler/X86/prefixes.txt b/test/MC/Disassembler/X86/prefixes.txt index 56596e3..b8830dc 100644 --- a/test/MC/Disassembler/X86/prefixes.txt +++ b/test/MC/Disassembler/X86/prefixes.txt @@ -44,6 +44,10 @@ # CHECK-NEXT: nop 0xf0 0x90 +# Test that immediate is printed correctly within opsize prefix +# CHECK: addw $-12, %ax +0x66,0x83,0xc0,0xf4 + # Test that multiple redundant prefixes work (redundant, but valid x86). # CHECK: rep # CHECK-NEXT: rep diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt index a4a0b2c..c9c5086 100644 --- a/test/MC/Disassembler/X86/x86-32.txt +++ b/test/MC/Disassembler/X86/x86-32.txt @@ -708,3 +708,6 @@ # CHECK: movl $4294967295, %eax 0xc7 0xc0 0xff 0xff 0xff 0xff + +# CHECK: movq %mm0, %mm1 +0x0f 0x7f 0xc1 |