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| author | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
| commit | dce4a407a24b04eebc6a376f8e62b41aaa7b071f (patch) | |
| tree | dcebc53f2b182f145a2e659393bf9a0472cedf23 /test/MC | |
| parent | 220b921aed042f9e520c26cffd8282a94c66c3d5 (diff) | |
| download | external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.zip external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.gz external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.bz2 | |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
Diffstat (limited to 'test/MC')
319 files changed, 22226 insertions, 8859 deletions
diff --git a/test/MC/AArch64/arm64-adr.s b/test/MC/AArch64/arm64-adr.s new file mode 100644 index 0000000..131e545 --- /dev/null +++ b/test/MC/AArch64/arm64-adr.s @@ -0,0 +1,31 @@ +// RUN: not llvm-mc -triple arm64 -show-encoding < %s 2>%t | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +adr x0, #0 +adr x0, #1 +adr x0, 1f +adr x0, foo +// CHECK: adr x0, #0 // encoding: [0x00,0x00,0x00,0x10] +// CHECK: adr x0, #1 // encoding: [0x00,0x00,0x00,0x30] +// CHECK: adr x0, .Ltmp0 // encoding: [A,A,A,0x10'A'] +// CHECK-NEXT: // fixup A - offset: 0, value: .Ltmp0, kind: fixup_aarch64_pcrel_adr_imm21 +// CHECK: adr x0, foo // encoding: [A,A,A,0x10'A'] +// CHECK-NEXT: // fixup A - offset: 0, value: foo, kind: fixup_aarch64_pcrel_adr_imm21 + +adrp x0, #0 +adrp x0, #4096 +adrp x0, 1f +adrp x0, foo +// CHECK: adrp x0, #0 // encoding: [0x00,0x00,0x00,0x90] +// CHECK: adrp x0, #4096 // encoding: [0x00,0x00,0x00,0xb0] +// CHECK: adrp x0, .Ltmp0 // encoding: [A,A,A,0x90'A'] +// CHECK-NEXT: // fixup A - offset: 0, value: .Ltmp0, kind: fixup_aarch64_pcrel_adrp_imm21 +// CHECK: adrp x0, foo // encoding: [A,A,A,0x90'A'] +// CHECK-NEXT: // fixup A - offset: 0, value: foo, kind: fixup_aarch64_pcrel_adrp_imm21 + +adr x0, #0xffffffff +adrp x0, #0xffffffff +adrp x0, #1 +// CHECK-ERRORS: error: expected label or encodable integer pc offset +// CHECK-ERRORS: error: expected label or encodable integer pc offset +// CHECK-ERRORS: error: expected label or encodable integer pc offset diff --git a/test/MC/ARM64/advsimd.s b/test/MC/AArch64/arm64-advsimd.s index fce0832..c627de7 100644 --- a/test/MC/ARM64/advsimd.s +++ b/test/MC/AArch64/arm64-advsimd.s @@ -1,4 +1,4 @@ -; RUN: llvm-mc -triple arm64-apple-darwin -output-asm-variant=1 -show-encoding < %s | FileCheck %s +; RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 -show-encoding < %s | FileCheck %s foo: @@ -193,10 +193,10 @@ foo: ; CHECK: smov.s x3, v2[2] ; encoding: [0x43,0x2c,0x14,0x4e] ; CHECK: smov.s x3, v2[2] ; encoding: [0x43,0x2c,0x14,0x4e] -; CHECK: umov.s w3, v2[2] ; encoding: [0x43,0x3c,0x14,0x0e] -; CHECK: umov.s w3, v2[2] ; encoding: [0x43,0x3c,0x14,0x0e] -; CHECK: umov.d x3, v2[1] ; encoding: [0x43,0x3c,0x18,0x4e] -; CHECK: umov.d x3, v2[1] ; encoding: [0x43,0x3c,0x18,0x4e] +; CHECK: mov.s w3, v2[2] ; encoding: [0x43,0x3c,0x14,0x0e] +; CHECK: mov.s w3, v2[2] ; encoding: [0x43,0x3c,0x14,0x0e] +; CHECK: mov.d x3, v2[1] ; encoding: [0x43,0x3c,0x18,0x4e] +; CHECK: mov.d x3, v2[1] ; encoding: [0x43,0x3c,0x18,0x4e] ; MOV aliases for UMOV instructions above @@ -205,10 +205,10 @@ foo: mov.d x11, v13[1] mov x17, v19.d[0] -; CHECK: umov.s w2, v3[3] ; encoding: [0x62,0x3c,0x1c,0x0e] -; CHECK: umov.s w5, v7[2] ; encoding: [0xe5,0x3c,0x14,0x0e] -; CHECK: umov.d x11, v13[1] ; encoding: [0xab,0x3d,0x18,0x4e] -; CHECK: umov.d x17, v19[0] ; encoding: [0x71,0x3e,0x08,0x4e] +; CHECK: mov.s w2, v3[3] ; encoding: [0x62,0x3c,0x1c,0x0e] +; CHECK: mov.s w5, v7[2] ; encoding: [0xe5,0x3c,0x14,0x0e] +; CHECK: mov.d x11, v13[1] ; encoding: [0xab,0x3d,0x18,0x4e] +; CHECK: mov.d x17, v19[0] ; encoding: [0x71,0x3e,0x08,0x4e] ins.d v2[1], x5 ins.s v2[1], w5 @@ -445,14 +445,14 @@ foo: bsl.8b v0, v0, v0 eor.8b v0, v0, v0 orn.8b v0, v0, v0 - orr.8b v0, v0, v0 + orr.8b v0, v0, v1 ; CHECK: bif.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xe0,0x2e] ; CHECK: bit.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xa0,0x2e] ; CHECK: bsl.8b v0, v0, v0 ; encoding: [0x00,0x1c,0x60,0x2e] ; CHECK: eor.8b v0, v0, v0 ; encoding: [0x00,0x1c,0x20,0x2e] ; CHECK: orn.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xe0,0x0e] -; CHECK: orr.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xa0,0x0e] +; CHECK: orr.8b v0, v0, v1 ; encoding: [0x00,0x1c,0xa1,0x0e] sadalp.4h v0, v0 sadalp.8h v0, v0 @@ -534,7 +534,7 @@ foo: ; CHECK: frsqrte.2s v0, v0 ; encoding: [0x00,0xd8,0xa1,0x2e] ; CHECK: fsqrt.2s v0, v0 ; encoding: [0x00,0xf8,0xa1,0x2e] ; CHECK: neg.8b v0, v0 ; encoding: [0x00,0xb8,0x20,0x2e] -; CHECK: not.8b v0, v0 ; encoding: [0x00,0x58,0x20,0x2e] +; CHECK: mvn.8b v0, v0 ; encoding: [0x00,0x58,0x20,0x2e] ; CHECK: rbit.8b v0, v0 ; encoding: [0x00,0x58,0x60,0x2e] ; CHECK: rev16.8b v0, v0 ; encoding: [0x00,0x18,0x20,0x0e] ; CHECK: rev32.8b v0, v0 ; encoding: [0x00,0x08,0x20,0x2e] @@ -608,11 +608,11 @@ foo: ; CHECK: cmgt.8b v0, v0, #0 ; encoding: [0x00,0x88,0x20,0x0e] ; CHECK: cmle.8b v0, v0, #0 ; encoding: [0x00,0x98,0x20,0x2e] ; CHECK: cmlt.8b v0, v0, #0 ; encoding: [0x00,0xa8,0x20,0x0e] -; CHECK: fcmeq.2s v0, v0, #0 ; encoding: [0x00,0xd8,0xa0,0x0e] -; CHECK: fcmge.2s v0, v0, #0 ; encoding: [0x00,0xc8,0xa0,0x2e] -; CHECK: fcmgt.2s v0, v0, #0 ; encoding: [0x00,0xc8,0xa0,0x0e] -; CHECK: fcmle.2s v0, v0, #0 ; encoding: [0x00,0xd8,0xa0,0x2e] -; CHECK: fcmlt.2s v0, v0, #0 ; encoding: [0x00,0xe8,0xa0,0x0e] +; CHECK: fcmeq.2s v0, v0, #0.0 ; encoding: [0x00,0xd8,0xa0,0x0e] +; CHECK: fcmge.2s v0, v0, #0.0 ; encoding: [0x00,0xc8,0xa0,0x2e] +; CHECK: fcmgt.2s v0, v0, #0.0 ; encoding: [0x00,0xc8,0xa0,0x0e] +; CHECK: fcmle.2s v0, v0, #0.0 ; encoding: [0x00,0xd8,0xa0,0x2e] +; CHECK: fcmlt.2s v0, v0, #0.0 ; encoding: [0x00,0xe8,0xa0,0x0e] ; CHECK: cmlt.8b v8, v14, #0 ; encoding: [0xc8,0xa9,0x20,0x0e] ; CHECK: cmlt.16b v8, v14, #0 ; encoding: [0xc8,0xa9,0x20,0x4e] ; CHECK: cmlt.4h v8, v14, #0 ; encoding: [0xc8,0xa9,0x60,0x0e] @@ -780,19 +780,19 @@ foo: bic.2s v0, #1, lsl #16 bic.2s v0, #1, lsl #24 -; CHECK: bic.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x2f] -; CHECK: bic.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x2f] -; CHECK: bic.2s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x2f] -; CHECK: bic.2s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x2f] -; CHECK: bic.2s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x2f] +; CHECK: bic.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x2f] +; CHECK: bic.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x2f] +; CHECK: bic.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x2f] +; CHECK: bic.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x2f] +; CHECK: bic.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x2f] bic.4h v0, #1 bic.4h v0, #1, lsl #0 bic.4h v0, #1, lsl #8 -; CHECK: bic.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x2f] -; CHECK: bic.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x2f] -; CHECK: bic.4h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x2f] +; CHECK: bic.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x2f] +; CHECK: bic.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x2f] +; CHECK: bic.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x2f] bic.4s v0, #1 bic.4s v0, #1, lsl #0 @@ -800,29 +800,29 @@ foo: bic.4s v0, #1, lsl #16 bic.4s v0, #1, lsl #24 -; CHECK: bic.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x6f] -; CHECK: bic.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x6f] -; CHECK: bic.4s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x6f] -; CHECK: bic.4s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x6f] -; CHECK: bic.4s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x6f] +; CHECK: bic.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x6f] +; CHECK: bic.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x6f] +; CHECK: bic.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x6f] +; CHECK: bic.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x6f] +; CHECK: bic.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x6f] bic.8h v0, #1 bic.8h v0, #1, lsl #0 bic.8h v0, #1, lsl #8 -; CHECK: bic.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x6f] -; CHECK: bic.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x6f] -; CHECK: bic.8h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x6f] +; CHECK: bic.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x6f] +; CHECK: bic.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x6f] +; CHECK: bic.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x6f] fmov.2d v0, #1.250000e-01 -; CHECK: fmov.2d v0, #1.250000e-01 ; encoding: [0x00,0xf4,0x02,0x6f] +; CHECK: fmov.2d v0, #0.12500000 ; encoding: [0x00,0xf4,0x02,0x6f] fmov.2s v0, #1.250000e-01 fmov.4s v0, #1.250000e-01 -; CHECK: fmov.2s v0, #1.250000e-01 ; encoding: [0x00,0xf4,0x02,0x0f] -; CHECK: fmov.4s v0, #1.250000e-01 ; encoding: [0x00,0xf4,0x02,0x4f] +; CHECK: fmov.2s v0, #0.12500000 ; encoding: [0x00,0xf4,0x02,0x0f] +; CHECK: fmov.4s v0, #0.12500000 ; encoding: [0x00,0xf4,0x02,0x4f] orr.2s v0, #1 orr.2s v0, #1, lsl #0 @@ -830,19 +830,19 @@ foo: orr.2s v0, #1, lsl #16 orr.2s v0, #1, lsl #24 -; CHECK: orr.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x0f] -; CHECK: orr.2s v0, #1 ; encoding: [0x20,0x14,0x00,0x0f] -; CHECK: orr.2s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x0f] -; CHECK: orr.2s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x0f] -; CHECK: orr.2s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x0f] +; CHECK: orr.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x0f] +; CHECK: orr.2s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x0f] +; CHECK: orr.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x0f] +; CHECK: orr.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x0f] +; CHECK: orr.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x0f] orr.4h v0, #1 orr.4h v0, #1, lsl #0 orr.4h v0, #1, lsl #8 -; CHECK: orr.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x0f] -; CHECK: orr.4h v0, #1 ; encoding: [0x20,0x94,0x00,0x0f] -; CHECK: orr.4h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x0f] +; CHECK: orr.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x0f] +; CHECK: orr.4h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x0f] +; CHECK: orr.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x0f] orr.4s v0, #1 orr.4s v0, #1, lsl #0 @@ -850,19 +850,19 @@ foo: orr.4s v0, #1, lsl #16 orr.4s v0, #1, lsl #24 -; CHECK: orr.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x4f] -; CHECK: orr.4s v0, #1 ; encoding: [0x20,0x14,0x00,0x4f] -; CHECK: orr.4s v0, #1, lsl #8 ; encoding: [0x20,0x34,0x00,0x4f] -; CHECK: orr.4s v0, #1, lsl #16 ; encoding: [0x20,0x54,0x00,0x4f] -; CHECK: orr.4s v0, #1, lsl #24 ; encoding: [0x20,0x74,0x00,0x4f] +; CHECK: orr.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x4f] +; CHECK: orr.4s v0, #0x1 ; encoding: [0x20,0x14,0x00,0x4f] +; CHECK: orr.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x34,0x00,0x4f] +; CHECK: orr.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x54,0x00,0x4f] +; CHECK: orr.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x74,0x00,0x4f] orr.8h v0, #1 orr.8h v0, #1, lsl #0 orr.8h v0, #1, lsl #8 -; CHECK: orr.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x4f] -; CHECK: orr.8h v0, #1 ; encoding: [0x20,0x94,0x00,0x4f] -; CHECK: orr.8h v0, #1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x4f] +; CHECK: orr.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x4f] +; CHECK: orr.8h v0, #0x1 ; encoding: [0x20,0x94,0x00,0x4f] +; CHECK: orr.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xb4,0x00,0x4f] movi d0, #0x000000000000ff movi.2d v0, #0x000000000000ff @@ -876,11 +876,11 @@ foo: movi.2s v0, #1, lsl #16 movi.2s v0, #1, lsl #24 -; CHECK: movi.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x0f] -; CHECK: movi.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x0f] -; CHECK: movi.2s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x0f] -; CHECK: movi.2s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x0f] -; CHECK: movi.2s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x0f] +; CHECK: movi.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x0f] +; CHECK: movi.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x0f] +; CHECK: movi.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x0f] +; CHECK: movi.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x0f] +; CHECK: movi.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x0f] movi.4s v0, #1 movi.4s v0, #1, lsl #0 @@ -888,43 +888,43 @@ foo: movi.4s v0, #1, lsl #16 movi.4s v0, #1, lsl #24 -; CHECK: movi.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x4f] -; CHECK: movi.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x4f] -; CHECK: movi.4s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x4f] -; CHECK: movi.4s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x4f] -; CHECK: movi.4s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x4f] +; CHECK: movi.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x4f] +; CHECK: movi.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x4f] +; CHECK: movi.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x4f] +; CHECK: movi.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x4f] +; CHECK: movi.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x4f] movi.4h v0, #1 movi.4h v0, #1, lsl #0 movi.4h v0, #1, lsl #8 -; CHECK: movi.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x0f] -; CHECK: movi.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x0f] -; CHECK: movi.4h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x0f] +; CHECK: movi.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x0f] +; CHECK: movi.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x0f] +; CHECK: movi.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x0f] movi.8h v0, #1 movi.8h v0, #1, lsl #0 movi.8h v0, #1, lsl #8 -; CHECK: movi.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x4f] -; CHECK: movi.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x4f] -; CHECK: movi.8h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x4f] +; CHECK: movi.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x4f] +; CHECK: movi.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x4f] +; CHECK: movi.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x4f] movi.2s v0, #1, msl #8 movi.2s v0, #1, msl #16 movi.4s v0, #1, msl #8 movi.4s v0, #1, msl #16 -; CHECK: movi.2s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x0f] -; CHECK: movi.2s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x0f] -; CHECK: movi.4s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x4f] -; CHECK: movi.4s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x4f] +; CHECK: movi.2s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x0f] +; CHECK: movi.2s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x0f] +; CHECK: movi.4s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x4f] +; CHECK: movi.4s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x4f] movi.8b v0, #1 movi.16b v0, #1 -; CHECK: movi.8b v0, #1 ; encoding: [0x20,0xe4,0x00,0x0f] -; CHECK: movi.16b v0, #1 ; encoding: [0x20,0xe4,0x00,0x4f] +; CHECK: movi.8b v0, #0x1 ; encoding: [0x20,0xe4,0x00,0x0f] +; CHECK: movi.16b v0, #0x1 ; encoding: [0x20,0xe4,0x00,0x4f] mvni.2s v0, #1 mvni.2s v0, #1, lsl #0 @@ -932,11 +932,11 @@ foo: mvni.2s v0, #1, lsl #16 mvni.2s v0, #1, lsl #24 -; CHECK: mvni.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x2f] -; CHECK: mvni.2s v0, #1 ; encoding: [0x20,0x04,0x00,0x2f] -; CHECK: mvni.2s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x2f] -; CHECK: mvni.2s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x2f] -; CHECK: mvni.2s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x2f] mvni.4s v0, #1 mvni.4s v0, #1, lsl #0 @@ -944,37 +944,37 @@ foo: mvni.4s v0, #1, lsl #16 mvni.4s v0, #1, lsl #24 -; CHECK: mvni.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x6f] -; CHECK: mvni.4s v0, #1 ; encoding: [0x20,0x04,0x00,0x6f] -; CHECK: mvni.4s v0, #1, lsl #8 ; encoding: [0x20,0x24,0x00,0x6f] -; CHECK: mvni.4s v0, #1, lsl #16 ; encoding: [0x20,0x44,0x00,0x6f] -; CHECK: mvni.4s v0, #1, lsl #24 ; encoding: [0x20,0x64,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1 ; encoding: [0x20,0x04,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1, lsl #8 ; encoding: [0x20,0x24,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1, lsl #16 ; encoding: [0x20,0x44,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1, lsl #24 ; encoding: [0x20,0x64,0x00,0x6f] mvni.4h v0, #1 mvni.4h v0, #1, lsl #0 mvni.4h v0, #1, lsl #8 -; CHECK: mvni.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x2f] -; CHECK: mvni.4h v0, #1 ; encoding: [0x20,0x84,0x00,0x2f] -; CHECK: mvni.4h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x2f] +; CHECK: mvni.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x2f] +; CHECK: mvni.4h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x2f] +; CHECK: mvni.4h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x2f] mvni.8h v0, #1 mvni.8h v0, #1, lsl #0 mvni.8h v0, #1, lsl #8 -; CHECK: mvni.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x6f] -; CHECK: mvni.8h v0, #1 ; encoding: [0x20,0x84,0x00,0x6f] -; CHECK: mvni.8h v0, #1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x6f] +; CHECK: mvni.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x6f] +; CHECK: mvni.8h v0, #0x1 ; encoding: [0x20,0x84,0x00,0x6f] +; CHECK: mvni.8h v0, #0x1, lsl #8 ; encoding: [0x20,0xa4,0x00,0x6f] mvni.2s v0, #1, msl #8 mvni.2s v0, #1, msl #16 mvni.4s v0, #1, msl #8 mvni.4s v0, #1, msl #16 -; CHECK: mvni.2s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x2f] -; CHECK: mvni.2s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x2f] -; CHECK: mvni.4s v0, #1, msl #8 ; encoding: [0x20,0xc4,0x00,0x6f] -; CHECK: mvni.4s v0, #1, msl #16 ; encoding: [0x20,0xd4,0x00,0x6f] +; CHECK: mvni.2s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x2f] +; CHECK: mvni.2s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x2f] +; CHECK: mvni.4s v0, #0x1, msl #8 ; encoding: [0x20,0xc4,0x00,0x6f] +; CHECK: mvni.4s v0, #0x1, msl #16 ; encoding: [0x20,0xd4,0x00,0x6f] ;===-------------------------------------------------------------------------=== ; AdvSIMD scalar x index @@ -1843,8 +1843,8 @@ foo: mov.16b v0, v0 mov.2s v0, v0 -; CHECK: orr.16b v0, v0, v0 ; encoding: [0x00,0x1c,0xa0,0x4e] -; CHECK: orr.8b v0, v0, v0 ; encoding: [0x00,0x1c,0xa0,0x0e] +; CHECK: mov.16b v0, v0 ; encoding: [0x00,0x1c,0xa0,0x4e] +; CHECK: mov.8b v0, v0 ; encoding: [0x00,0x1c,0xa0,0x0e] ; uadalp/sadalp verbose mode aliases. @@ -1881,10 +1881,10 @@ foo: mvn.8b v10, v6 mvn.16b v11, v7 -; CHECK: not.8b v1, v4 ; encoding: [0x81,0x58,0x20,0x2e] -; CHECK: not.16b v19, v17 ; encoding: [0x33,0x5a,0x20,0x6e] -; CHECK: not.8b v10, v6 ; encoding: [0xca,0x58,0x20,0x2e] -; CHECK: not.16b v11, v7 ; encoding: [0xeb,0x58,0x20,0x6e] +; CHECK: mvn.8b v1, v4 ; encoding: [0x81,0x58,0x20,0x2e] +; CHECK: mvn.16b v19, v17 ; encoding: [0x33,0x5a,0x20,0x6e] +; CHECK: mvn.8b v10, v6 ; encoding: [0xca,0x58,0x20,0x2e] +; CHECK: mvn.16b v11, v7 ; encoding: [0xeb,0x58,0x20,0x6e] ; sqdmull verbose mode aliases sqdmull v10.4s, v12.4h, v12.4h diff --git a/test/MC/ARM64/aliases.s b/test/MC/AArch64/arm64-aliases.s index 055edb5..c3affe3 100644 --- a/test/MC/ARM64/aliases.s +++ b/test/MC/AArch64/arm64-aliases.s @@ -1,4 +1,4 @@ -; RUN: llvm-mc -triple arm64-apple-darwin -output-asm-variant=1 -show-encoding < %s | FileCheck %s +; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon -output-asm-variant=1 -show-encoding < %s | FileCheck %s foo: ;----------------------------------------------------------------------------- @@ -67,7 +67,7 @@ foo: cmn x4, x5, uxtx #1 ; CHECK: cmn w1, #3 ; encoding: [0x3f,0x0c,0x00,0x31] -; CHECK: cmn x2, #4194304 ; encoding: [0x5f,0x00,0x50,0xb1] +; CHECK: cmn x2, #1024, lsl #12 ; encoding: [0x5f,0x00,0x50,0xb1] ; CHECK: cmn w4, w5 ; encoding: [0x9f,0x00,0x05,0x2b] ; CHECK: cmn x6, x7 ; encoding: [0xdf,0x00,0x07,0xab] ; CHECK: cmn w8, w9, asr #3 ; encoding: [0x1f,0x0d,0x89,0x2b] @@ -92,7 +92,7 @@ foo: cmp w9, w8, uxtw cmp wsp, w9, lsl #0 -; CHECK: cmp w1, #4194304 ; encoding: [0x3f,0x00,0x50,0x71] +; CHECK: cmp w1, #1024, lsl #12 ; encoding: [0x3f,0x00,0x50,0x71] ; CHECK: cmp x2, #1024 ; encoding: [0x5f,0x00,0x10,0xf1] ; CHECK: cmp w4, w5 ; encoding: [0x9f,0x00,0x05,0x6b] ; CHECK: cmp x6, x7 ; encoding: [0xdf,0x00,0x07,0xeb] @@ -103,7 +103,7 @@ foo: ; CHECK: cmp wzr, w1 ; encoding: [0xff,0x03,0x01,0x6b] ; CHECK: cmp x8, w8, uxtw ; encoding: [0x1f,0x41,0x28,0xeb] ; CHECK: cmp w9, w8, uxtw ; encoding: [0x3f,0x41,0x28,0x6b] -; CHECK: cmp wsp, w9 ; encoding: [0xff,0x63,0x29,0x6b] +; CHECK: cmp wsp, w9 ; encoding: [0xff,0x43,0x29,0x6b] ;----------------------------------------------------------------------------- @@ -113,19 +113,19 @@ foo: neg w0, w1 ; CHECK: neg w0, w1 neg w0, w1, lsl #1 -; CHECK: sub w0, wzr, w1, lsl #1 +; CHECK: neg w0, w1, lsl #1 neg x0, x1 ; CHECK: neg x0, x1 neg x0, x1, asr #1 -; CHECK: sub x0, xzr, x1, asr #1 +; CHECK: neg x0, x1, asr #1 negs w0, w1 ; CHECK: negs w0, w1 negs w0, w1, lsl #1 -; CHECK: subs w0, wzr, w1, lsl #1 +; CHECK: negs w0, w1, lsl #1 negs x0, x1 ; CHECK: negs x0, x1 negs x0, x1, asr #1 -; CHECK: subs x0, xzr, x1, asr #1 +; CHECK: negs x0, x1, asr #1 ;----------------------------------------------------------------------------- ; MOV aliases @@ -134,14 +134,18 @@ foo: mov x0, #281470681743360 mov x0, #18446744073709486080 -; CHECK: movz x0, #65535, lsl #32 -; CHECK: movn x0, #65535 +; CHECK: movz x0, #0xffff, lsl #32 +; CHECK: movn x0, #0xffff mov w0, #0xffffffff mov w0, #0xffffff00 + mov wzr, #0xffffffff + mov wzr, #0xffffff00 ; CHECK: movn w0, #0 -; CHECK: movn w0, #255 +; CHECK: movn w0, #0xff +; CHECK: movn wzr, #0 +; CHECK: movn wzr, #0xff ;----------------------------------------------------------------------------- ; MVN aliases @@ -155,6 +159,14 @@ foo: ; CHECK: mvn x2, x3 ; encoding: [0xe2,0x03,0x23,0xaa] ; CHECK: mvn w4, w9 ; encoding: [0xe4,0x03,0x29,0x2a] + mvn w4, w9, lsl #1 + mvn x2, x3, lsl #1 + orn w4, wzr, w9, lsl #1 + +; CHECK: mvn w4, w9, lsl #1 ; encoding: [0xe4,0x07,0x29,0x2a] +; CHECK: mvn x2, x3, lsl #1 ; encoding: [0xe2,0x07,0x23,0xaa] +; CHECK: mvn w4, w9, lsl #1 ; encoding: [0xe4,0x07,0x29,0x2a] + ;----------------------------------------------------------------------------- ; Bitfield aliases ;----------------------------------------------------------------------------- @@ -174,20 +186,20 @@ foo: ubfx w0, w0, #2, #3 ubfx x0, x0, #2, #3 -; CHECK: bfm w0, w0, #31, #3 -; CHECK: bfm x0, x0, #63, #3 -; CHECK: bfm w0, w0, #0, #1 -; CHECK: bfm x0, x0, #0, #1 -; CHECK: bfm w0, w0, #2, #4 -; CHECK: bfm x0, x0, #2, #4 -; CHECK: sbfm w0, w0, #31, #3 -; CHECK: sbfm x0, x0, #63, #3 -; CHECK: sbfm w0, w0, #2, #4 -; CHECK: sbfm x0, x0, #2, #4 -; CHECK: ubfm w0, w0, #31, #3 -; CHECK: ubfm x0, x0, #63, #3 -; CHECK: ubfm w0, w0, #2, #4 -; CHECK: ubfm x0, x0, #2, #4 +; CHECK: bfi w0, w0, #1, #4 +; CHECK: bfi x0, x0, #1, #4 +; CHECK: bfxil w0, w0, #0, #2 +; CHECK: bfxil x0, x0, #0, #2 +; CHECK: bfxil w0, w0, #2, #3 +; CHECK: bfxil x0, x0, #2, #3 +; CHECK: sbfiz w0, w0, #1, #4 +; CHECK: sbfiz x0, x0, #1, #4 +; CHECK: sbfx w0, w0, #2, #3 +; CHECK: sbfx x0, x0, #2, #3 +; CHECK: ubfiz w0, w0, #1, #4 +; CHECK: ubfiz x0, x0, #1, #4 +; CHECK: ubfx w0, w0, #2, #3 +; CHECK: ubfx x0, x0, #2, #3 ;----------------------------------------------------------------------------- ; Shift (immediate) aliases @@ -206,8 +218,8 @@ foo: ubfm x0, x0, #63, #62 ubfm w0, w0, #4, #31 ubfm x0, x0, #4, #63 -; CHECK: extr w1, w3, w3, #5 -; CHECK: extr x1, x3, x3, #5 +; CHECK: ror w1, w3, #5 +; CHECK: ror x1, x3, #5 ror w1, w3, #5 ror x1, x3, #5 ; CHECK: lsl w1, wzr, #3 @@ -227,19 +239,19 @@ foo: ; CHECK: uxtb w1, w2 ; CHECK: uxth w1, w2 - sxtb x1, x2 - sxth x1, x2 - sxtw x1, x2 - uxtb x1, x2 - uxth x1, x2 - uxtw x1, x2 + sxtb x1, w2 + sxth x1, w2 + sxtw x1, w2 + uxtb x1, w2 + uxth x1, w2 + uxtw x1, w2 -; CHECK: sxtb x1, x2 -; CHECK: sxth x1, x2 -; CHECK: sxtw x1, x2 -; CHECK: uxtb x1, x2 -; CHECK: uxth x1, x2 -; CHECK: uxtw x1, x2 +; CHECK: sxtb x1, w2 +; CHECK: sxth x1, w2 +; CHECK: sxtw x1, w2 +; CHECK: uxtb w1, w2 +; CHECK: uxth w1, w2 +; CHECK: ubfx x1, x2, #0, #32 ;----------------------------------------------------------------------------- ; Negate with carry @@ -290,14 +302,14 @@ foo: cinv w1, w2, mi cinv x1, x2, mi -; CHECK: csinc w1, wzr, wzr, ne -; CHECK: csinc x1, xzr, xzr, ne -; CHECK: csinv w1, wzr, wzr, eq -; CHECK: csinv x1, xzr, xzr, eq -; CHECK: csinc w1, w2, w2, ge -; CHECK: csinc x1, x2, x2, ge -; CHECK: csinv w1, w2, w2, pl -; CHECK: csinv x1, x2, x2, pl +; CHECK: cset w1, eq +; CHECK: cset x1, eq +; CHECK: csetm w1, ne +; CHECK: csetm x1, ne +; CHECK: cinc w1, w2, lt +; CHECK: cinc x1, x2, lt +; CHECK: cinv w1, w2, mi +; CHECK: cinv x1, x2, mi ;----------------------------------------------------------------------------- ; SYS aliases @@ -408,120 +420,128 @@ foo: ; CHECK: tlbi ipas2e1 sys #4, c8, c4, #5 ; CHECK: tlbi ipas2le1 + sys #4, c8, c0, #1 +; CHECK: tlbi ipas2e1is + sys #4, c8, c0, #5 +; CHECK: tlbi ipas2le1is sys #4, c8, c7, #6 ; CHECK: tlbi vmalls12e1 sys #4, c8, c3, #6 ; CHECK: tlbi vmalls12e1is ic ialluis -; CHECK: ic ialluis +; CHECK: ic ialluis ; encoding: [0x1f,0x71,0x08,0xd5] ic iallu -; CHECK: ic iallu - ic ivau -; CHECK: ic ivau - - dc zva -; CHECK: dc zva - dc ivac -; CHECK: dc ivac - dc isw -; CHECK: dc isw - dc cvac -; CHECK: dc cvac - dc csw -; CHECK: dc csw - dc cvau -; CHECK: dc cvau - dc civac -; CHECK: dc civac - dc cisw -; CHECK: dc cisw - - at s1e1r -; CHECK: at s1e1r - at s1e2r -; CHECK: at s1e2r - at s1e3r -; CHECK: at s1e3r - at s1e1w -; CHECK: at s1e1w - at s1e2w -; CHECK: at s1e2w - at s1e3w -; CHECK: at s1e3w - at s1e0r -; CHECK: at s1e0r - at s1e0w -; CHECK: at s1e0w - at s12e1r -; CHECK: at s12e1r - at s12e1w -; CHECK: at s12e1w - at s12e0r -; CHECK: at s12e0r - at s12e0w -; CHECK: at s12e0w +; CHECK: ic iallu ; encoding: [0x1f,0x75,0x08,0xd5] + ic ivau, x0 +; CHECK: ic ivau, x0 ; encoding: [0x20,0x75,0x0b,0xd5] + + dc zva, x0 +; CHECK: dc zva, x0 ; encoding: [0x20,0x74,0x0b,0xd5] + dc ivac, x0 +; CHECK: dc ivac, x0 ; encoding: [0x20,0x76,0x08,0xd5] + dc isw, x0 +; CHECK: dc isw, x0 ; encoding: [0x40,0x76,0x08,0xd5] + dc cvac, x0 +; CHECK: dc cvac, x0 ; encoding: [0x20,0x7a,0x0b,0xd5] + dc csw, x0 +; CHECK: dc csw, x0 ; encoding: [0x40,0x7a,0x08,0xd5] + dc cvau, x0 +; CHECK: dc cvau, x0 ; encoding: [0x20,0x7b,0x0b,0xd5] + dc civac, x0 +; CHECK: dc civac, x0 ; encoding: [0x20,0x7e,0x0b,0xd5] + dc cisw, x0 +; CHECK: dc cisw, x0 ; encoding: [0x40,0x7e,0x08,0xd5] + + at s1e1r, x0 +; CHECK: at s1e1r, x0 ; encoding: [0x00,0x78,0x08,0xd5] + at s1e2r, x0 +; CHECK: at s1e2r, x0 ; encoding: [0x00,0x78,0x0c,0xd5] + at s1e3r, x0 +; CHECK: at s1e3r, x0 ; encoding: [0x00,0x78,0x0e,0xd5] + at s1e1w, x0 +; CHECK: at s1e1w, x0 ; encoding: [0x20,0x78,0x08,0xd5] + at s1e2w, x0 +; CHECK: at s1e2w, x0 ; encoding: [0x20,0x78,0x0c,0xd5] + at s1e3w, x0 +; CHECK: at s1e3w, x0 ; encoding: [0x20,0x78,0x0e,0xd5] + at s1e0r, x0 +; CHECK: at s1e0r, x0 ; encoding: [0x40,0x78,0x08,0xd5] + at s1e0w, x0 +; CHECK: at s1e0w, x0 ; encoding: [0x60,0x78,0x08,0xd5] + at s12e1r, x0 +; CHECK: at s12e1r, x0 ; encoding: [0x80,0x78,0x0c,0xd5] + at s12e1w, x0 +; CHECK: at s12e1w, x0 ; encoding: [0xa0,0x78,0x0c,0xd5] + at s12e0r, x0 +; CHECK: at s12e0r, x0 ; encoding: [0xc0,0x78,0x0c,0xd5] + at s12e0w, x0 +; CHECK: at s12e0w, x0 ; encoding: [0xe0,0x78,0x0c,0xd5] tlbi vmalle1is -; CHECK: tlbi vmalle1is +; CHECK: tlbi vmalle1is ; encoding: [0x1f,0x83,0x08,0xd5] tlbi alle2is -; CHECK: tlbi alle2is +; CHECK: tlbi alle2is ; encoding: [0x1f,0x83,0x0c,0xd5] tlbi alle3is -; CHECK: tlbi alle3is - tlbi vae1is -; CHECK: tlbi vae1is - tlbi vae2is -; CHECK: tlbi vae2is - tlbi vae3is -; CHECK: tlbi vae3is - tlbi aside1is -; CHECK: tlbi aside1is - tlbi vaae1is -; CHECK: tlbi vaae1is +; CHECK: tlbi alle3is ; encoding: [0x1f,0x83,0x0e,0xd5] + tlbi vae1is, x0 +; CHECK: tlbi vae1is, x0 ; encoding: [0x20,0x83,0x08,0xd5] + tlbi vae2is, x0 +; CHECK: tlbi vae2is, x0 ; encoding: [0x20,0x83,0x0c,0xd5] + tlbi vae3is, x0 +; CHECK: tlbi vae3is, x0 ; encoding: [0x20,0x83,0x0e,0xd5] + tlbi aside1is, x0 +; CHECK: tlbi aside1is, x0 ; encoding: [0x40,0x83,0x08,0xd5] + tlbi vaae1is, x0 +; CHECK: tlbi vaae1is, x0 ; encoding: [0x60,0x83,0x08,0xd5] tlbi alle1is -; CHECK: tlbi alle1is - tlbi vale1is -; CHECK: tlbi vale1is - tlbi vaale1is -; CHECK: tlbi vaale1is +; CHECK: tlbi alle1is ; encoding: [0x9f,0x83,0x0c,0xd5] + tlbi vale1is, x0 +; CHECK: tlbi vale1is, x0 ; encoding: [0xa0,0x83,0x08,0xd5] + tlbi vaale1is, x0 +; CHECK: tlbi vaale1is, x0 ; encoding: [0xe0,0x83,0x08,0xd5] tlbi vmalle1 -; CHECK: tlbi vmalle1 +; CHECK: tlbi vmalle1 ; encoding: [0x1f,0x87,0x08,0xd5] tlbi alle2 -; CHECK: tlbi alle2 - tlbi vale2is -; CHECK: tlbi vale2is - tlbi vale3is -; CHECK: tlbi vale3is +; CHECK: tlbi alle2 ; encoding: [0x1f,0x87,0x0c,0xd5] + tlbi vale2is, x0 +; CHECK: tlbi vale2is, x0 ; encoding: [0xa0,0x83,0x0c,0xd5] + tlbi vale3is, x0 +; CHECK: tlbi vale3is, x0 ; encoding: [0xa0,0x83,0x0e,0xd5] tlbi alle3 -; CHECK: tlbi alle3 - tlbi vae1 -; CHECK: tlbi vae1 - tlbi vae2 -; CHECK: tlbi vae2 - tlbi vae3 -; CHECK: tlbi vae3 - tlbi aside1 -; CHECK: tlbi aside1 - tlbi vaae1 -; CHECK: tlbi vaae1 +; CHECK: tlbi alle3 ; encoding: [0x1f,0x87,0x0e,0xd5] + tlbi vae1, x0 +; CHECK: tlbi vae1, x0 ; encoding: [0x20,0x87,0x08,0xd5] + tlbi vae2, x0 +; CHECK: tlbi vae2, x0 ; encoding: [0x20,0x87,0x0c,0xd5] + tlbi vae3, x0 +; CHECK: tlbi vae3, x0 ; encoding: [0x20,0x87,0x0e,0xd5] + tlbi aside1, x0 +; CHECK: tlbi aside1, x0 ; encoding: [0x40,0x87,0x08,0xd5] + tlbi vaae1, x0 +; CHECK: tlbi vaae1, x0 ; encoding: [0x60,0x87,0x08,0xd5] tlbi alle1 -; CHECK: tlbi alle1 - tlbi vale1 -; CHECK: tlbi vale1 - tlbi vale2 -; CHECK: tlbi vale2 - tlbi vale3 -; CHECK: tlbi vale3 - tlbi vaale1 -; CHECK: tlbi vaale1 - tlbi ipas2e1, x10 -; CHECK: tlbi ipas2e1, x10 - tlbi ipas2le1, x1 -; CHECK: tlbi ipas2le1, x1 +; CHECK: tlbi alle1 ; encoding: [0x9f,0x87,0x0c,0xd5 + tlbi vale1, x0 +; CHECK: tlbi vale1, x0 ; encoding: [0xa0,0x87,0x08,0xd5] + tlbi vale2, x0 +; CHECK: tlbi vale2, x0 ; encoding: [0xa0,0x87,0x0c,0xd5] + tlbi vale3, x0 +; CHECK: tlbi vale3, x0 ; encoding: [0xa0,0x87,0x0e,0xd5] + tlbi vaale1, x0 +; CHECK: tlbi vaale1, x0 ; encoding: [0xe0,0x87,0x08,0xd5] + tlbi ipas2e1, x0 +; CHECK: tlbi ipas2e1, x0 ; encoding: [0x20,0x84,0x0c,0xd5] + tlbi ipas2le1, x0 +; CHECK: tlbi ipas2le1, x0 ; encoding: [0xa0,0x84,0x0c,0xd5] + tlbi ipas2e1is, x0 +; CHECK: tlbi ipas2e1is, x0 ; encoding: [0x20,0x80,0x0c,0xd5] + tlbi ipas2le1is, x0 +; CHECK: tlbi ipas2le1is, x0 ; encoding: [0xa0,0x80,0x0c,0xd5] tlbi vmalls12e1 -; CHECK: tlbi vmalls12e1 +; CHECK: tlbi vmalls12e1 ; encoding: [0xdf,0x87,0x0c,0xd5] tlbi vmalls12e1is -; CHECK: tlbi vmalls12e1is +; CHECK: tlbi vmalls12e1is ; encoding: [0xdf,0x83,0x0c,0xd5] ;----------------------------------------------------------------------------- ; 5.8.5 Vector Arithmetic aliases @@ -726,8 +746,8 @@ foo: movi v2.2D, #0x000000000000ff ; CHECK: movi.16b v4, #0 ; encoding: [0x04,0xe4,0x00,0x4f] -; CHECK: movi.16b v4, #1 ; encoding: [0x24,0xe4,0x00,0x4f] -; CHECK: movi.8b v4, #2 ; encoding: [0x44,0xe4,0x00,0x0f] -; CHECK: movi.8b v4, #3 ; encoding: [0x64,0xe4,0x00,0x0f] +; CHECK: movi.16b v4, #0x1 ; encoding: [0x24,0xe4,0x00,0x4f] +; CHECK: movi.8b v4, #0x2 ; encoding: [0x44,0xe4,0x00,0x0f] +; CHECK: movi.8b v4, #0x3 ; encoding: [0x64,0xe4,0x00,0x0f] ; CHECK: movi.2d v1, #0x000000000000ff ; encoding: [0x21,0xe4,0x00,0x6f] ; CHECK: movi.2d v2, #0x000000000000ff ; encoding: [0x22,0xe4,0x00,0x6f] diff --git a/test/MC/ARM64/arithmetic-encoding.s b/test/MC/AArch64/arm64-arithmetic-encoding.s index 7c89244..5fd5912 100644 --- a/test/MC/ARM64/arithmetic-encoding.s +++ b/test/MC/AArch64/arm64-arithmetic-encoding.s @@ -1,4 +1,4 @@ -; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s +; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon -show-encoding < %s | FileCheck %s foo: ;==---------------------------------------------------------------------------== @@ -47,11 +47,11 @@ foo: add x3, x4, #0, lsl #12 add sp, sp, #32 -; CHECK: add w3, w4, #4194304 ; encoding: [0x83,0x00,0x50,0x11] -; CHECK: add w3, w4, #4194304 ; encoding: [0x83,0x00,0x50,0x11] +; CHECK: add w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x11] +; CHECK: add w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x11] ; CHECK: add w3, w4, #0, lsl #12 ; encoding: [0x83,0x00,0x40,0x11] -; CHECK: add x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0x91] -; CHECK: add x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0x91] +; CHECK: add x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x91] +; CHECK: add x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x91] ; CHECK: add x3, x4, #0, lsl #12 ; encoding: [0x83,0x00,0x40,0x91] ; CHECK: add sp, sp, #32 ; encoding: [0xff,0x83,0x00,0x91] @@ -64,10 +64,10 @@ foo: ; CHECK: adds w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x31] ; CHECK: adds w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x31] -; CHECK: adds w3, w4, #4194304 ; encoding: [0x83,0x00,0x50,0x31] +; CHECK: adds w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x31] ; CHECK: adds x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xb1] ; CHECK: adds x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xb1] -; CHECK: adds x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0xb1] +; CHECK: adds x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xb1] sub w3, w4, #1024 sub w3, w4, #1024, lsl #0 @@ -79,10 +79,10 @@ foo: ; CHECK: sub w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x51] ; CHECK: sub w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x51] -; CHECK: sub w3, w4, #4194304 ; encoding: [0x83,0x00,0x50,0x51] +; CHECK: sub w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x51] ; CHECK: sub x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xd1] ; CHECK: sub x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xd1] -; CHECK: sub x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0xd1] +; CHECK: sub x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xd1] ; CHECK: sub sp, sp, #32 ; encoding: [0xff,0x83,0x00,0xd1] subs w3, w4, #1024 @@ -94,10 +94,10 @@ foo: ; CHECK: subs w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x71] ; CHECK: subs w3, w4, #1024 ; encoding: [0x83,0x00,0x10,0x71] -; CHECK: subs w3, w4, #4194304 ; encoding: [0x83,0x00,0x50,0x71] +; CHECK: subs w3, w4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0x71] ; CHECK: subs x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xf1] ; CHECK: subs x3, x4, #1024 ; encoding: [0x83,0x00,0x10,0xf1] -; CHECK: subs x3, x4, #4194304 ; encoding: [0x83,0x00,0x50,0xf1] +; CHECK: subs x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xf1] ;==---------------------------------------------------------------------------== ; Add/Subtract register with (optional) shift @@ -107,72 +107,56 @@ foo: add x12, x13, x14 add w12, w13, w14, lsl #12 add x12, x13, x14, lsl #12 - add w12, w13, w14, lsr #42 add x12, x13, x14, lsr #42 - add w12, w13, w14, asr #39 add x12, x13, x14, asr #39 ; CHECK: add w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x0b] ; CHECK: add x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0x8b] ; CHECK: add w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x0b] ; CHECK: add x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x8b] -; CHECK: add w12, w13, w14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0x0b] ; CHECK: add x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0x8b] -; CHECK: add w12, w13, w14, asr #39 ; encoding: [0xac,0x9d,0x8e,0x0b] ; CHECK: add x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0x8b] sub w12, w13, w14 sub x12, x13, x14 sub w12, w13, w14, lsl #12 sub x12, x13, x14, lsl #12 - sub w12, w13, w14, lsr #42 sub x12, x13, x14, lsr #42 - sub w12, w13, w14, asr #39 sub x12, x13, x14, asr #39 ; CHECK: sub w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x4b] ; CHECK: sub x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0xcb] ; CHECK: sub w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x4b] ; CHECK: sub x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0xcb] -; CHECK: sub w12, w13, w14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0x4b] ; CHECK: sub x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0xcb] -; CHECK: sub w12, w13, w14, asr #39 ; encoding: [0xac,0x9d,0x8e,0x4b] ; CHECK: sub x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0xcb] adds w12, w13, w14 adds x12, x13, x14 adds w12, w13, w14, lsl #12 adds x12, x13, x14, lsl #12 - adds w12, w13, w14, lsr #42 adds x12, x13, x14, lsr #42 - adds w12, w13, w14, asr #39 adds x12, x13, x14, asr #39 ; CHECK: adds w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x2b] ; CHECK: adds x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0xab] ; CHECK: adds w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x2b] ; CHECK: adds x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0xab] -; CHECK: adds w12, w13, w14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0x2b] ; CHECK: adds x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0xab] -; CHECK: adds w12, w13, w14, asr #39 ; encoding: [0xac,0x9d,0x8e,0x2b] ; CHECK: adds x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0xab] subs w12, w13, w14 subs x12, x13, x14 subs w12, w13, w14, lsl #12 subs x12, x13, x14, lsl #12 - subs w12, w13, w14, lsr #42 subs x12, x13, x14, lsr #42 - subs w12, w13, w14, asr #39 subs x12, x13, x14, asr #39 ; CHECK: subs w12, w13, w14 ; encoding: [0xac,0x01,0x0e,0x6b] ; CHECK: subs x12, x13, x14 ; encoding: [0xac,0x01,0x0e,0xeb] ; CHECK: subs w12, w13, w14, lsl #12 ; encoding: [0xac,0x31,0x0e,0x6b] ; CHECK: subs x12, x13, x14, lsl #12 ; encoding: [0xac,0x31,0x0e,0xeb] -; CHECK: subs w12, w13, w14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0x6b] ; CHECK: subs x12, x13, x14, lsr #42 ; encoding: [0xac,0xa9,0x4e,0xeb] -; CHECK: subs w12, w13, w14, asr #39 ; encoding: [0xac,0x9d,0x8e,0x6b] ; CHECK: subs x12, x13, x14, asr #39 ; encoding: [0xac,0x9d,0x8e,0xeb] ; Check use of upper case register names rdar://14354073 @@ -223,7 +207,7 @@ foo: ; CHECK: add w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x0b] ; CHECK: add w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x0b] -; CHECK: add w2, wsp, w3, lsl #1 ; encoding: [0xe2,0x67,0x23,0x0b] +; CHECK: add w2, wsp, w3, lsl #1 ; encoding: [0xe2,0x47,0x23,0x0b] ; CHECK: add sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0x8b] ; CHECK: add sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0x8b] @@ -313,7 +297,7 @@ foo: ; CHECK: adds w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x2b] ; CHECK: adds w1, wsp, w3 ; encoding: [0xe1,0x43,0x23,0x2b] -; CHECK: adds wzr, wsp, w3, lsl #4 ; encoding: [0xff,0x73,0x23,0x2b] +; CHECK: cmn wsp, w3, lsl #4 ; encoding: [0xff,0x53,0x23,0x2b] subs w1, w2, w3, uxtb subs w1, w2, w3, uxth @@ -364,12 +348,12 @@ foo: cmp sp, w8, uxtw subs xzr, sp, w8, uxtw -; CHECK: cmp wsp, w9 ; encoding: [0xff,0x63,0x29,0x6b] +; CHECK: cmp wsp, w9 ; encoding: [0xff,0x43,0x29,0x6b] ; CHECK: subs x3, sp, x9, lsl #2 ; encoding: [0xe3,0x6b,0x29,0xeb] ; CHECK: cmp wsp, w8 ; encoding: [0xff,0x43,0x28,0x6b] ; CHECK: cmp wsp, w8 ; encoding: [0xff,0x43,0x28,0x6b] -; CHECK: cmp sp, w8 ; encoding: [0xff,0x43,0x28,0xeb] -; CHECK: cmp sp, w8 ; encoding: [0xff,0x43,0x28,0xeb] +; CHECK: cmp sp, w8, uxtw ; encoding: [0xff,0x43,0x28,0xeb] +; CHECK: cmp sp, w8, uxtw ; encoding: [0xff,0x43,0x28,0xeb] sub wsp, w9, w8, uxtw sub w1, wsp, w8, uxtw @@ -383,11 +367,11 @@ foo: ; CHECK: sub wsp, w9, w8 ; encoding: [0x3f,0x41,0x28,0x4b] ; CHECK: sub w1, wsp, w8 ; encoding: [0xe1,0x43,0x28,0x4b] ; CHECK: sub wsp, wsp, w8 ; encoding: [0xff,0x43,0x28,0x4b] -; CHECK: sub sp, x9, w8 ; encoding: [0x3f,0x41,0x28,0xcb] -; CHECK: sub x1, sp, w8 ; encoding: [0xe1,0x43,0x28,0xcb] -; CHECK: sub sp, sp, w8 ; encoding: [0xff,0x43,0x28,0xcb] +; CHECK: sub sp, x9, w8, uxtw ; encoding: [0x3f,0x41,0x28,0xcb] +; CHECK: sub x1, sp, w8, uxtw ; encoding: [0xe1,0x43,0x28,0xcb] +; CHECK: sub sp, sp, w8, uxtw ; encoding: [0xff,0x43,0x28,0xcb] ; CHECK: subs w1, wsp, w8 ; encoding: [0xe1,0x43,0x28,0x6b] -; CHECK: subs x1, sp, w8 ; encoding: [0xe1,0x43,0x28,0xeb] +; CHECK: subs x1, sp, w8, uxtw ; encoding: [0xe1,0x43,0x28,0xeb] ;==---------------------------------------------------------------------------== ; Signed/Unsigned divide @@ -510,30 +494,30 @@ foo: movz w0, #1, lsl #16 movz x0, #1, lsl #16 -; CHECK: movz w0, #1 ; encoding: [0x20,0x00,0x80,0x52] -; CHECK: movz x0, #1 ; encoding: [0x20,0x00,0x80,0xd2] -; CHECK: movz w0, #1, lsl #16 ; encoding: [0x20,0x00,0xa0,0x52] -; CHECK: movz x0, #1, lsl #16 ; encoding: [0x20,0x00,0xa0,0xd2] +; CHECK: movz w0, #0x1 ; encoding: [0x20,0x00,0x80,0x52] +; CHECK: movz x0, #0x1 ; encoding: [0x20,0x00,0x80,0xd2] +; CHECK: movz w0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0x52] +; CHECK: movz x0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0xd2] movn w0, #2 movn x0, #2 movn w0, #2, lsl #16 movn x0, #2, lsl #16 -; CHECK: movn w0, #2 ; encoding: [0x40,0x00,0x80,0x12] -; CHECK: movn x0, #2 ; encoding: [0x40,0x00,0x80,0x92] -; CHECK: movn w0, #2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x12] -; CHECK: movn x0, #2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x92] +; CHECK: movn w0, #0x2 ; encoding: [0x40,0x00,0x80,0x12] +; CHECK: movn x0, #0x2 ; encoding: [0x40,0x00,0x80,0x92] +; CHECK: movn w0, #0x2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x12] +; CHECK: movn x0, #0x2, lsl #16 ; encoding: [0x40,0x00,0xa0,0x92] movk w0, #1 movk x0, #1 movk w0, #1, lsl #16 movk x0, #1, lsl #16 -; CHECK: movk w0, #1 ; encoding: [0x20,0x00,0x80,0x72] -; CHECK: movk x0, #1 ; encoding: [0x20,0x00,0x80,0xf2] -; CHECK: movk w0, #1, lsl #16 ; encoding: [0x20,0x00,0xa0,0x72] -; CHECK: movk x0, #1, lsl #16 ; encoding: [0x20,0x00,0xa0,0xf2] +; CHECK: movk w0, #0x1 ; encoding: [0x20,0x00,0x80,0x72] +; CHECK: movk x0, #0x1 ; encoding: [0x20,0x00,0x80,0xf2] +; CHECK: movk w0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0x72] +; CHECK: movk x0, #0x1, lsl #16 ; encoding: [0x20,0x00,0xa0,0xf2] ;==---------------------------------------------------------------------------== ; Conditionally set flags instructions @@ -602,10 +586,10 @@ foo: ; CHECK: csel w16, w7, w27, eq ; encoding: [0xf0,0x00,0x9b,0x1a] ; CHECK: csel w15, w6, w26, ne ; encoding: [0xcf,0x10,0x9a,0x1a] -; CHECK: csel w14, w5, w25, cs ; encoding: [0xae,0x20,0x99,0x1a] -; CHECK: csel w13, w4, w24, cs ; encoding: [0x8d,0x20,0x98,0x1a] -; CHECK: csel w12, w3, w23, cc ; encoding: [0x6c,0x30,0x97,0x1a] -; CHECK: csel w11, w2, w22, cc ; encoding: [0x4b,0x30,0x96,0x1a] +; CHECK: csel w14, w5, w25, hs ; encoding: [0xae,0x20,0x99,0x1a] +; CHECK: csel w13, w4, w24, hs ; encoding: [0x8d,0x20,0x98,0x1a] +; CHECK: csel w12, w3, w23, lo ; encoding: [0x6c,0x30,0x97,0x1a] +; CHECK: csel w11, w2, w22, lo ; encoding: [0x4b,0x30,0x96,0x1a] ; CHECK: csel w10, w1, w21, mi ; encoding: [0x2a,0x40,0x95,0x1a] ; CHECK: csel x9, x9, x1, pl ; encoding: [0x29,0x51,0x81,0x9a] ; CHECK: csel x8, x8, x2, vs ; encoding: [0x08,0x61,0x82,0x9a] diff --git a/test/MC/ARM64/arm64-fixup.s b/test/MC/AArch64/arm64-arm64-fixup.s index eae6f68..81306fb 100644 --- a/test/MC/ARM64/arm64-fixup.s +++ b/test/MC/AArch64/arm64-arm64-fixup.s @@ -3,8 +3,8 @@ foo: adr x3, Lbar ; CHECK: adr x3, Lbar ; encoding: [0x03'A',A,A,0x10'A'] -; CHECK: fixup A - offset: 0, value: Lbar, kind: fixup_arm64_pcrel_adr_imm21 +; CHECK: fixup A - offset: 0, value: Lbar, kind: fixup_aarch64_pcrel_adr_imm21 Lbar: adrp x3, _printf@page ; CHECK: adrp x3, _printf@PAGE ; encoding: [0x03'A',A,A,0x90'A'] -; CHECK: fixup A - offset: 0, value: _printf@PAGE, kind: fixup_arm64_pcrel_adrp_imm21 +; CHECK: fixup A - offset: 0, value: _printf@PAGE, kind: fixup_aarch64_pcrel_adrp_imm21 diff --git a/test/MC/ARM64/basic-a64-instructions.s b/test/MC/AArch64/arm64-basic-a64-instructions.s index 99b438d..2f58ead 100644 --- a/test/MC/ARM64/basic-a64-instructions.s +++ b/test/MC/AArch64/arm64-basic-a64-instructions.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple arm64 -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple arm64 -mattr=+crc -show-encoding < %s | FileCheck %s crc32b w5, w7, w20 crc32h w28, wzr, w30 diff --git a/test/MC/AArch64/arm64-be-datalayout.s b/test/MC/AArch64/arm64-be-datalayout.s new file mode 100644 index 0000000..f448a4b --- /dev/null +++ b/test/MC/AArch64/arm64-be-datalayout.s @@ -0,0 +1,4 @@ +// RUN: llvm-mc -filetype=obj -triple arm64_be %s | llvm-readobj -section-data -sections | FileCheck %s + +// CHECK: 0000: 00123456 789ABCDE +foo: .xword 0x123456789abcde diff --git a/test/MC/ARM64/bitfield-encoding.s b/test/MC/AArch64/arm64-bitfield-encoding.s index cdbac08..1589aa7 100644 --- a/test/MC/ARM64/bitfield-encoding.s +++ b/test/MC/AArch64/arm64-bitfield-encoding.s @@ -11,13 +11,21 @@ foo: sbfm x1, x2, #1, #15 ubfm w1, w2, #1, #15 ubfm x1, x2, #1, #15 + sbfiz wzr, w0, #31, #1 + sbfiz xzr, x0, #31, #1 + ubfiz wzr, w0, #31, #1 + ubfiz xzr, x0, #31, #1 -; CHECK: bfm w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x33] -; CHECK: bfm x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0xb3] -; CHECK: sbfm w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x13] -; CHECK: sbfm x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0x93] -; CHECK: ubfm w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x53] -; CHECK: ubfm x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0xd3] +; CHECK: bfxil w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x33] +; CHECK: bfxil x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0xb3] +; CHECK: sbfx w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x13] +; CHECK: sbfx x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0x93] +; CHECK: ubfx w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x53] +; CHECK: ubfx x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0xd3] +; CHECK: sbfiz wzr, w0, #31, #1 ; encoding: [0x1f,0x00,0x01,0x13] +; CHECK: sbfiz xzr, x0, #31, #1 ; encoding: [0x1f,0x00,0x61,0x93] +; CHECK: lsl wzr, w0, #31 ; encoding: [0x1f,0x00,0x01,0x53] +; CHECK: ubfiz xzr, x0, #31, #1 ; encoding: [0x1f,0x00,0x61,0xd3] ;==---------------------------------------------------------------------------== ; 5.4.5 Extract (immediate) diff --git a/test/MC/ARM64/branch-encoding.s b/test/MC/AArch64/arm64-branch-encoding.s index 7857fea..48c2099 100644 --- a/test/MC/ARM64/branch-encoding.s +++ b/test/MC/AArch64/arm64-branch-encoding.s @@ -20,7 +20,7 @@ foo: ; CHECK: encoding: [0x20,0x01,0x3f,0xd6] bl L1 ; CHECK: bl L1 ; encoding: [A,A,A,0b100101AA] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_call26 +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_call26 ;----------------------------------------------------------------------------- ; Contitional branch instructions. @@ -28,59 +28,59 @@ foo: b L1 ; CHECK: b L1 ; encoding: [A,A,A,0b000101AA] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_branch26 +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch26 b.eq L1 ; CHECK: b.eq L1 ; encoding: [0bAAA00000,A,A,0x54] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19 +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 b.ne L1 ; CHECK: b.ne L1 ; encoding: [0bAAA00001,A,A,0x54] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19 +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 b.cs L1 -; CHECK: b.cs L1 ; encoding: [0bAAA00010,A,A,0x54] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19 +; CHECK: b.hs L1 ; encoding: [0bAAA00010,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 b.cc L1 -; CHECK: b.cc L1 ; encoding: [0bAAA00011,A,A,0x54] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19 +; CHECK: b.lo L1 ; encoding: [0bAAA00011,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 b.mi L1 ; CHECK: b.mi L1 ; encoding: [0bAAA00100,A,A,0x54] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19 +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 b.pl L1 ; CHECK: b.pl L1 ; encoding: [0bAAA00101,A,A,0x54] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19 +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 b.vs L1 ; CHECK: b.vs L1 ; encoding: [0bAAA00110,A,A,0x54] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19 +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 b.vc L1 ; CHECK: b.vc L1 ; encoding: [0bAAA00111,A,A,0x54] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19 +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 b.hi L1 ; CHECK: b.hi L1 ; encoding: [0bAAA01000,A,A,0x54] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19 +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 b.ls L1 ; CHECK: b.ls L1 ; encoding: [0bAAA01001,A,A,0x54] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19 +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 b.ge L1 ; CHECK: b.ge L1 ; encoding: [0bAAA01010,A,A,0x54] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19 +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 b.lt L1 ; CHECK: b.lt L1 ; encoding: [0bAAA01011,A,A,0x54] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19 +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 b.gt L1 ; CHECK: b.gt L1 ; encoding: [0bAAA01100,A,A,0x54] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19 +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 b.le L1 ; CHECK: b.le L1 ; encoding: [0bAAA01101,A,A,0x54] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19 +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 b.al L1 -; CHECK: b L1 ; encoding: [0bAAA01110,A,A,0x54] -; CHECK: fixup A - offset: 0, value: L1, kind: fixup_arm64_pcrel_imm19 +; CHECK: b.al L1 ; encoding: [0bAAA01110,A,A,0x54] +; CHECK: fixup A - offset: 0, value: L1, kind: fixup_aarch64_pcrel_branch19 L1: b #28 ; CHECK: b #28 b.lt #28 ; CHECK: b.lt #28 b.cc #1048572 -; CHECK: b.cc #1048572 ; encoding: [0xe3,0xff,0x7f,0x54] +; CHECK: b.lo #1048572 ; encoding: [0xe3,0xff,0x7f,0x54] b #134217724 ; CHECK: b #134217724 ; encoding: [0xff,0xff,0xff,0x15] b #-134217728 diff --git a/test/MC/AArch64/arm64-condbr-without-dots.s b/test/MC/AArch64/arm64-condbr-without-dots.s new file mode 100644 index 0000000..2a9f7a7 --- /dev/null +++ b/test/MC/AArch64/arm64-condbr-without-dots.s @@ -0,0 +1,37 @@ +// RUN: llvm-mc -triple arm64-apple-ios -o - %s | FileCheck %s + + beq lbl + bne lbl + bcs lbl + bhs lbl + blo lbl + bcc lbl + bmi lbl + bpl lbl + bvs lbl + bvc lbl + bhi lbl + bls lbl + bge lbl + blt lbl + bgt lbl + ble lbl + bal lbl + +// CHECK: b.eq lbl +// CHECK: b.ne lbl +// CHECK: b.hs lbl +// CHECK: b.hs lbl +// CHECK: b.lo lbl +// CHECK: b.lo lbl +// CHECK: b.mi lbl +// CHECK: b.pl lbl +// CHECK: b.vs lbl +// CHECK: b.vc lbl +// CHECK: b.hi lbl +// CHECK: b.ls lbl +// CHECK: b.ge lbl +// CHECK: b.lt lbl +// CHECK: b.gt lbl +// CHECK: b.le lbl +// CHECK: b.al lbl diff --git a/test/MC/ARM64/crypto.s b/test/MC/AArch64/arm64-crypto.s index d7c4ec3..51efd21 100644 --- a/test/MC/ARM64/crypto.s +++ b/test/MC/AArch64/arm64-crypto.s @@ -1,4 +1,4 @@ -; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding -output-asm-variant=1 < %s | FileCheck %s +; RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -show-encoding -output-asm-variant=1 < %s | FileCheck %s foo: aese.16b v0, v1 diff --git a/test/MC/AArch64/arm64-diagno-predicate.s b/test/MC/AArch64/arm64-diagno-predicate.s new file mode 100644 index 0000000..3b757e8 --- /dev/null +++ b/test/MC/AArch64/arm64-diagno-predicate.s @@ -0,0 +1,24 @@ +// RUN: not llvm-mc -triple arm64-linux-gnu -mattr=-fp-armv8,-crc < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s + + + fcvt d0, s0 +// CHECK-ERROR: error: instruction requires: fp-armv8 +// CHECK-ERROR-NEXT: fcvt d0, s0 +// CHECK-ERROR-NEXT: ^ + + fmla v9.2s, v9.2s, v0.2s +// CHECK-ERROR: error: instruction requires: neon +// CHECK-ERROR-NEXT: fmla v9.2s, v9.2s, v0.2s +// CHECK-ERROR-NEXT: ^ + + pmull v0.1q, v1.1d, v2.1d +// CHECK-ERROR: error: instruction requires: crypto +// CHECK-ERROR-NEXT: pmull v0.1q, v1.1d, v2.1d +// CHECK-ERROR-NEXT: ^ + + crc32b w5, w7, w20 +// CHECK-ERROR: error: instruction requires: crc +// CHECK-ERROR-NEXT: crc32b w5, w7, w20 +// CHECK-ERROR-NEXT: ^ + diff --git a/test/MC/ARM64/diags.s b/test/MC/AArch64/arm64-diags.s index d857fe1..cf00e98 100644 --- a/test/MC/ARM64/diags.s +++ b/test/MC/AArch64/arm64-diags.s @@ -8,8 +8,8 @@ foo: ldr x3, (foo + 4) ldr x3, [foo + 4] ; CHECK: ldr x3, foo+4 ; encoding: [0bAAA00011,A,A,0x58] -; CHECK: ; fixup A - offset: 0, value: foo+4, kind: fixup_arm64_pcrel_imm19 -; CHECK-ERRORS: error: register expected +; CHECK: ; fixup A - offset: 0, value: foo+4, kind: fixup_aarch64_ldr_pcrel_imm19 +; CHECK-ERRORS: error: invalid operand for instruction ; The last argument should be flagged as an error. rdar://9576009 ld4.8b {v0, v1, v2, v3}, [x0], #33 @@ -33,47 +33,97 @@ foo: ldur x0, [x1, #-257] -; CHECK-ERRORS: error: index must be a multiple of 8 in range [0,32760]. +; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. ; CHECK-ERRORS: ldr x0, [x0, #804] ; CHECK-ERRORS: ^ -; CHECK-ERRORS: error: index must be a multiple of 4 in range [0,16380]. +; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. ; CHECK-ERRORS: ldr w0, [x0, #802] ; CHECK-ERRORS: ^ -; CHECK-ERRORS: error: index must be an integer in range [-256,255]. +; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. ; CHECK-ERRORS: ldr x0, [x0, #804]! ; CHECK-ERRORS: ^ -; CHECK-ERRORS: error: index must be an integer in range [-256,255]. +; CHECK-ERRORS: error: invalid operand for instruction ; CHECK-ERRORS: ldr w0, [w0, #301]! -; CHECK-ERRORS: ^ -; CHECK-ERRORS: error: index must be an integer in range [-256,255]. +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. ; CHECK-ERRORS: ldr x0, [x0], #804 ; CHECK-ERRORS: ^ -; CHECK-ERRORS: error: index must be an integer in range [-256,255]. +; CHECK-ERRORS: error: invalid operand for instruction ; CHECK-ERRORS: ldr w0, [w0], #301 -; CHECK-ERRORS: ^ -; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256,252]. +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252]. ; CHECK-ERRORS: ldp w3, w4, [x5, #11]! ; CHECK-ERRORS: ^ -; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512,504]. +; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504]. ; CHECK-ERRORS: ldp x3, x4, [x5, #12]! ; CHECK-ERRORS: ^ -; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024,1008]. +; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008]. ; CHECK-ERRORS: ldp q3, q4, [x5, #12]! ; CHECK-ERRORS: ^ -; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256,252]. +; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252]. ; CHECK-ERRORS: ldp w3, w4, [x5], #11 ; CHECK-ERRORS: ^ -; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512,504]. +; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504]. ; CHECK-ERRORS: ldp x3, x4, [x5], #12 ; CHECK-ERRORS: ^ -; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512,504]. +; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008]. ; CHECK-ERRORS: ldp q3, q4, [x5], #12 ; CHECK-ERRORS: ^ -; CHECK-ERRORS: error: index must be an integer in range [-256,255]. +; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. ; CHECK-ERRORS: ldur x0, [x1, #-257] ; CHECK-ERRORS: ^ +ldrb w1, [x3, w3, sxtw #4] +ldrh w1, [x3, w3, sxtw #4] +ldr w1, [x3, w3, sxtw #4] +ldr x1, [x3, w3, sxtw #4] +ldr b1, [x3, w3, sxtw #4] +ldr h1, [x3, w3, sxtw #4] +ldr s1, [x3, w3, sxtw #4] +ldr d1, [x3, w3, sxtw #4] +ldr q1, [x3, w3, sxtw #1] + +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 +; CHECK-ERRORS:ldrb w1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1 +; CHECK-ERRORS:ldrh w1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2 +; CHECK-ERRORS:ldr w1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3 +; CHECK-ERRORS:ldr x1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 +; CHECK-ERRORS:ldr b1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1 +; CHECK-ERRORS:ldr h1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2 +; CHECK-ERRORS:ldr s1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3 +; CHECK-ERRORS:ldr d1, [x3, w3, sxtw #4] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4 +; CHECK-ERRORS:ldr q1, [x3, w3, sxtw #1] +; CHECK-ERRORS: ^ + +; Check that register offset addressing modes only accept 32-bit offset +; registers when using uxtw/sxtw extends. Everything else requires a 64-bit +; register. + str d1, [x3, w3, sxtx #3] + ldr s1, [x3, d3, sxtx #2] + +; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3 +; CHECK-ERRORS: str d1, [x3, w3, sxtx #3] +; CHECK-ERRORS: ^ +; CHECK-ERRORS: error: index must be an integer in range [-256, 255]. +; CHECK-ERRORS: ldr s1, [x3, d3, sxtx #2] +; CHECK-ERRORS: ^ ; Shift immediates range checking. sqrshrn b4, h9, #10 @@ -81,16 +131,16 @@ foo: sqrshrn v7.4h, v8.4s, #39 uqshrn2 v4.4s, v5.2d, #67 -; CHECK-ERRORS: error: immediate must be an integer in range [1,8]. +; CHECK-ERRORS: error: immediate must be an integer in range [1, 8]. ; CHECK-ERRORS: sqrshrn b4, h9, #10 ; CHECK-ERRORS: ^ -; CHECK-ERRORS: error: immediate must be an integer in range [1,8]. +; CHECK-ERRORS: error: immediate must be an integer in range [1, 8]. ; CHECK-ERRORS: rshrn v9.8b, v11.8h, #17 ; CHECK-ERRORS: ^ -; CHECK-ERRORS: error: immediate must be an integer in range [1,16]. +; CHECK-ERRORS: error: immediate must be an integer in range [1, 16]. ; CHECK-ERRORS: sqrshrn v7.4h, v8.4s, #39 ; CHECK-ERRORS: ^ -; CHECK-ERRORS: error: immediate must be an integer in range [1,32]. +; CHECK-ERRORS: error: immediate must be an integer in range [1, 32]. ; CHECK-ERRORS: uqshrn2 v4.4s, v5.2d, #67 ; CHECK-ERRORS: ^ @@ -164,25 +214,25 @@ foo: ; Where the immediate is out of range. add w1, w2, w3, lsr #75 -; CHECK-ERRORS: error: immediate value too large for shifter operand +; CHECK-ERRORS: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4] ; CHECK-ERRORS: add w1, w2, w3, lsr #75 ; CHECK-ERRORS: ^ ; logical instructions on 32-bit regs with shift > 31 is not legal orr w0, w0, w0, lsl #32 -; CHECK-ERRORS: error: shift value out of range +; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31] ; CHECK-ERRORS: orr w0, w0, w0, lsl #32 ; CHECK-ERRORS: ^ eor w0, w0, w0, lsl #32 -; CHECK-ERRORS: error: shift value out of range +; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31] ; CHECK-ERRORS: eor w0, w0, w0, lsl #32 ; CHECK-ERRORS: ^ and w0, w0, w0, lsl #32 -; CHECK-ERRORS: error: shift value out of range +; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31] ; CHECK-ERRORS: and w0, w0, w0, lsl #32 ; CHECK-ERRORS: ^ ands w0, w0, w0, lsl #32 -; CHECK-ERRORS: error: shift value out of range +; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31] ; CHECK-ERRORS: ands w0, w0, w0, lsl #32 ; CHECK-ERRORS: ^ @@ -240,3 +290,103 @@ b.c #0x4 ; CHECK-ERRORS: error: invalid condition code ; CHECK-ERRORS: b.c #0x4 ; CHECK-ERRORS: ^ + +ic ialluis, x0 +; CHECK-ERRORS: error: specified ic op does not use a register +ic iallu, x0 +; CHECK-ERRORS: error: specified ic op does not use a register +ic ivau +; CHECK-ERRORS: error: specified ic op requires a register + +dc zva +; CHECK-ERRORS: error: specified dc op requires a register +dc ivac +; CHECK-ERRORS: error: specified dc op requires a register +dc isw +; CHECK-ERRORS: error: specified dc op requires a register +dc cvac +; CHECK-ERRORS: error: specified dc op requires a register +dc csw +; CHECK-ERRORS: error: specified dc op requires a register +dc cvau +; CHECK-ERRORS: error: specified dc op requires a register +dc civac +; CHECK-ERRORS: error: specified dc op requires a register +dc cisw +; CHECK-ERRORS: error: specified dc op requires a register + +at s1e1r +; CHECK-ERRORS: error: specified at op requires a register +at s1e2r +; CHECK-ERRORS: error: specified at op requires a register +at s1e3r +; CHECK-ERRORS: error: specified at op requires a register +at s1e1w +; CHECK-ERRORS: error: specified at op requires a register +at s1e2w +; CHECK-ERRORS: error: specified at op requires a register +at s1e3w +; CHECK-ERRORS: error: specified at op requires a register +at s1e0r +; CHECK-ERRORS: error: specified at op requires a register +at s1e0w +; CHECK-ERRORS: error: specified at op requires a register +at s12e1r +; CHECK-ERRORS: error: specified at op requires a register +at s12e1w +; CHECK-ERRORS: error: specified at op requires a register +at s12e0r +; CHECK-ERRORS: error: specified at op requires a register +at s12e0w +; CHECK-ERRORS: error: specified at op requires a register + +tlbi vmalle1is, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi vmalle1, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi alle1is, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi alle2is, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi alle3is, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi alle1, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi alle2, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi alle3, x0 +; CHECK-ERRORS: error: specified tlbi op does not use a register +tlbi vae1is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vae2is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vae3is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi aside1is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vaae1is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vale1is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vaale1is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vale2is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vale3is +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vae1 +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vae2 +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vae3 +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi aside1 +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vaae1 +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vale1 +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vale2 +; CHECK-ERRORS: error: specified tlbi op requires a register +tlbi vale3 +; CHECK-ERRORS: error: specified tlbi op requires a register diff --git a/test/MC/ARM64/directive_loh.s b/test/MC/AArch64/arm64-directive_loh.s index 76d2d7f..76d2d7f 100644 --- a/test/MC/ARM64/directive_loh.s +++ b/test/MC/AArch64/arm64-directive_loh.s diff --git a/test/MC/AArch64/elf-reloc-condbr.s b/test/MC/AArch64/arm64-elf-reloc-condbr.s index b70dfa7..9b70a20 100644 --- a/test/MC/AArch64/elf-reloc-condbr.s +++ b/test/MC/AArch64/arm64-elf-reloc-condbr.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ +// RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj %s -o - | \ // RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s b.eq somewhere diff --git a/test/MC/ARM64/elf-relocs.s b/test/MC/AArch64/arm64-elf-relocs.s index 31446ff..eb22cc2 100644 --- a/test/MC/ARM64/elf-relocs.s +++ b/test/MC/AArch64/arm64-elf-relocs.s @@ -14,7 +14,7 @@ // CHECK-OBJ: 8 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym add x20, x30, #:tprel_lo12:sym -// CHECK: add x20, lr, :tprel_lo12:sym +// CHECK: add x20, x30, :tprel_lo12:sym // CHECK-OBJ: c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym add x9, x12, #:tprel_lo12_nc:sym @@ -38,7 +38,7 @@ // CHECK-OBJ:20 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2 add x20, x30, #:tprel_lo12:sym+12 -// CHECK: add x20, lr, :tprel_lo12:sym+12 +// CHECK: add x20, x30, :tprel_lo12:sym+12 // CHECK-OBJ: 24 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12 add x9, x12, #:tprel_lo12_nc:sym+54 @@ -72,7 +72,7 @@ // CHECK-OBJ: 50 R_AARCH64_ADR_GOT_PAGE sym adrp x29, :gottprel:sym -// CHECK: adrp fp, :gottprel:sym +// CHECK: adrp x29, :gottprel:sym // CHECK-OBJ: 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym adrp x2, :tlsdesc:sym @@ -88,9 +88,9 @@ trickQuestion: // CHECK: adrp x3, trickQuestion // CHECK-OBJ: 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion - ldrb w2, [x3, #:lo12:sym] + ldrb w2, [x3, :lo12:sym] ldrsb w5, [x7, #:lo12:sym] - ldrsb x11, [x13, #:lo12:sym] + ldrsb x11, [x13, :lo12:sym] ldr b17, [x19, #:lo12:sym] // CHECK: ldrb w2, [x3, :lo12:sym] // CHECK: ldrsb w5, [x7, :lo12:sym] @@ -103,9 +103,9 @@ trickQuestion: ldrb w23, [x29, #:dtprel_lo12_nc:sym] ldrsb w23, [x19, #:dtprel_lo12:sym] - ldrsb x17, [x13, #:dtprel_lo12_nc:sym] + ldrsb x17, [x13, :dtprel_lo12_nc:sym] ldr b11, [x7, #:dtprel_lo12:sym] -// CHECK: ldrb w23, [fp, :dtprel_lo12_nc:sym] +// CHECK: ldrb w23, [x29, :dtprel_lo12_nc:sym] // CHECK: ldrsb w23, [x19, :dtprel_lo12:sym] // CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym] // CHECK: ldr b11, [x7, :dtprel_lo12:sym] @@ -114,9 +114,9 @@ trickQuestion: // CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym // CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym - ldrb w1, [x2, #:tprel_lo12:sym] + ldrb w1, [x2, :tprel_lo12:sym] ldrsb w3, [x4, #:tprel_lo12_nc:sym] - ldrsb x5, [x6, #:tprel_lo12:sym] + ldrsb x5, [x6, :tprel_lo12:sym] ldr b7, [x8, #:tprel_lo12_nc:sym] // CHECK: ldrb w1, [x2, :tprel_lo12:sym] // CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym] @@ -128,9 +128,9 @@ trickQuestion: // CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym ldrh w2, [x3, #:lo12:sym] - ldrsh w5, [x7, #:lo12:sym] + ldrsh w5, [x7, :lo12:sym] ldrsh x11, [x13, #:lo12:sym] - ldr h17, [x19, #:lo12:sym] + ldr h17, [x19, :lo12:sym] // CHECK: ldrh w2, [x3, :lo12:sym] // CHECK: ldrsh w5, [x7, :lo12:sym] // CHECK: ldrsh x11, [x13, :lo12:sym] @@ -141,10 +141,10 @@ trickQuestion: // CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym ldrh w23, [x29, #:dtprel_lo12_nc:sym] - ldrsh w23, [x19, #:dtprel_lo12:sym] - ldrsh x17, [x13, #:dtprel_lo12_nc:sym] + ldrsh w23, [x19, :dtprel_lo12:sym] + ldrsh x17, [x13, :dtprel_lo12_nc:sym] ldr h11, [x7, #:dtprel_lo12:sym] -// CHECK: ldrh w23, [fp, :dtprel_lo12_nc:sym] +// CHECK: ldrh w23, [x29, :dtprel_lo12_nc:sym] // CHECK: ldrsh w23, [x19, :dtprel_lo12:sym] // CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym] // CHECK: ldr h11, [x7, :dtprel_lo12:sym] @@ -153,9 +153,9 @@ trickQuestion: // CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym // CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym - ldrh w1, [x2, #:tprel_lo12:sym] + ldrh w1, [x2, :tprel_lo12:sym] ldrsh w3, [x4, #:tprel_lo12_nc:sym] - ldrsh x5, [x6, #:tprel_lo12:sym] + ldrsh x5, [x6, :tprel_lo12:sym] ldr h7, [x8, #:tprel_lo12_nc:sym] // CHECK: ldrh w1, [x2, :tprel_lo12:sym] // CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym] @@ -168,7 +168,7 @@ trickQuestion: ldr w1, [x2, #:lo12:sym] ldrsw x3, [x4, #:lo12:sym] - ldr s4, [x5, #:lo12:sym] + ldr s4, [x5, :lo12:sym] // CHECK: ldr w1, [x2, :lo12:sym] // CHECK: ldrsw x3, [x4, :lo12:sym] // CHECK: ldr s4, [x5, :lo12:sym] @@ -176,7 +176,7 @@ trickQuestion: // CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym // CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym - ldr w1, [x2, #:dtprel_lo12:sym] + ldr w1, [x2, :dtprel_lo12:sym] ldrsw x3, [x4, #:dtprel_lo12_nc:sym] ldr s4, [x5, #:dtprel_lo12_nc:sym] // CHECK: ldr w1, [x2, :dtprel_lo12:sym] @@ -188,8 +188,8 @@ trickQuestion: ldr w1, [x2, #:tprel_lo12:sym] - ldrsw x3, [x4, #:tprel_lo12_nc:sym] - ldr s4, [x5, #:tprel_lo12_nc:sym] + ldrsw x3, [x4, :tprel_lo12_nc:sym] + ldr s4, [x5, :tprel_lo12_nc:sym] // CHECK: ldr w1, [x2, :tprel_lo12:sym] // CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym] // CHECK: ldr s4, [x5, :tprel_lo12_nc:sym] @@ -197,7 +197,7 @@ trickQuestion: // CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym // CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym - ldr x28, [x27, #:lo12:sym] + ldr x28, [x27, :lo12:sym] ldr d26, [x25, #:lo12:sym] // CHECK: ldr x28, [x27, :lo12:sym] // CHECK: ldr d26, [x25, :lo12:sym] @@ -205,13 +205,13 @@ trickQuestion: // CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym ldr x24, [x23, #:got_lo12:sym] - ldr d22, [x21, #:got_lo12:sym] + ldr d22, [x21, :got_lo12:sym] // CHECK: ldr x24, [x23, :got_lo12:sym] // CHECK: ldr d22, [x21, :got_lo12:sym] // CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym // CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym - ldr x24, [x23, #:dtprel_lo12_nc:sym] + ldr x24, [x23, :dtprel_lo12_nc:sym] ldr d22, [x21, #:dtprel_lo12:sym] // CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym] // CHECK: ldr d22, [x21, :dtprel_lo12:sym] @@ -219,13 +219,13 @@ trickQuestion: // CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12 sym ldr x24, [x23, #:tprel_lo12:sym] - ldr d22, [x21, #:tprel_lo12_nc:sym] + ldr d22, [x21, :tprel_lo12_nc:sym] // CHECK: ldr x24, [x23, :tprel_lo12:sym] // CHECK: ldr d22, [x21, :tprel_lo12_nc:sym] // CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12 sym // CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC sym - ldr x24, [x23, #:gottprel_lo12:sym] + ldr x24, [x23, :gottprel_lo12:sym] ldr d22, [x21, #:gottprel_lo12:sym] // CHECK: ldr x24, [x23, :gottprel_lo12:sym] // CHECK: ldr d22, [x21, :gottprel_lo12:sym] @@ -233,7 +233,7 @@ trickQuestion: // CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym ldr x24, [x23, #:tlsdesc_lo12:sym] - ldr d22, [x21, #:tlsdesc_lo12:sym] + ldr d22, [x21, :tlsdesc_lo12:sym] // CHECK: ldr x24, [x23, :tlsdesc_lo12:sym] // CHECK: ldr d22, [x21, :tlsdesc_lo12:sym] // CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym diff --git a/test/MC/ARM64/fp-encoding.s b/test/MC/AArch64/arm64-fp-encoding.s index 25474c1..684d988 100644 --- a/test/MC/ARM64/fp-encoding.s +++ b/test/MC/AArch64/arm64-fp-encoding.s @@ -1,4 +1,4 @@ -; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s +; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon -show-encoding -output-asm-variant=1 < %s | FileCheck %s foo: ;----------------------------------------------------------------------------- @@ -158,148 +158,84 @@ foo: ; CHECK: fcvt h1, s2 ; encoding: [0x41,0xc0,0x23,0x1e] fcvtas w1, d2 - fcvtas w1, d2, #1 fcvtas x1, d2 - fcvtas x1, d2, #1 fcvtas w1, s2 - fcvtas w1, s2, #1 fcvtas x1, s2 - fcvtas x1, s2, #1 ; CHECK: fcvtas w1, d2 ; encoding: [0x41,0x00,0x64,0x1e] -; CHECK: fcvtas w1, d2, #1 ; encoding: [0x41,0xfc,0x44,0x1e] ; CHECK: fcvtas x1, d2 ; encoding: [0x41,0x00,0x64,0x9e] -; CHECK: fcvtas x1, d2, #1 ; encoding: [0x41,0xfc,0x44,0x9e] ; CHECK: fcvtas w1, s2 ; encoding: [0x41,0x00,0x24,0x1e] -; CHECK: fcvtas w1, s2, #1 ; encoding: [0x41,0xfc,0x04,0x1e] ; CHECK: fcvtas x1, s2 ; encoding: [0x41,0x00,0x24,0x9e] -; CHECK: fcvtas x1, s2, #1 ; encoding: [0x41,0xfc,0x04,0x9e] fcvtau w1, s2 - fcvtau w1, s2, #1 fcvtau w1, d2 - fcvtau w1, d2, #1 fcvtau x1, s2 - fcvtau x1, s2, #1 fcvtau x1, d2 - fcvtau x1, d2, #1 ; CHECK: fcvtau w1, s2 ; encoding: [0x41,0x00,0x25,0x1e] -; CHECK: fcvtau w1, s2, #1 ; encoding: [0x41,0xfc,0x05,0x1e] ; CHECK: fcvtau w1, d2 ; encoding: [0x41,0x00,0x65,0x1e] -; CHECK: fcvtau w1, d2, #1 ; encoding: [0x41,0xfc,0x45,0x1e] ; CHECK: fcvtau x1, s2 ; encoding: [0x41,0x00,0x25,0x9e] -; CHECK: fcvtau x1, s2, #1 ; encoding: [0x41,0xfc,0x05,0x9e] ; CHECK: fcvtau x1, d2 ; encoding: [0x41,0x00,0x65,0x9e] -; CHECK: fcvtau x1, d2, #1 ; encoding: [0x41,0xfc,0x45,0x9e] fcvtms w1, s2 - fcvtms w1, s2, #1 fcvtms w1, d2 - fcvtms w1, d2, #1 fcvtms x1, s2 - fcvtms x1, s2, #1 fcvtms x1, d2 - fcvtms x1, d2, #1 ; CHECK: fcvtms w1, s2 ; encoding: [0x41,0x00,0x30,0x1e] -; CHECK: fcvtms w1, s2, #1 ; encoding: [0x41,0xfc,0x10,0x1e] ; CHECK: fcvtms w1, d2 ; encoding: [0x41,0x00,0x70,0x1e] -; CHECK: fcvtms w1, d2, #1 ; encoding: [0x41,0xfc,0x50,0x1e] ; CHECK: fcvtms x1, s2 ; encoding: [0x41,0x00,0x30,0x9e] -; CHECK: fcvtms x1, s2, #1 ; encoding: [0x41,0xfc,0x10,0x9e] ; CHECK: fcvtms x1, d2 ; encoding: [0x41,0x00,0x70,0x9e] -; CHECK: fcvtms x1, d2, #1 ; encoding: [0x41,0xfc,0x50,0x9e] fcvtmu w1, s2 - fcvtmu w1, s2, #1 fcvtmu w1, d2 - fcvtmu w1, d2, #1 fcvtmu x1, s2 - fcvtmu x1, s2, #1 fcvtmu x1, d2 - fcvtmu x1, d2, #1 ; CHECK: fcvtmu w1, s2 ; encoding: [0x41,0x00,0x31,0x1e] -; CHECK: fcvtmu w1, s2, #1 ; encoding: [0x41,0xfc,0x11,0x1e] ; CHECK: fcvtmu w1, d2 ; encoding: [0x41,0x00,0x71,0x1e] -; CHECK: fcvtmu w1, d2, #1 ; encoding: [0x41,0xfc,0x51,0x1e] ; CHECK: fcvtmu x1, s2 ; encoding: [0x41,0x00,0x31,0x9e] -; CHECK: fcvtmu x1, s2, #1 ; encoding: [0x41,0xfc,0x11,0x9e] ; CHECK: fcvtmu x1, d2 ; encoding: [0x41,0x00,0x71,0x9e] -; CHECK: fcvtmu x1, d2, #1 ; encoding: [0x41,0xfc,0x51,0x9e] fcvtns w1, s2 - fcvtns w1, s2, #1 fcvtns w1, d2 - fcvtns w1, d2, #1 fcvtns x1, s2 - fcvtns x1, s2, #1 fcvtns x1, d2 - fcvtns x1, d2, #1 ; CHECK: fcvtns w1, s2 ; encoding: [0x41,0x00,0x20,0x1e] -; CHECK: fcvtns w1, s2, #1 ; encoding: [0x41,0xfc,0x00,0x1e] ; CHECK: fcvtns w1, d2 ; encoding: [0x41,0x00,0x60,0x1e] -; CHECK: fcvtns w1, d2, #1 ; encoding: [0x41,0xfc,0x40,0x1e] ; CHECK: fcvtns x1, s2 ; encoding: [0x41,0x00,0x20,0x9e] -; CHECK: fcvtns x1, s2, #1 ; encoding: [0x41,0xfc,0x00,0x9e] ; CHECK: fcvtns x1, d2 ; encoding: [0x41,0x00,0x60,0x9e] -; CHECK: fcvtns x1, d2, #1 ; encoding: [0x41,0xfc,0x40,0x9e] fcvtnu w1, s2 - fcvtnu w1, s2, #1 fcvtnu w1, d2 - fcvtnu w1, d2, #1 fcvtnu x1, s2 - fcvtnu x1, s2, #1 fcvtnu x1, d2 - fcvtnu x1, d2, #1 ; CHECK: fcvtnu w1, s2 ; encoding: [0x41,0x00,0x21,0x1e] -; CHECK: fcvtnu w1, s2, #1 ; encoding: [0x41,0xfc,0x01,0x1e] ; CHECK: fcvtnu w1, d2 ; encoding: [0x41,0x00,0x61,0x1e] -; CHECK: fcvtnu w1, d2, #1 ; encoding: [0x41,0xfc,0x41,0x1e] ; CHECK: fcvtnu x1, s2 ; encoding: [0x41,0x00,0x21,0x9e] -; CHECK: fcvtnu x1, s2, #1 ; encoding: [0x41,0xfc,0x01,0x9e] ; CHECK: fcvtnu x1, d2 ; encoding: [0x41,0x00,0x61,0x9e] -; CHECK: fcvtnu x1, d2, #1 ; encoding: [0x41,0xfc,0x41,0x9e] fcvtps w1, s2 - fcvtps w1, s2, #1 fcvtps w1, d2 - fcvtps w1, d2, #1 fcvtps x1, s2 - fcvtps x1, s2, #1 fcvtps x1, d2 - fcvtps x1, d2, #1 ; CHECK: fcvtps w1, s2 ; encoding: [0x41,0x00,0x28,0x1e] -; CHECK: fcvtps w1, s2, #1 ; encoding: [0x41,0xfc,0x08,0x1e] ; CHECK: fcvtps w1, d2 ; encoding: [0x41,0x00,0x68,0x1e] -; CHECK: fcvtps w1, d2, #1 ; encoding: [0x41,0xfc,0x48,0x1e] ; CHECK: fcvtps x1, s2 ; encoding: [0x41,0x00,0x28,0x9e] -; CHECK: fcvtps x1, s2, #1 ; encoding: [0x41,0xfc,0x08,0x9e] ; CHECK: fcvtps x1, d2 ; encoding: [0x41,0x00,0x68,0x9e] -; CHECK: fcvtps x1, d2, #1 ; encoding: [0x41,0xfc,0x48,0x9e] fcvtpu w1, s2 - fcvtpu w1, s2, #1 fcvtpu w1, d2 - fcvtpu w1, d2, #1 fcvtpu x1, s2 - fcvtpu x1, s2, #1 fcvtpu x1, d2 - fcvtpu x1, d2, #1 ; CHECK: fcvtpu w1, s2 ; encoding: [0x41,0x00,0x29,0x1e] -; CHECK: fcvtpu w1, s2, #1 ; encoding: [0x41,0xfc,0x09,0x1e] ; CHECK: fcvtpu w1, d2 ; encoding: [0x41,0x00,0x69,0x1e] -; CHECK: fcvtpu w1, d2, #1 ; encoding: [0x41,0xfc,0x49,0x1e] ; CHECK: fcvtpu x1, s2 ; encoding: [0x41,0x00,0x29,0x9e] -; CHECK: fcvtpu x1, s2, #1 ; encoding: [0x41,0xfc,0x09,0x9e] ; CHECK: fcvtpu x1, d2 ; encoding: [0x41,0x00,0x69,0x9e] -; CHECK: fcvtpu x1, d2, #1 ; encoding: [0x41,0xfc,0x49,0x9e] fcvtzs w1, s2 fcvtzs w1, s2, #1 @@ -397,13 +333,13 @@ foo: fmov s2, #0.0 fmov d2, #0.0 -; CHECK: fmov s1, #1.250000e-01 ; encoding: [0x01,0x10,0x28,0x1e] -; CHECK: fmov s1, #1.250000e-01 ; encoding: [0x01,0x10,0x28,0x1e] -; CHECK: fmov d1, #1.250000e-01 ; encoding: [0x01,0x10,0x68,0x1e] -; CHECK: fmov d1, #1.250000e-01 ; encoding: [0x01,0x10,0x68,0x1e] -; CHECK: fmov d1, #-4.843750e-01 ; encoding: [0x01,0xf0,0x7b,0x1e] -; CHECK: fmov d1, #4.843750e-01 ; encoding: [0x01,0xf0,0x6b,0x1e] -; CHECK: fmov d3, #3.000000e+00 ; encoding: [0x03,0x10,0x61,0x1e] +; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e] +; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e] +; CHECK: fmov d1, #0.12500000 ; encoding: [0x01,0x10,0x68,0x1e] +; CHECK: fmov d1, #0.12500000 ; encoding: [0x01,0x10,0x68,0x1e] +; CHECK: fmov d1, #-0.48437500 ; encoding: [0x01,0xf0,0x7b,0x1e] +; CHECK: fmov d1, #0.48437500 ; encoding: [0x01,0xf0,0x6b,0x1e] +; CHECK: fmov d3, #3.00000000 ; encoding: [0x03,0x10,0x61,0x1e] ; CHECK: fmov s2, wzr ; encoding: [0xe2,0x03,0x27,0x1e] ; CHECK: fmov d2, xzr ; encoding: [0xe2,0x03,0x67,0x9e] diff --git a/test/MC/ARM64/large-relocs.s b/test/MC/AArch64/arm64-large-relocs.s index 348ceb6..2a0cfa2 100644 --- a/test/MC/ARM64/large-relocs.s +++ b/test/MC/AArch64/arm64-large-relocs.s @@ -3,36 +3,36 @@ movz x2, #:abs_g0:sym movk w3, #:abs_g0_nc:sym -// CHECK: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_arm64_movw +// CHECK: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_aarch64_movw // CHECK: movk w3, #:abs_g0_nc:sym // encoding: [0bAAA00011,A,0b100AAAAA,0x72] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_aarch64_movw // CHECK-OBJ: 0 R_AARCH64_MOVW_UABS_G0 sym // CHECK-OBJ: 4 R_AARCH64_MOVW_UABS_G0_NC sym movz x4, #:abs_g1:sym movk w5, #:abs_g1_nc:sym -// CHECK: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_arm64_movw +// CHECK: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_aarch64_movw // CHECK: movk w5, #:abs_g1_nc:sym // encoding: [0bAAA00101,A,0b101AAAAA,0x72] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_aarch64_movw // CHECK-OBJ: 8 R_AARCH64_MOVW_UABS_G1 sym // CHECK-OBJ: c R_AARCH64_MOVW_UABS_G1_NC sym movz x6, #:abs_g2:sym movk x7, #:abs_g2_nc:sym -// CHECK: movz x6, #:abs_g2:sym // encoding: [0bAAA00110,A,0b110AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_arm64_movw +// CHECK: movz x6, #:abs_g2:sym // encoding: [0bAAA00110,A,0b110AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_aarch64_movw // CHECK: movk x7, #:abs_g2_nc:sym // encoding: [0bAAA00111,A,0b110AAAAA,0xf2] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_aarch64_movw // CHECK-OBJ: 10 R_AARCH64_MOVW_UABS_G2 sym // CHECK-OBJ: 14 R_AARCH64_MOVW_UABS_G2_NC sym movz x8, #:abs_g3:sym -// CHECK: movz x8, #:abs_g3:sym // encoding: [0bAAA01000,A,0b111AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_arm64_movw +// CHECK: movz x8, #:abs_g3:sym // encoding: [0bAAA01000,A,0b111AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_aarch64_movw // CHECK-OBJ: 18 R_AARCH64_MOVW_UABS_G3 sym diff --git a/test/MC/AArch64/arm64-leaf-compact-unwind.s b/test/MC/AArch64/arm64-leaf-compact-unwind.s new file mode 100644 index 0000000..d699813 --- /dev/null +++ b/test/MC/AArch64/arm64-leaf-compact-unwind.s @@ -0,0 +1,208 @@ +// RUN: llvm-mc -triple=arm64-apple-ios -filetype=obj < %s | \ +// RUN: llvm-readobj -sections -section-relocations -section-data | \ +// RUN: FileCheck %s +// +// rdar://13070556 + +// FIXME: we should add compact unwind support to llvm-objdump -unwind-info + +// CHECK: Section { +// CHECK: Index: 1 +// CHECK-NEXT: Name: __compact_unwind +// CHECK-NEXT: Segment: __LD +// CHECK-NEXT: Address: +// CHECK-NEXT: Size: +// CHECK-NEXT: Offset: +// CHECK-NEXT: Alignment: +// CHECK-NEXT: RelocationOffset: +// CHECK-NEXT: RelocationCount: +// CHECK-NEXT: Type: +// CHECK-NEXT: Attributes [ +// CHECK-NEXT: Debug +// CHECK-NEXT: ] +// CHECK-NEXT: Reserved1: +// CHECK-NEXT: Reserved2: +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x60 0 3 0 ARM64_RELOC_UNSIGNED 0 - +// CHECK-NEXT: 0x40 0 3 0 ARM64_RELOC_UNSIGNED 0 - +// CHECK-NEXT: 0x20 0 3 0 ARM64_RELOC_UNSIGNED 0 - +// CHECK-NEXT: 0x0 0 3 0 ARM64_RELOC_UNSIGNED 0 - +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 00000000 00000000 08000000 00000002 +// CHECK-NEXT: 0010: 00000000 00000000 00000000 00000000 +// CHECK-NEXT: 0020: 08000000 00000000 40000000 00900002 +// CHECK-NEXT: 0030: 00000000 00000000 00000000 00000000 +// CHECK-NEXT: 0040: 48000000 00000000 D4000000 0F400002 +// CHECK-NEXT: 0050: 00000000 00000000 00000000 00000000 +// CHECK-NEXT: 0060: 1C010000 00000000 54000000 10100202 +// CHECK-NEXT: 0070: 00000000 00000000 00000000 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } + + .section __TEXT,__text,regular,pure_instructions + .globl _foo1 + .align 2 +_foo1: ; @foo1 + .cfi_startproc +; BB#0: ; %entry + add w0, w0, #42 ; =#42 + ret + .cfi_endproc + + .globl _foo2 + .align 2 +_foo2: ; @foo2 + .cfi_startproc +; BB#0: ; %entry + sub sp, sp, #144 ; =#144 +Ltmp2: + .cfi_def_cfa_offset 144 + mov x9, xzr + mov x8, sp +LBB1_1: ; %for.body + ; =>This Inner Loop Header: Depth=1 + str w9, [x8, x9, lsl #2] + add x9, x9, #1 ; =#1 + cmp w9, #36 ; =#36 + b.ne LBB1_1 +; BB#2: + mov x9, xzr + mov w0, wzr +LBB1_3: ; %for.body4 + ; =>This Inner Loop Header: Depth=1 + ldr w10, [x8, x9] + add x9, x9, #4 ; =#4 + cmp w9, #144 ; =#144 + add w0, w10, w0 + b.ne LBB1_3 +; BB#4: ; %for.end9 + add sp, sp, #144 ; =#144 + ret + .cfi_endproc + + .globl _foo3 + .align 2 +_foo3: ; @foo3 + .cfi_startproc +; BB#0: ; %entry + stp x26, x25, [sp, #-64]! + stp x24, x23, [sp, #16] + stp x22, x21, [sp, #32] + stp x20, x19, [sp, #48] +Ltmp3: + .cfi_def_cfa_offset 64 +Ltmp4: + .cfi_offset w19, -16 +Ltmp5: + .cfi_offset w20, -24 +Ltmp6: + .cfi_offset w21, -32 +Ltmp7: + .cfi_offset w22, -40 +Ltmp8: + .cfi_offset w23, -48 +Ltmp9: + .cfi_offset w24, -56 +Ltmp10: + .cfi_offset w25, -64 +Ltmp11: + .cfi_offset w26, -72 +Lloh0: + adrp x8, _bar@GOTPAGE +Lloh1: + ldr x8, [x8, _bar@GOTPAGEOFF] + ldr w9, [x8] + ldr w10, [x8] + ldr w11, [x8] + ldr w12, [x8] + ldr w13, [x8] + ldr w14, [x8] + ldr w15, [x8] + ldr w16, [x8] + ldr w17, [x8] + ldr w0, [x8] + ldr w19, [x8] + ldr w20, [x8] + ldr w21, [x8] + ldr w22, [x8] + ldr w23, [x8] + ldr w24, [x8] + ldr w25, [x8] + ldr w8, [x8] + add w9, w10, w9 + add w9, w9, w11 + add w9, w9, w12 + add w9, w9, w13 + add w9, w9, w14 + add w9, w9, w15 + add w9, w9, w16 + add w9, w9, w17 + add w9, w9, w0 + add w9, w9, w19 + add w9, w9, w20 + add w9, w9, w21 + add w9, w9, w22 + add w9, w9, w23 + add w9, w9, w24 + add w9, w9, w25 + sub w8, w8, w9 + sub w8, w8, w7, lsl #1 + sub w8, w8, w6, lsl #1 + sub w8, w8, w5, lsl #1 + sub w8, w8, w4, lsl #1 + sub w8, w8, w3, lsl #1 + sub w8, w8, w2, lsl #1 + sub w0, w8, w1, lsl #1 + ldp x20, x19, [sp, #48] + ldp x22, x21, [sp, #32] + ldp x24, x23, [sp, #16] + ldp x26, x25, [sp], #64 + ret + .loh AdrpLdrGot Lloh0, Lloh1 + .cfi_endproc + + .globl _foo4 + .align 2 +_foo4: ; @foo4 + .cfi_startproc +; BB#0: ; %entry + stp x28, x27, [sp, #-16]! + sub sp, sp, #512 ; =#512 +Ltmp12: + .cfi_def_cfa_offset 528 +Ltmp13: + .cfi_offset w27, -16 +Ltmp14: + .cfi_offset w28, -24 + ; kill: W0<def> W0<kill> X0<def> + mov x9, xzr + ubfx x10, x0, #0, #32 + mov x8, sp +LBB3_1: ; %for.body + ; =>This Inner Loop Header: Depth=1 + add w11, w10, w9 + str w11, [x8, x9, lsl #2] + add x9, x9, #1 ; =#1 + cmp w9, #128 ; =#128 + b.ne LBB3_1 +; BB#2: ; %for.cond2.preheader + mov x9, xzr + mov w0, wzr + add x8, x8, w5, sxtw #2 +LBB3_3: ; %for.body4 + ; =>This Inner Loop Header: Depth=1 + ldr w10, [x8, x9] + add x9, x9, #4 ; =#4 + cmp w9, #512 ; =#512 + add w0, w10, w0 + b.ne LBB3_3 +; BB#4: ; %for.end11 + add sp, sp, #512 ; =#512 + ldp x28, x27, [sp], #16 + ret + .cfi_endproc + + .comm _bar,4,2 ; @bar + +.subsections_via_symbols diff --git a/test/MC/ARM64/logical-encoding.s b/test/MC/AArch64/arm64-logical-encoding.s index e5f1436..e5f1436 100644 --- a/test/MC/ARM64/logical-encoding.s +++ b/test/MC/AArch64/arm64-logical-encoding.s diff --git a/test/MC/ARM64/mapping-across-sections.s b/test/MC/AArch64/arm64-mapping-across-sections.s index 00b324c..00b324c 100644 --- a/test/MC/ARM64/mapping-across-sections.s +++ b/test/MC/AArch64/arm64-mapping-across-sections.s diff --git a/test/MC/ARM64/mapping-within-section.s b/test/MC/AArch64/arm64-mapping-within-section.s index f515cb9..f515cb9 100644 --- a/test/MC/ARM64/mapping-within-section.s +++ b/test/MC/AArch64/arm64-mapping-within-section.s diff --git a/test/MC/ARM64/memory.s b/test/MC/AArch64/arm64-memory.s index 0e8f1d5..5798596 100644 --- a/test/MC/ARM64/memory.s +++ b/test/MC/AArch64/arm64-memory.s @@ -208,32 +208,32 @@ foo: ; Pre-indexed loads and stores ;----------------------------------------------------------------------------- - ldr fp, [x7, #8]! - ldr lr, [x7, #8]! + ldr x29, [x7, #8]! + ldr x30, [x7, #8]! ldr b5, [x0, #1]! ldr h6, [x0, #2]! ldr s7, [x0, #4]! ldr d8, [x0, #8]! ldr q9, [x0, #16]! - str lr, [x7, #-8]! - str fp, [x7, #-8]! + str x30, [x7, #-8]! + str x29, [x7, #-8]! str b5, [x0, #-1]! str h6, [x0, #-2]! str s7, [x0, #-4]! str d8, [x0, #-8]! str q9, [x0, #-16]! -; CHECK: ldr fp, [x7, #8]! ; encoding: [0xfd,0x8c,0x40,0xf8] -; CHECK: ldr lr, [x7, #8]! ; encoding: [0xfe,0x8c,0x40,0xf8] +; CHECK: ldr x29, [x7, #8]! ; encoding: [0xfd,0x8c,0x40,0xf8] +; CHECK: ldr x30, [x7, #8]! ; encoding: [0xfe,0x8c,0x40,0xf8] ; CHECK: ldr b5, [x0, #1]! ; encoding: [0x05,0x1c,0x40,0x3c] ; CHECK: ldr h6, [x0, #2]! ; encoding: [0x06,0x2c,0x40,0x7c] ; CHECK: ldr s7, [x0, #4]! ; encoding: [0x07,0x4c,0x40,0xbc] ; CHECK: ldr d8, [x0, #8]! ; encoding: [0x08,0x8c,0x40,0xfc] ; CHECK: ldr q9, [x0, #16]! ; encoding: [0x09,0x0c,0xc1,0x3c] -; CHECK: str lr, [x7, #-8]! ; encoding: [0xfe,0x8c,0x1f,0xf8] -; CHECK: str fp, [x7, #-8]! ; encoding: [0xfd,0x8c,0x1f,0xf8] +; CHECK: str x30, [x7, #-8]! ; encoding: [0xfe,0x8c,0x1f,0xf8] +; CHECK: str x29, [x7, #-8]! ; encoding: [0xfd,0x8c,0x1f,0xf8] ; CHECK: str b5, [x0, #-1]! ; encoding: [0x05,0xfc,0x1f,0x3c] ; CHECK: str h6, [x0, #-2]! ; encoding: [0x06,0xec,0x1f,0x7c] ; CHECK: str s7, [x0, #-4]! ; encoding: [0x07,0xcc,0x1f,0xbc] @@ -243,32 +243,32 @@ foo: ;----------------------------------------------------------------------------- ; post-indexed loads and stores ;----------------------------------------------------------------------------- - str lr, [x7], #-8 - str fp, [x7], #-8 + str x30, [x7], #-8 + str x29, [x7], #-8 str b5, [x0], #-1 str h6, [x0], #-2 str s7, [x0], #-4 str d8, [x0], #-8 str q9, [x0], #-16 - ldr fp, [x7], #8 - ldr lr, [x7], #8 + ldr x29, [x7], #8 + ldr x30, [x7], #8 ldr b5, [x0], #1 ldr h6, [x0], #2 ldr s7, [x0], #4 ldr d8, [x0], #8 ldr q9, [x0], #16 -; CHECK: str lr, [x7], #-8 ; encoding: [0xfe,0x84,0x1f,0xf8] -; CHECK: str fp, [x7], #-8 ; encoding: [0xfd,0x84,0x1f,0xf8] +; CHECK: str x30, [x7], #-8 ; encoding: [0xfe,0x84,0x1f,0xf8] +; CHECK: str x29, [x7], #-8 ; encoding: [0xfd,0x84,0x1f,0xf8] ; CHECK: str b5, [x0], #-1 ; encoding: [0x05,0xf4,0x1f,0x3c] ; CHECK: str h6, [x0], #-2 ; encoding: [0x06,0xe4,0x1f,0x7c] ; CHECK: str s7, [x0], #-4 ; encoding: [0x07,0xc4,0x1f,0xbc] ; CHECK: str d8, [x0], #-8 ; encoding: [0x08,0x84,0x1f,0xfc] ; CHECK: str q9, [x0], #-16 ; encoding: [0x09,0x04,0x9f,0x3c] -; CHECK: ldr fp, [x7], #8 ; encoding: [0xfd,0x84,0x40,0xf8] -; CHECK: ldr lr, [x7], #8 ; encoding: [0xfe,0x84,0x40,0xf8] +; CHECK: ldr x29, [x7], #8 ; encoding: [0xfd,0x84,0x40,0xf8] +; CHECK: ldr x30, [x7], #8 ; encoding: [0xfe,0x84,0x40,0xf8] ; CHECK: ldr b5, [x0], #1 ; encoding: [0x05,0x14,0x40,0x3c] ; CHECK: ldr h6, [x0], #2 ; encoding: [0x06,0x24,0x40,0x7c] ; CHECK: ldr s7, [x0], #4 ; encoding: [0x07,0x44,0x40,0xbc] @@ -426,14 +426,14 @@ foo: ; CHECK: ldr q1, [x1, x2, lsl #4] ; encoding: [0x21,0x78,0xe2,0x3c] str d1, [sp, x3] - str d1, [sp, x3, uxtw #3] + str d1, [sp, w3, uxtw #3] str q1, [sp, x3] - str q1, [sp, x3, uxtw #4] + str q1, [sp, w3, uxtw #4] ; CHECK: str d1, [sp, x3] ; encoding: [0xe1,0x6b,0x23,0xfc] -; CHECK: str d1, [sp, x3, uxtw #3] ; encoding: [0xe1,0x5b,0x23,0xfc] +; CHECK: str d1, [sp, w3, uxtw #3] ; encoding: [0xe1,0x5b,0x23,0xfc] ; CHECK: str q1, [sp, x3] ; encoding: [0xe1,0x6b,0xa3,0x3c] -; CHECK: str q1, [sp, x3, uxtw #4] ; encoding: [0xe1,0x5b,0xa3,0x3c] +; CHECK: str q1, [sp, w3, uxtw #4] ; encoding: [0xe1,0x5b,0xa3,0x3c] ;----------------------------------------------------------------------------- ; Load literal @@ -545,8 +545,8 @@ foo: ; unambiguous, i.e. negative or unaligned." ;----------------------------------------------------------------------------- - ldr x11, [fp, #-8] - ldr x11, [fp, #7] + ldr x11, [x29, #-8] + ldr x11, [x29, #7] ldr w0, [x0, #2] ldr w0, [x0, #-256] ldr b2, [x1, #-2] @@ -559,8 +559,8 @@ foo: ldr q5, [x8, #8] ldr q5, [x9, #-16] -; CHECK: ldur x11, [fp, #-8] ; encoding: [0xab,0x83,0x5f,0xf8] -; CHECK: ldur x11, [fp, #7] ; encoding: [0xab,0x73,0x40,0xf8] +; CHECK: ldur x11, [x29, #-8] ; encoding: [0xab,0x83,0x5f,0xf8] +; CHECK: ldur x11, [x29, #7] ; encoding: [0xab,0x73,0x40,0xf8] ; CHECK: ldur w0, [x0, #2] ; encoding: [0x00,0x20,0x40,0xb8] ; CHECK: ldur w0, [x0, #-256] ; encoding: [0x00,0x00,0x50,0xb8] ; CHECK: ldur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x5f,0x3c] @@ -573,8 +573,8 @@ foo: ; CHECK: ldur q5, [x8, #8] ; encoding: [0x05,0x81,0xc0,0x3c] ; CHECK: ldur q5, [x9, #-16] ; encoding: [0x25,0x01,0xdf,0x3c] - str x11, [fp, #-8] - str x11, [fp, #7] + str x11, [x29, #-8] + str x11, [x29, #7] str w0, [x0, #2] str w0, [x0, #-256] str b2, [x1, #-2] @@ -587,8 +587,8 @@ foo: str q5, [x8, #8] str q5, [x9, #-16] -; CHECK: stur x11, [fp, #-8] ; encoding: [0xab,0x83,0x1f,0xf8] -; CHECK: stur x11, [fp, #7] ; encoding: [0xab,0x73,0x00,0xf8] +; CHECK: stur x11, [x29, #-8] ; encoding: [0xab,0x83,0x1f,0xf8] +; CHECK: stur x11, [x29, #7] ; encoding: [0xab,0x73,0x00,0xf8] ; CHECK: stur w0, [x0, #2] ; encoding: [0x00,0x20,0x00,0xb8] ; CHECK: stur w0, [x0, #-256] ; encoding: [0x00,0x00,0x10,0xb8] ; CHECK: stur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x1f,0x3c] diff --git a/test/MC/AArch64/arm64-nv-cond.s b/test/MC/AArch64/arm64-nv-cond.s new file mode 100644 index 0000000..1b4d054 --- /dev/null +++ b/test/MC/AArch64/arm64-nv-cond.s @@ -0,0 +1,11 @@ +// RUN: llvm-mc < %s -triple arm64 -mattr=neon -show-encoding | FileCheck %s + +fcsel d28,d31,d31,nv +csel x0,x0,x0,nv +ccmp x0,x0,#0,nv +b.nv #0 + +// CHECK: fcsel d28, d31, d31, nv // encoding: [0xfc,0xff,0x7f,0x1e] +// CHECK: csel x0, x0, x0, nv // encoding: [0x00,0xf0,0x80,0x9a] +// CHECK: ccmp x0, x0, #0, nv // encoding: [0x00,0xf0,0x40,0xfa] +// CHECK: b.nv #0 // encoding: [0x0f,0x00,0x00,0x54] diff --git a/test/MC/AArch64/arm64-optional-hash.s b/test/MC/AArch64/arm64-optional-hash.s new file mode 100644 index 0000000..71e2fda --- /dev/null +++ b/test/MC/AArch64/arm64-optional-hash.s @@ -0,0 +1,31 @@ +; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s +.text +; parseOperand check +; CHECK: add sp, sp, #32 ; encoding: [0xff,0x83,0x00,0x91] + add sp, sp, 32 + +; Optional shift +; CHECK: adds x3, x4, #1024, lsl #12 ; encoding: [0x83,0x00,0x50,0xb1] +adds x3, x4, 1024, lsl 12 + +; Optional extend +; CHECK: add sp, x2, x3 ; encoding: [0x5f,0x60,0x23,0x8b] +add sp, x2, x3, uxtx 0 + +; FP immediates +; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e] +fmov s1, 0.125 + +; Barrier operand +; CHECK: dmb osh ; encoding: [0xbf,0x33,0x03,0xd5] +dmb 3 + +; Prefetch and memory + +; Single register inside [] +; CHECK: ldnp w3, w2, [x15, #16] ; encoding: [0xe3,0x09,0x42,0x28] +ldnp w3, w2, [x15, 16] + +; Memory, two registers inside [] +; CHECK: prfm pstl3strm, [x4, x5, lsl #3] ; encoding: [0x95,0x78,0xa5,0xf8] +prfm pstl3strm, [x4, x5, lsl 3] diff --git a/test/MC/ARM64/separator.s b/test/MC/AArch64/arm64-separator.s index 18f34b9..e67deba 100644 --- a/test/MC/ARM64/separator.s +++ b/test/MC/AArch64/arm64-separator.s @@ -1,6 +1,6 @@ ; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s -; ARM64 uses a multi-character statment separator, "%%". Check that we lex +; ARM64 uses a multi-character statement separator, "%%". Check that we lex ; it properly and recognize the multiple assembly statements on the line. ; To make sure the output assembly correctly handled the instructions, diff --git a/test/MC/ARM64/simd-ldst.s b/test/MC/AArch64/arm64-simd-ldst.s index a754c72..3085485 100644 --- a/test/MC/ARM64/simd-ldst.s +++ b/test/MC/AArch64/arm64-simd-ldst.s @@ -1,4 +1,4 @@ -; RUN: llvm-mc -triple arm64-apple-darwin -output-asm-variant=1 -show-encoding < %s | FileCheck %s +; RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon -output-asm-variant=1 -show-encoding < %s | FileCheck %s _ld1st1_multiple: ld1.8b {v0}, [x1] @@ -263,10 +263,10 @@ ld3st3_multiple: ; CHECK: ld3.8b { v9, v10, v11 }, [x9] ; encoding: [0x29,0x41,0x40,0x0c] ; CHECK: ld3.16b { v14, v15, v16 }, [x19] ; encoding: [0x6e,0x42,0x40,0x4c] -; CHECK: ld3.4h { v24, v25, v26 }, [fp] ; encoding: [0xb8,0x47,0x40,0x0c] +; CHECK: ld3.4h { v24, v25, v26 }, [x29] ; encoding: [0xb8,0x47,0x40,0x0c] ; CHECK: ld3.8h { v30, v31, v0 }, [x9] ; encoding: [0x3e,0x45,0x40,0x4c] ; CHECK: ld3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x40,0x0c] -; CHECK: ld3.4s { v4, v5, v6 }, [fp] ; encoding: [0xa4,0x4b,0x40,0x4c] +; CHECK: ld3.4s { v4, v5, v6 }, [x29] ; encoding: [0xa4,0x4b,0x40,0x4c] ; CHECK: ld3.2d { v7, v8, v9 }, [x9] ; encoding: [0x27,0x4d,0x40,0x4c] ; CHECK: st3.8b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x00,0x0c] @@ -279,10 +279,10 @@ ld3st3_multiple: ; CHECK: st3.8b { v10, v11, v12 }, [x9] ; encoding: [0x2a,0x41,0x00,0x0c] ; CHECK: st3.16b { v14, v15, v16 }, [x19] ; encoding: [0x6e,0x42,0x00,0x4c] -; CHECK: st3.4h { v24, v25, v26 }, [fp] ; encoding: [0xb8,0x47,0x00,0x0c] +; CHECK: st3.4h { v24, v25, v26 }, [x29] ; encoding: [0xb8,0x47,0x00,0x0c] ; CHECK: st3.8h { v30, v31, v0 }, [x9] ; encoding: [0x3e,0x45,0x00,0x4c] ; CHECK: st3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x00,0x0c] -; CHECK: st3.4s { v7, v8, v9 }, [fp] ; encoding: [0xa7,0x4b,0x00,0x4c] +; CHECK: st3.4s { v7, v8, v9 }, [x29] ; encoding: [0xa7,0x4b,0x00,0x4c] ; CHECK: st3.2d { v4, v5, v6 }, [x9] ; encoding: [0x24,0x4d,0x00,0x4c] ld4st4_multiple: diff --git a/test/MC/ARM64/small-data-fixups.s b/test/MC/AArch64/arm64-small-data-fixups.s index 3fe7c75..3fe7c75 100644 --- a/test/MC/ARM64/small-data-fixups.s +++ b/test/MC/AArch64/arm64-small-data-fixups.s diff --git a/test/MC/AArch64/arm64-spsel-sysreg.s b/test/MC/AArch64/arm64-spsel-sysreg.s new file mode 100644 index 0000000..f1d94d8 --- /dev/null +++ b/test/MC/AArch64/arm64-spsel-sysreg.s @@ -0,0 +1,24 @@ +// RUN: not llvm-mc -triple arm64 -show-encoding < %s 2>%t | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + +msr SPSel, #0 +msr SPSel, x0 +msr DAIFSet, #0 +msr ESR_EL1, x0 +mrs x0, SPSel +mrs x0, ESR_EL1 + +// CHECK: msr SPSEL, #0 // encoding: [0xbf,0x40,0x00,0xd5] +// CHECK: msr SPSEL, x0 // encoding: [0x00,0x42,0x18,0xd5] +// CHECK: msr DAIFSET, #0 // encoding: [0xdf,0x40,0x03,0xd5] +// CHECK: msr ESR_EL1, x0 // encoding: [0x00,0x52,0x18,0xd5] +// CHECK: mrs x0, SPSEL // encoding: [0x00,0x42,0x38,0xd5] +// CHECK: mrs x0, ESR_EL1 // encoding: [0x00,0x52,0x38,0xd5] + + +msr DAIFSet, x0 +msr ESR_EL1, #0 +mrs x0, DAIFSet +// CHECK-ERRORS: error: immediate must be an integer in range [0, 15] +// CHECK-ERRORS: error: invalid operand for instruction +// CHECK-ERRORS: error: expected readable system register diff --git a/test/MC/ARM64/system-encoding.s b/test/MC/AArch64/arm64-system-encoding.s index 9f0d3c4..9246608 100644 --- a/test/MC/ARM64/system-encoding.s +++ b/test/MC/AArch64/arm64-system-encoding.s @@ -52,7 +52,7 @@ foo: ; Check for error on invalid 'C' operand value. sys #2, c16, c5, #7 -; CHECK-ERRORS: invalid operand for instruction +; CHECK-ERRORS: error: Expected cN operand where 0 <= N <= 15 ;----------------------------------------------------------------------------- ; MSR/MRS instructions @@ -60,29 +60,24 @@ foo: msr ACTLR_EL1, x3 msr ACTLR_EL2, x3 msr ACTLR_EL3, x3 - msr ADFSR_EL1, x3 - msr ADFSR_EL2, x3 - msr ADFSR_EL3, x3 - msr AIDR_EL1, x3 - msr AIFSR_EL1, x3 - msr AIFSR_EL2, x3 - msr AIFSR_EL3, x3 + msr AFSR0_EL1, x3 + msr AFSR0_EL2, x3 + msr AFSR0_EL3, x3 + msr AFSR1_EL1, x3 + msr AFSR1_EL2, x3 + msr AFSR1_EL3, x3 msr AMAIR_EL1, x3 msr AMAIR_EL2, x3 msr AMAIR_EL3, x3 - msr CCSIDR_EL1, x3 - msr CLIDR_EL1, x3 msr CNTFRQ_EL0, x3 msr CNTHCTL_EL2, x3 msr CNTHP_CTL_EL2, x3 msr CNTHP_CVAL_EL2, x3 msr CNTHP_TVAL_EL2, x3 msr CNTKCTL_EL1, x3 - msr CNTPCT_EL0, x3 msr CNTP_CTL_EL0, x3 msr CNTP_CVAL_EL0, x3 msr CNTP_TVAL_EL0, x3 - msr CNTVCT_EL0, x3 msr CNTVOFF_EL2, x3 msr CNTV_CTL_EL0, x3 msr CNTV_CVAL_EL0, x3 @@ -92,11 +87,8 @@ foo: msr CPTR_EL2, x3 msr CPTR_EL3, x3 msr CSSELR_EL1, x3 - msr CTR_EL0, x3 - msr CURRENT_EL, x3 + msr CURRENTEL, x3 msr DACR32_EL2, x3 - msr DCZID_EL0, x3 - msr ECOIDR_EL1, x3 msr ESR_EL1, x3 msr ESR_EL2, x3 msr ESR_EL3, x3 @@ -108,29 +100,13 @@ foo: msr HCR_EL2, x3 msr HPFAR_EL2, x3 msr HSTR_EL2, x3 - msr ID_AA64DFR0_EL1, x3 - msr ID_AA64DFR1_EL1, x3 - msr ID_AA64ISAR0_EL1, x3 - msr ID_AA64ISAR1_EL1, x3 - msr ID_AA64MMFR0_EL1, x3 - msr ID_AA64MMFR1_EL1, x3 - msr ID_AA64PFR0_EL1, x3 - msr ID_AA64PFR1_EL1, x3 msr IFSR32_EL2, x3 - msr ISR_EL1, x3 msr MAIR_EL1, x3 msr MAIR_EL2, x3 msr MAIR_EL3, x3 msr MDCR_EL2, x3 msr MDCR_EL3, x3 - msr MIDR_EL1, x3 - msr MPIDR_EL1, x3 - msr MVFR0_EL1, x3 - msr MVFR1_EL1, x3 msr PAR_EL1, x3 - msr RVBAR_EL1, x3 - msr RVBAR_EL2, x3 - msr RVBAR_EL3, x3 msr SCR_EL3, x3 msr SCTLR_EL1, x3 msr SCTLR_EL2, x3 @@ -158,33 +134,28 @@ foo: msr VTCR_EL2, x3 msr VTTBR_EL2, x3 msr SPSel, x3 - msr S2_2_C4_C6_4, x1 + msr S3_2_C11_C6_4, x1 ; CHECK: msr ACTLR_EL1, x3 ; encoding: [0x23,0x10,0x18,0xd5] ; CHECK: msr ACTLR_EL2, x3 ; encoding: [0x23,0x10,0x1c,0xd5] ; CHECK: msr ACTLR_EL3, x3 ; encoding: [0x23,0x10,0x1e,0xd5] ; CHECK: msr AFSR0_EL1, x3 ; encoding: [0x03,0x51,0x18,0xd5] -; CHECK: msr ADFSR_EL2, x3 ; encoding: [0x03,0x51,0x1c,0xd5] -; CHECK: msr ADFSR_EL3, x3 ; encoding: [0x03,0x51,0x1e,0xd5] -; CHECK: msr AIDR_EL1, x3 ; encoding: [0xe3,0x00,0x19,0xd5] +; CHECK: msr AFSR0_EL2, x3 ; encoding: [0x03,0x51,0x1c,0xd5] +; CHECK: msr AFSR0_EL3, x3 ; encoding: [0x03,0x51,0x1e,0xd5] ; CHECK: msr AFSR1_EL1, x3 ; encoding: [0x23,0x51,0x18,0xd5] -; CHECK: msr AIFSR_EL2, x3 ; encoding: [0x23,0x51,0x1c,0xd5] -; CHECK: msr AIFSR_EL3, x3 ; encoding: [0x23,0x51,0x1e,0xd5] +; CHECK: msr AFSR1_EL2, x3 ; encoding: [0x23,0x51,0x1c,0xd5] +; CHECK: msr AFSR1_EL3, x3 ; encoding: [0x23,0x51,0x1e,0xd5] ; CHECK: msr AMAIR_EL1, x3 ; encoding: [0x03,0xa3,0x18,0xd5] ; CHECK: msr AMAIR_EL2, x3 ; encoding: [0x03,0xa3,0x1c,0xd5] ; CHECK: msr AMAIR_EL3, x3 ; encoding: [0x03,0xa3,0x1e,0xd5] -; CHECK: msr CCSIDR_EL1, x3 ; encoding: [0x03,0x00,0x19,0xd5] -; CHECK: msr CLIDR_EL1, x3 ; encoding: [0x23,0x00,0x19,0xd5] ; CHECK: msr CNTFRQ_EL0, x3 ; encoding: [0x03,0xe0,0x1b,0xd5] ; CHECK: msr CNTHCTL_EL2, x3 ; encoding: [0x03,0xe1,0x1c,0xd5] ; CHECK: msr CNTHP_CTL_EL2, x3 ; encoding: [0x23,0xe2,0x1c,0xd5] ; CHECK: msr CNTHP_CVAL_EL2, x3 ; encoding: [0x43,0xe2,0x1c,0xd5] ; CHECK: msr CNTHP_TVAL_EL2, x3 ; encoding: [0x03,0xe2,0x1c,0xd5] ; CHECK: msr CNTKCTL_EL1, x3 ; encoding: [0x03,0xe1,0x18,0xd5] -; CHECK: msr CNTPCT_EL0, x3 ; encoding: [0x23,0xe0,0x1b,0xd5] ; CHECK: msr CNTP_CTL_EL0, x3 ; encoding: [0x23,0xe2,0x1b,0xd5] ; CHECK: msr CNTP_CVAL_EL0, x3 ; encoding: [0x43,0xe2,0x1b,0xd5] ; CHECK: msr CNTP_TVAL_EL0, x3 ; encoding: [0x03,0xe2,0x1b,0xd5] -; CHECK: msr CNTVCT_EL0, x3 ; encoding: [0x43,0xe0,0x1b,0xd5] ; CHECK: msr CNTVOFF_EL2, x3 ; encoding: [0x63,0xe0,0x1c,0xd5] ; CHECK: msr CNTV_CTL_EL0, x3 ; encoding: [0x23,0xe3,0x1b,0xd5] ; CHECK: msr CNTV_CVAL_EL0, x3 ; encoding: [0x43,0xe3,0x1b,0xd5] @@ -194,11 +165,8 @@ foo: ; CHECK: msr CPTR_EL2, x3 ; encoding: [0x43,0x11,0x1c,0xd5] ; CHECK: msr CPTR_EL3, x3 ; encoding: [0x43,0x11,0x1e,0xd5] ; CHECK: msr CSSELR_EL1, x3 ; encoding: [0x03,0x00,0x1a,0xd5] -; CHECK: msr CTR_EL0, x3 ; encoding: [0x23,0x00,0x1b,0xd5] -; CHECK: msr CurrentEL, x3 ; encoding: [0x43,0x42,0x18,0xd5] +; CHECK: msr CURRENTEL, x3 ; encoding: [0x43,0x42,0x18,0xd5] ; CHECK: msr DACR32_EL2, x3 ; encoding: [0x03,0x30,0x1c,0xd5] -; CHECK: msr DCZID_EL0, x3 ; encoding: [0xe3,0x00,0x1b,0xd5] -; CHECK: msr REVIDR_EL1, x3 ; encoding: [0xc3,0x00,0x18,0xd5] ; CHECK: msr ESR_EL1, x3 ; encoding: [0x03,0x52,0x18,0xd5] ; CHECK: msr ESR_EL2, x3 ; encoding: [0x03,0x52,0x1c,0xd5] ; CHECK: msr ESR_EL3, x3 ; encoding: [0x03,0x52,0x1e,0xd5] @@ -210,29 +178,13 @@ foo: ; CHECK: msr HCR_EL2, x3 ; encoding: [0x03,0x11,0x1c,0xd5] ; CHECK: msr HPFAR_EL2, x3 ; encoding: [0x83,0x60,0x1c,0xd5] ; CHECK: msr HSTR_EL2, x3 ; encoding: [0x63,0x11,0x1c,0xd5] -; CHECK: msr ID_AA64DFR0_EL1, x3 ; encoding: [0x03,0x05,0x18,0xd5] -; CHECK: msr ID_AA64DFR1_EL1, x3 ; encoding: [0x23,0x05,0x18,0xd5] -; CHECK: msr ID_AA64ISAR0_EL1, x3 ; encoding: [0x03,0x06,0x18,0xd5] -; CHECK: msr ID_AA64ISAR1_EL1, x3 ; encoding: [0x23,0x06,0x18,0xd5] -; CHECK: msr ID_AA64MMFR0_EL1, x3 ; encoding: [0x03,0x07,0x18,0xd5] -; CHECK: msr ID_AA64MMFR1_EL1, x3 ; encoding: [0x23,0x07,0x18,0xd5] -; CHECK: msr ID_AA64PFR0_EL1, x3 ; encoding: [0x03,0x04,0x18,0xd5] -; CHECK: msr ID_AA64PFR1_EL1, x3 ; encoding: [0x23,0x04,0x18,0xd5] ; CHECK: msr IFSR32_EL2, x3 ; encoding: [0x23,0x50,0x1c,0xd5] -; CHECK: msr ISR_EL1, x3 ; encoding: [0x03,0xc1,0x18,0xd5] ; CHECK: msr MAIR_EL1, x3 ; encoding: [0x03,0xa2,0x18,0xd5] ; CHECK: msr MAIR_EL2, x3 ; encoding: [0x03,0xa2,0x1c,0xd5] ; CHECK: msr MAIR_EL3, x3 ; encoding: [0x03,0xa2,0x1e,0xd5] ; CHECK: msr MDCR_EL2, x3 ; encoding: [0x23,0x11,0x1c,0xd5] ; CHECK: msr MDCR_EL3, x3 ; encoding: [0x23,0x13,0x1e,0xd5] -; CHECK: msr MIDR_EL1, x3 ; encoding: [0x03,0x00,0x18,0xd5] -; CHECK: msr MPIDR_EL1, x3 ; encoding: [0xa3,0x00,0x18,0xd5] -; CHECK: msr MVFR0_EL1, x3 ; encoding: [0x03,0x03,0x18,0xd5] -; CHECK: msr MVFR1_EL1, x3 ; encoding: [0x23,0x03,0x18,0xd5] ; CHECK: msr PAR_EL1, x3 ; encoding: [0x03,0x74,0x18,0xd5] -; CHECK: msr RVBAR_EL1, x3 ; encoding: [0x23,0xc0,0x18,0xd5] -; CHECK: msr RVBAR_EL2, x3 ; encoding: [0x23,0xc0,0x1c,0xd5] -; CHECK: msr RVBAR_EL3, x3 ; encoding: [0x23,0xc0,0x1e,0xd5] ; CHECK: msr SCR_EL3, x3 ; encoding: [0x03,0x11,0x1e,0xd5] ; CHECK: msr SCTLR_EL1, x3 ; encoding: [0x03,0x10,0x18,0xd5] ; CHECK: msr SCTLR_EL2, x3 ; encoding: [0x03,0x10,0x1c,0xd5] @@ -259,19 +211,19 @@ foo: ; CHECK: msr VPIDR_EL2, x3 ; encoding: [0x03,0x00,0x1c,0xd5] ; CHECK: msr VTCR_EL2, x3 ; encoding: [0x43,0x21,0x1c,0xd5] ; CHECK: msr VTTBR_EL2, x3 ; encoding: [0x03,0x21,0x1c,0xd5] -; CHECK: msr SPSel, x3 ; encoding: [0x03,0x42,0x18,0xd5] -; CHECK: msr S2_2_C4_C6_4, x1 ; encoding: [0x81,0x46,0x12,0xd5] +; CHECK: msr SPSEL, x3 ; encoding: [0x03,0x42,0x18,0xd5] +; CHECK: msr S3_2_C11_C6_4, x1 ; encoding: [0x81,0xb6,0x1a,0xd5] mrs x3, ACTLR_EL1 mrs x3, ACTLR_EL2 mrs x3, ACTLR_EL3 - mrs x3, ADFSR_EL1 - mrs x3, ADFSR_EL2 - mrs x3, ADFSR_EL3 + mrs x3, AFSR0_EL1 + mrs x3, AFSR0_EL2 + mrs x3, AFSR0_EL3 mrs x3, AIDR_EL1 - mrs x3, AIFSR_EL1 - mrs x3, AIFSR_EL2 - mrs x3, AIFSR_EL3 + mrs x3, AFSR1_EL1 + mrs x3, AFSR1_EL2 + mrs x3, AFSR1_EL3 mrs x3, AMAIR_EL1 mrs x3, AMAIR_EL2 mrs x3, AMAIR_EL3 @@ -298,10 +250,10 @@ foo: mrs x3, CPTR_EL3 mrs x3, CSSELR_EL1 mrs x3, CTR_EL0 - mrs x3, CURRENT_EL + mrs x3, CURRENTEL mrs x3, DACR32_EL2 mrs x3, DCZID_EL0 - mrs x3, ECOIDR_EL1 + mrs x3, REVIDR_EL1 mrs x3, ESR_EL1 mrs x3, ESR_EL2 mrs x3, ESR_EL3 @@ -367,12 +319,11 @@ foo: mrs x3, MDCCINT_EL1 mrs x3, DBGDTR_EL0 mrs x3, DBGDTRRX_EL0 - mrs x3, DBGDTRTX_EL0 mrs x3, DBGVCR32_EL2 mrs x3, OSDTRRX_EL1 mrs x3, MDSCR_EL1 mrs x3, OSDTRTX_EL1 - mrs x3, OSECCR_EL11 + mrs x3, OSECCR_EL1 mrs x3, DBGBVR0_EL1 mrs x3, DBGBVR1_EL1 mrs x3, DBGBVR2_EL1 @@ -438,30 +389,26 @@ foo: mrs x3, DBGWCR14_EL1 mrs x3, DBGWCR15_EL1 mrs x3, MDRAR_EL1 - mrs x3, OSLAR_EL1 mrs x3, OSLSR_EL1 mrs x3, OSDLR_EL1 mrs x3, DBGPRCR_EL1 mrs x3, DBGCLAIMSET_EL1 mrs x3, DBGCLAIMCLR_EL1 mrs x3, DBGAUTHSTATUS_EL1 - mrs x3, DBGDEVID2 - mrs x3, DBGDEVID1 - mrs x3, DBGDEVID0 - mrs x1, S2_2_C4_C6_4 - mrs x3, s2_3_c2_c1_4 - mrs x3, S2_3_c2_c1_4 + mrs x1, S3_2_C15_C6_4 + mrs x3, s3_3_c11_c1_4 + mrs x3, S3_3_c11_c1_4 ; CHECK: mrs x3, ACTLR_EL1 ; encoding: [0x23,0x10,0x38,0xd5] ; CHECK: mrs x3, ACTLR_EL2 ; encoding: [0x23,0x10,0x3c,0xd5] ; CHECK: mrs x3, ACTLR_EL3 ; encoding: [0x23,0x10,0x3e,0xd5] ; CHECK: mrs x3, AFSR0_EL1 ; encoding: [0x03,0x51,0x38,0xd5] -; CHECK: mrs x3, ADFSR_EL2 ; encoding: [0x03,0x51,0x3c,0xd5] -; CHECK: mrs x3, ADFSR_EL3 ; encoding: [0x03,0x51,0x3e,0xd5] +; CHECK: mrs x3, AFSR0_EL2 ; encoding: [0x03,0x51,0x3c,0xd5] +; CHECK: mrs x3, AFSR0_EL3 ; encoding: [0x03,0x51,0x3e,0xd5] ; CHECK: mrs x3, AIDR_EL1 ; encoding: [0xe3,0x00,0x39,0xd5] ; CHECK: mrs x3, AFSR1_EL1 ; encoding: [0x23,0x51,0x38,0xd5] -; CHECK: mrs x3, AIFSR_EL2 ; encoding: [0x23,0x51,0x3c,0xd5] -; CHECK: mrs x3, AIFSR_EL3 ; encoding: [0x23,0x51,0x3e,0xd5] +; CHECK: mrs x3, AFSR1_EL2 ; encoding: [0x23,0x51,0x3c,0xd5] +; CHECK: mrs x3, AFSR1_EL3 ; encoding: [0x23,0x51,0x3e,0xd5] ; CHECK: mrs x3, AMAIR_EL1 ; encoding: [0x03,0xa3,0x38,0xd5] ; CHECK: mrs x3, AMAIR_EL2 ; encoding: [0x03,0xa3,0x3c,0xd5] ; CHECK: mrs x3, AMAIR_EL3 ; encoding: [0x03,0xa3,0x3e,0xd5] @@ -488,7 +435,7 @@ foo: ; CHECK: mrs x3, CPTR_EL3 ; encoding: [0x43,0x11,0x3e,0xd5] ; CHECK: mrs x3, CSSELR_EL1 ; encoding: [0x03,0x00,0x3a,0xd5] ; CHECK: mrs x3, CTR_EL0 ; encoding: [0x23,0x00,0x3b,0xd5] -; CHECK: mrs x3, CurrentEL ; encoding: [0x43,0x42,0x38,0xd5] +; CHECK: mrs x3, CURRENTEL ; encoding: [0x43,0x42,0x38,0xd5] ; CHECK: mrs x3, DACR32_EL2 ; encoding: [0x03,0x30,0x3c,0xd5] ; CHECK: mrs x3, DCZID_EL0 ; encoding: [0xe3,0x00,0x3b,0xd5] ; CHECK: mrs x3, REVIDR_EL1 ; encoding: [0xc3,0x00,0x38,0xd5] @@ -556,12 +503,11 @@ foo: ; CHECK: mrs x3, MDCCINT_EL1 ; encoding: [0x03,0x02,0x30,0xd5] ; CHECK: mrs x3, DBGDTR_EL0 ; encoding: [0x03,0x04,0x33,0xd5] ; CHECK: mrs x3, DBGDTRRX_EL0 ; encoding: [0x03,0x05,0x33,0xd5] -; CHECK: mrs x3, DBGDTRRX_EL0 ; encoding: [0x03,0x05,0x33,0xd5] ; CHECK: mrs x3, DBGVCR32_EL2 ; encoding: [0x03,0x07,0x34,0xd5] ; CHECK: mrs x3, OSDTRRX_EL1 ; encoding: [0x43,0x00,0x30,0xd5] ; CHECK: mrs x3, MDSCR_EL1 ; encoding: [0x43,0x02,0x30,0xd5] ; CHECK: mrs x3, OSDTRTX_EL1 ; encoding: [0x43,0x03,0x30,0xd5] -; CHECK: mrs x3, OSECCR_EL11 ; encoding: [0x43,0x06,0x30,0xd5] +; CHECK: mrs x3, OSECCR_EL1 ; encoding: [0x43,0x06,0x30,0xd5] ; CHECK: mrs x3, DBGBVR0_EL1 ; encoding: [0x83,0x00,0x30,0xd5] ; CHECK: mrs x3, DBGBVR1_EL1 ; encoding: [0x83,0x01,0x30,0xd5] ; CHECK: mrs x3, DBGBVR2_EL1 ; encoding: [0x83,0x02,0x30,0xd5] @@ -627,30 +573,28 @@ foo: ; CHECK: mrs x3, DBGWCR14_EL1 ; encoding: [0xe3,0x0e,0x30,0xd5] ; CHECK: mrs x3, DBGWCR15_EL1 ; encoding: [0xe3,0x0f,0x30,0xd5] ; CHECK: mrs x3, MDRAR_EL1 ; encoding: [0x03,0x10,0x30,0xd5] -; CHECK: mrs x3, OSLAR_EL1 ; encoding: [0x83,0x10,0x30,0xd5] ; CHECK: mrs x3, OSLSR_EL1 ; encoding: [0x83,0x11,0x30,0xd5] ; CHECK: mrs x3, OSDLR_EL1 ; encoding: [0x83,0x13,0x30,0xd5] ; CHECK: mrs x3, DBGPRCR_EL1 ; encoding: [0x83,0x14,0x30,0xd5] ; CHECK: mrs x3, DBGCLAIMSET_EL1 ; encoding: [0xc3,0x78,0x30,0xd5] ; CHECK: mrs x3, DBGCLAIMCLR_EL1 ; encoding: [0xc3,0x79,0x30,0xd5] ; CHECK: mrs x3, DBGAUTHSTATUS_EL1 ; encoding: [0xc3,0x7e,0x30,0xd5] -; CHECK: mrs x3, DBGDEVID2 ; encoding: [0xe3,0x70,0x30,0xd5] -; CHECK: mrs x3, DBGDEVID1 ; encoding: [0xe3,0x71,0x30,0xd5] -; CHECK: mrs x3, DBGDEVID0 ; encoding: [0xe3,0x72,0x30,0xd5] -; CHECK: mrs x1, S2_2_C4_C6_4 ; encoding: [0x81,0x46,0x32,0xd5] -; CHECK: mrs x3, S2_3_C2_C1_4 ; encoding: [0x83,0x21,0x33,0xd5] -; CHECK: mrs x3, S2_3_C2_C1_4 ; encoding: [0x83,0x21,0x33,0xd5] +; CHECK: mrs x1, S3_2_C15_C6_4 ; encoding: [0x81,0xf6,0x3a,0xd5] +; CHECK: mrs x3, S3_3_C11_C1_4 ; encoding: [0x83,0xb1,0x3b,0xd5] +; CHECK: mrs x3, S3_3_C11_C1_4 ; encoding: [0x83,0xb1,0x3b,0xd5] msr RMR_EL3, x0 msr RMR_EL2, x0 msr RMR_EL1, x0 - msr CPM_IOACC_CTL_EL3, x0 - + msr OSLAR_EL1, x3 + msr DBGDTRTX_EL0, x3 + ; CHECK: msr RMR_EL3, x0 ; encoding: [0x40,0xc0,0x1e,0xd5] -; CHECK: msr RMR_EL2, x0 ; encoding: [0x40,0xc0,0x1a,0xd5] -; CHECK: msr RMR_EL1, x0 ; encoding: [0x40,0xc0,0x19,0xd5] -; CHECK: msr CPM_IOACC_CTL_EL3, x0 ; encoding: [0x00,0xf2,0x1f,0xd5] - +; CHECK: msr RMR_EL2, x0 ; encoding: [0x40,0xc0,0x1c,0xd5] +; CHECK: msr RMR_EL1, x0 ; encoding: [0x40,0xc0,0x18,0xd5] +; CHECK: msr OSLAR_EL1, x3 ; encoding: [0x83,0x10,0x10,0xd5] +; CHECK: msr DBGDTRTX_EL0, x3 ; encoding: [0x03,0x05,0x13,0xd5] + mrs x0, ID_PFR0_EL1 mrs x0, ID_PFR1_EL1 mrs x0, ID_DFR0_EL1 diff --git a/test/MC/AArch64/arm64-target-specific-sysreg.s b/test/MC/AArch64/arm64-target-specific-sysreg.s new file mode 100644 index 0000000..05cea3a --- /dev/null +++ b/test/MC/AArch64/arm64-target-specific-sysreg.s @@ -0,0 +1,10 @@ +// RUN: not llvm-mc -triple arm64 -mcpu=generic -show-encoding < %s 2>&1 | \ +// RUN: FileCheck %s --check-prefix=CHECK-GENERIC +// +// RUN: llvm-mc -triple arm64 -mcpu=cyclone -show-encoding < %s 2>&1 | \ +// RUN: FileCheck %s --check-prefix=CHECK-CYCLONE + +msr CPM_IOACC_CTL_EL3, x0 + +// CHECK-GENERIC: error: expected writable system register or pstate +// CHECK-CYCLONE: msr CPM_IOACC_CTL_EL3, x0 // encoding: [0x00,0xf2,0x1f,0xd5] diff --git a/test/MC/ARM64/tls-modifiers-darwin.s b/test/MC/AArch64/arm64-tls-modifiers-darwin.s index 6478d26..8ff07cd 100644 --- a/test/MC/ARM64/tls-modifiers-darwin.s +++ b/test/MC/AArch64/arm64-tls-modifiers-darwin.s @@ -3,10 +3,10 @@ adrp x2, _var@TLVPPAGE ldr x0, [x15, _var@TLVPPAGEOFF] - add lr, x0, _var@TLVPPAGEOFF + add x30, x0, _var@TLVPPAGEOFF ; CHECK: adrp x2, _var@TLVPPAG ; CHECK: ldr x0, [x15, _var@TLVPPAGEOFF] -; CHECK: add lr, x0, _var@TLVPPAGEOFF +; CHECK: add x30, x0, _var@TLVPPAGEOFF ; CHECK-OBJ: 8 ARM64_RELOC_TLVP_LOAD_PAGEOFF12 _var ; CHECK-OBJ: 4 ARM64_RELOC_TLVP_LOAD_PAGEOFF12 _var diff --git a/test/MC/ARM64/tls-relocs.s b/test/MC/AArch64/arm64-tls-relocs.s index 7e8b754..96c2b55 100644 --- a/test/MC/ARM64/tls-relocs.s +++ b/test/MC/AArch64/arm64-tls-relocs.s @@ -9,14 +9,14 @@ movz x15, #:gottprel_g1:var // CHECK: movz x15, #:gottprel_g1:var // encoding: [0bAAA01111,A,0b101AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_aarch64_movw // CHECK-ELF: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 [[VARSYM:[^ ]+]] movk x13, #:gottprel_g0_nc:var // CHECK: movk x13, #:gottprel_g0_nc:var // encoding: [0bAAA01101,A,0b100AAAAA,0xf2] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC [[VARSYM]] @@ -25,11 +25,11 @@ ldr x10, [x0, #:gottprel_lo12:var] ldr x9, :gottprel:var // CHECK: adrp x11, :gottprel:var // encoding: [0x0b'A',A,A,0x90'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_arm64_pcrel_adrp_imm21 +// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_pcrel_adrp_imm21 // CHECK: ldr x10, [x0, :gottprel_lo12:var] // encoding: [0x0a,0bAAAAAA00,0b01AAAAAA,0xf9] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8 +// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 // CHECK: ldr x9, :gottprel:var // encoding: [0bAAA01001,A,A,0x58] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_arm64_pcrel_imm19 +// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_ldr_pcrel_imm19 // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC [[VARSYM]] @@ -43,9 +43,9 @@ movz x3, #:tprel_g2:var movn x4, #:tprel_g2:var // CHECK: movz x3, #:tprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_aarch64_movw // CHECK: movn x4, #:tprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]] @@ -55,11 +55,11 @@ movn x6, #:tprel_g1:var movz w7, #:tprel_g1:var // CHECK: movz x5, #:tprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw // CHECK: movn x6, #:tprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw // CHECK: movz w7, #:tprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]] @@ -69,9 +69,9 @@ movk x9, #:tprel_g1_nc:var movk w10, #:tprel_g1_nc:var // CHECK: movk x9, #:tprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_aarch64_movw // CHECK: movk w10, #:tprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]] @@ -81,11 +81,11 @@ movn x12, #:tprel_g0:var movz w13, #:tprel_g0:var // CHECK: movz x11, #:tprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw // CHECK: movn x12, #:tprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw // CHECK: movz w13, #:tprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]] @@ -95,9 +95,9 @@ movk x15, #:tprel_g0_nc:var movk w16, #:tprel_g0_nc:var // CHECK: movk x15, #:tprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw // CHECK: movk w16, #:tprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]] @@ -105,24 +105,24 @@ add x21, x22, #:tprel_lo12:var // CHECK: add x21, x22, :tprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_add_imm12 +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_ADD_TPREL_LO12 [[VARSYM]] add x25, x26, #:tprel_lo12_nc:var // CHECK: add x25, x26, :tprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_add_imm12 +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]] ldrb w29, [x30, #:tprel_lo12:var] ldrsb x29, [x28, #:tprel_lo12_nc:var] -// CHECK: ldrb w29, [lr, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1 -// CHECK: ldrsb fp, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1 +// CHECK: ldrb w29, [x30, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1 +// CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39] +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1 // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST8_TPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC [[VARSYM]] @@ -131,9 +131,9 @@ strh w27, [x26, #:tprel_lo12:var] ldrsh x25, [x24, #:tprel_lo12_nc:var] // CHECK: strh w27, [x26, :tprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale2 +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2 // CHECK: ldrsh x25, [x24, :tprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale2 +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2 // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST16_TPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC [[VARSYM]] @@ -142,9 +142,9 @@ ldr w23, [x22, #:tprel_lo12:var] ldrsw x21, [x20, #:tprel_lo12_nc:var] // CHECK: ldr w23, [x22, :tprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale4 +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4 // CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale4 +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4 // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST32_TPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC [[VARSYM]] @@ -152,9 +152,9 @@ ldr x19, [x18, #:tprel_lo12:var] str x17, [x16, #:tprel_lo12_nc:var] // CHECK: ldr x19, [x18, :tprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8 +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 // CHECK: str x17, [x16, :tprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale8 +// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8 // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST64_TPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC [[VARSYM]] @@ -167,9 +167,9 @@ movz x3, #:dtprel_g2:var movn x4, #:dtprel_g2:var // CHECK: movz x3, #:dtprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw // CHECK: movn x4, #:dtprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]] @@ -179,11 +179,11 @@ movn x6, #:dtprel_g1:var movz w7, #:dtprel_g1:var // CHECK: movz x5, #:dtprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw // CHECK: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw // CHECK: movz w7, #:dtprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] @@ -193,9 +193,9 @@ movk x9, #:dtprel_g1_nc:var movk w10, #:dtprel_g1_nc:var // CHECK: movk x9, #:dtprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_aarch64_movw // CHECK: movk w10, #:dtprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]] @@ -205,11 +205,11 @@ movn x12, #:dtprel_g0:var movz w13, #:dtprel_g0:var // CHECK: movz x11, #:dtprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw // CHECK: movn x12, #:dtprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw // CHECK: movz w13, #:dtprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] @@ -219,9 +219,9 @@ movk x15, #:dtprel_g0_nc:var movk w16, #:dtprel_g0_nc:var // CHECK: movk x15, #:dtprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw // CHECK: movk w16, #:dtprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_arm64_movw +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]] @@ -229,24 +229,24 @@ add x21, x22, #:dtprel_lo12:var // CHECK: add x21, x22, :dtprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_add_imm12 +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_ADD_DTPREL_LO12 [[VARSYM]] add x25, x26, #:dtprel_lo12_nc:var // CHECK: add x25, x26, :dtprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_add_imm12 +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]] ldrb w29, [x30, #:dtprel_lo12:var] ldrsb x29, [x28, #:dtprel_lo12_nc:var] -// CHECK: ldrb w29, [lr, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1 -// CHECK: ldrsb fp, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1 +// CHECK: ldrb w29, [x30, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1 +// CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39] +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1 // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC [[VARSYM]] @@ -255,9 +255,9 @@ strh w27, [x26, #:dtprel_lo12:var] ldrsh x25, [x24, #:dtprel_lo12_nc:var] // CHECK: strh w27, [x26, :dtprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale2 +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2 // CHECK: ldrsh x25, [x24, :dtprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale2 +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2 // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST16_DTPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC [[VARSYM]] @@ -266,9 +266,9 @@ ldr w23, [x22, #:dtprel_lo12:var] ldrsw x21, [x20, #:dtprel_lo12_nc:var] // CHECK: ldr w23, [x22, :dtprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale4 +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4 // CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale4 +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4 // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST32_DTPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC [[VARSYM]] @@ -276,9 +276,9 @@ ldr x19, [x18, #:dtprel_lo12:var] str x17, [x16, #:dtprel_lo12_nc:var] // CHECK: ldr x19, [x18, :dtprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale8 +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 // CHECK: str x17, [x16, :dtprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale8 +// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8 // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST64_DTPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC [[VARSYM]] @@ -294,13 +294,13 @@ blr x3 // CHECK: adrp x8, :tlsdesc:var // encoding: [0x08'A',A,A,0x90'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_arm64_pcrel_adrp_imm21 +// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_aarch64_pcrel_adrp_imm21 // CHECK: ldr x7, [x6, :tlsdesc_lo12:var] // encoding: [0xc7,0bAAAAAA00,0b01AAAAAA,0xf9] -// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_arm64_ldst_imm12_scale8 +// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 // CHECK: add x5, x4, :tlsdesc_lo12:var // encoding: [0x85,0bAAAAAA00,0b00AAAAAA,0x91] -// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_arm64_add_imm12 +// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_add_imm12 // CHECK: .tlsdesccall var // encoding: [] -// CHECK-NEXT: // fixup A - offset: 0, value: var, kind: fixup_arm64_tlsdesc_call +// CHECK-NEXT: // fixup A - offset: 0, value: var, kind: fixup_aarch64_tlsdesc_call // CHECK: blr x3 // encoding: [0x60,0x00,0x3f,0xd6] @@ -313,7 +313,7 @@ // CHECK-ELF: Symbols [ // CHECK-ELF: Symbol { -// CHECK-ELF: Name: var (6) +// CHECK-ELF: Name: var // CHECK-ELF-NEXT: Value: // CHECK-ELF-NEXT: Size: // CHECK-ELF-NEXT: Binding: Global diff --git a/test/MC/AArch64/arm64-v128_lo-diagnostics.s b/test/MC/AArch64/arm64-v128_lo-diagnostics.s new file mode 100644 index 0000000..ffe29cf --- /dev/null +++ b/test/MC/AArch64/arm64-v128_lo-diagnostics.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -triple arm64 -mattr=neon %s 2> %t > /dev/null +// RUN: FileCheck %s < %t + + sqrdmulh v0.8h, v1.8h, v16.h[0] +// CHECK: error: invalid operand for instruction + + sqrdmulh h0, h1, v16.h[0] +// CHECK: error: invalid operand for instruction + + sqdmull2 v0.4h, v1.8h, v16.h[0] +// CHECK: error: invalid operand for instruction diff --git a/test/MC/ARM64/variable-exprs.s b/test/MC/AArch64/arm64-variable-exprs.s index 0120442..0120442 100644 --- a/test/MC/ARM64/variable-exprs.s +++ b/test/MC/AArch64/arm64-variable-exprs.s diff --git a/test/MC/AArch64/arm64-vector-lists.s b/test/MC/AArch64/arm64-vector-lists.s new file mode 100644 index 0000000..a9b2d19 --- /dev/null +++ b/test/MC/AArch64/arm64-vector-lists.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple arm64 -mattr=neon -show-encoding < %s 2>%t | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s + + ST4 {v0.8B-v3.8B}, [x0] + ST4 {v0.4H-v3.4H}, [x0] + +// CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x00,0x0c] +// CHECK: st4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0] // encoding: [0x00,0x04,0x00,0x0c] + + ST4 {v0.8B-v4.8B}, [x0] + ST4 {v0.8B-v3.8B,v4.8B}, [x0] + ST4 {v0.8B-v3.8H}, [x0] + ST4 {v0.8B-v3.16B}, [x0] + ST4 {v0.8B-},[x0] + +// CHECK-ERRORS: error: invalid number of vectors +// CHECK-ERRORS: error: '}' expected +// CHECK-ERRORS: error: mismatched register size suffix +// CHECK-ERRORS: error: mismatched register size suffix +// CHECK-ERRORS: error: vector register expected diff --git a/test/MC/AArch64/arm64-verbose-vector-case.s b/test/MC/AArch64/arm64-verbose-vector-case.s new file mode 100644 index 0000000..6f0a381 --- /dev/null +++ b/test/MC/AArch64/arm64-verbose-vector-case.s @@ -0,0 +1,19 @@ +// RUN: llvm-mc -triple arm64 -mattr=crypto -show-encoding < %s | FileCheck %s + +pmull v8.8h, v8.8b, v8.8b +pmull2 v8.8h, v8.16b, v8.16b +pmull v8.1q, v8.1d, v8.1d +pmull2 v8.1q, v8.2d, v8.2d +// CHECK: pmull v8.8h, v8.8b, v8.8b // encoding: [0x08,0xe1,0x28,0x0e] +// CHECK: pmull2 v8.8h, v8.16b, v8.16b // encoding: [0x08,0xe1,0x28,0x4e] +// CHECK: pmull v8.1q, v8.1d, v8.1d // encoding: [0x08,0xe1,0xe8,0x0e] +// CHECK: pmull2 v8.1q, v8.2d, v8.2d // encoding: [0x08,0xe1,0xe8,0x4e] + +pmull v8.8H, v8.8B, v8.8B +pmull2 v8.8H, v8.16B, v8.16B +pmull v8.1Q, v8.1D, v8.1D +pmull2 v8.1Q, v8.2D, v8.2D +// CHECK: pmull v8.8h, v8.8b, v8.8b // encoding: [0x08,0xe1,0x28,0x0e] +// CHECK: pmull2 v8.8h, v8.16b, v8.16b // encoding: [0x08,0xe1,0x28,0x4e] +// CHECK: pmull v8.1q, v8.1d, v8.1d // encoding: [0x08,0xe1,0xe8,0x0e] +// CHECK: pmull2 v8.1q, v8.2d, v8.2d // encoding: [0x08,0xe1,0xe8,0x4e] diff --git a/test/MC/AArch64/basic-a64-diagnostics.s b/test/MC/AArch64/basic-a64-diagnostics.s index 792538c..a4a3b13 100644 --- a/test/MC/AArch64/basic-a64-diagnostics.s +++ b/test/MC/AArch64/basic-a64-diagnostics.s @@ -1,5 +1,5 @@ // RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t -// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s +// RUN: FileCheck --check-prefix=CHECK-ERROR --check-prefix=CHECK-ERROR-ARM64 < %t %s //------------------------------------------------------------------------------ // Add/sub (extended register) @@ -83,9 +83,9 @@ // CHECK-ERROR: error: expected compatible register, symbol or integer in range [0, 4095] // CHECK-ERROR-NEXT: add w4, w5, #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected compatible register, symbol or integer in range [0, 4095] -// CHECK-ERROR-NEXT: add w5, w6, #0x1000 -// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: expected compatible register, symbol or integer in range [0, 4095] +// CHECK-ERROR-AARCH64-NEXT: add w5, w6, #0x1000 +// CHECK-ERROR-AARCH64-NEXT: ^ // CHECK-ERROR-NEXT: error: expected compatible register, symbol or integer in range [0, 4095] // CHECK-ERROR-NEXT: add w4, w5, #-1, lsl #12 // CHECK-ERROR-NEXT: ^ @@ -141,9 +141,9 @@ // Out of range immediate adds w0, w5, #0x10000 -// CHECK-ERROR: error: expected compatible register, symbol or integer in range [0, 4095] -// CHECK-ERROR-NEXT: adds w0, w5, #0x10000 -// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-AARCH64: error: expected compatible register, symbol or integer in range [0, 4095] +// CHECK-ERROR-AARCH64-NEXT: adds w0, w5, #0x10000 +// CHECK-ERROR-AARCH64-NEXT: ^ // Wn|WSP should be in second place adds w4, wzr, #0x123 @@ -750,10 +750,10 @@ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: sbfm w3, wsp, #1, #9 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: sbfm x9, x5, #-1, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: sbfm x9, x5, #0, #-1 // CHECK-ERROR-NEXT: ^ @@ -761,16 +761,16 @@ sbfm w7, w11, #19, #32 sbfm x29, x30, #64, #0 sbfm x10, x20, #63, #64 -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: sbfm w3, w5, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: sbfm w7, w11, #19, #32 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: sbfm x29, x30, #64, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: sbfm x10, x20, #63, #64 // CHECK-ERROR-NEXT: ^ @@ -778,16 +778,16 @@ ubfm w7, w11, #19, #32 ubfm x29, x30, #64, #0 ubfm x10, x20, #63, #64 -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ubfm w3, w5, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ubfm w7, w11, #19, #32 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: ubfm x29, x30, #64, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: ubfm x10, x20, #63, #64 // CHECK-ERROR-NEXT: ^ @@ -795,31 +795,31 @@ bfm w7, w11, #19, #32 bfm x29, x30, #64, #0 bfm x10, x20, #63, #64 -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: bfm w3, w5, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: bfm w7, w11, #19, #32 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: bfm x29, x30, #64, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: bfm x10, x20, #63, #64 // CHECK-ERROR-NEXT: ^ sxtb x3, x2 sxth xzr, xzr sxtw x3, x5 -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR-NEXT: sxtb x3, x2 -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: sxth xzr, xzr -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: sxtw x3, x5 -// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-AARCH64: error: invalid operand for instruction +// CHECK-ERROR-AARCH64-NEXT: sxtb x3, x2 +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: invalid operand for instruction +// CHECK-ERROR-AARCH64-NEXT: sxth xzr, xzr +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: invalid operand for instruction +// CHECK-ERROR-AARCH64-NEXT: sxtw x3, x5 +// CHECK-ERROR-AARCH64-NEXT: ^ uxtb x3, x12 uxth x5, x9 @@ -832,9 +832,9 @@ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: uxth x5, x9 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: invalid instruction -// CHECK-ERROR-NEXT: uxtw x3, x5 -// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: invalid instruction +// CHECK-ERROR-AARCH64-NEXT: uxtw x3, x5 +// CHECK-ERROR-AARCH64-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: uxtb x2, sp // CHECK-ERROR-NEXT: ^ @@ -853,13 +853,13 @@ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: asr sp, x2, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: asr x25, x26, #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: asr x25, x26, #64 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: asr w9, w8, #32 // CHECK-ERROR-NEXT: ^ @@ -869,18 +869,19 @@ sbfiz w11, w12, #32, #0 sbfiz w9, w10, #10, #23 sbfiz x3, x5, #12, #53 - sbfiz sp, x3, #5, #6 - sbfiz w3, wsp, #7, #8 -// CHECK-ERROR: error: expected integer in range [<lsb>, 31] + sbfiz sp, x3, #7, #6 + sbfiz w3, wsp, #10, #8 +// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: sbfiz w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: sbfiz wsp, w9, #0, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: sbfiz w9, w10, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: sbfiz w11, w12, #32, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: requested insert overflows register @@ -890,10 +891,10 @@ // CHECK-ERROR-NEXT: sbfiz x3, x5, #12, #53 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: sbfiz sp, x3, #5, #6 +// CHECK-ERROR-NEXT: sbfiz sp, x3, #7, #6 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: sbfiz w3, wsp, #7, #8 +// CHECK-ERROR-NEXT: sbfiz w3, wsp, #10, #8 // CHECK-ERROR-NEXT: ^ sbfx w1, w2, #0, #0 @@ -902,18 +903,19 @@ sbfx w11, w12, #32, #0 sbfx w9, w10, #10, #23 sbfx x3, x5, #12, #53 - sbfx sp, x3, #5, #6 - sbfx w3, wsp, #7, #8 -// CHECK-ERROR: error: expected integer in range [<lsb>, 31] + sbfx sp, x3, #7, #6 + sbfx w3, wsp, #10, #8 +// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: sbfx w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: sbfx wsp, w9, #0, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: sbfx w9, w10, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: sbfx w11, w12, #32, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: requested extract overflows register @@ -923,10 +925,10 @@ // CHECK-ERROR-NEXT: sbfx x3, x5, #12, #53 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: sbfx sp, x3, #5, #6 +// CHECK-ERROR-NEXT: sbfx sp, x3, #7, #6 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: sbfx w3, wsp, #7, #8 +// CHECK-ERROR-NEXT: sbfx w3, wsp, #10, #8 // CHECK-ERROR-NEXT: ^ bfi w1, w2, #0, #0 @@ -935,18 +937,19 @@ bfi w11, w12, #32, #0 bfi w9, w10, #10, #23 bfi x3, x5, #12, #53 - bfi sp, x3, #5, #6 - bfi w3, wsp, #7, #8 -// CHECK-ERROR: error: expected integer in range [<lsb>, 31] + bfi sp, x3, #7, #6 + bfi w3, wsp, #10, #8 +// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: bfi w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: bfi wsp, w9, #0, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: bfi w9, w10, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: bfi w11, w12, #32, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: requested insert overflows register @@ -956,10 +959,10 @@ // CHECK-ERROR-NEXT: bfi x3, x5, #12, #53 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: bfi sp, x3, #5, #6 +// CHECK-ERROR-NEXT: bfi sp, x3, #7, #6 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: bfi w3, wsp, #7, #8 +// CHECK-ERROR-NEXT: bfi w3, wsp, #10, #8 // CHECK-ERROR-NEXT: ^ bfxil w1, w2, #0, #0 @@ -968,18 +971,19 @@ bfxil w11, w12, #32, #0 bfxil w9, w10, #10, #23 bfxil x3, x5, #12, #53 - bfxil sp, x3, #5, #6 - bfxil w3, wsp, #7, #8 -// CHECK-ERROR: error: expected integer in range [<lsb>, 31] + bfxil sp, x3, #7, #6 + bfxil w3, wsp, #10, #8 +// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: bfxil w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: bfxil wsp, w9, #0, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: bfxil w9, w10, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: bfxil w11, w12, #32, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: requested extract overflows register @@ -989,10 +993,10 @@ // CHECK-ERROR-NEXT: bfxil x3, x5, #12, #53 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: bfxil sp, x3, #5, #6 +// CHECK-ERROR-NEXT: bfxil sp, x3, #7, #6 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: bfxil w3, wsp, #7, #8 +// CHECK-ERROR-NEXT: bfxil w3, wsp, #10, #8 // CHECK-ERROR-NEXT: ^ ubfiz w1, w2, #0, #0 @@ -1001,18 +1005,19 @@ ubfiz w11, w12, #32, #0 ubfiz w9, w10, #10, #23 ubfiz x3, x5, #12, #53 - ubfiz sp, x3, #5, #6 - ubfiz w3, wsp, #7, #8 -// CHECK-ERROR: error: expected integer in range [<lsb>, 31] + ubfiz sp, x3, #7, #6 + ubfiz w3, wsp, #10, #8 +// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: ubfiz w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ubfiz wsp, w9, #0, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ubfiz w9, w10, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ubfiz w11, w12, #32, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: requested insert overflows register @@ -1022,10 +1027,10 @@ // CHECK-ERROR-NEXT: ubfiz x3, x5, #12, #53 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: ubfiz sp, x3, #5, #6 +// CHECK-ERROR-NEXT: ubfiz sp, x3, #7, #6 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: ubfiz w3, wsp, #7, #8 +// CHECK-ERROR-NEXT: ubfiz w3, wsp, #10, #8 // CHECK-ERROR-NEXT: ^ ubfx w1, w2, #0, #0 @@ -1034,18 +1039,19 @@ ubfx w11, w12, #32, #0 ubfx w9, w10, #10, #23 ubfx x3, x5, #12, #53 - ubfx sp, x3, #5, #6 - ubfx w3, wsp, #7, #8 -// CHECK-ERROR: error: expected integer in range [<lsb>, 31] + ubfx sp, x3, #7, #6 + ubfx w3, wsp, #10, #8 +// CHECK-ERROR-AARCH64: error: expected integer in range [<lsb>, 31] +// CHECK-ERROR-ARM64: error: expected integer in range [1, 32] // CHECK-ERROR-NEXT: ubfx w1, w2, #0, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ubfx wsp, w9, #0, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ubfx w9, w10, #32, #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ubfx w11, w12, #32, #0 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: requested extract overflows register @@ -1055,10 +1061,10 @@ // CHECK-ERROR-NEXT: ubfx x3, x5, #12, #53 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: ubfx sp, x3, #5, #6 +// CHECK-ERROR-NEXT: ubfx sp, x3, #7, #6 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: ubfx w3, wsp, #7, #8 +// CHECK-ERROR-NEXT: ubfx w3, wsp, #10, #8 // CHECK-ERROR-NEXT: ^ //------------------------------------------------------------------------------ @@ -1125,16 +1131,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmp wsp, #4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmp w25, #-1, #15, hs // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmp w3, #32, #0, ge // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp w19, #5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp w20, #7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1146,16 +1152,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmp sp, #4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmp x25, #-1, #15, hs // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmp x3, #32, #0, ge // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp x19, #5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp x20, #7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1167,16 +1173,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmn wsp, #4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmn w25, #-1, #15, hs // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmn w3, #32, #0, ge // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn w19, #5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn w20, #7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1188,16 +1194,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmn sp, #4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmn x25, #-1, #15, hs // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmn x3, #32, #0, ge // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn x19, #5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn x20, #7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1212,13 +1218,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmp wsp, w4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmp w3, wsp, #0, ge // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp w19, w5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp w20, w7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1229,13 +1235,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmp sp, x4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmp x25, sp, #15, hs // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp x19, x5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmp x20, x7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1246,13 +1252,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmn wsp, w4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmn w25, wsp, #15, hs // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn w19, w5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn w20, w7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1263,13 +1269,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ccmn sp, x4, #2, ne // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ccmn x25, sp, #15, hs // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn x19, x5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: ccmn x20, x7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1418,16 +1424,16 @@ hlt #65536 dcps4 #43 dcps4 -// CHECK-ERROR: error: expected integer in range [0, 65535] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: svc #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: hlt #65536 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: invalid instruction +// CHECK-ERROR-NEXT: error: {{invalid instruction|unrecognized instruction mnemonic}} // CHECK-ERROR-NEXT: dcps4 #43 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: invalid instruction +// CHECK-ERROR-NEXT: error: {{invalid instruction|unrecognized instruction mnemonic}} // CHECK-ERROR-NEXT: dcps4 // CHECK-ERROR-NEXT: ^ @@ -1437,28 +1443,28 @@ extr w2, w20, w30, #-1 extr w9, w19, w20, #32 -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: extr w2, w20, w30, #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: extr w9, w19, w20, #32 // CHECK-ERROR-NEXT: ^ extr x10, x15, x20, #-1 extr x20, x25, x30, #64 -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: extr x10, x15, x20, #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: extr x20, x25, x30, #64 // CHECK-ERROR-NEXT: ^ ror w9, w10, #32 ror x10, x11, #64 -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: ror w9, w10, #32 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: ror x10, x11, #64 // CHECK-ERROR-NEXT: ^ @@ -1467,7 +1473,8 @@ //------------------------------------------------------------------------------ fcmp s3, d2 -// CHECK-ERROR: error: expected floating-point constant #0.0 +// CHECK-ERROR-AARCH64: error: expected floating-point constant #0.0 +// CHECK-ERROR-ARM64: error: invalid operand for instruction // CHECK-ERROR-NEXT: fcmp s3, d2 // CHECK-ERROR-NEXT: ^ @@ -1494,37 +1501,37 @@ fccmp s19, s5, #-1, lt fccmp s20, s7, #16, hs -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmp s19, s5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmp s20, s7, #16, hs // CHECK-ERROR-NEXT: ^ fccmp d19, d5, #-1, lt fccmp d20, d7, #16, hs -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmp d19, d5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmp d20, d7, #16, hs // CHECK-ERROR-NEXT: ^ fccmpe s19, s5, #-1, lt fccmpe s20, s7, #16, hs -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmpe s19, s5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmpe s20, s7, #16, hs // CHECK-ERROR-NEXT: ^ fccmpe d19, d5, #-1, lt fccmpe d20, d7, #16, hs -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmpe d19, d5, #-1, lt // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: fccmpe d20, d7, #16, hs // CHECK-ERROR-NEXT: ^ @@ -1604,10 +1611,10 @@ fcvtzs w13, s31, #0 fcvtzs w19, s20, #33 fcvtzs wsp, s19, #14 -// CHECK-ERROR-NEXT: error: expected integer in range [1, 32] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR-NEXT: fcvtzs w13, s31, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [1, 32] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR-NEXT: fcvtzs w19, s20, #33 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -1617,10 +1624,10 @@ fcvtzs x13, s31, #0 fcvtzs x19, s20, #65 fcvtzs sp, s19, #14 -// CHECK-ERROR-NEXT: error: expected integer in range [1, 64] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR-NEXT: fcvtzs x13, s31, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [1, 64] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR-NEXT: fcvtzs x19, s20, #65 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -1630,10 +1637,10 @@ fcvtzu w13, s31, #0 fcvtzu w19, s20, #33 fcvtzu wsp, s19, #14 -// CHECK-ERROR-NEXT: error: expected integer in range [1, 32] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR-NEXT: fcvtzu w13, s31, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [1, 32] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR-NEXT: fcvtzu w19, s20, #33 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -1643,10 +1650,10 @@ fcvtzu x13, s31, #0 fcvtzu x19, s20, #65 fcvtzu sp, s19, #14 -// CHECK-ERROR-NEXT: error: expected integer in range [1, 64] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR-NEXT: fcvtzu x13, s31, #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [1, 64] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR-NEXT: fcvtzu x19, s20, #65 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -1730,9 +1737,9 @@ ;; No particular reason, but a striking omission fmov d0, #0.0 -// CHECK-ERROR: error: expected compatible register or floating-point constant -// CHECK-ERROR-NEXT: fmov d0, #0.0 -// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-AARCH64: error: expected compatible register or floating-point constant +// CHECK-ERROR-AARCH64-NEXT: fmov d0, #0.0 +// CHECK-ERROR-AARCH64-NEXT: ^ //------------------------------------------------------------------------------ // Floating-point <-> integer conversion @@ -1746,10 +1753,12 @@ // CHECK-ERROR: error: expected lane specifier '[1]' // CHECK-ERROR-NEXT: fmov x3, v0.d[0] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: lane number incompatible with layout +// CHECK-ERROR-AARCH64-NEXT: error: lane number incompatible with layout +// CHECK-ERROR-ARM64-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: fmov v29.1d[1], x2 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: lane number incompatible with layout +// CHECK-ERROR-AARCH64-NEXT: error: lane number incompatible with layout +// CHECK-ERROR-ARM64-NEXT: error: expected lane specifier '[1]' // CHECK-ERROR-NEXT: fmov x7, v0.d[2] // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -1789,10 +1798,11 @@ // Load/store exclusive //------------------------------------------------------------------------------ - stxrb w2, x3, [x4, #20] + stxrb w2, w3, [x4, #20] stlxrh w10, w11, [w2] -// CHECK-ERROR: error: expected '#0' -// CHECK-ERROR-NEXT: stxrb w2, x3, [x4, #20] +// CHECK-ERROR-AARCH64: error: expected '#0' +// CHECK-ERROR-ARM64: error: index must be absent or #0 +// CHECK-ERROR-NEXT: stxrb w2, w3, [x4, #20] // CHECK-ERROR-NEXT: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: stlxrh w10, w11, [w2] @@ -1831,16 +1841,16 @@ sturh w17, [x1, #256] ldursw x20, [x1, #256] ldur x12, [sp, #256] -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldurb w2, [sp, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: sturh w17, [x1, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldursw x20, [x1, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldur x12, [sp, #256] // CHECK-ERROR-NEXT: ^ @@ -1849,19 +1859,19 @@ ldursb x9, [sp, #-257] ldur w2, [x30, #-257] stur q9, [x20, #-257] -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: stur h2, [x2, #-257] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: stur b2, [x2, #-257] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldursb x9, [sp, #-257] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldur w2, [x30, #-257] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: stur q9, [x20, #-257] // CHECK-ERROR-NEXT: ^ @@ -1875,12 +1885,13 @@ //------------------------------------------------------------------------------ ldr x3, [x4, #25], #0 ldr x4, [x9, #0], #4 -// CHECK-ERROR: error: expected symbolic reference or integer in range [0, 32760] +// CHECK-ERROR-AARCH64: error: {{expected symbolic reference or integer|index must be a multiple of 8}} in range [0, 32760] +// CHECK-ERROR-ARM64: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldr x3, [x4, #25], #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: invalid operand for instruction -// CHECK-ERROR-NEXT: ldr x4, [x9, #0], #4 -// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: invalid operand for instruction +// CHECK-ERROR-AARCH64-NEXT: ldr x4, [x9, #0], #4 +// CHECK-ERROR-AARCH64-NEXT: ^ strb w1, [x19], #256 strb w9, [sp], #-257 @@ -1888,22 +1899,22 @@ strh w9, [sp], #-257 str w1, [x19], #256 str w9, [sp], #-257 -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: strb w1, [x19], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: strb w9, [sp], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: strh w1, [x19], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: strh w9, [sp], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str w1, [x19], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str w9, [sp], #-257 // CHECK-ERROR-NEXT: ^ @@ -1913,22 +1924,22 @@ ldrh w9, [sp], #-257 ldr w1, [x19], #256 ldr w9, [sp], #-257 -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrb w1, [x19], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrb w9, [sp], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrh w1, [x19], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrh w9, [sp], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr w1, [x19], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr w9, [sp], #-257 // CHECK-ERROR-NEXT: ^ @@ -1938,22 +1949,22 @@ ldrsh x22, [x13], #-257 ldrsw x2, [x3], #256 ldrsw x22, [x13], #-257 -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsb x2, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsb x22, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsh x2, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsh x22, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsw x2, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsw x22, [x13], #-257 // CHECK-ERROR-NEXT: ^ @@ -1961,16 +1972,16 @@ ldrsb w22, [x13], #-257 ldrsh w2, [x3], #256 ldrsh w22, [x13], #-257 -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsb w2, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsb w22, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsh w2, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsh w22, [x13], #-257 // CHECK-ERROR-NEXT: ^ @@ -1984,34 +1995,34 @@ str d3, [x13], #-257 str q3, [x3], #256 str q3, [x13], #-257 -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str b3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str b3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str h3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str h3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str s3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str s3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str d3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str d3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str q3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str q3, [x13], #-257 // CHECK-ERROR-NEXT: ^ @@ -2025,34 +2036,34 @@ ldr d3, [x13], #-257 ldr q3, [x3], #256 ldr q3, [x13], #-257 -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr b3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr b3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr h3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr h3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr s3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr s3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr d3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr d3, [x13], #-257 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr q3, [x3], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr q3, [x13], #-257 // CHECK-ERROR-NEXT: ^ @@ -2074,19 +2085,19 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: strb w1, [x19, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: strb w9, [sp, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: strh w1, [x19, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: strh w9, [sp, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: str w1, [x19, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str w9, [sp, #-257]! // CHECK-ERROR-NEXT: ^ @@ -2099,19 +2110,19 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldrb w1, [x19, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrb w9, [sp, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldrh w1, [x19, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrh w9, [sp, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldr w1, [x19, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr w9, [sp, #-257]! // CHECK-ERROR-NEXT: ^ @@ -2124,19 +2135,19 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldrsb x2, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsb x22, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldrsh x2, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsh x22, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldrsw x2, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsw x22, [x13, #-257]! // CHECK-ERROR-NEXT: ^ @@ -2147,13 +2158,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldrsb w2, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsb w22, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldrsh w2, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrsh w22, [x13, #-257]! // CHECK-ERROR-NEXT: ^ @@ -2168,25 +2179,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: str b3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str b3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: str h3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str h3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: str s3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str s3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: str d3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str d3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ @@ -2201,25 +2212,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldr b3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr b3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldr h3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr h3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldr s3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr s3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldr d3, [x3, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr d3, [x13, #-257]! // CHECK-ERROR-NEXT: ^ @@ -2231,16 +2242,16 @@ sttrh w17, [x1, #256] ldtrsw x20, [x1, #256] ldtr x12, [sp, #256] -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldtrb w2, [sp, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: sttrh w17, [x1, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldtrsw x20, [x1, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldtr x12, [sp, #256] // CHECK-ERROR-NEXT: ^ @@ -2255,10 +2266,10 @@ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: sttr b2, [x2, #-257] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldtrsb x9, [sp, #-257] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldtr w2, [x30, #-257] // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -2276,19 +2287,19 @@ ldr w0, [x4, #16384] ldrh w2, [x21, #8192] ldrb w3, [x12, #4096] -// CHECK-ERROR: error: expected integer in range [-256, 255] +// CHECK-ERROR: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr q0, [x11, #65536] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr x0, [sp, #32768] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldr w0, [x4, #16384] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrh w2, [x21, #8192] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: ldrb w3, [x12, #4096] // CHECK-ERROR-NEXT: ^ @@ -2296,15 +2307,15 @@ ldr w0, [x0, #2] ldrsh w2, [x0, #123] str q0, [x0, #8] -// CHECK-ERROR: error: too few operands for instruction -// CHECK-ERROR-NEXT: ldr w0, [x0, #2] -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: too few operands for instruction -// CHECK-ERROR-NEXT: ldrsh w2, [x0, #123] -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: too few operands for instruction -// CHECK-ERROR-NEXT: str q0, [x0, #8] -// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-AARCH64: error: too few operands for instruction +// CHECK-ERROR-AARCH64-NEXT: ldr w0, [x0, #2] +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: too few operands for instruction +// CHECK-ERROR-AARCH64-NEXT: ldrsh w2, [x0, #123] +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: too few operands for instruction +// CHECK-ERROR-AARCH64-NEXT: str q0, [x0, #8] +// CHECK-ERROR-AARCH64-NEXT: ^ //// 32-bit addresses ldr w0, [w20] @@ -2324,13 +2335,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: strb w0, [wsp] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR: error: invalid operand for instruction -// CHECK-ERROR-NEXT: strh w31, [x23, #1] -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: too few operands for instruction -// CHECK-ERROR-NEXT: str x5, [x22, #12] -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [-256, 255] +// CHECK-ERROR-AARCH64: error: invalid operand for instruction +// CHECK-ERROR-AARCH64-NEXT: strh w31, [x23, #1] +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-AARCH64-NEXT: error: too few operands for instruction +// CHECK-ERROR-AARCH64-NEXT: str x5, [x22, #12] +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-NEXT: error: {{expected|index must be an}} integer in range [-256, 255] // CHECK-ERROR-NEXT: str w7, [x12, #16384] // CHECK-ERROR-NEXT: ^ @@ -2339,16 +2350,19 @@ prfm #32, [sp, #8] prfm pldl1strm, [w3, #8] prfm wibble, [sp] -// CHECK-ERROR: error: Invalid immediate for instruction +// CHECK-ERROR-AARCH64: error: Invalid immediate for instruction +// CHECK-ERROR-ARM64: error: prefetch operand out of range, [0,31] expected // CHECK-ERROR-NEXT: prfm #-1, [sp] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-AARCH64-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-ARM64-NEXT: error: prefetch operand out of range, [0,31] expected // CHECK-ERROR-NEXT: prfm #32, [sp, #8] // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: prfm pldl1strm, [w3, #8] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: operand specifier not recognised +// CHECK-ERROR-AARCH64-NEXT: error: operand specifier not recognised +// CHECK-ERROR-ARM64-NEXT: error: pre-fetch hint expected // CHECK-ERROR-NEXT: prfm wibble, [sp] // CHECK-ERROR-NEXT: ^ @@ -2431,10 +2445,12 @@ // CHECK-ERROR-NEXT: error: expected integer shift amount // CHECK-ERROR-NEXT: ldr q5, [sp, x2, lsl #-1] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4 +// CHECK-ERROR-AARCH64-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4 +// CHECK-ERROR-ARM64-NEXT: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4 // CHECK-ERROR-NEXT: ldr q10, [x20, w4, uxtw #2] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4 +// CHECK-ERROR-AARCH64-NEXT: error: expected 'lsl' or 'sxtw' with optional shift of #0 or #4 +// CHECK-ERROR-ARM64-NEXT: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4 // CHECK-ERROR-NEXT: str q21, [x20, w4, uxtw #5] // CHECK-ERROR-NEXT: ^ @@ -2446,16 +2462,16 @@ stp w9, w10, [x5, #256] ldp w11, w12, [x9, #-260] stp wsp, w9, [sp] -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp w3, w2, [x4, #1] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp w1, w2, [x3, #253] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp w9, w10, [x5, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp w11, w12, [x9, #-260] // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -2465,26 +2481,26 @@ ldpsw x9, x2, [sp, #2] ldpsw x1, x2, [x10, #256] ldpsw x3, x4, [x11, #-260] -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x9, x2, [sp, #2] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x1, x2, [x10, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x3, x4, [x11, #-260] // CHECK-ERROR-NEXT: ^ ldp x2, x5, [sp, #4] ldp x5, x6, [x9, #512] stp x7, x8, [x10, #-520] -// CHECK-ERROR: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp x2, x5, [sp, #4] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp x5, x6, [x9, #512] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stp x7, x8, [x10, #-520] // CHECK-ERROR-NEXT: ^ @@ -2500,13 +2516,13 @@ stp s3, s5, [sp, #-2] ldp s6, s26, [x4, #-260] stp s13, s19, [x5, #256] -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp s3, s5, [sp, #-2] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp s6, s26, [x4, #-260] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp s13, s19, [x5, #256] // CHECK-ERROR-NEXT: ^ @@ -2516,10 +2532,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldp d3, d4, [xzr] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp d5, d6, [x0, #512] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stp d7, d8, [x0, #-520] // CHECK-ERROR-NEXT: ^ @@ -2530,13 +2546,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldp d3, q2, [sp] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldp q3, q5, [sp, #8] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: stp q20, q25, [x5, #1024] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldp q30, q15, [x23, #-1040] // CHECK-ERROR-NEXT: ^ @@ -2549,16 +2565,16 @@ stp w9, w10, [x5], #256 ldp w11, w12, [x9], #-260 stp wsp, w9, [sp], #0 -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp w3, w2, [x4], #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp w1, w2, [x3], #253 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp w9, w10, [x5], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp w11, w12, [x9], #-260 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -2568,26 +2584,26 @@ ldpsw x9, x2, [sp], #2 ldpsw x1, x2, [x10], #256 ldpsw x3, x4, [x11], #-260 -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x9, x2, [sp], #2 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x1, x2, [x10], #256 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x3, x4, [x11], #-260 // CHECK-ERROR-NEXT: ^ ldp x2, x5, [sp], #4 ldp x5, x6, [x9], #512 stp x7, x8, [x10], #-520 -// CHECK-ERROR: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp x2, x5, [sp], #4 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp x5, x6, [x9], #512 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stp x7, x8, [x10], #-520 // CHECK-ERROR-NEXT: ^ @@ -2603,13 +2619,13 @@ stp s3, s5, [sp], #-2 ldp s6, s26, [x4], #-260 stp s13, s19, [x5], #256 -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp s3, s5, [sp], #-2 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp s6, s26, [x4], #-260 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp s13, s19, [x5], #256 // CHECK-ERROR-NEXT: ^ @@ -2619,10 +2635,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldp d3, d4, [xzr], #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp d5, d6, [x0], #512 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stp d7, d8, [x0], #-520 // CHECK-ERROR-NEXT: ^ @@ -2633,13 +2649,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldp d3, q2, [sp], #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldp q3, q5, [sp], #8 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: stp q20, q25, [x5], #1024 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldp q30, q15, [x23], #-1040 // CHECK-ERROR-NEXT: ^ @@ -2652,16 +2668,16 @@ stp w9, w10, [x5, #256]! ldp w11, w12, [x9, #-260]! stp wsp, w9, [sp, #0]! -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp w3, w2, [x4, #1]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp w1, w2, [x3, #253]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp w9, w10, [x5, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp w11, w12, [x9, #-260]! // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -2671,26 +2687,26 @@ ldpsw x9, x2, [sp, #2]! ldpsw x1, x2, [x10, #256]! ldpsw x3, x4, [x11, #-260]! -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x9, x2, [sp, #2]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x1, x2, [x10, #256]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldpsw x3, x4, [x11, #-260]! // CHECK-ERROR-NEXT: ^ ldp x2, x5, [sp, #4]! ldp x5, x6, [x9, #512]! stp x7, x8, [x10, #-520]! -// CHECK-ERROR: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp x2, x5, [sp, #4]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp x5, x6, [x9, #512]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stp x7, x8, [x10, #-520]! // CHECK-ERROR-NEXT: ^ @@ -2706,13 +2722,13 @@ stp s3, s5, [sp, #-2]! ldp s6, s26, [x4, #-260]! stp s13, s19, [x5, #256]! -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp s3, s5, [sp, #-2]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldp s6, s26, [x4, #-260]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stp s13, s19, [x5, #256]! // CHECK-ERROR-NEXT: ^ @@ -2722,10 +2738,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldp d3, d4, [xzr, #0]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldp d5, d6, [x0, #512]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stp d7, d8, [x0, #-520]! // CHECK-ERROR-NEXT: ^ @@ -2736,13 +2752,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldp d3, q2, [sp, #0]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldp q3, q5, [sp, #8]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: stp q20, q25, [x5, #1024]! // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldp q30, q15, [x23, #-1040]! // CHECK-ERROR-NEXT: ^ @@ -2754,16 +2770,16 @@ stnp w9, w10, [x5, #256] ldnp w11, w12, [x9, #-260] stnp wsp, w9, [sp] -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldnp w3, w2, [x4, #1] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stnp w1, w2, [x3, #253] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stnp w9, w10, [x5, #256] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldnp w11, w12, [x9, #-260] // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction @@ -2773,13 +2789,13 @@ ldnp x2, x5, [sp, #4] ldnp x5, x6, [x9, #512] stnp x7, x8, [x10, #-520] -// CHECK-ERROR: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldnp x2, x5, [sp, #4] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldnp x5, x6, [x9, #512] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stnp x7, x8, [x10, #-520] // CHECK-ERROR-NEXT: ^ @@ -2795,13 +2811,13 @@ stnp s3, s5, [sp, #-2] ldnp s6, s26, [x4, #-260] stnp s13, s19, [x5, #256] -// CHECK-ERROR: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stnp s3, s5, [sp, #-2] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: ldnp s6, s26, [x4, #-260] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 4 in range [-256, 252] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 4 in range [-256, 252] // CHECK-ERROR-NEXT: stnp s13, s19, [x5, #256] // CHECK-ERROR-NEXT: ^ @@ -2811,10 +2827,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldnp d3, d4, [xzr] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: ldnp d5, d6, [x0, #512] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 8 in range [-512, 504] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 8 in range [-512, 504] // CHECK-ERROR-NEXT: stnp d7, d8, [x0, #-520] // CHECK-ERROR-NEXT: ^ @@ -2825,13 +2841,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: ldnp d3, q2, [sp] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldnp q3, q5, [sp, #8] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: stnp q20, q25, [x5, #1024] // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer multiple of 16 in range [-1024, 1008] +// CHECK-ERROR-NEXT: error: {{expected integer|index must be a}} multiple of 16 in range [-1024, 1008] // CHECK-ERROR-NEXT: ldnp q30, q15, [x23, #-1040] // CHECK-ERROR-NEXT: ^ @@ -2974,28 +2990,32 @@ movz x3, #-1 movk w3, #1, lsl #32 movn x2, #12, lsl #64 -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz w3, #65536, lsl #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz w4, #65536 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' with optional integer 0 or 16 // CHECK-ERROR-NEXT: movn w1, #2, lsl #1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: only 'lsl #+N' valid after immediate +// CHECK-ERROR-AARCH64-NEXT: error: only 'lsl #+N' valid after immediate +// CHECK-ERROR-ARM64-NEXT: error: expected integer shift amount // CHECK-ERROR-NEXT: movk w3, #0, lsl #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movn w2, #-1, lsl #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz x3, #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' with optional integer 0 or 16 // CHECK-ERROR-NEXT: movk w3, #1, lsl #32 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-ARM64-NEXT: error: expected 'lsl' with optional integer 0, 16, 32 or 48 // CHECK-ERROR-NEXT: movn x2, #12, lsl #64 // CHECK-ERROR-NEXT: ^ @@ -3005,22 +3025,22 @@ movk w3, #:abs_g0:sym movz x3, #:abs_g0_nc:sym movn x4, #:abs_g0_nc:sym -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz x12, #:abs_g0:sym, lsl #16 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz x12, #:abs_g0:sym, lsl #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] -// CHECK-ERROR-NEXT: movn x2, #:abs_g0:sym -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: movn x2, #:abs_g0:sym +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk w3, #:abs_g0:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz x3, #:abs_g0_nc:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movn x4, #:abs_g0_nc:sym // CHECK-ERROR-NEXT: ^ @@ -3028,16 +3048,16 @@ movk w3, #:abs_g1:sym movz x3, #:abs_g1_nc:sym movn x4, #:abs_g1_nc:sym -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] -// CHECK-ERROR-NEXT: movn x2, #:abs_g1:sym -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-AARCH64: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: movn x2, #:abs_g1:sym +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk w3, #:abs_g1:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz x3, #:abs_g1_nc:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movn x4, #:abs_g1_nc:sym // CHECK-ERROR-NEXT: ^ @@ -3047,53 +3067,53 @@ movk w3, #:abs_g2_nc:sym movz x13, #:abs_g2_nc:sym movn x24, #:abs_g2_nc:sym -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz w12, #:abs_g2:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] -// CHECK-ERROR-NEXT: movn x12, #:abs_g2:sym -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: movn x12, #:abs_g2:sym +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk x13, #:abs_g2:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk w3, #:abs_g2_nc:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz x13, #:abs_g2_nc:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movn x24, #:abs_g2_nc:sym // CHECK-ERROR-NEXT: ^ movn x19, #:abs_g3:sym movz w20, #:abs_g3:sym movk w21, #:abs_g3:sym -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] -// CHECK-ERROR-NEXT: movn x19, #:abs_g3:sym -// CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-AARCH64: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] +// CHECK-ERROR-AARCH64-NEXT: movn x19, #:abs_g3:sym +// CHECK-ERROR-AARCH64-NEXT: ^ +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz w20, #:abs_g3:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk w21, #:abs_g3:sym // CHECK-ERROR-NEXT: ^ movk x19, #:abs_g0_s:sym movk w23, #:abs_g0_s:sym -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk x19, #:abs_g0_s:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk w23, #:abs_g0_s:sym // CHECK-ERROR-NEXT: ^ movk x19, #:abs_g1_s:sym movk w23, #:abs_g1_s:sym -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk x19, #:abs_g1_s:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk w23, #:abs_g1_s:sym // CHECK-ERROR-NEXT: ^ @@ -3101,16 +3121,16 @@ movn w29, #:abs_g2_s:sym movk x19, #:abs_g2_s:sym movk w23, #:abs_g2_s:sym -// CHECK-ERROR: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movz w2, #:abs_g2_s:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movn w29, #:abs_g2_s:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk x19, #:abs_g2_s:sym // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected relocated symbol or integer in range [0, 65535] +// CHECK-ERROR-NEXT: error: {{expected relocated symbol or|immediate must be an}} integer in range [0, 65535] // CHECK-ERROR-NEXT: movk w23, #:abs_g2_s:sym // CHECK-ERROR-NEXT: ^ @@ -3154,19 +3174,19 @@ hint #-1 hint #128 -// CHECK-ERROR: error: expected integer in range [0, 127] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 127] // CHECK-ERROR-NEXT: hint #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 127] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 127] // CHECK-ERROR-NEXT: hint #128 // CHECK-ERROR-NEXT: ^ clrex #-1 clrex #16 -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: clrex #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: clrex #16 // CHECK-ERROR-NEXT: ^ @@ -3174,25 +3194,25 @@ dsb #16 dmb #-1 dmb #16 -// CHECK-ERROR-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-NEXT: error: {{Invalid immediate for instruction|barrier operand out of range}} // CHECK-ERROR-NEXT: dsb #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-NEXT: error: {{Invalid immediate for instruction|barrier operand out of range}} // CHECK-ERROR-NEXT: dsb #16 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-NEXT: error: {{Invalid immediate for instruction|barrier operand out of range}} // CHECK-ERROR-NEXT: dmb #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-NEXT: error: {{Invalid immediate for instruction|barrier operand out of range}} // CHECK-ERROR-NEXT: dmb #16 // CHECK-ERROR-NEXT: ^ isb #-1 isb #16 -// CHECK-ERROR-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-NEXT: error: {{Invalid immediate for instruction|barrier operand out of range}} // CHECK-ERROR-NEXT: isb #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: Invalid immediate for instruction +// CHECK-ERROR-NEXT: error: {{Invalid immediate for instruction|barrier operand out of range}} // CHECK-ERROR-NEXT: isb #16 // CHECK-ERROR-NEXT: ^ @@ -3200,16 +3220,16 @@ msr spsel, #-1 msr spsel #-1 msr daifclr, #16 -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: msr daifset, x4 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: msr spsel, #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected comma before next operand +// CHECK-ERROR-NEXT: error: {{expected comma before next operand|unexpected token in argument list}} // CHECK-ERROR-NEXT: msr spsel #-1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 15] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR-NEXT: msr daifclr, #16 // CHECK-ERROR-NEXT: ^ @@ -3221,7 +3241,7 @@ sysl x13, #3, c16, c2, #3 sysl x9, #2, c11, c16, #5 sysl x4, #4, c9, c8, #8 -// CHECK-ERROR-NEXT: error: expected integer in range [0, 7] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR-NEXT: sys #8, c1, c2, #7, x9 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: Expected cN operand where 0 <= N <= 15 @@ -3230,10 +3250,10 @@ // CHECK-ERROR-NEXT: error: Expected cN operand where 0 <= N <= 15 // CHECK-ERROR-NEXT: sys #2, c11, c16, #5 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 7] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR-NEXT: sys #4, c9, c8, #8, xzr // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 7] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR-NEXT: sysl x11, #8, c1, c2, #7 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: Expected cN operand where 0 <= N <= 15 @@ -3242,20 +3262,21 @@ // CHECK-ERROR-NEXT: error: Expected cN operand where 0 <= N <= 15 // CHECK-ERROR-NEXT: sysl x9, #2, c11, c16, #5 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 7] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR-NEXT: sysl x4, #4, c9, c8, #8 // CHECK-ERROR-NEXT: ^ ic ialluis, x2 ic allu, x7 ic ivau -// CHECK-ERROR-NEXT: error: specified IC op does not use a register +// CHECK-ERROR-NEXT: error: specified {{IC|ic}} op does not use a register // CHECK-ERROR-NEXT: ic ialluis, x2 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: operand specifier not recognised +// CHECK-ERROR-AARCH64-NEXT: error: operand specifier not recognised +// CHECK-ERROR-ARM64-NEXT: error: invalid operand for IC instruction // CHECK-ERROR-NEXT: ic allu, x7 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified IC op requires a register +// CHECK-ERROR-NEXT: error: specified {{IC|ic}} op requires a register // CHECK-ERROR-NEXT: ic ivau // CHECK-ERROR-NEXT: ^ @@ -3291,100 +3312,100 @@ tlbi VALE3 tlbi VMALLS12E1, x15 tlbi VAALE1 -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi IPAS2E1IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi IPAS2LE1IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi VMALLE1IS, x12 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi ALLE2IS, x11 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi ALLE3IS, x20 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAE1IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAE2IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAE3IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi ASIDE1IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAAE1IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi ALLE1IS, x0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VALE1IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VALE2IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VALE3IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi VMALLS12E1IS, xzr // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAALE1IS // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi IPAS2E1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi IPAS2LE1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi VMALLE1, x9 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi ALLE2, x10 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi ALLE3, x11 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAE1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAE2 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAE3 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi ASIDE1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAAE1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi ALLE1, x25 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VALE1 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VALE2 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VALE3 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op does not use a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op does not use a register // CHECK-ERROR-NEXT: tlbi VMALLS12E1, x15 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: specified TLBI op requires a register +// CHECK-ERROR-NEXT: error: specified {{TLBI|tlbi}} op requires a register // CHECK-ERROR-NEXT: tlbi VAALE1 // CHECK-ERROR-NEXT: ^ @@ -3642,16 +3663,16 @@ tbz w3, #32, nowhere tbz x9, #-1, there tbz x20, #64, dont -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: tbz w3, #-1, addr // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: tbz w3, #32, nowhere // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: tbz x9, #-1, there // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: tbz x20, #64, dont // CHECK-ERROR-NEXT: ^ @@ -3659,16 +3680,16 @@ tbnz w3, #32, nowhere tbnz x9, #-1, there tbnz x20, #64, dont -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: tbnz w3, #-1, addr // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 31] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR-NEXT: tbnz w3, #32, nowhere // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: tbnz x9, #-1, there // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: expected integer in range [0, 63] +// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR-NEXT: tbnz x20, #64, dont //------------------------------------------------------------------------------ diff --git a/test/MC/AArch64/basic-a64-instructions.s b/test/MC/AArch64/basic-a64-instructions.s index be00e14..a12968b 100644 --- a/test/MC/AArch64/basic-a64-instructions.s +++ b/test/MC/AArch64/basic-a64-instructions.s @@ -108,9 +108,9 @@ _func: // CHECK: adds x20, sp, w19, uxth #4 // encoding: [0xf4,0x33,0x33,0xab] // CHECK: adds x12, x1, w20, uxtw // encoding: [0x2c,0x40,0x34,0xab] // CHECK: adds x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xab] -// CHECK: adds xzr, x25, w20, sxtb #3 // encoding: [0x3f,0x8f,0x34,0xab] +// CHECK: {{adds xzr,|cmn}} x25, w20, sxtb #3 // encoding: [0x3f,0x8f,0x34,0xab] // CHECK: adds x18, sp, w19, sxth // encoding: [0xf2,0xa3,0x33,0xab] -// CHECK: adds xzr, x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0xab] +// CHECK: {{adds xzr,|cmn}} x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0xab] // CHECK: adds x3, x5, x9, sxtx #2 // encoding: [0xa3,0xe8,0x29,0xab] adds w2, w5, w7, uxtb @@ -127,7 +127,7 @@ _func: // CHECK: adds w19, w17, w1, uxtx // encoding: [0x33,0x62,0x21,0x2b] // CHECK: adds w2, w5, w1, sxtb #1 // encoding: [0xa2,0x84,0x21,0x2b] // CHECK: adds w26, wsp, w19, sxth // encoding: [0xfa,0xa3,0x33,0x2b] -// CHECK: adds wzr, w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x2b] +// CHECK: cmn w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x2b] // CHECK: adds w2, w3, w5, sxtx // encoding: [0x62,0xe0,0x25,0x2b] // subs @@ -143,9 +143,9 @@ _func: // CHECK: subs x20, sp, w19, uxth #4 // encoding: [0xf4,0x33,0x33,0xeb] // CHECK: subs x12, x1, w20, uxtw // encoding: [0x2c,0x40,0x34,0xeb] // CHECK: subs x20, x3, x13, uxtx // encoding: [0x74,0x60,0x2d,0xeb] -// CHECK: subs xzr, x25, w20, sxtb #3 // encoding: [0x3f,0x8f,0x34,0xeb] +// CHECK: {{subs xzr,|cmp}} x25, w20, sxtb #3 // encoding: [0x3f,0x8f,0x34,0xeb] // CHECK: subs x18, sp, w19, sxth // encoding: [0xf2,0xa3,0x33,0xeb] -// CHECK: subs xzr, x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0xeb] +// CHECK: {{subs xzr,|cmp}} x2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0xeb] // CHECK: subs x3, x5, x9, sxtx #2 // encoding: [0xa3,0xe8,0x29,0xeb] subs w2, w5, w7, uxtb @@ -162,7 +162,7 @@ _func: // CHECK: subs w19, w17, w1, uxtx // encoding: [0x33,0x62,0x21,0x6b] // CHECK: subs w2, w5, w1, sxtb #1 // encoding: [0xa2,0x84,0x21,0x6b] // CHECK: subs w26, wsp, w19, sxth // encoding: [0xfa,0xa3,0x33,0x6b] -// CHECK: subs wzr, w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x6b] +// CHECK: {{subs wzr,|cmp}} w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x6b] // CHECK: subs w2, w3, w5, sxtx // encoding: [0x62,0xe0,0x25,0x6b] // cmp @@ -227,14 +227,14 @@ _func: cmn wsp, w19, sxth cmn w2, w3, sxtw cmn w3, w5, sxtx -// CHECK: cmn w5, w7, uxtb // encoding: [0xbf,0x00,0x27,0x2b] -// CHECK: cmn w15, w17, uxth // encoding: [0xff,0x21,0x31,0x2b] -// CHECK: cmn w29, wzr, uxtw // encoding: [0xbf,0x43,0x3f,0x2b] -// CHECK: cmn w17, w1, uxtx // encoding: [0x3f,0x62,0x21,0x2b] -// CHECK: cmn w5, w1, sxtb #1 // encoding: [0xbf,0x84,0x21,0x2b] -// CHECK: cmn wsp, w19, sxth // encoding: [0xff,0xa3,0x33,0x2b] -// CHECK: cmn w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x2b] -// CHECK: cmn w3, w5, sxtx // encoding: [0x7f,0xe0,0x25,0x2b] +// CHECK: {{cmn|adds wzr,}} w5, w7, uxtb // encoding: [0xbf,0x00,0x27,0x2b] +// CHECK: {{cmn|adds wzr,}} w15, w17, uxth // encoding: [0xff,0x21,0x31,0x2b] +// CHECK: {{cmn|adds wzr,}} w29, wzr, uxtw // encoding: [0xbf,0x43,0x3f,0x2b] +// CHECK: {{cmn|adds wzr,}} w17, w1, uxtx // encoding: [0x3f,0x62,0x21,0x2b] +// CHECK: {{cmn|adds wzr,}} w5, w1, sxtb #1 // encoding: [0xbf,0x84,0x21,0x2b] +// CHECK: {{cmn|adds wzr,}} wsp, w19, sxth // encoding: [0xff,0xa3,0x33,0x2b] +// CHECK: {{cmn|adds wzr,}} w2, w3, sxtw // encoding: [0x5f,0xc0,0x23,0x2b] +// CHECK: {{cmn|adds wzr,}} w3, w5, sxtx // encoding: [0x7f,0xe0,0x25,0x2b] // operands for cmp cmp x20, w29, uxtb #3 @@ -244,7 +244,7 @@ _func: // CHECK: cmp x20, w29, uxtb #3 // encoding: [0x9f,0x0e,0x3d,0xeb] // CHECK: cmp x12, x13, uxtx #4 // encoding: [0x9f,0x71,0x2d,0xeb] // CHECK: cmp wsp, w1, uxtb // encoding: [0xff,0x03,0x21,0x6b] -// CHECK: cmn wsp, wzr, sxtw // encoding: [0xff,0xc3,0x3f,0x2b] +// CHECK: {{cmn|adds wzr,}} wsp, wzr, sxtw // encoding: [0xff,0xc3,0x3f,0x2b] // LSL variant if sp involved sub sp, x3, x7, lsl #4 @@ -255,7 +255,7 @@ _func: // CHECK: sub sp, x3, x7, lsl #4 // encoding: [0x7f,0x70,0x27,0xcb] // CHECK: add w2, wsp, w3, lsl #1 // encoding: [0xe2,0x47,0x23,0x0b] // CHECK: cmp wsp, w9 // encoding: [0xff,0x43,0x29,0x6b] -// CHECK: adds wzr, wsp, w3, lsl #4 // encoding: [0xff,0x53,0x23,0x2b] +// CHECK: cmn wsp, w3, lsl #4 // encoding: [0xff,0x53,0x23,0x2b] // CHECK: subs x3, sp, x9, lsl #2 // encoding: [0xe3,0x6b,0x29,0xeb] //------------------------------------------------------------------------------ @@ -309,16 +309,16 @@ _func: adds w20, wsp, #0x0 adds xzr, x3, #0x1, lsl #12 // FIXME: canonically should be cmn // CHECK: adds w13, w23, #291, lsl #12 // encoding: [0xed,0x8e,0x44,0x31] -// CHECK: adds wzr, w2, #4095 // encoding: [0x5f,0xfc,0x3f,0x31] +// CHECK: {{adds wzr,|cmn}} w2, #4095 // encoding: [0x5f,0xfc,0x3f,0x31] // CHECK: adds w20, wsp, #0 // encoding: [0xf4,0x03,0x00,0x31] -// CHECK: adds xzr, x3, #1, lsl #12 // encoding: [0x7f,0x04,0x40,0xb1] +// CHECK: {{adds xzr,|cmn}} x3, #1, lsl #12 // encoding: [0x7f,0x04,0x40,0xb1] // Checks for subs subs xzr, sp, #20, lsl #12 // FIXME: canonically should be cmp subs xzr, x30, #4095, lsl #0 // FIXME: canonically should be cmp subs x4, sp, #3822 -// CHECK: subs xzr, sp, #20, lsl #12 // encoding: [0xff,0x53,0x40,0xf1] -// CHECK: subs xzr, x30, #4095 // encoding: [0xdf,0xff,0x3f,0xf1] +// CHECK: {{subs xzr,|cmp}} sp, #20, lsl #12 // encoding: [0xff,0x53,0x40,0xf1] +// CHECK: {{subs xzr,|cmp}} x30, #4095 // encoding: [0xdf,0xff,0x3f,0xf1] // CHECK: subs x4, sp, #3822 // encoding: [0xe4,0xbb,0x3b,0xf1] // cmn is an alias for adds zr, ... @@ -349,8 +349,8 @@ _func: // A relocation check (default to lo12, which is the only sane relocation anyway really) add x0, x4, #:lo12:var -// CHECK: add x0, x4, #:lo12:var // encoding: [0x80'A',A,A,0x91'A'] -// CHECK: // fixup A - offset: 0, value: :lo12:var, kind: fixup_a64_add_lo12 +// CHECK: add x0, x4, :lo12:var // encoding: [0x80,0bAAAAAA00,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :lo12:var, kind: fixup_aarch64_add_imm12 //------------------------------------------------------------------------------ // Add-sub (shifted register) @@ -423,7 +423,7 @@ _func: adds w20, wzr, w4 adds w4, w6, wzr // CHECK: adds w3, w5, w7 // encoding: [0xa3,0x00,0x07,0x2b] -// CHECK: adds wzr, w3, w5 // encoding: [0x7f,0x00,0x05,0x2b] +// CHECK: {{adds wzr,|cmn}} w3, w5 // encoding: [0x7f,0x00,0x05,0x2b] // CHECK: adds w20, wzr, w4 // encoding: [0xf4,0x03,0x04,0x2b] // CHECK: adds w4, w6, wzr // encoding: [0xc4,0x00,0x1f,0x2b] @@ -453,7 +453,7 @@ _func: adds x20, xzr, x4 adds x4, x6, xzr // CHECK: adds x3, x5, x7 // encoding: [0xa3,0x00,0x07,0xab] -// CHECK: adds xzr, x3, x5 // encoding: [0x7f,0x00,0x05,0xab] +// CHECK: {{adds xzr,|cmn}} x3, x5 // encoding: [0x7f,0x00,0x05,0xab] // CHECK: adds x20, xzr, x4 // encoding: [0xf4,0x03,0x04,0xab] // CHECK: adds x4, x6, xzr // encoding: [0xc4,0x00,0x1f,0xab] @@ -484,7 +484,7 @@ _func: sub w4, w6, wzr // CHECK: sub w3, w5, w7 // encoding: [0xa3,0x00,0x07,0x4b] // CHECK: sub wzr, w3, w5 // encoding: [0x7f,0x00,0x05,0x4b] -// CHECK: sub w20, wzr, w4 // encoding: [0xf4,0x03,0x04,0x4b] +// CHECK: neg w20, w4 // encoding: [0xf4,0x03,0x04,0x4b] // CHECK: sub w4, w6, wzr // encoding: [0xc4,0x00,0x1f,0x4b] sub w11, w13, w15, lsl #0 @@ -514,7 +514,7 @@ _func: sub x4, x6, xzr // CHECK: sub x3, x5, x7 // encoding: [0xa3,0x00,0x07,0xcb] // CHECK: sub xzr, x3, x5 // encoding: [0x7f,0x00,0x05,0xcb] -// CHECK: sub x20, xzr, x4 // encoding: [0xf4,0x03,0x04,0xcb] +// CHECK: neg x20, x4 // encoding: [0xf4,0x03,0x04,0xcb] // CHECK: sub x4, x6, xzr // encoding: [0xc4,0x00,0x1f,0xcb] sub x11, x13, x15, lsl #0 @@ -543,8 +543,8 @@ _func: subs w20, wzr, w4 subs w4, w6, wzr // CHECK: subs w3, w5, w7 // encoding: [0xa3,0x00,0x07,0x6b] -// CHECK: subs wzr, w3, w5 // encoding: [0x7f,0x00,0x05,0x6b] -// CHECK: subs w20, wzr, w4 // encoding: [0xf4,0x03,0x04,0x6b] +// CHECK: {{subs wzr,|cmp}} w3, w5 // encoding: [0x7f,0x00,0x05,0x6b] +// CHECK: negs w20, w4 // encoding: [0xf4,0x03,0x04,0x6b] // CHECK: subs w4, w6, wzr // encoding: [0xc4,0x00,0x1f,0x6b] subs w11, w13, w15, lsl #0 @@ -573,8 +573,8 @@ _func: subs x20, xzr, x4 subs x4, x6, xzr // CHECK: subs x3, x5, x7 // encoding: [0xa3,0x00,0x07,0xeb] -// CHECK: subs xzr, x3, x5 // encoding: [0x7f,0x00,0x05,0xeb] -// CHECK: subs x20, xzr, x4 // encoding: [0xf4,0x03,0x04,0xeb] +// CHECK: {{subs xzr,|cmp}} x3, x5 // encoding: [0x7f,0x00,0x05,0xeb] +// CHECK: negs x20, x4 // encoding: [0xf4,0x03,0x04,0xeb] // CHECK: subs x4, x6, xzr // encoding: [0xc4,0x00,0x1f,0xeb] subs x11, x13, x15, lsl #0 @@ -713,114 +713,118 @@ _func: neg w29, w30 neg w30, wzr neg wzr, w0 -// CHECK: sub w29, wzr, w30 // encoding: [0xfd,0x03,0x1e,0x4b] -// CHECK: sub w30, wzr, wzr // encoding: [0xfe,0x03,0x1f,0x4b] -// CHECK: sub wzr, wzr, w0 // encoding: [0xff,0x03,0x00,0x4b] +// CHECK: neg w29, w30 // encoding: [0xfd,0x03,0x1e,0x4b] +// CHECK: neg w30, wzr // encoding: [0xfe,0x03,0x1f,0x4b] +// CHECK: neg wzr, w0 // encoding: [0xff,0x03,0x00,0x4b] neg w28, w27, lsl #0 neg w26, w25, lsl #29 neg w24, w23, lsl #31 -// CHECK: sub w28, wzr, w27 // encoding: [0xfc,0x03,0x1b,0x4b] -// CHECK: sub w26, wzr, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b] -// CHECK: sub w24, wzr, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b] + +// CHECK: neg w28, w27 // encoding: [0xfc,0x03,0x1b,0x4b] +// CHECK: neg w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b] +// CHECK: neg w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b] neg w22, w21, lsr #0 neg w20, w19, lsr #1 neg w18, w17, lsr #31 -// CHECK: sub w22, wzr, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x4b] -// CHECK: sub w20, wzr, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x4b] -// CHECK: sub w18, wzr, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x4b] +// CHECK: neg w22, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x4b] +// CHECK: neg w20, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x4b] +// CHECK: neg w18, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x4b] neg w16, w15, asr #0 neg w14, w13, asr #12 neg w12, w11, asr #31 -// CHECK: sub w16, wzr, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x4b] -// CHECK: sub w14, wzr, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x4b] -// CHECK: sub w12, wzr, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x4b] +// CHECK: neg w16, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x4b] +// CHECK: neg w14, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x4b] +// CHECK: neg w12, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x4b] neg x29, x30 neg x30, xzr neg xzr, x0 -// CHECK: sub x29, xzr, x30 // encoding: [0xfd,0x03,0x1e,0xcb] -// CHECK: sub x30, xzr, xzr // encoding: [0xfe,0x03,0x1f,0xcb] -// CHECK: sub xzr, xzr, x0 // encoding: [0xff,0x03,0x00,0xcb] +// CHECK: neg x29, x30 // encoding: [0xfd,0x03,0x1e,0xcb] +// CHECK: neg x30, xzr // encoding: [0xfe,0x03,0x1f,0xcb] +// CHECK: neg xzr, x0 // encoding: [0xff,0x03,0x00,0xcb] neg x28, x27, lsl #0 neg x26, x25, lsl #29 neg x24, x23, lsl #31 -// CHECK: sub x28, xzr, x27 // encoding: [0xfc,0x03,0x1b,0xcb] -// CHECK: sub x26, xzr, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb] -// CHECK: sub x24, xzr, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb] + +// CHECK: neg x28, x27 // encoding: [0xfc,0x03,0x1b,0xcb] +// CHECK: neg x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb] +// CHECK: neg x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb] neg x22, x21, lsr #0 neg x20, x19, lsr #1 neg x18, x17, lsr #31 -// CHECK: sub x22, xzr, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xcb] -// CHECK: sub x20, xzr, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xcb] -// CHECK: sub x18, xzr, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xcb] +// CHECK: neg x22, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xcb] +// CHECK: neg x20, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xcb] +// CHECK: neg x18, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xcb] neg x16, x15, asr #0 neg x14, x13, asr #12 neg x12, x11, asr #31 -// CHECK: sub x16, xzr, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xcb] -// CHECK: sub x14, xzr, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xcb] -// CHECK: sub x12, xzr, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xcb] +// CHECK: neg x16, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xcb] +// CHECK: neg x14, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xcb] +// CHECK: neg x12, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xcb] negs w29, w30 negs w30, wzr negs wzr, w0 -// CHECK: subs w29, wzr, w30 // encoding: [0xfd,0x03,0x1e,0x6b] -// CHECK: subs w30, wzr, wzr // encoding: [0xfe,0x03,0x1f,0x6b] -// CHECK: subs wzr, wzr, w0 // encoding: [0xff,0x03,0x00,0x6b] +// CHECK: negs w29, w30 // encoding: [0xfd,0x03,0x1e,0x6b] +// CHECK: negs w30, wzr // encoding: [0xfe,0x03,0x1f,0x6b] +// CHECK: cmp wzr, w0 // encoding: [0xff,0x03,0x00,0x6b] negs w28, w27, lsl #0 negs w26, w25, lsl #29 negs w24, w23, lsl #31 -// CHECK: subs w28, wzr, w27 // encoding: [0xfc,0x03,0x1b,0x6b] -// CHECK: subs w26, wzr, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b] -// CHECK: subs w24, wzr, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b] + +// CHECK: negs w28, w27 // encoding: [0xfc,0x03,0x1b,0x6b] +// CHECK: negs w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b] +// CHECK: negs w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b] negs w22, w21, lsr #0 negs w20, w19, lsr #1 negs w18, w17, lsr #31 -// CHECK: subs w22, wzr, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x6b] -// CHECK: subs w20, wzr, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x6b] -// CHECK: subs w18, wzr, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x6b] +// CHECK: negs w22, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x6b] +// CHECK: negs w20, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x6b] +// CHECK: negs w18, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x6b] negs w16, w15, asr #0 negs w14, w13, asr #12 negs w12, w11, asr #31 -// CHECK: subs w16, wzr, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x6b] -// CHECK: subs w14, wzr, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x6b] -// CHECK: subs w12, wzr, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x6b] +// CHECK: negs w16, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x6b] +// CHECK: negs w14, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x6b] +// CHECK: negs w12, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x6b] negs x29, x30 negs x30, xzr negs xzr, x0 -// CHECK: subs x29, xzr, x30 // encoding: [0xfd,0x03,0x1e,0xeb] -// CHECK: subs x30, xzr, xzr // encoding: [0xfe,0x03,0x1f,0xeb] -// CHECK: subs xzr, xzr, x0 // encoding: [0xff,0x03,0x00,0xeb] +// CHECK: negs x29, x30 // encoding: [0xfd,0x03,0x1e,0xeb] +// CHECK: negs x30, xzr // encoding: [0xfe,0x03,0x1f,0xeb] +// CHECK: cmp xzr, x0 // encoding: [0xff,0x03,0x00,0xeb] negs x28, x27, lsl #0 negs x26, x25, lsl #29 negs x24, x23, lsl #31 -// CHECK: subs x28, xzr, x27 // encoding: [0xfc,0x03,0x1b,0xeb] -// CHECK: subs x26, xzr, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb] -// CHECK: subs x24, xzr, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb] + +// CHECK: negs x28, x27 // encoding: [0xfc,0x03,0x1b,0xeb] +// CHECK: negs x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb] +// CHECK: negs x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb] negs x22, x21, lsr #0 negs x20, x19, lsr #1 negs x18, x17, lsr #31 -// CHECK: subs x22, xzr, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xeb] -// CHECK: subs x20, xzr, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xeb] -// CHECK: subs x18, xzr, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xeb] +// CHECK: negs x22, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xeb] +// CHECK: negs x20, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xeb] +// CHECK: negs x18, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xeb] negs x16, x15, asr #0 negs x14, x13, asr #12 negs x12, x11, asr #31 -// CHECK: subs x16, xzr, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xeb] -// CHECK: subs x14, xzr, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xeb] -// CHECK: subs x12, xzr, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xeb] +// CHECK: negs x16, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xeb] +// CHECK: negs x14, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xeb] +// CHECK: negs x12, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xeb] //------------------------------------------------------------------------------ // Add-sub (shifted register) @@ -933,28 +937,29 @@ _func: sbfm x3, x4, #63, #63 sbfm wzr, wzr, #31, #31 sbfm w12, w9, #0, #0 -// CHECK: sbfm x1, x2, #3, #4 // encoding: [0x41,0x10,0x43,0x93] -// CHECK: sbfm x3, x4, #63, #63 // encoding: [0x83,0xfc,0x7f,0x93] -// CHECK: sbfm wzr, wzr, #31, #31 // encoding: [0xff,0x7f,0x1f,0x13] -// CHECK: sbfm w12, w9, #0, #0 // encoding: [0x2c,0x01,0x00,0x13] + +// CHECK: sbfx x1, x2, #3, #2 // encoding: [0x41,0x10,0x43,0x93] +// CHECK: asr x3, x4, #63 // encoding: [0x83,0xfc,0x7f,0x93] +// CHECK: asr wzr, wzr, #31 // encoding: [0xff,0x7f,0x1f,0x13] +// CHECK: sbfx w12, w9, #0, #1 // encoding: [0x2c,0x01,0x00,0x13] ubfm x4, x5, #12, #10 ubfm xzr, x4, #0, #0 ubfm x4, xzr, #63, #5 ubfm x5, x6, #12, #63 -// CHECK: ubfm x4, x5, #12, #10 // encoding: [0xa4,0x28,0x4c,0xd3] -// CHECK: ubfm xzr, x4, #0, #0 // encoding: [0x9f,0x00,0x40,0xd3] -// CHECK: ubfm x4, xzr, #63, #5 // encoding: [0xe4,0x17,0x7f,0xd3] -// CHECK: ubfm x5, x6, #12, #63 // encoding: [0xc5,0xfc,0x4c,0xd3] +// CHECK: ubfiz x4, x5, #52, #11 // encoding: [0xa4,0x28,0x4c,0xd3] +// CHECK: ubfx xzr, x4, #0, #1 // encoding: [0x9f,0x00,0x40,0xd3] +// CHECK: ubfiz x4, xzr, #1, #6 // encoding: [0xe4,0x17,0x7f,0xd3] +// CHECK: lsr x5, x6, #12 // encoding: [0xc5,0xfc,0x4c,0xd3] bfm x4, x5, #12, #10 bfm xzr, x4, #0, #0 bfm x4, xzr, #63, #5 bfm x5, x6, #12, #63 -// CHECK: bfm x4, x5, #12, #10 // encoding: [0xa4,0x28,0x4c,0xb3] -// CHECK: bfm xzr, x4, #0, #0 // encoding: [0x9f,0x00,0x40,0xb3] -// CHECK: bfm x4, xzr, #63, #5 // encoding: [0xe4,0x17,0x7f,0xb3] -// CHECK: bfm x5, x6, #12, #63 // encoding: [0xc5,0xfc,0x4c,0xb3] +// CHECK: bfi x4, x5, #52, #11 // encoding: [0xa4,0x28,0x4c,0xb3] +// CHECK: bfxil xzr, x4, #0, #1 // encoding: [0x9f,0x00,0x40,0xb3] +// CHECK: bfi x4, xzr, #1, #6 // encoding: [0xe4,0x17,0x7f,0xb3] +// CHECK: bfxil x5, x6, #12, #52 // encoding: [0xc5,0xfc,0x4c,0xb3] sxtb w1, w2 sxtb xzr, w3 @@ -972,9 +977,9 @@ _func: uxth w9, w10 uxth x0, w1 // CHECK: uxtb w1, w2 // encoding: [0x41,0x1c,0x00,0x53] -// CHECK: uxtb xzr, w3 // encoding: [0x7f,0x1c,0x00,0x53] +// CHECK: uxtb {{[wx]}}zr, w3 // encoding: [0x7f,0x1c,0x00,0x53] // CHECK: uxth w9, w10 // encoding: [0x49,0x3d,0x00,0x53] -// CHECK: uxth x0, w1 // encoding: [0x20,0x3c,0x00,0x53] +// CHECK: uxth {{[wx]}}0, w1 // encoding: [0x20,0x3c,0x00,0x53] asr w3, w2, #0 asr w9, w10, #31 @@ -998,7 +1003,7 @@ _func: lsl w9, w10, #31 lsl x20, x21, #63 lsl w1, wzr, #3 -// CHECK: lsl w3, w2, #0 // encoding: [0x43,0x7c,0x00,0x53] +// CHECK: {{lsl|lsr}} w3, w2, #0 // encoding: [0x43,0x7c,0x00,0x53] // CHECK: lsl w9, w10, #31 // encoding: [0x49,0x01,0x01,0x53] // CHECK: lsl x20, x21, #63 // encoding: [0xb4,0x02,0x41,0xd3] // CHECK: lsl w1, wzr, #3 // encoding: [0xe1,0x73,0x1d,0x53] @@ -1011,11 +1016,11 @@ _func: sbfiz w11, w12, #31, #1 sbfiz w13, w14, #29, #3 sbfiz xzr, xzr, #10, #11 -// CHECK: sbfiz w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x13] +// CHECK: {{sbfiz|sbfx}} w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x13] // CHECK: sbfiz x2, x3, #63, #1 // encoding: [0x62,0x00,0x41,0x93] -// CHECK: sbfiz x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0x93] +// CHECK: asr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0x93] // CHECK: sbfiz x9, x10, #5, #59 // encoding: [0x49,0xe9,0x7b,0x93] -// CHECK: sbfiz w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x13] +// CHECK: asr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x13] // CHECK: sbfiz w11, w12, #31, #1 // encoding: [0x8b,0x01,0x01,0x13] // CHECK: sbfiz w13, w14, #29, #3 // encoding: [0xcd,0x09,0x03,0x13] // CHECK: sbfiz xzr, xzr, #10, #11 // encoding: [0xff,0x2b,0x76,0x93] @@ -1029,12 +1034,12 @@ _func: sbfx w13, w14, #29, #3 sbfx xzr, xzr, #10, #11 // CHECK: sbfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x13] -// CHECK: sbfx x2, x3, #63, #1 // encoding: [0x62,0xfc,0x7f,0x93] -// CHECK: sbfx x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0x93] -// CHECK: sbfx x9, x10, #5, #59 // encoding: [0x49,0xfd,0x45,0x93] -// CHECK: sbfx w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x13] -// CHECK: sbfx w11, w12, #31, #1 // encoding: [0x8b,0x7d,0x1f,0x13] -// CHECK: sbfx w13, w14, #29, #3 // encoding: [0xcd,0x7d,0x1d,0x13] +// CHECK: asr x2, x3, #63 // encoding: [0x62,0xfc,0x7f,0x93] +// CHECK: asr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0x93] +// CHECK: asr x9, x10, #5 // encoding: [0x49,0xfd,0x45,0x93] +// CHECK: asr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x13] +// CHECK: asr w11, w12, #31 // encoding: [0x8b,0x7d,0x1f,0x13] +// CHECK: asr w13, w14, #29 // encoding: [0xcd,0x7d,0x1d,0x13] // CHECK: sbfx xzr, xzr, #10, #11 // encoding: [0xff,0x53,0x4a,0x93] bfi w9, w10, #0, #1 @@ -1045,11 +1050,12 @@ _func: bfi w11, w12, #31, #1 bfi w13, w14, #29, #3 bfi xzr, xzr, #10, #11 -// CHECK: bfi w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x33] + +// CHECK: bfxil w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x33] // CHECK: bfi x2, x3, #63, #1 // encoding: [0x62,0x00,0x41,0xb3] -// CHECK: bfi x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0xb3] +// CHECK: bfxil x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0xb3] // CHECK: bfi x9, x10, #5, #59 // encoding: [0x49,0xe9,0x7b,0xb3] -// CHECK: bfi w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x33] +// CHECK: bfxil w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x33] // CHECK: bfi w11, w12, #31, #1 // encoding: [0x8b,0x01,0x01,0x33] // CHECK: bfi w13, w14, #29, #3 // encoding: [0xcd,0x09,0x03,0x33] // CHECK: bfi xzr, xzr, #10, #11 // encoding: [0xff,0x2b,0x76,0xb3] @@ -1079,14 +1085,15 @@ _func: ubfiz w11, w12, #31, #1 ubfiz w13, w14, #29, #3 ubfiz xzr, xzr, #10, #11 -// CHECK: ubfiz w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53] -// CHECK: ubfiz x2, x3, #63, #1 // encoding: [0x62,0x00,0x41,0xd3] -// CHECK: ubfiz x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0xd3] -// CHECK: ubfiz x9, x10, #5, #59 // encoding: [0x49,0xe9,0x7b,0xd3] -// CHECK: ubfiz w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x53] -// CHECK: ubfiz w11, w12, #31, #1 // encoding: [0x8b,0x01,0x01,0x53] -// CHECK: ubfiz w13, w14, #29, #3 // encoding: [0xcd,0x09,0x03,0x53] -// CHECK: ubfiz xzr, xzr, #10, #11 // encoding: [0xff,0x2b,0x76,0xd3] + +// CHECK: ubfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53] +// CHECK: lsl x2, x3, #63 // encoding: [0x62,0x00,0x41,0xd3] +// CHECK: lsr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0xd3] +// CHECK: lsl x9, x10, #5 // encoding: [0x49,0xe9,0x7b,0xd3] +// CHECK: lsr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x53] +// CHECK: lsl w11, w12, #31 // encoding: [0x8b,0x01,0x01,0x53] +// CHECK: lsl w13, w14, #29 // encoding: [0xcd,0x09,0x03,0x53] +// CHECK: ubfiz xzr, xzr, #10, #11 // encoding: [0xff,0x2b,0x76,0xd3] ubfx w9, w10, #0, #1 ubfx x2, x3, #63, #1 @@ -1096,15 +1103,15 @@ _func: ubfx w11, w12, #31, #1 ubfx w13, w14, #29, #3 ubfx xzr, xzr, #10, #11 -// CHECK: ubfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53] -// CHECK: ubfx x2, x3, #63, #1 // encoding: [0x62,0xfc,0x7f,0xd3] -// CHECK: ubfx x19, x20, #0, #64 // encoding: [0x93,0xfe,0x40,0xd3] -// CHECK: ubfx x9, x10, #5, #59 // encoding: [0x49,0xfd,0x45,0xd3] -// CHECK: ubfx w9, w10, #0, #32 // encoding: [0x49,0x7d,0x00,0x53] -// CHECK: ubfx w11, w12, #31, #1 // encoding: [0x8b,0x7d,0x1f,0x53] -// CHECK: ubfx w13, w14, #29, #3 // encoding: [0xcd,0x7d,0x1d,0x53] -// CHECK: ubfx xzr, xzr, #10, #11 // encoding: [0xff,0x53,0x4a,0xd3] +// CHECK: ubfx w9, w10, #0, #1 // encoding: [0x49,0x01,0x00,0x53] +// CHECK: lsr x2, x3, #63 // encoding: [0x62,0xfc,0x7f,0xd3] +// CHECK: lsr x19, x20, #0 // encoding: [0x93,0xfe,0x40,0xd3] +// CHECK: lsr x9, x10, #5 // encoding: [0x49,0xfd,0x45,0xd3] +// CHECK: lsr w9, w10, #0 // encoding: [0x49,0x7d,0x00,0x53] +// CHECK: lsr w11, w12, #31 // encoding: [0x8b,0x7d,0x1f,0x53] +// CHECK: lsr w13, w14, #29 // encoding: [0xcd,0x7d,0x1d,0x53] +// CHECK: ubfx xzr, xzr, #10, #11 // encoding: [0xff,0x53,0x4a,0xd3] //------------------------------------------------------------------------------ // Compare & branch (immediate) //------------------------------------------------------------------------------ @@ -1113,21 +1120,22 @@ _func: cbz x5, lbl cbnz x2, lbl cbnz x26, lbl -// CHECK: cbz w5, lbl // encoding: [0x05'A',A,A,0x34'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: cbz x5, lbl // encoding: [0x05'A',A,A,0xb4'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: cbnz x2, lbl // encoding: [0x02'A',A,A,0xb5'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: cbnz x26, lbl // encoding: [0x1a'A',A,A,0xb5'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr +// CHECK: cbz w5, lbl // encoding: [0bAAA00101,A,A,0x34] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: cbz x5, lbl // encoding: [0bAAA00101,A,A,0xb4] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: cbnz x2, lbl // encoding: [0bAAA00010,A,A,0xb5] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: cbnz x26, lbl // encoding: [0bAAA11010,A,A,0xb5] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 cbz wzr, lbl cbnz xzr, lbl -// CHECK: cbz wzr, lbl // encoding: [0x1f'A',A,A,0x34'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: cbnz xzr, lbl // encoding: [0x1f'A',A,A,0xb5'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr + +// CHECK: cbz wzr, lbl // encoding: [0bAAA11111,A,A,0x34] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: cbnz xzr, lbl // encoding: [0bAAA11111,A,A,0xb5] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 cbz w5, #0 cbnz x3, #-4 @@ -1159,41 +1167,43 @@ _func: b.gt lbl b.le lbl b.al lbl -// CHECK: b.eq lbl // encoding: [A,A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.ne lbl // encoding: [0x01'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.hs lbl // encoding: [0x02'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.hs lbl // encoding: [0x02'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.lo lbl // encoding: [0x03'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.lo lbl // encoding: [0x03'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.mi lbl // encoding: [0x04'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.pl lbl // encoding: [0x05'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.vs lbl // encoding: [0x06'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.vc lbl // encoding: [0x07'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.hi lbl // encoding: [0x08'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.ls lbl // encoding: [0x09'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.ge lbl // encoding: [0x0a'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.lt lbl // encoding: [0x0b'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.gt lbl // encoding: [0x0c'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.le lbl // encoding: [0x0d'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.al lbl // encoding: [0x0e'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr +// CHECK: b.eq lbl // encoding: [0bAAA00000,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.ne lbl // encoding: [0bAAA00001,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.hs lbl // encoding: [0bAAA00010,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.hs lbl // encoding: [0bAAA00010,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.lo lbl // encoding: [0bAAA00011,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.lo lbl // encoding: [0bAAA00011,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.mi lbl // encoding: [0bAAA00100,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.pl lbl // encoding: [0bAAA00101,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.vs lbl // encoding: [0bAAA00110,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.vc lbl // encoding: [0bAAA00111,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.hi lbl // encoding: [0bAAA01000,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.ls lbl // encoding: [0bAAA01001,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.ge lbl // encoding: [0bAAA01010,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.lt lbl // encoding: [0bAAA01011,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.gt lbl // encoding: [0bAAA01100,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.le lbl // encoding: [0bAAA01101,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 +// CHECK: b.al lbl // encoding: [0bAAA01110,A,A,0x54] +// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_aarch64_pcrel_branch19 + + // ARM64 has these in a separate file beq lbl bne lbl bcs lbl @@ -1211,40 +1221,6 @@ _func: bgt lbl ble lbl bal lbl -// CHECK: b.eq lbl // encoding: [A,A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.ne lbl // encoding: [0x01'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.hs lbl // encoding: [0x02'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.hs lbl // encoding: [0x02'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.lo lbl // encoding: [0x03'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.lo lbl // encoding: [0x03'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.mi lbl // encoding: [0x04'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.pl lbl // encoding: [0x05'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.vs lbl // encoding: [0x06'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.vc lbl // encoding: [0x07'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.hi lbl // encoding: [0x08'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.ls lbl // encoding: [0x09'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.ge lbl // encoding: [0x0a'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.lt lbl // encoding: [0x0b'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.gt lbl // encoding: [0x0c'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.le lbl // encoding: [0x0d'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr -// CHECK: b.al lbl // encoding: [0x0e'A',A,A,0x54'A'] -// CHECK: // fixup A - offset: 0, value: lbl, kind: fixup_a64_condbr b.eq #0 b.lt #-4 @@ -1394,55 +1370,55 @@ _func: cset w3, eq cset x9, pl -// CHECK: csinc w3, wzr, wzr, ne // encoding: [0xe3,0x17,0x9f,0x1a] -// CHECK: csinc x9, xzr, xzr, mi // encoding: [0xe9,0x47,0x9f,0x9a] +// CHECK: cset w3, eq // encoding: [0xe3,0x17,0x9f,0x1a] +// CHECK: cset x9, pl // encoding: [0xe9,0x47,0x9f,0x9a] csetm w20, ne csetm x30, ge -// CHECK: csinv w20, wzr, wzr, eq // encoding: [0xf4,0x03,0x9f,0x5a] -// CHECK: csinv x30, xzr, xzr, lt // encoding: [0xfe,0xb3,0x9f,0xda] +// CHECK: csetm w20, ne // encoding: [0xf4,0x03,0x9f,0x5a] +// CHECK: csetm x30, ge // encoding: [0xfe,0xb3,0x9f,0xda] cinc w3, w5, gt cinc wzr, w4, le cinc w9, wzr, lt -// CHECK: csinc w3, w5, w5, le // encoding: [0xa3,0xd4,0x85,0x1a] -// CHECK: csinc wzr, w4, w4, gt // encoding: [0x9f,0xc4,0x84,0x1a] -// CHECK: csinc w9, wzr, wzr, ge // encoding: [0xe9,0xa7,0x9f,0x1a] +// CHECK: cinc w3, w5, gt // encoding: [0xa3,0xd4,0x85,0x1a] +// CHECK: cinc wzr, w4, le // encoding: [0x9f,0xc4,0x84,0x1a] +// CHECK: cset w9, lt // encoding: [0xe9,0xa7,0x9f,0x1a] cinc x3, x5, gt cinc xzr, x4, le cinc x9, xzr, lt -// CHECK: csinc x3, x5, x5, le // encoding: [0xa3,0xd4,0x85,0x9a] -// CHECK: csinc xzr, x4, x4, gt // encoding: [0x9f,0xc4,0x84,0x9a] -// CHECK: csinc x9, xzr, xzr, ge // encoding: [0xe9,0xa7,0x9f,0x9a] +// CHECK: cinc x3, x5, gt // encoding: [0xa3,0xd4,0x85,0x9a] +// CHECK: cinc xzr, x4, le // encoding: [0x9f,0xc4,0x84,0x9a] +// CHECK: cset x9, lt // encoding: [0xe9,0xa7,0x9f,0x9a] cinv w3, w5, gt cinv wzr, w4, le cinv w9, wzr, lt -// CHECK: csinv w3, w5, w5, le // encoding: [0xa3,0xd0,0x85,0x5a] -// CHECK: csinv wzr, w4, w4, gt // encoding: [0x9f,0xc0,0x84,0x5a] -// CHECK: csinv w9, wzr, wzr, ge // encoding: [0xe9,0xa3,0x9f,0x5a] +// CHECK: cinv w3, w5, gt // encoding: [0xa3,0xd0,0x85,0x5a] +// CHECK: cinv wzr, w4, le // encoding: [0x9f,0xc0,0x84,0x5a] +// CHECK: csetm w9, lt // encoding: [0xe9,0xa3,0x9f,0x5a] cinv x3, x5, gt cinv xzr, x4, le cinv x9, xzr, lt -// CHECK: csinv x3, x5, x5, le // encoding: [0xa3,0xd0,0x85,0xda] -// CHECK: csinv xzr, x4, x4, gt // encoding: [0x9f,0xc0,0x84,0xda] -// CHECK: csinv x9, xzr, xzr, ge // encoding: [0xe9,0xa3,0x9f,0xda] +// CHECK: cinv x3, x5, gt // encoding: [0xa3,0xd0,0x85,0xda] +// CHECK: cinv xzr, x4, le // encoding: [0x9f,0xc0,0x84,0xda] +// CHECK: csetm x9, lt // encoding: [0xe9,0xa3,0x9f,0xda] cneg w3, w5, gt cneg wzr, w4, le cneg w9, wzr, lt -// CHECK: csneg w3, w5, w5, le // encoding: [0xa3,0xd4,0x85,0x5a] -// CHECK: csneg wzr, w4, w4, gt // encoding: [0x9f,0xc4,0x84,0x5a] -// CHECK: csneg w9, wzr, wzr, ge // encoding: [0xe9,0xa7,0x9f,0x5a] +// CHECK: cneg w3, w5, gt // encoding: [0xa3,0xd4,0x85,0x5a] +// CHECK: cneg wzr, w4, le // encoding: [0x9f,0xc4,0x84,0x5a] +// CHECK: cneg w9, wzr, lt // encoding: [0xe9,0xa7,0x9f,0x5a] cneg x3, x5, gt cneg xzr, x4, le cneg x9, xzr, lt -// CHECK: csneg x3, x5, x5, le // encoding: [0xa3,0xd4,0x85,0xda] -// CHECK: csneg xzr, x4, x4, gt // encoding: [0x9f,0xc4,0x84,0xda] -// CHECK: csneg x9, xzr, xzr, ge // encoding: [0xe9,0xa7,0x9f,0xda] +// CHECK: cneg x3, x5, gt // encoding: [0xa3,0xd4,0x85,0xda] +// CHECK: cneg xzr, x4, le // encoding: [0x9f,0xc4,0x84,0xda] +// CHECK: cneg x9, xzr, lt // encoding: [0xe9,0xa7,0x9f,0xda] //------------------------------------------------------------------------------ // Data-processing (1 source) @@ -1699,23 +1675,23 @@ _func: svc #0 svc #65535 // CHECK: svc #0 // encoding: [0x01,0x00,0x00,0xd4] -// CHECK: svc #65535 // encoding: [0xe1,0xff,0x1f,0xd4] +// CHECK: svc #{{65535|0xffff}} // encoding: [0xe1,0xff,0x1f,0xd4] hvc #1 smc #12000 brk #12 hlt #123 -// CHECK: hvc #1 // encoding: [0x22,0x00,0x00,0xd4] -// CHECK: smc #12000 // encoding: [0x03,0xdc,0x05,0xd4] -// CHECK: brk #12 // encoding: [0x80,0x01,0x20,0xd4] -// CHECK: hlt #123 // encoding: [0x60,0x0f,0x40,0xd4] +// CHECK: hvc #{{1|0x1}} // encoding: [0x22,0x00,0x00,0xd4] +// CHECK: smc #{{12000|0x2ee0}} // encoding: [0x03,0xdc,0x05,0xd4] +// CHECK: brk #{{12|0xc}} // encoding: [0x80,0x01,0x20,0xd4] +// CHECK: hlt #{{123|0x7b}} // encoding: [0x60,0x0f,0x40,0xd4] dcps1 #42 dcps2 #9 dcps3 #1000 -// CHECK: dcps1 #42 // encoding: [0x41,0x05,0xa0,0xd4] -// CHECK: dcps2 #9 // encoding: [0x22,0x01,0xa0,0xd4] -// CHECK: dcps3 #1000 // encoding: [0x03,0x7d,0xa0,0xd4] +// CHECK: dcps1 #{{42|0x2a}} // encoding: [0x41,0x05,0xa0,0xd4] +// CHECK: dcps2 #{{9|0x9}} // encoding: [0x22,0x01,0xa0,0xd4] +// CHECK: dcps3 #{{1000|0x3e8}} // encoding: [0x03,0x7d,0xa0,0xd4] dcps1 dcps2 @@ -1740,11 +1716,11 @@ _func: ror x19, x23, #24 ror x29, xzr, #63 -// CHECK: extr x19, x23, x23, #24 // encoding: [0xf3,0x62,0xd7,0x93] -// CHECK: extr x29, xzr, xzr, #63 // encoding: [0xfd,0xff,0xdf,0x93] +// CHECK: ror x19, x23, #24 // encoding: [0xf3,0x62,0xd7,0x93] +// CHECK: ror x29, xzr, #63 // encoding: [0xfd,0xff,0xdf,0x93] ror w9, w13, #31 -// CHECK: extr w9, w13, w13, #31 // encoding: [0xa9,0x7d,0x8d,0x13] +// CHECK: ror w9, w13, #31 // encoding: [0xa9,0x7d,0x8d,0x13] //------------------------------------------------------------------------------ // Floating-point compare @@ -2176,7 +2152,7 @@ _func: fmov x3, v12.d[1] fmov v1.d[1], x19 - fmov v3.2d[1], xzr + fmov v3.d[1], xzr // CHECK: fmov x3, v12.d[1] // encoding: [0x83,0x01,0xae,0x9e] // CHECK: fmov v1.d[1], x19 // encoding: [0x61,0x02,0xaf,0x9e] // CHECK: fmov v3.d[1], xzr // encoding: [0xe3,0x03,0xaf,0x9e] @@ -2188,20 +2164,20 @@ _func: fmov s2, #0.125 fmov s3, #1.0 fmov d30, #16.0 -// CHECK: fmov s2, #0.12500000 // encoding: [0x02,0x10,0x28,0x1e] -// CHECK: fmov s3, #1.00000000 // encoding: [0x03,0x10,0x2e,0x1e] -// CHECK: fmov d30, #16.00000000 // encoding: [0x1e,0x10,0x66,0x1e] +// CHECK: fmov s2, #{{0.12500000|1.250*e-01}} // encoding: [0x02,0x10,0x28,0x1e] +// CHECK: fmov s3, #{{1.00000000|1.0*e\+00}} // encoding: [0x03,0x10,0x2e,0x1e] +// CHECK: fmov d30, #{{16.00000000|1.60*e\+01}} // encoding: [0x1e,0x10,0x66,0x1e] fmov s4, #1.0625 fmov d10, #1.9375 -// CHECK: fmov s4, #1.06250000 // encoding: [0x04,0x30,0x2e,0x1e] -// CHECK: fmov d10, #1.93750000 // encoding: [0x0a,0xf0,0x6f,0x1e] +// CHECK: fmov s4, #{{1.06250*(e\+00)?}} // encoding: [0x04,0x30,0x2e,0x1e] +// CHECK: fmov d10, #{{1.93750*(e\+00)?}} // encoding: [0x0a,0xf0,0x6f,0x1e] fmov s12, #-1.0 -// CHECK: fmov s12, #-1.00000000 // encoding: [0x0c,0x10,0x3e,0x1e] +// CHECK: fmov s12, #{{-1.0*(e\+00)?}} // encoding: [0x0c,0x10,0x3e,0x1e] fmov d16, #8.5 -// CHECK: fmov d16, #8.50000000 // encoding: [0x10,0x30,0x64,0x1e] +// CHECK: fmov d16, #{{8.50*(e\+00)?}} // encoding: [0x10,0x30,0x64,0x1e] //------------------------------------------------------------------------------ // Load-register (literal) @@ -2209,22 +2185,24 @@ _func: ldr w3, here ldr x29, there ldrsw xzr, everywhere -// CHECK: ldr w3, here // encoding: [0x03'A',A,A,0x18'A'] -// CHECK: // fixup A - offset: 0, value: here, kind: fixup_a64_ld_prel -// CHECK: ldr x29, there // encoding: [0x1d'A',A,A,0x58'A'] -// CHECK: // fixup A - offset: 0, value: there, kind: fixup_a64_ld_prel -// CHECK: ldrsw xzr, everywhere // encoding: [0x1f'A',A,A,0x98'A'] -// CHECK: // fixup A - offset: 0, value: everywhere, kind: fixup_a64_ld_prel + +// CHECK: ldr w3, here // encoding: [0bAAA00011,A,A,0x18] +// CHECK: // fixup A - offset: 0, value: here, kind: fixup_aarch64_ldr_pcrel_imm19 +// CHECK: ldr x29, there // encoding: [0bAAA11101,A,A,0x58] +// CHECK: // fixup A - offset: 0, value: there, kind: fixup_aarch64_ldr_pcrel_imm19 +// CHECK: ldrsw xzr, everywhere // encoding: [0bAAA11111,A,A,0x98] +// CHECK: // fixup A - offset: 0, value: everywhere, kind: fixup_aarch64_ldr_pcrel_imm19 ldr s0, who_knows ldr d0, i_dont ldr q0, there_must_be_a_better_way -// CHECK: ldr s0, who_knows // encoding: [A,A,A,0x1c'A'] -// CHECK: // fixup A - offset: 0, value: who_knows, kind: fixup_a64_ld_prel -// CHECK: ldr d0, i_dont // encoding: [A,A,A,0x5c'A'] -// CHECK: // fixup A - offset: 0, value: i_dont, kind: fixup_a64_ld_prel -// CHECK: ldr q0, there_must_be_a_better_way // encoding: [A,A,A,0x9c'A'] -// CHECK: // fixup A - offset: 0, value: there_must_be_a_better_way, kind: fixup_a64_ld_prel + +// CHECK: ldr s0, who_knows // encoding: [0bAAA00000,A,A,0x1c] +// CHECK: // fixup A - offset: 0, value: who_knows, kind: fixup_aarch64_ldr_pcrel_imm19 +// CHECK: ldr d0, i_dont // encoding: [0bAAA00000,A,A,0x5c] +// CHECK: // fixup A - offset: 0, value: i_dont, kind: fixup_aarch64_ldr_pcrel_imm19 +// CHECK: ldr q0, there_must_be_a_better_way // encoding: [0bAAA00000,A,A,0x9c] +// CHECK: // fixup A - offset: 0, value: there_must_be_a_better_way, kind: fixup_aarch64_ldr_pcrel_imm19 ldr w0, #1048572 ldr x10, #-1048576 @@ -2233,32 +2211,11 @@ _func: prfm pldl1strm, nowhere prfm #22, somewhere -// CHECK: prfm pldl1strm, nowhere // encoding: [0x01'A',A,A,0xd8'A'] -// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_a64_ld_prel -// CHECK: prfm #22, somewhere // encoding: [0x16'A',A,A,0xd8'A'] -// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_a64_ld_prel - -//------------------------------------------------------------------------------ -// Floating-point immediate -//------------------------------------------------------------------------------ - fmov s2, #0.125 - fmov s3, #1.0 - fmov d30, #16.0 -// CHECK: fmov s2, #0.12500000 // encoding: [0x02,0x10,0x28,0x1e] -// CHECK: fmov s3, #1.00000000 // encoding: [0x03,0x10,0x2e,0x1e] -// CHECK: fmov d30, #16.00000000 // encoding: [0x1e,0x10,0x66,0x1e] - - fmov s4, #1.0625 - fmov d10, #1.9375 -// CHECK: fmov s4, #1.06250000 // encoding: [0x04,0x30,0x2e,0x1e] -// CHECK: fmov d10, #1.93750000 // encoding: [0x0a,0xf0,0x6f,0x1e] - - fmov s12, #-1.0 -// CHECK: fmov s12, #-1.00000000 // encoding: [0x0c,0x10,0x3e,0x1e] - - fmov d16, #8.5 -// CHECK: fmov d16, #8.50000000 // encoding: [0x10,0x30,0x64,0x1e] +// CHECK: prfm pldl1strm, nowhere // encoding: [0bAAA00001,A,A,0xd8] +// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_aarch64_ldr_pcrel_imm19 +// CHECK: prfm #22, somewhere // encoding: [0bAAA10110,A,A,0xd8] +// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_aarch64_ldr_pcrel_imm19 //------------------------------------------------------------------------------ // Load/store exclusive @@ -2473,18 +2430,19 @@ _func: ldrsw x15, [x5, #:lo12:sym] ldr x15, [x5, #:lo12:sym] ldr q3, [x2, #:lo12:sym] -// CHECK: str x15, [x5, #:lo12:sym] // encoding: [0xaf'A',A,A,0xf9'A'] -// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst64_lo12 -// CHECK: ldrb w15, [x5, #:lo12:sym] // encoding: [0xaf'A',A,0x40'A',0x39'A'] -// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst8_lo12 -// CHECK: ldrsh x15, [x5, #:lo12:sym] // encoding: [0xaf'A',A,0x80'A',0x79'A'] -// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst16_lo12 -// CHECK: ldrsw x15, [x5, #:lo12:sym] // encoding: [0xaf'A',A,0x80'A',0xb9'A'] -// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst32_lo12 -// CHECK: ldr x15, [x5, #:lo12:sym] // encoding: [0xaf'A',A,0x40'A',0xf9'A'] -// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst64_lo12 -// CHECK: ldr q3, [x2, #:lo12:sym] // encoding: [0x43'A',A,0xc0'A',0x3d'A'] -// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_a64_ldst128_lo12 + +// CHECK: str x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b00AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: ldrb w15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b01AAAAAA,0x39] +// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale1 +// CHECK: ldrsh x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b10AAAAAA,0x79] +// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale2 +// CHECK: ldrsw x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b10AAAAAA,0xb9] +// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale4 +// CHECK: ldr x15, [x5, :lo12:sym] // encoding: [0xaf,0bAAAAAA00,0b01AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: ldr q3, [x2, :lo12:sym] // encoding: [0x43,0bAAAAAA00,0b11AAAAAA,0x3d] +// CHECK: // fixup A - offset: 0, value: :lo12:sym, kind: fixup_aarch64_ldst_imm12_scale16 prfm pldl1keep, [sp, #8] prfm pldl1strm, [x3] @@ -2506,24 +2464,24 @@ _func: prfm pstl3strm, [x6] prfm #15, [sp] // CHECK: prfm pldl1keep, [sp, #8] // encoding: [0xe0,0x07,0x80,0xf9] -// CHECK: prfm pldl1strm, [x3, #0] // encoding: [0x61,0x00,0x80,0xf9] +// CHECK: prfm pldl1strm, [x3{{(, #0)?}}] // encoding: [0x61,0x00,0x80,0xf9] // CHECK: prfm pldl2keep, [x5, #16] // encoding: [0xa2,0x08,0x80,0xf9] -// CHECK: prfm pldl2strm, [x2, #0] // encoding: [0x43,0x00,0x80,0xf9] -// CHECK: prfm pldl3keep, [x5, #0] // encoding: [0xa4,0x00,0x80,0xf9] -// CHECK: prfm pldl3strm, [x6, #0] // encoding: [0xc5,0x00,0x80,0xf9] +// CHECK: prfm pldl2strm, [x2{{(, #0)?}}] // encoding: [0x43,0x00,0x80,0xf9] +// CHECK: prfm pldl3keep, [x5{{(, #0)?}}] // encoding: [0xa4,0x00,0x80,0xf9] +// CHECK: prfm pldl3strm, [x6{{(, #0)?}}] // encoding: [0xc5,0x00,0x80,0xf9] // CHECK: prfm plil1keep, [sp, #8] // encoding: [0xe8,0x07,0x80,0xf9] -// CHECK: prfm plil1strm, [x3, #0] // encoding: [0x69,0x00,0x80,0xf9] +// CHECK: prfm plil1strm, [x3{{(, #0)?}}] // encoding: [0x69,0x00,0x80,0xf9] // CHECK: prfm plil2keep, [x5, #16] // encoding: [0xaa,0x08,0x80,0xf9] -// CHECK: prfm plil2strm, [x2, #0] // encoding: [0x4b,0x00,0x80,0xf9] -// CHECK: prfm plil3keep, [x5, #0] // encoding: [0xac,0x00,0x80,0xf9] -// CHECK: prfm plil3strm, [x6, #0] // encoding: [0xcd,0x00,0x80,0xf9] +// CHECK: prfm plil2strm, [x2{{(, #0)?}}] // encoding: [0x4b,0x00,0x80,0xf9] +// CHECK: prfm plil3keep, [x5{{(, #0)?}}] // encoding: [0xac,0x00,0x80,0xf9] +// CHECK: prfm plil3strm, [x6{{(, #0)?}}] // encoding: [0xcd,0x00,0x80,0xf9] // CHECK: prfm pstl1keep, [sp, #8] // encoding: [0xf0,0x07,0x80,0xf9] -// CHECK: prfm pstl1strm, [x3, #0] // encoding: [0x71,0x00,0x80,0xf9] +// CHECK: prfm pstl1strm, [x3{{(, #0)?}}] // encoding: [0x71,0x00,0x80,0xf9] // CHECK: prfm pstl2keep, [x5, #16] // encoding: [0xb2,0x08,0x80,0xf9] -// CHECK: prfm pstl2strm, [x2, #0] // encoding: [0x53,0x00,0x80,0xf9] -// CHECK: prfm pstl3keep, [x5, #0] // encoding: [0xb4,0x00,0x80,0xf9] -// CHECK: prfm pstl3strm, [x6, #0] // encoding: [0xd5,0x00,0x80,0xf9] -// CHECK: prfm #15, [sp, #0] // encoding: [0xef,0x03,0x80,0xf9] +// CHECK: prfm pstl2strm, [x2{{(, #0)?}}] // encoding: [0x53,0x00,0x80,0xf9] +// CHECK: prfm pstl3keep, [x5{{(, #0)?}}] // encoding: [0xb4,0x00,0x80,0xf9] +// CHECK: prfm pstl3strm, [x6{{(, #0)?}}] // encoding: [0xd5,0x00,0x80,0xf9] +// CHECK: prfm #15, [sp{{(, #0)?}}] // encoding: [0xef,0x03,0x80,0xf9] //// Floating-point versions @@ -2636,7 +2594,7 @@ _func: // CHECK: ldr x17, [x23, w9, sxtw] // encoding: [0xf1,0xca,0x69,0xf8] // CHECK: ldr x18, [x22, w10, sxtw] // encoding: [0xd2,0xca,0x6a,0xf8] // CHECK: str d19, [x21, wzr, sxtw #3] // encoding: [0xb3,0xda,0x3f,0xfc] -// CHECK: prfm #6, [x0, x5, lsl #0] // encoding: [0x06,0x68,0xa5,0xf8] +// CHECK: prfm #6, [x0, x5{{(, lsl #0)?}}] // encoding: [0x06,0x68,0xa5,0xf8] ldr q3, [sp, x5] ldr q9, [x27, x6, lsl #0] @@ -3218,15 +3176,15 @@ _func: ands wzr, w18, #0xcccccccc ands w19, w20, #0x33333333 ands w21, w22, #0x99999999 -// CHECK: ands wzr, w18, #0xcccccccc // encoding: [0x5f,0xe6,0x02,0x72] +// CHECK: {{ands wzr,|tst}} w18, #0xcccccccc // encoding: [0x5f,0xe6,0x02,0x72] // CHECK: ands w19, w20, #0x33333333 // encoding: [0x93,0xe6,0x00,0x72] // CHECK: ands w21, w22, #0x99999999 // encoding: [0xd5,0xe6,0x01,0x72] // 2 bit replication width tst w3, #0xaaaaaaaa tst wzr, #0x55555555 -// CHECK: ands wzr, w3, #0xaaaaaaaa // encoding: [0x7f,0xf0,0x01,0x72] -// CHECK: ands wzr, wzr, #0x55555555 // encoding: [0xff,0xf3,0x00,0x72] +// CHECK: {{ands wzr,|tst}} w3, #0xaaaaaaaa // encoding: [0x7f,0xf0,0x01,0x72] +// CHECK: {{ands wzr,|tst}} wzr, #0x55555555 // encoding: [0xff,0xf3,0x00,0x72] // 64 bit replication-width eor x3, x5, #0xffffffffc000000 @@ -3264,20 +3222,20 @@ _func: ands xzr, x18, #0xcccccccccccccccc ands x19, x20, #0x3333333333333333 ands x21, x22, #0x9999999999999999 -// CHECK: ands xzr, x18, #0xcccccccccccccccc // encoding: [0x5f,0xe6,0x02,0xf2] +// CHECK: {{ands xzr,|tst}} x18, #0xcccccccccccccccc // encoding: [0x5f,0xe6,0x02,0xf2] // CHECK: ands x19, x20, #0x3333333333333333 // encoding: [0x93,0xe6,0x00,0xf2] // CHECK: ands x21, x22, #0x9999999999999999 // encoding: [0xd5,0xe6,0x01,0xf2] // 2 bit replication-width tst x3, #0xaaaaaaaaaaaaaaaa tst xzr, #0x5555555555555555 -// CHECK: ands xzr, x3, #0xaaaaaaaaaaaaaaaa // encoding: [0x7f,0xf0,0x01,0xf2] -// CHECK: ands xzr, xzr, #0x5555555555555555 // encoding: [0xff,0xf3,0x00,0xf2] +// CHECK: {{ands xzr,|tst}} x3, #0xaaaaaaaaaaaaaaaa // encoding: [0x7f,0xf0,0x01,0xf2] +// CHECK: {{ands xzr,|tst}} xzr, #0x5555555555555555 // encoding: [0xff,0xf3,0x00,0xf2] mov w3, #0xf000f mov x10, #0xaaaaaaaaaaaaaaaa // CHECK: orr w3, wzr, #0xf000f // encoding: [0xe3,0x8f,0x00,0x32] -// CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa // encoding: [0xea,0xf3,0x01,0xb2] +// CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa // encoding: [0xea,0xf3,0x01,0xb2] //------------------------------------------------------------------------------ // Logical (shifted register) @@ -3353,75 +3311,83 @@ _func: movz w1, #65535, lsl #0 movz w2, #0, lsl #16 movn w2, #1234, lsl #0 -// CHECK: movz w1, #65535 // encoding: [0xe1,0xff,0x9f,0x52] +// CHECK: movz w1, #{{65535|0xffff}} // encoding: [0xe1,0xff,0x9f,0x52] // CHECK: movz w2, #0, lsl #16 // encoding: [0x02,0x00,0xa0,0x52] -// CHECK: movn w2, #1234 // encoding: [0x42,0x9a,0x80,0x12] +// CHECK: movn w2, #{{1234|0x4d2}} // encoding: [0x42,0x9a,0x80,0x12] movz x2, #1234, lsl #32 movk xzr, #4321, lsl #48 -// CHECK: movz x2, #1234, lsl #32 // encoding: [0x42,0x9a,0xc0,0xd2] -// CHECK: movk xzr, #4321, lsl #48 // encoding: [0x3f,0x1c,0xe2,0xf2] +// CHECK: movz x2, #{{1234|0x4d2}}, lsl #32 // encoding: [0x42,0x9a,0xc0,0xd2] +// CHECK: movk xzr, #{{4321|0x10e1}}, lsl #48 // encoding: [0x3f,0x1c,0xe2,0xf2] movz x2, #:abs_g0:sym movk w3, #:abs_g0_nc:sym -// CHECK: movz x2, #:abs_g0:sym // encoding: [0x02'A',A,0x80'A',0xd2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_a64_movw_uabs_g0 -// CHECK: movk w3, #:abs_g0_nc:sym // encoding: [0x03'A',A,0x80'A',0x72'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_a64_movw_uabs_g0_nc + +// CHECK: movz x2, #:abs_g0:sym // encoding: [0bAAA00010,A,0b100AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0:sym, kind: fixup_aarch64_movw +// CHECK: movk w3, #:abs_g0_nc:sym // encoding: [0bAAA00011,A,0b100AAAAA,0x72] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_nc:sym, kind: fixup_aarch64_movw movz x4, #:abs_g1:sym movk w5, #:abs_g1_nc:sym -// CHECK: movz x4, #:abs_g1:sym // encoding: [0x04'A',A,0xa0'A',0xd2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_a64_movw_uabs_g1 -// CHECK: movk w5, #:abs_g1_nc:sym // encoding: [0x05'A',A,0xa0'A',0x72'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_a64_movw_uabs_g1_nc + +// CHECK: movz x4, #:abs_g1:sym // encoding: [0bAAA00100,A,0b101AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1:sym, kind: fixup_aarch64_movw +// CHECK: movk w5, #:abs_g1_nc:sym // encoding: [0bAAA00101,A,0b101AAAAA,0x72] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_nc:sym, kind: fixup_aarch64_movw movz x6, #:abs_g2:sym movk x7, #:abs_g2_nc:sym -// CHECK: movz x6, #:abs_g2:sym // encoding: [0x06'A',A,0xc0'A',0xd2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_a64_movw_uabs_g2 -// CHECK: movk x7, #:abs_g2_nc:sym // encoding: [0x07'A',A,0xc0'A',0xf2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_a64_movw_uabs_g2_nc + +// CHECK: movz x6, #:abs_g2:sym // encoding: [0bAAA00110,A,0b110AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2:sym, kind: fixup_aarch64_movw +// CHECK: movk x7, #:abs_g2_nc:sym // encoding: [0bAAA00111,A,0b110AAAAA,0xf2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_nc:sym, kind: fixup_aarch64_movw movz x8, #:abs_g3:sym movk x9, #:abs_g3:sym -// CHECK: movz x8, #:abs_g3:sym // encoding: [0x08'A',A,0xe0'A',0xd2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_a64_movw_uabs_g3 -// CHECK: movk x9, #:abs_g3:sym // encoding: [0x09'A',A,0xe0'A',0xf2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_a64_movw_uabs_g3 + +// CHECK: movz x8, #:abs_g3:sym // encoding: [0bAAA01000,A,0b111AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_aarch64_movw +// CHECK: movk x9, #:abs_g3:sym // encoding: [0bAAA01001,A,0b111AAAAA,0xf2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g3:sym, kind: fixup_aarch64_movw + movn x30, #:abs_g0_s:sym movz x19, #:abs_g0_s:sym movn w10, #:abs_g0_s:sym movz w25, #:abs_g0_s:sym -// CHECK: movn x30, #:abs_g0_s:sym // encoding: [0x1e'A',A,0x80'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0 -// CHECK: movz x19, #:abs_g0_s:sym // encoding: [0x13'A',A,0x80'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0 -// CHECK: movn w10, #:abs_g0_s:sym // encoding: [0x0a'A',A,0x80'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0 -// CHECK: movz w25, #:abs_g0_s:sym // encoding: [0x19'A',A,0x80'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_a64_movw_sabs_g0 + +// CHECK: movn x30, #:abs_g0_s:sym // encoding: [0bAAA11110,A,0b100AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw +// CHECK: movz x19, #:abs_g0_s:sym // encoding: [0bAAA10011,A,0b100AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw +// CHECK: movn w10, #:abs_g0_s:sym // encoding: [0bAAA01010,A,0b100AAAAA,0x12] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw +// CHECK: movz w25, #:abs_g0_s:sym // encoding: [0bAAA11001,A,0b100AAAAA,0x52] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g0_s:sym, kind: fixup_aarch64_movw movn x30, #:abs_g1_s:sym movz x19, #:abs_g1_s:sym movn w10, #:abs_g1_s:sym movz w25, #:abs_g1_s:sym -// CHECK: movn x30, #:abs_g1_s:sym // encoding: [0x1e'A',A,0xa0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1 -// CHECK: movz x19, #:abs_g1_s:sym // encoding: [0x13'A',A,0xa0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1 -// CHECK: movn w10, #:abs_g1_s:sym // encoding: [0x0a'A',A,0xa0'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1 -// CHECK: movz w25, #:abs_g1_s:sym // encoding: [0x19'A',A,0xa0'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_a64_movw_sabs_g1 + +// CHECK: movn x30, #:abs_g1_s:sym // encoding: [0bAAA11110,A,0b101AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_aarch64_movw +// CHECK: movz x19, #:abs_g1_s:sym // encoding: [0bAAA10011,A,0b101AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_aarch64_movw +// CHECK: movn w10, #:abs_g1_s:sym // encoding: [0bAAA01010,A,0b101AAAAA,0x12] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_aarch64_movw +// CHECK: movz w25, #:abs_g1_s:sym // encoding: [0bAAA11001,A,0b101AAAAA,0x52] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g1_s:sym, kind: fixup_aarch64_movw movn x30, #:abs_g2_s:sym movz x19, #:abs_g2_s:sym -// CHECK: movn x30, #:abs_g2_s:sym // encoding: [0x1e'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_a64_movw_sabs_g2 -// CHECK: movz x19, #:abs_g2_s:sym // encoding: [0x13'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_a64_movw_sabs_g2 + +// CHECK: movn x30, #:abs_g2_s:sym // encoding: [0bAAA11110,A,0b110AAAAA,0x92] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_aarch64_movw +// CHECK: movz x19, #:abs_g2_s:sym // encoding: [0bAAA10011,A,0b110AAAAA,0xd2] +// CHECK-NEXT: // fixup A - offset: 0, value: :abs_g2_s:sym, kind: fixup_aarch64_movw //------------------------------------------------------------------------------ // PC-relative addressing @@ -3429,15 +3395,16 @@ _func: adr x2, loc adr xzr, loc - // CHECK: adr x2, loc // encoding: [0x02'A',A,A,0x10'A'] - // CHECK: // fixup A - offset: 0, value: loc, kind: fixup_a64_adr_prel - // CHECK: adr xzr, loc // encoding: [0x1f'A',A,A,0x10'A'] - // CHECK: // fixup A - offset: 0, value: loc, kind: fixup_a64_adr_prel + +// CHECK: adr x2, loc // encoding: [0x02'A',A,A,0x10'A'] +// CHECK: // fixup A - offset: 0, value: loc, kind: fixup_aarch64_pcrel_adr_imm21 +// CHECK: adr xzr, loc // encoding: [0x1f'A',A,A,0x10'A'] +// CHECK: // fixup A - offset: 0, value: loc, kind: fixup_aarch64_pcrel_adr_imm21 adrp x29, loc - // CHECK: adrp x29, loc // encoding: [0x1d'A',A,A,0x90'A'] - // CHECK: // fixup A - offset: 0, value: loc, kind: fixup_a64_adr_prel_page +// CHECK: adrp x29, loc // encoding: [0x1d'A',A,A,0x90'A'] +// CHECK: // fixup A - offset: 0, value: loc, kind: fixup_aarch64_pcrel_adrp_imm21 adrp x30, #4096 adr x20, #0 adr x9, #-1 @@ -3463,7 +3430,7 @@ _func: hint #0 hint #127 // CHECK: nop // encoding: [0x1f,0x20,0x03,0xd5] -// CHECK: hint #127 // encoding: [0xff,0x2f,0x03,0xd5] +// CHECK: hint #{{127|0x7f}} // encoding: [0xff,0x2f,0x03,0xd5] nop yield @@ -3560,14 +3527,14 @@ _func: msr spsel, #0 msr daifset, #15 msr daifclr, #12 -// CHECK: msr spsel, #0 // encoding: [0xbf,0x40,0x00,0xd5] -// CHECK: msr daifset, #15 // encoding: [0xdf,0x4f,0x03,0xd5] -// CHECK: msr daifclr, #12 // encoding: [0xff,0x4c,0x03,0xd5] +// CHECK: msr {{spsel|SPSEL}}, #0 // encoding: [0xbf,0x40,0x00,0xd5] +// CHECK: msr {{daifset|DAIFSET}}, #15 // encoding: [0xdf,0x4f,0x03,0xd5] +// CHECK: msr {{daifclr|DAIFCLR}}, #12 // encoding: [0xff,0x4c,0x03,0xd5] sys #7, c5, c9, #7, x5 sys #0, c15, c15, #2 // CHECK: sys #7, c5, c9, #7, x5 // encoding: [0xe5,0x59,0x0f,0xd5] -// CHECK: sys #0, c15, c15, #2, xzr // encoding: [0x5f,0xff,0x08,0xd5] +// CHECK: sys #0, c15, c15, #2 // encoding: [0x5f,0xff,0x08,0xd5] sysl x9, #7, c5, c9, #7 sysl x1, #0, c15, c15, #2 @@ -3942,260 +3909,260 @@ _func: msr PMEVTYPER28_EL0, x12 msr PMEVTYPER29_EL0, x12 msr PMEVTYPER30_EL0, x12 -// CHECK: msr teecr32_el1, x12 // encoding: [0x0c,0x00,0x12,0xd5] -// CHECK: msr osdtrrx_el1, x12 // encoding: [0x4c,0x00,0x10,0xd5] -// CHECK: msr mdccint_el1, x12 // encoding: [0x0c,0x02,0x10,0xd5] -// CHECK: msr mdscr_el1, x12 // encoding: [0x4c,0x02,0x10,0xd5] -// CHECK: msr osdtrtx_el1, x12 // encoding: [0x4c,0x03,0x10,0xd5] -// CHECK: msr dbgdtr_el0, x12 // encoding: [0x0c,0x04,0x13,0xd5] -// CHECK: msr dbgdtrtx_el0, x12 // encoding: [0x0c,0x05,0x13,0xd5] -// CHECK: msr oseccr_el1, x12 // encoding: [0x4c,0x06,0x10,0xd5] -// CHECK: msr dbgvcr32_el2, x12 // encoding: [0x0c,0x07,0x14,0xd5] -// CHECK: msr dbgbvr0_el1, x12 // encoding: [0x8c,0x00,0x10,0xd5] -// CHECK: msr dbgbvr1_el1, x12 // encoding: [0x8c,0x01,0x10,0xd5] -// CHECK: msr dbgbvr2_el1, x12 // encoding: [0x8c,0x02,0x10,0xd5] -// CHECK: msr dbgbvr3_el1, x12 // encoding: [0x8c,0x03,0x10,0xd5] -// CHECK: msr dbgbvr4_el1, x12 // encoding: [0x8c,0x04,0x10,0xd5] -// CHECK: msr dbgbvr5_el1, x12 // encoding: [0x8c,0x05,0x10,0xd5] -// CHECK: msr dbgbvr6_el1, x12 // encoding: [0x8c,0x06,0x10,0xd5] -// CHECK: msr dbgbvr7_el1, x12 // encoding: [0x8c,0x07,0x10,0xd5] -// CHECK: msr dbgbvr8_el1, x12 // encoding: [0x8c,0x08,0x10,0xd5] -// CHECK: msr dbgbvr9_el1, x12 // encoding: [0x8c,0x09,0x10,0xd5] -// CHECK: msr dbgbvr10_el1, x12 // encoding: [0x8c,0x0a,0x10,0xd5] -// CHECK: msr dbgbvr11_el1, x12 // encoding: [0x8c,0x0b,0x10,0xd5] -// CHECK: msr dbgbvr12_el1, x12 // encoding: [0x8c,0x0c,0x10,0xd5] -// CHECK: msr dbgbvr13_el1, x12 // encoding: [0x8c,0x0d,0x10,0xd5] -// CHECK: msr dbgbvr14_el1, x12 // encoding: [0x8c,0x0e,0x10,0xd5] -// CHECK: msr dbgbvr15_el1, x12 // encoding: [0x8c,0x0f,0x10,0xd5] -// CHECK: msr dbgbcr0_el1, x12 // encoding: [0xac,0x00,0x10,0xd5] -// CHECK: msr dbgbcr1_el1, x12 // encoding: [0xac,0x01,0x10,0xd5] -// CHECK: msr dbgbcr2_el1, x12 // encoding: [0xac,0x02,0x10,0xd5] -// CHECK: msr dbgbcr3_el1, x12 // encoding: [0xac,0x03,0x10,0xd5] -// CHECK: msr dbgbcr4_el1, x12 // encoding: [0xac,0x04,0x10,0xd5] -// CHECK: msr dbgbcr5_el1, x12 // encoding: [0xac,0x05,0x10,0xd5] -// CHECK: msr dbgbcr6_el1, x12 // encoding: [0xac,0x06,0x10,0xd5] -// CHECK: msr dbgbcr7_el1, x12 // encoding: [0xac,0x07,0x10,0xd5] -// CHECK: msr dbgbcr8_el1, x12 // encoding: [0xac,0x08,0x10,0xd5] -// CHECK: msr dbgbcr9_el1, x12 // encoding: [0xac,0x09,0x10,0xd5] -// CHECK: msr dbgbcr10_el1, x12 // encoding: [0xac,0x0a,0x10,0xd5] -// CHECK: msr dbgbcr11_el1, x12 // encoding: [0xac,0x0b,0x10,0xd5] -// CHECK: msr dbgbcr12_el1, x12 // encoding: [0xac,0x0c,0x10,0xd5] -// CHECK: msr dbgbcr13_el1, x12 // encoding: [0xac,0x0d,0x10,0xd5] -// CHECK: msr dbgbcr14_el1, x12 // encoding: [0xac,0x0e,0x10,0xd5] -// CHECK: msr dbgbcr15_el1, x12 // encoding: [0xac,0x0f,0x10,0xd5] -// CHECK: msr dbgwvr0_el1, x12 // encoding: [0xcc,0x00,0x10,0xd5] -// CHECK: msr dbgwvr1_el1, x12 // encoding: [0xcc,0x01,0x10,0xd5] -// CHECK: msr dbgwvr2_el1, x12 // encoding: [0xcc,0x02,0x10,0xd5] -// CHECK: msr dbgwvr3_el1, x12 // encoding: [0xcc,0x03,0x10,0xd5] -// CHECK: msr dbgwvr4_el1, x12 // encoding: [0xcc,0x04,0x10,0xd5] -// CHECK: msr dbgwvr5_el1, x12 // encoding: [0xcc,0x05,0x10,0xd5] -// CHECK: msr dbgwvr6_el1, x12 // encoding: [0xcc,0x06,0x10,0xd5] -// CHECK: msr dbgwvr7_el1, x12 // encoding: [0xcc,0x07,0x10,0xd5] -// CHECK: msr dbgwvr8_el1, x12 // encoding: [0xcc,0x08,0x10,0xd5] -// CHECK: msr dbgwvr9_el1, x12 // encoding: [0xcc,0x09,0x10,0xd5] -// CHECK: msr dbgwvr10_el1, x12 // encoding: [0xcc,0x0a,0x10,0xd5] -// CHECK: msr dbgwvr11_el1, x12 // encoding: [0xcc,0x0b,0x10,0xd5] -// CHECK: msr dbgwvr12_el1, x12 // encoding: [0xcc,0x0c,0x10,0xd5] -// CHECK: msr dbgwvr13_el1, x12 // encoding: [0xcc,0x0d,0x10,0xd5] -// CHECK: msr dbgwvr14_el1, x12 // encoding: [0xcc,0x0e,0x10,0xd5] -// CHECK: msr dbgwvr15_el1, x12 // encoding: [0xcc,0x0f,0x10,0xd5] -// CHECK: msr dbgwcr0_el1, x12 // encoding: [0xec,0x00,0x10,0xd5] -// CHECK: msr dbgwcr1_el1, x12 // encoding: [0xec,0x01,0x10,0xd5] -// CHECK: msr dbgwcr2_el1, x12 // encoding: [0xec,0x02,0x10,0xd5] -// CHECK: msr dbgwcr3_el1, x12 // encoding: [0xec,0x03,0x10,0xd5] -// CHECK: msr dbgwcr4_el1, x12 // encoding: [0xec,0x04,0x10,0xd5] -// CHECK: msr dbgwcr5_el1, x12 // encoding: [0xec,0x05,0x10,0xd5] -// CHECK: msr dbgwcr6_el1, x12 // encoding: [0xec,0x06,0x10,0xd5] -// CHECK: msr dbgwcr7_el1, x12 // encoding: [0xec,0x07,0x10,0xd5] -// CHECK: msr dbgwcr8_el1, x12 // encoding: [0xec,0x08,0x10,0xd5] -// CHECK: msr dbgwcr9_el1, x12 // encoding: [0xec,0x09,0x10,0xd5] -// CHECK: msr dbgwcr10_el1, x12 // encoding: [0xec,0x0a,0x10,0xd5] -// CHECK: msr dbgwcr11_el1, x12 // encoding: [0xec,0x0b,0x10,0xd5] -// CHECK: msr dbgwcr12_el1, x12 // encoding: [0xec,0x0c,0x10,0xd5] -// CHECK: msr dbgwcr13_el1, x12 // encoding: [0xec,0x0d,0x10,0xd5] -// CHECK: msr dbgwcr14_el1, x12 // encoding: [0xec,0x0e,0x10,0xd5] -// CHECK: msr dbgwcr15_el1, x12 // encoding: [0xec,0x0f,0x10,0xd5] -// CHECK: msr teehbr32_el1, x12 // encoding: [0x0c,0x10,0x12,0xd5] -// CHECK: msr oslar_el1, x12 // encoding: [0x8c,0x10,0x10,0xd5] -// CHECK: msr osdlr_el1, x12 // encoding: [0x8c,0x13,0x10,0xd5] -// CHECK: msr dbgprcr_el1, x12 // encoding: [0x8c,0x14,0x10,0xd5] -// CHECK: msr dbgclaimset_el1, x12 // encoding: [0xcc,0x78,0x10,0xd5] -// CHECK: msr dbgclaimclr_el1, x12 // encoding: [0xcc,0x79,0x10,0xd5] -// CHECK: msr csselr_el1, x12 // encoding: [0x0c,0x00,0x1a,0xd5] -// CHECK: msr vpidr_el2, x12 // encoding: [0x0c,0x00,0x1c,0xd5] -// CHECK: msr vmpidr_el2, x12 // encoding: [0xac,0x00,0x1c,0xd5] -// CHECK: msr sctlr_el1, x12 // encoding: [0x0c,0x10,0x18,0xd5] -// CHECK: msr sctlr_el2, x12 // encoding: [0x0c,0x10,0x1c,0xd5] -// CHECK: msr sctlr_el3, x12 // encoding: [0x0c,0x10,0x1e,0xd5] -// CHECK: msr actlr_el1, x12 // encoding: [0x2c,0x10,0x18,0xd5] -// CHECK: msr actlr_el2, x12 // encoding: [0x2c,0x10,0x1c,0xd5] -// CHECK: msr actlr_el3, x12 // encoding: [0x2c,0x10,0x1e,0xd5] -// CHECK: msr cpacr_el1, x12 // encoding: [0x4c,0x10,0x18,0xd5] -// CHECK: msr hcr_el2, x12 // encoding: [0x0c,0x11,0x1c,0xd5] -// CHECK: msr scr_el3, x12 // encoding: [0x0c,0x11,0x1e,0xd5] -// CHECK: msr mdcr_el2, x12 // encoding: [0x2c,0x11,0x1c,0xd5] -// CHECK: msr sder32_el3, x12 // encoding: [0x2c,0x11,0x1e,0xd5] -// CHECK: msr cptr_el2, x12 // encoding: [0x4c,0x11,0x1c,0xd5] -// CHECK: msr cptr_el3, x12 // encoding: [0x4c,0x11,0x1e,0xd5] -// CHECK: msr hstr_el2, x12 // encoding: [0x6c,0x11,0x1c,0xd5] -// CHECK: msr hacr_el2, x12 // encoding: [0xec,0x11,0x1c,0xd5] -// CHECK: msr mdcr_el3, x12 // encoding: [0x2c,0x13,0x1e,0xd5] -// CHECK: msr ttbr0_el1, x12 // encoding: [0x0c,0x20,0x18,0xd5] -// CHECK: msr ttbr0_el2, x12 // encoding: [0x0c,0x20,0x1c,0xd5] -// CHECK: msr ttbr0_el3, x12 // encoding: [0x0c,0x20,0x1e,0xd5] -// CHECK: msr ttbr1_el1, x12 // encoding: [0x2c,0x20,0x18,0xd5] -// CHECK: msr tcr_el1, x12 // encoding: [0x4c,0x20,0x18,0xd5] -// CHECK: msr tcr_el2, x12 // encoding: [0x4c,0x20,0x1c,0xd5] -// CHECK: msr tcr_el3, x12 // encoding: [0x4c,0x20,0x1e,0xd5] -// CHECK: msr vttbr_el2, x12 // encoding: [0x0c,0x21,0x1c,0xd5] -// CHECK: msr vtcr_el2, x12 // encoding: [0x4c,0x21,0x1c,0xd5] -// CHECK: msr dacr32_el2, x12 // encoding: [0x0c,0x30,0x1c,0xd5] -// CHECK: msr spsr_el1, x12 // encoding: [0x0c,0x40,0x18,0xd5] -// CHECK: msr spsr_el2, x12 // encoding: [0x0c,0x40,0x1c,0xd5] -// CHECK: msr spsr_el3, x12 // encoding: [0x0c,0x40,0x1e,0xd5] -// CHECK: msr elr_el1, x12 // encoding: [0x2c,0x40,0x18,0xd5] -// CHECK: msr elr_el2, x12 // encoding: [0x2c,0x40,0x1c,0xd5] -// CHECK: msr elr_el3, x12 // encoding: [0x2c,0x40,0x1e,0xd5] -// CHECK: msr sp_el0, x12 // encoding: [0x0c,0x41,0x18,0xd5] -// CHECK: msr sp_el1, x12 // encoding: [0x0c,0x41,0x1c,0xd5] -// CHECK: msr sp_el2, x12 // encoding: [0x0c,0x41,0x1e,0xd5] -// CHECK: msr spsel, x12 // encoding: [0x0c,0x42,0x18,0xd5] -// CHECK: msr nzcv, x12 // encoding: [0x0c,0x42,0x1b,0xd5] -// CHECK: msr daif, x12 // encoding: [0x2c,0x42,0x1b,0xd5] -// CHECK: msr currentel, x12 // encoding: [0x4c,0x42,0x18,0xd5] -// CHECK: msr spsr_irq, x12 // encoding: [0x0c,0x43,0x1c,0xd5] -// CHECK: msr spsr_abt, x12 // encoding: [0x2c,0x43,0x1c,0xd5] -// CHECK: msr spsr_und, x12 // encoding: [0x4c,0x43,0x1c,0xd5] -// CHECK: msr spsr_fiq, x12 // encoding: [0x6c,0x43,0x1c,0xd5] -// CHECK: msr fpcr, x12 // encoding: [0x0c,0x44,0x1b,0xd5] -// CHECK: msr fpsr, x12 // encoding: [0x2c,0x44,0x1b,0xd5] -// CHECK: msr dspsr_el0, x12 // encoding: [0x0c,0x45,0x1b,0xd5] -// CHECK: msr dlr_el0, x12 // encoding: [0x2c,0x45,0x1b,0xd5] -// CHECK: msr ifsr32_el2, x12 // encoding: [0x2c,0x50,0x1c,0xd5] -// CHECK: msr afsr0_el1, x12 // encoding: [0x0c,0x51,0x18,0xd5] -// CHECK: msr afsr0_el2, x12 // encoding: [0x0c,0x51,0x1c,0xd5] -// CHECK: msr afsr0_el3, x12 // encoding: [0x0c,0x51,0x1e,0xd5] -// CHECK: msr afsr1_el1, x12 // encoding: [0x2c,0x51,0x18,0xd5] -// CHECK: msr afsr1_el2, x12 // encoding: [0x2c,0x51,0x1c,0xd5] -// CHECK: msr afsr1_el3, x12 // encoding: [0x2c,0x51,0x1e,0xd5] -// CHECK: msr esr_el1, x12 // encoding: [0x0c,0x52,0x18,0xd5] -// CHECK: msr esr_el2, x12 // encoding: [0x0c,0x52,0x1c,0xd5] -// CHECK: msr esr_el3, x12 // encoding: [0x0c,0x52,0x1e,0xd5] -// CHECK: msr fpexc32_el2, x12 // encoding: [0x0c,0x53,0x1c,0xd5] -// CHECK: msr far_el1, x12 // encoding: [0x0c,0x60,0x18,0xd5] -// CHECK: msr far_el2, x12 // encoding: [0x0c,0x60,0x1c,0xd5] -// CHECK: msr far_el3, x12 // encoding: [0x0c,0x60,0x1e,0xd5] -// CHECK: msr hpfar_el2, x12 // encoding: [0x8c,0x60,0x1c,0xd5] -// CHECK: msr par_el1, x12 // encoding: [0x0c,0x74,0x18,0xd5] -// CHECK: msr pmcr_el0, x12 // encoding: [0x0c,0x9c,0x1b,0xd5] -// CHECK: msr pmcntenset_el0, x12 // encoding: [0x2c,0x9c,0x1b,0xd5] -// CHECK: msr pmcntenclr_el0, x12 // encoding: [0x4c,0x9c,0x1b,0xd5] -// CHECK: msr pmovsclr_el0, x12 // encoding: [0x6c,0x9c,0x1b,0xd5] -// CHECK: msr pmselr_el0, x12 // encoding: [0xac,0x9c,0x1b,0xd5] -// CHECK: msr pmccntr_el0, x12 // encoding: [0x0c,0x9d,0x1b,0xd5] -// CHECK: msr pmxevtyper_el0, x12 // encoding: [0x2c,0x9d,0x1b,0xd5] -// CHECK: msr pmxevcntr_el0, x12 // encoding: [0x4c,0x9d,0x1b,0xd5] -// CHECK: msr pmuserenr_el0, x12 // encoding: [0x0c,0x9e,0x1b,0xd5] -// CHECK: msr pmintenset_el1, x12 // encoding: [0x2c,0x9e,0x18,0xd5] -// CHECK: msr pmintenclr_el1, x12 // encoding: [0x4c,0x9e,0x18,0xd5] -// CHECK: msr pmovsset_el0, x12 // encoding: [0x6c,0x9e,0x1b,0xd5] -// CHECK: msr mair_el1, x12 // encoding: [0x0c,0xa2,0x18,0xd5] -// CHECK: msr mair_el2, x12 // encoding: [0x0c,0xa2,0x1c,0xd5] -// CHECK: msr mair_el3, x12 // encoding: [0x0c,0xa2,0x1e,0xd5] -// CHECK: msr amair_el1, x12 // encoding: [0x0c,0xa3,0x18,0xd5] -// CHECK: msr amair_el2, x12 // encoding: [0x0c,0xa3,0x1c,0xd5] -// CHECK: msr amair_el3, x12 // encoding: [0x0c,0xa3,0x1e,0xd5] -// CHECK: msr vbar_el1, x12 // encoding: [0x0c,0xc0,0x18,0xd5] -// CHECK: msr vbar_el2, x12 // encoding: [0x0c,0xc0,0x1c,0xd5] -// CHECK: msr vbar_el3, x12 // encoding: [0x0c,0xc0,0x1e,0xd5] -// CHECK: msr rmr_el1, x12 // encoding: [0x4c,0xc0,0x18,0xd5] -// CHECK: msr rmr_el2, x12 // encoding: [0x4c,0xc0,0x1c,0xd5] -// CHECK: msr rmr_el3, x12 // encoding: [0x4c,0xc0,0x1e,0xd5] -// CHECK: msr contextidr_el1, x12 // encoding: [0x2c,0xd0,0x18,0xd5] -// CHECK: msr tpidr_el0, x12 // encoding: [0x4c,0xd0,0x1b,0xd5] -// CHECK: msr tpidr_el2, x12 // encoding: [0x4c,0xd0,0x1c,0xd5] -// CHECK: msr tpidr_el3, x12 // encoding: [0x4c,0xd0,0x1e,0xd5] -// CHECK: msr tpidrro_el0, x12 // encoding: [0x6c,0xd0,0x1b,0xd5] -// CHECK: msr tpidr_el1, x12 // encoding: [0x8c,0xd0,0x18,0xd5] -// CHECK: msr cntfrq_el0, x12 // encoding: [0x0c,0xe0,0x1b,0xd5] -// CHECK: msr cntvoff_el2, x12 // encoding: [0x6c,0xe0,0x1c,0xd5] -// CHECK: msr cntkctl_el1, x12 // encoding: [0x0c,0xe1,0x18,0xd5] -// CHECK: msr cnthctl_el2, x12 // encoding: [0x0c,0xe1,0x1c,0xd5] -// CHECK: msr cntp_tval_el0, x12 // encoding: [0x0c,0xe2,0x1b,0xd5] -// CHECK: msr cnthp_tval_el2, x12 // encoding: [0x0c,0xe2,0x1c,0xd5] -// CHECK: msr cntps_tval_el1, x12 // encoding: [0x0c,0xe2,0x1f,0xd5] -// CHECK: msr cntp_ctl_el0, x12 // encoding: [0x2c,0xe2,0x1b,0xd5] -// CHECK: msr cnthp_ctl_el2, x12 // encoding: [0x2c,0xe2,0x1c,0xd5] -// CHECK: msr cntps_ctl_el1, x12 // encoding: [0x2c,0xe2,0x1f,0xd5] -// CHECK: msr cntp_cval_el0, x12 // encoding: [0x4c,0xe2,0x1b,0xd5] -// CHECK: msr cnthp_cval_el2, x12 // encoding: [0x4c,0xe2,0x1c,0xd5] -// CHECK: msr cntps_cval_el1, x12 // encoding: [0x4c,0xe2,0x1f,0xd5] -// CHECK: msr cntv_tval_el0, x12 // encoding: [0x0c,0xe3,0x1b,0xd5] -// CHECK: msr cntv_ctl_el0, x12 // encoding: [0x2c,0xe3,0x1b,0xd5] -// CHECK: msr cntv_cval_el0, x12 // encoding: [0x4c,0xe3,0x1b,0xd5] -// CHECK: msr pmevcntr0_el0, x12 // encoding: [0x0c,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr1_el0, x12 // encoding: [0x2c,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr2_el0, x12 // encoding: [0x4c,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr3_el0, x12 // encoding: [0x6c,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr4_el0, x12 // encoding: [0x8c,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr5_el0, x12 // encoding: [0xac,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr6_el0, x12 // encoding: [0xcc,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr7_el0, x12 // encoding: [0xec,0xe8,0x1b,0xd5] -// CHECK: msr pmevcntr8_el0, x12 // encoding: [0x0c,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr9_el0, x12 // encoding: [0x2c,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr10_el0, x12 // encoding: [0x4c,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr11_el0, x12 // encoding: [0x6c,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr12_el0, x12 // encoding: [0x8c,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr13_el0, x12 // encoding: [0xac,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr14_el0, x12 // encoding: [0xcc,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr15_el0, x12 // encoding: [0xec,0xe9,0x1b,0xd5] -// CHECK: msr pmevcntr16_el0, x12 // encoding: [0x0c,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr17_el0, x12 // encoding: [0x2c,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr18_el0, x12 // encoding: [0x4c,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr19_el0, x12 // encoding: [0x6c,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr20_el0, x12 // encoding: [0x8c,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr21_el0, x12 // encoding: [0xac,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr22_el0, x12 // encoding: [0xcc,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr23_el0, x12 // encoding: [0xec,0xea,0x1b,0xd5] -// CHECK: msr pmevcntr24_el0, x12 // encoding: [0x0c,0xeb,0x1b,0xd5] -// CHECK: msr pmevcntr25_el0, x12 // encoding: [0x2c,0xeb,0x1b,0xd5] -// CHECK: msr pmevcntr26_el0, x12 // encoding: [0x4c,0xeb,0x1b,0xd5] -// CHECK: msr pmevcntr27_el0, x12 // encoding: [0x6c,0xeb,0x1b,0xd5] -// CHECK: msr pmevcntr28_el0, x12 // encoding: [0x8c,0xeb,0x1b,0xd5] -// CHECK: msr pmevcntr29_el0, x12 // encoding: [0xac,0xeb,0x1b,0xd5] -// CHECK: msr pmevcntr30_el0, x12 // encoding: [0xcc,0xeb,0x1b,0xd5] -// CHECK: msr pmccfiltr_el0, x12 // encoding: [0xec,0xef,0x1b,0xd5] -// CHECK: msr pmevtyper0_el0, x12 // encoding: [0x0c,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper1_el0, x12 // encoding: [0x2c,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper2_el0, x12 // encoding: [0x4c,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper3_el0, x12 // encoding: [0x6c,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper4_el0, x12 // encoding: [0x8c,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper5_el0, x12 // encoding: [0xac,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper6_el0, x12 // encoding: [0xcc,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper7_el0, x12 // encoding: [0xec,0xec,0x1b,0xd5] -// CHECK: msr pmevtyper8_el0, x12 // encoding: [0x0c,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper9_el0, x12 // encoding: [0x2c,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper10_el0, x12 // encoding: [0x4c,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper11_el0, x12 // encoding: [0x6c,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper12_el0, x12 // encoding: [0x8c,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper13_el0, x12 // encoding: [0xac,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper14_el0, x12 // encoding: [0xcc,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper15_el0, x12 // encoding: [0xec,0xed,0x1b,0xd5] -// CHECK: msr pmevtyper16_el0, x12 // encoding: [0x0c,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper17_el0, x12 // encoding: [0x2c,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper18_el0, x12 // encoding: [0x4c,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper19_el0, x12 // encoding: [0x6c,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper20_el0, x12 // encoding: [0x8c,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper21_el0, x12 // encoding: [0xac,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper22_el0, x12 // encoding: [0xcc,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper23_el0, x12 // encoding: [0xec,0xee,0x1b,0xd5] -// CHECK: msr pmevtyper24_el0, x12 // encoding: [0x0c,0xef,0x1b,0xd5] -// CHECK: msr pmevtyper25_el0, x12 // encoding: [0x2c,0xef,0x1b,0xd5] -// CHECK: msr pmevtyper26_el0, x12 // encoding: [0x4c,0xef,0x1b,0xd5] -// CHECK: msr pmevtyper27_el0, x12 // encoding: [0x6c,0xef,0x1b,0xd5] -// CHECK: msr pmevtyper28_el0, x12 // encoding: [0x8c,0xef,0x1b,0xd5] -// CHECK: msr pmevtyper29_el0, x12 // encoding: [0xac,0xef,0x1b,0xd5] -// CHECK: msr pmevtyper30_el0, x12 // encoding: [0xcc,0xef,0x1b,0xd5] +// CHECK: msr {{teecr32_el1|TEECR32_EL1}}, x12 // encoding: [0x0c,0x00,0x12,0xd5] +// CHECK: msr {{osdtrrx_el1|OSDTRRX_EL1}}, x12 // encoding: [0x4c,0x00,0x10,0xd5] +// CHECK: msr {{mdccint_el1|MDCCINT_EL1}}, x12 // encoding: [0x0c,0x02,0x10,0xd5] +// CHECK: msr {{mdscr_el1|MDSCR_EL1}}, x12 // encoding: [0x4c,0x02,0x10,0xd5] +// CHECK: msr {{osdtrtx_el1|OSDTRTX_EL1}}, x12 // encoding: [0x4c,0x03,0x10,0xd5] +// CHECK: msr {{dbgdtr_el0|DBGDTR_EL0}}, x12 // encoding: [0x0c,0x04,0x13,0xd5] +// CHECK: msr {{dbgdtrtx_el0|DBGDTRTX_EL0}}, x12 // encoding: [0x0c,0x05,0x13,0xd5] +// CHECK: msr {{oseccr_el1|OSECCR_EL1}}, x12 // encoding: [0x4c,0x06,0x10,0xd5] +// CHECK: msr {{dbgvcr32_el2|DBGVCR32_EL2}}, x12 // encoding: [0x0c,0x07,0x14,0xd5] +// CHECK: msr {{dbgbvr0_el1|DBGBVR0_EL1}}, x12 // encoding: [0x8c,0x00,0x10,0xd5] +// CHECK: msr {{dbgbvr1_el1|DBGBVR1_EL1}}, x12 // encoding: [0x8c,0x01,0x10,0xd5] +// CHECK: msr {{dbgbvr2_el1|DBGBVR2_EL1}}, x12 // encoding: [0x8c,0x02,0x10,0xd5] +// CHECK: msr {{dbgbvr3_el1|DBGBVR3_EL1}}, x12 // encoding: [0x8c,0x03,0x10,0xd5] +// CHECK: msr {{dbgbvr4_el1|DBGBVR4_EL1}}, x12 // encoding: [0x8c,0x04,0x10,0xd5] +// CHECK: msr {{dbgbvr5_el1|DBGBVR5_EL1}}, x12 // encoding: [0x8c,0x05,0x10,0xd5] +// CHECK: msr {{dbgbvr6_el1|DBGBVR6_EL1}}, x12 // encoding: [0x8c,0x06,0x10,0xd5] +// CHECK: msr {{dbgbvr7_el1|DBGBVR7_EL1}}, x12 // encoding: [0x8c,0x07,0x10,0xd5] +// CHECK: msr {{dbgbvr8_el1|DBGBVR8_EL1}}, x12 // encoding: [0x8c,0x08,0x10,0xd5] +// CHECK: msr {{dbgbvr9_el1|DBGBVR9_EL1}}, x12 // encoding: [0x8c,0x09,0x10,0xd5] +// CHECK: msr {{dbgbvr10_el1|DBGBVR10_EL1}}, x12 // encoding: [0x8c,0x0a,0x10,0xd5] +// CHECK: msr {{dbgbvr11_el1|DBGBVR11_EL1}}, x12 // encoding: [0x8c,0x0b,0x10,0xd5] +// CHECK: msr {{dbgbvr12_el1|DBGBVR12_EL1}}, x12 // encoding: [0x8c,0x0c,0x10,0xd5] +// CHECK: msr {{dbgbvr13_el1|DBGBVR13_EL1}}, x12 // encoding: [0x8c,0x0d,0x10,0xd5] +// CHECK: msr {{dbgbvr14_el1|DBGBVR14_EL1}}, x12 // encoding: [0x8c,0x0e,0x10,0xd5] +// CHECK: msr {{dbgbvr15_el1|DBGBVR15_EL1}}, x12 // encoding: [0x8c,0x0f,0x10,0xd5] +// CHECK: msr {{dbgbcr0_el1|DBGBCR0_EL1}}, x12 // encoding: [0xac,0x00,0x10,0xd5] +// CHECK: msr {{dbgbcr1_el1|DBGBCR1_EL1}}, x12 // encoding: [0xac,0x01,0x10,0xd5] +// CHECK: msr {{dbgbcr2_el1|DBGBCR2_EL1}}, x12 // encoding: [0xac,0x02,0x10,0xd5] +// CHECK: msr {{dbgbcr3_el1|DBGBCR3_EL1}}, x12 // encoding: [0xac,0x03,0x10,0xd5] +// CHECK: msr {{dbgbcr4_el1|DBGBCR4_EL1}}, x12 // encoding: [0xac,0x04,0x10,0xd5] +// CHECK: msr {{dbgbcr5_el1|DBGBCR5_EL1}}, x12 // encoding: [0xac,0x05,0x10,0xd5] +// CHECK: msr {{dbgbcr6_el1|DBGBCR6_EL1}}, x12 // encoding: [0xac,0x06,0x10,0xd5] +// CHECK: msr {{dbgbcr7_el1|DBGBCR7_EL1}}, x12 // encoding: [0xac,0x07,0x10,0xd5] +// CHECK: msr {{dbgbcr8_el1|DBGBCR8_EL1}}, x12 // encoding: [0xac,0x08,0x10,0xd5] +// CHECK: msr {{dbgbcr9_el1|DBGBCR9_EL1}}, x12 // encoding: [0xac,0x09,0x10,0xd5] +// CHECK: msr {{dbgbcr10_el1|DBGBCR10_EL1}}, x12 // encoding: [0xac,0x0a,0x10,0xd5] +// CHECK: msr {{dbgbcr11_el1|DBGBCR11_EL1}}, x12 // encoding: [0xac,0x0b,0x10,0xd5] +// CHECK: msr {{dbgbcr12_el1|DBGBCR12_EL1}}, x12 // encoding: [0xac,0x0c,0x10,0xd5] +// CHECK: msr {{dbgbcr13_el1|DBGBCR13_EL1}}, x12 // encoding: [0xac,0x0d,0x10,0xd5] +// CHECK: msr {{dbgbcr14_el1|DBGBCR14_EL1}}, x12 // encoding: [0xac,0x0e,0x10,0xd5] +// CHECK: msr {{dbgbcr15_el1|DBGBCR15_EL1}}, x12 // encoding: [0xac,0x0f,0x10,0xd5] +// CHECK: msr {{dbgwvr0_el1|DBGWVR0_EL1}}, x12 // encoding: [0xcc,0x00,0x10,0xd5] +// CHECK: msr {{dbgwvr1_el1|DBGWVR1_EL1}}, x12 // encoding: [0xcc,0x01,0x10,0xd5] +// CHECK: msr {{dbgwvr2_el1|DBGWVR2_EL1}}, x12 // encoding: [0xcc,0x02,0x10,0xd5] +// CHECK: msr {{dbgwvr3_el1|DBGWVR3_EL1}}, x12 // encoding: [0xcc,0x03,0x10,0xd5] +// CHECK: msr {{dbgwvr4_el1|DBGWVR4_EL1}}, x12 // encoding: [0xcc,0x04,0x10,0xd5] +// CHECK: msr {{dbgwvr5_el1|DBGWVR5_EL1}}, x12 // encoding: [0xcc,0x05,0x10,0xd5] +// CHECK: msr {{dbgwvr6_el1|DBGWVR6_EL1}}, x12 // encoding: [0xcc,0x06,0x10,0xd5] +// CHECK: msr {{dbgwvr7_el1|DBGWVR7_EL1}}, x12 // encoding: [0xcc,0x07,0x10,0xd5] +// CHECK: msr {{dbgwvr8_el1|DBGWVR8_EL1}}, x12 // encoding: [0xcc,0x08,0x10,0xd5] +// CHECK: msr {{dbgwvr9_el1|DBGWVR9_EL1}}, x12 // encoding: [0xcc,0x09,0x10,0xd5] +// CHECK: msr {{dbgwvr10_el1|DBGWVR10_EL1}}, x12 // encoding: [0xcc,0x0a,0x10,0xd5] +// CHECK: msr {{dbgwvr11_el1|DBGWVR11_EL1}}, x12 // encoding: [0xcc,0x0b,0x10,0xd5] +// CHECK: msr {{dbgwvr12_el1|DBGWVR12_EL1}}, x12 // encoding: [0xcc,0x0c,0x10,0xd5] +// CHECK: msr {{dbgwvr13_el1|DBGWVR13_EL1}}, x12 // encoding: [0xcc,0x0d,0x10,0xd5] +// CHECK: msr {{dbgwvr14_el1|DBGWVR14_EL1}}, x12 // encoding: [0xcc,0x0e,0x10,0xd5] +// CHECK: msr {{dbgwvr15_el1|DBGWVR15_EL1}}, x12 // encoding: [0xcc,0x0f,0x10,0xd5] +// CHECK: msr {{dbgwcr0_el1|DBGWCR0_EL1}}, x12 // encoding: [0xec,0x00,0x10,0xd5] +// CHECK: msr {{dbgwcr1_el1|DBGWCR1_EL1}}, x12 // encoding: [0xec,0x01,0x10,0xd5] +// CHECK: msr {{dbgwcr2_el1|DBGWCR2_EL1}}, x12 // encoding: [0xec,0x02,0x10,0xd5] +// CHECK: msr {{dbgwcr3_el1|DBGWCR3_EL1}}, x12 // encoding: [0xec,0x03,0x10,0xd5] +// CHECK: msr {{dbgwcr4_el1|DBGWCR4_EL1}}, x12 // encoding: [0xec,0x04,0x10,0xd5] +// CHECK: msr {{dbgwcr5_el1|DBGWCR5_EL1}}, x12 // encoding: [0xec,0x05,0x10,0xd5] +// CHECK: msr {{dbgwcr6_el1|DBGWCR6_EL1}}, x12 // encoding: [0xec,0x06,0x10,0xd5] +// CHECK: msr {{dbgwcr7_el1|DBGWCR7_EL1}}, x12 // encoding: [0xec,0x07,0x10,0xd5] +// CHECK: msr {{dbgwcr8_el1|DBGWCR8_EL1}}, x12 // encoding: [0xec,0x08,0x10,0xd5] +// CHECK: msr {{dbgwcr9_el1|DBGWCR9_EL1}}, x12 // encoding: [0xec,0x09,0x10,0xd5] +// CHECK: msr {{dbgwcr10_el1|DBGWCR10_EL1}}, x12 // encoding: [0xec,0x0a,0x10,0xd5] +// CHECK: msr {{dbgwcr11_el1|DBGWCR11_EL1}}, x12 // encoding: [0xec,0x0b,0x10,0xd5] +// CHECK: msr {{dbgwcr12_el1|DBGWCR12_EL1}}, x12 // encoding: [0xec,0x0c,0x10,0xd5] +// CHECK: msr {{dbgwcr13_el1|DBGWCR13_EL1}}, x12 // encoding: [0xec,0x0d,0x10,0xd5] +// CHECK: msr {{dbgwcr14_el1|DBGWCR14_EL1}}, x12 // encoding: [0xec,0x0e,0x10,0xd5] +// CHECK: msr {{dbgwcr15_el1|DBGWCR15_EL1}}, x12 // encoding: [0xec,0x0f,0x10,0xd5] +// CHECK: msr {{teehbr32_el1|TEEHBR32_EL1}}, x12 // encoding: [0x0c,0x10,0x12,0xd5] +// CHECK: msr {{oslar_el1|OSLAR_EL1}}, x12 // encoding: [0x8c,0x10,0x10,0xd5] +// CHECK: msr {{osdlr_el1|OSDLR_EL1}}, x12 // encoding: [0x8c,0x13,0x10,0xd5] +// CHECK: msr {{dbgprcr_el1|DBGPRCR_EL1}}, x12 // encoding: [0x8c,0x14,0x10,0xd5] +// CHECK: msr {{dbgclaimset_el1|DBGCLAIMSET_EL1}}, x12 // encoding: [0xcc,0x78,0x10,0xd5] +// CHECK: msr {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}, x12 // encoding: [0xcc,0x79,0x10,0xd5] +// CHECK: msr {{csselr_el1|CSSELR_EL1}}, x12 // encoding: [0x0c,0x00,0x1a,0xd5] +// CHECK: msr {{vpidr_el2|VPIDR_EL2}}, x12 // encoding: [0x0c,0x00,0x1c,0xd5] +// CHECK: msr {{vmpidr_el2|VMPIDR_EL2}}, x12 // encoding: [0xac,0x00,0x1c,0xd5] +// CHECK: msr {{sctlr_el1|SCTLR_EL1}}, x12 // encoding: [0x0c,0x10,0x18,0xd5] +// CHECK: msr {{sctlr_el2|SCTLR_EL2}}, x12 // encoding: [0x0c,0x10,0x1c,0xd5] +// CHECK: msr {{sctlr_el3|SCTLR_EL3}}, x12 // encoding: [0x0c,0x10,0x1e,0xd5] +// CHECK: msr {{actlr_el1|ACTLR_EL1}}, x12 // encoding: [0x2c,0x10,0x18,0xd5] +// CHECK: msr {{actlr_el2|ACTLR_EL2}}, x12 // encoding: [0x2c,0x10,0x1c,0xd5] +// CHECK: msr {{actlr_el3|ACTLR_EL3}}, x12 // encoding: [0x2c,0x10,0x1e,0xd5] +// CHECK: msr {{cpacr_el1|CPACR_EL1}}, x12 // encoding: [0x4c,0x10,0x18,0xd5] +// CHECK: msr {{hcr_el2|HCR_EL2}}, x12 // encoding: [0x0c,0x11,0x1c,0xd5] +// CHECK: msr {{scr_el3|SCR_EL3}}, x12 // encoding: [0x0c,0x11,0x1e,0xd5] +// CHECK: msr {{mdcr_el2|MDCR_EL2}}, x12 // encoding: [0x2c,0x11,0x1c,0xd5] +// CHECK: msr {{sder32_el3|SDER32_EL3}}, x12 // encoding: [0x2c,0x11,0x1e,0xd5] +// CHECK: msr {{cptr_el2|CPTR_EL2}}, x12 // encoding: [0x4c,0x11,0x1c,0xd5] +// CHECK: msr {{cptr_el3|CPTR_EL3}}, x12 // encoding: [0x4c,0x11,0x1e,0xd5] +// CHECK: msr {{hstr_el2|HSTR_EL2}}, x12 // encoding: [0x6c,0x11,0x1c,0xd5] +// CHECK: msr {{hacr_el2|HACR_EL2}}, x12 // encoding: [0xec,0x11,0x1c,0xd5] +// CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12 // encoding: [0x2c,0x13,0x1e,0xd5] +// CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12 // encoding: [0x0c,0x20,0x18,0xd5] +// CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12 // encoding: [0x0c,0x20,0x1c,0xd5] +// CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12 // encoding: [0x0c,0x20,0x1e,0xd5] +// CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12 // encoding: [0x2c,0x20,0x18,0xd5] +// CHECK: msr {{tcr_el1|TCR_EL1}}, x12 // encoding: [0x4c,0x20,0x18,0xd5] +// CHECK: msr {{tcr_el2|TCR_EL2}}, x12 // encoding: [0x4c,0x20,0x1c,0xd5] +// CHECK: msr {{tcr_el3|TCR_EL3}}, x12 // encoding: [0x4c,0x20,0x1e,0xd5] +// CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12 // encoding: [0x0c,0x21,0x1c,0xd5] +// CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12 // encoding: [0x4c,0x21,0x1c,0xd5] +// CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12 // encoding: [0x0c,0x30,0x1c,0xd5] +// CHECK: msr {{spsr_el1|SPSR_EL1}}, x12 // encoding: [0x0c,0x40,0x18,0xd5] +// CHECK: msr {{spsr_el2|SPSR_EL2}}, x12 // encoding: [0x0c,0x40,0x1c,0xd5] +// CHECK: msr {{spsr_el3|SPSR_EL3}}, x12 // encoding: [0x0c,0x40,0x1e,0xd5] +// CHECK: msr {{elr_el1|ELR_EL1}}, x12 // encoding: [0x2c,0x40,0x18,0xd5] +// CHECK: msr {{elr_el2|ELR_EL2}}, x12 // encoding: [0x2c,0x40,0x1c,0xd5] +// CHECK: msr {{elr_el3|ELR_EL3}}, x12 // encoding: [0x2c,0x40,0x1e,0xd5] +// CHECK: msr {{sp_el0|SP_EL0}}, x12 // encoding: [0x0c,0x41,0x18,0xd5] +// CHECK: msr {{sp_el1|SP_EL1}}, x12 // encoding: [0x0c,0x41,0x1c,0xd5] +// CHECK: msr {{sp_el2|SP_EL2}}, x12 // encoding: [0x0c,0x41,0x1e,0xd5] +// CHECK: msr {{spsel|SPSEL}}, x12 // encoding: [0x0c,0x42,0x18,0xd5] +// CHECK: msr {{nzcv|NZCV}}, x12 // encoding: [0x0c,0x42,0x1b,0xd5] +// CHECK: msr {{daif|DAIF}}, x12 // encoding: [0x2c,0x42,0x1b,0xd5] +// CHECK: msr {{currentel|CURRENTEL}}, x12 // encoding: [0x4c,0x42,0x18,0xd5] +// CHECK: msr {{spsr_irq|SPSR_IRQ}}, x12 // encoding: [0x0c,0x43,0x1c,0xd5] +// CHECK: msr {{spsr_abt|SPSR_ABT}}, x12 // encoding: [0x2c,0x43,0x1c,0xd5] +// CHECK: msr {{spsr_und|SPSR_UND}}, x12 // encoding: [0x4c,0x43,0x1c,0xd5] +// CHECK: msr {{spsr_fiq|SPSR_FIQ}}, x12 // encoding: [0x6c,0x43,0x1c,0xd5] +// CHECK: msr {{fpcr|FPCR}}, x12 // encoding: [0x0c,0x44,0x1b,0xd5] +// CHECK: msr {{fpsr|FPSR}}, x12 // encoding: [0x2c,0x44,0x1b,0xd5] +// CHECK: msr {{dspsr_el0|DSPSR_EL0}}, x12 // encoding: [0x0c,0x45,0x1b,0xd5] +// CHECK: msr {{dlr_el0|DLR_EL0}}, x12 // encoding: [0x2c,0x45,0x1b,0xd5] +// CHECK: msr {{ifsr32_el2|IFSR32_EL2}}, x12 // encoding: [0x2c,0x50,0x1c,0xd5] +// CHECK: msr {{afsr0_el1|AFSR0_EL1}}, x12 // encoding: [0x0c,0x51,0x18,0xd5] +// CHECK: msr {{afsr0_el2|AFSR0_EL2}}, x12 // encoding: [0x0c,0x51,0x1c,0xd5] +// CHECK: msr {{afsr0_el3|AFSR0_EL3}}, x12 // encoding: [0x0c,0x51,0x1e,0xd5] +// CHECK: msr {{afsr1_el1|AFSR1_EL1}}, x12 // encoding: [0x2c,0x51,0x18,0xd5] +// CHECK: msr {{afsr1_el2|AFSR1_EL2}}, x12 // encoding: [0x2c,0x51,0x1c,0xd5] +// CHECK: msr {{afsr1_el3|AFSR1_EL3}}, x12 // encoding: [0x2c,0x51,0x1e,0xd5] +// CHECK: msr {{esr_el1|ESR_EL1}}, x12 // encoding: [0x0c,0x52,0x18,0xd5] +// CHECK: msr {{esr_el2|ESR_EL2}}, x12 // encoding: [0x0c,0x52,0x1c,0xd5] +// CHECK: msr {{esr_el3|ESR_EL3}}, x12 // encoding: [0x0c,0x52,0x1e,0xd5] +// CHECK: msr {{fpexc32_el2|FPEXC32_EL2}}, x12 // encoding: [0x0c,0x53,0x1c,0xd5] +// CHECK: msr {{far_el1|FAR_EL1}}, x12 // encoding: [0x0c,0x60,0x18,0xd5] +// CHECK: msr {{far_el2|FAR_EL2}}, x12 // encoding: [0x0c,0x60,0x1c,0xd5] +// CHECK: msr {{far_el3|FAR_EL3}}, x12 // encoding: [0x0c,0x60,0x1e,0xd5] +// CHECK: msr {{hpfar_el2|HPFAR_EL2}}, x12 // encoding: [0x8c,0x60,0x1c,0xd5] +// CHECK: msr {{par_el1|PAR_EL1}}, x12 // encoding: [0x0c,0x74,0x18,0xd5] +// CHECK: msr {{pmcr_el0|PMCR_EL0}}, x12 // encoding: [0x0c,0x9c,0x1b,0xd5] +// CHECK: msr {{pmcntenset_el0|PMCNTENSET_EL0}}, x12 // encoding: [0x2c,0x9c,0x1b,0xd5] +// CHECK: msr {{pmcntenclr_el0|PMCNTENCLR_EL0}}, x12 // encoding: [0x4c,0x9c,0x1b,0xd5] +// CHECK: msr {{pmovsclr_el0|PMOVSCLR_EL0}}, x12 // encoding: [0x6c,0x9c,0x1b,0xd5] +// CHECK: msr {{pmselr_el0|PMSELR_EL0}}, x12 // encoding: [0xac,0x9c,0x1b,0xd5] +// CHECK: msr {{pmccntr_el0|PMCCNTR_EL0}}, x12 // encoding: [0x0c,0x9d,0x1b,0xd5] +// CHECK: msr {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12 // encoding: [0x2c,0x9d,0x1b,0xd5] +// CHECK: msr {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12 // encoding: [0x4c,0x9d,0x1b,0xd5] +// CHECK: msr {{pmuserenr_el0|PMUSERENR_EL0}}, x12 // encoding: [0x0c,0x9e,0x1b,0xd5] +// CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12 // encoding: [0x2c,0x9e,0x18,0xd5] +// CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12 // encoding: [0x4c,0x9e,0x18,0xd5] +// CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12 // encoding: [0x6c,0x9e,0x1b,0xd5] +// CHECK: msr {{mair_el1|MAIR_EL1}}, x12 // encoding: [0x0c,0xa2,0x18,0xd5] +// CHECK: msr {{mair_el2|MAIR_EL2}}, x12 // encoding: [0x0c,0xa2,0x1c,0xd5] +// CHECK: msr {{mair_el3|MAIR_EL3}}, x12 // encoding: [0x0c,0xa2,0x1e,0xd5] +// CHECK: msr {{amair_el1|AMAIR_EL1}}, x12 // encoding: [0x0c,0xa3,0x18,0xd5] +// CHECK: msr {{amair_el2|AMAIR_EL2}}, x12 // encoding: [0x0c,0xa3,0x1c,0xd5] +// CHECK: msr {{amair_el3|AMAIR_EL3}}, x12 // encoding: [0x0c,0xa3,0x1e,0xd5] +// CHECK: msr {{vbar_el1|VBAR_EL1}}, x12 // encoding: [0x0c,0xc0,0x18,0xd5] +// CHECK: msr {{vbar_el2|VBAR_EL2}}, x12 // encoding: [0x0c,0xc0,0x1c,0xd5] +// CHECK: msr {{vbar_el3|VBAR_EL3}}, x12 // encoding: [0x0c,0xc0,0x1e,0xd5] +// CHECK: msr {{rmr_el1|RMR_EL1}}, x12 // encoding: [0x4c,0xc0,0x18,0xd5] +// CHECK: msr {{rmr_el2|RMR_EL2}}, x12 // encoding: [0x4c,0xc0,0x1c,0xd5] +// CHECK: msr {{rmr_el3|RMR_EL3}}, x12 // encoding: [0x4c,0xc0,0x1e,0xd5] +// CHECK: msr {{contextidr_el1|CONTEXTIDR_EL1}}, x12 // encoding: [0x2c,0xd0,0x18,0xd5] +// CHECK: msr {{tpidr_el0|TPIDR_EL0}}, x12 // encoding: [0x4c,0xd0,0x1b,0xd5] +// CHECK: msr {{tpidr_el2|TPIDR_EL2}}, x12 // encoding: [0x4c,0xd0,0x1c,0xd5] +// CHECK: msr {{tpidr_el3|TPIDR_EL3}}, x12 // encoding: [0x4c,0xd0,0x1e,0xd5] +// CHECK: msr {{tpidrro_el0|TPIDRRO_EL0}}, x12 // encoding: [0x6c,0xd0,0x1b,0xd5] +// CHECK: msr {{tpidr_el1|TPIDR_EL1}}, x12 // encoding: [0x8c,0xd0,0x18,0xd5] +// CHECK: msr {{cntfrq_el0|CNTFRQ_EL0}}, x12 // encoding: [0x0c,0xe0,0x1b,0xd5] +// CHECK: msr {{cntvoff_el2|CNTVOFF_EL2}}, x12 // encoding: [0x6c,0xe0,0x1c,0xd5] +// CHECK: msr {{cntkctl_el1|CNTKCTL_EL1}}, x12 // encoding: [0x0c,0xe1,0x18,0xd5] +// CHECK: msr {{cnthctl_el2|CNTHCTL_EL2}}, x12 // encoding: [0x0c,0xe1,0x1c,0xd5] +// CHECK: msr {{cntp_tval_el0|CNTP_TVAL_EL0}}, x12 // encoding: [0x0c,0xe2,0x1b,0xd5] +// CHECK: msr {{cnthp_tval_el2|CNTHP_TVAL_EL2}}, x12 // encoding: [0x0c,0xe2,0x1c,0xd5] +// CHECK: msr {{cntps_tval_el1|CNTPS_TVAL_EL1}}, x12 // encoding: [0x0c,0xe2,0x1f,0xd5] +// CHECK: msr {{cntp_ctl_el0|CNTP_CTL_EL0}}, x12 // encoding: [0x2c,0xe2,0x1b,0xd5] +// CHECK: msr {{cnthp_ctl_el2|CNTHP_CTL_EL2}}, x12 // encoding: [0x2c,0xe2,0x1c,0xd5] +// CHECK: msr {{cntps_ctl_el1|CNTPS_CTL_EL1}}, x12 // encoding: [0x2c,0xe2,0x1f,0xd5] +// CHECK: msr {{cntp_cval_el0|CNTP_CVAL_EL0}}, x12 // encoding: [0x4c,0xe2,0x1b,0xd5] +// CHECK: msr {{cnthp_cval_el2|CNTHP_CVAL_EL2}}, x12 // encoding: [0x4c,0xe2,0x1c,0xd5] +// CHECK: msr {{cntps_cval_el1|CNTPS_CVAL_EL1}}, x12 // encoding: [0x4c,0xe2,0x1f,0xd5] +// CHECK: msr {{cntv_tval_el0|CNTV_TVAL_EL0}}, x12 // encoding: [0x0c,0xe3,0x1b,0xd5] +// CHECK: msr {{cntv_ctl_el0|CNTV_CTL_EL0}}, x12 // encoding: [0x2c,0xe3,0x1b,0xd5] +// CHECK: msr {{cntv_cval_el0|CNTV_CVAL_EL0}}, x12 // encoding: [0x4c,0xe3,0x1b,0xd5] +// CHECK: msr {{pmevcntr0_el0|PMEVCNTR0_EL0}}, x12 // encoding: [0x0c,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr1_el0|PMEVCNTR1_EL0}}, x12 // encoding: [0x2c,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr2_el0|PMEVCNTR2_EL0}}, x12 // encoding: [0x4c,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr3_el0|PMEVCNTR3_EL0}}, x12 // encoding: [0x6c,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr4_el0|PMEVCNTR4_EL0}}, x12 // encoding: [0x8c,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr5_el0|PMEVCNTR5_EL0}}, x12 // encoding: [0xac,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr6_el0|PMEVCNTR6_EL0}}, x12 // encoding: [0xcc,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr7_el0|PMEVCNTR7_EL0}}, x12 // encoding: [0xec,0xe8,0x1b,0xd5] +// CHECK: msr {{pmevcntr8_el0|PMEVCNTR8_EL0}}, x12 // encoding: [0x0c,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr9_el0|PMEVCNTR9_EL0}}, x12 // encoding: [0x2c,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr10_el0|PMEVCNTR10_EL0}}, x12 // encoding: [0x4c,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr11_el0|PMEVCNTR11_EL0}}, x12 // encoding: [0x6c,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr12_el0|PMEVCNTR12_EL0}}, x12 // encoding: [0x8c,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr13_el0|PMEVCNTR13_EL0}}, x12 // encoding: [0xac,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr14_el0|PMEVCNTR14_EL0}}, x12 // encoding: [0xcc,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr15_el0|PMEVCNTR15_EL0}}, x12 // encoding: [0xec,0xe9,0x1b,0xd5] +// CHECK: msr {{pmevcntr16_el0|PMEVCNTR16_EL0}}, x12 // encoding: [0x0c,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr17_el0|PMEVCNTR17_EL0}}, x12 // encoding: [0x2c,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr18_el0|PMEVCNTR18_EL0}}, x12 // encoding: [0x4c,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr19_el0|PMEVCNTR19_EL0}}, x12 // encoding: [0x6c,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr20_el0|PMEVCNTR20_EL0}}, x12 // encoding: [0x8c,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr21_el0|PMEVCNTR21_EL0}}, x12 // encoding: [0xac,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr22_el0|PMEVCNTR22_EL0}}, x12 // encoding: [0xcc,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr23_el0|PMEVCNTR23_EL0}}, x12 // encoding: [0xec,0xea,0x1b,0xd5] +// CHECK: msr {{pmevcntr24_el0|PMEVCNTR24_EL0}}, x12 // encoding: [0x0c,0xeb,0x1b,0xd5] +// CHECK: msr {{pmevcntr25_el0|PMEVCNTR25_EL0}}, x12 // encoding: [0x2c,0xeb,0x1b,0xd5] +// CHECK: msr {{pmevcntr26_el0|PMEVCNTR26_EL0}}, x12 // encoding: [0x4c,0xeb,0x1b,0xd5] +// CHECK: msr {{pmevcntr27_el0|PMEVCNTR27_EL0}}, x12 // encoding: [0x6c,0xeb,0x1b,0xd5] +// CHECK: msr {{pmevcntr28_el0|PMEVCNTR28_EL0}}, x12 // encoding: [0x8c,0xeb,0x1b,0xd5] +// CHECK: msr {{pmevcntr29_el0|PMEVCNTR29_EL0}}, x12 // encoding: [0xac,0xeb,0x1b,0xd5] +// CHECK: msr {{pmevcntr30_el0|PMEVCNTR30_EL0}}, x12 // encoding: [0xcc,0xeb,0x1b,0xd5] +// CHECK: msr {{pmccfiltr_el0|PMCCFILTR_EL0}}, x12 // encoding: [0xec,0xef,0x1b,0xd5] +// CHECK: msr {{pmevtyper0_el0|PMEVTYPER0_EL0}}, x12 // encoding: [0x0c,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper1_el0|PMEVTYPER1_EL0}}, x12 // encoding: [0x2c,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper2_el0|PMEVTYPER2_EL0}}, x12 // encoding: [0x4c,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper3_el0|PMEVTYPER3_EL0}}, x12 // encoding: [0x6c,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper4_el0|PMEVTYPER4_EL0}}, x12 // encoding: [0x8c,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper5_el0|PMEVTYPER5_EL0}}, x12 // encoding: [0xac,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper6_el0|PMEVTYPER6_EL0}}, x12 // encoding: [0xcc,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper7_el0|PMEVTYPER7_EL0}}, x12 // encoding: [0xec,0xec,0x1b,0xd5] +// CHECK: msr {{pmevtyper8_el0|PMEVTYPER8_EL0}}, x12 // encoding: [0x0c,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper9_el0|PMEVTYPER9_EL0}}, x12 // encoding: [0x2c,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper10_el0|PMEVTYPER10_EL0}}, x12 // encoding: [0x4c,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper11_el0|PMEVTYPER11_EL0}}, x12 // encoding: [0x6c,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper12_el0|PMEVTYPER12_EL0}}, x12 // encoding: [0x8c,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper13_el0|PMEVTYPER13_EL0}}, x12 // encoding: [0xac,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper14_el0|PMEVTYPER14_EL0}}, x12 // encoding: [0xcc,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper15_el0|PMEVTYPER15_EL0}}, x12 // encoding: [0xec,0xed,0x1b,0xd5] +// CHECK: msr {{pmevtyper16_el0|PMEVTYPER16_EL0}}, x12 // encoding: [0x0c,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper17_el0|PMEVTYPER17_EL0}}, x12 // encoding: [0x2c,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper18_el0|PMEVTYPER18_EL0}}, x12 // encoding: [0x4c,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper19_el0|PMEVTYPER19_EL0}}, x12 // encoding: [0x6c,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper20_el0|PMEVTYPER20_EL0}}, x12 // encoding: [0x8c,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper21_el0|PMEVTYPER21_EL0}}, x12 // encoding: [0xac,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper22_el0|PMEVTYPER22_EL0}}, x12 // encoding: [0xcc,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper23_el0|PMEVTYPER23_EL0}}, x12 // encoding: [0xec,0xee,0x1b,0xd5] +// CHECK: msr {{pmevtyper24_el0|PMEVTYPER24_EL0}}, x12 // encoding: [0x0c,0xef,0x1b,0xd5] +// CHECK: msr {{pmevtyper25_el0|PMEVTYPER25_EL0}}, x12 // encoding: [0x2c,0xef,0x1b,0xd5] +// CHECK: msr {{pmevtyper26_el0|PMEVTYPER26_EL0}}, x12 // encoding: [0x4c,0xef,0x1b,0xd5] +// CHECK: msr {{pmevtyper27_el0|PMEVTYPER27_EL0}}, x12 // encoding: [0x6c,0xef,0x1b,0xd5] +// CHECK: msr {{pmevtyper28_el0|PMEVTYPER28_EL0}}, x12 // encoding: [0x8c,0xef,0x1b,0xd5] +// CHECK: msr {{pmevtyper29_el0|PMEVTYPER29_EL0}}, x12 // encoding: [0xac,0xef,0x1b,0xd5] +// CHECK: msr {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12 // encoding: [0xcc,0xef,0x1b,0xd5] mrs x9, TEECR32_EL1 mrs x9, OSDTRRX_EL1 @@ -4497,315 +4464,315 @@ _func: mrs x9, PMEVTYPER28_EL0 mrs x9, PMEVTYPER29_EL0 mrs x9, PMEVTYPER30_EL0 -// CHECK: mrs x9, teecr32_el1 // encoding: [0x09,0x00,0x32,0xd5] -// CHECK: mrs x9, osdtrrx_el1 // encoding: [0x49,0x00,0x30,0xd5] -// CHECK: mrs x9, mdccsr_el0 // encoding: [0x09,0x01,0x33,0xd5] -// CHECK: mrs x9, mdccint_el1 // encoding: [0x09,0x02,0x30,0xd5] -// CHECK: mrs x9, mdscr_el1 // encoding: [0x49,0x02,0x30,0xd5] -// CHECK: mrs x9, osdtrtx_el1 // encoding: [0x49,0x03,0x30,0xd5] -// CHECK: mrs x9, dbgdtr_el0 // encoding: [0x09,0x04,0x33,0xd5] -// CHECK: mrs x9, dbgdtrrx_el0 // encoding: [0x09,0x05,0x33,0xd5] -// CHECK: mrs x9, oseccr_el1 // encoding: [0x49,0x06,0x30,0xd5] -// CHECK: mrs x9, dbgvcr32_el2 // encoding: [0x09,0x07,0x34,0xd5] -// CHECK: mrs x9, dbgbvr0_el1 // encoding: [0x89,0x00,0x30,0xd5] -// CHECK: mrs x9, dbgbvr1_el1 // encoding: [0x89,0x01,0x30,0xd5] -// CHECK: mrs x9, dbgbvr2_el1 // encoding: [0x89,0x02,0x30,0xd5] -// CHECK: mrs x9, dbgbvr3_el1 // encoding: [0x89,0x03,0x30,0xd5] -// CHECK: mrs x9, dbgbvr4_el1 // encoding: [0x89,0x04,0x30,0xd5] -// CHECK: mrs x9, dbgbvr5_el1 // encoding: [0x89,0x05,0x30,0xd5] -// CHECK: mrs x9, dbgbvr6_el1 // encoding: [0x89,0x06,0x30,0xd5] -// CHECK: mrs x9, dbgbvr7_el1 // encoding: [0x89,0x07,0x30,0xd5] -// CHECK: mrs x9, dbgbvr8_el1 // encoding: [0x89,0x08,0x30,0xd5] -// CHECK: mrs x9, dbgbvr9_el1 // encoding: [0x89,0x09,0x30,0xd5] -// CHECK: mrs x9, dbgbvr10_el1 // encoding: [0x89,0x0a,0x30,0xd5] -// CHECK: mrs x9, dbgbvr11_el1 // encoding: [0x89,0x0b,0x30,0xd5] -// CHECK: mrs x9, dbgbvr12_el1 // encoding: [0x89,0x0c,0x30,0xd5] -// CHECK: mrs x9, dbgbvr13_el1 // encoding: [0x89,0x0d,0x30,0xd5] -// CHECK: mrs x9, dbgbvr14_el1 // encoding: [0x89,0x0e,0x30,0xd5] -// CHECK: mrs x9, dbgbvr15_el1 // encoding: [0x89,0x0f,0x30,0xd5] -// CHECK: mrs x9, dbgbcr0_el1 // encoding: [0xa9,0x00,0x30,0xd5] -// CHECK: mrs x9, dbgbcr1_el1 // encoding: [0xa9,0x01,0x30,0xd5] -// CHECK: mrs x9, dbgbcr2_el1 // encoding: [0xa9,0x02,0x30,0xd5] -// CHECK: mrs x9, dbgbcr3_el1 // encoding: [0xa9,0x03,0x30,0xd5] -// CHECK: mrs x9, dbgbcr4_el1 // encoding: [0xa9,0x04,0x30,0xd5] -// CHECK: mrs x9, dbgbcr5_el1 // encoding: [0xa9,0x05,0x30,0xd5] -// CHECK: mrs x9, dbgbcr6_el1 // encoding: [0xa9,0x06,0x30,0xd5] -// CHECK: mrs x9, dbgbcr7_el1 // encoding: [0xa9,0x07,0x30,0xd5] -// CHECK: mrs x9, dbgbcr8_el1 // encoding: [0xa9,0x08,0x30,0xd5] -// CHECK: mrs x9, dbgbcr9_el1 // encoding: [0xa9,0x09,0x30,0xd5] -// CHECK: mrs x9, dbgbcr10_el1 // encoding: [0xa9,0x0a,0x30,0xd5] -// CHECK: mrs x9, dbgbcr11_el1 // encoding: [0xa9,0x0b,0x30,0xd5] -// CHECK: mrs x9, dbgbcr12_el1 // encoding: [0xa9,0x0c,0x30,0xd5] -// CHECK: mrs x9, dbgbcr13_el1 // encoding: [0xa9,0x0d,0x30,0xd5] -// CHECK: mrs x9, dbgbcr14_el1 // encoding: [0xa9,0x0e,0x30,0xd5] -// CHECK: mrs x9, dbgbcr15_el1 // encoding: [0xa9,0x0f,0x30,0xd5] -// CHECK: mrs x9, dbgwvr0_el1 // encoding: [0xc9,0x00,0x30,0xd5] -// CHECK: mrs x9, dbgwvr1_el1 // encoding: [0xc9,0x01,0x30,0xd5] -// CHECK: mrs x9, dbgwvr2_el1 // encoding: [0xc9,0x02,0x30,0xd5] -// CHECK: mrs x9, dbgwvr3_el1 // encoding: [0xc9,0x03,0x30,0xd5] -// CHECK: mrs x9, dbgwvr4_el1 // encoding: [0xc9,0x04,0x30,0xd5] -// CHECK: mrs x9, dbgwvr5_el1 // encoding: [0xc9,0x05,0x30,0xd5] -// CHECK: mrs x9, dbgwvr6_el1 // encoding: [0xc9,0x06,0x30,0xd5] -// CHECK: mrs x9, dbgwvr7_el1 // encoding: [0xc9,0x07,0x30,0xd5] -// CHECK: mrs x9, dbgwvr8_el1 // encoding: [0xc9,0x08,0x30,0xd5] -// CHECK: mrs x9, dbgwvr9_el1 // encoding: [0xc9,0x09,0x30,0xd5] -// CHECK: mrs x9, dbgwvr10_el1 // encoding: [0xc9,0x0a,0x30,0xd5] -// CHECK: mrs x9, dbgwvr11_el1 // encoding: [0xc9,0x0b,0x30,0xd5] -// CHECK: mrs x9, dbgwvr12_el1 // encoding: [0xc9,0x0c,0x30,0xd5] -// CHECK: mrs x9, dbgwvr13_el1 // encoding: [0xc9,0x0d,0x30,0xd5] -// CHECK: mrs x9, dbgwvr14_el1 // encoding: [0xc9,0x0e,0x30,0xd5] -// CHECK: mrs x9, dbgwvr15_el1 // encoding: [0xc9,0x0f,0x30,0xd5] -// CHECK: mrs x9, dbgwcr0_el1 // encoding: [0xe9,0x00,0x30,0xd5] -// CHECK: mrs x9, dbgwcr1_el1 // encoding: [0xe9,0x01,0x30,0xd5] -// CHECK: mrs x9, dbgwcr2_el1 // encoding: [0xe9,0x02,0x30,0xd5] -// CHECK: mrs x9, dbgwcr3_el1 // encoding: [0xe9,0x03,0x30,0xd5] -// CHECK: mrs x9, dbgwcr4_el1 // encoding: [0xe9,0x04,0x30,0xd5] -// CHECK: mrs x9, dbgwcr5_el1 // encoding: [0xe9,0x05,0x30,0xd5] -// CHECK: mrs x9, dbgwcr6_el1 // encoding: [0xe9,0x06,0x30,0xd5] -// CHECK: mrs x9, dbgwcr7_el1 // encoding: [0xe9,0x07,0x30,0xd5] -// CHECK: mrs x9, dbgwcr8_el1 // encoding: [0xe9,0x08,0x30,0xd5] -// CHECK: mrs x9, dbgwcr9_el1 // encoding: [0xe9,0x09,0x30,0xd5] -// CHECK: mrs x9, dbgwcr10_el1 // encoding: [0xe9,0x0a,0x30,0xd5] -// CHECK: mrs x9, dbgwcr11_el1 // encoding: [0xe9,0x0b,0x30,0xd5] -// CHECK: mrs x9, dbgwcr12_el1 // encoding: [0xe9,0x0c,0x30,0xd5] -// CHECK: mrs x9, dbgwcr13_el1 // encoding: [0xe9,0x0d,0x30,0xd5] -// CHECK: mrs x9, dbgwcr14_el1 // encoding: [0xe9,0x0e,0x30,0xd5] -// CHECK: mrs x9, dbgwcr15_el1 // encoding: [0xe9,0x0f,0x30,0xd5] -// CHECK: mrs x9, mdrar_el1 // encoding: [0x09,0x10,0x30,0xd5] -// CHECK: mrs x9, teehbr32_el1 // encoding: [0x09,0x10,0x32,0xd5] -// CHECK: mrs x9, oslsr_el1 // encoding: [0x89,0x11,0x30,0xd5] -// CHECK: mrs x9, osdlr_el1 // encoding: [0x89,0x13,0x30,0xd5] -// CHECK: mrs x9, dbgprcr_el1 // encoding: [0x89,0x14,0x30,0xd5] -// CHECK: mrs x9, dbgclaimset_el1 // encoding: [0xc9,0x78,0x30,0xd5] -// CHECK: mrs x9, dbgclaimclr_el1 // encoding: [0xc9,0x79,0x30,0xd5] -// CHECK: mrs x9, dbgauthstatus_el1 // encoding: [0xc9,0x7e,0x30,0xd5] -// CHECK: mrs x9, midr_el1 // encoding: [0x09,0x00,0x38,0xd5] -// CHECK: mrs x9, ccsidr_el1 // encoding: [0x09,0x00,0x39,0xd5] -// CHECK: mrs x9, csselr_el1 // encoding: [0x09,0x00,0x3a,0xd5] -// CHECK: mrs x9, vpidr_el2 // encoding: [0x09,0x00,0x3c,0xd5] -// CHECK: mrs x9, clidr_el1 // encoding: [0x29,0x00,0x39,0xd5] -// CHECK: mrs x9, ctr_el0 // encoding: [0x29,0x00,0x3b,0xd5] -// CHECK: mrs x9, mpidr_el1 // encoding: [0xa9,0x00,0x38,0xd5] -// CHECK: mrs x9, vmpidr_el2 // encoding: [0xa9,0x00,0x3c,0xd5] -// CHECK: mrs x9, revidr_el1 // encoding: [0xc9,0x00,0x38,0xd5] -// CHECK: mrs x9, aidr_el1 // encoding: [0xe9,0x00,0x39,0xd5] -// CHECK: mrs x9, dczid_el0 // encoding: [0xe9,0x00,0x3b,0xd5] -// CHECK: mrs x9, id_pfr0_el1 // encoding: [0x09,0x01,0x38,0xd5] -// CHECK: mrs x9, id_pfr1_el1 // encoding: [0x29,0x01,0x38,0xd5] -// CHECK: mrs x9, id_dfr0_el1 // encoding: [0x49,0x01,0x38,0xd5] -// CHECK: mrs x9, id_afr0_el1 // encoding: [0x69,0x01,0x38,0xd5] -// CHECK: mrs x9, id_mmfr0_el1 // encoding: [0x89,0x01,0x38,0xd5] -// CHECK: mrs x9, id_mmfr1_el1 // encoding: [0xa9,0x01,0x38,0xd5] -// CHECK: mrs x9, id_mmfr2_el1 // encoding: [0xc9,0x01,0x38,0xd5] -// CHECK: mrs x9, id_mmfr3_el1 // encoding: [0xe9,0x01,0x38,0xd5] -// CHECK: mrs x9, id_isar0_el1 // encoding: [0x09,0x02,0x38,0xd5] -// CHECK: mrs x9, id_isar1_el1 // encoding: [0x29,0x02,0x38,0xd5] -// CHECK: mrs x9, id_isar2_el1 // encoding: [0x49,0x02,0x38,0xd5] -// CHECK: mrs x9, id_isar3_el1 // encoding: [0x69,0x02,0x38,0xd5] -// CHECK: mrs x9, id_isar4_el1 // encoding: [0x89,0x02,0x38,0xd5] -// CHECK: mrs x9, id_isar5_el1 // encoding: [0xa9,0x02,0x38,0xd5] -// CHECK: mrs x9, mvfr0_el1 // encoding: [0x09,0x03,0x38,0xd5] -// CHECK: mrs x9, mvfr1_el1 // encoding: [0x29,0x03,0x38,0xd5] -// CHECK: mrs x9, mvfr2_el1 // encoding: [0x49,0x03,0x38,0xd5] -// CHECK: mrs x9, id_aa64pfr0_el1 // encoding: [0x09,0x04,0x38,0xd5] -// CHECK: mrs x9, id_aa64pfr1_el1 // encoding: [0x29,0x04,0x38,0xd5] -// CHECK: mrs x9, id_aa64dfr0_el1 // encoding: [0x09,0x05,0x38,0xd5] -// CHECK: mrs x9, id_aa64dfr1_el1 // encoding: [0x29,0x05,0x38,0xd5] -// CHECK: mrs x9, id_aa64afr0_el1 // encoding: [0x89,0x05,0x38,0xd5] -// CHECK: mrs x9, id_aa64afr1_el1 // encoding: [0xa9,0x05,0x38,0xd5] -// CHECK: mrs x9, id_aa64isar0_el1 // encoding: [0x09,0x06,0x38,0xd5] -// CHECK: mrs x9, id_aa64isar1_el1 // encoding: [0x29,0x06,0x38,0xd5] -// CHECK: mrs x9, id_aa64mmfr0_el1 // encoding: [0x09,0x07,0x38,0xd5] -// CHECK: mrs x9, id_aa64mmfr1_el1 // encoding: [0x29,0x07,0x38,0xd5] -// CHECK: mrs x9, sctlr_el1 // encoding: [0x09,0x10,0x38,0xd5] -// CHECK: mrs x9, sctlr_el2 // encoding: [0x09,0x10,0x3c,0xd5] -// CHECK: mrs x9, sctlr_el3 // encoding: [0x09,0x10,0x3e,0xd5] -// CHECK: mrs x9, actlr_el1 // encoding: [0x29,0x10,0x38,0xd5] -// CHECK: mrs x9, actlr_el2 // encoding: [0x29,0x10,0x3c,0xd5] -// CHECK: mrs x9, actlr_el3 // encoding: [0x29,0x10,0x3e,0xd5] -// CHECK: mrs x9, cpacr_el1 // encoding: [0x49,0x10,0x38,0xd5] -// CHECK: mrs x9, hcr_el2 // encoding: [0x09,0x11,0x3c,0xd5] -// CHECK: mrs x9, scr_el3 // encoding: [0x09,0x11,0x3e,0xd5] -// CHECK: mrs x9, mdcr_el2 // encoding: [0x29,0x11,0x3c,0xd5] -// CHECK: mrs x9, sder32_el3 // encoding: [0x29,0x11,0x3e,0xd5] -// CHECK: mrs x9, cptr_el2 // encoding: [0x49,0x11,0x3c,0xd5] -// CHECK: mrs x9, cptr_el3 // encoding: [0x49,0x11,0x3e,0xd5] -// CHECK: mrs x9, hstr_el2 // encoding: [0x69,0x11,0x3c,0xd5] -// CHECK: mrs x9, hacr_el2 // encoding: [0xe9,0x11,0x3c,0xd5] -// CHECK: mrs x9, mdcr_el3 // encoding: [0x29,0x13,0x3e,0xd5] -// CHECK: mrs x9, ttbr0_el1 // encoding: [0x09,0x20,0x38,0xd5] -// CHECK: mrs x9, ttbr0_el2 // encoding: [0x09,0x20,0x3c,0xd5] -// CHECK: mrs x9, ttbr0_el3 // encoding: [0x09,0x20,0x3e,0xd5] -// CHECK: mrs x9, ttbr1_el1 // encoding: [0x29,0x20,0x38,0xd5] -// CHECK: mrs x9, tcr_el1 // encoding: [0x49,0x20,0x38,0xd5] -// CHECK: mrs x9, tcr_el2 // encoding: [0x49,0x20,0x3c,0xd5] -// CHECK: mrs x9, tcr_el3 // encoding: [0x49,0x20,0x3e,0xd5] -// CHECK: mrs x9, vttbr_el2 // encoding: [0x09,0x21,0x3c,0xd5] -// CHECK: mrs x9, vtcr_el2 // encoding: [0x49,0x21,0x3c,0xd5] -// CHECK: mrs x9, dacr32_el2 // encoding: [0x09,0x30,0x3c,0xd5] -// CHECK: mrs x9, spsr_el1 // encoding: [0x09,0x40,0x38,0xd5] -// CHECK: mrs x9, spsr_el2 // encoding: [0x09,0x40,0x3c,0xd5] -// CHECK: mrs x9, spsr_el3 // encoding: [0x09,0x40,0x3e,0xd5] -// CHECK: mrs x9, elr_el1 // encoding: [0x29,0x40,0x38,0xd5] -// CHECK: mrs x9, elr_el2 // encoding: [0x29,0x40,0x3c,0xd5] -// CHECK: mrs x9, elr_el3 // encoding: [0x29,0x40,0x3e,0xd5] -// CHECK: mrs x9, sp_el0 // encoding: [0x09,0x41,0x38,0xd5] -// CHECK: mrs x9, sp_el1 // encoding: [0x09,0x41,0x3c,0xd5] -// CHECK: mrs x9, sp_el2 // encoding: [0x09,0x41,0x3e,0xd5] -// CHECK: mrs x9, spsel // encoding: [0x09,0x42,0x38,0xd5] -// CHECK: mrs x9, nzcv // encoding: [0x09,0x42,0x3b,0xd5] -// CHECK: mrs x9, daif // encoding: [0x29,0x42,0x3b,0xd5] -// CHECK: mrs x9, currentel // encoding: [0x49,0x42,0x38,0xd5] -// CHECK: mrs x9, spsr_irq // encoding: [0x09,0x43,0x3c,0xd5] -// CHECK: mrs x9, spsr_abt // encoding: [0x29,0x43,0x3c,0xd5] -// CHECK: mrs x9, spsr_und // encoding: [0x49,0x43,0x3c,0xd5] -// CHECK: mrs x9, spsr_fiq // encoding: [0x69,0x43,0x3c,0xd5] -// CHECK: mrs x9, fpcr // encoding: [0x09,0x44,0x3b,0xd5] -// CHECK: mrs x9, fpsr // encoding: [0x29,0x44,0x3b,0xd5] -// CHECK: mrs x9, dspsr_el0 // encoding: [0x09,0x45,0x3b,0xd5] -// CHECK: mrs x9, dlr_el0 // encoding: [0x29,0x45,0x3b,0xd5] -// CHECK: mrs x9, ifsr32_el2 // encoding: [0x29,0x50,0x3c,0xd5] -// CHECK: mrs x9, afsr0_el1 // encoding: [0x09,0x51,0x38,0xd5] -// CHECK: mrs x9, afsr0_el2 // encoding: [0x09,0x51,0x3c,0xd5] -// CHECK: mrs x9, afsr0_el3 // encoding: [0x09,0x51,0x3e,0xd5] -// CHECK: mrs x9, afsr1_el1 // encoding: [0x29,0x51,0x38,0xd5] -// CHECK: mrs x9, afsr1_el2 // encoding: [0x29,0x51,0x3c,0xd5] -// CHECK: mrs x9, afsr1_el3 // encoding: [0x29,0x51,0x3e,0xd5] -// CHECK: mrs x9, esr_el1 // encoding: [0x09,0x52,0x38,0xd5] -// CHECK: mrs x9, esr_el2 // encoding: [0x09,0x52,0x3c,0xd5] -// CHECK: mrs x9, esr_el3 // encoding: [0x09,0x52,0x3e,0xd5] -// CHECK: mrs x9, fpexc32_el2 // encoding: [0x09,0x53,0x3c,0xd5] -// CHECK: mrs x9, far_el1 // encoding: [0x09,0x60,0x38,0xd5] -// CHECK: mrs x9, far_el2 // encoding: [0x09,0x60,0x3c,0xd5] -// CHECK: mrs x9, far_el3 // encoding: [0x09,0x60,0x3e,0xd5] -// CHECK: mrs x9, hpfar_el2 // encoding: [0x89,0x60,0x3c,0xd5] -// CHECK: mrs x9, par_el1 // encoding: [0x09,0x74,0x38,0xd5] -// CHECK: mrs x9, pmcr_el0 // encoding: [0x09,0x9c,0x3b,0xd5] -// CHECK: mrs x9, pmcntenset_el0 // encoding: [0x29,0x9c,0x3b,0xd5] -// CHECK: mrs x9, pmcntenclr_el0 // encoding: [0x49,0x9c,0x3b,0xd5] -// CHECK: mrs x9, pmovsclr_el0 // encoding: [0x69,0x9c,0x3b,0xd5] -// CHECK: mrs x9, pmselr_el0 // encoding: [0xa9,0x9c,0x3b,0xd5] -// CHECK: mrs x9, pmceid0_el0 // encoding: [0xc9,0x9c,0x3b,0xd5] -// CHECK: mrs x9, pmceid1_el0 // encoding: [0xe9,0x9c,0x3b,0xd5] -// CHECK: mrs x9, pmccntr_el0 // encoding: [0x09,0x9d,0x3b,0xd5] -// CHECK: mrs x9, pmxevtyper_el0 // encoding: [0x29,0x9d,0x3b,0xd5] -// CHECK: mrs x9, pmxevcntr_el0 // encoding: [0x49,0x9d,0x3b,0xd5] -// CHECK: mrs x9, pmuserenr_el0 // encoding: [0x09,0x9e,0x3b,0xd5] -// CHECK: mrs x9, pmintenset_el1 // encoding: [0x29,0x9e,0x38,0xd5] -// CHECK: mrs x9, pmintenclr_el1 // encoding: [0x49,0x9e,0x38,0xd5] -// CHECK: mrs x9, pmovsset_el0 // encoding: [0x69,0x9e,0x3b,0xd5] -// CHECK: mrs x9, mair_el1 // encoding: [0x09,0xa2,0x38,0xd5] -// CHECK: mrs x9, mair_el2 // encoding: [0x09,0xa2,0x3c,0xd5] -// CHECK: mrs x9, mair_el3 // encoding: [0x09,0xa2,0x3e,0xd5] -// CHECK: mrs x9, amair_el1 // encoding: [0x09,0xa3,0x38,0xd5] -// CHECK: mrs x9, amair_el2 // encoding: [0x09,0xa3,0x3c,0xd5] -// CHECK: mrs x9, amair_el3 // encoding: [0x09,0xa3,0x3e,0xd5] -// CHECK: mrs x9, vbar_el1 // encoding: [0x09,0xc0,0x38,0xd5] -// CHECK: mrs x9, vbar_el2 // encoding: [0x09,0xc0,0x3c,0xd5] -// CHECK: mrs x9, vbar_el3 // encoding: [0x09,0xc0,0x3e,0xd5] -// CHECK: mrs x9, rvbar_el1 // encoding: [0x29,0xc0,0x38,0xd5] -// CHECK: mrs x9, rvbar_el2 // encoding: [0x29,0xc0,0x3c,0xd5] -// CHECK: mrs x9, rvbar_el3 // encoding: [0x29,0xc0,0x3e,0xd5] -// CHECK: mrs x9, rmr_el1 // encoding: [0x49,0xc0,0x38,0xd5] -// CHECK: mrs x9, rmr_el2 // encoding: [0x49,0xc0,0x3c,0xd5] -// CHECK: mrs x9, rmr_el3 // encoding: [0x49,0xc0,0x3e,0xd5] -// CHECK: mrs x9, isr_el1 // encoding: [0x09,0xc1,0x38,0xd5] -// CHECK: mrs x9, contextidr_el1 // encoding: [0x29,0xd0,0x38,0xd5] -// CHECK: mrs x9, tpidr_el0 // encoding: [0x49,0xd0,0x3b,0xd5] -// CHECK: mrs x9, tpidr_el2 // encoding: [0x49,0xd0,0x3c,0xd5] -// CHECK: mrs x9, tpidr_el3 // encoding: [0x49,0xd0,0x3e,0xd5] -// CHECK: mrs x9, tpidrro_el0 // encoding: [0x69,0xd0,0x3b,0xd5] -// CHECK: mrs x9, tpidr_el1 // encoding: [0x89,0xd0,0x38,0xd5] -// CHECK: mrs x9, cntfrq_el0 // encoding: [0x09,0xe0,0x3b,0xd5] -// CHECK: mrs x9, cntpct_el0 // encoding: [0x29,0xe0,0x3b,0xd5] -// CHECK: mrs x9, cntvct_el0 // encoding: [0x49,0xe0,0x3b,0xd5] -// CHECK: mrs x9, cntvoff_el2 // encoding: [0x69,0xe0,0x3c,0xd5] -// CHECK: mrs x9, cntkctl_el1 // encoding: [0x09,0xe1,0x38,0xd5] -// CHECK: mrs x9, cnthctl_el2 // encoding: [0x09,0xe1,0x3c,0xd5] -// CHECK: mrs x9, cntp_tval_el0 // encoding: [0x09,0xe2,0x3b,0xd5] -// CHECK: mrs x9, cnthp_tval_el2 // encoding: [0x09,0xe2,0x3c,0xd5] -// CHECK: mrs x9, cntps_tval_el1 // encoding: [0x09,0xe2,0x3f,0xd5] -// CHECK: mrs x9, cntp_ctl_el0 // encoding: [0x29,0xe2,0x3b,0xd5] -// CHECK: mrs x9, cnthp_ctl_el2 // encoding: [0x29,0xe2,0x3c,0xd5] -// CHECK: mrs x9, cntps_ctl_el1 // encoding: [0x29,0xe2,0x3f,0xd5] -// CHECK: mrs x9, cntp_cval_el0 // encoding: [0x49,0xe2,0x3b,0xd5] -// CHECK: mrs x9, cnthp_cval_el2 // encoding: [0x49,0xe2,0x3c,0xd5] -// CHECK: mrs x9, cntps_cval_el1 // encoding: [0x49,0xe2,0x3f,0xd5] -// CHECK: mrs x9, cntv_tval_el0 // encoding: [0x09,0xe3,0x3b,0xd5] -// CHECK: mrs x9, cntv_ctl_el0 // encoding: [0x29,0xe3,0x3b,0xd5] -// CHECK: mrs x9, cntv_cval_el0 // encoding: [0x49,0xe3,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr0_el0 // encoding: [0x09,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr1_el0 // encoding: [0x29,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr2_el0 // encoding: [0x49,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr3_el0 // encoding: [0x69,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr4_el0 // encoding: [0x89,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr5_el0 // encoding: [0xa9,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr6_el0 // encoding: [0xc9,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr7_el0 // encoding: [0xe9,0xe8,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr8_el0 // encoding: [0x09,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr9_el0 // encoding: [0x29,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr10_el0 // encoding: [0x49,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr11_el0 // encoding: [0x69,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr12_el0 // encoding: [0x89,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr13_el0 // encoding: [0xa9,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr14_el0 // encoding: [0xc9,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr15_el0 // encoding: [0xe9,0xe9,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr16_el0 // encoding: [0x09,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr17_el0 // encoding: [0x29,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr18_el0 // encoding: [0x49,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr19_el0 // encoding: [0x69,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr20_el0 // encoding: [0x89,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr21_el0 // encoding: [0xa9,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr22_el0 // encoding: [0xc9,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr23_el0 // encoding: [0xe9,0xea,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr24_el0 // encoding: [0x09,0xeb,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr25_el0 // encoding: [0x29,0xeb,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr26_el0 // encoding: [0x49,0xeb,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr27_el0 // encoding: [0x69,0xeb,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr28_el0 // encoding: [0x89,0xeb,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr29_el0 // encoding: [0xa9,0xeb,0x3b,0xd5] -// CHECK: mrs x9, pmevcntr30_el0 // encoding: [0xc9,0xeb,0x3b,0xd5] -// CHECK: mrs x9, pmccfiltr_el0 // encoding: [0xe9,0xef,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper0_el0 // encoding: [0x09,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper1_el0 // encoding: [0x29,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper2_el0 // encoding: [0x49,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper3_el0 // encoding: [0x69,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper4_el0 // encoding: [0x89,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper5_el0 // encoding: [0xa9,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper6_el0 // encoding: [0xc9,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper7_el0 // encoding: [0xe9,0xec,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper8_el0 // encoding: [0x09,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper9_el0 // encoding: [0x29,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper10_el0 // encoding: [0x49,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper11_el0 // encoding: [0x69,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper12_el0 // encoding: [0x89,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper13_el0 // encoding: [0xa9,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper14_el0 // encoding: [0xc9,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper15_el0 // encoding: [0xe9,0xed,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper16_el0 // encoding: [0x09,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper17_el0 // encoding: [0x29,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper18_el0 // encoding: [0x49,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper19_el0 // encoding: [0x69,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper20_el0 // encoding: [0x89,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper21_el0 // encoding: [0xa9,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper22_el0 // encoding: [0xc9,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper23_el0 // encoding: [0xe9,0xee,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper24_el0 // encoding: [0x09,0xef,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper25_el0 // encoding: [0x29,0xef,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper26_el0 // encoding: [0x49,0xef,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper27_el0 // encoding: [0x69,0xef,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper28_el0 // encoding: [0x89,0xef,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper29_el0 // encoding: [0xa9,0xef,0x3b,0xd5] -// CHECK: mrs x9, pmevtyper30_el0 // encoding: [0xc9,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{teecr32_el1|TEECR32_EL1}} // encoding: [0x09,0x00,0x32,0xd5] +// CHECK: mrs x9, {{osdtrrx_el1|OSDTRRX_EL1}} // encoding: [0x49,0x00,0x30,0xd5] +// CHECK: mrs x9, {{mdccsr_el0|MDCCSR_EL0}} // encoding: [0x09,0x01,0x33,0xd5] +// CHECK: mrs x9, {{mdccint_el1|MDCCINT_EL1}} // encoding: [0x09,0x02,0x30,0xd5] +// CHECK: mrs x9, {{mdscr_el1|MDSCR_EL1}} // encoding: [0x49,0x02,0x30,0xd5] +// CHECK: mrs x9, {{osdtrtx_el1|OSDTRTX_EL1}} // encoding: [0x49,0x03,0x30,0xd5] +// CHECK: mrs x9, {{dbgdtr_el0|DBGDTR_EL0}} // encoding: [0x09,0x04,0x33,0xd5] +// CHECK: mrs x9, {{dbgdtrrx_el0|DBGDTRRX_EL0}} // encoding: [0x09,0x05,0x33,0xd5] +// CHECK: mrs x9, {{oseccr_el1|OSECCR_EL1}} // encoding: [0x49,0x06,0x30,0xd5] +// CHECK: mrs x9, {{dbgvcr32_el2|DBGVCR32_EL2}} // encoding: [0x09,0x07,0x34,0xd5] +// CHECK: mrs x9, {{dbgbvr0_el1|DBGBVR0_EL1}} // encoding: [0x89,0x00,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr1_el1|DBGBVR1_EL1}} // encoding: [0x89,0x01,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr2_el1|DBGBVR2_EL1}} // encoding: [0x89,0x02,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr3_el1|DBGBVR3_EL1}} // encoding: [0x89,0x03,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr4_el1|DBGBVR4_EL1}} // encoding: [0x89,0x04,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr5_el1|DBGBVR5_EL1}} // encoding: [0x89,0x05,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr6_el1|DBGBVR6_EL1}} // encoding: [0x89,0x06,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr7_el1|DBGBVR7_EL1}} // encoding: [0x89,0x07,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr8_el1|DBGBVR8_EL1}} // encoding: [0x89,0x08,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr9_el1|DBGBVR9_EL1}} // encoding: [0x89,0x09,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr10_el1|DBGBVR10_EL1}} // encoding: [0x89,0x0a,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr11_el1|DBGBVR11_EL1}} // encoding: [0x89,0x0b,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr12_el1|DBGBVR12_EL1}} // encoding: [0x89,0x0c,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr13_el1|DBGBVR13_EL1}} // encoding: [0x89,0x0d,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr14_el1|DBGBVR14_EL1}} // encoding: [0x89,0x0e,0x30,0xd5] +// CHECK: mrs x9, {{dbgbvr15_el1|DBGBVR15_EL1}} // encoding: [0x89,0x0f,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr0_el1|DBGBCR0_EL1}} // encoding: [0xa9,0x00,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr1_el1|DBGBCR1_EL1}} // encoding: [0xa9,0x01,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr2_el1|DBGBCR2_EL1}} // encoding: [0xa9,0x02,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr3_el1|DBGBCR3_EL1}} // encoding: [0xa9,0x03,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr4_el1|DBGBCR4_EL1}} // encoding: [0xa9,0x04,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr5_el1|DBGBCR5_EL1}} // encoding: [0xa9,0x05,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr6_el1|DBGBCR6_EL1}} // encoding: [0xa9,0x06,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr7_el1|DBGBCR7_EL1}} // encoding: [0xa9,0x07,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr8_el1|DBGBCR8_EL1}} // encoding: [0xa9,0x08,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr9_el1|DBGBCR9_EL1}} // encoding: [0xa9,0x09,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr10_el1|DBGBCR10_EL1}} // encoding: [0xa9,0x0a,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr11_el1|DBGBCR11_EL1}} // encoding: [0xa9,0x0b,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr12_el1|DBGBCR12_EL1}} // encoding: [0xa9,0x0c,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr13_el1|DBGBCR13_EL1}} // encoding: [0xa9,0x0d,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr14_el1|DBGBCR14_EL1}} // encoding: [0xa9,0x0e,0x30,0xd5] +// CHECK: mrs x9, {{dbgbcr15_el1|DBGBCR15_EL1}} // encoding: [0xa9,0x0f,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr0_el1|DBGWVR0_EL1}} // encoding: [0xc9,0x00,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr1_el1|DBGWVR1_EL1}} // encoding: [0xc9,0x01,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr2_el1|DBGWVR2_EL1}} // encoding: [0xc9,0x02,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr3_el1|DBGWVR3_EL1}} // encoding: [0xc9,0x03,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr4_el1|DBGWVR4_EL1}} // encoding: [0xc9,0x04,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr5_el1|DBGWVR5_EL1}} // encoding: [0xc9,0x05,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr6_el1|DBGWVR6_EL1}} // encoding: [0xc9,0x06,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr7_el1|DBGWVR7_EL1}} // encoding: [0xc9,0x07,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr8_el1|DBGWVR8_EL1}} // encoding: [0xc9,0x08,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr9_el1|DBGWVR9_EL1}} // encoding: [0xc9,0x09,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr10_el1|DBGWVR10_EL1}} // encoding: [0xc9,0x0a,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr11_el1|DBGWVR11_EL1}} // encoding: [0xc9,0x0b,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr12_el1|DBGWVR12_EL1}} // encoding: [0xc9,0x0c,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr13_el1|DBGWVR13_EL1}} // encoding: [0xc9,0x0d,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr14_el1|DBGWVR14_EL1}} // encoding: [0xc9,0x0e,0x30,0xd5] +// CHECK: mrs x9, {{dbgwvr15_el1|DBGWVR15_EL1}} // encoding: [0xc9,0x0f,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr0_el1|DBGWCR0_EL1}} // encoding: [0xe9,0x00,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr1_el1|DBGWCR1_EL1}} // encoding: [0xe9,0x01,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr2_el1|DBGWCR2_EL1}} // encoding: [0xe9,0x02,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr3_el1|DBGWCR3_EL1}} // encoding: [0xe9,0x03,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr4_el1|DBGWCR4_EL1}} // encoding: [0xe9,0x04,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr5_el1|DBGWCR5_EL1}} // encoding: [0xe9,0x05,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr6_el1|DBGWCR6_EL1}} // encoding: [0xe9,0x06,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr7_el1|DBGWCR7_EL1}} // encoding: [0xe9,0x07,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr8_el1|DBGWCR8_EL1}} // encoding: [0xe9,0x08,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr9_el1|DBGWCR9_EL1}} // encoding: [0xe9,0x09,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr10_el1|DBGWCR10_EL1}} // encoding: [0xe9,0x0a,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr11_el1|DBGWCR11_EL1}} // encoding: [0xe9,0x0b,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr12_el1|DBGWCR12_EL1}} // encoding: [0xe9,0x0c,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr13_el1|DBGWCR13_EL1}} // encoding: [0xe9,0x0d,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr14_el1|DBGWCR14_EL1}} // encoding: [0xe9,0x0e,0x30,0xd5] +// CHECK: mrs x9, {{dbgwcr15_el1|DBGWCR15_EL1}} // encoding: [0xe9,0x0f,0x30,0xd5] +// CHECK: mrs x9, {{mdrar_el1|MDRAR_EL1}} // encoding: [0x09,0x10,0x30,0xd5] +// CHECK: mrs x9, {{teehbr32_el1|TEEHBR32_EL1}} // encoding: [0x09,0x10,0x32,0xd5] +// CHECK: mrs x9, {{oslsr_el1|OSLSR_EL1}} // encoding: [0x89,0x11,0x30,0xd5] +// CHECK: mrs x9, {{osdlr_el1|OSDLR_EL1}} // encoding: [0x89,0x13,0x30,0xd5] +// CHECK: mrs x9, {{dbgprcr_el1|DBGPRCR_EL1}} // encoding: [0x89,0x14,0x30,0xd5] +// CHECK: mrs x9, {{dbgclaimset_el1|DBGCLAIMSET_EL1}} // encoding: [0xc9,0x78,0x30,0xd5] +// CHECK: mrs x9, {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}} // encoding: [0xc9,0x79,0x30,0xd5] +// CHECK: mrs x9, {{dbgauthstatus_el1|DBGAUTHSTATUS_EL1}} // encoding: [0xc9,0x7e,0x30,0xd5] +// CHECK: mrs x9, {{midr_el1|MIDR_EL1}} // encoding: [0x09,0x00,0x38,0xd5] +// CHECK: mrs x9, {{ccsidr_el1|CCSIDR_EL1}} // encoding: [0x09,0x00,0x39,0xd5] +// CHECK: mrs x9, {{csselr_el1|CSSELR_EL1}} // encoding: [0x09,0x00,0x3a,0xd5] +// CHECK: mrs x9, {{vpidr_el2|VPIDR_EL2}} // encoding: [0x09,0x00,0x3c,0xd5] +// CHECK: mrs x9, {{clidr_el1|CLIDR_EL1}} // encoding: [0x29,0x00,0x39,0xd5] +// CHECK: mrs x9, {{ctr_el0|CTR_EL0}} // encoding: [0x29,0x00,0x3b,0xd5] +// CHECK: mrs x9, {{mpidr_el1|MPIDR_EL1}} // encoding: [0xa9,0x00,0x38,0xd5] +// CHECK: mrs x9, {{vmpidr_el2|VMPIDR_EL2}} // encoding: [0xa9,0x00,0x3c,0xd5] +// CHECK: mrs x9, {{revidr_el1|REVIDR_EL1}} // encoding: [0xc9,0x00,0x38,0xd5] +// CHECK: mrs x9, {{aidr_el1|AIDR_EL1}} // encoding: [0xe9,0x00,0x39,0xd5] +// CHECK: mrs x9, {{dczid_el0|DCZID_EL0}} // encoding: [0xe9,0x00,0x3b,0xd5] +// CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}} // encoding: [0x09,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}} // encoding: [0x29,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}} // encoding: [0x49,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}} // encoding: [0x69,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}} // encoding: [0x89,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}} // encoding: [0xa9,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}} // encoding: [0xc9,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}} // encoding: [0xe9,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}} // encoding: [0x09,0x02,0x38,0xd5] +// CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}} // encoding: [0x29,0x02,0x38,0xd5] +// CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}} // encoding: [0x49,0x02,0x38,0xd5] +// CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}} // encoding: [0x69,0x02,0x38,0xd5] +// CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}} // encoding: [0x89,0x02,0x38,0xd5] +// CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}} // encoding: [0xa9,0x02,0x38,0xd5] +// CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}} // encoding: [0x09,0x03,0x38,0xd5] +// CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}} // encoding: [0x29,0x03,0x38,0xd5] +// CHECK: mrs x9, {{mvfr2_el1|MVFR2_EL1}} // encoding: [0x49,0x03,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64pfr0_el1|ID_AA64PFR0_EL1}} // encoding: [0x09,0x04,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64pfr1_el1|ID_AA64PFR1_EL1}} // encoding: [0x29,0x04,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64dfr0_el1|ID_AA64DFR0_EL1}} // encoding: [0x09,0x05,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64dfr1_el1|ID_AA64DFR1_EL1}} // encoding: [0x29,0x05,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64afr0_el1|ID_AA64AFR0_EL1}} // encoding: [0x89,0x05,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64afr1_el1|ID_AA64AFR1_EL1}} // encoding: [0xa9,0x05,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64isar0_el1|ID_AA64ISAR0_EL1}} // encoding: [0x09,0x06,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64isar1_el1|ID_AA64ISAR1_EL1}} // encoding: [0x29,0x06,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64mmfr0_el1|ID_AA64MMFR0_EL1}} // encoding: [0x09,0x07,0x38,0xd5] +// CHECK: mrs x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}} // encoding: [0x29,0x07,0x38,0xd5] +// CHECK: mrs x9, {{sctlr_el1|SCTLR_EL1}} // encoding: [0x09,0x10,0x38,0xd5] +// CHECK: mrs x9, {{sctlr_el2|SCTLR_EL2}} // encoding: [0x09,0x10,0x3c,0xd5] +// CHECK: mrs x9, {{sctlr_el3|SCTLR_EL3}} // encoding: [0x09,0x10,0x3e,0xd5] +// CHECK: mrs x9, {{actlr_el1|ACTLR_EL1}} // encoding: [0x29,0x10,0x38,0xd5] +// CHECK: mrs x9, {{actlr_el2|ACTLR_EL2}} // encoding: [0x29,0x10,0x3c,0xd5] +// CHECK: mrs x9, {{actlr_el3|ACTLR_EL3}} // encoding: [0x29,0x10,0x3e,0xd5] +// CHECK: mrs x9, {{cpacr_el1|CPACR_EL1}} // encoding: [0x49,0x10,0x38,0xd5] +// CHECK: mrs x9, {{hcr_el2|HCR_EL2}} // encoding: [0x09,0x11,0x3c,0xd5] +// CHECK: mrs x9, {{scr_el3|SCR_EL3}} // encoding: [0x09,0x11,0x3e,0xd5] +// CHECK: mrs x9, {{mdcr_el2|MDCR_EL2}} // encoding: [0x29,0x11,0x3c,0xd5] +// CHECK: mrs x9, {{sder32_el3|SDER32_EL3}} // encoding: [0x29,0x11,0x3e,0xd5] +// CHECK: mrs x9, {{cptr_el2|CPTR_EL2}} // encoding: [0x49,0x11,0x3c,0xd5] +// CHECK: mrs x9, {{cptr_el3|CPTR_EL3}} // encoding: [0x49,0x11,0x3e,0xd5] +// CHECK: mrs x9, {{hstr_el2|HSTR_EL2}} // encoding: [0x69,0x11,0x3c,0xd5] +// CHECK: mrs x9, {{hacr_el2|HACR_EL2}} // encoding: [0xe9,0x11,0x3c,0xd5] +// CHECK: mrs x9, {{mdcr_el3|MDCR_EL3}} // encoding: [0x29,0x13,0x3e,0xd5] +// CHECK: mrs x9, {{ttbr0_el1|TTBR0_EL1}} // encoding: [0x09,0x20,0x38,0xd5] +// CHECK: mrs x9, {{ttbr0_el2|TTBR0_EL2}} // encoding: [0x09,0x20,0x3c,0xd5] +// CHECK: mrs x9, {{ttbr0_el3|TTBR0_EL3}} // encoding: [0x09,0x20,0x3e,0xd5] +// CHECK: mrs x9, {{ttbr1_el1|TTBR1_EL1}} // encoding: [0x29,0x20,0x38,0xd5] +// CHECK: mrs x9, {{tcr_el1|TCR_EL1}} // encoding: [0x49,0x20,0x38,0xd5] +// CHECK: mrs x9, {{tcr_el2|TCR_EL2}} // encoding: [0x49,0x20,0x3c,0xd5] +// CHECK: mrs x9, {{tcr_el3|TCR_EL3}} // encoding: [0x49,0x20,0x3e,0xd5] +// CHECK: mrs x9, {{vttbr_el2|VTTBR_EL2}} // encoding: [0x09,0x21,0x3c,0xd5] +// CHECK: mrs x9, {{vtcr_el2|VTCR_EL2}} // encoding: [0x49,0x21,0x3c,0xd5] +// CHECK: mrs x9, {{dacr32_el2|DACR32_EL2}} // encoding: [0x09,0x30,0x3c,0xd5] +// CHECK: mrs x9, {{spsr_el1|SPSR_EL1}} // encoding: [0x09,0x40,0x38,0xd5] +// CHECK: mrs x9, {{spsr_el2|SPSR_EL2}} // encoding: [0x09,0x40,0x3c,0xd5] +// CHECK: mrs x9, {{spsr_el3|SPSR_EL3}} // encoding: [0x09,0x40,0x3e,0xd5] +// CHECK: mrs x9, {{elr_el1|ELR_EL1}} // encoding: [0x29,0x40,0x38,0xd5] +// CHECK: mrs x9, {{elr_el2|ELR_EL2}} // encoding: [0x29,0x40,0x3c,0xd5] +// CHECK: mrs x9, {{elr_el3|ELR_EL3}} // encoding: [0x29,0x40,0x3e,0xd5] +// CHECK: mrs x9, {{sp_el0|SP_EL0}} // encoding: [0x09,0x41,0x38,0xd5] +// CHECK: mrs x9, {{sp_el1|SP_EL1}} // encoding: [0x09,0x41,0x3c,0xd5] +// CHECK: mrs x9, {{sp_el2|SP_EL2}} // encoding: [0x09,0x41,0x3e,0xd5] +// CHECK: mrs x9, {{spsel|SPSEL}} // encoding: [0x09,0x42,0x38,0xd5] +// CHECK: mrs x9, {{nzcv|NZCV}} // encoding: [0x09,0x42,0x3b,0xd5] +// CHECK: mrs x9, {{daif|DAIF}} // encoding: [0x29,0x42,0x3b,0xd5] +// CHECK: mrs x9, {{currentel|CURRENTEL}} // encoding: [0x49,0x42,0x38,0xd5] +// CHECK: mrs x9, {{spsr_irq|SPSR_IRQ}} // encoding: [0x09,0x43,0x3c,0xd5] +// CHECK: mrs x9, {{spsr_abt|SPSR_ABT}} // encoding: [0x29,0x43,0x3c,0xd5] +// CHECK: mrs x9, {{spsr_und|SPSR_UND}} // encoding: [0x49,0x43,0x3c,0xd5] +// CHECK: mrs x9, {{spsr_fiq|SPSR_FIQ}} // encoding: [0x69,0x43,0x3c,0xd5] +// CHECK: mrs x9, {{fpcr|FPCR}} // encoding: [0x09,0x44,0x3b,0xd5] +// CHECK: mrs x9, {{fpsr|FPSR}} // encoding: [0x29,0x44,0x3b,0xd5] +// CHECK: mrs x9, {{dspsr_el0|DSPSR_EL0}} // encoding: [0x09,0x45,0x3b,0xd5] +// CHECK: mrs x9, {{dlr_el0|DLR_EL0}} // encoding: [0x29,0x45,0x3b,0xd5] +// CHECK: mrs x9, {{ifsr32_el2|IFSR32_EL2}} // encoding: [0x29,0x50,0x3c,0xd5] +// CHECK: mrs x9, {{afsr0_el1|AFSR0_EL1}} // encoding: [0x09,0x51,0x38,0xd5] +// CHECK: mrs x9, {{afsr0_el2|AFSR0_EL2}} // encoding: [0x09,0x51,0x3c,0xd5] +// CHECK: mrs x9, {{afsr0_el3|AFSR0_EL3}} // encoding: [0x09,0x51,0x3e,0xd5] +// CHECK: mrs x9, {{afsr1_el1|AFSR1_EL1}} // encoding: [0x29,0x51,0x38,0xd5] +// CHECK: mrs x9, {{afsr1_el2|AFSR1_EL2}} // encoding: [0x29,0x51,0x3c,0xd5] +// CHECK: mrs x9, {{afsr1_el3|AFSR1_EL3}} // encoding: [0x29,0x51,0x3e,0xd5] +// CHECK: mrs x9, {{esr_el1|ESR_EL1}} // encoding: [0x09,0x52,0x38,0xd5] +// CHECK: mrs x9, {{esr_el2|ESR_EL2}} // encoding: [0x09,0x52,0x3c,0xd5] +// CHECK: mrs x9, {{esr_el3|ESR_EL3}} // encoding: [0x09,0x52,0x3e,0xd5] +// CHECK: mrs x9, {{fpexc32_el2|FPEXC32_EL2}} // encoding: [0x09,0x53,0x3c,0xd5] +// CHECK: mrs x9, {{far_el1|FAR_EL1}} // encoding: [0x09,0x60,0x38,0xd5] +// CHECK: mrs x9, {{far_el2|FAR_EL2}} // encoding: [0x09,0x60,0x3c,0xd5] +// CHECK: mrs x9, {{far_el3|FAR_EL3}} // encoding: [0x09,0x60,0x3e,0xd5] +// CHECK: mrs x9, {{hpfar_el2|HPFAR_EL2}} // encoding: [0x89,0x60,0x3c,0xd5] +// CHECK: mrs x9, {{par_el1|PAR_EL1}} // encoding: [0x09,0x74,0x38,0xd5] +// CHECK: mrs x9, {{pmcr_el0|PMCR_EL0}} // encoding: [0x09,0x9c,0x3b,0xd5] +// CHECK: mrs x9, {{pmcntenset_el0|PMCNTENSET_EL0}} // encoding: [0x29,0x9c,0x3b,0xd5] +// CHECK: mrs x9, {{pmcntenclr_el0|PMCNTENCLR_EL0}} // encoding: [0x49,0x9c,0x3b,0xd5] +// CHECK: mrs x9, {{pmovsclr_el0|PMOVSCLR_EL0}} // encoding: [0x69,0x9c,0x3b,0xd5] +// CHECK: mrs x9, {{pmselr_el0|PMSELR_EL0}} // encoding: [0xa9,0x9c,0x3b,0xd5] +// CHECK: mrs x9, {{pmceid0_el0|PMCEID0_EL0}} // encoding: [0xc9,0x9c,0x3b,0xd5] +// CHECK: mrs x9, {{pmceid1_el0|PMCEID1_EL0}} // encoding: [0xe9,0x9c,0x3b,0xd5] +// CHECK: mrs x9, {{pmccntr_el0|PMCCNTR_EL0}} // encoding: [0x09,0x9d,0x3b,0xd5] +// CHECK: mrs x9, {{pmxevtyper_el0|PMXEVTYPER_EL0}} // encoding: [0x29,0x9d,0x3b,0xd5] +// CHECK: mrs x9, {{pmxevcntr_el0|PMXEVCNTR_EL0}} // encoding: [0x49,0x9d,0x3b,0xd5] +// CHECK: mrs x9, {{pmuserenr_el0|PMUSERENR_EL0}} // encoding: [0x09,0x9e,0x3b,0xd5] +// CHECK: mrs x9, {{pmintenset_el1|PMINTENSET_EL1}} // encoding: [0x29,0x9e,0x38,0xd5] +// CHECK: mrs x9, {{pmintenclr_el1|PMINTENCLR_EL1}} // encoding: [0x49,0x9e,0x38,0xd5] +// CHECK: mrs x9, {{pmovsset_el0|PMOVSSET_EL0}} // encoding: [0x69,0x9e,0x3b,0xd5] +// CHECK: mrs x9, {{mair_el1|MAIR_EL1}} // encoding: [0x09,0xa2,0x38,0xd5] +// CHECK: mrs x9, {{mair_el2|MAIR_EL2}} // encoding: [0x09,0xa2,0x3c,0xd5] +// CHECK: mrs x9, {{mair_el3|MAIR_EL3}} // encoding: [0x09,0xa2,0x3e,0xd5] +// CHECK: mrs x9, {{amair_el1|AMAIR_EL1}} // encoding: [0x09,0xa3,0x38,0xd5] +// CHECK: mrs x9, {{amair_el2|AMAIR_EL2}} // encoding: [0x09,0xa3,0x3c,0xd5] +// CHECK: mrs x9, {{amair_el3|AMAIR_EL3}} // encoding: [0x09,0xa3,0x3e,0xd5] +// CHECK: mrs x9, {{vbar_el1|VBAR_EL1}} // encoding: [0x09,0xc0,0x38,0xd5] +// CHECK: mrs x9, {{vbar_el2|VBAR_EL2}} // encoding: [0x09,0xc0,0x3c,0xd5] +// CHECK: mrs x9, {{vbar_el3|VBAR_EL3}} // encoding: [0x09,0xc0,0x3e,0xd5] +// CHECK: mrs x9, {{rvbar_el1|RVBAR_EL1}} // encoding: [0x29,0xc0,0x38,0xd5] +// CHECK: mrs x9, {{rvbar_el2|RVBAR_EL2}} // encoding: [0x29,0xc0,0x3c,0xd5] +// CHECK: mrs x9, {{rvbar_el3|RVBAR_EL3}} // encoding: [0x29,0xc0,0x3e,0xd5] +// CHECK: mrs x9, {{rmr_el1|RMR_EL1}} // encoding: [0x49,0xc0,0x38,0xd5] +// CHECK: mrs x9, {{rmr_el2|RMR_EL2}} // encoding: [0x49,0xc0,0x3c,0xd5] +// CHECK: mrs x9, {{rmr_el3|RMR_EL3}} // encoding: [0x49,0xc0,0x3e,0xd5] +// CHECK: mrs x9, {{isr_el1|ISR_EL1}} // encoding: [0x09,0xc1,0x38,0xd5] +// CHECK: mrs x9, {{contextidr_el1|CONTEXTIDR_EL1}} // encoding: [0x29,0xd0,0x38,0xd5] +// CHECK: mrs x9, {{tpidr_el0|TPIDR_EL0}} // encoding: [0x49,0xd0,0x3b,0xd5] +// CHECK: mrs x9, {{tpidr_el2|TPIDR_EL2}} // encoding: [0x49,0xd0,0x3c,0xd5] +// CHECK: mrs x9, {{tpidr_el3|TPIDR_EL3}} // encoding: [0x49,0xd0,0x3e,0xd5] +// CHECK: mrs x9, {{tpidrro_el0|TPIDRRO_EL0}} // encoding: [0x69,0xd0,0x3b,0xd5] +// CHECK: mrs x9, {{tpidr_el1|TPIDR_EL1}} // encoding: [0x89,0xd0,0x38,0xd5] +// CHECK: mrs x9, {{cntfrq_el0|CNTFRQ_EL0}} // encoding: [0x09,0xe0,0x3b,0xd5] +// CHECK: mrs x9, {{cntpct_el0|CNTPCT_EL0}} // encoding: [0x29,0xe0,0x3b,0xd5] +// CHECK: mrs x9, {{cntvct_el0|CNTVCT_EL0}} // encoding: [0x49,0xe0,0x3b,0xd5] +// CHECK: mrs x9, {{cntvoff_el2|CNTVOFF_EL2}} // encoding: [0x69,0xe0,0x3c,0xd5] +// CHECK: mrs x9, {{cntkctl_el1|CNTKCTL_EL1}} // encoding: [0x09,0xe1,0x38,0xd5] +// CHECK: mrs x9, {{cnthctl_el2|CNTHCTL_EL2}} // encoding: [0x09,0xe1,0x3c,0xd5] +// CHECK: mrs x9, {{cntp_tval_el0|CNTP_TVAL_EL0}} // encoding: [0x09,0xe2,0x3b,0xd5] +// CHECK: mrs x9, {{cnthp_tval_el2|CNTHP_TVAL_EL2}} // encoding: [0x09,0xe2,0x3c,0xd5] +// CHECK: mrs x9, {{cntps_tval_el1|CNTPS_TVAL_EL1}} // encoding: [0x09,0xe2,0x3f,0xd5] +// CHECK: mrs x9, {{cntp_ctl_el0|CNTP_CTL_EL0}} // encoding: [0x29,0xe2,0x3b,0xd5] +// CHECK: mrs x9, {{cnthp_ctl_el2|CNTHP_CTL_EL2}} // encoding: [0x29,0xe2,0x3c,0xd5] +// CHECK: mrs x9, {{cntps_ctl_el1|CNTPS_CTL_EL1}} // encoding: [0x29,0xe2,0x3f,0xd5] +// CHECK: mrs x9, {{cntp_cval_el0|CNTP_CVAL_EL0}} // encoding: [0x49,0xe2,0x3b,0xd5] +// CHECK: mrs x9, {{cnthp_cval_el2|CNTHP_CVAL_EL2}} // encoding: [0x49,0xe2,0x3c,0xd5] +// CHECK: mrs x9, {{cntps_cval_el1|CNTPS_CVAL_EL1}} // encoding: [0x49,0xe2,0x3f,0xd5] +// CHECK: mrs x9, {{cntv_tval_el0|CNTV_TVAL_EL0}} // encoding: [0x09,0xe3,0x3b,0xd5] +// CHECK: mrs x9, {{cntv_ctl_el0|CNTV_CTL_EL0}} // encoding: [0x29,0xe3,0x3b,0xd5] +// CHECK: mrs x9, {{cntv_cval_el0|CNTV_CVAL_EL0}} // encoding: [0x49,0xe3,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr0_el0|PMEVCNTR0_EL0}} // encoding: [0x09,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr1_el0|PMEVCNTR1_EL0}} // encoding: [0x29,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr2_el0|PMEVCNTR2_EL0}} // encoding: [0x49,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr3_el0|PMEVCNTR3_EL0}} // encoding: [0x69,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr4_el0|PMEVCNTR4_EL0}} // encoding: [0x89,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr5_el0|PMEVCNTR5_EL0}} // encoding: [0xa9,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr6_el0|PMEVCNTR6_EL0}} // encoding: [0xc9,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr7_el0|PMEVCNTR7_EL0}} // encoding: [0xe9,0xe8,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr8_el0|PMEVCNTR8_EL0}} // encoding: [0x09,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr9_el0|PMEVCNTR9_EL0}} // encoding: [0x29,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr10_el0|PMEVCNTR10_EL0}} // encoding: [0x49,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr11_el0|PMEVCNTR11_EL0}} // encoding: [0x69,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr12_el0|PMEVCNTR12_EL0}} // encoding: [0x89,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr13_el0|PMEVCNTR13_EL0}} // encoding: [0xa9,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr14_el0|PMEVCNTR14_EL0}} // encoding: [0xc9,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr15_el0|PMEVCNTR15_EL0}} // encoding: [0xe9,0xe9,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr16_el0|PMEVCNTR16_EL0}} // encoding: [0x09,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr17_el0|PMEVCNTR17_EL0}} // encoding: [0x29,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr18_el0|PMEVCNTR18_EL0}} // encoding: [0x49,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr19_el0|PMEVCNTR19_EL0}} // encoding: [0x69,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr20_el0|PMEVCNTR20_EL0}} // encoding: [0x89,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr21_el0|PMEVCNTR21_EL0}} // encoding: [0xa9,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr22_el0|PMEVCNTR22_EL0}} // encoding: [0xc9,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr23_el0|PMEVCNTR23_EL0}} // encoding: [0xe9,0xea,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr24_el0|PMEVCNTR24_EL0}} // encoding: [0x09,0xeb,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr25_el0|PMEVCNTR25_EL0}} // encoding: [0x29,0xeb,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr26_el0|PMEVCNTR26_EL0}} // encoding: [0x49,0xeb,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr27_el0|PMEVCNTR27_EL0}} // encoding: [0x69,0xeb,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr28_el0|PMEVCNTR28_EL0}} // encoding: [0x89,0xeb,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr29_el0|PMEVCNTR29_EL0}} // encoding: [0xa9,0xeb,0x3b,0xd5] +// CHECK: mrs x9, {{pmevcntr30_el0|PMEVCNTR30_EL0}} // encoding: [0xc9,0xeb,0x3b,0xd5] +// CHECK: mrs x9, {{pmccfiltr_el0|PMCCFILTR_EL0}} // encoding: [0xe9,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper0_el0|PMEVTYPER0_EL0}} // encoding: [0x09,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper1_el0|PMEVTYPER1_EL0}} // encoding: [0x29,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper2_el0|PMEVTYPER2_EL0}} // encoding: [0x49,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper3_el0|PMEVTYPER3_EL0}} // encoding: [0x69,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper4_el0|PMEVTYPER4_EL0}} // encoding: [0x89,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper5_el0|PMEVTYPER5_EL0}} // encoding: [0xa9,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper6_el0|PMEVTYPER6_EL0}} // encoding: [0xc9,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper7_el0|PMEVTYPER7_EL0}} // encoding: [0xe9,0xec,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper8_el0|PMEVTYPER8_EL0}} // encoding: [0x09,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper9_el0|PMEVTYPER9_EL0}} // encoding: [0x29,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper10_el0|PMEVTYPER10_EL0}} // encoding: [0x49,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper11_el0|PMEVTYPER11_EL0}} // encoding: [0x69,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper12_el0|PMEVTYPER12_EL0}} // encoding: [0x89,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper13_el0|PMEVTYPER13_EL0}} // encoding: [0xa9,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper14_el0|PMEVTYPER14_EL0}} // encoding: [0xc9,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper15_el0|PMEVTYPER15_EL0}} // encoding: [0xe9,0xed,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper16_el0|PMEVTYPER16_EL0}} // encoding: [0x09,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper17_el0|PMEVTYPER17_EL0}} // encoding: [0x29,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper18_el0|PMEVTYPER18_EL0}} // encoding: [0x49,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper19_el0|PMEVTYPER19_EL0}} // encoding: [0x69,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper20_el0|PMEVTYPER20_EL0}} // encoding: [0x89,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper21_el0|PMEVTYPER21_EL0}} // encoding: [0xa9,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper22_el0|PMEVTYPER22_EL0}} // encoding: [0xc9,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper23_el0|PMEVTYPER23_EL0}} // encoding: [0xe9,0xee,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper24_el0|PMEVTYPER24_EL0}} // encoding: [0x09,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper25_el0|PMEVTYPER25_EL0}} // encoding: [0x29,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper26_el0|PMEVTYPER26_EL0}} // encoding: [0x49,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper27_el0|PMEVTYPER27_EL0}} // encoding: [0x69,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper28_el0|PMEVTYPER28_EL0}} // encoding: [0x89,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper29_el0|PMEVTYPER29_EL0}} // encoding: [0xa9,0xef,0x3b,0xd5] +// CHECK: mrs x9, {{pmevtyper30_el0|PMEVTYPER30_EL0}} // encoding: [0xc9,0xef,0x3b,0xd5] mrs x12, s3_7_c15_c1_5 mrs x13, s3_2_c11_c15_7 msr s3_0_c15_c0_0, x12 msr s3_7_c11_c13_7, x5 -// CHECK: mrs x12, s3_7_c15_c1_5 // encoding: [0xac,0xf1,0x3f,0xd5] -// CHECK: mrs x13, s3_2_c11_c15_7 // encoding: [0xed,0xbf,0x3a,0xd5] -// CHECK: msr s3_0_c15_c0_0, x12 // encoding: [0x0c,0xf0,0x18,0xd5] -// CHECK: msr s3_7_c11_c13_7, x5 // encoding: [0xe5,0xbd,0x1f,0xd5] +// CHECK: mrs x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}} // encoding: [0xac,0xf1,0x3f,0xd5] +// CHECK: mrs x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}} // encoding: [0xed,0xbf,0x3a,0xd5] +// CHECK: msr {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12 // encoding: [0x0c,0xf0,0x18,0xd5] +// CHECK: msr {{s3_7_c11_c13_7|S3_7_C11_C13_7}}, x5 // encoding: [0xe5,0xbd,0x1f,0xd5] //------------------------------------------------------------------------------ // Unconditional branch (immediate) @@ -4814,22 +4781,25 @@ _func: tbz x5, #0, somewhere tbz xzr, #63, elsewhere tbnz x5, #45, nowhere -// CHECK: tbz x5, #0, somewhere // encoding: [0x05'A',A,A,0x36'A'] -// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_a64_tstbr -// CHECK: tbz xzr, #63, elsewhere // encoding: [0x1f'A',A,0xf8'A',0xb6'A'] -// CHECK: // fixup A - offset: 0, value: elsewhere, kind: fixup_a64_tstbr -// CHECK: tbnz x5, #45, nowhere // encoding: [0x05'A',A,0x68'A',0xb7'A'] -// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_a64_tstbr + +// CHECK: tbz w5, #0, somewhere // encoding: [0bAAA00101,A,0b00000AAA,0x36] +// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_aarch64_pcrel_branch14 +// CHECK: tbz xzr, #63, elsewhere // encoding: [0bAAA11111,A,0b11111AAA,0xb6] +// CHECK: // fixup A - offset: 0, value: elsewhere, kind: fixup_aarch64_pcrel_branch14 +// CHECK: tbnz x5, #45, nowhere // encoding: [0bAAA00101,A,0b01101AAA,0xb7] +// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_aarch64_pcrel_branch14 + tbnz w3, #2, there tbnz wzr, #31, nowhere tbz w5, #12, anywhere -// CHECK: tbnz w3, #2, there // encoding: [0x03'A',A,0x10'A',0x37'A'] -// CHECK: // fixup A - offset: 0, value: there, kind: fixup_a64_tstbr -// CHECK: tbnz wzr, #31, nowhere // encoding: [0x1f'A',A,0xf8'A',0x37'A'] -// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_a64_tstbr -// CHECK: tbz w5, #12, anywhere // encoding: [0x05'A',A,0x60'A',0x36'A'] -// CHECK: // fixup A - offset: 0, value: anywhere, kind: fixup_a64_tstbr + +// CHECK: tbnz w3, #2, there // encoding: [0bAAA00011,A,0b00010AAA,0x37] +// CHECK: // fixup A - offset: 0, value: there, kind: fixup_aarch64_pcrel_branch14 +// CHECK: tbnz wzr, #31, nowhere // encoding: [0bAAA11111,A,0b11111AAA,0x37] +// CHECK: // fixup A - offset: 0, value: nowhere, kind: fixup_aarch64_pcrel_branch14 +// CHECK: tbz w5, #12, anywhere // encoding: [0bAAA00101,A,0b01100AAA,0x36] +// CHECK: // fixup A - offset: 0, value: anywhere, kind: fixup_aarch64_pcrel_branch14 //------------------------------------------------------------------------------ // Unconditional branch (immediate) @@ -4837,10 +4807,11 @@ _func: b somewhere bl elsewhere -// CHECK: b somewhere // encoding: [A,A,A,0x14'A'] -// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_a64_uncondbr -// CHECK: bl elsewhere // encoding: [A,A,A,0x94'A'] -// CHECK: // fixup A - offset: 0, value: elsewhere, kind: fixup_a64_call + +// CHECK: b somewhere // encoding: [A,A,A,0b000101AA] +// CHECK: // fixup A - offset: 0, value: somewhere, kind: fixup_aarch64_pcrel_branch26 +// CHECK: bl elsewhere // encoding: [A,A,A,0b100101AA] +// CHECK: // fixup A - offset: 0, value: elsewhere, kind: fixup_aarch64_pcrel_call26 b #4 bl #0 diff --git a/test/MC/AArch64/elf-globaladdress.ll b/test/MC/AArch64/elf-globaladdress.ll index bc43113..7d031e6 100644 --- a/test/MC/AArch64/elf-globaladdress.ll +++ b/test/MC/AArch64/elf-globaladdress.ll @@ -3,7 +3,7 @@ ; Also take it on a round-trip through llvm-mc to stretch assembly-parsing's legs: ;; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | \ -;; RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj -o - | \ +;; RUN: llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -o - | \ ;; RUN: llvm-readobj -h -r | FileCheck -check-prefix=OBJ %s @var8 = global i8 0 diff --git a/test/MC/AArch64/elf-reloc-addend.s b/test/MC/AArch64/elf-reloc-addend.s deleted file mode 100644 index 0e7e2ca..0000000 --- a/test/MC/AArch64/elf-reloc-addend.s +++ /dev/null @@ -1,8 +0,0 @@ -// RUN: llvm-mc -triple=aarch64-linux-gnu -filetype=obj -o - %s | llvm-objdump -triple=aarch64-linux-gnu -r - | FileCheck %s - - add x0, x4, #:lo12:sym -// CHECK: 0 R_AARCH64_ADD_ABS_LO12_NC sym - add x3, x5, #:lo12:sym+1 -// CHECK: 4 R_AARCH64_ADD_ABS_LO12_NC sym+1 - add x3, x5, #:lo12:sym-1 -// CHECK: 8 R_AARCH64_ADD_ABS_LO12_NC sym-1 diff --git a/test/MC/AArch64/gicv3-regs.s b/test/MC/AArch64/gicv3-regs.s index f777651..0f5742e 100644 --- a/test/MC/AArch64/gicv3-regs.s +++ b/test/MC/AArch64/gicv3-regs.s @@ -56,62 +56,62 @@ mrs x8, ich_lr13_el2 mrs x2, ich_lr14_el2 mrs x8, ich_lr15_el2 -// CHECK: mrs x8, icc_iar1_el1 // encoding: [0x08,0xcc,0x38,0xd5] -// CHECK: mrs x26, icc_iar0_el1 // encoding: [0x1a,0xc8,0x38,0xd5] -// CHECK: mrs x2, icc_hppir1_el1 // encoding: [0x42,0xcc,0x38,0xd5] -// CHECK: mrs x17, icc_hppir0_el1 // encoding: [0x51,0xc8,0x38,0xd5] -// CHECK: mrs x29, icc_rpr_el1 // encoding: [0x7d,0xcb,0x38,0xd5] -// CHECK: mrs x4, ich_vtr_el2 // encoding: [0x24,0xcb,0x3c,0xd5] -// CHECK: mrs x24, ich_eisr_el2 // encoding: [0x78,0xcb,0x3c,0xd5] -// CHECK: mrs x9, ich_elsr_el2 // encoding: [0xa9,0xcb,0x3c,0xd5] -// CHECK: mrs x24, icc_bpr1_el1 // encoding: [0x78,0xcc,0x38,0xd5] -// CHECK: mrs x14, icc_bpr0_el1 // encoding: [0x6e,0xc8,0x38,0xd5] -// CHECK: mrs x19, icc_pmr_el1 // encoding: [0x13,0x46,0x38,0xd5] -// CHECK: mrs x23, icc_ctlr_el1 // encoding: [0x97,0xcc,0x38,0xd5] -// CHECK: mrs x20, icc_ctlr_el3 // encoding: [0x94,0xcc,0x3e,0xd5] -// CHECK: mrs x28, icc_sre_el1 // encoding: [0xbc,0xcc,0x38,0xd5] -// CHECK: mrs x25, icc_sre_el2 // encoding: [0xb9,0xc9,0x3c,0xd5] -// CHECK: mrs x8, icc_sre_el3 // encoding: [0xa8,0xcc,0x3e,0xd5] -// CHECK: mrs x22, icc_igrpen0_el1 // encoding: [0xd6,0xcc,0x38,0xd5] -// CHECK: mrs x5, icc_igrpen1_el1 // encoding: [0xe5,0xcc,0x38,0xd5] -// CHECK: mrs x7, icc_igrpen1_el3 // encoding: [0xe7,0xcc,0x3e,0xd5] -// CHECK: mrs x22, icc_seien_el1 // encoding: [0x16,0xcd,0x38,0xd5] -// CHECK: mrs x4, icc_ap0r0_el1 // encoding: [0x84,0xc8,0x38,0xd5] -// CHECK: mrs x11, icc_ap0r1_el1 // encoding: [0xab,0xc8,0x38,0xd5] -// CHECK: mrs x27, icc_ap0r2_el1 // encoding: [0xdb,0xc8,0x38,0xd5] -// CHECK: mrs x21, icc_ap0r3_el1 // encoding: [0xf5,0xc8,0x38,0xd5] -// CHECK: mrs x2, icc_ap1r0_el1 // encoding: [0x02,0xc9,0x38,0xd5] -// CHECK: mrs x21, icc_ap1r1_el1 // encoding: [0x35,0xc9,0x38,0xd5] -// CHECK: mrs x10, icc_ap1r2_el1 // encoding: [0x4a,0xc9,0x38,0xd5] -// CHECK: mrs x27, icc_ap1r3_el1 // encoding: [0x7b,0xc9,0x38,0xd5] -// CHECK: mrs x20, ich_ap0r0_el2 // encoding: [0x14,0xc8,0x3c,0xd5] -// CHECK: mrs x21, ich_ap0r1_el2 // encoding: [0x35,0xc8,0x3c,0xd5] -// CHECK: mrs x5, ich_ap0r2_el2 // encoding: [0x45,0xc8,0x3c,0xd5] -// CHECK: mrs x4, ich_ap0r3_el2 // encoding: [0x64,0xc8,0x3c,0xd5] -// CHECK: mrs x15, ich_ap1r0_el2 // encoding: [0x0f,0xc9,0x3c,0xd5] -// CHECK: mrs x12, ich_ap1r1_el2 // encoding: [0x2c,0xc9,0x3c,0xd5] -// CHECK: mrs x27, ich_ap1r2_el2 // encoding: [0x5b,0xc9,0x3c,0xd5] -// CHECK: mrs x20, ich_ap1r3_el2 // encoding: [0x74,0xc9,0x3c,0xd5] -// CHECK: mrs x10, ich_hcr_el2 // encoding: [0x0a,0xcb,0x3c,0xd5] -// CHECK: mrs x27, ich_misr_el2 // encoding: [0x5b,0xcb,0x3c,0xd5] -// CHECK: mrs x6, ich_vmcr_el2 // encoding: [0xe6,0xcb,0x3c,0xd5] -// CHECK: mrs x19, ich_vseir_el2 // encoding: [0x93,0xc9,0x3c,0xd5] -// CHECK: mrs x3, ich_lr0_el2 // encoding: [0x03,0xcc,0x3c,0xd5] -// CHECK: mrs x1, ich_lr1_el2 // encoding: [0x21,0xcc,0x3c,0xd5] -// CHECK: mrs x22, ich_lr2_el2 // encoding: [0x56,0xcc,0x3c,0xd5] -// CHECK: mrs x21, ich_lr3_el2 // encoding: [0x75,0xcc,0x3c,0xd5] -// CHECK: mrs x6, ich_lr4_el2 // encoding: [0x86,0xcc,0x3c,0xd5] -// CHECK: mrs x10, ich_lr5_el2 // encoding: [0xaa,0xcc,0x3c,0xd5] -// CHECK: mrs x11, ich_lr6_el2 // encoding: [0xcb,0xcc,0x3c,0xd5] -// CHECK: mrs x12, ich_lr7_el2 // encoding: [0xec,0xcc,0x3c,0xd5] -// CHECK: mrs x0, ich_lr8_el2 // encoding: [0x00,0xcd,0x3c,0xd5] -// CHECK: mrs x21, ich_lr9_el2 // encoding: [0x35,0xcd,0x3c,0xd5] -// CHECK: mrs x13, ich_lr10_el2 // encoding: [0x4d,0xcd,0x3c,0xd5] -// CHECK: mrs x26, ich_lr11_el2 // encoding: [0x7a,0xcd,0x3c,0xd5] -// CHECK: mrs x1, ich_lr12_el2 // encoding: [0x81,0xcd,0x3c,0xd5] -// CHECK: mrs x8, ich_lr13_el2 // encoding: [0xa8,0xcd,0x3c,0xd5] -// CHECK: mrs x2, ich_lr14_el2 // encoding: [0xc2,0xcd,0x3c,0xd5] -// CHECK: mrs x8, ich_lr15_el2 // encoding: [0xe8,0xcd,0x3c,0xd5] +// CHECK: mrs x8, {{icc_iar1_el1|ICC_IAR1_EL1}} // encoding: [0x08,0xcc,0x38,0xd5] +// CHECK: mrs x26, {{icc_iar0_el1|ICC_IAR0_EL1}} // encoding: [0x1a,0xc8,0x38,0xd5] +// CHECK: mrs x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}} // encoding: [0x42,0xcc,0x38,0xd5] +// CHECK: mrs x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}} // encoding: [0x51,0xc8,0x38,0xd5] +// CHECK: mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}} // encoding: [0x7d,0xcb,0x38,0xd5] +// CHECK: mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}} // encoding: [0x24,0xcb,0x3c,0xd5] +// CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}} // encoding: [0x78,0xcb,0x3c,0xd5] +// CHECK: mrs x9, {{ich_elsr_el2|ICH_ELSR_EL2}} // encoding: [0xa9,0xcb,0x3c,0xd5] +// CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}} // encoding: [0x78,0xcc,0x38,0xd5] +// CHECK: mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}} // encoding: [0x6e,0xc8,0x38,0xd5] +// CHECK: mrs x19, {{icc_pmr_el1|ICC_PMR_EL1}} // encoding: [0x13,0x46,0x38,0xd5] +// CHECK: mrs x23, {{icc_ctlr_el1|ICC_CTLR_EL1}} // encoding: [0x97,0xcc,0x38,0xd5] +// CHECK: mrs x20, {{icc_ctlr_el3|ICC_CTLR_EL3}} // encoding: [0x94,0xcc,0x3e,0xd5] +// CHECK: mrs x28, {{icc_sre_el1|ICC_SRE_EL1}} // encoding: [0xbc,0xcc,0x38,0xd5] +// CHECK: mrs x25, {{icc_sre_el2|ICC_SRE_EL2}} // encoding: [0xb9,0xc9,0x3c,0xd5] +// CHECK: mrs x8, {{icc_sre_el3|ICC_SRE_EL3}} // encoding: [0xa8,0xcc,0x3e,0xd5] +// CHECK: mrs x22, {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}} // encoding: [0xd6,0xcc,0x38,0xd5] +// CHECK: mrs x5, {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}} // encoding: [0xe5,0xcc,0x38,0xd5] +// CHECK: mrs x7, {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}} // encoding: [0xe7,0xcc,0x3e,0xd5] +// CHECK: mrs x22, {{icc_seien_el1|ICC_SEIEN_EL1}} // encoding: [0x16,0xcd,0x38,0xd5] +// CHECK: mrs x4, {{icc_ap0r0_el1|ICC_AP0R0_EL1}} // encoding: [0x84,0xc8,0x38,0xd5] +// CHECK: mrs x11, {{icc_ap0r1_el1|ICC_AP0R1_EL1}} // encoding: [0xab,0xc8,0x38,0xd5] +// CHECK: mrs x27, {{icc_ap0r2_el1|ICC_AP0R2_EL1}} // encoding: [0xdb,0xc8,0x38,0xd5] +// CHECK: mrs x21, {{icc_ap0r3_el1|ICC_AP0R3_EL1}} // encoding: [0xf5,0xc8,0x38,0xd5] +// CHECK: mrs x2, {{icc_ap1r0_el1|ICC_AP1R0_EL1}} // encoding: [0x02,0xc9,0x38,0xd5] +// CHECK: mrs x21, {{icc_ap1r1_el1|ICC_AP1R1_EL1}} // encoding: [0x35,0xc9,0x38,0xd5] +// CHECK: mrs x10, {{icc_ap1r2_el1|ICC_AP1R2_EL1}} // encoding: [0x4a,0xc9,0x38,0xd5] +// CHECK: mrs x27, {{icc_ap1r3_el1|ICC_AP1R3_EL1}} // encoding: [0x7b,0xc9,0x38,0xd5] +// CHECK: mrs x20, {{ich_ap0r0_el2|ICH_AP0R0_EL2}} // encoding: [0x14,0xc8,0x3c,0xd5] +// CHECK: mrs x21, {{ich_ap0r1_el2|ICH_AP0R1_EL2}} // encoding: [0x35,0xc8,0x3c,0xd5] +// CHECK: mrs x5, {{ich_ap0r2_el2|ICH_AP0R2_EL2}} // encoding: [0x45,0xc8,0x3c,0xd5] +// CHECK: mrs x4, {{ich_ap0r3_el2|ICH_AP0R3_EL2}} // encoding: [0x64,0xc8,0x3c,0xd5] +// CHECK: mrs x15, {{ich_ap1r0_el2|ICH_AP1R0_EL2}} // encoding: [0x0f,0xc9,0x3c,0xd5] +// CHECK: mrs x12, {{ich_ap1r1_el2|ICH_AP1R1_EL2}} // encoding: [0x2c,0xc9,0x3c,0xd5] +// CHECK: mrs x27, {{ich_ap1r2_el2|ICH_AP1R2_EL2}} // encoding: [0x5b,0xc9,0x3c,0xd5] +// CHECK: mrs x20, {{ich_ap1r3_el2|ICH_AP1R3_EL2}} // encoding: [0x74,0xc9,0x3c,0xd5] +// CHECK: mrs x10, {{ich_hcr_el2|ICH_HCR_EL2}} // encoding: [0x0a,0xcb,0x3c,0xd5] +// CHECK: mrs x27, {{ich_misr_el2|ICH_MISR_EL2}} // encoding: [0x5b,0xcb,0x3c,0xd5] +// CHECK: mrs x6, {{ich_vmcr_el2|ICH_VMCR_EL2}} // encoding: [0xe6,0xcb,0x3c,0xd5] +// CHECK: mrs x19, {{ich_vseir_el2|ICH_VSEIR_EL2}} // encoding: [0x93,0xc9,0x3c,0xd5] +// CHECK: mrs x3, {{ich_lr0_el2|ICH_LR0_EL2}} // encoding: [0x03,0xcc,0x3c,0xd5] +// CHECK: mrs x1, {{ich_lr1_el2|ICH_LR1_EL2}} // encoding: [0x21,0xcc,0x3c,0xd5] +// CHECK: mrs x22, {{ich_lr2_el2|ICH_LR2_EL2}} // encoding: [0x56,0xcc,0x3c,0xd5] +// CHECK: mrs x21, {{ich_lr3_el2|ICH_LR3_EL2}} // encoding: [0x75,0xcc,0x3c,0xd5] +// CHECK: mrs x6, {{ich_lr4_el2|ICH_LR4_EL2}} // encoding: [0x86,0xcc,0x3c,0xd5] +// CHECK: mrs x10, {{ich_lr5_el2|ICH_LR5_EL2}} // encoding: [0xaa,0xcc,0x3c,0xd5] +// CHECK: mrs x11, {{ich_lr6_el2|ICH_LR6_EL2}} // encoding: [0xcb,0xcc,0x3c,0xd5] +// CHECK: mrs x12, {{ich_lr7_el2|ICH_LR7_EL2}} // encoding: [0xec,0xcc,0x3c,0xd5] +// CHECK: mrs x0, {{ich_lr8_el2|ICH_LR8_EL2}} // encoding: [0x00,0xcd,0x3c,0xd5] +// CHECK: mrs x21, {{ich_lr9_el2|ICH_LR9_EL2}} // encoding: [0x35,0xcd,0x3c,0xd5] +// CHECK: mrs x13, {{ich_lr10_el2|ICH_LR10_EL2}} // encoding: [0x4d,0xcd,0x3c,0xd5] +// CHECK: mrs x26, {{ich_lr11_el2|ICH_LR11_EL2}} // encoding: [0x7a,0xcd,0x3c,0xd5] +// CHECK: mrs x1, {{ich_lr12_el2|ICH_LR12_EL2}} // encoding: [0x81,0xcd,0x3c,0xd5] +// CHECK: mrs x8, {{ich_lr13_el2|ICH_LR13_EL2}} // encoding: [0xa8,0xcd,0x3c,0xd5] +// CHECK: mrs x2, {{ich_lr14_el2|ICH_LR14_EL2}} // encoding: [0xc2,0xcd,0x3c,0xd5] +// CHECK: mrs x8, {{ich_lr15_el2|ICH_LR15_EL2}} // encoding: [0xe8,0xcd,0x3c,0xd5] msr icc_eoir1_el1, x27 msr icc_eoir0_el1, x5 @@ -167,57 +167,57 @@ msr ich_lr13_el2, x2 msr ich_lr14_el2, x13 msr ich_lr15_el2, x27 -// CHECK: msr icc_eoir1_el1, x27 // encoding: [0x3b,0xcc,0x18,0xd5] -// CHECK: msr icc_eoir0_el1, x5 // encoding: [0x25,0xc8,0x18,0xd5] -// CHECK: msr icc_dir_el1, x13 // encoding: [0x2d,0xcb,0x18,0xd5] -// CHECK: msr icc_sgi1r_el1, x21 // encoding: [0xb5,0xcb,0x18,0xd5] -// CHECK: msr icc_asgi1r_el1, x25 // encoding: [0xd9,0xcb,0x18,0xd5] -// CHECK: msr icc_sgi0r_el1, x28 // encoding: [0xfc,0xcb,0x18,0xd5] -// CHECK: msr icc_bpr1_el1, x7 // encoding: [0x67,0xcc,0x18,0xd5] -// CHECK: msr icc_bpr0_el1, x9 // encoding: [0x69,0xc8,0x18,0xd5] -// CHECK: msr icc_pmr_el1, x29 // encoding: [0x1d,0x46,0x18,0xd5] -// CHECK: msr icc_ctlr_el1, x24 // encoding: [0x98,0xcc,0x18,0xd5] -// CHECK: msr icc_ctlr_el3, x0 // encoding: [0x80,0xcc,0x1e,0xd5] -// CHECK: msr icc_sre_el1, x2 // encoding: [0xa2,0xcc,0x18,0xd5] -// CHECK: msr icc_sre_el2, x5 // encoding: [0xa5,0xc9,0x1c,0xd5] -// CHECK: msr icc_sre_el3, x10 // encoding: [0xaa,0xcc,0x1e,0xd5] -// CHECK: msr icc_igrpen0_el1, x22 // encoding: [0xd6,0xcc,0x18,0xd5] -// CHECK: msr icc_igrpen1_el1, x11 // encoding: [0xeb,0xcc,0x18,0xd5] -// CHECK: msr icc_igrpen1_el3, x8 // encoding: [0xe8,0xcc,0x1e,0xd5] -// CHECK: msr icc_seien_el1, x4 // encoding: [0x04,0xcd,0x18,0xd5] -// CHECK: msr icc_ap0r0_el1, x27 // encoding: [0x9b,0xc8,0x18,0xd5] -// CHECK: msr icc_ap0r1_el1, x5 // encoding: [0xa5,0xc8,0x18,0xd5] -// CHECK: msr icc_ap0r2_el1, x20 // encoding: [0xd4,0xc8,0x18,0xd5] -// CHECK: msr icc_ap0r3_el1, x0 // encoding: [0xe0,0xc8,0x18,0xd5] -// CHECK: msr icc_ap1r0_el1, x2 // encoding: [0x02,0xc9,0x18,0xd5] -// CHECK: msr icc_ap1r1_el1, x29 // encoding: [0x3d,0xc9,0x18,0xd5] -// CHECK: msr icc_ap1r2_el1, x23 // encoding: [0x57,0xc9,0x18,0xd5] -// CHECK: msr icc_ap1r3_el1, x11 // encoding: [0x6b,0xc9,0x18,0xd5] -// CHECK: msr ich_ap0r0_el2, x2 // encoding: [0x02,0xc8,0x1c,0xd5] -// CHECK: msr ich_ap0r1_el2, x27 // encoding: [0x3b,0xc8,0x1c,0xd5] -// CHECK: msr ich_ap0r2_el2, x7 // encoding: [0x47,0xc8,0x1c,0xd5] -// CHECK: msr ich_ap0r3_el2, x1 // encoding: [0x61,0xc8,0x1c,0xd5] -// CHECK: msr ich_ap1r0_el2, x7 // encoding: [0x07,0xc9,0x1c,0xd5] -// CHECK: msr ich_ap1r1_el2, x12 // encoding: [0x2c,0xc9,0x1c,0xd5] -// CHECK: msr ich_ap1r2_el2, x14 // encoding: [0x4e,0xc9,0x1c,0xd5] -// CHECK: msr ich_ap1r3_el2, x13 // encoding: [0x6d,0xc9,0x1c,0xd5] -// CHECK: msr ich_hcr_el2, x1 // encoding: [0x01,0xcb,0x1c,0xd5] -// CHECK: msr ich_misr_el2, x10 // encoding: [0x4a,0xcb,0x1c,0xd5] -// CHECK: msr ich_vmcr_el2, x24 // encoding: [0xf8,0xcb,0x1c,0xd5] -// CHECK: msr ich_vseir_el2, x29 // encoding: [0x9d,0xc9,0x1c,0xd5] -// CHECK: msr ich_lr0_el2, x26 // encoding: [0x1a,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr1_el2, x9 // encoding: [0x29,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr2_el2, x18 // encoding: [0x52,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr3_el2, x26 // encoding: [0x7a,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr4_el2, x22 // encoding: [0x96,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr5_el2, x26 // encoding: [0xba,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr6_el2, x27 // encoding: [0xdb,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr7_el2, x8 // encoding: [0xe8,0xcc,0x1c,0xd5] -// CHECK: msr ich_lr8_el2, x17 // encoding: [0x11,0xcd,0x1c,0xd5] -// CHECK: msr ich_lr9_el2, x19 // encoding: [0x33,0xcd,0x1c,0xd5] -// CHECK: msr ich_lr10_el2, x17 // encoding: [0x51,0xcd,0x1c,0xd5] -// CHECK: msr ich_lr11_el2, x5 // encoding: [0x65,0xcd,0x1c,0xd5] -// CHECK: msr ich_lr12_el2, x29 // encoding: [0x9d,0xcd,0x1c,0xd5] -// CHECK: msr ich_lr13_el2, x2 // encoding: [0xa2,0xcd,0x1c,0xd5] -// CHECK: msr ich_lr14_el2, x13 // encoding: [0xcd,0xcd,0x1c,0xd5] -// CHECK: msr ich_lr15_el2, x27 // encoding: [0xfb,0xcd,0x1c,0xd5] +// CHECK: msr {{icc_eoir1_el1|ICC_EOIR1_EL1}}, x27 // encoding: [0x3b,0xcc,0x18,0xd5] +// CHECK: msr {{icc_eoir0_el1|ICC_EOIR0_EL1}}, x5 // encoding: [0x25,0xc8,0x18,0xd5] +// CHECK: msr {{icc_dir_el1|ICC_DIR_EL1}}, x13 // encoding: [0x2d,0xcb,0x18,0xd5] +// CHECK: msr {{icc_sgi1r_el1|ICC_SGI1R_EL1}}, x21 // encoding: [0xb5,0xcb,0x18,0xd5] +// CHECK: msr {{icc_asgi1r_el1|ICC_ASGI1R_EL1}}, x25 // encoding: [0xd9,0xcb,0x18,0xd5] +// CHECK: msr {{icc_sgi0r_el1|ICC_SGI0R_EL1}}, x28 // encoding: [0xfc,0xcb,0x18,0xd5] +// CHECK: msr {{icc_bpr1_el1|ICC_BPR1_EL1}}, x7 // encoding: [0x67,0xcc,0x18,0xd5] +// CHECK: msr {{icc_bpr0_el1|ICC_BPR0_EL1}}, x9 // encoding: [0x69,0xc8,0x18,0xd5] +// CHECK: msr {{icc_pmr_el1|ICC_PMR_EL1}}, x29 // encoding: [0x1d,0x46,0x18,0xd5] +// CHECK: msr {{icc_ctlr_el1|ICC_CTLR_EL1}}, x24 // encoding: [0x98,0xcc,0x18,0xd5] +// CHECK: msr {{icc_ctlr_el3|ICC_CTLR_EL3}}, x0 // encoding: [0x80,0xcc,0x1e,0xd5] +// CHECK: msr {{icc_sre_el1|ICC_SRE_EL1}}, x2 // encoding: [0xa2,0xcc,0x18,0xd5] +// CHECK: msr {{icc_sre_el2|ICC_SRE_EL2}}, x5 // encoding: [0xa5,0xc9,0x1c,0xd5] +// CHECK: msr {{icc_sre_el3|ICC_SRE_EL3}}, x10 // encoding: [0xaa,0xcc,0x1e,0xd5] +// CHECK: msr {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x22 // encoding: [0xd6,0xcc,0x18,0xd5] +// CHECK: msr {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}, x11 // encoding: [0xeb,0xcc,0x18,0xd5] +// CHECK: msr {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}, x8 // encoding: [0xe8,0xcc,0x1e,0xd5] +// CHECK: msr {{icc_seien_el1|ICC_SEIEN_EL1}}, x4 // encoding: [0x04,0xcd,0x18,0xd5] +// CHECK: msr {{icc_ap0r0_el1|ICC_AP0R0_EL1}}, x27 // encoding: [0x9b,0xc8,0x18,0xd5] +// CHECK: msr {{icc_ap0r1_el1|ICC_AP0R1_EL1}}, x5 // encoding: [0xa5,0xc8,0x18,0xd5] +// CHECK: msr {{icc_ap0r2_el1|ICC_AP0R2_EL1}}, x20 // encoding: [0xd4,0xc8,0x18,0xd5] +// CHECK: msr {{icc_ap0r3_el1|ICC_AP0R3_EL1}}, x0 // encoding: [0xe0,0xc8,0x18,0xd5] +// CHECK: msr {{icc_ap1r0_el1|ICC_AP1R0_EL1}}, x2 // encoding: [0x02,0xc9,0x18,0xd5] +// CHECK: msr {{icc_ap1r1_el1|ICC_AP1R1_EL1}}, x29 // encoding: [0x3d,0xc9,0x18,0xd5] +// CHECK: msr {{icc_ap1r2_el1|ICC_AP1R2_EL1}}, x23 // encoding: [0x57,0xc9,0x18,0xd5] +// CHECK: msr {{icc_ap1r3_el1|ICC_AP1R3_EL1}}, x11 // encoding: [0x6b,0xc9,0x18,0xd5] +// CHECK: msr {{ich_ap0r0_el2|ICH_AP0R0_EL2}}, x2 // encoding: [0x02,0xc8,0x1c,0xd5] +// CHECK: msr {{ich_ap0r1_el2|ICH_AP0R1_EL2}}, x27 // encoding: [0x3b,0xc8,0x1c,0xd5] +// CHECK: msr {{ich_ap0r2_el2|ICH_AP0R2_EL2}}, x7 // encoding: [0x47,0xc8,0x1c,0xd5] +// CHECK: msr {{ich_ap0r3_el2|ICH_AP0R3_EL2}}, x1 // encoding: [0x61,0xc8,0x1c,0xd5] +// CHECK: msr {{ich_ap1r0_el2|ICH_AP1R0_EL2}}, x7 // encoding: [0x07,0xc9,0x1c,0xd5] +// CHECK: msr {{ich_ap1r1_el2|ICH_AP1R1_EL2}}, x12 // encoding: [0x2c,0xc9,0x1c,0xd5] +// CHECK: msr {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x14 // encoding: [0x4e,0xc9,0x1c,0xd5] +// CHECK: msr {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x13 // encoding: [0x6d,0xc9,0x1c,0xd5] +// CHECK: msr {{ich_hcr_el2|ICH_HCR_EL2}}, x1 // encoding: [0x01,0xcb,0x1c,0xd5] +// CHECK: msr {{ich_misr_el2|ICH_MISR_EL2}}, x10 // encoding: [0x4a,0xcb,0x1c,0xd5] +// CHECK: msr {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24 // encoding: [0xf8,0xcb,0x1c,0xd5] +// CHECK: msr {{ich_vseir_el2|ICH_VSEIR_EL2}}, x29 // encoding: [0x9d,0xc9,0x1c,0xd5] +// CHECK: msr {{ich_lr0_el2|ICH_LR0_EL2}}, x26 // encoding: [0x1a,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr1_el2|ICH_LR1_EL2}}, x9 // encoding: [0x29,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr2_el2|ICH_LR2_EL2}}, x18 // encoding: [0x52,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr3_el2|ICH_LR3_EL2}}, x26 // encoding: [0x7a,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr4_el2|ICH_LR4_EL2}}, x22 // encoding: [0x96,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr5_el2|ICH_LR5_EL2}}, x26 // encoding: [0xba,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr6_el2|ICH_LR6_EL2}}, x27 // encoding: [0xdb,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr7_el2|ICH_LR7_EL2}}, x8 // encoding: [0xe8,0xcc,0x1c,0xd5] +// CHECK: msr {{ich_lr8_el2|ICH_LR8_EL2}}, x17 // encoding: [0x11,0xcd,0x1c,0xd5] +// CHECK: msr {{ich_lr9_el2|ICH_LR9_EL2}}, x19 // encoding: [0x33,0xcd,0x1c,0xd5] +// CHECK: msr {{ich_lr10_el2|ICH_LR10_EL2}}, x17 // encoding: [0x51,0xcd,0x1c,0xd5] +// CHECK: msr {{ich_lr11_el2|ICH_LR11_EL2}}, x5 // encoding: [0x65,0xcd,0x1c,0xd5] +// CHECK: msr {{ich_lr12_el2|ICH_LR12_EL2}}, x29 // encoding: [0x9d,0xcd,0x1c,0xd5] +// CHECK: msr {{ich_lr13_el2|ICH_LR13_EL2}}, x2 // encoding: [0xa2,0xcd,0x1c,0xd5] +// CHECK: msr {{ich_lr14_el2|ICH_LR14_EL2}}, x13 // encoding: [0xcd,0xcd,0x1c,0xd5] +// CHECK: msr {{ich_lr15_el2|ICH_LR15_EL2}}, x27 // encoding: [0xfb,0xcd,0x1c,0xd5] diff --git a/test/MC/AArch64/lit.local.cfg b/test/MC/AArch64/lit.local.cfg index 75dba81..1be70c0 100644 --- a/test/MC/AArch64/lit.local.cfg +++ b/test/MC/AArch64/lit.local.cfg @@ -1,3 +1,3 @@ targets = set(config.root.targets_to_build.split()) -if not 'AArch64' in targets: - config.unsupported = True
\ No newline at end of file +if 'AArch64' not in targets: + config.unsupported = True diff --git a/test/MC/AArch64/neon-2velem.s b/test/MC/AArch64/neon-2velem.s index cde792a..04841d0 100644 --- a/test/MC/AArch64/neon-2velem.s +++ b/test/MC/AArch64/neon-2velem.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/test/MC/AArch64/neon-3vdiff.s b/test/MC/AArch64/neon-3vdiff.s index 3ff86bf..fc3215b 100644 --- a/test/MC/AArch64/neon-3vdiff.s +++ b/test/MC/AArch64/neon-3vdiff.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+crypto -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/test/MC/AArch64/neon-across.s b/test/MC/AArch64/neon-across.s index 8b1c2d4..60b766d 100644 --- a/test/MC/AArch64/neon-across.s +++ b/test/MC/AArch64/neon-across.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/test/MC/AArch64/neon-compare-instructions.s b/test/MC/AArch64/neon-compare-instructions.s index d4e3ef5..19cfaf1 100644 --- a/test/MC/AArch64/neon-compare-instructions.s +++ b/test/MC/AArch64/neon-compare-instructions.s @@ -255,13 +255,13 @@ cmeq v9.4s, v7.4s, #0 cmeq v3.2d, v31.2d, #0 -// CHECK: cmeq v0.8b, v15.8b, #0x0 // encoding: [0xe0,0x99,0x20,0x0e] -// CHECK: cmeq v1.16b, v31.16b, #0x0 // encoding: [0xe1,0x9b,0x20,0x4e] -// CHECK: cmeq v15.4h, v16.4h, #0x0 // encoding: [0x0f,0x9a,0x60,0x0e] -// CHECK: cmeq v5.8h, v6.8h, #0x0 // encoding: [0xc5,0x98,0x60,0x4e] -// CHECK: cmeq v29.2s, v27.2s, #0x0 // encoding: [0x7d,0x9b,0xa0,0x0e] -// CHECK: cmeq v9.4s, v7.4s, #0x0 // encoding: [0xe9,0x98,0xa0,0x4e] -// CHECK: cmeq v3.2d, v31.2d, #0x0 // encoding: [0xe3,0x9b,0xe0,0x4e] +// CHECK: cmeq v0.8b, v15.8b, #{{0x0|0}} // encoding: [0xe0,0x99,0x20,0x0e] +// CHECK: cmeq v1.16b, v31.16b, #{{0x0|0}} // encoding: [0xe1,0x9b,0x20,0x4e] +// CHECK: cmeq v15.4h, v16.4h, #{{0x0|0}} // encoding: [0x0f,0x9a,0x60,0x0e] +// CHECK: cmeq v5.8h, v6.8h, #{{0x0|0}} // encoding: [0xc5,0x98,0x60,0x4e] +// CHECK: cmeq v29.2s, v27.2s, #{{0x0|0}} // encoding: [0x7d,0x9b,0xa0,0x0e] +// CHECK: cmeq v9.4s, v7.4s, #{{0x0|0}} // encoding: [0xe9,0x98,0xa0,0x4e] +// CHECK: cmeq v3.2d, v31.2d, #{{0x0|0}} // encoding: [0xe3,0x9b,0xe0,0x4e] //---------------------------------------------------------------------- // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer) @@ -274,13 +274,13 @@ cmge v17.4s, v20.4s, #0 cmge v3.2d, v31.2d, #0 -// CHECK: cmge v0.8b, v15.8b, #0x0 // encoding: [0xe0,0x89,0x20,0x2e] -// CHECK: cmge v1.16b, v31.16b, #0x0 // encoding: [0xe1,0x8b,0x20,0x6e] -// CHECK: cmge v15.4h, v16.4h, #0x0 // encoding: [0x0f,0x8a,0x60,0x2e] -// CHECK: cmge v5.8h, v6.8h, #0x0 // encoding: [0xc5,0x88,0x60,0x6e] -// CHECK: cmge v29.2s, v27.2s, #0x0 // encoding: [0x7d,0x8b,0xa0,0x2e] -// CHECK: cmge v17.4s, v20.4s, #0x0 // encoding: [0x91,0x8a,0xa0,0x6e] -// CHECK: cmge v3.2d, v31.2d, #0x0 // encoding: [0xe3,0x8b,0xe0,0x6e] +// CHECK: cmge v0.8b, v15.8b, #{{0x0|0}} // encoding: [0xe0,0x89,0x20,0x2e] +// CHECK: cmge v1.16b, v31.16b, #{{0x0|0}} // encoding: [0xe1,0x8b,0x20,0x6e] +// CHECK: cmge v15.4h, v16.4h, #{{0x0|0}} // encoding: [0x0f,0x8a,0x60,0x2e] +// CHECK: cmge v5.8h, v6.8h, #{{0x0|0}} // encoding: [0xc5,0x88,0x60,0x6e] +// CHECK: cmge v29.2s, v27.2s, #{{0x0|0}} // encoding: [0x7d,0x8b,0xa0,0x2e] +// CHECK: cmge v17.4s, v20.4s, #{{0x0|0}} // encoding: [0x91,0x8a,0xa0,0x6e] +// CHECK: cmge v3.2d, v31.2d, #{{0x0|0}} // encoding: [0xe3,0x8b,0xe0,0x6e] //---------------------------------------------------------------------- // Vector Compare Mask Greater Than Zero (Signed Integer) @@ -294,13 +294,13 @@ cmgt v9.4s, v7.4s, #0 cmgt v3.2d, v31.2d, #0 -// CHECK: cmgt v0.8b, v15.8b, #0x0 // encoding: [0xe0,0x89,0x20,0x0e] -// CHECK: cmgt v1.16b, v31.16b, #0x0 // encoding: [0xe1,0x8b,0x20,0x4e] -// CHECK: cmgt v15.4h, v16.4h, #0x0 // encoding: [0x0f,0x8a,0x60,0x0e] -// CHECK: cmgt v5.8h, v6.8h, #0x0 // encoding: [0xc5,0x88,0x60,0x4e] -// CHECK: cmgt v29.2s, v27.2s, #0x0 // encoding: [0x7d,0x8b,0xa0,0x0e] -// CHECK: cmgt v9.4s, v7.4s, #0x0 // encoding: [0xe9,0x88,0xa0,0x4e] -// CHECK: cmgt v3.2d, v31.2d, #0x0 // encoding: [0xe3,0x8b,0xe0,0x4e] +// CHECK: cmgt v0.8b, v15.8b, #{{0x0|0}} // encoding: [0xe0,0x89,0x20,0x0e] +// CHECK: cmgt v1.16b, v31.16b, #{{0x0|0}} // encoding: [0xe1,0x8b,0x20,0x4e] +// CHECK: cmgt v15.4h, v16.4h, #{{0x0|0}} // encoding: [0x0f,0x8a,0x60,0x0e] +// CHECK: cmgt v5.8h, v6.8h, #{{0x0|0}} // encoding: [0xc5,0x88,0x60,0x4e] +// CHECK: cmgt v29.2s, v27.2s, #{{0x0|0}} // encoding: [0x7d,0x8b,0xa0,0x0e] +// CHECK: cmgt v9.4s, v7.4s, #{{0x0|0}} // encoding: [0xe9,0x88,0xa0,0x4e] +// CHECK: cmgt v3.2d, v31.2d, #{{0x0|0}} // encoding: [0xe3,0x8b,0xe0,0x4e] //---------------------------------------------------------------------- // Vector Compare Mask Less Than or Equal To Zero (Signed Integer) @@ -313,13 +313,13 @@ cmle v9.4s, v7.4s, #0 cmle v3.2d, v31.2d, #0 -// CHECK: cmle v0.8b, v15.8b, #0x0 // encoding: [0xe0,0x99,0x20,0x2e] -// CHECK: cmle v1.16b, v31.16b, #0x0 // encoding: [0xe1,0x9b,0x20,0x6e] -// CHECK: cmle v15.4h, v16.4h, #0x0 // encoding: [0x0f,0x9a,0x60,0x2e] -// CHECK: cmle v5.8h, v6.8h, #0x0 // encoding: [0xc5,0x98,0x60,0x6e] -// CHECK: cmle v29.2s, v27.2s, #0x0 // encoding: [0x7d,0x9b,0xa0,0x2e] -// CHECK: cmle v9.4s, v7.4s, #0x0 // encoding: [0xe9,0x98,0xa0,0x6e] -// CHECK: cmle v3.2d, v31.2d, #0x0 // encoding: [0xe3,0x9b,0xe0,0x6e] +// CHECK: cmle v0.8b, v15.8b, #{{0x0|0}} // encoding: [0xe0,0x99,0x20,0x2e] +// CHECK: cmle v1.16b, v31.16b, #{{0x0|0}} // encoding: [0xe1,0x9b,0x20,0x6e] +// CHECK: cmle v15.4h, v16.4h, #{{0x0|0}} // encoding: [0x0f,0x9a,0x60,0x2e] +// CHECK: cmle v5.8h, v6.8h, #{{0x0|0}} // encoding: [0xc5,0x98,0x60,0x6e] +// CHECK: cmle v29.2s, v27.2s, #{{0x0|0}} // encoding: [0x7d,0x9b,0xa0,0x2e] +// CHECK: cmle v9.4s, v7.4s, #{{0x0|0}} // encoding: [0xe9,0x98,0xa0,0x6e] +// CHECK: cmle v3.2d, v31.2d, #{{0x0|0}} // encoding: [0xe3,0x9b,0xe0,0x6e] //---------------------------------------------------------------------- // Vector Compare Mask Less Than Zero (Signed Integer) @@ -332,13 +332,13 @@ cmlt v9.4s, v7.4s, #0 cmlt v3.2d, v31.2d, #0 -// CHECK: cmlt v0.8b, v15.8b, #0x0 // encoding: [0xe0,0xa9,0x20,0x0e] -// CHECK: cmlt v1.16b, v31.16b, #0x0 // encoding: [0xe1,0xab,0x20,0x4e] -// CHECK: cmlt v15.4h, v16.4h, #0x0 // encoding: [0x0f,0xaa,0x60,0x0e] -// CHECK: cmlt v5.8h, v6.8h, #0x0 // encoding: [0xc5,0xa8,0x60,0x4e] -// CHECK: cmlt v29.2s, v27.2s, #0x0 // encoding: [0x7d,0xab,0xa0,0x0e] -// CHECK: cmlt v9.4s, v7.4s, #0x0 // encoding: [0xe9,0xa8,0xa0,0x4e] -// CHECK: cmlt v3.2d, v31.2d, #0x0 // encoding: [0xe3,0xab,0xe0,0x4e] +// CHECK: cmlt v0.8b, v15.8b, #{{0x0|0}} // encoding: [0xe0,0xa9,0x20,0x0e] +// CHECK: cmlt v1.16b, v31.16b, #{{0x0|0}} // encoding: [0xe1,0xab,0x20,0x4e] +// CHECK: cmlt v15.4h, v16.4h, #{{0x0|0}} // encoding: [0x0f,0xaa,0x60,0x0e] +// CHECK: cmlt v5.8h, v6.8h, #{{0x0|0}} // encoding: [0xc5,0xa8,0x60,0x4e] +// CHECK: cmlt v29.2s, v27.2s, #{{0x0|0}} // encoding: [0x7d,0xab,0xa0,0x0e] +// CHECK: cmlt v9.4s, v7.4s, #{{0x0|0}} // encoding: [0xe9,0xa8,0xa0,0x4e] +// CHECK: cmlt v3.2d, v31.2d, #{{0x0|0}} // encoding: [0xe3,0xab,0xe0,0x4e] //---------------------------------------------------------------------- // Vector Compare Mask Equal to Zero (Floating Point) diff --git a/test/MC/AArch64/neon-crypto.s b/test/MC/AArch64/neon-crypto.s index 2952dd5..ed1bf88 100644 --- a/test/MC/AArch64/neon-crypto.s +++ b/test/MC/AArch64/neon-crypto.s @@ -1,5 +1,5 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -mattr=+crypto -show-encoding < %s | FileCheck %s -// RUN: not llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s 2>&1 | FileCheck -check-prefix=CHECK-NO-CRYPTO %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -mattr=+crypto -show-encoding < %s | FileCheck %s +// RUN: not llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s 2>&1 | FileCheck -check-prefix=CHECK-NO-CRYPTO-ARM64 %s // Check that the assembler can handle the documented syntax for AArch64 @@ -13,6 +13,7 @@ aesimc v0.16b, v1.16b // CHECK-NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +// CHECK-NO-CRYPTO-ARM64: error: instruction requires: crypto // CHECK: aese v0.16b, v1.16b // encoding: [0x20,0x48,0x28,0x4e] // CHECK: aesd v0.16b, v1.16b // encoding: [0x20,0x58,0x28,0x4e] // CHECK: aesmc v0.16b, v1.16b // encoding: [0x20,0x68,0x28,0x4e] diff --git a/test/MC/AArch64/neon-diagnostics.s b/test/MC/AArch64/neon-diagnostics.s index aa08857..fa1f3ca 100644 --- a/test/MC/AArch64/neon-diagnostics.s +++ b/test/MC/AArch64/neon-diagnostics.s @@ -587,10 +587,11 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmgt v0.2d, v31.2s, v16.2s // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected floating-point constant #0.0 or invalid register type + +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmgt v4.4s, v7.4s, v15.4h // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected floating-point constant #0.0 or invalid register type +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmlt v29.2d, v5.2d, v2.16b // CHECK-ERROR: ^ @@ -680,12 +681,15 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmeq v0.16b, v1.16b, #0.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate + + +// CHECK-ERROR: error: expected floating-point constant #0.0 // CHECK-ERROR: fcmeq v0.8b, v1.4h, #1.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmeq v0.8b, v1.4h, #1 // CHECK-ERROR: ^ + //---------------------------------------------------------------------- // Vector Compare Mask Greater Than or Equal to Zero (Floating Point) //---------------------------------------------------------------------- @@ -702,12 +706,15 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmge v3.8b, v8.2s, #0.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate + + +// CHECK-ERROR: error: expected floating-point constant #0.0 // CHECK-ERROR: fcmle v17.8h, v15.2d, #-1.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmle v17.8h, v15.2d, #2 // CHECK-ERROR: ^ + //---------------------------------------------------------------------- // Vector Compare Mask Greater Than Zero (Floating Point) //---------------------------------------------------------------------- @@ -723,10 +730,12 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmgt v4.4s, v7.4h, #0.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate + + +// CHECK-ERROR: error: expected floating-point constant #0.0 // CHECK-ERROR: fcmlt v29.2d, v5.2d, #255.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmlt v29.2d, v5.2d, #255 // CHECK-ERROR: ^ @@ -745,10 +754,12 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmge v3.8b, v8.2s, #0.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate + + +// CHECK-ERROR: error: expected floating-point constant #0.0 // CHECK-ERROR: fcmle v17.2d, v15.2d, #15.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmle v17.2d, v15.2d, #15 // CHECK-ERROR: ^ @@ -767,10 +778,12 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmgt v4.4s, v7.4h, #0.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate + + +// CHECK-ERROR: error: expected floating-point constant #0.0 // CHECK-ERROR: fcmlt v29.2d, v5.2d, #16.0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: only #0.0 is acceptable as immediate +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcmlt v29.2d, v5.2d, #2 // CHECK-ERROR: ^ @@ -1285,22 +1298,24 @@ shl v0.4s, v21.4s, #32 shl v0.2d, v1.2d, #64 -// CHECK-ERROR: error: expected comma before next operand + +// CHECK-ERROR: error: unexpected token in argument list // CHECK-ERROR: shl v0.4s, v15,2s, #3 // CHECK-ERROR: ^ + // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: shl v0.2d, v17.4s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: shl v0.8b, v31.8b, #-1 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: shl v0.8b, v31.8b, #8 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: shl v0.4s, v21.4s, #32 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: shl v0.2d, v1.2d, #64 // CHECK-ERROR: ^ @@ -1334,25 +1349,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ushll2 v1.4s, v25.4s, #7 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sshll v0.8h, v1.8b, #-1 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sshll v0.8h, v1.8b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: ushll v0.4s, v1.4h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: ushll v0.2d, v1.2s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sshll2 v0.8h, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: sshll2 v0.4s, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: ushll2 v0.2d, v1.4s, #33 // CHECK-ERROR: ^ @@ -1377,16 +1392,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sshr v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sshr v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sshr v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sshr v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: sshr v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1410,16 +1425,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ushr v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: ushr v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: ushr v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: ushr v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ushr v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1443,16 +1458,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ssra v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: ssra v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: ssra v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: ssra v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ssra v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1476,16 +1491,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: usra v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: usra v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: usra v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: usra v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: usra v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1509,16 +1524,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: srshr v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: srshr v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: srshr v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: srshr v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: srshr v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1542,16 +1557,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: urshr v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: urshr v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: urshr v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: urshr v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: urshr v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1575,16 +1590,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: srsra v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: srsra v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: srsra v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: srsra v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: srsra v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1608,16 +1623,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ursra v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: ursra v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: ursra v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: ursra v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ursra v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1641,16 +1656,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sri v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sri v0.16b, v1.16b, #9 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sri v0.8h, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sri v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: sri v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -1674,16 +1689,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sli v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sli v0.16b, v1.16b, #8 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: sli v0.8h, v1.8h, #16 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: sli v0.4s, v1.4s, #32 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: sli v0.2d, v1.2d, #64 // CHECK-ERROR: ^ @@ -1707,16 +1722,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqshlu v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sqshlu v0.16b, v1.16b, #8 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: sqshlu v0.8h, v1.8h, #16 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: sqshlu v0.4s, v1.4s, #32 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: sqshlu v0.2d, v1.2d, #64 // CHECK-ERROR: ^ @@ -1740,16 +1755,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqshl v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sqshl v0.16b, v1.16b, #8 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: sqshl v0.8h, v1.8h, #16 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: sqshl v0.4s, v1.4s, #32 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: sqshl v0.2d, v1.2d, #64 // CHECK-ERROR: ^ @@ -1773,16 +1788,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: uqshl v0.2s, v1.2d, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: uqshl v0.16b, v1.16b, #8 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: uqshl v0.8h, v1.8h, #16 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: uqshl v0.4s, v1.4s, #32 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: uqshl v0.2d, v1.2d, #64 // CHECK-ERROR: ^ @@ -1805,13 +1820,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: shrn v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: shrn2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: shrn2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: shrn2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -1834,13 +1849,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqshrun v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqshrun2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqshrun2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqshrun2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -1863,13 +1878,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: rshrn v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: rshrn2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: rshrn2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: rshrn2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -1892,13 +1907,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqrshrun v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqrshrun2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqrshrun2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqrshrun2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -1921,13 +1936,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqshrn v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqshrn2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqshrn2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqshrn2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -1950,13 +1965,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: uqshrn v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: uqshrn2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: uqshrn2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: uqshrn2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -1979,13 +1994,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqrshrn v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqrshrn2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqrshrn2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqrshrn2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -2008,13 +2023,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: uqrshrn v0.2s, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: uqrshrn2 v0.16b, v1.8h, #17 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: uqrshrn2 v0.8h, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: uqrshrn2 v0.4s, v1.2d, #65 // CHECK-ERROR: ^ @@ -2037,13 +2052,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: scvtf v0.2d, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: ucvtf v0.2s, v1.2s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: ucvtf v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ucvtf v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -2066,13 +2081,13 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fcvtzs v0.2d, v1.2s, #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: fcvtzu v0.2s, v1.2s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: fcvtzu v0.4s, v1.4s, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: fcvtzu v0.2d, v1.2d, #65 // CHECK-ERROR: ^ @@ -2616,9 +2631,11 @@ pmull2 v0.4s, v1.8h v2.8h pmull2 v0.2d, v1.4s, v2.4s -// CHECK-ERROR: error: expected comma before next operand + +// CHECK-ERROR: error: unexpected token in argument list // CHECK-ERROR: pmull2 v0.4s, v1.8h v2.8h // CHECK-ERROR: ^ + // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: pmull2 v0.2d, v1.4s, v2.4s // CHECK-ERROR: ^ @@ -2941,19 +2958,19 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: mla v0.2d, v1.2d, v16.d[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mla v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mla v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: mla v0.2h, v1.2h, v2.h[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mla v0.4h, v1.4h, v2.h[8] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mla v0.8h, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -2975,19 +2992,19 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: mls v0.2d, v1.2d, v16.d[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mls v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mls v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: mls v0.2h, v1.2h, v2.h[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mls v0.4h, v1.4h, v2.h[8] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mls v0.8h, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3012,22 +3029,22 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmla v0.8h, v1.8h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v3.4s, v8.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v3.4s, v8.4s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v0.2d, v1.2d, v2.d[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla v0.2d, v1.2d, v22.d[2] // CHECK-ERROR: ^ @@ -3046,29 +3063,29 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmls v0.8h, v1.8h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v3.4s, v8.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v3.4s, v8.4s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v0.2d, v1.2d, v2.d[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmls v0.2d, v1.2d, v22.d[2] // CHECK-ERROR: ^ smlal v0.4h, v1.4h, v2.h[2] smlal v0.4s, v1.4h, v2.h[8] smlal v0.4s, v1.4h, v16.h[2] - smlal v0.2s, v1.2s, v2.s[4] + smlal v0.2s, v1.2s, v2.s[1] smlal v0.2d, v1.2s, v2.s[4] smlal v0.2d, v1.2s, v22.s[4] smlal2 v0.4h, v1.8h, v1.h[2] @@ -3081,25 +3098,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlal v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlal v0.4s, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout -// CHECK-ERROR: smlal v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlal v0.2s, v1.2s, v2.s[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlal2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3108,17 +3125,17 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlal2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlal2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ smlsl v0.4h, v1.4h, v2.h[2] smlsl v0.4s, v1.4h, v2.h[8] smlsl v0.4s, v1.4h, v16.h[2] - smlsl v0.2s, v1.2s, v2.s[4] + smlsl v0.2s, v1.2s, v2.s[1] smlsl v0.2d, v1.2s, v2.s[4] smlsl v0.2d, v1.2s, v22.s[4] smlsl2 v0.4h, v1.8h, v1.h[2] @@ -3131,25 +3148,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlsl v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlsl v0.4s, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout -// CHECK-ERROR: smlsl v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlsl v0.2s, v1.2s, v2.s[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlsl2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3158,17 +3175,17 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smlsl2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smlsl2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ umlal v0.4h, v1.4h, v2.h[2] umlal v0.4s, v1.4h, v2.h[8] umlal v0.4s, v1.4h, v16.h[2] - umlal v0.2s, v1.2s, v2.s[4] + umlal v0.2s, v1.2s, v2.s[1] umlal v0.2d, v1.2s, v2.s[4] umlal v0.2d, v1.2s, v22.s[4] umlal2 v0.4h, v1.8h, v1.h[2] @@ -3181,25 +3198,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlal v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlal v0.4s, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout -// CHECK-ERROR: umlal v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlal v0.2s, v1.2s, v2.s[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlal2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3208,17 +3225,17 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlal2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlal2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ umlsl v0.4h, v1.4h, v2.h[2] umlsl v0.4s, v1.4h, v2.h[8] umlsl v0.4s, v1.4h, v16.h[2] - umlsl v0.2s, v1.2s, v2.s[4] + umlsl v0.2s, v1.2s, v2.s[3] umlsl v0.2d, v1.2s, v2.s[4] umlsl v0.2d, v1.2s, v22.s[4] umlsl2 v0.4h, v1.8h, v1.h[2] @@ -3231,25 +3248,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlsl v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlsl v0.4s, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout -// CHECK-ERROR: umlsl v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlsl v0.2s, v1.2s, v2.s[3] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlsl2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3258,17 +3275,17 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umlsl2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umlsl2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ sqdmlal v0.4h, v1.4h, v2.h[2] sqdmlal v0.4s, v1.4h, v2.h[8] sqdmlal v0.4s, v1.4h, v16.h[2] - sqdmlal v0.2s, v1.2s, v2.s[4] + sqdmlal v0.2s, v1.2s, v2.s[3] sqdmlal v0.2d, v1.2s, v2.s[4] sqdmlal v0.2d, v1.2s, v22.s[4] sqdmlal2 v0.4h, v1.8h, v1.h[2] @@ -3281,25 +3298,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal v0.4s, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout -// CHECK-ERROR: sqdmlal v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal v0.2s, v1.2s, v2.s[3] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3308,17 +3325,17 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlal2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ sqdmlsl v0.4h, v1.4h, v2.h[2] sqdmlsl v0.4s, v1.4h, v2.h[8] sqdmlsl v0.4s, v1.4h, v16.h[2] - sqdmlsl v0.2s, v1.2s, v2.s[4] + sqdmlsl v0.2s, v1.2s, v2.s[3] sqdmlsl v0.2d, v1.2s, v2.s[4] sqdmlsl v0.2d, v1.2s, v22.s[4] sqdmlsl2 v0.4h, v1.8h, v1.h[2] @@ -3331,25 +3348,25 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl v0.4s, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout -// CHECK-ERROR: sqdmlsl v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl v0.2s, v1.2s, v2.s[3] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl2 v0.4h, v1.8h, v1.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl2 v0.4s, v1.8h, v1.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3358,10 +3375,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl2 v0.2s, v1.4s, v1.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl2 v0.2d, v1.4s, v1.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3375,28 +3392,28 @@ mul v0.4s, v1.4s, v22.s[4] mul v0.2d, v1.2d, v2.d[1] -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.4h, v1.4h, v2.h[8] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: mul v0.4h, v1.4h, v16.h[8] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.8h, v1.8h, v2.h[8] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: invalid operand for instruction // CHECK-ERROR: mul v0.8h, v1.8h, v16.h[8] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: mul v0.4s, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3414,22 +3431,22 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmul v0.4h, v1.4h, v2.h[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.4s, v1.4s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.2d, v1.2d, v2.d[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul v0.2d, v1.2d, v22.d[2] // CHECK-ERROR: ^ @@ -3444,22 +3461,22 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmulx v0.4h, v1.4h, v2.h[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.4s, v1.4s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.2d, v1.2d, v2.d[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx v0.2d, v1.2d, v22.d[2] // CHECK-ERROR: ^ @@ -3479,7 +3496,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smull v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3488,16 +3505,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smull v0.2s, v1.2s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smull2 v0.4h, v1.8h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull2 v0.4s, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3506,10 +3523,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: smull2 v0.2s, v1.4s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull2 v0.2d, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: smull2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3529,7 +3546,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umull v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3538,16 +3555,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umull v0.2s, v1.2s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umull2 v0.4h, v1.8h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull2 v0.4s, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3556,10 +3573,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: umull2 v0.2s, v1.4s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull2 v0.2d, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: umull2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3579,7 +3596,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull v0.4h, v1.4h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull v0.4s, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3588,16 +3605,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull v0.2s, v1.2s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull v0.2d, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull v0.2d, v1.2s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull2 v0.4h, v1.8h, v2.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull2 v0.4s, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3606,10 +3623,10 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull2 v0.2s, v1.4s, v2.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull2 v0.2d, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull2 v0.2d, v1.4s, v22.s[4] // CHECK-ERROR: ^ @@ -3623,28 +3640,28 @@ sqdmulh v0.4s, v1.4s, v22.s[4] sqdmulh v0.2d, v1.2d, v22.d[1] -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.4h, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmulh v0.4h, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.8h, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmulh v0.8h, v1.8h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh v0.4s, v1.4s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3661,28 +3678,28 @@ sqrdmulh v0.4s, v1.4s, v22.s[4] sqrdmulh v0.2d, v1.2d, v22.d[1] -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.4h, v1.4h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqrdmulh v0.4h, v1.4h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.8h, v1.8h, v2.h[8] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqrdmulh v0.8h, v1.8h, v16.h[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.2s, v1.2s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.2s, v1.2s, v22.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.4s, v1.4s, v2.s[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh v0.4s, v1.4s, v22.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3900,13 +3917,13 @@ ld1 {v4}, [x0] ld1 {v32.16b}, [x0] ld1 {v15.8h}, [x32] -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: vector register expected // CHECK-ERROR: ld1 {x3}, [x2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld1 {v4}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: vector register expected // CHECK-ERROR: ld1 {v32.16b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3920,13 +3937,13 @@ ld1 {v1.8h-v1.8h}, [x0] ld1 {v15.8h-v17.4h}, [x15] ld1 {v0.8b-v2.8b, [x0] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: ld1 {v0.16b, v2.16b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: ld1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: '{' expected +// CHECK-ERROR: error: unexpected token in argument list // CHECK-ERROR: ld1 v0.8b, v1.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors @@ -3935,7 +3952,7 @@ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: ld1 {v1.8h-v1.8h}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld1 {v15.8h-v17.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: '}' expected @@ -3947,16 +3964,15 @@ ld2 {v15.4h, v16.4h, v17.4h}, [x32] ld2 {v15.8h-v16.4h}, [x15] ld2 {v0.2d-v2.2d}, [x0] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld2 {v15.8h, v16.4h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: ld2 {v0.8b, v2.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld2 {v15.4h, v16.4h, v17.4h}, [x32] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld2 {v15.8h-v16.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3968,16 +3984,16 @@ ld3 {v0.8b, v2.8b, v3.8b}, [x0] ld3 {v15.8h-v17.4h}, [x15] ld3 {v31.4s-v2.4s}, [sp] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld3 {v15.8h, v16.8h, v17.4h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: ld3 {v0.8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld3 {v15.8h-v17.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -3989,16 +4005,16 @@ ld4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] ld4 {v15.8h-v18.4h}, [x15] ld4 {v31.2s-v1.2s}, [x31] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: ld4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: ld4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld4 {v15.8h-v18.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4009,13 +4025,13 @@ st1 {v4}, [x0] st1 {v32.16b}, [x0] st1 {v15.8h}, [x32] -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: vector register expected // CHECK-ERROR: st1 {x3}, [x2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st1 {v4}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: vector register expected // CHECK-ERROR: st1 {v32.16b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4029,13 +4045,13 @@ st1 {v1.8h-v1.8h}, [x0] st1 {v15.8h-v17.4h}, [x15] st1 {v0.8b-v2.8b, [x0] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: st1 {v0.16b, v2.16b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: st1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: '{' expected +// CHECK-ERROR: error: unexpected token in argument list // CHECK-ERROR: st1 v0.8b, v1.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors @@ -4044,7 +4060,7 @@ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: st1 {v1.8h-v1.8h}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st1 {v15.8h-v17.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: '}' expected @@ -4056,16 +4072,16 @@ st2 {v15.4h, v16.4h, v17.4h}, [x30] st2 {v15.8h-v16.4h}, [x15] st2 {v0.2d-v2.2d}, [x0] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st2 {v15.8h, v16.4h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: st2 {v0.8b, v2.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st2 {v15.4h, v16.4h, v17.4h}, [x30] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st2 {v15.8h-v16.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4077,16 +4093,16 @@ st3 {v0.8b, v2.8b, v3.8b}, [x0] st3 {v15.8h-v17.4h}, [x15] st3 {v31.4s-v2.4s}, [sp] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st3 {v15.8h, v16.8h, v17.4h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: st3 {v0.8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st3 {v15.8h-v17.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4098,16 +4114,16 @@ st4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] st4 {v15.8h-v18.4h}, [x15] st4 {v31.2s-v1.2s}, [x31] -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: registers must be sequential // CHECK-ERROR: st4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors // CHECK-ERROR: st4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st4 {v15.8h-v18.4h}, [x15] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4124,7 +4140,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld1 {v0.16b}, [x0], #8 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: invalid vector kind qualifier // CHECK-ERROR: ld1 {v0.8h, v1.16h}, [x0], x1 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4140,7 +4156,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld3 {v5.2s, v6.2s, v7.2s}, [x1], #48 // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1 // CHECK-ERROR: ^ @@ -4150,7 +4166,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st1 {v0.16b}, [x0], #8 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: invalid vector kind qualifier // CHECK-ERROR: st1 {v0.8h, v1.16h}, [x0], x1 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4166,7 +4182,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st3 {v5.2s, v6.2s, v7.2s}, [x1], #48 // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1 // CHECK-ERROR: ^ @@ -4178,16 +4194,16 @@ ld2r {v31.4s, v0.2s}, [sp] ld3r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] ld4r {v31.2s, v0.2s, v1.2d, v2.2s}, [sp] -// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: error: vector register expected // CHECK-ERROR: ld1r {x1}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld2r {v31.4s, v0.2s}, [sp] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld3r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld4r {v31.2s, v0.2s, v1.2d, v2.2s}, [sp] // CHECK-ERROR: ^ @@ -4199,16 +4215,16 @@ ld2 {v15.h, v16.h}[8], [x15] ld3 {v31.s, v0.s, v1.s}[-1], [sp] ld4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] -// CHECK-ERROR:: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: ld1 {v0.b}[16], [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: ld2 {v15.h, v16.h}[8], [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected lane number +// CHECK-ERROR: error: vector lane must be an integer in range // CHECK-ERROR: ld3 {v31.s, v0.s, v1.s}[-1], [sp] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: ld4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] // CHECK-ERROR: ^ @@ -4216,16 +4232,16 @@ st2 {v31.s, v0.s}[3], [8] st3 {v15.h, v16.h, v17.h}[-1], [x15] st4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] -// CHECK-ERROR:: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: st1 {v0.d}[16], [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st2 {v31.s, v0.s}[3], [8] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected lane number +// CHECK-ERROR: error: vector lane must be an integer in range // CHECK-ERROR: st3 {v15.h, v16.h, v17.h}[-1], [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: st4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] // CHECK-ERROR: ^ @@ -4264,7 +4280,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld2 {v15.h, v16.h}[0], [x15], #3 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld3 {v31.s, v0.s, v1.d}[0], [sp], x9 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4298,16 +4314,16 @@ ins v20.s[1], s30 ins v1.d[0], d7 -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: ins v2.b[16], w1 // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: ins v7.h[8], w14 // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: ins v20.s[5], w30 // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: ins v1.d[2], x7 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4334,19 +4350,19 @@ smov x14, v6.d[1] smov x20, v9.d[0] -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR smov w1, v0.b[16] // CHECK-ERROR ^ -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR smov w14, v6.h[8] // CHECK-ERROR ^ -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR smov x1, v0.b[16] // CHECK-ERROR ^ -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR smov x14, v6.h[8] // CHECK-ERROR ^ -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR smov x20, v9.s[5] // CHECK-ERROR ^ // CHECK-ERROR error: invalid operand for instruction @@ -4373,16 +4389,16 @@ umov s20, v9.s[2] umov d7, v18.d[1] -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR umov w1, v0.b[16] // CHECK-ERROR ^ -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR umov w14, v6.h[8] // CHECK-ERROR ^ -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR umov w20, v9.s[5] // CHECK-ERROR ^ -// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR umov x7, v18.d[3] // CHECK-ERROR ^ // CHECK-ERROR error: invalid operand for instruction @@ -4798,7 +4814,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal s17, h27, s12 // CHECK-ERROR: ^ -// CHECK-ERROR: error: too few operands for instruction +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal d19, s24, d12 // CHECK-ERROR: ^ @@ -4812,7 +4828,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl s14, h12, s25 // CHECK-ERROR: ^ -// CHECK-ERROR: error: too few operands for instruction +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl d12, s23, d13 // CHECK-ERROR: ^ @@ -4826,7 +4842,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull s12, h22, s12 // CHECK-ERROR: ^ -// CHECK-ERROR: error: too few operands for instruction +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull d15, s22, d12 // CHECK-ERROR: ^ @@ -4890,7 +4906,7 @@ //---------------------------------------------------------------------- sshr d15, d16, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: sshr d15, d16, #99 // CHECK-ERROR: ^ @@ -4906,7 +4922,7 @@ ushr d10, d17, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ushr d10, d17, #99 // CHECK-ERROR: ^ @@ -4916,7 +4932,7 @@ srshr d19, d18, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: srshr d19, d18, #99 // CHECK-ERROR: ^ @@ -4926,7 +4942,7 @@ urshr d20, d23, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: urshr d20, d23, #99 // CHECK-ERROR: ^ @@ -4936,7 +4952,7 @@ ssra d18, d12, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ssra d18, d12, #99 // CHECK-ERROR: ^ @@ -4946,7 +4962,7 @@ usra d20, d13, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: usra d20, d13, #99 // CHECK-ERROR: ^ @@ -4956,7 +4972,7 @@ srsra d15, d11, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: srsra d15, d11, #99 // CHECK-ERROR: ^ @@ -4966,7 +4982,7 @@ ursra d18, d10, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ursra d18, d10, #99 // CHECK-ERROR: ^ @@ -4976,7 +4992,7 @@ shl d7, d10, #99 -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: shl d7, d10, #99 // CHECK-ERROR: ^ @@ -4995,16 +5011,16 @@ sqshl s14, s17, #99 sqshl d15, d16, #99 -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sqshl b11, b19, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: sqshl h13, h18, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: sqshl s14, s17, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: sqshl d15, d16, #99 // CHECK-ERROR: ^ @@ -5017,16 +5033,16 @@ uqshl s14, s19, #99 uqshl d15, d12, #99 -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: uqshl b18, b15, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: uqshl h11, h18, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: uqshl s14, s19, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: uqshl d15, d12, #99 // CHECK-ERROR: ^ @@ -5039,16 +5055,16 @@ sqshlu s16, s14, #99 sqshlu d11, d13, #99 -// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 7] // CHECK-ERROR: sqshlu b15, b18, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 15] // CHECK-ERROR: sqshlu h19, h17, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 31] // CHECK-ERROR: sqshlu s16, s14, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: sqshlu d11, d13, #99 // CHECK-ERROR: ^ @@ -5058,7 +5074,7 @@ sri d10, d12, #99 -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: sri d10, d12, #99 // CHECK-ERROR: ^ @@ -5068,7 +5084,7 @@ sli d10, d14, #99 -// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [0, 63] // CHECK-ERROR: sli d10, d14, #99 // CHECK-ERROR: ^ @@ -5080,13 +5096,13 @@ sqshrn h17, s10, #99 sqshrn s18, d10, #99 -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqshrn b10, h15, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqshrn h17, s10, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqshrn s18, d10, #99 // CHECK-ERROR: ^ @@ -5098,13 +5114,13 @@ uqshrn h10, s14, #99 uqshrn s10, d12, #99 -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: uqshrn b12, h10, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: uqshrn h10, s14, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: uqshrn s10, d12, #99 // CHECK-ERROR: ^ @@ -5116,13 +5132,13 @@ sqrshrn h15, s10, #99 sqrshrn s15, d12, #99 -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqrshrn b10, h13, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqrshrn h15, s10, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqrshrn s15, d12, #99 // CHECK-ERROR: ^ @@ -5134,13 +5150,13 @@ uqrshrn h12, s10, #99 uqrshrn s10, d10, #99 -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: uqrshrn b10, h12, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: uqrshrn h12, s10, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: uqrshrn s10, d10, #99 // CHECK-ERROR: ^ @@ -5152,13 +5168,13 @@ sqshrun h20, s14, #99 sqshrun s10, d15, #99 -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqshrun b15, h10, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqshrun h20, s14, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqshrun s10, d15, #99 // CHECK-ERROR: ^ @@ -5170,13 +5186,13 @@ sqrshrun h10, s13, #99 sqrshrun s22, d16, #99 -// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 8] // CHECK-ERROR: sqrshrun b17, h10, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 16] // CHECK-ERROR: sqrshrun h10, s13, #99 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: sqrshrun s22, d16, #99 // CHECK-ERROR: ^ @@ -5189,13 +5205,13 @@ scvtf d21, d12, #65 scvtf d21, s12, #31 -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: scvtf s22, s13, #0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: scvtf s22, s13, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: scvtf d21, d12, #65 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -5210,10 +5226,10 @@ ucvtf d21, d14, #65 ucvtf d21, s14, #64 -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: ucvtf s22, s13, #34 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: ucvtf d21, d14, #65 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -6262,10 +6278,10 @@ fcvtzs d21, d12, #65 fcvtzs s21, d12, #1 -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: fcvtzs s21, s12, #0 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: fcvtzs d21, d12, #65 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -6280,10 +6296,10 @@ fcvtzu d21, d12, #0 fcvtzu s21, d12, #1 -// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 32] // CHECK-ERROR: fcvtzu s21, s12, #33 // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: error: {{expected|immediate must be an}} integer in range [1, 64] // CHECK-ERROR: fcvtzu d21, d12, #0 // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -6868,7 +6884,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmul h0, h1, v1.s[0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmul s2, s29, v10.s[4] // CHECK-ERROR: ^ @@ -6887,7 +6903,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmulx h0, h1, v1.d[0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmulx d2, d29, v10.d[3] // CHECK-ERROR: ^ @@ -6906,7 +6922,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmla d30, s11, v1.d[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: fmla s16, s22, v16.s[5] // CHECK-ERROR: ^ @@ -6925,7 +6941,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: fmls h7, h17, v26.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: expected lane number +// CHECK-ERROR: error: vector lane must be an integer in range [0, 1] // CHECK-ERROR: fmls d16, d22, v16.d[-1] // CHECK-ERROR: ^ @@ -6937,7 +6953,7 @@ sqdmlal s0, h0, v0.s[0] sqdmlal s8, s9, v14.s[1] // invalid lane - sqdmlal s4, s5, v1.s[5] + sqdmlal d4, s5, v1.s[5] // invalid vector index sqdmlal s0, h0, v17.h[0] @@ -6947,8 +6963,8 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal s8, s9, v14.s[1] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout -// CHECK-ERROR: sqdmlal s4, s5, v1.s[5] +// CHECK-ERROR: vector lane must be an integer in range +// CHECK-ERROR: sqdmlal d4, s5, v1.s[5] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlal s0, h0, v17.h[0] @@ -6972,7 +6988,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmlsl d1, h1, v13.s[0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmlsl d1, s1, v13.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -6999,7 +7015,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmull s1, s1, v4.s[0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmull s12, h17, v9.h[9] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -7024,7 +7040,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqdmulh s25, s26, v27.h[3] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqdmulh s25, s26, v27.s[4] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -7049,7 +7065,7 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: sqrdmulh s5, h6, v7.s[2] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: sqrdmulh h31, h30, v14.h[9] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -7081,16 +7097,16 @@ // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: dup d0, v17.s[3] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: dup d0, v17.d[4] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: dup s0, v1.s[7] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: dup h0, v31.h[16] // CHECK-ERROR: ^ -// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: vector lane must be an integer in range // CHECK-ERROR: dup b1, v3.b[16] // CHECK-ERROR: ^ diff --git a/test/MC/AArch64/neon-extract.s b/test/MC/AArch64/neon-extract.s index 2d58a75..1daa46d 100644 --- a/test/MC/AArch64/neon-extract.s +++ b/test/MC/AArch64/neon-extract.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 @@ -9,5 +9,5 @@ ext v0.8b, v1.8b, v2.8b, #0x3 ext v0.16b, v1.16b, v2.16b, #0x3 -// CHECK: ext v0.8b, v1.8b, v2.8b, #0x3 // encoding: [0x20,0x18,0x02,0x2e] -// CHECK: ext v0.16b, v1.16b, v2.16b, #0x3 // encoding: [0x20,0x18,0x02,0x6e] +// CHECK: ext v0.8b, v1.8b, v2.8b, #{{0x3|3}} // encoding: [0x20,0x18,0x02,0x2e] +// CHECK: ext v0.16b, v1.16b, v2.16b, #{{0x3|3}} // encoding: [0x20,0x18,0x02,0x6e] diff --git a/test/MC/AArch64/neon-mov.s b/test/MC/AArch64/neon-mov.s index c2ca803..567a5ec 100644 --- a/test/MC/AArch64/neon-mov.s +++ b/test/MC/AArch64/neon-mov.s @@ -20,19 +20,19 @@ movi v0.8h, #1 movi v0.8h, #1, lsl #8 -// CHECK: movi v0.2s, #0x1 // encoding: [0x20,0x04,0x00,0x0f] -// CHECK: movi v1.2s, #0x0 // encoding: [0x01,0x04,0x00,0x0f] -// CHECK: movi v15.2s, #0x1, lsl #8 // encoding: [0x2f,0x24,0x00,0x0f] -// CHECK: movi v16.2s, #0x1, lsl #16 // encoding: [0x30,0x44,0x00,0x0f] -// CHECK: movi v31.2s, #0x1, lsl #24 // encoding: [0x3f,0x64,0x00,0x0f] -// CHECK: movi v0.4s, #0x1 // encoding: [0x20,0x04,0x00,0x4f] -// CHECK: movi v0.4s, #0x1, lsl #8 // encoding: [0x20,0x24,0x00,0x4f] -// CHECK: movi v0.4s, #0x1, lsl #16 // encoding: [0x20,0x44,0x00,0x4f] -// CHECK: movi v0.4s, #0x1, lsl #24 // encoding: [0x20,0x64,0x00,0x4f] -// CHECK: movi v0.4h, #0x1 // encoding: [0x20,0x84,0x00,0x0f] -// CHECK: movi v0.4h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x0f] -// CHECK: movi v0.8h, #0x1 // encoding: [0x20,0x84,0x00,0x4f] -// CHECK: movi v0.8h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x4f] +// CHECK: movi v0.2s, #{{0x1|1}} // encoding: [0x20,0x04,0x00,0x0f] +// CHECK: movi v1.2s, #{{0x0|0}} // encoding: [0x01,0x04,0x00,0x0f] +// CHECK: movi v15.2s, #{{0x1|1}}, lsl #8 // encoding: [0x2f,0x24,0x00,0x0f] +// CHECK: movi v16.2s, #{{0x1|1}}, lsl #16 // encoding: [0x30,0x44,0x00,0x0f] +// CHECK: movi v31.2s, #{{0x1|1}}, lsl #24 // encoding: [0x3f,0x64,0x00,0x0f] +// CHECK: movi v0.4s, #{{0x1|1}} // encoding: [0x20,0x04,0x00,0x4f] +// CHECK: movi v0.4s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x24,0x00,0x4f] +// CHECK: movi v0.4s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x44,0x00,0x4f] +// CHECK: movi v0.4s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x64,0x00,0x4f] +// CHECK: movi v0.4h, #{{0x1|1}} // encoding: [0x20,0x84,0x00,0x0f] +// CHECK: movi v0.4h, #{{0x1|1}}, lsl #8 // encoding: [0x20,0xa4,0x00,0x0f] +// CHECK: movi v0.8h, #{{0x1|1}} // encoding: [0x20,0x84,0x00,0x4f] +// CHECK: movi v0.8h, #{{0x1|1}}, lsl #8 // encoding: [0x20,0xa4,0x00,0x4f] //---------------------------------------------------------------------- // Vector Move Inverted Immediate Shifted @@ -51,19 +51,19 @@ mvni v0.8h, #1 mvni v0.8h, #1, lsl #8 -// CHECK: mvni v0.2s, #0x1 // encoding: [0x20,0x04,0x00,0x2f] -// CHECK: mvni v1.2s, #0x0 // encoding: [0x01,0x04,0x00,0x2f] -// CHECK: mvni v0.2s, #0x1, lsl #8 // encoding: [0x20,0x24,0x00,0x2f] -// CHECK: mvni v0.2s, #0x1, lsl #16 // encoding: [0x20,0x44,0x00,0x2f] -// CHECK: mvni v0.2s, #0x1, lsl #24 // encoding: [0x20,0x64,0x00,0x2f] -// CHECK: mvni v0.4s, #0x1 // encoding: [0x20,0x04,0x00,0x6f] -// CHECK: mvni v15.4s, #0x1, lsl #8 // encoding: [0x2f,0x24,0x00,0x6f] -// CHECK: mvni v16.4s, #0x1, lsl #16 // encoding: [0x30,0x44,0x00,0x6f] -// CHECK: mvni v31.4s, #0x1, lsl #24 // encoding: [0x3f,0x64,0x00,0x6f] -// CHECK: mvni v0.4h, #0x1 // encoding: [0x20,0x84,0x00,0x2f] -// CHECK: mvni v0.4h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x2f] -// CHECK: mvni v0.8h, #0x1 // encoding: [0x20,0x84,0x00,0x6f] -// CHECK: mvni v0.8h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x6f] +// CHECK: mvni v0.2s, #{{0x1|1}} // encoding: [0x20,0x04,0x00,0x2f] +// CHECK: mvni v1.2s, #{{0x0|0}} // encoding: [0x01,0x04,0x00,0x2f] +// CHECK: mvni v0.2s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x24,0x00,0x2f] +// CHECK: mvni v0.2s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x44,0x00,0x2f] +// CHECK: mvni v0.2s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x64,0x00,0x2f] +// CHECK: mvni v0.4s, #{{0x1|1}} // encoding: [0x20,0x04,0x00,0x6f] +// CHECK: mvni v15.4s, #{{0x1|1}}, lsl #8 // encoding: [0x2f,0x24,0x00,0x6f] +// CHECK: mvni v16.4s, #{{0x1|1}}, lsl #16 // encoding: [0x30,0x44,0x00,0x6f] +// CHECK: mvni v31.4s, #{{0x1|1}}, lsl #24 // encoding: [0x3f,0x64,0x00,0x6f] +// CHECK: mvni v0.4h, #{{0x1|1}} // encoding: [0x20,0x84,0x00,0x2f] +// CHECK: mvni v0.4h, #{{0x1|1}}, lsl #8 // encoding: [0x20,0xa4,0x00,0x2f] +// CHECK: mvni v0.8h, #{{0x1|1}} // encoding: [0x20,0x84,0x00,0x6f] +// CHECK: mvni v0.8h, #{{0x1|1}}, lsl #8 // encoding: [0x20,0xa4,0x00,0x6f] //---------------------------------------------------------------------- // Vector Bitwise Bit Clear (AND NOT) - immediate @@ -82,19 +82,19 @@ bic v0.8h, #1 bic v31.8h, #1, lsl #8 -// CHECK: bic v0.2s, #0x1 // encoding: [0x20,0x14,0x00,0x2f] -// CHECK: bic v1.2s, #0x0 // encoding: [0x01,0x14,0x00,0x2f] -// CHECK: bic v0.2s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x2f] -// CHECK: bic v0.2s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x2f] -// CHECK: bic v0.2s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x2f] -// CHECK: bic v0.4s, #0x1 // encoding: [0x20,0x14,0x00,0x6f] -// CHECK: bic v0.4s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x6f] -// CHECK: bic v0.4s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x6f] -// CHECK: bic v0.4s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x6f] -// CHECK: bic v15.4h, #0x1 // encoding: [0x2f,0x94,0x00,0x2f] -// CHECK: bic v16.4h, #0x1, lsl #8 // encoding: [0x30,0xb4,0x00,0x2f] -// CHECK: bic v0.8h, #0x1 // encoding: [0x20,0x94,0x00,0x6f] -// CHECK: bic v31.8h, #0x1, lsl #8 // encoding: [0x3f,0xb4,0x00,0x6f] +// CHECK: bic v0.2s, #{{0x1|1}} // encoding: [0x20,0x14,0x00,0x2f] +// CHECK: bic v1.2s, #{{0x0|0}} // encoding: [0x01,0x14,0x00,0x2f] +// CHECK: bic v0.2s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x34,0x00,0x2f] +// CHECK: bic v0.2s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x54,0x00,0x2f] +// CHECK: bic v0.2s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x74,0x00,0x2f] +// CHECK: bic v0.4s, #{{0x1|1}} // encoding: [0x20,0x14,0x00,0x6f] +// CHECK: bic v0.4s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x34,0x00,0x6f] +// CHECK: bic v0.4s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x54,0x00,0x6f] +// CHECK: bic v0.4s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x74,0x00,0x6f] +// CHECK: bic v15.4h, #{{0x1|1}} // encoding: [0x2f,0x94,0x00,0x2f] +// CHECK: bic v16.4h, #{{0x1|1}}, lsl #8 // encoding: [0x30,0xb4,0x00,0x2f] +// CHECK: bic v0.8h, #{{0x1|1}} // encoding: [0x20,0x94,0x00,0x6f] +// CHECK: bic v31.8h, #{{0x1|1}}, lsl #8 // encoding: [0x3f,0xb4,0x00,0x6f] //---------------------------------------------------------------------- // Vector Bitwise OR - immedidate @@ -113,19 +113,19 @@ orr v0.8h, #1 orr v16.8h, #1, lsl #8 -// CHECK: orr v0.2s, #0x1 // encoding: [0x20,0x14,0x00,0x0f] -// CHECK: orr v1.2s, #0x0 // encoding: [0x01,0x14,0x00,0x0f] -// CHECK: orr v0.2s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x0f] -// CHECK: orr v0.2s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x0f] -// CHECK: orr v0.2s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x0f] -// CHECK: orr v0.4s, #0x1 // encoding: [0x20,0x14,0x00,0x4f] -// CHECK: orr v0.4s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x4f] -// CHECK: orr v0.4s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x4f] -// CHECK: orr v0.4s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x4f] -// CHECK: orr v31.4h, #0x1 // encoding: [0x3f,0x94,0x00,0x0f] -// CHECK: orr v15.4h, #0x1, lsl #8 // encoding: [0x2f,0xb4,0x00,0x0f] -// CHECK: orr v0.8h, #0x1 // encoding: [0x20,0x94,0x00,0x4f] -// CHECK: orr v16.8h, #0x1, lsl #8 // encoding: [0x30,0xb4,0x00,0x4f] +// CHECK: orr v0.2s, #{{0x1|1}} // encoding: [0x20,0x14,0x00,0x0f] +// CHECK: orr v1.2s, #{{0x0|0}} // encoding: [0x01,0x14,0x00,0x0f] +// CHECK: orr v0.2s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x34,0x00,0x0f] +// CHECK: orr v0.2s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x54,0x00,0x0f] +// CHECK: orr v0.2s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x74,0x00,0x0f] +// CHECK: orr v0.4s, #{{0x1|1}} // encoding: [0x20,0x14,0x00,0x4f] +// CHECK: orr v0.4s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x34,0x00,0x4f] +// CHECK: orr v0.4s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x54,0x00,0x4f] +// CHECK: orr v0.4s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x74,0x00,0x4f] +// CHECK: orr v31.4h, #{{0x1|1}} // encoding: [0x3f,0x94,0x00,0x0f] +// CHECK: orr v15.4h, #{{0x1|1}}, lsl #8 // encoding: [0x2f,0xb4,0x00,0x0f] +// CHECK: orr v0.8h, #{{0x1|1}} // encoding: [0x20,0x94,0x00,0x4f] +// CHECK: orr v16.8h, #{{0x1|1}}, lsl #8 // encoding: [0x30,0xb4,0x00,0x4f] //---------------------------------------------------------------------- // Vector Move Immediate Masked @@ -135,10 +135,10 @@ movi v0.4s, #1, msl #8 movi v31.4s, #1, msl #16 -// CHECK: movi v0.2s, #0x1, msl #8 // encoding: [0x20,0xc4,0x00,0x0f] -// CHECK: movi v1.2s, #0x1, msl #16 // encoding: [0x21,0xd4,0x00,0x0f] -// CHECK: movi v0.4s, #0x1, msl #8 // encoding: [0x20,0xc4,0x00,0x4f] -// CHECK: movi v31.4s, #0x1, msl #16 // encoding: [0x3f,0xd4,0x00,0x4f] +// CHECK: movi v0.2s, #{{0x1|1}}, msl #8 // encoding: [0x20,0xc4,0x00,0x0f] +// CHECK: movi v1.2s, #{{0x1|1}}, msl #16 // encoding: [0x21,0xd4,0x00,0x0f] +// CHECK: movi v0.4s, #{{0x1|1}}, msl #8 // encoding: [0x20,0xc4,0x00,0x4f] +// CHECK: movi v31.4s, #{{0x1|1}}, msl #16 // encoding: [0x3f,0xd4,0x00,0x4f] //---------------------------------------------------------------------- // Vector Move Inverted Immediate Masked @@ -148,10 +148,10 @@ mvni v31.4s, #0x1, msl #8 mvni v0.4s, #0x1, msl #16 -// CHECK: mvni v1.2s, #0x1, msl #8 // encoding: [0x21,0xc4,0x00,0x2f] -// CHECK: mvni v0.2s, #0x1, msl #16 // encoding: [0x20,0xd4,0x00,0x2f] -// CHECK: mvni v31.4s, #0x1, msl #8 // encoding: [0x3f,0xc4,0x00,0x6f] -// CHECK: mvni v0.4s, #0x1, msl #16 // encoding: [0x20,0xd4,0x00,0x6f] +// CHECK: mvni v1.2s, #{{0x1|1}}, msl #8 // encoding: [0x21,0xc4,0x00,0x2f] +// CHECK: mvni v0.2s, #{{0x1|1}}, msl #16 // encoding: [0x20,0xd4,0x00,0x2f] +// CHECK: mvni v31.4s, #{{0x1|1}}, msl #8 // encoding: [0x3f,0xc4,0x00,0x6f] +// CHECK: mvni v0.4s, #{{0x1|1}}, msl #16 // encoding: [0x20,0xd4,0x00,0x6f] //---------------------------------------------------------------------- // Vector Immediate - per byte @@ -161,10 +161,10 @@ movi v15.16b, #0xf movi v31.16b, #0x1f -// CHECK: movi v0.8b, #0x0 // encoding: [0x00,0xe4,0x00,0x0f] -// CHECK: movi v31.8b, #0xff // encoding: [0xff,0xe7,0x07,0x0f] -// CHECK: movi v15.16b, #0xf // encoding: [0xef,0xe5,0x00,0x4f] -// CHECK: movi v31.16b, #0x1f // encoding: [0xff,0xe7,0x00,0x4f] +// CHECK: movi v0.8b, #{{0x0|0}} // encoding: [0x00,0xe4,0x00,0x0f] +// CHECK: movi v31.8b, #{{0xff|255}} // encoding: [0xff,0xe7,0x07,0x0f] +// CHECK: movi v15.16b, #{{0xf|15}} // encoding: [0xef,0xe5,0x00,0x4f] +// CHECK: movi v31.16b, #{{0x1f|31}} // encoding: [0xff,0xe7,0x00,0x4f] //---------------------------------------------------------------------- // Vector Move Immediate - bytemask, per doubleword @@ -187,23 +187,22 @@ fmov v15.4s, #1.0 fmov v31.2d, #1.0 -// CHECK: fmov v1.2s, #1.00000000 // encoding: [0x01,0xf6,0x03,0x0f] -// CHECK: fmov v15.4s, #1.00000000 // encoding: [0x0f,0xf6,0x03,0x4f] -// CHECK: fmov v31.2d, #1.00000000 // encoding: [0x1f,0xf6,0x03,0x6f] +// CHECK: fmov v1.2s, #{{1.00000000|1.000000e\+00}} // encoding: [0x01,0xf6,0x03,0x0f] +// CHECK: fmov v15.4s, #{{1.00000000|1.000000e\+00}} // encoding: [0x0f,0xf6,0x03,0x4f] +// CHECK: fmov v31.2d, #{{1.00000000|1.000000e\+00}} // encoding: [0x1f,0xf6,0x03,0x6f] //---------------------------------------------------------------------- // Vector Move - register //---------------------------------------------------------------------- - // FIXME: these should all print with the "mov" syntax. mov v0.8b, v31.8b mov v15.16b, v16.16b orr v0.8b, v31.8b, v31.8b orr v15.16b, v16.16b, v16.16b -// CHECK: orr v0.8b, v31.8b, v31.8b // encoding: [0xe0,0x1f,0xbf,0x0e] -// CHECK: orr v15.16b, v16.16b, v16.16b // encoding: [0x0f,0x1e,0xb0,0x4e] -// CHECK: orr v0.8b, v31.8b, v31.8b // encoding: [0xe0,0x1f,0xbf,0x0e] -// CHECK: orr v15.16b, v16.16b, v16.16b // encoding: [0x0f,0x1e,0xb0,0x4e] +// CHECK: mov v0.8b, v31.8b // encoding: [0xe0,0x1f,0xbf,0x0e] +// CHECK: mov v15.16b, v16.16b // encoding: [0x0f,0x1e,0xb0,0x4e] +// CHECK: mov v0.8b, v31.8b // encoding: [0xe0,0x1f,0xbf,0x0e] +// CHECK: mov v15.16b, v16.16b // encoding: [0x0f,0x1e,0xb0,0x4e] diff --git a/test/MC/AArch64/neon-perm.s b/test/MC/AArch64/neon-perm.s index 20a4acde..4b28dd0 100644 --- a/test/MC/AArch64/neon-perm.s +++ b/test/MC/AArch64/neon-perm.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 diff --git a/test/MC/AArch64/neon-scalar-compare.s b/test/MC/AArch64/neon-scalar-compare.s index 55ade0e..28de46a 100644 --- a/test/MC/AArch64/neon-scalar-compare.s +++ b/test/MC/AArch64/neon-scalar-compare.s @@ -16,7 +16,7 @@ cmeq d20, d21, #0x0 -// CHECK: cmeq d20, d21, #0x0 // encoding: [0xb4,0x9a,0xe0,0x5e] +// CHECK: cmeq d20, d21, #{{0x0|0}} // encoding: [0xb4,0x9a,0xe0,0x5e] //---------------------------------------------------------------------- // Scalar Compare Unsigned Higher Or Same @@ -40,7 +40,7 @@ cmge d20, d21, #0x0 -// CHECK: cmge d20, d21, #0x0 // encoding: [0xb4,0x8a,0xe0,0x7e] +// CHECK: cmge d20, d21, #{{0x0|0}} // encoding: [0xb4,0x8a,0xe0,0x7e] //---------------------------------------------------------------------- // Scalar Compare Unsigned Higher @@ -63,7 +63,7 @@ cmgt d20, d21, #0x0 -// CHECK: cmgt d20, d21, #0x0 // encoding: [0xb4,0x8a,0xe0,0x5e] +// CHECK: cmgt d20, d21, #{{0x0|0}} // encoding: [0xb4,0x8a,0xe0,0x5e] //---------------------------------------------------------------------- // Scalar Compare Signed Less Than Or Equal To Zero @@ -71,7 +71,7 @@ cmle d20, d21, #0x0 -// CHECK: cmle d20, d21, #0x0 // encoding: [0xb4,0x9a,0xe0,0x7e] +// CHECK: cmle d20, d21, #{{0x0|0}} // encoding: [0xb4,0x9a,0xe0,0x7e] //---------------------------------------------------------------------- // Scalar Compare Less Than Zero @@ -79,7 +79,7 @@ cmlt d20, d21, #0x0 -// CHECK: cmlt d20, d21, #0x0 // encoding: [0xb4,0xaa,0xe0,0x5e] +// CHECK: cmlt d20, d21, #{{0x0|0}} // encoding: [0xb4,0xaa,0xe0,0x5e] //---------------------------------------------------------------------- // Scalar Compare Bitwise Test Bits diff --git a/test/MC/AArch64/neon-scalar-dup.s b/test/MC/AArch64/neon-scalar-dup.s index 77c638d..db11ea2 100644 --- a/test/MC/AArch64/neon-scalar-dup.s +++ b/test/MC/AArch64/neon-scalar-dup.s @@ -15,17 +15,17 @@ dup d3, v5.d[0] dup d6, v5.d[1] -// CHECK: dup b0, v0.b[15] // encoding: [0x00,0x04,0x1f,0x5e] -// CHECK: dup b1, v0.b[7] // encoding: [0x01,0x04,0x0f,0x5e] -// CHECK: dup b17, v0.b[0] // encoding: [0x11,0x04,0x01,0x5e] -// CHECK: dup h5, v31.h[7] // encoding: [0xe5,0x07,0x1e,0x5e] -// CHECK: dup h9, v1.h[4] // encoding: [0x29,0x04,0x12,0x5e] -// CHECK: dup h11, v17.h[0] // encoding: [0x2b,0x06,0x02,0x5e] -// CHECK: dup s2, v2.s[3] // encoding: [0x42,0x04,0x1c,0x5e] -// CHECK: dup s4, v21.s[0] // encoding: [0xa4,0x06,0x04,0x5e] -// CHECK: dup s31, v21.s[2] // encoding: [0xbf,0x06,0x14,0x5e] -// CHECK: dup d3, v5.d[0] // encoding: [0xa3,0x04,0x08,0x5e] -// CHECK: dup d6, v5.d[1] // encoding: [0xa6,0x04,0x18,0x5e] +// CHECK: {{dup|mov}} b0, v0.b[15] // encoding: [0x00,0x04,0x1f,0x5e] +// CHECK: {{dup|mov}} b1, v0.b[7] // encoding: [0x01,0x04,0x0f,0x5e] +// CHECK: {{dup|mov}} b17, v0.b[0] // encoding: [0x11,0x04,0x01,0x5e] +// CHECK: {{dup|mov}} h5, v31.h[7] // encoding: [0xe5,0x07,0x1e,0x5e] +// CHECK: {{dup|mov}} h9, v1.h[4] // encoding: [0x29,0x04,0x12,0x5e] +// CHECK: {{dup|mov}} h11, v17.h[0] // encoding: [0x2b,0x06,0x02,0x5e] +// CHECK: {{dup|mov}} s2, v2.s[3] // encoding: [0x42,0x04,0x1c,0x5e] +// CHECK: {{dup|mov}} s4, v21.s[0] // encoding: [0xa4,0x06,0x04,0x5e] +// CHECK: {{dup|mov}} s31, v21.s[2] // encoding: [0xbf,0x06,0x14,0x5e] +// CHECK: {{dup|mov}} d3, v5.d[0] // encoding: [0xa3,0x04,0x08,0x5e] +// CHECK: {{dup|mov}} d6, v5.d[1] // encoding: [0xa6,0x04,0x18,0x5e] //------------------------------------------------------------------------------ // Aliases for Duplicate element (scalar) @@ -42,14 +42,14 @@ mov d3, v5.d[0] mov d6, v5.d[1] -// CHECK: dup b0, v0.b[15] // encoding: [0x00,0x04,0x1f,0x5e] -// CHECK: dup b1, v0.b[7] // encoding: [0x01,0x04,0x0f,0x5e] -// CHECK: dup b17, v0.b[0] // encoding: [0x11,0x04,0x01,0x5e] -// CHECK: dup h5, v31.h[7] // encoding: [0xe5,0x07,0x1e,0x5e] -// CHECK: dup h9, v1.h[4] // encoding: [0x29,0x04,0x12,0x5e] -// CHECK: dup h11, v17.h[0] // encoding: [0x2b,0x06,0x02,0x5e] -// CHECK: dup s2, v2.s[3] // encoding: [0x42,0x04,0x1c,0x5e] -// CHECK: dup s4, v21.s[0] // encoding: [0xa4,0x06,0x04,0x5e] -// CHECK: dup s31, v21.s[2] // encoding: [0xbf,0x06,0x14,0x5e] -// CHECK: dup d3, v5.d[0] // encoding: [0xa3,0x04,0x08,0x5e] -// CHECK: dup d6, v5.d[1] // encoding: [0xa6,0x04,0x18,0x5e] +// CHECK: {{dup|mov}} b0, v0.b[15] // encoding: [0x00,0x04,0x1f,0x5e] +// CHECK: {{dup|mov}} b1, v0.b[7] // encoding: [0x01,0x04,0x0f,0x5e] +// CHECK: {{dup|mov}} b17, v0.b[0] // encoding: [0x11,0x04,0x01,0x5e] +// CHECK: {{dup|mov}} h5, v31.h[7] // encoding: [0xe5,0x07,0x1e,0x5e] +// CHECK: {{dup|mov}} h9, v1.h[4] // encoding: [0x29,0x04,0x12,0x5e] +// CHECK: {{dup|mov}} h11, v17.h[0] // encoding: [0x2b,0x06,0x02,0x5e] +// CHECK: {{dup|mov}} s2, v2.s[3] // encoding: [0x42,0x04,0x1c,0x5e] +// CHECK: {{dup|mov}} s4, v21.s[0] // encoding: [0xa4,0x06,0x04,0x5e] +// CHECK: {{dup|mov}} s31, v21.s[2] // encoding: [0xbf,0x06,0x14,0x5e] +// CHECK: {{dup|mov}} d3, v5.d[0] // encoding: [0xa3,0x04,0x08,0x5e] +// CHECK: {{dup|mov}} d6, v5.d[1] // encoding: [0xa6,0x04,0x18,0x5e] diff --git a/test/MC/AArch64/neon-simd-copy.s b/test/MC/AArch64/neon-simd-copy.s index f254d65..4837a4c 100644 --- a/test/MC/AArch64/neon-simd-copy.s +++ b/test/MC/AArch64/neon-simd-copy.s @@ -16,15 +16,15 @@ mov v20.s[0], w30 mov v1.d[1], x7 -// CHECK: ins v2.b[2], w1 // encoding: [0x22,0x1c,0x05,0x4e] -// CHECK: ins v7.h[7], w14 // encoding: [0xc7,0x1d,0x1e,0x4e] -// CHECK: ins v20.s[0], w30 // encoding: [0xd4,0x1f,0x04,0x4e] -// CHECK: ins v1.d[1], x7 // encoding: [0xe1,0x1c,0x18,0x4e] +// CHECK: {{mov|ins}} v2.b[2], w1 // encoding: [0x22,0x1c,0x05,0x4e] +// CHECK: {{mov|ins}} v7.h[7], w14 // encoding: [0xc7,0x1d,0x1e,0x4e] +// CHECK: {{mov|ins}} v20.s[0], w30 // encoding: [0xd4,0x1f,0x04,0x4e] +// CHECK: {{mov|ins}} v1.d[1], x7 // encoding: [0xe1,0x1c,0x18,0x4e] -// CHECK: ins v2.b[2], w1 // encoding: [0x22,0x1c,0x05,0x4e] -// CHECK: ins v7.h[7], w14 // encoding: [0xc7,0x1d,0x1e,0x4e] -// CHECK: ins v20.s[0], w30 // encoding: [0xd4,0x1f,0x04,0x4e] -// CHECK: ins v1.d[1], x7 // encoding: [0xe1,0x1c,0x18,0x4e] +// CHECK: {{mov|ins}} v2.b[2], w1 // encoding: [0x22,0x1c,0x05,0x4e] +// CHECK: {{mov|ins}} v7.h[7], w14 // encoding: [0xc7,0x1d,0x1e,0x4e] +// CHECK: {{mov|ins}} v20.s[0], w30 // encoding: [0xd4,0x1f,0x04,0x4e] +// CHECK: {{mov|ins}} v1.d[1], x7 // encoding: [0xe1,0x1c,0x18,0x4e] //------------------------------------------------------------------------------ @@ -54,13 +54,13 @@ mov w20, v9.s[2] mov x7, v18.d[1] -// CHECK: umov w1, v0.b[15] // encoding: [0x01,0x3c,0x1f,0x0e] -// CHECK: umov w14, v6.h[4] // encoding: [0xce,0x3c,0x12,0x0e] -// CHECK: umov w20, v9.s[2] // encoding: [0x34,0x3d,0x14,0x0e] -// CHECK: umov x7, v18.d[1] // encoding: [0x47,0x3e,0x18,0x4e] +// CHECK: {{mov|umov}} w1, v0.b[15] // encoding: [0x01,0x3c,0x1f,0x0e] +// CHECK: {{mov|umov}} w14, v6.h[4] // encoding: [0xce,0x3c,0x12,0x0e] +// CHECK: {{mov|umov}} w20, v9.s[2] // encoding: [0x34,0x3d,0x14,0x0e] +// CHECK: {{mov|umov}} x7, v18.d[1] // encoding: [0x47,0x3e,0x18,0x4e] -// CHECK: umov w20, v9.s[2] // encoding: [0x34,0x3d,0x14,0x0e] -// CHECK: umov x7, v18.d[1] // encoding: [0x47,0x3e,0x18,0x4e] +// CHECK: {{mov|umov}} w20, v9.s[2] // encoding: [0x34,0x3d,0x14,0x0e] +// CHECK: {{mov|umov}} x7, v18.d[1] // encoding: [0x47,0x3e,0x18,0x4e] //------------------------------------------------------------------------------ // Insert element (vector, from element) @@ -76,15 +76,15 @@ mov v15.s[3], v22.s[2] mov v0.d[0], v4.d[1] -// CHECK: ins v1.b[14], v3.b[6] // encoding: [0x61,0x34,0x1d,0x6e] -// CHECK: ins v6.h[7], v7.h[5] // encoding: [0xe6,0x54,0x1e,0x6e] -// CHECK: ins v15.s[3], v22.s[2] // encoding: [0xcf,0x46,0x1c,0x6e] -// CHECK: ins v0.d[0], v4.d[1] // encoding: [0x80,0x44,0x08,0x6e] +// CHECK: {{mov|ins}} v1.b[14], v3.b[6] // encoding: [0x61,0x34,0x1d,0x6e] +// CHECK: {{mov|ins}} v6.h[7], v7.h[5] // encoding: [0xe6,0x54,0x1e,0x6e] +// CHECK: {{mov|ins}} v15.s[3], v22.s[2] // encoding: [0xcf,0x46,0x1c,0x6e] +// CHECK: {{mov|ins}} v0.d[0], v4.d[1] // encoding: [0x80,0x44,0x08,0x6e] -// CHECK: ins v1.b[14], v3.b[6] // encoding: [0x61,0x34,0x1d,0x6e] -// CHECK: ins v6.h[7], v7.h[5] // encoding: [0xe6,0x54,0x1e,0x6e] -// CHECK: ins v15.s[3], v22.s[2] // encoding: [0xcf,0x46,0x1c,0x6e] -// CHECK: ins v0.d[0], v4.d[1] // encoding: [0x80,0x44,0x08,0x6e] +// CHECK: {{mov|ins}} v1.b[14], v3.b[6] // encoding: [0x61,0x34,0x1d,0x6e] +// CHECK: {{mov|ins}} v6.h[7], v7.h[5] // encoding: [0xe6,0x54,0x1e,0x6e] +// CHECK: {{mov|ins}} v15.s[3], v22.s[2] // encoding: [0xcf,0x46,0x1c,0x6e] +// CHECK: {{mov|ins}} v0.d[0], v4.d[1] // encoding: [0x80,0x44,0x08,0x6e] //------------------------------------------------------------------------------ // Duplicate to all lanes( vector, from element) @@ -97,13 +97,13 @@ dup v17.4s, v20.s[0] dup v5.2d, v1.d[1] -// CHECK: dup v1.8b, v2.b[2] // encoding: [0x41,0x04,0x05,0x0e] -// CHECK: dup v11.4h, v7.h[7] // encoding: [0xeb,0x04,0x1e,0x0e] -// CHECK: dup v17.2s, v20.s[0] // encoding: [0x91,0x06,0x04,0x0e] -// CHECK: dup v1.16b, v2.b[2] // encoding: [0x41,0x04,0x05,0x4e] -// CHECK: dup v11.8h, v7.h[7] // encoding: [0xeb,0x04,0x1e,0x4e] -// CHECK: dup v17.4s, v20.s[0] // encoding: [0x91,0x06,0x04,0x4e] -// CHECK: dup v5.2d, v1.d[1] // encoding: [0x25,0x04,0x18,0x4e] +// CHECK: {{mov|dup}} v1.8b, v2.b[2] // encoding: [0x41,0x04,0x05,0x0e] +// CHECK: {{mov|dup}} v11.4h, v7.h[7] // encoding: [0xeb,0x04,0x1e,0x0e] +// CHECK: {{mov|dup}} v17.2s, v20.s[0] // encoding: [0x91,0x06,0x04,0x0e] +// CHECK: {{mov|dup}} v1.16b, v2.b[2] // encoding: [0x41,0x04,0x05,0x4e] +// CHECK: {{mov|dup}} v11.8h, v7.h[7] // encoding: [0xeb,0x04,0x1e,0x4e] +// CHECK: {{mov|dup}} v17.4s, v20.s[0] // encoding: [0x91,0x06,0x04,0x4e] +// CHECK: {{mov|dup}} v5.2d, v1.d[1] // encoding: [0x25,0x04,0x18,0x4e] //------------------------------------------------------------------------------ // Duplicate to all lanes( vector, from main) @@ -116,13 +116,13 @@ dup v17.4s, w28 dup v5.2d, x0 -// CHECK: dup v1.8b, w1 // encoding: [0x21,0x0c,0x01,0x0e] -// CHECK: dup v11.4h, w14 // encoding: [0xcb,0x0d,0x02,0x0e] -// CHECK: dup v17.2s, w30 // encoding: [0xd1,0x0f,0x04,0x0e] -// CHECK: dup v1.16b, w2 // encoding: [0x41,0x0c,0x01,0x4e] -// CHECK: dup v11.8h, w16 // encoding: [0x0b,0x0e,0x02,0x4e] -// CHECK: dup v17.4s, w28 // encoding: [0x91,0x0f,0x04,0x4e] -// CHECK: dup v5.2d, x0 // encoding: [0x05,0x0c,0x08,0x4e] +// CHECK: {{mov|dup}} v1.8b, w1 // encoding: [0x21,0x0c,0x01,0x0e] +// CHECK: {{mov|dup}} v11.4h, w14 // encoding: [0xcb,0x0d,0x02,0x0e] +// CHECK: {{mov|dup}} v17.2s, w30 // encoding: [0xd1,0x0f,0x04,0x0e] +// CHECK: {{mov|dup}} v1.16b, w2 // encoding: [0x41,0x0c,0x01,0x4e] +// CHECK: {{mov|dup}} v11.8h, w16 // encoding: [0x0b,0x0e,0x02,0x4e] +// CHECK: {{mov|dup}} v17.4s, w28 // encoding: [0x91,0x0f,0x04,0x4e] +// CHECK: {{mov|dup}} v5.2d, x0 // encoding: [0x05,0x0c,0x08,0x4e] diff --git a/test/MC/AArch64/neon-simd-ldst-multi-elem.s b/test/MC/AArch64/neon-simd-ldst-multi-elem.s index 05fe4da..b8b3e72 100644 --- a/test/MC/AArch64/neon-simd-ldst-multi-elem.s +++ b/test/MC/AArch64/neon-simd-ldst-multi-elem.s @@ -1,463 +1,463 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 //------------------------------------------------------------------------------ // Store multiple 1-element structures from one register //------------------------------------------------------------------------------ - st1 {v0.16b}, [x0] - st1 {v15.8h}, [x15] - st1 {v31.4s}, [sp] - st1 {v0.2d}, [x0] - st1 {v0.8b}, [x0] - st1 {v15.4h}, [x15] - st1 {v31.2s}, [sp] - st1 {v0.1d}, [x0] -// CHECK: st1 {v0.16b}, [x0] // encoding: [0x00,0x70,0x00,0x4c] -// CHECK: st1 {v15.8h}, [x15] // encoding: [0xef,0x75,0x00,0x4c] -// CHECK: st1 {v31.4s}, [sp] // encoding: [0xff,0x7b,0x00,0x4c] -// CHECK: st1 {v0.2d}, [x0] // encoding: [0x00,0x7c,0x00,0x4c] -// CHECK: st1 {v0.8b}, [x0] // encoding: [0x00,0x70,0x00,0x0c] -// CHECK: st1 {v15.4h}, [x15] // encoding: [0xef,0x75,0x00,0x0c] -// CHECK: st1 {v31.2s}, [sp] // encoding: [0xff,0x7b,0x00,0x0c] -// CHECK: st1 {v0.1d}, [x0] // encoding: [0x00,0x7c,0x00,0x0c] + st1 { v0.16b }, [x0] + st1 { v15.8h }, [x15] + st1 { v31.4s }, [sp] + st1 { v0.2d }, [x0] + st1 { v0.8b }, [x0] + st1 { v15.4h }, [x15] + st1 { v31.2s }, [sp] + st1 { v0.1d }, [x0] +// CHECK: st1 { v0.16b }, [x0] // encoding: [0x00,0x70,0x00,0x4c] +// CHECK: st1 { v15.8h }, [x15] // encoding: [0xef,0x75,0x00,0x4c] +// CHECK: st1 { v31.4s }, [sp] // encoding: [0xff,0x7b,0x00,0x4c] +// CHECK: st1 { v0.2d }, [x0] // encoding: [0x00,0x7c,0x00,0x4c] +// CHECK: st1 { v0.8b }, [x0] // encoding: [0x00,0x70,0x00,0x0c] +// CHECK: st1 { v15.4h }, [x15] // encoding: [0xef,0x75,0x00,0x0c] +// CHECK: st1 { v31.2s }, [sp] // encoding: [0xff,0x7b,0x00,0x0c] +// CHECK: st1 { v0.1d }, [x0] // encoding: [0x00,0x7c,0x00,0x0c] //------------------------------------------------------------------------------ // Store multiple 1-element structures from two consecutive registers //------------------------------------------------------------------------------ - st1 {v0.16b, v1.16b}, [x0] - st1 {v15.8h, v16.8h}, [x15] - st1 {v31.4s, v0.4s}, [sp] - st1 {v0.2d, v1.2d}, [x0] - st1 {v0.8b, v1.8b}, [x0] - st1 {v15.4h, v16.4h}, [x15] - st1 {v31.2s, v0.2s}, [sp] - st1 {v0.1d, v1.1d}, [x0] -// CHECK: st1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x00,0x4c] -// CHECK: st1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x00,0x4c] -// CHECK: st1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x00,0x4c] -// CHECK: st1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x00,0x4c] -// CHECK: st1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x00,0x0c] -// CHECK: st1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x00,0x0c] -// CHECK: st1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x00,0x0c] -// CHECK: st1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x00,0x0c] + st1 { v0.16b, v1.16b }, [x0] + st1 { v15.8h, v16.8h }, [x15] + st1 { v31.4s, v0.4s }, [sp] + st1 { v0.2d, v1.2d }, [x0] + st1 { v0.8b, v1.8b }, [x0] + st1 { v15.4h, v16.4h }, [x15] + st1 { v31.2s, v0.2s }, [sp] + st1 { v0.1d, v1.1d }, [x0] +// CHECK: st1 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0xa0,0x00,0x4c] +// CHECK: st1 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xa5,0x00,0x4c] +// CHECK: st1 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0xab,0x00,0x4c] +// CHECK: st1 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0xac,0x00,0x4c] +// CHECK: st1 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0xa0,0x00,0x0c] +// CHECK: st1 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xa5,0x00,0x0c] +// CHECK: st1 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0xab,0x00,0x0c] +// CHECK: st1 { v0.1d, v1.1d }, [x0] // encoding: [0x00,0xac,0x00,0x0c] - st1 {v0.16b-v1.16b}, [x0] - st1 {v15.8h-v16.8h}, [x15] - st1 {v31.4s-v0.4s}, [sp] - st1 {v0.2d-v1.2d}, [x0] - st1 {v0.8b-v1.8b}, [x0] - st1 {v15.4h-v16.4h}, [x15] - st1 {v31.2s-v0.2s}, [sp] - st1 {v0.1d-v1.1d}, [x0] -// CHECK: st1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x00,0x4c] -// CHECK: st1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x00,0x4c] -// CHECK: st1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x00,0x4c] -// CHECK: st1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x00,0x4c] -// CHECK: st1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x00,0x0c] -// CHECK: st1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x00,0x0c] -// CHECK: st1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x00,0x0c] -// CHECK: st1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x00,0x0c] + st1 { v0.16b-v1.16b }, [x0] + st1 { v15.8h-v16.8h }, [x15] + st1 { v31.4s-v0.4s }, [sp] + st1 { v0.2d-v1.2d }, [x0] + st1 { v0.8b-v1.8b }, [x0] + st1 { v15.4h-v16.4h }, [x15] + st1 { v31.2s-v0.2s }, [sp] + st1 { v0.1d-v1.1d }, [x0] +// CHECK: st1 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0xa0,0x00,0x4c] +// CHECK: st1 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xa5,0x00,0x4c] +// CHECK: st1 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0xab,0x00,0x4c] +// CHECK: st1 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0xac,0x00,0x4c] +// CHECK: st1 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0xa0,0x00,0x0c] +// CHECK: st1 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xa5,0x00,0x0c] +// CHECK: st1 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0xab,0x00,0x0c] +// CHECK: st1 { v0.1d, v1.1d }, [x0] // encoding: [0x00,0xac,0x00,0x0c] //------------------------------------------------------------------------------ // Store multiple 1-element structures from three consecutive registers //------------------------------------------------------------------------------ - st1 {v0.16b, v1.16b, v2.16b}, [x0] - st1 {v15.8h, v16.8h, v17.8h}, [x15] - st1 {v31.4s, v0.4s, v1.4s}, [sp] - st1 {v0.2d, v1.2d, v2.2d}, [x0] - st1 {v0.8b, v1.8b, v2.8b}, [x0] - st1 {v15.4h, v16.4h, v17.4h}, [x15] - st1 {v31.2s, v0.2s, v1.2s}, [sp] - st1 {v0.1d, v1.1d, v2.1d}, [x0] -// CHECK: st1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x00,0x4c] -// CHECK: st1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x00,0x4c] -// CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x00,0x4c] -// CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x00,0x4c] -// CHECK: st1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x00,0x0c] -// CHECK: st1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x00,0x0c] -// CHECK: st1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x00,0x0c] -// CHECK: st1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x00,0x0c] + st1 { v0.16b, v1.16b, v2.16b }, [x0] + st1 { v15.8h, v16.8h, v17.8h }, [x15] + st1 { v31.4s, v0.4s, v1.4s }, [sp] + st1 { v0.2d, v1.2d, v2.2d }, [x0] + st1 { v0.8b, v1.8b, v2.8b }, [x0] + st1 { v15.4h, v16.4h, v17.4h }, [x15] + st1 { v31.2s, v0.2s, v1.2s }, [sp] + st1 { v0.1d, v1.1d, v2.1d }, [x0] +// CHECK: st1 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x60,0x00,0x4c] +// CHECK: st1 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x65,0x00,0x4c] +// CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x6b,0x00,0x4c] +// CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x6c,0x00,0x4c] +// CHECK: st1 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x60,0x00,0x0c] +// CHECK: st1 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x65,0x00,0x0c] +// CHECK: st1 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x6b,0x00,0x0c] +// CHECK: st1 { v0.1d, v1.1d, v2.1d }, [x0] // encoding: [0x00,0x6c,0x00,0x0c] - st1 {v0.16b-v2.16b}, [x0] - st1 {v15.8h-v17.8h}, [x15] - st1 {v31.4s-v1.4s}, [sp] - st1 {v0.2d-v2.2d}, [x0] - st1 {v0.8b-v2.8b}, [x0] - st1 {v15.4h-v17.4h}, [x15] - st1 {v31.2s-v1.2s}, [sp] - st1 {v0.1d-v2.1d}, [x0] -// CHECK: st1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x00,0x4c] -// CHECK: st1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x00,0x4c] -// CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x00,0x4c] -// CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x00,0x4c] -// CHECK: st1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x00,0x0c] -// CHECK: st1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x00,0x0c] -// CHECK: st1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x00,0x0c] -// CHECK: st1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x00,0x0c] + st1 { v0.16b-v2.16b }, [x0] + st1 { v15.8h-v17.8h }, [x15] + st1 { v31.4s-v1.4s }, [sp] + st1 { v0.2d-v2.2d }, [x0] + st1 { v0.8b-v2.8b }, [x0] + st1 { v15.4h-v17.4h }, [x15] + st1 { v31.2s-v1.2s }, [sp] + st1 { v0.1d-v2.1d }, [x0] +// CHECK: st1 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x60,0x00,0x4c] +// CHECK: st1 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x65,0x00,0x4c] +// CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x6b,0x00,0x4c] +// CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x6c,0x00,0x4c] +// CHECK: st1 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x60,0x00,0x0c] +// CHECK: st1 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x65,0x00,0x0c] +// CHECK: st1 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x6b,0x00,0x0c] +// CHECK: st1 { v0.1d, v1.1d, v2.1d }, [x0] // encoding: [0x00,0x6c,0x00,0x0c] //------------------------------------------------------------------------------ // Store multiple 1-element structures from four consecutive registers //------------------------------------------------------------------------------ - st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] - st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] - st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] - st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] - st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] - st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] - st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] - st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] -// CHECK: st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x00,0x4c] -// CHECK: st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x00,0x4c] -// CHECK: st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x00,0x4c] -// CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x00,0x4c] -// CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x00,0x0c] -// CHECK: st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x00,0x0c] -// CHECK: st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x00,0x0c] -// CHECK: st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x00,0x0c] + st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] + st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] + st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] + st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] + st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] + st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] + st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] + st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] +// CHECK: st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x20,0x00,0x4c] +// CHECK: st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x25,0x00,0x4c] +// CHECK: st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x2b,0x00,0x4c] +// CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x2c,0x00,0x4c] +// CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x20,0x00,0x0c] +// CHECK: st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x25,0x00,0x0c] +// CHECK: st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x2b,0x00,0x0c] +// CHECK: st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] // encoding: [0x00,0x2c,0x00,0x0c] - st1 {v0.16b-v3.16b}, [x0] - st1 {v15.8h-v18.8h}, [x15] - st1 {v31.4s-v2.4s}, [sp] - st1 {v0.2d-v3.2d}, [x0] - st1 {v0.8b-v3.8b}, [x0] - st1 {v15.4h-v18.4h}, [x15] - st1 {v31.2s-v2.2s}, [sp] - st1 {v0.1d-v3.1d}, [x0] -// CHECK: st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x00,0x4c] -// CHECK: st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x00,0x4c] -// CHECK: st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x00,0x4c] -// CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x00,0x4c] -// CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x00,0x0c] -// CHECK: st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x00,0x0c] -// CHECK: st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x00,0x0c] -// CHECK: st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x00,0x0c] + st1 { v0.16b-v3.16b }, [x0] + st1 { v15.8h-v18.8h }, [x15] + st1 { v31.4s-v2.4s }, [sp] + st1 { v0.2d-v3.2d }, [x0] + st1 { v0.8b-v3.8b }, [x0] + st1 { v15.4h-v18.4h }, [x15] + st1 { v31.2s-v2.2s }, [sp] + st1 { v0.1d-v3.1d }, [x0] +// CHECK: st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x20,0x00,0x4c] +// CHECK: st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x25,0x00,0x4c] +// CHECK: st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x2b,0x00,0x4c] +// CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x2c,0x00,0x4c] +// CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x20,0x00,0x0c] +// CHECK: st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x25,0x00,0x0c] +// CHECK: st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x2b,0x00,0x0c] +// CHECK: st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] // encoding: [0x00,0x2c,0x00,0x0c] //------------------------------------------------------------------------------ // Store multiple 2-element structures from two consecutive registers //------------------------------------------------------------------------------ - st2 {v0.16b, v1.16b}, [x0] - st2 {v15.8h, v16.8h}, [x15] - st2 {v31.4s, v0.4s}, [sp] - st2 {v0.2d, v1.2d}, [x0] - st2 {v0.8b, v1.8b}, [x0] - st2 {v15.4h, v16.4h}, [x15] - st2 {v31.2s, v0.2s}, [sp] -// CHECK: st2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x00,0x4c] -// CHECK: st2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x00,0x4c] -// CHECK: st2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x00,0x4c] -// CHECK: st2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x00,0x4c] -// CHECK: st2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x00,0x0c] -// CHECK: st2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x00,0x0c] -// CHECK: st2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x00,0x0c] + st2 { v0.16b, v1.16b }, [x0] + st2 { v15.8h, v16.8h }, [x15] + st2 { v31.4s, v0.4s }, [sp] + st2 { v0.2d, v1.2d }, [x0] + st2 { v0.8b, v1.8b }, [x0] + st2 { v15.4h, v16.4h }, [x15] + st2 { v31.2s, v0.2s }, [sp] +// CHECK: st2 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0x80,0x00,0x4c] +// CHECK: st2 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0x85,0x00,0x4c] +// CHECK: st2 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0x8b,0x00,0x4c] +// CHECK: st2 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0x8c,0x00,0x4c] +// CHECK: st2 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0x80,0x00,0x0c] +// CHECK: st2 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0x85,0x00,0x0c] +// CHECK: st2 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0x8b,0x00,0x0c] - st2 {v0.16b-v1.16b}, [x0] - st2 {v15.8h-v16.8h}, [x15] - st2 {v31.4s-v0.4s}, [sp] - st2 {v0.2d-v1.2d}, [x0] - st2 {v0.8b-v1.8b}, [x0] - st2 {v15.4h-v16.4h}, [x15] - st2 {v31.2s-v0.2s}, [sp] -// CHECK: st2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x00,0x4c] -// CHECK: st2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x00,0x4c] -// CHECK: st2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x00,0x4c] -// CHECK: st2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x00,0x4c] -// CHECK: st2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x00,0x0c] -// CHECK: st2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x00,0x0c] -// CHECK: st2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x00,0x0c] + st2 { v0.16b-v1.16b }, [x0] + st2 { v15.8h-v16.8h }, [x15] + st2 { v31.4s-v0.4s }, [sp] + st2 { v0.2d-v1.2d }, [x0] + st2 { v0.8b-v1.8b }, [x0] + st2 { v15.4h-v16.4h }, [x15] + st2 { v31.2s-v0.2s }, [sp] +// CHECK: st2 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0x80,0x00,0x4c] +// CHECK: st2 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0x85,0x00,0x4c] +// CHECK: st2 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0x8b,0x00,0x4c] +// CHECK: st2 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0x8c,0x00,0x4c] +// CHECK: st2 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0x80,0x00,0x0c] +// CHECK: st2 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0x85,0x00,0x0c] +// CHECK: st2 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0x8b,0x00,0x0c] //------------------------------------------------------------------------------ // Store multiple 3-element structures from three consecutive registers //------------------------------------------------------------------------------ - st3 {v0.16b, v1.16b, v2.16b}, [x0] - st3 {v15.8h, v16.8h, v17.8h}, [x15] - st3 {v31.4s, v0.4s, v1.4s}, [sp] - st3 {v0.2d, v1.2d, v2.2d}, [x0] - st3 {v0.8b, v1.8b, v2.8b}, [x0] - st3 {v15.4h, v16.4h, v17.4h}, [x15] - st3 {v31.2s, v0.2s, v1.2s}, [sp] -// CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x00,0x4c] -// CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x00,0x4c] -// CHECK: st3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x00,0x4c] -// CHECK: st3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x00,0x4c] -// CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x00,0x0c] -// CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x00,0x0c] -// CHECK: st3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x00,0x0c] + st3 { v0.16b, v1.16b, v2.16b }, [x0] + st3 { v15.8h, v16.8h, v17.8h }, [x15] + st3 { v31.4s, v0.4s, v1.4s }, [sp] + st3 { v0.2d, v1.2d, v2.2d }, [x0] + st3 { v0.8b, v1.8b, v2.8b }, [x0] + st3 { v15.4h, v16.4h, v17.4h }, [x15] + st3 { v31.2s, v0.2s, v1.2s }, [sp] +// CHECK: st3 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x40,0x00,0x4c] +// CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x45,0x00,0x4c] +// CHECK: st3 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x4b,0x00,0x4c] +// CHECK: st3 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x4c,0x00,0x4c] +// CHECK: st3 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x40,0x00,0x0c] +// CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x45,0x00,0x0c] +// CHECK: st3 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x4b,0x00,0x0c] - st3 {v0.16b-v2.16b}, [x0] - st3 {v15.8h-v17.8h}, [x15] - st3 {v31.4s-v1.4s}, [sp] - st3 {v0.2d-v2.2d}, [x0] - st3 {v0.8b-v2.8b}, [x0] - st3 {v15.4h-v17.4h}, [x15] - st3 {v31.2s-v1.2s}, [sp] -// CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x00,0x4c] -// CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x00,0x4c] -// CHECK: st3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x00,0x4c] -// CHECK: st3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x00,0x4c] -// CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x00,0x0c] -// CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x00,0x0c] -// CHECK: st3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x00,0x0c] + st3 { v0.16b-v2.16b }, [x0] + st3 { v15.8h-v17.8h }, [x15] + st3 { v31.4s-v1.4s }, [sp] + st3 { v0.2d-v2.2d }, [x0] + st3 { v0.8b-v2.8b }, [x0] + st3 { v15.4h-v17.4h }, [x15] + st3 { v31.2s-v1.2s }, [sp] +// CHECK: st3 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x40,0x00,0x4c] +// CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x45,0x00,0x4c] +// CHECK: st3 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x4b,0x00,0x4c] +// CHECK: st3 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x4c,0x00,0x4c] +// CHECK: st3 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x40,0x00,0x0c] +// CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x45,0x00,0x0c] +// CHECK: st3 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x4b,0x00,0x0c] //------------------------------------------------------------------------------ // Store multiple 4-element structures from four consecutive registers //------------------------------------------------------------------------------ - st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] - st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] - st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] - st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] - st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] - st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] - st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] -// CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x00,0x4c] -// CHECK: st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x00,0x4c] -// CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x00,0x4c] -// CHECK: st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x00,0x4c] -// CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x00,0x0c] -// CHECK: st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x00,0x0c] -// CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x00,0x0c] + st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] + st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] + st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] + st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] + st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] + st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] + st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] +// CHECK: st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x00,0x00,0x4c] +// CHECK: st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x05,0x00,0x4c] +// CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x0b,0x00,0x4c] +// CHECK: st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x0c,0x00,0x4c] +// CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x00,0x0c] +// CHECK: st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x05,0x00,0x0c] +// CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x0b,0x00,0x0c] - st4 {v0.16b-v3.16b}, [x0] - st4 {v15.8h-v18.8h}, [x15] - st4 {v31.4s-v2.4s}, [sp] - st4 {v0.2d-v3.2d}, [x0] - st4 {v0.8b-v3.8b}, [x0] - st4 {v15.4h-v18.4h}, [x15] - st4 {v31.2s-v2.2s}, [sp] -// CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x00,0x4c] -// CHECK: st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x00,0x4c] -// CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x00,0x4c] -// CHECK: st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x00,0x4c] -// CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x00,0x0c] -// CHECK: st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x00,0x0c] -// CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x00,0x0c] + st4 { v0.16b-v3.16b }, [x0] + st4 { v15.8h-v18.8h }, [x15] + st4 { v31.4s-v2.4s }, [sp] + st4 { v0.2d-v3.2d }, [x0] + st4 { v0.8b-v3.8b }, [x0] + st4 { v15.4h-v18.4h }, [x15] + st4 { v31.2s-v2.2s }, [sp] +// CHECK: st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x00,0x00,0x4c] +// CHECK: st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x05,0x00,0x4c] +// CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x0b,0x00,0x4c] +// CHECK: st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x0c,0x00,0x4c] +// CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x00,0x0c] +// CHECK: st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x05,0x00,0x0c] +// CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x0b,0x00,0x0c] //------------------------------------------------------------------------------ // Load multiple 1-element structures to one register //------------------------------------------------------------------------------ - ld1 {v0.16b}, [x0] - ld1 {v15.8h}, [x15] - ld1 {v31.4s}, [sp] - ld1 {v0.2d}, [x0] - ld1 {v0.8b}, [x0] - ld1 {v15.4h}, [x15] - ld1 {v31.2s}, [sp] - ld1 {v0.1d}, [x0] -// CHECK: ld1 {v0.16b}, [x0] // encoding: [0x00,0x70,0x40,0x4c] -// CHECK: ld1 {v15.8h}, [x15] // encoding: [0xef,0x75,0x40,0x4c] -// CHECK: ld1 {v31.4s}, [sp] // encoding: [0xff,0x7b,0x40,0x4c] -// CHECK: ld1 {v0.2d}, [x0] // encoding: [0x00,0x7c,0x40,0x4c] -// CHECK: ld1 {v0.8b}, [x0] // encoding: [0x00,0x70,0x40,0x0c] -// CHECK: ld1 {v15.4h}, [x15] // encoding: [0xef,0x75,0x40,0x0c] -// CHECK: ld1 {v31.2s}, [sp] // encoding: [0xff,0x7b,0x40,0x0c] -// CHECK: ld1 {v0.1d}, [x0] // encoding: [0x00,0x7c,0x40,0x0c] + ld1 { v0.16b }, [x0] + ld1 { v15.8h }, [x15] + ld1 { v31.4s }, [sp] + ld1 { v0.2d }, [x0] + ld1 { v0.8b }, [x0] + ld1 { v15.4h }, [x15] + ld1 { v31.2s }, [sp] + ld1 { v0.1d }, [x0] +// CHECK: ld1 { v0.16b }, [x0] // encoding: [0x00,0x70,0x40,0x4c] +// CHECK: ld1 { v15.8h }, [x15] // encoding: [0xef,0x75,0x40,0x4c] +// CHECK: ld1 { v31.4s }, [sp] // encoding: [0xff,0x7b,0x40,0x4c] +// CHECK: ld1 { v0.2d }, [x0] // encoding: [0x00,0x7c,0x40,0x4c] +// CHECK: ld1 { v0.8b }, [x0] // encoding: [0x00,0x70,0x40,0x0c] +// CHECK: ld1 { v15.4h }, [x15] // encoding: [0xef,0x75,0x40,0x0c] +// CHECK: ld1 { v31.2s }, [sp] // encoding: [0xff,0x7b,0x40,0x0c] +// CHECK: ld1 { v0.1d }, [x0] // encoding: [0x00,0x7c,0x40,0x0c] //------------------------------------------------------------------------------ // Load multiple 1-element structures to two consecutive registers //------------------------------------------------------------------------------ - ld1 {v0.16b, v1.16b}, [x0] - ld1 {v15.8h, v16.8h}, [x15] - ld1 {v31.4s, v0.4s}, [sp] - ld1 {v0.2d, v1.2d}, [x0] - ld1 {v0.8b, v1.8b}, [x0] - ld1 {v15.4h, v16.4h}, [x15] - ld1 {v31.2s, v0.2s}, [sp] - ld1 {v0.1d, v1.1d}, [x0] -// CHECK: ld1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x40,0x4c] -// CHECK: ld1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x40,0x4c] -// CHECK: ld1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x40,0x4c] -// CHECK: ld1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x40,0x4c] -// CHECK: ld1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x40,0x0c] -// CHECK: ld1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x40,0x0c] -// CHECK: ld1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x40,0x0c] -// CHECK: ld1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x40,0x0c] + ld1 { v0.16b, v1.16b }, [x0] + ld1 { v15.8h, v16.8h }, [x15] + ld1 { v31.4s, v0.4s }, [sp] + ld1 { v0.2d, v1.2d }, [x0] + ld1 { v0.8b, v1.8b }, [x0] + ld1 { v15.4h, v16.4h }, [x15] + ld1 { v31.2s, v0.2s }, [sp] + ld1 { v0.1d, v1.1d }, [x0] +// CHECK: ld1 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0xa0,0x40,0x4c] +// CHECK: ld1 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xa5,0x40,0x4c] +// CHECK: ld1 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0xab,0x40,0x4c] +// CHECK: ld1 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0xac,0x40,0x4c] +// CHECK: ld1 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0xa0,0x40,0x0c] +// CHECK: ld1 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xa5,0x40,0x0c] +// CHECK: ld1 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0xab,0x40,0x0c] +// CHECK: ld1 { v0.1d, v1.1d }, [x0] // encoding: [0x00,0xac,0x40,0x0c] - ld1 {v0.16b-v1.16b}, [x0] - ld1 {v15.8h-v16.8h}, [x15] - ld1 {v31.4s-v0.4s}, [sp] - ld1 {v0.2d-v1.2d}, [x0] - ld1 {v0.8b-v1.8b}, [x0] - ld1 {v15.4h-v16.4h}, [x15] - ld1 {v31.2s-v0.2s}, [sp] - ld1 {v0.1d-v1.1d}, [x0] -// CHECK: ld1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x40,0x4c] -// CHECK: ld1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x40,0x4c] -// CHECK: ld1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x40,0x4c] -// CHECK: ld1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x40,0x4c] -// CHECK: ld1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x40,0x0c] -// CHECK: ld1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x40,0x0c] -// CHECK: ld1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x40,0x0c] -// CHECK: ld1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x40,0x0c] + ld1 { v0.16b-v1.16b }, [x0] + ld1 { v15.8h-v16.8h }, [x15] + ld1 { v31.4s-v0.4s }, [sp] + ld1 { v0.2d-v1.2d }, [x0] + ld1 { v0.8b-v1.8b }, [x0] + ld1 { v15.4h-v16.4h }, [x15] + ld1 { v31.2s-v0.2s }, [sp] + ld1 { v0.1d-v1.1d }, [x0] +// CHECK: ld1 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0xa0,0x40,0x4c] +// CHECK: ld1 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xa5,0x40,0x4c] +// CHECK: ld1 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0xab,0x40,0x4c] +// CHECK: ld1 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0xac,0x40,0x4c] +// CHECK: ld1 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0xa0,0x40,0x0c] +// CHECK: ld1 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xa5,0x40,0x0c] +// CHECK: ld1 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0xab,0x40,0x0c] +// CHECK: ld1 { v0.1d, v1.1d }, [x0] // encoding: [0x00,0xac,0x40,0x0c] //------------------------------------------------------------------------------ // Load multiple 1-element structures to three consecutive registers //------------------------------------------------------------------------------ - ld1 {v0.16b, v1.16b, v2.16b}, [x0] - ld1 {v15.8h, v16.8h, v17.8h}, [x15] - ld1 {v31.4s, v0.4s, v1.4s}, [sp] - ld1 {v0.2d, v1.2d, v2.2d}, [x0] - ld1 {v0.8b, v1.8b, v2.8b}, [x0] - ld1 {v15.4h, v16.4h, v17.4h}, [x15] - ld1 {v31.2s, v0.2s, v1.2s}, [sp] - ld1 {v0.1d, v1.1d, v2.1d}, [x0] -// CHECK: ld1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x40,0x4c] -// CHECK: ld1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x40,0x4c] -// CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x40,0x4c] -// CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x40,0x4c] -// CHECK: ld1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x40,0x0c] -// CHECK: ld1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x40,0x0c] -// CHECK: ld1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x40,0x0c] -// CHECK: ld1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x40,0x0c] + ld1 { v0.16b, v1.16b, v2.16b }, [x0] + ld1 { v15.8h, v16.8h, v17.8h }, [x15] + ld1 { v31.4s, v0.4s, v1.4s }, [sp] + ld1 { v0.2d, v1.2d, v2.2d }, [x0] + ld1 { v0.8b, v1.8b, v2.8b }, [x0] + ld1 { v15.4h, v16.4h, v17.4h }, [x15] + ld1 { v31.2s, v0.2s, v1.2s }, [sp] + ld1 { v0.1d, v1.1d, v2.1d }, [x0] +// CHECK: ld1 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x60,0x40,0x4c] +// CHECK: ld1 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x65,0x40,0x4c] +// CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x6b,0x40,0x4c] +// CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x6c,0x40,0x4c] +// CHECK: ld1 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x60,0x40,0x0c] +// CHECK: ld1 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x65,0x40,0x0c] +// CHECK: ld1 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x6b,0x40,0x0c] +// CHECK: ld1 { v0.1d, v1.1d, v2.1d }, [x0] // encoding: [0x00,0x6c,0x40,0x0c] - ld1 {v0.16b-v2.16b}, [x0] - ld1 {v15.8h-v17.8h}, [x15] - ld1 {v31.4s-v1.4s}, [sp] - ld1 {v0.2d-v2.2d}, [x0] - ld1 {v0.8b-v2.8b}, [x0] - ld1 {v15.4h-v17.4h}, [x15] - ld1 {v31.2s-v1.2s}, [sp] - ld1 {v0.1d-v2.1d}, [x0] -// CHECK: ld1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x40,0x4c] -// CHECK: ld1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x40,0x4c] -// CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x40,0x4c] -// CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x40,0x4c] -// CHECK: ld1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x40,0x0c] -// CHECK: ld1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x40,0x0c] -// CHECK: ld1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x40,0x0c] -// CHECK: ld1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x40,0x0c] + ld1 { v0.16b-v2.16b }, [x0] + ld1 { v15.8h-v17.8h }, [x15] + ld1 { v31.4s-v1.4s }, [sp] + ld1 { v0.2d-v2.2d }, [x0] + ld1 { v0.8b-v2.8b }, [x0] + ld1 { v15.4h-v17.4h }, [x15] + ld1 { v31.2s-v1.2s }, [sp] + ld1 { v0.1d-v2.1d }, [x0] +// CHECK: ld1 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x60,0x40,0x4c] +// CHECK: ld1 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x65,0x40,0x4c] +// CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x6b,0x40,0x4c] +// CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x6c,0x40,0x4c] +// CHECK: ld1 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x60,0x40,0x0c] +// CHECK: ld1 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x65,0x40,0x0c] +// CHECK: ld1 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x6b,0x40,0x0c] +// CHECK: ld1 { v0.1d, v1.1d, v2.1d }, [x0] // encoding: [0x00,0x6c,0x40,0x0c] //------------------------------------------------------------------------------ // Load multiple 1-element structures to four consecutive registers //------------------------------------------------------------------------------ - ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] - ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] - ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] - ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] - ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] - ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] - ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] - ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] -// CHECK: ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x40,0x4c] -// CHECK: ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x40,0x4c] -// CHECK: ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x40,0x4c] -// CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x40,0x4c] -// CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x40,0x0c] -// CHECK: ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x40,0x0c] -// CHECK: ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x40,0x0c] -// CHECK: ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x40,0x0c] + ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] + ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] + ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] + ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] + ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] + ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] + ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] + ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] +// CHECK: ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x20,0x40,0x4c] +// CHECK: ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x25,0x40,0x4c] +// CHECK: ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x2b,0x40,0x4c] +// CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x2c,0x40,0x4c] +// CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x20,0x40,0x0c] +// CHECK: ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x25,0x40,0x0c] +// CHECK: ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x2b,0x40,0x0c] +// CHECK: ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] // encoding: [0x00,0x2c,0x40,0x0c] - ld1 {v0.16b-v3.16b}, [x0] - ld1 {v15.8h-v18.8h}, [x15] - ld1 {v31.4s-v2.4s}, [sp] - ld1 {v0.2d-v3.2d}, [x0] - ld1 {v0.8b-v3.8b}, [x0] - ld1 {v15.4h-v18.4h}, [x15] - ld1 {v31.2s-v2.2s}, [sp] - ld1 {v0.1d-v3.1d}, [x0] -// CHECK: ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x40,0x4c] -// CHECK: ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x40,0x4c] -// CHECK: ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x40,0x4c] -// CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x40,0x4c] -// CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x40,0x0c] -// CHECK: ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x40,0x0c] -// CHECK: ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x40,0x0c] -// CHECK: ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x40,0x0c] + ld1 { v0.16b-v3.16b }, [x0] + ld1 { v15.8h-v18.8h }, [x15] + ld1 { v31.4s-v2.4s }, [sp] + ld1 { v0.2d-v3.2d }, [x0] + ld1 { v0.8b-v3.8b }, [x0] + ld1 { v15.4h-v18.4h }, [x15] + ld1 { v31.2s-v2.2s }, [sp] + ld1 { v0.1d-v3.1d }, [x0] +// CHECK: ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x20,0x40,0x4c] +// CHECK: ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x25,0x40,0x4c] +// CHECK: ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x2b,0x40,0x4c] +// CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x2c,0x40,0x4c] +// CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x20,0x40,0x0c] +// CHECK: ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x25,0x40,0x0c] +// CHECK: ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x2b,0x40,0x0c] +// CHECK: ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0] // encoding: [0x00,0x2c,0x40,0x0c] //------------------------------------------------------------------------------ // Load multiple 4-element structures to two consecutive registers //------------------------------------------------------------------------------ - ld2 {v0.16b, v1.16b}, [x0] - ld2 {v15.8h, v16.8h}, [x15] - ld2 {v31.4s, v0.4s}, [sp] - ld2 {v0.2d, v1.2d}, [x0] - ld2 {v0.8b, v1.8b}, [x0] - ld2 {v15.4h, v16.4h}, [x15] - ld2 {v31.2s, v0.2s}, [sp] -// CHECK: ld2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x40,0x4c] -// CHECK: ld2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x40,0x4c] -// CHECK: ld2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x40,0x4c] -// CHECK: ld2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x40,0x4c] -// CHECK: ld2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x40,0x0c] -// CHECK: ld2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x40,0x0c] -// CHECK: ld2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x40,0x0c] + ld2 { v0.16b, v1.16b }, [x0] + ld2 { v15.8h, v16.8h }, [x15] + ld2 { v31.4s, v0.4s }, [sp] + ld2 { v0.2d, v1.2d }, [x0] + ld2 { v0.8b, v1.8b }, [x0] + ld2 { v15.4h, v16.4h }, [x15] + ld2 { v31.2s, v0.2s }, [sp] +// CHECK: ld2 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0x80,0x40,0x4c] +// CHECK: ld2 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0x85,0x40,0x4c] +// CHECK: ld2 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0x8b,0x40,0x4c] +// CHECK: ld2 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0x8c,0x40,0x4c] +// CHECK: ld2 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0x80,0x40,0x0c] +// CHECK: ld2 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0x85,0x40,0x0c] +// CHECK: ld2 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0x8b,0x40,0x0c] - ld2 {v0.16b-v1.16b}, [x0] - ld2 {v15.8h-v16.8h}, [x15] - ld2 {v31.4s-v0.4s}, [sp] - ld2 {v0.2d-v1.2d}, [x0] - ld2 {v0.8b-v1.8b}, [x0] - ld2 {v15.4h-v16.4h}, [x15] - ld2 {v31.2s-v0.2s}, [sp] -// CHECK: ld2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x40,0x4c] -// CHECK: ld2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x40,0x4c] -// CHECK: ld2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x40,0x4c] -// CHECK: ld2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x40,0x4c] -// CHECK: ld2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x40,0x0c] -// CHECK: ld2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x40,0x0c] -// CHECK: ld2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x40,0x0c] + ld2 { v0.16b-v1.16b }, [x0] + ld2 { v15.8h-v16.8h }, [x15] + ld2 { v31.4s-v0.4s }, [sp] + ld2 { v0.2d-v1.2d }, [x0] + ld2 { v0.8b-v1.8b }, [x0] + ld2 { v15.4h-v16.4h }, [x15] + ld2 { v31.2s-v0.2s }, [sp] +// CHECK: ld2 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0x80,0x40,0x4c] +// CHECK: ld2 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0x85,0x40,0x4c] +// CHECK: ld2 { v31.4s, v0.4s }, [sp] // encoding: [0xff,0x8b,0x40,0x4c] +// CHECK: ld2 { v0.2d, v1.2d }, [x0] // encoding: [0x00,0x8c,0x40,0x4c] +// CHECK: ld2 { v0.8b, v1.8b }, [x0] // encoding: [0x00,0x80,0x40,0x0c] +// CHECK: ld2 { v15.4h, v16.4h }, [x15] // encoding: [0xef,0x85,0x40,0x0c] +// CHECK: ld2 { v31.2s, v0.2s }, [sp] // encoding: [0xff,0x8b,0x40,0x0c] //------------------------------------------------------------------------------ // Load multiple 3-element structures to three consecutive registers //------------------------------------------------------------------------------ - ld3 {v0.16b, v1.16b, v2.16b}, [x0] - ld3 {v15.8h, v16.8h, v17.8h}, [x15] - ld3 {v31.4s, v0.4s, v1.4s}, [sp] - ld3 {v0.2d, v1.2d, v2.2d}, [x0] - ld3 {v0.8b, v1.8b, v2.8b}, [x0] - ld3 {v15.4h, v16.4h, v17.4h}, [x15] - ld3 {v31.2s, v0.2s, v1.2s}, [sp] -// CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x40,0x4c] -// CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x40,0x4c] -// CHECK: ld3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x40,0x4c] -// CHECK: ld3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x40,0x4c] -// CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x40,0x0c] -// CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x40,0x0c] -// CHECK: ld3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x40,0x0c] + ld3 { v0.16b, v1.16b, v2.16b }, [x0] + ld3 { v15.8h, v16.8h, v17.8h }, [x15] + ld3 { v31.4s, v0.4s, v1.4s }, [sp] + ld3 { v0.2d, v1.2d, v2.2d }, [x0] + ld3 { v0.8b, v1.8b, v2.8b }, [x0] + ld3 { v15.4h, v16.4h, v17.4h }, [x15] + ld3 { v31.2s, v0.2s, v1.2s }, [sp] +// CHECK: ld3 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x40,0x40,0x4c] +// CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x45,0x40,0x4c] +// CHECK: ld3 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x4b,0x40,0x4c] +// CHECK: ld3 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x4c,0x40,0x4c] +// CHECK: ld3 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x40,0x40,0x0c] +// CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x45,0x40,0x0c] +// CHECK: ld3 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x4b,0x40,0x0c] - ld3 {v0.16b-v2.16b}, [x0] - ld3 {v15.8h-v17.8h}, [x15] - ld3 {v31.4s-v1.4s}, [sp] - ld3 {v0.2d-v2.2d}, [x0] - ld3 {v0.8b-v2.8b}, [x0] - ld3 {v15.4h-v17.4h}, [x15] - ld3 {v31.2s-v1.2s}, [sp] -// CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x40,0x4c] -// CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x40,0x4c] -// CHECK: ld3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x40,0x4c] -// CHECK: ld3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x40,0x4c] -// CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x40,0x0c] -// CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x40,0x0c] -// CHECK: ld3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x40,0x0c] + ld3 { v0.16b-v2.16b }, [x0] + ld3 { v15.8h-v17.8h }, [x15] + ld3 { v31.4s-v1.4s }, [sp] + ld3 { v0.2d-v2.2d }, [x0] + ld3 { v0.8b-v2.8b }, [x0] + ld3 { v15.4h-v17.4h }, [x15] + ld3 { v31.2s-v1.2s }, [sp] +// CHECK: ld3 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x40,0x40,0x4c] +// CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x45,0x40,0x4c] +// CHECK: ld3 { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0x4b,0x40,0x4c] +// CHECK: ld3 { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0x4c,0x40,0x4c] +// CHECK: ld3 { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0x40,0x40,0x0c] +// CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0x45,0x40,0x0c] +// CHECK: ld3 { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0x4b,0x40,0x0c] //------------------------------------------------------------------------------ // Load multiple 4-element structures to four consecutive registers //------------------------------------------------------------------------------ - ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] - ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] - ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] - ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] - ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] - ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] - ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] -// CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x40,0x4c] -// CHECK: ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x40,0x4c] -// CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x40,0x4c] -// CHECK: ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x40,0x4c] -// CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x40,0x0c] -// CHECK: ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x40,0x0c] -// CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x40,0x0c] + ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] + ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] + ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] + ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] + ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] + ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] + ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] +// CHECK: ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x00,0x40,0x4c] +// CHECK: ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x05,0x40,0x4c] +// CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x0b,0x40,0x4c] +// CHECK: ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x0c,0x40,0x4c] +// CHECK: ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x40,0x0c] +// CHECK: ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x05,0x40,0x0c] +// CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x0b,0x40,0x0c] - ld4 {v0.16b-v3.16b}, [x0] - ld4 {v15.8h-v18.8h}, [x15] - ld4 {v31.4s-v2.4s}, [sp] - ld4 {v0.2d-v3.2d}, [x0] - ld4 {v0.8b-v3.8b}, [x0] - ld4 {v15.4h-v18.4h}, [x15] - ld4 {v31.2s-v2.2s}, [sp] -// CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x40,0x4c] -// CHECK: ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x40,0x4c] -// CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x40,0x4c] -// CHECK: ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x40,0x4c] -// CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x40,0x0c] -// CHECK: ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x40,0x0c] -// CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x40,0x0c] + ld4 { v0.16b-v3.16b }, [x0] + ld4 { v15.8h-v18.8h }, [x15] + ld4 { v31.4s-v2.4s }, [sp] + ld4 { v0.2d-v3.2d }, [x0] + ld4 { v0.8b-v3.8b }, [x0] + ld4 { v15.4h-v18.4h }, [x15] + ld4 { v31.2s-v2.2s }, [sp] +// CHECK: ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0x00,0x40,0x4c] +// CHECK: ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0x05,0x40,0x4c] +// CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0x0b,0x40,0x4c] +// CHECK: ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0x0c,0x40,0x4c] +// CHECK: ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0x00,0x40,0x0c] +// CHECK: ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0x05,0x40,0x0c] +// CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0x0b,0x40,0x0c] diff --git a/test/MC/AArch64/neon-simd-ldst-one-elem.s b/test/MC/AArch64/neon-simd-ldst-one-elem.s index 140d752..4febf6d 100644 --- a/test/MC/AArch64/neon-simd-ldst-one-elem.s +++ b/test/MC/AArch64/neon-simd-ldst-one-elem.s @@ -1,325 +1,325 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 //------------------------------------------------------------------------------ // Load single 1-element structure to all lanes of 1 register //------------------------------------------------------------------------------ - ld1r {v0.16b}, [x0] - ld1r {v15.8h}, [x15] - ld1r {v31.4s}, [sp] - ld1r {v0.2d}, [x0] - ld1r {v0.8b}, [x0] - ld1r {v15.4h}, [x15] - ld1r {v31.2s}, [sp] - ld1r {v0.1d}, [x0] -// CHECK: ld1r {v0.16b}, [x0] // encoding: [0x00,0xc0,0x40,0x4d] -// CHECK: ld1r {v15.8h}, [x15] // encoding: [0xef,0xc5,0x40,0x4d] -// CHECK: ld1r {v31.4s}, [sp] // encoding: [0xff,0xcb,0x40,0x4d] -// CHECK: ld1r {v0.2d}, [x0] // encoding: [0x00,0xcc,0x40,0x4d] -// CHECK: ld1r {v0.8b}, [x0] // encoding: [0x00,0xc0,0x40,0x0d] -// CHECK: ld1r {v15.4h}, [x15] // encoding: [0xef,0xc5,0x40,0x0d] -// CHECK: ld1r {v31.2s}, [sp] // encoding: [0xff,0xcb,0x40,0x0d] -// CHECK: ld1r {v0.1d}, [x0] // encoding: [0x00,0xcc,0x40,0x0d] + ld1r { v0.16b }, [x0] + ld1r { v15.8h }, [x15] + ld1r { v31.4s }, [sp] + ld1r { v0.2d }, [x0] + ld1r { v0.8b }, [x0] + ld1r { v15.4h }, [x15] + ld1r { v31.2s }, [sp] + ld1r { v0.1d }, [x0] +// CHECK: ld1r { v0.16b }, [x0] // encoding: [0x00,0xc0,0x40,0x4d] +// CHECK: ld1r { v15.8h }, [x15] // encoding: [0xef,0xc5,0x40,0x4d] +// CHECK: ld1r { v31.4s }, [sp] // encoding: [0xff,0xcb,0x40,0x4d] +// CHECK: ld1r { v0.2d }, [x0] // encoding: [0x00,0xcc,0x40,0x4d] +// CHECK: ld1r { v0.8b }, [x0] // encoding: [0x00,0xc0,0x40,0x0d] +// CHECK: ld1r { v15.4h }, [x15] // encoding: [0xef,0xc5,0x40,0x0d] +// CHECK: ld1r { v31.2s }, [sp] // encoding: [0xff,0xcb,0x40,0x0d] +// CHECK: ld1r { v0.1d }, [x0] // encoding: [0x00,0xcc,0x40,0x0d] //------------------------------------------------------------------------------ // Load single N-element structure to all lanes of N consecutive // registers (N = 2,3,4) //------------------------------------------------------------------------------ - ld2r {v0.16b, v1.16b}, [x0] - ld2r {v15.8h, v16.8h}, [x15] - ld2r {v31.4s, v0.4s}, [sp] - ld2r {v0.2d, v1.2d}, [x0] - ld2r {v0.8b, v1.8b}, [x0] - ld2r {v15.4h, v16.4h}, [x15] - ld2r {v31.2s, v0.2s}, [sp] - ld2r {v31.1d, v0.1d}, [sp] -// CHECK: ld2r {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xc0,0x60,0x4d] -// CHECK: ld2r {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xc5,0x60,0x4d] -// CHECK: ld2r {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xcb,0x60,0x4d] -// CHECK: ld2r {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xcc,0x60,0x4d] -// CHECK: ld2r {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xc0,0x60,0x0d] -// CHECK: ld2r {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xc5,0x60,0x0d] -// CHECK: ld2r {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xcb,0x60,0x0d] -// CHECK: ld2r {v31.1d, v0.1d}, [sp] // encoding: [0xff,0xcf,0x60,0x0d] + ld2r { v0.16b, v1.16b }, [x0] + ld2r { v15.8h, v16.8h }, [x15] + ld2r { v31.4s, v0.4s }, [sp] + ld2r { v0.2d, v1.2d }, [x0] + ld2r { v0.8b, v1.8b }, [x0] + ld2r { v15.4h, v16.4h }, [x15] + ld2r { v31.2s, v0.2s }, [sp] + ld2r { v31.1d, v0.1d }, [sp] +// CHECK: ld2r { v0.16b, v1.16b }, [x0] // encoding: [0x00,0xc0,0x60,0x4d] +// CHECK: ld2r { v15.8h, v16.8h }, [x15] // encoding: [0xef,0xc5,0x60,0x4d] +// CHECK: ld2r { v31.4s, v0.4s }, [sp] // encoding: [0xff,0xcb,0x60,0x4d] +// CHECK: ld2r { v0.2d, v1.2d }, [x0] // encoding: [0x00,0xcc,0x60,0x4d] +// CHECK: ld2r { v0.8b, v1.8b }, [x0] // encoding: [0x00,0xc0,0x60,0x0d] +// CHECK: ld2r { v15.4h, v16.4h }, [x15] // encoding: [0xef,0xc5,0x60,0x0d] +// CHECK: ld2r { v31.2s, v0.2s }, [sp] // encoding: [0xff,0xcb,0x60,0x0d] +// CHECK: ld2r { v31.1d, v0.1d }, [sp] // encoding: [0xff,0xcf,0x60,0x0d] - ld3r {v0.16b, v1.16b, v2.16b}, [x0] - ld3r {v15.8h, v16.8h, v17.8h}, [x15] - ld3r {v31.4s, v0.4s, v1.4s}, [sp] - ld3r {v0.2d, v1.2d, v2.2d}, [x0] - ld3r {v0.8b, v1.8b, v2.8b}, [x0] - ld3r {v15.4h, v16.4h, v17.4h}, [x15] - ld3r {v31.2s, v0.2s, v1.2s}, [sp] - ld3r {v31.1d, v0.1d, v1.1d}, [sp] -// CHECK: ld3r {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0xe0,0x40,0x4d] -// CHECK: ld3r {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0xe5,0x40,0x4d] -// CHECK: ld3r {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0xeb,0x40,0x4d] -// CHECK: ld3r {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0xec,0x40,0x4d] -// CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0xe0,0x40,0x0d] -// CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0xe5,0x40,0x0d] -// CHECK: ld3r {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0xeb,0x40,0x0d] -// CHECK: ld3r {v31.1d, v0.1d, v1.1d}, [sp] // encoding: [0xff,0xef,0x40,0x0d] + ld3r { v0.16b, v1.16b, v2.16b }, [x0] + ld3r { v15.8h, v16.8h, v17.8h }, [x15] + ld3r { v31.4s, v0.4s, v1.4s }, [sp] + ld3r { v0.2d, v1.2d, v2.2d }, [x0] + ld3r { v0.8b, v1.8b, v2.8b }, [x0] + ld3r { v15.4h, v16.4h, v17.4h }, [x15] + ld3r { v31.2s, v0.2s, v1.2s }, [sp] + ld3r { v31.1d, v0.1d, v1.1d }, [sp] +// CHECK: ld3r { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0xe0,0x40,0x4d] +// CHECK: ld3r { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0xe5,0x40,0x4d] +// CHECK: ld3r { v31.4s, v0.4s, v1.4s }, [sp] // encoding: [0xff,0xeb,0x40,0x4d] +// CHECK: ld3r { v0.2d, v1.2d, v2.2d }, [x0] // encoding: [0x00,0xec,0x40,0x4d] +// CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0] // encoding: [0x00,0xe0,0x40,0x0d] +// CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15] // encoding: [0xef,0xe5,0x40,0x0d] +// CHECK: ld3r { v31.2s, v0.2s, v1.2s }, [sp] // encoding: [0xff,0xeb,0x40,0x0d] +// CHECK: ld3r { v31.1d, v0.1d, v1.1d }, [sp] // encoding: [0xff,0xef,0x40,0x0d] - ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] - ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] - ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] - ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] - ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] - ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] - ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] - ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp] -// CHECK: ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0xe0,0x60,0x4d] -// CHECK: ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0xe5,0x60,0x4d] -// CHECK: ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0xeb,0x60,0x4d] -// CHECK: ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0xec,0x60,0x4d] -// CHECK: ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0xe0,0x60,0x0d] -// CHECK: ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0xe5,0x60,0x0d] -// CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0xeb,0x60,0x0d] -// CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp] // encoding: [0xff,0xef,0x60,0x0d] + ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] + ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] + ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] + ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] + ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] + ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] + ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] + ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp] +// CHECK: ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0xe0,0x60,0x4d] +// CHECK: ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15] // encoding: [0xef,0xe5,0x60,0x4d] +// CHECK: ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp] // encoding: [0xff,0xeb,0x60,0x4d] +// CHECK: ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] // encoding: [0x00,0xec,0x60,0x4d] +// CHECK: ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0] // encoding: [0x00,0xe0,0x60,0x0d] +// CHECK: ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15] // encoding: [0xef,0xe5,0x60,0x0d] +// CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] // encoding: [0xff,0xeb,0x60,0x0d] +// CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp] // encoding: [0xff,0xef,0x60,0x0d] //------------------------------------------------------------------------------ // Load single 1-element structure to one lane of 1 register. //------------------------------------------------------------------------------ - ld1 {v0.b}[9], [x0] - ld1 {v15.h}[7], [x15] - ld1 {v31.s}[3], [sp] - ld1 {v0.d}[1], [x0] -// CHECK: ld1 {v0.b}[9], [x0] // encoding: [0x00,0x04,0x40,0x4d] -// CHECK: ld1 {v15.h}[7], [x15] // encoding: [0xef,0x59,0x40,0x4d] -// CHECK: ld1 {v31.s}[3], [sp] // encoding: [0xff,0x93,0x40,0x4d] -// CHECK: ld1 {v0.d}[1], [x0] // encoding: [0x00,0x84,0x40,0x4d] + ld1 { v0.b }[9], [x0] + ld1 { v15.h }[7], [x15] + ld1 { v31.s }[3], [sp] + ld1 { v0.d }[1], [x0] +// CHECK: ld1 { v0.b }[9], [x0] // encoding: [0x00,0x04,0x40,0x4d] +// CHECK: ld1 { v15.h }[7], [x15] // encoding: [0xef,0x59,0x40,0x4d] +// CHECK: ld1 { v31.s }[3], [sp] // encoding: [0xff,0x93,0x40,0x4d] +// CHECK: ld1 { v0.d }[1], [x0] // encoding: [0x00,0x84,0x40,0x4d] //------------------------------------------------------------------------------ // Load single N-element structure to one lane of N consecutive registers // (N = 2,3,4) //------------------------------------------------------------------------------ - ld2 {v0.b, v1.b}[9], [x0] - ld2 {v15.h, v16.h}[7], [x15] - ld2 {v31.s, v0.s}[3], [sp] - ld2 {v0.d, v1.d}[1], [x0] -// CHECK: ld2 {v0.b, v1.b}[9], [x0] // encoding: [0x00,0x04,0x60,0x4d] -// CHECK: ld2 {v15.h, v16.h}[7], [x15] // encoding: [0xef,0x59,0x60,0x4d] -// CHECK: ld2 {v31.s, v0.s}[3], [sp] // encoding: [0xff,0x93,0x60,0x4d] -// CHECK: ld2 {v0.d, v1.d}[1], [x0] // encoding: [0x00,0x84,0x60,0x4d] + ld2 { v0.b, v1.b }[9], [x0] + ld2 { v15.h, v16.h }[7], [x15] + ld2 { v31.s, v0.s }[3], [sp] + ld2 { v0.d, v1.d }[1], [x0] +// CHECK: ld2 { v0.b, v1.b }[9], [x0] // encoding: [0x00,0x04,0x60,0x4d] +// CHECK: ld2 { v15.h, v16.h }[7], [x15] // encoding: [0xef,0x59,0x60,0x4d] +// CHECK: ld2 { v31.s, v0.s }[3], [sp] // encoding: [0xff,0x93,0x60,0x4d] +// CHECK: ld2 { v0.d, v1.d }[1], [x0] // encoding: [0x00,0x84,0x60,0x4d] - ld3 {v0.b, v1.b, v2.b}[9], [x0] - ld3 {v15.h, v16.h, v17.h}[7], [x15] - ld3 {v31.s, v0.s, v1.s}[3], [sp] - ld3 {v0.d, v1.d, v2.d}[1], [x0] -// CHECK: ld3 {v0.b, v1.b, v2.b}[9], [x0] // encoding: [0x00,0x24,0x40,0x4d] -// CHECK: ld3 {v15.h, v16.h, v17.h}[7], [x15] // encoding: [0xef,0x79,0x40,0x4d] -// CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp] // encoding: [0xff,0xb3,0x40,0x4d] -// CHECK: ld3 {v0.d, v1.d, v2.d}[1], [x0] // encoding: [0x00,0xa4,0x40,0x4d] + ld3 { v0.b, v1.b, v2.b }[9], [x0] + ld3 { v15.h, v16.h, v17.h }[7], [x15] + ld3 { v31.s, v0.s, v1.s }[3], [sp] + ld3 { v0.d, v1.d, v2.d }[1], [x0] +// CHECK: ld3 { v0.b, v1.b, v2.b }[9], [x0] // encoding: [0x00,0x24,0x40,0x4d] +// CHECK: ld3 { v15.h, v16.h, v17.h }[7], [x15] // encoding: [0xef,0x79,0x40,0x4d] +// CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp] // encoding: [0xff,0xb3,0x40,0x4d] +// CHECK: ld3 { v0.d, v1.d, v2.d }[1], [x0] // encoding: [0x00,0xa4,0x40,0x4d] - ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] - ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] - ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] - ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] -// CHECK: ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] // encoding: [0x00,0x24,0x60,0x4d] -// CHECK: ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] // encoding: [0xef,0x79,0x60,0x4d] -// CHECK: ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] // encoding: [0xff,0xb3,0x60,0x4d] -// CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] // encoding: [0x00,0xa4,0x60,0x4d] + ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] + ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15] + ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp] + ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] +// CHECK: ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] // encoding: [0x00,0x24,0x60,0x4d] +// CHECK: ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15] // encoding: [0xef,0x79,0x60,0x4d] +// CHECK: ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp] // encoding: [0xff,0xb3,0x60,0x4d] +// CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] // encoding: [0x00,0xa4,0x60,0x4d] //------------------------------------------------------------------------------ // Store single 1-element structure from one lane of 1 register. //------------------------------------------------------------------------------ - st1 {v0.b}[9], [x0] - st1 {v15.h}[7], [x15] - st1 {v31.s}[3], [sp] - st1 {v0.d}[1], [x0] -// CHECK: st1 {v0.b}[9], [x0] // encoding: [0x00,0x04,0x00,0x4d] -// CHECK: st1 {v15.h}[7], [x15] // encoding: [0xef,0x59,0x00,0x4d] -// CHECK: st1 {v31.s}[3], [sp] // encoding: [0xff,0x93,0x00,0x4d] -// CHECK: st1 {v0.d}[1], [x0] // encoding: [0x00,0x84,0x00,0x4d] + st1 { v0.b }[9], [x0] + st1 { v15.h }[7], [x15] + st1 { v31.s }[3], [sp] + st1 { v0.d }[1], [x0] +// CHECK: st1 { v0.b }[9], [x0] // encoding: [0x00,0x04,0x00,0x4d] +// CHECK: st1 { v15.h }[7], [x15] // encoding: [0xef,0x59,0x00,0x4d] +// CHECK: st1 { v31.s }[3], [sp] // encoding: [0xff,0x93,0x00,0x4d] +// CHECK: st1 { v0.d }[1], [x0] // encoding: [0x00,0x84,0x00,0x4d] //------------------------------------------------------------------------------ // Store single N-element structure from one lane of N consecutive registers // (N = 2,3,4) //------------------------------------------------------------------------------ - st2 {v0.b, v1.b}[9], [x0] - st2 {v15.h, v16.h}[7], [x15] - st2 {v31.s, v0.s}[3], [sp] - st2 {v0.d, v1.d}[1], [x0] -// CHECK: st2 {v0.b, v1.b}[9], [x0] // encoding: [0x00,0x04,0x20,0x4d] -// CHECK: st2 {v15.h, v16.h}[7], [x15] // encoding: [0xef,0x59,0x20,0x4d] -// CHECK: st2 {v31.s, v0.s}[3], [sp] // encoding: [0xff,0x93,0x20,0x4d] -// CHECK: st2 {v0.d, v1.d}[1], [x0] // encoding: [0x00,0x84,0x20,0x4d] + st2 { v0.b, v1.b }[9], [x0] + st2 { v15.h, v16.h }[7], [x15] + st2 { v31.s, v0.s }[3], [sp] + st2 { v0.d, v1.d }[1], [x0] +// CHECK: st2 { v0.b, v1.b }[9], [x0] // encoding: [0x00,0x04,0x20,0x4d] +// CHECK: st2 { v15.h, v16.h }[7], [x15] // encoding: [0xef,0x59,0x20,0x4d] +// CHECK: st2 { v31.s, v0.s }[3], [sp] // encoding: [0xff,0x93,0x20,0x4d] +// CHECK: st2 { v0.d, v1.d }[1], [x0] // encoding: [0x00,0x84,0x20,0x4d] - st3 {v0.b, v1.b, v2.b}[9], [x0] - st3 {v15.h, v16.h, v17.h}[7], [x15] - st3 {v31.s, v0.s, v1.s}[3], [sp] - st3 {v0.d, v1.d, v2.d}[1], [x0] -// CHECK: st3 {v0.b, v1.b, v2.b}[9], [x0] // encoding: [0x00,0x24,0x00,0x4d] -// CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15] // encoding: [0xef,0x79,0x00,0x4d] -// CHECK: st3 {v31.s, v0.s, v1.s}[3], [sp] // encoding: [0xff,0xb3,0x00,0x4d] -// CHECK: st3 {v0.d, v1.d, v2.d}[1], [x0] // encoding: [0x00,0xa4,0x00,0x4d] + st3 { v0.b, v1.b, v2.b }[9], [x0] + st3 { v15.h, v16.h, v17.h }[7], [x15] + st3 { v31.s, v0.s, v1.s }[3], [sp] + st3 { v0.d, v1.d, v2.d }[1], [x0] +// CHECK: st3 { v0.b, v1.b, v2.b }[9], [x0] // encoding: [0x00,0x24,0x00,0x4d] +// CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15] // encoding: [0xef,0x79,0x00,0x4d] +// CHECK: st3 { v31.s, v0.s, v1.s }[3], [sp] // encoding: [0xff,0xb3,0x00,0x4d] +// CHECK: st3 { v0.d, v1.d, v2.d }[1], [x0] // encoding: [0x00,0xa4,0x00,0x4d] - st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] - st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] - st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] - st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] -// CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] // encoding: [0x00,0x24,0x20,0x4d] -// CHECK: st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] // encoding: [0xef,0x79,0x20,0x4d] -// CHECK: st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] // encoding: [0xff,0xb3,0x20,0x4d] -// CHECK: st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] // encoding: [0x00,0xa4,0x20,0x4d] + st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] + st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15] + st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp] + st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] +// CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] // encoding: [0x00,0x24,0x20,0x4d] +// CHECK: st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15] // encoding: [0xef,0x79,0x20,0x4d] +// CHECK: st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp] // encoding: [0xff,0xb3,0x20,0x4d] +// CHECK: st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] // encoding: [0x00,0xa4,0x20,0x4d] //------------------------------------------------------------------------------ // Post-index oad single 1-element structure to all lanes of 1 register //------------------------------------------------------------------------------ - ld1r {v0.16b}, [x0], #1 - ld1r {v15.8h}, [x15], #2 - ld1r {v31.4s}, [sp], #4 - ld1r {v0.2d}, [x0], #8 - ld1r {v0.8b}, [x0], x0 - ld1r {v15.4h}, [x15], x1 - ld1r {v31.2s}, [sp], x2 - ld1r {v0.1d}, [x0], x3 -// CHECK: ld1r {v0.16b}, [x0], #1 // encoding: [0x00,0xc0,0xdf,0x4d] -// CHECK: ld1r {v15.8h}, [x15], #2 // encoding: [0xef,0xc5,0xdf,0x4d] -// CHECK: ld1r {v31.4s}, [sp], #4 // encoding: [0xff,0xcb,0xdf,0x4d] -// CHECK: ld1r {v0.2d}, [x0], #8 // encoding: [0x00,0xcc,0xdf,0x4d] -// CHECK: ld1r {v0.8b}, [x0], x0 // encoding: [0x00,0xc0,0xc0,0x0d] -// CHECK: ld1r {v15.4h}, [x15], x1 // encoding: [0xef,0xc5,0xc1,0x0d] -// CHECK: ld1r {v31.2s}, [sp], x2 // encoding: [0xff,0xcb,0xc2,0x0d] -// CHECK: ld1r {v0.1d}, [x0], x3 // encoding: [0x00,0xcc,0xc3,0x0d] + ld1r { v0.16b }, [x0], #1 + ld1r { v15.8h }, [x15], #2 + ld1r { v31.4s }, [sp], #4 + ld1r { v0.2d }, [x0], #8 + ld1r { v0.8b }, [x0], x0 + ld1r { v15.4h }, [x15], x1 + ld1r { v31.2s }, [sp], x2 + ld1r { v0.1d }, [x0], x3 +// CHECK: ld1r { v0.16b }, [x0], #1 // encoding: [0x00,0xc0,0xdf,0x4d] +// CHECK: ld1r { v15.8h }, [x15], #2 // encoding: [0xef,0xc5,0xdf,0x4d] +// CHECK: ld1r { v31.4s }, [sp], #4 // encoding: [0xff,0xcb,0xdf,0x4d] +// CHECK: ld1r { v0.2d }, [x0], #8 // encoding: [0x00,0xcc,0xdf,0x4d] +// CHECK: ld1r { v0.8b }, [x0], x0 // encoding: [0x00,0xc0,0xc0,0x0d] +// CHECK: ld1r { v15.4h }, [x15], x1 // encoding: [0xef,0xc5,0xc1,0x0d] +// CHECK: ld1r { v31.2s }, [sp], x2 // encoding: [0xff,0xcb,0xc2,0x0d] +// CHECK: ld1r { v0.1d }, [x0], x3 // encoding: [0x00,0xcc,0xc3,0x0d] //------------------------------------------------------------------------------ // Post-index load single N-element structure to all lanes of N consecutive // registers (N = 2,3,4) //------------------------------------------------------------------------------ - ld2r {v0.16b, v1.16b}, [x0], #2 - ld2r {v15.8h, v16.8h}, [x15], #4 - ld2r {v31.4s, v0.4s}, [sp], #8 - ld2r {v0.2d, v1.2d}, [x0], #16 - ld2r {v0.8b, v1.8b}, [x0], x6 - ld2r {v15.4h, v16.4h}, [x15], x7 - ld2r {v31.2s, v0.2s}, [sp], x9 - ld2r {v31.1d, v0.1d}, [x0], x5 -// CHECK: ld2r {v0.16b, v1.16b}, [x0], #2 // encoding: [0x00,0xc0,0xff,0x4d] -// CHECK: ld2r {v15.8h, v16.8h}, [x15], #4 // encoding: [0xef,0xc5,0xff,0x4d] -// CHECK: ld2r {v31.4s, v0.4s}, [sp], #8 // encoding: [0xff,0xcb,0xff,0x4d] -// CHECK: ld2r {v0.2d, v1.2d}, [x0], #16 // encoding: [0x00,0xcc,0xff,0x4d] -// CHECK: ld2r {v0.8b, v1.8b}, [x0], x6 // encoding: [0x00,0xc0,0xe6,0x0d] -// CHECK: ld2r {v15.4h, v16.4h}, [x15], x7 // encoding: [0xef,0xc5,0xe7,0x0d] -// CHECK: ld2r {v31.2s, v0.2s}, [sp], x9 // encoding: [0xff,0xcb,0xe9,0x0d] -// CHECK: ld2r {v31.1d, v0.1d}, [x0], x5 // encoding: [0x1f,0xcc,0xe5,0x0d] + ld2r { v0.16b, v1.16b }, [x0], #2 + ld2r { v15.8h, v16.8h }, [x15], #4 + ld2r { v31.4s, v0.4s }, [sp], #8 + ld2r { v0.2d, v1.2d }, [x0], #16 + ld2r { v0.8b, v1.8b }, [x0], x6 + ld2r { v15.4h, v16.4h }, [x15], x7 + ld2r { v31.2s, v0.2s }, [sp], x9 + ld2r { v31.1d, v0.1d }, [x0], x5 +// CHECK: ld2r { v0.16b, v1.16b }, [x0], #2 // encoding: [0x00,0xc0,0xff,0x4d] +// CHECK: ld2r { v15.8h, v16.8h }, [x15], #4 // encoding: [0xef,0xc5,0xff,0x4d] +// CHECK: ld2r { v31.4s, v0.4s }, [sp], #8 // encoding: [0xff,0xcb,0xff,0x4d] +// CHECK: ld2r { v0.2d, v1.2d }, [x0], #16 // encoding: [0x00,0xcc,0xff,0x4d] +// CHECK: ld2r { v0.8b, v1.8b }, [x0], x6 // encoding: [0x00,0xc0,0xe6,0x0d] +// CHECK: ld2r { v15.4h, v16.4h }, [x15], x7 // encoding: [0xef,0xc5,0xe7,0x0d] +// CHECK: ld2r { v31.2s, v0.2s }, [sp], x9 // encoding: [0xff,0xcb,0xe9,0x0d] +// CHECK: ld2r { v31.1d, v0.1d }, [x0], x5 // encoding: [0x1f,0xcc,0xe5,0x0d] - ld3r {v0.16b, v1.16b, v2.16b}, [x0], x9 - ld3r {v15.8h, v16.8h, v17.8h}, [x15], x6 - ld3r {v31.4s, v0.4s, v1.4s}, [sp], x7 - ld3r {v0.2d, v1.2d, v2.2d}, [x0], x5 - ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3 - ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6 - ld3r {v31.2s, v0.2s, v1.2s}, [sp], #12 - ld3r {v31.1d, v0.1d, v1.1d}, [sp], #24 -// CHECK: ld3r {v0.16b, v1.16b, v2.16b}, [x0], x9 // encoding: [0x00,0xe0,0xc9,0x4d] -// CHECK: ld3r {v15.8h, v16.8h, v17.8h}, [x15], x6 // encoding: [0xef,0xe5,0xc6,0x4d] -// CHECK: ld3r {v31.4s, v0.4s, v1.4s}, [sp], x7 // encoding: [0xff,0xeb,0xc7,0x4d] -// CHECK: ld3r {v0.2d, v1.2d, v2.2d}, [x0], x5 // encoding: [0x00,0xec,0xc5,0x4d] -// CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3 // encoding: [0x00,0xe0,0xdf,0x0d] -// CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6 // encoding: [0xef,0xe5,0xdf,0x0d] -// CHECK: ld3r {v31.2s, v0.2s, v1.2s}, [sp], #12 // encoding: [0xff,0xeb,0xdf,0x0d] -// CHECK: ld3r {v31.1d, v0.1d, v1.1d}, [sp], #24 // encoding: [0xff,0xef,0xdf,0x0d] + ld3r { v0.16b, v1.16b, v2.16b }, [x0], x9 + ld3r { v15.8h, v16.8h, v17.8h }, [x15], x6 + ld3r { v31.4s, v0.4s, v1.4s }, [sp], x7 + ld3r { v0.2d, v1.2d, v2.2d }, [x0], x5 + ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3 + ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6 + ld3r { v31.2s, v0.2s, v1.2s }, [sp], #12 + ld3r { v31.1d, v0.1d, v1.1d }, [sp], #24 +// CHECK: ld3r { v0.16b, v1.16b, v2.16b }, [x0], x9 // encoding: [0x00,0xe0,0xc9,0x4d] +// CHECK: ld3r { v15.8h, v16.8h, v17.8h }, [x15], x6 // encoding: [0xef,0xe5,0xc6,0x4d] +// CHECK: ld3r { v31.4s, v0.4s, v1.4s }, [sp], x7 // encoding: [0xff,0xeb,0xc7,0x4d] +// CHECK: ld3r { v0.2d, v1.2d, v2.2d }, [x0], x5 // encoding: [0x00,0xec,0xc5,0x4d] +// CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3 // encoding: [0x00,0xe0,0xdf,0x0d] +// CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6 // encoding: [0xef,0xe5,0xdf,0x0d] +// CHECK: ld3r { v31.2s, v0.2s, v1.2s }, [sp], #12 // encoding: [0xff,0xeb,0xdf,0x0d] +// CHECK: ld3r { v31.1d, v0.1d, v1.1d }, [sp], #24 // encoding: [0xff,0xef,0xdf,0x0d] - ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], #4 - ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], #8 - ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #16 - ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #32 - ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x5 - ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x9 - ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30 - ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7 -// CHECK: ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], #4 // encoding: [0x00,0xe0,0xff,0x4d] -// CHECK: ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], #8 // encoding: [0xef,0xe5,0xff,0x4d] -// CHECK: ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #16 // encoding: [0xff,0xeb,0xff,0x4d] -// CHECK: ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #32 // encoding: [0x00,0xec,0xff,0x4d] -// CHECK: ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x5 // encoding: [0x00,0xe0,0xe5,0x0d] -// CHECK: ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x9 // encoding: [0xef,0xe5,0xe9,0x0d] -// CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30 // encoding: [0xff,0xeb,0xfe,0x0d] -// CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7 // encoding: [0xff,0xef,0xe7,0x0d] + ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], #4 + ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], #8 + ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #16 + ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #32 + ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x5 + ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x9 + ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30 + ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7 +// CHECK: ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], #4 // encoding: [0x00,0xe0,0xff,0x4d] +// CHECK: ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], #8 // encoding: [0xef,0xe5,0xff,0x4d] +// CHECK: ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #16 // encoding: [0xff,0xeb,0xff,0x4d] +// CHECK: ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #32 // encoding: [0x00,0xec,0xff,0x4d] +// CHECK: ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x5 // encoding: [0x00,0xe0,0xe5,0x0d] +// CHECK: ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x9 // encoding: [0xef,0xe5,0xe9,0x0d] +// CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30 // encoding: [0xff,0xeb,0xfe,0x0d] +// CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7 // encoding: [0xff,0xef,0xe7,0x0d] //------------------------------------------------------------------------------ // Post-index load single 1-element structure to one lane of 1 register. //------------------------------------------------------------------------------ - ld1 {v0.b}[9], [x0], #1 - ld1 {v15.h}[7], [x15], x9 - ld1 {v31.s}[3], [sp], x6 - ld1 {v0.d}[1], [x0], #8 -// CHECK: ld1 {v0.b}[9], [x0], #1 // encoding: [0x00,0x04,0xdf,0x4d] -// CHECK: ld1 {v15.h}[7], [x15], x9 // encoding: [0xef,0x59,0xc9,0x4d] -// CHECK: ld1 {v31.s}[3], [sp], x6 // encoding: [0xff,0x93,0xc6,0x4d] -// CHECK: ld1 {v0.d}[1], [x0], #8 // encoding: [0x00,0x84,0xdf,0x4d] + ld1 { v0.b }[9], [x0], #1 + ld1 { v15.h }[7], [x15], x9 + ld1 { v31.s }[3], [sp], x6 + ld1 { v0.d }[1], [x0], #8 +// CHECK: ld1 { v0.b }[9], [x0], #1 // encoding: [0x00,0x04,0xdf,0x4d] +// CHECK: ld1 { v15.h }[7], [x15], x9 // encoding: [0xef,0x59,0xc9,0x4d] +// CHECK: ld1 { v31.s }[3], [sp], x6 // encoding: [0xff,0x93,0xc6,0x4d] +// CHECK: ld1 { v0.d }[1], [x0], #8 // encoding: [0x00,0x84,0xdf,0x4d] //------------------------------------------------------------------------------ // Post-index load single N-element structure to one lane of N consecutive // registers (N = 2,3,4) //------------------------------------------------------------------------------ - ld2 {v0.b, v1.b}[9], [x0], x3 - ld2 {v15.h, v16.h}[7], [x15], #4 - ld2 {v31.s, v0.s}[3], [sp], #8 - ld2 {v0.d, v1.d}[1], [x0], x0 -// CHECK: ld2 {v0.b, v1.b}[9], [x0], x3 // encoding: [0x00,0x04,0xe3,0x4d] -// CHECK: ld2 {v15.h, v16.h}[7], [x15], #4 // encoding: [0xef,0x59,0xff,0x4d] -// CHECK: ld2 {v31.s, v0.s}[3], [sp], #8 // encoding: [0xff,0x93,0xff,0x4d] -// CHECK: ld2 {v0.d, v1.d}[1], [x0], x0 // encoding: [0x00,0x84,0xe0,0x4d] + ld2 { v0.b, v1.b }[9], [x0], x3 + ld2 { v15.h, v16.h }[7], [x15], #4 + ld2 { v31.s, v0.s }[3], [sp], #8 + ld2 { v0.d, v1.d }[1], [x0], x0 +// CHECK: ld2 { v0.b, v1.b }[9], [x0], x3 // encoding: [0x00,0x04,0xe3,0x4d] +// CHECK: ld2 { v15.h, v16.h }[7], [x15], #4 // encoding: [0xef,0x59,0xff,0x4d] +// CHECK: ld2 { v31.s, v0.s }[3], [sp], #8 // encoding: [0xff,0x93,0xff,0x4d] +// CHECK: ld2 { v0.d, v1.d }[1], [x0], x0 // encoding: [0x00,0x84,0xe0,0x4d] - ld3 {v0.b, v1.b, v2.b}[9], [x0], #3 - ld3 {v15.h, v16.h, v17.h}[7], [x15], #6 - ld3 {v31.s, v0.s, v1.s}[3], [sp], x3 - ld3 {v0.d, v1.d, v2.d}[1], [x0], x6 -// CHECK: ld3 {v0.b, v1.b, v2.b}[9], [x0], #3 // encoding: [0x00,0x24,0xdf,0x4d] -// CHECK: ld3 {v15.h, v16.h, v17.h}[7], [x15], #6 // encoding: [0xef,0x79,0xdf,0x4d] -// CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3 // encoding: [0xff,0xb3,0xc3,0x4d] -// CHECK: ld3 {v0.d, v1.d, v2.d}[1], [x0], x6 // encoding: [0x00,0xa4,0xc6,0x4d] + ld3 { v0.b, v1.b, v2.b }[9], [x0], #3 + ld3 { v15.h, v16.h, v17.h }[7], [x15], #6 + ld3 { v31.s, v0.s, v1.s }[3], [sp], x3 + ld3 { v0.d, v1.d, v2.d }[1], [x0], x6 +// CHECK: ld3 { v0.b, v1.b, v2.b }[9], [x0], #3 // encoding: [0x00,0x24,0xdf,0x4d] +// CHECK: ld3 { v15.h, v16.h, v17.h }[7], [x15], #6 // encoding: [0xef,0x79,0xdf,0x4d] +// CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp], x3 // encoding: [0xff,0xb3,0xc3,0x4d] +// CHECK: ld3 { v0.d, v1.d, v2.d }[1], [x0], x6 // encoding: [0x00,0xa4,0xc6,0x4d] - ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 - ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 - ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 - ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 -// CHECK: ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 // encoding: [0x00,0x24,0xe5,0x4d] -// CHECK: ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 // encoding: [0xef,0x79,0xe7,0x4d] -// CHECK: ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 // encoding: [0xff,0xb3,0xff,0x4d] -// CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 // encoding: [0x00,0xa4,0xff,0x4d] + ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 + ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7 + ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16 + ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 +// CHECK: ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 // encoding: [0x00,0x24,0xe5,0x4d] +// CHECK: ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7 // encoding: [0xef,0x79,0xe7,0x4d] +// CHECK: ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16 // encoding: [0xff,0xb3,0xff,0x4d] +// CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 // encoding: [0x00,0xa4,0xff,0x4d] //------------------------------------------------------------------------------ // Post-index store single 1-element structure from one lane of 1 register. //------------------------------------------------------------------------------ - st1 {v0.b}[9], [x0], #1 - st1 {v15.h}[7], [x15], x9 - st1 {v31.s}[3], [sp], x6 - st1 {v0.d}[1], [x0], #8 -// CHECK: st1 {v0.b}[9], [x0], #1 // encoding: [0x00,0x04,0x9f,0x4d] -// CHECK: st1 {v15.h}[7], [x15], x9 // encoding: [0xef,0x59,0x89,0x4d] -// CHECK: st1 {v31.s}[3], [sp], x6 // encoding: [0xff,0x93,0x86,0x4d] -// CHECK: st1 {v0.d}[1], [x0], #8 // encoding: [0x00,0x84,0x9f,0x4d] + st1 { v0.b }[9], [x0], #1 + st1 { v15.h }[7], [x15], x9 + st1 { v31.s }[3], [sp], x6 + st1 { v0.d }[1], [x0], #8 +// CHECK: st1 { v0.b }[9], [x0], #1 // encoding: [0x00,0x04,0x9f,0x4d] +// CHECK: st1 { v15.h }[7], [x15], x9 // encoding: [0xef,0x59,0x89,0x4d] +// CHECK: st1 { v31.s }[3], [sp], x6 // encoding: [0xff,0x93,0x86,0x4d] +// CHECK: st1 { v0.d }[1], [x0], #8 // encoding: [0x00,0x84,0x9f,0x4d] //------------------------------------------------------------------------------ // Post-index store single N-element structure from one lane of N consecutive // registers (N = 2,3,4) //------------------------------------------------------------------------------ - st2 {v0.b, v1.b}[9], [x0], x3 - st2 {v15.h, v16.h}[7], [x15], #4 - st2 {v31.s, v0.s}[3], [sp], #8 - st2 {v0.d, v1.d}[1], [x0], x0 -// CHECK: st2 {v0.b, v1.b}[9], [x0], x3 // encoding: [0x00,0x04,0xa3,0x4d] -// CHECK: st2 {v15.h, v16.h}[7], [x15], #4 // encoding: [0xef,0x59,0xbf,0x4d] -// CHECK: st2 {v31.s, v0.s}[3], [sp], #8 // encoding: [0xff,0x93,0xbf,0x4d] -// CHECK: st2 {v0.d, v1.d}[1], [x0], x0 // encoding: [0x00,0x84,0xa0,0x4d] + st2 { v0.b, v1.b }[9], [x0], x3 + st2 { v15.h, v16.h }[7], [x15], #4 + st2 { v31.s, v0.s }[3], [sp], #8 + st2 { v0.d, v1.d }[1], [x0], x0 +// CHECK: st2 { v0.b, v1.b }[9], [x0], x3 // encoding: [0x00,0x04,0xa3,0x4d] +// CHECK: st2 { v15.h, v16.h }[7], [x15], #4 // encoding: [0xef,0x59,0xbf,0x4d] +// CHECK: st2 { v31.s, v0.s }[3], [sp], #8 // encoding: [0xff,0x93,0xbf,0x4d] +// CHECK: st2 { v0.d, v1.d }[1], [x0], x0 // encoding: [0x00,0x84,0xa0,0x4d] - st3 {v0.b, v1.b, v2.b}[9], [x0], #3 - st3 {v15.h, v16.h, v17.h}[7], [x15], #6 - st3 {v31.s, v0.s, v1.s}[3], [sp], x3 - st3 {v0.d, v1.d, v2.d}[1], [x0], x6 -// CHECK: st3 {v0.b, v1.b, v2.b}[9], [x0], #3 // encoding: [0x00,0x24,0x9f,0x4d] -// CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6 // encoding: [0xef,0x79,0x9f,0x4d] -// CHECK: st3 {v31.s, v0.s, v1.s}[3], [sp], x3 // encoding: [0xff,0xb3,0x83,0x4d] -// CHECK: st3 {v0.d, v1.d, v2.d}[1], [x0], x6 // encoding: [0x00,0xa4,0x86,0x4d] + st3 { v0.b, v1.b, v2.b }[9], [x0], #3 + st3 { v15.h, v16.h, v17.h }[7], [x15], #6 + st3 { v31.s, v0.s, v1.s }[3], [sp], x3 + st3 { v0.d, v1.d, v2.d }[1], [x0], x6 +// CHECK: st3 { v0.b, v1.b, v2.b }[9], [x0], #3 // encoding: [0x00,0x24,0x9f,0x4d] +// CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15], #6 // encoding: [0xef,0x79,0x9f,0x4d] +// CHECK: st3 { v31.s, v0.s, v1.s }[3], [sp], x3 // encoding: [0xff,0xb3,0x83,0x4d] +// CHECK: st3 { v0.d, v1.d, v2.d }[1], [x0], x6 // encoding: [0x00,0xa4,0x86,0x4d] - st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 - st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 - st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 - st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 -// CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 // encoding: [0x00,0x24,0xa5,0x4d] -// CHECK: st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 // encoding: [0xef,0x79,0xa7,0x4d] -// CHECK: st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 // encoding: [0xff,0xb3,0xbf,0x4d] -// CHECK: st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 // encoding: [0x00,0xa4,0xbf,0x4d] + st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 + st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7 + st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16 + st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 +// CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 // encoding: [0x00,0x24,0xa5,0x4d] +// CHECK: st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7 // encoding: [0xef,0x79,0xa7,0x4d] +// CHECK: st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16 // encoding: [0xff,0xb3,0xbf,0x4d] +// CHECK: st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 // encoding: [0x00,0xa4,0xbf,0x4d] diff --git a/test/MC/AArch64/neon-simd-misc.s b/test/MC/AArch64/neon-simd-misc.s index 9e0f9c5..6d1aafd 100644 --- a/test/MC/AArch64/neon-simd-misc.s +++ b/test/MC/AArch64/neon-simd-misc.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 @@ -281,8 +281,8 @@ not v0.16b, v31.16b not v1.8b, v9.8b -// CHECK: not v0.16b, v31.16b // encoding: [0xe0,0x5b,0x20,0x6e] -// CHECK: not v1.8b, v9.8b // encoding: [0x21,0x59,0x20,0x2e] +// CHECK: {{mvn|not}} v0.16b, v31.16b // encoding: [0xe0,0x5b,0x20,0x6e] +// CHECK: {{mvn|not}} v1.8b, v9.8b // encoding: [0x21,0x59,0x20,0x2e] //------------------------------------------------------------------------------ // Bitwise reverse diff --git a/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s b/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s index 8dc271e..c57a122 100644 --- a/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s +++ b/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s @@ -1,389 +1,389 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 //------------------------------------------------------------------------------ // Load multiple 1-element structures from one register (post-index) //------------------------------------------------------------------------------ - ld1 {v0.16b}, [x0], x1 - ld1 {v15.8h}, [x15], x2 - ld1 {v31.4s}, [sp], #16 - ld1 {v0.2d}, [x0], #16 - ld1 {v0.8b}, [x0], x2 - ld1 {v15.4h}, [x15], x3 - ld1 {v31.2s}, [sp], #8 - ld1 {v0.1d}, [x0], #8 -// CHECK: ld1 {v0.16b}, [x0], x1 + ld1 { v0.16b }, [x0], x1 + ld1 { v15.8h }, [x15], x2 + ld1 { v31.4s }, [sp], #16 + ld1 { v0.2d }, [x0], #16 + ld1 { v0.8b }, [x0], x2 + ld1 { v15.4h }, [x15], x3 + ld1 { v31.2s }, [sp], #8 + ld1 { v0.1d }, [x0], #8 +// CHECK: ld1 { v0.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x70,0xc1,0x4c] -// CHECK: ld1 {v15.8h}, [x15], x2 +// CHECK: ld1 { v15.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x75,0xc2,0x4c] -// CHECK: ld1 {v31.4s}, [sp], #16 +// CHECK: ld1 { v31.4s }, [sp], #16 // CHECK: // encoding: [0xff,0x7b,0xdf,0x4c] -// CHECK: ld1 {v0.2d}, [x0], #16 +// CHECK: ld1 { v0.2d }, [x0], #16 // CHECK: // encoding: [0x00,0x7c,0xdf,0x4c] -// CHECK: ld1 {v0.8b}, [x0], x2 +// CHECK: ld1 { v0.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x70,0xc2,0x0c] -// CHECK: ld1 {v15.4h}, [x15], x3 +// CHECK: ld1 { v15.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x75,0xc3,0x0c] -// CHECK: ld1 {v31.2s}, [sp], #8 +// CHECK: ld1 { v31.2s }, [sp], #8 // CHECK: // encoding: [0xff,0x7b,0xdf,0x0c] -// CHECK: ld1 {v0.1d}, [x0], #8 +// CHECK: ld1 { v0.1d }, [x0], #8 // CHECK: // encoding: [0x00,0x7c,0xdf,0x0c] //------------------------------------------------------------------------------ // Load multiple 1-element structures from two consecutive registers // (post-index) //------------------------------------------------------------------------------ - ld1 {v0.16b, v1.16b}, [x0], x1 - ld1 {v15.8h, v16.8h}, [x15], x2 - ld1 {v31.4s, v0.4s}, [sp], #32 - ld1 {v0.2d, v1.2d}, [x0], #32 - ld1 {v0.8b, v1.8b}, [x0], x2 - ld1 {v15.4h, v16.4h}, [x15], x3 - ld1 {v31.2s, v0.2s}, [sp], #16 - ld1 {v0.1d, v1.1d}, [x0], #16 -// CHECK: ld1 {v0.16b, v1.16b}, [x0], x1 + ld1 { v0.16b, v1.16b }, [x0], x1 + ld1 { v15.8h, v16.8h }, [x15], x2 + ld1 { v31.4s, v0.4s }, [sp], #32 + ld1 { v0.2d, v1.2d }, [x0], #32 + ld1 { v0.8b, v1.8b }, [x0], x2 + ld1 { v15.4h, v16.4h }, [x15], x3 + ld1 { v31.2s, v0.2s }, [sp], #16 + ld1 { v0.1d, v1.1d }, [x0], #16 +// CHECK: ld1 { v0.16b, v1.16b }, [x0], x1 // CHECK: // encoding: [0x00,0xa0,0xc1,0x4c] -// CHECK: ld1 {v15.8h, v16.8h}, [x15], x2 +// CHECK: ld1 { v15.8h, v16.8h }, [x15], x2 // CHECK: // encoding: [0xef,0xa5,0xc2,0x4c] -// CHECK: ld1 {v31.4s, v0.4s}, [sp], #32 +// CHECK: ld1 { v31.4s, v0.4s }, [sp], #32 // CHECK: // encoding: [0xff,0xab,0xdf,0x4c] -// CHECK: ld1 {v0.2d, v1.2d}, [x0], #32 +// CHECK: ld1 { v0.2d, v1.2d }, [x0], #32 // CHECK: // encoding: [0x00,0xac,0xdf,0x4c] -// CHECK: ld1 {v0.8b, v1.8b}, [x0], x2 +// CHECK: ld1 { v0.8b, v1.8b }, [x0], x2 // CHECK: // encoding: [0x00,0xa0,0xc2,0x0c] -// CHECK: ld1 {v15.4h, v16.4h}, [x15], x3 +// CHECK: ld1 { v15.4h, v16.4h }, [x15], x3 // CHECK: // encoding: [0xef,0xa5,0xc3,0x0c] -// CHECK: ld1 {v31.2s, v0.2s}, [sp], #16 +// CHECK: ld1 { v31.2s, v0.2s }, [sp], #16 // CHECK: // encoding: [0xff,0xab,0xdf,0x0c] -// CHECK: ld1 {v0.1d, v1.1d}, [x0], #16 +// CHECK: ld1 { v0.1d, v1.1d }, [x0], #16 // CHECK: // encoding: [0x00,0xac,0xdf,0x0c] //------------------------------------------------------------------------------ // Load multiple 1-element structures from three consecutive registers // (post-index) //------------------------------------------------------------------------------ - ld1 {v0.16b, v1.16b, v2.16b}, [x0], x1 - ld1 {v15.8h, v16.8h, v17.8h}, [x15], x2 - ld1 {v31.4s, v0.4s, v1.4s}, [sp], #48 - ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 - ld1 {v0.8b, v1.8b, v2.8b}, [x0], x2 - ld1 {v15.4h, v16.4h, v17.4h}, [x15], x3 - ld1 {v31.2s, v0.2s, v1.2s}, [sp], #24 - ld1 {v0.1d, v1.1d, v2.1d}, [x0], #24 -// CHECK: ld1 {v0.16b, v1.16b, v2.16b}, [x0], x1 + ld1 { v0.16b, v1.16b, v2.16b }, [x0], x1 + ld1 { v15.8h, v16.8h, v17.8h }, [x15], x2 + ld1 { v31.4s, v0.4s, v1.4s }, [sp], #48 + ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48 + ld1 { v0.8b, v1.8b, v2.8b }, [x0], x2 + ld1 { v15.4h, v16.4h, v17.4h }, [x15], x3 + ld1 { v31.2s, v0.2s, v1.2s }, [sp], #24 + ld1 { v0.1d, v1.1d, v2.1d }, [x0], #24 +// CHECK: ld1 { v0.16b, v1.16b, v2.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x60,0xc1,0x4c] -// CHECK: ld1 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: ld1 { v15.8h, v16.8h, v17.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x65,0xc2,0x4c] -// CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp], #48 // CHECK: // encoding: [0xff,0x6b,0xdf,0x4c] -// CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48 // CHECK: // encoding: [0x00,0x6c,0xdf,0x4c] -// CHECK: ld1 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: ld1 { v0.8b, v1.8b, v2.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x60,0xc2,0x0c] -// CHECK: ld1 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: ld1 { v15.4h, v16.4h, v17.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x65,0xc3,0x0c] -// CHECK: ld1 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: ld1 { v31.2s, v0.2s, v1.2s }, [sp], #24 // CHECK: // encoding: [0xff,0x6b,0xdf,0x0c] -// CHECK: ld1 {v0.1d, v1.1d, v2.1d}, [x0], #24 +// CHECK: ld1 { v0.1d, v1.1d, v2.1d }, [x0], #24 // CHECK: // encoding: [0x00,0x6c,0xdf,0x0c] //------------------------------------------------------------------------------ // Load multiple 1-element structures from four consecutive registers // (post-index) //------------------------------------------------------------------------------ - ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 - ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 - ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 - ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 - ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 - ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 - ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 - ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 -// CHECK: ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 + ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 + ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 + ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 + ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 + ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 + ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 + ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32 +// CHECK: ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x20,0xc1,0x4c] -// CHECK: ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x25,0xc2,0x4c] -// CHECK: ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 // CHECK: // encoding: [0xff,0x2b,0xdf,0x4c] -// CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 // CHECK: // encoding: [0x00,0x2c,0xdf,0x4c] -// CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 // CHECK: // encoding: [0x00,0x20,0xc3,0x0c] -// CHECK: ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 // CHECK: // encoding: [0xef,0x25,0xc4,0x0c] -// CHECK: ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 // CHECK: // encoding: [0xff,0x2b,0xdf,0x0c] -// CHECK: ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 +// CHECK: ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32 // CHECK: // encoding: [0x00,0x2c,0xdf,0x0c] //------------------------------------------------------------------------------ // Load multiple 2-element structures from two consecutive registers // (post-index) //------------------------------------------------------------------------------ - ld2 {v0.16b, v1.16b}, [x0], x1 - ld2 {v15.8h, v16.8h}, [x15], x2 - ld2 {v31.4s, v0.4s}, [sp], #32 - ld2 {v0.2d, v1.2d}, [x0], #32 - ld2 {v0.8b, v1.8b}, [x0], x2 - ld2 {v15.4h, v16.4h}, [x15], x3 - ld2 {v31.2s, v0.2s}, [sp], #16 -// CHECK: ld2 {v0.16b, v1.16b}, [x0], x1 + ld2 { v0.16b, v1.16b }, [x0], x1 + ld2 { v15.8h, v16.8h }, [x15], x2 + ld2 { v31.4s, v0.4s }, [sp], #32 + ld2 { v0.2d, v1.2d }, [x0], #32 + ld2 { v0.8b, v1.8b }, [x0], x2 + ld2 { v15.4h, v16.4h }, [x15], x3 + ld2 { v31.2s, v0.2s }, [sp], #16 +// CHECK: ld2 { v0.16b, v1.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x80,0xc1,0x4c] -// CHECK: ld2 {v15.8h, v16.8h}, [x15], x2 +// CHECK: ld2 { v15.8h, v16.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x85,0xc2,0x4c] -// CHECK: ld2 {v31.4s, v0.4s}, [sp], #32 +// CHECK: ld2 { v31.4s, v0.4s }, [sp], #32 // CHECK: // encoding: [0xff,0x8b,0xdf,0x4c] -// CHECK: ld2 {v0.2d, v1.2d}, [x0], #32 +// CHECK: ld2 { v0.2d, v1.2d }, [x0], #32 // CHECK: // encoding: [0x00,0x8c,0xdf,0x4c] -// CHECK: ld2 {v0.8b, v1.8b}, [x0], x2 +// CHECK: ld2 { v0.8b, v1.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x80,0xc2,0x0c] -// CHECK: ld2 {v15.4h, v16.4h}, [x15], x3 +// CHECK: ld2 { v15.4h, v16.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x85,0xc3,0x0c] -// CHECK: ld2 {v31.2s, v0.2s}, [sp], #16 +// CHECK: ld2 { v31.2s, v0.2s }, [sp], #16 // CHECK: // encoding: [0xff,0x8b,0xdf,0x0c] //------------------------------------------------------------------------------ // Load multiple 3-element structures from three consecutive registers // (post-index) //------------------------------------------------------------------------------ - ld3 {v0.16b, v1.16b, v2.16b}, [x0], x1 - ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 - ld3 {v31.4s, v0.4s, v1.4s}, [sp], #48 - ld3 {v0.2d, v1.2d, v2.2d}, [x0], #48 - ld3 {v0.8b, v1.8b, v2.8b}, [x0], x2 - ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3 - ld3 {v31.2s, v0.2s, v1.2s}, [sp], #24 -// CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0], x1 + ld3 { v0.16b, v1.16b, v2.16b }, [x0], x1 + ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2 + ld3 { v31.4s, v0.4s, v1.4s }, [sp], #48 + ld3 { v0.2d, v1.2d, v2.2d }, [x0], #48 + ld3 { v0.8b, v1.8b, v2.8b }, [x0], x2 + ld3 { v15.4h, v16.4h, v17.4h }, [x15], x3 + ld3 { v31.2s, v0.2s, v1.2s }, [sp], #24 +// CHECK: ld3 { v0.16b, v1.16b, v2.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x40,0xc1,0x4c] -// CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x45,0xc2,0x4c] -// CHECK: ld3 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: ld3 { v31.4s, v0.4s, v1.4s }, [sp], #48 // CHECK: // encoding: [0xff,0x4b,0xdf,0x4c] -// CHECK: ld3 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: ld3 { v0.2d, v1.2d, v2.2d }, [x0], #48 // CHECK: // encoding: [0x00,0x4c,0xdf,0x4c] -// CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: ld3 { v0.8b, v1.8b, v2.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x40,0xc2,0x0c] -// CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x45,0xc3,0x0c] -// CHECK: ld3 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: ld3 { v31.2s, v0.2s, v1.2s }, [sp], #24 // CHECK: // encoding: [0xff,0x4b,0xdf,0x0c] //------------------------------------------------------------------------------ // Load multiple 4-element structures from four consecutive registers // (post-index) //------------------------------------------------------------------------------ - ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 - ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 - ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 - ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 - ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 - ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 - ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 -// CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 + ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 + ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 + ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 + ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 + ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 + ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 +// CHECK: ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x00,0xc1,0x4c] -// CHECK: ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x05,0xc2,0x4c] -// CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 // CHECK: // encoding: [0xff,0x0b,0xdf,0x4c] -// CHECK: ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 // CHECK: // encoding: [0x00,0x0c,0xdf,0x4c] -// CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 // CHECK: // encoding: [0x00,0x00,0xc3,0x0c] -// CHECK: ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 // CHECK: // encoding: [0xef,0x05,0xc4,0x0c] -// CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 // CHECK: // encoding: [0xff,0x0b,0xdf,0x0c] //------------------------------------------------------------------------------ // Store multiple 1-element structures from one register (post-index) //------------------------------------------------------------------------------ - st1 {v0.16b}, [x0], x1 - st1 {v15.8h}, [x15], x2 - st1 {v31.4s}, [sp], #16 - st1 {v0.2d}, [x0], #16 - st1 {v0.8b}, [x0], x2 - st1 {v15.4h}, [x15], x3 - st1 {v31.2s}, [sp], #8 - st1 {v0.1d}, [x0], #8 -// CHECK: st1 {v0.16b}, [x0], x1 + st1 { v0.16b }, [x0], x1 + st1 { v15.8h }, [x15], x2 + st1 { v31.4s }, [sp], #16 + st1 { v0.2d }, [x0], #16 + st1 { v0.8b }, [x0], x2 + st1 { v15.4h }, [x15], x3 + st1 { v31.2s }, [sp], #8 + st1 { v0.1d }, [x0], #8 +// CHECK: st1 { v0.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x70,0x81,0x4c] -// CHECK: st1 {v15.8h}, [x15], x2 +// CHECK: st1 { v15.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x75,0x82,0x4c] -// CHECK: st1 {v31.4s}, [sp], #16 +// CHECK: st1 { v31.4s }, [sp], #16 // CHECK: // encoding: [0xff,0x7b,0x9f,0x4c] -// CHECK: st1 {v0.2d}, [x0], #16 +// CHECK: st1 { v0.2d }, [x0], #16 // CHECK: // encoding: [0x00,0x7c,0x9f,0x4c] -// CHECK: st1 {v0.8b}, [x0], x2 +// CHECK: st1 { v0.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x70,0x82,0x0c] -// CHECK: st1 {v15.4h}, [x15], x3 +// CHECK: st1 { v15.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x75,0x83,0x0c] -// CHECK: st1 {v31.2s}, [sp], #8 +// CHECK: st1 { v31.2s }, [sp], #8 // CHECK: // encoding: [0xff,0x7b,0x9f,0x0c] -// CHECK: st1 {v0.1d}, [x0], #8 +// CHECK: st1 { v0.1d }, [x0], #8 // CHECK: // encoding: [0x00,0x7c,0x9f,0x0c] //------------------------------------------------------------------------------ // Store multiple 1-element structures from two consecutive registers // (post-index) //------------------------------------------------------------------------------ - st1 {v0.16b, v1.16b}, [x0], x1 - st1 {v15.8h, v16.8h}, [x15], x2 - st1 {v31.4s, v0.4s}, [sp], #32 - st1 {v0.2d, v1.2d}, [x0], #32 - st1 {v0.8b, v1.8b}, [x0], x2 - st1 {v15.4h, v16.4h}, [x15], x3 - st1 {v31.2s, v0.2s}, [sp], #16 - st1 {v0.1d, v1.1d}, [x0], #16 -// CHECK: st1 {v0.16b, v1.16b}, [x0], x1 + st1 { v0.16b, v1.16b }, [x0], x1 + st1 { v15.8h, v16.8h }, [x15], x2 + st1 { v31.4s, v0.4s }, [sp], #32 + st1 { v0.2d, v1.2d }, [x0], #32 + st1 { v0.8b, v1.8b }, [x0], x2 + st1 { v15.4h, v16.4h }, [x15], x3 + st1 { v31.2s, v0.2s }, [sp], #16 + st1 { v0.1d, v1.1d }, [x0], #16 +// CHECK: st1 { v0.16b, v1.16b }, [x0], x1 // CHECK: // encoding: [0x00,0xa0,0x81,0x4c] -// CHECK: st1 {v15.8h, v16.8h}, [x15], x2 +// CHECK: st1 { v15.8h, v16.8h }, [x15], x2 // CHECK: // encoding: [0xef,0xa5,0x82,0x4c] -// CHECK: st1 {v31.4s, v0.4s}, [sp], #32 +// CHECK: st1 { v31.4s, v0.4s }, [sp], #32 // CHECK: // encoding: [0xff,0xab,0x9f,0x4c] -// CHECK: st1 {v0.2d, v1.2d}, [x0], #32 +// CHECK: st1 { v0.2d, v1.2d }, [x0], #32 // CHECK: // encoding: [0x00,0xac,0x9f,0x4c] -// CHECK: st1 {v0.8b, v1.8b}, [x0], x2 +// CHECK: st1 { v0.8b, v1.8b }, [x0], x2 // CHECK: // encoding: [0x00,0xa0,0x82,0x0c] -// CHECK: st1 {v15.4h, v16.4h}, [x15], x3 +// CHECK: st1 { v15.4h, v16.4h }, [x15], x3 // CHECK: // encoding: [0xef,0xa5,0x83,0x0c] -// CHECK: st1 {v31.2s, v0.2s}, [sp], #16 +// CHECK: st1 { v31.2s, v0.2s }, [sp], #16 // CHECK: // encoding: [0xff,0xab,0x9f,0x0c] -// CHECK: st1 {v0.1d, v1.1d}, [x0], #16 +// CHECK: st1 { v0.1d, v1.1d }, [x0], #16 // CHECK: // encoding: [0x00,0xac,0x9f,0x0c] //------------------------------------------------------------------------------ // Store multiple 1-element structures from three consecutive registers // (post-index) //------------------------------------------------------------------------------ - st1 {v0.16b, v1.16b, v2.16b}, [x0], x1 - st1 {v15.8h, v16.8h, v17.8h}, [x15], x2 - st1 {v31.4s, v0.4s, v1.4s}, [sp], #48 - st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 - st1 {v0.8b, v1.8b, v2.8b}, [x0], x2 - st1 {v15.4h, v16.4h, v17.4h}, [x15], x3 - st1 {v31.2s, v0.2s, v1.2s}, [sp], #24 - st1 {v0.1d, v1.1d, v2.1d}, [x0], #24 -// CHECK: st1 {v0.16b, v1.16b, v2.16b}, [x0], x1 + st1 { v0.16b, v1.16b, v2.16b }, [x0], x1 + st1 { v15.8h, v16.8h, v17.8h }, [x15], x2 + st1 { v31.4s, v0.4s, v1.4s }, [sp], #48 + st1 { v0.2d, v1.2d, v2.2d }, [x0], #48 + st1 { v0.8b, v1.8b, v2.8b }, [x0], x2 + st1 { v15.4h, v16.4h, v17.4h }, [x15], x3 + st1 { v31.2s, v0.2s, v1.2s }, [sp], #24 + st1 { v0.1d, v1.1d, v2.1d }, [x0], #24 +// CHECK: st1 { v0.16b, v1.16b, v2.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x60,0x81,0x4c] -// CHECK: st1 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: st1 { v15.8h, v16.8h, v17.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x65,0x82,0x4c] -// CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp], #48 // CHECK: // encoding: [0xff,0x6b,0x9f,0x4c] -// CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0], #48 // CHECK: // encoding: [0x00,0x6c,0x9f,0x4c] -// CHECK: st1 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: st1 { v0.8b, v1.8b, v2.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x60,0x82,0x0c] -// CHECK: st1 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: st1 { v15.4h, v16.4h, v17.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x65,0x83,0x0c] -// CHECK: st1 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: st1 { v31.2s, v0.2s, v1.2s }, [sp], #24 // CHECK: // encoding: [0xff,0x6b,0x9f,0x0c] -// CHECK: st1 {v0.1d, v1.1d, v2.1d}, [x0], #24 +// CHECK: st1 { v0.1d, v1.1d, v2.1d }, [x0], #24 // CHECK: // encoding: [0x00,0x6c,0x9f,0x0c] //------------------------------------------------------------------------------ // Store multiple 1-element structures from four consecutive registers // (post-index) //------------------------------------------------------------------------------ - st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 - st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 - st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 - st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 - st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 - st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 - st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 - st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 -// CHECK: st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 + st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 + st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 + st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 + st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 + st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 + st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 + st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32 +// CHECK: st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x20,0x81,0x4c] -// CHECK: st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x25,0x82,0x4c] -// CHECK: st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 // CHECK: // encoding: [0xff,0x2b,0x9f,0x4c] -// CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 // CHECK: // encoding: [0x00,0x2c,0x9f,0x4c] -// CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 // CHECK: // encoding: [0x00,0x20,0x83,0x0c] -// CHECK: st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 // CHECK: // encoding: [0xef,0x25,0x84,0x0c] -// CHECK: st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 // CHECK: // encoding: [0xff,0x2b,0x9f,0x0c] -// CHECK: st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 +// CHECK: st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32 // CHECK: // encoding: [0x00,0x2c,0x9f,0x0c] //------------------------------------------------------------------------------ // Store multiple 2-element structures from two consecutive registers // (post-index) //------------------------------------------------------------------------------ - st2 {v0.16b, v1.16b}, [x0], x1 - st2 {v15.8h, v16.8h}, [x15], x2 - st2 {v31.4s, v0.4s}, [sp], #32 - st2 {v0.2d, v1.2d}, [x0], #32 - st2 {v0.8b, v1.8b}, [x0], x2 - st2 {v15.4h, v16.4h}, [x15], x3 - st2 {v31.2s, v0.2s}, [sp], #16 -// CHECK: st2 {v0.16b, v1.16b}, [x0], x1 + st2 { v0.16b, v1.16b }, [x0], x1 + st2 { v15.8h, v16.8h }, [x15], x2 + st2 { v31.4s, v0.4s }, [sp], #32 + st2 { v0.2d, v1.2d }, [x0], #32 + st2 { v0.8b, v1.8b }, [x0], x2 + st2 { v15.4h, v16.4h }, [x15], x3 + st2 { v31.2s, v0.2s }, [sp], #16 +// CHECK: st2 { v0.16b, v1.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x80,0x81,0x4c] -// CHECK: st2 {v15.8h, v16.8h}, [x15], x2 +// CHECK: st2 { v15.8h, v16.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x85,0x82,0x4c] -// CHECK: st2 {v31.4s, v0.4s}, [sp], #32 +// CHECK: st2 { v31.4s, v0.4s }, [sp], #32 // CHECK: // encoding: [0xff,0x8b,0x9f,0x4c] -// CHECK: st2 {v0.2d, v1.2d}, [x0], #32 +// CHECK: st2 { v0.2d, v1.2d }, [x0], #32 // CHECK: // encoding: [0x00,0x8c,0x9f,0x4c] -// CHECK: st2 {v0.8b, v1.8b}, [x0], x2 +// CHECK: st2 { v0.8b, v1.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x80,0x82,0x0c] -// CHECK: st2 {v15.4h, v16.4h}, [x15], x3 +// CHECK: st2 { v15.4h, v16.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x85,0x83,0x0c] -// CHECK: st2 {v31.2s, v0.2s}, [sp], #16 +// CHECK: st2 { v31.2s, v0.2s }, [sp], #16 // CHECK: // encoding: [0xff,0x8b,0x9f,0x0c] //------------------------------------------------------------------------------ // Store multiple 3-element structures from three consecutive registers // (post-index) //------------------------------------------------------------------------------ - st3 {v0.16b, v1.16b, v2.16b}, [x0], x1 - st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 - st3 {v31.4s, v0.4s, v1.4s}, [sp], #48 - st3 {v0.2d, v1.2d, v2.2d}, [x0], #48 - st3 {v0.8b, v1.8b, v2.8b}, [x0], x2 - st3 {v15.4h, v16.4h, v17.4h}, [x15], x3 - st3 {v31.2s, v0.2s, v1.2s}, [sp], #24 -// CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0], x1 + st3 { v0.16b, v1.16b, v2.16b }, [x0], x1 + st3 { v15.8h, v16.8h, v17.8h }, [x15], x2 + st3 { v31.4s, v0.4s, v1.4s }, [sp], #48 + st3 { v0.2d, v1.2d, v2.2d }, [x0], #48 + st3 { v0.8b, v1.8b, v2.8b }, [x0], x2 + st3 { v15.4h, v16.4h, v17.4h }, [x15], x3 + st3 { v31.2s, v0.2s, v1.2s }, [sp], #24 +// CHECK: st3 { v0.16b, v1.16b, v2.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x40,0x81,0x4c] -// CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x45,0x82,0x4c] -// CHECK: st3 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: st3 { v31.4s, v0.4s, v1.4s }, [sp], #48 // CHECK: // encoding: [0xff,0x4b,0x9f,0x4c] -// CHECK: st3 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: st3 { v0.2d, v1.2d, v2.2d }, [x0], #48 // CHECK: // encoding: [0x00,0x4c,0x9f,0x4c] -// CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: st3 { v0.8b, v1.8b, v2.8b }, [x0], x2 // CHECK: // encoding: [0x00,0x40,0x82,0x0c] -// CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15], x3 // CHECK: // encoding: [0xef,0x45,0x83,0x0c] -// CHECK: st3 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: st3 { v31.2s, v0.2s, v1.2s }, [sp], #24 // CHECK: // encoding: [0xff,0x4b,0x9f,0x0c] //------------------------------------------------------------------------------ // Store multiple 4-element structures from four consecutive registers // (post-index) //------------------------------------------------------------------------------ - st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 - st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 - st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 - st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 - st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 - st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 - st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 -// CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 + st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 + st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 + st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 + st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 + st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 + st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 +// CHECK: st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1 // CHECK: // encoding: [0x00,0x00,0x81,0x4c] -// CHECK: st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2 // CHECK: // encoding: [0xef,0x05,0x82,0x4c] -// CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 // CHECK: // encoding: [0xff,0x0b,0x9f,0x4c] -// CHECK: st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64 // CHECK: // encoding: [0x00,0x0c,0x9f,0x4c] -// CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 // CHECK: // encoding: [0x00,0x00,0x83,0x0c] -// CHECK: st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4 // CHECK: // encoding: [0xef,0x05,0x84,0x0c] -// CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32 // CHECK: // encoding: [0xff,0x0b,0x9f,0x0c] diff --git a/test/MC/AArch64/neon-tbl.s b/test/MC/AArch64/neon-tbl.s index ff3e86b..bb39fa9 100644 --- a/test/MC/AArch64/neon-tbl.s +++ b/test/MC/AArch64/neon-tbl.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s // Check that the assembler can handle the documented syntax for AArch64 @@ -6,51 +6,50 @@ // Instructions across vector registers //------------------------------------------------------------------------------ - tbl v0.8b, {v1.16b}, v2.8b - tbl v0.8b, {v1.16b, v2.16b}, v2.8b - tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b - tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b - tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b - -// CHECK: tbl v0.8b, {v1.16b}, v2.8b // encoding: [0x20,0x00,0x02,0x0e] -// CHECK: tbl v0.8b, {v1.16b, v2.16b}, v2.8b // encoding: [0x20,0x20,0x02,0x0e] -// CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // encoding: [0x20,0x40,0x02,0x0e] -// CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b // encoding: [0x20,0x60,0x02,0x0e] -// CHECK: tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b // encoding: [0xe0,0x63,0x02,0x0e] - - tbl v0.16b, {v1.16b}, v2.16b - tbl v0.16b, {v1.16b, v2.16b}, v2.16b - tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b - tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b - tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b - -// CHECK: tbl v0.16b, {v1.16b}, v2.16b // encoding: [0x20,0x00,0x02,0x4e] -// CHECK: tbl v0.16b, {v1.16b, v2.16b}, v2.16b // encoding: [0x20,0x20,0x02,0x4e] -// CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b // encoding: [0x20,0x40,0x02,0x4e] -// CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b // encoding: [0x20,0x60,0x02,0x4e] -// CHECK: tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b // encoding: [0xc0,0x63,0x02,0x4e] - - tbx v0.8b, {v1.16b}, v2.8b - tbx v0.8b, {v1.16b, v2.16b}, v2.8b - tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b - tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b - tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b - -// CHECK: tbx v0.8b, {v1.16b}, v2.8b // encoding: [0x20,0x10,0x02,0x0e] -// CHECK: tbx v0.8b, {v1.16b, v2.16b}, v2.8b // encoding: [0x20,0x30,0x02,0x0e] -// CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // encoding: [0x20,0x50,0x02,0x0e] -// CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b // encoding: [0x20,0x70,0x02,0x0e] -// CHECK: tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b // encoding: [0xe0,0x73,0x02,0x0e] - - tbx v0.16b, {v1.16b}, v2.16b - tbx v0.16b, {v1.16b, v2.16b}, v2.16b - tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b - tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b - tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b - -// CHECK: tbx v0.16b, {v1.16b}, v2.16b // encoding: [0x20,0x10,0x02,0x4e] -// CHECK: tbx v0.16b, {v1.16b, v2.16b}, v2.16b // encoding: [0x20,0x30,0x02,0x4e] -// CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b // encoding: [0x20,0x50,0x02,0x4e] -// CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b // encoding: [0x20,0x70,0x02,0x4e] -// CHECK: tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b // encoding: [0xc0,0x73,0x02,0x4e] - + tbl v0.8b, { v1.16b }, v2.8b + tbl v0.8b, { v1.16b, v2.16b }, v2.8b + tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b + tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b + tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b + +// CHECK: tbl v0.8b, { v1.16b }, v2.8b // encoding: [0x20,0x00,0x02,0x0e] +// CHECK: tbl v0.8b, { v1.16b, v2.16b }, v2.8b // encoding: [0x20,0x20,0x02,0x0e] +// CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b // encoding: [0x20,0x40,0x02,0x0e] +// CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b // encoding: [0x20,0x60,0x02,0x0e] +// CHECK: tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b // encoding: [0xe0,0x63,0x02,0x0e] + + tbl v0.16b, { v1.16b }, v2.16b + tbl v0.16b, { v1.16b, v2.16b }, v2.16b + tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b + tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b + tbl v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b + +// CHECK: tbl v0.16b, { v1.16b }, v2.16b // encoding: [0x20,0x00,0x02,0x4e] +// CHECK: tbl v0.16b, { v1.16b, v2.16b }, v2.16b // encoding: [0x20,0x20,0x02,0x4e] +// CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b // encoding: [0x20,0x40,0x02,0x4e] +// CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b // encoding: [0x20,0x60,0x02,0x4e] +// CHECK: tbl v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b // encoding: [0xc0,0x63,0x02,0x4e] + + tbx v0.8b, { v1.16b }, v2.8b + tbx v0.8b, { v1.16b, v2.16b }, v2.8b + tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b + tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b + tbx v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b + +// CHECK: tbx v0.8b, { v1.16b }, v2.8b // encoding: [0x20,0x10,0x02,0x0e] +// CHECK: tbx v0.8b, { v1.16b, v2.16b }, v2.8b // encoding: [0x20,0x30,0x02,0x0e] +// CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b // encoding: [0x20,0x50,0x02,0x0e] +// CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b // encoding: [0x20,0x70,0x02,0x0e] +// CHECK: tbx v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b // encoding: [0xe0,0x73,0x02,0x0e] + + tbx v0.16b, { v1.16b }, v2.16b + tbx v0.16b, { v1.16b, v2.16b }, v2.16b + tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b + tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b + tbx v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b + +// CHECK: tbx v0.16b, { v1.16b }, v2.16b // encoding: [0x20,0x10,0x02,0x4e] +// CHECK: tbx v0.16b, { v1.16b, v2.16b }, v2.16b // encoding: [0x20,0x30,0x02,0x4e] +// CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b // encoding: [0x20,0x50,0x02,0x4e] +// CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b // encoding: [0x20,0x70,0x02,0x4e] +// CHECK: tbx v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b // encoding: [0xc0,0x73,0x02,0x4e] diff --git a/test/MC/AArch64/noneon-diagnostics.s b/test/MC/AArch64/noneon-diagnostics.s index ea786c0..60a5fd2 100644 --- a/test/MC/AArch64/noneon-diagnostics.s +++ b/test/MC/AArch64/noneon-diagnostics.s @@ -4,25 +4,26 @@ fmla v3.4s, v12.4s, v17.4s fmla v1.2d, v30.2d, v20.2d fmla v9.2s, v9.2s, v0.2s -// CHECK-ERROR: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR: error: instruction requires: neon // CHECK-ERROR-NEXT: fmla v3.4s, v12.4s, v17.4s // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR-NEXT: error: instruction requires: neon // CHECK-ERROR-NEXT: fmla v1.2d, v30.2d, v20.2d // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR-NEXT: error: instruction requires: neon // CHECK-ERROR-NEXT: fmla v9.2s, v9.2s, v0.2s // CHECK-ERROR-NEXT: ^ fmls v3.4s, v12.4s, v17.4s fmls v1.2d, v30.2d, v20.2d fmls v9.2s, v9.2s, v0.2s -// CHECK-ERROR: error: instruction requires a CPU feature not currently enabled + +// CHECK-ERROR: error: instruction requires: neon // CHECK-ERROR-NEXT: fmls v3.4s, v12.4s, v17.4s // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR-NEXT: error: instruction requires: neon // CHECK-ERROR-NEXT: fmls v1.2d, v30.2d, v20.2d // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR-NEXT: error: instruction requires: neon // CHECK-ERROR-NEXT: fmls v9.2s, v9.2s, v0.2s // CHECK-ERROR-NEXT: ^ diff --git a/test/MC/AArch64/optional-hash.s b/test/MC/AArch64/optional-hash.s index 54b6fb3..3922b5b 100644 --- a/test/MC/AArch64/optional-hash.s +++ b/test/MC/AArch64/optional-hash.s @@ -1,6 +1,6 @@ // PR18929 // RUN: llvm-mc < %s -triple=aarch64-linux-gnueabi -mattr=+fp-armv8,+neon -filetype=obj -o - \ -// RUN: | llvm-objdump --disassemble -arch=aarch64 -mattr=+fp-armv8,+neon - | FileCheck %s +// RUN: | llvm-objdump --disassemble -arch=arm64 -mattr=+fp-armv8,+neon - | FileCheck %s .text // CHECK: cmp w0, #123 diff --git a/test/MC/AArch64/tls-relocs.s b/test/MC/AArch64/tls-relocs.s index f99cb41..ebf0216 100644 --- a/test/MC/AArch64/tls-relocs.s +++ b/test/MC/AArch64/tls-relocs.s @@ -7,14 +7,15 @@ movn x2, #:dtprel_g2:var movz x3, #:dtprel_g2:var movn x4, #:dtprel_g2:var -// CHECK: movz x1, #:dtprel_g2:var // encoding: [0x01'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 -// CHECK: movn x2, #:dtprel_g2:var // encoding: [0x02'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 -// CHECK: movz x3, #:dtprel_g2:var // encoding: [0x03'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 -// CHECK: movn x4, #:dtprel_g2:var // encoding: [0x04'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 + +// CHECK: movz x1, #:dtprel_g2:var // encoding: [0bAAA00001,A,0b110AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw +// CHECK: movn x2, #:dtprel_g2:var // encoding: [0bAAA00010,A,0b110AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw +// CHECK: movz x3, #:dtprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw +// CHECK: movn x4, #:dtprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_aarch64_movw // CHECK-ELF: Relocations [ // CHECK-ELF-NEXT: Section (2) .rela.text { @@ -28,14 +29,15 @@ movn x6, #:dtprel_g1:var movz w7, #:dtprel_g1:var movn w8, #:dtprel_g1:var -// CHECK: movz x5, #:dtprel_g1:var // encoding: [0x05'A',A,0xa0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 -// CHECK: movn x6, #:dtprel_g1:var // encoding: [0x06'A',A,0xa0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 -// CHECK: movz w7, #:dtprel_g1:var // encoding: [0x07'A',A,0xa0'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 -// CHECK: movn w8, #:dtprel_g1:var // encoding: [0x08'A',A,0xa0'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 + +// CHECK: movz x5, #:dtprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movz w7, #:dtprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movn w8, #:dtprel_g1:var // encoding: [0bAAA01000,A,0b101AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x10 R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] // CHECK-ELF-NEXT: 0x14 R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] @@ -45,10 +47,11 @@ movk x9, #:dtprel_g1_nc:var movk w10, #:dtprel_g1_nc:var -// CHECK: movk x9, #:dtprel_g1_nc:var // encoding: [0x09'A',A,0xa0'A',0xf2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_a64_movw_dtprel_g1_nc -// CHECK: movk w10, #:dtprel_g1_nc:var // encoding: [0x0a'A',A,0xa0'A',0x72'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_a64_movw_dtprel_g1_nc + +// CHECK: movk x9, #:dtprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2] +// CHECK: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_aarch64_movw +// CHECK: movk w10, #:dtprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72] +// CHECK: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x20 R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]] // CHECK-ELF-NEXT: 0x24 R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]] @@ -58,13 +61,15 @@ movn x12, #:dtprel_g0:var movz w13, #:dtprel_g0:var movn w14, #:dtprel_g0:var -// CHECK: movz x11, #:dtprel_g0:var // encoding: [0x0b'A',A,0x80'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0 -// CHECK: movn x12, #:dtprel_g0:var // encoding: [0x0c'A',A,0x80'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0 -// CHECK: movz w13, #:dtprel_g0:var // encoding: [0x0d'A',A,0x80'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0 -// CHECK: movn w14, #:dtprel_g0:var // encoding: [0x0e'A',A,0x80'A',0x12'A'] + +// CHECK: movz x11, #:dtprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movn x12, #:dtprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movz w13, #:dtprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movn w14, #:dtprel_g0:var // encoding: [0bAAA01110,A,0b100AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x28 R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] // CHECK-ELF-NEXT: 0x2C R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] @@ -74,10 +79,11 @@ movk x15, #:dtprel_g0_nc:var movk w16, #:dtprel_g0_nc:var -// CHECK: movk x15, #:dtprel_g0_nc:var // encoding: [0x0f'A',A,0x80'A',0xf2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_a64_movw_dtprel_g0_nc -// CHECK: movk w16, #:dtprel_g0_nc:var // encoding: [0x10'A',A,0x80'A',0x72'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_a64_movw_dtprel_g0_nc + +// CHECK: movk x15, #:dtprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2] +// CHECK: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw +// CHECK: movk w16, #:dtprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72] +// CHECK: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x38 R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]] // CHECK-ELF-NEXT: 0x3C R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]] @@ -85,10 +91,11 @@ add x17, x18, #:dtprel_hi12:var, lsl #12 add w19, w20, #:dtprel_hi12:var, lsl #12 -// CHECK: add x17, x18, #:dtprel_hi12:var, lsl #12 // encoding: [0x51'A',0x02'A',0x40'A',0x91'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_a64_add_dtprel_hi12 -// CHECK: add w19, w20, #:dtprel_hi12:var, lsl #12 // encoding: [0x93'A',0x02'A',0x40'A',0x11'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_a64_add_dtprel_hi12 + +// CHECK: add x17, x18, :dtprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_aarch64_add_imm12 +// CHECK: add w19, w20, :dtprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b00AAAAAA,0x11] +// CHECK: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: 0x40 R_AARCH64_TLSLD_ADD_DTPREL_HI12 [[VARSYM]] // CHECK-ELF-NEXT: 0x44 R_AARCH64_TLSLD_ADD_DTPREL_HI12 [[VARSYM]] @@ -96,10 +103,11 @@ add x21, x22, #:dtprel_lo12:var add w23, w24, #:dtprel_lo12:var -// CHECK: add x21, x22, #:dtprel_lo12:var // encoding: [0xd5'A',0x02'A',A,0x91'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_add_dtprel_lo12 -// CHECK: add w23, w24, #:dtprel_lo12:var // encoding: [0x17'A',0x03'A',A,0x11'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_add_dtprel_lo12 + +// CHECK: add x21, x22, :dtprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_add_imm12 +// CHECK: add w23, w24, :dtprel_lo12:var // encoding: [0x17,0bAAAAAA11,0b00AAAAAA,0x11] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: 0x48 R_AARCH64_TLSLD_ADD_DTPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0x4C R_AARCH64_TLSLD_ADD_DTPREL_LO12 [[VARSYM]] @@ -107,10 +115,11 @@ add x25, x26, #:dtprel_lo12_nc:var add w27, w28, #:dtprel_lo12_nc:var -// CHECK: add x25, x26, #:dtprel_lo12_nc:var // encoding: [0x59'A',0x03'A',A,0x91'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_add_dtprel_lo12_nc -// CHECK: add w27, w28, #:dtprel_lo12_nc:var // encoding: [0x9b'A',0x03'A',A,0x11'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_add_dtprel_lo12_nc + +// CHECK: add x25, x26, :dtprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_add_imm12 +// CHECK: add w27, w28, :dtprel_lo12_nc:var // encoding: [0x9b,0bAAAAAA11,0b00AAAAAA,0x11] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: 0x50 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]] // CHECK-ELF-NEXT: 0x54 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]] @@ -118,10 +127,11 @@ ldrb w29, [x30, #:dtprel_lo12:var] ldrsb x29, [x28, #:dtprel_lo12_nc:var] -// CHECK: ldrb w29, [x30, #:dtprel_lo12:var] // encoding: [0xdd'A',0x03'A',0x40'A',0x39'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst8_dtprel_lo12 -// CHECK: ldrsb x29, [x28, #:dtprel_lo12_nc:var] // encoding: [0x9d'A',0x03'A',0x80'A',0x39'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst8_dtprel_lo12_nc + +// CHECK: ldrb w29, [x30, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1 +// CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1 // CHECK-ELF-NEXT: 0x58 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0x5C R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC [[VARSYM]] @@ -129,10 +139,11 @@ strh w27, [x26, #:dtprel_lo12:var] ldrsh x25, [x24, #:dtprel_lo12_nc:var] -// CHECK: strh w27, [x26, #:dtprel_lo12:var] // encoding: [0x5b'A',0x03'A',A,0x79'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst16_dtprel_lo12 -// CHECK: ldrsh x25, [x24, #:dtprel_lo12_nc:var] // encoding: [0x19'A',0x03'A',0x80'A',0x79'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst16_dtprel_lo12_n + +// CHECK: strh w27, [x26, :dtprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2 +// CHECK: ldrsh x25, [x24, :dtprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2 // CHECK-ELF-NEXT: 0x60 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0x64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC [[VARSYM]] @@ -140,10 +151,11 @@ ldr w23, [x22, #:dtprel_lo12:var] ldrsw x21, [x20, #:dtprel_lo12_nc:var] -// CHECK: ldr w23, [x22, #:dtprel_lo12:var] // encoding: [0xd7'A',0x02'A',0x40'A',0xb9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst32_dtprel_lo12 -// CHECK: ldrsw x21, [x20, #:dtprel_lo12_nc:var] // encoding: [0x95'A',0x02'A',0x80'A',0xb9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst32_dtprel_lo12_n + +// CHECK: ldr w23, [x22, :dtprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4 +// CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4 // CHECK-ELF-NEXT: 0x68 R_AARCH64_TLSLD_LDST32_DTPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0x6C R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC [[VARSYM]] @@ -151,11 +163,11 @@ ldr x19, [x18, #:dtprel_lo12:var] str x17, [x16, #:dtprel_lo12_nc:var] -// CHECK: ldr x19, [x18, #:dtprel_lo12:var] // encoding: [0x53'A',0x02'A',0x40'A',0xf9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst64_dtprel_lo12 -// CHECK: str x17, [x16, #:dtprel_lo12_nc:var] // encoding: [0x11'A',0x02'A',A,0xf9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst64_dtprel_lo12_nc +// CHECK: ldr x19, [x18, :dtprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: str x17, [x16, :dtprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8 // CHECK-ELF-NEXT: 0x70 R_AARCH64_TLSLD_LDST64_DTPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0x74 R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC [[VARSYM]] @@ -164,10 +176,11 @@ // TLS initial-exec forms movz x15, #:gottprel_g1:var movz w14, #:gottprel_g1:var -// CHECK: movz x15, #:gottprel_g1:var // encoding: [0x0f'A',A,0xa0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_a64_movw_gottprel_g1 -// CHECK: movz w14, #:gottprel_g1:var // encoding: [0x0e'A',A,0xa0'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_a64_movw_gottprel_g1 + +// CHECK: movz x15, #:gottprel_g1:var // encoding: [0bAAA01111,A,0b101AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movz w14, #:gottprel_g1:var // encoding: [0bAAA01110,A,0b101AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x78 R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 [[VARSYM]] // CHECK-ELF-NEXT: 0x7C R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 [[VARSYM]] @@ -175,10 +188,11 @@ movk x13, #:gottprel_g0_nc:var movk w12, #:gottprel_g0_nc:var -// CHECK: movk x13, #:gottprel_g0_nc:var // encoding: [0x0d'A',A,0x80'A',0xf2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_a64_movw_gottprel_g0_nc -// CHECK: movk w12, #:gottprel_g0_nc:var // encoding: [0x0c'A',A,0x80'A',0x72'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_a64_movw_gottprel_g0_nc + +// CHECK: movk x13, #:gottprel_g0_nc:var // encoding: [0bAAA01101,A,0b100AAAAA,0xf2] +// CHECK: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_aarch64_movw +// CHECK: movk w12, #:gottprel_g0_nc:var // encoding: [0bAAA01100,A,0b100AAAAA,0x72] +// CHECK: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x80 R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC [[VARSYM]] // CHECK-ELF-NEXT: 0x84 R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC [[VARSYM]] @@ -187,12 +201,13 @@ adrp x11, :gottprel:var ldr x10, [x0, #:gottprel_lo12:var] ldr x9, :gottprel:var + // CHECK: adrp x11, :gottprel:var // encoding: [0x0b'A',A,A,0x90'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_a64_adr_gottprel_page -// CHECK: ldr x10, [x0, #:gottprel_lo12:var] // encoding: [0x0a'A',A,0x40'A',0xf9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_a64_ld64_gottprel_lo12_nc -// CHECK: ldr x9, :gottprel:var // encoding: [0x09'A',A,A,0x58'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_a64_ld_gottprel_prel19 +// CHECK: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_pcrel_adrp_imm21 +// CHECK: ldr x10, [x0, :gottprel_lo12:var] // encoding: [0x0a,0bAAAAAA00,0b01AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: ldr x9, :gottprel:var // encoding: [0bAAA01001,A,A,0x58] +// CHECK: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_aarch64_ldr_pcrel_imm19 // CHECK-ELF-NEXT: 0x88 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 [[VARSYM]] // CHECK-ELF-NEXT: 0x8C R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC [[VARSYM]] @@ -202,10 +217,11 @@ // TLS local-exec forms movz x3, #:tprel_g2:var movn x4, #:tprel_g2:var -// CHECK: movz x3, #:tprel_g2:var // encoding: [0x03'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_a64_movw_tprel_g2 -// CHECK: movn x4, #:tprel_g2:var // encoding: [0x04'A',A,0xc0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_a64_movw_tprel_g2 + +// CHECK: movz x3, #:tprel_g2:var // encoding: [0bAAA00011,A,0b110AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_aarch64_movw +// CHECK: movn x4, #:tprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x94 R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]] // CHECK-ELF-NEXT: 0x98 R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]] @@ -215,14 +231,15 @@ movn x6, #:tprel_g1:var movz w7, #:tprel_g1:var movn w8, #:tprel_g1:var -// CHECK: movz x5, #:tprel_g1:var // encoding: [0x05'A',A,0xa0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 -// CHECK: movn x6, #:tprel_g1:var // encoding: [0x06'A',A,0xa0'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 -// CHECK: movz w7, #:tprel_g1:var // encoding: [0x07'A',A,0xa0'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 -// CHECK: movn w8, #:tprel_g1:var // encoding: [0x08'A',A,0xa0'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 + +// CHECK: movz x5, #:tprel_g1:var // encoding: [0bAAA00101,A,0b101AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movn x6, #:tprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movz w7, #:tprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw +// CHECK: movn w8, #:tprel_g1:var // encoding: [0bAAA01000,A,0b101AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0x9C R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]] // CHECK-ELF-NEXT: 0xA0 R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]] @@ -232,10 +249,11 @@ movk x9, #:tprel_g1_nc:var movk w10, #:tprel_g1_nc:var -// CHECK: movk x9, #:tprel_g1_nc:var // encoding: [0x09'A',A,0xa0'A',0xf2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_a64_movw_tprel_g1_nc -// CHECK: movk w10, #:tprel_g1_nc:var // encoding: [0x0a'A',A,0xa0'A',0x72'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_a64_movw_tprel_g1_nc + +// CHECK: movk x9, #:tprel_g1_nc:var // encoding: [0bAAA01001,A,0b101AAAAA,0xf2] +// CHECK: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_aarch64_movw +// CHECK: movk w10, #:tprel_g1_nc:var // encoding: [0bAAA01010,A,0b101AAAAA,0x72] +// CHECK: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0xAC R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]] // CHECK-ELF-NEXT: 0xB0 R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]] @@ -245,14 +263,15 @@ movn x12, #:tprel_g0:var movz w13, #:tprel_g0:var movn w14, #:tprel_g0:var -// CHECK: movz x11, #:tprel_g0:var // encoding: [0x0b'A',A,0x80'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 -// CHECK: movn x12, #:tprel_g0:var // encoding: [0x0c'A',A,0x80'A',0x92'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 -// CHECK: movz w13, #:tprel_g0:var // encoding: [0x0d'A',A,0x80'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 -// CHECK: movn w14, #:tprel_g0:var // encoding: [0x0e'A',A,0x80'A',0x12'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 + +// CHECK: movz x11, #:tprel_g0:var // encoding: [0bAAA01011,A,0b100AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movn x12, #:tprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92] +// CHECK: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movz w13, #:tprel_g0:var // encoding: [0bAAA01101,A,0b100AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw +// CHECK: movn w14, #:tprel_g0:var // encoding: [0bAAA01110,A,0b100AAAAA,0x12] +// CHECK: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0xB4 R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]] // CHECK-ELF-NEXT: 0xB8 R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]] @@ -262,10 +281,11 @@ movk x15, #:tprel_g0_nc:var movk w16, #:tprel_g0_nc:var -// CHECK: movk x15, #:tprel_g0_nc:var // encoding: [0x0f'A',A,0x80'A',0xf2'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_a64_movw_tprel_g0_nc -// CHECK: movk w16, #:tprel_g0_nc:var // encoding: [0x10'A',A,0x80'A',0x72'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_a64_movw_tprel_g0_nc + +// CHECK: movk x15, #:tprel_g0_nc:var // encoding: [0bAAA01111,A,0b100AAAAA,0xf2] +// CHECK: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw +// CHECK: movk w16, #:tprel_g0_nc:var // encoding: [0bAAA10000,A,0b100AAAAA,0x72] +// CHECK: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_aarch64_movw // CHECK-ELF-NEXT: 0xC4 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]] // CHECK-ELF-NEXT: 0xC8 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]] @@ -273,10 +293,11 @@ add x17, x18, #:tprel_hi12:var, lsl #12 add w19, w20, #:tprel_hi12:var, lsl #12 -// CHECK: add x17, x18, #:tprel_hi12:var, lsl #12 // encoding: [0x51'A',0x02'A',0x40'A',0x91'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_a64_add_tprel_hi12 -// CHECK: add w19, w20, #:tprel_hi12:var, lsl #12 // encoding: [0x93'A',0x02'A',0x40'A',0x11'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_a64_add_tprel_hi12 + +// CHECK: add x17, x18, :tprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_aarch64_add_imm12 +// CHECK: add w19, w20, :tprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b00AAAAAA,0x11] +// CHECK: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: 0xCC R_AARCH64_TLSLE_ADD_TPREL_HI12 [[VARSYM]] // CHECK-ELF-NEXT: 0xD0 R_AARCH64_TLSLE_ADD_TPREL_HI12 [[VARSYM]] @@ -284,10 +305,11 @@ add x21, x22, #:tprel_lo12:var add w23, w24, #:tprel_lo12:var -// CHECK: add x21, x22, #:tprel_lo12:var // encoding: [0xd5'A',0x02'A',A,0x91'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_add_tprel_lo12 -// CHECK: add w23, w24, #:tprel_lo12:var // encoding: [0x17'A',0x03'A',A,0x11'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_add_tprel_lo12 + +// CHECK: add x21, x22, :tprel_lo12:var // encoding: [0xd5,0bAAAAAA10,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_add_imm12 +// CHECK: add w23, w24, :tprel_lo12:var // encoding: [0x17,0bAAAAAA11,0b00AAAAAA,0x11] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: 0xD4 R_AARCH64_TLSLE_ADD_TPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0xD8 R_AARCH64_TLSLE_ADD_TPREL_LO12 [[VARSYM]] @@ -295,10 +317,11 @@ add x25, x26, #:tprel_lo12_nc:var add w27, w28, #:tprel_lo12_nc:var -// CHECK: add x25, x26, #:tprel_lo12_nc:var // encoding: [0x59'A',0x03'A',A,0x91'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_add_tprel_lo12_nc -// CHECK: add w27, w28, #:tprel_lo12_nc:var // encoding: [0x9b'A',0x03'A',A,0x11'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_add_tprel_lo12_nc + +// CHECK: add x25, x26, :tprel_lo12_nc:var // encoding: [0x59,0bAAAAAA11,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_add_imm12 +// CHECK: add w27, w28, :tprel_lo12_nc:var // encoding: [0x9b,0bAAAAAA11,0b00AAAAAA,0x11] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_add_imm12 // CHECK-ELF-NEXT: 0xDC R_AARCH64_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]] // CHECK-ELF-NEXT: 0xE0 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]] @@ -306,10 +329,11 @@ ldrb w29, [x30, #:tprel_lo12:var] ldrsb x29, [x28, #:tprel_lo12_nc:var] -// CHECK: ldrb w29, [x30, #:tprel_lo12:var] // encoding: [0xdd'A',0x03'A',0x40'A',0x39'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst8_tprel_lo12 -// CHECK: ldrsb x29, [x28, #:tprel_lo12_nc:var] // encoding: [0x9d'A',0x03'A',0x80'A',0x39'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst8_tprel_lo12_nc + +// CHECK: ldrb w29, [x30, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale1 +// CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale1 // CHECK-ELF-NEXT: 0xE4 R_AARCH64_TLSLE_LDST8_TPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0xE8 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC [[VARSYM]] @@ -317,10 +341,11 @@ strh w27, [x26, #:tprel_lo12:var] ldrsh x25, [x24, #:tprel_lo12_nc:var] -// CHECK: strh w27, [x26, #:tprel_lo12:var] // encoding: [0x5b'A',0x03'A',A,0x79'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst16_tprel_lo12 -// CHECK: ldrsh x25, [x24, #:tprel_lo12_nc:var] // encoding: [0x19'A',0x03'A',0x80'A',0x79'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst16_tprel_lo12_n + +// CHECK: strh w27, [x26, :tprel_lo12:var] // encoding: [0x5b,0bAAAAAA11,0b00AAAAAA,0x79] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale2 +// CHECK: ldrsh x25, [x24, :tprel_lo12_nc:var] // encoding: [0x19,0bAAAAAA11,0b10AAAAAA,0x79] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale2 // CHECK-ELF-NEXT: 0xEC R_AARCH64_TLSLE_LDST16_TPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0xF0 R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC [[VARSYM]] @@ -328,20 +353,22 @@ ldr w23, [x22, #:tprel_lo12:var] ldrsw x21, [x20, #:tprel_lo12_nc:var] -// CHECK: ldr w23, [x22, #:tprel_lo12:var] // encoding: [0xd7'A',0x02'A',0x40'A',0xb9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst32_tprel_lo12 -// CHECK: ldrsw x21, [x20, #:tprel_lo12_nc:var] // encoding: [0x95'A',0x02'A',0x80'A',0xb9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst32_tprel_lo12_n + +// CHECK: ldr w23, [x22, :tprel_lo12:var] // encoding: [0xd7,0bAAAAAA10,0b01AAAAAA,0xb9] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale4 +// CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale4 // CHECK-ELF-NEXT: 0xF4 R_AARCH64_TLSLE_LDST32_TPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0xF8 R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC [[VARSYM]] ldr x19, [x18, #:tprel_lo12:var] str x17, [x16, #:tprel_lo12_nc:var] -// CHECK: ldr x19, [x18, #:tprel_lo12:var] // encoding: [0x53'A',0x02'A',0x40'A',0xf9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst64_tprel_lo12 -// CHECK: str x17, [x16, #:tprel_lo12_nc:var] // encoding: [0x11'A',0x02'A',A,0xf9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst64_tprel_lo12_nc + +// CHECK: ldr x19, [x18, :tprel_lo12:var] // encoding: [0x53,0bAAAAAA10,0b01AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: str x17, [x16, :tprel_lo12_nc:var] // encoding: [0x11,0bAAAAAA10,0b00AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_aarch64_ldst_imm12_scale8 // CHECK-ELF-NEXT: 0xFC R_AARCH64_TLSLE_LDST64_TPREL_LO12 [[VARSYM]] // CHECK-ELF-NEXT: 0x100 R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC [[VARSYM]] @@ -353,16 +380,16 @@ .tlsdesccall var blr x3 + // CHECK: adrp x8, :tlsdesc:var // encoding: [0x08'A',A,A,0x90'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_a64_tlsdesc_adr_page -// CHECK: ldr x7, [x6, #:tlsdesc_lo12:var] // encoding: [0xc7'A',A,0x40'A',0xf9'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_a64_tlsdesc_ld64_lo12_nc -// CHECK: add x5, x4, #:tlsdesc_lo12:var // encoding: [0x85'A',A,A,0x91'A'] -// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_a64_tlsdesc_add_lo12_nc +// CHECK: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_aarch64_pcrel_adrp_imm21 +// CHECK: ldr x7, [x6, :tlsdesc_lo12:var] // encoding: [0xc7,0bAAAAAA00,0b01AAAAAA,0xf9] +// CHECK: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_ldst_imm12_scale8 +// CHECK: add x5, x4, :tlsdesc_lo12:var // encoding: [0x85,0bAAAAAA00,0b00AAAAAA,0x91] +// CHECK: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_aarch64_add_imm12 // CHECK: .tlsdesccall var // encoding: [] -// CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_a64_tlsdesc_call -// CHECK: blr x3 // encoding: [0x60,0x00,0x3f,0xd6] - +// CHECK: // fixup A - offset: 0, value: var, kind: fixup_aarch64_tlsdesc_call +// CHECK: blr x3 // encoding: [0x60,0x00,0x3f,0xd6] // CHECK-ELF-NEXT: 0x104 R_AARCH64_TLSDESC_ADR_PAGE [[VARSYM]] // CHECK-ELF-NEXT: 0x108 R_AARCH64_TLSDESC_LD64_LO12_NC [[VARSYM]] @@ -374,7 +401,7 @@ // CHECK-ELF: Symbols [ // CHECK-ELF: Symbol { -// CHECK-ELF: Name: var (6) +// CHECK-ELF: Name: var // CHECK-ELF-NEXT: Value: // CHECK-ELF-NEXT: Size: // CHECK-ELF-NEXT: Binding: Global diff --git a/test/MC/AArch64/trace-regs.s b/test/MC/AArch64/trace-regs.s index f9ab4c9..92f16cd 100644 --- a/test/MC/AArch64/trace-regs.s +++ b/test/MC/AArch64/trace-regs.s @@ -1,4 +1,5 @@ // RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s + mrs x8, trcstatr mrs x9, trcidr8 mrs x11, trcidr9 @@ -207,214 +208,214 @@ mrs x22, trcitctrl mrs x23, trcclaimset mrs x14, trcclaimclr -// CHECK: mrs x8, trcstatr // encoding: [0x08,0x03,0x31,0xd5] -// CHECK: mrs x9, trcidr8 // encoding: [0xc9,0x00,0x31,0xd5] -// CHECK: mrs x11, trcidr9 // encoding: [0xcb,0x01,0x31,0xd5] -// CHECK: mrs x25, trcidr10 // encoding: [0xd9,0x02,0x31,0xd5] -// CHECK: mrs x7, trcidr11 // encoding: [0xc7,0x03,0x31,0xd5] -// CHECK: mrs x7, trcidr12 // encoding: [0xc7,0x04,0x31,0xd5] -// CHECK: mrs x6, trcidr13 // encoding: [0xc6,0x05,0x31,0xd5] -// CHECK: mrs x27, trcidr0 // encoding: [0xfb,0x08,0x31,0xd5] -// CHECK: mrs x29, trcidr1 // encoding: [0xfd,0x09,0x31,0xd5] -// CHECK: mrs x4, trcidr2 // encoding: [0xe4,0x0a,0x31,0xd5] -// CHECK: mrs x8, trcidr3 // encoding: [0xe8,0x0b,0x31,0xd5] -// CHECK: mrs x15, trcidr4 // encoding: [0xef,0x0c,0x31,0xd5] -// CHECK: mrs x20, trcidr5 // encoding: [0xf4,0x0d,0x31,0xd5] -// CHECK: mrs x6, trcidr6 // encoding: [0xe6,0x0e,0x31,0xd5] -// CHECK: mrs x6, trcidr7 // encoding: [0xe6,0x0f,0x31,0xd5] -// CHECK: mrs x24, trcoslsr // encoding: [0x98,0x11,0x31,0xd5] -// CHECK: mrs x18, trcpdsr // encoding: [0x92,0x15,0x31,0xd5] -// CHECK: mrs x28, trcdevaff0 // encoding: [0xdc,0x7a,0x31,0xd5] -// CHECK: mrs x5, trcdevaff1 // encoding: [0xc5,0x7b,0x31,0xd5] -// CHECK: mrs x5, trclsr // encoding: [0xc5,0x7d,0x31,0xd5] -// CHECK: mrs x11, trcauthstatus // encoding: [0xcb,0x7e,0x31,0xd5] -// CHECK: mrs x13, trcdevarch // encoding: [0xcd,0x7f,0x31,0xd5] -// CHECK: mrs x18, trcdevid // encoding: [0xf2,0x72,0x31,0xd5] -// CHECK: mrs x22, trcdevtype // encoding: [0xf6,0x73,0x31,0xd5] -// CHECK: mrs x14, trcpidr4 // encoding: [0xee,0x74,0x31,0xd5] -// CHECK: mrs x5, trcpidr5 // encoding: [0xe5,0x75,0x31,0xd5] -// CHECK: mrs x5, trcpidr6 // encoding: [0xe5,0x76,0x31,0xd5] -// CHECK: mrs x9, trcpidr7 // encoding: [0xe9,0x77,0x31,0xd5] -// CHECK: mrs x15, trcpidr0 // encoding: [0xef,0x78,0x31,0xd5] -// CHECK: mrs x6, trcpidr1 // encoding: [0xe6,0x79,0x31,0xd5] -// CHECK: mrs x11, trcpidr2 // encoding: [0xeb,0x7a,0x31,0xd5] -// CHECK: mrs x20, trcpidr3 // encoding: [0xf4,0x7b,0x31,0xd5] -// CHECK: mrs x17, trccidr0 // encoding: [0xf1,0x7c,0x31,0xd5] -// CHECK: mrs x2, trccidr1 // encoding: [0xe2,0x7d,0x31,0xd5] -// CHECK: mrs x20, trccidr2 // encoding: [0xf4,0x7e,0x31,0xd5] -// CHECK: mrs x4, trccidr3 // encoding: [0xe4,0x7f,0x31,0xd5] -// CHECK: mrs x11, trcprgctlr // encoding: [0x0b,0x01,0x31,0xd5] -// CHECK: mrs x23, trcprocselr // encoding: [0x17,0x02,0x31,0xd5] -// CHECK: mrs x13, trcconfigr // encoding: [0x0d,0x04,0x31,0xd5] -// CHECK: mrs x23, trcauxctlr // encoding: [0x17,0x06,0x31,0xd5] -// CHECK: mrs x9, trceventctl0r // encoding: [0x09,0x08,0x31,0xd5] -// CHECK: mrs x16, trceventctl1r // encoding: [0x10,0x09,0x31,0xd5] -// CHECK: mrs x4, trcstallctlr // encoding: [0x04,0x0b,0x31,0xd5] -// CHECK: mrs x14, trctsctlr // encoding: [0x0e,0x0c,0x31,0xd5] -// CHECK: mrs x24, trcsyncpr // encoding: [0x18,0x0d,0x31,0xd5] -// CHECK: mrs x28, trcccctlr // encoding: [0x1c,0x0e,0x31,0xd5] -// CHECK: mrs x15, trcbbctlr // encoding: [0x0f,0x0f,0x31,0xd5] -// CHECK: mrs x1, trctraceidr // encoding: [0x21,0x00,0x31,0xd5] -// CHECK: mrs x20, trcqctlr // encoding: [0x34,0x01,0x31,0xd5] -// CHECK: mrs x2, trcvictlr // encoding: [0x42,0x00,0x31,0xd5] -// CHECK: mrs x12, trcviiectlr // encoding: [0x4c,0x01,0x31,0xd5] -// CHECK: mrs x16, trcvissctlr // encoding: [0x50,0x02,0x31,0xd5] -// CHECK: mrs x8, trcvipcssctlr // encoding: [0x48,0x03,0x31,0xd5] -// CHECK: mrs x27, trcvdctlr // encoding: [0x5b,0x08,0x31,0xd5] -// CHECK: mrs x9, trcvdsacctlr // encoding: [0x49,0x09,0x31,0xd5] -// CHECK: mrs x0, trcvdarcctlr // encoding: [0x40,0x0a,0x31,0xd5] -// CHECK: mrs x13, trcseqevr0 // encoding: [0x8d,0x00,0x31,0xd5] -// CHECK: mrs x11, trcseqevr1 // encoding: [0x8b,0x01,0x31,0xd5] -// CHECK: mrs x26, trcseqevr2 // encoding: [0x9a,0x02,0x31,0xd5] -// CHECK: mrs x14, trcseqrstevr // encoding: [0x8e,0x06,0x31,0xd5] -// CHECK: mrs x4, trcseqstr // encoding: [0x84,0x07,0x31,0xd5] -// CHECK: mrs x17, trcextinselr // encoding: [0x91,0x08,0x31,0xd5] -// CHECK: mrs x21, trccntrldvr0 // encoding: [0xb5,0x00,0x31,0xd5] -// CHECK: mrs x10, trccntrldvr1 // encoding: [0xaa,0x01,0x31,0xd5] -// CHECK: mrs x20, trccntrldvr2 // encoding: [0xb4,0x02,0x31,0xd5] -// CHECK: mrs x5, trccntrldvr3 // encoding: [0xa5,0x03,0x31,0xd5] -// CHECK: mrs x17, trccntctlr0 // encoding: [0xb1,0x04,0x31,0xd5] -// CHECK: mrs x1, trccntctlr1 // encoding: [0xa1,0x05,0x31,0xd5] -// CHECK: mrs x17, trccntctlr2 // encoding: [0xb1,0x06,0x31,0xd5] -// CHECK: mrs x6, trccntctlr3 // encoding: [0xa6,0x07,0x31,0xd5] -// CHECK: mrs x28, trccntvr0 // encoding: [0xbc,0x08,0x31,0xd5] -// CHECK: mrs x23, trccntvr1 // encoding: [0xb7,0x09,0x31,0xd5] -// CHECK: mrs x9, trccntvr2 // encoding: [0xa9,0x0a,0x31,0xd5] -// CHECK: mrs x6, trccntvr3 // encoding: [0xa6,0x0b,0x31,0xd5] -// CHECK: mrs x24, trcimspec0 // encoding: [0xf8,0x00,0x31,0xd5] -// CHECK: mrs x24, trcimspec1 // encoding: [0xf8,0x01,0x31,0xd5] -// CHECK: mrs x15, trcimspec2 // encoding: [0xef,0x02,0x31,0xd5] -// CHECK: mrs x10, trcimspec3 // encoding: [0xea,0x03,0x31,0xd5] -// CHECK: mrs x29, trcimspec4 // encoding: [0xfd,0x04,0x31,0xd5] -// CHECK: mrs x18, trcimspec5 // encoding: [0xf2,0x05,0x31,0xd5] -// CHECK: mrs x29, trcimspec6 // encoding: [0xfd,0x06,0x31,0xd5] -// CHECK: mrs x2, trcimspec7 // encoding: [0xe2,0x07,0x31,0xd5] -// CHECK: mrs x8, trcrsctlr2 // encoding: [0x08,0x12,0x31,0xd5] -// CHECK: mrs x0, trcrsctlr3 // encoding: [0x00,0x13,0x31,0xd5] -// CHECK: mrs x12, trcrsctlr4 // encoding: [0x0c,0x14,0x31,0xd5] -// CHECK: mrs x26, trcrsctlr5 // encoding: [0x1a,0x15,0x31,0xd5] -// CHECK: mrs x29, trcrsctlr6 // encoding: [0x1d,0x16,0x31,0xd5] -// CHECK: mrs x17, trcrsctlr7 // encoding: [0x11,0x17,0x31,0xd5] -// CHECK: mrs x0, trcrsctlr8 // encoding: [0x00,0x18,0x31,0xd5] -// CHECK: mrs x1, trcrsctlr9 // encoding: [0x01,0x19,0x31,0xd5] -// CHECK: mrs x17, trcrsctlr10 // encoding: [0x11,0x1a,0x31,0xd5] -// CHECK: mrs x21, trcrsctlr11 // encoding: [0x15,0x1b,0x31,0xd5] -// CHECK: mrs x1, trcrsctlr12 // encoding: [0x01,0x1c,0x31,0xd5] -// CHECK: mrs x8, trcrsctlr13 // encoding: [0x08,0x1d,0x31,0xd5] -// CHECK: mrs x24, trcrsctlr14 // encoding: [0x18,0x1e,0x31,0xd5] -// CHECK: mrs x0, trcrsctlr15 // encoding: [0x00,0x1f,0x31,0xd5] -// CHECK: mrs x2, trcrsctlr16 // encoding: [0x22,0x10,0x31,0xd5] -// CHECK: mrs x29, trcrsctlr17 // encoding: [0x3d,0x11,0x31,0xd5] -// CHECK: mrs x22, trcrsctlr18 // encoding: [0x36,0x12,0x31,0xd5] -// CHECK: mrs x6, trcrsctlr19 // encoding: [0x26,0x13,0x31,0xd5] -// CHECK: mrs x26, trcrsctlr20 // encoding: [0x3a,0x14,0x31,0xd5] -// CHECK: mrs x26, trcrsctlr21 // encoding: [0x3a,0x15,0x31,0xd5] -// CHECK: mrs x4, trcrsctlr22 // encoding: [0x24,0x16,0x31,0xd5] -// CHECK: mrs x12, trcrsctlr23 // encoding: [0x2c,0x17,0x31,0xd5] -// CHECK: mrs x1, trcrsctlr24 // encoding: [0x21,0x18,0x31,0xd5] -// CHECK: mrs x0, trcrsctlr25 // encoding: [0x20,0x19,0x31,0xd5] -// CHECK: mrs x17, trcrsctlr26 // encoding: [0x31,0x1a,0x31,0xd5] -// CHECK: mrs x8, trcrsctlr27 // encoding: [0x28,0x1b,0x31,0xd5] -// CHECK: mrs x10, trcrsctlr28 // encoding: [0x2a,0x1c,0x31,0xd5] -// CHECK: mrs x25, trcrsctlr29 // encoding: [0x39,0x1d,0x31,0xd5] -// CHECK: mrs x12, trcrsctlr30 // encoding: [0x2c,0x1e,0x31,0xd5] -// CHECK: mrs x11, trcrsctlr31 // encoding: [0x2b,0x1f,0x31,0xd5] -// CHECK: mrs x18, trcssccr0 // encoding: [0x52,0x10,0x31,0xd5] -// CHECK: mrs x12, trcssccr1 // encoding: [0x4c,0x11,0x31,0xd5] -// CHECK: mrs x3, trcssccr2 // encoding: [0x43,0x12,0x31,0xd5] -// CHECK: mrs x2, trcssccr3 // encoding: [0x42,0x13,0x31,0xd5] -// CHECK: mrs x21, trcssccr4 // encoding: [0x55,0x14,0x31,0xd5] -// CHECK: mrs x10, trcssccr5 // encoding: [0x4a,0x15,0x31,0xd5] -// CHECK: mrs x22, trcssccr6 // encoding: [0x56,0x16,0x31,0xd5] -// CHECK: mrs x23, trcssccr7 // encoding: [0x57,0x17,0x31,0xd5] -// CHECK: mrs x23, trcsscsr0 // encoding: [0x57,0x18,0x31,0xd5] -// CHECK: mrs x19, trcsscsr1 // encoding: [0x53,0x19,0x31,0xd5] -// CHECK: mrs x25, trcsscsr2 // encoding: [0x59,0x1a,0x31,0xd5] -// CHECK: mrs x17, trcsscsr3 // encoding: [0x51,0x1b,0x31,0xd5] -// CHECK: mrs x19, trcsscsr4 // encoding: [0x53,0x1c,0x31,0xd5] -// CHECK: mrs x11, trcsscsr5 // encoding: [0x4b,0x1d,0x31,0xd5] -// CHECK: mrs x5, trcsscsr6 // encoding: [0x45,0x1e,0x31,0xd5] -// CHECK: mrs x9, trcsscsr7 // encoding: [0x49,0x1f,0x31,0xd5] -// CHECK: mrs x1, trcsspcicr0 // encoding: [0x61,0x10,0x31,0xd5] -// CHECK: mrs x12, trcsspcicr1 // encoding: [0x6c,0x11,0x31,0xd5] -// CHECK: mrs x21, trcsspcicr2 // encoding: [0x75,0x12,0x31,0xd5] -// CHECK: mrs x11, trcsspcicr3 // encoding: [0x6b,0x13,0x31,0xd5] -// CHECK: mrs x3, trcsspcicr4 // encoding: [0x63,0x14,0x31,0xd5] -// CHECK: mrs x9, trcsspcicr5 // encoding: [0x69,0x15,0x31,0xd5] -// CHECK: mrs x5, trcsspcicr6 // encoding: [0x65,0x16,0x31,0xd5] -// CHECK: mrs x2, trcsspcicr7 // encoding: [0x62,0x17,0x31,0xd5] -// CHECK: mrs x26, trcpdcr // encoding: [0x9a,0x14,0x31,0xd5] -// CHECK: mrs x8, trcacvr0 // encoding: [0x08,0x20,0x31,0xd5] -// CHECK: mrs x15, trcacvr1 // encoding: [0x0f,0x22,0x31,0xd5] -// CHECK: mrs x19, trcacvr2 // encoding: [0x13,0x24,0x31,0xd5] -// CHECK: mrs x8, trcacvr3 // encoding: [0x08,0x26,0x31,0xd5] -// CHECK: mrs x28, trcacvr4 // encoding: [0x1c,0x28,0x31,0xd5] -// CHECK: mrs x3, trcacvr5 // encoding: [0x03,0x2a,0x31,0xd5] -// CHECK: mrs x25, trcacvr6 // encoding: [0x19,0x2c,0x31,0xd5] -// CHECK: mrs x24, trcacvr7 // encoding: [0x18,0x2e,0x31,0xd5] -// CHECK: mrs x6, trcacvr8 // encoding: [0x26,0x20,0x31,0xd5] -// CHECK: mrs x3, trcacvr9 // encoding: [0x23,0x22,0x31,0xd5] -// CHECK: mrs x24, trcacvr10 // encoding: [0x38,0x24,0x31,0xd5] -// CHECK: mrs x3, trcacvr11 // encoding: [0x23,0x26,0x31,0xd5] -// CHECK: mrs x12, trcacvr12 // encoding: [0x2c,0x28,0x31,0xd5] -// CHECK: mrs x9, trcacvr13 // encoding: [0x29,0x2a,0x31,0xd5] -// CHECK: mrs x14, trcacvr14 // encoding: [0x2e,0x2c,0x31,0xd5] -// CHECK: mrs x3, trcacvr15 // encoding: [0x23,0x2e,0x31,0xd5] -// CHECK: mrs x21, trcacatr0 // encoding: [0x55,0x20,0x31,0xd5] -// CHECK: mrs x26, trcacatr1 // encoding: [0x5a,0x22,0x31,0xd5] -// CHECK: mrs x8, trcacatr2 // encoding: [0x48,0x24,0x31,0xd5] -// CHECK: mrs x22, trcacatr3 // encoding: [0x56,0x26,0x31,0xd5] -// CHECK: mrs x6, trcacatr4 // encoding: [0x46,0x28,0x31,0xd5] -// CHECK: mrs x29, trcacatr5 // encoding: [0x5d,0x2a,0x31,0xd5] -// CHECK: mrs x5, trcacatr6 // encoding: [0x45,0x2c,0x31,0xd5] -// CHECK: mrs x18, trcacatr7 // encoding: [0x52,0x2e,0x31,0xd5] -// CHECK: mrs x2, trcacatr8 // encoding: [0x62,0x20,0x31,0xd5] -// CHECK: mrs x19, trcacatr9 // encoding: [0x73,0x22,0x31,0xd5] -// CHECK: mrs x13, trcacatr10 // encoding: [0x6d,0x24,0x31,0xd5] -// CHECK: mrs x25, trcacatr11 // encoding: [0x79,0x26,0x31,0xd5] -// CHECK: mrs x18, trcacatr12 // encoding: [0x72,0x28,0x31,0xd5] -// CHECK: mrs x29, trcacatr13 // encoding: [0x7d,0x2a,0x31,0xd5] -// CHECK: mrs x9, trcacatr14 // encoding: [0x69,0x2c,0x31,0xd5] -// CHECK: mrs x18, trcacatr15 // encoding: [0x72,0x2e,0x31,0xd5] -// CHECK: mrs x29, trcdvcvr0 // encoding: [0x9d,0x20,0x31,0xd5] -// CHECK: mrs x15, trcdvcvr1 // encoding: [0x8f,0x24,0x31,0xd5] -// CHECK: mrs x15, trcdvcvr2 // encoding: [0x8f,0x28,0x31,0xd5] -// CHECK: mrs x15, trcdvcvr3 // encoding: [0x8f,0x2c,0x31,0xd5] -// CHECK: mrs x19, trcdvcvr4 // encoding: [0xb3,0x20,0x31,0xd5] -// CHECK: mrs x22, trcdvcvr5 // encoding: [0xb6,0x24,0x31,0xd5] -// CHECK: mrs x27, trcdvcvr6 // encoding: [0xbb,0x28,0x31,0xd5] -// CHECK: mrs x1, trcdvcvr7 // encoding: [0xa1,0x2c,0x31,0xd5] -// CHECK: mrs x29, trcdvcmr0 // encoding: [0xdd,0x20,0x31,0xd5] -// CHECK: mrs x9, trcdvcmr1 // encoding: [0xc9,0x24,0x31,0xd5] -// CHECK: mrs x1, trcdvcmr2 // encoding: [0xc1,0x28,0x31,0xd5] -// CHECK: mrs x2, trcdvcmr3 // encoding: [0xc2,0x2c,0x31,0xd5] -// CHECK: mrs x5, trcdvcmr4 // encoding: [0xe5,0x20,0x31,0xd5] -// CHECK: mrs x21, trcdvcmr5 // encoding: [0xf5,0x24,0x31,0xd5] -// CHECK: mrs x5, trcdvcmr6 // encoding: [0xe5,0x28,0x31,0xd5] -// CHECK: mrs x1, trcdvcmr7 // encoding: [0xe1,0x2c,0x31,0xd5] -// CHECK: mrs x21, trccidcvr0 // encoding: [0x15,0x30,0x31,0xd5] -// CHECK: mrs x24, trccidcvr1 // encoding: [0x18,0x32,0x31,0xd5] -// CHECK: mrs x24, trccidcvr2 // encoding: [0x18,0x34,0x31,0xd5] -// CHECK: mrs x12, trccidcvr3 // encoding: [0x0c,0x36,0x31,0xd5] -// CHECK: mrs x10, trccidcvr4 // encoding: [0x0a,0x38,0x31,0xd5] -// CHECK: mrs x9, trccidcvr5 // encoding: [0x09,0x3a,0x31,0xd5] -// CHECK: mrs x6, trccidcvr6 // encoding: [0x06,0x3c,0x31,0xd5] -// CHECK: mrs x20, trccidcvr7 // encoding: [0x14,0x3e,0x31,0xd5] -// CHECK: mrs x20, trcvmidcvr0 // encoding: [0x34,0x30,0x31,0xd5] -// CHECK: mrs x20, trcvmidcvr1 // encoding: [0x34,0x32,0x31,0xd5] -// CHECK: mrs x26, trcvmidcvr2 // encoding: [0x3a,0x34,0x31,0xd5] -// CHECK: mrs x1, trcvmidcvr3 // encoding: [0x21,0x36,0x31,0xd5] -// CHECK: mrs x14, trcvmidcvr4 // encoding: [0x2e,0x38,0x31,0xd5] -// CHECK: mrs x27, trcvmidcvr5 // encoding: [0x3b,0x3a,0x31,0xd5] -// CHECK: mrs x29, trcvmidcvr6 // encoding: [0x3d,0x3c,0x31,0xd5] -// CHECK: mrs x17, trcvmidcvr7 // encoding: [0x31,0x3e,0x31,0xd5] -// CHECK: mrs x10, trccidcctlr0 // encoding: [0x4a,0x30,0x31,0xd5] -// CHECK: mrs x4, trccidcctlr1 // encoding: [0x44,0x31,0x31,0xd5] -// CHECK: mrs x9, trcvmidcctlr0 // encoding: [0x49,0x32,0x31,0xd5] -// CHECK: mrs x11, trcvmidcctlr1 // encoding: [0x4b,0x33,0x31,0xd5] -// CHECK: mrs x22, trcitctrl // encoding: [0x96,0x70,0x31,0xd5] -// CHECK: mrs x23, trcclaimset // encoding: [0xd7,0x78,0x31,0xd5] -// CHECK: mrs x14, trcclaimclr // encoding: [0xce,0x79,0x31,0xd5] +// CHECK: mrs x8, {{trcstatr|TRCSTATR}} // encoding: [0x08,0x03,0x31,0xd5] +// CHECK: mrs x9, {{trcidr8|TRCIDR8}} // encoding: [0xc9,0x00,0x31,0xd5] +// CHECK: mrs x11, {{trcidr9|TRCIDR9}} // encoding: [0xcb,0x01,0x31,0xd5] +// CHECK: mrs x25, {{trcidr10|TRCIDR10}} // encoding: [0xd9,0x02,0x31,0xd5] +// CHECK: mrs x7, {{trcidr11|TRCIDR11}} // encoding: [0xc7,0x03,0x31,0xd5] +// CHECK: mrs x7, {{trcidr12|TRCIDR12}} // encoding: [0xc7,0x04,0x31,0xd5] +// CHECK: mrs x6, {{trcidr13|TRCIDR13}} // encoding: [0xc6,0x05,0x31,0xd5] +// CHECK: mrs x27, {{trcidr0|TRCIDR0}} // encoding: [0xfb,0x08,0x31,0xd5] +// CHECK: mrs x29, {{trcidr1|TRCIDR1}} // encoding: [0xfd,0x09,0x31,0xd5] +// CHECK: mrs x4, {{trcidr2|TRCIDR2}} // encoding: [0xe4,0x0a,0x31,0xd5] +// CHECK: mrs x8, {{trcidr3|TRCIDR3}} // encoding: [0xe8,0x0b,0x31,0xd5] +// CHECK: mrs x15, {{trcidr4|TRCIDR4}} // encoding: [0xef,0x0c,0x31,0xd5] +// CHECK: mrs x20, {{trcidr5|TRCIDR5}} // encoding: [0xf4,0x0d,0x31,0xd5] +// CHECK: mrs x6, {{trcidr6|TRCIDR6}} // encoding: [0xe6,0x0e,0x31,0xd5] +// CHECK: mrs x6, {{trcidr7|TRCIDR7}} // encoding: [0xe6,0x0f,0x31,0xd5] +// CHECK: mrs x24, {{trcoslsr|TRCOSLSR}} // encoding: [0x98,0x11,0x31,0xd5] +// CHECK: mrs x18, {{trcpdsr|TRCPDSR}} // encoding: [0x92,0x15,0x31,0xd5] +// CHECK: mrs x28, {{trcdevaff0|TRCDEVAFF0}} // encoding: [0xdc,0x7a,0x31,0xd5] +// CHECK: mrs x5, {{trcdevaff1|TRCDEVAFF1}} // encoding: [0xc5,0x7b,0x31,0xd5] +// CHECK: mrs x5, {{trclsr|TRCLSR}} // encoding: [0xc5,0x7d,0x31,0xd5] +// CHECK: mrs x11, {{trcauthstatus|TRCAUTHSTATUS}} // encoding: [0xcb,0x7e,0x31,0xd5] +// CHECK: mrs x13, {{trcdevarch|TRCDEVARCH}} // encoding: [0xcd,0x7f,0x31,0xd5] +// CHECK: mrs x18, {{trcdevid|TRCDEVID}} // encoding: [0xf2,0x72,0x31,0xd5] +// CHECK: mrs x22, {{trcdevtype|TRCDEVTYPE}} // encoding: [0xf6,0x73,0x31,0xd5] +// CHECK: mrs x14, {{trcpidr4|TRCPIDR4}} // encoding: [0xee,0x74,0x31,0xd5] +// CHECK: mrs x5, {{trcpidr5|TRCPIDR5}} // encoding: [0xe5,0x75,0x31,0xd5] +// CHECK: mrs x5, {{trcpidr6|TRCPIDR6}} // encoding: [0xe5,0x76,0x31,0xd5] +// CHECK: mrs x9, {{trcpidr7|TRCPIDR7}} // encoding: [0xe9,0x77,0x31,0xd5] +// CHECK: mrs x15, {{trcpidr0|TRCPIDR0}} // encoding: [0xef,0x78,0x31,0xd5] +// CHECK: mrs x6, {{trcpidr1|TRCPIDR1}} // encoding: [0xe6,0x79,0x31,0xd5] +// CHECK: mrs x11, {{trcpidr2|TRCPIDR2}} // encoding: [0xeb,0x7a,0x31,0xd5] +// CHECK: mrs x20, {{trcpidr3|TRCPIDR3}} // encoding: [0xf4,0x7b,0x31,0xd5] +// CHECK: mrs x17, {{trccidr0|TRCCIDR0}} // encoding: [0xf1,0x7c,0x31,0xd5] +// CHECK: mrs x2, {{trccidr1|TRCCIDR1}} // encoding: [0xe2,0x7d,0x31,0xd5] +// CHECK: mrs x20, {{trccidr2|TRCCIDR2}} // encoding: [0xf4,0x7e,0x31,0xd5] +// CHECK: mrs x4, {{trccidr3|TRCCIDR3}} // encoding: [0xe4,0x7f,0x31,0xd5] +// CHECK: mrs x11, {{trcprgctlr|TRCPRGCTLR}} // encoding: [0x0b,0x01,0x31,0xd5] +// CHECK: mrs x23, {{trcprocselr|TRCPROCSELR}} // encoding: [0x17,0x02,0x31,0xd5] +// CHECK: mrs x13, {{trcconfigr|TRCCONFIGR}} // encoding: [0x0d,0x04,0x31,0xd5] +// CHECK: mrs x23, {{trcauxctlr|TRCAUXCTLR}} // encoding: [0x17,0x06,0x31,0xd5] +// CHECK: mrs x9, {{trceventctl0r|TRCEVENTCTL0R}} // encoding: [0x09,0x08,0x31,0xd5] +// CHECK: mrs x16, {{trceventctl1r|TRCEVENTCTL1R}} // encoding: [0x10,0x09,0x31,0xd5] +// CHECK: mrs x4, {{trcstallctlr|TRCSTALLCTLR}} // encoding: [0x04,0x0b,0x31,0xd5] +// CHECK: mrs x14, {{trctsctlr|TRCTSCTLR}} // encoding: [0x0e,0x0c,0x31,0xd5] +// CHECK: mrs x24, {{trcsyncpr|TRCSYNCPR}} // encoding: [0x18,0x0d,0x31,0xd5] +// CHECK: mrs x28, {{trcccctlr|TRCCCCTLR}} // encoding: [0x1c,0x0e,0x31,0xd5] +// CHECK: mrs x15, {{trcbbctlr|TRCBBCTLR}} // encoding: [0x0f,0x0f,0x31,0xd5] +// CHECK: mrs x1, {{trctraceidr|TRCTRACEIDR}} // encoding: [0x21,0x00,0x31,0xd5] +// CHECK: mrs x20, {{trcqctlr|TRCQCTLR}} // encoding: [0x34,0x01,0x31,0xd5] +// CHECK: mrs x2, {{trcvictlr|TRCVICTLR}} // encoding: [0x42,0x00,0x31,0xd5] +// CHECK: mrs x12, {{trcviiectlr|TRCVIIECTLR}} // encoding: [0x4c,0x01,0x31,0xd5] +// CHECK: mrs x16, {{trcvissctlr|TRCVISSCTLR}} // encoding: [0x50,0x02,0x31,0xd5] +// CHECK: mrs x8, {{trcvipcssctlr|TRCVIPCSSCTLR}} // encoding: [0x48,0x03,0x31,0xd5] +// CHECK: mrs x27, {{trcvdctlr|TRCVDCTLR}} // encoding: [0x5b,0x08,0x31,0xd5] +// CHECK: mrs x9, {{trcvdsacctlr|TRCVDSACCTLR}} // encoding: [0x49,0x09,0x31,0xd5] +// CHECK: mrs x0, {{trcvdarcctlr|TRCVDARCCTLR}} // encoding: [0x40,0x0a,0x31,0xd5] +// CHECK: mrs x13, {{trcseqevr0|TRCSEQEVR0}} // encoding: [0x8d,0x00,0x31,0xd5] +// CHECK: mrs x11, {{trcseqevr1|TRCSEQEVR1}} // encoding: [0x8b,0x01,0x31,0xd5] +// CHECK: mrs x26, {{trcseqevr2|TRCSEQEVR2}} // encoding: [0x9a,0x02,0x31,0xd5] +// CHECK: mrs x14, {{trcseqrstevr|TRCSEQRSTEVR}} // encoding: [0x8e,0x06,0x31,0xd5] +// CHECK: mrs x4, {{trcseqstr|TRCSEQSTR}} // encoding: [0x84,0x07,0x31,0xd5] +// CHECK: mrs x17, {{trcextinselr|TRCEXTINSELR}} // encoding: [0x91,0x08,0x31,0xd5] +// CHECK: mrs x21, {{trccntrldvr0|TRCCNTRLDVR0}} // encoding: [0xb5,0x00,0x31,0xd5] +// CHECK: mrs x10, {{trccntrldvr1|TRCCNTRLDVR1}} // encoding: [0xaa,0x01,0x31,0xd5] +// CHECK: mrs x20, {{trccntrldvr2|TRCCNTRLDVR2}} // encoding: [0xb4,0x02,0x31,0xd5] +// CHECK: mrs x5, {{trccntrldvr3|TRCCNTRLDVR3}} // encoding: [0xa5,0x03,0x31,0xd5] +// CHECK: mrs x17, {{trccntctlr0|TRCCNTCTLR0}} // encoding: [0xb1,0x04,0x31,0xd5] +// CHECK: mrs x1, {{trccntctlr1|TRCCNTCTLR1}} // encoding: [0xa1,0x05,0x31,0xd5] +// CHECK: mrs x17, {{trccntctlr2|TRCCNTCTLR2}} // encoding: [0xb1,0x06,0x31,0xd5] +// CHECK: mrs x6, {{trccntctlr3|TRCCNTCTLR3}} // encoding: [0xa6,0x07,0x31,0xd5] +// CHECK: mrs x28, {{trccntvr0|TRCCNTVR0}} // encoding: [0xbc,0x08,0x31,0xd5] +// CHECK: mrs x23, {{trccntvr1|TRCCNTVR1}} // encoding: [0xb7,0x09,0x31,0xd5] +// CHECK: mrs x9, {{trccntvr2|TRCCNTVR2}} // encoding: [0xa9,0x0a,0x31,0xd5] +// CHECK: mrs x6, {{trccntvr3|TRCCNTVR3}} // encoding: [0xa6,0x0b,0x31,0xd5] +// CHECK: mrs x24, {{trcimspec0|TRCIMSPEC0}} // encoding: [0xf8,0x00,0x31,0xd5] +// CHECK: mrs x24, {{trcimspec1|TRCIMSPEC1}} // encoding: [0xf8,0x01,0x31,0xd5] +// CHECK: mrs x15, {{trcimspec2|TRCIMSPEC2}} // encoding: [0xef,0x02,0x31,0xd5] +// CHECK: mrs x10, {{trcimspec3|TRCIMSPEC3}} // encoding: [0xea,0x03,0x31,0xd5] +// CHECK: mrs x29, {{trcimspec4|TRCIMSPEC4}} // encoding: [0xfd,0x04,0x31,0xd5] +// CHECK: mrs x18, {{trcimspec5|TRCIMSPEC5}} // encoding: [0xf2,0x05,0x31,0xd5] +// CHECK: mrs x29, {{trcimspec6|TRCIMSPEC6}} // encoding: [0xfd,0x06,0x31,0xd5] +// CHECK: mrs x2, {{trcimspec7|TRCIMSPEC7}} // encoding: [0xe2,0x07,0x31,0xd5] +// CHECK: mrs x8, {{trcrsctlr2|TRCRSCTLR2}} // encoding: [0x08,0x12,0x31,0xd5] +// CHECK: mrs x0, {{trcrsctlr3|TRCRSCTLR3}} // encoding: [0x00,0x13,0x31,0xd5] +// CHECK: mrs x12, {{trcrsctlr4|TRCRSCTLR4}} // encoding: [0x0c,0x14,0x31,0xd5] +// CHECK: mrs x26, {{trcrsctlr5|TRCRSCTLR5}} // encoding: [0x1a,0x15,0x31,0xd5] +// CHECK: mrs x29, {{trcrsctlr6|TRCRSCTLR6}} // encoding: [0x1d,0x16,0x31,0xd5] +// CHECK: mrs x17, {{trcrsctlr7|TRCRSCTLR7}} // encoding: [0x11,0x17,0x31,0xd5] +// CHECK: mrs x0, {{trcrsctlr8|TRCRSCTLR8}} // encoding: [0x00,0x18,0x31,0xd5] +// CHECK: mrs x1, {{trcrsctlr9|TRCRSCTLR9}} // encoding: [0x01,0x19,0x31,0xd5] +// CHECK: mrs x17, {{trcrsctlr10|TRCRSCTLR10}} // encoding: [0x11,0x1a,0x31,0xd5] +// CHECK: mrs x21, {{trcrsctlr11|TRCRSCTLR11}} // encoding: [0x15,0x1b,0x31,0xd5] +// CHECK: mrs x1, {{trcrsctlr12|TRCRSCTLR12}} // encoding: [0x01,0x1c,0x31,0xd5] +// CHECK: mrs x8, {{trcrsctlr13|TRCRSCTLR13}} // encoding: [0x08,0x1d,0x31,0xd5] +// CHECK: mrs x24, {{trcrsctlr14|TRCRSCTLR14}} // encoding: [0x18,0x1e,0x31,0xd5] +// CHECK: mrs x0, {{trcrsctlr15|TRCRSCTLR15}} // encoding: [0x00,0x1f,0x31,0xd5] +// CHECK: mrs x2, {{trcrsctlr16|TRCRSCTLR16}} // encoding: [0x22,0x10,0x31,0xd5] +// CHECK: mrs x29, {{trcrsctlr17|TRCRSCTLR17}} // encoding: [0x3d,0x11,0x31,0xd5] +// CHECK: mrs x22, {{trcrsctlr18|TRCRSCTLR18}} // encoding: [0x36,0x12,0x31,0xd5] +// CHECK: mrs x6, {{trcrsctlr19|TRCRSCTLR19}} // encoding: [0x26,0x13,0x31,0xd5] +// CHECK: mrs x26, {{trcrsctlr20|TRCRSCTLR20}} // encoding: [0x3a,0x14,0x31,0xd5] +// CHECK: mrs x26, {{trcrsctlr21|TRCRSCTLR21}} // encoding: [0x3a,0x15,0x31,0xd5] +// CHECK: mrs x4, {{trcrsctlr22|TRCRSCTLR22}} // encoding: [0x24,0x16,0x31,0xd5] +// CHECK: mrs x12, {{trcrsctlr23|TRCRSCTLR23}} // encoding: [0x2c,0x17,0x31,0xd5] +// CHECK: mrs x1, {{trcrsctlr24|TRCRSCTLR24}} // encoding: [0x21,0x18,0x31,0xd5] +// CHECK: mrs x0, {{trcrsctlr25|TRCRSCTLR25}} // encoding: [0x20,0x19,0x31,0xd5] +// CHECK: mrs x17, {{trcrsctlr26|TRCRSCTLR26}} // encoding: [0x31,0x1a,0x31,0xd5] +// CHECK: mrs x8, {{trcrsctlr27|TRCRSCTLR27}} // encoding: [0x28,0x1b,0x31,0xd5] +// CHECK: mrs x10, {{trcrsctlr28|TRCRSCTLR28}} // encoding: [0x2a,0x1c,0x31,0xd5] +// CHECK: mrs x25, {{trcrsctlr29|TRCRSCTLR29}} // encoding: [0x39,0x1d,0x31,0xd5] +// CHECK: mrs x12, {{trcrsctlr30|TRCRSCTLR30}} // encoding: [0x2c,0x1e,0x31,0xd5] +// CHECK: mrs x11, {{trcrsctlr31|TRCRSCTLR31}} // encoding: [0x2b,0x1f,0x31,0xd5] +// CHECK: mrs x18, {{trcssccr0|TRCSSCCR0}} // encoding: [0x52,0x10,0x31,0xd5] +// CHECK: mrs x12, {{trcssccr1|TRCSSCCR1}} // encoding: [0x4c,0x11,0x31,0xd5] +// CHECK: mrs x3, {{trcssccr2|TRCSSCCR2}} // encoding: [0x43,0x12,0x31,0xd5] +// CHECK: mrs x2, {{trcssccr3|TRCSSCCR3}} // encoding: [0x42,0x13,0x31,0xd5] +// CHECK: mrs x21, {{trcssccr4|TRCSSCCR4}} // encoding: [0x55,0x14,0x31,0xd5] +// CHECK: mrs x10, {{trcssccr5|TRCSSCCR5}} // encoding: [0x4a,0x15,0x31,0xd5] +// CHECK: mrs x22, {{trcssccr6|TRCSSCCR6}} // encoding: [0x56,0x16,0x31,0xd5] +// CHECK: mrs x23, {{trcssccr7|TRCSSCCR7}} // encoding: [0x57,0x17,0x31,0xd5] +// CHECK: mrs x23, {{trcsscsr0|TRCSSCSR0}} // encoding: [0x57,0x18,0x31,0xd5] +// CHECK: mrs x19, {{trcsscsr1|TRCSSCSR1}} // encoding: [0x53,0x19,0x31,0xd5] +// CHECK: mrs x25, {{trcsscsr2|TRCSSCSR2}} // encoding: [0x59,0x1a,0x31,0xd5] +// CHECK: mrs x17, {{trcsscsr3|TRCSSCSR3}} // encoding: [0x51,0x1b,0x31,0xd5] +// CHECK: mrs x19, {{trcsscsr4|TRCSSCSR4}} // encoding: [0x53,0x1c,0x31,0xd5] +// CHECK: mrs x11, {{trcsscsr5|TRCSSCSR5}} // encoding: [0x4b,0x1d,0x31,0xd5] +// CHECK: mrs x5, {{trcsscsr6|TRCSSCSR6}} // encoding: [0x45,0x1e,0x31,0xd5] +// CHECK: mrs x9, {{trcsscsr7|TRCSSCSR7}} // encoding: [0x49,0x1f,0x31,0xd5] +// CHECK: mrs x1, {{trcsspcicr0|TRCSSPCICR0}} // encoding: [0x61,0x10,0x31,0xd5] +// CHECK: mrs x12, {{trcsspcicr1|TRCSSPCICR1}} // encoding: [0x6c,0x11,0x31,0xd5] +// CHECK: mrs x21, {{trcsspcicr2|TRCSSPCICR2}} // encoding: [0x75,0x12,0x31,0xd5] +// CHECK: mrs x11, {{trcsspcicr3|TRCSSPCICR3}} // encoding: [0x6b,0x13,0x31,0xd5] +// CHECK: mrs x3, {{trcsspcicr4|TRCSSPCICR4}} // encoding: [0x63,0x14,0x31,0xd5] +// CHECK: mrs x9, {{trcsspcicr5|TRCSSPCICR5}} // encoding: [0x69,0x15,0x31,0xd5] +// CHECK: mrs x5, {{trcsspcicr6|TRCSSPCICR6}} // encoding: [0x65,0x16,0x31,0xd5] +// CHECK: mrs x2, {{trcsspcicr7|TRCSSPCICR7}} // encoding: [0x62,0x17,0x31,0xd5] +// CHECK: mrs x26, {{trcpdcr|TRCPDCR}} // encoding: [0x9a,0x14,0x31,0xd5] +// CHECK: mrs x8, {{trcacvr0|TRCACVR0}} // encoding: [0x08,0x20,0x31,0xd5] +// CHECK: mrs x15, {{trcacvr1|TRCACVR1}} // encoding: [0x0f,0x22,0x31,0xd5] +// CHECK: mrs x19, {{trcacvr2|TRCACVR2}} // encoding: [0x13,0x24,0x31,0xd5] +// CHECK: mrs x8, {{trcacvr3|TRCACVR3}} // encoding: [0x08,0x26,0x31,0xd5] +// CHECK: mrs x28, {{trcacvr4|TRCACVR4}} // encoding: [0x1c,0x28,0x31,0xd5] +// CHECK: mrs x3, {{trcacvr5|TRCACVR5}} // encoding: [0x03,0x2a,0x31,0xd5] +// CHECK: mrs x25, {{trcacvr6|TRCACVR6}} // encoding: [0x19,0x2c,0x31,0xd5] +// CHECK: mrs x24, {{trcacvr7|TRCACVR7}} // encoding: [0x18,0x2e,0x31,0xd5] +// CHECK: mrs x6, {{trcacvr8|TRCACVR8}} // encoding: [0x26,0x20,0x31,0xd5] +// CHECK: mrs x3, {{trcacvr9|TRCACVR9}} // encoding: [0x23,0x22,0x31,0xd5] +// CHECK: mrs x24, {{trcacvr10|TRCACVR10}} // encoding: [0x38,0x24,0x31,0xd5] +// CHECK: mrs x3, {{trcacvr11|TRCACVR11}} // encoding: [0x23,0x26,0x31,0xd5] +// CHECK: mrs x12, {{trcacvr12|TRCACVR12}} // encoding: [0x2c,0x28,0x31,0xd5] +// CHECK: mrs x9, {{trcacvr13|TRCACVR13}} // encoding: [0x29,0x2a,0x31,0xd5] +// CHECK: mrs x14, {{trcacvr14|TRCACVR14}} // encoding: [0x2e,0x2c,0x31,0xd5] +// CHECK: mrs x3, {{trcacvr15|TRCACVR15}} // encoding: [0x23,0x2e,0x31,0xd5] +// CHECK: mrs x21, {{trcacatr0|TRCACATR0}} // encoding: [0x55,0x20,0x31,0xd5] +// CHECK: mrs x26, {{trcacatr1|TRCACATR1}} // encoding: [0x5a,0x22,0x31,0xd5] +// CHECK: mrs x8, {{trcacatr2|TRCACATR2}} // encoding: [0x48,0x24,0x31,0xd5] +// CHECK: mrs x22, {{trcacatr3|TRCACATR3}} // encoding: [0x56,0x26,0x31,0xd5] +// CHECK: mrs x6, {{trcacatr4|TRCACATR4}} // encoding: [0x46,0x28,0x31,0xd5] +// CHECK: mrs x29, {{trcacatr5|TRCACATR5}} // encoding: [0x5d,0x2a,0x31,0xd5] +// CHECK: mrs x5, {{trcacatr6|TRCACATR6}} // encoding: [0x45,0x2c,0x31,0xd5] +// CHECK: mrs x18, {{trcacatr7|TRCACATR7}} // encoding: [0x52,0x2e,0x31,0xd5] +// CHECK: mrs x2, {{trcacatr8|TRCACATR8}} // encoding: [0x62,0x20,0x31,0xd5] +// CHECK: mrs x19, {{trcacatr9|TRCACATR9}} // encoding: [0x73,0x22,0x31,0xd5] +// CHECK: mrs x13, {{trcacatr10|TRCACATR10}} // encoding: [0x6d,0x24,0x31,0xd5] +// CHECK: mrs x25, {{trcacatr11|TRCACATR11}} // encoding: [0x79,0x26,0x31,0xd5] +// CHECK: mrs x18, {{trcacatr12|TRCACATR12}} // encoding: [0x72,0x28,0x31,0xd5] +// CHECK: mrs x29, {{trcacatr13|TRCACATR13}} // encoding: [0x7d,0x2a,0x31,0xd5] +// CHECK: mrs x9, {{trcacatr14|TRCACATR14}} // encoding: [0x69,0x2c,0x31,0xd5] +// CHECK: mrs x18, {{trcacatr15|TRCACATR15}} // encoding: [0x72,0x2e,0x31,0xd5] +// CHECK: mrs x29, {{trcdvcvr0|TRCDVCVR0}} // encoding: [0x9d,0x20,0x31,0xd5] +// CHECK: mrs x15, {{trcdvcvr1|TRCDVCVR1}} // encoding: [0x8f,0x24,0x31,0xd5] +// CHECK: mrs x15, {{trcdvcvr2|TRCDVCVR2}} // encoding: [0x8f,0x28,0x31,0xd5] +// CHECK: mrs x15, {{trcdvcvr3|TRCDVCVR3}} // encoding: [0x8f,0x2c,0x31,0xd5] +// CHECK: mrs x19, {{trcdvcvr4|TRCDVCVR4}} // encoding: [0xb3,0x20,0x31,0xd5] +// CHECK: mrs x22, {{trcdvcvr5|TRCDVCVR5}} // encoding: [0xb6,0x24,0x31,0xd5] +// CHECK: mrs x27, {{trcdvcvr6|TRCDVCVR6}} // encoding: [0xbb,0x28,0x31,0xd5] +// CHECK: mrs x1, {{trcdvcvr7|TRCDVCVR7}} // encoding: [0xa1,0x2c,0x31,0xd5] +// CHECK: mrs x29, {{trcdvcmr0|TRCDVCMR0}} // encoding: [0xdd,0x20,0x31,0xd5] +// CHECK: mrs x9, {{trcdvcmr1|TRCDVCMR1}} // encoding: [0xc9,0x24,0x31,0xd5] +// CHECK: mrs x1, {{trcdvcmr2|TRCDVCMR2}} // encoding: [0xc1,0x28,0x31,0xd5] +// CHECK: mrs x2, {{trcdvcmr3|TRCDVCMR3}} // encoding: [0xc2,0x2c,0x31,0xd5] +// CHECK: mrs x5, {{trcdvcmr4|TRCDVCMR4}} // encoding: [0xe5,0x20,0x31,0xd5] +// CHECK: mrs x21, {{trcdvcmr5|TRCDVCMR5}} // encoding: [0xf5,0x24,0x31,0xd5] +// CHECK: mrs x5, {{trcdvcmr6|TRCDVCMR6}} // encoding: [0xe5,0x28,0x31,0xd5] +// CHECK: mrs x1, {{trcdvcmr7|TRCDVCMR7}} // encoding: [0xe1,0x2c,0x31,0xd5] +// CHECK: mrs x21, {{trccidcvr0|TRCCIDCVR0}} // encoding: [0x15,0x30,0x31,0xd5] +// CHECK: mrs x24, {{trccidcvr1|TRCCIDCVR1}} // encoding: [0x18,0x32,0x31,0xd5] +// CHECK: mrs x24, {{trccidcvr2|TRCCIDCVR2}} // encoding: [0x18,0x34,0x31,0xd5] +// CHECK: mrs x12, {{trccidcvr3|TRCCIDCVR3}} // encoding: [0x0c,0x36,0x31,0xd5] +// CHECK: mrs x10, {{trccidcvr4|TRCCIDCVR4}} // encoding: [0x0a,0x38,0x31,0xd5] +// CHECK: mrs x9, {{trccidcvr5|TRCCIDCVR5}} // encoding: [0x09,0x3a,0x31,0xd5] +// CHECK: mrs x6, {{trccidcvr6|TRCCIDCVR6}} // encoding: [0x06,0x3c,0x31,0xd5] +// CHECK: mrs x20, {{trccidcvr7|TRCCIDCVR7}} // encoding: [0x14,0x3e,0x31,0xd5] +// CHECK: mrs x20, {{trcvmidcvr0|TRCVMIDCVR0}} // encoding: [0x34,0x30,0x31,0xd5] +// CHECK: mrs x20, {{trcvmidcvr1|TRCVMIDCVR1}} // encoding: [0x34,0x32,0x31,0xd5] +// CHECK: mrs x26, {{trcvmidcvr2|TRCVMIDCVR2}} // encoding: [0x3a,0x34,0x31,0xd5] +// CHECK: mrs x1, {{trcvmidcvr3|TRCVMIDCVR3}} // encoding: [0x21,0x36,0x31,0xd5] +// CHECK: mrs x14, {{trcvmidcvr4|TRCVMIDCVR4}} // encoding: [0x2e,0x38,0x31,0xd5] +// CHECK: mrs x27, {{trcvmidcvr5|TRCVMIDCVR5}} // encoding: [0x3b,0x3a,0x31,0xd5] +// CHECK: mrs x29, {{trcvmidcvr6|TRCVMIDCVR6}} // encoding: [0x3d,0x3c,0x31,0xd5] +// CHECK: mrs x17, {{trcvmidcvr7|TRCVMIDCVR7}} // encoding: [0x31,0x3e,0x31,0xd5] +// CHECK: mrs x10, {{trccidcctlr0|TRCCIDCCTLR0}} // encoding: [0x4a,0x30,0x31,0xd5] +// CHECK: mrs x4, {{trccidcctlr1|TRCCIDCCTLR1}} // encoding: [0x44,0x31,0x31,0xd5] +// CHECK: mrs x9, {{trcvmidcctlr0|TRCVMIDCCTLR0}} // encoding: [0x49,0x32,0x31,0xd5] +// CHECK: mrs x11, {{trcvmidcctlr1|TRCVMIDCCTLR1}} // encoding: [0x4b,0x33,0x31,0xd5] +// CHECK: mrs x22, {{trcitctrl|TRCITCTRL}} // encoding: [0x96,0x70,0x31,0xd5] +// CHECK: mrs x23, {{trcclaimset|TRCCLAIMSET}} // encoding: [0xd7,0x78,0x31,0xd5] +// CHECK: mrs x14, {{trcclaimclr|TRCCLAIMCLR}} // encoding: [0xce,0x79,0x31,0xd5] msr trcoslar, x28 msr trclar, x14 @@ -590,177 +591,177 @@ msr trcitctrl, x1 msr trcclaimset, x7 msr trcclaimclr, x29 -// CHECK: msr trcoslar, x28 // encoding: [0x9c,0x10,0x11,0xd5] -// CHECK: msr trclar, x14 // encoding: [0xce,0x7c,0x11,0xd5] -// CHECK: msr trcprgctlr, x10 // encoding: [0x0a,0x01,0x11,0xd5] -// CHECK: msr trcprocselr, x27 // encoding: [0x1b,0x02,0x11,0xd5] -// CHECK: msr trcconfigr, x24 // encoding: [0x18,0x04,0x11,0xd5] -// CHECK: msr trcauxctlr, x8 // encoding: [0x08,0x06,0x11,0xd5] -// CHECK: msr trceventctl0r, x16 // encoding: [0x10,0x08,0x11,0xd5] -// CHECK: msr trceventctl1r, x27 // encoding: [0x1b,0x09,0x11,0xd5] -// CHECK: msr trcstallctlr, x26 // encoding: [0x1a,0x0b,0x11,0xd5] -// CHECK: msr trctsctlr, x0 // encoding: [0x00,0x0c,0x11,0xd5] -// CHECK: msr trcsyncpr, x14 // encoding: [0x0e,0x0d,0x11,0xd5] -// CHECK: msr trcccctlr, x8 // encoding: [0x08,0x0e,0x11,0xd5] -// CHECK: msr trcbbctlr, x6 // encoding: [0x06,0x0f,0x11,0xd5] -// CHECK: msr trctraceidr, x23 // encoding: [0x37,0x00,0x11,0xd5] -// CHECK: msr trcqctlr, x5 // encoding: [0x25,0x01,0x11,0xd5] -// CHECK: msr trcvictlr, x0 // encoding: [0x40,0x00,0x11,0xd5] -// CHECK: msr trcviiectlr, x0 // encoding: [0x40,0x01,0x11,0xd5] -// CHECK: msr trcvissctlr, x1 // encoding: [0x41,0x02,0x11,0xd5] -// CHECK: msr trcvipcssctlr, x0 // encoding: [0x40,0x03,0x11,0xd5] -// CHECK: msr trcvdctlr, x7 // encoding: [0x47,0x08,0x11,0xd5] -// CHECK: msr trcvdsacctlr, x18 // encoding: [0x52,0x09,0x11,0xd5] -// CHECK: msr trcvdarcctlr, x24 // encoding: [0x58,0x0a,0x11,0xd5] -// CHECK: msr trcseqevr0, x28 // encoding: [0x9c,0x00,0x11,0xd5] -// CHECK: msr trcseqevr1, x21 // encoding: [0x95,0x01,0x11,0xd5] -// CHECK: msr trcseqevr2, x16 // encoding: [0x90,0x02,0x11,0xd5] -// CHECK: msr trcseqrstevr, x16 // encoding: [0x90,0x06,0x11,0xd5] -// CHECK: msr trcseqstr, x25 // encoding: [0x99,0x07,0x11,0xd5] -// CHECK: msr trcextinselr, x29 // encoding: [0x9d,0x08,0x11,0xd5] -// CHECK: msr trccntrldvr0, x20 // encoding: [0xb4,0x00,0x11,0xd5] -// CHECK: msr trccntrldvr1, x20 // encoding: [0xb4,0x01,0x11,0xd5] -// CHECK: msr trccntrldvr2, x22 // encoding: [0xb6,0x02,0x11,0xd5] -// CHECK: msr trccntrldvr3, x12 // encoding: [0xac,0x03,0x11,0xd5] -// CHECK: msr trccntctlr0, x20 // encoding: [0xb4,0x04,0x11,0xd5] -// CHECK: msr trccntctlr1, x4 // encoding: [0xa4,0x05,0x11,0xd5] -// CHECK: msr trccntctlr2, x8 // encoding: [0xa8,0x06,0x11,0xd5] -// CHECK: msr trccntctlr3, x16 // encoding: [0xb0,0x07,0x11,0xd5] -// CHECK: msr trccntvr0, x5 // encoding: [0xa5,0x08,0x11,0xd5] -// CHECK: msr trccntvr1, x27 // encoding: [0xbb,0x09,0x11,0xd5] -// CHECK: msr trccntvr2, x21 // encoding: [0xb5,0x0a,0x11,0xd5] -// CHECK: msr trccntvr3, x8 // encoding: [0xa8,0x0b,0x11,0xd5] -// CHECK: msr trcimspec0, x6 // encoding: [0xe6,0x00,0x11,0xd5] -// CHECK: msr trcimspec1, x27 // encoding: [0xfb,0x01,0x11,0xd5] -// CHECK: msr trcimspec2, x23 // encoding: [0xf7,0x02,0x11,0xd5] -// CHECK: msr trcimspec3, x15 // encoding: [0xef,0x03,0x11,0xd5] -// CHECK: msr trcimspec4, x13 // encoding: [0xed,0x04,0x11,0xd5] -// CHECK: msr trcimspec5, x25 // encoding: [0xf9,0x05,0x11,0xd5] -// CHECK: msr trcimspec6, x19 // encoding: [0xf3,0x06,0x11,0xd5] -// CHECK: msr trcimspec7, x27 // encoding: [0xfb,0x07,0x11,0xd5] -// CHECK: msr trcrsctlr2, x4 // encoding: [0x04,0x12,0x11,0xd5] -// CHECK: msr trcrsctlr3, x0 // encoding: [0x00,0x13,0x11,0xd5] -// CHECK: msr trcrsctlr4, x21 // encoding: [0x15,0x14,0x11,0xd5] -// CHECK: msr trcrsctlr5, x8 // encoding: [0x08,0x15,0x11,0xd5] -// CHECK: msr trcrsctlr6, x20 // encoding: [0x14,0x16,0x11,0xd5] -// CHECK: msr trcrsctlr7, x11 // encoding: [0x0b,0x17,0x11,0xd5] -// CHECK: msr trcrsctlr8, x18 // encoding: [0x12,0x18,0x11,0xd5] -// CHECK: msr trcrsctlr9, x24 // encoding: [0x18,0x19,0x11,0xd5] -// CHECK: msr trcrsctlr10, x15 // encoding: [0x0f,0x1a,0x11,0xd5] -// CHECK: msr trcrsctlr11, x21 // encoding: [0x15,0x1b,0x11,0xd5] -// CHECK: msr trcrsctlr12, x4 // encoding: [0x04,0x1c,0x11,0xd5] -// CHECK: msr trcrsctlr13, x28 // encoding: [0x1c,0x1d,0x11,0xd5] -// CHECK: msr trcrsctlr14, x3 // encoding: [0x03,0x1e,0x11,0xd5] -// CHECK: msr trcrsctlr15, x20 // encoding: [0x14,0x1f,0x11,0xd5] -// CHECK: msr trcrsctlr16, x12 // encoding: [0x2c,0x10,0x11,0xd5] -// CHECK: msr trcrsctlr17, x17 // encoding: [0x31,0x11,0x11,0xd5] -// CHECK: msr trcrsctlr18, x10 // encoding: [0x2a,0x12,0x11,0xd5] -// CHECK: msr trcrsctlr19, x11 // encoding: [0x2b,0x13,0x11,0xd5] -// CHECK: msr trcrsctlr20, x3 // encoding: [0x23,0x14,0x11,0xd5] -// CHECK: msr trcrsctlr21, x18 // encoding: [0x32,0x15,0x11,0xd5] -// CHECK: msr trcrsctlr22, x26 // encoding: [0x3a,0x16,0x11,0xd5] -// CHECK: msr trcrsctlr23, x5 // encoding: [0x25,0x17,0x11,0xd5] -// CHECK: msr trcrsctlr24, x25 // encoding: [0x39,0x18,0x11,0xd5] -// CHECK: msr trcrsctlr25, x5 // encoding: [0x25,0x19,0x11,0xd5] -// CHECK: msr trcrsctlr26, x4 // encoding: [0x24,0x1a,0x11,0xd5] -// CHECK: msr trcrsctlr27, x20 // encoding: [0x34,0x1b,0x11,0xd5] -// CHECK: msr trcrsctlr28, x5 // encoding: [0x25,0x1c,0x11,0xd5] -// CHECK: msr trcrsctlr29, x10 // encoding: [0x2a,0x1d,0x11,0xd5] -// CHECK: msr trcrsctlr30, x24 // encoding: [0x38,0x1e,0x11,0xd5] -// CHECK: msr trcrsctlr31, x20 // encoding: [0x34,0x1f,0x11,0xd5] -// CHECK: msr trcssccr0, x23 // encoding: [0x57,0x10,0x11,0xd5] -// CHECK: msr trcssccr1, x27 // encoding: [0x5b,0x11,0x11,0xd5] -// CHECK: msr trcssccr2, x27 // encoding: [0x5b,0x12,0x11,0xd5] -// CHECK: msr trcssccr3, x6 // encoding: [0x46,0x13,0x11,0xd5] -// CHECK: msr trcssccr4, x3 // encoding: [0x43,0x14,0x11,0xd5] -// CHECK: msr trcssccr5, x12 // encoding: [0x4c,0x15,0x11,0xd5] -// CHECK: msr trcssccr6, x7 // encoding: [0x47,0x16,0x11,0xd5] -// CHECK: msr trcssccr7, x6 // encoding: [0x46,0x17,0x11,0xd5] -// CHECK: msr trcsscsr0, x20 // encoding: [0x54,0x18,0x11,0xd5] -// CHECK: msr trcsscsr1, x17 // encoding: [0x51,0x19,0x11,0xd5] -// CHECK: msr trcsscsr2, x11 // encoding: [0x4b,0x1a,0x11,0xd5] -// CHECK: msr trcsscsr3, x4 // encoding: [0x44,0x1b,0x11,0xd5] -// CHECK: msr trcsscsr4, x14 // encoding: [0x4e,0x1c,0x11,0xd5] -// CHECK: msr trcsscsr5, x22 // encoding: [0x56,0x1d,0x11,0xd5] -// CHECK: msr trcsscsr6, x3 // encoding: [0x43,0x1e,0x11,0xd5] -// CHECK: msr trcsscsr7, x11 // encoding: [0x4b,0x1f,0x11,0xd5] -// CHECK: msr trcsspcicr0, x2 // encoding: [0x62,0x10,0x11,0xd5] -// CHECK: msr trcsspcicr1, x3 // encoding: [0x63,0x11,0x11,0xd5] -// CHECK: msr trcsspcicr2, x5 // encoding: [0x65,0x12,0x11,0xd5] -// CHECK: msr trcsspcicr3, x7 // encoding: [0x67,0x13,0x11,0xd5] -// CHECK: msr trcsspcicr4, x11 // encoding: [0x6b,0x14,0x11,0xd5] -// CHECK: msr trcsspcicr5, x13 // encoding: [0x6d,0x15,0x11,0xd5] -// CHECK: msr trcsspcicr6, x17 // encoding: [0x71,0x16,0x11,0xd5] -// CHECK: msr trcsspcicr7, x23 // encoding: [0x77,0x17,0x11,0xd5] -// CHECK: msr trcpdcr, x3 // encoding: [0x83,0x14,0x11,0xd5] -// CHECK: msr trcacvr0, x6 // encoding: [0x06,0x20,0x11,0xd5] -// CHECK: msr trcacvr1, x20 // encoding: [0x14,0x22,0x11,0xd5] -// CHECK: msr trcacvr2, x25 // encoding: [0x19,0x24,0x11,0xd5] -// CHECK: msr trcacvr3, x1 // encoding: [0x01,0x26,0x11,0xd5] -// CHECK: msr trcacvr4, x28 // encoding: [0x1c,0x28,0x11,0xd5] -// CHECK: msr trcacvr5, x15 // encoding: [0x0f,0x2a,0x11,0xd5] -// CHECK: msr trcacvr6, x25 // encoding: [0x19,0x2c,0x11,0xd5] -// CHECK: msr trcacvr7, x12 // encoding: [0x0c,0x2e,0x11,0xd5] -// CHECK: msr trcacvr8, x5 // encoding: [0x25,0x20,0x11,0xd5] -// CHECK: msr trcacvr9, x25 // encoding: [0x39,0x22,0x11,0xd5] -// CHECK: msr trcacvr10, x13 // encoding: [0x2d,0x24,0x11,0xd5] -// CHECK: msr trcacvr11, x10 // encoding: [0x2a,0x26,0x11,0xd5] -// CHECK: msr trcacvr12, x19 // encoding: [0x33,0x28,0x11,0xd5] -// CHECK: msr trcacvr13, x10 // encoding: [0x2a,0x2a,0x11,0xd5] -// CHECK: msr trcacvr14, x19 // encoding: [0x33,0x2c,0x11,0xd5] -// CHECK: msr trcacvr15, x2 // encoding: [0x22,0x2e,0x11,0xd5] -// CHECK: msr trcacatr0, x15 // encoding: [0x4f,0x20,0x11,0xd5] -// CHECK: msr trcacatr1, x13 // encoding: [0x4d,0x22,0x11,0xd5] -// CHECK: msr trcacatr2, x8 // encoding: [0x48,0x24,0x11,0xd5] -// CHECK: msr trcacatr3, x1 // encoding: [0x41,0x26,0x11,0xd5] -// CHECK: msr trcacatr4, x11 // encoding: [0x4b,0x28,0x11,0xd5] -// CHECK: msr trcacatr5, x8 // encoding: [0x48,0x2a,0x11,0xd5] -// CHECK: msr trcacatr6, x24 // encoding: [0x58,0x2c,0x11,0xd5] -// CHECK: msr trcacatr7, x6 // encoding: [0x46,0x2e,0x11,0xd5] -// CHECK: msr trcacatr8, x23 // encoding: [0x77,0x20,0x11,0xd5] -// CHECK: msr trcacatr9, x5 // encoding: [0x65,0x22,0x11,0xd5] -// CHECK: msr trcacatr10, x11 // encoding: [0x6b,0x24,0x11,0xd5] -// CHECK: msr trcacatr11, x11 // encoding: [0x6b,0x26,0x11,0xd5] -// CHECK: msr trcacatr12, x3 // encoding: [0x63,0x28,0x11,0xd5] -// CHECK: msr trcacatr13, x28 // encoding: [0x7c,0x2a,0x11,0xd5] -// CHECK: msr trcacatr14, x25 // encoding: [0x79,0x2c,0x11,0xd5] -// CHECK: msr trcacatr15, x4 // encoding: [0x64,0x2e,0x11,0xd5] -// CHECK: msr trcdvcvr0, x6 // encoding: [0x86,0x20,0x11,0xd5] -// CHECK: msr trcdvcvr1, x3 // encoding: [0x83,0x24,0x11,0xd5] -// CHECK: msr trcdvcvr2, x5 // encoding: [0x85,0x28,0x11,0xd5] -// CHECK: msr trcdvcvr3, x11 // encoding: [0x8b,0x2c,0x11,0xd5] -// CHECK: msr trcdvcvr4, x9 // encoding: [0xa9,0x20,0x11,0xd5] -// CHECK: msr trcdvcvr5, x14 // encoding: [0xae,0x24,0x11,0xd5] -// CHECK: msr trcdvcvr6, x10 // encoding: [0xaa,0x28,0x11,0xd5] -// CHECK: msr trcdvcvr7, x12 // encoding: [0xac,0x2c,0x11,0xd5] -// CHECK: msr trcdvcmr0, x8 // encoding: [0xc8,0x20,0x11,0xd5] -// CHECK: msr trcdvcmr1, x8 // encoding: [0xc8,0x24,0x11,0xd5] -// CHECK: msr trcdvcmr2, x22 // encoding: [0xd6,0x28,0x11,0xd5] -// CHECK: msr trcdvcmr3, x22 // encoding: [0xd6,0x2c,0x11,0xd5] -// CHECK: msr trcdvcmr4, x5 // encoding: [0xe5,0x20,0x11,0xd5] -// CHECK: msr trcdvcmr5, x16 // encoding: [0xf0,0x24,0x11,0xd5] -// CHECK: msr trcdvcmr6, x27 // encoding: [0xfb,0x28,0x11,0xd5] -// CHECK: msr trcdvcmr7, x21 // encoding: [0xf5,0x2c,0x11,0xd5] -// CHECK: msr trccidcvr0, x8 // encoding: [0x08,0x30,0x11,0xd5] -// CHECK: msr trccidcvr1, x6 // encoding: [0x06,0x32,0x11,0xd5] -// CHECK: msr trccidcvr2, x9 // encoding: [0x09,0x34,0x11,0xd5] -// CHECK: msr trccidcvr3, x8 // encoding: [0x08,0x36,0x11,0xd5] -// CHECK: msr trccidcvr4, x3 // encoding: [0x03,0x38,0x11,0xd5] -// CHECK: msr trccidcvr5, x21 // encoding: [0x15,0x3a,0x11,0xd5] -// CHECK: msr trccidcvr6, x12 // encoding: [0x0c,0x3c,0x11,0xd5] -// CHECK: msr trccidcvr7, x7 // encoding: [0x07,0x3e,0x11,0xd5] -// CHECK: msr trcvmidcvr0, x4 // encoding: [0x24,0x30,0x11,0xd5] -// CHECK: msr trcvmidcvr1, x3 // encoding: [0x23,0x32,0x11,0xd5] -// CHECK: msr trcvmidcvr2, x9 // encoding: [0x29,0x34,0x11,0xd5] -// CHECK: msr trcvmidcvr3, x17 // encoding: [0x31,0x36,0x11,0xd5] -// CHECK: msr trcvmidcvr4, x14 // encoding: [0x2e,0x38,0x11,0xd5] -// CHECK: msr trcvmidcvr5, x12 // encoding: [0x2c,0x3a,0x11,0xd5] -// CHECK: msr trcvmidcvr6, x10 // encoding: [0x2a,0x3c,0x11,0xd5] -// CHECK: msr trcvmidcvr7, x3 // encoding: [0x23,0x3e,0x11,0xd5] -// CHECK: msr trccidcctlr0, x14 // encoding: [0x4e,0x30,0x11,0xd5] -// CHECK: msr trccidcctlr1, x22 // encoding: [0x56,0x31,0x11,0xd5] -// CHECK: msr trcvmidcctlr0, x8 // encoding: [0x48,0x32,0x11,0xd5] -// CHECK: msr trcvmidcctlr1, x15 // encoding: [0x4f,0x33,0x11,0xd5] -// CHECK: msr trcitctrl, x1 // encoding: [0x81,0x70,0x11,0xd5] -// CHECK: msr trcclaimset, x7 // encoding: [0xc7,0x78,0x11,0xd5] -// CHECK: msr trcclaimclr, x29 // encoding: [0xdd,0x79,0x11,0xd5] +// CHECK: msr {{trcoslar|TRCOSLAR}}, x28 // encoding: [0x9c,0x10,0x11,0xd5] +// CHECK: msr {{trclar|TRCLAR}}, x14 // encoding: [0xce,0x7c,0x11,0xd5] +// CHECK: msr {{trcprgctlr|TRCPRGCTLR}}, x10 // encoding: [0x0a,0x01,0x11,0xd5] +// CHECK: msr {{trcprocselr|TRCPROCSELR}}, x27 // encoding: [0x1b,0x02,0x11,0xd5] +// CHECK: msr {{trcconfigr|TRCCONFIGR}}, x24 // encoding: [0x18,0x04,0x11,0xd5] +// CHECK: msr {{trcauxctlr|TRCAUXCTLR}}, x8 // encoding: [0x08,0x06,0x11,0xd5] +// CHECK: msr {{trceventctl0r|TRCEVENTCTL0R}}, x16 // encoding: [0x10,0x08,0x11,0xd5] +// CHECK: msr {{trceventctl1r|TRCEVENTCTL1R}}, x27 // encoding: [0x1b,0x09,0x11,0xd5] +// CHECK: msr {{trcstallctlr|TRCSTALLCTLR}}, x26 // encoding: [0x1a,0x0b,0x11,0xd5] +// CHECK: msr {{trctsctlr|TRCTSCTLR}}, x0 // encoding: [0x00,0x0c,0x11,0xd5] +// CHECK: msr {{trcsyncpr|TRCSYNCPR}}, x14 // encoding: [0x0e,0x0d,0x11,0xd5] +// CHECK: msr {{trcccctlr|TRCCCCTLR}}, x8 // encoding: [0x08,0x0e,0x11,0xd5] +// CHECK: msr {{trcbbctlr|TRCBBCTLR}}, x6 // encoding: [0x06,0x0f,0x11,0xd5] +// CHECK: msr {{trctraceidr|TRCTRACEIDR}}, x23 // encoding: [0x37,0x00,0x11,0xd5] +// CHECK: msr {{trcqctlr|TRCQCTLR}}, x5 // encoding: [0x25,0x01,0x11,0xd5] +// CHECK: msr {{trcvictlr|TRCVICTLR}}, x0 // encoding: [0x40,0x00,0x11,0xd5] +// CHECK: msr {{trcviiectlr|TRCVIIECTLR}}, x0 // encoding: [0x40,0x01,0x11,0xd5] +// CHECK: msr {{trcvissctlr|TRCVISSCTLR}}, x1 // encoding: [0x41,0x02,0x11,0xd5] +// CHECK: msr {{trcvipcssctlr|TRCVIPCSSCTLR}}, x0 // encoding: [0x40,0x03,0x11,0xd5] +// CHECK: msr {{trcvdctlr|TRCVDCTLR}}, x7 // encoding: [0x47,0x08,0x11,0xd5] +// CHECK: msr {{trcvdsacctlr|TRCVDSACCTLR}}, x18 // encoding: [0x52,0x09,0x11,0xd5] +// CHECK: msr {{trcvdarcctlr|TRCVDARCCTLR}}, x24 // encoding: [0x58,0x0a,0x11,0xd5] +// CHECK: msr {{trcseqevr0|TRCSEQEVR0}}, x28 // encoding: [0x9c,0x00,0x11,0xd5] +// CHECK: msr {{trcseqevr1|TRCSEQEVR1}}, x21 // encoding: [0x95,0x01,0x11,0xd5] +// CHECK: msr {{trcseqevr2|TRCSEQEVR2}}, x16 // encoding: [0x90,0x02,0x11,0xd5] +// CHECK: msr {{trcseqrstevr|TRCSEQRSTEVR}}, x16 // encoding: [0x90,0x06,0x11,0xd5] +// CHECK: msr {{trcseqstr|TRCSEQSTR}}, x25 // encoding: [0x99,0x07,0x11,0xd5] +// CHECK: msr {{trcextinselr|TRCEXTINSELR}}, x29 // encoding: [0x9d,0x08,0x11,0xd5] +// CHECK: msr {{trccntrldvr0|TRCCNTRLDVR0}}, x20 // encoding: [0xb4,0x00,0x11,0xd5] +// CHECK: msr {{trccntrldvr1|TRCCNTRLDVR1}}, x20 // encoding: [0xb4,0x01,0x11,0xd5] +// CHECK: msr {{trccntrldvr2|TRCCNTRLDVR2}}, x22 // encoding: [0xb6,0x02,0x11,0xd5] +// CHECK: msr {{trccntrldvr3|TRCCNTRLDVR3}}, x12 // encoding: [0xac,0x03,0x11,0xd5] +// CHECK: msr {{trccntctlr0|TRCCNTCTLR0}}, x20 // encoding: [0xb4,0x04,0x11,0xd5] +// CHECK: msr {{trccntctlr1|TRCCNTCTLR1}}, x4 // encoding: [0xa4,0x05,0x11,0xd5] +// CHECK: msr {{trccntctlr2|TRCCNTCTLR2}}, x8 // encoding: [0xa8,0x06,0x11,0xd5] +// CHECK: msr {{trccntctlr3|TRCCNTCTLR3}}, x16 // encoding: [0xb0,0x07,0x11,0xd5] +// CHECK: msr {{trccntvr0|TRCCNTVR0}}, x5 // encoding: [0xa5,0x08,0x11,0xd5] +// CHECK: msr {{trccntvr1|TRCCNTVR1}}, x27 // encoding: [0xbb,0x09,0x11,0xd5] +// CHECK: msr {{trccntvr2|TRCCNTVR2}}, x21 // encoding: [0xb5,0x0a,0x11,0xd5] +// CHECK: msr {{trccntvr3|TRCCNTVR3}}, x8 // encoding: [0xa8,0x0b,0x11,0xd5] +// CHECK: msr {{trcimspec0|TRCIMSPEC0}}, x6 // encoding: [0xe6,0x00,0x11,0xd5] +// CHECK: msr {{trcimspec1|TRCIMSPEC1}}, x27 // encoding: [0xfb,0x01,0x11,0xd5] +// CHECK: msr {{trcimspec2|TRCIMSPEC2}}, x23 // encoding: [0xf7,0x02,0x11,0xd5] +// CHECK: msr {{trcimspec3|TRCIMSPEC3}}, x15 // encoding: [0xef,0x03,0x11,0xd5] +// CHECK: msr {{trcimspec4|TRCIMSPEC4}}, x13 // encoding: [0xed,0x04,0x11,0xd5] +// CHECK: msr {{trcimspec5|TRCIMSPEC5}}, x25 // encoding: [0xf9,0x05,0x11,0xd5] +// CHECK: msr {{trcimspec6|TRCIMSPEC6}}, x19 // encoding: [0xf3,0x06,0x11,0xd5] +// CHECK: msr {{trcimspec7|TRCIMSPEC7}}, x27 // encoding: [0xfb,0x07,0x11,0xd5] +// CHECK: msr {{trcrsctlr2|TRCRSCTLR2}}, x4 // encoding: [0x04,0x12,0x11,0xd5] +// CHECK: msr {{trcrsctlr3|TRCRSCTLR3}}, x0 // encoding: [0x00,0x13,0x11,0xd5] +// CHECK: msr {{trcrsctlr4|TRCRSCTLR4}}, x21 // encoding: [0x15,0x14,0x11,0xd5] +// CHECK: msr {{trcrsctlr5|TRCRSCTLR5}}, x8 // encoding: [0x08,0x15,0x11,0xd5] +// CHECK: msr {{trcrsctlr6|TRCRSCTLR6}}, x20 // encoding: [0x14,0x16,0x11,0xd5] +// CHECK: msr {{trcrsctlr7|TRCRSCTLR7}}, x11 // encoding: [0x0b,0x17,0x11,0xd5] +// CHECK: msr {{trcrsctlr8|TRCRSCTLR8}}, x18 // encoding: [0x12,0x18,0x11,0xd5] +// CHECK: msr {{trcrsctlr9|TRCRSCTLR9}}, x24 // encoding: [0x18,0x19,0x11,0xd5] +// CHECK: msr {{trcrsctlr10|TRCRSCTLR10}}, x15 // encoding: [0x0f,0x1a,0x11,0xd5] +// CHECK: msr {{trcrsctlr11|TRCRSCTLR11}}, x21 // encoding: [0x15,0x1b,0x11,0xd5] +// CHECK: msr {{trcrsctlr12|TRCRSCTLR12}}, x4 // encoding: [0x04,0x1c,0x11,0xd5] +// CHECK: msr {{trcrsctlr13|TRCRSCTLR13}}, x28 // encoding: [0x1c,0x1d,0x11,0xd5] +// CHECK: msr {{trcrsctlr14|TRCRSCTLR14}}, x3 // encoding: [0x03,0x1e,0x11,0xd5] +// CHECK: msr {{trcrsctlr15|TRCRSCTLR15}}, x20 // encoding: [0x14,0x1f,0x11,0xd5] +// CHECK: msr {{trcrsctlr16|TRCRSCTLR16}}, x12 // encoding: [0x2c,0x10,0x11,0xd5] +// CHECK: msr {{trcrsctlr17|TRCRSCTLR17}}, x17 // encoding: [0x31,0x11,0x11,0xd5] +// CHECK: msr {{trcrsctlr18|TRCRSCTLR18}}, x10 // encoding: [0x2a,0x12,0x11,0xd5] +// CHECK: msr {{trcrsctlr19|TRCRSCTLR19}}, x11 // encoding: [0x2b,0x13,0x11,0xd5] +// CHECK: msr {{trcrsctlr20|TRCRSCTLR20}}, x3 // encoding: [0x23,0x14,0x11,0xd5] +// CHECK: msr {{trcrsctlr21|TRCRSCTLR21}}, x18 // encoding: [0x32,0x15,0x11,0xd5] +// CHECK: msr {{trcrsctlr22|TRCRSCTLR22}}, x26 // encoding: [0x3a,0x16,0x11,0xd5] +// CHECK: msr {{trcrsctlr23|TRCRSCTLR23}}, x5 // encoding: [0x25,0x17,0x11,0xd5] +// CHECK: msr {{trcrsctlr24|TRCRSCTLR24}}, x25 // encoding: [0x39,0x18,0x11,0xd5] +// CHECK: msr {{trcrsctlr25|TRCRSCTLR25}}, x5 // encoding: [0x25,0x19,0x11,0xd5] +// CHECK: msr {{trcrsctlr26|TRCRSCTLR26}}, x4 // encoding: [0x24,0x1a,0x11,0xd5] +// CHECK: msr {{trcrsctlr27|TRCRSCTLR27}}, x20 // encoding: [0x34,0x1b,0x11,0xd5] +// CHECK: msr {{trcrsctlr28|TRCRSCTLR28}}, x5 // encoding: [0x25,0x1c,0x11,0xd5] +// CHECK: msr {{trcrsctlr29|TRCRSCTLR29}}, x10 // encoding: [0x2a,0x1d,0x11,0xd5] +// CHECK: msr {{trcrsctlr30|TRCRSCTLR30}}, x24 // encoding: [0x38,0x1e,0x11,0xd5] +// CHECK: msr {{trcrsctlr31|TRCRSCTLR31}}, x20 // encoding: [0x34,0x1f,0x11,0xd5] +// CHECK: msr {{trcssccr0|TRCSSCCR0}}, x23 // encoding: [0x57,0x10,0x11,0xd5] +// CHECK: msr {{trcssccr1|TRCSSCCR1}}, x27 // encoding: [0x5b,0x11,0x11,0xd5] +// CHECK: msr {{trcssccr2|TRCSSCCR2}}, x27 // encoding: [0x5b,0x12,0x11,0xd5] +// CHECK: msr {{trcssccr3|TRCSSCCR3}}, x6 // encoding: [0x46,0x13,0x11,0xd5] +// CHECK: msr {{trcssccr4|TRCSSCCR4}}, x3 // encoding: [0x43,0x14,0x11,0xd5] +// CHECK: msr {{trcssccr5|TRCSSCCR5}}, x12 // encoding: [0x4c,0x15,0x11,0xd5] +// CHECK: msr {{trcssccr6|TRCSSCCR6}}, x7 // encoding: [0x47,0x16,0x11,0xd5] +// CHECK: msr {{trcssccr7|TRCSSCCR7}}, x6 // encoding: [0x46,0x17,0x11,0xd5] +// CHECK: msr {{trcsscsr0|TRCSSCSR0}}, x20 // encoding: [0x54,0x18,0x11,0xd5] +// CHECK: msr {{trcsscsr1|TRCSSCSR1}}, x17 // encoding: [0x51,0x19,0x11,0xd5] +// CHECK: msr {{trcsscsr2|TRCSSCSR2}}, x11 // encoding: [0x4b,0x1a,0x11,0xd5] +// CHECK: msr {{trcsscsr3|TRCSSCSR3}}, x4 // encoding: [0x44,0x1b,0x11,0xd5] +// CHECK: msr {{trcsscsr4|TRCSSCSR4}}, x14 // encoding: [0x4e,0x1c,0x11,0xd5] +// CHECK: msr {{trcsscsr5|TRCSSCSR5}}, x22 // encoding: [0x56,0x1d,0x11,0xd5] +// CHECK: msr {{trcsscsr6|TRCSSCSR6}}, x3 // encoding: [0x43,0x1e,0x11,0xd5] +// CHECK: msr {{trcsscsr7|TRCSSCSR7}}, x11 // encoding: [0x4b,0x1f,0x11,0xd5] +// CHECK: msr {{trcsspcicr0|TRCSSPCICR0}}, x2 // encoding: [0x62,0x10,0x11,0xd5] +// CHECK: msr {{trcsspcicr1|TRCSSPCICR1}}, x3 // encoding: [0x63,0x11,0x11,0xd5] +// CHECK: msr {{trcsspcicr2|TRCSSPCICR2}}, x5 // encoding: [0x65,0x12,0x11,0xd5] +// CHECK: msr {{trcsspcicr3|TRCSSPCICR3}}, x7 // encoding: [0x67,0x13,0x11,0xd5] +// CHECK: msr {{trcsspcicr4|TRCSSPCICR4}}, x11 // encoding: [0x6b,0x14,0x11,0xd5] +// CHECK: msr {{trcsspcicr5|TRCSSPCICR5}}, x13 // encoding: [0x6d,0x15,0x11,0xd5] +// CHECK: msr {{trcsspcicr6|TRCSSPCICR6}}, x17 // encoding: [0x71,0x16,0x11,0xd5] +// CHECK: msr {{trcsspcicr7|TRCSSPCICR7}}, x23 // encoding: [0x77,0x17,0x11,0xd5] +// CHECK: msr {{trcpdcr|TRCPDCR}}, x3 // encoding: [0x83,0x14,0x11,0xd5] +// CHECK: msr {{trcacvr0|TRCACVR0}}, x6 // encoding: [0x06,0x20,0x11,0xd5] +// CHECK: msr {{trcacvr1|TRCACVR1}}, x20 // encoding: [0x14,0x22,0x11,0xd5] +// CHECK: msr {{trcacvr2|TRCACVR2}}, x25 // encoding: [0x19,0x24,0x11,0xd5] +// CHECK: msr {{trcacvr3|TRCACVR3}}, x1 // encoding: [0x01,0x26,0x11,0xd5] +// CHECK: msr {{trcacvr4|TRCACVR4}}, x28 // encoding: [0x1c,0x28,0x11,0xd5] +// CHECK: msr {{trcacvr5|TRCACVR5}}, x15 // encoding: [0x0f,0x2a,0x11,0xd5] +// CHECK: msr {{trcacvr6|TRCACVR6}}, x25 // encoding: [0x19,0x2c,0x11,0xd5] +// CHECK: msr {{trcacvr7|TRCACVR7}}, x12 // encoding: [0x0c,0x2e,0x11,0xd5] +// CHECK: msr {{trcacvr8|TRCACVR8}}, x5 // encoding: [0x25,0x20,0x11,0xd5] +// CHECK: msr {{trcacvr9|TRCACVR9}}, x25 // encoding: [0x39,0x22,0x11,0xd5] +// CHECK: msr {{trcacvr10|TRCACVR10}}, x13 // encoding: [0x2d,0x24,0x11,0xd5] +// CHECK: msr {{trcacvr11|TRCACVR11}}, x10 // encoding: [0x2a,0x26,0x11,0xd5] +// CHECK: msr {{trcacvr12|TRCACVR12}}, x19 // encoding: [0x33,0x28,0x11,0xd5] +// CHECK: msr {{trcacvr13|TRCACVR13}}, x10 // encoding: [0x2a,0x2a,0x11,0xd5] +// CHECK: msr {{trcacvr14|TRCACVR14}}, x19 // encoding: [0x33,0x2c,0x11,0xd5] +// CHECK: msr {{trcacvr15|TRCACVR15}}, x2 // encoding: [0x22,0x2e,0x11,0xd5] +// CHECK: msr {{trcacatr0|TRCACATR0}}, x15 // encoding: [0x4f,0x20,0x11,0xd5] +// CHECK: msr {{trcacatr1|TRCACATR1}}, x13 // encoding: [0x4d,0x22,0x11,0xd5] +// CHECK: msr {{trcacatr2|TRCACATR2}}, x8 // encoding: [0x48,0x24,0x11,0xd5] +// CHECK: msr {{trcacatr3|TRCACATR3}}, x1 // encoding: [0x41,0x26,0x11,0xd5] +// CHECK: msr {{trcacatr4|TRCACATR4}}, x11 // encoding: [0x4b,0x28,0x11,0xd5] +// CHECK: msr {{trcacatr5|TRCACATR5}}, x8 // encoding: [0x48,0x2a,0x11,0xd5] +// CHECK: msr {{trcacatr6|TRCACATR6}}, x24 // encoding: [0x58,0x2c,0x11,0xd5] +// CHECK: msr {{trcacatr7|TRCACATR7}}, x6 // encoding: [0x46,0x2e,0x11,0xd5] +// CHECK: msr {{trcacatr8|TRCACATR8}}, x23 // encoding: [0x77,0x20,0x11,0xd5] +// CHECK: msr {{trcacatr9|TRCACATR9}}, x5 // encoding: [0x65,0x22,0x11,0xd5] +// CHECK: msr {{trcacatr10|TRCACATR10}}, x11 // encoding: [0x6b,0x24,0x11,0xd5] +// CHECK: msr {{trcacatr11|TRCACATR11}}, x11 // encoding: [0x6b,0x26,0x11,0xd5] +// CHECK: msr {{trcacatr12|TRCACATR12}}, x3 // encoding: [0x63,0x28,0x11,0xd5] +// CHECK: msr {{trcacatr13|TRCACATR13}}, x28 // encoding: [0x7c,0x2a,0x11,0xd5] +// CHECK: msr {{trcacatr14|TRCACATR14}}, x25 // encoding: [0x79,0x2c,0x11,0xd5] +// CHECK: msr {{trcacatr15|TRCACATR15}}, x4 // encoding: [0x64,0x2e,0x11,0xd5] +// CHECK: msr {{trcdvcvr0|TRCDVCVR0}}, x6 // encoding: [0x86,0x20,0x11,0xd5] +// CHECK: msr {{trcdvcvr1|TRCDVCVR1}}, x3 // encoding: [0x83,0x24,0x11,0xd5] +// CHECK: msr {{trcdvcvr2|TRCDVCVR2}}, x5 // encoding: [0x85,0x28,0x11,0xd5] +// CHECK: msr {{trcdvcvr3|TRCDVCVR3}}, x11 // encoding: [0x8b,0x2c,0x11,0xd5] +// CHECK: msr {{trcdvcvr4|TRCDVCVR4}}, x9 // encoding: [0xa9,0x20,0x11,0xd5] +// CHECK: msr {{trcdvcvr5|TRCDVCVR5}}, x14 // encoding: [0xae,0x24,0x11,0xd5] +// CHECK: msr {{trcdvcvr6|TRCDVCVR6}}, x10 // encoding: [0xaa,0x28,0x11,0xd5] +// CHECK: msr {{trcdvcvr7|TRCDVCVR7}}, x12 // encoding: [0xac,0x2c,0x11,0xd5] +// CHECK: msr {{trcdvcmr0|TRCDVCMR0}}, x8 // encoding: [0xc8,0x20,0x11,0xd5] +// CHECK: msr {{trcdvcmr1|TRCDVCMR1}}, x8 // encoding: [0xc8,0x24,0x11,0xd5] +// CHECK: msr {{trcdvcmr2|TRCDVCMR2}}, x22 // encoding: [0xd6,0x28,0x11,0xd5] +// CHECK: msr {{trcdvcmr3|TRCDVCMR3}}, x22 // encoding: [0xd6,0x2c,0x11,0xd5] +// CHECK: msr {{trcdvcmr4|TRCDVCMR4}}, x5 // encoding: [0xe5,0x20,0x11,0xd5] +// CHECK: msr {{trcdvcmr5|TRCDVCMR5}}, x16 // encoding: [0xf0,0x24,0x11,0xd5] +// CHECK: msr {{trcdvcmr6|TRCDVCMR6}}, x27 // encoding: [0xfb,0x28,0x11,0xd5] +// CHECK: msr {{trcdvcmr7|TRCDVCMR7}}, x21 // encoding: [0xf5,0x2c,0x11,0xd5] +// CHECK: msr {{trccidcvr0|TRCCIDCVR0}}, x8 // encoding: [0x08,0x30,0x11,0xd5] +// CHECK: msr {{trccidcvr1|TRCCIDCVR1}}, x6 // encoding: [0x06,0x32,0x11,0xd5] +// CHECK: msr {{trccidcvr2|TRCCIDCVR2}}, x9 // encoding: [0x09,0x34,0x11,0xd5] +// CHECK: msr {{trccidcvr3|TRCCIDCVR3}}, x8 // encoding: [0x08,0x36,0x11,0xd5] +// CHECK: msr {{trccidcvr4|TRCCIDCVR4}}, x3 // encoding: [0x03,0x38,0x11,0xd5] +// CHECK: msr {{trccidcvr5|TRCCIDCVR5}}, x21 // encoding: [0x15,0x3a,0x11,0xd5] +// CHECK: msr {{trccidcvr6|TRCCIDCVR6}}, x12 // encoding: [0x0c,0x3c,0x11,0xd5] +// CHECK: msr {{trccidcvr7|TRCCIDCVR7}}, x7 // encoding: [0x07,0x3e,0x11,0xd5] +// CHECK: msr {{trcvmidcvr0|TRCVMIDCVR0}}, x4 // encoding: [0x24,0x30,0x11,0xd5] +// CHECK: msr {{trcvmidcvr1|TRCVMIDCVR1}}, x3 // encoding: [0x23,0x32,0x11,0xd5] +// CHECK: msr {{trcvmidcvr2|TRCVMIDCVR2}}, x9 // encoding: [0x29,0x34,0x11,0xd5] +// CHECK: msr {{trcvmidcvr3|TRCVMIDCVR3}}, x17 // encoding: [0x31,0x36,0x11,0xd5] +// CHECK: msr {{trcvmidcvr4|TRCVMIDCVR4}}, x14 // encoding: [0x2e,0x38,0x11,0xd5] +// CHECK: msr {{trcvmidcvr5|TRCVMIDCVR5}}, x12 // encoding: [0x2c,0x3a,0x11,0xd5] +// CHECK: msr {{trcvmidcvr6|TRCVMIDCVR6}}, x10 // encoding: [0x2a,0x3c,0x11,0xd5] +// CHECK: msr {{trcvmidcvr7|TRCVMIDCVR7}}, x3 // encoding: [0x23,0x3e,0x11,0xd5] +// CHECK: msr {{trccidcctlr0|TRCCIDCCTLR0}}, x14 // encoding: [0x4e,0x30,0x11,0xd5] +// CHECK: msr {{trccidcctlr1|TRCCIDCCTLR1}}, x22 // encoding: [0x56,0x31,0x11,0xd5] +// CHECK: msr {{trcvmidcctlr0|TRCVMIDCCTLR0}}, x8 // encoding: [0x48,0x32,0x11,0xd5] +// CHECK: msr {{trcvmidcctlr1|TRCVMIDCCTLR1}}, x15 // encoding: [0x4f,0x33,0x11,0xd5] +// CHECK: msr {{trcitctrl|TRCITCTRL}}, x1 // encoding: [0x81,0x70,0x11,0xd5] +// CHECK: msr {{trcclaimset|TRCCLAIMSET}}, x7 // encoding: [0xc7,0x78,0x11,0xd5] +// CHECK: msr {{trcclaimclr|TRCCLAIMCLR}}, x29 // encoding: [0xdd,0x79,0x11,0xd5] diff --git a/test/MC/ARM/Windows/mov32t-range.s b/test/MC/ARM/Windows/mov32t-range.s new file mode 100644 index 0000000..fef8ff2 --- /dev/null +++ b/test/MC/ARM/Windows/mov32t-range.s @@ -0,0 +1,37 @@ +@ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \ +@ RUN: | llvm-readobj -r - | FileCheck -check-prefix CHECK-RELOCATIONS %s + +@ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \ +@ RUN: | llvm-objdump -d - | FileCheck -check-prefix CHECK-ENCODING %s + + .syntax unified + .thumb + .text + + .def truncation + .scl 3 + .type 32 + .endef + .align 2 + .thumb_func +truncation: + movw r0, :lower16:.Lerange + movt r0, :upper16:.Lerange + bx lr + + .section .rdata,"rd" +.Lbuffer: + .zero 65536 +.Lerange: + .asciz "-erange" + +@ CHECK-RELOCATIONS: Relocations [ +@ CHECK-RELOCATIONS: .text { +@ CHECK-RELOCATIONS: 0x0 IMAGE_REL_ARM_MOV32T .rdata +@ CHECK-RELOCATIONS-NOT: 0x4 IMAGE_REL_ARM_MOV32T .rdata +@ CHECK-RELOCATIONS: } +@ CHECK-RELOCATIONS: ] + +@ CHECK-ENCODING: 0: 40 f2 00 00 +@ CHECK-ENCODING-NEXT: 4: c0 f2 01 00 + diff --git a/test/MC/ARM/arm-thumb-cpus-default.s b/test/MC/ARM/arm-thumb-cpus-default.s index 636ee3c..d7a1849 100644 --- a/test/MC/ARM/arm-thumb-cpus-default.s +++ b/test/MC/ARM/arm-thumb-cpus-default.s @@ -1,9 +1,20 @@ -@ RUN: llvm-mc -show-encoding -arch=arm < %s | FileCheck %s --check-prefix=CHECK-ARM-ONLY -@ RUN: llvm-mc -show-encoding -triple=armv4t < %s | FileCheck %s --check-prefix=CHECK-ARM-THUMB -@ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-a15 < %s| FileCheck %s --check-prefix=CHECK-ARM-THUMB -@ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-THUMB-ONLY -@ RUN: llvm-mc -show-encoding -triple=armv7m < %s | FileCheck %s --check-prefix=CHECK-THUMB-ONLY -@ RUN: llvm-mc -show-encoding -triple=armv6m < %s | FileCheck %s --check-prefix=CHECK-THUMB-ONLY +@ RUN: llvm-mc -show-encoding -triple=arm-eabi < %s \ +@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-ONLY + +@ RUN: llvm-mc -show-encoding -triple=armv4t-eabi < %s \ +@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-THUMB + +@ RUN: llvm-mc -show-encoding -triple=arm-eabi -mcpu=cortex-a15 < %s \ +@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-THUMB + +@ RUN: llvm-mc -show-encoding -triple=arm-eabi -mcpu=cortex-m3 < %s \ +@ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY + +@ RUN: llvm-mc -show-encoding -triple=armv7m-eabi < %s \ +@ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY + +@ RUN: llvm-mc -show-encoding -triple=armv6m-eabi < %s \ +@ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY @ Make sure the architecture chosen by LLVM defaults to a compatible @ ARM/Thumb mode. diff --git a/test/MC/ARM/arm-thumb-cpus.s b/test/MC/ARM/arm-thumb-cpus.s index 24be989..9005c7f 100644 --- a/test/MC/ARM/arm-thumb-cpus.s +++ b/test/MC/ARM/arm-thumb-cpus.s @@ -1,9 +1,20 @@ -@ RUN: not llvm-mc -show-encoding -arch=arm < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ARM-ONLY -@ RUN: llvm-mc -show-encoding -triple=armv4t < %s 2>&1| FileCheck %s --check-prefix=CHECK-ARM-THUMB -@ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-a15 < %s 2>&1| FileCheck %s --check-prefix=CHECK-ARM-THUMB -@ RUN: not llvm-mc -show-encoding -arch=arm -mcpu=cortex-m3 < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY -@ RUN: not llvm-mc -show-encoding -triple=armv7m < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY -@ RUN: not llvm-mc -show-encoding -triple=armv6m < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY +@ RUN: not llvm-mc -show-encoding -triple=arm-eabi < %s 2>&1 \ +@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-ONLY + +@ RUN: llvm-mc -show-encoding -triple=armv4t < %s 2>&1 \ +@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-THUMB + +@ RUN: llvm-mc -show-encoding -triple=arm-eabi -mcpu=cortex-a15 < %s 2>&1 \ +@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-THUMB + +@ RUN: not llvm-mc -show-encoding -triple=arm-eabi -mcpu=cortex-m3 < %s 2>&1 \ +@ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY + +@ RUN: not llvm-mc -show-encoding -triple=armv7m-eabi < %s 2>&1 \ +@ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY + +@ RUN: not llvm-mc -show-encoding -triple=armv6m-eabi < %s 2>&1 \ +@ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY @ Make sure correct diagnostics are given for CPUs without support for @ one or other of the execution states. diff --git a/test/MC/ARM/arm_fixups.s b/test/MC/ARM/arm_fixups.s index bd6906b..1f56e12 100644 --- a/test/MC/ARM/arm_fixups.s +++ b/test/MC/ARM/arm_fixups.s @@ -26,9 +26,9 @@ @ CHECK-BE: movt r9, :upper16:_foo @ encoding: [0xe3,0b0100AAAA,0x90'A',A] @ CHECK-BE: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_movt_hi16 - mov r2, fred + mov r2, :lower16:fred -@ CHECK: movw r2, fred @ encoding: [A,0x20'A',0b0000AAAA,0xe3] +@ CHECK: movw r2, :lower16:fred @ encoding: [A,0x20'A',0b0000AAAA,0xe3] @ CHECK: @ fixup A - offset: 0, value: fred, kind: fixup_arm_movw_lo16 -@ CHECK-BE: movw r2, fred @ encoding: [0xe3,0b0000AAAA,0x20'A',A] +@ CHECK-BE: movw r2, :lower16:fred @ encoding: [0xe3,0b0000AAAA,0x20'A',A] @ CHECK-BE: @ fixup A - offset: 0, value: fred, kind: fixup_arm_movw_lo16 diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index a8c9cdc..05e0b2b 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -2805,6 +2805,9 @@ _func: strd r0, r1, [r2, #-0] strd r0, r1, [r2, #-0]! strd r0, r1, [r2], #-0 + strd r0, r1, [r2, #256] + strd r0, r1, [r2, #256]! + strd r0, r1, [r2], #256 @ CHECK: strd r3, r5, [r6, #24] @ encoding: [0xc6,0xe9,0x06,0x35] @ CHECK: strd r3, r5, [r6, #24]! @ encoding: [0xe6,0xe9,0x06,0x35] @@ -2815,6 +2818,9 @@ _func: @ CHECK: strd r0, r1, [r2, #-0] @ encoding: [0x42,0xe9,0x00,0x01] @ CHECK: strd r0, r1, [r2, #-0]! @ encoding: [0x62,0xe9,0x00,0x01] @ CHECK: strd r0, r1, [r2], #-0 @ encoding: [0x62,0xe8,0x00,0x01] +@ CHECK: strd r0, r1, [r2, #256] @ encoding: [0xc2,0xe9,0x40,0x01] +@ CHECK: strd r0, r1, [r2, #256]! @ encoding: [0xe2,0xe9,0x40,0x01] +@ CHECK: strd r0, r1, [r2], #256 @ encoding: [0xe2,0xe8,0x40,0x01] @------------------------------------------------------------------------------ diff --git a/test/MC/ARM/big-endian-arm-fixup.s b/test/MC/ARM/big-endian-arm-fixup.s new file mode 100644 index 0000000..5fb9cef --- /dev/null +++ b/test/MC/ARM/big-endian-arm-fixup.s @@ -0,0 +1,107 @@ +// RUN: llvm-mc -triple=armeb-eabi -mattr v7,vfp2 -filetype=obj < %s | llvm-objdump -s - | FileCheck %s + + .syntax unified + .text + .align 2 + .code 32 + +@ARM::fixup_arm_condbl +.section s_condbl,"ax",%progbits +// CHECK-LABEL: Contents of section s_condbl +// CHECK: 0000 0b000002 + bleq condbl_label+16 +condbl_label: + +@ARM::fixup_arm_uncondbl +.section s_uncondbl,"ax",%progbits +// CHECK-LABEL: Contents of section s_uncondbl +// CHECK: 0000 eb000002 + bl uncond_label+16 +uncond_label: + +@ARM::fixup_arm_blx +.section s_blx,"ax",%progbits +// CHECK-LABEL: Contents of section s_blx +// CHECK: 0000 fa000002 + blx blx_label+16 +blx_label: + +@ARM::fixup_arm_uncondbranch +.section s_uncondbranch,"ax",%progbits +// CHECK-LABEL: Contents of section s_uncondbranch +// CHECK: 0000 ea000003 + b uncondbranch_label+16 +uncondbranch_label: + +@ARM::fixup_arm_condbranch +.section s_condbranch,"ax",%progbits +// CHECK-LABEL: Contents of section s_condbranch +// CHECK: 0000 0a000003 + beq condbranch_label+16 +condbranch_label: + +@ARM::fixup_arm_pcrel_10 +.section s_arm_pcrel_10,"ax",%progbits +// CHECK-LABEL: Contents of section s_arm_pcrel_10 +// CHECK: 0000 ed9f0b03 + vldr d0, arm_pcrel_10_label+16 +arm_pcrel_10_label: + +@ARM::fixup_arm_ldst_pcrel_12 +.section s_arm_ldst_pcrel_12,"ax",%progbits +// CHECK-LABEL: Contents of section s_arm_ldst_pcrel_12 +// CHECK: 0000 e59f000c + ldr r0, arm_ldst_pcrel_12_label+16 +arm_ldst_pcrel_12_label: + +@ARM::fixup_arm_adr_pcrel_12 +.section s_arm_adr_pcrel_12,"ax",%progbits +// CHECK-LABEL: Contents of section s_arm_adr_pcrel_12 +// CHECK: 0000 e28f0010 + adr r0, arm_adr_pcrel_12_label+20 +arm_adr_pcrel_12_label: + +@ARM::fixup_arm_adr_pcrel_10_unscaled +.section s_arm_adr_pcrel_10_unscaled,"ax",%progbits +// CHECK-LABEL: Contents of section s_arm_adr_pcrel_10_unscaled +// CHECK: 0000 e1cf01d4 + ldrd r0, r1, arm_adr_pcrel_10_unscaled_label+24 +arm_adr_pcrel_10_unscaled_label: + +@ARM::fixup_arm_movw_lo16 +.section s_movw,"ax",%progbits +// CHECK-LABEL: Contents of section s_movw +// CHECK: 0000 e3000008 + movw r0, :lower16:(some_label+8) + +@ARM::fixup_arm_movt_hi16 +.section s_movt,"ax",%progbits +// CHECK-LABEL: Contents of section s_movt +// CHECK: 0000 e34f0ffc + movt r0, :upper16:GOT-(movt_label) +movt_label: + +@FK_Data_1 +.section s_fk_data_1 +// CHECK-LABEL: Contents of section s_fk_data_1 +// CHECK: 0000 01 +fk_data1_l_label: +.byte fk_data1_h_label-fk_data1_l_label +fk_data1_h_label: + +@FK_Data_2 +.section s_fk_data_2 +// CHECK-LABEL: Contents of section s_fk_data_2 +// CHECK: 0000 0002 +fk_data2_l_label: +.short fk_data2_h_label-fk_data2_l_label +fk_data2_h_label: + +@FK_Data_4 +.section s_fk_data_4 +// CHECK-LABEL: Contents of section s_fk_data_4 +// CHECK: 0000 00000004 +fk_data4_l_label: +.long fk_data4_h_label-fk_data4_l_label +fk_data4_h_label: + diff --git a/test/MC/ARM/big-endian-thumb-fixup.s b/test/MC/ARM/big-endian-thumb-fixup.s new file mode 100644 index 0000000..5023fca --- /dev/null +++ b/test/MC/ARM/big-endian-thumb-fixup.s @@ -0,0 +1,63 @@ +// RUN: llvm-mc -triple=armeb-eabi -mattr v7,vfp2 -filetype=obj < %s | llvm-objdump -s - | FileCheck %s + + .syntax unified + .text + .align 2 + .code 16 + +@ARM::fixup_arm_thumb_bl +.section s_thumb_bl,"ax",%progbits +// CHECK-LABEL: Contents of section s_thumb_bl +// CHECK: 0000 f000f801 + bl thumb_bl_label + nop +thumb_bl_label: + +@ARM::fixup_arm_thumb_blx +// CHECK-LABEL: Contents of section s_thumb_bl +// CHECK: 0000 f000e802 +.section s_thumb_blx,"ax",%progbits + blx thumb_blx_label+8 +thumb_blx_label: + +@ARM::fixup_arm_thumb_br +.section s_thumb_br,"ax",%progbits +// CHECK-LABEL: Contents of section s_thumb_br +// CHECK: 0000 e000bf00 + b thumb_br_label + nop +thumb_br_label: + +@ARM::fixup_arm_thumb_bcc +.section s_thumb_bcc,"ax",%progbits +// CHECK-LABEL: Contents of section s_thumb_bcc +// CHECK: 0000 d000bf00 + beq thumb_bcc_label + nop +thumb_bcc_label: + +@ARM::fixup_arm_thumb_cb +.section s_thumb_cb,"ax",%progbits +// CHECK-LABEL: Contents of section s_thumb_cb +// CHECK: 0000 b100bf00 + cbz r0, thumb_cb_label + nop +thumb_cb_label: + +@ARM::fixup_arm_thumb_cp +.section s_thumb_cp,"ax",%progbits +// CHECK-LABEL: Contents of section s_thumb_cp +// CHECK: 0000 4801bf00 + ldr r0, =thumb_cp_label + nop + nop +thumb_cp_label: + +@ARM::fixup_arm_thumb_adr_pcrel_10 +.section s_thumb_adr_pcrel_10,"ax",%progbits +// CHECK-LABEL: Contents of section s_thumb_adr_pcrel_10 +// CHECK: 0000 a000bf00 + adr r0, thumb_adr_pcrel_10_label + nop +thumb_adr_pcrel_10_label: + diff --git a/test/MC/ARM/big-endian-thumb2-fixup.s b/test/MC/ARM/big-endian-thumb2-fixup.s new file mode 100644 index 0000000..4fd5276 --- /dev/null +++ b/test/MC/ARM/big-endian-thumb2-fixup.s @@ -0,0 +1,49 @@ +// RUN: llvm-mc -triple=thumbeb-eabi -mattr v7,vfp2 -filetype=obj < %s | llvm-objdump -s - | FileCheck %s + + .syntax unified + .text + .align 2 + +@ARM::fixup_t2_movw_lo16 +.section s_movw,"ax",%progbits +// CHECK-LABEL: Contents of section s_movw +// CHECK: 0000 f2400008 + movw r0, :lower16:(some_label+8) + +@ARM::fixup_t2_movt_hi16 +.section s_movt,"ax",%progbits +// CHECK-LABEL: Contents of section s_movt +// CHECK: 0000 f6cf70fc + movt r0, :upper16:GOT-(movt_label) +movt_label: + +@ARM::fixup_t2_uncondbranch +.section s_uncondbranch,"ax",%progbits +// CHECK-LABEL: Contents of section s_uncondbranch +// CHECK: 0000 f000b801 bf00 + b.w uncond_label + nop +uncond_label: + +@ARM::fixup_t2_condbranch +.section s_condbranch,"ax",%progbits +// CHECK-LABEL: Contents of section s_condbranch +// CHECK: 0000 f0008001 bf00 + beq.w cond_label + nop +cond_label: + +@ARM::fixup_t2_ldst_precel_12 +.section s_ldst_precel_12,"ax",%progbits + ldr r0, ldst_precel_12_label + nop + nop +ldst_precel_12_label: + +@ARM::fixup_t2_adr_pcrel_12 +.section s_adr_pcrel_12,"ax",%progbits + adr r0, adr_pcrel_12_label + nop + nop +adr_pcrel_12_label: + diff --git a/test/MC/ARM/coff-debugging-secrel.ll b/test/MC/ARM/coff-debugging-secrel.ll new file mode 100644 index 0000000..f37b19e --- /dev/null +++ b/test/MC/ARM/coff-debugging-secrel.ll @@ -0,0 +1,49 @@ +; RUN: llc -mtriple thumbv7--windows-itanium -filetype obj -o - %s \ +; RUN: | llvm-readobj -r - | FileCheck %s -check-prefix CHECK-ITANIUM + +; RUN: llc -mtriple thumbv7--windows-msvc -filetype obj -o - %s \ +; RUN: | llvm-readobj -r - | FileCheck %s -check-prefix CHECK-MSVC + +; ModuleID = '/Users/compnerd/work/llvm/test/MC/ARM/reduced.c' +target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "thumbv7--windows-itanium" + +define arm_aapcs_vfpcc void @function() { +entry: + ret void, !dbg !0 +} + +!llvm.dbg.cu = !{!7} +!llvm.module.flags = !{!9, !10} + +!0 = metadata !{i32 1, i32 0, metadata !1, null} +!1 = metadata !{i32 786478, metadata !2, metadata !3, metadata !"function", metadata !"function", metadata !"", i32 1, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void ()* @function, null, null, metadata !6, i32 1} ; [ DW_TAG_subprogram ], [line 1], [def], [function] +!2 = metadata !{metadata !"/Users/compnerd/work/llvm/test/MC/ARM/reduced.c", metadata !"/Users/compnerd/work/llvm"} +!3 = metadata !{i32 786473, metadata !2} ; [ DW_TAG_file_type] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c] +!4 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ], [line 0, size 0, align 0, offset 0] [from ] +!5 = metadata !{null} +!6 = metadata !{} +!7 = metadata !{i32 786449, metadata !2, i32 12, metadata !"clang version 3.5.0", i1 false, metadata !"", i32 0, metadata !6, metadata !6, metadata !8, metadata !6, metadata !6, metadata !"", i32 1} ; [ DW_TAG_compile_unit ] [/Users/compnerd/work/llvm/test/MC/ARM/reduced.c] [DW_LANG_C99] +!8 = metadata !{metadata !1} +!9 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} +!10 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} + +; CHECK-ITANIUM: Relocations [ +; CHECK-ITANIUM: Section {{.*}} .debug_info { +; CHECK-ITANIUM: 0x6 IMAGE_REL_ARM_SECREL .debug_abbrev +; CHECK-ITANIUM: 0xC IMAGE_REL_ARM_SECREL .debug_str +; CHECK-ITANIUM: 0x12 IMAGE_REL_ARM_SECREL .debug_str +; CHECK-ITANIUM: 0x16 IMAGE_REL_ARM_SECREL .debug_line +; CHECK-ITANIUM: } +; CHECK-ITANIUM: Section {{.*}}.debug_pubnames { +; CHECK-ITANIUM: 0x6 IMAGE_REL_ARM_SECREL .debug_info +; CHECK-ITANIUM: } +; CHECK-ITANIUM: ] + +; CHECK-MSVC: Relocations [ +; CHECK-MSVC: Section {{.*}} .debug$S { +; CHECK-MSVC: 0xC IMAGE_REL_ARM_SECREL function +; CHECK-MSVC: 0x10 IMAGE_REL_ARM_SECTION function +; CHECK-MSVC: } +; CHECK-MSVC: ] + diff --git a/test/MC/ARM/coff-file.s b/test/MC/ARM/coff-file.s new file mode 100644 index 0000000..f0dd29a --- /dev/null +++ b/test/MC/ARM/coff-file.s @@ -0,0 +1,47 @@ +// RUN: llvm-mc -triple thumbv7-windows -filetype obj %s -o - | llvm-objdump -t - \ +// RUN: | FileCheck %s + +// RUN: llvm-mc -triple thumbv7-windows -filetype obj %s -o - \ +// RUN: | llvm-readobj -symbols | FileCheck %s -check-prefix CHECK-SCN + + .file "null-padded.asm" +// CHECK: (nx 1) {{0x[0-9]+}} .file +// CHECK-NEXT: AUX null-padded.asm{{$}} + + .file "eighteen-chars.asm" + +// CHECK: (nx 1) {{0x[0-9]+}} .file +// CHECK-NEXT: AUX eighteen-chars.asm{{$}} + + .file "multiple-auxiliary-entries.asm" + +// CHECK: (nx 2) {{0x[0-9]+}} .file +// CHECK-NEXT: AUX multiple-auxiliary-entries.asm{{$}} + +// CHECK-SCN: Symbols [ +// CHECK-SCN: Symbol { +// CHECK-SCN: Name: .file +// CHECK-SCN: Section: (65534) +// CHECK-SCN: StorageClass: File +// CHECK-SCN: AuxFileRecord { +// CHECK-SCN: FileName: null-padded.asm +// CHECK-SCN: } +// CHECK-SCN: } +// CHECK-SCN: Symbol { +// CHECK-SCN: Name: .file +// CHECK-SCN: Section: (65534) +// CHECK-SCN: StorageClass: File +// CHECK-SCN: AuxFileRecord { +// CHECK-SCN: FileName: eighteen-chars.asm +// CHECK-SCN: } +// CHECK-SCN: } +// CHECK-SCN: Symbol { +// CHECK-SCN: Name: .file +// CHECK-SCN: Section: (65534) +// CHECK-SCN: StorageClass: File +// CHECK-SCN: AuxFileRecord { +// CHECK-SCN: FileName: multiple-auxiliary-entries.asm +// CHECK-SCN: } +// CHECK-SCN: } +// CHECK-SCN: ] + diff --git a/test/MC/ARM/coff-function-type-info.ll b/test/MC/ARM/coff-function-type-info.ll new file mode 100644 index 0000000..a9f7c18 --- /dev/null +++ b/test/MC/ARM/coff-function-type-info.ll @@ -0,0 +1,45 @@ +; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o - %s \ +; RUN: | FileCheck %s -check-prefix CHECK-ASM + +; RUN: llc -mtriple thumbv7-windows-itanium -filetype obj -o - %s \ +; RUN: | llvm-readobj -t | FileCheck %s -check-prefix CHECK-OBJECT + +define arm_aapcs_vfpcc void @external() { +entry: + ret void +} + +; CHECK-ASM: .def external +; CHECK-ASM: .scl 2 +; CHECK-ASM: .type 32 +; CHECK-ASM: .endef +; CHECK-ASM: .globl external + +define internal arm_aapcs_vfpcc void @internal() { +entry: + ret void +} + +; CHECK-ASM: .def internal +; CHECK-ASM: .scl 3 +; CHECK-ASM: .type 32 +; CHECK-ASM: .endef +; CHECK-ASM-NOT: .globl internal + +; CHECK-OBJECT: Symbol { +; CHECK-OBJECT: Name: external +; CHECK-OBJECT: Section: .text +; CHECK-OBJECT: BaseType: Null +; CHECK-OBJECT: ComplexType: Function +; CHECK-OBJECT: StorageClass: External +; CHECK-OBJECT: AuxSymbolCount: 0 +; CHECK-OBJECT: } +; CHECK-OBJECT: Symbol { +; CHECK-OBJECT: Name: internal +; CHECK-OBJECT: Section: .text +; CHECK-OBJECT: BaseType: Null +; CHECK-OBJECT: ComplexType: Function +; CHECK-OBJECT: StorageClass: Static +; CHECK-OBJECT: AuxSymbolCount: 0 +; CHECK-OBJECT: } + diff --git a/test/MC/ARM/coff-relocations.s b/test/MC/ARM/coff-relocations.s new file mode 100644 index 0000000..6ebae70 --- /dev/null +++ b/test/MC/ARM/coff-relocations.s @@ -0,0 +1,101 @@ +@ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \ +@ RUN: | llvm-readobj -r - | FileCheck %s -check-prefix CHECK-RELOCATION + +@ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \ +@ RUN: | llvm-objdump -d - | FileCheck %s -check-prefix CHECK-ENCODING + + .syntax unified + .text + .thumb + + .global target + + .thumb_func +branch24t: + b target + +@ CHECK-ENCODING-LABEL: branch24t +@ CHECK-ENCODING-NEXT: b.w #0 + + .thumb_func +branch20t: + bcc target + +@ CHECK-ENCODING-LABEL: branch20t +@ CHECK-ENCODING-NEXT: blo.w #0 + + .thumb_func +blx23t: + bl target + +@ CHECK-ENCODING-LABEL: blx23t +@ CHECK-ENCODING-NEXT: bl #0 + + .thumb_func +mov32t: + movw r0, :lower16:target + movt r0, :upper16:target + blx r0 + +@ CHECK-ENCODING-LABEL: mov32t +@ CHECK-ENCODING-NEXT: movw r0, #0 +@ CHECK-ENCODING-NEXT: movt r0, #0 +@ CHECK-ENCODING-NEXT: blx r0 + + .thumb_func +addr32: + ldr r0, .Laddr32 + bx r0 + trap +.Laddr32: + .long target + +@ CHECK-ENCODING-LABEL: addr32 +@ CHECK-ENCODING-NEXT: ldr r0, [pc, #4] +@ CHECK-ENCODING-NEXT: bx r0 +@ CHECK-ENCODING-NEXT: trap +@ CHECK-ENCODING-NEXT: movs r0, r0 +@ CHECK-ENCODING-NEXT: movs r0, r0 + + .thumb_func +addr32nb: + ldr r0, .Laddr32nb + bx r0 + trap +.Laddr32nb: + .long target(imgrel) + +@ CHECK-ENCODING-LABEL: addr32nb +@ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4] +@ CHECK-ENCODING-NEXT: bx r0 +@ CHECK-ENCODING-NEXT: trap +@ CHECK-ENCODING-NEXT: movs r0, r0 +@ CHECK-ENCODING-NEXT: movs r0, r0 + + .thumb_func +secrel: + ldr r0, .Lsecrel + bx r0 + trap +.Lsecrel: + .long target(secrel32) + +@ CHECK-ENCODING-LABEL: secrel +@ CHECK-ENCODING-NEXT: ldr.w r0, [pc, #4] +@ CHECK-ENCODING-NEXT: bx r0 +@ CHECK-ENCODING-NEXT: trap +@ CHECK-ENCODING-NEXT: movs r0, r0 +@ CHECK-ENCODING-NEXT: movs r0, r0 + +@ CHECK-RELOCATION: Relocations [ +@ CHECK-RELOCATION: Section (1) .text { +@ CHCEK-RELOCATION: 0x0 IMAGE_REL_ARM_BRANCH24T +@ CHECK-RELOCATION: 0x4 IMAGE_REL_ARM_BRANCH20T +@ CHECK-RELOCATION: 0x8 IMAGE_REL_ARM_BLX23T +@ CHECK-RELOCATION: 0xC IMAGE_REL_ARM_MOV32T +@ CHECK-RELOCATION: 0x1C IMAGE_REL_ARM_ADDR32 +@ CHECK-RELOCATION: 0x28 IMAGE_REL_ARM_ADDR32NB +@ CHECK-RELOCATION: 0x34 IMAGE_REL_ARM_SECREL +@ CHECK-RELOCATION: } +@ CHECK-RELOCATION: ] + diff --git a/test/MC/ARM/complex-operands.s b/test/MC/ARM/complex-operands.s index 2a721c4..72f8f88 100644 --- a/test/MC/ARM/complex-operands.s +++ b/test/MC/ARM/complex-operands.s @@ -21,20 +21,20 @@ return: .global arm_function .type arm_function,%function arm_function: - mov r0, #(.L_table_end - .L_table_begin) >> 2 + mov r0, #:lower16:((.L_table_end - .L_table_begin) >> 2) blx return @ CHECK-LABEL: arm_function -@ CHECK: movw r0, #(.L_table_end-.L_table_begin)>>2 +@ CHECK: movw r0, :lower16:((.L_table_end-.L_table_begin)>>2) @ CHECK: blx return .global thumb_function .type thumb_function,%function thumb_function: - mov r0, #(.L_table_end - .L_table_begin) >> 2 + mov r0, #:lower16:((.L_table_end - .L_table_begin) >> 2) blx return @ CHECK-LABEL: thumb_function -@ CHECK: movw r0, #(.L_table_end-.L_table_begin)>>2 +@ CHECK: movw r0, :lower16:((.L_table_end-.L_table_begin)>>2) @ CHECK: blx return diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s index 3c26f6d..62d7dae 100644 --- a/test/MC/ARM/diagnostics.s +++ b/test/MC/ARM/diagnostics.s @@ -465,3 +465,11 @@ ldm sp!, {r0}^ @ CHECK-ERRORS: error: system STM cannot have writeback register @ CHECK-ERRORS: error: writeback register only allowed on system LDM if PC in register-list + +foo2: + mov r0, foo2 + movw r0, foo2 +@ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16 +@ CHECK-ERRORS: ^ diff --git a/test/MC/ARM/dwarf-cfi-initial-state.s b/test/MC/ARM/dwarf-cfi-initial-state.s index 2d638e9..0d1c08a 100644 --- a/test/MC/ARM/dwarf-cfi-initial-state.s +++ b/test/MC/ARM/dwarf-cfi-initial-state.s @@ -1,6 +1,7 @@ # RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o - \ # RUN: | llvm-dwarfdump - | FileCheck %s +_proc: .cfi_sections .debug_frame .cfi_startproc bx lr diff --git a/test/MC/ARM/eh-directive-save-diagnoatics.s b/test/MC/ARM/eh-directive-save-diagnostics.s index 0e6d740..0e6d740 100644 --- a/test/MC/ARM/eh-directive-save-diagnoatics.s +++ b/test/MC/ARM/eh-directive-save-diagnostics.s diff --git a/test/MC/ARM/elf-thumbfunc-reloc.s b/test/MC/ARM/elf-thumbfunc-reloc.s index 6147020..ea7d507 100644 --- a/test/MC/ARM/elf-thumbfunc-reloc.s +++ b/test/MC/ARM/elf-thumbfunc-reloc.s @@ -5,7 +5,6 @@ .syntax unified .text - .globl f .align 2 .type f,%function .code 16 @@ -16,9 +15,21 @@ f: bl g pop {r7, pc} + .section .data.rel.local,"aw",%progbits +ptr: + .long f + + @@ make sure an R_ARM_THM_CALL relocation is generated for the call to g @CHECK: Relocations [ @CHECK-NEXT: Section (2) .rel.text { @CHECK-NEXT: 0x4 R_ARM_THM_CALL g 0x0 @CHECK-NEXT: } + + +@@ make sure the relocation is with f. That is one way to make sure it includes +@@ the thumb bit. +@CHECK-NEXT: Section (6) .rel.data.rel.local { +@CHECK-NEXT: 0x0 R_ARM_ABS32 f 0x0 +@CHECK-NEXT: } @CHECK-NEXT: ] diff --git a/test/MC/ARM/elf-thumbfunc.s b/test/MC/ARM/elf-thumbfunc.s index 0ea1182..af061b5 100644 --- a/test/MC/ARM/elf-thumbfunc.s +++ b/test/MC/ARM/elf-thumbfunc.s @@ -11,7 +11,17 @@ foo: bx lr -@@ make sure foo is thumb function: bit 0 = 1 (st_value) + .global bar +bar = foo + +@@ make sure foo and bar are thumb function: bit 0 = 1 (st_value) +@CHECK: Symbol { +@CHECK: Name: bar +@CHECK-NEXT: Value: 0x1 +@CHECK-NEXT: Size: 0 +@CHECK-NEXT: Binding: Global +@CHECK-NEXT: Type: Function + @CHECK: Symbol { @CHECK: Name: foo @CHECK-NEXT: Value: 0x1 diff --git a/test/MC/ARM/ldrd-strd-gnu-arm-bad-imm.s b/test/MC/ARM/ldrd-strd-gnu-arm-bad-imm.s new file mode 100644 index 0000000..fbe459c --- /dev/null +++ b/test/MC/ARM/ldrd-strd-gnu-arm-bad-imm.s @@ -0,0 +1,9 @@ +@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s +.text +@ CHECK: error: instruction requires: thumb2 +@ CHECK: ldrd r0, [r0, #512] + ldrd r0, [r0, #512] + +@ CHECK: error: instruction requires: thumb2 +@ CHECK: strd r0, [r0, #512] + strd r0, [r0, #512] diff --git a/test/MC/ARM/ldrd-strd-gnu-arm.s b/test/MC/ARM/ldrd-strd-gnu-arm.s new file mode 100644 index 0000000..57d21c7 --- /dev/null +++ b/test/MC/ARM/ldrd-strd-gnu-arm.s @@ -0,0 +1,20 @@ +@ PR18921 +@ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s +.text + +@ CHECK-NOT: .code 16 + + +@ CHECK: ldrd r0, r1, [r10, #32]! @ encoding: [0xd0,0x02,0xea,0xe1] +@ CHECK: ldrd r0, r1, [r10], #32 @ encoding: [0xd0,0x02,0xca,0xe0] +@ CHECK: ldrd r0, r1, [r10, #32] @ encoding: [0xd0,0x02,0xca,0xe1] + ldrd r0, [r10, #32]! + ldrd r0, [r10], #32 + ldrd r0, [r10, #32] + +@ CHECK: strd r0, r1, [r10, #32]! @ encoding: [0xf0,0x02,0xea,0xe1] +@ CHECK: strd r0, r1, [r10], #32 @ encoding: [0xf0,0x02,0xca,0xe0] +@ CHECK: strd r0, r1, [r10, #32] @ encoding: [0xf0,0x02,0xca,0xe1] + strd r0, [r10, #32]! + strd r0, [r10], #32 + strd r0, [r10, #32] diff --git a/test/MC/ARM/ldrd-strd-gnu-thumb-bad-regs.s b/test/MC/ARM/ldrd-strd-gnu-thumb-bad-regs.s new file mode 100644 index 0000000..9d81a27 --- /dev/null +++ b/test/MC/ARM/ldrd-strd-gnu-thumb-bad-regs.s @@ -0,0 +1,10 @@ +@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s +.text +.thumb +@ CHECK: error: invalid operand for instruction +@ CHECK: ldrd r12, [r0, #512] + ldrd r12, [r0, #512] + +@ CHECK: error: invalid operand for instruction +@ CHECK: strd r12, [r0, #512] + strd r12, [r0, #512] diff --git a/test/MC/ARM/ldrd-strd-gnu-thumb.s b/test/MC/ARM/ldrd-strd-gnu-thumb.s new file mode 100644 index 0000000..67d2aa7 --- /dev/null +++ b/test/MC/ARM/ldrd-strd-gnu-thumb.s @@ -0,0 +1,20 @@ +@ PR18921 +@ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s +.text +.thumb + +@ CHECK: .code 16 + +@ CHECK: ldrd r0, r1, [r10, #512]! @ encoding: [0xfa,0xe9,0x80,0x01] +@ CHECK: ldrd r0, r1, [r10], #512 @ encoding: [0xfa,0xe8,0x80,0x01] +@ CHECK: ldrd r0, r1, [r10, #512] @ encoding: [0xda,0xe9,0x80,0x01] + ldrd r0, [r10, #512]! + ldrd r0, [r10], #512 + ldrd r0, [r10, #512] + +@ CHECK: strd r0, r1, [r10, #512]! @ encoding: [0xea,0xe9,0x80,0x01] +@ CHECK: strd r0, r1, [r10], #512 @ encoding: [0xea,0xe8,0x80,0x01] +@ CHECK: strd r0, r1, [r10, #512] @ encoding: [0xca,0xe9,0x80,0x01] + strd r0, [r10, #512]! + strd r0, [r10], #512 + strd r0, [r10, #512] diff --git a/test/MC/ARM/neon-vld-encoding.s b/test/MC/ARM/neon-vld-encoding.s index 3fcbe3e..b96784e 100644 --- a/test/MC/ARM/neon-vld-encoding.s +++ b/test/MC/ARM/neon-vld-encoding.s @@ -367,7 +367,7 @@ @ CHECK: vld3.16 {d16[], d17[], d18[]}, [r2]! @ encoding: [0x4d,0x0e,0xe2,0xf4] @ CHECK: vld3.32 {d16[], d17[], d18[]}, [r3]! @ encoding: [0x8d,0x0e,0xe3,0xf4] @ CHECK: vld3.8 {d17[], d18[], d19[]}, [r7]! @ encoding: [0x2d,0x1e,0xe7,0xf4] -@ CHECK: vld3.16 {d17[], d18[], d19[]}, [r7]! @ encoding: [0x6d,0x1e,0xe7,0xf4] +@ CHECK: vld3.16 {d17[], d19[], d21[]}, [r7]! @ encoding: [0x6d,0x1e,0xe7,0xf4] @ CHECK: vld3.32 {d16[], d18[], d20[]}, [r8]! @ encoding: [0xad,0x0e,0xe8,0xf4] @ CHECK: vld3.8 {d16[], d17[], d18[]}, [r1], r8 @ encoding: [0x08,0x0e,0xe1,0xf4] @ CHECK: vld3.16 {d16[], d17[], d18[]}, [r2], r7 @ encoding: [0x47,0x0e,0xe2,0xf4] diff --git a/test/MC/ARM/neon-vld-vst-align.s b/test/MC/ARM/neon-vld-vst-align.s new file mode 100644 index 0000000..c3628ce --- /dev/null +++ b/test/MC/ARM/neon-vld-vst-align.s @@ -0,0 +1,8354 @@ +@ RUN: not llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s > %t 2> %t.err +@ RUN: FileCheck < %t %s +@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t.err %s + + vld1.8 {d0}, [r4] + vld1.8 {d0}, [r4:16] + vld1.8 {d0}, [r4:32] + vld1.8 {d0}, [r4:64] + vld1.8 {d0}, [r4:128] + vld1.8 {d0}, [r4:256] + +@ CHECK: vld1.8 {d0}, [r4] @ encoding: [0x24,0xf9,0x0f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.8 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.8 {d0}, [r4]! + vld1.8 {d0}, [r4:16]! + vld1.8 {d0}, [r4:32]! + vld1.8 {d0}, [r4:64]! + vld1.8 {d0}, [r4:128]! + vld1.8 {d0}, [r4:256]! + +@ CHECK: vld1.8 {d0}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.8 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.8 {d0}, [r4], r6 + vld1.8 {d0}, [r4:16], r6 + vld1.8 {d0}, [r4:32], r6 + vld1.8 {d0}, [r4:64], r6 + vld1.8 {d0}, [r4:128], r6 + vld1.8 {d0}, [r4:256], r6 + +@ CHECK: vld1.8 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.8 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.8 {d0, d1}, [r4] + vld1.8 {d0, d1}, [r4:16] + vld1.8 {d0, d1}, [r4:32] + vld1.8 {d0, d1}, [r4:64] + vld1.8 {d0, d1}, [r4:128] + vld1.8 {d0, d1}, [r4:256] + +@ CHECK: vld1.8 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x0f,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.8 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x0a] +@ CHECK: vld1.8 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.8 {d0, d1}, [r4]! + vld1.8 {d0, d1}, [r4:16]! + vld1.8 {d0, d1}, [r4:32]! + vld1.8 {d0, d1}, [r4:64]! + vld1.8 {d0, d1}, [r4:128]! + vld1.8 {d0, d1}, [r4:256]! + +@ CHECK: vld1.8 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.8 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x0a] +@ CHECK: vld1.8 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.8 {d0, d1}, [r4], r6 + vld1.8 {d0, d1}, [r4:16], r6 + vld1.8 {d0, d1}, [r4:32], r6 + vld1.8 {d0, d1}, [r4:64], r6 + vld1.8 {d0, d1}, [r4:128], r6 + vld1.8 {d0, d1}, [r4:256], r6 + +@ CHECK: vld1.8 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.8 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x0a] +@ CHECK: vld1.8 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.8 {d0, d1, d2}, [r4] + vld1.8 {d0, d1, d2}, [r4:16] + vld1.8 {d0, d1, d2}, [r4:32] + vld1.8 {d0, d1, d2}, [r4:64] + vld1.8 {d0, d1, d2}, [r4:128] + vld1.8 {d0, d1, d2}, [r4:256] + +@ CHECK: vld1.8 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.8 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.8 {d0, d1, d2}, [r4]! + vld1.8 {d0, d1, d2}, [r4:16]! + vld1.8 {d0, d1, d2}, [r4:32]! + vld1.8 {d0, d1, d2}, [r4:64]! + vld1.8 {d0, d1, d2}, [r4:128]! + vld1.8 {d0, d1, d2}, [r4:256]! + +@ CHECK: vld1.8 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.8 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.8 {d0, d1, d2}, [r4], r6 + vld1.8 {d0, d1, d2}, [r4:16], r6 + vld1.8 {d0, d1, d2}, [r4:32], r6 + vld1.8 {d0, d1, d2}, [r4:64], r6 + vld1.8 {d0, d1, d2}, [r4:128], r6 + vld1.8 {d0, d1, d2}, [r4:256], r6 + +@ CHECK: vld1.8 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.8 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.8 {d0, d1, d2, d3}, [r4] + vld1.8 {d0, d1, d2, d3}, [r4:16] + vld1.8 {d0, d1, d2, d3}, [r4:32] + vld1.8 {d0, d1, d2, d3}, [r4:64] + vld1.8 {d0, d1, d2, d3}, [r4:128] + vld1.8 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x0f,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x02] +@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x02] +@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x3f,0x02] + + vld1.8 {d0, d1, d2, d3}, [r4]! + vld1.8 {d0, d1, d2, d3}, [r4:16]! + vld1.8 {d0, d1, d2, d3}, [r4:32]! + vld1.8 {d0, d1, d2, d3}, [r4:64]! + vld1.8 {d0, d1, d2, d3}, [r4:128]! + vld1.8 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x02] +@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x02] +@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x3d,0x02] + + vld1.8 {d0, d1, d2, d3}, [r4], r6 + vld1.8 {d0, d1, d2, d3}, [r4:16], r6 + vld1.8 {d0, d1, d2, d3}, [r4:32], r6 + vld1.8 {d0, d1, d2, d3}, [r4:64], r6 + vld1.8 {d0, d1, d2, d3}, [r4:128], r6 + vld1.8 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x02] +@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x02] +@ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x36,0x02] + + vld1.8 {d0[2]}, [r4] + vld1.8 {d0[2]}, [r4:16] + vld1.8 {d0[2]}, [r4:32] + vld1.8 {d0[2]}, [r4:64] + vld1.8 {d0[2]}, [r4:128] + vld1.8 {d0[2]}, [r4:256] + +@ CHECK: vld1.8 {d0[2]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x00] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.8 {d0[2]}, [r4]! + vld1.8 {d0[2]}, [r4:16]! + vld1.8 {d0[2]}, [r4:32]! + vld1.8 {d0[2]}, [r4:64]! + vld1.8 {d0[2]}, [r4:128]! + vld1.8 {d0[2]}, [r4:256]! + +@ CHECK: vld1.8 {d0[2]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x00] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.8 {d0[2]}, [r4], r6 + vld1.8 {d0[2]}, [r4:16], r6 + vld1.8 {d0[2]}, [r4:32], r6 + vld1.8 {d0[2]}, [r4:64], r6 + vld1.8 {d0[2]}, [r4:128], r6 + vld1.8 {d0[2]}, [r4:256], r6 + +@ CHECK: vld1.8 {d0[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x00] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.8 {d0[]}, [r4] + vld1.8 {d0[]}, [r4:16] + vld1.8 {d0[]}, [r4:32] + vld1.8 {d0[]}, [r4:64] + vld1.8 {d0[]}, [r4:128] + vld1.8 {d0[]}, [r4:256] + +@ CHECK: vld1.8 {d0[]}, [r4] @ encoding: [0xa4,0xf9,0x0f,0x0c] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.8 {d0[]}, [r4]! + vld1.8 {d0[]}, [r4:16]! + vld1.8 {d0[]}, [r4:32]! + vld1.8 {d0[]}, [r4:64]! + vld1.8 {d0[]}, [r4:128]! + vld1.8 {d0[]}, [r4:256]! + +@ CHECK: vld1.8 {d0[]}, [r4]! @ encoding: [0xa4,0xf9,0x0d,0x0c] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.8 {d0[]}, [r4], r6 + vld1.8 {d0[]}, [r4:16], r6 + vld1.8 {d0[]}, [r4:32], r6 + vld1.8 {d0[]}, [r4:64], r6 + vld1.8 {d0[]}, [r4:128], r6 + vld1.8 {d0[]}, [r4:256], r6 + +@ CHECK: vld1.8 {d0[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x06,0x0c] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.8 {d0[], d1[]}, [r4] + vld1.8 {d0[], d1[]}, [r4:16] + vld1.8 {d0[], d1[]}, [r4:32] + vld1.8 {d0[], d1[]}, [r4:64] + vld1.8 {d0[], d1[]}, [r4:128] + vld1.8 {d0[], d1[]}, [r4:256] + +@ CHECK: vld1.8 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x0c] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.8 {d0[], d1[]}, [r4]! + vld1.8 {d0[], d1[]}, [r4:16]! + vld1.8 {d0[], d1[]}, [r4:32]! + vld1.8 {d0[], d1[]}, [r4:64]! + vld1.8 {d0[], d1[]}, [r4:128]! + vld1.8 {d0[], d1[]}, [r4:256]! + +@ CHECK: vld1.8 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x0c] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.8 {d0[], d1[]}, [r4], r6 + vld1.8 {d0[], d1[]}, [r4:16], r6 + vld1.8 {d0[], d1[]}, [r4:32], r6 + vld1.8 {d0[], d1[]}, [r4:64], r6 + vld1.8 {d0[], d1[]}, [r4:128], r6 + vld1.8 {d0[], d1[]}, [r4:256], r6 + +@ CHECK: vld1.8 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x0c] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.16 {d0}, [r4] + vld1.16 {d0}, [r4:16] + vld1.16 {d0}, [r4:32] + vld1.16 {d0}, [r4:64] + vld1.16 {d0}, [r4:128] + vld1.16 {d0}, [r4:256] + +@ CHECK: vld1.16 {d0}, [r4] @ encoding: [0x24,0xf9,0x4f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.16 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.16 {d0}, [r4]! + vld1.16 {d0}, [r4:16]! + vld1.16 {d0}, [r4:32]! + vld1.16 {d0}, [r4:64]! + vld1.16 {d0}, [r4:128]! + vld1.16 {d0}, [r4:256]! + +@ CHECK: vld1.16 {d0}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.16 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.16 {d0}, [r4], r6 + vld1.16 {d0}, [r4:16], r6 + vld1.16 {d0}, [r4:32], r6 + vld1.16 {d0}, [r4:64], r6 + vld1.16 {d0}, [r4:128], r6 + vld1.16 {d0}, [r4:256], r6 + +@ CHECK: vld1.16 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.16 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.16 {d0, d1}, [r4] + vld1.16 {d0, d1}, [r4:16] + vld1.16 {d0, d1}, [r4:32] + vld1.16 {d0, d1}, [r4:64] + vld1.16 {d0, d1}, [r4:128] + vld1.16 {d0, d1}, [r4:256] + +@ CHECK: vld1.16 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x4f,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.16 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x0a] +@ CHECK: vld1.16 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.16 {d0, d1}, [r4]! + vld1.16 {d0, d1}, [r4:16]! + vld1.16 {d0, d1}, [r4:32]! + vld1.16 {d0, d1}, [r4:64]! + vld1.16 {d0, d1}, [r4:128]! + vld1.16 {d0, d1}, [r4:256]! + +@ CHECK: vld1.16 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.16 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x0a] +@ CHECK: vld1.16 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.16 {d0, d1}, [r4], r6 + vld1.16 {d0, d1}, [r4:16], r6 + vld1.16 {d0, d1}, [r4:32], r6 + vld1.16 {d0, d1}, [r4:64], r6 + vld1.16 {d0, d1}, [r4:128], r6 + vld1.16 {d0, d1}, [r4:256], r6 + +@ CHECK: vld1.16 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.16 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x0a] +@ CHECK: vld1.16 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.16 {d0, d1, d2}, [r4] + vld1.16 {d0, d1, d2}, [r4:16] + vld1.16 {d0, d1, d2}, [r4:32] + vld1.16 {d0, d1, d2}, [r4:64] + vld1.16 {d0, d1, d2}, [r4:128] + vld1.16 {d0, d1, d2}, [r4:256] + +@ CHECK: vld1.16 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x4f,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.16 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.16 {d0, d1, d2}, [r4]! + vld1.16 {d0, d1, d2}, [r4:16]! + vld1.16 {d0, d1, d2}, [r4:32]! + vld1.16 {d0, d1, d2}, [r4:64]! + vld1.16 {d0, d1, d2}, [r4:128]! + vld1.16 {d0, d1, d2}, [r4:256]! + +@ CHECK: vld1.16 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.16 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.16 {d0, d1, d2}, [r4], r6 + vld1.16 {d0, d1, d2}, [r4:16], r6 + vld1.16 {d0, d1, d2}, [r4:32], r6 + vld1.16 {d0, d1, d2}, [r4:64], r6 + vld1.16 {d0, d1, d2}, [r4:128], r6 + vld1.16 {d0, d1, d2}, [r4:256], r6 + +@ CHECK: vld1.16 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.16 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.16 {d0, d1, d2, d3}, [r4] + vld1.16 {d0, d1, d2, d3}, [r4:16] + vld1.16 {d0, d1, d2, d3}, [r4:32] + vld1.16 {d0, d1, d2, d3}, [r4:64] + vld1.16 {d0, d1, d2, d3}, [r4:128] + vld1.16 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x4f,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x02] +@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x02] +@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x7f,0x02] + + vld1.16 {d0, d1, d2, d3}, [r4]! + vld1.16 {d0, d1, d2, d3}, [r4:16]! + vld1.16 {d0, d1, d2, d3}, [r4:32]! + vld1.16 {d0, d1, d2, d3}, [r4:64]! + vld1.16 {d0, d1, d2, d3}, [r4:128]! + vld1.16 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x02] +@ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x02] +@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x02] +@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x7d,0x02] + + vld1.16 {d0, d1, d2, d3}, [r4], r6 + vld1.16 {d0, d1, d2, d3}, [r4:16], r6 + vld1.16 {d0, d1, d2, d3}, [r4:32], r6 + vld1.16 {d0, d1, d2, d3}, [r4:64], r6 + vld1.16 {d0, d1, d2, d3}, [r4:128], r6 + vld1.16 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x02] +@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x02] +@ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x76,0x02] + + vld1.16 {d0[2]}, [r4] + vld1.16 {d0[2]}, [r4:16] + vld1.16 {d0[2]}, [r4:32] + vld1.16 {d0[2]}, [r4:64] + vld1.16 {d0[2]}, [r4:128] + vld1.16 {d0[2]}, [r4:256] + +@ CHECK: vld1.16 {d0[2]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x04] +@ CHECK: vld1.16 {d0[2]}, [r4:16] @ encoding: [0xa4,0xf9,0x9f,0x04] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.16 {d0[2]}, [r4]! + vld1.16 {d0[2]}, [r4:16]! + vld1.16 {d0[2]}, [r4:32]! + vld1.16 {d0[2]}, [r4:64]! + vld1.16 {d0[2]}, [r4:128]! + vld1.16 {d0[2]}, [r4:256]! + +@ CHECK: vld1.16 {d0[2]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x04] +@ CHECK: vld1.16 {d0[2]}, [r4:16]! @ encoding: [0xa4,0xf9,0x9d,0x04] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.16 {d0[2]}, [r4], r6 + vld1.16 {d0[2]}, [r4:16], r6 + vld1.16 {d0[2]}, [r4:32], r6 + vld1.16 {d0[2]}, [r4:64], r6 + vld1.16 {d0[2]}, [r4:128], r6 + vld1.16 {d0[2]}, [r4:256], r6 + +@ CHECK: vld1.16 {d0[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x04] +@ CHECK: vld1.16 {d0[2]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x96,0x04] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.16 {d0[]}, [r4] + vld1.16 {d0[]}, [r4:16] + vld1.16 {d0[]}, [r4:32] + vld1.16 {d0[]}, [r4:64] + vld1.16 {d0[]}, [r4:128] + vld1.16 {d0[]}, [r4:256] + +@ CHECK: vld1.16 {d0[]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x0c] +@ CHECK: vld1.16 {d0[]}, [r4:16] @ encoding: [0xa4,0xf9,0x5f,0x0c] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.16 {d0[]}, [r4]! + vld1.16 {d0[]}, [r4:16]! + vld1.16 {d0[]}, [r4:32]! + vld1.16 {d0[]}, [r4:64]! + vld1.16 {d0[]}, [r4:128]! + vld1.16 {d0[]}, [r4:256]! + +@ CHECK: vld1.16 {d0[]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x0c] +@ CHECK: vld1.16 {d0[]}, [r4:16]! @ encoding: [0xa4,0xf9,0x5d,0x0c] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.16 {d0[]}, [r4], r6 + vld1.16 {d0[]}, [r4:16], r6 + vld1.16 {d0[]}, [r4:32], r6 + vld1.16 {d0[]}, [r4:64], r6 + vld1.16 {d0[]}, [r4:128], r6 + vld1.16 {d0[]}, [r4:256], r6 + +@ CHECK: vld1.16 {d0[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x0c] +@ CHECK: vld1.16 {d0[]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x56,0x0c] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.16 {d0[], d1[]}, [r4] + vld1.16 {d0[], d1[]}, [r4:16] + vld1.16 {d0[], d1[]}, [r4:32] + vld1.16 {d0[], d1[]}, [r4:64] + vld1.16 {d0[], d1[]}, [r4:128] + vld1.16 {d0[], d1[]}, [r4:256] + +@ CHECK: vld1.16 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x0c] +@ CHECK: vld1.16 {d0[], d1[]}, [r4:16] @ encoding: [0xa4,0xf9,0x7f,0x0c] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.16 {d0[], d1[]}, [r4]! + vld1.16 {d0[], d1[]}, [r4:16]! + vld1.16 {d0[], d1[]}, [r4:32]! + vld1.16 {d0[], d1[]}, [r4:64]! + vld1.16 {d0[], d1[]}, [r4:128]! + vld1.16 {d0[], d1[]}, [r4:256]! + +@ CHECK: vld1.16 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x0c] +@ CHECK: vld1.16 {d0[], d1[]}, [r4:16]! @ encoding: [0xa4,0xf9,0x7d,0x0c] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.16 {d0[], d1[]}, [r4], r6 + vld1.16 {d0[], d1[]}, [r4:16], r6 + vld1.16 {d0[], d1[]}, [r4:32], r6 + vld1.16 {d0[], d1[]}, [r4:64], r6 + vld1.16 {d0[], d1[]}, [r4:128], r6 + vld1.16 {d0[], d1[]}, [r4:256], r6 + +@ CHECK: vld1.16 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x0c] +@ CHECK: vld1.16 {d0[], d1[]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x76,0x0c] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.32 {d0}, [r4] + vld1.32 {d0}, [r4:16] + vld1.32 {d0}, [r4:32] + vld1.32 {d0}, [r4:64] + vld1.32 {d0}, [r4:128] + vld1.32 {d0}, [r4:256] + +@ CHECK: vld1.32 {d0}, [r4] @ encoding: [0x24,0xf9,0x8f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.32 {d0}, [r4]! + vld1.32 {d0}, [r4:16]! + vld1.32 {d0}, [r4:32]! + vld1.32 {d0}, [r4:64]! + vld1.32 {d0}, [r4:128]! + vld1.32 {d0}, [r4:256]! + +@ CHECK: vld1.32 {d0}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.32 {d0}, [r4], r6 + vld1.32 {d0}, [r4:16], r6 + vld1.32 {d0}, [r4:32], r6 + vld1.32 {d0}, [r4:64], r6 + vld1.32 {d0}, [r4:128], r6 + vld1.32 {d0}, [r4:256], r6 + +@ CHECK: vld1.32 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.32 {d0, d1}, [r4] + vld1.32 {d0, d1}, [r4:16] + vld1.32 {d0, d1}, [r4:32] + vld1.32 {d0, d1}, [r4:64] + vld1.32 {d0, d1}, [r4:128] + vld1.32 {d0, d1}, [r4:256] + +@ CHECK: vld1.32 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x8f,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x0a] +@ CHECK: vld1.32 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.32 {d0, d1}, [r4]! + vld1.32 {d0, d1}, [r4:16]! + vld1.32 {d0, d1}, [r4:32]! + vld1.32 {d0, d1}, [r4:64]! + vld1.32 {d0, d1}, [r4:128]! + vld1.32 {d0, d1}, [r4:256]! + +@ CHECK: vld1.32 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x0a] +@ CHECK: vld1.32 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.32 {d0, d1}, [r4], r6 + vld1.32 {d0, d1}, [r4:16], r6 + vld1.32 {d0, d1}, [r4:32], r6 + vld1.32 {d0, d1}, [r4:64], r6 + vld1.32 {d0, d1}, [r4:128], r6 + vld1.32 {d0, d1}, [r4:256], r6 + +@ CHECK: vld1.32 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x0a] +@ CHECK: vld1.32 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.32 {d0, d1, d2}, [r4] + vld1.32 {d0, d1, d2}, [r4:16] + vld1.32 {d0, d1, d2}, [r4:32] + vld1.32 {d0, d1, d2}, [r4:64] + vld1.32 {d0, d1, d2}, [r4:128] + vld1.32 {d0, d1, d2}, [r4:256] + +@ CHECK: vld1.32 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x8f,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.32 {d0, d1, d2}, [r4]! + vld1.32 {d0, d1, d2}, [r4:16]! + vld1.32 {d0, d1, d2}, [r4:32]! + vld1.32 {d0, d1, d2}, [r4:64]! + vld1.32 {d0, d1, d2}, [r4:128]! + vld1.32 {d0, d1, d2}, [r4:256]! + +@ CHECK: vld1.32 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.32 {d0, d1, d2}, [r4], r6 + vld1.32 {d0, d1, d2}, [r4:16], r6 + vld1.32 {d0, d1, d2}, [r4:32], r6 + vld1.32 {d0, d1, d2}, [r4:64], r6 + vld1.32 {d0, d1, d2}, [r4:128], r6 + vld1.32 {d0, d1, d2}, [r4:256], r6 + +@ CHECK: vld1.32 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.32 {d0, d1, d2, d3}, [r4] + vld1.32 {d0, d1, d2, d3}, [r4:16] + vld1.32 {d0, d1, d2, d3}, [r4:32] + vld1.32 {d0, d1, d2, d3}, [r4:64] + vld1.32 {d0, d1, d2, d3}, [r4:128] + vld1.32 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x8f,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x02] +@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x02] +@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0xbf,0x02] + + vld1.32 {d0, d1, d2, d3}, [r4]! + vld1.32 {d0, d1, d2, d3}, [r4:16]! + vld1.32 {d0, d1, d2, d3}, [r4:32]! + vld1.32 {d0, d1, d2, d3}, [r4:64]! + vld1.32 {d0, d1, d2, d3}, [r4:128]! + vld1.32 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x02] +@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x02] +@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0xbd,0x02] + + vld1.32 {d0, d1, d2, d3}, [r4], r6 + vld1.32 {d0, d1, d2, d3}, [r4:16], r6 + vld1.32 {d0, d1, d2, d3}, [r4:32], r6 + vld1.32 {d0, d1, d2, d3}, [r4:64], r6 + vld1.32 {d0, d1, d2, d3}, [r4:128], r6 + vld1.32 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x02] +@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x02] +@ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0xb6,0x02] + + vld1.32 {d0[1]}, [r4] + vld1.32 {d0[1]}, [r4:16] + vld1.32 {d0[1]}, [r4:32] + vld1.32 {d0[1]}, [r4:64] + vld1.32 {d0[1]}, [r4:128] + vld1.32 {d0[1]}, [r4:256] + +@ CHECK: vld1.32 {d0[1]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0[1]}, [r4:32] @ encoding: [0xa4,0xf9,0xbf,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.32 {d0[1]}, [r4]! + vld1.32 {d0[1]}, [r4:16]! + vld1.32 {d0[1]}, [r4:32]! + vld1.32 {d0[1]}, [r4:64]! + vld1.32 {d0[1]}, [r4:128]! + vld1.32 {d0[1]}, [r4:256]! + +@ CHECK: vld1.32 {d0[1]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0[1]}, [r4:32]! @ encoding: [0xa4,0xf9,0xbd,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.32 {d0[1]}, [r4], r6 + vld1.32 {d0[1]}, [r4:16], r6 + vld1.32 {d0[1]}, [r4:32], r6 + vld1.32 {d0[1]}, [r4:64], r6 + vld1.32 {d0[1]}, [r4:128], r6 + vld1.32 {d0[1]}, [r4:256], r6 + +@ CHECK: vld1.32 {d0[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0[1]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0xb6,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.32 {d0[]}, [r4] + vld1.32 {d0[]}, [r4:16] + vld1.32 {d0[]}, [r4:32] + vld1.32 {d0[]}, [r4:64] + vld1.32 {d0[]}, [r4:128] + vld1.32 {d0[]}, [r4:256] + +@ CHECK: vld1.32 {d0[]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0c] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0[]}, [r4:32] @ encoding: [0xa4,0xf9,0x9f,0x0c] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.32 {d0[]}, [r4]! + vld1.32 {d0[]}, [r4:16]! + vld1.32 {d0[]}, [r4:32]! + vld1.32 {d0[]}, [r4:64]! + vld1.32 {d0[]}, [r4:128]! + vld1.32 {d0[]}, [r4:256]! + +@ CHECK: vld1.32 {d0[]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0c] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0[]}, [r4:32]! @ encoding: [0xa4,0xf9,0x9d,0x0c] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.32 {d0[]}, [r4], r6 + vld1.32 {d0[]}, [r4:16], r6 + vld1.32 {d0[]}, [r4:32], r6 + vld1.32 {d0[]}, [r4:64], r6 + vld1.32 {d0[]}, [r4:128], r6 + vld1.32 {d0[]}, [r4:256], r6 + +@ CHECK: vld1.32 {d0[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0c] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x96,0x0c] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.32 {d0[], d1[]}, [r4] + vld1.32 {d0[], d1[]}, [r4:16] + vld1.32 {d0[], d1[]}, [r4:32] + vld1.32 {d0[], d1[]}, [r4:64] + vld1.32 {d0[], d1[]}, [r4:128] + vld1.32 {d0[], d1[]}, [r4:256] + +@ CHECK: vld1.32 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0xaf,0x0c] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0[], d1[]}, [r4:32] @ encoding: [0xa4,0xf9,0xbf,0x0c] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.32 {d0[], d1[]}, [r4]! + vld1.32 {d0[], d1[]}, [r4:16]! + vld1.32 {d0[], d1[]}, [r4:32]! + vld1.32 {d0[], d1[]}, [r4:64]! + vld1.32 {d0[], d1[]}, [r4:128]! + vld1.32 {d0[], d1[]}, [r4:256]! + +@ CHECK: vld1.32 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0xad,0x0c] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0[], d1[]}, [r4:32]! @ encoding: [0xa4,0xf9,0xbd,0x0c] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.32 {d0[], d1[]}, [r4], r6 + vld1.32 {d0[], d1[]}, [r4:16], r6 + vld1.32 {d0[], d1[]}, [r4:32], r6 + vld1.32 {d0[], d1[]}, [r4:64], r6 + vld1.32 {d0[], d1[]}, [r4:128], r6 + vld1.32 {d0[], d1[]}, [r4:256], r6 + +@ CHECK: vld1.32 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0xa6,0x0c] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0[], d1[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0xb6,0x0c] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.32 {d0[1]}, [r4] + vld1.32 {d0[1]}, [r4:16] + vld1.32 {d0[1]}, [r4:32] + vld1.32 {d0[1]}, [r4:64] + vld1.32 {d0[1]}, [r4:128] + vld1.32 {d0[1]}, [r4:256] + +@ CHECK: vld1.32 {d0[1]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0[1]}, [r4:32] @ encoding: [0xa4,0xf9,0xbf,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.32 {d0[1]}, [r4]! + vld1.32 {d0[1]}, [r4:16]! + vld1.32 {d0[1]}, [r4:32]! + vld1.32 {d0[1]}, [r4:64]! + vld1.32 {d0[1]}, [r4:128]! + vld1.32 {d0[1]}, [r4:256]! + +@ CHECK: vld1.32 {d0[1]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0[1]}, [r4:32]! @ encoding: [0xa4,0xf9,0xbd,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.32 {d0[1]}, [r4], r6 + vld1.32 {d0[1]}, [r4:16], r6 + vld1.32 {d0[1]}, [r4:32], r6 + vld1.32 {d0[1]}, [r4:64], r6 + vld1.32 {d0[1]}, [r4:128], r6 + vld1.32 {d0[1]}, [r4:256], r6 + +@ CHECK: vld1.32 {d0[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.32 {d0[1]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0xb6,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.64 {d0}, [r4] + vld1.64 {d0}, [r4:16] + vld1.64 {d0}, [r4:32] + vld1.64 {d0}, [r4:64] + vld1.64 {d0}, [r4:128] + vld1.64 {d0}, [r4:256] + +@ CHECK: vld1.64 {d0}, [r4] @ encoding: [0x24,0xf9,0xcf,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.64 {d0}, [r4:64] @ encoding: [0x24,0xf9,0xdf,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.64 {d0}, [r4]! + vld1.64 {d0}, [r4:16]! + vld1.64 {d0}, [r4:32]! + vld1.64 {d0}, [r4:64]! + vld1.64 {d0}, [r4:128]! + vld1.64 {d0}, [r4:256]! + +@ CHECK: vld1.64 {d0}, [r4]! @ encoding: [0x24,0xf9,0xcd,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.64 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0xdd,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.64 {d0}, [r4], r6 + vld1.64 {d0}, [r4:16], r6 + vld1.64 {d0}, [r4:32], r6 + vld1.64 {d0}, [r4:64], r6 + vld1.64 {d0}, [r4:128], r6 + vld1.64 {d0}, [r4:256], r6 + +@ CHECK: vld1.64 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0xc6,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.64 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0xd6,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.64 {d0, d1}, [r4] + vld1.64 {d0, d1}, [r4:16] + vld1.64 {d0, d1}, [r4:32] + vld1.64 {d0, d1}, [r4:64] + vld1.64 {d0, d1}, [r4:128] + vld1.64 {d0, d1}, [r4:256] + +@ CHECK: vld1.64 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0xcf,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.64 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0xdf,0x0a] +@ CHECK: vld1.64 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0xef,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.64 {d0, d1}, [r4]! + vld1.64 {d0, d1}, [r4:16]! + vld1.64 {d0, d1}, [r4:32]! + vld1.64 {d0, d1}, [r4:64]! + vld1.64 {d0, d1}, [r4:128]! + vld1.64 {d0, d1}, [r4:256]! + +@ CHECK: vld1.64 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0xcd,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.64 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0xdd,0x0a] +@ CHECK: vld1.64 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0xed,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.64 {d0, d1}, [r4], r6 + vld1.64 {d0, d1}, [r4:16], r6 + vld1.64 {d0, d1}, [r4:32], r6 + vld1.64 {d0, d1}, [r4:64], r6 + vld1.64 {d0, d1}, [r4:128], r6 + vld1.64 {d0, d1}, [r4:256], r6 + +@ CHECK: vld1.64 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0xc6,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.64 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0xd6,0x0a] +@ CHECK: vld1.64 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0xe6,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.64 {d0, d1, d2}, [r4] + vld1.64 {d0, d1, d2}, [r4:16] + vld1.64 {d0, d1, d2}, [r4:32] + vld1.64 {d0, d1, d2}, [r4:64] + vld1.64 {d0, d1, d2}, [r4:128] + vld1.64 {d0, d1, d2}, [r4:256] + +@ CHECK: vld1.64 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0xcf,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.64 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0xdf,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vld1.64 {d0, d1, d2}, [r4]! + vld1.64 {d0, d1, d2}, [r4:16]! + vld1.64 {d0, d1, d2}, [r4:32]! + vld1.64 {d0, d1, d2}, [r4:64]! + vld1.64 {d0, d1, d2}, [r4:128]! + vld1.64 {d0, d1, d2}, [r4:256]! + +@ CHECK: vld1.64 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0xcd,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.64 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0xdd,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld1.64 {d0, d1, d2}, [r4], r6 + vld1.64 {d0, d1, d2}, [r4:16], r6 + vld1.64 {d0, d1, d2}, [r4:32], r6 + vld1.64 {d0, d1, d2}, [r4:64], r6 + vld1.64 {d0, d1, d2}, [r4:128], r6 + vld1.64 {d0, d1, d2}, [r4:256], r6 + +@ CHECK: vld1.64 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0xc6,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.64 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0xd6,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld1.64 {d0, d1, d2, d3}, [r4] + vld1.64 {d0, d1, d2, d3}, [r4:16] + vld1.64 {d0, d1, d2, d3}, [r4:32] + vld1.64 {d0, d1, d2, d3}, [r4:64] + vld1.64 {d0, d1, d2, d3}, [r4:128] + vld1.64 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0xcf,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0xdf,0x02] +@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0xef,0x02] +@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0xff,0x02] + + vld1.64 {d0, d1, d2, d3}, [r4]! + vld1.64 {d0, d1, d2, d3}, [r4:16]! + vld1.64 {d0, d1, d2, d3}, [r4:32]! + vld1.64 {d0, d1, d2, d3}, [r4:64]! + vld1.64 {d0, d1, d2, d3}, [r4:128]! + vld1.64 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0xcd,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0xdd,0x02] +@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0xed,0x02] +@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0xfd,0x02] + + vld1.64 {d0, d1, d2, d3}, [r4], r6 + vld1.64 {d0, d1, d2, d3}, [r4:16], r6 + vld1.64 {d0, d1, d2, d3}, [r4:32], r6 + vld1.64 {d0, d1, d2, d3}, [r4:64], r6 + vld1.64 {d0, d1, d2, d3}, [r4:128], r6 + vld1.64 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0xc6,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0xd6,0x02] +@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0xe6,0x02] +@ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0xf6,0x02] + + vld2.8 {d0, d1}, [r4] + vld2.8 {d0, d1}, [r4:16] + vld2.8 {d0, d1}, [r4:32] + vld2.8 {d0, d1}, [r4:64] + vld2.8 {d0, d1}, [r4:128] + vld2.8 {d0, d1}, [r4:256] + +@ CHECK: vld2.8 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x0f,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.8 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x08] +@ CHECK: vld2.8 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.8 {d0, d1}, [r4]! + vld2.8 {d0, d1}, [r4:16]! + vld2.8 {d0, d1}, [r4:32]! + vld2.8 {d0, d1}, [r4:64]! + vld2.8 {d0, d1}, [r4:128]! + vld2.8 {d0, d1}, [r4:256]! + +@ CHECK: vld2.8 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.8 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x08] +@ CHECK: vld2.8 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.8 {d0, d1}, [r4], r6 + vld2.8 {d0, d1}, [r4:16], r6 + vld2.8 {d0, d1}, [r4:32], r6 + vld2.8 {d0, d1}, [r4:64], r6 + vld2.8 {d0, d1}, [r4:128], r6 + vld2.8 {d0, d1}, [r4:256], r6 + +@ CHECK: vld2.8 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.8 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x08] +@ CHECK: vld2.8 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.8 {d0, d2}, [r4] + vld2.8 {d0, d2}, [r4:16] + vld2.8 {d0, d2}, [r4:32] + vld2.8 {d0, d2}, [r4:64] + vld2.8 {d0, d2}, [r4:128] + vld2.8 {d0, d2}, [r4:256] + +@ CHECK: vld2.8 {d0, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.8 {d0, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x09] +@ CHECK: vld2.8 {d0, d2}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.8 {d0, d2}, [r4]! + vld2.8 {d0, d2}, [r4:16]! + vld2.8 {d0, d2}, [r4:32]! + vld2.8 {d0, d2}, [r4:64]! + vld2.8 {d0, d2}, [r4:128]! + vld2.8 {d0, d2}, [r4:256]! + +@ CHECK: vld2.8 {d0, d2}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.8 {d0, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x09] +@ CHECK: vld2.8 {d0, d2}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.8 {d0, d2}, [r4], r6 + vld2.8 {d0, d2}, [r4:16], r6 + vld2.8 {d0, d2}, [r4:32], r6 + vld2.8 {d0, d2}, [r4:64], r6 + vld2.8 {d0, d2}, [r4:128], r6 + vld2.8 {d0, d2}, [r4:256], r6 + +@ CHECK: vld2.8 {d0, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.8 {d0, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x09] +@ CHECK: vld2.8 {d0, d2}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.8 {d0, d1, d2, d3}, [r4] + vld2.8 {d0, d1, d2, d3}, [r4:16] + vld2.8 {d0, d1, d2, d3}, [r4:32] + vld2.8 {d0, d1, d2, d3}, [r4:64] + vld2.8 {d0, d1, d2, d3}, [r4:128] + vld2.8 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x0f,0x03] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x03] +@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x03] +@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x3f,0x03] + + vld2.8 {d0, d1, d2, d3}, [r4]! + vld2.8 {d0, d1, d2, d3}, [r4:16]! + vld2.8 {d0, d1, d2, d3}, [r4:32]! + vld2.8 {d0, d1, d2, d3}, [r4:64]! + vld2.8 {d0, d1, d2, d3}, [r4:128]! + vld2.8 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x03] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x03] +@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x03] +@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x3d,0x03] + + vld2.8 {d0, d1, d2, d3}, [r4], r6 + vld2.8 {d0, d1, d2, d3}, [r4:16], r6 + vld2.8 {d0, d1, d2, d3}, [r4:32], r6 + vld2.8 {d0, d1, d2, d3}, [r4:64], r6 + vld2.8 {d0, d1, d2, d3}, [r4:128], r6 + vld2.8 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x03] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x03] +@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x03] +@ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x36,0x03] + + vld2.8 {d0[2], d1[2]}, [r4] + vld2.8 {d0[2], d1[2]}, [r4:16] + vld2.8 {d0[2], d1[2]}, [r4:32] + vld2.8 {d0[2], d1[2]}, [r4:64] + vld2.8 {d0[2], d1[2]}, [r4:128] + vld2.8 {d0[2], d1[2]}, [r4:256] + +@ CHECK: vld2.8 {d0[2], d1[2]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x01] +@ CHECK: vld2.8 {d0[2], d1[2]}, [r4:16] @ encoding: [0xa4,0xf9,0x5f,0x01] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.8 {d0[2], d1[2]}, [r4]! + vld2.8 {d0[2], d1[2]}, [r4:16]! + vld2.8 {d0[2], d1[2]}, [r4:32]! + vld2.8 {d0[2], d1[2]}, [r4:64]! + vld2.8 {d0[2], d1[2]}, [r4:128]! + vld2.8 {d0[2], d1[2]}, [r4:256]! + +@ CHECK: vld2.8 {d0[2], d1[2]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x01] +@ CHECK: vld2.8 {d0[2], d1[2]}, [r4:16]! @ encoding: [0xa4,0xf9,0x5d,0x01] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.8 {d0[2], d1[2]}, [r4], r6 + vld2.8 {d0[2], d1[2]}, [r4:16], r6 + vld2.8 {d0[2], d1[2]}, [r4:32], r6 + vld2.8 {d0[2], d1[2]}, [r4:64], r6 + vld2.8 {d0[2], d1[2]}, [r4:128], r6 + vld2.8 {d0[2], d1[2]}, [r4:256], r6 + +@ CHECK: vld2.8 {d0[2], d1[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x01] +@ CHECK: vld2.8 {d0[2], d1[2]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x56,0x01] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.8 {d0[], d1[]}, [r4] + vld2.8 {d0[], d1[]}, [r4:16] + vld2.8 {d0[], d1[]}, [r4:32] + vld2.8 {d0[], d1[]}, [r4:64] + vld2.8 {d0[], d1[]}, [r4:128] + vld2.8 {d0[], d1[]}, [r4:256] + +@ CHECK: vld2.8 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x0f,0x0d] +@ CHECK: vld2.8 {d0[], d1[]}, [r4:16] @ encoding: [0xa4,0xf9,0x1f,0x0d] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.8 {d0[], d1[]}, [r4]! + vld2.8 {d0[], d1[]}, [r4:16]! + vld2.8 {d0[], d1[]}, [r4:32]! + vld2.8 {d0[], d1[]}, [r4:64]! + vld2.8 {d0[], d1[]}, [r4:128]! + vld2.8 {d0[], d1[]}, [r4:256]! + +@ CHECK: vld2.8 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x0d,0x0d] +@ CHECK: vld2.8 {d0[], d1[]}, [r4:16]! @ encoding: [0xa4,0xf9,0x1d,0x0d] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.8 {d0[], d1[]}, [r4], r6 + vld2.8 {d0[], d1[]}, [r4:16], r6 + vld2.8 {d0[], d1[]}, [r4:32], r6 + vld2.8 {d0[], d1[]}, [r4:64], r6 + vld2.8 {d0[], d1[]}, [r4:128], r6 + vld2.8 {d0[], d1[]}, [r4:256], r6 + +@ CHECK: vld2.8 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x06,0x0d] +@ CHECK: vld2.8 {d0[], d1[]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x16,0x0d] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.8 {d0[], d2[]}, [r4] + vld2.8 {d0[], d2[]}, [r4:16] + vld2.8 {d0[], d2[]}, [r4:32] + vld2.8 {d0[], d2[]}, [r4:64] + vld2.8 {d0[], d2[]}, [r4:128] + vld2.8 {d0[], d2[]}, [r4:256] + +@ CHECK: vld2.8 {d0[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x0d] +@ CHECK: vld2.8 {d0[], d2[]}, [r4:16] @ encoding: [0xa4,0xf9,0x3f,0x0d] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.8 {d0[], d2[]}, [r4]! + vld2.8 {d0[], d2[]}, [r4:16]! + vld2.8 {d0[], d2[]}, [r4:32]! + vld2.8 {d0[], d2[]}, [r4:64]! + vld2.8 {d0[], d2[]}, [r4:128]! + vld2.8 {d0[], d2[]}, [r4:256]! + +@ CHECK: vld2.8 {d0[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x0d] +@ CHECK: vld2.8 {d0[], d2[]}, [r4:16]! @ encoding: [0xa4,0xf9,0x3d,0x0d] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.8 {d0[], d2[]}, [r4], r6 + vld2.8 {d0[], d2[]}, [r4:16], r6 + vld2.8 {d0[], d2[]}, [r4:32], r6 + vld2.8 {d0[], d2[]}, [r4:64], r6 + vld2.8 {d0[], d2[]}, [r4:128], r6 + vld2.8 {d0[], d2[]}, [r4:256], r6 + +@ CHECK: vld2.8 {d0[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x0d] +@ CHECK: vld2.8 {d0[], d2[]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x36,0x0d] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.16 {d0, d1}, [r4] + vld2.16 {d0, d1}, [r4:16] + vld2.16 {d0, d1}, [r4:32] + vld2.16 {d0, d1}, [r4:64] + vld2.16 {d0, d1}, [r4:128] + vld2.16 {d0, d1}, [r4:256] + +@ CHECK: vld2.16 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x4f,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x08] +@ CHECK: vld2.16 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.16 {d0, d1}, [r4]! + vld2.16 {d0, d1}, [r4:16]! + vld2.16 {d0, d1}, [r4:32]! + vld2.16 {d0, d1}, [r4:64]! + vld2.16 {d0, d1}, [r4:128]! + vld2.16 {d0, d1}, [r4:256]! + +@ CHECK: vld2.16 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x08] +@ CHECK: vld2.16 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.16 {d0, d1}, [r4], r6 + vld2.16 {d0, d1}, [r4:16], r6 + vld2.16 {d0, d1}, [r4:32], r6 + vld2.16 {d0, d1}, [r4:64], r6 + vld2.16 {d0, d1}, [r4:128], r6 + vld2.16 {d0, d1}, [r4:256], r6 + +@ CHECK: vld2.16 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x08] +@ CHECK: vld2.16 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.16 {d0, d2}, [r4] + vld2.16 {d0, d2}, [r4:16] + vld2.16 {d0, d2}, [r4:32] + vld2.16 {d0, d2}, [r4:64] + vld2.16 {d0, d2}, [r4:128] + vld2.16 {d0, d2}, [r4:256] + +@ CHECK: vld2.16 {d0, d2}, [r4] @ encoding: [0x24,0xf9,0x4f,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0, d2}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x09] +@ CHECK: vld2.16 {d0, d2}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.16 {d0, d2}, [r4]! + vld2.16 {d0, d2}, [r4:16]! + vld2.16 {d0, d2}, [r4:32]! + vld2.16 {d0, d2}, [r4:64]! + vld2.16 {d0, d2}, [r4:128]! + vld2.16 {d0, d2}, [r4:256]! + +@ CHECK: vld2.16 {d0, d2}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x09] +@ CHECK: vld2.16 {d0, d2}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.16 {d0, d2}, [r4], r6 + vld2.16 {d0, d2}, [r4:16], r6 + vld2.16 {d0, d2}, [r4:32], r6 + vld2.16 {d0, d2}, [r4:64], r6 + vld2.16 {d0, d2}, [r4:128], r6 + vld2.16 {d0, d2}, [r4:256], r6 + +@ CHECK: vld2.16 {d0, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x09] +@ CHECK: vld2.16 {d0, d2}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.16 {d0, d1, d2, d3}, [r4] + vld2.16 {d0, d1, d2, d3}, [r4:16] + vld2.16 {d0, d1, d2, d3}, [r4:32] + vld2.16 {d0, d1, d2, d3}, [r4:64] + vld2.16 {d0, d1, d2, d3}, [r4:128] + vld2.16 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x4f,0x03] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x03] +@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x03] +@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x7f,0x03] + + vld2.16 {d0, d1, d2, d3}, [r4]! + vld2.16 {d0, d1, d2, d3}, [r4:16]! + vld2.16 {d0, d1, d2, d3}, [r4:32]! + vld2.16 {d0, d1, d2, d3}, [r4:64]! + vld2.16 {d0, d1, d2, d3}, [r4:128]! + vld2.16 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x03] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x03] +@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x03] +@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x7d,0x03] + + vld2.16 {d0, d1, d2, d3}, [r4], r6 + vld2.16 {d0, d1, d2, d3}, [r4:16], r6 + vld2.16 {d0, d1, d2, d3}, [r4:32], r6 + vld2.16 {d0, d1, d2, d3}, [r4:64], r6 + vld2.16 {d0, d1, d2, d3}, [r4:128], r6 + vld2.16 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x03] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x03] +@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x03] +@ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x76,0x03] + + vld2.16 {d0[2], d1[2]}, [r4] + vld2.16 {d0[2], d1[2]}, [r4:16] + vld2.16 {d0[2], d1[2]}, [r4:32] + vld2.16 {d0[2], d1[2]}, [r4:64] + vld2.16 {d0[2], d1[2]}, [r4:128] + vld2.16 {d0[2], d1[2]}, [r4:256] + +@ CHECK: vld2.16 {d0[2], d1[2]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x05] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0[2], d1[2]}, [r4:32] @ encoding: [0xa4,0xf9,0x9f,0x05] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.16 {d0[2], d1[2]}, [r4]! + vld2.16 {d0[2], d1[2]}, [r4:16]! + vld2.16 {d0[2], d1[2]}, [r4:32]! + vld2.16 {d0[2], d1[2]}, [r4:64]! + vld2.16 {d0[2], d1[2]}, [r4:128]! + vld2.16 {d0[2], d1[2]}, [r4:256]! + +@ CHECK: vld2.16 {d0[2], d1[2]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x05] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0[2], d1[2]}, [r4:32]! @ encoding: [0xa4,0xf9,0x9d,0x05] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.16 {d0[2], d1[2]}, [r4], r6 + vld2.16 {d0[2], d1[2]}, [r4:16], r6 + vld2.16 {d0[2], d1[2]}, [r4:32], r6 + vld2.16 {d0[2], d1[2]}, [r4:64], r6 + vld2.16 {d0[2], d1[2]}, [r4:128], r6 + vld2.16 {d0[2], d1[2]}, [r4:256], r6 + +@ CHECK: vld2.16 {d0[2], d1[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x05] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0[2], d1[2]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x96,0x05] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.16 {d0[2], d2[2]}, [r4] + vld2.16 {d0[2], d2[2]}, [r4:16] + vld2.16 {d0[2], d2[2]}, [r4:32] + vld2.16 {d0[2], d2[2]}, [r4:64] + vld2.16 {d0[2], d2[2]}, [r4:128] + vld2.16 {d0[2], d2[2]}, [r4:256] + +@ CHECK: vld2.16 {d0[2], d2[2]}, [r4] @ encoding: [0xa4,0xf9,0xaf,0x05] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0[2], d2[2]}, [r4:32] @ encoding: [0xa4,0xf9,0xbf,0x05] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.16 {d0[2], d2[2]}, [r4]! + vld2.16 {d0[2], d2[2]}, [r4:16]! + vld2.16 {d0[2], d2[2]}, [r4:32]! + vld2.16 {d0[2], d2[2]}, [r4:64]! + vld2.16 {d0[2], d2[2]}, [r4:128]! + vld2.16 {d0[2], d2[2]}, [r4:256]! + +@ CHECK: vld2.16 {d0[2], d1[2]}, [r4]! @ encoding: [0xa4,0xf9,0xad,0x05] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0[2], d1[2]}, [r4:32]! @ encoding: [0xa4,0xf9,0xbd,0x05] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.16 {d0[2], d2[2]}, [r4], r6 + vld2.16 {d0[2], d2[2]}, [r4:16], r6 + vld2.16 {d0[2], d2[2]}, [r4:32], r6 + vld2.16 {d0[2], d2[2]}, [r4:64], r6 + vld2.16 {d0[2], d2[2]}, [r4:128], r6 + vld2.16 {d0[2], d2[2]}, [r4:256], r6 + +@ CHECK: vld2.16 {d0[2], d2[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0xa6,0x05] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0[2], d2[2]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0xb6,0x05] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.16 {d0[], d1[]}, [r4] + vld2.16 {d0[], d1[]}, [r4:16] + vld2.16 {d0[], d1[]}, [r4:32] + vld2.16 {d0[], d1[]}, [r4:64] + vld2.16 {d0[], d1[]}, [r4:128] + vld2.16 {d0[], d1[]}, [r4:256] + +@ CHECK: vld2.16 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x0d] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0[], d1[]}, [r4:32] @ encoding: [0xa4,0xf9,0x5f,0x0d] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.16 {d0[], d1[]}, [r4]! + vld2.16 {d0[], d1[]}, [r4:16]! + vld2.16 {d0[], d1[]}, [r4:32]! + vld2.16 {d0[], d1[]}, [r4:64]! + vld2.16 {d0[], d1[]}, [r4:128]! + vld2.16 {d0[], d1[]}, [r4:256]! + +@ CHECK: vld2.16 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x0d] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0[], d1[]}, [r4:32]! @ encoding: [0xa4,0xf9,0x5d,0x0d] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.16 {d0[], d1[]}, [r4], r6 + vld2.16 {d0[], d1[]}, [r4:16], r6 + vld2.16 {d0[], d1[]}, [r4:32], r6 + vld2.16 {d0[], d1[]}, [r4:64], r6 + vld2.16 {d0[], d1[]}, [r4:128], r6 + vld2.16 {d0[], d1[]}, [r4:256], r6 + +@ CHECK: vld2.16 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x0d] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0[], d1[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x56,0x0d] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.16 {d0[], d2[]}, [r4] + vld2.16 {d0[], d2[]}, [r4:16] + vld2.16 {d0[], d2[]}, [r4:32] + vld2.16 {d0[], d2[]}, [r4:64] + vld2.16 {d0[], d2[]}, [r4:128] + vld2.16 {d0[], d2[]}, [r4:256] + +@ CHECK: vld2.16 {d0[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x0d] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0[], d2[]}, [r4:32] @ encoding: [0xa4,0xf9,0x7f,0x0d] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.16 {d0[], d2[]}, [r4]! + vld2.16 {d0[], d2[]}, [r4:16]! + vld2.16 {d0[], d2[]}, [r4:32]! + vld2.16 {d0[], d2[]}, [r4:64]! + vld2.16 {d0[], d2[]}, [r4:128]! + vld2.16 {d0[], d2[]}, [r4:256]! + +@ CHECK: vld2.16 {d0[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x0d] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0[], d2[]}, [r4:32]! @ encoding: [0xa4,0xf9,0x7d,0x0d] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:256]! + + vld2.16 {d0[], d2[]}, [r4], r6 + vld2.16 {d0[], d2[]}, [r4:16], r6 + vld2.16 {d0[], d2[]}, [r4:32], r6 + vld2.16 {d0[], d2[]}, [r4:64], r6 + vld2.16 {d0[], d2[]}, [r4:128], r6 + vld2.16 {d0[], d2[]}, [r4:256], r6 + +@ CHECK: vld2.16 {d0[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x0d] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.16 {d0[], d2[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x76,0x0d] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.32 {d0, d1}, [r4] + vld2.32 {d0, d1}, [r4:16] + vld2.32 {d0, d1}, [r4:32] + vld2.32 {d0, d1}, [r4:64] + vld2.32 {d0, d1}, [r4:128] + vld2.32 {d0, d1}, [r4:256] + +@ CHECK: vld2.32 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x8f,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x08] +@ CHECK: vld2.32 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.32 {d0, d1}, [r4]! + vld2.32 {d0, d1}, [r4:16]! + vld2.32 {d0, d1}, [r4:32]! + vld2.32 {d0, d1}, [r4:64]! + vld2.32 {d0, d1}, [r4:128]! + vld2.32 {d0, d1}, [r4:256]! + +@ CHECK: vld2.32 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x08] +@ CHECK: vld2.32 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.32 {d0, d1}, [r4], r6 + vld2.32 {d0, d1}, [r4:16], r6 + vld2.32 {d0, d1}, [r4:32], r6 + vld2.32 {d0, d1}, [r4:64], r6 + vld2.32 {d0, d1}, [r4:128], r6 + vld2.32 {d0, d1}, [r4:256], r6 + +@ CHECK: vld2.32 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x08] +@ CHECK: vld2.32 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.32 {d0, d2}, [r4] + vld2.32 {d0, d2}, [r4:16] + vld2.32 {d0, d2}, [r4:32] + vld2.32 {d0, d2}, [r4:64] + vld2.32 {d0, d2}, [r4:128] + vld2.32 {d0, d2}, [r4:256] + +@ CHECK: vld2.32 {d0, d2}, [r4] @ encoding: [0x24,0xf9,0x8f,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0, d2}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x09] +@ CHECK: vld2.32 {d0, d2}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.32 {d0, d2}, [r4]! + vld2.32 {d0, d2}, [r4:16]! + vld2.32 {d0, d2}, [r4:32]! + vld2.32 {d0, d2}, [r4:64]! + vld2.32 {d0, d2}, [r4:128]! + vld2.32 {d0, d2}, [r4:256]! + +@ CHECK: vld2.32 {d0, d2}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x09] +@ CHECK: vld2.32 {d0, d2}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.32 {d0, d2}, [r4], r6 + vld2.32 {d0, d2}, [r4:16], r6 + vld2.32 {d0, d2}, [r4:32], r6 + vld2.32 {d0, d2}, [r4:64], r6 + vld2.32 {d0, d2}, [r4:128], r6 + vld2.32 {d0, d2}, [r4:256], r6 + +@ CHECK: vld2.32 {d0, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x09] +@ CHECK: vld2.32 {d0, d2}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.32 {d0, d1, d2, d3}, [r4] + vld2.32 {d0, d1, d2, d3}, [r4:16] + vld2.32 {d0, d1, d2, d3}, [r4:32] + vld2.32 {d0, d1, d2, d3}, [r4:64] + vld2.32 {d0, d1, d2, d3}, [r4:128] + vld2.32 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x8f,0x03] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x03] +@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x03] +@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0xbf,0x03] + + vld2.32 {d0, d1, d2, d3}, [r4]! + vld2.32 {d0, d1, d2, d3}, [r4:16]! + vld2.32 {d0, d1, d2, d3}, [r4:32]! + vld2.32 {d0, d1, d2, d3}, [r4:64]! + vld2.32 {d0, d1, d2, d3}, [r4:128]! + vld2.32 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x03] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x03] +@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x03] +@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0xbd,0x03] + + vld2.32 {d0, d1, d2, d3}, [r4], r6 + vld2.32 {d0, d1, d2, d3}, [r4:16], r6 + vld2.32 {d0, d1, d2, d3}, [r4:32], r6 + vld2.32 {d0, d1, d2, d3}, [r4:64], r6 + vld2.32 {d0, d1, d2, d3}, [r4:128], r6 + vld2.32 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x03] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x03] +@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x03] +@ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0xb6,0x03] + + vld2.32 {d0[1], d1[1]}, [r4] + vld2.32 {d0[1], d1[1]}, [r4:16] + vld2.32 {d0[1], d1[1]}, [r4:32] + vld2.32 {d0[1], d1[1]}, [r4:64] + vld2.32 {d0[1], d1[1]}, [r4:128] + vld2.32 {d0[1], d1[1]}, [r4:256] + +@ CHECK: vld2.32 {d0[1], d1[1]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0[1], d1[1]}, [r4:64] @ encoding: [0xa4,0xf9,0x9f,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.32 {d0[1], d1[1]}, [r4]! + vld2.32 {d0[1], d1[1]}, [r4:16]! + vld2.32 {d0[1], d1[1]}, [r4:32]! + vld2.32 {d0[1], d1[1]}, [r4:64]! + vld2.32 {d0[1], d1[1]}, [r4:128]! + vld2.32 {d0[1], d1[1]}, [r4:256]! + +@ CHECK: vld2.32 {d0[1], d1[1]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0[1], d1[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0x9d,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.32 {d0[1], d1[1]}, [r4], r6 + vld2.32 {d0[1], d1[1]}, [r4:16], r6 + vld2.32 {d0[1], d1[1]}, [r4:32], r6 + vld2.32 {d0[1], d1[1]}, [r4:64], r6 + vld2.32 {d0[1], d1[1]}, [r4:128], r6 + vld2.32 {d0[1], d1[1]}, [r4:256], r6 + +@ CHECK: vld2.32 {d0[1], d1[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0[1], d1[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x96,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.32 {d0[1], d2[1]}, [r4] + vld2.32 {d0[1], d2[1]}, [r4:16] + vld2.32 {d0[1], d2[1]}, [r4:32] + vld2.32 {d0[1], d2[1]}, [r4:64] + vld2.32 {d0[1], d2[1]}, [r4:128] + vld2.32 {d0[1], d2[1]}, [r4:256] + +@ CHECK: vld2.32 {d0[1], d2[1]}, [r4] @ encoding: [0xa4,0xf9,0xcf,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0[1], d2[1]}, [r4:64] @ encoding: [0xa4,0xf9,0xdf,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.32 {d0[1], d2[1]}, [r4]! + vld2.32 {d0[1], d2[1]}, [r4:16]! + vld2.32 {d0[1], d2[1]}, [r4:32]! + vld2.32 {d0[1], d2[1]}, [r4:64]! + vld2.32 {d0[1], d2[1]}, [r4:128]! + vld2.32 {d0[1], d2[1]}, [r4:256]! + +@ CHECK: vld2.32 {d0[1], d2[1]}, [r4]! @ encoding: [0xa4,0xf9,0xcd,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0[1], d2[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0xdd,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.32 {d0[1], d2[1]}, [r4], r6 + vld2.32 {d0[1], d2[1]}, [r4:16], r6 + vld2.32 {d0[1], d2[1]}, [r4:32], r6 + vld2.32 {d0[1], d2[1]}, [r4:64], r6 + vld2.32 {d0[1], d2[1]}, [r4:128], r6 + vld2.32 {d0[1], d2[1]}, [r4:256], r6 + +@ CHECK: vld2.32 {d0[1], d2[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0xc6,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0[1], d2[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0xd6,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.32 {d0[], d1[]}, [r4] + vld2.32 {d0[], d1[]}, [r4:16] + vld2.32 {d0[], d1[]}, [r4:32] + vld2.32 {d0[], d1[]}, [r4:64] + vld2.32 {d0[], d1[]}, [r4:128] + vld2.32 {d0[], d1[]}, [r4:256] + +@ CHECK: vld2.32 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0d] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0[], d1[]}, [r4:64] @ encoding: [0xa4,0xf9,0x9f,0x0d] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.32 {d0[], d1[]}, [r4]! + vld2.32 {d0[], d1[]}, [r4:16]! + vld2.32 {d0[], d1[]}, [r4:32]! + vld2.32 {d0[], d1[]}, [r4:64]! + vld2.32 {d0[], d1[]}, [r4:128]! + vld2.32 {d0[], d1[]}, [r4:256]! + +@ CHECK: vld2.32 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0d] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0[], d1[]}, [r4:64]! @ encoding: [0xa4,0xf9,0x9d,0x0d] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.32 {d0[], d1[]}, [r4], r6 + vld2.32 {d0[], d1[]}, [r4:16], r6 + vld2.32 {d0[], d1[]}, [r4:32], r6 + vld2.32 {d0[], d1[]}, [r4:64], r6 + vld2.32 {d0[], d1[]}, [r4:128], r6 + vld2.32 {d0[], d1[]}, [r4:256], r6 + +@ CHECK: vld2.32 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0d] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0[], d1[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x96,0x0d] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld2.32 {d0[], d2[]}, [r4] + vld2.32 {d0[], d2[]}, [r4:16] + vld2.32 {d0[], d2[]}, [r4:32] + vld2.32 {d0[], d2[]}, [r4:64] + vld2.32 {d0[], d2[]}, [r4:128] + vld2.32 {d0[], d2[]}, [r4:256] + +@ CHECK: vld2.32 {d0[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0xaf,0x0d] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0[], d2[]}, [r4:64] @ encoding: [0xa4,0xf9,0xbf,0x0d] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld2.32 {d0[], d2[]}, [r4]! + vld2.32 {d0[], d2[]}, [r4:16]! + vld2.32 {d0[], d2[]}, [r4:32]! + vld2.32 {d0[], d2[]}, [r4:64]! + vld2.32 {d0[], d2[]}, [r4:128]! + vld2.32 {d0[], d2[]}, [r4:256]! + +@ CHECK: vld2.32 {d0[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0xad,0x0d] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0[], d2[]}, [r4:64]! @ encoding: [0xa4,0xf9,0xbd,0x0d] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld2.32 {d0[], d2[]}, [r4], r6 + vld2.32 {d0[], d2[]}, [r4:16], r6 + vld2.32 {d0[], d2[]}, [r4:32], r6 + vld2.32 {d0[], d2[]}, [r4:64], r6 + vld2.32 {d0[], d2[]}, [r4:128], r6 + vld2.32 {d0[], d2[]}, [r4:256], r6 + +@ CHECK: vld2.32 {d0[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0xa6,0x0d] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld2.32 {d0[], d2[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0xb6,0x0d] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.8 {d0, d1, d2}, [r4] + vld3.8 {d0, d1, d2}, [r4:16] + vld3.8 {d0, d1, d2}, [r4:32] + vld3.8 {d0, d1, d2}, [r4:64] + vld3.8 {d0, d1, d2}, [r4:128] + vld3.8 {d0, d1, d2}, [r4:256] + +@ CHECK: vld3.8 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld3.8 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.8 {d0, d1, d2}, [r4]! + vld3.8 {d0, d1, d2}, [r4:16]! + vld3.8 {d0, d1, d2}, [r4:32]! + vld3.8 {d0, d1, d2}, [r4:64]! + vld3.8 {d0, d1, d2}, [r4:128]! + vld3.8 {d0, d1, d2}, [r4:256]! + +@ CHECK: vld3.8 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld3.8 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.8 {d0, d1, d2}, [r4], r6 + vld3.8 {d0, d1, d2}, [r4:16], r6 + vld3.8 {d0, d1, d2}, [r4:32], r6 + vld3.8 {d0, d1, d2}, [r4:64], r6 + vld3.8 {d0, d1, d2}, [r4:128], r6 + vld3.8 {d0, d1, d2}, [r4:256], r6 + +@ CHECK: vld3.8 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld3.8 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.8 {d0, d2, d4}, [r4] + vld3.8 {d0, d2, d4}, [r4:16] + vld3.8 {d0, d2, d4}, [r4:32] + vld3.8 {d0, d2, d4}, [r4:64] + vld3.8 {d0, d2, d4}, [r4:128] + vld3.8 {d0, d2, d4}, [r4:256] + +@ CHECK: vld3.8 {d0, d2, d4}, [r4] @ encoding: [0x24,0xf9,0x0f,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld3.8 {d0, d2, d4}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.8 {d0, d2, d4}, [r4]! + vld3.8 {d0, d2, d4}, [r4:16]! + vld3.8 {d0, d2, d4}, [r4:32]! + vld3.8 {d0, d2, d4}, [r4:64]! + vld3.8 {d0, d2, d4}, [r4:128]! + vld3.8 {d0, d2, d4}, [r4:256]! + +@ CHECK: vld3.8 {d0, d2, d4}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld3.8 {d0, d2, d4}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.8 {d0, d2, d4}, [r4], r6 + vld3.8 {d0, d2, d4}, [r4:16], r6 + vld3.8 {d0, d2, d4}, [r4:32], r6 + vld3.8 {d0, d2, d4}, [r4:64], r6 + vld3.8 {d0, d2, d4}, [r4:128], r6 + vld3.8 {d0, d2, d4}, [r4:256], r6 + +@ CHECK: vld3.8 {d0, d2, d4}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld3.8 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.8 {d0[1], d1[1], d2[1]}, [r4] + vld3.8 {d0[1], d1[1], d2[1]}, [r4:16] + vld3.8 {d0[1], d1[1], d2[1]}, [r4:32] + vld3.8 {d0[1], d1[1], d2[1]}, [r4:64] + vld3.8 {d0[1], d1[1], d2[1]}, [r4:128] + vld3.8 {d0[1], d1[1], d2[1]}, [r4:256] + +@ CHECK: vld3.8 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x02] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.8 {d0[1], d1[1], d2[1]}, [r4]! + vld3.8 {d0[1], d1[1], d2[1]}, [r4:16]! + vld3.8 {d0[1], d1[1], d2[1]}, [r4:32]! + vld3.8 {d0[1], d1[1], d2[1]}, [r4:64]! + vld3.8 {d0[1], d1[1], d2[1]}, [r4:128]! + vld3.8 {d0[1], d1[1], d2[1]}, [r4:256]! + +@ CHECK: vld3.8 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x02] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.8 {d0[1], d1[1], d2[1]}, [r4], r6 + vld3.8 {d0[1], d1[1], d2[1]}, [r4:16], r6 + vld3.8 {d0[1], d1[1], d2[1]}, [r4:32], r6 + vld3.8 {d0[1], d1[1], d2[1]}, [r4:64], r6 + vld3.8 {d0[1], d1[1], d2[1]}, [r4:128], r6 + vld3.8 {d0[1], d1[1], d2[1]}, [r4:256], r6 + +@ CHECK: vld3.8 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x02] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.8 {d0[], d1[], d2[]}, [r4] + vld3.8 {d0[], d1[], d2[]}, [r4:16] + vld3.8 {d0[], d1[], d2[]}, [r4:32] + vld3.8 {d0[], d1[], d2[]}, [r4:64] + vld3.8 {d0[], d1[], d2[]}, [r4:128] + vld3.8 {d0[], d1[], d2[]}, [r4:256] + +@ CHECK: vld3.8 {d0[], d1[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0x0f,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.8 {d0[], d1[], d2[]}, [r4]! + vld3.8 {d0[], d1[], d2[]}, [r4:16]! + vld3.8 {d0[], d1[], d2[]}, [r4:32]! + vld3.8 {d0[], d1[], d2[]}, [r4:64]! + vld3.8 {d0[], d1[], d2[]}, [r4:128]! + vld3.8 {d0[], d1[], d2[]}, [r4:256]! + +@ CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x0d,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.8 {d0[], d1[], d2[]}, [r4], r6 + vld3.8 {d0[], d1[], d2[]}, [r4:16], r6 + vld3.8 {d0[], d1[], d2[]}, [r4:32], r6 + vld3.8 {d0[], d1[], d2[]}, [r4:64], r6 + vld3.8 {d0[], d1[], d2[]}, [r4:128], r6 + vld3.8 {d0[], d1[], d2[]}, [r4:256], r6 + +@ CHECK: vld3.8 {d0[], d1[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x06,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.8 {d0[], d2[], d4[]}, [r4] + vld3.8 {d0[], d2[], d4[]}, [r4:16] + vld3.8 {d0[], d2[], d4[]}, [r4:32] + vld3.8 {d0[], d2[], d4[]}, [r4:64] + vld3.8 {d0[], d2[], d4[]}, [r4:128] + vld3.8 {d0[], d2[], d4[]}, [r4:256] + +@ CHECK: vld3.8 {d0[], d2[], d4[]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.8 {d0[], d2[], d4[]}, [r4]! + vld3.8 {d0[], d2[], d4[]}, [r4:16]! + vld3.8 {d0[], d2[], d4[]}, [r4:32]! + vld3.8 {d0[], d2[], d4[]}, [r4:64]! + vld3.8 {d0[], d2[], d4[]}, [r4:128]! + vld3.8 {d0[], d2[], d4[]}, [r4:256]! + +@ CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.8 {d0[], d2[], d4[]}, [r4], r6 + vld3.8 {d0[], d2[], d4[]}, [r4:16], r6 + vld3.8 {d0[], d2[], d4[]}, [r4:32], r6 + vld3.8 {d0[], d2[], d4[]}, [r4:64], r6 + vld3.8 {d0[], d2[], d4[]}, [r4:128], r6 + vld3.8 {d0[], d2[], d4[]}, [r4:256], r6 + +@ CHECK: vld3.8 {d0[], d2[], d4[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.16 {d0, d1, d2}, [r4] + vld3.16 {d0, d1, d2}, [r4:16] + vld3.16 {d0, d1, d2}, [r4:32] + vld3.16 {d0, d1, d2}, [r4:64] + vld3.16 {d0, d1, d2}, [r4:128] + vld3.16 {d0, d1, d2}, [r4:256] + +@ CHECK: vld3.16 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x4f,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld3.16 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.16 {d0, d1, d2}, [r4]! + vld3.16 {d0, d1, d2}, [r4:16]! + vld3.16 {d0, d1, d2}, [r4:32]! + vld3.16 {d0, d1, d2}, [r4:64]! + vld3.16 {d0, d1, d2}, [r4:128]! + vld3.16 {d0, d1, d2}, [r4:256]! + +@ CHECK: vld3.16 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld3.16 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.16 {d0, d1, d2}, [r4], r6 + vld3.16 {d0, d1, d2}, [r4:16], r6 + vld3.16 {d0, d1, d2}, [r4:32], r6 + vld3.16 {d0, d1, d2}, [r4:64], r6 + vld3.16 {d0, d1, d2}, [r4:128], r6 + vld3.16 {d0, d1, d2}, [r4:256], r6 + +@ CHECK: vld3.16 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld3.16 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.16 {d0, d2, d4}, [r4] + vld3.16 {d0, d2, d4}, [r4:16] + vld3.16 {d0, d2, d4}, [r4:32] + vld3.16 {d0, d2, d4}, [r4:64] + vld3.16 {d0, d2, d4}, [r4:128] + vld3.16 {d0, d2, d4}, [r4:256] + +@ CHECK: vld3.16 {d0, d2, d4}, [r4] @ encoding: [0x24,0xf9,0x4f,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld3.16 {d0, d2, d4}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.16 {d0, d2, d4}, [r4]! + vld3.16 {d0, d2, d4}, [r4:16]! + vld3.16 {d0, d2, d4}, [r4:32]! + vld3.16 {d0, d2, d4}, [r4:64]! + vld3.16 {d0, d2, d4}, [r4:128]! + vld3.16 {d0, d2, d4}, [r4:256]! + +@ CHECK: vld3.16 {d0, d2, d4}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld3.16 {d0, d2, d4}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.16 {d0, d2, d4}, [r4], r6 + vld3.16 {d0, d2, d4}, [r4:16], r6 + vld3.16 {d0, d2, d4}, [r4:32], r6 + vld3.16 {d0, d2, d4}, [r4:64], r6 + vld3.16 {d0, d2, d4}, [r4:128], r6 + vld3.16 {d0, d2, d4}, [r4:256], r6 + +@ CHECK: vld3.16 {d0, d2, d4}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld3.16 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.16 {d0[1], d1[1], d2[1]}, [r4] + vld3.16 {d0[1], d1[1], d2[1]}, [r4:16] + vld3.16 {d0[1], d1[1], d2[1]}, [r4:32] + vld3.16 {d0[1], d1[1], d2[1]}, [r4:64] + vld3.16 {d0[1], d1[1], d2[1]}, [r4:128] + vld3.16 {d0[1], d1[1], d2[1]}, [r4:256] + +@ CHECK: vld3.16 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x06] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.16 {d0[1], d1[1], d2[1]}, [r4]! + vld3.16 {d0[1], d1[1], d2[1]}, [r4:16]! + vld3.16 {d0[1], d1[1], d2[1]}, [r4:32]! + vld3.16 {d0[1], d1[1], d2[1]}, [r4:64]! + vld3.16 {d0[1], d1[1], d2[1]}, [r4:128]! + vld3.16 {d0[1], d1[1], d2[1]}, [r4:256]! + +@ CHECK: vld3.16 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x06] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.16 {d0[1], d1[1], d2[1]}, [r4], r6 + vld3.16 {d0[1], d1[1], d2[1]}, [r4:16], r6 + vld3.16 {d0[1], d1[1], d2[1]}, [r4:32], r6 + vld3.16 {d0[1], d1[1], d2[1]}, [r4:64], r6 + vld3.16 {d0[1], d1[1], d2[1]}, [r4:128], r6 + vld3.16 {d0[1], d1[1], d2[1]}, [r4:256], r6 + +@ CHECK: vld3.16 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x06] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.16 {d0[1], d2[1], d4[1]}, [r4] + vld3.16 {d0[1], d2[1], d4[1]}, [r4:16] + vld3.16 {d0[1], d2[1], d4[1]}, [r4:32] + vld3.16 {d0[1], d2[1], d4[1]}, [r4:64] + vld3.16 {d0[1], d2[1], d4[1]}, [r4:128] + vld3.16 {d0[1], d2[1], d4[1]}, [r4:256] + +@ CHECK: vld3.16 {d0[1], d2[1], d4[1]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x06] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.16 {d0[1], d2[1], d4[1]}, [r4]! + vld3.16 {d0[1], d2[1], d4[1]}, [r4:16]! + vld3.16 {d0[1], d2[1], d4[1]}, [r4:32]! + vld3.16 {d0[1], d2[1], d4[1]}, [r4:64]! + vld3.16 {d0[1], d2[1], d4[1]}, [r4:128]! + vld3.16 {d0[1], d2[1], d4[1]}, [r4:256]! + +@ CHECK: vld3.16 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x06] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.16 {d0[1], d2[1], d4[1]}, [r4], r6 + vld3.16 {d0[1], d2[1], d4[1]}, [r4:16], r6 + vld3.16 {d0[1], d2[1], d4[1]}, [r4:32], r6 + vld3.16 {d0[1], d2[1], d4[1]}, [r4:64], r6 + vld3.16 {d0[1], d2[1], d4[1]}, [r4:128], r6 + vld3.16 {d0[1], d2[1], d4[1]}, [r4:256], r6 + +@ CHECK: vld3.16 {d0[1], d2[1], d4[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x06] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.16 {d0[], d1[], d2[]}, [r4] + vld3.16 {d0[], d1[], d2[]}, [r4:16] + vld3.16 {d0[], d1[], d2[]}, [r4:32] + vld3.16 {d0[], d1[], d2[]}, [r4:64] + vld3.16 {d0[], d1[], d2[]}, [r4:128] + vld3.16 {d0[], d1[], d2[]}, [r4:256] + +@ CHECK: vld3.16 {d0[], d1[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.16 {d0[], d1[], d2[]}, [r4]! + vld3.16 {d0[], d1[], d2[]}, [r4:16]! + vld3.16 {d0[], d1[], d2[]}, [r4:32]! + vld3.16 {d0[], d1[], d2[]}, [r4:64]! + vld3.16 {d0[], d1[], d2[]}, [r4:128]! + vld3.16 {d0[], d1[], d2[]}, [r4:256]! + +@ CHECK: vld3.16 {d0[], d1[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.16 {d0[], d1[], d2[]}, [r4], r6 + vld3.16 {d0[], d1[], d2[]}, [r4:16], r6 + vld3.16 {d0[], d1[], d2[]}, [r4:32], r6 + vld3.16 {d0[], d1[], d2[]}, [r4:64], r6 + vld3.16 {d0[], d1[], d2[]}, [r4:128], r6 + vld3.16 {d0[], d1[], d2[]}, [r4:256], r6 + +@ CHECK: vld3.16 {d0[], d1[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.16 {d0[], d2[], d4[]}, [r4] + vld3.16 {d0[], d2[], d4[]}, [r4:16] + vld3.16 {d0[], d2[], d4[]}, [r4:32] + vld3.16 {d0[], d2[], d4[]}, [r4:64] + vld3.16 {d0[], d2[], d4[]}, [r4:128] + vld3.16 {d0[], d2[], d4[]}, [r4:256] + +@ CHECK: vld3.16 {d0[], d2[], d4[]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.16 {d0[], d2[], d4[]}, [r4]! + vld3.16 {d0[], d2[], d4[]}, [r4:16]! + vld3.16 {d0[], d2[], d4[]}, [r4:32]! + vld3.16 {d0[], d2[], d4[]}, [r4:64]! + vld3.16 {d0[], d2[], d4[]}, [r4:128]! + vld3.16 {d0[], d2[], d4[]}, [r4:256]! + +@ CHECK: vld3.16 {d0[], d2[], d4[]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.16 {d0[], d2[], d4[]}, [r4], r6 + vld3.16 {d0[], d2[], d4[]}, [r4:16], r6 + vld3.16 {d0[], d2[], d4[]}, [r4:32], r6 + vld3.16 {d0[], d2[], d4[]}, [r4:64], r6 + vld3.16 {d0[], d2[], d4[]}, [r4:128], r6 + vld3.16 {d0[], d2[], d4[]}, [r4:256], r6 + +@ CHECK: vld3.16 {d0[], d2[], d4[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:256], r6 + + vld3.32 {d0, d1, d2}, [r4] + vld3.32 {d0, d1, d2}, [r4:16] + vld3.32 {d0, d1, d2}, [r4:32] + vld3.32 {d0, d1, d2}, [r4:64] + vld3.32 {d0, d1, d2}, [r4:128] + vld3.32 {d0, d1, d2}, [r4:256] + +@ CHECK: vld3.32 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x8f,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld3.32 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.32 {d0, d1, d2}, [r4]! + vld3.32 {d0, d1, d2}, [r4:16]! + vld3.32 {d0, d1, d2}, [r4:32]! + vld3.32 {d0, d1, d2}, [r4:64]! + vld3.32 {d0, d1, d2}, [r4:128]! + vld3.32 {d0, d1, d2}, [r4:256]! + +@ CHECK: vld3.32 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld3.32 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.32 {d0, d1, d2}, [r4], r6 + vld3.32 {d0, d1, d2}, [r4:16], r6 + vld3.32 {d0, d1, d2}, [r4:32], r6 + vld3.32 {d0, d1, d2}, [r4:64], r6 + vld3.32 {d0, d1, d2}, [r4:128], r6 + vld3.32 {d0, d1, d2}, [r4:256], r6 + +@ CHECK: vld3.32 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld3.32 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.32 {d0, d2, d4}, [r4] + vld3.32 {d0, d2, d4}, [r4:16] + vld3.32 {d0, d2, d4}, [r4:32] + vld3.32 {d0, d2, d4}, [r4:64] + vld3.32 {d0, d2, d4}, [r4:128] + vld3.32 {d0, d2, d4}, [r4:256] + +@ CHECK: vld3.32 {d0, d2, d4}, [r4] @ encoding: [0x24,0xf9,0x8f,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld3.32 {d0, d2, d4}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.32 {d0, d2, d4}, [r4]! + vld3.32 {d0, d2, d4}, [r4:16]! + vld3.32 {d0, d2, d4}, [r4:32]! + vld3.32 {d0, d2, d4}, [r4:64]! + vld3.32 {d0, d2, d4}, [r4:128]! + vld3.32 {d0, d2, d4}, [r4:256]! + +@ CHECK: vld3.32 {d0, d2, d4}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld3.32 {d0, d2, d4}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.32 {d0, d2, d4}, [r4], r6 + vld3.32 {d0, d2, d4}, [r4:16], r6 + vld3.32 {d0, d2, d4}, [r4:32], r6 + vld3.32 {d0, d2, d4}, [r4:64], r6 + vld3.32 {d0, d2, d4}, [r4:128], r6 + vld3.32 {d0, d2, d4}, [r4:256], r6 + +@ CHECK: vld3.32 {d0, d2, d4}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld3.32 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.32 {d0[1], d1[1], d2[1]}, [r4] + vld3.32 {d0[1], d1[1], d2[1]}, [r4:16] + vld3.32 {d0[1], d1[1], d2[1]}, [r4:32] + vld3.32 {d0[1], d1[1], d2[1]}, [r4:64] + vld3.32 {d0[1], d1[1], d2[1]}, [r4:128] + vld3.32 {d0[1], d1[1], d2[1]}, [r4:256] + +@ CHECK: vld3.32 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0a] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.32 {d0[1], d1[1], d2[1]}, [r4]! + vld3.32 {d0[1], d1[1], d2[1]}, [r4:16]! + vld3.32 {d0[1], d1[1], d2[1]}, [r4:32]! + vld3.32 {d0[1], d1[1], d2[1]}, [r4:64]! + vld3.32 {d0[1], d1[1], d2[1]}, [r4:128]! + vld3.32 {d0[1], d1[1], d2[1]}, [r4:256]! + +@ CHECK: vld3.32 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0a] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.32 {d0[1], d1[1], d2[1]}, [r4], r6 + vld3.32 {d0[1], d1[1], d2[1]}, [r4:16], r6 + vld3.32 {d0[1], d1[1], d2[1]}, [r4:32], r6 + vld3.32 {d0[1], d1[1], d2[1]}, [r4:64], r6 + vld3.32 {d0[1], d1[1], d2[1]}, [r4:128], r6 + vld3.32 {d0[1], d1[1], d2[1]}, [r4:256], r6 + +@ CHECK: vld3.32 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0a] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.32 {d0[1], d2[1], d4[1]}, [r4] + vld3.32 {d0[1], d2[1], d4[1]}, [r4:16] + vld3.32 {d0[1], d2[1], d4[1]}, [r4:32] + vld3.32 {d0[1], d2[1], d4[1]}, [r4:64] + vld3.32 {d0[1], d2[1], d4[1]}, [r4:128] + vld3.32 {d0[1], d2[1], d4[1]}, [r4:256] + +@ CHECK: vld3.32 {d0[1], d2[1], d4[1]}, [r4] @ encoding: [0xa4,0xf9,0xcf,0x0a] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.32 {d0[1], d2[1], d4[1]}, [r4]! + vld3.32 {d0[1], d2[1], d4[1]}, [r4:16]! + vld3.32 {d0[1], d2[1], d4[1]}, [r4:32]! + vld3.32 {d0[1], d2[1], d4[1]}, [r4:64]! + vld3.32 {d0[1], d2[1], d4[1]}, [r4:128]! + vld3.32 {d0[1], d2[1], d4[1]}, [r4:256]! + +@ CHECK: vld3.32 {d0[1], d2[1], d4[1]}, [r4]! @ encoding: [0xa4,0xf9,0xcd,0x0a] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.32 {d0[1], d2[1], d4[1]}, [r4], r6 + vld3.32 {d0[1], d2[1], d4[1]}, [r4:16], r6 + vld3.32 {d0[1], d2[1], d4[1]}, [r4:32], r6 + vld3.32 {d0[1], d2[1], d4[1]}, [r4:64], r6 + vld3.32 {d0[1], d2[1], d4[1]}, [r4:128], r6 + vld3.32 {d0[1], d2[1], d4[1]}, [r4:256], r6 + +@ CHECK: vld3.32 {d0[1], d2[1], d4[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0xc6,0x0a] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.32 {d0[], d1[], d2[]}, [r4] + vld3.32 {d0[], d1[], d2[]}, [r4:16] + vld3.32 {d0[], d1[], d2[]}, [r4:32] + vld3.32 {d0[], d1[], d2[]}, [r4:64] + vld3.32 {d0[], d1[], d2[]}, [r4:128] + vld3.32 {d0[], d1[], d2[]}, [r4:256] + +@ CHECK: vld3.32 {d0[], d1[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.32 {d0[], d1[], d2[]}, [r4]! + vld3.32 {d0[], d1[], d2[]}, [r4:16]! + vld3.32 {d0[], d1[], d2[]}, [r4:32]! + vld3.32 {d0[], d1[], d2[]}, [r4:64]! + vld3.32 {d0[], d1[], d2[]}, [r4:128]! + vld3.32 {d0[], d1[], d2[]}, [r4:256]! + +@ CHECK: vld3.32 {d0[], d1[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.32 {d0[], d1[], d2[]}, [r4], r6 + vld3.32 {d0[], d1[], d2[]}, [r4:16], r6 + vld3.32 {d0[], d1[], d2[]}, [r4:32], r6 + vld3.32 {d0[], d1[], d2[]}, [r4:64], r6 + vld3.32 {d0[], d1[], d2[]}, [r4:128], r6 + vld3.32 {d0[], d1[], d2[]}, [r4:256], r6 + +@ CHECK: vld3.32 {d0[], d1[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld3.32 {d0[], d2[], d4[]}, [r4] + vld3.32 {d0[], d2[], d4[]}, [r4:16] + vld3.32 {d0[], d2[], d4[]}, [r4:32] + vld3.32 {d0[], d2[], d4[]}, [r4:64] + vld3.32 {d0[], d2[], d4[]}, [r4:128] + vld3.32 {d0[], d2[], d4[]}, [r4:256] + +@ CHECK: vld3.32 {d0[], d2[], d4[]}, [r4] @ encoding: [0xa4,0xf9,0xaf,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld3.32 {d0[], d2[], d4[]}, [r4]! + vld3.32 {d0[], d2[], d4[]}, [r4:16]! + vld3.32 {d0[], d2[], d4[]}, [r4:32]! + vld3.32 {d0[], d2[], d4[]}, [r4:64]! + vld3.32 {d0[], d2[], d4[]}, [r4:128]! + vld3.32 {d0[], d2[], d4[]}, [r4:256]! + +@ CHECK: vld3.32 {d0[], d2[], d4[]}, [r4]! @ encoding: [0xa4,0xf9,0xad,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld3.32 {d0[], d2[], d4[]}, [r4], r6 + vld3.32 {d0[], d2[], d4[]}, [r4:16], r6 + vld3.32 {d0[], d2[], d4[]}, [r4:32], r6 + vld3.32 {d0[], d2[], d4[]}, [r4:64], r6 + vld3.32 {d0[], d2[], d4[]}, [r4:128], r6 + vld3.32 {d0[], d2[], d4[]}, [r4:256], r6 + +@ CHECK: vld3.32 {d0[], d2[], d4[]}, [r4], r6 @ encoding: [0xa4,0xf9,0xa6,0x0e] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld4.8 {d0, d1, d2, d3}, [r4] + vld4.8 {d0, d1, d2, d3}, [r4:16] + vld4.8 {d0, d1, d2, d3}, [r4:32] + vld4.8 {d0, d1, d2, d3}, [r4:64] + vld4.8 {d0, d1, d2, d3}, [r4:128] + vld4.8 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x0f,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x00] +@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x00] +@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x3f,0x00] + + vld4.8 {d0, d1, d2, d3}, [r4]! + vld4.8 {d0, d1, d2, d3}, [r4:16]! + vld4.8 {d0, d1, d2, d3}, [r4:32]! + vld4.8 {d0, d1, d2, d3}, [r4:64]! + vld4.8 {d0, d1, d2, d3}, [r4:128]! + vld4.8 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x00] +@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x00] +@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x3d,0x00] + + vld4.8 {d0, d1, d2, d3}, [r4], r6 + vld4.8 {d0, d1, d2, d3}, [r4:16], r6 + vld4.8 {d0, d1, d2, d3}, [r4:32], r6 + vld4.8 {d0, d1, d2, d3}, [r4:64], r6 + vld4.8 {d0, d1, d2, d3}, [r4:128], r6 + vld4.8 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x00] +@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x00] +@ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x36,0x00] + + vld4.8 {d0, d2, d4, d6}, [r4] + vld4.8 {d0, d2, d4, d6}, [r4:16] + vld4.8 {d0, d2, d4, d6}, [r4:32] + vld4.8 {d0, d2, d4, d6}, [r4:64] + vld4.8 {d0, d2, d4, d6}, [r4:128] + vld4.8 {d0, d2, d4, d6}, [r4:256] + +@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4] @ encoding: [0x24,0xf9,0x0f,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x01] +@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x01] +@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:256] @ encoding: [0x24,0xf9,0x3f,0x01] + + vld4.8 {d0, d2, d4, d6}, [r4]! + vld4.8 {d0, d2, d4, d6}, [r4:16]! + vld4.8 {d0, d2, d4, d6}, [r4:32]! + vld4.8 {d0, d2, d4, d6}, [r4:64]! + vld4.8 {d0, d2, d4, d6}, [r4:128]! + vld4.8 {d0, d2, d4, d6}, [r4:256]! + +@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x01] +@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x01] +@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:256]! @ encoding: [0x24,0xf9,0x3d,0x01] + + vld4.8 {d0, d2, d4, d6}, [r4], r6 + vld4.8 {d0, d2, d4, d6}, [r4:16], r6 + vld4.8 {d0, d2, d4, d6}, [r4:32], r6 + vld4.8 {d0, d2, d4, d6}, [r4:64], r6 + vld4.8 {d0, d2, d4, d6}, [r4:128], r6 + vld4.8 {d0, d2, d4, d6}, [r4:256], r6 + +@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x01] +@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x01] +@ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:256], r6 @ encoding: [0x24,0xf9,0x36,0x01] + + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4] + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] + +@ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x03] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] @ encoding: [0xa4,0xf9,0x3f,0x03] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]! + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! + +@ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x03] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! @ encoding: [0xa4,0xf9,0x3d,0x03] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 + vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 + +@ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x03] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x36,0x03] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld4.8 {d0[], d1[], d2[], d3[]}, [r4] + vld4.8 {d0[], d1[], d2[], d3[]}, [r4:16] + vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32] + vld4.8 {d0[], d1[], d2[], d3[]}, [r4:64] + vld4.8 {d0[], d1[], d2[], d3[]}, [r4:128] + vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256] + +@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4] @ encoding: [0xa4,0xf9,0x0f,0x0f] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32] @ encoding: [0xa4,0xf9,0x1f,0x0f] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld4.8 {d0[], d1[], d2[], d3[]}, [r4]! + vld4.8 {d0[], d1[], d2[], d3[]}, [r4:16]! + vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]! + vld4.8 {d0[], d1[], d2[], d3[]}, [r4:64]! + vld4.8 {d0[], d1[], d2[], d3[]}, [r4:128]! + vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256]! + +@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4]! @ encoding: [0xa4,0xf9,0x0d,0x0f] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]! @ encoding: [0xa4,0xf9,0x1d,0x0f] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld4.8 {d0[], d1[], d2[], d3[]}, [r4], r6 + vld4.8 {d0[], d1[], d2[], d3[]}, [r4:16], r6 + vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32], r6 + vld4.8 {d0[], d1[], d2[], d3[]}, [r4:64], r6 + vld4.8 {d0[], d1[], d2[], d3[]}, [r4:128], r6 + vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256], r6 + +@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x06,0x0f] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x16,0x0f] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld4.8 {d0[], d2[], d4[], d6[]}, [r4] + vld4.8 {d0[], d2[], d4[], d6[]}, [r4:16] + vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32] + vld4.8 {d0[], d2[], d4[], d6[]}, [r4:64] + vld4.8 {d0[], d2[], d4[], d6[]}, [r4:128] + vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256] + +@ CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x0f] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32] @ encoding: [0xa4,0xf9,0x3f,0x0f] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld4.8 {d0[], d2[], d4[], d6[]}, [r4]! + vld4.8 {d0[], d2[], d4[], d6[]}, [r4:16]! + vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]! + vld4.8 {d0[], d2[], d4[], d6[]}, [r4:64]! + vld4.8 {d0[], d2[], d4[], d6[]}, [r4:128]! + vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256]! + +@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x0f] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]! @ encoding: [0xa4,0xf9,0x3d,0x0f] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld4.8 {d0[], d2[], d4[], d6[]}, [r4], r6 + vld4.8 {d0[], d2[], d4[], d6[]}, [r4:16], r6 + vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r6 + vld4.8 {d0[], d2[], d4[], d6[]}, [r4:64], r6 + vld4.8 {d0[], d2[], d4[], d6[]}, [r4:128], r6 + vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256], r6 + +@ CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x0f] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x36,0x0f] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld4.16 {d0, d1, d2, d3}, [r4] + vld4.16 {d0, d1, d2, d3}, [r4:16] + vld4.16 {d0, d1, d2, d3}, [r4:32] + vld4.16 {d0, d1, d2, d3}, [r4:64] + vld4.16 {d0, d1, d2, d3}, [r4:128] + vld4.16 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x4f,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x00] +@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x00] +@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0x7f,0x00] + + vld4.16 {d0, d1, d2, d3}, [r4]! + vld4.16 {d0, d1, d2, d3}, [r4:16]! + vld4.16 {d0, d1, d2, d3}, [r4:32]! + vld4.16 {d0, d1, d2, d3}, [r4:64]! + vld4.16 {d0, d1, d2, d3}, [r4:128]! + vld4.16 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x00] +@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x00] +@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0x7d,0x00] + + vld4.16 {d0, d1, d2, d3}, [r4], r6 + vld4.16 {d0, d1, d2, d3}, [r4:16], r6 + vld4.16 {d0, d1, d2, d3}, [r4:32], r6 + vld4.16 {d0, d1, d2, d3}, [r4:64], r6 + vld4.16 {d0, d1, d2, d3}, [r4:128], r6 + vld4.16 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x00] +@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x00] +@ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0x76,0x00] + + vld4.16 {d0, d2, d4, d6}, [r4] + vld4.16 {d0, d2, d4, d6}, [r4:16] + vld4.16 {d0, d2, d4, d6}, [r4:32] + vld4.16 {d0, d2, d4, d6}, [r4:64] + vld4.16 {d0, d2, d4, d6}, [r4:128] + vld4.16 {d0, d2, d4, d6}, [r4:256] + +@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4] @ encoding: [0x24,0xf9,0x4f,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x01] +@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x01] +@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:256] @ encoding: [0x24,0xf9,0x7f,0x01] + + vld4.16 {d0, d2, d4, d6}, [r4]! + vld4.16 {d0, d2, d4, d6}, [r4:16]! + vld4.16 {d0, d2, d4, d6}, [r4:32]! + vld4.16 {d0, d2, d4, d6}, [r4:64]! + vld4.16 {d0, d2, d4, d6}, [r4:128]! + vld4.16 {d0, d2, d4, d6}, [r4:256]! + +@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x01] +@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x01] +@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:256]! @ encoding: [0x24,0xf9,0x7d,0x01] + + vld4.16 {d0, d2, d4, d6}, [r4], r6 + vld4.16 {d0, d2, d4, d6}, [r4:16], r6 + vld4.16 {d0, d2, d4, d6}, [r4:32], r6 + vld4.16 {d0, d2, d4, d6}, [r4:64], r6 + vld4.16 {d0, d2, d4, d6}, [r4:128], r6 + vld4.16 {d0, d2, d4, d6}, [r4:256], r6 + +@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x01] +@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x01] +@ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:256], r6 @ encoding: [0x24,0xf9,0x76,0x01] + + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4] + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] + +@ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] @ encoding: [0xa4,0xf9,0x5f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]! + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! + +@ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0x5d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 + vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 + +@ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x56,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4] + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16] + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32] + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] + +@ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] @ encoding: [0xa4,0xf9,0x7f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]! + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]! + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]! + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! + +@ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0x7d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6 + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6 + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 + vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 + +@ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x76,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld4.16 {d0[], d1[], d2[], d3[]}, [r4] + vld4.16 {d0[], d1[], d2[], d3[]}, [r4:16] + vld4.16 {d0[], d1[], d2[], d3[]}, [r4:32] + vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64] + vld4.16 {d0[], d1[], d2[], d3[]}, [r4:128] + vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256] + +@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x0f] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64] @ encoding: [0xa4,0xf9,0x5f,0x0f] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld4.16 {d0[], d1[], d2[], d3[]}, [r4]! + vld4.16 {d0[], d1[], d2[], d3[]}, [r4:16]! + vld4.16 {d0[], d1[], d2[], d3[]}, [r4:32]! + vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]! + vld4.16 {d0[], d1[], d2[], d3[]}, [r4:128]! + vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256]! + +@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x0f] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]! @ encoding: [0xa4,0xf9,0x5d,0x0f] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld4.16 {d0[], d1[], d2[], d3[]}, [r4], r6 + vld4.16 {d0[], d1[], d2[], d3[]}, [r4:16], r6 + vld4.16 {d0[], d1[], d2[], d3[]}, [r4:32], r6 + vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64], r6 + vld4.16 {d0[], d1[], d2[], d3[]}, [r4:128], r6 + vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256], r6 + +@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x0f] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x56,0x0f] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld4.16 {d0[], d2[], d4[], d6[]}, [r4] + vld4.16 {d0[], d2[], d4[], d6[]}, [r4:16] + vld4.16 {d0[], d2[], d4[], d6[]}, [r4:32] + vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64] + vld4.16 {d0[], d2[], d4[], d6[]}, [r4:128] + vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256] + +@ CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x0f] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64] @ encoding: [0xa4,0xf9,0x7f,0x0f] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld4.16 {d0[], d2[], d4[], d6[]}, [r4]! + vld4.16 {d0[], d2[], d4[], d6[]}, [r4:16]! + vld4.16 {d0[], d2[], d4[], d6[]}, [r4:32]! + vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]! + vld4.16 {d0[], d2[], d4[], d6[]}, [r4:128]! + vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256]! + +@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x0f] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]! @ encoding: [0xa4,0xf9,0x7d,0x0f] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld4.16 {d0[], d2[], d4[], d6[]}, [r4], r6 + vld4.16 {d0[], d2[], d4[], d6[]}, [r4:16], r6 + vld4.16 {d0[], d2[], d4[], d6[]}, [r4:32], r6 + vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r6 + vld4.16 {d0[], d2[], d4[], d6[]}, [r4:128], r6 + vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256], r6 + +@ CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x0f] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x76,0x0f] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld4.32 {d0, d1, d2, d3}, [r4] + vld4.32 {d0, d1, d2, d3}, [r4:16] + vld4.32 {d0, d1, d2, d3}, [r4:32] + vld4.32 {d0, d1, d2, d3}, [r4:64] + vld4.32 {d0, d1, d2, d3}, [r4:128] + vld4.32 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x8f,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x00] +@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x00] +@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x24,0xf9,0xbf,0x00] + + vld4.32 {d0, d1, d2, d3}, [r4]! + vld4.32 {d0, d1, d2, d3}, [r4:16]! + vld4.32 {d0, d1, d2, d3}, [r4:32]! + vld4.32 {d0, d1, d2, d3}, [r4:64]! + vld4.32 {d0, d1, d2, d3}, [r4:128]! + vld4.32 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x00] +@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x00] +@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x24,0xf9,0xbd,0x00] + + vld4.32 {d0, d1, d2, d3}, [r4], r6 + vld4.32 {d0, d1, d2, d3}, [r4:16], r6 + vld4.32 {d0, d1, d2, d3}, [r4:32], r6 + vld4.32 {d0, d1, d2, d3}, [r4:64], r6 + vld4.32 {d0, d1, d2, d3}, [r4:128], r6 + vld4.32 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x00] +@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x00] +@ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x24,0xf9,0xb6,0x00] + + vld4.32 {d0, d2, d4, d6}, [r4] + vld4.32 {d0, d2, d4, d6}, [r4:16] + vld4.32 {d0, d2, d4, d6}, [r4:32] + vld4.32 {d0, d2, d4, d6}, [r4:64] + vld4.32 {d0, d2, d4, d6}, [r4:128] + vld4.32 {d0, d2, d4, d6}, [r4:256] + +@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4] @ encoding: [0x24,0xf9,0x8f,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x01] +@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x01] +@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:256] @ encoding: [0x24,0xf9,0xbf,0x01] + + vld4.32 {d0, d2, d4, d6}, [r4]! + vld4.32 {d0, d2, d4, d6}, [r4:16]! + vld4.32 {d0, d2, d4, d6}, [r4:32]! + vld4.32 {d0, d2, d4, d6}, [r4:64]! + vld4.32 {d0, d2, d4, d6}, [r4:128]! + vld4.32 {d0, d2, d4, d6}, [r4:256]! + +@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x01] +@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x01] +@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:256]! @ encoding: [0x24,0xf9,0xbd,0x01] + + vld4.32 {d0, d2, d4, d6}, [r4], r6 + vld4.32 {d0, d2, d4, d6}, [r4:16], r6 + vld4.32 {d0, d2, d4, d6}, [r4:32], r6 + vld4.32 {d0, d2, d4, d6}, [r4:64], r6 + vld4.32 {d0, d2, d4, d6}, [r4:128], r6 + vld4.32 {d0, d2, d4, d6}, [r4:256], r6 + +@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x01] +@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x01] +@ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:256], r6 @ encoding: [0x24,0xf9,0xb6,0x01] + + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4] + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] + +@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] @ encoding: [0xa4,0xf9,0x9f,0x0b] +@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] @ encoding: [0xa4,0xf9,0xaf,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]! + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! + +@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0x9d,0x0b] +@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! @ encoding: [0xa4,0xf9,0xad,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 + vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 + +@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x96,0x0b] +@ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 @ encoding: [0xa4,0xf9,0xa6,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4] + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16] + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32] + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] + +@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4] @ encoding: [0xa4,0xf9,0xcf,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] @ encoding: [0xa4,0xf9,0xdf,0x0b] +@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] @ encoding: [0xa4,0xf9,0xef,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]! + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]! + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]! + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! + +@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]! @ encoding: [0xa4,0xf9,0xcd,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0xdd,0x0b] +@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! @ encoding: [0xa4,0xf9,0xed,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6 + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6 + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 + vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 + +@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0xc6,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0xd6,0x0b] +@ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 @ encoding: [0xa4,0xf9,0xe6,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld4.32 {d0[], d1[], d2[], d3[]}, [r4] + vld4.32 {d0[], d1[], d2[], d3[]}, [r4:16] + vld4.32 {d0[], d1[], d2[], d3[]}, [r4:32] + vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64] + vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128] + vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256] + +@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0f] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64] @ encoding: [0xa4,0xf9,0x9f,0x0f] +@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128] @ encoding: [0xa4,0xf9,0xdf,0x0f] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld4.32 {d0[], d1[], d2[], d3[]}, [r4]! + vld4.32 {d0[], d1[], d2[], d3[]}, [r4:16]! + vld4.32 {d0[], d1[], d2[], d3[]}, [r4:32]! + vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]! + vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]! + vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256]! + +@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0f] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]! @ encoding: [0xa4,0xf9,0x9d,0x0f] +@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]! @ encoding: [0xa4,0xf9,0xdd,0x0f] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld4.32 {d0[], d1[], d2[], d3[]}, [r4], r6 + vld4.32 {d0[], d1[], d2[], d3[]}, [r4:16], r6 + vld4.32 {d0[], d1[], d2[], d3[]}, [r4:32], r6 + vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64], r6 + vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128], r6 + vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256], r6 + +@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0f] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x96,0x0f] +@ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128], r6 @ encoding: [0xa4,0xf9,0xd6,0x0f] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vld4.32 {d0[], d2[], d4[], d6[]}, [r4] + vld4.32 {d0[], d2[], d4[], d6[]}, [r4:16] + vld4.32 {d0[], d2[], d4[], d6[]}, [r4:32] + vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64] + vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128] + vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256] + +@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4] @ encoding: [0xa4,0xf9,0xaf,0x0f] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64] @ encoding: [0xa4,0xf9,0xbf,0x0f] +@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128] @ encoding: [0xa4,0xf9,0xff,0x0f] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256] +@ CHECK-ERRORS: ^ + + vld4.32 {d0[], d2[], d4[], d6[]}, [r4]! + vld4.32 {d0[], d2[], d4[], d6[]}, [r4:16]! + vld4.32 {d0[], d2[], d4[], d6[]}, [r4:32]! + vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]! + vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]! + vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256]! + +@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4]! @ encoding: [0xa4,0xf9,0xad,0x0f] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]! @ encoding: [0xa4,0xf9,0xbd,0x0f] +@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]! @ encoding: [0xa4,0xf9,0xfd,0x0f] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vld4.32 {d0[], d2[], d4[], d6[]}, [r4], r6 + vld4.32 {d0[], d2[], d4[], d6[]}, [r4:16], r6 + vld4.32 {d0[], d2[], d4[], d6[]}, [r4:32], r6 + vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64], r6 + vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r6 + vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256], r6 + +@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4], r6 @ encoding: [0xa4,0xf9,0xa6,0x0f] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0xb6,0x0f] +@ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r6 @ encoding: [0xa4,0xf9,0xf6,0x0f] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.8 {d0}, [r4] + vst1.8 {d0}, [r4:16] + vst1.8 {d0}, [r4:32] + vst1.8 {d0}, [r4:64] + vst1.8 {d0}, [r4:128] + vst1.8 {d0}, [r4:256] + +@ CHECK: vst1.8 {d0}, [r4] @ encoding: [0x04,0xf9,0x0f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.8 {d0}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0}, [r4:256] +@ CHECK-ERRORS: ^ + + vst1.8 {d0}, [r4]! + vst1.8 {d0}, [r4:16]! + vst1.8 {d0}, [r4:32]! + vst1.8 {d0}, [r4:64]! + vst1.8 {d0}, [r4:128]! + vst1.8 {d0}, [r4:256]! + +@ CHECK: vst1.8 {d0}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.8 {d0}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst1.8 {d0}, [r4], r6 + vst1.8 {d0}, [r4:16], r6 + vst1.8 {d0}, [r4:32], r6 + vst1.8 {d0}, [r4:64], r6 + vst1.8 {d0}, [r4:128], r6 + vst1.8 {d0}, [r4:256], r6 + +@ CHECK: vst1.8 {d0}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.8 {d0}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.8 {d0, d1}, [r4] + vst1.8 {d0, d1}, [r4:16] + vst1.8 {d0, d1}, [r4:32] + vst1.8 {d0, d1}, [r4:64] + vst1.8 {d0, d1}, [r4:128] + vst1.8 {d0, d1}, [r4:256] + +@ CHECK: vst1.8 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0x0f,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.8 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x0a] +@ CHECK: vst1.8 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:256] +@ CHECK-ERRORS: ^ + + vst1.8 {d0, d1}, [r4]! + vst1.8 {d0, d1}, [r4:16]! + vst1.8 {d0, d1}, [r4:32]! + vst1.8 {d0, d1}, [r4:64]! + vst1.8 {d0, d1}, [r4:128]! + vst1.8 {d0, d1}, [r4:256]! + +@ CHECK: vst1.8 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.8 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x0a] +@ CHECK: vst1.8 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst1.8 {d0, d1}, [r4], r6 + vst1.8 {d0, d1}, [r4:16], r6 + vst1.8 {d0, d1}, [r4:32], r6 + vst1.8 {d0, d1}, [r4:64], r6 + vst1.8 {d0, d1}, [r4:128], r6 + vst1.8 {d0, d1}, [r4:256], r6 + +@ CHECK: vst1.8 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.8 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x0a] +@ CHECK: vst1.8 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.8 {d0, d1, d2}, [r4] + vst1.8 {d0, d1, d2}, [r4:16] + vst1.8 {d0, d1, d2}, [r4:32] + vst1.8 {d0, d1, d2}, [r4:64] + vst1.8 {d0, d1, d2}, [r4:128] + vst1.8 {d0, d1, d2}, [r4:256] + +@ CHECK: vst1.8 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x0f,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.8 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vst1.8 {d0, d1, d2}, [r4]! + vst1.8 {d0, d1, d2}, [r4:16]! + vst1.8 {d0, d1, d2}, [r4:32]! + vst1.8 {d0, d1, d2}, [r4:64]! + vst1.8 {d0, d1, d2}, [r4:128]! + vst1.8 {d0, d1, d2}, [r4:256]! + +@ CHECK: vst1.8 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.8 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst1.8 {d0, d1, d2}, [r4], r6 + vst1.8 {d0, d1, d2}, [r4:16], r6 + vst1.8 {d0, d1, d2}, [r4:32], r6 + vst1.8 {d0, d1, d2}, [r4:64], r6 + vst1.8 {d0, d1, d2}, [r4:128], r6 + vst1.8 {d0, d1, d2}, [r4:256], r6 + +@ CHECK: vst1.8 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.8 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.8 {d0, d1, d2, d3}, [r4] + vst1.8 {d0, d1, d2, d3}, [r4:16] + vst1.8 {d0, d1, d2, d3}, [r4:32] + vst1.8 {d0, d1, d2, d3}, [r4:64] + vst1.8 {d0, d1, d2, d3}, [r4:128] + vst1.8 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x0f,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x02] +@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x02] +@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0x3f,0x02] + + vst1.8 {d0, d1, d2, d3}, [r4]! + vst1.8 {d0, d1, d2, d3}, [r4:16]! + vst1.8 {d0, d1, d2, d3}, [r4:32]! + vst1.8 {d0, d1, d2, d3}, [r4:64]! + vst1.8 {d0, d1, d2, d3}, [r4:128]! + vst1.8 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x02] +@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x02] +@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0x3d,0x02] + + vst1.8 {d0, d1, d2, d3}, [r4], r6 + vst1.8 {d0, d1, d2, d3}, [r4:16], r6 + vst1.8 {d0, d1, d2, d3}, [r4:32], r6 + vst1.8 {d0, d1, d2, d3}, [r4:64], r6 + vst1.8 {d0, d1, d2, d3}, [r4:128], r6 + vst1.8 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x02] +@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x02] +@ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0x36,0x02] + + vst1.8 {d0[2]}, [r4] + vst1.8 {d0[2]}, [r4:16] + vst1.8 {d0[2]}, [r4:32] + vst1.8 {d0[2]}, [r4:64] + vst1.8 {d0[2]}, [r4:128] + vst1.8 {d0[2]}, [r4:256] + +@ CHECK: vst1.8 {d0[2]}, [r4] @ encoding: [0x84,0xf9,0x4f,0x00] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst1.8 {d0[2]}, [r4]! + vst1.8 {d0[2]}, [r4:16]! + vst1.8 {d0[2]}, [r4:32]! + vst1.8 {d0[2]}, [r4:64]! + vst1.8 {d0[2]}, [r4:128]! + vst1.8 {d0[2]}, [r4:256]! + +@ CHECK: vst1.8 {d0[2]}, [r4]! @ encoding: [0x84,0xf9,0x4d,0x00] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst1.8 {d0[2]}, [r4], r6 + vst1.8 {d0[2]}, [r4:16], r6 + vst1.8 {d0[2]}, [r4:32], r6 + vst1.8 {d0[2]}, [r4:64], r6 + vst1.8 {d0[2]}, [r4:128], r6 + vst1.8 {d0[2]}, [r4:256], r6 + +@ CHECK: vst1.8 {d0[2]}, [r4], r6 @ encoding: [0x84,0xf9,0x46,0x00] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.16 {d0}, [r4] + vst1.16 {d0}, [r4:16] + vst1.16 {d0}, [r4:32] + vst1.16 {d0}, [r4:64] + vst1.16 {d0}, [r4:128] + vst1.16 {d0}, [r4:256] + +@ CHECK: vst1.16 {d0}, [r4] @ encoding: [0x04,0xf9,0x4f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.16 {d0}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0}, [r4:256] +@ CHECK-ERRORS: ^ + + vst1.16 {d0}, [r4]! + vst1.16 {d0}, [r4:16]! + vst1.16 {d0}, [r4:32]! + vst1.16 {d0}, [r4:64]! + vst1.16 {d0}, [r4:128]! + vst1.16 {d0}, [r4:256]! + +@ CHECK: vst1.16 {d0}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.16 {d0}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst1.16 {d0}, [r4], r6 + vst1.16 {d0}, [r4:16], r6 + vst1.16 {d0}, [r4:32], r6 + vst1.16 {d0}, [r4:64], r6 + vst1.16 {d0}, [r4:128], r6 + vst1.16 {d0}, [r4:256], r6 + +@ CHECK: vst1.16 {d0}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.16 {d0}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.16 {d0, d1}, [r4] + vst1.16 {d0, d1}, [r4:16] + vst1.16 {d0, d1}, [r4:32] + vst1.16 {d0, d1}, [r4:64] + vst1.16 {d0, d1}, [r4:128] + vst1.16 {d0, d1}, [r4:256] + +@ CHECK: vst1.16 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0x4f,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.16 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x0a] +@ CHECK: vst1.16 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0x6f,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:256] +@ CHECK-ERRORS: ^ + + vst1.16 {d0, d1}, [r4]! + vst1.16 {d0, d1}, [r4:16]! + vst1.16 {d0, d1}, [r4:32]! + vst1.16 {d0, d1}, [r4:64]! + vst1.16 {d0, d1}, [r4:128]! + vst1.16 {d0, d1}, [r4:256]! + +@ CHECK: vst1.16 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.16 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x0a] +@ CHECK: vst1.16 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0x6d,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst1.16 {d0, d1}, [r4], r6 + vst1.16 {d0, d1}, [r4:16], r6 + vst1.16 {d0, d1}, [r4:32], r6 + vst1.16 {d0, d1}, [r4:64], r6 + vst1.16 {d0, d1}, [r4:128], r6 + vst1.16 {d0, d1}, [r4:256], r6 + +@ CHECK: vst1.16 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.16 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x0a] +@ CHECK: vst1.16 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0x66,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.16 {d0, d1, d2}, [r4] + vst1.16 {d0, d1, d2}, [r4:16] + vst1.16 {d0, d1, d2}, [r4:32] + vst1.16 {d0, d1, d2}, [r4:64] + vst1.16 {d0, d1, d2}, [r4:128] + vst1.16 {d0, d1, d2}, [r4:256] + +@ CHECK: vst1.16 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x4f,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.16 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vst1.16 {d0, d1, d2}, [r4]! + vst1.16 {d0, d1, d2}, [r4:16]! + vst1.16 {d0, d1, d2}, [r4:32]! + vst1.16 {d0, d1, d2}, [r4:64]! + vst1.16 {d0, d1, d2}, [r4:128]! + vst1.16 {d0, d1, d2}, [r4:256]! + +@ CHECK: vst1.16 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.16 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst1.16 {d0, d1, d2}, [r4], r6 + vst1.16 {d0, d1, d2}, [r4:16], r6 + vst1.16 {d0, d1, d2}, [r4:32], r6 + vst1.16 {d0, d1, d2}, [r4:64], r6 + vst1.16 {d0, d1, d2}, [r4:128], r6 + vst1.16 {d0, d1, d2}, [r4:256], r6 + +@ CHECK: vst1.16 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.16 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.16 {d0, d1, d2, d3}, [r4] + vst1.16 {d0, d1, d2, d3}, [r4:16] + vst1.16 {d0, d1, d2, d3}, [r4:32] + vst1.16 {d0, d1, d2, d3}, [r4:64] + vst1.16 {d0, d1, d2, d3}, [r4:128] + vst1.16 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x4f,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x02] +@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0x6f,0x02] +@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0x7f,0x02] + + vst1.16 {d0, d1, d2, d3}, [r4]! + vst1.16 {d0, d1, d2, d3}, [r4:16]! + vst1.16 {d0, d1, d2, d3}, [r4:32]! + vst1.16 {d0, d1, d2, d3}, [r4:64]! + vst1.16 {d0, d1, d2, d3}, [r4:128]! + vst1.16 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x02] +@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0x6d,0x02] +@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0x7d,0x02] + + vst1.16 {d0, d1, d2, d3}, [r4], r6 + vst1.16 {d0, d1, d2, d3}, [r4:16], r6 + vst1.16 {d0, d1, d2, d3}, [r4:32], r6 + vst1.16 {d0, d1, d2, d3}, [r4:64], r6 + vst1.16 {d0, d1, d2, d3}, [r4:128], r6 + vst1.16 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x02] +@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0x66,0x02] +@ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0x76,0x02] + + vst1.16 {d0[2]}, [r4] + vst1.16 {d0[2]}, [r4:16] + vst1.16 {d0[2]}, [r4:32] + vst1.16 {d0[2]}, [r4:64] + vst1.16 {d0[2]}, [r4:128] + vst1.16 {d0[2]}, [r4:256] + +@ CHECK: vst1.16 {d0[2]}, [r4] @ encoding: [0x84,0xf9,0x8f,0x04] +@ CHECK: vst1.16 {d0[2]}, [r4:16] @ encoding: [0x84,0xf9,0x9f,0x04] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst1.16 {d0[2]}, [r4]! + vst1.16 {d0[2]}, [r4:16]! + vst1.16 {d0[2]}, [r4:32]! + vst1.16 {d0[2]}, [r4:64]! + vst1.16 {d0[2]}, [r4:128]! + vst1.16 {d0[2]}, [r4:256]! + +@ CHECK: vst1.16 {d0[2]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x04] +@ CHECK: vst1.16 {d0[2]}, [r4:16]! @ encoding: [0x84,0xf9,0x9d,0x04] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst1.16 {d0[2]}, [r4], r6 + vst1.16 {d0[2]}, [r4:16], r6 + vst1.16 {d0[2]}, [r4:32], r6 + vst1.16 {d0[2]}, [r4:64], r6 + vst1.16 {d0[2]}, [r4:128], r6 + vst1.16 {d0[2]}, [r4:256], r6 + +@ CHECK: vst1.16 {d0[2]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x04] +@ CHECK: vst1.16 {d0[2]}, [r4:16], r6 @ encoding: [0x84,0xf9,0x96,0x04] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.32 {d0}, [r4] + vst1.32 {d0}, [r4:16] + vst1.32 {d0}, [r4:32] + vst1.32 {d0}, [r4:64] + vst1.32 {d0}, [r4:128] + vst1.32 {d0}, [r4:256] + +@ CHECK: vst1.32 {d0}, [r4] @ encoding: [0x04,0xf9,0x8f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.32 {d0}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0}, [r4:256] +@ CHECK-ERRORS: ^ + + vst1.32 {d0}, [r4]! + vst1.32 {d0}, [r4:16]! + vst1.32 {d0}, [r4:32]! + vst1.32 {d0}, [r4:64]! + vst1.32 {d0}, [r4:128]! + vst1.32 {d0}, [r4:256]! + +@ CHECK: vst1.32 {d0}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.32 {d0}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst1.32 {d0}, [r4], r6 + vst1.32 {d0}, [r4:16], r6 + vst1.32 {d0}, [r4:32], r6 + vst1.32 {d0}, [r4:64], r6 + vst1.32 {d0}, [r4:128], r6 + vst1.32 {d0}, [r4:256], r6 + +@ CHECK: vst1.32 {d0}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.32 {d0}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.32 {d0, d1}, [r4] + vst1.32 {d0, d1}, [r4:16] + vst1.32 {d0, d1}, [r4:32] + vst1.32 {d0, d1}, [r4:64] + vst1.32 {d0, d1}, [r4:128] + vst1.32 {d0, d1}, [r4:256] + +@ CHECK: vst1.32 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0x8f,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.32 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x0a] +@ CHECK: vst1.32 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:256] +@ CHECK-ERRORS: ^ + + vst1.32 {d0, d1}, [r4]! + vst1.32 {d0, d1}, [r4:16]! + vst1.32 {d0, d1}, [r4:32]! + vst1.32 {d0, d1}, [r4:64]! + vst1.32 {d0, d1}, [r4:128]! + vst1.32 {d0, d1}, [r4:256]! + +@ CHECK: vst1.32 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.32 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x0a] +@ CHECK: vst1.32 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst1.32 {d0, d1}, [r4], r6 + vst1.32 {d0, d1}, [r4:16], r6 + vst1.32 {d0, d1}, [r4:32], r6 + vst1.32 {d0, d1}, [r4:64], r6 + vst1.32 {d0, d1}, [r4:128], r6 + vst1.32 {d0, d1}, [r4:256], r6 + +@ CHECK: vst1.32 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.32 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x0a] +@ CHECK: vst1.32 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.32 {d0, d1, d2}, [r4] + vst1.32 {d0, d1, d2}, [r4:16] + vst1.32 {d0, d1, d2}, [r4:32] + vst1.32 {d0, d1, d2}, [r4:64] + vst1.32 {d0, d1, d2}, [r4:128] + vst1.32 {d0, d1, d2}, [r4:256] + +@ CHECK: vst1.32 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x8f,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.32 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vst1.32 {d0, d1, d2}, [r4]! + vst1.32 {d0, d1, d2}, [r4:16]! + vst1.32 {d0, d1, d2}, [r4:32]! + vst1.32 {d0, d1, d2}, [r4:64]! + vst1.32 {d0, d1, d2}, [r4:128]! + vst1.32 {d0, d1, d2}, [r4:256]! + +@ CHECK: vst1.32 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.32 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst1.32 {d0, d1, d2}, [r4], r6 + vst1.32 {d0, d1, d2}, [r4:16], r6 + vst1.32 {d0, d1, d2}, [r4:32], r6 + vst1.32 {d0, d1, d2}, [r4:64], r6 + vst1.32 {d0, d1, d2}, [r4:128], r6 + vst1.32 {d0, d1, d2}, [r4:256], r6 + +@ CHECK: vst1.32 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.32 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.32 {d0, d1, d2, d3}, [r4] + vst1.32 {d0, d1, d2, d3}, [r4:16] + vst1.32 {d0, d1, d2, d3}, [r4:32] + vst1.32 {d0, d1, d2, d3}, [r4:64] + vst1.32 {d0, d1, d2, d3}, [r4:128] + vst1.32 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x8f,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x02] +@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x02] +@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0xbf,0x02] + + vst1.32 {d0, d1, d2, d3}, [r4]! + vst1.32 {d0, d1, d2, d3}, [r4:16]! + vst1.32 {d0, d1, d2, d3}, [r4:32]! + vst1.32 {d0, d1, d2, d3}, [r4:64]! + vst1.32 {d0, d1, d2, d3}, [r4:128]! + vst1.32 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x02] +@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x02] +@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0xbd,0x02] + + vst1.32 {d0, d1, d2, d3}, [r4], r6 + vst1.32 {d0, d1, d2, d3}, [r4:16], r6 + vst1.32 {d0, d1, d2, d3}, [r4:32], r6 + vst1.32 {d0, d1, d2, d3}, [r4:64], r6 + vst1.32 {d0, d1, d2, d3}, [r4:128], r6 + vst1.32 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x02] +@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x02] +@ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0xb6,0x02] + + vst1.32 {d0[1]}, [r4] + vst1.32 {d0[1]}, [r4:16] + vst1.32 {d0[1]}, [r4:32] + vst1.32 {d0[1]}, [r4:64] + vst1.32 {d0[1]}, [r4:128] + vst1.32 {d0[1]}, [r4:256] + +@ CHECK: vst1.32 {d0[1]}, [r4] @ encoding: [0x84,0xf9,0x8f,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.32 {d0[1]}, [r4:32] @ encoding: [0x84,0xf9,0xbf,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst1.32 {d0[1]}, [r4]! + vst1.32 {d0[1]}, [r4:16]! + vst1.32 {d0[1]}, [r4:32]! + vst1.32 {d0[1]}, [r4:64]! + vst1.32 {d0[1]}, [r4:128]! + vst1.32 {d0[1]}, [r4:256]! + +@ CHECK: vst1.32 {d0[1]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.32 {d0[1]}, [r4:32]! @ encoding: [0x84,0xf9,0xbd,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst1.32 {d0[1]}, [r4], r6 + vst1.32 {d0[1]}, [r4:16], r6 + vst1.32 {d0[1]}, [r4:32], r6 + vst1.32 {d0[1]}, [r4:64], r6 + vst1.32 {d0[1]}, [r4:128], r6 + vst1.32 {d0[1]}, [r4:256], r6 + +@ CHECK: vst1.32 {d0[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.32 {d0[1]}, [r4:32], r6 @ encoding: [0x84,0xf9,0xb6,0x08] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.64 {d0}, [r4] + vst1.64 {d0}, [r4:16] + vst1.64 {d0}, [r4:32] + vst1.64 {d0}, [r4:64] + vst1.64 {d0}, [r4:128] + vst1.64 {d0}, [r4:256] + +@ CHECK: vst1.64 {d0}, [r4] @ encoding: [0x04,0xf9,0xcf,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.64 {d0}, [r4:64] @ encoding: [0x04,0xf9,0xdf,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0}, [r4:256] +@ CHECK-ERRORS: ^ + + vst1.64 {d0}, [r4]! + vst1.64 {d0}, [r4:16]! + vst1.64 {d0}, [r4:32]! + vst1.64 {d0}, [r4:64]! + vst1.64 {d0}, [r4:128]! + vst1.64 {d0}, [r4:256]! + +@ CHECK: vst1.64 {d0}, [r4]! @ encoding: [0x04,0xf9,0xcd,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.64 {d0}, [r4:64]! @ encoding: [0x04,0xf9,0xdd,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst1.64 {d0}, [r4], r6 + vst1.64 {d0}, [r4:16], r6 + vst1.64 {d0}, [r4:32], r6 + vst1.64 {d0}, [r4:64], r6 + vst1.64 {d0}, [r4:128], r6 + vst1.64 {d0}, [r4:256], r6 + +@ CHECK: vst1.64 {d0}, [r4], r6 @ encoding: [0x04,0xf9,0xc6,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.64 {d0}, [r4:64], r6 @ encoding: [0x04,0xf9,0xd6,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.64 {d0, d1}, [r4] + vst1.64 {d0, d1}, [r4:16] + vst1.64 {d0, d1}, [r4:32] + vst1.64 {d0, d1}, [r4:64] + vst1.64 {d0, d1}, [r4:128] + vst1.64 {d0, d1}, [r4:256] + +@ CHECK: vst1.64 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0xcf,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.64 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0xdf,0x0a] +@ CHECK: vst1.64 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0xef,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:256] +@ CHECK-ERRORS: ^ + + vst1.64 {d0, d1}, [r4]! + vst1.64 {d0, d1}, [r4:16]! + vst1.64 {d0, d1}, [r4:32]! + vst1.64 {d0, d1}, [r4:64]! + vst1.64 {d0, d1}, [r4:128]! + vst1.64 {d0, d1}, [r4:256]! + +@ CHECK: vst1.64 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0xcd,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.64 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0xdd,0x0a] +@ CHECK: vst1.64 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0xed,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst1.64 {d0, d1}, [r4], r6 + vst1.64 {d0, d1}, [r4:16], r6 + vst1.64 {d0, d1}, [r4:32], r6 + vst1.64 {d0, d1}, [r4:64], r6 + vst1.64 {d0, d1}, [r4:128], r6 + vst1.64 {d0, d1}, [r4:256], r6 + +@ CHECK: vst1.64 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0xc6,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.64 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0xd6,0x0a] +@ CHECK: vst1.64 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0xe6,0x0a] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.64 {d0, d1, d2}, [r4] + vst1.64 {d0, d1, d2}, [r4:16] + vst1.64 {d0, d1, d2}, [r4:32] + vst1.64 {d0, d1, d2}, [r4:64] + vst1.64 {d0, d1, d2}, [r4:128] + vst1.64 {d0, d1, d2}, [r4:256] + +@ CHECK: vst1.64 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0xcf,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.64 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0xdf,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vst1.64 {d0, d1, d2}, [r4]! + vst1.64 {d0, d1, d2}, [r4:16]! + vst1.64 {d0, d1, d2}, [r4:32]! + vst1.64 {d0, d1, d2}, [r4:64]! + vst1.64 {d0, d1, d2}, [r4:128]! + vst1.64 {d0, d1, d2}, [r4:256]! + +@ CHECK: vst1.64 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0xcd,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.64 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0xdd,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst1.64 {d0, d1, d2}, [r4], r6 + vst1.64 {d0, d1, d2}, [r4:16], r6 + vst1.64 {d0, d1, d2}, [r4:32], r6 + vst1.64 {d0, d1, d2}, [r4:64], r6 + vst1.64 {d0, d1, d2}, [r4:128], r6 + vst1.64 {d0, d1, d2}, [r4:256], r6 + +@ CHECK: vst1.64 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0xc6,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.64 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0xd6,0x06] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst1.64 {d0, d1, d2, d3}, [r4] + vst1.64 {d0, d1, d2, d3}, [r4:16] + vst1.64 {d0, d1, d2, d3}, [r4:32] + vst1.64 {d0, d1, d2, d3}, [r4:64] + vst1.64 {d0, d1, d2, d3}, [r4:128] + vst1.64 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0xcf,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0xdf,0x02] +@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0xef,0x02] +@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0xff,0x02] + + vst1.64 {d0, d1, d2, d3}, [r4]! + vst1.64 {d0, d1, d2, d3}, [r4:16]! + vst1.64 {d0, d1, d2, d3}, [r4:32]! + vst1.64 {d0, d1, d2, d3}, [r4:64]! + vst1.64 {d0, d1, d2, d3}, [r4:128]! + vst1.64 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0xcd,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0xdd,0x02] +@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0xed,0x02] +@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0xfd,0x02] + + vst1.64 {d0, d1, d2, d3}, [r4], r6 + vst1.64 {d0, d1, d2, d3}, [r4:16], r6 + vst1.64 {d0, d1, d2, d3}, [r4:32], r6 + vst1.64 {d0, d1, d2, d3}, [r4:64], r6 + vst1.64 {d0, d1, d2, d3}, [r4:128], r6 + vst1.64 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0xc6,0x02] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0xd6,0x02] +@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0xe6,0x02] +@ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0xf6,0x02] + + vst2.8 {d0, d1}, [r4] + vst2.8 {d0, d1}, [r4:16] + vst2.8 {d0, d1}, [r4:32] + vst2.8 {d0, d1}, [r4:64] + vst2.8 {d0, d1}, [r4:128] + vst2.8 {d0, d1}, [r4:256] + +@ CHECK: vst2.8 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0x0f,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst2.8 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x08] +@ CHECK: vst2.8 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:256] +@ CHECK-ERRORS: ^ + + vst2.8 {d0, d1}, [r4]! + vst2.8 {d0, d1}, [r4:16]! + vst2.8 {d0, d1}, [r4:32]! + vst2.8 {d0, d1}, [r4:64]! + vst2.8 {d0, d1}, [r4:128]! + vst2.8 {d0, d1}, [r4:256]! + +@ CHECK: vst2.8 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst2.8 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x08] +@ CHECK: vst2.8 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst2.8 {d0, d1}, [r4], r6 + vst2.8 {d0, d1}, [r4:16], r6 + vst2.8 {d0, d1}, [r4:32], r6 + vst2.8 {d0, d1}, [r4:64], r6 + vst2.8 {d0, d1}, [r4:128], r6 + vst2.8 {d0, d1}, [r4:256], r6 + +@ CHECK: vst2.8 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst2.8 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x08] +@ CHECK: vst2.8 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst2.8 {d0, d2}, [r4] + vst2.8 {d0, d2}, [r4:16] + vst2.8 {d0, d2}, [r4:32] + vst2.8 {d0, d2}, [r4:64] + vst2.8 {d0, d2}, [r4:128] + vst2.8 {d0, d2}, [r4:256] + +@ CHECK: vst2.8 {d0, d2}, [r4] @ encoding: [0x04,0xf9,0x0f,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst2.8 {d0, d2}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x09] +@ CHECK: vst2.8 {d0, d2}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vst2.8 {d0, d2}, [r4]! + vst2.8 {d0, d2}, [r4:16]! + vst2.8 {d0, d2}, [r4:32]! + vst2.8 {d0, d2}, [r4:64]! + vst2.8 {d0, d2}, [r4:128]! + vst2.8 {d0, d2}, [r4:256]! + +@ CHECK: vst2.8 {d0, d2}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst2.8 {d0, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x09] +@ CHECK: vst2.8 {d0, d2}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst2.8 {d0, d2}, [r4], r6 + vst2.8 {d0, d2}, [r4:16], r6 + vst2.8 {d0, d2}, [r4:32], r6 + vst2.8 {d0, d2}, [r4:64], r6 + vst2.8 {d0, d2}, [r4:128], r6 + vst2.8 {d0, d2}, [r4:256], r6 + +@ CHECK: vst2.8 {d0, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst2.8 {d0, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x09] +@ CHECK: vst2.8 {d0, d2}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst2.8 {d0, d1, d2, d3}, [r4] + vst2.8 {d0, d1, d2, d3}, [r4:16] + vst2.8 {d0, d1, d2, d3}, [r4:32] + vst2.8 {d0, d1, d2, d3}, [r4:64] + vst2.8 {d0, d1, d2, d3}, [r4:128] + vst2.8 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x0f,0x03] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x03] +@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x03] +@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0x3f,0x03] + + vst2.8 {d0, d1, d2, d3}, [r4]! + vst2.8 {d0, d1, d2, d3}, [r4:16]! + vst2.8 {d0, d1, d2, d3}, [r4:32]! + vst2.8 {d0, d1, d2, d3}, [r4:64]! + vst2.8 {d0, d1, d2, d3}, [r4:128]! + vst2.8 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x03] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x03] +@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x03] +@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0x3d,0x03] + + vst2.8 {d0, d1, d2, d3}, [r4], r6 + vst2.8 {d0, d1, d2, d3}, [r4:16], r6 + vst2.8 {d0, d1, d2, d3}, [r4:32], r6 + vst2.8 {d0, d1, d2, d3}, [r4:64], r6 + vst2.8 {d0, d1, d2, d3}, [r4:128], r6 + vst2.8 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x03] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x03] +@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x03] +@ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0x36,0x03] + + vst2.8 {d0[2], d1[2]}, [r4] + vst2.8 {d0[2], d1[2]}, [r4:16] + vst2.8 {d0[2], d1[2]}, [r4:32] + vst2.8 {d0[2], d1[2]}, [r4:64] + vst2.8 {d0[2], d1[2]}, [r4:128] + vst2.8 {d0[2], d1[2]}, [r4:256] + +@ CHECK: vst2.8 {d0[2], d1[2]}, [r4] @ encoding: [0x84,0xf9,0x4f,0x01] +@ CHECK: vst2.8 {d0[2], d1[2]}, [r4:16] @ encoding: [0x84,0xf9,0x5f,0x01] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst2.8 {d0[2], d1[2]}, [r4]! + vst2.8 {d0[2], d1[2]}, [r4:16]! + vst2.8 {d0[2], d1[2]}, [r4:32]! + vst2.8 {d0[2], d1[2]}, [r4:64]! + vst2.8 {d0[2], d1[2]}, [r4:128]! + vst2.8 {d0[2], d1[2]}, [r4:256]! + +@ CHECK: vst2.8 {d0[2], d1[2]}, [r4]! @ encoding: [0x84,0xf9,0x4d,0x01] +@ CHECK: vst2.8 {d0[2], d1[2]}, [r4:16]! @ encoding: [0x84,0xf9,0x5d,0x01] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst2.8 {d0[2], d1[2]}, [r4], r6 + vst2.8 {d0[2], d1[2]}, [r4:16], r6 + vst2.8 {d0[2], d1[2]}, [r4:32], r6 + vst2.8 {d0[2], d1[2]}, [r4:64], r6 + vst2.8 {d0[2], d1[2]}, [r4:128], r6 + vst2.8 {d0[2], d1[2]}, [r4:256], r6 + +@ CHECK: vst2.8 {d0[2], d1[2]}, [r4], r6 @ encoding: [0x84,0xf9,0x46,0x01] +@ CHECK: vst2.8 {d0[2], d1[2]}, [r4:16], r6 @ encoding: [0x84,0xf9,0x56,0x01] +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 16 or omitted +@ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst2.32 {d0, d1}, [r4] + vst2.32 {d0, d1}, [r4:16] + vst2.32 {d0, d1}, [r4:32] + vst2.32 {d0, d1}, [r4:64] + vst2.32 {d0, d1}, [r4:128] + vst2.32 {d0, d1}, [r4:256] + +@ CHECK: vst2.32 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0x8f,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst2.32 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x08] +@ CHECK: vst2.32 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:256] +@ CHECK-ERRORS: ^ + + vst2.32 {d0, d1}, [r4]! + vst2.32 {d0, d1}, [r4:16]! + vst2.32 {d0, d1}, [r4:32]! + vst2.32 {d0, d1}, [r4:64]! + vst2.32 {d0, d1}, [r4:128]! + vst2.32 {d0, d1}, [r4:256]! + +@ CHECK: vst2.32 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst2.32 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x08] +@ CHECK: vst2.32 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst2.32 {d0, d1}, [r4], r6 + vst2.32 {d0, d1}, [r4:16], r6 + vst2.32 {d0, d1}, [r4:32], r6 + vst2.32 {d0, d1}, [r4:64], r6 + vst2.32 {d0, d1}, [r4:128], r6 + vst2.32 {d0, d1}, [r4:256], r6 + +@ CHECK: vst2.32 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst2.32 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x08] +@ CHECK: vst2.32 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x08] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst2.32 {d0, d2}, [r4] + vst2.32 {d0, d2}, [r4:16] + vst2.32 {d0, d2}, [r4:32] + vst2.32 {d0, d2}, [r4:64] + vst2.32 {d0, d2}, [r4:128] + vst2.32 {d0, d2}, [r4:256] + +@ CHECK: vst2.32 {d0, d2}, [r4] @ encoding: [0x04,0xf9,0x8f,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst2.32 {d0, d2}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x09] +@ CHECK: vst2.32 {d0, d2}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vst2.32 {d0, d2}, [r4]! + vst2.32 {d0, d2}, [r4:16]! + vst2.32 {d0, d2}, [r4:32]! + vst2.32 {d0, d2}, [r4:64]! + vst2.32 {d0, d2}, [r4:128]! + vst2.32 {d0, d2}, [r4:256]! + +@ CHECK: vst2.32 {d0, d2}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst2.32 {d0, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x09] +@ CHECK: vst2.32 {d0, d2}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst2.32 {d0, d2}, [r4], r6 + vst2.32 {d0, d2}, [r4:16], r6 + vst2.32 {d0, d2}, [r4:32], r6 + vst2.32 {d0, d2}, [r4:64], r6 + vst2.32 {d0, d2}, [r4:128], r6 + vst2.32 {d0, d2}, [r4:256], r6 + +@ CHECK: vst2.32 {d0, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst2.32 {d0, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x09] +@ CHECK: vst2.32 {d0, d2}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x09] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst2.32 {d0, d1, d2, d3}, [r4] + vst2.32 {d0, d1, d2, d3}, [r4:16] + vst2.32 {d0, d1, d2, d3}, [r4:32] + vst2.32 {d0, d1, d2, d3}, [r4:64] + vst2.32 {d0, d1, d2, d3}, [r4:128] + vst2.32 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x8f,0x03] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x03] +@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x03] +@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0xbf,0x03] + + vst2.32 {d0, d1, d2, d3}, [r4]! + vst2.32 {d0, d1, d2, d3}, [r4:16]! + vst2.32 {d0, d1, d2, d3}, [r4:32]! + vst2.32 {d0, d1, d2, d3}, [r4:64]! + vst2.32 {d0, d1, d2, d3}, [r4:128]! + vst2.32 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x03] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x03] +@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x03] +@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0xbd,0x03] + + vst2.32 {d0, d1, d2, d3}, [r4], r6 + vst2.32 {d0, d1, d2, d3}, [r4:16], r6 + vst2.32 {d0, d1, d2, d3}, [r4:32], r6 + vst2.32 {d0, d1, d2, d3}, [r4:64], r6 + vst2.32 {d0, d1, d2, d3}, [r4:128], r6 + vst2.32 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x03] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x03] +@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x03] +@ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0xb6,0x03] + + vst2.32 {d0[1], d1[1]}, [r4] + vst2.32 {d0[1], d1[1]}, [r4:16] + vst2.32 {d0[1], d1[1]}, [r4:32] + vst2.32 {d0[1], d1[1]}, [r4:64] + vst2.32 {d0[1], d1[1]}, [r4:128] + vst2.32 {d0[1], d1[1]}, [r4:256] + +@ CHECK: vst2.32 {d0[1], d1[1]}, [r4] @ encoding: [0x84,0xf9,0x8f,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst2.32 {d0[1], d1[1]}, [r4:64] @ encoding: [0x84,0xf9,0x9f,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst2.32 {d0[1], d1[1]}, [r4]! + vst2.32 {d0[1], d1[1]}, [r4:16]! + vst2.32 {d0[1], d1[1]}, [r4:32]! + vst2.32 {d0[1], d1[1]}, [r4:64]! + vst2.32 {d0[1], d1[1]}, [r4:128]! + vst2.32 {d0[1], d1[1]}, [r4:256]! + +@ CHECK: vst2.32 {d0[1], d1[1]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst2.32 {d0[1], d1[1]}, [r4:64]! @ encoding: [0x84,0xf9,0x9d,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst2.32 {d0[1], d1[1]}, [r4], r6 + vst2.32 {d0[1], d1[1]}, [r4:16], r6 + vst2.32 {d0[1], d1[1]}, [r4:32], r6 + vst2.32 {d0[1], d1[1]}, [r4:64], r6 + vst2.32 {d0[1], d1[1]}, [r4:128], r6 + vst2.32 {d0[1], d1[1]}, [r4:256], r6 + +@ CHECK: vst2.32 {d0[1], d1[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst2.32 {d0[1], d1[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0x96,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst2.32 {d0[1], d2[1]}, [r4] + vst2.32 {d0[1], d2[1]}, [r4:16] + vst2.32 {d0[1], d2[1]}, [r4:32] + vst2.32 {d0[1], d2[1]}, [r4:64] + vst2.32 {d0[1], d2[1]}, [r4:128] + vst2.32 {d0[1], d2[1]}, [r4:256] + +@ CHECK: vst2.32 {d0[1], d2[1]}, [r4] @ encoding: [0x84,0xf9,0xcf,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst2.32 {d0[1], d2[1]}, [r4:64] @ encoding: [0x84,0xf9,0xdf,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst2.32 {d0[1], d2[1]}, [r4]! + vst2.32 {d0[1], d2[1]}, [r4:16]! + vst2.32 {d0[1], d2[1]}, [r4:32]! + vst2.32 {d0[1], d2[1]}, [r4:64]! + vst2.32 {d0[1], d2[1]}, [r4:128]! + vst2.32 {d0[1], d2[1]}, [r4:256]! + +@ CHECK: vst2.32 {d0[1], d2[1]}, [r4]! @ encoding: [0x84,0xf9,0xcd,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst2.32 {d0[1], d2[1]}, [r4:64]! @ encoding: [0x84,0xf9,0xdd,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst2.32 {d0[1], d2[1]}, [r4], r6 + vst2.32 {d0[1], d2[1]}, [r4:16], r6 + vst2.32 {d0[1], d2[1]}, [r4:32], r6 + vst2.32 {d0[1], d2[1]}, [r4:64], r6 + vst2.32 {d0[1], d2[1]}, [r4:128], r6 + vst2.32 {d0[1], d2[1]}, [r4:256], r6 + +@ CHECK: vst2.32 {d0[1], d2[1]}, [r4], r6 @ encoding: [0x84,0xf9,0xc6,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst2.32 {d0[1], d2[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0xd6,0x09] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst3.8 {d0, d1, d2}, [r4] + vst3.8 {d0, d1, d2}, [r4:16] + vst3.8 {d0, d1, d2}, [r4:32] + vst3.8 {d0, d1, d2}, [r4:64] + vst3.8 {d0, d1, d2}, [r4:128] + vst3.8 {d0, d1, d2}, [r4:256] + +@ CHECK: vst3.8 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x0f,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst3.8 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vst3.8 {d0, d1, d2}, [r4]! + vst3.8 {d0, d1, d2}, [r4:16]! + vst3.8 {d0, d1, d2}, [r4:32]! + vst3.8 {d0, d1, d2}, [r4:64]! + vst3.8 {d0, d1, d2}, [r4:128]! + vst3.8 {d0, d1, d2}, [r4:256]! + +@ CHECK: vst3.8 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst3.8 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst3.8 {d0, d1, d2}, [r4], r6 + vst3.8 {d0, d1, d2}, [r4:16], r6 + vst3.8 {d0, d1, d2}, [r4:32], r6 + vst3.8 {d0, d1, d2}, [r4:64], r6 + vst3.8 {d0, d1, d2}, [r4:128], r6 + vst3.8 {d0, d1, d2}, [r4:256], r6 + +@ CHECK: vst3.8 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst3.8 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst3.8 {d0, d2, d4}, [r4] + vst3.8 {d0, d2, d4}, [r4:16] + vst3.8 {d0, d2, d4}, [r4:32] + vst3.8 {d0, d2, d4}, [r4:64] + vst3.8 {d0, d2, d4}, [r4:128] + vst3.8 {d0, d2, d4}, [r4:256] + +@ CHECK: vst3.8 {d0, d2, d4}, [r4] @ encoding: [0x04,0xf9,0x0f,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst3.8 {d0, d2, d4}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:256] +@ CHECK-ERRORS: ^ + + vst3.8 {d0, d2, d4}, [r4]! + vst3.8 {d0, d2, d4}, [r4:16]! + vst3.8 {d0, d2, d4}, [r4:32]! + vst3.8 {d0, d2, d4}, [r4:64]! + vst3.8 {d0, d2, d4}, [r4:128]! + vst3.8 {d0, d2, d4}, [r4:256]! + +@ CHECK: vst3.8 {d0, d2, d4}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst3.8 {d0, d2, d4}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst3.8 {d0, d2, d4}, [r4], r6 + vst3.8 {d0, d2, d4}, [r4:16], r6 + vst3.8 {d0, d2, d4}, [r4:32], r6 + vst3.8 {d0, d2, d4}, [r4:64], r6 + vst3.8 {d0, d2, d4}, [r4:128], r6 + vst3.8 {d0, d2, d4}, [r4:256], r6 + +@ CHECK: vst3.8 {d0, d2, d4}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst3.8 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst3.8 {d0[1], d1[1], d2[1]}, [r4] + vst3.8 {d0[1], d1[1], d2[1]}, [r4:16] + vst3.8 {d0[1], d1[1], d2[1]}, [r4:32] + vst3.8 {d0[1], d1[1], d2[1]}, [r4:64] + vst3.8 {d0[1], d1[1], d2[1]}, [r4:128] + vst3.8 {d0[1], d1[1], d2[1]}, [r4:256] + +@ CHECK: vst3.8 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0x84,0xf9,0x2f,0x02] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst3.8 {d0[1], d1[1], d2[1]}, [r4]! + vst3.8 {d0[1], d1[1], d2[1]}, [r4:16]! + vst3.8 {d0[1], d1[1], d2[1]}, [r4:32]! + vst3.8 {d0[1], d1[1], d2[1]}, [r4:64]! + vst3.8 {d0[1], d1[1], d2[1]}, [r4:128]! + vst3.8 {d0[1], d1[1], d2[1]}, [r4:256]! + +@ CHECK: vst3.8 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0x84,0xf9,0x2d,0x02] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst3.8 {d0[1], d1[1], d2[1]}, [r4], r6 + vst3.8 {d0[1], d1[1], d2[1]}, [r4:16], r6 + vst3.8 {d0[1], d1[1], d2[1]}, [r4:32], r6 + vst3.8 {d0[1], d1[1], d2[1]}, [r4:64], r6 + vst3.8 {d0[1], d1[1], d2[1]}, [r4:128], r6 + vst3.8 {d0[1], d1[1], d2[1]}, [r4:256], r6 + +@ CHECK: vst3.8 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x26,0x02] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst3.16 {d0, d1, d2}, [r4] + vst3.16 {d0, d1, d2}, [r4:16] + vst3.16 {d0, d1, d2}, [r4:32] + vst3.16 {d0, d1, d2}, [r4:64] + vst3.16 {d0, d1, d2}, [r4:128] + vst3.16 {d0, d1, d2}, [r4:256] + +@ CHECK: vst3.16 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x4f,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst3.16 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vst3.16 {d0, d1, d2}, [r4]! + vst3.16 {d0, d1, d2}, [r4:16]! + vst3.16 {d0, d1, d2}, [r4:32]! + vst3.16 {d0, d1, d2}, [r4:64]! + vst3.16 {d0, d1, d2}, [r4:128]! + vst3.16 {d0, d1, d2}, [r4:256]! + +@ CHECK: vst3.16 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst3.16 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst3.16 {d0, d1, d2}, [r4], r6 + vst3.16 {d0, d1, d2}, [r4:16], r6 + vst3.16 {d0, d1, d2}, [r4:32], r6 + vst3.16 {d0, d1, d2}, [r4:64], r6 + vst3.16 {d0, d1, d2}, [r4:128], r6 + vst3.16 {d0, d1, d2}, [r4:256], r6 + +@ CHECK: vst3.16 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst3.16 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst3.16 {d0, d2, d4}, [r4] + vst3.16 {d0, d2, d4}, [r4:16] + vst3.16 {d0, d2, d4}, [r4:32] + vst3.16 {d0, d2, d4}, [r4:64] + vst3.16 {d0, d2, d4}, [r4:128] + vst3.16 {d0, d2, d4}, [r4:256] + +@ CHECK: vst3.16 {d0, d2, d4}, [r4] @ encoding: [0x04,0xf9,0x4f,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst3.16 {d0, d2, d4}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:256] +@ CHECK-ERRORS: ^ + + vst3.16 {d0, d2, d4}, [r4]! + vst3.16 {d0, d2, d4}, [r4:16]! + vst3.16 {d0, d2, d4}, [r4:32]! + vst3.16 {d0, d2, d4}, [r4:64]! + vst3.16 {d0, d2, d4}, [r4:128]! + vst3.16 {d0, d2, d4}, [r4:256]! + +@ CHECK: vst3.16 {d0, d2, d4}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst3.16 {d0, d2, d4}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst3.16 {d0, d2, d4}, [r4], r6 + vst3.16 {d0, d2, d4}, [r4:16], r6 + vst3.16 {d0, d2, d4}, [r4:32], r6 + vst3.16 {d0, d2, d4}, [r4:64], r6 + vst3.16 {d0, d2, d4}, [r4:128], r6 + vst3.16 {d0, d2, d4}, [r4:256], r6 + +@ CHECK: vst3.16 {d0, d2, d4}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst3.16 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst3.16 {d0[1], d1[1], d2[1]}, [r4] + vst3.16 {d0[1], d1[1], d2[1]}, [r4:16] + vst3.16 {d0[1], d1[1], d2[1]}, [r4:32] + vst3.16 {d0[1], d1[1], d2[1]}, [r4:64] + vst3.16 {d0[1], d1[1], d2[1]}, [r4:128] + vst3.16 {d0[1], d1[1], d2[1]}, [r4:256] + +@ CHECK: vst3.16 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0x84,0xf9,0x4f,0x06] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst3.16 {d0[1], d1[1], d2[1]}, [r4]! + vst3.16 {d0[1], d1[1], d2[1]}, [r4:16]! + vst3.16 {d0[1], d1[1], d2[1]}, [r4:32]! + vst3.16 {d0[1], d1[1], d2[1]}, [r4:64]! + vst3.16 {d0[1], d1[1], d2[1]}, [r4:128]! + vst3.16 {d0[1], d1[1], d2[1]}, [r4:256]! + +@ CHECK: vst3.16 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0x84,0xf9,0x4d,0x06] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst3.16 {d0[1], d1[1], d2[1]}, [r4], r6 + vst3.16 {d0[1], d1[1], d2[1]}, [r4:16], r6 + vst3.16 {d0[1], d1[1], d2[1]}, [r4:32], r6 + vst3.16 {d0[1], d1[1], d2[1]}, [r4:64], r6 + vst3.16 {d0[1], d1[1], d2[1]}, [r4:128], r6 + vst3.16 {d0[1], d1[1], d2[1]}, [r4:256], r6 + +@ CHECK: vst3.16 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x46,0x06] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst3.16 {d0[1], d2[1], d4[1]}, [r4] + vst3.16 {d0[1], d2[1], d4[1]}, [r4:16] + vst3.16 {d0[1], d2[1], d4[1]}, [r4:32] + vst3.16 {d0[1], d2[1], d4[1]}, [r4:64] + vst3.16 {d0[1], d2[1], d4[1]}, [r4:128] + vst3.16 {d0[1], d2[1], d4[1]}, [r4:256] + +@ CHECK: vst3.16 {d0[1], d2[1], d4[1]}, [r4] @ encoding: [0x84,0xf9,0x6f,0x06] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst3.16 {d0[1], d2[1], d4[1]}, [r4]! + vst3.16 {d0[1], d2[1], d4[1]}, [r4:16]! + vst3.16 {d0[1], d2[1], d4[1]}, [r4:32]! + vst3.16 {d0[1], d2[1], d4[1]}, [r4:64]! + vst3.16 {d0[1], d2[1], d4[1]}, [r4:128]! + vst3.16 {d0[1], d2[1], d4[1]}, [r4:256]! + +@ CHECK: vst3.16 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0x84,0xf9,0x6d,0x06] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst3.16 {d0[1], d2[1], d4[1]}, [r4], r6 + vst3.16 {d0[1], d2[1], d4[1]}, [r4:16], r6 + vst3.16 {d0[1], d2[1], d4[1]}, [r4:32], r6 + vst3.16 {d0[1], d2[1], d4[1]}, [r4:64], r6 + vst3.16 {d0[1], d2[1], d4[1]}, [r4:128], r6 + vst3.16 {d0[1], d2[1], d4[1]}, [r4:256], r6 + +@ CHECK: vst3.16 {d0[1], d2[1], d4[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x66,0x06] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst3.32 {d0, d1, d2}, [r4] + vst3.32 {d0, d1, d2}, [r4:16] + vst3.32 {d0, d1, d2}, [r4:32] + vst3.32 {d0, d1, d2}, [r4:64] + vst3.32 {d0, d1, d2}, [r4:128] + vst3.32 {d0, d1, d2}, [r4:256] + +@ CHECK: vst3.32 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x8f,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst3.32 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:256] +@ CHECK-ERRORS: ^ + + vst3.32 {d0, d1, d2}, [r4]! + vst3.32 {d0, d1, d2}, [r4:16]! + vst3.32 {d0, d1, d2}, [r4:32]! + vst3.32 {d0, d1, d2}, [r4:64]! + vst3.32 {d0, d1, d2}, [r4:128]! + vst3.32 {d0, d1, d2}, [r4:256]! + +@ CHECK: vst3.32 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst3.32 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst3.32 {d0, d1, d2}, [r4], r6 + vst3.32 {d0, d1, d2}, [r4:16], r6 + vst3.32 {d0, d1, d2}, [r4:32], r6 + vst3.32 {d0, d1, d2}, [r4:64], r6 + vst3.32 {d0, d1, d2}, [r4:128], r6 + vst3.32 {d0, d1, d2}, [r4:256], r6 + +@ CHECK: vst3.32 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst3.32 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x04] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst3.32 {d0, d2, d4}, [r4] + vst3.32 {d0, d2, d4}, [r4:16] + vst3.32 {d0, d2, d4}, [r4:32] + vst3.32 {d0, d2, d4}, [r4:64] + vst3.32 {d0, d2, d4}, [r4:128] + vst3.32 {d0, d2, d4}, [r4:256] + +@ CHECK: vst3.32 {d0, d2, d4}, [r4] @ encoding: [0x04,0xf9,0x8f,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst3.32 {d0, d2, d4}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:256] +@ CHECK-ERRORS: ^ + + vst3.32 {d0, d2, d4}, [r4]! + vst3.32 {d0, d2, d4}, [r4:16]! + vst3.32 {d0, d2, d4}, [r4:32]! + vst3.32 {d0, d2, d4}, [r4:64]! + vst3.32 {d0, d2, d4}, [r4:128]! + vst3.32 {d0, d2, d4}, [r4:256]! + +@ CHECK: vst3.32 {d0, d2, d4}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst3.32 {d0, d2, d4}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst3.32 {d0, d2, d4}, [r4], r6 + vst3.32 {d0, d2, d4}, [r4:16], r6 + vst3.32 {d0, d2, d4}, [r4:32], r6 + vst3.32 {d0, d2, d4}, [r4:64], r6 + vst3.32 {d0, d2, d4}, [r4:128], r6 + vst3.32 {d0, d2, d4}, [r4:256], r6 + +@ CHECK: vst3.32 {d0, d2, d4}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst3.32 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x05] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst3.32 {d0[1], d1[1], d2[1]}, [r4] + vst3.32 {d0[1], d1[1], d2[1]}, [r4:16] + vst3.32 {d0[1], d1[1], d2[1]}, [r4:32] + vst3.32 {d0[1], d1[1], d2[1]}, [r4:64] + vst3.32 {d0[1], d1[1], d2[1]}, [r4:128] + vst3.32 {d0[1], d1[1], d2[1]}, [r4:256] + +@ CHECK: vst3.32 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0x84,0xf9,0x8f,0x0a] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst3.32 {d0[1], d1[1], d2[1]}, [r4]! + vst3.32 {d0[1], d1[1], d2[1]}, [r4:16]! + vst3.32 {d0[1], d1[1], d2[1]}, [r4:32]! + vst3.32 {d0[1], d1[1], d2[1]}, [r4:64]! + vst3.32 {d0[1], d1[1], d2[1]}, [r4:128]! + vst3.32 {d0[1], d1[1], d2[1]}, [r4:256]! + +@ CHECK: vst3.32 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x0a] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst3.32 {d0[1], d1[1], d2[1]}, [r4], r6 + vst3.32 {d0[1], d1[1], d2[1]}, [r4:16], r6 + vst3.32 {d0[1], d1[1], d2[1]}, [r4:32], r6 + vst3.32 {d0[1], d1[1], d2[1]}, [r4:64], r6 + vst3.32 {d0[1], d1[1], d2[1]}, [r4:128], r6 + vst3.32 {d0[1], d1[1], d2[1]}, [r4:256], r6 + +@ CHECK: vst3.32 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x0a] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst3.32 {d0[1], d2[1], d4[1]}, [r4] + vst3.32 {d0[1], d2[1], d4[1]}, [r4:16] + vst3.32 {d0[1], d2[1], d4[1]}, [r4:32] + vst3.32 {d0[1], d2[1], d4[1]}, [r4:64] + vst3.32 {d0[1], d2[1], d4[1]}, [r4:128] + vst3.32 {d0[1], d2[1], d4[1]}, [r4:256] + +@ CHECK: vst3.32 {d0[1], d2[1], d4[1]}, [r4] @ encoding: [0x84,0xf9,0xcf,0x0a] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst3.32 {d0[1], d2[1], d4[1]}, [r4]! + vst3.32 {d0[1], d2[1], d4[1]}, [r4:16]! + vst3.32 {d0[1], d2[1], d4[1]}, [r4:32]! + vst3.32 {d0[1], d2[1], d4[1]}, [r4:64]! + vst3.32 {d0[1], d2[1], d4[1]}, [r4:128]! + vst3.32 {d0[1], d2[1], d4[1]}, [r4:256]! + +@ CHECK: vst3.32 {d0[1], d2[1], d4[1]}, [r4]! @ encoding: [0x84,0xf9,0xcd,0x0a] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst3.32 {d0[1], d2[1], d4[1]}, [r4], r6 + vst3.32 {d0[1], d2[1], d4[1]}, [r4:16], r6 + vst3.32 {d0[1], d2[1], d4[1]}, [r4:32], r6 + vst3.32 {d0[1], d2[1], d4[1]}, [r4:64], r6 + vst3.32 {d0[1], d2[1], d4[1]}, [r4:128], r6 + vst3.32 {d0[1], d2[1], d4[1]}, [r4:256], r6 + +@ CHECK: vst3.32 {d0[1], d2[1], d4[1]}, [r4], r6 @ encoding: [0x84,0xf9,0xc6,0x0a] +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be omitted +@ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst4.8 {d0, d1, d2, d3}, [r4] + vst4.8 {d0, d1, d2, d3}, [r4:16] + vst4.8 {d0, d1, d2, d3}, [r4:32] + vst4.8 {d0, d1, d2, d3}, [r4:64] + vst4.8 {d0, d1, d2, d3}, [r4:128] + vst4.8 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x0f,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x00] +@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x00] +@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0x3f,0x00] + + vst4.8 {d0, d1, d2, d3}, [r4]! + vst4.8 {d0, d1, d2, d3}, [r4:16]! + vst4.8 {d0, d1, d2, d3}, [r4:32]! + vst4.8 {d0, d1, d2, d3}, [r4:64]! + vst4.8 {d0, d1, d2, d3}, [r4:128]! + vst4.8 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x00] +@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x00] +@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0x3d,0x00] + + vst4.8 {d0, d1, d2, d3}, [r4], r6 + vst4.8 {d0, d1, d2, d3}, [r4:16], r6 + vst4.8 {d0, d1, d2, d3}, [r4:32], r6 + vst4.8 {d0, d1, d2, d3}, [r4:64], r6 + vst4.8 {d0, d1, d2, d3}, [r4:128], r6 + vst4.8 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x00] +@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x00] +@ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0x36,0x00] + + vst4.8 {d0, d2, d4, d6}, [r4] + vst4.8 {d0, d2, d4, d6}, [r4:16] + vst4.8 {d0, d2, d4, d6}, [r4:32] + vst4.8 {d0, d2, d4, d6}, [r4:64] + vst4.8 {d0, d2, d4, d6}, [r4:128] + vst4.8 {d0, d2, d4, d6}, [r4:256] + +@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4] @ encoding: [0x04,0xf9,0x0f,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x01] +@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x01] +@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:256] @ encoding: [0x04,0xf9,0x3f,0x01] + + vst4.8 {d0, d2, d4, d6}, [r4]! + vst4.8 {d0, d2, d4, d6}, [r4:16]! + vst4.8 {d0, d2, d4, d6}, [r4:32]! + vst4.8 {d0, d2, d4, d6}, [r4:64]! + vst4.8 {d0, d2, d4, d6}, [r4:128]! + vst4.8 {d0, d2, d4, d6}, [r4:256]! + +@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x01] +@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x01] +@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:256]! @ encoding: [0x04,0xf9,0x3d,0x01] + + vst4.8 {d0, d2, d4, d6}, [r4], r6 + vst4.8 {d0, d2, d4, d6}, [r4:16], r6 + vst4.8 {d0, d2, d4, d6}, [r4:32], r6 + vst4.8 {d0, d2, d4, d6}, [r4:64], r6 + vst4.8 {d0, d2, d4, d6}, [r4:128], r6 + vst4.8 {d0, d2, d4, d6}, [r4:256], r6 + +@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x01] +@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x01] +@ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:256], r6 @ encoding: [0x04,0xf9,0x36,0x01] + + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4] + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] + +@ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0x84,0xf9,0x2f,0x03] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] @ encoding: [0x84,0xf9,0x3f,0x03] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]! + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! + +@ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0x84,0xf9,0x2d,0x03] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! @ encoding: [0x84,0xf9,0x3d,0x03] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 + vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 + +@ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x26,0x03] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 @ encoding: [0x84,0xf9,0x36,0x03] +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 32 or omitted +@ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst4.16 {d0, d1, d2, d3}, [r4] + vst4.16 {d0, d1, d2, d3}, [r4:16] + vst4.16 {d0, d1, d2, d3}, [r4:32] + vst4.16 {d0, d1, d2, d3}, [r4:64] + vst4.16 {d0, d1, d2, d3}, [r4:128] + vst4.16 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x4f,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x00] +@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0x6f,0x00] +@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0x7f,0x00] + + vst4.16 {d0, d1, d2, d3}, [r4]! + vst4.16 {d0, d1, d2, d3}, [r4:16]! + vst4.16 {d0, d1, d2, d3}, [r4:32]! + vst4.16 {d0, d1, d2, d3}, [r4:64]! + vst4.16 {d0, d1, d2, d3}, [r4:128]! + vst4.16 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x00] +@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0x6d,0x00] +@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0x7d,0x00] + + vst4.16 {d0, d1, d2, d3}, [r4], r6 + vst4.16 {d0, d1, d2, d3}, [r4:16], r6 + vst4.16 {d0, d1, d2, d3}, [r4:32], r6 + vst4.16 {d0, d1, d2, d3}, [r4:64], r6 + vst4.16 {d0, d1, d2, d3}, [r4:128], r6 + vst4.16 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x00] +@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0x66,0x00] +@ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0x76,0x00] + + vst4.16 {d0, d2, d4, d6}, [r4] + vst4.16 {d0, d2, d4, d6}, [r4:16] + vst4.16 {d0, d2, d4, d6}, [r4:32] + vst4.16 {d0, d2, d4, d6}, [r4:64] + vst4.16 {d0, d2, d4, d6}, [r4:128] + vst4.16 {d0, d2, d4, d6}, [r4:256] + +@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4] @ encoding: [0x04,0xf9,0x4f,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x01] +@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:128] @ encoding: [0x04,0xf9,0x6f,0x01] +@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:256] @ encoding: [0x04,0xf9,0x7f,0x01] + + vst4.16 {d0, d2, d4, d6}, [r4]! + vst4.16 {d0, d2, d4, d6}, [r4:16]! + vst4.16 {d0, d2, d4, d6}, [r4:32]! + vst4.16 {d0, d2, d4, d6}, [r4:64]! + vst4.16 {d0, d2, d4, d6}, [r4:128]! + vst4.16 {d0, d2, d4, d6}, [r4:256]! + +@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x01] +@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:128]! @ encoding: [0x04,0xf9,0x6d,0x01] +@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:256]! @ encoding: [0x04,0xf9,0x7d,0x01] + + vst4.16 {d0, d2, d4, d6}, [r4], r6 + vst4.16 {d0, d2, d4, d6}, [r4:16], r6 + vst4.16 {d0, d2, d4, d6}, [r4:32], r6 + vst4.16 {d0, d2, d4, d6}, [r4:64], r6 + vst4.16 {d0, d2, d4, d6}, [r4:128], r6 + vst4.16 {d0, d2, d4, d6}, [r4:256], r6 + +@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x01] +@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:128], r6 @ encoding: [0x04,0xf9,0x66,0x01] +@ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:256], r6 @ encoding: [0x04,0xf9,0x76,0x01] + + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4] + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] + +@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0x84,0xf9,0x4f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] @ encoding: [0x84,0xf9,0x5f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]! + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! + +@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0x84,0xf9,0x4d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0x84,0xf9,0x5d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 + vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 + +@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x46,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0x56,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4] + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16] + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32] + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] + +@ CHECK: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4] @ encoding: [0x84,0xf9,0x6f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] @ encoding: [0x84,0xf9,0x7f,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]! + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]! + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]! + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! + +@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0x84,0xf9,0x6d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0x84,0xf9,0x7d,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6 + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6 + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 + vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 + +@ CHECK: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x66,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0x76,0x07] +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64 or omitted +@ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst4.32 {d0, d1, d2, d3}, [r4] + vst4.32 {d0, d1, d2, d3}, [r4:16] + vst4.32 {d0, d1, d2, d3}, [r4:32] + vst4.32 {d0, d1, d2, d3}, [r4:64] + vst4.32 {d0, d1, d2, d3}, [r4:128] + vst4.32 {d0, d1, d2, d3}, [r4:256] + +@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x8f,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x00] +@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x00] +@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:256] @ encoding: [0x04,0xf9,0xbf,0x00] + + vst4.32 {d0, d1, d2, d3}, [r4]! + vst4.32 {d0, d1, d2, d3}, [r4:16]! + vst4.32 {d0, d1, d2, d3}, [r4:32]! + vst4.32 {d0, d1, d2, d3}, [r4:64]! + vst4.32 {d0, d1, d2, d3}, [r4:128]! + vst4.32 {d0, d1, d2, d3}, [r4:256]! + +@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x00] +@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x00] +@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:256]! @ encoding: [0x04,0xf9,0xbd,0x00] + + vst4.32 {d0, d1, d2, d3}, [r4], r6 + vst4.32 {d0, d1, d2, d3}, [r4:16], r6 + vst4.32 {d0, d1, d2, d3}, [r4:32], r6 + vst4.32 {d0, d1, d2, d3}, [r4:64], r6 + vst4.32 {d0, d1, d2, d3}, [r4:128], r6 + vst4.32 {d0, d1, d2, d3}, [r4:256], r6 + +@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x00] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x00] +@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x00] +@ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:256], r6 @ encoding: [0x04,0xf9,0xb6,0x00] + + vst4.32 {d0, d2, d4, d6}, [r4] + vst4.32 {d0, d2, d4, d6}, [r4:16] + vst4.32 {d0, d2, d4, d6}, [r4:32] + vst4.32 {d0, d2, d4, d6}, [r4:64] + vst4.32 {d0, d2, d4, d6}, [r4:128] + vst4.32 {d0, d2, d4, d6}, [r4:256] + +@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4] @ encoding: [0x04,0xf9,0x8f,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x01] +@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x01] +@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:256] @ encoding: [0x04,0xf9,0xbf,0x01] + + vst4.32 {d0, d2, d4, d6}, [r4]! + vst4.32 {d0, d2, d4, d6}, [r4:16]! + vst4.32 {d0, d2, d4, d6}, [r4:32]! + vst4.32 {d0, d2, d4, d6}, [r4:64]! + vst4.32 {d0, d2, d4, d6}, [r4:128]! + vst4.32 {d0, d2, d4, d6}, [r4:256]! + +@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x01] +@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x01] +@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:256]! @ encoding: [0x04,0xf9,0xbd,0x01] + + vst4.32 {d0, d2, d4, d6}, [r4], r6 + vst4.32 {d0, d2, d4, d6}, [r4:16], r6 + vst4.32 {d0, d2, d4, d6}, [r4:32], r6 + vst4.32 {d0, d2, d4, d6}, [r4:64], r6 + vst4.32 {d0, d2, d4, d6}, [r4:128], r6 + vst4.32 {d0, d2, d4, d6}, [r4:256], r6 + +@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x01] +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x01] +@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x01] +@ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:256], r6 @ encoding: [0x04,0xf9,0xb6,0x01] + + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4] + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] + +@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0x84,0xf9,0x8f,0x0b] +@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] @ encoding: [0x84,0xf9,0x9f,0x0b] +@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] @ encoding: [0x84,0xf9,0xaf,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]! + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! + +@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0x84,0xf9,0x9d,0x0b] +@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! @ encoding: [0x84,0xf9,0xad,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 + +@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0x96,0x0b] +@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 @ encoding: [0x84,0xf9,0xa6,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4] + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16] + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32] + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] + +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4] @ encoding: [0x84,0xf9,0xcf,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] @ encoding: [0x84,0xf9,0xdf,0x0b] +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] @ encoding: [0x84,0xf9,0xef,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]! + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]! + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]! + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! + +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]! @ encoding: [0x84,0xf9,0xcd,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! @ encoding: [0x84,0xf9,0xdd,0x0b] +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! @ encoding: [0x84,0xf9,0xed,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6 + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6 + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 + +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 @ encoding: [0x84,0xf9,0xc6,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0xd6,0x0b] +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 @ encoding: [0x84,0xf9,0xe6,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]! + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! + +@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0x84,0xf9,0x9d,0x0b] +@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! @ encoding: [0x84,0xf9,0xad,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 + vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 + +@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0x96,0x0b] +@ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 @ encoding: [0x84,0xf9,0xa6,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ + + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4] + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16] + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32] + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] + +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4] @ encoding: [0x84,0xf9,0xcf,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16] +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32] +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] @ encoding: [0x84,0xf9,0xdf,0x0b] +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] @ encoding: [0x84,0xf9,0xef,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] +@ CHECK-ERRORS: ^ + + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]! + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]! + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]! + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! + +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]! @ encoding: [0x84,0xf9,0xcd,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]! +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]! +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! @ encoding: [0x84,0xf9,0xdd,0x0b] +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! @ encoding: [0x84,0xf9,0xed,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! +@ CHECK-ERRORS: ^ + + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6 + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6 + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 + vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 + +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 @ encoding: [0x84,0xf9,0xc6,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6 +@ CHECK-ERRORS: ^ +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0xd6,0x0b] +@ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 @ encoding: [0x84,0xf9,0xe6,0x0b] +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 +@ CHECK-ERRORS: ^ diff --git a/test/MC/ARM/pool.s b/test/MC/ARM/pool.s index 926b4f1..782f67e 100644 --- a/test/MC/ARM/pool.s +++ b/test/MC/ARM/pool.s @@ -16,3 +16,4 @@ pool: @ CHECK-LABEL: .Ltmp0: @ CHECK: .long 3126770193 + diff --git a/test/MC/ARM/symbol-variants.s b/test/MC/ARM/symbol-variants.s index e1036a3..a10fe50 100644 --- a/test/MC/ARM/symbol-variants.s +++ b/test/MC/ARM/symbol-variants.s @@ -2,6 +2,7 @@ @ RUN: llvm-mc < %s -triple thumbv7-none-linux-gnueabi -filetype=obj | llvm-objdump -triple thumbv7-none-linux-gnueabi -r - | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB @ CHECK-LABEL: RELOCATION RECORDS FOR [.rel.text] +.Lsym: @ empty .word f00 @@ -83,3 +84,8 @@ bl f05(plt) @ CHECK: 60 R_ARM_TLS_GOTDESC f24 @ CHECK: 64 R_ARM_TLS_GOTDESC f25 +@ got_prel +.word f26(GOT_PREL) + (. - .Lsym) + ldr r3, =f27(GOT_PREL) +@ CHECK: 68 R_ARM_GOT_PREL f26 +@ CHECK: 70 R_ARM_GOT_PREL f27 diff --git a/test/MC/ARM/thumb2-diagnostics.s b/test/MC/ARM/thumb2-diagnostics.s index 6ac2db0..b2b14bc 100644 --- a/test/MC/ARM/thumb2-diagnostics.s +++ b/test/MC/ARM/thumb2-diagnostics.s @@ -70,3 +70,21 @@ @ CHECK-ERRORS: error: branch target out of range @ CHECK-ERRORS: error: branch target out of range @ CHECK-ERRORS: error: branch target out of range + +foo2: + mov r0, foo2 + movw r0, foo2 + movt r0, foo2 +@ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16 +@ CHECK-ERRORS: ^ + + and sp, r1, #80008000 + and pc, r1, #80008000 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction + + diff --git a/test/MC/ARM/thumb2-strd.s b/test/MC/ARM/thumb2-strd.s new file mode 100644 index 0000000..3f8025d --- /dev/null +++ b/test/MC/ARM/thumb2-strd.s @@ -0,0 +1,10 @@ +@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s +.text +.thumb + +@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid operand for instruction +@ CHECK: error: invalid operand for instruction +strd r12, SP, [r0, #256] +strd r12, SP, [r0, #256]! +strd r12, SP, [r0], #256 diff --git a/test/MC/ARM/thumb2be-b.w-encoding.s b/test/MC/ARM/thumb2be-b.w-encoding.s new file mode 100644 index 0000000..2c3e31b --- /dev/null +++ b/test/MC/ARM/thumb2be-b.w-encoding.s @@ -0,0 +1,9 @@ +@ RUN: llvm-mc -triple=thumbv7-none-linux-gnueabi -show-encoding < %s | FileCheck %s --check-prefix=CHECK-LE +@ RUN: llvm-mc -triple=thumbebv7-none-linux-gnueabi -show-encoding < %s | FileCheck %s --check-prefix=CHECK-BE + +b.w bar +@ CHECK-LE: b.w bar @ encoding: [A,0xf0'A',A,0x90'A'] +@ CHECK-LE-NEXT: @ fixup A - offset: 0, value: bar, kind: fixup_t2_uncondbranch +@ CHECK-BE: b.w bar @ encoding: [0xf0'A',A,0x90'A',A] +@ CHECK-BE-NEXT: @ fixup A - offset: 0, value: bar, kind: fixup_t2_uncondbranch + diff --git a/test/MC/ARM/thumb2be-beq.w-encoding.s b/test/MC/ARM/thumb2be-beq.w-encoding.s new file mode 100644 index 0000000..e39e541 --- /dev/null +++ b/test/MC/ARM/thumb2be-beq.w-encoding.s @@ -0,0 +1,9 @@ +@ RUN: llvm-mc -triple=thumbv7-none-linux-gnueabi -show-encoding < %s | FileCheck %s --check-prefix=CHECK-LE +@ RUN: llvm-mc -triple=thumbebv7-none-linux-gnueabi -show-encoding < %s | FileCheck %s --check-prefix=CHECK-BE + +beq.w bar +@ CHECK-LE: beq.w bar @ encoding: [A,0xf0'A',A,0x80'A'] +@ CHECK-LE-NEXT: @ fixup A - offset: 0, value: bar, kind: fixup_t2_condbranch +@ CHECK-BE: beq.w bar @ encoding: [0xf0'A',A,0x80'A',A] +@ CHECK-BE-NEXT: @ fixup A - offset: 0, value: bar, kind: fixup_t2_condbranch + diff --git a/test/MC/ARM/thumb2be-movt-encoding.s b/test/MC/ARM/thumb2be-movt-encoding.s new file mode 100644 index 0000000..cc6c04e --- /dev/null +++ b/test/MC/ARM/thumb2be-movt-encoding.s @@ -0,0 +1,9 @@ +@ RUN: llvm-mc -triple=thumbv7-none-linux-gnueabi -show-encoding < %s | FileCheck %s --check-prefix=CHECK-LE +@ RUN: llvm-mc -triple=thumbebv7-none-linux-gnueabi -show-encoding < %s | FileCheck %s --check-prefix=CHECK-BE + +movt r9, :upper16:(_bar) +@ CHECK-LE: movt r9, :upper16:_bar @ encoding: [0xc0'A',0xf2'A',0b0000AAAA,0x09] +@ CHECK-LE-NEXT: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_movt_hi16 +@ CHECK-BE: movt r9, :upper16:_bar @ encoding: [0xf2,0b1100AAAA,0x09'A',A] +@ CHECK-BE-NEXT: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_movt_hi16 + diff --git a/test/MC/ARM/thumb2be-movw-encoding.s b/test/MC/ARM/thumb2be-movw-encoding.s new file mode 100644 index 0000000..3bff457 --- /dev/null +++ b/test/MC/ARM/thumb2be-movw-encoding.s @@ -0,0 +1,9 @@ +@ RUN: llvm-mc -triple=thumbv7-none-linux-gnueabi -show-encoding < %s | FileCheck %s --check-prefix=CHECK-LE +@ RUN: llvm-mc -triple=thumbebv7-none-linux-gnueabi -show-encoding < %s | FileCheck %s --check-prefix=CHECK-BE + +movw r9, :lower16:(_bar) +@ CHECK-LE: movw r9, :lower16:_bar @ encoding: [0x40'A',0xf2'A',0b0000AAAA,0x09] +@ CHECK-LE-NEXT: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_movw_lo16 +@ CHECK-BE: movw r9, :lower16:_bar @ encoding: [0xf2,0b0100AAAA,0x09'A',A] +@ CHECK-BE-NEXT: @ fixup A - offset: 0, value: _bar, kind: fixup_t2_movw_lo16 + diff --git a/test/MC/ARM/thumb_set.s b/test/MC/ARM/thumb_set.s index d0bc985..d2a0dc0 100644 --- a/test/MC/ARM/thumb_set.s +++ b/test/MC/ARM/thumb_set.s @@ -1,6 +1,9 @@ @ RUN: llvm-mc -triple armv7-eabi -filetype obj -o - %s | llvm-readobj -t \ @ RUN: | FileCheck %s +@ RUN: llvm-mc -triple armv7-eabi -filetype asm -o - %s \ +@ RUN: | FileCheck --check-prefix=ASM %s + .syntax unified .arm @@ -11,6 +14,11 @@ arm_func: .thumb_set alias_arm_func, arm_func + alias_arm_func2 = alias_arm_func + alias_arm_func3 = alias_arm_func2 + +@ ASM: .thumb_set alias_arm_func, arm_func + .thumb .type thumb_func,%function @@ -51,8 +59,6 @@ beta: .thumb_set beta, alpha - .thumb_set alias_undefined, undefined - @ CHECK: Symbol { @ CHECK: Name: alias_arm_func @ CHECK: Value: 0x1 @@ -60,6 +66,18 @@ beta: @ CHECK: } @ CHECK: Symbol { +@ CHECK: Name: alias_arm_func2 +@ CHECK: Value: 0x1 +@ CHECK: Type: Function +@ CHECK: } + +@ CHECK: Symbol { +@ CHECK: Name: alias_arm_func3 +@ CHECK: Value: 0x1 +@ CHECK: Type: Function +@ CHECK: } + +@ CHECK: Symbol { @ CHECK: Name: alias_defined_data @ CHECK: Value: 0x5 @ CHECK: Type: Function @@ -89,6 +107,16 @@ beta: @ CHECK: Type: Function @ CHECK: } +@ CHECK: Symbol { +@ CHECK: Name: badblood +@ CHECK-NEXT: Value: 0x0 +@ CHECK-NEXT: Size: 0 +@ CHECK-NEXT: Binding: Local +@ CHECK-NEXT: Type: Object +@ CHECK-NEXT: Other: 0 +@ CHECK-NEXT: Section: .data +@ CHECK-NEXT: } + @ CHECK: Symbol { @ CHECK: Name: bedazzle @ CHECK: Value: 0x4 @@ -124,16 +152,3 @@ beta: @ CHECK: Value: 0x5 @ CHECK: Type: Function @ CHECK: } - -@ CHECK: Symbol { -@ CHECK: Name: badblood -@ CHECK: Value: 0x0 -@ CHECK: Type: Object -@ CHECK: } - -@ CHECK: Symbol { -@ CHECK: Name: undefined -@ CHECK: Value: 0x0 -@ CHECK: Type: None -@ CHECK: } - diff --git a/test/MC/ARM/udf-arm-diagnostics.s b/test/MC/ARM/udf-arm-diagnostics.s new file mode 100644 index 0000000..9ec9bf2 --- /dev/null +++ b/test/MC/ARM/udf-arm-diagnostics.s @@ -0,0 +1,19 @@ +@ RUN: not llvm-mc -triple arm-eabi %s 2>&1 | FileCheck %s + + .syntax unified + .text + .arm + +undefined: + udfpl + +@ CHECK: error: instruction 'udf' is not predicable, but condition code specified +@ CHECK: udfpl +@ CHECK: ^ + + udf #65536 + +@ CHECK: error: invalid operand for instruction +@ CHECK: udf #65536 +@ CHECK: ^ + diff --git a/test/MC/ARM/udf-arm.s b/test/MC/ARM/udf-arm.s new file mode 100644 index 0000000..a9d19ca --- /dev/null +++ b/test/MC/ARM/udf-arm.s @@ -0,0 +1,11 @@ +@ RUN: llvm-mc -triple arm-eabi -show-encoding %s | FileCheck %s + + .syntax unified + .text + .arm + +undefined: + udf #0 + +@ CHECK: udf #0 @ encoding: [0xf0,0x00,0xf0,0xe7] + diff --git a/test/MC/ARM/udf-thumb-2-diagnostics.s b/test/MC/ARM/udf-thumb-2-diagnostics.s new file mode 100644 index 0000000..f837560 --- /dev/null +++ b/test/MC/ARM/udf-thumb-2-diagnostics.s @@ -0,0 +1,25 @@ +@ RUN: not llvm-mc -triple thumbv7-eabi -mattr +thumb2 %s 2>&1 | FileCheck %s + + .syntax unified + .text + .thumb + +undefined: + udfpl + +@ CHECK: error: instruction 'udf' is not predicable, but condition code specified +@ CHECK: udfpl +@ CHECK: ^ + + udf #256 + +@ CHECK: error: instruction requires: arm-mode +@ CHECK: udf #256 +@ CHECK: ^ + + udf.w #65536 + +@ CHECK: error: invalid operand for instruction +@ CHECK: udf.w #65536 +@ CHECK: ^ + diff --git a/test/MC/ARM/udf-thumb-2.s b/test/MC/ARM/udf-thumb-2.s new file mode 100644 index 0000000..beb6549 --- /dev/null +++ b/test/MC/ARM/udf-thumb-2.s @@ -0,0 +1,13 @@ +@ RUN: llvm-mc -triple thumbv7-eabi -mattr +thumb2 -show-encoding %s | FileCheck %s + + .syntax unified + .text + .thumb + +undefined: + udf #0 + udf.w #0 + +@ CHECK: udf #0 @ encoding: [0x00,0xde] +@ CHECK: udf.w #0 @ encoding: [0xf0,0xf7,0x00,0xa0] + diff --git a/test/MC/ARM/udf-thumb-diagnostics.s b/test/MC/ARM/udf-thumb-diagnostics.s new file mode 100644 index 0000000..51388d0 --- /dev/null +++ b/test/MC/ARM/udf-thumb-diagnostics.s @@ -0,0 +1,19 @@ +@ RUN: not llvm-mc -triple thumbv6m-eabi %s 2>&1 | FileCheck %s + + .syntax unified + .text + .thumb + +undefined: + udfpl + +@ CHECK: error: conditional execution not supported in Thumb1 +@ CHECK: udfpl +@ CHECK: ^ + + udf #256 + +@ CHECK: error: instruction requires: arm-mode +@ CHECK: udf #256 +@ CHECK: ^ + diff --git a/test/MC/ARM/udf-thumb.s b/test/MC/ARM/udf-thumb.s new file mode 100644 index 0000000..10b3aff --- /dev/null +++ b/test/MC/ARM/udf-thumb.s @@ -0,0 +1,11 @@ +@ RUN: llvm-mc -triple thumbv6m-eabi -show-encoding %s | FileCheck %s + + .syntax unified + .text + .thumb + +undefined: + udf #0 + +@ CHECK: udf #0 @ encoding: [0x00,0xde] + diff --git a/test/MC/ARM/vmov-vmvn-byte-replicate.s b/test/MC/ARM/vmov-vmvn-byte-replicate.s new file mode 100644 index 0000000..5931160 --- /dev/null +++ b/test/MC/ARM/vmov-vmvn-byte-replicate.s @@ -0,0 +1,31 @@ +@ PR18921, "vmov" part. +@ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s +.text + +@ CHECK: vmov.i8 d2, #0xff @ encoding: [0x1f,0x2e,0x87,0xf3] +@ CHECK: vmov.i8 q2, #0xff @ encoding: [0x5f,0x4e,0x87,0xf3] +@ CHECK: vmov.i8 d2, #0xab @ encoding: [0x1b,0x2e,0x82,0xf3] +@ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3] +@ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3] +@ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3] + +@ CHECK: vmov.i8 d2, #0x0 @ encoding: [0x10,0x2e,0x80,0xf2] +@ CHECK: vmov.i8 q2, #0x0 @ encoding: [0x50,0x4e,0x80,0xf2] +@ CHECK: vmov.i8 d2, #0x54 @ encoding: [0x14,0x2e,0x85,0xf2] +@ CHECK: vmov.i8 q2, #0x54 @ encoding: [0x54,0x4e,0x85,0xf2] +@ CHECK: vmov.i8 d2, #0x54 @ encoding: [0x14,0x2e,0x85,0xf2] +@ CHECK: vmov.i8 q2, #0x54 @ encoding: [0x54,0x4e,0x85,0xf2] + + vmov.i32 d2, #0xffffffff + vmov.i32 q2, #0xffffffff + vmov.i32 d2, #0xabababab + vmov.i32 q2, #0xabababab + vmov.i16 q2, #0xabab + vmov.i16 q2, #0xabab + + vmvn.i32 d2, #0xffffffff + vmvn.i32 q2, #0xffffffff + vmvn.i32 d2, #0xabababab + vmvn.i32 q2, #0xabababab + vmvn.i16 d2, #0xabab + vmvn.i16 q2, #0xabab diff --git a/test/MC/ARM/vmov-vmvn-illegal-cases.s b/test/MC/ARM/vmov-vmvn-illegal-cases.s new file mode 100644 index 0000000..4609b77 --- /dev/null +++ b/test/MC/ARM/vmov-vmvn-illegal-cases.s @@ -0,0 +1,30 @@ +@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s +.text + +@ CHECK: error: invalid operand for instruction +@ CHECK: vmov.i32 d2, #0xffffffab +@ CHECK: error: invalid operand for instruction +@ CHECK: vmov.i32 q2, #0xffffffab +@ CHECK: error: invalid operand for instruction +@ CHECK: vmov.i16 q2, #0xffab +@ CHECK: error: invalid operand for instruction +@ CHECK: vmov.i16 q2, #0xffab + +@ CHECK: error: invalid operand for instruction +@ CHECK: vmvn.i32 d2, #0xffffffab +@ CHECK: error: invalid operand for instruction +@ CHECK: vmvn.i32 q2, #0xffffffab +@ CHECK: error: invalid operand for instruction +@ CHECK: vmvn.i16 q2, #0xffab +@ CHECK: error: invalid operand for instruction +@ CHECK: vmvn.i16 q2, #0xffab + + vmov.i32 d2, #0xffffffab + vmov.i32 q2, #0xffffffab + vmov.i16 q2, #0xffab + vmov.i16 q2, #0xffab + + vmvn.i32 d2, #0xffffffab + vmvn.i32 q2, #0xffffffab + vmvn.i16 q2, #0xffab + vmvn.i16 q2, #0xffab diff --git a/test/MC/ARM/vorr-vbic-illegal-cases.s b/test/MC/ARM/vorr-vbic-illegal-cases.s new file mode 100644 index 0000000..16ab6b5 --- /dev/null +++ b/test/MC/ARM/vorr-vbic-illegal-cases.s @@ -0,0 +1,42 @@ +@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s +.text + +@ CHECK: error: invalid operand for instruction +@ CHECK: vorr.i32 d2, #0xffffffff +@ CHECK: error: invalid operand for instruction +@ CHECK: vorr.i32 q2, #0xffffffff +@ CHECK: error: invalid operand for instruction +@ CHECK: vorr.i32 d2, #0xabababab +@ CHECK: error: invalid operand for instruction +@ CHECK: vorr.i32 q2, #0xabababab +@ CHECK: error: invalid operand for instruction +@ CHECK: vorr.i16 q2, #0xabab +@ CHECK: error: invalid operand for instruction +@ CHECK: vorr.i16 q2, #0xabab + +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i32 d2, #0xffffffff +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i32 q2, #0xffffffff +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i32 d2, #0xabababab +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i32 q2, #0xabababab +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i16 d2, #0xabab +@ CHECK: error: invalid operand for instruction +@ CHECK: vbic.i16 q2, #0xabab + + vorr.i32 d2, #0xffffffff + vorr.i32 q2, #0xffffffff + vorr.i32 d2, #0xabababab + vorr.i32 q2, #0xabababab + vorr.i16 q2, #0xabab + vorr.i16 q2, #0xabab + + vbic.i32 d2, #0xffffffff + vbic.i32 q2, #0xffffffff + vbic.i32 d2, #0xabababab + vbic.i32 q2, #0xabababab + vbic.i16 d2, #0xabab + vbic.i16 q2, #0xabab diff --git a/test/MC/ARM64/lit.local.cfg b/test/MC/ARM64/lit.local.cfg deleted file mode 100644 index 49447af..0000000 --- a/test/MC/ARM64/lit.local.cfg +++ /dev/null @@ -1,6 +0,0 @@ -config.suffixes = ['.ll', '.c', '.cpp', '.s'] - -targets = set(config.root.targets_to_build.split()) -if not 'ARM64' in targets: - config.unsupported = True - diff --git a/test/MC/AsmParser/cfi-invalid-startproc.s b/test/MC/AsmParser/cfi-invalid-startproc.s new file mode 100644 index 0000000..57ded13 --- /dev/null +++ b/test/MC/AsmParser/cfi-invalid-startproc.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple=x86_64-apple-macosx10.8 -filetype=obj -o %t %s 2>&1 | FileCheck %s +# Check that the cfi_startproc is declared after the beginning of +# a procedure, otherwise it will reference an invalid symbol for +# emitting the relocation. +# <rdar://problem/15939159> + +# CHECK: No symbol to start a frame +.text +.cfi_startproc +.globl _someFunction +_someFunction: +.cfi_def_cfa_offset 16 +.cfi_offset %rbp, -16 +.cfi_def_cfa_register rbp + ret +.cfi_endproc diff --git a/test/MC/AsmParser/directive_seh.s b/test/MC/AsmParser/directive_seh.s index 98fc606..f6eb970 100644 --- a/test/MC/AsmParser/directive_seh.s +++ b/test/MC/AsmParser/directive_seh.s @@ -3,10 +3,10 @@ # CHECK: .seh_proc func # CHECK: .seh_pushframe @code # CHECK: .seh_stackalloc 24 -# CHECK: .seh_savereg 6, 16 -# CHECK: .seh_savexmm 8, 0 -# CHECK: .seh_pushreg 3 -# CHECK: .seh_setframe 3, 0 +# CHECK: .seh_savereg %rbp, 16 +# CHECK: .seh_savexmm %r8, 0 +# CHECK: .seh_pushreg %rbx +# CHECK: .seh_setframe %rbx, 0 # CHECK: .seh_endprologue # CHECK: .seh_handler __C_specific_handler, @except # CHECK-NOT: .section{{.*}}.xdata diff --git a/test/MC/AsmParser/invalid-input-assertion.s b/test/MC/AsmParser/invalid-input-assertion.s new file mode 100644 index 0000000..2557f6e --- /dev/null +++ b/test/MC/AsmParser/invalid-input-assertion.s @@ -0,0 +1,9 @@ +// RUN: not llvm-mc -triple i686-linux -o /dev/null %s + + .macro macro parameter=0 + .if \parameter + .else + .endm + + macro 1 + diff --git a/test/MC/AsmParser/macros-darwin-vararg.s b/test/MC/AsmParser/macros-darwin-vararg.s new file mode 100644 index 0000000..a650c08 --- /dev/null +++ b/test/MC/AsmParser/macros-darwin-vararg.s @@ -0,0 +1,8 @@ +// RUN: not llvm-mc -triple i386-apple-darwin10 %s 2>&1 | FileCheck %s + +// CHECK: error: vararg is not a valid parameter qualifier for 'arg' in macro 'abc' +// CHECK: .macro abc arg:vararg + +.macro abc arg:vararg + \arg +.endm diff --git a/test/MC/AsmParser/vararg-default-value.s b/test/MC/AsmParser/vararg-default-value.s new file mode 100644 index 0000000..77cd1e8 --- /dev/null +++ b/test/MC/AsmParser/vararg-default-value.s @@ -0,0 +1,15 @@ +// RUN: llvm-mc -triple x86_64-linux-gnu %s | FileCheck %s +.macro abc arg:vararg=nop + \arg +.endm + +.macro abcd arg0=%eax arg1:vararg=%ebx + movl \arg0, \arg1 +.endm + +.text + +// CHECK: nop + abc +// CHECK: movl %eax, %ebx + abcd , diff --git a/test/MC/AsmParser/vararg.s b/test/MC/AsmParser/vararg.s new file mode 100644 index 0000000..b27668e --- /dev/null +++ b/test/MC/AsmParser/vararg.s @@ -0,0 +1,41 @@ +// RUN: llvm-mc -triple x86_64-linux-gnu %s | FileCheck %s +.macro ifcc arg:vararg +.if cc + \arg +.endif +.endm + +.macro ifcc2 arg0 arg1:vararg +.if cc + movl \arg0, \arg1 +.endif +.endm + +.macro ifcc3 arg0, arg1:vararg +.if cc + movl \arg0, \arg1 +.endif +.endm + +.text + +// CHECK: movl %esp, %ebp +// CHECK: subl $0, %esp +// CHECK: movl %eax, %ebx +// CHECK: movl %ecx, %ebx +// CHECK: movl %ecx, %eax +// CHECK: movl %eax, %ecx +.set cc,1 + ifcc movl %esp, %ebp + subl $0, %esp + + ifcc2 %eax %ebx + ifcc2 %ecx, %ebx + ifcc3 %ecx %eax + ifcc3 %eax, %ecx + +// CHECK-NOT movl +// CHECK: subl $1, %esp +.set cc,0 + ifcc movl %esp, %ebp + subl $1, %esp diff --git a/test/MC/COFF/alias.s b/test/MC/COFF/alias.s index f6f6d46..dc4f65a 100644 --- a/test/MC/COFF/alias.s +++ b/test/MC/COFF/alias.s @@ -68,7 +68,7 @@ weak_aliased_to_external = external2 // CHECK-NEXT: Section: .text (1) // CHECK-NEXT: BaseType: Null (0x0) // CHECK-NEXT: ComplexType: Null (0x0) -// CHECK-NEXT: StorageClass: Static (0x3) +// CHECK-NEXT: StorageClass: External (0x2) // CHECK-NEXT: AuxSymbolCount: 0 // CHECK-NEXT: } // CHECK-NEXT: Symbol { diff --git a/test/MC/COFF/comm.ll b/test/MC/COFF/comm.ll index 74da557..6fe122e 100644 --- a/test/MC/COFF/comm.ll +++ b/test/MC/COFF/comm.ll @@ -9,5 +9,5 @@ ; CHECK: .lcomm _a,1 ; CHECK: .lcomm _b,8,8 ; .comm uses log2 alignment -; CHECK: .comm _c,1,0 -; CHECK: .comm _d,8,3 +; CHECK: .comm _c,1 +; CHECK: .comm _d,8 diff --git a/test/MC/COFF/comm.s b/test/MC/COFF/comm.s index 21ae5d2..37db75f 100644 --- a/test/MC/COFF/comm.s +++ b/test/MC/COFF/comm.s @@ -1,7 +1,7 @@ // RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | llvm-readobj -t | FileCheck %s .lcomm _a,4,4 -.comm _b, 4, 2 +.comm _b, 4 // CHECK: Symbol { @@ -17,7 +17,7 @@ // CHECK: Symbol { // CHECK: Name: _b // CHECK-NEXT: Value: 4 -// CHECK-NEXT: Section: .bss +// CHECK-NEXT: Section: (0) // CHECK-NEXT: BaseType: Null // CHECK-NEXT: ComplexType: Null // CHECK-NEXT: StorageClass: External diff --git a/test/MC/COFF/directive-section-characteristics.ll b/test/MC/COFF/directive-section-characteristics.ll new file mode 100644 index 0000000..ca8102a --- /dev/null +++ b/test/MC/COFF/directive-section-characteristics.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple i686-windows -filetype obj -o - %s | llvm-readobj -sections \ +; RUN: | FileCheck %s + +define dllexport void @function() { +entry: + ret void +} + +; CHECK: Section { +; CHECK: Name: .drectve +; CHECK: Characteristics [ +; CHECK: IMAGE_SCN_ALIGN_1BYTES +; CHECK: IMAGE_SCN_LNK_INFO +; CHECK: IMAGE_SCN_LNK_REMOVE +; CHECK: ] +; CHECK: } + diff --git a/test/MC/COFF/file.s b/test/MC/COFF/file.s new file mode 100644 index 0000000..132e82b --- /dev/null +++ b/test/MC/COFF/file.s @@ -0,0 +1,47 @@ +// RUN: llvm-mc -triple i686-windows -filetype obj %s -o - | llvm-objdump -t - \ +// RUN: | FileCheck %s + +// RUN: llvm-mc -triple i686-windows -filetype obj %s -o - \ +// RUN: | llvm-readobj -symbols | FileCheck %s -check-prefix CHECK-SCN + + .file "null-padded.asm" +// CHECK: (nx 1) {{0x[0-9]+}} .file +// CHECK-NEXT: AUX null-padded.asm{{$}} + + .file "eighteen-chars.asm" + +// CHECK: (nx 1) {{0x[0-9]+}} .file +// CHECK-NEXT: AUX eighteen-chars.asm{{$}} + + .file "multiple-auxiliary-entries.asm" + +// CHECK: (nx 2) {{0x[0-9]+}} .file +// CHECK-NEXT: AUX multiple-auxiliary-entries.asm{{$}} + +// CHECK-SCN: Symbols [ +// CHECK-SCN: Symbol { +// CHECK-SCN: Name: .file +// CHECK-SCN: Section: (65534) +// CHECK-SCN: StorageClass: File +// CHECK-SCN: AuxFileRecord { +// CHECK-SCN: FileName: null-padded.asm +// CHECK-SCN: } +// CHECK-SCN: } +// CHECK-SCN: Symbol { +// CHECK-SCN: Name: .file +// CHECK-SCN: Section: (65534) +// CHECK-SCN: StorageClass: File +// CHECK-SCN: AuxFileRecord { +// CHECK-SCN: FileName: eighteen-chars.asm +// CHECK-SCN: } +// CHECK-SCN: } +// CHECK-SCN: Symbol { +// CHECK-SCN: Name: .file +// CHECK-SCN: Section: (65534) +// CHECK-SCN: StorageClass: File +// CHECK-SCN: AuxFileRecord { +// CHECK-SCN: FileName: multiple-auxiliary-entries.asm +// CHECK-SCN: } +// CHECK-SCN: } +// CHECK-SCN: ] + diff --git a/test/MC/COFF/global_ctors_dtors.ll b/test/MC/COFF/global_ctors_dtors.ll index 2a25219..046e93a 100644 --- a/test/MC/COFF/global_ctors_dtors.ll +++ b/test/MC/COFF/global_ctors_dtors.ll @@ -9,8 +9,13 @@ @.str2 = private unnamed_addr constant [12 x i8] c"destructing\00", align 1 @.str3 = private unnamed_addr constant [5 x i8] c"main\00", align 1 -@llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @a_global_ctor }] -@llvm.global_dtors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @a_global_dtor }] +%ini = type { i32, void()*, i8* } + +@llvm.global_ctors = appending global [2 x %ini ] [ + %ini { i32 65535, void ()* @a_global_ctor, i8* null }, + %ini { i32 65535, void ()* @b_global_ctor, i8* bitcast (i32* @b to i8*) } +] +@llvm.global_dtors = appending global [1 x %ini ] [%ini { i32 65535, void ()* @a_global_dtor, i8* null }] declare i32 @puts(i8*) @@ -19,6 +24,13 @@ define void @a_global_ctor() nounwind { ret void } +@b = global i32 zeroinitializer + +define void @b_global_ctor() nounwind { + store i32 42, i32* @b + ret void +} + define void @a_global_dtor() nounwind { %1 = call i32 @puts(i8* getelementptr inbounds ([12 x i8]* @.str2, i32 0, i32 0)) ret void @@ -29,11 +41,15 @@ define i32 @main() nounwind { ret i32 0 } -; WIN32: .section .CRT$XCU,"r" +; WIN32: .section .CRT$XCU,"rd" ; WIN32: a_global_ctor -; WIN32: .section .CRT$XTX,"r" +; WIN32: .section .CRT$XCU,"rd",associative .bss,{{_?}}b +; WIN32: b_global_ctor +; WIN32: .section .CRT$XTX,"rd" ; WIN32: a_global_dtor -; MINGW32: .section .ctors,"w" +; MINGW32: .section .ctors,"wd" ; MINGW32: a_global_ctor -; MINGW32: .section .dtors,"w" +; MINGW32: .section .ctors,"wd",associative .bss,{{_?}}b +; MINGW32: b_global_ctor +; MINGW32: .section .dtors,"wd" ; MINGW32: a_global_dtor diff --git a/test/MC/COFF/initialised-data.ll b/test/MC/COFF/initialised-data.ll new file mode 100644 index 0000000..c428469 --- /dev/null +++ b/test/MC/COFF/initialised-data.ll @@ -0,0 +1,7 @@ +; RUN: llc -mtriple i686-windows %s -o - | FileCheck %s +; RUN: llc -mtriple x86_64-windows %s -o - | FileCheck %s + +@data = dllexport constant [5 x i8] c"data\00", align 1 + +; CHECK: .section .rdata,"rd" + diff --git a/test/MC/COFF/invalid-def.s b/test/MC/COFF/invalid-def.s new file mode 100644 index 0000000..42821c2 --- /dev/null +++ b/test/MC/COFF/invalid-def.s @@ -0,0 +1,5 @@ +# RUN: not llvm-mc -triple i686-windows -filetype obj -o /dev/null %s + + .def first + .def second + diff --git a/test/MC/COFF/invalid-endef.s b/test/MC/COFF/invalid-endef.s new file mode 100644 index 0000000..c6fd8f5 --- /dev/null +++ b/test/MC/COFF/invalid-endef.s @@ -0,0 +1,4 @@ +# RUN: not llvm-mc -triple i686-windows -filetype obj -o /dev/null %s + + .endef + diff --git a/test/MC/COFF/invalid-scl-range.s b/test/MC/COFF/invalid-scl-range.s new file mode 100644 index 0000000..5722505 --- /dev/null +++ b/test/MC/COFF/invalid-scl-range.s @@ -0,0 +1,6 @@ +# RUN: not llvm-mc -triple i686-windows -filetype obj -o /dev/null %s + + .def storage_class_range + .scl 1337 + .endef + diff --git a/test/MC/COFF/invalid-scl.s b/test/MC/COFF/invalid-scl.s new file mode 100644 index 0000000..8565a5a --- /dev/null +++ b/test/MC/COFF/invalid-scl.s @@ -0,0 +1,4 @@ +# RUN: not llvm-mc -triple i686-windows -filetype obj -o /dev/null %s + + .scl 1337 + diff --git a/test/MC/COFF/invalid-type-range.s b/test/MC/COFF/invalid-type-range.s new file mode 100644 index 0000000..92874cc --- /dev/null +++ b/test/MC/COFF/invalid-type-range.s @@ -0,0 +1,6 @@ +# RUN: not llvm-mc -triple i686-windows -filetype obj -o /dev/null %s + + .def invalid_type_range + .type 65536 + .endef + diff --git a/test/MC/COFF/invalid-type.s b/test/MC/COFF/invalid-type.s new file mode 100644 index 0000000..a1e131e --- /dev/null +++ b/test/MC/COFF/invalid-type.s @@ -0,0 +1,4 @@ +# RUN: not llvm-mc -triple i686-windows -filetype obj -o /dev/null %s + + .type 65536 + diff --git a/test/MC/COFF/offset.s b/test/MC/COFF/offset.s new file mode 100644 index 0000000..d0d3710 --- /dev/null +++ b/test/MC/COFF/offset.s @@ -0,0 +1,19 @@ +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s -o - | llvm-readobj -t -r | FileCheck %s + + .data + .globl test1_foo +test1_foo: + .long 42 + + .globl test1_zed +test1_zed = test1_foo + 1 + +// CHECK: Symbol { +// CHECK: Name: test1_zed +// CHECK-NEXT: Value: 1 +// CHECK-NEXT: Section: .data +// CHECK-NEXT: BaseType: Null +// CHECK-NEXT: ComplexType: Null +// CHECK-NEXT: StorageClass: External +// CHECK-NEXT: AuxSymbolCount: 0 +// CHECK-NEXT: } diff --git a/test/MC/COFF/symbol-alias.s b/test/MC/COFF/symbol-alias.s index ccada37..71ccec3 100644 --- a/test/MC/COFF/symbol-alias.s +++ b/test/MC/COFF/symbol-alias.s @@ -51,7 +51,7 @@ _bar_alias = _bar // CHECK-NEXT: Value: [[FOO_VALUE]] // CHECK-NEXT: Section: [[FOO_SECTION_NUMBER]] // CHECK-NEXT: BaseType: [[FOO_SIMPLE_TYPE]] -// CHECK-NEXT: ComplexType: [[FOO_COMPLEX_TYPE]] +// CHECK-NEXT: ComplexType: Null (0x0) // CHECK-NEXT: StorageClass: [[FOO_STORAGE_CLASS]] // CHECK-NEXT: AuxSymbolCount: [[FOO_NUMBER_OF_AUX_SYMBOLS]] diff --git a/test/MC/COFF/weak-symbol.ll b/test/MC/COFF/weak-symbol.ll index c06692e..fd78307 100644 --- a/test/MC/COFF/weak-symbol.ll +++ b/test/MC/COFF/weak-symbol.ll @@ -28,20 +28,20 @@ define weak void @f() section ".sect" { }
; Weak global
-; X86: .section .data,"r",discard,_a
+; X86: .section .data,"rd",discard,_a
; X86: .globl _a
; X86: .zero 12
;
-; X64: .section .data,"r",discard,a
+; X64: .section .data,"rd",discard,a
; X64: .globl a
; X64: .zero 12
@a = weak unnamed_addr constant { i32, i32, i32 } { i32 0, i32 0, i32 0}, section ".data"
-; X86: .section .tls$,"w",discard,_b
+; X86: .section .tls$,"wd",discard,_b
; X86: .globl _b
; X86: .long 0
;
-; X64: .section .tls$,"w",discard,b
+; X64: .section .tls$,"wd",discard,b
; X64: .globl b
; X64: .long 0
diff --git a/test/MC/Disassembler/AArch64/a64-ignored-fields.txt b/test/MC/Disassembler/AArch64/a64-ignored-fields.txt index 799ecdf..1860bf6 100644 --- a/test/MC/Disassembler/AArch64/a64-ignored-fields.txt +++ b/test/MC/Disassembler/AArch64/a64-ignored-fields.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s # The "Rm" bits are ignored, but the canonical representation has them filled # with 0s. This is what we should produce even if the input bit-pattern had diff --git a/test/MC/Disassembler/ARM64/advsimd.txt b/test/MC/Disassembler/AArch64/arm64-advsimd.txt index 486dd16..cceee67 100644 --- a/test/MC/Disassembler/ARM64/advsimd.txt +++ b/test/MC/Disassembler/AArch64/arm64-advsimd.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple arm64-apple-darwin -output-asm-variant=1 --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 --disassemble < %s | FileCheck %s 0x00 0xb8 0x20 0x0e 0x00 0xb8 0x20 0x4e @@ -124,10 +124,10 @@ # CHECK: smov.s x3, v2[2] # CHECK: smov.s x3, v2[2] -# CHECK: umov.s w3, v2[2] -# CHECK: umov.s w3, v2[2] -# CHECK: umov.d x3, v2[1] -# CHECK: umov.d x3, v2[1] +# CHECK: mov.s w3, v2[2] +# CHECK: mov.s w3, v2[2] +# CHECK: mov.d x3, v2[1] +# CHECK: mov.d x3, v2[1] 0xa2 0x1c 0x18 0x4e 0xa2 0x1c 0x0c 0x4e @@ -320,14 +320,14 @@ 0x00 0x1c 0x60 0x2e 0x00 0x1c 0x20 0x2e 0x00 0x1c 0xe0 0x0e -0x00 0x1c 0xa0 0x0e +0x00 0x1c 0xa1 0x0e # CHECK: bif.8b v0, v0, v0 # CHECK: bit.8b v0, v0, v0 # CHECK: bsl.8b v0, v0, v0 # CHECK: eor.8b v0, v0, v0 # CHECK: orn.8b v0, v0, v0 -# CHECK: orr.8b v0, v0, v0 +# CHECK: orr.8b v0, v0, v1 0x00 0x68 0x20 0x0e 0x00 0x68 0x20 0x4e @@ -445,7 +445,7 @@ # CHECK: frsqrte.2s v0, v0 # CHECK: fsqrt.2s v0, v0 # CHECK: neg.8b v0, v0 -# CHECK: not.8b v0, v0 +# CHECK: mvn.8b v0, v0 # CHECK: rbit.8b v0, v0 # CHECK: rev16.8b v0, v0 # CHECK: rev32.8b v0, v0 @@ -535,18 +535,18 @@ 0x20 0x54 0x00 0x2f 0x20 0x74 0x00 0x2f -# CHECK: bic.2s v0, #1 -# CHECK: bic.2s v0, #1, lsl #8 -# CHECK: bic.2s v0, #1, lsl #16 -# CHECK: bic.2s v0, #1, lsl #24 +# CHECK: bic.2s v0, #0x1 +# CHECK: bic.2s v0, #0x1, lsl #8 +# CHECK: bic.2s v0, #0x1, lsl #16 +# CHECK: bic.2s v0, #0x1, lsl #24 0x20 0x94 0x00 0x2f 0x20 0x94 0x00 0x2f 0x20 0xb4 0x00 0x2f -# CHECK: bic.4h v0, #1 -# CHECK: bic.4h v0, #1 -# FIXME: bic.4h v0, #1, lsl #8 +# CHECK: bic.4h v0, #0x1 +# CHECK: bic.4h v0, #0x1 +# FIXME: bic.4h v0, #0x1, lsl #8 # 'bic.4h' should be selected over "fcvtnu.2s v0, v1, #0" 0x20 0x14 0x00 0x6f @@ -554,43 +554,43 @@ 0x20 0x54 0x00 0x6f 0x20 0x74 0x00 0x6f -# CHECK: bic.4s v0, #1 -# CHECK: bic.4s v0, #1, lsl #8 -# CHECK: bic.4s v0, #1, lsl #16 -# CHECK: bic.4s v0, #1, lsl #24 +# CHECK: bic.4s v0, #0x1 +# CHECK: bic.4s v0, #0x1, lsl #8 +# CHECK: bic.4s v0, #0x1, lsl #16 +# CHECK: bic.4s v0, #0x1, lsl #24 0x20 0x94 0x00 0x6f 0x20 0xb4 0x00 0x6f -# CHECK: bic.8h v0, #1 -# FIXME: bic.8h v0, #1, lsl #8 +# CHECK: bic.8h v0, #0x1 +# FIXME: bic.8h v0, #0x1, lsl #8 # "bic.8h" should be selected over "fcvtnu.4s v0, v1, #0" 0x00 0xf4 0x02 0x6f -# CHECK: fmov.2d v0, #1.250000e-01 +# CHECK: fmov.2d v0, #0.12500000 0x00 0xf4 0x02 0x0f 0x00 0xf4 0x02 0x4f -# CHECK: fmov.2s v0, #1.250000e-01 -# CHECK: fmov.4s v0, #1.250000e-01 +# CHECK: fmov.2s v0, #0.12500000 +# CHECK: fmov.4s v0, #0.12500000 0x20 0x14 0x00 0x0f 0x20 0x34 0x00 0x0f 0x20 0x54 0x00 0x0f 0x20 0x74 0x00 0x0f -# CHECK: orr.2s v0, #1 -# CHECK: orr.2s v0, #1, lsl #8 -# CHECK: orr.2s v0, #1, lsl #16 -# CHECK: orr.2s v0, #1, lsl #24 +# CHECK: orr.2s v0, #0x1 +# CHECK: orr.2s v0, #0x1, lsl #8 +# CHECK: orr.2s v0, #0x1, lsl #16 +# CHECK: orr.2s v0, #0x1, lsl #24 0x20 0x94 0x00 0x0f 0x20 0xb4 0x00 0x0f -# CHECK: orr.4h v0, #1 -# FIXME: orr.4h v0, #1, lsl #8 +# CHECK: orr.4h v0, #0x1 +# FIXME: orr.4h v0, #0x1, lsl #8 # 'orr.4h' should be selected over "fcvtns.2s v0, v1, #0" 0x20 0x14 0x00 0x4f @@ -598,17 +598,16 @@ 0x20 0x54 0x00 0x4f 0x20 0x74 0x00 0x4f -# CHECK: orr.4s v0, #1 -# CHECK: orr.4s v0, #1, lsl #8 -# CHECK: orr.4s v0, #1, lsl #16 -# CHECK: orr.4s v0, #1, lsl #24 +# CHECK: orr.4s v0, #0x1 +# CHECK: orr.4s v0, #0x1, lsl #8 +# CHECK: orr.4s v0, #0x1, lsl #16 +# CHECK: orr.4s v0, #0x1, lsl #24 0x20 0x94 0x00 0x4f 0x20 0xb4 0x00 0x4f -# CHECK: orr.8h v0, #1 -# FIXME: orr.8h v0, #1, lsl #8 -# "orr.8h" should be selected over "fcvtns.4s v0, v1, #0" +# CHECK: orr.8h v0, #0x1 +# CHECK: orr.8h v0, #0x1, lsl #8 0x21 0x70 0x40 0x0c 0x42 0xa0 0x40 0x4c @@ -618,6 +617,7 @@ 0x0a 0x68 0x40 0x4c 0x2d 0xac 0x40 0x0c 0x4f 0x7c 0x40 0x4c +0xe0 0x03 0x40 0x0d # CHECK: ld1.8b { v1 }, [x1] # CHECK: ld1.16b { v2, v3 }, [x2] @@ -627,6 +627,7 @@ # CHECK: ld1.4s { v10, v11, v12 }, [x0] # CHECK: ld1.1d { v13, v14 }, [x1] # CHECK: ld1.2d { v15 }, [x2] +# CHECK: ld1.b { v0 }[0], [sp] 0x41 0x70 0xdf 0x0c 0x41 0xa0 0xdf 0x0c @@ -1443,82 +1444,82 @@ # CHECK: movi d0, #0x000000000000ff # CHECK: movi.2d v0, #0x000000000000ff -# CHECK: movi.8b v0, #1 -# CHECK: movi.16b v0, #1 +# CHECK: movi.8b v0, #0x1 +# CHECK: movi.16b v0, #0x1 0x20 0x04 0x00 0x0f 0x20 0x24 0x00 0x0f 0x20 0x44 0x00 0x0f 0x20 0x64 0x00 0x0f -# CHECK: movi.2s v0, #1 -# CHECK: movi.2s v0, #1, lsl #8 -# CHECK: movi.2s v0, #1, lsl #16 -# CHECK: movi.2s v0, #1, lsl #24 +# CHECK: movi.2s v0, #0x1 +# CHECK: movi.2s v0, #0x1, lsl #8 +# CHECK: movi.2s v0, #0x1, lsl #16 +# CHECK: movi.2s v0, #0x1, lsl #24 0x20 0x04 0x00 0x4f 0x20 0x24 0x00 0x4f 0x20 0x44 0x00 0x4f 0x20 0x64 0x00 0x4f -# CHECK: movi.4s v0, #1 -# CHECK: movi.4s v0, #1, lsl #8 -# CHECK: movi.4s v0, #1, lsl #16 -# CHECK: movi.4s v0, #1, lsl #24 +# CHECK: movi.4s v0, #0x1 +# CHECK: movi.4s v0, #0x1, lsl #8 +# CHECK: movi.4s v0, #0x1, lsl #16 +# CHECK: movi.4s v0, #0x1, lsl #24 0x20 0x84 0x00 0x0f 0x20 0xa4 0x00 0x0f -# CHECK: movi.4h v0, #1 -# CHECK: movi.4h v0, #1, lsl #8 +# CHECK: movi.4h v0, #0x1 +# CHECK: movi.4h v0, #0x1, lsl #8 0x20 0x84 0x00 0x4f 0x20 0xa4 0x00 0x4f -# CHECK: movi.8h v0, #1 -# CHECK: movi.8h v0, #1, lsl #8 +# CHECK: movi.8h v0, #0x1 +# CHECK: movi.8h v0, #0x1, lsl #8 0x20 0x04 0x00 0x2f 0x20 0x24 0x00 0x2f 0x20 0x44 0x00 0x2f 0x20 0x64 0x00 0x2f -# CHECK: mvni.2s v0, #1 -# CHECK: mvni.2s v0, #1, lsl #8 -# CHECK: mvni.2s v0, #1, lsl #16 -# CHECK: mvni.2s v0, #1, lsl #24 +# CHECK: mvni.2s v0, #0x1 +# CHECK: mvni.2s v0, #0x1, lsl #8 +# CHECK: mvni.2s v0, #0x1, lsl #16 +# CHECK: mvni.2s v0, #0x1, lsl #24 0x20 0x04 0x00 0x6f 0x20 0x24 0x00 0x6f 0x20 0x44 0x00 0x6f 0x20 0x64 0x00 0x6f -# CHECK: mvni.4s v0, #1 -# CHECK: mvni.4s v0, #1, lsl #8 -# CHECK: mvni.4s v0, #1, lsl #16 -# CHECK: mvni.4s v0, #1, lsl #24 +# CHECK: mvni.4s v0, #0x1 +# CHECK: mvni.4s v0, #0x1, lsl #8 +# CHECK: mvni.4s v0, #0x1, lsl #16 +# CHECK: mvni.4s v0, #0x1, lsl #24 0x20 0x84 0x00 0x2f 0x20 0xa4 0x00 0x2f -# CHECK: mvni.4h v0, #1 -# CHECK: mvni.4h v0, #1, lsl #8 +# CHECK: mvni.4h v0, #0x1 +# CHECK: mvni.4h v0, #0x1, lsl #8 0x20 0x84 0x00 0x6f 0x20 0xa4 0x00 0x6f -# CHECK: mvni.8h v0, #1 -# CHECK: mvni.8h v0, #1, lsl #8 +# CHECK: mvni.8h v0, #0x1 +# CHECK: mvni.8h v0, #0x1, lsl #8 0x20 0xc4 0x00 0x2f 0x20 0xd4 0x00 0x2f 0x20 0xc4 0x00 0x6f 0x20 0xd4 0x00 0x6f -# CHECK: mvni.2s v0, #1, msl #8 -# CHECK: mvni.2s v0, #1, msl #16 -# CHECK: mvni.4s v0, #1, msl #8 -# CHECK: mvni.4s v0, #1, msl #16 +# CHECK: mvni.2s v0, #0x1, msl #8 +# CHECK: mvni.2s v0, #0x1, msl #16 +# CHECK: mvni.4s v0, #0x1, msl #8 +# CHECK: mvni.4s v0, #0x1, msl #16 0x00 0x88 0x21 0x2e 0x00 0x98 0x21 0x2e diff --git a/test/MC/Disassembler/ARM64/arithmetic.txt b/test/MC/Disassembler/AArch64/arm64-arithmetic.txt index 3981219..bd870ed 100644 --- a/test/MC/Disassembler/ARM64/arithmetic.txt +++ b/test/MC/Disassembler/AArch64/arm64-arithmetic.txt @@ -40,8 +40,8 @@ 0x83 0x00 0x40 0x91 0xff 0x83 0x00 0x91 -# CHECK: add w3, w4, #4194304 -# CHECK: add x3, x4, #4194304 +# CHECK: add w3, w4, #1024, lsl #12 +# CHECK: add x3, x4, #1024, lsl #12 # CHECK: add x3, x4, #0, lsl #12 # CHECK: add sp, sp, #32 @@ -49,11 +49,13 @@ 0x83 0x00 0x50 0x31 0x83 0x00 0x10 0xb1 0x83 0x00 0x50 0xb1 +0xff 0x83 0x00 0xb1 # CHECK: adds w3, w4, #1024 -# CHECK: adds w3, w4, #4194304 +# CHECK: adds w3, w4, #1024, lsl #12 # CHECK: adds x3, x4, #1024 -# CHECK: adds x3, x4, #4194304 +# CHECK: adds x3, x4, #1024, lsl #12 +# CHECK: cmn sp, #32 0x83 0x00 0x10 0x51 0x83 0x00 0x50 0x51 @@ -62,20 +64,22 @@ 0xff 0x83 0x00 0xd1 # CHECK: sub w3, w4, #1024 -# CHECK: sub w3, w4, #4194304 +# CHECK: sub w3, w4, #1024, lsl #12 # CHECK: sub x3, x4, #1024 -# CHECK: sub x3, x4, #4194304 +# CHECK: sub x3, x4, #1024, lsl #12 # CHECK: sub sp, sp, #32 0x83 0x00 0x10 0x71 0x83 0x00 0x50 0x71 0x83 0x00 0x10 0xf1 0x83 0x00 0x50 0xf1 +0xff 0x83 0x00 0xf1 # CHECK: subs w3, w4, #1024 -# CHECK: subs w3, w4, #4194304 +# CHECK: subs w3, w4, #1024, lsl #12 # CHECK: subs x3, x4, #1024 -# CHECK: subs x3, x4, #4194304 +# CHECK: subs x3, x4, #1024, lsl #12 +# CHECK: cmp sp, #32 #==---------------------------------------------------------------------------== # Add/Subtract register with (optional) shift @@ -85,72 +89,72 @@ 0xac 0x01 0x0e 0x8b 0xac 0x31 0x0e 0x0b 0xac 0x31 0x0e 0x8b -0xac 0xa9 0x4e 0x0b -0xac 0xa9 0x4e 0x8b -0xac 0x9d 0x8e 0x0b +0xac 0x29 0x4e 0x0b +0xac 0x29 0x4e 0x8b +0xac 0x1d 0x8e 0x0b 0xac 0x9d 0x8e 0x8b # CHECK: add w12, w13, w14 # CHECK: add x12, x13, x14 # CHECK: add w12, w13, w14, lsl #12 # CHECK: add x12, x13, x14, lsl #12 -# CHECK: add w12, w13, w14, lsr #42 -# CHECK: add x12, x13, x14, lsr #42 -# CHECK: add w12, w13, w14, asr #39 +# CHECK: add w12, w13, w14, lsr #10 +# CHECK: add x12, x13, x14, lsr #10 +# CHECK: add w12, w13, w14, asr #7 # CHECK: add x12, x13, x14, asr #39 0xac 0x01 0x0e 0x4b 0xac 0x01 0x0e 0xcb 0xac 0x31 0x0e 0x4b 0xac 0x31 0x0e 0xcb -0xac 0xa9 0x4e 0x4b -0xac 0xa9 0x4e 0xcb -0xac 0x9d 0x8e 0x4b +0xac 0x29 0x4e 0x4b +0xac 0x29 0x4e 0xcb +0xac 0x1d 0x8e 0x4b 0xac 0x9d 0x8e 0xcb # CHECK: sub w12, w13, w14 # CHECK: sub x12, x13, x14 # CHECK: sub w12, w13, w14, lsl #12 # CHECK: sub x12, x13, x14, lsl #12 -# CHECK: sub w12, w13, w14, lsr #42 -# CHECK: sub x12, x13, x14, lsr #42 -# CHECK: sub w12, w13, w14, asr #39 +# CHECK: sub w12, w13, w14, lsr #10 +# CHECK: sub x12, x13, x14, lsr #10 +# CHECK: sub w12, w13, w14, asr #7 # CHECK: sub x12, x13, x14, asr #39 0xac 0x01 0x0e 0x2b 0xac 0x01 0x0e 0xab 0xac 0x31 0x0e 0x2b 0xac 0x31 0x0e 0xab -0xac 0xa9 0x4e 0x2b -0xac 0xa9 0x4e 0xab -0xac 0x9d 0x8e 0x2b +0xac 0x29 0x4e 0x2b +0xac 0x29 0x4e 0xab +0xac 0x1d 0x8e 0x2b 0xac 0x9d 0x8e 0xab # CHECK: adds w12, w13, w14 # CHECK: adds x12, x13, x14 # CHECK: adds w12, w13, w14, lsl #12 # CHECK: adds x12, x13, x14, lsl #12 -# CHECK: adds w12, w13, w14, lsr #42 -# CHECK: adds x12, x13, x14, lsr #42 -# CHECK: adds w12, w13, w14, asr #39 +# CHECK: adds w12, w13, w14, lsr #10 +# CHECK: adds x12, x13, x14, lsr #10 +# CHECK: adds w12, w13, w14, asr #7 # CHECK: adds x12, x13, x14, asr #39 0xac 0x01 0x0e 0x6b 0xac 0x01 0x0e 0xeb 0xac 0x31 0x0e 0x6b 0xac 0x31 0x0e 0xeb -0xac 0xa9 0x4e 0x6b -0xac 0xa9 0x4e 0xeb -0xac 0x9d 0x8e 0x6b +0xac 0x29 0x4e 0x6b +0xac 0x29 0x4e 0xeb +0xac 0x1d 0x8e 0x6b 0xac 0x9d 0x8e 0xeb # CHECK: subs w12, w13, w14 # CHECK: subs x12, x13, x14 # CHECK: subs w12, w13, w14, lsl #12 # CHECK: subs x12, x13, x14, lsl #12 -# CHECK: subs w12, w13, w14, lsr #42 -# CHECK: subs x12, x13, x14, lsr #42 -# CHECK: subs w12, w13, w14, asr #39 +# CHECK: subs w12, w13, w14, lsr #10 +# CHECK: subs x12, x13, x14, lsr #10 +# CHECK: subs w12, w13, w14, asr #7 # CHECK: subs x12, x13, x14, asr #39 #==---------------------------------------------------------------------------== @@ -168,7 +172,7 @@ # CHECK: add w1, w2, w3, uxtb # CHECK: add w1, w2, w3, uxth -# CHECK: add w1, w2, w3, uxtw +# CHECK: add w1, w2, w3 # CHECK: add w1, w2, w3, uxtx # CHECK: add w1, w2, w3, sxtb # CHECK: add w1, w2, w3, sxth @@ -210,7 +214,7 @@ # CHECK: sub w1, w2, w3, uxtb # CHECK: sub w1, w2, w3, uxth -# CHECK: sub w1, w2, w3, uxtw +# CHECK: sub w1, w2, w3 # CHECK: sub w1, w2, w3, uxtx # CHECK: sub w1, w2, w3, sxtb # CHECK: sub w1, w2, w3, sxth @@ -252,7 +256,7 @@ # CHECK: adds w1, w2, w3, uxtb # CHECK: adds w1, w2, w3, uxth -# CHECK: adds w1, w2, w3, uxtw +# CHECK: adds w1, w2, w3 # CHECK: adds w1, w2, w3, uxtx # CHECK: adds w1, w2, w3, sxtb # CHECK: adds w1, w2, w3, sxth @@ -290,7 +294,7 @@ # CHECK: subs w1, w2, w3, uxtb # CHECK: subs w1, w2, w3, uxth -# CHECK: subs w1, w2, w3, uxtw +# CHECK: subs w1, w2, w3 # CHECK: subs w1, w2, w3, uxtx # CHECK: subs w1, w2, w3, sxtb # CHECK: subs w1, w2, w3, sxth @@ -364,21 +368,21 @@ #==---------------------------------------------------------------------------== 0x41 0x28 0xc3 0x1a -# CHECK: asrv w1, w2, w3 +# CHECK: asr w1, w2, w3 0x41 0x28 0xc3 0x9a -# CHECK: asrv x1, x2, x3 +# CHECK: asr x1, x2, x3 0x41 0x20 0xc3 0x1a -# CHECK: lslv w1, w2, w3 +# CHECK: lsl w1, w2, w3 0x41 0x20 0xc3 0x9a -# CHECK: lslv x1, x2, x3 +# CHECK: lsl x1, x2, x3 0x41 0x24 0xc3 0x1a -# CHECK: lsrv w1, w2, w3 +# CHECK: lsr w1, w2, w3 0x41 0x24 0xc3 0x9a -# CHECK: lsrv x1, x2, x3 +# CHECK: lsr x1, x2, x3 0x41 0x2c 0xc3 0x1a -# CHECK: rorv w1, w2, w3 +# CHECK: ror w1, w2, w3 0x41 0x2c 0xc3 0x9a -# CHECK: rorv x1, x2, x3 +# CHECK: ror x1, x2, x3 #==---------------------------------------------------------------------------== # One operand instructions @@ -448,30 +452,30 @@ 0x20 0x00 0xa0 0x52 0x20 0x00 0xa0 0xd2 -# CHECK: movz w0, #1 -# CHECK: movz x0, #1 -# CHECK: movz w0, #1, lsl #16 -# CHECK: movz x0, #1, lsl #16 +# CHECK: movz w0, #0x1 +# CHECK: movz x0, #0x1 +# CHECK: movz w0, #0x1, lsl #16 +# CHECK: movz x0, #0x1, lsl #16 0x40 0x00 0x80 0x12 0x40 0x00 0x80 0x92 0x40 0x00 0xa0 0x12 0x40 0x00 0xa0 0x92 -# CHECK: movn w0, #2 -# CHECK: movn x0, #2 -# CHECK: movn w0, #2, lsl #16 -# CHECK: movn x0, #2, lsl #16 +# CHECK: movn w0, #0x2 +# CHECK: movn x0, #0x2 +# CHECK: movn w0, #0x2, lsl #16 +# CHECK: movn x0, #0x2, lsl #16 0x20 0x00 0x80 0x72 0x20 0x00 0x80 0xf2 0x20 0x00 0xa0 0x72 0x20 0x00 0xa0 0xf2 -# CHECK: movk w0, #1 -# CHECK: movk x0, #1 -# CHECK: movk w0, #1, lsl #16 -# CHECK: movk x0, #1, lsl #16 +# CHECK: movk w0, #0x1 +# CHECK: movk x0, #0x1 +# CHECK: movk w0, #0x1, lsl #16 +# CHECK: movk x0, #0x1, lsl #16 #==---------------------------------------------------------------------------== # Conditionally set flags instructions diff --git a/test/MC/Disassembler/AArch64/arm64-basic-a64-undefined.txt b/test/MC/Disassembler/AArch64/arm64-basic-a64-undefined.txt new file mode 100644 index 0000000..0e15af6 --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-basic-a64-undefined.txt @@ -0,0 +1,31 @@ +# These spawn another process so they're rather expensive. Not many. + +# LDR/STR: undefined if option field is 10x or 00x. +# RUN: echo "0x00 0x08 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x88 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s + +# Instructions notionally in the add/sub (extended register) sheet, but with +# invalid shift amount or "opt" field. +# RUN: echo "0x00 0x10 0xa0 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x10 0x60 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x14 0x20 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# MOVK with sf == 0 and hw<1> == 1 is unallocated. +# RUN: echo "0x00 0x00 0xc0 0x72" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'. +# RUN: echo "0x00 0x00 0xc0 0xeb" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x80 0x80 0x6b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# UBFM is undefined when s == 0 and imms<5> or immr<5> is 1. +# RUN: echo "0x00 0x80 0x00 0x53" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# EXT on vectors of i8 must have imm<3> = 0. +# RUN: echo "0x00 0x40 0x00 0x2e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# SCVTF on fixed point W-registers is undefined if scale<5> == 0. +# Same with FCVTZS and FCVTZU. +# RUN: echo "0x00 0x00 0x02 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s +# RUN: echo "0x00 0x00 0x18 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s + +# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM64/bitfield.txt b/test/MC/Disassembler/AArch64/arm64-bitfield.txt index 99e7af1..d620cb3 100644 --- a/test/MC/Disassembler/ARM64/bitfield.txt +++ b/test/MC/Disassembler/AArch64/arm64-bitfield.txt @@ -11,12 +11,12 @@ 0x41 0x3c 0x01 0x53 0x41 0x3c 0x41 0xd3 -# CHECK: bfm w1, w2, #1, #15 -# CHECK: bfm x1, x2, #1, #15 -# CHECK: sbfm w1, w2, #1, #15 -# CHECK: sbfm x1, x2, #1, #15 -# CHECK: ubfm w1, w2, #1, #15 -# CHECK: ubfm x1, x2, #1, #15 +# CHECK: bfxil w1, w2, #1, #15 +# CHECK: bfxil x1, x2, #1, #15 +# CHECK: sbfx w1, w2, #1, #15 +# CHECK: sbfx x1, x2, #1, #15 +# CHECK: ubfx w1, w2, #1, #15 +# CHECK: ubfx x1, x2, #1, #15 #==---------------------------------------------------------------------------== # 5.4.5 Extract (immediate) diff --git a/test/MC/Disassembler/ARM64/branch.txt b/test/MC/Disassembler/AArch64/arm64-branch.txt index c5b254b..6af1ad8 100644 --- a/test/MC/Disassembler/ARM64/branch.txt +++ b/test/MC/Disassembler/AArch64/arm64-branch.txt @@ -24,21 +24,21 @@ #----------------------------------------------------------------------------- 0x20 0x00 0x20 0xd4 -# CHECK: brk #1 +# CHECK: brk #0x1 0x41 0x00 0xa0 0xd4 -# CHECK: dcps1 #2 +# CHECK: dcps1 #0x2 0x62 0x00 0xa0 0xd4 -# CHECK: dcps2 #3 +# CHECK: dcps2 #0x3 0x83 0x00 0xa0 0xd4 -# CHECK: dcps3 #4 +# CHECK: dcps3 #0x4 0xa0 0x00 0x40 0xd4 -# CHECK: hlt #5 +# CHECK: hlt #0x5 0xc2 0x00 0x00 0xd4 -# CHECK: hvc #6 +# CHECK: hvc #0x6 0xe3 0x00 0x00 0xd4 -# CHECK: smc #7 +# CHECK: smc #0x7 0x01 0x01 0x00 0xd4 -# CHECK: svc #8 +# CHECK: svc #0x8 #----------------------------------------------------------------------------- # PC-relative branches (both positive and negative displacement) diff --git a/test/MC/Disassembler/AArch64/arm64-canonical-form.txt b/test/MC/Disassembler/AArch64/arm64-canonical-form.txt new file mode 100644 index 0000000..1c94b13 --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-canonical-form.txt @@ -0,0 +1,21 @@ +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon --disassemble < %s | FileCheck %s + +0x00 0x08 0x00 0xc8 + +# CHECK: stxr w0, x0, [x0] + +0x00 0x00 0x40 0x9b + +# CHECK: smulh x0, x0, x0 + +0x08 0x20 0x21 0x1e + +# CHECK: fcmp s0, #0.0 + +0x1f 0x00 0x00 0x11 + +# CHECK: mov wsp, w0 + +0x00 0x7c 0x00 0x13 + +# CHECK: asr w0, w0, #0 diff --git a/test/MC/Disassembler/ARM64/crc32.txt b/test/MC/Disassembler/AArch64/arm64-crc32.txt index ef0a26e..51717ee 100644 --- a/test/MC/Disassembler/ARM64/crc32.txt +++ b/test/MC/Disassembler/AArch64/arm64-crc32.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=arm64 -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+crc -disassemble < %s | FileCheck %s # CHECK: crc32b w5, w7, w20 # CHECK: crc32h w28, wzr, w30 diff --git a/test/MC/Disassembler/ARM64/crypto.txt b/test/MC/Disassembler/AArch64/arm64-crypto.txt index e163b2c..b905b92 100644 --- a/test/MC/Disassembler/ARM64/crypto.txt +++ b/test/MC/Disassembler/AArch64/arm64-crypto.txt @@ -1,5 +1,5 @@ -# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s -# RUN: llvm-mc -triple arm64-apple-darwin -output-asm-variant=1 --disassemble < %s | FileCheck %s --check-prefix=CHECK-APPLE +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 --disassemble < %s | FileCheck %s --check-prefix=CHECK-APPLE 0x20 0x48 0x28 0x4e 0x20 0x58 0x28 0x4e diff --git a/test/MC/Disassembler/ARM64/invalid-logical.txt b/test/MC/Disassembler/AArch64/arm64-invalid-logical.txt index 8a4ecb6..8a4ecb6 100644 --- a/test/MC/Disassembler/ARM64/invalid-logical.txt +++ b/test/MC/Disassembler/AArch64/arm64-invalid-logical.txt diff --git a/test/MC/Disassembler/ARM64/logical.txt b/test/MC/Disassembler/AArch64/arm64-logical.txt index 29db8cb..e3cb3eb 100644 --- a/test/MC/Disassembler/ARM64/logical.txt +++ b/test/MC/Disassembler/AArch64/arm64-logical.txt @@ -13,6 +13,7 @@ 0x00 0x00 0x40 0xf2 0x41 0x0c 0x00 0x72 0x41 0x0c 0x40 0xf2 +0x5f 0x0c 0x40 0xf2 # CHECK: and w0, w0, #0x1 # CHECK: and x0, x0, #0x1 @@ -23,18 +24,23 @@ # CHECK: ands x0, x0, #0x1 # CHECK: ands w1, w2, #0xf # CHECK: ands x1, x2, #0xf +# CHECK: tst x2, #0xf 0x41 0x00 0x12 0x52 0x41 0x00 0x71 0xd2 +0x5f 0x00 0x71 0xd2 # CHECK: eor w1, w2, #0x4000 # CHECK: eor x1, x2, #0x8000 +# CHECK: eor sp, x2, #0x8000 0x41 0x00 0x12 0x32 0x41 0x00 0x71 0xb2 +0x5f 0x00 0x71 0xb2 # CHECK: orr w1, w2, #0x4000 # CHECK: orr x1, x2, #0x8000 +# CHECK: orr sp, x2, #0x8000 #==---------------------------------------------------------------------------== # 5.5.3 Logical (shifted register) diff --git a/test/MC/Disassembler/ARM64/memory.txt b/test/MC/Disassembler/AArch64/arm64-memory.txt index 031bfa6..54556a1 100644 --- a/test/MC/Disassembler/ARM64/memory.txt +++ b/test/MC/Disassembler/AArch64/arm64-memory.txt @@ -83,6 +83,8 @@ 0x64 0x00 0x00 0x39 0x85 0x50 0x00 0x39 0xe2 0x43 0x00 0x79 + 0x00 0xe8 0x20 0x38 + 0x00 0x48 0x20 0x38 # CHECK: str x4, [x3] # CHECK: str x2, [sp, #32] @@ -95,6 +97,8 @@ # CHECK: strb w4, [x3] # CHECK: strb w5, [x4, #20] # CHECK: strh w2, [sp, #32] +# CHECK: strb w0, [x0, x0, sxtx] +# CHECK: strb w0, [x0, w0, uxtw] #----------------------------------------------------------------------------- # Unscaled immediate loads and stores @@ -210,8 +214,8 @@ 0x08 0x8c 0x40 0xfc 0x09 0x0c 0xc1 0x3c -# CHECK: ldr fp, [x7, #8]! -# CHECK: ldr lr, [x7, #8]! +# CHECK: ldr x29, [x7, #8]! +# CHECK: ldr x30, [x7, #8]! # CHECK: ldr b5, [x0, #1]! # CHECK: ldr h6, [x0, #2]! # CHECK: ldr s7, [x0, #4]! @@ -226,8 +230,8 @@ 0x08 0x8c 0x1f 0xfc 0x09 0x0c 0x9f 0x3c -# CHECK: str lr, [x7, #-8]! -# CHECK: str fp, [x7, #-8]! +# CHECK: str x30, [x7, #-8]! +# CHECK: str x29, [x7, #-8]! # CHECK: str b5, [x0, #-1]! # CHECK: str h6, [x0, #-2]! # CHECK: str s7, [x0, #-4]! @@ -246,8 +250,8 @@ 0x08 0x84 0x1f 0xfc 0x09 0x04 0x9f 0x3c -# CHECK: str lr, [x7], #-8 -# CHECK: str fp, [x7], #-8 +# CHECK: str x30, [x7], #-8 +# CHECK: str x29, [x7], #-8 # CHECK: str b5, [x0], #-1 # CHECK: str h6, [x0], #-2 # CHECK: str s7, [x0], #-4 @@ -262,8 +266,8 @@ 0x08 0x84 0x40 0xfc 0x09 0x04 0xc1 0x3c -# CHECK: ldr fp, [x7], #8 -# CHECK: ldr lr, [x7], #8 +# CHECK: ldr x29, [x7], #8 +# CHECK: ldr x30, [x7], #8 # CHECK: ldr b5, [x0], #1 # CHECK: ldr h6, [x0], #2 # CHECK: ldr s7, [x0], #4 @@ -416,15 +420,17 @@ # CHECK: ldr q1, [x1, x2] # CHECK: ldr q1, [x1, x2, lsl #4] + 0x00 0x48 0x20 0x7c 0xe1 0x6b 0x23 0xfc 0xe1 0x5b 0x23 0xfc 0xe1 0x6b 0xa3 0x3c 0xe1 0x5b 0xa3 0x3c +# CHECK: str h0, [x0, w0, uxtw] # CHECK: str d1, [sp, x3] -# CHECK: str d1, [sp, x3, uxtw #3] +# CHECK: str d1, [sp, w3, uxtw #3] # CHECK: str q1, [sp, x3] -# CHECK: str q1, [sp, x3, uxtw #4] +# CHECK: str q1, [sp, w3, uxtw #4] #----------------------------------------------------------------------------- # Load/Store exclusive diff --git a/test/MC/Disassembler/AArch64/arm64-non-apple-fmov.txt b/test/MC/Disassembler/AArch64/arm64-non-apple-fmov.txt new file mode 100644 index 0000000..75cb95c --- /dev/null +++ b/test/MC/Disassembler/AArch64/arm64-non-apple-fmov.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc -triple arm64 -mattr=neon -disassemble < %s | FileCheck %s + +0x00 0x00 0xae 0x9e +0x00 0x00 0xaf 0x9e + +# CHECK: fmov x0, v0.d[1] +# CHECK: fmov v0.d[1], x0 diff --git a/test/MC/Disassembler/ARM64/scalar-fp.txt b/test/MC/Disassembler/AArch64/arm64-scalar-fp.txt index b242df5..f139700 100644 --- a/test/MC/Disassembler/ARM64/scalar-fp.txt +++ b/test/MC/Disassembler/AArch64/arm64-scalar-fp.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon --disassemble -output-asm-variant=1 < %s | FileCheck %s #----------------------------------------------------------------------------- # Floating-point arithmetic @@ -184,10 +184,10 @@ 0x01 0xf0 0x7b 0x1e 0x01 0xf0 0x6b 0x1e -# CHECK: fmov s1, #1.250000e-01 -# CHECK: fmov d1, #1.250000e-01 -# CHECK: fmov d1, #-4.843750e-01 -# CHECK: fmov d1, #4.843750e-01 +# CHECK: fmov s1, #0.12500000 +# CHECK: fmov d1, #0.12500000 +# CHECK: fmov d1, #-0.48437500 +# CHECK: fmov d1, #0.48437500 0x41 0x40 0x20 0x1e 0x41 0x40 0x60 0x1e diff --git a/test/MC/Disassembler/ARM64/system.txt b/test/MC/Disassembler/AArch64/arm64-system.txt index cefa635..9027a60 100644 --- a/test/MC/Disassembler/ARM64/system.txt +++ b/test/MC/Disassembler/AArch64/arm64-system.txt @@ -26,10 +26,14 @@ # CHECK: clrex #10 0xdf 0x3f 0x03 0xd5 # CHECK: isb{{$}} + 0xdf 0x31 0x03 0xd5 +# CHECK: isb #1 0xbf 0x33 0x03 0xd5 # CHECK: dmb osh 0x9f 0x37 0x03 0xd5 # CHECK: dsb nsh + 0x3f 0x76 0x08 0xd5 +# CHECK: dc ivac #----------------------------------------------------------------------------- # Generic system instructions @@ -38,19 +42,19 @@ 0xe7 0x6a 0x0f 0xd5 0xf4 0x3f 0x2e 0xd5 0xbf 0x40 0x00 0xd5 - 0x00 0x00 0x10 0xd5 - 0x00 0x00 0x30 0xd5 + 0x00 0xb0 0x18 0xd5 + 0x00 0xb0 0x38 0xd5 # CHECK: sys #2, c0, c5, #7 # CHECK: sys #7, c6, c10, #7, x7 # CHECK: sysl x20, #6, c3, c15, #7 -# CHECK: msr SPSel, #0 -# CHECK: msr S2_0_C0_C0_0, x0 -# CHECK: mrs x0, S2_0_C0_C0_0 +# CHECK: msr SPSEL, #0 +# CHECK: msr S3_0_C11_C0_0, x0 +# CHECK: mrs x0, S3_0_C11_C0_0 0x40 0xc0 0x1e 0xd5 - 0x40 0xc0 0x1a 0xd5 - 0x40 0xc0 0x19 0xd5 + 0x40 0xc0 0x1c 0xd5 + 0x40 0xc0 0x18 0xd5 # CHECK: msr RMR_EL3, x0 # CHECK: msr RMR_EL2, x0 diff --git a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt index 40926b1..397a39e 100644 --- a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # Add/sub (immediate) @@ -187,7 +188,7 @@ # CHECK: sub w3, w5, w7 # CHECK: sub wzr, w3, w5 -# CHECK: sub w20, wzr, w4 +# CHECK: {{sub w20, wzr, w4|neg w20, w4}} # CHECK: sub w4, w6, wzr # CHECK: sub w11, w13, w15 # CHECK: sub w9, w3, wzr, lsl #10 @@ -214,7 +215,7 @@ # CHECK: sub x3, x5, x7 # CHECK: sub xzr, x3, x5 -# CHECK: sub x20, xzr, x4 +# CHECK: {{sub x20, xzr, x4|neg x20, x4}} # CHECK: sub x4, x6, xzr # CHECK: sub x11, x13, x15 # CHECK: sub x9, x3, xzr, lsl #10 @@ -241,7 +242,7 @@ # CHECK: subs w3, w5, w7 # CHECK: cmp w3, w5 -# CHECK: subs w20, wzr, w4 +# CHECK: {{subs w20, wzr, w4|negs w20, w4}} # CHECK: subs w4, w6, wzr # CHECK: subs w11, w13, w15 # CHECK: subs w9, w3, wzr, lsl #10 @@ -268,7 +269,7 @@ # CHECK: subs x3, x5, x7 # CHECK: cmp x3, x5 -# CHECK: subs x20, xzr, x4 +# CHECK: {{subs x20, xzr, x4|negs x20, x4}} # CHECK: subs x4, x6, xzr # CHECK: subs x11, x13, x15 # CHECK: subs x9, x3, xzr, lsl #10 @@ -393,18 +394,18 @@ 0x9f 0xde 0x95 0xeb 0xdf 0xfe 0x97 0xeb -# CHECK: sub w29, wzr, w30 -# CHECK: sub w30, wzr, wzr -# CHECK: sub wzr, wzr, w0 -# CHECK: sub w28, wzr, w27 -# CHECK: sub w26, wzr, w25, lsl #29 -# CHECK: sub w24, wzr, w23, lsl #31 -# CHECK: sub w22, wzr, w21, lsr #0 -# CHECK: sub w20, wzr, w19, lsr #1 -# CHECK: sub w18, wzr, w17, lsr #31 -# CHECK: sub w16, wzr, w15, asr #0 -# CHECK: sub w14, wzr, w13, asr #12 -# CHECK: sub w12, wzr, w11, asr #31 +# CHECK: {{sub w29, wzr|neg w29}}, w30 +# CHECK: {{sub w30, wzr|neg w30}}, wzr +# CHECK: {{sub wzr, wzr|neg wzr}}, w0 +# CHECK: {{sub w28, wzr|neg w28}}, w27 +# CHECK: {{sub w26, wzr|neg w26}}, w25, lsl #29 +# CHECK: {{sub w24, wzr|neg w24}}, w23, lsl #31 +# CHECK: {{sub w22, wzr|neg w22}}, w21, lsr #0 +# CHECK: {{sub w20, wzr|neg w20}}, w19, lsr #1 +# CHECK: {{sub w18, wzr|neg w18}}, w17, lsr #31 +# CHECK: {{sub w16, wzr|neg w16}}, w15, asr #0 +# CHECK: {{sub w14, wzr|neg w14}}, w13, asr #12 +# CHECK: {{sub w12, wzr|neg w12}}, w11, asr #31 0xfd 0x3 0x1e 0x4b 0xfe 0x3 0x1f 0x4b 0xff 0x3 0x0 0x4b @@ -418,18 +419,18 @@ 0xee 0x33 0x8d 0x4b 0xec 0x7f 0x8b 0x4b -# CHECK: sub x29, xzr, x30 -# CHECK: sub x30, xzr, xzr -# CHECK: sub xzr, xzr, x0 -# CHECK: sub x28, xzr, x27 -# CHECK: sub x26, xzr, x25, lsl #29 -# CHECK: sub x24, xzr, x23, lsl #31 -# CHECK: sub x22, xzr, x21, lsr #0 -# CHECK: sub x20, xzr, x19, lsr #1 -# CHECK: sub x18, xzr, x17, lsr #31 -# CHECK: sub x16, xzr, x15, asr #0 -# CHECK: sub x14, xzr, x13, asr #12 -# CHECK: sub x12, xzr, x11, asr #31 +# CHECK: {{sub x29, xzr|neg x29}}, x30 +# CHECK: {{sub x30, xzr|neg x30}}, xzr +# CHECK: {{sub xzr, xzr|neg xzr}}, x0 +# CHECK: {{sub x28, xzr|neg x28}}, x27 +# CHECK: {{sub x26, xzr|neg x26}}, x25, lsl #29 +# CHECK: {{sub x24, xzr|neg x24}}, x23, lsl #31 +# CHECK: {{sub x22, xzr|neg x22}}, x21, lsr #0 +# CHECK: {{sub x20, xzr|neg x20}}, x19, lsr #1 +# CHECK: {{sub x18, xzr|neg x18}}, x17, lsr #31 +# CHECK: {{sub x16, xzr|neg x16}}, x15, asr #0 +# CHECK: {{sub x14, xzr|neg x14}}, x13, asr #12 +# CHECK: {{sub x12, xzr|neg x12}}, x11, asr #31 0xfd 0x3 0x1e 0xcb 0xfe 0x3 0x1f 0xcb 0xff 0x3 0x0 0xcb @@ -443,18 +444,18 @@ 0xee 0x33 0x8d 0xcb 0xec 0x7f 0x8b 0xcb -# CHECK: subs w29, wzr, w30 -# CHECK: subs w30, wzr, wzr +# CHECK: {{subs w29, wzr|negs w29}}, w30 +# CHECK: {{subs w30, wzr|negs w30}}, wzr # CHECK: cmp wzr, w0 -# CHECK: subs w28, wzr, w27 -# CHECK: subs w26, wzr, w25, lsl #29 -# CHECK: subs w24, wzr, w23, lsl #31 -# CHECK: subs w22, wzr, w21, lsr #0 -# CHECK: subs w20, wzr, w19, lsr #1 -# CHECK: subs w18, wzr, w17, lsr #31 -# CHECK: subs w16, wzr, w15, asr #0 -# CHECK: subs w14, wzr, w13, asr #12 -# CHECK: subs w12, wzr, w11, asr #31 +# CHECK: {{subs w28, wzr|negs w28}}, w27 +# CHECK: {{subs w26, wzr|negs w26}}, w25, lsl #29 +# CHECK: {{subs w24, wzr|negs w24}}, w23, lsl #31 +# CHECK: {{subs w22, wzr|negs w22}}, w21, lsr #0 +# CHECK: {{subs w20, wzr|negs w20}}, w19, lsr #1 +# CHECK: {{subs w18, wzr|negs w18}}, w17, lsr #31 +# CHECK: {{subs w16, wzr|negs w16}}, w15, asr #0 +# CHECK: {{subs w14, wzr|negs w14}}, w13, asr #12 +# CHECK: {{subs w12, wzr|negs w12}}, w11, asr #31 0xfd 0x3 0x1e 0x6b 0xfe 0x3 0x1f 0x6b 0xff 0x3 0x0 0x6b @@ -468,18 +469,18 @@ 0xee 0x33 0x8d 0x6b 0xec 0x7f 0x8b 0x6b -# CHECK: subs x29, xzr, x30 -# CHECK: subs x30, xzr, xzr +# CHECK: {{subs x29, xzr|negs x29}}, x30 +# CHECK: {{subs x30, xzr|negs x30}}, xzr # CHECK: cmp xzr, x0 -# CHECK: subs x28, xzr, x27 -# CHECK: subs x26, xzr, x25, lsl #29 -# CHECK: subs x24, xzr, x23, lsl #31 -# CHECK: subs x22, xzr, x21, lsr #0 -# CHECK: subs x20, xzr, x19, lsr #1 -# CHECK: subs x18, xzr, x17, lsr #31 -# CHECK: subs x16, xzr, x15, asr #0 -# CHECK: subs x14, xzr, x13, asr #12 -# CHECK: subs x12, xzr, x11, asr #31 +# CHECK: {{subs x28, xzr|negs x28}}, x27 +# CHECK: {{subs x26, xzr|negs x26}}, x25, lsl #29 +# CHECK: {{subs x24, xzr|negs x24}}, x23, lsl #31 +# CHECK: {{subs x22, xzr|negs x22}}, x21, lsr #0 +# CHECK: {{subs x20, xzr|negs x20}}, x19, lsr #1 +# CHECK: {{subs x18, xzr|negs x18}}, x17, lsr #31 +# CHECK: {{subs x16, xzr|negs x16}}, x15, asr #0 +# CHECK: {{subs x14, xzr|negs x14}}, x13, asr #12 +# CHECK: {{subs x12, xzr|negs x12}}, x11, asr #31 0xfd 0x3 0x1e 0xeb 0xfe 0x3 0x1f 0xeb 0xff 0x3 0x0 0xeb @@ -940,21 +941,21 @@ 0xe5 0x27 0x86 0xda 0x7 0x35 0x9f 0xda -# CHECK: csinc w3, wzr, wzr, ne -# CHECK: csinc x9, xzr, xzr, mi -# CHECK: csinv w20, wzr, wzr, eq -# CHECK: csinv x30, xzr, xzr, lt +# CHECK: cset w3, eq +# CHECK: cset x9, pl +# CHECK: csetm w20, ne +# CHECK: csetm x30, ge 0xe3 0x17 0x9f 0x1a 0xe9 0x47 0x9f 0x9a 0xf4 0x3 0x9f 0x5a 0xfe 0xb3 0x9f 0xda -# CHECK: csinc w3, w5, w5, le -# CHECK: csinc wzr, w4, w4, gt -# CHECK: csinc w9, wzr, wzr, ge -# CHECK: csinc x3, x5, x5, le -# CHECK: csinc xzr, x4, x4, gt -# CHECK: csinc x9, xzr, xzr, ge +# CHECK: cinc w3, w5, gt +# CHECK: cinc wzr, w4, le +# CHECK: cset w9, lt +# CHECK: cinc x3, x5, gt +# CHECK: cinc xzr, x4, le +# CHECK: cset x9, lt 0xa3 0xd4 0x85 0x1a 0x9f 0xc4 0x84 0x1a 0xe9 0xa7 0x9f 0x1a @@ -962,12 +963,12 @@ 0x9f 0xc4 0x84 0x9a 0xe9 0xa7 0x9f 0x9a -# CHECK: csinv w3, w5, w5, le -# CHECK: csinv wzr, w4, w4, gt -# CHECK: csinv w9, wzr, wzr, ge -# CHECK: csinv x3, x5, x5, le -# CHECK: csinv xzr, x4, x4, gt -# CHECK: csinv x9, xzr, xzr, ge +# CHECK: cinv w3, w5, gt +# CHECK: cinv wzr, w4, le +# CHECK: csetm w9, lt +# CHECK: cinv x3, x5, gt +# CHECK: cinv xzr, x4, le +# CHECK: csetm x9, lt 0xa3 0xd0 0x85 0x5a 0x9f 0xc0 0x84 0x5a 0xe9 0xa3 0x9f 0x5a @@ -975,12 +976,12 @@ 0x9f 0xc0 0x84 0xda 0xe9 0xa3 0x9f 0xda -# CHECK: csneg w3, w5, w5, le -# CHECK: csneg wzr, w4, w4, gt -# CHECK: csneg w9, wzr, wzr, ge -# CHECK: csneg x3, x5, x5, le -# CHECK: csneg xzr, x4, x4, gt -# CHECK: csneg x9, xzr, xzr, ge +# CHECK: cneg w3, w5, gt +# CHECK: cneg wzr, w4, le +# CHECK: cneg w9, wzr, lt +# CHECK: cneg x3, x5, gt +# CHECK: cneg xzr, x4, le +# CHECK: cneg x9, xzr, lt 0xa3 0xd4 0x85 0x5a 0x9f 0xc4 0x84 0x5a 0xe9 0xa7 0x9f 0x5a @@ -1243,22 +1244,22 @@ #------------------------------------------------------------------------------ # CHECK: svc #0 -# CHECK: svc #65535 +# CHECK: svc #{{65535|0xffff}} 0x1 0x0 0x0 0xd4 0xe1 0xff 0x1f 0xd4 -# CHECK: hvc #1 -# CHECK: smc #12000 -# CHECK: brk #12 -# CHECK: hlt #123 +# CHECK: hvc #{{1|0x1}} +# CHECK: smc #{{12000|0x2ee0}} +# CHECK: brk #{{12|0xc}} +# CHECK: hlt #{{123|0x7b}} 0x22 0x0 0x0 0xd4 0x3 0xdc 0x5 0xd4 0x80 0x1 0x20 0xd4 0x60 0xf 0x40 0xd4 -# CHECK: dcps1 #42 -# CHECK: dcps2 #9 -# CHECK: dcps3 #1000 +# CHECK: dcps1 #{{42|0x2a}} +# CHECK: dcps2 #{{9|0x9}} +# CHECK: dcps3 #{{1000|0x3e8}} 0x41 0x5 0xa0 0xd4 0x22 0x1 0xa0 0xd4 0x3 0x7d 0xa0 0xd4 @@ -1284,9 +1285,9 @@ 0xa3 0x3c 0xc7 0x93 0xab 0xfd 0xd1 0x93 -# CHECK: extr x19, x23, x23, #24 -# CHECK: extr x29, xzr, xzr, #63 -# CHECK: extr w9, w13, w13, #31 +# CHECK: ror x19, x23, #24 +# CHECK: ror x29, xzr, #63 +# CHECK: ror w9, w13, #31 0xf3 0x62 0xd7 0x93 0xfd 0xff 0xdf 0x93 0xa9 0x7d 0x8d 0x13 @@ -2353,23 +2354,23 @@ 0xec 0xff 0xbf 0x3d # CHECK: prfm pldl1keep, [sp, #8] -# CHECK: prfm pldl1strm, [x3, #0] +# CHECK: prfm pldl1strm, [x3{{(, #0)?}}] # CHECK: prfm pldl2keep, [x5, #16] -# CHECK: prfm pldl2strm, [x2, #0] -# CHECK: prfm pldl3keep, [x5, #0] -# CHECK: prfm pldl3strm, [x6, #0] +# CHECK: prfm pldl2strm, [x2{{(, #0)?}}] +# CHECK: prfm pldl3keep, [x5{{(, #0)?}}] +# CHECK: prfm pldl3strm, [x6{{(, #0)?}}] # CHECK: prfm plil1keep, [sp, #8] -# CHECK: prfm plil1strm, [x3, #0] +# CHECK: prfm plil1strm, [x3{{(, #0)?}}] # CHECK: prfm plil2keep, [x5, #16] -# CHECK: prfm plil2strm, [x2, #0] -# CHECK: prfm plil3keep, [x5, #0] -# CHECK: prfm plil3strm, [x6, #0] +# CHECK: prfm plil2strm, [x2{{(, #0)?}}] +# CHECK: prfm plil3keep, [x5{{(, #0)?}}] +# CHECK: prfm plil3strm, [x6{{(, #0)?}}] # CHECK: prfm pstl1keep, [sp, #8] -# CHECK: prfm pstl1strm, [x3, #0] +# CHECK: prfm pstl1strm, [x3{{(, #0)?}}] # CHECK: prfm pstl2keep, [x5, #16] -# CHECK: prfm pstl2strm, [x2, #0] -# CHECK: prfm pstl3keep, [x5, #0] -# CHECK: prfm pstl3strm, [x6, #0] +# CHECK: prfm pstl2strm, [x2{{(, #0)?}}] +# CHECK: prfm pstl3keep, [x5{{(, #0)?}}] +# CHECK: prfm pstl3strm, [x6{{(, #0)?}}] 0xe0 0x07 0x80 0xf9 0x61 0x00 0x80 0xf9 0xa2 0x08 0x80 0xf9 @@ -2722,15 +2723,15 @@ 0xff 0xc7 0x0 0x52 0x30 0xc6 0x1 0x52 -# CHECK: ands wzr, w18, #0xcccccccc +# CHECK: {{ands wzr,|tst}} w18, #0xcccccccc # CHECK: ands w19, w20, #0x33333333 # CHECK: ands w21, w22, #0x99999999 0x5f 0xe6 0x2 0x72 0x93 0xe6 0x0 0x72 0xd5 0xe6 0x1 0x72 -# CHECK: ands wzr, w3, #0xaaaaaaaa -# CHECK: ands wzr, wzr, #0x55555555 +# CHECK: {{ands wzr,|tst}} w3, #0xaaaaaaaa +# CHECK: {{ands wzr,|tst}} wzr, #0x55555555 0x7f 0xf0 0x1 0x72 0xff 0xf3 0x0 0x72 @@ -2762,15 +2763,15 @@ 0xff 0xc7 0x0 0xd2 0x30 0xc6 0x1 0xd2 -# CHECK: ands xzr, x18, #0xcccccccccccccccc +# CHECK: {{ands xzr,|tst}} x18, #0xcccccccccccccccc # CHECK: ands x19, x20, #0x3333333333333333 # CHECK: ands x21, x22, #0x9999999999999999 0x5f 0xe6 0x2 0xf2 0x93 0xe6 0x0 0xf2 0xd5 0xe6 0x1 0xf2 -# CHECK: ands xzr, x3, #0xaaaaaaaaaaaaaaaa -# CHECK: ands xzr, xzr, #0x5555555555555555 +# CHECK: {{ands xzr,|tst}} x3, #0xaaaaaaaaaaaaaaaa +# CHECK: {{ands xzr,|tst}} xzr, #0x5555555555555555 0x7f 0xf0 0x1 0xf2 0xff 0xf3 0x0 0xf2 @@ -2858,15 +2859,15 @@ # limitation in InstAlias. Lots of the "mov[nz]" instructions should # be "mov". -# CHECK: movz w1, #65535 +# CHECK: movz w1, #{{65535|0xffff}} # CHECK: movz w2, #0, lsl #16 -# CHECK: movn w2, #1234 +# CHECK: movn w2, #{{1234|0x4d2}} 0xe1 0xff 0x9f 0x52 0x2 0x0 0xa0 0x52 0x42 0x9a 0x80 0x12 -# CHECK: movz x2, #1234, lsl #32 -# CHECK: movk xzr, #4321, lsl #48 +# CHECK: movz x2, #{{1234|0x4d2}}, lsl #32 +# CHECK: movk xzr, #{{4321|0x10e1}}, lsl #48 0x42 0x9a 0xc0 0xd2 0x3f 0x1c 0xe2 0xf2 @@ -2906,7 +2907,7 @@ #------------------------------------------------------------------------------ # CHECK: nop -# CHECK: hint #127 +# CHECK: hint #{{127|0x7f}} # CHECK: nop # CHECK: yield # CHECK: wfe @@ -2998,9 +2999,9 @@ 0xdf 0x3f 0x3 0xd5 0xdf 0x3c 0x3 0xd5 -# CHECK: msr spsel, #0 -# CHECK: msr daifset, #15 -# CHECK: msr daifclr, #12 +# CHECK: msr {{spsel|SPSEL}}, #0 +# CHECK: msr {{daifset|DAIFSET}}, #15 +# CHECK: msr {{daifclr|DAIFCLR}}, #12 0xbf 0x40 0x0 0xd5 0xdf 0x4f 0x3 0xd5 0xff 0x4c 0x3 0xd5 @@ -3014,21 +3015,21 @@ 0xe9 0x59 0x2f 0xd5 0x41 0xff 0x28 0xd5 -# CHECK: sys #0, c7, c1, #0, xzr -# CHECK: sys #0, c7, c5, #0, xzr -# CHECK: sys #3, c7, c5, #1, x9 +# CHECK: {{sys #0, c7, c1, #0|ic ialluis}} +# CHECK: {{sys #0, c7, c5, #0|ic iallu}} +# CHECK: {{sys #3, c7, c5, #1|ic ivau}}, x9 0x1f 0x71 0x8 0xd5 0x1f 0x75 0x8 0xd5 0x29 0x75 0xb 0xd5 -# CHECK: sys #3, c7, c4, #1, x12 -# CHECK: sys #0, c7, c6, #1, xzr -# CHECK: sys #0, c7, c6, #2, x2 -# CHECK: sys #3, c7, c10, #1, x9 -# CHECK: sys #0, c7, c10, #2, x10 -# CHECK: sys #3, c7, c11, #1, x0 -# CHECK: sys #3, c7, c14, #1, x3 -# CHECK: sys #0, c7, c14, #2, x30 +# CHECK: {{sys #3, c7, c4, #1|dc zva}}, x12 +# CHECK: {{sys #0, c7, c6, #1|dc ivac}} +# CHECK: {{sys #0, c7, c6, #2|dc isw}}, x2 +# CHECK: {{sys #3, c7, c10, #1|dc cvac}}, x9 +# CHECK: {{sys #0, c7, c10, #2|dc csw}}, x10 +# CHECK: {{sys #3, c7, c11, #1|dc cvau}}, x0 +# CHECK: {{sys #3, c7, c14, #1|dc civac}}, x3 +# CHECK: {{sys #0, c7, c14, #2|dc cisw}}, x30 0x2c 0x74 0xb 0xd5 0x3f 0x76 0x8 0xd5 0x42 0x76 0x8 0xd5 @@ -3039,559 +3040,559 @@ 0x5e 0x7e 0x8 0xd5 -# CHECK: msr teecr32_el1, x12 -# CHECK: msr osdtrrx_el1, x12 -# CHECK: msr mdccint_el1, x12 -# CHECK: msr mdscr_el1, x12 -# CHECK: msr osdtrtx_el1, x12 -# CHECK: msr dbgdtr_el0, x12 -# CHECK: msr dbgdtrtx_el0, x12 -# CHECK: msr oseccr_el1, x12 -# CHECK: msr dbgvcr32_el2, x12 -# CHECK: msr dbgbvr0_el1, x12 -# CHECK: msr dbgbvr1_el1, x12 -# CHECK: msr dbgbvr2_el1, x12 -# CHECK: msr dbgbvr3_el1, x12 -# CHECK: msr dbgbvr4_el1, x12 -# CHECK: msr dbgbvr5_el1, x12 -# CHECK: msr dbgbvr6_el1, x12 -# CHECK: msr dbgbvr7_el1, x12 -# CHECK: msr dbgbvr8_el1, x12 -# CHECK: msr dbgbvr9_el1, x12 -# CHECK: msr dbgbvr10_el1, x12 -# CHECK: msr dbgbvr11_el1, x12 -# CHECK: msr dbgbvr12_el1, x12 -# CHECK: msr dbgbvr13_el1, x12 -# CHECK: msr dbgbvr14_el1, x12 -# CHECK: msr dbgbvr15_el1, x12 -# CHECK: msr dbgbcr0_el1, x12 -# CHECK: msr dbgbcr1_el1, x12 -# CHECK: msr dbgbcr2_el1, x12 -# CHECK: msr dbgbcr3_el1, x12 -# CHECK: msr dbgbcr4_el1, x12 -# CHECK: msr dbgbcr5_el1, x12 -# CHECK: msr dbgbcr6_el1, x12 -# CHECK: msr dbgbcr7_el1, x12 -# CHECK: msr dbgbcr8_el1, x12 -# CHECK: msr dbgbcr9_el1, x12 -# CHECK: msr dbgbcr10_el1, x12 -# CHECK: msr dbgbcr11_el1, x12 -# CHECK: msr dbgbcr12_el1, x12 -# CHECK: msr dbgbcr13_el1, x12 -# CHECK: msr dbgbcr14_el1, x12 -# CHECK: msr dbgbcr15_el1, x12 -# CHECK: msr dbgwvr0_el1, x12 -# CHECK: msr dbgwvr1_el1, x12 -# CHECK: msr dbgwvr2_el1, x12 -# CHECK: msr dbgwvr3_el1, x12 -# CHECK: msr dbgwvr4_el1, x12 -# CHECK: msr dbgwvr5_el1, x12 -# CHECK: msr dbgwvr6_el1, x12 -# CHECK: msr dbgwvr7_el1, x12 -# CHECK: msr dbgwvr8_el1, x12 -# CHECK: msr dbgwvr9_el1, x12 -# CHECK: msr dbgwvr10_el1, x12 -# CHECK: msr dbgwvr11_el1, x12 -# CHECK: msr dbgwvr12_el1, x12 -# CHECK: msr dbgwvr13_el1, x12 -# CHECK: msr dbgwvr14_el1, x12 -# CHECK: msr dbgwvr15_el1, x12 -# CHECK: msr dbgwcr0_el1, x12 -# CHECK: msr dbgwcr1_el1, x12 -# CHECK: msr dbgwcr2_el1, x12 -# CHECK: msr dbgwcr3_el1, x12 -# CHECK: msr dbgwcr4_el1, x12 -# CHECK: msr dbgwcr5_el1, x12 -# CHECK: msr dbgwcr6_el1, x12 -# CHECK: msr dbgwcr7_el1, x12 -# CHECK: msr dbgwcr8_el1, x12 -# CHECK: msr dbgwcr9_el1, x12 -# CHECK: msr dbgwcr10_el1, x12 -# CHECK: msr dbgwcr11_el1, x12 -# CHECK: msr dbgwcr12_el1, x12 -# CHECK: msr dbgwcr13_el1, x12 -# CHECK: msr dbgwcr14_el1, x12 -# CHECK: msr dbgwcr15_el1, x12 -# CHECK: msr teehbr32_el1, x12 -# CHECK: msr oslar_el1, x12 -# CHECK: msr osdlr_el1, x12 -# CHECK: msr dbgprcr_el1, x12 -# CHECK: msr dbgclaimset_el1, x12 -# CHECK: msr dbgclaimclr_el1, x12 -# CHECK: msr csselr_el1, x12 -# CHECK: msr vpidr_el2, x12 -# CHECK: msr vmpidr_el2, x12 -# CHECK: msr sctlr_el1, x12 -# CHECK: msr sctlr_el2, x12 -# CHECK: msr sctlr_el3, x12 -# CHECK: msr actlr_el1, x12 -# CHECK: msr actlr_el2, x12 -# CHECK: msr actlr_el3, x12 -# CHECK: msr cpacr_el1, x12 -# CHECK: msr hcr_el2, x12 -# CHECK: msr scr_el3, x12 -# CHECK: msr mdcr_el2, x12 -# CHECK: msr sder32_el3, x12 -# CHECK: msr cptr_el2, x12 -# CHECK: msr cptr_el3, x12 -# CHECK: msr hstr_el2, x12 -# CHECK: msr hacr_el2, x12 -# CHECK: msr mdcr_el3, x12 -# CHECK: msr ttbr0_el1, x12 -# CHECK: msr ttbr0_el2, x12 -# CHECK: msr ttbr0_el3, x12 -# CHECK: msr ttbr1_el1, x12 -# CHECK: msr tcr_el1, x12 -# CHECK: msr tcr_el2, x12 -# CHECK: msr tcr_el3, x12 -# CHECK: msr vttbr_el2, x12 -# CHECK: msr vtcr_el2, x12 -# CHECK: msr dacr32_el2, x12 -# CHECK: msr spsr_el1, x12 -# CHECK: msr spsr_el2, x12 -# CHECK: msr spsr_el3, x12 -# CHECK: msr elr_el1, x12 -# CHECK: msr elr_el2, x12 -# CHECK: msr elr_el3, x12 -# CHECK: msr sp_el0, x12 -# CHECK: msr sp_el1, x12 -# CHECK: msr sp_el2, x12 -# CHECK: msr spsel, x12 -# CHECK: msr nzcv, x12 -# CHECK: msr daif, x12 -# CHECK: msr currentel, x12 -# CHECK: msr spsr_irq, x12 -# CHECK: msr spsr_abt, x12 -# CHECK: msr spsr_und, x12 -# CHECK: msr spsr_fiq, x12 -# CHECK: msr fpcr, x12 -# CHECK: msr fpsr, x12 -# CHECK: msr dspsr_el0, x12 -# CHECK: msr dlr_el0, x12 -# CHECK: msr ifsr32_el2, x12 -# CHECK: msr afsr0_el1, x12 -# CHECK: msr afsr0_el2, x12 -# CHECK: msr afsr0_el3, x12 -# CHECK: msr afsr1_el1, x12 -# CHECK: msr afsr1_el2, x12 -# CHECK: msr afsr1_el3, x12 -# CHECK: msr esr_el1, x12 -# CHECK: msr esr_el2, x12 -# CHECK: msr esr_el3, x12 -# CHECK: msr fpexc32_el2, x12 -# CHECK: msr far_el1, x12 -# CHECK: msr far_el2, x12 -# CHECK: msr far_el3, x12 -# CHECK: msr hpfar_el2, x12 -# CHECK: msr par_el1, x12 -# CHECK: msr pmcr_el0, x12 -# CHECK: msr pmcntenset_el0, x12 -# CHECK: msr pmcntenclr_el0, x12 -# CHECK: msr pmovsclr_el0, x12 -# CHECK: msr pmselr_el0, x12 -# CHECK: msr pmccntr_el0, x12 -# CHECK: msr pmxevtyper_el0, x12 -# CHECK: msr pmxevcntr_el0, x12 -# CHECK: msr pmuserenr_el0, x12 -# CHECK: msr pmintenset_el1, x12 -# CHECK: msr pmintenclr_el1, x12 -# CHECK: msr pmovsset_el0, x12 -# CHECK: msr mair_el1, x12 -# CHECK: msr mair_el2, x12 -# CHECK: msr mair_el3, x12 -# CHECK: msr amair_el1, x12 -# CHECK: msr amair_el2, x12 -# CHECK: msr amair_el3, x12 -# CHECK: msr vbar_el1, x12 -# CHECK: msr vbar_el2, x12 -# CHECK: msr vbar_el3, x12 -# CHECK: msr rmr_el1, x12 -# CHECK: msr rmr_el2, x12 -# CHECK: msr rmr_el3, x12 -# CHECK: msr tpidr_el0, x12 -# CHECK: msr tpidr_el2, x12 -# CHECK: msr tpidr_el3, x12 -# CHECK: msr tpidrro_el0, x12 -# CHECK: msr tpidr_el1, x12 -# CHECK: msr cntfrq_el0, x12 -# CHECK: msr cntvoff_el2, x12 -# CHECK: msr cntkctl_el1, x12 -# CHECK: msr cnthctl_el2, x12 -# CHECK: msr cntp_tval_el0, x12 -# CHECK: msr cnthp_tval_el2, x12 -# CHECK: msr cntps_tval_el1, x12 -# CHECK: msr cntp_ctl_el0, x12 -# CHECK: msr cnthp_ctl_el2, x12 -# CHECK: msr cntps_ctl_el1, x12 -# CHECK: msr cntp_cval_el0, x12 -# CHECK: msr cnthp_cval_el2, x12 -# CHECK: msr cntps_cval_el1, x12 -# CHECK: msr cntv_tval_el0, x12 -# CHECK: msr cntv_ctl_el0, x12 -# CHECK: msr cntv_cval_el0, x12 -# CHECK: msr pmevcntr0_el0, x12 -# CHECK: msr pmevcntr1_el0, x12 -# CHECK: msr pmevcntr2_el0, x12 -# CHECK: msr pmevcntr3_el0, x12 -# CHECK: msr pmevcntr4_el0, x12 -# CHECK: msr pmevcntr5_el0, x12 -# CHECK: msr pmevcntr6_el0, x12 -# CHECK: msr pmevcntr7_el0, x12 -# CHECK: msr pmevcntr8_el0, x12 -# CHECK: msr pmevcntr9_el0, x12 -# CHECK: msr pmevcntr10_el0, x12 -# CHECK: msr pmevcntr11_el0, x12 -# CHECK: msr pmevcntr12_el0, x12 -# CHECK: msr pmevcntr13_el0, x12 -# CHECK: msr pmevcntr14_el0, x12 -# CHECK: msr pmevcntr15_el0, x12 -# CHECK: msr pmevcntr16_el0, x12 -# CHECK: msr pmevcntr17_el0, x12 -# CHECK: msr pmevcntr18_el0, x12 -# CHECK: msr pmevcntr19_el0, x12 -# CHECK: msr pmevcntr20_el0, x12 -# CHECK: msr pmevcntr21_el0, x12 -# CHECK: msr pmevcntr22_el0, x12 -# CHECK: msr pmevcntr23_el0, x12 -# CHECK: msr pmevcntr24_el0, x12 -# CHECK: msr pmevcntr25_el0, x12 -# CHECK: msr pmevcntr26_el0, x12 -# CHECK: msr pmevcntr27_el0, x12 -# CHECK: msr pmevcntr28_el0, x12 -# CHECK: msr pmevcntr29_el0, x12 -# CHECK: msr pmevcntr30_el0, x12 -# CHECK: msr pmccfiltr_el0, x12 -# CHECK: msr pmevtyper0_el0, x12 -# CHECK: msr pmevtyper1_el0, x12 -# CHECK: msr pmevtyper2_el0, x12 -# CHECK: msr pmevtyper3_el0, x12 -# CHECK: msr pmevtyper4_el0, x12 -# CHECK: msr pmevtyper5_el0, x12 -# CHECK: msr pmevtyper6_el0, x12 -# CHECK: msr pmevtyper7_el0, x12 -# CHECK: msr pmevtyper8_el0, x12 -# CHECK: msr pmevtyper9_el0, x12 -# CHECK: msr pmevtyper10_el0, x12 -# CHECK: msr pmevtyper11_el0, x12 -# CHECK: msr pmevtyper12_el0, x12 -# CHECK: msr pmevtyper13_el0, x12 -# CHECK: msr pmevtyper14_el0, x12 -# CHECK: msr pmevtyper15_el0, x12 -# CHECK: msr pmevtyper16_el0, x12 -# CHECK: msr pmevtyper17_el0, x12 -# CHECK: msr pmevtyper18_el0, x12 -# CHECK: msr pmevtyper19_el0, x12 -# CHECK: msr pmevtyper20_el0, x12 -# CHECK: msr pmevtyper21_el0, x12 -# CHECK: msr pmevtyper22_el0, x12 -# CHECK: msr pmevtyper23_el0, x12 -# CHECK: msr pmevtyper24_el0, x12 -# CHECK: msr pmevtyper25_el0, x12 -# CHECK: msr pmevtyper26_el0, x12 -# CHECK: msr pmevtyper27_el0, x12 -# CHECK: msr pmevtyper28_el0, x12 -# CHECK: msr pmevtyper29_el0, x12 -# CHECK: msr pmevtyper30_el0, x12 -# CHECK: mrs x9, teecr32_el1 -# CHECK: mrs x9, osdtrrx_el1 -# CHECK: mrs x9, mdccsr_el0 -# CHECK: mrs x9, mdccint_el1 -# CHECK: mrs x9, mdscr_el1 -# CHECK: mrs x9, osdtrtx_el1 -# CHECK: mrs x9, dbgdtr_el0 -# CHECK: mrs x9, dbgdtrrx_el0 -# CHECK: mrs x9, oseccr_el1 -# CHECK: mrs x9, dbgvcr32_el2 -# CHECK: mrs x9, dbgbvr0_el1 -# CHECK: mrs x9, dbgbvr1_el1 -# CHECK: mrs x9, dbgbvr2_el1 -# CHECK: mrs x9, dbgbvr3_el1 -# CHECK: mrs x9, dbgbvr4_el1 -# CHECK: mrs x9, dbgbvr5_el1 -# CHECK: mrs x9, dbgbvr6_el1 -# CHECK: mrs x9, dbgbvr7_el1 -# CHECK: mrs x9, dbgbvr8_el1 -# CHECK: mrs x9, dbgbvr9_el1 -# CHECK: mrs x9, dbgbvr10_el1 -# CHECK: mrs x9, dbgbvr11_el1 -# CHECK: mrs x9, dbgbvr12_el1 -# CHECK: mrs x9, dbgbvr13_el1 -# CHECK: mrs x9, dbgbvr14_el1 -# CHECK: mrs x9, dbgbvr15_el1 -# CHECK: mrs x9, dbgbcr0_el1 -# CHECK: mrs x9, dbgbcr1_el1 -# CHECK: mrs x9, dbgbcr2_el1 -# CHECK: mrs x9, dbgbcr3_el1 -# CHECK: mrs x9, dbgbcr4_el1 -# CHECK: mrs x9, dbgbcr5_el1 -# CHECK: mrs x9, dbgbcr6_el1 -# CHECK: mrs x9, dbgbcr7_el1 -# CHECK: mrs x9, dbgbcr8_el1 -# CHECK: mrs x9, dbgbcr9_el1 -# CHECK: mrs x9, dbgbcr10_el1 -# CHECK: mrs x9, dbgbcr11_el1 -# CHECK: mrs x9, dbgbcr12_el1 -# CHECK: mrs x9, dbgbcr13_el1 -# CHECK: mrs x9, dbgbcr14_el1 -# CHECK: mrs x9, dbgbcr15_el1 -# CHECK: mrs x9, dbgwvr0_el1 -# CHECK: mrs x9, dbgwvr1_el1 -# CHECK: mrs x9, dbgwvr2_el1 -# CHECK: mrs x9, dbgwvr3_el1 -# CHECK: mrs x9, dbgwvr4_el1 -# CHECK: mrs x9, dbgwvr5_el1 -# CHECK: mrs x9, dbgwvr6_el1 -# CHECK: mrs x9, dbgwvr7_el1 -# CHECK: mrs x9, dbgwvr8_el1 -# CHECK: mrs x9, dbgwvr9_el1 -# CHECK: mrs x9, dbgwvr10_el1 -# CHECK: mrs x9, dbgwvr11_el1 -# CHECK: mrs x9, dbgwvr12_el1 -# CHECK: mrs x9, dbgwvr13_el1 -# CHECK: mrs x9, dbgwvr14_el1 -# CHECK: mrs x9, dbgwvr15_el1 -# CHECK: mrs x9, dbgwcr0_el1 -# CHECK: mrs x9, dbgwcr1_el1 -# CHECK: mrs x9, dbgwcr2_el1 -# CHECK: mrs x9, dbgwcr3_el1 -# CHECK: mrs x9, dbgwcr4_el1 -# CHECK: mrs x9, dbgwcr5_el1 -# CHECK: mrs x9, dbgwcr6_el1 -# CHECK: mrs x9, dbgwcr7_el1 -# CHECK: mrs x9, dbgwcr8_el1 -# CHECK: mrs x9, dbgwcr9_el1 -# CHECK: mrs x9, dbgwcr10_el1 -# CHECK: mrs x9, dbgwcr11_el1 -# CHECK: mrs x9, dbgwcr12_el1 -# CHECK: mrs x9, dbgwcr13_el1 -# CHECK: mrs x9, dbgwcr14_el1 -# CHECK: mrs x9, dbgwcr15_el1 -# CHECK: mrs x9, mdrar_el1 -# CHECK: mrs x9, teehbr32_el1 -# CHECK: mrs x9, oslsr_el1 -# CHECK: mrs x9, osdlr_el1 -# CHECK: mrs x9, dbgprcr_el1 -# CHECK: mrs x9, dbgclaimset_el1 -# CHECK: mrs x9, dbgclaimclr_el1 -# CHECK: mrs x9, dbgauthstatus_el1 -# CHECK: mrs x9, midr_el1 -# CHECK: mrs x9, ccsidr_el1 -# CHECK: mrs x9, csselr_el1 -# CHECK: mrs x9, vpidr_el2 -# CHECK: mrs x9, clidr_el1 -# CHECK: mrs x9, ctr_el0 -# CHECK: mrs x9, mpidr_el1 -# CHECK: mrs x9, vmpidr_el2 -# CHECK: mrs x9, revidr_el1 -# CHECK: mrs x9, aidr_el1 -# CHECK: mrs x9, dczid_el0 -# CHECK: mrs x9, id_pfr0_el1 -# CHECK: mrs x9, id_pfr1_el1 -# CHECK: mrs x9, id_dfr0_el1 -# CHECK: mrs x9, id_afr0_el1 -# CHECK: mrs x9, id_mmfr0_el1 -# CHECK: mrs x9, id_mmfr1_el1 -# CHECK: mrs x9, id_mmfr2_el1 -# CHECK: mrs x9, id_mmfr3_el1 -# CHECK: mrs x9, id_isar0_el1 -# CHECK: mrs x9, id_isar1_el1 -# CHECK: mrs x9, id_isar2_el1 -# CHECK: mrs x9, id_isar3_el1 -# CHECK: mrs x9, id_isar4_el1 -# CHECK: mrs x9, id_isar5_el1 -# CHECK: mrs x9, mvfr0_el1 -# CHECK: mrs x9, mvfr1_el1 -# CHECK: mrs x9, mvfr2_el1 -# CHECK: mrs x9, id_aa64pfr0_el1 -# CHECK: mrs x9, id_aa64pfr1_el1 -# CHECK: mrs x9, id_aa64dfr0_el1 -# CHECK: mrs x9, id_aa64dfr1_el1 -# CHECK: mrs x9, id_aa64afr0_el1 -# CHECK: mrs x9, id_aa64afr1_el1 -# CHECK: mrs x9, id_aa64isar0_el1 -# CHECK: mrs x9, id_aa64isar1_el1 -# CHECK: mrs x9, id_aa64mmfr0_el1 -# CHECK: mrs x9, id_aa64mmfr1_el1 -# CHECK: mrs x9, sctlr_el1 -# CHECK: mrs x9, sctlr_el2 -# CHECK: mrs x9, sctlr_el3 -# CHECK: mrs x9, actlr_el1 -# CHECK: mrs x9, actlr_el2 -# CHECK: mrs x9, actlr_el3 -# CHECK: mrs x9, cpacr_el1 -# CHECK: mrs x9, hcr_el2 -# CHECK: mrs x9, scr_el3 -# CHECK: mrs x9, mdcr_el2 -# CHECK: mrs x9, sder32_el3 -# CHECK: mrs x9, cptr_el2 -# CHECK: mrs x9, cptr_el3 -# CHECK: mrs x9, hstr_el2 -# CHECK: mrs x9, hacr_el2 -# CHECK: mrs x9, mdcr_el3 -# CHECK: mrs x9, ttbr0_el1 -# CHECK: mrs x9, ttbr0_el2 -# CHECK: mrs x9, ttbr0_el3 -# CHECK: mrs x9, ttbr1_el1 -# CHECK: mrs x9, tcr_el1 -# CHECK: mrs x9, tcr_el2 -# CHECK: mrs x9, tcr_el3 -# CHECK: mrs x9, vttbr_el2 -# CHECK: mrs x9, vtcr_el2 -# CHECK: mrs x9, dacr32_el2 -# CHECK: mrs x9, spsr_el1 -# CHECK: mrs x9, spsr_el2 -# CHECK: mrs x9, spsr_el3 -# CHECK: mrs x9, elr_el1 -# CHECK: mrs x9, elr_el2 -# CHECK: mrs x9, elr_el3 -# CHECK: mrs x9, sp_el0 -# CHECK: mrs x9, sp_el1 -# CHECK: mrs x9, sp_el2 -# CHECK: mrs x9, spsel -# CHECK: mrs x9, nzcv -# CHECK: mrs x9, daif -# CHECK: mrs x9, currentel -# CHECK: mrs x9, spsr_irq -# CHECK: mrs x9, spsr_abt -# CHECK: mrs x9, spsr_und -# CHECK: mrs x9, spsr_fiq -# CHECK: mrs x9, fpcr -# CHECK: mrs x9, fpsr -# CHECK: mrs x9, dspsr_el0 -# CHECK: mrs x9, dlr_el0 -# CHECK: mrs x9, ifsr32_el2 -# CHECK: mrs x9, afsr0_el1 -# CHECK: mrs x9, afsr0_el2 -# CHECK: mrs x9, afsr0_el3 -# CHECK: mrs x9, afsr1_el1 -# CHECK: mrs x9, afsr1_el2 -# CHECK: mrs x9, afsr1_el3 -# CHECK: mrs x9, esr_el1 -# CHECK: mrs x9, esr_el2 -# CHECK: mrs x9, esr_el3 -# CHECK: mrs x9, fpexc32_el2 -# CHECK: mrs x9, far_el1 -# CHECK: mrs x9, far_el2 -# CHECK: mrs x9, far_el3 -# CHECK: mrs x9, hpfar_el2 -# CHECK: mrs x9, par_el1 -# CHECK: mrs x9, pmcr_el0 -# CHECK: mrs x9, pmcntenset_el0 -# CHECK: mrs x9, pmcntenclr_el0 -# CHECK: mrs x9, pmovsclr_el0 -# CHECK: mrs x9, pmselr_el0 -# CHECK: mrs x9, pmceid0_el0 -# CHECK: mrs x9, pmceid1_el0 -# CHECK: mrs x9, pmccntr_el0 -# CHECK: mrs x9, pmxevtyper_el0 -# CHECK: mrs x9, pmxevcntr_el0 -# CHECK: mrs x9, pmuserenr_el0 -# CHECK: mrs x9, pmintenset_el1 -# CHECK: mrs x9, pmintenclr_el1 -# CHECK: mrs x9, pmovsset_el0 -# CHECK: mrs x9, mair_el1 -# CHECK: mrs x9, mair_el2 -# CHECK: mrs x9, mair_el3 -# CHECK: mrs x9, amair_el1 -# CHECK: mrs x9, amair_el2 -# CHECK: mrs x9, amair_el3 -# CHECK: mrs x9, vbar_el1 -# CHECK: mrs x9, vbar_el2 -# CHECK: mrs x9, vbar_el3 -# CHECK: mrs x9, rvbar_el1 -# CHECK: mrs x9, rvbar_el2 -# CHECK: mrs x9, rvbar_el3 -# CHECK: mrs x9, rmr_el1 -# CHECK: mrs x9, rmr_el2 -# CHECK: mrs x9, rmr_el3 -# CHECK: mrs x9, isr_el1 -# CHECK: mrs x9, contextidr_el1 -# CHECK: mrs x9, tpidr_el0 -# CHECK: mrs x9, tpidr_el2 -# CHECK: mrs x9, tpidr_el3 -# CHECK: mrs x9, tpidrro_el0 -# CHECK: mrs x9, tpidr_el1 -# CHECK: mrs x9, cntfrq_el0 -# CHECK: mrs x9, cntpct_el0 -# CHECK: mrs x9, cntvct_el0 -# CHECK: mrs x9, cntvoff_el2 -# CHECK: mrs x9, cntkctl_el1 -# CHECK: mrs x9, cnthctl_el2 -# CHECK: mrs x9, cntp_tval_el0 -# CHECK: mrs x9, cnthp_tval_el2 -# CHECK: mrs x9, cntps_tval_el1 -# CHECK: mrs x9, cntp_ctl_el0 -# CHECK: mrs x9, cnthp_ctl_el2 -# CHECK: mrs x9, cntps_ctl_el1 -# CHECK: mrs x9, cntp_cval_el0 -# CHECK: mrs x9, cnthp_cval_el2 -# CHECK: mrs x9, cntps_cval_el1 -# CHECK: mrs x9, cntv_tval_el0 -# CHECK: mrs x9, cntv_ctl_el0 -# CHECK: mrs x9, cntv_cval_el0 -# CHECK: mrs x9, pmevcntr0_el0 -# CHECK: mrs x9, pmevcntr1_el0 -# CHECK: mrs x9, pmevcntr2_el0 -# CHECK: mrs x9, pmevcntr3_el0 -# CHECK: mrs x9, pmevcntr4_el0 -# CHECK: mrs x9, pmevcntr5_el0 -# CHECK: mrs x9, pmevcntr6_el0 -# CHECK: mrs x9, pmevcntr7_el0 -# CHECK: mrs x9, pmevcntr8_el0 -# CHECK: mrs x9, pmevcntr9_el0 -# CHECK: mrs x9, pmevcntr10_el0 -# CHECK: mrs x9, pmevcntr11_el0 -# CHECK: mrs x9, pmevcntr12_el0 -# CHECK: mrs x9, pmevcntr13_el0 -# CHECK: mrs x9, pmevcntr14_el0 -# CHECK: mrs x9, pmevcntr15_el0 -# CHECK: mrs x9, pmevcntr16_el0 -# CHECK: mrs x9, pmevcntr17_el0 -# CHECK: mrs x9, pmevcntr18_el0 -# CHECK: mrs x9, pmevcntr19_el0 -# CHECK: mrs x9, pmevcntr20_el0 -# CHECK: mrs x9, pmevcntr21_el0 -# CHECK: mrs x9, pmevcntr22_el0 -# CHECK: mrs x9, pmevcntr23_el0 -# CHECK: mrs x9, pmevcntr24_el0 -# CHECK: mrs x9, pmevcntr25_el0 -# CHECK: mrs x9, pmevcntr26_el0 -# CHECK: mrs x9, pmevcntr27_el0 -# CHECK: mrs x9, pmevcntr28_el0 -# CHECK: mrs x9, pmevcntr29_el0 -# CHECK: mrs x9, pmevcntr30_el0 -# CHECK: mrs x9, pmccfiltr_el0 -# CHECK: mrs x9, pmevtyper0_el0 -# CHECK: mrs x9, pmevtyper1_el0 -# CHECK: mrs x9, pmevtyper2_el0 -# CHECK: mrs x9, pmevtyper3_el0 -# CHECK: mrs x9, pmevtyper4_el0 -# CHECK: mrs x9, pmevtyper5_el0 -# CHECK: mrs x9, pmevtyper6_el0 -# CHECK: mrs x9, pmevtyper7_el0 -# CHECK: mrs x9, pmevtyper8_el0 -# CHECK: mrs x9, pmevtyper9_el0 -# CHECK: mrs x9, pmevtyper10_el0 -# CHECK: mrs x9, pmevtyper11_el0 -# CHECK: mrs x9, pmevtyper12_el0 -# CHECK: mrs x9, pmevtyper13_el0 -# CHECK: mrs x9, pmevtyper14_el0 -# CHECK: mrs x9, pmevtyper15_el0 -# CHECK: mrs x9, pmevtyper16_el0 -# CHECK: mrs x9, pmevtyper17_el0 -# CHECK: mrs x9, pmevtyper18_el0 -# CHECK: mrs x9, pmevtyper19_el0 -# CHECK: mrs x9, pmevtyper20_el0 -# CHECK: mrs x9, pmevtyper21_el0 -# CHECK: mrs x9, pmevtyper22_el0 -# CHECK: mrs x9, pmevtyper23_el0 -# CHECK: mrs x9, pmevtyper24_el0 -# CHECK: mrs x9, pmevtyper25_el0 -# CHECK: mrs x9, pmevtyper26_el0 -# CHECK: mrs x9, pmevtyper27_el0 -# CHECK: mrs x9, pmevtyper28_el0 -# CHECK: mrs x9, pmevtyper29_el0 -# CHECK: mrs x9, pmevtyper30_el0 +# CHECK: msr {{teecr32_el1|TEECR32_EL1}}, x12 +# CHECK: msr {{osdtrrx_el1|OSDTRRX_EL1}}, x12 +# CHECK: msr {{mdccint_el1|MDCCINT_EL1}}, x12 +# CHECK: msr {{mdscr_el1|MDSCR_EL1}}, x12 +# CHECK: msr {{osdtrtx_el1|OSDTRTX_EL1}}, x12 +# CHECK: msr {{dbgdtr_el0|DBGDTR_EL0}}, x12 +# CHECK: msr {{dbgdtrtx_el0|DBGDTRTX_EL0}}, x12 +# CHECK: msr {{oseccr_el1|OSECCR_EL1}}, x12 +# CHECK: msr {{dbgvcr32_el2|DBGVCR32_EL2}}, x12 +# CHECK: msr {{dbgbvr0_el1|DBGBVR0_EL1}}, x12 +# CHECK: msr {{dbgbvr1_el1|DBGBVR1_EL1}}, x12 +# CHECK: msr {{dbgbvr2_el1|DBGBVR2_EL1}}, x12 +# CHECK: msr {{dbgbvr3_el1|DBGBVR3_EL1}}, x12 +# CHECK: msr {{dbgbvr4_el1|DBGBVR4_EL1}}, x12 +# CHECK: msr {{dbgbvr5_el1|DBGBVR5_EL1}}, x12 +# CHECK: msr {{dbgbvr6_el1|DBGBVR6_EL1}}, x12 +# CHECK: msr {{dbgbvr7_el1|DBGBVR7_EL1}}, x12 +# CHECK: msr {{dbgbvr8_el1|DBGBVR8_EL1}}, x12 +# CHECK: msr {{dbgbvr9_el1|DBGBVR9_EL1}}, x12 +# CHECK: msr {{dbgbvr10_el1|DBGBVR10_EL1}}, x12 +# CHECK: msr {{dbgbvr11_el1|DBGBVR11_EL1}}, x12 +# CHECK: msr {{dbgbvr12_el1|DBGBVR12_EL1}}, x12 +# CHECK: msr {{dbgbvr13_el1|DBGBVR13_EL1}}, x12 +# CHECK: msr {{dbgbvr14_el1|DBGBVR14_EL1}}, x12 +# CHECK: msr {{dbgbvr15_el1|DBGBVR15_EL1}}, x12 +# CHECK: msr {{dbgbcr0_el1|DBGBCR0_EL1}}, x12 +# CHECK: msr {{dbgbcr1_el1|DBGBCR1_EL1}}, x12 +# CHECK: msr {{dbgbcr2_el1|DBGBCR2_EL1}}, x12 +# CHECK: msr {{dbgbcr3_el1|DBGBCR3_EL1}}, x12 +# CHECK: msr {{dbgbcr4_el1|DBGBCR4_EL1}}, x12 +# CHECK: msr {{dbgbcr5_el1|DBGBCR5_EL1}}, x12 +# CHECK: msr {{dbgbcr6_el1|DBGBCR6_EL1}}, x12 +# CHECK: msr {{dbgbcr7_el1|DBGBCR7_EL1}}, x12 +# CHECK: msr {{dbgbcr8_el1|DBGBCR8_EL1}}, x12 +# CHECK: msr {{dbgbcr9_el1|DBGBCR9_EL1}}, x12 +# CHECK: msr {{dbgbcr10_el1|DBGBCR10_EL1}}, x12 +# CHECK: msr {{dbgbcr11_el1|DBGBCR11_EL1}}, x12 +# CHECK: msr {{dbgbcr12_el1|DBGBCR12_EL1}}, x12 +# CHECK: msr {{dbgbcr13_el1|DBGBCR13_EL1}}, x12 +# CHECK: msr {{dbgbcr14_el1|DBGBCR14_EL1}}, x12 +# CHECK: msr {{dbgbcr15_el1|DBGBCR15_EL1}}, x12 +# CHECK: msr {{dbgwvr0_el1|DBGWVR0_EL1}}, x12 +# CHECK: msr {{dbgwvr1_el1|DBGWVR1_EL1}}, x12 +# CHECK: msr {{dbgwvr2_el1|DBGWVR2_EL1}}, x12 +# CHECK: msr {{dbgwvr3_el1|DBGWVR3_EL1}}, x12 +# CHECK: msr {{dbgwvr4_el1|DBGWVR4_EL1}}, x12 +# CHECK: msr {{dbgwvr5_el1|DBGWVR5_EL1}}, x12 +# CHECK: msr {{dbgwvr6_el1|DBGWVR6_EL1}}, x12 +# CHECK: msr {{dbgwvr7_el1|DBGWVR7_EL1}}, x12 +# CHECK: msr {{dbgwvr8_el1|DBGWVR8_EL1}}, x12 +# CHECK: msr {{dbgwvr9_el1|DBGWVR9_EL1}}, x12 +# CHECK: msr {{dbgwvr10_el1|DBGWVR10_EL1}}, x12 +# CHECK: msr {{dbgwvr11_el1|DBGWVR11_EL1}}, x12 +# CHECK: msr {{dbgwvr12_el1|DBGWVR12_EL1}}, x12 +# CHECK: msr {{dbgwvr13_el1|DBGWVR13_EL1}}, x12 +# CHECK: msr {{dbgwvr14_el1|DBGWVR14_EL1}}, x12 +# CHECK: msr {{dbgwvr15_el1|DBGWVR15_EL1}}, x12 +# CHECK: msr {{dbgwcr0_el1|DBGWCR0_EL1}}, x12 +# CHECK: msr {{dbgwcr1_el1|DBGWCR1_EL1}}, x12 +# CHECK: msr {{dbgwcr2_el1|DBGWCR2_EL1}}, x12 +# CHECK: msr {{dbgwcr3_el1|DBGWCR3_EL1}}, x12 +# CHECK: msr {{dbgwcr4_el1|DBGWCR4_EL1}}, x12 +# CHECK: msr {{dbgwcr5_el1|DBGWCR5_EL1}}, x12 +# CHECK: msr {{dbgwcr6_el1|DBGWCR6_EL1}}, x12 +# CHECK: msr {{dbgwcr7_el1|DBGWCR7_EL1}}, x12 +# CHECK: msr {{dbgwcr8_el1|DBGWCR8_EL1}}, x12 +# CHECK: msr {{dbgwcr9_el1|DBGWCR9_EL1}}, x12 +# CHECK: msr {{dbgwcr10_el1|DBGWCR10_EL1}}, x12 +# CHECK: msr {{dbgwcr11_el1|DBGWCR11_EL1}}, x12 +# CHECK: msr {{dbgwcr12_el1|DBGWCR12_EL1}}, x12 +# CHECK: msr {{dbgwcr13_el1|DBGWCR13_EL1}}, x12 +# CHECK: msr {{dbgwcr14_el1|DBGWCR14_EL1}}, x12 +# CHECK: msr {{dbgwcr15_el1|DBGWCR15_EL1}}, x12 +# CHECK: msr {{teehbr32_el1|TEEHBR32_EL1}}, x12 +# CHECK: msr {{oslar_el1|OSLAR_EL1}}, x12 +# CHECK: msr {{osdlr_el1|OSDLR_EL1}}, x12 +# CHECK: msr {{dbgprcr_el1|DBGPRCR_EL1}}, x12 +# CHECK: msr {{dbgclaimset_el1|DBGCLAIMSET_EL1}}, x12 +# CHECK: msr {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}, x12 +# CHECK: msr {{csselr_el1|CSSELR_EL1}}, x12 +# CHECK: msr {{vpidr_el2|VPIDR_EL2}}, x12 +# CHECK: msr {{vmpidr_el2|VMPIDR_EL2}}, x12 +# CHECK: msr {{sctlr_el1|SCTLR_EL1}}, x12 +# CHECK: msr {{sctlr_el2|SCTLR_EL2}}, x12 +# CHECK: msr {{sctlr_el3|SCTLR_EL3}}, x12 +# CHECK: msr {{actlr_el1|ACTLR_EL1}}, x12 +# CHECK: msr {{actlr_el2|ACTLR_EL2}}, x12 +# CHECK: msr {{actlr_el3|ACTLR_EL3}}, x12 +# CHECK: msr {{cpacr_el1|CPACR_EL1}}, x12 +# CHECK: msr {{hcr_el2|HCR_EL2}}, x12 +# CHECK: msr {{scr_el3|SCR_EL3}}, x12 +# CHECK: msr {{mdcr_el2|MDCR_EL2}}, x12 +# CHECK: msr {{sder32_el3|SDER32_EL3}}, x12 +# CHECK: msr {{cptr_el2|CPTR_EL2}}, x12 +# CHECK: msr {{cptr_el3|CPTR_EL3}}, x12 +# CHECK: msr {{hstr_el2|HSTR_EL2}}, x12 +# CHECK: msr {{hacr_el2|HACR_EL2}}, x12 +# CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12 +# CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12 +# CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12 +# CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12 +# CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12 +# CHECK: msr {{tcr_el1|TCR_EL1}}, x12 +# CHECK: msr {{tcr_el2|TCR_EL2}}, x12 +# CHECK: msr {{tcr_el3|TCR_EL3}}, x12 +# CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12 +# CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12 +# CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12 +# CHECK: msr {{spsr_el1|SPSR_EL1}}, x12 +# CHECK: msr {{spsr_el2|SPSR_EL2}}, x12 +# CHECK: msr {{spsr_el3|SPSR_EL3}}, x12 +# CHECK: msr {{elr_el1|ELR_EL1}}, x12 +# CHECK: msr {{elr_el2|ELR_EL2}}, x12 +# CHECK: msr {{elr_el3|ELR_EL3}}, x12 +# CHECK: msr {{sp_el0|SP_EL0}}, x12 +# CHECK: msr {{sp_el1|SP_EL1}}, x12 +# CHECK: msr {{sp_el2|SP_EL2}}, x12 +# CHECK: msr {{spsel|SPSEL}}, x12 +# CHECK: msr {{nzcv|NZCV}}, x12 +# CHECK: msr {{daif|DAIF}}, x12 +# CHECK: msr {{currentel|CURRENTEL}}, x12 +# CHECK: msr {{spsr_irq|SPSR_IRQ}}, x12 +# CHECK: msr {{spsr_abt|SPSR_ABT}}, x12 +# CHECK: msr {{spsr_und|SPSR_UND}}, x12 +# CHECK: msr {{spsr_fiq|SPSR_FIQ}}, x12 +# CHECK: msr {{fpcr|FPCR}}, x12 +# CHECK: msr {{fpsr|FPSR}}, x12 +# CHECK: msr {{dspsr_el0|DSPSR_EL0}}, x12 +# CHECK: msr {{dlr_el0|DLR_EL0}}, x12 +# CHECK: msr {{ifsr32_el2|IFSR32_EL2}}, x12 +# CHECK: msr {{afsr0_el1|AFSR0_EL1}}, x12 +# CHECK: msr {{afsr0_el2|AFSR0_EL2}}, x12 +# CHECK: msr {{afsr0_el3|AFSR0_EL3}}, x12 +# CHECK: msr {{afsr1_el1|AFSR1_EL1}}, x12 +# CHECK: msr {{afsr1_el2|AFSR1_EL2}}, x12 +# CHECK: msr {{afsr1_el3|AFSR1_EL3}}, x12 +# CHECK: msr {{esr_el1|ESR_EL1}}, x12 +# CHECK: msr {{esr_el2|ESR_EL2}}, x12 +# CHECK: msr {{esr_el3|ESR_EL3}}, x12 +# CHECK: msr {{fpexc32_el2|FPEXC32_EL2}}, x12 +# CHECK: msr {{far_el1|FAR_EL1}}, x12 +# CHECK: msr {{far_el2|FAR_EL2}}, x12 +# CHECK: msr {{far_el3|FAR_EL3}}, x12 +# CHECK: msr {{hpfar_el2|HPFAR_EL2}}, x12 +# CHECK: msr {{par_el1|PAR_EL1}}, x12 +# CHECK: msr {{pmcr_el0|PMCR_EL0}}, x12 +# CHECK: msr {{pmcntenset_el0|PMCNTENSET_EL0}}, x12 +# CHECK: msr {{pmcntenclr_el0|PMCNTENCLR_EL0}}, x12 +# CHECK: msr {{pmovsclr_el0|PMOVSCLR_EL0}}, x12 +# CHECK: msr {{pmselr_el0|PMSELR_EL0}}, x12 +# CHECK: msr {{pmccntr_el0|PMCCNTR_EL0}}, x12 +# CHECK: msr {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12 +# CHECK: msr {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12 +# CHECK: msr {{pmuserenr_el0|PMUSERENR_EL0}}, x12 +# CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12 +# CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12 +# CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12 +# CHECK: msr {{mair_el1|MAIR_EL1}}, x12 +# CHECK: msr {{mair_el2|MAIR_EL2}}, x12 +# CHECK: msr {{mair_el3|MAIR_EL3}}, x12 +# CHECK: msr {{amair_el1|AMAIR_EL1}}, x12 +# CHECK: msr {{amair_el2|AMAIR_EL2}}, x12 +# CHECK: msr {{amair_el3|AMAIR_EL3}}, x12 +# CHECK: msr {{vbar_el1|VBAR_EL1}}, x12 +# CHECK: msr {{vbar_el2|VBAR_EL2}}, x12 +# CHECK: msr {{vbar_el3|VBAR_EL3}}, x12 +# CHECK: msr {{rmr_el1|RMR_EL1}}, x12 +# CHECK: msr {{rmr_el2|RMR_EL2}}, x12 +# CHECK: msr {{rmr_el3|RMR_EL3}}, x12 +# CHECK: msr {{tpidr_el0|TPIDR_EL0}}, x12 +# CHECK: msr {{tpidr_el2|TPIDR_EL2}}, x12 +# CHECK: msr {{tpidr_el3|TPIDR_EL3}}, x12 +# CHECK: msr {{tpidrro_el0|TPIDRRO_EL0}}, x12 +# CHECK: msr {{tpidr_el1|TPIDR_EL1}}, x12 +# CHECK: msr {{cntfrq_el0|CNTFRQ_EL0}}, x12 +# CHECK: msr {{cntvoff_el2|CNTVOFF_EL2}}, x12 +# CHECK: msr {{cntkctl_el1|CNTKCTL_EL1}}, x12 +# CHECK: msr {{cnthctl_el2|CNTHCTL_EL2}}, x12 +# CHECK: msr {{cntp_tval_el0|CNTP_TVAL_EL0}}, x12 +# CHECK: msr {{cnthp_tval_el2|CNTHP_TVAL_EL2}}, x12 +# CHECK: msr {{cntps_tval_el1|CNTPS_TVAL_EL1}}, x12 +# CHECK: msr {{cntp_ctl_el0|CNTP_CTL_EL0}}, x12 +# CHECK: msr {{cnthp_ctl_el2|CNTHP_CTL_EL2}}, x12 +# CHECK: msr {{cntps_ctl_el1|CNTPS_CTL_EL1}}, x12 +# CHECK: msr {{cntp_cval_el0|CNTP_CVAL_EL0}}, x12 +# CHECK: msr {{cnthp_cval_el2|CNTHP_CVAL_EL2}}, x12 +# CHECK: msr {{cntps_cval_el1|CNTPS_CVAL_EL1}}, x12 +# CHECK: msr {{cntv_tval_el0|CNTV_TVAL_EL0}}, x12 +# CHECK: msr {{cntv_ctl_el0|CNTV_CTL_EL0}}, x12 +# CHECK: msr {{cntv_cval_el0|CNTV_CVAL_EL0}}, x12 +# CHECK: msr {{pmevcntr0_el0|PMEVCNTR0_EL0}}, x12 +# CHECK: msr {{pmevcntr1_el0|PMEVCNTR1_EL0}}, x12 +# CHECK: msr {{pmevcntr2_el0|PMEVCNTR2_EL0}}, x12 +# CHECK: msr {{pmevcntr3_el0|PMEVCNTR3_EL0}}, x12 +# CHECK: msr {{pmevcntr4_el0|PMEVCNTR4_EL0}}, x12 +# CHECK: msr {{pmevcntr5_el0|PMEVCNTR5_EL0}}, x12 +# CHECK: msr {{pmevcntr6_el0|PMEVCNTR6_EL0}}, x12 +# CHECK: msr {{pmevcntr7_el0|PMEVCNTR7_EL0}}, x12 +# CHECK: msr {{pmevcntr8_el0|PMEVCNTR8_EL0}}, x12 +# CHECK: msr {{pmevcntr9_el0|PMEVCNTR9_EL0}}, x12 +# CHECK: msr {{pmevcntr10_el0|PMEVCNTR10_EL0}}, x12 +# CHECK: msr {{pmevcntr11_el0|PMEVCNTR11_EL0}}, x12 +# CHECK: msr {{pmevcntr12_el0|PMEVCNTR12_EL0}}, x12 +# CHECK: msr {{pmevcntr13_el0|PMEVCNTR13_EL0}}, x12 +# CHECK: msr {{pmevcntr14_el0|PMEVCNTR14_EL0}}, x12 +# CHECK: msr {{pmevcntr15_el0|PMEVCNTR15_EL0}}, x12 +# CHECK: msr {{pmevcntr16_el0|PMEVCNTR16_EL0}}, x12 +# CHECK: msr {{pmevcntr17_el0|PMEVCNTR17_EL0}}, x12 +# CHECK: msr {{pmevcntr18_el0|PMEVCNTR18_EL0}}, x12 +# CHECK: msr {{pmevcntr19_el0|PMEVCNTR19_EL0}}, x12 +# CHECK: msr {{pmevcntr20_el0|PMEVCNTR20_EL0}}, x12 +# CHECK: msr {{pmevcntr21_el0|PMEVCNTR21_EL0}}, x12 +# CHECK: msr {{pmevcntr22_el0|PMEVCNTR22_EL0}}, x12 +# CHECK: msr {{pmevcntr23_el0|PMEVCNTR23_EL0}}, x12 +# CHECK: msr {{pmevcntr24_el0|PMEVCNTR24_EL0}}, x12 +# CHECK: msr {{pmevcntr25_el0|PMEVCNTR25_EL0}}, x12 +# CHECK: msr {{pmevcntr26_el0|PMEVCNTR26_EL0}}, x12 +# CHECK: msr {{pmevcntr27_el0|PMEVCNTR27_EL0}}, x12 +# CHECK: msr {{pmevcntr28_el0|PMEVCNTR28_EL0}}, x12 +# CHECK: msr {{pmevcntr29_el0|PMEVCNTR29_EL0}}, x12 +# CHECK: msr {{pmevcntr30_el0|PMEVCNTR30_EL0}}, x12 +# CHECK: msr {{pmccfiltr_el0|PMCCFILTR_EL0}}, x12 +# CHECK: msr {{pmevtyper0_el0|PMEVTYPER0_EL0}}, x12 +# CHECK: msr {{pmevtyper1_el0|PMEVTYPER1_EL0}}, x12 +# CHECK: msr {{pmevtyper2_el0|PMEVTYPER2_EL0}}, x12 +# CHECK: msr {{pmevtyper3_el0|PMEVTYPER3_EL0}}, x12 +# CHECK: msr {{pmevtyper4_el0|PMEVTYPER4_EL0}}, x12 +# CHECK: msr {{pmevtyper5_el0|PMEVTYPER5_EL0}}, x12 +# CHECK: msr {{pmevtyper6_el0|PMEVTYPER6_EL0}}, x12 +# CHECK: msr {{pmevtyper7_el0|PMEVTYPER7_EL0}}, x12 +# CHECK: msr {{pmevtyper8_el0|PMEVTYPER8_EL0}}, x12 +# CHECK: msr {{pmevtyper9_el0|PMEVTYPER9_EL0}}, x12 +# CHECK: msr {{pmevtyper10_el0|PMEVTYPER10_EL0}}, x12 +# CHECK: msr {{pmevtyper11_el0|PMEVTYPER11_EL0}}, x12 +# CHECK: msr {{pmevtyper12_el0|PMEVTYPER12_EL0}}, x12 +# CHECK: msr {{pmevtyper13_el0|PMEVTYPER13_EL0}}, x12 +# CHECK: msr {{pmevtyper14_el0|PMEVTYPER14_EL0}}, x12 +# CHECK: msr {{pmevtyper15_el0|PMEVTYPER15_EL0}}, x12 +# CHECK: msr {{pmevtyper16_el0|PMEVTYPER16_EL0}}, x12 +# CHECK: msr {{pmevtyper17_el0|PMEVTYPER17_EL0}}, x12 +# CHECK: msr {{pmevtyper18_el0|PMEVTYPER18_EL0}}, x12 +# CHECK: msr {{pmevtyper19_el0|PMEVTYPER19_EL0}}, x12 +# CHECK: msr {{pmevtyper20_el0|PMEVTYPER20_EL0}}, x12 +# CHECK: msr {{pmevtyper21_el0|PMEVTYPER21_EL0}}, x12 +# CHECK: msr {{pmevtyper22_el0|PMEVTYPER22_EL0}}, x12 +# CHECK: msr {{pmevtyper23_el0|PMEVTYPER23_EL0}}, x12 +# CHECK: msr {{pmevtyper24_el0|PMEVTYPER24_EL0}}, x12 +# CHECK: msr {{pmevtyper25_el0|PMEVTYPER25_EL0}}, x12 +# CHECK: msr {{pmevtyper26_el0|PMEVTYPER26_EL0}}, x12 +# CHECK: msr {{pmevtyper27_el0|PMEVTYPER27_EL0}}, x12 +# CHECK: msr {{pmevtyper28_el0|PMEVTYPER28_EL0}}, x12 +# CHECK: msr {{pmevtyper29_el0|PMEVTYPER29_EL0}}, x12 +# CHECK: msr {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12 +# CHECK: mrs x9, {{teecr32_el1|TEECR32_EL1}} +# CHECK: mrs x9, {{osdtrrx_el1|OSDTRRX_EL1}} +# CHECK: mrs x9, {{mdccsr_el0|MDCCSR_EL0}} +# CHECK: mrs x9, {{mdccint_el1|MDCCINT_EL1}} +# CHECK: mrs x9, {{mdscr_el1|MDSCR_EL1}} +# CHECK: mrs x9, {{osdtrtx_el1|OSDTRTX_EL1}} +# CHECK: mrs x9, {{dbgdtr_el0|DBGDTR_EL0}} +# CHECK: mrs x9, {{dbgdtrrx_el0|DBGDTRRX_EL0}} +# CHECK: mrs x9, {{oseccr_el1|OSECCR_EL1}} +# CHECK: mrs x9, {{dbgvcr32_el2|DBGVCR32_EL2}} +# CHECK: mrs x9, {{dbgbvr0_el1|DBGBVR0_EL1}} +# CHECK: mrs x9, {{dbgbvr1_el1|DBGBVR1_EL1}} +# CHECK: mrs x9, {{dbgbvr2_el1|DBGBVR2_EL1}} +# CHECK: mrs x9, {{dbgbvr3_el1|DBGBVR3_EL1}} +# CHECK: mrs x9, {{dbgbvr4_el1|DBGBVR4_EL1}} +# CHECK: mrs x9, {{dbgbvr5_el1|DBGBVR5_EL1}} +# CHECK: mrs x9, {{dbgbvr6_el1|DBGBVR6_EL1}} +# CHECK: mrs x9, {{dbgbvr7_el1|DBGBVR7_EL1}} +# CHECK: mrs x9, {{dbgbvr8_el1|DBGBVR8_EL1}} +# CHECK: mrs x9, {{dbgbvr9_el1|DBGBVR9_EL1}} +# CHECK: mrs x9, {{dbgbvr10_el1|DBGBVR10_EL1}} +# CHECK: mrs x9, {{dbgbvr11_el1|DBGBVR11_EL1}} +# CHECK: mrs x9, {{dbgbvr12_el1|DBGBVR12_EL1}} +# CHECK: mrs x9, {{dbgbvr13_el1|DBGBVR13_EL1}} +# CHECK: mrs x9, {{dbgbvr14_el1|DBGBVR14_EL1}} +# CHECK: mrs x9, {{dbgbvr15_el1|DBGBVR15_EL1}} +# CHECK: mrs x9, {{dbgbcr0_el1|DBGBCR0_EL1}} +# CHECK: mrs x9, {{dbgbcr1_el1|DBGBCR1_EL1}} +# CHECK: mrs x9, {{dbgbcr2_el1|DBGBCR2_EL1}} +# CHECK: mrs x9, {{dbgbcr3_el1|DBGBCR3_EL1}} +# CHECK: mrs x9, {{dbgbcr4_el1|DBGBCR4_EL1}} +# CHECK: mrs x9, {{dbgbcr5_el1|DBGBCR5_EL1}} +# CHECK: mrs x9, {{dbgbcr6_el1|DBGBCR6_EL1}} +# CHECK: mrs x9, {{dbgbcr7_el1|DBGBCR7_EL1}} +# CHECK: mrs x9, {{dbgbcr8_el1|DBGBCR8_EL1}} +# CHECK: mrs x9, {{dbgbcr9_el1|DBGBCR9_EL1}} +# CHECK: mrs x9, {{dbgbcr10_el1|DBGBCR10_EL1}} +# CHECK: mrs x9, {{dbgbcr11_el1|DBGBCR11_EL1}} +# CHECK: mrs x9, {{dbgbcr12_el1|DBGBCR12_EL1}} +# CHECK: mrs x9, {{dbgbcr13_el1|DBGBCR13_EL1}} +# CHECK: mrs x9, {{dbgbcr14_el1|DBGBCR14_EL1}} +# CHECK: mrs x9, {{dbgbcr15_el1|DBGBCR15_EL1}} +# CHECK: mrs x9, {{dbgwvr0_el1|DBGWVR0_EL1}} +# CHECK: mrs x9, {{dbgwvr1_el1|DBGWVR1_EL1}} +# CHECK: mrs x9, {{dbgwvr2_el1|DBGWVR2_EL1}} +# CHECK: mrs x9, {{dbgwvr3_el1|DBGWVR3_EL1}} +# CHECK: mrs x9, {{dbgwvr4_el1|DBGWVR4_EL1}} +# CHECK: mrs x9, {{dbgwvr5_el1|DBGWVR5_EL1}} +# CHECK: mrs x9, {{dbgwvr6_el1|DBGWVR6_EL1}} +# CHECK: mrs x9, {{dbgwvr7_el1|DBGWVR7_EL1}} +# CHECK: mrs x9, {{dbgwvr8_el1|DBGWVR8_EL1}} +# CHECK: mrs x9, {{dbgwvr9_el1|DBGWVR9_EL1}} +# CHECK: mrs x9, {{dbgwvr10_el1|DBGWVR10_EL1}} +# CHECK: mrs x9, {{dbgwvr11_el1|DBGWVR11_EL1}} +# CHECK: mrs x9, {{dbgwvr12_el1|DBGWVR12_EL1}} +# CHECK: mrs x9, {{dbgwvr13_el1|DBGWVR13_EL1}} +# CHECK: mrs x9, {{dbgwvr14_el1|DBGWVR14_EL1}} +# CHECK: mrs x9, {{dbgwvr15_el1|DBGWVR15_EL1}} +# CHECK: mrs x9, {{dbgwcr0_el1|DBGWCR0_EL1}} +# CHECK: mrs x9, {{dbgwcr1_el1|DBGWCR1_EL1}} +# CHECK: mrs x9, {{dbgwcr2_el1|DBGWCR2_EL1}} +# CHECK: mrs x9, {{dbgwcr3_el1|DBGWCR3_EL1}} +# CHECK: mrs x9, {{dbgwcr4_el1|DBGWCR4_EL1}} +# CHECK: mrs x9, {{dbgwcr5_el1|DBGWCR5_EL1}} +# CHECK: mrs x9, {{dbgwcr6_el1|DBGWCR6_EL1}} +# CHECK: mrs x9, {{dbgwcr7_el1|DBGWCR7_EL1}} +# CHECK: mrs x9, {{dbgwcr8_el1|DBGWCR8_EL1}} +# CHECK: mrs x9, {{dbgwcr9_el1|DBGWCR9_EL1}} +# CHECK: mrs x9, {{dbgwcr10_el1|DBGWCR10_EL1}} +# CHECK: mrs x9, {{dbgwcr11_el1|DBGWCR11_EL1}} +# CHECK: mrs x9, {{dbgwcr12_el1|DBGWCR12_EL1}} +# CHECK: mrs x9, {{dbgwcr13_el1|DBGWCR13_EL1}} +# CHECK: mrs x9, {{dbgwcr14_el1|DBGWCR14_EL1}} +# CHECK: mrs x9, {{dbgwcr15_el1|DBGWCR15_EL1}} +# CHECK: mrs x9, {{mdrar_el1|MDRAR_EL1}} +# CHECK: mrs x9, {{teehbr32_el1|TEEHBR32_EL1}} +# CHECK: mrs x9, {{oslsr_el1|OSLSR_EL1}} +# CHECK: mrs x9, {{osdlr_el1|OSDLR_EL1}} +# CHECK: mrs x9, {{dbgprcr_el1|DBGPRCR_EL1}} +# CHECK: mrs x9, {{dbgclaimset_el1|DBGCLAIMSET_EL1}} +# CHECK: mrs x9, {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}} +# CHECK: mrs x9, {{dbgauthstatus_el1|DBGAUTHSTATUS_EL1}} +# CHECK: mrs x9, {{midr_el1|MIDR_EL1}} +# CHECK: mrs x9, {{ccsidr_el1|CCSIDR_EL1}} +# CHECK: mrs x9, {{csselr_el1|CSSELR_EL1}} +# CHECK: mrs x9, {{vpidr_el2|VPIDR_EL2}} +# CHECK: mrs x9, {{clidr_el1|CLIDR_EL1}} +# CHECK: mrs x9, {{ctr_el0|CTR_EL0}} +# CHECK: mrs x9, {{mpidr_el1|MPIDR_EL1}} +# CHECK: mrs x9, {{vmpidr_el2|VMPIDR_EL2}} +# CHECK: mrs x9, {{revidr_el1|REVIDR_EL1}} +# CHECK: mrs x9, {{aidr_el1|AIDR_EL1}} +# CHECK: mrs x9, {{dczid_el0|DCZID_EL0}} +# CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}} +# CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}} +# CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}} +# CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}} +# CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}} +# CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}} +# CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}} +# CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}} +# CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}} +# CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}} +# CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}} +# CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}} +# CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}} +# CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}} +# CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}} +# CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}} +# CHECK: mrs x9, {{mvfr2_el1|MVFR2_EL1}} +# CHECK: mrs x9, {{id_aa64pfr0_el1|ID_AA64PFR0_EL1}} +# CHECK: mrs x9, {{id_aa64pfr1_el1|ID_AA64PFR1_EL1}} +# CHECK: mrs x9, {{id_aa64dfr0_el1|ID_AA64DFR0_EL1}} +# CHECK: mrs x9, {{id_aa64dfr1_el1|ID_AA64DFR1_EL1}} +# CHECK: mrs x9, {{id_aa64afr0_el1|ID_AA64AFR0_EL1}} +# CHECK: mrs x9, {{id_aa64afr1_el1|ID_AA64AFR1_EL1}} +# CHECK: mrs x9, {{id_aa64isar0_el1|ID_AA64ISAR0_EL1}} +# CHECK: mrs x9, {{id_aa64isar1_el1|ID_AA64ISAR1_EL1}} +# CHECK: mrs x9, {{id_aa64mmfr0_el1|ID_AA64MMFR0_EL1}} +# CHECK: mrs x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}} +# CHECK: mrs x9, {{sctlr_el1|SCTLR_EL1}} +# CHECK: mrs x9, {{sctlr_el2|SCTLR_EL2}} +# CHECK: mrs x9, {{sctlr_el3|SCTLR_EL3}} +# CHECK: mrs x9, {{actlr_el1|ACTLR_EL1}} +# CHECK: mrs x9, {{actlr_el2|ACTLR_EL2}} +# CHECK: mrs x9, {{actlr_el3|ACTLR_EL3}} +# CHECK: mrs x9, {{cpacr_el1|CPACR_EL1}} +# CHECK: mrs x9, {{hcr_el2|HCR_EL2}} +# CHECK: mrs x9, {{scr_el3|SCR_EL3}} +# CHECK: mrs x9, {{mdcr_el2|MDCR_EL2}} +# CHECK: mrs x9, {{sder32_el3|SDER32_EL3}} +# CHECK: mrs x9, {{cptr_el2|CPTR_EL2}} +# CHECK: mrs x9, {{cptr_el3|CPTR_EL3}} +# CHECK: mrs x9, {{hstr_el2|HSTR_EL2}} +# CHECK: mrs x9, {{hacr_el2|HACR_EL2}} +# CHECK: mrs x9, {{mdcr_el3|MDCR_EL3}} +# CHECK: mrs x9, {{ttbr0_el1|TTBR0_EL1}} +# CHECK: mrs x9, {{ttbr0_el2|TTBR0_EL2}} +# CHECK: mrs x9, {{ttbr0_el3|TTBR0_EL3}} +# CHECK: mrs x9, {{ttbr1_el1|TTBR1_EL1}} +# CHECK: mrs x9, {{tcr_el1|TCR_EL1}} +# CHECK: mrs x9, {{tcr_el2|TCR_EL2}} +# CHECK: mrs x9, {{tcr_el3|TCR_EL3}} +# CHECK: mrs x9, {{vttbr_el2|VTTBR_EL2}} +# CHECK: mrs x9, {{vtcr_el2|VTCR_EL2}} +# CHECK: mrs x9, {{dacr32_el2|DACR32_EL2}} +# CHECK: mrs x9, {{spsr_el1|SPSR_EL1}} +# CHECK: mrs x9, {{spsr_el2|SPSR_EL2}} +# CHECK: mrs x9, {{spsr_el3|SPSR_EL3}} +# CHECK: mrs x9, {{elr_el1|ELR_EL1}} +# CHECK: mrs x9, {{elr_el2|ELR_EL2}} +# CHECK: mrs x9, {{elr_el3|ELR_EL3}} +# CHECK: mrs x9, {{sp_el0|SP_EL0}} +# CHECK: mrs x9, {{sp_el1|SP_EL1}} +# CHECK: mrs x9, {{sp_el2|SP_EL2}} +# CHECK: mrs x9, {{spsel|SPSEL}} +# CHECK: mrs x9, {{nzcv|NZCV}} +# CHECK: mrs x9, {{daif|DAIF}} +# CHECK: mrs x9, {{currentel|CURRENTEL}} +# CHECK: mrs x9, {{spsr_irq|SPSR_IRQ}} +# CHECK: mrs x9, {{spsr_abt|SPSR_ABT}} +# CHECK: mrs x9, {{spsr_und|SPSR_UND}} +# CHECK: mrs x9, {{spsr_fiq|SPSR_FIQ}} +# CHECK: mrs x9, {{fpcr|FPCR}} +# CHECK: mrs x9, {{fpsr|FPSR}} +# CHECK: mrs x9, {{dspsr_el0|DSPSR_EL0}} +# CHECK: mrs x9, {{dlr_el0|DLR_EL0}} +# CHECK: mrs x9, {{ifsr32_el2|IFSR32_EL2}} +# CHECK: mrs x9, {{afsr0_el1|AFSR0_EL1}} +# CHECK: mrs x9, {{afsr0_el2|AFSR0_EL2}} +# CHECK: mrs x9, {{afsr0_el3|AFSR0_EL3}} +# CHECK: mrs x9, {{afsr1_el1|AFSR1_EL1}} +# CHECK: mrs x9, {{afsr1_el2|AFSR1_EL2}} +# CHECK: mrs x9, {{afsr1_el3|AFSR1_EL3}} +# CHECK: mrs x9, {{esr_el1|ESR_EL1}} +# CHECK: mrs x9, {{esr_el2|ESR_EL2}} +# CHECK: mrs x9, {{esr_el3|ESR_EL3}} +# CHECK: mrs x9, {{fpexc32_el2|FPEXC32_EL2}} +# CHECK: mrs x9, {{far_el1|FAR_EL1}} +# CHECK: mrs x9, {{far_el2|FAR_EL2}} +# CHECK: mrs x9, {{far_el3|FAR_EL3}} +# CHECK: mrs x9, {{hpfar_el2|HPFAR_EL2}} +# CHECK: mrs x9, {{par_el1|PAR_EL1}} +# CHECK: mrs x9, {{pmcr_el0|PMCR_EL0}} +# CHECK: mrs x9, {{pmcntenset_el0|PMCNTENSET_EL0}} +# CHECK: mrs x9, {{pmcntenclr_el0|PMCNTENCLR_EL0}} +# CHECK: mrs x9, {{pmovsclr_el0|PMOVSCLR_EL0}} +# CHECK: mrs x9, {{pmselr_el0|PMSELR_EL0}} +# CHECK: mrs x9, {{pmceid0_el0|PMCEID0_EL0}} +# CHECK: mrs x9, {{pmceid1_el0|PMCEID1_EL0}} +# CHECK: mrs x9, {{pmccntr_el0|PMCCNTR_EL0}} +# CHECK: mrs x9, {{pmxevtyper_el0|PMXEVTYPER_EL0}} +# CHECK: mrs x9, {{pmxevcntr_el0|PMXEVCNTR_EL0}} +# CHECK: mrs x9, {{pmuserenr_el0|PMUSERENR_EL0}} +# CHECK: mrs x9, {{pmintenset_el1|PMINTENSET_EL1}} +# CHECK: mrs x9, {{pmintenclr_el1|PMINTENCLR_EL1}} +# CHECK: mrs x9, {{pmovsset_el0|PMOVSSET_EL0}} +# CHECK: mrs x9, {{mair_el1|MAIR_EL1}} +# CHECK: mrs x9, {{mair_el2|MAIR_EL2}} +# CHECK: mrs x9, {{mair_el3|MAIR_EL3}} +# CHECK: mrs x9, {{amair_el1|AMAIR_EL1}} +# CHECK: mrs x9, {{amair_el2|AMAIR_EL2}} +# CHECK: mrs x9, {{amair_el3|AMAIR_EL3}} +# CHECK: mrs x9, {{vbar_el1|VBAR_EL1}} +# CHECK: mrs x9, {{vbar_el2|VBAR_EL2}} +# CHECK: mrs x9, {{vbar_el3|VBAR_EL3}} +# CHECK: mrs x9, {{rvbar_el1|RVBAR_EL1}} +# CHECK: mrs x9, {{rvbar_el2|RVBAR_EL2}} +# CHECK: mrs x9, {{rvbar_el3|RVBAR_EL3}} +# CHECK: mrs x9, {{rmr_el1|RMR_EL1}} +# CHECK: mrs x9, {{rmr_el2|RMR_EL2}} +# CHECK: mrs x9, {{rmr_el3|RMR_EL3}} +# CHECK: mrs x9, {{isr_el1|ISR_EL1}} +# CHECK: mrs x9, {{contextidr_el1|CONTEXTIDR_EL1}} +# CHECK: mrs x9, {{tpidr_el0|TPIDR_EL0}} +# CHECK: mrs x9, {{tpidr_el2|TPIDR_EL2}} +# CHECK: mrs x9, {{tpidr_el3|TPIDR_EL3}} +# CHECK: mrs x9, {{tpidrro_el0|TPIDRRO_EL0}} +# CHECK: mrs x9, {{tpidr_el1|TPIDR_EL1}} +# CHECK: mrs x9, {{cntfrq_el0|CNTFRQ_EL0}} +# CHECK: mrs x9, {{cntpct_el0|CNTPCT_EL0}} +# CHECK: mrs x9, {{cntvct_el0|CNTVCT_EL0}} +# CHECK: mrs x9, {{cntvoff_el2|CNTVOFF_EL2}} +# CHECK: mrs x9, {{cntkctl_el1|CNTKCTL_EL1}} +# CHECK: mrs x9, {{cnthctl_el2|CNTHCTL_EL2}} +# CHECK: mrs x9, {{cntp_tval_el0|CNTP_TVAL_EL0}} +# CHECK: mrs x9, {{cnthp_tval_el2|CNTHP_TVAL_EL2}} +# CHECK: mrs x9, {{cntps_tval_el1|CNTPS_TVAL_EL1}} +# CHECK: mrs x9, {{cntp_ctl_el0|CNTP_CTL_EL0}} +# CHECK: mrs x9, {{cnthp_ctl_el2|CNTHP_CTL_EL2}} +# CHECK: mrs x9, {{cntps_ctl_el1|CNTPS_CTL_EL1}} +# CHECK: mrs x9, {{cntp_cval_el0|CNTP_CVAL_EL0}} +# CHECK: mrs x9, {{cnthp_cval_el2|CNTHP_CVAL_EL2}} +# CHECK: mrs x9, {{cntps_cval_el1|CNTPS_CVAL_EL1}} +# CHECK: mrs x9, {{cntv_tval_el0|CNTV_TVAL_EL0}} +# CHECK: mrs x9, {{cntv_ctl_el0|CNTV_CTL_EL0}} +# CHECK: mrs x9, {{cntv_cval_el0|CNTV_CVAL_EL0}} +# CHECK: mrs x9, {{pmevcntr0_el0|PMEVCNTR0_EL0}} +# CHECK: mrs x9, {{pmevcntr1_el0|PMEVCNTR1_EL0}} +# CHECK: mrs x9, {{pmevcntr2_el0|PMEVCNTR2_EL0}} +# CHECK: mrs x9, {{pmevcntr3_el0|PMEVCNTR3_EL0}} +# CHECK: mrs x9, {{pmevcntr4_el0|PMEVCNTR4_EL0}} +# CHECK: mrs x9, {{pmevcntr5_el0|PMEVCNTR5_EL0}} +# CHECK: mrs x9, {{pmevcntr6_el0|PMEVCNTR6_EL0}} +# CHECK: mrs x9, {{pmevcntr7_el0|PMEVCNTR7_EL0}} +# CHECK: mrs x9, {{pmevcntr8_el0|PMEVCNTR8_EL0}} +# CHECK: mrs x9, {{pmevcntr9_el0|PMEVCNTR9_EL0}} +# CHECK: mrs x9, {{pmevcntr10_el0|PMEVCNTR10_EL0}} +# CHECK: mrs x9, {{pmevcntr11_el0|PMEVCNTR11_EL0}} +# CHECK: mrs x9, {{pmevcntr12_el0|PMEVCNTR12_EL0}} +# CHECK: mrs x9, {{pmevcntr13_el0|PMEVCNTR13_EL0}} +# CHECK: mrs x9, {{pmevcntr14_el0|PMEVCNTR14_EL0}} +# CHECK: mrs x9, {{pmevcntr15_el0|PMEVCNTR15_EL0}} +# CHECK: mrs x9, {{pmevcntr16_el0|PMEVCNTR16_EL0}} +# CHECK: mrs x9, {{pmevcntr17_el0|PMEVCNTR17_EL0}} +# CHECK: mrs x9, {{pmevcntr18_el0|PMEVCNTR18_EL0}} +# CHECK: mrs x9, {{pmevcntr19_el0|PMEVCNTR19_EL0}} +# CHECK: mrs x9, {{pmevcntr20_el0|PMEVCNTR20_EL0}} +# CHECK: mrs x9, {{pmevcntr21_el0|PMEVCNTR21_EL0}} +# CHECK: mrs x9, {{pmevcntr22_el0|PMEVCNTR22_EL0}} +# CHECK: mrs x9, {{pmevcntr23_el0|PMEVCNTR23_EL0}} +# CHECK: mrs x9, {{pmevcntr24_el0|PMEVCNTR24_EL0}} +# CHECK: mrs x9, {{pmevcntr25_el0|PMEVCNTR25_EL0}} +# CHECK: mrs x9, {{pmevcntr26_el0|PMEVCNTR26_EL0}} +# CHECK: mrs x9, {{pmevcntr27_el0|PMEVCNTR27_EL0}} +# CHECK: mrs x9, {{pmevcntr28_el0|PMEVCNTR28_EL0}} +# CHECK: mrs x9, {{pmevcntr29_el0|PMEVCNTR29_EL0}} +# CHECK: mrs x9, {{pmevcntr30_el0|PMEVCNTR30_EL0}} +# CHECK: mrs x9, {{pmccfiltr_el0|PMCCFILTR_EL0}} +# CHECK: mrs x9, {{pmevtyper0_el0|PMEVTYPER0_EL0}} +# CHECK: mrs x9, {{pmevtyper1_el0|PMEVTYPER1_EL0}} +# CHECK: mrs x9, {{pmevtyper2_el0|PMEVTYPER2_EL0}} +# CHECK: mrs x9, {{pmevtyper3_el0|PMEVTYPER3_EL0}} +# CHECK: mrs x9, {{pmevtyper4_el0|PMEVTYPER4_EL0}} +# CHECK: mrs x9, {{pmevtyper5_el0|PMEVTYPER5_EL0}} +# CHECK: mrs x9, {{pmevtyper6_el0|PMEVTYPER6_EL0}} +# CHECK: mrs x9, {{pmevtyper7_el0|PMEVTYPER7_EL0}} +# CHECK: mrs x9, {{pmevtyper8_el0|PMEVTYPER8_EL0}} +# CHECK: mrs x9, {{pmevtyper9_el0|PMEVTYPER9_EL0}} +# CHECK: mrs x9, {{pmevtyper10_el0|PMEVTYPER10_EL0}} +# CHECK: mrs x9, {{pmevtyper11_el0|PMEVTYPER11_EL0}} +# CHECK: mrs x9, {{pmevtyper12_el0|PMEVTYPER12_EL0}} +# CHECK: mrs x9, {{pmevtyper13_el0|PMEVTYPER13_EL0}} +# CHECK: mrs x9, {{pmevtyper14_el0|PMEVTYPER14_EL0}} +# CHECK: mrs x9, {{pmevtyper15_el0|PMEVTYPER15_EL0}} +# CHECK: mrs x9, {{pmevtyper16_el0|PMEVTYPER16_EL0}} +# CHECK: mrs x9, {{pmevtyper17_el0|PMEVTYPER17_EL0}} +# CHECK: mrs x9, {{pmevtyper18_el0|PMEVTYPER18_EL0}} +# CHECK: mrs x9, {{pmevtyper19_el0|PMEVTYPER19_EL0}} +# CHECK: mrs x9, {{pmevtyper20_el0|PMEVTYPER20_EL0}} +# CHECK: mrs x9, {{pmevtyper21_el0|PMEVTYPER21_EL0}} +# CHECK: mrs x9, {{pmevtyper22_el0|PMEVTYPER22_EL0}} +# CHECK: mrs x9, {{pmevtyper23_el0|PMEVTYPER23_EL0}} +# CHECK: mrs x9, {{pmevtyper24_el0|PMEVTYPER24_EL0}} +# CHECK: mrs x9, {{pmevtyper25_el0|PMEVTYPER25_EL0}} +# CHECK: mrs x9, {{pmevtyper26_el0|PMEVTYPER26_EL0}} +# CHECK: mrs x9, {{pmevtyper27_el0|PMEVTYPER27_EL0}} +# CHECK: mrs x9, {{pmevtyper28_el0|PMEVTYPER28_EL0}} +# CHECK: mrs x9, {{pmevtyper29_el0|PMEVTYPER29_EL0}} +# CHECK: mrs x9, {{pmevtyper30_el0|PMEVTYPER30_EL0}} 0xc 0x0 0x12 0xd5 0x4c 0x0 0x10 0xd5 @@ -4147,10 +4148,10 @@ 0xa9 0xef 0x3b 0xd5 0xc9 0xef 0x3b 0xd5 -# CHECK: mrs x12, s3_7_c15_c1_5 -# CHECK: mrs x13, s3_2_c11_c15_7 -# CHECK: msr s3_0_c15_c0_0, x12 -# CHECK: msr s3_7_c11_c13_7, x5 +# CHECK: mrs x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}} +# CHECK: mrs x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}} +# CHECK: msr {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12 +# CHECK: msr {{s3_7_c11_c13_7|S3_7_C11_C13_7}}, x5 0xac 0xf1 0x3f 0xd5 0xed 0xbf 0x3a 0xd5 0x0c 0xf0 0x18 0xd5 diff --git a/test/MC/Disassembler/AArch64/basic-a64-undefined.txt b/test/MC/Disassembler/AArch64/basic-a64-undefined.txt index a17579c..968a454 100644 --- a/test/MC/Disassembler/AArch64/basic-a64-undefined.txt +++ b/test/MC/Disassembler/AArch64/basic-a64-undefined.txt @@ -1,43 +1,66 @@ -# These spawn another process so they're rather expensive. Not many. +# RUN: not llvm-mc -disassemble -triple=aarch64 %s 2> %t +# RUN: FileCheck %s < %t +# RUN: not llvm-mc -disassemble -triple=arm64 %s 2> %t +# RUN: FileCheck %s < %t # Instructions notionally in the add/sub (extended register) sheet, but with # invalid shift amount or "opt" field. -# RUN: echo "0x00 0x10 0xa0 0x0b" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x00 0x10 0x60 0x0b" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x00 0x14 0x20 0x0b" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0x00 0x10 0xa0 0x0b] +[0x00 0x10 0x60 0x0b] +[0x00 0x14 0x20 0x0b] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding # Instructions notionally in the add/sub (immediate) sheet, but with # invalid "shift" field. -# RUN: echo "0xdf 0x3 0x80 0x91" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0xed 0x8e 0xc4 0x31" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x62 0xfc 0xbf 0x11" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x3 0xff 0xff 0x91" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0xdf 0x3 0x80 0x91] +[0xed 0x8e 0xc4 0x31] +[0x62 0xfc 0xbf 0x11] +[0x3 0xff 0xff 0x91] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding # Instructions notionally in the load/store (unsigned immediate) sheet. # Only unallocated (int-register) variants are: opc=0b11, size=0b10, 0b11 -# RUN: echo "0xd7 0xfc 0xff 0xb9" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0xd7 0xfc 0xcf 0xf9" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0xd7 0xfc 0xff 0xb9] +[0xd7 0xfc 0xcf 0xf9] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding # Instructions notionally in the floating-point <-> fixed-point conversion # Scale field is 64-<imm> and <imm> should be 1-32 for a 32-bit int register. -# RUN: echo "0x23 0x01 0x18 0x1e" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x23 0x25 0x42 0x1e" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0x23 0x01 0x18 0x1e] +[0x23 0x25 0x42 0x1e] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding # Instructions notionally in the logical (shifted register) sheet, but with out # of range shift: w-registers can only have 0-31. -# RUN: echo "0x00 0x80 0x00 0x0a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0x00 0x80 0x00 0x0a] +# CHECK: invalid instruction encoding # Instructions notionally in the move wide (immediate) sheet, but with out # of range shift: w-registers can only have 0 or 16. -# RUN: echo "0x00 0x00 0xc0 0x12" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x12 0x34 0xe0 0x52" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s - -# Data-processing instructions are undefined when S=1 and for the 0b0000111 value in opcode:sf -# RUN: echo "0x00 0x00 0xc0 0x5f" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x56 0x0c 0xc0 0x5a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +[0x00 0x00 0xc0 0x12] +[0x12 0x34 0xe0 0x52] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding -# Data-processing instructions (2 source) are undefined for a value of 0001xx:0:x or 0011xx:0:x for opcode:S:sf -# RUN: echo "0x00 0x30 0xc1 0x1a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x00 0x10 0xc1 0x1a" | llvm-mc -triple=aarch64 -disassemble 2>&1 | FileCheck %s +# Data-processing instructions are undefined when S=1 and for the 0b0000111 +# value in opcode:sf +[0x00 0x00 0xc0 0x5f] +[0x56 0x0c 0xc0 0x5a] +# CHECK: invalid instruction encoding +# CHECK: invalid instruction encoding +# Data-processing instructions (2 source) are undefined for a value of +# 0001xx:0:x or 0011xx:0:x for opcode:S:sf +[0x00 0x30 0xc1 0x1a] +[0x00 0x10 0xc1 0x1a] +# CHECK: invalid instruction encoding # CHECK: invalid instruction encoding + + diff --git a/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt b/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt index 5363863..2fccccb 100644 --- a/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt +++ b/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s #------------------------------------------------------------------------------ # Load-store exclusive diff --git a/test/MC/Disassembler/AArch64/gicv3-regs.txt b/test/MC/Disassembler/AArch64/gicv3-regs.txt index 4351f64..851e83d 100644 --- a/test/MC/Disassembler/AArch64/gicv3-regs.txt +++ b/test/MC/Disassembler/AArch64/gicv3-regs.txt @@ -1,222 +1,223 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-none-linux-gnu -disassemble < %s | FileCheck %s 0x8 0xcc 0x38 0xd5 -# CHECK: mrs x8, icc_iar1_el1 +# CHECK: mrs x8, {{icc_iar1_el1|ICC_IAR1_EL1}} 0x1a 0xc8 0x38 0xd5 -# CHECK: mrs x26, icc_iar0_el1 +# CHECK: mrs x26, {{icc_iar0_el1|ICC_IAR0_EL1}} 0x42 0xcc 0x38 0xd5 -# CHECK: mrs x2, icc_hppir1_el1 +# CHECK: mrs x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}} 0x51 0xc8 0x38 0xd5 -# CHECK: mrs x17, icc_hppir0_el1 +# CHECK: mrs x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}} 0x7d 0xcb 0x38 0xd5 -# CHECK: mrs x29, icc_rpr_el1 +# CHECK: mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}} 0x24 0xcb 0x3c 0xd5 -# CHECK: mrs x4, ich_vtr_el2 +# CHECK: mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}} 0x78 0xcb 0x3c 0xd5 -# CHECK: mrs x24, ich_eisr_el2 +# CHECK: mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}} 0xa9 0xcb 0x3c 0xd5 -# CHECK: mrs x9, ich_elsr_el2 +# CHECK: mrs x9, {{ich_elsr_el2|ICH_ELSR_EL2}} 0x78 0xcc 0x38 0xd5 -# CHECK: mrs x24, icc_bpr1_el1 +# CHECK: mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}} 0x6e 0xc8 0x38 0xd5 -# CHECK: mrs x14, icc_bpr0_el1 +# CHECK: mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}} 0x13 0x46 0x38 0xd5 -# CHECK: mrs x19, icc_pmr_el1 +# CHECK: mrs x19, {{icc_pmr_el1|ICC_PMR_EL1}} 0x97 0xcc 0x38 0xd5 -# CHECK: mrs x23, icc_ctlr_el1 +# CHECK: mrs x23, {{icc_ctlr_el1|ICC_CTLR_EL1}} 0x94 0xcc 0x3e 0xd5 -# CHECK: mrs x20, icc_ctlr_el3 +# CHECK: mrs x20, {{icc_ctlr_el3|ICC_CTLR_EL3}} 0xbc 0xcc 0x38 0xd5 -# CHECK: mrs x28, icc_sre_el1 +# CHECK: mrs x28, {{icc_sre_el1|ICC_SRE_EL1}} 0xb9 0xc9 0x3c 0xd5 -# CHECK: mrs x25, icc_sre_el2 +# CHECK: mrs x25, {{icc_sre_el2|ICC_SRE_EL2}} 0xa8 0xcc 0x3e 0xd5 -# CHECK: mrs x8, icc_sre_el3 +# CHECK: mrs x8, {{icc_sre_el3|ICC_SRE_EL3}} 0xd6 0xcc 0x38 0xd5 -# CHECK: mrs x22, icc_igrpen0_el1 +# CHECK: mrs x22, {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}} 0xe5 0xcc 0x38 0xd5 -# CHECK: mrs x5, icc_igrpen1_el1 +# CHECK: mrs x5, {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}} 0xe7 0xcc 0x3e 0xd5 -# CHECK: mrs x7, icc_igrpen1_el3 +# CHECK: mrs x7, {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}} 0x16 0xcd 0x38 0xd5 -# CHECK: mrs x22, icc_seien_el1 +# CHECK: mrs x22, {{icc_seien_el1|ICC_SEIEN_EL1}} 0x84 0xc8 0x38 0xd5 -# CHECK: mrs x4, icc_ap0r0_el1 +# CHECK: mrs x4, {{icc_ap0r0_el1|ICC_AP0R0_EL1}} 0xab 0xc8 0x38 0xd5 -# CHECK: mrs x11, icc_ap0r1_el1 +# CHECK: mrs x11, {{icc_ap0r1_el1|ICC_AP0R1_EL1}} 0xdb 0xc8 0x38 0xd5 -# CHECK: mrs x27, icc_ap0r2_el1 +# CHECK: mrs x27, {{icc_ap0r2_el1|ICC_AP0R2_EL1}} 0xf5 0xc8 0x38 0xd5 -# CHECK: mrs x21, icc_ap0r3_el1 +# CHECK: mrs x21, {{icc_ap0r3_el1|ICC_AP0R3_EL1}} 0x2 0xc9 0x38 0xd5 -# CHECK: mrs x2, icc_ap1r0_el1 +# CHECK: mrs x2, {{icc_ap1r0_el1|ICC_AP1R0_EL1}} 0x35 0xc9 0x38 0xd5 -# CHECK: mrs x21, icc_ap1r1_el1 +# CHECK: mrs x21, {{icc_ap1r1_el1|ICC_AP1R1_EL1}} 0x4a 0xc9 0x38 0xd5 -# CHECK: mrs x10, icc_ap1r2_el1 +# CHECK: mrs x10, {{icc_ap1r2_el1|ICC_AP1R2_EL1}} 0x7b 0xc9 0x38 0xd5 -# CHECK: mrs x27, icc_ap1r3_el1 +# CHECK: mrs x27, {{icc_ap1r3_el1|ICC_AP1R3_EL1}} 0x14 0xc8 0x3c 0xd5 -# CHECK: mrs x20, ich_ap0r0_el2 +# CHECK: mrs x20, {{ich_ap0r0_el2|ICH_AP0R0_EL2}} 0x35 0xc8 0x3c 0xd5 -# CHECK: mrs x21, ich_ap0r1_el2 +# CHECK: mrs x21, {{ich_ap0r1_el2|ICH_AP0R1_EL2}} 0x45 0xc8 0x3c 0xd5 -# CHECK: mrs x5, ich_ap0r2_el2 +# CHECK: mrs x5, {{ich_ap0r2_el2|ICH_AP0R2_EL2}} 0x64 0xc8 0x3c 0xd5 -# CHECK: mrs x4, ich_ap0r3_el2 +# CHECK: mrs x4, {{ich_ap0r3_el2|ICH_AP0R3_EL2}} 0xf 0xc9 0x3c 0xd5 -# CHECK: mrs x15, ich_ap1r0_el2 +# CHECK: mrs x15, {{ich_ap1r0_el2|ICH_AP1R0_EL2}} 0x2c 0xc9 0x3c 0xd5 -# CHECK: mrs x12, ich_ap1r1_el2 +# CHECK: mrs x12, {{ich_ap1r1_el2|ICH_AP1R1_EL2}} 0x5b 0xc9 0x3c 0xd5 -# CHECK: mrs x27, ich_ap1r2_el2 +# CHECK: mrs x27, {{ich_ap1r2_el2|ICH_AP1R2_EL2}} 0x74 0xc9 0x3c 0xd5 -# CHECK: mrs x20, ich_ap1r3_el2 +# CHECK: mrs x20, {{ich_ap1r3_el2|ICH_AP1R3_EL2}} 0xa 0xcb 0x3c 0xd5 -# CHECK: mrs x10, ich_hcr_el2 +# CHECK: mrs x10, {{ich_hcr_el2|ICH_HCR_EL2}} 0x5b 0xcb 0x3c 0xd5 -# CHECK: mrs x27, ich_misr_el2 +# CHECK: mrs x27, {{ich_misr_el2|ICH_MISR_EL2}} 0xe6 0xcb 0x3c 0xd5 -# CHECK: mrs x6, ich_vmcr_el2 +# CHECK: mrs x6, {{ich_vmcr_el2|ICH_VMCR_EL2}} 0x93 0xc9 0x3c 0xd5 -# CHECK: mrs x19, ich_vseir_el2 +# CHECK: mrs x19, {{ich_vseir_el2|ICH_VSEIR_EL2}} 0x3 0xcc 0x3c 0xd5 -# CHECK: mrs x3, ich_lr0_el2 +# CHECK: mrs x3, {{ich_lr0_el2|ICH_LR0_EL2}} 0x21 0xcc 0x3c 0xd5 -# CHECK: mrs x1, ich_lr1_el2 +# CHECK: mrs x1, {{ich_lr1_el2|ICH_LR1_EL2}} 0x56 0xcc 0x3c 0xd5 -# CHECK: mrs x22, ich_lr2_el2 +# CHECK: mrs x22, {{ich_lr2_el2|ICH_LR2_EL2}} 0x75 0xcc 0x3c 0xd5 -# CHECK: mrs x21, ich_lr3_el2 +# CHECK: mrs x21, {{ich_lr3_el2|ICH_LR3_EL2}} 0x86 0xcc 0x3c 0xd5 -# CHECK: mrs x6, ich_lr4_el2 +# CHECK: mrs x6, {{ich_lr4_el2|ICH_LR4_EL2}} 0xaa 0xcc 0x3c 0xd5 -# CHECK: mrs x10, ich_lr5_el2 +# CHECK: mrs x10, {{ich_lr5_el2|ICH_LR5_EL2}} 0xcb 0xcc 0x3c 0xd5 -# CHECK: mrs x11, ich_lr6_el2 +# CHECK: mrs x11, {{ich_lr6_el2|ICH_LR6_EL2}} 0xec 0xcc 0x3c 0xd5 -# CHECK: mrs x12, ich_lr7_el2 +# CHECK: mrs x12, {{ich_lr7_el2|ICH_LR7_EL2}} 0x0 0xcd 0x3c 0xd5 -# CHECK: mrs x0, ich_lr8_el2 +# CHECK: mrs x0, {{ich_lr8_el2|ICH_LR8_EL2}} 0x35 0xcd 0x3c 0xd5 -# CHECK: mrs x21, ich_lr9_el2 +# CHECK: mrs x21, {{ich_lr9_el2|ICH_LR9_EL2}} 0x4d 0xcd 0x3c 0xd5 -# CHECK: mrs x13, ich_lr10_el2 +# CHECK: mrs x13, {{ich_lr10_el2|ICH_LR10_EL2}} 0x7a 0xcd 0x3c 0xd5 -# CHECK: mrs x26, ich_lr11_el2 +# CHECK: mrs x26, {{ich_lr11_el2|ICH_LR11_EL2}} 0x81 0xcd 0x3c 0xd5 -# CHECK: mrs x1, ich_lr12_el2 +# CHECK: mrs x1, {{ich_lr12_el2|ICH_LR12_EL2}} 0xa8 0xcd 0x3c 0xd5 -# CHECK: mrs x8, ich_lr13_el2 +# CHECK: mrs x8, {{ich_lr13_el2|ICH_LR13_EL2}} 0xc2 0xcd 0x3c 0xd5 -# CHECK: mrs x2, ich_lr14_el2 +# CHECK: mrs x2, {{ich_lr14_el2|ICH_LR14_EL2}} 0xe8 0xcd 0x3c 0xd5 -# CHECK: mrs x8, ich_lr15_el2 +# CHECK: mrs x8, {{ich_lr15_el2|ICH_LR15_EL2}} 0x3b 0xcc 0x18 0xd5 -# CHECK: msr icc_eoir1_el1, x27 +# CHECK: msr {{icc_eoir1_el1|ICC_EOIR1_EL1}}, x27 0x25 0xc8 0x18 0xd5 -# CHECK: msr icc_eoir0_el1, x5 +# CHECK: msr {{icc_eoir0_el1|ICC_EOIR0_EL1}}, x5 0x2d 0xcb 0x18 0xd5 -# CHECK: msr icc_dir_el1, x13 +# CHECK: msr {{icc_dir_el1|ICC_DIR_EL1}}, x13 0xb5 0xcb 0x18 0xd5 -# CHECK: msr icc_sgi1r_el1, x21 +# CHECK: msr {{icc_sgi1r_el1|ICC_SGI1R_EL1}}, x21 0xd9 0xcb 0x18 0xd5 -# CHECK: msr icc_asgi1r_el1, x25 +# CHECK: msr {{icc_asgi1r_el1|ICC_ASGI1R_EL1}}, x25 0xfc 0xcb 0x18 0xd5 -# CHECK: msr icc_sgi0r_el1, x28 +# CHECK: msr {{icc_sgi0r_el1|ICC_SGI0R_EL1}}, x28 0x67 0xcc 0x18 0xd5 -# CHECK: msr icc_bpr1_el1, x7 +# CHECK: msr {{icc_bpr1_el1|ICC_BPR1_EL1}}, x7 0x69 0xc8 0x18 0xd5 -# CHECK: msr icc_bpr0_el1, x9 +# CHECK: msr {{icc_bpr0_el1|ICC_BPR0_EL1}}, x9 0x1d 0x46 0x18 0xd5 -# CHECK: msr icc_pmr_el1, x29 +# CHECK: msr {{icc_pmr_el1|ICC_PMR_EL1}}, x29 0x98 0xcc 0x18 0xd5 -# CHECK: msr icc_ctlr_el1, x24 +# CHECK: msr {{icc_ctlr_el1|ICC_CTLR_EL1}}, x24 0x80 0xcc 0x1e 0xd5 -# CHECK: msr icc_ctlr_el3, x0 +# CHECK: msr {{icc_ctlr_el3|ICC_CTLR_EL3}}, x0 0xa2 0xcc 0x18 0xd5 -# CHECK: msr icc_sre_el1, x2 +# CHECK: msr {{icc_sre_el1|ICC_SRE_EL1}}, x2 0xa5 0xc9 0x1c 0xd5 -# CHECK: msr icc_sre_el2, x5 +# CHECK: msr {{icc_sre_el2|ICC_SRE_EL2}}, x5 0xaa 0xcc 0x1e 0xd5 -# CHECK: msr icc_sre_el3, x10 +# CHECK: msr {{icc_sre_el3|ICC_SRE_EL3}}, x10 0xd6 0xcc 0x18 0xd5 -# CHECK: msr icc_igrpen0_el1, x22 +# CHECK: msr {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x22 0xeb 0xcc 0x18 0xd5 -# CHECK: msr icc_igrpen1_el1, x11 +# CHECK: msr {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}, x11 0xe8 0xcc 0x1e 0xd5 -# CHECK: msr icc_igrpen1_el3, x8 +# CHECK: msr {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}, x8 0x4 0xcd 0x18 0xd5 -# CHECK: msr icc_seien_el1, x4 +# CHECK: msr {{icc_seien_el1|ICC_SEIEN_EL1}}, x4 0x9b 0xc8 0x18 0xd5 -# CHECK: msr icc_ap0r0_el1, x27 +# CHECK: msr {{icc_ap0r0_el1|ICC_AP0R0_EL1}}, x27 0xa5 0xc8 0x18 0xd5 -# CHECK: msr icc_ap0r1_el1, x5 +# CHECK: msr {{icc_ap0r1_el1|ICC_AP0R1_EL1}}, x5 0xd4 0xc8 0x18 0xd5 -# CHECK: msr icc_ap0r2_el1, x20 +# CHECK: msr {{icc_ap0r2_el1|ICC_AP0R2_EL1}}, x20 0xe0 0xc8 0x18 0xd5 -# CHECK: msr icc_ap0r3_el1, x0 +# CHECK: msr {{icc_ap0r3_el1|ICC_AP0R3_EL1}}, x0 0x2 0xc9 0x18 0xd5 -# CHECK: msr icc_ap1r0_el1, x2 +# CHECK: msr {{icc_ap1r0_el1|ICC_AP1R0_EL1}}, x2 0x3d 0xc9 0x18 0xd5 -# CHECK: msr icc_ap1r1_el1, x29 +# CHECK: msr {{icc_ap1r1_el1|ICC_AP1R1_EL1}}, x29 0x57 0xc9 0x18 0xd5 -# CHECK: msr icc_ap1r2_el1, x23 +# CHECK: msr {{icc_ap1r2_el1|ICC_AP1R2_EL1}}, x23 0x6b 0xc9 0x18 0xd5 -# CHECK: msr icc_ap1r3_el1, x11 +# CHECK: msr {{icc_ap1r3_el1|ICC_AP1R3_EL1}}, x11 0x2 0xc8 0x1c 0xd5 -# CHECK: msr ich_ap0r0_el2, x2 +# CHECK: msr {{ich_ap0r0_el2|ICH_AP0R0_EL2}}, x2 0x3b 0xc8 0x1c 0xd5 -# CHECK: msr ich_ap0r1_el2, x27 +# CHECK: msr {{ich_ap0r1_el2|ICH_AP0R1_EL2}}, x27 0x47 0xc8 0x1c 0xd5 -# CHECK: msr ich_ap0r2_el2, x7 +# CHECK: msr {{ich_ap0r2_el2|ICH_AP0R2_EL2}}, x7 0x61 0xc8 0x1c 0xd5 -# CHECK: msr ich_ap0r3_el2, x1 +# CHECK: msr {{ich_ap0r3_el2|ICH_AP0R3_EL2}}, x1 0x7 0xc9 0x1c 0xd5 -# CHECK: msr ich_ap1r0_el2, x7 +# CHECK: msr {{ich_ap1r0_el2|ICH_AP1R0_EL2}}, x7 0x2c 0xc9 0x1c 0xd5 -# CHECK: msr ich_ap1r1_el2, x12 +# CHECK: msr {{ich_ap1r1_el2|ICH_AP1R1_EL2}}, x12 0x4e 0xc9 0x1c 0xd5 -# CHECK: msr ich_ap1r2_el2, x14 +# CHECK: msr {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x14 0x6d 0xc9 0x1c 0xd5 -# CHECK: msr ich_ap1r3_el2, x13 +# CHECK: msr {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x13 0x1 0xcb 0x1c 0xd5 -# CHECK: msr ich_hcr_el2, x1 +# CHECK: msr {{ich_hcr_el2|ICH_HCR_EL2}}, x1 0x4a 0xcb 0x1c 0xd5 -# CHECK: msr ich_misr_el2, x10 +# CHECK: msr {{ich_misr_el2|ICH_MISR_EL2}}, x10 0xf8 0xcb 0x1c 0xd5 -# CHECK: msr ich_vmcr_el2, x24 +# CHECK: msr {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24 0x9d 0xc9 0x1c 0xd5 -# CHECK: msr ich_vseir_el2, x29 +# CHECK: msr {{ich_vseir_el2|ICH_VSEIR_EL2}}, x29 0x1a 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr0_el2, x26 +# CHECK: msr {{ich_lr0_el2|ICH_LR0_EL2}}, x26 0x29 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr1_el2, x9 +# CHECK: msr {{ich_lr1_el2|ICH_LR1_EL2}}, x9 0x52 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr2_el2, x18 +# CHECK: msr {{ich_lr2_el2|ICH_LR2_EL2}}, x18 0x7a 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr3_el2, x26 +# CHECK: msr {{ich_lr3_el2|ICH_LR3_EL2}}, x26 0x96 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr4_el2, x22 +# CHECK: msr {{ich_lr4_el2|ICH_LR4_EL2}}, x22 0xba 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr5_el2, x26 +# CHECK: msr {{ich_lr5_el2|ICH_LR5_EL2}}, x26 0xdb 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr6_el2, x27 +# CHECK: msr {{ich_lr6_el2|ICH_LR6_EL2}}, x27 0xe8 0xcc 0x1c 0xd5 -# CHECK: msr ich_lr7_el2, x8 +# CHECK: msr {{ich_lr7_el2|ICH_LR7_EL2}}, x8 0x11 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr8_el2, x17 +# CHECK: msr {{ich_lr8_el2|ICH_LR8_EL2}}, x17 0x33 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr9_el2, x19 +# CHECK: msr {{ich_lr9_el2|ICH_LR9_EL2}}, x19 0x51 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr10_el2, x17 +# CHECK: msr {{ich_lr10_el2|ICH_LR10_EL2}}, x17 0x65 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr11_el2, x5 +# CHECK: msr {{ich_lr11_el2|ICH_LR11_EL2}}, x5 0x9d 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr12_el2, x29 +# CHECK: msr {{ich_lr12_el2|ICH_LR12_EL2}}, x29 0xa2 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr13_el2, x2 +# CHECK: msr {{ich_lr13_el2|ICH_LR13_EL2}}, x2 0xcd 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr14_el2, x13 +# CHECK: msr {{ich_lr14_el2|ICH_LR14_EL2}}, x13 0xfb 0xcd 0x1c 0xd5 -# CHECK: msr ich_lr15_el2, x27 +# CHECK: msr {{ich_lr15_el2|ICH_LR15_EL2}}, x27 diff --git a/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt b/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt index 7ff495f..3c443a9 100644 --- a/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt +++ b/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=arm64 -disassemble < %s 2>&1 | FileCheck %s # Stores are OK. 0xe0 0x83 0x00 0xa9 diff --git a/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt b/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt index 637ebdb..6ba33ad 100644 --- a/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt +++ b/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s # None of these instructions should be classified as unpredictable: diff --git a/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt b/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt index f52d37f..1915340 100644 --- a/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt +++ b/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s # None of these instructions should be classified as unpredictable: diff --git a/test/MC/Disassembler/AArch64/lit.local.cfg b/test/MC/Disassembler/AArch64/lit.local.cfg index 9a66a00..2c423d1 100644 --- a/test/MC/Disassembler/AArch64/lit.local.cfg +++ b/test/MC/Disassembler/AArch64/lit.local.cfg @@ -1,4 +1,4 @@ targets = set(config.root.targets_to_build.split()) -if not 'AArch64' in targets: +if 'AArch64' not in targets: config.unsupported = True diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt index 863730a..3590668 100644 --- a/test/MC/Disassembler/AArch64/neon-instructions.txt +++ b/test/MC/Disassembler/AArch64/neon-instructions.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # Vector Integer Add/Sub @@ -87,7 +88,7 @@ # Vector Bitwise OR - immedidate #------------------------------------------------------------------------------ # CHECK: movi v31.4s, #0xff, lsl #24 -# CHECK: mvni v0.2s, #0x0 +# CHECK: mvni v0.2s, #{{0x0|0}} # CHECK: bic v15.4h, #0xf, lsl #8 # CHECK: orr v16.8h, #0x1f 0xff 0x67 0x07 0x4f @@ -132,10 +133,8 @@ # Vector Move - register #------------------------------------------------------------------------------ -# FIXME: these should print as "mov", but TableGen can't handle it. - -# CHECK: orr v1.16b, v15.16b, v15.16b -# CHECK: orr v25.8b, v4.8b, v4.8b +# CHECK: mov v1.16b, v15.16b +# CHECK: mov v25.8b, v4.8b 0xe1 0x1d 0xaf 0x4e 0x99 0x1c 0xa4 0x0e @@ -246,31 +245,31 @@ #---------------------------------------------------------------------- # Vector Compare Mask Equal to Zero (Integer) #---------------------------------------------------------------------- -# CHECK: cmeq v31.16b, v15.16b, #0x0 +# CHECK: cmeq v31.16b, v15.16b, #{{0x0|0}} 0xff 0x99 0x20 0x4e #---------------------------------------------------------------------- # Vector Compare Mask Greater Than or Equal to Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmge v3.8b, v15.8b, #0x0 +# CHECK: cmge v3.8b, v15.8b, #{{0x0|0}} 0xe3 0x89 0x20 0x2e #---------------------------------------------------------------------- # Vector Compare Mask Greater Than Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmgt v22.2s, v9.2s, #0x0 +# CHECK: cmgt v22.2s, v9.2s, #{{0x0|0}} 0x36 0x89 0xa0 0x0e #---------------------------------------------------------------------- # Vector Compare Mask Less Than or Equal To Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmle v5.2d, v14.2d, #0x0 +# CHECK: cmle v5.2d, v14.2d, #{{0x0|0}} 0xc5 0x99 0xe0 0x6e #---------------------------------------------------------------------- # Vector Compare Mask Less Than Zero (Signed Integer) #---------------------------------------------------------------------- -# CHECK: cmlt v13.8h, v11.8h, #0x0 +# CHECK: cmlt v13.8h, v11.8h, #{{0x0|0}} 0x6d 0xa9 0x60 0x4e #---------------------------------------------------------------------- @@ -1559,7 +1558,7 @@ #---------------------------------------------------------------------- # Scalar Compare Bitwise Equal To Zero #---------------------------------------------------------------------- -# CHECK: cmeq d20, d21, #0x0 +# CHECK: cmeq d20, d21, #{{0x0|0}} 0xb4,0x9a,0xe0,0x5e #---------------------------------------------------------------------- @@ -1578,7 +1577,7 @@ #---------------------------------------------------------------------- # Scalar Compare Signed Greather Than Or Equal To Zero #---------------------------------------------------------------------- -# CHECK: cmge d20, d21, #0x0 +# CHECK: cmge d20, d21, #{{0x0|0}} 0xb4,0x8a,0xe0,0x7e #---------------------------------------------------------------------- @@ -1596,19 +1595,19 @@ #---------------------------------------------------------------------- # Scalar Compare Signed Greater Than Zero #---------------------------------------------------------------------- -# CHECK: cmgt d20, d21, #0x0 +# CHECK: cmgt d20, d21, #{{0x0|0}} 0xb4,0x8a,0xe0,0x5e #---------------------------------------------------------------------- # Scalar Compare Signed Less Than Or Equal To Zero #---------------------------------------------------------------------- -# CHECK: cmle d20, d21, #0x0 +# CHECK: cmle d20, d21, #{{0x0|0}} 0xb4,0x9a,0xe0,0x7e #---------------------------------------------------------------------- # Scalar Compare Less Than Zero #---------------------------------------------------------------------- -# CHECK: cmlt d20, d21, #0x0 +# CHECK: cmlt d20, d21, #{{0x0|0}} 0xb4,0xaa,0xe0,0x5e #---------------------------------------------------------------------- @@ -2008,34 +2007,34 @@ #---------------------------------------------------------------------- # Vector load/store multiple N-element structure #---------------------------------------------------------------------- -# CHECK: ld1 {v0.16b}, [x0] -# CHECK: ld1 {v15.8h, v16.8h}, [x15] -# CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp] -# CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +# CHECK: ld1 { v0.16b }, [x0] +# CHECK: ld1 { v15.8h, v16.8h }, [x15] +# CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp] +# CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] 0x00,0x70,0x40,0x4c 0xef,0xa5,0x40,0x4c 0xff,0x6b,0x40,0x4c 0x00,0x2c,0x40,0x4c -# CHECK: ld2 {v0.8b, v1.8b}, [x0] -# CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15] -# CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +# CHECK: ld2 { v0.8b, v1.8b }, [x0] +# CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15] +# CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] 0x00,0x80,0x40,0x0c 0xef,0x45,0x40,0x0c 0xff,0x0b,0x40,0x0c -# CHECK: st1 {v0.16b}, [x0] -# CHECK: st1 {v15.8h, v16.8h}, [x15] -# CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp] -# CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +# CHECK: st1 { v0.16b }, [x0] +# CHECK: st1 { v15.8h, v16.8h }, [x15] +# CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp] +# CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] 0x00,0x70,0x00,0x4c 0xef,0xa5,0x00,0x4c 0xff,0x6b,0x00,0x4c 0x00,0x2c,0x00,0x4c -# CHECK: st2 {v0.8b, v1.8b}, [x0] -# CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15] -# CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +# CHECK: st2 { v0.8b, v1.8b }, [x0] +# CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15] +# CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] 0x00,0x80,0x00,0x0c 0xef,0x45,0x00,0x0c 0xff,0x0b,0x00,0x0c @@ -2043,35 +2042,35 @@ #---------------------------------------------------------------------- # Vector load/store multiple N-element structure (post-index) #---------------------------------------------------------------------- -# CHECK: ld1 {v15.8h}, [x15], x2 -# CHECK: ld1 {v31.4s, v0.4s}, [sp], #32 -# CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 -# CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +# CHECK: ld1 { v15.8h }, [x15], x2 +# CHECK: ld1 { v31.4s, v0.4s }, [sp], #32 +# CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +# CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 0xef,0x75,0xc2,0x4c 0xff,0xab,0xdf,0x4c 0x00,0x6c,0xdf,0x4c 0x00,0x20,0xc3,0x0c -# CHECK: ld2 {v0.16b, v1.16b}, [x0], x1 -# CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 -# CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +# CHECK: ld2 { v0.16b, v1.16b }, [x0], x1 +# CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2 +# CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 0x00,0x80,0xc1,0x4c 0xef,0x45,0xc2,0x4c 0xff,0x0b,0xdf,0x4c -# CHECK: st1 {v15.8h}, [x15], x2 -# CHECK: st1 {v31.4s, v0.4s}, [sp], #32 -# CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 -# CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +# CHECK: st1 { v15.8h }, [x15], x2 +# CHECK: st1 { v31.4s, v0.4s }, [sp], #32 +# CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +# CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 0xef,0x75,0x82,0x4c 0xff,0xab,0x9f,0x4c 0x00,0x6c,0x9f,0x4c 0x00,0x20,0x83,0x0c -# CHECK: st2 {v0.16b, v1.16b}, [x0], x1 -# CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 -# CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +# CHECK: st2 { v0.16b, v1.16b }, [x0], x1 +# CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15], x2 +# CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 0x00,0x80,0x81,0x4c 0xef,0x45,0x82,0x4c 0xff,0x0b,0x9f,0x4c @@ -2080,14 +2079,14 @@ # Vector load single N-element structure to all lane of N # consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1r {v0.16b}, [x0] -# CHECK: ld1r {v15.8h}, [x15] -# CHECK: ld2r {v31.4s, v0.4s}, [sp] -# CHECK: ld2r {v0.2d, v1.2d}, [x0] -# CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0] -# CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15] -# CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] -# CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp] +# CHECK: ld1r { v0.16b }, [x0] +# CHECK: ld1r { v15.8h }, [x15] +# CHECK: ld2r { v31.4s, v0.4s }, [sp] +# CHECK: ld2r { v0.2d, v1.2d }, [x0] +# CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0] +# CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15] +# CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] +# CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp] 0x00,0xc0,0x40,0x4d 0xef,0xc5,0x40,0x4d 0xff,0xcb,0x60,0x4d @@ -2101,14 +2100,14 @@ # Vector load/store single N-element structure to/from one lane of N # consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1 {v0.b}[9], [x0] -# CHECK: ld2 {v15.h, v16.h}[7], [x15] -# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp] -# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] -# CHECK: st1 {v0.d}[1], [x0] -# CHECK: st2 {v31.s, v0.s}[3], [sp] -# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15] -# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] +# CHECK: ld1 { v0.b }[9], [x0] +# CHECK: ld2 { v15.h, v16.h }[7], [x15] +# CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp] +# CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] +# CHECK: st1 { v0.d }[1], [x0] +# CHECK: st2 { v31.s, v0.s }[3], [sp] +# CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15] +# CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] 0x00,0x04,0x40,0x4d 0xef,0x59,0x60,0x4d 0xff,0xb3,0x40,0x4d @@ -2122,14 +2121,14 @@ # Post-index of vector load single N-element structure to all lane of N # consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1r {v0.16b}, [x0], #1 -# CHECK: ld1r {v15.8h}, [x15], #2 -# CHECK: ld2r {v31.4s, v0.4s}, [sp], #8 -# CHECK: ld2r {v0.2d, v1.2d}, [x0], #16 -# CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3 -# CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6 -# CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30 -# CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7 +# CHECK: ld1r { v0.16b }, [x0], #1 +# CHECK: ld1r { v15.8h }, [x15], #2 +# CHECK: ld2r { v31.4s, v0.4s }, [sp], #8 +# CHECK: ld2r { v0.2d, v1.2d }, [x0], #16 +# CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3 +# CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6 +# CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30 +# CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7 0x00,0xc0,0xdf,0x4d 0xef,0xc5,0xdf,0x4d 0xff,0xcb,0xff,0x4d @@ -2143,15 +2142,15 @@ # Post-index of vector load/store single N-element structure to/from # one lane of N consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1 {v0.b}[9], [x0], #1 -# CHECK: ld2 {v15.h, v16.h}[7], [x15], #4 -# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3 -# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 -# CHECK: ld4 {v0.h, v1.h, v2.h, v3.h}[7], [x0], x0 -# CHECK: st1 {v0.d}[1], [x0], #8 -# CHECK: st2 {v31.s, v0.s}[3], [sp], #8 -# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6 -# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 +# CHECK: ld1 { v0.b }[9], [x0], #1 +# CHECK: ld2 { v15.h, v16.h }[7], [x15], #4 +# CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp], x3 +# CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 +# CHECK: ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0 +# CHECK: st1 { v0.d }[1], [x0], #8 +# CHECK: st2 { v31.s, v0.s }[3], [sp], #8 +# CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15], #6 +# CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 0x00,0x04,0xdf,0x4d 0xef,0x59,0xff,0x4d 0xff,0xb3,0xc3,0x4d @@ -2167,8 +2166,8 @@ #---------------------------------------------------------------------- 0x20,0x18,0x02,0x2e 0x20,0x18,0x02,0x6e -# CHECK: ext v0.8b, v1.8b, v2.8b, #0x3 -# CHECK: ext v0.16b, v1.16b, v2.16b, #0x3 +# CHECK: ext v0.8b, v1.8b, v2.8b, #{{0x3|3}} +# CHECK: ext v0.16b, v1.16b, v2.16b, #{{0x3|3}} #---------------------------------------------------------------------- # unzip with 3 same vectors to get primary result @@ -2481,10 +2480,10 @@ #---------------------------------------------------------------------- #Duplicate element (scalar) #---------------------------------------------------------------------- -# CHECK: dup b0, v0.b[15] -# CHECK: dup h2, v31.h[5] -# CHECK: dup s17, v2.s[2] -# CHECK: dup d6, v12.d[1] +# CHECK: {{dup|mov}} b0, v0.b[15] +# CHECK: {{dup|mov}} h2, v31.h[5] +# CHECK: {{dup|mov}} s17, v2.s[2] +# CHECK: {{dup|mov}} d6, v12.d[1] 0x00 0x04 0x1f 0x5e 0xe2 0x07 0x16 0x5e 0x51 0x04 0x14 0x5e @@ -2497,37 +2496,37 @@ 0xf0,0x23,0x02,0x0e 0x20,0x40,0x02,0x0e 0xf0,0x62,0x02,0x0e -# CHECK: tbl v0.8b, {v1.16b}, v2.8b -# CHECK: tbl v16.8b, {v31.16b, v0.16b}, v2.8b -# CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b -# CHECK: tbl v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b +# CHECK: tbl v0.8b, { v1.16b }, v2.8b +# CHECK: tbl v16.8b, { v31.16b, v0.16b }, v2.8b +# CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b +# CHECK: tbl v16.8b, { v23.16b, v24.16b, v25.16b, v26.16b }, v2.8b 0x20,0x00,0x02,0x4e 0xf0,0x23,0x02,0x4e 0x20,0x40,0x02,0x4e 0xe0,0x63,0x02,0x4e -# CHECK: tbl v0.16b, {v1.16b}, v2.16b -# CHECK: tbl v16.16b, {v31.16b, v0.16b}, v2.16b -# CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b -# CHECK: tbl v0.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b +# CHECK: tbl v0.16b, { v1.16b }, v2.16b +# CHECK: tbl v16.16b, { v31.16b, v0.16b }, v2.16b +# CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b +# CHECK: tbl v0.16b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.16b 0x20,0x10,0x02,0x0e 0xf0,0x33,0x02,0x0e 0x20,0x50,0x02,0x0e 0xf0,0x72,0x02,0x0e -# CHECK: tbx v0.8b, {v1.16b}, v2.8b -# CHECK: tbx v16.8b, {v31.16b, v0.16b}, v2.8b -# CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b -# CHECK: tbx v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b +# CHECK: tbx v0.8b, { v1.16b }, v2.8b +# CHECK: tbx v16.8b, { v31.16b, v0.16b }, v2.8b +# CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b +# CHECK: tbx v16.8b, { v23.16b, v24.16b, v25.16b, v26.16b }, v2.8b 0x20,0x10,0x02,0x4e 0xf0,0x33,0x02,0x4e 0x20,0x50,0x02,0x4e 0xf0,0x73,0x02,0x4e -# CHECK: tbx v0.16b, {v1.16b}, v2.16b -# CHECK: tbx v16.16b, {v31.16b, v0.16b}, v2.16b -# CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b -# CHECK: tbx v16.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b +# CHECK: tbx v0.16b, { v1.16b }, v2.16b +# CHECK: tbx v16.16b, { v31.16b, v0.16b }, v2.16b +# CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b +# CHECK: tbx v16.16b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.16b #---------------------------------------------------------------------- # Scalar Floating-point Convert To Lower Precision Narrow, Rounding To diff --git a/test/MC/Disassembler/AArch64/trace-regs.txt b/test/MC/Disassembler/AArch64/trace-regs.txt index 10c5937..43171e3 100644 --- a/test/MC/Disassembler/AArch64/trace-regs.txt +++ b/test/MC/Disassembler/AArch64/trace-regs.txt @@ -1,736 +1,737 @@ # RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple arm64-none-linux-gnu -disassemble < %s | FileCheck %s 0x8 0x3 0x31 0xd5 -# CHECK: mrs x8, trcstatr +# CHECK: mrs x8, {{trcstatr|TRCSTATR}} 0xc9 0x0 0x31 0xd5 -# CHECK: mrs x9, trcidr8 +# CHECK: mrs x9, {{trcidr8|TRCIDR8}} 0xcb 0x1 0x31 0xd5 -# CHECK: mrs x11, trcidr9 +# CHECK: mrs x11, {{trcidr9|TRCIDR9}} 0xd9 0x2 0x31 0xd5 -# CHECK: mrs x25, trcidr10 +# CHECK: mrs x25, {{trcidr10|TRCIDR10}} 0xc7 0x3 0x31 0xd5 -# CHECK: mrs x7, trcidr11 +# CHECK: mrs x7, {{trcidr11|TRCIDR11}} 0xc7 0x4 0x31 0xd5 -# CHECK: mrs x7, trcidr12 +# CHECK: mrs x7, {{trcidr12|TRCIDR12}} 0xc6 0x5 0x31 0xd5 -# CHECK: mrs x6, trcidr13 +# CHECK: mrs x6, {{trcidr13|TRCIDR13}} 0xfb 0x8 0x31 0xd5 -# CHECK: mrs x27, trcidr0 +# CHECK: mrs x27, {{trcidr0|TRCIDR0}} 0xfd 0x9 0x31 0xd5 -# CHECK: mrs x29, trcidr1 +# CHECK: mrs x29, {{trcidr1|TRCIDR1}} 0xe4 0xa 0x31 0xd5 -# CHECK: mrs x4, trcidr2 +# CHECK: mrs x4, {{trcidr2|TRCIDR2}} 0xe8 0xb 0x31 0xd5 -# CHECK: mrs x8, trcidr3 +# CHECK: mrs x8, {{trcidr3|TRCIDR3}} 0xef 0xc 0x31 0xd5 -# CHECK: mrs x15, trcidr4 +# CHECK: mrs x15, {{trcidr4|TRCIDR4}} 0xf4 0xd 0x31 0xd5 -# CHECK: mrs x20, trcidr5 +# CHECK: mrs x20, {{trcidr5|TRCIDR5}} 0xe6 0xe 0x31 0xd5 -# CHECK: mrs x6, trcidr6 +# CHECK: mrs x6, {{trcidr6|TRCIDR6}} 0xe6 0xf 0x31 0xd5 -# CHECK: mrs x6, trcidr7 +# CHECK: mrs x6, {{trcidr7|TRCIDR7}} 0x98 0x11 0x31 0xd5 -# CHECK: mrs x24, trcoslsr +# CHECK: mrs x24, {{trcoslsr|TRCOSLSR}} 0x92 0x15 0x31 0xd5 -# CHECK: mrs x18, trcpdsr +# CHECK: mrs x18, {{trcpdsr|TRCPDSR}} 0xdc 0x7a 0x31 0xd5 -# CHECK: mrs x28, trcdevaff0 +# CHECK: mrs x28, {{trcdevaff0|TRCDEVAFF0}} 0xc5 0x7b 0x31 0xd5 -# CHECK: mrs x5, trcdevaff1 +# CHECK: mrs x5, {{trcdevaff1|TRCDEVAFF1}} 0xc5 0x7d 0x31 0xd5 -# CHECK: mrs x5, trclsr +# CHECK: mrs x5, {{trclsr|TRCLSR}} 0xcb 0x7e 0x31 0xd5 -# CHECK: mrs x11, trcauthstatus +# CHECK: mrs x11, {{trcauthstatus|TRCAUTHSTATUS}} 0xcd 0x7f 0x31 0xd5 -# CHECK: mrs x13, trcdevarch +# CHECK: mrs x13, {{trcdevarch|TRCDEVARCH}} 0xf2 0x72 0x31 0xd5 -# CHECK: mrs x18, trcdevid +# CHECK: mrs x18, {{trcdevid|TRCDEVID}} 0xf6 0x73 0x31 0xd5 -# CHECK: mrs x22, trcdevtype +# CHECK: mrs x22, {{trcdevtype|TRCDEVTYPE}} 0xee 0x74 0x31 0xd5 -# CHECK: mrs x14, trcpidr4 +# CHECK: mrs x14, {{trcpidr4|TRCPIDR4}} 0xe5 0x75 0x31 0xd5 -# CHECK: mrs x5, trcpidr5 +# CHECK: mrs x5, {{trcpidr5|TRCPIDR5}} 0xe5 0x76 0x31 0xd5 -# CHECK: mrs x5, trcpidr6 +# CHECK: mrs x5, {{trcpidr6|TRCPIDR6}} 0xe9 0x77 0x31 0xd5 -# CHECK: mrs x9, trcpidr7 +# CHECK: mrs x9, {{trcpidr7|TRCPIDR7}} 0xef 0x78 0x31 0xd5 -# CHECK: mrs x15, trcpidr0 +# CHECK: mrs x15, {{trcpidr0|TRCPIDR0}} 0xe6 0x79 0x31 0xd5 -# CHECK: mrs x6, trcpidr1 +# CHECK: mrs x6, {{trcpidr1|TRCPIDR1}} 0xeb 0x7a 0x31 0xd5 -# CHECK: mrs x11, trcpidr2 +# CHECK: mrs x11, {{trcpidr2|TRCPIDR2}} 0xf4 0x7b 0x31 0xd5 -# CHECK: mrs x20, trcpidr3 +# CHECK: mrs x20, {{trcpidr3|TRCPIDR3}} 0xf1 0x7c 0x31 0xd5 -# CHECK: mrs x17, trccidr0 +# CHECK: mrs x17, {{trccidr0|TRCCIDR0}} 0xe2 0x7d 0x31 0xd5 -# CHECK: mrs x2, trccidr1 +# CHECK: mrs x2, {{trccidr1|TRCCIDR1}} 0xf4 0x7e 0x31 0xd5 -# CHECK: mrs x20, trccidr2 +# CHECK: mrs x20, {{trccidr2|TRCCIDR2}} 0xe4 0x7f 0x31 0xd5 -# CHECK: mrs x4, trccidr3 +# CHECK: mrs x4, {{trccidr3|TRCCIDR3}} 0xb 0x1 0x31 0xd5 -# CHECK: mrs x11, trcprgctlr +# CHECK: mrs x11, {{trcprgctlr|TRCPRGCTLR}} 0x17 0x2 0x31 0xd5 -# CHECK: mrs x23, trcprocselr +# CHECK: mrs x23, {{trcprocselr|TRCPROCSELR}} 0xd 0x4 0x31 0xd5 -# CHECK: mrs x13, trcconfigr +# CHECK: mrs x13, {{trcconfigr|TRCCONFIGR}} 0x17 0x6 0x31 0xd5 -# CHECK: mrs x23, trcauxctlr +# CHECK: mrs x23, {{trcauxctlr|TRCAUXCTLR}} 0x9 0x8 0x31 0xd5 -# CHECK: mrs x9, trceventctl0r +# CHECK: mrs x9, {{trceventctl0r|TRCEVENTCTL0R}} 0x10 0x9 0x31 0xd5 -# CHECK: mrs x16, trceventctl1r +# CHECK: mrs x16, {{trceventctl1r|TRCEVENTCTL1R}} 0x4 0xb 0x31 0xd5 -# CHECK: mrs x4, trcstallctlr +# CHECK: mrs x4, {{trcstallctlr|TRCSTALLCTLR}} 0xe 0xc 0x31 0xd5 -# CHECK: mrs x14, trctsctlr +# CHECK: mrs x14, {{trctsctlr|TRCTSCTLR}} 0x18 0xd 0x31 0xd5 -# CHECK: mrs x24, trcsyncpr +# CHECK: mrs x24, {{trcsyncpr|TRCSYNCPR}} 0x1c 0xe 0x31 0xd5 -# CHECK: mrs x28, trcccctlr +# CHECK: mrs x28, {{trcccctlr|TRCCCCTLR}} 0xf 0xf 0x31 0xd5 -# CHECK: mrs x15, trcbbctlr +# CHECK: mrs x15, {{trcbbctlr|TRCBBCTLR}} 0x21 0x0 0x31 0xd5 -# CHECK: mrs x1, trctraceidr +# CHECK: mrs x1, {{trctraceidr|TRCTRACEIDR}} 0x34 0x1 0x31 0xd5 -# CHECK: mrs x20, trcqctlr +# CHECK: mrs x20, {{trcqctlr|TRCQCTLR}} 0x42 0x0 0x31 0xd5 -# CHECK: mrs x2, trcvictlr +# CHECK: mrs x2, {{trcvictlr|TRCVICTLR}} 0x4c 0x1 0x31 0xd5 -# CHECK: mrs x12, trcviiectlr +# CHECK: mrs x12, {{trcviiectlr|TRCVIIECTLR}} 0x50 0x2 0x31 0xd5 -# CHECK: mrs x16, trcvissctlr +# CHECK: mrs x16, {{trcvissctlr|TRCVISSCTLR}} 0x48 0x3 0x31 0xd5 -# CHECK: mrs x8, trcvipcssctlr +# CHECK: mrs x8, {{trcvipcssctlr|TRCVIPCSSCTLR}} 0x5b 0x8 0x31 0xd5 -# CHECK: mrs x27, trcvdctlr +# CHECK: mrs x27, {{trcvdctlr|TRCVDCTLR}} 0x49 0x9 0x31 0xd5 -# CHECK: mrs x9, trcvdsacctlr +# CHECK: mrs x9, {{trcvdsacctlr|TRCVDSACCTLR}} 0x40 0xa 0x31 0xd5 -# CHECK: mrs x0, trcvdarcctlr +# CHECK: mrs x0, {{trcvdarcctlr|TRCVDARCCTLR}} 0x8d 0x0 0x31 0xd5 -# CHECK: mrs x13, trcseqevr0 +# CHECK: mrs x13, {{trcseqevr0|TRCSEQEVR0}} 0x8b 0x1 0x31 0xd5 -# CHECK: mrs x11, trcseqevr1 +# CHECK: mrs x11, {{trcseqevr1|TRCSEQEVR1}} 0x9a 0x2 0x31 0xd5 -# CHECK: mrs x26, trcseqevr2 +# CHECK: mrs x26, {{trcseqevr2|TRCSEQEVR2}} 0x8e 0x6 0x31 0xd5 -# CHECK: mrs x14, trcseqrstevr +# CHECK: mrs x14, {{trcseqrstevr|TRCSEQRSTEVR}} 0x84 0x7 0x31 0xd5 -# CHECK: mrs x4, trcseqstr +# CHECK: mrs x4, {{trcseqstr|TRCSEQSTR}} 0x91 0x8 0x31 0xd5 -# CHECK: mrs x17, trcextinselr +# CHECK: mrs x17, {{trcextinselr|TRCEXTINSELR}} 0xb5 0x0 0x31 0xd5 -# CHECK: mrs x21, trccntrldvr0 +# CHECK: mrs x21, {{trccntrldvr0|TRCCNTRLDVR0}} 0xaa 0x1 0x31 0xd5 -# CHECK: mrs x10, trccntrldvr1 +# CHECK: mrs x10, {{trccntrldvr1|TRCCNTRLDVR1}} 0xb4 0x2 0x31 0xd5 -# CHECK: mrs x20, trccntrldvr2 +# CHECK: mrs x20, {{trccntrldvr2|TRCCNTRLDVR2}} 0xa5 0x3 0x31 0xd5 -# CHECK: mrs x5, trccntrldvr3 +# CHECK: mrs x5, {{trccntrldvr3|TRCCNTRLDVR3}} 0xb1 0x4 0x31 0xd5 -# CHECK: mrs x17, trccntctlr0 +# CHECK: mrs x17, {{trccntctlr0|TRCCNTCTLR0}} 0xa1 0x5 0x31 0xd5 -# CHECK: mrs x1, trccntctlr1 +# CHECK: mrs x1, {{trccntctlr1|TRCCNTCTLR1}} 0xb1 0x6 0x31 0xd5 -# CHECK: mrs x17, trccntctlr2 +# CHECK: mrs x17, {{trccntctlr2|TRCCNTCTLR2}} 0xa6 0x7 0x31 0xd5 -# CHECK: mrs x6, trccntctlr3 +# CHECK: mrs x6, {{trccntctlr3|TRCCNTCTLR3}} 0xbc 0x8 0x31 0xd5 -# CHECK: mrs x28, trccntvr0 +# CHECK: mrs x28, {{trccntvr0|TRCCNTVR0}} 0xb7 0x9 0x31 0xd5 -# CHECK: mrs x23, trccntvr1 +# CHECK: mrs x23, {{trccntvr1|TRCCNTVR1}} 0xa9 0xa 0x31 0xd5 -# CHECK: mrs x9, trccntvr2 +# CHECK: mrs x9, {{trccntvr2|TRCCNTVR2}} 0xa6 0xb 0x31 0xd5 -# CHECK: mrs x6, trccntvr3 +# CHECK: mrs x6, {{trccntvr3|TRCCNTVR3}} 0xf8 0x0 0x31 0xd5 -# CHECK: mrs x24, trcimspec0 +# CHECK: mrs x24, {{trcimspec0|TRCIMSPEC0}} 0xf8 0x1 0x31 0xd5 -# CHECK: mrs x24, trcimspec1 +# CHECK: mrs x24, {{trcimspec1|TRCIMSPEC1}} 0xef 0x2 0x31 0xd5 -# CHECK: mrs x15, trcimspec2 +# CHECK: mrs x15, {{trcimspec2|TRCIMSPEC2}} 0xea 0x3 0x31 0xd5 -# CHECK: mrs x10, trcimspec3 +# CHECK: mrs x10, {{trcimspec3|TRCIMSPEC3}} 0xfd 0x4 0x31 0xd5 -# CHECK: mrs x29, trcimspec4 +# CHECK: mrs x29, {{trcimspec4|TRCIMSPEC4}} 0xf2 0x5 0x31 0xd5 -# CHECK: mrs x18, trcimspec5 +# CHECK: mrs x18, {{trcimspec5|TRCIMSPEC5}} 0xfd 0x6 0x31 0xd5 -# CHECK: mrs x29, trcimspec6 +# CHECK: mrs x29, {{trcimspec6|TRCIMSPEC6}} 0xe2 0x7 0x31 0xd5 -# CHECK: mrs x2, trcimspec7 +# CHECK: mrs x2, {{trcimspec7|TRCIMSPEC7}} 0x8 0x12 0x31 0xd5 -# CHECK: mrs x8, trcrsctlr2 +# CHECK: mrs x8, {{trcrsctlr2|TRCRSCTLR2}} 0x0 0x13 0x31 0xd5 -# CHECK: mrs x0, trcrsctlr3 +# CHECK: mrs x0, {{trcrsctlr3|TRCRSCTLR3}} 0xc 0x14 0x31 0xd5 -# CHECK: mrs x12, trcrsctlr4 +# CHECK: mrs x12, {{trcrsctlr4|TRCRSCTLR4}} 0x1a 0x15 0x31 0xd5 -# CHECK: mrs x26, trcrsctlr5 +# CHECK: mrs x26, {{trcrsctlr5|TRCRSCTLR5}} 0x1d 0x16 0x31 0xd5 -# CHECK: mrs x29, trcrsctlr6 +# CHECK: mrs x29, {{trcrsctlr6|TRCRSCTLR6}} 0x11 0x17 0x31 0xd5 -# CHECK: mrs x17, trcrsctlr7 +# CHECK: mrs x17, {{trcrsctlr7|TRCRSCTLR7}} 0x0 0x18 0x31 0xd5 -# CHECK: mrs x0, trcrsctlr8 +# CHECK: mrs x0, {{trcrsctlr8|TRCRSCTLR8}} 0x1 0x19 0x31 0xd5 -# CHECK: mrs x1, trcrsctlr9 +# CHECK: mrs x1, {{trcrsctlr9|TRCRSCTLR9}} 0x11 0x1a 0x31 0xd5 -# CHECK: mrs x17, trcrsctlr10 +# CHECK: mrs x17, {{trcrsctlr10|TRCRSCTLR10}} 0x15 0x1b 0x31 0xd5 -# CHECK: mrs x21, trcrsctlr11 +# CHECK: mrs x21, {{trcrsctlr11|TRCRSCTLR11}} 0x1 0x1c 0x31 0xd5 -# CHECK: mrs x1, trcrsctlr12 +# CHECK: mrs x1, {{trcrsctlr12|TRCRSCTLR12}} 0x8 0x1d 0x31 0xd5 -# CHECK: mrs x8, trcrsctlr13 +# CHECK: mrs x8, {{trcrsctlr13|TRCRSCTLR13}} 0x18 0x1e 0x31 0xd5 -# CHECK: mrs x24, trcrsctlr14 +# CHECK: mrs x24, {{trcrsctlr14|TRCRSCTLR14}} 0x0 0x1f 0x31 0xd5 -# CHECK: mrs x0, trcrsctlr15 +# CHECK: mrs x0, {{trcrsctlr15|TRCRSCTLR15}} 0x22 0x10 0x31 0xd5 -# CHECK: mrs x2, trcrsctlr16 +# CHECK: mrs x2, {{trcrsctlr16|TRCRSCTLR16}} 0x3d 0x11 0x31 0xd5 -# CHECK: mrs x29, trcrsctlr17 +# CHECK: mrs x29, {{trcrsctlr17|TRCRSCTLR17}} 0x36 0x12 0x31 0xd5 -# CHECK: mrs x22, trcrsctlr18 +# CHECK: mrs x22, {{trcrsctlr18|TRCRSCTLR18}} 0x26 0x13 0x31 0xd5 -# CHECK: mrs x6, trcrsctlr19 +# CHECK: mrs x6, {{trcrsctlr19|TRCRSCTLR19}} 0x3a 0x14 0x31 0xd5 -# CHECK: mrs x26, trcrsctlr20 +# CHECK: mrs x26, {{trcrsctlr20|TRCRSCTLR20}} 0x3a 0x15 0x31 0xd5 -# CHECK: mrs x26, trcrsctlr21 +# CHECK: mrs x26, {{trcrsctlr21|TRCRSCTLR21}} 0x24 0x16 0x31 0xd5 -# CHECK: mrs x4, trcrsctlr22 +# CHECK: mrs x4, {{trcrsctlr22|TRCRSCTLR22}} 0x2c 0x17 0x31 0xd5 -# CHECK: mrs x12, trcrsctlr23 +# CHECK: mrs x12, {{trcrsctlr23|TRCRSCTLR23}} 0x21 0x18 0x31 0xd5 -# CHECK: mrs x1, trcrsctlr24 +# CHECK: mrs x1, {{trcrsctlr24|TRCRSCTLR24}} 0x20 0x19 0x31 0xd5 -# CHECK: mrs x0, trcrsctlr25 +# CHECK: mrs x0, {{trcrsctlr25|TRCRSCTLR25}} 0x31 0x1a 0x31 0xd5 -# CHECK: mrs x17, trcrsctlr26 +# CHECK: mrs x17, {{trcrsctlr26|TRCRSCTLR26}} 0x28 0x1b 0x31 0xd5 -# CHECK: mrs x8, trcrsctlr27 +# CHECK: mrs x8, {{trcrsctlr27|TRCRSCTLR27}} 0x2a 0x1c 0x31 0xd5 -# CHECK: mrs x10, trcrsctlr28 +# CHECK: mrs x10, {{trcrsctlr28|TRCRSCTLR28}} 0x39 0x1d 0x31 0xd5 -# CHECK: mrs x25, trcrsctlr29 +# CHECK: mrs x25, {{trcrsctlr29|TRCRSCTLR29}} 0x2c 0x1e 0x31 0xd5 -# CHECK: mrs x12, trcrsctlr30 +# CHECK: mrs x12, {{trcrsctlr30|TRCRSCTLR30}} 0x2b 0x1f 0x31 0xd5 -# CHECK: mrs x11, trcrsctlr31 +# CHECK: mrs x11, {{trcrsctlr31|TRCRSCTLR31}} 0x52 0x10 0x31 0xd5 -# CHECK: mrs x18, trcssccr0 +# CHECK: mrs x18, {{trcssccr0|TRCSSCCR0}} 0x4c 0x11 0x31 0xd5 -# CHECK: mrs x12, trcssccr1 +# CHECK: mrs x12, {{trcssccr1|TRCSSCCR1}} 0x43 0x12 0x31 0xd5 -# CHECK: mrs x3, trcssccr2 +# CHECK: mrs x3, {{trcssccr2|TRCSSCCR2}} 0x42 0x13 0x31 0xd5 -# CHECK: mrs x2, trcssccr3 +# CHECK: mrs x2, {{trcssccr3|TRCSSCCR3}} 0x55 0x14 0x31 0xd5 -# CHECK: mrs x21, trcssccr4 +# CHECK: mrs x21, {{trcssccr4|TRCSSCCR4}} 0x4a 0x15 0x31 0xd5 -# CHECK: mrs x10, trcssccr5 +# CHECK: mrs x10, {{trcssccr5|TRCSSCCR5}} 0x56 0x16 0x31 0xd5 -# CHECK: mrs x22, trcssccr6 +# CHECK: mrs x22, {{trcssccr6|TRCSSCCR6}} 0x57 0x17 0x31 0xd5 -# CHECK: mrs x23, trcssccr7 +# CHECK: mrs x23, {{trcssccr7|TRCSSCCR7}} 0x57 0x18 0x31 0xd5 -# CHECK: mrs x23, trcsscsr0 +# CHECK: mrs x23, {{trcsscsr0|TRCSSCSR0}} 0x53 0x19 0x31 0xd5 -# CHECK: mrs x19, trcsscsr1 +# CHECK: mrs x19, {{trcsscsr1|TRCSSCSR1}} 0x59 0x1a 0x31 0xd5 -# CHECK: mrs x25, trcsscsr2 +# CHECK: mrs x25, {{trcsscsr2|TRCSSCSR2}} 0x51 0x1b 0x31 0xd5 -# CHECK: mrs x17, trcsscsr3 +# CHECK: mrs x17, {{trcsscsr3|TRCSSCSR3}} 0x53 0x1c 0x31 0xd5 -# CHECK: mrs x19, trcsscsr4 +# CHECK: mrs x19, {{trcsscsr4|TRCSSCSR4}} 0x4b 0x1d 0x31 0xd5 -# CHECK: mrs x11, trcsscsr5 +# CHECK: mrs x11, {{trcsscsr5|TRCSSCSR5}} 0x45 0x1e 0x31 0xd5 -# CHECK: mrs x5, trcsscsr6 +# CHECK: mrs x5, {{trcsscsr6|TRCSSCSR6}} 0x49 0x1f 0x31 0xd5 -# CHECK: mrs x9, trcsscsr7 +# CHECK: mrs x9, {{trcsscsr7|TRCSSCSR7}} 0x9a 0x14 0x31 0xd5 -# CHECK: mrs x26, trcpdcr +# CHECK: mrs x26, {{trcpdcr|TRCPDCR}} 0x8 0x20 0x31 0xd5 -# CHECK: mrs x8, trcacvr0 +# CHECK: mrs x8, {{trcacvr0|TRCACVR0}} 0xf 0x22 0x31 0xd5 -# CHECK: mrs x15, trcacvr1 +# CHECK: mrs x15, {{trcacvr1|TRCACVR1}} 0x13 0x24 0x31 0xd5 -# CHECK: mrs x19, trcacvr2 +# CHECK: mrs x19, {{trcacvr2|TRCACVR2}} 0x8 0x26 0x31 0xd5 -# CHECK: mrs x8, trcacvr3 +# CHECK: mrs x8, {{trcacvr3|TRCACVR3}} 0x1c 0x28 0x31 0xd5 -# CHECK: mrs x28, trcacvr4 +# CHECK: mrs x28, {{trcacvr4|TRCACVR4}} 0x3 0x2a 0x31 0xd5 -# CHECK: mrs x3, trcacvr5 +# CHECK: mrs x3, {{trcacvr5|TRCACVR5}} 0x19 0x2c 0x31 0xd5 -# CHECK: mrs x25, trcacvr6 +# CHECK: mrs x25, {{trcacvr6|TRCACVR6}} 0x18 0x2e 0x31 0xd5 -# CHECK: mrs x24, trcacvr7 +# CHECK: mrs x24, {{trcacvr7|TRCACVR7}} 0x26 0x20 0x31 0xd5 -# CHECK: mrs x6, trcacvr8 +# CHECK: mrs x6, {{trcacvr8|TRCACVR8}} 0x23 0x22 0x31 0xd5 -# CHECK: mrs x3, trcacvr9 +# CHECK: mrs x3, {{trcacvr9|TRCACVR9}} 0x38 0x24 0x31 0xd5 -# CHECK: mrs x24, trcacvr10 +# CHECK: mrs x24, {{trcacvr10|TRCACVR10}} 0x23 0x26 0x31 0xd5 -# CHECK: mrs x3, trcacvr11 +# CHECK: mrs x3, {{trcacvr11|TRCACVR11}} 0x2c 0x28 0x31 0xd5 -# CHECK: mrs x12, trcacvr12 +# CHECK: mrs x12, {{trcacvr12|TRCACVR12}} 0x29 0x2a 0x31 0xd5 -# CHECK: mrs x9, trcacvr13 +# CHECK: mrs x9, {{trcacvr13|TRCACVR13}} 0x2e 0x2c 0x31 0xd5 -# CHECK: mrs x14, trcacvr14 +# CHECK: mrs x14, {{trcacvr14|TRCACVR14}} 0x23 0x2e 0x31 0xd5 -# CHECK: mrs x3, trcacvr15 +# CHECK: mrs x3, {{trcacvr15|TRCACVR15}} 0x55 0x20 0x31 0xd5 -# CHECK: mrs x21, trcacatr0 +# CHECK: mrs x21, {{trcacatr0|TRCACATR0}} 0x5a 0x22 0x31 0xd5 -# CHECK: mrs x26, trcacatr1 +# CHECK: mrs x26, {{trcacatr1|TRCACATR1}} 0x48 0x24 0x31 0xd5 -# CHECK: mrs x8, trcacatr2 +# CHECK: mrs x8, {{trcacatr2|TRCACATR2}} 0x56 0x26 0x31 0xd5 -# CHECK: mrs x22, trcacatr3 +# CHECK: mrs x22, {{trcacatr3|TRCACATR3}} 0x46 0x28 0x31 0xd5 -# CHECK: mrs x6, trcacatr4 +# CHECK: mrs x6, {{trcacatr4|TRCACATR4}} 0x5d 0x2a 0x31 0xd5 -# CHECK: mrs x29, trcacatr5 +# CHECK: mrs x29, {{trcacatr5|TRCACATR5}} 0x45 0x2c 0x31 0xd5 -# CHECK: mrs x5, trcacatr6 +# CHECK: mrs x5, {{trcacatr6|TRCACATR6}} 0x52 0x2e 0x31 0xd5 -# CHECK: mrs x18, trcacatr7 +# CHECK: mrs x18, {{trcacatr7|TRCACATR7}} 0x62 0x20 0x31 0xd5 -# CHECK: mrs x2, trcacatr8 +# CHECK: mrs x2, {{trcacatr8|TRCACATR8}} 0x73 0x22 0x31 0xd5 -# CHECK: mrs x19, trcacatr9 +# CHECK: mrs x19, {{trcacatr9|TRCACATR9}} 0x6d 0x24 0x31 0xd5 -# CHECK: mrs x13, trcacatr10 +# CHECK: mrs x13, {{trcacatr10|TRCACATR10}} 0x79 0x26 0x31 0xd5 -# CHECK: mrs x25, trcacatr11 +# CHECK: mrs x25, {{trcacatr11|TRCACATR11}} 0x72 0x28 0x31 0xd5 -# CHECK: mrs x18, trcacatr12 +# CHECK: mrs x18, {{trcacatr12|TRCACATR12}} 0x7d 0x2a 0x31 0xd5 -# CHECK: mrs x29, trcacatr13 +# CHECK: mrs x29, {{trcacatr13|TRCACATR13}} 0x69 0x2c 0x31 0xd5 -# CHECK: mrs x9, trcacatr14 +# CHECK: mrs x9, {{trcacatr14|TRCACATR14}} 0x72 0x2e 0x31 0xd5 -# CHECK: mrs x18, trcacatr15 +# CHECK: mrs x18, {{trcacatr15|TRCACATR15}} 0x9d 0x20 0x31 0xd5 -# CHECK: mrs x29, trcdvcvr0 +# CHECK: mrs x29, {{trcdvcvr0|TRCDVCVR0}} 0x8f 0x24 0x31 0xd5 -# CHECK: mrs x15, trcdvcvr1 +# CHECK: mrs x15, {{trcdvcvr1|TRCDVCVR1}} 0x8f 0x28 0x31 0xd5 -# CHECK: mrs x15, trcdvcvr2 +# CHECK: mrs x15, {{trcdvcvr2|TRCDVCVR2}} 0x8f 0x2c 0x31 0xd5 -# CHECK: mrs x15, trcdvcvr3 +# CHECK: mrs x15, {{trcdvcvr3|TRCDVCVR3}} 0xb3 0x20 0x31 0xd5 -# CHECK: mrs x19, trcdvcvr4 +# CHECK: mrs x19, {{trcdvcvr4|TRCDVCVR4}} 0xb6 0x24 0x31 0xd5 -# CHECK: mrs x22, trcdvcvr5 +# CHECK: mrs x22, {{trcdvcvr5|TRCDVCVR5}} 0xbb 0x28 0x31 0xd5 -# CHECK: mrs x27, trcdvcvr6 +# CHECK: mrs x27, {{trcdvcvr6|TRCDVCVR6}} 0xa1 0x2c 0x31 0xd5 -# CHECK: mrs x1, trcdvcvr7 +# CHECK: mrs x1, {{trcdvcvr7|TRCDVCVR7}} 0xdd 0x20 0x31 0xd5 -# CHECK: mrs x29, trcdvcmr0 +# CHECK: mrs x29, {{trcdvcmr0|TRCDVCMR0}} 0xc9 0x24 0x31 0xd5 -# CHECK: mrs x9, trcdvcmr1 +# CHECK: mrs x9, {{trcdvcmr1|TRCDVCMR1}} 0xc1 0x28 0x31 0xd5 -# CHECK: mrs x1, trcdvcmr2 +# CHECK: mrs x1, {{trcdvcmr2|TRCDVCMR2}} 0xc2 0x2c 0x31 0xd5 -# CHECK: mrs x2, trcdvcmr3 +# CHECK: mrs x2, {{trcdvcmr3|TRCDVCMR3}} 0xe5 0x20 0x31 0xd5 -# CHECK: mrs x5, trcdvcmr4 +# CHECK: mrs x5, {{trcdvcmr4|TRCDVCMR4}} 0xf5 0x24 0x31 0xd5 -# CHECK: mrs x21, trcdvcmr5 +# CHECK: mrs x21, {{trcdvcmr5|TRCDVCMR5}} 0xe5 0x28 0x31 0xd5 -# CHECK: mrs x5, trcdvcmr6 +# CHECK: mrs x5, {{trcdvcmr6|TRCDVCMR6}} 0xe1 0x2c 0x31 0xd5 -# CHECK: mrs x1, trcdvcmr7 +# CHECK: mrs x1, {{trcdvcmr7|TRCDVCMR7}} 0x15 0x30 0x31 0xd5 -# CHECK: mrs x21, trccidcvr0 +# CHECK: mrs x21, {{trccidcvr0|TRCCIDCVR0}} 0x18 0x32 0x31 0xd5 -# CHECK: mrs x24, trccidcvr1 +# CHECK: mrs x24, {{trccidcvr1|TRCCIDCVR1}} 0x18 0x34 0x31 0xd5 -# CHECK: mrs x24, trccidcvr2 +# CHECK: mrs x24, {{trccidcvr2|TRCCIDCVR2}} 0xc 0x36 0x31 0xd5 -# CHECK: mrs x12, trccidcvr3 +# CHECK: mrs x12, {{trccidcvr3|TRCCIDCVR3}} 0xa 0x38 0x31 0xd5 -# CHECK: mrs x10, trccidcvr4 +# CHECK: mrs x10, {{trccidcvr4|TRCCIDCVR4}} 0x9 0x3a 0x31 0xd5 -# CHECK: mrs x9, trccidcvr5 +# CHECK: mrs x9, {{trccidcvr5|TRCCIDCVR5}} 0x6 0x3c 0x31 0xd5 -# CHECK: mrs x6, trccidcvr6 +# CHECK: mrs x6, {{trccidcvr6|TRCCIDCVR6}} 0x14 0x3e 0x31 0xd5 -# CHECK: mrs x20, trccidcvr7 +# CHECK: mrs x20, {{trccidcvr7|TRCCIDCVR7}} 0x34 0x30 0x31 0xd5 -# CHECK: mrs x20, trcvmidcvr0 +# CHECK: mrs x20, {{trcvmidcvr0|TRCVMIDCVR0}} 0x34 0x32 0x31 0xd5 -# CHECK: mrs x20, trcvmidcvr1 +# CHECK: mrs x20, {{trcvmidcvr1|TRCVMIDCVR1}} 0x3a 0x34 0x31 0xd5 -# CHECK: mrs x26, trcvmidcvr2 +# CHECK: mrs x26, {{trcvmidcvr2|TRCVMIDCVR2}} 0x21 0x36 0x31 0xd5 -# CHECK: mrs x1, trcvmidcvr3 +# CHECK: mrs x1, {{trcvmidcvr3|TRCVMIDCVR3}} 0x2e 0x38 0x31 0xd5 -# CHECK: mrs x14, trcvmidcvr4 +# CHECK: mrs x14, {{trcvmidcvr4|TRCVMIDCVR4}} 0x3b 0x3a 0x31 0xd5 -# CHECK: mrs x27, trcvmidcvr5 +# CHECK: mrs x27, {{trcvmidcvr5|TRCVMIDCVR5}} 0x3d 0x3c 0x31 0xd5 -# CHECK: mrs x29, trcvmidcvr6 +# CHECK: mrs x29, {{trcvmidcvr6|TRCVMIDCVR6}} 0x31 0x3e 0x31 0xd5 -# CHECK: mrs x17, trcvmidcvr7 +# CHECK: mrs x17, {{trcvmidcvr7|TRCVMIDCVR7}} 0x4a 0x30 0x31 0xd5 -# CHECK: mrs x10, trccidcctlr0 +# CHECK: mrs x10, {{trccidcctlr0|TRCCIDCCTLR0}} 0x44 0x31 0x31 0xd5 -# CHECK: mrs x4, trccidcctlr1 +# CHECK: mrs x4, {{trccidcctlr1|TRCCIDCCTLR1}} 0x49 0x32 0x31 0xd5 -# CHECK: mrs x9, trcvmidcctlr0 +# CHECK: mrs x9, {{trcvmidcctlr0|TRCVMIDCCTLR0}} 0x4b 0x33 0x31 0xd5 -# CHECK: mrs x11, trcvmidcctlr1 +# CHECK: mrs x11, {{trcvmidcctlr1|TRCVMIDCCTLR1}} 0x96 0x70 0x31 0xd5 -# CHECK: mrs x22, trcitctrl +# CHECK: mrs x22, {{trcitctrl|TRCITCTRL}} 0xd7 0x78 0x31 0xd5 -# CHECK: mrs x23, trcclaimset +# CHECK: mrs x23, {{trcclaimset|TRCCLAIMSET}} 0xce 0x79 0x31 0xd5 -# CHECK: mrs x14, trcclaimclr +# CHECK: mrs x14, {{trcclaimclr|TRCCLAIMCLR}} 0x9c 0x10 0x11 0xd5 -# CHECK: msr trcoslar, x28 +# CHECK: msr {{trcoslar|TRCOSLAR}}, x28 0xce 0x7c 0x11 0xd5 -# CHECK: msr trclar, x14 +# CHECK: msr {{trclar|TRCLAR}}, x14 0xa 0x1 0x11 0xd5 -# CHECK: msr trcprgctlr, x10 +# CHECK: msr {{trcprgctlr|TRCPRGCTLR}}, x10 0x1b 0x2 0x11 0xd5 -# CHECK: msr trcprocselr, x27 +# CHECK: msr {{trcprocselr|TRCPROCSELR}}, x27 0x18 0x4 0x11 0xd5 -# CHECK: msr trcconfigr, x24 +# CHECK: msr {{trcconfigr|TRCCONFIGR}}, x24 0x8 0x6 0x11 0xd5 -# CHECK: msr trcauxctlr, x8 +# CHECK: msr {{trcauxctlr|TRCAUXCTLR}}, x8 0x10 0x8 0x11 0xd5 -# CHECK: msr trceventctl0r, x16 +# CHECK: msr {{trceventctl0r|TRCEVENTCTL0R}}, x16 0x1b 0x9 0x11 0xd5 -# CHECK: msr trceventctl1r, x27 +# CHECK: msr {{trceventctl1r|TRCEVENTCTL1R}}, x27 0x1a 0xb 0x11 0xd5 -# CHECK: msr trcstallctlr, x26 +# CHECK: msr {{trcstallctlr|TRCSTALLCTLR}}, x26 0x0 0xc 0x11 0xd5 -# CHECK: msr trctsctlr, x0 +# CHECK: msr {{trctsctlr|TRCTSCTLR}}, x0 0xe 0xd 0x11 0xd5 -# CHECK: msr trcsyncpr, x14 +# CHECK: msr {{trcsyncpr|TRCSYNCPR}}, x14 0x8 0xe 0x11 0xd5 -# CHECK: msr trcccctlr, x8 +# CHECK: msr {{trcccctlr|TRCCCCTLR}}, x8 0x6 0xf 0x11 0xd5 -# CHECK: msr trcbbctlr, x6 +# CHECK: msr {{trcbbctlr|TRCBBCTLR}}, x6 0x37 0x0 0x11 0xd5 -# CHECK: msr trctraceidr, x23 +# CHECK: msr {{trctraceidr|TRCTRACEIDR}}, x23 0x25 0x1 0x11 0xd5 -# CHECK: msr trcqctlr, x5 +# CHECK: msr {{trcqctlr|TRCQCTLR}}, x5 0x40 0x0 0x11 0xd5 -# CHECK: msr trcvictlr, x0 +# CHECK: msr {{trcvictlr|TRCVICTLR}}, x0 0x40 0x1 0x11 0xd5 -# CHECK: msr trcviiectlr, x0 +# CHECK: msr {{trcviiectlr|TRCVIIECTLR}}, x0 0x41 0x2 0x11 0xd5 -# CHECK: msr trcvissctlr, x1 +# CHECK: msr {{trcvissctlr|TRCVISSCTLR}}, x1 0x40 0x3 0x11 0xd5 -# CHECK: msr trcvipcssctlr, x0 +# CHECK: msr {{trcvipcssctlr|TRCVIPCSSCTLR}}, x0 0x47 0x8 0x11 0xd5 -# CHECK: msr trcvdctlr, x7 +# CHECK: msr {{trcvdctlr|TRCVDCTLR}}, x7 0x52 0x9 0x11 0xd5 -# CHECK: msr trcvdsacctlr, x18 +# CHECK: msr {{trcvdsacctlr|TRCVDSACCTLR}}, x18 0x58 0xa 0x11 0xd5 -# CHECK: msr trcvdarcctlr, x24 +# CHECK: msr {{trcvdarcctlr|TRCVDARCCTLR}}, x24 0x9c 0x0 0x11 0xd5 -# CHECK: msr trcseqevr0, x28 +# CHECK: msr {{trcseqevr0|TRCSEQEVR0}}, x28 0x95 0x1 0x11 0xd5 -# CHECK: msr trcseqevr1, x21 +# CHECK: msr {{trcseqevr1|TRCSEQEVR1}}, x21 0x90 0x2 0x11 0xd5 -# CHECK: msr trcseqevr2, x16 +# CHECK: msr {{trcseqevr2|TRCSEQEVR2}}, x16 0x90 0x6 0x11 0xd5 -# CHECK: msr trcseqrstevr, x16 +# CHECK: msr {{trcseqrstevr|TRCSEQRSTEVR}}, x16 0x99 0x7 0x11 0xd5 -# CHECK: msr trcseqstr, x25 +# CHECK: msr {{trcseqstr|TRCSEQSTR}}, x25 0x9d 0x8 0x11 0xd5 -# CHECK: msr trcextinselr, x29 +# CHECK: msr {{trcextinselr|TRCEXTINSELR}}, x29 0xb4 0x0 0x11 0xd5 -# CHECK: msr trccntrldvr0, x20 +# CHECK: msr {{trccntrldvr0|TRCCNTRLDVR0}}, x20 0xb4 0x1 0x11 0xd5 -# CHECK: msr trccntrldvr1, x20 +# CHECK: msr {{trccntrldvr1|TRCCNTRLDVR1}}, x20 0xb6 0x2 0x11 0xd5 -# CHECK: msr trccntrldvr2, x22 +# CHECK: msr {{trccntrldvr2|TRCCNTRLDVR2}}, x22 0xac 0x3 0x11 0xd5 -# CHECK: msr trccntrldvr3, x12 +# CHECK: msr {{trccntrldvr3|TRCCNTRLDVR3}}, x12 0xb4 0x4 0x11 0xd5 -# CHECK: msr trccntctlr0, x20 +# CHECK: msr {{trccntctlr0|TRCCNTCTLR0}}, x20 0xa4 0x5 0x11 0xd5 -# CHECK: msr trccntctlr1, x4 +# CHECK: msr {{trccntctlr1|TRCCNTCTLR1}}, x4 0xa8 0x6 0x11 0xd5 -# CHECK: msr trccntctlr2, x8 +# CHECK: msr {{trccntctlr2|TRCCNTCTLR2}}, x8 0xb0 0x7 0x11 0xd5 -# CHECK: msr trccntctlr3, x16 +# CHECK: msr {{trccntctlr3|TRCCNTCTLR3}}, x16 0xa5 0x8 0x11 0xd5 -# CHECK: msr trccntvr0, x5 +# CHECK: msr {{trccntvr0|TRCCNTVR0}}, x5 0xbb 0x9 0x11 0xd5 -# CHECK: msr trccntvr1, x27 +# CHECK: msr {{trccntvr1|TRCCNTVR1}}, x27 0xb5 0xa 0x11 0xd5 -# CHECK: msr trccntvr2, x21 +# CHECK: msr {{trccntvr2|TRCCNTVR2}}, x21 0xa8 0xb 0x11 0xd5 -# CHECK: msr trccntvr3, x8 +# CHECK: msr {{trccntvr3|TRCCNTVR3}}, x8 0xe6 0x0 0x11 0xd5 -# CHECK: msr trcimspec0, x6 +# CHECK: msr {{trcimspec0|TRCIMSPEC0}}, x6 0xfb 0x1 0x11 0xd5 -# CHECK: msr trcimspec1, x27 +# CHECK: msr {{trcimspec1|TRCIMSPEC1}}, x27 0xf7 0x2 0x11 0xd5 -# CHECK: msr trcimspec2, x23 +# CHECK: msr {{trcimspec2|TRCIMSPEC2}}, x23 0xef 0x3 0x11 0xd5 -# CHECK: msr trcimspec3, x15 +# CHECK: msr {{trcimspec3|TRCIMSPEC3}}, x15 0xed 0x4 0x11 0xd5 -# CHECK: msr trcimspec4, x13 +# CHECK: msr {{trcimspec4|TRCIMSPEC4}}, x13 0xf9 0x5 0x11 0xd5 -# CHECK: msr trcimspec5, x25 +# CHECK: msr {{trcimspec5|TRCIMSPEC5}}, x25 0xf3 0x6 0x11 0xd5 -# CHECK: msr trcimspec6, x19 +# CHECK: msr {{trcimspec6|TRCIMSPEC6}}, x19 0xfb 0x7 0x11 0xd5 -# CHECK: msr trcimspec7, x27 +# CHECK: msr {{trcimspec7|TRCIMSPEC7}}, x27 0x4 0x12 0x11 0xd5 -# CHECK: msr trcrsctlr2, x4 +# CHECK: msr {{trcrsctlr2|TRCRSCTLR2}}, x4 0x0 0x13 0x11 0xd5 -# CHECK: msr trcrsctlr3, x0 +# CHECK: msr {{trcrsctlr3|TRCRSCTLR3}}, x0 0x15 0x14 0x11 0xd5 -# CHECK: msr trcrsctlr4, x21 +# CHECK: msr {{trcrsctlr4|TRCRSCTLR4}}, x21 0x8 0x15 0x11 0xd5 -# CHECK: msr trcrsctlr5, x8 +# CHECK: msr {{trcrsctlr5|TRCRSCTLR5}}, x8 0x14 0x16 0x11 0xd5 -# CHECK: msr trcrsctlr6, x20 +# CHECK: msr {{trcrsctlr6|TRCRSCTLR6}}, x20 0xb 0x17 0x11 0xd5 -# CHECK: msr trcrsctlr7, x11 +# CHECK: msr {{trcrsctlr7|TRCRSCTLR7}}, x11 0x12 0x18 0x11 0xd5 -# CHECK: msr trcrsctlr8, x18 +# CHECK: msr {{trcrsctlr8|TRCRSCTLR8}}, x18 0x18 0x19 0x11 0xd5 -# CHECK: msr trcrsctlr9, x24 +# CHECK: msr {{trcrsctlr9|TRCRSCTLR9}}, x24 0xf 0x1a 0x11 0xd5 -# CHECK: msr trcrsctlr10, x15 +# CHECK: msr {{trcrsctlr10|TRCRSCTLR10}}, x15 0x15 0x1b 0x11 0xd5 -# CHECK: msr trcrsctlr11, x21 +# CHECK: msr {{trcrsctlr11|TRCRSCTLR11}}, x21 0x4 0x1c 0x11 0xd5 -# CHECK: msr trcrsctlr12, x4 +# CHECK: msr {{trcrsctlr12|TRCRSCTLR12}}, x4 0x1c 0x1d 0x11 0xd5 -# CHECK: msr trcrsctlr13, x28 +# CHECK: msr {{trcrsctlr13|TRCRSCTLR13}}, x28 0x3 0x1e 0x11 0xd5 -# CHECK: msr trcrsctlr14, x3 +# CHECK: msr {{trcrsctlr14|TRCRSCTLR14}}, x3 0x14 0x1f 0x11 0xd5 -# CHECK: msr trcrsctlr15, x20 +# CHECK: msr {{trcrsctlr15|TRCRSCTLR15}}, x20 0x2c 0x10 0x11 0xd5 -# CHECK: msr trcrsctlr16, x12 +# CHECK: msr {{trcrsctlr16|TRCRSCTLR16}}, x12 0x31 0x11 0x11 0xd5 -# CHECK: msr trcrsctlr17, x17 +# CHECK: msr {{trcrsctlr17|TRCRSCTLR17}}, x17 0x2a 0x12 0x11 0xd5 -# CHECK: msr trcrsctlr18, x10 +# CHECK: msr {{trcrsctlr18|TRCRSCTLR18}}, x10 0x2b 0x13 0x11 0xd5 -# CHECK: msr trcrsctlr19, x11 +# CHECK: msr {{trcrsctlr19|TRCRSCTLR19}}, x11 0x23 0x14 0x11 0xd5 -# CHECK: msr trcrsctlr20, x3 +# CHECK: msr {{trcrsctlr20|TRCRSCTLR20}}, x3 0x32 0x15 0x11 0xd5 -# CHECK: msr trcrsctlr21, x18 +# CHECK: msr {{trcrsctlr21|TRCRSCTLR21}}, x18 0x3a 0x16 0x11 0xd5 -# CHECK: msr trcrsctlr22, x26 +# CHECK: msr {{trcrsctlr22|TRCRSCTLR22}}, x26 0x25 0x17 0x11 0xd5 -# CHECK: msr trcrsctlr23, x5 +# CHECK: msr {{trcrsctlr23|TRCRSCTLR23}}, x5 0x39 0x18 0x11 0xd5 -# CHECK: msr trcrsctlr24, x25 +# CHECK: msr {{trcrsctlr24|TRCRSCTLR24}}, x25 0x25 0x19 0x11 0xd5 -# CHECK: msr trcrsctlr25, x5 +# CHECK: msr {{trcrsctlr25|TRCRSCTLR25}}, x5 0x24 0x1a 0x11 0xd5 -# CHECK: msr trcrsctlr26, x4 +# CHECK: msr {{trcrsctlr26|TRCRSCTLR26}}, x4 0x34 0x1b 0x11 0xd5 -# CHECK: msr trcrsctlr27, x20 +# CHECK: msr {{trcrsctlr27|TRCRSCTLR27}}, x20 0x25 0x1c 0x11 0xd5 -# CHECK: msr trcrsctlr28, x5 +# CHECK: msr {{trcrsctlr28|TRCRSCTLR28}}, x5 0x2a 0x1d 0x11 0xd5 -# CHECK: msr trcrsctlr29, x10 +# CHECK: msr {{trcrsctlr29|TRCRSCTLR29}}, x10 0x38 0x1e 0x11 0xd5 -# CHECK: msr trcrsctlr30, x24 +# CHECK: msr {{trcrsctlr30|TRCRSCTLR30}}, x24 0x34 0x1f 0x11 0xd5 -# CHECK: msr trcrsctlr31, x20 +# CHECK: msr {{trcrsctlr31|TRCRSCTLR31}}, x20 0x57 0x10 0x11 0xd5 -# CHECK: msr trcssccr0, x23 +# CHECK: msr {{trcssccr0|TRCSSCCR0}}, x23 0x5b 0x11 0x11 0xd5 -# CHECK: msr trcssccr1, x27 +# CHECK: msr {{trcssccr1|TRCSSCCR1}}, x27 0x5b 0x12 0x11 0xd5 -# CHECK: msr trcssccr2, x27 +# CHECK: msr {{trcssccr2|TRCSSCCR2}}, x27 0x46 0x13 0x11 0xd5 -# CHECK: msr trcssccr3, x6 +# CHECK: msr {{trcssccr3|TRCSSCCR3}}, x6 0x43 0x14 0x11 0xd5 -# CHECK: msr trcssccr4, x3 +# CHECK: msr {{trcssccr4|TRCSSCCR4}}, x3 0x4c 0x15 0x11 0xd5 -# CHECK: msr trcssccr5, x12 +# CHECK: msr {{trcssccr5|TRCSSCCR5}}, x12 0x47 0x16 0x11 0xd5 -# CHECK: msr trcssccr6, x7 +# CHECK: msr {{trcssccr6|TRCSSCCR6}}, x7 0x46 0x17 0x11 0xd5 -# CHECK: msr trcssccr7, x6 +# CHECK: msr {{trcssccr7|TRCSSCCR7}}, x6 0x54 0x18 0x11 0xd5 -# CHECK: msr trcsscsr0, x20 +# CHECK: msr {{trcsscsr0|TRCSSCSR0}}, x20 0x51 0x19 0x11 0xd5 -# CHECK: msr trcsscsr1, x17 +# CHECK: msr {{trcsscsr1|TRCSSCSR1}}, x17 0x4b 0x1a 0x11 0xd5 -# CHECK: msr trcsscsr2, x11 +# CHECK: msr {{trcsscsr2|TRCSSCSR2}}, x11 0x44 0x1b 0x11 0xd5 -# CHECK: msr trcsscsr3, x4 +# CHECK: msr {{trcsscsr3|TRCSSCSR3}}, x4 0x4e 0x1c 0x11 0xd5 -# CHECK: msr trcsscsr4, x14 +# CHECK: msr {{trcsscsr4|TRCSSCSR4}}, x14 0x56 0x1d 0x11 0xd5 -# CHECK: msr trcsscsr5, x22 +# CHECK: msr {{trcsscsr5|TRCSSCSR5}}, x22 0x43 0x1e 0x11 0xd5 -# CHECK: msr trcsscsr6, x3 +# CHECK: msr {{trcsscsr6|TRCSSCSR6}}, x3 0x4b 0x1f 0x11 0xd5 -# CHECK: msr trcsscsr7, x11 +# CHECK: msr {{trcsscsr7|TRCSSCSR7}}, x11 0x83 0x14 0x11 0xd5 -# CHECK: msr trcpdcr, x3 +# CHECK: msr {{trcpdcr|TRCPDCR}}, x3 0x6 0x20 0x11 0xd5 -# CHECK: msr trcacvr0, x6 +# CHECK: msr {{trcacvr0|TRCACVR0}}, x6 0x14 0x22 0x11 0xd5 -# CHECK: msr trcacvr1, x20 +# CHECK: msr {{trcacvr1|TRCACVR1}}, x20 0x19 0x24 0x11 0xd5 -# CHECK: msr trcacvr2, x25 +# CHECK: msr {{trcacvr2|TRCACVR2}}, x25 0x1 0x26 0x11 0xd5 -# CHECK: msr trcacvr3, x1 +# CHECK: msr {{trcacvr3|TRCACVR3}}, x1 0x1c 0x28 0x11 0xd5 -# CHECK: msr trcacvr4, x28 +# CHECK: msr {{trcacvr4|TRCACVR4}}, x28 0xf 0x2a 0x11 0xd5 -# CHECK: msr trcacvr5, x15 +# CHECK: msr {{trcacvr5|TRCACVR5}}, x15 0x19 0x2c 0x11 0xd5 -# CHECK: msr trcacvr6, x25 +# CHECK: msr {{trcacvr6|TRCACVR6}}, x25 0xc 0x2e 0x11 0xd5 -# CHECK: msr trcacvr7, x12 +# CHECK: msr {{trcacvr7|TRCACVR7}}, x12 0x25 0x20 0x11 0xd5 -# CHECK: msr trcacvr8, x5 +# CHECK: msr {{trcacvr8|TRCACVR8}}, x5 0x39 0x22 0x11 0xd5 -# CHECK: msr trcacvr9, x25 +# CHECK: msr {{trcacvr9|TRCACVR9}}, x25 0x2d 0x24 0x11 0xd5 -# CHECK: msr trcacvr10, x13 +# CHECK: msr {{trcacvr10|TRCACVR10}}, x13 0x2a 0x26 0x11 0xd5 -# CHECK: msr trcacvr11, x10 +# CHECK: msr {{trcacvr11|TRCACVR11}}, x10 0x33 0x28 0x11 0xd5 -# CHECK: msr trcacvr12, x19 +# CHECK: msr {{trcacvr12|TRCACVR12}}, x19 0x2a 0x2a 0x11 0xd5 -# CHECK: msr trcacvr13, x10 +# CHECK: msr {{trcacvr13|TRCACVR13}}, x10 0x33 0x2c 0x11 0xd5 -# CHECK: msr trcacvr14, x19 +# CHECK: msr {{trcacvr14|TRCACVR14}}, x19 0x22 0x2e 0x11 0xd5 -# CHECK: msr trcacvr15, x2 +# CHECK: msr {{trcacvr15|TRCACVR15}}, x2 0x4f 0x20 0x11 0xd5 -# CHECK: msr trcacatr0, x15 +# CHECK: msr {{trcacatr0|TRCACATR0}}, x15 0x4d 0x22 0x11 0xd5 -# CHECK: msr trcacatr1, x13 +# CHECK: msr {{trcacatr1|TRCACATR1}}, x13 0x48 0x24 0x11 0xd5 -# CHECK: msr trcacatr2, x8 +# CHECK: msr {{trcacatr2|TRCACATR2}}, x8 0x41 0x26 0x11 0xd5 -# CHECK: msr trcacatr3, x1 +# CHECK: msr {{trcacatr3|TRCACATR3}}, x1 0x4b 0x28 0x11 0xd5 -# CHECK: msr trcacatr4, x11 +# CHECK: msr {{trcacatr4|TRCACATR4}}, x11 0x48 0x2a 0x11 0xd5 -# CHECK: msr trcacatr5, x8 +# CHECK: msr {{trcacatr5|TRCACATR5}}, x8 0x58 0x2c 0x11 0xd5 -# CHECK: msr trcacatr6, x24 +# CHECK: msr {{trcacatr6|TRCACATR6}}, x24 0x46 0x2e 0x11 0xd5 -# CHECK: msr trcacatr7, x6 +# CHECK: msr {{trcacatr7|TRCACATR7}}, x6 0x77 0x20 0x11 0xd5 -# CHECK: msr trcacatr8, x23 +# CHECK: msr {{trcacatr8|TRCACATR8}}, x23 0x65 0x22 0x11 0xd5 -# CHECK: msr trcacatr9, x5 +# CHECK: msr {{trcacatr9|TRCACATR9}}, x5 0x6b 0x24 0x11 0xd5 -# CHECK: msr trcacatr10, x11 +# CHECK: msr {{trcacatr10|TRCACATR10}}, x11 0x6b 0x26 0x11 0xd5 -# CHECK: msr trcacatr11, x11 +# CHECK: msr {{trcacatr11|TRCACATR11}}, x11 0x63 0x28 0x11 0xd5 -# CHECK: msr trcacatr12, x3 +# CHECK: msr {{trcacatr12|TRCACATR12}}, x3 0x7c 0x2a 0x11 0xd5 -# CHECK: msr trcacatr13, x28 +# CHECK: msr {{trcacatr13|TRCACATR13}}, x28 0x79 0x2c 0x11 0xd5 -# CHECK: msr trcacatr14, x25 +# CHECK: msr {{trcacatr14|TRCACATR14}}, x25 0x64 0x2e 0x11 0xd5 -# CHECK: msr trcacatr15, x4 +# CHECK: msr {{trcacatr15|TRCACATR15}}, x4 0x86 0x20 0x11 0xd5 -# CHECK: msr trcdvcvr0, x6 +# CHECK: msr {{trcdvcvr0|TRCDVCVR0}}, x6 0x83 0x24 0x11 0xd5 -# CHECK: msr trcdvcvr1, x3 +# CHECK: msr {{trcdvcvr1|TRCDVCVR1}}, x3 0x85 0x28 0x11 0xd5 -# CHECK: msr trcdvcvr2, x5 +# CHECK: msr {{trcdvcvr2|TRCDVCVR2}}, x5 0x8b 0x2c 0x11 0xd5 -# CHECK: msr trcdvcvr3, x11 +# CHECK: msr {{trcdvcvr3|TRCDVCVR3}}, x11 0xa9 0x20 0x11 0xd5 -# CHECK: msr trcdvcvr4, x9 +# CHECK: msr {{trcdvcvr4|TRCDVCVR4}}, x9 0xae 0x24 0x11 0xd5 -# CHECK: msr trcdvcvr5, x14 +# CHECK: msr {{trcdvcvr5|TRCDVCVR5}}, x14 0xaa 0x28 0x11 0xd5 -# CHECK: msr trcdvcvr6, x10 +# CHECK: msr {{trcdvcvr6|TRCDVCVR6}}, x10 0xac 0x2c 0x11 0xd5 -# CHECK: msr trcdvcvr7, x12 +# CHECK: msr {{trcdvcvr7|TRCDVCVR7}}, x12 0xc8 0x20 0x11 0xd5 -# CHECK: msr trcdvcmr0, x8 +# CHECK: msr {{trcdvcmr0|TRCDVCMR0}}, x8 0xc8 0x24 0x11 0xd5 -# CHECK: msr trcdvcmr1, x8 +# CHECK: msr {{trcdvcmr1|TRCDVCMR1}}, x8 0xd6 0x28 0x11 0xd5 -# CHECK: msr trcdvcmr2, x22 +# CHECK: msr {{trcdvcmr2|TRCDVCMR2}}, x22 0xd6 0x2c 0x11 0xd5 -# CHECK: msr trcdvcmr3, x22 +# CHECK: msr {{trcdvcmr3|TRCDVCMR3}}, x22 0xe5 0x20 0x11 0xd5 -# CHECK: msr trcdvcmr4, x5 +# CHECK: msr {{trcdvcmr4|TRCDVCMR4}}, x5 0xf0 0x24 0x11 0xd5 -# CHECK: msr trcdvcmr5, x16 +# CHECK: msr {{trcdvcmr5|TRCDVCMR5}}, x16 0xfb 0x28 0x11 0xd5 -# CHECK: msr trcdvcmr6, x27 +# CHECK: msr {{trcdvcmr6|TRCDVCMR6}}, x27 0xf5 0x2c 0x11 0xd5 -# CHECK: msr trcdvcmr7, x21 +# CHECK: msr {{trcdvcmr7|TRCDVCMR7}}, x21 0x8 0x30 0x11 0xd5 -# CHECK: msr trccidcvr0, x8 +# CHECK: msr {{trccidcvr0|TRCCIDCVR0}}, x8 0x6 0x32 0x11 0xd5 -# CHECK: msr trccidcvr1, x6 +# CHECK: msr {{trccidcvr1|TRCCIDCVR1}}, x6 0x9 0x34 0x11 0xd5 -# CHECK: msr trccidcvr2, x9 +# CHECK: msr {{trccidcvr2|TRCCIDCVR2}}, x9 0x8 0x36 0x11 0xd5 -# CHECK: msr trccidcvr3, x8 +# CHECK: msr {{trccidcvr3|TRCCIDCVR3}}, x8 0x3 0x38 0x11 0xd5 -# CHECK: msr trccidcvr4, x3 +# CHECK: msr {{trccidcvr4|TRCCIDCVR4}}, x3 0x15 0x3a 0x11 0xd5 -# CHECK: msr trccidcvr5, x21 +# CHECK: msr {{trccidcvr5|TRCCIDCVR5}}, x21 0xc 0x3c 0x11 0xd5 -# CHECK: msr trccidcvr6, x12 +# CHECK: msr {{trccidcvr6|TRCCIDCVR6}}, x12 0x7 0x3e 0x11 0xd5 -# CHECK: msr trccidcvr7, x7 +# CHECK: msr {{trccidcvr7|TRCCIDCVR7}}, x7 0x24 0x30 0x11 0xd5 -# CHECK: msr trcvmidcvr0, x4 +# CHECK: msr {{trcvmidcvr0|TRCVMIDCVR0}}, x4 0x23 0x32 0x11 0xd5 -# CHECK: msr trcvmidcvr1, x3 +# CHECK: msr {{trcvmidcvr1|TRCVMIDCVR1}}, x3 0x29 0x34 0x11 0xd5 -# CHECK: msr trcvmidcvr2, x9 +# CHECK: msr {{trcvmidcvr2|TRCVMIDCVR2}}, x9 0x31 0x36 0x11 0xd5 -# CHECK: msr trcvmidcvr3, x17 +# CHECK: msr {{trcvmidcvr3|TRCVMIDCVR3}}, x17 0x2e 0x38 0x11 0xd5 -# CHECK: msr trcvmidcvr4, x14 +# CHECK: msr {{trcvmidcvr4|TRCVMIDCVR4}}, x14 0x2c 0x3a 0x11 0xd5 -# CHECK: msr trcvmidcvr5, x12 +# CHECK: msr {{trcvmidcvr5|TRCVMIDCVR5}}, x12 0x2a 0x3c 0x11 0xd5 -# CHECK: msr trcvmidcvr6, x10 +# CHECK: msr {{trcvmidcvr6|TRCVMIDCVR6}}, x10 0x23 0x3e 0x11 0xd5 -# CHECK: msr trcvmidcvr7, x3 +# CHECK: msr {{trcvmidcvr7|TRCVMIDCVR7}}, x3 0x4e 0x30 0x11 0xd5 -# CHECK: msr trccidcctlr0, x14 +# CHECK: msr {{trccidcctlr0|TRCCIDCCTLR0}}, x14 0x56 0x31 0x11 0xd5 -# CHECK: msr trccidcctlr1, x22 +# CHECK: msr {{trccidcctlr1|TRCCIDCCTLR1}}, x22 0x48 0x32 0x11 0xd5 -# CHECK: msr trcvmidcctlr0, x8 +# CHECK: msr {{trcvmidcctlr0|TRCVMIDCCTLR0}}, x8 0x4f 0x33 0x11 0xd5 -# CHECK: msr trcvmidcctlr1, x15 +# CHECK: msr {{trcvmidcctlr1|TRCVMIDCCTLR1}}, x15 0x81 0x70 0x11 0xd5 -# CHECK: msr trcitctrl, x1 +# CHECK: msr {{trcitctrl|TRCITCTRL}}, x1 0xc7 0x78 0x11 0xd5 -# CHECK: msr trcclaimset, x7 +# CHECK: msr {{trcclaimset|TRCCLAIMSET}}, x7 0xdd 0x79 0x11 0xd5 -# CHECK: msr trcclaimclr, x29 +# CHECK: msr {{trcclaimclr|TRCCLAIMCLR}}, x29 diff --git a/test/MC/Disassembler/ARM/invalid-thumbv7.txt b/test/MC/Disassembler/ARM/invalid-thumbv7.txt index 2c84b8a..5257633 100644 --- a/test/MC/Disassembler/ARM/invalid-thumbv7.txt +++ b/test/MC/Disassembler/ARM/invalid-thumbv7.txt @@ -21,17 +21,6 @@ # CHECK: warning: invalid instruction encoding # CHECK-NEXT: [0xaf 0xf7 0x44 0x8b] -# Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# if cond = '1110' then UNDEFINED -[0x6f 0xde] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0x6f 0xde] - #------------------------------------------------------------------------------ # Undefined encoding for it #------------------------------------------------------------------------------ @@ -249,34 +238,6 @@ # CHECK-NEXT: [0xe4 0xe9 0x02 0x46] #------------------------------------------------------------------------------ -# Undefined encodings for NEON/VFP instructions with invalid predicate bits -#------------------------------------------------------------------------------ - -# VABS -[0x40 0xde 0x00 0x0a] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0x40 0xde 0x00 0x0a] - - -# VMLA -[0xf0 0xde 0xe0 0x0b] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0xf0 0xde 0xe0 0x0b] - -# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110) - -# VMOV -[0x00 0xde 0x10 0x0b] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0x00 0xde 0x10 0x0b] - -# VDUP -[0xff 0xde 0xf0 0xfb] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0xff 0xde 0xf0 0xfb] - - -#------------------------------------------------------------------------------ # Undefined encodings for NEON vld instructions #------------------------------------------------------------------------------ diff --git a/test/MC/Disassembler/ARM64/lit.local.cfg b/test/MC/Disassembler/ARM64/lit.local.cfg deleted file mode 100644 index 46a9468..0000000 --- a/test/MC/Disassembler/ARM64/lit.local.cfg +++ /dev/null @@ -1,5 +0,0 @@ -config.suffixes = ['.txt'] - -targets = set(config.root.targets_to_build.split()) -if not 'ARM64' in targets: - config.unsupported = True diff --git a/test/MC/Disassembler/Mips/mips32r6.txt b/test/MC/Disassembler/Mips/mips32r6.txt new file mode 100644 index 0000000..adbcd99 --- /dev/null +++ b/test/MC/Disassembler/Mips/mips32r6.txt @@ -0,0 +1,116 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 | FileCheck %s + +0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 +0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2 +0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 +0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 +0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 +0xe8 0x37 0x96 0xb8 # CHECK: balc 14572256 +0xc8 0x37 0x96 0xb8 # CHECK: bc 14572256 + +# FIXME: Don't check the immediate on these for the moment, the encode/decode +# functions are not inverses of eachother. +# The immediate should be 4 but the disassembler currently emits 8 +0x45 0x20 0x00 0x01 # CHECK: bc1eqz $f0, +0x45 0x3f 0x00 0x01 # CHECK: bc1eqz $f31, +0x45 0xa0 0x00 0x01 # CHECK: bc1nez $f0, +0x45 0xbf 0x00 0x01 # CHECK: bc1nez $f31, +# FIXME: Don't check the immediate on these for the moment, the encode/decode +# functions are not inverses of eachother. +# The immediate should be 8 but the disassembler currently emits 12 +0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, +0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, +0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, +0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, + +0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256 +# FIXME: Don't check the immediate on the bcczal's for the moment, the +# encode/decode functions are not inverses of eachother. +0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, +0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 +0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, +0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 +0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, +0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 +0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256 +0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 256 +0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, +0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256 +0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, +0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256 +0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 +0x18 0x02 0x01 0x4d # CHECK: blezalc $2, +0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 +0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4 +0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4 +0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4 +0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4 +0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4 +0x46 0x84 0x18 0x80 # CHECK: cmp.f.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x80 # CHECK: cmp.f.d $f2, $f3, $f4 +0x46 0x84 0x18 0x81 # CHECK: cmp.un.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4 +0x46 0x84 0x18 0x82 # CHECK: cmp.eq.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x82 # CHECK: cmp.eq.d $f2, $f3, $f4 +0x46 0x84 0x18 0x83 # CHECK: cmp.ueq.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4 +0x46 0x84 0x18 0x84 # CHECK: cmp.olt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x84 # CHECK: cmp.olt.d $f2, $f3, $f4 +0x46 0x84 0x18 0x85 # CHECK: cmp.ult.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4 +0x46 0x84 0x18 0x86 # CHECK: cmp.ole.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x86 # CHECK: cmp.ole.d $f2, $f3, $f4 +0x46 0x84 0x18 0x87 # CHECK: cmp.ule.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4 +0x46 0x84 0x18 0x88 # CHECK: cmp.sf.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x88 # CHECK: cmp.sf.d $f2, $f3, $f4 +0x46 0x84 0x18 0x89 # CHECK: cmp.ngle.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x89 # CHECK: cmp.ngle.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8a # CHECK: cmp.seq.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8b # CHECK: cmp.ngl.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8b # CHECK: cmp.ngl.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8c # CHECK: cmp.lt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8c # CHECK: cmp.lt.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8d # CHECK: cmp.nge.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8d # CHECK: cmp.nge.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8e # CHECK: cmp.le.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8e # CHECK: cmp.le.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8f # CHECK: cmp.ngt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8f # CHECK: cmp.ngt.d $f2, $f3, $f4 +0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4 +0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4 +# 0xf8 0x05 0x01 0x00 # CHECK-TODO: jialc $5, 256 +# 0xd8 0x05 0x01 0x00 # CHECK-TODO: jic $5, 256 +0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268 +0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 +0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4 +0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4 +0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4 +0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4 +0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4 +0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4 +0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 +0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 +0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 +0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 +0x46 0x22 0x08 0x10 # CHECK: sel.d $f0, $f1, $f2 +0x46 0x02 0x08 0x10 # CHECK: sel.s $f0, $f1, $f2 +0x00 0x64 0x10 0x35 # CHECK: seleqz $2, $3, $4 +0x00 0x64 0x10 0x37 # CHECK: selnez $2, $3, $4 +0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4 +0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4 +0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4 +0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4 +0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4 +0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4 +0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4 +0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4 +0x46 0x00 0x20 0x9a # CHECK: rint.s $f2, $f4 +0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4 +0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4 +0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4 diff --git a/test/MC/Disassembler/Mips/mips64r6.txt b/test/MC/Disassembler/Mips/mips64r6.txt new file mode 100644 index 0000000..f5bb14e --- /dev/null +++ b/test/MC/Disassembler/Mips/mips64r6.txt @@ -0,0 +1,129 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips64r6 | FileCheck %s + +0xec 0x80 0x00 0x19 # CHECK: addiupc $4, 100 +0x7c 0x43 0x22 0xa0 # CHECK: align $4, $2, $3, 2 +0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56 +0x3c 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 +0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1 +0xe8 0x37 0x96 0xb8 # CHECK: balc 14572256 +0xc8 0x37 0x96 0xb8 # CHECK: bc 14572256 + +# FIXME: Don't check the immediate on these for the moment, the encode/decode +# functions are not inverses of eachother. +# The immediate should be 4 but the disassembler currently emits 8 +0x45 0x20 0x00 0x01 # CHECK: bc1eqz $f0, +0x45 0x3f 0x00 0x01 # CHECK: bc1eqz $f31, +0x45 0xa0 0x00 0x01 # CHECK: bc1nez $f0, +0x45 0xbf 0x00 0x01 # CHECK: bc1nez $f31, +# FIXME: Don't check the immediate on these for the moment, the encode/decode +# functions are not inverses of eachother. +# The immediate should be 8 but the disassembler currently emits 12 +0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, +0x49 0x3f 0x00 0x02 # CHECK: bc2eqz $31, +0x49 0xa0 0x00 0x02 # CHECK: bc2nez $0, +0x49 0xbf 0x00 0x02 # CHECK: bc2nez $31, + +0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256 +# FIXME: Don't check the immediate on the bcczal's for the moment, the +# encode/decode functions are not inverses of eachother. +0x20 0x02 0x01 0x4d # CHECK: beqzalc $2, +0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 +0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, +0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 +0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, +0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 +0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256 +0x58 0xa5 0x00 0x40 # CHECK: bgezc $5, 256 +0x1c 0x02 0x01 0x4d # CHECK: bgtzalc $2, +0x58 0x05 0x00 0x40 # CHECK: blezc $5, 256 +0x1c 0x42 0x01 0x4d # CHECK: bltzalc $2, +0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256 +0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 +0x18 0x02 0x01 0x4d # CHECK: blezalc $2, +0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 +0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4 +0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4 +0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4 +0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4 +0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4 +0x46 0x84 0x18 0x80 # CHECK: cmp.f.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x80 # CHECK: cmp.f.d $f2, $f3, $f4 +0x46 0x84 0x18 0x81 # CHECK: cmp.un.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4 +0x46 0x84 0x18 0x82 # CHECK: cmp.eq.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x82 # CHECK: cmp.eq.d $f2, $f3, $f4 +0x46 0x84 0x18 0x83 # CHECK: cmp.ueq.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4 +0x46 0x84 0x18 0x84 # CHECK: cmp.olt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x84 # CHECK: cmp.olt.d $f2, $f3, $f4 +0x46 0x84 0x18 0x85 # CHECK: cmp.ult.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4 +0x46 0x84 0x18 0x86 # CHECK: cmp.ole.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x86 # CHECK: cmp.ole.d $f2, $f3, $f4 +0x46 0x84 0x18 0x87 # CHECK: cmp.ule.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4 +0x46 0x84 0x18 0x88 # CHECK: cmp.sf.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x88 # CHECK: cmp.sf.d $f2, $f3, $f4 +0x46 0x84 0x18 0x89 # CHECK: cmp.ngle.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x89 # CHECK: cmp.ngle.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8a # CHECK: cmp.seq.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8b # CHECK: cmp.ngl.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8b # CHECK: cmp.ngl.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8c # CHECK: cmp.lt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8c # CHECK: cmp.lt.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8d # CHECK: cmp.nge.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8d # CHECK: cmp.nge.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8e # CHECK: cmp.le.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8e # CHECK: cmp.le.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8f # CHECK: cmp.ngt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8f # CHECK: cmp.ngt.d $f2, $f3, $f4 +0x7c 0x43 0x23 0x64 # CHECK: dalign $4, $2, $3, 5 +0x74 0x62 0x12 0x34 # CHECK: daui $3, $2, 4660 +0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136 +0x04 0x7e 0xab 0xcd # CHECK: dati $3, -21555 +0x7c 0x02 0x20 0x24 # CHECK: dbitswap $4, $2 +0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4 +0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4 +# 0xf8 0x05 0x01 0x00 # CHECK-TODO: jialc $5, 256 +# 0xd8 0x05 0x01 0x00 # CHECK-TODO: jic $5, 256 +0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268 +0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268 +0x00 0x64 0x10 0xda # CHECK: mod $2, $3, $4 +0x00 0x64 0x10 0xdb # CHECK: modu $2, $3, $4 +0x00 0x64 0x10 0x9e # CHECK: ddiv $2, $3, $4 +0x00 0x64 0x10 0x9f # CHECK: ddivu $2, $3, $4 +0x00 0x64 0x10 0xde # CHECK: dmod $2, $3, $4 +0x00 0x64 0x10 0xdf # CHECK: dmodu $2, $3, $4 +0x00 0x64 0x10 0x98 # CHECK: mul $2, $3, $4 +0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4 +0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4 +0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4 +0x00 0x64 0x10 0xb8 # CHECK: dmul $2, $3, $4 +0x00 0x64 0x10 0xf8 # CHECK: dmuh $2, $3, $4 +0x00 0x64 0x10 0xb9 # CHECK: dmulu $2, $3, $4 +0x00 0x64 0x10 0xf9 # CHECK: dmuhu $2, $3, $4 +0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 +0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 +0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 +0x46 0x24 0x18 0x99 # CHECK: msubf.d $f2, $f3, $f4 +0x46 0x22 0x08 0x10 # CHECK: sel.d $f0, $f1, $f2 +0x46 0x02 0x08 0x10 # CHECK: sel.s $f0, $f1, $f2 +0x00 0x64 0x10 0x35 # CHECK: seleqz $2, $3, $4 +0x00 0x64 0x10 0x37 # CHECK: selnez $2, $3, $4 +0x46 0x04 0x10 0x1d # CHECK: max.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1d # CHECK: max.d $f0, $f2, $f4 +0x46 0x04 0x10 0x1c # CHECK: min.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1c # CHECK: min.d $f0, $f2, $f4 +0x46 0x04 0x10 0x1f # CHECK: maxa.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1f # CHECK: maxa.d $f0, $f2, $f4 +0x46 0x04 0x10 0x1e # CHECK: mina.s $f0, $f2, $f4 +0x46 0x24 0x10 0x1e # CHECK: mina.d $f0, $f2, $f4 +0x46 0x04 0x10 0x14 # CHECK: seleqz.s $f0, $f2, $f4 +0x46 0x24 0x10 0x14 # CHECK: seleqz.d $f0, $f2, $f4 +0x46 0x04 0x10 0x17 # CHECK: selnez.s $f0, $f2, $f4 +0x46 0x24 0x10 0x17 # CHECK: selnez.d $f0, $f2, $f4 +0x46 0x00 0x20 0x9a # CHECK: rint.s $f2, $f4 +0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4 +0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4 +0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4 diff --git a/test/MC/Disassembler/Mips/msa/test_2r.txt b/test/MC/Disassembler/Mips/msa/test_2r.txt new file mode 100644 index 0000000..7faa13c --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_2r.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x7b 0x00 0x4f 0x9e # CHECK: fill.b $w30, $9 +0x7b 0x01 0xbf 0xde # CHECK: fill.h $w31, $23 +0x7b 0x02 0xc4 0x1e # CHECK: fill.w $w16, $24 +0x7b 0x08 0x05 0x5e # CHECK: nloc.b $w21, $w0 +0x7b 0x09 0xfc 0x9e # CHECK: nloc.h $w18, $w31 +0x7b 0x0a 0xb8 0x9e # CHECK: nloc.w $w2, $w23 +0x7b 0x0b 0x51 0x1e # CHECK: nloc.d $w4, $w10 +0x7b 0x0c 0x17 0xde # CHECK: nlzc.b $w31, $w2 +0x7b 0x0d 0xb6 0xde # CHECK: nlzc.h $w27, $w22 +0x7b 0x0e 0xea 0x9e # CHECK: nlzc.w $w10, $w29 +0x7b 0x0f 0x4e 0x5e # CHECK: nlzc.d $w25, $w9 +0x7b 0x04 0x95 0x1e # CHECK: pcnt.b $w20, $w18 +0x7b 0x05 0x40 0x1e # CHECK: pcnt.h $w0, $w8 +0x7b 0x06 0x4d 0xde # CHECK: pcnt.w $w23, $w9 +0x7b 0x07 0xc5 0x5e # CHECK: pcnt.d $w21, $w24 diff --git a/test/MC/Disassembler/Mips/msa/test_2r_msa64.txt b/test/MC/Disassembler/Mips/msa/test_2r_msa64.txt new file mode 100644 index 0000000..f212390 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_2r_msa64.txt @@ -0,0 +1,3 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r2 -mattr=+msa | FileCheck %s + +0x7b 0x03 0x4e 0xde # CHECK: fill.d $w27, $9 diff --git a/test/MC/Disassembler/Mips/msa/test_2rf.txt b/test/MC/Disassembler/Mips/msa/test_2rf.txt new file mode 100644 index 0000000..e004f11 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_2rf.txt @@ -0,0 +1,34 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x7b 0x20 0x66 0x9e # CHECK: fclass.w $w26, $w12 +0x7b 0x21 0x8e 0x1e # CHECK: fclass.d $w24, $w17 +0x7b 0x30 0x02 0x1e # CHECK: fexupl.w $w8, $w0 +0x7b 0x31 0xec 0x5e # CHECK: fexupl.d $w17, $w29 +0x7b 0x32 0x23 0x5e # CHECK: fexupr.w $w13, $w4 +0x7b 0x33 0x11 0x5e # CHECK: fexupr.d $w5, $w2 +0x7b 0x3c 0xed 0x1e # CHECK: ffint_s.w $w20, $w29 +0x7b 0x3d 0x7b 0x1e # CHECK: ffint_s.d $w12, $w15 +0x7b 0x3e 0xd9 0xde # CHECK: ffint_u.w $w7, $w27 +0x7b 0x3f 0x84 0xde # CHECK: ffint_u.d $w19, $w16 +0x7b 0x34 0x6f 0xde # CHECK: ffql.w $w31, $w13 +0x7b 0x35 0x6b 0x1e # CHECK: ffql.d $w12, $w13 +0x7b 0x36 0xf6 0xde # CHECK: ffqr.w $w27, $w30 +0x7b 0x37 0x7f 0x9e # CHECK: ffqr.d $w30, $w15 +0x7b 0x2e 0xfe 0x5e # CHECK: flog2.w $w25, $w31 +0x7b 0x2f 0x54 0x9e # CHECK: flog2.d $w18, $w10 +0x7b 0x2c 0x79 0xde # CHECK: frint.w $w7, $w15 +0x7b 0x2d 0xb5 0x5e # CHECK: frint.d $w21, $w22 +0x7b 0x2a 0x04 0xde # CHECK: frcp.w $w19, $w0 +0x7b 0x2b 0x71 0x1e # CHECK: frcp.d $w4, $w14 +0x7b 0x28 0x8b 0x1e # CHECK: frsqrt.w $w12, $w17 +0x7b 0x29 0x5d 0xde # CHECK: frsqrt.d $w23, $w11 +0x7b 0x26 0x58 0x1e # CHECK: fsqrt.w $w0, $w11 +0x7b 0x27 0x63 0xde # CHECK: fsqrt.d $w15, $w12 +0x7b 0x38 0x2f 0x9e # CHECK: ftint_s.w $w30, $w5 +0x7b 0x39 0xb9 0x5e # CHECK: ftint_s.d $w5, $w23 +0x7b 0x3a 0x75 0x1e # CHECK: ftint_u.w $w20, $w14 +0x7b 0x3b 0xad 0xde # CHECK: ftint_u.d $w23, $w21 +0x7b 0x22 0x8f 0x5e # CHECK: ftrunc_s.w $w29, $w17 +0x7b 0x23 0xdb 0x1e # CHECK: ftrunc_s.d $w12, $w27 +0x7b 0x24 0x7c 0x5e # CHECK: ftrunc_u.w $w17, $w15 +0x7b 0x25 0xd9 0x5e # CHECK: ftrunc_u.d $w5, $w27 diff --git a/test/MC/Disassembler/Mips/msa/test_3r.txt b/test/MC/Disassembler/Mips/msa/test_3r.txt new file mode 100644 index 0000000..2ef3a89 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_3r.txt @@ -0,0 +1,244 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x78 0x04 0x4e 0x90 # CHECK: add_a.b $w26, $w9, $w4 +0x78 0x3f 0xdd 0xd0 # CHECK: add_a.h $w23, $w27, $w31 +0x78 0x56 0x32 0xd0 # CHECK: add_a.w $w11, $w6, $w22 +0x78 0x60 0x51 0x90 # CHECK: add_a.d $w6, $w10, $w0 +0x78 0x93 0xc4 0xd0 # CHECK: adds_a.b $w19, $w24, $w19 +0x78 0xa4 0x36 0x50 # CHECK: adds_a.h $w25, $w6, $w4 +0x78 0xdb 0x8e 0x50 # CHECK: adds_a.w $w25, $w17, $w27 +0x78 0xfa 0x93 0xd0 # CHECK: adds_a.d $w15, $w18, $w26 +0x79 0x13 0x5f 0x50 # CHECK: adds_s.b $w29, $w11, $w19 +0x79 0x3a 0xb9 0x50 # CHECK: adds_s.h $w5, $w23, $w26 +0x79 0x4d 0x74 0x10 # CHECK: adds_s.w $w16, $w14, $w13 +0x79 0x7c 0x70 0x90 # CHECK: adds_s.d $w2, $w14, $w28 +0x79 0x8e 0x88 0xd0 # CHECK: adds_u.b $w3, $w17, $w14 +0x79 0xa4 0xf2 0x90 # CHECK: adds_u.h $w10, $w30, $w4 +0x79 0xd4 0x93 0xd0 # CHECK: adds_u.w $w15, $w18, $w20 +0x79 0xe9 0x57 0x90 # CHECK: adds_u.d $w30, $w10, $w9 +0x78 0x15 0xa6 0x0e # CHECK: addv.b $w24, $w20, $w21 +0x78 0x3b 0x69 0x0e # CHECK: addv.h $w4, $w13, $w27 +0x78 0x4e 0x5c 0xce # CHECK: addv.w $w19, $w11, $w14 +0x78 0x7f 0xa8 0x8e # CHECK: addv.d $w2, $w21, $w31 +0x7a 0x03 0x85 0xd1 # CHECK: asub_s.b $w23, $w16, $w3 +0x7a 0x39 0x8d 0x91 # CHECK: asub_s.h $w22, $w17, $w25 +0x7a 0x49 0x0e 0x11 # CHECK: asub_s.w $w24, $w1, $w9 +0x7a 0x6c 0x63 0x51 # CHECK: asub_s.d $w13, $w12, $w12 +0x7a 0x8b 0xea 0x91 # CHECK: asub_u.b $w10, $w29, $w11 +0x7a 0xaf 0x4c 0x91 # CHECK: asub_u.h $w18, $w9, $w15 +0x7a 0xdf 0x9a 0x91 # CHECK: asub_u.w $w10, $w19, $w31 +0x7a 0xe0 0x54 0x51 # CHECK: asub_u.d $w17, $w10, $w0 +0x7a 0x01 0x28 0x90 # CHECK: ave_s.b $w2, $w5, $w1 +0x7a 0x29 0x9c 0x10 # CHECK: ave_s.h $w16, $w19, $w9 +0x7a 0x45 0xfc 0x50 # CHECK: ave_s.w $w17, $w31, $w5 +0x7a 0x6a 0xce 0xd0 # CHECK: ave_s.d $w27, $w25, $w10 +0x7a 0x89 0x9c 0x10 # CHECK: ave_u.b $w16, $w19, $w9 +0x7a 0xab 0xe7 0x10 # CHECK: ave_u.h $w28, $w28, $w11 +0x7a 0xcb 0x62 0xd0 # CHECK: ave_u.w $w11, $w12, $w11 +0x7a 0xfc 0x9f 0x90 # CHECK: ave_u.d $w30, $w19, $w28 +0x7b 0x02 0x86 0x90 # CHECK: aver_s.b $w26, $w16, $w2 +0x7b 0x3b 0xdf 0xd0 # CHECK: aver_s.h $w31, $w27, $w27 +0x7b 0x59 0x97 0x10 # CHECK: aver_s.w $w28, $w18, $w25 +0x7b 0x7b 0xaf 0x50 # CHECK: aver_s.d $w29, $w21, $w27 +0x7b 0x83 0xd7 0x50 # CHECK: aver_u.b $w29, $w26, $w3 +0x7b 0xa9 0x94 0x90 # CHECK: aver_u.h $w18, $w18, $w9 +0x7b 0xdd 0xcc 0x50 # CHECK: aver_u.w $w17, $w25, $w29 +0x7b 0xf3 0xb5 0x90 # CHECK: aver_u.d $w22, $w22, $w19 +0x79 0x9d 0x78 0x8d # CHECK: bclr.b $w2, $w15, $w29 +0x79 0xbc 0xac 0x0d # CHECK: bclr.h $w16, $w21, $w28 +0x79 0xc9 0x14 0xcd # CHECK: bclr.w $w19, $w2, $w9 +0x79 0xe4 0xfe 0xcd # CHECK: bclr.d $w27, $w31, $w4 +0x7b 0x18 0x81 0x4d # CHECK: binsl.b $w5, $w16, $w24 +0x7b 0x2a 0x2f 0x8d # CHECK: binsl.h $w30, $w5, $w10 +0x7b 0x4d 0x7b 0x8d # CHECK: binsl.w $w14, $w15, $w13 +0x7b 0x6c 0xa5 0xcd # CHECK: binsl.d $w23, $w20, $w12 +0x7b 0x82 0x5d 0x8d # CHECK: binsr.b $w22, $w11, $w2 +0x7b 0xa6 0xd0 0x0d # CHECK: binsr.h $w0, $w26, $w6 +0x7b 0xdc 0x1e 0x8d # CHECK: binsr.w $w26, $w3, $w28 +0x7b 0xf5 0x00 0x0d # CHECK: binsr.d $w0, $w0, $w21 +0x7a 0x98 0x58 0x0d # CHECK: bneg.b $w0, $w11, $w24 +0x7a 0xa4 0x87 0x0d # CHECK: bneg.h $w28, $w16, $w4 +0x7a 0xd3 0xd0 0xcd # CHECK: bneg.w $w3, $w26, $w19 +0x7a 0xef 0xeb 0x4d # CHECK: bneg.d $w13, $w29, $w15 +0x7a 0x1f 0x2f 0xcd # CHECK: bset.b $w31, $w5, $w31 +0x7a 0x26 0x63 0x8d # CHECK: bset.h $w14, $w12, $w6 +0x7a 0x4c 0x4f 0xcd # CHECK: bset.w $w31, $w9, $w12 +0x7a 0x65 0xb1 0x4d # CHECK: bset.d $w5, $w22, $w5 +0x78 0x12 0xff 0xcf # CHECK: ceq.b $w31, $w31, $w18 +0x78 0x29 0xda 0x8f # CHECK: ceq.h $w10, $w27, $w9 +0x78 0x4e 0x2a 0x4f # CHECK: ceq.w $w9, $w5, $w14 +0x78 0x60 0x89 0x4f # CHECK: ceq.d $w5, $w17, $w0 +0x7a 0x09 0x25 0xcf # CHECK: cle_s.b $w23, $w4, $w9 +0x7a 0x33 0xdd 0x8f # CHECK: cle_s.h $w22, $w27, $w19 +0x7a 0x4a 0xd7 0x8f # CHECK: cle_s.w $w30, $w26, $w10 +0x7a 0x6a 0x2c 0x8f # CHECK: cle_s.d $w18, $w5, $w10 +0x7a 0x80 0xc8 0x4f # CHECK: cle_u.b $w1, $w25, $w0 +0x7a 0xbd 0x01 0xcf # CHECK: cle_u.h $w7, $w0, $w29 +0x7a 0xc1 0x96 0x4f # CHECK: cle_u.w $w25, $w18, $w1 +0x7a 0xfe 0x01 0x8f # CHECK: cle_u.d $w6, $w0, $w30 +0x79 0x15 0x16 0x4f # CHECK: clt_s.b $w25, $w2, $w21 +0x79 0x29 0x98 0x8f # CHECK: clt_s.h $w2, $w19, $w9 +0x79 0x50 0x45 0xcf # CHECK: clt_s.w $w23, $w8, $w16 +0x79 0x6c 0xf1 0xcf # CHECK: clt_s.d $w7, $w30, $w12 +0x79 0x8d 0xf8 0x8f # CHECK: clt_u.b $w2, $w31, $w13 +0x79 0xb7 0xfc 0x0f # CHECK: clt_u.h $w16, $w31, $w23 +0x79 0xc9 0xc0 0xcf # CHECK: clt_u.w $w3, $w24, $w9 +0x79 0xe1 0x01 0xcf # CHECK: clt_u.d $w7, $w0, $w1 +0x7a 0x12 0x1f 0x52 # CHECK: div_s.b $w29, $w3, $w18 +0x7a 0x2d 0x84 0x52 # CHECK: div_s.h $w17, $w16, $w13 +0x7a 0x5e 0xc9 0x12 # CHECK: div_s.w $w4, $w25, $w30 +0x7a 0x74 0x4f 0xd2 # CHECK: div_s.d $w31, $w9, $w20 +0x7a 0x8a 0xe9 0x92 # CHECK: div_u.b $w6, $w29, $w10 +0x7a 0xae 0xae 0x12 # CHECK: div_u.h $w24, $w21, $w14 +0x7a 0xd9 0x77 0x52 # CHECK: div_u.w $w29, $w14, $w25 +0x7a 0xf5 0x0f 0xd2 # CHECK: div_u.d $w31, $w1, $w21 +0x78 0x39 0xb5 0xd3 # CHECK: dotp_s.h $w23, $w22, $w25 +0x78 0x45 0x75 0x13 # CHECK: dotp_s.w $w20, $w14, $w5 +0x78 0x76 0x14 0x53 # CHECK: dotp_s.d $w17, $w2, $w22 +0x78 0xa6 0x13 0x53 # CHECK: dotp_u.h $w13, $w2, $w6 +0x78 0xd5 0xb3 0xd3 # CHECK: dotp_u.w $w15, $w22, $w21 +0x78 0xfa 0x81 0x13 # CHECK: dotp_u.d $w4, $w16, $w26 +0x79 0x36 0xe0 0x53 # CHECK: dpadd_s.h $w1, $w28, $w22 +0x79 0x4c 0x0a 0x93 # CHECK: dpadd_s.w $w10, $w1, $w12 +0x79 0x7b 0xa8 0xd3 # CHECK: dpadd_s.d $w3, $w21, $w27 +0x79 0xb4 0x2c 0x53 # CHECK: dpadd_u.h $w17, $w5, $w20 +0x79 0xd0 0x46 0x13 # CHECK: dpadd_u.w $w24, $w8, $w16 +0x79 0xf0 0xeb 0xd3 # CHECK: dpadd_u.d $w15, $w29, $w16 +0x7a 0x2c 0x59 0x13 # CHECK: dpsub_s.h $w4, $w11, $w12 +0x7a 0x46 0x39 0x13 # CHECK: dpsub_s.w $w4, $w7, $w6 +0x7a 0x7c 0x67 0xd3 # CHECK: dpsub_s.d $w31, $w12, $w28 +0x7a 0xb1 0xc9 0x13 # CHECK: dpsub_u.h $w4, $w25, $w17 +0x7a 0xd0 0xcc 0xd3 # CHECK: dpsub_u.w $w19, $w25, $w16 +0x7a 0xfa 0x51 0xd3 # CHECK: dpsub_u.d $w7, $w10, $w26 +0x7a 0x22 0xc7 0x15 # CHECK: hadd_s.h $w28, $w24, $w2 +0x7a 0x4b 0x8e 0x15 # CHECK: hadd_s.w $w24, $w17, $w11 +0x7a 0x74 0x7c 0x55 # CHECK: hadd_s.d $w17, $w15, $w20 +0x7a 0xb1 0xeb 0x15 # CHECK: hadd_u.h $w12, $w29, $w17 +0x7a 0xc6 0x2a 0x55 # CHECK: hadd_u.w $w9, $w5, $w6 +0x7a 0xe6 0xa0 0x55 # CHECK: hadd_u.d $w1, $w20, $w6 +0x7b 0x3d 0x74 0x15 # CHECK: hsub_s.h $w16, $w14, $w29 +0x7b 0x4b 0x6a 0x55 # CHECK: hsub_s.w $w9, $w13, $w11 +0x7b 0x6e 0x97 0x95 # CHECK: hsub_s.d $w30, $w18, $w14 +0x7b 0xae 0x61 0xd5 # CHECK: hsub_u.h $w7, $w12, $w14 +0x7b 0xc5 0x2d 0x55 # CHECK: hsub_u.w $w21, $w5, $w5 +0x7b 0xff 0x62 0xd5 # CHECK: hsub_u.d $w11, $w12, $w31 +0x7b 0x1e 0x84 0x94 # CHECK: ilvev.b $w18, $w16, $w30 +0x7b 0x2d 0x03 0x94 # CHECK: ilvev.h $w14, $w0, $w13 +0x7b 0x56 0xcb 0x14 # CHECK: ilvev.w $w12, $w25, $w22 +0x7b 0x63 0xdf 0x94 # CHECK: ilvev.d $w30, $w27, $w3 +0x7a 0x15 0x1f 0x54 # CHECK: ilvl.b $w29, $w3, $w21 +0x7a 0x31 0x56 0xd4 # CHECK: ilvl.h $w27, $w10, $w17 +0x7a 0x40 0x09 0x94 # CHECK: ilvl.w $w6, $w1, $w0 +0x7a 0x78 0x80 0xd4 # CHECK: ilvl.d $w3, $w16, $w24 +0x7b 0x94 0x2a 0xd4 # CHECK: ilvod.b $w11, $w5, $w20 +0x7b 0xbf 0x6c 0x94 # CHECK: ilvod.h $w18, $w13, $w31 +0x7b 0xd8 0x87 0x54 # CHECK: ilvod.w $w29, $w16, $w24 +0x7b 0xfd 0x65 0x94 # CHECK: ilvod.d $w22, $w12, $w29 +0x7a 0x86 0xf1 0x14 # CHECK: ilvr.b $w4, $w30, $w6 +0x7a 0xbd 0x9f 0x14 # CHECK: ilvr.h $w28, $w19, $w29 +0x7a 0xd5 0xa4 0x94 # CHECK: ilvr.w $w18, $w20, $w21 +0x7a 0xec 0xf5 0xd4 # CHECK: ilvr.d $w23, $w30, $w12 +0x78 0x9d 0xfc 0x52 # CHECK: maddv.b $w17, $w31, $w29 +0x78 0xa9 0xc1 0xd2 # CHECK: maddv.h $w7, $w24, $w9 +0x78 0xd4 0xb5 0x92 # CHECK: maddv.w $w22, $w22, $w20 +0x78 0xf4 0xd7 0x92 # CHECK: maddv.d $w30, $w26, $w20 +0x7b 0x17 0x5d 0xce # CHECK: max_a.b $w23, $w11, $w23 +0x7b 0x3e 0x2d 0x0e # CHECK: max_a.h $w20, $w5, $w30 +0x7b 0x5e 0x91 0xce # CHECK: max_a.w $w7, $w18, $w30 +0x7b 0x7f 0x42 0x0e # CHECK: max_a.d $w8, $w8, $w31 +0x79 0x13 0x0a 0x8e # CHECK: max_s.b $w10, $w1, $w19 +0x79 0x31 0xeb 0xce # CHECK: max_s.h $w15, $w29, $w17 +0x79 0x4e 0xeb 0xce # CHECK: max_s.w $w15, $w29, $w14 +0x79 0x63 0xc6 0x4e # CHECK: max_s.d $w25, $w24, $w3 +0x79 0x85 0xc3 0x0e # CHECK: max_u.b $w12, $w24, $w5 +0x79 0xa7 0x31 0x4e # CHECK: max_u.h $w5, $w6, $w7 +0x79 0xc7 0x24 0x0e # CHECK: max_u.w $w16, $w4, $w7 +0x79 0xf8 0x66 0x8e # CHECK: max_u.d $w26, $w12, $w24 +0x7b 0x81 0xd1 0x0e # CHECK: min_a.b $w4, $w26, $w1 +0x7b 0xbf 0x6b 0x0e # CHECK: min_a.h $w12, $w13, $w31 +0x7b 0xc0 0xa7 0x0e # CHECK: min_a.w $w28, $w20, $w0 +0x7b 0xf3 0xa3 0x0e # CHECK: min_a.d $w12, $w20, $w19 +0x7a 0x0e 0x1c 0xce # CHECK: min_s.b $w19, $w3, $w14 +0x7a 0x28 0xae 0xce # CHECK: min_s.h $w27, $w21, $w8 +0x7a 0x5e 0x70 0x0e # CHECK: min_s.w $w0, $w14, $w30 +0x7a 0x75 0x41 0x8e # CHECK: min_s.d $w6, $w8, $w21 +0x7a 0x88 0xd5 0x8e # CHECK: min_u.b $w22, $w26, $w8 +0x7a 0xac 0xd9 0xce # CHECK: min_u.h $w7, $w27, $w12 +0x7a 0xce 0xa2 0x0e # CHECK: min_u.w $w8, $w20, $w14 +0x7a 0xef 0x76 0x8e # CHECK: min_u.d $w26, $w14, $w15 +0x7b 0x1a 0x0c 0x92 # CHECK: mod_s.b $w18, $w1, $w26 +0x7b 0x3c 0xf7 0xd2 # CHECK: mod_s.h $w31, $w30, $w28 +0x7b 0x4d 0x30 0x92 # CHECK: mod_s.w $w2, $w6, $w13 +0x7b 0x76 0xdd 0x52 # CHECK: mod_s.d $w21, $w27, $w22 +0x7b 0x8d 0x3c 0x12 # CHECK: mod_u.b $w16, $w7, $w13 +0x7b 0xa7 0x46 0x12 # CHECK: mod_u.h $w24, $w8, $w7 +0x7b 0xd1 0x17 0x92 # CHECK: mod_u.w $w30, $w2, $w17 +0x7b 0xf9 0x17 0xd2 # CHECK: mod_u.d $w31, $w2, $w25 +0x79 0x0c 0x2b 0x92 # CHECK: msubv.b $w14, $w5, $w12 +0x79 0x3e 0x39 0x92 # CHECK: msubv.h $w6, $w7, $w30 +0x79 0x55 0x13 0x52 # CHECK: msubv.w $w13, $w2, $w21 +0x79 0x7b 0x74 0x12 # CHECK: msubv.d $w16, $w14, $w27 +0x78 0x0d 0x1d 0x12 # CHECK: mulv.b $w20, $w3, $w13 +0x78 0x2e 0xd6 0xd2 # CHECK: mulv.h $w27, $w26, $w14 +0x78 0x43 0xea 0x92 # CHECK: mulv.w $w10, $w29, $w3 +0x78 0x7d 0x99 0xd2 # CHECK: mulv.d $w7, $w19, $w29 +0x79 0x07 0xd9 0x54 # CHECK: pckev.b $w5, $w27, $w7 +0x79 0x3b 0x20 0x54 # CHECK: pckev.h $w1, $w4, $w27 +0x79 0x40 0xa7 0x94 # CHECK: pckev.w $w30, $w20, $w0 +0x79 0x6f 0x09 0x94 # CHECK: pckev.d $w6, $w1, $w15 +0x79 0x9e 0xe4 0x94 # CHECK: pckod.b $w18, $w28, $w30 +0x79 0xa8 0x2e 0x94 # CHECK: pckod.h $w26, $w5, $w8 +0x79 0xc2 0x22 0x54 # CHECK: pckod.w $w9, $w4, $w2 +0x79 0xf4 0xb7 0x94 # CHECK: pckod.d $w30, $w22, $w20 +0x78 0x0c 0xb9 0x54 # CHECK: sld.b $w5, $w23[$12] +0x78 0x23 0xb8 0x54 # CHECK: sld.h $w1, $w23[$3] +0x78 0x49 0x45 0x14 # CHECK: sld.w $w20, $w8[$9] +0x78 0x7e 0xb9 0xd4 # CHECK: sld.d $w7, $w23[$fp] +0x78 0x11 0x00 0xcd # CHECK: sll.b $w3, $w0, $w17 +0x78 0x23 0xdc 0x4d # CHECK: sll.h $w17, $w27, $w3 +0x78 0x46 0x3c 0x0d # CHECK: sll.w $w16, $w7, $w6 +0x78 0x7a 0x02 0x4d # CHECK: sll.d $w9, $w0, $w26 +0x78 0x81 0x0f 0x14 # CHECK: splat.b $w28, $w1[$1] +0x78 0xab 0x58 0x94 # CHECK: splat.h $w2, $w11[$11] +0x78 0xcb 0x05 0x94 # CHECK: splat.w $w22, $w0[$11] +0x78 0xe2 0x00 0x14 # CHECK: splat.d $w0, $w0[$2] +0x78 0x91 0x27 0x0d # CHECK: sra.b $w28, $w4, $w17 +0x78 0xa3 0x4b 0x4d # CHECK: sra.h $w13, $w9, $w3 +0x78 0xd3 0xae 0xcd # CHECK: sra.w $w27, $w21, $w19 +0x78 0xf7 0x47 0x8d # CHECK: sra.d $w30, $w8, $w23 +0x78 0x92 0x94 0xd5 # CHECK: srar.b $w19, $w18, $w18 +0x78 0xa8 0xb9 0xd5 # CHECK: srar.h $w7, $w23, $w8 +0x78 0xc2 0x60 0x55 # CHECK: srar.w $w1, $w12, $w2 +0x78 0xee 0x3d 0x55 # CHECK: srar.d $w21, $w7, $w14 +0x79 0x13 0x1b 0x0d # CHECK: srl.b $w12, $w3, $w19 +0x79 0x34 0xfd 0xcd # CHECK: srl.h $w23, $w31, $w20 +0x79 0x4b 0xdc 0x8d # CHECK: srl.w $w18, $w27, $w11 +0x79 0x7a 0x60 0xcd # CHECK: srl.d $w3, $w12, $w26 +0x79 0x0b 0xab 0xd5 # CHECK: srlr.b $w15, $w21, $w11 +0x79 0x33 0x6d 0x55 # CHECK: srlr.h $w21, $w13, $w19 +0x79 0x43 0xf1 0x95 # CHECK: srlr.w $w6, $w30, $w3 +0x79 0x6e 0x10 0x55 # CHECK: srlr.d $w1, $w2, $w14 +0x78 0x01 0x7e 0x51 # CHECK: subs_s.b $w25, $w15, $w1 +0x78 0x36 0xcf 0x11 # CHECK: subs_s.h $w28, $w25, $w22 +0x78 0x55 0x62 0x91 # CHECK: subs_s.w $w10, $w12, $w21 +0x78 0x72 0xa1 0x11 # CHECK: subs_s.d $w4, $w20, $w18 +0x78 0x99 0x35 0x51 # CHECK: subs_u.b $w21, $w6, $w25 +0x78 0xa7 0x50 0xd1 # CHECK: subs_u.h $w3, $w10, $w7 +0x78 0xca 0x7a 0x51 # CHECK: subs_u.w $w9, $w15, $w10 +0x78 0xea 0x99 0xd1 # CHECK: subs_u.d $w7, $w19, $w10 +0x79 0x0c 0x39 0x91 # CHECK: subsus_u.b $w6, $w7, $w12 +0x79 0x33 0xe9 0x91 # CHECK: subsus_u.h $w6, $w29, $w19 +0x79 0x47 0x79 0xd1 # CHECK: subsus_u.w $w7, $w15, $w7 +0x79 0x6f 0x1a 0x51 # CHECK: subsus_u.d $w9, $w3, $w15 +0x79 0x9f 0x1d 0x91 # CHECK: subsuu_s.b $w22, $w3, $w31 +0x79 0xb6 0xbc 0xd1 # CHECK: subsuu_s.h $w19, $w23, $w22 +0x79 0xcd 0x52 0x51 # CHECK: subsuu_s.w $w9, $w10, $w13 +0x79 0xe0 0x31 0x51 # CHECK: subsuu_s.d $w5, $w6, $w0 +0x78 0x93 0x69 0x8e # CHECK: subv.b $w6, $w13, $w19 +0x78 0xac 0xc9 0x0e # CHECK: subv.h $w4, $w25, $w12 +0x78 0xcb 0xde 0xce # CHECK: subv.w $w27, $w27, $w11 +0x78 0xea 0xc2 0x4e # CHECK: subv.d $w9, $w24, $w10 +0x78 0x05 0x80 0xd5 # CHECK: vshf.b $w3, $w16, $w5 +0x78 0x28 0x9d 0x15 # CHECK: vshf.h $w20, $w19, $w8 +0x78 0x59 0xf4 0x15 # CHECK: vshf.w $w16, $w30, $w25 +0x78 0x6f 0x5c 0xd5 # CHECK: vshf.d $w19, $w11, $w15 diff --git a/test/MC/Disassembler/Mips/msa/test_3rf.txt b/test/MC/Disassembler/Mips/msa/test_3rf.txt new file mode 100644 index 0000000..3b7b07c --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_3rf.txt @@ -0,0 +1,84 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x78 0x1c 0x9f 0x1b # CHECK: fadd.w $w28, $w19, $w28 +0x78 0x3d 0x13 0x5b # CHECK: fadd.d $w13, $w2, $w29 +0x78 0x19 0x5b 0x9a # CHECK: fcaf.w $w14, $w11, $w25 +0x78 0x33 0x08 0x5a # CHECK: fcaf.d $w1, $w1, $w19 +0x78 0x90 0xb8 0x5a # CHECK: fceq.w $w1, $w23, $w16 +0x78 0xb0 0x40 0x1a # CHECK: fceq.d $w0, $w8, $w16 +0x79 0x98 0x4c 0x1a # CHECK: fcle.w $w16, $w9, $w24 +0x79 0xa1 0x76 0xda # CHECK: fcle.d $w27, $w14, $w1 +0x79 0x08 0x47 0x1a # CHECK: fclt.w $w28, $w8, $w8 +0x79 0x2b 0xcf 0x9a # CHECK: fclt.d $w30, $w25, $w11 +0x78 0xd7 0x90 0x9c # CHECK: fcne.w $w2, $w18, $w23 +0x78 0xef 0xa3 0x9c # CHECK: fcne.d $w14, $w20, $w15 +0x78 0x59 0x92 0x9c # CHECK: fcor.w $w10, $w18, $w25 +0x78 0x6b 0xcc 0x5c # CHECK: fcor.d $w17, $w25, $w11 +0x78 0xd5 0x13 0x9a # CHECK: fcueq.w $w14, $w2, $w21 +0x78 0xe7 0x1f 0x5a # CHECK: fcueq.d $w29, $w3, $w7 +0x79 0xc3 0x2c 0x5a # CHECK: fcule.w $w17, $w5, $w3 +0x79 0xfe 0x0f 0xda # CHECK: fcule.d $w31, $w1, $w30 +0x79 0x49 0xc9 0x9a # CHECK: fcult.w $w6, $w25, $w9 +0x79 0x71 0x46 0xda # CHECK: fcult.d $w27, $w8, $w17 +0x78 0x48 0xa1 0x1a # CHECK: fcun.w $w4, $w20, $w8 +0x78 0x63 0x5f 0x5a # CHECK: fcun.d $w29, $w11, $w3 +0x78 0x93 0x93 0x5c # CHECK: fcune.w $w13, $w18, $w19 +0x78 0xb5 0xd4 0x1c # CHECK: fcune.d $w16, $w26, $w21 +0x78 0xc2 0xc3 0x5b # CHECK: fdiv.w $w13, $w24, $w2 +0x78 0xf9 0x24 0xdb # CHECK: fdiv.d $w19, $w4, $w25 +0x7a 0x10 0x02 0x1b # CHECK: fexdo.h $w8, $w0, $w16 +0x7a 0x3b 0x68 0x1b # CHECK: fexdo.w $w0, $w13, $w27 +0x79 0xc3 0x04 0x5b # CHECK: fexp2.w $w17, $w0, $w3 +0x79 0xea 0x05 0x9b # CHECK: fexp2.d $w22, $w0, $w10 +0x79 0x17 0x37 0x5b # CHECK: fmadd.w $w29, $w6, $w23 +0x79 0x35 0xe2 0xdb # CHECK: fmadd.d $w11, $w28, $w21 +0x7b 0x8d 0xb8 0x1b # CHECK: fmax.w $w0, $w23, $w13 +0x7b 0xa8 0x96 0x9b # CHECK: fmax.d $w26, $w18, $w8 +0x7b 0xca 0x82 0x9b # CHECK: fmax_a.w $w10, $w16, $w10 +0x7b 0xf6 0x4f 0x9b # CHECK: fmax_a.d $w30, $w9, $w22 +0x7b 0x1e 0x0e 0x1b # CHECK: fmin.w $w24, $w1, $w30 +0x7b 0x2a 0xde 0xdb # CHECK: fmin.d $w27, $w27, $w10 +0x7b 0x54 0xea 0x9b # CHECK: fmin_a.w $w10, $w29, $w20 +0x7b 0x78 0xf3 0x5b # CHECK: fmin_a.d $w13, $w30, $w24 +0x79 0x40 0xcc 0x5b # CHECK: fmsub.w $w17, $w25, $w0 +0x79 0x70 0x92 0x1b # CHECK: fmsub.d $w8, $w18, $w16 +0x78 0x8f 0x78 0xdb # CHECK: fmul.w $w3, $w15, $w15 +0x78 0xaa 0xf2 0x5b # CHECK: fmul.d $w9, $w30, $w10 +0x7a 0x0a 0x2e 0x5a # CHECK: fsaf.w $w25, $w5, $w10 +0x7a 0x3d 0x1e 0x5a # CHECK: fsaf.d $w25, $w3, $w29 +0x7a 0x8d 0x8a 0xda # CHECK: fseq.w $w11, $w17, $w13 +0x7a 0xbf 0x07 0x5a # CHECK: fseq.d $w29, $w0, $w31 +0x7b 0x9f 0xff 0x9a # CHECK: fsle.w $w30, $w31, $w31 +0x7b 0xb8 0xbc 0x9a # CHECK: fsle.d $w18, $w23, $w24 +0x7b 0x06 0x2b 0x1a # CHECK: fslt.w $w12, $w5, $w6 +0x7b 0x35 0xd4 0x1a # CHECK: fslt.d $w16, $w26, $w21 +0x7a 0xcc 0x0f 0x9c # CHECK: fsne.w $w30, $w1, $w12 +0x7a 0xf7 0x6b 0x9c # CHECK: fsne.d $w14, $w13, $w23 +0x7a 0x5b 0x6e 0xdc # CHECK: fsor.w $w27, $w13, $w27 +0x7a 0x6b 0xc3 0x1c # CHECK: fsor.d $w12, $w24, $w11 +0x78 0x41 0xd7 0xdb # CHECK: fsub.w $w31, $w26, $w1 +0x78 0x7b 0x8c 0xdb # CHECK: fsub.d $w19, $w17, $w27 +0x7a 0xd9 0xc4 0x1a # CHECK: fsueq.w $w16, $w24, $w25 +0x7a 0xee 0x74 0x9a # CHECK: fsueq.d $w18, $w14, $w14 +0x7b 0xcd 0xf5 0xda # CHECK: fsule.w $w23, $w30, $w13 +0x7b 0xfa 0x58 0x9a # CHECK: fsule.d $w2, $w11, $w26 +0x7b 0x56 0xd2 0xda # CHECK: fsult.w $w11, $w26, $w22 +0x7b 0x7e 0xb9 0x9a # CHECK: fsult.d $w6, $w23, $w30 +0x7a 0x5c 0x90 0xda # CHECK: fsun.w $w3, $w18, $w28 +0x7a 0x73 0x5c 0x9a # CHECK: fsun.d $w18, $w11, $w19 +0x7a 0x82 0xfc 0x1c # CHECK: fsune.w $w16, $w31, $w2 +0x7a 0xb1 0xd0 0xdc # CHECK: fsune.d $w3, $w26, $w17 +0x7a 0x98 0x24 0x1b # CHECK: ftq.h $w16, $w4, $w24 +0x7a 0xb9 0x29 0x5b # CHECK: ftq.w $w5, $w5, $w25 +0x79 0x4a 0xa4 0x1c # CHECK: madd_q.h $w16, $w20, $w10 +0x79 0x69 0x17 0x1c # CHECK: madd_q.w $w28, $w2, $w9 +0x7b 0x49 0x92 0x1c # CHECK: maddr_q.h $w8, $w18, $w9 +0x7b 0x70 0x67 0x5c # CHECK: maddr_q.w $w29, $w12, $w16 +0x79 0x8a 0xd6 0x1c # CHECK: msub_q.h $w24, $w26, $w10 +0x79 0xbc 0xf3 0x5c # CHECK: msub_q.w $w13, $w30, $w28 +0x7b 0x8b 0xab 0x1c # CHECK: msubr_q.h $w12, $w21, $w11 +0x7b 0xb4 0x70 0x5c # CHECK: msubr_q.w $w1, $w14, $w20 +0x79 0x1e 0x81 0x9c # CHECK: mul_q.h $w6, $w16, $w30 +0x79 0x24 0x0c 0x1c # CHECK: mul_q.w $w16, $w1, $w4 +0x7b 0x13 0xa1 0x9c # CHECK: mulr_q.h $w6, $w20, $w19 +0x7b 0x34 0x0e 0xdc # CHECK: mulr_q.w $w27, $w1, $w20 diff --git a/test/MC/Disassembler/Mips/msa/test_bit.txt b/test/MC/Disassembler/Mips/msa/test_bit.txt new file mode 100644 index 0000000..422d71e --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_bit.txt @@ -0,0 +1,50 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x79 0xf2 0xf5 0x49 # CHECK: bclri.b $w21, $w30, 2 +0x79 0xe0 0xae 0x09 # CHECK: bclri.h $w24, $w21, 0 +0x79 0xc3 0xf5 0xc9 # CHECK: bclri.w $w23, $w30, 3 +0x79 0x80 0x5a 0x49 # CHECK: bclri.d $w9, $w11, 0 +0x7b 0x71 0x66 0x49 # CHECK: binsli.b $w25, $w12, 1 +0x7b 0x60 0xb5 0x49 # CHECK: binsli.h $w21, $w22, 0 +0x7b 0x40 0x25 0x89 # CHECK: binsli.w $w22, $w4, 0 +0x7b 0x06 0x11 0x89 # CHECK: binsli.d $w6, $w2, 6 +0x7b 0xf0 0x9b 0xc9 # CHECK: binsri.b $w15, $w19, 0 +0x7b 0xe1 0xf2 0x09 # CHECK: binsri.h $w8, $w30, 1 +0x7b 0xc5 0x98 0x89 # CHECK: binsri.w $w2, $w19, 5 +0x7b 0x81 0xa4 0x89 # CHECK: binsri.d $w18, $w20, 1 +0x7a 0xf0 0x9e 0x09 # CHECK: bnegi.b $w24, $w19, 0 +0x7a 0xe3 0x5f 0x09 # CHECK: bnegi.h $w28, $w11, 3 +0x7a 0xc5 0xd8 0x49 # CHECK: bnegi.w $w1, $w27, 5 +0x7a 0x81 0xa9 0x09 # CHECK: bnegi.d $w4, $w21, 1 +0x7a 0x70 0x44 0x89 # CHECK: bseti.b $w18, $w8, 0 +0x7a 0x62 0x76 0x09 # CHECK: bseti.h $w24, $w14, 2 +0x7a 0x44 0x92 0x49 # CHECK: bseti.w $w9, $w18, 4 +0x7a 0x01 0x79 0xc9 # CHECK: bseti.d $w7, $w15, 1 +0x78 0x72 0xff 0xca # CHECK: sat_s.b $w31, $w31, 2 +0x78 0x60 0x9c 0xca # CHECK: sat_s.h $w19, $w19, 0 +0x78 0x40 0xec 0xca # CHECK: sat_s.w $w19, $w29, 0 +0x78 0x00 0xb2 0xca # CHECK: sat_s.d $w11, $w22, 0 +0x78 0xf3 0x68 0x4a # CHECK: sat_u.b $w1, $w13, 3 +0x78 0xe4 0xc7 0x8a # CHECK: sat_u.h $w30, $w24, 4 +0x78 0xc0 0x6f 0xca # CHECK: sat_u.w $w31, $w13, 0 +0x78 0x85 0x87 0x4a # CHECK: sat_u.d $w29, $w16, 5 +0x78 0x71 0x55 0xc9 # CHECK: slli.b $w23, $w10, 1 +0x78 0x61 0x92 0x49 # CHECK: slli.h $w9, $w18, 1 +0x78 0x44 0xea 0xc9 # CHECK: slli.w $w11, $w29, 4 +0x78 0x01 0xa6 0x49 # CHECK: slli.d $w25, $w20, 1 +0x78 0xf1 0xee 0x09 # CHECK: srai.b $w24, $w29, 1 +0x78 0xe0 0x30 0x49 # CHECK: srai.h $w1, $w6, 0 +0x78 0xc1 0xd1 0xc9 # CHECK: srai.w $w7, $w26, 1 +0x78 0x83 0xcd 0x09 # CHECK: srai.d $w20, $w25, 3 +0x79 0x70 0xc9 0x4a # CHECK: srari.b $w5, $w25, 0 +0x79 0x64 0x31 0xca # CHECK: srari.h $w7, $w6, 4 +0x79 0x45 0x5c 0x4a # CHECK: srari.w $w17, $w11, 5 +0x79 0x05 0xcd 0x4a # CHECK: srari.d $w21, $w25, 5 +0x79 0x72 0x00 0x89 # CHECK: srli.b $w2, $w0, 2 +0x79 0x62 0xff 0xc9 # CHECK: srli.h $w31, $w31, 2 +0x79 0x44 0x49 0x49 # CHECK: srli.w $w5, $w9, 4 +0x79 0x05 0xd6 0xc9 # CHECK: srli.d $w27, $w26, 5 +0x79 0xf0 0x1c 0x8a # CHECK: srlri.b $w18, $w3, 0 +0x79 0xe3 0x10 0x4a # CHECK: srlri.h $w1, $w2, 3 +0x79 0xc2 0xb2 0xca # CHECK: srlri.w $w11, $w22, 2 +0x79 0x86 0x56 0x0a # CHECK: srlri.d $w24, $w10, 6 diff --git a/test/MC/Disassembler/Mips/msa/test_ctrlregs.txt b/test/MC/Disassembler/Mips/msa/test_ctrlregs.txt new file mode 100644 index 0000000..fb5b0be --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_ctrlregs.txt @@ -0,0 +1,35 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x78 0x7e 0x00 0x59 # CHECK: cfcmsa $1, $0 +0x78 0x7e 0x00 0x59 # CHECK: cfcmsa $1, $0 +0x78 0x7e 0x08 0x99 # CHECK: cfcmsa $2, $1 +0x78 0x7e 0x08 0x99 # CHECK: cfcmsa $2, $1 +0x78 0x7e 0x10 0xd9 # CHECK: cfcmsa $3, $2 +0x78 0x7e 0x10 0xd9 # CHECK: cfcmsa $3, $2 +0x78 0x7e 0x19 0x19 # CHECK: cfcmsa $4, $3 +0x78 0x7e 0x19 0x19 # CHECK: cfcmsa $4, $3 +0x78 0x7e 0x21 0x59 # CHECK: cfcmsa $5, $4 +0x78 0x7e 0x21 0x59 # CHECK: cfcmsa $5, $4 +0x78 0x7e 0x29 0x99 # CHECK: cfcmsa $6, $5 +0x78 0x7e 0x29 0x99 # CHECK: cfcmsa $6, $5 +0x78 0x7e 0x31 0xd9 # CHECK: cfcmsa $7, $6 +0x78 0x7e 0x31 0xd9 # CHECK: cfcmsa $7, $6 +0x78 0x7e 0x3a 0x19 # CHECK: cfcmsa $8, $7 +0x78 0x7e 0x3a 0x19 # CHECK: cfcmsa $8, $7 + +0x78 0x3e 0x08 0x19 # CHECK: ctcmsa $0, $1 +0x78 0x3e 0x08 0x19 # CHECK: ctcmsa $0, $1 +0x78 0x3e 0x10 0x59 # CHECK: ctcmsa $1, $2 +0x78 0x3e 0x10 0x59 # CHECK: ctcmsa $1, $2 +0x78 0x3e 0x18 0x99 # CHECK: ctcmsa $2, $3 +0x78 0x3e 0x18 0x99 # CHECK: ctcmsa $2, $3 +0x78 0x3e 0x20 0xd9 # CHECK: ctcmsa $3, $4 +0x78 0x3e 0x20 0xd9 # CHECK: ctcmsa $3, $4 +0x78 0x3e 0x29 0x19 # CHECK: ctcmsa $4, $5 +0x78 0x3e 0x29 0x19 # CHECK: ctcmsa $4, $5 +0x78 0x3e 0x31 0x59 # CHECK: ctcmsa $5, $6 +0x78 0x3e 0x31 0x59 # CHECK: ctcmsa $5, $6 +0x78 0x3e 0x39 0x99 # CHECK: ctcmsa $6, $7 +0x78 0x3e 0x39 0x99 # CHECK: ctcmsa $6, $7 +0x78 0x3e 0x41 0xd9 # CHECK: ctcmsa $7, $8 +0x78 0x3e 0x41 0xd9 # CHECK: ctcmsa $7, $8 diff --git a/test/MC/Disassembler/Mips/msa/test_dlsa.txt b/test/MC/Disassembler/Mips/msa/test_dlsa.txt new file mode 100644 index 0000000..2a1d90b --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_dlsa.txt @@ -0,0 +1,6 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r2 -mattr=+msa | FileCheck %s + +0x01 0x2a 0x40 0x15 # CHECK: dlsa $8, $9, $10, 1 +0x01 0x2a 0x40 0x55 # CHECK: dlsa $8, $9, $10, 2 +0x01 0x2a 0x40 0x95 # CHECK: dlsa $8, $9, $10, 3 +0x01 0x2a 0x40 0xd5 # CHECK: dlsa $8, $9, $10, 4 diff --git a/test/MC/Disassembler/Mips/msa/test_elm.txt b/test/MC/Disassembler/Mips/msa/test_elm.txt new file mode 100644 index 0000000..832587b --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_elm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x78 0x82 0x43 0x59 # CHECK: copy_s.b $13, $w8[2] +0x78 0xa0 0xc8 0x59 # CHECK: copy_s.h $1, $w25[0] +0x78 0xb1 0x2d 0x99 # CHECK: copy_s.w $22, $w5[1] +0x78 0xc4 0xa5 0x99 # CHECK: copy_u.b $22, $w20[4] +0x78 0xe0 0x25 0x19 # CHECK: copy_u.h $20, $w4[0] +0x78 0xf2 0x6f 0x99 # CHECK: copy_u.w $fp, $w13[2] +0x78 0x04 0xe8 0x19 # CHECK: sldi.b $w0, $w29[4] +0x78 0x20 0x8a 0x19 # CHECK: sldi.h $w8, $w17[0] +0x78 0x32 0xdd 0x19 # CHECK: sldi.w $w20, $w27[2] +0x78 0x38 0x61 0x19 # CHECK: sldi.d $w4, $w12[0] +0x78 0x42 0x1e 0x59 # CHECK: splati.b $w25, $w3[2] +0x78 0x61 0xe6 0x19 # CHECK: splati.h $w24, $w28[1] +0x78 0x70 0x93 0x59 # CHECK: splati.w $w13, $w18[0] +0x78 0x78 0x0f 0x19 # CHECK: splati.d $w28, $w1[0] +0x78 0xbe 0xc5 0xd9 # CHECK: move.v $w23, $w24 diff --git a/test/MC/Disassembler/Mips/msa/test_elm_insert.txt b/test/MC/Disassembler/Mips/msa/test_elm_insert.txt new file mode 100644 index 0000000..605d495 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_elm_insert.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x79 0x03 0xed 0xd9 # CHECK: insert.b $w23[3], $sp +0x79 0x22 0x2d 0x19 # CHECK: insert.h $w20[2], $5 +0x79 0x32 0x7a 0x19 # CHECK: insert.w $w8[2], $15 diff --git a/test/MC/Disassembler/Mips/msa/test_elm_insert_msa64.txt b/test/MC/Disassembler/Mips/msa/test_elm_insert_msa64.txt new file mode 100644 index 0000000..62920f3 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_elm_insert_msa64.txt @@ -0,0 +1,3 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r2 -mattr=+msa | FileCheck %s + +0x79 0x39 0xe8 0x59 # CHECK: insert.d $w1[1], $sp diff --git a/test/MC/Disassembler/Mips/msa/test_elm_insve.txt b/test/MC/Disassembler/Mips/msa/test_elm_insve.txt new file mode 100644 index 0000000..c5c3ba0 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_elm_insve.txt @@ -0,0 +1,6 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x79 0x43 0x4e 0x59 # CHECK: insve.b $w25[3], $w9[0] +0x79 0x62 0x16 0x19 # CHECK: insve.h $w24[2], $w2[0] +0x79 0x72 0x68 0x19 # CHECK: insve.w $w0[2], $w13[0] +0x79 0x78 0x90 0xd9 # CHECK: insve.d $w3[0], $w18[0] diff --git a/test/MC/Disassembler/Mips/msa/test_elm_msa64.txt b/test/MC/Disassembler/Mips/msa/test_elm_msa64.txt new file mode 100644 index 0000000..70c831a --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_elm_msa64.txt @@ -0,0 +1,6 @@ +# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r2 -mattr=+msa | FileCheck %s + +# CHECK: copy_s.d $19, $w31[0] +0x78 0xb8 0xfc 0xd9 +# CHECK: copy_u.d $18, $w29[1] +0x78 0xf9 0xec 0x99 diff --git a/test/MC/Disassembler/Mips/msa/test_i10.txt b/test/MC/Disassembler/Mips/msa/test_i10.txt new file mode 100644 index 0000000..ac95d88 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_i10.txt @@ -0,0 +1,6 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32 -mattr=+msa | FileCheck %s + +0x7b 0x06 0x32 0x07 # CHECK: ldi.b $w8, 198 +0x7b 0x29 0xcd 0x07 # CHECK: ldi.h $w20, 313 +0x7b 0x4f 0x66 0x07 # CHECK: ldi.w $w24, 492 +0x7b 0x7a 0x66 0xc7 # CHECK: ldi.d $w27, 844 diff --git a/test/MC/Disassembler/Mips/msa/test_i5.txt b/test/MC/Disassembler/Mips/msa/test_i5.txt new file mode 100644 index 0000000..bf5bc51 --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_i5.txt @@ -0,0 +1,46 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32 -mattr=+msa | FileCheck %s + +0x78 0x1e 0xf8 0xc6 # CHECK: addvi.b $w3, $w31, 30 +0x78 0x3a 0x6e 0x06 # CHECK: addvi.h $w24, $w13, 26 +0x78 0x5a 0xa6 0x86 # CHECK: addvi.w $w26, $w20, 26 +0x78 0x75 0x0c 0x06 # CHECK: addvi.d $w16, $w1, 21 +0x78 0x18 0xae 0x07 # CHECK: ceqi.b $w24, $w21, 24 +0x78 0x22 0x7f 0xc7 # CHECK: ceqi.h $w31, $w15, 2 +0x78 0x5f 0x0b 0x07 # CHECK: ceqi.w $w12, $w1, 31 +0x78 0x67 0xb6 0x07 # CHECK: ceqi.d $w24, $w22, 7 +0x7a 0x01 0x83 0x07 # CHECK: clei_s.b $w12, $w16, 1 +0x7a 0x37 0x50 0x87 # CHECK: clei_s.h $w2, $w10, 23 +0x7a 0x56 0x59 0x07 # CHECK: clei_s.w $w4, $w11, 22 +0x7a 0x76 0xe8 0x07 # CHECK: clei_s.d $w0, $w29, 22 +0x7a 0x83 0x8d 0x47 # CHECK: clei_u.b $w21, $w17, 3 +0x7a 0xb1 0x3f 0x47 # CHECK: clei_u.h $w29, $w7, 17 +0x7a 0xc2 0x08 0x47 # CHECK: clei_u.w $w1, $w1, 2 +0x7a 0xfd 0xde 0xc7 # CHECK: clei_u.d $w27, $w27, 29 +0x79 0x19 0x6c 0xc7 # CHECK: clti_s.b $w19, $w13, 25 +0x79 0x34 0x53 0xc7 # CHECK: clti_s.h $w15, $w10, 20 +0x79 0x4b 0x63 0x07 # CHECK: clti_s.w $w12, $w12, 11 +0x79 0x71 0xa7 0x47 # CHECK: clti_s.d $w29, $w20, 17 +0x79 0x9d 0x4b 0x87 # CHECK: clti_u.b $w14, $w9, 29 +0x79 0xb9 0xce 0x07 # CHECK: clti_u.h $w24, $w25, 25 +0x79 0xd6 0x08 0x47 # CHECK: clti_u.w $w1, $w1, 22 +0x79 0xe1 0xcd 0x47 # CHECK: clti_u.d $w21, $w25, 1 +0x79 0x01 0xad 0x86 # CHECK: maxi_s.b $w22, $w21, 1 +0x79 0x38 0x2f 0x46 # CHECK: maxi_s.h $w29, $w5, 24 +0x79 0x54 0x50 0x46 # CHECK: maxi_s.w $w1, $w10, 20 +0x79 0x70 0xeb 0x46 # CHECK: maxi_s.d $w13, $w29, 16 +0x79 0x8c 0x05 0x06 # CHECK: maxi_u.b $w20, $w0, 12 +0x79 0xa3 0x70 0x46 # CHECK: maxi_u.h $w1, $w14, 3 +0x79 0xcb 0xb6 0xc6 # CHECK: maxi_u.w $w27, $w22, 11 +0x79 0xe4 0x36 0x86 # CHECK: maxi_u.d $w26, $w6, 4 +0x7a 0x01 0x09 0x06 # CHECK: mini_s.b $w4, $w1, 1 +0x7a 0x37 0xde 0xc6 # CHECK: mini_s.h $w27, $w27, 23 +0x7a 0x49 0x5f 0x06 # CHECK: mini_s.w $w28, $w11, 9 +0x7a 0x6a 0x52 0xc6 # CHECK: mini_s.d $w11, $w10, 10 +0x7a 0x9b 0xbc 0x86 # CHECK: mini_u.b $w18, $w23, 27 +0x7a 0xb2 0xd1 0xc6 # CHECK: mini_u.h $w7, $w26, 18 +0x7a 0xda 0x62 0xc6 # CHECK: mini_u.w $w11, $w12, 26 +0x7a 0xe2 0x7a 0xc6 # CHECK: mini_u.d $w11, $w15, 2 +0x78 0x93 0xa6 0x06 # CHECK: subvi.b $w24, $w20, 19 +0x78 0xa4 0x9a 0xc6 # CHECK: subvi.h $w11, $w19, 4 +0x78 0xcb 0x53 0x06 # CHECK: subvi.w $w12, $w10, 11 +0x78 0xe7 0x84 0xc6 # CHECK: subvi.d $w19, $w16, 7 diff --git a/test/MC/Disassembler/Mips/msa/test_i8.txt b/test/MC/Disassembler/Mips/msa/test_i8.txt new file mode 100644 index 0000000..e08c39b --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_i8.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32 -mattr=+msa | FileCheck %s + +0x78 0x30 0xe8 0x80 # CHECK: andi.b $w2, $w29, 48 +0x78 0x7e 0xb1 0x81 # CHECK: bmnzi.b $w6, $w22, 126 +0x79 0x58 0x0e 0xc1 # CHECK: bmzi.b $w27, $w1, 88 +0x7a 0xbd 0x1f 0x41 # CHECK: bseli.b $w29, $w3, 189 +0x7a 0x38 0x88 0x40 # CHECK: nori.b $w1, $w17, 56 +0x79 0x87 0xa6 0x80 # CHECK: ori.b $w26, $w20, 135 +0x78 0x69 0xf4 0xc2 # CHECK: shf.b $w19, $w30, 105 +0x79 0x4c 0x44 0x42 # CHECK: shf.h $w17, $w8, 76 +0x7a 0x5d 0x1b 0x82 # CHECK: shf.w $w14, $w3, 93 +0x7b 0x14 0x54 0x00 # CHECK: xori.b $w16, $w10, 20 diff --git a/test/MC/Disassembler/Mips/msa/test_lsa.txt b/test/MC/Disassembler/Mips/msa/test_lsa.txt new file mode 100644 index 0000000..c3e950b --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_lsa.txt @@ -0,0 +1,6 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 -mattr=+msa | FileCheck %s + +0x01 0x2a 0x40 0x05 # CHECK: lsa $8, $9, $10, 1 +0x01 0x2a 0x40 0x45 # CHECK: lsa $8, $9, $10, 2 +0x01 0x2a 0x40 0x85 # CHECK: lsa $8, $9, $10, 3 +0x01 0x2a 0x40 0xc5 # CHECK: lsa $8, $9, $10, 4 diff --git a/test/MC/Disassembler/Mips/msa/test_mi10.txt b/test/MC/Disassembler/Mips/msa/test_mi10.txt new file mode 100644 index 0000000..b75b49e --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_mi10.txt @@ -0,0 +1,28 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32 -mattr=+msa | FileCheck %s + +0x7a 0x00 0x08 0x20 # CHECK: ld.b $w0, -512($1) +0x78 0x00 0x10 0x60 # CHECK: ld.b $w1, 0($2) +0x79 0xff 0x18 0xa0 # CHECK: ld.b $w2, 511($3) + +0x7a 0x00 0x20 0xe1 # CHECK: ld.h $w3, -1024($4) +0x7b 0x00 0x29 0x21 # CHECK: ld.h $w4, -512($5) +0x78 0x00 0x31 0x61 # CHECK: ld.h $w5, 0($6) +0x79 0x00 0x39 0xa1 # CHECK: ld.h $w6, 512($7) +0x79 0xff 0x41 0xe1 # CHECK: ld.h $w7, 1022($8) + +0x7a 0x00 0x4a 0x22 # CHECK: ld.w $w8, -2048($9) +0x7b 0x00 0x52 0x62 # CHECK: ld.w $w9, -1024($10) +0x7b 0x80 0x5a 0xa2 # CHECK: ld.w $w10, -512($11) +0x78 0x80 0x62 0xe2 # CHECK: ld.w $w11, 512($12) +0x79 0x00 0x6b 0x22 # CHECK: ld.w $w12, 1024($13) +0x79 0xff 0x73 0x62 # CHECK: ld.w $w13, 2044($14) + +0x7a 0x00 0x7b 0xa3 # CHECK: ld.d $w14, -4096($15) +0x7b 0x00 0x83 0xe3 # CHECK: ld.d $w15, -2048($16) +0x7b 0x80 0x8c 0x23 # CHECK: ld.d $w16, -1024($17) +0x7b 0xc0 0x94 0x63 # CHECK: ld.d $w17, -512($18) +0x78 0x00 0x9c 0xa3 # CHECK: ld.d $w18, 0($19) +0x78 0x40 0xa4 0xe3 # CHECK: ld.d $w19, 512($20) +0x78 0x80 0xad 0x23 # CHECK: ld.d $w20, 1024($21) +0x79 0x00 0xb5 0x63 # CHECK: ld.d $w21, 2048($22) +0x79 0xff 0xbd 0xa3 # CHECK: ld.d $w22, 4088($23) diff --git a/test/MC/Disassembler/Mips/msa/test_vec.txt b/test/MC/Disassembler/Mips/msa/test_vec.txt new file mode 100644 index 0000000..eff984f --- /dev/null +++ b/test/MC/Disassembler/Mips/msa/test_vec.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32 -mattr=+msa | FileCheck %s + +0x78 0x1b 0xa6 0x5e # CHECK: and.v $w25, $w20, $w27 +0x78 0x87 0x34 0x5e # CHECK: bmnz.v $w17, $w6, $w7 +0x78 0xa9 0x88 0xde # CHECK: bmz.v $w3, $w17, $w9 +0x78 0xce 0x02 0x1e # CHECK: bsel.v $w8, $w0, $w14 +0x78 0x40 0xf9 0xde # CHECK: nor.v $w7, $w31, $w0 +0x78 0x3e 0xd6 0x1e # CHECK: or.v $w24, $w26, $w30 +0x78 0x6f 0xd9 0xde # CHECK: xor.v $w7, $w27, $w15 diff --git a/test/MC/Disassembler/Sparc/sparc-fp.txt b/test/MC/Disassembler/Sparc/sparc-fp.txt index b279da8..b8a5017 100644 --- a/test/MC/Disassembler/Sparc/sparc-fp.txt +++ b/test/MC/Disassembler/Sparc/sparc-fp.txt @@ -120,13 +120,13 @@ # CHECK: fdivq %f0, %f4, %f8 0x91 0xa0 0x09 0xe4 -# CHECK: fcmps %fcc0, %f0, %f4 +# CHECK: fcmps %f0, %f4 0x81 0xa8 0x0a 0x24 -# CHECK: fcmpd %fcc0, %f0, %f4 +# CHECK: fcmpd %f0, %f4 0x81 0xa8 0x0a 0x44 -# CHECK: fcmpq %fcc0, %f0, %f4 +# CHECK: fcmpq %f0, %f4 0x81 0xa8 0x0a 0x64 # CHECK: fxtos %f0, %f4 diff --git a/test/MC/Disassembler/X86/prefixes.txt b/test/MC/Disassembler/X86/prefixes.txt index 56596e3..b8830dc 100644 --- a/test/MC/Disassembler/X86/prefixes.txt +++ b/test/MC/Disassembler/X86/prefixes.txt @@ -44,6 +44,10 @@ # CHECK-NEXT: nop 0xf0 0x90 +# Test that immediate is printed correctly within opsize prefix +# CHECK: addw $-12, %ax +0x66,0x83,0xc0,0xf4 + # Test that multiple redundant prefixes work (redundant, but valid x86). # CHECK: rep # CHECK-NEXT: rep diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt index a4a0b2c..c9c5086 100644 --- a/test/MC/Disassembler/X86/x86-32.txt +++ b/test/MC/Disassembler/X86/x86-32.txt @@ -708,3 +708,6 @@ # CHECK: movl $4294967295, %eax 0xc7 0xc0 0xff 0xff 0xff 0xff + +# CHECK: movq %mm0, %mm1 +0x0f 0x7f 0xc1 diff --git a/test/MC/ELF/comdat.s b/test/MC/ELF/comdat.s index 05d08e14..68b0f32 100644 --- a/test/MC/ELF/comdat.s +++ b/test/MC/ELF/comdat.s @@ -49,7 +49,7 @@ // Test that g1 and g2 are local, but g3 is an undefined global. // CHECK: Symbol { -// CHECK: Name: g1 (1) +// CHECK: Name: g1 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local @@ -58,7 +58,7 @@ // CHECK-NEXT: Section: .foo (0x7) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: g2 (4) +// CHECK-NEXT: Name: g2 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local @@ -68,7 +68,7 @@ // CHECK-NEXT: } // CHECK: Symbol { -// CHECK: Name: g3 (7) +// CHECK: Name: g3 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global diff --git a/test/MC/ELF/common.s b/test/MC/ELF/common.s index 9cff927..bd96564 100644 --- a/test/MC/ELF/common.s +++ b/test/MC/ELF/common.s @@ -9,7 +9,7 @@ .comm common1,1,1 // CHECK: Symbol { -// CHECK: Name: common1 (1) +// CHECK: Name: common1 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 1 // CHECK-NEXT: Binding: Local @@ -25,7 +25,7 @@ .comm common2,1,1 // CHECK: Symbol { -// CHECK: Name: common2 (9) +// CHECK: Name: common2 // CHECK-NEXT: Value: 0x1 // CHECK-NEXT: Size: 1 // CHECK-NEXT: Binding: Local @@ -39,7 +39,7 @@ .comm common6,8,16 // CHECK: Symbol { -// CHECK: Name: common6 (17) +// CHECK: Name: common6 // CHECK-NEXT: Value: 0x10 // CHECK-NEXT: Size: 8 // CHECK-NEXT: Binding: Local @@ -54,7 +54,7 @@ .comm common3,4,4 // CHECK: Symbol { -// CHECK: Name: common3 (25) +// CHECK: Name: common3 // CHECK-NEXT: Value: 0x4 // CHECK-NEXT: Size: 4 // CHECK-NEXT: Binding: Global @@ -76,7 +76,7 @@ foo: .comm common4,40,16 // CHECK: Symbol { -// CHECK: Name: common4 (37) +// CHECK: Name: common4 // CHECK-NEXT: Value: 0x10 // CHECK-NEXT: Size: 40 // CHECK-NEXT: Binding: Global @@ -89,7 +89,7 @@ foo: .comm common5,4,4 // CHECK: Symbol { -// CHECK: Name: common5 (45) +// CHECK: Name: common5 // CHECK-NEXT: Value: 0x4 // CHECK-NEXT: Size: 4 // CHECK-NEXT: Binding: Global diff --git a/test/MC/ELF/comp-dir.s b/test/MC/ELF/comp-dir.s index 1b91f64..c8d996f 100644 --- a/test/MC/ELF/comp-dir.s +++ b/test/MC/ELF/comp-dir.s @@ -1,5 +1,4 @@ // REQUIRES: shell -// XFAIL: mingw // RUN: llvm-mc -triple=x86_64-linux-unknown -g -fdebug-compilation-dir=/test/comp/dir %s -filetype=obj -o %t.o // RUN: llvm-dwarfdump -debug-dump=info %t.o | FileCheck %s diff --git a/test/MC/ELF/compression.s b/test/MC/ELF/compression.s index 305a84e..07b689e 100644 --- a/test/MC/ELF/compression.s +++ b/test/MC/ELF/compression.s @@ -1,28 +1,80 @@ -// RUN: llvm-mc -filetype=obj -compress-debug-sections -triple x86_64-pc-linux-gnu %s -o - | llvm-objdump -s - | FileCheck %s +// RUN: llvm-mc -filetype=obj -compress-debug-sections -triple x86_64-pc-linux-gnu < %s -o %t +// RUN: llvm-objdump -s %t | FileCheck %s +// RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck --check-prefix=INFO %s +// RUN: llvm-mc -filetype=obj -compress-debug-sections -triple i386-pc-linux-gnu < %s \ +// RUN: | llvm-readobj -symbols - | FileCheck --check-prefix=386-SYMBOLS %s // REQUIRES: zlib -// CHECK: Contents of section .debug_line: -// FIXME: Figure out how to handle debug_line that currently uses multiple section fragments +// CHECK: Contents of section .zdebug_line: +// Check for the 'ZLIB' file magic at the start of the section only +// CHECK-NEXT: ZLIB // CHECK-NOT: ZLIB +// CHECK: Contents of -// CHECK: Contents of section .zdebug_abbrev: -// Check for the 'ZLIB' file magic at the start of the section -// CHECK-NEXT: ZLIB +// Don't compress small sections, such as this simple debug_abbrev example +// CHECK: Contents of section .debug_abbrev: +// CHECK-NOT: ZLIB +// CHECK-NOT: Contents of + +// CHECK: Contents of section .debug_info: -// We shouldn't compress the debug_frame section, since it can be relaxed -// CHECK: Contents of section .debug_frame +// FIXME: Handle compressing alignment fragments to support compressing debug_frame +// CHECK: Contents of section .debug_frame: // CHECK-NOT: ZLIB +// CHECK: Contents of + +// Decompress one valid dwarf section just to check that this roundtrips +// INFO: 0x00000000: Compile Unit: length = 0x0000000c version = 0x0004 abbr_offset = 0x0000 addr_size = 0x08 (next unit at 0x00000010) + +// In x86 32 bit named symbols are used for temporary symbols in merge +// sections, so make sure we handle symbols inside compressed sections +// 386-SYMBOLS: Name: .Linfo_string0 +// 386-SYMBOLS-NOT: } +// 386-SYMBOLS: Section: .zdebug_str .section .debug_line,"",@progbits .section .debug_abbrev,"",@progbits +.Lsection_abbrev: .byte 1 # Abbreviation Code + .byte 17 # DW_TAG_compile_unit + .byte 0 # DW_CHILDREN_no + .byte 27 # DW_AT_comp_dir + .byte 14 # DW_FORM_strp + .byte 0 # EOM(1) + .byte 0 # EOM(2) + + .section .debug_info,"",@progbits + .long 12 # Length of Unit + .short 4 # DWARF version number + .long .Lsection_abbrev # Offset Into Abbrev. Section + .byte 8 # Address Size (in bytes) + .byte 1 # Abbrev [1] DW_TAG_compile_unit + .long .Linfo_string0 # DW_AT_comp_dir + .text foo: .cfi_startproc .file 1 "Driver.ii" +# pad out the line table to make sure it's big enough to warrant compression .loc 1 2 0 nop + .loc 1 3 0 + nop + .loc 1 4 0 + nop + .loc 1 5 0 + nop + .loc 1 6 0 + nop + .loc 1 7 0 + nop + .loc 1 8 0 + nop .cfi_endproc .cfi_sections .debug_frame + + .section .debug_str,"MS",@progbits,1 +.Linfo_string0: + .asciz "compress this " diff --git a/test/MC/ELF/file-double.s b/test/MC/ELF/file-double.s index f9b91ed..b5da8c5 100644 --- a/test/MC/ELF/file-double.s +++ b/test/MC/ELF/file-double.s @@ -11,7 +11,7 @@ foo.c: bar.c: // CHECK: Symbol { -// CHECK: Name: foo.c (1) +// CHECK: Name: foo.c // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local @@ -19,7 +19,7 @@ bar.c: // CHECK-NEXT: Other: 0 // CHECK-NEXT: Section: Absolute (0xFFF1) // CHECK-NEXT: } -// CHECK: Name: bar.c (7) +// CHECK: Name: bar.c // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local @@ -28,7 +28,7 @@ bar.c: // CHECK-NEXT: Section: Absolute (0xFFF1) // CHECK-NEXT: } // CHECK: Symbol { -// CHECK: Name: bar.c (7) +// CHECK: Name: bar.c // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -37,7 +37,7 @@ bar.c: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK: Symbol { -// CHECK: Name: foo.c (1) +// CHECK: Name: foo.c // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global diff --git a/test/MC/ELF/gen-dwarf.s b/test/MC/ELF/gen-dwarf.s index 946119b..7f0c059 100644 --- a/test/MC/ELF/gen-dwarf.s +++ b/test/MC/ELF/gen-dwarf.s @@ -1,5 +1,9 @@ -// RUN: llvm-mc -g -triple i686-pc-linux-gnu %s -filetype=obj -o - | llvm-readobj -r | FileCheck %s -// RUN: llvm-mc -g -triple i686-pc-linux-gnu %s -filetype=asm -o - | FileCheck --check-prefix=ASM %s +// RUN: llvm-mc -g -dwarf-version 2 -triple i686-pc-linux-gnu %s -filetype=obj -o - | llvm-readobj -r | FileCheck %s +// RUN: not llvm-mc -g -dwarf-version 1 -triple i686-pc-linux-gnu %s -filetype=asm -o - 2>&1 | FileCheck --check-prefix=DWARF1 %s +// RUN: llvm-mc -g -dwarf-version 2 -triple i686-pc-linux-gnu %s -filetype=asm -o - | FileCheck --check-prefix=ASM --check-prefix=DWARF2 %s +// RUN: llvm-mc -g -dwarf-version 3 -triple i686-pc-linux-gnu %s -filetype=asm -o - | FileCheck --check-prefix=ASM --check-prefix=DWARF3 %s +// RUN: llvm-mc -g -triple i686-pc-linux-gnu %s -filetype=asm -o - | FileCheck --check-prefix=ASM --check-prefix=DWARF4 %s +// RUN: not llvm-mc -g -dwarf-version 5 -triple i686-pc-linux-gnu %s -filetype=asm -o - 2>&1 | FileCheck --check-prefix=DWARF5 %s // Test that on ELF: @@ -35,7 +39,9 @@ foo: // Second instance of the section has the CU // ASM: .section .debug_info // Dwarf version -// ASM: .short 2 +// DWARF2: .short 2 +// DWARF3: .short 3 +// DWARF4: .short 4 // ASM-NEXT: .long [[ABBREV_LABEL]] // First .byte 1 is the abbreviation number for the compile_unit abbrev // ASM: .byte 1 @@ -44,3 +50,5 @@ foo: // ASM: .section .debug_line // ASM-NEXT: [[LINE_LABEL]] +// DWARF1: Dwarf version 1 is not supported. +// DWARF5: Dwarf version 5 is not supported. diff --git a/test/MC/ELF/lcomm.s b/test/MC/ELF/lcomm.s index 430b79b..7d8ac3f 100644 --- a/test/MC/ELF/lcomm.s +++ b/test/MC/ELF/lcomm.s @@ -4,7 +4,7 @@ .lcomm B, 32 << 20 // CHECK: Symbol { -// CHECK: Name: A (1) +// CHECK: Name: A // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 5 // CHECK-NEXT: Binding: Local @@ -13,7 +13,7 @@ // CHECK-NEXT: Section: .bss (0x3) // CHECK-NEXT: } // CHECK: Symbol { -// CHECK: Name: B (3) +// CHECK: Name: B // CHECK-NEXT: Value: 0x5 // CHECK-NEXT: Size: 33554432 // CHECK-NEXT: Binding: Local diff --git a/test/MC/ELF/many-sections-2.s b/test/MC/ELF/many-sections-2.s index d1f9d00..88a4822 100644 --- a/test/MC/ELF/many-sections-2.s +++ b/test/MC/ELF/many-sections-2.s @@ -12,7 +12,7 @@ // Test that both a and b show up in the correct section. -// SYMBOLS: Name: a (1) +// SYMBOLS: Name: a // SYMBOLS-NEXT: Value: 0x0 // SYMBOLS-NEXT: Size: 0 // SYMBOLS-NEXT: Binding: Local (0x0) @@ -21,7 +21,7 @@ // SYMBOLS-NEXT: Section: last (0xFF00) // SYMBOLS-NEXT: } // SYMBOLS-NEXT: Symbol { -// SYMBOLS-NEXT: Name: b (3) +// SYMBOLS-NEXT: Name: b // SYMBOLS-NEXT: Value: 0x1 // SYMBOLS-NEXT: Size: 0 // SYMBOLS-NEXT: Binding: Local (0x0) @@ -32,7 +32,7 @@ // Test that this file has one section too many. -// SYMBOLS: Name: last (0) +// SYMBOLS: Name: last // SYMBOLS-NEXT: Value: 0x0 // SYMBOLS-NEXT: Size: 0 // SYMBOLS-NEXT: Binding: Local (0x0) diff --git a/test/MC/ELF/noexec.s b/test/MC/ELF/noexec.s index 33cb8ae..28f50cb 100644 --- a/test/MC/ELF/noexec.s +++ b/test/MC/ELF/noexec.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -mc-no-exec-stack -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -t | FileCheck %s +// RUN: llvm-mc -no-exec-stack -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -t | FileCheck %s // CHECK: Section { // CHECK: Index: 4 diff --git a/test/MC/ELF/offset.s b/test/MC/ELF/offset.s index a412619..f448332 100644 --- a/test/MC/ELF/offset.s +++ b/test/MC/ELF/offset.s @@ -71,3 +71,62 @@ sym_f = sym_a + (1 - 1) // CHECK-NEXT: Other: 0 // CHECK-NEXT: Section: .data // CHECK-NEXT: } + + + .globl test2_a + .globl test2_b + .globl test2_c + .globl test2_d + .globl test2_e +test2_a: + .long 0 +test2_b = test2_a +test2_c: + .long 0 +test2_d = test2_c +test2_e = test2_d - test2_b +// CHECK: Symbol { +// CHECK: Name: test2_a +// CHECK-NEXT: Value: 0x5 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .data +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: test2_b +// CHECK-NEXT: Value: 0x5 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .data +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: test2_c +// CHECK-NEXT: Value: 0x9 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .data +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: test2_d +// CHECK-NEXT: Value: 0x9 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .data +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: test2_e +// CHECK-NEXT: Value: 0x4 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: Absolute +// CHECK-NEXT: } diff --git a/test/MC/ELF/pic-diff.s b/test/MC/ELF/pic-diff.s index 30c9278..5f0b145 100644 --- a/test/MC/ELF/pic-diff.s +++ b/test/MC/ELF/pic-diff.s @@ -7,7 +7,7 @@ // CHECK-NEXT: ] // CHECK: Symbol { -// CHECK: Name: baz (5) +// CHECK: Name: baz // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global diff --git a/test/MC/ELF/pr9292.s b/test/MC/ELF/pr9292.s index a433650..1e01194 100644 --- a/test/MC/ELF/pr9292.s +++ b/test/MC/ELF/pr9292.s @@ -8,7 +8,7 @@ mov %eax,bar // CHECK: Symbol { -// CHECK: Name: bar (5) +// CHECK: Name: bar // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -17,7 +17,7 @@ mov %eax,bar // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: foo (1) +// CHECK-NEXT: Name: foo // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global diff --git a/test/MC/ELF/relocation-386.s b/test/MC/ELF/relocation-386.s index 4ddfd00..ba12df0 100644 --- a/test/MC/ELF/relocation-386.s +++ b/test/MC/ELF/relocation-386.s @@ -62,6 +62,7 @@ // CHECK-NEXT: 0x9E R_386_PC16 und_symbol 0x0 // Relocation 28 (und_symbol-bar2) is of type R_386_PC8 // CHECK-NEXT: 0xA0 R_386_PC8 und_symbol 0x0 +// CHECK-NEXT: 0xA3 R_386_GOTOFF und_symbol 0x0 // CHECK-NEXT: } // CHECK-NEXT: ] @@ -127,6 +128,8 @@ bar2: .word und_symbol-bar2 .byte und_symbol-bar2 + leal 1 + und_symbol@GOTOFF, %edi + .section zedsec,"awT",@progbits zed: .long 0 diff --git a/test/MC/ELF/relocation.s b/test/MC/ELF/relocation.s index d2ee6af..c0e6007 100644 --- a/test/MC/ELF/relocation.s +++ b/test/MC/ELF/relocation.s @@ -25,9 +25,15 @@ bar: .word foo-bar .byte foo-bar + # this should probably be an error... zed = foo +2 call zed@PLT + leaq -1+foo(%rip), %r11 + + movl $_GLOBAL_OFFSET_TABLE_, %eax + movabs $_GLOBAL_OFFSET_TABLE_, %rax + // CHECK: Section { // CHECK: Name: .rela.text // CHECK: Relocations [ @@ -52,7 +58,10 @@ bar: // CHECK-NEXT: 0x85 R_X86_64_TPOFF64 baz 0x0 // CHECK-NEXT: 0x8D R_X86_64_PC16 foo 0x8D // CHECK-NEXT: 0x8F R_X86_64_PC8 foo 0x8F -// CHECK-NEXT: 0x91 R_X86_64_PLT32 foo 0xFFFFFFFFFFFFFFFE +// CHECK-NEXT: 0x91 R_X86_64_PLT32 zed 0xFFFFFFFFFFFFFFFC +// CHECK-NEXT: 0x98 R_X86_64_PC32 foo 0xFFFFFFFFFFFFFFFB +// CHECK-NEXT: 0x9D R_X86_64_GOTPC32 _GLOBAL_OFFSET_TABLE_ 0x1 +// CHECK-NEXT: 0xA3 R_X86_64_GOTPC64 _GLOBAL_OFFSET_TABLE_ 0x2 // CHECK-NEXT: ] // CHECK-NEXT: } diff --git a/test/MC/ELF/set.s b/test/MC/ELF/set.s index 80e7e53..b4f77f5 100644 --- a/test/MC/ELF/set.s +++ b/test/MC/ELF/set.s @@ -5,7 +5,7 @@ .set kernbase,0xffffffff80000000 // CHECK: Symbol { -// CHECK: Name: kernbase (1) +// CHECK: Name: kernbase // CHECK-NEXT: Value: 0xFFFFFFFF80000000 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local @@ -26,7 +26,7 @@ // Test that there is an undefined reference to bar // CHECK: Symbol { -// CHECK: Name: bar (10) +// CHECK: Name: bar // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global diff --git a/test/MC/ELF/strtab-suffix-opt.s b/test/MC/ELF/strtab-suffix-opt.s new file mode 100644 index 0000000..eb5da8a --- /dev/null +++ b/test/MC/ELF/strtab-suffix-opt.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | llvm-readobj -symbols | FileCheck %s + + .text + .globl foobar + .align 16, 0x90 + .type foobar,@function +foobar: + pushl %ebp + movl %esp, %ebp + subl $8, %esp + calll foo + calll bar + addl $8, %esp + popl %ebp + retl +.Ltmp3: + .size foobar, .Ltmp3-foobar + +// CHECK: Name: foobar (1) +// CHECK: Name: bar (4) +// CHECK: Name: foo (8) diff --git a/test/MC/ELF/subtraction-error.s b/test/MC/ELF/subtraction-error.s new file mode 100644 index 0000000..6b93d3a --- /dev/null +++ b/test/MC/ELF/subtraction-error.s @@ -0,0 +1,8 @@ +// RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux < %s 2>&1 | FileCheck %s + +a: + .section foo +b: +c = b - a + +; CHECK: symbol 'a' could not be evaluated in a subtraction expression diff --git a/test/MC/ELF/symref.s b/test/MC/ELF/symver.s index 737683b..6e5825f 100644 --- a/test/MC/ELF/symref.s +++ b/test/MC/ELF/symver.s @@ -32,111 +32,111 @@ global1: // CHECK-NEXT: ] // CHECK: Symbol { -// CHECK: Name: bar1@zed (19) +// CHECK: Name: bar1@zed // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local // CHECK-NEXT: Type: None // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: Section: .text // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar3@@zed (37) +// CHECK-NEXT: Name: bar3@@zed // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local // CHECK-NEXT: Type: None // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: Section: .text // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar5@@zed (47) +// CHECK-NEXT: Name: bar5@@zed // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local // CHECK-NEXT: Type: None // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: Section: .text // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: defined1 (1) +// CHECK-NEXT: Name: defined1 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local // CHECK-NEXT: Type: None // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: Section: .text // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: defined2 (10) +// CHECK-NEXT: Name: defined2 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local // CHECK-NEXT: Type: None // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: Section: .text // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: .text (0) +// CHECK-NEXT: Name: .text // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local // CHECK-NEXT: Type: Section // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: Section: .text // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: .data (0) +// CHECK-NEXT: Name: .data // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local // CHECK-NEXT: Type: Section // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .data (0x3) +// CHECK-NEXT: Section: .data // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: .bss (0) +// CHECK-NEXT: Name: .bss // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local // CHECK-NEXT: Type: Section // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .bss (0x4) +// CHECK-NEXT: Section: .bss // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: g1@@zed (74) +// CHECK-NEXT: Name: g1@@zed // CHECK-NEXT: Value: 0x14 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global // CHECK-NEXT: Type: None // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: Section: .text // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: global1 (66) +// CHECK-NEXT: Name: global1 // CHECK-NEXT: Value: 0x14 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global // CHECK-NEXT: Type: None // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: Section: .text // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar2@zed (28) +// CHECK-NEXT: Name: bar2@zed // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global // CHECK-NEXT: Type: None // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: Undefined (0x0) +// CHECK-NEXT: Section: Undefined // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar6@zed (57) +// CHECK-NEXT: Name: bar6@zed // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global // CHECK-NEXT: Type: None // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: Undefined (0x0) +// CHECK-NEXT: Section: Undefined // CHECK-NEXT: } // CHECK-NEXT: ] diff --git a/test/MC/ELF/tls-i386.s b/test/MC/ELF/tls-i386.s index 88e96ff..5ee3668 100644 --- a/test/MC/ELF/tls-i386.s +++ b/test/MC/ELF/tls-i386.s @@ -18,7 +18,7 @@ .long fooE@INDNTPOFF // CHECK: Symbol { -// CHECK: Name: foo1 (1) +// CHECK: Name: foo1 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -27,7 +27,7 @@ // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: foo2 (6) +// CHECK-NEXT: Name: foo2 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -36,7 +36,7 @@ // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: foo3 (11) +// CHECK-NEXT: Name: foo3 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -45,7 +45,7 @@ // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: foo4 (16) +// CHECK-NEXT: Name: foo4 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -54,7 +54,7 @@ // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: foo5 (21) +// CHECK-NEXT: Name: foo5 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -63,7 +63,7 @@ // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: foo6 (26) +// CHECK-NEXT: Name: foo6 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -72,7 +72,7 @@ // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: foo7 (31) +// CHECK-NEXT: Name: foo7 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -81,7 +81,7 @@ // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: foo8 (36) +// CHECK-NEXT: Name: foo8 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -90,7 +90,7 @@ // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: foo9 (41) +// CHECK-NEXT: Name: foo9 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -99,7 +99,7 @@ // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: fooA (46) +// CHECK-NEXT: Name: fooA // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -108,7 +108,7 @@ // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: fooB (51) +// CHECK-NEXT: Name: fooB // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -117,7 +117,7 @@ // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: fooC (56) +// CHECK-NEXT: Name: fooC // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -126,7 +126,7 @@ // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: fooD (61) +// CHECK-NEXT: Name: fooD // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -135,7 +135,7 @@ // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: fooE (66) +// CHECK-NEXT: Name: fooE // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global diff --git a/test/MC/ELF/tls.s b/test/MC/ELF/tls.s index 6d4b703..79865cd 100644 --- a/test/MC/ELF/tls.s +++ b/test/MC/ELF/tls.s @@ -13,7 +13,7 @@ foobar: .long 43 // CHECK: Symbol { -// CHECK: Name: foobar (31) +// CHECK: Name: foobar // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local @@ -23,7 +23,7 @@ foobar: // CHECK-NEXT: } // CHECK: Symbol { -// CHECK: Name: foo1 (1) +// CHECK: Name: foo1 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -32,7 +32,7 @@ foobar: // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: foo2 (6) +// CHECK-NEXT: Name: foo2 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -41,7 +41,7 @@ foobar: // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: foo3 (11) +// CHECK-NEXT: Name: foo3 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -50,7 +50,7 @@ foobar: // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: foo4 (16) +// CHECK-NEXT: Name: foo4 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -59,7 +59,7 @@ foobar: // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: foo5 (21) +// CHECK-NEXT: Name: foo5 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -68,7 +68,7 @@ foobar: // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: foo6 (26) +// CHECK-NEXT: Name: foo6 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global diff --git a/test/MC/ELF/type.s b/test/MC/ELF/type.s index 638d828..c82d300 100644 --- a/test/MC/ELF/type.s +++ b/test/MC/ELF/type.s @@ -176,7 +176,7 @@ alias12: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: sym1 (54) +// CHECK-NEXT: Name: sym1 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global (0x1) @@ -185,7 +185,7 @@ alias12: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: sym10 (162) +// CHECK-NEXT: Name: sym10 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global (0x1) @@ -194,7 +194,7 @@ alias12: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: sym11 (176) +// CHECK-NEXT: Name: sym11 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global (0x1) @@ -203,7 +203,7 @@ alias12: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: sym12 (190) +// CHECK-NEXT: Name: sym12 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global (0x1) @@ -212,7 +212,7 @@ alias12: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: sym2 (66) +// CHECK-NEXT: Name: sym2 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global (0x1) @@ -221,7 +221,7 @@ alias12: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: sym3 (78) +// CHECK-NEXT: Name: sym3 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global (0x1) @@ -230,7 +230,7 @@ alias12: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: sym4 (90) +// CHECK-NEXT: Name: sym4 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global (0x1) @@ -239,7 +239,7 @@ alias12: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: sym5 (102) +// CHECK-NEXT: Name: sym5 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global (0x1) @@ -248,7 +248,7 @@ alias12: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: sym6 (114) +// CHECK-NEXT: Name: sym6 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global (0x1) @@ -257,7 +257,7 @@ alias12: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: sym7 (126) +// CHECK-NEXT: Name: sym7 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global (0x1) @@ -266,7 +266,7 @@ alias12: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: sym8 (138) +// CHECK-NEXT: Name: sym8 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global (0x1) @@ -275,7 +275,7 @@ alias12: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: sym9 (150) +// CHECK-NEXT: Name: sym9 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global (0x1) diff --git a/test/MC/ELF/undef.s b/test/MC/ELF/undef.s index 7c2a876..245b563 100644 --- a/test/MC/ELF/undef.s +++ b/test/MC/ELF/undef.s @@ -19,21 +19,80 @@ .text movsd .Lsym8(%rip), %xmm1 -// CHECK: Symbols [ - -// CHECK: Symbol { -// CHECK: Name: .Lsym8 - -// CHECK: Symbol { -// CHECK: Name: .Lsym1 +test2_a = undef +test2_b = undef + 1 -// CHECK: Symbol { -// CHECK: Name: sym6 +// CHECK: Symbols [ +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: (0) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: Undefined +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: .Lsym8 +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .rodata.str1.1 +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: .text +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Section +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: .data +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Section +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .data +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: .bss +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Section +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .bss +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: .rodata.str1.1 +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Section +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .rodata.str1.1 +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: .Lsym1 +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: Undefined +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: sym6 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global // CHECK-NEXT: Type: Object // CHECK-NEXT: Other: 0 -// CHECK-NEXT: Section: Undefined (0x0) +// CHECK-NEXT: Section: Undefined // CHECK-NEXT: } // CHECK-NEXT: ] diff --git a/test/MC/ELF/weakref.s b/test/MC/ELF/weakref.s index cf2228d..2288264 100644 --- a/test/MC/ELF/weakref.s +++ b/test/MC/ELF/weakref.s @@ -80,7 +80,7 @@ bar15: // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar6 (21) +// CHECK-NEXT: Name: bar6 // CHECK-NEXT: Value: 0x18 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local @@ -89,7 +89,7 @@ bar15: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar7 (26) +// CHECK-NEXT: Name: bar7 // CHECK-NEXT: Value: 0x18 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local @@ -98,7 +98,7 @@ bar15: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar8 (31) +// CHECK-NEXT: Name: bar8 // CHECK-NEXT: Value: 0x1C // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local @@ -107,7 +107,7 @@ bar15: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar9 (36) +// CHECK-NEXT: Name: bar9 // CHECK-NEXT: Value: 0x20 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local @@ -116,7 +116,7 @@ bar15: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: .text (0) +// CHECK-NEXT: Name: .text // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local @@ -125,7 +125,7 @@ bar15: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: .data (0) +// CHECK-NEXT: Name: .data // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local @@ -134,7 +134,7 @@ bar15: // CHECK-NEXT: Section: .data (0x3) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: .bss (0) +// CHECK-NEXT: Name: .bss // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Local @@ -143,7 +143,7 @@ bar15: // CHECK-NEXT: Section: .bss (0x4) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar10 (41) +// CHECK-NEXT: Name: bar10 // CHECK-NEXT: Value: 0x28 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -152,7 +152,7 @@ bar15: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar11 (47) +// CHECK-NEXT: Name: bar11 // CHECK-NEXT: Value: 0x30 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -161,7 +161,7 @@ bar15: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar12 (53) +// CHECK-NEXT: Name: bar12 // CHECK-NEXT: Value: 0x30 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -170,7 +170,7 @@ bar15: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar13 (59) +// CHECK-NEXT: Name: bar13 // CHECK-NEXT: Value: 0x34 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -179,7 +179,7 @@ bar15: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar14 (65) +// CHECK-NEXT: Name: bar14 // CHECK-NEXT: Value: 0x38 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -188,7 +188,7 @@ bar15: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar15 (71) +// CHECK-NEXT: Name: bar15 // CHECK-NEXT: Value: 0x40 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -197,7 +197,7 @@ bar15: // CHECK-NEXT: Section: .text (0x1) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar2 (1) +// CHECK-NEXT: Name: bar2 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -206,7 +206,7 @@ bar15: // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar3 (6) +// CHECK-NEXT: Name: bar3 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Weak @@ -215,7 +215,7 @@ bar15: // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar4 (11) +// CHECK-NEXT: Name: bar4 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global @@ -224,7 +224,7 @@ bar15: // CHECK-NEXT: Section: Undefined (0x0) // CHECK-NEXT: } // CHECK-NEXT: Symbol { -// CHECK-NEXT: Name: bar5 (16) +// CHECK-NEXT: Name: bar5 // CHECK-NEXT: Value: 0x0 // CHECK-NEXT: Size: 0 // CHECK-NEXT: Binding: Global diff --git a/test/MC/MachO/ARM64/darwin-ARM64-local-label-diff.s b/test/MC/MachO/AArch64/darwin-ARM64-local-label-diff.s index d98c257..d98c257 100644 --- a/test/MC/MachO/ARM64/darwin-ARM64-local-label-diff.s +++ b/test/MC/MachO/AArch64/darwin-ARM64-local-label-diff.s diff --git a/test/MC/MachO/ARM64/darwin-ARM64-reloc.s b/test/MC/MachO/AArch64/darwin-ARM64-reloc.s index 7f586ae..7f586ae 100644 --- a/test/MC/MachO/ARM64/darwin-ARM64-reloc.s +++ b/test/MC/MachO/AArch64/darwin-ARM64-reloc.s diff --git a/test/MC/MachO/ARM64/lit.local.cfg b/test/MC/MachO/AArch64/lit.local.cfg index a75a42b..9a66a00 100644 --- a/test/MC/MachO/ARM64/lit.local.cfg +++ b/test/MC/MachO/AArch64/lit.local.cfg @@ -1,4 +1,4 @@ targets = set(config.root.targets_to_build.split()) -if not 'ARM64' in targets: +if not 'AArch64' in targets: config.unsupported = True diff --git a/test/MC/MachO/ARM/bad-darwin-directives.s b/test/MC/MachO/ARM/bad-darwin-directives.s index 0499e40..7ac0f6f 100644 --- a/test/MC/MachO/ARM/bad-darwin-directives.s +++ b/test/MC/MachO/ARM/bad-darwin-directives.s @@ -1,24 +1,29 @@ -@ RUN: not llvm-mc -n -triple armv7-apple-darwin10 %s -filetype=obj -o - 2> %t.err > %t -@ RUN: FileCheck --check-prefix=CHECK-ERROR < %t.err %s +@ RUN: not llvm-mc -n -triple armv7-apple-darwin10 %s -filetype asm -o /dev/null 2>&1 \ +@ RUN: | FileCheck --check-prefix CHECK-ERROR %s + +@ RUN: not llvm-mc -n -triple armv7-apple-darwin10 %s -filetype obj -o /dev/null 2>&1 \ +@ RUN: | FileCheck --check-prefix CHECK-ERROR %s + @ rdar://16335232 .eabi_attribute 8, 1 -@ CHECK-ERROR: error: .eabi_attribute directive not valid for Mach-O +@ CHECK-ERROR: error: unknown directive .cpu -@ CHECK-ERROR: error: .cpu directive not valid for Mach-O +@ CHECK-ERROR: error: unknown directive .fpu neon -@ CHECK-ERROR: error: .fpu directive not valid for Mach-O +@ CHECK-ERROR: error: unknown directive .arch armv7 -@ CHECK-ERROR: error: .arch directive not valid for Mach-O +@ CHECK-ERROR: error: unknown directive .fnstart -@ CHECK-ERROR: error: .fnstart directive not valid for Mach-O +@ CHECK-ERROR: error: unknown directive .tlsdescseq -@ CHECK-ERROR: error: .tlsdescseq directive not valid for Mach-O +@ CHECK-ERROR: error: unknown directive .object_arch armv7 -@ CHECK-ERROR: error: .object_arch directive not valid for Mach-O +@ CHECK-ERROR: error: unknown directive + diff --git a/test/MC/MachO/bad-darwin-x86_64-reloc-expr.s b/test/MC/MachO/bad-darwin-x86_64-reloc-expr.s new file mode 100644 index 0000000..2b4271f --- /dev/null +++ b/test/MC/MachO/bad-darwin-x86_64-reloc-expr.s @@ -0,0 +1,6 @@ +// RUN: not llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -o - 2> %t.err > %t +// RUN: FileCheck --check-prefix=CHECK-ERROR < %t.err %s + +.quad (0x1234 + (4 * SOME_VALUE)) +// CHECK-ERROR: error: expected relocatable expression +// CHECK-ERROR: ^ diff --git a/test/MC/MachO/debug_frame.s b/test/MC/MachO/debug_frame.s index 20bfd8d..247347d 100644 --- a/test/MC/MachO/debug_frame.s +++ b/test/MC/MachO/debug_frame.s @@ -3,6 +3,7 @@ // Make sure MC can handle file level .cfi_startproc and .cfi_endproc that creates // an empty frame. // rdar://10017184 +_proc: .cfi_startproc .cfi_endproc diff --git a/test/MC/MachO/temp-labels.s b/test/MC/MachO/temp-labels.s index b7382b7..ac0f620 100644 --- a/test/MC/MachO/temp-labels.s +++ b/test/MC/MachO/temp-labels.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -L -o - | macho-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -save-temp-labels -o - | macho-dump --dump-section-data | FileCheck %s // CHECK: # Load Command 1 // CHECK: (('command', 2) diff --git a/test/MC/Mips/cpload-bad.s b/test/MC/Mips/cpload-bad.s new file mode 100644 index 0000000..7d186f6 --- /dev/null +++ b/test/MC/Mips/cpload-bad.s @@ -0,0 +1,15 @@ +# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1 +# RUN: FileCheck %s < %t1 -check-prefix=ASM + + .text + .option pic2 + .set reorder + .cpload $25 +# ASM: :[[@LINE-1]]:9: warning: .cpload in reorder section + .set noreorder + .cpload $32 +# ASM: :[[@LINE-1]]:17: error: invalid register + .cpload $foo +# ASM: :[[@LINE-1]]:17: error: expected register containing function address + .cpload bar +# ASM: :[[@LINE-1]]:17: error: expected register containing function address diff --git a/test/MC/Mips/cpload.s b/test/MC/Mips/cpload.s new file mode 100644 index 0000000..bc5e797 --- /dev/null +++ b/test/MC/Mips/cpload.s @@ -0,0 +1,33 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -filetype=obj -o -| \ +# RUN: llvm-objdump -d -r -arch=mips - | \ +# RUN: FileCheck %s -check-prefix=OBJ + +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -filetype=obj -o -| \ +# RUN: llvm-objdump -d -r -arch=mips - | \ +# RUN: FileCheck %s -check-prefix=OBJ64 + +# ASM: .text +# ASM: .option pic2 +# ASM: .set noreorder +# ASM: .cpload $25 +# ASM: .set reorder + +# OBJ: .text +# OBJ: lui $gp, 0 +# OBJ: R_MIPS_HI16 _gp_disp +# OBJ: addiu $gp, $gp, 0 +# OBJ: R_MIPS_LO16 _gp_disp +# OBJ: addu $gp, $gp, $25 + +# OBJ64: .text +# OBJ64-NOT: lui $gp, 0 +# OBJ64-NOT: addiu $gp, $gp, 0 +# OBJ64-NOT: addu $gp, $gp, $25 + + .text + .option pic2 + .set noreorder + .cpload $25 + .set reorder diff --git a/test/MC/Mips/cpsetup.s b/test/MC/Mips/cpsetup.s index dbdcaab..a21a1e3 100644 --- a/test/MC/Mips/cpsetup.s +++ b/test/MC/Mips/cpsetup.s @@ -1,36 +1,78 @@ +# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+o32 -filetype=obj -o - %s | \ +# RUN: llvm-objdump -d -r -arch=mips64 - | \ +# RUN: FileCheck -check-prefix=O32 %s + # RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+o32 %s | \ -# RUN: FileCheck -check-prefix=ANY -check-prefix=O32 %s +# RUN: FileCheck -check-prefix=ASM %s + +# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+n32 -filetype=obj -o - %s | \ +# RUN: llvm-objdump -d -r -arch=mips64 - | \ +# RUN: FileCheck -check-prefix=NXX -check-prefix=N32 %s + # RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+n32 %s | \ -# RUN: FileCheck -check-prefix=ANY -check-prefix=NXX -check-prefix=N32 %s -# RUN: llvm-mc -triple mips64-unknown-unknown %s | \ -# RUN: FileCheck -check-prefix=ANY -check-prefix=NXX -check-prefix=N64 %s +# RUN: FileCheck -check-prefix=ASM %s -# TODO: !PIC -> no output +# RUN: llvm-mc -triple mips64-unknown-unknown %s -filetype=obj -o - | \ +# RUN: llvm-objdump -d -r -arch=mips64 - | \ +# RUN: FileCheck -check-prefix=NXX -check-prefix=N64 %s + +# RUN: llvm-mc -triple mips64-unknown-unknown %s | \ +# RUN: FileCheck -check-prefix=ASM %s .text .option pic2 t1: .cpsetup $25, 8, __cerror -# ANY-LABEL: t1: # O32-NOT: __cerror +# FIXME: Direct object emission for N32 is still under development. +# N32 doesn't allow 3 operations to be specified in the same relocation +# record like N64 does. + # NXX: sd $gp, 8($sp) -# NXX: lui $gp, %hi(%neg(%gp_rel(__cerror))) -# NXX: addiu $gp, $gp, %lo(%neg(%gp_rel(__cerror))) +# NXX: lui $gp, 0 +# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror +# NXX: addiu $gp, $gp, 0 +# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror # N32: addu $gp, $gp, $25 # N64: daddu $gp, $gp, $25 +# ASM: .cpsetup $25, 8, __cerror + t2: -# ANY-LABEL: t2: .cpsetup $25, $2, __cerror # O32-NOT: __cerror +# FIXME: Direct object emission for N32 is still under development. +# N32 doesn't allow 3 operations to be specified in the same relocation +# record like N64 does. + # NXX: move $2, $gp -# NXX: lui $gp, %hi(%neg(%gp_rel(__cerror))) -# NXX: addiu $gp, $gp, %lo(%neg(%gp_rel(__cerror))) +# NXX: lui $gp, 0 +# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror +# NXX: addiu $gp, $gp, 0 +# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror # N32: addu $gp, $gp, $25 # N64: daddu $gp, $gp, $25 + +# ASM: .cpsetup $25, $2, __cerror + +t3: + .option pic0 + nop + .cpsetup $25, 8, __cerror + nop + +# Testing that .cpsetup expands to nothing in this case +# by checking that the next instruction after the first +# nop is also a 'nop'. +# NXX: nop +# NXX-NEXT: nop + +# ASM: nop +# ASM: .cpsetup $25, 8, __cerror +# ASM: nop diff --git a/test/MC/Mips/elf-N64.s b/test/MC/Mips/elf-N64.s index 3c01803..bf6ebd7 100644 --- a/test/MC/Mips/elf-N64.s +++ b/test/MC/Mips/elf-N64.s @@ -1,4 +1,5 @@ // RUN: llvm-mc -filetype=obj -triple=mips64el-pc-linux -mcpu=mips64 %s -o - | llvm-readobj -r | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple=mips64-pc-linux -mcpu=mips64 %s -o - | llvm-readobj -r | FileCheck %s // Check for N64 relocation production. // Check that the appropriate relocations were created. diff --git a/test/MC/Mips/elf-gprel-32-64.s b/test/MC/Mips/elf-gprel-32-64.s index ae75197..2f5ac66 100644 --- a/test/MC/Mips/elf-gprel-32-64.s +++ b/test/MC/Mips/elf-gprel-32-64.s @@ -1,6 +1,9 @@ // RUN: llvm-mc -filetype=obj -triple=mips64el-pc-linux -mcpu=mips64 %s -o - \ // RUN: | llvm-readobj -r \ // RUN: | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple=mips64-pc-linux -mcpu=mips64 %s -o - \ +// RUN: | llvm-readobj -r \ +// RUN: | FileCheck %s // Check that the appropriate relocations were created. diff --git a/test/MC/Mips/elf_eflags.s b/test/MC/Mips/elf_eflags.s index c789428..8cf4960 100644 --- a/test/MC/Mips/elf_eflags.s +++ b/test/MC/Mips/elf_eflags.s @@ -4,40 +4,79 @@ # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2 %s # MIPSEL-MIPS64R2: Flags [ (0x80001100) +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2-NAN2008 %s +# MIPSEL-MIPS64R2-NAN2008: Flags [ (0x80001500) + # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64 %s # MIPSEL-MIPS64: Flags [ (0x60001100) +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64-NAN2008 %s +# MIPSEL-MIPS64-NAN2008: Flags [ (0x60001500) + # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2 %s # MIPSEL-MIPS32R2: Flags [ (0x70001000) +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2-NAN2008 %s +# MIPSEL-MIPS32R2-NAN2008: Flags [ (0x70001400) + # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32 %s # MIPSEL-MIPS32: Flags [ (0x50001000) +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32-NAN2008 %s +# MIPSEL-MIPS32-NAN2008: Flags [ (0x50001400) + # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32 %s # MIPS64EL-MIPS64R2-N32: Flags [ (0x80000020) +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,n32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32-NAN2008 %s +# MIPS64EL-MIPS64R2-N32-NAN2008: Flags [ (0x80000420) + # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=-n64,n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N32 %s # MIPS64EL-MIPS64-N32: Flags [ (0x60000020) +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=-n64,n32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N32-NAN2008 %s +# MIPS64EL-MIPS64-N32-NAN2008: Flags [ (0x60000420) + # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=n64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N64 %s # MIPS64EL-MIPS64R2-N64: Flags [ (0x80000000) +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=n64,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N64-NAN2008 %s +# MIPS64EL-MIPS64R2-N64-NAN2008: Flags [ (0x80000400) + # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=n64 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N64 %s # MIPS64EL-MIPS64-N64: Flags [ (0x60000000) +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=n64,+nan2008 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N64-NAN2008 %s +# MIPS64EL-MIPS64-N64-NAN2008: Flags [ (0x60000400) + # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,o32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-O32 %s # MIPS64EL-MIPS64R2-O32: Flags [ (0x80001100) +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,o32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-O32-NAN2008 %s +# MIPS64EL-MIPS64R2-O32-NAN2008: Flags [ (0x80001500) + # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips4 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS4 %s # MIPS4: Flags [ (0x30000000) + # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips4 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS4-NAN2008 %s +# MIPS4-NAN2008: Flags [ (0x30000400) + # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=-n64,o32 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-O32 %s # MIPS64EL-MIPS64-O32: Flags [ (0x60001100) - + +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=-n64,o32,+nan2008 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-O32-NAN2008 %s +# MIPS64EL-MIPS64-O32-NAN2008: Flags [ (0x60001500) + # Default ABI for MIPS64 is N64 as opposed to GCC/GAS (N32) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2 %s # MIPS64EL-MIPS64R2: Flags [ (0x80000000) +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-NAN2008 %s +# MIPS64EL-MIPS64R2-NAN2008: Flags [ (0x80000400) + # Default ABI for MIPS64 is N64 as opposed to GCC/GAS (N32) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64 %s # MIPS64EL-MIPS64: Flags [ (0x60000000) + +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-NAN2008 %s +# MIPS64EL-MIPS64-NAN2008: Flags [ (0x60000400) diff --git a/test/MC/Mips/elf_eflags_nan2008.s b/test/MC/Mips/elf_eflags_nan2008.s new file mode 100644 index 0000000..71a22be --- /dev/null +++ b/test/MC/Mips/elf_eflags_nan2008.s @@ -0,0 +1,12 @@ +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o - | \ +# RUN: llvm-readobj -h | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ +# RUN: llvm-mc -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM + +# This *MUST* match the output of gas compiled with the same triple. +# CHECK-OBJ: Flags [ (0x50001400) + +# CHECK-ASM: .nan 2008 + +.nan 2008 diff --git a/test/MC/Mips/elf_eflags_nanlegacy.s b/test/MC/Mips/elf_eflags_nanlegacy.s new file mode 100644 index 0000000..6897ad2 --- /dev/null +++ b/test/MC/Mips/elf_eflags_nanlegacy.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o - | \ +# RUN: llvm-readobj -h | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ +# RUN: llvm-mc -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM + +# This *MUST* match the output of gas compiled with the same triple. +# CHECK-OBJ: Flags [ (0x50001000) + +# CHECK-ASM: .nan 2008 +# CHECK-ASM: .nan legacy + +.nan 2008 +// Let's override the previous directive! +.nan legacy diff --git a/test/MC/Mips/llvm-mc-fixup-endianness.s b/test/MC/Mips/llvm-mc-fixup-endianness.s new file mode 100644 index 0000000..bc6a5d9 --- /dev/null +++ b/test/MC/Mips/llvm-mc-fixup-endianness.s @@ -0,0 +1,6 @@ +# RUN: llvm-mc -show-encoding -mcpu=mips32 -triple mips-unknown-unknown %s | FileCheck -check-prefix=BE %s +# RUN: llvm-mc -show-encoding -mcpu=mips32 -triple mipsel-unknown-unknown %s | FileCheck -check-prefix=LE %s +# + .text + b foo # BE: b foo # encoding: [0x10,0x00,A,A] + # LE: b foo # encoding: [A,A,0x00,0x10] diff --git a/test/MC/Mips/micromips-control-instructions.s b/test/MC/Mips/micromips-control-instructions.s index 8170a9c..aff84c2 100644 --- a/test/MC/Mips/micromips-control-instructions.s +++ b/test/MC/Mips/micromips-control-instructions.s @@ -1,6 +1,6 @@ -# RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips \ +# RUN: llvm-mc %s -triple=mipsel -show-encoding -mcpu=mips32r2 -mattr=micromips \ # RUN: | FileCheck -check-prefix=CHECK-EL %s -# RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips \ +# RUN: llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r2 -mattr=micromips \ # RUN: | FileCheck -check-prefix=CHECK-EB %s # Check that the assembler can handle the documented syntax # for control instructions. @@ -10,7 +10,7 @@ # Little endian #------------------------------------------------------------------------------ # CHECK-EL: break # encoding: [0x00,0x00,0x07,0x00] -# CHECK-EL: break 7, 0 # encoding: [0x07,0x00,0x07,0x00] +# CHECK-EL: break 7 # encoding: [0x07,0x00,0x07,0x00] # CHECK-EL: break 7, 5 # encoding: [0x07,0x00,0x47,0x01] # CHECK-EL: syscall # encoding: [0x00,0x00,0x7c,0x8b] # CHECK-EL: syscall 396 # encoding: [0x8c,0x01,0x7c,0x8b] @@ -28,7 +28,7 @@ # Big endian #------------------------------------------------------------------------------ # CHECK-EB: break # encoding: [0x00,0x00,0x00,0x07] -# CHECK-EB: break 7, 0 # encoding: [0x00,0x07,0x00,0x07] +# CHECK-EB: break 7 # encoding: [0x00,0x07,0x00,0x07] # CHECK-EB: break 7, 5 # encoding: [0x00,0x07,0x01,0x47] # CHECK-EB: syscall # encoding: [0x00,0x00,0x8b,0x7c] # CHECK-EB: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c] diff --git a/test/MC/Mips/micromips-el-fixup-data.s b/test/MC/Mips/micromips-el-fixup-data.s index 2293f63..4753835 100644 --- a/test/MC/Mips/micromips-el-fixup-data.s +++ b/test/MC/Mips/micromips-el-fixup-data.s @@ -2,7 +2,7 @@ # RUN: -mattr=+micromips 2>&1 -filetype=obj > %t.o # RUN: llvm-objdump %t.o -triple mipsel -mattr=+micromips -d | FileCheck %s -# Check that fixup data is writen in the microMIPS specific little endian +# Check that fixup data is written in the microMIPS specific little endian # byte order. .text diff --git a/test/MC/Mips/mips-control-instructions.s b/test/MC/Mips/mips-control-instructions.s index 4a16c53..47da8cc 100644 --- a/test/MC/Mips/mips-control-instructions.s +++ b/test/MC/Mips/mips-control-instructions.s @@ -4,7 +4,7 @@ # RUN: | FileCheck -check-prefix=CHECK64 %s # CHECK32: break # encoding: [0x00,0x00,0x00,0x0d] -# CHECK32: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d] +# CHECK32: break 7 # encoding: [0x00,0x07,0x00,0x0d] # CHECK32: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d] # CHECK32: syscall # encoding: [0x00,0x00,0x00,0x0c] # CHECK32: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c] @@ -37,7 +37,7 @@ # CHECK32: tnei $3, 1023 # encoding: [0x04,0x6e,0x03,0xff] # CHECK64: break # encoding: [0x00,0x00,0x00,0x0d] -# CHECK64: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d] +# CHECK64: break 7 # encoding: [0x00,0x07,0x00,0x0d] # CHECK64: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d] # CHECK64: syscall # encoding: [0x00,0x00,0x00,0x0c] # CHECK64: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c] diff --git a/test/MC/Mips/mips1/invalid-mips2-wrong-error.s b/test/MC/Mips/mips1/invalid-mips2-wrong-error.s new file mode 100644 index 0000000..8e878fe --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips2-wrong-error.s @@ -0,0 +1,16 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldc3 $29,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sc $t7,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc1 $f31,30574($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc3 $12,5835($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips1/invalid-mips2.s b/test/MC/Mips/mips1/invalid-mips2.s new file mode 100644 index 0000000..6c3e80a --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips2.s @@ -0,0 +1,23 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.s $f8,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlti $t6,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tnei $t4,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips1/invalid-mips3-wrong-error.s b/test/MC/Mips/mips1/invalid-mips3-wrong-error.s new file mode 100644 index 0000000..2016e70 --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips3-wrong-error.s @@ -0,0 +1,23 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sc $15,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips1/invalid-mips3.s b/test/MC/Mips/mips1/invalid-mips3.s new file mode 100644 index 0000000..d1b0eec --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips3.s @@ -0,0 +1,65 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsllv $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrlv $s3,$14,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.s $f8,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlti $14,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tnei $12,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips1/invalid-mips4-wrong-error.s b/test/MC/Mips/mips1/invalid-mips4-wrong-error.s new file mode 100644 index 0000000..2016e70 --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips4-wrong-error.s @@ -0,0 +1,23 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sc $15,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips1/invalid-mips4.s b/test/MC/Mips/mips1/invalid-mips4.s new file mode 100644 index 0000000..61aaf58 --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips4.s @@ -0,0 +1,82 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsllv $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrlv $s3,$14,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.s $f8,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f10,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f26,$f20,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlti $14,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tnei $12,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips1/invalid-mips5-wrong-error.s b/test/MC/Mips/mips1/invalid-mips5-wrong-error.s new file mode 100644 index 0000000..74473a3 --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips5-wrong-error.s @@ -0,0 +1,46 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips1/invalid-mips5.s b/test/MC/Mips/mips1/invalid-mips5.s new file mode 100644 index 0000000..1eddf02 --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips5.s @@ -0,0 +1,83 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsllv $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.s $f8,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ldxc1 $f8,$s7($t3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$a0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlti $t2,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tnei $t0,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$a2($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips1/valid-xfail.s b/test/MC/Mips/mips1/valid-xfail.s index 2ffeaa9..7696c9e 100644 --- a/test/MC/Mips/mips1/valid-xfail.s +++ b/test/MC/Mips/mips1/valid-xfail.s @@ -2,16 +2,10 @@ # they aren't implemented yet). # This test is set up to XPASS if any instruction generates an encoding. # -# FIXME: Test MIPS-I instead of MIPS32 -# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | not FileCheck %s # CHECK-NOT: encoding # XFAIL: * - .set noat - tlbp - tlbr - tlbwi - tlbwr - lwc0 c0_entrylo,-7321($s2) - lwc3 $10,-32265($k0) - swc0 c0_prid,18904($s3) + .set noat + lwc0 c0_entrylo,-7321($s2) + swc0 c0_prid,18904($s3) diff --git a/test/MC/Mips/mips1/valid.s b/test/MC/Mips/mips1/valid.s index 7fc866a..473e6b9 100644 --- a/test/MC/Mips/mips1/valid.s +++ b/test/MC/Mips/mips1/valid.s @@ -1,85 +1,102 @@ # Instructions that are valid # -# FIXME: Test MIPS-I instead of MIPS32 -# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s - .set noat - abs.d $f7,$f25 # CHECK: encoding: - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - cfc1 $s1,$21 - ctc1 $a2,$26 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.s.d $f26,$f8 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - lb $t8,-14515($t2) - lbu $t0,30195($v1) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - mfc1 $a3,$f27 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $s8,$a0 - move $t9,$a2 - mtc1 $s8,$f9 - mthi $s1 - mtlo $sp - mtlo $t9 - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - sb $s6,-19857($t6) - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - xor $s2,$a0,$s8 + .set noat + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + cfc1 $s1,$21 + ctc1 $a2,$26 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.s.d $f26,$f8 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + lb $24,-14515($10) + lbu $8,30195($v1) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwc3 $10,-32265($k0) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + mfc1 $a3,$f27 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $s8,$a0 + move $25,$a2 + mtc1 $s8,$f9 + mthi $s1 + mtlo $sp + mtlo $25 + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + sb $s6,-19857($14) + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swc3 $10,-32265($k0) + swl $15,13694($s3) + swr $s1,-26590($14) + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips2/invalid-mips3-wrong-error.s b/test/MC/Mips/mips2/invalid-mips3-wrong-error.s new file mode 100644 index 0000000..a3f829b --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips3-wrong-error.s @@ -0,0 +1,19 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + dmult $s7,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + dsub $a3,$s6,$a4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldl $t8,-4167($t8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldr $t2,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + scd $t3,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sd $t0,5835($a6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdr $a7,-20423($t0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips2/invalid-mips3.s b/test/MC/Mips/mips2/invalid-mips3.s new file mode 100644 index 0000000..ef498d7 --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips3.s @@ -0,0 +1,48 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsllv $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/invalid-mips32.s b/test/MC/Mips/mips2/invalid-mips32.s new file mode 100644 index 0000000..2975c68 --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips32.s @@ -0,0 +1,32 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + clo $11,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/invalid-mips32r2-xfail.s b/test/MC/Mips/mips2/invalid-mips32r2-xfail.s new file mode 100644 index 0000000..073f777 --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips32r2-xfail.s @@ -0,0 +1,11 @@ +# Instructions that are supposed to be invalid but currently aren't +# This test will XPASS if any insn stops assembling. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2> %t1 +# RUN: not FileCheck %s < %t1 +# XFAIL: * + +# CHECK-NOT: error + .set noat + rdhwr $sp,$11 diff --git a/test/MC/Mips/mips2/invalid-mips32r2.s b/test/MC/Mips/mips2/invalid-mips32r2.s new file mode 100644 index 0000000..37f2eed --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips32r2.s @@ -0,0 +1,59 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $t8,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$t0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msubu $t7,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$t2($t6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$t4($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/invalid-mips4-wrong-error.s b/test/MC/Mips/mips2/invalid-mips4-wrong-error.s new file mode 100644 index 0000000..193f6d7 --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips4-wrong-error.s @@ -0,0 +1,14 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips2/invalid-mips4.s b/test/MC/Mips/mips2/invalid-mips4.s new file mode 100644 index 0000000..e2eb672 --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips4.s @@ -0,0 +1,65 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsllv $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrlv $s3,$14,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/invalid-mips5-wrong-error.s b/test/MC/Mips/mips2/invalid-mips5-wrong-error.s new file mode 100644 index 0000000..0c58c6c --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips5-wrong-error.s @@ -0,0 +1,46 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips2/invalid-mips5.s b/test/MC/Mips/mips2/invalid-mips5.s new file mode 100644 index 0000000..f777ffe --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips5.s @@ -0,0 +1,66 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsllv $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ldxc1 $f8,$s7($t3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$a0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$a2($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/valid-xfail.s b/test/MC/Mips/mips2/valid-xfail.s deleted file mode 100644 index 2f82f5c..0000000 --- a/test/MC/Mips/mips2/valid-xfail.s +++ /dev/null @@ -1,17 +0,0 @@ -# Instructions that should be valid but currently fail for known reasons (e.g. -# they aren't implemented yet). -# This test is set up to XPASS if any instruction generates an encoding. -# -# FIXME: Test MIPS-II instead of MIPS32 -# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s -# CHECK-NOT: encoding -# XFAIL: * - - .set noat - ldc3 $29,-28645($s1) - lwc3 $10,-32265($k0) - sdc3 $12,5835($t2) - tlbp - tlbr - tlbwi - tlbwr diff --git a/test/MC/Mips/mips2/valid.s b/test/MC/Mips/mips2/valid.s index 1a05040..e3effde 100644 --- a/test/MC/Mips/mips2/valid.s +++ b/test/MC/Mips/mips2/valid.s @@ -1,107 +1,126 @@ # Instructions that are valid # -# FIXME: Test MIPS-II instead of MIPS32 -# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s - .set noat - abs.d $f7,$f25 # CHECK: encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - ctc1 $a2,$26 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.s.d $f26,$f8 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - mfc1 $a3,$f27 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $s8,$a0 - move $t9,$a2 - mtc1 $s8,$f9 - mthi $s1 - mtlo $sp - mtlo $t9 - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - xor $s2,$a0,$s8 + .set noat + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + ctc1 $a2,$26 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.s.d $f26,$f8 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + ldc3 $29,-28645($s1) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwc3 $10,-32265($k0) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + mfc1 $a3,$f27 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $s8,$a0 + move $25,$a2 + mtc1 $s8,$f9 + mthi $s1 + mtlo $sp + mtlo $25 + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sdc3 $12,5835($10) + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swc3 $10,-32265($k0) + swl $15,13694($s3) + swr $s1,-26590($14) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips3/invalid-mips4.s b/test/MC/Mips/mips3/invalid-mips4.s new file mode 100644 index 0000000..6e15d79 --- /dev/null +++ b/test/MC/Mips/mips3/invalid-mips4.s @@ -0,0 +1,23 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips3/invalid-mips5-wrong-error.s b/test/MC/Mips/mips3/invalid-mips5-wrong-error.s new file mode 100644 index 0000000..2c0246a --- /dev/null +++ b/test/MC/Mips/mips3/invalid-mips5-wrong-error.s @@ -0,0 +1,46 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips3/invalid-mips5.s b/test/MC/Mips/mips3/invalid-mips5.s new file mode 100644 index 0000000..d25621b --- /dev/null +++ b/test/MC/Mips/mips3/invalid-mips5.s @@ -0,0 +1,25 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ldxc1 $f8,$s7($t3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$a4,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$a6($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips3/valid-xfail.s b/test/MC/Mips/mips3/valid-xfail.s deleted file mode 100644 index 740663e..0000000 --- a/test/MC/Mips/mips3/valid-xfail.s +++ /dev/null @@ -1,15 +0,0 @@ -# Instructions that should be valid but currently fail for known reasons (e.g. -# they aren't implemented yet). -# This test is set up to XPASS if any instruction generates an encoding. -# -# FIXME: Test MIPS-III instead of MIPS64 -# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64 | not FileCheck %s -# CHECK-NOT: encoding -# XFAIL: * - - .set noat - lwc3 $10,-32265($k0) - tlbp - tlbr - tlbwi - tlbwr diff --git a/test/MC/Mips/mips3/valid.s b/test/MC/Mips/mips3/valid.s index dc9b48c..2067666 100644 --- a/test/MC/Mips/mips3/valid.s +++ b/test/MC/Mips/mips3/valid.s @@ -1,145 +1,176 @@ # Instructions that are valid # -# FIXME: Test MIPS-III instead of MIPS64 -# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s +# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 | FileCheck %s - .set noat - abs.d $f7,$f25 # CHECK:encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.l.d $f1,$f3 - ceil.l.s $f18,$f13 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - ctc1 $a2,$26 - cvt.d.l $f4,$f16 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.l.d $f24,$f15 - cvt.l.s $f11,$f29 - cvt.s.d $f26,$f8 - cvt.s.l $f15,$f30 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - dadd $s3,$at,$ra - daddi $sp,$s4,-27705 - daddiu $k0,$s6,-4586 - ddiv $zero,$k0,$s3 - ddivu $zero,$s0,$s1 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - dmfc1 $t4,$f13 - dmtc1 $s0,$f14 - dmult $s7,$t1 - dmultu $a1,$a2 - dsllv $zero,$s4,$t4 - dsrav $gp,$s2,$s3 - dsrlv $s3,$t6,$s4 - dsub $a3,$s6,$t0 - dsubu $a1,$a1,$k0 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - eret - floor.l.d $f26,$f7 - floor.l.s $f12,$f5 - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ld $sp,-28645($s1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - ldl $t8,-4167($t8) - ldr $t6,-30358($s4) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - lld $zero,-14736($ra) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - lwu $s3,-24086($v1) - mfc1 $a3,$f27 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $a0,$a3 - move $s5,$a0 - move $s8,$a0 - move $t9,$a2 - mtc1 $s8,$f9 - mthi $s1 - mtlo $sp - mtlo $t9 - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - round.l.d $f12,$f1 - round.l.s $f25,$f5 - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - scd $t7,-8243($sp) - sd $t4,5835($t2) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sdl $a3,-20961($s8) - sdr $t3,-20423($t4) - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.l.d $f23,$f23 - trunc.l.s $f28,$f31 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - xor $s2,$a0,$s8 + .set noat + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + ctc1 $a2,$26 + cvt.d.l $f4,$f16 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.l $f15,$f30 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + dadd $s3,$at,$ra + daddi $sp,$s4,-27705 + daddiu $k0,$s6,-4586 + daddu $s3,$at,$ra + ddiv $zero,$k0,$s3 + ddivu $zero,$s0,$s1 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + dmfc1 $12,$f13 + dmtc1 $s0,$f14 + dmult $s7,$9 + dmultu $a1,$a2 + dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8] + dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8] + dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbb] + dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbb] + dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] + dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf] + dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] + dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] + dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] + dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] + dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + eret + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ld $sp,-28645($s1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + ldl $24,-4167($24) + ldr $14,-30358($s4) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + lld $zero,-14736($ra) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwu $s3,-24086($v1) + mfc1 $a3,$f27 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $a0,$a3 + move $s5,$a0 + move $s8,$a0 + move $25,$a2 + mtc1 $s8,$f9 + mthi $s1 + mtlo $sp + mtlo $25 + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + round.l.d $f12,$f1 + round.l.s $f25,$f5 + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + scd $15,-8243($sp) + sd $12,5835($10) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sdl $a3,-20961($s8) + sdr $11,-20423($12) + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swl $15,13694($s3) + swr $s1,-26590($14) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips32/invalid-mips32r2-xfail.s b/test/MC/Mips/mips32/invalid-mips32r2-xfail.s index 73fba94..604ddbf 100644 --- a/test/MC/Mips/mips32/invalid-mips32r2-xfail.s +++ b/test/MC/Mips/mips32/invalid-mips32r2-xfail.s @@ -8,12 +8,4 @@ # CHECK-NOT: error .set noat - cvt.l.d $f24,$f15 - cvt.l.s $f11,$f29 - di $s8 - ei $t6 - luxc1 $f19,$s6($s5) - mfhc1 $s8,$f24 - mthc1 $zero,$f16 rdhwr $sp,$11 - suxc1 $f12,$k1($t5) diff --git a/test/MC/Mips/mips32/invalid-mips32r2.s b/test/MC/Mips/mips32/invalid-mips32r2.s index 881f7f1..fa6fe32 100644 --- a/test/MC/Mips/mips32/invalid-mips32r2.s +++ b/test/MC/Mips/mips32/invalid-mips32r2.s @@ -4,20 +4,31 @@ # RUN: 2>%t1 # RUN: FileCheck %s < %t1 - .set noat + .set noat + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdxc1 $f11,$t2($t6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swxc1 $f19,$t4($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32/invalid-mips64.s b/test/MC/Mips/mips32/invalid-mips64.s new file mode 100644 index 0000000..41040ed --- /dev/null +++ b/test/MC/Mips/mips32/invalid-mips64.s @@ -0,0 +1,9 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips32 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32/valid-xfail.s b/test/MC/Mips/mips32/valid-xfail.s index 65cebd3..d680740 100644 --- a/test/MC/Mips/mips32/valid-xfail.s +++ b/test/MC/Mips/mips32/valid-xfail.s @@ -2,43 +2,37 @@ # they aren't implemented yet). # This test is set up to XPASS if any instruction generates an encoding. # -# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s # CHECK-NOT: encoding # XFAIL: * - .set noat - c.eq.d $fcc1,$f15,$f15 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.s $fcc3,$f11,$f8 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.s $fcc7,$f1,$f25 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.s $fcc1,$f30,$f4 - ldc3 $29,-28645($s1) - rorv $t5,$a3,$s5 - sdc3 $12,5835($t2) - tlbp - tlbr - tlbwi - tlbwr + .set noat + c.eq.d $fcc1,$f15,$f15 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.s $fcc3,$f11,$f8 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.s $fcc7,$f1,$f25 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.s $fcc1,$f30,$f4 + rorv $13,$a3,$s5 diff --git a/test/MC/Mips/mips32/valid.s b/test/MC/Mips/mips32/valid.s index 9e83c0f..bc29bdc 100644 --- a/test/MC/Mips/mips32/valid.s +++ b/test/MC/Mips/mips32/valid.s @@ -1,131 +1,147 @@ # Instructions that are valid # -# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s .set noat - abs.d $f7,$f25 # CHECK: encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - clo $t3,$a1 - clz $sp,$gp - ctc1 $a2,$26 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.s.d $f26,$f8 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - deret - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - eret - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - madd $s6,$t5 - madd $zero,$t1 - maddu $s3,$gp - maddu $t8,$s2 - mfc0 $a2,$14,1 - mfc1 $a3,$f27 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $s8,$a0 - move $t9,$a2 - movf $gp,$t0,$fcc7 - movf.d $f6,$f11,$fcc5 - movf.s $f23,$f5,$fcc6 - movn $v1,$s1,$s0 - movn.d $f27,$f21,$k0 - movn.s $f12,$f0,$s7 - movt $zero,$s4,$fcc5 - movt.d $f0,$f2,$fcc0 - movt.s $f30,$f2,$fcc1 - movz $a1,$s6,$t1 - movz.d $f12,$f29,$t1 - movz.s $f25,$f7,$v1 - msub $s7,$k1 - msubu $t7,$a1 - mtc0 $t1,$29,3 - mtc1 $s8,$f9 - mthi $s1 - mtlo $sp - mtlo $t9 - mul $s0,$s4,$at - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - xor $s2,$a0,$s8 + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + clo $11,$a1 + clz $sp,$gp + ctc1 $a2,$26 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.s.d $f26,$f8 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + deret + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + eret + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + madd $s6,$13 + madd $zero,$9 + maddu $s3,$gp + maddu $24,$s2 + mfc0 $a2,$14,1 + mfc1 $a3,$f27 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + msub $s7,$k1 + msubu $15,$a1 + mtc0 $9,$29,3 + mtc1 $s8,$f9 + mthi $s1 + mtlo $sp + mtlo $25 + mul $s0,$s4,$at + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swl $15,13694($s3) + swr $s1,-26590($14) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips32r2/invalid-mips64r2.s b/test/MC/Mips/mips32r2/invalid-mips64r2.s new file mode 100644 index 0000000..293e58e --- /dev/null +++ b/test/MC/Mips/mips32r2/invalid-mips64r2.s @@ -0,0 +1,10 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding \ +# RUN: -mcpu=mips32r2 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + diff --git a/test/MC/Mips/mips32r2/valid-xfail.s b/test/MC/Mips/mips32r2/valid-xfail.s index 623c7f6..ef02d51 100644 --- a/test/MC/Mips/mips32r2/valid-xfail.s +++ b/test/MC/Mips/mips32r2/valid-xfail.s @@ -6,310 +6,304 @@ # CHECK-NOT: encoding # XFAIL: * - .set noat - abs.ps $f22,$f8 - absq_s.ph $t0,$a0 - absq_s.qb $t7,$s1 - absq_s.w $s3,$ra - add.ps $f25,$f27,$f13 - addq.ph $s1,$t7,$at - addq_s.ph $s3,$s6,$s2 - addq_s.w $a2,$t0,$at - addqh.ph $s4,$t6,$s1 - addqh.w $s7,$s7,$k1 - addqh_r.ph $sp,$t9,$s8 - addqh_r.w $t0,$v1,$zero - addsc $s8,$t7,$t4 - addu.ph $a2,$t6,$s3 - addu.qb $s6,$v1,$v1 - addu_s.ph $a3,$s3,$gp - addu_s.qb $s4,$s8,$s1 - adduh.qb $a1,$a1,$at - adduh_r.qb $a0,$t1,$t4 - addwc $k0,$s6,$s7 - alnv.ps $f12,$f18,$f30,$t4 - and.v $w10,$w25,$w29 - bitrev $t6,$at - bmnz.v $w15,$w2,$w28 - bmz.v $w13,$w11,$w21 - bsel.v $w28,$w7,$w0 - c.eq.d $fcc1,$f15,$f15 - c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 - c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 - c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 - ceil.l.d $f1,$f3 - ceil.l.s $f18,$f13 - cfcmsa $s6,$19 - cmp.eq.ph $s7,$t6 - cmp.le.ph $t0,$t6 - cmp.lt.ph $k0,$sp - cmpgdu.eq.qb $s3,$zero,$k0 - cmpgdu.le.qb $v1,$t7,$s2 - cmpgdu.lt.qb $s0,$gp,$sp - cmpgu.eq.qb $t6,$s6,$s8 - cmpgu.le.qb $t1,$a3,$s4 - cmpgu.lt.qb $sp,$at,$t0 - cmpu.eq.qb $v0,$t8 - cmpu.le.qb $s1,$a1 - cmpu.lt.qb $at,$a3 - ctcmsa $31,$s7 - cvt.d.l $f4,$f16 - cvt.ps.s $f3,$f18,$f19 - cvt.s.l $f15,$f30 - cvt.s.pl $f30,$f1 - cvt.s.pu $f14,$f25 - dmt $k0 - dpa.w.ph $ac1,$s7,$k0 - dpaq_s.w.ph $ac2,$a0,$t5 - dpaq_sa.l.w $ac0,$a2,$t6 - dpaqx_s.w.ph $ac3,$a0,$t8 - dpaqx_sa.w.ph $ac1,$zero,$s5 - dpau.h.qbl $ac1,$t2,$t8 - dpau.h.qbr $ac1,$s7,$s6 - dpax.w.ph $ac3,$a0,$k0 - dps.w.ph $ac1,$a3,$a1 - dpsq_s.w.ph $ac0,$gp,$k0 - dpsq_sa.l.w $ac0,$a3,$t7 - dpsqx_s.w.ph $ac3,$t5,$a3 - dpsqx_sa.w.ph $ac3,$sp,$s2 - dpsu.h.qbl $ac2,$t6,$t2 - dpsu.h.qbr $ac2,$a1,$s6 - dpsx.w.ph $ac0,$s7,$gp - dvpe $s6 - emt $t0 - evpe $v0 - extpdpv $s6,$ac0,$s8 - extpv $t5,$ac0,$t6 - extrv.w $t0,$ac3,$at - extrv_r.w $t0,$ac1,$s6 - extrv_rs.w $gp,$ac1,$s6 - extrv_s.h $s2,$ac1,$t6 - fclass.d $w14,$w27 - fclass.w $w19,$w28 - fexupl.d $w10,$w29 - fexupl.w $w12,$w27 - fexupr.d $w31,$w15 - fexupr.w $w29,$w12 - ffint_s.d $w1,$w30 - ffint_s.w $w16,$w14 - ffint_u.d $w23,$w18 - ffint_u.w $w19,$w12 - ffql.d $w2,$w3 - ffql.w $w9,$w0 - ffqr.d $w25,$w24 - ffqr.w $w10,$w6 - fill.b $w9,$v1 - fill.h $w9,$t0 - fill.w $w31,$t7 - flog2.d $w12,$w16 - flog2.w $w19,$w23 - floor.l.d $f26,$f7 - floor.l.s $f12,$f5 - fork $s2,$t0,$a0 - frcp.d $w12,$w4 - frcp.w $w30,$w8 - frint.d $w20,$w8 - frint.w $w11,$w29 - frsqrt.d $w29,$w2 - frsqrt.w $w9,$w8 - fsqrt.d $w3,$w1 - fsqrt.w $w5,$w15 - ftint_s.d $w31,$w26 - ftint_s.w $w27,$w14 - ftint_u.d $w5,$w31 - ftint_u.w $w12,$w29 - ftrunc_s.d $w4,$w22 - ftrunc_s.w $w24,$w7 - ftrunc_u.d $w20,$w25 - ftrunc_u.w $w7,$w26 - insv $s2,$at - iret - lbe $t6,122($t1) - lbue $t3,-108($t2) - lbux $t1,$t6($v0) - ldc3 $29,-28645($s1) - lhe $s6,219($v1) - lhue $gp,118($t3) - lhx $sp,$k0($t7) - lle $gp,-237($ra) - lwe $ra,-145($t6) - lwle $t3,-42($t3) - lwre $sp,-152($t8) - lwx $t4,$t4($s4) - madd.ps $f22,$f3,$f14,$f3 - maq_s.w.phl $ac2,$t9,$t3 - maq_s.w.phr $ac0,$t2,$t9 - maq_sa.w.phl $ac3,$a1,$v1 - maq_sa.w.phr $ac1,$at,$t2 - mfgc0 $s6,c0_datahi1 - mflo $t1,$ac2 - modsub $a3,$t4,$a3 - mov.ps $f22,$f17 - move.v $w8,$w17 - movf.ps $f10,$f28,$fcc6 - movn.ps $f31,$f31,$s3 - movt.ps $f20,$f25,$fcc2 - movz.ps $f18,$f17,$ra - msub $ac2,$sp,$t6 - msub.ps $f12,$f14,$f29,$f17 - msubu $ac2,$a1,$t8 - mtc0 $t1,c0_datahi1 - mtgc0 $s4,$21,7 - mthi $v0,$ac1 - mthlip $a3,$ac0 - mul.ph $s4,$t8,$s0 - mul.ps $f14,$f0,$f16 - mul_s.ph $t2,$t6,$t7 - muleq_s.w.phl $t3,$s4,$s4 - muleq_s.w.phr $s6,$a0,$s8 - muleu_s.ph.qbl $a2,$t6,$t0 - muleu_s.ph.qbr $a1,$ra,$t1 - mulq_rs.ph $s2,$t6,$t7 - mulq_rs.w $at,$s4,$t9 - mulq_s.ph $s0,$k1,$t7 - mulq_s.w $t1,$a3,$s0 - mulsa.w.ph $ac1,$s4,$s6 - mulsaq_s.w.ph $ac0,$ra,$s2 - neg.ps $f19,$f13 - nloc.b $w12,$w30 - nloc.d $w16,$w7 - nloc.h $w21,$w17 - nloc.w $w17,$w16 - nlzc.b $w12,$w7 - nlzc.d $w14,$w14 - nlzc.h $w24,$w24 - nlzc.w $w10,$w4 - nmadd.ps $f27,$f4,$f9,$f25 - nmsub.ps $f6,$f12,$f14,$f17 - nor.v $w20,$w20,$w15 - or.v $w13,$w23,$w12 - packrl.ph $ra,$t8,$t6 - pcnt.b $w30,$w15 - pcnt.d $w5,$w16 - pcnt.h $w20,$w24 - pcnt.w $w22,$w20 - pick.ph $ra,$a2,$gp - pick.qb $t3,$a0,$gp - pll.ps $f25,$f9,$f30 - plu.ps $f1,$f26,$f29 - preceq.w.phl $s8,$gp - preceq.w.phr $s5,$t7 - precequ.ph.qbl $s7,$ra - precequ.ph.qbla $a0,$t1 - precequ.ph.qbr $ra,$s3 - precequ.ph.qbra $t8,$t0 - preceu.ph.qbl $sp,$t0 - preceu.ph.qbla $s6,$t3 - preceu.ph.qbr $gp,$s1 - preceu.ph.qbra $k1,$s0 - precr.qb.ph $v0,$t4,$s8 - precrq.ph.w $t6,$s8,$t8 - precrq.qb.ph $a2,$t4,$t4 - precrq_rs.ph.w $a1,$k0,$a3 - precrqu_s.qb.ph $zero,$gp,$s5 - pul.ps $f9,$f30,$f26 - puu.ps $f24,$f9,$f2 - raddu.w.qb $t9,$s3 - rdpgpr $s3,$t1 - recip.d $f19,$f6 - recip.s $f3,$f30 - repl.ph $at,-307 - replv.ph $v1,$s7 - replv.qb $t9,$t4 - rorv $t5,$a3,$s5 - round.l.d $f12,$f1 - round.l.s $f25,$f5 - rsqrt.d $f3,$f28 - rsqrt.s $f4,$f8 - sbe $s7,33($s1) - sce $sp,189($t2) - sdc3 $12,5835($t2) - she $t8,105($v0) - shilo $ac1,26 - shilov $ac2,$t2 - shllv.ph $t2,$s0,$s0 - shllv.qb $gp,$v1,$zero - shllv_s.ph $k1,$at,$t5 - shllv_s.w $s1,$ra,$k0 - shrav.ph $t9,$s2,$s1 - shrav.qb $zero,$t8,$t3 - shrav_r.ph $s3,$t3,$t9 - shrav_r.qb $a0,$sp,$s5 - shrav_r.w $s7,$s4,$s6 - shrlv.ph $t6,$t2,$t1 - shrlv.qb $a2,$s2,$t3 - sub.ps $f5,$f14,$f26 - subq.ph $ra,$t1,$s8 - subq_s.ph $t5,$s8,$s5 - subq_s.w $k1,$a2,$a3 - subqh.ph $t2,$at,$t1 - subqh.w $v0,$a2,$zero - subqh_r.ph $a0,$t4,$s6 - subqh_r.w $t2,$a2,$gp - subu.ph $t1,$s6,$s4 - subu.qb $s6,$a2,$s6 - subu_s.ph $v1,$a1,$s3 - subu_s.qb $s1,$at,$ra - subuh.qb $zero,$gp,$gp - subuh_r.qb $s4,$s8,$s6 - swe $t8,94($k0) - swle $v1,-209($gp) - swre $k0,-202($s2) - synci 20023($s0) - tlbginv - tlbginvf - tlbgp - tlbgr - tlbgwi - tlbgwr - tlbinv - tlbinvf - tlbp - tlbr - tlbwi - tlbwr - trunc.l.d $f23,$f23 - trunc.l.s $f28,$f31 - wrpgpr $zero,$t5 - xor.v $w20,$w21,$w30 - yield $v1,$s0 + .set noat + abs.ps $f22,$f8 + absq_s.ph $8,$a0 + absq_s.qb $15,$s1 + absq_s.w $s3,$ra + add.ps $f25,$f27,$f13 + addq.ph $s1,$15,$at + addq_s.ph $s3,$s6,$s2 + addq_s.w $a2,$8,$at + addqh.ph $s4,$14,$s1 + addqh.w $s7,$s7,$k1 + addqh_r.ph $sp,$25,$s8 + addqh_r.w $8,$v1,$zero + addsc $s8,$15,$12 + addu.ph $a2,$14,$s3 + addu.qb $s6,$v1,$v1 + addu_s.ph $a3,$s3,$gp + addu_s.qb $s4,$s8,$s1 + adduh.qb $a1,$a1,$at + adduh_r.qb $a0,$9,$12 + addwc $k0,$s6,$s7 + alnv.ps $f12,$f18,$f30,$12 + and.v $w10,$w25,$w29 + bitrev $14,$at + bmnz.v $w15,$w2,$w28 + bmz.v $w13,$w11,$w21 + bsel.v $w28,$w7,$w0 + c.eq.d $fcc1,$f15,$f15 + c.eq.ps $fcc5,$f0,$f9 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.ps $fcc6,$f11,$f11 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.ps $fcc1,$f7,$f20 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.ps $f19,$f5 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.ps $f1,$f26 + c.nge.s $fcc3,$f11,$f8 + c.ngl.ps $f21,$f30 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.ps $fcc7,$f12,$f20 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.ps $fcc5,$f30,$f6 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.ps $fcc7,$f21,$f8 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.ps $fcc3,$f7,$f16 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.ps $fcc6,$f31,$f14 + c.seq.s $fcc7,$f1,$f25 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.ps $fcc1,$f5,$f29 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.ps $fcc6,$f17,$f3 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.ps $fcc7,$f14,$f0 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.ps $fcc4,$f2,$f26 + c.un.s $fcc1,$f30,$f4 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + cfcmsa $s6,$19 + cmp.eq.ph $s7,$14 + cmp.le.ph $8,$14 + cmp.lt.ph $k0,$sp + cmpgdu.eq.qb $s3,$zero,$k0 + cmpgdu.le.qb $v1,$15,$s2 + cmpgdu.lt.qb $s0,$gp,$sp + cmpgu.eq.qb $14,$s6,$s8 + cmpgu.le.qb $9,$a3,$s4 + cmpgu.lt.qb $sp,$at,$8 + cmpu.eq.qb $v0,$24 + cmpu.le.qb $s1,$a1 + cmpu.lt.qb $at,$a3 + ctcmsa $31,$s7 + cvt.d.l $f4,$f16 + cvt.ps.s $f3,$f18,$f19 + cvt.s.l $f15,$f30 + cvt.s.pl $f30,$f1 + cvt.s.pu $f14,$f25 + dmt $k0 + dpa.w.ph $ac1,$s7,$k0 + dpaq_s.w.ph $ac2,$a0,$13 + dpaq_sa.l.w $ac0,$a2,$14 + dpaqx_s.w.ph $ac3,$a0,$24 + dpaqx_sa.w.ph $ac1,$zero,$s5 + dpau.h.qbl $ac1,$10,$24 + dpau.h.qbr $ac1,$s7,$s6 + dpax.w.ph $ac3,$a0,$k0 + dps.w.ph $ac1,$a3,$a1 + dpsq_s.w.ph $ac0,$gp,$k0 + dpsq_sa.l.w $ac0,$a3,$15 + dpsqx_s.w.ph $ac3,$13,$a3 + dpsqx_sa.w.ph $ac3,$sp,$s2 + dpsu.h.qbl $ac2,$14,$10 + dpsu.h.qbr $ac2,$a1,$s6 + dpsx.w.ph $ac0,$s7,$gp + dvpe $s6 + emt $8 + evpe $v0 + extpdpv $s6,$ac0,$s8 + extpv $13,$ac0,$14 + extrv.w $8,$ac3,$at + extrv_r.w $8,$ac1,$s6 + extrv_rs.w $gp,$ac1,$s6 + extrv_s.h $s2,$ac1,$14 + fclass.d $w14,$w27 + fclass.w $w19,$w28 + fexupl.d $w10,$w29 + fexupl.w $w12,$w27 + fexupr.d $w31,$w15 + fexupr.w $w29,$w12 + ffint_s.d $w1,$w30 + ffint_s.w $w16,$w14 + ffint_u.d $w23,$w18 + ffint_u.w $w19,$w12 + ffql.d $w2,$w3 + ffql.w $w9,$w0 + ffqr.d $w25,$w24 + ffqr.w $w10,$w6 + fill.b $w9,$v1 + fill.h $w9,$8 + fill.w $w31,$15 + flog2.d $w12,$w16 + flog2.w $w19,$w23 + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + fork $s2,$8,$a0 + frcp.d $w12,$w4 + frcp.w $w30,$w8 + frint.d $w20,$w8 + frint.w $w11,$w29 + frsqrt.d $w29,$w2 + frsqrt.w $w9,$w8 + fsqrt.d $w3,$w1 + fsqrt.w $w5,$w15 + ftint_s.d $w31,$w26 + ftint_s.w $w27,$w14 + ftint_u.d $w5,$w31 + ftint_u.w $w12,$w29 + ftrunc_s.d $w4,$w22 + ftrunc_s.w $w24,$w7 + ftrunc_u.d $w20,$w25 + ftrunc_u.w $w7,$w26 + insv $s2,$at + iret + lbe $14,122($9) + lbue $11,-108($10) + lbux $9,$14($v0) + lhe $s6,219($v1) + lhue $gp,118($11) + lhx $sp,$k0($15) + lle $gp,-237($ra) + lwe $ra,-145($14) + lwle $11,-42($11) + lwre $sp,-152($24) + lwx $12,$12($s4) + madd.ps $f22,$f3,$f14,$f3 + maq_s.w.phl $ac2,$25,$11 + maq_s.w.phr $ac0,$10,$25 + maq_sa.w.phl $ac3,$a1,$v1 + maq_sa.w.phr $ac1,$at,$10 + mfgc0 $s6,c0_datahi1 + mflo $9,$ac2 + modsub $a3,$12,$a3 + mov.ps $f22,$f17 + move.v $w8,$w17 + movf.ps $f10,$f28,$fcc6 + movn.ps $f31,$f31,$s3 + movt.ps $f20,$f25,$fcc2 + movz.ps $f18,$f17,$ra + msub $ac2,$sp,$14 + msub.ps $f12,$f14,$f29,$f17 + msubu $ac2,$a1,$24 + mtc0 $9,c0_datahi1 + mtgc0 $s4,$21,7 + mthi $v0,$ac1 + mthlip $a3,$ac0 + mul.ph $s4,$24,$s0 + mul.ps $f14,$f0,$f16 + mul_s.ph $10,$14,$15 + muleq_s.w.phl $11,$s4,$s4 + muleq_s.w.phr $s6,$a0,$s8 + muleu_s.ph.qbl $a2,$14,$8 + muleu_s.ph.qbr $a1,$ra,$9 + mulq_rs.ph $s2,$14,$15 + mulq_rs.w $at,$s4,$25 + mulq_s.ph $s0,$k1,$15 + mulq_s.w $9,$a3,$s0 + mulsa.w.ph $ac1,$s4,$s6 + mulsaq_s.w.ph $ac0,$ra,$s2 + neg.ps $f19,$f13 + nloc.b $w12,$w30 + nloc.d $w16,$w7 + nloc.h $w21,$w17 + nloc.w $w17,$w16 + nlzc.b $w12,$w7 + nlzc.d $w14,$w14 + nlzc.h $w24,$w24 + nlzc.w $w10,$w4 + nmadd.ps $f27,$f4,$f9,$f25 + nmsub.ps $f6,$f12,$f14,$f17 + nor.v $w20,$w20,$w15 + or.v $w13,$w23,$w12 + packrl.ph $ra,$24,$14 + pcnt.b $w30,$w15 + pcnt.d $w5,$w16 + pcnt.h $w20,$w24 + pcnt.w $w22,$w20 + pick.ph $ra,$a2,$gp + pick.qb $11,$a0,$gp + pll.ps $f25,$f9,$f30 + plu.ps $f1,$f26,$f29 + preceq.w.phl $s8,$gp + preceq.w.phr $s5,$15 + precequ.ph.qbl $s7,$ra + precequ.ph.qbla $a0,$9 + precequ.ph.qbr $ra,$s3 + precequ.ph.qbra $24,$8 + preceu.ph.qbl $sp,$8 + preceu.ph.qbla $s6,$11 + preceu.ph.qbr $gp,$s1 + preceu.ph.qbra $k1,$s0 + precr.qb.ph $v0,$12,$s8 + precrq.ph.w $14,$s8,$24 + precrq.qb.ph $a2,$12,$12 + precrq_rs.ph.w $a1,$k0,$a3 + precrqu_s.qb.ph $zero,$gp,$s5 + pul.ps $f9,$f30,$f26 + puu.ps $f24,$f9,$f2 + raddu.w.qb $25,$s3 + rdpgpr $s3,$9 + recip.d $f19,$f6 + recip.s $f3,$f30 + repl.ph $at,-307 + replv.ph $v1,$s7 + replv.qb $25,$12 + rorv $13,$a3,$s5 + round.l.d $f12,$f1 + round.l.s $f25,$f5 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 + sbe $s7,33($s1) + sce $sp,189($10) + she $24,105($v0) + shilo $ac1,26 + shilov $ac2,$10 + shllv.ph $10,$s0,$s0 + shllv.qb $gp,$v1,$zero + shllv_s.ph $k1,$at,$13 + shllv_s.w $s1,$ra,$k0 + shrav.ph $25,$s2,$s1 + shrav.qb $zero,$24,$11 + shrav_r.ph $s3,$11,$25 + shrav_r.qb $a0,$sp,$s5 + shrav_r.w $s7,$s4,$s6 + shrlv.ph $14,$10,$9 + shrlv.qb $a2,$s2,$11 + sub.ps $f5,$f14,$f26 + subq.ph $ra,$9,$s8 + subq_s.ph $13,$s8,$s5 + subq_s.w $k1,$a2,$a3 + subqh.ph $10,$at,$9 + subqh.w $v0,$a2,$zero + subqh_r.ph $a0,$12,$s6 + subqh_r.w $10,$a2,$gp + subu.ph $9,$s6,$s4 + subu.qb $s6,$a2,$s6 + subu_s.ph $v1,$a1,$s3 + subu_s.qb $s1,$at,$ra + subuh.qb $zero,$gp,$gp + subuh_r.qb $s4,$s8,$s6 + swe $24,94($k0) + swle $v1,-209($gp) + swre $k0,-202($s2) + synci 20023($s0) + tlbginv + tlbginvf + tlbgp + tlbgr + tlbgwi + tlbgwr + tlbinv + tlbinvf + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + wrpgpr $zero,$13 + xor.v $w20,$w21,$w30 + yield $v1,$s0 diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s index 3e9a1d3..26f8b6b 100644 --- a/test/MC/Mips/mips32r2/valid.s +++ b/test/MC/Mips/mips32r2/valid.s @@ -3,154 +3,173 @@ # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s .set noat - abs.d $f7,$f25 # CHECK: encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - clo $t3,$a1 - clz $sp,$gp - ctc1 $a2,$26 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.l.d $f24,$f15 - cvt.l.s $f11,$f29 - cvt.s.d $f26,$f8 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - deret - di $s8 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - ei $t6 - eret - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - ldxc1 $f8,$s7($t7) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - luxc1 $f19,$s6($s5) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - lwxc1 $f12,$s1($s8) - madd $s6,$t5 - madd $zero,$t1 - madd.d $f18,$f19,$f26,$f20 - madd.s $f1,$f31,$f19,$f25 - maddu $s3,$gp - maddu $t8,$s2 - mfc0 $a2,$14,1 - mfc1 $a3,$f27 - mfhc1 $s8,$f24 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $s8,$a0 - move $t9,$a2 - movf $gp,$t0,$fcc7 - movf.d $f6,$f11,$fcc5 - movf.s $f23,$f5,$fcc6 - movn $v1,$s1,$s0 - movn.d $f27,$f21,$k0 - movn.s $f12,$f0,$s7 - movt $zero,$s4,$fcc5 - movt.d $f0,$f2,$fcc0 - movt.s $f30,$f2,$fcc1 - movz $a1,$s6,$t1 - movz.d $f12,$f29,$t1 - movz.s $f25,$f7,$v1 - msub $s7,$k1 - msub.d $f10,$f1,$f31,$f18 - msub.s $f12,$f19,$f10,$f16 - msubu $t7,$a1 - mtc0 $t1,$29,3 - mtc1 $s8,$f9 - mthc1 $zero,$f16 - mthi $s1 - mtlo $sp - mtlo $t9 - mul $s0,$s4,$at - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nmadd.d $f18,$f9,$f14,$f19 - nmadd.s $f0,$f5,$f25,$f12 - nmsub.d $f30,$f8,$f16,$f30 - nmsub.s $f1,$f24,$f19,$f4 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] - rdhwr $sp,$11 - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sdxc1 $f11,$t2($t6) - seb $t9,$t7 - seh $v1,$t4 - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - suxc1 $f12,$k1($t5) - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - swxc1 $f19,$t4($k0) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - wsbh $k1,$t1 - xor $s2,$a0,$s8 + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + clo $11,$a1 + clz $sp,$gp + ctc1 $a2,$26 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + deret + di $s8 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + ei $14 + eret + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + ldxc1 $f8,$s7($15) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + luxc1 $f19,$s6($s5) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwxc1 $f12,$s1($s8) + madd $s6,$13 + madd $zero,$9 + madd.d $f18,$f19,$f26,$f20 + madd.s $f1,$f31,$f19,$f25 + maddu $s3,$gp + maddu $24,$s2 + mfc0 $a2,$14,1 + mfc1 $a3,$f27 + mfhc1 $s8,$f24 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + msub $s7,$k1 + msub.d $f10,$f1,$f31,$f18 + msub.s $f12,$f19,$f10,$f16 + msubu $15,$a1 + mtc0 $9,$29,3 + mtc1 $s8,$f9 + mthc1 $zero,$f16 + mthi $s1 + mtlo $sp + mtlo $25 + mul $s0,$s4,$at + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nmadd.d $f18,$f9,$f14,$f19 + nmadd.s $f0,$f5,$f25,$f12 + nmsub.d $f30,$f8,$f16,$f30 + nmsub.s $f1,$f24,$f19,$f4 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] + rdhwr $sp,$11 + rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] + rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] + rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sdxc1 $f11,$10($14) + seb $25,$15 + seh $v1,$12 + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + suxc1 $f12,$k1($13) + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swl $15,13694($s3) + swr $s1,-26590($14) + swxc1 $f19,$12($k0) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + wsbh $k1,$9 + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s new file mode 100644 index 0000000..aee068a --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s @@ -0,0 +1,15 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips1.s b/test/MC/Mips/mips32r6/invalid-mips1.s new file mode 100644 index 0000000..aa7d407 --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips1.s @@ -0,0 +1,8 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s new file mode 100644 index 0000000..b799c8e --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s @@ -0,0 +1,20 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + beql $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bgezall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bgezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bgtzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + blezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bltzall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bltzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bnel $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips2.s b/test/MC/Mips/mips32r6/invalid-mips2.s new file mode 100644 index 0000000..0638e78 --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips2.s @@ -0,0 +1,14 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlti $14,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tnei $12,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s new file mode 100644 index 0000000..e416a20 --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s @@ -0,0 +1,16 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips32r6/relocations.s b/test/MC/Mips/mips32r6/relocations.s new file mode 100644 index 0000000..4532e42 --- /dev/null +++ b/test/MC/Mips/mips32r6/relocations.s @@ -0,0 +1,55 @@ +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: | FileCheck %s -check-prefix=CHECK-FIXUP +# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r6 \ +# RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF +#------------------------------------------------------------------------------ +# Check that the assembler can handle the documented syntax for fixups. +#------------------------------------------------------------------------------ +# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16 +# CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16 +# CHECK-FIXUP: beqzc $9, bar # encoding: [0xd9,0b001AAAAA,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2 +# CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2 +# CHECK-FIXUP: balc bar # encoding: [0b111010AA,A,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2 +# CHECK-FIXUP: bc bar # encoding: [0b110010AA,A,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2 +# CHECK-FIXUP: aluipc $2, %pcrel_hi(bar) # encoding: [0xec,0x5f,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar@PCREL_HI16, +# CHECK-FIXUP: kind: fixup_MIPS_PCHI16 +# CHECK-FIXUP: addiu $2, $2, %pcrel_lo(bar) # encoding: [0x24,0x42,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar@PCREL_LO16, +# CHECK-FIXUP: kind: fixup_MIPS_PCLO16 +#------------------------------------------------------------------------------ +# Check that the appropriate relocations were created. +#------------------------------------------------------------------------------ +# CHECK-ELF: Relocations [ +# CHECK-ELF: 0x0 R_MIPS_PC16 bar 0x0 +# CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0 +# CHECK-ELF: 0x8 R_MIPS_PC21_S2 bar 0x0 +# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0 +# CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0 +# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0 +# CHECK-ELF: 0x18 R_MIPS_PCHI16 bar 0x0 +# CHECK-ELF: 0x1C R_MIPS_PCLO16 bar 0x0 +# CHECK-ELF: ] + + beqc $5, $6, bar + bnec $5, $6, bar + beqzc $9, bar + bnezc $9, bar + balc bar + bc bar + aluipc $2, %pcrel_hi(bar) + addiu $2, $2, %pcrel_lo(bar) diff --git a/test/MC/Mips/mips32r6/valid-xfail.s b/test/MC/Mips/mips32r6/valid-xfail.s new file mode 100644 index 0000000..0c911d7 --- /dev/null +++ b/test/MC/Mips/mips32r6/valid-xfail.s @@ -0,0 +1,19 @@ +# Instructions that should be valid but currently fail for known reasons (e.g. +# they aren't implemented yet). +# This test is set up to XPASS if any instruction generates an encoding. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 | not FileCheck %s +# CHECK-NOT: encoding +# XFAIL: * + + .set noat + bovc $0, $2, 4 # TODO: bovc $0, $2, 4 # encoding: [0x20,0x40,0x00,0x01] + bovc $2, $4, 4 # TODO: bovc $2, $4, 4 # encoding: [0x20,0x82,0x00,0x01] + bnvc $0, $2, 4 # TODO: bnvc $0, $2, 4 # encoding: [0x60,0x40,0x00,0x01] + bnvc $2, $4, 4 # TODO: bnvc $2, $4, 4 # encoding: [0x60,0x82,0x00,0x01] + beqc $0, $6, 256 # TODO: beqc $6, $zero, 256 # encoding: [0x20,0xc0,0x00,0x40] + beqc $5, $0, 256 # TODO: beqc $5, $zero, 256 # encoding: [0x20,0xa0,0x00,0x40] + beqc $6, $5, 256 # TODO: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40] + bnec $0, $6, 256 # TODO: bnec $6, $zero, 256 # encoding: [0x60,0xc0,0x00,0x40] + bnec $5, $0, 256 # TODO: bnec $5, $zero, 256 # encoding: [0x60,0xa0,0x00,0x40] + bnec $6, $5, 256 # TODO: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40] diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s new file mode 100644 index 0000000..5b4b928 --- /dev/null +++ b/test/MC/Mips/mips32r6/valid.s @@ -0,0 +1,126 @@ +# Instructions that are valid +# +# Branches have some unusual encoding rules in MIPS32r6 so we need to test: +# rs == 0 +# rs != 0 +# rt == 0 +# rt != 0 +# rs < rt +# rs == rt +# rs > rt +# appropriately for each branch instruction +# +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 | FileCheck %s + + .set noat + # FIXME: Add the instructions carried forward from older ISA's + addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19] + align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0] + aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] + aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9] + auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff] + balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8] + bc 14572256 # CHECK: bc 14572256 # encoding: [0xc8,0x37,0x96,0xb8] + bc1eqz $f0,4 # CHECK: bc1eqz $f0, 4 # encoding: [0x45,0x20,0x00,0x01] + bc1eqz $f31,4 # CHECK: bc1eqz $f31, 4 # encoding: [0x45,0x3f,0x00,0x01] + bc1nez $f0,4 # CHECK: bc1nez $f0, 4 # encoding: [0x45,0xa0,0x00,0x01] + bc1nez $f31,4 # CHECK: bc1nez $f31, 4 # encoding: [0x45,0xbf,0x00,0x01] + bc2eqz $0,8 # CHECK: bc2eqz $0, 8 # encoding: [0x49,0x20,0x00,0x02] + bc2eqz $31,8 # CHECK: bc2eqz $31, 8 # encoding: [0x49,0x3f,0x00,0x02] + bc2nez $0,8 # CHECK: bc2nez $0, 8 # encoding: [0x49,0xa0,0x00,0x02] + bc2nez $31,8 # CHECK: bc2nez $31, 8 # encoding: [0x49,0xbf,0x00,0x02] + # beqc requires rs < rt && rs != 0 but we also accept when this is not true. See also bovc + # FIXME: Testcases are in valid-xfail.s at the moment + beqc $5, $6, 256 # CHECK: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40] + beqzalc $2, 1332 # CHECK: beqzalc $2, 1332 # encoding: [0x20,0x02,0x01,0x4d] + # bnec requires rs < rt && rs != 0 but we accept when this is not true. See also bnvc + # FIXME: Testcases are in valid-xfail.s at the moment + bnec $5, $6, 256 # CHECK: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40] + bnezalc $2, 1332 # CHECK: bnezalc $2, 1332 # encoding: [0x60,0x02,0x01,0x4d] + beqzc $5, 72256 # CHECK: beqzc $5, 72256 # encoding: [0xd8,0xa0,0x46,0x90] + bgezalc $2, 1332 # CHECK: bgezalc $2, 1332 # encoding: [0x18,0x42,0x01,0x4d] + bnezc $5, 72256 # CHECK: bnezc $5, 72256 # encoding: [0xf8,0xa0,0x46,0x90] + bltzc $5, 256 # CHECK: bltzc $5, 256 # encoding: [0x5c,0xa5,0x00,0x40] + bgezc $5, 256 # CHECK: bgezc $5, 256 # encoding: [0x58,0xa5,0x00,0x40] + bgtzalc $2, 1332 # CHECK: bgtzalc $2, 1332 # encoding: [0x1c,0x02,0x01,0x4d] + blezc $5, 256 # CHECK: blezc $5, 256 # encoding: [0x58,0x05,0x00,0x40] + bltzalc $2, 1332 # CHECK: bltzalc $2, 1332 # encoding: [0x1c,0x42,0x01,0x4d] + bgtzc $5, 256 # CHECK: bgtzc $5, 256 # encoding: [0x5c,0x05,0x00,0x40] + bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20] + blezalc $2, 1332 # CHECK: blezalc $2, 1332 # encoding: [0x18,0x02,0x01,0x4d] + # bnvc requires that rs >= rt but we accept both. See also bnec + bnvc $0, $0, 4 # CHECK: bnvc $zero, $zero, 4 # encoding: [0x60,0x00,0x00,0x01] + bnvc $2, $0, 4 # CHECK: bnvc $2, $zero, 4 # encoding: [0x60,0x40,0x00,0x01] + bnvc $4, $2, 4 # CHECK: bnvc $4, $2, 4 # encoding: [0x60,0x82,0x00,0x01] + # bovc requires that rs >= rt but we accept both. See also beqc + bovc $0, $0, 4 # CHECK: bovc $zero, $zero, 4 # encoding: [0x20,0x00,0x00,0x01] + bovc $2, $0, 4 # CHECK: bovc $2, $zero, 4 # encoding: [0x20,0x40,0x00,0x01] + bovc $4, $2, 4 # CHECK: bovc $4, $2, 4 # encoding: [0x20,0x82,0x00,0x01] + cmp.f.s $f2,$f3,$f4 # CHECK: cmp.f.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80] + cmp.f.d $f2,$f3,$f4 # CHECK: cmp.f.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80] + cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81] + cmp.un.d $f2,$f3,$f4 # CHECK: cmp.un.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x81] + cmp.eq.s $f2,$f3,$f4 # CHECK: cmp.eq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x82] + cmp.eq.d $f2,$f3,$f4 # CHECK: cmp.eq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x82] + cmp.ueq.s $f2,$f3,$f4 # CHECK: cmp.ueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x83] + cmp.ueq.d $f2,$f3,$f4 # CHECK: cmp.ueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x83] + cmp.olt.s $f2,$f3,$f4 # CHECK: cmp.olt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x84] + cmp.olt.d $f2,$f3,$f4 # CHECK: cmp.olt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x84] + cmp.ult.s $f2,$f3,$f4 # CHECK: cmp.ult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x85] + cmp.ult.d $f2,$f3,$f4 # CHECK: cmp.ult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x85] + cmp.ole.s $f2,$f3,$f4 # CHECK: cmp.ole.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x86] + cmp.ole.d $f2,$f3,$f4 # CHECK: cmp.ole.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x86] + cmp.ule.s $f2,$f3,$f4 # CHECK: cmp.ule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x87] + cmp.ule.d $f2,$f3,$f4 # CHECK: cmp.ule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x87] + cmp.sf.s $f2,$f3,$f4 # CHECK: cmp.sf.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x88] + cmp.sf.d $f2,$f3,$f4 # CHECK: cmp.sf.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x88] + cmp.ngle.s $f2,$f3,$f4 # CHECK: cmp.ngle.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x89] + cmp.ngle.d $f2,$f3,$f4 # CHECK: cmp.ngle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x89] + cmp.seq.s $f2,$f3,$f4 # CHECK: cmp.seq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8a] + cmp.seq.d $f2,$f3,$f4 # CHECK: cmp.seq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8a] + cmp.ngl.s $f2,$f3,$f4 # CHECK: cmp.ngl.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8b] + cmp.ngl.d $f2,$f3,$f4 # CHECK: cmp.ngl.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8b] + cmp.lt.s $f2,$f3,$f4 # CHECK: cmp.lt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8c] + cmp.lt.d $f2,$f3,$f4 # CHECK: cmp.lt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8c] + cmp.nge.s $f2,$f3,$f4 # CHECK: cmp.nge.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8d] + cmp.nge.d $f2,$f3,$f4 # CHECK: cmp.nge.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8d] + cmp.le.s $f2,$f3,$f4 # CHECK: cmp.le.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8e] + cmp.le.d $f2,$f3,$f4 # CHECK: cmp.le.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e] + cmp.ngt.s $f2,$f3,$f4 # CHECK: cmp.ngt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f] + cmp.ngt.d $f2,$f3,$f4 # CHECK: cmp.ngt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f] + div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a] + divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b] + jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00] + jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00] + lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43] + lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43] + mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] + modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb] +# mul $2,$3,$4 # CHECK-TODO: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98] + muh $2,$3,$4 # CHECK: muh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd8] + mulu $2,$3,$4 # CHECK: mulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x99] + muhu $2,$3,$4 # CHECK: muhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd9] + maddf.s $f2,$f3,$f4 # CHECK: maddf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x98] + maddf.d $f2,$f3,$f4 # CHECK: maddf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x98] + msubf.s $f2,$f3,$f4 # CHECK: msubf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x99] + msubf.d $f2,$f3,$f4 # CHECK: msubf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x99] + sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10] + sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10] + seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35] + selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37] + max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d] + max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d] + min.s $f0, $f2, $f4 # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c] + min.d $f0, $f2, $f4 # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c] + maxa.s $f0, $f2, $f4 # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f] + maxa.d $f0, $f2, $f4 # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f] + mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e] + mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e] + seleqz.s $f0, $f2, $f4 # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14] + seleqz.d $f0, $f2, $f4 # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14] + selnez.s $f0, $f2, $f4 # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17] + selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17] + rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a] + rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a] + class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b] + class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b] diff --git a/test/MC/Mips/mips4/invalid-mips5-wrong-error.s b/test/MC/Mips/mips4/invalid-mips5-wrong-error.s new file mode 100644 index 0000000..c6c8968 --- /dev/null +++ b/test/MC/Mips/mips4/invalid-mips5-wrong-error.s @@ -0,0 +1,46 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips4 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips4/invalid-mips5.s b/test/MC/Mips/mips4/invalid-mips5.s new file mode 100644 index 0000000..8c0db00 --- /dev/null +++ b/test/MC/Mips/mips4/invalid-mips5.s @@ -0,0 +1,9 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips4/invalid-mips64.s b/test/MC/Mips/mips4/invalid-mips64.s index e0b69f2..c6245cc 100644 --- a/test/MC/Mips/mips4/invalid-mips64.s +++ b/test/MC/Mips/mips4/invalid-mips64.s @@ -6,7 +6,19 @@ # RUN: FileCheck %s < %t1 .set noat - clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $t8,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msubu $t7,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips4/invalid-mips64r2-xfail.s b/test/MC/Mips/mips4/invalid-mips64r2-xfail.s index 63edb60..a5581fd 100644 --- a/test/MC/Mips/mips4/invalid-mips64r2-xfail.s +++ b/test/MC/Mips/mips4/invalid-mips64r2-xfail.s @@ -8,20 +8,4 @@ # CHECK-NOT: error .set noat - deret - di $s8 - ei $t6 - luxc1 $f19,$s6($s5) - madd $s6,$t5 - madd $zero,$t1 - maddu $s3,$gp - maddu $t8,$s2 - mfc0 $a2,$14,1 - mfhc1 $s8,$f24 - msub $s7,$k1 - msubu $t7,$a1 - mtc0 $t1,$29,3 - mthc1 $zero,$f16 - mul $s0,$s4,$at rdhwr $sp,$11 - suxc1 $f12,$k1($t5) diff --git a/test/MC/Mips/mips4/invalid-mips64r2.s b/test/MC/Mips/mips4/invalid-mips64r2.s index ed2dff8..b259706 100644 --- a/test/MC/Mips/mips4/invalid-mips64r2.s +++ b/test/MC/Mips/mips4/invalid-mips64r2.s @@ -1,22 +1,37 @@ # Instructions that are invalid # -# FIXME: This test should be moved to the mips5 directory when mips5 is supported # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \ # RUN: 2>%t1 # RUN: FileCheck %s < %t1 .set noat - clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $t8,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msubu $t7,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips4/valid-xfail.s b/test/MC/Mips/mips4/valid-xfail.s index baf5c53..ff6f457 100644 --- a/test/MC/Mips/mips4/valid-xfail.s +++ b/test/MC/Mips/mips4/valid-xfail.s @@ -2,53 +2,48 @@ # they aren't implemented yet). # This test is set up to XPASS if any instruction generates an encoding. # -# FIXME: Test MIPS-IV instead of MIPS64 -# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | not FileCheck %s +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | not FileCheck %s # CHECK-NOT: encoding # XFAIL: * - .set noat - c.eq.d $fcc1,$f15,$f15 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.s $fcc3,$f11,$f8 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.s $fcc7,$f1,$f25 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.s $fcc1,$f30,$f4 - madd.d $f18,$f19,$f26,$f20 - madd.s $f1,$f31,$f19,$f25 - msub.d $f10,$f1,$f31,$f18 - msub.s $f12,$f19,$f10,$f16 - nmadd.d $f18,$f9,$f14,$f19 - nmadd.s $f0,$f5,$f25,$f12 - nmsub.d $f30,$f8,$f16,$f30 - nmsub.s $f1,$f24,$f19,$f4 - recip.d $f19,$f6 - recip.s $f3,$f30 - rsqrt.d $f3,$f28 - rsqrt.s $f4,$f8 - tlbp - tlbr - tlbwi - tlbwr + .set noat + c.eq.d $fcc1,$f15,$f15 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.s $fcc3,$f11,$f8 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.s $fcc7,$f1,$f25 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.s $fcc1,$f30,$f4 + madd.d $f18,$f19,$f26,$f20 + madd.s $f1,$f31,$f19,$f25 + msub.d $f10,$f1,$f31,$f18 + msub.s $f12,$f19,$f10,$f16 + nmadd.d $f18,$f9,$f14,$f19 + nmadd.s $f0,$f5,$f25,$f12 + nmsub.d $f30,$f8,$f16,$f30 + nmsub.s $f1,$f24,$f19,$f4 + recip.d $f19,$f6 + recip.s $f3,$f30 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 diff --git a/test/MC/Mips/mips4/valid.s b/test/MC/Mips/mips4/valid.s index 8dc2a23..811584e 100644 --- a/test/MC/Mips/mips4/valid.s +++ b/test/MC/Mips/mips4/valid.s @@ -1,161 +1,194 @@ # Instructions that are valid # -# FIXME: Test MIPS-IV instead of MIPS64 -# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s +# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | FileCheck %s - .set noat - abs.d $f7,$f25 # CHECK: encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.l.d $f1,$f3 - ceil.l.s $f18,$f13 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - ctc1 $a2,$26 - cvt.d.l $f4,$f16 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.l.d $f24,$f15 - cvt.l.s $f11,$f29 - cvt.s.d $f26,$f8 - cvt.s.l $f15,$f30 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - dadd $s3,$at,$ra - daddi $sp,$s4,-27705 - daddiu $k0,$s6,-4586 - ddiv $zero,$k0,$s3 - ddivu $zero,$s0,$s1 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - dmfc1 $t4,$f13 - dmtc1 $s0,$f14 - dmult $s7,$t1 - dmultu $a1,$a2 - dsllv $zero,$s4,$t4 - dsrav $gp,$s2,$s3 - dsrlv $s3,$t6,$s4 - dsub $a3,$s6,$t0 - dsubu $a1,$a1,$k0 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - eret - floor.l.d $f26,$f7 - floor.l.s $f12,$f5 - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ld $sp,-28645($s1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - ldl $t8,-4167($t8) - ldr $t6,-30358($s4) - ldxc1 $f8,$s7($t7) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - lld $zero,-14736($ra) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - lwu $s3,-24086($v1) - lwxc1 $f12,$s1($s8) - mfc1 $a3,$f27 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $a0,$a3 - move $s5,$a0 - move $s8,$a0 - move $t9,$a2 - movf $gp,$t0,$fcc7 - movf.d $f6,$f11,$fcc5 - movf.s $f23,$f5,$fcc6 - movn $v1,$s1,$s0 - movn.d $f27,$f21,$k0 - movn.s $f12,$f0,$s7 - movt $zero,$s4,$fcc5 - movt.d $f0,$f2,$fcc0 - movt.s $f30,$f2,$fcc1 - movz $a1,$s6,$t1 - movz.d $f12,$f29,$t1 - movz.s $f25,$f7,$v1 - mtc1 $s8,$f9 - mthi $s1 - mtlo $sp - mtlo $t9 - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - round.l.d $f12,$f1 - round.l.s $f25,$f5 - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - scd $t7,-8243($sp) - sd $t4,5835($t2) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sdl $a3,-20961($s8) - sdr $t3,-20423($t4) - sdxc1 $f11,$t2($t6) - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - swxc1 $f19,$t4($k0) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.l.d $f23,$f23 - trunc.l.s $f28,$f31 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - xor $s2,$a0,$s8 + .set noat + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + ctc1 $a2,$26 + cvt.d.l $f4,$f16 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.l $f15,$f30 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + dadd $s3,$at,$ra + daddi $sp,$s4,-27705 + daddiu $k0,$s6,-4586 + daddu $s3,$at,$ra + ddiv $zero,$k0,$s3 + ddivu $zero,$s0,$s1 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + dmfc1 $12,$f13 + dmtc1 $s0,$f14 + dmult $s7,$9 + dmultu $a1,$a2 + dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8] + dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8] + dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbb] + dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbb] + dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] + dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf] + dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] + dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] + dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] + dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] + dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + eret + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ld $sp,-28645($s1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + ldl $24,-4167($24) + ldr $14,-30358($s4) + ldxc1 $f8,$s7($15) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + lld $zero,-14736($ra) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwu $s3,-24086($v1) + lwxc1 $f12,$s1($s8) + mfc1 $a3,$f27 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $a0,$a3 + move $s5,$a0 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + mtc1 $s8,$f9 + mthi $s1 + mtlo $sp + mtlo $25 + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + round.l.d $f12,$f1 + round.l.s $f25,$f5 + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + scd $15,-8243($sp) + sd $12,5835($10) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sdl $a3,-20961($s8) + sdr $11,-20423($12) + sdxc1 $f11,$10($14) + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swl $15,13694($s3) + swr $s1,-26590($14) + swxc1 $f19,$12($k0) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips5/invalid-mips64.s b/test/MC/Mips/mips5/invalid-mips64.s new file mode 100644 index 0000000..19d64dc --- /dev/null +++ b/test/MC/Mips/mips5/invalid-mips64.s @@ -0,0 +1,21 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + clo $11,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips4/invalid-mips64-xfail.s b/test/MC/Mips/mips5/invalid-mips64r2-xfail.s index d8ebcd3..b2b612d 100644 --- a/test/MC/Mips/mips4/invalid-mips64-xfail.s +++ b/test/MC/Mips/mips5/invalid-mips64r2-xfail.s @@ -8,15 +8,4 @@ # CHECK-NOT: error .set noat - deret - luxc1 $f19,$s6($s5) - madd $s6,$t5 - madd $zero,$t1 - maddu $s3,$gp - maddu $t8,$s2 - mfc0 $a2,$14,1 - msub $s7,$k1 - msubu $t7,$a1 - mtc0 $t1,$29,3 - mul $s0,$s4,$at - suxc1 $f12,$k1($t5) + rdhwr $sp,$11 diff --git a/test/MC/Mips/mips5/invalid-mips64r2.s b/test/MC/Mips/mips5/invalid-mips64r2.s new file mode 100644 index 0000000..b91e520 --- /dev/null +++ b/test/MC/Mips/mips5/invalid-mips64r2.s @@ -0,0 +1,43 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + clo $11,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr32 $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsbh $v1,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei $14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seb $25,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seh $v1,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + wsbh $k1,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips5/valid-xfail.s b/test/MC/Mips/mips5/valid-xfail.s index 85d961b..8d1d0d7 100644 --- a/test/MC/Mips/mips5/valid-xfail.s +++ b/test/MC/Mips/mips5/valid-xfail.s @@ -2,91 +2,86 @@ # they aren't implemented yet). # This test is set up to XPASS if any instruction generates an encoding. # -# FIXME: Test MIPS-V instead of MIPS64 -# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | not FileCheck %s +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | not FileCheck %s # CHECK-NOT: encoding # XFAIL: * .set noat - abs.ps $f22,$f8 - add.ps $f25,$f27,$f13 - alnv.ps $f12,$f18,$f30,$t4 - c.eq.d $fcc1,$f15,$f15 - c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 - c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 - c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 - cvt.ps.s $f3,$f18,$f19 - cvt.s.pl $f30,$f1 - cvt.s.pu $f14,$f25 - madd.d $f18,$f19,$f26,$f20 - madd.ps $f22,$f3,$f14,$f3 - madd.s $f1,$f31,$f19,$f25 - mov.ps $f22,$f17 - movf.ps $f10,$f28,$fcc6 - movn.ps $f31,$f31,$s3 - movt.ps $f20,$f25,$fcc2 - movz.ps $f18,$f17,$ra - msub.d $f10,$f1,$f31,$f18 - msub.ps $f12,$f14,$f29,$f17 - msub.s $f12,$f19,$f10,$f16 - mul.ps $f14,$f0,$f16 - neg.ps $f19,$f13 - nmadd.d $f18,$f9,$f14,$f19 - nmadd.ps $f27,$f4,$f9,$f25 - nmadd.s $f0,$f5,$f25,$f12 - nmsub.d $f30,$f8,$f16,$f30 - nmsub.ps $f6,$f12,$f14,$f17 - nmsub.s $f1,$f24,$f19,$f4 - pll.ps $f25,$f9,$f30 - plu.ps $f1,$f26,$f29 - pul.ps $f9,$f30,$f26 - puu.ps $f24,$f9,$f2 - recip.d $f19,$f6 - recip.s $f3,$f30 - rsqrt.d $f3,$f28 - rsqrt.s $f4,$f8 - sub.ps $f5,$f14,$f26 - tlbp - tlbr - tlbwi - tlbwr + abs.ps $f22,$f8 + add.ps $f25,$f27,$f13 + alnv.ps $f12,$f18,$f30,$12 + c.eq.d $fcc1,$f15,$f15 + c.eq.ps $fcc5,$f0,$f9 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.ps $fcc6,$f11,$f11 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.ps $fcc1,$f7,$f20 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.ps $f19,$f5 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.ps $f1,$f26 + c.nge.s $fcc3,$f11,$f8 + c.ngl.ps $f21,$f30 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.ps $fcc7,$f12,$f20 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.ps $fcc5,$f30,$f6 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.ps $fcc7,$f21,$f8 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.ps $fcc3,$f7,$f16 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.ps $fcc6,$f31,$f14 + c.seq.s $fcc7,$f1,$f25 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.ps $fcc1,$f5,$f29 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.ps $fcc6,$f17,$f3 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.ps $fcc7,$f14,$f0 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.ps $fcc4,$f2,$f26 + c.un.s $fcc1,$f30,$f4 + cvt.ps.s $f3,$f18,$f19 + cvt.s.pl $f30,$f1 + cvt.s.pu $f14,$f25 + madd.d $f18,$f19,$f26,$f20 + madd.ps $f22,$f3,$f14,$f3 + madd.s $f1,$f31,$f19,$f25 + mov.ps $f22,$f17 + movf.ps $f10,$f28,$fcc6 + movn.ps $f31,$f31,$s3 + movt.ps $f20,$f25,$fcc2 + movz.ps $f18,$f17,$ra + msub.d $f10,$f1,$f31,$f18 + msub.ps $f12,$f14,$f29,$f17 + msub.s $f12,$f19,$f10,$f16 + mul.ps $f14,$f0,$f16 + neg.ps $f19,$f13 + nmadd.d $f18,$f9,$f14,$f19 + nmadd.ps $f27,$f4,$f9,$f25 + nmadd.s $f0,$f5,$f25,$f12 + nmsub.d $f30,$f8,$f16,$f30 + nmsub.ps $f6,$f12,$f14,$f17 + nmsub.s $f1,$f24,$f19,$f4 + pll.ps $f25,$f9,$f30 + plu.ps $f1,$f26,$f29 + pul.ps $f9,$f30,$f26 + puu.ps $f24,$f9,$f2 + recip.d $f19,$f6 + recip.s $f3,$f30 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 + sub.ps $f5,$f14,$f26 diff --git a/test/MC/Mips/mips5/valid.s b/test/MC/Mips/mips5/valid.s index ebe2f70..19aad05 100644 --- a/test/MC/Mips/mips5/valid.s +++ b/test/MC/Mips/mips5/valid.s @@ -1,163 +1,196 @@ # Instructions that are valid # -# FIXME: Test MIPS-V instead of MIPS64 -# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s +# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | FileCheck %s .set noat - abs.d $f7,$f25 # CHECK: encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.l.d $f1,$f3 - ceil.l.s $f18,$f13 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - ctc1 $a2,$26 - cvt.d.l $f4,$f16 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.l.d $f24,$f15 - cvt.l.s $f11,$f29 - cvt.s.d $f26,$f8 - cvt.s.l $f15,$f30 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - dadd $s3,$at,$ra - daddi $sp,$s4,-27705 - daddiu $k0,$s6,-4586 - ddiv $zero,$k0,$s3 - ddivu $zero,$s0,$s1 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - dmfc1 $t4,$f13 - dmtc1 $s0,$f14 - dmult $s7,$t1 - dmultu $a1,$a2 - dsllv $zero,$s4,$t4 - dsrav $gp,$s2,$s3 - dsrlv $s3,$t6,$s4 - dsub $a3,$s6,$t0 - dsubu $a1,$a1,$k0 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - eret - floor.l.d $f26,$f7 - floor.l.s $f12,$f5 - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ld $sp,-28645($s1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - ldl $t8,-4167($t8) - ldr $t6,-30358($s4) - ldxc1 $f8,$s7($t7) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - lld $zero,-14736($ra) - luxc1 $f19,$s6($s5) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - lwu $s3,-24086($v1) - lwxc1 $f12,$s1($s8) - mfc1 $a3,$f27 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $a0,$a3 - move $s5,$a0 - move $s8,$a0 - move $t9,$a2 - movf $gp,$t0,$fcc7 - movf.d $f6,$f11,$fcc5 - movf.s $f23,$f5,$fcc6 - movn $v1,$s1,$s0 - movn.d $f27,$f21,$k0 - movn.s $f12,$f0,$s7 - movt $zero,$s4,$fcc5 - movt.d $f0,$f2,$fcc0 - movt.s $f30,$f2,$fcc1 - movz $a1,$s6,$t1 - movz.d $f12,$f29,$t1 - movz.s $f25,$f7,$v1 - mtc1 $s8,$f9 - mthi $s1 - mtlo $sp - mtlo $t9 - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - round.l.d $f12,$f1 - round.l.s $f25,$f5 - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - scd $t7,-8243($sp) - sd $t4,5835($t2) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sdl $a3,-20961($s8) - sdr $t3,-20423($t4) - sdxc1 $f11,$t2($t6) - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - suxc1 $f12,$k1($t5) - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - swxc1 $f19,$t4($k0) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.l.d $f23,$f23 - trunc.l.s $f28,$f31 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - xor $s2,$a0,$s8 + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + ctc1 $a2,$26 + cvt.d.l $f4,$f16 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.l $f15,$f30 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + dadd $s3,$at,$ra + daddi $sp,$s4,-27705 + daddiu $k0,$s6,-4586 + daddu $s3,$at,$ra + ddiv $zero,$k0,$s3 + ddivu $zero,$s0,$s1 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + dmfc1 $12,$f13 + dmtc1 $s0,$f14 + dmult $s7,$9 + dmultu $a1,$a2 + dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8] + dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8] + dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbb] + dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbb] + dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] + dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf] + dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] + dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] + dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] + dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] + dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + eret + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ld $sp,-28645($s1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + ldl $24,-4167($24) + ldr $14,-30358($s4) + ldxc1 $f8,$s7($15) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + lld $zero,-14736($ra) + luxc1 $f19,$s6($s5) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwu $s3,-24086($v1) + lwxc1 $f12,$s1($s8) + mfc1 $a3,$f27 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $a0,$a3 + move $s5,$a0 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + mtc1 $s8,$f9 + mthi $s1 + mtlo $sp + mtlo $25 + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + round.l.d $f12,$f1 + round.l.s $f25,$f5 + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + scd $15,-8243($sp) + sd $12,5835($10) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sdl $a3,-20961($s8) + sdr $11,-20423($12) + sdxc1 $f11,$10($14) + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + suxc1 $f12,$k1($13) + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swl $15,13694($s3) + swr $s1,-26590($14) + swxc1 $f19,$12($k0) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips64/invalid-mips64r2-xfail.s b/test/MC/Mips/mips64/invalid-mips64r2-xfail.s index 4baf26b..b2b612d 100644 --- a/test/MC/Mips/mips64/invalid-mips64r2-xfail.s +++ b/test/MC/Mips/mips64/invalid-mips64r2-xfail.s @@ -8,8 +8,4 @@ # CHECK-NOT: error .set noat - di $s8 - ei $t6 - mfhc1 $s8,$f24 - mthc1 $zero,$f16 rdhwr $sp,$11 diff --git a/test/MC/Mips/mips64/invalid-mips64r2.s b/test/MC/Mips/mips64/invalid-mips64r2.s index 41aa8ae..1a5abb6 100644 --- a/test/MC/Mips/mips64/invalid-mips64r2.s +++ b/test/MC/Mips/mips64/invalid-mips64r2.s @@ -5,13 +5,25 @@ # RUN: FileCheck %s < %t1 .set noat - dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr32 $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsbh $v1,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei $14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seb $25,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seh $v1,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + wsbh $k1,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64/valid-xfail.s b/test/MC/Mips/mips64/valid-xfail.s index 61bf060..e5455f5 100644 --- a/test/MC/Mips/mips64/valid-xfail.s +++ b/test/MC/Mips/mips64/valid-xfail.s @@ -6,93 +6,89 @@ # CHECK-NOT: encoding # XFAIL: * - .set noat - abs.ps $f22,$f8 - add.ps $f25,$f27,$f13 - alnv.ob $v22,$v19,$v30,$v1 - alnv.ob $v31,$v23,$v30,$at - alnv.ob $v8,$v17,$v30,$a1 - alnv.ps $f12,$f18,$f30,$t4 - c.eq.d $fcc1,$f15,$f15 - c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 - c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 - c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 - cvt.ps.s $f3,$f18,$f19 - cvt.s.pl $f30,$f1 - cvt.s.pu $f14,$f25 - dmfc0 $t2,c0_watchhi,2 - dmtc0 $t7,c0_datalo - madd.d $f18,$f19,$f26,$f20 - madd.ps $f22,$f3,$f14,$f3 - madd.s $f1,$f31,$f19,$f25 - mov.ps $f22,$f17 - movf.ps $f10,$f28,$fcc6 - movn.ps $f31,$f31,$s3 - movt.ps $f20,$f25,$fcc2 - movz.ps $f18,$f17,$ra - msgn.qh $v0,$v24,$v20 - msgn.qh $v12,$v21,$v0[1] - msub.d $f10,$f1,$f31,$f18 - msub.ps $f12,$f14,$f29,$f17 - msub.s $f12,$f19,$f10,$f16 - mul.ps $f14,$f0,$f16 - neg.ps $f19,$f13 - nmadd.d $f18,$f9,$f14,$f19 - nmadd.ps $f27,$f4,$f9,$f25 - nmadd.s $f0,$f5,$f25,$f12 - nmsub.d $f30,$f8,$f16,$f30 - nmsub.ps $f6,$f12,$f14,$f17 - nmsub.s $f1,$f24,$f19,$f4 - pll.ps $f25,$f9,$f30 - plu.ps $f1,$f26,$f29 - pul.ps $f9,$f30,$f26 - puu.ps $f24,$f9,$f2 - recip.d $f19,$f6 - recip.s $f3,$f30 - rsqrt.d $f3,$f28 - rsqrt.s $f4,$f8 - sub.ps $f5,$f14,$f26 - tlbp - tlbr - tlbwi - tlbwr + .set noat + abs.ps $f22,$f8 + add.ps $f25,$f27,$f13 + alnv.ob $v22,$v19,$v30,$v1 + alnv.ob $v31,$v23,$v30,$at + alnv.ob $v8,$v17,$v30,$a1 + alnv.ps $f12,$f18,$f30,$12 + c.eq.d $fcc1,$f15,$f15 + c.eq.ps $fcc5,$f0,$f9 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.ps $fcc6,$f11,$f11 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.ps $fcc1,$f7,$f20 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.ps $f19,$f5 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.ps $f1,$f26 + c.nge.s $fcc3,$f11,$f8 + c.ngl.ps $f21,$f30 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.ps $fcc7,$f12,$f20 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.ps $fcc5,$f30,$f6 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.ps $fcc7,$f21,$f8 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.ps $fcc3,$f7,$f16 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.ps $fcc6,$f31,$f14 + c.seq.s $fcc7,$f1,$f25 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.ps $fcc1,$f5,$f29 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.ps $fcc6,$f17,$f3 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.ps $fcc7,$f14,$f0 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.ps $fcc4,$f2,$f26 + c.un.s $fcc1,$f30,$f4 + cvt.ps.s $f3,$f18,$f19 + cvt.s.pl $f30,$f1 + cvt.s.pu $f14,$f25 + dmfc0 $10,c0_watchhi,2 + dmtc0 $15,c0_datalo + madd.d $f18,$f19,$f26,$f20 + madd.ps $f22,$f3,$f14,$f3 + madd.s $f1,$f31,$f19,$f25 + mov.ps $f22,$f17 + movf.ps $f10,$f28,$fcc6 + movn.ps $f31,$f31,$s3 + movt.ps $f20,$f25,$fcc2 + movz.ps $f18,$f17,$ra + msgn.qh $v0,$v24,$v20 + msgn.qh $v12,$v21,$v0[1] + msub.d $f10,$f1,$f31,$f18 + msub.ps $f12,$f14,$f29,$f17 + msub.s $f12,$f19,$f10,$f16 + mul.ps $f14,$f0,$f16 + neg.ps $f19,$f13 + nmadd.d $f18,$f9,$f14,$f19 + nmadd.ps $f27,$f4,$f9,$f25 + nmadd.s $f0,$f5,$f25,$f12 + nmsub.d $f30,$f8,$f16,$f30 + nmsub.ps $f6,$f12,$f14,$f17 + nmsub.s $f1,$f24,$f19,$f4 + pll.ps $f25,$f9,$f30 + plu.ps $f1,$f26,$f29 + pul.ps $f9,$f30,$f26 + puu.ps $f24,$f9,$f2 + recip.d $f19,$f6 + recip.s $f3,$f30 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 + sub.ps $f5,$f14,$f26 diff --git a/test/MC/Mips/mips64/valid.s b/test/MC/Mips/mips64/valid.s index 9ccb2ff..b9e1002 100644 --- a/test/MC/Mips/mips64/valid.s +++ b/test/MC/Mips/mips64/valid.s @@ -3,174 +3,208 @@ # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s .set noat - abs.d $f7,$f25 # CHECK: encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.l.d $f1,$f3 - ceil.l.s $f18,$f13 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - clo $t3,$a1 - clz $sp,$gp - ctc1 $a2,$26 - cvt.d.l $f4,$f16 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.l.d $f24,$f15 - cvt.l.s $f11,$f29 - cvt.s.d $f26,$f8 - cvt.s.l $f15,$f30 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - dadd $s3,$at,$ra - daddi $sp,$s4,-27705 - daddiu $k0,$s6,-4586 - dclo $s2,$a2 - dclz $s0,$t9 - deret - ddiv $zero,$k0,$s3 - ddivu $zero,$s0,$s1 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - dmfc1 $t4,$f13 - dmtc1 $s0,$f14 - dmult $s7,$t1 - dmultu $a1,$a2 - dsllv $zero,$s4,$t4 - dsrav $gp,$s2,$s3 - dsrlv $s3,$t6,$s4 - dsub $a3,$s6,$t0 - dsubu $a1,$a1,$k0 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - eret - floor.l.d $f26,$f7 - floor.l.s $f12,$f5 - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ld $sp,-28645($s1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - ldl $t8,-4167($t8) - ldr $t6,-30358($s4) - ldxc1 $f8,$s7($t7) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - lld $zero,-14736($ra) - luxc1 $f19,$s6($s5) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - lwu $s3,-24086($v1) - lwxc1 $f12,$s1($s8) - madd $s6,$t5 - madd $zero,$t1 - maddu $s3,$gp - maddu $t8,$s2 - mfc0 $a2,$14,1 - mfc1 $a3,$f27 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $a0,$a3 - move $s5,$a0 - move $s8,$a0 - move $t9,$a2 - movf $gp,$t0,$fcc7 - movf.d $f6,$f11,$fcc5 - movf.s $f23,$f5,$fcc6 - movn $v1,$s1,$s0 - movn.d $f27,$f21,$k0 - movn.s $f12,$f0,$s7 - movt $zero,$s4,$fcc5 - movt.d $f0,$f2,$fcc0 - movt.s $f30,$f2,$fcc1 - movz $a1,$s6,$t1 - movz.d $f12,$f29,$t1 - movz.s $f25,$f7,$v1 - msub $s7,$k1 - msubu $t7,$a1 - mtc0 $t1,$29,3 - mtc1 $s8,$f9 - mthi $s1 - mtlo $sp - mtlo $t9 - mul $s0,$s4,$at - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - round.l.d $f12,$f1 - round.l.s $f25,$f5 - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - scd $t7,-8243($sp) - sd $t4,5835($t2) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sdl $a3,-20961($s8) - sdr $t3,-20423($t4) - sdxc1 $f11,$t2($t6) - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - suxc1 $f12,$k1($t5) - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - swxc1 $f19,$t4($k0) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.l.d $f23,$f23 - trunc.l.s $f28,$f31 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - xor $s2,$a0,$s8 + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + clo $11,$a1 + clz $sp,$gp + ctc1 $a2,$26 + cvt.d.l $f4,$f16 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.l $f15,$f30 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + dadd $s3,$at,$ra + daddi $sp,$s4,-27705 + daddiu $k0,$s6,-4586 + daddu $s3,$at,$ra + dclo $s2,$a2 + dclz $s0,$25 + deret + ddiv $zero,$k0,$s3 + ddivu $zero,$s0,$s1 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + dmfc1 $12,$f13 + dmtc1 $s0,$f14 + dmult $s7,$9 + dmultu $a1,$a2 + dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8] + dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8] + dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbb] + dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbb] + dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] + dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf] + dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] + dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] + dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] + dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] + dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + eret + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ld $sp,-28645($s1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + ldl $24,-4167($24) + ldr $14,-30358($s4) + ldxc1 $f8,$s7($15) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + lld $zero,-14736($ra) + luxc1 $f19,$s6($s5) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwu $s3,-24086($v1) + lwxc1 $f12,$s1($s8) + madd $s6,$13 + madd $zero,$9 + maddu $s3,$gp + maddu $24,$s2 + mfc0 $a2,$14,1 + mfc1 $a3,$f27 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $a0,$a3 + move $s5,$a0 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + msub $s7,$k1 + msubu $15,$a1 + mtc0 $9,$29,3 + mtc1 $s8,$f9 + mthi $s1 + mtlo $sp + mtlo $25 + mul $s0,$s4,$at + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + round.l.d $f12,$f1 + round.l.s $f25,$f5 + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + scd $15,-8243($sp) + sd $12,5835($10) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sdl $a3,-20961($s8) + sdr $11,-20423($12) + sdxc1 $f11,$10($14) + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + suxc1 $f12,$k1($13) + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swl $15,13694($s3) + swr $s1,-26590($14) + swxc1 $f19,$12($k0) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips64r2/valid-xfail.s b/test/MC/Mips/mips64r2/valid-xfail.s index 9d9d6cd..9ac47f6 100644 --- a/test/MC/Mips/mips64r2/valid-xfail.s +++ b/test/MC/Mips/mips64r2/valid-xfail.s @@ -5,312 +5,307 @@ # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | not FileCheck %s # CHECK-NOT: encoding # XFAIL: * -# REQUIRES: asserts - .set noat - abs.ps $f22,$f8 - absq_s.ph $t0,$a0 - absq_s.qb $t7,$s1 - absq_s.w $s3,$ra - add.ps $f25,$f27,$f13 - addq.ph $s1,$t7,$at - addq_s.ph $s3,$s6,$s2 - addq_s.w $a2,$t0,$at - addqh.ph $s4,$t6,$s1 - addqh.w $s7,$s7,$k1 - addqh_r.ph $sp,$t9,$s8 - addqh_r.w $t0,$v1,$zero - addsc $s8,$t7,$t4 - addu.ph $a2,$t6,$s3 - addu.qb $s6,$v1,$v1 - addu_s.ph $a3,$s3,$gp - addu_s.qb $s4,$s8,$s1 - adduh.qb $a1,$a1,$at - adduh_r.qb $a0,$t1,$t4 - addwc $k0,$s6,$s7 - alnv.ob $v22,$v19,$v30,$v1 - alnv.ob $v31,$v23,$v30,$at - alnv.ob $v8,$v17,$v30,$a1 - alnv.ps $f12,$f18,$f30,$t4 - and.v $w10,$w25,$w29 - bitrev $t6,$at - bmnz.v $w15,$w2,$w28 - bmz.v $w13,$w11,$w21 - bsel.v $w28,$w7,$w0 - c.eq.d $fcc1,$f15,$f15 - c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 - c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 - c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 - cvt.ps.s $f3,$f18,$f19 - cmp.eq.ph $s7,$t6 - cmp.le.ph $t0,$t6 - cmp.lt.ph $k0,$sp - cmpgdu.eq.qb $s3,$zero,$k0 - cmpgdu.le.qb $v1,$t7,$s2 - cmpgdu.lt.qb $s0,$gp,$sp - cmpgu.eq.qb $t6,$s6,$s8 - cmpgu.le.qb $t1,$a3,$s4 - cmpgu.lt.qb $sp,$at,$t0 - cmpu.eq.qb $v0,$t8 - cmpu.le.qb $s1,$a1 - cmpu.lt.qb $at,$a3 - cvt.s.pl $f30,$f1 - cvt.s.pu $f14,$f25 - dmfc0 $t2,c0_watchhi,2 - dmfgc0 $gp,c0_perfcnt,6 - dmt $k0 - dmtc0 $t7,c0_datalo - dmtgc0 $a2,c0_watchlo,2 - dpa.w.ph $ac1,$s7,$k0 - dpaq_s.w.ph $ac2,$a0,$t5 - dpaq_sa.l.w $ac0,$a2,$t6 - dpaqx_s.w.ph $ac3,$a0,$t8 - dpaqx_sa.w.ph $ac1,$zero,$s5 - dpau.h.qbl $ac1,$t2,$t8 - dpau.h.qbr $ac1,$s7,$s6 - dpax.w.ph $ac3,$a0,$k0 - dps.w.ph $ac1,$a3,$a1 - dpsq_s.w.ph $ac0,$gp,$k0 - dpsq_sa.l.w $ac0,$a3,$t7 - dpsqx_s.w.ph $ac3,$t5,$a3 - dpsqx_sa.w.ph $ac3,$sp,$s2 - dpsu.h.qbl $ac2,$t6,$t2 - dpsu.h.qbr $ac2,$a1,$s6 - dpsx.w.ph $ac0,$s7,$gp - drorv $at,$a1,$s7 - dvpe $s6 - emt $t0 - evpe $v0 - extpdpv $s6,$ac0,$s8 - extpv $t5,$ac0,$t6 - extrv.w $t0,$ac3,$at - extrv_r.w $t0,$ac1,$s6 - extrv_rs.w $gp,$ac1,$s6 - extrv_s.h $s2,$ac1,$t6 - fclass.d $w14,$w27 - fclass.w $w19,$w28 - fexupl.d $w10,$w29 - fexupl.w $w12,$w27 - fexupr.d $w31,$w15 - fexupr.w $w29,$w12 - ffint_s.d $w1,$w30 - ffint_s.w $w16,$w14 - ffint_u.d $w23,$w18 - ffint_u.w $w19,$w12 - ffql.d $w2,$w3 - ffql.w $w9,$w0 - ffqr.d $w25,$w24 - ffqr.w $w10,$w6 - fill.b $w9,$v1 - fill.d $w28,$t0 - fill.h $w9,$t0 - fill.w $w31,$t7 - flog2.d $w12,$w16 - flog2.w $w19,$w23 - fork $s2,$t0,$a0 - frcp.d $w12,$w4 - frcp.w $w30,$w8 - frint.d $w20,$w8 - frint.w $w11,$w29 - frsqrt.d $w29,$w2 - frsqrt.w $w9,$w8 - fsqrt.d $w3,$w1 - fsqrt.w $w5,$w15 - ftint_s.d $w31,$w26 - ftint_s.w $w27,$w14 - ftint_u.d $w5,$w31 - ftint_u.w $w12,$w29 - ftrunc_s.d $w4,$w22 - ftrunc_s.w $w24,$w7 - ftrunc_u.d $w20,$w25 - ftrunc_u.w $w7,$w26 - insv $s2,$at - iret - lbe $t6,122($t1) - lbue $t3,-108($t2) - lbux $t1,$t6($v0) - lhe $s6,219($v1) - lhue $gp,118($t3) - lhx $sp,$k0($t7) - lle $gp,-237($ra) - lwe $ra,-145($t6) - lwle $t3,-42($t3) - lwre $sp,-152($t8) - lwx $t4,$t4($s4) - madd.d $f18,$f19,$f26,$f20 - madd.ps $f22,$f3,$f14,$f3 - maq_s.w.phl $ac2,$t9,$t3 - maq_s.w.phr $ac0,$t2,$t9 - maq_sa.w.phl $ac3,$a1,$v1 - maq_sa.w.phr $ac1,$at,$t2 - mfgc0 $s6,c0_datahi1 - mflo $t1,$ac2 - modsub $a3,$t4,$a3 - mov.ps $f22,$f17 - movf.ps $f10,$f28,$fcc6 - movn.ps $f31,$f31,$s3 - movt.ps $f20,$f25,$fcc2 - movz.ps $f18,$f17,$ra - msgn.qh $v0,$v24,$v20 - msgn.qh $v12,$v21,$v0[1] - msub $ac2,$sp,$t6 - msub.d $f10,$f1,$f31,$f18 - msub.ps $f12,$f14,$f29,$f17 - msubu $ac2,$a1,$t8 - mtc0 $t1,c0_datahi1 - mtgc0 $s4,$21,7 - mthi $v0,$ac1 - mthlip $a3,$ac0 - mul.ph $s4,$t8,$s0 - mul.ps $f14,$f0,$f16 - mul_s.ph $t2,$t6,$t7 - muleq_s.w.phl $t3,$s4,$s4 - muleq_s.w.phr $s6,$a0,$s8 - muleu_s.ph.qbl $a2,$t6,$t0 - muleu_s.ph.qbr $a1,$ra,$t1 - mulq_rs.ph $s2,$t6,$t7 - mulq_rs.w $at,$s4,$t9 - mulq_s.ph $s0,$k1,$t7 - mulq_s.w $t1,$a3,$s0 - mulsa.w.ph $ac1,$s4,$s6 - mulsaq_s.w.ph $ac0,$ra,$s2 - neg.ps $f19,$f13 - nloc.b $w12,$w30 - nloc.d $w16,$w7 - nloc.h $w21,$w17 - nloc.w $w17,$w16 - nlzc.b $w12,$w7 - nlzc.d $w14,$w14 - nlzc.h $w24,$w24 - nlzc.w $w10,$w4 - nmadd.d $f18,$f9,$f14,$f19 - nmadd.ps $f27,$f4,$f9,$f25 - nmsub.d $f30,$f8,$f16,$f30 - nmsub.ps $f6,$f12,$f14,$f17 - nor.v $w20,$w20,$w15 - or.v $w13,$w23,$w12 - packrl.ph $ra,$t8,$t6 - pcnt.b $w30,$w15 - pcnt.d $w5,$w16 - pcnt.h $w20,$w24 - pcnt.w $w22,$w20 - pick.ph $ra,$a2,$gp - pick.qb $t3,$a0,$gp - pll.ps $f25,$f9,$f30 - plu.ps $f1,$f26,$f29 - preceq.w.phl $s8,$gp - preceq.w.phr $s5,$t7 - precequ.ph.qbl $s7,$ra - precequ.ph.qbla $a0,$t1 - precequ.ph.qbr $ra,$s3 - precequ.ph.qbra $t8,$t0 - preceu.ph.qbl $sp,$t0 - preceu.ph.qbla $s6,$t3 - preceu.ph.qbr $gp,$s1 - preceu.ph.qbra $k1,$s0 - precr.qb.ph $v0,$t4,$s8 - precrq.ph.w $t6,$s8,$t8 - precrq.qb.ph $a2,$t4,$t4 - precrq_rs.ph.w $a1,$k0,$a3 - precrqu_s.qb.ph $zero,$gp,$s5 - pul.ps $f9,$f30,$f26 - puu.ps $f24,$f9,$f2 - raddu.w.qb $t9,$s3 - rdpgpr $s3,$t1 - recip.d $f19,$f6 - recip.s $f3,$f30 - repl.ph $at,-307 - replv.ph $v1,$s7 - replv.qb $t9,$t4 - rorv $t5,$a3,$s5 - rsqrt.d $f3,$f28 - rsqrt.s $f4,$f8 - sbe $s7,33($s1) - sce $sp,189($t2) - she $t8,105($v0) - shilo $ac1,26 - shilov $ac2,$t2 - shllv.ph $t2,$s0,$s0 - shllv.qb $gp,$v1,$zero - shllv_s.ph $k1,$at,$t5 - shllv_s.w $s1,$ra,$k0 - shrav.ph $t9,$s2,$s1 - shrav.qb $zero,$t8,$t3 - shrav_r.ph $s3,$t3,$t9 - shrav_r.qb $a0,$sp,$s5 - shrav_r.w $s7,$s4,$s6 - shrlv.ph $t6,$t2,$t1 - shrlv.qb $a2,$s2,$t3 - sub.ps $f5,$f14,$f26 - subq.ph $ra,$t1,$s8 - subq_s.ph $t5,$s8,$s5 - subq_s.w $k1,$a2,$a3 - subqh.ph $t2,$at,$t1 - subqh.w $v0,$a2,$zero - subqh_r.ph $a0,$t4,$s6 - subqh_r.w $t2,$a2,$gp - subu.ph $t1,$s6,$s4 - subu.qb $s6,$a2,$s6 - subu_s.ph $v1,$a1,$s3 - subu_s.qb $s1,$at,$ra - subuh.qb $zero,$gp,$gp - subuh_r.qb $s4,$s8,$s6 - swe $t8,94($k0) - swle $v1,-209($gp) - swre $k0,-202($s2) - synci 20023($s0) - tlbginv - tlbginvf - tlbgp - tlbgr - tlbgwi - tlbgwr - tlbinv - tlbinvf - tlbp - tlbr - tlbwi - tlbwr - wrpgpr $zero,$t5 - xor.v $w20,$w21,$w30 - yield $v1,$s0 + .set noat + abs.ps $f22,$f8 + absq_s.ph $8,$a0 + absq_s.qb $15,$s1 + absq_s.w $s3,$ra + add.ps $f25,$f27,$f13 + addq.ph $s1,$15,$at + addq_s.ph $s3,$s6,$s2 + addq_s.w $a2,$8,$at + addqh.ph $s4,$14,$s1 + addqh.w $s7,$s7,$k1 + addqh_r.ph $sp,$25,$s8 + addqh_r.w $8,$v1,$zero + addsc $s8,$15,$12 + addu.ph $a2,$14,$s3 + addu.qb $s6,$v1,$v1 + addu_s.ph $a3,$s3,$gp + addu_s.qb $s4,$s8,$s1 + adduh.qb $a1,$a1,$at + adduh_r.qb $a0,$9,$12 + addwc $k0,$s6,$s7 + alnv.ob $v22,$v19,$v30,$v1 + alnv.ob $v31,$v23,$v30,$at + alnv.ob $v8,$v17,$v30,$a1 + alnv.ps $f12,$f18,$f30,$12 + and.v $w10,$w25,$w29 + bitrev $14,$at + bmnz.v $w15,$w2,$w28 + bmz.v $w13,$w11,$w21 + bsel.v $w28,$w7,$w0 + c.eq.d $fcc1,$f15,$f15 + c.eq.ps $fcc5,$f0,$f9 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.ps $fcc6,$f11,$f11 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.ps $fcc1,$f7,$f20 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.ps $f19,$f5 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.ps $f1,$f26 + c.nge.s $fcc3,$f11,$f8 + c.ngl.ps $f21,$f30 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.ps $fcc7,$f12,$f20 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.ps $fcc5,$f30,$f6 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.ps $fcc7,$f21,$f8 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.ps $fcc3,$f7,$f16 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.ps $fcc6,$f31,$f14 + c.seq.s $fcc7,$f1,$f25 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.ps $fcc1,$f5,$f29 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.ps $fcc6,$f17,$f3 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.ps $fcc7,$f14,$f0 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.ps $fcc4,$f2,$f26 + c.un.s $fcc1,$f30,$f4 + cvt.ps.s $f3,$f18,$f19 + cmp.eq.ph $s7,$14 + cmp.le.ph $8,$14 + cmp.lt.ph $k0,$sp + cmpgdu.eq.qb $s3,$zero,$k0 + cmpgdu.le.qb $v1,$15,$s2 + cmpgdu.lt.qb $s0,$gp,$sp + cmpgu.eq.qb $14,$s6,$s8 + cmpgu.le.qb $9,$a3,$s4 + cmpgu.lt.qb $sp,$at,$8 + cmpu.eq.qb $v0,$24 + cmpu.le.qb $s1,$a1 + cmpu.lt.qb $at,$a3 + cvt.s.pl $f30,$f1 + cvt.s.pu $f14,$f25 + dmfc0 $10,c0_watchhi,2 + dmfgc0 $gp,c0_perfcnt,6 + dmt $k0 + dmtc0 $15,c0_datalo + dmtgc0 $a2,c0_watchlo,2 + dpa.w.ph $ac1,$s7,$k0 + dpaq_s.w.ph $ac2,$a0,$13 + dpaq_sa.l.w $ac0,$a2,$14 + dpaqx_s.w.ph $ac3,$a0,$24 + dpaqx_sa.w.ph $ac1,$zero,$s5 + dpau.h.qbl $ac1,$10,$24 + dpau.h.qbr $ac1,$s7,$s6 + dpax.w.ph $ac3,$a0,$k0 + dps.w.ph $ac1,$a3,$a1 + dpsq_s.w.ph $ac0,$gp,$k0 + dpsq_sa.l.w $ac0,$a3,$15 + dpsqx_s.w.ph $ac3,$13,$a3 + dpsqx_sa.w.ph $ac3,$sp,$s2 + dpsu.h.qbl $ac2,$14,$10 + dpsu.h.qbr $ac2,$a1,$s6 + dpsx.w.ph $ac0,$s7,$gp + drorv $at,$a1,$s7 + dvpe $s6 + emt $8 + evpe $v0 + extpdpv $s6,$ac0,$s8 + extpv $13,$ac0,$14 + extrv.w $8,$ac3,$at + extrv_r.w $8,$ac1,$s6 + extrv_rs.w $gp,$ac1,$s6 + extrv_s.h $s2,$ac1,$14 + fclass.d $w14,$w27 + fclass.w $w19,$w28 + fexupl.d $w10,$w29 + fexupl.w $w12,$w27 + fexupr.d $w31,$w15 + fexupr.w $w29,$w12 + ffint_s.d $w1,$w30 + ffint_s.w $w16,$w14 + ffint_u.d $w23,$w18 + ffint_u.w $w19,$w12 + ffql.d $w2,$w3 + ffql.w $w9,$w0 + ffqr.d $w25,$w24 + ffqr.w $w10,$w6 + fill.b $w9,$v1 + fill.d $w28,$8 + fill.h $w9,$8 + fill.w $w31,$15 + flog2.d $w12,$w16 + flog2.w $w19,$w23 + fork $s2,$8,$a0 + frcp.d $w12,$w4 + frcp.w $w30,$w8 + frint.d $w20,$w8 + frint.w $w11,$w29 + frsqrt.d $w29,$w2 + frsqrt.w $w9,$w8 + fsqrt.d $w3,$w1 + fsqrt.w $w5,$w15 + ftint_s.d $w31,$w26 + ftint_s.w $w27,$w14 + ftint_u.d $w5,$w31 + ftint_u.w $w12,$w29 + ftrunc_s.d $w4,$w22 + ftrunc_s.w $w24,$w7 + ftrunc_u.d $w20,$w25 + ftrunc_u.w $w7,$w26 + insv $s2,$at + iret + lbe $14,122($9) + lbue $11,-108($10) + lbux $9,$14($v0) + lhe $s6,219($v1) + lhue $gp,118($11) + lhx $sp,$k0($15) + lle $gp,-237($ra) + lwe $ra,-145($14) + lwle $11,-42($11) + lwre $sp,-152($24) + lwx $12,$12($s4) + madd.d $f18,$f19,$f26,$f20 + madd.ps $f22,$f3,$f14,$f3 + maq_s.w.phl $ac2,$25,$11 + maq_s.w.phr $ac0,$10,$25 + maq_sa.w.phl $ac3,$a1,$v1 + maq_sa.w.phr $ac1,$at,$10 + mfgc0 $s6,c0_datahi1 + mflo $9,$ac2 + modsub $a3,$12,$a3 + mov.ps $f22,$f17 + movf.ps $f10,$f28,$fcc6 + movn.ps $f31,$f31,$s3 + movt.ps $f20,$f25,$fcc2 + movz.ps $f18,$f17,$ra + msgn.qh $v0,$v24,$v20 + msgn.qh $v12,$v21,$v0[1] + msub $ac2,$sp,$14 + msub.d $f10,$f1,$f31,$f18 + msub.ps $f12,$f14,$f29,$f17 + msubu $ac2,$a1,$24 + mtc0 $9,c0_datahi1 + mtgc0 $s4,$21,7 + mthi $v0,$ac1 + mthlip $a3,$ac0 + mul.ph $s4,$24,$s0 + mul.ps $f14,$f0,$f16 + mul_s.ph $10,$14,$15 + muleq_s.w.phl $11,$s4,$s4 + muleq_s.w.phr $s6,$a0,$s8 + muleu_s.ph.qbl $a2,$14,$8 + muleu_s.ph.qbr $a1,$ra,$9 + mulq_rs.ph $s2,$14,$15 + mulq_rs.w $at,$s4,$25 + mulq_s.ph $s0,$k1,$15 + mulq_s.w $9,$a3,$s0 + mulsa.w.ph $ac1,$s4,$s6 + mulsaq_s.w.ph $ac0,$ra,$s2 + neg.ps $f19,$f13 + nloc.b $w12,$w30 + nloc.d $w16,$w7 + nloc.h $w21,$w17 + nloc.w $w17,$w16 + nlzc.b $w12,$w7 + nlzc.d $w14,$w14 + nlzc.h $w24,$w24 + nlzc.w $w10,$w4 + nmadd.d $f18,$f9,$f14,$f19 + nmadd.ps $f27,$f4,$f9,$f25 + nmsub.d $f30,$f8,$f16,$f30 + nmsub.ps $f6,$f12,$f14,$f17 + nor.v $w20,$w20,$w15 + or.v $w13,$w23,$w12 + packrl.ph $ra,$24,$14 + pcnt.b $w30,$w15 + pcnt.d $w5,$w16 + pcnt.h $w20,$w24 + pcnt.w $w22,$w20 + pick.ph $ra,$a2,$gp + pick.qb $11,$a0,$gp + pll.ps $f25,$f9,$f30 + plu.ps $f1,$f26,$f29 + preceq.w.phl $s8,$gp + preceq.w.phr $s5,$15 + precequ.ph.qbl $s7,$ra + precequ.ph.qbla $a0,$9 + precequ.ph.qbr $ra,$s3 + precequ.ph.qbra $24,$8 + preceu.ph.qbl $sp,$8 + preceu.ph.qbla $s6,$11 + preceu.ph.qbr $gp,$s1 + preceu.ph.qbra $k1,$s0 + precr.qb.ph $v0,$12,$s8 + precrq.ph.w $14,$s8,$24 + precrq.qb.ph $a2,$12,$12 + precrq_rs.ph.w $a1,$k0,$a3 + precrqu_s.qb.ph $zero,$gp,$s5 + pul.ps $f9,$f30,$f26 + puu.ps $f24,$f9,$f2 + raddu.w.qb $25,$s3 + rdpgpr $s3,$9 + recip.d $f19,$f6 + recip.s $f3,$f30 + repl.ph $at,-307 + replv.ph $v1,$s7 + replv.qb $25,$12 + rorv $13,$a3,$s5 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 + sbe $s7,33($s1) + sce $sp,189($10) + she $24,105($v0) + shilo $ac1,26 + shilov $ac2,$10 + shllv.ph $10,$s0,$s0 + shllv.qb $gp,$v1,$zero + shllv_s.ph $k1,$at,$13 + shllv_s.w $s1,$ra,$k0 + shrav.ph $25,$s2,$s1 + shrav.qb $zero,$24,$11 + shrav_r.ph $s3,$11,$25 + shrav_r.qb $a0,$sp,$s5 + shrav_r.w $s7,$s4,$s6 + shrlv.ph $14,$10,$9 + shrlv.qb $a2,$s2,$11 + sub.ps $f5,$f14,$f26 + subq.ph $ra,$9,$s8 + subq_s.ph $13,$s8,$s5 + subq_s.w $k1,$a2,$a3 + subqh.ph $10,$at,$9 + subqh.w $v0,$a2,$zero + subqh_r.ph $a0,$12,$s6 + subqh_r.w $10,$a2,$gp + subu.ph $9,$s6,$s4 + subu.qb $s6,$a2,$s6 + subu_s.ph $v1,$a1,$s3 + subu_s.qb $s1,$at,$ra + subuh.qb $zero,$gp,$gp + subuh_r.qb $s4,$s8,$s6 + swe $24,94($k0) + swle $v1,-209($gp) + swre $k0,-202($s2) + synci 20023($s0) + tlbginv + tlbginvf + tlbgp + tlbgr + tlbgwi + tlbgwr + tlbinv + tlbinvf + wrpgpr $zero,$13 + xor.v $w20,$w21,$w30 + yield $v1,$s0 diff --git a/test/MC/Mips/mips64r2/valid.s b/test/MC/Mips/mips64r2/valid.s index 826a6b2..252589d 100644 --- a/test/MC/Mips/mips64r2/valid.s +++ b/test/MC/Mips/mips64r2/valid.s @@ -3,189 +3,231 @@ # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s .set noat - abs.d $f7,$f25 # CHECK: encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.l.d $f1,$f3 - ceil.l.s $f18,$f13 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - clo $t3,$a1 - clz $sp,$gp - ctc1 $a2,$26 - cvt.d.l $f4,$f16 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.l.d $f24,$f15 - cvt.l.s $f11,$f29 - cvt.s.d $f26,$f8 - cvt.s.l $f15,$f30 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - dadd $s3,$at,$ra - daddi $sp,$s4,-27705 - daddiu $k0,$s6,-4586 - dclo $s2,$a2 - dclz $s0,$t9 - deret - di $s8 - ddiv $zero,$k0,$s3 - ddivu $zero,$s0,$s1 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - dmfc1 $t4,$f13 - dmtc1 $s0,$f14 - dmult $s7,$t1 - dmultu $a1,$a2 - dsbh $v1,$t6 - dshd $v0,$sp - dsllv $zero,$s4,$t4 - dsrav $gp,$s2,$s3 - dsrlv $s3,$t6,$s4 - dsub $a3,$s6,$t0 - dsubu $a1,$a1,$k0 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - ei $t6 - eret - floor.l.d $f26,$f7 - floor.l.s $f12,$f5 - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ld $sp,-28645($s1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - ldl $t8,-4167($t8) - ldr $t6,-30358($s4) - ldxc1 $f8,$s7($t7) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - lld $zero,-14736($ra) - luxc1 $f19,$s6($s5) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - lwu $s3,-24086($v1) - lwxc1 $f12,$s1($s8) - madd $s6,$t5 - madd $zero,$t1 - madd.s $f1,$f31,$f19,$f25 - maddu $s3,$gp - maddu $t8,$s2 - mfc0 $a2,$14,1 - mfc1 $a3,$f27 - mfhc1 $s8,$f24 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $a0,$a3 - move $s5,$a0 - move $s8,$a0 - move $t9,$a2 - movf $gp,$t0,$fcc7 - movf.d $f6,$f11,$fcc5 - movf.s $f23,$f5,$fcc6 - movn $v1,$s1,$s0 - movn.d $f27,$f21,$k0 - movn.s $f12,$f0,$s7 - movt $zero,$s4,$fcc5 - movt.d $f0,$f2,$fcc0 - movt.s $f30,$f2,$fcc1 - movz $a1,$s6,$t1 - movz.d $f12,$f29,$t1 - movz.s $f25,$f7,$v1 - msub $s7,$k1 - msub.s $f12,$f19,$f10,$f16 - msubu $t7,$a1 - mtc0 $t1,$29,3 - mtc1 $s8,$f9 - mthc1 $zero,$f16 - mthi $s1 - mtlo $sp - mtlo $t9 - mul $s0,$s4,$at - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nmadd.s $f0,$f5,$f25,$f12 - nmsub.s $f1,$f24,$f19,$f4 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] - rdhwr $sp,$11 - round.l.d $f12,$f1 - round.l.s $f25,$f5 - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - scd $t7,-8243($sp) - sd $t4,5835($t2) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sdl $a3,-20961($s8) - sdr $t3,-20423($t4) - sdxc1 $f11,$t2($t6) - seb $t9,$t7 - seh $v1,$t4 - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - suxc1 $f12,$k1($t5) - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - swxc1 $f19,$t4($k0) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.l.d $f23,$f23 - trunc.l.s $f28,$f31 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - xor $s2,$a0,$s8 - wsbh $k1,$t1 + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + clo $11,$a1 + clz $sp,$gp + ctc1 $a2,$26 + cvt.d.l $f4,$f16 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.l $f15,$f30 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + dadd $s3,$at,$ra + daddi $sp,$s4,-27705 + daddiu $k0,$s6,-4586 + daddu $s3,$at,$ra + dclo $s2,$a2 + dclz $s0,$25 + deret + di $s8 + ddiv $zero,$k0,$s3 + ddivu $zero,$s0,$s1 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + dmfc1 $12,$f13 + dmtc1 $s0,$f14 + dmult $s7,$9 + dmultu $a1,$a2 + drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfa] + drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfa] + drotr32 $1,15 # CHECK: drotr32 $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfe] + drotr32 $1,$14,15 # CHECK: drotr32 $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfe] + drotrv $1,$14,$15 # CHECK: drotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x56] + dsbh $v1,$14 + dshd $v0,$sp + dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8] + dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8] + dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbb] + dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbb] + dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] + dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf] + dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] + dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] + dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] + dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] + dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + ei $14 + eret + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ld $sp,-28645($s1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + ldl $24,-4167($24) + ldr $14,-30358($s4) + ldxc1 $f8,$s7($15) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + lld $zero,-14736($ra) + luxc1 $f19,$s6($s5) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwu $s3,-24086($v1) + lwxc1 $f12,$s1($s8) + madd $s6,$13 + madd $zero,$9 + madd.s $f1,$f31,$f19,$f25 + maddu $s3,$gp + maddu $24,$s2 + mfc0 $a2,$14,1 + mfc1 $a3,$f27 + mfhc1 $s8,$f24 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $a0,$a3 + move $s5,$a0 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + msub $s7,$k1 + msub.s $f12,$f19,$f10,$f16 + msubu $15,$a1 + mtc0 $9,$29,3 + mtc1 $s8,$f9 + mthc1 $zero,$f16 + mthi $s1 + mtlo $sp + mtlo $25 + mul $s0,$s4,$at + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nmadd.s $f0,$f5,$f25,$f12 + nmsub.s $f1,$f24,$f19,$f4 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] + rdhwr $sp,$11 + rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] + rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] + rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] + round.l.d $f12,$f1 + round.l.s $f25,$f5 + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + scd $15,-8243($sp) + sd $12,5835($10) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sdl $a3,-20961($s8) + sdr $11,-20423($12) + sdxc1 $f11,$10($14) + seb $25,$15 + seh $v1,$12 + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + suxc1 $f12,$k1($13) + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swl $15,13694($s3) + swr $s1,-26590($14) + swxc1 $f19,$12($k0) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 + wsbh $k1,$9 diff --git a/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s b/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s new file mode 100644 index 0000000..f7949bb --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s @@ -0,0 +1,15 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips64r6/invalid-mips1.s b/test/MC/Mips/mips64r6/invalid-mips1.s new file mode 100644 index 0000000..1225005 --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips1.s @@ -0,0 +1,8 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64r6/invalid-mips2.s b/test/MC/Mips/mips64r6/invalid-mips2.s new file mode 100644 index 0000000..0638e78 --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips2.s @@ -0,0 +1,14 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlti $14,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tnei $12,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s b/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s new file mode 100644 index 0000000..7424f49 --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s @@ -0,0 +1,23 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ldl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + ldre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + sdle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + sdre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips64r6/invalid-mips3.s b/test/MC/Mips/mips64r6/invalid-mips3.s new file mode 100644 index 0000000..0638e78 --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips3.s @@ -0,0 +1,14 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlti $14,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tnei $12,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s b/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s new file mode 100644 index 0000000..6b980e6 --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s @@ -0,0 +1,44 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + alnv.ps $f12,$f18,$f30,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.ps.pw $f3,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips64r6/relocations.s b/test/MC/Mips/mips64r6/relocations.s new file mode 100644 index 0000000..db84715 --- /dev/null +++ b/test/MC/Mips/mips64r6/relocations.s @@ -0,0 +1,55 @@ +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: | FileCheck %s -check-prefix=CHECK-FIXUP +# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips64r6 \ +# RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF +#------------------------------------------------------------------------------ +# Check that the assembler can handle the documented syntax for fixups. +#------------------------------------------------------------------------------ +# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16 +# CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16 +# CHECK-FIXUP: beqzc $9, bar # encoding: [0xd9,0b001AAAAA,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2 +# CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2 +# CHECK-FIXUP: balc bar # encoding: [0b111010AA,A,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2 +# CHECK-FIXUP: bc bar # encoding: [0b110010AA,A,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2 +# CHECK-FIXUP: aluipc $2, %pcrel_hi(bar) # encoding: [0xec,0x5f,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar@PCREL_HI16, +# CHECK-FIXUP: kind: fixup_MIPS_PCHI16 +# CHECK-FIXUP: addiu $2, $2, %pcrel_lo(bar) # encoding: [0x24,0x42,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar@PCREL_LO16, +# CHECK-FIXUP: kind: fixup_MIPS_PCLO16 +#------------------------------------------------------------------------------ +# Check that the appropriate relocations were created. +#------------------------------------------------------------------------------ +# CHECK-ELF: Relocations [ +# CHECK-ELF: 0x0 R_MIPS_PC16 bar 0x0 +# CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0 +# CHECK-ELF: 0x8 R_MIPS_PC21_S2 bar 0x0 +# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0 +# CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0 +# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0 +# CHECK-ELF: 0x18 R_MIPS_PCHI16 bar 0x0 +# CHECK-ELF: 0x1C R_MIPS_PCLO16 bar 0x0 +# CHECK-ELF: ] + + beqc $5, $6, bar + bnec $5, $6, bar + beqzc $9, bar + bnezc $9, bar + balc bar + bc bar + aluipc $2, %pcrel_hi(bar) + addiu $2, $2, %pcrel_lo(bar) diff --git a/test/MC/Mips/mips64r6/valid-xfail.s b/test/MC/Mips/mips64r6/valid-xfail.s new file mode 100644 index 0000000..a751225 --- /dev/null +++ b/test/MC/Mips/mips64r6/valid-xfail.s @@ -0,0 +1,19 @@ +# Instructions that should be valid but currently fail for known reasons (e.g. +# they aren't implemented yet). +# This test is set up to XPASS if any instruction generates an encoding. +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 | not FileCheck %s +# CHECK-NOT: encoding +# XFAIL: * + + .set noat + bovc $0, $2, 4 # TODO: bovc $0, $2, 4 # encoding: [0x20,0x40,0x00,0x01] + bovc $2, $4, 4 # TODO: bovc $2, $4, 4 # encoding: [0x20,0x82,0x00,0x01] + bnvc $0, $2, 4 # TODO: bnvc $0, $2, 4 # encoding: [0x60,0x40,0x00,0x01] + bnvc $2, $4, 4 # TODO: bnvc $2, $4, 4 # encoding: [0x60,0x82,0x00,0x01] + beqc $0, $6, 256 # TODO: beqc $6, $zero, 256 # encoding: [0x20,0xc0,0x00,0x40] + beqc $5, $0, 256 # TODO: beqc $5, $zero, 256 # encoding: [0x20,0xa0,0x00,0x40] + beqc $6, $5, 256 # TODO: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40] + bnec $0, $6, 256 # TODO: bnec $6, $zero, 256 # encoding: [0x60,0xc0,0x00,0x40] + bnec $5, $0, 256 # TODO: bnec $5, $zero, 256 # encoding: [0x60,0xa0,0x00,0x40] + bnec $6, $5, 256 # TODO: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40] diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s new file mode 100644 index 0000000..efdfc7f --- /dev/null +++ b/test/MC/Mips/mips64r6/valid.s @@ -0,0 +1,139 @@ +# Instructions that are valid +# +# Branches have some unusual encoding rules in MIPS32r6 so we need to test: +# rs == 0 +# rs != 0 +# rt == 0 +# rt != 0 +# rs < rt +# rs == rt +# rs > rt +# appropriately for each branch instruction +# +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 | FileCheck %s + + .set noat + # FIXME: Add the instructions carried forward from older ISA's + addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19] + align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0] + aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] + aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9] + auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff] + balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8] + bc 14572256 # CHECK: bc 14572256 # encoding: [0xc8,0x37,0x96,0xb8] + bc1eqz $f0,4 # CHECK: bc1eqz $f0, 4 # encoding: [0x45,0x20,0x00,0x01] + bc1eqz $f31,4 # CHECK: bc1eqz $f31, 4 # encoding: [0x45,0x3f,0x00,0x01] + bc1nez $f0,4 # CHECK: bc1nez $f0, 4 # encoding: [0x45,0xa0,0x00,0x01] + bc1nez $f31,4 # CHECK: bc1nez $f31, 4 # encoding: [0x45,0xbf,0x00,0x01] + bc2eqz $0,8 # CHECK: bc2eqz $0, 8 # encoding: [0x49,0x20,0x00,0x02] + bc2eqz $31,8 # CHECK: bc2eqz $31, 8 # encoding: [0x49,0x3f,0x00,0x02] + bc2nez $0,8 # CHECK: bc2nez $0, 8 # encoding: [0x49,0xa0,0x00,0x02] + bc2nez $31,8 # CHECK: bc2nez $31, 8 # encoding: [0x49,0xbf,0x00,0x02] + # beqc requires rs < rt && rs != 0 but we also accept when this is not true. See also bovc + # FIXME: Testcases are in valid-xfail.s at the moment + beqc $5, $6, 256 # CHECK: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40] + beqzalc $2, 1332 # CHECK: beqzalc $2, 1332 # encoding: [0x20,0x02,0x01,0x4d] + # bnec requires rs < rt && rs != 0 but we accept when this is not true. See also bnvc + # FIXME: Testcases are in valid-xfail.s at the moment + bnec $5, $6, 256 # CHECK: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40] + bnezalc $2, 1332 # CHECK: bnezalc $2, 1332 # encoding: [0x60,0x02,0x01,0x4d] + beqzc $5, 72256 # CHECK: beqzc $5, 72256 # encoding: [0xd8,0xa0,0x46,0x90] + bgezalc $2, 1332 # CHECK: bgezalc $2, 1332 # encoding: [0x18,0x42,0x01,0x4d] + bnezc $5, 72256 # CHECK: bnezc $5, 72256 # encoding: [0xf8,0xa0,0x46,0x90] + bltzc $5, 256 # CHECK: bltzc $5, 256 # encoding: [0x5c,0xa5,0x00,0x40] + bgezc $5, 256 # CHECK: bgezc $5, 256 # encoding: [0x58,0xa5,0x00,0x40] + bgtzalc $2, 1332 # CHECK: bgtzalc $2, 1332 # encoding: [0x1c,0x02,0x01,0x4d] + blezc $5, 256 # CHECK: blezc $5, 256 # encoding: [0x58,0x05,0x00,0x40] + bltzalc $2, 1332 # CHECK: bltzalc $2, 1332 # encoding: [0x1c,0x42,0x01,0x4d] + bgtzc $5, 256 # CHECK: bgtzc $5, 256 # encoding: [0x5c,0x05,0x00,0x40] + bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20] + blezalc $2, 1332 # CHECK: blezalc $2, 1332 # encoding: [0x18,0x02,0x01,0x4d] + # bnvc requires that rs >= rt but we accept both. See also bnec + bnvc $0, $0, 4 # CHECK: bnvc $zero, $zero, 4 # encoding: [0x60,0x00,0x00,0x01] + bnvc $2, $0, 4 # CHECK: bnvc $2, $zero, 4 # encoding: [0x60,0x40,0x00,0x01] + bnvc $4, $2, 4 # CHECK: bnvc $4, $2, 4 # encoding: [0x60,0x82,0x00,0x01] + # bovc requires that rs >= rt but we accept both. See also beqc + bovc $0, $0, 4 # CHECK: bovc $zero, $zero, 4 # encoding: [0x20,0x00,0x00,0x01] + bovc $2, $0, 4 # CHECK: bovc $2, $zero, 4 # encoding: [0x20,0x40,0x00,0x01] + bovc $4, $2, 4 # CHECK: bovc $4, $2, 4 # encoding: [0x20,0x82,0x00,0x01] + cmp.f.s $f2,$f3,$f4 # CHECK: cmp.f.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80] + cmp.f.d $f2,$f3,$f4 # CHECK: cmp.f.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80] + cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81] + cmp.un.d $f2,$f3,$f4 # CHECK: cmp.un.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x81] + cmp.eq.s $f2,$f3,$f4 # CHECK: cmp.eq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x82] + cmp.eq.d $f2,$f3,$f4 # CHECK: cmp.eq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x82] + cmp.ueq.s $f2,$f3,$f4 # CHECK: cmp.ueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x83] + cmp.ueq.d $f2,$f3,$f4 # CHECK: cmp.ueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x83] + cmp.olt.s $f2,$f3,$f4 # CHECK: cmp.olt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x84] + cmp.olt.d $f2,$f3,$f4 # CHECK: cmp.olt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x84] + cmp.ult.s $f2,$f3,$f4 # CHECK: cmp.ult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x85] + cmp.ult.d $f2,$f3,$f4 # CHECK: cmp.ult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x85] + cmp.ole.s $f2,$f3,$f4 # CHECK: cmp.ole.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x86] + cmp.ole.d $f2,$f3,$f4 # CHECK: cmp.ole.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x86] + cmp.ule.s $f2,$f3,$f4 # CHECK: cmp.ule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x87] + cmp.ule.d $f2,$f3,$f4 # CHECK: cmp.ule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x87] + cmp.sf.s $f2,$f3,$f4 # CHECK: cmp.sf.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x88] + cmp.sf.d $f2,$f3,$f4 # CHECK: cmp.sf.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x88] + cmp.ngle.s $f2,$f3,$f4 # CHECK: cmp.ngle.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x89] + cmp.ngle.d $f2,$f3,$f4 # CHECK: cmp.ngle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x89] + cmp.seq.s $f2,$f3,$f4 # CHECK: cmp.seq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8a] + cmp.seq.d $f2,$f3,$f4 # CHECK: cmp.seq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8a] + cmp.ngl.s $f2,$f3,$f4 # CHECK: cmp.ngl.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8b] + cmp.ngl.d $f2,$f3,$f4 # CHECK: cmp.ngl.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8b] + cmp.lt.s $f2,$f3,$f4 # CHECK: cmp.lt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8c] + cmp.lt.d $f2,$f3,$f4 # CHECK: cmp.lt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8c] + cmp.nge.s $f2,$f3,$f4 # CHECK: cmp.nge.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8d] + cmp.nge.d $f2,$f3,$f4 # CHECK: cmp.nge.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8d] + cmp.le.s $f2,$f3,$f4 # CHECK: cmp.le.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8e] + cmp.le.d $f2,$f3,$f4 # CHECK: cmp.le.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e] + cmp.ngt.s $f2,$f3,$f4 # CHECK: cmp.ngt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f] + cmp.ngt.d $f2,$f3,$f4 # CHECK: cmp.ngt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f] + dalign $4,$2,$3,5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64] + daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34] + dahi $3,0x5678 # CHECK: dahi $3, 22136 # encoding: [0x04,0x66,0x56,0x78] + dati $3,0xabcd # CHECK: dati $3, 43981 # encoding: [0x04,0x7e,0xab,0xcd] + dbitswap $4, $2 # CHECK: dbitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x24] + div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a] + divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b] + jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00] + jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00] + mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] + modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb] + ddiv $2,$3,$4 # CHECK: ddiv $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9e] + ddivu $2,$3,$4 # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f] + dmod $2,$3,$4 # CHECK: dmod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xde] + dmodu $2,$3,$4 # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf] + lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43] + lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43] +# mul $2,$3,$4 # CHECK-TODO: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98] + muh $2,$3,$4 # CHECK: muh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd8] + mulu $2,$3,$4 # CHECK: mulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x99] + muhu $2,$3,$4 # CHECK: muhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd9] + dmul $2,$3,$4 # CHECK: dmul $2, $3, $4 # encoding: [0x00,0x64,0x10,0xb8] + dmuh $2,$3,$4 # CHECK: dmuh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xf8] + dmulu $2,$3,$4 # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xb9] + dmuhu $2,$3,$4 # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xf9] + maddf.s $f2,$f3,$f4 # CHECK: maddf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x98] + maddf.d $f2,$f3,$f4 # CHECK: maddf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x98] + msubf.s $f2,$f3,$f4 # CHECK: msubf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x99] + msubf.d $f2,$f3,$f4 # CHECK: msubf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x99] + sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10] + sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10] + seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35] + selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37] + max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d] + max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d] + min.s $f0, $f2, $f4 # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c] + min.d $f0, $f2, $f4 # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c] + maxa.s $f0, $f2, $f4 # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f] + maxa.d $f0, $f2, $f4 # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f] + mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e] + mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e] + seleqz.s $f0, $f2, $f4 # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14] + seleqz.d $f0, $f2, $f4 # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14] + selnez.s $f0, $f2, $f4 # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17] + selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17] + rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a] + rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a] + class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b] + class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b] diff --git a/test/MC/Mips/mips_directives.s b/test/MC/Mips/mips_directives.s index 6780dd0..1a7d61f 100644 --- a/test/MC/Mips/mips_directives.s +++ b/test/MC/Mips/mips_directives.s @@ -51,7 +51,7 @@ $BB0_4: .set $tmp7, $BB0_4-$BB0_2 .set f6,$f6 # CHECK: abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85] -# CHECK: lui $1, %hi($tmp7) # encoding: [0x3c'A',0x01'A',0x00,0x00] +# CHECK: lui $1, %hi($tmp7) # encoding: [0x3c,0x01,A,A] # CHECK: # fixup A - offset: 0, value: ($tmp7)@ABS_HI, kind: fixup_Mips_HI16 abs.s f6,FPU_MASK lui $1, %hi($tmp7) diff --git a/test/MC/Mips/mips_gprel16.s b/test/MC/Mips/mips_gprel16.s index 716c75e..9dd3fa3 100644 --- a/test/MC/Mips/mips_gprel16.s +++ b/test/MC/Mips/mips_gprel16.s @@ -6,6 +6,9 @@ // RUN: llvm-mc -mcpu=mips32r2 -triple=mipsel-pc-linux -filetype=obj -relocation-model=static %s -o - \ // RUN: | llvm-objdump -disassemble -mattr +mips32r2 - \ // RUN: | FileCheck %s +// RUN: llvm-mc -mcpu=mips32r2 -triple=mips-pc-linux -filetype=obj -relocation-model=static %s -o - \ +// RUN: | llvm-objdump -disassemble -mattr +mips32r2 - \ +// RUN: | FileCheck %s .text .abicalls diff --git a/test/MC/Mips/msa/test_2r.s b/test/MC/Mips/msa/test_2r.s index b657d5f..01bea64 100644 --- a/test/MC/Mips/msa/test_2r.s +++ b/test/MC/Mips/msa/test_2r.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: fill.b $w30, $9 # encoding: [0x7b,0x00,0x4f,0x9e] # CHECK: fill.h $w31, $23 # encoding: [0x7b,0x01,0xbf,0xde] # CHECK: fill.w $w16, $24 # encoding: [0x7b,0x02,0xc4,0x1e] @@ -20,22 +16,6 @@ # CHECK: pcnt.w $w23, $w9 # encoding: [0x7b,0x06,0x4d,0xde] # CHECK: pcnt.d $w21, $w24 # encoding: [0x7b,0x07,0xc5,0x5e] -# CHECKOBJDUMP: fill.b $w30, $9 -# CHECKOBJDUMP: fill.h $w31, $23 -# CHECKOBJDUMP: fill.w $w16, $24 -# CHECKOBJDUMP: nloc.b $w21, $w0 -# CHECKOBJDUMP: nloc.h $w18, $w31 -# CHECKOBJDUMP: nloc.w $w2, $w23 -# CHECKOBJDUMP: nloc.d $w4, $w10 -# CHECKOBJDUMP: nlzc.b $w31, $w2 -# CHECKOBJDUMP: nlzc.h $w27, $w22 -# CHECKOBJDUMP: nlzc.w $w10, $w29 -# CHECKOBJDUMP: nlzc.d $w25, $w9 -# CHECKOBJDUMP: pcnt.b $w20, $w18 -# CHECKOBJDUMP: pcnt.h $w0, $w8 -# CHECKOBJDUMP: pcnt.w $w23, $w9 -# CHECKOBJDUMP: pcnt.d $w21, $w24 - fill.b $w30, $9 fill.h $w31, $23 fill.w $w16, $24 diff --git a/test/MC/Mips/msa/test_2r_msa64.s b/test/MC/Mips/msa/test_2r_msa64.s index 743fb88..f6e35c4 100644 --- a/test/MC/Mips/msa/test_2r_msa64.s +++ b/test/MC/Mips/msa/test_2r_msa64.s @@ -1,11 +1,5 @@ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips64 -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: fill.d $w27, $9 # encoding: [0x7b,0x03,0x4e,0xde] -# CHECKOBJDUMP: fill.d $w27, $9 - fill.d $w27, $9 diff --git a/test/MC/Mips/msa/test_2rf.s b/test/MC/Mips/msa/test_2rf.s index 284a7d9..5d41545 100644 --- a/test/MC/Mips/msa/test_2rf.s +++ b/test/MC/Mips/msa/test_2rf.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: fclass.w $w26, $w12 # encoding: [0x7b,0x20,0x66,0x9e] # CHECK: fclass.d $w24, $w17 # encoding: [0x7b,0x21,0x8e,0x1e] # CHECK: fexupl.w $w8, $w0 # encoding: [0x7b,0x30,0x02,0x1e] @@ -37,39 +33,6 @@ # CHECK: ftrunc_u.w $w17, $w15 # encoding: [0x7b,0x24,0x7c,0x5e] # CHECK: ftrunc_u.d $w5, $w27 # encoding: [0x7b,0x25,0xd9,0x5e] -# CHECKOBJDUMP: fclass.w $w26, $w12 -# CHECKOBJDUMP: fclass.d $w24, $w17 -# CHECKOBJDUMP: fexupl.w $w8, $w0 -# CHECKOBJDUMP: fexupl.d $w17, $w29 -# CHECKOBJDUMP: fexupr.w $w13, $w4 -# CHECKOBJDUMP: fexupr.d $w5, $w2 -# CHECKOBJDUMP: ffint_s.w $w20, $w29 -# CHECKOBJDUMP: ffint_s.d $w12, $w15 -# CHECKOBJDUMP: ffint_u.w $w7, $w27 -# CHECKOBJDUMP: ffint_u.d $w19, $w16 -# CHECKOBJDUMP: ffql.w $w31, $w13 -# CHECKOBJDUMP: ffql.d $w12, $w13 -# CHECKOBJDUMP: ffqr.w $w27, $w30 -# CHECKOBJDUMP: ffqr.d $w30, $w15 -# CHECKOBJDUMP: flog2.w $w25, $w31 -# CHECKOBJDUMP: flog2.d $w18, $w10 -# CHECKOBJDUMP: frint.w $w7, $w15 -# CHECKOBJDUMP: frint.d $w21, $w22 -# CHECKOBJDUMP: frcp.w $w19, $w0 -# CHECKOBJDUMP: frcp.d $w4, $w14 -# CHECKOBJDUMP: frsqrt.w $w12, $w17 -# CHECKOBJDUMP: frsqrt.d $w23, $w11 -# CHECKOBJDUMP: fsqrt.w $w0, $w11 -# CHECKOBJDUMP: fsqrt.d $w15, $w12 -# CHECKOBJDUMP: ftint_s.w $w30, $w5 -# CHECKOBJDUMP: ftint_s.d $w5, $w23 -# CHECKOBJDUMP: ftint_u.w $w20, $w14 -# CHECKOBJDUMP: ftint_u.d $w23, $w21 -# CHECKOBJDUMP: ftrunc_s.w $w29, $w17 -# CHECKOBJDUMP: ftrunc_s.d $w12, $w27 -# CHECKOBJDUMP: ftrunc_u.w $w17, $w15 -# CHECKOBJDUMP: ftrunc_u.d $w5, $w27 - fclass.w $w26, $w12 fclass.d $w24, $w17 fexupl.w $w8, $w0 diff --git a/test/MC/Mips/msa/test_3r.s b/test/MC/Mips/msa/test_3r.s index d6b33f1..df2e1e1 100644 --- a/test/MC/Mips/msa/test_3r.s +++ b/test/MC/Mips/msa/test_3r.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: add_a.b $w26, $w9, $w4 # encoding: [0x78,0x04,0x4e,0x90] # CHECK: add_a.h $w23, $w27, $w31 # encoding: [0x78,0x3f,0xdd,0xd0] # CHECK: add_a.w $w11, $w6, $w22 # encoding: [0x78,0x56,0x32,0xd0] @@ -247,249 +243,6 @@ # CHECK: vshf.w $w16, $w30, $w25 # encoding: [0x78,0x59,0xf4,0x15] # CHECK: vshf.d $w19, $w11, $w15 # encoding: [0x78,0x6f,0x5c,0xd5] -# CHECKOBJDUMP: add_a.b $w26, $w9, $w4 -# CHECKOBJDUMP: add_a.h $w23, $w27, $w31 -# CHECKOBJDUMP: add_a.w $w11, $w6, $w22 -# CHECKOBJDUMP: add_a.d $w6, $w10, $w0 -# CHECKOBJDUMP: adds_a.b $w19, $w24, $w19 -# CHECKOBJDUMP: adds_a.h $w25, $w6, $w4 -# CHECKOBJDUMP: adds_a.w $w25, $w17, $w27 -# CHECKOBJDUMP: adds_a.d $w15, $w18, $w26 -# CHECKOBJDUMP: adds_s.b $w29, $w11, $w19 -# CHECKOBJDUMP: adds_s.h $w5, $w23, $w26 -# CHECKOBJDUMP: adds_s.w $w16, $w14, $w13 -# CHECKOBJDUMP: adds_s.d $w2, $w14, $w28 -# CHECKOBJDUMP: adds_u.b $w3, $w17, $w14 -# CHECKOBJDUMP: adds_u.h $w10, $w30, $w4 -# CHECKOBJDUMP: adds_u.w $w15, $w18, $w20 -# CHECKOBJDUMP: adds_u.d $w30, $w10, $w9 -# CHECKOBJDUMP: addv.b $w24, $w20, $w21 -# CHECKOBJDUMP: addv.h $w4, $w13, $w27 -# CHECKOBJDUMP: addv.w $w19, $w11, $w14 -# CHECKOBJDUMP: addv.d $w2, $w21, $w31 -# CHECKOBJDUMP: asub_s.b $w23, $w16, $w3 -# CHECKOBJDUMP: asub_s.h $w22, $w17, $w25 -# CHECKOBJDUMP: asub_s.w $w24, $w1, $w9 -# CHECKOBJDUMP: asub_s.d $w13, $w12, $w12 -# CHECKOBJDUMP: asub_u.b $w10, $w29, $w11 -# CHECKOBJDUMP: asub_u.h $w18, $w9, $w15 -# CHECKOBJDUMP: asub_u.w $w10, $w19, $w31 -# CHECKOBJDUMP: asub_u.d $w17, $w10, $w0 -# CHECKOBJDUMP: ave_s.b $w2, $w5, $w1 -# CHECKOBJDUMP: ave_s.h $w16, $w19, $w9 -# CHECKOBJDUMP: ave_s.w $w17, $w31, $w5 -# CHECKOBJDUMP: ave_s.d $w27, $w25, $w10 -# CHECKOBJDUMP: ave_u.b $w16, $w19, $w9 -# CHECKOBJDUMP: ave_u.h $w28, $w28, $w11 -# CHECKOBJDUMP: ave_u.w $w11, $w12, $w11 -# CHECKOBJDUMP: ave_u.d $w30, $w19, $w28 -# CHECKOBJDUMP: aver_s.b $w26, $w16, $w2 -# CHECKOBJDUMP: aver_s.h $w31, $w27, $w27 -# CHECKOBJDUMP: aver_s.w $w28, $w18, $w25 -# CHECKOBJDUMP: aver_s.d $w29, $w21, $w27 -# CHECKOBJDUMP: aver_u.b $w29, $w26, $w3 -# CHECKOBJDUMP: aver_u.h $w18, $w18, $w9 -# CHECKOBJDUMP: aver_u.w $w17, $w25, $w29 -# CHECKOBJDUMP: aver_u.d $w22, $w22, $w19 -# CHECKOBJDUMP: bclr.b $w2, $w15, $w29 -# CHECKOBJDUMP: bclr.h $w16, $w21, $w28 -# CHECKOBJDUMP: bclr.w $w19, $w2, $w9 -# CHECKOBJDUMP: bclr.d $w27, $w31, $w4 -# CHECKOBJDUMP: binsl.b $w5, $w16, $w24 -# CHECKOBJDUMP: binsl.h $w30, $w5, $w10 -# CHECKOBJDUMP: binsl.w $w14, $w15, $w13 -# CHECKOBJDUMP: binsl.d $w23, $w20, $w12 -# CHECKOBJDUMP: binsr.b $w22, $w11, $w2 -# CHECKOBJDUMP: binsr.h $w0, $w26, $w6 -# CHECKOBJDUMP: binsr.w $w26, $w3, $w28 -# CHECKOBJDUMP: binsr.d $w0, $w0, $w21 -# CHECKOBJDUMP: bneg.b $w0, $w11, $w24 -# CHECKOBJDUMP: bneg.h $w28, $w16, $w4 -# CHECKOBJDUMP: bneg.w $w3, $w26, $w19 -# CHECKOBJDUMP: bneg.d $w13, $w29, $w15 -# CHECKOBJDUMP: bset.b $w31, $w5, $w31 -# CHECKOBJDUMP: bset.h $w14, $w12, $w6 -# CHECKOBJDUMP: bset.w $w31, $w9, $w12 -# CHECKOBJDUMP: bset.d $w5, $w22, $w5 -# CHECKOBJDUMP: ceq.b $w31, $w31, $w18 -# CHECKOBJDUMP: ceq.h $w10, $w27, $w9 -# CHECKOBJDUMP: ceq.w $w9, $w5, $w14 -# CHECKOBJDUMP: ceq.d $w5, $w17, $w0 -# CHECKOBJDUMP: cle_s.b $w23, $w4, $w9 -# CHECKOBJDUMP: cle_s.h $w22, $w27, $w19 -# CHECKOBJDUMP: cle_s.w $w30, $w26, $w10 -# CHECKOBJDUMP: cle_s.d $w18, $w5, $w10 -# CHECKOBJDUMP: cle_u.b $w1, $w25, $w0 -# CHECKOBJDUMP: cle_u.h $w7, $w0, $w29 -# CHECKOBJDUMP: cle_u.w $w25, $w18, $w1 -# CHECKOBJDUMP: cle_u.d $w6, $w0, $w30 -# CHECKOBJDUMP: clt_s.b $w25, $w2, $w21 -# CHECKOBJDUMP: clt_s.h $w2, $w19, $w9 -# CHECKOBJDUMP: clt_s.w $w23, $w8, $w16 -# CHECKOBJDUMP: clt_s.d $w7, $w30, $w12 -# CHECKOBJDUMP: clt_u.b $w2, $w31, $w13 -# CHECKOBJDUMP: clt_u.h $w16, $w31, $w23 -# CHECKOBJDUMP: clt_u.w $w3, $w24, $w9 -# CHECKOBJDUMP: clt_u.d $w7, $w0, $w1 -# CHECKOBJDUMP: div_s.b $w29, $w3, $w18 -# CHECKOBJDUMP: div_s.h $w17, $w16, $w13 -# CHECKOBJDUMP: div_s.w $w4, $w25, $w30 -# CHECKOBJDUMP: div_s.d $w31, $w9, $w20 -# CHECKOBJDUMP: div_u.b $w6, $w29, $w10 -# CHECKOBJDUMP: div_u.h $w24, $w21, $w14 -# CHECKOBJDUMP: div_u.w $w29, $w14, $w25 -# CHECKOBJDUMP: div_u.d $w31, $w1, $w21 -# CHECKOBJDUMP: dotp_s.h $w23, $w22, $w25 -# CHECKOBJDUMP: dotp_s.w $w20, $w14, $w5 -# CHECKOBJDUMP: dotp_s.d $w17, $w2, $w22 -# CHECKOBJDUMP: dotp_u.h $w13, $w2, $w6 -# CHECKOBJDUMP: dotp_u.w $w15, $w22, $w21 -# CHECKOBJDUMP: dotp_u.d $w4, $w16, $w26 -# CHECKOBJDUMP: dpadd_s.h $w1, $w28, $w22 -# CHECKOBJDUMP: dpadd_s.w $w10, $w1, $w12 -# CHECKOBJDUMP: dpadd_s.d $w3, $w21, $w27 -# CHECKOBJDUMP: dpadd_u.h $w17, $w5, $w20 -# CHECKOBJDUMP: dpadd_u.w $w24, $w8, $w16 -# CHECKOBJDUMP: dpadd_u.d $w15, $w29, $w16 -# CHECKOBJDUMP: dpsub_s.h $w4, $w11, $w12 -# CHECKOBJDUMP: dpsub_s.w $w4, $w7, $w6 -# CHECKOBJDUMP: dpsub_s.d $w31, $w12, $w28 -# CHECKOBJDUMP: dpsub_u.h $w4, $w25, $w17 -# CHECKOBJDUMP: dpsub_u.w $w19, $w25, $w16 -# CHECKOBJDUMP: dpsub_u.d $w7, $w10, $w26 -# CHECKOBJDUMP: hadd_s.h $w28, $w24, $w2 -# CHECKOBJDUMP: hadd_s.w $w24, $w17, $w11 -# CHECKOBJDUMP: hadd_s.d $w17, $w15, $w20 -# CHECKOBJDUMP: hadd_u.h $w12, $w29, $w17 -# CHECKOBJDUMP: hadd_u.w $w9, $w5, $w6 -# CHECKOBJDUMP: hadd_u.d $w1, $w20, $w6 -# CHECKOBJDUMP: hsub_s.h $w16, $w14, $w29 -# CHECKOBJDUMP: hsub_s.w $w9, $w13, $w11 -# CHECKOBJDUMP: hsub_s.d $w30, $w18, $w14 -# CHECKOBJDUMP: hsub_u.h $w7, $w12, $w14 -# CHECKOBJDUMP: hsub_u.w $w21, $w5, $w5 -# CHECKOBJDUMP: hsub_u.d $w11, $w12, $w31 -# CHECKOBJDUMP: ilvev.b $w18, $w16, $w30 -# CHECKOBJDUMP: ilvev.h $w14, $w0, $w13 -# CHECKOBJDUMP: ilvev.w $w12, $w25, $w22 -# CHECKOBJDUMP: ilvev.d $w30, $w27, $w3 -# CHECKOBJDUMP: ilvl.b $w29, $w3, $w21 -# CHECKOBJDUMP: ilvl.h $w27, $w10, $w17 -# CHECKOBJDUMP: ilvl.w $w6, $w1, $w0 -# CHECKOBJDUMP: ilvl.d $w3, $w16, $w24 -# CHECKOBJDUMP: ilvod.b $w11, $w5, $w20 -# CHECKOBJDUMP: ilvod.h $w18, $w13, $w31 -# CHECKOBJDUMP: ilvod.w $w29, $w16, $w24 -# CHECKOBJDUMP: ilvod.d $w22, $w12, $w29 -# CHECKOBJDUMP: ilvr.b $w4, $w30, $w6 -# CHECKOBJDUMP: ilvr.h $w28, $w19, $w29 -# CHECKOBJDUMP: ilvr.w $w18, $w20, $w21 -# CHECKOBJDUMP: ilvr.d $w23, $w30, $w12 -# CHECKOBJDUMP: maddv.b $w17, $w31, $w29 -# CHECKOBJDUMP: maddv.h $w7, $w24, $w9 -# CHECKOBJDUMP: maddv.w $w22, $w22, $w20 -# CHECKOBJDUMP: maddv.d $w30, $w26, $w20 -# CHECKOBJDUMP: max_a.b $w23, $w11, $w23 -# CHECKOBJDUMP: max_a.h $w20, $w5, $w30 -# CHECKOBJDUMP: max_a.w $w7, $w18, $w30 -# CHECKOBJDUMP: max_a.d $w8, $w8, $w31 -# CHECKOBJDUMP: max_s.b $w10, $w1, $w19 -# CHECKOBJDUMP: max_s.h $w15, $w29, $w17 -# CHECKOBJDUMP: max_s.w $w15, $w29, $w14 -# CHECKOBJDUMP: max_s.d $w25, $w24, $w3 -# CHECKOBJDUMP: max_u.b $w12, $w24, $w5 -# CHECKOBJDUMP: max_u.h $w5, $w6, $w7 -# CHECKOBJDUMP: max_u.w $w16, $w4, $w7 -# CHECKOBJDUMP: max_u.d $w26, $w12, $w24 -# CHECKOBJDUMP: min_a.b $w4, $w26, $w1 -# CHECKOBJDUMP: min_a.h $w12, $w13, $w31 -# CHECKOBJDUMP: min_a.w $w28, $w20, $w0 -# CHECKOBJDUMP: min_a.d $w12, $w20, $w19 -# CHECKOBJDUMP: min_s.b $w19, $w3, $w14 -# CHECKOBJDUMP: min_s.h $w27, $w21, $w8 -# CHECKOBJDUMP: min_s.w $w0, $w14, $w30 -# CHECKOBJDUMP: min_s.d $w6, $w8, $w21 -# CHECKOBJDUMP: min_u.b $w22, $w26, $w8 -# CHECKOBJDUMP: min_u.h $w7, $w27, $w12 -# CHECKOBJDUMP: min_u.w $w8, $w20, $w14 -# CHECKOBJDUMP: min_u.d $w26, $w14, $w15 -# CHECKOBJDUMP: mod_s.b $w18, $w1, $w26 -# CHECKOBJDUMP: mod_s.h $w31, $w30, $w28 -# CHECKOBJDUMP: mod_s.w $w2, $w6, $w13 -# CHECKOBJDUMP: mod_s.d $w21, $w27, $w22 -# CHECKOBJDUMP: mod_u.b $w16, $w7, $w13 -# CHECKOBJDUMP: mod_u.h $w24, $w8, $w7 -# CHECKOBJDUMP: mod_u.w $w30, $w2, $w17 -# CHECKOBJDUMP: mod_u.d $w31, $w2, $w25 -# CHECKOBJDUMP: msubv.b $w14, $w5, $w12 -# CHECKOBJDUMP: msubv.h $w6, $w7, $w30 -# CHECKOBJDUMP: msubv.w $w13, $w2, $w21 -# CHECKOBJDUMP: msubv.d $w16, $w14, $w27 -# CHECKOBJDUMP: mulv.b $w20, $w3, $w13 -# CHECKOBJDUMP: mulv.h $w27, $w26, $w14 -# CHECKOBJDUMP: mulv.w $w10, $w29, $w3 -# CHECKOBJDUMP: mulv.d $w7, $w19, $w29 -# CHECKOBJDUMP: pckev.b $w5, $w27, $w7 -# CHECKOBJDUMP: pckev.h $w1, $w4, $w27 -# CHECKOBJDUMP: pckev.w $w30, $w20, $w0 -# CHECKOBJDUMP: pckev.d $w6, $w1, $w15 -# CHECKOBJDUMP: pckod.b $w18, $w28, $w30 -# CHECKOBJDUMP: pckod.h $w26, $w5, $w8 -# CHECKOBJDUMP: pckod.w $w9, $w4, $w2 -# CHECKOBJDUMP: pckod.d $w30, $w22, $w20 -# CHECKOBJDUMP: sld.b $w5, $w23[$12] -# CHECKOBJDUMP: sld.h $w1, $w23[$3] -# CHECKOBJDUMP: sld.w $w20, $w8[$9] -# CHECKOBJDUMP: sld.d $w7, $w23[$fp] -# CHECKOBJDUMP: sll.b $w3, $w0, $w17 -# CHECKOBJDUMP: sll.h $w17, $w27, $w3 -# CHECKOBJDUMP: sll.w $w16, $w7, $w6 -# CHECKOBJDUMP: sll.d $w9, $w0, $w26 -# CHECKOBJDUMP: splat.b $w28, $w1[$1] -# CHECKOBJDUMP: splat.h $w2, $w11[$11] -# CHECKOBJDUMP: splat.w $w22, $w0[$11] -# CHECKOBJDUMP: splat.d $w0, $w0[$2] -# CHECKOBJDUMP: sra.b $w28, $w4, $w17 -# CHECKOBJDUMP: sra.h $w13, $w9, $w3 -# CHECKOBJDUMP: sra.w $w27, $w21, $w19 -# CHECKOBJDUMP: sra.d $w30, $w8, $w23 -# CHECKOBJDUMP: srar.b $w19, $w18, $w18 -# CHECKOBJDUMP: srar.h $w7, $w23, $w8 -# CHECKOBJDUMP: srar.w $w1, $w12, $w2 -# CHECKOBJDUMP: srar.d $w21, $w7, $w14 -# CHECKOBJDUMP: srl.b $w12, $w3, $w19 -# CHECKOBJDUMP: srl.h $w23, $w31, $w20 -# CHECKOBJDUMP: srl.w $w18, $w27, $w11 -# CHECKOBJDUMP: srl.d $w3, $w12, $w26 -# CHECKOBJDUMP: srlr.b $w15, $w21, $w11 -# CHECKOBJDUMP: srlr.h $w21, $w13, $w19 -# CHECKOBJDUMP: srlr.w $w6, $w30, $w3 -# CHECKOBJDUMP: srlr.d $w1, $w2, $w14 -# CHECKOBJDUMP: subs_s.b $w25, $w15, $w1 -# CHECKOBJDUMP: subs_s.h $w28, $w25, $w22 -# CHECKOBJDUMP: subs_s.w $w10, $w12, $w21 -# CHECKOBJDUMP: subs_s.d $w4, $w20, $w18 -# CHECKOBJDUMP: subs_u.b $w21, $w6, $w25 -# CHECKOBJDUMP: subs_u.h $w3, $w10, $w7 -# CHECKOBJDUMP: subs_u.w $w9, $w15, $w10 -# CHECKOBJDUMP: subs_u.d $w7, $w19, $w10 -# CHECKOBJDUMP: subsus_u.b $w6, $w7, $w12 -# CHECKOBJDUMP: subsus_u.h $w6, $w29, $w19 -# CHECKOBJDUMP: subsus_u.w $w7, $w15, $w7 -# CHECKOBJDUMP: subsus_u.d $w9, $w3, $w15 -# CHECKOBJDUMP: subsuu_s.b $w22, $w3, $w31 -# CHECKOBJDUMP: subsuu_s.h $w19, $w23, $w22 -# CHECKOBJDUMP: subsuu_s.w $w9, $w10, $w13 -# CHECKOBJDUMP: subsuu_s.d $w5, $w6, $w0 -# CHECKOBJDUMP: subv.b $w6, $w13, $w19 -# CHECKOBJDUMP: subv.h $w4, $w25, $w12 -# CHECKOBJDUMP: subv.w $w27, $w27, $w11 -# CHECKOBJDUMP: subv.d $w9, $w24, $w10 -# CHECKOBJDUMP: vshf.b $w3, $w16, $w5 -# CHECKOBJDUMP: vshf.h $w20, $w19, $w8 -# CHECKOBJDUMP: vshf.w $w16, $w30, $w25 -# CHECKOBJDUMP: vshf.d $w19, $w11, $w15 - add_a.b $w26, $w9, $w4 add_a.h $w23, $w27, $w31 add_a.w $w11, $w6, $w22 diff --git a/test/MC/Mips/msa/test_3rf.s b/test/MC/Mips/msa/test_3rf.s index 6787d85..c5896d7 100644 --- a/test/MC/Mips/msa/test_3rf.s +++ b/test/MC/Mips/msa/test_3rf.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: fadd.w $w28, $w19, $w28 # encoding: [0x78,0x1c,0x9f,0x1b] # CHECK: fadd.d $w13, $w2, $w29 # encoding: [0x78,0x3d,0x13,0x5b] # CHECK: fcaf.w $w14, $w11, $w25 # encoding: [0x78,0x19,0x5b,0x9a] @@ -87,89 +83,6 @@ # CHECK: mulr_q.h $w6, $w20, $w19 # encoding: [0x7b,0x13,0xa1,0x9c] # CHECK: mulr_q.w $w27, $w1, $w20 # encoding: [0x7b,0x34,0x0e,0xdc] -# CHECKOBJDUMP: fadd.w $w28, $w19, $w28 -# CHECKOBJDUMP: fadd.d $w13, $w2, $w29 -# CHECKOBJDUMP: fcaf.w $w14, $w11, $w25 -# CHECKOBJDUMP: fcaf.d $w1, $w1, $w19 -# CHECKOBJDUMP: fceq.w $w1, $w23, $w16 -# CHECKOBJDUMP: fceq.d $w0, $w8, $w16 -# CHECKOBJDUMP: fcle.w $w16, $w9, $w24 -# CHECKOBJDUMP: fcle.d $w27, $w14, $w1 -# CHECKOBJDUMP: fclt.w $w28, $w8, $w8 -# CHECKOBJDUMP: fclt.d $w30, $w25, $w11 -# CHECKOBJDUMP: fcne.w $w2, $w18, $w23 -# CHECKOBJDUMP: fcne.d $w14, $w20, $w15 -# CHECKOBJDUMP: fcor.w $w10, $w18, $w25 -# CHECKOBJDUMP: fcor.d $w17, $w25, $w11 -# CHECKOBJDUMP: fcueq.w $w14, $w2, $w21 -# CHECKOBJDUMP: fcueq.d $w29, $w3, $w7 -# CHECKOBJDUMP: fcule.w $w17, $w5, $w3 -# CHECKOBJDUMP: fcule.d $w31, $w1, $w30 -# CHECKOBJDUMP: fcult.w $w6, $w25, $w9 -# CHECKOBJDUMP: fcult.d $w27, $w8, $w17 -# CHECKOBJDUMP: fcun.w $w4, $w20, $w8 -# CHECKOBJDUMP: fcun.d $w29, $w11, $w3 -# CHECKOBJDUMP: fcune.w $w13, $w18, $w19 -# CHECKOBJDUMP: fcune.d $w16, $w26, $w21 -# CHECKOBJDUMP: fdiv.w $w13, $w24, $w2 -# CHECKOBJDUMP: fdiv.d $w19, $w4, $w25 -# CHECKOBJDUMP: fexdo.h $w8, $w0, $w16 -# CHECKOBJDUMP: fexdo.w $w0, $w13, $w27 -# CHECKOBJDUMP: fexp2.w $w17, $w0, $w3 -# CHECKOBJDUMP: fexp2.d $w22, $w0, $w10 -# CHECKOBJDUMP: fmadd.w $w29, $w6, $w23 -# CHECKOBJDUMP: fmadd.d $w11, $w28, $w21 -# CHECKOBJDUMP: fmax.w $w0, $w23, $w13 -# CHECKOBJDUMP: fmax.d $w26, $w18, $w8 -# CHECKOBJDUMP: fmax_a.w $w10, $w16, $w10 -# CHECKOBJDUMP: fmax_a.d $w30, $w9, $w22 -# CHECKOBJDUMP: fmin.w $w24, $w1, $w30 -# CHECKOBJDUMP: fmin.d $w27, $w27, $w10 -# CHECKOBJDUMP: fmin_a.w $w10, $w29, $w20 -# CHECKOBJDUMP: fmin_a.d $w13, $w30, $w24 -# CHECKOBJDUMP: fmsub.w $w17, $w25, $w0 -# CHECKOBJDUMP: fmsub.d $w8, $w18, $w16 -# CHECKOBJDUMP: fmul.w $w3, $w15, $w15 -# CHECKOBJDUMP: fmul.d $w9, $w30, $w10 -# CHECKOBJDUMP: fsaf.w $w25, $w5, $w10 -# CHECKOBJDUMP: fsaf.d $w25, $w3, $w29 -# CHECKOBJDUMP: fseq.w $w11, $w17, $w13 -# CHECKOBJDUMP: fseq.d $w29, $w0, $w31 -# CHECKOBJDUMP: fsle.w $w30, $w31, $w31 -# CHECKOBJDUMP: fsle.d $w18, $w23, $w24 -# CHECKOBJDUMP: fslt.w $w12, $w5, $w6 -# CHECKOBJDUMP: fslt.d $w16, $w26, $w21 -# CHECKOBJDUMP: fsne.w $w30, $w1, $w12 -# CHECKOBJDUMP: fsne.d $w14, $w13, $w23 -# CHECKOBJDUMP: fsor.w $w27, $w13, $w27 -# CHECKOBJDUMP: fsor.d $w12, $w24, $w11 -# CHECKOBJDUMP: fsub.w $w31, $w26, $w1 -# CHECKOBJDUMP: fsub.d $w19, $w17, $w27 -# CHECKOBJDUMP: fsueq.w $w16, $w24, $w25 -# CHECKOBJDUMP: fsueq.d $w18, $w14, $w14 -# CHECKOBJDUMP: fsule.w $w23, $w30, $w13 -# CHECKOBJDUMP: fsule.d $w2, $w11, $w26 -# CHECKOBJDUMP: fsult.w $w11, $w26, $w22 -# CHECKOBJDUMP: fsult.d $w6, $w23, $w30 -# CHECKOBJDUMP: fsun.w $w3, $w18, $w28 -# CHECKOBJDUMP: fsun.d $w18, $w11, $w19 -# CHECKOBJDUMP: fsune.w $w16, $w31, $w2 -# CHECKOBJDUMP: fsune.d $w3, $w26, $w17 -# CHECKOBJDUMP: ftq.h $w16, $w4, $w24 -# CHECKOBJDUMP: ftq.w $w5, $w5, $w25 -# CHECKOBJDUMP: madd_q.h $w16, $w20, $w10 -# CHECKOBJDUMP: madd_q.w $w28, $w2, $w9 -# CHECKOBJDUMP: maddr_q.h $w8, $w18, $w9 -# CHECKOBJDUMP: maddr_q.w $w29, $w12, $w16 -# CHECKOBJDUMP: msub_q.h $w24, $w26, $w10 -# CHECKOBJDUMP: msub_q.w $w13, $w30, $w28 -# CHECKOBJDUMP: msubr_q.h $w12, $w21, $w11 -# CHECKOBJDUMP: msubr_q.w $w1, $w14, $w20 -# CHECKOBJDUMP: mul_q.h $w6, $w16, $w30 -# CHECKOBJDUMP: mul_q.w $w16, $w1, $w4 -# CHECKOBJDUMP: mulr_q.h $w6, $w20, $w19 -# CHECKOBJDUMP: mulr_q.w $w27, $w1, $w20 - fadd.w $w28, $w19, $w28 fadd.d $w13, $w2, $w29 fcaf.w $w14, $w11, $w25 diff --git a/test/MC/Mips/msa/test_bit.s b/test/MC/Mips/msa/test_bit.s index 2e5a6a5..85ebe54 100644 --- a/test/MC/Mips/msa/test_bit.s +++ b/test/MC/Mips/msa/test_bit.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: bclri.b $w21, $w30, 2 # encoding: [0x79,0xf2,0xf5,0x49] # CHECK: bclri.h $w24, $w21, 0 # encoding: [0x79,0xe0,0xae,0x09] # CHECK: bclri.w $w23, $w30, 3 # encoding: [0x79,0xc3,0xf5,0xc9] @@ -53,55 +49,6 @@ # CHECK: srlri.w $w11, $w22, 2 # encoding: [0x79,0xc2,0xb2,0xca] # CHECK: srlri.d $w24, $w10, 6 # encoding: [0x79,0x86,0x56,0x0a] -# CHECKOBJDUMP: bclri.b $w21, $w30, 2 -# CHECKOBJDUMP: bclri.h $w24, $w21, 0 -# CHECKOBJDUMP: bclri.w $w23, $w30, 3 -# CHECKOBJDUMP: bclri.d $w9, $w11, 0 -# CHECKOBJDUMP: binsli.b $w25, $w12, 1 -# CHECKOBJDUMP: binsli.h $w21, $w22, 0 -# CHECKOBJDUMP: binsli.w $w22, $w4, 0 -# CHECKOBJDUMP: binsli.d $w6, $w2, 6 -# CHECKOBJDUMP: binsri.b $w15, $w19, 0 -# CHECKOBJDUMP: binsri.h $w8, $w30, 1 -# CHECKOBJDUMP: binsri.w $w2, $w19, 5 -# CHECKOBJDUMP: binsri.d $w18, $w20, 1 -# CHECKOBJDUMP: bnegi.b $w24, $w19, 0 -# CHECKOBJDUMP: bnegi.h $w28, $w11, 3 -# CHECKOBJDUMP: bnegi.w $w1, $w27, 5 -# CHECKOBJDUMP: bnegi.d $w4, $w21, 1 -# CHECKOBJDUMP: bseti.b $w18, $w8, 0 -# CHECKOBJDUMP: bseti.h $w24, $w14, 2 -# CHECKOBJDUMP: bseti.w $w9, $w18, 4 -# CHECKOBJDUMP: bseti.d $w7, $w15, 1 -# CHECKOBJDUMP: sat_s.b $w31, $w31, 2 -# CHECKOBJDUMP: sat_s.h $w19, $w19, 0 -# CHECKOBJDUMP: sat_s.w $w19, $w29, 0 -# CHECKOBJDUMP: sat_s.d $w11, $w22, 0 -# CHECKOBJDUMP: sat_u.b $w1, $w13, 3 -# CHECKOBJDUMP: sat_u.h $w30, $w24, 4 -# CHECKOBJDUMP: sat_u.w $w31, $w13, 0 -# CHECKOBJDUMP: sat_u.d $w29, $w16, 5 -# CHECKOBJDUMP: slli.b $w23, $w10, 1 -# CHECKOBJDUMP: slli.h $w9, $w18, 1 -# CHECKOBJDUMP: slli.w $w11, $w29, 4 -# CHECKOBJDUMP: slli.d $w25, $w20, 1 -# CHECKOBJDUMP: srai.b $w24, $w29, 1 -# CHECKOBJDUMP: srai.h $w1, $w6, 0 -# CHECKOBJDUMP: srai.w $w7, $w26, 1 -# CHECKOBJDUMP: srai.d $w20, $w25, 3 -# CHECKOBJDUMP: srari.b $w5, $w25, 0 -# CHECKOBJDUMP: srari.h $w7, $w6, 4 -# CHECKOBJDUMP: srari.w $w17, $w11, 5 -# CHECKOBJDUMP: srari.d $w21, $w25, 5 -# CHECKOBJDUMP: srli.b $w2, $w0, 2 -# CHECKOBJDUMP: srli.h $w31, $w31, 2 -# CHECKOBJDUMP: srli.w $w5, $w9, 4 -# CHECKOBJDUMP: srli.d $w27, $w26, 5 -# CHECKOBJDUMP: srlri.b $w18, $w3, 0 -# CHECKOBJDUMP: srlri.h $w1, $w2, 3 -# CHECKOBJDUMP: srlri.w $w11, $w22, 2 -# CHECKOBJDUMP: srlri.d $w24, $w10, 6 - bclri.b $w21, $w30, 2 bclri.h $w24, $w21, 0 bclri.w $w23, $w30, 3 diff --git a/test/MC/Mips/msa/test_cbranch.s b/test/MC/Mips/msa/test_cbranch.s index 37b8872..aa6779b 100644 --- a/test/MC/Mips/msa/test_cbranch.s +++ b/test/MC/Mips/msa/test_cbranch.s @@ -7,22 +7,22 @@ #CHECK: bnz.w $w2, 128 # encoding: [0x47,0xc2,0x00,0x20] #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] #CHECK: bnz.d $w3, -128 # encoding: [0x47,0xe3,0xff,0xe0] -#CHECK: bnz.b $w0, SYMBOL0 # encoding: [0x47'A',0x80'A',0x00,0x00] +#CHECK: bnz.b $w0, SYMBOL0 # encoding: [0x47,0x80,A,A] # fixup A - offset: 0, value: SYMBOL0, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bnz.h $w1, SYMBOL1 # encoding: [0x47'A',0xa1'A',0x00,0x00] +#CHECK: bnz.h $w1, SYMBOL1 # encoding: [0x47,0xa1,A,A] # fixup A - offset: 0, value: SYMBOL1, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bnz.w $w2, SYMBOL2 # encoding: [0x47'A',0xc2'A',0x00,0x00] +#CHECK: bnz.w $w2, SYMBOL2 # encoding: [0x47,0xc2,A,A] # fixup A - offset: 0, value: SYMBOL2, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bnz.d $w3, SYMBOL3 # encoding: [0x47'A',0xe3'A',0x00,0x00] +#CHECK: bnz.d $w3, SYMBOL3 # encoding: [0x47,0xe3,A,A] # fixup A - offset: 0, value: SYMBOL3, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] #CHECK: bnz.v $w0, 4 # encoding: [0x45,0xe0,0x00,0x01] #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bnz.v $w0, SYMBOL0 # encoding: [0x45'A',0xe0'A',0x00,0x00] +#CHECK: bnz.v $w0, SYMBOL0 # encoding: [0x45,0xe0,A,A] # fixup A - offset: 0, value: SYMBOL0, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] @@ -34,22 +34,22 @@ #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] #CHECK: bz.d $w3, -1024 # encoding: [0x47,0x63,0xff,0x00] #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bz.b $w0, SYMBOL0 # encoding: [0x47'A',A,0x00,0x00] +#CHECK: bz.b $w0, SYMBOL0 # encoding: [0x47,0x00,A,A] # fixup A - offset: 0, value: SYMBOL0, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bz.h $w1, SYMBOL1 # encoding: [0x47'A',0x21'A',0x00,0x00] +#CHECK: bz.h $w1, SYMBOL1 # encoding: [0x47,0x21,A,A] # fixup A - offset: 0, value: SYMBOL1, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bz.w $w2, SYMBOL2 # encoding: [0x47'A',0x42'A',0x00,0x00] +#CHECK: bz.w $w2, SYMBOL2 # encoding: [0x47,0x42,A,A] # fixup A - offset: 0, value: SYMBOL2, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bz.d $w3, SYMBOL3 # encoding: [0x47'A',0x63'A',0x00,0x00] +#CHECK: bz.d $w3, SYMBOL3 # encoding: [0x47,0x63,A,A] # fixup A - offset: 0, value: SYMBOL3, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] #CHECK: bz.v $w0, 4 # encoding: [0x45,0x60,0x00,0x01] #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bz.v $w0, SYMBOL0 # encoding: [0x45'A',0x60'A',0x00,0x00] +#CHECK: bz.v $w0, SYMBOL0 # encoding: [0x45,0x60,A,A] # fixup A - offset: 0, value: SYMBOL0, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] diff --git a/test/MC/Mips/msa/test_ctrlregs.s b/test/MC/Mips/msa/test_ctrlregs.s index a014c03..3329072b 100644 --- a/test/MC/Mips/msa/test_ctrlregs.s +++ b/test/MC/Mips/msa/test_ctrlregs.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# #CHECK: cfcmsa $1, $0 # encoding: [0x78,0x7e,0x00,0x59] #CHECK: cfcmsa $1, $0 # encoding: [0x78,0x7e,0x00,0x59] #CHECK: cfcmsa $2, $1 # encoding: [0x78,0x7e,0x08,0x99] @@ -38,40 +34,6 @@ #CHECK: ctcmsa $7, $8 # encoding: [0x78,0x3e,0x41,0xd9] #CHECK: ctcmsa $7, $8 # encoding: [0x78,0x3e,0x41,0xd9] -#CHECKOBJDUMP: cfcmsa $1, $0 -#CHECKOBJDUMP: cfcmsa $1, $0 -#CHECKOBJDUMP: cfcmsa $2, $1 -#CHECKOBJDUMP: cfcmsa $2, $1 -#CHECKOBJDUMP: cfcmsa $3, $2 -#CHECKOBJDUMP: cfcmsa $3, $2 -#CHECKOBJDUMP: cfcmsa $4, $3 -#CHECKOBJDUMP: cfcmsa $4, $3 -#CHECKOBJDUMP: cfcmsa $5, $4 -#CHECKOBJDUMP: cfcmsa $5, $4 -#CHECKOBJDUMP: cfcmsa $6, $5 -#CHECKOBJDUMP: cfcmsa $6, $5 -#CHECKOBJDUMP: cfcmsa $7, $6 -#CHECKOBJDUMP: cfcmsa $7, $6 -#CHECKOBJDUMP: cfcmsa $8, $7 -#CHECKOBJDUMP: cfcmsa $8, $7 - -#CHECKOBJDUMP: ctcmsa $0, $1 -#CHECKOBJDUMP: ctcmsa $0, $1 -#CHECKOBJDUMP: ctcmsa $1, $2 -#CHECKOBJDUMP: ctcmsa $1, $2 -#CHECKOBJDUMP: ctcmsa $2, $3 -#CHECKOBJDUMP: ctcmsa $2, $3 -#CHECKOBJDUMP: ctcmsa $3, $4 -#CHECKOBJDUMP: ctcmsa $3, $4 -#CHECKOBJDUMP: ctcmsa $4, $5 -#CHECKOBJDUMP: ctcmsa $4, $5 -#CHECKOBJDUMP: ctcmsa $5, $6 -#CHECKOBJDUMP: ctcmsa $5, $6 -#CHECKOBJDUMP: ctcmsa $6, $7 -#CHECKOBJDUMP: ctcmsa $6, $7 -#CHECKOBJDUMP: ctcmsa $7, $8 -#CHECKOBJDUMP: ctcmsa $7, $8 - cfcmsa $1, $msair cfcmsa $1, $0 cfcmsa $2, $msacsr diff --git a/test/MC/Mips/msa/test_dlsa.s b/test/MC/Mips/msa/test_dlsa.s index a70999d..5e14571 100644 --- a/test/MC/Mips/msa/test_dlsa.s +++ b/test/MC/Mips/msa/test_dlsa.s @@ -1,20 +1,11 @@ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | \ # RUN: FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips64r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips64 -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: dlsa $8, $9, $10, 1 # encoding: [0x01,0x2a,0x40,0x15] # CHECK: dlsa $8, $9, $10, 2 # encoding: [0x01,0x2a,0x40,0x55] # CHECK: dlsa $8, $9, $10, 3 # encoding: [0x01,0x2a,0x40,0x95] # CHECK: dlsa $8, $9, $10, 4 # encoding: [0x01,0x2a,0x40,0xd5] -# CHECKOBJDUMP: dlsa $8, $9, $10, 1 -# CHECKOBJDUMP: dlsa $8, $9, $10, 2 -# CHECKOBJDUMP: dlsa $8, $9, $10, 3 -# CHECKOBJDUMP: dlsa $8, $9, $10, 4 - dlsa $8, $9, $10, 1 dlsa $8, $9, $10, 2 dlsa $8, $9, $10, 3 diff --git a/test/MC/Mips/msa/test_elm.s b/test/MC/Mips/msa/test_elm.s index 1e45fd4..dbe6d5c 100644 --- a/test/MC/Mips/msa/test_elm.s +++ b/test/MC/Mips/msa/test_elm.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: copy_s.b $13, $w8[2] # encoding: [0x78,0x82,0x43,0x59] # CHECK: copy_s.h $1, $w25[0] # encoding: [0x78,0xa0,0xc8,0x59] # CHECK: copy_s.w $22, $w5[1] # encoding: [0x78,0xb1,0x2d,0x99] @@ -20,22 +16,6 @@ # CHECK: splati.d $w28, $w1[0] # encoding: [0x78,0x78,0x0f,0x19] # CHECK: move.v $w23, $w24 # encoding: [0x78,0xbe,0xc5,0xd9] -# CHECKOBJDUMP: copy_s.b $13, $w8[2] -# CHECKOBJDUMP: copy_s.h $1, $w25[0] -# CHECKOBJDUMP: copy_s.w $22, $w5[1] -# CHECKOBJDUMP: copy_u.b $22, $w20[4] -# CHECKOBJDUMP: copy_u.h $20, $w4[0] -# CHECKOBJDUMP: copy_u.w $fp, $w13[2] -# CHECKOBJDUMP: sldi.b $w0, $w29[4] -# CHECKOBJDUMP: sldi.h $w8, $w17[0] -# CHECKOBJDUMP: sldi.w $w20, $w27[2] -# CHECKOBJDUMP: sldi.d $w4, $w12[0] -# CHECKOBJDUMP: splati.b $w25, $w3[2] -# CHECKOBJDUMP: splati.h $w24, $w28[1] -# CHECKOBJDUMP: splati.w $w13, $w18[0] -# CHECKOBJDUMP: splati.d $w28, $w1[0] -# CHECKOBJDUMP: move.v $w23, $w24 - copy_s.b $13, $w8[2] copy_s.h $1, $w25[0] copy_s.w $22, $w5[1] diff --git a/test/MC/Mips/msa/test_elm_insert.s b/test/MC/Mips/msa/test_elm_insert.s index f66b26c..d58a4e0 100644 --- a/test/MC/Mips/msa/test_elm_insert.s +++ b/test/MC/Mips/msa/test_elm_insert.s @@ -1,17 +1,9 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: insert.b $w23[3], $sp # encoding: [0x79,0x03,0xed,0xd9] # CHECK: insert.h $w20[2], $5 # encoding: [0x79,0x22,0x2d,0x19] # CHECK: insert.w $w8[2], $15 # encoding: [0x79,0x32,0x7a,0x19] -# CHECKOBJDUMP: insert.b $w23[3], $sp -# CHECKOBJDUMP: insert.h $w20[2], $5 -# CHECKOBJDUMP: insert.w $w8[2], $15 - insert.b $w23[3], $sp insert.h $w20[2], $5 insert.w $w8[2], $15 diff --git a/test/MC/Mips/msa/test_elm_insert_msa64.s b/test/MC/Mips/msa/test_elm_insert_msa64.s index 8196fd0..4e99bdb 100644 --- a/test/MC/Mips/msa/test_elm_insert_msa64.s +++ b/test/MC/Mips/msa/test_elm_insert_msa64.s @@ -1,11 +1,5 @@ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips64 -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: insert.d $w1[1], $sp # encoding: [0x79,0x39,0xe8,0x59] -# CHECKOBJDUMP: insert.d $w1[1], $sp - insert.d $w1[1], $sp diff --git a/test/MC/Mips/msa/test_elm_insve.s b/test/MC/Mips/msa/test_elm_insve.s index efdf88f..0053322 100644 --- a/test/MC/Mips/msa/test_elm_insve.s +++ b/test/MC/Mips/msa/test_elm_insve.s @@ -1,19 +1,10 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: insve.b $w25[3], $w9[0] # encoding: [0x79,0x43,0x4e,0x59] # CHECK: insve.h $w24[2], $w2[0] # encoding: [0x79,0x62,0x16,0x19] # CHECK: insve.w $w0[2], $w13[0] # encoding: [0x79,0x72,0x68,0x19] # CHECK: insve.d $w3[0], $w18[0] # encoding: [0x79,0x78,0x90,0xd9] -# CHECKOBJDUMP: insve.b $w25[3], $w9[0] -# CHECKOBJDUMP: insve.h $w24[2], $w2[0] -# CHECKOBJDUMP: insve.w $w0[2], $w13[0] -# CHECKOBJDUMP: insve.d $w3[0], $w18[0] - insve.b $w25[3], $w9[0] insve.h $w24[2], $w2[0] insve.w $w0[2], $w13[0] diff --git a/test/MC/Mips/msa/test_elm_msa64.s b/test/MC/Mips/msa/test_elm_msa64.s index 15bfcca..5cc9147 100644 --- a/test/MC/Mips/msa/test_elm_msa64.s +++ b/test/MC/Mips/msa/test_elm_msa64.s @@ -1,14 +1,7 @@ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips64 -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: copy_s.d $19, $w31[0] # encoding: [0x78,0xb8,0xfc,0xd9] # CHECK: copy_u.d $18, $w29[1] # encoding: [0x78,0xf9,0xec,0x99] -# CHECKOBJDUMP: copy_s.d $19, $w31[0] -# CHECKOBJDUMP: copy_u.d $18, $w29[1] - copy_s.d $19, $w31[0] copy_u.d $18, $w29[1] diff --git a/test/MC/Mips/msa/test_i10.s b/test/MC/Mips/msa/test_i10.s index e029dfd..d89218a 100644 --- a/test/MC/Mips/msa/test_i10.s +++ b/test/MC/Mips/msa/test_i10.s @@ -1,20 +1,10 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# - # CHECK: ldi.b $w8, 198 # encoding: [0x7b,0x06,0x32,0x07] # CHECK: ldi.h $w20, 313 # encoding: [0x7b,0x29,0xcd,0x07] # CHECK: ldi.w $w24, 492 # encoding: [0x7b,0x4f,0x66,0x07] # CHECK: ldi.d $w27, -180 # encoding: [0x7b,0x7a,0x66,0xc7] -# CHECKOBJDUMP: ldi.b $w8, 198 -# CHECKOBJDUMP: ldi.h $w20, 313 -# CHECKOBJDUMP: ldi.w $w24, 492 -# CHECKOBJDUMP: ldi.d $w27, 844 - ldi.b $w8, 198 ldi.h $w20, 313 ldi.w $w24, 492 diff --git a/test/MC/Mips/msa/test_i5.s b/test/MC/Mips/msa/test_i5.s index 56c4811..d923787 100644 --- a/test/MC/Mips/msa/test_i5.s +++ b/test/MC/Mips/msa/test_i5.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: addvi.b $w3, $w31, 30 # encoding: [0x78,0x1e,0xf8,0xc6] # CHECK: addvi.h $w24, $w13, 26 # encoding: [0x78,0x3a,0x6e,0x06] # CHECK: addvi.w $w26, $w20, 26 # encoding: [0x78,0x5a,0xa6,0x86] @@ -49,51 +45,6 @@ # CHECK: subvi.w $w12, $w10, 11 # encoding: [0x78,0xcb,0x53,0x06] # CHECK: subvi.d $w19, $w16, 7 # encoding: [0x78,0xe7,0x84,0xc6] -# CHECKOBJDUMP: addvi.b $w3, $w31, 30 -# CHECKOBJDUMP: addvi.h $w24, $w13, 26 -# CHECKOBJDUMP: addvi.w $w26, $w20, 26 -# CHECKOBJDUMP: addvi.d $w16, $w1, 21 -# CHECKOBJDUMP: ceqi.b $w24, $w21, 24 -# CHECKOBJDUMP: ceqi.h $w31, $w15, 2 -# CHECKOBJDUMP: ceqi.w $w12, $w1, 31 -# CHECKOBJDUMP: ceqi.d $w24, $w22, 7 -# CHECKOBJDUMP: clei_s.b $w12, $w16, 1 -# CHECKOBJDUMP: clei_s.h $w2, $w10, 23 -# CHECKOBJDUMP: clei_s.w $w4, $w11, 22 -# CHECKOBJDUMP: clei_s.d $w0, $w29, 22 -# CHECKOBJDUMP: clei_u.b $w21, $w17, 3 -# CHECKOBJDUMP: clei_u.h $w29, $w7, 17 -# CHECKOBJDUMP: clei_u.w $w1, $w1, 2 -# CHECKOBJDUMP: clei_u.d $w27, $w27, 29 -# CHECKOBJDUMP: clti_s.b $w19, $w13, 25 -# CHECKOBJDUMP: clti_s.h $w15, $w10, 20 -# CHECKOBJDUMP: clti_s.w $w12, $w12, 11 -# CHECKOBJDUMP: clti_s.d $w29, $w20, 17 -# CHECKOBJDUMP: clti_u.b $w14, $w9, 29 -# CHECKOBJDUMP: clti_u.h $w24, $w25, 25 -# CHECKOBJDUMP: clti_u.w $w1, $w1, 22 -# CHECKOBJDUMP: clti_u.d $w21, $w25, 1 -# CHECKOBJDUMP: maxi_s.b $w22, $w21, 1 -# CHECKOBJDUMP: maxi_s.h $w29, $w5, 24 -# CHECKOBJDUMP: maxi_s.w $w1, $w10, 20 -# CHECKOBJDUMP: maxi_s.d $w13, $w29, 16 -# CHECKOBJDUMP: maxi_u.b $w20, $w0, 12 -# CHECKOBJDUMP: maxi_u.h $w1, $w14, 3 -# CHECKOBJDUMP: maxi_u.w $w27, $w22, 11 -# CHECKOBJDUMP: maxi_u.d $w26, $w6, 4 -# CHECKOBJDUMP: mini_s.b $w4, $w1, 1 -# CHECKOBJDUMP: mini_s.h $w27, $w27, 23 -# CHECKOBJDUMP: mini_s.w $w28, $w11, 9 -# CHECKOBJDUMP: mini_s.d $w11, $w10, 10 -# CHECKOBJDUMP: mini_u.b $w18, $w23, 27 -# CHECKOBJDUMP: mini_u.h $w7, $w26, 18 -# CHECKOBJDUMP: mini_u.w $w11, $w12, 26 -# CHECKOBJDUMP: mini_u.d $w11, $w15, 2 -# CHECKOBJDUMP: subvi.b $w24, $w20, 19 -# CHECKOBJDUMP: subvi.h $w11, $w19, 4 -# CHECKOBJDUMP: subvi.w $w12, $w10, 11 -# CHECKOBJDUMP: subvi.d $w19, $w16, 7 - addvi.b $w3, $w31, 30 addvi.h $w24, $w13, 26 addvi.w $w26, $w20, 26 diff --git a/test/MC/Mips/msa/test_i8.s b/test/MC/Mips/msa/test_i8.s index d4138a1..b520bb4 100644 --- a/test/MC/Mips/msa/test_i8.s +++ b/test/MC/Mips/msa/test_i8.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: andi.b $w2, $w29, 48 # encoding: [0x78,0x30,0xe8,0x80] # CHECK: bmnzi.b $w6, $w22, 126 # encoding: [0x78,0x7e,0xb1,0x81] # CHECK: bmzi.b $w27, $w1, 88 # encoding: [0x79,0x58,0x0e,0xc1] @@ -15,17 +11,6 @@ # CHECK: shf.w $w14, $w3, 93 # encoding: [0x7a,0x5d,0x1b,0x82] # CHECK: xori.b $w16, $w10, 20 # encoding: [0x7b,0x14,0x54,0x00] -# CHECKOBJDUMP: andi.b $w2, $w29, 48 -# CHECKOBJDUMP: bmnzi.b $w6, $w22, 126 -# CHECKOBJDUMP: bmzi.b $w27, $w1, 88 -# CHECKOBJDUMP: bseli.b $w29, $w3, 189 -# CHECKOBJDUMP: nori.b $w1, $w17, 56 -# CHECKOBJDUMP: ori.b $w26, $w20, 135 -# CHECKOBJDUMP: shf.b $w19, $w30, 105 -# CHECKOBJDUMP: shf.h $w17, $w8, 76 -# CHECKOBJDUMP: shf.w $w14, $w3, 93 -# CHECKOBJDUMP: xori.b $w16, $w10, 20 - andi.b $w2, $w29, 48 bmnzi.b $w6, $w22, 126 bmzi.b $w27, $w1, 88 diff --git a/test/MC/Mips/msa/test_lsa.s b/test/MC/Mips/msa/test_lsa.s index 9ea76f6..22fd0b3 100644 --- a/test/MC/Mips/msa/test_lsa.s +++ b/test/MC/Mips/msa/test_lsa.s @@ -1,19 +1,10 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: lsa $8, $9, $10, 1 # encoding: [0x01,0x2a,0x40,0x05] # CHECK: lsa $8, $9, $10, 2 # encoding: [0x01,0x2a,0x40,0x45] # CHECK: lsa $8, $9, $10, 3 # encoding: [0x01,0x2a,0x40,0x85] # CHECK: lsa $8, $9, $10, 4 # encoding: [0x01,0x2a,0x40,0xc5] -# CHECKOBJDUMP: lsa $8, $9, $10, 1 -# CHECKOBJDUMP: lsa $8, $9, $10, 2 -# CHECKOBJDUMP: lsa $8, $9, $10, 3 -# CHECKOBJDUMP: lsa $8, $9, $10, 4 - lsa $8, $9, $10, 1 lsa $8, $9, $10, 2 lsa $8, $9, $10, 3 diff --git a/test/MC/Mips/msa/test_mi10.s b/test/MC/Mips/msa/test_mi10.s index 90baeba..7269960 100644 --- a/test/MC/Mips/msa/test_mi10.s +++ b/test/MC/Mips/msa/test_mi10.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: ld.b $w0, -512($1) # encoding: [0x7a,0x00,0x08,0x20] # CHECK: ld.b $w1, 0($2) # encoding: [0x78,0x00,0x10,0x60] # CHECK: ld.b $w2, 511($3) # encoding: [0x79,0xff,0x18,0xa0] @@ -31,33 +27,6 @@ # CHECK: ld.d $w21, 2048($22) # encoding: [0x79,0x00,0xb5,0x63] # CHECK: ld.d $w22, 4088($23) # encoding: [0x79,0xff,0xbd,0xa3] -# CHECKOBJDUMP: ld.b $w0, -512($1) -# CHECKOBJDUMP: ld.b $w1, 0($2) -# CHECKOBJDUMP: ld.b $w2, 511($3) - -# CHECKOBJDUMP: ld.h $w3, -1024($4) -# CHECKOBJDUMP: ld.h $w4, -512($5) -# CHECKOBJDUMP: ld.h $w5, 0($6) -# CHECKOBJDUMP: ld.h $w6, 512($7) -# CHECKOBJDUMP: ld.h $w7, 1022($8) - -# CHECKOBJDUMP: ld.w $w8, -2048($9) -# CHECKOBJDUMP: ld.w $w9, -1024($10) -# CHECKOBJDUMP: ld.w $w10, -512($11) -# CHECKOBJDUMP: ld.w $w11, 512($12) -# CHECKOBJDUMP: ld.w $w12, 1024($13) -# CHECKOBJDUMP: ld.w $w13, 2044($14) - -# CHECKOBJDUMP: ld.d $w14, -4096($15) -# CHECKOBJDUMP: ld.d $w15, -2048($16) -# CHECKOBJDUMP: ld.d $w16, -1024($17) -# CHECKOBJDUMP: ld.d $w17, -512($18) -# CHECKOBJDUMP: ld.d $w18, 0($19) -# CHECKOBJDUMP: ld.d $w19, 512($20) -# CHECKOBJDUMP: ld.d $w20, 1024($21) -# CHECKOBJDUMP: ld.d $w21, 2048($22) -# CHECKOBJDUMP: ld.d $w22, 4088($23) - ld.b $w0, -512($1) ld.b $w1, 0($2) ld.b $w2, 511($3) diff --git a/test/MC/Mips/msa/test_vec.s b/test/MC/Mips/msa/test_vec.s index b62da70..3f989d3 100644 --- a/test/MC/Mips/msa/test_vec.s +++ b/test/MC/Mips/msa/test_vec.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: and.v $w25, $w20, $w27 # encoding: [0x78,0x1b,0xa6,0x5e] # CHECK: bmnz.v $w17, $w6, $w7 # encoding: [0x78,0x87,0x34,0x5e] # CHECK: bmz.v $w3, $w17, $w9 # encoding: [0x78,0xa9,0x88,0xde] @@ -12,14 +8,6 @@ # CHECK: or.v $w24, $w26, $w30 # encoding: [0x78,0x3e,0xd6,0x1e] # CHECK: xor.v $w7, $w27, $w15 # encoding: [0x78,0x6f,0xd9,0xde] -# CHECKOBJDUMP: and.v $w25, $w20, $w27 -# CHECKOBJDUMP: bmnz.v $w17, $w6, $w7 -# CHECKOBJDUMP: bmz.v $w3, $w17, $w9 -# CHECKOBJDUMP: bsel.v $w8, $w0, $w14 -# CHECKOBJDUMP: nor.v $w7, $w31, $w0 -# CHECKOBJDUMP: or.v $w24, $w26, $w30 -# CHECKOBJDUMP: xor.v $w7, $w27, $w15 - and.v $w25, $w20, $w27 bmnz.v $w17, $w6, $w7 bmz.v $w3, $w17, $w9 diff --git a/test/MC/Mips/octeon-instructions.s b/test/MC/Mips/octeon-instructions.s index 0244e19..b7c89b4 100644 --- a/test/MC/Mips/octeon-instructions.s +++ b/test/MC/Mips/octeon-instructions.s @@ -29,8 +29,18 @@ # CHECK: pop $2, $2 # encoding: [0x70,0x40,0x10,0x2c] # CHECK: seq $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2a] # CHECK: seq $6, $6, $24 # encoding: [0x70,0xd8,0x30,0x2a] +# CHECK: seqi $17, $15, -512 # encoding: [0x71,0xf1,0x80,0x2e] +# CHECK: seqi $16, $16, 38 # encoding: [0x72,0x10,0x09,0xae] # CHECK: sne $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2b] # CHECK: sne $23, $23, $20 # encoding: [0x72,0xf4,0xb8,0x2b] +# CHECK: snei $4, $16, -313 # encoding: [0x72,0x04,0xb1,0xef] +# CHECK: snei $26, $26, 511 # encoding: [0x73,0x5a,0x7f,0xef] +# CHECK: v3mulu $21, $10, $21 # encoding: [0x71,0x55,0xa8,0x11] +# CHECK: v3mulu $20, $20, $10 # encoding: [0x72,0x8a,0xa0,0x11] +# CHECK: vmm0 $3, $19, $16 # encoding: [0x72,0x70,0x18,0x10] +# CHECK: vmm0 $ra, $ra, $9 # encoding: [0x73,0xe9,0xf8,0x10] +# CHECK: vmulu $sp, $10, $17 # encoding: [0x71,0x51,0xe8,0x0f] +# CHECK: vmulu $27, $27, $6 # encoding: [0x73,0x66,0xd8,0x0f] baddu $9, $6, $7 baddu $17, $18, $19 @@ -61,5 +71,15 @@ pop $2 seq $25, $23, $24 seq $6, $24 + seqi $17, $15, -512 + seqi $16, 38 sne $25, $23, $24 sne $23, $20 + snei $4, $16, -313 + snei $26, 511 + v3mulu $21, $10, $21 + v3mulu $20, $10 + vmm0 $3, $19, $16 + vmm0 $31, $9 + vmulu $29, $10, $17 + vmulu $27, $6 diff --git a/test/MC/PowerPC/ppc64-initial-cfa.s b/test/MC/PowerPC/ppc64-initial-cfa.s index b890b30..ca97e1b 100644 --- a/test/MC/PowerPC/ppc64-initial-cfa.s +++ b/test/MC/PowerPC/ppc64-initial-cfa.s @@ -7,6 +7,7 @@ # RUN: llvm-mc -triple=powerpc64le-unknown-linux-gnu -filetype=obj -relocation-model=pic %s | \ # RUN: llvm-readobj -s -sr -sd | FileCheck %s -check-prefix=PIC -check-prefix=PIC-LE +_proc: .cfi_startproc nop .cfi_endproc diff --git a/test/MC/Sparc/sparc-alu-instructions.s b/test/MC/Sparc/sparc-alu-instructions.s index afebf64..e2e5ef8 100644 --- a/test/MC/Sparc/sparc-alu-instructions.s +++ b/test/MC/Sparc/sparc-alu-instructions.s @@ -70,10 +70,10 @@ ! CHECK: subxcc %g1, %g2, %g3 ! encoding: [0x86,0xe0,0x40,0x02] subxcc %g1, %g2, %g3 - ! CHECK: or %g0, %g1, %g3 ! encoding: [0x86,0x10,0x00,0x01] + ! CHECK: mov %g1, %g3 ! encoding: [0x86,0x10,0x00,0x01] mov %g1, %g3 - ! CHECK: or %g0, 255, %g3 ! encoding: [0x86,0x10,0x20,0xff] + ! CHECK: mov 255, %g3 ! encoding: [0x86,0x10,0x20,0xff] mov 0xff, %g3 ! CHECK: restore ! encoding: [0x81,0xe8,0x00,0x00] diff --git a/test/MC/Sparc/sparc-fp-instructions.s b/test/MC/Sparc/sparc-fp-instructions.s index fdeaa8c..f8c130f 100644 --- a/test/MC/Sparc/sparc-fp-instructions.s +++ b/test/MC/Sparc/sparc-fp-instructions.s @@ -96,16 +96,16 @@ fdivd %f0, %f4, %f8 fdivq %f0, %f4, %f8 - ! CHECK: fcmps %fcc0, %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x24] - ! CHECK: fcmpd %fcc0, %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x44] - ! CHECK: fcmpq %fcc0, %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x64] + ! CHECK: fcmps %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x24] + ! CHECK: fcmpd %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x44] + ! CHECK: fcmpq %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0x64] fcmps %f0, %f4 fcmpd %f0, %f4 fcmpq %f0, %f4 - ! CHECK: fcmpes %fcc0, %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xa4] - ! CHECK: fcmped %fcc0, %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xc4] - ! CHECK: fcmpeq %fcc0, %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xe4] + ! CHECK: fcmpes %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xa4] + ! CHECK: fcmped %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xc4] + ! CHECK: fcmpeq %f0, %f4 ! encoding: [0x81,0xa8,0x0a,0xe4] fcmpes %f0, %f4 fcmped %f0, %f4 fcmpeq %f0, %f4 diff --git a/test/MC/X86/avx512-encodings.s b/test/MC/X86/avx512-encodings.s index 42c50e1..2915b7a 100644 --- a/test/MC/X86/avx512-encodings.s +++ b/test/MC/X86/avx512-encodings.s @@ -1,101 +1,5 @@ // RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=knl --show-encoding %s | FileCheck %s -// CHECK: vaddpd -8192(%rdx), %zmm27, %zmm8 -// CHECK: encoding: [0x62,0x71,0xa5,0x40,0x58,0x42,0x80] - vaddpd -8192(%rdx), %zmm27, %zmm8 - -// CHECK: vaddpd -1024(%rdx){1to8}, %zmm27, %zmm8 -// CHECK: encoding: [0x62,0x71,0xa5,0x50,0x58,0x42,0x80] - vaddpd -1024(%rdx){1to8}, %zmm27, %zmm8 - -// CHECK: vaddps -8192(%rdx), %zmm13, %zmm18 -// CHECK: encoding: [0x62,0xe1,0x14,0x48,0x58,0x52,0x80] - vaddps -8192(%rdx), %zmm13, %zmm18 - -// CHECK: vaddps -512(%rdx){1to16}, %zmm13, %zmm18 -// CHECK: encoding: [0x62,0xe1,0x14,0x58,0x58,0x52,0x80] - vaddps -512(%rdx){1to16}, %zmm13, %zmm18 - -// CHECK: vdivpd -8192(%rdx), %zmm6, %zmm18 -// CHECK: encoding: [0x62,0xe1,0xcd,0x48,0x5e,0x52,0x80] - vdivpd -8192(%rdx), %zmm6, %zmm18 - -// CHECK: vdivpd -1024(%rdx){1to8}, %zmm6, %zmm18 -// CHECK: encoding: [0x62,0xe1,0xcd,0x58,0x5e,0x52,0x80] - vdivpd -1024(%rdx){1to8}, %zmm6, %zmm18 - -// CHECK: vdivps -8192(%rdx), %zmm23, %zmm23 -// CHECK: encoding: [0x62,0xe1,0x44,0x40,0x5e,0x7a,0x80] - vdivps -8192(%rdx), %zmm23, %zmm23 - -// CHECK: vdivps -512(%rdx){1to16}, %zmm23, %zmm23 -// CHECK: encoding: [0x62,0xe1,0x44,0x50,0x5e,0x7a,0x80] - vdivps -512(%rdx){1to16}, %zmm23, %zmm23 - -// CHECK: vmaxpd -8192(%rdx), %zmm28, %zmm30 -// CHECK: encoding: [0x62,0x61,0x9d,0x40,0x5f,0x72,0x80] - vmaxpd -8192(%rdx), %zmm28, %zmm30 - -// CHECK: vmaxpd -1024(%rdx){1to8}, %zmm28, %zmm30 -// CHECK: encoding: [0x62,0x61,0x9d,0x50,0x5f,0x72,0x80] - vmaxpd -1024(%rdx){1to8}, %zmm28, %zmm30 - -// CHECK: vmaxps -8192(%rdx), %zmm6, %zmm25 -// CHECK: encoding: [0x62,0x61,0x4c,0x48,0x5f,0x4a,0x80] - vmaxps -8192(%rdx), %zmm6, %zmm25 - -// CHECK: vmaxps -512(%rdx){1to16}, %zmm6, %zmm25 -// CHECK: encoding: [0x62,0x61,0x4c,0x58,0x5f,0x4a,0x80] - vmaxps -512(%rdx){1to16}, %zmm6, %zmm25 - -// CHECK: vminpd -8192(%rdx), %zmm6, %zmm6 -// CHECK: encoding: [0x62,0xf1,0xcd,0x48,0x5d,0x72,0x80] - vminpd -8192(%rdx), %zmm6, %zmm6 - -// CHECK: vminpd -1024(%rdx){1to8}, %zmm6, %zmm6 -// CHECK: encoding: [0x62,0xf1,0xcd,0x58,0x5d,0x72,0x80] - vminpd -1024(%rdx){1to8}, %zmm6, %zmm6 - -// CHECK: vminps -8192(%rdx), %zmm3, %zmm3 -// CHECK: encoding: [0x62,0xf1,0x64,0x48,0x5d,0x5a,0x80] - vminps -8192(%rdx), %zmm3, %zmm3 - -// CHECK: vminps -512(%rdx){1to16}, %zmm3, %zmm3 -// CHECK: encoding: [0x62,0xf1,0x64,0x58,0x5d,0x5a,0x80] - vminps -512(%rdx){1to16}, %zmm3, %zmm3 - -// CHECK: vmulpd -8192(%rdx), %zmm4, %zmm24 -// CHECK: encoding: [0x62,0x61,0xdd,0x48,0x59,0x42,0x80] - vmulpd -8192(%rdx), %zmm4, %zmm24 - -// CHECK: vmulpd -1024(%rdx){1to8}, %zmm4, %zmm24 -// CHECK: encoding: [0x62,0x61,0xdd,0x58,0x59,0x42,0x80] - vmulpd -1024(%rdx){1to8}, %zmm4, %zmm24 - -// CHECK: vmulps -8192(%rdx), %zmm6, %zmm3 -// CHECK: encoding: [0x62,0xf1,0x4c,0x48,0x59,0x5a,0x80] - vmulps -8192(%rdx), %zmm6, %zmm3 - -// CHECK: vmulps -512(%rdx){1to16}, %zmm6, %zmm3 -// CHECK: encoding: [0x62,0xf1,0x4c,0x58,0x59,0x5a,0x80] - vmulps -512(%rdx){1to16}, %zmm6, %zmm3 - -// CHECK: vsubpd -8192(%rdx), %zmm12, %zmm9 -// CHECK: encoding: [0x62,0x71,0x9d,0x48,0x5c,0x4a,0x80] - vsubpd -8192(%rdx), %zmm12, %zmm9 - -// CHECK: vsubpd -1024(%rdx){1to8}, %zmm12, %zmm9 -// CHECK: encoding: [0x62,0x71,0x9d,0x58,0x5c,0x4a,0x80] - vsubpd -1024(%rdx){1to8}, %zmm12, %zmm9 - -// CHECK: vsubps -8192(%rdx), %zmm27, %zmm14 -// CHECK: encoding: [0x62,0x71,0x24,0x40,0x5c,0x72,0x80] - vsubps -8192(%rdx), %zmm27, %zmm14 - -// CHECK: vsubps -512(%rdx){1to16}, %zmm27, %zmm14 -// CHECK: encoding: [0x62,0x71,0x24,0x50,0x5c,0x72,0x80] - vsubps -512(%rdx){1to16}, %zmm27, %zmm14 - // CHECK: vaddpd %zmm6, %zmm27, %zmm8 // CHECK: encoding: [0x62,0x71,0xa5,0x40,0x58,0xc6] vaddpd %zmm6, %zmm27, %zmm8 @@ -128,6 +32,10 @@ // CHECK: encoding: [0x62,0x71,0xa5,0x40,0x58,0x82,0x00,0x20,0x00,0x00] vaddpd 8192(%rdx), %zmm27, %zmm8 +// CHECK: vaddpd -8192(%rdx), %zmm27, %zmm8 +// CHECK: encoding: [0x62,0x71,0xa5,0x40,0x58,0x42,0x80] + vaddpd -8192(%rdx), %zmm27, %zmm8 + // CHECK: vaddpd -8256(%rdx), %zmm27, %zmm8 // CHECK: encoding: [0x62,0x71,0xa5,0x40,0x58,0x82,0xc0,0xdf,0xff,0xff] vaddpd -8256(%rdx), %zmm27, %zmm8 @@ -140,6 +48,10 @@ // CHECK: encoding: [0x62,0x71,0xa5,0x50,0x58,0x82,0x00,0x04,0x00,0x00] vaddpd 1024(%rdx){1to8}, %zmm27, %zmm8 +// CHECK: vaddpd -1024(%rdx){1to8}, %zmm27, %zmm8 +// CHECK: encoding: [0x62,0x71,0xa5,0x50,0x58,0x42,0x80] + vaddpd -1024(%rdx){1to8}, %zmm27, %zmm8 + // CHECK: vaddpd -1032(%rdx){1to8}, %zmm27, %zmm8 // CHECK: encoding: [0x62,0x71,0xa5,0x50,0x58,0x82,0xf8,0xfb,0xff,0xff] vaddpd -1032(%rdx){1to8}, %zmm27, %zmm8 @@ -176,6 +88,10 @@ // CHECK: encoding: [0x62,0xe1,0x14,0x48,0x58,0x92,0x00,0x20,0x00,0x00] vaddps 8192(%rdx), %zmm13, %zmm18 +// CHECK: vaddps -8192(%rdx), %zmm13, %zmm18 +// CHECK: encoding: [0x62,0xe1,0x14,0x48,0x58,0x52,0x80] + vaddps -8192(%rdx), %zmm13, %zmm18 + // CHECK: vaddps -8256(%rdx), %zmm13, %zmm18 // CHECK: encoding: [0x62,0xe1,0x14,0x48,0x58,0x92,0xc0,0xdf,0xff,0xff] vaddps -8256(%rdx), %zmm13, %zmm18 @@ -188,6 +104,10 @@ // CHECK: encoding: [0x62,0xe1,0x14,0x58,0x58,0x92,0x00,0x02,0x00,0x00] vaddps 512(%rdx){1to16}, %zmm13, %zmm18 +// CHECK: vaddps -512(%rdx){1to16}, %zmm13, %zmm18 +// CHECK: encoding: [0x62,0xe1,0x14,0x58,0x58,0x52,0x80] + vaddps -512(%rdx){1to16}, %zmm13, %zmm18 + // CHECK: vaddps -516(%rdx){1to16}, %zmm13, %zmm18 // CHECK: encoding: [0x62,0xe1,0x14,0x58,0x58,0x92,0xfc,0xfd,0xff,0xff] vaddps -516(%rdx){1to16}, %zmm13, %zmm18 @@ -224,6 +144,10 @@ // CHECK: encoding: [0x62,0xe1,0xcd,0x48,0x5e,0x92,0x00,0x20,0x00,0x00] vdivpd 8192(%rdx), %zmm6, %zmm18 +// CHECK: vdivpd -8192(%rdx), %zmm6, %zmm18 +// CHECK: encoding: [0x62,0xe1,0xcd,0x48,0x5e,0x52,0x80] + vdivpd -8192(%rdx), %zmm6, %zmm18 + // CHECK: vdivpd -8256(%rdx), %zmm6, %zmm18 // CHECK: encoding: [0x62,0xe1,0xcd,0x48,0x5e,0x92,0xc0,0xdf,0xff,0xff] vdivpd -8256(%rdx), %zmm6, %zmm18 @@ -236,6 +160,10 @@ // CHECK: encoding: [0x62,0xe1,0xcd,0x58,0x5e,0x92,0x00,0x04,0x00,0x00] vdivpd 1024(%rdx){1to8}, %zmm6, %zmm18 +// CHECK: vdivpd -1024(%rdx){1to8}, %zmm6, %zmm18 +// CHECK: encoding: [0x62,0xe1,0xcd,0x58,0x5e,0x52,0x80] + vdivpd -1024(%rdx){1to8}, %zmm6, %zmm18 + // CHECK: vdivpd -1032(%rdx){1to8}, %zmm6, %zmm18 // CHECK: encoding: [0x62,0xe1,0xcd,0x58,0x5e,0x92,0xf8,0xfb,0xff,0xff] vdivpd -1032(%rdx){1to8}, %zmm6, %zmm18 @@ -272,6 +200,10 @@ // CHECK: encoding: [0x62,0xe1,0x44,0x40,0x5e,0xba,0x00,0x20,0x00,0x00] vdivps 8192(%rdx), %zmm23, %zmm23 +// CHECK: vdivps -8192(%rdx), %zmm23, %zmm23 +// CHECK: encoding: [0x62,0xe1,0x44,0x40,0x5e,0x7a,0x80] + vdivps -8192(%rdx), %zmm23, %zmm23 + // CHECK: vdivps -8256(%rdx), %zmm23, %zmm23 // CHECK: encoding: [0x62,0xe1,0x44,0x40,0x5e,0xba,0xc0,0xdf,0xff,0xff] vdivps -8256(%rdx), %zmm23, %zmm23 @@ -284,6 +216,10 @@ // CHECK: encoding: [0x62,0xe1,0x44,0x50,0x5e,0xba,0x00,0x02,0x00,0x00] vdivps 512(%rdx){1to16}, %zmm23, %zmm23 +// CHECK: vdivps -512(%rdx){1to16}, %zmm23, %zmm23 +// CHECK: encoding: [0x62,0xe1,0x44,0x50,0x5e,0x7a,0x80] + vdivps -512(%rdx){1to16}, %zmm23, %zmm23 + // CHECK: vdivps -516(%rdx){1to16}, %zmm23, %zmm23 // CHECK: encoding: [0x62,0xe1,0x44,0x50,0x5e,0xba,0xfc,0xfd,0xff,0xff] vdivps -516(%rdx){1to16}, %zmm23, %zmm23 @@ -320,6 +256,10 @@ // CHECK: encoding: [0x62,0x61,0x9d,0x40,0x5f,0xb2,0x00,0x20,0x00,0x00] vmaxpd 8192(%rdx), %zmm28, %zmm30 +// CHECK: vmaxpd -8192(%rdx), %zmm28, %zmm30 +// CHECK: encoding: [0x62,0x61,0x9d,0x40,0x5f,0x72,0x80] + vmaxpd -8192(%rdx), %zmm28, %zmm30 + // CHECK: vmaxpd -8256(%rdx), %zmm28, %zmm30 // CHECK: encoding: [0x62,0x61,0x9d,0x40,0x5f,0xb2,0xc0,0xdf,0xff,0xff] vmaxpd -8256(%rdx), %zmm28, %zmm30 @@ -332,6 +272,10 @@ // CHECK: encoding: [0x62,0x61,0x9d,0x50,0x5f,0xb2,0x00,0x04,0x00,0x00] vmaxpd 1024(%rdx){1to8}, %zmm28, %zmm30 +// CHECK: vmaxpd -1024(%rdx){1to8}, %zmm28, %zmm30 +// CHECK: encoding: [0x62,0x61,0x9d,0x50,0x5f,0x72,0x80] + vmaxpd -1024(%rdx){1to8}, %zmm28, %zmm30 + // CHECK: vmaxpd -1032(%rdx){1to8}, %zmm28, %zmm30 // CHECK: encoding: [0x62,0x61,0x9d,0x50,0x5f,0xb2,0xf8,0xfb,0xff,0xff] vmaxpd -1032(%rdx){1to8}, %zmm28, %zmm30 @@ -368,6 +312,10 @@ // CHECK: encoding: [0x62,0x61,0x4c,0x48,0x5f,0x8a,0x00,0x20,0x00,0x00] vmaxps 8192(%rdx), %zmm6, %zmm25 +// CHECK: vmaxps -8192(%rdx), %zmm6, %zmm25 +// CHECK: encoding: [0x62,0x61,0x4c,0x48,0x5f,0x4a,0x80] + vmaxps -8192(%rdx), %zmm6, %zmm25 + // CHECK: vmaxps -8256(%rdx), %zmm6, %zmm25 // CHECK: encoding: [0x62,0x61,0x4c,0x48,0x5f,0x8a,0xc0,0xdf,0xff,0xff] vmaxps -8256(%rdx), %zmm6, %zmm25 @@ -380,6 +328,10 @@ // CHECK: encoding: [0x62,0x61,0x4c,0x58,0x5f,0x8a,0x00,0x02,0x00,0x00] vmaxps 512(%rdx){1to16}, %zmm6, %zmm25 +// CHECK: vmaxps -512(%rdx){1to16}, %zmm6, %zmm25 +// CHECK: encoding: [0x62,0x61,0x4c,0x58,0x5f,0x4a,0x80] + vmaxps -512(%rdx){1to16}, %zmm6, %zmm25 + // CHECK: vmaxps -516(%rdx){1to16}, %zmm6, %zmm25 // CHECK: encoding: [0x62,0x61,0x4c,0x58,0x5f,0x8a,0xfc,0xfd,0xff,0xff] vmaxps -516(%rdx){1to16}, %zmm6, %zmm25 @@ -416,6 +368,10 @@ // CHECK: encoding: [0x62,0xf1,0xcd,0x48,0x5d,0xb2,0x00,0x20,0x00,0x00] vminpd 8192(%rdx), %zmm6, %zmm6 +// CHECK: vminpd -8192(%rdx), %zmm6, %zmm6 +// CHECK: encoding: [0x62,0xf1,0xcd,0x48,0x5d,0x72,0x80] + vminpd -8192(%rdx), %zmm6, %zmm6 + // CHECK: vminpd -8256(%rdx), %zmm6, %zmm6 // CHECK: encoding: [0x62,0xf1,0xcd,0x48,0x5d,0xb2,0xc0,0xdf,0xff,0xff] vminpd -8256(%rdx), %zmm6, %zmm6 @@ -428,6 +384,10 @@ // CHECK: encoding: [0x62,0xf1,0xcd,0x58,0x5d,0xb2,0x00,0x04,0x00,0x00] vminpd 1024(%rdx){1to8}, %zmm6, %zmm6 +// CHECK: vminpd -1024(%rdx){1to8}, %zmm6, %zmm6 +// CHECK: encoding: [0x62,0xf1,0xcd,0x58,0x5d,0x72,0x80] + vminpd -1024(%rdx){1to8}, %zmm6, %zmm6 + // CHECK: vminpd -1032(%rdx){1to8}, %zmm6, %zmm6 // CHECK: encoding: [0x62,0xf1,0xcd,0x58,0x5d,0xb2,0xf8,0xfb,0xff,0xff] vminpd -1032(%rdx){1to8}, %zmm6, %zmm6 @@ -464,6 +424,10 @@ // CHECK: encoding: [0x62,0xf1,0x64,0x48,0x5d,0x9a,0x00,0x20,0x00,0x00] vminps 8192(%rdx), %zmm3, %zmm3 +// CHECK: vminps -8192(%rdx), %zmm3, %zmm3 +// CHECK: encoding: [0x62,0xf1,0x64,0x48,0x5d,0x5a,0x80] + vminps -8192(%rdx), %zmm3, %zmm3 + // CHECK: vminps -8256(%rdx), %zmm3, %zmm3 // CHECK: encoding: [0x62,0xf1,0x64,0x48,0x5d,0x9a,0xc0,0xdf,0xff,0xff] vminps -8256(%rdx), %zmm3, %zmm3 @@ -476,6 +440,10 @@ // CHECK: encoding: [0x62,0xf1,0x64,0x58,0x5d,0x9a,0x00,0x02,0x00,0x00] vminps 512(%rdx){1to16}, %zmm3, %zmm3 +// CHECK: vminps -512(%rdx){1to16}, %zmm3, %zmm3 +// CHECK: encoding: [0x62,0xf1,0x64,0x58,0x5d,0x5a,0x80] + vminps -512(%rdx){1to16}, %zmm3, %zmm3 + // CHECK: vminps -516(%rdx){1to16}, %zmm3, %zmm3 // CHECK: encoding: [0x62,0xf1,0x64,0x58,0x5d,0x9a,0xfc,0xfd,0xff,0xff] vminps -516(%rdx){1to16}, %zmm3, %zmm3 @@ -512,6 +480,10 @@ // CHECK: encoding: [0x62,0x61,0xdd,0x48,0x59,0x82,0x00,0x20,0x00,0x00] vmulpd 8192(%rdx), %zmm4, %zmm24 +// CHECK: vmulpd -8192(%rdx), %zmm4, %zmm24 +// CHECK: encoding: [0x62,0x61,0xdd,0x48,0x59,0x42,0x80] + vmulpd -8192(%rdx), %zmm4, %zmm24 + // CHECK: vmulpd -8256(%rdx), %zmm4, %zmm24 // CHECK: encoding: [0x62,0x61,0xdd,0x48,0x59,0x82,0xc0,0xdf,0xff,0xff] vmulpd -8256(%rdx), %zmm4, %zmm24 @@ -524,6 +496,10 @@ // CHECK: encoding: [0x62,0x61,0xdd,0x58,0x59,0x82,0x00,0x04,0x00,0x00] vmulpd 1024(%rdx){1to8}, %zmm4, %zmm24 +// CHECK: vmulpd -1024(%rdx){1to8}, %zmm4, %zmm24 +// CHECK: encoding: [0x62,0x61,0xdd,0x58,0x59,0x42,0x80] + vmulpd -1024(%rdx){1to8}, %zmm4, %zmm24 + // CHECK: vmulpd -1032(%rdx){1to8}, %zmm4, %zmm24 // CHECK: encoding: [0x62,0x61,0xdd,0x58,0x59,0x82,0xf8,0xfb,0xff,0xff] vmulpd -1032(%rdx){1to8}, %zmm4, %zmm24 @@ -560,6 +536,10 @@ // CHECK: encoding: [0x62,0xf1,0x4c,0x48,0x59,0x9a,0x00,0x20,0x00,0x00] vmulps 8192(%rdx), %zmm6, %zmm3 +// CHECK: vmulps -8192(%rdx), %zmm6, %zmm3 +// CHECK: encoding: [0x62,0xf1,0x4c,0x48,0x59,0x5a,0x80] + vmulps -8192(%rdx), %zmm6, %zmm3 + // CHECK: vmulps -8256(%rdx), %zmm6, %zmm3 // CHECK: encoding: [0x62,0xf1,0x4c,0x48,0x59,0x9a,0xc0,0xdf,0xff,0xff] vmulps -8256(%rdx), %zmm6, %zmm3 @@ -572,6 +552,10 @@ // CHECK: encoding: [0x62,0xf1,0x4c,0x58,0x59,0x9a,0x00,0x02,0x00,0x00] vmulps 512(%rdx){1to16}, %zmm6, %zmm3 +// CHECK: vmulps -512(%rdx){1to16}, %zmm6, %zmm3 +// CHECK: encoding: [0x62,0xf1,0x4c,0x58,0x59,0x5a,0x80] + vmulps -512(%rdx){1to16}, %zmm6, %zmm3 + // CHECK: vmulps -516(%rdx){1to16}, %zmm6, %zmm3 // CHECK: encoding: [0x62,0xf1,0x4c,0x58,0x59,0x9a,0xfc,0xfd,0xff,0xff] vmulps -516(%rdx){1to16}, %zmm6, %zmm3 @@ -1504,6 +1488,374 @@ // CHECK: encoding: [0x62,0x72,0xad,0x50,0x3b,0x9a,0xf8,0xfb,0xff,0xff] vpminuq -1032(%rdx){1to8}, %zmm26, %zmm11 +// CHECK: vpmovsxbd %xmm7, %zmm27 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x21,0xdf] + vpmovsxbd %xmm7, %zmm27 + +// CHECK: vpmovsxbd %xmm7, %zmm27 {%k5} +// CHECK: encoding: [0x62,0x62,0x7d,0x4d,0x21,0xdf] + vpmovsxbd %xmm7, %zmm27 {%k5} + +// CHECK: vpmovsxbd %xmm7, %zmm27 {%k5} {z} +// CHECK: encoding: [0x62,0x62,0x7d,0xcd,0x21,0xdf] + vpmovsxbd %xmm7, %zmm27 {%k5} {z} + +// CHECK: vpmovsxbd (%rcx), %zmm27 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x21,0x19] + vpmovsxbd (%rcx), %zmm27 + +// CHECK: vpmovsxbd 291(%rax,%r14,8), %zmm27 +// CHECK: encoding: [0x62,0x22,0x7d,0x48,0x21,0x9c,0xf0,0x23,0x01,0x00,0x00] + vpmovsxbd 291(%rax,%r14,8), %zmm27 + +// CHECK: vpmovsxbd 2032(%rdx), %zmm27 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x21,0x5a,0x7f] + vpmovsxbd 2032(%rdx), %zmm27 + +// CHECK: vpmovsxbd 2048(%rdx), %zmm27 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x21,0x9a,0x00,0x08,0x00,0x00] + vpmovsxbd 2048(%rdx), %zmm27 + +// CHECK: vpmovsxbd -2048(%rdx), %zmm27 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x21,0x5a,0x80] + vpmovsxbd -2048(%rdx), %zmm27 + +// CHECK: vpmovsxbd -2064(%rdx), %zmm27 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x21,0x9a,0xf0,0xf7,0xff,0xff] + vpmovsxbd -2064(%rdx), %zmm27 + +// CHECK: vpmovsxbd (%rcx), %zmm27 {%k1} +// CHECK: encoding: [0x62,0x62,0x7d,0x49,0x21,0x19] + vpmovsxbd (%rcx), %zmm27 {%k1} + +// CHECK: vpmovsxbd (%rcx), %zmm27 {%k2} {z} +// CHECK: encoding: [0x62,0x62,0x7d,0xca,0x21,0x19] + vpmovsxbd (%rcx), %zmm27 {%k2} {z} + +// CHECK: vpmovsxbq %xmm11, %zmm11 +// CHECK: encoding: [0x62,0x52,0x7d,0x48,0x22,0xdb] + vpmovsxbq %xmm11, %zmm11 + +// CHECK: vpmovsxbq %xmm11, %zmm11 {%k5} +// CHECK: encoding: [0x62,0x52,0x7d,0x4d,0x22,0xdb] + vpmovsxbq %xmm11, %zmm11 {%k5} + +// CHECK: vpmovsxbq %xmm11, %zmm11 {%k5} {z} +// CHECK: encoding: [0x62,0x52,0x7d,0xcd,0x22,0xdb] + vpmovsxbq %xmm11, %zmm11 {%k5} {z} + +// CHECK: vpmovsxbq (%rcx), %zmm11 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x22,0x19] + vpmovsxbq (%rcx), %zmm11 + +// CHECK: vpmovsxbq 291(%rax,%r14,8), %zmm11 +// CHECK: encoding: [0x62,0x32,0x7d,0x48,0x22,0x9c,0xf0,0x23,0x01,0x00,0x00] + vpmovsxbq 291(%rax,%r14,8), %zmm11 + +// CHECK: vpmovsxbq 1016(%rdx), %zmm11 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x22,0x5a,0x7f] + vpmovsxbq 1016(%rdx), %zmm11 + +// CHECK: vpmovsxbq 1024(%rdx), %zmm11 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x22,0x9a,0x00,0x04,0x00,0x00] + vpmovsxbq 1024(%rdx), %zmm11 + +// CHECK: vpmovsxbq -1024(%rdx), %zmm11 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x22,0x5a,0x80] + vpmovsxbq -1024(%rdx), %zmm11 + +// CHECK: vpmovsxbq -1032(%rdx), %zmm11 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x22,0x9a,0xf8,0xfb,0xff,0xff] + vpmovsxbq -1032(%rdx), %zmm11 + +// CHECK: vpmovsxdq %ymm29, %zmm26 +// CHECK: encoding: [0x62,0x02,0x7d,0x48,0x25,0xd5] + vpmovsxdq %ymm29, %zmm26 + +// CHECK: vpmovsxdq %ymm29, %zmm26 {%k1} +// CHECK: encoding: [0x62,0x02,0x7d,0x49,0x25,0xd5] + vpmovsxdq %ymm29, %zmm26 {%k1} + +// CHECK: vpmovsxdq %ymm29, %zmm26 {%k1} {z} +// CHECK: encoding: [0x62,0x02,0x7d,0xc9,0x25,0xd5] + vpmovsxdq %ymm29, %zmm26 {%k1} {z} + +// CHECK: vpmovsxdq (%rcx), %zmm26 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x25,0x11] + vpmovsxdq (%rcx), %zmm26 + +// CHECK: vpmovsxdq 291(%rax,%r14,8), %zmm26 +// CHECK: encoding: [0x62,0x22,0x7d,0x48,0x25,0x94,0xf0,0x23,0x01,0x00,0x00] + vpmovsxdq 291(%rax,%r14,8), %zmm26 + +// CHECK: vpmovsxdq 4064(%rdx), %zmm26 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x25,0x52,0x7f] + vpmovsxdq 4064(%rdx), %zmm26 + +// CHECK: vpmovsxdq 4096(%rdx), %zmm26 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x25,0x92,0x00,0x10,0x00,0x00] + vpmovsxdq 4096(%rdx), %zmm26 + +// CHECK: vpmovsxdq -4096(%rdx), %zmm26 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x25,0x52,0x80] + vpmovsxdq -4096(%rdx), %zmm26 + +// CHECK: vpmovsxdq -4128(%rdx), %zmm26 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x25,0x92,0xe0,0xef,0xff,0xff] + vpmovsxdq -4128(%rdx), %zmm26 + +// CHECK: vpmovsxwd %ymm11, %zmm23 +// CHECK: encoding: [0x62,0xc2,0x7d,0x48,0x23,0xfb] + vpmovsxwd %ymm11, %zmm23 + +// CHECK: vpmovsxwd %ymm11, %zmm23 {%k2} +// CHECK: encoding: [0x62,0xc2,0x7d,0x4a,0x23,0xfb] + vpmovsxwd %ymm11, %zmm23 {%k2} + +// CHECK: vpmovsxwd %ymm11, %zmm23 {%k2} {z} +// CHECK: encoding: [0x62,0xc2,0x7d,0xca,0x23,0xfb] + vpmovsxwd %ymm11, %zmm23 {%k2} {z} + +// CHECK: vpmovsxwd (%rcx), %zmm23 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x23,0x39] + vpmovsxwd (%rcx), %zmm23 + +// CHECK: vpmovsxwd 291(%rax,%r14,8), %zmm23 +// CHECK: encoding: [0x62,0xa2,0x7d,0x48,0x23,0xbc,0xf0,0x23,0x01,0x00,0x00] + vpmovsxwd 291(%rax,%r14,8), %zmm23 + +// CHECK: vpmovsxwd 4064(%rdx), %zmm23 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x23,0x7a,0x7f] + vpmovsxwd 4064(%rdx), %zmm23 + +// CHECK: vpmovsxwd 4096(%rdx), %zmm23 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x23,0xba,0x00,0x10,0x00,0x00] + vpmovsxwd 4096(%rdx), %zmm23 + +// CHECK: vpmovsxwd -4096(%rdx), %zmm23 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x23,0x7a,0x80] + vpmovsxwd -4096(%rdx), %zmm23 + +// CHECK: vpmovsxwd -4128(%rdx), %zmm23 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x23,0xba,0xe0,0xef,0xff,0xff] + vpmovsxwd -4128(%rdx), %zmm23 + +// CHECK: vpmovsxwq %xmm25, %zmm25 +// CHECK: encoding: [0x62,0x02,0x7d,0x48,0x24,0xc9] + vpmovsxwq %xmm25, %zmm25 + +// CHECK: vpmovsxwq %xmm25, %zmm25 {%k4} +// CHECK: encoding: [0x62,0x02,0x7d,0x4c,0x24,0xc9] + vpmovsxwq %xmm25, %zmm25 {%k4} + +// CHECK: vpmovsxwq %xmm25, %zmm25 {%k4} {z} +// CHECK: encoding: [0x62,0x02,0x7d,0xcc,0x24,0xc9] + vpmovsxwq %xmm25, %zmm25 {%k4} {z} + +// CHECK: vpmovsxwq (%rcx), %zmm25 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x24,0x09] + vpmovsxwq (%rcx), %zmm25 + +// CHECK: vpmovsxwq 291(%rax,%r14,8), %zmm25 +// CHECK: encoding: [0x62,0x22,0x7d,0x48,0x24,0x8c,0xf0,0x23,0x01,0x00,0x00] + vpmovsxwq 291(%rax,%r14,8), %zmm25 + +// CHECK: vpmovsxwq 2032(%rdx), %zmm25 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x24,0x4a,0x7f] + vpmovsxwq 2032(%rdx), %zmm25 + +// CHECK: vpmovsxwq 2048(%rdx), %zmm25 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x24,0x8a,0x00,0x08,0x00,0x00] + vpmovsxwq 2048(%rdx), %zmm25 + +// CHECK: vpmovsxwq -2048(%rdx), %zmm25 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x24,0x4a,0x80] + vpmovsxwq -2048(%rdx), %zmm25 + +// CHECK: vpmovsxwq -2064(%rdx), %zmm25 +// CHECK: encoding: [0x62,0x62,0x7d,0x48,0x24,0x8a,0xf0,0xf7,0xff,0xff] + vpmovsxwq -2064(%rdx), %zmm25 + +// CHECK: vpmovzxbd %xmm25, %zmm18 +// CHECK: encoding: [0x62,0x82,0x7d,0x48,0x31,0xd1] + vpmovzxbd %xmm25, %zmm18 + +// CHECK: vpmovzxbd %xmm25, %zmm18 {%k7} +// CHECK: encoding: [0x62,0x82,0x7d,0x4f,0x31,0xd1] + vpmovzxbd %xmm25, %zmm18 {%k7} + +// CHECK: vpmovzxbd %xmm25, %zmm18 {%k7} {z} +// CHECK: encoding: [0x62,0x82,0x7d,0xcf,0x31,0xd1] + vpmovzxbd %xmm25, %zmm18 {%k7} {z} + +// CHECK: vpmovzxbd (%rcx), %zmm18 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x31,0x11] + vpmovzxbd (%rcx), %zmm18 + +// CHECK: vpmovzxbd 291(%rax,%r14,8), %zmm18 +// CHECK: encoding: [0x62,0xa2,0x7d,0x48,0x31,0x94,0xf0,0x23,0x01,0x00,0x00] + vpmovzxbd 291(%rax,%r14,8), %zmm18 + +// CHECK: vpmovzxbd 2032(%rdx), %zmm18 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x31,0x52,0x7f] + vpmovzxbd 2032(%rdx), %zmm18 + +// CHECK: vpmovzxbd 2048(%rdx), %zmm18 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x31,0x92,0x00,0x08,0x00,0x00] + vpmovzxbd 2048(%rdx), %zmm18 + +// CHECK: vpmovzxbd -2048(%rdx), %zmm18 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x31,0x52,0x80] + vpmovzxbd -2048(%rdx), %zmm18 + +// CHECK: vpmovzxbd -2064(%rdx), %zmm18 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x31,0x92,0xf0,0xf7,0xff,0xff] + vpmovzxbd -2064(%rdx), %zmm18 + +// CHECK: vpmovzxbq %xmm15, %zmm5 +// CHECK: encoding: [0x62,0xd2,0x7d,0x48,0x32,0xef] + vpmovzxbq %xmm15, %zmm5 + +// CHECK: vpmovzxbq %xmm15, %zmm5 {%k1} +// CHECK: encoding: [0x62,0xd2,0x7d,0x49,0x32,0xef] + vpmovzxbq %xmm15, %zmm5 {%k1} + +// CHECK: vpmovzxbq %xmm15, %zmm5 {%k1} {z} +// CHECK: encoding: [0x62,0xd2,0x7d,0xc9,0x32,0xef] + vpmovzxbq %xmm15, %zmm5 {%k1} {z} + +// CHECK: vpmovzxbq (%rcx), %zmm5 +// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x32,0x29] + vpmovzxbq (%rcx), %zmm5 + +// CHECK: vpmovzxbq 291(%rax,%r14,8), %zmm5 +// CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x32,0xac,0xf0,0x23,0x01,0x00,0x00] + vpmovzxbq 291(%rax,%r14,8), %zmm5 + +// CHECK: vpmovzxbq 1016(%rdx), %zmm5 +// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x32,0x6a,0x7f] + vpmovzxbq 1016(%rdx), %zmm5 + +// CHECK: vpmovzxbq 1024(%rdx), %zmm5 +// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x32,0xaa,0x00,0x04,0x00,0x00] + vpmovzxbq 1024(%rdx), %zmm5 + +// CHECK: vpmovzxbq -1024(%rdx), %zmm5 +// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x32,0x6a,0x80] + vpmovzxbq -1024(%rdx), %zmm5 + +// CHECK: vpmovzxbq -1032(%rdx), %zmm5 +// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x32,0xaa,0xf8,0xfb,0xff,0xff] + vpmovzxbq -1032(%rdx), %zmm5 + +// CHECK: vpmovzxdq %ymm4, %zmm20 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x35,0xe4] + vpmovzxdq %ymm4, %zmm20 + +// CHECK: vpmovzxdq %ymm4, %zmm20 {%k3} +// CHECK: encoding: [0x62,0xe2,0x7d,0x4b,0x35,0xe4] + vpmovzxdq %ymm4, %zmm20 {%k3} + +// CHECK: vpmovzxdq %ymm4, %zmm20 {%k3} {z} +// CHECK: encoding: [0x62,0xe2,0x7d,0xcb,0x35,0xe4] + vpmovzxdq %ymm4, %zmm20 {%k3} {z} + +// CHECK: vpmovzxdq (%rcx), %zmm20 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x35,0x21] + vpmovzxdq (%rcx), %zmm20 + +// CHECK: vpmovzxdq 291(%rax,%r14,8), %zmm20 +// CHECK: encoding: [0x62,0xa2,0x7d,0x48,0x35,0xa4,0xf0,0x23,0x01,0x00,0x00] + vpmovzxdq 291(%rax,%r14,8), %zmm20 + +// CHECK: vpmovzxdq 4064(%rdx), %zmm20 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x35,0x62,0x7f] + vpmovzxdq 4064(%rdx), %zmm20 + +// CHECK: vpmovzxdq 4096(%rdx), %zmm20 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x35,0xa2,0x00,0x10,0x00,0x00] + vpmovzxdq 4096(%rdx), %zmm20 + +// CHECK: vpmovzxdq -4096(%rdx), %zmm20 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x35,0x62,0x80] + vpmovzxdq -4096(%rdx), %zmm20 + +// CHECK: vpmovzxdq -4128(%rdx), %zmm20 +// CHECK: encoding: [0x62,0xe2,0x7d,0x48,0x35,0xa2,0xe0,0xef,0xff,0xff] + vpmovzxdq -4128(%rdx), %zmm20 + +// CHECK: vpmovzxwd %ymm6, %zmm8 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x33,0xc6] + vpmovzxwd %ymm6, %zmm8 + +// CHECK: vpmovzxwd %ymm6, %zmm8 {%k7} +// CHECK: encoding: [0x62,0x72,0x7d,0x4f,0x33,0xc6] + vpmovzxwd %ymm6, %zmm8 {%k7} + +// CHECK: vpmovzxwd %ymm6, %zmm8 {%k7} {z} +// CHECK: encoding: [0x62,0x72,0x7d,0xcf,0x33,0xc6] + vpmovzxwd %ymm6, %zmm8 {%k7} {z} + +// CHECK: vpmovzxwd (%rcx), %zmm8 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x33,0x01] + vpmovzxwd (%rcx), %zmm8 + +// CHECK: vpmovzxwd 291(%rax,%r14,8), %zmm8 +// CHECK: encoding: [0x62,0x32,0x7d,0x48,0x33,0x84,0xf0,0x23,0x01,0x00,0x00] + vpmovzxwd 291(%rax,%r14,8), %zmm8 + +// CHECK: vpmovzxwd 4064(%rdx), %zmm8 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x33,0x42,0x7f] + vpmovzxwd 4064(%rdx), %zmm8 + +// CHECK: vpmovzxwd 4096(%rdx), %zmm8 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x33,0x82,0x00,0x10,0x00,0x00] + vpmovzxwd 4096(%rdx), %zmm8 + +// CHECK: vpmovzxwd -4096(%rdx), %zmm8 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x33,0x42,0x80] + vpmovzxwd -4096(%rdx), %zmm8 + +// CHECK: vpmovzxwd -4128(%rdx), %zmm8 +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x33,0x82,0xe0,0xef,0xff,0xff] + vpmovzxwd -4128(%rdx), %zmm8 + +// CHECK: vpmovzxwq %xmm15, %zmm5 +// CHECK: encoding: [0x62,0xd2,0x7d,0x48,0x34,0xef] + vpmovzxwq %xmm15, %zmm5 + +// CHECK: vpmovzxwq %xmm15, %zmm5 {%k7} +// CHECK: encoding: [0x62,0xd2,0x7d,0x4f,0x34,0xef] + vpmovzxwq %xmm15, %zmm5 {%k7} + +// CHECK: vpmovzxwq %xmm15, %zmm5 {%k7} {z} +// CHECK: encoding: [0x62,0xd2,0x7d,0xcf,0x34,0xef] + vpmovzxwq %xmm15, %zmm5 {%k7} {z} + +// CHECK: vpmovzxwq (%rcx), %zmm5 +// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x34,0x29] + vpmovzxwq (%rcx), %zmm5 + +// CHECK: vpmovzxwq 291(%rax,%r14,8), %zmm5 +// CHECK: encoding: [0x62,0xb2,0x7d,0x48,0x34,0xac,0xf0,0x23,0x01,0x00,0x00] + vpmovzxwq 291(%rax,%r14,8), %zmm5 + +// CHECK: vpmovzxwq 2032(%rdx), %zmm5 +// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x34,0x6a,0x7f] + vpmovzxwq 2032(%rdx), %zmm5 + +// CHECK: vpmovzxwq 2048(%rdx), %zmm5 +// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x34,0xaa,0x00,0x08,0x00,0x00] + vpmovzxwq 2048(%rdx), %zmm5 + +// CHECK: vpmovzxwq -2048(%rdx), %zmm5 +// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x34,0x6a,0x80] + vpmovzxwq -2048(%rdx), %zmm5 + +// CHECK: vpmovzxwq -2064(%rdx), %zmm5 +// CHECK: encoding: [0x62,0xf2,0x7d,0x48,0x34,0xaa,0xf0,0xf7,0xff,0xff] + vpmovzxwq -2064(%rdx), %zmm5 + // CHECK: vpmuldq %zmm9, %zmm9, %zmm29 // CHECK: encoding: [0x62,0x42,0xb5,0x48,0x28,0xe9] vpmuldq %zmm9, %zmm9, %zmm29 @@ -2056,6 +2408,10 @@ // CHECK: encoding: [0x62,0x71,0x9d,0x48,0x5c,0x8a,0x00,0x20,0x00,0x00] vsubpd 8192(%rdx), %zmm12, %zmm9 +// CHECK: vsubpd -8192(%rdx), %zmm12, %zmm9 +// CHECK: encoding: [0x62,0x71,0x9d,0x48,0x5c,0x4a,0x80] + vsubpd -8192(%rdx), %zmm12, %zmm9 + // CHECK: vsubpd -8256(%rdx), %zmm12, %zmm9 // CHECK: encoding: [0x62,0x71,0x9d,0x48,0x5c,0x8a,0xc0,0xdf,0xff,0xff] vsubpd -8256(%rdx), %zmm12, %zmm9 @@ -2068,6 +2424,10 @@ // CHECK: encoding: [0x62,0x71,0x9d,0x58,0x5c,0x8a,0x00,0x04,0x00,0x00] vsubpd 1024(%rdx){1to8}, %zmm12, %zmm9 +// CHECK: vsubpd -1024(%rdx){1to8}, %zmm12, %zmm9 +// CHECK: encoding: [0x62,0x71,0x9d,0x58,0x5c,0x4a,0x80] + vsubpd -1024(%rdx){1to8}, %zmm12, %zmm9 + // CHECK: vsubpd -1032(%rdx){1to8}, %zmm12, %zmm9 // CHECK: encoding: [0x62,0x71,0x9d,0x58,0x5c,0x8a,0xf8,0xfb,0xff,0xff] vsubpd -1032(%rdx){1to8}, %zmm12, %zmm9 @@ -2104,6 +2464,10 @@ // CHECK: encoding: [0x62,0x71,0x24,0x40,0x5c,0xb2,0x00,0x20,0x00,0x00] vsubps 8192(%rdx), %zmm27, %zmm14 +// CHECK: vsubps -8192(%rdx), %zmm27, %zmm14 +// CHECK: encoding: [0x62,0x71,0x24,0x40,0x5c,0x72,0x80] + vsubps -8192(%rdx), %zmm27, %zmm14 + // CHECK: vsubps -8256(%rdx), %zmm27, %zmm14 // CHECK: encoding: [0x62,0x71,0x24,0x40,0x5c,0xb2,0xc0,0xdf,0xff,0xff] vsubps -8256(%rdx), %zmm27, %zmm14 @@ -2116,10 +2480,614 @@ // CHECK: encoding: [0x62,0x71,0x24,0x50,0x5c,0xb2,0x00,0x02,0x00,0x00] vsubps 512(%rdx){1to16}, %zmm27, %zmm14 +// CHECK: vsubps -512(%rdx){1to16}, %zmm27, %zmm14 +// CHECK: encoding: [0x62,0x71,0x24,0x50,0x5c,0x72,0x80] + vsubps -512(%rdx){1to16}, %zmm27, %zmm14 + // CHECK: vsubps -516(%rdx){1to16}, %zmm27, %zmm14 // CHECK: encoding: [0x62,0x71,0x24,0x50,0x5c,0xb2,0xfc,0xfd,0xff,0xff] vsubps -516(%rdx){1to16}, %zmm27, %zmm14 +// CHECK: vpmovqb %zmm2, %xmm3 +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x32,0xd3] + vpmovqb %zmm2, %xmm3 + +// CHECK: vpmovqb %zmm2, %xmm3 {%k1} +// CHECK: encoding: [0x62,0xf2,0x7e,0x49,0x32,0xd3] + vpmovqb %zmm2, %xmm3 {%k1} + +// CHECK: vpmovqb %zmm2, %xmm3 {%k1} {z} +// CHECK: encoding: [0x62,0xf2,0x7e,0xc9,0x32,0xd3] + vpmovqb %zmm2, %xmm3 {%k1} {z} + +// CHECK: vpmovsqb %zmm29, %xmm30 +// CHECK: encoding: [0x62,0x02,0x7e,0x48,0x22,0xee] + vpmovsqb %zmm29, %xmm30 + +// CHECK: vpmovsqb %zmm29, %xmm30 {%k5} +// CHECK: encoding: [0x62,0x02,0x7e,0x4d,0x22,0xee] + vpmovsqb %zmm29, %xmm30 {%k5} + +// CHECK: vpmovsqb %zmm29, %xmm30 {%k5} {z} +// CHECK: encoding: [0x62,0x02,0x7e,0xcd,0x22,0xee] + vpmovsqb %zmm29, %xmm30 {%k5} {z} + +// CHECK: vpmovusqb %zmm28, %xmm24 +// CHECK: encoding: [0x62,0x02,0x7e,0x48,0x12,0xe0] + vpmovusqb %zmm28, %xmm24 + +// CHECK: vpmovusqb %zmm28, %xmm24 {%k7} +// CHECK: encoding: [0x62,0x02,0x7e,0x4f,0x12,0xe0] + vpmovusqb %zmm28, %xmm24 {%k7} + +// CHECK: vpmovusqb %zmm28, %xmm24 {%k7} {z} +// CHECK: encoding: [0x62,0x02,0x7e,0xcf,0x12,0xe0] + vpmovusqb %zmm28, %xmm24 {%k7} {z} + +// CHECK: vpmovqw %zmm18, %xmm6 +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x34,0xd6] + vpmovqw %zmm18, %xmm6 + +// CHECK: vpmovqw %zmm18, %xmm6 {%k1} +// CHECK: encoding: [0x62,0xe2,0x7e,0x49,0x34,0xd6] + vpmovqw %zmm18, %xmm6 {%k1} + +// CHECK: vpmovqw %zmm18, %xmm6 {%k1} {z} +// CHECK: encoding: [0x62,0xe2,0x7e,0xc9,0x34,0xd6] + vpmovqw %zmm18, %xmm6 {%k1} {z} + +// CHECK: vpmovsqw %zmm19, %xmm27 +// CHECK: encoding: [0x62,0x82,0x7e,0x48,0x24,0xdb] + vpmovsqw %zmm19, %xmm27 + +// CHECK: vpmovsqw %zmm19, %xmm27 {%k6} +// CHECK: encoding: [0x62,0x82,0x7e,0x4e,0x24,0xdb] + vpmovsqw %zmm19, %xmm27 {%k6} + +// CHECK: vpmovsqw %zmm19, %xmm27 {%k6} {z} +// CHECK: encoding: [0x62,0x82,0x7e,0xce,0x24,0xdb] + vpmovsqw %zmm19, %xmm27 {%k6} {z} + +// CHECK: vpmovusqw %zmm10, %xmm28 +// CHECK: encoding: [0x62,0x12,0x7e,0x48,0x14,0xd4] + vpmovusqw %zmm10, %xmm28 + +// CHECK: vpmovusqw %zmm10, %xmm28 {%k7} +// CHECK: encoding: [0x62,0x12,0x7e,0x4f,0x14,0xd4] + vpmovusqw %zmm10, %xmm28 {%k7} + +// CHECK: vpmovusqw %zmm10, %xmm28 {%k7} {z} +// CHECK: encoding: [0x62,0x12,0x7e,0xcf,0x14,0xd4] + vpmovusqw %zmm10, %xmm28 {%k7} {z} + +// CHECK: vpmovqd %zmm25, %ymm6 +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x35,0xce] + vpmovqd %zmm25, %ymm6 + +// CHECK: vpmovqd %zmm25, %ymm6 {%k5} +// CHECK: encoding: [0x62,0x62,0x7e,0x4d,0x35,0xce] + vpmovqd %zmm25, %ymm6 {%k5} + +// CHECK: vpmovqd %zmm25, %ymm6 {%k5} {z} +// CHECK: encoding: [0x62,0x62,0x7e,0xcd,0x35,0xce] + vpmovqd %zmm25, %ymm6 {%k5} {z} + +// CHECK: vpmovsqd %zmm2, %ymm15 +// CHECK: encoding: [0x62,0xd2,0x7e,0x48,0x25,0xd7] + vpmovsqd %zmm2, %ymm15 + +// CHECK: vpmovsqd %zmm2, %ymm15 {%k2} +// CHECK: encoding: [0x62,0xd2,0x7e,0x4a,0x25,0xd7] + vpmovsqd %zmm2, %ymm15 {%k2} + +// CHECK: vpmovsqd %zmm2, %ymm15 {%k2} {z} +// CHECK: encoding: [0x62,0xd2,0x7e,0xca,0x25,0xd7] + vpmovsqd %zmm2, %ymm15 {%k2} {z} + +// CHECK: vpmovusqd %zmm4, %ymm8 +// CHECK: encoding: [0x62,0xd2,0x7e,0x48,0x15,0xe0] + vpmovusqd %zmm4, %ymm8 + +// CHECK: vpmovusqd %zmm4, %ymm8 {%k4} +// CHECK: encoding: [0x62,0xd2,0x7e,0x4c,0x15,0xe0] + vpmovusqd %zmm4, %ymm8 {%k4} + +// CHECK: vpmovusqd %zmm4, %ymm8 {%k4} {z} +// CHECK: encoding: [0x62,0xd2,0x7e,0xcc,0x15,0xe0] + vpmovusqd %zmm4, %ymm8 {%k4} {z} + +// CHECK: vpmovdb %zmm5, %xmm2 +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x31,0xea] + vpmovdb %zmm5, %xmm2 + +// CHECK: vpmovdb %zmm5, %xmm2 {%k5} +// CHECK: encoding: [0x62,0xf2,0x7e,0x4d,0x31,0xea] + vpmovdb %zmm5, %xmm2 {%k5} + +// CHECK: vpmovdb %zmm5, %xmm2 {%k5} {z} +// CHECK: encoding: [0x62,0xf2,0x7e,0xcd,0x31,0xea] + vpmovdb %zmm5, %xmm2 {%k5} {z} + +// CHECK: vpmovsdb %zmm2, %xmm21 +// CHECK: encoding: [0x62,0xb2,0x7e,0x48,0x21,0xd5] + vpmovsdb %zmm2, %xmm21 + +// CHECK: vpmovsdb %zmm2, %xmm21 {%k4} +// CHECK: encoding: [0x62,0xb2,0x7e,0x4c,0x21,0xd5] + vpmovsdb %zmm2, %xmm21 {%k4} + +// CHECK: vpmovsdb %zmm2, %xmm21 {%k4} {z} +// CHECK: encoding: [0x62,0xb2,0x7e,0xcc,0x21,0xd5] + vpmovsdb %zmm2, %xmm21 {%k4} {z} + +// CHECK: vpmovusdb %zmm2, %xmm20 +// CHECK: encoding: [0x62,0xb2,0x7e,0x48,0x11,0xd4] + vpmovusdb %zmm2, %xmm20 + +// CHECK: vpmovusdb %zmm2, %xmm20 {%k3} +// CHECK: encoding: [0x62,0xb2,0x7e,0x4b,0x11,0xd4] + vpmovusdb %zmm2, %xmm20 {%k3} + +// CHECK: vpmovusdb %zmm2, %xmm20 {%k3} {z} +// CHECK: encoding: [0x62,0xb2,0x7e,0xcb,0x11,0xd4] + vpmovusdb %zmm2, %xmm20 {%k3} {z} + +// CHECK: vpmovdw %zmm29, %ymm22 +// CHECK: encoding: [0x62,0x22,0x7e,0x48,0x33,0xee] + vpmovdw %zmm29, %ymm22 + +// CHECK: vpmovdw %zmm29, %ymm22 {%k5} +// CHECK: encoding: [0x62,0x22,0x7e,0x4d,0x33,0xee] + vpmovdw %zmm29, %ymm22 {%k5} + +// CHECK: vpmovdw %zmm29, %ymm22 {%k5} {z} +// CHECK: encoding: [0x62,0x22,0x7e,0xcd,0x33,0xee] + vpmovdw %zmm29, %ymm22 {%k5} {z} + +// CHECK: vpmovsdw %zmm14, %ymm25 +// CHECK: encoding: [0x62,0x12,0x7e,0x48,0x23,0xf1] + vpmovsdw %zmm14, %ymm25 + +// CHECK: vpmovsdw %zmm14, %ymm25 {%k4} +// CHECK: encoding: [0x62,0x12,0x7e,0x4c,0x23,0xf1] + vpmovsdw %zmm14, %ymm25 {%k4} + +// CHECK: vpmovsdw %zmm14, %ymm25 {%k4} {z} +// CHECK: encoding: [0x62,0x12,0x7e,0xcc,0x23,0xf1] + vpmovsdw %zmm14, %ymm25 {%k4} {z} + +// CHECK: vpmovusdw %zmm7, %ymm8 +// CHECK: encoding: [0x62,0xd2,0x7e,0x48,0x13,0xf8] + vpmovusdw %zmm7, %ymm8 + +// CHECK: vpmovusdw %zmm7, %ymm8 {%k1} +// CHECK: encoding: [0x62,0xd2,0x7e,0x49,0x13,0xf8] + vpmovusdw %zmm7, %ymm8 {%k1} + +// CHECK: vpmovusdw %zmm7, %ymm8 {%k1} {z} +// CHECK: encoding: [0x62,0xd2,0x7e,0xc9,0x13,0xf8] + vpmovusdw %zmm7, %ymm8 {%k1} {z} + +// CHECK: vpmovqb %zmm3, (%rcx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x32,0x19] + vpmovqb %zmm3, (%rcx) + +// CHECK: vpmovqb %zmm3, (%rcx) {%k7} +// CHECK: encoding: [0x62,0xf2,0x7e,0x4f,0x32,0x19] + vpmovqb %zmm3, (%rcx) {%k7} + +// CHECK: vpmovqb %zmm3, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0xb2,0x7e,0x48,0x32,0x9c,0xf0,0x23,0x01,0x00,0x00] + vpmovqb %zmm3, 291(%rax,%r14,8) + +// CHECK: vpmovqb %zmm3, 1016(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x32,0x5a,0x7f] + vpmovqb %zmm3, 1016(%rdx) + +// CHECK: vpmovqb %zmm3, 1024(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x32,0x9a,0x00,0x04,0x00,0x00] + vpmovqb %zmm3, 1024(%rdx) + +// CHECK: vpmovqb %zmm3, -1024(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x32,0x5a,0x80] + vpmovqb %zmm3, -1024(%rdx) + +// CHECK: vpmovqb %zmm3, -1032(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x32,0x9a,0xf8,0xfb,0xff,0xff] + vpmovqb %zmm3, -1032(%rdx) + +// CHECK: vpmovsqb %zmm16, (%rcx) +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x22,0x01] + vpmovsqb %zmm16, (%rcx) + +// CHECK: vpmovsqb %zmm16, (%rcx) {%k2} +// CHECK: encoding: [0x62,0xe2,0x7e,0x4a,0x22,0x01] + vpmovsqb %zmm16, (%rcx) {%k2} + +// CHECK: vpmovsqb %zmm16, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0xa2,0x7e,0x48,0x22,0x84,0xf0,0x23,0x01,0x00,0x00] + vpmovsqb %zmm16, 291(%rax,%r14,8) + +// CHECK: vpmovsqb %zmm16, 1016(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x22,0x42,0x7f] + vpmovsqb %zmm16, 1016(%rdx) + +// CHECK: vpmovsqb %zmm16, 1024(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x22,0x82,0x00,0x04,0x00,0x00] + vpmovsqb %zmm16, 1024(%rdx) + +// CHECK: vpmovsqb %zmm16, -1024(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x22,0x42,0x80] + vpmovsqb %zmm16, -1024(%rdx) + +// CHECK: vpmovsqb %zmm16, -1032(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x22,0x82,0xf8,0xfb,0xff,0xff] + vpmovsqb %zmm16, -1032(%rdx) + +// CHECK: vpmovusqb %zmm28, (%rcx) +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x12,0x21] + vpmovusqb %zmm28, (%rcx) + +// CHECK: vpmovusqb %zmm28, (%rcx) {%k1} +// CHECK: encoding: [0x62,0x62,0x7e,0x49,0x12,0x21] + vpmovusqb %zmm28, (%rcx) {%k1} + +// CHECK: vpmovusqb %zmm28, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0x22,0x7e,0x48,0x12,0xa4,0xf0,0x23,0x01,0x00,0x00] + vpmovusqb %zmm28, 291(%rax,%r14,8) + +// CHECK: vpmovusqb %zmm28, 1016(%rdx) +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x12,0x62,0x7f] + vpmovusqb %zmm28, 1016(%rdx) + +// CHECK: vpmovusqb %zmm28, 1024(%rdx) +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x12,0xa2,0x00,0x04,0x00,0x00] + vpmovusqb %zmm28, 1024(%rdx) + +// CHECK: vpmovusqb %zmm28, -1024(%rdx) +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x12,0x62,0x80] + vpmovusqb %zmm28, -1024(%rdx) + +// CHECK: vpmovusqb %zmm28, -1032(%rdx) +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x12,0xa2,0xf8,0xfb,0xff,0xff] + vpmovusqb %zmm28, -1032(%rdx) + +// CHECK: vpmovqw %zmm7, (%rcx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x34,0x39] + vpmovqw %zmm7, (%rcx) + +// CHECK: vpmovqw %zmm7, (%rcx) {%k6} +// CHECK: encoding: [0x62,0xf2,0x7e,0x4e,0x34,0x39] + vpmovqw %zmm7, (%rcx) {%k6} + +// CHECK: vpmovqw %zmm7, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0xb2,0x7e,0x48,0x34,0xbc,0xf0,0x23,0x01,0x00,0x00] + vpmovqw %zmm7, 291(%rax,%r14,8) + +// CHECK: vpmovqw %zmm7, 2032(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x34,0x7a,0x7f] + vpmovqw %zmm7, 2032(%rdx) + +// CHECK: vpmovqw %zmm7, 2048(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x34,0xba,0x00,0x08,0x00,0x00] + vpmovqw %zmm7, 2048(%rdx) + +// CHECK: vpmovqw %zmm7, -2048(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x34,0x7a,0x80] + vpmovqw %zmm7, -2048(%rdx) + +// CHECK: vpmovqw %zmm7, -2064(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x34,0xba,0xf0,0xf7,0xff,0xff] + vpmovqw %zmm7, -2064(%rdx) + +// CHECK: vpmovsqw %zmm1, (%rcx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x24,0x09] + vpmovsqw %zmm1, (%rcx) + +// CHECK: vpmovsqw %zmm1, (%rcx) {%k5} +// CHECK: encoding: [0x62,0xf2,0x7e,0x4d,0x24,0x09] + vpmovsqw %zmm1, (%rcx) {%k5} + +// CHECK: vpmovsqw %zmm1, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0xb2,0x7e,0x48,0x24,0x8c,0xf0,0x23,0x01,0x00,0x00] + vpmovsqw %zmm1, 291(%rax,%r14,8) + +// CHECK: vpmovsqw %zmm1, 2032(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x24,0x4a,0x7f] + vpmovsqw %zmm1, 2032(%rdx) + +// CHECK: vpmovsqw %zmm1, 2048(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x24,0x8a,0x00,0x08,0x00,0x00] + vpmovsqw %zmm1, 2048(%rdx) + +// CHECK: vpmovsqw %zmm1, -2048(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x24,0x4a,0x80] + vpmovsqw %zmm1, -2048(%rdx) + +// CHECK: vpmovsqw %zmm1, -2064(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x24,0x8a,0xf0,0xf7,0xff,0xff] + vpmovsqw %zmm1, -2064(%rdx) + +// CHECK: vpmovusqw %zmm25, (%rcx) +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x14,0x09] + vpmovusqw %zmm25, (%rcx) + +// CHECK: vpmovusqw %zmm25, (%rcx) {%k3} +// CHECK: encoding: [0x62,0x62,0x7e,0x4b,0x14,0x09] + vpmovusqw %zmm25, (%rcx) {%k3} + +// CHECK: vpmovusqw %zmm25, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0x22,0x7e,0x48,0x14,0x8c,0xf0,0x23,0x01,0x00,0x00] + vpmovusqw %zmm25, 291(%rax,%r14,8) + +// CHECK: vpmovusqw %zmm25, 2032(%rdx) +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x14,0x4a,0x7f] + vpmovusqw %zmm25, 2032(%rdx) + +// CHECK: vpmovusqw %zmm25, 2048(%rdx) +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x14,0x8a,0x00,0x08,0x00,0x00] + vpmovusqw %zmm25, 2048(%rdx) + +// CHECK: vpmovusqw %zmm25, -2048(%rdx) +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x14,0x4a,0x80] + vpmovusqw %zmm25, -2048(%rdx) + +// CHECK: vpmovusqw %zmm25, -2064(%rdx) +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x14,0x8a,0xf0,0xf7,0xff,0xff] + vpmovusqw %zmm25, -2064(%rdx) + +// CHECK: vpmovqd %zmm28, (%rcx) +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x35,0x21] + vpmovqd %zmm28, (%rcx) + +// CHECK: vpmovqd %zmm28, (%rcx) {%k5} +// CHECK: encoding: [0x62,0x62,0x7e,0x4d,0x35,0x21] + vpmovqd %zmm28, (%rcx) {%k5} + +// CHECK: vpmovqd %zmm28, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0x22,0x7e,0x48,0x35,0xa4,0xf0,0x23,0x01,0x00,0x00] + vpmovqd %zmm28, 291(%rax,%r14,8) + +// CHECK: vpmovqd %zmm28, 4064(%rdx) +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x35,0x62,0x7f] + vpmovqd %zmm28, 4064(%rdx) + +// CHECK: vpmovqd %zmm28, 4096(%rdx) +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x35,0xa2,0x00,0x10,0x00,0x00] + vpmovqd %zmm28, 4096(%rdx) + +// CHECK: vpmovqd %zmm28, -4096(%rdx) +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x35,0x62,0x80] + vpmovqd %zmm28, -4096(%rdx) + +// CHECK: vpmovqd %zmm28, -4128(%rdx) +// CHECK: encoding: [0x62,0x62,0x7e,0x48,0x35,0xa2,0xe0,0xef,0xff,0xff] + vpmovqd %zmm28, -4128(%rdx) + +// CHECK: vpmovsqd %zmm9, (%rcx) +// CHECK: encoding: [0x62,0x72,0x7e,0x48,0x25,0x09] + vpmovsqd %zmm9, (%rcx) + +// CHECK: vpmovsqd %zmm9, (%rcx) {%k7} +// CHECK: encoding: [0x62,0x72,0x7e,0x4f,0x25,0x09] + vpmovsqd %zmm9, (%rcx) {%k7} + +// CHECK: vpmovsqd %zmm9, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0x32,0x7e,0x48,0x25,0x8c,0xf0,0x23,0x01,0x00,0x00] + vpmovsqd %zmm9, 291(%rax,%r14,8) + +// CHECK: vpmovsqd %zmm9, 4064(%rdx) +// CHECK: encoding: [0x62,0x72,0x7e,0x48,0x25,0x4a,0x7f] + vpmovsqd %zmm9, 4064(%rdx) + +// CHECK: vpmovsqd %zmm9, 4096(%rdx) +// CHECK: encoding: [0x62,0x72,0x7e,0x48,0x25,0x8a,0x00,0x10,0x00,0x00] + vpmovsqd %zmm9, 4096(%rdx) + +// CHECK: vpmovsqd %zmm9, -4096(%rdx) +// CHECK: encoding: [0x62,0x72,0x7e,0x48,0x25,0x4a,0x80] + vpmovsqd %zmm9, -4096(%rdx) + +// CHECK: vpmovsqd %zmm9, -4128(%rdx) +// CHECK: encoding: [0x62,0x72,0x7e,0x48,0x25,0x8a,0xe0,0xef,0xff,0xff] + vpmovsqd %zmm9, -4128(%rdx) + +// CHECK: vpmovusqd %zmm22, (%rcx) +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x15,0x31] + vpmovusqd %zmm22, (%rcx) + +// CHECK: vpmovusqd %zmm22, (%rcx) {%k1} +// CHECK: encoding: [0x62,0xe2,0x7e,0x49,0x15,0x31] + vpmovusqd %zmm22, (%rcx) {%k1} + +// CHECK: vpmovusqd %zmm22, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0xa2,0x7e,0x48,0x15,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpmovusqd %zmm22, 291(%rax,%r14,8) + +// CHECK: vpmovusqd %zmm22, 4064(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x15,0x72,0x7f] + vpmovusqd %zmm22, 4064(%rdx) + +// CHECK: vpmovusqd %zmm22, 4096(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x15,0xb2,0x00,0x10,0x00,0x00] + vpmovusqd %zmm22, 4096(%rdx) + +// CHECK: vpmovusqd %zmm22, -4096(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x15,0x72,0x80] + vpmovusqd %zmm22, -4096(%rdx) + +// CHECK: vpmovusqd %zmm22, -4128(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x15,0xb2,0xe0,0xef,0xff,0xff] + vpmovusqd %zmm22, -4128(%rdx) + +// CHECK: vpmovdb %zmm12, (%rcx) +// CHECK: encoding: [0x62,0x72,0x7e,0x48,0x31,0x21] + vpmovdb %zmm12, (%rcx) + +// CHECK: vpmovdb %zmm12, (%rcx) {%k3} +// CHECK: encoding: [0x62,0x72,0x7e,0x4b,0x31,0x21] + vpmovdb %zmm12, (%rcx) {%k3} + +// CHECK: vpmovdb %zmm12, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0x32,0x7e,0x48,0x31,0xa4,0xf0,0x23,0x01,0x00,0x00] + vpmovdb %zmm12, 291(%rax,%r14,8) + +// CHECK: vpmovdb %zmm12, 2032(%rdx) +// CHECK: encoding: [0x62,0x72,0x7e,0x48,0x31,0x62,0x7f] + vpmovdb %zmm12, 2032(%rdx) + +// CHECK: vpmovdb %zmm12, 2048(%rdx) +// CHECK: encoding: [0x62,0x72,0x7e,0x48,0x31,0xa2,0x00,0x08,0x00,0x00] + vpmovdb %zmm12, 2048(%rdx) + +// CHECK: vpmovdb %zmm12, -2048(%rdx) +// CHECK: encoding: [0x62,0x72,0x7e,0x48,0x31,0x62,0x80] + vpmovdb %zmm12, -2048(%rdx) + +// CHECK: vpmovdb %zmm12, -2064(%rdx) +// CHECK: encoding: [0x62,0x72,0x7e,0x48,0x31,0xa2,0xf0,0xf7,0xff,0xff] + vpmovdb %zmm12, -2064(%rdx) + +// CHECK: vpmovsdb %zmm6, (%rcx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x21,0x31] + vpmovsdb %zmm6, (%rcx) + +// CHECK: vpmovsdb %zmm6, (%rcx) {%k1} +// CHECK: encoding: [0x62,0xf2,0x7e,0x49,0x21,0x31] + vpmovsdb %zmm6, (%rcx) {%k1} + +// CHECK: vpmovsdb %zmm6, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0xb2,0x7e,0x48,0x21,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpmovsdb %zmm6, 291(%rax,%r14,8) + +// CHECK: vpmovsdb %zmm6, 2032(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x21,0x72,0x7f] + vpmovsdb %zmm6, 2032(%rdx) + +// CHECK: vpmovsdb %zmm6, 2048(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x21,0xb2,0x00,0x08,0x00,0x00] + vpmovsdb %zmm6, 2048(%rdx) + +// CHECK: vpmovsdb %zmm6, -2048(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x21,0x72,0x80] + vpmovsdb %zmm6, -2048(%rdx) + +// CHECK: vpmovsdb %zmm6, -2064(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x21,0xb2,0xf0,0xf7,0xff,0xff] + vpmovsdb %zmm6, -2064(%rdx) + +// CHECK: vpmovusdb %zmm23, (%rcx) +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x11,0x39] + vpmovusdb %zmm23, (%rcx) + +// CHECK: vpmovusdb %zmm23, (%rcx) {%k3} +// CHECK: encoding: [0x62,0xe2,0x7e,0x4b,0x11,0x39] + vpmovusdb %zmm23, (%rcx) {%k3} + +// CHECK: vpmovusdb %zmm23, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0xa2,0x7e,0x48,0x11,0xbc,0xf0,0x23,0x01,0x00,0x00] + vpmovusdb %zmm23, 291(%rax,%r14,8) + +// CHECK: vpmovusdb %zmm23, 2032(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x11,0x7a,0x7f] + vpmovusdb %zmm23, 2032(%rdx) + +// CHECK: vpmovusdb %zmm23, 2048(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x11,0xba,0x00,0x08,0x00,0x00] + vpmovusdb %zmm23, 2048(%rdx) + +// CHECK: vpmovusdb %zmm23, -2048(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x11,0x7a,0x80] + vpmovusdb %zmm23, -2048(%rdx) + +// CHECK: vpmovusdb %zmm23, -2064(%rdx) +// CHECK: encoding: [0x62,0xe2,0x7e,0x48,0x11,0xba,0xf0,0xf7,0xff,0xff] + vpmovusdb %zmm23, -2064(%rdx) + +// CHECK: vpmovdw %zmm7, (%rcx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x33,0x39] + vpmovdw %zmm7, (%rcx) + +// CHECK: vpmovdw %zmm7, (%rcx) {%k7} +// CHECK: encoding: [0x62,0xf2,0x7e,0x4f,0x33,0x39] + vpmovdw %zmm7, (%rcx) {%k7} + +// CHECK: vpmovdw %zmm7, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0xb2,0x7e,0x48,0x33,0xbc,0xf0,0x23,0x01,0x00,0x00] + vpmovdw %zmm7, 291(%rax,%r14,8) + +// CHECK: vpmovdw %zmm7, 4064(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x33,0x7a,0x7f] + vpmovdw %zmm7, 4064(%rdx) + +// CHECK: vpmovdw %zmm7, 4096(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x33,0xba,0x00,0x10,0x00,0x00] + vpmovdw %zmm7, 4096(%rdx) + +// CHECK: vpmovdw %zmm7, -4096(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x33,0x7a,0x80] + vpmovdw %zmm7, -4096(%rdx) + +// CHECK: vpmovdw %zmm7, -4128(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x33,0xba,0xe0,0xef,0xff,0xff] + vpmovdw %zmm7, -4128(%rdx) + +// CHECK: vpmovsdw %zmm14, (%rcx) +// CHECK: encoding: [0x62,0x72,0x7e,0x48,0x23,0x31] + vpmovsdw %zmm14, (%rcx) + +// CHECK: vpmovsdw %zmm14, (%rcx) {%k6} +// CHECK: encoding: [0x62,0x72,0x7e,0x4e,0x23,0x31] + vpmovsdw %zmm14, (%rcx) {%k6} + +// CHECK: vpmovsdw %zmm14, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0x32,0x7e,0x48,0x23,0xb4,0xf0,0x23,0x01,0x00,0x00] + vpmovsdw %zmm14, 291(%rax,%r14,8) + +// CHECK: vpmovsdw %zmm14, 4064(%rdx) +// CHECK: encoding: [0x62,0x72,0x7e,0x48,0x23,0x72,0x7f] + vpmovsdw %zmm14, 4064(%rdx) + +// CHECK: vpmovsdw %zmm14, 4096(%rdx) +// CHECK: encoding: [0x62,0x72,0x7e,0x48,0x23,0xb2,0x00,0x10,0x00,0x00] + vpmovsdw %zmm14, 4096(%rdx) + +// CHECK: vpmovsdw %zmm14, -4096(%rdx) +// CHECK: encoding: [0x62,0x72,0x7e,0x48,0x23,0x72,0x80] + vpmovsdw %zmm14, -4096(%rdx) + +// CHECK: vpmovsdw %zmm14, -4128(%rdx) +// CHECK: encoding: [0x62,0x72,0x7e,0x48,0x23,0xb2,0xe0,0xef,0xff,0xff] + vpmovsdw %zmm14, -4128(%rdx) + +// CHECK: vpmovusdw %zmm5, (%rcx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x13,0x29] + vpmovusdw %zmm5, (%rcx) + +// CHECK: vpmovusdw %zmm5, (%rcx) {%k3} +// CHECK: encoding: [0x62,0xf2,0x7e,0x4b,0x13,0x29] + vpmovusdw %zmm5, (%rcx) {%k3} + +// CHECK: vpmovusdw %zmm5, 291(%rax,%r14,8) +// CHECK: encoding: [0x62,0xb2,0x7e,0x48,0x13,0xac,0xf0,0x23,0x01,0x00,0x00] + vpmovusdw %zmm5, 291(%rax,%r14,8) + +// CHECK: vpmovusdw %zmm5, 4064(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x13,0x6a,0x7f] + vpmovusdw %zmm5, 4064(%rdx) + +// CHECK: vpmovusdw %zmm5, 4096(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x13,0xaa,0x00,0x10,0x00,0x00] + vpmovusdw %zmm5, 4096(%rdx) + +// CHECK: vpmovusdw %zmm5, -4096(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x13,0x6a,0x80] + vpmovusdw %zmm5, -4096(%rdx) + +// CHECK: vpmovusdw %zmm5, -4128(%rdx) +// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x13,0xaa,0xe0,0xef,0xff,0xff] + vpmovusdw %zmm5, -4128(%rdx) + // CHECK: vinserti32x4 // CHECK: encoding: [0x62,0xa3,0x55,0x48,0x38,0xcd,0x01] vinserti32x4 $1, %xmm21, %zmm5, %zmm17 diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s index 2781ef4..10d420a 100644 --- a/test/MC/X86/x86-64.s +++ b/test/MC/X86/x86-64.s @@ -203,7 +203,7 @@ int $3 // CHECK-STDERR: warning: scale factor without index register is ignored movaps %xmm3, (%esi, 2) -// CHECK: imull $12, %eax, %eax +// CHECK: imull $12, %eax imul $12, %eax // CHECK: imull %ecx, %eax |