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authorJack Carter <jcarter@mips.com>2012-08-28 19:07:39 +0000
committerJack Carter <jcarter@mips.com>2012-08-28 19:07:39 +0000
commit69dba7e20476ec0e64791e47b498ae3a69619f7d (patch)
tree0db6a376d87abeb78ac6345e53868e7178a67746 /test/MC/Mips
parentc6c2ced38411215e5bf46ded787c23810160dfa7 (diff)
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Some instructions are passed to the assembler to be
transformed to the final instruction variant. An example would be dsrll which is transformed into dsll32 if the shift value is greater than 32. For direct object output we need to do this transformation in the codegen. If the instruction was inside branch delay slot, it was being missed. This patch corrects this oversight. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162779 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Mips')
-rw-r--r--test/MC/Mips/mips64shift.ll5
1 files changed, 4 insertions, 1 deletions
diff --git a/test/MC/Mips/mips64shift.ll b/test/MC/Mips/mips64shift.ll
index e1c1857..99cac7b 100644
--- a/test/MC/Mips/mips64shift.ll
+++ b/test/MC/Mips/mips64shift.ll
@@ -1,5 +1,8 @@
-; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler %s -o - | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
+; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler %s -o - \
+; RUN: | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
+; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - \
+; RUN: | llvm-objdump -disassemble -triple mips64el - | FileCheck %s
define i64 @f3(i64 %a0) nounwind readnone {
entry: