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| author | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
| commit | dce4a407a24b04eebc6a376f8e62b41aaa7b071f (patch) | |
| tree | dcebc53f2b182f145a2e659393bf9a0472cedf23 /test/MC/Mips | |
| parent | 220b921aed042f9e520c26cffd8282a94c66c3d5 (diff) | |
| download | external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.zip external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.gz external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.bz2 | |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
Diffstat (limited to 'test/MC/Mips')
104 files changed, 4217 insertions, 2958 deletions
diff --git a/test/MC/Mips/cpload-bad.s b/test/MC/Mips/cpload-bad.s new file mode 100644 index 0000000..7d186f6 --- /dev/null +++ b/test/MC/Mips/cpload-bad.s @@ -0,0 +1,15 @@ +# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1 +# RUN: FileCheck %s < %t1 -check-prefix=ASM + + .text + .option pic2 + .set reorder + .cpload $25 +# ASM: :[[@LINE-1]]:9: warning: .cpload in reorder section + .set noreorder + .cpload $32 +# ASM: :[[@LINE-1]]:17: error: invalid register + .cpload $foo +# ASM: :[[@LINE-1]]:17: error: expected register containing function address + .cpload bar +# ASM: :[[@LINE-1]]:17: error: expected register containing function address diff --git a/test/MC/Mips/cpload.s b/test/MC/Mips/cpload.s new file mode 100644 index 0000000..bc5e797 --- /dev/null +++ b/test/MC/Mips/cpload.s @@ -0,0 +1,33 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -filetype=obj -o -| \ +# RUN: llvm-objdump -d -r -arch=mips - | \ +# RUN: FileCheck %s -check-prefix=OBJ + +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -filetype=obj -o -| \ +# RUN: llvm-objdump -d -r -arch=mips - | \ +# RUN: FileCheck %s -check-prefix=OBJ64 + +# ASM: .text +# ASM: .option pic2 +# ASM: .set noreorder +# ASM: .cpload $25 +# ASM: .set reorder + +# OBJ: .text +# OBJ: lui $gp, 0 +# OBJ: R_MIPS_HI16 _gp_disp +# OBJ: addiu $gp, $gp, 0 +# OBJ: R_MIPS_LO16 _gp_disp +# OBJ: addu $gp, $gp, $25 + +# OBJ64: .text +# OBJ64-NOT: lui $gp, 0 +# OBJ64-NOT: addiu $gp, $gp, 0 +# OBJ64-NOT: addu $gp, $gp, $25 + + .text + .option pic2 + .set noreorder + .cpload $25 + .set reorder diff --git a/test/MC/Mips/cpsetup.s b/test/MC/Mips/cpsetup.s index dbdcaab..a21a1e3 100644 --- a/test/MC/Mips/cpsetup.s +++ b/test/MC/Mips/cpsetup.s @@ -1,36 +1,78 @@ +# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+o32 -filetype=obj -o - %s | \ +# RUN: llvm-objdump -d -r -arch=mips64 - | \ +# RUN: FileCheck -check-prefix=O32 %s + # RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+o32 %s | \ -# RUN: FileCheck -check-prefix=ANY -check-prefix=O32 %s +# RUN: FileCheck -check-prefix=ASM %s + +# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+n32 -filetype=obj -o - %s | \ +# RUN: llvm-objdump -d -r -arch=mips64 - | \ +# RUN: FileCheck -check-prefix=NXX -check-prefix=N32 %s + # RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+n32 %s | \ -# RUN: FileCheck -check-prefix=ANY -check-prefix=NXX -check-prefix=N32 %s -# RUN: llvm-mc -triple mips64-unknown-unknown %s | \ -# RUN: FileCheck -check-prefix=ANY -check-prefix=NXX -check-prefix=N64 %s +# RUN: FileCheck -check-prefix=ASM %s -# TODO: !PIC -> no output +# RUN: llvm-mc -triple mips64-unknown-unknown %s -filetype=obj -o - | \ +# RUN: llvm-objdump -d -r -arch=mips64 - | \ +# RUN: FileCheck -check-prefix=NXX -check-prefix=N64 %s + +# RUN: llvm-mc -triple mips64-unknown-unknown %s | \ +# RUN: FileCheck -check-prefix=ASM %s .text .option pic2 t1: .cpsetup $25, 8, __cerror -# ANY-LABEL: t1: # O32-NOT: __cerror +# FIXME: Direct object emission for N32 is still under development. +# N32 doesn't allow 3 operations to be specified in the same relocation +# record like N64 does. + # NXX: sd $gp, 8($sp) -# NXX: lui $gp, %hi(%neg(%gp_rel(__cerror))) -# NXX: addiu $gp, $gp, %lo(%neg(%gp_rel(__cerror))) +# NXX: lui $gp, 0 +# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror +# NXX: addiu $gp, $gp, 0 +# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror # N32: addu $gp, $gp, $25 # N64: daddu $gp, $gp, $25 +# ASM: .cpsetup $25, 8, __cerror + t2: -# ANY-LABEL: t2: .cpsetup $25, $2, __cerror # O32-NOT: __cerror +# FIXME: Direct object emission for N32 is still under development. +# N32 doesn't allow 3 operations to be specified in the same relocation +# record like N64 does. + # NXX: move $2, $gp -# NXX: lui $gp, %hi(%neg(%gp_rel(__cerror))) -# NXX: addiu $gp, $gp, %lo(%neg(%gp_rel(__cerror))) +# NXX: lui $gp, 0 +# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 __cerror +# NXX: addiu $gp, $gp, 0 +# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 __cerror # N32: addu $gp, $gp, $25 # N64: daddu $gp, $gp, $25 + +# ASM: .cpsetup $25, $2, __cerror + +t3: + .option pic0 + nop + .cpsetup $25, 8, __cerror + nop + +# Testing that .cpsetup expands to nothing in this case +# by checking that the next instruction after the first +# nop is also a 'nop'. +# NXX: nop +# NXX-NEXT: nop + +# ASM: nop +# ASM: .cpsetup $25, 8, __cerror +# ASM: nop diff --git a/test/MC/Mips/elf-N64.s b/test/MC/Mips/elf-N64.s index 3c01803..bf6ebd7 100644 --- a/test/MC/Mips/elf-N64.s +++ b/test/MC/Mips/elf-N64.s @@ -1,4 +1,5 @@ // RUN: llvm-mc -filetype=obj -triple=mips64el-pc-linux -mcpu=mips64 %s -o - | llvm-readobj -r | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple=mips64-pc-linux -mcpu=mips64 %s -o - | llvm-readobj -r | FileCheck %s // Check for N64 relocation production. // Check that the appropriate relocations were created. diff --git a/test/MC/Mips/elf-gprel-32-64.s b/test/MC/Mips/elf-gprel-32-64.s index ae75197..2f5ac66 100644 --- a/test/MC/Mips/elf-gprel-32-64.s +++ b/test/MC/Mips/elf-gprel-32-64.s @@ -1,6 +1,9 @@ // RUN: llvm-mc -filetype=obj -triple=mips64el-pc-linux -mcpu=mips64 %s -o - \ // RUN: | llvm-readobj -r \ // RUN: | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple=mips64-pc-linux -mcpu=mips64 %s -o - \ +// RUN: | llvm-readobj -r \ +// RUN: | FileCheck %s // Check that the appropriate relocations were created. diff --git a/test/MC/Mips/elf_eflags.s b/test/MC/Mips/elf_eflags.s index c789428..8cf4960 100644 --- a/test/MC/Mips/elf_eflags.s +++ b/test/MC/Mips/elf_eflags.s @@ -4,40 +4,79 @@ # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2 %s # MIPSEL-MIPS64R2: Flags [ (0x80001100) +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2-NAN2008 %s +# MIPSEL-MIPS64R2-NAN2008: Flags [ (0x80001500) + # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64 %s # MIPSEL-MIPS64: Flags [ (0x60001100) +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64-NAN2008 %s +# MIPSEL-MIPS64-NAN2008: Flags [ (0x60001500) + # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2 %s # MIPSEL-MIPS32R2: Flags [ (0x70001000) +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2-NAN2008 %s +# MIPSEL-MIPS32R2-NAN2008: Flags [ (0x70001400) + # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32 %s # MIPSEL-MIPS32: Flags [ (0x50001000) +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32-NAN2008 %s +# MIPSEL-MIPS32-NAN2008: Flags [ (0x50001400) + # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32 %s # MIPS64EL-MIPS64R2-N32: Flags [ (0x80000020) +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,n32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32-NAN2008 %s +# MIPS64EL-MIPS64R2-N32-NAN2008: Flags [ (0x80000420) + # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=-n64,n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N32 %s # MIPS64EL-MIPS64-N32: Flags [ (0x60000020) +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=-n64,n32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N32-NAN2008 %s +# MIPS64EL-MIPS64-N32-NAN2008: Flags [ (0x60000420) + # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=n64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N64 %s # MIPS64EL-MIPS64R2-N64: Flags [ (0x80000000) +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=n64,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N64-NAN2008 %s +# MIPS64EL-MIPS64R2-N64-NAN2008: Flags [ (0x80000400) + # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=n64 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N64 %s # MIPS64EL-MIPS64-N64: Flags [ (0x60000000) +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=n64,+nan2008 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N64-NAN2008 %s +# MIPS64EL-MIPS64-N64-NAN2008: Flags [ (0x60000400) + # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,o32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-O32 %s # MIPS64EL-MIPS64R2-O32: Flags [ (0x80001100) +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,o32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-O32-NAN2008 %s +# MIPS64EL-MIPS64R2-O32-NAN2008: Flags [ (0x80001500) + # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips4 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS4 %s # MIPS4: Flags [ (0x30000000) + # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips4 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS4-NAN2008 %s +# MIPS4-NAN2008: Flags [ (0x30000400) + # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=-n64,o32 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-O32 %s # MIPS64EL-MIPS64-O32: Flags [ (0x60001100) - + +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=-n64,o32,+nan2008 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-O32-NAN2008 %s +# MIPS64EL-MIPS64-O32-NAN2008: Flags [ (0x60001500) + # Default ABI for MIPS64 is N64 as opposed to GCC/GAS (N32) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2 %s # MIPS64EL-MIPS64R2: Flags [ (0x80000000) +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-NAN2008 %s +# MIPS64EL-MIPS64R2-NAN2008: Flags [ (0x80000400) + # Default ABI for MIPS64 is N64 as opposed to GCC/GAS (N32) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64 %s # MIPS64EL-MIPS64: Flags [ (0x60000000) + +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-NAN2008 %s +# MIPS64EL-MIPS64-NAN2008: Flags [ (0x60000400) diff --git a/test/MC/Mips/elf_eflags_nan2008.s b/test/MC/Mips/elf_eflags_nan2008.s new file mode 100644 index 0000000..71a22be --- /dev/null +++ b/test/MC/Mips/elf_eflags_nan2008.s @@ -0,0 +1,12 @@ +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o - | \ +# RUN: llvm-readobj -h | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ +# RUN: llvm-mc -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM + +# This *MUST* match the output of gas compiled with the same triple. +# CHECK-OBJ: Flags [ (0x50001400) + +# CHECK-ASM: .nan 2008 + +.nan 2008 diff --git a/test/MC/Mips/elf_eflags_nanlegacy.s b/test/MC/Mips/elf_eflags_nanlegacy.s new file mode 100644 index 0000000..6897ad2 --- /dev/null +++ b/test/MC/Mips/elf_eflags_nanlegacy.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o - | \ +# RUN: llvm-readobj -h | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ +# RUN: llvm-mc -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM + +# This *MUST* match the output of gas compiled with the same triple. +# CHECK-OBJ: Flags [ (0x50001000) + +# CHECK-ASM: .nan 2008 +# CHECK-ASM: .nan legacy + +.nan 2008 +// Let's override the previous directive! +.nan legacy diff --git a/test/MC/Mips/llvm-mc-fixup-endianness.s b/test/MC/Mips/llvm-mc-fixup-endianness.s new file mode 100644 index 0000000..bc6a5d9 --- /dev/null +++ b/test/MC/Mips/llvm-mc-fixup-endianness.s @@ -0,0 +1,6 @@ +# RUN: llvm-mc -show-encoding -mcpu=mips32 -triple mips-unknown-unknown %s | FileCheck -check-prefix=BE %s +# RUN: llvm-mc -show-encoding -mcpu=mips32 -triple mipsel-unknown-unknown %s | FileCheck -check-prefix=LE %s +# + .text + b foo # BE: b foo # encoding: [0x10,0x00,A,A] + # LE: b foo # encoding: [A,A,0x00,0x10] diff --git a/test/MC/Mips/micromips-control-instructions.s b/test/MC/Mips/micromips-control-instructions.s index 8170a9c..aff84c2 100644 --- a/test/MC/Mips/micromips-control-instructions.s +++ b/test/MC/Mips/micromips-control-instructions.s @@ -1,6 +1,6 @@ -# RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips \ +# RUN: llvm-mc %s -triple=mipsel -show-encoding -mcpu=mips32r2 -mattr=micromips \ # RUN: | FileCheck -check-prefix=CHECK-EL %s -# RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips \ +# RUN: llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r2 -mattr=micromips \ # RUN: | FileCheck -check-prefix=CHECK-EB %s # Check that the assembler can handle the documented syntax # for control instructions. @@ -10,7 +10,7 @@ # Little endian #------------------------------------------------------------------------------ # CHECK-EL: break # encoding: [0x00,0x00,0x07,0x00] -# CHECK-EL: break 7, 0 # encoding: [0x07,0x00,0x07,0x00] +# CHECK-EL: break 7 # encoding: [0x07,0x00,0x07,0x00] # CHECK-EL: break 7, 5 # encoding: [0x07,0x00,0x47,0x01] # CHECK-EL: syscall # encoding: [0x00,0x00,0x7c,0x8b] # CHECK-EL: syscall 396 # encoding: [0x8c,0x01,0x7c,0x8b] @@ -28,7 +28,7 @@ # Big endian #------------------------------------------------------------------------------ # CHECK-EB: break # encoding: [0x00,0x00,0x00,0x07] -# CHECK-EB: break 7, 0 # encoding: [0x00,0x07,0x00,0x07] +# CHECK-EB: break 7 # encoding: [0x00,0x07,0x00,0x07] # CHECK-EB: break 7, 5 # encoding: [0x00,0x07,0x01,0x47] # CHECK-EB: syscall # encoding: [0x00,0x00,0x8b,0x7c] # CHECK-EB: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c] diff --git a/test/MC/Mips/micromips-el-fixup-data.s b/test/MC/Mips/micromips-el-fixup-data.s index 2293f63..4753835 100644 --- a/test/MC/Mips/micromips-el-fixup-data.s +++ b/test/MC/Mips/micromips-el-fixup-data.s @@ -2,7 +2,7 @@ # RUN: -mattr=+micromips 2>&1 -filetype=obj > %t.o # RUN: llvm-objdump %t.o -triple mipsel -mattr=+micromips -d | FileCheck %s -# Check that fixup data is writen in the microMIPS specific little endian +# Check that fixup data is written in the microMIPS specific little endian # byte order. .text diff --git a/test/MC/Mips/mips-control-instructions.s b/test/MC/Mips/mips-control-instructions.s index 4a16c53..47da8cc 100644 --- a/test/MC/Mips/mips-control-instructions.s +++ b/test/MC/Mips/mips-control-instructions.s @@ -4,7 +4,7 @@ # RUN: | FileCheck -check-prefix=CHECK64 %s # CHECK32: break # encoding: [0x00,0x00,0x00,0x0d] -# CHECK32: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d] +# CHECK32: break 7 # encoding: [0x00,0x07,0x00,0x0d] # CHECK32: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d] # CHECK32: syscall # encoding: [0x00,0x00,0x00,0x0c] # CHECK32: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c] @@ -37,7 +37,7 @@ # CHECK32: tnei $3, 1023 # encoding: [0x04,0x6e,0x03,0xff] # CHECK64: break # encoding: [0x00,0x00,0x00,0x0d] -# CHECK64: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d] +# CHECK64: break 7 # encoding: [0x00,0x07,0x00,0x0d] # CHECK64: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d] # CHECK64: syscall # encoding: [0x00,0x00,0x00,0x0c] # CHECK64: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c] diff --git a/test/MC/Mips/mips1/invalid-mips2-wrong-error.s b/test/MC/Mips/mips1/invalid-mips2-wrong-error.s new file mode 100644 index 0000000..8e878fe --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips2-wrong-error.s @@ -0,0 +1,16 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldc3 $29,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sc $t7,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc1 $f31,30574($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc3 $12,5835($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips1/invalid-mips2.s b/test/MC/Mips/mips1/invalid-mips2.s new file mode 100644 index 0000000..6c3e80a --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips2.s @@ -0,0 +1,23 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.s $f8,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlti $t6,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tnei $t4,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips1/invalid-mips3-wrong-error.s b/test/MC/Mips/mips1/invalid-mips3-wrong-error.s new file mode 100644 index 0000000..2016e70 --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips3-wrong-error.s @@ -0,0 +1,23 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sc $15,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips1/invalid-mips3.s b/test/MC/Mips/mips1/invalid-mips3.s new file mode 100644 index 0000000..d1b0eec --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips3.s @@ -0,0 +1,65 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsllv $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrlv $s3,$14,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.s $f8,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlti $14,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tnei $12,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips1/invalid-mips4-wrong-error.s b/test/MC/Mips/mips1/invalid-mips4-wrong-error.s new file mode 100644 index 0000000..2016e70 --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips4-wrong-error.s @@ -0,0 +1,23 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sc $15,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips1/invalid-mips4.s b/test/MC/Mips/mips1/invalid-mips4.s new file mode 100644 index 0000000..61aaf58 --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips4.s @@ -0,0 +1,82 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsllv $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrlv $s3,$14,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.s $f8,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f10,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f26,$f20,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlti $14,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tnei $12,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips1/invalid-mips5-wrong-error.s b/test/MC/Mips/mips1/invalid-mips5-wrong-error.s new file mode 100644 index 0000000..74473a3 --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips5-wrong-error.s @@ -0,0 +1,46 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips1/invalid-mips5.s b/test/MC/Mips/mips1/invalid-mips5.s new file mode 100644 index 0000000..1eddf02 --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips5.s @@ -0,0 +1,83 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsllv $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.w.s $f8,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ldxc1 $f8,$s7($t3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$a0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlti $t2,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tnei $t0,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$a2($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips1/valid-xfail.s b/test/MC/Mips/mips1/valid-xfail.s index 2ffeaa9..7696c9e 100644 --- a/test/MC/Mips/mips1/valid-xfail.s +++ b/test/MC/Mips/mips1/valid-xfail.s @@ -2,16 +2,10 @@ # they aren't implemented yet). # This test is set up to XPASS if any instruction generates an encoding. # -# FIXME: Test MIPS-I instead of MIPS32 -# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | not FileCheck %s # CHECK-NOT: encoding # XFAIL: * - .set noat - tlbp - tlbr - tlbwi - tlbwr - lwc0 c0_entrylo,-7321($s2) - lwc3 $10,-32265($k0) - swc0 c0_prid,18904($s3) + .set noat + lwc0 c0_entrylo,-7321($s2) + swc0 c0_prid,18904($s3) diff --git a/test/MC/Mips/mips1/valid.s b/test/MC/Mips/mips1/valid.s index 7fc866a..473e6b9 100644 --- a/test/MC/Mips/mips1/valid.s +++ b/test/MC/Mips/mips1/valid.s @@ -1,85 +1,102 @@ # Instructions that are valid # -# FIXME: Test MIPS-I instead of MIPS32 -# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 | FileCheck %s - .set noat - abs.d $f7,$f25 # CHECK: encoding: - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - cfc1 $s1,$21 - ctc1 $a2,$26 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.s.d $f26,$f8 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - lb $t8,-14515($t2) - lbu $t0,30195($v1) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - mfc1 $a3,$f27 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $s8,$a0 - move $t9,$a2 - mtc1 $s8,$f9 - mthi $s1 - mtlo $sp - mtlo $t9 - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - sb $s6,-19857($t6) - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - xor $s2,$a0,$s8 + .set noat + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + cfc1 $s1,$21 + ctc1 $a2,$26 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.s.d $f26,$f8 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + lb $24,-14515($10) + lbu $8,30195($v1) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwc3 $10,-32265($k0) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + mfc1 $a3,$f27 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $s8,$a0 + move $25,$a2 + mtc1 $s8,$f9 + mthi $s1 + mtlo $sp + mtlo $25 + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + sb $s6,-19857($14) + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swc3 $10,-32265($k0) + swl $15,13694($s3) + swr $s1,-26590($14) + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips2/invalid-mips3-wrong-error.s b/test/MC/Mips/mips2/invalid-mips3-wrong-error.s new file mode 100644 index 0000000..a3f829b --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips3-wrong-error.s @@ -0,0 +1,19 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + dmult $s7,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + dsub $a3,$s6,$a4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldl $t8,-4167($t8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldr $t2,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + scd $t3,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sd $t0,5835($a6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdr $a7,-20423($t0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips2/invalid-mips3.s b/test/MC/Mips/mips2/invalid-mips3.s new file mode 100644 index 0000000..ef498d7 --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips3.s @@ -0,0 +1,48 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsllv $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/invalid-mips32.s b/test/MC/Mips/mips2/invalid-mips32.s new file mode 100644 index 0000000..2975c68 --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips32.s @@ -0,0 +1,32 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + clo $11,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/invalid-mips32r2-xfail.s b/test/MC/Mips/mips2/invalid-mips32r2-xfail.s new file mode 100644 index 0000000..073f777 --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips32r2-xfail.s @@ -0,0 +1,11 @@ +# Instructions that are supposed to be invalid but currently aren't +# This test will XPASS if any insn stops assembling. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2> %t1 +# RUN: not FileCheck %s < %t1 +# XFAIL: * + +# CHECK-NOT: error + .set noat + rdhwr $sp,$11 diff --git a/test/MC/Mips/mips2/invalid-mips32r2.s b/test/MC/Mips/mips2/invalid-mips32r2.s new file mode 100644 index 0000000..37f2eed --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips32r2.s @@ -0,0 +1,59 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $t8,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$t0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msubu $t7,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$t2($t6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$t4($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/invalid-mips4-wrong-error.s b/test/MC/Mips/mips2/invalid-mips4-wrong-error.s new file mode 100644 index 0000000..193f6d7 --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips4-wrong-error.s @@ -0,0 +1,14 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips2/invalid-mips4.s b/test/MC/Mips/mips2/invalid-mips4.s new file mode 100644 index 0000000..e2eb672 --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips4.s @@ -0,0 +1,65 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsllv $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrlv $s3,$14,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/invalid-mips5-wrong-error.s b/test/MC/Mips/mips2/invalid-mips5-wrong-error.s new file mode 100644 index 0000000..0c58c6c --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips5-wrong-error.s @@ -0,0 +1,46 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips2/invalid-mips5.s b/test/MC/Mips/mips2/invalid-mips5.s new file mode 100644 index 0000000..f777ffe --- /dev/null +++ b/test/MC/Mips/mips2/invalid-mips5.s @@ -0,0 +1,66 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsllv $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ldxc1 $f8,$s7($t3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$a0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$a2($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/valid-xfail.s b/test/MC/Mips/mips2/valid-xfail.s deleted file mode 100644 index 2f82f5c..0000000 --- a/test/MC/Mips/mips2/valid-xfail.s +++ /dev/null @@ -1,17 +0,0 @@ -# Instructions that should be valid but currently fail for known reasons (e.g. -# they aren't implemented yet). -# This test is set up to XPASS if any instruction generates an encoding. -# -# FIXME: Test MIPS-II instead of MIPS32 -# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s -# CHECK-NOT: encoding -# XFAIL: * - - .set noat - ldc3 $29,-28645($s1) - lwc3 $10,-32265($k0) - sdc3 $12,5835($t2) - tlbp - tlbr - tlbwi - tlbwr diff --git a/test/MC/Mips/mips2/valid.s b/test/MC/Mips/mips2/valid.s index 1a05040..e3effde 100644 --- a/test/MC/Mips/mips2/valid.s +++ b/test/MC/Mips/mips2/valid.s @@ -1,107 +1,126 @@ # Instructions that are valid # -# FIXME: Test MIPS-II instead of MIPS32 -# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 | FileCheck %s - .set noat - abs.d $f7,$f25 # CHECK: encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - ctc1 $a2,$26 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.s.d $f26,$f8 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - mfc1 $a3,$f27 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $s8,$a0 - move $t9,$a2 - mtc1 $s8,$f9 - mthi $s1 - mtlo $sp - mtlo $t9 - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - xor $s2,$a0,$s8 + .set noat + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + ctc1 $a2,$26 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.s.d $f26,$f8 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + ldc3 $29,-28645($s1) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwc3 $10,-32265($k0) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + mfc1 $a3,$f27 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $s8,$a0 + move $25,$a2 + mtc1 $s8,$f9 + mthi $s1 + mtlo $sp + mtlo $25 + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sdc3 $12,5835($10) + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swc3 $10,-32265($k0) + swl $15,13694($s3) + swr $s1,-26590($14) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips3/invalid-mips4.s b/test/MC/Mips/mips3/invalid-mips4.s new file mode 100644 index 0000000..6e15d79 --- /dev/null +++ b/test/MC/Mips/mips3/invalid-mips4.s @@ -0,0 +1,23 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips3/invalid-mips5-wrong-error.s b/test/MC/Mips/mips3/invalid-mips5-wrong-error.s new file mode 100644 index 0000000..2c0246a --- /dev/null +++ b/test/MC/Mips/mips3/invalid-mips5-wrong-error.s @@ -0,0 +1,46 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips3/invalid-mips5.s b/test/MC/Mips/mips3/invalid-mips5.s new file mode 100644 index 0000000..d25621b --- /dev/null +++ b/test/MC/Mips/mips3/invalid-mips5.s @@ -0,0 +1,25 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ldxc1 $f8,$s7($t3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$a4,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$a6($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips3/valid-xfail.s b/test/MC/Mips/mips3/valid-xfail.s deleted file mode 100644 index 740663e..0000000 --- a/test/MC/Mips/mips3/valid-xfail.s +++ /dev/null @@ -1,15 +0,0 @@ -# Instructions that should be valid but currently fail for known reasons (e.g. -# they aren't implemented yet). -# This test is set up to XPASS if any instruction generates an encoding. -# -# FIXME: Test MIPS-III instead of MIPS64 -# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64 | not FileCheck %s -# CHECK-NOT: encoding -# XFAIL: * - - .set noat - lwc3 $10,-32265($k0) - tlbp - tlbr - tlbwi - tlbwr diff --git a/test/MC/Mips/mips3/valid.s b/test/MC/Mips/mips3/valid.s index dc9b48c..2067666 100644 --- a/test/MC/Mips/mips3/valid.s +++ b/test/MC/Mips/mips3/valid.s @@ -1,145 +1,176 @@ # Instructions that are valid # -# FIXME: Test MIPS-III instead of MIPS64 -# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s +# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 | FileCheck %s - .set noat - abs.d $f7,$f25 # CHECK:encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.l.d $f1,$f3 - ceil.l.s $f18,$f13 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - ctc1 $a2,$26 - cvt.d.l $f4,$f16 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.l.d $f24,$f15 - cvt.l.s $f11,$f29 - cvt.s.d $f26,$f8 - cvt.s.l $f15,$f30 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - dadd $s3,$at,$ra - daddi $sp,$s4,-27705 - daddiu $k0,$s6,-4586 - ddiv $zero,$k0,$s3 - ddivu $zero,$s0,$s1 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - dmfc1 $t4,$f13 - dmtc1 $s0,$f14 - dmult $s7,$t1 - dmultu $a1,$a2 - dsllv $zero,$s4,$t4 - dsrav $gp,$s2,$s3 - dsrlv $s3,$t6,$s4 - dsub $a3,$s6,$t0 - dsubu $a1,$a1,$k0 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - eret - floor.l.d $f26,$f7 - floor.l.s $f12,$f5 - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ld $sp,-28645($s1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - ldl $t8,-4167($t8) - ldr $t6,-30358($s4) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - lld $zero,-14736($ra) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - lwu $s3,-24086($v1) - mfc1 $a3,$f27 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $a0,$a3 - move $s5,$a0 - move $s8,$a0 - move $t9,$a2 - mtc1 $s8,$f9 - mthi $s1 - mtlo $sp - mtlo $t9 - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - round.l.d $f12,$f1 - round.l.s $f25,$f5 - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - scd $t7,-8243($sp) - sd $t4,5835($t2) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sdl $a3,-20961($s8) - sdr $t3,-20423($t4) - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.l.d $f23,$f23 - trunc.l.s $f28,$f31 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - xor $s2,$a0,$s8 + .set noat + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + ctc1 $a2,$26 + cvt.d.l $f4,$f16 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.l $f15,$f30 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + dadd $s3,$at,$ra + daddi $sp,$s4,-27705 + daddiu $k0,$s6,-4586 + daddu $s3,$at,$ra + ddiv $zero,$k0,$s3 + ddivu $zero,$s0,$s1 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + dmfc1 $12,$f13 + dmtc1 $s0,$f14 + dmult $s7,$9 + dmultu $a1,$a2 + dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8] + dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8] + dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbb] + dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbb] + dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] + dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf] + dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] + dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] + dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] + dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] + dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + eret + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ld $sp,-28645($s1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + ldl $24,-4167($24) + ldr $14,-30358($s4) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + lld $zero,-14736($ra) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwu $s3,-24086($v1) + mfc1 $a3,$f27 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $a0,$a3 + move $s5,$a0 + move $s8,$a0 + move $25,$a2 + mtc1 $s8,$f9 + mthi $s1 + mtlo $sp + mtlo $25 + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + round.l.d $f12,$f1 + round.l.s $f25,$f5 + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + scd $15,-8243($sp) + sd $12,5835($10) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sdl $a3,-20961($s8) + sdr $11,-20423($12) + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swl $15,13694($s3) + swr $s1,-26590($14) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips32/invalid-mips32r2-xfail.s b/test/MC/Mips/mips32/invalid-mips32r2-xfail.s index 73fba94..604ddbf 100644 --- a/test/MC/Mips/mips32/invalid-mips32r2-xfail.s +++ b/test/MC/Mips/mips32/invalid-mips32r2-xfail.s @@ -8,12 +8,4 @@ # CHECK-NOT: error .set noat - cvt.l.d $f24,$f15 - cvt.l.s $f11,$f29 - di $s8 - ei $t6 - luxc1 $f19,$s6($s5) - mfhc1 $s8,$f24 - mthc1 $zero,$f16 rdhwr $sp,$11 - suxc1 $f12,$k1($t5) diff --git a/test/MC/Mips/mips32/invalid-mips32r2.s b/test/MC/Mips/mips32/invalid-mips32r2.s index 881f7f1..fa6fe32 100644 --- a/test/MC/Mips/mips32/invalid-mips32r2.s +++ b/test/MC/Mips/mips32/invalid-mips32r2.s @@ -4,20 +4,31 @@ # RUN: 2>%t1 # RUN: FileCheck %s < %t1 - .set noat + .set noat + cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdxc1 $f11,$t2($t6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swxc1 $f19,$t4($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32/invalid-mips64.s b/test/MC/Mips/mips32/invalid-mips64.s new file mode 100644 index 0000000..41040ed --- /dev/null +++ b/test/MC/Mips/mips32/invalid-mips64.s @@ -0,0 +1,9 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips32 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32/valid-xfail.s b/test/MC/Mips/mips32/valid-xfail.s index 65cebd3..d680740 100644 --- a/test/MC/Mips/mips32/valid-xfail.s +++ b/test/MC/Mips/mips32/valid-xfail.s @@ -2,43 +2,37 @@ # they aren't implemented yet). # This test is set up to XPASS if any instruction generates an encoding. # -# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | not FileCheck %s # CHECK-NOT: encoding # XFAIL: * - .set noat - c.eq.d $fcc1,$f15,$f15 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.s $fcc3,$f11,$f8 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.s $fcc7,$f1,$f25 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.s $fcc1,$f30,$f4 - ldc3 $29,-28645($s1) - rorv $t5,$a3,$s5 - sdc3 $12,5835($t2) - tlbp - tlbr - tlbwi - tlbwr + .set noat + c.eq.d $fcc1,$f15,$f15 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.s $fcc3,$f11,$f8 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.s $fcc7,$f1,$f25 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.s $fcc1,$f30,$f4 + rorv $13,$a3,$s5 diff --git a/test/MC/Mips/mips32/valid.s b/test/MC/Mips/mips32/valid.s index 9e83c0f..bc29bdc 100644 --- a/test/MC/Mips/mips32/valid.s +++ b/test/MC/Mips/mips32/valid.s @@ -1,131 +1,147 @@ # Instructions that are valid # -# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 | FileCheck %s .set noat - abs.d $f7,$f25 # CHECK: encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - clo $t3,$a1 - clz $sp,$gp - ctc1 $a2,$26 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.s.d $f26,$f8 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - deret - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - eret - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - madd $s6,$t5 - madd $zero,$t1 - maddu $s3,$gp - maddu $t8,$s2 - mfc0 $a2,$14,1 - mfc1 $a3,$f27 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $s8,$a0 - move $t9,$a2 - movf $gp,$t0,$fcc7 - movf.d $f6,$f11,$fcc5 - movf.s $f23,$f5,$fcc6 - movn $v1,$s1,$s0 - movn.d $f27,$f21,$k0 - movn.s $f12,$f0,$s7 - movt $zero,$s4,$fcc5 - movt.d $f0,$f2,$fcc0 - movt.s $f30,$f2,$fcc1 - movz $a1,$s6,$t1 - movz.d $f12,$f29,$t1 - movz.s $f25,$f7,$v1 - msub $s7,$k1 - msubu $t7,$a1 - mtc0 $t1,$29,3 - mtc1 $s8,$f9 - mthi $s1 - mtlo $sp - mtlo $t9 - mul $s0,$s4,$at - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - xor $s2,$a0,$s8 + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + clo $11,$a1 + clz $sp,$gp + ctc1 $a2,$26 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.s.d $f26,$f8 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + deret + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + eret + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + madd $s6,$13 + madd $zero,$9 + maddu $s3,$gp + maddu $24,$s2 + mfc0 $a2,$14,1 + mfc1 $a3,$f27 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + msub $s7,$k1 + msubu $15,$a1 + mtc0 $9,$29,3 + mtc1 $s8,$f9 + mthi $s1 + mtlo $sp + mtlo $25 + mul $s0,$s4,$at + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swl $15,13694($s3) + swr $s1,-26590($14) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips32r2/invalid-mips64r2.s b/test/MC/Mips/mips32r2/invalid-mips64r2.s new file mode 100644 index 0000000..293e58e --- /dev/null +++ b/test/MC/Mips/mips32r2/invalid-mips64r2.s @@ -0,0 +1,10 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding \ +# RUN: -mcpu=mips32r2 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + diff --git a/test/MC/Mips/mips32r2/valid-xfail.s b/test/MC/Mips/mips32r2/valid-xfail.s index 623c7f6..ef02d51 100644 --- a/test/MC/Mips/mips32r2/valid-xfail.s +++ b/test/MC/Mips/mips32r2/valid-xfail.s @@ -6,310 +6,304 @@ # CHECK-NOT: encoding # XFAIL: * - .set noat - abs.ps $f22,$f8 - absq_s.ph $t0,$a0 - absq_s.qb $t7,$s1 - absq_s.w $s3,$ra - add.ps $f25,$f27,$f13 - addq.ph $s1,$t7,$at - addq_s.ph $s3,$s6,$s2 - addq_s.w $a2,$t0,$at - addqh.ph $s4,$t6,$s1 - addqh.w $s7,$s7,$k1 - addqh_r.ph $sp,$t9,$s8 - addqh_r.w $t0,$v1,$zero - addsc $s8,$t7,$t4 - addu.ph $a2,$t6,$s3 - addu.qb $s6,$v1,$v1 - addu_s.ph $a3,$s3,$gp - addu_s.qb $s4,$s8,$s1 - adduh.qb $a1,$a1,$at - adduh_r.qb $a0,$t1,$t4 - addwc $k0,$s6,$s7 - alnv.ps $f12,$f18,$f30,$t4 - and.v $w10,$w25,$w29 - bitrev $t6,$at - bmnz.v $w15,$w2,$w28 - bmz.v $w13,$w11,$w21 - bsel.v $w28,$w7,$w0 - c.eq.d $fcc1,$f15,$f15 - c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 - c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 - c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 - ceil.l.d $f1,$f3 - ceil.l.s $f18,$f13 - cfcmsa $s6,$19 - cmp.eq.ph $s7,$t6 - cmp.le.ph $t0,$t6 - cmp.lt.ph $k0,$sp - cmpgdu.eq.qb $s3,$zero,$k0 - cmpgdu.le.qb $v1,$t7,$s2 - cmpgdu.lt.qb $s0,$gp,$sp - cmpgu.eq.qb $t6,$s6,$s8 - cmpgu.le.qb $t1,$a3,$s4 - cmpgu.lt.qb $sp,$at,$t0 - cmpu.eq.qb $v0,$t8 - cmpu.le.qb $s1,$a1 - cmpu.lt.qb $at,$a3 - ctcmsa $31,$s7 - cvt.d.l $f4,$f16 - cvt.ps.s $f3,$f18,$f19 - cvt.s.l $f15,$f30 - cvt.s.pl $f30,$f1 - cvt.s.pu $f14,$f25 - dmt $k0 - dpa.w.ph $ac1,$s7,$k0 - dpaq_s.w.ph $ac2,$a0,$t5 - dpaq_sa.l.w $ac0,$a2,$t6 - dpaqx_s.w.ph $ac3,$a0,$t8 - dpaqx_sa.w.ph $ac1,$zero,$s5 - dpau.h.qbl $ac1,$t2,$t8 - dpau.h.qbr $ac1,$s7,$s6 - dpax.w.ph $ac3,$a0,$k0 - dps.w.ph $ac1,$a3,$a1 - dpsq_s.w.ph $ac0,$gp,$k0 - dpsq_sa.l.w $ac0,$a3,$t7 - dpsqx_s.w.ph $ac3,$t5,$a3 - dpsqx_sa.w.ph $ac3,$sp,$s2 - dpsu.h.qbl $ac2,$t6,$t2 - dpsu.h.qbr $ac2,$a1,$s6 - dpsx.w.ph $ac0,$s7,$gp - dvpe $s6 - emt $t0 - evpe $v0 - extpdpv $s6,$ac0,$s8 - extpv $t5,$ac0,$t6 - extrv.w $t0,$ac3,$at - extrv_r.w $t0,$ac1,$s6 - extrv_rs.w $gp,$ac1,$s6 - extrv_s.h $s2,$ac1,$t6 - fclass.d $w14,$w27 - fclass.w $w19,$w28 - fexupl.d $w10,$w29 - fexupl.w $w12,$w27 - fexupr.d $w31,$w15 - fexupr.w $w29,$w12 - ffint_s.d $w1,$w30 - ffint_s.w $w16,$w14 - ffint_u.d $w23,$w18 - ffint_u.w $w19,$w12 - ffql.d $w2,$w3 - ffql.w $w9,$w0 - ffqr.d $w25,$w24 - ffqr.w $w10,$w6 - fill.b $w9,$v1 - fill.h $w9,$t0 - fill.w $w31,$t7 - flog2.d $w12,$w16 - flog2.w $w19,$w23 - floor.l.d $f26,$f7 - floor.l.s $f12,$f5 - fork $s2,$t0,$a0 - frcp.d $w12,$w4 - frcp.w $w30,$w8 - frint.d $w20,$w8 - frint.w $w11,$w29 - frsqrt.d $w29,$w2 - frsqrt.w $w9,$w8 - fsqrt.d $w3,$w1 - fsqrt.w $w5,$w15 - ftint_s.d $w31,$w26 - ftint_s.w $w27,$w14 - ftint_u.d $w5,$w31 - ftint_u.w $w12,$w29 - ftrunc_s.d $w4,$w22 - ftrunc_s.w $w24,$w7 - ftrunc_u.d $w20,$w25 - ftrunc_u.w $w7,$w26 - insv $s2,$at - iret - lbe $t6,122($t1) - lbue $t3,-108($t2) - lbux $t1,$t6($v0) - ldc3 $29,-28645($s1) - lhe $s6,219($v1) - lhue $gp,118($t3) - lhx $sp,$k0($t7) - lle $gp,-237($ra) - lwe $ra,-145($t6) - lwle $t3,-42($t3) - lwre $sp,-152($t8) - lwx $t4,$t4($s4) - madd.ps $f22,$f3,$f14,$f3 - maq_s.w.phl $ac2,$t9,$t3 - maq_s.w.phr $ac0,$t2,$t9 - maq_sa.w.phl $ac3,$a1,$v1 - maq_sa.w.phr $ac1,$at,$t2 - mfgc0 $s6,c0_datahi1 - mflo $t1,$ac2 - modsub $a3,$t4,$a3 - mov.ps $f22,$f17 - move.v $w8,$w17 - movf.ps $f10,$f28,$fcc6 - movn.ps $f31,$f31,$s3 - movt.ps $f20,$f25,$fcc2 - movz.ps $f18,$f17,$ra - msub $ac2,$sp,$t6 - msub.ps $f12,$f14,$f29,$f17 - msubu $ac2,$a1,$t8 - mtc0 $t1,c0_datahi1 - mtgc0 $s4,$21,7 - mthi $v0,$ac1 - mthlip $a3,$ac0 - mul.ph $s4,$t8,$s0 - mul.ps $f14,$f0,$f16 - mul_s.ph $t2,$t6,$t7 - muleq_s.w.phl $t3,$s4,$s4 - muleq_s.w.phr $s6,$a0,$s8 - muleu_s.ph.qbl $a2,$t6,$t0 - muleu_s.ph.qbr $a1,$ra,$t1 - mulq_rs.ph $s2,$t6,$t7 - mulq_rs.w $at,$s4,$t9 - mulq_s.ph $s0,$k1,$t7 - mulq_s.w $t1,$a3,$s0 - mulsa.w.ph $ac1,$s4,$s6 - mulsaq_s.w.ph $ac0,$ra,$s2 - neg.ps $f19,$f13 - nloc.b $w12,$w30 - nloc.d $w16,$w7 - nloc.h $w21,$w17 - nloc.w $w17,$w16 - nlzc.b $w12,$w7 - nlzc.d $w14,$w14 - nlzc.h $w24,$w24 - nlzc.w $w10,$w4 - nmadd.ps $f27,$f4,$f9,$f25 - nmsub.ps $f6,$f12,$f14,$f17 - nor.v $w20,$w20,$w15 - or.v $w13,$w23,$w12 - packrl.ph $ra,$t8,$t6 - pcnt.b $w30,$w15 - pcnt.d $w5,$w16 - pcnt.h $w20,$w24 - pcnt.w $w22,$w20 - pick.ph $ra,$a2,$gp - pick.qb $t3,$a0,$gp - pll.ps $f25,$f9,$f30 - plu.ps $f1,$f26,$f29 - preceq.w.phl $s8,$gp - preceq.w.phr $s5,$t7 - precequ.ph.qbl $s7,$ra - precequ.ph.qbla $a0,$t1 - precequ.ph.qbr $ra,$s3 - precequ.ph.qbra $t8,$t0 - preceu.ph.qbl $sp,$t0 - preceu.ph.qbla $s6,$t3 - preceu.ph.qbr $gp,$s1 - preceu.ph.qbra $k1,$s0 - precr.qb.ph $v0,$t4,$s8 - precrq.ph.w $t6,$s8,$t8 - precrq.qb.ph $a2,$t4,$t4 - precrq_rs.ph.w $a1,$k0,$a3 - precrqu_s.qb.ph $zero,$gp,$s5 - pul.ps $f9,$f30,$f26 - puu.ps $f24,$f9,$f2 - raddu.w.qb $t9,$s3 - rdpgpr $s3,$t1 - recip.d $f19,$f6 - recip.s $f3,$f30 - repl.ph $at,-307 - replv.ph $v1,$s7 - replv.qb $t9,$t4 - rorv $t5,$a3,$s5 - round.l.d $f12,$f1 - round.l.s $f25,$f5 - rsqrt.d $f3,$f28 - rsqrt.s $f4,$f8 - sbe $s7,33($s1) - sce $sp,189($t2) - sdc3 $12,5835($t2) - she $t8,105($v0) - shilo $ac1,26 - shilov $ac2,$t2 - shllv.ph $t2,$s0,$s0 - shllv.qb $gp,$v1,$zero - shllv_s.ph $k1,$at,$t5 - shllv_s.w $s1,$ra,$k0 - shrav.ph $t9,$s2,$s1 - shrav.qb $zero,$t8,$t3 - shrav_r.ph $s3,$t3,$t9 - shrav_r.qb $a0,$sp,$s5 - shrav_r.w $s7,$s4,$s6 - shrlv.ph $t6,$t2,$t1 - shrlv.qb $a2,$s2,$t3 - sub.ps $f5,$f14,$f26 - subq.ph $ra,$t1,$s8 - subq_s.ph $t5,$s8,$s5 - subq_s.w $k1,$a2,$a3 - subqh.ph $t2,$at,$t1 - subqh.w $v0,$a2,$zero - subqh_r.ph $a0,$t4,$s6 - subqh_r.w $t2,$a2,$gp - subu.ph $t1,$s6,$s4 - subu.qb $s6,$a2,$s6 - subu_s.ph $v1,$a1,$s3 - subu_s.qb $s1,$at,$ra - subuh.qb $zero,$gp,$gp - subuh_r.qb $s4,$s8,$s6 - swe $t8,94($k0) - swle $v1,-209($gp) - swre $k0,-202($s2) - synci 20023($s0) - tlbginv - tlbginvf - tlbgp - tlbgr - tlbgwi - tlbgwr - tlbinv - tlbinvf - tlbp - tlbr - tlbwi - tlbwr - trunc.l.d $f23,$f23 - trunc.l.s $f28,$f31 - wrpgpr $zero,$t5 - xor.v $w20,$w21,$w30 - yield $v1,$s0 + .set noat + abs.ps $f22,$f8 + absq_s.ph $8,$a0 + absq_s.qb $15,$s1 + absq_s.w $s3,$ra + add.ps $f25,$f27,$f13 + addq.ph $s1,$15,$at + addq_s.ph $s3,$s6,$s2 + addq_s.w $a2,$8,$at + addqh.ph $s4,$14,$s1 + addqh.w $s7,$s7,$k1 + addqh_r.ph $sp,$25,$s8 + addqh_r.w $8,$v1,$zero + addsc $s8,$15,$12 + addu.ph $a2,$14,$s3 + addu.qb $s6,$v1,$v1 + addu_s.ph $a3,$s3,$gp + addu_s.qb $s4,$s8,$s1 + adduh.qb $a1,$a1,$at + adduh_r.qb $a0,$9,$12 + addwc $k0,$s6,$s7 + alnv.ps $f12,$f18,$f30,$12 + and.v $w10,$w25,$w29 + bitrev $14,$at + bmnz.v $w15,$w2,$w28 + bmz.v $w13,$w11,$w21 + bsel.v $w28,$w7,$w0 + c.eq.d $fcc1,$f15,$f15 + c.eq.ps $fcc5,$f0,$f9 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.ps $fcc6,$f11,$f11 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.ps $fcc1,$f7,$f20 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.ps $f19,$f5 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.ps $f1,$f26 + c.nge.s $fcc3,$f11,$f8 + c.ngl.ps $f21,$f30 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.ps $fcc7,$f12,$f20 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.ps $fcc5,$f30,$f6 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.ps $fcc7,$f21,$f8 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.ps $fcc3,$f7,$f16 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.ps $fcc6,$f31,$f14 + c.seq.s $fcc7,$f1,$f25 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.ps $fcc1,$f5,$f29 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.ps $fcc6,$f17,$f3 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.ps $fcc7,$f14,$f0 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.ps $fcc4,$f2,$f26 + c.un.s $fcc1,$f30,$f4 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + cfcmsa $s6,$19 + cmp.eq.ph $s7,$14 + cmp.le.ph $8,$14 + cmp.lt.ph $k0,$sp + cmpgdu.eq.qb $s3,$zero,$k0 + cmpgdu.le.qb $v1,$15,$s2 + cmpgdu.lt.qb $s0,$gp,$sp + cmpgu.eq.qb $14,$s6,$s8 + cmpgu.le.qb $9,$a3,$s4 + cmpgu.lt.qb $sp,$at,$8 + cmpu.eq.qb $v0,$24 + cmpu.le.qb $s1,$a1 + cmpu.lt.qb $at,$a3 + ctcmsa $31,$s7 + cvt.d.l $f4,$f16 + cvt.ps.s $f3,$f18,$f19 + cvt.s.l $f15,$f30 + cvt.s.pl $f30,$f1 + cvt.s.pu $f14,$f25 + dmt $k0 + dpa.w.ph $ac1,$s7,$k0 + dpaq_s.w.ph $ac2,$a0,$13 + dpaq_sa.l.w $ac0,$a2,$14 + dpaqx_s.w.ph $ac3,$a0,$24 + dpaqx_sa.w.ph $ac1,$zero,$s5 + dpau.h.qbl $ac1,$10,$24 + dpau.h.qbr $ac1,$s7,$s6 + dpax.w.ph $ac3,$a0,$k0 + dps.w.ph $ac1,$a3,$a1 + dpsq_s.w.ph $ac0,$gp,$k0 + dpsq_sa.l.w $ac0,$a3,$15 + dpsqx_s.w.ph $ac3,$13,$a3 + dpsqx_sa.w.ph $ac3,$sp,$s2 + dpsu.h.qbl $ac2,$14,$10 + dpsu.h.qbr $ac2,$a1,$s6 + dpsx.w.ph $ac0,$s7,$gp + dvpe $s6 + emt $8 + evpe $v0 + extpdpv $s6,$ac0,$s8 + extpv $13,$ac0,$14 + extrv.w $8,$ac3,$at + extrv_r.w $8,$ac1,$s6 + extrv_rs.w $gp,$ac1,$s6 + extrv_s.h $s2,$ac1,$14 + fclass.d $w14,$w27 + fclass.w $w19,$w28 + fexupl.d $w10,$w29 + fexupl.w $w12,$w27 + fexupr.d $w31,$w15 + fexupr.w $w29,$w12 + ffint_s.d $w1,$w30 + ffint_s.w $w16,$w14 + ffint_u.d $w23,$w18 + ffint_u.w $w19,$w12 + ffql.d $w2,$w3 + ffql.w $w9,$w0 + ffqr.d $w25,$w24 + ffqr.w $w10,$w6 + fill.b $w9,$v1 + fill.h $w9,$8 + fill.w $w31,$15 + flog2.d $w12,$w16 + flog2.w $w19,$w23 + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + fork $s2,$8,$a0 + frcp.d $w12,$w4 + frcp.w $w30,$w8 + frint.d $w20,$w8 + frint.w $w11,$w29 + frsqrt.d $w29,$w2 + frsqrt.w $w9,$w8 + fsqrt.d $w3,$w1 + fsqrt.w $w5,$w15 + ftint_s.d $w31,$w26 + ftint_s.w $w27,$w14 + ftint_u.d $w5,$w31 + ftint_u.w $w12,$w29 + ftrunc_s.d $w4,$w22 + ftrunc_s.w $w24,$w7 + ftrunc_u.d $w20,$w25 + ftrunc_u.w $w7,$w26 + insv $s2,$at + iret + lbe $14,122($9) + lbue $11,-108($10) + lbux $9,$14($v0) + lhe $s6,219($v1) + lhue $gp,118($11) + lhx $sp,$k0($15) + lle $gp,-237($ra) + lwe $ra,-145($14) + lwle $11,-42($11) + lwre $sp,-152($24) + lwx $12,$12($s4) + madd.ps $f22,$f3,$f14,$f3 + maq_s.w.phl $ac2,$25,$11 + maq_s.w.phr $ac0,$10,$25 + maq_sa.w.phl $ac3,$a1,$v1 + maq_sa.w.phr $ac1,$at,$10 + mfgc0 $s6,c0_datahi1 + mflo $9,$ac2 + modsub $a3,$12,$a3 + mov.ps $f22,$f17 + move.v $w8,$w17 + movf.ps $f10,$f28,$fcc6 + movn.ps $f31,$f31,$s3 + movt.ps $f20,$f25,$fcc2 + movz.ps $f18,$f17,$ra + msub $ac2,$sp,$14 + msub.ps $f12,$f14,$f29,$f17 + msubu $ac2,$a1,$24 + mtc0 $9,c0_datahi1 + mtgc0 $s4,$21,7 + mthi $v0,$ac1 + mthlip $a3,$ac0 + mul.ph $s4,$24,$s0 + mul.ps $f14,$f0,$f16 + mul_s.ph $10,$14,$15 + muleq_s.w.phl $11,$s4,$s4 + muleq_s.w.phr $s6,$a0,$s8 + muleu_s.ph.qbl $a2,$14,$8 + muleu_s.ph.qbr $a1,$ra,$9 + mulq_rs.ph $s2,$14,$15 + mulq_rs.w $at,$s4,$25 + mulq_s.ph $s0,$k1,$15 + mulq_s.w $9,$a3,$s0 + mulsa.w.ph $ac1,$s4,$s6 + mulsaq_s.w.ph $ac0,$ra,$s2 + neg.ps $f19,$f13 + nloc.b $w12,$w30 + nloc.d $w16,$w7 + nloc.h $w21,$w17 + nloc.w $w17,$w16 + nlzc.b $w12,$w7 + nlzc.d $w14,$w14 + nlzc.h $w24,$w24 + nlzc.w $w10,$w4 + nmadd.ps $f27,$f4,$f9,$f25 + nmsub.ps $f6,$f12,$f14,$f17 + nor.v $w20,$w20,$w15 + or.v $w13,$w23,$w12 + packrl.ph $ra,$24,$14 + pcnt.b $w30,$w15 + pcnt.d $w5,$w16 + pcnt.h $w20,$w24 + pcnt.w $w22,$w20 + pick.ph $ra,$a2,$gp + pick.qb $11,$a0,$gp + pll.ps $f25,$f9,$f30 + plu.ps $f1,$f26,$f29 + preceq.w.phl $s8,$gp + preceq.w.phr $s5,$15 + precequ.ph.qbl $s7,$ra + precequ.ph.qbla $a0,$9 + precequ.ph.qbr $ra,$s3 + precequ.ph.qbra $24,$8 + preceu.ph.qbl $sp,$8 + preceu.ph.qbla $s6,$11 + preceu.ph.qbr $gp,$s1 + preceu.ph.qbra $k1,$s0 + precr.qb.ph $v0,$12,$s8 + precrq.ph.w $14,$s8,$24 + precrq.qb.ph $a2,$12,$12 + precrq_rs.ph.w $a1,$k0,$a3 + precrqu_s.qb.ph $zero,$gp,$s5 + pul.ps $f9,$f30,$f26 + puu.ps $f24,$f9,$f2 + raddu.w.qb $25,$s3 + rdpgpr $s3,$9 + recip.d $f19,$f6 + recip.s $f3,$f30 + repl.ph $at,-307 + replv.ph $v1,$s7 + replv.qb $25,$12 + rorv $13,$a3,$s5 + round.l.d $f12,$f1 + round.l.s $f25,$f5 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 + sbe $s7,33($s1) + sce $sp,189($10) + she $24,105($v0) + shilo $ac1,26 + shilov $ac2,$10 + shllv.ph $10,$s0,$s0 + shllv.qb $gp,$v1,$zero + shllv_s.ph $k1,$at,$13 + shllv_s.w $s1,$ra,$k0 + shrav.ph $25,$s2,$s1 + shrav.qb $zero,$24,$11 + shrav_r.ph $s3,$11,$25 + shrav_r.qb $a0,$sp,$s5 + shrav_r.w $s7,$s4,$s6 + shrlv.ph $14,$10,$9 + shrlv.qb $a2,$s2,$11 + sub.ps $f5,$f14,$f26 + subq.ph $ra,$9,$s8 + subq_s.ph $13,$s8,$s5 + subq_s.w $k1,$a2,$a3 + subqh.ph $10,$at,$9 + subqh.w $v0,$a2,$zero + subqh_r.ph $a0,$12,$s6 + subqh_r.w $10,$a2,$gp + subu.ph $9,$s6,$s4 + subu.qb $s6,$a2,$s6 + subu_s.ph $v1,$a1,$s3 + subu_s.qb $s1,$at,$ra + subuh.qb $zero,$gp,$gp + subuh_r.qb $s4,$s8,$s6 + swe $24,94($k0) + swle $v1,-209($gp) + swre $k0,-202($s2) + synci 20023($s0) + tlbginv + tlbginvf + tlbgp + tlbgr + tlbgwi + tlbgwr + tlbinv + tlbinvf + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + wrpgpr $zero,$13 + xor.v $w20,$w21,$w30 + yield $v1,$s0 diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s index 3e9a1d3..26f8b6b 100644 --- a/test/MC/Mips/mips32r2/valid.s +++ b/test/MC/Mips/mips32r2/valid.s @@ -3,154 +3,173 @@ # RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s .set noat - abs.d $f7,$f25 # CHECK: encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - clo $t3,$a1 - clz $sp,$gp - ctc1 $a2,$26 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.l.d $f24,$f15 - cvt.l.s $f11,$f29 - cvt.s.d $f26,$f8 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - deret - di $s8 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - ei $t6 - eret - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - ldxc1 $f8,$s7($t7) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - luxc1 $f19,$s6($s5) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - lwxc1 $f12,$s1($s8) - madd $s6,$t5 - madd $zero,$t1 - madd.d $f18,$f19,$f26,$f20 - madd.s $f1,$f31,$f19,$f25 - maddu $s3,$gp - maddu $t8,$s2 - mfc0 $a2,$14,1 - mfc1 $a3,$f27 - mfhc1 $s8,$f24 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $s8,$a0 - move $t9,$a2 - movf $gp,$t0,$fcc7 - movf.d $f6,$f11,$fcc5 - movf.s $f23,$f5,$fcc6 - movn $v1,$s1,$s0 - movn.d $f27,$f21,$k0 - movn.s $f12,$f0,$s7 - movt $zero,$s4,$fcc5 - movt.d $f0,$f2,$fcc0 - movt.s $f30,$f2,$fcc1 - movz $a1,$s6,$t1 - movz.d $f12,$f29,$t1 - movz.s $f25,$f7,$v1 - msub $s7,$k1 - msub.d $f10,$f1,$f31,$f18 - msub.s $f12,$f19,$f10,$f16 - msubu $t7,$a1 - mtc0 $t1,$29,3 - mtc1 $s8,$f9 - mthc1 $zero,$f16 - mthi $s1 - mtlo $sp - mtlo $t9 - mul $s0,$s4,$at - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nmadd.d $f18,$f9,$f14,$f19 - nmadd.s $f0,$f5,$f25,$f12 - nmsub.d $f30,$f8,$f16,$f30 - nmsub.s $f1,$f24,$f19,$f4 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] - rdhwr $sp,$11 - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sdxc1 $f11,$t2($t6) - seb $t9,$t7 - seh $v1,$t4 - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - suxc1 $f12,$k1($t5) - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - swxc1 $f19,$t4($k0) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - wsbh $k1,$t1 - xor $s2,$a0,$s8 + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + clo $11,$a1 + clz $sp,$gp + ctc1 $a2,$26 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + deret + di $s8 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + ei $14 + eret + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + ldxc1 $f8,$s7($15) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + luxc1 $f19,$s6($s5) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwxc1 $f12,$s1($s8) + madd $s6,$13 + madd $zero,$9 + madd.d $f18,$f19,$f26,$f20 + madd.s $f1,$f31,$f19,$f25 + maddu $s3,$gp + maddu $24,$s2 + mfc0 $a2,$14,1 + mfc1 $a3,$f27 + mfhc1 $s8,$f24 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + msub $s7,$k1 + msub.d $f10,$f1,$f31,$f18 + msub.s $f12,$f19,$f10,$f16 + msubu $15,$a1 + mtc0 $9,$29,3 + mtc1 $s8,$f9 + mthc1 $zero,$f16 + mthi $s1 + mtlo $sp + mtlo $25 + mul $s0,$s4,$at + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nmadd.d $f18,$f9,$f14,$f19 + nmadd.s $f0,$f5,$f25,$f12 + nmsub.d $f30,$f8,$f16,$f30 + nmsub.s $f1,$f24,$f19,$f4 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] + rdhwr $sp,$11 + rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] + rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] + rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sdxc1 $f11,$10($14) + seb $25,$15 + seh $v1,$12 + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + suxc1 $f12,$k1($13) + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swl $15,13694($s3) + swr $s1,-26590($14) + swxc1 $f19,$12($k0) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + wsbh $k1,$9 + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s new file mode 100644 index 0000000..aee068a --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s @@ -0,0 +1,15 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips1.s b/test/MC/Mips/mips32r6/invalid-mips1.s new file mode 100644 index 0000000..aa7d407 --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips1.s @@ -0,0 +1,8 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s new file mode 100644 index 0000000..b799c8e --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s @@ -0,0 +1,20 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + beql $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bgezall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bgezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bgtzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + blezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bltzall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bltzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bnel $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips2.s b/test/MC/Mips/mips32r6/invalid-mips2.s new file mode 100644 index 0000000..0638e78 --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips2.s @@ -0,0 +1,14 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlti $14,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tnei $12,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s new file mode 100644 index 0000000..e416a20 --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s @@ -0,0 +1,16 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips32r6/relocations.s b/test/MC/Mips/mips32r6/relocations.s new file mode 100644 index 0000000..4532e42 --- /dev/null +++ b/test/MC/Mips/mips32r6/relocations.s @@ -0,0 +1,55 @@ +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: | FileCheck %s -check-prefix=CHECK-FIXUP +# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r6 \ +# RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF +#------------------------------------------------------------------------------ +# Check that the assembler can handle the documented syntax for fixups. +#------------------------------------------------------------------------------ +# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16 +# CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16 +# CHECK-FIXUP: beqzc $9, bar # encoding: [0xd9,0b001AAAAA,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2 +# CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2 +# CHECK-FIXUP: balc bar # encoding: [0b111010AA,A,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2 +# CHECK-FIXUP: bc bar # encoding: [0b110010AA,A,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2 +# CHECK-FIXUP: aluipc $2, %pcrel_hi(bar) # encoding: [0xec,0x5f,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar@PCREL_HI16, +# CHECK-FIXUP: kind: fixup_MIPS_PCHI16 +# CHECK-FIXUP: addiu $2, $2, %pcrel_lo(bar) # encoding: [0x24,0x42,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar@PCREL_LO16, +# CHECK-FIXUP: kind: fixup_MIPS_PCLO16 +#------------------------------------------------------------------------------ +# Check that the appropriate relocations were created. +#------------------------------------------------------------------------------ +# CHECK-ELF: Relocations [ +# CHECK-ELF: 0x0 R_MIPS_PC16 bar 0x0 +# CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0 +# CHECK-ELF: 0x8 R_MIPS_PC21_S2 bar 0x0 +# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0 +# CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0 +# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0 +# CHECK-ELF: 0x18 R_MIPS_PCHI16 bar 0x0 +# CHECK-ELF: 0x1C R_MIPS_PCLO16 bar 0x0 +# CHECK-ELF: ] + + beqc $5, $6, bar + bnec $5, $6, bar + beqzc $9, bar + bnezc $9, bar + balc bar + bc bar + aluipc $2, %pcrel_hi(bar) + addiu $2, $2, %pcrel_lo(bar) diff --git a/test/MC/Mips/mips32r6/valid-xfail.s b/test/MC/Mips/mips32r6/valid-xfail.s new file mode 100644 index 0000000..0c911d7 --- /dev/null +++ b/test/MC/Mips/mips32r6/valid-xfail.s @@ -0,0 +1,19 @@ +# Instructions that should be valid but currently fail for known reasons (e.g. +# they aren't implemented yet). +# This test is set up to XPASS if any instruction generates an encoding. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 | not FileCheck %s +# CHECK-NOT: encoding +# XFAIL: * + + .set noat + bovc $0, $2, 4 # TODO: bovc $0, $2, 4 # encoding: [0x20,0x40,0x00,0x01] + bovc $2, $4, 4 # TODO: bovc $2, $4, 4 # encoding: [0x20,0x82,0x00,0x01] + bnvc $0, $2, 4 # TODO: bnvc $0, $2, 4 # encoding: [0x60,0x40,0x00,0x01] + bnvc $2, $4, 4 # TODO: bnvc $2, $4, 4 # encoding: [0x60,0x82,0x00,0x01] + beqc $0, $6, 256 # TODO: beqc $6, $zero, 256 # encoding: [0x20,0xc0,0x00,0x40] + beqc $5, $0, 256 # TODO: beqc $5, $zero, 256 # encoding: [0x20,0xa0,0x00,0x40] + beqc $6, $5, 256 # TODO: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40] + bnec $0, $6, 256 # TODO: bnec $6, $zero, 256 # encoding: [0x60,0xc0,0x00,0x40] + bnec $5, $0, 256 # TODO: bnec $5, $zero, 256 # encoding: [0x60,0xa0,0x00,0x40] + bnec $6, $5, 256 # TODO: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40] diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s new file mode 100644 index 0000000..5b4b928 --- /dev/null +++ b/test/MC/Mips/mips32r6/valid.s @@ -0,0 +1,126 @@ +# Instructions that are valid +# +# Branches have some unusual encoding rules in MIPS32r6 so we need to test: +# rs == 0 +# rs != 0 +# rt == 0 +# rt != 0 +# rs < rt +# rs == rt +# rs > rt +# appropriately for each branch instruction +# +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 | FileCheck %s + + .set noat + # FIXME: Add the instructions carried forward from older ISA's + addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19] + align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0] + aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] + aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9] + auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff] + balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8] + bc 14572256 # CHECK: bc 14572256 # encoding: [0xc8,0x37,0x96,0xb8] + bc1eqz $f0,4 # CHECK: bc1eqz $f0, 4 # encoding: [0x45,0x20,0x00,0x01] + bc1eqz $f31,4 # CHECK: bc1eqz $f31, 4 # encoding: [0x45,0x3f,0x00,0x01] + bc1nez $f0,4 # CHECK: bc1nez $f0, 4 # encoding: [0x45,0xa0,0x00,0x01] + bc1nez $f31,4 # CHECK: bc1nez $f31, 4 # encoding: [0x45,0xbf,0x00,0x01] + bc2eqz $0,8 # CHECK: bc2eqz $0, 8 # encoding: [0x49,0x20,0x00,0x02] + bc2eqz $31,8 # CHECK: bc2eqz $31, 8 # encoding: [0x49,0x3f,0x00,0x02] + bc2nez $0,8 # CHECK: bc2nez $0, 8 # encoding: [0x49,0xa0,0x00,0x02] + bc2nez $31,8 # CHECK: bc2nez $31, 8 # encoding: [0x49,0xbf,0x00,0x02] + # beqc requires rs < rt && rs != 0 but we also accept when this is not true. See also bovc + # FIXME: Testcases are in valid-xfail.s at the moment + beqc $5, $6, 256 # CHECK: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40] + beqzalc $2, 1332 # CHECK: beqzalc $2, 1332 # encoding: [0x20,0x02,0x01,0x4d] + # bnec requires rs < rt && rs != 0 but we accept when this is not true. See also bnvc + # FIXME: Testcases are in valid-xfail.s at the moment + bnec $5, $6, 256 # CHECK: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40] + bnezalc $2, 1332 # CHECK: bnezalc $2, 1332 # encoding: [0x60,0x02,0x01,0x4d] + beqzc $5, 72256 # CHECK: beqzc $5, 72256 # encoding: [0xd8,0xa0,0x46,0x90] + bgezalc $2, 1332 # CHECK: bgezalc $2, 1332 # encoding: [0x18,0x42,0x01,0x4d] + bnezc $5, 72256 # CHECK: bnezc $5, 72256 # encoding: [0xf8,0xa0,0x46,0x90] + bltzc $5, 256 # CHECK: bltzc $5, 256 # encoding: [0x5c,0xa5,0x00,0x40] + bgezc $5, 256 # CHECK: bgezc $5, 256 # encoding: [0x58,0xa5,0x00,0x40] + bgtzalc $2, 1332 # CHECK: bgtzalc $2, 1332 # encoding: [0x1c,0x02,0x01,0x4d] + blezc $5, 256 # CHECK: blezc $5, 256 # encoding: [0x58,0x05,0x00,0x40] + bltzalc $2, 1332 # CHECK: bltzalc $2, 1332 # encoding: [0x1c,0x42,0x01,0x4d] + bgtzc $5, 256 # CHECK: bgtzc $5, 256 # encoding: [0x5c,0x05,0x00,0x40] + bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20] + blezalc $2, 1332 # CHECK: blezalc $2, 1332 # encoding: [0x18,0x02,0x01,0x4d] + # bnvc requires that rs >= rt but we accept both. See also bnec + bnvc $0, $0, 4 # CHECK: bnvc $zero, $zero, 4 # encoding: [0x60,0x00,0x00,0x01] + bnvc $2, $0, 4 # CHECK: bnvc $2, $zero, 4 # encoding: [0x60,0x40,0x00,0x01] + bnvc $4, $2, 4 # CHECK: bnvc $4, $2, 4 # encoding: [0x60,0x82,0x00,0x01] + # bovc requires that rs >= rt but we accept both. See also beqc + bovc $0, $0, 4 # CHECK: bovc $zero, $zero, 4 # encoding: [0x20,0x00,0x00,0x01] + bovc $2, $0, 4 # CHECK: bovc $2, $zero, 4 # encoding: [0x20,0x40,0x00,0x01] + bovc $4, $2, 4 # CHECK: bovc $4, $2, 4 # encoding: [0x20,0x82,0x00,0x01] + cmp.f.s $f2,$f3,$f4 # CHECK: cmp.f.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80] + cmp.f.d $f2,$f3,$f4 # CHECK: cmp.f.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80] + cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81] + cmp.un.d $f2,$f3,$f4 # CHECK: cmp.un.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x81] + cmp.eq.s $f2,$f3,$f4 # CHECK: cmp.eq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x82] + cmp.eq.d $f2,$f3,$f4 # CHECK: cmp.eq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x82] + cmp.ueq.s $f2,$f3,$f4 # CHECK: cmp.ueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x83] + cmp.ueq.d $f2,$f3,$f4 # CHECK: cmp.ueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x83] + cmp.olt.s $f2,$f3,$f4 # CHECK: cmp.olt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x84] + cmp.olt.d $f2,$f3,$f4 # CHECK: cmp.olt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x84] + cmp.ult.s $f2,$f3,$f4 # CHECK: cmp.ult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x85] + cmp.ult.d $f2,$f3,$f4 # CHECK: cmp.ult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x85] + cmp.ole.s $f2,$f3,$f4 # CHECK: cmp.ole.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x86] + cmp.ole.d $f2,$f3,$f4 # CHECK: cmp.ole.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x86] + cmp.ule.s $f2,$f3,$f4 # CHECK: cmp.ule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x87] + cmp.ule.d $f2,$f3,$f4 # CHECK: cmp.ule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x87] + cmp.sf.s $f2,$f3,$f4 # CHECK: cmp.sf.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x88] + cmp.sf.d $f2,$f3,$f4 # CHECK: cmp.sf.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x88] + cmp.ngle.s $f2,$f3,$f4 # CHECK: cmp.ngle.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x89] + cmp.ngle.d $f2,$f3,$f4 # CHECK: cmp.ngle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x89] + cmp.seq.s $f2,$f3,$f4 # CHECK: cmp.seq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8a] + cmp.seq.d $f2,$f3,$f4 # CHECK: cmp.seq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8a] + cmp.ngl.s $f2,$f3,$f4 # CHECK: cmp.ngl.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8b] + cmp.ngl.d $f2,$f3,$f4 # CHECK: cmp.ngl.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8b] + cmp.lt.s $f2,$f3,$f4 # CHECK: cmp.lt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8c] + cmp.lt.d $f2,$f3,$f4 # CHECK: cmp.lt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8c] + cmp.nge.s $f2,$f3,$f4 # CHECK: cmp.nge.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8d] + cmp.nge.d $f2,$f3,$f4 # CHECK: cmp.nge.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8d] + cmp.le.s $f2,$f3,$f4 # CHECK: cmp.le.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8e] + cmp.le.d $f2,$f3,$f4 # CHECK: cmp.le.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e] + cmp.ngt.s $f2,$f3,$f4 # CHECK: cmp.ngt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f] + cmp.ngt.d $f2,$f3,$f4 # CHECK: cmp.ngt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f] + div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a] + divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b] + jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00] + jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00] + lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43] + lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43] + mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] + modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb] +# mul $2,$3,$4 # CHECK-TODO: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98] + muh $2,$3,$4 # CHECK: muh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd8] + mulu $2,$3,$4 # CHECK: mulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x99] + muhu $2,$3,$4 # CHECK: muhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd9] + maddf.s $f2,$f3,$f4 # CHECK: maddf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x98] + maddf.d $f2,$f3,$f4 # CHECK: maddf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x98] + msubf.s $f2,$f3,$f4 # CHECK: msubf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x99] + msubf.d $f2,$f3,$f4 # CHECK: msubf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x99] + sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10] + sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10] + seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35] + selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37] + max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d] + max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d] + min.s $f0, $f2, $f4 # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c] + min.d $f0, $f2, $f4 # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c] + maxa.s $f0, $f2, $f4 # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f] + maxa.d $f0, $f2, $f4 # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f] + mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e] + mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e] + seleqz.s $f0, $f2, $f4 # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14] + seleqz.d $f0, $f2, $f4 # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14] + selnez.s $f0, $f2, $f4 # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17] + selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17] + rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a] + rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a] + class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b] + class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b] diff --git a/test/MC/Mips/mips4/invalid-mips5-wrong-error.s b/test/MC/Mips/mips4/invalid-mips5-wrong-error.s new file mode 100644 index 0000000..c6c8968 --- /dev/null +++ b/test/MC/Mips/mips4/invalid-mips5-wrong-error.s @@ -0,0 +1,46 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips4 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips4/invalid-mips5.s b/test/MC/Mips/mips4/invalid-mips5.s new file mode 100644 index 0000000..8c0db00 --- /dev/null +++ b/test/MC/Mips/mips4/invalid-mips5.s @@ -0,0 +1,9 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips4/invalid-mips64.s b/test/MC/Mips/mips4/invalid-mips64.s index e0b69f2..c6245cc 100644 --- a/test/MC/Mips/mips4/invalid-mips64.s +++ b/test/MC/Mips/mips4/invalid-mips64.s @@ -6,7 +6,19 @@ # RUN: FileCheck %s < %t1 .set noat - clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $t8,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msubu $t7,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips4/invalid-mips64r2-xfail.s b/test/MC/Mips/mips4/invalid-mips64r2-xfail.s index 63edb60..a5581fd 100644 --- a/test/MC/Mips/mips4/invalid-mips64r2-xfail.s +++ b/test/MC/Mips/mips4/invalid-mips64r2-xfail.s @@ -8,20 +8,4 @@ # CHECK-NOT: error .set noat - deret - di $s8 - ei $t6 - luxc1 $f19,$s6($s5) - madd $s6,$t5 - madd $zero,$t1 - maddu $s3,$gp - maddu $t8,$s2 - mfc0 $a2,$14,1 - mfhc1 $s8,$f24 - msub $s7,$k1 - msubu $t7,$a1 - mtc0 $t1,$29,3 - mthc1 $zero,$f16 - mul $s0,$s4,$at rdhwr $sp,$11 - suxc1 $f12,$k1($t5) diff --git a/test/MC/Mips/mips4/invalid-mips64r2.s b/test/MC/Mips/mips4/invalid-mips64r2.s index ed2dff8..b259706 100644 --- a/test/MC/Mips/mips4/invalid-mips64r2.s +++ b/test/MC/Mips/mips4/invalid-mips64r2.s @@ -1,22 +1,37 @@ # Instructions that are invalid # -# FIXME: This test should be moved to the mips5 directory when mips5 is supported # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 \ # RUN: 2>%t1 # RUN: FileCheck %s < %t1 .set noat - clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclz $s0,$t9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $t8,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msubu $t7,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($t5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips4/valid-xfail.s b/test/MC/Mips/mips4/valid-xfail.s index baf5c53..ff6f457 100644 --- a/test/MC/Mips/mips4/valid-xfail.s +++ b/test/MC/Mips/mips4/valid-xfail.s @@ -2,53 +2,48 @@ # they aren't implemented yet). # This test is set up to XPASS if any instruction generates an encoding. # -# FIXME: Test MIPS-IV instead of MIPS64 -# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | not FileCheck %s +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | not FileCheck %s # CHECK-NOT: encoding # XFAIL: * - .set noat - c.eq.d $fcc1,$f15,$f15 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.s $fcc3,$f11,$f8 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.s $fcc7,$f1,$f25 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.s $fcc1,$f30,$f4 - madd.d $f18,$f19,$f26,$f20 - madd.s $f1,$f31,$f19,$f25 - msub.d $f10,$f1,$f31,$f18 - msub.s $f12,$f19,$f10,$f16 - nmadd.d $f18,$f9,$f14,$f19 - nmadd.s $f0,$f5,$f25,$f12 - nmsub.d $f30,$f8,$f16,$f30 - nmsub.s $f1,$f24,$f19,$f4 - recip.d $f19,$f6 - recip.s $f3,$f30 - rsqrt.d $f3,$f28 - rsqrt.s $f4,$f8 - tlbp - tlbr - tlbwi - tlbwr + .set noat + c.eq.d $fcc1,$f15,$f15 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.s $fcc3,$f11,$f8 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.s $fcc7,$f1,$f25 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.s $fcc1,$f30,$f4 + madd.d $f18,$f19,$f26,$f20 + madd.s $f1,$f31,$f19,$f25 + msub.d $f10,$f1,$f31,$f18 + msub.s $f12,$f19,$f10,$f16 + nmadd.d $f18,$f9,$f14,$f19 + nmadd.s $f0,$f5,$f25,$f12 + nmsub.d $f30,$f8,$f16,$f30 + nmsub.s $f1,$f24,$f19,$f4 + recip.d $f19,$f6 + recip.s $f3,$f30 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 diff --git a/test/MC/Mips/mips4/valid.s b/test/MC/Mips/mips4/valid.s index 8dc2a23..811584e 100644 --- a/test/MC/Mips/mips4/valid.s +++ b/test/MC/Mips/mips4/valid.s @@ -1,161 +1,194 @@ # Instructions that are valid # -# FIXME: Test MIPS-IV instead of MIPS64 -# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s +# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | FileCheck %s - .set noat - abs.d $f7,$f25 # CHECK: encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.l.d $f1,$f3 - ceil.l.s $f18,$f13 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - ctc1 $a2,$26 - cvt.d.l $f4,$f16 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.l.d $f24,$f15 - cvt.l.s $f11,$f29 - cvt.s.d $f26,$f8 - cvt.s.l $f15,$f30 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - dadd $s3,$at,$ra - daddi $sp,$s4,-27705 - daddiu $k0,$s6,-4586 - ddiv $zero,$k0,$s3 - ddivu $zero,$s0,$s1 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - dmfc1 $t4,$f13 - dmtc1 $s0,$f14 - dmult $s7,$t1 - dmultu $a1,$a2 - dsllv $zero,$s4,$t4 - dsrav $gp,$s2,$s3 - dsrlv $s3,$t6,$s4 - dsub $a3,$s6,$t0 - dsubu $a1,$a1,$k0 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - eret - floor.l.d $f26,$f7 - floor.l.s $f12,$f5 - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ld $sp,-28645($s1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - ldl $t8,-4167($t8) - ldr $t6,-30358($s4) - ldxc1 $f8,$s7($t7) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - lld $zero,-14736($ra) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - lwu $s3,-24086($v1) - lwxc1 $f12,$s1($s8) - mfc1 $a3,$f27 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $a0,$a3 - move $s5,$a0 - move $s8,$a0 - move $t9,$a2 - movf $gp,$t0,$fcc7 - movf.d $f6,$f11,$fcc5 - movf.s $f23,$f5,$fcc6 - movn $v1,$s1,$s0 - movn.d $f27,$f21,$k0 - movn.s $f12,$f0,$s7 - movt $zero,$s4,$fcc5 - movt.d $f0,$f2,$fcc0 - movt.s $f30,$f2,$fcc1 - movz $a1,$s6,$t1 - movz.d $f12,$f29,$t1 - movz.s $f25,$f7,$v1 - mtc1 $s8,$f9 - mthi $s1 - mtlo $sp - mtlo $t9 - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - round.l.d $f12,$f1 - round.l.s $f25,$f5 - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - scd $t7,-8243($sp) - sd $t4,5835($t2) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sdl $a3,-20961($s8) - sdr $t3,-20423($t4) - sdxc1 $f11,$t2($t6) - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - swxc1 $f19,$t4($k0) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.l.d $f23,$f23 - trunc.l.s $f28,$f31 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - xor $s2,$a0,$s8 + .set noat + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + ctc1 $a2,$26 + cvt.d.l $f4,$f16 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.l $f15,$f30 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + dadd $s3,$at,$ra + daddi $sp,$s4,-27705 + daddiu $k0,$s6,-4586 + daddu $s3,$at,$ra + ddiv $zero,$k0,$s3 + ddivu $zero,$s0,$s1 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + dmfc1 $12,$f13 + dmtc1 $s0,$f14 + dmult $s7,$9 + dmultu $a1,$a2 + dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8] + dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8] + dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbb] + dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbb] + dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] + dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf] + dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] + dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] + dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] + dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] + dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + eret + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ld $sp,-28645($s1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + ldl $24,-4167($24) + ldr $14,-30358($s4) + ldxc1 $f8,$s7($15) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + lld $zero,-14736($ra) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwu $s3,-24086($v1) + lwxc1 $f12,$s1($s8) + mfc1 $a3,$f27 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $a0,$a3 + move $s5,$a0 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + mtc1 $s8,$f9 + mthi $s1 + mtlo $sp + mtlo $25 + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + round.l.d $f12,$f1 + round.l.s $f25,$f5 + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + scd $15,-8243($sp) + sd $12,5835($10) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sdl $a3,-20961($s8) + sdr $11,-20423($12) + sdxc1 $f11,$10($14) + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swl $15,13694($s3) + swr $s1,-26590($14) + swxc1 $f19,$12($k0) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips5/invalid-mips64.s b/test/MC/Mips/mips5/invalid-mips64.s new file mode 100644 index 0000000..19d64dc --- /dev/null +++ b/test/MC/Mips/mips5/invalid-mips64.s @@ -0,0 +1,21 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + clo $11,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips4/invalid-mips64-xfail.s b/test/MC/Mips/mips5/invalid-mips64r2-xfail.s index d8ebcd3..b2b612d 100644 --- a/test/MC/Mips/mips4/invalid-mips64-xfail.s +++ b/test/MC/Mips/mips5/invalid-mips64r2-xfail.s @@ -8,15 +8,4 @@ # CHECK-NOT: error .set noat - deret - luxc1 $f19,$s6($s5) - madd $s6,$t5 - madd $zero,$t1 - maddu $s3,$gp - maddu $t8,$s2 - mfc0 $a2,$14,1 - msub $s7,$k1 - msubu $t7,$a1 - mtc0 $t1,$29,3 - mul $s0,$s4,$at - suxc1 $f12,$k1($t5) + rdhwr $sp,$11 diff --git a/test/MC/Mips/mips5/invalid-mips64r2.s b/test/MC/Mips/mips5/invalid-mips64r2.s new file mode 100644 index 0000000..b91e520 --- /dev/null +++ b/test/MC/Mips/mips5/invalid-mips64r2.s @@ -0,0 +1,43 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + clo $11,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr32 $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsbh $v1,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei $14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seb $25,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seh $v1,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + wsbh $k1,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips5/valid-xfail.s b/test/MC/Mips/mips5/valid-xfail.s index 85d961b..8d1d0d7 100644 --- a/test/MC/Mips/mips5/valid-xfail.s +++ b/test/MC/Mips/mips5/valid-xfail.s @@ -2,91 +2,86 @@ # they aren't implemented yet). # This test is set up to XPASS if any instruction generates an encoding. # -# FIXME: Test MIPS-V instead of MIPS64 -# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | not FileCheck %s +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | not FileCheck %s # CHECK-NOT: encoding # XFAIL: * .set noat - abs.ps $f22,$f8 - add.ps $f25,$f27,$f13 - alnv.ps $f12,$f18,$f30,$t4 - c.eq.d $fcc1,$f15,$f15 - c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 - c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 - c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 - cvt.ps.s $f3,$f18,$f19 - cvt.s.pl $f30,$f1 - cvt.s.pu $f14,$f25 - madd.d $f18,$f19,$f26,$f20 - madd.ps $f22,$f3,$f14,$f3 - madd.s $f1,$f31,$f19,$f25 - mov.ps $f22,$f17 - movf.ps $f10,$f28,$fcc6 - movn.ps $f31,$f31,$s3 - movt.ps $f20,$f25,$fcc2 - movz.ps $f18,$f17,$ra - msub.d $f10,$f1,$f31,$f18 - msub.ps $f12,$f14,$f29,$f17 - msub.s $f12,$f19,$f10,$f16 - mul.ps $f14,$f0,$f16 - neg.ps $f19,$f13 - nmadd.d $f18,$f9,$f14,$f19 - nmadd.ps $f27,$f4,$f9,$f25 - nmadd.s $f0,$f5,$f25,$f12 - nmsub.d $f30,$f8,$f16,$f30 - nmsub.ps $f6,$f12,$f14,$f17 - nmsub.s $f1,$f24,$f19,$f4 - pll.ps $f25,$f9,$f30 - plu.ps $f1,$f26,$f29 - pul.ps $f9,$f30,$f26 - puu.ps $f24,$f9,$f2 - recip.d $f19,$f6 - recip.s $f3,$f30 - rsqrt.d $f3,$f28 - rsqrt.s $f4,$f8 - sub.ps $f5,$f14,$f26 - tlbp - tlbr - tlbwi - tlbwr + abs.ps $f22,$f8 + add.ps $f25,$f27,$f13 + alnv.ps $f12,$f18,$f30,$12 + c.eq.d $fcc1,$f15,$f15 + c.eq.ps $fcc5,$f0,$f9 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.ps $fcc6,$f11,$f11 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.ps $fcc1,$f7,$f20 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.ps $f19,$f5 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.ps $f1,$f26 + c.nge.s $fcc3,$f11,$f8 + c.ngl.ps $f21,$f30 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.ps $fcc7,$f12,$f20 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.ps $fcc5,$f30,$f6 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.ps $fcc7,$f21,$f8 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.ps $fcc3,$f7,$f16 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.ps $fcc6,$f31,$f14 + c.seq.s $fcc7,$f1,$f25 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.ps $fcc1,$f5,$f29 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.ps $fcc6,$f17,$f3 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.ps $fcc7,$f14,$f0 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.ps $fcc4,$f2,$f26 + c.un.s $fcc1,$f30,$f4 + cvt.ps.s $f3,$f18,$f19 + cvt.s.pl $f30,$f1 + cvt.s.pu $f14,$f25 + madd.d $f18,$f19,$f26,$f20 + madd.ps $f22,$f3,$f14,$f3 + madd.s $f1,$f31,$f19,$f25 + mov.ps $f22,$f17 + movf.ps $f10,$f28,$fcc6 + movn.ps $f31,$f31,$s3 + movt.ps $f20,$f25,$fcc2 + movz.ps $f18,$f17,$ra + msub.d $f10,$f1,$f31,$f18 + msub.ps $f12,$f14,$f29,$f17 + msub.s $f12,$f19,$f10,$f16 + mul.ps $f14,$f0,$f16 + neg.ps $f19,$f13 + nmadd.d $f18,$f9,$f14,$f19 + nmadd.ps $f27,$f4,$f9,$f25 + nmadd.s $f0,$f5,$f25,$f12 + nmsub.d $f30,$f8,$f16,$f30 + nmsub.ps $f6,$f12,$f14,$f17 + nmsub.s $f1,$f24,$f19,$f4 + pll.ps $f25,$f9,$f30 + plu.ps $f1,$f26,$f29 + pul.ps $f9,$f30,$f26 + puu.ps $f24,$f9,$f2 + recip.d $f19,$f6 + recip.s $f3,$f30 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 + sub.ps $f5,$f14,$f26 diff --git a/test/MC/Mips/mips5/valid.s b/test/MC/Mips/mips5/valid.s index ebe2f70..19aad05 100644 --- a/test/MC/Mips/mips5/valid.s +++ b/test/MC/Mips/mips5/valid.s @@ -1,163 +1,196 @@ # Instructions that are valid # -# FIXME: Test MIPS-V instead of MIPS64 -# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s +# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | FileCheck %s .set noat - abs.d $f7,$f25 # CHECK: encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.l.d $f1,$f3 - ceil.l.s $f18,$f13 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - ctc1 $a2,$26 - cvt.d.l $f4,$f16 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.l.d $f24,$f15 - cvt.l.s $f11,$f29 - cvt.s.d $f26,$f8 - cvt.s.l $f15,$f30 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - dadd $s3,$at,$ra - daddi $sp,$s4,-27705 - daddiu $k0,$s6,-4586 - ddiv $zero,$k0,$s3 - ddivu $zero,$s0,$s1 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - dmfc1 $t4,$f13 - dmtc1 $s0,$f14 - dmult $s7,$t1 - dmultu $a1,$a2 - dsllv $zero,$s4,$t4 - dsrav $gp,$s2,$s3 - dsrlv $s3,$t6,$s4 - dsub $a3,$s6,$t0 - dsubu $a1,$a1,$k0 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - eret - floor.l.d $f26,$f7 - floor.l.s $f12,$f5 - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ld $sp,-28645($s1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - ldl $t8,-4167($t8) - ldr $t6,-30358($s4) - ldxc1 $f8,$s7($t7) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - lld $zero,-14736($ra) - luxc1 $f19,$s6($s5) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - lwu $s3,-24086($v1) - lwxc1 $f12,$s1($s8) - mfc1 $a3,$f27 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $a0,$a3 - move $s5,$a0 - move $s8,$a0 - move $t9,$a2 - movf $gp,$t0,$fcc7 - movf.d $f6,$f11,$fcc5 - movf.s $f23,$f5,$fcc6 - movn $v1,$s1,$s0 - movn.d $f27,$f21,$k0 - movn.s $f12,$f0,$s7 - movt $zero,$s4,$fcc5 - movt.d $f0,$f2,$fcc0 - movt.s $f30,$f2,$fcc1 - movz $a1,$s6,$t1 - movz.d $f12,$f29,$t1 - movz.s $f25,$f7,$v1 - mtc1 $s8,$f9 - mthi $s1 - mtlo $sp - mtlo $t9 - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - round.l.d $f12,$f1 - round.l.s $f25,$f5 - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - scd $t7,-8243($sp) - sd $t4,5835($t2) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sdl $a3,-20961($s8) - sdr $t3,-20423($t4) - sdxc1 $f11,$t2($t6) - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - suxc1 $f12,$k1($t5) - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - swxc1 $f19,$t4($k0) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.l.d $f23,$f23 - trunc.l.s $f28,$f31 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - xor $s2,$a0,$s8 + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + ctc1 $a2,$26 + cvt.d.l $f4,$f16 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.l $f15,$f30 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + dadd $s3,$at,$ra + daddi $sp,$s4,-27705 + daddiu $k0,$s6,-4586 + daddu $s3,$at,$ra + ddiv $zero,$k0,$s3 + ddivu $zero,$s0,$s1 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + dmfc1 $12,$f13 + dmtc1 $s0,$f14 + dmult $s7,$9 + dmultu $a1,$a2 + dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8] + dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8] + dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbb] + dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbb] + dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] + dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf] + dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] + dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] + dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] + dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] + dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + eret + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ld $sp,-28645($s1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + ldl $24,-4167($24) + ldr $14,-30358($s4) + ldxc1 $f8,$s7($15) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + lld $zero,-14736($ra) + luxc1 $f19,$s6($s5) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwu $s3,-24086($v1) + lwxc1 $f12,$s1($s8) + mfc1 $a3,$f27 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $a0,$a3 + move $s5,$a0 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + mtc1 $s8,$f9 + mthi $s1 + mtlo $sp + mtlo $25 + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + round.l.d $f12,$f1 + round.l.s $f25,$f5 + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + scd $15,-8243($sp) + sd $12,5835($10) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sdl $a3,-20961($s8) + sdr $11,-20423($12) + sdxc1 $f11,$10($14) + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + suxc1 $f12,$k1($13) + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swl $15,13694($s3) + swr $s1,-26590($14) + swxc1 $f19,$12($k0) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips64/invalid-mips64r2-xfail.s b/test/MC/Mips/mips64/invalid-mips64r2-xfail.s index 4baf26b..b2b612d 100644 --- a/test/MC/Mips/mips64/invalid-mips64r2-xfail.s +++ b/test/MC/Mips/mips64/invalid-mips64r2-xfail.s @@ -8,8 +8,4 @@ # CHECK-NOT: error .set noat - di $s8 - ei $t6 - mfhc1 $s8,$f24 - mthc1 $zero,$f16 rdhwr $sp,$11 diff --git a/test/MC/Mips/mips64/invalid-mips64r2.s b/test/MC/Mips/mips64/invalid-mips64r2.s index 41aa8ae..1a5abb6 100644 --- a/test/MC/Mips/mips64/invalid-mips64r2.s +++ b/test/MC/Mips/mips64/invalid-mips64r2.s @@ -5,13 +5,25 @@ # RUN: FileCheck %s < %t1 .set noat - dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - wsbh $k1,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotr32 $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + drotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsbh $v1,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei $14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seb $25,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + seh $v1,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + wsbh $k1,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64/valid-xfail.s b/test/MC/Mips/mips64/valid-xfail.s index 61bf060..e5455f5 100644 --- a/test/MC/Mips/mips64/valid-xfail.s +++ b/test/MC/Mips/mips64/valid-xfail.s @@ -6,93 +6,89 @@ # CHECK-NOT: encoding # XFAIL: * - .set noat - abs.ps $f22,$f8 - add.ps $f25,$f27,$f13 - alnv.ob $v22,$v19,$v30,$v1 - alnv.ob $v31,$v23,$v30,$at - alnv.ob $v8,$v17,$v30,$a1 - alnv.ps $f12,$f18,$f30,$t4 - c.eq.d $fcc1,$f15,$f15 - c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 - c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 - c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 - cvt.ps.s $f3,$f18,$f19 - cvt.s.pl $f30,$f1 - cvt.s.pu $f14,$f25 - dmfc0 $t2,c0_watchhi,2 - dmtc0 $t7,c0_datalo - madd.d $f18,$f19,$f26,$f20 - madd.ps $f22,$f3,$f14,$f3 - madd.s $f1,$f31,$f19,$f25 - mov.ps $f22,$f17 - movf.ps $f10,$f28,$fcc6 - movn.ps $f31,$f31,$s3 - movt.ps $f20,$f25,$fcc2 - movz.ps $f18,$f17,$ra - msgn.qh $v0,$v24,$v20 - msgn.qh $v12,$v21,$v0[1] - msub.d $f10,$f1,$f31,$f18 - msub.ps $f12,$f14,$f29,$f17 - msub.s $f12,$f19,$f10,$f16 - mul.ps $f14,$f0,$f16 - neg.ps $f19,$f13 - nmadd.d $f18,$f9,$f14,$f19 - nmadd.ps $f27,$f4,$f9,$f25 - nmadd.s $f0,$f5,$f25,$f12 - nmsub.d $f30,$f8,$f16,$f30 - nmsub.ps $f6,$f12,$f14,$f17 - nmsub.s $f1,$f24,$f19,$f4 - pll.ps $f25,$f9,$f30 - plu.ps $f1,$f26,$f29 - pul.ps $f9,$f30,$f26 - puu.ps $f24,$f9,$f2 - recip.d $f19,$f6 - recip.s $f3,$f30 - rsqrt.d $f3,$f28 - rsqrt.s $f4,$f8 - sub.ps $f5,$f14,$f26 - tlbp - tlbr - tlbwi - tlbwr + .set noat + abs.ps $f22,$f8 + add.ps $f25,$f27,$f13 + alnv.ob $v22,$v19,$v30,$v1 + alnv.ob $v31,$v23,$v30,$at + alnv.ob $v8,$v17,$v30,$a1 + alnv.ps $f12,$f18,$f30,$12 + c.eq.d $fcc1,$f15,$f15 + c.eq.ps $fcc5,$f0,$f9 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.ps $fcc6,$f11,$f11 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.ps $fcc1,$f7,$f20 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.ps $f19,$f5 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.ps $f1,$f26 + c.nge.s $fcc3,$f11,$f8 + c.ngl.ps $f21,$f30 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.ps $fcc7,$f12,$f20 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.ps $fcc5,$f30,$f6 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.ps $fcc7,$f21,$f8 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.ps $fcc3,$f7,$f16 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.ps $fcc6,$f31,$f14 + c.seq.s $fcc7,$f1,$f25 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.ps $fcc1,$f5,$f29 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.ps $fcc6,$f17,$f3 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.ps $fcc7,$f14,$f0 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.ps $fcc4,$f2,$f26 + c.un.s $fcc1,$f30,$f4 + cvt.ps.s $f3,$f18,$f19 + cvt.s.pl $f30,$f1 + cvt.s.pu $f14,$f25 + dmfc0 $10,c0_watchhi,2 + dmtc0 $15,c0_datalo + madd.d $f18,$f19,$f26,$f20 + madd.ps $f22,$f3,$f14,$f3 + madd.s $f1,$f31,$f19,$f25 + mov.ps $f22,$f17 + movf.ps $f10,$f28,$fcc6 + movn.ps $f31,$f31,$s3 + movt.ps $f20,$f25,$fcc2 + movz.ps $f18,$f17,$ra + msgn.qh $v0,$v24,$v20 + msgn.qh $v12,$v21,$v0[1] + msub.d $f10,$f1,$f31,$f18 + msub.ps $f12,$f14,$f29,$f17 + msub.s $f12,$f19,$f10,$f16 + mul.ps $f14,$f0,$f16 + neg.ps $f19,$f13 + nmadd.d $f18,$f9,$f14,$f19 + nmadd.ps $f27,$f4,$f9,$f25 + nmadd.s $f0,$f5,$f25,$f12 + nmsub.d $f30,$f8,$f16,$f30 + nmsub.ps $f6,$f12,$f14,$f17 + nmsub.s $f1,$f24,$f19,$f4 + pll.ps $f25,$f9,$f30 + plu.ps $f1,$f26,$f29 + pul.ps $f9,$f30,$f26 + puu.ps $f24,$f9,$f2 + recip.d $f19,$f6 + recip.s $f3,$f30 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 + sub.ps $f5,$f14,$f26 diff --git a/test/MC/Mips/mips64/valid.s b/test/MC/Mips/mips64/valid.s index 9ccb2ff..b9e1002 100644 --- a/test/MC/Mips/mips64/valid.s +++ b/test/MC/Mips/mips64/valid.s @@ -3,174 +3,208 @@ # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s .set noat - abs.d $f7,$f25 # CHECK: encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.l.d $f1,$f3 - ceil.l.s $f18,$f13 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - clo $t3,$a1 - clz $sp,$gp - ctc1 $a2,$26 - cvt.d.l $f4,$f16 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.l.d $f24,$f15 - cvt.l.s $f11,$f29 - cvt.s.d $f26,$f8 - cvt.s.l $f15,$f30 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - dadd $s3,$at,$ra - daddi $sp,$s4,-27705 - daddiu $k0,$s6,-4586 - dclo $s2,$a2 - dclz $s0,$t9 - deret - ddiv $zero,$k0,$s3 - ddivu $zero,$s0,$s1 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - dmfc1 $t4,$f13 - dmtc1 $s0,$f14 - dmult $s7,$t1 - dmultu $a1,$a2 - dsllv $zero,$s4,$t4 - dsrav $gp,$s2,$s3 - dsrlv $s3,$t6,$s4 - dsub $a3,$s6,$t0 - dsubu $a1,$a1,$k0 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - eret - floor.l.d $f26,$f7 - floor.l.s $f12,$f5 - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ld $sp,-28645($s1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - ldl $t8,-4167($t8) - ldr $t6,-30358($s4) - ldxc1 $f8,$s7($t7) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - lld $zero,-14736($ra) - luxc1 $f19,$s6($s5) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - lwu $s3,-24086($v1) - lwxc1 $f12,$s1($s8) - madd $s6,$t5 - madd $zero,$t1 - maddu $s3,$gp - maddu $t8,$s2 - mfc0 $a2,$14,1 - mfc1 $a3,$f27 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $a0,$a3 - move $s5,$a0 - move $s8,$a0 - move $t9,$a2 - movf $gp,$t0,$fcc7 - movf.d $f6,$f11,$fcc5 - movf.s $f23,$f5,$fcc6 - movn $v1,$s1,$s0 - movn.d $f27,$f21,$k0 - movn.s $f12,$f0,$s7 - movt $zero,$s4,$fcc5 - movt.d $f0,$f2,$fcc0 - movt.s $f30,$f2,$fcc1 - movz $a1,$s6,$t1 - movz.d $f12,$f29,$t1 - movz.s $f25,$f7,$v1 - msub $s7,$k1 - msubu $t7,$a1 - mtc0 $t1,$29,3 - mtc1 $s8,$f9 - mthi $s1 - mtlo $sp - mtlo $t9 - mul $s0,$s4,$at - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - round.l.d $f12,$f1 - round.l.s $f25,$f5 - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - scd $t7,-8243($sp) - sd $t4,5835($t2) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sdl $a3,-20961($s8) - sdr $t3,-20423($t4) - sdxc1 $f11,$t2($t6) - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - suxc1 $f12,$k1($t5) - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - swxc1 $f19,$t4($k0) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.l.d $f23,$f23 - trunc.l.s $f28,$f31 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - xor $s2,$a0,$s8 + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + clo $11,$a1 + clz $sp,$gp + ctc1 $a2,$26 + cvt.d.l $f4,$f16 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.l $f15,$f30 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + dadd $s3,$at,$ra + daddi $sp,$s4,-27705 + daddiu $k0,$s6,-4586 + daddu $s3,$at,$ra + dclo $s2,$a2 + dclz $s0,$25 + deret + ddiv $zero,$k0,$s3 + ddivu $zero,$s0,$s1 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + dmfc1 $12,$f13 + dmtc1 $s0,$f14 + dmult $s7,$9 + dmultu $a1,$a2 + dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8] + dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8] + dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbb] + dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbb] + dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] + dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf] + dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] + dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] + dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] + dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] + dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + eret + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ld $sp,-28645($s1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + ldl $24,-4167($24) + ldr $14,-30358($s4) + ldxc1 $f8,$s7($15) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + lld $zero,-14736($ra) + luxc1 $f19,$s6($s5) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwu $s3,-24086($v1) + lwxc1 $f12,$s1($s8) + madd $s6,$13 + madd $zero,$9 + maddu $s3,$gp + maddu $24,$s2 + mfc0 $a2,$14,1 + mfc1 $a3,$f27 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $a0,$a3 + move $s5,$a0 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + msub $s7,$k1 + msubu $15,$a1 + mtc0 $9,$29,3 + mtc1 $s8,$f9 + mthi $s1 + mtlo $sp + mtlo $25 + mul $s0,$s4,$at + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + round.l.d $f12,$f1 + round.l.s $f25,$f5 + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + scd $15,-8243($sp) + sd $12,5835($10) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sdl $a3,-20961($s8) + sdr $11,-20423($12) + sdxc1 $f11,$10($14) + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + suxc1 $f12,$k1($13) + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swl $15,13694($s3) + swr $s1,-26590($14) + swxc1 $f19,$12($k0) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 diff --git a/test/MC/Mips/mips64r2/valid-xfail.s b/test/MC/Mips/mips64r2/valid-xfail.s index 9d9d6cd..9ac47f6 100644 --- a/test/MC/Mips/mips64r2/valid-xfail.s +++ b/test/MC/Mips/mips64r2/valid-xfail.s @@ -5,312 +5,307 @@ # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | not FileCheck %s # CHECK-NOT: encoding # XFAIL: * -# REQUIRES: asserts - .set noat - abs.ps $f22,$f8 - absq_s.ph $t0,$a0 - absq_s.qb $t7,$s1 - absq_s.w $s3,$ra - add.ps $f25,$f27,$f13 - addq.ph $s1,$t7,$at - addq_s.ph $s3,$s6,$s2 - addq_s.w $a2,$t0,$at - addqh.ph $s4,$t6,$s1 - addqh.w $s7,$s7,$k1 - addqh_r.ph $sp,$t9,$s8 - addqh_r.w $t0,$v1,$zero - addsc $s8,$t7,$t4 - addu.ph $a2,$t6,$s3 - addu.qb $s6,$v1,$v1 - addu_s.ph $a3,$s3,$gp - addu_s.qb $s4,$s8,$s1 - adduh.qb $a1,$a1,$at - adduh_r.qb $a0,$t1,$t4 - addwc $k0,$s6,$s7 - alnv.ob $v22,$v19,$v30,$v1 - alnv.ob $v31,$v23,$v30,$at - alnv.ob $v8,$v17,$v30,$a1 - alnv.ps $f12,$f18,$f30,$t4 - and.v $w10,$w25,$w29 - bitrev $t6,$at - bmnz.v $w15,$w2,$w28 - bmz.v $w13,$w11,$w21 - bsel.v $w28,$w7,$w0 - c.eq.d $fcc1,$f15,$f15 - c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 - c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 - c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 - cvt.ps.s $f3,$f18,$f19 - cmp.eq.ph $s7,$t6 - cmp.le.ph $t0,$t6 - cmp.lt.ph $k0,$sp - cmpgdu.eq.qb $s3,$zero,$k0 - cmpgdu.le.qb $v1,$t7,$s2 - cmpgdu.lt.qb $s0,$gp,$sp - cmpgu.eq.qb $t6,$s6,$s8 - cmpgu.le.qb $t1,$a3,$s4 - cmpgu.lt.qb $sp,$at,$t0 - cmpu.eq.qb $v0,$t8 - cmpu.le.qb $s1,$a1 - cmpu.lt.qb $at,$a3 - cvt.s.pl $f30,$f1 - cvt.s.pu $f14,$f25 - dmfc0 $t2,c0_watchhi,2 - dmfgc0 $gp,c0_perfcnt,6 - dmt $k0 - dmtc0 $t7,c0_datalo - dmtgc0 $a2,c0_watchlo,2 - dpa.w.ph $ac1,$s7,$k0 - dpaq_s.w.ph $ac2,$a0,$t5 - dpaq_sa.l.w $ac0,$a2,$t6 - dpaqx_s.w.ph $ac3,$a0,$t8 - dpaqx_sa.w.ph $ac1,$zero,$s5 - dpau.h.qbl $ac1,$t2,$t8 - dpau.h.qbr $ac1,$s7,$s6 - dpax.w.ph $ac3,$a0,$k0 - dps.w.ph $ac1,$a3,$a1 - dpsq_s.w.ph $ac0,$gp,$k0 - dpsq_sa.l.w $ac0,$a3,$t7 - dpsqx_s.w.ph $ac3,$t5,$a3 - dpsqx_sa.w.ph $ac3,$sp,$s2 - dpsu.h.qbl $ac2,$t6,$t2 - dpsu.h.qbr $ac2,$a1,$s6 - dpsx.w.ph $ac0,$s7,$gp - drorv $at,$a1,$s7 - dvpe $s6 - emt $t0 - evpe $v0 - extpdpv $s6,$ac0,$s8 - extpv $t5,$ac0,$t6 - extrv.w $t0,$ac3,$at - extrv_r.w $t0,$ac1,$s6 - extrv_rs.w $gp,$ac1,$s6 - extrv_s.h $s2,$ac1,$t6 - fclass.d $w14,$w27 - fclass.w $w19,$w28 - fexupl.d $w10,$w29 - fexupl.w $w12,$w27 - fexupr.d $w31,$w15 - fexupr.w $w29,$w12 - ffint_s.d $w1,$w30 - ffint_s.w $w16,$w14 - ffint_u.d $w23,$w18 - ffint_u.w $w19,$w12 - ffql.d $w2,$w3 - ffql.w $w9,$w0 - ffqr.d $w25,$w24 - ffqr.w $w10,$w6 - fill.b $w9,$v1 - fill.d $w28,$t0 - fill.h $w9,$t0 - fill.w $w31,$t7 - flog2.d $w12,$w16 - flog2.w $w19,$w23 - fork $s2,$t0,$a0 - frcp.d $w12,$w4 - frcp.w $w30,$w8 - frint.d $w20,$w8 - frint.w $w11,$w29 - frsqrt.d $w29,$w2 - frsqrt.w $w9,$w8 - fsqrt.d $w3,$w1 - fsqrt.w $w5,$w15 - ftint_s.d $w31,$w26 - ftint_s.w $w27,$w14 - ftint_u.d $w5,$w31 - ftint_u.w $w12,$w29 - ftrunc_s.d $w4,$w22 - ftrunc_s.w $w24,$w7 - ftrunc_u.d $w20,$w25 - ftrunc_u.w $w7,$w26 - insv $s2,$at - iret - lbe $t6,122($t1) - lbue $t3,-108($t2) - lbux $t1,$t6($v0) - lhe $s6,219($v1) - lhue $gp,118($t3) - lhx $sp,$k0($t7) - lle $gp,-237($ra) - lwe $ra,-145($t6) - lwle $t3,-42($t3) - lwre $sp,-152($t8) - lwx $t4,$t4($s4) - madd.d $f18,$f19,$f26,$f20 - madd.ps $f22,$f3,$f14,$f3 - maq_s.w.phl $ac2,$t9,$t3 - maq_s.w.phr $ac0,$t2,$t9 - maq_sa.w.phl $ac3,$a1,$v1 - maq_sa.w.phr $ac1,$at,$t2 - mfgc0 $s6,c0_datahi1 - mflo $t1,$ac2 - modsub $a3,$t4,$a3 - mov.ps $f22,$f17 - movf.ps $f10,$f28,$fcc6 - movn.ps $f31,$f31,$s3 - movt.ps $f20,$f25,$fcc2 - movz.ps $f18,$f17,$ra - msgn.qh $v0,$v24,$v20 - msgn.qh $v12,$v21,$v0[1] - msub $ac2,$sp,$t6 - msub.d $f10,$f1,$f31,$f18 - msub.ps $f12,$f14,$f29,$f17 - msubu $ac2,$a1,$t8 - mtc0 $t1,c0_datahi1 - mtgc0 $s4,$21,7 - mthi $v0,$ac1 - mthlip $a3,$ac0 - mul.ph $s4,$t8,$s0 - mul.ps $f14,$f0,$f16 - mul_s.ph $t2,$t6,$t7 - muleq_s.w.phl $t3,$s4,$s4 - muleq_s.w.phr $s6,$a0,$s8 - muleu_s.ph.qbl $a2,$t6,$t0 - muleu_s.ph.qbr $a1,$ra,$t1 - mulq_rs.ph $s2,$t6,$t7 - mulq_rs.w $at,$s4,$t9 - mulq_s.ph $s0,$k1,$t7 - mulq_s.w $t1,$a3,$s0 - mulsa.w.ph $ac1,$s4,$s6 - mulsaq_s.w.ph $ac0,$ra,$s2 - neg.ps $f19,$f13 - nloc.b $w12,$w30 - nloc.d $w16,$w7 - nloc.h $w21,$w17 - nloc.w $w17,$w16 - nlzc.b $w12,$w7 - nlzc.d $w14,$w14 - nlzc.h $w24,$w24 - nlzc.w $w10,$w4 - nmadd.d $f18,$f9,$f14,$f19 - nmadd.ps $f27,$f4,$f9,$f25 - nmsub.d $f30,$f8,$f16,$f30 - nmsub.ps $f6,$f12,$f14,$f17 - nor.v $w20,$w20,$w15 - or.v $w13,$w23,$w12 - packrl.ph $ra,$t8,$t6 - pcnt.b $w30,$w15 - pcnt.d $w5,$w16 - pcnt.h $w20,$w24 - pcnt.w $w22,$w20 - pick.ph $ra,$a2,$gp - pick.qb $t3,$a0,$gp - pll.ps $f25,$f9,$f30 - plu.ps $f1,$f26,$f29 - preceq.w.phl $s8,$gp - preceq.w.phr $s5,$t7 - precequ.ph.qbl $s7,$ra - precequ.ph.qbla $a0,$t1 - precequ.ph.qbr $ra,$s3 - precequ.ph.qbra $t8,$t0 - preceu.ph.qbl $sp,$t0 - preceu.ph.qbla $s6,$t3 - preceu.ph.qbr $gp,$s1 - preceu.ph.qbra $k1,$s0 - precr.qb.ph $v0,$t4,$s8 - precrq.ph.w $t6,$s8,$t8 - precrq.qb.ph $a2,$t4,$t4 - precrq_rs.ph.w $a1,$k0,$a3 - precrqu_s.qb.ph $zero,$gp,$s5 - pul.ps $f9,$f30,$f26 - puu.ps $f24,$f9,$f2 - raddu.w.qb $t9,$s3 - rdpgpr $s3,$t1 - recip.d $f19,$f6 - recip.s $f3,$f30 - repl.ph $at,-307 - replv.ph $v1,$s7 - replv.qb $t9,$t4 - rorv $t5,$a3,$s5 - rsqrt.d $f3,$f28 - rsqrt.s $f4,$f8 - sbe $s7,33($s1) - sce $sp,189($t2) - she $t8,105($v0) - shilo $ac1,26 - shilov $ac2,$t2 - shllv.ph $t2,$s0,$s0 - shllv.qb $gp,$v1,$zero - shllv_s.ph $k1,$at,$t5 - shllv_s.w $s1,$ra,$k0 - shrav.ph $t9,$s2,$s1 - shrav.qb $zero,$t8,$t3 - shrav_r.ph $s3,$t3,$t9 - shrav_r.qb $a0,$sp,$s5 - shrav_r.w $s7,$s4,$s6 - shrlv.ph $t6,$t2,$t1 - shrlv.qb $a2,$s2,$t3 - sub.ps $f5,$f14,$f26 - subq.ph $ra,$t1,$s8 - subq_s.ph $t5,$s8,$s5 - subq_s.w $k1,$a2,$a3 - subqh.ph $t2,$at,$t1 - subqh.w $v0,$a2,$zero - subqh_r.ph $a0,$t4,$s6 - subqh_r.w $t2,$a2,$gp - subu.ph $t1,$s6,$s4 - subu.qb $s6,$a2,$s6 - subu_s.ph $v1,$a1,$s3 - subu_s.qb $s1,$at,$ra - subuh.qb $zero,$gp,$gp - subuh_r.qb $s4,$s8,$s6 - swe $t8,94($k0) - swle $v1,-209($gp) - swre $k0,-202($s2) - synci 20023($s0) - tlbginv - tlbginvf - tlbgp - tlbgr - tlbgwi - tlbgwr - tlbinv - tlbinvf - tlbp - tlbr - tlbwi - tlbwr - wrpgpr $zero,$t5 - xor.v $w20,$w21,$w30 - yield $v1,$s0 + .set noat + abs.ps $f22,$f8 + absq_s.ph $8,$a0 + absq_s.qb $15,$s1 + absq_s.w $s3,$ra + add.ps $f25,$f27,$f13 + addq.ph $s1,$15,$at + addq_s.ph $s3,$s6,$s2 + addq_s.w $a2,$8,$at + addqh.ph $s4,$14,$s1 + addqh.w $s7,$s7,$k1 + addqh_r.ph $sp,$25,$s8 + addqh_r.w $8,$v1,$zero + addsc $s8,$15,$12 + addu.ph $a2,$14,$s3 + addu.qb $s6,$v1,$v1 + addu_s.ph $a3,$s3,$gp + addu_s.qb $s4,$s8,$s1 + adduh.qb $a1,$a1,$at + adduh_r.qb $a0,$9,$12 + addwc $k0,$s6,$s7 + alnv.ob $v22,$v19,$v30,$v1 + alnv.ob $v31,$v23,$v30,$at + alnv.ob $v8,$v17,$v30,$a1 + alnv.ps $f12,$f18,$f30,$12 + and.v $w10,$w25,$w29 + bitrev $14,$at + bmnz.v $w15,$w2,$w28 + bmz.v $w13,$w11,$w21 + bsel.v $w28,$w7,$w0 + c.eq.d $fcc1,$f15,$f15 + c.eq.ps $fcc5,$f0,$f9 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.ps $fcc6,$f11,$f11 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.ps $fcc1,$f7,$f20 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.ps $f19,$f5 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.ps $f1,$f26 + c.nge.s $fcc3,$f11,$f8 + c.ngl.ps $f21,$f30 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.ps $fcc7,$f12,$f20 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.ps $fcc5,$f30,$f6 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.ps $fcc7,$f21,$f8 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.ps $fcc3,$f7,$f16 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.ps $fcc6,$f31,$f14 + c.seq.s $fcc7,$f1,$f25 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.ps $fcc1,$f5,$f29 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.ps $fcc6,$f17,$f3 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.ps $fcc7,$f14,$f0 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.ps $fcc4,$f2,$f26 + c.un.s $fcc1,$f30,$f4 + cvt.ps.s $f3,$f18,$f19 + cmp.eq.ph $s7,$14 + cmp.le.ph $8,$14 + cmp.lt.ph $k0,$sp + cmpgdu.eq.qb $s3,$zero,$k0 + cmpgdu.le.qb $v1,$15,$s2 + cmpgdu.lt.qb $s0,$gp,$sp + cmpgu.eq.qb $14,$s6,$s8 + cmpgu.le.qb $9,$a3,$s4 + cmpgu.lt.qb $sp,$at,$8 + cmpu.eq.qb $v0,$24 + cmpu.le.qb $s1,$a1 + cmpu.lt.qb $at,$a3 + cvt.s.pl $f30,$f1 + cvt.s.pu $f14,$f25 + dmfc0 $10,c0_watchhi,2 + dmfgc0 $gp,c0_perfcnt,6 + dmt $k0 + dmtc0 $15,c0_datalo + dmtgc0 $a2,c0_watchlo,2 + dpa.w.ph $ac1,$s7,$k0 + dpaq_s.w.ph $ac2,$a0,$13 + dpaq_sa.l.w $ac0,$a2,$14 + dpaqx_s.w.ph $ac3,$a0,$24 + dpaqx_sa.w.ph $ac1,$zero,$s5 + dpau.h.qbl $ac1,$10,$24 + dpau.h.qbr $ac1,$s7,$s6 + dpax.w.ph $ac3,$a0,$k0 + dps.w.ph $ac1,$a3,$a1 + dpsq_s.w.ph $ac0,$gp,$k0 + dpsq_sa.l.w $ac0,$a3,$15 + dpsqx_s.w.ph $ac3,$13,$a3 + dpsqx_sa.w.ph $ac3,$sp,$s2 + dpsu.h.qbl $ac2,$14,$10 + dpsu.h.qbr $ac2,$a1,$s6 + dpsx.w.ph $ac0,$s7,$gp + drorv $at,$a1,$s7 + dvpe $s6 + emt $8 + evpe $v0 + extpdpv $s6,$ac0,$s8 + extpv $13,$ac0,$14 + extrv.w $8,$ac3,$at + extrv_r.w $8,$ac1,$s6 + extrv_rs.w $gp,$ac1,$s6 + extrv_s.h $s2,$ac1,$14 + fclass.d $w14,$w27 + fclass.w $w19,$w28 + fexupl.d $w10,$w29 + fexupl.w $w12,$w27 + fexupr.d $w31,$w15 + fexupr.w $w29,$w12 + ffint_s.d $w1,$w30 + ffint_s.w $w16,$w14 + ffint_u.d $w23,$w18 + ffint_u.w $w19,$w12 + ffql.d $w2,$w3 + ffql.w $w9,$w0 + ffqr.d $w25,$w24 + ffqr.w $w10,$w6 + fill.b $w9,$v1 + fill.d $w28,$8 + fill.h $w9,$8 + fill.w $w31,$15 + flog2.d $w12,$w16 + flog2.w $w19,$w23 + fork $s2,$8,$a0 + frcp.d $w12,$w4 + frcp.w $w30,$w8 + frint.d $w20,$w8 + frint.w $w11,$w29 + frsqrt.d $w29,$w2 + frsqrt.w $w9,$w8 + fsqrt.d $w3,$w1 + fsqrt.w $w5,$w15 + ftint_s.d $w31,$w26 + ftint_s.w $w27,$w14 + ftint_u.d $w5,$w31 + ftint_u.w $w12,$w29 + ftrunc_s.d $w4,$w22 + ftrunc_s.w $w24,$w7 + ftrunc_u.d $w20,$w25 + ftrunc_u.w $w7,$w26 + insv $s2,$at + iret + lbe $14,122($9) + lbue $11,-108($10) + lbux $9,$14($v0) + lhe $s6,219($v1) + lhue $gp,118($11) + lhx $sp,$k0($15) + lle $gp,-237($ra) + lwe $ra,-145($14) + lwle $11,-42($11) + lwre $sp,-152($24) + lwx $12,$12($s4) + madd.d $f18,$f19,$f26,$f20 + madd.ps $f22,$f3,$f14,$f3 + maq_s.w.phl $ac2,$25,$11 + maq_s.w.phr $ac0,$10,$25 + maq_sa.w.phl $ac3,$a1,$v1 + maq_sa.w.phr $ac1,$at,$10 + mfgc0 $s6,c0_datahi1 + mflo $9,$ac2 + modsub $a3,$12,$a3 + mov.ps $f22,$f17 + movf.ps $f10,$f28,$fcc6 + movn.ps $f31,$f31,$s3 + movt.ps $f20,$f25,$fcc2 + movz.ps $f18,$f17,$ra + msgn.qh $v0,$v24,$v20 + msgn.qh $v12,$v21,$v0[1] + msub $ac2,$sp,$14 + msub.d $f10,$f1,$f31,$f18 + msub.ps $f12,$f14,$f29,$f17 + msubu $ac2,$a1,$24 + mtc0 $9,c0_datahi1 + mtgc0 $s4,$21,7 + mthi $v0,$ac1 + mthlip $a3,$ac0 + mul.ph $s4,$24,$s0 + mul.ps $f14,$f0,$f16 + mul_s.ph $10,$14,$15 + muleq_s.w.phl $11,$s4,$s4 + muleq_s.w.phr $s6,$a0,$s8 + muleu_s.ph.qbl $a2,$14,$8 + muleu_s.ph.qbr $a1,$ra,$9 + mulq_rs.ph $s2,$14,$15 + mulq_rs.w $at,$s4,$25 + mulq_s.ph $s0,$k1,$15 + mulq_s.w $9,$a3,$s0 + mulsa.w.ph $ac1,$s4,$s6 + mulsaq_s.w.ph $ac0,$ra,$s2 + neg.ps $f19,$f13 + nloc.b $w12,$w30 + nloc.d $w16,$w7 + nloc.h $w21,$w17 + nloc.w $w17,$w16 + nlzc.b $w12,$w7 + nlzc.d $w14,$w14 + nlzc.h $w24,$w24 + nlzc.w $w10,$w4 + nmadd.d $f18,$f9,$f14,$f19 + nmadd.ps $f27,$f4,$f9,$f25 + nmsub.d $f30,$f8,$f16,$f30 + nmsub.ps $f6,$f12,$f14,$f17 + nor.v $w20,$w20,$w15 + or.v $w13,$w23,$w12 + packrl.ph $ra,$24,$14 + pcnt.b $w30,$w15 + pcnt.d $w5,$w16 + pcnt.h $w20,$w24 + pcnt.w $w22,$w20 + pick.ph $ra,$a2,$gp + pick.qb $11,$a0,$gp + pll.ps $f25,$f9,$f30 + plu.ps $f1,$f26,$f29 + preceq.w.phl $s8,$gp + preceq.w.phr $s5,$15 + precequ.ph.qbl $s7,$ra + precequ.ph.qbla $a0,$9 + precequ.ph.qbr $ra,$s3 + precequ.ph.qbra $24,$8 + preceu.ph.qbl $sp,$8 + preceu.ph.qbla $s6,$11 + preceu.ph.qbr $gp,$s1 + preceu.ph.qbra $k1,$s0 + precr.qb.ph $v0,$12,$s8 + precrq.ph.w $14,$s8,$24 + precrq.qb.ph $a2,$12,$12 + precrq_rs.ph.w $a1,$k0,$a3 + precrqu_s.qb.ph $zero,$gp,$s5 + pul.ps $f9,$f30,$f26 + puu.ps $f24,$f9,$f2 + raddu.w.qb $25,$s3 + rdpgpr $s3,$9 + recip.d $f19,$f6 + recip.s $f3,$f30 + repl.ph $at,-307 + replv.ph $v1,$s7 + replv.qb $25,$12 + rorv $13,$a3,$s5 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 + sbe $s7,33($s1) + sce $sp,189($10) + she $24,105($v0) + shilo $ac1,26 + shilov $ac2,$10 + shllv.ph $10,$s0,$s0 + shllv.qb $gp,$v1,$zero + shllv_s.ph $k1,$at,$13 + shllv_s.w $s1,$ra,$k0 + shrav.ph $25,$s2,$s1 + shrav.qb $zero,$24,$11 + shrav_r.ph $s3,$11,$25 + shrav_r.qb $a0,$sp,$s5 + shrav_r.w $s7,$s4,$s6 + shrlv.ph $14,$10,$9 + shrlv.qb $a2,$s2,$11 + sub.ps $f5,$f14,$f26 + subq.ph $ra,$9,$s8 + subq_s.ph $13,$s8,$s5 + subq_s.w $k1,$a2,$a3 + subqh.ph $10,$at,$9 + subqh.w $v0,$a2,$zero + subqh_r.ph $a0,$12,$s6 + subqh_r.w $10,$a2,$gp + subu.ph $9,$s6,$s4 + subu.qb $s6,$a2,$s6 + subu_s.ph $v1,$a1,$s3 + subu_s.qb $s1,$at,$ra + subuh.qb $zero,$gp,$gp + subuh_r.qb $s4,$s8,$s6 + swe $24,94($k0) + swle $v1,-209($gp) + swre $k0,-202($s2) + synci 20023($s0) + tlbginv + tlbginvf + tlbgp + tlbgr + tlbgwi + tlbgwr + tlbinv + tlbinvf + wrpgpr $zero,$13 + xor.v $w20,$w21,$w30 + yield $v1,$s0 diff --git a/test/MC/Mips/mips64r2/valid.s b/test/MC/Mips/mips64r2/valid.s index 826a6b2..252589d 100644 --- a/test/MC/Mips/mips64r2/valid.s +++ b/test/MC/Mips/mips64r2/valid.s @@ -3,189 +3,231 @@ # RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s .set noat - abs.d $f7,$f25 # CHECK: encoding - abs.s $f9,$f16 - add $s7,$s2,$a1 - add.d $f1,$f7,$f29 - add.s $f8,$f21,$f24 - addi $t5,$t1,26322 - addu $t1,$a0,$a2 - and $s7,$v0,$t4 - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 - ceil.l.d $f1,$f3 - ceil.l.s $f18,$f13 - ceil.w.d $f11,$f25 - ceil.w.s $f6,$f20 - cfc1 $s1,$21 - clo $t3,$a1 - clz $sp,$gp - ctc1 $a2,$26 - cvt.d.l $f4,$f16 - cvt.d.s $f22,$f28 - cvt.d.w $f26,$f11 - cvt.l.d $f24,$f15 - cvt.l.s $f11,$f29 - cvt.s.d $f26,$f8 - cvt.s.l $f15,$f30 - cvt.s.w $f22,$f15 - cvt.w.d $f20,$f14 - cvt.w.s $f20,$f24 - dadd $s3,$at,$ra - daddi $sp,$s4,-27705 - daddiu $k0,$s6,-4586 - dclo $s2,$a2 - dclz $s0,$t9 - deret - di $s8 - ddiv $zero,$k0,$s3 - ddivu $zero,$s0,$s1 - div $zero,$t9,$t3 - div.d $f29,$f20,$f27 - div.s $f4,$f5,$f15 - divu $zero,$t9,$t7 - dmfc1 $t4,$f13 - dmtc1 $s0,$f14 - dmult $s7,$t1 - dmultu $a1,$a2 - dsbh $v1,$t6 - dshd $v0,$sp - dsllv $zero,$s4,$t4 - dsrav $gp,$s2,$s3 - dsrlv $s3,$t6,$s4 - dsub $a3,$s6,$t0 - dsubu $a1,$a1,$k0 - ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - ei $t6 - eret - floor.l.d $f26,$f7 - floor.l.s $f12,$f5 - floor.w.d $f14,$f11 - floor.w.s $f8,$f9 - lb $t8,-14515($t2) - lbu $t0,30195($v1) - ld $sp,-28645($s1) - ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) - ldl $t8,-4167($t8) - ldr $t6,-30358($s4) - ldxc1 $f8,$s7($t7) - lh $t3,-8556($s5) - lhu $s3,-22851($v0) - li $at,-29773 - li $zero,-29889 - ll $v0,-7321($s2) - lld $zero,-14736($ra) - luxc1 $f19,$s6($s5) - lw $t0,5674($a1) - lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) - lwl $s4,-4231($t7) - lwr $zero,-19147($gp) - lwu $s3,-24086($v1) - lwxc1 $f12,$s1($s8) - madd $s6,$t5 - madd $zero,$t1 - madd.s $f1,$f31,$f19,$f25 - maddu $s3,$gp - maddu $t8,$s2 - mfc0 $a2,$14,1 - mfc1 $a3,$f27 - mfhc1 $s8,$f24 - mfhi $s3 - mfhi $sp - mflo $s1 - mov.d $f20,$f14 - mov.s $f2,$f27 - move $a0,$a3 - move $s5,$a0 - move $s8,$a0 - move $t9,$a2 - movf $gp,$t0,$fcc7 - movf.d $f6,$f11,$fcc5 - movf.s $f23,$f5,$fcc6 - movn $v1,$s1,$s0 - movn.d $f27,$f21,$k0 - movn.s $f12,$f0,$s7 - movt $zero,$s4,$fcc5 - movt.d $f0,$f2,$fcc0 - movt.s $f30,$f2,$fcc1 - movz $a1,$s6,$t1 - movz.d $f12,$f29,$t1 - movz.s $f25,$f7,$v1 - msub $s7,$k1 - msub.s $f12,$f19,$f10,$f16 - msubu $t7,$a1 - mtc0 $t1,$29,3 - mtc1 $s8,$f9 - mthc1 $zero,$f16 - mthi $s1 - mtlo $sp - mtlo $t9 - mul $s0,$s4,$at - mul.d $f20,$f20,$f16 - mul.s $f30,$f10,$f2 - mult $sp,$s4 - mult $sp,$v0 - multu $gp,$k0 - multu $t1,$s2 - neg.d $f27,$f18 - neg.s $f1,$f15 - nmadd.s $f0,$f5,$f25,$f12 - nmsub.s $f1,$f24,$f19,$f4 - nop - nor $a3,$zero,$a3 - or $t4,$s0,$sp - pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] - rdhwr $sp,$11 - round.l.d $f12,$f1 - round.l.s $f25,$f5 - round.w.d $f6,$f4 - round.w.s $f27,$f28 - sb $s6,-19857($t6) - sc $t7,18904($s3) - scd $t7,-8243($sp) - sd $t4,5835($t2) - sdc1 $f31,30574($t5) - sdc2 $20,23157($s2) - sdl $a3,-20961($s8) - sdr $t3,-20423($t4) - sdxc1 $f11,$t2($t6) - seb $t9,$t7 - seh $v1,$t4 - sh $t6,-6704($t7) - sllv $a3,$zero,$t1 - slt $s7,$t3,$k1 - slti $s1,$t2,9489 - sltiu $t9,$t9,-15531 - sltu $s4,$s5,$t3 - sqrt.d $f17,$f22 - sqrt.s $f0,$f1 - srav $s1,$s7,$sp - srlv $t9,$s4,$a0 - ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] - sub $s6,$s3,$t4 - sub.d $f18,$f3,$f17 - sub.s $f23,$f22,$f22 - subu $sp,$s6,$s6 - suxc1 $f12,$k1($t5) - sw $ra,-10160($sp) - swc1 $f6,-8465($t8) - swc2 $25,24880($s0) - swl $t7,13694($s3) - swr $s1,-26590($t6) - swxc1 $f19,$t4($k0) - teqi $s5,-17504 - tgei $s1,5025 - tgeiu $sp,-28621 - tlti $t6,-21059 - tltiu $ra,-5076 - tnei $t4,-29647 - trunc.l.d $f23,$f23 - trunc.l.s $f28,$f31 - trunc.w.d $f22,$f15 - trunc.w.s $f28,$f30 - xor $s2,$a0,$s8 - wsbh $k1,$t1 + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addu $9,$a0,$a2 + and $s7,$v0,$12 + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + clo $11,$a1 + clz $sp,$gp + ctc1 $a2,$26 + cvt.d.l $f4,$f16 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.l $f15,$f30 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + dadd $s3,$at,$ra + daddi $sp,$s4,-27705 + daddiu $k0,$s6,-4586 + daddu $s3,$at,$ra + dclo $s2,$a2 + dclz $s0,$25 + deret + di $s8 + ddiv $zero,$k0,$s3 + ddivu $zero,$s0,$s1 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + dmfc1 $12,$f13 + dmtc1 $s0,$f14 + dmult $s7,$9 + dmultu $a1,$a2 + drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfa] + drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfa] + drotr32 $1,15 # CHECK: drotr32 $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfe] + drotr32 $1,$14,15 # CHECK: drotr32 $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfe] + drotrv $1,$14,$15 # CHECK: drotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x56] + dsbh $v1,$14 + dshd $v0,$sp + dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8] + dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8] + dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbb] + dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbb] + dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] + dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf] + dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] + dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] + dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] + dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] + dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + dsub $a3,$s6,$8 + dsubu $a1,$a1,$k0 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + ei $14 + eret + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + lb $24,-14515($10) + lbu $8,30195($v1) + ld $sp,-28645($s1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) + ldl $24,-4167($24) + ldr $14,-30358($s4) + ldxc1 $f8,$s7($15) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) + lld $zero,-14736($ra) + luxc1 $f19,$s6($s5) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwu $s3,-24086($v1) + lwxc1 $f12,$s1($s8) + madd $s6,$13 + madd $zero,$9 + madd.s $f1,$f31,$f19,$f25 + maddu $s3,$gp + maddu $24,$s2 + mfc0 $a2,$14,1 + mfc1 $a3,$f27 + mfhc1 $s8,$f24 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $a0,$a3 + move $s5,$a0 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + msub $s7,$k1 + msub.s $f12,$f19,$f10,$f16 + msubu $15,$a1 + mtc0 $9,$29,3 + mtc1 $s8,$f9 + mthc1 $zero,$f16 + mthi $s1 + mtlo $sp + mtlo $25 + mul $s0,$s4,$at + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nmadd.s $f0,$f5,$f25,$f12 + nmsub.s $f1,$f24,$f19,$f4 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] + rdhwr $sp,$11 + rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] + rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] + rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] + round.l.d $f12,$f1 + round.l.s $f25,$f5 + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) + scd $15,-8243($sp) + sd $12,5835($10) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) + sdl $a3,-20961($s8) + sdr $11,-20423($12) + sdxc1 $f11,$10($14) + seb $25,$15 + seh $v1,$12 + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + suxc1 $f12,$k1($13) + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) + swl $15,13694($s3) + swr $s1,-26590($14) + swxc1 $f19,$12($k0) + teqi $s5,-17504 + tgei $s1,5025 + tgeiu $sp,-28621 + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlti $14,-21059 + tltiu $ra,-5076 + tnei $12,-29647 + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 + wsbh $k1,$9 diff --git a/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s b/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s new file mode 100644 index 0000000..f7949bb --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s @@ -0,0 +1,15 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips64r6/invalid-mips1.s b/test/MC/Mips/mips64r6/invalid-mips1.s new file mode 100644 index 0000000..1225005 --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips1.s @@ -0,0 +1,8 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64r6/invalid-mips2.s b/test/MC/Mips/mips64r6/invalid-mips2.s new file mode 100644 index 0000000..0638e78 --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips2.s @@ -0,0 +1,14 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlti $14,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tnei $12,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s b/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s new file mode 100644 index 0000000..7424f49 --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s @@ -0,0 +1,23 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ldl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sdr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + ldle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + ldre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + sdle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + sdre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips64r6/invalid-mips3.s b/test/MC/Mips/mips64r6/invalid-mips3.s new file mode 100644 index 0000000..0638e78 --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips3.s @@ -0,0 +1,14 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlti $14,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tnei $12,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s b/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s new file mode 100644 index 0000000..6b980e6 --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s @@ -0,0 +1,44 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + alnv.ps $f12,$f18,$f30,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + cvt.ps.pw $f3,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips64r6/relocations.s b/test/MC/Mips/mips64r6/relocations.s new file mode 100644 index 0000000..db84715 --- /dev/null +++ b/test/MC/Mips/mips64r6/relocations.s @@ -0,0 +1,55 @@ +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: | FileCheck %s -check-prefix=CHECK-FIXUP +# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips64r6 \ +# RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF +#------------------------------------------------------------------------------ +# Check that the assembler can handle the documented syntax for fixups. +#------------------------------------------------------------------------------ +# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16 +# CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16 +# CHECK-FIXUP: beqzc $9, bar # encoding: [0xd9,0b001AAAAA,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2 +# CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC21_S2 +# CHECK-FIXUP: balc bar # encoding: [0b111010AA,A,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2 +# CHECK-FIXUP: bc bar # encoding: [0b110010AA,A,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC26_S2 +# CHECK-FIXUP: aluipc $2, %pcrel_hi(bar) # encoding: [0xec,0x5f,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar@PCREL_HI16, +# CHECK-FIXUP: kind: fixup_MIPS_PCHI16 +# CHECK-FIXUP: addiu $2, $2, %pcrel_lo(bar) # encoding: [0x24,0x42,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar@PCREL_LO16, +# CHECK-FIXUP: kind: fixup_MIPS_PCLO16 +#------------------------------------------------------------------------------ +# Check that the appropriate relocations were created. +#------------------------------------------------------------------------------ +# CHECK-ELF: Relocations [ +# CHECK-ELF: 0x0 R_MIPS_PC16 bar 0x0 +# CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0 +# CHECK-ELF: 0x8 R_MIPS_PC21_S2 bar 0x0 +# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0 +# CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0 +# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0 +# CHECK-ELF: 0x18 R_MIPS_PCHI16 bar 0x0 +# CHECK-ELF: 0x1C R_MIPS_PCLO16 bar 0x0 +# CHECK-ELF: ] + + beqc $5, $6, bar + bnec $5, $6, bar + beqzc $9, bar + bnezc $9, bar + balc bar + bc bar + aluipc $2, %pcrel_hi(bar) + addiu $2, $2, %pcrel_lo(bar) diff --git a/test/MC/Mips/mips64r6/valid-xfail.s b/test/MC/Mips/mips64r6/valid-xfail.s new file mode 100644 index 0000000..a751225 --- /dev/null +++ b/test/MC/Mips/mips64r6/valid-xfail.s @@ -0,0 +1,19 @@ +# Instructions that should be valid but currently fail for known reasons (e.g. +# they aren't implemented yet). +# This test is set up to XPASS if any instruction generates an encoding. +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 | not FileCheck %s +# CHECK-NOT: encoding +# XFAIL: * + + .set noat + bovc $0, $2, 4 # TODO: bovc $0, $2, 4 # encoding: [0x20,0x40,0x00,0x01] + bovc $2, $4, 4 # TODO: bovc $2, $4, 4 # encoding: [0x20,0x82,0x00,0x01] + bnvc $0, $2, 4 # TODO: bnvc $0, $2, 4 # encoding: [0x60,0x40,0x00,0x01] + bnvc $2, $4, 4 # TODO: bnvc $2, $4, 4 # encoding: [0x60,0x82,0x00,0x01] + beqc $0, $6, 256 # TODO: beqc $6, $zero, 256 # encoding: [0x20,0xc0,0x00,0x40] + beqc $5, $0, 256 # TODO: beqc $5, $zero, 256 # encoding: [0x20,0xa0,0x00,0x40] + beqc $6, $5, 256 # TODO: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40] + bnec $0, $6, 256 # TODO: bnec $6, $zero, 256 # encoding: [0x60,0xc0,0x00,0x40] + bnec $5, $0, 256 # TODO: bnec $5, $zero, 256 # encoding: [0x60,0xa0,0x00,0x40] + bnec $6, $5, 256 # TODO: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40] diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s new file mode 100644 index 0000000..efdfc7f --- /dev/null +++ b/test/MC/Mips/mips64r6/valid.s @@ -0,0 +1,139 @@ +# Instructions that are valid +# +# Branches have some unusual encoding rules in MIPS32r6 so we need to test: +# rs == 0 +# rs != 0 +# rt == 0 +# rt != 0 +# rs < rt +# rs == rt +# rs > rt +# appropriately for each branch instruction +# +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 | FileCheck %s + + .set noat + # FIXME: Add the instructions carried forward from older ISA's + addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19] + align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0] + aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] + aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9] + auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff] + balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8] + bc 14572256 # CHECK: bc 14572256 # encoding: [0xc8,0x37,0x96,0xb8] + bc1eqz $f0,4 # CHECK: bc1eqz $f0, 4 # encoding: [0x45,0x20,0x00,0x01] + bc1eqz $f31,4 # CHECK: bc1eqz $f31, 4 # encoding: [0x45,0x3f,0x00,0x01] + bc1nez $f0,4 # CHECK: bc1nez $f0, 4 # encoding: [0x45,0xa0,0x00,0x01] + bc1nez $f31,4 # CHECK: bc1nez $f31, 4 # encoding: [0x45,0xbf,0x00,0x01] + bc2eqz $0,8 # CHECK: bc2eqz $0, 8 # encoding: [0x49,0x20,0x00,0x02] + bc2eqz $31,8 # CHECK: bc2eqz $31, 8 # encoding: [0x49,0x3f,0x00,0x02] + bc2nez $0,8 # CHECK: bc2nez $0, 8 # encoding: [0x49,0xa0,0x00,0x02] + bc2nez $31,8 # CHECK: bc2nez $31, 8 # encoding: [0x49,0xbf,0x00,0x02] + # beqc requires rs < rt && rs != 0 but we also accept when this is not true. See also bovc + # FIXME: Testcases are in valid-xfail.s at the moment + beqc $5, $6, 256 # CHECK: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40] + beqzalc $2, 1332 # CHECK: beqzalc $2, 1332 # encoding: [0x20,0x02,0x01,0x4d] + # bnec requires rs < rt && rs != 0 but we accept when this is not true. See also bnvc + # FIXME: Testcases are in valid-xfail.s at the moment + bnec $5, $6, 256 # CHECK: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40] + bnezalc $2, 1332 # CHECK: bnezalc $2, 1332 # encoding: [0x60,0x02,0x01,0x4d] + beqzc $5, 72256 # CHECK: beqzc $5, 72256 # encoding: [0xd8,0xa0,0x46,0x90] + bgezalc $2, 1332 # CHECK: bgezalc $2, 1332 # encoding: [0x18,0x42,0x01,0x4d] + bnezc $5, 72256 # CHECK: bnezc $5, 72256 # encoding: [0xf8,0xa0,0x46,0x90] + bltzc $5, 256 # CHECK: bltzc $5, 256 # encoding: [0x5c,0xa5,0x00,0x40] + bgezc $5, 256 # CHECK: bgezc $5, 256 # encoding: [0x58,0xa5,0x00,0x40] + bgtzalc $2, 1332 # CHECK: bgtzalc $2, 1332 # encoding: [0x1c,0x02,0x01,0x4d] + blezc $5, 256 # CHECK: blezc $5, 256 # encoding: [0x58,0x05,0x00,0x40] + bltzalc $2, 1332 # CHECK: bltzalc $2, 1332 # encoding: [0x1c,0x42,0x01,0x4d] + bgtzc $5, 256 # CHECK: bgtzc $5, 256 # encoding: [0x5c,0x05,0x00,0x40] + bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20] + blezalc $2, 1332 # CHECK: blezalc $2, 1332 # encoding: [0x18,0x02,0x01,0x4d] + # bnvc requires that rs >= rt but we accept both. See also bnec + bnvc $0, $0, 4 # CHECK: bnvc $zero, $zero, 4 # encoding: [0x60,0x00,0x00,0x01] + bnvc $2, $0, 4 # CHECK: bnvc $2, $zero, 4 # encoding: [0x60,0x40,0x00,0x01] + bnvc $4, $2, 4 # CHECK: bnvc $4, $2, 4 # encoding: [0x60,0x82,0x00,0x01] + # bovc requires that rs >= rt but we accept both. See also beqc + bovc $0, $0, 4 # CHECK: bovc $zero, $zero, 4 # encoding: [0x20,0x00,0x00,0x01] + bovc $2, $0, 4 # CHECK: bovc $2, $zero, 4 # encoding: [0x20,0x40,0x00,0x01] + bovc $4, $2, 4 # CHECK: bovc $4, $2, 4 # encoding: [0x20,0x82,0x00,0x01] + cmp.f.s $f2,$f3,$f4 # CHECK: cmp.f.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80] + cmp.f.d $f2,$f3,$f4 # CHECK: cmp.f.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80] + cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81] + cmp.un.d $f2,$f3,$f4 # CHECK: cmp.un.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x81] + cmp.eq.s $f2,$f3,$f4 # CHECK: cmp.eq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x82] + cmp.eq.d $f2,$f3,$f4 # CHECK: cmp.eq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x82] + cmp.ueq.s $f2,$f3,$f4 # CHECK: cmp.ueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x83] + cmp.ueq.d $f2,$f3,$f4 # CHECK: cmp.ueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x83] + cmp.olt.s $f2,$f3,$f4 # CHECK: cmp.olt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x84] + cmp.olt.d $f2,$f3,$f4 # CHECK: cmp.olt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x84] + cmp.ult.s $f2,$f3,$f4 # CHECK: cmp.ult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x85] + cmp.ult.d $f2,$f3,$f4 # CHECK: cmp.ult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x85] + cmp.ole.s $f2,$f3,$f4 # CHECK: cmp.ole.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x86] + cmp.ole.d $f2,$f3,$f4 # CHECK: cmp.ole.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x86] + cmp.ule.s $f2,$f3,$f4 # CHECK: cmp.ule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x87] + cmp.ule.d $f2,$f3,$f4 # CHECK: cmp.ule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x87] + cmp.sf.s $f2,$f3,$f4 # CHECK: cmp.sf.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x88] + cmp.sf.d $f2,$f3,$f4 # CHECK: cmp.sf.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x88] + cmp.ngle.s $f2,$f3,$f4 # CHECK: cmp.ngle.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x89] + cmp.ngle.d $f2,$f3,$f4 # CHECK: cmp.ngle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x89] + cmp.seq.s $f2,$f3,$f4 # CHECK: cmp.seq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8a] + cmp.seq.d $f2,$f3,$f4 # CHECK: cmp.seq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8a] + cmp.ngl.s $f2,$f3,$f4 # CHECK: cmp.ngl.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8b] + cmp.ngl.d $f2,$f3,$f4 # CHECK: cmp.ngl.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8b] + cmp.lt.s $f2,$f3,$f4 # CHECK: cmp.lt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8c] + cmp.lt.d $f2,$f3,$f4 # CHECK: cmp.lt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8c] + cmp.nge.s $f2,$f3,$f4 # CHECK: cmp.nge.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8d] + cmp.nge.d $f2,$f3,$f4 # CHECK: cmp.nge.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8d] + cmp.le.s $f2,$f3,$f4 # CHECK: cmp.le.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8e] + cmp.le.d $f2,$f3,$f4 # CHECK: cmp.le.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e] + cmp.ngt.s $f2,$f3,$f4 # CHECK: cmp.ngt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f] + cmp.ngt.d $f2,$f3,$f4 # CHECK: cmp.ngt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f] + dalign $4,$2,$3,5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64] + daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34] + dahi $3,0x5678 # CHECK: dahi $3, 22136 # encoding: [0x04,0x66,0x56,0x78] + dati $3,0xabcd # CHECK: dati $3, 43981 # encoding: [0x04,0x7e,0xab,0xcd] + dbitswap $4, $2 # CHECK: dbitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x24] + div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a] + divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b] + jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00] + jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00] + mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] + modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb] + ddiv $2,$3,$4 # CHECK: ddiv $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9e] + ddivu $2,$3,$4 # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f] + dmod $2,$3,$4 # CHECK: dmod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xde] + dmodu $2,$3,$4 # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf] + lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43] + lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43] +# mul $2,$3,$4 # CHECK-TODO: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98] + muh $2,$3,$4 # CHECK: muh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd8] + mulu $2,$3,$4 # CHECK: mulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x99] + muhu $2,$3,$4 # CHECK: muhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd9] + dmul $2,$3,$4 # CHECK: dmul $2, $3, $4 # encoding: [0x00,0x64,0x10,0xb8] + dmuh $2,$3,$4 # CHECK: dmuh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xf8] + dmulu $2,$3,$4 # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xb9] + dmuhu $2,$3,$4 # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xf9] + maddf.s $f2,$f3,$f4 # CHECK: maddf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x98] + maddf.d $f2,$f3,$f4 # CHECK: maddf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x98] + msubf.s $f2,$f3,$f4 # CHECK: msubf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x99] + msubf.d $f2,$f3,$f4 # CHECK: msubf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x99] + sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10] + sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10] + seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35] + selnez $2,$3,$4 # CHECK: selnez $2, $3, $4 # encoding: [0x00,0x64,0x10,0x37] + max.s $f0, $f2, $f4 # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d] + max.d $f0, $f2, $f4 # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d] + min.s $f0, $f2, $f4 # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c] + min.d $f0, $f2, $f4 # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c] + maxa.s $f0, $f2, $f4 # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f] + maxa.d $f0, $f2, $f4 # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f] + mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e] + mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e] + seleqz.s $f0, $f2, $f4 # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14] + seleqz.d $f0, $f2, $f4 # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14] + selnez.s $f0, $f2, $f4 # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17] + selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17] + rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a] + rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a] + class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b] + class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b] diff --git a/test/MC/Mips/mips_directives.s b/test/MC/Mips/mips_directives.s index 6780dd0..1a7d61f 100644 --- a/test/MC/Mips/mips_directives.s +++ b/test/MC/Mips/mips_directives.s @@ -51,7 +51,7 @@ $BB0_4: .set $tmp7, $BB0_4-$BB0_2 .set f6,$f6 # CHECK: abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85] -# CHECK: lui $1, %hi($tmp7) # encoding: [0x3c'A',0x01'A',0x00,0x00] +# CHECK: lui $1, %hi($tmp7) # encoding: [0x3c,0x01,A,A] # CHECK: # fixup A - offset: 0, value: ($tmp7)@ABS_HI, kind: fixup_Mips_HI16 abs.s f6,FPU_MASK lui $1, %hi($tmp7) diff --git a/test/MC/Mips/mips_gprel16.s b/test/MC/Mips/mips_gprel16.s index 716c75e..9dd3fa3 100644 --- a/test/MC/Mips/mips_gprel16.s +++ b/test/MC/Mips/mips_gprel16.s @@ -6,6 +6,9 @@ // RUN: llvm-mc -mcpu=mips32r2 -triple=mipsel-pc-linux -filetype=obj -relocation-model=static %s -o - \ // RUN: | llvm-objdump -disassemble -mattr +mips32r2 - \ // RUN: | FileCheck %s +// RUN: llvm-mc -mcpu=mips32r2 -triple=mips-pc-linux -filetype=obj -relocation-model=static %s -o - \ +// RUN: | llvm-objdump -disassemble -mattr +mips32r2 - \ +// RUN: | FileCheck %s .text .abicalls diff --git a/test/MC/Mips/msa/test_2r.s b/test/MC/Mips/msa/test_2r.s index b657d5f..01bea64 100644 --- a/test/MC/Mips/msa/test_2r.s +++ b/test/MC/Mips/msa/test_2r.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: fill.b $w30, $9 # encoding: [0x7b,0x00,0x4f,0x9e] # CHECK: fill.h $w31, $23 # encoding: [0x7b,0x01,0xbf,0xde] # CHECK: fill.w $w16, $24 # encoding: [0x7b,0x02,0xc4,0x1e] @@ -20,22 +16,6 @@ # CHECK: pcnt.w $w23, $w9 # encoding: [0x7b,0x06,0x4d,0xde] # CHECK: pcnt.d $w21, $w24 # encoding: [0x7b,0x07,0xc5,0x5e] -# CHECKOBJDUMP: fill.b $w30, $9 -# CHECKOBJDUMP: fill.h $w31, $23 -# CHECKOBJDUMP: fill.w $w16, $24 -# CHECKOBJDUMP: nloc.b $w21, $w0 -# CHECKOBJDUMP: nloc.h $w18, $w31 -# CHECKOBJDUMP: nloc.w $w2, $w23 -# CHECKOBJDUMP: nloc.d $w4, $w10 -# CHECKOBJDUMP: nlzc.b $w31, $w2 -# CHECKOBJDUMP: nlzc.h $w27, $w22 -# CHECKOBJDUMP: nlzc.w $w10, $w29 -# CHECKOBJDUMP: nlzc.d $w25, $w9 -# CHECKOBJDUMP: pcnt.b $w20, $w18 -# CHECKOBJDUMP: pcnt.h $w0, $w8 -# CHECKOBJDUMP: pcnt.w $w23, $w9 -# CHECKOBJDUMP: pcnt.d $w21, $w24 - fill.b $w30, $9 fill.h $w31, $23 fill.w $w16, $24 diff --git a/test/MC/Mips/msa/test_2r_msa64.s b/test/MC/Mips/msa/test_2r_msa64.s index 743fb88..f6e35c4 100644 --- a/test/MC/Mips/msa/test_2r_msa64.s +++ b/test/MC/Mips/msa/test_2r_msa64.s @@ -1,11 +1,5 @@ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips64 -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: fill.d $w27, $9 # encoding: [0x7b,0x03,0x4e,0xde] -# CHECKOBJDUMP: fill.d $w27, $9 - fill.d $w27, $9 diff --git a/test/MC/Mips/msa/test_2rf.s b/test/MC/Mips/msa/test_2rf.s index 284a7d9..5d41545 100644 --- a/test/MC/Mips/msa/test_2rf.s +++ b/test/MC/Mips/msa/test_2rf.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: fclass.w $w26, $w12 # encoding: [0x7b,0x20,0x66,0x9e] # CHECK: fclass.d $w24, $w17 # encoding: [0x7b,0x21,0x8e,0x1e] # CHECK: fexupl.w $w8, $w0 # encoding: [0x7b,0x30,0x02,0x1e] @@ -37,39 +33,6 @@ # CHECK: ftrunc_u.w $w17, $w15 # encoding: [0x7b,0x24,0x7c,0x5e] # CHECK: ftrunc_u.d $w5, $w27 # encoding: [0x7b,0x25,0xd9,0x5e] -# CHECKOBJDUMP: fclass.w $w26, $w12 -# CHECKOBJDUMP: fclass.d $w24, $w17 -# CHECKOBJDUMP: fexupl.w $w8, $w0 -# CHECKOBJDUMP: fexupl.d $w17, $w29 -# CHECKOBJDUMP: fexupr.w $w13, $w4 -# CHECKOBJDUMP: fexupr.d $w5, $w2 -# CHECKOBJDUMP: ffint_s.w $w20, $w29 -# CHECKOBJDUMP: ffint_s.d $w12, $w15 -# CHECKOBJDUMP: ffint_u.w $w7, $w27 -# CHECKOBJDUMP: ffint_u.d $w19, $w16 -# CHECKOBJDUMP: ffql.w $w31, $w13 -# CHECKOBJDUMP: ffql.d $w12, $w13 -# CHECKOBJDUMP: ffqr.w $w27, $w30 -# CHECKOBJDUMP: ffqr.d $w30, $w15 -# CHECKOBJDUMP: flog2.w $w25, $w31 -# CHECKOBJDUMP: flog2.d $w18, $w10 -# CHECKOBJDUMP: frint.w $w7, $w15 -# CHECKOBJDUMP: frint.d $w21, $w22 -# CHECKOBJDUMP: frcp.w $w19, $w0 -# CHECKOBJDUMP: frcp.d $w4, $w14 -# CHECKOBJDUMP: frsqrt.w $w12, $w17 -# CHECKOBJDUMP: frsqrt.d $w23, $w11 -# CHECKOBJDUMP: fsqrt.w $w0, $w11 -# CHECKOBJDUMP: fsqrt.d $w15, $w12 -# CHECKOBJDUMP: ftint_s.w $w30, $w5 -# CHECKOBJDUMP: ftint_s.d $w5, $w23 -# CHECKOBJDUMP: ftint_u.w $w20, $w14 -# CHECKOBJDUMP: ftint_u.d $w23, $w21 -# CHECKOBJDUMP: ftrunc_s.w $w29, $w17 -# CHECKOBJDUMP: ftrunc_s.d $w12, $w27 -# CHECKOBJDUMP: ftrunc_u.w $w17, $w15 -# CHECKOBJDUMP: ftrunc_u.d $w5, $w27 - fclass.w $w26, $w12 fclass.d $w24, $w17 fexupl.w $w8, $w0 diff --git a/test/MC/Mips/msa/test_3r.s b/test/MC/Mips/msa/test_3r.s index d6b33f1..df2e1e1 100644 --- a/test/MC/Mips/msa/test_3r.s +++ b/test/MC/Mips/msa/test_3r.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: add_a.b $w26, $w9, $w4 # encoding: [0x78,0x04,0x4e,0x90] # CHECK: add_a.h $w23, $w27, $w31 # encoding: [0x78,0x3f,0xdd,0xd0] # CHECK: add_a.w $w11, $w6, $w22 # encoding: [0x78,0x56,0x32,0xd0] @@ -247,249 +243,6 @@ # CHECK: vshf.w $w16, $w30, $w25 # encoding: [0x78,0x59,0xf4,0x15] # CHECK: vshf.d $w19, $w11, $w15 # encoding: [0x78,0x6f,0x5c,0xd5] -# CHECKOBJDUMP: add_a.b $w26, $w9, $w4 -# CHECKOBJDUMP: add_a.h $w23, $w27, $w31 -# CHECKOBJDUMP: add_a.w $w11, $w6, $w22 -# CHECKOBJDUMP: add_a.d $w6, $w10, $w0 -# CHECKOBJDUMP: adds_a.b $w19, $w24, $w19 -# CHECKOBJDUMP: adds_a.h $w25, $w6, $w4 -# CHECKOBJDUMP: adds_a.w $w25, $w17, $w27 -# CHECKOBJDUMP: adds_a.d $w15, $w18, $w26 -# CHECKOBJDUMP: adds_s.b $w29, $w11, $w19 -# CHECKOBJDUMP: adds_s.h $w5, $w23, $w26 -# CHECKOBJDUMP: adds_s.w $w16, $w14, $w13 -# CHECKOBJDUMP: adds_s.d $w2, $w14, $w28 -# CHECKOBJDUMP: adds_u.b $w3, $w17, $w14 -# CHECKOBJDUMP: adds_u.h $w10, $w30, $w4 -# CHECKOBJDUMP: adds_u.w $w15, $w18, $w20 -# CHECKOBJDUMP: adds_u.d $w30, $w10, $w9 -# CHECKOBJDUMP: addv.b $w24, $w20, $w21 -# CHECKOBJDUMP: addv.h $w4, $w13, $w27 -# CHECKOBJDUMP: addv.w $w19, $w11, $w14 -# CHECKOBJDUMP: addv.d $w2, $w21, $w31 -# CHECKOBJDUMP: asub_s.b $w23, $w16, $w3 -# CHECKOBJDUMP: asub_s.h $w22, $w17, $w25 -# CHECKOBJDUMP: asub_s.w $w24, $w1, $w9 -# CHECKOBJDUMP: asub_s.d $w13, $w12, $w12 -# CHECKOBJDUMP: asub_u.b $w10, $w29, $w11 -# CHECKOBJDUMP: asub_u.h $w18, $w9, $w15 -# CHECKOBJDUMP: asub_u.w $w10, $w19, $w31 -# CHECKOBJDUMP: asub_u.d $w17, $w10, $w0 -# CHECKOBJDUMP: ave_s.b $w2, $w5, $w1 -# CHECKOBJDUMP: ave_s.h $w16, $w19, $w9 -# CHECKOBJDUMP: ave_s.w $w17, $w31, $w5 -# CHECKOBJDUMP: ave_s.d $w27, $w25, $w10 -# CHECKOBJDUMP: ave_u.b $w16, $w19, $w9 -# CHECKOBJDUMP: ave_u.h $w28, $w28, $w11 -# CHECKOBJDUMP: ave_u.w $w11, $w12, $w11 -# CHECKOBJDUMP: ave_u.d $w30, $w19, $w28 -# CHECKOBJDUMP: aver_s.b $w26, $w16, $w2 -# CHECKOBJDUMP: aver_s.h $w31, $w27, $w27 -# CHECKOBJDUMP: aver_s.w $w28, $w18, $w25 -# CHECKOBJDUMP: aver_s.d $w29, $w21, $w27 -# CHECKOBJDUMP: aver_u.b $w29, $w26, $w3 -# CHECKOBJDUMP: aver_u.h $w18, $w18, $w9 -# CHECKOBJDUMP: aver_u.w $w17, $w25, $w29 -# CHECKOBJDUMP: aver_u.d $w22, $w22, $w19 -# CHECKOBJDUMP: bclr.b $w2, $w15, $w29 -# CHECKOBJDUMP: bclr.h $w16, $w21, $w28 -# CHECKOBJDUMP: bclr.w $w19, $w2, $w9 -# CHECKOBJDUMP: bclr.d $w27, $w31, $w4 -# CHECKOBJDUMP: binsl.b $w5, $w16, $w24 -# CHECKOBJDUMP: binsl.h $w30, $w5, $w10 -# CHECKOBJDUMP: binsl.w $w14, $w15, $w13 -# CHECKOBJDUMP: binsl.d $w23, $w20, $w12 -# CHECKOBJDUMP: binsr.b $w22, $w11, $w2 -# CHECKOBJDUMP: binsr.h $w0, $w26, $w6 -# CHECKOBJDUMP: binsr.w $w26, $w3, $w28 -# CHECKOBJDUMP: binsr.d $w0, $w0, $w21 -# CHECKOBJDUMP: bneg.b $w0, $w11, $w24 -# CHECKOBJDUMP: bneg.h $w28, $w16, $w4 -# CHECKOBJDUMP: bneg.w $w3, $w26, $w19 -# CHECKOBJDUMP: bneg.d $w13, $w29, $w15 -# CHECKOBJDUMP: bset.b $w31, $w5, $w31 -# CHECKOBJDUMP: bset.h $w14, $w12, $w6 -# CHECKOBJDUMP: bset.w $w31, $w9, $w12 -# CHECKOBJDUMP: bset.d $w5, $w22, $w5 -# CHECKOBJDUMP: ceq.b $w31, $w31, $w18 -# CHECKOBJDUMP: ceq.h $w10, $w27, $w9 -# CHECKOBJDUMP: ceq.w $w9, $w5, $w14 -# CHECKOBJDUMP: ceq.d $w5, $w17, $w0 -# CHECKOBJDUMP: cle_s.b $w23, $w4, $w9 -# CHECKOBJDUMP: cle_s.h $w22, $w27, $w19 -# CHECKOBJDUMP: cle_s.w $w30, $w26, $w10 -# CHECKOBJDUMP: cle_s.d $w18, $w5, $w10 -# CHECKOBJDUMP: cle_u.b $w1, $w25, $w0 -# CHECKOBJDUMP: cle_u.h $w7, $w0, $w29 -# CHECKOBJDUMP: cle_u.w $w25, $w18, $w1 -# CHECKOBJDUMP: cle_u.d $w6, $w0, $w30 -# CHECKOBJDUMP: clt_s.b $w25, $w2, $w21 -# CHECKOBJDUMP: clt_s.h $w2, $w19, $w9 -# CHECKOBJDUMP: clt_s.w $w23, $w8, $w16 -# CHECKOBJDUMP: clt_s.d $w7, $w30, $w12 -# CHECKOBJDUMP: clt_u.b $w2, $w31, $w13 -# CHECKOBJDUMP: clt_u.h $w16, $w31, $w23 -# CHECKOBJDUMP: clt_u.w $w3, $w24, $w9 -# CHECKOBJDUMP: clt_u.d $w7, $w0, $w1 -# CHECKOBJDUMP: div_s.b $w29, $w3, $w18 -# CHECKOBJDUMP: div_s.h $w17, $w16, $w13 -# CHECKOBJDUMP: div_s.w $w4, $w25, $w30 -# CHECKOBJDUMP: div_s.d $w31, $w9, $w20 -# CHECKOBJDUMP: div_u.b $w6, $w29, $w10 -# CHECKOBJDUMP: div_u.h $w24, $w21, $w14 -# CHECKOBJDUMP: div_u.w $w29, $w14, $w25 -# CHECKOBJDUMP: div_u.d $w31, $w1, $w21 -# CHECKOBJDUMP: dotp_s.h $w23, $w22, $w25 -# CHECKOBJDUMP: dotp_s.w $w20, $w14, $w5 -# CHECKOBJDUMP: dotp_s.d $w17, $w2, $w22 -# CHECKOBJDUMP: dotp_u.h $w13, $w2, $w6 -# CHECKOBJDUMP: dotp_u.w $w15, $w22, $w21 -# CHECKOBJDUMP: dotp_u.d $w4, $w16, $w26 -# CHECKOBJDUMP: dpadd_s.h $w1, $w28, $w22 -# CHECKOBJDUMP: dpadd_s.w $w10, $w1, $w12 -# CHECKOBJDUMP: dpadd_s.d $w3, $w21, $w27 -# CHECKOBJDUMP: dpadd_u.h $w17, $w5, $w20 -# CHECKOBJDUMP: dpadd_u.w $w24, $w8, $w16 -# CHECKOBJDUMP: dpadd_u.d $w15, $w29, $w16 -# CHECKOBJDUMP: dpsub_s.h $w4, $w11, $w12 -# CHECKOBJDUMP: dpsub_s.w $w4, $w7, $w6 -# CHECKOBJDUMP: dpsub_s.d $w31, $w12, $w28 -# CHECKOBJDUMP: dpsub_u.h $w4, $w25, $w17 -# CHECKOBJDUMP: dpsub_u.w $w19, $w25, $w16 -# CHECKOBJDUMP: dpsub_u.d $w7, $w10, $w26 -# CHECKOBJDUMP: hadd_s.h $w28, $w24, $w2 -# CHECKOBJDUMP: hadd_s.w $w24, $w17, $w11 -# CHECKOBJDUMP: hadd_s.d $w17, $w15, $w20 -# CHECKOBJDUMP: hadd_u.h $w12, $w29, $w17 -# CHECKOBJDUMP: hadd_u.w $w9, $w5, $w6 -# CHECKOBJDUMP: hadd_u.d $w1, $w20, $w6 -# CHECKOBJDUMP: hsub_s.h $w16, $w14, $w29 -# CHECKOBJDUMP: hsub_s.w $w9, $w13, $w11 -# CHECKOBJDUMP: hsub_s.d $w30, $w18, $w14 -# CHECKOBJDUMP: hsub_u.h $w7, $w12, $w14 -# CHECKOBJDUMP: hsub_u.w $w21, $w5, $w5 -# CHECKOBJDUMP: hsub_u.d $w11, $w12, $w31 -# CHECKOBJDUMP: ilvev.b $w18, $w16, $w30 -# CHECKOBJDUMP: ilvev.h $w14, $w0, $w13 -# CHECKOBJDUMP: ilvev.w $w12, $w25, $w22 -# CHECKOBJDUMP: ilvev.d $w30, $w27, $w3 -# CHECKOBJDUMP: ilvl.b $w29, $w3, $w21 -# CHECKOBJDUMP: ilvl.h $w27, $w10, $w17 -# CHECKOBJDUMP: ilvl.w $w6, $w1, $w0 -# CHECKOBJDUMP: ilvl.d $w3, $w16, $w24 -# CHECKOBJDUMP: ilvod.b $w11, $w5, $w20 -# CHECKOBJDUMP: ilvod.h $w18, $w13, $w31 -# CHECKOBJDUMP: ilvod.w $w29, $w16, $w24 -# CHECKOBJDUMP: ilvod.d $w22, $w12, $w29 -# CHECKOBJDUMP: ilvr.b $w4, $w30, $w6 -# CHECKOBJDUMP: ilvr.h $w28, $w19, $w29 -# CHECKOBJDUMP: ilvr.w $w18, $w20, $w21 -# CHECKOBJDUMP: ilvr.d $w23, $w30, $w12 -# CHECKOBJDUMP: maddv.b $w17, $w31, $w29 -# CHECKOBJDUMP: maddv.h $w7, $w24, $w9 -# CHECKOBJDUMP: maddv.w $w22, $w22, $w20 -# CHECKOBJDUMP: maddv.d $w30, $w26, $w20 -# CHECKOBJDUMP: max_a.b $w23, $w11, $w23 -# CHECKOBJDUMP: max_a.h $w20, $w5, $w30 -# CHECKOBJDUMP: max_a.w $w7, $w18, $w30 -# CHECKOBJDUMP: max_a.d $w8, $w8, $w31 -# CHECKOBJDUMP: max_s.b $w10, $w1, $w19 -# CHECKOBJDUMP: max_s.h $w15, $w29, $w17 -# CHECKOBJDUMP: max_s.w $w15, $w29, $w14 -# CHECKOBJDUMP: max_s.d $w25, $w24, $w3 -# CHECKOBJDUMP: max_u.b $w12, $w24, $w5 -# CHECKOBJDUMP: max_u.h $w5, $w6, $w7 -# CHECKOBJDUMP: max_u.w $w16, $w4, $w7 -# CHECKOBJDUMP: max_u.d $w26, $w12, $w24 -# CHECKOBJDUMP: min_a.b $w4, $w26, $w1 -# CHECKOBJDUMP: min_a.h $w12, $w13, $w31 -# CHECKOBJDUMP: min_a.w $w28, $w20, $w0 -# CHECKOBJDUMP: min_a.d $w12, $w20, $w19 -# CHECKOBJDUMP: min_s.b $w19, $w3, $w14 -# CHECKOBJDUMP: min_s.h $w27, $w21, $w8 -# CHECKOBJDUMP: min_s.w $w0, $w14, $w30 -# CHECKOBJDUMP: min_s.d $w6, $w8, $w21 -# CHECKOBJDUMP: min_u.b $w22, $w26, $w8 -# CHECKOBJDUMP: min_u.h $w7, $w27, $w12 -# CHECKOBJDUMP: min_u.w $w8, $w20, $w14 -# CHECKOBJDUMP: min_u.d $w26, $w14, $w15 -# CHECKOBJDUMP: mod_s.b $w18, $w1, $w26 -# CHECKOBJDUMP: mod_s.h $w31, $w30, $w28 -# CHECKOBJDUMP: mod_s.w $w2, $w6, $w13 -# CHECKOBJDUMP: mod_s.d $w21, $w27, $w22 -# CHECKOBJDUMP: mod_u.b $w16, $w7, $w13 -# CHECKOBJDUMP: mod_u.h $w24, $w8, $w7 -# CHECKOBJDUMP: mod_u.w $w30, $w2, $w17 -# CHECKOBJDUMP: mod_u.d $w31, $w2, $w25 -# CHECKOBJDUMP: msubv.b $w14, $w5, $w12 -# CHECKOBJDUMP: msubv.h $w6, $w7, $w30 -# CHECKOBJDUMP: msubv.w $w13, $w2, $w21 -# CHECKOBJDUMP: msubv.d $w16, $w14, $w27 -# CHECKOBJDUMP: mulv.b $w20, $w3, $w13 -# CHECKOBJDUMP: mulv.h $w27, $w26, $w14 -# CHECKOBJDUMP: mulv.w $w10, $w29, $w3 -# CHECKOBJDUMP: mulv.d $w7, $w19, $w29 -# CHECKOBJDUMP: pckev.b $w5, $w27, $w7 -# CHECKOBJDUMP: pckev.h $w1, $w4, $w27 -# CHECKOBJDUMP: pckev.w $w30, $w20, $w0 -# CHECKOBJDUMP: pckev.d $w6, $w1, $w15 -# CHECKOBJDUMP: pckod.b $w18, $w28, $w30 -# CHECKOBJDUMP: pckod.h $w26, $w5, $w8 -# CHECKOBJDUMP: pckod.w $w9, $w4, $w2 -# CHECKOBJDUMP: pckod.d $w30, $w22, $w20 -# CHECKOBJDUMP: sld.b $w5, $w23[$12] -# CHECKOBJDUMP: sld.h $w1, $w23[$3] -# CHECKOBJDUMP: sld.w $w20, $w8[$9] -# CHECKOBJDUMP: sld.d $w7, $w23[$fp] -# CHECKOBJDUMP: sll.b $w3, $w0, $w17 -# CHECKOBJDUMP: sll.h $w17, $w27, $w3 -# CHECKOBJDUMP: sll.w $w16, $w7, $w6 -# CHECKOBJDUMP: sll.d $w9, $w0, $w26 -# CHECKOBJDUMP: splat.b $w28, $w1[$1] -# CHECKOBJDUMP: splat.h $w2, $w11[$11] -# CHECKOBJDUMP: splat.w $w22, $w0[$11] -# CHECKOBJDUMP: splat.d $w0, $w0[$2] -# CHECKOBJDUMP: sra.b $w28, $w4, $w17 -# CHECKOBJDUMP: sra.h $w13, $w9, $w3 -# CHECKOBJDUMP: sra.w $w27, $w21, $w19 -# CHECKOBJDUMP: sra.d $w30, $w8, $w23 -# CHECKOBJDUMP: srar.b $w19, $w18, $w18 -# CHECKOBJDUMP: srar.h $w7, $w23, $w8 -# CHECKOBJDUMP: srar.w $w1, $w12, $w2 -# CHECKOBJDUMP: srar.d $w21, $w7, $w14 -# CHECKOBJDUMP: srl.b $w12, $w3, $w19 -# CHECKOBJDUMP: srl.h $w23, $w31, $w20 -# CHECKOBJDUMP: srl.w $w18, $w27, $w11 -# CHECKOBJDUMP: srl.d $w3, $w12, $w26 -# CHECKOBJDUMP: srlr.b $w15, $w21, $w11 -# CHECKOBJDUMP: srlr.h $w21, $w13, $w19 -# CHECKOBJDUMP: srlr.w $w6, $w30, $w3 -# CHECKOBJDUMP: srlr.d $w1, $w2, $w14 -# CHECKOBJDUMP: subs_s.b $w25, $w15, $w1 -# CHECKOBJDUMP: subs_s.h $w28, $w25, $w22 -# CHECKOBJDUMP: subs_s.w $w10, $w12, $w21 -# CHECKOBJDUMP: subs_s.d $w4, $w20, $w18 -# CHECKOBJDUMP: subs_u.b $w21, $w6, $w25 -# CHECKOBJDUMP: subs_u.h $w3, $w10, $w7 -# CHECKOBJDUMP: subs_u.w $w9, $w15, $w10 -# CHECKOBJDUMP: subs_u.d $w7, $w19, $w10 -# CHECKOBJDUMP: subsus_u.b $w6, $w7, $w12 -# CHECKOBJDUMP: subsus_u.h $w6, $w29, $w19 -# CHECKOBJDUMP: subsus_u.w $w7, $w15, $w7 -# CHECKOBJDUMP: subsus_u.d $w9, $w3, $w15 -# CHECKOBJDUMP: subsuu_s.b $w22, $w3, $w31 -# CHECKOBJDUMP: subsuu_s.h $w19, $w23, $w22 -# CHECKOBJDUMP: subsuu_s.w $w9, $w10, $w13 -# CHECKOBJDUMP: subsuu_s.d $w5, $w6, $w0 -# CHECKOBJDUMP: subv.b $w6, $w13, $w19 -# CHECKOBJDUMP: subv.h $w4, $w25, $w12 -# CHECKOBJDUMP: subv.w $w27, $w27, $w11 -# CHECKOBJDUMP: subv.d $w9, $w24, $w10 -# CHECKOBJDUMP: vshf.b $w3, $w16, $w5 -# CHECKOBJDUMP: vshf.h $w20, $w19, $w8 -# CHECKOBJDUMP: vshf.w $w16, $w30, $w25 -# CHECKOBJDUMP: vshf.d $w19, $w11, $w15 - add_a.b $w26, $w9, $w4 add_a.h $w23, $w27, $w31 add_a.w $w11, $w6, $w22 diff --git a/test/MC/Mips/msa/test_3rf.s b/test/MC/Mips/msa/test_3rf.s index 6787d85..c5896d7 100644 --- a/test/MC/Mips/msa/test_3rf.s +++ b/test/MC/Mips/msa/test_3rf.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: fadd.w $w28, $w19, $w28 # encoding: [0x78,0x1c,0x9f,0x1b] # CHECK: fadd.d $w13, $w2, $w29 # encoding: [0x78,0x3d,0x13,0x5b] # CHECK: fcaf.w $w14, $w11, $w25 # encoding: [0x78,0x19,0x5b,0x9a] @@ -87,89 +83,6 @@ # CHECK: mulr_q.h $w6, $w20, $w19 # encoding: [0x7b,0x13,0xa1,0x9c] # CHECK: mulr_q.w $w27, $w1, $w20 # encoding: [0x7b,0x34,0x0e,0xdc] -# CHECKOBJDUMP: fadd.w $w28, $w19, $w28 -# CHECKOBJDUMP: fadd.d $w13, $w2, $w29 -# CHECKOBJDUMP: fcaf.w $w14, $w11, $w25 -# CHECKOBJDUMP: fcaf.d $w1, $w1, $w19 -# CHECKOBJDUMP: fceq.w $w1, $w23, $w16 -# CHECKOBJDUMP: fceq.d $w0, $w8, $w16 -# CHECKOBJDUMP: fcle.w $w16, $w9, $w24 -# CHECKOBJDUMP: fcle.d $w27, $w14, $w1 -# CHECKOBJDUMP: fclt.w $w28, $w8, $w8 -# CHECKOBJDUMP: fclt.d $w30, $w25, $w11 -# CHECKOBJDUMP: fcne.w $w2, $w18, $w23 -# CHECKOBJDUMP: fcne.d $w14, $w20, $w15 -# CHECKOBJDUMP: fcor.w $w10, $w18, $w25 -# CHECKOBJDUMP: fcor.d $w17, $w25, $w11 -# CHECKOBJDUMP: fcueq.w $w14, $w2, $w21 -# CHECKOBJDUMP: fcueq.d $w29, $w3, $w7 -# CHECKOBJDUMP: fcule.w $w17, $w5, $w3 -# CHECKOBJDUMP: fcule.d $w31, $w1, $w30 -# CHECKOBJDUMP: fcult.w $w6, $w25, $w9 -# CHECKOBJDUMP: fcult.d $w27, $w8, $w17 -# CHECKOBJDUMP: fcun.w $w4, $w20, $w8 -# CHECKOBJDUMP: fcun.d $w29, $w11, $w3 -# CHECKOBJDUMP: fcune.w $w13, $w18, $w19 -# CHECKOBJDUMP: fcune.d $w16, $w26, $w21 -# CHECKOBJDUMP: fdiv.w $w13, $w24, $w2 -# CHECKOBJDUMP: fdiv.d $w19, $w4, $w25 -# CHECKOBJDUMP: fexdo.h $w8, $w0, $w16 -# CHECKOBJDUMP: fexdo.w $w0, $w13, $w27 -# CHECKOBJDUMP: fexp2.w $w17, $w0, $w3 -# CHECKOBJDUMP: fexp2.d $w22, $w0, $w10 -# CHECKOBJDUMP: fmadd.w $w29, $w6, $w23 -# CHECKOBJDUMP: fmadd.d $w11, $w28, $w21 -# CHECKOBJDUMP: fmax.w $w0, $w23, $w13 -# CHECKOBJDUMP: fmax.d $w26, $w18, $w8 -# CHECKOBJDUMP: fmax_a.w $w10, $w16, $w10 -# CHECKOBJDUMP: fmax_a.d $w30, $w9, $w22 -# CHECKOBJDUMP: fmin.w $w24, $w1, $w30 -# CHECKOBJDUMP: fmin.d $w27, $w27, $w10 -# CHECKOBJDUMP: fmin_a.w $w10, $w29, $w20 -# CHECKOBJDUMP: fmin_a.d $w13, $w30, $w24 -# CHECKOBJDUMP: fmsub.w $w17, $w25, $w0 -# CHECKOBJDUMP: fmsub.d $w8, $w18, $w16 -# CHECKOBJDUMP: fmul.w $w3, $w15, $w15 -# CHECKOBJDUMP: fmul.d $w9, $w30, $w10 -# CHECKOBJDUMP: fsaf.w $w25, $w5, $w10 -# CHECKOBJDUMP: fsaf.d $w25, $w3, $w29 -# CHECKOBJDUMP: fseq.w $w11, $w17, $w13 -# CHECKOBJDUMP: fseq.d $w29, $w0, $w31 -# CHECKOBJDUMP: fsle.w $w30, $w31, $w31 -# CHECKOBJDUMP: fsle.d $w18, $w23, $w24 -# CHECKOBJDUMP: fslt.w $w12, $w5, $w6 -# CHECKOBJDUMP: fslt.d $w16, $w26, $w21 -# CHECKOBJDUMP: fsne.w $w30, $w1, $w12 -# CHECKOBJDUMP: fsne.d $w14, $w13, $w23 -# CHECKOBJDUMP: fsor.w $w27, $w13, $w27 -# CHECKOBJDUMP: fsor.d $w12, $w24, $w11 -# CHECKOBJDUMP: fsub.w $w31, $w26, $w1 -# CHECKOBJDUMP: fsub.d $w19, $w17, $w27 -# CHECKOBJDUMP: fsueq.w $w16, $w24, $w25 -# CHECKOBJDUMP: fsueq.d $w18, $w14, $w14 -# CHECKOBJDUMP: fsule.w $w23, $w30, $w13 -# CHECKOBJDUMP: fsule.d $w2, $w11, $w26 -# CHECKOBJDUMP: fsult.w $w11, $w26, $w22 -# CHECKOBJDUMP: fsult.d $w6, $w23, $w30 -# CHECKOBJDUMP: fsun.w $w3, $w18, $w28 -# CHECKOBJDUMP: fsun.d $w18, $w11, $w19 -# CHECKOBJDUMP: fsune.w $w16, $w31, $w2 -# CHECKOBJDUMP: fsune.d $w3, $w26, $w17 -# CHECKOBJDUMP: ftq.h $w16, $w4, $w24 -# CHECKOBJDUMP: ftq.w $w5, $w5, $w25 -# CHECKOBJDUMP: madd_q.h $w16, $w20, $w10 -# CHECKOBJDUMP: madd_q.w $w28, $w2, $w9 -# CHECKOBJDUMP: maddr_q.h $w8, $w18, $w9 -# CHECKOBJDUMP: maddr_q.w $w29, $w12, $w16 -# CHECKOBJDUMP: msub_q.h $w24, $w26, $w10 -# CHECKOBJDUMP: msub_q.w $w13, $w30, $w28 -# CHECKOBJDUMP: msubr_q.h $w12, $w21, $w11 -# CHECKOBJDUMP: msubr_q.w $w1, $w14, $w20 -# CHECKOBJDUMP: mul_q.h $w6, $w16, $w30 -# CHECKOBJDUMP: mul_q.w $w16, $w1, $w4 -# CHECKOBJDUMP: mulr_q.h $w6, $w20, $w19 -# CHECKOBJDUMP: mulr_q.w $w27, $w1, $w20 - fadd.w $w28, $w19, $w28 fadd.d $w13, $w2, $w29 fcaf.w $w14, $w11, $w25 diff --git a/test/MC/Mips/msa/test_bit.s b/test/MC/Mips/msa/test_bit.s index 2e5a6a5..85ebe54 100644 --- a/test/MC/Mips/msa/test_bit.s +++ b/test/MC/Mips/msa/test_bit.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: bclri.b $w21, $w30, 2 # encoding: [0x79,0xf2,0xf5,0x49] # CHECK: bclri.h $w24, $w21, 0 # encoding: [0x79,0xe0,0xae,0x09] # CHECK: bclri.w $w23, $w30, 3 # encoding: [0x79,0xc3,0xf5,0xc9] @@ -53,55 +49,6 @@ # CHECK: srlri.w $w11, $w22, 2 # encoding: [0x79,0xc2,0xb2,0xca] # CHECK: srlri.d $w24, $w10, 6 # encoding: [0x79,0x86,0x56,0x0a] -# CHECKOBJDUMP: bclri.b $w21, $w30, 2 -# CHECKOBJDUMP: bclri.h $w24, $w21, 0 -# CHECKOBJDUMP: bclri.w $w23, $w30, 3 -# CHECKOBJDUMP: bclri.d $w9, $w11, 0 -# CHECKOBJDUMP: binsli.b $w25, $w12, 1 -# CHECKOBJDUMP: binsli.h $w21, $w22, 0 -# CHECKOBJDUMP: binsli.w $w22, $w4, 0 -# CHECKOBJDUMP: binsli.d $w6, $w2, 6 -# CHECKOBJDUMP: binsri.b $w15, $w19, 0 -# CHECKOBJDUMP: binsri.h $w8, $w30, 1 -# CHECKOBJDUMP: binsri.w $w2, $w19, 5 -# CHECKOBJDUMP: binsri.d $w18, $w20, 1 -# CHECKOBJDUMP: bnegi.b $w24, $w19, 0 -# CHECKOBJDUMP: bnegi.h $w28, $w11, 3 -# CHECKOBJDUMP: bnegi.w $w1, $w27, 5 -# CHECKOBJDUMP: bnegi.d $w4, $w21, 1 -# CHECKOBJDUMP: bseti.b $w18, $w8, 0 -# CHECKOBJDUMP: bseti.h $w24, $w14, 2 -# CHECKOBJDUMP: bseti.w $w9, $w18, 4 -# CHECKOBJDUMP: bseti.d $w7, $w15, 1 -# CHECKOBJDUMP: sat_s.b $w31, $w31, 2 -# CHECKOBJDUMP: sat_s.h $w19, $w19, 0 -# CHECKOBJDUMP: sat_s.w $w19, $w29, 0 -# CHECKOBJDUMP: sat_s.d $w11, $w22, 0 -# CHECKOBJDUMP: sat_u.b $w1, $w13, 3 -# CHECKOBJDUMP: sat_u.h $w30, $w24, 4 -# CHECKOBJDUMP: sat_u.w $w31, $w13, 0 -# CHECKOBJDUMP: sat_u.d $w29, $w16, 5 -# CHECKOBJDUMP: slli.b $w23, $w10, 1 -# CHECKOBJDUMP: slli.h $w9, $w18, 1 -# CHECKOBJDUMP: slli.w $w11, $w29, 4 -# CHECKOBJDUMP: slli.d $w25, $w20, 1 -# CHECKOBJDUMP: srai.b $w24, $w29, 1 -# CHECKOBJDUMP: srai.h $w1, $w6, 0 -# CHECKOBJDUMP: srai.w $w7, $w26, 1 -# CHECKOBJDUMP: srai.d $w20, $w25, 3 -# CHECKOBJDUMP: srari.b $w5, $w25, 0 -# CHECKOBJDUMP: srari.h $w7, $w6, 4 -# CHECKOBJDUMP: srari.w $w17, $w11, 5 -# CHECKOBJDUMP: srari.d $w21, $w25, 5 -# CHECKOBJDUMP: srli.b $w2, $w0, 2 -# CHECKOBJDUMP: srli.h $w31, $w31, 2 -# CHECKOBJDUMP: srli.w $w5, $w9, 4 -# CHECKOBJDUMP: srli.d $w27, $w26, 5 -# CHECKOBJDUMP: srlri.b $w18, $w3, 0 -# CHECKOBJDUMP: srlri.h $w1, $w2, 3 -# CHECKOBJDUMP: srlri.w $w11, $w22, 2 -# CHECKOBJDUMP: srlri.d $w24, $w10, 6 - bclri.b $w21, $w30, 2 bclri.h $w24, $w21, 0 bclri.w $w23, $w30, 3 diff --git a/test/MC/Mips/msa/test_cbranch.s b/test/MC/Mips/msa/test_cbranch.s index 37b8872..aa6779b 100644 --- a/test/MC/Mips/msa/test_cbranch.s +++ b/test/MC/Mips/msa/test_cbranch.s @@ -7,22 +7,22 @@ #CHECK: bnz.w $w2, 128 # encoding: [0x47,0xc2,0x00,0x20] #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] #CHECK: bnz.d $w3, -128 # encoding: [0x47,0xe3,0xff,0xe0] -#CHECK: bnz.b $w0, SYMBOL0 # encoding: [0x47'A',0x80'A',0x00,0x00] +#CHECK: bnz.b $w0, SYMBOL0 # encoding: [0x47,0x80,A,A] # fixup A - offset: 0, value: SYMBOL0, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bnz.h $w1, SYMBOL1 # encoding: [0x47'A',0xa1'A',0x00,0x00] +#CHECK: bnz.h $w1, SYMBOL1 # encoding: [0x47,0xa1,A,A] # fixup A - offset: 0, value: SYMBOL1, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bnz.w $w2, SYMBOL2 # encoding: [0x47'A',0xc2'A',0x00,0x00] +#CHECK: bnz.w $w2, SYMBOL2 # encoding: [0x47,0xc2,A,A] # fixup A - offset: 0, value: SYMBOL2, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bnz.d $w3, SYMBOL3 # encoding: [0x47'A',0xe3'A',0x00,0x00] +#CHECK: bnz.d $w3, SYMBOL3 # encoding: [0x47,0xe3,A,A] # fixup A - offset: 0, value: SYMBOL3, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] #CHECK: bnz.v $w0, 4 # encoding: [0x45,0xe0,0x00,0x01] #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bnz.v $w0, SYMBOL0 # encoding: [0x45'A',0xe0'A',0x00,0x00] +#CHECK: bnz.v $w0, SYMBOL0 # encoding: [0x45,0xe0,A,A] # fixup A - offset: 0, value: SYMBOL0, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] @@ -34,22 +34,22 @@ #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] #CHECK: bz.d $w3, -1024 # encoding: [0x47,0x63,0xff,0x00] #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bz.b $w0, SYMBOL0 # encoding: [0x47'A',A,0x00,0x00] +#CHECK: bz.b $w0, SYMBOL0 # encoding: [0x47,0x00,A,A] # fixup A - offset: 0, value: SYMBOL0, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bz.h $w1, SYMBOL1 # encoding: [0x47'A',0x21'A',0x00,0x00] +#CHECK: bz.h $w1, SYMBOL1 # encoding: [0x47,0x21,A,A] # fixup A - offset: 0, value: SYMBOL1, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bz.w $w2, SYMBOL2 # encoding: [0x47'A',0x42'A',0x00,0x00] +#CHECK: bz.w $w2, SYMBOL2 # encoding: [0x47,0x42,A,A] # fixup A - offset: 0, value: SYMBOL2, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bz.d $w3, SYMBOL3 # encoding: [0x47'A',0x63'A',0x00,0x00] +#CHECK: bz.d $w3, SYMBOL3 # encoding: [0x47,0x63,A,A] # fixup A - offset: 0, value: SYMBOL3, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] #CHECK: bz.v $w0, 4 # encoding: [0x45,0x60,0x00,0x01] #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -#CHECK: bz.v $w0, SYMBOL0 # encoding: [0x45'A',0x60'A',0x00,0x00] +#CHECK: bz.v $w0, SYMBOL0 # encoding: [0x45,0x60,A,A] # fixup A - offset: 0, value: SYMBOL0, kind: fixup_Mips_PC16 #CHECK: nop # encoding: [0x00,0x00,0x00,0x00] diff --git a/test/MC/Mips/msa/test_ctrlregs.s b/test/MC/Mips/msa/test_ctrlregs.s index a014c03..3329072b 100644 --- a/test/MC/Mips/msa/test_ctrlregs.s +++ b/test/MC/Mips/msa/test_ctrlregs.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# #CHECK: cfcmsa $1, $0 # encoding: [0x78,0x7e,0x00,0x59] #CHECK: cfcmsa $1, $0 # encoding: [0x78,0x7e,0x00,0x59] #CHECK: cfcmsa $2, $1 # encoding: [0x78,0x7e,0x08,0x99] @@ -38,40 +34,6 @@ #CHECK: ctcmsa $7, $8 # encoding: [0x78,0x3e,0x41,0xd9] #CHECK: ctcmsa $7, $8 # encoding: [0x78,0x3e,0x41,0xd9] -#CHECKOBJDUMP: cfcmsa $1, $0 -#CHECKOBJDUMP: cfcmsa $1, $0 -#CHECKOBJDUMP: cfcmsa $2, $1 -#CHECKOBJDUMP: cfcmsa $2, $1 -#CHECKOBJDUMP: cfcmsa $3, $2 -#CHECKOBJDUMP: cfcmsa $3, $2 -#CHECKOBJDUMP: cfcmsa $4, $3 -#CHECKOBJDUMP: cfcmsa $4, $3 -#CHECKOBJDUMP: cfcmsa $5, $4 -#CHECKOBJDUMP: cfcmsa $5, $4 -#CHECKOBJDUMP: cfcmsa $6, $5 -#CHECKOBJDUMP: cfcmsa $6, $5 -#CHECKOBJDUMP: cfcmsa $7, $6 -#CHECKOBJDUMP: cfcmsa $7, $6 -#CHECKOBJDUMP: cfcmsa $8, $7 -#CHECKOBJDUMP: cfcmsa $8, $7 - -#CHECKOBJDUMP: ctcmsa $0, $1 -#CHECKOBJDUMP: ctcmsa $0, $1 -#CHECKOBJDUMP: ctcmsa $1, $2 -#CHECKOBJDUMP: ctcmsa $1, $2 -#CHECKOBJDUMP: ctcmsa $2, $3 -#CHECKOBJDUMP: ctcmsa $2, $3 -#CHECKOBJDUMP: ctcmsa $3, $4 -#CHECKOBJDUMP: ctcmsa $3, $4 -#CHECKOBJDUMP: ctcmsa $4, $5 -#CHECKOBJDUMP: ctcmsa $4, $5 -#CHECKOBJDUMP: ctcmsa $5, $6 -#CHECKOBJDUMP: ctcmsa $5, $6 -#CHECKOBJDUMP: ctcmsa $6, $7 -#CHECKOBJDUMP: ctcmsa $6, $7 -#CHECKOBJDUMP: ctcmsa $7, $8 -#CHECKOBJDUMP: ctcmsa $7, $8 - cfcmsa $1, $msair cfcmsa $1, $0 cfcmsa $2, $msacsr diff --git a/test/MC/Mips/msa/test_dlsa.s b/test/MC/Mips/msa/test_dlsa.s index a70999d..5e14571 100644 --- a/test/MC/Mips/msa/test_dlsa.s +++ b/test/MC/Mips/msa/test_dlsa.s @@ -1,20 +1,11 @@ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | \ # RUN: FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips64r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips64 -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: dlsa $8, $9, $10, 1 # encoding: [0x01,0x2a,0x40,0x15] # CHECK: dlsa $8, $9, $10, 2 # encoding: [0x01,0x2a,0x40,0x55] # CHECK: dlsa $8, $9, $10, 3 # encoding: [0x01,0x2a,0x40,0x95] # CHECK: dlsa $8, $9, $10, 4 # encoding: [0x01,0x2a,0x40,0xd5] -# CHECKOBJDUMP: dlsa $8, $9, $10, 1 -# CHECKOBJDUMP: dlsa $8, $9, $10, 2 -# CHECKOBJDUMP: dlsa $8, $9, $10, 3 -# CHECKOBJDUMP: dlsa $8, $9, $10, 4 - dlsa $8, $9, $10, 1 dlsa $8, $9, $10, 2 dlsa $8, $9, $10, 3 diff --git a/test/MC/Mips/msa/test_elm.s b/test/MC/Mips/msa/test_elm.s index 1e45fd4..dbe6d5c 100644 --- a/test/MC/Mips/msa/test_elm.s +++ b/test/MC/Mips/msa/test_elm.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: copy_s.b $13, $w8[2] # encoding: [0x78,0x82,0x43,0x59] # CHECK: copy_s.h $1, $w25[0] # encoding: [0x78,0xa0,0xc8,0x59] # CHECK: copy_s.w $22, $w5[1] # encoding: [0x78,0xb1,0x2d,0x99] @@ -20,22 +16,6 @@ # CHECK: splati.d $w28, $w1[0] # encoding: [0x78,0x78,0x0f,0x19] # CHECK: move.v $w23, $w24 # encoding: [0x78,0xbe,0xc5,0xd9] -# CHECKOBJDUMP: copy_s.b $13, $w8[2] -# CHECKOBJDUMP: copy_s.h $1, $w25[0] -# CHECKOBJDUMP: copy_s.w $22, $w5[1] -# CHECKOBJDUMP: copy_u.b $22, $w20[4] -# CHECKOBJDUMP: copy_u.h $20, $w4[0] -# CHECKOBJDUMP: copy_u.w $fp, $w13[2] -# CHECKOBJDUMP: sldi.b $w0, $w29[4] -# CHECKOBJDUMP: sldi.h $w8, $w17[0] -# CHECKOBJDUMP: sldi.w $w20, $w27[2] -# CHECKOBJDUMP: sldi.d $w4, $w12[0] -# CHECKOBJDUMP: splati.b $w25, $w3[2] -# CHECKOBJDUMP: splati.h $w24, $w28[1] -# CHECKOBJDUMP: splati.w $w13, $w18[0] -# CHECKOBJDUMP: splati.d $w28, $w1[0] -# CHECKOBJDUMP: move.v $w23, $w24 - copy_s.b $13, $w8[2] copy_s.h $1, $w25[0] copy_s.w $22, $w5[1] diff --git a/test/MC/Mips/msa/test_elm_insert.s b/test/MC/Mips/msa/test_elm_insert.s index f66b26c..d58a4e0 100644 --- a/test/MC/Mips/msa/test_elm_insert.s +++ b/test/MC/Mips/msa/test_elm_insert.s @@ -1,17 +1,9 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: insert.b $w23[3], $sp # encoding: [0x79,0x03,0xed,0xd9] # CHECK: insert.h $w20[2], $5 # encoding: [0x79,0x22,0x2d,0x19] # CHECK: insert.w $w8[2], $15 # encoding: [0x79,0x32,0x7a,0x19] -# CHECKOBJDUMP: insert.b $w23[3], $sp -# CHECKOBJDUMP: insert.h $w20[2], $5 -# CHECKOBJDUMP: insert.w $w8[2], $15 - insert.b $w23[3], $sp insert.h $w20[2], $5 insert.w $w8[2], $15 diff --git a/test/MC/Mips/msa/test_elm_insert_msa64.s b/test/MC/Mips/msa/test_elm_insert_msa64.s index 8196fd0..4e99bdb 100644 --- a/test/MC/Mips/msa/test_elm_insert_msa64.s +++ b/test/MC/Mips/msa/test_elm_insert_msa64.s @@ -1,11 +1,5 @@ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips64 -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: insert.d $w1[1], $sp # encoding: [0x79,0x39,0xe8,0x59] -# CHECKOBJDUMP: insert.d $w1[1], $sp - insert.d $w1[1], $sp diff --git a/test/MC/Mips/msa/test_elm_insve.s b/test/MC/Mips/msa/test_elm_insve.s index efdf88f..0053322 100644 --- a/test/MC/Mips/msa/test_elm_insve.s +++ b/test/MC/Mips/msa/test_elm_insve.s @@ -1,19 +1,10 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: insve.b $w25[3], $w9[0] # encoding: [0x79,0x43,0x4e,0x59] # CHECK: insve.h $w24[2], $w2[0] # encoding: [0x79,0x62,0x16,0x19] # CHECK: insve.w $w0[2], $w13[0] # encoding: [0x79,0x72,0x68,0x19] # CHECK: insve.d $w3[0], $w18[0] # encoding: [0x79,0x78,0x90,0xd9] -# CHECKOBJDUMP: insve.b $w25[3], $w9[0] -# CHECKOBJDUMP: insve.h $w24[2], $w2[0] -# CHECKOBJDUMP: insve.w $w0[2], $w13[0] -# CHECKOBJDUMP: insve.d $w3[0], $w18[0] - insve.b $w25[3], $w9[0] insve.h $w24[2], $w2[0] insve.w $w0[2], $w13[0] diff --git a/test/MC/Mips/msa/test_elm_msa64.s b/test/MC/Mips/msa/test_elm_msa64.s index 15bfcca..5cc9147 100644 --- a/test/MC/Mips/msa/test_elm_msa64.s +++ b/test/MC/Mips/msa/test_elm_msa64.s @@ -1,14 +1,7 @@ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips64 -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: copy_s.d $19, $w31[0] # encoding: [0x78,0xb8,0xfc,0xd9] # CHECK: copy_u.d $18, $w29[1] # encoding: [0x78,0xf9,0xec,0x99] -# CHECKOBJDUMP: copy_s.d $19, $w31[0] -# CHECKOBJDUMP: copy_u.d $18, $w29[1] - copy_s.d $19, $w31[0] copy_u.d $18, $w29[1] diff --git a/test/MC/Mips/msa/test_i10.s b/test/MC/Mips/msa/test_i10.s index e029dfd..d89218a 100644 --- a/test/MC/Mips/msa/test_i10.s +++ b/test/MC/Mips/msa/test_i10.s @@ -1,20 +1,10 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# - # CHECK: ldi.b $w8, 198 # encoding: [0x7b,0x06,0x32,0x07] # CHECK: ldi.h $w20, 313 # encoding: [0x7b,0x29,0xcd,0x07] # CHECK: ldi.w $w24, 492 # encoding: [0x7b,0x4f,0x66,0x07] # CHECK: ldi.d $w27, -180 # encoding: [0x7b,0x7a,0x66,0xc7] -# CHECKOBJDUMP: ldi.b $w8, 198 -# CHECKOBJDUMP: ldi.h $w20, 313 -# CHECKOBJDUMP: ldi.w $w24, 492 -# CHECKOBJDUMP: ldi.d $w27, 844 - ldi.b $w8, 198 ldi.h $w20, 313 ldi.w $w24, 492 diff --git a/test/MC/Mips/msa/test_i5.s b/test/MC/Mips/msa/test_i5.s index 56c4811..d923787 100644 --- a/test/MC/Mips/msa/test_i5.s +++ b/test/MC/Mips/msa/test_i5.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: addvi.b $w3, $w31, 30 # encoding: [0x78,0x1e,0xf8,0xc6] # CHECK: addvi.h $w24, $w13, 26 # encoding: [0x78,0x3a,0x6e,0x06] # CHECK: addvi.w $w26, $w20, 26 # encoding: [0x78,0x5a,0xa6,0x86] @@ -49,51 +45,6 @@ # CHECK: subvi.w $w12, $w10, 11 # encoding: [0x78,0xcb,0x53,0x06] # CHECK: subvi.d $w19, $w16, 7 # encoding: [0x78,0xe7,0x84,0xc6] -# CHECKOBJDUMP: addvi.b $w3, $w31, 30 -# CHECKOBJDUMP: addvi.h $w24, $w13, 26 -# CHECKOBJDUMP: addvi.w $w26, $w20, 26 -# CHECKOBJDUMP: addvi.d $w16, $w1, 21 -# CHECKOBJDUMP: ceqi.b $w24, $w21, 24 -# CHECKOBJDUMP: ceqi.h $w31, $w15, 2 -# CHECKOBJDUMP: ceqi.w $w12, $w1, 31 -# CHECKOBJDUMP: ceqi.d $w24, $w22, 7 -# CHECKOBJDUMP: clei_s.b $w12, $w16, 1 -# CHECKOBJDUMP: clei_s.h $w2, $w10, 23 -# CHECKOBJDUMP: clei_s.w $w4, $w11, 22 -# CHECKOBJDUMP: clei_s.d $w0, $w29, 22 -# CHECKOBJDUMP: clei_u.b $w21, $w17, 3 -# CHECKOBJDUMP: clei_u.h $w29, $w7, 17 -# CHECKOBJDUMP: clei_u.w $w1, $w1, 2 -# CHECKOBJDUMP: clei_u.d $w27, $w27, 29 -# CHECKOBJDUMP: clti_s.b $w19, $w13, 25 -# CHECKOBJDUMP: clti_s.h $w15, $w10, 20 -# CHECKOBJDUMP: clti_s.w $w12, $w12, 11 -# CHECKOBJDUMP: clti_s.d $w29, $w20, 17 -# CHECKOBJDUMP: clti_u.b $w14, $w9, 29 -# CHECKOBJDUMP: clti_u.h $w24, $w25, 25 -# CHECKOBJDUMP: clti_u.w $w1, $w1, 22 -# CHECKOBJDUMP: clti_u.d $w21, $w25, 1 -# CHECKOBJDUMP: maxi_s.b $w22, $w21, 1 -# CHECKOBJDUMP: maxi_s.h $w29, $w5, 24 -# CHECKOBJDUMP: maxi_s.w $w1, $w10, 20 -# CHECKOBJDUMP: maxi_s.d $w13, $w29, 16 -# CHECKOBJDUMP: maxi_u.b $w20, $w0, 12 -# CHECKOBJDUMP: maxi_u.h $w1, $w14, 3 -# CHECKOBJDUMP: maxi_u.w $w27, $w22, 11 -# CHECKOBJDUMP: maxi_u.d $w26, $w6, 4 -# CHECKOBJDUMP: mini_s.b $w4, $w1, 1 -# CHECKOBJDUMP: mini_s.h $w27, $w27, 23 -# CHECKOBJDUMP: mini_s.w $w28, $w11, 9 -# CHECKOBJDUMP: mini_s.d $w11, $w10, 10 -# CHECKOBJDUMP: mini_u.b $w18, $w23, 27 -# CHECKOBJDUMP: mini_u.h $w7, $w26, 18 -# CHECKOBJDUMP: mini_u.w $w11, $w12, 26 -# CHECKOBJDUMP: mini_u.d $w11, $w15, 2 -# CHECKOBJDUMP: subvi.b $w24, $w20, 19 -# CHECKOBJDUMP: subvi.h $w11, $w19, 4 -# CHECKOBJDUMP: subvi.w $w12, $w10, 11 -# CHECKOBJDUMP: subvi.d $w19, $w16, 7 - addvi.b $w3, $w31, 30 addvi.h $w24, $w13, 26 addvi.w $w26, $w20, 26 diff --git a/test/MC/Mips/msa/test_i8.s b/test/MC/Mips/msa/test_i8.s index d4138a1..b520bb4 100644 --- a/test/MC/Mips/msa/test_i8.s +++ b/test/MC/Mips/msa/test_i8.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: andi.b $w2, $w29, 48 # encoding: [0x78,0x30,0xe8,0x80] # CHECK: bmnzi.b $w6, $w22, 126 # encoding: [0x78,0x7e,0xb1,0x81] # CHECK: bmzi.b $w27, $w1, 88 # encoding: [0x79,0x58,0x0e,0xc1] @@ -15,17 +11,6 @@ # CHECK: shf.w $w14, $w3, 93 # encoding: [0x7a,0x5d,0x1b,0x82] # CHECK: xori.b $w16, $w10, 20 # encoding: [0x7b,0x14,0x54,0x00] -# CHECKOBJDUMP: andi.b $w2, $w29, 48 -# CHECKOBJDUMP: bmnzi.b $w6, $w22, 126 -# CHECKOBJDUMP: bmzi.b $w27, $w1, 88 -# CHECKOBJDUMP: bseli.b $w29, $w3, 189 -# CHECKOBJDUMP: nori.b $w1, $w17, 56 -# CHECKOBJDUMP: ori.b $w26, $w20, 135 -# CHECKOBJDUMP: shf.b $w19, $w30, 105 -# CHECKOBJDUMP: shf.h $w17, $w8, 76 -# CHECKOBJDUMP: shf.w $w14, $w3, 93 -# CHECKOBJDUMP: xori.b $w16, $w10, 20 - andi.b $w2, $w29, 48 bmnzi.b $w6, $w22, 126 bmzi.b $w27, $w1, 88 diff --git a/test/MC/Mips/msa/test_lsa.s b/test/MC/Mips/msa/test_lsa.s index 9ea76f6..22fd0b3 100644 --- a/test/MC/Mips/msa/test_lsa.s +++ b/test/MC/Mips/msa/test_lsa.s @@ -1,19 +1,10 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: lsa $8, $9, $10, 1 # encoding: [0x01,0x2a,0x40,0x05] # CHECK: lsa $8, $9, $10, 2 # encoding: [0x01,0x2a,0x40,0x45] # CHECK: lsa $8, $9, $10, 3 # encoding: [0x01,0x2a,0x40,0x85] # CHECK: lsa $8, $9, $10, 4 # encoding: [0x01,0x2a,0x40,0xc5] -# CHECKOBJDUMP: lsa $8, $9, $10, 1 -# CHECKOBJDUMP: lsa $8, $9, $10, 2 -# CHECKOBJDUMP: lsa $8, $9, $10, 3 -# CHECKOBJDUMP: lsa $8, $9, $10, 4 - lsa $8, $9, $10, 1 lsa $8, $9, $10, 2 lsa $8, $9, $10, 3 diff --git a/test/MC/Mips/msa/test_mi10.s b/test/MC/Mips/msa/test_mi10.s index 90baeba..7269960 100644 --- a/test/MC/Mips/msa/test_mi10.s +++ b/test/MC/Mips/msa/test_mi10.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: ld.b $w0, -512($1) # encoding: [0x7a,0x00,0x08,0x20] # CHECK: ld.b $w1, 0($2) # encoding: [0x78,0x00,0x10,0x60] # CHECK: ld.b $w2, 511($3) # encoding: [0x79,0xff,0x18,0xa0] @@ -31,33 +27,6 @@ # CHECK: ld.d $w21, 2048($22) # encoding: [0x79,0x00,0xb5,0x63] # CHECK: ld.d $w22, 4088($23) # encoding: [0x79,0xff,0xbd,0xa3] -# CHECKOBJDUMP: ld.b $w0, -512($1) -# CHECKOBJDUMP: ld.b $w1, 0($2) -# CHECKOBJDUMP: ld.b $w2, 511($3) - -# CHECKOBJDUMP: ld.h $w3, -1024($4) -# CHECKOBJDUMP: ld.h $w4, -512($5) -# CHECKOBJDUMP: ld.h $w5, 0($6) -# CHECKOBJDUMP: ld.h $w6, 512($7) -# CHECKOBJDUMP: ld.h $w7, 1022($8) - -# CHECKOBJDUMP: ld.w $w8, -2048($9) -# CHECKOBJDUMP: ld.w $w9, -1024($10) -# CHECKOBJDUMP: ld.w $w10, -512($11) -# CHECKOBJDUMP: ld.w $w11, 512($12) -# CHECKOBJDUMP: ld.w $w12, 1024($13) -# CHECKOBJDUMP: ld.w $w13, 2044($14) - -# CHECKOBJDUMP: ld.d $w14, -4096($15) -# CHECKOBJDUMP: ld.d $w15, -2048($16) -# CHECKOBJDUMP: ld.d $w16, -1024($17) -# CHECKOBJDUMP: ld.d $w17, -512($18) -# CHECKOBJDUMP: ld.d $w18, 0($19) -# CHECKOBJDUMP: ld.d $w19, 512($20) -# CHECKOBJDUMP: ld.d $w20, 1024($21) -# CHECKOBJDUMP: ld.d $w21, 2048($22) -# CHECKOBJDUMP: ld.d $w22, 4088($23) - ld.b $w0, -512($1) ld.b $w1, 0($2) ld.b $w2, 511($3) diff --git a/test/MC/Mips/msa/test_vec.s b/test/MC/Mips/msa/test_vec.s index b62da70..3f989d3 100644 --- a/test/MC/Mips/msa/test_vec.s +++ b/test/MC/Mips/msa/test_vec.s @@ -1,9 +1,5 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -show-encoding | FileCheck %s # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ -# RUN: llvm-objdump -d -arch=mips -mattr=+msa - | \ -# RUN: FileCheck %s -check-prefix=CHECKOBJDUMP -# # CHECK: and.v $w25, $w20, $w27 # encoding: [0x78,0x1b,0xa6,0x5e] # CHECK: bmnz.v $w17, $w6, $w7 # encoding: [0x78,0x87,0x34,0x5e] # CHECK: bmz.v $w3, $w17, $w9 # encoding: [0x78,0xa9,0x88,0xde] @@ -12,14 +8,6 @@ # CHECK: or.v $w24, $w26, $w30 # encoding: [0x78,0x3e,0xd6,0x1e] # CHECK: xor.v $w7, $w27, $w15 # encoding: [0x78,0x6f,0xd9,0xde] -# CHECKOBJDUMP: and.v $w25, $w20, $w27 -# CHECKOBJDUMP: bmnz.v $w17, $w6, $w7 -# CHECKOBJDUMP: bmz.v $w3, $w17, $w9 -# CHECKOBJDUMP: bsel.v $w8, $w0, $w14 -# CHECKOBJDUMP: nor.v $w7, $w31, $w0 -# CHECKOBJDUMP: or.v $w24, $w26, $w30 -# CHECKOBJDUMP: xor.v $w7, $w27, $w15 - and.v $w25, $w20, $w27 bmnz.v $w17, $w6, $w7 bmz.v $w3, $w17, $w9 diff --git a/test/MC/Mips/octeon-instructions.s b/test/MC/Mips/octeon-instructions.s index 0244e19..b7c89b4 100644 --- a/test/MC/Mips/octeon-instructions.s +++ b/test/MC/Mips/octeon-instructions.s @@ -29,8 +29,18 @@ # CHECK: pop $2, $2 # encoding: [0x70,0x40,0x10,0x2c] # CHECK: seq $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2a] # CHECK: seq $6, $6, $24 # encoding: [0x70,0xd8,0x30,0x2a] +# CHECK: seqi $17, $15, -512 # encoding: [0x71,0xf1,0x80,0x2e] +# CHECK: seqi $16, $16, 38 # encoding: [0x72,0x10,0x09,0xae] # CHECK: sne $25, $23, $24 # encoding: [0x72,0xf8,0xc8,0x2b] # CHECK: sne $23, $23, $20 # encoding: [0x72,0xf4,0xb8,0x2b] +# CHECK: snei $4, $16, -313 # encoding: [0x72,0x04,0xb1,0xef] +# CHECK: snei $26, $26, 511 # encoding: [0x73,0x5a,0x7f,0xef] +# CHECK: v3mulu $21, $10, $21 # encoding: [0x71,0x55,0xa8,0x11] +# CHECK: v3mulu $20, $20, $10 # encoding: [0x72,0x8a,0xa0,0x11] +# CHECK: vmm0 $3, $19, $16 # encoding: [0x72,0x70,0x18,0x10] +# CHECK: vmm0 $ra, $ra, $9 # encoding: [0x73,0xe9,0xf8,0x10] +# CHECK: vmulu $sp, $10, $17 # encoding: [0x71,0x51,0xe8,0x0f] +# CHECK: vmulu $27, $27, $6 # encoding: [0x73,0x66,0xd8,0x0f] baddu $9, $6, $7 baddu $17, $18, $19 @@ -61,5 +71,15 @@ pop $2 seq $25, $23, $24 seq $6, $24 + seqi $17, $15, -512 + seqi $16, 38 sne $25, $23, $24 sne $23, $20 + snei $4, $16, -313 + snei $26, 511 + v3mulu $21, $10, $21 + v3mulu $20, $10 + vmm0 $3, $19, $16 + vmm0 $31, $9 + vmulu $29, $10, $17 + vmulu $27, $6 |