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| author | Stephen Hines <srhines@google.com> | 2014-07-21 00:45:20 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-07-21 00:45:20 -0700 |
| commit | c6a4f5e819217e1e12c458aed8e7b122e23a3a58 (patch) | |
| tree | 81b7dd2bb4370a392f31d332a566c903b5744764 /test/MC | |
| parent | 19c6fbb3e8aaf74093afa08013134b61fa08f245 (diff) | |
| download | external_llvm-c6a4f5e819217e1e12c458aed8e7b122e23a3a58.zip external_llvm-c6a4f5e819217e1e12c458aed8e7b122e23a3a58.tar.gz external_llvm-c6a4f5e819217e1e12c458aed8e7b122e23a3a58.tar.bz2 | |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
Diffstat (limited to 'test/MC')
194 files changed, 3570 insertions, 555 deletions
diff --git a/test/MC/AArch64/alias-logicalimm.s b/test/MC/AArch64/alias-logicalimm.s new file mode 100644 index 0000000..28ec40b --- /dev/null +++ b/test/MC/AArch64/alias-logicalimm.s @@ -0,0 +1,41 @@ +// RUN: llvm-mc -triple=aarch64-none-linux-gnu < %s | FileCheck %s + +// CHECK: and x0, x1, #0xfffffffffffffffd +// CHECK: and x0, x1, #0xfffffffffffffffd + and x0, x1, #~2 + bic x0, x1, #2 + +// CHECK: and w0, w1, #0xfffffffd +// CHECK: and w0, w1, #0xfffffffd + and w0, w1, #~2 + bic w0, w1, #2 + +// CHECK: ands x0, x1, #0xfffffffffffffffd +// CHECK: ands x0, x1, #0xfffffffffffffffd + ands x0, x1, #~2 + bics x0, x1, #2 + +// CHECK: ands w0, w1, #0xfffffffd +// CHECK: ands w0, w1, #0xfffffffd + ands w0, w1, #~2 + bics w0, w1, #2 + +// CHECK: orr x0, x1, #0xfffffffffffffffd +// CHECK: orr x0, x1, #0xfffffffffffffffd + orr x0, x1, #~2 + orn x0, x1, #2 + +// CHECK: orr w2, w1, #0xfffffffc +// CHECK: orr w2, w1, #0xfffffffc + orr w2, w1, #~3 + orn w2, w1, #3 + +// CHECK: eor x0, x1, #0xfffffffffffffffd +// CHECK: eor x0, x1, #0xfffffffffffffffd + eor x0, x1, #~2 + eon x0, x1, #2 + +// CHECK: eor w2, w1, #0xfffffffc +// CHECK: eor w2, w1, #0xfffffffc + eor w2, w1, #~3 + eon w2, w1, #3 diff --git a/test/MC/AArch64/arm64-leaf-compact-unwind.s b/test/MC/AArch64/arm64-leaf-compact-unwind.s index d699813..27d3d51 100644 --- a/test/MC/AArch64/arm64-leaf-compact-unwind.s +++ b/test/MC/AArch64/arm64-leaf-compact-unwind.s @@ -23,10 +23,10 @@ // CHECK-NEXT: Reserved1: // CHECK-NEXT: Reserved2: // CHECK-NEXT: Relocations [ -// CHECK-NEXT: 0x60 0 3 0 ARM64_RELOC_UNSIGNED 0 - -// CHECK-NEXT: 0x40 0 3 0 ARM64_RELOC_UNSIGNED 0 - -// CHECK-NEXT: 0x20 0 3 0 ARM64_RELOC_UNSIGNED 0 - -// CHECK-NEXT: 0x0 0 3 0 ARM64_RELOC_UNSIGNED 0 - +// CHECK-NEXT: 0x60 0 3 0 ARM64_RELOC_UNSIGNED 0 0x1 +// CHECK-NEXT: 0x40 0 3 0 ARM64_RELOC_UNSIGNED 0 0x1 +// CHECK-NEXT: 0x20 0 3 0 ARM64_RELOC_UNSIGNED 0 0x1 +// CHECK-NEXT: 0x0 0 3 0 ARM64_RELOC_UNSIGNED 0 0x1 // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 00000000 00000000 08000000 00000002 diff --git a/test/MC/AArch64/arm64-system-encoding.s b/test/MC/AArch64/arm64-system-encoding.s index 9246608..87f8f8a 100644 --- a/test/MC/AArch64/arm64-system-encoding.s +++ b/test/MC/AArch64/arm64-system-encoding.s @@ -4,7 +4,7 @@ foo: ;----------------------------------------------------------------------------- -; Simple encodings (instuctions w/ no operands) +; Simple encodings (instructions w/ no operands) ;----------------------------------------------------------------------------- nop diff --git a/test/MC/AArch64/basic-a64-diagnostics.s b/test/MC/AArch64/basic-a64-diagnostics.s index a4a3b13..5293131 100644 --- a/test/MC/AArch64/basic-a64-diagnostics.s +++ b/test/MC/AArch64/basic-a64-diagnostics.s @@ -729,6 +729,27 @@ // CHECK-ERROR-NEXT: ^ //------------------------------------------------------------------------------ +// Logical (immediates) +//------------------------------------------------------------------------------ + + and w2, w3, #4294967296 + eor w2, w3, #4294967296 + orr w2, w3, #4294967296 + ands w2, w3, #4294967296 +// CHECK-ERROR: error: expected compatible register or logical immediate +// CHECK-ERROR-NEXT: and w2, w3, #4294967296 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: expected compatible register or logical immediate +// CHECK-ERROR-NEXT: eor w2, w3, #4294967296 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: expected compatible register or logical immediate +// CHECK-ERROR-NEXT: orr w2, w3, #4294967296 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: expected compatible register or logical immediate +// CHECK-ERROR-NEXT: ands w2, w3, #4294967296 +// CHECK-ERROR-NEXT: ^ + +//------------------------------------------------------------------------------ // Bitfield //------------------------------------------------------------------------------ @@ -1345,39 +1366,59 @@ cset wsp, lt csetm sp, ge + cset w1, al + csetm x6, nv // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: cset wsp, lt // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: csetm sp, ge // CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: condition codes AL and NV are invalid for this instruction +// CHECK-ERROR-NEXT: cset w1, al +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: condition codes AL and NV are invalid for this instruction +// CHECK-ERROR-NEXT: csetm x6, nv +// CHECK-ERROR-NEXT: ^ cinc w3, wsp, ne cinc sp, x9, eq + cinc x2, x0, nv // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: cinc w3, wsp, ne // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: cinc sp, x9, eq // CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: condition codes AL and NV are invalid for this instruction +// CHECK-ERROR-NEXT: cinc x2, x0, nv +// CHECK-ERROR-NEXT: ^ cinv w3, wsp, ne cinv sp, x9, eq + cinv w8, x7, nv // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: cinv w3, wsp, ne // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: cinv sp, x9, eq // CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: condition codes AL and NV are invalid for this instruction +// CHECK-ERROR-NEXT: cinv w8, x7, nv +// CHECK-ERROR-NEXT: ^ cneg w3, wsp, ne cneg sp, x9, eq + cneg x4, x5, al // CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: cneg w3, wsp, ne // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: cneg sp, x9, eq // CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: condition codes AL and NV are invalid for this instruction +// CHECK-ERROR-NEXT: cneg x4, x5, al +// CHECK-ERROR-NEXT: ^ //------------------------------------------------------------------------------ // Data Processing (1 source) @@ -2944,13 +2985,17 @@ orn wsp, w3, w5 bics x20, sp, x9, lsr #0 orn x2, x6, sp, lsl #3 -// CHECK-ERROR: error: invalid operand for instruction +// FIXME: the diagnostic we get for 'orn wsp, w3, w5' is from the orn alias, +// which is a better match than the genuine ORNWri, whereas it would be better +// to get the ORNWri diagnostic when the alias did not match, i.e. the +// alias' diagnostics should have a lower priority. +// CHECK-ERROR: error: expected compatible register or logical immediate // CHECK-ERROR-NEXT: orn wsp, w3, w5 -// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: invalid operand for instruction // CHECK-ERROR-NEXT: bics x20, sp, x9, lsr #0 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR-NEXT: error: invalid operand for instruction +// CHECK-ERROR-NEXT: error: expected compatible register or logical immediate // CHECK-ERROR-NEXT: orn x2, x6, sp, lsl #3 // CHECK-ERROR-NEXT: ^ diff --git a/test/MC/AArch64/basic-a64-instructions.s b/test/MC/AArch64/basic-a64-instructions.s index a12968b..140ea33 100644 --- a/test/MC/AArch64/basic-a64-instructions.s +++ b/test/MC/AArch64/basic-a64-instructions.s @@ -601,9 +601,11 @@ _func: cmn w0, w3 cmn wzr, w4 cmn w5, wzr + cmn wsp, w6 // CHECK: cmn w0, w3 // encoding: [0x1f,0x00,0x03,0x2b] // CHECK: cmn wzr, w4 // encoding: [0xff,0x03,0x04,0x2b] // CHECK: cmn w5, wzr // encoding: [0xbf,0x00,0x1f,0x2b] +// CHECK: cmn wsp, w6 // encoding: [0xff,0x43,0x26,0x2b] cmn w6, w7, lsl #0 cmn w8, w9, lsl #15 @@ -629,9 +631,11 @@ _func: cmn x0, x3 cmn xzr, x4 cmn x5, xzr + cmn sp, x6 // CHECK: cmn x0, x3 // encoding: [0x1f,0x00,0x03,0xab] // CHECK: cmn xzr, x4 // encoding: [0xff,0x03,0x04,0xab] // CHECK: cmn x5, xzr // encoding: [0xbf,0x00,0x1f,0xab] +// CHECK: cmn sp, x6 // encoding: [0xff,0x63,0x26,0xab] cmn x6, x7, lsl #0 cmn x8, x9, lsl #15 @@ -657,9 +661,11 @@ _func: cmp w0, w3 cmp wzr, w4 cmp w5, wzr + cmp wsp, w6 // CHECK: cmp w0, w3 // encoding: [0x1f,0x00,0x03,0x6b] // CHECK: cmp wzr, w4 // encoding: [0xff,0x03,0x04,0x6b] // CHECK: cmp w5, wzr // encoding: [0xbf,0x00,0x1f,0x6b] +// CHECK: cmp wsp, w6 // encoding: [0xff,0x43,0x26,0x6b] cmp w6, w7, lsl #0 cmp w8, w9, lsl #15 @@ -685,9 +691,11 @@ _func: cmp x0, x3 cmp xzr, x4 cmp x5, xzr + cmp sp, x6 // CHECK: cmp x0, x3 // encoding: [0x1f,0x00,0x03,0xeb] // CHECK: cmp xzr, x4 // encoding: [0xff,0x03,0x04,0xeb] // CHECK: cmp x5, xzr // encoding: [0xbf,0x00,0x1f,0xeb] +// CHECK: cmp sp, x6 // encoding: [0xff,0x63,0x26,0xeb] cmp x6, x7, lsl #0 cmp x8, x9, lsl #15 @@ -3237,6 +3245,17 @@ _func: // CHECK: orr w3, wzr, #0xf000f // encoding: [0xe3,0x8f,0x00,0x32] // CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa // encoding: [0xea,0xf3,0x01,0xb2] + // The Imm field of logicalImm operations has to be truncated to the + // register width, i.e. 32 bits + and w2, w3, #-3 + orr w0, w1, #~2 + eor w16, w17, #-7 + ands w19, w20, #~15 +// CHECK: and w2, w3, #0xfffffffd // encoding: [0x62,0x78,0x1e,0x12] +// CHECK: orr w0, w1, #0xfffffffd // encoding: [0x20,0x78,0x1e,0x32] +// CHECK: eor w16, w17, #0xfffffff9 // encoding: [0x30,0x76,0x1d,0x52] +// CHECK: ands w19, w20, #0xfffffff0 // encoding: [0x93,0x6e,0x1c,0x72] + //------------------------------------------------------------------------------ // Logical (shifted register) //------------------------------------------------------------------------------ diff --git a/test/MC/AArch64/dot-req-case-insensitive.s b/test/MC/AArch64/dot-req-case-insensitive.s new file mode 100644 index 0000000..e68b101 --- /dev/null +++ b/test/MC/AArch64/dot-req-case-insensitive.s @@ -0,0 +1,18 @@ +// RUN: llvm-mc -triple=arm64-eabi < %s | FileCheck %s +_foo: + OBJECT .req x2 + mov x4, OBJECT + mov x4, oBjEcT + .unreq oBJECT + +_foo2: + OBJECT .req w5 + mov w4, OBJECT + .unreq OBJECT + +// CHECK-LABEL: _foo: +// CHECK: mov x4, x2 +// CHECK: mov x4, x2 + +// CHECK-LABEL: _foo2: +// CHECK: mov w4, w5 diff --git a/test/MC/AArch64/dot-req-diagnostics.s b/test/MC/AArch64/dot-req-diagnostics.s new file mode 100644 index 0000000..44065f8 --- /dev/null +++ b/test/MC/AArch64/dot-req-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ERROR %s + +bar: + fred .req x5 + fred .req x6 +// CHECK-ERROR: warning: ignoring redefinition of register alias 'fred' +// CHECK-ERROR: fred .req x6 +// CHECK-ERROR: ^ + + ada .req v2.8b +// CHECK-ERROR: error: vector register without type specifier expected +// CHECK-ERROR: ada .req v2.8b +// CHECK-ERROR: ^ + + bob .req lisa +// CHECK-ERROR: error: register name or alias expected +// CHECK-ERROR: bob .req lisa +// CHECK-ERROR: ^ + + lisa .req x1, 23 +// CHECK-ERROR: error: unexpected input in .req directive +// CHECK-ERROR: lisa .req x1, 23 +// CHECK-ERROR: ^ + + mov bob, fred +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mov bob, fred +// CHECK-ERROR: ^ + + .unreq 1 +// CHECK-ERROR: error: unexpected input in .unreq directive. +// CHECK-ERROR: .unreq 1 +// CHECK-ERROR: ^ + + mov x1, fred +// CHECK: mov x1, x5 +// CHECK-NOT: mov x1, x6 diff --git a/test/MC/AArch64/dot-req.s b/test/MC/AArch64/dot-req.s new file mode 100644 index 0000000..947f945 --- /dev/null +++ b/test/MC/AArch64/dot-req.s @@ -0,0 +1,37 @@ +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s + +bar: + fred .req x5 + mov fred, x11 + .unreq fred + fred .req w6 + mov w1, fred + + bob .req fred + ada .req w1 + mov ada, bob + .unreq bob + .unreq fred + .unreq ada +// CHECK: mov x5, x11 // encoding: [0xe5,0x03,0x0b,0xaa] +// CHECK: mov w1, w6 // encoding: [0xe1,0x03,0x06,0x2a] +// CHECK: mov w1, w6 // encoding: [0xe1,0x03,0x06,0x2a] + + bob .req b6 + hanah .req h5 + sam .req s4 + dora .req d3 + quentin .req q2 + vesna .req v1 + addv bob, v0.8b + mov hanah, v4.h[3] + fadd s0, sam, sam + fmov d2, dora + ldr quentin, [sp] + mov v0.8b, vesna.8b +// CHECK: addv b6, v0.8b // encoding: [0x06,0xb8,0x31,0x0e] +// CHECK: mov h5, v4.h[3] // encoding: [0x85,0x04,0x0e,0x5e] +// CHECK: fadd s0, s4, s4 // encoding: [0x80,0x28,0x24,0x1e] +// CHECK: fmov d2, d3 // encoding: [0x62,0x40,0x60,0x1e] +// CHECK: ldr q2, [sp] // encoding: [0xe2,0x03,0xc0,0x3d] +// CHECK: mov v0.8b, v1.8b // encoding: [0x20,0x1c,0xa1,0x0e] diff --git a/test/MC/AArch64/ldr-pseudo-obj-errors.s b/test/MC/AArch64/ldr-pseudo-obj-errors.s new file mode 100644 index 0000000..7f1b642 --- /dev/null +++ b/test/MC/AArch64/ldr-pseudo-obj-errors.s @@ -0,0 +1,13 @@ +//RUN: not llvm-mc -triple=aarch64-linux -filetype=obj %s -o %t1 2> %t2 +//RUN: cat %t2 | FileCheck %s + +//These tests look for errors that should be reported for invalid object layout +//with the ldr pseudo. They are tested separately from parse errors because they +//only trigger when the file has successfully parsed and the object file is about +//to be written out. + +.text +foo: + ldr x0, =0x10111 + .space 0xdeadb0 +// CHECK: LVM ERROR: fixup value out of range diff --git a/test/MC/AArch64/ldr-pseudo.s b/test/MC/AArch64/ldr-pseudo.s new file mode 100644 index 0000000..6c82fb9 --- /dev/null +++ b/test/MC/AArch64/ldr-pseudo.s @@ -0,0 +1,231 @@ +//RUN: llvm-mc -triple=aarch64-linux-gnu %s | FileCheck %s + +// +// Check that large constants are converted to ldr from constant pool +// +// simple test +.section a, "ax", @progbits +// CHECK-LABEL: f1: +f1: + ldr x0, =0x1234 +// CHECK: movz x0, #0x1234 + ldr w1, =0x4567 +// CHECK: movz w1, #0x4567 + ldr x0, =0x12340000 +// CHECK: movz x0, #0x1234, lsl #16 + ldr w1, =0x45670000 +// CHECK: movz w1, #0x4567, lsl #16 + ldr x0, =0xabc00000000 +// CHECK: movz x0, #0xabc, lsl #32 + ldr x0, =0xbeef000000000000 +// CHECK: movz x0, #0xbeef, lsl #48 + +.section b,"ax",@progbits +// CHECK-LABEL: f3: +f3: + ldr x0, =0x10001 +// CHECK: ldr x0, .Ltmp[[TMP0:[0-9]+]] + +// loading multiple constants +.section c,"ax",@progbits +// CHECK-LABEL: f4: +f4: + ldr x0, =0x10002 +// CHECK: ldr x0, .Ltmp[[TMP1:[0-9]+]] + adds x0, x0, #1 + adds x0, x0, #1 + adds x0, x0, #1 + adds x0, x0, #1 + ldr x0, =0x10003 +// CHECK: ldr x0, .Ltmp[[TMP2:[0-9]+]] + adds x0, x0, #1 + adds x0, x0, #1 + +// TODO: the same constants should have the same constant pool location +.section d,"ax",@progbits +// CHECK-LABEL: f5: +f5: + ldr x0, =0x10004 +// CHECK: ldr x0, .Ltmp[[TMP3:[0-9]+]] + adds x0, x0, #1 + adds x0, x0, #1 + adds x0, x0, #1 + adds x0, x0, #1 + adds x0, x0, #1 + adds x0, x0, #1 + adds x0, x0, #1 + ldr x0, =0x10004 +// CHECK: ldr x0, .Ltmp[[TMP4:[0-9]+]] + adds x0, x0, #1 + adds x0, x0, #1 + adds x0, x0, #1 + adds x0, x0, #1 + adds x0, x0, #1 + adds x0, x0, #1 + +// a section defined in multiple pieces should be merged and use a single constant pool +.section e,"ax",@progbits +// CHECK-LABEL: f6: +f6: + ldr x0, =0x10006 +// CHECK: ldr x0, .Ltmp[[TMP5:[0-9]+]] + adds x0, x0, #1 + adds x0, x0, #1 + adds x0, x0, #1 + +.section f, "ax", @progbits +// CHECK-LABEL: f7: +f7: + adds x0, x0, #1 + adds x0, x0, #1 + adds x0, x0, #1 + +.section e, "ax", @progbits +// CHECK-LABEL: f8: +f8: + adds x0, x0, #1 + ldr x0, =0x10007 +// CHECK: ldr x0, .Ltmp[[TMP6:[0-9]+]] + adds x0, x0, #1 + adds x0, x0, #1 + +// +// Check that symbols can be loaded using ldr pseudo +// + +// load an undefined symbol +.section g,"ax",@progbits +// CHECK-LABEL: f9: +f9: + ldr x0, =foo +// CHECK: ldr x0, .Ltmp[[TMP7:[0-9]+]] + +// load a symbol from another section +.section h,"ax",@progbits +// CHECK-LABEL: f10: +f10: + ldr x0, =f5 +// CHECK: ldr x0, .Ltmp[[TMP8:[0-9]+]] + +// load a symbol from the same section +.section i,"ax",@progbits +// CHECK-LABEL: f11: +f11: + ldr x0, =f12 +// CHECK: ldr x0, .Ltmp[[TMP9:[0-9]+]] + ldr w0,=0x3C000 +// CHECK: ldr w0, .Ltmp[[TMP10:[0-9]+]] + +// CHECK-LABEL: f12: +f12: + adds x0, x0, #1 + adds x0, x0, #1 + +.section j,"ax",@progbits +// mix of symbols and constants +// CHECK-LABEL: f13: +f13: + adds x0, x0, #1 + adds x0, x0, #1 + ldr x0, =0x101 +// CHECK: movz x0, #0x101 + adds x0, x0, #1 + adds x0, x0, #1 + ldr x0, =bar +// CHECK: ldr x0, .Ltmp[[TMP11:[0-9]+]] + adds x0, x0, #1 + adds x0, x0, #1 +// +// Check for correct usage in other contexts +// + +// usage in macro +.macro useit_in_a_macro + ldr x0, =0x10008 + ldr x0, =baz +.endm +.section k,"ax",@progbits +// CHECK-LABEL: f14: +f14: + useit_in_a_macro +// CHECK: ldr x0, .Ltmp[[TMP12:[0-9]+]] +// CHECK: ldr x0, .Ltmp[[TMP13:[0-9]+]] + +// usage with expressions +.section l, "ax", @progbits +// CHECK-LABEL: f15: +f15: + ldr x0, =0x10001+8 +// CHECK: ldr x0, .Ltmp[[TMP14:[0-9]+]] + adds x0, x0, #1 + ldr x0, =bar+4 +// CHECK: ldr x0, .Ltmp[[TMP15:[0-9]+]] + adds x0, x0, #1 + +// +// Constant Pools +// +// CHECK: .section b,"ax",@progbits +// CHECK: .align 2 +// CHECK: .Ltmp[[TMP0]] +// CHECK: .word 65537 + +// CHECK: .section c,"ax",@progbits +// CHECK: .align 2 +// CHECK: .Ltmp[[TMP1]] +// CHECK: .word 65538 +// CHECK: .Ltmp[[TMP2]] +// CHECK: .word 65539 + +// CHECK: .section d,"ax",@progbits +// CHECK: .align 2 +// CHECK: .Ltmp[[TMP3]] +// CHECK: .word 65540 +// CHECK: .Ltmp[[TMP4]] +// CHECK: .word 65540 + +// CHECK: .section e,"ax",@progbits +// CHECK: .align 2 +// CHECK: .Ltmp[[TMP5]] +// CHECK: .word 65542 +// CHECK: .Ltmp[[TMP6]] +// CHECK: .word 65543 + +// Should not switch to section because it has no constant pool +// CHECK-NOT: .section f,"ax",@progbits + +// CHECK: .section g,"ax",@progbits +// CHECK: .align 2 +// CHECK: .Ltmp[[TMP7]] +// CHECK: .word foo + +// CHECK: .section h,"ax",@progbits +// CHECK: .align 2 +// CHECK: .Ltmp[[TMP8]] +// CHECK: .word f5 + +// CHECK: .section i,"ax",@progbits +// CHECK: .align 2 +// CHECK: .Ltmp[[TMP9]] +// CHECK: .word f12 +// CHECK: .Ltmp[[TMP10]] +// CHECK: .word 245760 + +// CHECK: .section j,"ax",@progbits +// CHECK: .align 2 +// CHECK: .Ltmp[[TMP11]] +// CHECK: .word bar + +// CHECK: .section k,"ax",@progbits +// CHECK: .align 2 +// CHECK: .Ltmp[[TMP12]] +// CHECK: .word 65544 +// CHECK: .Ltmp[[TMP13]] +// CHECK: .word baz + +// CHECK: .section l,"ax",@progbits +// CHECK: .align 2 +// CHECK: .Ltmp[[TMP14]] +// CHECK: .word 65545 +// CHECK: .Ltmp[[TMP15]] +// CHECK: .word bar+4 diff --git a/test/MC/AArch64/lit.local.cfg b/test/MC/AArch64/lit.local.cfg index 1be70c0..5822b72 100644 --- a/test/MC/AArch64/lit.local.cfg +++ b/test/MC/AArch64/lit.local.cfg @@ -1,3 +1,2 @@ -targets = set(config.root.targets_to_build.split()) -if 'AArch64' not in targets: +if 'AArch64' not in config.root.targets: config.unsupported = True diff --git a/test/MC/ARM/AlignedBundling/lit.local.cfg b/test/MC/ARM/AlignedBundling/lit.local.cfg index ba763cf..e71f3cc 100644 --- a/test/MC/ARM/AlignedBundling/lit.local.cfg +++ b/test/MC/ARM/AlignedBundling/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True diff --git a/test/MC/ARM/Windows/multiple-text-sections.s b/test/MC/ARM/Windows/multiple-text-sections.s new file mode 100644 index 0000000..241eee4 --- /dev/null +++ b/test/MC/ARM/Windows/multiple-text-sections.s @@ -0,0 +1,58 @@ +@ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \ +@ RUN: | llvm-readobj -s - | FileCheck %s + + .syntax unified + .text + .thumb + + .section .text,"xr",one_only,a + + .def a; + .scl 2; + .type 32; + .endef +a: + movs r0, #65 + bx lr + + .section .text,"xr",one_only,b + + .def b; + .scl 2; + .type 32; + .endef + .thumb_func +b: + movs r0, #66 + bx lr + +@ CHECK: Sections [ +@ CHECK: Section { +@ CHECK: Name: .text +@ CHECK: Characteristics [ +@ CHECK: IMAGE_SCN_CNT_CODE +@ CHECK: IMAGE_SCN_MEM_16BIT +@ CHECK: IMAGE_SCN_MEM_EXECUTE +@ CHECK: IMAGE_SCN_MEM_READ +@ CHECK: ] +@ CHECK: } +@ CHECK: Section { +@ CHECK: Name: .text +@ CHECK: Characteristics [ +@ CHECK: IMAGE_SCN_CNT_CODE +@ CHECK: IMAGE_SCN_MEM_16BIT +@ CHECK: IMAGE_SCN_MEM_EXECUTE +@ CHECK: IMAGE_SCN_MEM_READ +@ CHECK: ] +@ CHECK: } +@ CHECK: Section { +@ CHECK: Name: .text +@ CHECK: Characteristics [ +@ CHECK: IMAGE_SCN_CNT_CODE +@ CHECK: IMAGE_SCN_MEM_16BIT +@ CHECK: IMAGE_SCN_MEM_EXECUTE +@ CHECK: IMAGE_SCN_MEM_READ +@ CHECK: ] +@ CHECK: } +@ CHECK: ] + diff --git a/test/MC/ARM/Windows/text-attributes.s b/test/MC/ARM/Windows/text-attributes.s new file mode 100644 index 0000000..62aa028 --- /dev/null +++ b/test/MC/ARM/Windows/text-attributes.s @@ -0,0 +1,30 @@ +@ RUN: llvm-mc -triple thumbv7-windows-itanium -filetype obj -o - %s \ +@ RUN: | llvm-readobj -s - | FileCheck %s + + .syntax unified + .thumb + + .text + + .def function + .type 32 + .scl 2 + .endef + .global function + .thumb_func +function: + bx lr + +@ CHECK: Sections [ +@ CHECK: Section { +@ CHECK: Name: .text +@ CHECK: Characteristics [ +@ CHECK: IMAGE_SCN_ALIGN_4BYTES +@ CHECK: IMAGE_SCN_CNT_CODE +@ CHECK: IMAGE_SCN_MEM_16BIT +@ CHECK: IMAGE_SCN_MEM_EXECUTE +@ CHECK: IMAGE_SCN_MEM_PURGEABLE +@ CHECK: IMAGE_SCN_MEM_READ +@ CHECK: ] +@ CHECK: } +@ CHECK: ] diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s index 62d7dae..88c5fb5 100644 --- a/test/MC/ARM/diagnostics.s +++ b/test/MC/ARM/diagnostics.s @@ -351,6 +351,24 @@ @ CHECK-ERRORS: ubfxgt r4, r5, #16, #17 @ CHECK-ERRORS: ^ + @ Using pc for SBFX/UBFX + sbfx pc, r2, #1, #3 + sbfx sp, pc, #4, #5 + ubfx pc, r0, #0, #31 + ubfx r14, pc, #1, #2 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: sbfx pc, r2, #1, #3 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: sbfx sp, pc, #4, #5 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: ubfx pc, r0, #0, #31 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: ubfx r14, pc, #1, #2 +@ CHECK-ERRORS: ^ + @ Out of order Rt/Rt2 operands for ldrd ldrd r4, r3, [r8] ldrd r4, r3, [r8, #8]! diff --git a/test/MC/ARM/dwarf-asm-multiple-sections.s b/test/MC/ARM/dwarf-asm-multiple-sections.s new file mode 100644 index 0000000..ed1b89e --- /dev/null +++ b/test/MC/ARM/dwarf-asm-multiple-sections.s @@ -0,0 +1,79 @@ +// RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp +// RUN: llvm-dwarfdump %t | FileCheck -check-prefix DWARF %s +// RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s +// RUN: not llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 2 2>&1 | FileCheck -check-prefix VERSION %s +// RUN: not llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 1 2>&1 | FileCheck -check-prefix DWARF1 %s +// RUN: not llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 5 2>&1 | FileCheck -check-prefix DWARF5 %s + .section .text, "ax" +a: + mov r0, r0 + + .section foo, "ax" +b: + mov r1, r1 + +// DWARF: .debug_abbrev contents: +// DWARF: Abbrev table for offset: 0x00000000 +// DWARF: [1] DW_TAG_compile_unit DW_CHILDREN_yes +// DWARF: DW_AT_stmt_list DW_FORM_data4 +// DWARF: DW_AT_ranges DW_FORM_data4 +// DWARF: DW_AT_name DW_FORM_string +// DWARF: DW_AT_comp_dir DW_FORM_string +// DWARF: DW_AT_producer DW_FORM_string +// DWARF: DW_AT_language DW_FORM_data2 + +// DWARF: .debug_info contents: +// DWARF: 0x{{[0-9a-f]+}}: DW_TAG_compile_unit [1] +// CHECK-NOT-DWARF: DW_TAG_ +// DWARF: DW_AT_ranges [DW_FORM_data4] (0x00000000) + +// DWARF: 0x{{[0-9a-f]+}}: DW_TAG_label [2] * +// DWARF-NEXT: DW_AT_name [DW_FORM_string] ("a") + +// DWARF: 0x{{[0-9a-f]+}}: DW_TAG_label [2] * +// DWARF-NEXT: DW_AT_name [DW_FORM_string] ("b") + + +// DWARF: .debug_aranges contents: +// DWARF-NEXT: Address Range Header: length = 0x00000024, version = 0x0002, cu_offset = 0x00000000, addr_size = 0x04, seg_size = 0x00 +// DWARF-NEXT: [0x00000000 - 0x00000004) +// DWARF-NEXT: [0x00000000 - 0x00000004) + + +// DWARF: .debug_line contents: +// DWARF: 0x0000000000000000 9 0 1 0 0 is_stmt +// DWARF-NEXT: 0x0000000000000004 9 0 1 0 0 is_stmt end_sequence +// DWARF-NEXT: 0x0000000000000000 13 0 1 0 0 is_stmt +// DWARF-NEXT: 0x0000000000000004 13 0 1 0 0 is_stmt end_sequence + + +// DWARF: .debug_ranges contents: +// DWARF: 00000000 ffffffff 00000000 +// DWARF: 00000000 00000000 00000004 +// DWARF: 00000000 ffffffff 00000000 +// DWARF: 00000000 00000000 00000004 +// DWARF: 00000000 <End of list> + + + +// RELOC: RELOCATION RECORDS FOR [.rel.debug_info]: +// RELOC-NEXT: 00000006 R_ARM_ABS32 .debug_abbrev +// RELOC-NEXT: 0000000c R_ARM_ABS32 .debug_line +// RELOC-NEXT: 00000010 R_ARM_ABS32 .debug_ranges +// RELOC-NEXT: R_ARM_ABS32 .text +// RELOC-NEXT: R_ARM_ABS32 foo + +// RELOC: RELOCATION RECORDS FOR [.rel.debug_ranges]: +// RELOC-NEXT: 00000004 R_ARM_ABS32 .text +// RELOC-NEXT: 00000014 R_ARM_ABS32 foo + +// RELOC: RELOCATION RECORDS FOR [.rel.debug_aranges]: +// RELOC-NEXT: 00000006 R_ARM_ABS32 .debug_info +// RELOC-NEXT: 00000010 R_ARM_ABS32 .text +// RELOC-NEXT: 00000018 R_ARM_ABS32 foo + + +// VERSION: {{.*}} error: DWARF2 only supports one section per compilation unit + +// DWARF1: Dwarf version 1 is not supported. +// DWARF5: Dwarf version 5 is not supported. diff --git a/test/MC/ARM/dwarf-asm-no-code.s b/test/MC/ARM/dwarf-asm-no-code.s new file mode 100644 index 0000000..7d06a41 --- /dev/null +++ b/test/MC/ARM/dwarf-asm-no-code.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp +// RUN: llvm-dwarfdump %t | FileCheck -check-prefix DWARF %s +// RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s + +// If there is no code in an assembly file, no debug info is produced + +.section .data, "aw" +a: +.long 42 + +// DWARF: .debug_abbrev contents: +// DWARF-NEXT: < EMPTY > + +// DWARF: .debug_info contents: + +// DWARF: .debug_aranges contents: + +// DWARF: .debug_line contents: + +// DWARF: .debug_ranges contents: + + +// RELOC-NOT: RELOCATION RECORDS FOR [.rel.debug_info]: + +// RELOC-NOT: RELOCATION RECORDS FOR [.rel.debug_ranges]: + +// RELOC-NOT: RELOCATION RECORDS FOR [.rel.debug_aranges]: diff --git a/test/MC/ARM/dwarf-asm-nonstandard-section.s b/test/MC/ARM/dwarf-asm-nonstandard-section.s new file mode 100644 index 0000000..497a39a --- /dev/null +++ b/test/MC/ARM/dwarf-asm-nonstandard-section.s @@ -0,0 +1,57 @@ +// RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp +// RUN: llvm-dwarfdump %t | FileCheck -check-prefix DWARF %s +// RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s + + .section foo, "ax" +b: + mov r1, r1 + +// DWARF: .debug_abbrev contents: +// DWARF: Abbrev table for offset: 0x00000000 +// DWARF: [1] DW_TAG_compile_unit DW_CHILDREN_yes +// DWARF: DW_AT_stmt_list DW_FORM_data4 +// DWARF: DW_AT_low_pc DW_FORM_addr +// DWARF: DW_AT_high_pc DW_FORM_addr +// DWARF: DW_AT_name DW_FORM_string +// DWARF: DW_AT_comp_dir DW_FORM_string +// DWARF: DW_AT_producer DW_FORM_string +// DWARF: DW_AT_language DW_FORM_data2 + +// DWARF: .debug_info contents: +// DWARF: 0x{{[0-9a-f]+}}: DW_TAG_compile_unit [1] +// DWARF-NOT: DW_TAG_ +// DWARF: DW_AT_low_pc [DW_FORM_addr] (0x0000000000000000) +// DWARF: DW_AT_high_pc [DW_FORM_addr] (0x0000000000000004) + +// DWARF: 0x{{[0-9a-f]+}}: DW_TAG_label [2] * +// DWARF-NEXT: DW_AT_name [DW_FORM_string] ("b") + + +// DWARF: .debug_aranges contents: +// DWARF-NEXT: Address Range Header: length = 0x0000001c, version = 0x0002, cu_offset = 0x00000000, addr_size = 0x04, seg_size = 0x00 +// DWARF-NEXT: [0x00000000 - 0x00000004) + + +// DWARF: .debug_line contents: +// DWARF: 0x0000000000000000 7 0 1 0 0 is_stmt +// DWARF-NEXT: 0x0000000000000004 7 0 1 0 0 is_stmt end_sequence + + +// DWARF: .debug_ranges contents: +// DWARF-NOT: {{0-9a-f}} +// DWARF: .debug_pubnames contents: + + + +// RELOC: RELOCATION RECORDS FOR [.rel.debug_info]: +// RELOC-NEXT: 00000006 R_ARM_ABS32 .debug_abbrev +// RELOC-NEXT: 0000000c R_ARM_ABS32 .debug_line +// RELOC-NEXT: R_ARM_ABS32 foo +// RELOC-NEXT: R_ARM_ABS32 foo +// RELOC-NEXT: R_ARM_ABS32 foo + +// RELOC-NOT: RELOCATION RECORDS FOR [.rel.debug_ranges]: + +// RELOC: RELOCATION RECORDS FOR [.rel.debug_aranges]: +// RELOC-NEXT: 00000006 R_ARM_ABS32 .debug_info +// RELOC-NEXT: 00000010 R_ARM_ABS32 foo diff --git a/test/MC/ARM/dwarf-asm-single-section.s b/test/MC/ARM/dwarf-asm-single-section.s new file mode 100644 index 0000000..c57e649 --- /dev/null +++ b/test/MC/ARM/dwarf-asm-single-section.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp +// RUN: llvm-dwarfdump %t | FileCheck -check-prefix DWARF %s +// RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s + + .section .text, "ax" +a: + mov r0, r0 + + +// DWARF: .debug_abbrev contents: +// DWARF: Abbrev table for offset: 0x00000000 +// DWARF: [1] DW_TAG_compile_unit DW_CHILDREN_yes +// DWARF: DW_AT_stmt_list DW_FORM_data4 +// DWARF: DW_AT_low_pc DW_FORM_addr +// DWARF: DW_AT_high_pc DW_FORM_addr +// DWARF: DW_AT_name DW_FORM_string +// DWARF: DW_AT_comp_dir DW_FORM_string +// DWARF: DW_AT_producer DW_FORM_string +// DWARF: DW_AT_language DW_FORM_data2 + +// DWARF: .debug_info contents: +// DWARF: 0x{{[0-9a-f]+}}: DW_TAG_compile_unit [1] +// CHECK-NOT-DWARF: DW_TAG_ +// DWARF: DW_AT_low_pc [DW_FORM_addr] (0x0000000000000000) +// DWARF: DW_AT_high_pc [DW_FORM_addr] (0x0000000000000004) + +// DWARF: 0x{{[0-9a-f]+}}: DW_TAG_label [2] * +// DWARF-NEXT: DW_AT_name [DW_FORM_string] ("a") + + +// DWARF: .debug_aranges contents: +// DWARF-NEXT: Address Range Header: length = 0x0000001c, version = 0x0002, cu_offset = 0x00000000, addr_size = 0x04, seg_size = 0x00 +// DWARF-NEXT: [0x00000000 - 0x00000004) + +// DWARF: .debug_line contents: +// DWARF: 0x0000000000000000 7 0 1 0 0 is_stmt +// DWARF-NEXT: 0x0000000000000004 7 0 1 0 0 is_stmt end_sequence + + +// DWARF: .debug_ranges contents: +// DWARF-NOT: {{0-9a-f}} +// DWARF: .debug_pubnames contents: + + +// RELOC: RELOCATION RECORDS FOR [.rel.debug_info]: +// RELOC-NEXT: 00000006 R_ARM_ABS32 .debug_abbrev +// RELOC-NEXT: 0000000c R_ARM_ABS32 .debug_line +// RELOC-NEXT: R_ARM_ABS32 .text +// RELOC-NEXT: R_ARM_ABS32 .text +// RELOC-NEXT: R_ARM_ABS32 .text + +// RELOC-NOT: RELOCATION RECORDS FOR [.rel.debug_ranges]: + +// RELOC: RELOCATION RECORDS FOR [.rel.debug_aranges]: +// RELOC-NEXT: 00000006 R_ARM_ABS32 .debug_info +// RELOC-NEXT: 00000010 R_ARM_ABS32 .text diff --git a/test/MC/ARM/gas-compl-copr-reg.s b/test/MC/ARM/gas-compl-copr-reg.s new file mode 100644 index 0000000..ab0b023 --- /dev/null +++ b/test/MC/ARM/gas-compl-copr-reg.s @@ -0,0 +1,14 @@ +@ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s + +@ CHECK: ldc p12, c4, [r0, #4] @ encoding: [0x01,0x4c,0x90,0xed] +@ CHECK: stc p14, c6, [r2, #-224] @ encoding: [0x38,0x6e,0x02,0xed] + + ldc p12, cr4, [r0, #4] + stc p14, cr6, [r2, #-224] +@ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
+
+@ CHECK: ldc p12, c4, [r0, #4] @ encoding: [0x01,0x4c,0x90,0xed]
+@ CHECK: stc p14, c6, [r2, #-224] @ encoding: [0x38,0x6e,0x02,0xed]
+
+ ldc p12, cr4, [r0, #4]
+ stc p14, cr6, [r2, #-224]
diff --git a/test/MC/ARM/lit.local.cfg b/test/MC/ARM/lit.local.cfg index 8a3ba96..98c6700 100644 --- a/test/MC/ARM/lit.local.cfg +++ b/test/MC/ARM/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'ARM' in targets: +if not 'ARM' in config.root.targets: config.unsupported = True diff --git a/test/MC/ARM/macho-relocs-with-addend.s b/test/MC/ARM/macho-relocs-with-addend.s new file mode 100644 index 0000000..fee930e --- /dev/null +++ b/test/MC/ARM/macho-relocs-with-addend.s @@ -0,0 +1,34 @@ +@ RUN: llvm-mc -triple thumbv7-apple-ios7.0 -filetype=obj -o - %s | \ +@ RUN: llvm-readobj -r - | FileCheck %s + + @ MachO relocations that end up expressed as internal + @ (scattered) still need to have the type set correctly. + + .text + .thumb_func + .thumb + .globl _with_thumb +_with_thumb: + bl _dest+10 + blx _dest+20 + + .globl _with_arm + .arm +_with_arm: + bl _dest+10 + blx _dest+20 + bne _dest+30 + b _dest+40 + + .data +_dest: + .word 42 + +@ CHECK: Relocations [ +@ CHECK-NEXT: Section __text { +@ CHECK-NEXT: 0x14 1 2 n/a ARM_RELOC_BR24 1 0x18 +@ CHECK-NEXT: 0x10 1 2 n/a ARM_RELOC_BR24 1 0x18 +@ CHECK-NEXT: 0xC 1 2 n/a ARM_RELOC_BR24 1 0x18 +@ CHECK-NEXT: 0x8 1 2 n/a ARM_RELOC_BR24 1 0x18 +@ CHECK-NEXT: 0x4 1 2 n/a ARM_THUMB_RELOC_BR22 1 0x18 +@ CHECK-NEXT: 0x0 1 2 n/a ARM_THUMB_RELOC_BR22 1 0x18 diff --git a/test/MC/ARM/thumb-types.s b/test/MC/ARM/thumb-types.s index 2fd7152..b3aaf7d 100644 --- a/test/MC/ARM/thumb-types.s +++ b/test/MC/ARM/thumb-types.s @@ -29,6 +29,12 @@ untyped_text_label: explicit_function: nop + .long tls(TPOFF) + + .type indirect_function,%gnu_indirect_function +indirect_function: + nop + .data untyped_data_label: @@ -38,6 +44,14 @@ untyped_data_label: explicit_data: .long 0 + .section .tdata,"awT",%progbits + .type tls,%object + .align 2 +tls: + .long 42 + .size tls, 4 + + @ CHECK: Symbol { @ CHECK: Name: arm_function @ CHECK: Value: 0x6 @@ -69,6 +83,18 @@ explicit_data: @ CHECK: } @ CHECK: Symbol { +@ CHECK: Name: indirect_function +@ CHECK: Value: 0x13 +@ CHECK: Type: GNU_IFunc +@ CHECK: } + +@ CHECK: Symbol { +@ CHECK: Name: tls +@ CHECK: Value: 0x0 +@ CHECK: Type: TLS +@ CHECK: } + +@ CHECK: Symbol { @ CHECK: Name: untyped_data_label @ CHECK: Value: 0x0 @ CHECK: Type: None diff --git a/test/MC/AsmParser/cfi-invalid-startproc.s b/test/MC/AsmParser/cfi-invalid-startproc.s deleted file mode 100644 index 57ded13..0000000 --- a/test/MC/AsmParser/cfi-invalid-startproc.s +++ /dev/null @@ -1,16 +0,0 @@ -# RUN: not llvm-mc -triple=x86_64-apple-macosx10.8 -filetype=obj -o %t %s 2>&1 | FileCheck %s -# Check that the cfi_startproc is declared after the beginning of -# a procedure, otherwise it will reference an invalid symbol for -# emitting the relocation. -# <rdar://problem/15939159> - -# CHECK: No symbol to start a frame -.text -.cfi_startproc -.globl _someFunction -_someFunction: -.cfi_def_cfa_offset 16 -.cfi_offset %rbp, -16 -.cfi_def_cfa_register rbp - ret -.cfi_endproc diff --git a/test/MC/AsmParser/conditional_asm.s b/test/MC/AsmParser/conditional_asm.s index b9bee33..ecbceb1 100644 --- a/test/MC/AsmParser/conditional_asm.s +++ b/test/MC/AsmParser/conditional_asm.s @@ -11,6 +11,66 @@ .endif .endif +# CHECK: .byte 0 +# CHECK-NOT: .byte 1 +.ifeq 32 - 32 + .byte 0 +.else + .byte 1 +.endif + +# CHECK: .byte 0 +# CHECK: .byte 1 +# CHECK-NOT: .byte 2 +.ifge 32 - 31 + .byte 0 +.endif +.ifge 32 - 32 + .byte 1 +.endif +.ifge 32 - 33 + .byte 2 +.endif + +# CHECK: .byte 0 +# CHECK-NOT: .byte 1 +# CHECK-NOT: .byte 2 +.ifgt 32 - 31 + .byte 0 +.endif +.ifgt 32 - 32 + .byte 1 +.endif +.ifgt 32 - 33 + .byte 2 +.endif + +# CHECK-NOT: .byte 0 +# CHECK: .byte 1 +# CHECK: .byte 2 +.ifle 32 - 31 + .byte 0 +.endif +.ifle 32 - 32 + .byte 1 +.endif +.ifle 32 - 33 + .byte 2 +.endif + +# CHECK-NOT: .byte 0 +# CHECK-NOT: .byte 1 +# CHECK: .byte 2 +.iflt 32 - 31 + .byte 0 +.endif +.iflt 32 - 32 + .byte 1 +.endif +.iflt 32 - 33 + .byte 2 +.endif + # CHECK: .byte 1 # CHECK-NOT: .byte 0 .ifne 32 - 32 diff --git a/test/MC/AsmParser/directive_file.s b/test/MC/AsmParser/directive_file.s index 9b99e0f..d7290eb 100644 --- a/test/MC/AsmParser/directive_file.s +++ b/test/MC/AsmParser/directive_file.s @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s +# RUN: llvm-mc -triple i386-unknown-unknown %s -filetype=null .file "hello" .file 1 "worl\144" # "\144" is "d" diff --git a/test/MC/AsmParser/directive_line.s b/test/MC/AsmParser/directive_line.s index 94ce446..110b68a 100644 --- a/test/MC/AsmParser/directive_line.s +++ b/test/MC/AsmParser/directive_line.s @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple i386-unknown-unknown %s +# RUN: llvm-mc -triple i386-unknown-unknown %s -filetype=null # FIXME: Actually test the output. .line diff --git a/test/MC/AsmParser/directive_loc.s b/test/MC/AsmParser/directive_loc.s index cda9579..404ebce 100644 --- a/test/MC/AsmParser/directive_loc.s +++ b/test/MC/AsmParser/directive_loc.s @@ -1,4 +1,5 @@ # RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s +# RUN: llvm-mc -triple i386-unknown-unknown %s -filetype=null .file 1 "hello" # CHECK: .file 1 "hello" diff --git a/test/MC/AsmParser/directive_seh.s b/test/MC/AsmParser/directive_seh.s index f6eb970..1821747 100644 --- a/test/MC/AsmParser/directive_seh.s +++ b/test/MC/AsmParser/directive_seh.s @@ -1,36 +1,25 @@ # RUN: llvm-mc -triple x86_64-pc-win32 %s | FileCheck %s -# CHECK: .seh_proc func -# CHECK: .seh_pushframe @code -# CHECK: .seh_stackalloc 24 -# CHECK: .seh_savereg %rbp, 16 -# CHECK: .seh_savexmm %r8, 0 -# CHECK: .seh_pushreg %rbx -# CHECK: .seh_setframe %rbx, 0 -# CHECK: .seh_endprologue -# CHECK: .seh_handler __C_specific_handler, @except -# CHECK-NOT: .section{{.*}}.xdata -# CHECK: .seh_handlerdata -# CHECK: .text -# CHECK: .seh_startchained -# CHECK: .seh_endprologue -# CHECK: .seh_endchained -# CHECK: .seh_endproc - .text .globl func .def func; .scl 2; .type 32; .endef .seh_proc func +# CHECK: .seh_proc func func: .seh_pushframe @code +# CHECK: .seh_pushframe @code subq $24, %rsp .seh_stackalloc 24 +# CHECK: .seh_stackalloc 24 movq %rsi, 16(%rsp) .seh_savereg %rsi, 16 +# CHECK: .seh_savereg 6, 16 movups %xmm8, (%rsp) .seh_savexmm %xmm8, 0 +# CHECK: .seh_savexmm 8, 0 pushq %rbx .seh_pushreg 3 +# CHECK: .seh_pushreg 3 mov %rsp, %rbx .seh_setframe 3, 0 .seh_endprologue @@ -41,8 +30,18 @@ func: .seh_startchained .seh_endprologue .seh_endchained +# CHECK: .seh_setframe 3, 0 +# CHECK: .seh_endprologue +# CHECK: .seh_handler __C_specific_handler, @except +# CHECK-NOT: .section{{.*}}.xdata +# CHECK: .seh_handlerdata +# CHECK: .text +# CHECK: .seh_startchained +# CHECK: .seh_endprologue +# CHECK: .seh_endchained lea (%rbx), %rsp pop %rbx addq $24, %rsp ret .seh_endproc +# CHECK: .seh_endproc diff --git a/test/MC/AsmParser/if-diagnostics.s b/test/MC/AsmParser/if-diagnostics.s new file mode 100644 index 0000000..d102a56 --- /dev/null +++ b/test/MC/AsmParser/if-diagnostics.s @@ -0,0 +1,29 @@ +// RUN: not llvm-mc -triple i386 %s -o /dev/null 2>&1 | FileCheck %s + +.if +.endif + +// CHECK: error: unknown token in expression +// CHECK: .if +// CHECK: ^ + +.ifeq 0, 3 +.endif + +// CHECK:error: unexpected token in '.if' directive +// CHECK: .ifeq 0, 3 +// CHECK: ^ + +.iflt "string1" +.endif + +// CHECK: error: expected absolute expression +// CHECK: .iflt "string1" +// CHECK: ^ + +.ifge test +.endif + +// CHECK: error: expected absolute expression +// CHECK: .ifge test +// CHECK: ^ diff --git a/test/MC/AsmParser/lit.local.cfg b/test/MC/AsmParser/lit.local.cfg index ba763cf..e71f3cc 100644 --- a/test/MC/AsmParser/lit.local.cfg +++ b/test/MC/AsmParser/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True diff --git a/test/MC/AsmParser/vararg.s b/test/MC/AsmParser/vararg.s index b27668e..e3236b0 100644 --- a/test/MC/AsmParser/vararg.s +++ b/test/MC/AsmParser/vararg.s @@ -17,6 +17,12 @@ .endif .endm +.macro ifcc4 arg0, arg1:vararg +.if cc + movl \arg1, \arg0 +.endif +.endm + .text // CHECK: movl %esp, %ebp @@ -25,6 +31,8 @@ // CHECK: movl %ecx, %ebx // CHECK: movl %ecx, %eax // CHECK: movl %eax, %ecx +// CHECK: movl %ecx, %eax +// CHECK: movl %eax, %ecx .set cc,1 ifcc movl %esp, %ebp subl $0, %esp @@ -33,6 +41,8 @@ ifcc2 %ecx, %ebx ifcc3 %ecx %eax ifcc3 %eax, %ecx + ifcc4 %eax %ecx ## test + ifcc4 %ecx, %eax ## test // CHECK-NOT movl // CHECK: subl $1, %esp diff --git a/test/MC/COFF/alias.s b/test/MC/COFF/alias.s index dc4f65a..eb5398a 100644 --- a/test/MC/COFF/alias.s +++ b/test/MC/COFF/alias.s @@ -1,4 +1,5 @@ -// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s -o - | llvm-readobj -t -r | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s -o - \ +// RUN: | llvm-readobj -t -r | FileCheck %s local1: external_aliased_to_local = local1 @@ -36,7 +37,7 @@ weak_aliased_to_external = external2 // CHECK-NEXT: AuxSymbolCount: 1 // CHECK: } // CHECK: Symbol { -// CHECK-NEXT: Name: local1 +// CHECK: Name: local1 // CHECK-NEXT: Value: 0 // CHECK-NEXT: Section: .text (1) // CHECK-NEXT: BaseType: Null (0x0) @@ -89,7 +90,7 @@ weak_aliased_to_external = external2 // CHECK-NEXT: StorageClass: WeakExternal (0x69) // CHECK-NEXT: AuxSymbolCount: 1 // CHECK-NEXT: AuxWeakExternal { -// CHECK-NEXT: Linked: external2 (9) +// CHECK-NEXT: Linked: external2 (13) // CHECK-NEXT: Search: Library (0x2) // CHECK-NEXT: Unused: (00 00 00 00 00 00 00 00 00 00) // CHECK-NEXT: } diff --git a/test/MC/COFF/basic-coff-64.s b/test/MC/COFF/basic-coff-64.s index 89d1745..38a9e57 100644 --- a/test/MC/COFF/basic-coff-64.s +++ b/test/MC/COFF/basic-coff-64.s @@ -25,10 +25,10 @@ _main: # @main // CHECK: ImageFileHeader { // CHECK: Machine: IMAGE_FILE_MACHINE_AMD64 -// CHECK: SectionCount: 2 +// CHECK: SectionCount: 3 // CHECK: TimeDateStamp: {{[0-9]+}} // CHECK: PointerToSymbolTable: 0x{{[0-9A-F]+}} -// CHECK: SymbolCount: 6 +// CHECK: SymbolCount: 8 // CHECK: OptionalHeaderSize: 0 // CHECK: Characteristics [ (0x0) // CHECK: ] diff --git a/test/MC/COFF/basic-coff.s b/test/MC/COFF/basic-coff.s index 9b29970..38bfa6d 100644 --- a/test/MC/COFF/basic-coff.s +++ b/test/MC/COFF/basic-coff.s @@ -25,10 +25,10 @@ L_.str: # @.str // CHECK: ImageFileHeader { // CHECK: Machine: IMAGE_FILE_MACHINE_I386 -// CHECK: SectionCount: 2 +// CHECK: SectionCount: 3 // CHECK: TimeDateStamp: {{[0-9]+}} // CHECK: PointerToSymbolTable: 0x{{[0-9A-F]+}} -// CHECK: SymbolCount: 6 +// CHECK: SymbolCount: 8 // CHECK: OptionalHeaderSize: 0 // CHECK: Characteristics [ (0x0) // CHECK: ] diff --git a/test/MC/COFF/early-dce.s b/test/MC/COFF/early-dce.s new file mode 100644 index 0000000..ec1a9bd --- /dev/null +++ b/test/MC/COFF/early-dce.s @@ -0,0 +1,16 @@ +# RUN: llvm-mc -triple i686-windows -g -filetype obj -o - %s \ +# RUN: | llvm-readobj -s -t | FileCheck %s + + .section .rdata + + .align 8 + .global data +data: + .quad 0 + +# CHECK: Sections [ +# CHECK: Section { +# CHECK: Name: .text +# CHECK: } +# CHECK: ] + diff --git a/test/MC/COFF/global_ctors_dtors.ll b/test/MC/COFF/global_ctors_dtors.ll index 046e93a..ca17f24 100644 --- a/test/MC/COFF/global_ctors_dtors.ll +++ b/test/MC/COFF/global_ctors_dtors.ll @@ -11,9 +11,10 @@ %ini = type { i32, void()*, i8* } -@llvm.global_ctors = appending global [2 x %ini ] [ +@llvm.global_ctors = appending global [3 x %ini ] [ %ini { i32 65535, void ()* @a_global_ctor, i8* null }, - %ini { i32 65535, void ()* @b_global_ctor, i8* bitcast (i32* @b to i8*) } + %ini { i32 65535, void ()* @b_global_ctor, i8* bitcast (i32* @b to i8*) }, + %ini { i32 65535, void ()* @c_global_ctor, i8* bitcast (i32* @c to i8*) } ] @llvm.global_dtors = appending global [1 x %ini ] [%ini { i32 65535, void ()* @a_global_dtor, i8* null }] @@ -26,11 +27,18 @@ define void @a_global_ctor() nounwind { @b = global i32 zeroinitializer +@c = available_externally dllimport global i32 zeroinitializer + define void @b_global_ctor() nounwind { store i32 42, i32* @b ret void } +define void @c_global_ctor() nounwind { + store i32 42, i32* @c + ret void +} + define void @a_global_dtor() nounwind { %1 = call i32 @puts(i8* getelementptr inbounds ([12 x i8]* @.str2, i32 0, i32 0)) ret void @@ -43,13 +51,15 @@ define i32 @main() nounwind { ; WIN32: .section .CRT$XCU,"rd" ; WIN32: a_global_ctor -; WIN32: .section .CRT$XCU,"rd",associative .bss,{{_?}}b +; WIN32: .section .CRT$XCU,"rd",associative,{{_?}}b ; WIN32: b_global_ctor +; WIN32-NOT: c_global_ctor ; WIN32: .section .CRT$XTX,"rd" ; WIN32: a_global_dtor ; MINGW32: .section .ctors,"wd" ; MINGW32: a_global_ctor -; MINGW32: .section .ctors,"wd",associative .bss,{{_?}}b +; MINGW32: .section .ctors,"wd",associative,{{_?}}b ; MINGW32: b_global_ctor +; MINGW32-NOT: c_global_ctor ; MINGW32: .section .dtors,"wd" ; MINGW32: a_global_dtor diff --git a/test/MC/COFF/linker-options.ll b/test/MC/COFF/linker-options.ll index de11941..0be74e5 100755 --- a/test/MC/COFF/linker-options.ll +++ b/test/MC/COFF/linker-options.ll @@ -5,6 +5,7 @@ metadata !{ metadata !"/DEFAULTLIB:msvcrt.lib" }, metadata !{ metadata !"/DEFAULTLIB:msvcrt.lib", metadata !"/DEFAULTLIB:secur32.lib" }, + metadata !{ metadata !"/DEFAULTLIB:C:\5Cpath to\5Casan_rt.lib" }, metadata !{ metadata !"/with spaces" } } } !llvm.module.flags = !{ !0 } @@ -17,5 +18,6 @@ define dllexport void @foo() { ; CHECK: .ascii " /DEFAULTLIB:msvcrt.lib" ; CHECK: .ascii " /DEFAULTLIB:msvcrt.lib" ; CHECK: .ascii " /DEFAULTLIB:secur32.lib" +; CHECK: .ascii " \"/DEFAULTLIB:C:\\path to\\asan_rt.lib\"" ; CHECK: .ascii " \"/with spaces\"" ; CHECK: .ascii " /EXPORT:_foo" diff --git a/test/MC/COFF/linkonce-invalid.s b/test/MC/COFF/linkonce-invalid.s index 90ce4a7..cc3a27c 100644 --- a/test/MC/COFF/linkonce-invalid.s +++ b/test/MC/COFF/linkonce-invalid.s @@ -19,21 +19,9 @@ // CHECK: error: unexpected token in directive .linkonce discard foo -// CHECK: error: expected associated section name +// CHECK: error: cannot make section associative with .linkonce .linkonce associative -// CHECK: error: cannot associate unknown section 'unknown' -.linkonce associative unknown - -// CHECK: error: cannot associate a section with itself -.linkonce associative invalid - -// CHECK: error: associated section must be a COMDAT section -.linkonce associative non_comdat - -// CHECK: error: associated section cannot be itself associative -.linkonce associative assoc - // CHECK: error: section 'multi' is already linkonce .section multi .linkonce discard diff --git a/test/MC/COFF/linkonce.s b/test/MC/COFF/linkonce.s index e7b7f47..f2e3506 100644 --- a/test/MC/COFF/linkonce.s +++ b/test/MC/COFF/linkonce.s @@ -24,7 +24,6 @@ .long 1 .section s6 -.linkonce associative s1 .long 1 .section s7 @@ -39,11 +38,6 @@ .linkonce discard .long 1 -// Check that valid '.section' names can be associated. -.section multi -.linkonce associative .foo$bar -.long 1 - // CHECK: Sections [ // CHECK: Section { @@ -79,7 +73,6 @@ // CHECK: Section { // CHECK: Name: s6 // CHECK: Characteristics [ -// CHECK: IMAGE_SCN_LNK_COMDAT // CHECK: ] // CHECK: } // CHECK: Section { @@ -94,86 +87,64 @@ // CHECK: IMAGE_SCN_LNK_COMDAT // CHECK: ] // CHECK: } -// CHECK: Section { -// CHECK: Name: multi -// CHECK: Characteristics [ -// CHECK: IMAGE_SCN_LNK_COMDAT -// CHECK: ] -// CHECK: } // CHECK: ] // CHECK: Symbols [ // CHECK: Symbol { // CHECK: Name: s1 -// CHECK: Section: s1 (1) +// CHECK: Section: s1 (4) // CHECK: AuxSectionDef { -// CHECK: Number: 1 +// CHECK: Number: 4 // CHECK: Selection: Any (0x2) // CHECK: } // CHECK: } // CHECK: Symbol { // CHECK: Name: s2 -// CHECK: Section: s2 (2) +// CHECK: Section: s2 (5) // CHECK: AuxSectionDef { -// CHECK: Number: 2 +// CHECK: Number: 5 // CHECK: Selection: NoDuplicates (0x1) // CHECK: } // CHECK: } // CHECK: Symbol { // CHECK: Name: s3 -// CHECK: Section: s3 (3) +// CHECK: Section: s3 (6) // CHECK: AuxSectionDef { -// CHECK: Number: 3 +// CHECK: Number: 6 // CHECK: Selection: Any (0x2) // CHECK: } // CHECK: } // CHECK: Symbol { // CHECK: Name: s4 -// CHECK: Section: s4 (4) +// CHECK: Section: s4 (7) // CHECK: AuxSectionDef { -// CHECK: Number: 4 +// CHECK: Number: 7 // CHECK: Selection: SameSize (0x3) // CHECK: } // CHECK: } // CHECK: Symbol { // CHECK: Name: s5 -// CHECK: Section: s5 (5) +// CHECK: Section: s5 (8) // CHECK: AuxSectionDef { -// CHECK: Number: 5 +// CHECK: Number: 8 // CHECK: Selection: ExactMatch (0x4) // CHECK: } // CHECK: } // CHECK: Symbol { // CHECK: Name: s6 -// CHECK: Section: s6 (6) -// CHECK: AuxSectionDef { -// CHECK: Number: 1 -// CHECK: Selection: Associative (0x5) -// CHECK: AssocSection: s1 -// CHECK: } // CHECK: } // CHECK: Symbol { // CHECK: Name: s7 -// CHECK: Section: s7 (7) +// CHECK: Section: s7 (10) // CHECK: AuxSectionDef { -// CHECK: Number: 7 +// CHECK: Number: 10 // CHECK: Selection: Largest (0x6) // CHECK: } // CHECK: } // CHECK: Symbol { // CHECK: Name: s8 -// CHECK: Section: s8 (8) +// CHECK: Section: s8 (11) // CHECK: AuxSectionDef { -// CHECK: Number: 8 +// CHECK: Number: 11 // CHECK: Selection: Newest (0x7) // CHECK: } // CHECK: } -// CHECK: Symbol { -// CHECK: Name: multi -// CHECK: Value: 0 -// CHECK: Section: multi (10) -// CHECK: AuxSectionDef { -// CHECK: Number: 9 -// CHECK: Selection: Associative (0x5) -// CHECK: AssocSection: .foo$bar -// CHECK: } -// CHECK: } diff --git a/test/MC/COFF/lit.local.cfg b/test/MC/COFF/lit.local.cfg index ba763cf..e71f3cc 100644 --- a/test/MC/COFF/lit.local.cfg +++ b/test/MC/COFF/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True diff --git a/test/MC/COFF/lset0.s b/test/MC/COFF/lset0.s index f5020c8..7321b01 100755 --- a/test/MC/COFF/lset0.s +++ b/test/MC/COFF/lset0.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s -o - | llvm-nm | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s -o - | llvm-nm - | FileCheck %s not_global = 123 global = 456 diff --git a/test/MC/COFF/section-comdat-conflict.s b/test/MC/COFF/section-comdat-conflict.s new file mode 100644 index 0000000..7ed452a --- /dev/null +++ b/test/MC/COFF/section-comdat-conflict.s @@ -0,0 +1,13 @@ +// RUN: not llvm-mc -triple i386-pc-win32 -filetype=obj < %s 2>&1 | FileCheck %s + +// CHECK: conflicting sections for symbol + + .section .xyz + .global bar +bar: + .long 42 + + .section .abcd,"xr",discard,bar + .global foo +foo: + .long 42 diff --git a/test/MC/COFF/section-comdat-conflict2.s b/test/MC/COFF/section-comdat-conflict2.s new file mode 100644 index 0000000..e2dfc2d --- /dev/null +++ b/test/MC/COFF/section-comdat-conflict2.s @@ -0,0 +1,6 @@ +// RUN: not llvm-mc -triple i386-pc-win32 -filetype=obj < %s 2>&1 | FileCheck %s + +// CHECK: two sections have the same comdat + + .section .xyz,"xr",discard,bar + .section .abcd,"xr",discard,bar diff --git a/test/MC/COFF/section-comdat.s b/test/MC/COFF/section-comdat.s index dd5be87..e7052d8 100644 --- a/test/MC/COFF/section-comdat.s +++ b/test/MC/COFF/section-comdat.s @@ -1,8 +1,7 @@ // RUN: llvm-mc -triple i386-pc-win32 -filetype=obj %s | llvm-readobj -s -t | FileCheck %s // RUN: llvm-mc -triple x86_64-pc-win32 -filetype=obj %s | llvm-readobj -s -t | FileCheck %s -.section assocSec -.linkonce +.section assocSec, "dr", discard, "assocSym" .long 1 .section secName, "dr", discard, "Symbol1" @@ -25,7 +24,7 @@ Symbol3: Symbol4: .long 1 -.section SecName, "dr", associative assocSec, "Symbol5" +.section SecName, "dr", associative, "assocSym" .globl Symbol5 Symbol5: .long 1 @@ -40,58 +39,63 @@ Symbol6: Symbol7: .long 1 +.section assocSec, "dr", associative, "assocSym" +.globl Symbol8 +Symbol8: +.long 1 + // CHECK: Sections [ // CHECK: Section { -// CHECK: Number: 1 +// CHECK: Number: 4 // CHECK: Name: assocSec // CHECK: Characteristics [ // CHECK: IMAGE_SCN_LNK_COMDAT // CHECK: ] // CHECK: } // CHECK: Section { -// CHECK: Number: 2 +// CHECK: Number: 5 // CHECK: Name: secName // CHECK: Characteristics [ // CHECK: IMAGE_SCN_LNK_COMDAT // CHECK: ] // CHECK: } // CHECK: Section { -// CHECK: Number: 3 +// CHECK: Number: 6 // CHECK: Name: secName // CHECK: Characteristics [ // CHECK: IMAGE_SCN_LNK_COMDAT // CHECK: ] // CHECK: } // CHECK: Section { -// CHECK: Number: 4 +// CHECK: Number: 7 // CHECK: Name: SecName // CHECK: Characteristics [ // CHECK: IMAGE_SCN_LNK_COMDAT // CHECK: ] // CHECK: } // CHECK: Section { -// CHECK: Number: 5 +// CHECK: Number: 8 // CHECK: Name: SecName // CHECK: Characteristics [ // CHECK: IMAGE_SCN_LNK_COMDAT // CHECK: ] // CHECK: } // CHECK: Section { -// CHECK: Number: 6 +// CHECK: Number: 9 // CHECK: Name: SecName // CHECK: Characteristics [ // CHECK: IMAGE_SCN_LNK_COMDAT // CHECK: ] // CHECK: } // CHECK: Section { -// CHECK: Number: 7 +// CHECK: Number: 10 // CHECK: Name: SecName // CHECK: Characteristics [ // CHECK: IMAGE_SCN_LNK_COMDAT // CHECK: ] // CHECK: } // CHECK: Section { -// CHECK: Number: 8 +// CHECK: Number: 11 // CHECK: Name: SecName // CHECK: Characteristics [ // CHECK: IMAGE_SCN_LNK_COMDAT @@ -101,88 +105,104 @@ Symbol7: // CHECK: Symbols [ // CHECK: Symbol { // CHECK: Name: assocSec -// CHECK: Section: assocSec (1) +// CHECK: Section: assocSec (4) // CHECK: AuxSectionDef { // CHECK: Selection: Any // CHECK: } // CHECK: } // CHECK: Symbol { +// CHECK: Name: assocSym +// CHECK: Section: assocSec +// CHECK: } +// CHECK: Symbol { // CHECK: Name: secName -// CHECK: Section: secName (2) +// CHECK: Section: secName (5) // CHECK: AuxSectionDef { // CHECK: Selection: Any // CHECK: } // CHECK: } // CHECK: Symbol { +// CHECK: Name: Symbol1 +// CHECK: Section: secName (5) +// CHECK: } +// CHECK: Symbol { // CHECK: Name: secName -// CHECK: Section: secName (3) +// CHECK: Section: secName (6) // CHECK: AuxSectionDef { // CHECK: Selection: NoDuplicates // CHECK: } // CHECK: } // CHECK: Symbol { +// CHECK: Name: Symbol2 +// CHECK: Section: secName (6) +// CHECK: } +// CHECK: Symbol { // CHECK: Name: SecName -// CHECK: Section: SecName (4) +// CHECK: Section: SecName (7) // CHECK: AuxSectionDef { // CHECK: Selection: SameSize // CHECK: } // CHECK: } // CHECK: Symbol { +// CHECK: Name: Symbol3 +// CHECK: Section: SecName (7) +// CHECK: } +// CHECK: Symbol { // CHECK: Name: SecName -// CHECK: Section: SecName (5) +// CHECK: Section: SecName (8) // CHECK: AuxSymbolCount: 1 // CHECK: AuxSectionDef { // CHECK: Selection: ExactMatch // CHECK: } // CHECK: } // CHECK: Symbol { +// CHECK: Name: Symbol4 +// CHECK: Section: SecName (8) +// CHECK: } +// CHECK: Symbol { // CHECK: Name: SecName -// CHECK: Section: SecName (6) +// CHECK: Section: SecName (9) // CHECK: AuxSectionDef { // CHECK: Selection: Associative -// CHECK: AssocSection: assocSec (1) +// CHECK: AssocSection: assocSec (4) // CHECK: } // CHECK: } // CHECK: Symbol { // CHECK: Name: SecName -// CHECK: Section: SecName (7) +// CHECK: Section: SecName (10) // CHECK: AuxSectionDef { // CHECK: Selection: Largest // CHECK: } // CHECK: } // CHECK: Symbol { +// CHECK: Name: Symbol6 +// CHECK: Section: SecName (10) +// CHECK: } +// CHECK: Symbol { // CHECK: Name: SecName -// CHECK: Section: SecName (8) +// CHECK: Section: SecName (11) // CHECK: AuxSectionDef { // CHECK: Selection: Newest (0x7) // CHECK: } // CHECK: } // CHECK: Symbol { -// CHECK: Name: Symbol1 -// CHECK: Section: secName (2) -// CHECK: } -// CHECK: Symbol { -// CHECK: Name: Symbol2 -// CHECK: Section: secName (3) -// CHECK: } -// CHECK: Symbol { -// CHECK: Name: Symbol3 -// CHECK: Section: SecName (4) +// CHECK: Name: Symbol7 +// CHECK: Section: SecName (11) // CHECK: } // CHECK: Symbol { -// CHECK: Name: Symbol4 -// CHECK: Section: SecName (5) +// CHECK: Name: assocSec +// CHECK: Section: assocSec (12) +// CHECK: AuxSectionDef { +// CHECK: Selection: Associative (0x5) +// CHECK: AssocSection: assocSec (4) +// CHECK: } // CHECK: } // CHECK: Symbol { // CHECK: Name: Symbol5 -// CHECK: Section: SecName (6) +// CHECK: Section: SecName (9) // CHECK: } // CHECK: Symbol { -// CHECK: Name: Symbol6 -// CHECK: Section: SecName (7) -// CHECK: } -// CHECK: Symbol { -// CHECK: Name: Symbol7 -// CHECK: Section: SecName (8) +// CHECK: Name: Symbol8 +// CHECK: Section: assocSec (12) // CHECK: } // CHECK: ] diff --git a/test/MC/COFF/section-name-encoding.s b/test/MC/COFF/section-name-encoding.s index 74cd490..7edd6d7 100644 --- a/test/MC/COFF/section-name-encoding.s +++ b/test/MC/COFF/section-name-encoding.s @@ -10,11 +10,11 @@ // Raw encoding // CHECK: Section { -// CHECK: Number: 1 +// CHECK: Number: 4 // CHECK: Name: s (73 00 00 00 00 00 00 00) // CHECK: } // CHECK: Section { -// CHECK: Number: 2 +// CHECK: Number: 5 // CHECK: Name: s1234567 (73 31 32 33 34 35 36 37) // CHECK: } .section s; .long 1 @@ -25,7 +25,7 @@ // /4 // CHECK: Section { -// CHECK: Number: 3 +// CHECK: Number: 6 // CHECK: Name: s12345678 (2F 34 00 00 00 00 00 00) // CHECK: } .section s12345678; .long 1 @@ -57,7 +57,7 @@ pad_sections aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa // "s12345678\0" # of pad sections // // CHECK: Section { -// CHECK: Number: 9 +// CHECK: Number: 12 // CHECK: Name: seven_digit (2F 31 30 30 30 30 32 39) // CHECK: } .section seven_digit; .long 1 @@ -82,7 +82,7 @@ pad_sections_ex aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa // "2F 2F 41 41 6D 4A 61 34" is "//AAmJa4", which decodes to "0 0 38 9 26 56". // // CHECK: Section { -// CHECK: Number: 15 +// CHECK: Number: 18 // CHECK: Name: double_slash (2F 2F 41 41 6D 4A 61 34) // CHECK: } .section double_slash; .long 1 diff --git a/test/MC/COFF/seh-stackalloc-zero.s b/test/MC/COFF/seh-stackalloc-zero.s new file mode 100644 index 0000000..898ac84 --- /dev/null +++ b/test/MC/COFF/seh-stackalloc-zero.s @@ -0,0 +1,11 @@ +// RUN: not llvm-mc -triple x86_64-pc-win32 -filetype=obj %s -o %t.o 2>&1 | FileCheck %s + +// CHECK: Allocation size must be non-zero! + + .globl smallFunc + .def smallFunc; .scl 2; .type 32; .endef + .seh_proc smallFunc + .seh_stackalloc 0 +smallFunc: + ret + .seh_endproc diff --git a/test/MC/COFF/seh.s b/test/MC/COFF/seh.s index 72d42f4..cd884b4 100644 --- a/test/MC/COFF/seh.s +++ b/test/MC/COFF/seh.s @@ -35,13 +35,13 @@ // CHECK-NEXT: ] // CHECK-NEXT: Relocations [ -// CHECK-NEXT: Section (2) .xdata { +// CHECK-NEXT: Section (4) .xdata { // CHECK-NEXT: 0x14 IMAGE_REL_AMD64_ADDR32NB __C_specific_handler // CHECK-NEXT: 0x20 IMAGE_REL_AMD64_ADDR32NB func // CHECK-NEXT: 0x24 IMAGE_REL_AMD64_ADDR32NB func // CHECK-NEXT: 0x28 IMAGE_REL_AMD64_ADDR32NB .xdata // CHECK-NEXT: } -// CHECK-NEXT: Section (3) .pdata { +// CHECK-NEXT: Section (5) .pdata { // CHECK-NEXT: 0x0 IMAGE_REL_AMD64_ADDR32NB func // CHECK-NEXT: 0x4 IMAGE_REL_AMD64_ADDR32NB func // CHECK-NEXT: 0x8 IMAGE_REL_AMD64_ADDR32NB .xdata diff --git a/test/MC/COFF/symbol-fragment-offset-64.s b/test/MC/COFF/symbol-fragment-offset-64.s index b824470..deac888 100644 --- a/test/MC/COFF/symbol-fragment-offset-64.s +++ b/test/MC/COFF/symbol-fragment-offset-64.s @@ -36,10 +36,10 @@ _main: # @main // CHECK: { // CHECK: Machine: IMAGE_FILE_MACHINE_AMD64 -// CHECK: SectionCount: 2 +// CHECK: SectionCount: 3 // CHECK: TimeDateStamp: {{[0-9]+}} // CHECK: PointerToSymbolTable: 0x{{[0-9A-F]+}} -// CHECK: SymbolCount: 7 +// CHECK: SymbolCount: 9 // CHECK: OptionalHeaderSize: 0 // CHECK: Characteristics [ (0x0) // CHECK: ] diff --git a/test/MC/COFF/symbol-fragment-offset.s b/test/MC/COFF/symbol-fragment-offset.s index 71b1703..b09c5af 100644 --- a/test/MC/COFF/symbol-fragment-offset.s +++ b/test/MC/COFF/symbol-fragment-offset.s @@ -36,10 +36,10 @@ L_.str2: // CHECK: { // CHECK: Machine: IMAGE_FILE_MACHINE_I386 (0x14C) -// CHECK: SectionCount: 2 +// CHECK: SectionCount: 3 // CHECK: TimeDateStamp: {{[0-9]+}} // CHECK: PointerToSymbolTable: 0x{{[0-9A-F]+}} -// CHECK: SymbolCount: 7 +// CHECK: SymbolCount: 9 // CHECK: OptionalHeaderSize: 0 // CHECK: Characteristics [ (0x0) // CHECK: ] diff --git a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt index 397a39e..23da001 100644 --- a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -945,10 +945,15 @@ # CHECK: cset x9, pl # CHECK: csetm w20, ne # CHECK: csetm x30, ge +# "cset w2, nv" and "csetm x3, al" are invalid aliases for these two +# CHECK: csinc w2, wzr, wzr, al +# CHECK: csinv x3, xzr, xzr, nv 0xe3 0x17 0x9f 0x1a 0xe9 0x47 0x9f 0x9a 0xf4 0x3 0x9f 0x5a 0xfe 0xb3 0x9f 0xda +0xe2,0xe7,0x9f,0x1a +0xe3,0xf3,0x9f,0xda # CHECK: cinc w3, w5, gt # CHECK: cinc wzr, w4, le @@ -956,25 +961,35 @@ # CHECK: cinc x3, x5, gt # CHECK: cinc xzr, x4, le # CHECK: cset x9, lt +# "cinc w5, w6, al" and "cinc x1, x2, nv" are invalid aliases for these two +# CHECK: csinc w5, w6, w6, nv +# CHECK: csinc x1, x2, x2, al 0xa3 0xd4 0x85 0x1a 0x9f 0xc4 0x84 0x1a 0xe9 0xa7 0x9f 0x1a 0xa3 0xd4 0x85 0x9a 0x9f 0xc4 0x84 0x9a 0xe9 0xa7 0x9f 0x9a +0xc5,0xf4,0x86,0x1a +0x41,0xe4,0x82,0x9a # CHECK: cinv w3, w5, gt # CHECK: cinv wzr, w4, le -# CHECK: csetm w9, lt +# CHECK: csetm w9, lt # CHECK: cinv x3, x5, gt # CHECK: cinv xzr, x4, le -# CHECK: csetm x9, lt +# CHECK: csetm x9, lt +# "cinv x1, x0, nv" and "cinv w9, w8, al" are invalid aliases for these two +# CHECK: csinv x1, x0, x0, al +# CHECK: csinv w9, w8, w8, nv 0xa3 0xd0 0x85 0x5a 0x9f 0xc0 0x84 0x5a 0xe9 0xa3 0x9f 0x5a 0xa3 0xd0 0x85 0xda 0x9f 0xc0 0x84 0xda 0xe9 0xa3 0x9f 0xda +0x01 0xe0 0x80 0xda +0x09,0xf1,0x88,0x5a # CHECK: cneg w3, w5, gt # CHECK: cneg wzr, w4, le @@ -982,12 +997,17 @@ # CHECK: cneg x3, x5, gt # CHECK: cneg xzr, x4, le # CHECK: cneg x9, xzr, lt +# "cneg x4, x8, nv" and "cneg w5, w6, al" are invalid aliases for these two +# CHECK: csneg x4, x8, x8, al +# CHECK: csinv w9, w8, w8, nv 0xa3 0xd4 0x85 0x5a 0x9f 0xc4 0x84 0x5a 0xe9 0xa7 0x9f 0x5a 0xa3 0xd4 0x85 0xda 0x9f 0xc4 0x84 0xda 0xe9 0xa7 0x9f 0xda +0x04,0xe5,0x88,0xda +0x09,0xf1,0x88,0x5a #------------------------------------------------------------------------------ # Data-processing (1 source) diff --git a/test/MC/Disassembler/AArch64/lit.local.cfg b/test/MC/Disassembler/AArch64/lit.local.cfg index 2c423d1..180bb8a 100644 --- a/test/MC/Disassembler/AArch64/lit.local.cfg +++ b/test/MC/Disassembler/AArch64/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if 'AArch64' not in targets: +if 'AArch64' not in config.root.targets: config.unsupported = True diff --git a/test/MC/Disassembler/ARM/hex-immediates.txt b/test/MC/Disassembler/ARM/hex-immediates.txt index 2634d7e..875d667 100644 --- a/test/MC/Disassembler/ARM/hex-immediates.txt +++ b/test/MC/Disassembler/ARM/hex-immediates.txt @@ -1,5 +1,11 @@ -# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -hdis < %s | FileCheck %s +# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 --disassemble --print-imm-hex < %s | FileCheck %s # CHECK: ldr r4, [pc, #0x20] 0x08 0x4c # CHECK: sub sp, #0x84 0xa1 0xb0 +# CHECK: ldr r0, [sp, #0xb4] +0x2d 0x98 +# CHECK: str.w r8, [sp, #0xb4] +0xcd 0xf8 0xb4 0x80 +# CHECK: ldr.w r8, [sp, #0xb4] +0xdd 0xf8 0xb4 0x80 diff --git a/test/MC/Disassembler/ARM/lit.local.cfg b/test/MC/Disassembler/ARM/lit.local.cfg index 8a3ba96..98c6700 100644 --- a/test/MC/Disassembler/ARM/lit.local.cfg +++ b/test/MC/Disassembler/ARM/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'ARM' in targets: +if not 'ARM' in config.root.targets: config.unsupported = True diff --git a/test/MC/Disassembler/Mips/lit.local.cfg b/test/MC/Disassembler/Mips/lit.local.cfg index 1fa54b4..a3183a2 100644 --- a/test/MC/Disassembler/Mips/lit.local.cfg +++ b/test/MC/Disassembler/Mips/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'Mips' in targets: +if not 'Mips' in config.root.targets: config.unsupported = True diff --git a/test/MC/Disassembler/Mips/mips32r6.txt b/test/MC/Disassembler/Mips/mips32r6.txt index adbcd99..afef8ad 100644 --- a/test/MC/Disassembler/Mips/mips32r6.txt +++ b/test/MC/Disassembler/Mips/mips32r6.txt @@ -30,6 +30,8 @@ 0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, 0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 +0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 256 +0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256 @@ -40,44 +42,46 @@ 0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256 0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, +0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256 +0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 256 0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4 0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4 0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4 0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4 0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4 -0x46 0x84 0x18 0x80 # CHECK: cmp.f.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x80 # CHECK: cmp.f.d $f2, $f3, $f4 +0x46 0x84 0x18 0x80 # CHECK: cmp.af.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x80 # CHECK: cmp.af.d $f2, $f3, $f4 0x46 0x84 0x18 0x81 # CHECK: cmp.un.s $f2, $f3, $f4 0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4 0x46 0x84 0x18 0x82 # CHECK: cmp.eq.s $f2, $f3, $f4 0x46 0xa4 0x18 0x82 # CHECK: cmp.eq.d $f2, $f3, $f4 0x46 0x84 0x18 0x83 # CHECK: cmp.ueq.s $f2, $f3, $f4 0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x84 # CHECK: cmp.olt.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x84 # CHECK: cmp.olt.d $f2, $f3, $f4 +0x46 0x84 0x18 0x84 # CHECK: cmp.lt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x84 # CHECK: cmp.lt.d $f2, $f3, $f4 0x46 0x84 0x18 0x85 # CHECK: cmp.ult.s $f2, $f3, $f4 0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4 -0x46 0x84 0x18 0x86 # CHECK: cmp.ole.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x86 # CHECK: cmp.ole.d $f2, $f3, $f4 +0x46 0x84 0x18 0x86 # CHECK: cmp.le.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x86 # CHECK: cmp.le.d $f2, $f3, $f4 0x46 0x84 0x18 0x87 # CHECK: cmp.ule.s $f2, $f3, $f4 0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4 -0x46 0x84 0x18 0x88 # CHECK: cmp.sf.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x88 # CHECK: cmp.sf.d $f2, $f3, $f4 -0x46 0x84 0x18 0x89 # CHECK: cmp.ngle.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x89 # CHECK: cmp.ngle.d $f2, $f3, $f4 +0x46 0x84 0x18 0x88 # CHECK: cmp.saf.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4 +0x46 0x84 0x18 0x89 # CHECK: cmp.sun.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4 0x46 0x84 0x18 0x8a # CHECK: cmp.seq.s $f2, $f3, $f4 0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8b # CHECK: cmp.ngl.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8b # CHECK: cmp.ngl.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8c # CHECK: cmp.lt.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8c # CHECK: cmp.lt.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8d # CHECK: cmp.nge.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8d # CHECK: cmp.nge.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8e # CHECK: cmp.le.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8e # CHECK: cmp.le.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8f # CHECK: cmp.ngt.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8f # CHECK: cmp.ngt.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8b # CHECK: cmp.sueq.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8c # CHECK: cmp.slt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8d # CHECK: cmp.sult.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8e # CHECK: cmp.sle.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8f # CHECK: cmp.sule.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4 0x00 0x64 0x10 0x9a # CHECK: div $2, $3, $4 0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4 # 0xf8 0x05 0x01 0x00 # CHECK-TODO: jialc $5, 256 @@ -114,3 +118,10 @@ 0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4 0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4 0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4 +0x00 0x80 0x04 0x09 # CHECK: jr.hb $4 +0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 +0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 +0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18) +0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) +0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5 +0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp diff --git a/test/MC/Disassembler/Mips/mips64r6.txt b/test/MC/Disassembler/Mips/mips64r6.txt index f5bb14e..3ddef9ab 100644 --- a/test/MC/Disassembler/Mips/mips64r6.txt +++ b/test/MC/Disassembler/Mips/mips64r6.txt @@ -30,6 +30,8 @@ 0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256 0x60 0x02 0x01 0x4d # CHECK: bnezalc $2, 0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72256 +0x58 0x43 0x00 0x40 # CHECK: bgec $2, $3, 256 +0x18 0x43 0x00 0x40 # CHECK: bgeuc $2, $3, 256 0x18 0x42 0x01 0x4d # CHECK: bgezalc $2, 0xf8 0xa0 0x46 0x90 # CHECK: bnezc $5, 72256 0x5c 0xa5 0x00 0x40 # CHECK: bltzc $5, 256 @@ -40,44 +42,46 @@ 0x5c 0x05 0x00 0x40 # CHECK: bgtzc $5, 256 0x7c 0x02 0x20 0x20 # CHECK: bitswap $4, $2 0x18 0x02 0x01 0x4d # CHECK: blezalc $2, +0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256 +0x1c 0xa6 0x00 0x40 # CHECK: bltuc $5, $6, 256 0x60 0x00 0x00 0x01 # CHECK: bnvc $zero, $zero, 4 0x60 0x40 0x00 0x01 # CHECK: bnvc $2, $zero, 4 0x60 0x82 0x00 0x01 # CHECK: bnvc $4, $2, 4 0x20 0x00 0x00 0x01 # CHECK: bovc $zero, $zero, 4 0x20 0x40 0x00 0x01 # CHECK: bovc $2, $zero, 4 0x20 0x82 0x00 0x01 # CHECK: bovc $4, $2, 4 -0x46 0x84 0x18 0x80 # CHECK: cmp.f.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x80 # CHECK: cmp.f.d $f2, $f3, $f4 +0x46 0x84 0x18 0x80 # CHECK: cmp.af.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x80 # CHECK: cmp.af.d $f2, $f3, $f4 0x46 0x84 0x18 0x81 # CHECK: cmp.un.s $f2, $f3, $f4 0x46 0xa4 0x18 0x81 # CHECK: cmp.un.d $f2, $f3, $f4 0x46 0x84 0x18 0x82 # CHECK: cmp.eq.s $f2, $f3, $f4 0x46 0xa4 0x18 0x82 # CHECK: cmp.eq.d $f2, $f3, $f4 0x46 0x84 0x18 0x83 # CHECK: cmp.ueq.s $f2, $f3, $f4 0x46 0xa4 0x18 0x83 # CHECK: cmp.ueq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x84 # CHECK: cmp.olt.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x84 # CHECK: cmp.olt.d $f2, $f3, $f4 +0x46 0x84 0x18 0x84 # CHECK: cmp.lt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x84 # CHECK: cmp.lt.d $f2, $f3, $f4 0x46 0x84 0x18 0x85 # CHECK: cmp.ult.s $f2, $f3, $f4 0x46 0xa4 0x18 0x85 # CHECK: cmp.ult.d $f2, $f3, $f4 -0x46 0x84 0x18 0x86 # CHECK: cmp.ole.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x86 # CHECK: cmp.ole.d $f2, $f3, $f4 +0x46 0x84 0x18 0x86 # CHECK: cmp.le.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x86 # CHECK: cmp.le.d $f2, $f3, $f4 0x46 0x84 0x18 0x87 # CHECK: cmp.ule.s $f2, $f3, $f4 0x46 0xa4 0x18 0x87 # CHECK: cmp.ule.d $f2, $f3, $f4 -0x46 0x84 0x18 0x88 # CHECK: cmp.sf.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x88 # CHECK: cmp.sf.d $f2, $f3, $f4 -0x46 0x84 0x18 0x89 # CHECK: cmp.ngle.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x89 # CHECK: cmp.ngle.d $f2, $f3, $f4 +0x46 0x84 0x18 0x88 # CHECK: cmp.saf.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x88 # CHECK: cmp.saf.d $f2, $f3, $f4 +0x46 0x84 0x18 0x89 # CHECK: cmp.sun.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x89 # CHECK: cmp.sun.d $f2, $f3, $f4 0x46 0x84 0x18 0x8a # CHECK: cmp.seq.s $f2, $f3, $f4 0x46 0xa4 0x18 0x8a # CHECK: cmp.seq.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8b # CHECK: cmp.ngl.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8b # CHECK: cmp.ngl.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8c # CHECK: cmp.lt.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8c # CHECK: cmp.lt.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8d # CHECK: cmp.nge.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8d # CHECK: cmp.nge.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8e # CHECK: cmp.le.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8e # CHECK: cmp.le.d $f2, $f3, $f4 -0x46 0x84 0x18 0x8f # CHECK: cmp.ngt.s $f2, $f3, $f4 -0x46 0xa4 0x18 0x8f # CHECK: cmp.ngt.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8b # CHECK: cmp.sueq.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8b # CHECK: cmp.sueq.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8c # CHECK: cmp.slt.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8c # CHECK: cmp.slt.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8d # CHECK: cmp.sult.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8e # CHECK: cmp.sle.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4 +0x46 0x84 0x18 0x8f # CHECK: cmp.sule.s $f2, $f3, $f4 +0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4 0x7c 0x43 0x23 0x64 # CHECK: dalign $4, $2, $3, 5 0x74 0x62 0x12 0x34 # CHECK: daui $3, $2, 4660 0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136 @@ -99,10 +103,10 @@ 0x00 0x64 0x10 0xd8 # CHECK: muh $2, $3, $4 0x00 0x64 0x10 0x99 # CHECK: mulu $2, $3, $4 0x00 0x64 0x10 0xd9 # CHECK: muhu $2, $3, $4 -0x00 0x64 0x10 0xb8 # CHECK: dmul $2, $3, $4 -0x00 0x64 0x10 0xf8 # CHECK: dmuh $2, $3, $4 -0x00 0x64 0x10 0xb9 # CHECK: dmulu $2, $3, $4 -0x00 0x64 0x10 0xf9 # CHECK: dmuhu $2, $3, $4 +0x00 0x64 0x10 0x9c # CHECK: dmul $2, $3, $4 +0x00 0x64 0x10 0xdc # CHECK: dmuh $2, $3, $4 +0x00 0x64 0x10 0x9d # CHECK: dmulu $2, $3, $4 +0x00 0x64 0x10 0xdd # CHECK: dmuhu $2, $3, $4 0x46 0x04 0x18 0x98 # CHECK: maddf.s $f2, $f3, $f4 0x46 0x24 0x18 0x98 # CHECK: maddf.d $f2, $f3, $f4 0x46 0x04 0x18 0x99 # CHECK: msubf.s $f2, $f3, $f4 @@ -127,3 +131,15 @@ 0x46 0x20 0x20 0x9a # CHECK: rint.d $f2, $f4 0x46 0x00 0x20 0x9b # CHECK: class.s $f2, $f4 0x46 0x20 0x20 0x9b # CHECK: class.d $f2, $f4 +0xec 0x58 0x3c 0x48 # CHECK: ldpc $2, 123456 +0x00 0x80 0x04 0x09 # CHECK: jr.hb $4 +0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4 +0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 +0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18) +0x7f 0xe0 0x38 0x37 # CHECK: lld $zero, 112($ra) +0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) +0x7f 0xaf 0xe6 0xa7 # CHECK: scd $15, -51($sp) +0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5 +0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp +0x00 0xc0 0x90 0x53 # CHECK: dclo $18, $6 +0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25 diff --git a/test/MC/Disassembler/PowerPC/lit.local.cfg b/test/MC/Disassembler/PowerPC/lit.local.cfg index 2e46300..5d33887 100644 --- a/test/MC/Disassembler/PowerPC/lit.local.cfg +++ b/test/MC/Disassembler/PowerPC/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'PowerPC' in targets: +if not 'PowerPC' in config.root.targets: config.unsupported = True diff --git a/test/MC/Disassembler/Sparc/lit.local.cfg b/test/MC/Disassembler/Sparc/lit.local.cfg index 4d344fa..fa6a54e 100644 --- a/test/MC/Disassembler/Sparc/lit.local.cfg +++ b/test/MC/Disassembler/Sparc/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'Sparc' in targets: +if not 'Sparc' in config.root.targets: config.unsupported = True diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt index 1a5634d..54a3c5b 100644 --- a/test/MC/Disassembler/SystemZ/insns.txt +++ b/test/MC/Disassembler/SystemZ/insns.txt @@ -3355,6 +3355,24 @@ # CHECK: ldxbr %f13, %f13 0xb3 0x45 0x00 0xdd +# CHECK: ldxbra %f0, 0, %f0, 1 +0xb3 0x45 0x01 0x00 + +# CHECK: ldxbra %f0, 0, %f0, 15 +0xb3 0x45 0x0f 0x00 + +# CHECK: ldxbra %f0, 0, %f13, 1 +0xb3 0x45 0x01 0x0d + +# CHECK: ldxbra %f0, 15, %f0, 1 +0xb3 0x45 0xf1 0x00 + +# CHECK: ldxbra %f4, 5, %f8, 9 +0xb3 0x45 0x59 0x48 + +# CHECK: ldxbra %f13, 0, %f0, 1 +0xb3 0x45 0x01 0xd0 + # CHECK: ldy %f0, -524288 0xed 0x00 0x00 0x00 0x80 0x65 @@ -3400,6 +3418,24 @@ # CHECK: ledbr %f15, %f15 0xb3 0x44 0x00 0xff +# CHECK: ledbra %f0, 0, %f0, 1 +0xb3 0x44 0x01 0x00 + +# CHECK: ledbra %f0, 0, %f0, 15 +0xb3 0x44 0x0f 0x00 + +# CHECK: ledbra %f0, 0, %f15, 1 +0xb3 0x44 0x01 0x0f + +# CHECK: ledbra %f0, 15, %f0, 1 +0xb3 0x44 0xf1 0x00 + +# CHECK: ledbra %f4, 5, %f6, 7 +0xb3 0x44 0x57 0x46 + +# CHECK: ledbra %f15, 0, %f0, 1 +0xb3 0x44 0x01 0xf0 + # CHECK: ler %f0, %f9 0x38 0x09 @@ -3448,6 +3484,24 @@ # CHECK: lexbr %f13, %f13 0xb3 0x46 0x00 0xdd +# CHECK: lexbra %f0, 0, %f0, 1 +0xb3 0x46 0x01 0x00 + +# CHECK: lexbra %f0, 0, %f0, 15 +0xb3 0x46 0x0f 0x00 + +# CHECK: lexbra %f0, 0, %f13, 1 +0xb3 0x46 0x01 0x0d + +# CHECK: lexbra %f0, 15, %f0, 1 +0xb3 0x46 0xf1 0x00 + +# CHECK: lexbra %f4, 5, %f8, 9 +0xb3 0x46 0x59 0x48 + +# CHECK: lexbra %f13, 0, %f0, 1 +0xb3 0x46 0x01 0xd0 + # CHECK: ley %f0, -524288 0xed 0x00 0x00 0x00 0x80 0x64 diff --git a/test/MC/Disassembler/SystemZ/lit.local.cfg b/test/MC/Disassembler/SystemZ/lit.local.cfg index b12af09..5c02dd3 100644 --- a/test/MC/Disassembler/SystemZ/lit.local.cfg +++ b/test/MC/Disassembler/SystemZ/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'SystemZ' in targets: +if not 'SystemZ' in config.root.targets: config.unsupported = True diff --git a/test/MC/Disassembler/X86/avx-512.txt b/test/MC/Disassembler/X86/avx-512.txt index e5ad2a9..b1a8aaf 100644 --- a/test/MC/Disassembler/X86/avx-512.txt +++ b/test/MC/Disassembler/X86/avx-512.txt @@ -39,6 +39,12 @@ # CHECK: vgatherdpd (%rsi,%ymm0,4), %zmm1 {%k2} 0x62 0xf2 0xfd 0x4a 0x92 0x0c 0x86 +# CHECK: vpslld $16, %zmm21, %zmm22 +0x62 0xb1 0x4d 0x40 0x72 0xf5 0x10 + +# CHECK: vpord %zmm22, %zmm21, %zmm23 +0x62 0xa1 0x55 0x40 0xeb 0xfe + ##################################################### # MASK INSTRUCTIONS # ##################################################### diff --git a/test/MC/Disassembler/X86/hex-immediates.txt b/test/MC/Disassembler/X86/hex-immediates.txt index 80d2448..fb76c26 100644 --- a/test/MC/Disassembler/X86/hex-immediates.txt +++ b/test/MC/Disassembler/X86/hex-immediates.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --hdis %s -triple=x86_64-apple-darwin9 2>&1 | FileCheck %s +# RUN: llvm-mc --print-imm-hex --disassemble %s -triple=x86_64-apple-darwin9 2>&1 | FileCheck %s # CHECK: movabsq $0x7fffffffffffffff, %rcx 0x48 0xb9 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x7f diff --git a/test/MC/Disassembler/X86/lit.local.cfg b/test/MC/Disassembler/X86/lit.local.cfg index ba763cf..e71f3cc 100644 --- a/test/MC/Disassembler/X86/lit.local.cfg +++ b/test/MC/Disassembler/X86/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True diff --git a/test/MC/Disassembler/X86/moffs.txt b/test/MC/Disassembler/X86/moffs.txt index 67d64e8..dd2664c 100644 --- a/test/MC/Disassembler/X86/moffs.txt +++ b/test/MC/Disassembler/X86/moffs.txt @@ -1,6 +1,6 @@ -# RUN: llvm-mc --hdis %s -triple=i686-linux-gnu-code16 | FileCheck --check-prefix=16 %s -# RUN: llvm-mc --hdis %s -triple=i686-linux-gnu | FileCheck --check-prefix=32 %s -# RUN: llvm-mc --hdis %s -triple=x86_64-linux-gnu | FileCheck --check-prefix=64 %s +# RUN: llvm-mc --disassemble --print-imm-hex %s -triple=i686-linux-gnu-code16 | FileCheck --check-prefix=16 %s +# RUN: llvm-mc --disassemble --print-imm-hex %s -triple=i686-linux-gnu | FileCheck --check-prefix=32 %s +# RUN: llvm-mc --disassemble --print-imm-hex %s -triple=x86_64-linux-gnu | FileCheck --check-prefix=64 %s # 16: movb 0x5a5a, %al # 32: movb 0x5a5a5a5a, %al diff --git a/test/MC/Disassembler/XCore/lit.local.cfg b/test/MC/Disassembler/XCore/lit.local.cfg index 4d17d46..bb48713 100644 --- a/test/MC/Disassembler/XCore/lit.local.cfg +++ b/test/MC/Disassembler/XCore/lit.local.cfg @@ -1,3 +1,2 @@ -targets = set(config.root.targets_to_build.split()) -if not 'XCore' in targets: +if not 'XCore' in config.root.targets: config.unsupported = True diff --git a/test/MC/ELF/ARM/bss-non-zero-value.s b/test/MC/ELF/ARM/bss-non-zero-value.s new file mode 100644 index 0000000..999b8b0 --- /dev/null +++ b/test/MC/ELF/ARM/bss-non-zero-value.s @@ -0,0 +1,9 @@ +// RUN: not llvm-mc -filetype=obj -triple arm-linux-gnu %s -o %t 2>%t.out +// RUN: FileCheck --input-file=%t.out %s +// CHECK: non-zero initializer found in section '.bss' + .bss + .globl a + .align 2 +a: + .long 1 + .size a, 4 diff --git a/test/MC/ELF/ARM/gnu-type-hash-diagnostics.s b/test/MC/ELF/ARM/gnu-type-hash-diagnostics.s new file mode 100644 index 0000000..eb36475 --- /dev/null +++ b/test/MC/ELF/ARM/gnu-type-hash-diagnostics.s @@ -0,0 +1,9 @@ +@ RUN: not llvm-mc -triple arm-elf -filetype asm -o /dev/null %s 2>&1 | FileCheck %s + + .syntax unified + + .type TYPE #32 +// CHECK: error: expected symbol type in directive +// CHECK: .type TYPE #32 +// CHECK: ^ + diff --git a/test/MC/ELF/ARM/gnu-type-hash.s b/test/MC/ELF/ARM/gnu-type-hash.s new file mode 100644 index 0000000..ae5c47c --- /dev/null +++ b/test/MC/ELF/ARM/gnu-type-hash.s @@ -0,0 +1,16 @@ +@ RUN: llvm-mc -triple arm-elf -filetype asm -o - %s | FileCheck %s + + .syntax unified + + .type TYPE #STT_FUNC +// CHECK: .type TYPE,%function + + .type type #function +// CHECK: .type type,%function + + .type comma_TYPE, #STT_FUNC +// CHECK: .type comma_TYPE,%function + + .type comma_type, #function +// CHECK: .type comma_type,%function + diff --git a/test/MC/ELF/ARM/lit.local.cfg b/test/MC/ELF/ARM/lit.local.cfg new file mode 100644 index 0000000..d825cc0 --- /dev/null +++ b/test/MC/ELF/ARM/lit.local.cfg @@ -0,0 +1,3 @@ +# We have to reset config.unsupported here because the parent directory is +# predicated on 'X86'. +config.unsupported = not 'ARM' in config.root.targets diff --git a/test/MC/ELF/cfi-adjust-cfa-offset.s b/test/MC/ELF/cfi-adjust-cfa-offset.s index b3768cb..9d639f7 100644 --- a/test/MC/ELF/cfi-adjust-cfa-offset.s +++ b/test/MC/ELF/cfi-adjust-cfa-offset.s @@ -28,7 +28,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 1C000000 1C000000 // CHECK-NEXT: 0020: 00000000 0A000000 00440E10 410E1444 // CHECK-NEXT: 0030: 0E080000 00000000 diff --git a/test/MC/ELF/cfi-advance-loc2.s b/test/MC/ELF/cfi-advance-loc2.s index d7a53c4..98caa01 100644 --- a/test/MC/ELF/cfi-advance-loc2.s +++ b/test/MC/ELF/cfi-advance-loc2.s @@ -26,7 +26,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 // CHECK-NEXT: 0020: 00000000 01010000 00030001 0E080000 // CHECK-NEXT: ) diff --git a/test/MC/ELF/cfi-def-cfa-offset.s b/test/MC/ELF/cfi-def-cfa-offset.s index eac2c73..59f7400 100644 --- a/test/MC/ELF/cfi-def-cfa-offset.s +++ b/test/MC/ELF/cfi-def-cfa-offset.s @@ -27,7 +27,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 // CHECK-NEXT: 0020: 00000000 0A000000 00440E10 450E0800 // CHECK-NEXT: ) diff --git a/test/MC/ELF/cfi-def-cfa-register.s b/test/MC/ELF/cfi-def-cfa-register.s index 00d8b99..178ba32 100644 --- a/test/MC/ELF/cfi-def-cfa-register.s +++ b/test/MC/ELF/cfi-def-cfa-register.s @@ -23,7 +23,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 // CHECK-NEXT: 0020: 00000000 02000000 00410D06 00000000 // CHECK-NEXT: ) diff --git a/test/MC/ELF/cfi-def-cfa.s b/test/MC/ELF/cfi-def-cfa.s index 36e147f..dfb0d4b 100644 --- a/test/MC/ELF/cfi-def-cfa.s +++ b/test/MC/ELF/cfi-def-cfa.s @@ -23,7 +23,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 // CHECK-NEXT: 0020: 00000000 02000000 00410C07 08000000 // CHECK-NEXT: ) diff --git a/test/MC/ELF/cfi-escape.s b/test/MC/ELF/cfi-escape.s index 839d671..5394ee4 100644 --- a/test/MC/ELF/cfi-escape.s +++ b/test/MC/ELF/cfi-escape.s @@ -24,7 +24,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 // CHECK-NEXT: 0020: 00000000 02000000 00411507 7F000000 // CHECK-NEXT: ) diff --git a/test/MC/ELF/cfi-offset.s b/test/MC/ELF/cfi-offset.s index 951a600..a65b4fc 100644 --- a/test/MC/ELF/cfi-offset.s +++ b/test/MC/ELF/cfi-offset.s @@ -23,7 +23,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 // CHECK-NEXT: 0020: 00000000 02000000 00418602 00000000 // CHECK-NEXT: ) diff --git a/test/MC/ELF/cfi-register.s b/test/MC/ELF/cfi-register.s index 4abbb53..9441770 100644 --- a/test/MC/ELF/cfi-register.s +++ b/test/MC/ELF/cfi-register.s @@ -24,7 +24,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 // CHECK-NEXT: 0020: 00000000 02000000 00410906 00000000 // CHECK-NEXT: ) diff --git a/test/MC/ELF/cfi-rel-offset.s b/test/MC/ELF/cfi-rel-offset.s index 34254c8..0dc69c8 100644 --- a/test/MC/ELF/cfi-rel-offset.s +++ b/test/MC/ELF/cfi-rel-offset.s @@ -31,7 +31,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 24000000 1C000000 // CHECK-NEXT: 0020: 00000000 05000000 00410E08 410D0641 // CHECK-NEXT: 0030: 11067F41 0E104186 02000000 00000000 diff --git a/test/MC/ELF/cfi-rel-offset2.s b/test/MC/ELF/cfi-rel-offset2.s index 3de769f..360e7b0 100644 --- a/test/MC/ELF/cfi-rel-offset2.s +++ b/test/MC/ELF/cfi-rel-offset2.s @@ -23,7 +23,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 // CHECK-NEXT: 0020: 00000000 01000000 00411106 7F000000 // CHECK-NEXT: ) diff --git a/test/MC/ELF/cfi-remember.s b/test/MC/ELF/cfi-remember.s index 98c759d..3a38948 100644 --- a/test/MC/ELF/cfi-remember.s +++ b/test/MC/ELF/cfi-remember.s @@ -26,7 +26,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 // CHECK-NEXT: 0020: 00000000 03000000 00410A41 0B000000 // CHECK-NEXT: ) diff --git a/test/MC/ELF/cfi-restore.s b/test/MC/ELF/cfi-restore.s index d25b5ff..e225797 100644 --- a/test/MC/ELF/cfi-restore.s +++ b/test/MC/ELF/cfi-restore.s @@ -24,7 +24,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 // CHECK-NEXT: 0020: 00000000 02000000 0041C600 00000000 // CHECK-NEXT: ) diff --git a/test/MC/ELF/cfi-same-value.s b/test/MC/ELF/cfi-same-value.s index 9f5ae4b..2d37f4d 100644 --- a/test/MC/ELF/cfi-same-value.s +++ b/test/MC/ELF/cfi-same-value.s @@ -24,7 +24,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 // CHECK-NEXT: 0020: 00000000 02000000 00410806 00000000 // CHECK-NEXT: ) diff --git a/test/MC/ELF/cfi-sections.s b/test/MC/ELF/cfi-sections.s index 15a79e5..b0ba543 100644 --- a/test/MC/ELF/cfi-sections.s +++ b/test/MC/ELF/cfi-sections.s @@ -26,7 +26,7 @@ f2: // ELF_64-NEXT: AddressAlignment: 8 // ELF_64-NEXT: EntrySize: 0 // ELF_64-NEXT: SectionData ( -// ELF_64-NEXT: 0000: 14000000 FFFFFFFF 01000178 100C0708 +// ELF_64-NEXT: 0000: 14000000 FFFFFFFF 03000178 100C0708 // ELF_64-NEXT: 0010: 90010000 00000000 14000000 00000000 // ELF_64-NEXT: 0020: 00000000 00000000 01000000 00000000 // ELF_64-NEXT: 0030: 14000000 00000000 00000000 00000000 @@ -47,7 +47,7 @@ f2: // ELF_32-NEXT: AddressAlignment: 4 // ELF_32-NEXT: EntrySize: 0 // ELF_32-NEXT: SectionData ( -// ELF_32-NEXT: 0000: 10000000 FFFFFFFF 0100017C 080C0404 +// ELF_32-NEXT: 0000: 10000000 FFFFFFFF 0300017C 080C0404 // ELF_32-NEXT: 0010: 88010000 0C000000 00000000 00000000 // ELF_32-NEXT: 0020: 01000000 0C000000 00000000 01000000 // ELF_32-NEXT: 0030: 01000000 diff --git a/test/MC/ELF/cfi-signal-frame.s b/test/MC/ELF/cfi-signal-frame.s index 0233119..98deb0a 100644 --- a/test/MC/ELF/cfi-signal-frame.s +++ b/test/MC/ELF/cfi-signal-frame.s @@ -23,10 +23,10 @@ g: // CHECK-NEXT: AddressAlignment: 8 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5253 00017810 +// CHECK-NEXT: 0000: 14000000 00000000 037A5253 00017810 // CHECK-NEXT: 0010: 011B0C07 08900100 10000000 1C000000 // CHECK-NEXT: 0020: 00000000 00000000 00000000 14000000 -// CHECK-NEXT: 0030: 00000000 017A5200 01781001 1B0C0708 +// CHECK-NEXT: 0030: 00000000 037A5200 01781001 1B0C0708 // CHECK-NEXT: 0040: 90010000 10000000 1C000000 00000000 // CHECK-NEXT: 0050: 00000000 00000000 // CHECK-NEXT: ) diff --git a/test/MC/ELF/cfi-undefined.s b/test/MC/ELF/cfi-undefined.s index 9773a36..568b315 100644 --- a/test/MC/ELF/cfi-undefined.s +++ b/test/MC/ELF/cfi-undefined.s @@ -24,7 +24,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 // CHECK-NEXT: 0020: 00000000 02000000 00410706 00000000 // CHECK-NEXT: ) diff --git a/test/MC/ELF/cfi-version.ll b/test/MC/ELF/cfi-version.ll new file mode 100644 index 0000000..10daa1d --- /dev/null +++ b/test/MC/ELF/cfi-version.ll @@ -0,0 +1,45 @@ +; RUN: %llc_dwarf %s -o - -dwarf-version 2 -filetype=obj | llvm-dwarfdump - | FileCheck %s --check-prefix=DWARF2 +; RUN: %llc_dwarf %s -o - -dwarf-version 3 -filetype=obj | llvm-dwarfdump - | FileCheck %s --check-prefix=DWARF34 +; RUN: %llc_dwarf %s -o - -dwarf-version 4 -filetype=obj | llvm-dwarfdump - | FileCheck %s --check-prefix=DWARF34 + +; .debug_frame is not emitted for targeting Windows x64. +; REQUIRES: debug_frame + +; Function Attrs: nounwind +define i32 @foo() #0 { +entry: + %call = call i32 bitcast (i32 (...)* @bar to i32 ()*)(), !dbg !12 + %add = add nsw i32 %call, 1, !dbg !12 + ret i32 %add, !dbg !12 +} + +declare i32 @bar(...) #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!9, !10} +!llvm.ident = !{!11} + +!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.5.0 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !"", i32 1} ; [ DW_TAG_compile_unit ] [/tmp/test.c] [DW_LANG_C99] +!1 = metadata !{metadata !"test.c", metadata !"/tmp"} +!2 = metadata !{} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"foo", metadata !"foo", metadata !"", i32 2, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @foo, null, null, metadata !2, i32 2} ; [ DW_TAG_subprogram ] [line 2] [def] [foo] +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [/tmp/test.c] +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = metadata !{metadata !8} +!8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!9 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} +!10 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} +!11 = metadata !{metadata !"clang version 3.5.0 "} +!12 = metadata !{i32 2, i32 0, metadata !4, null} + +; DWARF2: .debug_frame contents: +; DWARF2: Version: 1 +; DWARF2-NEXT: Augmentation: + +; DWARF34: .debug_frame contents: +; DWARF34: Version: 3 +; DWARF34-NEXT: Augmentation: diff --git a/test/MC/ELF/cfi-window-save.s b/test/MC/ELF/cfi-window-save.s index c7d438a..b083901 100644 --- a/test/MC/ELF/cfi-window-save.s +++ b/test/MC/ELF/cfi-window-save.s @@ -26,7 +26,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 // CHECK-NEXT: 0020: 00000000 02000000 00412D00 00000000 // CHECK-NEXT: ) diff --git a/test/MC/ELF/cfi-zero-addr-delta.s b/test/MC/ELF/cfi-zero-addr-delta.s index 05cb0ae..8662839 100644 --- a/test/MC/ELF/cfi-zero-addr-delta.s +++ b/test/MC/ELF/cfi-zero-addr-delta.s @@ -30,7 +30,7 @@ f: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0000: 14000000 00000000 037A5200 01781001 // CHECK-NEXT: 0010: 1B0C0708 90010000 1C000000 1C000000 // CHECK-NEXT: 0020: 00000000 04000000 00410E10 410A0E08 // CHECK-NEXT: 0030: 410B0000 00000000 diff --git a/test/MC/ELF/cfi.s b/test/MC/ELF/cfi.s index fd229b6..21be615 100644 --- a/test/MC/ELF/cfi.s +++ b/test/MC/ELF/cfi.s @@ -234,116 +234,116 @@ f37: // CHECK-NEXT: Relocations [ // CHECK-NEXT: ] // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 14000000 00000000 017A4C52 00017810 +// CHECK-NEXT: 0000: 14000000 00000000 037A4C52 00017810 // CHECK-NEXT: 0010: 02031B0C 07089001 14000000 1C000000 // CHECK-NEXT: 0020: 00000000 01000000 04000000 00000000 -// CHECK-NEXT: 0030: 20000000 00000000 017A504C 52000178 +// CHECK-NEXT: 0030: 20000000 00000000 037A504C 52000178 // CHECK-NEXT: 0040: 100B0000 00000000 00000003 1B0C0708 // CHECK-NEXT: 0050: 90010000 14000000 28000000 00000000 // CHECK-NEXT: 0060: 01000000 04000000 00000000 14000000 // CHECK-NEXT: 0070: 70000000 00000000 01000000 04000000 -// CHECK-NEXT: 0080: 00000000 20000000 00000000 017A504C +// CHECK-NEXT: 0080: 00000000 20000000 00000000 037A504C // CHECK-NEXT: 0090: 52000178 100B0000 00000000 00000002 // CHECK-NEXT: 00A0: 1B0C0708 90010000 10000000 28000000 // CHECK-NEXT: 00B0: 00000000 01000000 02000000 18000000 -// CHECK-NEXT: 00C0: 00000000 017A5052 00017810 04020000 +// CHECK-NEXT: 00C0: 00000000 037A5052 00017810 04020000 // CHECK-NEXT: 00D0: 1B0C0708 90010000 10000000 20000000 // CHECK-NEXT: 00E0: 00000000 01000000 00000000 18000000 -// CHECK-NEXT: 00F0: 00000000 017A5052 00017810 06030000 +// CHECK-NEXT: 00F0: 00000000 037A5052 00017810 06030000 // CHECK-NEXT: 0100: 00001B0C 07089001 10000000 20000000 // CHECK-NEXT: 0110: 00000000 01000000 00000000 1C000000 -// CHECK-NEXT: 0120: 00000000 017A5052 00017810 0A040000 +// CHECK-NEXT: 0120: 00000000 037A5052 00017810 0A040000 // CHECK-NEXT: 0130: 00000000 00001B0C 07089001 10000000 // CHECK-NEXT: 0140: 24000000 00000000 01000000 00000000 -// CHECK-NEXT: 0150: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0150: 18000000 00000000 037A5052 00017810 // CHECK-NEXT: 0160: 040A0000 1B0C0708 90010000 10000000 // CHECK-NEXT: 0170: 20000000 00000000 01000000 00000000 -// CHECK-NEXT: 0180: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0180: 18000000 00000000 037A5052 00017810 // CHECK-NEXT: 0190: 060B0000 00001B0C 07089001 10000000 // CHECK-NEXT: 01A0: 20000000 00000000 01000000 00000000 -// CHECK-NEXT: 01B0: 1C000000 00000000 017A5052 00017810 +// CHECK-NEXT: 01B0: 1C000000 00000000 037A5052 00017810 // CHECK-NEXT: 01C0: 0A0C0000 00000000 00001B0C 07089001 // CHECK-NEXT: 01D0: 10000000 24000000 00000000 01000000 -// CHECK-NEXT: 01E0: 00000000 1C000000 00000000 017A5052 +// CHECK-NEXT: 01E0: 00000000 1C000000 00000000 037A5052 // CHECK-NEXT: 01F0: 00017810 0A080000 00000000 00001B0C // CHECK-NEXT: 0200: 07089001 10000000 24000000 00000000 // CHECK-NEXT: 0210: 01000000 00000000 1C000000 00000000 -// CHECK-NEXT: 0220: 017A5052 00017810 0A100000 00000000 +// CHECK-NEXT: 0220: 037A5052 00017810 0A100000 00000000 // CHECK-NEXT: 0230: 00001B0C 07089001 10000000 24000000 // CHECK-NEXT: 0240: 00000000 01000000 00000000 18000000 -// CHECK-NEXT: 0250: 00000000 017A5052 00017810 04120000 +// CHECK-NEXT: 0250: 00000000 037A5052 00017810 04120000 // CHECK-NEXT: 0260: 1B0C0708 90010000 10000000 20000000 // CHECK-NEXT: 0270: 00000000 01000000 00000000 18000000 -// CHECK-NEXT: 0280: 00000000 017A5052 00017810 06130000 +// CHECK-NEXT: 0280: 00000000 037A5052 00017810 06130000 // CHECK-NEXT: 0290: 00001B0C 07089001 10000000 20000000 // CHECK-NEXT: 02A0: 00000000 01000000 00000000 1C000000 -// CHECK-NEXT: 02B0: 00000000 017A5052 00017810 0A140000 +// CHECK-NEXT: 02B0: 00000000 037A5052 00017810 0A140000 // CHECK-NEXT: 02C0: 00000000 00001B0C 07089001 10000000 // CHECK-NEXT: 02D0: 24000000 00000000 01000000 00000000 -// CHECK-NEXT: 02E0: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 02E0: 18000000 00000000 037A5052 00017810 // CHECK-NEXT: 02F0: 041A0000 1B0C0708 90010000 10000000 // CHECK-NEXT: 0300: 20000000 00000000 01000000 00000000 -// CHECK-NEXT: 0310: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0310: 18000000 00000000 037A5052 00017810 // CHECK-NEXT: 0320: 061B0000 00001B0C 07089001 10000000 // CHECK-NEXT: 0330: 20000000 00000000 01000000 00000000 -// CHECK-NEXT: 0340: 1C000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0340: 1C000000 00000000 037A5052 00017810 // CHECK-NEXT: 0350: 0A1C0000 00000000 00001B0C 07089001 // CHECK-NEXT: 0360: 10000000 24000000 00000000 01000000 -// CHECK-NEXT: 0370: 00000000 1C000000 00000000 017A5052 +// CHECK-NEXT: 0370: 00000000 1C000000 00000000 037A5052 // CHECK-NEXT: 0380: 00017810 0A180000 00000000 00001B0C // CHECK-NEXT: 0390: 07089001 10000000 24000000 00000000 // CHECK-NEXT: 03A0: 01000000 00000000 1C000000 00000000 -// CHECK-NEXT: 03B0: 017A5052 00017810 0A800000 00000000 +// CHECK-NEXT: 03B0: 037A5052 00017810 0A800000 00000000 // CHECK-NEXT: 03C0: 00001B0C 07089001 10000000 24000000 // CHECK-NEXT: 03D0: 00000000 01000000 00000000 18000000 -// CHECK-NEXT: 03E0: 00000000 017A5052 00017810 04820000 +// CHECK-NEXT: 03E0: 00000000 037A5052 00017810 04820000 // CHECK-NEXT: 03F0: 1B0C0708 90010000 10000000 20000000 // CHECK-NEXT: 0400: 00000000 01000000 00000000 18000000 -// CHECK-NEXT: 0410: 00000000 017A5052 00017810 06830000 +// CHECK-NEXT: 0410: 00000000 037A5052 00017810 06830000 // CHECK-NEXT: 0420: 00001B0C 07089001 10000000 20000000 // CHECK-NEXT: 0430: 00000000 01000000 00000000 1C000000 -// CHECK-NEXT: 0440: 00000000 017A5052 00017810 0A840000 +// CHECK-NEXT: 0440: 00000000 037A5052 00017810 0A840000 // CHECK-NEXT: 0450: 00000000 00001B0C 07089001 10000000 // CHECK-NEXT: 0460: 24000000 00000000 01000000 00000000 -// CHECK-NEXT: 0470: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0470: 18000000 00000000 037A5052 00017810 // CHECK-NEXT: 0480: 048A0000 1B0C0708 90010000 10000000 // CHECK-NEXT: 0490: 20000000 00000000 01000000 00000000 -// CHECK-NEXT: 04A0: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 04A0: 18000000 00000000 037A5052 00017810 // CHECK-NEXT: 04B0: 068B0000 00001B0C 07089001 10000000 // CHECK-NEXT: 04C0: 20000000 00000000 01000000 00000000 -// CHECK-NEXT: 04D0: 1C000000 00000000 017A5052 00017810 +// CHECK-NEXT: 04D0: 1C000000 00000000 037A5052 00017810 // CHECK-NEXT: 04E0: 0A8C0000 00000000 00001B0C 07089001 // CHECK-NEXT: 04F0: 10000000 24000000 00000000 01000000 -// CHECK-NEXT: 0500: 00000000 1C000000 00000000 017A5052 +// CHECK-NEXT: 0500: 00000000 1C000000 00000000 037A5052 // CHECK-NEXT: 0510: 00017810 0A880000 00000000 00001B0C // CHECK-NEXT: 0520: 07089001 10000000 24000000 00000000 // CHECK-NEXT: 0530: 01000000 00000000 1C000000 00000000 -// CHECK-NEXT: 0540: 017A5052 00017810 0A900000 00000000 +// CHECK-NEXT: 0540: 037A5052 00017810 0A900000 00000000 // CHECK-NEXT: 0550: 00001B0C 07089001 10000000 24000000 // CHECK-NEXT: 0560: 00000000 01000000 00000000 18000000 -// CHECK-NEXT: 0570: 00000000 017A5052 00017810 04920000 +// CHECK-NEXT: 0570: 00000000 037A5052 00017810 04920000 // CHECK-NEXT: 0580: 1B0C0708 90010000 10000000 20000000 // CHECK-NEXT: 0590: 00000000 01000000 00000000 18000000 -// CHECK-NEXT: 05A0: 00000000 017A5052 00017810 06930000 +// CHECK-NEXT: 05A0: 00000000 037A5052 00017810 06930000 // CHECK-NEXT: 05B0: 00001B0C 07089001 10000000 20000000 // CHECK-NEXT: 05C0: 00000000 01000000 00000000 1C000000 -// CHECK-NEXT: 05D0: 00000000 017A5052 00017810 0A940000 +// CHECK-NEXT: 05D0: 00000000 037A5052 00017810 0A940000 // CHECK-NEXT: 05E0: 00000000 00001B0C 07089001 10000000 // CHECK-NEXT: 05F0: 24000000 00000000 01000000 00000000 -// CHECK-NEXT: 0600: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0600: 18000000 00000000 037A5052 00017810 // CHECK-NEXT: 0610: 049A0000 1B0C0708 90010000 10000000 // CHECK-NEXT: 0620: 20000000 00000000 01000000 00000000 -// CHECK-NEXT: 0630: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0630: 18000000 00000000 037A5052 00017810 // CHECK-NEXT: 0640: 069B0000 00001B0C 07089001 10000000 // CHECK-NEXT: 0650: 20000000 00000000 01000000 00000000 -// CHECK-NEXT: 0660: 1C000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0660: 1C000000 00000000 037A5052 00017810 // CHECK-NEXT: 0670: 0A9C0000 00000000 00001B0C 07089001 // CHECK-NEXT: 0680: 10000000 24000000 00000000 01000000 -// CHECK-NEXT: 0690: 00000000 1C000000 00000000 017A5052 +// CHECK-NEXT: 0690: 00000000 1C000000 00000000 037A5052 // CHECK-NEXT: 06A0: 00017810 0A980000 00000000 00001B0C // CHECK-NEXT: 06B0: 07089001 10000000 24000000 00000000 // CHECK-NEXT: 06C0: 01000000 00000000 10000000 00000000 -// CHECK-NEXT: 06D0: 017A5200 01781001 1B000000 10000000 +// CHECK-NEXT: 06D0: 037A5200 01781001 1B000000 10000000 // CHECK-NEXT: 06E0: 18000000 00000000 01000000 00000000 // CHECK-NEXT: ) // CHECK-NEXT: } diff --git a/test/MC/ELF/gnu-type-diagnostics.s b/test/MC/ELF/gnu-type-diagnostics.s new file mode 100644 index 0000000..df87d6d --- /dev/null +++ b/test/MC/ELF/gnu-type-diagnostics.s @@ -0,0 +1,18 @@ +// RUN: not llvm-mc -triple i686-elf -filetype asm -o /dev/null %s 2>&1 | FileCheck %s + + .type TYPE FUNC +// CHECK: error: unsupported attribute in '.type' directive +// CHECK: .type TYPE FUNC +// CHECK: ^ + + .type type stt_func +// CHECK: error: unsupported attribute in '.type' directive +// CHECK: .type type stt_func +// CHECK: ^ + + .type symbol 32 +// CHECK: error: expected STT_<TYPE_IN_UPPER_CASE>, '#<type>', '@<type>', '%<type>' or "<type>" +// CHECK: .type symbol 32 +// CHECK: ^ + + diff --git a/test/MC/ELF/gnu-type.s b/test/MC/ELF/gnu-type.s new file mode 100644 index 0000000..19029e4 --- /dev/null +++ b/test/MC/ELF/gnu-type.s @@ -0,0 +1,38 @@ +// RUN: llvm-mc -triple i686-elf -filetype asm -o - %s | FileCheck %s + + .type TYPE STT_FUNC +// CHECK: .type TYPE,@function + + .type comma_TYPE, STT_FUNC +// CHECK: .type comma_TYPE,@function + + .type at_TYPE, @STT_FUNC +// CHECK: .type at_TYPE,@function + + .type percent_TYPE, %STT_FUNC +// CHECK: .type percent_TYPE,@function + + .type string_TYPE, "STT_FUNC" +// CHECK: .type string_TYPE,@function + + .type type function +// CHECK: .type type,@function + + .type comma_type, function +// CHECK: .type comma_type,@function + + .type at_type, @function +// CHECK: .type at_type,@function + + .type percent_type, %function +// CHECK: .type percent_type,@function + + .type string_type, "function" +// CHECK: .type string_type,@function + + .type special gnu_unique_object +// CHECK: .type special,@gnu_unique_object + + .type comma_special, gnu_unique_object +// CHECK: .type comma_special,@gnu_unique_object + diff --git a/test/MC/ELF/lit.local.cfg b/test/MC/ELF/lit.local.cfg index ba763cf..e71f3cc 100644 --- a/test/MC/ELF/lit.local.cfg +++ b/test/MC/ELF/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True diff --git a/test/MC/ELF/no-reloc.s b/test/MC/ELF/no-reloc.s new file mode 100644 index 0000000..78f1b88 --- /dev/null +++ b/test/MC/ELF/no-reloc.s @@ -0,0 +1,19 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -r | FileCheck %s + +// CHECK: Relocations [ +// CHECK-NEXT: ] + + .section .test1_foo +.Ltest1_1: +.Ltest1_2 = .Ltest1_1 + .section .test1_bar + .long .Ltest1_1-.Ltest1_2 + + + .section test2 + +.Ltest2_a: +.Ltest2_b = .Ltest2_a +.Ltest2_c: +.Ltest2_d = .Ltest2_c-.Ltest2_b + .long .Ltest2_d diff --git a/test/MC/ELF/pr19430.s b/test/MC/ELF/pr19430.s new file mode 100644 index 0000000..a1e5246 --- /dev/null +++ b/test/MC/ELF/pr19430.s @@ -0,0 +1,14 @@ +// RUN: llvm-mc -triple x86_64-pc-linux-gnu %s -filetype=obj -o - | llvm-readobj -r | FileCheck %s + +// Test that we can use .cfi_startproc without a global symbol. + +.text +.space 1000 +.cfi_startproc + .cfi_endproc + +// CHECK: Relocations [ +// CHECK-NEXT: Section (5) .rela.eh_frame { +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x3E8 +// CHECK-NEXT: } +// CHECK-NEXT: ] diff --git a/test/MC/MachO/AArch64/lit.local.cfg b/test/MC/MachO/AArch64/lit.local.cfg index 9a66a00..cec29af 100644 --- a/test/MC/MachO/AArch64/lit.local.cfg +++ b/test/MC/MachO/AArch64/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'AArch64' in targets: +if not 'AArch64' in config.root.targets: config.unsupported = True diff --git a/test/MC/MachO/ARM/aliased-symbols.s b/test/MC/MachO/ARM/aliased-symbols.s new file mode 100644 index 0000000..0b4463d --- /dev/null +++ b/test/MC/MachO/ARM/aliased-symbols.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple thumbv7m-apple-darwin-eabi %s -filetype=obj -o %t +// RUN: llvm-readobj -symbols %t | FileCheck %s + + .data + var1 = var2 + .long var1 + .long var2 + .long var2 + 4 +defined_early: + .long 0 + + alias_to_early = defined_early + alias_to_late = defined_late + +defined_late: + .long 0 + + .global extern_test + extern_test = var2 + + alias_to_local = Ltmp0 +Ltmp0: + +// CHECK: Symbols [ + + // defined_early was defined. Actually has value 0xc. +// CHECK: Symbol { +// CHECK-NEXT: Name: defined_early +// CHECK-NEXT: Type: Section (0xE) +// CHECK-NEXT: Section: __data (0x2) +// CHECK-NEXT: RefType: UndefinedNonLazy (0x0) +// CHECK-NEXT: Flags [ (0x0) +// CHECK-NEXT: ] +// CHECK-NEXT: Value: 0x[[DEFINED_EARLY:[0-9A-F]+]] +// CHECK-NEXT: } + + // alias_to_early was an alias to defined_early. But we can resolve it. +// CHECK: Symbol { +// CHECK-NEXT: Name: alias_to_early +// CHECK-NEXT: Type: Section (0xE) +// CHECK-NEXT: Section: __data (0x2) +// CHECK-NEXT: RefType: UndefinedNonLazy (0x0) +// CHECK-NEXT: Flags [ (0x0) +// CHECK-NEXT: ] +// CHECK-NEXT: Value: 0x[[DEFINED_EARLY]] +// CHECK-NEXT: } + + // defined_late was defined. Just after defined_early. +// CHECK: Symbol { +// CHECK-NEXT: Name: defined_late +// CHECK-NEXT: Type: Section (0xE) +// CHECK-NEXT: Section: __data (0x2) +// CHECK-NEXT: RefType: UndefinedNonLazy (0x0) +// CHECK-NEXT: Flags [ (0x0) +// CHECK-NEXT: ] +// CHECK-NEXT: Value: 0x[[DEFINED_LATE:[0-9A-F]+]] +// CHECK-NEXT: } + + // alias_to_late was an alias to defined_late. But we can resolve it. +// CHECK: Symbol { +// CHECK-NEXT: Name: alias_to_late +// CHECK-NEXT: Type: Section (0xE) +// CHECK-NEXT: Section: __data (0x2) +// CHECK-NEXT: RefType: UndefinedNonLazy (0x0) +// CHECK-NEXT: Flags [ (0x0) +// CHECK-NEXT: ] +// CHECK-NEXT: Value: 0x[[DEFINED_LATE]] +// CHECK-NEXT: } + + // alias_to_local is an alias, but what it points to has no + // MachO representation. We must resolve it. +// CHECK: Symbol { +// CHECK-NEXT: Name: alias_to_local (37) +// CHECK-NEXT: Type: Section (0xE) +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: RefType: UndefinedNonLazy (0x0) +// CHECK-NEXT: Flags [ (0x0) +// CHECK-NEXT: ] +// CHECK-NEXT: Value: 0x14 +// CHECK-NEXT: } + + // extern_test was a pure alias to the unknown "var2". + // N_INDR and Extern. +// CHECK: Name: extern_test +// CHECK-NEXT: Extern +// CHECK-NEXT: Type: Indirect (0xA) +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: RefType: UndefinedNonLazy (0x0) +// CHECK-NEXT: Flags [ (0x0) +// CHECK-NEXT: ] +// CHECK-NEXT: Value: 0x[[VAR2_STRINGINDEX:[0-9a-f]+]] +// CHECK-NEXT: } + + // var1 was another alias to an unknown variable. Not extern this time. +// CHECK: Symbol { +// CHECK-NEXT: Name: var1 (1) +// CHECK-NEXT: Type: Indirect (0xA) +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: RefType: UndefinedNonLazy (0x0) +// CHECK-NEXT: Flags [ (0x0) +// CHECK-NEXT: ] +// CHECK-NEXT: Value: 0x[[VAR2_STRINGINDEX]] +// CHECK-NEXT: } + + // var2 was a normal undefined (extern) symbol. +// CHECK: Symbol { +// CHECK-NEXT: Name: var2 +// CHECK-NEXT: Extern +// CHECK-NEXT: Type: Undef (0x0) +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: RefType: UndefinedNonLazy (0x0) +// CHECK-NEXT: Flags [ (0x0) +// CHECK-NEXT: ] +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: } diff --git a/test/MC/MachO/ARM/lit.local.cfg b/test/MC/MachO/ARM/lit.local.cfg index 8a3ba96..98c6700 100644 --- a/test/MC/MachO/ARM/lit.local.cfg +++ b/test/MC/MachO/ARM/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'ARM' in targets: +if not 'ARM' in config.root.targets: config.unsupported = True diff --git a/test/MC/MachO/eh-frame-reloc.s b/test/MC/MachO/eh-frame-reloc.s index 1b1c674..e14825b 100644 --- a/test/MC/MachO/eh-frame-reloc.s +++ b/test/MC/MachO/eh-frame-reloc.s @@ -1,5 +1,6 @@ // RUN: llvm-mc < %s -triple=x86_64-apple-macosx10.7 -filetype=obj | llvm-readobj -r | FileCheck %s // RUN: llvm-mc < %s -triple=x86_64-apple-macosx10.6 -filetype=obj | llvm-readobj -r | FileCheck %s +// RUN: llvm-mc < %s -triple=x86_64-apple-ios7.0.0 -filetype=obj | llvm-readobj -r | FileCheck %s // RUN: llvm-mc < %s -triple=x86_64-apple-macosx10.5 -filetype=obj | llvm-readobj -r | FileCheck --check-prefix=OLD64 %s // RUN: llvm-mc < %s -triple=i686-apple-macosx10.6 -filetype=obj | llvm-readobj -r | FileCheck %s // RUN: llvm-mc < %s -triple=i686-apple-macosx10.5 -filetype=obj | llvm-readobj -r | FileCheck --check-prefix=OLD32 %s @@ -16,14 +17,14 @@ _bar: // OLD32: Relocations [ // OLD32-NEXT: Section __eh_frame { -// OLD32-NEXT: 0x20 0 2 n/a GENERIC_RELOC_LOCAL_SECTDIFF 1 - -// OLD32-NEXT: 0x0 0 2 n/a GENERIC_RELOC_PAIR 1 - +// OLD32-NEXT: 0x20 0 2 n/a GENERIC_RELOC_LOCAL_SECTDIFF 1 0x0 +// OLD32-NEXT: 0x0 0 2 n/a GENERIC_RELOC_PAIR 1 0x20 // OLD32-NEXT: } // OLD32-NEXT: ] // OLD64: Relocations [ // OLD64-NEXT: Section __eh_frame { -// OLD64-NEXT: 0x20 0 3 1 X86_64_RELOC_SUBTRACTOR 0 _bar.eh +// OLD64-NEXT: 0x20 0 3 0 X86_64_RELOC_SUBTRACTOR 0 // OLD64-NEXT: 0x20 0 3 1 X86_64_RELOC_UNSIGNED 0 _bar // OLD64-NEXT: } // OLD64-NEXT: ] diff --git a/test/MC/MachO/eh-symbols.s b/test/MC/MachO/eh-symbols.s deleted file mode 100644 index 6adca56..0000000 --- a/test/MC/MachO/eh-symbols.s +++ /dev/null @@ -1,25 +0,0 @@ -// RUN: llvm-mc -filetype=obj -triple i686-apple-darwin %s -o - | llvm-readobj -t | FileCheck %s - -// Make sure that the exception handling data has the same visibility as the -// function it's generated for. - - .private_extern _main - .globl _main -_main: - .cfi_startproc - retl - .cfi_endproc - -"_-[NSString(local) isNullOrNil]": - .cfi_startproc - retl - .cfi_endproc - -// CHECK: Name: _-[NSString(local) isNullOrNil].eh - -// CHECK: Name: _main -// CHECK-NEXT: PrivateExtern - -// CHECK: Name: _main.eh -// CHECK-NEXT: PrivateExtern - diff --git a/test/MC/MachO/eh_symbol.s b/test/MC/MachO/eh_symbol.s index 1135196..738e2b6 100644 --- a/test/MC/MachO/eh_symbol.s +++ b/test/MC/MachO/eh_symbol.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | llvm-nm | FileCheck %s +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o - | llvm-nm - | FileCheck %s // test that we don't produce foo.eh symbols in a debug_frame section. // CHECK-NOT: _f.eh diff --git a/test/MC/MachO/lit.local.cfg b/test/MC/MachO/lit.local.cfg index ba763cf..e71f3cc 100644 --- a/test/MC/MachO/lit.local.cfg +++ b/test/MC/MachO/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True diff --git a/test/MC/MachO/pr19185.s b/test/MC/MachO/pr19185.s new file mode 100644 index 0000000..fb21e51 --- /dev/null +++ b/test/MC/MachO/pr19185.s @@ -0,0 +1,6 @@ +// RUN: llvm-mc -triple x86_64-apple-darwin %s -filetype=obj -o %t.o +f: + .cfi_startproc + .cfi_endproc + +EH_frame0: diff --git a/test/MC/MachO/variable-exprs.s b/test/MC/MachO/variable-exprs.s index 8eeb82f..a7fa45d 100644 --- a/test/MC/MachO/variable-exprs.s +++ b/test/MC/MachO/variable-exprs.s @@ -202,10 +202,10 @@ Lt0_x = Lt0_a - Lt0_b // CHECK-I386: ), // CHECK-I386: # Symbol 8 // CHECK-I386: (('n_strx', 1) -// CHECK-I386: ('n_type', 0x1) +// CHECK-I386: ('n_type', 0xb) // CHECK-I386: ('n_sect', 0) // CHECK-I386: ('n_desc', 0) -// CHECK-I386: ('n_value', 0) +// CHECK-I386: ('n_value', 4) // CHECK-I386: ('_string', 'd2') // CHECK-I386: ), // CHECK-I386: # Symbol 9 @@ -403,10 +403,10 @@ Lt0_x = Lt0_a - Lt0_b // CHECK-X86_64: ), // CHECK-X86_64: # Symbol 8 // CHECK-X86_64: (('n_strx', 1) -// CHECK-X86_64: ('n_type', 0x1) +// CHECK-X86_64: ('n_type', 0xb) // CHECK-X86_64: ('n_sect', 0) // CHECK-X86_64: ('n_desc', 0) -// CHECK-X86_64: ('n_value', 0) +// CHECK-X86_64: ('n_value', 4) // CHECK-X86_64: ('_string', 'd2') // CHECK-X86_64: ), // CHECK-X86_64: # Symbol 9 diff --git a/test/MC/Mips/cpsetup-bad.s b/test/MC/Mips/cpsetup-bad.s new file mode 100644 index 0000000..09252a1 --- /dev/null +++ b/test/MC/Mips/cpsetup-bad.s @@ -0,0 +1,14 @@ +# RUN: not llvm-mc %s -triple mips64-unknown-unknown 2>%t1 +# RUN: FileCheck %s < %t1 -check-prefix=ASM + + .text + .option pic2 +t1: + .cpsetup $bar, 8, __cerror +# ASM: :[[@LINE-1]]:18: error: expected register containing function address + .cpsetup $33, 8, __cerror +# ASM: :[[@LINE-1]]:18: error: invalid register + .cpsetup $31, foo, __cerror +# ASM: :[[@LINE-1]]:23: error: expected save register or stack offset + .cpsetup $31, $32, __cerror +# ASM: :[[@LINE-1]]:23: error: invalid register diff --git a/test/MC/Mips/eh-frame.s b/test/MC/Mips/eh-frame.s index 1671598..d6b9cf0 100644 --- a/test/MC/Mips/eh-frame.s +++ b/test/MC/Mips/eh-frame.s @@ -31,7 +31,7 @@ func: // MIPS32: 00000000 // Version -// MIPS32: 01 +// MIPS32: 03 // Augmentation String // MIPS32: 7a5200 @@ -67,7 +67,7 @@ func: // MIPS32EL: 00000000 // Version -// MIPS32EL: 01 +// MIPS32EL: 03 // Augmentation String // MIPS32EL: 7a5200 @@ -103,7 +103,7 @@ func: // MIPS64: 00000000 // Version -// MIPS64: 01 +// MIPS64: 03 // Augmentation String // MIPS64: 7a5200 @@ -141,7 +141,7 @@ func: // MIPS64EL: 00000000 // Version -// MIPS64EL: 01 +// MIPS64EL: 03 // Augmentation String // MIPS64EL: 7a5200 diff --git a/test/MC/Mips/elf_eflags.s b/test/MC/Mips/elf_eflags.s index 8cf4960..36f4f9e 100644 --- a/test/MC/Mips/elf_eflags.s +++ b/test/MC/Mips/elf_eflags.s @@ -1,6 +1,12 @@ # These *MUST* match the output of gas compiled with the same triple and # corresponding options (-mcpu=mips32 -> -mips32 for example). +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r6 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R6 %s +# MIPSEL-MIPS64R6: Flags [ (0xA0001500) + +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r6 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R6-NAN2008 %s +# MIPSEL-MIPS64R6-NAN2008: Flags [ (0xA0001500) + # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2 %s # MIPSEL-MIPS64R2: Flags [ (0x80001100) @@ -13,6 +19,12 @@ # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64-NAN2008 %s # MIPSEL-MIPS64-NAN2008: Flags [ (0x60001500) +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r6 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R6 %s +# MIPSEL-MIPS32R6: Flags [ (0x90001400) + +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r6 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R6-NAN2008 %s +# MIPSEL-MIPS32R6-NAN2008: Flags [ (0x90001400) + # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2 %s # MIPSEL-MIPS32R2: Flags [ (0x70001000) @@ -55,12 +67,36 @@ # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,o32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-O32-NAN2008 %s # MIPS64EL-MIPS64R2-O32-NAN2008: Flags [ (0x80001500) +# RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips5 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS5 %s +# MIPS5: Flags [ (0x40000000) + + # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips5 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS5-NAN2008 %s +# MIPS5-NAN2008: Flags [ (0x40000400) + # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips4 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS4 %s # MIPS4: Flags [ (0x30000000) # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips4 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS4-NAN2008 %s # MIPS4-NAN2008: Flags [ (0x30000400) +# RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips3 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS3 %s +# MIPS3: Flags [ (0x20000000) + + # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips3 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS3-NAN2008 %s +# MIPS3-NAN2008: Flags [ (0x20000400) + +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS2 %s +# MIPSEL-MIPS2: Flags [ (0x10001000) + +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS2-NAN2008 %s +# MIPSEL-MIPS2-NAN2008: Flags [ (0x10001400) + +# RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips1 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS1 %s +# MIPS1: Flags [ (0x1000) + + # RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips1 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS1-NAN2008 %s +# MIPS1-NAN2008: Flags [ (0x1400) + # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=-n64,o32 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-O32 %s # MIPS64EL-MIPS64-O32: Flags [ (0x60001100) diff --git a/test/MC/Mips/lit.local.cfg b/test/MC/Mips/lit.local.cfg index 1fa54b4..a3183a2 100644 --- a/test/MC/Mips/lit.local.cfg +++ b/test/MC/Mips/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'Mips' in targets: +if not 'Mips' in config.root.targets: config.unsupported = True diff --git a/test/MC/Mips/mips-abi-bad.s b/test/MC/Mips/mips-abi-bad.s new file mode 100644 index 0000000..c4653cf --- /dev/null +++ b/test/MC/Mips/mips-abi-bad.s @@ -0,0 +1,20 @@ +# Error checking for malformed abi related directives +# RUN: not llvm-mc -triple mips-unknown-unknown %s 2>&1 | FileCheck %s +# CHECK: .text + .module fp=3 +# CHECK : mips-abi-bad.s:4:16: error: unsupported option +# CHECK-NEXT : .module fp=3 +# CHECK-NEXT : ^ + + .set fp=xx,6 +# CHECK :mips-abi-bad.s:5:15: error: unexpected token in statement +# CHECK-NEXT : .set fp=xx,6 +# CHECK-NEXT : ^ + +# CHECK :.set mips16 + .set mips16 + .module fp=32 + +# CHECK :mips-abi-bad.s:14:13: error: .module directive must come before any code +# CHECK-NEXT : .module fp=32 +# CHECK-NEXT : ^ diff --git a/test/MC/Mips/mips-data-directives.s b/test/MC/Mips/mips-data-directives.s index 630a807..8b3e0b3 100644 --- a/test/MC/Mips/mips-data-directives.s +++ b/test/MC/Mips/mips-data-directives.s @@ -12,7 +12,7 @@ # Checking if the data and reloations were correctly emitted # CHECK-OBJ: Section { -# CHECK-OBJ: Name: .data (51) +# CHECK-OBJ: Name: .data (66) # CHECK-OBJ: SectionData ( # CHECK-OBJ: 0000: DEADC0DE DEADC0DE DEADBEEF 00000000 # CHECK-OBJ: 0010: 00000000 00000000 @@ -20,7 +20,7 @@ # CHECK-OBJ: } # CHECK-OBJ: Section { -# CHECK-OBJ: Name: .rel.data (47) +# CHECK-OBJ: Name: .rel.data (62) # CHECK-OBJ: Relocations [ # CHECK-OBJ: 0xC R_MIPS_32 .data 0x0 # CHECK-OBJ: 0x10 R_MIPS_64 .data 0x0 diff --git a/test/MC/Mips/mips-expansions-bad.s b/test/MC/Mips/mips-expansions-bad.s new file mode 100644 index 0000000..a137deb --- /dev/null +++ b/test/MC/Mips/mips-expansions-bad.s @@ -0,0 +1,6 @@ +# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1 +# RUN: FileCheck %s < %t1 + + .text + li $5, 0x100000000 # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled + dli $5, 1 # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips-expansions.s b/test/MC/Mips/mips-expansions.s index 1622965..f0a04a5 100644 --- a/test/MC/Mips/mips-expansions.s +++ b/test/MC/Mips/mips-expansions.s @@ -8,6 +8,8 @@ # CHECK: addiu $6, $zero, -2345 # encoding: [0xd7,0xf6,0x06,0x24] # CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c] # CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34] +# CHECK: addiu $8, $zero, -8 # encoding: [0xf8,0xff,0x08,0x24] + # CHECK: addiu $4, $zero, 20 # encoding: [0x14,0x00,0x04,0x24] # CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c] # CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34] @@ -32,17 +34,28 @@ # CHECK: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00] # CHECK: sw $10, 57920($1) # encoding: [0x40,0xe2,0x2a,0xac] +# CHECK: lui $1, %hi(symbol) +# CHECK: ldc1 $f0, %lo(symbol)($1) +# CHECK: lui $1, %hi(symbol) +# CHECK: sdc1 $f0, %lo(symbol)($1) + li $5,123 li $6,-2345 li $7,65538 + li $8, ~7 la $a0, 20 la $7,65538 la $a0, 20($a1) la $7,65538($8) + .set noat lw $t2, symbol($a0) + .set at sw $t2, symbol($t1) lw $t2, 655483($a0) sw $t2, 123456($t1) + + ldc1 $f0, symbol + sdc1 $f0, symbol diff --git a/test/MC/Mips/mips-noat.s b/test/MC/Mips/mips-noat.s index b83c517..07db251 100644 --- a/test/MC/Mips/mips-noat.s +++ b/test/MC/Mips/mips-noat.s @@ -10,11 +10,10 @@ test1: lw $2, 65536($2) -# FIXME: It would be better if the error pointed at the mnemonic instead of the newline -# ERROR: mips-noat.s:[[@LINE+4]]:1: error: Pseudo instruction requires $at, which is not available test2: .set noat - lw $2, 65536($2) + lw $2, 65536($2) # ERROR: mips-noat.s:[[@LINE]]:9: error: Pseudo instruction requires $at, which is not available + # Can we switch it back on successfully? # CHECK-LABEL: test3: @@ -25,10 +24,6 @@ test3: .set at lw $2, 65536($2) -# FIXME: It would be better if the error pointed at the mnemonic instead of the newline -# ERROR: mips-noat.s:[[@LINE+4]]:1: error: Pseudo instruction requires $at, which is not available test4: .set at=$0 - lw $2, 65536($2) - -# ERROR-NOT: error + lw $2, 65536($2) # ERROR: mips-noat.s:[[@LINE]]:9: error: Pseudo instruction requires $at, which is not available diff --git a/test/MC/Mips/mips1/invalid-mips2.s b/test/MC/Mips/mips1/invalid-mips2.s index 6c3e80a..7db261d 100644 --- a/test/MC/Mips/mips1/invalid-mips2.s +++ b/test/MC/Mips/mips1/invalid-mips2.s @@ -21,3 +21,4 @@ tnei $t4,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sync # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips1/invalid-mips32.s b/test/MC/Mips/mips1/invalid-mips32.s new file mode 100644 index 0000000..4ad8d63 --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips32.s @@ -0,0 +1,10 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + + sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips1/invalid-mips4.s b/test/MC/Mips/mips1/invalid-mips4.s index 61aaf58..9f246bc 100644 --- a/test/MC/Mips/mips1/invalid-mips4.s +++ b/test/MC/Mips/mips1/invalid-mips4.s @@ -4,7 +4,9 @@ # RUN: 2>%t1 # RUN: FileCheck %s < %t1 - .set noat + .set noat + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -50,15 +52,20 @@ floor.w.s $f8,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f10,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f10,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f10,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f26,$f20,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips1/invalid-mips5.s b/test/MC/Mips/mips1/invalid-mips5.s index 1eddf02..af5b278 100644 --- a/test/MC/Mips/mips1/invalid-mips5.s +++ b/test/MC/Mips/mips1/invalid-mips5.s @@ -4,7 +4,9 @@ # RUN: 2>%t1 # RUN: FileCheck %s < %t1 - .set noat + .set noat + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -49,15 +51,20 @@ ldxc1 $f8,$s7($t3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$a0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f10,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f10,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movz $a1,$s6,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips1/valid.s b/test/MC/Mips/mips1/valid.s index 473e6b9..66e11ba 100644 --- a/test/MC/Mips/mips1/valid.s +++ b/test/MC/Mips/mips1/valid.s @@ -9,8 +9,18 @@ add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 + addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 and $s7,$v0,$12 + and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] + bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] + bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 @@ -36,7 +46,7 @@ li $zero,-29889 lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwc3 $10,-32265($k0) lwl $s4,-4231($15) lwr $zero,-19147($gp) @@ -65,6 +75,7 @@ nop nor $a3,$zero,$a3 or $12,$s0,$sp + or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] sb $s6,-19857($14) sh $14,-6704($15) sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] @@ -91,7 +102,7 @@ subu $sp,$s6,$s6 sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc3 $10,-32265($k0) swl $15,13694($s3) swr $s1,-26590($14) diff --git a/test/MC/Mips/mips2/invalid-mips3-wrong-error.s b/test/MC/Mips/mips2/invalid-mips3-wrong-error.s index a3f829b..3eb4ef3 100644 --- a/test/MC/Mips/mips2/invalid-mips3-wrong-error.s +++ b/test/MC/Mips/mips2/invalid-mips3-wrong-error.s @@ -7,7 +7,6 @@ .set noat dmult $s7,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - dsub $a3,$s6,$a4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldl $t8,-4167($t8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldr $t2,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips2/invalid-mips3.s b/test/MC/Mips/mips2/invalid-mips3.s index ef498d7..458c416 100644 --- a/test/MC/Mips/mips2/invalid-mips3.s +++ b/test/MC/Mips/mips2/invalid-mips3.s @@ -38,6 +38,7 @@ dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsub $a3,$s6,$a4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/invalid-mips32.s b/test/MC/Mips/mips2/invalid-mips32.s index 2975c68..43ea345 100644 --- a/test/MC/Mips/mips2/invalid-mips32.s +++ b/test/MC/Mips/mips2/invalid-mips32.s @@ -1,28 +1,38 @@ # Instructions that are invalid # -# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ # RUN: 2>%t1 # RUN: FileCheck %s < %t1 - .set noat + .set noat + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction clo $11,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + jr.hb $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + jalr.hb $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + jalr.hb $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -30,3 +40,5 @@ msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/invalid-mips32r2.s b/test/MC/Mips/mips2/invalid-mips32r2.s index 37f2eed..72a570a 100644 --- a/test/MC/Mips/mips2/invalid-mips32r2.s +++ b/test/MC/Mips/mips2/invalid-mips32r2.s @@ -1,10 +1,12 @@ # Instructions that are invalid # -# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips2 \ +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \ # RUN: 2>%t1 # RUN: FileCheck %s < %t1 - .set noat + .set noat + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -24,15 +26,20 @@ maddu $t8,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$t0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movz $a1,$s6,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/invalid-mips4.s b/test/MC/Mips/mips2/invalid-mips4.s index e2eb672..13923f0 100644 --- a/test/MC/Mips/mips2/invalid-mips4.s +++ b/test/MC/Mips/mips2/invalid-mips4.s @@ -4,7 +4,9 @@ # RUN: 2>%t1 # RUN: FileCheck %s < %t1 - .set noat + .set noat + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -46,15 +48,20 @@ floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/invalid-mips5.s b/test/MC/Mips/mips2/invalid-mips5.s index f777ffe..8f460c7 100644 --- a/test/MC/Mips/mips2/invalid-mips5.s +++ b/test/MC/Mips/mips2/invalid-mips5.s @@ -4,7 +4,9 @@ # RUN: 2>%t1 # RUN: FileCheck %s < %t1 - .set noat + .set noat + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -45,15 +47,20 @@ ldxc1 $f8,$s7($t3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$a0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$a0,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$a0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movz $a1,$s6,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/valid.s b/test/MC/Mips/mips2/valid.s index e3effde..9c3706e 100644 --- a/test/MC/Mips/mips2/valid.s +++ b/test/MC/Mips/mips2/valid.s @@ -9,8 +9,18 @@ add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 + addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 and $s7,$v0,$12 + and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] + bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] + bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 @@ -35,16 +45,16 @@ lb $24,-14515($10) lbu $8,30195($v1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] ldc3 $29,-28645($s1) lh $11,-8556($s5) lhu $s3,-22851($v0) li $at,-29773 li $zero,-29889 - ll $v0,-7321($s2) + ll $v0,-7321($s2) # CHECK: ll $2, -7321($18) # encoding: [0xc2,0x42,0xe3,0x67] lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwc3 $10,-32265($k0) lwl $s4,-4231($15) lwr $zero,-19147($gp) @@ -73,12 +83,13 @@ nop nor $a3,$zero,$a3 or $12,$s0,$sp + or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] round.w.d $f6,$f4 round.w.s $f27,$f28 sb $s6,-19857($14) - sc $15,18904($s3) + sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdc3 $12,5835($10) sh $14,-6704($15) sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] @@ -107,10 +118,11 @@ subu $sp,$s6,$s6 sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swc3 $10,-32265($k0) swl $15,13694($s3) swr $s1,-26590($14) + sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] teqi $s5,-17504 tgei $s1,5025 tgeiu $sp,-28621 diff --git a/test/MC/Mips/mips3/invalid-mips32.s b/test/MC/Mips/mips3/invalid-mips32.s new file mode 100644 index 0000000..3acd765 --- /dev/null +++ b/test/MC/Mips/mips3/invalid-mips32.s @@ -0,0 +1,10 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + + sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips3/invalid-mips4.s b/test/MC/Mips/mips3/invalid-mips4.s index 6e15d79..9cd92d3 100644 --- a/test/MC/Mips/mips3/invalid-mips4.s +++ b/test/MC/Mips/mips3/invalid-mips4.s @@ -4,20 +4,27 @@ # RUN: 2>%t1 # RUN: FileCheck %s < %t1 - .set noat + .set noat + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips3/invalid-mips5.s b/test/MC/Mips/mips3/invalid-mips5.s index d25621b..307eee8 100644 --- a/test/MC/Mips/mips3/invalid-mips5.s +++ b/test/MC/Mips/mips3/invalid-mips5.s @@ -4,19 +4,26 @@ # RUN: 2>%t1 # RUN: FileCheck %s < %t1 - .set noat + .set noat + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldxc1 $f8,$s7($t3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$a4,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction movz $a1,$s6,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips3/valid.s b/test/MC/Mips/mips3/valid.s index 2067666..cb209fd 100644 --- a/test/MC/Mips/mips3/valid.s +++ b/test/MC/Mips/mips3/valid.s @@ -9,8 +9,19 @@ add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 + addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 and $s7,$v0,$12 + and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] + bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] + bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 @@ -32,7 +43,11 @@ cvt.w.d $f20,$f14 cvt.w.s $f20,$f24 dadd $s3,$at,$ra + dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] + dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,$s4,-27705 + daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] + daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddiu $k0,$s6,-4586 daddu $s3,$at,$ra ddiv $zero,$k0,$s3 @@ -64,6 +79,10 @@ dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] dsub $a3,$s6,$8 + dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] + dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] + dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] + dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] dsubu $a1,$a1,$k0 ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] eret @@ -75,18 +94,18 @@ lbu $8,30195($v1) ld $sp,-28645($s1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] ldl $24,-4167($24) ldr $14,-30358($s4) lh $11,-8556($s5) lhu $s3,-22851($v0) li $at,-29773 li $zero,-29889 - ll $v0,-7321($s2) - lld $zero,-14736($ra) + ll $v0,-7321($s2) # CHECK: ll $2, -7321($18) # encoding: [0xc2,0x42,0xe3,0x67] + lld $zero,-14736($ra) # CHECK: lld $zero, -14736($ra) # encoding: [0xd3,0xe0,0xc6,0x70] lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwl $s4,-4231($15) lwr $zero,-19147($gp) lwu $s3,-24086($v1) @@ -117,16 +136,17 @@ nop nor $a3,$zero,$a3 or $12,$s0,$sp + or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] round.l.d $f12,$f1 round.l.s $f25,$f5 round.w.d $f6,$f4 round.w.s $f27,$f28 sb $s6,-19857($14) - sc $15,18904($s3) - scd $15,-8243($sp) + sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] + scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd] sd $12,5835($10) sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdl $a3,-20961($s8) sdr $11,-20423($12) sh $14,-6704($15) @@ -156,9 +176,10 @@ subu $sp,$s6,$s6 sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swl $15,13694($s3) swr $s1,-26590($14) + sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] teqi $s5,-17504 tgei $s1,5025 tgeiu $sp,-28621 diff --git a/test/MC/Mips/mips32/abiflags.s b/test/MC/Mips/mips32/abiflags.s new file mode 100644 index 0000000..896dd84 --- /dev/null +++ b/test/MC/Mips/mips32/abiflags.s @@ -0,0 +1,37 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ + +# CHECK-ASM: .module fp=32 + +# Checking if the Mips.abiflags were correctly emitted. +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Offset: 0x50 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 0 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00002001 01010001 00000000 00000000 |.. .............| +# CHECK-OBJ: 0010: 00000000 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ: } + + .module fp=32 + +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/mips32/valid.s b/test/MC/Mips/mips32/valid.s index bc29bdc..d330905 100644 --- a/test/MC/Mips/mips32/valid.s +++ b/test/MC/Mips/mips32/valid.s @@ -9,8 +9,21 @@ add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 + addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 and $s7,$v0,$12 + and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] + bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] + bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] + bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] + bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 @@ -18,8 +31,8 @@ ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 - clo $11,$a1 - clz $sp,$gp + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] ctc1 $a2,$26 cvt.d.s $f22,$f28 cvt.d.w $f26,$f11 @@ -39,15 +52,15 @@ lb $24,-14515($10) lbu $8,30195($v1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] lh $11,-8556($s5) lhu $s3,-22851($v0) li $at,-29773 li $zero,-29889 - ll $v0,-7321($s2) + ll $v0,-7321($s2) # CHECK: ll $2, -7321($18) # encoding: [0xc2,0x42,0xe3,0x67] lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwl $s4,-4231($15) lwr $zero,-19147($gp) madd $s6,$13 @@ -96,12 +109,16 @@ nop nor $a3,$zero,$a3 or $12,$s0,$sp + or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] + pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] round.w.d $f6,$f4 round.w.s $f27,$f28 sb $s6,-19857($14) - sc $15,18904($s3) + sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] + sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f] + sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sh $14,-6704($15) sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] @@ -129,9 +146,11 @@ subu $sp,$s6,$s6 sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swl $15,13694($s3) swr $s1,-26590($14) + sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] teqi $s5,-17504 tgei $s1,5025 tgeiu $sp,-28621 diff --git a/test/MC/Mips/mips32r2/abiflags.s b/test/MC/Mips/mips32r2/abiflags.s new file mode 100644 index 0000000..41a809a --- /dev/null +++ b/test/MC/Mips/mips32r2/abiflags.s @@ -0,0 +1,38 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ + +# CHECK-ASM: .module fp=32 +# CHECK-ASM: .set fp=64 + +# Checking if the Mips.abiflags were correctly emitted. +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Offset: 0x50 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 0 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00002002 01010001 00000000 00000000 |.. .............| +# CHECK-OBJ: 0010: 00000000 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ: } + + .module fp=32 + .set fp=64 +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/mips32r2/invalid.s b/test/MC/Mips/mips32r2/invalid.s new file mode 100644 index 0000000..ebccc43 --- /dev/null +++ b/test/MC/Mips/mips32r2/invalid.s @@ -0,0 +1,10 @@ +# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g. +# invalid set of operands or operand's restrictions not met). + +# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 2>%t1 +# RUN: FileCheck %s < %t1 -check-prefix=ASM + + .text + .set noreorder + jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s index 26f8b6b..631c691 100644 --- a/test/MC/Mips/mips32r2/valid.s +++ b/test/MC/Mips/mips32r2/valid.s @@ -9,8 +9,21 @@ add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 + addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 and $s7,$v0,$12 + and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] + bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] + bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] + bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] + bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 @@ -18,8 +31,8 @@ ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 - clo $11,$a1 - clz $sp,$gp + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] ctc1 $a2,$26 cvt.d.s $f22,$f28 cvt.d.w $f26,$f11 @@ -40,20 +53,23 @@ eret floor.w.d $f14,$f11 floor.w.s $f8,$f9 + jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] + jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] + jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] lb $24,-14515($10) lbu $8,30195($v1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] ldxc1 $f8,$s7($15) lh $11,-8556($s5) lhu $s3,-22851($v0) li $at,-29773 li $zero,-29889 - ll $v0,-7321($s2) + ll $v0,-7321($s2) # CHECK: ll $2, -7321($18) # encoding: [0xc2,0x42,0xe3,0x67] luxc1 $f19,$s6($s5) lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwl $s4,-4231($15) lwr $zero,-19147($gp) lwxc1 $f12,$s1($s8) @@ -113,7 +129,9 @@ nop nor $a3,$zero,$a3 or $12,$s0,$sp + or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] + pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] rdhwr $sp,$11 rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] @@ -121,9 +139,11 @@ round.w.d $f6,$f4 round.w.s $f27,$f28 sb $s6,-19857($14) - sc $15,18904($s3) + sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] + sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f] + sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdxc1 $f11,$10($14) seb $25,$15 seh $v1,$12 @@ -155,10 +175,12 @@ suxc1 $f12,$k1($13) sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swl $15,13694($s3) swr $s1,-26590($14) swxc1 $f19,$12($k0) + sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] teqi $s5,-17504 tgei $s1,5025 tgeiu $sp,-28621 diff --git a/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s index aee068a..52fa5f5 100644 --- a/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s +++ b/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s @@ -5,6 +5,8 @@ # RUN: FileCheck %s < %t1 .set noat + bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips1.s b/test/MC/Mips/mips32r6/invalid-mips1.s index aa7d407..44d4fbb 100644 --- a/test/MC/Mips/mips32r6/invalid-mips1.s +++ b/test/MC/Mips/mips32r6/invalid-mips1.s @@ -6,3 +6,19 @@ .set noat addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + c.sf.d $f30,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + c.sf.s $f14,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthi $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtlo $25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtlo $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mult $sp,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mult $sp,$v0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled +# div has been re-encoded. See valid.s +# divu has been re-encoded. See valid.s diff --git a/test/MC/Mips/mips32r6/invalid-mips2.s b/test/MC/Mips/mips32r6/invalid-mips2.s index 0638e78..bfa2c4c 100644 --- a/test/MC/Mips/mips32r6/invalid-mips2.s +++ b/test/MC/Mips/mips32r6/invalid-mips2.s @@ -6,9 +6,21 @@ .set noat addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthi $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtlo $25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtlo $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mult $sp,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mult $sp,$v0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tlti $14,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tnei $12,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled +# div has been re-encoded. See valid.s +# divu has been re-encoded. See valid.s diff --git a/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s index e416a20..e63bdd4 100644 --- a/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s +++ b/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s @@ -10,6 +10,10 @@ bc1tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction bc1fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips32.s b/test/MC/Mips/mips32r6/invalid-mips32.s new file mode 100644 index 0000000..e0889ea --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips32.s @@ -0,0 +1,25 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid-mips32r2.s b/test/MC/Mips/mips32r6/invalid-mips32r2.s new file mode 100644 index 0000000..25694e3 --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips32r2.s @@ -0,0 +1,15 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s new file mode 100644 index 0000000..f3131a9 --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s @@ -0,0 +1,21 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + beql $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bgezall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bgezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bgtzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + blezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bltzall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bltzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bnel $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips4.s b/test/MC/Mips/mips32r6/invalid-mips4.s new file mode 100644 index 0000000..8ba2ed8 --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips4.s @@ -0,0 +1,11 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s new file mode 100644 index 0000000..99d10c3 --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s @@ -0,0 +1,11 @@ +# Instructions that are invalid but currently emit the wrong error message. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + bc1any2f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any2t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any4f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any4t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips5.s b/test/MC/Mips/mips32r6/invalid-mips5.s new file mode 100644 index 0000000..63f1cca --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid-mips5.s @@ -0,0 +1,9 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid.s b/test/MC/Mips/mips32r6/invalid.s new file mode 100644 index 0000000..82cb5ab --- /dev/null +++ b/test/MC/Mips/mips32r6/invalid.s @@ -0,0 +1,14 @@ +# Instructions that are available for the current ISA but should be rejected by +# the assembler (e.g. invalid set of operands or operand's restrictions not met). + +# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 2>%t1 +# RUN: FileCheck %s < %t1 -check-prefix=ASM + + .text + .set noreorder + .set noat + jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdc2 $20,23157($s2) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swc2 $25,24880($s0) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/relocations.s b/test/MC/Mips/mips32r6/relocations.s index 4532e42..13b3387 100644 --- a/test/MC/Mips/mips32r6/relocations.s +++ b/test/MC/Mips/mips32r6/relocations.s @@ -5,6 +5,9 @@ #------------------------------------------------------------------------------ # Check that the assembler can handle the documented syntax for fixups. #------------------------------------------------------------------------------ +# CHECK-FIXUP: addiupc $2, bar # encoding: [0xec,0b01000AAA,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A] # CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16 @@ -31,20 +34,30 @@ # CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: value: bar@PCREL_LO16, # CHECK-FIXUP: kind: fixup_MIPS_PCLO16 +# CHECK-FIXUP: lwpc $2, bar # encoding: [0xec,0b01001AAA,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 +# CHECK-FIXUP: lwupc $2, bar # encoding: [0xec,0b01010AAA,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 #------------------------------------------------------------------------------ # Check that the appropriate relocations were created. #------------------------------------------------------------------------------ # CHECK-ELF: Relocations [ -# CHECK-ELF: 0x0 R_MIPS_PC16 bar 0x0 +# CHECK-ELF: 0x0 R_MIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0 -# CHECK-ELF: 0x8 R_MIPS_PC21_S2 bar 0x0 +# CHECK-ELF: 0x8 R_MIPS_PC16 bar 0x0 # CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0 -# CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0 +# CHECK-ELF: 0x10 R_MIPS_PC21_S2 bar 0x0 # CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0 -# CHECK-ELF: 0x18 R_MIPS_PCHI16 bar 0x0 -# CHECK-ELF: 0x1C R_MIPS_PCLO16 bar 0x0 +# CHECK-ELF: 0x18 R_MIPS_PC26_S2 bar 0x0 +# CHECK-ELF: 0x1C R_MIPS_PCHI16 bar 0x0 +# CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0 +# CHECK-ELF: 0x24 R_MIPS_PC19_S2 bar 0x0 +# CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0 # CHECK-ELF: ] + addiupc $2,bar beqc $5, $6, bar bnec $5, $6, bar beqzc $9, bar @@ -53,3 +66,5 @@ bc bar aluipc $2, %pcrel_hi(bar) addiu $2, $2, %pcrel_lo(bar) + lwpc $2,bar + lwupc $2,bar diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s index 5b4b928..f23dbd7 100644 --- a/test/MC/Mips/mips32r6/valid.s +++ b/test/MC/Mips/mips32r6/valid.s @@ -10,15 +10,18 @@ # rs > rt # appropriately for each branch instruction # -# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 | FileCheck %s +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 2> %t0 | FileCheck %s +# RUN: FileCheck %s -check-prefix=WARNING < %t0 .set noat # FIXME: Add the instructions carried forward from older ISA's + and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19] align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0] aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9] auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff] + bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8] bc 14572256 # CHECK: bc 14572256 # encoding: [0xc8,0x37,0x96,0xb8] bc1eqz $f0,4 # CHECK: bc1eqz $f0, 4 # encoding: [0x45,0x20,0x00,0x01] @@ -38,6 +41,8 @@ bnec $5, $6, 256 # CHECK: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40] bnezalc $2, 1332 # CHECK: bnezalc $2, 1332 # encoding: [0x60,0x02,0x01,0x4d] beqzc $5, 72256 # CHECK: beqzc $5, 72256 # encoding: [0xd8,0xa0,0x46,0x90] + bgec $2, $3, 256 # CHECK: bgec $2, $3, 256 # encoding: [0x58,0x43,0x00,0x40] + bgeuc $2, $3, 256 # CHECK: bgeuc $2, $3, 256 # encoding: [0x18,0x43,0x00,0x40] bgezalc $2, 1332 # CHECK: bgezalc $2, 1332 # encoding: [0x18,0x42,0x01,0x4d] bnezc $5, 72256 # CHECK: bnezc $5, 72256 # encoding: [0xf8,0xa0,0x46,0x90] bltzc $5, 256 # CHECK: bltzc $5, 256 # encoding: [0x5c,0xa5,0x00,0x40] @@ -48,6 +53,8 @@ bgtzc $5, 256 # CHECK: bgtzc $5, 256 # encoding: [0x5c,0x05,0x00,0x40] bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20] blezalc $2, 1332 # CHECK: blezalc $2, 1332 # encoding: [0x18,0x02,0x01,0x4d] + bltc $5, $6, 256 # CHECK: bltc $5, $6, 256 # encoding: [0x5c,0xa6,0x00,0x40] + bltuc $5, $6, 256 # CHECK: bltuc $5, $6, 256 # encoding: [0x1c,0xa6,0x00,0x40] # bnvc requires that rs >= rt but we accept both. See also bnec bnvc $0, $0, 4 # CHECK: bnvc $zero, $zero, 4 # encoding: [0x60,0x00,0x00,0x01] bnvc $2, $0, 4 # CHECK: bnvc $2, $zero, 4 # encoding: [0x60,0x40,0x00,0x01] @@ -56,47 +63,49 @@ bovc $0, $0, 4 # CHECK: bovc $zero, $zero, 4 # encoding: [0x20,0x00,0x00,0x01] bovc $2, $0, 4 # CHECK: bovc $2, $zero, 4 # encoding: [0x20,0x40,0x00,0x01] bovc $4, $2, 4 # CHECK: bovc $4, $2, 4 # encoding: [0x20,0x82,0x00,0x01] - cmp.f.s $f2,$f3,$f4 # CHECK: cmp.f.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80] - cmp.f.d $f2,$f3,$f4 # CHECK: cmp.f.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x25] + cmp.af.s $f2,$f3,$f4 # CHECK: cmp.af.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80] + cmp.af.d $f2,$f3,$f4 # CHECK: cmp.af.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80] cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81] cmp.un.d $f2,$f3,$f4 # CHECK: cmp.un.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x81] cmp.eq.s $f2,$f3,$f4 # CHECK: cmp.eq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x82] cmp.eq.d $f2,$f3,$f4 # CHECK: cmp.eq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x82] cmp.ueq.s $f2,$f3,$f4 # CHECK: cmp.ueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x83] cmp.ueq.d $f2,$f3,$f4 # CHECK: cmp.ueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x83] - cmp.olt.s $f2,$f3,$f4 # CHECK: cmp.olt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x84] - cmp.olt.d $f2,$f3,$f4 # CHECK: cmp.olt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x84] + cmp.lt.s $f2,$f3,$f4 # CHECK: cmp.lt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x84] + cmp.lt.d $f2,$f3,$f4 # CHECK: cmp.lt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x84] cmp.ult.s $f2,$f3,$f4 # CHECK: cmp.ult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x85] cmp.ult.d $f2,$f3,$f4 # CHECK: cmp.ult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x85] - cmp.ole.s $f2,$f3,$f4 # CHECK: cmp.ole.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x86] - cmp.ole.d $f2,$f3,$f4 # CHECK: cmp.ole.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x86] + cmp.le.s $f2,$f3,$f4 # CHECK: cmp.le.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x86] + cmp.le.d $f2,$f3,$f4 # CHECK: cmp.le.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x86] cmp.ule.s $f2,$f3,$f4 # CHECK: cmp.ule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x87] cmp.ule.d $f2,$f3,$f4 # CHECK: cmp.ule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x87] - cmp.sf.s $f2,$f3,$f4 # CHECK: cmp.sf.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x88] - cmp.sf.d $f2,$f3,$f4 # CHECK: cmp.sf.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x88] - cmp.ngle.s $f2,$f3,$f4 # CHECK: cmp.ngle.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x89] - cmp.ngle.d $f2,$f3,$f4 # CHECK: cmp.ngle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x89] + cmp.saf.s $f2,$f3,$f4 # CHECK: cmp.saf.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x88] + cmp.saf.d $f2,$f3,$f4 # CHECK: cmp.saf.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x88] + cmp.sun.s $f2,$f3,$f4 # CHECK: cmp.sun.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x89] + cmp.sun.d $f2,$f3,$f4 # CHECK: cmp.sun.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x89] cmp.seq.s $f2,$f3,$f4 # CHECK: cmp.seq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8a] cmp.seq.d $f2,$f3,$f4 # CHECK: cmp.seq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8a] - cmp.ngl.s $f2,$f3,$f4 # CHECK: cmp.ngl.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8b] - cmp.ngl.d $f2,$f3,$f4 # CHECK: cmp.ngl.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8b] - cmp.lt.s $f2,$f3,$f4 # CHECK: cmp.lt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8c] - cmp.lt.d $f2,$f3,$f4 # CHECK: cmp.lt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8c] - cmp.nge.s $f2,$f3,$f4 # CHECK: cmp.nge.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8d] - cmp.nge.d $f2,$f3,$f4 # CHECK: cmp.nge.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8d] - cmp.le.s $f2,$f3,$f4 # CHECK: cmp.le.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8e] - cmp.le.d $f2,$f3,$f4 # CHECK: cmp.le.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e] - cmp.ngt.s $f2,$f3,$f4 # CHECK: cmp.ngt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f] - cmp.ngt.d $f2,$f3,$f4 # CHECK: cmp.ngt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f] + cmp.sueq.s $f2,$f3,$f4 # CHECK: cmp.sueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8b] + cmp.sueq.d $f2,$f3,$f4 # CHECK: cmp.sueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8b] + cmp.slt.s $f2,$f3,$f4 # CHECK: cmp.slt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8c] + cmp.slt.d $f2,$f3,$f4 # CHECK: cmp.slt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8c] + cmp.sult.s $f2,$f3,$f4 # CHECK: cmp.sult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8d] + cmp.sult.d $f2,$f3,$f4 # CHECK: cmp.sult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8d] + cmp.sle.s $f2,$f3,$f4 # CHECK: cmp.sle.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8e] + cmp.sle.d $f2,$f3,$f4 # CHECK: cmp.sle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e] + cmp.sule.s $f2,$f3,$f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f] + cmp.sule.d $f2,$f3,$f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f] div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a] divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b] jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00] jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00] + lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5] lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43] lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43] mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb] -# mul $2,$3,$4 # CHECK-TODO: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98] + mul $2,$3,$4 # CHECK: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98] muh $2,$3,$4 # CHECK: muh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd8] mulu $2,$3,$4 # CHECK: mulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x99] muhu $2,$3,$4 # CHECK: muhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd9] @@ -104,6 +113,7 @@ maddf.d $f2,$f3,$f4 # CHECK: maddf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x98] msubf.s $f2,$f3,$f4 # CHECK: msubf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x99] msubf.d $f2,$f3,$f4 # CHECK: msubf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x99] + pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35] sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10] sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10] seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35] @@ -116,6 +126,7 @@ maxa.d $f0, $f2, $f4 # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f] mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e] mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e] + or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] seleqz.s $f0, $f2, $f4 # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14] seleqz.d $f0, $f2, $f4 # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14] selnez.s $f0, $f2, $f4 # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17] @@ -124,3 +135,20 @@ rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a] class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b] + jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x09] + jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] + jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] + ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43] + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7] + sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75] + swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30] + ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6] + sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] + ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e] + sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e] + sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] diff --git a/test/MC/Mips/mips4/invalid-mips32.s b/test/MC/Mips/mips4/invalid-mips32.s new file mode 100644 index 0000000..52dea02 --- /dev/null +++ b/test/MC/Mips/mips4/invalid-mips32.s @@ -0,0 +1,10 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips4 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + + sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips4/valid.s b/test/MC/Mips/mips4/valid.s index 811584e..949b91d 100644 --- a/test/MC/Mips/mips4/valid.s +++ b/test/MC/Mips/mips4/valid.s @@ -9,8 +9,21 @@ add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 + addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 and $s7,$v0,$12 + and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] + bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] + bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] + bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] + bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 @@ -32,7 +45,11 @@ cvt.w.d $f20,$f14 cvt.w.s $f20,$f24 dadd $s3,$at,$ra + dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] + dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,$s4,-27705 + daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] + daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddiu $k0,$s6,-4586 daddu $s3,$at,$ra ddiv $zero,$k0,$s3 @@ -64,8 +81,10 @@ dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] dsub $a3,$s6,$8 - dsubu $a1,$a1,$k0 - dsub $a3,$s6,$8 + dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] + dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] + dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] + dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] dsubu $a1,$a1,$k0 ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] eret @@ -77,7 +96,7 @@ lbu $8,30195($v1) ld $sp,-28645($s1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] ldl $24,-4167($24) ldr $14,-30358($s4) ldxc1 $f8,$s7($15) @@ -85,11 +104,11 @@ lhu $s3,-22851($v0) li $at,-29773 li $zero,-29889 - ll $v0,-7321($s2) - lld $zero,-14736($ra) + ll $v0,-7321($s2) # CHECK: ll $2, -7321($18) # encoding: [0xc2,0x42,0xe3,0x67] + lld $zero,-14736($ra) # CHECK: lld $zero, -14736($ra) # encoding: [0xd3,0xe0,0xc6,0x70] lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwl $s4,-4231($15) lwr $zero,-19147($gp) lwu $s3,-24086($v1) @@ -133,16 +152,18 @@ nop nor $a3,$zero,$a3 or $12,$s0,$sp + or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] + pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] round.l.d $f12,$f1 round.l.s $f25,$f5 round.w.d $f6,$f4 round.w.s $f27,$f28 sb $s6,-19857($14) - sc $15,18904($s3) - scd $15,-8243($sp) + sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] + scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd] sd $12,5835($10) sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdl $a3,-20961($s8) sdr $11,-20423($12) sdxc1 $f11,$10($14) @@ -173,10 +194,11 @@ subu $sp,$s6,$s6 sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swl $15,13694($s3) swr $s1,-26590($14) swxc1 $f19,$12($k0) + sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] teqi $s5,-17504 tgei $s1,5025 tgeiu $sp,-28621 diff --git a/test/MC/Mips/mips5/invalid-mips32.s b/test/MC/Mips/mips5/invalid-mips32.s new file mode 100644 index 0000000..2e2c8da --- /dev/null +++ b/test/MC/Mips/mips5/invalid-mips32.s @@ -0,0 +1,10 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips5 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + + sync 0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips5/invalid-mips64.s b/test/MC/Mips/mips5/invalid-mips64.s index 19d64dc..0a15da8 100644 --- a/test/MC/Mips/mips5/invalid-mips64.s +++ b/test/MC/Mips/mips5/invalid-mips64.s @@ -10,6 +10,9 @@ dclo $s2,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dclz $s0,$25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + jr.hb $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + jalr.hb $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + jalr.hb $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips5/valid.s b/test/MC/Mips/mips5/valid.s index 19aad05..3afdee1 100644 --- a/test/MC/Mips/mips5/valid.s +++ b/test/MC/Mips/mips5/valid.s @@ -9,8 +9,21 @@ add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 + addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 and $s7,$v0,$12 + and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] + bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] + bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] + bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] + bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 @@ -32,7 +45,11 @@ cvt.w.d $f20,$f14 cvt.w.s $f20,$f24 dadd $s3,$at,$ra + dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] + dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,$s4,-27705 + daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] + daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddiu $k0,$s6,-4586 daddu $s3,$at,$ra ddiv $zero,$k0,$s3 @@ -64,8 +81,10 @@ dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] dsub $a3,$s6,$8 - dsubu $a1,$a1,$k0 - dsub $a3,$s6,$8 + dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] + dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] + dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] + dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] dsubu $a1,$a1,$k0 ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] eret @@ -77,7 +96,7 @@ lbu $8,30195($v1) ld $sp,-28645($s1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] ldl $24,-4167($24) ldr $14,-30358($s4) ldxc1 $f8,$s7($15) @@ -85,12 +104,12 @@ lhu $s3,-22851($v0) li $at,-29773 li $zero,-29889 - ll $v0,-7321($s2) - lld $zero,-14736($ra) + ll $v0,-7321($s2) # CHECK: ll $2, -7321($18) # encoding: [0xc2,0x42,0xe3,0x67] + lld $zero,-14736($ra) # CHECK: lld $zero, -14736($ra) # encoding: [0xd3,0xe0,0xc6,0x70] luxc1 $f19,$s6($s5) lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwl $s4,-4231($15) lwr $zero,-19147($gp) lwu $s3,-24086($v1) @@ -134,16 +153,18 @@ nop nor $a3,$zero,$a3 or $12,$s0,$sp + or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] + pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] round.l.d $f12,$f1 round.l.s $f25,$f5 round.w.d $f6,$f4 round.w.s $f27,$f28 sb $s6,-19857($14) - sc $15,18904($s3) - scd $15,-8243($sp) + sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] + scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd] sd $12,5835($10) sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdl $a3,-20961($s8) sdr $11,-20423($12) sdxc1 $f11,$10($14) @@ -175,10 +196,11 @@ suxc1 $f12,$k1($13) sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swl $15,13694($s3) swr $s1,-26590($14) swxc1 $f19,$12($k0) + sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] teqi $s5,-17504 tgei $s1,5025 tgeiu $sp,-28621 diff --git a/test/MC/Mips/mips64-expansions.s b/test/MC/Mips/mips64-expansions.s new file mode 100644 index 0000000..0efdd2f --- /dev/null +++ b/test/MC/Mips/mips64-expansions.s @@ -0,0 +1,209 @@ +# RUN: llvm-mc %s -triple=mips64el-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s +# +# The GNU assembler implements 'dli' and 'dla' variants on 'li' and 'la' +# supporting double-word lengths. Test that not only are they present, bu +# that they also seem to handle 64-bit values. +# +# XXXRW: Does using powers of ten make me a bad person? +# +# CHECK: ori $12, $zero, 1 # encoding: [0x01,0x00,0x0c,0x34] +# CHECK: ori $12, $zero, 10 # encoding: [0x0a,0x00,0x0c,0x34] +# CHECK: ori $12, $zero, 100 # encoding: [0x64,0x00,0x0c,0x34] +# CHECK: ori $12, $zero, 1000 # encoding: [0xe8,0x03,0x0c,0x34] +# CHECK: ori $12, $zero, 10000 # encoding: [0x10,0x27,0x0c,0x34] +# CHECK: lui $12, 1 # encoding: [0x01,0x00,0x0c,0x3c] +# CHECK: ori $12, $12, 34464 # encoding: [0xa0,0x86,0x8c,0x35] +# CHECK: lui $12, 15 # encoding: [0x0f,0x00,0x0c,0x3c] +# CHECK: ori $12, $12, 16960 # encoding: [0x40,0x42,0x8c,0x35] +# CHECK: lui $12, 152 # encoding: [0x98,0x00,0x0c,0x3c] +# CHECK: ori $12, $12, 38528 # encoding: [0x80,0x96,0x8c,0x35] +# CHECK: lui $12, 1525 # encoding: [0xf5,0x05,0x0c,0x3c] +# CHECK: ori $12, $12, 57600 # encoding: [0x00,0xe1,0x8c,0x35] +# CHECK: lui $12, 15258 # encoding: [0x9a,0x3b,0x0c,0x3c] +# CHECK: ori $12, $12, 51712 # encoding: [0x00,0xca,0x8c,0x35] +# CHECK: lui $12, 2 # encoding: [0x02,0x00,0x0c,0x3c] +# CHECK: ori $12, $12, 21515 # encoding: [0x0b,0x54,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 58368 # encoding: [0x00,0xe4,0x8c,0x35] +# CHECK: lui $12, 23 # encoding: [0x17,0x00,0x0c,0x3c] +# CHECK: ori $12, $12, 18550 # encoding: [0x76,0x48,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 59392 # encoding: [0x00,0xe8,0x8c,0x35] +# CHECK: lui $12, 232 # encoding: [0xe8,0x00,0x0c,0x3c] +# CHECK: ori $12, $12, 54437 # encoding: [0xa5,0xd4,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 4096 # encoding: [0x00,0x10,0x8c,0x35] +# CHECK: lui $12, 2328 # encoding: [0x18,0x09,0x0c,0x3c] +# CHECK: ori $12, $12, 20082 # encoding: [0x72,0x4e,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 40960 # encoding: [0x00,0xa0,0x8c,0x35] +# CHECK: lui $12, 23283 # encoding: [0xf3,0x5a,0x0c,0x3c] +# CHECK: ori $12, $12, 4218 # encoding: [0x7a,0x10,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 16384 # encoding: [0x00,0x40,0x8c,0x35] +# CHECK: lui $12, 3 # encoding: [0x03,0x00,0x0c,0x3c] +# CHECK: ori $12, $12, 36222 # encoding: [0x7e,0x8d,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 42182 # encoding: [0xc6,0xa4,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 32768 # encoding: [0x00,0x80,0x8c,0x35] +# CHECK: lui $12, 35 # encoding: [0x23,0x00,0x0c,0x3c] +# CHECK: ori $12, $12, 34546 # encoding: [0xf2,0x86,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 28609 # encoding: [0xc1,0x6f,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35] +# CHECK: lui $12, 355 # encoding: [0x63,0x01,0x0c,0x3c] +# CHECK: ori $12, $12, 17784 # encoding: [0x78,0x45,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 23946 # encoding: [0x8a,0x5d,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35] +# CHECK: lui $12, 3552 # encoding: [0xe0,0x0d,0x0c,0x3c] +# CHECK: ori $12, $12, 46771 # encoding: [0xb3,0xb6,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 42852 # encoding: [0x64,0xa7,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35] +# CHECK: lui $12, 35527 # encoding: [0xc7,0x8a,0x0c,0x3c] +# CHECK: ori $12, $12, 8964 # encoding: [0x04,0x23,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 35304 # encoding: [0xe8,0x89,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35] +# CHECK: addiu $12, $zero, -1 # encoding: [0xff,0xff,0x0c,0x24] +# CHECK: addiu $12, $zero, -10 # encoding: [0xf6,0xff,0x0c,0x24] +# CHECK: addiu $12, $zero, -100 # encoding: [0x9c,0xff,0x0c,0x24] +# CHECK: addiu $12, $zero, -1000 # encoding: [0x18,0xfc,0x0c,0x24] +# CHECK: addiu $12, $zero, -10000 # encoding: [0xf0,0xd8,0x0c,0x24] +# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c] +# CHECK: ori $12, $12, 65535 # encoding: [0xff,0xff,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 65534 # encoding: [0xfe,0xff,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 31072 # encoding: [0x60,0x79,0x8c,0x35] +# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c] +# CHECK: ori $12, $12, 65535 # encoding: [0xff,0xff,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 65520 # encoding: [0xf0,0xff,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 48576 # encoding: [0xc0,0xbd,0x8c,0x35] +# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c] +# CHECK: ori $12, $12, 65535 # encoding: [0xff,0xff,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 65383 # encoding: [0x67,0xff,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 27008 # encoding: [0x80,0x69,0x8c,0x35] +# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c] +# CHECK: ori $12, $12, 65535 # encoding: [0xff,0xff,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 64010 # encoding: [0x0a,0xfa,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 7936 # encoding: [0x00,0x1f,0x8c,0x35] +# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c] +# CHECK: ori $12, $12, 65535 # encoding: [0xff,0xff,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 50277 # encoding: [0x65,0xc4,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 13824 # encoding: [0x00,0x36,0x8c,0x35] +# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c] +# CHECK: ori $12, $12, 65533 # encoding: [0xfd,0xff,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 44020 # encoding: [0xf4,0xab,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 7168 # encoding: [0x00,0x1c,0x8c,0x35] +# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c] +# CHECK: ori $12, $12, 65512 # encoding: [0xe8,0xff,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 46985 # encoding: [0x89,0xb7,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 6144 # encoding: [0x00,0x18,0x8c,0x35] +# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c] +# CHECK: ori $12, $12, 65303 # encoding: [0x17,0xff,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 11098 # encoding: [0x5a,0x2b,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 61440 # encoding: [0x00,0xf0,0x8c,0x35] +# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c] +# CHECK: ori $12, $12, 63207 # encoding: [0xe7,0xf6,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 45453 # encoding: [0x8d,0xb1,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 24576 # encoding: [0x00,0x60,0x8c,0x35] +# CHECK: lui $12, 65535 # encoding: [0xff,0xff,0x0c,0x3c] +# CHECK: ori $12, $12, 42252 # encoding: [0x0c,0xa5,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 61317 # encoding: [0x85,0xef,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 49152 # encoding: [0x00,0xc0,0x8c,0x35] +# CHECK: lui $12, 65532 # encoding: [0xfc,0xff,0x0c,0x3c] +# CHECK: ori $12, $12, 29313 # encoding: [0x81,0x72,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 23353 # encoding: [0x39,0x5b,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 32768 # encoding: [0x00,0x80,0x8c,0x35] +# CHECK: lui $12, 65500 # encoding: [0xdc,0xff,0x0c,0x3c] +# CHECK: ori $12, $12, 30989 # encoding: [0x0d,0x79,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 36927 # encoding: [0x3f,0x90,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35] +# CHECK: lui $12, 65180 # encoding: [0x9c,0xfe,0x0c,0x3c] +# CHECK: ori $12, $12, 47751 # encoding: [0x87,0xba,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 41590 # encoding: [0x76,0xa2,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35] +# CHECK: lui $12, 61983 # encoding: [0x1f,0xf2,0x0c,0x3c] +# CHECK: ori $12, $12, 18764 # encoding: [0x4c,0x49,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 22684 # encoding: [0x9c,0x58,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35] +# CHECK: lui $12, 30008 # encoding: [0x38,0x75,0x0c,0x3c] +# CHECK: ori $12, $12, 56571 # encoding: [0xfb,0xdc,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 30232 # encoding: [0x18,0x76,0x8c,0x35] +# CHECK: dsll $12, $12, 16 # encoding: [0x38,0x64,0x0c,0x00] +# CHECK: ori $12, $12, 0 # encoding: [0x00,0x00,0x8c,0x35] + + dli $t0, 1 + dli $t0, 10 + dli $t0, 100 + dli $t0, 1000 + dli $t0, 10000 + dli $t0, 100000 + dli $t0, 1000000 + dli $t0, 10000000 + dli $t0, 100000000 + dli $t0, 1000000000 + dli $t0, 10000000000 + dli $t0, 100000000000 + dli $t0, 1000000000000 + dli $t0, 10000000000000 + dli $t0, 100000000000000 + dli $t0, 1000000000000000 + dli $t0, 10000000000000000 + dli $t0, 100000000000000000 + dli $t0, 1000000000000000000 + dli $t0, 10000000000000000000 + dli $t0, -1 + dli $t0, -10 + dli $t0, -100 + dli $t0, -1000 + dli $t0, -10000 + dli $t0, -100000 + dli $t0, -1000000 + dli $t0, -10000000 + dli $t0, -100000000 + dli $t0, -1000000000 + dli $t0, -10000000000 + dli $t0, -100000000000 + dli $t0, -1000000000000 + dli $t0, -10000000000000 + dli $t0, -100000000000000 + dli $t0, -1000000000000000 + dli $t0, -10000000000000000 + dli $t0, -100000000000000000 + dli $t0, -1000000000000000000 + dli $t0, -10000000000000000000 diff --git a/test/MC/Mips/mips64/abiflags.s b/test/MC/Mips/mips64/abiflags.s new file mode 100644 index 0000000..557e32a --- /dev/null +++ b/test/MC/Mips/mips64/abiflags.s @@ -0,0 +1,37 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips64 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips64 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ + +# CHECK-ASM: .module fp=64 + +# Checking if the Mips.abiflags were correctly emitted. +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Offset: 0x50 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 0 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00004001 02020001 00000000 00000000 |..@.............| +# CHECK-OBJ: 0010: 00000000 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ: } + + .module fp=64 + +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/mips64/valid.s b/test/MC/Mips/mips64/valid.s index b9e1002..1bd057d 100644 --- a/test/MC/Mips/mips64/valid.s +++ b/test/MC/Mips/mips64/valid.s @@ -9,8 +9,21 @@ add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 + addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 and $s7,$v0,$12 + and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] + bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] + bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] + bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] + bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 @@ -20,8 +33,8 @@ ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 - clo $11,$a1 - clz $sp,$gp + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] ctc1 $a2,$26 cvt.d.l $f4,$f16 cvt.d.s $f22,$f28 @@ -34,11 +47,15 @@ cvt.w.d $f20,$f14 cvt.w.s $f20,$f24 dadd $s3,$at,$ra + dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] + dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,$s4,-27705 + daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] + daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddiu $k0,$s6,-4586 daddu $s3,$at,$ra - dclo $s2,$a2 - dclz $s0,$25 + dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25] + dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24] deret ddiv $zero,$k0,$s3 ddivu $zero,$s0,$s1 @@ -69,8 +86,10 @@ dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] dsub $a3,$s6,$8 - dsubu $a1,$a1,$k0 - dsub $a3,$s6,$8 + dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] + dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] + dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] + dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] dsubu $a1,$a1,$k0 ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] eret @@ -82,7 +101,7 @@ lbu $8,30195($v1) ld $sp,-28645($s1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] ldl $24,-4167($24) ldr $14,-30358($s4) ldxc1 $f8,$s7($15) @@ -90,12 +109,12 @@ lhu $s3,-22851($v0) li $at,-29773 li $zero,-29889 - ll $v0,-7321($s2) - lld $zero,-14736($ra) + ll $v0,-7321($s2) # CHECK: ll $2, -7321($18) # encoding: [0xc2,0x42,0xe3,0x67] + lld $zero,-14736($ra) # CHECK: lld $zero, -14736($ra) # encoding: [0xd3,0xe0,0xc6,0x70] luxc1 $f19,$s6($s5) lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwl $s4,-4231($15) lwr $zero,-19147($gp) lwu $s3,-24086($v1) @@ -148,16 +167,20 @@ nop nor $a3,$zero,$a3 or $12,$s0,$sp + or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] + pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] round.l.d $f12,$f1 round.l.s $f25,$f5 round.w.d $f6,$f4 round.w.s $f27,$f28 sb $s6,-19857($14) - sc $15,18904($s3) - scd $15,-8243($sp) + sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] + scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd] + sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f] + sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] sd $12,5835($10) sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdl $a3,-20961($s8) sdr $11,-20423($12) sdxc1 $f11,$10($14) @@ -189,10 +212,12 @@ suxc1 $f12,$k1($13) sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swl $15,13694($s3) swr $s1,-26590($14) swxc1 $f19,$12($k0) + sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] teqi $s5,-17504 tgei $s1,5025 tgeiu $sp,-28621 diff --git a/test/MC/Mips/mips64r2/abi-bad.s b/test/MC/Mips/mips64r2/abi-bad.s new file mode 100644 index 0000000..31d13ab --- /dev/null +++ b/test/MC/Mips/mips64r2/abi-bad.s @@ -0,0 +1,9 @@ +# RUN: not llvm-mc %s -triple mips-unknown-unknown -mcpu=mips64r2 2>&1 | FileCheck %s +# CHECK: .text + + + + .set fp=xx +# CHECK : error: 'set fp=xx'option requires O32 ABI +# CHECK : .set fp=xx +# CHECK : ^ diff --git a/test/MC/Mips/mips64r2/abiflags.s b/test/MC/Mips/mips64r2/abiflags.s new file mode 100644 index 0000000..aa76dee --- /dev/null +++ b/test/MC/Mips/mips64r2/abiflags.s @@ -0,0 +1,37 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips64r2 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips64r2 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ + +# CHECK-ASM: .module fp=64 + +# Checking if the Mips.abiflags were correctly emitted. +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Offset: 0x50 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 0 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00004002 02020001 00000000 00000000 |..@.............| +# CHECK-OBJ: 0010: 00000000 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ: } + + .module fp=64 + +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/mips64r2/invalid.s b/test/MC/Mips/mips64r2/invalid.s new file mode 100644 index 0000000..f53cfff --- /dev/null +++ b/test/MC/Mips/mips64r2/invalid.s @@ -0,0 +1,10 @@ +# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g. +# invalid set of operands or operand's restrictions not met). + +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r2 2>%t1 +# RUN: FileCheck %s < %t1 -check-prefix=ASM + + .text + .set noreorder + jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different diff --git a/test/MC/Mips/mips64r2/valid.s b/test/MC/Mips/mips64r2/valid.s index 252589d..7a2244a 100644 --- a/test/MC/Mips/mips64r2/valid.s +++ b/test/MC/Mips/mips64r2/valid.s @@ -9,8 +9,21 @@ add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 + addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 and $s7,$v0,$12 + and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] + bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] + bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] + bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] + bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 @@ -20,8 +33,8 @@ ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 - clo $11,$a1 - clz $sp,$gp + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] ctc1 $a2,$26 cvt.d.l $f4,$f16 cvt.d.s $f22,$f28 @@ -34,11 +47,15 @@ cvt.w.d $f20,$f14 cvt.w.s $f20,$f24 dadd $s3,$at,$ra + dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] + dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddi $sp,$s4,-27705 + daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] + daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddiu $k0,$s6,-4586 daddu $s3,$at,$ra - dclo $s2,$a2 - dclz $s0,$25 + dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25] + dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24] deret di $s8 ddiv $zero,$k0,$s3 @@ -77,8 +94,12 @@ dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] dsub $a3,$s6,$8 - dsubu $a1,$a1,$k0 dsub $a3,$s6,$8 + dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] + dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] + dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] + dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] + dsubu $a1,$a1,$k0 dsubu $a1,$a1,$k0 ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] ei $14 @@ -87,11 +108,14 @@ floor.l.s $f12,$f5 floor.w.d $f14,$f11 floor.w.s $f8,$f9 + jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] + jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] + jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] lb $24,-14515($10) lbu $8,30195($v1) ld $sp,-28645($s1) ldc1 $f11,16391($s0) - ldc2 $8,-21181($at) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] ldl $24,-4167($24) ldr $14,-30358($s4) ldxc1 $f8,$s7($15) @@ -99,12 +123,12 @@ lhu $s3,-22851($v0) li $at,-29773 li $zero,-29889 - ll $v0,-7321($s2) - lld $zero,-14736($ra) + ll $v0,-7321($s2) # CHECK: ll $2, -7321($18) # encoding: [0xc2,0x42,0xe3,0x67] + lld $zero,-14736($ra) # CHECK: lld $zero, -14736($ra) # encoding: [0xd3,0xe0,0xc6,0x70] luxc1 $f19,$s6($s5) lw $8,5674($a1) lwc1 $f16,10225($k0) - lwc2 $18,-841($a2) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] lwl $s4,-4231($15) lwr $zero,-19147($gp) lwu $s3,-24086($v1) @@ -163,7 +187,9 @@ nop nor $a3,$zero,$a3 or $12,$s0,$sp + or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] + pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] rdhwr $sp,$11 rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] @@ -173,11 +199,13 @@ round.w.d $f6,$f4 round.w.s $f27,$f28 sb $s6,-19857($14) - sc $15,18904($s3) - scd $15,-8243($sp) + sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] + scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd] + sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f] + sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] sd $12,5835($10) sdc1 $f31,30574($13) - sdc2 $20,23157($s2) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] sdl $a3,-20961($s8) sdr $11,-20423($12) sdxc1 $f11,$10($14) @@ -211,10 +239,12 @@ suxc1 $f12,$k1($13) sw $ra,-10160($sp) swc1 $f6,-8465($24) - swc2 $25,24880($s0) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] swl $15,13694($s3) swr $s1,-26590($14) swxc1 $f19,$12($k0) + sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] teqi $s5,-17504 tgei $s1,5025 tgeiu $sp,-28621 diff --git a/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s b/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s index f7949bb..e914c89 100644 --- a/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s +++ b/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s @@ -5,6 +5,8 @@ # RUN: FileCheck %s < %t1 .set noat + bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips64r6/invalid-mips1.s b/test/MC/Mips/mips64r6/invalid-mips1.s index 1225005..6efd8f4 100644 --- a/test/MC/Mips/mips64r6/invalid-mips1.s +++ b/test/MC/Mips/mips64r6/invalid-mips1.s @@ -6,3 +6,22 @@ .set noat addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + c.sf.d $f30,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + c.sf.s $f14,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthi $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtlo $25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtlo $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mult $sp,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mult $sp,$v0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled +# div has been re-encoded. See valid.s +# divu has been re-encoded. See valid.s diff --git a/test/MC/Mips/mips64r6/invalid-mips2.s b/test/MC/Mips/mips64r6/invalid-mips2.s index 0638e78..8a5c50c 100644 --- a/test/MC/Mips/mips64r6/invalid-mips2.s +++ b/test/MC/Mips/mips64r6/invalid-mips2.s @@ -6,9 +6,24 @@ .set noat addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthi $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtlo $25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtlo $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mult $sp,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mult $sp,$v0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tlti $14,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tnei $12,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled +# div has been re-encoded. See valid.s +# divu has been re-encoded. See valid.s diff --git a/test/MC/Mips/mips64r6/invalid-mips3.s b/test/MC/Mips/mips64r6/invalid-mips3.s index 0638e78..322dabd 100644 --- a/test/MC/Mips/mips64r6/invalid-mips3.s +++ b/test/MC/Mips/mips64r6/invalid-mips3.s @@ -6,9 +6,28 @@ .set noat addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthi $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtlo $25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtlo $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mult $sp,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mult $sp,$v0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tlti $14,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tnei $12,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled +# ddiv has been re-encoded. See valid.s +# ddivu has been re-encoded. See valid.s +# div has been re-encoded. See valid.s +# divu has been re-encoded. See valid.s diff --git a/test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s b/test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s new file mode 100644 index 0000000..cc85f18 --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s @@ -0,0 +1,20 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + bc1fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips64r6/invalid-mips4-wrong-error.s b/test/MC/Mips/mips64r6/invalid-mips4-wrong-error.s new file mode 100644 index 0000000..f3131a9 --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips4-wrong-error.s @@ -0,0 +1,21 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + beql $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bgezall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bgezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bgtzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + blezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bltzall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bltzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bnel $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips64r6/invalid-mips4.s b/test/MC/Mips/mips64r6/invalid-mips4.s new file mode 100644 index 0000000..706db27 --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips4.s @@ -0,0 +1,14 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s b/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s index 6b980e6..4fc94e2 100644 --- a/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s +++ b/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s @@ -1,4 +1,4 @@ -# Instructions that are invalid +# Instructions that are invalid but currently emit the wrong error message. # # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ # RUN: 2>%t1 @@ -8,6 +8,10 @@ abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction alnv.ps $f12,$f18,$f30,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any2f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any2t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any4f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any4t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction diff --git a/test/MC/Mips/mips64r6/invalid-mips5.s b/test/MC/Mips/mips64r6/invalid-mips5.s new file mode 100644 index 0000000..e7fd99a --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips5.s @@ -0,0 +1,12 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + suxc1 $f12,$k1($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64r6/invalid-mips64.s b/test/MC/Mips/mips64r6/invalid-mips64.s new file mode 100644 index 0000000..51e5708 --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid-mips64.s @@ -0,0 +1,54 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r6 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddi $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dadd $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dadd $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmult $s7,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubi $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsub $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsub $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + jalx 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mthi $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtlo $25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mtlo $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mult $sp,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mult $sp,$v0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + multu $9,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlti $14,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tnei $12,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled +# ddiv has been re-encoded. See valid.s +# ddivu has been re-encoded. See valid.s +# div has been re-encoded. See valid.s +# divu has been re-encoded. See valid.s diff --git a/test/MC/Mips/mips64r6/invalid.s b/test/MC/Mips/mips64r6/invalid.s new file mode 100644 index 0000000..1b01827 --- /dev/null +++ b/test/MC/Mips/mips64r6/invalid.s @@ -0,0 +1,12 @@ +# Instructions that are available for the current ISA but should be rejected by +# the assembler (e.g. invalid set of operands or operand's restrictions not met). + +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r6 2>%t1 +# RUN: FileCheck %s < %t1 -check-prefix=ASM + + .text + .set noreorder + .set noat + jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64r6/relocations.s b/test/MC/Mips/mips64r6/relocations.s index db84715..651ebfb 100644 --- a/test/MC/Mips/mips64r6/relocations.s +++ b/test/MC/Mips/mips64r6/relocations.s @@ -5,7 +5,10 @@ #------------------------------------------------------------------------------ # Check that the assembler can handle the documented syntax for fixups. #------------------------------------------------------------------------------ -# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A] +# CHECK-FIXUP: addiupc $2, bar # encoding: [0xec,0b01000AAA,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 +# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A] # CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: value: bar, kind: fixup_Mips_PC16 # CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A] @@ -31,20 +34,35 @@ # CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: value: bar@PCREL_LO16, # CHECK-FIXUP: kind: fixup_MIPS_PCLO16 +# CHECK-FIXUP: ldpc $2, bar # encoding: [0xec,0b010110AA,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, +# CHECK-FIXUP: kind: fixup_Mips_PC18_S3 +# CHECK-FIXUP: lwpc $2, bar # encoding: [0xec,0b01001AAA,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 +# CHECK-FIXUP: lwupc $2, bar # encoding: [0xec,0b01010AAA,A,A] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2 #------------------------------------------------------------------------------ # Check that the appropriate relocations were created. #------------------------------------------------------------------------------ # CHECK-ELF: Relocations [ -# CHECK-ELF: 0x0 R_MIPS_PC16 bar 0x0 +# CHECK-ELF: 0x0 R_MIPS_PC19_S2 bar 0x0 # CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0 -# CHECK-ELF: 0x8 R_MIPS_PC21_S2 bar 0x0 +# CHECK-ELF: 0x8 R_MIPS_PC16 bar 0x0 # CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0 -# CHECK-ELF: 0x10 R_MIPS_PC26_S2 bar 0x0 +# CHECK-ELF: 0x10 R_MIPS_PC21_S2 bar 0x0 # CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0 -# CHECK-ELF: 0x18 R_MIPS_PCHI16 bar 0x0 -# CHECK-ELF: 0x1C R_MIPS_PCLO16 bar 0x0 +# CHECK-ELF: 0x18 R_MIPS_PC26_S2 bar 0x0 +# CHECK-ELF: 0x1C R_MIPS_PCHI16 bar 0x0 +# CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0 +# CHECK-ELF: 0x24 R_MIPS_PC18_S3 bar 0x0 +# CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0 +# CHECK-ELF: 0x2C R_MIPS_PC19_S2 bar 0x0 # CHECK-ELF: ] + addiupc $2,bar beqc $5, $6, bar bnec $5, $6, bar beqzc $9, bar @@ -53,3 +71,6 @@ bc bar aluipc $2, %pcrel_hi(bar) addiu $2, $2, %pcrel_lo(bar) + ldpc $2,bar + lwpc $2,bar + lwupc $2,bar diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s index efdfc7f..34c1dac 100644 --- a/test/MC/Mips/mips64r6/valid.s +++ b/test/MC/Mips/mips64r6/valid.s @@ -10,15 +10,18 @@ # rs > rt # appropriately for each branch instruction # -# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 | FileCheck %s +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 2> %t0 | FileCheck %s +# RUN: FileCheck %s -check-prefix=WARNING < %t0 .set noat # FIXME: Add the instructions carried forward from older ISA's + and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19] align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0] aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9] auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0xec,0x7e,0xff,0xff] + bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] balc 14572256 # CHECK: balc 14572256 # encoding: [0xe8,0x37,0x96,0xb8] bc 14572256 # CHECK: bc 14572256 # encoding: [0xc8,0x37,0x96,0xb8] bc1eqz $f0,4 # CHECK: bc1eqz $f0, 4 # encoding: [0x45,0x20,0x00,0x01] @@ -38,6 +41,8 @@ bnec $5, $6, 256 # CHECK: bnec $5, $6, 256 # encoding: [0x60,0xa6,0x00,0x40] bnezalc $2, 1332 # CHECK: bnezalc $2, 1332 # encoding: [0x60,0x02,0x01,0x4d] beqzc $5, 72256 # CHECK: beqzc $5, 72256 # encoding: [0xd8,0xa0,0x46,0x90] + bgec $2, $3, 256 # CHECK: bgec $2, $3, 256 # encoding: [0x58,0x43,0x00,0x40] + bgeuc $2, $3, 256 # CHECK: bgeuc $2, $3, 256 # encoding: [0x18,0x43,0x00,0x40] bgezalc $2, 1332 # CHECK: bgezalc $2, 1332 # encoding: [0x18,0x42,0x01,0x4d] bnezc $5, 72256 # CHECK: bnezc $5, 72256 # encoding: [0xf8,0xa0,0x46,0x90] bltzc $5, 256 # CHECK: bltzc $5, 256 # encoding: [0x5c,0xa5,0x00,0x40] @@ -48,6 +53,8 @@ bgtzc $5, 256 # CHECK: bgtzc $5, 256 # encoding: [0x5c,0x05,0x00,0x40] bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x20] blezalc $2, 1332 # CHECK: blezalc $2, 1332 # encoding: [0x18,0x02,0x01,0x4d] + bltc $5, $6, 256 # CHECK: bltc $5, $6, 256 # encoding: [0x5c,0xa6,0x00,0x40] + bltuc $5, $6, 256 # CHECK: bltuc $5, $6, 256 # encoding: [0x1c,0xa6,0x00,0x40] # bnvc requires that rs >= rt but we accept both. See also bnec bnvc $0, $0, 4 # CHECK: bnvc $zero, $zero, 4 # encoding: [0x60,0x00,0x00,0x01] bnvc $2, $0, 4 # CHECK: bnvc $2, $zero, 4 # encoding: [0x60,0x40,0x00,0x01] @@ -56,38 +63,39 @@ bovc $0, $0, 4 # CHECK: bovc $zero, $zero, 4 # encoding: [0x20,0x00,0x00,0x01] bovc $2, $0, 4 # CHECK: bovc $2, $zero, 4 # encoding: [0x20,0x40,0x00,0x01] bovc $4, $2, 4 # CHECK: bovc $4, $2, 4 # encoding: [0x20,0x82,0x00,0x01] - cmp.f.s $f2,$f3,$f4 # CHECK: cmp.f.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80] - cmp.f.d $f2,$f3,$f4 # CHECK: cmp.f.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x25] + cmp.af.s $f2,$f3,$f4 # CHECK: cmp.af.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x80] + cmp.af.d $f2,$f3,$f4 # CHECK: cmp.af.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x80] cmp.un.s $f2,$f3,$f4 # CHECK: cmp.un.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x81] cmp.un.d $f2,$f3,$f4 # CHECK: cmp.un.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x81] cmp.eq.s $f2,$f3,$f4 # CHECK: cmp.eq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x82] cmp.eq.d $f2,$f3,$f4 # CHECK: cmp.eq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x82] cmp.ueq.s $f2,$f3,$f4 # CHECK: cmp.ueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x83] cmp.ueq.d $f2,$f3,$f4 # CHECK: cmp.ueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x83] - cmp.olt.s $f2,$f3,$f4 # CHECK: cmp.olt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x84] - cmp.olt.d $f2,$f3,$f4 # CHECK: cmp.olt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x84] + cmp.lt.s $f2,$f3,$f4 # CHECK: cmp.lt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x84] + cmp.lt.d $f2,$f3,$f4 # CHECK: cmp.lt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x84] cmp.ult.s $f2,$f3,$f4 # CHECK: cmp.ult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x85] cmp.ult.d $f2,$f3,$f4 # CHECK: cmp.ult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x85] - cmp.ole.s $f2,$f3,$f4 # CHECK: cmp.ole.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x86] - cmp.ole.d $f2,$f3,$f4 # CHECK: cmp.ole.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x86] + cmp.le.s $f2,$f3,$f4 # CHECK: cmp.le.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x86] + cmp.le.d $f2,$f3,$f4 # CHECK: cmp.le.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x86] cmp.ule.s $f2,$f3,$f4 # CHECK: cmp.ule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x87] cmp.ule.d $f2,$f3,$f4 # CHECK: cmp.ule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x87] - cmp.sf.s $f2,$f3,$f4 # CHECK: cmp.sf.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x88] - cmp.sf.d $f2,$f3,$f4 # CHECK: cmp.sf.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x88] - cmp.ngle.s $f2,$f3,$f4 # CHECK: cmp.ngle.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x89] - cmp.ngle.d $f2,$f3,$f4 # CHECK: cmp.ngle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x89] + cmp.saf.s $f2,$f3,$f4 # CHECK: cmp.saf.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x88] + cmp.saf.d $f2,$f3,$f4 # CHECK: cmp.saf.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x88] + cmp.sun.s $f2,$f3,$f4 # CHECK: cmp.sun.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x89] + cmp.sun.d $f2,$f3,$f4 # CHECK: cmp.sun.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x89] cmp.seq.s $f2,$f3,$f4 # CHECK: cmp.seq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8a] cmp.seq.d $f2,$f3,$f4 # CHECK: cmp.seq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8a] - cmp.ngl.s $f2,$f3,$f4 # CHECK: cmp.ngl.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8b] - cmp.ngl.d $f2,$f3,$f4 # CHECK: cmp.ngl.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8b] - cmp.lt.s $f2,$f3,$f4 # CHECK: cmp.lt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8c] - cmp.lt.d $f2,$f3,$f4 # CHECK: cmp.lt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8c] - cmp.nge.s $f2,$f3,$f4 # CHECK: cmp.nge.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8d] - cmp.nge.d $f2,$f3,$f4 # CHECK: cmp.nge.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8d] - cmp.le.s $f2,$f3,$f4 # CHECK: cmp.le.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8e] - cmp.le.d $f2,$f3,$f4 # CHECK: cmp.le.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e] - cmp.ngt.s $f2,$f3,$f4 # CHECK: cmp.ngt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f] - cmp.ngt.d $f2,$f3,$f4 # CHECK: cmp.ngt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f] + cmp.sueq.s $f2,$f3,$f4 # CHECK: cmp.sueq.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8b] + cmp.sueq.d $f2,$f3,$f4 # CHECK: cmp.sueq.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8b] + cmp.slt.s $f2,$f3,$f4 # CHECK: cmp.slt.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8c] + cmp.slt.d $f2,$f3,$f4 # CHECK: cmp.slt.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8c] + cmp.sult.s $f2,$f3,$f4 # CHECK: cmp.sult.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8d] + cmp.sult.d $f2,$f3,$f4 # CHECK: cmp.sult.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8d] + cmp.sle.s $f2,$f3,$f4 # CHECK: cmp.sle.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8e] + cmp.sle.d $f2,$f3,$f4 # CHECK: cmp.sle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e] + cmp.sule.s $f2,$f3,$f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f] + cmp.sule.d $f2,$f3,$f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f] dalign $4,$2,$3,5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64] daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34] dahi $3,0x5678 # CHECK: dahi $3, 22136 # encoding: [0x04,0x66,0x56,0x78] @@ -103,20 +111,24 @@ ddivu $2,$3,$4 # CHECK: ddivu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9f] dmod $2,$3,$4 # CHECK: dmod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xde] dmodu $2,$3,$4 # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf] + lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5] + dlsa $2, $3, $4, 3 # CHECK: dlsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xd5] + ldpc $2,123456 # CHECK: ldpc $2, 123456 # encoding: [0xec,0x58,0x3c,0x48] lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43] lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43] -# mul $2,$3,$4 # CHECK-TODO: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98] + mul $2,$3,$4 # CHECK: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98] muh $2,$3,$4 # CHECK: muh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd8] mulu $2,$3,$4 # CHECK: mulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x99] muhu $2,$3,$4 # CHECK: muhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd9] - dmul $2,$3,$4 # CHECK: dmul $2, $3, $4 # encoding: [0x00,0x64,0x10,0xb8] - dmuh $2,$3,$4 # CHECK: dmuh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xf8] - dmulu $2,$3,$4 # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xb9] - dmuhu $2,$3,$4 # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xf9] + dmul $2,$3,$4 # CHECK: dmul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9c] + dmuh $2,$3,$4 # CHECK: dmuh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdc] + dmulu $2,$3,$4 # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9d] + dmuhu $2,$3,$4 # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdd] maddf.s $f2,$f3,$f4 # CHECK: maddf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x98] maddf.d $f2,$f3,$f4 # CHECK: maddf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x98] msubf.s $f2,$f3,$f4 # CHECK: msubf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x99] msubf.d $f2,$f3,$f4 # CHECK: msubf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x99] + pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35] sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10] sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10] seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35] @@ -129,6 +141,7 @@ maxa.d $f0, $f2, $f4 # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f] mina.s $f0, $f2, $f4 # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e] mina.d $f0, $f2, $f4 # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e] + or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] seleqz.s $f0, $f2, $f4 # CHECK: seleqz.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x14] seleqz.d $f0, $f2, $f4 # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14] selnez.s $f0, $f2, $f4 # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17] @@ -137,3 +150,24 @@ rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a] class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b] class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9b] + jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x09] + jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] + jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] + ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding: [0x49,0xc8,0x0d,0x43] + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0x49,0x52,0x34,0xb7] + sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75] + swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30] + ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6] + lld $zero,112($ra) # CHECK: lld $zero, 112($ra) # encoding: [0x7f,0xe0,0x38,0x37] + sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] + scd $15,-51($sp) # CHECK: scd $15, -51($sp) # encoding: [0x7f,0xaf,0xe6,0xa7] + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] + dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x00,0xc0,0x90,0x53] + dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52] + ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS64r6 and is equivalent to a nop instruction + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e] + sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e] + sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] diff --git a/test/MC/Mips/mips_abi_flags_xx.s b/test/MC/Mips/mips_abi_flags_xx.s new file mode 100644 index 0000000..1d65e99 --- /dev/null +++ b/test/MC/Mips/mips_abi_flags_xx.s @@ -0,0 +1,37 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ + +# CHECK-ASM: .module fp=xx + +# Checking if the Mips.abiflags were correctly emitted. +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Offset: 0x50 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 0 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00002001 01010005 00000000 00000000 |.. .............| +# CHECK-OBJ: 0010: 00000000 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ: } + + .module fp=xx + +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/mips_abi_flags_xx_set.s b/test/MC/Mips/mips_abi_flags_xx_set.s new file mode 100644 index 0000000..56f19d3 --- /dev/null +++ b/test/MC/Mips/mips_abi_flags_xx_set.s @@ -0,0 +1,38 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ + +# CHECK-ASM: .module fp=xx +# CHECK-ASM: .set fp=64 + +# Checking if the Mips.abiflags were correctly emitted. +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Offset: 0x50 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 0 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00002001 01010005 00000000 00000000 |.. .............| +# CHECK-OBJ: 0010: 00000000 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ: } + + .module fp=xx + .set fp=64 +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/msa/abiflags.s b/test/MC/Mips/msa/abiflags.s new file mode 100644 index 0000000..83b83cc --- /dev/null +++ b/test/MC/Mips/msa/abiflags.s @@ -0,0 +1,38 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ + +# CHECK-ASM: .module fp=32 +# CHECK-ASM: .set fp=64 + +# Checking if the Mips.abiflags were correctly emitted. +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Offset: 0x50 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 0 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00002002 01030001 00000000 00000200 |.. .............| +# CHECK-OBJ: 0010: 00000000 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ: } + + .module fp=32 + .set fp=64 +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/nacl-mask.s b/test/MC/Mips/nacl-mask.s index 8205835..22286ac 100644 --- a/test/MC/Mips/nacl-mask.s +++ b/test/MC/Mips/nacl-mask.s @@ -283,3 +283,37 @@ test5: # CHECK-NEXT: and $25, $25, $14 # CHECK-NEXT: jalr $25 # CHECK-NEXT: addiu $4, $zero, 5 + + + +# Test that we can put non-dangerous loads and stores in branch delay slot. + + .align 4 +test6: + .set noreorder + + jal func1 + sw $4, 0($sp) + + bal func2 + lw $5, 0($t8) + + jalr $t9 + sw $sp, 0($sp) + +# CHECK-LABEL: test6: + +# CHECK-NEXT: nop +# CHECK-NEXT: nop +# CHECK-NEXT: jal +# CHECK-NEXT: sw $4, 0($sp) + +# CHECK-NEXT: nop +# CHECK-NEXT: nop +# CHECK-NEXT: bal +# CHECK-NEXT: lw $5, 0($24) + +# CHECK-NEXT: nop +# CHECK-NEXT: and $25, $25, $14 +# CHECK-NEXT: jalr +# CHECK-NEXT: sw $sp, 0($sp) diff --git a/test/MC/Mips/nooddspreg-cmdarg.s b/test/MC/Mips/nooddspreg-cmdarg.s new file mode 100644 index 0000000..826db12 --- /dev/null +++ b/test/MC/Mips/nooddspreg-cmdarg.s @@ -0,0 +1,43 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64,+nooddspreg | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64,+nooddspreg -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ + +# RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -mattr=-n64,+n32,+nooddspreg 2> %t0 +# RUN: FileCheck %s -check-prefix=INVALID < %t0 +# +# RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -mattr=+nooddspreg 2> %t0 +# RUN: FileCheck %s -check-prefix=INVALID < %t0 +# +# CHECK-ASM-NOT: .module nooddspreg + +# Checking if the Mips.abiflags were correctly emitted. +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Offset: 0x50 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 0 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00002001 01020007 00000000 00000000 |.. .............| +# CHECK-OBJ: 0010: 00000000 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ: } + +# INVALID: ERROR: -mno-odd-spreg requires the O32 ABI + +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/nooddspreg-error.s b/test/MC/Mips/nooddspreg-error.s new file mode 100644 index 0000000..b4aabbe --- /dev/null +++ b/test/MC/Mips/nooddspreg-error.s @@ -0,0 +1,14 @@ +# RUN: not llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64 2> %t0 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# RUN: FileCheck %s -check-prefix=CHECK-ERROR < %t0 +# + .module nooddspreg +# CHECK-ASM: .module nooddspreg + + add.s $f1, $f2, $f5 +# CHECK-ERROR: :[[@LINE-1]]:15: error: -mno-odd-spreg prohibits the use of odd FPU registers +# CHECK-ERROR: :[[@LINE-2]]:25: error: -mno-odd-spreg prohibits the use of odd FPU registers + +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/nooddspreg.s b/test/MC/Mips/nooddspreg.s new file mode 100644 index 0000000..5a283f5 --- /dev/null +++ b/test/MC/Mips/nooddspreg.s @@ -0,0 +1,45 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ + +# RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -mattr=-n64,n32 2> %t1 +# RUN: FileCheck %s -check-prefix=INVALID < %t1 +# +# RUN: not llvm-mc %s -arch=mips -mcpu=mips64 2> %t2 +# RUN: FileCheck %s -check-prefix=INVALID < %t2 +# +# CHECK-ASM: .module nooddspreg + +# Checking if the Mips.abiflags were correctly emitted. +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Offset: 0x50 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 0 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00002001 01020007 00000000 00000000 |.. .............| +# CHECK-OBJ: 0010: 00000000 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ: } + +# INVALID: '.module nooddspreg' requires the O32 ABI + + .module nooddspreg + +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/oddspreg.s b/test/MC/Mips/oddspreg.s new file mode 100644 index 0000000..f5aa9c0 --- /dev/null +++ b/test/MC/Mips/oddspreg.s @@ -0,0 +1,56 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ-ALL -check-prefix=CHECK-OBJ-O32 +# +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -mattr=-n64,+n32 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -mattr=-n64,+n32 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ-ALL -check-prefix=CHECK-OBJ-N32 + +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ-ALL -check-prefix=CHECK-OBJ-N64 + +# CHECK-ASM: .module oddspreg + +# Checking if the Mips.abiflags were correctly emitted. +# CHECK-OBJ-ALL: Section { +# CHECK-OBJ-ALL: Index: 5 +# CHECK-OBJ-ALL: Name: .MIPS.abiflags ({{[0-9]+}}) +# CHECK-OBJ-ALL: Type: (0x7000002A) +# CHECK-OBJ-ALL: Flags [ (0x2) +# CHECK-OBJ-ALL: SHF_ALLOC (0x2) +# CHECK-OBJ-ALL: ] +# CHECK-OBJ-ALL: Address: 0x0 +# CHECK-OBJ-ALL: Offset: 0x{{[0-9A-F]+}} +# CHECK-OBJ-ALL: Size: 24 +# CHECK-OBJ-ALL: Link: 0 +# CHECK-OBJ-ALL: Info: 0 +# CHECK-OBJ-ALL: AddressAlignment: 8 +# CHECK-OBJ-ALL: EntrySize: 0 +# CHECK-OBJ-ALL: Relocations [ +# CHECK-OBJ-ALL: ] +# CHECK-OBJ-ALL: SectionData ( +# CHECK-OBJ-O32: 0000: 00002001 01020006 00000000 00000000 |.. .............| +# CHECK-OBJ-O32: 0010: 00000001 00000000 |........| +# CHECK-OBJ-N32: 0000: 00004001 02020001 00000000 00000000 |..@.............| +# CHECK-OBJ-N32: 0010: 00000001 00000000 |........| +# CHECK-OBJ-N64: 0000: 00004001 02020001 00000000 00000000 |..@.............| +# CHECK-OBJ-N64: 0010: 00000001 00000000 |........| +# CHECK-OBJ-ALL: ) +# CHECK-OBJ-ALL: } + + .module oddspreg + add.s $f3, $f1, $f5 + +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/PowerPC/lit.local.cfg b/test/MC/PowerPC/lit.local.cfg index 193ebeb..0913324 100644 --- a/test/MC/PowerPC/lit.local.cfg +++ b/test/MC/PowerPC/lit.local.cfg @@ -1,3 +1,2 @@ -targets = set(config.root.targets_to_build.split()) -if not 'PowerPC' in targets: +if not 'PowerPC' in config.root.targets: config.unsupported = True diff --git a/test/MC/PowerPC/ppc64-initial-cfa.s b/test/MC/PowerPC/ppc64-initial-cfa.s index ca97e1b..d0bc6b3 100644 --- a/test/MC/PowerPC/ppc64-initial-cfa.s +++ b/test/MC/PowerPC/ppc64-initial-cfa.s @@ -28,8 +28,8 @@ _proc: # STATIC-NEXT: Relocations [ # STATIC-NEXT: ] # STATIC-NEXT: SectionData ( -# STATIC-BE-NEXT: 0000: 00000010 00000000 017A5200 04784101 -# STATIC-LE-NEXT: 0000: 10000000 00000000 017A5200 04784101 +# STATIC-BE-NEXT: 0000: 00000010 00000000 037A5200 04784101 +# STATIC-LE-NEXT: 0000: 10000000 00000000 037A5200 04784101 # STATIC-BE-NEXT: 0010: 1B0C0100 00000010 00000018 00000000 # STATIC-LE-NEXT: 0010: 1B0C0100 10000000 18000000 00000000 # STATIC-BE-NEXT: 0020: 00000004 00000000 @@ -69,8 +69,8 @@ _proc: # PIC-NEXT: Relocations [ # PIC-NEXT: ] # PIC-NEXT: SectionData ( -# PIC-BE-NEXT: 0000: 00000010 00000000 017A5200 04784101 -# PIC-LE-NEXT: 0000: 10000000 00000000 017A5200 04784101 +# PIC-BE-NEXT: 0000: 00000010 00000000 037A5200 04784101 +# PIC-LE-NEXT: 0000: 10000000 00000000 037A5200 04784101 # PIC-BE-NEXT: 0010: 1B0C0100 00000010 00000018 00000000 # PIC-LE-NEXT: 0010: 1B0C0100 10000000 18000000 00000000 # PIC-BE-NEXT: 0020: 00000004 00000000 diff --git a/test/MC/Sparc/lit.local.cfg b/test/MC/Sparc/lit.local.cfg index 4d344fa..fa6a54e 100644 --- a/test/MC/Sparc/lit.local.cfg +++ b/test/MC/Sparc/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'Sparc' in targets: +if not 'Sparc' in config.root.targets: config.unsupported = True diff --git a/test/MC/SystemZ/insn-bad-z196.s b/test/MC/SystemZ/insn-bad-z196.s index da23a4b..47dbe08 100644 --- a/test/MC/SystemZ/insn-bad-z196.s +++ b/test/MC/SystemZ/insn-bad-z196.s @@ -411,6 +411,60 @@ lbh %r0, 524288 #CHECK: error: invalid operand +#CHECK: ldxbra %f0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: ldxbra %f0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: ldxbra %f0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: ldxbra %f0, 16, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: ldxbra %f0, 0, %f2, 0 +#CHECK: error: invalid register pair +#CHECK: ldxbra %f2, 0, %f0, 0 + + ldxbra %f0, 0, %f0, -1 + ldxbra %f0, 0, %f0, 16 + ldxbra %f0, -1, %f0, 0 + ldxbra %f0, 16, %f0, 0 + ldxbra %f0, 0, %f2, 0 + ldxbra %f2, 0, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: ledbra %f0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: ledbra %f0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: ledbra %f0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: ledbra %f0, 16, %f0, 0 + + ledbra %f0, 0, %f0, -1 + ledbra %f0, 0, %f0, 16 + ledbra %f0, -1, %f0, 0 + ledbra %f0, 16, %f0, 0 + +#CHECK: error: invalid operand +#CHECK: lexbra %f0, 0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: lexbra %f0, 0, %f0, 16 +#CHECK: error: invalid operand +#CHECK: lexbra %f0, -1, %f0, 0 +#CHECK: error: invalid operand +#CHECK: lexbra %f0, 16, %f0, 0 +#CHECK: error: invalid register pair +#CHECK: lexbra %f0, 0, %f2, 0 +#CHECK: error: invalid register pair +#CHECK: lexbra %f2, 0, %f0, 0 + + lexbra %f0, 0, %f0, -1 + lexbra %f0, 0, %f0, 16 + lexbra %f0, -1, %f0, 0 + lexbra %f0, 16, %f0, 0 + lexbra %f0, 0, %f2, 0 + lexbra %f2, 0, %f0, 0 + +#CHECK: error: invalid operand #CHECK: lfh %r0, -524289 #CHECK: error: invalid operand #CHECK: lfh %r0, 524288 diff --git a/test/MC/SystemZ/insn-bad.s b/test/MC/SystemZ/insn-bad.s index 8004168..a08cb34 100644 --- a/test/MC/SystemZ/insn-bad.s +++ b/test/MC/SystemZ/insn-bad.s @@ -1560,6 +1560,11 @@ ldxbr %f0, %f2 ldxbr %f2, %f0 +#CHECK: error: {{(instruction requires: fp-extension)?}} +#CHECK: ldxbra %f0, 0, %f0, 0 + + ldxbra %f0, 0, %f0, 0 + #CHECK: error: invalid operand #CHECK: ldy %f0, -524289 #CHECK: error: invalid operand @@ -1576,6 +1581,11 @@ le %f0, -1 le %f0, 4096 +#CHECK: error: {{(instruction requires: fp-extension)?}} +#CHECK: ledbra %f0, 0, %f0, 0 + + ledbra %f0, 0, %f0, 0 + #CHECK: error: invalid register pair #CHECK: lexbr %f0, %f2 #CHECK: error: invalid register pair @@ -1584,6 +1594,11 @@ lexbr %f0, %f2 lexbr %f2, %f0 +#CHECK: error: {{(instruction requires: fp-extension)?}} +#CHECK: lexbra %f0, 0, %f0, 0 + + lexbra %f0, 0, %f0, 0 + #CHECK: error: invalid operand #CHECK: ley %f0, -524289 #CHECK: error: invalid operand diff --git a/test/MC/SystemZ/insn-good-z196.s b/test/MC/SystemZ/insn-good-z196.s index 834bdad..db5ecdd 100644 --- a/test/MC/SystemZ/insn-good-z196.s +++ b/test/MC/SystemZ/insn-good-z196.s @@ -675,6 +675,48 @@ lbh %r0, 524287(%r15,%r1) lbh %r15, 0 +#CHECK: ldxbra %f0, 0, %f0, 0 # encoding: [0xb3,0x45,0x00,0x00] +#CHECK: ldxbra %f0, 0, %f0, 15 # encoding: [0xb3,0x45,0x0f,0x00] +#CHECK: ldxbra %f0, 0, %f13, 0 # encoding: [0xb3,0x45,0x00,0x0d] +#CHECK: ldxbra %f0, 15, %f0, 0 # encoding: [0xb3,0x45,0xf0,0x00] +#CHECK: ldxbra %f4, 5, %f8, 9 # encoding: [0xb3,0x45,0x59,0x48] +#CHECK: ldxbra %f13, 0, %f0, 0 # encoding: [0xb3,0x45,0x00,0xd0] + + ldxbra %f0, 0, %f0, 0 + ldxbra %f0, 0, %f0, 15 + ldxbra %f0, 0, %f13, 0 + ldxbra %f0, 15, %f0, 0 + ldxbra %f4, 5, %f8, 9 + ldxbra %f13, 0, %f0, 0 + +#CHECK: ledbra %f0, 0, %f0, 0 # encoding: [0xb3,0x44,0x00,0x00] +#CHECK: ledbra %f0, 0, %f0, 15 # encoding: [0xb3,0x44,0x0f,0x00] +#CHECK: ledbra %f0, 0, %f15, 0 # encoding: [0xb3,0x44,0x00,0x0f] +#CHECK: ledbra %f0, 15, %f0, 0 # encoding: [0xb3,0x44,0xf0,0x00] +#CHECK: ledbra %f4, 5, %f6, 7 # encoding: [0xb3,0x44,0x57,0x46] +#CHECK: ledbra %f15, 0, %f0, 0 # encoding: [0xb3,0x44,0x00,0xf0] + + ledbra %f0, 0, %f0, 0 + ledbra %f0, 0, %f0, 15 + ledbra %f0, 0, %f15, 0 + ledbra %f0, 15, %f0, 0 + ledbra %f4, 5, %f6, 7 + ledbra %f15, 0, %f0, 0 + +#CHECK: lexbra %f0, 0, %f0, 0 # encoding: [0xb3,0x46,0x00,0x00] +#CHECK: lexbra %f0, 0, %f0, 15 # encoding: [0xb3,0x46,0x0f,0x00] +#CHECK: lexbra %f0, 0, %f13, 0 # encoding: [0xb3,0x46,0x00,0x0d] +#CHECK: lexbra %f0, 15, %f0, 0 # encoding: [0xb3,0x46,0xf0,0x00] +#CHECK: lexbra %f4, 5, %f8, 9 # encoding: [0xb3,0x46,0x59,0x48] +#CHECK: lexbra %f13, 0, %f0, 0 # encoding: [0xb3,0x46,0x00,0xd0] + + lexbra %f0, 0, %f0, 0 + lexbra %f0, 0, %f0, 15 + lexbra %f0, 0, %f13, 0 + lexbra %f0, 15, %f0, 0 + lexbra %f4, 5, %f8, 9 + lexbra %f13, 0, %f0, 0 + #CHECK: lfh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xca] #CHECK: lfh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xca] #CHECK: lfh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xca] diff --git a/test/MC/SystemZ/lit.local.cfg b/test/MC/SystemZ/lit.local.cfg index b12af09..5c02dd3 100644 --- a/test/MC/SystemZ/lit.local.cfg +++ b/test/MC/SystemZ/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'SystemZ' in targets: +if not 'SystemZ' in config.root.targets: config.unsupported = True diff --git a/test/MC/X86/AlignedBundling/lit.local.cfg b/test/MC/X86/AlignedBundling/lit.local.cfg index ba763cf..e71f3cc 100644 --- a/test/MC/X86/AlignedBundling/lit.local.cfg +++ b/test/MC/X86/AlignedBundling/lit.local.cfg @@ -1,4 +1,3 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True diff --git a/test/MC/X86/avx512-encodings.s b/test/MC/X86/avx512-encodings.s index 2915b7a..187b512 100644 --- a/test/MC/X86/avx512-encodings.s +++ b/test/MC/X86/avx512-encodings.s @@ -1,4 +1,5 @@ -// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=knl --show-encoding %s | FileCheck %s +// RUN: not llvm-mc -triple x86_64-unknown-unknown -mcpu=knl --show-encoding %s 2> %t.err | FileCheck %s +// RUN: FileCheck --check-prefix=ERR < %t.err %s // CHECK: vaddpd %zmm6, %zmm27, %zmm8 // CHECK: encoding: [0x62,0x71,0xa5,0x40,0x58,0xc6] @@ -3128,6 +3129,14 @@ vpsrad 512(%rdi, %rsi, 4), %zmm12, %zmm25 // CHECK: encoding: [0x62,0xf2,0x7d,0xc9,0x58,0xc8] vpbroadcastd %xmm0, %zmm1 {%k1} {z} +// CHECK: vbroadcasti32x4 {{.*}} {%k7} {z} +// CHECK: encoding: [0x67,0x62,0xf2,0x7d,0xcf,0x5a,0x52,0x02] +vbroadcasti32x4 0x20(%edx), %zmm2 {%k7} {z} + +// CHECK: vbroadcasti64x4 {{.*}} %zmm22 +// CHECK: encoding: [0x62,0xe2,0xfd,0x48,0x5b,0x72,0x02] +vbroadcasti64x4 0x40(%rdx), %zmm22 + // CHECK: vmovdqu64 {{.*}} {%k3} // CHECK: encoding: [0x62,0xf1,0xfe,0x4b,0x7f,0x07] vmovdqu64 %zmm0, (%rdi) {%k3} @@ -3151,3 +3160,62 @@ vaddpd 512(%rdi, %rsi, 8) {1to8}, %zmm20, %zmm30 // CHECK: vaddps {{.*}}{1to16} // CHECK: encoding: [0x62,0x61,0x5c,0x50,0x58,0xb4,0xf7,0x00,0x02,0x00,0x00] vaddps 512(%rdi, %rsi, 8) {1to16}, %zmm20, %zmm30 + +// CHECK: vmovntdqa +// CHECK: encoding: [0x62,0x72,0x7d,0x48,0x2a,0xab,0x78,0x56,0x34,0x12] +vmovntdqa 0x12345678(%rbx), %zmm13 + +// CHECK: vmovntdqa +// CHECK: encoding: [0x62,0xc2,0x7d,0x48,0x2a,0x14,0x56] +vmovntdqa (%r14,%rdx,2), %zmm18 + +// CHECK: vmovntdqa +// CHECK: encoding: [0x62,0xc2,0x7d,0x48,0x2a,0x7c,0x14,0x02] +vmovntdqa 128(%r12,%rdx), %zmm23 + +// CHECK: vmovntdq +// CHECK: encoding: [0x62,0x21,0x7d,0x48,0xe7,0x24,0xa9] +vmovntdq %zmm28, (%rcx,%r13,4) + +// CHECK: vmovntpd +// CHECK: encoding: [0x62,0xf1,0xfd,0x48,0x2b,0xb2,0x04,0x00,0x00,0x00] +vmovntpd %zmm6, 4(%rdx) + +// CHECK: vmovntps +// CHECK: encoding: [0x62,0x51,0x7c,0x48,0x2b,0x5c,0x8d,0x00] +vmovntps %zmm11, (%r13,%rcx,4) + +// CHECK: vcmpps $14 +// CHECK: encoding: [0x62,0xb1,0x54,0x48,0xc2,0xd1,0x0e] +vcmpgtps %zmm17, %zmm5, %k2 + +// CHECK: vcmppd $13 +// CHECK: encoding: [0x62,0xd1,0xf5,0x40,0xc2,0x76,0x02,0x0d] +vcmpgepd 0x80(%r14), %zmm17, %k6 + +// CHECK: vpcmpd $1, +// CHECK: encoding: [0x62,0x93,0x45,0x4c,0x1f,0xe8,0x01] +vpcmpd $1, %zmm24, %zmm7, %k5{%k4} + +// CHECK: vpcmpuq $2, +// CHECK: encoding: [0x62,0xf3,0xf5,0x47,0x1e,0x72,0x01,0x02] +vpcmpuq $2, 0x40(%rdx), %zmm17, %k6{%k7} + +// ERR: invalid operand for instruction +vpcmpd $1, %zmm24, %zmm7, %k5{%k0} + +// CHECK: vpermi2d +// CHECK: encoding: [0x62,0x42,0x6d,0x4b,0x76,0xd6] +vpermi2d %zmm14, %zmm2, %zmm26 {%k3} + +// CHECK: vpermt2pd +// CHECK: encoding: [0x62,0xf2,0xcd,0xc6,0x7f,0xf3] +vpermt2pd %zmm3, %zmm22, %zmm6 {%k6} {z} + +// CHECK: vpermi2q +// CHECK: encoding: [0x62,0x62,0xed,0x4b,0x76,0x54,0x58,0x02] +vpermi2q 0x80(%rax,%rbx,2), %zmm2, %zmm26 {%k3} + +// CHECK: vpermt2d +// CHECK: encoding: [0x62,0x32,0x4d,0xc2,0x7e,0x24,0xad,0x05,0x00,0x00,0x00] +vpermt2d 5(,%r13,4), %zmm22, %zmm12 {%k2} {z} diff --git a/test/MC/X86/intel-syntax.s b/test/MC/X86/intel-syntax.s index 540282a..7968918 100644 --- a/test/MC/X86/intel-syntax.s +++ b/test/MC/X86/intel-syntax.s @@ -599,3 +599,11 @@ fxrstor64 opaque ptr [rax] // CHECK: movq _g0+8, %rcx mov rbx, qword ptr [_g0] mov rcx, qword ptr [_g0 + 8] + +"?half@?0??bar@@YAXXZ@4NA": + .quad 4602678819172646912 + +fadd "?half@?0??bar@@YAXXZ@4NA" +fadd "?half@?0??bar@@YAXXZ@4NA"@IMGREL +// CHECK: fadds "?half@?0??bar@@YAXXZ@4NA" +// CHECK: fadds "?half@?0??bar@@YAXXZ@4NA"@IMGREL32 diff --git a/test/MC/X86/lit.local.cfg b/test/MC/X86/lit.local.cfg index 19840aa..c8625f4 100644 --- a/test/MC/X86/lit.local.cfg +++ b/test/MC/X86/lit.local.cfg @@ -1,3 +1,2 @@ -targets = set(config.root.targets_to_build.split()) -if not 'X86' in targets: +if not 'X86' in config.root.targets: config.unsupported = True diff --git a/test/MC/X86/no-elf-compact-unwind.s b/test/MC/X86/no-elf-compact-unwind.s index 017c52a..4e9236b 100644 --- a/test/MC/X86/no-elf-compact-unwind.s +++ b/test/MC/X86/no-elf-compact-unwind.s @@ -1,4 +1,5 @@ // RUN: llvm-mc < %s -filetype=obj -triple x86_64-apple-macosx10.8.0 | llvm-readobj -s | FileCheck -check-prefix=MACHO %s +// RUN: llvm-mc < %s -filetype=obj -triple x86_64-apple-ios7.0.0 | llvm-readobj -s | FileCheck -check-prefix=MACHO %s // RUN: llvm-mc < %s -filetype=obj -triple x86_64-unknown-linux | llvm-readobj -s | FileCheck -check-prefix=ELF %s .globl __Z3barv diff --git a/test/MC/X86/x86_long_nop.s b/test/MC/X86/x86_long_nop.s index ac1bc08..eee840c 100644 --- a/test/MC/X86/x86_long_nop.s +++ b/test/MC/X86/x86_long_nop.s @@ -2,6 +2,7 @@ # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s # RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-apple-darwin10.0 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s # RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-apple-darwin8 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s +# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=slm %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=SLM %s # Ensure alignment directives also emit sequences of 15-byte NOPs on processors # capable of using long NOPs. @@ -13,3 +14,12 @@ inc %eax # CHECK-NEXT: 10: nop # CHECK-NEXT: 1f: nop # CHECK-NEXT: 20: inc + +# On Silvermont we emit only 7 byte NOPs since longer NOPs are not profitable +# SLM: 0: inc +# SLM-NEXT: 1: nop +# SLM-NEXT: 8: nop +# SLM-NEXT: f: nop +# SLM-NEXT: 16: nop +# SLM-NEXT: 1d: nop +# SLM-NEXT: 20: inc diff --git a/test/MC/X86/x86_nop.s b/test/MC/X86/x86_nop.s index 059f591..572487b 100644 --- a/test/MC/X86/x86_nop.s +++ b/test/MC/X86/x86_nop.s @@ -14,6 +14,7 @@ # RUN: llvm-mc -filetype=obj -triple=i686-pc-linux -mcpu=c3 %s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -filetype=obj -triple=i686-pc-linux -mcpu=c3-2 %s | llvm-objdump -d - | FileCheck %s # RUN: llvm-mc -filetype=obj -triple=i686-pc-linux -mcpu=core2 %s | llvm-objdump -d - | FileCheck --check-prefix=NOPL %s +# RUN: llvm-mc -filetype=obj -triple=i686-pc-linux -mcpu=slm %s | llvm-objdump -d - | FileCheck --check-prefix=NOPL %s inc %eax |