Merge with LLVM upstream r135568 (Jul 20th 2011)

Conflicts:
	lib/Bitcode/Reader/BitcodeReader.cpp

Change-Id: Iebed76d2f7d281e742947e31d9a0b78174daf2d6

6 files changed, 189 insertions, 61 deletions

diff --git a/test/MC/ARM/arm_fixups.s b/test/MC/ARM/arm_fixups.s
index 0dceb83..aba0cd8 100644
--- a/test/MC/ARM/arm_fixups.s
+++ b/test/MC/ARM/arm_fixups.s
@@ -1,7 +1,17 @@
-// RUN: llvm-mc -triple arm-unknown-unknown %s --show-encoding > %t
-// RUN: FileCheck < %t %s
+@ RUN: llvm-mc -triple armv7-unknown-unknown %s --show-encoding > %t
+@ RUN: FileCheck < %t %s
 
-// CHECK: bl _printf @ encoding: [A,A,A,0xeb]
-// CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_uncondbranch
-bl _printf
-        
\ No newline at end of file
+    bl _printf
+@ CHECK: bl _printf @ encoding: [A,A,A,0xeb]
+@ CHECK: @ fixup A - offset: 0, value: _printf, kind: fixup_arm_uncondbranch
+
+    mov r9, :lower16:(_foo)
+    movw r9, :lower16:(_foo)
+    movt r9, :upper16:(_foo)
+
+@ CHECK: movw	r9, :lower16:_foo       @ encoding: [A,0x90'A',0b0000AAAA,0xe3]
+@ CHECK: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_movw_lo16
+@ CHECK: movw	r9, :lower16:_foo       @ encoding: [A,0x90'A',0b0000AAAA,0xe3]
+@ CHECK: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_movw_lo16
+@ CHECK: movt	r9, :upper16:_foo       @ encoding: [A,0x90'A',0b0100AAAA,0xe3]
+@ CHECK: @   fixup A - offset: 0, value: _foo, kind: fixup_arm_movt_hi16
diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s
index 650fcd2..5154e55 100644
--- a/test/MC/ARM/arm_instructions.s
+++ b/test/MC/ARM/arm_instructions.s
@@ -83,19 +83,6 @@
 @ CHECK: bkpt  #10 @ encoding: [0x7a,0x00,0x20,0xe1]
         bkpt  #10
 
-@ CHECK: mrs  r8, cpsr @ encoding: [0x00,0x80,0x0f,0xe1]
-        mrs  r8, cpsr
-
-@ CHECK: mrc  p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee]
-        mrc  p14, #0, r1, c1, c2, #4
-@ CHECK: mrrc  p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec]
-        mrrc  p7, #1, r5, r4, c1
-
-@ CHECK: mrc2  p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe]
-        mrc2  p14, #0, r1, c1, c2, #4
-@ CHECK: mrrc2  p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc]
-        mrrc2  p7, #1, r5, r4, c1
-
 @ CHECK: cdp  p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee]
         cdp  p7, #1, c1, c1, c1, #4
 @ CHECK: cdp2  p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe]
@@ -134,45 +121,6 @@
 @ CHECK: cpsie  if, #10 @ encoding: [0xca,0x00,0x0a,0xf1]
         cpsie  if, #10
 
-@ CHECK: msr  cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
-        msr  apsr, r0
-
-@ CHECK: msr  cpsr_s, r0 @ encoding: [0x00,0xf0,0x24,0xe1]
-        msr  apsr_g, r0
-
-@ CHECK: msr  cpsr_f, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
-        msr  apsr_nzcvq, r0
-
-@ CHECK: msr  cpsr_fs, r0 @ encoding: [0x00,0xf0,0x2c,0xe1]
-        msr  apsr_nzcvqg, r0
-
-@ CHECK: msr  cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
-        msr  cpsr_fc, r0
-
-@ CHECK: msr  cpsr_c, r0 @ encoding: [0x00,0xf0,0x21,0xe1]
-        msr  cpsr_c, r0
-
-@ CHECK: msr  cpsr_x, r0 @ encoding: [0x00,0xf0,0x22,0xe1]
-        msr  cpsr_x, r0
-
-@ CHECK: msr  cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
-        msr  cpsr_fc, r0
-
-@ CHECK: msr  cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
-        msr  cpsr_all, r0
-
-@ CHECK: msr  cpsr_fsx, r0 @ encoding: [0x00,0xf0,0x2e,0xe1]
-        msr  cpsr_fsx, r0
-
-@ CHECK: msr  spsr_fc, r0 @ encoding: [0x00,0xf0,0x69,0xe1]
-        msr  spsr_fc, r0
-
-@ CHECK: msr  spsr_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1]
-        msr  spsr_fsxc, r0
-
-@ CHECK: msr  cpsr_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1]
-        msr  cpsr_fsxc, r0
-
 @ CHECK: add	r1, r2, r3, lsl r4      @ encoding: [0x13,0x14,0x82,0xe0]
   add r1, r2, r3, lsl r4
 
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 0b728bc..00cfec9 100644
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -671,6 +671,147 @@ _func:
 @ CHECK: mlsne	r2, r5, r6, r3          @ encoding: [0x95,0x36,0x62,0x10]
 
 @------------------------------------------------------------------------------
+@ MOV (immediate)
+@------------------------------------------------------------------------------
+    mov r3, #7
+    mov r4, #0xff0
+    mov r5, #0xff0000
+    mov r6, #0xffff
+    movw r9, #0xffff
+    movs r3, #7
+    moveq r4, #0xff0
+    movseq r5, #0xff0000
+
+@ CHECK: mov	r3, #7                  @ encoding: [0x07,0x30,0xa0,0xe3]
+@ CHECK: mov	r4, #4080               @ encoding: [0xff,0x4e,0xa0,0xe3]
+@ CHECK: mov	r5, #16711680           @ encoding: [0xff,0x58,0xa0,0xe3]
+@ CHECK: movw	r6, #65535              @ encoding: [0xff,0x6f,0x0f,0xe3]
+@ CHECK: movw	r9, #65535              @ encoding: [0xff,0x9f,0x0f,0xe3]
+@ CHECK: movs	r3, #7                  @ encoding: [0x07,0x30,0xb0,0xe3]
+@ CHECK: moveq	r4, #4080               @ encoding: [0xff,0x4e,0xa0,0x03]
+@ CHECK: movseq	r5, #16711680           @ encoding: [0xff,0x58,0xb0,0x03]
+
+@------------------------------------------------------------------------------
+@ MOV (register)
+@------------------------------------------------------------------------------
+        mov r2, r3
+        movs r2, r3
+        moveq r2, r3
+        movseq r2, r3
+
+@ CHECK: mov	r2, r3                  @ encoding: [0x03,0x20,0xa0,0xe1]
+@ CHECK: movs	r2, r3                  @ encoding: [0x03,0x20,0xb0,0xe1]
+@ CHECK: moveq	r2, r3                  @ encoding: [0x03,0x20,0xa0,0x01]
+@ CHECK: movseq	r2, r3                  @ encoding: [0x03,0x20,0xb0,0x01]
+
+@------------------------------------------------------------------------------
+@ MOVT
+@------------------------------------------------------------------------------
+    movt r3, #7
+    movt r6, #0xffff
+    movteq r4, #0xff0
+
+@ CHECK: movt	r3, #7                  @ encoding: [0x07,0x30,0x40,0xe3]
+@ CHECK: movt	r6, #65535              @ encoding: [0xff,0x6f,0x4f,0xe3]
+@ CHECK: movteq	r4, #4080               @ encoding: [0xf0,0x4f,0x40,0x03]
+
+
+@------------------------------------------------------------------------------
+@ MRC/MRC2
+@------------------------------------------------------------------------------
+        mrc  p14, #0, r1, c1, c2, #4
+        mrc2  p14, #0, r1, c1, c2, #4
+
+@ CHECK: mrc  p14, #0, r1, c1, c2, #4   @ encoding: [0x92,0x1e,0x11,0xee]
+@ CHECK: mrc2  p14, #0, r1, c1, c2, #4  @ encoding: [0x92,0x1e,0x11,0xfe]
+
+@------------------------------------------------------------------------------
+@ MRRC/MRRC2
+@------------------------------------------------------------------------------
+        mrrc  p7, #1, r5, r4, c1
+        mrrc2  p7, #1, r5, r4, c1
+
+@ CHECK: mrrc  p7, #1, r5, r4, c1       @ encoding: [0x11,0x57,0x54,0xec]
+@ CHECK: mrrc2  p7, #1, r5, r4, c1      @ encoding: [0x11,0x57,0x54,0xfc]
+
+
+@------------------------------------------------------------------------------
+@ MRS
+@------------------------------------------------------------------------------
+        mrs  r8, apsr
+        mrs  r8, cpsr
+        mrs  r8, spsr
+@ CHECK: mrs  r8, apsr @ encoding: [0x00,0x80,0x0f,0xe1]
+@ CHECK: mrs  r8, apsr @ encoding: [0x00,0x80,0x0f,0xe1]
+@ CHECK: mrs  r8, spsr @ encoding: [0x00,0x80,0x4f,0xe1]
+
+
+
+@------------------------------------------------------------------------------
+@ MSR
+@------------------------------------------------------------------------------
+
+        msr  apsr, #5
+        msr  apsr_g, #5
+        msr  apsr_nzcvq, #5
+        msr  APSR_nzcvq, #5
+        msr  apsr_nzcvqg, #5
+        msr  cpsr_fc, #5
+        msr  cpsr_c, #5
+        msr  cpsr_x, #5
+        msr  cpsr_fc, #5
+        msr  cpsr_all, #5
+        msr  cpsr_fsx, #5
+        msr  spsr_fc, #5
+        msr  SPSR_fsxc, #5
+        msr  cpsr_fsxc, #5
+
+@ CHECK: msr	CPSR_fc, #5             @ encoding: [0x05,0xf0,0x29,0xe3]
+@ CHECK: msr	APSR_g, #5              @ encoding: [0x05,0xf0,0x24,0xe3]
+@ CHECK: msr	APSR_nzcvq, #5          @ encoding: [0x05,0xf0,0x28,0xe3]
+@ CHECK: msr	APSR_nzcvq, #5          @ encoding: [0x05,0xf0,0x28,0xe3]
+@ CHECK: msr	APSR_nzcvqg, #5         @ encoding: [0x05,0xf0,0x2c,0xe3]
+@ CHECK: msr	CPSR_fc, #5             @ encoding: [0x05,0xf0,0x29,0xe3]
+@ CHECK: msr	CPSR_c, #5              @ encoding: [0x05,0xf0,0x21,0xe3]
+@ CHECK: msr	CPSR_x, #5              @ encoding: [0x05,0xf0,0x22,0xe3]
+@ CHECK: msr	CPSR_fc, #5             @ encoding: [0x05,0xf0,0x29,0xe3]
+@ CHECK: msr	CPSR_fc, #5             @ encoding: [0x05,0xf0,0x29,0xe3]
+@ CHECK: msr	CPSR_fsx, #5            @ encoding: [0x05,0xf0,0x2e,0xe3]
+@ CHECK: msr	SPSR_fc, #5             @ encoding: [0x05,0xf0,0x69,0xe3]
+@ CHECK: msr	SPSR_fsxc, #5           @ encoding: [0x05,0xf0,0x6f,0xe3]
+@ CHECK: msr	CPSR_fsxc, #5           @ encoding: [0x05,0xf0,0x2f,0xe3]
+
+        msr  apsr, r0
+        msr  apsr_g, r0
+        msr  apsr_nzcvq, r0
+        msr  APSR_nzcvq, r0
+        msr  apsr_nzcvqg, r0
+        msr  cpsr_fc, r0
+        msr  cpsr_c, r0
+        msr  cpsr_x, r0
+        msr  cpsr_fc, r0
+        msr  cpsr_all, r0
+        msr  cpsr_fsx, r0
+        msr  spsr_fc, r0
+        msr  SPSR_fsxc, r0
+        msr  cpsr_fsxc, r0
+
+@ CHECK: msr  CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
+@ CHECK: msr  APSR_g, r0 @ encoding: [0x00,0xf0,0x24,0xe1]
+@ CHECK: msr  APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
+@ CHECK: msr  APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
+@ CHECK: msr  APSR_nzcvqg, r0 @ encoding: [0x00,0xf0,0x2c,0xe1]
+@ CHECK: msr  CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
+@ CHECK: msr  CPSR_c, r0 @ encoding: [0x00,0xf0,0x21,0xe1]
+@ CHECK: msr  CPSR_x, r0 @ encoding: [0x00,0xf0,0x22,0xe1]
+@ CHECK: msr  CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
+@ CHECK: msr  CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
+@ CHECK: msr  CPSR_fsx, r0 @ encoding: [0x00,0xf0,0x2e,0xe1]
+@ CHECK: msr  SPSR_fc, r0 @ encoding: [0x00,0xf0,0x69,0xe1]
+@ CHECK: msr  SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1]
+@ CHECK: msr  CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1]
+
+@------------------------------------------------------------------------------
 @ STM*
 @------------------------------------------------------------------------------
         stm       r2, {r1,r3-r6,sp}
diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s
index 4537a0f..aaea336 100644
--- a/test/MC/ARM/diagnostics.s
+++ b/test/MC/ARM/diagnostics.s
@@ -88,3 +88,32 @@
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: invalid operand for instruction
+
+
+        @ Out of range immediate for MOV
+        movw r9, 0x10000
+@ CHECK-ERRORS: error: invalid operand for instruction
+
+        @ Invalid 's' bit usage for MOVW
+        movs r6, #0xffff
+        movwseq r9, #0xffff
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: instruction 'movw' can not set flags, but 's' suffix specified
+
+        @ Out of range immediate for MOVT
+        movt r9, 0x10000
+@ CHECK-ERRORS: error: invalid operand for instruction
+
+        @ Out of range immediates for MRC/MRC2/MRRC/MRRC2
+        mrc  p14, #8, r1, c1, c2, #4
+        mrc  p14, #1, r1, c1, c2, #8
+        mrc2  p14, #8, r1, c1, c2, #4
+        mrc2  p14, #0, r1, c1, c2, #9
+        mrrc  p7, #16, r5, r4, c1
+        mrrc2  p7, #17, r5, r4, c1
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: invalid operand for instruction
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt
index 0536eeb..537ad55 100644
--- a/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/test/MC/Disassembler/ARM/arm-tests.txt
@@ -149,10 +149,10 @@
 # CHECK: cpsie if, #10
 0xca 0x00 0x0a 0xf1
 
-# CHECK: msr cpsr_fc, r0
+# CHECK: msr CPSR_fc, r0
 0x00 0xf0 0x29 0xe1
 
-# CHECK:	msrmi	cpsr_c, #4043309056
+# CHECK:	msrmi	CPSR_c, #4043309056
 0xf1 0xf4 0x21 0x43
 
 # CHECK: rsbs r6, r7, r8
diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt
index 895a5bb..0d55bb7 100644
--- a/test/MC/Disassembler/ARM/thumb-tests.txt
+++ b/test/MC/Disassembler/ARM/thumb-tests.txt
@@ -131,7 +131,7 @@
 # CHECK: cpsie aif
 0x67 0xb6
 
-# CHECK: msr cpsr_fc, r0
+# CHECK: msr CPSR_fc, r0
 0x80 0xf3 0x00 0x89
 
 # CHECK: blx	#-4