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authorArtyom Skrobov <Artyom.Skrobov@arm.com>2013-11-08 16:16:30 +0000
committerArtyom Skrobov <Artyom.Skrobov@arm.com>2013-11-08 16:16:30 +0000
commitfa840ba402806d978c18401c6bea1c808607d944 (patch)
tree7281ba6ee9459592bac2f4fbcc1a48790ba5d346 /test/MC
parent62ab26548fee37422fb90daaac22fc1140be797d (diff)
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[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC')
-rw-r--r--test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt35
1 files changed, 35 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt b/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt
index 454b394..d9286bf 100644
--- a/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt
+++ b/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt
@@ -21,3 +21,38 @@
0x05 0xf0 0x20 0xe3
# CHECK: sevl
+
+
+# These are the only coprocessor instructions that remain defined in ARMv8
+# (The operations on p10/p11 disassemble into FP/NEON instructions)
+
+0x10 0x0e 0x00 0xee
+# CHECK: mcr p14
+
+0x10 0x0f 0x00 0xee
+# CHECK: mcr p15
+
+0x10 0x0e 0x10 0xee
+# CHECK: mrc p14
+
+0x10 0x0f 0x10 0xee
+# CHECK: mrc p15
+
+0x00 0x0e 0x40 0xec
+# CHECK: mcrr p14
+
+0x00 0x0f 0x40 0xec
+# CHECK: mcrr p15
+
+0x00 0x0e 0x50 0xec
+# CHECK: mrrc p14
+
+0x00 0x0f 0x50 0xec
+# CHECK: mrrc p15
+
+0x00 0x0e 0x80 0xec
+# CHECK: stc p14
+
+0x00 0x0e 0x90 0xec
+# CHECK: ldc p14
+