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authorEli Friedman <eli.friedman@gmail.com>2009-08-22 03:13:10 +0000
committerEli Friedman <eli.friedman@gmail.com>2009-08-22 03:13:10 +0000
commitce392eb3ea16b781de89b7ff8f42c39f8b3df30e (patch)
treee221dde4f89d2ff0a80a8c4c9f0967550c59c791 /test
parentb8b85cfd4d7b8e54e3323e555c3e644b3af46ccb (diff)
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Make x86 test actually test x86 code generation. Fix the
construct on ARM, which was breaking by coincidence, and add a similar testcase for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79719 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
-rw-r--r--test/CodeGen/ARM/vshift_split.ll8
-rw-r--r--test/CodeGen/X86/vshift_split.ll4
2 files changed, 10 insertions, 2 deletions
diff --git a/test/CodeGen/ARM/vshift_split.ll b/test/CodeGen/ARM/vshift_split.ll
new file mode 100644
index 0000000..a44db66
--- /dev/null
+++ b/test/CodeGen/ARM/vshift_split.ll
@@ -0,0 +1,8 @@
+; RUN: llvm-as < %s | llc -march=arm -mattr=-neon
+
+; Example that requires splitting and expanding a vector shift.
+define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
+entry:
+ %shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %shr
+}
diff --git a/test/CodeGen/X86/vshift_split.ll b/test/CodeGen/X86/vshift_split.ll
index 8f485dd..a1376e5 100644
--- a/test/CodeGen/X86/vshift_split.ll
+++ b/test/CodeGen/X86/vshift_split.ll
@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
; Example that requires splitting and expanding a vector shift.
define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
entry:
- %shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1]
+ %shr = lshr <2 x i64> %val, < i64 2, i64 3 >
ret <2 x i64> %shr
}