diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 20 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 9 | ||||
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 15 | ||||
| -rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 9 |
4 files changed, 45 insertions, 8 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index f9969b9..c5bf607 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -293,21 +293,27 @@ class InstThumb<AddrMode am, int sz, IndexMode im, // Pseudo-instructions for alternate assembly syntax (never used by codegen). // These are aliases that require C++ handling to convert to the target // instruction, while InstAliases can be handled directly by tblgen. -class AsmPseudoInst<dag iops> +class AsmPseudoInst<string asm, dag iops> : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, "", NoItinerary> { - let OutOperandList = (ops); + let OutOperandList = (outs); let InOperandList = iops; let Pattern = []; let isCodeGenOnly = 0; // So we get asm matcher for it. + let AsmString = asm; let isPseudo = 1; } -class ARMAsmPseudo<dag iops> : AsmPseudoInst<iops>, Requires<[IsARM]>; -class tAsmPseudo<dag iops> : AsmPseudoInst<iops>, Requires<[IsThumb]>; -class t2AsmPseudo<dag iops> : AsmPseudoInst<iops>, Requires<[IsThumb2]>; -class VFP2AsmPseudo<dag iops> : AsmPseudoInst<iops>, Requires<[HasVFP2]>; -class NEONAsmPseudo<dag iops> : AsmPseudoInst<iops>, Requires<[HasNEON]>; +class ARMAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, + Requires<[IsARM]>; +class tAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, + Requires<[IsThumb]>; +class t2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, + Requires<[IsThumb2]>; +class VFP2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, + Requires<[HasVFP2]>; +class NEONAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>, + Requires<[HasNEON]>; // Pseudo instructions for the code generator. class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern> diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index af98af8..359053c 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -4994,3 +4994,12 @@ def : MnemonicAlias<"usubaddx", "usax">; // for isel. def : ARMInstAlias<"mov${s}${p} $Rd, $imm", (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>; + +// The shifter forms of the MOV instruction are aliased to the ASR, LSL, +// LSR, ROR, and RRX instructions. +// FIXME: We need C++ parser hooks to map the alias to the MOV +// encoding. It seems we should be able to do that sort of thing +// in tblgen, but it could get ugly. +def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", + (ins GPR:$Rd, GPR:$Rm, imm1_32:$imm, pred:$p, + cc_out:$s)>; diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index cb0c97b..e68ecec 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -4541,6 +4541,21 @@ void ARMAsmParser:: processInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { switch (Inst.getOpcode()) { + // Handle the MOV complex aliases. + case ARM::ASRi: { + unsigned Amt = Inst.getOperand(2).getImm() + 1; + unsigned ShiftOp = ARM_AM::getSORegOpc(ARM_AM::asr, Amt); + MCInst TmpInst; + TmpInst.setOpcode(ARM::MOVsi); + TmpInst.addOperand(Inst.getOperand(0)); // Rd + TmpInst.addOperand(Inst.getOperand(1)); // Rn + TmpInst.addOperand(MCOperand::CreateImm(ShiftOp)); // Shift value and ty + TmpInst.addOperand(Inst.getOperand(3)); // CondCode + TmpInst.addOperand(Inst.getOperand(4)); + TmpInst.addOperand(Inst.getOperand(5)); // cc_out + Inst = TmpInst; + break; + } case ARM::LDMIA_UPD: // If this is a load of a single register via a 'pop', then we should use // a post-indexed LDR instruction instead, per the ARM ARM. diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 55d9f02..f2f6a94 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -257,8 +257,15 @@ Lforward: @ CHECK: and r10, r10, r1, rrx @ encoding: [0x61,0xa0,0x0a,0xe0] @------------------------------------------------------------------------------ -@ FIXME: ASR +@ ASR @------------------------------------------------------------------------------ + asr r2, r4, #32 + asr r2, r4, #2 + +@ CHECK: asr r2, r4, #32 @ encoding: [0x44,0x20,0xa0,0xe1] +@ CHECK: asr r2, r4, #2 @ encoding: [0x44,0x21,0xa0,0xe1] + + @------------------------------------------------------------------------------ @ B @------------------------------------------------------------------------------ |