diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 23 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/ppcf128-3.ll | 32 |
2 files changed, 45 insertions, 10 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index a8217b9..56ac375 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -6713,6 +6713,19 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ case ISD::UINT_TO_FP: { bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); + + // Promote the operand if needed. Do this before checking for + // ppcf128 so conversions of i16 and i8 work. + if (getTypeAction(SrcVT) == Promote) { + SDOperand Tmp = PromoteOp(Node->getOperand(0)); + Tmp = isSigned + ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, + DAG.getValueType(SrcVT)) + : DAG.getZeroExtendInReg(Tmp, SrcVT); + Node = DAG.UpdateNodeOperands(Op, Tmp).Val; + SrcVT = Node->getOperand(0).getValueType(); + } + if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { static const uint64_t zero = 0; if (isSigned) { @@ -6757,16 +6770,6 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ break; } - // Promote the operand if needed. - if (getTypeAction(SrcVT) == Promote) { - SDOperand Tmp = PromoteOp(Node->getOperand(0)); - Tmp = isSigned - ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, - DAG.getValueType(SrcVT)) - : DAG.getZeroExtendInReg(Tmp, SrcVT); - Node = DAG.UpdateNodeOperands(Op, Tmp).Val; - } - Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, Node->getOperand(0)); ExpandOp(Lo, Lo, Hi); diff --git a/test/CodeGen/PowerPC/ppcf128-3.ll b/test/CodeGen/PowerPC/ppcf128-3.ll new file mode 100644 index 0000000..3a51f4d --- /dev/null +++ b/test/CodeGen/PowerPC/ppcf128-3.ll @@ -0,0 +1,32 @@ +; RUN: llvm-as < %s | llc -march=ppc32 + %struct.stp_sequence = type { double, double } + +define i32 @stp_sequence_set_short_data(%struct.stp_sequence* %sequence, i32 %count, i16* %data) { +entry: + %tmp1112 = sitofp i16 0 to ppc_fp128 ; <ppc_fp128> [#uses=1] + %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] + ret i32 0 +} + +define i32 @stp_sequence_set_short_data2(%struct.stp_sequence* %sequence, i32 %count, i16* %data) { +entry: + %tmp1112 = sitofp i8 0 to ppc_fp128 ; <ppc_fp128> [#uses=1] + %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] + ret i32 0 +} + +define i32 @stp_sequence_set_short_data3(%struct.stp_sequence* %sequence, i32 %count, i16* %data) { +entry: + %tmp1112 = uitofp i16 0 to ppc_fp128 ; <ppc_fp128> [#uses=1] + %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] + ret i32 0 +} + +define i32 @stp_sequence_set_short_data4(%struct.stp_sequence* %sequence, i32 %count, i16* %data) { +entry: + %tmp1112 = uitofp i8 0 to ppc_fp128 ; <ppc_fp128> [#uses=1] + %tmp13 = call i32 (...)* @__inline_isfinite( ppc_fp128 %tmp1112 ) nounwind ; <i32> [#uses=0] + ret i32 0 +} + +declare i32 @__inline_isfinite(...) |