diff options
Diffstat (limited to 'lib/CodeGen/SelectionDAG/LegalizeDAG.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index a8217b9..56ac375 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -6713,6 +6713,19 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ case ISD::UINT_TO_FP: { bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); + + // Promote the operand if needed. Do this before checking for + // ppcf128 so conversions of i16 and i8 work. + if (getTypeAction(SrcVT) == Promote) { + SDOperand Tmp = PromoteOp(Node->getOperand(0)); + Tmp = isSigned + ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, + DAG.getValueType(SrcVT)) + : DAG.getZeroExtendInReg(Tmp, SrcVT); + Node = DAG.UpdateNodeOperands(Op, Tmp).Val; + SrcVT = Node->getOperand(0).getValueType(); + } + if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { static const uint64_t zero = 0; if (isSigned) { @@ -6757,16 +6770,6 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ break; } - // Promote the operand if needed. - if (getTypeAction(SrcVT) == Promote) { - SDOperand Tmp = PromoteOp(Node->getOperand(0)); - Tmp = isSigned - ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, - DAG.getValueType(SrcVT)) - : DAG.getZeroExtendInReg(Tmp, SrcVT); - Node = DAG.UpdateNodeOperands(Op, Tmp).Val; - } - Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, Node->getOperand(0)); ExpandOp(Lo, Lo, Hi); |