diff options
| -rw-r--r-- | lib/Target/Mips/MipsInstrFormats.td | 28 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 21 | ||||
| -rw-r--r-- | test/MC/Mips/mips_directives.s | 10 |
3 files changed, 59 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index 14cfcf9..6073476 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -491,6 +491,34 @@ class TEQ_FM<bits<6> funct> { } //===----------------------------------------------------------------------===// +// System calls format <op|code_|funct> +//===----------------------------------------------------------------------===// + +class SYS_FM<bits<6> funct> +{ + bits<20> code_; + bits<32> Inst; + let Inst{31-26} = 0x0; + let Inst{25-6} = code_; + let Inst{5-0} = funct; +} + +//===----------------------------------------------------------------------===// +// Break instruction format <op|code_1|funct> +//===----------------------------------------------------------------------===// + +class BRK_FM<bits<6> funct> +{ + bits<10> code_1; + bits<10> code_2; + bits<32> Inst; + let Inst{31-26} = 0x0; + let Inst{25-16} = code_1; + let Inst{15-6} = code_2; + let Inst{5-0} = funct; +} + +//===----------------------------------------------------------------------===// // // FLOATING POINT INSTRUCTION FORMATS // diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index d2164f7..712e204 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -250,6 +250,12 @@ def simm16 : Operand<i32> { def simm20 : Operand<i32> { } +def uimm20 : Operand<i32> { +} + +def uimm10 : Operand<i32> { +} + def simm16_64 : Operand<i64>; def shamt : Operand<i32>; @@ -637,6 +643,14 @@ class BAL_FT : let hasDelaySlot = 1; let Defs = [RA]; } +// Syscall +class SYS_FT<string opstr> : + InstSE<(outs), (ins uimm20:$code_), + !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>; +// Break +class BRK_FT<string opstr> : + InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2), + !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>; // Sync let hasSideEffects = 1 in @@ -941,6 +955,9 @@ defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; def SYNC : SYNC_FT, SYNC_FM; def TEQ : TEQ_FT<"teq", CPURegsOpnd>, TEQ_FM<0x34>; +def BREAK : BRK_FT<"break">, BRK_FM<0xd>; +def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>; + /// Load-linked, Store-conditional let Predicates = [NotN64, HasStdEnc] in { def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; @@ -1119,6 +1136,10 @@ def : InstAlias<"bnez $rs,$offset", def : InstAlias<"beqz $rs,$offset", (BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>, Requires<[NotMips64]>; +def : InstAlias<"syscall", (SYSCALL 0), 1>; + +def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; +def : InstAlias<"break", (BREAK 0, 0), 1>; //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions //===----------------------------------------------------------------------===// diff --git a/test/MC/Mips/mips_directives.s b/test/MC/Mips/mips_directives.s index bbb2616..c29806a 100644 --- a/test/MC/Mips/mips_directives.s +++ b/test/MC/Mips/mips_directives.s @@ -41,5 +41,15 @@ $JTI0_0: .set f6,$f6 # CHECK: abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85] # CHECK: and $3, $15, $15 # encoding: [0x01,0xef,0x18,0x24] +# CHECK: break # encoding: [0x00,0x00,0x00,0x0d] +# CHECK: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d] +# CHECK: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d] +# CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c] +# CHECK: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c] abs.s f6,FPU_MASK and r3,$t7,STORE_MASK + break + break 7 + break 7,5 + syscall + syscall 0x3454 |