diff options
Diffstat (limited to 'include/llvm/Target')
| -rw-r--r-- | include/llvm/Target/Target.td | 11 | ||||
| -rw-r--r-- | include/llvm/Target/TargetMachine.h | 112 | ||||
| -rw-r--r-- | include/llvm/Target/TargetOptions.h | 6 | ||||
| -rw-r--r-- | include/llvm/Target/TargetRegisterInfo.h | 3 | ||||
| -rw-r--r-- | include/llvm/Target/TargetSubtargetInfo.h | 27 |
5 files changed, 82 insertions, 77 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index 6c970d0..1ff8db8 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -207,6 +207,12 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, // The function should return 0 to select the default order defined by // MemberList, 1 to select the first AltOrders entry and so on. code AltOrderSelect = [{}]; + + // Specify allocation priority for register allocators using a greedy + // heuristic. Classes with higher priority values are assigned first. This is + // useful as it is sometimes beneficial to assign registers to highly + // constrained classes first. The value has to be in the range [0,63]. + int AllocationPriority = 0; } // The memberList in a RegisterClass is a dag of set operations. TableGen @@ -1015,6 +1021,11 @@ class AsmWriter { // name. string AsmWriterClassName = "InstPrinter"; + // PassSubtarget - Determines whether MCSubtargetInfo should be passed to + // the various print methods. + // FIXME: Remove after all ports are updated. + int PassSubtarget = 0; + // Variant - AsmWriters can be of multiple different variants. Variants are // used to support targets that need to emit assembly code in ways that are // mostly the same for different targets, but have minor differences in diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index 87aba9f..2a1ce04 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -48,6 +48,7 @@ class TargetSubtargetInfo; class TargetTransformInfo; class formatted_raw_ostream; class raw_ostream; +class raw_pwrite_stream; class TargetLoweringObjectFile; // The old pass manager infrastructure is hidden in a legacy namespace now. @@ -58,9 +59,9 @@ using legacy::PassManagerBase; //===----------------------------------------------------------------------===// /// -/// TargetMachine - Primary interface to the complete machine description for -/// the target machine. All target-specific information should be accessible -/// through this interface. +/// Primary interface to the complete machine description for the target +/// machine. All target-specific information should be accessible through this +/// interface. /// class TargetMachine { TargetMachine(const TargetMachine &) = delete; @@ -70,25 +71,25 @@ protected: // Can only create subclasses. StringRef TargetTriple, StringRef CPU, StringRef FS, const TargetOptions &Options); - /// TheTarget - The Target that this machine was created for. + /// The Target that this machine was created for. const Target &TheTarget; - /// DataLayout - For ABI type size and alignment. + /// For ABI type size and alignment. const DataLayout DL; - /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target - /// feature strings the TargetMachine instance is created with. + /// Triple string, CPU name, and target feature strings the TargetMachine + /// instance is created with. std::string TargetTriple; std::string TargetCPU; std::string TargetFS; - /// CodeGenInfo - Low level target information such as relocation model. - /// Non-const to allow resetting optimization level per-function. + /// Low level target information such as relocation model. Non-const to + /// allow resetting optimization level per-function. MCCodeGenInfo *CodeGenInfo; - /// AsmInfo - Contains target specific asm information. - /// + /// Contains target specific asm information. const MCAsmInfo *AsmInfo; + const MCRegisterInfo *MRI; const MCInstrInfo *MII; const MCSubtargetInfo *STI; @@ -106,8 +107,8 @@ public: StringRef getTargetCPU() const { return TargetCPU; } StringRef getTargetFeatureString() const { return TargetFS; } - /// getSubtargetImpl - virtual method implemented by subclasses that returns - /// a reference to that target's TargetSubtargetInfo-derived member variable. + /// Virtual method implemented by subclasses that returns a reference to that + /// target's TargetSubtargetInfo-derived member variable. virtual const TargetSubtargetInfo *getSubtargetImpl(const Function &) const { return nullptr; } @@ -115,15 +116,15 @@ public: return nullptr; } - /// getSubtarget - This method returns a pointer to the specified type of + /// This method returns a pointer to the specified type of /// TargetSubtargetInfo. In debug builds, it verifies that the object being /// returned is of the correct type. template <typename STC> const STC &getSubtarget(const Function &F) const { return *static_cast<const STC*>(getSubtargetImpl(F)); } - /// getDataLayout - This method returns a pointer to the DataLayout for - /// the target. It should be unchanging for every subtarget. + /// This method returns a pointer to the DataLayout for the target. It should + /// be unchanging for every subtarget. const DataLayout *getDataLayout() const { return &DL; } /// \brief Reset the target options based on the function's attributes. @@ -131,16 +132,14 @@ public: // from TargetMachine. void resetTargetOptions(const Function &F) const; - /// getMCAsmInfo - Return target specific asm information. - /// + /// Return target specific asm information. const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; } + const MCRegisterInfo *getMCRegisterInfo() const { return MRI; } const MCInstrInfo *getMCInstrInfo() const { return MII; } const MCSubtargetInfo *getMCSubtargetInfo() const { return STI; } - /// getIntrinsicInfo - If intrinsic information is available, return it. If - /// not, return null. - /// + /// If intrinsic information is available, return it. If not, return null. virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return nullptr; } @@ -148,20 +147,18 @@ public: bool requiresStructuredCFG() const { return RequireStructuredCFG; } void setRequiresStructuredCFG(bool Value) { RequireStructuredCFG = Value; } - /// getRelocationModel - Returns the code generation relocation model. The - /// choices are static, PIC, and dynamic-no-pic, and target default. + /// Returns the code generation relocation model. The choices are static, PIC, + /// and dynamic-no-pic, and target default. Reloc::Model getRelocationModel() const; - /// getCodeModel - Returns the code model. The choices are small, kernel, - /// medium, large, and target default. + /// Returns the code model. The choices are small, kernel, medium, large, and + /// target default. CodeModel::Model getCodeModel() const; - /// getTLSModel - Returns the TLS model which should be used for the given - /// global variable. + /// Returns the TLS model which should be used for the given global variable. TLSModel::Model getTLSModel(const GlobalValue *GV) const; - /// getOptLevel - Returns the optimization level: None, Less, - /// Default, or Aggressive. + /// Returns the optimization level: None, Less, Default, or Aggressive. CodeGenOpt::Level getOptLevel() const; /// \brief Overrides the optimization level. @@ -198,21 +195,20 @@ public: /// uses this to answer queries about the IR. virtual TargetIRAnalysis getTargetIRAnalysis(); - /// CodeGenFileType - These enums are meant to be passed into - /// addPassesToEmitFile to indicate what type of file to emit, and returned by - /// it to indicate what type of file could actually be made. + /// These enums are meant to be passed into addPassesToEmitFile to indicate + /// what type of file to emit, and returned by it to indicate what type of + /// file could actually be made. enum CodeGenFileType { CGFT_AssemblyFile, CGFT_ObjectFile, CGFT_Null // Do not emit any output. }; - /// addPassesToEmitFile - Add passes to the specified pass manager to get the - /// specified file emitted. Typically this will involve several steps of code - /// generation. This method should return true if emission of this file type - /// is not supported, or false on success. - virtual bool addPassesToEmitFile(PassManagerBase &, - formatted_raw_ostream &, + /// Add passes to the specified pass manager to get the specified file + /// emitted. Typically this will involve several steps of code generation. + /// This method should return true if emission of this file type is not + /// supported, or false on success. + virtual bool addPassesToEmitFile(PassManagerBase &, raw_pwrite_stream &, CodeGenFileType, bool /*DisableVerify*/ = true, AnalysisID /*StartAfter*/ = nullptr, @@ -220,14 +216,13 @@ public: return true; } - /// addPassesToEmitMC - Add passes to the specified pass manager to get - /// machine code emitted with the MCJIT. This method returns true if machine - /// code is not supported. It fills the MCContext Ctx pointer which can be - /// used to build custom MCStreamer. + /// Add passes to the specified pass manager to get machine code emitted with + /// the MCJIT. This method returns true if machine code is not supported. It + /// fills the MCContext Ctx pointer which can be used to build custom + /// MCStreamer. /// - virtual bool addPassesToEmitMC(PassManagerBase &, - MCContext *&, - raw_ostream &, + virtual bool addPassesToEmitMC(PassManagerBase &, MCContext *&, + raw_pwrite_stream &, bool /*DisableVerify*/ = true) { return true; } @@ -237,8 +232,8 @@ public: MCSymbol *getSymbol(const GlobalValue *GV, Mangler &Mang) const; }; -/// LLVMTargetMachine - This class describes a target machine that is -/// implemented with the LLVM target-independent code generator. +/// This class describes a target machine that is implemented with the LLVM +/// target-independent code generator. /// class LLVMTargetMachine : public TargetMachine { protected: // Can only create subclasses. @@ -255,25 +250,24 @@ public: /// generator to answer queries about the IR. TargetIRAnalysis getTargetIRAnalysis() override; - /// createPassConfig - Create a pass configuration object to be used by - /// addPassToEmitX methods for generating a pipeline of CodeGen passes. + /// Create a pass configuration object to be used by addPassToEmitX methods + /// for generating a pipeline of CodeGen passes. virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); - /// addPassesToEmitFile - Add passes to the specified pass manager to get the - /// specified file emitted. Typically this will involve several steps of code - /// generation. - bool addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out, + /// Add passes to the specified pass manager to get the specified file + /// emitted. Typically this will involve several steps of code generation. + bool addPassesToEmitFile(PassManagerBase &PM, raw_pwrite_stream &Out, CodeGenFileType FileType, bool DisableVerify = true, AnalysisID StartAfter = nullptr, AnalysisID StopAfter = nullptr) override; - /// addPassesToEmitMC - Add passes to the specified pass manager to get - /// machine code emitted with the MCJIT. This method returns true if machine - /// code is not supported. It fills the MCContext Ctx pointer which can be - /// used to build custom MCStreamer. - /// + /// Add passes to the specified pass manager to get machine code emitted with + /// the MCJIT. This method returns true if machine code is not supported. It + /// fills the MCContext Ctx pointer which can be used to build custom + /// MCStreamer. bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx, - raw_ostream &OS, bool DisableVerify = true) override; + raw_pwrite_stream &OS, + bool DisableVerify = true) override; }; } // End llvm namespace diff --git a/include/llvm/Target/TargetOptions.h b/include/llvm/Target/TargetOptions.h index f447fd6..d41ca99 100644 --- a/include/llvm/Target/TargetOptions.h +++ b/include/llvm/Target/TargetOptions.h @@ -212,9 +212,9 @@ namespace llvm { /// FloatABIType - This setting is set by -float-abi=xxx option is specfied /// on the command line. This setting may either be Default, Soft, or Hard. /// Default selects the target's default behavior. Soft selects the ABI for - /// UseSoftFloat, but does not indicate that FP hardware may not be used. - /// Such a combination is unfortunately popular (e.g. arm-apple-darwin). - /// Hard presumes that the normal FP ABI is used. + /// software floating point, but does not indicate that FP hardware may not + /// be used. Such a combination is unfortunately popular (e.g. + /// arm-apple-darwin). Hard presumes that the normal FP ABI is used. FloatABI::ABIType FloatABIType; /// AllowFPOpFusion - This flag is set by the -fuse-fp-ops=xxx option. diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h index 4184052..121b8a2 100644 --- a/include/llvm/Target/TargetRegisterInfo.h +++ b/include/llvm/Target/TargetRegisterInfo.h @@ -46,6 +46,9 @@ public: const uint32_t *SubClassMask; const uint16_t *SuperRegIndices; const unsigned LaneMask; + /// Classes with a higher priority value are assigned first by register + /// allocators using a greedy heuristic. The value is in the range [0,63]. + const uint8_t AllocationPriority; /// Whether the class supports two (or more) disjunct subregister indices. const bool HasDisjunctSubRegs; const sc_iterator SuperClasses; diff --git a/include/llvm/Target/TargetSubtargetInfo.h b/include/llvm/Target/TargetSubtargetInfo.h index bb5409b6..0f42790 100644 --- a/include/llvm/Target/TargetSubtargetInfo.h +++ b/include/llvm/Target/TargetSubtargetInfo.h @@ -42,15 +42,17 @@ template <typename T> class SmallVectorImpl; /// be exposed through a TargetSubtargetInfo-derived class. /// class TargetSubtargetInfo : public MCSubtargetInfo { - TargetSubtargetInfo(const TargetSubtargetInfo&) = delete; - void operator=(const TargetSubtargetInfo&) = delete; + TargetSubtargetInfo(const TargetSubtargetInfo &) = delete; + void operator=(const TargetSubtargetInfo &) = delete; + protected: // Can only create subclasses... TargetSubtargetInfo(); + public: // AntiDepBreakMode - Type of anti-dependence breaking that should // be performed before post-RA scheduling. typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode; - typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector; + typedef SmallVectorImpl<const TargetRegisterClass *> RegClassVector; virtual ~TargetSubtargetInfo(); @@ -89,8 +91,9 @@ public: /// MCSchedClassDesc with the isVariant property. This may return the ID of /// another variant SchedClass, but repeated invocation must quickly terminate /// in a nonvariant SchedClass. - virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, - const TargetSchedModel* SchedModel) const { + virtual unsigned resolveSchedClass(unsigned SchedClass, + const MachineInstr *MI, + const TargetSchedModel *SchedModel) const { return 0; } @@ -128,20 +131,16 @@ public: /// scheduling heuristics (no custom MachineSchedStrategy) to make /// changes to the generic scheduling policy. virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, - MachineInstr *begin, - MachineInstr *end, + MachineInstr *begin, MachineInstr *end, unsigned NumRegionInstrs) const {} // \brief Perform target specific adjustments to the latency of a schedule // dependency. - virtual void adjustSchedDependency(SUnit *def, SUnit *use, - SDep& dep) const { } + virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {} // For use with PostRAScheduling: get the anti-dependence breaking that should // be performed before post-RA scheduling. - virtual AntiDepBreakMode getAntiDepBreakMode() const { - return ANTIDEP_NONE; - } + virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; } // For use with PostRAScheduling: in CriticalPathRCs, return any register // classes that should only be considered for anti-dependence breaking if they @@ -177,9 +176,7 @@ public: } /// Enable tracking of subregister liveness in register allocator. - virtual bool enableSubRegLiveness() const { - return false; - } + virtual bool enableSubRegLiveness() const { return false; } }; } // End llvm namespace |