aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/llvm/CodeGen/ScheduleDAGInstrs.h4
-rw-r--r--include/llvm/CodeGen/TargetSchedule.h28
-rw-r--r--include/llvm/MC/MCSchedule.h25
-rw-r--r--include/llvm/MC/MCSubtargetInfo.h14
-rw-r--r--include/llvm/Target/TargetInstrInfo.h3
-rw-r--r--include/llvm/Target/TargetSubtargetInfo.h19
6 files changed, 22 insertions, 71 deletions
diff --git a/include/llvm/CodeGen/ScheduleDAGInstrs.h b/include/llvm/CodeGen/ScheduleDAGInstrs.h
index d13ee84..8b52b5a 100644
--- a/include/llvm/CodeGen/ScheduleDAGInstrs.h
+++ b/include/llvm/CodeGen/ScheduleDAGInstrs.h
@@ -18,7 +18,6 @@
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
-#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/SmallSet.h"
@@ -182,9 +181,6 @@ namespace llvm {
/// Live Intervals provides reaching defs in preRA scheduling.
LiveIntervals *LIS;
- /// TargetSchedModel provides an interface to the machine model.
- TargetSchedModel SchedModel;
-
/// isPostRA flag indicates vregs cannot be present.
bool IsPostRA;
diff --git a/include/llvm/CodeGen/TargetSchedule.h b/include/llvm/CodeGen/TargetSchedule.h
index d2a26af..5023f49 100644
--- a/include/llvm/CodeGen/TargetSchedule.h
+++ b/include/llvm/CodeGen/TargetSchedule.h
@@ -45,33 +45,17 @@ public:
/// Return true if this machine model includes an instruction-level scheduling
/// model. This is more detailed than the course grain IssueWidth and default
/// latency properties, but separate from the per-cycle itinerary data.
- bool hasInstrSchedModel() const { return SchedModel.hasInstrSchedModel(); }
+ bool hasInstrSchedModel() const {
+ return SchedModel.hasInstrSchedModel();
+ }
/// Return true if this machine model includes cycle-to-cycle itinerary
/// data. This models scheduling at each stage in the processor pipeline.
- bool hasInstrItineraries() const { return !InstrItins.isEmpty(); }
-
- /// computeOperandLatency - Compute and return the latency of the given data
- /// dependent def and use when the operand indices are already known. UseMI
- /// may be NULL for an unknown user.
- ///
- /// FindMin may be set to get the minimum vs. expected latency. Minimum
- /// latency is used for scheduling groups, while expected latency is for
- /// instruction cost and critical path.
- unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
- const MachineInstr *UseMI, unsigned UseOperIdx,
- bool FindMin) const;
+ bool hasInstrItineraries() const {
+ return SchedModel.hasInstrItineraries();
+ }
unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
-
-private:
- /// getDefLatency is a helper for computeOperandLatency. Return the
- /// instruction's latency if operand lookup is not required.
- /// Otherwise return -1.
- int getDefLatency(const MachineInstr *DefMI, bool FindMin) const;
-
- /// Return the MCSchedClassDesc for this instruction.
- const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
};
} // namespace llvm
diff --git a/include/llvm/MC/MCSchedule.h b/include/llvm/MC/MCSchedule.h
index 41bdb02..af68a29 100644
--- a/include/llvm/MC/MCSchedule.h
+++ b/include/llvm/MC/MCSchedule.h
@@ -172,8 +172,10 @@ private:
unsigned ProcID;
const MCProcResourceDesc *ProcResourceTable;
const MCSchedClassDesc *SchedClassTable;
+#ifndef NDEBUG
unsigned NumProcResourceKinds;
unsigned NumSchedClasses;
+#endif
// Instruction itinerary tables used by InstrItineraryData.
friend class InstrItineraryData;
const InstrItinerary *InstrItineraries;
@@ -188,27 +190,26 @@ public:
LoadLatency(DefaultLoadLatency),
HighLatency(DefaultHighLatency),
MispredictPenalty(DefaultMispredictPenalty),
- ProcID(0), ProcResourceTable(0), SchedClassTable(0),
- NumProcResourceKinds(0), NumSchedClasses(0),
- InstrItineraries(0) {
- (void)NumProcResourceKinds;
- (void)NumSchedClasses;
- }
+ ProcID(0), InstrItineraries(0) {}
// Table-gen driven ctor.
MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl, unsigned mp,
- unsigned pi, const MCProcResourceDesc *pr,
- const MCSchedClassDesc *sc, unsigned npr, unsigned nsc,
const InstrItinerary *ii):
IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl),
- MispredictPenalty(mp), ProcID(pi), ProcResourceTable(pr),
- SchedClassTable(sc), NumProcResourceKinds(npr), NumSchedClasses(nsc),
- InstrItineraries(ii) {}
+ MispredictPenalty(mp), ProcID(0), ProcResourceTable(0),
+ SchedClassTable(0), InstrItineraries(ii) {}
unsigned getProcessorID() const { return ProcID; }
/// Does this machine model include instruction-level scheduling.
- bool hasInstrSchedModel() const { return SchedClassTable; }
+ bool hasInstrSchedModel() const {
+ return SchedClassTable;
+ }
+
+ /// Does this machine model include cycle-to-cycle itineraries.
+ bool hasInstrItineraries() const {
+ return InstrItineraries;
+ }
const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
assert(hasInstrSchedModel() && "No scheduling machine model");
diff --git a/include/llvm/MC/MCSubtargetInfo.h b/include/llvm/MC/MCSubtargetInfo.h
index 451f435..d1d4047 100644
--- a/include/llvm/MC/MCSubtargetInfo.h
+++ b/include/llvm/MC/MCSubtargetInfo.h
@@ -36,7 +36,6 @@ class MCSubtargetInfo {
const MCWriteProcResEntry *WriteProcResTable;
const MCWriteLatencyEntry *WriteLatencyTable;
const MCReadAdvanceEntry *ReadAdvanceTable;
- const MCSchedModel *CPUSchedModel;
const InstrStage *Stages; // Instruction itinerary stages
const unsigned *OperandCycles; // Itinerary operand cycles
@@ -50,9 +49,6 @@ public:
const SubtargetFeatureKV *PF,
const SubtargetFeatureKV *PD,
const SubtargetInfoKV *ProcSched,
- const MCWriteProcResEntry *WPR,
- const MCWriteLatencyEntry *WL,
- const MCReadAdvanceEntry *RA,
const InstrStage *IS,
const unsigned *OC, const unsigned *FP,
unsigned NF, unsigned NP);
@@ -68,9 +64,9 @@ public:
return FeatureBits;
}
- /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
- /// feature string). Recompute feature bits and scheduling model.
- void InitMCProcessorInfo(StringRef CPU, StringRef FS);
+ /// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
+ /// feature string), recompute and return feature bits.
+ uint64_t ReInitMCSubtargetInfo(StringRef CPU, StringRef FS);
/// ToggleFeature - Toggle a feature and returns the re-computed feature
/// bits. This version does not change the implied bits.
@@ -84,10 +80,6 @@ public:
///
const MCSchedModel *getSchedModelForCPU(StringRef CPU) const;
- /// getSchedModel - Get the machine model for this subtarget's CPU.
- ///
- const MCSchedModel *getSchedModel() const { return CPUSchedModel; }
-
/// Return an iterator at the first process resource consumed by the given
/// scheduling class.
const MCWriteProcResEntry *getWriteProcResBegin(
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index c5c5a7a..bdf6a6d 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -824,9 +824,6 @@ public:
unsigned defaultDefLatency(const MCSchedModel *SchedModel,
const MachineInstr *DefMI) const;
- int computeDefOperandLatency(const InstrItineraryData *ItinData,
- const MachineInstr *DefMI, bool FindMin) const;
-
/// isHighLatencyDef - Return true if this opcode has high latency to its
/// result.
virtual bool isHighLatencyDef(int opc) const { return false; }
diff --git a/include/llvm/Target/TargetSubtargetInfo.h b/include/llvm/Target/TargetSubtargetInfo.h
index 0b294a3..8c6c695 100644
--- a/include/llvm/Target/TargetSubtargetInfo.h
+++ b/include/llvm/Target/TargetSubtargetInfo.h
@@ -14,7 +14,6 @@
#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
#define LLVM_TARGET_TARGETSUBTARGETINFO_H
-#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/CodeGen.h"
@@ -44,24 +43,6 @@ public:
virtual ~TargetSubtargetInfo();
- /// Initialize a copy of the scheduling model for this subtarget.
- /// TargetSchedModel provides the interface for the subtarget's
- /// instruction scheduling information.
- void initSchedModel(TargetSchedModel &SchedModel,
- const TargetInstrInfo *TII) const {
- // CPUSchedModel is initialized to a static instance by InitMCSubtargetInfo.
- SchedModel.init(*getSchedModel(), this, TII);
- }
-
- /// Resolve a SchedClass at runtime, where SchedClass identifies an
- /// MCSchedClassDesc with the isVariant property. This may return the ID of
- /// another variant SchedClass, but repeated invocation must quickly terminate
- /// in a nonvariant SchedClass.
- virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,
- const TargetSchedModel* SchedModel) const {
- return 0;
- }
-
/// getSpecialAddressLatency - For targets where it is beneficial to
/// backschedule instructions that compute addresses, return a value
/// indicating the number of scheduling cycles of backscheduling that
generated by cgit v1.1 at 2025-08-18 08:11:06 +0000