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Diffstat (limited to 'lib/Target/AArch64/AArch64InstrFormats.td')
-rw-r--r-- | lib/Target/AArch64/AArch64InstrFormats.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td index 2b0f5d2..d295c02 100644 --- a/lib/Target/AArch64/AArch64InstrFormats.td +++ b/lib/Target/AArch64/AArch64InstrFormats.td @@ -4383,7 +4383,7 @@ class BaseSIMDVectorLShiftLongBySize<bit Q, bits<2> size, } multiclass SIMDVectorLShiftLongBySizeBHS { - let neverHasSideEffects = 1 in { + let hasSideEffects = 0 in { def v8i8 : BaseSIMDVectorLShiftLongBySize<0, 0b00, V64, "shll", ".8h", ".8b", "8">; def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128, |