diff options
Diffstat (limited to 'lib/Target/Hexagon/HexagonISelLowering.cpp')
| -rw-r--r-- | lib/Target/Hexagon/HexagonISelLowering.cpp | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp index 9241df1..b76de22 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -449,7 +449,7 @@ HexagonTargetLowering::LowerCall(SDValue Chain, SDValue Callee, switch (VA.getLocInfo()) { default: // Loc info must be one of Full, SExt, ZExt, or AExt. - assert(0 && "Unknown loc info!"); + llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: @@ -1345,12 +1345,12 @@ bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { SDValue HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { - default: assert(0 && "Should not custom lower this!"); + default: llvm_unreachable("Should not custom lower this!"); // Frame & Return address. Currently unimplemented. case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); case ISD::GlobalTLSAddress: - assert(0 && "TLS not implemented for Hexagon."); + llvm_unreachable("TLS not implemented for Hexagon."); case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG); @@ -1382,10 +1382,8 @@ const { FuncInfo->addAllocaAdjustInst(MI); return BB; } - default: - assert(false && "Unexpected instr type to insert"); + default: llvm_unreachable("Unexpected instr type to insert"); } // switch - return NULL; } //===----------------------------------------------------------------------===// @@ -1401,7 +1399,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(const case 'r': // R0-R31 switch (VT.getSimpleVT().SimpleTy) { default: - assert(0 && "getRegForInlineAsmConstraint Unhandled data type"); + llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type"); case MVT::i32: case MVT::i16: case MVT::i8: @@ -1410,7 +1408,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(const return std::make_pair(0U, Hexagon::DoubleRegsRegisterClass); } default: - assert(0 && "Unknown asm register class"); + llvm_unreachable("Unknown asm register class"); } } |