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-rw-r--r--lib/Target/Hexagon/HexagonAsmPrinter.cpp6
-rw-r--r--lib/Target/Hexagon/HexagonCFGOptimizer.cpp2
-rw-r--r--lib/Target/Hexagon/HexagonISelDAGToDAG.cpp4
-rw-r--r--lib/Target/Hexagon/HexagonISelLowering.cpp14
-rw-r--r--lib/Target/Hexagon/HexagonInstrInfo.cpp15
-rw-r--r--lib/Target/Hexagon/HexagonRegisterInfo.cpp8
6 files changed, 21 insertions, 28 deletions
diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp
index e2f7992..5402374 100644
--- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp
+++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp
@@ -318,14 +318,14 @@ bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
if (Base.isReg())
printOperand(MI, OpNo, O);
else
- assert(0 && "Unimplemented");
+ llvm_unreachable("Unimplemented");
if (Offset.isImm()) {
if (Offset.getImm())
O << " + #" << Offset.getImm();
}
else
- assert(0 && "Unimplemented");
+ llvm_unreachable("Unimplemented");
return false;
}
@@ -333,7 +333,7 @@ bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
void HexagonAsmPrinter::printPredicateOperand(const MachineInstr *MI,
unsigned OpNo,
raw_ostream &O) {
- assert(0 && "Unimplemented");
+ llvm_unreachable("Unimplemented");
}
diff --git a/lib/Target/Hexagon/HexagonCFGOptimizer.cpp b/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
index 433d71c..fc46080 100644
--- a/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
+++ b/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
@@ -84,7 +84,7 @@ HexagonCFGOptimizer::InvertAndChangeJumpTarget(MachineInstr* MI,
break;
default:
- assert(0 && "Cannot handle this case");
+ llvm_unreachable("Cannot handle this case");
}
MI->setDesc(QII->get(NewOpcode));
diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index 2570420..0bbb2d2 100644
--- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -1099,7 +1099,7 @@ SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
ReplaceUses(N, RsPd);
return RsPd;
}
- assert(0 && "Unexpected value type");
+ llvm_unreachable("Unexpected value type");
}
}
return SelectCode(N);
@@ -1145,7 +1145,7 @@ SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
SDValue SDVal = CurDAG->getTargetConstant(Val, MVT::i32);
Ops.push_back(SDVal);
} else {
- assert(0 && "Unimplemented");
+ llvm_unreachable("Unimplemented");
}
}
EVT ReturnValueVT = N->getValueType(0);
diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp
index 9241df1..b76de22 100644
--- a/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -449,7 +449,7 @@ HexagonTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
switch (VA.getLocInfo()) {
default:
// Loc info must be one of Full, SExt, ZExt, or AExt.
- assert(0 && "Unknown loc info!");
+ llvm_unreachable("Unknown loc info!");
case CCValAssign::Full:
break;
case CCValAssign::SExt:
@@ -1345,12 +1345,12 @@ bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
SDValue
HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
- default: assert(0 && "Should not custom lower this!");
+ default: llvm_unreachable("Should not custom lower this!");
// Frame & Return address. Currently unimplemented.
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
case ISD::GlobalTLSAddress:
- assert(0 && "TLS not implemented for Hexagon.");
+ llvm_unreachable("TLS not implemented for Hexagon.");
case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
@@ -1382,10 +1382,8 @@ const {
FuncInfo->addAllocaAdjustInst(MI);
return BB;
}
- default:
- assert(false && "Unexpected instr type to insert");
+ default: llvm_unreachable("Unexpected instr type to insert");
} // switch
- return NULL;
}
//===----------------------------------------------------------------------===//
@@ -1401,7 +1399,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(const
case 'r': // R0-R31
switch (VT.getSimpleVT().SimpleTy) {
default:
- assert(0 && "getRegForInlineAsmConstraint Unhandled data type");
+ llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
case MVT::i32:
case MVT::i16:
case MVT::i8:
@@ -1410,7 +1408,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(const
return std::make_pair(0U, Hexagon::DoubleRegsRegisterClass);
}
default:
- assert(0 && "Unknown asm register class");
+ llvm_unreachable("Unknown asm register class");
}
}
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp
index e83da50..2cc5578 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -383,7 +383,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
.addFrameIndex(FI).addImm(0)
.addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
} else {
- assert(0 && "Unimplemented");
+ llvm_unreachable("Unimplemented");
}
}
@@ -395,8 +395,7 @@ void HexagonInstrInfo::storeRegToAddr(
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const
{
- assert(0 && "Unimplemented");
- return;
+ llvm_unreachable("Unimplemented");
}
@@ -427,7 +426,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
} else {
- assert(0 && "Can't store this register to stack slot");
+ llvm_unreachable("Can't store this register to stack slot");
}
}
@@ -436,7 +435,7 @@ void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const {
- assert(0 && "Unimplemented");
+ llvm_unreachable("Unimplemented");
}
@@ -823,7 +822,7 @@ PredicateInstruction(MachineInstr *MI,
} else if (MO.isImm()) {
MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
} else {
- assert(false && "Unexpected operand type");
+ llvm_unreachable("Unexpected operand type");
}
}
@@ -1269,10 +1268,8 @@ isValidAutoIncImm(const EVT VT, const int Offset) const {
return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
Offset <= Hexagon_MEMB_AUTOINC_MAX);
}
-
- assert(0 && "Not an auto-inc opc!");
- return false;
+ llvm_unreachable("Not an auto-inc opc!");
}
diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/lib/Target/Hexagon/HexagonRegisterInfo.cpp
index 31377a6..6bbc71d 100644
--- a/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+++ b/lib/Target/Hexagon/HexagonRegisterInfo.cpp
@@ -125,7 +125,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
} else if (MI.getOpcode() == Hexagon::ADJCALLSTACKUP) {
// Hexagon_TODO: add code
} else {
- assert(0 && "Cannot handle this call frame pseudo instruction");
+ llvm_unreachable("Cannot handle this call frame pseudo instruction");
}
MBB.erase(I);
}
@@ -305,13 +305,11 @@ void HexagonRegisterInfo::getInitialFrameState(std::vector<MachineMove>
}
unsigned HexagonRegisterInfo::getEHExceptionRegister() const {
- assert(0 && "What is the exception register");
- return 0;
+ llvm_unreachable("What is the exception register");
}
unsigned HexagonRegisterInfo::getEHHandlerRegister() const {
- assert(0 && "What is the exception handler register");
- return 0;
+ llvm_unreachable("What is the exception handler register");
}
#define GET_REGINFO_TARGET_DESC
generated by cgit v1.1 at 2025-08-19 15:16:33 +0000