diff options
Diffstat (limited to 'lib/Target/Hexagon/HexagonInstrFormats.td')
| -rw-r--r-- | lib/Target/Hexagon/HexagonInstrFormats.td | 167 |
1 files changed, 93 insertions, 74 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td index d25bfa8..1057343 100644 --- a/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/lib/Target/Hexagon/HexagonInstrFormats.td @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// Hexagon Intruction Flags + +// Hexagon Instruction Flags + // // *** Must match HexagonBaseInfo.h *** //===----------------------------------------------------------------------===// @@ -68,7 +68,7 @@ def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd) //===----------------------------------------------------------------------===// -// Intruction Class Declaration + +// Instruction Class Declaration + //===----------------------------------------------------------------------===// class OpcodeHexagon { @@ -104,54 +104,72 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, // Solo instructions, i.e., those that cannot be in a packet with others. bits<1> isSolo = 0; let TSFlags{5} = isSolo; + // Packed only with A or X-type instructions. + bits<1> isSoloAX = 0; + let TSFlags{6} = isSoloAX; + // Only A-type instruction in first slot or nothing. + bits<1> isSoloAin1 = 0; + let TSFlags{7} = isSoloAin1; // Predicated instructions. bits<1> isPredicated = 0; - let TSFlags{6} = isPredicated; + let TSFlags{8} = isPredicated; bits<1> isPredicatedFalse = 0; - let TSFlags{7} = isPredicatedFalse; + let TSFlags{9} = isPredicatedFalse; bits<1> isPredicatedNew = 0; - let TSFlags{8} = isPredicatedNew; + let TSFlags{10} = isPredicatedNew; + bits<1> isPredicateLate = 0; + let TSFlags{11} = isPredicateLate; // Late predicate producer insn. // New-value insn helper fields. bits<1> isNewValue = 0; - let TSFlags{9} = isNewValue; // New-value consumer insn. + let TSFlags{12} = isNewValue; // New-value consumer insn. bits<1> hasNewValue = 0; - let TSFlags{10} = hasNewValue; // New-value producer insn. + let TSFlags{13} = hasNewValue; // New-value producer insn. bits<3> opNewValue = 0; - let TSFlags{13-11} = opNewValue; // New-value produced operand. - bits<2> opNewBits = 0; - let TSFlags{15-14} = opNewBits; // New-value opcode bits location: 0, 8, 16. + let TSFlags{16-14} = opNewValue; // New-value produced operand. bits<1> isNVStorable = 0; - let TSFlags{16} = isNVStorable; // Store that can become new-value store. + let TSFlags{17} = isNVStorable; // Store that can become new-value store. bits<1> isNVStore = 0; - let TSFlags{17} = isNVStore; // New-value store insn. + let TSFlags{18} = isNVStore; // New-value store insn. + bits<1> isCVLoadable = 0; + let TSFlags{19} = isCVLoadable; // Load that can become cur-value load. + bits<1> isCVLoad = 0; + let TSFlags{20} = isCVLoad; // Cur-value load insn. // Immediate extender helper fields. bits<1> isExtendable = 0; - let TSFlags{18} = isExtendable; // Insn may be extended. + let TSFlags{21} = isExtendable; // Insn may be extended. bits<1> isExtended = 0; - let TSFlags{19} = isExtended; // Insn must be extended. + let TSFlags{22} = isExtended; // Insn must be extended. bits<3> opExtendable = 0; - let TSFlags{22-20} = opExtendable; // Which operand may be extended. + let TSFlags{25-23} = opExtendable; // Which operand may be extended. bits<1> isExtentSigned = 0; - let TSFlags{23} = isExtentSigned; // Signed or unsigned range. + let TSFlags{26} = isExtentSigned; // Signed or unsigned range. bits<5> opExtentBits = 0; - let TSFlags{28-24} = opExtentBits; //Number of bits of range before extending. + let TSFlags{31-27} = opExtentBits; //Number of bits of range before extending. + bits<2> opExtentAlign = 0; + let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending. // If an instruction is valid on a subtarget (v2-v5), set the corresponding // bit from validSubTargets. v2 is the least significant bit. // By default, instruction is valid on all subtargets. SubTarget validSubTargets = HasV2SubT; - let TSFlags{32-29} = validSubTargets.Value; + let TSFlags{37-34} = validSubTargets.Value; // Addressing mode for load/store instructions. AddrModeType addrMode = NoAddrMode; - let TSFlags{35-33} = addrMode.Value; + let TSFlags{42-40} = addrMode.Value; // Memory access size for mem access instructions (load/store) MemAccessSize accessSize = NoMemAccess; - let TSFlags{38-36} = accessSize.Value; + let TSFlags{45-43} = accessSize.Value; + + bits<1> isTaken = 0; + let TSFlags {47} = isTaken; // Branch prediction. + + bits<1> isFP = 0; + let TSFlags {48} = isFP; // Floating-point. // Fields used for relation models. string BaseOpcode = ""; @@ -173,14 +191,14 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, } //===----------------------------------------------------------------------===// -// Intruction Classes Definitions + +// Instruction Classes Definitions + //===----------------------------------------------------------------------===// // LD Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD>; + string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>; let mayLoad = 1 in class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], @@ -199,16 +217,16 @@ class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [], let mayLoad = 1 in class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : LDInst<outs, ins, asmstr, pattern, cstr>; + string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>; // ST Instruction Class in V2/V3 can take SLOT0 only. // ST Instruction Class in V4 can take SLOT0 & SLOT1. // Definition of the instruction class CHANGED from V2/V3 to V4. let mayStore = 1 in class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST>; + string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>; class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = ""> @@ -216,39 +234,39 @@ class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], let mayStore = 1 in class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, ST0, TypeST>; + string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>; // ST Instruction Class in V2/V3 can take SLOT0 only. // ST Instruction Class in V4 can take SLOT0 & SLOT1. // Definition of the instruction class CHANGED from V2/V3 to V4. class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : STInst<outs, ins, asmstr, pattern, cstr>; + string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01> + : STInst<outs, ins, asmstr, pattern, cstr, itin>; // SYSTEM Instruction Class in V4 can take SLOT0 only // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1. class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, SYS, TypeSYSTEM>; + string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeSYSTEM>; // ALU32 Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU32, TypeALU32>; + string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32>; // ALU64 Instruction Class in V2/V3. // XTYPE Instruction Class in V4. // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4. class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE>; + string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>; class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : ALU64Inst<outs, ins, asmstr, pattern, cstr>; + string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23> + : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>; // M Instruction Class in V2/V3. @@ -256,55 +274,55 @@ class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE>; + string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>; // M Instruction Class in V2/V3. // XTYPE Instruction Class in V4. // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : MInst<outs, ins, asmstr, pattern, cstr>; + string cstr = "", InstrItinClass itin = M_tc_2_SLOT23> + : MInst<outs, ins, asmstr, pattern, cstr, itin>; // S Instruction Class in V2/V3. // XTYPE Instruction Class in V4. // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE>; + string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>; // S Instruction Class in V2/V3. // XTYPE Instruction Class in V4. // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : SInst<outs, ins, asmstr, pattern, cstr>; + string cstr = "", InstrItinClass itin = S_3op_tc_1_SLOT23> + : SInst<outs, ins, asmstr, pattern, cstr, itin>; // J Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, J, TypeJ>; + string cstr = "", InstrItinClass itin = J_tc_2early_SLOT23> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>; // JR Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, JR, TypeJR>; + string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJR>; // CR Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, CR, TypeCR>; + string cstr = "", InstrItinClass itin = CR_tc_2early_SLOT3> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCR>; let isCodeGenOnly = 1, isPseudo = 1 in class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, ENDLOOP, TypeENDLOOP>; + string cstr = "", InstrItinClass itin = J_tc_2early_SLOT0123> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>; let isCodeGenOnly = 1, isPseudo = 1 in class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [], @@ -317,39 +335,40 @@ class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [], : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>; //===----------------------------------------------------------------------===// -// Intruction Classes Definitions - +// Instruction Classes Definitions - //===----------------------------------------------------------------------===// // // ALU32 patterns //. -class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr = ""> - : ALU32Inst<outs, ins, asmstr, pattern, cstr>; +class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> + : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; -class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr = ""> - : ALU32Inst<outs, ins, asmstr, pattern, cstr>; +class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> + : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; -class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr = ""> - : ALU32Inst<outs, ins, asmstr, pattern, cstr>; +class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> + : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; + +class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> + : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; -class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr = ""> - : ALU32Inst<outs, ins, asmstr, pattern, cstr>; // // ALU64 patterns. // -class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr = ""> - : ALU64Inst<outs, ins, asmstr, pattern, cstr>; +class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23> + : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>; -class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr = ""> - : ALU64Inst<outs, ins, asmstr, pattern, cstr>; +class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23> + : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>; // Post increment ST Instruction. class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [], |