diff options
Diffstat (limited to 'lib/Target/Hexagon')
43 files changed, 702 insertions, 586 deletions
diff --git a/lib/Target/Hexagon/Hexagon.td b/lib/Target/Hexagon/Hexagon.td index c1b6d45..5f4a6c6 100644 --- a/lib/Target/Hexagon/Hexagon.td +++ b/lib/Target/Hexagon/Hexagon.td @@ -200,8 +200,6 @@ class Proc<string Name, SchedMachineModel Model, list<SubtargetFeature> Features> : ProcessorModel<Name, Model, Features>; -def : Proc<"hexagonv2", HexagonModel, [ArchV2]>; -def : Proc<"hexagonv3", HexagonModel, [ArchV2, ArchV3]>; def : Proc<"hexagonv4", HexagonModelV4, [ArchV2, ArchV3, ArchV4]>; def : Proc<"hexagonv5", HexagonModelV4, [ArchV2, ArchV3, ArchV4, ArchV5]>; diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp index a588274..2e011bd 100644 --- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -13,7 +13,6 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "asm-printer" #include "Hexagon.h" #include "HexagonAsmPrinter.h" #include "HexagonMachineFunctionInfo.h" @@ -56,6 +55,8 @@ using namespace llvm; +#define DEBUG_TYPE "asm-printer" + static cl::opt<bool> AlignCalls( "hexagon-align-calls", cl::Hidden, cl::init(true), cl::desc("Insert falign after call instruction for Hexagon target")); @@ -224,7 +225,7 @@ static MCInstPrinter *createHexagonMCInstPrinter(const Target &T, if (SyntaxVariant == 0) return(new HexagonInstPrinter(MAI, MII, MRI)); else - return NULL; + return nullptr; } extern "C" void LLVMInitializeHexagonAsmPrinter() { diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.h b/lib/Target/Hexagon/HexagonAsmPrinter.h index a186dc9..7fe8c57 100644 --- a/lib/Target/Hexagon/HexagonAsmPrinter.h +++ b/lib/Target/Hexagon/HexagonAsmPrinter.h @@ -30,21 +30,22 @@ namespace llvm { Subtarget = &TM.getSubtarget<HexagonSubtarget>(); } - virtual const char *getPassName() const { + const char *getPassName() const override { return "Hexagon Assembly Printer"; } - bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const; + bool isBlockOnlyReachableByFallthrough( + const MachineBasicBlock *MBB) const override; - virtual void EmitInstruction(const MachineInstr *MI); + void EmitInstruction(const MachineInstr *MI) override; void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O); bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, - raw_ostream &OS); + raw_ostream &OS) override; bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, - raw_ostream &OS); + raw_ostream &OS) override; static const char *getRegisterName(unsigned RegNo); }; diff --git a/lib/Target/Hexagon/HexagonCFGOptimizer.cpp b/lib/Target/Hexagon/HexagonCFGOptimizer.cpp index 8597f11..de340e0 100644 --- a/lib/Target/Hexagon/HexagonCFGOptimizer.cpp +++ b/lib/Target/Hexagon/HexagonCFGOptimizer.cpp @@ -6,7 +6,6 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "hexagon_cfg" #include "Hexagon.h" #include "HexagonMachineFunctionInfo.h" #include "HexagonSubtarget.h" @@ -26,6 +25,8 @@ using namespace llvm; +#define DEBUG_TYPE "hexagon_cfg" + namespace llvm { void initializeHexagonCFGOptimizerPass(PassRegistry&); } @@ -48,10 +49,10 @@ private: initializeHexagonCFGOptimizerPass(*PassRegistry::getPassRegistry()); } - const char *getPassName() const { + const char *getPassName() const override { return "Hexagon CFG Optimizer"; } - bool runOnMachineFunction(MachineFunction &Fn); + bool runOnMachineFunction(MachineFunction &Fn) override; }; @@ -146,8 +147,8 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) { MachineBasicBlock::succ_iterator SI = MBB->succ_begin(); MachineBasicBlock* FirstSucc = *SI; MachineBasicBlock* SecondSucc = *(++SI); - MachineBasicBlock* LayoutSucc = NULL; - MachineBasicBlock* JumpAroundTarget = NULL; + MachineBasicBlock* LayoutSucc = nullptr; + MachineBasicBlock* JumpAroundTarget = nullptr; if (MBB->isLayoutSuccessor(FirstSucc)) { LayoutSucc = FirstSucc; @@ -161,7 +162,7 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) { // The target of the unconditional branch must be JumpAroundTarget. // TODO: If not, we should not invert the unconditional branch. - MachineBasicBlock* CondBranchTarget = NULL; + MachineBasicBlock* CondBranchTarget = nullptr; if ((MI->getOpcode() == Hexagon::JMP_t) || (MI->getOpcode() == Hexagon::JMP_f)) { CondBranchTarget = MI->getOperand(1).getMBB(); @@ -239,7 +240,7 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) { static void initializePassOnce(PassRegistry &Registry) { PassInfo *PI = new PassInfo("Hexagon CFG Optimizer", "hexagon-cfg", - &HexagonCFGOptimizer::ID, 0, false, false); + &HexagonCFGOptimizer::ID, nullptr, false, false); Registry.registerPass(*PI, true); } diff --git a/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/lib/Target/Hexagon/HexagonCopyToCombine.cpp index 60c933b..aeff680 100644 --- a/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -11,8 +11,6 @@ // to move them together. If we can move them next to each other we do so and // replace them with a combine instruction. //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "hexagon-copy-combine" - #include "llvm/PassSupport.h" #include "Hexagon.h" #include "HexagonInstrInfo.h" @@ -36,6 +34,8 @@ using namespace llvm; +#define DEBUG_TYPE "hexagon-copy-combine" + static cl::opt<bool> IsCombinesDisabled("disable-merge-into-combines", cl::Hidden, cl::ZeroOrMore, @@ -68,15 +68,15 @@ public: initializeHexagonCopyToCombinePass(*PassRegistry::getPassRegistry()); } - virtual void getAnalysisUsage(AnalysisUsage &AU) const { + void getAnalysisUsage(AnalysisUsage &AU) const override { MachineFunctionPass::getAnalysisUsage(AU); } - const char *getPassName() const { + const char *getPassName() const override { return "Hexagon Copy-To-Combine Pass"; } - virtual bool runOnMachineFunction(MachineFunction &Fn); + bool runOnMachineFunction(MachineFunction &Fn) override; private: MachineInstr *findPairable(MachineInstr *I1, bool &DoInsertAtI1); @@ -262,7 +262,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1, unsigned KilledOperand = 0; if (I2->killsRegister(I2UseReg)) KilledOperand = I2UseReg; - MachineInstr *KillingInstr = 0; + MachineInstr *KillingInstr = nullptr; for (; I != End; ++I) { // If the intervening instruction I: @@ -306,7 +306,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1, // Track killed operands. If we move across an instruction that kills our // operand, we need to update the kill information on the moved I1. It kills // the operand now. - MachineInstr *KillingInstr = 0; + MachineInstr *KillingInstr = nullptr; unsigned KilledOperand = 0; while(++I != End) { @@ -333,7 +333,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1, // Check for an exact kill (registers match). if (I1UseReg && I->killsRegister(I1UseReg)) { - assert(KillingInstr == 0 && "Should only see one killing instruction"); + assert(!KillingInstr && "Should only see one killing instruction"); KilledOperand = I1UseReg; KillingInstr = &*I; } @@ -506,7 +506,7 @@ MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr *I1, // Not safe. Stop searching. break; } - return 0; + return nullptr; } void HexagonCopyToCombine::combine(MachineInstr *I1, MachineInstr *I2, diff --git a/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp b/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp index 8a5991f..3dafe80 100644 --- a/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp +++ b/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp @@ -60,10 +60,10 @@ class HexagonExpandPredSpillCode : public MachineFunctionPass { initializeHexagonExpandPredSpillCodePass(Registry); } - const char *getPassName() const { + const char *getPassName() const override { return "Hexagon Expand Predicate Spill Code"; } - bool runOnMachineFunction(MachineFunction &Fn); + bool runOnMachineFunction(MachineFunction &Fn) override; }; @@ -187,7 +187,7 @@ static void initializePassOnce(PassRegistry &Registry) { const char *Name = "Hexagon Expand Predicate Spill Code"; PassInfo *PI = new PassInfo(Name, "hexagon-spill-pred", &HexagonExpandPredSpillCode::ID, - 0, false, false); + nullptr, false, false); Registry.registerPass(*PI, true); } diff --git a/lib/Target/Hexagon/HexagonFixupHwLoops.cpp b/lib/Target/Hexagon/HexagonFixupHwLoops.cpp index a79264b..d41939a 100644 --- a/lib/Target/Hexagon/HexagonFixupHwLoops.cpp +++ b/lib/Target/Hexagon/HexagonFixupHwLoops.cpp @@ -40,11 +40,13 @@ namespace { initializeHexagonFixupHwLoopsPass(*PassRegistry::getPassRegistry()); } - virtual bool runOnMachineFunction(MachineFunction &MF); + bool runOnMachineFunction(MachineFunction &MF) override; - const char *getPassName() const { return "Hexagon Hardware Loop Fixup"; } + const char *getPassName() const override { + return "Hexagon Hardware Loop Fixup"; + } - virtual void getAnalysisUsage(AnalysisUsage &AU) const { + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/lib/Target/Hexagon/HexagonFrameLowering.cpp b/lib/Target/Hexagon/HexagonFrameLowering.cpp index 0ea13d4..d551ca9 100644 --- a/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -246,7 +246,7 @@ HexagonFrameLowering::spillCalleeSavedRegisters( // unsigned SuperReg = uniqueSuperReg(Reg, TRI); bool CanUseDblStore = false; - const TargetRegisterClass* SuperRegClass = 0; + const TargetRegisterClass* SuperRegClass = nullptr; if (ContiguousRegs && (i < CSI.size()-1)) { unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI); @@ -300,7 +300,7 @@ bool HexagonFrameLowering::restoreCalleeSavedRegisters( // Check if we can use a double-word load. // unsigned SuperReg = uniqueSuperReg(Reg, TRI); - const TargetRegisterClass* SuperRegClass = 0; + const TargetRegisterClass* SuperRegClass = nullptr; bool CanUseDblLoad = false; if (ContiguousRegs && (i < CSI.size()-1)) { unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI); diff --git a/lib/Target/Hexagon/HexagonFrameLowering.h b/lib/Target/Hexagon/HexagonFrameLowering.h index a62c76a..446af16 100644 --- a/lib/Target/Hexagon/HexagonFrameLowering.h +++ b/lib/Target/Hexagon/HexagonFrameLowering.h @@ -28,25 +28,25 @@ public: /// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - virtual bool - spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const; - - void eliminateCallFramePseudoInstr(MachineFunction &MF, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) const; - - virtual bool + void emitPrologue(MachineFunction &MF) const override; + void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; + bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector<CalleeSavedInfo> &CSI, + const TargetRegisterInfo *TRI) const override; + + void + eliminateCallFramePseudoInstr(MachineFunction &MF, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const override; + + bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const; - int getFrameIndexOffset(const MachineFunction &MF, int FI) const; - bool hasFP(const MachineFunction &MF) const; + const TargetRegisterInfo *TRI) const override; + int getFrameIndexOffset(const MachineFunction &MF, int FI) const override; + bool hasFP(const MachineFunction &MF) const override; bool hasTailCall(MachineBasicBlock &MBB) const; }; diff --git a/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/lib/Target/Hexagon/HexagonHardwareLoops.cpp index 936fb11..7f76421 100644 --- a/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -26,7 +26,6 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "hwloops" #include "llvm/ADT/SmallSet.h" #include "Hexagon.h" #include "HexagonTargetMachine.h" @@ -47,6 +46,8 @@ using namespace llvm; +#define DEBUG_TYPE "hwloops" + #ifndef NDEBUG static cl::opt<int> HWLoopLimit("max-hwloop", cl::Hidden, cl::init(-1)); #endif @@ -77,11 +78,11 @@ namespace { initializeHexagonHardwareLoopsPass(*PassRegistry::getPassRegistry()); } - virtual bool runOnMachineFunction(MachineFunction &MF); + bool runOnMachineFunction(MachineFunction &MF) override; - const char *getPassName() const { return "Hexagon Hardware Loops"; } + const char *getPassName() const override { return "Hexagon Hardware Loops"; } - virtual void getAnalysisUsage(AnalysisUsage &AU) const { + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired<MachineDominatorTree>(); AU.addRequired<MachineLoopInfo>(); MachineFunctionPass::getAnalysisUsage(AU); @@ -264,8 +265,8 @@ namespace { return Contents.ImmVal; } - void print(raw_ostream &OS, const TargetMachine *TM = 0) const { - const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0; + void print(raw_ostream &OS, const TargetMachine *TM = nullptr) const { + const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : nullptr; if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); } if (isImm()) { OS << Contents.ImmVal; } } @@ -369,7 +370,7 @@ bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L, } // for (instr) SmallVector<MachineOperand,2> Cond; - MachineBasicBlock *TB = 0, *FB = 0; + MachineBasicBlock *TB = nullptr, *FB = nullptr; bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false); if (NotAnalyzed) return false; @@ -434,37 +435,37 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, "Loop must have more than one incoming edge!"); MachineBasicBlock *Backedge = *PI++; if (PI == TopMBB->pred_end()) // dead loop? - return 0; + return nullptr; MachineBasicBlock *Incoming = *PI++; if (PI != TopMBB->pred_end()) // multiple backedges? - return 0; + return nullptr; // Make sure there is one incoming and one backedge and determine which // is which. if (L->contains(Incoming)) { if (L->contains(Backedge)) - return 0; + return nullptr; std::swap(Incoming, Backedge); } else if (!L->contains(Backedge)) - return 0; + return nullptr; // Look for the cmp instruction to determine if we can get a useful trip // count. The trip count can be either a register or an immediate. The // location of the value depends upon the type (reg or imm). MachineBasicBlock *Latch = L->getLoopLatch(); if (!Latch) - return 0; + return nullptr; unsigned IVReg = 0; int64_t IVBump = 0; MachineInstr *IVOp; bool FoundIV = findInductionRegister(L, IVReg, IVBump, IVOp); if (!FoundIV) - return 0; + return nullptr; MachineBasicBlock *Preheader = L->getLoopPreheader(); - MachineOperand *InitialValue = 0; + MachineOperand *InitialValue = nullptr; MachineInstr *IV_Phi = MRI->getVRegDef(IVReg); for (unsigned i = 1, n = IV_Phi->getNumOperands(); i < n; i += 2) { MachineBasicBlock *MBB = IV_Phi->getOperand(i+1).getMBB(); @@ -474,13 +475,13 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, IVReg = IV_Phi->getOperand(i).getReg(); // Want IV reg after bump. } if (!InitialValue) - return 0; + return nullptr; SmallVector<MachineOperand,2> Cond; - MachineBasicBlock *TB = 0, *FB = 0; + MachineBasicBlock *TB = nullptr, *FB = nullptr; bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false); if (NotAnalyzed) - return 0; + return nullptr; MachineBasicBlock *Header = L->getHeader(); // TB must be non-null. If FB is also non-null, one of them must be @@ -489,7 +490,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, assert (TB && "Latch block without a branch?"); assert ((!FB || TB == Header || FB == Header) && "Branches not to header?"); if (!TB || (FB && TB != Header && FB != Header)) - return 0; + return nullptr; // Branches of form "if (!P) ..." cause HexagonInstrInfo::AnalyzeBranch // to put imm(0), followed by P in the vector Cond. @@ -505,7 +506,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, bool AnalyzedCmp = TII->analyzeCompare(CondI, CmpReg1, CmpReg2, Mask, ImmValue); if (!AnalyzedCmp) - return 0; + return nullptr; // The comparison operator type determines how we compute the loop // trip count. @@ -521,7 +522,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, bool isSwapped = false; const MachineOperand &Op1 = CondI->getOperand(1); const MachineOperand &Op2 = CondI->getOperand(2); - const MachineOperand *EndValue = 0; + const MachineOperand *EndValue = nullptr; if (Op1.isReg()) { if (Op2.isImm() || Op1.getReg() == IVReg) @@ -533,7 +534,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, } if (!EndValue) - return 0; + return nullptr; switch (CondOpc) { case Hexagon::CMPEQri: @@ -552,7 +553,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, case Hexagon::CMPbEQri_V4: case Hexagon::CMPhEQri_V4: { if (IVBump != 1) - return 0; + return nullptr; int64_t InitV, EndV; // Since the comparisons are "ri", the EndValue should be an @@ -562,26 +563,26 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, // Allow InitialValue to be a register defined with an immediate. if (InitialValue->isReg()) { if (!defWithImmediate(InitialValue->getReg())) - return 0; + return nullptr; InitV = getImmediate(*InitialValue); } else { assert(InitialValue->isImm()); InitV = InitialValue->getImm(); } if (InitV >= EndV) - return 0; + return nullptr; if (CondOpc == Hexagon::CMPbEQri_V4) { if (!isInt<8>(InitV) || !isInt<8>(EndV)) - return 0; + return nullptr; } else { // Hexagon::CMPhEQri_V4 if (!isInt<16>(InitV) || !isInt<16>(EndV)) - return 0; + return nullptr; } Cmp = !Negated ? Comparison::EQ : Comparison::NE; break; } default: - return 0; + return nullptr; } if (isSwapped) @@ -591,14 +592,14 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, unsigned R = InitialValue->getReg(); MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); if (!MDT->properlyDominates(DefBB, Header)) - return 0; + return nullptr; OldInsts.push_back(MRI->getVRegDef(R)); } if (EndValue->isReg()) { unsigned R = EndValue->getReg(); MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); if (!MDT->properlyDominates(DefBB, Header)) - return 0; + return nullptr; } return computeCount(L, InitialValue, EndValue, IVReg, IVBump, Cmp); @@ -616,7 +617,7 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop, Comparison::Kind Cmp) const { // Cannot handle comparison EQ, i.e. while (A == B). if (Cmp == Comparison::EQ) - return 0; + return nullptr; // Check if either the start or end values are an assignment of an immediate. // If so, use the immediate value rather than the register. @@ -642,11 +643,11 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop, // If loop executes while iv is "less" with the iv value going down, then // the iv must wrap. if (CmpLess && IVBump < 0) - return 0; + return nullptr; // If loop executes while iv is "greater" with the iv value going up, then // the iv must wrap. if (CmpGreater && IVBump > 0) - return 0; + return nullptr; if (Start->isImm() && End->isImm()) { // Both, start and end are immediates. @@ -654,15 +655,15 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop, int64_t EndV = End->getImm(); int64_t Dist = EndV - StartV; if (Dist == 0) - return 0; + return nullptr; bool Exact = (Dist % IVBump) == 0; if (Cmp == Comparison::NE) { if (!Exact) - return 0; + return nullptr; if ((Dist < 0) ^ (IVBump < 0)) - return 0; + return nullptr; } // For comparisons that include the final value (i.e. include equality @@ -683,7 +684,7 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop, uint64_t Count = Dist1; if (Count > 0xFFFFFFFFULL) - return 0; + return nullptr; return new CountValue(CountValue::CV_Immediate, Count); } @@ -695,7 +696,7 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop, // If the induction variable bump is not a power of 2, quit. // Othwerise we'd need a general integer division. if (!isPowerOf2_64(abs64(IVBump))) - return 0; + return nullptr; MachineBasicBlock *PH = Loop->getLoopPreheader(); assert (PH && "Should have a preheader by now"); @@ -766,7 +767,7 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop, // Hardware loops cannot handle 64-bit registers. If it's a double // register, it has to have a subregister. if (!SR && RC == &Hexagon::DoubleRegsRegClass) - return 0; + return nullptr; const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass; // Compute DistR (register with the distance between Start and End). @@ -1013,7 +1014,7 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L) { MachineBasicBlock *LastMBB = L->getExitingBlock(); // Don't generate hw loop if the loop has more than one exit. - if (LastMBB == 0) + if (!LastMBB) return false; MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator(); @@ -1035,7 +1036,7 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L) { SmallVector<MachineInstr*, 2> OldInsts; // Are we able to determine the trip count for the loop? CountValue *TripCount = getLoopTripCount(L, OldInsts); - if (TripCount == 0) + if (!TripCount) return false; // Is the trip count available in the preheader? @@ -1127,7 +1128,7 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L) { if (LastI != LastMBB->end()) LastI = LastMBB->erase(LastI); SmallVector<MachineOperand, 0> Cond; - TII->InsertBranch(*LastMBB, BranchTarget, 0, Cond, LastIDL); + TII->InsertBranch(*LastMBB, BranchTarget, nullptr, Cond, LastIDL); } } else { // Conditional branch to loop start; just delete it. @@ -1196,7 +1197,7 @@ MachineInstr *HexagonHardwareLoops::defWithImmediate(unsigned R) { case Hexagon::CONST64_Int_Real: return DI; } - return 0; + return nullptr; } @@ -1291,7 +1292,7 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) { if (IndRegs.empty()) return false; - MachineBasicBlock *TB = 0, *FB = 0; + MachineBasicBlock *TB = nullptr, *FB = nullptr; SmallVector<MachineOperand,2> Cond; // AnalyzeBranch returns true if it fails to analyze branch. bool NotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Cond, false); @@ -1322,7 +1323,7 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) { return false; SmallSet<unsigned,2> CmpRegs; - MachineOperand *CmpImmOp = 0; + MachineOperand *CmpImmOp = nullptr; // Go over all operands to the compare and look for immediate and register // operands. Assume that if the compare has a single register use and a @@ -1420,7 +1421,7 @@ MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop( DebugLoc DL; if (!Latch || Header->hasAddressTaken()) - return 0; + return nullptr; typedef MachineBasicBlock::instr_iterator instr_iterator; @@ -1429,17 +1430,17 @@ MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop( typedef std::vector<MachineBasicBlock*> MBBVector; MBBVector Preds(Header->pred_begin(), Header->pred_end()); SmallVector<MachineOperand,2> Tmp1; - MachineBasicBlock *TB = 0, *FB = 0; + MachineBasicBlock *TB = nullptr, *FB = nullptr; if (TII->AnalyzeBranch(*Latch, TB, FB, Tmp1, false)) - return 0; + return nullptr; for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) { MachineBasicBlock *PB = *I; if (PB != Latch) { bool NotAnalyzed = TII->AnalyzeBranch(*PB, TB, FB, Tmp1, false); if (NotAnalyzed) - return 0; + return nullptr; } } @@ -1515,7 +1516,7 @@ MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop( SmallVector<MachineOperand,1> Tmp2; SmallVector<MachineOperand,1> EmptyCond; - TB = FB = 0; + TB = FB = nullptr; for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) { MachineBasicBlock *PB = *I; @@ -1525,22 +1526,22 @@ MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop( (void)NotAnalyzed; // suppress compiler warning assert (!NotAnalyzed && "Should be analyzable!"); if (TB != Header && (Tmp2.empty() || FB != Header)) - TII->InsertBranch(*PB, NewPH, 0, EmptyCond, DL); + TII->InsertBranch(*PB, NewPH, nullptr, EmptyCond, DL); PB->ReplaceUsesOfBlockWith(Header, NewPH); } } // It can happen that the latch block will fall through into the header. // Insert an unconditional branch to the header. - TB = FB = 0; + TB = FB = nullptr; bool LatchNotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Tmp2, false); (void)LatchNotAnalyzed; // suppress compiler warning assert (!LatchNotAnalyzed && "Should be analyzable!"); if (!TB && !FB) - TII->InsertBranch(*Latch, Header, 0, EmptyCond, DL); + TII->InsertBranch(*Latch, Header, nullptr, EmptyCond, DL); // Finally, the branch from the preheader to the header. - TII->InsertBranch(*NewPH, Header, 0, EmptyCond, DL); + TII->InsertBranch(*NewPH, Header, nullptr, EmptyCond, DL); NewPH->addSuccessor(Header); return NewPH; diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index ed8c786..dabe650 100644 --- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -11,7 +11,6 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "hexagon-isel" #include "Hexagon.h" #include "HexagonISelLowering.h" #include "HexagonTargetMachine.h" @@ -23,6 +22,8 @@ #include "llvm/Support/Debug.h" using namespace llvm; +#define DEBUG_TYPE "hexagon-isel" + static cl::opt<unsigned> MaxNumOfUsesForConstExtenders("ga-max-num-uses-for-constant-extenders", @@ -61,7 +62,7 @@ public: } bool hasNumUsesBelowThresGA(SDNode *N) const; - SDNode *Select(SDNode *N); + SDNode *Select(SDNode *N) override; // Complex Pattern Selectors. inline bool foldGlobalAddress(SDValue &N, SDValue &R); @@ -78,15 +79,15 @@ public: bool SelectADDRriU6_1(SDValue& N, SDValue &R1, SDValue &R2); bool SelectADDRriU6_2(SDValue& N, SDValue &R1, SDValue &R2); - virtual const char *getPassName() const { + const char *getPassName() const override { return "Hexagon DAG->DAG Pattern Instruction Selection"; } /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. - virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, - char ConstraintCode, - std::vector<SDValue> &OutOps); + bool SelectInlineAsmMemoryOperand(const SDValue &Op, + char ConstraintCode, + std::vector<SDValue> &OutOps) override; bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset); SDNode *SelectLoad(SDNode *N); @@ -186,7 +187,7 @@ FunctionPass *llvm::createHexagonISelDag(HexagonTargetMachine &TM, static void initializePassOnce(PassRegistry &Registry) { const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection"; PassInfo *PI = new PassInfo(Name, "hexagon-isel", - &SelectionDAGISel::ID, 0, false, false); + &SelectionDAGISel::ID, nullptr, false, false); Registry.registerPass(*PI, true); } @@ -1238,7 +1239,7 @@ SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) { SDNode *PdRs = CurDAG->getMachineNode(Hexagon::TFR_PdRs, dl, MVT::i1, SDValue(Arg, 0)); Ops.push_back(SDValue(PdRs,0)); - } else if (RC == NULL && (dyn_cast<ConstantSDNode>(Arg) != NULL)) { + } else if (!RC && (dyn_cast<ConstantSDNode>(Arg) != nullptr)) { // This is immediate operand. Lower it here making sure that we DO have // const SDNode for immediate value. int32_t Val = cast<ConstantSDNode>(Arg)->getSExtValue(); @@ -1346,7 +1347,7 @@ SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) { SDNode *HexagonDAGToDAGISel::Select(SDNode *N) { if (N->isMachineOpcode()) { N->setNodeId(-1); - return NULL; // Already selected. + return nullptr; // Already selected. } diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp index 92b794d..b8e5d24 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -39,6 +39,8 @@ using namespace llvm; +#define DEBUG_TYPE "hexagon-lowering" + static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, cl::desc("Control jump table emission on Hexagon target")); @@ -135,7 +137,7 @@ CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT, State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); return false; } - llvm_unreachable(0); + llvm_unreachable(nullptr); } @@ -182,7 +184,7 @@ static bool CC_Hexagon32(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) { - static const uint16_t RegList[] = { + static const MCPhysReg RegList[] = { Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R5 }; @@ -205,10 +207,10 @@ static bool CC_Hexagon64(unsigned ValNo, MVT ValVT, return false; } - static const uint16_t RegList1[] = { + static const MCPhysReg RegList1[] = { Hexagon::D1, Hexagon::D2 }; - static const uint16_t RegList2[] = { + static const MCPhysReg RegList2[] = { Hexagon::R1, Hexagon::R3 }; if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) { @@ -346,8 +348,7 @@ HexagonTargetLowering::LowerReturn(SDValue Chain, if (Flag.getNode()) RetOps.push_back(Flag); - return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, - &RetOps[0], RetOps.size()); + return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps); } @@ -410,7 +411,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, int NumNamedVarArgParams = -1; if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee)) { - const Function* CalleeFn = NULL; + const Function* CalleeFn = nullptr; Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32); if ((CalleeFn = dyn_cast<Function>(GA->getGlobal()))) { @@ -520,8 +521,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Transform all store nodes into one single node because all store // nodes are independent of each other. if (!MemOpChains.empty()) { - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], - MemOpChains.size()); + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); } if (!isTailCall) @@ -595,9 +595,9 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, } if (isTailCall) - return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); + return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops); - Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); + Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops); InFlag = Chain.getValue(1); // Create the CALLSEQ_END node. @@ -817,7 +817,7 @@ HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, Sub); SDValue Ops[2] = { ArgAdjust, CopyChain }; - return DAG.getMergeValues(Ops, 2, dl); + return DAG.getMergeValues(Ops, dl); } SDValue @@ -916,8 +916,7 @@ const { } if (!MemOps.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], - MemOps.size()); + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); if (isVarArg) { // This will point to the next argument passed via stack. @@ -1480,7 +1479,7 @@ HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { switch (Opcode) { - default: return 0; + default: return nullptr; case HexagonISD::CONST32: return "HexagonISD::CONST32"; case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP"; case HexagonISD::CONST32_Int_Real: return "HexagonISD::CONST32_Int_Real"; diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h index 73da226..4f27c27 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.h +++ b/lib/Target/Hexagon/HexagonISelLowering.h @@ -92,14 +92,14 @@ namespace llvm { const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const; - virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const; - virtual bool isTruncateFree(EVT VT1, EVT VT2) const; + bool isTruncateFree(Type *Ty1, Type *Ty2) const override; + bool isTruncateFree(EVT VT1, EVT VT2) const override; - virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const; + bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; - virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; - virtual const char *getTargetNodeName(unsigned Opcode) const; + const char *getTargetNodeName(unsigned Opcode) const override; SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; @@ -109,12 +109,12 @@ namespace llvm { CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG, - SmallVectorImpl<SDValue> &InVals) const; + SmallVectorImpl<SDValue> &InVals) const override; SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, - SmallVectorImpl<SDValue> &InVals) const; + SmallVectorImpl<SDValue> &InVals) const override; SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, @@ -133,46 +133,45 @@ namespace llvm { CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, - SDLoc dl, SelectionDAG &DAG) const; + SDLoc dl, SelectionDAG &DAG) const override; - virtual MachineBasicBlock - *EmitInstrWithCustomInserter(MachineInstr *MI, - MachineBasicBlock *BB) const; + MachineBasicBlock * + EmitInstrWithCustomInserter(MachineInstr *MI, + MachineBasicBlock *BB) const override; SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; - virtual EVT getSetCCResultType(LLVMContext &C, EVT VT) const { + EVT getSetCCResultType(LLVMContext &C, EVT VT) const override { if (!VT.isVector()) return MVT::i1; else return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements()); } - virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, - SDValue &Base, SDValue &Offset, - ISD::MemIndexedMode &AM, - SelectionDAG &DAG) const; + bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, + SDValue &Base, SDValue &Offset, + ISD::MemIndexedMode &AM, + SelectionDAG &DAG) const override; std::pair<unsigned, const TargetRegisterClass*> getRegForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const; + MVT VT) const override; // Intrinsics - virtual SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, - SelectionDAG &DAG) const; + SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; /// isLegalAddressingMode - Return true if the addressing mode represented /// by AM is legal for this target, for a load/store of the specified type. /// The type may be VoidTy, in which case only return true if the addressing /// mode is legal for a load/store of any legal type. /// TODO: Handle pre/postinc as well. - virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; - virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; + bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override; + bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; /// isLegalICmpImmediate - Return true if the specified immediate is legal /// icmp immediate, that is the target has icmp instructions which can /// compare a register against the immediate without having to materialize /// the immediate into a register. - virtual bool isLegalICmpImmediate(int64_t Imm) const; + bool isLegalICmpImmediate(int64_t Imm) const override; }; } // end namespace llvm diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td index d25bfa8..1057343 100644 --- a/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/lib/Target/Hexagon/HexagonInstrFormats.td @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// Hexagon Intruction Flags + +// Hexagon Instruction Flags + // // *** Must match HexagonBaseInfo.h *** //===----------------------------------------------------------------------===// @@ -68,7 +68,7 @@ def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd) //===----------------------------------------------------------------------===// -// Intruction Class Declaration + +// Instruction Class Declaration + //===----------------------------------------------------------------------===// class OpcodeHexagon { @@ -104,54 +104,72 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, // Solo instructions, i.e., those that cannot be in a packet with others. bits<1> isSolo = 0; let TSFlags{5} = isSolo; + // Packed only with A or X-type instructions. + bits<1> isSoloAX = 0; + let TSFlags{6} = isSoloAX; + // Only A-type instruction in first slot or nothing. + bits<1> isSoloAin1 = 0; + let TSFlags{7} = isSoloAin1; // Predicated instructions. bits<1> isPredicated = 0; - let TSFlags{6} = isPredicated; + let TSFlags{8} = isPredicated; bits<1> isPredicatedFalse = 0; - let TSFlags{7} = isPredicatedFalse; + let TSFlags{9} = isPredicatedFalse; bits<1> isPredicatedNew = 0; - let TSFlags{8} = isPredicatedNew; + let TSFlags{10} = isPredicatedNew; + bits<1> isPredicateLate = 0; + let TSFlags{11} = isPredicateLate; // Late predicate producer insn. // New-value insn helper fields. bits<1> isNewValue = 0; - let TSFlags{9} = isNewValue; // New-value consumer insn. + let TSFlags{12} = isNewValue; // New-value consumer insn. bits<1> hasNewValue = 0; - let TSFlags{10} = hasNewValue; // New-value producer insn. + let TSFlags{13} = hasNewValue; // New-value producer insn. bits<3> opNewValue = 0; - let TSFlags{13-11} = opNewValue; // New-value produced operand. - bits<2> opNewBits = 0; - let TSFlags{15-14} = opNewBits; // New-value opcode bits location: 0, 8, 16. + let TSFlags{16-14} = opNewValue; // New-value produced operand. bits<1> isNVStorable = 0; - let TSFlags{16} = isNVStorable; // Store that can become new-value store. + let TSFlags{17} = isNVStorable; // Store that can become new-value store. bits<1> isNVStore = 0; - let TSFlags{17} = isNVStore; // New-value store insn. + let TSFlags{18} = isNVStore; // New-value store insn. + bits<1> isCVLoadable = 0; + let TSFlags{19} = isCVLoadable; // Load that can become cur-value load. + bits<1> isCVLoad = 0; + let TSFlags{20} = isCVLoad; // Cur-value load insn. // Immediate extender helper fields. bits<1> isExtendable = 0; - let TSFlags{18} = isExtendable; // Insn may be extended. + let TSFlags{21} = isExtendable; // Insn may be extended. bits<1> isExtended = 0; - let TSFlags{19} = isExtended; // Insn must be extended. + let TSFlags{22} = isExtended; // Insn must be extended. bits<3> opExtendable = 0; - let TSFlags{22-20} = opExtendable; // Which operand may be extended. + let TSFlags{25-23} = opExtendable; // Which operand may be extended. bits<1> isExtentSigned = 0; - let TSFlags{23} = isExtentSigned; // Signed or unsigned range. + let TSFlags{26} = isExtentSigned; // Signed or unsigned range. bits<5> opExtentBits = 0; - let TSFlags{28-24} = opExtentBits; //Number of bits of range before extending. + let TSFlags{31-27} = opExtentBits; //Number of bits of range before extending. + bits<2> opExtentAlign = 0; + let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending. // If an instruction is valid on a subtarget (v2-v5), set the corresponding // bit from validSubTargets. v2 is the least significant bit. // By default, instruction is valid on all subtargets. SubTarget validSubTargets = HasV2SubT; - let TSFlags{32-29} = validSubTargets.Value; + let TSFlags{37-34} = validSubTargets.Value; // Addressing mode for load/store instructions. AddrModeType addrMode = NoAddrMode; - let TSFlags{35-33} = addrMode.Value; + let TSFlags{42-40} = addrMode.Value; // Memory access size for mem access instructions (load/store) MemAccessSize accessSize = NoMemAccess; - let TSFlags{38-36} = accessSize.Value; + let TSFlags{45-43} = accessSize.Value; + + bits<1> isTaken = 0; + let TSFlags {47} = isTaken; // Branch prediction. + + bits<1> isFP = 0; + let TSFlags {48} = isFP; // Floating-point. // Fields used for relation models. string BaseOpcode = ""; @@ -173,14 +191,14 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, } //===----------------------------------------------------------------------===// -// Intruction Classes Definitions + +// Instruction Classes Definitions + //===----------------------------------------------------------------------===// // LD Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD>; + string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>; let mayLoad = 1 in class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], @@ -199,16 +217,16 @@ class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [], let mayLoad = 1 in class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : LDInst<outs, ins, asmstr, pattern, cstr>; + string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>; // ST Instruction Class in V2/V3 can take SLOT0 only. // ST Instruction Class in V4 can take SLOT0 & SLOT1. // Definition of the instruction class CHANGED from V2/V3 to V4. let mayStore = 1 in class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST>; + string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>; class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = ""> @@ -216,39 +234,39 @@ class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], let mayStore = 1 in class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, ST0, TypeST>; + string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>; // ST Instruction Class in V2/V3 can take SLOT0 only. // ST Instruction Class in V4 can take SLOT0 & SLOT1. // Definition of the instruction class CHANGED from V2/V3 to V4. class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : STInst<outs, ins, asmstr, pattern, cstr>; + string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01> + : STInst<outs, ins, asmstr, pattern, cstr, itin>; // SYSTEM Instruction Class in V4 can take SLOT0 only // In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1. class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, SYS, TypeSYSTEM>; + string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeSYSTEM>; // ALU32 Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU32, TypeALU32>; + string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32>; // ALU64 Instruction Class in V2/V3. // XTYPE Instruction Class in V4. // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4. class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE>; + string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>; class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : ALU64Inst<outs, ins, asmstr, pattern, cstr>; + string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23> + : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>; // M Instruction Class in V2/V3. @@ -256,55 +274,55 @@ class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE>; + string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>; // M Instruction Class in V2/V3. // XTYPE Instruction Class in V4. // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : MInst<outs, ins, asmstr, pattern, cstr>; + string cstr = "", InstrItinClass itin = M_tc_2_SLOT23> + : MInst<outs, ins, asmstr, pattern, cstr, itin>; // S Instruction Class in V2/V3. // XTYPE Instruction Class in V4. // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE>; + string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>; // S Instruction Class in V2/V3. // XTYPE Instruction Class in V4. // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : SInst<outs, ins, asmstr, pattern, cstr>; + string cstr = "", InstrItinClass itin = S_3op_tc_1_SLOT23> + : SInst<outs, ins, asmstr, pattern, cstr, itin>; // J Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, J, TypeJ>; + string cstr = "", InstrItinClass itin = J_tc_2early_SLOT23> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>; // JR Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, JR, TypeJR>; + string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJR>; // CR Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, CR, TypeCR>; + string cstr = "", InstrItinClass itin = CR_tc_2early_SLOT3> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCR>; let isCodeGenOnly = 1, isPseudo = 1 in class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, ENDLOOP, TypeENDLOOP>; + string cstr = "", InstrItinClass itin = J_tc_2early_SLOT0123> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>; let isCodeGenOnly = 1, isPseudo = 1 in class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [], @@ -317,39 +335,40 @@ class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [], : InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>; //===----------------------------------------------------------------------===// -// Intruction Classes Definitions - +// Instruction Classes Definitions - //===----------------------------------------------------------------------===// // // ALU32 patterns //. -class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr = ""> - : ALU32Inst<outs, ins, asmstr, pattern, cstr>; +class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> + : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; -class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr = ""> - : ALU32Inst<outs, ins, asmstr, pattern, cstr>; +class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> + : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; -class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr = ""> - : ALU32Inst<outs, ins, asmstr, pattern, cstr>; +class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> + : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; + +class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> + : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; -class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr = ""> - : ALU32Inst<outs, ins, asmstr, pattern, cstr>; // // ALU64 patterns. // -class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr = ""> - : ALU64Inst<outs, ins, asmstr, pattern, cstr>; +class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23> + : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>; -class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr = ""> - : ALU64Inst<outs, ins, asmstr, pattern, cstr>; +class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23> + : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>; // Post increment ST Instruction. class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [], diff --git a/lib/Target/Hexagon/HexagonInstrFormatsV4.td b/lib/Target/Hexagon/HexagonInstrFormatsV4.td index 9fda0da..d92f97b 100644 --- a/lib/Target/Hexagon/HexagonInstrFormatsV4.td +++ b/lib/Target/Hexagon/HexagonInstrFormatsV4.td @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// //----------------------------------------------------------------------------// -// Hexagon Intruction Flags + +// Hexagon Instruction Flags // // *** Must match BaseInfo.h *** //----------------------------------------------------------------------------// @@ -22,30 +22,30 @@ def TypeNV : IType<10>; def TypePREFIX : IType<30>; //----------------------------------------------------------------------------// -// Intruction Classes Definitions + +// Instruction Classes Definitions //----------------------------------------------------------------------------// // // NV type instructions. // class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4, TypeNV>; + string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNV>; class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : NVInst<outs, ins, asmstr, pattern, cstr>; + string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0> + : NVInst<outs, ins, asmstr, pattern, cstr, itin>; // Definition of Post increment new value store. class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : NVInst<outs, ins, asmstr, pattern, cstr>; + string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0> + : NVInst<outs, ins, asmstr, pattern, cstr, itin>; // Post increment ST Instruction. let mayStore = 1 in class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : NVInst<outs, ins, asmstr, pattern, cstr>; + string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0> + : NVInst<outs, ins, asmstr, pattern, cstr, itin>; // New-value conditional branch. class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], @@ -54,13 +54,14 @@ class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], let mayLoad = 1, mayStore = 1 in class MEMInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, MEM_V4, TypeMEMOP>; + string cstr = "", InstrItinClass itin = V4LDST_tc_st_SLOT0> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeMEMOP>; class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : MEMInst<outs, ins, asmstr, pattern, cstr>; + string cstr = "", InstrItinClass itin = V4LDST_tc_st_SLOT0> + : MEMInst<outs, ins, asmstr, pattern, cstr, itin>; let isCodeGenOnly = 1 in class EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []> - : InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypePREFIX>; + : InstHexagon<outs, ins, asmstr, pattern, "", EXTENDER_tc_1_SLOT0123, + TypePREFIX>; diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 21a12de..ea6367a 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -26,13 +26,16 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" + +using namespace llvm; + +#define DEBUG_TYPE "hexagon-instrinfo" + #define GET_INSTRINFO_CTOR_DTOR #define GET_INSTRMAP_INFO #include "HexagonGenInstrInfo.inc" #include "HexagonGenDFAPacketizer.inc" -using namespace llvm; - /// /// Constants for Hexagon instructions. /// @@ -135,7 +138,7 @@ HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, regPos = 1; } - if (FBB == 0) { + if (!FBB) { if (Cond.empty()) { // Due to a bug in TailMerging/CFG Optimization, we need to add a // special case handling of a predicated jump followed by an @@ -151,7 +154,7 @@ HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, if (NewTBB == NextBB) { ReverseBranchCondition(Cond); RemoveBranch(MBB); - return InsertBranch(MBB, TBB, 0, Cond, DL); + return InsertBranch(MBB, TBB, nullptr, Cond, DL); } } BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); @@ -174,8 +177,8 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const { - TBB = NULL; - FBB = NULL; + TBB = nullptr; + FBB = nullptr; // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::instr_iterator I = MBB.instr_end(); @@ -224,7 +227,7 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, // Get the last instruction in the block. MachineInstr *LastInst = I; - MachineInstr *SecondLastInst = NULL; + MachineInstr *SecondLastInst = nullptr; // Find one more terminator if present. do { if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(I)) { @@ -557,7 +560,7 @@ MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, const SmallVectorImpl<unsigned> &Ops, int FI) const { // Hexagon_TODO: Implement. - return(0); + return nullptr; } unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const { diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h index 5da23cb..6b032c9 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/lib/Target/Hexagon/HexagonInstrInfo.h @@ -40,124 +40,121 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; } + const HexagonRegisterInfo &getRegisterInfo() const { return RI; } /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. - virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, - int &FrameIndex) const; + unsigned isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const override; /// isStoreToStackSlot - If the specified machine instruction is a direct /// store to a stack slot, return the virtual or physical register number of /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. - virtual unsigned isStoreToStackSlot(const MachineInstr *MI, - int &FrameIndex) const; - - - virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, - SmallVectorImpl<MachineOperand> &Cond, - bool AllowModify) const; - - virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; - - virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl<MachineOperand> &Cond, - DebugLoc DL) const; - - virtual bool analyzeCompare(const MachineInstr *MI, - unsigned &SrcReg, unsigned &SrcReg2, - int &Mask, int &Value) const; - - virtual void copyPhysReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, DebugLoc DL, - unsigned DestReg, unsigned SrcReg, - bool KillSrc) const; - - virtual void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned SrcReg, bool isKill, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const; - - virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, - SmallVectorImpl<MachineOperand> &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl<MachineInstr*> &NewMIs) const; - - virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MBBI, - unsigned DestReg, int FrameIndex, - const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI) const; - - virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl<MachineOperand> &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl<MachineInstr*> &NewMIs) const; - - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, - MachineInstr* MI, - const SmallVectorImpl<unsigned> &Ops, - int FrameIndex) const; - - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, - MachineInstr* MI, - const SmallVectorImpl<unsigned> &Ops, - MachineInstr* LoadMI) const { - return 0; + unsigned isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const override; + + + bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl<MachineOperand> &Cond, + bool AllowModify) const override; + + unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + + unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, + MachineBasicBlock *FBB, + const SmallVectorImpl<MachineOperand> &Cond, + DebugLoc DL) const override; + + bool analyzeCompare(const MachineInstr *MI, + unsigned &SrcReg, unsigned &SrcReg2, + int &Mask, int &Value) const override; + + void copyPhysReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, DebugLoc DL, + unsigned DestReg, unsigned SrcReg, + bool KillSrc) const override; + + void storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned SrcReg, bool isKill, int FrameIndex, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const override; + + void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, + SmallVectorImpl<MachineOperand> &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl<MachineInstr*> &NewMIs) const; + + void loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned DestReg, int FrameIndex, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const override; + + void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, + SmallVectorImpl<MachineOperand> &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl<MachineInstr*> &NewMIs) const; + + MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, + MachineInstr* MI, + const SmallVectorImpl<unsigned> &Ops, + int FrameIndex) const override; + + MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, + MachineInstr* MI, + const SmallVectorImpl<unsigned> &Ops, + MachineInstr* LoadMI) const override { + return nullptr; } unsigned createVR(MachineFunction* MF, MVT VT) const; - virtual bool isBranch(const MachineInstr *MI) const; - virtual bool isPredicable(MachineInstr *MI) const; - virtual bool - PredicateInstruction(MachineInstr *MI, - const SmallVectorImpl<MachineOperand> &Cond) const; - - virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, - unsigned ExtraPredCycles, - const BranchProbability &Probability) const; - - virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, - unsigned NumTCycles, unsigned ExtraTCycles, - MachineBasicBlock &FMBB, - unsigned NumFCycles, unsigned ExtraFCycles, - const BranchProbability &Probability) const; - - virtual bool isPredicated(const MachineInstr *MI) const; - virtual bool isPredicated(unsigned Opcode) const; - virtual bool isPredicatedTrue(const MachineInstr *MI) const; - virtual bool isPredicatedTrue(unsigned Opcode) const; - virtual bool isPredicatedNew(const MachineInstr *MI) const; - virtual bool isPredicatedNew(unsigned Opcode) const; - virtual bool DefinesPredicate(MachineInstr *MI, - std::vector<MachineOperand> &Pred) const; - virtual bool - SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, - const SmallVectorImpl<MachineOperand> &Pred2) const; - - virtual bool - ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; - - virtual bool - isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles, - const BranchProbability &Probability) const; - - virtual DFAPacketizer* + bool isBranch(const MachineInstr *MI) const; + bool isPredicable(MachineInstr *MI) const override; + bool PredicateInstruction(MachineInstr *MI, + const SmallVectorImpl<MachineOperand> &Cond) const override; + + bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, + unsigned ExtraPredCycles, + const BranchProbability &Probability) const override; + + bool isProfitableToIfCvt(MachineBasicBlock &TMBB, + unsigned NumTCycles, unsigned ExtraTCycles, + MachineBasicBlock &FMBB, + unsigned NumFCycles, unsigned ExtraFCycles, + const BranchProbability &Probability) const override; + + bool isPredicated(const MachineInstr *MI) const override; + bool isPredicated(unsigned Opcode) const; + bool isPredicatedTrue(const MachineInstr *MI) const; + bool isPredicatedTrue(unsigned Opcode) const; + bool isPredicatedNew(const MachineInstr *MI) const; + bool isPredicatedNew(unsigned Opcode) const; + bool DefinesPredicate(MachineInstr *MI, + std::vector<MachineOperand> &Pred) const override; + bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, + const SmallVectorImpl<MachineOperand> &Pred2) const override; + + bool + ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; + + bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, + const BranchProbability &Probability) const override; + + DFAPacketizer* CreateTargetScheduleState(const TargetMachine *TM, - const ScheduleDAG *DAG) const; + const ScheduleDAG *DAG) const override; - virtual bool isSchedulingBoundary(const MachineInstr *MI, - const MachineBasicBlock *MBB, - const MachineFunction &MF) const; + bool isSchedulingBoundary(const MachineInstr *MI, + const MachineBasicBlock *MBB, + const MachineFunction &MF) const override; bool isValidOffset(const int Opcode, const int Offset) const; bool isValidAutoIncImm(const EVT VT, const int Offset) const; bool isMemOp(const MachineInstr *MI) const; diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index c96aaca..4dcf101 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -768,12 +768,13 @@ class T_JMP <dag InsDag, list<dag> JumpList = []> let InputType = "imm", isExtendable = 1, opExtendable = 1, isExtentSigned = 1, Defs = [PC], isPredicated = 1, opExtentBits = 17 in -class T_JMP_c <bit PredNot, bit isPredNew, bit isTaken>: +class T_JMP_c <bit PredNot, bit isPredNew, bit isTak>: JInst<(outs ), (ins PredRegs:$src, brtarget:$dst), !if(PredNot, "if (!$src", "if ($src")# !if(isPredNew, ".new) ", ") ")#"jump"# - !if(isPredNew, !if(isTaken, ":t ", ":nt "), " ")#"$dst"> { + !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> { + let isTaken = isTak; let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), ""); let isPredicatedFalse = PredNot; let isPredicatedNew = isPredNew; @@ -784,7 +785,7 @@ class T_JMP_c <bit PredNot, bit isPredNew, bit isTaken>: let Inst{27-24} = 0b1100; let Inst{21} = PredNot; - let Inst{12} = !if(isPredNew, isTaken, zero); + let Inst{12} = !if(isPredNew, isTak, zero); let Inst{11} = isPredNew; let Inst{9-8} = src; let Inst{23-22} = dst{16-15}; @@ -806,12 +807,13 @@ class T_JMPr<dag InsDag = (ins IntRegs:$dst)> } let Defs = [PC], isPredicated = 1, InputType = "reg" in -class T_JMPr_c <bit PredNot, bit isPredNew, bit isTaken>: +class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>: JRInst <(outs ), (ins PredRegs:$src, IntRegs:$dst), !if(PredNot, "if (!$src", "if ($src")# !if(isPredNew, ".new) ", ") ")#"jumpr"# - !if(isPredNew, !if(isTaken, ":t ", ":nt "), " ")#"$dst"> { + !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> { + let isTaken = isTak; let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), ""); let isPredicatedFalse = PredNot; let isPredicatedNew = isPredNew; @@ -823,7 +825,7 @@ class T_JMPr_c <bit PredNot, bit isPredNew, bit isTaken>: let Inst{27-22} = 0b001101; let Inst{21} = PredNot; let Inst{20-16} = dst; - let Inst{12} = !if(isPredNew, isTaken, zero); + let Inst{12} = !if(isPredNew, isTak, zero); let Inst{11} = isPredNew; let Inst{9-8} = src; let Predicates = !if(isPredNew, [HasV3T], [HasV2T]); diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index a95fb80..db5b7ea 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -1004,13 +1004,13 @@ defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel; let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum, - bit isNegCond, bit isTaken> + bit isNegCond, bit isTak> : NVInst_V4<(outs), (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset), "if ("#!if(isNegCond, "!","")#mnemonic# "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")# "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:" - #!if(isTaken, "t","nt")#" $offset", + #!if(isTak, "t","nt")#" $offset", []>, Requires<[HasV4T]> { bits<5> src1; @@ -1019,6 +1019,7 @@ class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum, bits<5> RegOp; // Non-New-Value Operand bits<11> offset; + let isTaken = isTak; let isBrTaken = !if(isTaken, "true", "false"); let isPredicatedFalse = isNegCond; @@ -1030,7 +1031,7 @@ class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum, let Inst{25-23} = majOp; let Inst{22} = isNegCond; let Inst{18-16} = Ns; - let Inst{13} = isTaken; + let Inst{13} = isTak; let Inst{12-8} = RegOp; let Inst{21-20} = offset{10-9}; let Inst{7-1} = offset{8-2}; @@ -1078,13 +1079,14 @@ let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1, let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond, - bit isTaken> + bit isTak> : NVInst_V4<(outs), (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset), "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:" - #!if(isTaken, "t","nt")#" $offset", + #!if(isTak, "t","nt")#" $offset", []>, Requires<[HasV4T]> { + let isTaken = isTak; let isPredicatedFalse = isNegCond; let isBrTaken = !if(isTaken, "true", "false"); @@ -1097,7 +1099,7 @@ class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond, let Inst{25-23} = majOp; let Inst{22} = isNegCond; let Inst{18-16} = src1; - let Inst{13} = isTaken; + let Inst{13} = isTak; let Inst{12-8} = src2; let Inst{21-20} = offset{10-9}; let Inst{7-1} = offset{8-2}; @@ -1135,14 +1137,15 @@ let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1, let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11 in class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal, - bit isNegCond, bit isTaken> + bit isNegCond, bit isTak> : NVInst_V4<(outs), (ins IntRegs:$src1, brtarget:$offset), "if ("#!if(isNegCond, "!","")#mnemonic #"($src1.new, #"#ImmVal#")) jump:" - #!if(isTaken, "t","nt")#" $offset", + #!if(isTak, "t","nt")#" $offset", []>, Requires<[HasV4T]> { + let isTaken = isTak; let isPredicatedFalse = isNegCond; let isBrTaken = !if(isTaken, "true", "false"); @@ -1153,7 +1156,7 @@ class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal, let Inst{25-23} = majOp; let Inst{22} = isNegCond; let Inst{18-16} = src1; - let Inst{13} = isTaken; + let Inst{13} = isTak; let Inst{21-20} = offset{10-9}; let Inst{7-1} = offset{8-2}; } @@ -2019,9 +2022,10 @@ multiclass MemOpi_bitPats <PatFrag ldOp, PatFrag stOp, PatLeaf immPred, // mem[bhw](Rs+#0) = [clrbit|setbit](#U5) let AddedComplexity = 225 in - def : Pat <(stOp (OpNode (ldOp addrPred:$addr), immPred:$bitend), - addrPred:$addr), - (MI IntRegs:$addr, #0, (xformFunc immPred:$bitend))>; + def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)), + immPred:$bitend), + (addrPred (i32 IntRegs:$addr), extPred:$offset)), + (MI IntRegs:$addr, extPred:$offset, (xformFunc immPred:$bitend))>; } multiclass MemOpi_bitExtType<PatFrag ldOpByte, PatFrag ldOpHalf > { @@ -2065,9 +2069,10 @@ multiclass MemOpr_Pats <PatFrag ldOp, PatFrag stOp, ComplexPattern addrPred, PatLeaf extPred, InstHexagon MI, SDNode OpNode> { let AddedComplexity = 141 in // mem[bhw](Rs+#0) [+-&|]= Rt - def : Pat <(stOp (OpNode (ldOp addrPred:$addr), (i32 IntRegs:$addend)), - addrPred:$addr), - (MI IntRegs:$addr, #0, (i32 IntRegs:$addend) )>; + def : Pat <(stOp (OpNode (ldOp (addrPred IntRegs:$addr, extPred:$offset)), + (i32 IntRegs:$addend)), + (addrPred (i32 IntRegs:$addr), extPred:$offset)), + (MI IntRegs:$addr, extPred:$offset, (i32 IntRegs:$addend) )>; // mem[bhw](Rs+#U6:[012]) [+-&|]= Rt let AddedComplexity = 150 in diff --git a/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/lib/Target/Hexagon/HexagonMachineScheduler.cpp index 51318ff..7dd6e95 100644 --- a/lib/Target/Hexagon/HexagonMachineScheduler.cpp +++ b/lib/Target/Hexagon/HexagonMachineScheduler.cpp @@ -12,17 +12,17 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "misched" - #include "HexagonMachineScheduler.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/IR/Function.h" using namespace llvm; +#define DEBUG_TYPE "misched" + /// Platform specific modifications to DAG. void VLIWMachineScheduler::postprocessDAG() { - SUnit* LastSequentialCall = NULL; + SUnit* LastSequentialCall = nullptr; // Currently we only catch the situation when compare gets scheduled // before preceding call. for (unsigned su = 0, e = SUnits.size(); su != e; ++su) { @@ -398,13 +398,13 @@ SUnit *ConvergingVLIWScheduler::VLIWSchedBoundary::pickOnlyChoice() { for (unsigned i = 0; Available.empty(); ++i) { assert(i <= (HazardRec->getMaxLookAhead() + MaxMinLatency) && "permanent hazard"); (void)i; - ResourceModel->reserveResources(0); + ResourceModel->reserveResources(nullptr); bumpCycle(); releasePending(); } if (Available.size() == 1) return *Available.begin(); - return NULL; + return nullptr; } #ifndef NDEBUG @@ -424,7 +424,7 @@ void ConvergingVLIWScheduler::traceCandidate(const char *Label, /// getSingleUnscheduledPred - If there is exactly one unscheduled predecessor /// of SU, return it, otherwise return null. static SUnit *getSingleUnscheduledPred(SUnit *SU) { - SUnit *OnlyAvailablePred = 0; + SUnit *OnlyAvailablePred = nullptr; for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E; ++I) { SUnit &Pred = *I->getSUnit(); @@ -432,7 +432,7 @@ static SUnit *getSingleUnscheduledPred(SUnit *SU) { // We found an available, but not scheduled, predecessor. If it's the // only one we have found, keep track of it... otherwise give up. if (OnlyAvailablePred && OnlyAvailablePred != &Pred) - return 0; + return nullptr; OnlyAvailablePred = &Pred; } } @@ -442,7 +442,7 @@ static SUnit *getSingleUnscheduledPred(SUnit *SU) { /// getSingleUnscheduledSucc - If there is exactly one unscheduled successor /// of SU, return it, otherwise return null. static SUnit *getSingleUnscheduledSucc(SUnit *SU) { - SUnit *OnlyAvailableSucc = 0; + SUnit *OnlyAvailableSucc = nullptr; for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) { SUnit &Succ = *I->getSUnit(); @@ -450,7 +450,7 @@ static SUnit *getSingleUnscheduledSucc(SUnit *SU) { // We found an available, but not scheduled, successor. If it's the // only one we have found, keep track of it... otherwise give up. if (OnlyAvailableSucc && OnlyAvailableSucc != &Succ) - return 0; + return nullptr; OnlyAvailableSucc = &Succ; } } @@ -639,7 +639,7 @@ SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) { if (DAG->top() == DAG->bottom()) { assert(Top.Available.empty() && Top.Pending.empty() && Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage"); - return NULL; + return nullptr; } SUnit *SU; if (llvm::ForceTopDown) { diff --git a/lib/Target/Hexagon/HexagonMachineScheduler.h b/lib/Target/Hexagon/HexagonMachineScheduler.h index 300f1c7..99100a1 100644 --- a/lib/Target/Hexagon/HexagonMachineScheduler.h +++ b/lib/Target/Hexagon/HexagonMachineScheduler.h @@ -14,7 +14,6 @@ #ifndef HEXAGONASMPRINTER_H #define HEXAGONASMPRINTER_H -#include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/PriorityQueue.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" @@ -57,7 +56,7 @@ class VLIWResourceModel { public: VLIWResourceModel(const TargetMachine &TM, const TargetSchedModel *SM) : SchedModel(SM), TotalPackets(0) { - ResourcesModel = TM.getInstrInfo()->CreateTargetScheduleState(&TM,NULL); + ResourcesModel = TM.getInstrInfo()->CreateTargetScheduleState(&TM, nullptr); // This hard requirement could be relaxed, // but for now do not let it proceed. @@ -94,8 +93,9 @@ VLIWResourceModel(const TargetMachine &TM, const TargetSchedModel *SM) : /// top-level schedule() driver. class VLIWMachineScheduler : public ScheduleDAGMILive { public: - VLIWMachineScheduler(MachineSchedContext *C, MachineSchedStrategy *S): - ScheduleDAGMILive(C, S) {} + VLIWMachineScheduler(MachineSchedContext *C, + std::unique_ptr<MachineSchedStrategy> S) + : ScheduleDAGMILive(C, std::move(S)) {} /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's /// time to do some work. @@ -120,7 +120,7 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy { // Best scheduling cost. int SCost; - SchedCandidate(): SU(NULL), SCost(0) {} + SchedCandidate(): SU(nullptr), SCost(0) {} }; /// Represent the type of SchedCandidate found within a single queue. enum CandResult { @@ -153,9 +153,9 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy { /// Pending queues extend the ready queues with the same ID and the /// PendingFlag set. VLIWSchedBoundary(unsigned ID, const Twine &Name): - DAG(0), SchedModel(0), Available(ID, Name+".A"), + DAG(nullptr), SchedModel(nullptr), Available(ID, Name+".A"), Pending(ID << ConvergingVLIWScheduler::LogMaxQID, Name+".P"), - CheckPending(false), HazardRec(0), ResourceModel(0), + CheckPending(false), HazardRec(nullptr), ResourceModel(nullptr), CurrCycle(0), IssueCount(0), MinReadyCycle(UINT_MAX), MaxMinLatency(0) {} @@ -203,8 +203,9 @@ public: LogMaxQID = 2 }; - ConvergingVLIWScheduler(): - DAG(0), SchedModel(0), Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {} + ConvergingVLIWScheduler() + : DAG(nullptr), SchedModel(nullptr), Top(TopQID, "TopQ"), + Bot(BotQID, "BotQ") {} virtual void initialize(ScheduleDAGMI *dag) override; diff --git a/lib/Target/Hexagon/HexagonNewValueJump.cpp b/lib/Target/Hexagon/HexagonNewValueJump.cpp index 3e238bf..b7c03a7 100644 --- a/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -21,7 +21,6 @@ // // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "hexagon-nvj" #include "llvm/PassSupport.h" #include "Hexagon.h" #include "HexagonInstrInfo.h" @@ -47,6 +46,8 @@ #include <map> using namespace llvm; +#define DEBUG_TYPE "hexagon-nvj" + STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created"); static cl::opt<int> @@ -74,16 +75,16 @@ namespace { initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry()); } - virtual void getAnalysisUsage(AnalysisUsage &AU) const { + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired<MachineBranchProbabilityInfo>(); MachineFunctionPass::getAnalysisUsage(AU); } - const char *getPassName() const { + const char *getPassName() const override { return "Hexagon NewValueJump"; } - virtual bool runOnMachineFunction(MachineFunction &Fn); + bool runOnMachineFunction(MachineFunction &Fn) override; private: /// \brief A handle to the branch probability pass. @@ -393,8 +394,8 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { bool MO2IsKill = false; MachineBasicBlock::iterator jmpPos; MachineBasicBlock::iterator cmpPos; - MachineInstr *cmpInstr = NULL, *jmpInstr = NULL; - MachineBasicBlock *jmpTarget = NULL; + MachineInstr *cmpInstr = nullptr, *jmpInstr = nullptr; + MachineBasicBlock *jmpTarget = nullptr; bool afterRA = false; bool isSecondOpReg = false; bool isSecondOpNewified = false; diff --git a/lib/Target/Hexagon/HexagonPeephole.cpp b/lib/Target/Hexagon/HexagonPeephole.cpp index 5490ecd..48b6159 100644 --- a/lib/Target/Hexagon/HexagonPeephole.cpp +++ b/lib/Target/Hexagon/HexagonPeephole.cpp @@ -35,7 +35,6 @@ //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "hexagon-peephole" #include "Hexagon.h" #include "HexagonTargetMachine.h" #include "llvm/ADT/DenseMap.h" @@ -57,6 +56,8 @@ using namespace llvm; +#define DEBUG_TYPE "hexagon-peephole" + static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Peephole Optimization")); @@ -89,13 +90,13 @@ namespace { initializeHexagonPeepholePass(*PassRegistry::getPassRegistry()); } - bool runOnMachineFunction(MachineFunction &MF); + bool runOnMachineFunction(MachineFunction &MF) override; - const char *getPassName() const { + const char *getPassName() const override { return "Hexagon optimize redundant zero and size extends"; } - void getAnalysisUsage(AnalysisUsage &AU) const { + void getAnalysisUsage(AnalysisUsage &AU) const override { MachineFunctionPass::getAnalysisUsage(AU); } diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/lib/Target/Hexagon/HexagonRegisterInfo.cpp index 9a20dfd..fb466d3 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -43,13 +43,12 @@ HexagonRegisterInfo::HexagonRegisterInfo(HexagonSubtarget &st) Subtarget(st) { } -const uint16_t* HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction - *MF) - const { - static const uint16_t CalleeSavedRegsV2[] = { +const MCPhysReg * +HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { + static const MCPhysReg CalleeSavedRegsV2[] = { Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 }; - static const uint16_t CalleeSavedRegsV3[] = { + static const MCPhysReg CalleeSavedRegsV3[] = { Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.h b/lib/Target/Hexagon/HexagonRegisterInfo.h index 89af7c3..648b4af 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.h +++ b/lib/Target/Hexagon/HexagonRegisterInfo.h @@ -48,16 +48,17 @@ struct HexagonRegisterInfo : public HexagonGenRegisterInfo { HexagonRegisterInfo(HexagonSubtarget &st); /// Code Generation virtual methods... - const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const; + const MCPhysReg * + getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override; - const TargetRegisterClass* const* getCalleeSavedRegClasses( - const MachineFunction *MF = 0) const; + const TargetRegisterClass* const* + getCalleeSavedRegClasses(const MachineFunction *MF = nullptr) const; - BitVector getReservedRegs(const MachineFunction &MF) const; + BitVector getReservedRegs(const MachineFunction &MF) const override; void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, - RegScavenger *RS = NULL) const; + RegScavenger *RS = nullptr) const override; /// determineFrameLayout - Determine the size of the frame and maximum call /// frame size. @@ -65,17 +66,17 @@ struct HexagonRegisterInfo : public HexagonGenRegisterInfo { /// requiresRegisterScavenging - returns true since we may need scavenging for /// a temporary register when generating hardware loop instructions. - bool requiresRegisterScavenging(const MachineFunction &MF) const { + bool requiresRegisterScavenging(const MachineFunction &MF) const override { return true; } - bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { + bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override { return true; } // Debug information queries. unsigned getRARegister() const; - unsigned getFrameRegister(const MachineFunction &MF) const; + unsigned getFrameRegister(const MachineFunction &MF) const override; unsigned getFrameRegister() const; unsigned getStackRegister() const; }; diff --git a/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp b/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp index cadcb32..2b459a4 100644 --- a/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp +++ b/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp @@ -33,13 +33,13 @@ namespace { HexagonRemoveExtendArgs() : FunctionPass(ID) { initializeHexagonRemoveExtendArgsPass(*PassRegistry::getPassRegistry()); } - virtual bool runOnFunction(Function &F); + bool runOnFunction(Function &F) override; - const char *getPassName() const { + const char *getPassName() const override { return "Remove sign extends"; } - virtual void getAnalysisUsage(AnalysisUsage &AU) const { + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired<MachineFunctionAnalysis>(); AU.addPreserved<MachineFunctionAnalysis>(); AU.addPreserved("stack-protector"); diff --git a/lib/Target/Hexagon/HexagonSchedule.td b/lib/Target/Hexagon/HexagonSchedule.td index c2cfbb9..528cafc 100644 --- a/lib/Target/Hexagon/HexagonSchedule.td +++ b/lib/Target/Hexagon/HexagonSchedule.td @@ -7,57 +7,6 @@ // //===----------------------------------------------------------------------===// -// Functional Units -def LSUNIT : FuncUnit; // SLOT0 -def LUNIT : FuncUnit; // SLOT1 -def MUNIT : FuncUnit; // SLOT2 -def SUNIT : FuncUnit; // SLOT3 -def LOOPUNIT : FuncUnit; - -// Itinerary classes -def ALU32 : InstrItinClass; -def ALU64 : InstrItinClass; -def CR : InstrItinClass; -def J : InstrItinClass; -def JR : InstrItinClass; -def LD : InstrItinClass; -def LD0 : InstrItinClass; -def M : InstrItinClass; -def ST : InstrItinClass; -def ST0 : InstrItinClass; -def S : InstrItinClass; -def SYS : InstrItinClass; -def ENDLOOP : InstrItinClass; -def PSEUDO : InstrItinClass; -def PSEUDOM : InstrItinClass; - -def HexagonItineraries : - ProcessorItineraries<[LSUNIT, LUNIT, MUNIT, SUNIT, LOOPUNIT], [], [ - InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>, - InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>, - InstrItinData<CR , [InstrStage<1, [SUNIT]>]>, - InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>, - InstrItinData<JR , [InstrStage<1, [MUNIT]>]>, - InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>, - InstrItinData<LD0 , [InstrStage<1, [LSUNIT]>]>, - InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>, - InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>, - InstrItinData<ST0 , [InstrStage<1, [LSUNIT]>]>, - InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>, - InstrItinData<SYS , [InstrStage<1, [LSUNIT]>]>, - InstrItinData<ENDLOOP, [InstrStage<1, [LOOPUNIT]>]>, - InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>, - InstrItinData<PSEUDOM, [InstrStage<1, [MUNIT, SUNIT], 0>, - InstrStage<1, [MUNIT, SUNIT]>]> - ]>; - -def HexagonModel : SchedMachineModel { - // Max issue per cycle == bundle width. - let IssueWidth = 4; - let Itineraries = HexagonItineraries; - let LoadLatency = 1; -} - //===----------------------------------------------------------------------===// // V4 Machine Info + //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonScheduleV4.td b/lib/Target/Hexagon/HexagonScheduleV4.td index ef72cf4..a7d2d47 100644 --- a/lib/Target/Hexagon/HexagonScheduleV4.td +++ b/lib/Target/Hexagon/HexagonScheduleV4.td @@ -34,29 +34,158 @@ def SLOT3 : FuncUnit; def SLOT_ENDLOOP: FuncUnit; // Itinerary classes. -def NV_V4 : InstrItinClass; -def MEM_V4 : InstrItinClass; +def PSEUDO : InstrItinClass; +def PSEUDOM : InstrItinClass; // ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4. +def DUPLEX : InstrItinClass; def PREFIX : InstrItinClass; +def COMPOUND : InstrItinClass; + +def ALU32_2op_tc_1_SLOT0123 : InstrItinClass; +def ALU32_2op_tc_2early_SLOT0123 : InstrItinClass; +def ALU32_3op_tc_2early_SLOT0123 : InstrItinClass; +def ALU32_3op_tc_1_SLOT0123 : InstrItinClass; +def ALU32_3op_tc_2_SLOT0123 : InstrItinClass; +def ALU32_ADDI_tc_1_SLOT0123 : InstrItinClass; +def ALU64_tc_1_SLOT23 : InstrItinClass; +def ALU64_tc_1or2_SLOT23 : InstrItinClass; +def ALU64_tc_2_SLOT23 : InstrItinClass; +def ALU64_tc_2early_SLOT23 : InstrItinClass; +def ALU64_tc_3x_SLOT23 : InstrItinClass; +def CR_tc_2_SLOT3 : InstrItinClass; +def CR_tc_2early_SLOT23 : InstrItinClass; +def CR_tc_2early_SLOT3 : InstrItinClass; +def CR_tc_3x_SLOT23 : InstrItinClass; +def CR_tc_3x_SLOT3 : InstrItinClass; +def J_tc_2early_SLOT23 : InstrItinClass; +def J_tc_2early_SLOT2 : InstrItinClass; +def LD_tc_ld_SLOT01 : InstrItinClass; +def LD_tc_ld_SLOT0 : InstrItinClass; +def LD_tc_3or4stall_SLOT0 : InstrItinClass; +def M_tc_1_SLOT23 : InstrItinClass; +def M_tc_1or2_SLOT23 : InstrItinClass; +def M_tc_2_SLOT23 : InstrItinClass; +def M_tc_3_SLOT23 : InstrItinClass; +def M_tc_3x_SLOT23 : InstrItinClass; +def M_tc_3or4x_SLOT23 : InstrItinClass; +def ST_tc_st_SLOT01 : InstrItinClass; +def ST_tc_st_SLOT0 : InstrItinClass; +def ST_tc_ld_SLOT0 : InstrItinClass; +def ST_tc_3stall_SLOT0 : InstrItinClass; +def S_2op_tc_1_SLOT23 : InstrItinClass; +def S_2op_tc_2_SLOT23 : InstrItinClass; +def S_2op_tc_2early_SLOT23 : InstrItinClass; +def S_2op_tc_3or4x_SLOT23 : InstrItinClass; +def S_3op_tc_1_SLOT23 : InstrItinClass; +def S_3op_tc_1or2_SLOT23 : InstrItinClass; +def S_3op_tc_2_SLOT23 : InstrItinClass; +def S_3op_tc_2early_SLOT23 : InstrItinClass; +def S_3op_tc_3_SLOT23 : InstrItinClass; +def S_3op_tc_3x_SLOT23 : InstrItinClass; +def NCJ_tc_3or4stall_SLOT0 : InstrItinClass; +def V2LDST_tc_ld_SLOT01 : InstrItinClass; +def V2LDST_tc_st_SLOT0 : InstrItinClass; +def V2LDST_tc_st_SLOT01 : InstrItinClass; +def V4LDST_tc_ld_SLOT01 : InstrItinClass; +def V4LDST_tc_st_SLOT0 : InstrItinClass; +def V4LDST_tc_st_SLOT01 : InstrItinClass; +def J_tc_2early_SLOT0123 : InstrItinClass; +def EXTENDER_tc_1_SLOT0123 : InstrItinClass; + def HexagonItinerariesV4 : ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [ - InstrItinData<ALU32 , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData<ALU64 , [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData<CR , [InstrStage<1, [SLOT3]>]>, - InstrItinData<J , [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData<JR , [InstrStage<1, [SLOT2]>]>, - InstrItinData<LD , [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData<LD0 , [InstrStage<1, [SLOT0]>]>, - InstrItinData<M , [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData<ST , [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData<ST0 , [InstrStage<1, [SLOT0]>]>, - InstrItinData<S , [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData<SYS , [InstrStage<1, [SLOT0]>]>, - InstrItinData<NV_V4 , [InstrStage<1, [SLOT0]>]>, - InstrItinData<MEM_V4 , [InstrStage<1, [SLOT0]>]>, - InstrItinData<ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>]>, - InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + // ALU32 + InstrItinData<ALU32_2op_tc_1_SLOT0123 , + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData<ALU32_2op_tc_2early_SLOT0123, + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData<ALU32_3op_tc_1_SLOT0123 , + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData<ALU32_3op_tc_2early_SLOT0123, + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData<ALU32_3op_tc_2_SLOT0123 , + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData<ALU32_ADDI_tc_1_SLOT0123 , + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + + // ALU64 + InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<ALU64_tc_1or2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<ALU64_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + + // CR -> System + InstrItinData<CR_tc_2_SLOT3 , [InstrStage<1, [SLOT3]>]>, + InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<1, [SLOT3]>]>, + InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<1, [SLOT3]>]>, + + // Jump (conditional/unconditional/return etc) + // CR + InstrItinData<CR_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + // J + InstrItinData<J_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + // JR + InstrItinData<J_tc_2early_SLOT2 , [InstrStage<1, [SLOT2]>]>, + + //Load + InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>, + InstrItinData<LD_tc_3or4stall_SLOT0 , [InstrStage<1, [SLOT0]>]>, + + // M + InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_1or2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + + // Store + // ST + InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, + // ST0 + InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, + InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>, + + // S + InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<S_2op_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<S_3op_tc_1or2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<S_3op_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + + // SYS + InstrItinData<ST_tc_3stall_SLOT0 , [InstrStage<1, [SLOT0]>]>, + + // New Value Compare Jump + InstrItinData<NCJ_tc_3or4stall_SLOT0 , [InstrStage<1, [SLOT0]>]>, + + // Mem ops - MEM_V4 + InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, + InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, + InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, + + InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>, + + // ENDLOOP + InstrItinData<J_tc_2early_SLOT0123 , [InstrStage<1, [SLOT_ENDLOOP]>]>, + + // Extender/PREFIX + InstrItinData<EXTENDER_tc_1_SLOT0123, + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + + InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>, InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>, InstrStage<1, [SLOT2, SLOT3]>]> diff --git a/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp b/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp index c37bf9f..9e1e0fd 100644 --- a/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp +++ b/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp @@ -11,10 +11,11 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "hexagon-selectiondag-info" #include "HexagonTargetMachine.h" using namespace llvm; +#define DEBUG_TYPE "hexagon-selectiondag-info" + bool llvm::flag_aligned_memcpy; HexagonSelectionDAGInfo::HexagonSelectionDAGInfo(const HexagonTargetMachine diff --git a/lib/Target/Hexagon/HexagonSelectionDAGInfo.h b/lib/Target/Hexagon/HexagonSelectionDAGInfo.h index 31f278a..8ba6108 100644 --- a/lib/Target/Hexagon/HexagonSelectionDAGInfo.h +++ b/lib/Target/Hexagon/HexagonSelectionDAGInfo.h @@ -25,14 +25,13 @@ public: explicit HexagonSelectionDAGInfo(const HexagonTargetMachine &TM); ~HexagonSelectionDAGInfo(); - virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, - MachinePointerInfo SrcPtrInfo) const; + MachinePointerInfo SrcPtrInfo) const override; }; } diff --git a/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp b/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp index 5303f44..247207f 100644 --- a/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp +++ b/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp @@ -17,11 +17,10 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "xfer" - -#include "HexagonTargetMachine.h" #include "HexagonMachineFunctionInfo.h" #include "HexagonSubtarget.h" +#include "HexagonTargetMachine.h" +#include "HexagonTargetObjectFile.h" #include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/LatencyPriorityQueue.h" #include "llvm/CodeGen/MachineDominators.h" @@ -44,21 +43,22 @@ using namespace llvm; +#define DEBUG_TYPE "xfer" + namespace { class HexagonSplitConst32AndConst64 : public MachineFunctionPass { - const HexagonTargetMachine& QTM; - const HexagonSubtarget &QST; + const HexagonTargetMachine &QTM; public: static char ID; - HexagonSplitConst32AndConst64(const HexagonTargetMachine& TM) - : MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {} + HexagonSplitConst32AndConst64(const HexagonTargetMachine &TM) + : MachineFunctionPass(ID), QTM(TM) {} - const char *getPassName() const { + const char *getPassName() const override { return "Hexagon Split Const32s and Const64s"; } - bool runOnMachineFunction(MachineFunction &Fn); + bool runOnMachineFunction(MachineFunction &Fn) override; }; @@ -67,6 +67,12 @@ char HexagonSplitConst32AndConst64::ID = 0; bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) { + const HexagonTargetObjectFile &TLOF = + (const HexagonTargetObjectFile &) + QTM.getTargetLowering()->getObjFileLowering(); + if (TLOF.IsSmallDataEnabled()) + return true; + const TargetInstrInfo *TII = QTM.getInstrInfo(); // Loop over all of the basic blocks diff --git a/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp b/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp index 8608e08..9601090 100644 --- a/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp +++ b/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp @@ -26,7 +26,6 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "xfer" #include "Hexagon.h" #include "HexagonMachineFunctionInfo.h" #include "HexagonSubtarget.h" @@ -49,6 +48,8 @@ using namespace llvm; +#define DEBUG_TYPE "xfer" + namespace llvm { void initializeHexagonSplitTFRCondSetsPass(PassRegistry&); } @@ -67,10 +68,10 @@ class HexagonSplitTFRCondSets : public MachineFunctionPass { initializeHexagonSplitTFRCondSetsPass(*PassRegistry::getPassRegistry()); } - const char *getPassName() const { + const char *getPassName() const override { return "Hexagon Split TFRCondSets"; } - bool runOnMachineFunction(MachineFunction &Fn); + bool runOnMachineFunction(MachineFunction &Fn) override; }; @@ -221,7 +222,8 @@ bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) { static void initializePassOnce(PassRegistry &Registry) { const char *Name = "Hexagon Split TFRCondSets"; PassInfo *PI = new PassInfo(Name, "hexagon-split-tfr", - &HexagonSplitTFRCondSets::ID, 0, false, false); + &HexagonSplitTFRCondSets::ID, nullptr, false, + false); Registry.registerPass(*PI, true); } diff --git a/lib/Target/Hexagon/HexagonSubtarget.cpp b/lib/Target/Hexagon/HexagonSubtarget.cpp index fca6707..70c87fa 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -18,6 +18,8 @@ #include "llvm/Support/ErrorHandling.h" using namespace llvm; +#define DEBUG_TYPE "hexagon-subtarget" + #define GET_SUBTARGETINFO_CTOR #define GET_SUBTARGETINFO_TARGET_DESC #include "HexagonGenSubtargetInfo.inc" diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp index 9ce1fb8..b923764 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -52,7 +52,7 @@ extern "C" void LLVMInitializeHexagonTarget() { } static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) { - return new VLIWMachineScheduler(C, new ConvergingVLIWScheduler()); + return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>()); } static MachineSchedRegistry @@ -79,20 +79,6 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT, initAsmInfo(); } -// addPassesForOptimizations - Allow the backend (target) to add Target -// Independent Optimization passes to the Pass Manager. -bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) { - if (getOptLevel() != CodeGenOpt::None) { - PM.add(createConstantPropagationPass()); - PM.add(createLoopSimplifyPass()); - PM.add(createDeadCodeEliminationPass()); - PM.add(createConstantPropagationPass()); - PM.add(createLoopUnrollPass()); - PM.add(createLoopStrengthReducePass()); - } - return true; -} - namespace { /// Hexagon Code Generator Pass Configuration Options. class HexagonPassConfig : public TargetPassConfig { @@ -113,16 +99,16 @@ public: return getTM<HexagonTargetMachine>(); } - virtual ScheduleDAGInstrs * - createMachineScheduler(MachineSchedContext *C) const { + ScheduleDAGInstrs * + createMachineScheduler(MachineSchedContext *C) const override { return createVLIWMachineSched(C); } - virtual bool addInstSelector(); - virtual bool addPreRegAlloc(); - virtual bool addPostRegAlloc(); - virtual bool addPreSched2(); - virtual bool addPreEmitPass(); + bool addInstSelector() override; + bool addPreRegAlloc() override; + bool addPostRegAlloc() override; + bool addPreSched2() override; + bool addPreEmitPass() override; }; } // namespace @@ -164,16 +150,12 @@ bool HexagonPassConfig::addPostRegAlloc() { bool HexagonPassConfig::addPreSched2() { const HexagonTargetMachine &TM = getHexagonTargetMachine(); - const HexagonTargetObjectFile &TLOF = - (const HexagonTargetObjectFile &)getTargetLowering()->getObjFileLowering(); addPass(createHexagonCopyToCombine()); if (getOptLevel() != CodeGenOpt::None) addPass(&IfConverterID); - if (!TLOF.IsSmallDataEnabled()) { - addPass(createHexagonSplitConst32AndConst64(TM)); - printAndVerify("After hexagon split const32/64 pass"); - } + addPass(createHexagonSplitConst32AndConst64(TM)); + printAndVerify("After hexagon split const32/64 pass"); return true; } diff --git a/lib/Target/Hexagon/HexagonTargetMachine.h b/lib/Target/Hexagon/HexagonTargetMachine.h index cf8f9aa..70b835e 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.h +++ b/lib/Target/Hexagon/HexagonTargetMachine.h @@ -41,39 +41,37 @@ public: Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); - virtual const HexagonInstrInfo *getInstrInfo() const { + const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; } - virtual const HexagonSubtarget *getSubtargetImpl() const { + const HexagonSubtarget *getSubtargetImpl() const override { return &Subtarget; } - virtual const HexagonRegisterInfo *getRegisterInfo() const { + const HexagonRegisterInfo *getRegisterInfo() const override { return &InstrInfo.getRegisterInfo(); } - virtual const InstrItineraryData* getInstrItineraryData() const { + const InstrItineraryData* getInstrItineraryData() const override { return InstrItins; } - virtual const HexagonTargetLowering* getTargetLowering() const { + const HexagonTargetLowering* getTargetLowering() const override { return &TLInfo; } - virtual const HexagonFrameLowering* getFrameLowering() const { + const HexagonFrameLowering* getFrameLowering() const override { return &FrameLowering; } - virtual const HexagonSelectionDAGInfo* getSelectionDAGInfo() const { + const HexagonSelectionDAGInfo* getSelectionDAGInfo() const override { return &TSInfo; } - virtual const DataLayout *getDataLayout() const { return &DL; } + const DataLayout *getDataLayout() const override { return &DL; } static unsigned getModuleMatchQuality(const Module &M); - // Pass Pipeline Configuration. - virtual bool addPassesForOptimizations(PassManagerBase &PM); - virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); + TargetPassConfig *createPassConfig(PassManagerBase &PM) override; }; extern bool flag_aligned_memcpy; diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 976ff2b..87ce960 100644 --- a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -16,7 +16,6 @@ // prune the dependence. // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "packets" #include "llvm/CodeGen/DFAPacketizer.h" #include "Hexagon.h" #include "HexagonMachineFunctionInfo.h" @@ -51,6 +50,8 @@ using namespace llvm; +#define DEBUG_TYPE "packets" + static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles", cl::ZeroOrMore, cl::Hidden, cl::init(true), cl::desc("Allow non-solo packetization of volatile memory references")); @@ -69,7 +70,7 @@ namespace { initializeHexagonPacketizerPass(*PassRegistry::getPassRegistry()); } - void getAnalysisUsage(AnalysisUsage &AU) const { + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); AU.addRequired<MachineDominatorTree>(); AU.addRequired<MachineBranchProbabilityInfo>(); @@ -79,11 +80,11 @@ namespace { MachineFunctionPass::getAnalysisUsage(AU); } - const char *getPassName() const { + const char *getPassName() const override { return "Hexagon Packetizer"; } - bool runOnMachineFunction(MachineFunction &Fn); + bool runOnMachineFunction(MachineFunction &Fn) override; }; char HexagonPacketizer::ID = 0; @@ -121,24 +122,25 @@ namespace { const MachineBranchProbabilityInfo *MBPI); // initPacketizerState - initialize some internal flags. - void initPacketizerState(); + void initPacketizerState() override; // ignorePseudoInstruction - Ignore bundling of pseudo instructions. - bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB); + bool ignorePseudoInstruction(MachineInstr *MI, + MachineBasicBlock *MBB) override; // isSoloInstruction - return true if instruction MI can not be packetized // with any other instruction, which means that MI itself is a packet. - bool isSoloInstruction(MachineInstr *MI); + bool isSoloInstruction(MachineInstr *MI) override; // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ // together. - bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ); + bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override; // isLegalToPruneDependencies - Is it legal to prune dependece between SUI // and SUJ. - bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ); + bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override; - MachineBasicBlock::iterator addToPacket(MachineInstr *MI); + MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override; private: bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg); bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType, @@ -390,7 +392,7 @@ static bool IsLoopN(MachineInstr *MI) { /// callee-saved register. static bool DoesModifyCalleeSavedReg(MachineInstr *MI, const TargetRegisterInfo *TRI) { - for (const uint16_t *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) { + for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) { unsigned CalleeSavedReg = *CSR; if (MI->modifiesRegister(CalleeSavedReg, TRI)) return true; @@ -603,7 +605,7 @@ bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI, // evaluate identically unsigned predRegNumSrc = 0; unsigned predRegNumDst = 0; - const TargetRegisterClass* predRegClass = NULL; + const TargetRegisterClass* predRegClass = nullptr; // Get predicate register used in the source instruction for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) { @@ -1172,7 +1174,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { // of that (IsCallDependent) function. Bug 6216 is opened for this. // unsigned DepReg = 0; - const TargetRegisterClass* RC = NULL; + const TargetRegisterClass* RC = nullptr; if (DepType == SDep::Data) { DepReg = SUJ->Succs[i].getReg(); RC = QRI->getMinimalPhysRegClass(DepReg); diff --git a/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp b/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp index 33667f4..9942a60 100644 --- a/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp +++ b/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp @@ -11,7 +11,6 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "asm-printer" #include "HexagonAsmPrinter.h" #include "Hexagon.h" #include "HexagonInstPrinter.h" @@ -24,6 +23,8 @@ using namespace llvm; +#define DEBUG_TYPE "asm-printer" + #define GET_INSTRUCTION_NAME #include "HexagonGenAsmWriter.inc" diff --git a/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h b/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h index d0cef68..09e3f88 100644 --- a/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h +++ b/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h @@ -27,7 +27,7 @@ namespace llvm { const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI), MII(MII) {} - virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot); + void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override; void printInst(const HexagonMCInst *MI, raw_ostream &O, StringRef Annot); virtual StringRef getOpcodeName(unsigned Opcode) const; void printInstruction(const MCInst *MI, raw_ostream &O); diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index 8519cf3..f8be77c 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -87,70 +87,82 @@ namespace HexagonII { // Solo instructions. SoloPos = 5, SoloMask = 0x1, + // Packed only with A or X-type instructions. + SoloAXPos = 6, + SoloAXMask = 0x1, + // Only A-type instruction in first slot or nothing. + SoloAin1Pos = 7, + SoloAin1Mask = 0x1, // Predicated instructions. - PredicatedPos = 6, + PredicatedPos = 8, PredicatedMask = 0x1, - PredicatedFalsePos = 7, + PredicatedFalsePos = 9, PredicatedFalseMask = 0x1, - PredicatedNewPos = 8, + PredicatedNewPos = 10, PredicatedNewMask = 0x1, + PredicateLatePos = 11, + PredicateLateMask = 0x1, // New-Value consumer instructions. - NewValuePos = 9, + NewValuePos = 12, NewValueMask = 0x1, - // New-Value producer instructions. - hasNewValuePos = 10, + hasNewValuePos = 13, hasNewValueMask = 0x1, - // Which operand consumes or produces a new value. - NewValueOpPos = 11, + NewValueOpPos = 14, NewValueOpMask = 0x7, - - // Which bits encode the new value. - NewValueBitsPos = 14, - NewValueBitsMask = 0x3, - // Stores that can become new-value stores. - mayNVStorePos = 16, + mayNVStorePos = 17, mayNVStoreMask = 0x1, - // New-value store instructions. - NVStorePos = 17, + NVStorePos = 18, NVStoreMask = 0x1, + // Loads that can become current-value loads. + mayCVLoadPos = 19, + mayCVLoadMask = 0x1, + // Current-value load instructions. + CVLoadPos = 20, + CVLoadMask = 0x1, // Extendable insns. - ExtendablePos = 18, + ExtendablePos = 21, ExtendableMask = 0x1, - // Insns must be extended. - ExtendedPos = 19, + ExtendedPos = 22, ExtendedMask = 0x1, - // Which operand may be extended. - ExtendableOpPos = 20, + ExtendableOpPos = 23, ExtendableOpMask = 0x7, - // Signed or unsigned range. - ExtentSignedPos = 23, + ExtentSignedPos = 26, ExtentSignedMask = 0x1, - // Number of bits of range before extending operand. - ExtentBitsPos = 24, + ExtentBitsPos = 27, ExtentBitsMask = 0x1f, + // Alignment power-of-two before extending operand. + ExtentAlignPos = 32, + ExtentAlignMask = 0x3, // Valid subtargets - validSubTargetPos = 29, + validSubTargetPos = 34, validSubTargetMask = 0xf, // Addressing mode for load/store instructions. - AddrModePos = 33, + AddrModePos = 40, AddrModeMask = 0x7, + // Access size for load/store instructions. + MemAccessSizePos = 43, + MemAccesSizeMask = 0x7, + + // Branch predicted taken. + TakenPos = 47, + TakenMask = 0x1, - // Access size of memory access instructions (load/store). - MemAccessSizePos = 36, - MemAccesSizeMask = 0x7 + // Floating-point instructions. + FPPos = 48, + FPMask = 0x1 }; // *** The code above must match HexagonInstrFormat*.td *** // diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp index f1a65c3..141e514 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp @@ -21,7 +21,7 @@ void HexagonMCAsmInfo::anchor() {} HexagonMCAsmInfo::HexagonMCAsmInfo(StringRef TT) { Data16bitsDirective = "\t.half\t"; Data32bitsDirective = "\t.word\t"; - Data64bitsDirective = 0; // .xword is only supported by V9. + Data64bitsDirective = nullptr; // .xword is only supported by V9. ZeroDirective = "\t.skip\t"; CommentString = "//"; HasLEB128 = true; diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h index bd8cb76..953d804 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h @@ -19,7 +19,7 @@ namespace llvm { class HexagonMCAsmInfo : public MCAsmInfoELF { - virtual void anchor(); + void anchor() override; public: explicit HexagonMCAsmInfo(StringRef TT); }; diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h index 3ca71f0..3c52d45 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h @@ -31,7 +31,7 @@ namespace llvm { public: explicit HexagonMCInst(): - MCInst(), MCID(0), packetStart(0), packetEnd(0) {}; + MCInst(), MCID(nullptr), packetStart(0), packetEnd(0) {}; HexagonMCInst(const MCInstrDesc& mcid): MCInst(), MCID(&mcid), packetStart(0), packetEnd(0) {}; diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 7f103d8..581674d 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -23,6 +23,8 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" +using namespace llvm; + #define GET_INSTRINFO_MC_DESC #include "HexagonGenInstrInfo.inc" @@ -32,8 +34,6 @@ #define GET_REGINFO_MC_DESC #include "HexagonGenRegisterInfo.inc" -using namespace llvm; - static MCInstrInfo *createHexagonMCInstrInfo() { MCInstrInfo *X = new MCInstrInfo(); InitHexagonMCInstrInfo(X); @@ -60,7 +60,7 @@ static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, // VirtualFP = (R30 + #0). MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( - 0, Hexagon::R30, 0); + nullptr, Hexagon::R30, 0); MAI->addInitialFrameState(Inst); return MAI; |