aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/X86
diff options
context:
space:
mode:
Diffstat (limited to 'lib/Target/X86')
-rw-r--r--lib/Target/X86/FloatingPoint.cpp6
-rw-r--r--lib/Target/X86/InstSelectPattern.cpp5
-rw-r--r--lib/Target/X86/InstSelectSimple.cpp25
-rw-r--r--lib/Target/X86/PeepholeOptimizer.cpp4
-rw-r--r--lib/Target/X86/Printer.cpp4
-rw-r--r--lib/Target/X86/X86.h5
-rw-r--r--lib/Target/X86/X86AsmPrinter.cpp4
-rw-r--r--lib/Target/X86/X86CodeEmitter.cpp4
-rw-r--r--lib/Target/X86/X86FloatingPoint.cpp6
-rw-r--r--lib/Target/X86/X86ISelPattern.cpp5
-rw-r--r--lib/Target/X86/X86ISelSimple.cpp25
-rw-r--r--lib/Target/X86/X86InstrBuilder.h4
-rw-r--r--lib/Target/X86/X86InstrInfo.cpp2
-rw-r--r--lib/Target/X86/X86InstrInfo.h4
-rw-r--r--lib/Target/X86/X86PeepholeOpt.cpp4
-rw-r--r--lib/Target/X86/X86RegisterInfo.cpp8
-rw-r--r--lib/Target/X86/X86RegisterInfo.h6
-rw-r--r--lib/Target/X86/X86TargetMachine.cpp4
-rw-r--r--lib/Target/X86/X86TargetMachine.h4
19 files changed, 102 insertions, 27 deletions
diff --git a/lib/Target/X86/FloatingPoint.cpp b/lib/Target/X86/FloatingPoint.cpp
index 07e58ba..5c6e6eb 100644
--- a/lib/Target/X86/FloatingPoint.cpp
+++ b/lib/Target/X86/FloatingPoint.cpp
@@ -25,6 +25,8 @@
#include <algorithm>
#include <iostream>
+namespace llvm {
+
namespace {
Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted");
Statistic<> NumFP ("x86-codegen", "Number of floating point instructions");
@@ -70,7 +72,7 @@ namespace {
// getSTReg - Return the X86::ST(i) register which contains the specified
// FP<RegNo> register
unsigned getSTReg(unsigned RegNo) const {
- return StackTop - 1 - getSlot(RegNo) + X86::ST0;
+ return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
}
// pushReg - Push the specifiex FP<n> register onto the stack
@@ -598,3 +600,5 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
I = MBB->erase(I)-1; // Remove the pseudo instruction
}
+
+} // End llvm namespace
diff --git a/lib/Target/X86/InstSelectPattern.cpp b/lib/Target/X86/InstSelectPattern.cpp
index 434ceee..e518294 100644
--- a/lib/Target/X86/InstSelectPattern.cpp
+++ b/lib/Target/X86/InstSelectPattern.cpp
@@ -28,6 +28,8 @@
// Include the generated instruction selector...
#include "X86GenInstrSelector.inc"
+namespace llvm {
+
namespace {
struct ISel : public FunctionPass, SelectionDAGTargetBuilder {
TargetMachine &TM;
@@ -114,7 +116,6 @@ void ISel::expandCall(SelectionDAG &SD, CallInst &CI) {
assert(0 && "ISel::expandCall not implemented!");
}
-
/// createX86PatternInstructionSelector - This pass converts an LLVM function
/// into a machine code representation using pattern matching and a machine
/// description file.
@@ -122,3 +123,5 @@ void ISel::expandCall(SelectionDAG &SD, CallInst &CI) {
FunctionPass *createX86PatternInstructionSelector(TargetMachine &TM) {
return new ISel(TM);
}
+
+} // End llvm namespace
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp
index 1242545..de341c4 100644
--- a/lib/Target/X86/InstSelectSimple.cpp
+++ b/lib/Target/X86/InstSelectSimple.cpp
@@ -29,6 +29,8 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/InstVisitor.h"
+namespace llvm {
+
/// BMI - A special BuildMI variant that takes an iterator to insert the
/// instruction at as well as a basic block. This is the version for when you
/// have a destination register in mind.
@@ -138,7 +140,7 @@ namespace {
void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
const std::vector<ValueRecord> &Args);
void visitCallInst(CallInst &I);
- void visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &I);
+ void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
// Arithmetic operators
void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
@@ -1045,7 +1047,7 @@ void ISel::visitCallInst(CallInst &CI) {
MachineInstr *TheCall;
if (Function *F = CI.getCalledFunction()) {
// Is it an intrinsic function call?
- if (LLVMIntrinsic::ID ID = (LLVMIntrinsic::ID)F->getIntrinsicID()) {
+ if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
return;
}
@@ -1066,29 +1068,29 @@ void ISel::visitCallInst(CallInst &CI) {
}
-void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) {
+void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
unsigned TmpReg1, TmpReg2;
switch (ID) {
- case LLVMIntrinsic::va_start:
+ case Intrinsic::va_start:
// Get the address of the first vararg value...
TmpReg1 = getReg(CI);
addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
return;
- case LLVMIntrinsic::va_copy:
+ case Intrinsic::va_copy:
TmpReg1 = getReg(CI);
TmpReg2 = getReg(CI.getOperand(1));
BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2);
return;
- case LLVMIntrinsic::va_end: return; // Noop on X86
+ case Intrinsic::va_end: return; // Noop on X86
- case LLVMIntrinsic::longjmp:
- case LLVMIntrinsic::siglongjmp:
+ case Intrinsic::longjmp:
+ case Intrinsic::siglongjmp:
BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("abort", true);
return;
- case LLVMIntrinsic::setjmp:
- case LLVMIntrinsic::sigsetjmp:
+ case Intrinsic::setjmp:
+ case Intrinsic::sigsetjmp:
// Setjmp always returns zero...
BuildMI(BB, X86::MOVir32, 1, getReg(CI)).addZImm(0);
return;
@@ -2127,7 +2129,6 @@ void ISel::visitFreeInst(FreeInst &I) {
doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
}
-
/// createX86SimpleInstructionSelector - This pass converts an LLVM function
/// into a machine code representation is a very simple peep-hole fashion. The
/// generated code sucks but the implementation is nice and simple.
@@ -2135,3 +2136,5 @@ void ISel::visitFreeInst(FreeInst &I) {
FunctionPass *createX86SimpleInstructionSelector(TargetMachine &TM) {
return new ISel(TM);
}
+
+} // End llvm namespace
diff --git a/lib/Target/X86/PeepholeOptimizer.cpp b/lib/Target/X86/PeepholeOptimizer.cpp
index fbc84f7..2f3280a 100644
--- a/lib/Target/X86/PeepholeOptimizer.cpp
+++ b/lib/Target/X86/PeepholeOptimizer.cpp
@@ -15,6 +15,8 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+namespace llvm {
+
namespace {
struct PH : public MachineFunctionPass {
virtual bool runOnMachineFunction(MachineFunction &MF);
@@ -131,3 +133,5 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
return false;
}
}
+
+} // End llvm namespace
diff --git a/lib/Target/X86/Printer.cpp b/lib/Target/X86/Printer.cpp
index 3d073f7..292a465 100644
--- a/lib/Target/X86/Printer.cpp
+++ b/lib/Target/X86/Printer.cpp
@@ -29,6 +29,8 @@
#include "Support/StringExtras.h"
#include "Support/CommandLine.h"
+namespace llvm {
+
namespace {
Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
@@ -960,3 +962,5 @@ bool Printer::doFinalization(Module &M) {
delete Mang;
return false; // success
}
+
+} // End llvm namespace
diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h
index 01041f8..5cf897f 100644
--- a/lib/Target/X86/X86.h
+++ b/lib/Target/X86/X86.h
@@ -16,6 +16,9 @@
#define TARGET_X86_H
#include <iosfwd>
+
+namespace llvm {
+
class TargetMachine;
class FunctionPass;
@@ -58,6 +61,8 @@ FunctionPass *createEmitX86CodeToMemory();
// Defines symbolic names for X86 registers. This defines a mapping from
// register name to register number.
//
+} // End llvm namespace
+
#include "X86GenRegisterNames.inc"
// Defines symbolic names for the X86 instructions.
diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp
index 3d073f7..292a465 100644
--- a/lib/Target/X86/X86AsmPrinter.cpp
+++ b/lib/Target/X86/X86AsmPrinter.cpp
@@ -29,6 +29,8 @@
#include "Support/StringExtras.h"
#include "Support/CommandLine.h"
+namespace llvm {
+
namespace {
Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
@@ -960,3 +962,5 @@ bool Printer::doFinalization(Module &M) {
delete Mang;
return false; // success
}
+
+} // End llvm namespace
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index f49fde5..e24e290 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -24,6 +24,8 @@
#include "Support/Statistic.h"
#include "Config/alloca.h"
+namespace llvm {
+
namespace {
Statistic<>
NumEmitted("x86-emitter", "Number of machine instructions emitted");
@@ -589,3 +591,5 @@ void Emitter::emitInstruction(MachineInstr &MI) {
break;
}
}
+
+} // End llvm namespace
diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index 07e58ba..5c6e6eb 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -25,6 +25,8 @@
#include <algorithm>
#include <iostream>
+namespace llvm {
+
namespace {
Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted");
Statistic<> NumFP ("x86-codegen", "Number of floating point instructions");
@@ -70,7 +72,7 @@ namespace {
// getSTReg - Return the X86::ST(i) register which contains the specified
// FP<RegNo> register
unsigned getSTReg(unsigned RegNo) const {
- return StackTop - 1 - getSlot(RegNo) + X86::ST0;
+ return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
}
// pushReg - Push the specifiex FP<n> register onto the stack
@@ -598,3 +600,5 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
I = MBB->erase(I)-1; // Remove the pseudo instruction
}
+
+} // End llvm namespace
diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index 434ceee..e518294 100644
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -28,6 +28,8 @@
// Include the generated instruction selector...
#include "X86GenInstrSelector.inc"
+namespace llvm {
+
namespace {
struct ISel : public FunctionPass, SelectionDAGTargetBuilder {
TargetMachine &TM;
@@ -114,7 +116,6 @@ void ISel::expandCall(SelectionDAG &SD, CallInst &CI) {
assert(0 && "ISel::expandCall not implemented!");
}
-
/// createX86PatternInstructionSelector - This pass converts an LLVM function
/// into a machine code representation using pattern matching and a machine
/// description file.
@@ -122,3 +123,5 @@ void ISel::expandCall(SelectionDAG &SD, CallInst &CI) {
FunctionPass *createX86PatternInstructionSelector(TargetMachine &TM) {
return new ISel(TM);
}
+
+} // End llvm namespace
diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index 1242545..de341c4 100644
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -29,6 +29,8 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/InstVisitor.h"
+namespace llvm {
+
/// BMI - A special BuildMI variant that takes an iterator to insert the
/// instruction at as well as a basic block. This is the version for when you
/// have a destination register in mind.
@@ -138,7 +140,7 @@ namespace {
void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
const std::vector<ValueRecord> &Args);
void visitCallInst(CallInst &I);
- void visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &I);
+ void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
// Arithmetic operators
void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
@@ -1045,7 +1047,7 @@ void ISel::visitCallInst(CallInst &CI) {
MachineInstr *TheCall;
if (Function *F = CI.getCalledFunction()) {
// Is it an intrinsic function call?
- if (LLVMIntrinsic::ID ID = (LLVMIntrinsic::ID)F->getIntrinsicID()) {
+ if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
return;
}
@@ -1066,29 +1068,29 @@ void ISel::visitCallInst(CallInst &CI) {
}
-void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) {
+void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
unsigned TmpReg1, TmpReg2;
switch (ID) {
- case LLVMIntrinsic::va_start:
+ case Intrinsic::va_start:
// Get the address of the first vararg value...
TmpReg1 = getReg(CI);
addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex);
return;
- case LLVMIntrinsic::va_copy:
+ case Intrinsic::va_copy:
TmpReg1 = getReg(CI);
TmpReg2 = getReg(CI.getOperand(1));
BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2);
return;
- case LLVMIntrinsic::va_end: return; // Noop on X86
+ case Intrinsic::va_end: return; // Noop on X86
- case LLVMIntrinsic::longjmp:
- case LLVMIntrinsic::siglongjmp:
+ case Intrinsic::longjmp:
+ case Intrinsic::siglongjmp:
BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("abort", true);
return;
- case LLVMIntrinsic::setjmp:
- case LLVMIntrinsic::sigsetjmp:
+ case Intrinsic::setjmp:
+ case Intrinsic::sigsetjmp:
// Setjmp always returns zero...
BuildMI(BB, X86::MOVir32, 1, getReg(CI)).addZImm(0);
return;
@@ -2127,7 +2129,6 @@ void ISel::visitFreeInst(FreeInst &I) {
doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
}
-
/// createX86SimpleInstructionSelector - This pass converts an LLVM function
/// into a machine code representation is a very simple peep-hole fashion. The
/// generated code sucks but the implementation is nice and simple.
@@ -2135,3 +2136,5 @@ void ISel::visitFreeInst(FreeInst &I) {
FunctionPass *createX86SimpleInstructionSelector(TargetMachine &TM) {
return new ISel(TM);
}
+
+} // End llvm namespace
diff --git a/lib/Target/X86/X86InstrBuilder.h b/lib/Target/X86/X86InstrBuilder.h
index a6d65d4..a5643bd 100644
--- a/lib/Target/X86/X86InstrBuilder.h
+++ b/lib/Target/X86/X86InstrBuilder.h
@@ -26,6 +26,8 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
+namespace llvm {
+
/// addDirectMem - This function is used to add a direct memory reference to the
/// current instruction -- that is, a dereference of an address in a register,
/// with no scale, index or displacement. An example is: DWORD PTR [EAX].
@@ -69,4 +71,6 @@ addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
return MIB.addConstantPoolIndex(CPI).addZImm(1).addReg(0).addSImm(Offset);
}
+} // End llvm namespace
+
#endif
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 012cead..681bf02 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -17,6 +17,8 @@
#include "X86GenInstrInfo.inc"
+using namespace llvm;
+
X86InstrInfo::X86InstrInfo()
: TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
}
diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index 26b2618..2bf82d1 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -17,6 +17,8 @@
#include "llvm/Target/TargetInstrInfo.h"
#include "X86RegisterInfo.h"
+namespace llvm {
+
/// X86II - This namespace holds all of the target specific flags that
/// instruction info tracks.
///
@@ -181,4 +183,6 @@ public:
}
};
+} // End llvm namespace
+
#endif
diff --git a/lib/Target/X86/X86PeepholeOpt.cpp b/lib/Target/X86/X86PeepholeOpt.cpp
index fbc84f7..2f3280a 100644
--- a/lib/Target/X86/X86PeepholeOpt.cpp
+++ b/lib/Target/X86/X86PeepholeOpt.cpp
@@ -15,6 +15,8 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+namespace llvm {
+
namespace {
struct PH : public MachineFunctionPass {
virtual bool runOnMachineFunction(MachineFunction &MF);
@@ -131,3 +133,5 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
return false;
}
}
+
+} // End llvm namespace
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index fd8a615..0e8b889 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -25,6 +25,8 @@
#include "llvm/Target/TargetFrameInfo.h"
#include "Support/CommandLine.h"
+namespace llvm {
+
namespace {
cl::opt<bool>
NoFPElim("disable-fp-elim",
@@ -253,8 +255,12 @@ int X86RegisterInfo::emitEpilogue(MachineFunction &MF,
return MBB.size() - oldSize;
}
+} // End llvm namespace
+
#include "X86GenRegisterInfo.inc"
+namespace llvm {
+
const TargetRegisterClass*
X86RegisterInfo::getRegClassForType(const Type* Ty) const {
switch (Ty->getPrimitiveID()) {
@@ -274,3 +280,5 @@ X86RegisterInfo::getRegClassForType(const Type* Ty) const {
case Type::DoubleTyID: return &RFPInstance;
}
}
+
+} // End llvm namespace
diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h
index 0db8e18..77a8a1a 100644
--- a/lib/Target/X86/X86RegisterInfo.h
+++ b/lib/Target/X86/X86RegisterInfo.h
@@ -16,10 +16,12 @@
#include "llvm/Target/MRegisterInfo.h"
-class Type;
+class llvm::Type;
#include "X86GenRegisterInfo.h.inc"
+namespace llvm {
+
struct X86RegisterInfo : public X86GenRegisterInfo {
X86RegisterInfo();
const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
@@ -52,4 +54,6 @@ struct X86RegisterInfo : public X86GenRegisterInfo {
int emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
};
+} // End llvm namespace
+
#endif
diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index 954d4f4..31eb4bd 100644
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -22,6 +22,8 @@
#include "Support/CommandLine.h"
#include "Support/Statistic.h"
+namespace llvm {
+
namespace {
cl::opt<bool> PrintCode("print-machineinstrs",
cl::desc("Print generated machine code"));
@@ -153,3 +155,5 @@ void X86TargetMachine::replaceMachineCodeForFunction (void *Old, void *New) {
int32_t OldAddr = (intptr_t) OldWord;
*OldWord = NewAddr - OldAddr - 4; // Emit PC-relative addr of New code.
}
+
+} // End llvm namespace
diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h
index 5581da4..12f5c0e6 100644
--- a/lib/Target/X86/X86TargetMachine.h
+++ b/lib/Target/X86/X86TargetMachine.h
@@ -19,6 +19,8 @@
#include "llvm/PassManager.h"
#include "X86InstrInfo.h"
+namespace llvm {
+
class X86TargetMachine : public TargetMachine {
X86InstrInfo InstrInfo;
TargetFrameInfo FrameInfo;
@@ -55,4 +57,6 @@ public:
virtual void replaceMachineCodeForFunction (void *Old, void *New);
};
+} // End llvm namespace
+
#endif
generated by cgit v1.1 at 2025-08-16 00:15:36 +0000