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-rw-r--r--test/CodeGen/ARM/vpadd.ll32
1 files changed, 16 insertions, 16 deletions
diff --git a/test/CodeGen/ARM/vpadd.ll b/test/CodeGen/ARM/vpadd.ll
index 1ba68f5..f84721f 100644
--- a/test/CodeGen/ARM/vpadd.ll
+++ b/test/CodeGen/ARM/vpadd.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpaddi8:
+;CHECK-LABEL: vpaddi8:
;CHECK: vpadd.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
}
define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpaddi16:
+;CHECK-LABEL: vpaddi16:
;CHECK: vpadd.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
}
define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpaddi32:
+;CHECK-LABEL: vpaddi32:
;CHECK: vpadd.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
}
define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vpaddf32:
+;CHECK-LABEL: vpaddf32:
;CHECK: vpadd.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
@@ -43,7 +43,7 @@ declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind read
declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
-;CHECK: vpaddls8:
+;CHECK-LABEL: vpaddls8:
;CHECK: vpaddl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1)
@@ -51,7 +51,7 @@ define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
}
define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
-;CHECK: vpaddls16:
+;CHECK-LABEL: vpaddls16:
;CHECK: vpaddl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1)
@@ -59,7 +59,7 @@ define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
}
define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
-;CHECK: vpaddls32:
+;CHECK-LABEL: vpaddls32:
;CHECK: vpaddl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1)
@@ -67,7 +67,7 @@ define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
}
define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
-;CHECK: vpaddlu8:
+;CHECK-LABEL: vpaddlu8:
;CHECK: vpaddl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1)
@@ -75,7 +75,7 @@ define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
}
define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
-;CHECK: vpaddlu16:
+;CHECK-LABEL: vpaddlu16:
;CHECK: vpaddl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1)
@@ -83,7 +83,7 @@ define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
}
define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
-;CHECK: vpaddlu32:
+;CHECK-LABEL: vpaddlu32:
;CHECK: vpaddl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1)
@@ -91,7 +91,7 @@ define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
}
define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
-;CHECK: vpaddlQs8:
+;CHECK-LABEL: vpaddlQs8:
;CHECK: vpaddl.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1)
@@ -99,7 +99,7 @@ define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
}
define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
-;CHECK: vpaddlQs16:
+;CHECK-LABEL: vpaddlQs16:
;CHECK: vpaddl.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1)
@@ -107,7 +107,7 @@ define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
}
define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
-;CHECK: vpaddlQs32:
+;CHECK-LABEL: vpaddlQs32:
;CHECK: vpaddl.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1)
@@ -115,7 +115,7 @@ define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
}
define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
-;CHECK: vpaddlQu8:
+;CHECK-LABEL: vpaddlQu8:
;CHECK: vpaddl.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1)
@@ -123,7 +123,7 @@ define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
}
define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
-;CHECK: vpaddlQu16:
+;CHECK-LABEL: vpaddlQu16:
;CHECK: vpaddl.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1)
@@ -131,7 +131,7 @@ define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
}
define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind {
-;CHECK: vpaddlQu32:
+;CHECK-LABEL: vpaddlQu32:
;CHECK: vpaddl.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)