2613 files changed, 64166 insertions, 29357 deletions

diff --git a/test/Analysis/BlockFrequencyInfo/basic.ll b/test/Analysis/BlockFrequencyInfo/basic.ll
index 540d06b..ce29fb5 100644
--- a/test/Analysis/BlockFrequencyInfo/basic.ll
+++ b/test/Analysis/BlockFrequencyInfo/basic.ll
@@ -2,12 +2,12 @@
 
 define i32 @test1(i32 %i, i32* %a) {
 ; CHECK: Printing analysis {{.*}} for function 'test1'
-; CHECK: entry = 1024
+; CHECK: entry = 1.0
 entry:
   br label %body
 
 ; Loop backedges are weighted and thus their bodies have a greater frequency.
-; CHECK: body = 31744
+; CHECK: body = 32.0
 body:
   %iv = phi i32 [ 0, %entry ], [ %next, %body ]
   %base = phi i32 [ 0, %entry ], [ %sum, %body ]
@@ -18,29 +18,29 @@ body:
   %exitcond = icmp eq i32 %next, %i
   br i1 %exitcond, label %exit, label %body
 
-; CHECK: exit = 1024
+; CHECK: exit = 1.0
 exit:
   ret i32 %sum
 }
 
 define i32 @test2(i32 %i, i32 %a, i32 %b) {
 ; CHECK: Printing analysis {{.*}} for function 'test2'
-; CHECK: entry = 1024
+; CHECK: entry = 1.0
 entry:
   %cond = icmp ult i32 %i, 42
   br i1 %cond, label %then, label %else, !prof !0
 
 ; The 'then' branch is predicted more likely via branch weight metadata.
-; CHECK: then = 963
+; CHECK: then = 0.94116
 then:
   br label %exit
 
-; CHECK: else = 60
+; CHECK: else = 0.05877
 else:
   br label %exit
 
-; FIXME: It may be a bug that we don't sum back to 1024.
-; CHECK: exit = 1023
+; FIXME: It may be a bug that we don't sum back to 1.0.
+; CHECK: exit = 0.99993
 exit:
   %result = phi i32 [ %a, %then ], [ %b, %else ]
   ret i32 %result
@@ -50,36 +50,36 @@ exit:
 
 define i32 @test3(i32 %i, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
 ; CHECK: Printing analysis {{.*}} for function 'test3'
-; CHECK: entry = 1024
+; CHECK: entry = 1.0
 entry:
   switch i32 %i, label %case_a [ i32 1, label %case_b
                                  i32 2, label %case_c
                                  i32 3, label %case_d
                                  i32 4, label %case_e ], !prof !1
 
-; CHECK: case_a = 51
+; CHECK: case_a = 0.04998
 case_a:
   br label %exit
 
-; CHECK: case_b = 51
+; CHECK: case_b = 0.04998
 case_b:
   br label %exit
 
 ; The 'case_c' branch is predicted more likely via branch weight metadata.
-; CHECK: case_c = 819
+; CHECK: case_c = 0.79998
 case_c:
   br label %exit
 
-; CHECK: case_d = 51
+; CHECK: case_d = 0.04998
 case_d:
   br label %exit
 
-; CHECK: case_e = 51
+; CHECK: case_e = 0.04998
 case_e:
   br label %exit
 
-; FIXME: It may be a bug that we don't sum back to 1024.
-; CHECK: exit = 1023
+; FIXME: It may be a bug that we don't sum back to 1.0.
+; CHECK: exit = 0.99993
 exit:
   %result = phi i32 [ %a, %case_a ],
                     [ %b, %case_b ],
@@ -90,3 +90,45 @@ exit:
 }
 
 !1 = metadata !{metadata !"branch_weights", i32 4, i32 4, i32 64, i32 4, i32 4}
+
+; CHECK: Printing analysis {{.*}} for function 'nested_loops'
+; CHECK: entry = 1.0
+; This test doesn't seem to be assigning sensible frequencies to nested loops.
+define void @nested_loops(i32 %a) {
+entry:
+  br label %for.cond1.preheader
+
+for.cond1.preheader:
+  %x.024 = phi i32 [ 0, %entry ], [ %inc12, %for.inc11 ]
+  br label %for.cond4.preheader
+
+for.cond4.preheader:
+  %y.023 = phi i32 [ 0, %for.cond1.preheader ], [ %inc9, %for.inc8 ]
+  %add = add i32 %y.023, %x.024
+  br label %for.body6
+
+for.body6:
+  %z.022 = phi i32 [ 0, %for.cond4.preheader ], [ %inc, %for.body6 ]
+  %add7 = add i32 %add, %z.022
+  tail call void @g(i32 %add7) #2
+  %inc = add i32 %z.022, 1
+  %cmp5 = icmp ugt i32 %inc, %a
+  br i1 %cmp5, label %for.inc8, label %for.body6, !prof !2
+
+for.inc8:
+  %inc9 = add i32 %y.023, 1
+  %cmp2 = icmp ugt i32 %inc9, %a
+  br i1 %cmp2, label %for.inc11, label %for.cond4.preheader, !prof !2
+
+for.inc11:
+  %inc12 = add i32 %x.024, 1
+  %cmp = icmp ugt i32 %inc12, %a
+  br i1 %cmp, label %for.end13, label %for.cond1.preheader, !prof !2
+
+for.end13:
+  ret void
+}
+
+declare void @g(i32) #1
+
+!2 = metadata !{metadata !"branch_weights", i32 1, i32 4000}
diff --git a/test/Analysis/CallGraph/no-intrinsics.ll b/test/Analysis/CallGraph/no-intrinsics.ll
index 450dce5..d858907 100644
--- a/test/Analysis/CallGraph/no-intrinsics.ll
+++ b/test/Analysis/CallGraph/no-intrinsics.ll
@@ -10,4 +10,4 @@ define void @f(i8* %out, i8* %in) {
 }
 
 ; CHECK: Call graph node for function: 'f'
-; CHECK-NOT: calls function 'llvm.memcpy.p0i8.p0i8.i32'
\ No newline at end of file
+; CHECK-NOT: calls function 'llvm.memcpy.p0i8.p0i8.i32'
diff --git a/test/Analysis/CostModel/ARM/select.ll b/test/Analysis/CostModel/ARM/select.ll
index 34ed1ee..21eef83 100644
--- a/test/Analysis/CostModel/ARM/select.ll
+++ b/test/Analysis/CostModel/ARM/select.ll
@@ -63,5 +63,13 @@ define void @casts() {
   ; CHECK: cost of 1 {{.*}} select
   %v19 = select <2 x i1>  undef, <2 x double> undef, <2 x double> undef
 
+  ; odd vectors get legalized and should have similar costs
+  ; CHECK: cost of 1 {{.*}} select
+  %v20 = select <1 x i1>  undef, <1 x i32> undef, <1 x i32> undef
+  ; CHECK: cost of 1 {{.*}} select
+  %v21 = select <3 x i1>  undef, <3 x float> undef, <3 x float> undef
+  ; CHECK: cost of 4 {{.*}} select
+  %v22 = select <5 x i1>  undef, <5 x double> undef, <5 x double> undef
+
   ret void
 }
diff --git a/test/Analysis/CostModel/X86/div.ll b/test/Analysis/CostModel/X86/div.ll
new file mode 100644
index 0000000..c7d6517
--- /dev/null
+++ b/test/Analysis/CostModel/X86/div.ll
@@ -0,0 +1,32 @@
+; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE2 %s
+; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -cost-model -analyze < %s | FileCheck --check-prefix=AVX2 %s
+
+
+define void @div_sse() {
+  ; SSE2: div_sse
+  ; SSE2: cost of 320 {{.*}} sdiv
+  %a0 = sdiv <16 x i8> undef, undef
+  ; SSE2: cost of 160 {{.*}} sdiv
+  %a1 = sdiv <8 x i16> undef, undef
+  ; SSE2: cost of 80 {{.*}} sdiv
+  %a2 = sdiv <4 x i32> undef, undef
+  ; SSE2: cost of 40 {{.*}} sdiv
+  %a3 = sdiv <2 x i32> undef, undef
+  ret void
+}
+; SSE2: div_avx
+
+define void @div_avx() {
+  ; AVX2: div_avx
+  ; AVX2: cost of 640 {{.*}} sdiv
+  %a0 = sdiv <32 x i8> undef, undef
+  ; AVX2: cost of 320 {{.*}} sdiv
+  %a1 = sdiv <16 x i16> undef, undef
+  ; AVX2: cost of 160 {{.*}} sdiv
+  %a2 = sdiv <8 x i32> undef, undef
+  ; AVX2: cost of 80 {{.*}} sdiv
+  %a3 = sdiv <4 x i32> undef, undef
+  ret void
+}
+
+
diff --git a/test/Analysis/CostModel/X86/intrinsic-cost.ll b/test/Analysis/CostModel/X86/intrinsic-cost.ll
index e235a36..8eeee81 100644
--- a/test/Analysis/CostModel/X86/intrinsic-cost.ll
+++ b/test/Analysis/CostModel/X86/intrinsic-cost.ll
@@ -30,3 +30,31 @@ for.end:                                          ; preds = %vector.body
 }
 
 declare <4 x float> @llvm.ceil.v4f32(<4 x float>)  nounwind readnone
+
+define void @test2(float* nocapture %f) nounwind {
+vector.ph:
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %vector.ph
+  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+  %0 = getelementptr inbounds float* %f, i64 %index
+  %1 = bitcast float* %0 to <4 x float>*
+  %wide.load = load <4 x float>* %1, align 4
+  %2 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %wide.load)
+  store <4 x float> %2, <4 x float>* %1, align 4
+  %index.next = add i64 %index, 4
+  %3 = icmp eq i64 %index.next, 1024
+  br i1 %3, label %for.end, label %vector.body
+
+for.end:                                          ; preds = %vector.body
+  ret void
+
+; CORE2: Printing analysis 'Cost Model Analysis' for function 'test2':
+; CORE2: Cost Model: Found an estimated cost of 400 for instruction:   %2 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %wide.load)
+
+; COREI7: Printing analysis 'Cost Model Analysis' for function 'test2':
+; COREI7: Cost Model: Found an estimated cost of 1 for instruction:   %2 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %wide.load)
+
+}
+
+declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>)  nounwind readnone
diff --git a/test/Analysis/CostModel/X86/load_store.ll b/test/Analysis/CostModel/X86/load_store.ll
index 4195b1d..a53d0bd 100644
--- a/test/Analysis/CostModel/X86/load_store.ll
+++ b/test/Analysis/CostModel/X86/load_store.ll
@@ -59,6 +59,25 @@ define i32 @loads(i32 %arg) {
   ;CHECK: cost of 4 {{.*}} load
   load <8 x i64>* undef, align 4
 
+
+  ;CHECK: cost of 3 {{.*}} load
+  load <3 x float>* undef, align 4
+
+  ;CHECK: cost of 3 {{.*}} load
+  load <3 x double>* undef, align 4
+
+  ;CHECK: cost of 3 {{.*}} load
+  load <3 x i32>* undef, align 4
+
+  ;CHECK: cost of 3 {{.*}} load
+  load <3 x i64>* undef, align 4
+
+  ;CHECK: cost of 10 {{.*}} load
+  load <5 x i32>* undef, align 4
+
+  ;CHECK: cost of 10 {{.*}} load
+  load <5 x i64>* undef, align 4
+
   ret i32 undef
 }
 
diff --git a/test/Analysis/DependenceAnalysis/Invariant.ll b/test/Analysis/DependenceAnalysis/Invariant.ll
new file mode 100644
index 0000000..202d8e2
--- /dev/null
+++ b/test/Analysis/DependenceAnalysis/Invariant.ll
@@ -0,0 +1,40 @@
+; RUN: opt < %s -analyze -basicaa -da | FileCheck %s
+
+; Test for a bug, which caused an assert when an invalid
+; SCEVAddRecExpr is created in addToCoefficient.
+
+; CHECK: da analyze - consistent input [S 0]!
+; CHECK: da analyze - input [* 0|<]!
+; CHECK: da analyze - none!
+
+define float @foo(float %g, [40 x float]* %rr) nounwind {
+entry:
+  br label %for.cond1.preheader
+
+for.cond1.preheader:
+  %i.04 = phi i32 [ 0, %entry ], [ %add10, %for.inc9 ]
+  %res.03 = phi float [ 0.000000e+00, %entry ], [ %add.res.1, %for.inc9 ]
+  br label %for.body3
+
+for.body3:
+  %j.02 = phi i32 [ 0, %for.cond1.preheader ], [ %add8, %for.body3 ]
+  %res.11 = phi float [ %res.03, %for.cond1.preheader ], [ %add.res.1, %for.body3 ]
+  %arrayidx4 = getelementptr inbounds [40 x float]* %rr, i32 %j.02, i32 %j.02
+  %0 = load float* %arrayidx4, align 4
+  %arrayidx6 = getelementptr inbounds [40 x float]* %rr, i32 %i.04, i32 %j.02
+  %1 = load float* %arrayidx6, align 4
+  %add = fadd float %0, %1
+  %cmp7 = fcmp ogt float %add, %g
+  %add.res.1 = select i1 %cmp7, float %add, float %res.11
+  %add8 = add nsw i32 %j.02, 5
+  %cmp2 = icmp slt i32 %add8, 40
+  br i1 %cmp2, label %for.body3, label %for.inc9
+
+for.inc9:
+  %add10 = add nsw i32 %i.04, 5
+  %cmp = icmp slt i32 %add10, 40
+  br i1 %cmp, label %for.cond1.preheader, label %for.end11
+
+for.end11:
+  ret float %add.res.1
+}
diff --git a/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll b/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll
index e0c5583..b5eb9fc 100644
--- a/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll
+++ b/test/Analysis/ScalarEvolution/2007-07-15-NegativeStride.ll
@@ -1,9 +1,10 @@
-; RUN: opt < %s -analyze -scalar-evolution \
-; RUN:   -scalar-evolution-max-iterations=0 | grep "Loop %bb: backedge-taken count is 100"
+; RUN: opt < %s -analyze -scalar-evolution -scalar-evolution-max-iterations=0 | FileCheck %s
 ; PR1533
 
 @array = weak global [101 x i32] zeroinitializer, align 32		; <[100 x i32]*> [#uses=1]
 
+; CHECK: Loop %bb: backedge-taken count is 100
+
 define void @loop(i32 %x) {
 entry:
 	br label %bb
diff --git a/test/Analysis/ScalarEvolution/2011-04-26-FoldAddRec.ll b/test/Analysis/ScalarEvolution/2011-04-26-FoldAddRec.ll
index 1600d5f..973dd7d 100644
--- a/test/Analysis/ScalarEvolution/2011-04-26-FoldAddRec.ll
+++ b/test/Analysis/ScalarEvolution/2011-04-26-FoldAddRec.ll
@@ -30,4 +30,4 @@ for.inc9:
 if.then:
   ret i8 0
 
-}
\ No newline at end of file
+}
diff --git a/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll b/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
index e946d7a..2cb8c5b 100644
--- a/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
+++ b/test/Analysis/ScalarEvolution/SolveQuadraticEquation.ll
@@ -1,5 +1,4 @@
-; RUN: opt < %s -analyze -scalar-evolution \
-; RUN:   -scalar-evolution-max-iterations=0 | FileCheck %s
+; RUN: opt < %s -analyze -scalar-evolution -scalar-evolution-max-iterations=0 | FileCheck %s
 
 ; PR1101
 
diff --git a/test/Analysis/ScalarEvolution/smax.ll b/test/Analysis/ScalarEvolution/smax.ll
index eceb429..122e9e4 100644
--- a/test/Analysis/ScalarEvolution/smax.ll
+++ b/test/Analysis/ScalarEvolution/smax.ll
@@ -1,8 +1,10 @@
-; RUN: opt < %s -analyze -scalar-evolution | grep smax | count 2
-; RUN: opt < %s -analyze -scalar-evolution | grep \
-; RUN:     "%. smax %. smax %."
+; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s
 ; PR1614
 
+; CHECK: -->  (%a smax %b)
+; CHECK: -->  (%a smax %b smax %c)
+; CHECK-NOT: smax
+
 define i32 @x(i32 %a, i32 %b, i32 %c) {
   %A = icmp sgt i32 %a, %b
   %B = select i1 %A, i32 %a, i32 %b
diff --git a/test/Analysis/ScalarEvolution/trip-count.ll b/test/Analysis/ScalarEvolution/trip-count.ll
index 94f6882..f89125a 100644
--- a/test/Analysis/ScalarEvolution/trip-count.ll
+++ b/test/Analysis/ScalarEvolution/trip-count.ll
@@ -1,9 +1,9 @@
-; RUN: opt < %s -analyze -scalar-evolution \
-; RUN:   -scalar-evolution-max-iterations=0 | grep "backedge-taken count is 10000"
+; RUN: opt < %s -analyze -scalar-evolution -scalar-evolution-max-iterations=0 | FileCheck %s
 ; PR1101
 
 @A = weak global [1000 x i32] zeroinitializer, align 32         
 
+; CHECK: backedge-taken count is 10000
 
 define void @test(i32 %N) {
 entry:
diff --git a/test/Analysis/ScalarEvolution/trip-count2.ll b/test/Analysis/ScalarEvolution/trip-count2.ll
index d84e99f..e76488a 100644
--- a/test/Analysis/ScalarEvolution/trip-count2.ll
+++ b/test/Analysis/ScalarEvolution/trip-count2.ll
@@ -1,9 +1,9 @@
-; RUN: opt < %s -analyze -scalar-evolution | \
-; RUN:   grep "backedge-taken count is 4"
+; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s
 ; PR1101
 
 @A = weak global [1000 x i32] zeroinitializer, align 32         
 
+; CHECK: backedge-taken count is 4
 
 define void @test(i32 %N) {
 entry:
diff --git a/test/Analysis/ScalarEvolution/trip-count3.ll b/test/Analysis/ScalarEvolution/trip-count3.ll
index 0cb6c95..32c51bf 100644
--- a/test/Analysis/ScalarEvolution/trip-count3.ll
+++ b/test/Analysis/ScalarEvolution/trip-count3.ll
@@ -1,10 +1,11 @@
-; RUN: opt < %s -scalar-evolution -analyze \
-; RUN:  | grep "Loop %bb3\.i: Unpredictable backedge-taken count\."
+; RUN: opt < %s -scalar-evolution -analyze | FileCheck %s
 
 ; ScalarEvolution can't compute a trip count because it doesn't know if
 ; dividing by the stride will have a remainder. This could theoretically
 ; be teaching it how to use a more elaborate trip count computation.
 
+; CHECK: Loop %bb3.i: Unpredictable backedge-taken count.
+
 %struct.FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct.FILE*, i32, i32, i64, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i64, i32, [20 x i8] }
 %struct.SHA_INFO = type { [5 x i32], i32, i32, [16 x i32] }
 %struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 }
diff --git a/test/Analysis/ScalarEvolution/trip-count4.ll b/test/Analysis/ScalarEvolution/trip-count4.ll
index c02ae14..b7184a4 100644
--- a/test/Analysis/ScalarEvolution/trip-count4.ll
+++ b/test/Analysis/ScalarEvolution/trip-count4.ll
@@ -1,8 +1,9 @@
-; RUN: opt < %s -analyze -scalar-evolution \
-; RUN:   | grep "sext.*trunc.*Exits: 11"
+; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s
 
 ; ScalarEvolution should be able to compute a loop exit value for %indvar.i8.
 
+; CHECK: sext{{.*}}trunc{{.*}}Exits: 11
+
 define void @another_count_down_signed(double* %d, i64 %n) nounwind {
 entry:
 	br label %loop
diff --git a/test/Analysis/ScalarEvolution/trip-count6.ll b/test/Analysis/ScalarEvolution/trip-count6.ll
index 882f552..0f394a0 100644
--- a/test/Analysis/ScalarEvolution/trip-count6.ll
+++ b/test/Analysis/ScalarEvolution/trip-count6.ll
@@ -1,8 +1,9 @@
-; RUN: opt < %s -analyze -scalar-evolution \
-; RUN:  | grep "max backedge-taken count is 1$"
+; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s
 
 @mode_table = global [4 x i32] zeroinitializer          ; <[4 x i32]*> [#uses=1]
 
+; CHECK: max backedge-taken count is 1{{$}}
+
 define i8 @f() {
 entry:
   tail call i32 @fegetround( )          ; <i32>:0 [#uses=1]
diff --git a/test/Analysis/ScalarEvolution/trip-count7.ll b/test/Analysis/ScalarEvolution/trip-count7.ll
index 2bcb9e9..d01a18a 100644
--- a/test/Analysis/ScalarEvolution/trip-count7.ll
+++ b/test/Analysis/ScalarEvolution/trip-count7.ll
@@ -1,8 +1,9 @@
-; RUN: opt < %s -analyze -scalar-evolution \
-; RUN:   | grep "Loop %bb7.i: Unpredictable backedge-taken count\."
+; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 
+; CHECK: Loop %bb7.i: Unpredictable backedge-taken count.
+
 	%struct.complex = type { float, float }
 	%struct.element = type { i32, i32 }
 	%struct.node = type { %struct.node*, %struct.node*, i32 }
diff --git a/test/Analysis/ScalarEvolution/trip-count8.ll b/test/Analysis/ScalarEvolution/trip-count8.ll
index 005162b..a1777bc 100644
--- a/test/Analysis/ScalarEvolution/trip-count8.ll
+++ b/test/Analysis/ScalarEvolution/trip-count8.ll
@@ -1,9 +1,10 @@
-; RUN: opt < %s -analyze -scalar-evolution \
-; RUN:  | grep "Loop %for\.body: backedge-taken count is (-1 + [%]ecx)"
+; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s
 ; PR4599
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 
+; CHECK: Loop %for.body: backedge-taken count is (-1 + {{%?}}ecx)
+
 define i32 @foo(i32 %ecx) nounwind {
 entry:
 	%cmp2 = icmp eq i32 %ecx, 0		; <i1> [#uses=1]
diff --git a/test/Analysis/ScalarEvolution/xor-and.ll b/test/Analysis/ScalarEvolution/xor-and.ll
index 4ab2f39..2616ea9 100644
--- a/test/Analysis/ScalarEvolution/xor-and.ll
+++ b/test/Analysis/ScalarEvolution/xor-and.ll
@@ -1,9 +1,10 @@
-; RUN: opt < %s -scalar-evolution -analyze \
-; RUN:   | grep "\-->  (zext i4 (-8 + (trunc i64 (8 \* %x) to i4)) to i64)"
+; RUN: opt < %s -scalar-evolution -analyze | FileCheck %s
 
 ; ScalarEvolution shouldn't try to analyze %z into something like
 ;   -->  (zext i4 (-1 + (-1 * (trunc i64 (8 * %x) to i4))) to i64)
 
+; CHECK: -->  (zext i4 (-8 + (trunc i64 (8 * %x) to i4)) to i64)
+
 define i64 @foo(i64 %x) {
   %a = shl i64 %x, 3
   %t = and i64 %a, 8
diff --git a/test/Analysis/ScalarEvolution/zext-wrap.ll b/test/Analysis/ScalarEvolution/zext-wrap.ll
index 38d15ff..104ed41 100644
--- a/test/Analysis/ScalarEvolution/zext-wrap.ll
+++ b/test/Analysis/ScalarEvolution/zext-wrap.ll
@@ -1,5 +1,4 @@
-; RUN: opt < %s -analyze -scalar-evolution \
-; RUN:  | FileCheck %s
+; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s
 ; PR4569
 
 define i16 @main() nounwind {
diff --git a/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll b/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll
index 3b5211e..bb66e37 100644
--- a/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll
+++ b/test/Analysis/TypeBasedAliasAnalysis/argument-promotion.ll
@@ -1,7 +1,9 @@
-; RUN: opt < %s -tbaa -basicaa -argpromotion -mem2reg -S | not grep alloca
+; RUN: opt < %s -tbaa -basicaa -argpromotion -mem2reg -S | FileCheck %s
 
 target datalayout = "E-p:64:64:64"
 
+; CHECK: test
+; CHECK-NOT: alloca
 define internal i32 @test(i32* %X, i32* %Y, i32* %Q) {
   store i32 77, i32* %Q, !tbaa !2
   %A = load i32* %X, !tbaa !1
@@ -10,6 +12,8 @@ define internal i32 @test(i32* %X, i32* %Y, i32* %Q) {
   ret i32 %C
 }
 
+; CHECK: caller
+; CHECK-NOT: alloca
 define internal i32 @caller(i32* %B, i32* %Q) {
   %A = alloca i32
   store i32 78, i32* %Q, !tbaa !2
@@ -18,6 +22,8 @@ define internal i32 @caller(i32* %B, i32* %Q) {
   ret i32 %C
 }
 
+; CHECK: callercaller
+; CHECK-NOT: alloca
 define i32 @callercaller(i32* %Q) {
   %B = alloca i32
   store i32 2, i32* %B, !tbaa !1
diff --git a/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll b/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
index c6cc26a..0a30b30 100644
--- a/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
+++ b/test/Analysis/TypeBasedAliasAnalysis/functionattrs.ll
@@ -49,7 +49,7 @@ define void @test2_yes(i8* %p, i8* %q, i64 %n) nounwind {
   ret void
 }
 
-; CHECK: define void @test2_no(i8* nocapture %p, i8* nocapture %q, i64 %n) #1 {
+; CHECK: define void @test2_no(i8* nocapture %p, i8* nocapture readonly %q, i64 %n) #1 {
 define void @test2_no(i8* %p, i8* %q, i64 %n) nounwind {
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %p, i8* %q, i64 %n, i32 1, i1 false), !tbaa !2
   ret void
diff --git a/test/Archive/README.txt b/test/Archive/README.txt
deleted file mode 100644
index 6810bef..0000000
--- a/test/Archive/README.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-test/Regression/Archive
-=======================
-
-This directory contains various tests of llvm-ar and llvm-ranlib to ensure 
-compatibility reading other ar(1) formats. It also provides a basic
-functionality test for these tools.
-
-There are four archives accompanying these tests: 
-
-GNU.a    - constructed on Linux with GNU ar
-MacOSX.a - constructed on Mac OS X with its native BSD4.4 ar
-SVR4.a   - constructed on Solaris with /usr/ccs/bin/ar
-xpg4.a   - constructed on Solaris with /usr/xpg4/bin/ar
-
-Each type of test is run on each of these archive files.  These archives each 
-contain four members:
-
-oddlen - a member with an odd lengthed name and content
-evenlen - a member with an even lengthed name and content
-IsNAN.o - a Linux native binary
-very_long_bytecode_file_name.bc - LLVM bytecode file with really long name
-
-These files test different aspects of the archiver that should cause failures
-in llvm-ar if regressions are introduced.
diff --git a/test/Archive/extract.ll b/test/Archive/extract.ll
deleted file mode 100644
index 5c0f508..0000000
--- a/test/Archive/extract.ll
+++ /dev/null
@@ -1,16 +0,0 @@
-; This isn't really an assembly file, its just here to run the test.
-
-; This test just makes sure that llvm-ar can extract bytecode members
-; from various style archives.
-
-; RUN: llvm-ar p %p/GNU.a very_long_bytecode_file_name.bc | \
-; RUN:   cmp -s %p/very_long_bytecode_file_name.bc -
-
-; RUN: llvm-ar p %p/MacOSX.a very_long_bytecode_file_name.bc | \
-; RUN:   cmp -s %p/very_long_bytecode_file_name.bc -
-
-; RUN: llvm-ar p %p/SVR4.a very_long_bytecode_file_name.bc | \
-; RUN:   cmp -s %p/very_long_bytecode_file_name.bc -
-
-; RUN: llvm-ar p %p/xpg4.a very_long_bytecode_file_name.bc |\
-; RUN:   cmp -s %p/very_long_bytecode_file_name.bc -
diff --git a/test/Archive/toc_GNU.ll b/test/Archive/toc_GNU.ll
deleted file mode 100644
index 9ed7d8e..0000000
--- a/test/Archive/toc_GNU.ll
+++ /dev/null
@@ -1,8 +0,0 @@
-;This isn't really an assembly file, its just here to run the test.
-;This test just makes sure that llvm-ar can generate a table of contents for
-;GNU style archives
-;RUN: llvm-ar t %p/GNU.a | FileCheck %s
-;CHECK:      evenlen
-;CHECK-NEXT: oddlen
-;CHECK-NEXT: very_long_bytecode_file_name.bc
-;CHECK-NEXT: IsNAN.o
diff --git a/test/Archive/toc_MacOSX.ll b/test/Archive/toc_MacOSX.ll
deleted file mode 100644
index 6dbc9d2..0000000
--- a/test/Archive/toc_MacOSX.ll
+++ /dev/null
@@ -1,9 +0,0 @@
-;This isn't really an assembly file, its just here to run the test.
-;This test just makes sure that llvm-ar can generate a table of contents for
-;MacOSX style archives
-;RUN: llvm-ar t %p/MacOSX.a | FileCheck %s
-;CHECK:      __.SYMDEF SORTED
-;CHECK-NEXT: evenlen
-;CHECK-NEXT: oddlen
-;CHECK-NEXT: very_long_bytecode_file_name.bc
-;CHECK-NEXT: IsNAN.o
diff --git a/test/Archive/toc_SVR4.ll b/test/Archive/toc_SVR4.ll
deleted file mode 100644
index d447b92..0000000
--- a/test/Archive/toc_SVR4.ll
+++ /dev/null
@@ -1,8 +0,0 @@
-;This isn't really an assembly file, its just here to run the test.
-;This test just makes sure that llvm-ar can generate a table of contents for
-;SVR4 style archives
-;RUN: llvm-ar t %p/SVR4.a | FileCheck %s
-;CHECK:      evenlen
-;CHECK-NEXT: oddlen
-;CHECK-NEXT: very_long_bytecode_file_name.bc
-;CHECK-NEXT: IsNAN.o
diff --git a/test/Archive/toc_xpg4.ll b/test/Archive/toc_xpg4.ll
deleted file mode 100644
index fd875ee..0000000
--- a/test/Archive/toc_xpg4.ll
+++ /dev/null
@@ -1,8 +0,0 @@
-;This isn't really an assembly file, its just here to run the test.
-;This test just makes sure that llvm-ar can generate a table of contents for
-;xpg4 style archives
-;RUN: llvm-ar t %p/xpg4.a | FileCheck %s
-CHECK:      evenlen
-CHECK-NEXT: oddlen
-CHECK-NEXT: very_long_bytecode_file_name.bc
-CHECK-NEXT: IsNAN.o
diff --git a/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll b/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll
index df70149..a0d77fa 100644
--- a/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll
+++ b/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll
@@ -1,4 +1,4 @@
-; RUN: opt -std-compile-opts < %s | llvm-dis | not grep badref 
+; RUN: opt -std-compile-opts < %s | llvm-dis | not grep badref
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10.2"
@@ -23,10 +23,12 @@ define i32 @main() nounwind readonly {
 declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 
 !7 = metadata !{metadata !1}
-!6 = metadata !{i32 786449, i32 0, i32 12, metadata !"/d/j/debug-test.c", metadata !"/Volumes/Data/b", metadata !"clang version 3.0 (trunk 131941)", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !7, null, null} ; [ DW_TAG_compile_unit ]
+!6 = metadata !{i32 786449, metadata !8, i32 12, metadata !"clang version 3.0 (trunk 131941)", i1 true, metadata !"", i32 0, metadata !9, metadata !9, metadata !7, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !0 = metadata !{i32 786688, metadata !1, metadata !"c", metadata !2, i32 2, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!1 = metadata !{i32 786478, i32 0, metadata !2, metadata !"main", metadata !"main", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 ()* @main, null, null, null, i32 1} ; [ DW_TAG_subprogram ]
-!2 = metadata !{i32 786473, metadata !"/d/j/debug-test.c", metadata !"/Volumes/Data/b", metadata !0} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!1 = metadata !{i32 786478, metadata !8, metadata !2, metadata !"main", metadata !"main", metadata !"", i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 ()* @main, null, null, null, i32 1} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 786473, metadata !8} ; [ DW_TAG_file_type ]
+!3 = metadata !{i32 786453, metadata !8, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !6, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 786468, null, metadata !6, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!8 = metadata !{metadata !"/d/j/debug-test.c", metadata !"/Volumes/Data/b"}
+!9 = metadata !{i32 0}
diff --git a/test/Assembler/attribute-builtin.ll b/test/Assembler/attribute-builtin.ll
new file mode 100644
index 0000000..a7799f0
--- /dev/null
+++ b/test/Assembler/attribute-builtin.ll
@@ -0,0 +1,52 @@
+
+; Make sure that llvm-as/llvm-dis properly assembly/disassembly the 'builtin'
+; attribute.
+;
+; rdar://13727199
+
+; RUN: llvm-as -disable-verify < %s | \
+; RUN: llvm-dis | \
+; RUN: llvm-as -disable-verify | \
+; RUN: llvm-dis | \
+; RUN: FileCheck -check-prefix=ASSEMBLES %s
+
+; CHECK-ASSEMBLES: declare i8* @foo(i8*) [[NOBUILTIN:#[0-9]+]]
+; CHECK-ASSEMBLES: call i8* @foo(i8* %x) [[BUILTIN:#[0-9]+]]
+; CHECK-ASSEMBLES: attributes [[NOBUILTIN]] = { nobuiltin }
+; CHECK-ASSEMBLES: attributes [[BUILTIN]] = { builtin }
+
+declare i8* @foo(i8*) #1
+define i8* @bar(i8* %x) {
+  %y = call i8* @foo(i8* %x) #0
+  ret i8* %y
+}
+
+; Make sure that we do not accept the 'builtin' attribute on function
+; definitions, function declarations, and on call sites that call functions
+; which do not have nobuiltin on them.
+; rdar://13727199
+
+; RUN: not llvm-as <%s 2>&1  | FileCheck -check-prefix=BAD %s
+
+; CHECK-BAD: Attribute 'builtin' can only be used in a call to a function with the 'nobuiltin' attribute.
+; CHECK-BAD-NEXT: %y = call i8* @lar(i8* %x) #1
+; CHECK-BAD: Attribute 'builtin' can only be applied to a callsite.
+; CHECK-BAD-NEXT: i8* (i8*)* @car
+; CHECK-BAD: Attribute 'builtin' can only be applied to a callsite.
+; CHECK-BAD-NEXT: i8* (i8*)* @mar
+
+declare i8* @lar(i8*)
+
+define i8* @har(i8* %x) {
+  %y = call i8* @lar(i8* %x) #0
+  ret i8* %y
+}
+
+define i8* @car(i8* %x) #0 {
+  ret i8* %x
+}
+
+declare i8* @mar(i8*) #0
+
+attributes #0 = { builtin }
+attributes #1 = { nobuiltin }
diff --git a/test/Assembler/functionlocal-metadata.ll b/test/Assembler/functionlocal-metadata.ll
index 216587d..0f0ab4c 100644
--- a/test/Assembler/functionlocal-metadata.ll
+++ b/test/Assembler/functionlocal-metadata.ll
@@ -2,8 +2,8 @@
 
 define void @Foo(i32 %a, i32 %b) {
 entry:
-  call void @llvm.dbg.value(metadata !{ i32* %1 }, i64 16, metadata !"bar")
-; CHECK: call void @llvm.dbg.value(metadata !{i32* %1}, i64 16, metadata !"bar")
+  call void @llvm.dbg.value(metadata !{ i32* %1 }, i64 16, metadata !2)
+; CHECK: call void @llvm.dbg.value(metadata !{i32* %1}, i64 16, metadata !2)
   %0 = add i32 %a, 1                              ; <i32> [#uses=1]
   %two = add i32 %b, %0                           ; <i32> [#uses=0]
   %1 = alloca i32                                 ; <i32*> [#uses=1]
@@ -25,10 +25,10 @@ entry:
 ; CHECK: metadata !{i32 %a}, i64 0, metadata !1
   call void @llvm.dbg.value(metadata !{ i32 %0 }, i64 25, metadata !0)
 ; CHECK: metadata !{i32 %0}, i64 25, metadata !0
-  call void @llvm.dbg.value(metadata !{ i32* %1 }, i64 16, metadata !"foo")
-; CHECK: call void @llvm.dbg.value(metadata !{i32* %1}, i64 16, metadata !"foo")
-  call void @llvm.dbg.value(metadata !"foo", i64 12, metadata !"bar")
-; CHECK: metadata !"foo", i64 12, metadata !"bar"
+  call void @llvm.dbg.value(metadata !{ i32* %1 }, i64 16, metadata !3)
+; CHECK: call void @llvm.dbg.value(metadata !{i32* %1}, i64 16, metadata !3)
+  call void @llvm.dbg.value(metadata !3, i64 12, metadata !2)
+; CHECK: metadata !3, i64 12, metadata !2
 
   ret void, !foo !0, !bar !1
 ; CHECK: ret void, !foo !0, !bar !1
@@ -36,6 +36,8 @@ entry:
 
 !0 = metadata !{i32 662302, i32 26, metadata !1, null}
 !1 = metadata !{i32 4, metadata !"foo"}
+!2 = metadata !{metadata !"bar"}
+!3 = metadata !{metadata !"foo"}
 
 declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
diff --git a/test/Bindings/Ocaml/vmcore.ml b/test/Bindings/Ocaml/vmcore.ml
index b49bab9..ccde1f0 100644
--- a/test/Bindings/Ocaml/vmcore.ml
+++ b/test/Bindings/Ocaml/vmcore.ml
@@ -1,6 +1,9 @@
 (* RUN: %ocamlopt -warn-error A llvm.cmxa llvm_analysis.cmxa llvm_bitwriter.cmxa %s -o %t
  * RUN: %t %t.bc
  * RUN: llvm-dis < %t.bc > %t.ll
+ * RUN: FileCheck %s < %t.ll
+ * Do a second pass for things that shouldn't be anywhere.
+ * RUN: FileCheck -check-prefix=CHECK-NOWHERE %s < %t.ll
  * XFAIL: vg_leak
  *)
 
@@ -65,26 +68,25 @@ let m = create_module context filename
 
 let test_target () =
   begin group "triple";
-    (* RUN: grep "i686-apple-darwin8" < %t.ll
-     *)
     let trip = "i686-apple-darwin8" in
     set_target_triple trip m;
     insist (trip = target_triple m)
   end;
   
   begin group "layout";
-    (* RUN: grep "bogus" < %t.ll
-     *)
     let layout = "bogus" in
     set_data_layout layout m;
     insist (layout = data_layout m)
   end
+  (* CHECK: target datalayout = "bogus"
+   * CHECK: target triple = "i686-apple-darwin8"
+   *)
 
 
 (*===-- Constants ---------------------------------------------------------===*)
 
 let test_constants () =
-  (* RUN: grep "const_int.*i32.*-1" < %t.ll
+  (* CHECK: const_int{{.*}}i32{{.*}}-1
    *)
   group "int";
   let c = const_int i32_type (-1) in
@@ -92,44 +94,44 @@ let test_constants () =
   insist (i32_type = type_of c);
   insist (is_constant c);
 
-  (* RUN: grep "const_sext_int.*i64.*-1" < %t.ll
+  (* CHECK: const_sext_int{{.*}}i64{{.*}}-1
    *)
   group "sext int";
   let c = const_int i64_type (-1) in
   ignore (define_global "const_sext_int" c m);
   insist (i64_type = type_of c);
 
-  (* RUN: grep "const_zext_int64.*i64.*4294967295" < %t.ll
+  (* CHECK: const_zext_int64{{.*}}i64{{.*}}4294967295
    *)
   group "zext int64";
   let c = const_of_int64 i64_type (Int64.of_string "4294967295") false in
   ignore (define_global "const_zext_int64" c m);
   insist (i64_type = type_of c);
 
-  (* RUN: grep "const_int_string.*i32.*-1" < %t.ll
+  (* CHECK: const_int_string{{.*}}i32{{.*}}-1
    *)
   group "int string";
   let c = const_int_of_string i32_type "-1" 10 in
   ignore (define_global "const_int_string" c m);
   insist (i32_type = type_of c);
 
-  (* RUN: grep 'const_string.*"cruel\\00world"' < %t.ll
+  (* CHECK: @const_string = global {{.*}}c"cruel\00world"
    *)
   group "string";
   let c = const_string context "cruel\000world" in
   ignore (define_global "const_string" c m);
   insist ((array_type i8_type 11) = type_of c);
 
-  (* RUN: grep 'const_stringz.*"hi\\00again\\00"' < %t.ll
+  (* CHECK: const_stringz{{.*}}"hi\00again\00"
    *)
   group "stringz";
   let c = const_stringz context "hi\000again" in
   ignore (define_global "const_stringz" c m);
   insist ((array_type i8_type 9) = type_of c);
 
-  (* RUN: grep "const_single.*2.75" < %t.ll
-   * RUN: grep "const_double.*3.1459" < %t.ll
-   * RUN: grep "const_double_string.*1.25" < %t.ll
+  (* CHECK: const_single{{.*}}2.75
+   * CHECK: const_double{{.*}}3.1459
+   * CHECK: const_double_string{{.*}}1.25
    *)
   begin group "real";
     let cs = const_float float_type 2.75 in
@@ -150,14 +152,14 @@ let test_constants () =
   let three = const_int i32_type 3 in
   let four = const_int i32_type 4 in
   
-  (* RUN: grep "const_array.*[i32 3, i32 4]" < %t.ll
+  (* CHECK: const_array{{.*}}[i32 3, i32 4]
    *)
   group "array";
   let c = const_array i32_type [| three; four |] in
   ignore (define_global "const_array" c m);
   insist ((array_type i32_type 2) = (type_of c));
   
-  (* RUN: grep "const_vector.*<i16 1, i16 2.*>" < %t.ll
+  (* CHECK: const_vector{{.*}}<i16 1, i16 2{{.*}}>
    *)
   group "vector";
   let c = const_vector [| one; two; one; two;
@@ -165,7 +167,7 @@ let test_constants () =
   ignore (define_global "const_vector" c m);
   insist ((vector_type i16_type 8) = (type_of c));
 
-  (* RUN: grep "const_structure.*.i16 1, i16 2, i32 3, i32 4" < %t.ll
+  (* CHECK: const_structure{{.*.}}i16 1, i16 2, i32 3, i32 4
    *)
   group "structure";
   let c = const_struct context [| one; two; three; four |] in
@@ -173,27 +175,27 @@ let test_constants () =
   insist ((struct_type context [| i16_type; i16_type; i32_type; i32_type |])
         = (type_of c));
 
-  (* RUN: grep "const_null.*zeroinit" < %t.ll
+  (* CHECK: const_null{{.*}}zeroinit
    *)
   group "null";
   let c = const_null (packed_struct_type context [| i1_type; i8_type; i64_type;
                                                     double_type |]) in
   ignore (define_global "const_null" c m);
   
-  (* RUN: grep "const_all_ones.*-1" < %t.ll
+  (* CHECK: const_all_ones{{.*}}-1
    *)
   group "all ones";
   let c = const_all_ones i64_type in
   ignore (define_global "const_all_ones" c m);
 
   group "pointer null"; begin
-    (* RUN: grep "const_pointer_null = global i64\* null" < %t.ll
+    (* CHECK: const_pointer_null = global i64* null
      *)
     let c = const_pointer_null (pointer_type i64_type) in
     ignore (define_global "const_pointer_null" c m);
   end;
   
-  (* RUN: grep "const_undef.*undef" < %t.ll
+  (* CHECK: const_undef{{.*}}undef
    *)
   group "undef";
   let c = undef i1_type in
@@ -202,35 +204,35 @@ let test_constants () =
   insist (is_undef c);
   
   group "constant arithmetic";
-  (* RUN: grep "@const_neg = global i64 sub" < %t.ll
-   * RUN: grep "@const_nsw_neg = global i64 sub nsw " < %t.ll
-   * RUN: grep "@const_nuw_neg = global i64 sub nuw " < %t.ll
-   * RUN: grep "@const_fneg = global double fsub " < %t.ll
-   * RUN: grep "@const_not = global i64 xor " < %t.ll
-   * RUN: grep "@const_add = global i64 add " < %t.ll
-   * RUN: grep "@const_nsw_add = global i64 add nsw " < %t.ll
-   * RUN: grep "@const_nuw_add = global i64 add nuw " < %t.ll
-   * RUN: grep "@const_fadd = global double fadd " < %t.ll
-   * RUN: grep "@const_sub = global i64 sub " < %t.ll
-   * RUN: grep "@const_nsw_sub = global i64 sub nsw " < %t.ll
-   * RUN: grep "@const_nuw_sub = global i64 sub nuw " < %t.ll
-   * RUN: grep "@const_fsub = global double fsub " < %t.ll
-   * RUN: grep "@const_mul = global i64 mul " < %t.ll
-   * RUN: grep "@const_nsw_mul = global i64 mul nsw " < %t.ll
-   * RUN: grep "@const_nuw_mul = global i64 mul nuw " < %t.ll
-   * RUN: grep "@const_fmul = global double fmul " < %t.ll
-   * RUN: grep "@const_udiv = global i64 udiv " < %t.ll
-   * RUN: grep "@const_sdiv = global i64 sdiv " < %t.ll
-   * RUN: grep "@const_exact_sdiv = global i64 sdiv exact " < %t.ll
-   * RUN: grep "@const_fdiv = global double fdiv " < %t.ll
-   * RUN: grep "@const_urem = global i64 urem " < %t.ll
-   * RUN: grep "@const_srem = global i64 srem " < %t.ll
-   * RUN: grep "@const_frem = global double frem " < %t.ll
-   * RUN: grep "@const_and = global i64 and " < %t.ll
-   * RUN: grep "@const_or = global i64 or " < %t.ll
-   * RUN: grep "@const_xor = global i64 xor " < %t.ll
-   * RUN: grep "@const_icmp = global i1 icmp sle " < %t.ll
-   * RUN: grep "@const_fcmp = global i1 fcmp ole " < %t.ll
+  (* CHECK: @const_neg = global i64 sub
+   * CHECK: @const_nsw_neg = global i64 sub nsw
+   * CHECK: @const_nuw_neg = global i64 sub nuw
+   * CHECK: @const_fneg = global double fsub
+   * CHECK: @const_not = global i64 xor
+   * CHECK: @const_add = global i64 add
+   * CHECK: @const_nsw_add = global i64 add nsw
+   * CHECK: @const_nuw_add = global i64 add nuw
+   * CHECK: @const_fadd = global double fadd
+   * CHECK: @const_sub = global i64 sub
+   * CHECK: @const_nsw_sub = global i64 sub nsw
+   * CHECK: @const_nuw_sub = global i64 sub nuw
+   * CHECK: @const_fsub = global double fsub
+   * CHECK: @const_mul = global i64 mul
+   * CHECK: @const_nsw_mul = global i64 mul nsw
+   * CHECK: @const_nuw_mul = global i64 mul nuw
+   * CHECK: @const_fmul = global double fmul
+   * CHECK: @const_udiv = global i64 udiv
+   * CHECK: @const_sdiv = global i64 sdiv
+   * CHECK: @const_exact_sdiv = global i64 sdiv exact
+   * CHECK: @const_fdiv = global double fdiv
+   * CHECK: @const_urem = global i64 urem
+   * CHECK: @const_srem = global i64 srem
+   * CHECK: @const_frem = global double frem
+   * CHECK: @const_and = global i64 and
+   * CHECK: @const_or = global i64 or
+   * CHECK: @const_xor = global i64 xor
+   * CHECK: @const_icmp = global i1 icmp sle
+   * CHECK: @const_fcmp = global i1 fcmp ole
    *)
   let void_ptr = pointer_type i8_type in
   let five = const_int i64_type 5 in
@@ -269,18 +271,18 @@ let test_constants () =
   ignore (define_global "const_fcmp" (const_fcmp Fcmp.Ole ffoldbomb ffive) m);
   
   group "constant casts";
-  (* RUN: grep "const_trunc.*trunc" < %t.ll
-   * RUN: grep "const_sext.*sext" < %t.ll
-   * RUN: grep "const_zext.*zext" < %t.ll
-   * RUN: grep "const_fptrunc.*fptrunc" < %t.ll
-   * RUN: grep "const_fpext.*fpext" < %t.ll
-   * RUN: grep "const_uitofp.*uitofp" < %t.ll
-   * RUN: grep "const_sitofp.*sitofp" < %t.ll
-   * RUN: grep "const_fptoui.*fptoui" < %t.ll
-   * RUN: grep "const_fptosi.*fptosi" < %t.ll
-   * RUN: grep "const_ptrtoint.*ptrtoint" < %t.ll
-   * RUN: grep "const_inttoptr.*inttoptr" < %t.ll
-   * RUN: grep "const_bitcast.*bitcast" < %t.ll
+  (* CHECK: const_trunc{{.*}}trunc
+   * CHECK: const_sext{{.*}}sext
+   * CHECK: const_zext{{.*}}zext
+   * CHECK: const_fptrunc{{.*}}fptrunc
+   * CHECK: const_fpext{{.*}}fpext
+   * CHECK: const_uitofp{{.*}}uitofp
+   * CHECK: const_sitofp{{.*}}sitofp
+   * CHECK: const_fptoui{{.*}}fptoui
+   * CHECK: const_fptosi{{.*}}fptosi
+   * CHECK: const_ptrtoint{{.*}}ptrtoint
+   * CHECK: const_inttoptr{{.*}}inttoptr
+   * CHECK: const_bitcast{{.*}}bitcast
    *)
   let i128_type = integer_type context 128 in
   ignore (define_global "const_trunc" (const_trunc (const_add foldbomb five)
@@ -302,12 +304,12 @@ let test_constants () =
   ignore (define_global "const_bitcast" (const_bitcast ffoldbomb i64_type) m);
   
   group "misc constants";
-  (* RUN: grep "const_size_of.*getelementptr.*null" < %t.ll
-   * RUN: grep "const_gep.*getelementptr" < %t.ll
-   * RUN: grep "const_select.*select" < %t.ll
-   * RUN: grep "const_extractelement.*extractelement" < %t.ll
-   * RUN: grep "const_insertelement.*insertelement" < %t.ll
-   * RUN: grep "const_shufflevector = global <4 x i32> <i32 0, i32 1, i32 1, i32 0>" < %t.ll
+  (* CHECK: const_size_of{{.*}}getelementptr{{.*}}null
+   * CHECK: const_gep{{.*}}getelementptr
+   * CHECK: const_select{{.*}}select
+   * CHECK: const_extractelement{{.*}}extractelement
+   * CHECK: const_insertelement{{.*}}insertelement
+   * CHECK: const_shufflevector = global <4 x i32> <i32 0, i32 1, i32 1, i32 0>
    *)
   ignore (define_global "const_size_of" (size_of (pointer_type i8_type)) m);
   ignore (define_global "const_gep" (const_gep foldbomb_gv [| five |]) m);
@@ -356,7 +358,7 @@ let test_global_values () =
   let (++) x f = f x; x in
   let zero32 = const_null i32_type in
 
-  (* RUN: grep "GVal01" < %t.ll
+  (* CHECK: GVal01
    *)
   group "naming";
   let g = define_global "TEMPORARY" zero32 m in
@@ -364,28 +366,28 @@ let test_global_values () =
   set_value_name "GVal01" g;
   insist ("GVal01" = value_name g);
 
-  (* RUN: grep "GVal02.*linkonce" < %t.ll
+  (* CHECK: GVal02{{.*}}linkonce
    *)
   group "linkage";
   let g = define_global "GVal02" zero32 m ++
           set_linkage Linkage.Link_once in
   insist (Linkage.Link_once = linkage g);
 
-  (* RUN: grep "GVal03.*Hanalei" < %t.ll
+  (* CHECK: GVal03{{.*}}Hanalei
    *)
   group "section";
   let g = define_global "GVal03" zero32 m ++
           set_section "Hanalei" in
   insist ("Hanalei" = section g);
   
-  (* RUN: grep "GVal04.*hidden" < %t.ll
+  (* CHECK: GVal04{{.*}}hidden
    *)
   group "visibility";
   let g = define_global "GVal04" zero32 m ++
           set_visibility Visibility.Hidden in
   insist (Visibility.Hidden = visibility g);
   
-  (* RUN: grep "GVal05.*align 128" < %t.ll
+  (* CHECK: GVal05{{.*}}align 128
    *)
   group "alignment";
   let g = define_global "GVal05" zero32 m ++
@@ -400,7 +402,7 @@ let test_global_variables () =
   let fourty_two32 = const_int i32_type 42 in
 
   group "declarations"; begin
-    (* RUN: grep "GVar01.*external" < %t.ll
+    (* CHECK: GVar01{{.*}}external
      *)
     insist (None == lookup_global "GVar01" m);
     let g = declare_global i32_type "GVar01" m in
@@ -422,8 +424,8 @@ let test_global_variables () =
   end;
   
   group "definitions"; begin
-    (* RUN: grep "GVar02.*42" < %t.ll
-     * RUN: grep "GVar03.*42" < %t.ll
+    (* CHECK: GVar02{{.*}}42
+     * CHECK: GVar03{{.*}}42
      *)
     let g = define_global "GVar02" fourty_two32 m in
     let g2 = declare_global i32_type "GVar03" m ++
@@ -440,20 +442,20 @@ let test_global_variables () =
     insist ((global_initializer g) == (global_initializer g2));
   end;
 
-  (* RUN: grep "GVar04.*thread_local" < %t.ll
+  (* CHECK: GVar04{{.*}}thread_local
    *)
   group "threadlocal";
   let g = define_global "GVar04" fourty_two32 m ++
           set_thread_local true in
   insist (is_thread_local g);
 
-  (* RUN: grep -v "GVar05" < %t.ll
+  (* CHECK-NOWHERE-NOT: GVar05
    *)
   group "delete";
   let g = define_global "GVar05" fourty_two32 m in
   delete_global g;
 
-  (* RUN: grep -v "ConstGlobalVar.*constant" < %t.ll
+  (* CHECK: ConstGlobalVar{{.*}}constant
    *)
   group "constant";
   let g = define_global "ConstGlobalVar" fourty_two32 m in
@@ -487,6 +489,10 @@ let test_global_variables () =
     dispose_module m
   end
 
+(* String globals built below are emitted here.
+ * CHECK: build_global_string{{.*}}stringval
+ *)
+
 
 (*===-- Uses --------------------------------------------------------------===*)
 
@@ -542,7 +548,7 @@ let test_users () =
 (*===-- Aliases -----------------------------------------------------------===*)
 
 let test_aliases () =
-  (* RUN: grep "@alias = alias i32\* @aliasee" < %t.ll
+  (* CHECK: @alias = alias i32* @aliasee
    *)
   let v = declare_global i32_type "aliasee" m in
   ignore (add_alias m (pointer_type i32_type) v "alias")
@@ -554,7 +560,7 @@ let test_functions () =
   let ty = function_type i32_type [| i32_type; i64_type |] in
   let ty2 = function_type i8_type [| i8_type; i64_type |] in
   
-  (* RUN: grep 'declare i32 @Fn1(i32, i64)' < %t.ll
+  (* CHECK: declare i32 @Fn1(i32, i64)
    *)
   begin group "declare";
     insist (None = lookup_function "Fn1" m);
@@ -570,13 +576,13 @@ let test_functions () =
     insist (m == global_parent fn)
   end;
   
-  (* RUN: grep -v "Fn2" < %t.ll
+  (* CHECK-NOWHERE-NOT: Fn2
    *)
   group "delete";
   let fn = declare_function "Fn2" ty m in
   delete_function fn;
   
-  (* RUN: grep "define.*Fn3" < %t.ll
+  (* CHECK: define{{.*}}Fn3
    *)
   group "define";
   let fn = define_function "Fn3" ty m in
@@ -584,7 +590,7 @@ let test_functions () =
   insist (1 = Array.length (basic_blocks fn));
   ignore (build_unreachable (builder_at_end context (entry_block fn)));
   
-  (* RUN: grep "define.*Fn4.*Param1.*Param2" < %t.ll
+  (* CHECK: define{{.*}}Fn4{{.*}}Param1{{.*}}Param2
    *)
   group "params";
   let fn = define_function "Fn4" ty m in
@@ -598,7 +604,7 @@ let test_functions () =
   set_value_name "Param2" params.(1);
   ignore (build_unreachable (builder_at_end context (entry_block fn)));
   
-  (* RUN: grep "fastcc.*Fn5" < %t.ll
+  (* CHECK: fastcc{{.*}}Fn5
    *)
   group "callconv";
   let fn = define_function "Fn5" ty m in
@@ -608,7 +614,7 @@ let test_functions () =
   ignore (build_unreachable (builder_at_end context (entry_block fn)));
   
   begin group "gc";
-    (* RUN: grep "Fn6.*gc.*shadowstack" < %t.ll
+    (* CHECK: Fn6{{.*}}gc{{.*}}shadowstack
      *)
     let fn = define_function "Fn6" ty m in
     insist (None = gc fn);
@@ -694,7 +700,7 @@ let test_params () =
 let test_basic_blocks () =
   let ty = function_type void_type [| |] in
   
-  (* RUN: grep "Bb1" < %t.ll
+  (* CHECK: Bb1
    *)
   group "entry";
   let fn = declare_function "X" ty m in
@@ -702,7 +708,7 @@ let test_basic_blocks () =
   insist (bb = entry_block fn);
   ignore (build_unreachable (builder_at_end context bb));
   
-  (* RUN: grep -v Bb2 < %t.ll
+  (* CHECK-NOWHERE-NOT: Bb2
    *)
   group "delete";
   let fn = declare_function "X2" ty m in
@@ -717,7 +723,7 @@ let test_basic_blocks () =
   ignore (build_unreachable (builder_at_end context bba));
   ignore (build_unreachable (builder_at_end context bbb));
   
-  (* RUN: grep Bb3 < %t.ll
+  (* CHECK: Bb3
    *)
   group "name/value";
   let fn = define_function "X4" ty m in
@@ -825,7 +831,7 @@ let test_builder () =
   
   group "ret void";
   begin
-    (* RUN: grep "ret void" < %t.ll
+    (* CHECK: ret void
      *)
     let fty = function_type void_type [| |] in
     let fn = declare_function "X6" fty m in
@@ -835,7 +841,7 @@ let test_builder () =
 
   group "ret aggregate";
   begin
-      (* RUN: grep "ret { i8, i64 } { i8 4, i64 5 }" < %t.ll
+      (* CHECK: ret { i8, i64 } { i8 4, i64 5 }
        *)
       let sty = struct_type context [| i8_type; i64_type |] in
       let fty = function_type sty [| |] in
@@ -860,12 +866,192 @@ let test_builder () =
   group "function attribute";
   begin
       ignore (add_function_attr fn Attribute.UWTable);
-      (* RUN: grep "X7.*#0" < %t.ll
-       * RUN: grep "attributes #0 = .*uwtable.*" < %t.ll
+      (* CHECK: X7{{.*}}#0
+       * #0 is uwtable, defined at EOF.
        *)
       insist ([Attribute.UWTable] = function_attr fn);
   end;
 
+  group "casts"; begin
+    let void_ptr = pointer_type i8_type in
+
+    (* CHECK-DAG: %build_trunc = trunc i32 %P1 to i8
+     * CHECK-DAG: %build_trunc2 = trunc i32 %P1 to i8
+     * CHECK-DAG: %build_trunc3 = trunc i32 %P1 to i8
+     * CHECK-DAG: %build_zext = zext i8 %build_trunc to i32
+     * CHECK-DAG: %build_zext2 = zext i8 %build_trunc to i32
+     * CHECK-DAG: %build_sext = sext i32 %build_zext to i64
+     * CHECK-DAG: %build_sext2 = sext i32 %build_zext to i64
+     * CHECK-DAG: %build_sext3 = sext i32 %build_zext to i64
+     * CHECK-DAG: %build_uitofp = uitofp i64 %build_sext to float
+     * CHECK-DAG: %build_sitofp = sitofp i32 %build_zext to double
+     * CHECK-DAG: %build_fptoui = fptoui float %build_uitofp to i32
+     * CHECK-DAG: %build_fptosi = fptosi double %build_sitofp to i64
+     * CHECK-DAG: %build_fptrunc = fptrunc double %build_sitofp to float
+     * CHECK-DAG: %build_fptrunc2 = fptrunc double %build_sitofp to float
+     * CHECK-DAG: %build_fpext = fpext float %build_fptrunc to double
+     * CHECK-DAG: %build_fpext2 = fpext float %build_fptrunc to double
+     * CHECK-DAG: %build_inttoptr = inttoptr i32 %P1 to i8*
+     * CHECK-DAG: %build_ptrtoint = ptrtoint i8* %build_inttoptr to i64
+     * CHECK-DAG: %build_ptrtoint2 = ptrtoint i8* %build_inttoptr to i64
+     * CHECK-DAG: %build_bitcast = bitcast i64 %build_ptrtoint to double
+     * CHECK-DAG: %build_bitcast2 = bitcast i64 %build_ptrtoint to double
+     * CHECK-DAG: %build_bitcast3 = bitcast i64 %build_ptrtoint to double
+     * CHECK-DAG: %build_bitcast4 = bitcast i64 %build_ptrtoint to double
+     * CHECK-DAG: %build_pointercast = bitcast i8* %build_inttoptr to i16*
+     *)
+    let inst28 = build_trunc p1 i8_type "build_trunc" atentry in
+    let inst29 = build_zext inst28 i32_type "build_zext" atentry in
+    let inst30 = build_sext inst29 i64_type "build_sext" atentry in
+    let inst31 = build_uitofp inst30 float_type "build_uitofp" atentry in
+    let inst32 = build_sitofp inst29 double_type "build_sitofp" atentry in
+    ignore(build_fptoui inst31 i32_type "build_fptoui" atentry);
+    ignore(build_fptosi inst32 i64_type "build_fptosi" atentry);
+    let inst35 = build_fptrunc inst32 float_type "build_fptrunc" atentry in
+    ignore(build_fpext inst35 double_type "build_fpext" atentry);
+    let inst37 = build_inttoptr p1 void_ptr "build_inttoptr" atentry in
+    let inst38 = build_ptrtoint inst37 i64_type "build_ptrtoint" atentry in
+    ignore(build_bitcast inst38 double_type "build_bitcast" atentry);
+    ignore(build_zext_or_bitcast inst38 double_type "build_bitcast2" atentry);
+    ignore(build_sext_or_bitcast inst38 double_type "build_bitcast3" atentry);
+    ignore(build_trunc_or_bitcast inst38 double_type "build_bitcast4" atentry);
+    ignore(build_pointercast inst37 (pointer_type i16_type) "build_pointercast" atentry);
+
+    ignore(build_zext_or_bitcast inst28 i32_type "build_zext2" atentry);
+    ignore(build_sext_or_bitcast inst29 i64_type "build_sext2" atentry);
+    ignore(build_trunc_or_bitcast p1 i8_type "build_trunc2" atentry);
+    ignore(build_pointercast inst37 i64_type "build_ptrtoint2" atentry);
+    ignore(build_intcast inst29 i64_type "build_sext3" atentry);
+    ignore(build_intcast p1 i8_type "build_trunc3" atentry);
+    ignore(build_fpcast inst35 double_type "build_fpext2" atentry);
+    ignore(build_fpcast inst32 float_type "build_fptrunc2" atentry);
+  end;
+
+  group "comparisons"; begin
+    (* CHECK: %build_icmp_ne = icmp ne i32 %P1, %P2
+     * CHECK: %build_icmp_sle = icmp sle i32 %P2, %P1
+     * CHECK: %build_fcmp_false = fcmp false float %F1, %F2
+     * CHECK: %build_fcmp_true = fcmp true float %F2, %F1
+     * CHECK: %build_is_null{{.*}}= icmp eq{{.*}}%X0,{{.*}}null
+     * CHECK: %build_is_not_null = icmp ne i8* %X1, null
+     * CHECK: %build_ptrdiff
+     *)
+    ignore (build_icmp Icmp.Ne    p1 p2 "build_icmp_ne" atentry);
+    ignore (build_icmp Icmp.Sle   p2 p1 "build_icmp_sle" atentry);
+    ignore (build_fcmp Fcmp.False f1 f2 "build_fcmp_false" atentry);
+    ignore (build_fcmp Fcmp.True  f2 f1 "build_fcmp_true" atentry);
+    let g0 = declare_global (pointer_type i8_type) "g0" m in
+    let g1 = declare_global (pointer_type i8_type) "g1" m in
+    let p0 = build_load g0 "X0" atentry in
+    let p1 = build_load g1 "X1" atentry in
+    ignore (build_is_null p0 "build_is_null" atentry);
+    ignore (build_is_not_null p1 "build_is_not_null" atentry);
+    ignore (build_ptrdiff p1 p0 "build_ptrdiff" atentry);
+  end;
+
+  group "miscellaneous"; begin
+    (* CHECK: %build_call = tail call cc63 i32 @{{.*}}(i32 signext %P2, i32 %P1)
+     * CHECK: %build_select = select i1 %build_icmp, i32 %P1, i32 %P2
+     * CHECK: %build_va_arg = va_arg i8** null, i32
+     * CHECK: %build_extractelement = extractelement <4 x i32> %Vec1, i32 %P2
+     * CHECK: %build_insertelement = insertelement <4 x i32> %Vec1, i32 %P1, i32 %P2
+     * CHECK: %build_shufflevector = shufflevector <4 x i32> %Vec1, <4 x i32> %Vec2, <4 x i32> <i32 1, i32 1, i32 0, i32 0>
+     * CHECK: %build_insertvalue0 = insertvalue{{.*}}%bl, i32 1, 0
+     * CHECK: %build_extractvalue = extractvalue{{.*}}%build_insertvalue1, 1
+     *)
+    let ci = build_call fn [| p2; p1 |] "build_call" atentry in
+    insist (CallConv.c = instruction_call_conv ci);
+    set_instruction_call_conv 63 ci;
+    insist (63 = instruction_call_conv ci);
+    insist (not (is_tail_call ci));
+    set_tail_call true ci;
+    insist (is_tail_call ci);
+    add_instruction_param_attr ci 1 Attribute.Sext;
+    add_instruction_param_attr ci 2 Attribute.Noalias;
+    remove_instruction_param_attr ci 2 Attribute.Noalias;
+
+    let inst46 = build_icmp Icmp.Eq p1 p2 "build_icmp" atentry in
+    ignore (build_select inst46 p1 p2 "build_select" atentry);
+    ignore (build_va_arg
+      (const_null (pointer_type (pointer_type i8_type)))
+      i32_type "build_va_arg" atentry);
+
+    (* Set up some vector vregs. *)
+    let one  = const_int i32_type 1 in
+    let zero = const_int i32_type 0 in
+    let t1 = const_vector [| one; zero; one; zero |] in
+    let t2 = const_vector [| zero; one; zero; one |] in
+    let t3 = const_vector [| one; one; zero; zero |] in
+    let vec1 = build_insertelement t1 p1 p2 "Vec1" atentry in
+    let vec2 = build_insertelement t2 p1 p2 "Vec2" atentry in
+    let sty = struct_type context [| i32_type; i8_type |] in
+
+    ignore (build_extractelement vec1 p2 "build_extractelement" atentry);
+    ignore (build_insertelement vec1 p1 p2 "build_insertelement" atentry);
+    ignore (build_shufflevector vec1 vec2 t3 "build_shufflevector" atentry);
+
+    let p = build_alloca sty "ba" atentry in
+    let agg = build_load p "bl" atentry in
+    let agg0 = build_insertvalue agg (const_int i32_type 1) 0
+                 "build_insertvalue0" atentry in
+    let agg1 = build_insertvalue agg0 (const_int i8_type 2) 1
+                 "build_insertvalue1" atentry in
+    ignore (build_extractvalue agg1 1 "build_extractvalue" atentry)
+  end;
+
+  group "metadata"; begin
+    (* CHECK: %metadata = add i32 %P1, %P2, !test !0
+     * !0 is metadata emitted at EOF.
+     *)
+    let i = build_add p1 p2 "metadata" atentry in
+    insist ((has_metadata i) = false);
+
+    let m1 = const_int i32_type 1 in
+    let m2 = mdstring context "metadata test" in
+    let md = mdnode context [| m1; m2 |] in
+
+    let kind = mdkind_id context "test" in
+    set_metadata i kind md;
+
+    insist ((has_metadata i) = true);
+    insist ((metadata i kind) = Some md);
+
+    clear_metadata i kind;
+
+    insist ((has_metadata i) = false);
+    insist ((metadata i kind) = None);
+
+    set_metadata i kind md
+  end;
+
+  group "dbg"; begin
+    (* CHECK: %dbg = add i32 %P1, %P2, !dbg !1
+     * !1 is metadata emitted at EOF.
+     *)
+    insist ((current_debug_location atentry) = None);
+
+    let m_line = const_int i32_type 2 in
+    let m_col = const_int i32_type 3 in
+    let m_scope = mdnode context [| |] in
+    let m_inlined = mdnode context [| |] in
+    let md = mdnode context [| m_line; m_col; m_scope; m_inlined |] in
+    set_current_debug_location atentry md;
+
+    insist ((current_debug_location atentry) = Some md);
+
+    let i = build_add p1 p2 "dbg" atentry in
+    insist ((has_metadata i) = true);
+
+    clear_current_debug_location atentry
+  end;
+
+  group "ret"; begin
+    (* CHECK: ret{{.*}}P1
+     *)
+    let ret = build_ret p1 atentry in
+    position_before ret atentry
+  end;
+
   (* see test/Feature/exception.ll *)
   let bblpad = append_block context "Bblpad" fn in
   let rt = struct_type context [| pointer_type i8_type; i32_type |] in
@@ -887,23 +1073,16 @@ let test_builder () =
            add_clause lp (const_array ety [| ztipkc; ztid |]);
            ignore (build_resume lp (builder_at_end context bblpad));
       end;
-      (* RUN: grep "landingpad.*personality.*__gxx_personality_v0" < %t.ll
-       * RUN: grep "cleanup" < %t.ll
-       * RUN: grep "catch.*i8\*\*.*@_ZTIc" < %t.ll
-       * RUN: grep "filter.*@_ZTIPKc.*@_ZTId" < %t.ll
-       * RUN: grep "resume " < %t.ll
+      (* CHECK: landingpad{{.*}}personality{{.*}}__gxx_personality_v0
+       * CHECK: cleanup
+       * CHECK: catch{{.*}}i8**{{.*}}@_ZTIc
+       * CHECK: filter{{.*}}@_ZTIPKc{{.*}}@_ZTId
+       * CHECK: resume
        * *)
   end;
 
-  group "ret"; begin
-    (* RUN: grep "ret.*P1" < %t.ll
-     *)
-    let ret = build_ret p1 atentry in
-    position_before ret atentry
-  end;
-  
   group "br"; begin
-    (* RUN: grep "br.*Bb02" < %t.ll
+    (* CHECK: br{{.*}}Bb02
      *)
     let bb02 = append_block context "Bb02" fn in
     let b = builder_at_end context bb02 in
@@ -911,7 +1090,7 @@ let test_builder () =
   end;
   
   group "cond_br"; begin
-    (* RUN: grep "br.*build_br.*Bb03.*Bb00" < %t.ll
+    (* CHECK: br{{.*}}build_br{{.*}}Bb03{{.*}}Bb00
      *)
     let bb03 = append_block context "Bb03" fn in
     let b = builder_at_end context bb03 in
@@ -920,8 +1099,8 @@ let test_builder () =
   end;
   
   group "switch"; begin
-    (* RUN: grep "switch.*P1.*SwiBlock3" < %t.ll
-     * RUN: grep "2,.*SwiBlock2" < %t.ll
+    (* CHECK: switch{{.*}}P1{{.*}}SwiBlock3
+     * CHECK: 2,{{.*}}SwiBlock2
      *)
     let bb1 = append_block context "SwiBlock1" fn in
     let bb2 = append_block context "SwiBlock2" fn in
@@ -935,9 +1114,9 @@ let test_builder () =
   end;
 
   group "malloc/free"; begin
-      (* RUN: grep "call.*@malloc(i32 ptrtoint" < %t.ll
-       * RUN: grep "call.*@free(i8\*" < %t.ll
-       * RUN: grep "call.*@malloc(i32 %" < %t.ll
+      (* CHECK: call{{.*}}@malloc(i32 ptrtoint
+       * CHECK: call{{.*}}@free(i8*
+       * CHECK: call{{.*}}@malloc(i32 %
        *)
       let bb1 = append_block context "MallocBlock1" fn in
       let m1 = (build_malloc (pointer_type i32_type) "m1"
@@ -948,7 +1127,7 @@ let test_builder () =
   end;
 
   group "indirectbr"; begin
-    (* RUN: grep "indirectbr i8\* blockaddress(@X7, %IBRBlock2), \[label %IBRBlock2, label %IBRBlock3\]" < %t.ll
+    (* CHECK: indirectbr i8* blockaddress(@X7, %IBRBlock2), [label %IBRBlock2, label %IBRBlock3]
      *)
     let bb1 = append_block context "IBRBlock1" fn in
 
@@ -965,8 +1144,8 @@ let test_builder () =
   end;
   
   group "invoke"; begin
-    (* RUN: grep "build_invoke.*invoke.*P1.*P2" < %t.ll
-     * RUN: grep "to.*Bb04.*unwind.*Bblpad" < %t.ll
+    (* CHECK: build_invoke{{.*}}invoke{{.*}}P1{{.*}}P2
+     * CHECK: to{{.*}}Bb04{{.*}}unwind{{.*}}Bblpad
      *)
     let bb04 = append_block context "Bb04" fn in
     let b = builder_at_end context bb04 in
@@ -974,7 +1153,7 @@ let test_builder () =
   end;
   
   group "unreachable"; begin
-    (* RUN: grep "unreachable" < %t.ll
+    (* CHECK: unreachable
      *)
     let bb06 = append_block context "Bb06" fn in
     let b = builder_at_end context bb06 in
@@ -985,36 +1164,36 @@ let test_builder () =
     let bb07 = append_block context "Bb07" fn in
     let b = builder_at_end context bb07 in
     
-    (* RUN: grep "%build_add = add i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_nsw_add = add nsw i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_nuw_add = add nuw i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_fadd = fadd float %F1, %F2" < %t.ll
-     * RUN: grep "%build_sub = sub i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_nsw_sub = sub nsw i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_nuw_sub = sub nuw i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_fsub = fsub float %F1, %F2" < %t.ll
-     * RUN: grep "%build_mul = mul i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_nsw_mul = mul nsw i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_nuw_mul = mul nuw i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_fmul = fmul float %F1, %F2" < %t.ll
-     * RUN: grep "%build_udiv = udiv i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_sdiv = sdiv i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_exact_sdiv = sdiv exact i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_fdiv = fdiv float %F1, %F2" < %t.ll
-     * RUN: grep "%build_urem = urem i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_srem = srem i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_frem = frem float %F1, %F2" < %t.ll
-     * RUN: grep "%build_shl = shl i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_lshl = lshr i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_ashl = ashr i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_and = and i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_or = or i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_xor = xor i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_neg = sub i32 0, %P1" < %t.ll
-     * RUN: grep "%build_nsw_neg = sub nsw i32 0, %P1" < %t.ll
-     * RUN: grep "%build_nuw_neg = sub nuw i32 0, %P1" < %t.ll
-     * RUN: grep "%build_fneg = fsub float .*0.*, %F1" < %t.ll
-     * RUN: grep "%build_not = xor i32 %P1, -1" < %t.ll
+    (* CHECK: %build_add = add i32 %P1, %P2
+     * CHECK: %build_nsw_add = add nsw i32 %P1, %P2
+     * CHECK: %build_nuw_add = add nuw i32 %P1, %P2
+     * CHECK: %build_fadd = fadd float %F1, %F2
+     * CHECK: %build_sub = sub i32 %P1, %P2
+     * CHECK: %build_nsw_sub = sub nsw i32 %P1, %P2
+     * CHECK: %build_nuw_sub = sub nuw i32 %P1, %P2
+     * CHECK: %build_fsub = fsub float %F1, %F2
+     * CHECK: %build_mul = mul i32 %P1, %P2
+     * CHECK: %build_nsw_mul = mul nsw i32 %P1, %P2
+     * CHECK: %build_nuw_mul = mul nuw i32 %P1, %P2
+     * CHECK: %build_fmul = fmul float %F1, %F2
+     * CHECK: %build_udiv = udiv i32 %P1, %P2
+     * CHECK: %build_sdiv = sdiv i32 %P1, %P2
+     * CHECK: %build_exact_sdiv = sdiv exact i32 %P1, %P2
+     * CHECK: %build_fdiv = fdiv float %F1, %F2
+     * CHECK: %build_urem = urem i32 %P1, %P2
+     * CHECK: %build_srem = srem i32 %P1, %P2
+     * CHECK: %build_frem = frem float %F1, %F2
+     * CHECK: %build_shl = shl i32 %P1, %P2
+     * CHECK: %build_lshl = lshr i32 %P1, %P2
+     * CHECK: %build_ashl = ashr i32 %P1, %P2
+     * CHECK: %build_and = and i32 %P1, %P2
+     * CHECK: %build_or = or i32 %P1, %P2
+     * CHECK: %build_xor = xor i32 %P1, %P2
+     * CHECK: %build_neg = sub i32 0, %P1
+     * CHECK: %build_nsw_neg = sub nsw i32 0, %P1
+     * CHECK: %build_nuw_neg = sub nuw i32 0, %P1
+     * CHECK: %build_fneg = fsub float {{.*}}0{{.*}}, %F1
+     * CHECK: %build_not = xor i32 %P1, -1
      *)
     ignore (build_add p1 p2 "build_add" b);
     ignore (build_nsw_add p1 p2 "build_nsw_add" b);
@@ -1053,13 +1232,13 @@ let test_builder () =
     let bb08 = append_block context "Bb08" fn in
     let b = builder_at_end context bb08 in
 
-    (* RUN: grep "%build_alloca = alloca i32" < %t.ll
-     * RUN: grep "%build_array_alloca = alloca i32, i32 %P2" < %t.ll
-     * RUN: grep "%build_load = load i32\* %build_array_alloca" < %t.ll
-     * RUN: grep "store i32 %P2, i32\* %build_alloca" < %t.ll
-     * RUN: grep "%build_gep = getelementptr i32\* %build_array_alloca, i32 %P2" < %t.ll
-     * RUN: grep "%build_in_bounds_gep = getelementptr inbounds i32\* %build_array_alloca, i32 %P2" < %t.ll
-     * RUN: grep "%build_struct_gep = getelementptr inbounds.*%build_alloca2, i32 0, i32 1" < %t.ll
+    (* CHECK: %build_alloca = alloca i32
+     * CHECK: %build_array_alloca = alloca i32, i32 %P2
+     * CHECK: %build_load = load i32* %build_array_alloca
+     * CHECK: store i32 %P2, i32* %build_alloca
+     * CHECK: %build_gep = getelementptr i32* %build_array_alloca, i32 %P2
+     * CHECK: %build_in_bounds_gep = getelementptr inbounds i32* %build_array_alloca, i32 %P2
+     * CHECK: %build_struct_gep = getelementptr inbounds{{.*}}%build_alloca2, i32 0, i32 1
      *)
     let alloca = build_alloca i32_type "build_alloca" b in
     let array_alloca = build_array_alloca i32_type p2 "build_array_alloca" b in
@@ -1079,8 +1258,8 @@ let test_builder () =
     let bb09 = append_block context "Bb09" fn in
     let b = builder_at_end context bb09 in
     let p = build_alloca (pointer_type i8_type) "p" b in
-    (* RUN: grep "build_global_string.*stringval" < %t.ll
-     * RUN: grep "store.*build_global_string1.*p" < %t.ll
+    (* build_global_string is emitted above.
+     * CHECK: store{{.*}}build_global_string1{{.*}}p
      * *)
     ignore (build_global_string "stringval" "build_global_string" b);
     let g = build_global_stringptr "stringval" "build_global_string1" b in
@@ -1088,181 +1267,8 @@ let test_builder () =
     ignore(build_unreachable b);
   end;
 
-  group "casts"; begin
-    let void_ptr = pointer_type i8_type in
-    
-    (* RUN: grep "%build_trunc = trunc i32 %P1 to i8" < %t.ll
-     * RUN: grep "%build_trunc2 = trunc i32 %P1 to i8" < %t.ll
-     * RUN: grep "%build_trunc3 = trunc i32 %P1 to i8" < %t.ll
-     * RUN: grep "%build_zext = zext i8 %build_trunc to i32" < %t.ll
-     * RUN: grep "%build_zext2 = zext i8 %build_trunc to i32" < %t.ll
-     * RUN: grep "%build_sext = sext i32 %build_zext to i64" < %t.ll
-     * RUN: grep "%build_sext2 = sext i32 %build_zext to i64" < %t.ll
-     * RUN: grep "%build_sext3 = sext i32 %build_zext to i64" < %t.ll
-     * RUN: grep "%build_uitofp = uitofp i64 %build_sext to float" < %t.ll
-     * RUN: grep "%build_sitofp = sitofp i32 %build_zext to double" < %t.ll
-     * RUN: grep "%build_fptoui = fptoui float %build_uitofp to i32" < %t.ll
-     * RUN: grep "%build_fptosi = fptosi double %build_sitofp to i64" < %t.ll
-     * RUN: grep "%build_fptrunc = fptrunc double %build_sitofp to float" < %t.ll
-     * RUN: grep "%build_fptrunc2 = fptrunc double %build_sitofp to float" < %t.ll
-     * RUN: grep "%build_fpext = fpext float %build_fptrunc to double" < %t.ll
-     * RUN: grep "%build_fpext2 = fpext float %build_fptrunc to double" < %t.ll
-     * RUN: grep "%build_inttoptr = inttoptr i32 %P1 to i8\*" < %t.ll
-     * RUN: grep "%build_ptrtoint = ptrtoint i8\* %build_inttoptr to i64" < %t.ll
-     * RUN: grep "%build_ptrtoint2 = ptrtoint i8\* %build_inttoptr to i64" < %t.ll
-     * RUN: grep "%build_bitcast = bitcast i64 %build_ptrtoint to double" < %t.ll
-     * RUN: grep "%build_bitcast2 = bitcast i64 %build_ptrtoint to double" < %t.ll
-     * RUN: grep "%build_bitcast3 = bitcast i64 %build_ptrtoint to double" < %t.ll
-     * RUN: grep "%build_bitcast4 = bitcast i64 %build_ptrtoint to double" < %t.ll
-     * RUN: grep "%build_pointercast = bitcast i8\* %build_inttoptr to i16*" < %t.ll
-     *)
-    let inst28 = build_trunc p1 i8_type "build_trunc" atentry in
-    let inst29 = build_zext inst28 i32_type "build_zext" atentry in
-    let inst30 = build_sext inst29 i64_type "build_sext" atentry in
-    let inst31 = build_uitofp inst30 float_type "build_uitofp" atentry in
-    let inst32 = build_sitofp inst29 double_type "build_sitofp" atentry in
-    ignore(build_fptoui inst31 i32_type "build_fptoui" atentry);
-    ignore(build_fptosi inst32 i64_type "build_fptosi" atentry);
-    let inst35 = build_fptrunc inst32 float_type "build_fptrunc" atentry in
-    ignore(build_fpext inst35 double_type "build_fpext" atentry);
-    let inst37 = build_inttoptr p1 void_ptr "build_inttoptr" atentry in
-    let inst38 = build_ptrtoint inst37 i64_type "build_ptrtoint" atentry in
-    ignore(build_bitcast inst38 double_type "build_bitcast" atentry);
-    ignore(build_zext_or_bitcast inst38 double_type "build_bitcast2" atentry);
-    ignore(build_sext_or_bitcast inst38 double_type "build_bitcast3" atentry);
-    ignore(build_trunc_or_bitcast inst38 double_type "build_bitcast4" atentry);
-    ignore(build_pointercast inst37 (pointer_type i16_type) "build_pointercast" atentry);
-
-    ignore(build_zext_or_bitcast inst28 i32_type "build_zext2" atentry);
-    ignore(build_sext_or_bitcast inst29 i64_type "build_sext2" atentry);
-    ignore(build_trunc_or_bitcast p1 i8_type "build_trunc2" atentry);
-    ignore(build_pointercast inst37 i64_type "build_ptrtoint2" atentry);
-    ignore(build_intcast inst29 i64_type "build_sext3" atentry);
-    ignore(build_intcast p1 i8_type "build_trunc3" atentry);
-    ignore(build_fpcast inst35 double_type "build_fpext2" atentry);
-    ignore(build_fpcast inst32 float_type "build_fptrunc2" atentry);
-  end;
-  
-  group "comparisons"; begin
-    (* RUN: grep "%build_icmp_ne = icmp ne i32 %P1, %P2" < %t.ll
-     * RUN: grep "%build_icmp_sle = icmp sle i32 %P2, %P1" < %t.ll
-     * RUN: grep "%build_fcmp_false = fcmp false float %F1, %F2" < %t.ll
-     * RUN: grep "%build_fcmp_true = fcmp true float %F2, %F1" < %t.ll
-     * RUN: grep "%build_is_null.*= icmp eq.*%X0,.*null" < %t.ll
-     * RUN: grep "%build_is_not_null = icmp ne i8\* %X1, null" < %t.ll
-     * RUN: grep "%build_ptrdiff" < %t.ll
-     *)
-    ignore (build_icmp Icmp.Ne    p1 p2 "build_icmp_ne" atentry);
-    ignore (build_icmp Icmp.Sle   p2 p1 "build_icmp_sle" atentry);
-    ignore (build_fcmp Fcmp.False f1 f2 "build_fcmp_false" atentry);
-    ignore (build_fcmp Fcmp.True  f2 f1 "build_fcmp_true" atentry);
-    let g0 = declare_global (pointer_type i8_type) "g0" m in
-    let g1 = declare_global (pointer_type i8_type) "g1" m in
-    let p0 = build_load g0 "X0" atentry in
-    let p1 = build_load g1 "X1" atentry in
-    ignore (build_is_null p0 "build_is_null" atentry);
-    ignore (build_is_not_null p1 "build_is_not_null" atentry);
-    ignore (build_ptrdiff p1 p0 "build_ptrdiff" atentry);
-  end;
-  
-  group "miscellaneous"; begin
-    (* RUN: grep "%build_call = tail call cc63 i32 @.*(i32 signext %P2, i32 %P1)" < %t.ll
-     * RUN: grep "%build_select = select i1 %build_icmp, i32 %P1, i32 %P2" < %t.ll
-     * RUN: grep "%build_va_arg = va_arg i8\*\* null, i32" < %t.ll
-     * RUN: grep "%build_extractelement = extractelement <4 x i32> %Vec1, i32 %P2" < %t.ll
-     * RUN: grep "%build_insertelement = insertelement <4 x i32> %Vec1, i32 %P1, i32 %P2" < %t.ll
-     * RUN: grep "%build_shufflevector = shufflevector <4 x i32> %Vec1, <4 x i32> %Vec2, <4 x i32> <i32 1, i32 1, i32 0, i32 0>" < %t.ll
-     * RUN: grep "%build_insertvalue0 = insertvalue.*%bl, i32 1, 0" < %t.ll
-     * RUN: grep "%build_extractvalue = extractvalue.*%build_insertvalue1, 1" < %t.ll
-     *)
-    let ci = build_call fn [| p2; p1 |] "build_call" atentry in
-    insist (CallConv.c = instruction_call_conv ci);
-    set_instruction_call_conv 63 ci;
-    insist (63 = instruction_call_conv ci);
-    insist (not (is_tail_call ci));
-    set_tail_call true ci;
-    insist (is_tail_call ci);
-    add_instruction_param_attr ci 1 Attribute.Sext;
-    add_instruction_param_attr ci 2 Attribute.Noalias;
-    remove_instruction_param_attr ci 2 Attribute.Noalias;
-    
-    let inst46 = build_icmp Icmp.Eq p1 p2 "build_icmp" atentry in
-    ignore (build_select inst46 p1 p2 "build_select" atentry);
-    ignore (build_va_arg
-      (const_null (pointer_type (pointer_type i8_type)))
-      i32_type "build_va_arg" atentry);
-    
-    (* Set up some vector vregs. *)
-    let one  = const_int i32_type 1 in
-    let zero = const_int i32_type 0 in
-    let t1 = const_vector [| one; zero; one; zero |] in
-    let t2 = const_vector [| zero; one; zero; one |] in
-    let t3 = const_vector [| one; one; zero; zero |] in
-    let vec1 = build_insertelement t1 p1 p2 "Vec1" atentry in
-    let vec2 = build_insertelement t2 p1 p2 "Vec2" atentry in
-    let sty = struct_type context [| i32_type; i8_type |] in
-    
-    ignore (build_extractelement vec1 p2 "build_extractelement" atentry);
-    ignore (build_insertelement vec1 p1 p2 "build_insertelement" atentry);
-    ignore (build_shufflevector vec1 vec2 t3 "build_shufflevector" atentry);
-
-    let p = build_alloca sty "ba" atentry in
-    let agg = build_load p "bl" atentry in
-    let agg0 = build_insertvalue agg (const_int i32_type 1) 0
-                 "build_insertvalue0" atentry in
-    let agg1 = build_insertvalue agg0 (const_int i8_type 2) 1
-                 "build_insertvalue1" atentry in
-    ignore (build_extractvalue agg1 1 "build_extractvalue" atentry)
-  end;
-
-  group "metadata"; begin
-    (* RUN: grep '%metadata = add i32 %P1, %P2, !test !0' < %t.ll
-     * RUN: grep '!0 = metadata !{i32 1, metadata !"metadata test"}' < %t.ll
-     *)
-    let i = build_add p1 p2 "metadata" atentry in
-    insist ((has_metadata i) = false);
-
-    let m1 = const_int i32_type 1 in
-    let m2 = mdstring context "metadata test" in
-    let md = mdnode context [| m1; m2 |] in
-
-    let kind = mdkind_id context "test" in
-    set_metadata i kind md;
-
-    insist ((has_metadata i) = true);
-    insist ((metadata i kind) = Some md);
-
-    clear_metadata i kind;
-
-    insist ((has_metadata i) = false);
-    insist ((metadata i kind) = None);
-
-    set_metadata i kind md
-  end;
-
-  group "dbg"; begin
-    (* RUN: grep '%dbg = add i32 %P1, %P2, !dbg !1' < %t.ll
-     * RUN: grep '!1 = metadata !{i32 2, i32 3, metadata !2, metadata !2}' < %t.ll
-     *)
-    insist ((current_debug_location atentry) = None);
-
-    let m_line = const_int i32_type 2 in
-    let m_col = const_int i32_type 3 in
-    let m_scope = mdnode context [| |] in
-    let m_inlined = mdnode context [| |] in
-    let md = mdnode context [| m_line; m_col; m_scope; m_inlined |] in
-    set_current_debug_location atentry md;
-
-    insist ((current_debug_location atentry) = Some md);
-
-    let i = build_add p1 p2 "dbg" atentry in
-    insist ((has_metadata i) = true);
-
-    clear_current_debug_location atentry
-  end;
-  
   group "phi"; begin
-    (* RUN: grep "PhiNode.*P1.*PhiBlock1.*P2.*PhiBlock2" < %t.ll
+    (* CHECK: PhiNode{{.*}}P1{{.*}}PhiBlock1{{.*}}P2{{.*}}PhiBlock2
      *)
     let b1 = append_block context "PhiBlock1" fn in
     let b2 = append_block context "PhiBlock2" fn in
@@ -1281,6 +1287,11 @@ let test_builder () =
     ignore (build_unreachable at_jb);
   end
 
+(* End-of-file checks for things like metdata and attributes.
+ * CHECK: attributes #0 = {{.*}}uwtable{{.*}}
+ * CHECK: !0 = metadata !{i32 1, metadata !"metadata test"}
+ * CHECK: !1 = metadata !{i32 2, i32 3, metadata !2, metadata !2}
+ *)
 
 (*===-- Pass Managers -----------------------------------------------------===*)
 
diff --git a/test/Bitcode/attributes-3.3.ll b/test/Bitcode/attributes-3.3.ll
new file mode 100644
index 0000000..cd70ba1
--- /dev/null
+++ b/test/Bitcode/attributes-3.3.ll
@@ -0,0 +1,236 @@
+; RUN:  llvm-dis < %s.bc| FileCheck %s
+
+; attributes-3.3.ll.bc was generated by passing this file to llvm-as-3.3.
+; The test checks that LLVM does not silently misread attributes of
+; older bitcode files.
+
+define void @f1(i8 zeroext)
+; CHECK: define void @f1(i8 zeroext)
+{
+        ret void;
+}
+
+define void @f2(i8 signext)
+; CHECK: define void @f2(i8 signext)
+{
+        ret void;
+}
+
+define void @f3() noreturn
+; CHECK: define void @f3() #0
+{
+        ret void;
+}
+
+define void @f4(i8 inreg)
+; CHECK: define void @f4(i8 inreg)
+{
+        ret void;
+}
+
+define void @f5(i8* sret)
+; CHECK: define void @f5(i8* sret)
+{
+        ret void;
+}
+
+define void @f6() nounwind
+; CHECK: define void @f6() #1
+{
+        ret void;
+}
+
+define void @f7(i8* noalias)
+; CHECK: define void @f7(i8* noalias)
+{
+        ret void;
+}
+
+define void @f8(i8* byval)
+; CHECK: define void @f8(i8* byval)
+{
+        ret void;
+}
+
+define void @f9(i8* nest)
+; CHECK: define void @f9(i8* nest)
+{
+        ret void;
+}
+
+define void @f10() readnone
+; CHECK: define void @f10() #2
+{
+        ret void;
+}
+
+define void @f11() readonly
+; CHECK: define void @f11() #3
+{
+        ret void;
+}
+
+define void @f12() noinline
+; CHECK: define void @f12() #4
+{
+        ret void;
+}
+
+define void @f13() alwaysinline
+; CHECK: define void @f13() #5
+{
+        ret void;
+}
+
+define void @f14() optsize
+; CHECK: define void @f14() #6
+{
+        ret void;
+}
+
+define void @f15() ssp
+; CHECK: define void @f15() #7
+{
+        ret void;
+}
+
+define void @f16() sspreq
+; CHECK: define void @f16() #8
+{
+        ret void;
+}
+
+define void @f17(i8 align 4)
+; CHECK: define void @f17(i8 align 4)
+{
+        ret void;
+}
+
+define void @f18(i8* nocapture)
+; CHECK: define void @f18(i8* nocapture)
+{
+        ret void;
+}
+
+define void @f19() noredzone
+; CHECK: define void @f19() #9
+{
+        ret void;
+}
+
+define void @f20() noimplicitfloat
+; CHECK: define void @f20() #10
+{
+        ret void;
+}
+
+define void @f21() naked
+; CHECK: define void @f21() #11
+{
+        ret void;
+}
+
+define void @f22() inlinehint
+; CHECK: define void @f22() #12
+{
+        ret void;
+}
+
+define void @f23() alignstack(4)
+; CHECK: define void @f23() #13
+{
+        ret void;
+}
+
+define void @f24() returns_twice
+; CHECK: define void @f24() #14
+{
+        ret void;
+}
+
+define void @f25() uwtable
+; CHECK: define void @f25() #15
+{
+        ret void;
+}
+
+define void @f26() nonlazybind
+; CHECK: define void @f26() #16
+{
+        ret void;
+}
+
+define void @f27() sanitize_address
+; CHECK: define void @f27() #17
+{
+        ret void;
+}
+define void @f28() sanitize_thread
+; CHECK: define void @f28() #18
+{
+        ret void;
+}
+define void @f29() sanitize_memory
+; CHECK: define void @f29() #19
+{
+        ret void;
+}
+
+define void @f30() "cpu"="cortex-a8"
+; CHECK: define void @f30() #20
+{
+        ret void;
+}
+
+define i8 @f31(i8 returned %A)
+; CHECK: define i8 @f31(i8 returned %A)
+{
+        ret i8 %A;
+}
+
+define void @f32() sspstrong
+; CHECK: define void @f32() #21
+{
+        ret void;
+}
+
+define void @f33() minsize
+; CHECK: define void @f33() #22
+{
+        ret void;
+}
+
+declare void @nobuiltin()
+
+define void @f34()
+; CHECK: define void @f34()
+{
+        call void @nobuiltin() nobuiltin
+; CHECK: call void @nobuiltin() #23
+        ret void;
+}
+
+; CHECK: attributes #0 = { noreturn }
+; CHECK: attributes #1 = { nounwind }
+; CHECK: attributes #2 = { readnone }
+; CHECK: attributes #3 = { readonly }
+; CHECK: attributes #4 = { noinline }
+; CHECK: attributes #5 = { alwaysinline }
+; CHECK: attributes #6 = { optsize }
+; CHECK: attributes #7 = { ssp }
+; CHECK: attributes #8 = { sspreq }
+; CHECK: attributes #9 = { noredzone }
+; CHECK: attributes #10 = { noimplicitfloat }
+; CHECK: attributes #11 = { naked }
+; CHECK: attributes #12 = { inlinehint }
+; CHECK: attributes #13 = { alignstack=4 }
+; CHECK: attributes #14 = { returns_twice }
+; CHECK: attributes #15 = { uwtable }
+; CHECK: attributes #16 = { nonlazybind }
+; CHECK: attributes #17 = { sanitize_address }
+; CHECK: attributes #18 = { sanitize_thread }
+; CHECK: attributes #19 = { sanitize_memory }
+; CHECK: attributes #20 = { "cpu"="cortex-a8" }
+; CHECK: attributes #21 = { sspstrong }
+; CHECK: attributes #22 = { minsize }
+; CHECK: attributes #23 = { nobuiltin }
diff --git a/test/Bitcode/attributes-3.3.ll.bc b/test/Bitcode/attributes-3.3.ll.bc
new file mode 100644
index 0000000..5dd7186
--- /dev/null
+++ b/test/Bitcode/attributes-3.3.ll.bc
diff --git a/test/Bitcode/attributes.ll b/test/Bitcode/attributes.ll
index 6c46e94..92f892a 100644
--- a/test/Bitcode/attributes.ll
+++ b/test/Bitcode/attributes.ll
@@ -179,6 +179,34 @@ define void @f30() "cpu"="cortex-a8"
         ret void;
 }
 
+define i8 @f31(i8 returned %A)
+; CHECK: define i8 @f31(i8 returned %A)
+{
+        ret i8 %A;
+}
+
+define void @f32() sspstrong
+; CHECK: define void @f32() #21
+{
+        ret void;
+}
+
+define void @f33() minsize
+; CHECK: define void @f33() #22
+{
+        ret void;
+}
+
+declare void @nobuiltin()
+
+define void @f34()
+; CHECK: define void @f34()
+{
+        call void @nobuiltin() nobuiltin
+; CHECK: call void @nobuiltin() #23
+        ret void;
+}
+
 ; CHECK: attributes #0 = { noreturn }
 ; CHECK: attributes #1 = { nounwind }
 ; CHECK: attributes #2 = { readnone }
@@ -200,3 +228,6 @@ define void @f30() "cpu"="cortex-a8"
 ; CHECK: attributes #18 = { sanitize_thread }
 ; CHECK: attributes #19 = { sanitize_memory }
 ; CHECK: attributes #20 = { "cpu"="cortex-a8" }
+; CHECK: attributes #21 = { sspstrong }
+; CHECK: attributes #22 = { minsize }
+; CHECK: attributes #23 = { nobuiltin }
diff --git a/test/BugPoint/crash-narrowfunctiontest.ll b/test/BugPoint/crash-narrowfunctiontest.ll
index c812836..d080d9d 100644
--- a/test/BugPoint/crash-narrowfunctiontest.ll
+++ b/test/BugPoint/crash-narrowfunctiontest.ll
@@ -2,7 +2,6 @@
 ;
 ; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -silence-passes > /dev/null
 ; REQUIRES: loadable_module
-; XFAIL: lto_on_osx
 
 define i32 @foo() { ret i32 1 }
 
diff --git a/test/BugPoint/metadata.ll b/test/BugPoint/metadata.ll
index 6dc9574..2ba1a9f 100644
--- a/test/BugPoint/metadata.ll
+++ b/test/BugPoint/metadata.ll
@@ -1,14 +1,15 @@
 ; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -silence-passes > /dev/null
 ; RUN: llvm-dis %t-reduced-simplified.bc -o - | FileCheck %s
 ; REQUIRES: loadable_module
-; XFAIL: lto_on_osx
 
 ; Bugpoint should keep the call's metadata attached to the call.
 
-; CHECK: call void @foo(), !dbg !0, !attach !2
+; CHECK: call void @foo(), !dbg !0, !attach !4
 ; CHECK: !0 = metadata !{i32 104, i32 105, metadata !1, metadata !1}
-; CHECK: !1 = metadata !{i32 0, i32 0, i32 0, metadata !"source.c", metadata !"/dir", metadata !"me", i1 true, i1 false, metadata !"", i32 0}
-; CHECK: !2 = metadata !{metadata !"the call to foo"}
+; CHECK: !1 = metadata !{i32 458769, metadata !2, i32 0, metadata !"me", i1 true, metadata !"", i32 0, metadata !3, metadata !3, null, null, null, metadata !""}
+; CHECK: !2 = metadata !{metadata !"source.c", metadata !"/dir"}
+; CHECK: !3 = metadata !{i32 0}
+; CHECK: !4 = metadata !{metadata !"the call to foo"}
 
 %rust_task = type {}
 define void @test(i32* %a, i8* %b) {
@@ -28,9 +29,11 @@ declare void @foo()
 !3 = metadata !{metadata !"noise"}
 !4 = metadata !{metadata !"filler"}
 
-!9 = metadata !{i32 0, i32 0, i32 0, metadata !"source.c", metadata !"/dir", metadata !"me", i1 true, i1 false, metadata !"", i32 0}
+!9 = metadata !{i32 458769, metadata !15, i32 0, metadata !"me", i1 true, metadata !"", i32 0, metadata !16, metadata !16, null, null, null, metadata !""}
 !10 = metadata !{i32 100, i32 101, metadata !9, metadata !9}
 !11 = metadata !{i32 102, i32 103, metadata !9, metadata !9}
 !12 = metadata !{i32 104, i32 105, metadata !9, metadata !9}
 !13 = metadata !{i32 106, i32 107, metadata !9, metadata !9}
 !14 = metadata !{i32 108, i32 109, metadata !9, metadata !9}
+!15 = metadata !{metadata !"source.c", metadata !"/dir"}
+!16 = metadata !{i32 0}
diff --git a/test/BugPoint/remove_arguments_test.ll b/test/BugPoint/remove_arguments_test.ll
index 5a45f84..29a03b8 100644
--- a/test/BugPoint/remove_arguments_test.ll
+++ b/test/BugPoint/remove_arguments_test.ll
@@ -1,7 +1,6 @@
 ; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -silence-passes
 ; RUN: llvm-dis %t-reduced-simplified.bc -o - | FileCheck %s
 ; REQUIRES: loadable_module
-; XFAIL: lto_on_osx
 
 ; Test to make sure that arguments are removed from the function if they are 
 ; unnecessary. And clean up any types that that frees up too.
diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt
index 728213f..392f5f2 100644
--- a/test/CMakeLists.txt
+++ b/test/CMakeLists.txt
@@ -13,11 +13,20 @@ if(NOT LLVM_BUILD_TOOLS)
 endif()
 
 # Set the depends list as a variable so that it can grow conditionally.
-set(LLVM_TEST_DEPENDS UnitTests
-          BugpointPasses LLVMHello
-          llc lli llvm-ar llvm-as
-          llvm-bcanalyzer llvm-diff
-          llvm-dis llvm-extract llvm-dwarfdump
+set(LLVM_TEST_DEPENDS
+          UnitTests
+          BugpointPasses
+          LLVMHello
+          llc
+          lli
+          llvm-ar
+          llvm-as
+          llvm-bcanalyzer
+          llvm-cov
+          llvm-diff
+          llvm-dis
+          llvm-extract
+          llvm-dwarfdump
           llvm-link
           llvm-mc
           llvm-mcmarkup
@@ -26,10 +35,15 @@ set(LLVM_TEST_DEPENDS UnitTests
           llvm-readobj
           llvm-rtdyld
           llvm-symbolizer
-          macho-dump opt
+          macho-dump
+          opt
           profile_rt-shared
-          FileCheck count not
-          yaml2obj obj2yaml)
+          FileCheck
+          count
+          not
+          yaml2obj
+          obj2yaml
+        )
 
 # If Intel JIT events are supported, depend on a tool that tests the listener.
 if( LLVM_USE_INTEL_JITEVENTS )
diff --git a/test/CodeGen/AArch64/adc.ll b/test/CodeGen/AArch64/adc.ll
index 7cb3732..26fd3e6 100644
--- a/test/CodeGen/AArch64/adc.ll
+++ b/test/CodeGen/AArch64/adc.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
 
 define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
-; CHECK: test_simple:
+; CHECK-LABEL: test_simple:
 
   %valadd = add i128 %a, %b
 ; CHECK: adds [[ADDLO:x[0-9]+]], x0, x2
@@ -16,7 +16,7 @@ define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
 }
 
 define i128 @test_imm(i128 %a) {
-; CHECK: test_imm:
+; CHECK-LABEL: test_imm:
 
   %val = add i128 %a, 12
 ; CHECK: adds x0, x0, #12
@@ -27,7 +27,7 @@ define i128 @test_imm(i128 %a) {
 }
 
 define i128 @test_shifted(i128 %a, i128 %b) {
-; CHECK: test_shifted:
+; CHECK-LABEL: test_shifted:
 
   %rhs = shl i128 %b, 45
 
@@ -40,7 +40,7 @@ define i128 @test_shifted(i128 %a, i128 %b) {
 }
 
 define i128 @test_extended(i128 %a, i16 %b) {
-; CHECK: test_extended:
+; CHECK-LABEL: test_extended:
 
   %ext = sext i16 %b to i128
   %rhs = shl i128 %ext, 3
diff --git a/test/CodeGen/AArch64/addsub-shifted.ll b/test/CodeGen/AArch64/addsub-shifted.ll
index f2c74f6..269c1e8 100644
--- a/test/CodeGen/AArch64/addsub-shifted.ll
+++ b/test/CodeGen/AArch64/addsub-shifted.ll
@@ -4,7 +4,7 @@
 @var64 = global i64 0
 
 define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
-; CHECK: test_lsl_arith:
+; CHECK-LABEL: test_lsl_arith:
 
   %rhs1 = load volatile i32* @var32
   %shift1 = shl i32 %rhs1, 18
@@ -73,7 +73,7 @@ define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
 }
 
 define void @test_lsr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
-; CHECK: test_lsr_arith:
+; CHECK-LABEL: test_lsr_arith:
 
   %shift1 = lshr i32 %rhs32, 18
   %val1 = add i32 %lhs32, %shift1
@@ -132,7 +132,7 @@ define void @test_lsr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
 }
 
 define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
-; CHECK: test_asr_arith:
+; CHECK-LABEL: test_asr_arith:
 
   %shift1 = ashr i32 %rhs32, 18
   %val1 = add i32 %lhs32, %shift1
@@ -191,7 +191,7 @@ define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
 }
 
 define i32 @test_cmp(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
-; CHECK: test_cmp:
+; CHECK-LABEL: test_cmp:
 
   %shift1 = shl i32 %rhs32, 13
   %tst1 = icmp uge i32 %lhs32, %shift1
@@ -237,7 +237,7 @@ end:
 }
 
 define i32 @test_cmn(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
-; CHECK: test_cmn:
+; CHECK-LABEL: test_cmn:
 
   %shift1 = shl i32 %rhs32, 13
   %val1 = sub i32 0, %shift1
diff --git a/test/CodeGen/AArch64/addsub.ll b/test/CodeGen/AArch64/addsub.ll
index 5148807..4d46d04 100644
--- a/test/CodeGen/AArch64/addsub.ll
+++ b/test/CodeGen/AArch64/addsub.ll
@@ -9,7 +9,7 @@
 
 ; Add pure 12-bit immediates:
 define void @add_small() {
-; CHECK: add_small:
+; CHECK-LABEL: add_small:
 
 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4095
   %val32 = load i32* @var_i32
@@ -26,7 +26,7 @@ define void @add_small() {
 
 ; Add 12-bit immediates, shifted left by 12 bits
 define void @add_med() {
-; CHECK: add_med:
+; CHECK-LABEL: add_med:
 
 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
   %val32 = load i32* @var_i32
@@ -43,7 +43,7 @@ define void @add_med() {
 
 ; Subtract 12-bit immediates
 define void @sub_small() {
-; CHECK: sub_small:
+; CHECK-LABEL: sub_small:
 
 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4095
   %val32 = load i32* @var_i32
@@ -60,7 +60,7 @@ define void @sub_small() {
 
 ; Subtract 12-bit immediates, shifted left by 12 bits
 define void @sub_med() {
-; CHECK: sub_med:
+; CHECK-LABEL: sub_med:
 
 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
   %val32 = load i32* @var_i32
@@ -76,7 +76,7 @@ define void @sub_med() {
 }
 
 define void @testing() {
-; CHECK: testing:
+; CHECK-LABEL: testing:
   %val = load i32* @var_i32
 
 ; CHECK: cmp {{w[0-9]+}}, #4095
diff --git a/test/CodeGen/AArch64/addsub_ext.ll b/test/CodeGen/AArch64/addsub_ext.ll
index 2dd1662..f0e11c6 100644
--- a/test/CodeGen/AArch64/addsub_ext.ll
+++ b/test/CodeGen/AArch64/addsub_ext.ll
@@ -6,7 +6,7 @@
 @var64 = global i64 0
 
 define void @addsub_i8rhs() {
-; CHECK: addsub_i8rhs:
+; CHECK-LABEL: addsub_i8rhs:
     %val8_tmp = load i8* @var8
     %lhs32 = load i32* @var32
     %lhs64 = load i64* @var64
@@ -81,7 +81,7 @@ end:
 }
 
 define void @addsub_i16rhs() {
-; CHECK: addsub_i16rhs:
+; CHECK-LABEL: addsub_i16rhs:
     %val16_tmp = load i16* @var16
     %lhs32 = load i32* @var32
     %lhs64 = load i64* @var64
@@ -159,7 +159,7 @@ end:
 ; example), but the remaining instructions are probably not idiomatic
 ; in the face of "add/sub (shifted register)" so I don't intend to.
 define void @addsub_i32rhs() {
-; CHECK: addsub_i32rhs:
+; CHECK-LABEL: addsub_i32rhs:
     %val32_tmp = load i32* @var32
     %lhs64 = load i64* @var64
 
@@ -186,4 +186,4 @@ define void @addsub_i32rhs() {
 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw #2
 
     ret void
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/AArch64/alloca.ll b/test/CodeGen/AArch64/alloca.ll
index c62edf6..a84217f 100644
--- a/test/CodeGen/AArch64/alloca.ll
+++ b/test/CodeGen/AArch64/alloca.ll
@@ -3,7 +3,7 @@
 declare void @use_addr(i8*)
 
 define void @test_simple_alloca(i64 %n) {
-; CHECK: test_simple_alloca:
+; CHECK-LABEL: test_simple_alloca:
 
   %buf = alloca i8, i64 %n
   ; Make sure we align the stack change to 16 bytes:
@@ -30,7 +30,7 @@ define void @test_simple_alloca(i64 %n) {
 declare void @use_addr_loc(i8*, i64*)
 
 define i64 @test_alloca_with_local(i64 %n) {
-; CHECK: test_alloca_with_local:
+; CHECK-LABEL: test_alloca_with_local:
 ; CHECK: sub sp, sp, #32
 ; CHECK: stp x29, x30, [sp, #16]
 
@@ -66,7 +66,7 @@ define i64 @test_alloca_with_local(i64 %n) {
 }
 
 define void @test_variadic_alloca(i64 %n, ...) {
-; CHECK: test_variadic_alloca:
+; CHECK-LABEL: test_variadic_alloca:
 
 ; CHECK: sub     sp, sp, #208
 ; CHECK: stp     x29, x30, [sp, #192]
@@ -89,7 +89,7 @@ define void @test_variadic_alloca(i64 %n, ...) {
 }
 
 define void @test_alloca_large_frame(i64 %n) {
-; CHECK: test_alloca_large_frame:
+; CHECK-LABEL: test_alloca_large_frame:
 
 ; CHECK: sub sp, sp, #496
 ; CHECK: stp x29, x30, [sp, #480]
diff --git a/test/CodeGen/AArch64/analyze-branch.ll b/test/CodeGen/AArch64/analyze-branch.ll
index e10bbb0..36bc2e0 100644
--- a/test/CodeGen/AArch64/analyze-branch.ll
+++ b/test/CodeGen/AArch64/analyze-branch.ll
@@ -11,7 +11,7 @@ declare void @test_false()
 !1 = metadata !{metadata !"branch_weights", i32 4, i32 64}
 
 define void @test_Bcc_fallthrough_taken(i32 %in) nounwind {
-; CHECK: test_Bcc_fallthrough_taken:
+; CHECK-LABEL: test_Bcc_fallthrough_taken:
   %tst = icmp eq i32 %in, 42
   br i1 %tst, label %true, label %false, !prof !0
 
@@ -34,7 +34,7 @@ false:
 }
 
 define void @test_Bcc_fallthrough_nottaken(i32 %in) nounwind {
-; CHECK: test_Bcc_fallthrough_nottaken:
+; CHECK-LABEL: test_Bcc_fallthrough_nottaken:
   %tst = icmp eq i32 %in, 42
   br i1 %tst, label %true, label %false, !prof !1
 
@@ -57,7 +57,7 @@ false:
 }
 
 define void @test_CBZ_fallthrough_taken(i32 %in) nounwind {
-; CHECK: test_CBZ_fallthrough_taken:
+; CHECK-LABEL: test_CBZ_fallthrough_taken:
   %tst = icmp eq i32 %in, 0
   br i1 %tst, label %true, label %false, !prof !0
 
@@ -78,7 +78,7 @@ false:
 }
 
 define void @test_CBZ_fallthrough_nottaken(i64 %in) nounwind {
-; CHECK: test_CBZ_fallthrough_nottaken:
+; CHECK-LABEL: test_CBZ_fallthrough_nottaken:
   %tst = icmp eq i64 %in, 0
   br i1 %tst, label %true, label %false, !prof !1
 
@@ -99,7 +99,7 @@ false:
 }
 
 define void @test_CBNZ_fallthrough_taken(i32 %in) nounwind {
-; CHECK: test_CBNZ_fallthrough_taken:
+; CHECK-LABEL: test_CBNZ_fallthrough_taken:
   %tst = icmp ne i32 %in, 0
   br i1 %tst, label %true, label %false, !prof !0
 
@@ -120,7 +120,7 @@ false:
 }
 
 define void @test_CBNZ_fallthrough_nottaken(i64 %in) nounwind {
-; CHECK: test_CBNZ_fallthrough_nottaken:
+; CHECK-LABEL: test_CBNZ_fallthrough_nottaken:
   %tst = icmp ne i64 %in, 0
   br i1 %tst, label %true, label %false, !prof !1
 
@@ -141,7 +141,7 @@ false:
 }
 
 define void @test_TBZ_fallthrough_taken(i32 %in) nounwind {
-; CHECK: test_TBZ_fallthrough_taken:
+; CHECK-LABEL: test_TBZ_fallthrough_taken:
   %bit = and i32 %in, 32768
   %tst = icmp eq i32 %bit, 0
   br i1 %tst, label %true, label %false, !prof !0
@@ -163,7 +163,7 @@ false:
 }
 
 define void @test_TBZ_fallthrough_nottaken(i64 %in) nounwind {
-; CHECK: test_TBZ_fallthrough_nottaken:
+; CHECK-LABEL: test_TBZ_fallthrough_nottaken:
   %bit = and i64 %in, 32768
   %tst = icmp eq i64 %bit, 0
   br i1 %tst, label %true, label %false, !prof !1
@@ -186,7 +186,7 @@ false:
 
 
 define void @test_TBNZ_fallthrough_taken(i32 %in) nounwind {
-; CHECK: test_TBNZ_fallthrough_taken:
+; CHECK-LABEL: test_TBNZ_fallthrough_taken:
   %bit = and i32 %in, 32768
   %tst = icmp ne i32 %bit, 0
   br i1 %tst, label %true, label %false, !prof !0
@@ -208,7 +208,7 @@ false:
 }
 
 define void @test_TBNZ_fallthrough_nottaken(i64 %in) nounwind {
-; CHECK: test_TBNZ_fallthrough_nottaken:
+; CHECK-LABEL: test_TBNZ_fallthrough_nottaken:
   %bit = and i64 %in, 32768
   %tst = icmp ne i64 %bit, 0
   br i1 %tst, label %true, label %false, !prof !1
diff --git a/test/CodeGen/AArch64/atomic-ops-not-barriers.ll b/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
index 9888a74..da095a0 100644
--- a/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
+++ b/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
 
 define i32 @foo(i32* %var, i1 %cond) {
-; CHECK: foo:
+; CHECK-LABEL: foo:
   br i1 %cond, label %atomic_ver, label %simple_ver
 simple_ver:
   %oldval = load i32* %var
diff --git a/test/CodeGen/AArch64/atomic-ops.ll b/test/CodeGen/AArch64/atomic-ops.ll
index 5e87f21..de84ff4 100644
--- a/test/CodeGen/AArch64/atomic-ops.ll
+++ b/test/CodeGen/AArch64/atomic-ops.ll
@@ -6,7 +6,7 @@
 @var64 = global i64 0
 
 define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_add_i8:
+; CHECK-LABEL: test_atomic_load_add_i8:
    %old = atomicrmw add i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -26,7 +26,7 @@ define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_add_i16:
+; CHECK-LABEL: test_atomic_load_add_i16:
    %old = atomicrmw add i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -46,7 +46,7 @@ define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_add_i32:
+; CHECK-LABEL: test_atomic_load_add_i32:
    %old = atomicrmw add i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -66,7 +66,7 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_add_i64:
+; CHECK-LABEL: test_atomic_load_add_i64:
    %old = atomicrmw add i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -86,7 +86,7 @@ define i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_sub_i8:
+; CHECK-LABEL: test_atomic_load_sub_i8:
    %old = atomicrmw sub i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -106,7 +106,7 @@ define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_sub_i16:
+; CHECK-LABEL: test_atomic_load_sub_i16:
    %old = atomicrmw sub i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -126,7 +126,7 @@ define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_sub_i32:
+; CHECK-LABEL: test_atomic_load_sub_i32:
    %old = atomicrmw sub i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -146,7 +146,7 @@ define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_sub_i64:
+; CHECK-LABEL: test_atomic_load_sub_i64:
    %old = atomicrmw sub i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -166,7 +166,7 @@ define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_and_i8:
+; CHECK-LABEL: test_atomic_load_and_i8:
    %old = atomicrmw and i8* @var8, i8 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -186,7 +186,7 @@ define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_and_i16:
+; CHECK-LABEL: test_atomic_load_and_i16:
    %old = atomicrmw and i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -206,7 +206,7 @@ define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_and_i32:
+; CHECK-LABEL: test_atomic_load_and_i32:
    %old = atomicrmw and i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -226,7 +226,7 @@ define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_and_i64:
+; CHECK-LABEL: test_atomic_load_and_i64:
    %old = atomicrmw and i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -246,7 +246,7 @@ define i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_or_i8:
+; CHECK-LABEL: test_atomic_load_or_i8:
    %old = atomicrmw or i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -266,7 +266,7 @@ define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_or_i16:
+; CHECK-LABEL: test_atomic_load_or_i16:
    %old = atomicrmw or i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -286,7 +286,7 @@ define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_or_i32:
+; CHECK-LABEL: test_atomic_load_or_i32:
    %old = atomicrmw or i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -306,7 +306,7 @@ define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_or_i64:
+; CHECK-LABEL: test_atomic_load_or_i64:
    %old = atomicrmw or i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -326,7 +326,7 @@ define i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_xor_i8:
+; CHECK-LABEL: test_atomic_load_xor_i8:
    %old = atomicrmw xor i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -346,7 +346,7 @@ define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_xor_i16:
+; CHECK-LABEL: test_atomic_load_xor_i16:
    %old = atomicrmw xor i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -366,7 +366,7 @@ define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_xor_i32:
+; CHECK-LABEL: test_atomic_load_xor_i32:
    %old = atomicrmw xor i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -386,7 +386,7 @@ define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_xor_i64:
+; CHECK-LABEL: test_atomic_load_xor_i64:
    %old = atomicrmw xor i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -406,7 +406,7 @@ define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_xchg_i8:
+; CHECK-LABEL: test_atomic_load_xchg_i8:
    %old = atomicrmw xchg i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -425,7 +425,7 @@ define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_xchg_i16:
+; CHECK-LABEL: test_atomic_load_xchg_i16:
    %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -444,7 +444,7 @@ define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_xchg_i32:
+; CHECK-LABEL: test_atomic_load_xchg_i32:
    %old = atomicrmw xchg i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -463,7 +463,7 @@ define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_xchg_i64:
+; CHECK-LABEL: test_atomic_load_xchg_i64:
    %old = atomicrmw xchg i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -483,7 +483,7 @@ define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
 
 
 define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_min_i8:
+; CHECK-LABEL: test_atomic_load_min_i8:
    %old = atomicrmw min i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -504,7 +504,7 @@ define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_min_i16:
+; CHECK-LABEL: test_atomic_load_min_i16:
    %old = atomicrmw min i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -525,7 +525,7 @@ define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_min_i32:
+; CHECK-LABEL: test_atomic_load_min_i32:
    %old = atomicrmw min i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -546,7 +546,7 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_min_i64:
+; CHECK-LABEL: test_atomic_load_min_i64:
    %old = atomicrmw min i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -567,7 +567,7 @@ define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_max_i8:
+; CHECK-LABEL: test_atomic_load_max_i8:
    %old = atomicrmw max i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -588,7 +588,7 @@ define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_max_i16:
+; CHECK-LABEL: test_atomic_load_max_i16:
    %old = atomicrmw max i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -609,7 +609,7 @@ define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_max_i32:
+; CHECK-LABEL: test_atomic_load_max_i32:
    %old = atomicrmw max i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -630,7 +630,7 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_max_i64:
+; CHECK-LABEL: test_atomic_load_max_i64:
    %old = atomicrmw max i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -651,7 +651,7 @@ define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_umin_i8:
+; CHECK-LABEL: test_atomic_load_umin_i8:
    %old = atomicrmw umin i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -672,7 +672,7 @@ define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_umin_i16:
+; CHECK-LABEL: test_atomic_load_umin_i16:
    %old = atomicrmw umin i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -693,7 +693,7 @@ define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_umin_i32:
+; CHECK-LABEL: test_atomic_load_umin_i32:
    %old = atomicrmw umin i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -714,7 +714,7 @@ define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_umin_i64:
+; CHECK-LABEL: test_atomic_load_umin_i64:
    %old = atomicrmw umin i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -735,7 +735,7 @@ define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_umax_i8:
+; CHECK-LABEL: test_atomic_load_umax_i8:
    %old = atomicrmw umax i8* @var8, i8 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -756,7 +756,7 @@ define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_umax_i16:
+; CHECK-LABEL: test_atomic_load_umax_i16:
    %old = atomicrmw umax i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -777,7 +777,7 @@ define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_umax_i32:
+; CHECK-LABEL: test_atomic_load_umax_i32:
    %old = atomicrmw umax i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -798,7 +798,7 @@ define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_umax_i64:
+; CHECK-LABEL: test_atomic_load_umax_i64:
    %old = atomicrmw umax i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -819,7 +819,7 @@ define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
-; CHECK: test_atomic_cmpxchg_i8:
+; CHECK-LABEL: test_atomic_cmpxchg_i8:
    %old = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -841,7 +841,7 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
 }
 
 define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
-; CHECK: test_atomic_cmpxchg_i16:
+; CHECK-LABEL: test_atomic_cmpxchg_i16:
    %old = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -863,7 +863,7 @@ define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
 }
 
 define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
-; CHECK: test_atomic_cmpxchg_i32:
+; CHECK-LABEL: test_atomic_cmpxchg_i32:
    %old = cmpxchg i32* @var32, i32 %wanted, i32 %new release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -885,7 +885,7 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
 }
 
 define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
-; CHECK: test_atomic_cmpxchg_i64:
+; CHECK-LABEL: test_atomic_cmpxchg_i64:
    %old = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -907,7 +907,7 @@ define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
 }
 
 define i8 @test_atomic_load_monotonic_i8() nounwind {
-; CHECK: test_atomic_load_monotonic_i8:
+; CHECK-LABEL: test_atomic_load_monotonic_i8:
   %val = load atomic i8* @var8 monotonic, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp x[[HIADDR:[0-9]+]], var8
@@ -918,7 +918,7 @@ define i8 @test_atomic_load_monotonic_i8() nounwind {
 }
 
 define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
-; CHECK: test_atomic_load_monotonic_regoff_i8:
+; CHECK-LABEL: test_atomic_load_monotonic_regoff_i8:
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i8*
 
@@ -931,7 +931,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
 }
 
 define i8 @test_atomic_load_acquire_i8() nounwind {
-; CHECK: test_atomic_load_acquire_i8:
+; CHECK-LABEL: test_atomic_load_acquire_i8:
   %val = load atomic i8* @var8 acquire, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -944,7 +944,7 @@ define i8 @test_atomic_load_acquire_i8() nounwind {
 }
 
 define i8 @test_atomic_load_seq_cst_i8() nounwind {
-; CHECK: test_atomic_load_seq_cst_i8:
+; CHECK-LABEL: test_atomic_load_seq_cst_i8:
   %val = load atomic i8* @var8 seq_cst, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var8
@@ -957,7 +957,7 @@ define i8 @test_atomic_load_seq_cst_i8() nounwind {
 }
 
 define i16 @test_atomic_load_monotonic_i16() nounwind {
-; CHECK: test_atomic_load_monotonic_i16:
+; CHECK-LABEL: test_atomic_load_monotonic_i16:
   %val = load atomic i16* @var16 monotonic, align 2
 ; CHECK-NOT: dmb
 ; CHECK: adrp x[[HIADDR:[0-9]+]], var16
@@ -969,7 +969,7 @@ define i16 @test_atomic_load_monotonic_i16() nounwind {
 }
 
 define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind {
-; CHECK: test_atomic_load_monotonic_regoff_i32:
+; CHECK-LABEL: test_atomic_load_monotonic_regoff_i32:
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i32*
 
@@ -982,7 +982,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind
 }
 
 define i64 @test_atomic_load_seq_cst_i64() nounwind {
-; CHECK: test_atomic_load_seq_cst_i64:
+; CHECK-LABEL: test_atomic_load_seq_cst_i64:
   %val = load atomic i64* @var64 seq_cst, align 8
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var64
@@ -995,7 +995,7 @@ define i64 @test_atomic_load_seq_cst_i64() nounwind {
 }
 
 define void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
-; CHECK: test_atomic_store_monotonic_i8:
+; CHECK-LABEL: test_atomic_store_monotonic_i8:
   store atomic i8 %val, i8* @var8 monotonic, align 1
 ; CHECK: adrp x[[HIADDR:[0-9]+]], var8
 ; CHECK: strb w0, [x[[HIADDR]], #:lo12:var8]
@@ -1004,7 +1004,7 @@ define void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
 }
 
 define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) nounwind {
-; CHECK: test_atomic_store_monotonic_regoff_i8:
+; CHECK-LABEL: test_atomic_store_monotonic_regoff_i8:
 
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i8*
@@ -1015,7 +1015,7 @@ define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val)
   ret void
 }
 define void @test_atomic_store_release_i8(i8 %val) nounwind {
-; CHECK: test_atomic_store_release_i8:
+; CHECK-LABEL: test_atomic_store_release_i8:
   store atomic i8 %val, i8* @var8 release, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var8
@@ -1028,7 +1028,7 @@ define void @test_atomic_store_release_i8(i8 %val) nounwind {
 }
 
 define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
-; CHECK: test_atomic_store_seq_cst_i8:
+; CHECK-LABEL: test_atomic_store_seq_cst_i8:
   store atomic i8 %val, i8* @var8 seq_cst, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var8
@@ -1042,7 +1042,7 @@ define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
 }
 
 define void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
-; CHECK: test_atomic_store_monotonic_i16:
+; CHECK-LABEL: test_atomic_store_monotonic_i16:
   store atomic i16 %val, i16* @var16 monotonic, align 2
 ; CHECK-NOT: dmb
 ; CHECK: adrp x[[HIADDR:[0-9]+]], var16
@@ -1053,7 +1053,7 @@ define void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
 }
 
 define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %val) nounwind {
-; CHECK: test_atomic_store_monotonic_regoff_i32:
+; CHECK-LABEL: test_atomic_store_monotonic_regoff_i32:
 
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i32*
@@ -1067,7 +1067,7 @@ define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %va
 }
 
 define void @test_atomic_store_release_i64(i64 %val) nounwind {
-; CHECK: test_atomic_store_release_i64:
+; CHECK-LABEL: test_atomic_store_release_i64:
   store atomic i64 %val, i64* @var64 release, align 8
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var64
diff --git a/test/CodeGen/AArch64/basic-pic.ll b/test/CodeGen/AArch64/basic-pic.ll
index 5343cc7..1b14be2 100644
--- a/test/CodeGen/AArch64/basic-pic.ll
+++ b/test/CodeGen/AArch64/basic-pic.ll
@@ -6,7 +6,7 @@
 ; CHECK-ELF: RELOCATION RECORDS FOR [.rela.text]
 
 define i32 @get_globalvar() {
-; CHECK: get_globalvar:
+; CHECK-LABEL: get_globalvar:
 
   %val = load i32* @var
 ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
@@ -19,7 +19,7 @@ define i32 @get_globalvar() {
 }
 
 define i32* @get_globalvaraddr() {
-; CHECK: get_globalvaraddr:
+; CHECK-LABEL: get_globalvaraddr:
 
   %val = load i32* @var
 ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
@@ -33,7 +33,7 @@ define i32* @get_globalvaraddr() {
 @hiddenvar = hidden global i32 0
 
 define i32 @get_hiddenvar() {
-; CHECK: get_hiddenvar:
+; CHECK-LABEL: get_hiddenvar:
 
   %val = load i32* @hiddenvar
 ; CHECK: adrp x[[HI:[0-9]+]], hiddenvar
@@ -45,7 +45,7 @@ define i32 @get_hiddenvar() {
 }
 
 define i32* @get_hiddenvaraddr() {
-; CHECK: get_hiddenvaraddr:
+; CHECK-LABEL: get_hiddenvaraddr:
 
   %val = load i32* @hiddenvar
 ; CHECK: adrp [[HI:x[0-9]+]], hiddenvar
@@ -57,7 +57,7 @@ define i32* @get_hiddenvaraddr() {
 }
 
 define void()* @get_func() {
-; CHECK: get_func:
+; CHECK-LABEL: get_func:
 
   ret void()* bitcast(void()*()* @get_func to void()*)
 ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:get_func
@@ -67,4 +67,4 @@ define void()* @get_func() {
   ; it can relax it because it knows where get_func is. It can't!
 ; CHECK-ELF: R_AARCH64_ADR_GOT_PAGE get_func
 ; CHECK-ELF: R_AARCH64_LD64_GOT_LO12_NC get_func
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/AArch64/bitfield-insert-0.ll b/test/CodeGen/AArch64/bitfield-insert-0.ll
index d1191f6..37a18b7 100644
--- a/test/CodeGen/AArch64/bitfield-insert-0.ll
+++ b/test/CodeGen/AArch64/bitfield-insert-0.ll
@@ -16,4 +16,4 @@ define void @test_bfi0(i32* %existing, i32* %new) {
   store volatile i32 %combined, i32* %existing
 
   ret void
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/AArch64/bitfield-insert.ll b/test/CodeGen/AArch64/bitfield-insert.ll
index 3e871b9..1f04608 100644
--- a/test/CodeGen/AArch64/bitfield-insert.ll
+++ b/test/CodeGen/AArch64/bitfield-insert.ll
@@ -6,7 +6,7 @@
 %struct.foo = type { i8, [2 x i8], i8 }
 
 define [1 x i64] @from_clang([1 x i64] %f.coerce, i32 %n) nounwind readnone {
-; CHECK: from_clang:
+; CHECK-LABEL: from_clang:
 ; CHECK: bfi w0, w1, #3, #4
 ; CHECK-NEXT: ret
 
@@ -25,7 +25,7 @@ entry:
 }
 
 define void @test_whole32(i32* %existing, i32* %new) {
-; CHECK: test_whole32:
+; CHECK-LABEL: test_whole32:
 ; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #26, #5
 
   %oldval = load volatile i32* %existing
@@ -42,7 +42,7 @@ define void @test_whole32(i32* %existing, i32* %new) {
 }
 
 define void @test_whole64(i64* %existing, i64* %new) {
-; CHECK: test_whole64:
+; CHECK-LABEL: test_whole64:
 ; CHECK: bfi {{x[0-9]+}}, {{x[0-9]+}}, #26, #14
 ; CHECK-NOT: and
 ; CHECK: ret
@@ -61,7 +61,7 @@ define void @test_whole64(i64* %existing, i64* %new) {
 }
 
 define void @test_whole32_from64(i64* %existing, i64* %new) {
-; CHECK: test_whole32_from64:
+; CHECK-LABEL: test_whole32_from64:
 ; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #{{0|16}}, #16
 ; CHECK-NOT: and
 ; CHECK: ret
@@ -79,7 +79,7 @@ define void @test_whole32_from64(i64* %existing, i64* %new) {
 }
 
 define void @test_32bit_masked(i32 *%existing, i32 *%new) {
-; CHECK: test_32bit_masked:
+; CHECK-LABEL: test_32bit_masked:
 ; CHECK: bfi [[INSERT:w[0-9]+]], {{w[0-9]+}}, #3, #4
 ; CHECK: and {{w[0-9]+}}, [[INSERT]], #0xff
 
@@ -97,7 +97,7 @@ define void @test_32bit_masked(i32 *%existing, i32 *%new) {
 }
 
 define void @test_64bit_masked(i64 *%existing, i64 *%new) {
-; CHECK: test_64bit_masked:
+; CHECK-LABEL: test_64bit_masked:
 ; CHECK: bfi [[INSERT:x[0-9]+]], {{x[0-9]+}}, #40, #8
 ; CHECK: and {{x[0-9]+}}, [[INSERT]], #0xffff00000000
 
@@ -116,7 +116,7 @@ define void @test_64bit_masked(i64 *%existing, i64 *%new) {
 
 ; Mask is too complicated for literal ANDwwi, make sure other avenues are tried.
 define void @test_32bit_complexmask(i32 *%existing, i32 *%new) {
-; CHECK: test_32bit_complexmask:
+; CHECK-LABEL: test_32bit_complexmask:
 ; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4
 ; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
 
@@ -135,7 +135,7 @@ define void @test_32bit_complexmask(i32 *%existing, i32 *%new) {
 
 ; Neither mask is is a contiguous set of 1s. BFI can't be used
 define void @test_32bit_badmask(i32 *%existing, i32 *%new) {
-; CHECK: test_32bit_badmask:
+; CHECK-LABEL: test_32bit_badmask:
 ; CHECK-NOT: bfi
 ; CHECK: ret
 
@@ -154,7 +154,7 @@ define void @test_32bit_badmask(i32 *%existing, i32 *%new) {
 
 ; Ditto
 define void @test_64bit_badmask(i64 *%existing, i64 *%new) {
-; CHECK: test_64bit_badmask:
+; CHECK-LABEL: test_64bit_badmask:
 ; CHECK-NOT: bfi
 ; CHECK: ret
 
@@ -174,7 +174,7 @@ define void @test_64bit_badmask(i64 *%existing, i64 *%new) {
 ; Bitfield insert where there's a left-over shr needed at the beginning
 ; (e.g. result of str.bf1 = str.bf2)
 define void @test_32bit_with_shr(i32* %existing, i32* %new) {
-; CHECK: test_32bit_with_shr:
+; CHECK-LABEL: test_32bit_with_shr:
 
   %oldval = load volatile i32* %existing
   %oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff
diff --git a/test/CodeGen/AArch64/bitfield.ll b/test/CodeGen/AArch64/bitfield.ll
index 36d337e..1c84f5d 100644
--- a/test/CodeGen/AArch64/bitfield.ll
+++ b/test/CodeGen/AArch64/bitfield.ll
@@ -5,7 +5,7 @@
 @var64 = global i64 0
 
 define void @test_extendb(i8 %var) {
-; CHECK: test_extendb:
+; CHECK-LABEL: test_extendb:
 
   %sxt32 = sext i8 %var to i32
   store volatile i32 %sxt32, i32* @var32
@@ -29,7 +29,7 @@ define void @test_extendb(i8 %var) {
 }
 
 define void @test_extendh(i16 %var) {
-; CHECK: test_extendh:
+; CHECK-LABEL: test_extendh:
 
   %sxt32 = sext i16 %var to i32
   store volatile i32 %sxt32, i32* @var32
@@ -53,7 +53,7 @@ define void @test_extendh(i16 %var) {
 }
 
 define void @test_extendw(i32 %var) {
-; CHECK: test_extendw:
+; CHECK-LABEL: test_extendw:
 
   %sxt64 = sext i32 %var to i64
   store volatile i64 %sxt64, i64* @var64
@@ -66,7 +66,7 @@ define void @test_extendw(i32 %var) {
 }
 
 define void @test_shifts(i32 %val32, i64 %val64) {
-; CHECK: test_shifts:
+; CHECK-LABEL: test_shifts:
 
   %shift1 = ashr i32 %val32, 31
   store volatile i32 %shift1, i32* @var32
@@ -114,7 +114,7 @@ define void @test_shifts(i32 %val32, i64 %val64) {
 ; LLVM can produce in-register extensions taking place entirely with
 ; 64-bit registers too.
 define void @test_sext_inreg_64(i64 %in) {
-; CHECK: test_sext_inreg_64:
+; CHECK-LABEL: test_sext_inreg_64:
 
 ; i1 doesn't have an official alias, but crops up and is handled by
 ; the bitfield ops.
@@ -143,7 +143,7 @@ define void @test_sext_inreg_64(i64 %in) {
 ; These instructions don't actually select to official bitfield
 ; operations, but it's important that we select them somehow:
 define void @test_zext_inreg_64(i64 %in) {
-; CHECK: test_zext_inreg_64:
+; CHECK-LABEL: test_zext_inreg_64:
 
   %trunc_i8 = trunc i64 %in to i8
   %zext_i8 = zext i8 %trunc_i8 to i64
@@ -164,7 +164,7 @@ define void @test_zext_inreg_64(i64 %in) {
 }
 
 define i64 @test_sext_inreg_from_32(i32 %in) {
-; CHECK: test_sext_inreg_from_32:
+; CHECK-LABEL: test_sext_inreg_from_32:
 
   %small = trunc i32 %in to i1
   %ext = sext i1 %small to i64
@@ -178,7 +178,7 @@ define i64 @test_sext_inreg_from_32(i32 %in) {
 
 
 define i32 @test_ubfx32(i32* %addr) {
-; CHECK: test_ubfx32:
+; CHECK-LABEL: test_ubfx32:
 ; CHECK: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #23, #3
 
    %fields = load i32* %addr
@@ -188,7 +188,7 @@ define i32 @test_ubfx32(i32* %addr) {
 }
 
 define i64 @test_ubfx64(i64* %addr) {
-; CHECK: test_ubfx64:
+; CHECK-LABEL: test_ubfx64:
 ; CHECK: ubfx {{x[0-9]+}}, {{x[0-9]+}}, #25, #10
 
    %fields = load i64* %addr
@@ -198,7 +198,7 @@ define i64 @test_ubfx64(i64* %addr) {
 }
 
 define i32 @test_sbfx32(i32* %addr) {
-; CHECK: test_sbfx32:
+; CHECK-LABEL: test_sbfx32:
 ; CHECK: sbfx {{w[0-9]+}}, {{w[0-9]+}}, #6, #3
 
    %fields = load i32* %addr
@@ -208,7 +208,7 @@ define i32 @test_sbfx32(i32* %addr) {
 }
 
 define i64 @test_sbfx64(i64* %addr) {
-; CHECK: test_sbfx64:
+; CHECK-LABEL: test_sbfx64:
 ; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #63
 
    %fields = load i64* %addr
diff --git a/test/CodeGen/AArch64/blockaddress.ll b/test/CodeGen/AArch64/blockaddress.ll
index 5e85057..8cda431 100644
--- a/test/CodeGen/AArch64/blockaddress.ll
+++ b/test/CodeGen/AArch64/blockaddress.ll
@@ -4,7 +4,7 @@
 @addr = global i8* null
 
 define void @test_blockaddress() {
-; CHECK: test_blockaddress:
+; CHECK-LABEL: test_blockaddress:
   store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr
   %val = load volatile i8** @addr
   indirectbr i8* %val, [label %block]
diff --git a/test/CodeGen/AArch64/breg.ll b/test/CodeGen/AArch64/breg.ll
index 38ed473..1ed5b9b 100644
--- a/test/CodeGen/AArch64/breg.ll
+++ b/test/CodeGen/AArch64/breg.ll
@@ -3,7 +3,7 @@
 @stored_label = global i8* null
 
 define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
   %lab = load i8** @stored_label
   indirectbr i8* %lab, [label  %otherlab, label %retlab]
 ; CHECK: adrp {{x[0-9]+}}, stored_label
diff --git a/test/CodeGen/AArch64/callee-save.ll b/test/CodeGen/AArch64/callee-save.ll
index c66aa5b..52243b0 100644
--- a/test/CodeGen/AArch64/callee-save.ll
+++ b/test/CodeGen/AArch64/callee-save.ll
@@ -3,7 +3,7 @@
 @var = global float 0.0
 
 define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 
 ; CHECK: stp d14, d15, [sp
 ; CHECK: stp d12, d13, [sp
diff --git a/test/CodeGen/AArch64/code-model-large-abs.ll b/test/CodeGen/AArch64/code-model-large-abs.ll
index a365568..b387f28 100644
--- a/test/CodeGen/AArch64/code-model-large-abs.ll
+++ b/test/CodeGen/AArch64/code-model-large-abs.ll
@@ -6,7 +6,7 @@
 @var64 = global i64 0
 
 define i8* @global_addr() {
-; CHECK: global_addr:
+; CHECK-LABEL: global_addr:
   ret i8* @var8
   ; The movz/movk calculation should end up returned directly in x0.
 ; CHECK: movz x0, #:abs_g3:var8
@@ -17,7 +17,7 @@ define i8* @global_addr() {
 }
 
 define i8 @global_i8() {
-; CHECK: global_i8:
+; CHECK-LABEL: global_i8:
   %val = load i8* @var8
   ret i8 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
@@ -28,7 +28,7 @@ define i8 @global_i8() {
 }
 
 define i16 @global_i16() {
-; CHECK: global_i16:
+; CHECK-LABEL: global_i16:
   %val = load i16* @var16
   ret i16 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
@@ -39,7 +39,7 @@ define i16 @global_i16() {
 }
 
 define i32 @global_i32() {
-; CHECK: global_i32:
+; CHECK-LABEL: global_i32:
   %val = load i32* @var32
   ret i32 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
@@ -50,7 +50,7 @@ define i32 @global_i32() {
 }
 
 define i64 @global_i64() {
-; CHECK: global_i64:
+; CHECK-LABEL: global_i64:
   %val = load i64* @var64
   ret i64 %val
 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
diff --git a/test/CodeGen/AArch64/compare-branch.ll b/test/CodeGen/AArch64/compare-branch.ll
index 4213110..75efd9d 100644
--- a/test/CodeGen/AArch64/compare-branch.ll
+++ b/test/CodeGen/AArch64/compare-branch.ll
@@ -4,7 +4,7 @@
 @var64 = global i64 0
 
 define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 
   %val1 = load volatile i32* @var32
   %tst1 = icmp eq i32 %val1, 0
@@ -35,4 +35,4 @@ test5:
 
 end:
   ret void
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/AArch64/complex-copy-noneon.ll b/test/CodeGen/AArch64/complex-copy-noneon.ll
new file mode 100644
index 0000000..4ae5478
--- /dev/null
+++ b/test/CodeGen/AArch64/complex-copy-noneon.ll
@@ -0,0 +1,21 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=-neon < %s
+
+; The DAG combiner decided to use a vector load/store for this struct copy
+; previously. This probably shouldn't happen without NEON, but the most
+; important thing is that it compiles.
+
+define void @store_combine() nounwind {
+  %src = alloca { double, double }, align 8
+  %dst = alloca { double, double }, align 8
+
+  %src.realp = getelementptr inbounds { double, double }* %src, i32 0, i32 0
+  %src.real = load double* %src.realp
+  %src.imagp = getelementptr inbounds { double, double }* %src, i32 0, i32 1
+  %src.imag = load double* %src.imagp
+
+  %dst.realp = getelementptr inbounds { double, double }* %dst, i32 0, i32 0
+  %dst.imagp = getelementptr inbounds { double, double }* %dst, i32 0, i32 1
+  store double %src.real, double* %dst.realp
+  store double %src.imag, double* %dst.imagp
+  ret void
+}
diff --git a/test/CodeGen/AArch64/cond-sel.ll b/test/CodeGen/AArch64/cond-sel.ll
index 3051cf5..48c50a1 100644
--- a/test/CodeGen/AArch64/cond-sel.ll
+++ b/test/CodeGen/AArch64/cond-sel.ll
@@ -4,7 +4,7 @@
 @var64 = global i64 0
 
 define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
-; CHECK: test_csel:
+; CHECK-LABEL: test_csel:
 
   %tst1 = icmp ugt i32 %lhs32, %rhs32
   %val1 = select i1 %tst1, i32 42, i32 52
@@ -26,7 +26,7 @@ define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
 }
 
 define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %rhs64) {
-; CHECK: test_floatcsel:
+; CHECK-LABEL: test_floatcsel:
 
   %tst1 = fcmp one float %lhs32, %rhs32
 ; CHECK: fcmp {{s[0-9]+}}, {{s[0-9]+}}
@@ -53,7 +53,7 @@ define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %r
 
 
 define void @test_csinc(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
-; CHECK: test_csinc:
+; CHECK-LABEL: test_csinc:
 
 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
   %tst1 = icmp ugt i32 %lhs32, %rhs32
@@ -93,7 +93,7 @@ define void @test_csinc(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
 }
 
 define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
-; CHECK: test_csinv:
+; CHECK-LABEL: test_csinv:
 
 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
   %tst1 = icmp ugt i32 %lhs32, %rhs32
@@ -133,7 +133,7 @@ define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
 }
 
 define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
-; CHECK: test_csneg:
+; CHECK-LABEL: test_csneg:
 
 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
   %tst1 = icmp ugt i32 %lhs32, %rhs32
@@ -173,7 +173,7 @@ define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
 }
 
 define void @test_cset(i32 %lhs, i32 %rhs, i64 %lhs64) {
-; CHECK: test_cset:
+; CHECK-LABEL: test_cset:
 
 ; N.b. code is not optimal here (32-bit csinc would be better) but
 ; incoming DAG is too complex
@@ -194,7 +194,7 @@ define void @test_cset(i32 %lhs, i32 %rhs, i64 %lhs64) {
 }
 
 define void @test_csetm(i32 %lhs, i32 %rhs, i64 %lhs64) {
-; CHECK: test_csetm:
+; CHECK-LABEL: test_csetm:
 
   %tst1 = icmp eq i32 %lhs, %rhs
   %val1 = sext i1 %tst1 to i32
diff --git a/test/CodeGen/AArch64/directcond.ll b/test/CodeGen/AArch64/directcond.ll
index f5d5759..13f032d 100644
--- a/test/CodeGen/AArch64/directcond.ll
+++ b/test/CodeGen/AArch64/directcond.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
 
 define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) {
-; CHECK: test_select_i32:
+; CHECK-LABEL: test_select_i32:
   %val = select i1 %bit, i32 %a, i32 %b
 ; CHECK: movz [[ONE:w[0-9]+]], #1
 ; CHECK: tst w0, [[ONE]]
@@ -11,7 +11,7 @@ define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) {
 }
 
 define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) {
-; CHECK: test_select_i64:
+; CHECK-LABEL: test_select_i64:
   %val = select i1 %bit, i64 %a, i64 %b
 ; CHECK: movz [[ONE:w[0-9]+]], #1
 ; CHECK: tst w0, [[ONE]]
@@ -21,7 +21,7 @@ define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) {
 }
 
 define float @test_select_float(i1 %bit, float %a, float %b) {
-; CHECK: test_select_float:
+; CHECK-LABEL: test_select_float:
   %val = select i1 %bit, float %a, float %b
 ; CHECK: movz [[ONE:w[0-9]+]], #1
 ; CHECK: tst w0, [[ONE]]
@@ -31,7 +31,7 @@ define float @test_select_float(i1 %bit, float %a, float %b) {
 }
 
 define double @test_select_double(i1 %bit, double %a, double %b) {
-; CHECK: test_select_double:
+; CHECK-LABEL: test_select_double:
   %val = select i1 %bit, double %a, double %b
 ; CHECK: movz [[ONE:w[0-9]+]], #1
 ; CHECK: tst w0, [[ONE]]
@@ -41,7 +41,7 @@ define double @test_select_double(i1 %bit, double %a, double %b) {
 }
 
 define i32 @test_brcond(i1 %bit) {
-; CHECK: test_brcond:
+; CHECK-LABEL: test_brcond:
   br i1 %bit, label %true, label %false
 ; CHECK: tbz {{w[0-9]+}}, #0, .LBB
 
diff --git a/test/CodeGen/AArch64/dp-3source.ll b/test/CodeGen/AArch64/dp-3source.ll
index c40d393..81d9e15 100644
--- a/test/CodeGen/AArch64/dp-3source.ll
+++ b/test/CodeGen/AArch64/dp-3source.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
 
 define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) {
-; CHECK: test_madd32:
+; CHECK-LABEL: test_madd32:
   %mid = mul i32 %val1, %val2
   %res = add i32 %val0, %mid
 ; CHECK: madd {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
@@ -9,7 +9,7 @@ define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) {
 }
 
 define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) {
-; CHECK: test_madd64:
+; CHECK-LABEL: test_madd64:
   %mid = mul i64 %val1, %val2
   %res = add i64 %val0, %mid
 ; CHECK: madd {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
@@ -17,7 +17,7 @@ define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) {
 }
 
 define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) {
-; CHECK: test_msub32:
+; CHECK-LABEL: test_msub32:
   %mid = mul i32 %val1, %val2
   %res = sub i32 %val0, %mid
 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
@@ -25,7 +25,7 @@ define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) {
 }
 
 define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) {
-; CHECK: test_msub64:
+; CHECK-LABEL: test_msub64:
   %mid = mul i64 %val1, %val2
   %res = sub i64 %val0, %mid
 ; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
@@ -33,7 +33,7 @@ define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) {
 }
 
 define i64 @test_smaddl(i64 %acc, i32 %val1, i32 %val2) {
-; CHECK: test_smaddl:
+; CHECK-LABEL: test_smaddl:
   %ext1 = sext i32 %val1 to i64
   %ext2 = sext i32 %val2 to i64
   %prod = mul i64 %ext1, %ext2
@@ -43,7 +43,7 @@ define i64 @test_smaddl(i64 %acc, i32 %val1, i32 %val2) {
 }
 
 define i64 @test_smsubl(i64 %acc, i32 %val1, i32 %val2) {
-; CHECK: test_smsubl:
+; CHECK-LABEL: test_smsubl:
   %ext1 = sext i32 %val1 to i64
   %ext2 = sext i32 %val2 to i64
   %prod = mul i64 %ext1, %ext2
@@ -53,7 +53,7 @@ define i64 @test_smsubl(i64 %acc, i32 %val1, i32 %val2) {
 }
 
 define i64 @test_umaddl(i64 %acc, i32 %val1, i32 %val2) {
-; CHECK: test_umaddl:
+; CHECK-LABEL: test_umaddl:
   %ext1 = zext i32 %val1 to i64
   %ext2 = zext i32 %val2 to i64
   %prod = mul i64 %ext1, %ext2
@@ -63,7 +63,7 @@ define i64 @test_umaddl(i64 %acc, i32 %val1, i32 %val2) {
 }
 
 define i64 @test_umsubl(i64 %acc, i32 %val1, i32 %val2) {
-; CHECK: test_umsubl:
+; CHECK-LABEL: test_umsubl:
   %ext1 = zext i32 %val1 to i64
   %ext2 = zext i32 %val2 to i64
   %prod = mul i64 %ext1, %ext2
@@ -73,7 +73,7 @@ define i64 @test_umsubl(i64 %acc, i32 %val1, i32 %val2) {
 }
 
 define i64 @test_smulh(i64 %lhs, i64 %rhs) {
-; CHECK: test_smulh:
+; CHECK-LABEL: test_smulh:
   %ext1 = sext i64 %lhs to i128
   %ext2 = sext i64 %rhs to i128
   %res = mul i128 %ext1, %ext2
@@ -84,7 +84,7 @@ define i64 @test_smulh(i64 %lhs, i64 %rhs) {
 }
 
 define i64 @test_umulh(i64 %lhs, i64 %rhs) {
-; CHECK: test_umulh:
+; CHECK-LABEL: test_umulh:
   %ext1 = zext i64 %lhs to i128
   %ext2 = zext i64 %rhs to i128
   %res = mul i128 %ext1, %ext2
@@ -95,21 +95,21 @@ define i64 @test_umulh(i64 %lhs, i64 %rhs) {
 }
 
 define i32 @test_mul32(i32 %lhs, i32 %rhs) {
-; CHECK: test_mul32:
+; CHECK-LABEL: test_mul32:
   %res = mul i32 %lhs, %rhs
 ; CHECK: mul {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
   ret i32 %res
 }
 
 define i64 @test_mul64(i64 %lhs, i64 %rhs) {
-; CHECK: test_mul64:
+; CHECK-LABEL: test_mul64:
   %res = mul i64 %lhs, %rhs
 ; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
   ret i64 %res
 }
 
 define i32 @test_mneg32(i32 %lhs, i32 %rhs) {
-; CHECK: test_mneg32:
+; CHECK-LABEL: test_mneg32:
   %prod = mul i32 %lhs, %rhs
   %res = sub i32 0, %prod
 ; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
@@ -117,7 +117,7 @@ define i32 @test_mneg32(i32 %lhs, i32 %rhs) {
 }
 
 define i64 @test_mneg64(i64 %lhs, i64 %rhs) {
-; CHECK: test_mneg64:
+; CHECK-LABEL: test_mneg64:
   %prod = mul i64 %lhs, %rhs
   %res = sub i64 0, %prod
 ; CHECK: mneg {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
@@ -125,7 +125,7 @@ define i64 @test_mneg64(i64 %lhs, i64 %rhs) {
 }
 
 define i64 @test_smull(i32 %lhs, i32 %rhs) {
-; CHECK: test_smull:
+; CHECK-LABEL: test_smull:
   %ext1 = sext i32 %lhs to i64
   %ext2 = sext i32 %rhs to i64
   %res = mul i64 %ext1, %ext2
@@ -134,7 +134,7 @@ define i64 @test_smull(i32 %lhs, i32 %rhs) {
 }
 
 define i64 @test_umull(i32 %lhs, i32 %rhs) {
-; CHECK: test_umull:
+; CHECK-LABEL: test_umull:
   %ext1 = zext i32 %lhs to i64
   %ext2 = zext i32 %rhs to i64
   %res = mul i64 %ext1, %ext2
@@ -143,7 +143,7 @@ define i64 @test_umull(i32 %lhs, i32 %rhs) {
 }
 
 define i64 @test_smnegl(i32 %lhs, i32 %rhs) {
-; CHECK: test_smnegl:
+; CHECK-LABEL: test_smnegl:
   %ext1 = sext i32 %lhs to i64
   %ext2 = sext i32 %rhs to i64
   %prod = mul i64 %ext1, %ext2
@@ -153,7 +153,7 @@ define i64 @test_smnegl(i32 %lhs, i32 %rhs) {
 }
 
 define i64 @test_umnegl(i32 %lhs, i32 %rhs) {
-; CHECK: test_umnegl:
+; CHECK-LABEL: test_umnegl:
   %ext1 = zext i32 %lhs to i64
   %ext2 = zext i32 %rhs to i64
   %prod = mul i64 %ext1, %ext2
diff --git a/test/CodeGen/AArch64/dp1.ll b/test/CodeGen/AArch64/dp1.ll
index 83aa8b4..6a8d55c 100644
--- a/test/CodeGen/AArch64/dp1.ll
+++ b/test/CodeGen/AArch64/dp1.ll
@@ -4,7 +4,7 @@
 @var64 = global i64 0
 
 define void @rev_i32() {
-; CHECK: rev_i32:
+; CHECK-LABEL: rev_i32:
     %val0_tmp = load i32* @var32
     %val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)
 ; CHECK: rev	{{w[0-9]+}}, {{w[0-9]+}}
@@ -13,7 +13,7 @@ define void @rev_i32() {
 }
 
 define void @rev_i64() {
-; CHECK: rev_i64:
+; CHECK-LABEL: rev_i64:
     %val0_tmp = load i64* @var64
     %val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)
 ; CHECK: rev	{{x[0-9]+}}, {{x[0-9]+}}
@@ -22,7 +22,7 @@ define void @rev_i64() {
 }
 
 define void @rev32_i64() {
-; CHECK: rev32_i64:
+; CHECK-LABEL: rev32_i64:
     %val0_tmp = load i64* @var64
     %val1_tmp = shl i64 %val0_tmp, 32
     %val5_tmp = sub i64 64, 32
@@ -35,7 +35,7 @@ define void @rev32_i64() {
 }
 
 define void @rev16_i32() {
-; CHECK: rev16_i32:
+; CHECK-LABEL: rev16_i32:
     %val0_tmp = load i32* @var32
     %val1_tmp = shl i32 %val0_tmp, 16
     %val2_tmp = lshr i32 %val0_tmp, 16
@@ -47,7 +47,7 @@ define void @rev16_i32() {
 }
 
 define void @clz_zerodef_i32() {
-; CHECK: clz_zerodef_i32:
+; CHECK-LABEL: clz_zerodef_i32:
     %val0_tmp = load i32* @var32
     %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0)
 ; CHECK: clz	{{w[0-9]+}}, {{w[0-9]+}}
@@ -56,7 +56,7 @@ define void @clz_zerodef_i32() {
 }
 
 define void @clz_zerodef_i64() {
-; CHECK: clz_zerodef_i64:
+; CHECK-LABEL: clz_zerodef_i64:
     %val0_tmp = load i64* @var64
     %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0)
 ; CHECK: clz	{{x[0-9]+}}, {{x[0-9]+}}
@@ -65,7 +65,7 @@ define void @clz_zerodef_i64() {
 }
 
 define void @clz_zeroundef_i32() {
-; CHECK: clz_zeroundef_i32:
+; CHECK-LABEL: clz_zeroundef_i32:
     %val0_tmp = load i32* @var32
     %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1)
 ; CHECK: clz	{{w[0-9]+}}, {{w[0-9]+}}
@@ -74,7 +74,7 @@ define void @clz_zeroundef_i32() {
 }
 
 define void @clz_zeroundef_i64() {
-; CHECK: clz_zeroundef_i64:
+; CHECK-LABEL: clz_zeroundef_i64:
     %val0_tmp = load i64* @var64
     %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1)
 ; CHECK: clz	{{x[0-9]+}}, {{x[0-9]+}}
@@ -83,7 +83,7 @@ define void @clz_zeroundef_i64() {
 }
 
 define void @cttz_zerodef_i32() {
-; CHECK: cttz_zerodef_i32:
+; CHECK-LABEL: cttz_zerodef_i32:
     %val0_tmp = load i32* @var32
     %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0)
 ; CHECK: rbit   [[REVERSED:w[0-9]+]], {{w[0-9]+}}
@@ -93,7 +93,7 @@ define void @cttz_zerodef_i32() {
 }
 
 define void @cttz_zerodef_i64() {
-; CHECK: cttz_zerodef_i64:
+; CHECK-LABEL: cttz_zerodef_i64:
     %val0_tmp = load i64* @var64
     %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0)
 ; CHECK: rbit   [[REVERSED:x[0-9]+]], {{x[0-9]+}}
@@ -103,7 +103,7 @@ define void @cttz_zerodef_i64() {
 }
 
 define void @cttz_zeroundef_i32() {
-; CHECK: cttz_zeroundef_i32:
+; CHECK-LABEL: cttz_zeroundef_i32:
     %val0_tmp = load i32* @var32
     %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1)
 ; CHECK: rbit   [[REVERSED:w[0-9]+]], {{w[0-9]+}}
@@ -113,7 +113,7 @@ define void @cttz_zeroundef_i32() {
 }
 
 define void @cttz_zeroundef_i64() {
-; CHECK: cttz_zeroundef_i64:
+; CHECK-LABEL: cttz_zeroundef_i64:
     %val0_tmp = load i64* @var64
     %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1)
 ; CHECK: rbit   [[REVERSED:x[0-9]+]], {{x[0-9]+}}
@@ -125,7 +125,7 @@ define void @cttz_zeroundef_i64() {
 ; These two are just compilation tests really: the operation's set to Expand in
 ; ISelLowering.
 define void @ctpop_i32() {
-; CHECK: ctpop_i32:
+; CHECK-LABEL: ctpop_i32:
     %val0_tmp = load i32* @var32
     %val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp)
     store volatile i32 %val4_tmp, i32* @var32
@@ -133,7 +133,7 @@ define void @ctpop_i32() {
 }
 
 define void @ctpop_i64() {
-; CHECK: ctpop_i64:
+; CHECK-LABEL: ctpop_i64:
     %val0_tmp = load i64* @var64
     %val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp)
     store volatile i64 %val4_tmp, i64* @var64
diff --git a/test/CodeGen/AArch64/dp2.ll b/test/CodeGen/AArch64/dp2.ll
index 4c740f6..48b0701 100644
--- a/test/CodeGen/AArch64/dp2.ll
+++ b/test/CodeGen/AArch64/dp2.ll
@@ -6,7 +6,7 @@
 @var64_1 = global i64 0
 
 define void @rorv_i64() {
-; CHECK: rorv_i64:
+; CHECK-LABEL: rorv_i64:
     %val0_tmp = load i64* @var64_0
     %val1_tmp = load i64* @var64_1
     %val2_tmp = sub i64 64, %val1_tmp
@@ -19,7 +19,7 @@ define void @rorv_i64() {
 }
 
 define void @asrv_i64() {
-; CHECK: asrv_i64:
+; CHECK-LABEL: asrv_i64:
     %val0_tmp = load i64* @var64_0
     %val1_tmp = load i64* @var64_1
     %val4_tmp = ashr i64 %val0_tmp, %val1_tmp
@@ -29,7 +29,7 @@ define void @asrv_i64() {
 }
 
 define void @lsrv_i64() {
-; CHECK: lsrv_i64:
+; CHECK-LABEL: lsrv_i64:
     %val0_tmp = load i64* @var64_0
     %val1_tmp = load i64* @var64_1
     %val4_tmp = lshr i64 %val0_tmp, %val1_tmp
@@ -39,7 +39,7 @@ define void @lsrv_i64() {
 }
 
 define void @lslv_i64() {
-; CHECK: lslv_i64:
+; CHECK-LABEL: lslv_i64:
     %val0_tmp = load i64* @var64_0
     %val1_tmp = load i64* @var64_1
     %val4_tmp = shl i64 %val0_tmp, %val1_tmp
@@ -49,7 +49,7 @@ define void @lslv_i64() {
 }
 
 define void @udiv_i64() {
-; CHECK: udiv_i64:
+; CHECK-LABEL: udiv_i64:
     %val0_tmp = load i64* @var64_0
     %val1_tmp = load i64* @var64_1
     %val4_tmp = udiv i64 %val0_tmp, %val1_tmp
@@ -59,7 +59,7 @@ define void @udiv_i64() {
 }
 
 define void @sdiv_i64() {
-; CHECK: sdiv_i64:
+; CHECK-LABEL: sdiv_i64:
     %val0_tmp = load i64* @var64_0
     %val1_tmp = load i64* @var64_1
     %val4_tmp = sdiv i64 %val0_tmp, %val1_tmp
@@ -70,7 +70,7 @@ define void @sdiv_i64() {
 
 
 define void @lsrv_i32() {
-; CHECK: lsrv_i32:
+; CHECK-LABEL: lsrv_i32:
     %val0_tmp = load i32* @var32_0
     %val1_tmp = load i32* @var32_1
     %val2_tmp = add i32 1, %val1_tmp
@@ -81,7 +81,7 @@ define void @lsrv_i32() {
 }
 
 define void @lslv_i32() {
-; CHECK: lslv_i32:
+; CHECK-LABEL: lslv_i32:
     %val0_tmp = load i32* @var32_0
     %val1_tmp = load i32* @var32_1
     %val2_tmp = add i32 1, %val1_tmp
@@ -92,7 +92,7 @@ define void @lslv_i32() {
 }
 
 define void @rorv_i32() {
-; CHECK: rorv_i32:
+; CHECK-LABEL: rorv_i32:
     %val0_tmp = load i32* @var32_0
     %val6_tmp = load i32* @var32_1
     %val1_tmp = add i32 1, %val6_tmp
@@ -106,7 +106,7 @@ define void @rorv_i32() {
 }
 
 define void @asrv_i32() {
-; CHECK: asrv_i32:
+; CHECK-LABEL: asrv_i32:
     %val0_tmp = load i32* @var32_0
     %val1_tmp = load i32* @var32_1
     %val2_tmp = add i32 1, %val1_tmp
@@ -117,7 +117,7 @@ define void @asrv_i32() {
 }
 
 define void @sdiv_i32() {
-; CHECK: sdiv_i32:
+; CHECK-LABEL: sdiv_i32:
     %val0_tmp = load i32* @var32_0
     %val1_tmp = load i32* @var32_1
     %val4_tmp = sdiv i32 %val0_tmp, %val1_tmp
@@ -127,7 +127,7 @@ define void @sdiv_i32() {
 }
 
 define void @udiv_i32() {
-; CHECK: udiv_i32:
+; CHECK-LABEL: udiv_i32:
     %val0_tmp = load i32* @var32_0
     %val1_tmp = load i32* @var32_1
     %val4_tmp = udiv i32 %val0_tmp, %val1_tmp
@@ -139,7 +139,7 @@ define void @udiv_i32() {
 ; The point of this test is that we may not actually see (shl GPR32:$Val, (zext GPR32:$Val2))
 ; in the DAG (the RHS may be natively 64-bit), but we should still use the lsl instructions.
 define i32 @test_lsl32() {
-; CHECK: test_lsl32:
+; CHECK-LABEL: test_lsl32:
 
   %val = load i32* @var32_0
   %ret = shl i32 1, %val
@@ -149,7 +149,7 @@ define i32 @test_lsl32() {
 }
 
 define i32 @test_lsr32() {
-; CHECK: test_lsr32:
+; CHECK-LABEL: test_lsr32:
 
   %val = load i32* @var32_0
   %ret = lshr i32 1, %val
@@ -159,7 +159,7 @@ define i32 @test_lsr32() {
 }
 
 define i32 @test_asr32(i32 %in) {
-; CHECK: test_asr32:
+; CHECK-LABEL: test_asr32:
 
   %val = load i32* @var32_0
   %ret = ashr i32 %in, %val
diff --git a/test/CodeGen/AArch64/extern-weak.ll b/test/CodeGen/AArch64/extern-weak.ll
index bc0acc2..322b3f4 100644
--- a/test/CodeGen/AArch64/extern-weak.ll
+++ b/test/CodeGen/AArch64/extern-weak.ll
@@ -51,4 +51,4 @@ define i32* @wibble() {
 ; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
 ; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var
 ; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/AArch64/extract.ll b/test/CodeGen/AArch64/extract.ll
index 0626781..62d9ed2 100644
--- a/test/CodeGen/AArch64/extract.ll
+++ b/test/CodeGen/AArch64/extract.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
 
 define i64 @ror_i64(i64 %in) {
-; CHECK: ror_i64:
+; CHECK-LABEL: ror_i64:
     %left = shl i64 %in, 19
     %right = lshr i64 %in, 45
     %val5 = or i64 %left, %right
@@ -10,7 +10,7 @@ define i64 @ror_i64(i64 %in) {
 }
 
 define i32 @ror_i32(i32 %in) {
-; CHECK: ror_i32:
+; CHECK-LABEL: ror_i32:
     %left = shl i32 %in, 9
     %right = lshr i32 %in, 23
     %val5 = or i32 %left, %right
@@ -19,7 +19,7 @@ define i32 @ror_i32(i32 %in) {
 }
 
 define i32 @extr_i32(i32 %lhs, i32 %rhs) {
-; CHECK: extr_i32:
+; CHECK-LABEL: extr_i32:
   %left = shl i32 %lhs, 6
   %right = lshr i32 %rhs, 26
   %val = or i32 %left, %right
@@ -31,7 +31,7 @@ define i32 @extr_i32(i32 %lhs, i32 %rhs) {
 }
 
 define i64 @extr_i64(i64 %lhs, i64 %rhs) {
-; CHECK: extr_i64:
+; CHECK-LABEL: extr_i64:
   %right = lshr i64 %rhs, 40
   %left = shl i64 %lhs, 24
   %val = or i64 %right, %left
@@ -45,7 +45,7 @@ define i64 @extr_i64(i64 %lhs, i64 %rhs) {
 ; Regression test: a bad experimental pattern crept into git which optimised
 ; this pattern to a single EXTR.
 define i32 @extr_regress(i32 %a, i32 %b) {
-; CHECK: extr_regress:
+; CHECK-LABEL: extr_regress:
 
     %sh1 = shl i32 %a, 14
     %sh2 = lshr i32 %b, 14
diff --git a/test/CodeGen/AArch64/fastcc-reserved.ll b/test/CodeGen/AArch64/fastcc-reserved.ll
index e40aa30..c6c0505 100644
--- a/test/CodeGen/AArch64/fastcc-reserved.ll
+++ b/test/CodeGen/AArch64/fastcc-reserved.ll
@@ -7,7 +7,7 @@
 declare fastcc void @will_pop([8 x i32], i32 %val)
 
 define fastcc void @foo(i32 %in) {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 
   %addr = alloca i8, i32 %in
 
@@ -34,7 +34,7 @@ define fastcc void @foo(i32 %in) {
 declare void @wont_pop([8 x i32], i32 %val)
 
 define void @foo1(i32 %in) {
-; CHECK: foo1:
+; CHECK-LABEL: foo1:
 
   %addr = alloca i8, i32 %in
 ; Normal frame setup again
diff --git a/test/CodeGen/AArch64/fastcc.ll b/test/CodeGen/AArch64/fastcc.ll
index 41cde94..a4cd378 100644
--- a/test/CodeGen/AArch64/fastcc.ll
+++ b/test/CodeGen/AArch64/fastcc.ll
@@ -5,10 +5,10 @@
 ; stack, so try to make sure this is respected.
 
 define fastcc void @func_stack0() {
-; CHECK: func_stack0:
+; CHECK-LABEL: func_stack0:
 ; CHECK: sub sp, sp, #48
 
-; CHECK-TAIL: func_stack0:
+; CHECK-TAIL-LABEL: func_stack0:
 ; CHECK-TAIL: sub sp, sp, #48
 
 
@@ -45,10 +45,10 @@ define fastcc void @func_stack0() {
 }
 
 define fastcc void @func_stack8([8 x i32], i32 %stacked) {
-; CHECK: func_stack8:
+; CHECK-LABEL: func_stack8:
 ; CHECK: sub sp, sp, #48
 
-; CHECK-TAIL: func_stack8:
+; CHECK-TAIL-LABEL: func_stack8:
 ; CHECK-TAIL: sub sp, sp, #48
 
 
@@ -84,10 +84,10 @@ define fastcc void @func_stack8([8 x i32], i32 %stacked) {
 }
 
 define fastcc void @func_stack32([8 x i32], i128 %stacked0, i128 %stacked1) {
-; CHECK: func_stack32:
+; CHECK-LABEL: func_stack32:
 ; CHECK: sub sp, sp, #48
 
-; CHECK-TAIL: func_stack32:
+; CHECK-TAIL-LABEL: func_stack32:
 ; CHECK-TAIL: sub sp, sp, #48
 
 
diff --git a/test/CodeGen/AArch64/fcmp.ll b/test/CodeGen/AArch64/fcmp.ll
index ad4a903..a9518ea 100644
--- a/test/CodeGen/AArch64/fcmp.ll
+++ b/test/CodeGen/AArch64/fcmp.ll
@@ -3,7 +3,7 @@
 declare void @bar(i32)
 
 define void @test_float(float %a, float %b) {
-; CHECK: test_float:
+; CHECK-LABEL: test_float:
 
   %tst1 = fcmp oeq float %a, %b
   br i1 %tst1, label %end, label %t2
@@ -42,7 +42,7 @@ end:
 }
 
 define void @test_double(double %a, double %b) {
-; CHECK: test_double:
+; CHECK-LABEL: test_double:
 
   %tst1 = fcmp oeq double %a, %b
   br i1 %tst1, label %end, label %t2
diff --git a/test/CodeGen/AArch64/fcvt-fixed.ll b/test/CodeGen/AArch64/fcvt-fixed.ll
index 0f7b95b..9d66da4 100644
--- a/test/CodeGen/AArch64/fcvt-fixed.ll
+++ b/test/CodeGen/AArch64/fcvt-fixed.ll
@@ -4,7 +4,7 @@
 @var64 = global i64 0
 
 define void @test_fcvtzs(float %flt, double %dbl) {
-; CHECK: test_fcvtzs:
+; CHECK-LABEL: test_fcvtzs:
 
   %fix1 = fmul float %flt, 128.0
   %cvt1 = fptosi float %fix1 to i32
@@ -50,7 +50,7 @@ define void @test_fcvtzs(float %flt, double %dbl) {
 }
 
 define void @test_fcvtzu(float %flt, double %dbl) {
-; CHECK: test_fcvtzu:
+; CHECK-LABEL: test_fcvtzu:
 
   %fix1 = fmul float %flt, 128.0
   %cvt1 = fptoui float %fix1 to i32
@@ -99,7 +99,7 @@ define void @test_fcvtzu(float %flt, double %dbl) {
 @vardouble = global double 0.0
 
 define void @test_scvtf(i32 %int, i64 %long) {
-; CHECK: test_scvtf:
+; CHECK-LABEL: test_scvtf:
 
   %cvt1 = sitofp i32 %int to float
   %fix1 = fdiv float %cvt1, 128.0
@@ -145,7 +145,7 @@ define void @test_scvtf(i32 %int, i64 %long) {
 }
 
 define void @test_ucvtf(i32 %int, i64 %long) {
-; CHECK: test_ucvtf:
+; CHECK-LABEL: test_ucvtf:
 
   %cvt1 = uitofp i32 %int to float
   %fix1 = fdiv float %cvt1, 128.0
diff --git a/test/CodeGen/AArch64/fcvt-int.ll b/test/CodeGen/AArch64/fcvt-int.ll
index c771d68..9afcfc4 100644
--- a/test/CodeGen/AArch64/fcvt-int.ll
+++ b/test/CodeGen/AArch64/fcvt-int.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
 
 define i32 @test_floattoi32(float %in) {
-; CHECK: test_floattoi32:
+; CHECK-LABEL: test_floattoi32:
 
   %signed = fptosi float %in to i32
   %unsigned = fptoui float %in to i32
@@ -16,7 +16,7 @@ define i32 @test_floattoi32(float %in) {
 }
 
 define i32 @test_doubletoi32(double %in) {
-; CHECK: test_doubletoi32:
+; CHECK-LABEL: test_doubletoi32:
 
   %signed = fptosi double %in to i32
   %unsigned = fptoui double %in to i32
@@ -31,7 +31,7 @@ define i32 @test_doubletoi32(double %in) {
 }
 
 define i64 @test_floattoi64(float %in) {
-; CHECK: test_floattoi64:
+; CHECK-LABEL: test_floattoi64:
 
   %signed = fptosi float %in to i64
   %unsigned = fptoui float %in to i64
@@ -46,7 +46,7 @@ define i64 @test_floattoi64(float %in) {
 }
 
 define i64 @test_doubletoi64(double %in) {
-; CHECK: test_doubletoi64:
+; CHECK-LABEL: test_doubletoi64:
 
   %signed = fptosi double %in to i64
   %unsigned = fptoui double %in to i64
@@ -61,7 +61,7 @@ define i64 @test_doubletoi64(double %in) {
 }
 
 define float @test_i32tofloat(i32 %in) {
-; CHECK: test_i32tofloat:
+; CHECK-LABEL: test_i32tofloat:
 
   %signed = sitofp i32 %in to float
   %unsigned = uitofp i32 %in to float
@@ -75,7 +75,7 @@ define float @test_i32tofloat(i32 %in) {
 }
 
 define double @test_i32todouble(i32 %in) {
-; CHECK: test_i32todouble:
+; CHECK-LABEL: test_i32todouble:
 
   %signed = sitofp i32 %in to double
   %unsigned = uitofp i32 %in to double
@@ -89,7 +89,7 @@ define double @test_i32todouble(i32 %in) {
 }
 
 define float @test_i64tofloat(i64 %in) {
-; CHECK: test_i64tofloat:
+; CHECK-LABEL: test_i64tofloat:
 
   %signed = sitofp i64 %in to float
   %unsigned = uitofp i64 %in to float
@@ -103,7 +103,7 @@ define float @test_i64tofloat(i64 %in) {
 }
 
 define double @test_i64todouble(i64 %in) {
-; CHECK: test_i64todouble:
+; CHECK-LABEL: test_i64todouble:
 
   %signed = sitofp i64 %in to double
   %unsigned = uitofp i64 %in to double
@@ -117,7 +117,7 @@ define double @test_i64todouble(i64 %in) {
 }
 
 define i32 @test_bitcastfloattoi32(float %in) {
-; CHECK: test_bitcastfloattoi32:
+; CHECK-LABEL: test_bitcastfloattoi32:
 
    %res = bitcast float %in to i32
 ; CHECK: fmov {{w[0-9]+}}, {{s[0-9]+}}
@@ -125,7 +125,7 @@ define i32 @test_bitcastfloattoi32(float %in) {
 }
 
 define i64 @test_bitcastdoubletoi64(double %in) {
-; CHECK: test_bitcastdoubletoi64:
+; CHECK-LABEL: test_bitcastdoubletoi64:
 
    %res = bitcast double %in to i64
 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
@@ -133,7 +133,7 @@ define i64 @test_bitcastdoubletoi64(double %in) {
 }
 
 define float @test_bitcasti32tofloat(i32 %in) {
-; CHECK: test_bitcasti32tofloat:
+; CHECK-LABEL: test_bitcasti32tofloat:
 
    %res = bitcast i32 %in to float
 ; CHECK: fmov {{s[0-9]+}}, {{w[0-9]+}}
@@ -142,7 +142,7 @@ define float @test_bitcasti32tofloat(i32 %in) {
 }
 
 define double @test_bitcasti64todouble(i64 %in) {
-; CHECK: test_bitcasti64todouble:
+; CHECK-LABEL: test_bitcasti64todouble:
 
    %res = bitcast i64 %in to double
 ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
diff --git a/test/CodeGen/AArch64/flags-multiuse.ll b/test/CodeGen/AArch64/flags-multiuse.ll
index 940c146..e99c728 100644
--- a/test/CodeGen/AArch64/flags-multiuse.ll
+++ b/test/CodeGen/AArch64/flags-multiuse.ll
@@ -9,7 +9,7 @@ declare void @bar()
 @var = global i32 0
 
 define i32 @test_multiflag(i32 %n, i32 %m, i32 %o) {
-; CHECK: test_multiflag:
+; CHECK-LABEL: test_multiflag:
 
   %test = icmp ne i32 %n, %m
 ; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
diff --git a/test/CodeGen/AArch64/floatdp_1source.ll b/test/CodeGen/AArch64/floatdp_1source.ll
index c94ba9b..3d7f8f0 100644
--- a/test/CodeGen/AArch64/floatdp_1source.ll
+++ b/test/CodeGen/AArch64/floatdp_1source.ll
@@ -26,7 +26,7 @@ declare float @nearbyintf(float) readonly
 declare double @nearbyint(double) readonly
 
 define void @simple_float() {
-; CHECK: simple_float:
+; CHECK-LABEL: simple_float:
   %val1 = load volatile float* @varfloat
 
   %valabs = call float @fabsf(float %val1)
@@ -65,7 +65,7 @@ define void @simple_float() {
 }
 
 define void @simple_double() {
-; CHECK: simple_double:
+; CHECK-LABEL: simple_double:
   %val1 = load volatile double* @vardouble
 
   %valabs = call double @fabs(double %val1)
@@ -104,7 +104,7 @@ define void @simple_double() {
 }
 
 define void @converts() {
-; CHECK: converts:
+; CHECK-LABEL: converts:
 
   %val16 = load volatile half* @varhalf
   %val32 = load volatile float* @varfloat
diff --git a/test/CodeGen/AArch64/floatdp_2source.ll b/test/CodeGen/AArch64/floatdp_2source.ll
index b2256b3..bb65528 100644
--- a/test/CodeGen/AArch64/floatdp_2source.ll
+++ b/test/CodeGen/AArch64/floatdp_2source.ll
@@ -4,7 +4,7 @@
 @vardouble = global double 0.0
 
 define void @testfloat() {
-; CHECK: testfloat:
+; CHECK-LABEL: testfloat:
   %val1 = load float* @varfloat
 
   %val2 = fadd float %val1, %val1
@@ -32,7 +32,7 @@ define void @testfloat() {
 }
 
 define void @testdouble() {
-; CHECK: testdouble:
+; CHECK-LABEL: testdouble:
   %val1 = load double* @vardouble
 
   %val2 = fadd double %val1, %val1
diff --git a/test/CodeGen/AArch64/fp-cond-sel.ll b/test/CodeGen/AArch64/fp-cond-sel.ll
index 56e8f16..572f42e 100644
--- a/test/CodeGen/AArch64/fp-cond-sel.ll
+++ b/test/CodeGen/AArch64/fp-cond-sel.ll
@@ -4,7 +4,7 @@
 @vardouble = global double 0.0
 
 define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
-; CHECK: test_csel:
+; CHECK-LABEL: test_csel:
 
   %tst1 = icmp ugt i32 %lhs32, %rhs32
   %val1 = select i1 %tst1, float 0.0, float 1.0
diff --git a/test/CodeGen/AArch64/fp-dp3.ll b/test/CodeGen/AArch64/fp-dp3.ll
index 39db9be..3a9a6fc 100644
--- a/test/CodeGen/AArch64/fp-dp3.ll
+++ b/test/CodeGen/AArch64/fp-dp3.ll
@@ -1,102 +1,136 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -fp-contract=fast | FileCheck %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s -check-prefix=CHECK-NOFAST
 
 declare float @llvm.fma.f32(float, float, float)
 declare double @llvm.fma.f64(double, double, double)
 
 define float @test_fmadd(float %a, float %b, float %c) {
-; CHECK: test_fmadd:
+; CHECK-LABEL: test_fmadd:
+; CHECK-NOFAST-LABEL: test_fmadd:
   %val = call float @llvm.fma.f32(float %a, float %b, float %c)
 ; CHECK: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
   ret float %val
 }
 
 define float @test_fmsub(float %a, float %b, float %c) {
-; CHECK: test_fmsub:
+; CHECK-LABEL: test_fmsub:
+; CHECK-NOFAST-LABEL: test_fmsub:
   %nega = fsub float -0.0, %a
   %val = call float @llvm.fma.f32(float %nega, float %b, float %c)
 ; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
   ret float %val
 }
 
 define float @test_fnmadd(float %a, float %b, float %c) {
-; CHECK: test_fnmadd:
+; CHECK-LABEL: test_fnmadd:
+; CHECK-NOFAST-LABEL: test_fnmadd:
   %negc = fsub float -0.0, %c
   %val = call float @llvm.fma.f32(float %a, float %b, float %negc)
 ; CHECK: fnmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST: fnmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
   ret float %val
 }
 
 define float @test_fnmsub(float %a, float %b, float %c) {
-; CHECK: test_fnmsub:
+; CHECK-LABEL: test_fnmsub:
+; CHECK-NOFAST-LABEL: test_fnmsub:
   %nega = fsub float -0.0, %a
   %negc = fsub float -0.0, %c
   %val = call float @llvm.fma.f32(float %nega, float %b, float %negc)
 ; CHECK: fnmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST: fnmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
   ret float %val
 }
 
 define double @testd_fmadd(double %a, double %b, double %c) {
-; CHECK: testd_fmadd:
+; CHECK-LABEL: testd_fmadd:
+; CHECK-NOFAST-LABEL: testd_fmadd:
   %val = call double @llvm.fma.f64(double %a, double %b, double %c)
 ; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
+; CHECK-NOFAST: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
   ret double %val
 }
 
 define double @testd_fmsub(double %a, double %b, double %c) {
-; CHECK: testd_fmsub:
+; CHECK-LABEL: testd_fmsub:
+; CHECK-NOFAST-LABEL: testd_fmsub:
   %nega = fsub double -0.0, %a
   %val = call double @llvm.fma.f64(double %nega, double %b, double %c)
 ; CHECK: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
+; CHECK-NOFAST: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
   ret double %val
 }
 
 define double @testd_fnmadd(double %a, double %b, double %c) {
-; CHECK: testd_fnmadd:
+; CHECK-LABEL: testd_fnmadd:
+; CHECK-NOFAST-LABEL: testd_fnmadd:
   %negc = fsub double -0.0, %c
   %val = call double @llvm.fma.f64(double %a, double %b, double %negc)
 ; CHECK: fnmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
+; CHECK-NOFAST: fnmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
   ret double %val
 }
 
 define double @testd_fnmsub(double %a, double %b, double %c) {
-; CHECK: testd_fnmsub:
+; CHECK-LABEL: testd_fnmsub:
+; CHECK-NOFAST-LABEL: testd_fnmsub:
   %nega = fsub double -0.0, %a
   %negc = fsub double -0.0, %c
   %val = call double @llvm.fma.f64(double %nega, double %b, double %negc)
 ; CHECK: fnmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
+; CHECK-NOFAST: fnmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
   ret double %val
 }
 
 define float @test_fmadd_unfused(float %a, float %b, float %c) {
-; CHECK: test_fmadd_unfused:
+; CHECK-LABEL: test_fmadd_unfused:
+; CHECK-NOFAST-LABEL: test_fmadd_unfused:
   %prod = fmul float %b, %c
   %sum = fadd float %a, %prod
 ; CHECK: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST-NOT: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST: fadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
   ret float %sum
 }
 
 define float @test_fmsub_unfused(float %a, float %b, float %c) {
-; CHECK: test_fmsub_unfused:
+; CHECK-LABEL: test_fmsub_unfused:
+; CHECK-NOFAST-LABEL: test_fmsub_unfused:
   %prod = fmul float %b, %c
   %diff = fsub float %a, %prod
 ; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST-NOT: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST: fsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
   ret float %diff
 }
 
 define float @test_fnmadd_unfused(float %a, float %b, float %c) {
-; CHECK: test_fnmadd_unfused:
+; CHECK-LABEL: test_fnmadd_unfused:
+; CHECK-NOFAST-LABEL: test_fnmadd_unfused:
   %nega = fsub float -0.0, %a
   %prod = fmul float %b, %c
   %sum = fadd float %nega, %prod
 ; CHECK: fnmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST-NOT: fnmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST: fsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
   ret float %sum
 }
 
 define float @test_fnmsub_unfused(float %a, float %b, float %c) {
-; CHECK: test_fnmsub_unfused:
+; CHECK-LABEL: test_fnmsub_unfused:
+; CHECK-NOFAST-LABEL: test_fnmsub_unfused:
   %nega = fsub float -0.0, %a
   %prod = fmul float %b, %c
   %diff = fsub float %nega, %prod
 ; CHECK: fnmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST-NOT: fnmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST: fneg {{s[0-9]+}}, {{s[0-9]+}}
+; CHECK-NOFAST: fsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
   ret float %diff
 }
diff --git a/test/CodeGen/AArch64/fp128-folding.ll b/test/CodeGen/AArch64/fp128-folding.ll
index b5bdcf4..b1c560d 100644
--- a/test/CodeGen/AArch64/fp128-folding.ll
+++ b/test/CodeGen/AArch64/fp128-folding.ll
@@ -5,7 +5,7 @@ declare void @bar(i8*, i8*, i32*)
 ; which is not supported.
 
 define fp128 @test_folding() {
-; CHECK: test_folding:
+; CHECK-LABEL: test_folding:
   %l = alloca i32
   store i32 42, i32* %l
   %val = load i32* %l
@@ -14,4 +14,4 @@ define fp128 @test_folding() {
   ; successfully.
 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI
   ret fp128 %fpval
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/AArch64/fp128.ll b/test/CodeGen/AArch64/fp128.ll
index 258d34b..853c03d 100644
--- a/test/CodeGen/AArch64/fp128.ll
+++ b/test/CodeGen/AArch64/fp128.ll
@@ -4,7 +4,7 @@
 @rhs = global fp128 zeroinitializer
 
 define fp128 @test_add() {
-; CHECK: test_add:
+; CHECK-LABEL: test_add:
 
   %lhs = load fp128* @lhs
   %rhs = load fp128* @rhs
@@ -17,7 +17,7 @@ define fp128 @test_add() {
 }
 
 define fp128 @test_sub() {
-; CHECK: test_sub:
+; CHECK-LABEL: test_sub:
 
   %lhs = load fp128* @lhs
   %rhs = load fp128* @rhs
@@ -30,7 +30,7 @@ define fp128 @test_sub() {
 }
 
 define fp128 @test_mul() {
-; CHECK: test_mul:
+; CHECK-LABEL: test_mul:
 
   %lhs = load fp128* @lhs
   %rhs = load fp128* @rhs
@@ -43,7 +43,7 @@ define fp128 @test_mul() {
 }
 
 define fp128 @test_div() {
-; CHECK: test_div:
+; CHECK-LABEL: test_div:
 
   %lhs = load fp128* @lhs
   %rhs = load fp128* @rhs
@@ -59,7 +59,7 @@ define fp128 @test_div() {
 @var64 = global i64 0
 
 define void @test_fptosi() {
-; CHECK: test_fptosi:
+; CHECK-LABEL: test_fptosi:
   %val = load fp128* @lhs
 
   %val32 = fptosi fp128 %val to i32
@@ -74,7 +74,7 @@ define void @test_fptosi() {
 }
 
 define void @test_fptoui() {
-; CHECK: test_fptoui:
+; CHECK-LABEL: test_fptoui:
   %val = load fp128* @lhs
 
   %val32 = fptoui fp128 %val to i32
@@ -89,7 +89,7 @@ define void @test_fptoui() {
 }
 
 define void @test_sitofp() {
-; CHECK: test_sitofp:
+; CHECK-LABEL: test_sitofp:
 
   %src32 = load i32* @var32
   %val32 = sitofp i32 %src32 to fp128
@@ -105,7 +105,7 @@ define void @test_sitofp() {
 }
 
 define void @test_uitofp() {
-; CHECK: test_uitofp:
+; CHECK-LABEL: test_uitofp:
 
   %src32 = load i32* @var32
   %val32 = uitofp i32 %src32 to fp128
@@ -121,7 +121,7 @@ define void @test_uitofp() {
 }
 
 define i1 @test_setcc1() {
-; CHECK: test_setcc1:
+; CHECK-LABEL: test_setcc1:
 
   %lhs = load fp128* @lhs
   %rhs = load fp128* @rhs
@@ -140,7 +140,7 @@ define i1 @test_setcc1() {
 }
 
 define i1 @test_setcc2() {
-; CHECK: test_setcc2:
+; CHECK-LABEL: test_setcc2:
 
   %lhs = load fp128* @lhs
   %rhs = load fp128* @rhs
@@ -165,7 +165,7 @@ define i1 @test_setcc2() {
 }
 
 define i32 @test_br_cc() {
-; CHECK: test_br_cc:
+; CHECK-LABEL: test_br_cc:
 
   %lhs = load fp128* @lhs
   %rhs = load fp128* @rhs
@@ -202,7 +202,7 @@ iffalse:
 }
 
 define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
-; CHECK: test_select:
+; CHECK-LABEL: test_select:
 
   %val = select i1 %cond, fp128 %lhs, fp128 %rhs
   store fp128 %val, fp128* @lhs
@@ -222,7 +222,7 @@ define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
 @vardouble = global double 0.0
 
 define void @test_round() {
-; CHECK: test_round:
+; CHECK-LABEL: test_round:
 
   %val = load fp128* @lhs
 
@@ -240,7 +240,7 @@ define void @test_round() {
 }
 
 define void @test_extend() {
-; CHECK: test_extend:
+; CHECK-LABEL: test_extend:
 
   %val = load fp128* @lhs
 
@@ -265,7 +265,7 @@ define fp128 @test_neg(fp128 %in) {
 ; Make sure the weird hex constant below *is* -0.0
 ; CHECK-NEXT: fp128 -0
 
-; CHECK: test_neg:
+; CHECK-LABEL: test_neg:
 
   ; Could in principle be optimized to fneg which we can't select, this makes
   ; sure that doesn't happen.
diff --git a/test/CodeGen/AArch64/fpimm.ll b/test/CodeGen/AArch64/fpimm.ll
index fd28aee..ccf7c8a 100644
--- a/test/CodeGen/AArch64/fpimm.ll
+++ b/test/CodeGen/AArch64/fpimm.ll
@@ -4,7 +4,7 @@
 @varf64 = global double 0.0
 
 define void @check_float() {
-; CHECK: check_float:
+; CHECK-LABEL: check_float:
 
   %val = load float* @varf32
   %newval1 = fadd float %val, 8.5
@@ -19,7 +19,7 @@ define void @check_float() {
 }
 
 define void @check_double() {
-; CHECK: check_double:
+; CHECK-LABEL: check_double:
 
   %val = load double* @varf64
   %newval1 = fadd double %val, 8.5
diff --git a/test/CodeGen/AArch64/func-argpassing.ll b/test/CodeGen/AArch64/func-argpassing.ll
index 78fde6a..15f8e76 100644
--- a/test/CodeGen/AArch64/func-argpassing.ll
+++ b/test/CodeGen/AArch64/func-argpassing.ll
@@ -11,7 +11,7 @@
 @varstruct = global %myStruct zeroinitializer
 
 define void @take_i8s(i8 %val1, i8 %val2) {
-; CHECK: take_i8s:
+; CHECK-LABEL: take_i8s:
     store i8 %val2, i8* @var8
     ; Not using w1 may be technically allowed, but it would indicate a
     ; problem in itself.
@@ -20,7 +20,7 @@ define void @take_i8s(i8 %val1, i8 %val2) {
 }
 
 define void @add_floats(float %val1, float %val2) {
-; CHECK: add_floats:
+; CHECK-LABEL: add_floats:
     %newval = fadd float %val1, %val2
 ; CHECK: fadd [[ADDRES:s[0-9]+]], s0, s1
     store float %newval, float* @varfloat
@@ -31,7 +31,7 @@ define void @add_floats(float %val1, float %val2) {
 ; byval pointers should be allocated to the stack and copied as if
 ; with memcpy.
 define void @take_struct(%myStruct* byval %structval) {
-; CHECK: take_struct:
+; CHECK-LABEL: take_struct:
     %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
     %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
 
@@ -51,7 +51,7 @@ define void @take_struct(%myStruct* byval %structval) {
 
 ; %structval should be at sp + 16
 define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) {
-; CHECK: check_byval_align:
+; CHECK-LABEL: check_byval_align:
 
     %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
     %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
@@ -72,7 +72,7 @@ define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %st
 }
 
 define i32 @return_int() {
-; CHECK: return_int:
+; CHECK-LABEL: return_int:
     %val = load i32* @var32
     ret i32 %val
 ; CHECK: ldr w0, [{{x[0-9]+}}, #:lo12:var32]
@@ -81,7 +81,7 @@ define i32 @return_int() {
 }
 
 define double @return_double() {
-; CHECK: return_double:
+; CHECK-LABEL: return_double:
     ret double 3.14
 ; CHECK: ldr d0, [{{x[0-9]+}}, #:lo12:.LCPI
 }
@@ -90,7 +90,7 @@ define double @return_double() {
 ; small enough to go into registers. Not all that pretty, but it
 ; works.
 define [2 x i64] @return_struct() {
-; CHECK: return_struct:
+; CHECK-LABEL: return_struct:
     %addr = bitcast %myStruct* @varstruct to [2 x i64]*
     %val = load [2 x i64]* %addr
     ret [2 x i64] %val
@@ -107,7 +107,7 @@ define [2 x i64] @return_struct() {
 ; structs larger than 16 bytes, but C semantics can still be provided
 ; if LLVM does it to %myStruct too. So this is the simplest check
 define void @return_large_struct(%myStruct* sret %retval) {
-; CHECK: return_large_struct:
+; CHECK-LABEL: return_large_struct:
     %addr0 = getelementptr %myStruct* %retval, i64 0, i32 0
     %addr1 = getelementptr %myStruct* %retval, i64 0, i32 1
     %addr2 = getelementptr %myStruct* %retval, i64 0, i32 2
@@ -128,7 +128,7 @@ define void @return_large_struct(%myStruct* sret %retval) {
 define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45,
                           i32* %var6, %myStruct* byval %struct, i32* byval %stacked,
                           double %notstacked) {
-; CHECK: struct_on_stack:
+; CHECK-LABEL: struct_on_stack:
     %addr = getelementptr %myStruct* %struct, i64 0, i32 0
     %val64 = load i64* %addr
     store i64 %val64, i64* @var64
@@ -148,7 +148,7 @@ define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var
 define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,
                          float %var4, float %var5, float %var6, float %var7,
                          float %var8) {
-; CHECK: stacked_fpu:
+; CHECK-LABEL: stacked_fpu:
     store float %var8, float* @varfloat
     ; Beware as above: the offset would be different on big-endian
     ; machines if the first ldr were changed to use s-registers.
@@ -186,7 +186,7 @@ define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3,
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
 
 define i32 @test_extern() {
-; CHECK: test_extern:
+; CHECK-LABEL: test_extern:
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* undef, i32 undef, i32 4, i1 0)
 ; CHECK: bl memcpy
   ret i32 0
diff --git a/test/CodeGen/AArch64/func-calls.ll b/test/CodeGen/AArch64/func-calls.ll
index 13b689c..b12130b 100644
--- a/test/CodeGen/AArch64/func-calls.ll
+++ b/test/CodeGen/AArch64/func-calls.ll
@@ -17,7 +17,7 @@ declare void @take_i8s(i8 %val1, i8 %val2)
 declare void @take_floats(float %val1, float %val2)
 
 define void @simple_args() {
-; CHECK: simple_args:
+; CHECK-LABEL: simple_args:
   %char1 = load i8* @var8
   %char2 = load i8* @var8_2
   call void @take_i8s(i8 %char1, i8 %char2)
@@ -41,7 +41,7 @@ declare [2 x i64] @return_smallstruct()
 declare void @return_large_struct(%myStruct* sret %retval)
 
 define void @simple_rets() {
-; CHECK: simple_rets:
+; CHECK-LABEL: simple_rets:
 
   %int = call i32 @return_int()
   store i32 %int, i32* @var32
@@ -106,7 +106,7 @@ declare void @check_i128_regalign(i32 %val0, i128 %val1)
 
 
 define void @check_i128_align() {
-; CHECK: check_i128_align:
+; CHECK-LABEL: check_i128_align:
   %val = load i128* @var128
   call void @check_i128_stackalign(i32 0, i32 1, i32 2, i32 3,
                                    i32 4, i32 5, i32 6, i32 7,
@@ -130,7 +130,7 @@ define void @check_i128_align() {
 @fptr = global void()* null
 
 define void @check_indirect_call() {
-; CHECK: check_indirect_call:
+; CHECK-LABEL: check_indirect_call:
   %func = load void()** @fptr
   call void %func()
 ; CHECK: ldr [[FPTR:x[0-9]+]], [{{x[0-9]+}}, #:lo12:fptr]
diff --git a/test/CodeGen/AArch64/global-alignment.ll b/test/CodeGen/AArch64/global-alignment.ll
index 8ed6e55..56e5cba 100644
--- a/test/CodeGen/AArch64/global-alignment.ll
+++ b/test/CodeGen/AArch64/global-alignment.ll
@@ -5,7 +5,7 @@
 @var32_align64 = global [3 x i32] zeroinitializer, align 8
 
 define i64 @test_align32() {
-; CHECK: test_align32:
+; CHECK-LABEL: test_align32:
   %addr = bitcast [3 x i32]* @var32 to i64*
 
   ; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to
@@ -19,7 +19,7 @@ define i64 @test_align32() {
 }
 
 define i64 @test_align64() {
-; CHECK: test_align64:
+; CHECK-LABEL: test_align64:
   %addr = bitcast [3 x i64]* @var64 to i64*
 
   ; However, var64 *is* properly aligned and emitting an adrp/add/ldr would be
@@ -33,7 +33,7 @@ define i64 @test_align64() {
 }
 
 define i64 @test_var32_align64() {
-; CHECK: test_var32_align64:
+; CHECK-LABEL: test_var32_align64:
   %addr = bitcast [3 x i32]* @var32_align64 to i64*
 
   ; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to
@@ -49,7 +49,7 @@ define i64 @test_var32_align64() {
 @yet_another_var = external global {i32, i32}
 
 define i64 @test_yet_another_var() {
-; CHECK: test_yet_another_var:
+; CHECK-LABEL: test_yet_another_var:
 
   ; @yet_another_var has a preferred alignment of 8, but that's not enough if
   ; we're going to be linking against other things. Its ABI alignment is only 4
@@ -62,7 +62,7 @@ define i64 @test_yet_another_var() {
 }
 
 define i64()* @test_functions() {
-; CHECK: test_functions:
+; CHECK-LABEL: test_functions:
   ret i64()* @test_yet_another_var
 ; CHECK: adrp [[HIBITS:x[0-9]+]], test_yet_another_var
 ; CHECK: add x0, [[HIBITS]], #:lo12:test_yet_another_var
diff --git a/test/CodeGen/AArch64/got-abuse.ll b/test/CodeGen/AArch64/got-abuse.ll
index c474e58..8b06031 100644
--- a/test/CodeGen/AArch64/got-abuse.ll
+++ b/test/CodeGen/AArch64/got-abuse.ll
@@ -13,7 +13,7 @@ declare void @consume(i32)
 declare void @func()
 
 define void @foo() nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 entry:
   call void @consume(i32 ptrtoint (void ()* @func to i32))
 ; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:func
diff --git a/test/CodeGen/AArch64/i128-align.ll b/test/CodeGen/AArch64/i128-align.ll
index f019ea0..21ca7ed 100644
--- a/test/CodeGen/AArch64/i128-align.ll
+++ b/test/CodeGen/AArch64/i128-align.ll
@@ -5,7 +5,7 @@
 @var = global %struct zeroinitializer
 
 define i64 @check_size() {
-; CHECK: check_size:
+; CHECK-LABEL: check_size:
   %starti = ptrtoint %struct* @var to i64
 
   %endp = getelementptr %struct* @var, i64 1
@@ -17,7 +17,7 @@ define i64 @check_size() {
 }
 
 define i64 @check_field() {
-; CHECK: check_field:
+; CHECK-LABEL: check_field:
   %starti = ptrtoint %struct* @var to i64
 
   %endp = getelementptr %struct* @var, i64 0, i32 1
@@ -26,4 +26,4 @@ define i64 @check_field() {
   %diff = sub i64 %endi, %starti
   ret i64 %diff
 ; CHECK: movz x0, #16
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/AArch64/illegal-float-ops.ll b/test/CodeGen/AArch64/illegal-float-ops.ll
index 446151b..03c6d8d 100644
--- a/test/CodeGen/AArch64/illegal-float-ops.ll
+++ b/test/CodeGen/AArch64/illegal-float-ops.ll
@@ -9,7 +9,7 @@ declare double @llvm.cos.f64(double)
 declare fp128 @llvm.cos.f128(fp128)
 
 define void @test_cos(float %float, double %double, fp128 %fp128) {
-; CHECK: test_cos:
+; CHECK-LABEL: test_cos:
 
    %cosfloat = call float @llvm.cos.f32(float %float)
    store float %cosfloat, float* @varfloat
@@ -31,7 +31,7 @@ declare double @llvm.exp.f64(double)
 declare fp128 @llvm.exp.f128(fp128)
 
 define void @test_exp(float %float, double %double, fp128 %fp128) {
-; CHECK: test_exp:
+; CHECK-LABEL: test_exp:
 
    %expfloat = call float @llvm.exp.f32(float %float)
    store float %expfloat, float* @varfloat
@@ -53,7 +53,7 @@ declare double @llvm.exp2.f64(double)
 declare fp128 @llvm.exp2.f128(fp128)
 
 define void @test_exp2(float %float, double %double, fp128 %fp128) {
-; CHECK: test_exp2:
+; CHECK-LABEL: test_exp2:
 
    %exp2float = call float @llvm.exp2.f32(float %float)
    store float %exp2float, float* @varfloat
@@ -75,7 +75,7 @@ declare double @llvm.log.f64(double)
 declare fp128 @llvm.log.f128(fp128)
 
 define void @test_log(float %float, double %double, fp128 %fp128) {
-; CHECK: test_log:
+; CHECK-LABEL: test_log:
 
    %logfloat = call float @llvm.log.f32(float %float)
    store float %logfloat, float* @varfloat
@@ -97,7 +97,7 @@ declare double @llvm.log2.f64(double)
 declare fp128 @llvm.log2.f128(fp128)
 
 define void @test_log2(float %float, double %double, fp128 %fp128) {
-; CHECK: test_log2:
+; CHECK-LABEL: test_log2:
 
    %log2float = call float @llvm.log2.f32(float %float)
    store float %log2float, float* @varfloat
@@ -119,7 +119,7 @@ declare double @llvm.log10.f64(double)
 declare fp128 @llvm.log10.f128(fp128)
 
 define void @test_log10(float %float, double %double, fp128 %fp128) {
-; CHECK: test_log10:
+; CHECK-LABEL: test_log10:
 
    %log10float = call float @llvm.log10.f32(float %float)
    store float %log10float, float* @varfloat
@@ -141,7 +141,7 @@ declare double @llvm.sin.f64(double)
 declare fp128 @llvm.sin.f128(fp128)
 
 define void @test_sin(float %float, double %double, fp128 %fp128) {
-; CHECK: test_sin:
+; CHECK-LABEL: test_sin:
 
    %sinfloat = call float @llvm.sin.f32(float %float)
    store float %sinfloat, float* @varfloat
@@ -163,7 +163,7 @@ declare double @llvm.pow.f64(double, double)
 declare fp128 @llvm.pow.f128(fp128, fp128)
 
 define void @test_pow(float %float, double %double, fp128 %fp128) {
-; CHECK: test_pow:
+; CHECK-LABEL: test_pow:
 
    %powfloat = call float @llvm.pow.f32(float %float, float %float)
    store float %powfloat, float* @varfloat
@@ -185,7 +185,7 @@ declare double @llvm.powi.f64(double, i32)
 declare fp128 @llvm.powi.f128(fp128, i32)
 
 define void @test_powi(float %float, double %double, i32 %exponent, fp128 %fp128) {
-; CHECK: test_powi:
+; CHECK-LABEL: test_powi:
 
    %powifloat = call float @llvm.powi.f32(float %float, i32 %exponent)
    store float %powifloat, float* @varfloat
@@ -203,7 +203,7 @@ define void @test_powi(float %float, double %double, i32 %exponent, fp128 %fp128
 }
 
 define void @test_frem(float %float, double %double, fp128 %fp128) {
-; CHECK: test_frem:
+; CHECK-LABEL: test_frem:
 
   %fremfloat = frem float %float, %float
   store float %fremfloat, float* @varfloat
@@ -219,3 +219,29 @@ define void @test_frem(float %float, double %double, fp128 %fp128) {
 
   ret void
 }
+
+declare fp128 @llvm.fma.f128(fp128, fp128, fp128)
+
+define void @test_fma(fp128 %fp128) {
+; CHECK-LABEL: test_fma:
+
+  %fmafp128 = call fp128 @llvm.fma.f128(fp128 %fp128, fp128 %fp128, fp128 %fp128)
+  store fp128 %fmafp128, fp128* @varfp128
+; CHECK: bl fmal
+
+  ret void
+}
+
+declare fp128 @llvm.fmuladd.f128(fp128, fp128, fp128)
+
+define void @test_fmuladd(fp128 %fp128) {
+; CHECK-LABEL: test_fmuladd:
+
+  %fmuladdfp128 = call fp128 @llvm.fmuladd.f128(fp128 %fp128, fp128 %fp128, fp128 %fp128)
+  store fp128 %fmuladdfp128, fp128* @varfp128
+; CHECK-NOT: bl fmal
+; CHECK: bl __multf3
+; CHECK: bl __addtf3
+
+  ret void
+}
diff --git a/test/CodeGen/AArch64/init-array.ll b/test/CodeGen/AArch64/init-array.ll
index d80be8f..3ff1c1a 100644
--- a/test/CodeGen/AArch64/init-array.ll
+++ b/test/CodeGen/AArch64/init-array.ll
@@ -6,4 +6,4 @@ define internal void @_GLOBAL__I_a() section ".text.startup" {
 
 @llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }]
 
-; CHECK: .section .init_array
\ No newline at end of file
+; CHECK: .section .init_array
diff --git a/test/CodeGen/AArch64/inline-asm-constraints-badI.ll b/test/CodeGen/AArch64/inline-asm-constraints-badI.ll
index c39c57f..61bbfc2 100644
--- a/test/CodeGen/AArch64/inline-asm-constraints-badI.ll
+++ b/test/CodeGen/AArch64/inline-asm-constraints-badI.ll
@@ -4,4 +4,4 @@ define void @foo() {
   ; Out of range immediate for I.
   call void asm sideeffect "add x0, x0, $0", "I"(i32 4096)
   ret void
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/AArch64/inline-asm-constraints-badK.ll b/test/CodeGen/AArch64/inline-asm-constraints-badK.ll
index 47c5f98..40746e1 100644
--- a/test/CodeGen/AArch64/inline-asm-constraints-badK.ll
+++ b/test/CodeGen/AArch64/inline-asm-constraints-badK.ll
@@ -4,4 +4,4 @@ define void @foo() {
   ; 32-bit bitpattern ending in 1101 can't be produced.
   call void asm sideeffect "and w0, w0, $0", "K"(i32 13)
   ret void
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll b/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll
index 7a5b99e..2c53381 100644
--- a/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll
+++ b/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll
@@ -4,4 +4,4 @@ define void @foo() {
   ; 32-bit bitpattern ending in 1101 can't be produced.
   call void asm sideeffect "and w0, w0, $0", "K"(i64 4294967296)
   ret void
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/AArch64/inline-asm-constraints-badL.ll b/test/CodeGen/AArch64/inline-asm-constraints-badL.ll
index 4f00398..d82d5a2 100644
--- a/test/CodeGen/AArch64/inline-asm-constraints-badL.ll
+++ b/test/CodeGen/AArch64/inline-asm-constraints-badL.ll
@@ -4,4 +4,4 @@ define void @foo() {
   ; 32-bit bitpattern ending in 1101 can't be produced.
   call void asm sideeffect "and x0, x0, $0", "L"(i32 13)
   ret void
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/AArch64/inline-asm-constraints.ll b/test/CodeGen/AArch64/inline-asm-constraints.ll
index c232f32..18a3b37 100644
--- a/test/CodeGen/AArch64/inline-asm-constraints.ll
+++ b/test/CodeGen/AArch64/inline-asm-constraints.ll
@@ -1,21 +1,21 @@
-; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
+;RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
 
 define i64 @test_inline_constraint_r(i64 %base, i32 %offset) {
-; CHECK: test_inline_constraint_r:
+; CHECK-LABEL: test_inline_constraint_r:
   %val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 %base, i32 %offset)
 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
   ret i64 %val
 }
 
 define i16 @test_small_reg(i16 %lhs, i16 %rhs) {
-; CHECK: test_small_reg:
+; CHECK-LABEL: test_small_reg:
   %val = call i16 asm sideeffect "add $0, $1, $2, sxth", "=r,r,r"(i16 %lhs, i16 %rhs)
 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth
   ret i16 %val
 }
 
 define i64 @test_inline_constraint_r_imm(i64 %base, i32 %offset) {
-; CHECK: test_inline_constraint_r_imm:
+; CHECK-LABEL: test_inline_constraint_r_imm:
   %val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 4, i32 12)
 ; CHECK: movz [[FOUR:x[0-9]+]], #4
 ; CHECK: movz [[TWELVE:w[0-9]+]], #12
@@ -26,7 +26,7 @@ define i64 @test_inline_constraint_r_imm(i64 %base, i32 %offset) {
 ; m is permitted to have a base/offset form. We don't do that
 ; currently though.
 define i32 @test_inline_constraint_m(i32 *%ptr) {
-; CHECK: test_inline_constraint_m:
+; CHECK-LABEL: test_inline_constraint_m:
   %val = call i32 asm "ldr $0, $1", "=r,m"(i32 *%ptr)
 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
   ret i32 %val
@@ -36,7 +36,7 @@ define i32 @test_inline_constraint_m(i32 *%ptr) {
 
 ; Q should *never* have base/offset form even if given the chance.
 define i32 @test_inline_constraint_Q(i32 *%ptr) {
-; CHECK: test_inline_constraint_Q:
+; CHECK-LABEL: test_inline_constraint_Q:
   %val = call i32 asm "ldr $0, $1", "=r,Q"(i32* getelementptr([8 x i32]* @arr, i32 0, i32 1))
 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
   ret i32 %val
@@ -44,8 +44,28 @@ define i32 @test_inline_constraint_Q(i32 *%ptr) {
 
 @dump = global fp128 zeroinitializer
 
+define void @test_inline_constraint_w(<8 x i8> %vec64, <4 x float> %vec128, half %hlf, float %flt, double %dbl, fp128 %quad) {
+; CHECK: test_inline_constraint_w:
+  call <8 x i8> asm sideeffect "add $0.8b, $1.8b, $1.8b", "=w,w"(<8 x i8> %vec64)
+  call <8 x i8> asm sideeffect "fadd $0.4s, $1.4s, $1.4s", "=w,w"(<4 x float> %vec128)
+; CHECK: add {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK: fadd {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+
+  ; Arguably semantically dodgy to output "vN", but it's what GCC does
+  ; so purely for compatibility we want vector registers to be output.
+  call float asm sideeffect "fcvt ${0:s}, ${1:h}", "=w,w"(half undef)
+  call float asm sideeffect "fadd $0.2s, $0.2s, $0.2s", "=w,w"(float %flt)
+  call double asm sideeffect "fadd $0.2d, $0.2d, $0.2d", "=w,w"(double %dbl)
+  call fp128 asm sideeffect "fadd $0.2d, $0.2d, $0.2d", "=w,w"(fp128 %quad)
+; CHECK: fcvt {{s[0-9]+}}, {{h[0-9]+}}
+; CHECK: fadd {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK: fadd {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK: fadd {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+  ret void
+}
+
 define void @test_inline_constraint_I() {
-; CHECK: test_inline_constraint_I:
+; CHECK-LABEL: test_inline_constraint_I:
   call void asm sideeffect "add x0, x0, $0", "I"(i32 0)
   call void asm sideeffect "add x0, x0, $0", "I"(i64 4095)
 ; CHECK: add x0, x0, #0
@@ -57,7 +77,7 @@ define void @test_inline_constraint_I() {
 ; Skip J because it's useless
 
 define void @test_inline_constraint_K() {
-; CHECK: test_inline_constraint_K:
+; CHECK-LABEL: test_inline_constraint_K:
   call void asm sideeffect "and w0, w0, $0", "K"(i32 2863311530) ; = 0xaaaaaaaa
   call void asm sideeffect "and w0, w0, $0", "K"(i32 65535)
 ; CHECK: and w0, w0, #-1431655766
@@ -67,7 +87,7 @@ define void @test_inline_constraint_K() {
 }
 
 define void @test_inline_constraint_L() {
-; CHECK: test_inline_constraint_L:
+; CHECK-LABEL: test_inline_constraint_L:
   call void asm sideeffect "and x0, x0, $0", "L"(i64 4294967296) ; = 0xaaaaaaaa
   call void asm sideeffect "and x0, x0, $0", "L"(i64 65535)
 ; CHECK: and x0, x0, #4294967296
@@ -81,7 +101,7 @@ define void @test_inline_constraint_L() {
 @var = global i32 0
 
 define void @test_inline_constraint_S() {
-; CHECK: test_inline_constraint_S:
+; CHECK-LABEL: test_inline_constraint_S:
   call void asm sideeffect "adrp x0, $0", "S"(i32* @var)
   call void asm sideeffect "adrp x0, ${0:A}", "S"(i32* @var)
   call void asm sideeffect "add x0, x0, ${0:L}", "S"(i32* @var)
@@ -92,7 +112,7 @@ define void @test_inline_constraint_S() {
 }
 
 define i32 @test_inline_constraint_S_label(i1 %in) {
-; CHECK: test_inline_constraint_S_label:
+; CHECK-LABEL: test_inline_constraint_S_label:
   call void asm sideeffect "adr x0, $0", "S"(i8* blockaddress(@test_inline_constraint_S_label, %loc))
 ; CHECK: adr x0, .Ltmp{{[0-9]+}}
   br i1 %in, label %loc, label %loc2
@@ -103,15 +123,15 @@ loc2:
 }
 
 define void @test_inline_constraint_Y() {
-; CHECK: test_inline_constraint_Y:
+; CHECK-LABEL: test_inline_constraint_Y:
   call void asm sideeffect "fcmp s0, $0", "Y"(float 0.0)
 ; CHECK: fcmp s0, #0.0
   ret void
 }
 
 define void @test_inline_constraint_Z() {
-; CHECK: test_inline_constraint_Z:
+; CHECK-LABEL: test_inline_constraint_Z:
   call void asm sideeffect "cmp w0, $0", "Z"(i32 0)
 ; CHECK: cmp w0, #0
   ret void
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/AArch64/inline-asm-modifiers.ll b/test/CodeGen/AArch64/inline-asm-modifiers.ll
index 3b55945..d1b21f8 100644
--- a/test/CodeGen/AArch64/inline-asm-modifiers.ll
+++ b/test/CodeGen/AArch64/inline-asm-modifiers.ll
@@ -9,7 +9,7 @@
 @var_tlsle = thread_local(localexec) global i32 0
 
 define void @test_inline_modifier_L() nounwind {
-; CHECK: test_inline_modifier_L:
+; CHECK-LABEL: test_inline_modifier_L:
   call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_simple)
   call void asm sideeffect "ldr x0, [x0, ${0:L}]", "S,~{x0}"(i32* @var_got)
   call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_tlsgd)
@@ -34,7 +34,7 @@ define void @test_inline_modifier_L() nounwind {
 }
 
 define void @test_inline_modifier_G() nounwind {
-; CHECK: test_inline_modifier_G:
+; CHECK-LABEL: test_inline_modifier_G:
   call void asm sideeffect "add x0, x0, ${0:G}, lsl #12", "S,~{x0}"(i32* @var_tlsld)
   call void asm sideeffect "add x0, x0, ${0:G}, lsl #12", "S,~{x0}"(i32* @var_tlsle)
 ; CHECK: add x0, x0, #:dtprel_hi12:var_tlsld, lsl #12
@@ -47,7 +47,7 @@ define void @test_inline_modifier_G() nounwind {
 }
 
 define void @test_inline_modifier_A() nounwind {
-; CHECK: test_inline_modifier_A:
+; CHECK-LABEL: test_inline_modifier_A:
   call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_simple)
   call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_got)
   call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_tlsgd)
@@ -67,7 +67,7 @@ define void @test_inline_modifier_A() nounwind {
 }
 
 define void @test_inline_modifier_wx(i32 %small, i64 %big) nounwind {
-; CHECK: test_inline_modifier_wx:
+; CHECK-LABEL: test_inline_modifier_wx:
   call i32 asm sideeffect "add $0, $0, $0", "=r,0"(i32 %small)
   call i32 asm sideeffect "add ${0:w}, ${0:w}, ${0:w}", "=r,0"(i32 %small)
   call i32 asm sideeffect "add ${0:x}, ${0:x}, ${0:x}", "=r,0"(i32 %small)
@@ -91,7 +91,7 @@ define void @test_inline_modifier_wx(i32 %small, i64 %big) nounwind {
 }
 
 define void @test_inline_modifier_bhsdq() nounwind {
-; CHECK: test_inline_modifier_bhsdq:
+; CHECK-LABEL: test_inline_modifier_bhsdq:
   call float asm sideeffect "ldr ${0:b}, [sp]", "=w"()
   call float asm sideeffect "ldr ${0:h}, [sp]", "=w"()
   call float asm sideeffect "ldr ${0:s}, [sp]", "=w"()
@@ -117,9 +117,9 @@ define void @test_inline_modifier_bhsdq() nounwind {
 }
 
 define void @test_inline_modifier_c() nounwind {
-; CHECK: test_inline_modifier_c:
+; CHECK-LABEL: test_inline_modifier_c:
   call void asm sideeffect "adr x0, ${0:c}", "i"(i32 3)
 ; CHECK: adr x0, 3
 
   ret void
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/AArch64/large-consts.ll b/test/CodeGen/AArch64/large-consts.ll
new file mode 100644
index 0000000..1b769c6
--- /dev/null
+++ b/test/CodeGen/AArch64/large-consts.ll
@@ -0,0 +1,13 @@
+; RUN: llc -mtriple=aarch64-linux-gnu -o - %s -code-model=large -show-mc-encoding | FileCheck %s
+
+; Make sure the shift amount is encoded into the instructions by LLVM because
+; it's not the linker's job to put it there.
+
+define double @foo() {
+; CHECK: movz [[CPADDR:x[0-9]+]], #:abs_g3:.LCPI0_0   // encoding: [A,A,0xe0'A',0xd2'A']
+; CHECK: movk [[CPADDR]], #:abs_g2_nc:.LCPI0_0 // encoding: [A,A,0xc0'A',0xf2'A']
+; CHECK: movk [[CPADDR]], #:abs_g1_nc:.LCPI0_0 // encoding: [A,A,0xa0'A',0xf2'A']
+; CHECK: movk [[CPADDR]], #:abs_g0_nc:.LCPI0_0 // encoding: [A,A,0x80'A',0xf2'A']
+
+  ret double 3.14159
+}
diff --git a/test/CodeGen/AArch64/large-frame.ll b/test/CodeGen/AArch64/large-frame.ll
index 690b21d..fde3036 100644
--- a/test/CodeGen/AArch64/large-frame.ll
+++ b/test/CodeGen/AArch64/large-frame.ll
@@ -4,7 +4,7 @@ declare void @use_addr(i8*)
 @addr = global i8* null
 
 define void @test_bigframe() {
-; CHECK: test_bigframe:
+; CHECK-LABEL: test_bigframe:
 ; CHECK: .cfi_startproc
 
   %var1 = alloca i8, i32 20000000
@@ -50,7 +50,7 @@ define void @test_bigframe() {
 }
 
 define void @test_mediumframe() {
-; CHECK: test_mediumframe:
+; CHECK-LABEL: test_mediumframe:
   %var1 = alloca i8, i32 1000000
   %var2 = alloca i8, i32 16
   %var3 = alloca i8, i32 1000000
@@ -93,7 +93,7 @@ define void @test_mediumframe() {
 ; If temporary registers are allocated for adjustment, they should *not* clobber
 ; argument registers.
 define void @test_tempallocation([8 x i64] %val) nounwind {
-; CHECK: test_tempallocation:
+; CHECK-LABEL: test_tempallocation:
   %var = alloca i8, i32 1000000
 ; CHECK: sub sp, sp,
 
diff --git a/test/CodeGen/AArch64/ldst-regoffset.ll b/test/CodeGen/AArch64/ldst-regoffset.ll
index 4593512..c83fb52 100644
--- a/test/CodeGen/AArch64/ldst-regoffset.ll
+++ b/test/CodeGen/AArch64/ldst-regoffset.ll
@@ -9,7 +9,7 @@
 @var_double = global double 0.0
 
 define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_8bit:
+; CHECK-LABEL: ldst_8bit:
 
    %addr8_sxtw = getelementptr i8* %base, i32 %off32
    %val8_sxtw = load volatile i8* %addr8_sxtw
@@ -37,7 +37,7 @@ define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) {
 
 
 define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_16bit:
+; CHECK-LABEL: ldst_16bit:
 
    %addr8_sxtwN = getelementptr i16* %base, i32 %off32
    %val8_sxtwN = load volatile i16* %addr8_sxtwN
@@ -91,7 +91,7 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) {
 }
 
 define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_32bit:
+; CHECK-LABEL: ldst_32bit:
 
    %addr_sxtwN = getelementptr i32* %base, i32 %off32
    %val_sxtwN = load volatile i32* %addr_sxtwN
@@ -143,7 +143,7 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) {
 }
 
 define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_64bit:
+; CHECK-LABEL: ldst_64bit:
 
    %addr_sxtwN = getelementptr i64* %base, i32 %off32
    %val_sxtwN = load volatile i64* %addr_sxtwN
@@ -191,7 +191,7 @@ define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) {
 }
 
 define void @ldst_float(float* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_float:
+; CHECK-LABEL: ldst_float:
 
    %addr_sxtwN = getelementptr float* %base, i32 %off32
    %val_sxtwN = load volatile float* %addr_sxtwN
@@ -238,7 +238,7 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) {
 }
 
 define void @ldst_double(double* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_double:
+; CHECK-LABEL: ldst_double:
 
    %addr_sxtwN = getelementptr double* %base, i32 %off32
    %val_sxtwN = load volatile double* %addr_sxtwN
@@ -286,7 +286,7 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) {
 
 
 define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_128bit:
+; CHECK-LABEL: ldst_128bit:
 
    %addr_sxtwN = getelementptr fp128* %base, i32 %off32
    %val_sxtwN = load volatile fp128* %addr_sxtwN
diff --git a/test/CodeGen/AArch64/ldst-unscaledimm.ll b/test/CodeGen/AArch64/ldst-unscaledimm.ll
index 78a3c83..03dedcc 100644
--- a/test/CodeGen/AArch64/ldst-unscaledimm.ll
+++ b/test/CodeGen/AArch64/ldst-unscaledimm.ll
@@ -11,7 +11,7 @@
 @varptr = global i8* null
 
 define void @ldst_8bit() {
-; CHECK: ldst_8bit:
+; CHECK-LABEL: ldst_8bit:
 
 ; No architectural support for loads to 16-bit or 8-bit since we
 ; promote i8 during lowering.
@@ -72,7 +72,7 @@ define void @ldst_8bit() {
 }
 
 define void @ldst_16bit() {
-; CHECK: ldst_16bit:
+; CHECK-LABEL: ldst_16bit:
 
 ; No architectural support for loads to 16-bit or 16-bit since we
 ; promote i16 during lowering.
@@ -140,7 +140,7 @@ define void @ldst_16bit() {
 }
 
 define void @ldst_32bit() {
-; CHECK: ldst_32bit:
+; CHECK-LABEL: ldst_32bit:
 
   %addr_8bit = load i8** @varptr
 
@@ -186,7 +186,7 @@ define void @ldst_32bit() {
 }
 
 define void @ldst_float() {
-; CHECK: ldst_float:
+; CHECK-LABEL: ldst_float:
 
   %addr_8bit = load i8** @varptr
   %addrfp_8 = getelementptr i8* %addr_8bit, i64 -5
@@ -202,7 +202,7 @@ define void @ldst_float() {
 }
 
 define void @ldst_double() {
-; CHECK: ldst_double:
+; CHECK-LABEL: ldst_double:
 
   %addr_8bit = load i8** @varptr
   %addrfp_8 = getelementptr i8* %addr_8bit, i64 4
diff --git a/test/CodeGen/AArch64/ldst-unsignedimm.ll b/test/CodeGen/AArch64/ldst-unsignedimm.ll
index 1e7540d..77cef4e 100644
--- a/test/CodeGen/AArch64/ldst-unsignedimm.ll
+++ b/test/CodeGen/AArch64/ldst-unsignedimm.ll
@@ -9,7 +9,7 @@
 @var_double = global double 0.0
 
 define void @ldst_8bit() {
-; CHECK: ldst_8bit:
+; CHECK-LABEL: ldst_8bit:
 
 ; No architectural support for loads to 16-bit or 8-bit since we
 ; promote i8 during lowering.
@@ -63,7 +63,7 @@ define void @ldst_8bit() {
 }
 
 define void @ldst_16bit() {
-; CHECK: ldst_16bit:
+; CHECK-LABEL: ldst_16bit:
 
 ; No architectural support for load volatiles to 16-bit promote i16 during
 ; lowering.
@@ -117,7 +117,7 @@ define void @ldst_16bit() {
 }
 
 define void @ldst_32bit() {
-; CHECK: ldst_32bit:
+; CHECK-LABEL: ldst_32bit:
 
 ; Straight 32-bit load/store
   %val32_noext = load volatile i32* @var_32bit
@@ -225,7 +225,7 @@ define void @ldst_complex_offsets() {
 }
 
 define void @ldst_float() {
-; CHECK: ldst_float:
+; CHECK-LABEL: ldst_float:
 
    %valfp = load volatile float* @var_float
 ; CHECK: adrp {{x[0-9]+}}, var_float
@@ -238,7 +238,7 @@ define void @ldst_float() {
 }
 
 define void @ldst_double() {
-; CHECK: ldst_double:
+; CHECK-LABEL: ldst_double:
 
    %valfp = load volatile double* @var_double
 ; CHECK: adrp {{x[0-9]+}}, var_double
diff --git a/test/CodeGen/AArch64/literal_pools.ll b/test/CodeGen/AArch64/literal_pools.ll
index 9cfa8c5..b82f290 100644
--- a/test/CodeGen/AArch64/literal_pools.ll
+++ b/test/CodeGen/AArch64/literal_pools.ll
@@ -5,7 +5,7 @@
 @var64 = global i64 0
 
 define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
     %val32 = load i32* @var32
     %val64 = load i64* @var64
 
@@ -60,7 +60,7 @@ define void @foo() {
 @vardouble = global double 0.0
 
 define void @floating_lits() {
-; CHECK: floating_lits:
+; CHECK-LABEL: floating_lits:
 
   %floatval = load float* @varfloat
   %newfloat = fadd float %floatval, 128.0
diff --git a/test/CodeGen/AArch64/local_vars.ll b/test/CodeGen/AArch64/local_vars.ll
index 5cbf5a3..b5cef85 100644
--- a/test/CodeGen/AArch64/local_vars.ll
+++ b/test/CodeGen/AArch64/local_vars.ll
@@ -24,7 +24,7 @@ define void @trivial_func() nounwind {
 }
 
 define void @trivial_fp_func() {
-; CHECK-WITHFP: trivial_fp_func:
+; CHECK-WITHFP-LABEL: trivial_fp_func:
 
 ; CHECK-WITHFP: sub sp, sp, #16
 ; CHECK-WITHFP: stp x29, x30, [sp]
@@ -43,7 +43,7 @@ define void @trivial_fp_func() {
 
 define void @stack_local() {
   %local_var = alloca i64
-; CHECK: stack_local:
+; CHECK-LABEL: stack_local:
 ; CHECK: sub sp, sp, #16
 
   %val = load i64* @var
diff --git a/test/CodeGen/AArch64/logical-imm.ll b/test/CodeGen/AArch64/logical-imm.ll
index 5f3f4da..e04bb51 100644
--- a/test/CodeGen/AArch64/logical-imm.ll
+++ b/test/CodeGen/AArch64/logical-imm.ll
@@ -4,7 +4,7 @@
 @var64 = global i64 0
 
 define void @test_and(i32 %in32, i64 %in64) {
-; CHECK: test_and:
+; CHECK-LABEL: test_and:
 
   %val0 = and i32 %in32, 2863311530
   store volatile i32 %val0, i32* @var32
@@ -26,7 +26,7 @@ define void @test_and(i32 %in32, i64 %in64) {
 }
 
 define void @test_orr(i32 %in32, i64 %in64) {
-; CHECK: test_orr:
+; CHECK-LABEL: test_orr:
 
   %val0 = or i32 %in32, 2863311530
   store volatile i32 %val0, i32* @var32
@@ -48,7 +48,7 @@ define void @test_orr(i32 %in32, i64 %in64) {
 }
 
 define void @test_eor(i32 %in32, i64 %in64) {
-; CHECK: test_eor:
+; CHECK-LABEL: test_eor:
 
   %val0 = xor i32 %in32, 2863311530
   store volatile i32 %val0, i32* @var32
@@ -70,7 +70,7 @@ define void @test_eor(i32 %in32, i64 %in64) {
 }
 
 define void @test_mov(i32 %in32, i64 %in64) {
-; CHECK: test_mov:
+; CHECK-LABEL: test_mov:
   %val0 = add i32 %in32, 2863311530
   store i32 %val0, i32* @var32
 ; CHECK: orr {{w[0-9]+}}, wzr, #0xaaaaaaaa
diff --git a/test/CodeGen/AArch64/logical_shifted_reg.ll b/test/CodeGen/AArch64/logical_shifted_reg.ll
index bbbfcc1..a08ba20 100644
--- a/test/CodeGen/AArch64/logical_shifted_reg.ll
+++ b/test/CodeGen/AArch64/logical_shifted_reg.ll
@@ -7,7 +7,7 @@
 @var2_64 = global i64 0
 
 define void @logical_32bit() {
-; CHECK: logical_32bit:
+; CHECK-LABEL: logical_32bit:
   %val1 = load i32* @var1_32
   %val2 = load i32* @var2_32
 
@@ -97,7 +97,7 @@ define void @logical_32bit() {
 }
 
 define void @logical_64bit() {
-; CHECK: logical_64bit:
+; CHECK-LABEL: logical_64bit:
   %val1 = load i64* @var1_64
   %val2 = load i64* @var2_64
 
@@ -190,7 +190,7 @@ define void @logical_64bit() {
 }
 
 define void @flag_setting() {
-; CHECK: flag_setting:
+; CHECK-LABEL: flag_setting:
   %val1 = load i64* @var1_64
   %val2 = load i64* @var2_64
 
diff --git a/test/CodeGen/AArch64/logical_shifted_reg.s b/test/CodeGen/AArch64/logical_shifted_reg.s
deleted file mode 100644
index 89aea58..0000000
--- a/test/CodeGen/AArch64/logical_shifted_reg.s
+++ /dev/null
@@ -1,208 +0,0 @@
-	.file	"/home/timnor01/a64-trunk/llvm/test/CodeGen/AArch64/logical_shifted_reg.ll"
-	.text
-	.globl	logical_32bit
-	.type	logical_32bit,@function
-logical_32bit:                          // @logical_32bit
-	.cfi_startproc
-// BB#0:
-	adrp	x0, var1_32
-	ldr	w1, [x0, #:lo12:var1_32]
-	adrp	x0, var2_32
-	ldr	w2, [x0, #:lo12:var2_32]
-	and	w3, w1, w2
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	bic	w3, w1, w2
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	orr	w3, w1, w2
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	orn	w3, w1, w2
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	eor	w3, w1, w2
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	eon	w3, w2, w1
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	and	w3, w1, w2, lsl #31
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	bic	w3, w1, w2, lsl #31
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	orr	w3, w1, w2, lsl #31
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	orn	w3, w1, w2, lsl #31
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	eor	w3, w1, w2, lsl #31
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	eon	w3, w1, w2, lsl #31
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	bic	w3, w1, w2, asr #10
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	eor	w3, w1, w2, asr #10
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	orn	w3, w1, w2, lsr #1
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	eor	w3, w1, w2, lsr #1
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	eon	w3, w1, w2, ror #20
-	adrp	x0, var1_32
-	str	w3, [x0, #:lo12:var1_32]
-	and	w1, w1, w2, ror #20
-	adrp	x0, var1_32
-	str	w1, [x0, #:lo12:var1_32]
-	ret
-.Ltmp0:
-	.size	logical_32bit, .Ltmp0-logical_32bit
-	.cfi_endproc
-
-	.globl	logical_64bit
-	.type	logical_64bit,@function
-logical_64bit:                          // @logical_64bit
-	.cfi_startproc
-// BB#0:
-	adrp	x0, var1_64
-	ldr	x0, [x0, #:lo12:var1_64]
-	adrp	x1, var2_64
-	ldr	x1, [x1, #:lo12:var2_64]
-	and	x2, x0, x1
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	bic	x2, x0, x1
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	orr	x2, x0, x1
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	orn	x2, x0, x1
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	eor	x2, x0, x1
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	eon	x2, x1, x0
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	and	x2, x0, x1, lsl #63
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	bic	x2, x0, x1, lsl #63
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	orr	x2, x0, x1, lsl #63
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	orn	x2, x0, x1, lsl #63
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	eor	x2, x0, x1, lsl #63
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	eon	x2, x0, x1, lsl #63
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	bic	x2, x0, x1, asr #10
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	eor	x2, x0, x1, asr #10
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	orn	x2, x0, x1, lsr #1
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	eor	x2, x0, x1, lsr #1
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	eon	x2, x0, x1, ror #20
-	adrp	x3, var1_64
-	str	x2, [x3, #:lo12:var1_64]
-	and	x0, x0, x1, ror #20
-	adrp	x1, var1_64
-	str	x0, [x1, #:lo12:var1_64]
-	ret
-.Ltmp1:
-	.size	logical_64bit, .Ltmp1-logical_64bit
-	.cfi_endproc
-
-	.globl	flag_setting
-	.type	flag_setting,@function
-flag_setting:                           // @flag_setting
-	.cfi_startproc
-// BB#0:
-	sub	sp, sp, #16
-	adrp	x0, var1_64
-	ldr	x0, [x0, #:lo12:var1_64]
-	adrp	x1, var2_64
-	ldr	x1, [x1, #:lo12:var2_64]
-	tst	x0, x1
-	str	x0, [sp, #8]            // 8-byte Folded Spill
-	str	x1, [sp]                // 8-byte Folded Spill
-	b.gt .LBB2_4
-	b	.LBB2_1
-.LBB2_1:                                // %test2
-	ldr	x0, [sp, #8]            // 8-byte Folded Reload
-	ldr	x1, [sp]                // 8-byte Folded Reload
-	tst	x0, x1, lsl #63
-	b.lt .LBB2_4
-	b	.LBB2_2
-.LBB2_2:                                // %test3
-	ldr	x0, [sp, #8]            // 8-byte Folded Reload
-	ldr	x1, [sp]                // 8-byte Folded Reload
-	tst	x0, x1, asr #12
-	b.gt .LBB2_4
-	b	.LBB2_3
-.LBB2_3:                                // %other_exit
-	adrp	x0, var1_64
-	ldr	x1, [sp, #8]            // 8-byte Folded Reload
-	str	x1, [x0, #:lo12:var1_64]
-	add	sp, sp, #16
-	ret
-.LBB2_4:                                // %ret
-	add	sp, sp, #16
-	ret
-.Ltmp2:
-	.size	flag_setting, .Ltmp2-flag_setting
-	.cfi_endproc
-
-	.type	var1_32,@object         // @var1_32
-	.bss
-	.globl	var1_32
-	.align	2
-var1_32:
-	.word	0                       // 0x0
-	.size	var1_32, 4
-
-	.type	var2_32,@object         // @var2_32
-	.globl	var2_32
-	.align	2
-var2_32:
-	.word	0                       // 0x0
-	.size	var2_32, 4
-
-	.type	var1_64,@object         // @var1_64
-	.globl	var1_64
-	.align	3
-var1_64:
-	.xword	0                       // 0x0
-	.size	var1_64, 8
-
-	.type	var2_64,@object         // @var2_64
-	.globl	var2_64
-	.align	3
-var2_64:
-	.xword	0                       // 0x0
-	.size	var2_64, 8
-
-
diff --git a/test/CodeGen/AArch64/movw-consts.ll b/test/CodeGen/AArch64/movw-consts.ll
index b8a5fb9..38e37db 100644
--- a/test/CodeGen/AArch64/movw-consts.ll
+++ b/test/CodeGen/AArch64/movw-consts.ll
@@ -1,50 +1,50 @@
 ; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
 
 define i64 @test0() {
-; CHECK: test0:
+; CHECK-LABEL: test0:
 ; Not produced by move wide instructions, but good to make sure we can return 0 anyway:
 ; CHECK: mov x0, xzr
   ret i64 0
 }
 
 define i64 @test1() {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: movz x0, #1
   ret i64 1
 }
 
 define i64 @test2() {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movz x0, #65535
   ret i64 65535
 }
 
 define i64 @test3() {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: movz x0, #1, lsl #16
   ret i64 65536
 }
 
 define i64 @test4() {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: movz x0, #65535, lsl #16
   ret i64 4294901760
 }
 
 define i64 @test5() {
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: movz x0, #1, lsl #32
   ret i64 4294967296
 }
 
 define i64 @test6() {
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: movz x0, #65535, lsl #32
   ret i64 281470681743360
 }
 
 define i64 @test7() {
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: movz x0, #1, lsl #48
   ret i64 281474976710656
 }
@@ -52,19 +52,19 @@ define i64 @test7() {
 ; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one
 ; couldn't. Useful even for i64
 define i64 @test8() {
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: movn w0, #60875
   ret i64 4294906420
 }
 
 define i64 @test9() {
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: movn x0, #0
   ret i64 -1
 }
 
 define i64 @test10() {
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: movn x0, #60875, lsl #16
   ret i64 18446744069720047615
 }
@@ -74,49 +74,49 @@ define i64 @test10() {
 @var32 = global i32 0
 
 define void @test11() {
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK: mov {{w[0-9]+}}, wzr
   store i32 0, i32* @var32
   ret void
 }
 
 define void @test12() {
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK: movz {{w[0-9]+}}, #1
   store i32 1, i32* @var32
   ret void
 }
 
 define void @test13() {
-; CHECK: test13:
+; CHECK-LABEL: test13:
 ; CHECK: movz {{w[0-9]+}}, #65535
   store i32 65535, i32* @var32
   ret void
 }
 
 define void @test14() {
-; CHECK: test14:
+; CHECK-LABEL: test14:
 ; CHECK: movz {{w[0-9]+}}, #1, lsl #16
   store i32 65536, i32* @var32
   ret void
 }
 
 define void @test15() {
-; CHECK: test15:
+; CHECK-LABEL: test15:
 ; CHECK: movz {{w[0-9]+}}, #65535, lsl #16
   store i32 4294901760, i32* @var32
   ret void
 }
 
 define void @test16() {
-; CHECK: test16:
+; CHECK-LABEL: test16:
 ; CHECK: movn {{w[0-9]+}}, #0
   store i32 -1, i32* @var32
   ret void
 }
 
 define i64 @test17() {
-; CHECK: test17:
+; CHECK-LABEL: test17:
 
   ; Mustn't MOVN w0 here.
 ; CHECK: movn x0, #2
diff --git a/test/CodeGen/AArch64/movw-shift-encoding.ll b/test/CodeGen/AArch64/movw-shift-encoding.ll
new file mode 100644
index 0000000..ec133bd
--- /dev/null
+++ b/test/CodeGen/AArch64/movw-shift-encoding.ll
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=aarch64-linux-gnu < %s -show-mc-encoding -code-model=large | FileCheck %s
+
+@var = global i32 0
+
+; CodeGen should ensure that the correct shift bits are set, because the linker
+; isn't going to!
+
+define i32* @get_var() {
+  ret i32* @var
+; CHECK: movz    x0, #:abs_g3:var        // encoding: [A,A,0xe0'A',0xd2'A']
+; CHECK: movk    x0, #:abs_g2_nc:var     // encoding: [A,A,0xc0'A',0xf2'A']
+; CHECK: movk    x0, #:abs_g1_nc:var     // encoding: [A,A,0xa0'A',0xf2'A']
+; CHECK: movk    x0, #:abs_g0_nc:var     // encoding: [A,A,0x80'A',0xf2'A']
+}
diff --git a/test/CodeGen/AArch64/neon-aba-abd.ll b/test/CodeGen/AArch64/neon-aba-abd.ll
new file mode 100644
index 0000000..b423666
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-aba-abd.ll
@@ -0,0 +1,226 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+declare <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8>, <8 x i8>)
+declare <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @test_uabd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_uabd_v8i8:
+  %abd = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: uabd v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %abd
+}
+
+define <8 x i8> @test_uaba_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_uaba_v8i8:
+  %abd = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+  %aba = add <8 x i8> %lhs, %abd
+; CHECK: uaba v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %aba
+}
+
+define <8 x i8> @test_sabd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_sabd_v8i8:
+  %abd = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: sabd v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %abd
+}
+
+define <8 x i8> @test_saba_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_saba_v8i8:
+  %abd = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+  %aba = add <8 x i8> %lhs, %abd
+; CHECK: saba v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %aba
+}
+
+declare <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_uabd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_uabd_v16i8:
+  %abd = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: uabd v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %abd
+}
+
+define <16 x i8> @test_uaba_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_uaba_v16i8:
+  %abd = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+  %aba = add <16 x i8> %lhs, %abd
+; CHECK: uaba v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %aba
+}
+
+define <16 x i8> @test_sabd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_sabd_v16i8:
+  %abd = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: sabd v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %abd
+}
+
+define <16 x i8> @test_saba_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_saba_v16i8:
+  %abd = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+  %aba = add <16 x i8> %lhs, %abd
+; CHECK: saba v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %aba
+}
+
+declare <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16>, <4 x i16>)
+declare <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @test_uabd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_uabd_v4i16:
+  %abd = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: uabd v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %abd
+}
+
+define <4 x i16> @test_uaba_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_uaba_v4i16:
+  %abd = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+  %aba = add <4 x i16> %lhs, %abd
+; CHECK: uaba v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %aba
+}
+
+define <4 x i16> @test_sabd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_sabd_v4i16:
+  %abd = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: sabd v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %abd
+}
+
+define <4 x i16> @test_saba_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_saba_v4i16:
+  %abd = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+  %aba = add <4 x i16> %lhs, %abd
+; CHECK: saba v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %aba
+}
+
+declare <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test_uabd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_uabd_v8i16:
+  %abd = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: uabd v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %abd
+}
+
+define <8 x i16> @test_uaba_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_uaba_v8i16:
+  %abd = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+  %aba = add <8 x i16> %lhs, %abd
+; CHECK: uaba v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %aba
+}
+
+define <8 x i16> @test_sabd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_sabd_v8i16:
+  %abd = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: sabd v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %abd
+}
+
+define <8 x i16> @test_saba_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_saba_v8i16:
+  %abd = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+  %aba = add <8 x i16> %lhs, %abd
+; CHECK: saba v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %aba
+}
+
+declare <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @test_uabd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_uabd_v2i32:
+  %abd = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: uabd v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %abd
+}
+
+define <2 x i32> @test_uaba_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_uaba_v2i32:
+  %abd = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+  %aba = add <2 x i32> %lhs, %abd
+; CHECK: uaba v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %aba
+}
+
+define <2 x i32> @test_sabd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_sabd_v2i32:
+  %abd = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: sabd v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %abd
+}
+
+define <2 x i32> @test_saba_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_saba_v2i32:
+  %abd = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+  %aba = add <2 x i32> %lhs, %abd
+; CHECK: saba v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %aba
+}
+
+declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @test_uabd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_uabd_v4i32:
+  %abd = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: uabd v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %abd
+}
+
+define <4 x i32> @test_uaba_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_uaba_v4i32:
+  %abd = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+  %aba = add <4 x i32> %lhs, %abd
+; CHECK: uaba v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %aba
+}
+
+define <4 x i32> @test_sabd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_sabd_v4i32:
+  %abd = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: sabd v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %abd
+}
+
+define <4 x i32> @test_saba_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_saba_v4i32:
+  %abd = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+  %aba = add <4 x i32> %lhs, %abd
+; CHECK: saba v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %aba
+}
+
+declare <2 x float> @llvm.arm.neon.vabds.v2f32(<2 x float>, <2 x float>)
+
+define <2 x float> @test_fabd_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
+; CHECK: test_fabd_v2f32:
+  %abd = call <2 x float> @llvm.arm.neon.vabds.v2f32(<2 x float> %lhs, <2 x float> %rhs)
+; CHECK: fabd v0.2s, v0.2s, v1.2s
+  ret <2 x float> %abd
+}
+
+declare <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float>, <4 x float>)
+
+define <4 x float> @test_fabd_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
+; CHECK: test_fabd_v4f32:
+  %abd = call <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float> %lhs, <4 x float> %rhs)
+; CHECK: fabd v0.4s, v0.4s, v1.4s
+  ret <4 x float> %abd
+}
+
+declare <2 x double> @llvm.arm.neon.vabds.v2f64(<2 x double>, <2 x double>)
+
+define <2 x double> @test_fabd_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
+; CHECK: test_fabd_v2f64:
+  %abd = call <2 x double> @llvm.arm.neon.vabds.v2f64(<2 x double> %lhs, <2 x double> %rhs)
+; CHECK: fabd v0.2d, v0.2d, v1.2d
+  ret <2 x double> %abd
+}
\ No newline at end of file
diff --git a/test/CodeGen/AArch64/neon-add-pairwise.ll b/test/CodeGen/AArch64/neon-add-pairwise.ll
new file mode 100644
index 0000000..1abfed3
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-add-pairwise.ll
@@ -0,0 +1,92 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+declare <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @test_addp_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; CHECK: test_addp_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: addp v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+declare <16 x i8> @llvm.arm.neon.vpadd.v16i8(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_addp_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_addp_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vpadd.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: addp v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+declare <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @test_addp_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_addp_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: addp v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+declare <8 x i16> @llvm.arm.neon.vpadd.v8i16(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test_addp_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_addp_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vpadd.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: addp v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @test_addp_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_addp_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: addp v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+declare <4 x i32> @llvm.arm.neon.vpadd.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @test_addp_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_addp_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vpadd.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: addp v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+
+declare <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64>, <2 x i64>)
+
+define <2 x i64> @test_addp_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
+; CHECK: test_addp_v2i64:
+        %val = call <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
+; CHECK: addp v0.2d, v0.2d, v1.2d
+        ret <2 x i64> %val
+}
+
+declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.arm.neon.vpadd.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.arm.neon.vpadd.v2f64(<2 x double>, <2 x double>)
+
+define <2 x float> @test_faddp_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
+; CHECK: test_faddp_v2f32:
+        %val = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %lhs, <2 x float> %rhs)
+; CHECK: faddp v0.2s, v0.2s, v1.2s
+        ret <2 x float> %val
+}
+
+define <4 x float> @test_faddp_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
+; CHECK: test_faddp_v4f32:
+        %val = call <4 x float> @llvm.arm.neon.vpadd.v4f32(<4 x float> %lhs, <4 x float> %rhs)
+; CHECK: faddp v0.4s, v0.4s, v1.4s
+        ret <4 x float> %val
+}
+
+define <2 x double> @test_faddp_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
+; CHECK: test_faddp_v2f64:
+        %val = call <2 x double> @llvm.arm.neon.vpadd.v2f64(<2 x double> %lhs, <2 x double> %rhs)
+; CHECK: faddp v0.2d, v0.2d, v1.2d
+        ret <2 x double> %val
+}
+
diff --git a/test/CodeGen/AArch64/neon-add-sub.ll b/test/CodeGen/AArch64/neon-add-sub.ll
new file mode 100644
index 0000000..65ec8a2
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-add-sub.ll
@@ -0,0 +1,132 @@
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
+
+define <8 x i8> @add8xi8(<8 x i8> %A, <8 x i8> %B) {
+;CHECK: add {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp3 = add <8 x i8> %A, %B;
+	ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @add16xi8(<16 x i8> %A, <16 x i8> %B) {
+;CHECK: add {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp3 = add <16 x i8> %A, %B;
+	ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @add4xi16(<4 x i16> %A, <4 x i16> %B) {
+;CHECK: add {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
+	%tmp3 = add <4 x i16> %A, %B;
+	ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @add8xi16(<8 x i16> %A, <8 x i16> %B) {
+;CHECK: add {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
+	%tmp3 = add <8 x i16> %A, %B;
+	ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @add2xi32(<2 x i32> %A, <2 x i32> %B) {
+;CHECK: add {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
+	%tmp3 = add <2 x i32> %A, %B;
+	ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @add4x32(<4 x i32> %A, <4 x i32> %B) {
+;CHECK: add {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
+	%tmp3 = add <4 x i32> %A, %B;
+	ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @add2xi64(<2 x i64> %A, <2 x i64> %B) {
+;CHECK: add {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
+	%tmp3 = add <2 x i64> %A, %B;
+	ret <2 x i64> %tmp3
+}
+
+define <2 x float> @add2xfloat(<2 x float> %A, <2 x float> %B) {
+;CHECK: fadd {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
+	%tmp3 = fadd <2 x float> %A, %B;
+	ret <2 x float> %tmp3
+}
+
+define <4 x float> @add4xfloat(<4 x float> %A, <4 x float> %B) {
+;CHECK: fadd {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
+	%tmp3 = fadd <4 x float> %A, %B;
+	ret <4 x float> %tmp3
+}
+define <2 x double> @add2xdouble(<2 x double> %A, <2 x double> %B) {
+;CHECK: add {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
+	%tmp3 = fadd <2 x double> %A, %B;
+	ret <2 x double> %tmp3
+}
+
+define <8 x i8> @sub8xi8(<8 x i8> %A, <8 x i8> %B) {
+;CHECK: sub {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp3 = sub <8 x i8> %A, %B;
+	ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @sub16xi8(<16 x i8> %A, <16 x i8> %B) {
+;CHECK: sub {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp3 = sub <16 x i8> %A, %B;
+	ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @sub4xi16(<4 x i16> %A, <4 x i16> %B) {
+;CHECK: sub {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
+	%tmp3 = sub <4 x i16> %A, %B;
+	ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @sub8xi16(<8 x i16> %A, <8 x i16> %B) {
+;CHECK: sub {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
+	%tmp3 = sub <8 x i16> %A, %B;
+	ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @sub2xi32(<2 x i32> %A, <2 x i32> %B) {
+;CHECK: sub {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
+	%tmp3 = sub <2 x i32> %A, %B;
+	ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @sub4x32(<4 x i32> %A, <4 x i32> %B) {
+;CHECK: sub {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
+	%tmp3 = sub <4 x i32> %A, %B;
+	ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @sub2xi64(<2 x i64> %A, <2 x i64> %B) {
+;CHECK: sub {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
+	%tmp3 = sub <2 x i64> %A, %B;
+	ret <2 x i64> %tmp3
+}
+
+define <2 x float> @sub2xfloat(<2 x float> %A, <2 x float> %B) {
+;CHECK: fsub {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
+	%tmp3 = fsub <2 x float> %A, %B;
+	ret <2 x float> %tmp3
+}
+
+define <4 x float> @sub4xfloat(<4 x float> %A, <4 x float> %B) {
+;CHECK: fsub {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
+	%tmp3 = fsub <4 x float> %A, %B;
+	ret <4 x float> %tmp3
+}
+define <2 x double> @sub2xdouble(<2 x double> %A, <2 x double> %B) {
+;CHECK: sub {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
+	%tmp3 = fsub <2 x double> %A, %B;
+	ret <2 x double> %tmp3
+}
+
+define <1 x i64> @add1xi64(<1 x i64> %A, <1 x i64> %B) {
+;CHECK: add {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
+	%tmp3 = add <1 x i64> %A, %B;
+	ret <1 x i64> %tmp3
+}
+
+define <1 x i64> @sub1xi64(<1 x i64> %A, <1 x i64> %B) {
+;CHECK: sub {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
+	%tmp3 = sub <1 x i64> %A, %B;
+	ret <1 x i64> %tmp3
+}
+
diff --git a/test/CodeGen/AArch64/neon-bitcast.ll b/test/CodeGen/AArch64/neon-bitcast.ll
new file mode 100644
index 0000000..f9ec704
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-bitcast.ll
@@ -0,0 +1,574 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -verify-machineinstrs < %s | FileCheck %s
+
+; From <8 x i8>
+
+define <1 x i64> @test_v8i8_to_v1i64(<8 x i8> %in) nounwind {
+; CHECK: test_v8i8_to_v1i64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <8 x i8> %in to <1 x i64>
+  ret <1 x i64> %val
+}
+
+define <2 x i32> @test_v8i8_to_v2i32(<8 x i8> %in) nounwind {
+; CHECK: test_v8i8_to_v2i32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <8 x i8> %in to <2 x i32>
+  ret <2 x i32> %val
+}
+
+define <2 x float> @test_v8i8_to_v1f32(<8 x i8> %in) nounwind{
+; CHECK: test_v8i8_to_v1f32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <8 x i8> %in to <2 x float>
+  ret <2 x float> %val
+}
+
+define <4 x i16> @test_v8i8_to_v4i16(<8 x i8> %in) nounwind{
+; CHECK: test_v8i8_to_v4i16:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <8 x i8> %in to <4 x i16>
+  ret <4 x i16> %val
+}
+
+define <8 x i8> @test_v8i8_to_v8i8(<8 x i8> %in) nounwind{
+; CHECK: test_v8i8_to_v8i8:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <8 x i8> %in to <8 x i8>
+  ret <8 x i8> %val
+}
+
+; From <4 x i16>
+
+define <1 x i64> @test_v4i16_to_v1i64(<4 x i16> %in) nounwind {
+; CHECK: test_v4i16_to_v1i64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x i16> %in to <1 x i64>
+  ret <1 x i64> %val
+}
+
+define <2 x i32> @test_v4i16_to_v2i32(<4 x i16> %in) nounwind {
+; CHECK: test_v4i16_to_v2i32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x i16> %in to <2 x i32>
+  ret <2 x i32> %val
+}
+
+define <2 x float> @test_v4i16_to_v1f32(<4 x i16> %in) nounwind{
+; CHECK: test_v4i16_to_v1f32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x i16> %in to <2 x float>
+  ret <2 x float> %val
+}
+
+define <4 x i16> @test_v4i16_to_v4i16(<4 x i16> %in) nounwind{
+; CHECK: test_v4i16_to_v4i16:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x i16> %in to <4 x i16>
+  ret <4 x i16> %val
+}
+
+define <8 x i8> @test_v4i16_to_v8i8(<4 x i16> %in) nounwind{
+; CHECK: test_v4i16_to_v8i8:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x i16> %in to <8 x i8>
+  ret <8 x i8> %val
+}
+
+; From <2 x i32>
+
+define <1 x i64> @test_v2i32_to_v1i64(<2 x i32> %in) nounwind {
+; CHECK: test_v2i32_to_v1i64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x i32> %in to <1 x i64>
+  ret <1 x i64> %val
+}
+
+define <2 x i32> @test_v2i32_to_v2i32(<2 x i32> %in) nounwind {
+; CHECK: test_v2i32_to_v2i32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x i32> %in to <2 x i32>
+  ret <2 x i32> %val
+}
+
+define <2 x float> @test_v2i32_to_v1f32(<2 x i32> %in) nounwind{
+; CHECK: test_v2i32_to_v1f32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x i32> %in to <2 x float>
+  ret <2 x float> %val
+}
+
+define <4 x i16> @test_v2i32_to_v4i16(<2 x i32> %in) nounwind{
+; CHECK: test_v2i32_to_v4i16:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x i32> %in to <4 x i16>
+  ret <4 x i16> %val
+}
+
+define <8 x i8> @test_v2i32_to_v8i8(<2 x i32> %in) nounwind{
+; CHECK: test_v2i32_to_v8i8:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x i32> %in to <8 x i8>
+  ret <8 x i8> %val
+}
+
+; From <2 x float>
+
+define <1 x i64> @test_v2f32_to_v1i64(<2 x float> %in) nounwind {
+; CHECK: test_v2f32_to_v1i64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x float> %in to <1 x i64>
+  ret <1 x i64> %val
+}
+
+define <2 x i32> @test_v2f32_to_v2i32(<2 x float> %in) nounwind {
+; CHECK: test_v2f32_to_v2i32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x float> %in to <2 x i32>
+  ret <2 x i32> %val
+}
+
+define <2 x float> @test_v2f32_to_v2f32(<2 x float> %in) nounwind{
+; CHECK: test_v2f32_to_v2f32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x float> %in to <2 x float>
+  ret <2 x float> %val
+}
+
+define <4 x i16> @test_v2f32_to_v4i16(<2 x float> %in) nounwind{
+; CHECK: test_v2f32_to_v4i16:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x float> %in to <4 x i16>
+  ret <4 x i16> %val
+}
+
+define <8 x i8> @test_v2f32_to_v8i8(<2 x float> %in) nounwind{
+; CHECK: test_v2f32_to_v8i8:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x float> %in to <8 x i8>
+  ret <8 x i8> %val
+}
+
+; From <1 x i64>
+
+define <1 x i64> @test_v1i64_to_v1i64(<1 x i64> %in) nounwind {
+; CHECK: test_v1i64_to_v1i64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <1 x i64> %in to <1 x i64>
+  ret <1 x i64> %val
+}
+
+define <2 x i32> @test_v1i64_to_v2i32(<1 x i64> %in) nounwind {
+; CHECK: test_v1i64_to_v2i32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <1 x i64> %in to <2 x i32>
+  ret <2 x i32> %val
+}
+
+define <2 x float> @test_v1i64_to_v2f32(<1 x i64> %in) nounwind{
+; CHECK: test_v1i64_to_v2f32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <1 x i64> %in to <2 x float>
+  ret <2 x float> %val
+}
+
+define <4 x i16> @test_v1i64_to_v4i16(<1 x i64> %in) nounwind{
+; CHECK: test_v1i64_to_v4i16:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <1 x i64> %in to <4 x i16>
+  ret <4 x i16> %val
+}
+
+define <8 x i8> @test_v1i64_to_v8i8(<1 x i64> %in) nounwind{
+; CHECK: test_v1i64_to_v8i8:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <1 x i64> %in to <8 x i8>
+  ret <8 x i8> %val
+}
+
+
+; From <16 x i8>
+
+define <2 x double> @test_v16i8_to_v2f64(<16 x i8> %in) nounwind {
+; CHECK: test_v16i8_to_v2f64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <16 x i8> %in to <2 x double>
+  ret <2 x double> %val
+}
+
+define <2 x i64> @test_v16i8_to_v2i64(<16 x i8> %in) nounwind {
+; CHECK: test_v16i8_to_v2i64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <16 x i8> %in to <2 x i64>
+  ret <2 x i64> %val
+}
+
+define <4 x i32> @test_v16i8_to_v4i32(<16 x i8> %in) nounwind {
+; CHECK: test_v16i8_to_v4i32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <16 x i8> %in to <4 x i32>
+  ret <4 x i32> %val
+}
+
+define <4 x float> @test_v16i8_to_v2f32(<16 x i8> %in) nounwind{
+; CHECK: test_v16i8_to_v2f32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <16 x i8> %in to <4 x float>
+  ret <4 x float> %val
+}
+
+define <8 x i16> @test_v16i8_to_v8i16(<16 x i8> %in) nounwind{
+; CHECK: test_v16i8_to_v8i16:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <16 x i8> %in to <8 x i16>
+  ret <8 x i16> %val
+}
+
+define <16 x i8> @test_v16i8_to_v16i8(<16 x i8> %in) nounwind{
+; CHECK: test_v16i8_to_v16i8:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <16 x i8> %in to <16 x i8>
+  ret <16 x i8> %val
+}
+
+; From <8 x i16>
+
+define <2 x double> @test_v8i16_to_v2f64(<8 x i16> %in) nounwind {
+; CHECK: test_v8i16_to_v2f64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <8 x i16> %in to <2 x double>
+  ret <2 x double> %val
+}
+
+define <2 x i64> @test_v8i16_to_v2i64(<8 x i16> %in) nounwind {
+; CHECK: test_v8i16_to_v2i64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <8 x i16> %in to <2 x i64>
+  ret <2 x i64> %val
+}
+
+define <4 x i32> @test_v8i16_to_v4i32(<8 x i16> %in) nounwind {
+; CHECK: test_v8i16_to_v4i32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <8 x i16> %in to <4 x i32>
+  ret <4 x i32> %val
+}
+
+define <4 x float> @test_v8i16_to_v2f32(<8 x i16> %in) nounwind{
+; CHECK: test_v8i16_to_v2f32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <8 x i16> %in to <4 x float>
+  ret <4 x float> %val
+}
+
+define <8 x i16> @test_v8i16_to_v8i16(<8 x i16> %in) nounwind{
+; CHECK: test_v8i16_to_v8i16:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <8 x i16> %in to <8 x i16>
+  ret <8 x i16> %val
+}
+
+define <16 x i8> @test_v8i16_to_v16i8(<8 x i16> %in) nounwind{
+; CHECK: test_v8i16_to_v16i8:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <8 x i16> %in to <16 x i8>
+  ret <16 x i8> %val
+}
+
+; From <4 x i32>
+
+define <2 x double> @test_v4i32_to_v2f64(<4 x i32> %in) nounwind {
+; CHECK: test_v4i32_to_v2f64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x i32> %in to <2 x double>
+  ret <2 x double> %val
+}
+
+define <2 x i64> @test_v4i32_to_v2i64(<4 x i32> %in) nounwind {
+; CHECK: test_v4i32_to_v2i64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x i32> %in to <2 x i64>
+  ret <2 x i64> %val
+}
+
+define <4 x i32> @test_v4i32_to_v4i32(<4 x i32> %in) nounwind {
+; CHECK: test_v4i32_to_v4i32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x i32> %in to <4 x i32>
+  ret <4 x i32> %val
+}
+
+define <4 x float> @test_v4i32_to_v2f32(<4 x i32> %in) nounwind{
+; CHECK: test_v4i32_to_v2f32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x i32> %in to <4 x float>
+  ret <4 x float> %val
+}
+
+define <8 x i16> @test_v4i32_to_v8i16(<4 x i32> %in) nounwind{
+; CHECK: test_v4i32_to_v8i16:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x i32> %in to <8 x i16>
+  ret <8 x i16> %val
+}
+
+define <16 x i8> @test_v4i32_to_v16i8(<4 x i32> %in) nounwind{
+; CHECK: test_v4i32_to_v16i8:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x i32> %in to <16 x i8>
+  ret <16 x i8> %val
+}
+
+; From <4 x float>
+
+define <2 x double> @test_v4f32_to_v2f64(<4 x float> %in) nounwind {
+; CHECK: test_v4f32_to_v2f64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x float> %in to <2 x double>
+  ret <2 x double> %val
+}
+
+define <2 x i64> @test_v4f32_to_v2i64(<4 x float> %in) nounwind {
+; CHECK: test_v4f32_to_v2i64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x float> %in to <2 x i64>
+  ret <2 x i64> %val
+}
+
+define <4 x i32> @test_v4f32_to_v4i32(<4 x float> %in) nounwind {
+; CHECK: test_v4f32_to_v4i32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x float> %in to <4 x i32>
+  ret <4 x i32> %val
+}
+
+define <4 x float> @test_v4f32_to_v4f32(<4 x float> %in) nounwind{
+; CHECK: test_v4f32_to_v4f32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x float> %in to <4 x float>
+  ret <4 x float> %val
+}
+
+define <8 x i16> @test_v4f32_to_v8i16(<4 x float> %in) nounwind{
+; CHECK: test_v4f32_to_v8i16:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x float> %in to <8 x i16>
+  ret <8 x i16> %val
+}
+
+define <16 x i8> @test_v4f32_to_v16i8(<4 x float> %in) nounwind{
+; CHECK: test_v4f32_to_v16i8:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <4 x float> %in to <16 x i8>
+  ret <16 x i8> %val
+}
+
+; From <2 x i64>
+
+define <2 x double> @test_v2i64_to_v2f64(<2 x i64> %in) nounwind {
+; CHECK: test_v2i64_to_v2f64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x i64> %in to <2 x double>
+  ret <2 x double> %val
+}
+
+define <2 x i64> @test_v2i64_to_v2i64(<2 x i64> %in) nounwind {
+; CHECK: test_v2i64_to_v2i64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x i64> %in to <2 x i64>
+  ret <2 x i64> %val
+}
+
+define <4 x i32> @test_v2i64_to_v4i32(<2 x i64> %in) nounwind {
+; CHECK: test_v2i64_to_v4i32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x i64> %in to <4 x i32>
+  ret <4 x i32> %val
+}
+
+define <4 x float> @test_v2i64_to_v4f32(<2 x i64> %in) nounwind{
+; CHECK: test_v2i64_to_v4f32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x i64> %in to <4 x float>
+  ret <4 x float> %val
+}
+
+define <8 x i16> @test_v2i64_to_v8i16(<2 x i64> %in) nounwind{
+; CHECK: test_v2i64_to_v8i16:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x i64> %in to <8 x i16>
+  ret <8 x i16> %val
+}
+
+define <16 x i8> @test_v2i64_to_v16i8(<2 x i64> %in) nounwind{
+; CHECK: test_v2i64_to_v16i8:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x i64> %in to <16 x i8>
+  ret <16 x i8> %val
+}
+
+; From <2 x double>
+
+define <2 x double> @test_v2f64_to_v2f64(<2 x double> %in) nounwind {
+; CHECK: test_v2f64_to_v2f64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x double> %in to <2 x double>
+  ret <2 x double> %val
+}
+
+define <2 x i64> @test_v2f64_to_v2i64(<2 x double> %in) nounwind {
+; CHECK: test_v2f64_to_v2i64:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x double> %in to <2 x i64>
+  ret <2 x i64> %val
+}
+
+define <4 x i32> @test_v2f64_to_v4i32(<2 x double> %in) nounwind {
+; CHECK: test_v2f64_to_v4i32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x double> %in to <4 x i32>
+  ret <4 x i32> %val
+}
+
+define <4 x float> @test_v2f64_to_v4f32(<2 x double> %in) nounwind{
+; CHECK: test_v2f64_to_v4f32:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x double> %in to <4 x float>
+  ret <4 x float> %val
+}
+
+define <8 x i16> @test_v2f64_to_v8i16(<2 x double> %in) nounwind{
+; CHECK: test_v2f64_to_v8i16:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x double> %in to <8 x i16>
+  ret <8 x i16> %val
+}
+
+define <16 x i8> @test_v2f64_to_v16i8(<2 x double> %in) nounwind{
+; CHECK: test_v2f64_to_v16i8:
+; CHECK-NEXT: // BB#0:
+; CHECK-NEXT: ret
+
+  %val = bitcast <2 x double> %in to <16 x i8>
+  ret <16 x i8> %val
+}
+
diff --git a/test/CodeGen/AArch64/neon-bitwise-instructions.ll b/test/CodeGen/AArch64/neon-bitwise-instructions.ll
new file mode 100644
index 0000000..1c43b97
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-bitwise-instructions.ll
@@ -0,0 +1,594 @@
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
+
+
+define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) {
+;CHECK: and {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = and <8 x i8> %a, %b;
+	ret <8 x i8> %tmp1
+}
+
+define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) {
+;CHECK: and {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = and <16 x i8> %a, %b;
+	ret <16 x i8> %tmp1
+}
+
+
+define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) {
+;CHECK: orr {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = or <8 x i8> %a, %b;
+	ret <8 x i8> %tmp1
+}
+
+define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) {
+;CHECK: orr {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = or <16 x i8> %a, %b;
+	ret <16 x i8> %tmp1
+}
+
+
+define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) {
+;CHECK: eor {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = xor <8 x i8> %a, %b;
+	ret <8 x i8> %tmp1
+}
+
+define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) {
+;CHECK: eor {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = xor <16 x i8> %a, %b;
+	ret <16 x i8> %tmp1
+}
+
+define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b)  {
+;CHECK:  bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+	%tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0 >
+	%tmp3 = or <8 x i8> %tmp1, %tmp2
+	ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) {
+;CHECK:  bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+	%tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0 >
+	%tmp3 = or <16 x i8> %tmp1, %tmp2
+	ret <16 x i8> %tmp3
+}
+
+define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b)  {
+;CHECK:  orn {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+  %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+  %tmp2 = or <8 x i8> %a, %tmp1
+  ret <8 x i8> %tmp2
+}
+
+define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) {
+;CHECK:  orn {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+  %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+  %tmp2 = or <16 x i8> %a, %tmp1
+  ret <16 x i8> %tmp2
+}
+
+define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b)  {
+;CHECK:  bic {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+  %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+  %tmp2 = and <8 x i8> %a, %tmp1
+  ret <8 x i8> %tmp2
+}
+
+define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) {
+;CHECK:  bic {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+  %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+  %tmp2 = and <16 x i8> %a, %tmp1
+  ret <16 x i8> %tmp2
+}
+
+define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) {
+;CHECK:  orr {{v[0-31]+}}.2s, #0xff
+	%tmp1 = or <2 x i32> %a, < i32 255, i32 255>
+	ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) {
+;CHECK:  orr {{v[0-31]+}}.2s, #0xff, lsl #8
+	%tmp1 = or <2 x i32> %a, < i32 65280, i32 65280>
+	ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) {
+;CHECK:  orr {{v[0-31]+}}.2s, #0xff, lsl #16
+	%tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680>
+	ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) {
+;CHECK:  orr {{v[0-31]+}}.2s, #0xff, lsl #24
+	%tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080>
+	ret <2 x i32> %tmp1
+}
+
+define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) {
+;CHECK:  orr {{v[0-31]+}}.4s, #0xff
+	%tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255>
+	ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) {
+;CHECK:  orr {{v[0-31]+}}.4s, #0xff, lsl #8
+	%tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280>
+	ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) {
+;CHECK:  orr {{v[0-31]+}}.4s, #0xff, lsl #16
+	%tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680>
+	ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) {
+;CHECK:  orr {{v[0-31]+}}.4s, #0xff, lsl #24
+	%tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080>
+	ret <4 x i32> %tmp1
+}
+
+define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) {
+;CHECK:  orr {{v[0-31]+}}.4h, #0xff
+	%tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 >
+	ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) {
+;CHECK:  orr {{v[0-31]+}}.4h, #0xff, lsl #8
+	%tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
+	ret <4 x i16> %tmp1
+}
+
+define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) {
+;CHECK:  orr {{v[0-31]+}}.8h, #0xff
+	%tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
+	ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) {
+;CHECK:  orr {{v[0-31]+}}.8h, #0xff, lsl #8
+	%tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
+	ret <8 x i16> %tmp1
+}
+
+define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) {
+;CHECK:  bic {{v[0-31]+}}.2s, #0x10
+	%tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 >
+	ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) {
+;CHECK:  bic {{v[0-31]+}}.2s, #0x10, lsl #8
+	%tmp1 = and <2 x i32> %a, < i32 18446744073709547519, i32  18446744073709547519 >
+	ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) {
+;CHECK:  bic {{v[0-31]+}}.2s, #0x10, lsl #16
+	%tmp1 = and <2 x i32> %a, < i32 18446744073708503039, i32 18446744073708503039 >
+	ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) {
+;CHECK:  bic {{v[0-31]+}}.2s, #0x10, lsl #24
+	%tmp1 = and <2 x i32> %a, < i32 18446744073441116159, i32  18446744073441116159>
+	ret <2 x i32> %tmp1
+}
+
+define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) {
+;CHECK:  bic {{v[0-31]+}}.4s, #0x10
+	%tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
+	ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) {
+;CHECK:  bic {{v[0-31]+}}.4s, #0x10, lsl #8
+	%tmp1 = and <4 x i32> %a, < i32 18446744073709547519, i32  18446744073709547519, i32  18446744073709547519, i32  18446744073709547519 >
+	ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) {
+;CHECK:  bic {{v[0-31]+}}.4s, #0x10, lsl #16
+	%tmp1 = and <4 x i32> %a, < i32 18446744073708503039, i32 18446744073708503039, i32 18446744073708503039, i32 18446744073708503039 >
+	ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) {
+;CHECK:  bic {{v[0-31]+}}.4s, #0x10, lsl #24
+	%tmp1 = and <4 x i32> %a, < i32 18446744073441116159, i32  18446744073441116159, i32  18446744073441116159, i32  18446744073441116159>
+	ret <4 x i32> %tmp1
+}
+
+define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) {
+;CHECK:  bic {{v[0-31]+}}.4h, #0x10
+	%tmp1 = and <4 x i16> %a, < i16 18446744073709551599, i16  18446744073709551599, i16  18446744073709551599, i16  18446744073709551599 >
+	ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) {
+;CHECK:  bic {{v[0-31]+}}.4h, #0x0
+	%tmp1 = and <4 x i16> %a, < i16 65280, i16  65280, i16  65280, i16 65280 >
+	ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) {
+;CHECK:  bic {{v[0-31]+}}.4h, #0x10, lsl #8
+	%tmp1 = and <4 x i16> %a, < i16 18446744073709547519, i16  18446744073709547519, i16  18446744073709547519, i16  18446744073709547519>
+	ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) {
+;CHECK:  bic {{v[0-31]+}}.4h, #0x0, lsl #8
+	%tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255>
+	ret <4 x i16> %tmp1
+}
+
+define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) {
+;CHECK:  bic {{v[0-31]+}}.8h, #0x10
+	%tmp1 = and <8 x i16> %a, < i16 18446744073709551599, i16  18446744073709551599, i16  18446744073709551599, i16  18446744073709551599,
+   i16  18446744073709551599, i16  18446744073709551599, i16  18446744073709551599, i16  18446744073709551599 >
+	ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) {
+;CHECK:  bic {{v[0-31]+}}.8h, #0x0
+	%tmp1 = and <8 x i16> %a, < i16 65280, i16  65280, i16  65280, i16 65280, i16 65280, i16  65280, i16  65280, i16 65280 >
+	ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) {
+;CHECK:  bic {{v[0-31]+}}.8h, #0x10, lsl #8
+	%tmp1 = and <8 x i16> %a, < i16 18446744073709547519, i16  18446744073709547519, i16  18446744073709547519, i16  18446744073709547519,
+   i16  18446744073709547519, i16  18446744073709547519, i16  18446744073709547519, i16  18446744073709547519>
+	ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) {
+;CHECK:  bic {{v[0-31]+}}.8h, #0x0, lsl #8
+	%tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+	ret <8 x i16> %tmp1
+}
+
+define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) {
+;CHECK: and {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = and <2 x i32> %a, %b;
+	ret <2 x i32> %tmp1
+}
+
+define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) {
+;CHECK: and {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = and <4 x i16> %a, %b;
+	ret <4 x i16> %tmp1
+}
+
+define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) {
+;CHECK: and {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = and <1 x i64> %a, %b;
+	ret <1 x i64> %tmp1
+}
+
+define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) {
+;CHECK: and {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = and <4 x i32> %a, %b;
+	ret <4 x i32> %tmp1
+}
+
+define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) {
+;CHECK: and {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = and <8 x i16> %a, %b;
+	ret <8 x i16> %tmp1
+}
+
+define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) {
+;CHECK: and {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = and <2 x i64> %a, %b;
+	ret <2 x i64> %tmp1
+}
+
+define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) {
+;CHECK: orr {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = or <2 x i32> %a, %b;
+	ret <2 x i32> %tmp1
+}
+
+define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) {
+;CHECK: orr {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = or <4 x i16> %a, %b;
+	ret <4 x i16> %tmp1
+}
+
+define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) {
+;CHECK: orr {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = or <1 x i64> %a, %b;
+	ret <1 x i64> %tmp1
+}
+
+define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) {
+;CHECK: orr {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = or <4 x i32> %a, %b;
+	ret <4 x i32> %tmp1
+}
+
+define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) {
+;CHECK: orr {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = or <8 x i16> %a, %b;
+	ret <8 x i16> %tmp1
+}
+
+define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) {
+;CHECK: orr {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = or <2 x i64> %a, %b;
+	ret <2 x i64> %tmp1
+}
+
+define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) {
+;CHECK: eor {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = xor <2 x i32> %a, %b;
+	ret <2 x i32> %tmp1
+}
+
+define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) {
+;CHECK: eor {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = xor <4 x i16> %a, %b;
+	ret <4 x i16> %tmp1
+}
+
+define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) {
+;CHECK: eor {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = xor <1 x i64> %a, %b;
+	ret <1 x i64> %tmp1
+}
+
+define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) {
+;CHECK: eor {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = xor <4 x i32> %a, %b;
+	ret <4 x i32> %tmp1
+}
+
+define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) {
+;CHECK: eor {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = xor <8 x i16> %a, %b;
+	ret <8 x i16> %tmp1
+}
+
+define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) {
+;CHECK: eor {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = xor <2 x i64> %a, %b;
+	ret <2 x i64> %tmp1
+}
+
+
+define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b)  {
+;CHECK:  bic {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+  %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
+  %tmp2 = and <2 x i32> %a, %tmp1
+  ret <2 x i32> %tmp2
+}
+
+define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b)  {
+;CHECK:  bic {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+  %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
+  %tmp2 = and <4 x i16> %a, %tmp1
+  ret <4 x i16> %tmp2
+}
+
+define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b)  {
+;CHECK:  bic {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+  %tmp1 = xor <1 x i64> %b, < i64 -1>
+  %tmp2 = and <1 x i64> %a, %tmp1
+  ret <1 x i64> %tmp2
+}
+
+define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b)  {
+;CHECK:  bic {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+  %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
+  %tmp2 = and <4 x i32> %a, %tmp1
+  ret <4 x i32> %tmp2
+}
+
+define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b)  {
+;CHECK:  bic {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+  %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
+  %tmp2 = and <8 x i16> %a, %tmp1
+  ret <8 x i16> %tmp2
+}
+
+define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b)  {
+;CHECK:  bic {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+  %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
+  %tmp2 = and <2 x i64> %a, %tmp1
+  ret <2 x i64> %tmp2
+}
+
+define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b)  {
+;CHECK:  orn {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+  %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
+  %tmp2 = or <2 x i32> %a, %tmp1
+  ret <2 x i32> %tmp2
+}
+
+define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b)  {
+;CHECK:  orn {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+  %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
+  %tmp2 = or <4 x i16> %a, %tmp1
+  ret <4 x i16> %tmp2
+}
+
+define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b)  {
+;CHECK:  orn {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+  %tmp1 = xor <1 x i64> %b, < i64 -1>
+  %tmp2 = or <1 x i64> %a, %tmp1
+  ret <1 x i64> %tmp2
+}
+
+define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b)  {
+;CHECK:  orn {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+  %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
+  %tmp2 = or <4 x i32> %a, %tmp1
+  ret <4 x i32> %tmp2
+}
+
+define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b)  {
+;CHECK:  orn {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+  %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
+  %tmp2 = or <8 x i16> %a, %tmp1
+  ret <8 x i16> %tmp2
+}
+
+define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b)  {
+;CHECK:  orn {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+  %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
+  %tmp2 = or <2 x i64> %a, %tmp1
+  ret <2 x i64> %tmp2
+}
+define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b)  {
+;CHECK:  bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = and <2 x i32> %a, < i32 -1, i32 -1 >
+	%tmp2 = and <2 x i32> %b, < i32 0, i32 0 >
+	%tmp3 = or <2 x i32> %tmp1, %tmp2
+	ret <2 x i32> %tmp3
+}
+
+
+define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b)  {
+;CHECK:  bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = and <4 x i16> %a, < i16 -1, i16 -1, i16 -1,i16 -1 >
+	%tmp2 = and <4 x i16> %b, < i16 0, i16 0,i16 0, i16 0 >
+	%tmp3 = or <4 x i16> %tmp1, %tmp2
+	ret <4 x i16> %tmp3
+}
+
+define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b)  {
+;CHECK:  bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = and <1 x i64> %a, < i64 -1 >
+	%tmp2 = and <1 x i64> %b, < i64 0 >
+	%tmp3 = or <1 x i64> %tmp1, %tmp2
+	ret <1 x i64> %tmp3
+}
+
+define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b)  {
+;CHECK:  bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = and <4 x i32> %a, < i32 -1, i32 -1, i32 -1, i32 -1 >
+	%tmp2 = and <4 x i32> %b, < i32 0, i32 0, i32 0, i32 0 >
+	%tmp3 = or <4 x i32> %tmp1, %tmp2
+	ret <4 x i32> %tmp3
+}
+
+define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b)  {
+;CHECK:  bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 -1,i16 -1, i16 -1, i16 -1, i16 -1,i16 -1 >
+	%tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0 >
+	%tmp3 = or <8 x i16> %tmp1, %tmp2
+	ret <8 x i16> %tmp3
+}
+
+define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b)  {
+;CHECK:  bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = and <2 x i64> %a, < i64 -1, i64 -1 >
+	%tmp2 = and <2 x i64> %b, < i64 0, i64 0 >
+	%tmp3 = or <2 x i64> %tmp1, %tmp2
+	ret <2 x i64> %tmp3
+}
+
+
+define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {
+;CHECK:  bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+  %1 = and <8 x i8> %v1, %v2
+  %2 = xor <8 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %3 = and <8 x i8> %2, %v3
+  %4 = or <8 x i8> %1, %3
+  ret <8 x i8> %4
+}
+
+define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) {
+;CHECK:  bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+  %1 = and <4 x i16> %v1, %v2
+  %2 = xor <4 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1>
+  %3 = and <4 x i16> %2, %v3
+  %4 = or <4 x i16> %1, %3
+  ret <4 x i16> %4
+}
+
+define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {
+;CHECK:  bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+  %1 = and <2 x i32> %v1, %v2
+  %2 = xor <2 x i32> %v1, <i32 -1, i32 -1>
+  %3 = and <2 x i32> %2, %v3
+  %4 = or <2 x i32> %1, %3
+  ret <2 x i32> %4
+}
+
+define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
+;CHECK:  bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+  %1 = and <1 x i64> %v1, %v2
+  %2 = xor <1 x i64> %v1, <i64 -1>
+  %3 = and <1 x i64> %2, %v3
+  %4 = or <1 x i64> %1, %3
+  ret <1 x i64> %4
+}
+
+define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {
+;CHECK:  bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+  %1 = and <16 x i8> %v1, %v2
+  %2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+  %3 = and <16 x i8> %2, %v3
+  %4 = or <16 x i8> %1, %3
+  ret <16 x i8> %4
+}
+
+define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
+;CHECK:  bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+  %1 = and <8 x i16> %v1, %v2
+  %2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+  %3 = and <8 x i16> %2, %v3
+  %4 = or <8 x i16> %1, %3
+  ret <8 x i16> %4
+}
+
+define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
+;CHECK:  bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+  %1 = and <4 x i32> %v1, %v2
+  %2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %3 = and <4 x i32> %2, %v3
+  %4 = or <4 x i32> %1, %3
+  ret <4 x i32> %4
+}
+
+define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) {
+;CHECK:  bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+  %1 = and <2 x i64> %v1, %v2
+  %2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
+  %3 = and <2 x i64> %2, %v3
+  %4 = or <2 x i64> %1, %3
+  ret <2 x i64> %4
+}
+
+define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) {
+;CHECK:  orr {{v[0-31]+}}.4h, #0xff
+  %val = or <8 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
+  ret <8 x i8> %val
+}
+
+define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) {
+;CHECK:  orr {{v[0-31]+}}.4h, #0xff, lsl #8
+  %val = or <8 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
+  ret <8 x i8> %val
+}
+
+define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) {
+;CHECK:  orr {{v[0-31]+}}.8h, #0xff
+  %val = or <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
+  ret <16 x i8> %val
+}
+
+define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) {
+;CHECK:  orr {{v[0-31]+}}.8h, #0xff, lsl #8
+  %val = or <16 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
+  ret <16 x i8> %val
+}
+
+
diff --git a/test/CodeGen/AArch64/neon-compare-instructions.ll b/test/CodeGen/AArch64/neon-compare-instructions.ll
new file mode 100644
index 0000000..0848f9b
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-compare-instructions.ll
@@ -0,0 +1,1982 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+define <8 x i8> @cmeq8xi8(<8 x i8> %A, <8 x i8> %B) {
+;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+	%tmp3 = icmp eq <8 x i8> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmeq16xi8(<16 x i8> %A, <16 x i8> %B) {
+;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = icmp eq <16 x i8> %A, %B;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmeq4xi16(<4 x i16> %A, <4 x i16> %B) {
+;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+	%tmp3 = icmp eq <4 x i16> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmeq8xi16(<8 x i16> %A, <8 x i16> %B) {
+;CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+	%tmp3 = icmp eq <8 x i16> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmeq2xi32(<2 x i32> %A, <2 x i32> %B) {
+;CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+	%tmp3 = icmp eq <2 x i32> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmeq4xi32(<4 x i32> %A, <4 x i32> %B) {
+;CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+	%tmp3 = icmp eq <4 x i32> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmeq2xi64(<2 x i64> %A, <2 x i64> %B) {
+;CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+	%tmp3 = icmp eq <2 x i64> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) {
+;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+	%tmp3 = icmp ne <8 x i8> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) {
+;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = icmp ne <16 x i8> %A, %B;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) {
+;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+	%tmp3 = icmp ne <4 x i16> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) {
+;CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = icmp ne <8 x i16> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) {
+;CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+	%tmp3 = icmp ne <2 x i32> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) {
+;CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = icmp ne <4 x i32> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmne2xi64(<2 x i64> %A, <2 x i64> %B) {
+;CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = icmp ne <2 x i64> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmgt8xi8(<8 x i8> %A, <8 x i8> %B) {
+;CHECK: cmgt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+	%tmp3 = icmp sgt <8 x i8> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmgt16xi8(<16 x i8> %A, <16 x i8> %B) {
+;CHECK: cmgt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = icmp sgt <16 x i8> %A, %B;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmgt4xi16(<4 x i16> %A, <4 x i16> %B) {
+;CHECK: cmgt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+	%tmp3 = icmp sgt <4 x i16> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmgt8xi16(<8 x i16> %A, <8 x i16> %B) {
+;CHECK: cmgt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+	%tmp3 = icmp sgt <8 x i16> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmgt2xi32(<2 x i32> %A, <2 x i32> %B) {
+;CHECK: cmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+	%tmp3 = icmp sgt <2 x i32> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmgt4xi32(<4 x i32> %A, <4 x i32> %B) {
+;CHECK: cmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+	%tmp3 = icmp sgt <4 x i32> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmgt2xi64(<2 x i64> %A, <2 x i64> %B) {
+;CHECK: cmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+	%tmp3 = icmp sgt <2 x i64> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmlt8xi8(<8 x i8> %A, <8 x i8> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LT implemented as GT, so check reversed operands.
+;CHECK: cmgt {{v[0-9]+}}.8b, v1.8b, v0.8b
+	%tmp3 = icmp slt <8 x i8> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmlt16xi8(<16 x i8> %A, <16 x i8> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LT implemented as GT, so check reversed operands.
+;CHECK: cmgt {{v[0-9]+}}.16b, v1.16b, v0.16b
+	%tmp3 = icmp slt <16 x i8> %A, %B;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmlt4xi16(<4 x i16> %A, <4 x i16> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LT implemented as GT, so check reversed operands.
+;CHECK: cmgt {{v[0-9]+}}.4h, v1.4h, v0.4h
+	%tmp3 = icmp slt <4 x i16> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmlt8xi16(<8 x i16> %A, <8 x i16> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LT implemented as GT, so check reversed operands.
+;CHECK: cmgt {{v[0-9]+}}.8h, v1.8h, v0.8h
+	%tmp3 = icmp slt <8 x i16> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmlt2xi32(<2 x i32> %A, <2 x i32> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LT implemented as GT, so check reversed operands.
+;CHECK: cmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
+	%tmp3 = icmp slt <2 x i32> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmlt4xi32(<4 x i32> %A, <4 x i32> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LT implemented as GT, so check reversed operands.
+;CHECK: cmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
+	%tmp3 = icmp slt <4 x i32> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmlt2xi64(<2 x i64> %A, <2 x i64> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LT implemented as GT, so check reversed operands.
+;CHECK: cmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
+	%tmp3 = icmp slt <2 x i64> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmge8xi8(<8 x i8> %A, <8 x i8> %B) {
+;CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+	%tmp3 = icmp sge <8 x i8> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmge16xi8(<16 x i8> %A, <16 x i8> %B) {
+;CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = icmp sge <16 x i8> %A, %B;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmge4xi16(<4 x i16> %A, <4 x i16> %B) {
+;CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+	%tmp3 = icmp sge <4 x i16> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmge8xi16(<8 x i16> %A, <8 x i16> %B) {
+;CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+	%tmp3 = icmp sge <8 x i16> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmge2xi32(<2 x i32> %A, <2 x i32> %B) {
+;CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+	%tmp3 = icmp sge <2 x i32> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmge4xi32(<4 x i32> %A, <4 x i32> %B) {
+;CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+	%tmp3 = icmp sge <4 x i32> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmge2xi64(<2 x i64> %A, <2 x i64> %B) {
+;CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+	%tmp3 = icmp sge <2 x i64> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmle8xi8(<8 x i8> %A, <8 x i8> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LE implemented as GE, so check reversed operands.
+;CHECK: cmge {{v[0-9]+}}.8b, v1.8b, v0.8b
+	%tmp3 = icmp sle <8 x i8> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmle16xi8(<16 x i8> %A, <16 x i8> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LE implemented as GE, so check reversed operands.
+;CHECK: cmge {{v[0-9]+}}.16b, v1.16b, v0.16b
+	%tmp3 = icmp sle <16 x i8> %A, %B;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmle4xi16(<4 x i16> %A, <4 x i16> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LE implemented as GE, so check reversed operands.
+;CHECK: cmge {{v[0-9]+}}.4h, v1.4h, v0.4h
+	%tmp3 = icmp sle <4 x i16> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmle8xi16(<8 x i16> %A, <8 x i16> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LE implemented as GE, so check reversed operands.
+;CHECK: cmge {{v[0-9]+}}.8h, v1.8h, v0.8h
+	%tmp3 = icmp sle <8 x i16> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmle2xi32(<2 x i32> %A, <2 x i32> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LE implemented as GE, so check reversed operands.
+;CHECK: cmge {{v[0-9]+}}.2s, v1.2s, v0.2s
+	%tmp3 = icmp sle <2 x i32> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmle4xi32(<4 x i32> %A, <4 x i32> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LE implemented as GE, so check reversed operands.
+;CHECK: cmge {{v[0-9]+}}.4s, v1.4s, v0.4s
+	%tmp3 = icmp sle <4 x i32> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmle2xi64(<2 x i64> %A, <2 x i64> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LE implemented as GE, so check reversed operands.
+;CHECK: cmge {{v[0-9]+}}.2d, v1.2d, v0.2d
+	%tmp3 = icmp sle <2 x i64> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmhi8xi8(<8 x i8> %A, <8 x i8> %B) {
+;CHECK: cmhi {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+	%tmp3 = icmp ugt <8 x i8> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmhi16xi8(<16 x i8> %A, <16 x i8> %B) {
+;CHECK: cmhi {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = icmp ugt <16 x i8> %A, %B;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmhi4xi16(<4 x i16> %A, <4 x i16> %B) {
+;CHECK: cmhi {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+	%tmp3 = icmp ugt <4 x i16> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmhi8xi16(<8 x i16> %A, <8 x i16> %B) {
+;CHECK: cmhi {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+	%tmp3 = icmp ugt <8 x i16> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmhi2xi32(<2 x i32> %A, <2 x i32> %B) {
+;CHECK: cmhi {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+	%tmp3 = icmp ugt <2 x i32> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmhi4xi32(<4 x i32> %A, <4 x i32> %B) {
+;CHECK: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+	%tmp3 = icmp ugt <4 x i32> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmhi2xi64(<2 x i64> %A, <2 x i64> %B) {
+;CHECK: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+	%tmp3 = icmp ugt <2 x i64> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmlo8xi8(<8 x i8> %A, <8 x i8> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LO implemented as HI, so check reversed operands.
+;CHECK: cmhi {{v[0-9]+}}.8b, v1.8b, v0.8b
+	%tmp3 = icmp ult <8 x i8> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmlo16xi8(<16 x i8> %A, <16 x i8> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LO implemented as HI, so check reversed operands.
+;CHECK: cmhi {{v[0-9]+}}.16b, v1.16b, v0.16b
+	%tmp3 = icmp ult <16 x i8> %A, %B;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmlo4xi16(<4 x i16> %A, <4 x i16> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LO implemented as HI, so check reversed operands.
+;CHECK: cmhi {{v[0-9]+}}.4h, v1.4h, v0.4h
+	%tmp3 = icmp ult <4 x i16> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmlo8xi16(<8 x i16> %A, <8 x i16> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LO implemented as HI, so check reversed operands.
+;CHECK: cmhi {{v[0-9]+}}.8h, v1.8h, v0.8h
+	%tmp3 = icmp ult <8 x i16> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmlo2xi32(<2 x i32> %A, <2 x i32> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LO implemented as HI, so check reversed operands.
+;CHECK: cmhi {{v[0-9]+}}.2s, v1.2s, v0.2s
+	%tmp3 = icmp ult <2 x i32> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmlo4xi32(<4 x i32> %A, <4 x i32> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LO implemented as HI, so check reversed operands.
+;CHECK: cmhi {{v[0-9]+}}.4s, v1.4s, v0.4s
+	%tmp3 = icmp ult <4 x i32> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmlo2xi64(<2 x i64> %A, <2 x i64> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LO implemented as HI, so check reversed operands.
+;CHECK: cmhi {{v[0-9]+}}.2d, v1.2d, v0.2d
+	%tmp3 = icmp ult <2 x i64> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmhs8xi8(<8 x i8> %A, <8 x i8> %B) {
+;CHECK: cmhs {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+	%tmp3 = icmp uge <8 x i8> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmhs16xi8(<16 x i8> %A, <16 x i8> %B) {
+;CHECK: cmhs {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = icmp uge <16 x i8> %A, %B;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmhs4xi16(<4 x i16> %A, <4 x i16> %B) {
+;CHECK: cmhs {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+	%tmp3 = icmp uge <4 x i16> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmhs8xi16(<8 x i16> %A, <8 x i16> %B) {
+;CHECK: cmhs {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+	%tmp3 = icmp uge <8 x i16> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmhs2xi32(<2 x i32> %A, <2 x i32> %B) {
+;CHECK: cmhs {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+	%tmp3 = icmp uge <2 x i32> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmhs4xi32(<4 x i32> %A, <4 x i32> %B) {
+;CHECK: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+	%tmp3 = icmp uge <4 x i32> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmhs2xi64(<2 x i64> %A, <2 x i64> %B) {
+;CHECK: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+	%tmp3 = icmp uge <2 x i64> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmls8xi8(<8 x i8> %A, <8 x i8> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LS implemented as HS, so check reversed operands.
+;CHECK: cmhs {{v[0-9]+}}.8b, v1.8b, v0.8b
+	%tmp3 = icmp ule <8 x i8> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmls16xi8(<16 x i8> %A, <16 x i8> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LS implemented as HS, so check reversed operands.
+;CHECK: cmhs {{v[0-9]+}}.16b, v1.16b, v0.16b
+	%tmp3 = icmp ule <16 x i8> %A, %B;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmls4xi16(<4 x i16> %A, <4 x i16> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LS implemented as HS, so check reversed operands.
+;CHECK: cmhs {{v[0-9]+}}.4h, v1.4h, v0.4h
+	%tmp3 = icmp ule <4 x i16> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmls8xi16(<8 x i16> %A, <8 x i16> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LS implemented as HS, so check reversed operands.
+;CHECK: cmhs {{v[0-9]+}}.8h, v1.8h, v0.8h
+	%tmp3 = icmp ule <8 x i16> %A, %B;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmls2xi32(<2 x i32> %A, <2 x i32> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LS implemented as HS, so check reversed operands.
+;CHECK: cmhs {{v[0-9]+}}.2s, v1.2s, v0.2s
+	%tmp3 = icmp ule <2 x i32> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmls4xi32(<4 x i32> %A, <4 x i32> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LS implemented as HS, so check reversed operands.
+;CHECK: cmhs {{v[0-9]+}}.4s, v1.4s, v0.4s
+	%tmp3 = icmp ule <4 x i32> %A, %B;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmls2xi64(<2 x i64> %A, <2 x i64> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LS implemented as HS, so check reversed operands.
+;CHECK: cmhs {{v[0-9]+}}.2d, v1.2d, v0.2d
+	%tmp3 = icmp ule <2 x i64> %A, %B;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmtst8xi8(<8 x i8> %A, <8 x i8> %B) {
+;CHECK: cmtst {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+	%tmp3 = and <8 x i8> %A, %B
+	%tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
+   %tmp5 = sext <8 x i1> %tmp4 to <8 x i8>
+	ret <8 x i8> %tmp5
+}
+
+define <16 x i8> @cmtst16xi8(<16 x i8> %A, <16 x i8> %B) {
+;CHECK: cmtst {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = and <16 x i8> %A, %B
+	%tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer
+   %tmp5 = sext <16 x i1> %tmp4 to <16 x i8>
+	ret <16 x i8> %tmp5
+}
+
+define <4 x i16> @cmtst4xi16(<4 x i16> %A, <4 x i16> %B) {
+;CHECK: cmtst {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+	%tmp3 = and <4 x i16> %A, %B
+	%tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer
+   %tmp5 = sext <4 x i1> %tmp4 to <4 x i16>
+	ret <4 x i16> %tmp5
+}
+
+define <8 x i16> @cmtst8xi16(<8 x i16> %A, <8 x i16> %B) {
+;CHECK: cmtst {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+	%tmp3 = and <8 x i16> %A, %B
+	%tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer
+   %tmp5 = sext <8 x i1> %tmp4 to <8 x i16>
+	ret <8 x i16> %tmp5
+}
+
+define <2 x i32> @cmtst2xi32(<2 x i32> %A, <2 x i32> %B) {
+;CHECK: cmtst {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+	%tmp3 = and <2 x i32> %A, %B
+	%tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer
+   %tmp5 = sext <2 x i1> %tmp4 to <2 x i32>
+	ret <2 x i32> %tmp5
+}
+
+define <4 x i32> @cmtst4xi32(<4 x i32> %A, <4 x i32> %B) {
+;CHECK: cmtst {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+	%tmp3 = and <4 x i32> %A, %B
+	%tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer
+   %tmp5 = sext <4 x i1> %tmp4 to <4 x i32>
+	ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @cmtst2xi64(<2 x i64> %A, <2 x i64> %B) {
+;CHECK: cmtst {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+	%tmp3 = and <2 x i64> %A, %B
+	%tmp4 = icmp ne <2 x i64> %tmp3, zeroinitializer
+   %tmp5 = sext <2 x i1> %tmp4 to <2 x i64>
+	ret <2 x i64> %tmp5
+}
+
+
+
+define <8 x i8> @cmeqz8xi8(<8 x i8> %A) {
+;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x0
+	%tmp3 = icmp eq <8 x i8> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmeqz16xi8(<16 x i8> %A) {
+;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x0
+	%tmp3 = icmp eq <16 x i8> %A, zeroinitializer;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmeqz4xi16(<4 x i16> %A) {
+;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0x0
+	%tmp3 = icmp eq <4 x i16> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmeqz8xi16(<8 x i16> %A) {
+;CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0x0
+	%tmp3 = icmp eq <8 x i16> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmeqz2xi32(<2 x i32> %A) {
+;CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0x0
+	%tmp3 = icmp eq <2 x i32> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmeqz4xi32(<4 x i32> %A) {
+;CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0x0
+	%tmp3 = icmp eq <4 x i32> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmeqz2xi64(<2 x i64> %A) {
+;CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0x0
+	%tmp3 = icmp eq <2 x i64> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+
+define <8 x i8> @cmgez8xi8(<8 x i8> %A) {
+;CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x0
+	%tmp3 = icmp sge <8 x i8> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmgez16xi8(<16 x i8> %A) {
+;CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x0
+	%tmp3 = icmp sge <16 x i8> %A, zeroinitializer;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmgez4xi16(<4 x i16> %A) {
+;CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0x0
+	%tmp3 = icmp sge <4 x i16> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmgez8xi16(<8 x i16> %A) {
+;CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0x0
+	%tmp3 = icmp sge <8 x i16> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmgez2xi32(<2 x i32> %A) {
+;CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0x0
+	%tmp3 = icmp sge <2 x i32> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmgez4xi32(<4 x i32> %A) {
+;CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0x0
+	%tmp3 = icmp sge <4 x i32> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmgez2xi64(<2 x i64> %A) {
+;CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0x0
+	%tmp3 = icmp sge <2 x i64> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+
+define <8 x i8> @cmgtz8xi8(<8 x i8> %A) {
+;CHECK: cmgt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x0
+	%tmp3 = icmp sgt <8 x i8> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmgtz16xi8(<16 x i8> %A) {
+;CHECK: cmgt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x0
+	%tmp3 = icmp sgt <16 x i8> %A, zeroinitializer;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmgtz4xi16(<4 x i16> %A) {
+;CHECK: cmgt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0x0
+	%tmp3 = icmp sgt <4 x i16> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmgtz8xi16(<8 x i16> %A) {
+;CHECK: cmgt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0x0
+	%tmp3 = icmp sgt <8 x i16> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmgtz2xi32(<2 x i32> %A) {
+;CHECK: cmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0x0
+	%tmp3 = icmp sgt <2 x i32> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmgtz4xi32(<4 x i32> %A) {
+;CHECK: cmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0x0
+	%tmp3 = icmp sgt <4 x i32> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmgtz2xi64(<2 x i64> %A) {
+;CHECK: cmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0x0
+	%tmp3 = icmp sgt <2 x i64> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmlez8xi8(<8 x i8> %A) {
+;CHECK: cmle {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x0
+	%tmp3 = icmp sle <8 x i8> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmlez16xi8(<16 x i8> %A) {
+;CHECK: cmle {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x0
+	%tmp3 = icmp sle <16 x i8> %A, zeroinitializer;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmlez4xi16(<4 x i16> %A) {
+;CHECK: cmle {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0x0
+	%tmp3 = icmp sle <4 x i16> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmlez8xi16(<8 x i16> %A) {
+;CHECK: cmle {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0x0
+	%tmp3 = icmp sle <8 x i16> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmlez2xi32(<2 x i32> %A) {
+;CHECK: cmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0x0
+	%tmp3 = icmp sle <2 x i32> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmlez4xi32(<4 x i32> %A) {
+;CHECK: cmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0x0
+	%tmp3 = icmp sle <4 x i32> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmlez2xi64(<2 x i64> %A) {
+;CHECK: cmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0x0
+	%tmp3 = icmp sle <2 x i64> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmltz8xi8(<8 x i8> %A) {
+;CHECK: cmlt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x0
+	%tmp3 = icmp slt <8 x i8> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmltz16xi8(<16 x i8> %A) {
+;CHECK: cmlt {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x0
+	%tmp3 = icmp slt <16 x i8> %A, zeroinitializer;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmltz4xi16(<4 x i16> %A) {
+;CHECK: cmlt {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0x0
+	%tmp3 = icmp slt <4 x i16> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmltz8xi16(<8 x i16> %A) {
+;CHECK: cmlt {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0x0
+	%tmp3 = icmp slt <8 x i16> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmltz2xi32(<2 x i32> %A) {
+;CHECK: cmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0x0
+	%tmp3 = icmp slt <2 x i32> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmltz4xi32(<4 x i32> %A) {
+;CHECK: cmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0x0
+	%tmp3 = icmp slt <4 x i32> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmltz2xi64(<2 x i64> %A) {
+;CHECK: cmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0x0
+	%tmp3 = icmp slt <2 x i64> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmneqz8xi8(<8 x i8> %A) {
+;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x0
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+	%tmp3 = icmp ne <8 x i8> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmneqz16xi8(<16 x i8> %A) {
+;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x0
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = icmp ne <16 x i8> %A, zeroinitializer;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmneqz4xi16(<4 x i16> %A) {
+;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0x0
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+	%tmp3 = icmp ne <4 x i16> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmneqz8xi16(<8 x i16> %A) {
+;CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0x0
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = icmp ne <8 x i16> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmneqz2xi32(<2 x i32> %A) {
+;CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0x0
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+	%tmp3 = icmp ne <2 x i32> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmneqz4xi32(<4 x i32> %A) {
+;CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0x0
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = icmp ne <4 x i32> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmneqz2xi64(<2 x i64> %A) {
+;CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0x0
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = icmp ne <2 x i64> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmhsz8xi8(<8 x i8> %A) {
+;CHECK: movi {{v[0-9]+}}.8b, #0x0
+;CHECK-NEXT: cmhs {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+	%tmp3 = icmp uge <8 x i8> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmhsz16xi8(<16 x i8> %A) {
+;CHECK: movi {{v[0-9]+}}.16b, #0x0
+;CHECK-NEXT: cmhs {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = icmp uge <16 x i8> %A, zeroinitializer;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmhsz4xi16(<4 x i16> %A) {
+;CHECK: movi {{v[0-9]+}}.8b, #0x0
+;CHECK-NEXT: cmhs {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+	%tmp3 = icmp uge <4 x i16> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmhsz8xi16(<8 x i16> %A) {
+;CHECK: movi {{v[0-9]+}}.16b, #0x0
+;CHECK-NEXT: cmhs {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+	%tmp3 = icmp uge <8 x i16> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmhsz2xi32(<2 x i32> %A) {
+;CHECK: movi {{v[0-9]+}}.8b, #0x0
+;CHECK-NEXT: cmhs {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+	%tmp3 = icmp uge <2 x i32> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmhsz4xi32(<4 x i32> %A) {
+;CHECK: movi {{v[0-9]+}}.16b, #0x0
+;CHECK-NEXT: cmhs {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+	%tmp3 = icmp uge <4 x i32> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmhsz2xi64(<2 x i64> %A) {
+;CHECK: movi {{v[0-9]+}}.16b, #0x0
+;CHECK-NEXT: cmhs {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+	%tmp3 = icmp uge <2 x i64> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+
+define <8 x i8> @cmhiz8xi8(<8 x i8> %A) {
+;CHECK: movi {{v[0-9]+}}.8b, #0x0
+;CHECK-NEXT: cmhi {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+	%tmp3 = icmp ugt <8 x i8> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmhiz16xi8(<16 x i8> %A) {
+;CHECK: movi {{v[0-9]+}}.16b, #0x0
+;CHECK-NEXT: cmhi {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+	%tmp3 = icmp ugt <16 x i8> %A, zeroinitializer;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmhiz4xi16(<4 x i16> %A) {
+;CHECK: movi {{v[0-9]+}}.8b, #0x0
+;CHECK-NEXT: cmhi {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+	%tmp3 = icmp ugt <4 x i16> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmhiz8xi16(<8 x i16> %A) {
+;CHECK: movi {{v[0-9]+}}.16b, #0x0
+;CHECK-NEXT: cmhi {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+	%tmp3 = icmp ugt <8 x i16> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmhiz2xi32(<2 x i32> %A) {
+;CHECK: movi {{v[0-9]+}}.8b, #0x0
+;CHECK-NEXT: cmhi {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+	%tmp3 = icmp ugt <2 x i32> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmhiz4xi32(<4 x i32> %A) {
+;CHECK: movi {{v[0-9]+}}.16b, #0x0
+;CHECK-NEXT: cmhi {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+	%tmp3 = icmp ugt <4 x i32> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmhiz2xi64(<2 x i64> %A) {
+;CHECK: movi {{v[0-9]+}}.16b, #0x0
+;CHECK-NEXT: cmhi {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+	%tmp3 = icmp ugt <2 x i64> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmlsz8xi8(<8 x i8> %A) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LS implemented as HS, so check reversed operands.
+;CHECK: movi v1.8b, #0x0
+;CHECK-NEXT: cmhs {{v[0-9]+}}.8b, v1.8b, v0.8b
+	%tmp3 = icmp ule <8 x i8> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmlsz16xi8(<16 x i8> %A) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LS implemented as HS, so check reversed operands.
+;CHECK: movi v1.16b, #0x0
+;CHECK-NEXT: cmhs {{v[0-9]+}}.16b, v1.16b, v0.16b
+	%tmp3 = icmp ule <16 x i8> %A, zeroinitializer;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmlsz4xi16(<4 x i16> %A) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LS implemented as HS, so check reversed operands.
+;CHECK: movi v1.8b, #0x0
+;CHECK-NEXT: cmhs {{v[0-9]+}}.4h, v1.4h, v0.4h
+	%tmp3 = icmp ule <4 x i16> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmlsz8xi16(<8 x i16> %A) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LS implemented as HS, so check reversed operands.
+;CHECK: movi v1.16b, #0x0
+;CHECK-NEXT: cmhs {{v[0-9]+}}.8h, v1.8h, v0.8h
+	%tmp3 = icmp ule <8 x i16> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmlsz2xi32(<2 x i32> %A) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LS implemented as HS, so check reversed operands.
+;CHECK: movi v1.8b, #0x0
+;CHECK-NEXT: cmhs {{v[0-9]+}}.2s, v1.2s, v0.2s
+	%tmp3 = icmp ule <2 x i32> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmlsz4xi32(<4 x i32> %A) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LS implemented as HS, so check reversed operands.
+;CHECK: movi v1.16b, #0x0
+;CHECK-NEXT: cmhs {{v[0-9]+}}.4s, v1.4s, v0.4s
+	%tmp3 = icmp ule <4 x i32> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmlsz2xi64(<2 x i64> %A) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LS implemented as HS, so check reversed operands.
+;CHECK: movi v1.16b, #0x0
+;CHECK-NEXT: cmhs {{v[0-9]+}}.2d, v1.2d, v0.2d
+	%tmp3 = icmp ule <2 x i64> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <8 x i8> @cmloz8xi8(<8 x i8> %A) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LO implemented as HI, so check reversed operands.
+;CHECK: movi v1.8b, #0x0
+;CHECK-NEXT: cmhi {{v[0-9]+}}.8b, v1.8b, {{v[0-9]+}}.8b
+	%tmp3 = icmp ult <8 x i8> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
+	ret <8 x i8> %tmp4
+}
+
+define <16 x i8> @cmloz16xi8(<16 x i8> %A) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LO implemented as HI, so check reversed operands.
+;CHECK: movi v1.16b, #0x0
+;CHECK-NEXT: cmhi {{v[0-9]+}}.16b, v1.16b, v0.16b
+	%tmp3 = icmp ult <16 x i8> %A, zeroinitializer;
+   %tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
+	ret <16 x i8> %tmp4
+}
+
+define <4 x i16> @cmloz4xi16(<4 x i16> %A) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LO implemented as HI, so check reversed operands.
+;CHECK: movi v1.8b, #0x0
+;CHECK-NEXT: cmhi {{v[0-9]+}}.4h, v1.4h, v0.4h
+	%tmp3 = icmp ult <4 x i16> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
+	ret <4 x i16> %tmp4
+}
+
+define <8 x i16> @cmloz8xi16(<8 x i16> %A) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LO implemented as HI, so check reversed operands.
+;CHECK: movi v1.16b, #0x0
+;CHECK-NEXT: cmhi {{v[0-9]+}}.8h, v1.8h, v0.8h
+	%tmp3 = icmp ult <8 x i16> %A, zeroinitializer;
+   %tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
+	ret <8 x i16> %tmp4
+}
+
+define <2 x i32> @cmloz2xi32(<2 x i32> %A) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LO implemented as HI, so check reversed operands.
+;CHECK: movi v1.8b, #0x0
+;CHECK-NEXT: cmhi {{v[0-9]+}}.2s, v1.2s, v0.2s
+	%tmp3 = icmp ult <2 x i32> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @cmloz4xi32(<4 x i32> %A) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LO implemented as HI, so check reversed operands.
+;CHECK: movi v1.16b, #0x0
+;CHECK-NEXT: cmhi {{v[0-9]+}}.4s, v1.4s, v0.4s
+	%tmp3 = icmp ult <4 x i32> %A, zeroinitializer;
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @cmloz2xi64(<2 x i64> %A) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; LO implemented as HI, so check reversed operands.
+;CHECK: movi v1.16b, #0x0
+;CHECK-NEXT: cmhi {{v[0-9]+}}.2d, v1.2d, v0.2d
+	%tmp3 = icmp ult <2 x i64> %A, zeroinitializer;
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+
+define <2 x i32> @fcmoeq2xfloat(<2 x float> %A, <2 x float> %B) {
+;CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+   %tmp3 = fcmp oeq <2 x float> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmoeq4xfloat(<4 x float> %A, <4 x float> %B) {
+;CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+   %tmp3 = fcmp oeq <4 x float> %A, %B
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmoeq2xdouble(<2 x double> %A, <2 x double> %B) {
+;CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+   %tmp3 = fcmp oeq <2 x double> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmoge2xfloat(<2 x float> %A, <2 x float> %B) {
+;CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+   %tmp3 = fcmp oge <2 x float> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmoge4xfloat(<4 x float> %A, <4 x float> %B) {
+;CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+   %tmp3 = fcmp oge <4 x float> %A, %B
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmoge2xdouble(<2 x double> %A, <2 x double> %B) {
+;CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+   %tmp3 = fcmp oge <2 x double> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmogt2xfloat(<2 x float> %A, <2 x float> %B) {
+;CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+   %tmp3 = fcmp ogt <2 x float> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmogt4xfloat(<4 x float> %A, <4 x float> %B) {
+;CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+   %tmp3 = fcmp ogt <4 x float> %A, %B
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmogt2xdouble(<2 x double> %A, <2 x double> %B) {
+;CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+   %tmp3 = fcmp ogt <2 x double> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmole2xfloat(<2 x float> %A, <2 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; OLE implemented as OGE, so check reversed operands.
+;CHECK: fcmge {{v[0-9]+}}.2s, v1.2s, v0.2s
+   %tmp3 = fcmp ole <2 x float> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmole4xfloat(<4 x float> %A, <4 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; OLE implemented as OGE, so check reversed operands.
+;CHECK: fcmge {{v[0-9]+}}.4s, v1.4s, v0.4s
+   %tmp3 = fcmp ole <4 x float> %A, %B
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmole2xdouble(<2 x double> %A, <2 x double> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; OLE implemented as OGE, so check reversed operands.
+;CHECK: fcmge {{v[0-9]+}}.2d, v1.2d, v0.2d
+   %tmp3 = fcmp ole <2 x double> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmolt2xfloat(<2 x float> %A, <2 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; OLE implemented as OGE, so check reversed operands.
+;CHECK: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
+   %tmp3 = fcmp olt <2 x float> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmolt4xfloat(<4 x float> %A, <4 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; OLE implemented as OGE, so check reversed operands.
+;CHECK: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
+   %tmp3 = fcmp olt <4 x float> %A, %B
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmolt2xdouble(<2 x double> %A, <2 x double> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; OLE implemented as OGE, so check reversed operands.
+;CHECK: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
+   %tmp3 = fcmp olt <2 x double> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmone2xfloat(<2 x float> %A, <2 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
+;CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s
+;CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
+;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp one <2 x float> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmone4xfloat(<4 x float> %A, <4 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
+;CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s
+;CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp one <4 x float> %A, %B
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmone2xdouble(<2 x double> %A, <2 x double> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; ONE = OGT | OLT, OLT implemented as OGT so check reversed operands
+;CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d
+;CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; todo check reversed operands
+   %tmp3 = fcmp one <2 x double> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+
+define <2 x i32> @fcmord2xfloat(<2 x float> %A, <2 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
+;CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s
+;CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
+;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp ord <2 x float> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+
+define <4 x i32> @fcmord4xfloat(<4 x float> %A, <4 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
+;CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s
+;CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ord <4 x float> %A, %B
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @fcmord2xdouble(<2 x double> %A, <2 x double> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; ORD = OGE | OLT, OLT implemented as OGT, so check reversed operands.
+;CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d
+;CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ord <2 x double> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+
+define <2 x i32> @fcmuno2xfloat(<2 x float> %A, <2 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
+;CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s
+;CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
+;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp uno <2 x float> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmuno4xfloat(<4 x float> %A, <4 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
+;CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s
+;CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp uno <4 x float> %A, %B
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @fcmuno2xdouble(<2 x double> %A, <2 x double> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; UNO = !(OGE | OLT), OLT implemented as OGT, so check reversed operands.
+;CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d
+;CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp uno <2 x double> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmueq2xfloat(<2 x float> %A, <2 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
+;CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s
+;CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
+;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp ueq <2 x float> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmueq4xfloat(<4 x float> %A, <4 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
+;CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s
+;CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ueq <4 x float> %A, %B
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @fcmueq2xdouble(<2 x double> %A, <2 x double> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; UEQ = !ONE = !(OGT | OLT), OLT implemented as OGT so check reversed operands
+;CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d
+;CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ueq <2 x double> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmuge2xfloat(<2 x float> %A, <2 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; UGE = ULE with swapped operands, ULE implemented as !OGT.
+;CHECK: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp uge <2 x float> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmuge4xfloat(<4 x float> %A, <4 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; UGE = ULE with swapped operands, ULE implemented as !OGT.
+;CHECK: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp uge <4 x float> %A, %B
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @fcmuge2xdouble(<2 x double> %A, <2 x double> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; UGE = ULE with swapped operands, ULE implemented as !OGT.
+;CHECK: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp uge <2 x double> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmugt2xfloat(<2 x float> %A, <2 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; UGT = ULT with swapped operands, ULT implemented as !OGE.
+;CHECK: fcmge {{v[0-9]+}}.2s, v1.2s, v0.2s
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp ugt <2 x float> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmugt4xfloat(<4 x float> %A, <4 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; UGT = ULT with swapped operands, ULT implemented as !OGE.
+;CHECK: fcmge {{v[0-9]+}}.4s, v1.4s, v0.4s
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ugt <4 x float> %A, %B
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmugt2xdouble(<2 x double> %A, <2 x double> %B) {
+;CHECK: fcmge {{v[0-9]+}}.2d, v1.2d, v0.2d
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ugt <2 x double> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmule2xfloat(<2 x float> %A, <2 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; ULE implemented as !OGT.
+;CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp ule <2 x float> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmule4xfloat(<4 x float> %A, <4 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; ULE implemented as !OGT.
+;CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ule <4 x float> %A, %B
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmule2xdouble(<2 x double> %A, <2 x double> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; ULE implemented as !OGT.
+;CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ule <2 x double> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmult2xfloat(<2 x float> %A, <2 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; ULT implemented as !OGE.
+;CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp ult <2 x float> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmult4xfloat(<4 x float> %A, <4 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; ULT implemented as !OGE.
+;CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ult <4 x float> %A, %B
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmult2xdouble(<2 x double> %A, <2 x double> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; ULT implemented as !OGE.
+;CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ult <2 x double> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmune2xfloat(<2 x float> %A, <2 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; UNE = !OEQ.
+;CHECK: fcmeq {{v[0-9]+}}.2s, v0.2s, v1.2s
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp une <2 x float> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmune4xfloat(<4 x float> %A, <4 x float> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; UNE = !OEQ.
+;CHECK: fcmeq {{v[0-9]+}}.4s, v0.4s, v1.4s
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp une <4 x float> %A, %B
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x double> %B) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; UNE = !OEQ.
+;CHECK: fcmeq {{v[0-9]+}}.2d, v0.2d, v1.2d
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp une <2 x double> %A, %B
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmoeqz2xfloat(<2 x float> %A) {
+;CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+   %tmp3 = fcmp oeq <2 x float> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmoeqz4xfloat(<4 x float> %A) {
+;CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+   %tmp3 = fcmp oeq <4 x float> %A, zeroinitializer
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmoeqz2xdouble(<2 x double> %A) {
+;CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+   %tmp3 = fcmp oeq <2 x double> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+
+define <2 x i32> @fcmogez2xfloat(<2 x float> %A) {
+;CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+   %tmp3 = fcmp oge <2 x float> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmogez4xfloat(<4 x float> %A) {
+;CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+   %tmp3 = fcmp oge <4 x float> %A, zeroinitializer
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmogez2xdouble(<2 x double> %A) {
+;CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+   %tmp3 = fcmp oge <2 x double> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmogtz2xfloat(<2 x float> %A) {
+;CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+   %tmp3 = fcmp ogt <2 x float> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmogtz4xfloat(<4 x float> %A) {
+;CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+   %tmp3 = fcmp ogt <4 x float> %A, zeroinitializer
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmogtz2xdouble(<2 x double> %A) {
+;CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+   %tmp3 = fcmp ogt <2 x double> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmoltz2xfloat(<2 x float> %A) {
+;CHECK: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+   %tmp3 = fcmp olt <2 x float> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmoltz4xfloat(<4 x float> %A) {
+;CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+   %tmp3 = fcmp olt <4 x float> %A, zeroinitializer
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @fcmoltz2xdouble(<2 x double> %A) {
+;CHECK: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+   %tmp3 = fcmp olt <2 x double> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmolez2xfloat(<2 x float> %A) {
+;CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+   %tmp3 = fcmp ole <2 x float> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmolez4xfloat(<4 x float> %A) {
+;CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+   %tmp3 = fcmp ole <4 x float> %A, zeroinitializer
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @fcmolez2xdouble(<2 x double> %A) {
+;CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+   %tmp3 = fcmp ole <2 x double> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmonez2xfloat(<2 x float> %A) {
+; ONE with zero = OLT | OGT
+;CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+;CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp one <2 x float> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmonez4xfloat(<4 x float> %A) {
+; ONE with zero = OLT | OGT
+;CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+;CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp one <4 x float> %A, zeroinitializer
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmonez2xdouble(<2 x double> %A) {
+; ONE with zero = OLT | OGT
+;CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+;CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp one <2 x double> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmordz2xfloat(<2 x float> %A) {
+; ORD with zero = OLT | OGE
+;CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+;CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp ord <2 x float> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmordz4xfloat(<4 x float> %A) {
+; ORD with zero = OLT | OGE
+;CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+;CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ord <4 x float> %A, zeroinitializer
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmordz2xdouble(<2 x double> %A) {
+; ORD with zero = OLT | OGE
+;CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+;CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ord <2 x double> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmueqz2xfloat(<2 x float> %A) {
+; UEQ with zero = !ONE = !(OLT |OGT)
+;CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+;CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp ueq <2 x float> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmueqz4xfloat(<4 x float> %A) {
+; UEQ with zero = !ONE = !(OLT |OGT)
+;CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+;CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ueq <4 x float> %A, zeroinitializer
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @fcmueqz2xdouble(<2 x double> %A) {
+; UEQ with zero = !ONE = !(OLT |OGT)
+;CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+;CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ueq <2 x double> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmugez2xfloat(<2 x float> %A) {
+; UGE with zero = !OLT
+;CHECK: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp uge <2 x float> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmugez4xfloat(<4 x float> %A) {
+; UGE with zero = !OLT
+;CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp uge <4 x float> %A, zeroinitializer
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmugez2xdouble(<2 x double> %A) {
+; UGE with zero = !OLT
+;CHECK: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp uge <2 x double> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmugtz2xfloat(<2 x float> %A) {
+; UGT with zero = !OLE
+;CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp ugt <2 x float> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmugtz4xfloat(<4 x float> %A) {
+; UGT with zero = !OLE
+;CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ugt <4 x float> %A, zeroinitializer
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmugtz2xdouble(<2 x double> %A) {
+; UGT with zero = !OLE
+;CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ugt <2 x double> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmultz2xfloat(<2 x float> %A) {
+; ULT with zero = !OGE
+;CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp ult <2 x float> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmultz4xfloat(<4 x float> %A) {
+;CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ult <4 x float> %A, zeroinitializer
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @fcmultz2xdouble(<2 x double> %A) {
+;CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ult <2 x double> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+
+define <2 x i32> @fcmulez2xfloat(<2 x float> %A) {
+; ULE with zero = !OGT
+;CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp ule <2 x float> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmulez4xfloat(<4 x float> %A) {
+; ULE with zero = !OGT
+;CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ule <4 x float> %A, zeroinitializer
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @fcmulez2xdouble(<2 x double> %A) {
+; ULE with zero = !OGT
+;CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp ule <2 x double> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+define <2 x i32> @fcmunez2xfloat(<2 x float> %A) {
+; UNE with zero = !OEQ with zero
+;CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp une <2 x float> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmunez4xfloat(<4 x float> %A) {
+; UNE with zero = !OEQ with zero
+;CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp une <4 x float> %A, zeroinitializer
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+define <2 x i64> @fcmunez2xdouble(<2 x double> %A) {
+; UNE with zero = !OEQ with zero
+;CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp une <2 x double> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+}
+
+
+define <2 x i32> @fcmunoz2xfloat(<2 x float> %A) {
+; UNO with zero = !ORD = !(OLT | OGE)
+;CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+;CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0
+;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+   %tmp3 = fcmp uno <2 x float> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
+	ret <2 x i32> %tmp4
+}
+
+define <4 x i32> @fcmunoz4xfloat(<4 x float> %A) {
+; UNO with zero = !ORD = !(OLT | OGE)
+;CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+;CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp uno <4 x float> %A, zeroinitializer
+   %tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
+	ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @fcmunoz2xdouble(<2 x double> %A) {
+; UNO with zero = !ORD = !(OLT | OGE)
+;CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+;CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0
+;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff
+;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+   %tmp3 = fcmp uno <2 x double> %A, zeroinitializer
+   %tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
+	ret <2 x i64> %tmp4
+
+}
diff --git a/test/CodeGen/AArch64/neon-facge-facgt.ll b/test/CodeGen/AArch64/neon-facge-facgt.ll
new file mode 100644
index 0000000..146256e
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-facge-facgt.ll
@@ -0,0 +1,56 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+declare <2 x i32> @llvm.arm.neon.vacged(<2 x float>, <2 x float>)
+declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>)
+declare <2 x i64> @llvm.aarch64.neon.vacgeq(<2 x double>, <2 x double>)
+
+define <2 x i32> @facge_from_intr_v2i32(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
+; Using registers other than v0, v1 and v2 are possible, but would be odd.
+; CHECK: facge_from_intr_v2i32:
+  %val = call <2 x i32> @llvm.arm.neon.vacged(<2 x float> %A, <2 x float> %B)
+; CHECK: facge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+  ret <2 x i32> %val
+}
+define <4 x i32> @facge_from_intr_v4i32( <4 x float> %A, <4 x float> %B) {
+; Using registers other than v0, v1 and v2 are possible, but would be odd.
+; CHECK: facge_from_intr_v4i32:
+  %val = call <4 x i32> @llvm.arm.neon.vacgeq(<4 x float> %A, <4 x float> %B)
+; CHECK: facge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+  ret <4 x i32> %val
+}
+
+define <2 x i64> @facge_from_intr_v2i64(<2 x double> %A, <2 x double> %B) {
+; Using registers other than v0, v1 and v2 are possible, but would be odd.
+; CHECK: facge_from_intr_v2i64:
+  %val = call <2 x i64> @llvm.aarch64.neon.vacgeq(<2 x double> %A, <2 x double> %B)
+; CHECK: facge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+  ret <2 x i64> %val
+}
+
+declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>)
+declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>)
+declare <2 x i64> @llvm.aarch64.neon.vacgtq(<2 x double>, <2 x double>)
+
+define <2 x i32> @facgt_from_intr_v2i32(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
+; Using registers other than v0, v1 and v2 are possible, but would be odd.
+; CHECK: facgt_from_intr_v2i32:
+  %val = call <2 x i32> @llvm.arm.neon.vacgtd(<2 x float> %A, <2 x float> %B)
+; CHECK: facgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+  ret <2 x i32> %val
+}
+define <4 x i32> @facgt_from_intr_v4i32( <4 x float> %A, <4 x float> %B) {
+; Using registers other than v0, v1 and v2 are possible, but would be odd.
+; CHECK: facgt_from_intr_v4i32:
+  %val = call <4 x i32> @llvm.arm.neon.vacgtq(<4 x float> %A, <4 x float> %B)
+; CHECK: facgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+  ret <4 x i32> %val
+}
+
+define <2 x i64> @facgt_from_intr_v2i64(<2 x double> %A, <2 x double> %B) {
+; Using registers other than v0, v1 and v2 are possible, but would be odd.
+; CHECK: facgt_from_intr_v2i64:
+  %val = call <2 x i64> @llvm.aarch64.neon.vacgtq(<2 x double> %A, <2 x double> %B)
+; CHECK: facgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+  ret <2 x i64> %val
+}
+
diff --git a/test/CodeGen/AArch64/neon-fma.ll b/test/CodeGen/AArch64/neon-fma.ll
new file mode 100644
index 0000000..dcf4e28
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-fma.ll
@@ -0,0 +1,112 @@
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
+
+define <2 x float> @fmla2xfloat(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
+;CHECK: fmla {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
+	%tmp1 = fmul <2 x float> %A, %B;
+	%tmp2 = fadd <2 x float> %C, %tmp1;
+	ret <2 x float> %tmp2
+}
+
+define <4 x float> @fmla4xfloat(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
+;CHECK: fmla {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
+	%tmp1 = fmul <4 x float> %A, %B;
+	%tmp2 = fadd <4 x float> %C, %tmp1;
+	ret <4 x float> %tmp2
+}
+
+define <2 x double> @fmla2xdouble(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
+;CHECK: fmla {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
+	%tmp1 = fmul <2 x double> %A, %B;
+	%tmp2 = fadd <2 x double> %C, %tmp1;
+	ret <2 x double> %tmp2
+}
+
+
+define <2 x float> @fmls2xfloat(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
+;CHECK: fmls {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
+	%tmp1 = fmul <2 x float> %A, %B;
+	%tmp2 = fsub <2 x float> %C, %tmp1;
+	ret <2 x float> %tmp2
+}
+
+define <4 x float> @fmls4xfloat(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
+;CHECK: fmls {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
+	%tmp1 = fmul <4 x float> %A, %B;
+	%tmp2 = fsub <4 x float> %C, %tmp1;
+	ret <4 x float> %tmp2
+}
+
+define <2 x double> @fmls2xdouble(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
+;CHECK: fmls {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
+	%tmp1 = fmul <2 x double> %A, %B;
+	%tmp2 = fsub <2 x double> %C, %tmp1;
+	ret <2 x double> %tmp2
+}
+
+
+; Another set of tests for when the intrinsic is used.
+
+declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>)
+declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)
+declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)
+
+define <2 x float> @fmla2xfloat_fused(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
+;CHECK: fmla {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
+        %val = call <2 x float> @llvm.fma.v2f32(<2 x float> %A, <2 x float> %B, <2 x float> %C)
+	ret <2 x float> %val
+}
+
+define <4 x float> @fmla4xfloat_fused(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
+;CHECK: fmla {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
+        %val = call <4 x float> @llvm.fma.v4f32(<4 x float> %A, <4 x float> %B, <4 x float> %C)
+	ret <4 x float> %val
+}
+
+define <2 x double> @fmla2xdouble_fused(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
+;CHECK: fmla {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
+        %val = call <2 x double> @llvm.fma.v2f64(<2 x double> %A, <2 x double> %B, <2 x double> %C)
+	ret <2 x double> %val
+}
+
+define <2 x float> @fmls2xfloat_fused(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
+;CHECK: fmls {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
+        %negA = fsub <2 x float> <float -0.0, float -0.0>, %A
+        %val = call <2 x float> @llvm.fma.v2f32(<2 x float> %negA, <2 x float> %B, <2 x float> %C)
+	ret <2 x float> %val
+}
+
+define <4 x float> @fmls4xfloat_fused(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
+;CHECK: fmls {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
+        %negA = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %A
+        %val = call <4 x float> @llvm.fma.v4f32(<4 x float> %negA, <4 x float> %B, <4 x float> %C)
+	ret <4 x float> %val
+}
+
+define <2 x double> @fmls2xdouble_fused(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
+;CHECK: fmls {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
+        %negA = fsub <2 x double> <double -0.0, double -0.0>, %A
+        %val = call <2 x double> @llvm.fma.v2f64(<2 x double> %negA, <2 x double> %B, <2 x double> %C)
+	ret <2 x double> %val
+}
+
+declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>)
+declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>)
+declare <2 x double> @llvm.fmuladd.v2f64(<2 x double>, <2 x double>, <2 x double>)
+
+define <2 x float> @fmuladd2xfloat(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
+;CHECK: fmla {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
+        %val = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %A, <2 x float> %B, <2 x float> %C)
+	ret <2 x float> %val
+}
+
+define <4 x float> @fmuladd4xfloat_fused(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
+;CHECK: fmla {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
+        %val = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %A, <4 x float> %B, <4 x float> %C)
+	ret <4 x float> %val
+}
+
+define <2 x double> @fmuladd2xdouble_fused(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
+;CHECK: fmla {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
+        %val = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %A, <2 x double> %B, <2 x double> %C)
+	ret <2 x double> %val
+}
diff --git a/test/CodeGen/AArch64/neon-frsqrt-frecp.ll b/test/CodeGen/AArch64/neon-frsqrt-frecp.ll
new file mode 100644
index 0000000..46fe25d
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-frsqrt-frecp.ll
@@ -0,0 +1,54 @@
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon  | FileCheck %s
+
+; Set of tests for when the intrinsic is used.
+
+declare <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.arm.neon.vrsqrts.v2f64(<2 x double>, <2 x double>)
+
+define <2 x float> @frsqrts_from_intr_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; CHECK: frsqrts v0.2s, v0.2s, v1.2s
+        %val = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %lhs, <2 x float> %rhs)
+        ret <2 x float> %val
+}
+
+define <4 x float> @frsqrts_from_intr_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; CHECK: frsqrts v0.4s, v0.4s, v1.4s
+        %val = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %lhs, <4 x float> %rhs)
+        ret <4 x float> %val
+}
+
+define <2 x double> @frsqrts_from_intr_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; CHECK: frsqrts v0.2d, v0.2d, v1.2d
+        %val = call <2 x double> @llvm.arm.neon.vrsqrts.v2f64(<2 x double> %lhs, <2 x double> %rhs)
+        ret <2 x double> %val
+}
+
+declare <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.arm.neon.vrecps.v2f64(<2 x double>, <2 x double>)
+
+define <2 x float> @frecps_from_intr_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; CHECK: frecps v0.2s, v0.2s, v1.2s
+        %val = call <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float> %lhs, <2 x float> %rhs)
+        ret <2 x float> %val
+}
+
+define <4 x float> @frecps_from_intr_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; CHECK: frecps v0.4s, v0.4s, v1.4s
+        %val = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %lhs, <4 x float> %rhs)
+        ret <4 x float> %val
+}
+
+define <2 x double> @frecps_from_intr_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; CHECK: frecps v0.2d, v0.2d, v1.2d
+        %val = call <2 x double> @llvm.arm.neon.vrecps.v2f64(<2 x double> %lhs, <2 x double> %rhs)
+        ret <2 x double> %val
+}
+
diff --git a/test/CodeGen/AArch64/neon-halving-add-sub.ll b/test/CodeGen/AArch64/neon-halving-add-sub.ll
new file mode 100644
index 0000000..a8f59db
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-halving-add-sub.ll
@@ -0,0 +1,207 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+declare <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8>, <8 x i8>)
+declare <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @test_uhadd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_uhadd_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: uhadd v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+define <8 x i8> @test_shadd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_shadd_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vhadds.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: shadd v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+declare <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_uhadd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_uhadd_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vhaddu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: uhadd v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+define <16 x i8> @test_shadd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_shadd_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vhadds.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: shadd v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+declare <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16>, <4 x i16>)
+declare <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @test_uhadd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_uhadd_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vhaddu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: uhadd v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @test_shadd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_shadd_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vhadds.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: shadd v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+declare <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test_uhadd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_uhadd_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: uhadd v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @test_shadd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_shadd_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vhadds.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: shadd v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+declare <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @test_uhadd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_uhadd_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vhaddu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: uhadd v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @test_shadd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_shadd_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vhadds.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: shadd v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+declare <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @test_uhadd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_uhadd_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: uhadd v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @test_shadd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_shadd_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vhadds.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: shadd v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+
+declare <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8>, <8 x i8>)
+declare <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @test_uhsub_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_uhsub_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: uhsub v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+define <8 x i8> @test_shsub_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_shsub_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: shsub v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+declare <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_uhsub_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_uhsub_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: uhsub v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+define <16 x i8> @test_shsub_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_shsub_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: shsub v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+declare <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16>, <4 x i16>)
+declare <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @test_uhsub_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_uhsub_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: uhsub v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @test_shsub_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_shsub_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: shsub v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+declare <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test_uhsub_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_uhsub_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: uhsub v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @test_shsub_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_shsub_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: shsub v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+declare <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @test_uhsub_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_uhsub_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: uhsub v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @test_shsub_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_shsub_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: shsub v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+declare <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @test_uhsub_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_uhsub_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: uhsub v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @test_shsub_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_shsub_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: shsub v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
diff --git a/test/CodeGen/AArch64/neon-max-min-pairwise.ll b/test/CodeGen/AArch64/neon-max-min-pairwise.ll
new file mode 100644
index 0000000..d757aca
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-max-min-pairwise.ll
@@ -0,0 +1,310 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+declare <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8>, <8 x i8>)
+declare <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @test_smaxp_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; CHECK: test_smaxp_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: smaxp v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+define <8 x i8> @test_umaxp_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: umaxp v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+declare <16 x i8> @llvm.arm.neon.vpmaxs.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.arm.neon.vpmaxu.v16i8(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_smaxp_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_smaxp_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vpmaxs.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: smaxp v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+define <16 x i8> @test_umaxp_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_umaxp_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vpmaxu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: umaxp v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+declare <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16>, <4 x i16>)
+declare <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @test_smaxp_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_smaxp_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: smaxp v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @test_umaxp_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_umaxp_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: umaxp v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+
+declare <8 x i16> @llvm.arm.neon.vpmaxs.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.arm.neon.vpmaxu.v8i16(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test_smaxp_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_smaxp_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vpmaxs.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: smaxp v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @test_umaxp_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_umaxp_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vpmaxu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: umaxp v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+
+declare <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @test_smaxp_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_smaxp_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: smaxp v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @test_umaxp_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_umaxp_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: umaxp v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+declare <4 x i32> @llvm.arm.neon.vpmaxs.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.arm.neon.vpmaxu.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @test_smaxp_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_smaxp_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vpmaxs.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: smaxp v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @test_umaxp_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_umaxp_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vpmaxu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: umaxp v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+declare <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8>, <8 x i8>)
+declare <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @test_sminp_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; CHECK: test_sminp_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: sminp v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+define <8 x i8> @test_uminp_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: uminp v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+declare <16 x i8> @llvm.arm.neon.vpmins.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.arm.neon.vpminu.v16i8(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_sminp_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_sminp_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vpmins.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: sminp v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+define <16 x i8> @test_uminp_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_uminp_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vpminu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: uminp v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+declare <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16>, <4 x i16>)
+declare <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @test_sminp_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_sminp_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: sminp v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @test_uminp_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_uminp_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: uminp v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+
+declare <8 x i16> @llvm.arm.neon.vpmins.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.arm.neon.vpminu.v8i16(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test_sminp_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_sminp_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vpmins.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: sminp v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @test_uminp_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_uminp_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vpminu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: uminp v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+
+declare <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @test_sminp_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_sminp_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: sminp v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @test_uminp_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_uminp_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: uminp v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+declare <4 x i32> @llvm.arm.neon.vpmins.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.arm.neon.vpminu.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @test_sminp_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_sminp_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vpmins.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: sminp v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @test_uminp_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_uminp_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vpminu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: uminp v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+declare <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.arm.neon.vpmaxs.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.arm.neon.vpmaxs.v2f64(<2 x double>, <2 x double>)
+
+define <2 x float> @test_fmaxp_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
+; CHECK: test_fmaxp_v2f32:
+        %val = call <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float> %lhs, <2 x float> %rhs)
+; CHECK: fmaxp v0.2s, v0.2s, v1.2s
+        ret <2 x float> %val
+}
+
+define <4 x float> @test_fmaxp_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
+; CHECK: test_fmaxp_v4f32:
+        %val = call <4 x float> @llvm.arm.neon.vpmaxs.v4f32(<4 x float> %lhs, <4 x float> %rhs)
+; CHECK: fmaxp v0.4s, v0.4s, v1.4s
+        ret <4 x float> %val
+}
+
+define <2 x double> @test_fmaxp_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
+; CHECK: test_fmaxp_v2f64:
+        %val = call <2 x double> @llvm.arm.neon.vpmaxs.v2f64(<2 x double> %lhs, <2 x double> %rhs)
+; CHECK: fmaxp v0.2d, v0.2d, v1.2d
+        ret <2 x double> %val
+}
+
+declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.arm.neon.vpmins.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.arm.neon.vpmins.v2f64(<2 x double>, <2 x double>)
+
+define <2 x float> @test_fminp_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
+; CHECK: test_fminp_v2f32:
+        %val = call <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float> %lhs, <2 x float> %rhs)
+; CHECK: fminp v0.2s, v0.2s, v1.2s
+        ret <2 x float> %val
+}
+
+define <4 x float> @test_fminp_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
+; CHECK: test_fminp_v4f32:
+        %val = call <4 x float> @llvm.arm.neon.vpmins.v4f32(<4 x float> %lhs, <4 x float> %rhs)
+; CHECK: fminp v0.4s, v0.4s, v1.4s
+        ret <4 x float> %val
+}
+
+define <2 x double> @test_fminp_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
+; CHECK: test_fminp_v2f64:
+        %val = call <2 x double> @llvm.arm.neon.vpmins.v2f64(<2 x double> %lhs, <2 x double> %rhs)
+; CHECK: fminp v0.2d, v0.2d, v1.2d
+        ret <2 x double> %val
+}
+
+declare <2 x float> @llvm.aarch64.neon.vpmaxnm.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.aarch64.neon.vpmaxnm.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.aarch64.neon.vpmaxnm.v2f64(<2 x double>, <2 x double>)
+
+define <2 x float> @test_fmaxnmp_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
+; CHECK: test_fmaxnmp_v2f32:
+        %val = call <2 x float> @llvm.aarch64.neon.vpmaxnm.v2f32(<2 x float> %lhs, <2 x float> %rhs)
+; CHECK: fmaxnmp v0.2s, v0.2s, v1.2s
+        ret <2 x float> %val
+}
+
+define <4 x float> @test_fmaxnmp_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
+; CHECK: test_fmaxnmp_v4f32:
+        %val = call <4 x float> @llvm.aarch64.neon.vpmaxnm.v4f32(<4 x float> %lhs, <4 x float> %rhs)
+; CHECK: fmaxnmp v0.4s, v0.4s, v1.4s
+        ret <4 x float> %val
+}
+
+define <2 x double> @test_fmaxnmp_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
+; CHECK: test_fmaxnmp_v2f64:
+        %val = call <2 x double> @llvm.aarch64.neon.vpmaxnm.v2f64(<2 x double> %lhs, <2 x double> %rhs)
+; CHECK: fmaxnmp v0.2d, v0.2d, v1.2d
+        ret <2 x double> %val
+}
+
+declare <2 x float> @llvm.aarch64.neon.vpminnm.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.aarch64.neon.vpminnm.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.aarch64.neon.vpminnm.v2f64(<2 x double>, <2 x double>)
+
+define <2 x float> @test_fminnmp_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
+; CHECK: test_fminnmp_v2f32:
+        %val = call <2 x float> @llvm.aarch64.neon.vpminnm.v2f32(<2 x float> %lhs, <2 x float> %rhs)
+; CHECK: fminnmp v0.2s, v0.2s, v1.2s
+        ret <2 x float> %val
+}
+
+define <4 x float> @test_fminnmp_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
+; CHECK: test_fminnmp_v4f32:
+        %val = call <4 x float> @llvm.aarch64.neon.vpminnm.v4f32(<4 x float> %lhs, <4 x float> %rhs)
+; CHECK: fminnmp v0.4s, v0.4s, v1.4s
+        ret <4 x float> %val
+}
+
+define <2 x double> @test_fminnmp_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
+; CHECK: test_fminnmp_v2f64:
+        %val = call <2 x double> @llvm.aarch64.neon.vpminnm.v2f64(<2 x double> %lhs, <2 x double> %rhs)
+; CHECK: fminnmp v0.2d, v0.2d, v1.2d
+        ret <2 x double> %val
+}
+
diff --git a/test/CodeGen/AArch64/neon-max-min.ll b/test/CodeGen/AArch64/neon-max-min.ll
new file mode 100644
index 0000000..7889c77
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-max-min.ll
@@ -0,0 +1,310 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+declare <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8>, <8 x i8>)
+declare <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @test_smax_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; CHECK: test_smax_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vmaxs.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: smax v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+define <8 x i8> @test_umax_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vmaxu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: umax v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+declare <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_smax_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_smax_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vmaxs.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: smax v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+define <16 x i8> @test_umax_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_umax_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vmaxu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: umax v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+declare <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16>, <4 x i16>)
+declare <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @test_smax_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_smax_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: smax v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @test_umax_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_umax_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: umax v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+
+declare <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test_smax_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_smax_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vmaxs.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: smax v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @test_umax_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_umax_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: umax v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+
+declare <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @test_smax_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_smax_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: smax v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @test_umax_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_umax_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: umax v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+declare <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @test_smax_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_smax_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: smax v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @test_umax_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_umax_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: umax v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+declare <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8>, <8 x i8>)
+declare <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @test_smin_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; Using registers other than v0, v1 are possible, but would be odd.
+; CHECK: test_smin_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vmins.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: smin v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+define <8 x i8> @test_umin_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vminu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: umin v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+declare <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_smin_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_smin_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vmins.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: smin v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+define <16 x i8> @test_umin_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_umin_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vminu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: umin v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+declare <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16>, <4 x i16>)
+declare <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @test_smin_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_smin_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: smin v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @test_umin_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_umin_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: umin v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+
+declare <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test_smin_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_smin_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vmins.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: smin v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @test_umin_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_umin_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vminu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: umin v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+
+declare <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @test_smin_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_smin_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: smin v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @test_umin_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_umin_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: umin v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+declare <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @test_smin_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_smin_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: smin v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @test_umin_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_umin_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: umin v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+declare <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.arm.neon.vmaxs.v2f64(<2 x double>, <2 x double>)
+
+define <2 x float> @test_fmax_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
+; CHECK: test_fmax_v2f32:
+        %val = call <2 x float> @llvm.arm.neon.vmaxs.v2f32(<2 x float> %lhs, <2 x float> %rhs)
+; CHECK: fmax v0.2s, v0.2s, v1.2s
+        ret <2 x float> %val
+}
+
+define <4 x float> @test_fmax_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
+; CHECK: test_fmax_v4f32:
+        %val = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> %lhs, <4 x float> %rhs)
+; CHECK: fmax v0.4s, v0.4s, v1.4s
+        ret <4 x float> %val
+}
+
+define <2 x double> @test_fmax_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
+; CHECK: test_fmax_v2f64:
+        %val = call <2 x double> @llvm.arm.neon.vmaxs.v2f64(<2 x double> %lhs, <2 x double> %rhs)
+; CHECK: fmax v0.2d, v0.2d, v1.2d
+        ret <2 x double> %val
+}
+
+declare <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.arm.neon.vmins.v2f64(<2 x double>, <2 x double>)
+
+define <2 x float> @test_fmin_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
+; CHECK: test_fmin_v2f32:
+        %val = call <2 x float> @llvm.arm.neon.vmins.v2f32(<2 x float> %lhs, <2 x float> %rhs)
+; CHECK: fmin v0.2s, v0.2s, v1.2s
+        ret <2 x float> %val
+}
+
+define <4 x float> @test_fmin_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
+; CHECK: test_fmin_v4f32:
+        %val = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %lhs, <4 x float> %rhs)
+; CHECK: fmin v0.4s, v0.4s, v1.4s
+        ret <4 x float> %val
+}
+
+define <2 x double> @test_fmin_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
+; CHECK: test_fmin_v2f64:
+        %val = call <2 x double> @llvm.arm.neon.vmins.v2f64(<2 x double> %lhs, <2 x double> %rhs)
+; CHECK: fmin v0.2d, v0.2d, v1.2d
+        ret <2 x double> %val
+}
+
+
+declare <2 x float> @llvm.aarch64.neon.vmaxnm.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.aarch64.neon.vmaxnm.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.aarch64.neon.vmaxnm.v2f64(<2 x double>, <2 x double>)
+
+define <2 x float> @test_fmaxnm_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
+; CHECK: test_fmaxnm_v2f32:
+        %val = call <2 x float> @llvm.aarch64.neon.vmaxnm.v2f32(<2 x float> %lhs, <2 x float> %rhs)
+; CHECK: fmaxnm v0.2s, v0.2s, v1.2s
+        ret <2 x float> %val
+}
+
+define <4 x float> @test_fmaxnm_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
+; CHECK: test_fmaxnm_v4f32:
+        %val = call <4 x float> @llvm.aarch64.neon.vmaxnm.v4f32(<4 x float> %lhs, <4 x float> %rhs)
+; CHECK: fmaxnm v0.4s, v0.4s, v1.4s
+        ret <4 x float> %val
+}
+
+define <2 x double> @test_fmaxnm_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
+; CHECK: test_fmaxnm_v2f64:
+        %val = call <2 x double> @llvm.aarch64.neon.vmaxnm.v2f64(<2 x double> %lhs, <2 x double> %rhs)
+; CHECK: fmaxnm v0.2d, v0.2d, v1.2d
+        ret <2 x double> %val
+}
+
+declare <2 x float> @llvm.aarch64.neon.vminnm.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.aarch64.neon.vminnm.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.aarch64.neon.vminnm.v2f64(<2 x double>, <2 x double>)
+
+define <2 x float> @test_fminnm_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
+; CHECK: test_fminnm_v2f32:
+        %val = call <2 x float> @llvm.aarch64.neon.vminnm.v2f32(<2 x float> %lhs, <2 x float> %rhs)
+; CHECK: fminnm v0.2s, v0.2s, v1.2s
+        ret <2 x float> %val
+}
+
+define <4 x float> @test_fminnm_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
+; CHECK: test_fminnm_v4f32:
+        %val = call <4 x float> @llvm.aarch64.neon.vminnm.v4f32(<4 x float> %lhs, <4 x float> %rhs)
+; CHECK: fminnm v0.4s, v0.4s, v1.4s
+        ret <4 x float> %val
+}
+
+define <2 x double> @test_fminnm_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
+; CHECK: test_fminnm_v2f64:
+        %val = call <2 x double> @llvm.aarch64.neon.vminnm.v2f64(<2 x double> %lhs, <2 x double> %rhs)
+; CHECK: fminnm v0.2d, v0.2d, v1.2d
+        ret <2 x double> %val
+}
diff --git a/test/CodeGen/AArch64/neon-mla-mls.ll b/test/CodeGen/AArch64/neon-mla-mls.ll
new file mode 100644
index 0000000..23e9223
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-mla-mls.ll
@@ -0,0 +1,88 @@
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
+
+
+define <8 x i8> @mla8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
+;CHECK: mla {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = mul <8 x i8> %A, %B;
+	%tmp2 = add <8 x i8> %C, %tmp1;
+	ret <8 x i8> %tmp2
+}
+
+define <16 x i8> @mla16xi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {
+;CHECK: mla {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = mul <16 x i8> %A, %B;
+	%tmp2 = add <16 x i8> %C, %tmp1;
+	ret <16 x i8> %tmp2
+}
+
+define <4 x i16> @mla4xi16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) {
+;CHECK: mla {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
+	%tmp1 = mul <4 x i16> %A, %B;
+	%tmp2 = add <4 x i16> %C, %tmp1;
+	ret <4 x i16> %tmp2
+}
+
+define <8 x i16> @mla8xi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) {
+;CHECK: mla {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
+	%tmp1 = mul <8 x i16> %A, %B;
+	%tmp2 = add <8 x i16> %C, %tmp1;
+	ret <8 x i16> %tmp2
+}
+
+define <2 x i32> @mla2xi32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
+;CHECK: mla {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
+	%tmp1 = mul <2 x i32> %A, %B;
+	%tmp2 = add <2 x i32> %C, %tmp1;
+	ret <2 x i32> %tmp2
+}
+
+define <4 x i32> @mla4xi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
+;CHECK: mla {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
+	%tmp1 = mul <4 x i32> %A, %B;
+	%tmp2 = add <4 x i32> %C, %tmp1;
+	ret <4 x i32> %tmp2
+}
+
+define <8 x i8> @mls8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
+;CHECK: mls {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp1 = mul <8 x i8> %A, %B;
+	%tmp2 = sub <8 x i8> %C, %tmp1;
+	ret <8 x i8> %tmp2
+}
+
+define <16 x i8> @mls16xi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {
+;CHECK: mls {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp1 = mul <16 x i8> %A, %B;
+	%tmp2 = sub <16 x i8> %C, %tmp1;
+	ret <16 x i8> %tmp2
+}
+
+define <4 x i16> @mls4xi16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) {
+;CHECK: mls {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
+	%tmp1 = mul <4 x i16> %A, %B;
+	%tmp2 = sub <4 x i16> %C, %tmp1;
+	ret <4 x i16> %tmp2
+}
+
+define <8 x i16> @mls8xi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) {
+;CHECK: mls {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
+	%tmp1 = mul <8 x i16> %A, %B;
+	%tmp2 = sub <8 x i16> %C, %tmp1;
+	ret <8 x i16> %tmp2
+}
+
+define <2 x i32> @mls2xi32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
+;CHECK: mls {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
+	%tmp1 = mul <2 x i32> %A, %B;
+	%tmp2 = sub <2 x i32> %C, %tmp1;
+	ret <2 x i32> %tmp2
+}
+
+define <4 x i32> @mls4xi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
+;CHECK: mls {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
+	%tmp1 = mul <4 x i32> %A, %B;
+	%tmp2 = sub <4 x i32> %C, %tmp1;
+	ret <4 x i32> %tmp2
+}
+
+
diff --git a/test/CodeGen/AArch64/neon-mov.ll b/test/CodeGen/AArch64/neon-mov.ll
new file mode 100644
index 0000000..42f6a89
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-mov.ll
@@ -0,0 +1,205 @@
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
+
+define <8 x i8> @movi8b() {
+;CHECK:  movi {{v[0-31]+}}.8b, #0x8
+   ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+}
+
+define <16 x i8> @movi16b() {
+;CHECK:  movi {{v[0-31]+}}.16b, #0x8
+   ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
+}
+
+define <2 x i32> @movi2s_lsl0() {
+;CHECK:  movi {{v[0-31]+}}.2s, #0xff
+   ret <2 x i32> < i32 255, i32 255 >
+}
+
+define <2 x i32> @movi2s_lsl8() {
+;CHECK:  movi {{v[0-31]+}}.2s, #0xff, lsl #8
+   ret <2 x i32> < i32 65280, i32 65280 >
+}
+
+define <2 x i32> @movi2s_lsl16() {
+;CHECK:  movi {{v[0-31]+}}.2s, #0xff, lsl #16
+   ret <2 x i32> < i32 16711680, i32 16711680 >
+
+}
+
+define <2 x i32> @movi2s_lsl24() {
+;CHECK:  movi {{v[0-31]+}}.2s, #0xff, lsl #24
+   ret <2 x i32> < i32 4278190080, i32 4278190080 >
+}
+
+define <4 x i32> @movi4s_lsl0() {
+;CHECK:  movi {{v[0-31]+}}.4s, #0xff
+   ret <4 x i32> < i32 255, i32 255, i32 255, i32 255 >
+}
+
+define <4 x i32> @movi4s_lsl8() {
+;CHECK:  movi {{v[0-31]+}}.4s, #0xff, lsl #8
+   ret <4 x i32> < i32 65280, i32 65280, i32 65280, i32 65280 >
+}
+
+define <4 x i32> @movi4s_lsl16() {
+;CHECK:  movi {{v[0-31]+}}.4s, #0xff, lsl #16
+   ret <4 x i32> < i32 16711680, i32 16711680, i32 16711680, i32 16711680 >
+
+}
+
+define <4 x i32> @movi4s_lsl24() {
+;CHECK:  movi {{v[0-31]+}}.4s, #0xff, lsl #24
+   ret <4 x i32> < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080 >
+}
+
+define <4 x i16> @movi4h_lsl0() {
+;CHECK:  movi {{v[0-31]+}}.4h, #0xff
+   ret <4 x i16> < i16 255, i16 255, i16 255, i16 255 >
+}
+
+define <4 x i16> @movi4h_lsl8() {
+;CHECK:  movi {{v[0-31]+}}.4h, #0xff, lsl #8
+   ret <4 x i16> < i16 65280, i16 65280, i16 65280, i16 65280 >
+}
+
+define <8 x i16> @movi8h_lsl0() {
+;CHECK:  movi {{v[0-31]+}}.8h, #0xff
+   ret <8 x i16> < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
+}
+
+define <8 x i16> @movi8h_lsl8() {
+;CHECK:  movi {{v[0-31]+}}.8h, #0xff, lsl #8
+   ret <8 x i16> < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
+}
+
+
+define <2 x i32> @mvni2s_lsl0() {
+;CHECK:  mvni {{v[0-31]+}}.2s, #0x10
+   ret <2 x i32> < i32 4294967279, i32 4294967279 >
+}
+
+define <2 x i32> @mvni2s_lsl8() {
+;CHECK:  mvni {{v[0-31]+}}.2s, #0x10, lsl #8
+   ret <2 x i32> < i32 4294963199, i32 4294963199 >
+}
+
+define <2 x i32> @mvni2s_lsl16() {
+;CHECK:  mvni {{v[0-31]+}}.2s, #0x10, lsl #16
+   ret <2 x i32> < i32 4293918719, i32 4293918719 >
+}
+
+define <2 x i32> @mvni2s_lsl24() {
+;CHECK:  mvni {{v[0-31]+}}.2s, #0x10, lsl #24
+   ret <2 x i32> < i32 4026531839, i32 4026531839 >
+}
+
+define <4 x i32> @mvni4s_lsl0() {
+;CHECK:  mvni {{v[0-31]+}}.4s, #0x10
+   ret <4 x i32> < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
+}
+
+define <4 x i32> @mvni4s_lsl8() {
+;CHECK:  mvni {{v[0-31]+}}.4s, #0x10, lsl #8
+   ret <4 x i32> < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
+}
+
+define <4 x i32> @mvni4s_lsl16() {
+;CHECK:  mvni {{v[0-31]+}}.4s, #0x10, lsl #16
+   ret <4 x i32> < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
+
+}
+
+define <4 x i32> @mvni4s_lsl24() {
+;CHECK:  mvni {{v[0-31]+}}.4s, #0x10, lsl #24
+   ret <4 x i32> < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839 >
+}
+
+
+define <4 x i16> @mvni4h_lsl0() {
+;CHECK:  mvni {{v[0-31]+}}.4h, #0x10
+   ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
+}
+
+define <4 x i16> @mvni4h_lsl8() {
+;CHECK:  mvni {{v[0-31]+}}.4h, #0x10, lsl #8
+   ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
+}
+
+define <8 x i16> @mvni8h_lsl0() {
+;CHECK:  mvni {{v[0-31]+}}.8h, #0x10
+   ret <8 x i16> < i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519 >
+}
+
+define <8 x i16> @mvni8h_lsl8() {
+;CHECK:  mvni {{v[0-31]+}}.8h, #0x10, lsl #8
+   ret <8 x i16> < i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439 >
+}
+
+
+define <2 x i32> @movi2s_msl8(<2 x i32> %a) {
+;CHECK:  movi {{v[0-31]+}}.2s, #0xff, msl #8
+	ret <2 x i32> < i32 65535, i32 65535 >
+}
+
+define <2 x i32> @movi2s_msl16() {
+;CHECK:  movi {{v[0-31]+}}.2s, #0xff, msl #16
+   ret <2 x i32> < i32 16777215, i32 16777215 >
+}
+
+
+define <4 x i32> @movi4s_msl8() {
+;CHECK:  movi {{v[0-31]+}}.4s, #0xff, msl #8
+   ret <4 x i32> < i32 65535, i32 65535, i32 65535, i32 65535 >
+}
+
+define <4 x i32> @movi4s_msl16() {
+;CHECK:  movi {{v[0-31]+}}.4s, #0xff, msl #16
+   ret <4 x i32> < i32 16777215, i32 16777215, i32 16777215, i32 16777215 >
+}
+
+define <2 x i32> @mvni2s_msl8() {
+;CHECK:  mvni {{v[0-31]+}}.2s, #0x10, msl #8
+   ret <2 x i32> < i32 18446744073709547264, i32 18446744073709547264>
+}
+
+define <2 x i32> @mvni2s_msl16() {
+;CHECK:  mvni {{v[0-31]+}}.2s, #0x10, msl #16
+   ret <2 x i32> < i32 18446744073708437504, i32 18446744073708437504>
+}
+
+define <4 x i32> @mvni4s_msl8() {
+;CHECK:  mvni {{v[0-31]+}}.4s, #0x10, msl #8
+   ret <4 x i32> < i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264>
+}
+
+define <4 x i32> @mvni4s_msl16() {
+;CHECK:  mvni {{v[0-31]+}}.4s, #0x10, msl #16
+   ret <4 x i32> < i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504>
+}
+
+define <2 x i64> @movi2d() {
+;CHECK: movi {{v[0-31]+}}.2d, #0xff0000ff0000ffff
+	ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
+}
+
+define <1 x i64> @movid() {
+;CHECK: movi {{d[0-31]+}}, #0xff0000ff0000ffff
+	ret  <1 x i64> < i64 18374687574888349695 >
+}
+
+define <2 x float> @fmov2s() {
+;CHECK:  fmov {{v[0-31]+}}.2s, #-12.00000000
+	ret <2 x float> < float -1.2e1, float -1.2e1>
+}
+
+define <4 x float> @fmov4s() {
+;CHECK:  fmov {{v[0-31]+}}.4s, #-12.00000000
+	ret <4 x float> < float -1.2e1, float -1.2e1, float -1.2e1, float -1.2e1>
+}
+
+define <2 x double> @fmov2d() {
+;CHECK:  fmov {{v[0-31]+}}.2d, #-12.00000000
+	ret <2 x double> < double -1.2e1, double -1.2e1>
+}
+
+
diff --git a/test/CodeGen/AArch64/neon-mul-div.ll b/test/CodeGen/AArch64/neon-mul-div.ll
new file mode 100644
index 0000000..e1be313
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-mul-div.ll
@@ -0,0 +1,181 @@
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
+
+
+define <8 x i8> @mul8xi8(<8 x i8> %A, <8 x i8> %B) {
+;CHECK: mul {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
+	%tmp3 = mul <8 x i8> %A, %B;
+	ret <8 x i8> %tmp3
+}
+
+define <16 x i8> @mul16xi8(<16 x i8> %A, <16 x i8> %B) {
+;CHECK: mul {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
+	%tmp3 = mul <16 x i8> %A, %B;
+	ret <16 x i8> %tmp3
+}
+
+define <4 x i16> @mul4xi16(<4 x i16> %A, <4 x i16> %B) {
+;CHECK: mul {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
+	%tmp3 = mul <4 x i16> %A, %B;
+	ret <4 x i16> %tmp3
+}
+
+define <8 x i16> @mul8xi16(<8 x i16> %A, <8 x i16> %B) {
+;CHECK: mul {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
+	%tmp3 = mul <8 x i16> %A, %B;
+	ret <8 x i16> %tmp3
+}
+
+define <2 x i32> @mul2xi32(<2 x i32> %A, <2 x i32> %B) {
+;CHECK: mul {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
+	%tmp3 = mul <2 x i32> %A, %B;
+	ret <2 x i32> %tmp3
+}
+
+define <4 x i32> @mul4x32(<4 x i32> %A, <4 x i32> %B) {
+;CHECK: mul {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
+	%tmp3 = mul <4 x i32> %A, %B;
+	ret <4 x i32> %tmp3
+}
+
+ define <2 x float> @mul2xfloat(<2 x float> %A, <2 x float> %B) {
+;CHECK: fmul {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
+	%tmp3 = fmul <2 x float> %A, %B;
+	ret <2 x float> %tmp3
+}
+
+define <4 x float> @mul4xfloat(<4 x float> %A, <4 x float> %B) {
+;CHECK: fmul {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
+	%tmp3 = fmul <4 x float> %A, %B;
+	ret <4 x float> %tmp3
+}
+define <2 x double> @mul2xdouble(<2 x double> %A, <2 x double> %B) {
+;CHECK: fmul {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
+	%tmp3 = fmul <2 x double> %A, %B;
+	ret <2 x double> %tmp3
+}
+
+
+ define <2 x float> @div2xfloat(<2 x float> %A, <2 x float> %B) {
+;CHECK: fdiv {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
+	%tmp3 = fdiv <2 x float> %A, %B;
+	ret <2 x float> %tmp3
+}
+
+define <4 x float> @div4xfloat(<4 x float> %A, <4 x float> %B) {
+;CHECK: fdiv {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
+	%tmp3 = fdiv <4 x float> %A, %B;
+	ret <4 x float> %tmp3
+}
+define <2 x double> @div2xdouble(<2 x double> %A, <2 x double> %B) {
+;CHECK: fdiv {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
+	%tmp3 = fdiv <2 x double> %A, %B;
+	ret <2 x double> %tmp3
+}
+
+declare <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8>, <8 x i8>)
+declare <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8>, <16 x i8>)
+
+define <8 x i8> @poly_mulv8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: poly_mulv8i8:
+   %prod = call <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: pmul v0.8b, v0.8b, v1.8b
+   ret <8 x i8> %prod
+}
+
+define <16 x i8> @poly_mulv16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: poly_mulv16i8:
+   %prod = call <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: pmul v0.16b, v0.16b, v1.16b
+   ret <16 x i8> %prod
+}
+
+declare <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16>, <8 x i16>)
+declare <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i16> @test_sqdmulh_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_sqdmulh_v4i16:
+   %prod = call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: sqdmulh v0.4h, v0.4h, v1.4h
+   ret <4 x i16> %prod
+}
+
+define <8 x i16> @test_sqdmulh_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_sqdmulh_v8i16:
+   %prod = call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: sqdmulh v0.8h, v0.8h, v1.8h
+   ret <8 x i16> %prod
+}
+
+define <2 x i32> @test_sqdmulh_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_sqdmulh_v2i32:
+   %prod = call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: sqdmulh v0.2s, v0.2s, v1.2s
+   ret <2 x i32> %prod
+}
+
+define <4 x i32> @test_sqdmulh_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_sqdmulh_v4i32:
+   %prod = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: sqdmulh v0.4s, v0.4s, v1.4s
+   ret <4 x i32> %prod
+}
+
+declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>)
+declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>)
+declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>)
+declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i16> @test_sqrdmulh_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_sqrdmulh_v4i16:
+   %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: sqrdmulh v0.4h, v0.4h, v1.4h
+   ret <4 x i16> %prod
+}
+
+define <8 x i16> @test_sqrdmulh_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_sqrdmulh_v8i16:
+   %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: sqrdmulh v0.8h, v0.8h, v1.8h
+   ret <8 x i16> %prod
+}
+
+define <2 x i32> @test_sqrdmulh_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_sqrdmulh_v2i32:
+   %prod = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: sqrdmulh v0.2s, v0.2s, v1.2s
+   ret <2 x i32> %prod
+}
+
+define <4 x i32> @test_sqrdmulh_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_sqrdmulh_v4i32:
+   %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: sqrdmulh v0.4s, v0.4s, v1.4s
+   ret <4 x i32> %prod
+}
+
+declare <2 x float> @llvm.aarch64.neon.vmulx.v2f32(<2 x float>, <2 x float>)
+declare <4 x float> @llvm.aarch64.neon.vmulx.v4f32(<4 x float>, <4 x float>)
+declare <2 x double> @llvm.aarch64.neon.vmulx.v2f64(<2 x double>, <2 x double>)
+
+define <2 x float> @fmulx_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
+; Using registers other than v0, v1 and v2 are possible, but would be odd.
+; CHECK: fmulx v0.2s, v0.2s, v1.2s
+        %val = call <2 x float> @llvm.aarch64.neon.vmulx.v2f32(<2 x float> %lhs, <2 x float> %rhs)
+        ret <2 x float> %val
+}
+
+define <4 x float> @fmulx_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
+; Using registers other than v0, v1 and v2 are possible, but would be odd.
+; CHECK: fmulx v0.4s, v0.4s, v1.4s
+        %val = call <4 x float> @llvm.aarch64.neon.vmulx.v4f32(<4 x float> %lhs, <4 x float> %rhs)
+        ret <4 x float> %val
+}
+
+define <2 x double> @fmulx_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
+; Using registers other than v0, v1 and v2 are possible, but would be odd.
+; CHECK: fmulx v0.2d, v0.2d, v1.2d
+        %val = call <2 x double> @llvm.aarch64.neon.vmulx.v2f64(<2 x double> %lhs, <2 x double> %rhs)
+        ret <2 x double> %val
+}
diff --git a/test/CodeGen/AArch64/neon-rounding-halving-add.ll b/test/CodeGen/AArch64/neon-rounding-halving-add.ll
new file mode 100644
index 0000000..009da3b
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-rounding-halving-add.ll
@@ -0,0 +1,105 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+declare <8 x i8> @llvm.arm.neon.vrhaddu.v8i8(<8 x i8>, <8 x i8>)
+declare <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @test_urhadd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_urhadd_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vrhaddu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: urhadd v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+define <8 x i8> @test_srhadd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_srhadd_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vrhadds.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: srhadd v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+declare <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_urhadd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_urhadd_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vrhaddu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: urhadd v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+define <16 x i8> @test_srhadd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_srhadd_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vrhadds.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: srhadd v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+declare <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16>, <4 x i16>)
+declare <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @test_urhadd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_urhadd_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vrhaddu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: urhadd v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @test_srhadd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_srhadd_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vrhadds.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: srhadd v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+declare <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test_urhadd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_urhadd_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vrhaddu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: urhadd v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @test_srhadd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_srhadd_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vrhadds.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: srhadd v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+declare <2 x i32> @llvm.arm.neon.vrhaddu.v2i32(<2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.arm.neon.vrhadds.v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @test_urhadd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_urhadd_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vrhaddu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: urhadd v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @test_srhadd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_srhadd_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vrhadds.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: srhadd v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+declare <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @test_urhadd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_urhadd_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vrhaddu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: urhadd v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @test_srhadd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_srhadd_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vrhadds.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: srhadd v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+
diff --git a/test/CodeGen/AArch64/neon-rounding-shift.ll b/test/CodeGen/AArch64/neon-rounding-shift.ll
new file mode 100644
index 0000000..404e491
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-rounding-shift.ll
@@ -0,0 +1,138 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+declare <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8>, <8 x i8>)
+declare <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @test_urshl_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_urshl_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: urshl v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+define <8 x i8> @test_srshl_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_srshl_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: srshl v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+declare <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_urshl_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_urshl_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: urshl v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+define <16 x i8> @test_srshl_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_srshl_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: srshl v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+declare <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16>, <4 x i16>)
+declare <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @test_urshl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_urshl_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: urshl v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @test_srshl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_srshl_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: srshl v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test_urshl_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_urshl_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: urshl v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @test_srshl_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_srshl_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: srshl v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+declare <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @test_urshl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_urshl_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: urshl v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @test_srshl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_srshl_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: srshl v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+declare <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @test_urshl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_urshl_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: urshl v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @test_srshl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_srshl_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: srshl v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+declare <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64>, <1 x i64>)
+declare <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64>, <1 x i64>)
+
+define <1 x i64> @test_urshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
+; CHECK: test_urshl_v1i64:
+  %tmp1 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
+; CHECK: urshl d0, d0, d1
+  ret <1 x i64> %tmp1
+}
+
+define <1 x i64> @test_srshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
+; CHECK: test_srshl_v1i64:
+  %tmp1 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
+; CHECK: srshl d0, d0, d1
+  ret <1 x i64> %tmp1
+}
+
+declare <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64>, <2 x i64>)
+
+define <2 x i64> @test_urshl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
+; CHECK: test_urshl_v2i64:
+  %tmp1 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
+; CHECK: urshl v0.2d, v0.2d, v1.2d
+  ret <2 x i64> %tmp1
+}
+
+define <2 x i64> @test_srshl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
+; CHECK: test_srshl_v2i64:
+  %tmp1 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
+; CHECK: srshl v0.2d, v0.2d, v1.2d
+  ret <2 x i64> %tmp1
+}
+
diff --git a/test/CodeGen/AArch64/neon-saturating-add-sub.ll b/test/CodeGen/AArch64/neon-saturating-add-sub.ll
new file mode 100644
index 0000000..b2fac1f
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-saturating-add-sub.ll
@@ -0,0 +1,274 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+declare <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8>, <8 x i8>)
+declare <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @test_uqadd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_uqadd_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vqaddu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: uqadd v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+define <8 x i8> @test_sqadd_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_sqadd_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vqadds.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: sqadd v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+declare <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_uqadd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_uqadd_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vqaddu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: uqadd v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+define <16 x i8> @test_sqadd_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_sqadd_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vqadds.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: sqadd v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+declare <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16>, <4 x i16>)
+declare <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @test_uqadd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_uqadd_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vqaddu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: uqadd v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @test_sqadd_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_sqadd_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: sqadd v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+declare <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test_uqadd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_uqadd_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vqaddu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: uqadd v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @test_sqadd_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_sqadd_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: sqadd v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+declare <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @test_uqadd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_uqadd_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vqaddu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: uqadd v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @test_sqadd_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_sqadd_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: sqadd v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+declare <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @test_uqadd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_uqadd_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vqaddu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: uqadd v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @test_sqadd_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_sqadd_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: sqadd v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+declare <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64>, <1 x i64>)
+declare <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64>, <1 x i64>)
+
+define <1 x i64> @test_uqadd_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
+; CHECK: test_uqadd_v1i64:
+  %tmp1 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
+; CHECK: uqadd d0, d0, d1
+  ret <1 x i64> %tmp1
+}
+
+define <1 x i64> @test_sqadd_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
+; CHECK: test_sqadd_v1i64:
+  %tmp1 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
+; CHECK: sqadd d0, d0, d1
+  ret <1 x i64> %tmp1
+}
+
+declare <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64>, <2 x i64>)
+
+define <2 x i64> @test_uqadd_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
+; CHECK: test_uqadd_v2i64:
+  %tmp1 = call <2 x i64> @llvm.arm.neon.vqaddu.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
+; CHECK: uqadd v0.2d, v0.2d, v1.2d
+  ret <2 x i64> %tmp1
+}
+
+define <2 x i64> @test_sqadd_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
+; CHECK: test_sqadd_v2i64:
+  %tmp1 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
+; CHECK: sqadd v0.2d, v0.2d, v1.2d
+  ret <2 x i64> %tmp1
+}
+
+declare <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8>, <8 x i8>)
+declare <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @test_uqsub_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_uqsub_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vqsubu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: uqsub v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+define <8 x i8> @test_sqsub_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_sqsub_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vqsubs.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: sqsub v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+declare <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_uqsub_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_uqsub_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vqsubu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: uqsub v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+define <16 x i8> @test_sqsub_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_sqsub_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vqsubs.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: sqsub v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+declare <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16>, <4 x i16>)
+declare <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @test_uqsub_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_uqsub_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vqsubu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: uqsub v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @test_sqsub_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_sqsub_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: sqsub v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+declare <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test_uqsub_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_uqsub_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: uqsub v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @test_sqsub_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_sqsub_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: sqsub v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+declare <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @test_uqsub_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_uqsub_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vqsubu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: uqsub v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @test_sqsub_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_sqsub_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: sqsub v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+declare <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @test_uqsub_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_uqsub_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vqsubu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: uqsub v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @test_sqsub_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_sqsub_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: sqsub v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+declare <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64>, <2 x i64>)
+
+define <2 x i64> @test_uqsub_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
+; CHECK: test_uqsub_v2i64:
+  %tmp1 = call <2 x i64> @llvm.arm.neon.vqsubu.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
+; CHECK: uqsub v0.2d, v0.2d, v1.2d
+  ret <2 x i64> %tmp1
+}
+
+define <2 x i64> @test_sqsub_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
+; CHECK: test_sqsub_v2i64:
+  %tmp1 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
+; CHECK: sqsub v0.2d, v0.2d, v1.2d
+  ret <2 x i64> %tmp1
+}
+
+declare <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64>, <1 x i64>)
+declare <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64>, <1 x i64>)
+
+define <1 x i64> @test_uqsub_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
+; CHECK: test_uqsub_v1i64:
+  %tmp1 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
+; CHECK: uqsub d0, d0, d1
+  ret <1 x i64> %tmp1
+}
+
+define <1 x i64> @test_sqsub_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
+; CHECK: test_sqsub_v1i64:
+  %tmp1 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
+; CHECK: sqsub d0, d0, d1
+  ret <1 x i64> %tmp1
+}
+
diff --git a/test/CodeGen/AArch64/neon-saturating-rounding-shift.ll b/test/CodeGen/AArch64/neon-saturating-rounding-shift.ll
new file mode 100644
index 0000000..05d8dfe
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-saturating-rounding-shift.ll
@@ -0,0 +1,138 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+declare <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8>, <8 x i8>)
+declare <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @test_uqrshl_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_uqrshl_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vqrshiftu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: uqrshl v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+define <8 x i8> @test_sqrshl_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_sqrshl_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vqrshifts.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: sqrshl v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+declare <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_uqrshl_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_uqrshl_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vqrshiftu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: uqrshl v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+define <16 x i8> @test_sqrshl_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_sqrshl_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vqrshifts.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: sqrshl v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+declare <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16>, <4 x i16>)
+declare <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @test_uqrshl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_uqrshl_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vqrshiftu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: uqrshl v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @test_sqrshl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_sqrshl_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vqrshifts.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: sqrshl v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+declare <8 x i16> @llvm.arm.neon.vqrshiftu.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.arm.neon.vqrshifts.v8i16(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test_uqrshl_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_uqrshl_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vqrshiftu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: uqrshl v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @test_sqrshl_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_sqrshl_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vqrshifts.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: sqrshl v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+declare <2 x i32> @llvm.arm.neon.vqrshiftu.v2i32(<2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.arm.neon.vqrshifts.v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @test_uqrshl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_uqrshl_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vqrshiftu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: uqrshl v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @test_sqrshl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_sqrshl_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vqrshifts.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: sqrshl v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+declare <4 x i32> @llvm.arm.neon.vqrshiftu.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.arm.neon.vqrshifts.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @test_uqrshl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_uqrshl_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vqrshiftu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: uqrshl v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @test_sqrshl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_sqrshl_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vqrshifts.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: sqrshl v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+declare <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64>, <1 x i64>)
+declare <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64>, <1 x i64>)
+
+define <1 x i64> @test_uqrshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
+; CHECK: test_uqrshl_v1i64:
+  %tmp1 = call <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
+; CHECK: uqrshl d0, d0, d1
+  ret <1 x i64> %tmp1
+}
+
+define <1 x i64> @test_sqrshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
+; CHECK: test_sqrshl_v1i64:
+  %tmp1 = call <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
+; CHECK: sqrshl d0, d0, d1
+  ret <1 x i64> %tmp1
+}
+
+declare <2 x i64> @llvm.arm.neon.vqrshiftu.v2i64(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.arm.neon.vqrshifts.v2i64(<2 x i64>, <2 x i64>)
+
+define <2 x i64> @test_uqrshl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
+; CHECK: test_uqrshl_v2i64:
+  %tmp1 = call <2 x i64> @llvm.arm.neon.vqrshiftu.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
+; CHECK: uqrshl v0.2d, v0.2d, v1.2d
+  ret <2 x i64> %tmp1
+}
+
+define <2 x i64> @test_sqrshl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
+; CHECK: test_sqrshl_v2i64:
+  %tmp1 = call <2 x i64> @llvm.arm.neon.vqrshifts.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
+; CHECK: sqrshl v0.2d, v0.2d, v1.2d
+  ret <2 x i64> %tmp1
+}
+
diff --git a/test/CodeGen/AArch64/neon-saturating-shift.ll b/test/CodeGen/AArch64/neon-saturating-shift.ll
new file mode 100644
index 0000000..3b7f78c
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-saturating-shift.ll
@@ -0,0 +1,138 @@
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
+
+declare <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8>, <8 x i8>)
+declare <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @test_uqshl_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_uqshl_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: uqshl v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+define <8 x i8> @test_sqshl_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_sqshl_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: sqshl v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+declare <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_uqshl_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_uqshl_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: uqshl v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+define <16 x i8> @test_sqshl_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_sqshl_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: sqshl v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+declare <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16>, <4 x i16>)
+declare <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @test_uqshl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_uqshl_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: uqshl v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @test_sqshl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_sqshl_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: sqshl v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+declare <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test_uqshl_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_uqshl_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: uqshl v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @test_sqshl_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_sqshl_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: sqshl v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+declare <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @test_uqshl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_uqshl_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: uqshl v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @test_sqshl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_sqshl_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: sqshl v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+declare <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @test_uqshl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_uqshl_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: uqshl v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @test_sqshl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_sqshl_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: sqshl v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+declare <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64>, <1 x i64>)
+declare <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64>, <1 x i64>)
+
+define <1 x i64> @test_uqshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
+; CHECK: test_uqshl_v1i64:
+  %tmp1 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
+; CHECK: uqshl d0, d0, d1
+  ret <1 x i64> %tmp1
+}
+
+define <1 x i64> @test_sqshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
+; CHECK: test_sqshl_v1i64:
+  %tmp1 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
+; CHECK: sqshl d0, d0, d1
+  ret <1 x i64> %tmp1
+}
+
+declare <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64>, <2 x i64>)
+
+define <2 x i64> @test_uqshl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
+; CHECK: test_uqshl_v2i64:
+  %tmp1 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
+; CHECK: uqshl v0.2d, v0.2d, v1.2d
+  ret <2 x i64> %tmp1
+}
+
+define <2 x i64> @test_sqshl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
+; CHECK: test_sqshl_v2i64:
+  %tmp1 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
+; CHECK: sqshl v0.2d, v0.2d, v1.2d
+  ret <2 x i64> %tmp1
+}
+
diff --git a/test/CodeGen/AArch64/neon-shift.ll b/test/CodeGen/AArch64/neon-shift.ll
new file mode 100644
index 0000000..45a2605
--- /dev/null
+++ b/test/CodeGen/AArch64/neon-shift.ll
@@ -0,0 +1,140 @@
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
+
+declare <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8>, <8 x i8>)
+declare <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8>, <8 x i8>)
+
+define <8 x i8> @test_uqshl_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_uqshl_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: ushl v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+define <8 x i8> @test_sqshl_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
+; CHECK: test_sqshl_v8i8:
+  %tmp1 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
+; CHECK: sshl v0.8b, v0.8b, v1.8b
+  ret <8 x i8> %tmp1
+}
+
+declare <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @test_ushl_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_ushl_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: ushl v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+define <16 x i8> @test_sshl_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
+; CHECK: test_sshl_v16i8:
+  %tmp1 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
+; CHECK: sshl v0.16b, v0.16b, v1.16b
+  ret <16 x i8> %tmp1
+}
+
+declare <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16>, <4 x i16>)
+declare <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16>, <4 x i16>)
+
+define <4 x i16> @test_ushl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_ushl_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: ushl v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+define <4 x i16> @test_sshl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
+; CHECK: test_sshl_v4i16:
+  %tmp1 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
+; CHECK: sshl v0.4h, v0.4h, v1.4h
+  ret <4 x i16> %tmp1
+}
+
+declare <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @test_ushl_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_ushl_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: ushl v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+define <8 x i16> @test_sshl_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
+; CHECK: test_sshl_v8i16:
+  %tmp1 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
+; CHECK: sshl v0.8h, v0.8h, v1.8h
+  ret <8 x i16> %tmp1
+}
+
+declare <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32>, <2 x i32>)
+
+define <2 x i32> @test_ushl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_ushl_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: ushl v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+define <2 x i32> @test_sshl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
+; CHECK: test_sshl_v2i32:
+  %tmp1 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
+; CHECK: sshl v0.2s, v0.2s, v1.2s
+  ret <2 x i32> %tmp1
+}
+
+declare <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32>, <4 x i32>)
+
+define <4 x i32> @test_ushl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_ushl_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: ushl v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+define <4 x i32> @test_sshl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
+; CHECK: test_sshl_v4i32:
+  %tmp1 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
+; CHECK: sshl v0.4s, v0.4s, v1.4s
+  ret <4 x i32> %tmp1
+}
+
+declare <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64>, <1 x i64>)
+declare <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64>, <1 x i64>)
+
+define <1 x i64> @test_ushl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
+; CHECK: test_ushl_v1i64:
+  %tmp1 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
+; CHECK: ushl d0, d0, d1
+  ret <1 x i64> %tmp1
+}
+
+define <1 x i64> @test_sshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
+; CHECK: test_sshl_v1i64:
+  %tmp1 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
+; CHECK: sshl d0, d0, d1
+  ret <1 x i64> %tmp1
+}
+
+declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>)
+declare <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64>, <2 x i64>)
+
+define <2 x i64> @test_ushl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
+; CHECK: test_ushl_v2i64:
+  %tmp1 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
+; CHECK: ushl v0.2d, v0.2d, v1.2d
+  ret <2 x i64> %tmp1
+}
+
+define <2 x i64> @test_sshl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
+; CHECK: test_sshl_v2i64:
+  %tmp1 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
+; CHECK: sshl v0.2d, v0.2d, v1.2d
+  ret <2 x i64> %tmp1
+}
+
+
+
diff --git a/test/CodeGen/AArch64/pic-eh-stubs.ll b/test/CodeGen/AArch64/pic-eh-stubs.ll
index 77bf691..6ec4b19 100644
--- a/test/CodeGen/AArch64/pic-eh-stubs.ll
+++ b/test/CodeGen/AArch64/pic-eh-stubs.ll
@@ -57,4 +57,4 @@ declare i32 @llvm.eh.typeid.for(i8*) nounwind readnone
 
 declare i8* @__cxa_begin_catch(i8*)
 
-declare void @__cxa_end_catch()
\ No newline at end of file
+declare void @__cxa_end_catch()
diff --git a/test/CodeGen/AArch64/regress-bitcast-formals.ll b/test/CodeGen/AArch64/regress-bitcast-formals.ll
index 28dc9a7..9655f90 100644
--- a/test/CodeGen/AArch64/regress-bitcast-formals.ll
+++ b/test/CodeGen/AArch64/regress-bitcast-formals.ll
@@ -4,7 +4,7 @@
 ; actually capable of that (the test was omitted from LowerFormalArguments).
 
 define void @test_bitcast_lower(<2 x i32> %a) {
-; CHECK: test_bitcast_lower:
+; CHECK-LABEL: test_bitcast_lower:
 
   ret void
 ; CHECK: ret
diff --git a/test/CodeGen/AArch64/regress-tail-livereg.ll b/test/CodeGen/AArch64/regress-tail-livereg.ll
index 8d5485c..053249c 100644
--- a/test/CodeGen/AArch64/regress-tail-livereg.ll
+++ b/test/CodeGen/AArch64/regress-tail-livereg.ll
@@ -4,7 +4,7 @@
 declare void @bar()
 
 define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
        %func = load void()** @var
 
        ; Calling a function encourages @foo to use a callee-saved register,
@@ -16,4 +16,4 @@ define void @foo() {
        tail call void %func()
 ; CHECK: br {{x([0-79]|1[0-8])}}
        ret void
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/AArch64/regress-tblgen-chains.ll b/test/CodeGen/AArch64/regress-tblgen-chains.ll
index e54552f..ff77fb4 100644
--- a/test/CodeGen/AArch64/regress-tblgen-chains.ll
+++ b/test/CodeGen/AArch64/regress-tblgen-chains.ll
@@ -12,7 +12,7 @@
 declare void @bar(i8*)
 
 define i64 @test_chains() {
-; CHECK: test_chains:
+; CHECK-LABEL: test_chains:
 
   %locvar = alloca i8
 
diff --git a/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll b/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
index 9176651..0ef9818 100644
--- a/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
+++ b/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
@@ -4,7 +4,7 @@
 declare void @bar()
 
 define void @test_w29_reserved() {
-; CHECK: test_w29_reserved:
+; CHECK-LABEL: test_w29_reserved:
 ; CHECK: .cfi_startproc
 ; CHECK: .cfi_def_cfa sp, 96
 ; CHECK: add x29, sp, #{{[0-9]+}}
diff --git a/test/CodeGen/AArch64/setcc-takes-i32.ll b/test/CodeGen/AArch64/setcc-takes-i32.ll
index d2eb77a..bd79685 100644
--- a/test/CodeGen/AArch64/setcc-takes-i32.ll
+++ b/test/CodeGen/AArch64/setcc-takes-i32.ll
@@ -12,11 +12,11 @@
 declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64)
 
 define i64 @test_select(i64 %lhs, i64 %rhs) {
-; CHECK: test_select:
+; CHECK-LABEL: test_select:
 
   %res = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %lhs, i64 %rhs)
   %flag = extractvalue {i64, i1} %res, 1
   %retval = select i1 %flag, i64 %lhs, i64 %rhs
   ret i64 %retval
 ; CHECK: ret
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/AArch64/sibling-call.ll b/test/CodeGen/AArch64/sibling-call.ll
index 6df4e7e..20f1062 100644
--- a/test/CodeGen/AArch64/sibling-call.ll
+++ b/test/CodeGen/AArch64/sibling-call.ll
@@ -5,7 +5,7 @@ declare void @callee_stack8([8 x i32], i64)
 declare void @callee_stack16([8 x i32], i64, i64)
 
 define void @caller_to0_from0() nounwind {
-; CHECK: caller_to0_from0:
+; CHECK-LABEL: caller_to0_from0:
 ; CHECK-NEXT: // BB
   tail call void @callee_stack0()
   ret void
@@ -13,7 +13,7 @@ define void @caller_to0_from0() nounwind {
 }
 
 define void @caller_to0_from8([8 x i32], i64) nounwind{
-; CHECK: caller_to0_from8:
+; CHECK-LABEL: caller_to0_from8:
 ; CHECK-NEXT: // BB
 
   tail call void @callee_stack0()
@@ -22,7 +22,7 @@ define void @caller_to0_from8([8 x i32], i64) nounwind{
 }
 
 define void @caller_to8_from0() {
-; CHECK: caller_to8_from0:
+; CHECK-LABEL: caller_to8_from0:
 
 ; Caller isn't going to clean up any extra stack we allocate, so it
 ; can't be a tail call.
@@ -32,7 +32,7 @@ define void @caller_to8_from0() {
 }
 
 define void @caller_to8_from8([8 x i32], i64 %a) {
-; CHECK: caller_to8_from8:
+; CHECK-LABEL: caller_to8_from8:
 ; CHECK-NOT: sub sp, sp,
 
 ; This should reuse our stack area for the 42
@@ -43,7 +43,7 @@ define void @caller_to8_from8([8 x i32], i64 %a) {
 }
 
 define void @caller_to16_from8([8 x i32], i64 %a) {
-; CHECK: caller_to16_from8:
+; CHECK-LABEL: caller_to16_from8:
 
 ; Shouldn't be a tail call: we can't use SP+8 because our caller might
 ; have something there. This may sound obvious but implementation does
@@ -54,7 +54,7 @@ define void @caller_to16_from8([8 x i32], i64 %a) {
 }
 
 define void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
-; CHECK: caller_to8_from24:
+; CHECK-LABEL: caller_to8_from24:
 ; CHECK-NOT: sub sp, sp
 
 ; Reuse our area, putting "42" at incoming sp
@@ -65,7 +65,7 @@ define void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
 }
 
 define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
-; CHECK: caller_to16_from16:
+; CHECK-LABEL: caller_to16_from16:
 ; CHECK-NOT: sub sp, sp,
 
 ; Here we want to make sure that both loads happen before the stores:
@@ -85,7 +85,7 @@ define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
 @func = global void(i32)* null
 
 define void @indirect_tail() {
-; CHECK: indirect_tail:
+; CHECK-LABEL: indirect_tail:
 ; CHECK-NOT: sub sp, sp
 
   %fptr = load void(i32)** @func
diff --git a/test/CodeGen/AArch64/sincos-expansion.ll b/test/CodeGen/AArch64/sincos-expansion.ll
index f1b7441..4cd4449 100644
--- a/test/CodeGen/AArch64/sincos-expansion.ll
+++ b/test/CodeGen/AArch64/sincos-expansion.ll
@@ -32,4 +32,4 @@ declare double @sin(double) readonly
 declare fp128 @sinl(fp128) readonly
 declare float @cosf(float) readonly
 declare double @cos(double) readonly
-declare fp128 @cosl(fp128) readonly
\ No newline at end of file
+declare fp128 @cosl(fp128) readonly
diff --git a/test/CodeGen/AArch64/tail-call.ll b/test/CodeGen/AArch64/tail-call.ll
index f323b15..81885f1 100644
--- a/test/CodeGen/AArch64/tail-call.ll
+++ b/test/CodeGen/AArch64/tail-call.ll
@@ -5,7 +5,7 @@ declare fastcc void @callee_stack8([8 x i32], i64)
 declare fastcc void @callee_stack16([8 x i32], i64, i64)
 
 define fastcc void @caller_to0_from0() nounwind {
-; CHECK: caller_to0_from0:
+; CHECK-LABEL: caller_to0_from0:
 ; CHECK-NEXT: // BB
   tail call fastcc void @callee_stack0()
   ret void
@@ -13,7 +13,7 @@ define fastcc void @caller_to0_from0() nounwind {
 }
 
 define fastcc void @caller_to0_from8([8 x i32], i64) {
-; CHECK: caller_to0_from8:
+; CHECK-LABEL: caller_to0_from8:
 
   tail call fastcc void @callee_stack0()
   ret void
@@ -22,7 +22,7 @@ define fastcc void @caller_to0_from8([8 x i32], i64) {
 }
 
 define fastcc void @caller_to8_from0() {
-; CHECK: caller_to8_from0:
+; CHECK-LABEL: caller_to8_from0:
 ; CHECK: sub sp, sp, #32
 
 ; Key point is that the "42" should go #16 below incoming stack
@@ -35,7 +35,7 @@ define fastcc void @caller_to8_from0() {
 }
 
 define fastcc void @caller_to8_from8([8 x i32], i64 %a) {
-; CHECK: caller_to8_from8:
+; CHECK-LABEL: caller_to8_from8:
 ; CHECK: sub sp, sp, #16
 
 ; Key point is that the "%a" should go where at SP on entry.
@@ -47,7 +47,7 @@ define fastcc void @caller_to8_from8([8 x i32], i64 %a) {
 }
 
 define fastcc void @caller_to16_from8([8 x i32], i64 %a) {
-; CHECK: caller_to16_from8:
+; CHECK-LABEL: caller_to16_from8:
 ; CHECK: sub sp, sp, #16
 
 ; Important point is that the call reuses the "dead" argument space
@@ -63,7 +63,7 @@ define fastcc void @caller_to16_from8([8 x i32], i64 %a) {
 
 
 define fastcc void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
-; CHECK: caller_to8_from24:
+; CHECK-LABEL: caller_to8_from24:
 ; CHECK: sub sp, sp, #16
 
 ; Key point is that the "%a" should go where at #16 above SP on entry.
@@ -76,7 +76,7 @@ define fastcc void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
 
 
 define fastcc void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
-; CHECK: caller_to16_from16:
+; CHECK-LABEL: caller_to16_from16:
 ; CHECK: sub sp, sp, #16
 
 ; Here we want to make sure that both loads happen before the stores:
diff --git a/test/CodeGen/AArch64/tls-dynamic-together.ll b/test/CodeGen/AArch64/tls-dynamic-together.ll
index bad2298..b5d7d89 100644
--- a/test/CodeGen/AArch64/tls-dynamic-together.ll
+++ b/test/CodeGen/AArch64/tls-dynamic-together.ll
@@ -8,7 +8,7 @@
 @general_dynamic_var = external thread_local global i32
 
 define i32 @test_generaldynamic() {
-; CHECK: test_generaldynamic:
+; CHECK-LABEL: test_generaldynamic:
 
   %val = load i32* @general_dynamic_var
   ret i32 %val
diff --git a/test/CodeGen/AArch64/tls-dynamics.ll b/test/CodeGen/AArch64/tls-dynamics.ll
index cdfd117..887d2f8 100644
--- a/test/CodeGen/AArch64/tls-dynamics.ll
+++ b/test/CodeGen/AArch64/tls-dynamics.ll
@@ -4,7 +4,7 @@
 @general_dynamic_var = external thread_local global i32
 
 define i32 @test_generaldynamic() {
-; CHECK: test_generaldynamic:
+; CHECK-LABEL: test_generaldynamic:
 
   %val = load i32* @general_dynamic_var
   ret i32 %val
@@ -26,7 +26,7 @@ define i32 @test_generaldynamic() {
 }
 
 define i32* @test_generaldynamic_addr() {
-; CHECK: test_generaldynamic_addr:
+; CHECK-LABEL: test_generaldynamic_addr:
 
   ret i32* @general_dynamic_var
 
@@ -49,7 +49,7 @@ define i32* @test_generaldynamic_addr() {
 @local_dynamic_var = external thread_local(localdynamic) global i32
 
 define i32 @test_localdynamic() {
-; CHECK: test_localdynamic:
+; CHECK-LABEL: test_localdynamic:
 
   %val = load i32* @local_dynamic_var
   ret i32 %val
@@ -73,7 +73,7 @@ define i32 @test_localdynamic() {
 }
 
 define i32* @test_localdynamic_addr() {
-; CHECK: test_localdynamic_addr:
+; CHECK-LABEL: test_localdynamic_addr:
 
   ret i32* @local_dynamic_var
 
@@ -101,7 +101,7 @@ define i32* @test_localdynamic_addr() {
 @local_dynamic_var2 = external thread_local(localdynamic) global i32
 
 define i32 @test_localdynamic_deduplicate() {
-; CHECK: test_localdynamic_deduplicate:
+; CHECK-LABEL: test_localdynamic_deduplicate:
 
   %val = load i32* @local_dynamic_var
   %val2 = load i32* @local_dynamic_var2
diff --git a/test/CodeGen/AArch64/tls-execs.ll b/test/CodeGen/AArch64/tls-execs.ll
index a665884..39ceb9a 100644
--- a/test/CodeGen/AArch64/tls-execs.ll
+++ b/test/CodeGen/AArch64/tls-execs.ll
@@ -1,10 +1,10 @@
-; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -show-mc-encoding < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
 
 @initial_exec_var = external thread_local(initialexec) global i32
 
 define i32 @test_initial_exec() {
-; CHECK: test_initial_exec:
+; CHECK-LABEL: test_initial_exec:
   %val = load i32* @initial_exec_var
 
 ; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var
@@ -19,7 +19,7 @@ define i32 @test_initial_exec() {
 }
 
 define i32* @test_initial_exec_addr() {
-; CHECK: test_initial_exec_addr:
+; CHECK-LABEL: test_initial_exec_addr:
   ret i32* @initial_exec_var
 
 ; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var
@@ -35,10 +35,10 @@ define i32* @test_initial_exec_addr() {
 @local_exec_var = thread_local(initialexec) global i32 0
 
 define i32 @test_local_exec() {
-; CHECK: test_local_exec:
+; CHECK-LABEL: test_local_exec:
   %val = load i32* @local_exec_var
 
-; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var
+; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var // encoding: [A,A,0xa0'A',0x92'A']
 ; CHECK: movk [[TP_OFFSET]], #:tprel_g0_nc:local_exec_var
 ; CHECK: mrs x[[TP:[0-9]+]], tpidr_el0
 ; CHECK: ldr w0, [x[[TP]], [[TP_OFFSET]]]
@@ -50,7 +50,7 @@ define i32 @test_local_exec() {
 }
 
 define i32* @test_local_exec_addr() {
-; CHECK: test_local_exec_addr:
+; CHECK-LABEL: test_local_exec_addr:
   ret i32* @local_exec_var
 
 ; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var
diff --git a/test/CodeGen/AArch64/tst-br.ll b/test/CodeGen/AArch64/tst-br.ll
index 65c1fda..154bc08 100644
--- a/test/CodeGen/AArch64/tst-br.ll
+++ b/test/CodeGen/AArch64/tst-br.ll
@@ -7,7 +7,7 @@
 @var64 = global i64 0
 
 define i32 @test_tbz() {
-; CHECK: test_tbz:
+; CHECK-LABEL: test_tbz:
 
   %val = load i32* @var32
   %val64 = load i64* @var64
diff --git a/test/CodeGen/AArch64/variadic.ll b/test/CodeGen/AArch64/variadic.ll
index c5d319e..1c7e3bf 100644
--- a/test/CodeGen/AArch64/variadic.ll
+++ b/test/CodeGen/AArch64/variadic.ll
@@ -7,7 +7,7 @@
 declare void @llvm.va_start(i8*)
 
 define void @test_simple(i32 %n, ...) {
-; CHECK: test_simple:
+; CHECK-LABEL: test_simple:
 ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
 ; CHECK: mov x[[FPRBASE:[0-9]+]], sp
 ; CHECK: str q7, [x[[FPRBASE]], #112]
@@ -37,7 +37,7 @@ define void @test_simple(i32 %n, ...) {
 }
 
 define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
-; CHECK: test_fewargs:
+; CHECK-LABEL: test_fewargs:
 ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
 ; CHECK: mov x[[FPRBASE:[0-9]+]], sp
 ; CHECK: str q7, [x[[FPRBASE]], #96]
@@ -67,7 +67,7 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
 }
 
 define void @test_nospare([8 x i64], [8 x float], ...) {
-; CHECK: test_nospare:
+; CHECK-LABEL: test_nospare:
 
   %addr = bitcast %va_list* @var to i8*
   call void @llvm.va_start(i8* %addr)
@@ -81,7 +81,7 @@ define void @test_nospare([8 x i64], [8 x float], ...) {
 ; If there are non-variadic arguments on the stack (here two i64s) then the
 ; __stack field should point just past them.
 define void @test_offsetstack([10 x i64], [3 x float], ...) {
-; CHECK: test_offsetstack:
+; CHECK-LABEL: test_offsetstack:
 ; CHECK: sub sp, sp, #80
 ; CHECK: mov x[[FPRBASE:[0-9]+]], sp
 ; CHECK: str q7, [x[[FPRBASE]], #64]
@@ -108,7 +108,7 @@ define void @test_offsetstack([10 x i64], [3 x float], ...) {
 declare void @llvm.va_end(i8*)
 
 define void @test_va_end() nounwind {
-; CHECK: test_va_end:
+; CHECK-LABEL: test_va_end:
 ; CHECK-NEXT: BB#0
 
   %addr = bitcast %va_list* @var to i8*
@@ -123,7 +123,7 @@ declare void @llvm.va_copy(i8* %dest, i8* %src)
 @second_list = global %va_list zeroinitializer
 
 define void @test_va_copy() {
-; CHECK: test_va_copy:
+; CHECK-LABEL: test_va_copy:
   %srcaddr = bitcast %va_list* @var to i8*
   %dstaddr = bitcast %va_list* @second_list to i8*
   call void @llvm.va_copy(i8* %dstaddr, i8* %srcaddr)
diff --git a/test/CodeGen/AArch64/zero-reg.ll b/test/CodeGen/AArch64/zero-reg.ll
index fef0437..9b1e527 100644
--- a/test/CodeGen/AArch64/zero-reg.ll
+++ b/test/CodeGen/AArch64/zero-reg.ll
@@ -4,7 +4,7 @@
 @var64 = global i64 0
 
 define void @test_zr() {
-; CHECK: test_zr:
+; CHECK-LABEL: test_zr:
 
   store i32 0, i32* @var32
 ; CHECK: str wzr, [{{x[0-9]+}}, #:lo12:var32]
@@ -16,7 +16,7 @@ define void @test_zr() {
 }
 
 define void @test_sp(i32 %val) {
-; CHECK: test_sp:
+; CHECK-LABEL: test_sp:
 
 ; Important correctness point here is that LLVM doesn't try to use xzr
 ; as an addressing register: "str w0, [xzr]" is not a valid A64
@@ -28,4 +28,4 @@ define void @test_sp(i32 %val) {
 
   ret void
 ; CHECK: ret
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
index 0bfe331..e7c0129 100644
--- a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
+++ b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
@@ -4,7 +4,7 @@
 @dequant_coef = external global [6 x [4 x [4 x i32]]]		; <[6 x [4 x [4 x i32]]]*> [#uses=1]
 @A = external global [4 x [4 x i32]]		; <[4 x [4 x i32]]*> [#uses=1]
 
-; CHECK: dct_luma_sp:
+; CHECK-LABEL: dct_luma_sp:
 define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) {
 entry:
 ; Make sure to use base-updating stores for saving callee-saved registers.
diff --git a/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll b/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
index e1e60e6..ee99c70 100644
--- a/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
+++ b/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 ; pr4843
 define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind {
-;CHECK: v2regbug:
+;CHECK-LABEL: v2regbug:
 ;CHECK: vzip.16
 	%tmp1 = load <4 x i16>* %B
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32><i32 0, i32 0, i32 1, i32 1>
diff --git a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
index 0fe3b39..e2ff164 100644
--- a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
+++ b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll
@@ -4,7 +4,7 @@
 %0 = type { double, double }
 
 define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: bl __aeabi_dadd
 ; CHECK-NOT: strd
 ; CHECK: mov
diff --git a/test/CodeGen/ARM/2009-10-16-Scope.ll b/test/CodeGen/ARM/2009-10-16-Scope.ll
index a2e7ff7..dd08b56 100644
--- a/test/CodeGen/ARM/2009-10-16-Scope.ll
+++ b/test/CodeGen/ARM/2009-10-16-Scope.ll
@@ -23,10 +23,13 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 declare i32 @foo(i32) ssp
 
 !0 = metadata !{i32 5, i32 2, metadata !1, null}
-!1 = metadata !{i32 458763, metadata !2, i32 1, i32 1}; [DW_TAG_lexical_block ]
-!2 = metadata !{i32 458798, i32 0, metadata !3, metadata !"bar", metadata !"bar", metadata !"bar", metadata !3, i32 4, null, i1 false, i1 true}; [DW_TAG_subprogram ]
-!3 = metadata !{i32 458769, i32 0, i32 12, metadata !"genmodes.i", metadata !"/Users/yash/Downloads", metadata !"clang 1.1", i1 true, i1 false, metadata !"", i32 0}; [DW_TAG_compile_unit ]
+!1 = metadata !{i32 458763, null, metadata !2, i32 1, i32 1, i32 0}; [DW_TAG_lexical_block ]
+!2 = metadata !{i32 458798, i32 0, metadata !3, metadata !"bar", metadata !"bar", metadata !"bar", i32 4, null, i1 false, i1 true,
+                i32 0, i32 0, null, i32 0, i32 0, null, null, null, null, i32 0}; [DW_TAG_subprogram ]
+!3 = metadata !{i32 458769, metadata !8, i32 12, metadata !"clang 1.1", i1 true, metadata !"", i32 0, null, metadata !9, null, null, null, metadata !""}; [DW_TAG_compile_unit ]
 !4 = metadata !{i32 459008, metadata !5, metadata !"count_", metadata !3, i32 5, metadata !6}; [ DW_TAG_auto_variable ]
-!5 = metadata !{i32 458763, metadata !1, i32 1, i32 1}; [DW_TAG_lexical_block ]
-!6 = metadata !{i32 458788, metadata !3, metadata !"int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}; [DW_TAG_base_type ]
+!5 = metadata !{i32 458763, null, metadata !1, i32 1, i32 1, i32 0}; [DW_TAG_lexical_block ]
+!6 = metadata !{i32 458788, null, metadata !3, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}; [DW_TAG_base_type ]
 !7 = metadata !{i32 6, i32 1, metadata !2, null}
+!8 = metadata !{metadata !"genmodes.i", metadata !"/Users/yash/Downloads"}
+!9 = metadata !{i32 0}
diff --git a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
index a8afc20..4fb2be0 100644
--- a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
+++ b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
@@ -12,7 +12,7 @@ entry:
   %3 = fmul float %0, %1                          ; <float> [#uses=1]
   %4 = fadd float 0.000000e+00, %3                ; <float> [#uses=1]
   %5 = fsub float 1.000000e+00, %4                ; <float> [#uses=1]
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: vmov.f32 s{{[0-9]+}}, #1.000000e+00
   %6 = fsub float 1.000000e+00, undef             ; <float> [#uses=2]
   %7 = fsub float %2, undef                       ; <float> [#uses=1]
diff --git a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll
index 05581c3..89f468a 100644
--- a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll
+++ b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll
@@ -12,15 +12,19 @@ entry:
 
 declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
-!0 = metadata !{i32 524545, metadata !1, metadata !"b", metadata !2, i32 93, metadata !6} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"__addvsi3", metadata !"__addvsi3", metadata !"__addvsi3", metadata !2, i32 94, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
-!2 = metadata !{i32 524329, metadata !"libgcc2.c", metadata !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc", metadata !3} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"libgcc2.c", metadata !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!llvm.dbg.cu = !{!3}
+!0 = metadata !{i32 524545, metadata !1, metadata !"b", metadata !2, i32 93, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ]
+!1 = metadata !{i32 524334, metadata !12, null, metadata !"__addvsi3", metadata !"__addvsi3", metadata !"__addvsi3", i32 94, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 524329, metadata !12} ; [ DW_TAG_file_type ]
+!12 = metadata !{metadata !"libgcc2.c", metadata !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc"}
+!3 = metadata !{i32 524305, metadata !12, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)", i1 true, metadata !"", i32 0, metadata !13, metadata !13, metadata !14, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!4 = metadata !{i32 524309, metadata !12, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{metadata !6, metadata !6, metadata !6}
-!6 = metadata !{i32 524310, metadata !2, metadata !"SItype", metadata !7, i32 152, i64 0, i64 0, i64 0, i32 0, metadata !8} ; [ DW_TAG_typedef ]
+!6 = metadata !{i32 524310, metadata !12, null, metadata !"SItype", i32 152, i64 0, i64 0, i64 0, i32 0, metadata !8} ; [ DW_TAG_typedef ]
 !7 = metadata !{i32 524329, metadata !"libgcc2.h", metadata !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc", metadata !3} ; [ DW_TAG_file_type ]
-!8 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!8 = metadata !{i32 524324, metadata !12, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !9 = metadata !{i32 95, i32 0, metadata !10, null}
-!10 = metadata !{i32 524299, metadata !1, i32 94, i32 0} ; [ DW_TAG_lexical_block ]
+!10 = metadata !{i32 524299, metadata !12, metadata !1, i32 94, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !11 = metadata !{i32 100, i32 0, metadata !10, null}
+!13 = metadata !{i32 0}
+!14 = metadata !{metadata !1}
diff --git a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
index 0ae7f84..35995b7 100644
--- a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
+++ b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll
@@ -6,10 +6,10 @@
 
 define zeroext i8 @t(%struct.foo* %this) noreturn optsize {
 entry:
-; ARM:       t:
+; ARM-LABEL:       t:
 ; ARM:       str r2, [r1], r0
 
-; THUMB:     t:
+; THUMB-LABEL:     t:
 ; THUMB-NOT: str r0, [r1], r0
 ; THUMB:     str r1, [r0]
   %0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1]
diff --git a/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll
index cdb11c7..a53200e 100644
--- a/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll
+++ b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll
@@ -48,19 +48,19 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !llvm.dbg.gv = !{!14}
 
 !0 = metadata !{i32 524545, metadata !1, metadata !"buf", metadata !2, i32 4, metadata !6} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"x0", metadata !"x0", metadata !"x0", metadata !2, i32 5, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!2 = metadata !{i32 524329, metadata !"t.c", metadata !"/private/tmp", metadata !3} ; [ DW_TAG_file_type ]
+!1 = metadata !{i32 524334, metadata !26, null, metadata !"x0", metadata !"x0", metadata !"x0", i32 5, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 524329, metadata !26} ; [ DW_TAG_file_type ]
 !3 = metadata !{i32 524305, i32 0, i32 12, metadata !"t.c", metadata !".", metadata !"clang 2.0", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!4 = metadata !{i32 524309, metadata !26, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{null}
-!6 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ]
-!7 = metadata !{i32 524324, metadata !2, metadata !"unsigned char", metadata !2, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 524303, metadata !26, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ]
+!7 = metadata !{i32 524324, metadata !26, metadata !2, metadata !"unsigned char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ]
 !8 = metadata !{i32 524545, metadata !1, metadata !"nbytes", metadata !2, i32 4, metadata !9} ; [ DW_TAG_arg_variable ]
-!9 = metadata !{i32 524324, metadata !2, metadata !"unsigned long", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 524324, metadata !26, metadata !2, metadata !"unsigned long", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
 !10 = metadata !{i32 524544, metadata !11, metadata !"nread", metadata !2, i32 6, metadata !9} ; [ DW_TAG_auto_variable ]
-!11 = metadata !{i32 524299, metadata !1, i32 5, i32 1} ; [ DW_TAG_lexical_block ]
+!11 = metadata !{i32 524299, metadata !26, metadata !1, i32 5, i32 1, i32 0} ; [ DW_TAG_lexical_block ]
 !12 = metadata !{i32 524544, metadata !11, metadata !"c", metadata !2, i32 7, metadata !13} ; [ DW_TAG_auto_variable ]
-!13 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!13 = metadata !{i32 524324, metadata !26, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !14 = metadata !{i32 524340, i32 0, metadata !2, metadata !"length", metadata !"length", metadata !"length", metadata !2, i32 1, metadata !13, i1 false, i1 true, i32* @length} ; [ DW_TAG_variable ]
 !15 = metadata !{i32 4, i32 24, metadata !1, null}
 !16 = metadata !{i32 4, i32 43, metadata !1, null}
@@ -69,7 +69,8 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !19 = metadata !{i32 10, i32 2, metadata !11, null}
 !20 = metadata !{i32 11, i32 2, metadata !11, null}
 !21 = metadata !{i32 12, i32 3, metadata !22, null}
-!22 = metadata !{i32 524299, metadata !11, i32 11, i32 45} ; [ DW_TAG_lexical_block ]
+!22 = metadata !{i32 524299, metadata !26, metadata !11, i32 11, i32 45, i32 0} ; [ DW_TAG_lexical_block ]
 !23 = metadata !{i32 13, i32 3, metadata !22, null}
 !24 = metadata !{i32 14, i32 2, metadata !22, null}
 !25 = metadata !{i32 15, i32 1, metadata !11, null}
+!26 = metadata !{metadata !"t.c", metadata !"/private/tmp"}
diff --git a/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/test/CodeGen/ARM/2010-08-04-StackVariable.ll
index 112512f..f4ad4bc 100644
--- a/test/CodeGen/ARM/2010-08-04-StackVariable.ll
+++ b/test/CodeGen/ARM/2010-08-04-StackVariable.ll
@@ -76,47 +76,47 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!3}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", metadata !2, i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 786451, metadata !2, metadata !"SVal", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ]
+!0 = metadata !{i32 786478, metadata !48, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786451, metadata !48, null, metadata !"SVal", i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ]
 !2 = metadata !{i32 786473, metadata !48} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786449, i32 4, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !47, metadata !47, metadata !46, metadata !47,  metadata !47, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786449, metadata !48, i32 4, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !47, metadata !47, metadata !46, metadata !47,  metadata !47, metadata !""} ; [ DW_TAG_compile_unit ]
 !4 = metadata !{metadata !5, metadata !7, metadata !0, metadata !9}
-!5 = metadata !{i32 786445, metadata !1, metadata !"Data", metadata !2, i32 7, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ]
-!6 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
-!7 = metadata !{i32 786445, metadata !1, metadata !"Kind", metadata !2, i32 8, i64 32, i64 32, i64 64, i32 0, metadata !8} ; [ DW_TAG_member ]
-!8 = metadata !{i32 786468, metadata !2, metadata !"unsigned int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
-!9 = metadata !{i32 786478, metadata !1, metadata !"~SVal", metadata !"~SVal", metadata !"", metadata !2, i32 12, metadata !10, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!10 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!5 = metadata !{i32 786445, metadata !48, metadata !1, metadata !"Data", i32 7, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ]
+!6 = metadata !{i32 786447, metadata !48, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
+!7 = metadata !{i32 786445, metadata !48, metadata !1, metadata !"Kind", i32 8, i64 32, i64 32, i64 64, i32 0, metadata !8} ; [ DW_TAG_member ]
+!8 = metadata !{i32 786468, metadata !48, null, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 786478, metadata !48, metadata !1, metadata !"~SVal", metadata !"~SVal", metadata !"", i32 12, metadata !10, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!10 = metadata !{i32 786453, metadata !48, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !11 = metadata !{null, metadata !12, metadata !13}
-!12 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ]
-!13 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!14 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!12 = metadata !{i32 786447, metadata !48, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ]
+!13 = metadata !{i32 786468, metadata !48, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!14 = metadata !{i32 786453, metadata !48, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !15 = metadata !{null, metadata !12}
-!16 = metadata !{i32 786478, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"_ZN4SValC1Ev", metadata !2, i32 11, metadata !14, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void (%struct.SVal*)* @_ZN4SValC1Ev} ; [ DW_TAG_subprogram ]
-!17 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3fooi4SVal", metadata !2, i32 16, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal} ; [ DW_TAG_subprogram ]
-!18 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !19, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!16 = metadata !{i32 786478, metadata !48, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"_ZN4SValC1Ev", i32 11, metadata !14, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void (%struct.SVal*)* @_ZN4SValC1Ev, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!17 = metadata !{i32 786478, metadata !48, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3fooi4SVal", i32 16, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!18 = metadata !{i32 786453, metadata !48, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !19, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !19 = metadata !{metadata !13, metadata !13, metadata !1}
-!20 = metadata !{i32 786478, metadata !2, metadata !"main", metadata !"main", metadata !"main", metadata !2, i32 23, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ]
-!21 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!20 = metadata !{i32 786478, metadata !48, metadata !2, metadata !"main", metadata !"main", metadata !"main", i32 23, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!21 = metadata !{i32 786453, metadata !48, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !22 = metadata !{metadata !13}
 !23 = metadata !{i32 786689, metadata !17, metadata !"i", metadata !2, i32 16, metadata !13, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
 !24 = metadata !{i32 16, i32 0, metadata !17, null}
 !25 = metadata !{i32 786689, metadata !17, metadata !"location", metadata !2, i32 16, metadata !26, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
-!26 = metadata !{i32 786448, metadata !2, metadata !"SVal", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_reference_type ]
+!26 = metadata !{i32 786448, metadata !48, metadata !2, metadata !"SVal", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_reference_type ]
 !27 = metadata !{i32 17, i32 0, metadata !28, null}
 !28 = metadata !{i32 786443, metadata !2, metadata !17, i32 16, i32 0, i32 2} ; [ DW_TAG_lexical_block ]
 !29 = metadata !{i32 18, i32 0, metadata !28, null}
 !30 = metadata !{i32 20, i32 0, metadata !28, null}
 !31 = metadata !{i32 786689, metadata !16, metadata !"this", metadata !2, i32 11, metadata !32, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
-!32 = metadata !{i32 786470, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !33} ; [ DW_TAG_const_type ]
-!33 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_pointer_type ]
+!32 = metadata !{i32 786470, metadata !48, metadata !2, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 64, metadata !33} ; [ DW_TAG_const_type ]
+!33 = metadata !{i32 786447, metadata !48, metadata !2, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_pointer_type ]
 !34 = metadata !{i32 11, i32 0, metadata !16, null}
 !35 = metadata !{i32 11, i32 0, metadata !36, null}
-!36 = metadata !{i32 786443, metadata !2, metadata !37, i32 11, i32 0, i32 1} ; [ DW_TAG_lexical_block ]
-!37 = metadata !{i32 786443, metadata !2, metadata !16, i32 11, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!36 = metadata !{i32 786443, metadata !48, metadata !37, i32 11, i32 0, i32 1} ; [ DW_TAG_lexical_block ]
+!37 = metadata !{i32 786443, metadata !48, metadata !16, i32 11, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !38 = metadata !{i32 786688, metadata !39, metadata !"v", metadata !2, i32 24, metadata !1, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
-!39 = metadata !{i32 786443, metadata !2, metadata !40, i32 23, i32 0, i32 4} ; [ DW_TAG_lexical_block ]
-!40 = metadata !{i32 786443, metadata !2, metadata !20, i32 23, i32 0, i32 3} ; [ DW_TAG_lexical_block ]
+!39 = metadata !{i32 786443, metadata !48, metadata !40, i32 23, i32 0, i32 4} ; [ DW_TAG_lexical_block ]
+!40 = metadata !{i32 786443, metadata !48, metadata !20, i32 23, i32 0, i32 3} ; [ DW_TAG_lexical_block ]
 !41 = metadata !{i32 24, i32 0, metadata !39, null}
 !42 = metadata !{i32 25, i32 0, metadata !39, null}
 !43 = metadata !{i32 26, i32 0, metadata !39, null}
diff --git a/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll b/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll
index bda14bc..e6d1518 100644
--- a/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll
+++ b/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll
@@ -1,12 +1,31 @@
-; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
+; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=V7
+; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8
+; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi | FileCheck %s --check-prefix=Vt8
+; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+v8fp | FileCheck %s --check-prefix=V8-V8FP
+; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+neon | FileCheck %s --check-prefix=V8-NEON
 ; This tests that MC/asm header conversion is smooth
 ;
-; CHECK:      .syntax unified
-; CHECK: .eabi_attribute 20, 1
-; CHECK: .eabi_attribute 21, 1
-; CHECK: .eabi_attribute 23, 3
-; CHECK: .eabi_attribute 24, 1
-; CHECK: .eabi_attribute 25, 1
+; V7:      .syntax unified
+; V7: .eabi_attribute 6, 10
+; V7: .eabi_attribute 20, 1
+; V7: .eabi_attribute 21, 1
+; V7: .eabi_attribute 23, 3
+; V7: .eabi_attribute 24, 1
+; V7: .eabi_attribute 25, 1
+
+; V8:      .syntax unified
+; V8: .eabi_attribute 6, 14
+
+; Vt8:     .syntax unified
+; Vt8: .eabi_attribute 6, 14
+
+; V8-V8FP:      .syntax unified
+; V8-V8FP: .eabi_attribute 6, 14
+; V8-V8FP: .eabi_attribute 10, 7
+
+; V8-NEON:      .syntax unified
+; V8-NEON: .eabi_attribute 6, 14
+; V8-NEON: .eabi_attribute 12, 3
 
 define i32 @f(i64 %z) {
 	ret i32 0
diff --git a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll
index b253fef..d19adcc 100644
--- a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll
+++ b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll
@@ -15,15 +15,14 @@
 ; BASIC-NEXT:     ]
 ; BASIC-NEXT:     Address: 0x0
 ; BASIC-NEXT:     Offset: 0x3C
-; BASIC-NEXT:     Size: 34
+; BASIC-NEXT:     Size: 28
 ; BASIC-NEXT:     Link: 0
 ; BASIC-NEXT:     Info: 0
 ; BASIC-NEXT:     AddressAlignment: 1
 ; BASIC-NEXT:     EntrySize: 0
 ; BASIC-NEXT:     SectionData (
-; BASIC-NEXT:       0000: 41210000 00616561 62690001 17000000
-; BASIC-NEXT:       0010: 060A0741 08010902 14011501 17031801
-; BASIC-NEXT:       0020: 1901
+; BASIC-NEXT:       0000: 411B0000 00616561 62690001 11000000
+; BASIC-NEXT:       0010: 06011401 15011703 18011901
 ; BASIC-NEXT:     )
 
 ; CORTEXA8:        Name: .ARM.attributes
diff --git a/test/CodeGen/ARM/2010-11-29-PrologueBug.ll b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
index da4d157..4179d8c 100644
--- a/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
+++ b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll
@@ -4,7 +4,7 @@
 
 define i32* @t(i32* %x) nounwind {
 entry:
-; ARM: t:
+; ARM-LABEL: t:
 ; ARM: push
 ; ARM: mov r7, sp
 ; ARM: bl _foo
@@ -12,7 +12,7 @@ entry:
 ; ARM: bl _foo
 ; ARM: pop {r7, pc}
 
-; THUMB2: t:
+; THUMB2-LABEL: t:
 ; THUMB2: push
 ; THUMB2: mov r7, sp
 ; THUMB2: blx _foo
diff --git a/test/CodeGen/ARM/2010-12-07-PEIBug.ll b/test/CodeGen/ARM/2010-12-07-PEIBug.ll
index 4879f4e..eef6abd 100644
--- a/test/CodeGen/ARM/2010-12-07-PEIBug.ll
+++ b/test/CodeGen/ARM/2010-12-07-PEIBug.ll
@@ -3,7 +3,7 @@
 
 define hidden void @foo() nounwind ssp {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: mov r7, sp
 ; CHECK-NEXT: vpush {d8}
 ; CHECK-NEXT: vpush {d10, d11}
diff --git a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll
index 98c0af3..626d121 100644
--- a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll
+++ b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll
@@ -77,19 +77,19 @@ entry:
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"get1", metadata !"get1", metadata !"get1", metadata !1, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get1, null, null, metadata !42, i32 4} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !47, metadata !1, metadata !"get1", metadata !"get1", metadata !"get1", i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get1, null, null, metadata !42, i32 4} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !47} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, metadata !47, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41,  metadata !41, metadata !""} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 786449, metadata !47, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", i1 true, metadata !"", i32 0, metadata !48, metadata !48, metadata !40, metadata !41,  metadata !41, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !47, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5, metadata !5}
-!5 = metadata !{i32 786468, metadata !1, metadata !1, metadata !"_Bool", i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 786478, metadata !1, metadata !"get2", metadata !"get2", metadata !"get2", metadata !1, i32 7, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get2, null, null, metadata !43, i32 7} ; [ DW_TAG_subprogram ]
-!7 = metadata !{i32 786478, metadata !1, metadata !"get3", metadata !"get3", metadata !"get3", metadata !1, i32 10, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get3, null, null, metadata !44, i32 10} ; [ DW_TAG_subprogram ]
-!8 = metadata !{i32 786478, metadata !1, metadata !"get4", metadata !"get4", metadata !"get4", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get4, null, null, metadata !45, i32 13} ; [ DW_TAG_subprogram ]
-!9 = metadata !{i32 786478, metadata !1, metadata !"get5", metadata !"get5", metadata !"get5", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get5, null, null, metadata !46, i32 16} ; [ DW_TAG_subprogram ]
+!5 = metadata !{i32 786468, metadata !47, metadata !1, metadata !"_Bool", i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786478, metadata !47, metadata !1, metadata !"get2", metadata !"get2", metadata !"get2", i32 7, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get2, null, null, metadata !43, i32 7} ; [ DW_TAG_subprogram ]
+!7 = metadata !{i32 786478, metadata !47, metadata !1, metadata !"get3", metadata !"get3", metadata !"get3", i32 10, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get3, null, null, metadata !44, i32 10} ; [ DW_TAG_subprogram ]
+!8 = metadata !{i32 786478, metadata !47, metadata !1, metadata !"get4", metadata !"get4", metadata !"get4", i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get4, null, null, metadata !45, i32 13} ; [ DW_TAG_subprogram ]
+!9 = metadata !{i32 786478, metadata !47, metadata !1, metadata !"get5", metadata !"get5", metadata !"get5", i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get5, null, null, metadata !46, i32 16} ; [ DW_TAG_subprogram ]
 !10 = metadata !{i32 786689, metadata !0, metadata !"a", metadata !1, i32 4, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !11 = metadata !{i32 786688, metadata !12, metadata !"b", metadata !1, i32 4, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!12 = metadata !{i32 786443, metadata !0, i32 4, i32 0, metadata !1, i32 0} ; [ DW_TAG_lexical_block ]
+!12 = metadata !{i32 786443, metadata !47, metadata !0, i32 4, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !13 = metadata !{i32 786484, i32 0, metadata !1, metadata !"x1", metadata !"x1", metadata !"", metadata !1, i32 3, metadata !5, i1 true, i1 true, i8* @x1, null} ; [ DW_TAG_variable ]
 !14 = metadata !{i32 786484, i32 0, metadata !1, metadata !"x2", metadata !"x2", metadata !"", metadata !1, i32 6, metadata !5, i1 true, i1 true, i8* @x2, null} ; [ DW_TAG_variable ]
 !15 = metadata !{i32 786484, i32 0, metadata !1, metadata !"x3", metadata !"x3", metadata !"", metadata !1, i32 9, metadata !5, i1 true, i1 true, i8* @x3, null} ; [ DW_TAG_variable ]
@@ -97,16 +97,16 @@ entry:
 !17 = metadata !{i32 786484, i32 0, metadata !1, metadata !"x5", metadata !"x5", metadata !"", metadata !1, i32 15, metadata !5, i1 false, i1 true, i8* @x5, null} ; [ DW_TAG_variable ]
 !18 = metadata !{i32 786689, metadata !6, metadata !"a", metadata !1, i32 7, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !19 = metadata !{i32 786688, metadata !20, metadata !"b", metadata !1, i32 7, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!20 = metadata !{i32 786443, metadata !6, i32 7, i32 0, metadata !1, i32 1} ; [ DW_TAG_lexical_block ]
+!20 = metadata !{i32 786443, metadata !47, metadata !6, i32 7, i32 0, i32 1} ; [ DW_TAG_lexical_block ]
 !21 = metadata !{i32 786689, metadata !7, metadata !"a", metadata !1, i32 10, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !22 = metadata !{i32 786688, metadata !23, metadata !"b", metadata !1, i32 10, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!23 = metadata !{i32 786443, metadata !7, i32 10, i32 0, metadata !1, i32 2} ; [ DW_TAG_lexical_block ]
+!23 = metadata !{i32 786443, metadata !47, metadata !7, i32 10, i32 0, i32 2} ; [ DW_TAG_lexical_block ]
 !24 = metadata !{i32 786689, metadata !8, metadata !"a", metadata !1, i32 13, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !25 = metadata !{i32 786688, metadata !26, metadata !"b", metadata !1, i32 13, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!26 = metadata !{i32 786443, metadata !8, i32 13, i32 0, metadata !1, i32 3} ; [ DW_TAG_lexical_block ]
+!26 = metadata !{i32 786443, metadata !47, metadata !8, i32 13, i32 0, i32 3} ; [ DW_TAG_lexical_block ]
 !27 = metadata !{i32 786689, metadata !9, metadata !"a", metadata !1, i32 16, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !28 = metadata !{i32 786688, metadata !29, metadata !"b", metadata !1, i32 16, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!29 = metadata !{i32 786443, metadata !9, i32 16, i32 0, metadata !1, i32 4} ; [ DW_TAG_lexical_block ]
+!29 = metadata !{i32 786443, metadata !47, metadata !9, i32 16, i32 0, i32 4} ; [ DW_TAG_lexical_block ]
 !30 = metadata !{i32 4, i32 0, metadata !0, null}
 !31 = metadata !{i32 4, i32 0, metadata !12, null}
 !32 = metadata !{i32 7, i32 0, metadata !6, null}
@@ -125,3 +125,4 @@ entry:
 !45 = metadata !{metadata !24, metadata !25}
 !46 = metadata !{metadata !27, metadata !28}
 !47 = metadata !{metadata !"foo.c", metadata !"/tmp/"}
+!48 = metadata !{i32 0}
diff --git a/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
index e84ce0e..f689d49 100644
--- a/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
+++ b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll
@@ -9,7 +9,7 @@
 @oStruct = external global %struct.Outer, align 4
 
 define void @main() nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK-NOT: ldrd
 ; CHECK: mul
 for.body.lr.ph:
diff --git a/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll b/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
index 0fe88bd..caa0be5 100644
--- a/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
+++ b/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
@@ -8,7 +8,7 @@
 ; rdar://9172742
 
 define i32 @t() nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 entry:
   br label %bb2
 
diff --git a/test/CodeGen/ARM/2011-04-07-schediv.ll b/test/CodeGen/ARM/2011-04-07-schediv.ll
index 19f756f..f3dd3dd 100644
--- a/test/CodeGen/ARM/2011-04-07-schediv.ll
+++ b/test/CodeGen/ARM/2011-04-07-schediv.ll
@@ -12,7 +12,7 @@ entry:
 
 ; Make sure the scheduler schedules all uses of the preincrement
 ; induction variable before defining the postincrement value.
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: %bb
 ; CHECK-NOT: mov
 bb:                                               ; preds = %entry, %bb
diff --git a/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll
index 568718c..348ec9f 100644
--- a/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll
+++ b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll
@@ -4,7 +4,7 @@
 ; rdar://9266679
 
 define zeroext i1 @t(i32* nocapture %A, i32 %size, i32 %value) nounwind readonly ssp {
-; CHECK: t:
+; CHECK-LABEL: t:
 entry:
   br label %for.cond
 
diff --git a/test/CodeGen/ARM/2011-04-26-SchedTweak.ll b/test/CodeGen/ARM/2011-04-26-SchedTweak.ll
index ed7dd03..057c199 100644
--- a/test/CodeGen/ARM/2011-04-26-SchedTweak.ll
+++ b/test/CodeGen/ARM/2011-04-26-SchedTweak.ll
@@ -15,7 +15,7 @@
 
 define i32 @test() nounwind optsize ssp {
 entry:
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: push
 ; CHECK-NOT: push
   %block_size = alloca i32, align 4
diff --git a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll
index 7a7ca8e..33826f8 100644
--- a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll
+++ b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll
@@ -74,28 +74,28 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, metadata !47, i32 12, metadata !"clang", i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41,  metadata !41, null} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"get1", metadata !"get1", metadata !"", metadata !2, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get1, null, null, metadata !42, i32 5} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786449, metadata !47, i32 12, metadata !"clang", i1 true, metadata !"", i32 0, metadata !48, metadata !48, metadata !40, metadata !41,  metadata !41, null} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"get1", metadata !"get1", metadata !"", i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get1, null, null, metadata !42, i32 5} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !47} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786453, metadata !2, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!3 = metadata !{i32 786453, metadata !47, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
 !5 = metadata !{i32 786468, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 786478, metadata !2, metadata !"get2", metadata !"get2", metadata !"", metadata !2, i32 8, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get2, null, null, metadata !43, i32 8} ; [ DW_TAG_subprogram ]
-!7 = metadata !{i32 786478, metadata !2, metadata !"get3", metadata !"get3", metadata !"", metadata !2, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get3, null, null, metadata !44, i32 11} ; [ DW_TAG_subprogram ]
-!8 = metadata !{i32 786478, metadata !2, metadata !"get4", metadata !"get4", metadata !"", metadata !2, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get4, null, null, metadata !45, i32 14} ; [ DW_TAG_subprogram ]
-!9 = metadata !{i32 786478, metadata !2, metadata !"get5", metadata !"get5", metadata !"", metadata !2, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get5, null, null, metadata !46, i32 17} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"get2", metadata !"get2", metadata !"", i32 8, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get2, null, null, metadata !43, i32 8} ; [ DW_TAG_subprogram ]
+!7 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"get3", metadata !"get3", metadata !"", i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get3, null, null, metadata !44, i32 11} ; [ DW_TAG_subprogram ]
+!8 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"get4", metadata !"get4", metadata !"", i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get4, null, null, metadata !45, i32 14} ; [ DW_TAG_subprogram ]
+!9 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"get5", metadata !"get5", metadata !"", i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get5, null, null, metadata !46, i32 17} ; [ DW_TAG_subprogram ]
 !10 = metadata !{i32 786689, metadata !1, metadata !"a", metadata !2, i32 16777221, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !11 = metadata !{i32 786688, metadata !12, metadata !"b", metadata !2, i32 5, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!12 = metadata !{i32 786443, metadata !1, i32 5, i32 19, metadata !2, i32 0} ; [ DW_TAG_lexical_block ]
+!12 = metadata !{i32 786443, metadata !47, metadata !1, i32 5, i32 19, i32 0} ; [ DW_TAG_lexical_block ]
 !13 = metadata !{i32 786689, metadata !6, metadata !"a", metadata !2, i32 16777224, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !14 = metadata !{i32 786688, metadata !15, metadata !"b", metadata !2, i32 8, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!15 = metadata !{i32 786443, metadata !6, i32 8, i32 17, metadata !2, i32 1} ; [ DW_TAG_lexical_block ]
+!15 = metadata !{i32 786443, metadata !47, metadata !6, i32 8, i32 17, i32 1} ; [ DW_TAG_lexical_block ]
 !16 = metadata !{i32 786689, metadata !7, metadata !"a", metadata !2, i32 16777227, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !17 = metadata !{i32 786688, metadata !18, metadata !"b", metadata !2, i32 11, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!18 = metadata !{i32 786443, metadata !7, i32 11, i32 19, metadata !2, i32 2} ; [ DW_TAG_lexical_block ]
+!18 = metadata !{i32 786443, metadata !47, metadata !7, i32 11, i32 19, i32 2} ; [ DW_TAG_lexical_block ]
 !19 = metadata !{i32 786689, metadata !8, metadata !"a", metadata !2, i32 16777230, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !20 = metadata !{i32 786688, metadata !21, metadata !"b", metadata !2, i32 14, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!21 = metadata !{i32 786443, metadata !8, i32 14, i32 19, metadata !2, i32 3} ; [ DW_TAG_lexical_block ]
+!21 = metadata !{i32 786443, metadata !47, metadata !8, i32 14, i32 19, i32 3} ; [ DW_TAG_lexical_block ]
 !22 = metadata !{i32 786484, i32 0, metadata !0, metadata !"x5", metadata !"x5", metadata !"", metadata !2, i32 16, metadata !5, i32 0, i32 1, i32* @x5, null} ; [ DW_TAG_variable ]
 !23 = metadata !{i32 786484, i32 0, metadata !0, metadata !"x4", metadata !"x4", metadata !"", metadata !2, i32 13, metadata !5, i32 1, i32 1, i32* @x4, null} ; [ DW_TAG_variable ]
 !24 = metadata !{i32 786484, i32 0, metadata !0, metadata !"x3", metadata !"x3", metadata !"", metadata !2, i32 10, metadata !5, i32 1, i32 1, i32* @x3, null} ; [ DW_TAG_variable ]
@@ -103,7 +103,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !26 = metadata !{i32 786484, i32 0, metadata !0, metadata !"x1", metadata !"x1", metadata !"", metadata !2, i32 4, metadata !5, i32 1, i32 1, i32* @x1, null} ; [ DW_TAG_variable ]
 !27 = metadata !{i32 786689, metadata !9, metadata !"a", metadata !2, i32 16777233, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !28 = metadata !{i32 786688, metadata !29, metadata !"b", metadata !2, i32 17, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!29 = metadata !{i32 786443, metadata !9, i32 17, i32 19, metadata !2, i32 4} ; [ DW_TAG_lexical_block ]
+!29 = metadata !{i32 786443, metadata !47, metadata !9, i32 17, i32 19, i32 4} ; [ DW_TAG_lexical_block ]
 !30 = metadata !{i32 5, i32 16, metadata !1, null}
 !31 = metadata !{i32 5, i32 32, metadata !12, null}
 !32 = metadata !{i32 8, i32 14, metadata !6, null}
@@ -122,3 +122,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !45 = metadata !{metadata !19, metadata !20}
 !46 = metadata !{metadata !27, metadata !28}
 !47 = metadata !{metadata !"ss3.c", metadata !"/private/tmp"}
+!48 = metadata !{i32 0}
diff --git a/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll b/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
index 113cbfe..8a65f2e 100644
--- a/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
+++ b/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
@@ -6,7 +6,7 @@
 @i8_src2 = global <2 x i8> <i8 2, i8 1>
 
 define void @test_neon_vector_add_2xi8() nounwind {
-; CHECK: test_neon_vector_add_2xi8:
+; CHECK-LABEL: test_neon_vector_add_2xi8:
   %1 = load <2 x i8>* @i8_src1
   %2 = load <2 x i8>* @i8_src2
   %3 = add <2 x i8> %1, %2
@@ -15,7 +15,7 @@ define void @test_neon_vector_add_2xi8() nounwind {
 }
 
 define void @test_neon_ld_st_volatile_with_ashr_2xi8() {
-; CHECK: test_neon_ld_st_volatile_with_ashr_2xi8:
+; CHECK-LABEL: test_neon_ld_st_volatile_with_ashr_2xi8:
   %1 = load volatile <2 x i8>* @i8_src1
   %2 = load volatile <2 x i8>* @i8_src2
   %3 = ashr <2 x i8> %1, %2
diff --git a/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll b/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll
index 2ab6a4f..42eb32d 100644
--- a/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll
+++ b/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll
@@ -7,7 +7,7 @@
 declare <2 x i16> @foo_v2i16(<2 x i16>) nounwind
 
 define void @test_neon_call_return_v2i16() {
-; CHECK: test_neon_call_return_v2i16:
+; CHECK-LABEL: test_neon_call_return_v2i16:
   %1 = load <2 x i16>* @src1_v2i16
   %2 = call <2 x i16> @foo_v2i16(<2 x i16> %1) nounwind
   store <2 x i16> %2, <2 x i16>* @res_v2i16
diff --git a/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll b/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll
index 5409f8c..bc496b9 100644
--- a/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll
+++ b/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll
@@ -10,7 +10,7 @@
 @infoBlock = external global %struct.InformationBlock
 
 define hidden void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: ldr.w
 ; CHECK: ldr.w
 ; CHECK-NOT: ldm
diff --git a/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
index 0d0d03b..a263c9c 100644
--- a/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
+++ b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
@@ -4,7 +4,7 @@
 
 define void @test_sqrt(<4 x float>* %X) nounwind {
 
-; CHECK: test_sqrt:
+; CHECK-LABEL: test_sqrt:
 
 ; CHECK:      movw    r1, :lower16:{{.*}}
 ; CHECK:      movt    r1, :upper16:{{.*}}
@@ -27,7 +27,7 @@ declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly
 
 define void @test_cos(<4 x float>* %X) nounwind {
 
-; CHECK: test_cos:
+; CHECK-LABEL: test_cos:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -58,7 +58,7 @@ declare <4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly
 
 define void @test_exp(<4 x float>* %X) nounwind {
 
-; CHECK: test_exp:
+; CHECK-LABEL: test_exp:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -89,7 +89,7 @@ declare <4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly
 
 define void @test_exp2(<4 x float>* %X) nounwind {
 
-; CHECK: test_exp2:
+; CHECK-LABEL: test_exp2:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -120,7 +120,7 @@ declare <4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly
 
 define void @test_log10(<4 x float>* %X) nounwind {
 
-; CHECK: test_log10:
+; CHECK-LABEL: test_log10:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -151,7 +151,7 @@ declare <4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonly
 
 define void @test_log(<4 x float>* %X) nounwind {
 
-; CHECK: test_log:
+; CHECK-LABEL: test_log:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -182,7 +182,7 @@ declare <4 x float> @llvm.log.v4f32(<4 x float>) nounwind readonly
 
 define void @test_log2(<4 x float>* %X) nounwind {
 
-; CHECK: test_log2:
+; CHECK-LABEL: test_log2:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -214,7 +214,7 @@ declare <4 x float> @llvm.log2.v4f32(<4 x float>) nounwind readonly
 
 define void @test_pow(<4 x float>* %X) nounwind {
 
-; CHECK: test_pow:
+; CHECK-LABEL: test_pow:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -248,7 +248,7 @@ declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) nounwind readonly
 
 define void @test_powi(<4 x float>* %X) nounwind {
 
-; CHECK: test_powi:
+; CHECK-LABEL: test_powi:
 
 ; CHECK:       movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:       movt  [[reg0]], :upper16:{{.*}}
@@ -271,7 +271,7 @@ declare <4 x float> @llvm.powi.v4f32(<4 x float>, i32) nounwind readonly
 
 define void @test_sin(<4 x float>* %X) nounwind {
 
-; CHECK: test_sin:
+; CHECK-LABEL: test_sin:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -302,7 +302,7 @@ declare <4 x float> @llvm.sin.v4f32(<4 x float>) nounwind readonly
 
 define void @test_floor(<4 x float>* %X) nounwind {
 
-; CHECK: test_floor:
+; CHECK-LABEL: test_floor:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
diff --git a/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll b/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll
index 0ff4f51..e795ec5 100644
--- a/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll
+++ b/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll
@@ -23,7 +23,7 @@
 ;
 ; rdar://11116189
 define i64 @t(i64 %aInput) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movs [[REG:(r[0-9]+)]], #0
 ; CHECK: movt [[REG]], #46540
 ; CHECK: adds r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
diff --git a/test/CodeGen/ARM/2012-05-04-vmov.ll b/test/CodeGen/ARM/2012-05-04-vmov.ll
index d52ef2c..14dbf7f 100644
--- a/test/CodeGen/ARM/2012-05-04-vmov.ll
+++ b/test/CodeGen/ARM/2012-05-04-vmov.ll
@@ -7,5 +7,8 @@ entry:
   %div = udiv <2 x i32> %A, %B
   ret <2 x i32> %div
 ; A9-CHECK: vmov.32
-; SWIFT-CHECK-NOT: vmov.32
+; vmov.32 should not be used to get a lane:
+; vmov.32 <dst>, <src>[<lane>].
+; but vmov.32 <dst>[<lane>], <src> is fine.
+; SWIFT-CHECK-NOT: vmov.32 {{r[0-9]+}}, {{d[0-9]\[[0-9]+\]}}
 }
diff --git a/test/CodeGen/ARM/2012-08-09-neon-extload.ll b/test/CodeGen/ARM/2012-08-09-neon-extload.ll
index 764c58f..a710825 100644
--- a/test/CodeGen/ARM/2012-08-09-neon-extload.ll
+++ b/test/CodeGen/ARM/2012-08-09-neon-extload.ll
@@ -12,7 +12,7 @@
 @var_v2i64 = global <2 x i64> zeroinitializer
 
 define void @test_v2i8tov2i32() {
-; CHECK: test_v2i8tov2i32:
+; CHECK-LABEL: test_v2i8tov2i32:
 
   %i8val = load <2 x i8>* @var_v2i8
 
@@ -26,7 +26,7 @@ define void @test_v2i8tov2i32() {
 }
 
 define void @test_v2i8tov2i64() {
-; CHECK: test_v2i8tov2i64:
+; CHECK-LABEL: test_v2i8tov2i64:
 
   %i8val = load <2 x i8>* @var_v2i8
 
@@ -44,7 +44,7 @@ define void @test_v2i8tov2i64() {
 }
 
 define void @test_v4i8tov4i16() {
-; CHECK: test_v4i8tov4i16:
+; CHECK-LABEL: test_v4i8tov4i16:
 
   %i8val = load <4 x i8>* @var_v4i8
 
@@ -59,7 +59,7 @@ define void @test_v4i8tov4i16() {
 }
 
 define void @test_v4i8tov4i32() {
-; CHECK: test_v4i8tov4i32:
+; CHECK-LABEL: test_v4i8tov4i32:
 
   %i8val = load <4 x i8>* @var_v4i8
 
@@ -73,7 +73,7 @@ define void @test_v4i8tov4i32() {
 }
 
 define void @test_v2i16tov2i32() {
-; CHECK: test_v2i16tov2i32:
+; CHECK-LABEL: test_v2i16tov2i32:
 
   %i16val = load <2 x i16>* @var_v2i16
 
@@ -88,7 +88,7 @@ define void @test_v2i16tov2i32() {
 }
 
 define void @test_v2i16tov2i64() {
-; CHECK: test_v2i16tov2i64:
+; CHECK-LABEL: test_v2i16tov2i64:
 
   %i16val = load <2 x i16>* @var_v2i16
 
diff --git a/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll b/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
index 2f55204..647ebd6 100644
--- a/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
+++ b/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll
@@ -13,7 +13,7 @@
 ; v4i8
 ;
 define void @sextload_v4i8_c(<4 x i8>* %v) nounwind {
-;CHECK: sextload_v4i8_c:
+;CHECK-LABEL: sextload_v4i8_c:
 entry:
   %0 = load <4 x i8>* %v, align 8
   %v0  = sext <4 x i8> %0 to <4 x i32>
@@ -26,7 +26,7 @@ entry:
 ; v2i8
 ;
 define void @sextload_v2i8_c(<2 x i8>* %v) nounwind {
-;CHECK: sextload_v2i8_c:
+;CHECK-LABEL: sextload_v2i8_c:
 entry:
   %0   = load <2 x i8>* %v, align 8
   %v0  = sext <2 x i8>  %0 to <2 x i64>
@@ -39,7 +39,7 @@ entry:
 ; v2i16
 ;
 define void @sextload_v2i16_c(<2 x i16>* %v) nounwind {
-;CHECK: sextload_v2i16_c:
+;CHECK-LABEL: sextload_v2i16_c:
 entry:
   %0   = load <2 x i16>* %v, align 8
   %v0  = sext <2 x i16>  %0 to <2 x i64>
@@ -54,7 +54,7 @@ entry:
 ; v4i8
 ;
 define void @sextload_v4i8_v(<4 x i8>* %v, <4 x i8>* %p) nounwind {
-;CHECK: sextload_v4i8_v:
+;CHECK-LABEL: sextload_v4i8_v:
 entry:
   %0 = load <4 x i8>* %v, align 8
   %v0  = sext <4 x i8> %0 to <4 x i32>
@@ -70,7 +70,7 @@ entry:
 ; v2i8
 ;
 define void @sextload_v2i8_v(<2 x i8>* %v, <2 x i8>* %p) nounwind {
-;CHECK: sextload_v2i8_v:
+;CHECK-LABEL: sextload_v2i8_v:
 entry:
   %0 = load <2 x i8>* %v, align 8
   %v0  = sext <2 x i8> %0 to <2 x i64>
@@ -86,7 +86,7 @@ entry:
 ; v2i16
 ;
 define void @sextload_v2i16_v(<2 x i16>* %v, <2 x i16>* %p) nounwind {
-;CHECK: sextload_v2i16_v:
+;CHECK-LABEL: sextload_v2i16_v:
 entry:
   %0 = load <2 x i16>* %v, align 8
   %v0  = sext <2 x i16> %0 to <2 x i64>
@@ -104,7 +104,7 @@ entry:
 ; v4i8 x v4i16
 ;
 define void @sextload_v4i8_vs(<4 x i8>* %v, <4 x i16>* %p) nounwind {
-;CHECK: sextload_v4i8_vs:
+;CHECK-LABEL: sextload_v4i8_vs:
 entry:
   %0 = load <4 x i8>* %v, align 8
   %v0  = sext <4 x i8> %0 to <4 x i32>
@@ -120,7 +120,7 @@ entry:
 ; v2i8
 ; v2i8 x v2i16
 define void @sextload_v2i8_vs(<2 x i8>* %v, <2 x i16>* %p) nounwind {
-;CHECK: sextload_v2i8_vs:
+;CHECK-LABEL: sextload_v2i8_vs:
 entry:
   %0 = load <2 x i8>* %v, align 8
   %v0  = sext <2 x i8> %0 to <2 x i64>
@@ -136,7 +136,7 @@ entry:
 ; v2i16
 ; v2i16 x v2i32
 define void @sextload_v2i16_vs(<2 x i16>* %v, <2 x i32>* %p) nounwind {
-;CHECK: sextload_v2i16_vs:
+;CHECK-LABEL: sextload_v2i16_vs:
 entry:
   %0 = load <2 x i16>* %v, align 8
   %v0  = sext <2 x i16> %0 to <2 x i64>
diff --git a/test/CodeGen/ARM/2012-08-30-select.ll b/test/CodeGen/ARM/2012-08-30-select.ll
index 8471be5..2fd8df4 100644
--- a/test/CodeGen/ARM/2012-08-30-select.ll
+++ b/test/CodeGen/ARM/2012-08-30-select.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
 ; rdar://12201387
 
-;CHECK: select_s_v_v
+;CHECK-LABEL: select_s_v_v:
 ;CHECK: it  ne
 ;CHECK-NEXT: vmovne.i32
 ;CHECK: bx
diff --git a/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll b/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll
index e761ffe..3bdbb3c 100644
--- a/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll
+++ b/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll
@@ -4,7 +4,7 @@
 ; rdar://12300648
 
 define i32 @t(i32 %x) {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK-NOT: movw
   %tmp = add i32 %x, -65535
   ret i32 %tmp
diff --git a/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll b/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll
index 7576609..38624e0 100644
--- a/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll
+++ b/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mcpu=cortex-a8 2>&1 | FileCheck %s
+; RUN: not llc < %s -march=arm -mcpu=cortex-a8 2>&1 | FileCheck %s
 
 ; Check for error message:
 ; CHECK: non-trivial scalar-to-vector conversion, possible invalid constraint for vector type
diff --git a/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll b/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll
index 6fa1391..7ba693d 100644
--- a/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll
+++ b/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mcpu=cortex-a8 2>&1 | FileCheck %s
+; RUN: not llc < %s -march=arm -mcpu=cortex-a8 2>&1 | FileCheck %s
 
 ; Check for error message:
 ; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type
diff --git a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
index b0644d1..f864c8c 100644
--- a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
+++ b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
@@ -7,7 +7,7 @@
 declare void @llvm.va_start(i8*) nounwind
 declare void @llvm.va_end(i8*) nounwind
 
-; CHECK: test_byval_8_bytes_alignment:
+; CHECK-LABEL: test_byval_8_bytes_alignment:
 define void @test_byval_8_bytes_alignment(i32 %i, ...) {
 entry:
 ; CHECK: stm     r0, {r1, r2, r3}
@@ -23,8 +23,12 @@ entry:
   ret void
 }
 
-; CHECK: main:
-; CHECK: ldm     r0, {r2, r3}
+; CHECK-LABEL: main:
+; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
+; CHECK: movt [[BASE]], :upper16:static_val
+; ldm is not formed when the coalescer failed to coalesce everything.
+; CHECK: ldrd    r2, [[TMP:r[0-9]+]], {{\[}}[[BASE]]{{\]}}
+; CHECK: movw r0, #555
 define i32 @main() {
 entry:
   call void (i32, ...)* @test_byval_8_bytes_alignment(i32 555, %struct_t* byval @static_val)
@@ -33,7 +37,7 @@ entry:
 
 declare void @f(double);
 
-; CHECK:     test_byval_8_bytes_alignment_fixed_arg:
+; CHECK-LABEL:     test_byval_8_bytes_alignment_fixed_arg:
 ; CHECK-NOT:   str     r1
 ; CHECK:       str     r3, [sp, #12]
 ; CHECK:       str     r2, [sp, #8]
@@ -46,11 +50,14 @@ entry:
   ret void
 }
 
-; CHECK: main_fixed_arg:
-; CHECK: ldm     r0, {r2, r3}
+; CHECK-LABEL: main_fixed_arg:
+; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
+; CHECK: movt [[BASE]], :upper16:static_val
+; ldm is not formed when the coalescer failed to coalesce everything.
+; CHECK: ldrd     r2, [[TMP:r[0-9]+]], {{\[}}[[BASE]]{{\]}}
+; CHECK: movw r0, #555
 define i32 @main_fixed_arg() {
 entry:
   call void (i32, %struct_t*)* @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval @static_val)
   ret i32 0
 }
-
diff --git a/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll b/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
index 478048d..c9ccc10 100644
--- a/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
+++ b/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
@@ -6,7 +6,7 @@
 
 declare i32 @printf(i8*, ...)
 
-; CHECK:     test_byval_usage_scheduling:
+; CHECK-LABEL:     test_byval_usage_scheduling:
 ; CHECK:       str     r3, [sp, #12]
 ; CHECK:       str     r2, [sp, #8]
 ; CHECK:       vldr    d16, [sp, #8]
diff --git a/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll b/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll
index f239510..a59533c 100644
--- a/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll
+++ b/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll
@@ -6,7 +6,7 @@
 
 declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval %val);
 
-; CHECK: main:
+; CHECK-LABEL: main:
 define i32 @main() nounwind {
 entry:
 ; CHECK: ldrb	{{(r[0-9]+)}}, {{(\[r[0-9]+\])}}, #1
diff --git a/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll b/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
index fcc6a7f..0028eec 100644
--- a/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
+++ b/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
@@ -5,7 +5,7 @@
 
 declare void @f(%struct.s* %p);
 
-; CHECK: t:
+; CHECK-LABEL: t:
 define void @t(i32 %a, %struct.s* byval %s) nounwind {
 entry:
 
@@ -20,7 +20,7 @@ entry:
   ret void
 }
 
-; CHECK: caller:
+; CHECK-LABEL: caller:
 define void @caller() {
 
 ; CHECK:      ldm     r0, {r1, r2, r3}
diff --git a/test/CodeGen/ARM/2012-11-14-subs_carry.ll b/test/CodeGen/ARM/2012-11-14-subs_carry.ll
index 38700f3..8df295a 100644
--- a/test/CodeGen/ARM/2012-11-14-subs_carry.ll
+++ b/test/CodeGen/ARM/2012-11-14-subs_carry.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
 
-;CHECK: foo
+;CHECK-LABEL: foo:
 ;CHECK: adds
 ;CHECK-NEXT: adc
 ;CHECK-NEXT: bx
diff --git a/test/CodeGen/ARM/2013-01-21-PR14992.ll b/test/CodeGen/ARM/2013-01-21-PR14992.ll
index 05abded..014686f 100644
--- a/test/CodeGen/ARM/2013-01-21-PR14992.ll
+++ b/test/CodeGen/ARM/2013-01-21-PR14992.ll
@@ -2,8 +2,8 @@
 ;RUN: llc -mtriple=thumbv7 < %s  | FileCheck -check-prefix=EXPECTED %s
 ;RUN: llc -mtriple=thumbv7 < %s  | FileCheck %s
 
-;EXPECTED: foo:
-;CHECK: foo:
+;EXPECTED-LABEL: foo:
+;CHECK-LABEL: foo:
 define i32 @foo(i32* %a) nounwind optsize {
 entry:
   %0 = load i32* %a, align 4
diff --git a/test/CodeGen/ARM/2013-02-27-expand-vfma.ll b/test/CodeGen/ARM/2013-02-27-expand-vfma.ll
index 0e3bf23..135b144 100644
--- a/test/CodeGen/ARM/2013-02-27-expand-vfma.ll
+++ b/test/CodeGen/ARM/2013-02-27-expand-vfma.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -mtriple=armv7s-apple-darwin | FileCheck %s -check-prefix=VFP4
 
 define <4 x float> @muladd(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind {
-; CHECK: muladd:
+; CHECK-LABEL: muladd:
 ; CHECK: fmaf
 ; CHECK: fmaf
 ; CHECK: fmaf
@@ -17,7 +17,7 @@ define <4 x float> @muladd(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounw
 declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
 
 define <2 x float> @muladd2(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind {
-; CHECK: muladd2:
+; CHECK-LABEL: muladd2:
 ; CHECK: fmaf
 ; CHECK: fmaf
 ; CHECK-NOT: fmaf
diff --git a/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
index 80b9d28..127429b 100644
--- a/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
+++ b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll
@@ -1,7 +1,7 @@
 ;PR15293: ARM codegen ice - expected larger existing stack allocation
 ;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
 
-;CHECK: foo:
+;CHECK-LABEL: foo:
 ;CHECK: 	sub	sp, sp, #8
 ;CHECK: 	push	{r11, lr}
 ;CHECK: 	str	r0, [sp, #8]
@@ -11,7 +11,7 @@
 ;CHECK: 	add	sp, sp, #8
 ;CHECK: 	mov	pc, lr
 
-;CHECK: foo2:
+;CHECK-LABEL: foo2:
 ;CHECK: 	sub	sp, sp, #8
 ;CHECK: 	push	{r11, lr}
 ;CHECK: 	str	r0, [sp, #8]
@@ -24,7 +24,7 @@
 ;CHECK: 	add	sp, sp, #8
 ;CHECK: 	mov	pc, lr
 
-;CHECK: doFoo:
+;CHECK-LABEL: doFoo:
 ;CHECK: 	push	{r11, lr}
 ;CHECK: 	ldr	r0,
 ;CHECK: 	ldr	r0, [r0]
@@ -33,7 +33,7 @@
 ;CHECK: 	mov	pc, lr
 
 
-;CHECK: doFoo2:
+;CHECK-LABEL: doFoo2:
 ;CHECK: 	push	{r11, lr}
 ;CHECK: 	ldr	r0,
 ;CHECK: 	mov	r1, #0
diff --git a/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll b/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll
index 38d515f..08bf99b 100644
--- a/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll
+++ b/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll
@@ -53,11 +53,11 @@
 
 ;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s
 ;
-;CHECK:     foo:
+;CHECK-LABEL:     foo:
 ;CHECK-NOT:     mov r0
 ;CHECK-NOT:     ldr r0
 ;CHECK:         bl fooUseI32
-;CHECK:     doFoo:
+;CHECK-LABEL:     doFoo:
 ;CHECK:         movs    r0, #43
 ;CHECK:         bl      foo
 
diff --git a/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll b/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll
index de5fd31..0e0537e 100644
--- a/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll
+++ b/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll
@@ -9,7 +9,7 @@
 
 @.str = private unnamed_addr constant [13 x i8] c"%d %d %f %i\0A\00", align 1
 
-;CHECK: printfn:
+;CHECK-LABEL: printfn:
 define void @printfn(i32 %a, i16 signext %b, double %C, i8 signext %E) {
 entry:
   %conv = sext i16 %b to i32
diff --git a/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll b/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
index abc6e0d..2eeebac 100644
--- a/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
+++ b/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll
@@ -2,7 +2,7 @@
 ; rdar://13782395
 
 define i32 @t1(i32 %a, i32 %b, i8** %retaddr) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: Block address taken
 ; CHECK-NOT: Address of block that was removed by CodeGen
   store i8* blockaddress(@t1, %cond_true), i8** %retaddr
@@ -19,7 +19,7 @@ cond_false:
 }
 
 define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d, i8** %retaddr) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: Block address taken
 ; CHECK: %cond_true
 ; CHECK: add
@@ -41,7 +41,7 @@ UnifiedReturnBlock:
 }
 
 define hidden fastcc void @t3(i8** %retaddr) {
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: Block address taken
 ; CHECK-NOT: Address of block that was removed by CodeGen
 bb:
@@ -69,3 +69,62 @@ bb6.i350:                                         ; preds = %bb2.i
 KBBlockZero.exit:                                 ; preds = %bb2.i
   indirectbr i8* undef, [label %KBBlockZero_return_1, label %KBBlockZero_return_0]
 }
+
+
+; If-converter was checking for the wrong predicate subsumes pattern when doing
+; nested predicates.
+; E.g., Let A be a basic block that flows conditionally into B and B be a
+; predicated block.
+; B can be predicated with A.BrToBPredicate into A iff B.Predicate is less
+; "permissive" than A.BrToBPredicate, i.e., iff A.BrToBPredicate subsumes
+; B.Predicate. 
+; <rdar://problem/14379453>
+
+; Hard-coded registers comes from the ABI.
+; CHECK: wrapDistance:
+; CHECK: cmp r1, #59
+; CHECK-NEXT: itt le
+; CHECK-NEXT: suble r0, r2, #1
+; CHECK-NEXT: bxle lr
+; CHECK-NEXT: subs [[REG:r[0-9]+]], #120
+; CHECK-NEXT: cmp [[REG]], r1
+; CHECK-NOT: it lt
+; CHECK-NEXT: bge [[LABEL:.+]]
+; Next BB
+; CHECK-NOT: cmplt
+; CHECK: cmp r0, #119
+; CHECK-NEXT: itt le
+; CHECK-NEXT: addle r0, r1, #1
+; CHECK-NEXT: bxle lr
+; Next BB
+; CHECK: [[LABEL]]:
+; CHECK-NEXT: subs r0, r1, r0
+; CHECK-NEXT: bx lr
+define i32 @wrapDistance(i32 %tx, i32 %sx, i32 %w) {
+entry:
+  %cmp = icmp slt i32 %sx, 60
+  br i1 %cmp, label %if.then, label %if.else
+
+if.then:                                          ; preds = %entry
+  %sub = add nsw i32 %w, -1
+  br label %return
+
+if.else:                                          ; preds = %entry
+  %sub1 = add nsw i32 %w, -120
+  %cmp2 = icmp slt i32 %sub1, %sx
+  %cmp3 = icmp slt i32 %tx, 120
+  %or.cond = and i1 %cmp2, %cmp3
+  br i1 %or.cond, label %if.then4, label %if.end5
+
+if.then4:                                         ; preds = %if.else
+  %add = add nsw i32 %sx, 1
+  br label %return
+
+if.end5:                                          ; preds = %if.else
+  %sub6 = sub nsw i32 %sx, %tx
+  br label %return
+
+return:                                           ; preds = %if.end5, %if.then4, %if.then
+  %retval.0 = phi i32 [ %sub, %if.then ], [ %add, %if.then4 ], [ %sub6, %if.end5 ]
+  ret i32 %retval.0
+}
diff --git a/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll b/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll
new file mode 100644
index 0000000..1c13800
--- /dev/null
+++ b/test/CodeGen/ARM/2013-06-03-ByVal-2Kbytes.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -mcpu=cortex-a15 | FileCheck %s
+; ModuleID = 'attri_16.c'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
+target triple = "armv4t--linux-gnueabihf"
+
+%big_struct0 = type { [517 x i32] }
+%big_struct1 = type { [516 x i32] }
+
+;CHECK-LABEL: f:
+define void @f(%big_struct0* %p0, %big_struct1* %p1) {
+
+;CHECK: sub sp, sp, #8
+;CHECK: sub sp, sp, #2048
+;CHECK: bl callme0
+  call void @callme0(%big_struct0* byval %p0)
+
+;CHECK: add sp, sp, #8
+;CHECK: add sp, sp, #2048
+;CHECK: sub sp, sp, #2048
+;CHECK: bl callme1
+  call void @callme1(%big_struct1* byval %p1)
+
+;CHECK: add sp, sp, #2048
+
+  ret void
+}
+
+declare void @callme0(%big_struct0* byval)
+declare void @callme1(%big_struct1* byval)
+
diff --git a/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll b/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
new file mode 100644
index 0000000..a438c1f
--- /dev/null
+++ b/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
+target triple = "armv7--linux-gnueabi"
+
+; CHECK-LABEL: function
+define void @function() {
+; CHECK: cmp r0, #0
+; CHECK: bxne lr
+; CHECK: vmov.i32 q8, #0xff0000
+entry:
+  br i1 undef, label %vector.body, label %for.end
+
+; CHECK: vld1.32 {d18, d19}, [r0]
+; CHECK: vand q10, q9, q8
+; CHECK: vbic.i16 q9, #0xff
+; CHECK: vorr q9, q9, q10
+; CHECK: vst1.32 {d18, d19}, [r0]
+vector.body:
+  %wide.load = load <4 x i32>* undef, align 4
+  %0 = and <4 x i32> %wide.load, <i32 -16711936, i32 -16711936, i32 -16711936, i32 -16711936>
+  %1 = sub <4 x i32> %wide.load, zeroinitializer
+  %2 = and <4 x i32> %1, <i32 16711680, i32 16711680, i32 16711680, i32 16711680>
+  %3 = or <4 x i32> undef, %0
+  %4 = or <4 x i32> %3, %2
+  store <4 x i32> %4, <4 x i32>* undef, align 4
+  br label %vector.body
+
+for.end:
+  ret void
+}
+
diff --git a/test/CodeGen/ARM/a15-SD-dep.ll b/test/CodeGen/ARM/a15-SD-dep.ll
index a52468e..df921e0 100644
--- a/test/CodeGen/ARM/a15-SD-dep.ll
+++ b/test/CodeGen/ARM/a15-SD-dep.ll
@@ -1,8 +1,8 @@
 ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -disable-a15-sd-optimization -verify-machineinstrs < %s  | FileCheck -check-prefix=DISABLED %s
 ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck -check-prefix=ENABLED %s
 
-; CHECK-ENABLED: t1:
-; CHECK-DISABLED: t1:
+; CHECK-ENABLED-LABEL: t1:
+; CHECK-DISABLED-LABEL: t1:
 define <2 x float> @t1(float %f) {
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
   ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
@@ -11,8 +11,8 @@ define <2 x float> @t1(float %f) {
   ret <2 x float> %i2
 }
 
-; CHECK-ENABLED: t2:
-; CHECK-DISABLED: t2:
+; CHECK-ENABLED-LABEL: t2:
+; CHECK-DISABLED-LABEL: t2:
 define <4 x float> @t2(float %g, float %f) {
   ; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d0[0]
   ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
@@ -21,8 +21,8 @@ define <4 x float> @t2(float %g, float %f) {
   ret <4 x float> %i2
 }
 
-; CHECK-ENABLED: t3:
-; CHECK-DISABLED: t3:
+; CHECK-ENABLED-LABEL: t3:
+; CHECK-DISABLED-LABEL: t3:
 define arm_aapcs_vfpcc <2 x float> @t3(float %f) {
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] 
   ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
@@ -31,8 +31,8 @@ define arm_aapcs_vfpcc <2 x float> @t3(float %f) {
   ret <2 x float> %i2
 }
 
-; CHECK-ENABLED: t4:
-; CHECK-DISABLED: t4:
+; CHECK-ENABLED-LABEL: t4:
+; CHECK-DISABLED-LABEL: t4:
 define <2 x float> @t4(float %f) {
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
   ; CHECK-DISABLED-NOT: vdup
@@ -45,8 +45,8 @@ b:
   ret <2 x float> %i2
 }
 
-; CHECK-ENABLED: t5:
-; CHECK-DISABLED: t5:
+; CHECK-ENABLED-LABEL: t5:
+; CHECK-DISABLED-LABEL: t5:
 define arm_aapcs_vfpcc <4 x float> @t5(<4 x float> %q, float %f) {
   ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0]
   ; CHECK-ENABLED: vadd.f32
diff --git a/test/CodeGen/ARM/a15-mla.ll b/test/CodeGen/ARM/a15-mla.ll
index 25f6de4..b233cc2 100644
--- a/test/CodeGen/ARM/a15-mla.ll
+++ b/test/CodeGen/ARM/a15-mla.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s  -march=arm -float-abi=hard -mcpu=cortex-a15 -mattr=+neon,+neonfp | FileCheck %s
 
 ; This test checks that the VMLxForwarting feature is disabled for A15.
-; CHECK: fun_a
+; CHECK: fun_a:
 define <4 x i32> @fun_a(<4 x i32> %x, <4 x i32> %y) nounwind{
   %1 = add <4 x i32> %x, %y
 ; CHECK-NOT: vmul
@@ -10,3 +10,27 @@ define <4 x i32> @fun_a(<4 x i32> %x, <4 x i32> %y) nounwind{
   %3 = add <4 x i32> %y, %2
   ret <4 x i32> %3
 }
+
+; This tests checks that VMLA FP patterns can be matched in instruction selection when targeting
+; Cortex-A15.
+; CHECK: fun_b:
+define <4 x float> @fun_b(<4 x float> %x, <4 x float> %y, <4 x float> %z) nounwind{
+; CHECK: vmla.f32
+  %t = fmul <4 x float> %x, %y
+  %r = fadd <4 x float> %t, %z
+  ret <4 x float> %r
+}
+
+; This tests checks that FP VMLA instructions are not expanded into separate multiply/addition
+; operations when targeting Cortex-A15.
+; CHECK: fun_c:
+define <4 x float> @fun_c(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %u, <4 x float> %v) nounwind{
+; CHECK: vmla.f32
+  %t1 = fmul <4 x float> %x, %y
+  %r1 = fadd <4 x float> %t1, %z
+; CHECK: vmla.f32
+  %t2 = fmul <4 x float> %u, %v
+  %r2 = fadd <4 x float> %t2, %r1
+  ret <4 x float> %r2
+}
+
diff --git a/test/CodeGen/ARM/a15-partial-update.ll b/test/CodeGen/ARM/a15-partial-update.ll
index 6306790..5747253 100644
--- a/test/CodeGen/ARM/a15-partial-update.ll
+++ b/test/CodeGen/ARM/a15-partial-update.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s  | FileCheck %s
 
-; CHECK: t1:
+; CHECK-LABEL: t1:
 define <2 x float> @t1(float* %A, <2 x float> %B) {
 ; The generated code for this test uses a vld1.32 instruction
 ; to write the lane 1 of a D register containing the value of
@@ -15,7 +15,7 @@ define <2 x float> @t1(float* %A, <2 x float> %B) {
   ret <2 x float> %tmp3
 }
 
-; CHECK: t2:
+; CHECK-LABEL: t2:
 define void @t2(<4 x i8> *%in, <4 x i8> *%out, i32 %n) {
 entry:
   br label %loop
diff --git a/test/CodeGen/ARM/alloc-no-stack-realign.ll b/test/CodeGen/ARM/alloc-no-stack-realign.ll
index 273041d..6e6311d 100644
--- a/test/CodeGen/ARM/alloc-no-stack-realign.ll
+++ b/test/CodeGen/ARM/alloc-no-stack-realign.ll
@@ -1,30 +1,14 @@
-; RUN: llc < %s -mtriple=armv7-apple-ios -O0 -realign-stack=0 | FileCheck %s -check-prefix=NO-REALIGN
-; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s
+; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=NO-REALIGN
+; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=REALIGN
 
 ; rdar://12713765
 ; When realign-stack is set to false, make sure we are not creating stack
 ; objects that are assumed to be 64-byte aligned.
 @T3_retval = common global <16 x float> zeroinitializer, align 16
 
-define void @test(<16 x float>* noalias sret %agg.result) nounwind ssp {
+define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" {
 entry:
-; CHECK: test
-; CHECK: bic sp, sp, #63
-; CHECK: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48
-; CHECK: vst1.64
-; CHECK: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32
-; CHECK: vst1.64
-; CHECK: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16
-; CHECK: vst1.64
-; CHECK: vst1.64
-; CHECK: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48
-; CHECK: vst1.64
-; CHECK: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32
-; CHECK: vst1.64
-; CHECK: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16
-; CHECK: vst1.64
-; CHECK: vst1.64
-; NO-REALIGN: test
+; NO-REALIGN: test1
 ; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48
 ; NO-REALIGN: vst1.64
 ; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32
@@ -46,3 +30,29 @@ entry:
  store <16 x float> %1, <16 x float>* %agg.result, align 16
  ret void
 }
+
+define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp {
+entry:
+; REALIGN: test2
+; REALIGN: bic sp, sp, #63
+; REALIGN: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48
+; REALIGN: vst1.64
+; REALIGN: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32
+; REALIGN: vst1.64
+; REALIGN: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16
+; REALIGN: vst1.64
+; REALIGN: vst1.64
+; REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48
+; REALIGN: vst1.64
+; REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32
+; REALIGN: vst1.64
+; REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16
+; REALIGN: vst1.64
+; REALIGN: vst1.64
+ %retval = alloca <16 x float>, align 16
+ %0 = load <16 x float>* @T3_retval, align 16
+ store <16 x float> %0, <16 x float>* %retval
+ %1 = load <16 x float>* %retval
+ store <16 x float> %1, <16 x float>* %agg.result, align 16
+ ret void
+}
diff --git a/test/CodeGen/ARM/arguments.ll b/test/CodeGen/ARM/arguments.ll
index a8b42e6..e7fbf9f 100644
--- a/test/CodeGen/ARM/arguments.ll
+++ b/test/CodeGen/ARM/arguments.ll
@@ -2,9 +2,9 @@
 ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+vfp2 | FileCheck %s -check-prefix=DARWIN
 
 define i32 @f1(i32 %a, i64 %b) {
-; ELF: f1:
+; ELF-LABEL: f1:
 ; ELF: mov r0, r2
-; DARWIN: f1:
+; DARWIN-LABEL: f1:
 ; DARWIN: mov r0, r1
         %tmp = call i32 @g1(i64 %b)
         ret i32 %tmp
@@ -12,10 +12,10 @@ define i32 @f1(i32 %a, i64 %b) {
 
 ; test that allocating the double to r2/r3 makes r1 unavailable on gnueabi.
 define i32 @f2() nounwind optsize {
-; ELF: f2:
+; ELF-LABEL: f2:
 ; ELF: mov  [[REGISTER:(r[0-9]+)]], #128
 ; ELF: str  [[REGISTER]], [
-; DARWIN: f2:
+; DARWIN-LABEL: f2:
 ; DARWIN: mov	r3, #128
 entry:
   %0 = tail call i32 (i32, ...)* @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; <i32> [#uses=1]
@@ -26,10 +26,10 @@ entry:
 
 ; test that on gnueabi a 64 bit value at this position will cause r3 to go
 ; unused and the value stored in [sp]
-; ELF: f3:
+; ELF-LABEL: f3:
 ; ELF: ldr r0, [sp]
 ; ELF-NEXT: mov pc, lr
-; DARWIN: f3:
+; DARWIN-LABEL: f3:
 ; DARWIN: mov r0, r3
 ; DARWIN-NEXT: mov pc, lr
 define i32 @f3(i32 %i, i32 %j, i32 %k, i64 %l, ...) {
diff --git a/test/CodeGen/ARM/arm-frameaddr.ll b/test/CodeGen/ARM/arm-frameaddr.ll
index 2cf1422..9c4173e 100644
--- a/test/CodeGen/ARM/arm-frameaddr.ll
+++ b/test/CodeGen/ARM/arm-frameaddr.ll
@@ -5,10 +5,10 @@
 
 define i8* @t() nounwind {
 entry:
-; DARWIN: t:
+; DARWIN-LABEL: t:
 ; DARWIN: mov r0, r7
 
-; LINUX: t:
+; LINUX-LABEL: t:
 ; LINUX: mov r0, r11
 	%0 = call i8* @llvm.frameaddress(i32 0)
         ret i8* %0
diff --git a/test/CodeGen/ARM/arm-modifier.ll b/test/CodeGen/ARM/arm-modifier.ll
index c747016..8548642 100644
--- a/test/CodeGen/ARM/arm-modifier.ll
+++ b/test/CodeGen/ARM/arm-modifier.ll
@@ -60,8 +60,14 @@ ret void
 
 define i64 @f4(i64* %val) nounwind {
 entry:
-  ;CHECK: f4
+  ;CHECK-LABEL: f4:
   ;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
   %0 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [$1]", "=&r,r,*Qo"(i64* %val, i64* %val) nounwind
   ret i64 %0
 }
+
+; PR16490
+define void @f5(i64 %__pu_val) {
+  call void asm sideeffect "$1", "r,i"(i64 %__pu_val, i32 -14)
+  ret void
+}
diff --git a/test/CodeGen/ARM/arm-returnaddr.ll b/test/CodeGen/ARM/arm-returnaddr.ll
index 1272e8e..4266572 100644
--- a/test/CodeGen/ARM/arm-returnaddr.ll
+++ b/test/CodeGen/ARM/arm-returnaddr.ll
@@ -7,7 +7,7 @@
 
 define i8* @rt0(i32 %x) nounwind readnone {
 entry:
-; CHECK: rt0:
+; CHECK-LABEL: rt0:
 ; CHECK: {r7, lr}
 ; CHECK: mov r0, lr
   %0 = tail call i8* @llvm.returnaddress(i32 0)
@@ -16,7 +16,7 @@ entry:
 
 define i8* @rt2() nounwind readnone {
 entry:
-; CHECK: rt2:
+; CHECK-LABEL: rt2:
 ; CHECK: {r7, lr}
 ; CHECK: ldr r[[R0:[0-9]+]], [r7]
 ; CHECK: ldr r0, [r0]
diff --git a/test/CodeGen/ARM/atomic-64bit.ll b/test/CodeGen/ARM/atomic-64bit.ll
index f2c7305..8ec829c 100644
--- a/test/CodeGen/ARM/atomic-64bit.ll
+++ b/test/CodeGen/ARM/atomic-64bit.ll
@@ -2,154 +2,154 @@
 ; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB
 
 define i64 @test1(i64* %ptr, i64 %val) {
-; CHECK: test1:
-; CHECK: dmb ish
+; CHECK-LABEL: test1:
+; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
 ; CHECK: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK: cmp
 ; CHECK: bne
-; CHECK: dmb ish
+; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test1:
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB-LABEL: test1:
+; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
 ; CHECK-THUMB: adc.w [[REG4:[a-z0-9]+]], [[REG2]]
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB: dmb {{ish$}}
 
   %r = atomicrmw add i64* %ptr, i64 %val seq_cst
   ret i64 %r
 }
 
 define i64 @test2(i64* %ptr, i64 %val) {
-; CHECK: test2:
-; CHECK: dmb ish
+; CHECK-LABEL: test2:
+; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
 ; CHECK: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK: cmp
 ; CHECK: bne
-; CHECK: dmb ish
+; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test2:
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB-LABEL: test2:
+; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
 ; CHECK-THUMB: sbc.w [[REG4:[a-z0-9]+]], [[REG2]]
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB: dmb {{ish$}}
 
   %r = atomicrmw sub i64* %ptr, i64 %val seq_cst
   ret i64 %r
 }
 
 define i64 @test3(i64* %ptr, i64 %val) {
-; CHECK: test3:
-; CHECK: dmb ish
+; CHECK-LABEL: test3:
+; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
 ; CHECK: and [[REG4:(r[0-9]?[13579])]], [[REG2]]
 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK: cmp
 ; CHECK: bne
-; CHECK: dmb ish
+; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test3:
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB-LABEL: test3:
+; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: and.w [[REG3:[a-z0-9]+]], [[REG1]]
 ; CHECK-THUMB: and.w [[REG4:[a-z0-9]+]], [[REG2]]
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB: dmb {{ish$}}
 
   %r = atomicrmw and i64* %ptr, i64 %val seq_cst
   ret i64 %r
 }
 
 define i64 @test4(i64* %ptr, i64 %val) {
-; CHECK: test4:
-; CHECK: dmb ish
+; CHECK-LABEL: test4:
+; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
 ; CHECK: orr [[REG4:(r[0-9]?[13579])]], [[REG2]]
 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK: cmp
 ; CHECK: bne
-; CHECK: dmb ish
+; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test4:
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB-LABEL: test4:
+; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: orr.w [[REG3:[a-z0-9]+]], [[REG1]]
 ; CHECK-THUMB: orr.w [[REG4:[a-z0-9]+]], [[REG2]]
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB: dmb {{ish$}}
 
   %r = atomicrmw or i64* %ptr, i64 %val seq_cst
   ret i64 %r
 }
 
 define i64 @test5(i64* %ptr, i64 %val) {
-; CHECK: test5:
-; CHECK: dmb ish
+; CHECK-LABEL: test5:
+; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
 ; CHECK: eor [[REG4:(r[0-9]?[13579])]], [[REG2]]
 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK: cmp
 ; CHECK: bne
-; CHECK: dmb ish
+; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test5:
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB-LABEL: test5:
+; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: eor.w [[REG3:[a-z0-9]+]], [[REG1]]
 ; CHECK-THUMB: eor.w [[REG4:[a-z0-9]+]], [[REG2]]
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB: dmb {{ish$}}
 
   %r = atomicrmw xor i64* %ptr, i64 %val seq_cst
   ret i64 %r
 }
 
 define i64 @test6(i64* %ptr, i64 %val) {
-; CHECK: test6:
-; CHECK: dmb ish
+; CHECK-LABEL: test6:
+; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
 ; CHECK: cmp
 ; CHECK: bne
-; CHECK: dmb ish
+; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test6:
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB-LABEL: test6:
+; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB: dmb {{ish$}}
 
   %r = atomicrmw xchg i64* %ptr, i64 %val seq_cst
   ret i64 %r
 }
 
 define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
-; CHECK: test7:
-; CHECK: dmb ish
+; CHECK-LABEL: test7:
+; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: cmp [[REG1]]
 ; CHECK: cmpeq [[REG2]]
@@ -157,10 +157,10 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
 ; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
 ; CHECK: cmp
 ; CHECK: bne
-; CHECK: dmb ish
+; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test7:
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB-LABEL: test7:
+; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: cmp [[REG1]]
 ; CHECK-THUMB: it eq
@@ -169,7 +169,7 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB: dmb {{ish$}}
 
   %r = cmpxchg i64* %ptr, i64 %val1, i64 %val2 seq_cst
   ret i64 %r
@@ -178,7 +178,7 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
 ; Compiles down to cmpxchg
 ; FIXME: Should compile to a single ldrexd
 define i64 @test8(i64* %ptr) {
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: cmp [[REG1]]
 ; CHECK: cmpeq [[REG2]]
@@ -186,9 +186,9 @@ define i64 @test8(i64* %ptr) {
 ; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
 ; CHECK: cmp
 ; CHECK: bne
-; CHECK: dmb ish
+; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test8:
+; CHECK-THUMB-LABEL: test8:
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: cmp [[REG1]]
 ; CHECK-THUMB: it eq
@@ -197,7 +197,7 @@ define i64 @test8(i64* %ptr) {
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB: dmb {{ish$}}
 
   %r = load atomic i64* %ptr seq_cst, align 8
   ret i64 %r
@@ -206,29 +206,29 @@ define i64 @test8(i64* %ptr) {
 ; Compiles down to atomicrmw xchg; there really isn't any more efficient
 ; way to write it.
 define void @test9(i64* %ptr, i64 %val) {
-; CHECK: test9:
-; CHECK: dmb ish
+; CHECK-LABEL: test9:
+; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
 ; CHECK: cmp
 ; CHECK: bne
-; CHECK: dmb ish
+; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test9:
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB-LABEL: test9:
+; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB: dmb {{ish$}}
 
   store atomic i64 %val, i64* %ptr seq_cst, align 8
   ret void
 }
 
 define i64 @test10(i64* %ptr, i64 %val) {
-; CHECK: test10:
-; CHECK: dmb ish
+; CHECK-LABEL: test10:
+; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
 ; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
@@ -236,10 +236,10 @@ define i64 @test10(i64* %ptr, i64 %val) {
 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK: cmp
 ; CHECK: bne
-; CHECK: dmb ish
+; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test10:
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB-LABEL: test10:
+; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
 ; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
@@ -247,15 +247,15 @@ define i64 @test10(i64* %ptr, i64 %val) {
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB: dmb {{ish$}}
 
   %r = atomicrmw min i64* %ptr, i64 %val seq_cst
   ret i64 %r
 }
 
 define i64 @test11(i64* %ptr, i64 %val) {
-; CHECK: test11:
-; CHECK: dmb ish
+; CHECK-LABEL: test11:
+; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
 ; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
@@ -263,11 +263,11 @@ define i64 @test11(i64* %ptr, i64 %val) {
 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK: cmp
 ; CHECK: bne
-; CHECK: dmb ish
+; CHECK: dmb {{ish$}}
 
 
-; CHECK-THUMB: test11:
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB-LABEL: test11:
+; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
 ; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
@@ -275,15 +275,15 @@ define i64 @test11(i64* %ptr, i64 %val) {
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB: dmb {{ish$}}
 
   %r = atomicrmw umin i64* %ptr, i64 %val seq_cst
   ret i64 %r
 }
 
 define i64 @test12(i64* %ptr, i64 %val) {
-; CHECK: test12:
-; CHECK: dmb ish
+; CHECK-LABEL: test12:
+; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
 ; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
@@ -291,10 +291,10 @@ define i64 @test12(i64* %ptr, i64 %val) {
 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK: cmp
 ; CHECK: bne
-; CHECK: dmb ish
+; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test12:
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB-LABEL: test12:
+; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
 ; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
@@ -302,15 +302,15 @@ define i64 @test12(i64* %ptr, i64 %val) {
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB: dmb {{ish$}}
 
   %r = atomicrmw max i64* %ptr, i64 %val seq_cst
   ret i64 %r
 }
 
 define i64 @test13(i64* %ptr, i64 %val) {
-; CHECK: test13:
-; CHECK: dmb ish
+; CHECK-LABEL: test13:
+; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
 ; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
@@ -318,10 +318,10 @@ define i64 @test13(i64* %ptr, i64 %val) {
 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK: cmp
 ; CHECK: bne
-; CHECK: dmb ish
+; CHECK: dmb {{ish$}}
 
-; CHECK-THUMB: test13:
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB-LABEL: test13:
+; CHECK-THUMB: dmb {{ish$}}
 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
 ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
 ; CHECK-THUMB: sbcs.w {{[a-z0-9]+}}, [[REG2]], [[REG4:[a-z0-9]+]]
@@ -329,7 +329,7 @@ define i64 @test13(i64* %ptr, i64 %val) {
 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
 ; CHECK-THUMB: cmp
 ; CHECK-THUMB: bne
-; CHECK-THUMB: dmb ish
+; CHECK-THUMB: dmb {{ish$}}
   %r = atomicrmw umax i64* %ptr, i64 %val seq_cst
   ret i64 %r
 }
diff --git a/test/CodeGen/ARM/atomic-cmp.ll b/test/CodeGen/ARM/atomic-cmp.ll
index 82726da..51ada69 100644
--- a/test/CodeGen/ARM/atomic-cmp.ll
+++ b/test/CodeGen/ARM/atomic-cmp.ll
@@ -3,11 +3,11 @@
 ; rdar://8964854
 
 define i8 @t(i8* %a, i8 %b, i8 %c) nounwind {
-; ARM: t:
+; ARM-LABEL: t:
 ; ARM: ldrexb
 ; ARM: strexb
 
-; T2: t:
+; T2-LABEL: t:
 ; T2: ldrexb
 ; T2: strexb
   %tmp0 = cmpxchg i8* %a, i8 %b, i8 %c monotonic
diff --git a/test/CodeGen/ARM/atomic-load-store.ll b/test/CodeGen/ARM/atomic-load-store.ll
index 12a8fe4..476b3dd 100644
--- a/test/CodeGen/ARM/atomic-load-store.ll
+++ b/test/CodeGen/ARM/atomic-load-store.ll
@@ -2,18 +2,19 @@
 ; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=ARM
 ; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s -check-prefix=THUMBTWO
 ; RUN: llc < %s -mtriple=thumbv6-apple-ios | FileCheck %s -check-prefix=THUMBONE
+; RUN  llc < %s -mtriple=armv4-apple-ios | FileCheck %s -check-prefix=ARMV4
 
 define void @test1(i32* %ptr, i32 %val1) {
 ; ARM: test1
-; ARM: dmb ish
+; ARM: dmb {{ish$}}
 ; ARM-NEXT: str
-; ARM-NEXT: dmb ish
+; ARM-NEXT: dmb {{ish$}}
 ; THUMBONE: test1
 ; THUMBONE: __sync_lock_test_and_set_4
 ; THUMBTWO: test1
-; THUMBTWO: dmb ish
+; THUMBTWO: dmb {{ish$}}
 ; THUMBTWO-NEXT: str
-; THUMBTWO-NEXT: dmb ish
+; THUMBTWO-NEXT: dmb {{ish$}}
   store atomic i32 %val1, i32* %ptr seq_cst, align 4
   ret void
 }
@@ -21,12 +22,12 @@ define void @test1(i32* %ptr, i32 %val1) {
 define i32 @test2(i32* %ptr) {
 ; ARM: test2
 ; ARM: ldr
-; ARM-NEXT: dmb ish
+; ARM-NEXT: dmb {{ish$}}
 ; THUMBONE: test2
 ; THUMBONE: __sync_val_compare_and_swap_4
 ; THUMBTWO: test2
 ; THUMBTWO: ldr
-; THUMBTWO-NEXT: dmb ish
+; THUMBTWO-NEXT: dmb {{ish$}}
   %val = load atomic i32* %ptr seq_cst, align 4
   ret i32 %val
 }
@@ -54,3 +55,17 @@ define void @test4(i8* %ptr1, i8* %ptr2) {
   store atomic i8 %val, i8* %ptr2 seq_cst, align 1
   ret void
 }
+
+define i64 @test_old_load_64bit(i64* %p) {
+; ARMV4: test_old_load_64bit
+; ARMV4: ___sync_val_compare_and_swap_8
+  %1 = load atomic i64* %p seq_cst, align 8
+  ret i64 %1
+}
+
+define void @test_old_store_64bit(i64* %p, i64 %v) {
+; ARMV4: test_old_store_64bit
+; ARMV4: ___sync_lock_test_and_set_8
+  store atomic i64 %v, i64* %p seq_cst, align 8
+  ret void
+}
diff --git a/test/CodeGen/ARM/atomicrmw_minmax.ll b/test/CodeGen/ARM/atomicrmw_minmax.ll
index 69f1384..5befc22 100644
--- a/test/CodeGen/ARM/atomicrmw_minmax.ll
+++ b/test/CodeGen/ARM/atomicrmw_minmax.ll
@@ -1,6 +1,6 @@
 ;  RUN: llc -march=arm -mcpu=cortex-a9 < %s | FileCheck %s
 
-;  CHECK: max:
+;  CHECK-LABEL: max:
 define i32 @max(i8 %ctx, i32* %ptr, i32 %val)
 {
 ;  CHECK: ldrex
@@ -10,7 +10,7 @@ define i32 @max(i8 %ctx, i32* %ptr, i32 %val)
   ret i32 %old
 }
 
-;  CHECK: min:
+;  CHECK-LABEL: min:
 define i32 @min(i8 %ctx, i32* %ptr, i32 %val)
 {
 ;  CHECK: ldrex
diff --git a/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/test/CodeGen/ARM/avoid-cpsr-rmw.ll
index c14f530..0217a4a 100644
--- a/test/CodeGen/ARM/avoid-cpsr-rmw.ll
+++ b/test/CodeGen/ARM/avoid-cpsr-rmw.ll
@@ -6,7 +6,7 @@
 
 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
  entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: muls [[REG:(r[0-9]+)]], r3, r2
 ; CHECK-NEXT: mul  [[REG2:(r[0-9]+)]], r1, r0
 ; CHECK-NEXT: muls r0, [[REG]], [[REG2]]
@@ -20,7 +20,7 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
 ; rdar://10357570
 define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
   %tobool7 = icmp eq i32* %ptr2, null
   br i1 %tobool7, label %while.end, label %while.body
 
@@ -54,7 +54,7 @@ while.end:
 ; rdar://12878928
 define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
   %tobool7 = icmp eq i32* %ptr2, null
   br i1 %tobool7, label %while.end, label %while.body
 
diff --git a/test/CodeGen/ARM/bfc.ll b/test/CodeGen/ARM/bfc.ll
index c4a44b4..3a17d2b 100644
--- a/test/CodeGen/ARM/bfc.ll
+++ b/test/CodeGen/ARM/bfc.ll
@@ -2,7 +2,7 @@
 
 ; 4278190095 = 0xff00000f
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: bfc
     %tmp = and i32 %a, 4278190095
     ret i32 %tmp
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
 
 ; 4286578688 = 0xff800000
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: bfc
     %tmp = and i32 %a, 4286578688
     ret i32 %tmp
@@ -18,7 +18,7 @@ define i32 @f2(i32 %a) {
 
 ; 4095 = 0x00000fff
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: bfc
     %tmp = and i32 %a, 4095
     ret i32 %tmp
diff --git a/test/CodeGen/ARM/bfi.ll b/test/CodeGen/ARM/bfi.ll
index 84f3813..72a4678 100644
--- a/test/CodeGen/ARM/bfi.ll
+++ b/test/CodeGen/ARM/bfi.ll
@@ -52,7 +52,7 @@ define i32 @f4(i32 %a) nounwind {
 ; rdar://8458663
 define i32 @f5(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: bfc
 ; CHECK: bfi r0, r1, #20, #4
   %0 = and i32 %a, -15728641
@@ -65,7 +65,7 @@ entry:
 ; rdar://9609030
 define i32 @f6(i32 %a, i32 %b) nounwind readnone {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: bic
 ; CHECK: bfi r0, r1, #8, #9
   %and = and i32 %a, -130817
diff --git a/test/CodeGen/ARM/bswap-inline-asm.ll b/test/CodeGen/ARM/bswap-inline-asm.ll
index 472213d..31f9d72 100644
--- a/test/CodeGen/ARM/bswap-inline-asm.ll
+++ b/test/CodeGen/ARM/bswap-inline-asm.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 | FileCheck %s
 
 define i32 @t1(i32 %x) nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK-NOT: InlineAsm
 ; CHECK: rev
   %asmtmp = tail call i32 asm "rev $0, $1\0A", "=l,l"(i32 %x) nounwind
diff --git a/test/CodeGen/ARM/call-noret-minsize.ll b/test/CodeGen/ARM/call-noret-minsize.ll
index df3c19e..e610d29 100644
--- a/test/CodeGen/ARM/call-noret-minsize.ll
+++ b/test/CodeGen/ARM/call-noret-minsize.ll
@@ -4,10 +4,10 @@
 
 define void @t1() noreturn minsize nounwind ssp {
 entry:
-; ARM: t1:
+; ARM-LABEL: t1:
 ; ARM: bl _bar
 
-; SWIFT: t1:
+; SWIFT-LABEL: t1:
 ; SWIFT: bl _bar
   tail call void @bar() noreturn nounwind
   unreachable
@@ -15,10 +15,10 @@ entry:
 
 define void @t2() noreturn minsize nounwind ssp {
 entry:
-; ARM: t2:
+; ARM-LABEL: t2:
 ; ARM: bl _t1
 
-; SWIFT: t2:
+; SWIFT-LABEL: t2:
 ; SWIFT: bl _t1
   tail call void @t1() noreturn nounwind
   unreachable
diff --git a/test/CodeGen/ARM/call-noret.ll b/test/CodeGen/ARM/call-noret.ll
index 27062dc..bb56e8b 100644
--- a/test/CodeGen/ARM/call-noret.ll
+++ b/test/CodeGen/ARM/call-noret.ll
@@ -4,11 +4,11 @@
 
 define void @t1() noreturn nounwind ssp {
 entry:
-; ARM: t1:
+; ARM-LABEL: t1:
 ; ARM: mov lr, pc
 ; ARM: b _bar
 
-; SWIFT: t1:
+; SWIFT-LABEL: t1:
 ; SWIFT: mov lr, pc
 ; SWIFT: b _bar
   tail call void @bar() noreturn nounwind
@@ -17,11 +17,11 @@ entry:
 
 define void @t2() noreturn nounwind ssp {
 entry:
-; ARM: t2:
+; ARM-LABEL: t2:
 ; ARM: mov lr, pc
 ; ARM: b _t1
 
-; SWIFT: t2:
+; SWIFT-LABEL: t2:
 ; SWIFT: mov lr, pc
 ; SWIFT: b _t1
   tail call void @t1() noreturn nounwind
diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll
index c7e17ea..d463602 100644
--- a/test/CodeGen/ARM/call-tc.ll
+++ b/test/CodeGen/ARM/call-tc.ll
@@ -11,16 +11,16 @@
 declare void @g(i32, i32, i32, i32)
 
 define void @t1() {
-; CHECKELF: t1:
+; CHECKELF-LABEL: t1:
 ; CHECKELF: bl g(PLT)
         call void @g( i32 1, i32 2, i32 3, i32 4 )
         ret void
 }
 
 define void @t2() {
-; CHECKV6: t2:
+; CHECKV6-LABEL: t2:
 ; CHECKV6: bx r0
-; CHECKT2D: t2:
+; CHECKT2D-LABEL: t2:
 ; CHECKT2D: ldr
 ; CHECKT2D-NEXT: ldr
 ; CHECKT2D-NEXT: bx r0
@@ -30,11 +30,11 @@ define void @t2() {
 }
 
 define void @t3() {
-; CHECKV6: t3:
+; CHECKV6-LABEL: t3:
 ; CHECKV6: b _t2
-; CHECKELF: t3:
+; CHECKELF-LABEL: t3:
 ; CHECKELF: b t2(PLT)
-; CHECKT2D: t3:
+; CHECKT2D-LABEL: t3:
 ; CHECKT2D: b.w _t2
 
         tail call void @t2( )            ; <i32> [#uses=0]
@@ -44,9 +44,9 @@ define void @t3() {
 ; Sibcall optimization of expanded libcalls. rdar://8707777
 define double @t4(double %a) nounwind readonly ssp {
 entry:
-; CHECKV6: t4:
+; CHECKV6-LABEL: t4:
 ; CHECKV6: b _sin
-; CHECKELF: t4:
+; CHECKELF-LABEL: t4:
 ; CHECKELF: b sin(PLT)
   %0 = tail call double @sin(double %a) nounwind readonly ; <double> [#uses=1]
   ret double %0
@@ -54,9 +54,9 @@ entry:
 
 define float @t5(float %a) nounwind readonly ssp {
 entry:
-; CHECKV6: t5:
+; CHECKV6-LABEL: t5:
 ; CHECKV6: b _sinf
-; CHECKELF: t5:
+; CHECKELF-LABEL: t5:
 ; CHECKELF: b sinf(PLT)
   %0 = tail call float @sinf(float %a) nounwind readonly ; <float> [#uses=1]
   ret float %0
@@ -68,9 +68,9 @@ declare double @sin(double) nounwind readonly
 
 define i32 @t6(i32 %a, i32 %b) nounwind readnone {
 entry:
-; CHECKV6: t6:
+; CHECKV6-LABEL: t6:
 ; CHECKV6: b ___divsi3
-; CHECKELF: t6:
+; CHECKELF-LABEL: t6:
 ; CHECKELF: b __aeabi_idiv(PLT)
   %0 = sdiv i32 %a, %b
   ret i32 %0
@@ -82,7 +82,7 @@ declare void @foo() nounwind
 
 define void @t7() nounwind {
 entry:
-; CHECKT2D: t7:
+; CHECKT2D-LABEL: t7:
 ; CHECKT2D: blxeq _foo
 ; CHECKT2D-NEXT: pop.w
 ; CHECKT2D-NEXT: b.w _foo
@@ -101,7 +101,7 @@ bb:
 ; rdar://11140249
 define i32 @t8(i32 %x) nounwind ssp {
 entry:
-; CHECKT2D: t8:
+; CHECKT2D-LABEL: t8:
 ; CHECKT2D-NOT: push
   %and = and i32 %x, 1
   %tobool = icmp eq i32 %and, 0
@@ -147,7 +147,7 @@ declare i32 @c(i32)
 @x = external global i32, align 4
 
 define i32 @t9() nounwind {
-; CHECKT2D: t9:
+; CHECKT2D-LABEL: t9:
 ; CHECKT2D: blx __ZN9MutexLockC1Ev
 ; CHECKT2D: blx __ZN9MutexLockD1Ev
 ; CHECKT2D: b.w ___divsi3
@@ -167,7 +167,7 @@ declare %class.MutexLock* @_ZN9MutexLockD1Ev(%class.MutexLock*) unnamed_addr nou
 ; Correctly preserve the input chain for the tailcall node in the bitcast case,
 ; otherwise the call to floorf is lost.
 define float @libcall_tc_test2(float* nocapture %a, float %b) {
-; CHECKT2D: libcall_tc_test2:
+; CHECKT2D-LABEL: libcall_tc_test2:
 ; CHECKT2D: blx _floorf
 ; CHECKT2D: b.w _truncf
   %1 = load float* %a, align 4
diff --git a/test/CodeGen/ARM/call_nolink.ll b/test/CodeGen/ARM/call_nolink.ll
index 5ec7f74..48fa3a6 100644
--- a/test/CodeGen/ARM/call_nolink.ll
+++ b/test/CodeGen/ARM/call_nolink.ll
@@ -7,7 +7,7 @@
 @numi = external global i32		; <i32*> [#uses=1]
 @counter = external global [2 x i32]		; <[2 x i32]*> [#uses=1]
 
-; CHECK: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i:
+; CHECK-LABEL: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i:
 ; CHECK-NOT: bx lr
 
 define void @main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i() {
@@ -56,7 +56,7 @@ define void @PR15520(void ()* %fn) {
   call void %fn()
   ret void
 
-; CHECK: PR15520:
+; CHECK-LABEL: PR15520:
 ; CHECK: mov lr, pc
 ; CHECK: mov pc, r0
 }
diff --git a/test/CodeGen/ARM/carry.ll b/test/CodeGen/ARM/carry.ll
index bf51cd6..f67987f 100644
--- a/test/CodeGen/ARM/carry.ll
+++ b/test/CodeGen/ARM/carry.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: subs r
 ; CHECK: sbc r
 entry:
@@ -10,7 +10,7 @@ entry:
 }
 
 define i64 @f2(i64 %a, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: adc r
 ; CHECK: subs r
 ; CHECK: sbc r
@@ -22,7 +22,7 @@ entry:
 
 ; add with live carry
 define i64 @f3(i32 %al, i32 %bl) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: adds r
 ; CHECK: adc r
 entry:
@@ -39,7 +39,7 @@ entry:
 ; rdar://10073745
 define i64 @f4(i64 %x) nounwind readnone {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: rsbs r
 ; CHECK: rsc r
   %0 = sub nsw i64 0, %x
@@ -49,7 +49,7 @@ entry:
 ; rdar://12559385
 define i64 @f5(i32 %vi) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: movw [[REG:r[0-9]+]], #36102
 ; CHECK: sbc r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
     %v0 = zext i32 %vi to i64
diff --git a/test/CodeGen/ARM/code-placement.ll b/test/CodeGen/ARM/code-placement.ll
index 487ec69..70d85c9 100644
--- a/test/CodeGen/ARM/code-placement.ll
+++ b/test/CodeGen/ARM/code-placement.ll
@@ -7,7 +7,7 @@
 
 define arm_apcscc %struct.list_head* @t1(%struct.list_head* %list) nounwind {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
   %0 = icmp eq %struct.list_head* %list, null
   br i1 %0, label %bb2, label %bb
 
@@ -33,7 +33,7 @@ bb2:
 ; rdar://8117827
 define i32 @t2(i32 %passes, i32* nocapture %src, i32 %size) nounwind readonly {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: beq LBB1_[[RET:.]]
   %0 = icmp eq i32 %passes, 0                     ; <i1> [#uses=1]
   br i1 %0, label %bb5, label %bb.nph15
diff --git a/test/CodeGen/ARM/copy-paired-reg.ll b/test/CodeGen/ARM/copy-paired-reg.ll
new file mode 100644
index 0000000..17a4461
--- /dev/null
+++ b/test/CodeGen/ARM/copy-paired-reg.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs
+; RUN: llc < %s -mtriple=armv7-linux-gnueabi -verify-machineinstrs
+
+define void @f() {
+  %a = alloca i8, i32 8, align 8
+  %b = alloca i8, i32 8, align 8
+
+  %c = bitcast i8* %a to i64*
+  %d = bitcast i8* %b to i64*
+
+  store atomic i64 0, i64* %c seq_cst, align 8
+  store atomic i64 0, i64* %d seq_cst, align 8
+
+  %e = load atomic i64* %d seq_cst, align 8
+
+  ret void
+}
diff --git a/test/CodeGen/ARM/crash-shufflevector.ll b/test/CodeGen/ARM/crash-shufflevector.ll
index bdc0e0e..0ae8668 100644
--- a/test/CodeGen/ARM/crash-shufflevector.ll
+++ b/test/CodeGen/ARM/crash-shufflevector.ll
@@ -7,4 +7,4 @@ define void @f(<4 x i8> %param1, <4 x i8> %param2) {
    %z = shufflevector <16 x i8> %y1, <16 x i8> %y2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
    call void @g(<16 x i8> %z)
    ret void
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/ARM/ctz.ll b/test/CodeGen/ARM/ctz.ll
index 5ebca53..2c7efc7 100644
--- a/test/CodeGen/ARM/ctz.ll
+++ b/test/CodeGen/ARM/ctz.ll
@@ -3,7 +3,7 @@
 declare i32 @llvm.cttz.i32(i32, i1)
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: rbit
 ; CHECK: clz
   %tmp = call i32 @llvm.cttz.i32( i32 %a, i1 true )
diff --git a/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll b/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
index 18f57ea..8950abd 100644
--- a/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
+++ b/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
 
-; CHECK: f:
+; CHECK-LABEL: f:
 define float @f(<4 x i16>* nocapture %in) {
   ; CHECK: vldr
   ; CHECK: vmovl.u16
diff --git a/test/CodeGen/ARM/dagcombine-concatvector.ll b/test/CodeGen/ARM/dagcombine-concatvector.ll
index e9e0fe3..d8c6c64 100644
--- a/test/CodeGen/ARM/dagcombine-concatvector.ll
+++ b/test/CodeGen/ARM/dagcombine-concatvector.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 | FileCheck %s
 
 ; PR15525
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: ldr.w	[[REG:r[0-9]+]], [sp]
 ; CHECK-NEXT: vmov	{{d[0-9]+}}, r1, r2
 ; CHECK-NEXT: vmov	{{d[0-9]+}}, r3, [[REG]]
diff --git a/test/CodeGen/ARM/data-in-code-annotations.ll b/test/CodeGen/ARM/data-in-code-annotations.ll
index a66a9d1..da70178 100644
--- a/test/CodeGen/ARM/data-in-code-annotations.ll
+++ b/test/CodeGen/ARM/data-in-code-annotations.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
 
 define double @f1() nounwind {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .data_region
 ; CHECK: .long 1413754129
 ; CHECK: .long 1074340347
@@ -11,7 +11,7 @@ define double @f1() nounwind {
 
 
 define i32 @f2()  {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .data_region jt32
 ; CHECK: .end_data_region
 
diff --git a/test/CodeGen/ARM/debug-info-arg.ll b/test/CodeGen/ARM/debug-info-arg.ll
index c162260..89ccb20 100644
--- a/test/CodeGen/ARM/debug-info-arg.ll
+++ b/test/CodeGen/ARM/debug-info-arg.ll
@@ -11,7 +11,7 @@ define void @foo(%struct.tag_s* nocapture %this, %struct.tag_s* %c, i64 %x, i64
   tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %c}, i64 0, metadata !13), !dbg !21
   tail call void @llvm.dbg.value(metadata !{i64 %x}, i64 0, metadata !14), !dbg !22
   tail call void @llvm.dbg.value(metadata !{i64 %y}, i64 0, metadata !17), !dbg !23
-;CHECK:	@DEBUG_VALUE: foo:y <- R7+4294967295
+;CHECK:	@DEBUG_VALUE: foo:y <- [R7+8]
   tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %ptr1}, i64 0, metadata !18), !dbg !24
   tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %ptr2}, i64 0, metadata !19), !dbg !25
   %1 = icmp eq %struct.tag_s* %c, null, !dbg !26
@@ -31,7 +31,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, metadata !32, i32 12, metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, metadata !"", i32 0, null, null, metadata !30, null,  null, null} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !32, i32 12, metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, metadata !"", i32 0, metadata !4, metadata !4, metadata !30, null,  null, null} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 786478, metadata !2, metadata !2, metadata !"foo", metadata !"foo", metadata !"", i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void (%struct.tag_s*, %struct.tag_s*, i64, i64, %struct.tag_s*, %struct.tag_s*)* @foo, null, null, metadata !31, i32 11} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !32} ; [ DW_TAG_file_type ]
 !3 = metadata !{i32 786453, metadata !32, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
diff --git a/test/CodeGen/ARM/debug-info-blocks.ll b/test/CodeGen/ARM/debug-info-blocks.ll
index d0bfecc..bd55786 100644
--- a/test/CodeGen/ARM/debug-info-blocks.ll
+++ b/test/CodeGen/ARM/debug-info-blocks.ll
@@ -1,5 +1,5 @@
 ; RUN: llc -O0 < %s | FileCheck %s
-; CHECK: @DEBUG_VALUE: mydata <- [sp+#{{[0-9]+}}]+#0
+; CHECK: @DEBUG_VALUE: foobar_func_block_invoke_0:mydata <- [SP+{{[0-9]+}}]
 ; Radar 9331779
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
 target triple = "thumbv7-apple-ios"
@@ -94,7 +94,7 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 16, metadata !40, metadata !"Apple clang version 2.1", i1 false, metadata !"", i32 2, metadata !147, null, metadata !148, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !153, i32 16, metadata !"Apple clang version 2.1", i1 false, metadata !"", i32 2, metadata !147, metadata !26, metadata !148, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 786433, metadata !160, metadata !0, metadata !"", i32 248, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !3, i32 0, i32 0} ; [ DW_TAG_enumeration_type ]
 !2 = metadata !{i32 786473, metadata !160} ; [ DW_TAG_file_type ]
 !3 = metadata !{metadata !4}
@@ -117,7 +117,7 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load
 !20 = metadata !{i32 786473, metadata !151} ; [ DW_TAG_file_type ]
 !21 = metadata !{metadata !22}
 !22 = metadata !{i32 786472, metadata !"Eleven", i64 0} ; [ DW_TAG_enumerator ]
-!23 = metadata !{i32 786478, metadata !24, metadata !"foobar_func_block_invoke_0", metadata !"foobar_func_block_invoke_0", metadata !"", metadata !24, i32 609, metadata !25, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (i8*, %0*, [4 x i32], [4 x i32])* @foobar_func_block_invoke_0, null, null, null, i32 609} ; [ DW_TAG_subprogram ]
+!23 = metadata !{i32 786478, metadata !152, metadata !24, metadata !"foobar_func_block_invoke_0", metadata !"foobar_func_block_invoke_0", metadata !"", i32 609, metadata !25, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (i8*, %0*, [4 x i32], [4 x i32])* @foobar_func_block_invoke_0, null, null, null, i32 609} ; [ DW_TAG_subprogram ]
 !24 = metadata !{i32 786473, metadata !152} ; [ DW_TAG_file_type ]
 !25 = metadata !{i32 786453, metadata !152, metadata !24, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !26, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !26 = metadata !{null}
@@ -162,15 +162,15 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load
 !65 = metadata !{i32 786473, metadata !155} ; [ DW_TAG_file_type ]
 !66 = metadata !{metadata !67}
 !67 = metadata !{i32 786445, metadata !155, metadata !65, metadata !"isa", i32 67, i64 32, i64 32, i64 0, i32 2, metadata !68, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ]
-!68 = metadata !{i32 786454, metadata !0, metadata !"Class", metadata !40, i32 197, i64 0, i64 0, i64 0, i32 0, metadata !69} ; [ DW_TAG_typedef ]
+!68 = metadata !{i32 786454, metadata !153, metadata !0, metadata !"Class", i32 197, i64 0, i64 0, i64 0, i32 0, metadata !69} ; [ DW_TAG_typedef ]
 !69 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !70} ; [ DW_TAG_pointer_type ]
-!70 = metadata !{i32 786451, metadata !40, metadata !0, metadata !"objc_class", i32 0, i64 0, i64 0, i32 0, i32 4, i32 0, null, i32 0, i32 0} ; [ DW_TAG_structure_type ]
+!70 = metadata !{i32 786451, metadata !153, metadata !0, metadata !"objc_class", i32 0, i64 0, i64 0, i32 0, i32 4, i32 0, null, i32 0, i32 0} ; [ DW_TAG_structure_type ]
 !71 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"_mydataRef", i32 28, i64 32, i64 32, i64 32, i32 0, metadata !72, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ]
-!72 = metadata !{i32 786454, metadata !0, metadata !"CFTypeRef", metadata !24, i32 313, i64 0, i64 0, i64 0, i32 0, metadata !73} ; [ DW_TAG_typedef ]
+!72 = metadata !{i32 786454, metadata !152, metadata !0, metadata !"CFTypeRef", i32 313, i64 0, i64 0, i64 0, i32 0, metadata !73} ; [ DW_TAG_typedef ]
 !73 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !74} ; [ DW_TAG_pointer_type ]
 !74 = metadata !{i32 786470, null, metadata !0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null} ; [ DW_TAG_const_type ]
 !75 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"_scale", i32 29, i64 32, i64 32, i64 64, i32 0, metadata !76, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ]
-!76 = metadata !{i32 786454, metadata !0, metadata !"Float", metadata !77, i32 89, i64 0, i64 0, i64 0, i32 0, metadata !78} ; [ DW_TAG_typedef ]
+!76 = metadata !{i32 786454, metadata !156, metadata !0, metadata !"Float", i32 89, i64 0, i64 0, i64 0, i32 0, metadata !78} ; [ DW_TAG_typedef ]
 !77 = metadata !{i32 786473, metadata !156} ; [ DW_TAG_file_type ]
 !78 = metadata !{i32 786468, null, metadata !0, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
 !79 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"_mydataFlags", i32 37, i64 8, i64 8, i64 96, i32 0, metadata !80, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ]
@@ -187,13 +187,13 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load
 !90 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !91} ; [ DW_TAG_pointer_type ]
 !91 = metadata !{i32 786451, metadata !152, metadata !40, metadata !"MyWork", i32 36, i64 384, i64 32, i32 0, i32 0, i32 0, metadata !92, i32 16, i32 0} ; [ DW_TAG_structure_type ]
 !92 = metadata !{metadata !93, metadata !98, metadata !101, metadata !107, metadata !123}
-!93 = metadata !{i32 786460, metadata !91, null, metadata !24, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !94} ; [ DW_TAG_inheritance ]
+!93 = metadata !{i32 786460, metadata !152, metadata !91, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !94} ; [ DW_TAG_inheritance ]
 !94 = metadata !{i32 786451, metadata !157, metadata !40, metadata !"twork", i32 43, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !96, i32 16, i32 0} ; [ DW_TAG_structure_type ]
 !95 = metadata !{i32 786473, metadata !157} ; [ DW_TAG_file_type ]
 !96 = metadata !{metadata !97}
 !97 = metadata !{i32 786460, metadata !94, null, metadata !95, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !64} ; [ DW_TAG_inheritance ]
 !98 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"_itemID", i32 38, i64 64, i64 32, i64 32, i32 1, metadata !99, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ]
-!99 = metadata !{i32 786454, metadata !0, metadata !"uint64_t", metadata !40, i32 55, i64 0, i64 0, i64 0, i32 0, metadata !100} ; [ DW_TAG_typedef ]
+!99 = metadata !{i32 786454, metadata !153, metadata !0, metadata !"uint64_t", i32 55, i64 0, i64 0, i64 0, i32 0, metadata !100} ; [ DW_TAG_typedef ]
 !100 = metadata !{i32 786468, null, metadata !0, metadata !"long long unsigned int", i32 0, i64 64, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
 !101 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"_library", i32 39, i64 32, i64 32, i64 96, i32 1, metadata !102, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ]
 !102 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !103} ; [ DW_TAG_pointer_type ]
@@ -202,24 +202,24 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load
 !105 = metadata !{metadata !106}
 !106 = metadata !{i32 786460, metadata !103, null, metadata !104, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !64} ; [ DW_TAG_inheritance ]
 !107 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"_bounds", i32 40, i64 128, i64 32, i64 128, i32 1, metadata !108, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ]
-!108 = metadata !{i32 786454, metadata !0, metadata !"CR", metadata !40, i32 33, i64 0, i64 0, i64 0, i32 0, metadata !109} ; [ DW_TAG_typedef ]
+!108 = metadata !{i32 786454, metadata !153, metadata !0, metadata !"CR", i32 33, i64 0, i64 0, i64 0, i32 0, metadata !109} ; [ DW_TAG_typedef ]
 !109 = metadata !{i32 786451, metadata !156, metadata !0, metadata !"CR", i32 29, i64 128, i64 32, i32 0, i32 0, i32 0, metadata !110, i32 0, i32 0} ; [ DW_TAG_structure_type ]
 !110 = metadata !{metadata !111, metadata !117}
 !111 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"origin", i32 30, i64 64, i64 32, i64 0, i32 0, metadata !112} ; [ DW_TAG_member ]
-!112 = metadata !{i32 786454, metadata !0, metadata !"CP", metadata !77, i32 17, i64 0, i64 0, i64 0, i32 0, metadata !113} ; [ DW_TAG_typedef ]
+!112 = metadata !{i32 786454, metadata !156, metadata !0, metadata !"CP", i32 17, i64 0, i64 0, i64 0, i32 0, metadata !113} ; [ DW_TAG_typedef ]
 !113 = metadata !{i32 786451, metadata !156, metadata !0, metadata !"CP", i32 13, i64 64, i64 32, i32 0, i32 0, i32 0, metadata !114, i32 0, i32 0} ; [ DW_TAG_structure_type ]
 !114 = metadata !{metadata !115, metadata !116}
 !115 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"x", i32 14, i64 32, i64 32, i64 0, i32 0, metadata !76} ; [ DW_TAG_member ]
 !116 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"y", i32 15, i64 32, i64 32, i64 32, i32 0, metadata !76} ; [ DW_TAG_member ]
 !117 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"size", i32 31, i64 64, i64 32, i64 64, i32 0, metadata !118} ; [ DW_TAG_member ]
-!118 = metadata !{i32 786454, metadata !0, metadata !"Size", metadata !77, i32 25, i64 0, i64 0, i64 0, i32 0, metadata !119} ; [ DW_TAG_typedef ]
+!118 = metadata !{i32 786454, metadata !156, metadata !0, metadata !"Size", i32 25, i64 0, i64 0, i64 0, i32 0, metadata !119} ; [ DW_TAG_typedef ]
 !119 = metadata !{i32 786451, metadata !156, metadata !0, metadata !"Size", i32 21, i64 64, i64 32, i32 0, i32 0, i32 0, metadata !120, i32 0, i32 0} ; [ DW_TAG_structure_type ]
 !120 = metadata !{metadata !121, metadata !122}
 !121 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"width", i32 22, i64 32, i64 32, i64 0, i32 0, metadata !76} ; [ DW_TAG_member ]
 !122 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"height", i32 23, i64 32, i64 32, i64 32, i32 0, metadata !76} ; [ DW_TAG_member ]
 !123 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"_data", i32 40, i64 128, i64 32, i64 256, i32 1, metadata !108, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ]
 !124 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"semi", i32 609, i64 32, i64 32, i64 224, i32 0, metadata !125} ; [ DW_TAG_member ]
-!125 = metadata !{i32 786454, metadata !0, metadata !"d_t", metadata !24, i32 35, i64 0, i64 0, i64 0, i32 0, metadata !126} ; [ DW_TAG_typedef ]
+!125 = metadata !{i32 786454, metadata !152, metadata !0, metadata !"d_t", i32 35, i64 0, i64 0, i64 0, i32 0, metadata !126} ; [ DW_TAG_typedef ]
 !126 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !127} ; [ DW_TAG_pointer_type ]
 !127 = metadata !{i32 786451, metadata !159, metadata !0, metadata !"my_struct", i32 49, i64 0, i64 0, i32 0, i32 4, i32 0, null, i32 0, i32 0} ; [ DW_TAG_structure_type ]
 !128 = metadata !{i32 786473, metadata !159} ; [ DW_TAG_file_type ]
@@ -236,7 +236,7 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load
 !139 = metadata !{i32 786688, metadata !23, metadata !"semi", metadata !24, i32 607, metadata !125, i32 0, null, i64 1, i64 28} ; [ DW_TAG_auto_variable ]
 !140 = metadata !{i32 607, i32 30, metadata !23, null}
 !141 = metadata !{i32 610, i32 17, metadata !142, null}
-!142 = metadata !{i32 786443, metadata !23, i32 609, i32 200, metadata !24, i32 94} ; [ DW_TAG_lexical_block ]
+!142 = metadata !{i32 786443, metadata !152, metadata !23, i32 609, i32 200, i32 94} ; [ DW_TAG_lexical_block ]
 !143 = metadata !{i32 611, i32 17, metadata !142, null}
 !144 = metadata !{i32 612, i32 17, metadata !142, null}
 !145 = metadata !{i32 613, i32 17, metadata !142, null}
diff --git a/test/CodeGen/ARM/debug-info-branch-folding.ll b/test/CodeGen/ARM/debug-info-branch-folding.ll
index 38945ac..052fd22 100644
--- a/test/CodeGen/ARM/debug-info-branch-folding.ll
+++ b/test/CodeGen/ARM/debug-info-branch-folding.ll
@@ -5,8 +5,8 @@ target triple = "thumbv7-apple-macosx10.6.7"
 ;CHECK: 	vadd.f32	q4, q8, q8
 ;CHECK-NEXT: LBB0_1
 
-;CHECK:@DEBUG_VALUE: x <- Q4+0
-;CHECK-NEXT:@DEBUG_VALUE: y <- Q4+0
+;CHECK:@DEBUG_VALUE: x <- Q4{{$}}
+;CHECK-NEXT:@DEBUG_VALUE: y <- Q4{{$}}
 
 
 @.str = external constant [13 x i8]
@@ -38,21 +38,21 @@ declare i32 @printf(i8* nocapture, ...) nounwind
 
 declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
-!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"test0001", metadata !"test0001", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, <4 x float> (float)* @test0001, null, null, metadata !51, i32 0} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !54, null, metadata !"test0001", metadata !"test0001", metadata !"", i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, <4 x float> (float)* @test0001, null, null, metadata !51, i32 0} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !54} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, metadata !54, i32 12, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, null, null, metadata !50, null,  null, null} ; [ DW_TAG_compile_unit ]
+!2 = metadata !{i32 786449, metadata !54, i32 12, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, metadata !17, metadata !17, metadata !50, null,  null, null} ; [ DW_TAG_compile_unit ]
 !3 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
 !5 = metadata !{i32 786454, metadata !54, metadata !2, metadata !"v4f32", i32 14, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ]
-!6 = metadata !{i32 786691, metadata !2, metadata !"", metadata !2, i32 0, i64 128, i64 128, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_vector_type ]
+!6 = metadata !{i32 786433, metadata !54, metadata !2, metadata !"", i32 0, i64 128, i64 128, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_vector_type ]
 !7 = metadata !{i32 786468, null, metadata !2, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
 !8 = metadata !{metadata !9}
 !9 = metadata !{i32 786465, i64 0, i64 4}         ; [ DW_TAG_subrange_type ]
-!10 = metadata !{i32 786478, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 59, metadata !11, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**, i1)* @main, null, null, metadata !52, i32 0} ; [ DW_TAG_subprogram ]
+!10 = metadata !{i32 786478, metadata !54, null, metadata !"main", metadata !"main", metadata !"", i32 59, metadata !11, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**, i1)* @main, null, null, metadata !52, i32 0} ; [ DW_TAG_subprogram ]
 !11 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !12 = metadata !{metadata !13}
 !13 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!14 = metadata !{i32 786478, i32 0, metadata !15, metadata !"printFV", metadata !"printFV", metadata !"", metadata !15, i32 41, metadata !16, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null, null, null, metadata !53, i32 0} ; [ DW_TAG_subprogram ]
+!14 = metadata !{i32 786478, metadata !55, null, metadata !"printFV", metadata !"printFV", metadata !"", i32 41, metadata !16, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null, null, null, metadata !53, i32 0} ; [ DW_TAG_subprogram ]
 !15 = metadata !{i32 786473, metadata !55} ; [ DW_TAG_file_type ]
 !16 = metadata !{i32 786453, metadata !55, metadata !15, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !17, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !17 = metadata !{null}
diff --git a/test/CodeGen/ARM/debug-info-d16-reg.ll b/test/CodeGen/ARM/debug-info-d16-reg.ll
index e4040fa..11631ae 100644
--- a/test/CodeGen/ARM/debug-info-d16-reg.ll
+++ b/test/CodeGen/ARM/debug-info-d16-reg.ll
@@ -58,22 +58,22 @@ declare i32 @puts(i8* nocapture) nounwind
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"printer", metadata !"printer", metadata !"printer", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, double, i8)* @printer, null, null, metadata !43, i32 12} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !46, metadata !1, metadata !"printer", metadata !"printer", metadata !"printer", i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, double, i8)* @printer, null, null, metadata !43, i32 12} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !46} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"(LLVM build 00)", i1 true, metadata !"", i32 0, null, null, metadata !42, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 786449, metadata !46, i32 1, metadata !"(LLVM build 00)", i1 true, metadata !"", i32 0, metadata !47, metadata !47, metadata !42, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !46, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5, metadata !6, metadata !7, metadata !8}
-!5 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
-!7 = metadata !{i32 786468, metadata !1, metadata !"double", metadata !1, i32 0, i64 64, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
-!8 = metadata !{i32 786468, metadata !1, metadata !"unsigned char", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ]
-!9 = metadata !{i32 786478, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"inlineprinter", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, double, i8)* @inlineprinter, null, null, metadata !44, i32 5} ; [ DW_TAG_subprogram ]
-!10 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 18, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !45, i32 18} ; [ DW_TAG_subprogram ]
-!11 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!5 = metadata !{i32 786468, metadata !46, metadata !1, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786447, metadata !46, metadata !1, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
+!7 = metadata !{i32 786468, metadata !46, metadata !1, metadata !"double", i32 0, i64 64, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
+!8 = metadata !{i32 786468, metadata !46, metadata !1, metadata !"unsigned char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 786478, metadata !46, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"inlineprinter", i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, double, i8)* @inlineprinter, null, null, metadata !44, i32 5} ; [ DW_TAG_subprogram ]
+!10 = metadata !{i32 786478, metadata !46, metadata !1, metadata !"main", metadata !"main", metadata !"main", i32 18, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !45, i32 18} ; [ DW_TAG_subprogram ]
+!11 = metadata !{i32 786453, metadata !46, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !12 = metadata !{metadata !5, metadata !5, metadata !13}
-!13 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ]
-!14 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !15} ; [ DW_TAG_pointer_type ]
-!15 = metadata !{i32 786468, metadata !1, metadata !"char", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!13 = metadata !{i32 786447, metadata !46, metadata !1, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ]
+!14 = metadata !{i32 786447, metadata !46, metadata !1, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !15} ; [ DW_TAG_pointer_type ]
+!15 = metadata !{i32 786468, metadata !46, metadata !1, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !16 = metadata !{i32 786689, metadata !0, metadata !"ptr", metadata !1, i32 11, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ]
 !17 = metadata !{i32 786689, metadata !0, metadata !"val", metadata !1, i32 11, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ]
 !18 = metadata !{i32 786689, metadata !0, metadata !"c", metadata !1, i32 11, metadata !8, i32 0, null} ; [ DW_TAG_arg_variable ]
@@ -83,14 +83,14 @@ declare i32 @puts(i8* nocapture) nounwind
 !22 = metadata !{i32 786689, metadata !10, metadata !"argc", metadata !1, i32 17, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !23 = metadata !{i32 786689, metadata !10, metadata !"argv", metadata !1, i32 17, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ]
 !24 = metadata !{i32 786688, metadata !25, metadata !"dval", metadata !1, i32 19, metadata !7, i32 0, null} ; [ DW_TAG_auto_variable ]
-!25 = metadata !{i32 786443, metadata !1, metadata !10, i32 18, i32 0, i32 2} ; [ DW_TAG_lexical_block ]
+!25 = metadata !{i32 786443, metadata !46, metadata !10, i32 18, i32 0, i32 2} ; [ DW_TAG_lexical_block ]
 !26 = metadata !{i32 4, i32 0, metadata !9, null}
 !27 = metadata !{i32 6, i32 0, metadata !28, null}
-!28 = metadata !{i32 786443, metadata !1, metadata !9, i32 5, i32 0, i32 1} ; [ DW_TAG_lexical_block ]
+!28 = metadata !{i32 786443, metadata !46, metadata !9, i32 5, i32 0, i32 1} ; [ DW_TAG_lexical_block ]
 !29 = metadata !{i32 7, i32 0, metadata !28, null}
 !30 = metadata !{i32 11, i32 0, metadata !0, null}
 !31 = metadata !{i32 13, i32 0, metadata !32, null}
-!32 = metadata !{i32 786443, metadata !1, metadata !0, i32 12, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!32 = metadata !{i32 786443, metadata !46, metadata !0, i32 12, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !33 = metadata !{i32 14, i32 0, metadata !32, null}
 !34 = metadata !{i32 17, i32 0, metadata !10, null}
 !35 = metadata !{i32 19, i32 0, metadata !25, null}
@@ -105,3 +105,4 @@ declare i32 @puts(i8* nocapture) nounwind
 !44 = metadata !{metadata !19, metadata !20, metadata !21}
 !45 = metadata !{metadata !22, metadata !23, metadata !24}
 !46 = metadata !{metadata !"a.c", metadata !"/tmp/"}
+!47 = metadata !{i32 0}
diff --git a/test/CodeGen/ARM/debug-info-qreg.ll b/test/CodeGen/ARM/debug-info-qreg.ll
index 1de6ffa..af61f6c 100644
--- a/test/CodeGen/ARM/debug-info-qreg.ll
+++ b/test/CodeGen/ARM/debug-info-qreg.ll
@@ -37,21 +37,21 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"test0001", metadata !"test0001", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, <4 x float> (float)* @test0001, null, null, metadata !51, i32 3} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !54, metadata !1, metadata !"test0001", metadata !"test0001", metadata !"", i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, <4 x float> (float)* @test0001, null, null, metadata !51, i32 3} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !54} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, metadata !54, i32 12, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, null, null, metadata !50, null,  null, null} ; [ DW_TAG_compile_unit ]
+!2 = metadata !{i32 786449, metadata !54, i32 12, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, metadata !17, metadata !17, metadata !50, null,  null, null} ; [ DW_TAG_compile_unit ]
 !3 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
 !5 = metadata !{i32 786454, metadata !54, metadata !2, metadata !"v4f32", i32 14, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ]
-!6 = metadata !{i32 786691, metadata !2, metadata !"", metadata !2, i32 0, i64 128, i64 128, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_vector_type ]
+!6 = metadata !{i32 786433, metadata !2, metadata !"", metadata !2, i32 0, i64 128, i64 128, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_vector_type ]
 !7 = metadata !{i32 786468, null, metadata !2, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
 !8 = metadata !{metadata !9}
 !9 = metadata !{i32 786465, i64 0, i64 4}         ; [ DW_TAG_subrange_type ]
-!10 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 59, metadata !11, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !52, i32 59} ; [ DW_TAG_subprogram ]
+!10 = metadata !{i32 786478, metadata !54, metadata !1, metadata !"main", metadata !"main", metadata !"", i32 59, metadata !11, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !52, i32 59} ; [ DW_TAG_subprogram ]
 !11 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !12 = metadata !{metadata !13}
 !13 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!14 = metadata !{i32 786478, metadata !15, metadata !"printFV", metadata !"printFV", metadata !"", metadata !15, i32 41, metadata !16, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null, null, null, metadata !53, i32 41} ; [ DW_TAG_subprogram ]
+!14 = metadata !{i32 786478, metadata !55, metadata !15, metadata !"printFV", metadata !"printFV", metadata !"", i32 41, metadata !16, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null, null, null, metadata !53, i32 41} ; [ DW_TAG_subprogram ]
 !15 = metadata !{i32 786473, metadata !55} ; [ DW_TAG_file_type ]
 !16 = metadata !{i32 786453, metadata !55, metadata !15, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !17, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !17 = metadata !{null}
@@ -62,7 +62,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !22 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ]
 !23 = metadata !{i32 786468, null, metadata !2, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !24 = metadata !{i32 786688, metadata !25, metadata !"i", metadata !1, i32 60, metadata !13, i32 0, null} ; [ DW_TAG_auto_variable ]
-!25 = metadata !{i32 786443, metadata !1, metadata !10, i32 59, i32 33, i32 14} ; [ DW_TAG_lexical_block ]
+!25 = metadata !{i32 786443, metadata !54, metadata !10, i32 59, i32 33, i32 14} ; [ DW_TAG_lexical_block ]
 !26 = metadata !{i32 786688, metadata !25, metadata !"j", metadata !1, i32 60, metadata !13, i32 0, null} ; [ DW_TAG_auto_variable ]
 !27 = metadata !{i32 786688, metadata !25, metadata !"x", metadata !1, i32 61, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
 !28 = metadata !{i32 786688, metadata !25, metadata !"y", metadata !1, i32 62, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
@@ -77,14 +77,14 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !37 = metadata !{i32 786445, metadata !55, metadata !15, metadata !"A", i32 24, i64 128, i64 32, i64 0, i32 0, metadata !38} ; [ DW_TAG_member ]
 !38 = metadata !{i32 786433, null, metadata !2, metadata !"", i32 0, i64 128, i64 32, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_array_type ]
 !39 = metadata !{i32 79, i32 7, metadata !40, null}
-!40 = metadata !{i32 786443, metadata !1, metadata !41, i32 75, i32 35, i32 18} ; [ DW_TAG_lexical_block ]
-!41 = metadata !{i32 786443, metadata !1, metadata !42, i32 75, i32 5, i32 17} ; [ DW_TAG_lexical_block ]
-!42 = metadata !{i32 786443, metadata !1, metadata !43, i32 71, i32 32, i32 16} ; [ DW_TAG_lexical_block ]
-!43 = metadata !{i32 786443, metadata !1, metadata !25, i32 71, i32 3, i32 15} ; [ DW_TAG_lexical_block ]
+!40 = metadata !{i32 786443, metadata !54, metadata !41, i32 75, i32 35, i32 18} ; [ DW_TAG_lexical_block ]
+!41 = metadata !{i32 786443, metadata !54, metadata !42, i32 75, i32 5, i32 17} ; [ DW_TAG_lexical_block ]
+!42 = metadata !{i32 786443, metadata !54, metadata !43, i32 71, i32 32, i32 16} ; [ DW_TAG_lexical_block ]
+!43 = metadata !{i32 786443, metadata !54, metadata !25, i32 71, i32 3, i32 15} ; [ DW_TAG_lexical_block ]
 !44 = metadata !{i32 75, i32 5, metadata !42, null}
 !45 = metadata !{i32 42, i32 2, metadata !46, metadata !48}
-!46 = metadata !{i32 786443, metadata !15, metadata !47, i32 42, i32 2, i32 20} ; [ DW_TAG_lexical_block ]
-!47 = metadata !{i32 786443, metadata !15, metadata !14, i32 41, i32 28, i32 19} ; [ DW_TAG_lexical_block ]
+!46 = metadata !{i32 786443, metadata !55, metadata !47, i32 42, i32 2, i32 20} ; [ DW_TAG_lexical_block ]
+!47 = metadata !{i32 786443, metadata !55, metadata !14, i32 41, i32 28, i32 19} ; [ DW_TAG_lexical_block ]
 !48 = metadata !{i32 95, i32 3, metadata !25, null}
 !49 = metadata !{i32 99, i32 3, metadata !25, null}
 !50 = metadata !{metadata !0, metadata !10, metadata !14}
diff --git a/test/CodeGen/ARM/debug-info-s16-reg.ll b/test/CodeGen/ARM/debug-info-s16-reg.ll
index 1868942..83e7dac 100644
--- a/test/CodeGen/ARM/debug-info-s16-reg.ll
+++ b/test/CodeGen/ARM/debug-info-s16-reg.ll
@@ -63,41 +63,41 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i8*, float, i8)* @inlineprinter, null, null, metadata !48, i32 5} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !51, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"", i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i8*, float, i8)* @inlineprinter, null, null, metadata !48, i32 5} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !51} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, null, null, metadata !47, null,  null, null} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 786449, metadata !51, i32 12, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, metadata !52, metadata !52, metadata !47, null,  null, null} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !51, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 786478, metadata !1, metadata !"printer", metadata !"printer", metadata !"", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i8*, float, i8)* @printer, null, null, metadata !49, i32 12} ; [ DW_TAG_subprogram ]
-!7 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !50, i32 18} ; [ DW_TAG_subprogram ]
+!5 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786478, metadata !51, metadata !1, metadata !"printer", metadata !"printer", metadata !"", i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i8*, float, i8)* @printer, null, null, metadata !49, i32 12} ; [ DW_TAG_subprogram ]
+!7 = metadata !{i32 786478, metadata !51, metadata !1, metadata !"main", metadata !"main", metadata !"", i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !50, i32 18} ; [ DW_TAG_subprogram ]
 !8 = metadata !{i32 786689, metadata !0, metadata !"ptr", metadata !1, i32 16777220, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ]
-!9 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
+!9 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
 !10 = metadata !{i32 786689, metadata !0, metadata !"val", metadata !1, i32 33554436, metadata !11, i32 0, null} ; [ DW_TAG_arg_variable ]
-!11 = metadata !{i32 786468, metadata !2, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
+!11 = metadata !{i32 786468, null, metadata !2, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
 !12 = metadata !{i32 786689, metadata !0, metadata !"c", metadata !1, i32 50331652, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ]
-!13 = metadata !{i32 786468, metadata !2, metadata !"unsigned char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ]
+!13 = metadata !{i32 786468, null, metadata !2, metadata !"unsigned char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ]
 !14 = metadata !{i32 786689, metadata !6, metadata !"ptr", metadata !1, i32 16777227, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ]
 !15 = metadata !{i32 786689, metadata !6, metadata !"val", metadata !1, i32 33554443, metadata !11, i32 0, null} ; [ DW_TAG_arg_variable ]
 !16 = metadata !{i32 786689, metadata !6, metadata !"c", metadata !1, i32 50331659, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ]
 !17 = metadata !{i32 786689, metadata !7, metadata !"argc", metadata !1, i32 16777233, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !18 = metadata !{i32 786689, metadata !7, metadata !"argv", metadata !1, i32 33554449, metadata !19, i32 0, null} ; [ DW_TAG_arg_variable ]
-!19 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !20} ; [ DW_TAG_pointer_type ]
-!20 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !21} ; [ DW_TAG_pointer_type ]
-!21 = metadata !{i32 786468, metadata !2, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!19 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !20} ; [ DW_TAG_pointer_type ]
+!20 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !21} ; [ DW_TAG_pointer_type ]
+!21 = metadata !{i32 786468, null, metadata !2, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !22 = metadata !{i32 786688, metadata !23, metadata !"dval", metadata !1, i32 19, metadata !11, i32 0, null} ; [ DW_TAG_auto_variable ]
-!23 = metadata !{i32 786443, metadata !1, metadata !7, i32 18, i32 1, i32 2} ; [ DW_TAG_lexical_block ]
+!23 = metadata !{i32 786443, metadata !51, metadata !7, i32 18, i32 1, i32 2} ; [ DW_TAG_lexical_block ]
 !24 = metadata !{i32 4, i32 22, metadata !0, null}
 !25 = metadata !{i32 4, i32 33, metadata !0, null}
 !26 = metadata !{i32 4, i32 52, metadata !0, null}
 !27 = metadata !{i32 6, i32 3, metadata !28, null}
-!28 = metadata !{i32 786443, metadata !1, metadata !0, i32 5, i32 1, i32 0} ; [ DW_TAG_lexical_block ]
+!28 = metadata !{i32 786443, metadata !51, metadata !0, i32 5, i32 1, i32 0} ; [ DW_TAG_lexical_block ]
 !29 = metadata !{i32 7, i32 3, metadata !28, null}
 !30 = metadata !{i32 11, i32 42, metadata !6, null}
 !31 = metadata !{i32 11, i32 53, metadata !6, null}
 !32 = metadata !{i32 11, i32 72, metadata !6, null}
 !33 = metadata !{i32 13, i32 3, metadata !34, null}
-!34 = metadata !{i32 786443, metadata !1, metadata !6, i32 12, i32 1, i32 1} ; [ DW_TAG_lexical_block ]
+!34 = metadata !{i32 786443, metadata !51, metadata !6, i32 12, i32 1, i32 1} ; [ DW_TAG_lexical_block ]
 !35 = metadata !{i32 14, i32 3, metadata !34, null}
 !36 = metadata !{i32 17, i32 15, metadata !7, null}
 !37 = metadata !{i32 17, i32 28, metadata !7, null}
@@ -115,3 +115,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !49 = metadata !{metadata !14, metadata !15, metadata !16}
 !50 = metadata !{metadata !17, metadata !18, metadata !22}
 !51 = metadata !{metadata !"a.c", metadata !"/private/tmp"}
+!52 = metadata !{i32 0}
diff --git a/test/CodeGen/ARM/debug-info-sreg2.ll b/test/CodeGen/ARM/debug-info-sreg2.ll
index ba83f79..cc2e831 100644
--- a/test/CodeGen/ARM/debug-info-sreg2.ll
+++ b/test/CodeGen/ARM/debug-info-sreg2.ll
@@ -41,17 +41,17 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 4, metadata !2, metadata !"clang version 3.0 (trunk 130845)", i1 true, metadata !"", i32 0, null, null, metadata !16, null,  null, null} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3foov", metadata !2, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void ()* @_Z3foov, null, null, metadata !17, i32 5} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786449, metadata !18, i32 4, metadata !"clang version 3.0 (trunk 130845)", i1 true, metadata !"", i32 0, metadata !19, metadata !19, metadata !16, null,  null, null} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 786478, metadata !18, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3foov", i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void ()* @_Z3foov, null, null, metadata !17, i32 5} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !18} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!3 = metadata !{i32 786453, metadata !18, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{null}
 !5 = metadata !{i32 786688, metadata !6, metadata !"k", metadata !2, i32 6, metadata !7, i32 0, null} ; [ DW_TAG_auto_variable ]
-!6 = metadata !{i32 786443, metadata !2, metadata !1, i32 5, i32 12, i32 0} ; [ DW_TAG_lexical_block ]
-!7 = metadata !{i32 786468, metadata !0, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786443, metadata !18, metadata !1, i32 5, i32 12, i32 0} ; [ DW_TAG_lexical_block ]
+!7 = metadata !{i32 786468, null, metadata !0, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
 !8 = metadata !{i32 786688, metadata !9, metadata !"y", metadata !2, i32 8, metadata !7, i32 0, null} ; [ DW_TAG_auto_variable ]
-!9 = metadata !{i32 786443, metadata !2, metadata !10, i32 7, i32 25, i32 2} ; [ DW_TAG_lexical_block ]
-!10 = metadata !{i32 786443, metadata !2, metadata !6, i32 7, i32 3, i32 1} ; [ DW_TAG_lexical_block ]
+!9 = metadata !{i32 786443, metadata !18, metadata !10, i32 7, i32 25, i32 2} ; [ DW_TAG_lexical_block ]
+!10 = metadata !{i32 786443, metadata !18, metadata !6, i32 7, i32 3, i32 1} ; [ DW_TAG_lexical_block ]
 !11 = metadata !{i32 6, i32 18, metadata !6, null}
 !12 = metadata !{i32 7, i32 3, metadata !6, null}
 !13 = metadata !{i32 8, i32 20, metadata !9, null}
@@ -60,3 +60,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !16 = metadata !{metadata !1}
 !17 = metadata !{metadata !5, metadata !8}
 !18 = metadata !{metadata !"k.cc", metadata !"/private/tmp"}
+!19 = metadata !{i32 0}
diff --git a/test/CodeGen/ARM/divmod-eabi.ll b/test/CodeGen/ARM/divmod-eabi.ll
new file mode 100644
index 0000000..404cae0
--- /dev/null
+++ b/test/CodeGen/ARM/divmod-eabi.ll
@@ -0,0 +1,202 @@
+; RUN: llc -mtriple armv7-none-eabi %s -o - | FileCheck %s --check-prefix=EABI
+; RUN: llc -mtriple armv7-linux-gnueabi %s -o - | FileCheck %s --check-prefix=GNU
+; RUN: llc -mtriple armv7-apple-darwin %s -o - | FileCheck %s --check-prefix=DARWIN
+
+define signext i16 @f16(i16 signext %a, i16 signext %b) {
+; EABI-LABEL: f16:
+; GNU-LABEL: f16:
+; DARWIN-LABEL: f16:
+entry:
+  %conv = sext i16 %a to i32
+  %conv1 = sext i16 %b to i32
+  %div = sdiv i32 %conv, %conv1
+  %rem = srem i32 %conv, %conv1
+; EABI: __aeabi_idivmod
+; EABI: mov [[div:r[0-9]+]], r0
+; EABI: mov [[rem:r[0-9]+]], r1
+; GNU: __aeabi_idiv
+; GNU: mov [[sum:r[0-9]+]], r0
+; GNU: __modsi3
+; GNU: add [[sum]]{{.*}}r0
+; DARWIN: ___divsi3
+; DARWIN: mov [[sum:r[0-9]+]], r0
+; DARWIN: __modsi3
+; DARWIN: add [[sum]]{{.*}}r0
+  %rem8 = srem i32 %conv1, %conv
+; EABI: __aeabi_idivmod
+; GNU: __modsi3
+; DARWIN: __modsi3
+  %add = add nsw i32 %rem, %div
+  %add13 = add nsw i32 %add, %rem8
+  %conv14 = trunc i32 %add13 to i16
+; EABI: add r0{{.*}}r1
+; EABI: sxth r0, r0
+; GNU: add r0{{.*}}[[sum]]
+; GNU: sxth r0, r0
+; DARWIN: add r0{{.*}}[[sum]]
+; DARWIN: sxth r0, r0
+  ret i16 %conv14
+}
+
+define i32 @f32(i32 %a, i32 %b) {
+; EABI-LABEL: f32:
+; GNU-LABEL: f32:
+; DARWIN-LABEL: f32:
+entry:
+  %div = sdiv i32 %a, %b
+  %rem = srem i32 %a, %b
+; EABI: __aeabi_idivmod
+; EABI: mov [[div:r[0-9]+]], r0
+; EABI: mov [[rem:r[0-9]+]], r1
+; GNU: __aeabi_idiv
+; GNU: mov [[sum:r[0-9]+]], r0
+; GNU: __modsi3
+; GNU: add [[sum]]{{.*}}r0
+; DARWIN: ___divsi3
+; DARWIN: mov [[sum:r[0-9]+]], r0
+; DARWIN: __modsi3
+; DARWIN: add [[sum]]{{.*}}r0
+  %rem1 = srem i32 %b, %a
+; EABI: __aeabi_idivmod
+; GNU: __modsi3
+; DARWIN: __modsi3
+  %add = add nsw i32 %rem, %div
+  %add2 = add nsw i32 %add, %rem1
+; EABI: add r0{{.*}}r1
+; GNU: add r0{{.*}}[[sum]]
+; DARWIN: add r0{{.*}}[[sum]]
+  ret i32 %add2
+}
+
+define i32 @uf(i32 %a, i32 %b) {
+; EABI-LABEL: uf:
+; GNU-LABEL: uf:
+; DARWIN-LABEL: uf:
+entry:
+  %div = udiv i32 %a, %b
+  %rem = urem i32 %a, %b
+; EABI: __aeabi_uidivmod
+; GNU: __aeabi_uidiv
+; GNU: mov [[sum:r[0-9]+]], r0
+; GNU: __umodsi3
+; GNU: add [[sum]]{{.*}}r0
+; DARWIN: ___udivsi3
+; DARWIN: mov [[sum:r[0-9]+]], r0
+; DARWIN: __umodsi3
+; DARWIN: add [[sum]]{{.*}}r0
+  %rem1 = urem i32 %b, %a
+; EABI: __aeabi_uidivmod
+; GNU: __umodsi3
+; DARWIN: __umodsi3
+  %add = add nuw i32 %rem, %div
+  %add2 = add nuw i32 %add, %rem1
+; EABI: add r0{{.*}}r1
+; GNU: add r0{{.*}}[[sum]]
+; DARWIN: add r0{{.*}}[[sum]]
+  ret i32 %add2
+}
+
+; FIXME: AEABI is not lowering long u/srem into u/ldivmod
+define i64 @longf(i64 %a, i64 %b) {
+; EABI-LABEL: longf:
+; GNU-LABEL: longf:
+; DARWIN-LABEL: longf:
+entry:
+  %div = sdiv i64 %a, %b
+  %rem = srem i64 %a, %b
+; EABI: __aeabi_ldivmod
+; GNU: __aeabi_ldivmod
+; GNU: mov [[div1:r[0-9]+]], r0
+; GNU: mov [[div2:r[0-9]+]], r1
+; DARWIN: ___divdi3
+; DARWIN: mov [[div1:r[0-9]+]], r0
+; DARWIN: mov [[div2:r[0-9]+]], r1
+; DARWIN: __moddi3
+  %add = add nsw i64 %rem, %div
+; GNU: adds r0{{.*}}[[div1]]
+; GNU: adc r1{{.*}}[[div2]]
+; DARWIN: adds r0{{.*}}[[div1]]
+; DARWIN: adc r1{{.*}}[[div2]]
+  ret i64 %add
+}
+
+define i32 @g1(i32 %a, i32 %b) {
+; EABI-LABEL: g1:
+; GNU-LABEL: g1:
+; DARWIN-LABEL: g1:
+entry:
+  %div = sdiv i32 %a, %b
+  %rem = srem i32 %a, %b
+; EABI: __aeabi_idivmod
+; GNU: __aeabi_idiv
+; GNU: mov [[sum:r[0-9]+]], r0
+; GNU: __modsi3
+; DARWIN: ___divsi3
+; DARWIN: mov [[sum:r[0-9]+]], r0
+; DARWIN: __modsi3
+  %add = add nsw i32 %rem, %div
+; EABI:	add	r0{{.*}}r1
+; GNU: add r0{{.*}}[[sum]]
+; DARWIN: add r0{{.*}}[[sum]]
+  ret i32 %add
+}
+
+; On both Darwin and Gnu, this is just a call to __modsi3
+define i32 @g2(i32 %a, i32 %b) {
+; EABI-LABEL: g2:
+; GNU-LABEL: g2:
+; DARWIN-LABEL: g2:
+entry:
+  %rem = srem i32 %a, %b
+; EABI: __aeabi_idivmod
+; GNU: __modsi3
+; DARWIN: __modsi3
+  ret i32 %rem
+; EABI:	mov	r0, r1
+}
+
+define i32 @g3(i32 %a, i32 %b) {
+; EABI-LABEL: g3:
+; GNU-LABEL: g3:
+; DARWIN-LABEL: g3:
+entry:
+  %rem = srem i32 %a, %b
+; EABI: __aeabi_idivmod
+; EABI: mov [[mod:r[0-9]+]], r1
+; GNU: __modsi3
+; GNU: mov [[sum:r[0-9]+]], r0
+; DARWIN: __modsi3
+; DARWIN: mov [[sum:r[0-9]+]], r0
+  %rem1 = srem i32 %b, %rem
+; EABI: __aeabi_idivmod
+; GNU: __modsi3
+; DARWIN: __modsi3
+  %add = add nsw i32 %rem1, %rem
+; EABI: add r0, r1, [[mod]]
+; GNU: add r0{{.*}}[[sum]]
+; DARWIN: add r0{{.*}}[[sum]]
+  ret i32 %add
+}
+
+define i32 @g4(i32 %a, i32 %b) {
+; EABI-LABEL: g4:
+; GNU-LABEL: g4:
+; DARWIN-LABEL: g4:
+entry:
+  %div = sdiv i32 %a, %b
+; EABI: __aeabi_idivmod
+; EABI: mov [[div:r[0-9]+]], r0
+; GNU __aeabi_idiv
+; GNU: mov [[sum:r[0-9]+]], r0
+; DARWIN: ___divsi3
+; DARWIN: mov [[sum:r[0-9]+]], r0
+  %rem = srem i32 %b, %div
+; EABI: __aeabi_idivmod
+; GNU: __modsi3
+; DARWIN: __modsi3
+  %add = add nsw i32 %rem, %div
+; EABI: add r0, r1, [[div]]
+; GNU: add r0{{.*}}[[sum]]
+; DARWIN: add r0{{.*}}[[sum]]
+  ret i32 %add
+}
diff --git a/test/CodeGen/ARM/divmod.ll b/test/CodeGen/ARM/divmod.ll
index 577f8aa..06d6172 100644
--- a/test/CodeGen/ARM/divmod.ll
+++ b/test/CodeGen/ARM/divmod.ll
@@ -5,11 +5,11 @@
 
 define void @foo(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp {
 entry:
-; A8: foo:
+; A8-LABEL: foo:
 ; A8: bl ___divmodsi4
 ; A8-NOT: bl ___divmodsi4
 
-; SWIFT: foo:
+; SWIFT-LABEL: foo:
 ; SWIFT: sdiv
 ; SWIFT: mls
 ; SWIFT-NOT: bl __divmodsi4
@@ -23,11 +23,11 @@ entry:
 
 define void @bar(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp {
 entry:
-; A8: bar:
+; A8-LABEL: bar:
 ; A8: bl ___udivmodsi4
 ; A8-NOT: bl ___udivmodsi4
 
-; SWIFT: bar:
+; SWIFT-LABEL: bar:
 ; SWIFT: udiv
 ; SWIFT: mls
 ; SWIFT-NOT: bl __udivmodsi4
@@ -45,8 +45,8 @@ entry:
 
 define void @do_indent(i32 %cols) nounwind {
 entry:
-; A8: do_indent:
-; SWIFT: do_indent:
+; A8-LABEL: do_indent:
+; SWIFT-LABEL: do_indent:
   %0 = load i32* @flags, align 4
   %1 = and i32 %0, 67108864
   %2 = icmp eq i32 %1, 0
@@ -77,11 +77,11 @@ declare i8* @__memset_chk(i8*, i32, i32, i32) nounwind
 ; rdar://11714607
 define i32 @howmany(i32 %x, i32 %y) nounwind {
 entry:
-; A8: howmany:
+; A8-LABEL: howmany:
 ; A8: bl ___udivmodsi4
 ; A8-NOT: ___udivsi3
 
-; SWIFT: howmany:
+; SWIFT-LABEL: howmany:
 ; SWIFT: udiv
 ; SWIFT: mls
 ; SWIFT-NOT: bl __udivmodsi4
diff --git a/test/CodeGen/ARM/domain-conv-vmovs.ll b/test/CodeGen/ARM/domain-conv-vmovs.ll
index b5586cc..d6528db 100644
--- a/test/CodeGen/ARM/domain-conv-vmovs.ll
+++ b/test/CodeGen/ARM/domain-conv-vmovs.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a9 -mattr=+neon,+neonfp -float-abi=hard < %s | FileCheck %s
 
 define <2 x float> @test_vmovs_via_vext_lane0to0(float %arg, <2 x float> %in) {
-; CHECK: test_vmovs_via_vext_lane0to0:
+; CHECK-LABEL: test_vmovs_via_vext_lane0to0:
   %vec = insertelement <2 x float> %in, float %arg, i32 0
   %res = fadd <2 x float> %vec, %vec
 
@@ -13,7 +13,7 @@ define <2 x float> @test_vmovs_via_vext_lane0to0(float %arg, <2 x float> %in) {
 }
 
 define <2 x float> @test_vmovs_via_vext_lane0to1(float %arg, <2 x float> %in) {
-; CHECK: test_vmovs_via_vext_lane0to1:
+; CHECK-LABEL: test_vmovs_via_vext_lane0to1:
   %vec = insertelement <2 x float> %in, float %arg, i32 1
   %res = fadd <2 x float> %vec, %vec
 
@@ -25,7 +25,7 @@ define <2 x float> @test_vmovs_via_vext_lane0to1(float %arg, <2 x float> %in) {
 }
 
 define <2 x float> @test_vmovs_via_vext_lane1to0(float, float %arg, <2 x float> %in) {
-; CHECK: test_vmovs_via_vext_lane1to0:
+; CHECK-LABEL: test_vmovs_via_vext_lane1to0:
   %vec = insertelement <2 x float> %in, float %arg, i32 0
   %res = fadd <2 x float> %vec, %vec
 
@@ -37,7 +37,7 @@ define <2 x float> @test_vmovs_via_vext_lane1to0(float, float %arg, <2 x float>
 }
 
 define <2 x float> @test_vmovs_via_vext_lane1to1(float, float %arg, <2 x float> %in) {
-; CHECK: test_vmovs_via_vext_lane1to1:
+; CHECK-LABEL: test_vmovs_via_vext_lane1to1:
   %vec = insertelement <2 x float> %in, float %arg, i32 1
   %res = fadd <2 x float> %vec, %vec
 
@@ -50,7 +50,7 @@ define <2 x float> @test_vmovs_via_vext_lane1to1(float, float %arg, <2 x float>
 
 
 define float @test_vmovs_via_vdup(float, float %ret, float %lhs, float %rhs) {
-; CHECK: test_vmovs_via_vdup:
+; CHECK-LABEL: test_vmovs_via_vdup:
 
   ; Do an operation (which will end up NEON because of +neonfp) to convince the
   ; execution-domain pass that NEON is a good thing to use.
@@ -68,7 +68,7 @@ declare void @bar()
 
 ; This is a comp
 define float @test_ineligible(float, float %in) {
-; CHECK: test_ineligible:
+; CHECK-LABEL: test_ineligible:
 
   %sqrt = call float @llvm.sqrt.f32(float %in)
   %val = fadd float %sqrt, %sqrt
@@ -85,7 +85,7 @@ define float @test_ineligible(float, float %in) {
 }
 
 define i32 @test_vmovs_no_sreg(i32 %in) {
-; CHECK: test_vmovs_no_sreg:
+; CHECK-LABEL: test_vmovs_no_sreg:
 
   ; Check that the movement to and from GPRs takes place in the NEON domain.
 ; CHECK: vmov.32 d
diff --git a/test/CodeGen/ARM/eh-dispcont.ll b/test/CodeGen/ARM/eh-dispcont.ll
index 935965b..57ab15f 100644
--- a/test/CodeGen/ARM/eh-dispcont.ll
+++ b/test/CodeGen/ARM/eh-dispcont.ll
@@ -65,10 +65,10 @@ attributes #2 = { noreturn }
 
 ; THUMB1-PIC: cxa_throw
 ; THUMB1-PIC: trap
-; THUMB1-PIC: adr [[REG0:r[0-9]+]], [[LJTI:.*]]
-; THUMB1-PIC: adds [[REG1:r[0-9]+]], [[REG1]], [[REG0]]
-; THUMB1-PIC: ldr [[REG1]]
-; THUMB1-PIC: adds [[REG0]], [[REG1]], [[REG0]]
+; THUMB1-PIC: adr [[REG1:r[0-9]+]], [[LJTI:.*]]
+; THUMB1-PIC: adds [[REG0:r[0-9]+]], [[REG0]], [[REG1]]
+; THUMB1-PIC: ldr [[REG0]]
+; THUMB1-PIC: adds [[REG0]], [[REG0]], [[REG1]]
 ; THUMB1-PIC: mov pc, [[REG0]]
 ; THUMB1-PIC: [[LJTI]]
 ; THUMB1-PIC: .data_region jt32
diff --git a/test/CodeGen/ARM/ehabi-filters.ll b/test/CodeGen/ARM/ehabi-filters.ll
index 4c92a29..cb5291b 100644
--- a/test/CodeGen/ARM/ehabi-filters.ll
+++ b/test/CodeGen/ARM/ehabi-filters.ll
@@ -15,7 +15,7 @@ declare void @__cxa_throw(i8*, i8*, i8*)
 declare void @__cxa_call_unexpected(i8*)
 
 define i32 @main() {
-; CHECK: main:
+; CHECK-LABEL: main:
 entry:
   %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind
   %0 = bitcast i8* %exception.i to i32*
diff --git a/test/CodeGen/ARM/ehabi.ll b/test/CodeGen/ARM/ehabi.ll
index b05d4be..6644652 100644
--- a/test/CodeGen/ARM/ehabi.ll
+++ b/test/CodeGen/ARM/ehabi.ll
@@ -112,7 +112,7 @@ declare void @__cxa_end_catch()
 
 declare void @_ZSt9terminatev()
 
-; CHECK-FP: _Z4testiiiiiddddd:
+; CHECK-FP-LABEL: _Z4testiiiiiddddd:
 ; CHECK-FP:   .fnstart
 ; CHECK-FP:   .save  {r4, r5, r6, r7, r8, r9, r10, r11, lr}
 ; CHECK-FP:   push   {r4, r5, r6, r7, r8, r9, r10, r11, lr}
@@ -124,7 +124,7 @@ declare void @_ZSt9terminatev()
 ; CHECK-FP:   .handlerdata
 ; CHECK-FP:   .fnend
 
-; CHECK-FP-ELIM: _Z4testiiiiiddddd:
+; CHECK-FP-ELIM-LABEL: _Z4testiiiiiddddd:
 ; CHECK-FP-ELIM:   .fnstart
 ; CHECK-FP-ELIM:   .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
 ; CHECK-FP-ELIM:   push  {r4, r5, r6, r7, r8, r9, r10, r11, lr}
@@ -134,7 +134,7 @@ declare void @_ZSt9terminatev()
 ; CHECK-FP-ELIM:   .handlerdata
 ; CHECK-FP-ELIM:   .fnend
 
-; CHECK-V7-FP: _Z4testiiiiiddddd:
+; CHECK-V7-FP-LABEL: _Z4testiiiiiddddd:
 ; CHECK-V7-FP:   .fnstart
 ; CHECK-V7-FP:   .save  {r4, r11, lr}
 ; CHECK-V7-FP:   push   {r4, r11, lr}
@@ -148,7 +148,7 @@ declare void @_ZSt9terminatev()
 ; CHECK-V7-FP:   .handlerdata
 ; CHECK-V7-FP:   .fnend
 
-; CHECK-V7-FP-ELIM: _Z4testiiiiiddddd:
+; CHECK-V7-FP-ELIM-LABEL: _Z4testiiiiiddddd:
 ; CHECK-V7-FP-ELIM:   .fnstart
 ; CHECK-V7-FP-ELIM:   .save  {r4, lr}
 ; CHECK-V7-FP-ELIM:   push   {r4, lr}
@@ -173,7 +173,7 @@ entry:
   ret void
 }
 
-; CHECK-FP: test2:
+; CHECK-FP-LABEL: test2:
 ; CHECK-FP:   .fnstart
 ; CHECK-FP:   .save  {r11, lr}
 ; CHECK-FP:   push   {r11, lr}
@@ -183,7 +183,7 @@ entry:
 ; CHECK-FP:   mov    pc, lr
 ; CHECK-FP:   .fnend
 
-; CHECK-FP-ELIM: test2:
+; CHECK-FP-ELIM-LABEL: test2:
 ; CHECK-FP-ELIM:   .fnstart
 ; CHECK-FP-ELIM:   .save {r11, lr}
 ; CHECK-FP-ELIM:   push  {r11, lr}
@@ -191,7 +191,7 @@ entry:
 ; CHECK-FP-ELIM:   mov   pc, lr
 ; CHECK-FP-ELIM:   .fnend
 
-; CHECK-V7-FP: test2:
+; CHECK-V7-FP-LABEL: test2:
 ; CHECK-V7-FP:   .fnstart
 ; CHECK-V7-FP:   .save  {r11, lr}
 ; CHECK-V7-FP:   push   {r11, lr}
@@ -200,7 +200,7 @@ entry:
 ; CHECK-V7-FP:   pop    {r11, pc}
 ; CHECK-V7-FP:   .fnend
 
-; CHECK-V7-FP-ELIM: test2:
+; CHECK-V7-FP-ELIM-LABEL: test2:
 ; CHECK-V7-FP-ELIM:   .fnstart
 ; CHECK-V7-FP-ELIM:   .save {r11, lr}
 ; CHECK-V7-FP-ELIM:   push  {r11, lr}
@@ -229,7 +229,7 @@ entry:
   ret i32 %add6
 }
 
-; CHECK-FP: test3:
+; CHECK-FP-LABEL: test3:
 ; CHECK-FP:   .fnstart
 ; CHECK-FP:   .save  {r4, r5, r11, lr}
 ; CHECK-FP:   push   {r4, r5, r11, lr}
@@ -239,7 +239,7 @@ entry:
 ; CHECK-FP:   mov    pc, lr
 ; CHECK-FP:   .fnend
 
-; CHECK-FP-ELIM: test3:
+; CHECK-FP-ELIM-LABEL: test3:
 ; CHECK-FP-ELIM:   .fnstart
 ; CHECK-FP-ELIM:   .save {r4, r5, r11, lr}
 ; CHECK-FP-ELIM:   push  {r4, r5, r11, lr}
@@ -247,7 +247,7 @@ entry:
 ; CHECK-FP-ELIM:   mov   pc, lr
 ; CHECK-FP-ELIM:   .fnend
 
-; CHECK-V7-FP: test3:
+; CHECK-V7-FP-LABEL: test3:
 ; CHECK-V7-FP:   .fnstart
 ; CHECK-V7-FP:   .save  {r4, r5, r11, lr}
 ; CHECK-V7-FP:   push   {r4, r5, r11, lr}
@@ -256,7 +256,7 @@ entry:
 ; CHECK-V7-FP:   pop    {r4, r5, r11, pc}
 ; CHECK-V7-FP:   .fnend
 
-; CHECK-V7-FP-ELIM: test3:
+; CHECK-V7-FP-ELIM-LABEL: test3:
 ; CHECK-V7-FP-ELIM:   .fnstart
 ; CHECK-V7-FP-ELIM:   .save {r4, r5, r11, lr}
 ; CHECK-V7-FP-ELIM:   push  {r4, r5, r11, lr}
@@ -273,25 +273,25 @@ entry:
   ret void
 }
 
-; CHECK-FP: test4:
+; CHECK-FP-LABEL: test4:
 ; CHECK-FP:   .fnstart
 ; CHECK-FP:   mov pc, lr
 ; CHECK-FP:   .cantunwind
 ; CHECK-FP:   .fnend
 
-; CHECK-FP-ELIM: test4:
+; CHECK-FP-ELIM-LABEL: test4:
 ; CHECK-FP-ELIM:   .fnstart
 ; CHECK-FP-ELIM:   mov pc, lr
 ; CHECK-FP-ELIM:   .cantunwind
 ; CHECK-FP-ELIM:   .fnend
 
-; CHECK-V7-FP: test4:
+; CHECK-V7-FP-LABEL: test4:
 ; CHECK-V7-FP:   .fnstart
 ; CHECK-V7-FP:   bx lr
 ; CHECK-V7-FP:   .cantunwind
 ; CHECK-V7-FP:   .fnend
 
-; CHECK-V7-FP-ELIM: test4:
+; CHECK-V7-FP-ELIM-LABEL: test4:
 ; CHECK-V7-FP-ELIM:   .fnstart
 ; CHECK-V7-FP-ELIM:   bx lr
 ; CHECK-V7-FP-ELIM:   .cantunwind
diff --git a/test/CodeGen/ARM/extload-knownzero.ll b/test/CodeGen/ARM/extload-knownzero.ll
index 8fd6b6b..8ccf58c 100644
--- a/test/CodeGen/ARM/extload-knownzero.ll
+++ b/test/CodeGen/ARM/extload-knownzero.ll
@@ -3,7 +3,7 @@
 
 define void @foo(i16* %ptr, i32 %a) nounwind {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
   %tmp1 = icmp ult i32 %a, 100
   br i1 %tmp1, label %bb1, label %bb2
 bb1:
diff --git a/test/CodeGen/ARM/fabs-neon.ll b/test/CodeGen/ARM/fabs-neon.ll
index 614117f..e3094aa 100644
--- a/test/CodeGen/ARM/fabs-neon.ll
+++ b/test/CodeGen/ARM/fabs-neon.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=armv7-eabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s
 
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK:         vabs.f32        q0, q0
 define <4 x float> @test(<4 x float> %a) {
   %foo = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
@@ -8,7 +8,7 @@ define <4 x float> @test(<4 x float> %a) {
 }
 declare <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK:        vabs.f32        d0, d0
 define <2 x float> @test2(<2 x float> %a) {
   %foo = call <2 x float> @llvm.fabs.v2f32(<2 x float> %a)
diff --git a/test/CodeGen/ARM/fabss.ll b/test/CodeGen/ARM/fabss.ll
index c3e00ce..77c21c5 100644
--- a/test/CodeGen/ARM/fabss.ll
+++ b/test/CodeGen/ARM/fabss.ll
@@ -13,17 +13,17 @@ entry:
 
 declare float @fabsf(float)
 
-; VFP2: test:
+; VFP2-LABEL: test:
 ; VFP2: 	vabs.f32	s
 
-; NFP1: test:
+; NFP1-LABEL: test:
 ; NFP1: 	vabs.f32	d
-; NFP0: test:
+; NFP0-LABEL: test:
 ; NFP0: 	vabs.f32	s
 
-; CORTEXA8: test:
+; CORTEXA8-LABEL: test:
 ; CORTEXA8:     vadd.f32        [[D1:d[0-9]+]]
 ; CORTEXA8: 	vabs.f32	{{d[0-9]+}}, [[D1]]
 
-; CORTEXA9: test:
+; CORTEXA9-LABEL: test:
 ; CORTEXA9: 	vabs.f32	s{{.}}, s{{.}}
diff --git a/test/CodeGen/ARM/fadds.ll b/test/CodeGen/ARM/fadds.ll
index c7e2f5d..21219ce 100644
--- a/test/CodeGen/ARM/fadds.ll
+++ b/test/CodeGen/ARM/fadds.ll
@@ -11,17 +11,17 @@ entry:
 	ret float %0
 }
 
-; VFP2: test:
+; VFP2-LABEL: test:
 ; VFP2: 	vadd.f32	s
 
-; NFP1: test:
+; NFP1-LABEL: test:
 ; NFP1: 	vadd.f32	d
-; NFP0: test:
+; NFP0-LABEL: test:
 ; NFP0: 	vadd.f32	s
 
-; CORTEXA8: test:
+; CORTEXA8-LABEL: test:
 ; CORTEXA8: 	vadd.f32	s
-; CORTEXA8U: test:
+; CORTEXA8U-LABEL: test:
 ; CORTEXA8U: 	vadd.f32	d
-; CORTEXA9: test:
+; CORTEXA9-LABEL: test:
 ; CORTEXA9: 	vadd.f32	s
diff --git a/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll b/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll
index 28a84e3..05a6bab 100644
--- a/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll
+++ b/test/CodeGen/ARM/fast-isel-GEP-coalesce.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
 
 %struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] }
diff --git a/test/CodeGen/ARM/fast-isel-binary.ll b/test/CodeGen/ARM/fast-isel-binary.ll
index 723383e..3159627 100644
--- a/test/CodeGen/ARM/fast-isel-binary.ll
+++ b/test/CodeGen/ARM/fast-isel-binary.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 ; Test add with non-legal types
diff --git a/test/CodeGen/ARM/fast-isel-br-const.ll b/test/CodeGen/ARM/fast-isel-br-const.ll
index aefe200..2e28b08 100644
--- a/test/CodeGen/ARM/fast-isel-br-const.ll
+++ b/test/CodeGen/ARM/fast-isel-br-const.ll
@@ -1,10 +1,11 @@
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp {
 entry:
-; THUMB: t1:
-; ARM: t1:
+; THUMB-LABEL: t1:
+; ARM-LABEL: t1:
   %x = add i32 %a, %b  
   br i1 1, label %if.then, label %if.else
 ; THUMB-NOT: b {{\.?}}LBB0_1
diff --git a/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll b/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll
index 46d5f99..da829e9 100644
--- a/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll
+++ b/test/CodeGen/ARM/fast-isel-call-multi-reg-return.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 ; Fast-isel can't handle non-double multi-reg retvals.
diff --git a/test/CodeGen/ARM/fast-isel-call.ll b/test/CodeGen/ARM/fast-isel-call.ll
index f4a5d99..d10a381 100644
--- a/test/CodeGen/ARM/fast-isel-call.ll
+++ b/test/CodeGen/ARM/fast-isel-call.ll
@@ -1,8 +1,11 @@
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP
 
 ; Note that some of these tests assume that relocations are either
@@ -89,7 +92,7 @@ declare signext i8 @t7();
 declare zeroext i8 @t8();
 declare zeroext i1 @t9();
 
-define i32 @t10(i32 %argc, i8** nocapture %argv) {
+define i32 @t10() {
 entry:
 ; ARM: @t10
 ; ARM: movw [[R0:l?r[0-9]*]], #0
diff --git a/test/CodeGen/ARM/fast-isel-cmp-imm.ll b/test/CodeGen/ARM/fast-isel-cmp-imm.ll
index 660156a..45ef4ed 100644
--- a/test/CodeGen/ARM/fast-isel-cmp-imm.ll
+++ b/test/CodeGen/ARM/fast-isel-cmp-imm.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 define void @t1a(float %a) uwtable ssp {
diff --git a/test/CodeGen/ARM/fast-isel-conversion.ll b/test/CodeGen/ARM/fast-isel-conversion.ll
index 94654f3..e40891a 100644
--- a/test/CodeGen/ARM/fast-isel-conversion.ll
+++ b/test/CodeGen/ARM/fast-isel-conversion.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 ; Test sitofp
diff --git a/test/CodeGen/ARM/fast-isel-crash.ll b/test/CodeGen/ARM/fast-isel-crash.ll
index 7d45fef..ec9cf8d 100644
--- a/test/CodeGen/ARM/fast-isel-crash.ll
+++ b/test/CodeGen/ARM/fast-isel-crash.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-darwin
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-linux-gnueabi
 
 %union.anon = type { <16 x i32> }
 
diff --git a/test/CodeGen/ARM/fast-isel-crash2.ll b/test/CodeGen/ARM/fast-isel-crash2.ll
index 8867f87..d606877 100644
--- a/test/CodeGen/ARM/fast-isel-crash2.ll
+++ b/test/CodeGen/ARM/fast-isel-crash2.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-apple-darwin
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=thumbv7-linux-gnueabi
 ; rdar://9515076
 ; (Make sure this doesn't crash.)
 
diff --git a/test/CodeGen/ARM/fast-isel-ext.ll b/test/CodeGen/ARM/fast-isel-ext.ll
index cb6e9ba..15d0d3c 100644
--- a/test/CodeGen/ARM/fast-isel-ext.ll
+++ b/test/CodeGen/ARM/fast-isel-ext.ll
@@ -1,6 +1,9 @@
 ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=v7
+; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=v7
 ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-apple-ios | FileCheck %s --check-prefix=prev6
+; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-linux-gnueabi | FileCheck %s --check-prefix=prev6
 ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-apple-ios | FileCheck %s --check-prefix=prev6
+; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-linux-gnueabi | FileCheck %s --check-prefix=prev6
 ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=v7
 
 ; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports
@@ -14,54 +17,54 @@
 ; zext
 
 define i8 @zext_1_8(i1 %a) nounwind ssp {
-; v7: zext_1_8:
+; v7-LABEL: zext_1_8:
 ; v7: and r0, r0, #1
-; prev6: zext_1_8:
+; prev6-LABEL: zext_1_8:
 ; prev6: and r0, r0, #1
   %r = zext i1 %a to i8
   ret i8 %r
 }
 
 define i16 @zext_1_16(i1 %a) nounwind ssp {
-; v7: zext_1_16:
+; v7-LABEL: zext_1_16:
 ; v7: and r0, r0, #1
-; prev6: zext_1_16:
+; prev6-LABEL: zext_1_16:
 ; prev6: and r0, r0, #1
   %r = zext i1 %a to i16
   ret i16 %r
 }
 
 define i32 @zext_1_32(i1 %a) nounwind ssp {
-; v7: zext_1_32:
+; v7-LABEL: zext_1_32:
 ; v7: and r0, r0, #1
-; prev6: zext_1_32:
+; prev6-LABEL: zext_1_32:
 ; prev6: and r0, r0, #1
   %r = zext i1 %a to i32
   ret i32 %r
 }
 
 define i16 @zext_8_16(i8 %a) nounwind ssp {
-; v7: zext_8_16:
+; v7-LABEL: zext_8_16:
 ; v7: and r0, r0, #255
-; prev6: zext_8_16:
+; prev6-LABEL: zext_8_16:
 ; prev6: and r0, r0, #255
   %r = zext i8 %a to i16
   ret i16 %r
 }
 
 define i32 @zext_8_32(i8 %a) nounwind ssp {
-; v7: zext_8_32:
+; v7-LABEL: zext_8_32:
 ; v7: and r0, r0, #255
-; prev6: zext_8_32:
+; prev6-LABEL: zext_8_32:
 ; prev6: and r0, r0, #255
   %r = zext i8 %a to i32
   ret i32 %r
 }
 
 define i32 @zext_16_32(i16 %a) nounwind ssp {
-; v7: zext_16_32:
+; v7-LABEL: zext_16_32:
 ; v7: uxth r0, r0
-; prev6: zext_16_32:
+; prev6-LABEL: zext_16_32:
 ; prev6: lsl{{s?}} r0, r0, #16
 ; prev6: lsr{{s?}} r0, r0, #16
   %r = zext i16 %a to i32
@@ -71,10 +74,10 @@ define i32 @zext_16_32(i16 %a) nounwind ssp {
 ; sext
 
 define i8 @sext_1_8(i1 %a) nounwind ssp {
-; v7: sext_1_8:
+; v7-LABEL: sext_1_8:
 ; v7: lsl{{s?}} r0, r0, #31
 ; v7: asr{{s?}} r0, r0, #31
-; prev6: sext_1_8:
+; prev6-LABEL: sext_1_8:
 ; prev6: lsl{{s?}} r0, r0, #31
 ; prev6: asr{{s?}} r0, r0, #31
   %r = sext i1 %a to i8
@@ -82,10 +85,10 @@ define i8 @sext_1_8(i1 %a) nounwind ssp {
 }
 
 define i16 @sext_1_16(i1 %a) nounwind ssp {
-; v7: sext_1_16:
+; v7-LABEL: sext_1_16:
 ; v7: lsl{{s?}} r0, r0, #31
 ; v7: asr{{s?}} r0, r0, #31
-; prev6: sext_1_16:
+; prev6-LABEL: sext_1_16:
 ; prev6: lsl{{s?}} r0, r0, #31
 ; prev6: asr{{s?}} r0, r0, #31
   %r = sext i1 %a to i16
@@ -93,10 +96,10 @@ define i16 @sext_1_16(i1 %a) nounwind ssp {
 }
 
 define i32 @sext_1_32(i1 %a) nounwind ssp {
-; v7: sext_1_32:
+; v7-LABEL: sext_1_32:
 ; v7: lsl{{s?}} r0, r0, #31
 ; v7: asr{{s?}} r0, r0, #31
-; prev6: sext_1_32:
+; prev6-LABEL: sext_1_32:
 ; prev6: lsl{{s?}} r0, r0, #31
 ; prev6: asr{{s?}} r0, r0, #31
   %r = sext i1 %a to i32
@@ -104,9 +107,9 @@ define i32 @sext_1_32(i1 %a) nounwind ssp {
 }
 
 define i16 @sext_8_16(i8 %a) nounwind ssp {
-; v7: sext_8_16:
+; v7-LABEL: sext_8_16:
 ; v7: sxtb r0, r0
-; prev6: sext_8_16:
+; prev6-LABEL: sext_8_16:
 ; prev6: lsl{{s?}} r0, r0, #24
 ; prev6: asr{{s?}} r0, r0, #24
   %r = sext i8 %a to i16
@@ -114,9 +117,9 @@ define i16 @sext_8_16(i8 %a) nounwind ssp {
 }
 
 define i32 @sext_8_32(i8 %a) nounwind ssp {
-; v7: sext_8_32:
+; v7-LABEL: sext_8_32:
 ; v7: sxtb r0, r0
-; prev6: sext_8_32:
+; prev6-LABEL: sext_8_32:
 ; prev6: lsl{{s?}} r0, r0, #24
 ; prev6: asr{{s?}} r0, r0, #24
   %r = sext i8 %a to i32
@@ -124,9 +127,9 @@ define i32 @sext_8_32(i8 %a) nounwind ssp {
 }
 
 define i32 @sext_16_32(i16 %a) nounwind ssp {
-; v7: sext_16_32:
+; v7-LABEL: sext_16_32:
 ; v7: sxth r0, r0
-; prev6: sext_16_32:
+; prev6-LABEL: sext_16_32:
 ; prev6: lsl{{s?}} r0, r0, #16
 ; prev6: asr{{s?}} r0, r0, #16
   %r = sext i16 %a to i32
diff --git a/test/CodeGen/ARM/fast-isel-fold.ll b/test/CodeGen/ARM/fast-isel-fold.ll
index c920f9b..e8ed8cb 100644
--- a/test/CodeGen/ARM/fast-isel-fold.ll
+++ b/test/CodeGen/ARM/fast-isel-fold.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
 
 @a = global i8 1, align 1
diff --git a/test/CodeGen/ARM/fast-isel-frameaddr.ll b/test/CodeGen/ARM/fast-isel-frameaddr.ll
index c256e73..8542bb5 100644
--- a/test/CodeGen/ARM/fast-isel-frameaddr.ll
+++ b/test/CodeGen/ARM/fast-isel-frameaddr.ll
@@ -5,22 +5,22 @@
 
 define i8* @frameaddr_index0() nounwind {
 entry:
-; DARWIN-ARM: frameaddr_index0:
+; DARWIN-ARM-LABEL: frameaddr_index0:
 ; DARWIN-ARM: push {r7}
 ; DARWIN-ARM: mov r7, sp
 ; DARWIN-ARM: mov r0, r7
 
-; DARWIN-THUMB2: frameaddr_index0:
+; DARWIN-THUMB2-LABEL: frameaddr_index0:
 ; DARWIN-THUMB2: str r7, [sp, #-4]!
 ; DARWIN-THUMB2: mov r7, sp
 ; DARWIN-THUMB2: mov r0, r7
 
-; LINUX-ARM: frameaddr_index0:
+; LINUX-ARM-LABEL: frameaddr_index0:
 ; LINUX-ARM: push {r11}
 ; LINUX-ARM: mov r11, sp
 ; LINUX-ARM: mov r0, r11
 
-; LINUX-THUMB2: frameaddr_index0:
+; LINUX-THUMB2-LABEL: frameaddr_index0:
 ; LINUX-THUMB2: str r7, [sp, #-4]!
 ; LINUX-THUMB2: mov r7, sp
 ; LINUX-THUMB2: mov r0, r7
@@ -31,25 +31,24 @@ entry:
 
 define i8* @frameaddr_index1() nounwind {
 entry:
-; DARWIN-ARM: frameaddr_index1:
+; DARWIN-ARM-LABEL: frameaddr_index1:
 ; DARWIN-ARM: push {r7}
 ; DARWIN-ARM: mov r7, sp
 ; DARWIN-ARM: mov r0, r7
 ; DARWIN-ARM: ldr r0, [r0]
 
-; DARWIN-THUMB2: frameaddr_index1:
+; DARWIN-THUMB2-LABEL: frameaddr_index1:
 ; DARWIN-THUMB2: str r7, [sp, #-4]!
 ; DARWIN-THUMB2: mov r7, sp
 ; DARWIN-THUMB2: mov r0, r7
 ; DARWIN-THUMB2: ldr r0, [r0]
 
-; LINUX-ARM: frameaddr_index1:
+; LINUX-ARM-LABEL: frameaddr_index1:
 ; LINUX-ARM: push {r11}
 ; LINUX-ARM: mov r11, sp
-; LINUX-ARM: mov r0, r11
-; LINUX-ARM: ldr r0, [r0]
+; LINUX-ARM: ldr r0, [r11]
 
-; LINUX-THUMB2: frameaddr_index1:
+; LINUX-THUMB2-LABEL: frameaddr_index1:
 ; LINUX-THUMB2: str r7, [sp, #-4]!
 ; LINUX-THUMB2: mov r7, sp
 ; LINUX-THUMB2: mov r0, r7
@@ -61,7 +60,7 @@ entry:
 
 define i8* @frameaddr_index3() nounwind {
 entry:
-; DARWIN-ARM: frameaddr_index3:
+; DARWIN-ARM-LABEL: frameaddr_index3:
 ; DARWIN-ARM: push {r7}
 ; DARWIN-ARM: mov r7, sp
 ; DARWIN-ARM: mov r0, r7
@@ -69,7 +68,7 @@ entry:
 ; DARWIN-ARM: ldr r0, [r0]
 ; DARWIN-ARM: ldr r0, [r0]
 
-; DARWIN-THUMB2: frameaddr_index3:
+; DARWIN-THUMB2-LABEL: frameaddr_index3:
 ; DARWIN-THUMB2: str r7, [sp, #-4]!
 ; DARWIN-THUMB2: mov r7, sp
 ; DARWIN-THUMB2: mov r0, r7
@@ -77,15 +76,14 @@ entry:
 ; DARWIN-THUMB2: ldr r0, [r0]
 ; DARWIN-THUMB2: ldr r0, [r0]
 
-; LINUX-ARM: frameaddr_index3:
+; LINUX-ARM-LABEL: frameaddr_index3:
 ; LINUX-ARM: push {r11}
 ; LINUX-ARM: mov r11, sp
-; LINUX-ARM: mov r0, r11
-; LINUX-ARM: ldr r0, [r0]
+; LINUX-ARM: ldr r0, [r11]
 ; LINUX-ARM: ldr r0, [r0]
 ; LINUX-ARM: ldr r0, [r0]
 
-; LINUX-THUMB2: frameaddr_index3:
+; LINUX-THUMB2-LABEL: frameaddr_index3:
 ; LINUX-THUMB2: str r7, [sp, #-4]!
 ; LINUX-THUMB2: mov r7, sp
 ; LINUX-THUMB2: mov r0, r7
diff --git a/test/CodeGen/ARM/fast-isel-icmp.ll b/test/CodeGen/ARM/fast-isel-icmp.ll
index 9d4beb6..3dc1109 100644
--- a/test/CodeGen/ARM/fast-isel-icmp.ll
+++ b/test/CodeGen/ARM/fast-isel-icmp.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 define i32 @icmp_i16_signed(i16 %a, i16 %b) nounwind {
diff --git a/test/CodeGen/ARM/fast-isel-indirectbr.ll b/test/CodeGen/ARM/fast-isel-indirectbr.ll
index ebc0e84..2456ef4 100644
--- a/test/CodeGen/ARM/fast-isel-indirectbr.ll
+++ b/test/CodeGen/ARM/fast-isel-indirectbr.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 define void @t1(i8* %x) {
diff --git a/test/CodeGen/ARM/fast-isel-intrinsic.ll b/test/CodeGen/ARM/fast-isel-intrinsic.ll
index d2d208b..572ac3a 100644
--- a/test/CodeGen/ARM/fast-isel-intrinsic.ll
+++ b/test/CodeGen/ARM/fast-isel-intrinsic.ll
@@ -1,6 +1,8 @@
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG
 
 ; Note that some of these tests assume that relocations are either
@@ -20,8 +22,8 @@ define void @t1() nounwind ssp {
 ; ARM: and r1, r1, #255
 ; ARM: bl {{_?}}memset
 ; ARM-LONG: t1
-; ARM-LONG: movw r3, :lower16:L_memset$non_lazy_ptr
-; ARM-LONG: movt r3, :upper16:L_memset$non_lazy_ptr
+; ARM-LONG: {{(movw r3, :lower16:L_memset\$non_lazy_ptr)|(ldr r3, .LCPI)}}
+; ARM-LONG: {{(movt r3, :upper16:L_memset\$non_lazy_ptr)?}}
 ; ARM-LONG: ldr r3, [r3]
 ; ARM-LONG: blx r3
 ; THUMB: t1
@@ -58,8 +60,8 @@ define void @t2() nounwind ssp {
 ; ARM: ldr r1, [sp[[SLOT]]] @ 4-byte Reload
 ; ARM: bl {{_?}}memcpy
 ; ARM-LONG: t2
-; ARM-LONG: movw r3, :lower16:L_memcpy$non_lazy_ptr
-; ARM-LONG: movt r3, :upper16:L_memcpy$non_lazy_ptr
+; ARM-LONG: {{(movw r3, :lower16:L_memcpy\$non_lazy_ptr)|(ldr r3, .LCPI)}}
+; ARM-LONG: {{(movt r3, :upper16:L_memcpy\$non_lazy_ptr)?}}
 ; ARM-LONG: ldr r3, [r3]
 ; ARM-LONG: blx r3
 ; THUMB: t2
@@ -96,8 +98,8 @@ define void @t3() nounwind ssp {
 ; ARM: mov r0, r1
 ; ARM: bl {{_?}}memmove
 ; ARM-LONG: t3
-; ARM-LONG: movw r3, :lower16:L_memmove$non_lazy_ptr
-; ARM-LONG: movt r3, :upper16:L_memmove$non_lazy_ptr
+; ARM-LONG: {{(movw r3, :lower16:L_memmove\$non_lazy_ptr)|(ldr r3, .LCPI)}}
+; ARM-LONG: {{(movt r3, :upper16:L_memmove\$non_lazy_ptr)?}}
 ; ARM-LONG: ldr r3, [r3]
 ; ARM-LONG: blx r3
 ; THUMB: t3
diff --git a/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll b/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
index 0e71322..c05ea39 100644
--- a/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
+++ b/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; rdar://10418009
 
 define zeroext i16 @t1(i16* nocapture %a) nounwind uwtable readonly ssp {
diff --git a/test/CodeGen/ARM/fast-isel-mvn.ll b/test/CodeGen/ARM/fast-isel-mvn.ll
index 328168a..0bc9395 100644
--- a/test/CodeGen/ARM/fast-isel-mvn.ll
+++ b/test/CodeGen/ARM/fast-isel-mvn.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 ; rdar://10412592
 
diff --git a/test/CodeGen/ARM/fast-isel-pic.ll b/test/CodeGen/ARM/fast-isel-pic.ll
index da7007b..ad0f159 100644
--- a/test/CodeGen/ARM/fast-isel-pic.ll
+++ b/test/CodeGen/ARM/fast-isel-pic.ll
@@ -13,8 +13,8 @@ entry:
 ; THUMB: movt [[reg0]],
 ; THUMB: add  [[reg0]], pc
 ; THUMB-ELF: LoadGV
-; THUMB-ELF: ldr.n r[[reg0:[0-9]+]],
-; THUMB-ELF: ldr.n r[[reg1:[0-9]+]],
+; THUMB-ELF: ldr r[[reg0:[0-9]+]],
+; THUMB-ELF: ldr r[[reg1:[0-9]+]],
 ; THUMB-ELF: ldr r[[reg0]], [r[[reg0]], r[[reg1]]]
 ; ARM: LoadGV
 ; ARM: ldr [[reg1:r[0-9]+]],
@@ -26,7 +26,7 @@ entry:
 ; ARMv7-ELF: LoadGV
 ; ARMv7-ELF: ldr r[[reg2:[0-9]+]],
 ; ARMv7-ELF: ldr r[[reg3:[0-9]+]],
-; ARMv7-ELF: ldr r[[reg2]], [r[[reg2]], r[[reg3]]]
+; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
   %tmp = load i32* @g
   ret i32 %tmp
 }
@@ -41,8 +41,8 @@ entry:
 ; THUMB: add  r[[reg3]], pc
 ; THUMB: ldr  r[[reg3]], [r[[reg3]]]
 ; THUMB-ELF: LoadIndirectSymbol
-; THUMB-ELF: ldr.n r[[reg3:[0-9]+]],
-; THUMB-ELF: ldr.n r[[reg4:[0-9]+]],
+; THUMB-ELF: ldr r[[reg3:[0-9]+]],
+; THUMB-ELF: ldr r[[reg4:[0-9]+]],
 ; THUMB-ELF: ldr r[[reg3]], [r[[reg3]], r[[reg4]]]
 ; ARM: LoadIndirectSymbol
 ; ARM: ldr [[reg4:r[0-9]+]],
@@ -55,7 +55,7 @@ entry:
 ; ARMv7-ELF: LoadIndirectSymbol
 ; ARMv7-ELF: ldr r[[reg5:[0-9]+]],
 ; ARMv7-ELF: ldr r[[reg6:[0-9]+]],
-; ARMv7-ELF: ldr r[[reg5]], [r[[reg5]], r[[reg6]]]
+; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]]
   %tmp = load i32* @i
   ret i32 %tmp
 }
diff --git a/test/CodeGen/ARM/fast-isel-pred.ll b/test/CodeGen/ARM/fast-isel-pred.ll
index 27731de..48f9322 100644
--- a/test/CodeGen/ARM/fast-isel-pred.ll
+++ b/test/CodeGen/ARM/fast-isel-pred.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -O0 -verify-machineinstrs -mtriple=armv7-apple-darwin < %s
+; RUN: llc -O0 -verify-machineinstrs -mtriple=armv7-linux-gnueabi < %s
 
 define i32 @main() nounwind ssp {
 entry:
diff --git a/test/CodeGen/ARM/fast-isel-ret.ll b/test/CodeGen/ARM/fast-isel-ret.ll
index 4091dc6..ba5412c 100644
--- a/test/CodeGen/ARM/fast-isel-ret.ll
+++ b/test/CodeGen/ARM/fast-isel-ret.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s
 
 ; Sign-extend of i1 currently not supported by fast-isel
diff --git a/test/CodeGen/ARM/fast-isel-select.ll b/test/CodeGen/ARM/fast-isel-select.ll
index a937036..bb88814 100644
--- a/test/CodeGen/ARM/fast-isel-select.ll
+++ b/test/CodeGen/ARM/fast-isel-select.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 define i32 @t1(i1 %c) nounwind readnone {
diff --git a/test/CodeGen/ARM/fast-isel-shifter.ll b/test/CodeGen/ARM/fast-isel-shifter.ll
index 111818b..dbb1ce2 100644
--- a/test/CodeGen/ARM/fast-isel-shifter.ll
+++ b/test/CodeGen/ARM/fast-isel-shifter.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 
 define i32 @shl() nounwind ssp {
 entry:
diff --git a/test/CodeGen/ARM/fast-isel-static.ll b/test/CodeGen/ARM/fast-isel-static.ll
index afdfa84..7d86cb9 100644
--- a/test/CodeGen/ARM/fast-isel-static.ll
+++ b/test/CodeGen/ARM/fast-isel-static.ll
@@ -1,5 +1,7 @@
 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=LONG %s
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=LONG %s
 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=NORM %s
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=NORM %s
 
 define void @myadd(float* %sum, float* %addend) nounwind {
 entry:
diff --git a/test/CodeGen/ARM/fast-isel-vararg.ll b/test/CodeGen/ARM/fast-isel-vararg.ll
new file mode 100644
index 0000000..0b7b0bd
--- /dev/null
+++ b/test/CodeGen/ARM/fast-isel-vararg.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
+
+define i32 @VarArg() nounwind {
+entry:
+  %i = alloca i32, align 4
+  %j = alloca i32, align 4
+  %k = alloca i32, align 4
+  %m = alloca i32, align 4
+  %n = alloca i32, align 4
+  %tmp = alloca i32, align 4
+  %0 = load i32* %i, align 4
+  %1 = load i32* %j, align 4
+  %2 = load i32* %k, align 4
+  %3 = load i32* %m, align 4
+  %4 = load i32* %n, align 4
+; ARM: VarArg
+; ARM: mov [[FP:r[0-9]+]], sp
+; ARM: sub sp, sp, #32
+; ARM: movw r0, #5
+; ARM: ldr r1, {{\[}}[[FP]], #-4]
+; ARM: ldr r2, {{\[}}[[FP]], #-8]
+; ARM: ldr r3, {{\[}}[[FP]], #-12]
+; ARM: ldr [[Ra:r[0-9]+]], [sp, #16]
+; ARM: ldr [[Rb:[lr]+[0-9]*]], [sp, #12]
+; ARM: str [[Ra]], [sp]
+; ARM: str [[Rb]], [sp, #4]
+; ARM: bl {{_?CallVariadic}}
+; THUMB: sub sp, #32
+; THUMB: movs r0, #5
+; THUMB: movt r0, #0
+; THUMB: ldr r1, [sp, #28]
+; THUMB: ldr r2, [sp, #24]
+; THUMB: ldr r3, [sp, #20]
+; THUMB: ldr.w {{[a-z0-9]+}}, [sp, #16]
+; THUMB: ldr.w {{[a-z0-9]+}}, [sp, #12]
+; THUMB: str.w {{[a-z0-9]+}}, [sp]
+; THUMB: str.w {{[a-z0-9]+}}, [sp, #4]
+; THUMB: bl {{_?}}CallVariadic
+  %call = call i32 (i32, ...)* @CallVariadic(i32 5, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4)
+  store i32 %call, i32* %tmp, align 4
+  %5 = load i32* %tmp, align 4
+  ret i32 %5
+}
+
+declare i32 @CallVariadic(i32, ...)
diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll
index f877e78..0cebc90 100644
--- a/test/CodeGen/ARM/fast-isel.ll
+++ b/test/CodeGen/ARM/fast-isel.ll
@@ -1,8 +1,9 @@
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
 
 ; Very basic fast-isel functionality.
-define i32 @add(i32 %a, i32 %b) nounwind {
+define i32 @test0(i32 %a, i32 %b) nounwind {
 entry:
   %a.addr = alloca i32, align 4
   %b.addr = alloca i32, align 4
@@ -26,16 +27,16 @@ br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
 ret void
-; ARM: test1:
+; ARM-LABEL: test1:
 ; ARM: tst r0, #1
-; THUMB: test1:
+; THUMB-LABEL: test1:
 ; THUMB: tst.w r0, #1
 }
 
 ; Check some simple operations with immediates
 define void @test2(i32 %tmp, i32* %ptr) nounwind {
-; THUMB: test2:
-; ARM: test2:
+; THUMB-LABEL: test2:
+; ARM-LABEL: test2:
 
 b1:
   %a = add i32 %tmp, 4096
@@ -63,8 +64,8 @@ b3:
 }
 
 define void @test3(i32 %tmp, i32* %ptr1, i16* %ptr2, i8* %ptr3) nounwind {
-; THUMB: test3:
-; ARM: test3:
+; THUMB-LABEL: test3:
+; ARM-LABEL: test3:
 
 bb1:
   %a1 = trunc i32 %tmp to i16
diff --git a/test/CodeGen/ARM/fast-tail-call.ll b/test/CodeGen/ARM/fast-tail-call.ll
new file mode 100644
index 0000000..9fbdc9d
--- /dev/null
+++ b/test/CodeGen/ARM/fast-tail-call.ll
@@ -0,0 +1,16 @@
+; RUN: llc -mtriple=thumbv7-linux-gnueabi -O0 -arm-tail-calls < %s | FileCheck %s
+
+; Primarily a non-crash test: Thumbv7 Linux does not have FastISel support,
+; which led (via a convoluted route) to DAG nodes after a TC_RETURN that
+; couldn't possibly work.
+
+declare i8* @g(i8*)
+
+define i8* @f(i8* %a) {
+entry:
+  %0 = tail call i8* @g(i8* %a)
+  ret i8* %0
+; CHECK: b g
+; CHECK-NOT: ldr
+; CHECK-NOT: str
+}
diff --git a/test/CodeGen/ARM/fcopysign.ll b/test/CodeGen/ARM/fcopysign.ll
index 5511d24..1de0572 100644
--- a/test/CodeGen/ARM/fcopysign.ll
+++ b/test/CodeGen/ARM/fcopysign.ll
@@ -4,11 +4,11 @@
 ; rdar://8984306
 define float @test1(float %x, float %y) nounwind {
 entry:
-; SOFT: test1:
+; SOFT-LABEL: test1:
 ; SOFT: lsr r1, r1, #31
 ; SOFT: bfi r0, r1, #31, #1
 
-; HARD: test1:
+; HARD-LABEL: test1:
 ; HARD: vmov.i32 [[REG1:(d[0-9]+)]], #0x80000000
 ; HARD: vbsl [[REG1]], d
   %0 = tail call float @copysignf(float %x, float %y) nounwind readnone
@@ -17,11 +17,11 @@ entry:
 
 define double @test2(double %x, double %y) nounwind {
 entry:
-; SOFT: test2:
+; SOFT-LABEL: test2:
 ; SOFT: lsr r2, r3, #31
 ; SOFT: bfi r1, r2, #31, #1
 
-; HARD: test2:
+; HARD-LABEL: test2:
 ; HARD: vmov.i32 [[REG2:(d[0-9]+)]], #0x80000000
 ; HARD: vshl.i64 [[REG2]], [[REG2]], #32
 ; HARD: vbsl [[REG2]], d1, d0
@@ -31,7 +31,7 @@ entry:
 
 define double @test3(double %x, double %y, double %z) nounwind {
 entry:
-; SOFT: test3:
+; SOFT-LABEL: test3:
 ; SOFT: vmov.i32 [[REG3:(d[0-9]+)]], #0x80000000
 ; SOFT: vshl.i64 [[REG3]], [[REG3]], #32
 ; SOFT: vbsl [[REG3]],
@@ -43,7 +43,7 @@ entry:
 ; rdar://9287902
 define float @test4() nounwind {
 entry:
-; SOFT: test4:
+; SOFT-LABEL: test4:
 ; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1
 ; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000
 ; SOFT: vshr.u64 [[REG7]], [[REG7]], #32
diff --git a/test/CodeGen/ARM/fdivs.ll b/test/CodeGen/ARM/fdivs.ll
index 8f13f39..a4fecfe 100644
--- a/test/CodeGen/ARM/fdivs.ll
+++ b/test/CodeGen/ARM/fdivs.ll
@@ -9,15 +9,15 @@ entry:
 	ret float %0
 }
 
-; VFP2: test:
+; VFP2-LABEL: test:
 ; VFP2: 	vdiv.f32	s{{.}}, s{{.}}, s{{.}}
 
-; NFP1: test:
+; NFP1-LABEL: test:
 ; NFP1: 	vdiv.f32	s{{.}}, s{{.}}, s{{.}}
-; NFP0: test:
+; NFP0-LABEL: test:
 ; NFP0: 	vdiv.f32	s{{.}}, s{{.}}, s{{.}}
 
-; CORTEXA8: test:
+; CORTEXA8-LABEL: test:
 ; CORTEXA8: 	vdiv.f32	s{{.}}, s{{.}}, s{{.}}
-; CORTEXA9: test:
+; CORTEXA9-LABEL: test:
 ; CORTEXA9: 	vdiv.f32	s{{.}}, s{{.}}, s{{.}}
diff --git a/test/CodeGen/ARM/fmacs.ll b/test/CodeGen/ARM/fmacs.ll
index b63f609..f2486c6 100644
--- a/test/CodeGen/ARM/fmacs.ll
+++ b/test/CodeGen/ARM/fmacs.ll
@@ -6,13 +6,13 @@
 
 define float @t1(float %acc, float %a, float %b) {
 entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
 ; VFP2: vmla.f32
 
-; NEON: t1:
+; NEON-LABEL: t1:
 ; NEON: vmla.f32
 
-; A8: t1:
+; A8-LABEL: t1:
 ; A8: vmul.f32
 ; A8: vadd.f32
 	%0 = fmul float %a, %b
@@ -22,13 +22,13 @@ entry:
 
 define double @t2(double %acc, double %a, double %b) {
 entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
 ; VFP2: vmla.f64
 
-; NEON: t2:
+; NEON-LABEL: t2:
 ; NEON: vmla.f64
 
-; A8: t2:
+; A8-LABEL: t2:
 ; A8: vmul.f64
 ; A8: vadd.f64
 	%0 = fmul double %a, %b
@@ -38,13 +38,13 @@ entry:
 
 define float @t3(float %acc, float %a, float %b) {
 entry:
-; VFP2: t3:
+; VFP2-LABEL: t3:
 ; VFP2: vmla.f32
 
-; NEON: t3:
+; NEON-LABEL: t3:
 ; NEON: vmla.f32
 
-; A8: t3:
+; A8-LABEL: t3:
 ; A8: vmul.f32
 ; A8: vadd.f32
 	%0 = fmul float %a, %b
@@ -56,18 +56,18 @@ entry:
 ; rdar://8659675
 define void @t4(float %acc1, float %a, float %b, float %acc2, float %c, float* %P1, float* %P2) {
 entry:
-; A8: t4:
+; A8-LABEL: t4:
 ; A8: vmul.f32
 ; A8: vmul.f32
 ; A8: vadd.f32
 ; A8: vadd.f32
 
 ; Two vmla with now RAW hazard
-; A9: t4:
+; A9-LABEL: t4:
 ; A9: vmla.f32
 ; A9: vmla.f32
 
-; HARD: t4:
+; HARD-LABEL: t4:
 ; HARD: vmla.f32 s0, s1, s2
 ; HARD: vmla.f32 s3, s1, s4
   %0 = fmul float %a, %b
@@ -81,18 +81,18 @@ entry:
 
 define float @t5(float %a, float %b, float %c, float %d, float %e) {
 entry:
-; A8: t5:
+; A8-LABEL: t5:
 ; A8: vmul.f32
 ; A8: vmul.f32
 ; A8: vadd.f32
 ; A8: vadd.f32
 
-; A9: t5:
+; A9-LABEL: t5:
 ; A9: vmla.f32
 ; A9: vmul.f32
 ; A9: vadd.f32
 
-; HARD: t5:
+; HARD-LABEL: t5:
 ; HARD: vmla.f32 s4, s0, s1
 ; HARD: vmul.f32 s0, s2, s3
 ; HARD: vadd.f32 s0, s4, s0
diff --git a/test/CodeGen/ARM/fmscs.ll b/test/CodeGen/ARM/fmscs.ll
index a182833..f16ec17 100644
--- a/test/CodeGen/ARM/fmscs.ll
+++ b/test/CodeGen/ARM/fmscs.ll
@@ -4,13 +4,13 @@
 
 define float @t1(float %acc, float %a, float %b) {
 entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
 ; VFP2: vnmls.f32
 
-; NEON: t1:
+; NEON-LABEL: t1:
 ; NEON: vnmls.f32
 
-; A8: t1:
+; A8-LABEL: t1:
 ; A8: vmul.f32
 ; A8: vsub.f32
 	%0 = fmul float %a, %b
@@ -20,13 +20,13 @@ entry:
 
 define double @t2(double %acc, double %a, double %b) {
 entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
 ; VFP2: vnmls.f64
 
-; NEON: t2:
+; NEON-LABEL: t2:
 ; NEON: vnmls.f64
 
-; A8: t2:
+; A8-LABEL: t2:
 ; A8: vmul.f64
 ; A8: vsub.f64
 	%0 = fmul double %a, %b
diff --git a/test/CodeGen/ARM/fmuls.ll b/test/CodeGen/ARM/fmuls.ll
index f5245c9..d11f6bd 100644
--- a/test/CodeGen/ARM/fmuls.ll
+++ b/test/CodeGen/ARM/fmuls.ll
@@ -11,19 +11,19 @@ entry:
 	ret float %0
 }
 
-; VFP2: test:
+; VFP2-LABEL: test:
 ; VFP2: 	vmul.f32	s
 
-; NFP1: test:
+; NFP1-LABEL: test:
 ; NFP1: 	vmul.f32	d
-; NFP0: test:
+; NFP0-LABEL: test:
 ; NFP0: 	vmul.f32	s
 
-; CORTEXA8: test:
+; CORTEXA8-LABEL: test:
 ; CORTEXA8: 	vmul.f32	s
-; CORTEXA8U: test:
+; CORTEXA8U-LABEL: test:
 ; CORTEXA8U: 	vmul.f32	d
-; CORTEXA9: test:
+; CORTEXA9-LABEL: test:
 ; CORTEXA9: 	vmul.f32	s
 
 ; VFP2: test2
diff --git a/test/CodeGen/ARM/fnegs.ll b/test/CodeGen/ARM/fnegs.ll
index d84690b..dc4c2e3 100644
--- a/test/CodeGen/ARM/fnegs.ll
+++ b/test/CodeGen/ARM/fnegs.ll
@@ -14,22 +14,22 @@ entry:
 	%retval = select i1 %3, float %1, float %0		; <float> [#uses=1]
 	ret float %retval
 }
-; VFP2: test1:
+; VFP2-LABEL: test1:
 ; VFP2: 	vneg.f32	s{{.*}}, s{{.*}}
 
-; NFP1: test1:
+; NFP1-LABEL: test1:
 ; NFP1: 	vneg.f32	d{{.*}}, d{{.*}}
 
-; NFP0: test1:
+; NFP0-LABEL: test1:
 ; NFP0: 	vneg.f32	s{{.*}}, s{{.*}}
 
-; CORTEXA8: test1:
+; CORTEXA8-LABEL: test1:
 ; CORTEXA8: 	vneg.f32	s{{.*}}, s{{.*}}
 
-; CORTEXA8U: test1:
+; CORTEXA8U-LABEL: test1:
 ; CORTEXA8U: 	vneg.f32	d{{.*}}, d{{.*}}
 
-; CORTEXA9: test1:
+; CORTEXA9-LABEL: test1:
 ; CORTEXA9: 	vneg.f32	s{{.*}}, s{{.*}}
 
 define float @test2(float* %a) {
@@ -41,21 +41,21 @@ entry:
 	%retval = select i1 %3, float %1, float %0		; <float> [#uses=1]
 	ret float %retval
 }
-; VFP2: test2:
+; VFP2-LABEL: test2:
 ; VFP2: 	vneg.f32	s{{.*}}, s{{.*}}
 
-; NFP1: test2:
+; NFP1-LABEL: test2:
 ; NFP1: 	vneg.f32	d{{.*}}, d{{.*}}
 
-; NFP0: test2:
+; NFP0-LABEL: test2:
 ; NFP0: 	vneg.f32	s{{.*}}, s{{.*}}
 
-; CORTEXA8: test2:
+; CORTEXA8-LABEL: test2:
 ; CORTEXA8: 	vneg.f32	s{{.*}}, s{{.*}}
 
-; CORTEXA8U: test2:
+; CORTEXA8U-LABEL: test2:
 ; CORTEXA8U: 	vneg.f32	d{{.*}}, d{{.*}}
 
-; CORTEXA9: test2:
+; CORTEXA9-LABEL: test2:
 ; CORTEXA9: 	vneg.f32	s{{.*}}, s{{.*}}
 
diff --git a/test/CodeGen/ARM/fnmacs.ll b/test/CodeGen/ARM/fnmacs.ll
index 1763d46..825feaa 100644
--- a/test/CodeGen/ARM/fnmacs.ll
+++ b/test/CodeGen/ARM/fnmacs.ll
@@ -4,13 +4,13 @@
 
 define float @t1(float %acc, float %a, float %b) {
 entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
 ; VFP2: vmls.f32
 
-; NEON: t1:
+; NEON-LABEL: t1:
 ; NEON: vmls.f32
 
-; A8: t1:
+; A8-LABEL: t1:
 ; A8: vmul.f32
 ; A8: vsub.f32
 	%0 = fmul float %a, %b
@@ -20,13 +20,13 @@ entry:
 
 define double @t2(double %acc, double %a, double %b) {
 entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
 ; VFP2: vmls.f64
 
-; NEON: t2:
+; NEON-LABEL: t2:
 ; NEON: vmls.f64
 
-; A8: t2:
+; A8-LABEL: t2:
 ; A8: vmul.f64
 ; A8: vsub.f64
 	%0 = fmul double %a, %b
diff --git a/test/CodeGen/ARM/fnmscs.ll b/test/CodeGen/ARM/fnmscs.ll
index c308061..78ccb60 100644
--- a/test/CodeGen/ARM/fnmscs.ll
+++ b/test/CodeGen/ARM/fnmscs.ll
@@ -7,17 +7,17 @@
 
 define float @t1(float %acc, float %a, float %b) nounwind {
 entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
 ; VFP2: vnmla.f32
 
-; NEON: t1:
+; NEON-LABEL: t1:
 ; NEON: vnmla.f32
 
-; A8U: t1:
+; A8U-LABEL: t1:
 ; A8U: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
 ; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
 
-; A8: t1:
+; A8-LABEL: t1:
 ; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
 ; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
 	%0 = fmul float %a, %b
@@ -28,17 +28,17 @@ entry:
 
 define float @t2(float %acc, float %a, float %b) nounwind {
 entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
 ; VFP2: vnmla.f32
 
-; NEON: t2:
+; NEON-LABEL: t2:
 ; NEON: vnmla.f32
 
-; A8U: t2:
+; A8U-LABEL: t2:
 ; A8U: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
 ; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
 
-; A8: t2:
+; A8-LABEL: t2:
 ; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
 ; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
 	%0 = fmul float %a, %b
@@ -49,17 +49,17 @@ entry:
 
 define double @t3(double %acc, double %a, double %b) nounwind {
 entry:
-; VFP2: t3:
+; VFP2-LABEL: t3:
 ; VFP2: vnmla.f64
 
-; NEON: t3:
+; NEON-LABEL: t3:
 ; NEON: vnmla.f64
 
-; A8U: t3:
+; A8U-LABEL: t3:
 ; A8U: vnmul.f64 d
 ; A8U: vsub.f64 d
 
-; A8: t3:
+; A8-LABEL: t3:
 ; A8: vnmul.f64 d
 ; A8: vsub.f64 d
 	%0 = fmul double %a, %b
@@ -70,17 +70,17 @@ entry:
 
 define double @t4(double %acc, double %a, double %b) nounwind {
 entry:
-; VFP2: t4:
+; VFP2-LABEL: t4:
 ; VFP2: vnmla.f64
 
-; NEON: t4:
+; NEON-LABEL: t4:
 ; NEON: vnmla.f64
 
-; A8U: t4:
+; A8U-LABEL: t4:
 ; A8U: vnmul.f64 d
 ; A8U: vsub.f64 d
 
-; A8: t4:
+; A8-LABEL: t4:
 ; A8: vnmul.f64 d
 ; A8: vsub.f64 d
 	%0 = fmul double %a, %b
diff --git a/test/CodeGen/ARM/fp.ll b/test/CodeGen/ARM/fp.ll
index 93601cf..fbf3a4a 100644
--- a/test/CodeGen/ARM/fp.ll
+++ b/test/CodeGen/ARM/fp.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
 
 define float @f(i32 %a) {
-;CHECK: f:
+;CHECK-LABEL: f:
 ;CHECK: vmov
 ;CHECK-NEXT: vcvt.f32.s32
 ;CHECK-NEXT: vmov
@@ -11,7 +11,7 @@ entry:
 }
 
 define double @g(i32 %a) {
-;CHECK: g:
+;CHECK-LABEL: g:
 ;CHECK: vmov
 ;CHECK-NEXT: vcvt.f64.s32
 ;CHECK-NEXT: vmov
@@ -21,7 +21,7 @@ entry:
 }
 
 define double @uint_to_double(i32 %a) {
-;CHECK: uint_to_double:
+;CHECK-LABEL: uint_to_double:
 ;CHECK: vmov
 ;CHECK-NEXT: vcvt.f64.u32
 ;CHECK-NEXT: vmov
@@ -31,7 +31,7 @@ entry:
 }
 
 define float @uint_to_float(i32 %a) {
-;CHECK: uint_to_float:
+;CHECK-LABEL: uint_to_float:
 ;CHECK: vmov
 ;CHECK-NEXT: vcvt.f32.u32
 ;CHECK-NEXT: vmov
@@ -41,7 +41,7 @@ entry:
 }
 
 define double @h(double* %v) {
-;CHECK: h:
+;CHECK-LABEL: h:
 ;CHECK: vldr
 ;CHECK-NEXT: vmov
 entry:
@@ -50,20 +50,20 @@ entry:
 }
 
 define float @h2() {
-;CHECK: h2:
+;CHECK-LABEL: h2:
 ;CHECK: mov r0, #1065353216
 entry:
         ret float 1.000000e+00
 }
 
 define double @f2(double %a) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
 ;CHECK-NOT: vmov
         ret double %a
 }
 
 define void @f3() {
-;CHECK: f3:
+;CHECK-LABEL: f3:
 ;CHECK-NOT: vmov
 ;CHECK: f4
 entry:
diff --git a/test/CodeGen/ARM/fp16.ll b/test/CodeGen/ARM/fp16.ll
index 1261ea5..a5c1aed 100644
--- a/test/CodeGen/ARM/fp16.ll
+++ b/test/CodeGen/ARM/fp16.ll
@@ -8,8 +8,8 @@ target triple = "armv7-eabi"
 @z = common global i16 0
 
 define arm_aapcs_vfpcc void @foo() nounwind {
-; CHECK: foo:
-; CHECK-FP6: foo:
+; CHECK-LABEL: foo:
+; CHECK-FP6-LABEL: foo:
 entry:
   %0 = load i16* @x, align 2
   %1 = load i16* @y, align 2
diff --git a/test/CodeGen/ARM/fp_convert.ll b/test/CodeGen/ARM/fp_convert.ll
index 3c47eb5..f0d9100 100644
--- a/test/CodeGen/ARM/fp_convert.ll
+++ b/test/CodeGen/ARM/fp_convert.ll
@@ -6,9 +6,9 @@
 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2
 
 define i32 @test1(float %a, float %b) {
-; VFP2: test1:
+; VFP2-LABEL: test1:
 ; VFP2: vcvt.s32.f32 s{{.}}, s{{.}}
-; NEON: test1:
+; NEON-LABEL: test1:
 ; NEON: vadd.f32 [[D0:d[0-9]+]]
 ; NEON: vcvt.s32.f32 d0, [[D0]]
 entry:
@@ -18,9 +18,9 @@ entry:
 }
 
 define i32 @test2(float %a, float %b) {
-; VFP2: test2:
+; VFP2-LABEL: test2:
 ; VFP2: vcvt.u32.f32 s{{.}}, s{{.}}
-; NEON: test2:
+; NEON-LABEL: test2:
 ; NEON: vadd.f32 [[D0:d[0-9]+]]
 ; NEON: vcvt.u32.f32 d0, [[D0]]
 entry:
@@ -30,9 +30,9 @@ entry:
 }
 
 define float @test3(i32 %a, i32 %b) {
-; VFP2: test3:
+; VFP2-LABEL: test3:
 ; VFP2: vcvt.f32.u32 s{{.}}, s{{.}}
-; NEON: test3:
+; NEON-LABEL: test3:
 ; NEON: vcvt.f32.u32 d
 entry:
         %0 = add i32 %a, %b
@@ -41,9 +41,9 @@ entry:
 }
 
 define float @test4(i32 %a, i32 %b) {
-; VFP2: test4:
+; VFP2-LABEL: test4:
 ; VFP2: vcvt.f32.s32 s{{.}}, s{{.}}
-; NEON: test4:
+; NEON-LABEL: test4:
 ; NEON: vcvt.f32.s32 d
 entry:
         %0 = add i32 %a, %b
diff --git a/test/CodeGen/ARM/fparith.ll b/test/CodeGen/ARM/fparith.ll
index 40ea33b..cc88014 100644
--- a/test/CodeGen/ARM/fparith.ll
+++ b/test/CodeGen/ARM/fparith.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+vfp2 | FileCheck %s
 
 define float @f1(float %a, float %b) {
-;CHECK: f1:
+;CHECK-LABEL: f1:
 ;CHECK: vadd.f32
 entry:
 	%tmp = fadd float %a, %b		; <float> [#uses=1]
@@ -9,7 +9,7 @@ entry:
 }
 
 define double @f2(double %a, double %b) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
 ;CHECK: vadd.f64
 entry:
 	%tmp = fadd double %a, %b		; <double> [#uses=1]
@@ -17,7 +17,7 @@ entry:
 }
 
 define float @f3(float %a, float %b) {
-;CHECK: f3:
+;CHECK-LABEL: f3:
 ;CHECK: vmul.f32
 entry:
 	%tmp = fmul float %a, %b		; <float> [#uses=1]
@@ -25,7 +25,7 @@ entry:
 }
 
 define double @f4(double %a, double %b) {
-;CHECK: f4:
+;CHECK-LABEL: f4:
 ;CHECK: vmul.f64
 entry:
 	%tmp = fmul double %a, %b		; <double> [#uses=1]
@@ -33,7 +33,7 @@ entry:
 }
 
 define float @f5(float %a, float %b) {
-;CHECK: f5:
+;CHECK-LABEL: f5:
 ;CHECK: vsub.f32
 entry:
 	%tmp = fsub float %a, %b		; <float> [#uses=1]
@@ -41,7 +41,7 @@ entry:
 }
 
 define double @f6(double %a, double %b) {
-;CHECK: f6:
+;CHECK-LABEL: f6:
 ;CHECK: vsub.f64
 entry:
 	%tmp = fsub double %a, %b		; <double> [#uses=1]
@@ -49,7 +49,7 @@ entry:
 }
 
 define float @f7(float %a) {
-;CHECK: f7:
+;CHECK-LABEL: f7:
 ;CHECK: eor
 entry:
 	%tmp1 = fsub float -0.000000e+00, %a		; <float> [#uses=1]
@@ -57,7 +57,7 @@ entry:
 }
 
 define double @f8(double %a) {
-;CHECK: f8:
+;CHECK-LABEL: f8:
 ;CHECK: vneg.f64
 entry:
 	%tmp1 = fsub double -0.000000e+00, %a		; <double> [#uses=1]
@@ -65,7 +65,7 @@ entry:
 }
 
 define float @f9(float %a, float %b) {
-;CHECK: f9:
+;CHECK-LABEL: f9:
 ;CHECK: vdiv.f32
 entry:
 	%tmp1 = fdiv float %a, %b		; <float> [#uses=1]
@@ -73,7 +73,7 @@ entry:
 }
 
 define double @f10(double %a, double %b) {
-;CHECK: f10:
+;CHECK-LABEL: f10:
 ;CHECK: vdiv.f64
 entry:
 	%tmp1 = fdiv double %a, %b		; <double> [#uses=1]
@@ -81,7 +81,7 @@ entry:
 }
 
 define float @f11(float %a) {
-;CHECK: f11:
+;CHECK-LABEL: f11:
 ;CHECK: bic
 entry:
 	%tmp1 = call float @fabsf( float %a ) readnone	; <float> [#uses=1]
@@ -91,7 +91,7 @@ entry:
 declare float @fabsf(float)
 
 define double @f12(double %a) {
-;CHECK: f12:
+;CHECK-LABEL: f12:
 ;CHECK: vabs.f64
 entry:
 	%tmp1 = call double @fabs( double %a ) readnone	; <double> [#uses=1]
diff --git a/test/CodeGen/ARM/fpcmp-opt.ll b/test/CodeGen/ARM/fpcmp-opt.ll
index 2d8f710..3a0af16 100644
--- a/test/CodeGen/ARM/fpcmp-opt.ll
+++ b/test/CodeGen/ARM/fpcmp-opt.ll
@@ -5,7 +5,7 @@
 ; Disable this optimization unless we know one of them is zero.
 define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: vldr [[S0:s[0-9]+]],
 ; CHECK: vldr [[S1:s[0-9]+]],
 ; CHECK: vcmpe.f32 [[S1]], [[S0]]
@@ -29,13 +29,12 @@ bb2:
 ; +0.0 == -0.0
 define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK-NOT: vldr
-; CHECK: ldr [[REG1:(r[0-9]+)]], [r0]
-; CHECK: ldr [[REG2:(r[0-9]+)]], [r0, #4]
+; CHECK: ldrd [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], [r0]
 ; CHECK-NOT: b LBB
-; CHECK: cmp [[REG1]], #0
 ; CHECK: bfc [[REG2]], #31, #1
+; CHECK: cmp [[REG1]], #0
 ; CHECK: cmpeq [[REG2]], #0
 ; CHECK-NOT: vcmpe.f32
 ; CHECK-NOT: vmrs
@@ -55,7 +54,7 @@ bb2:
 
 define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK-NOT: vldr
 ; CHECK: ldr [[REG3:(r[0-9]+)]], [r0]
 ; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648
diff --git a/test/CodeGen/ARM/fpcmp.ll b/test/CodeGen/ARM/fpcmp.ll
index 260ec49..916a1ae 100644
--- a/test/CodeGen/ARM/fpcmp.ll
+++ b/test/CodeGen/ARM/fpcmp.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
 
 define i32 @f1(float %a) {
-;CHECK: f1:
+;CHECK-LABEL: f1:
 ;CHECK: vcmpe.f32
 ;CHECK: movmi
 entry:
@@ -11,7 +11,7 @@ entry:
 }
 
 define i32 @f2(float %a) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
 ;CHECK: vcmpe.f32
 ;CHECK: moveq
 entry:
@@ -21,7 +21,7 @@ entry:
 }
 
 define i32 @f3(float %a) {
-;CHECK: f3:
+;CHECK-LABEL: f3:
 ;CHECK: vcmpe.f32
 ;CHECK: movgt
 entry:
@@ -31,7 +31,7 @@ entry:
 }
 
 define i32 @f4(float %a) {
-;CHECK: f4:
+;CHECK-LABEL: f4:
 ;CHECK: vcmpe.f32
 ;CHECK: movge
 entry:
@@ -41,7 +41,7 @@ entry:
 }
 
 define i32 @f5(float %a) {
-;CHECK: f5:
+;CHECK-LABEL: f5:
 ;CHECK: vcmpe.f32
 ;CHECK: movls
 entry:
@@ -51,7 +51,7 @@ entry:
 }
 
 define i32 @f6(float %a) {
-;CHECK: f6:
+;CHECK-LABEL: f6:
 ;CHECK: vcmpe.f32
 ;CHECK: movne
 entry:
@@ -61,7 +61,7 @@ entry:
 }
 
 define i32 @g1(double %a) {
-;CHECK: g1:
+;CHECK-LABEL: g1:
 ;CHECK: vcmpe.f64
 ;CHECK: movmi
 entry:
diff --git a/test/CodeGen/ARM/fpcmp_ueq.ll b/test/CodeGen/ARM/fpcmp_ueq.ll
index 4a4c5b1..d84c7ae 100644
--- a/test/CodeGen/ARM/fpcmp_ueq.ll
+++ b/test/CodeGen/ARM/fpcmp_ueq.ll
@@ -3,7 +3,7 @@
 
 define i32 @f7(float %a, float %b) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: vcmpe.f32
 ; CHECK: vmrs APSR_nzcv, fpscr
 ; CHECK: movweq
diff --git a/test/CodeGen/ARM/fpconsts.ll b/test/CodeGen/ARM/fpconsts.ll
index 638dde9..0679a47 100644
--- a/test/CodeGen/ARM/fpconsts.ll
+++ b/test/CodeGen/ARM/fpconsts.ll
@@ -2,7 +2,7 @@
 
 define float @t1(float %x) nounwind readnone optsize {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: vmov.f32 s{{.*}}, #4.000000e+00
   %0 = fadd float %x, 4.000000e+00
   ret float %0
@@ -10,7 +10,7 @@ entry:
 
 define double @t2(double %x) nounwind readnone optsize {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: vmov.f64 d{{.*}}, #3.000000e+00
   %0 = fadd double %x, 3.000000e+00
   ret double %0
@@ -18,7 +18,7 @@ entry:
 
 define double @t3(double %x) nounwind readnone optsize {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: vmov.f64 d{{.*}}, #-1.300000e+01
   %0 = fmul double %x, -1.300000e+01
   ret double %0
@@ -26,7 +26,7 @@ entry:
 
 define float @t4(float %x) nounwind readnone optsize {
 entry:
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: vmov.f32 s{{.*}}, #-2.400000e+01
   %0 = fmul float %x, -2.400000e+01
   ret float %0
diff --git a/test/CodeGen/ARM/fpconv.ll b/test/CodeGen/ARM/fpconv.ll
index 1b4c008..326e062 100644
--- a/test/CodeGen/ARM/fpconv.ll
+++ b/test/CodeGen/ARM/fpconv.ll
@@ -2,9 +2,9 @@
 ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
 
 define float @f1(double %x) {
-;CHECK-VFP: f1:
+;CHECK-VFP-LABEL: f1:
 ;CHECK-VFP: vcvt.f32.f64
-;CHECK: f1:
+;CHECK-LABEL: f1:
 ;CHECK: truncdfsf2
 entry:
 	%tmp1 = fptrunc double %x to float		; <float> [#uses=1]
@@ -12,9 +12,9 @@ entry:
 }
 
 define double @f2(float %x) {
-;CHECK-VFP: f2:
+;CHECK-VFP-LABEL: f2:
 ;CHECK-VFP: vcvt.f64.f32
-;CHECK: f2:
+;CHECK-LABEL: f2:
 ;CHECK: extendsfdf2
 entry:
 	%tmp1 = fpext float %x to double		; <double> [#uses=1]
@@ -22,9 +22,9 @@ entry:
 }
 
 define i32 @f3(float %x) {
-;CHECK-VFP: f3:
+;CHECK-VFP-LABEL: f3:
 ;CHECK-VFP: vcvt.s32.f32
-;CHECK: f3:
+;CHECK-LABEL: f3:
 ;CHECK: fixsfsi
 entry:
 	%tmp = fptosi float %x to i32		; <i32> [#uses=1]
@@ -32,9 +32,9 @@ entry:
 }
 
 define i32 @f4(float %x) {
-;CHECK-VFP: f4:
+;CHECK-VFP-LABEL: f4:
 ;CHECK-VFP: vcvt.u32.f32
-;CHECK: f4:
+;CHECK-LABEL: f4:
 ;CHECK: fixunssfsi
 entry:
 	%tmp = fptoui float %x to i32		; <i32> [#uses=1]
@@ -42,9 +42,9 @@ entry:
 }
 
 define i32 @f5(double %x) {
-;CHECK-VFP: f5:
+;CHECK-VFP-LABEL: f5:
 ;CHECK-VFP: vcvt.s32.f64
-;CHECK: f5:
+;CHECK-LABEL: f5:
 ;CHECK: fixdfsi
 entry:
 	%tmp = fptosi double %x to i32		; <i32> [#uses=1]
@@ -52,9 +52,9 @@ entry:
 }
 
 define i32 @f6(double %x) {
-;CHECK-VFP: f6:
+;CHECK-VFP-LABEL: f6:
 ;CHECK-VFP: vcvt.u32.f64
-;CHECK: f6:
+;CHECK-LABEL: f6:
 ;CHECK: fixunsdfsi
 entry:
 	%tmp = fptoui double %x to i32		; <i32> [#uses=1]
@@ -62,9 +62,9 @@ entry:
 }
 
 define float @f7(i32 %a) {
-;CHECK-VFP: f7:
+;CHECK-VFP-LABEL: f7:
 ;CHECK-VFP: vcvt.f32.s32
-;CHECK: f7:
+;CHECK-LABEL: f7:
 ;CHECK: floatsisf
 entry:
 	%tmp = sitofp i32 %a to float		; <float> [#uses=1]
@@ -72,9 +72,9 @@ entry:
 }
 
 define double @f8(i32 %a) {
-;CHECK-VFP: f8:
+;CHECK-VFP-LABEL: f8:
 ;CHECK-VFP: vcvt.f64.s32
-;CHECK: f8:
+;CHECK-LABEL: f8:
 ;CHECK: floatsidf
 entry:
 	%tmp = sitofp i32 %a to double		; <double> [#uses=1]
@@ -82,9 +82,9 @@ entry:
 }
 
 define float @f9(i32 %a) {
-;CHECK-VFP: f9:
+;CHECK-VFP-LABEL: f9:
 ;CHECK-VFP: vcvt.f32.u32
-;CHECK: f9:
+;CHECK-LABEL: f9:
 ;CHECK: floatunsisf
 entry:
 	%tmp = uitofp i32 %a to float		; <float> [#uses=1]
@@ -92,9 +92,9 @@ entry:
 }
 
 define double @f10(i32 %a) {
-;CHECK-VFP: f10:
+;CHECK-VFP-LABEL: f10:
 ;CHECK-VFP: vcvt.f64.u32
-;CHECK: f10:
+;CHECK-LABEL: f10:
 ;CHECK: floatunsidf
 entry:
 	%tmp = uitofp i32 %a to double		; <double> [#uses=1]
diff --git a/test/CodeGen/ARM/fpmem.ll b/test/CodeGen/ARM/fpmem.ll
index 8faa578..8fbd1d8 100644
--- a/test/CodeGen/ARM/fpmem.ll
+++ b/test/CodeGen/ARM/fpmem.ll
@@ -1,13 +1,13 @@
 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
 
 define float @f1(float %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mov r0, #0
         ret float 0.000000e+00
 }
 
 define float @f2(float* %v, float %u) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: vldr{{.*}}[
         %tmp = load float* %v           ; <float> [#uses=1]
         %tmp1 = fadd float %tmp, %u              ; <float> [#uses=1]
@@ -15,7 +15,7 @@ define float @f2(float* %v, float %u) {
 }
 
 define float @f2offset(float* %v, float %u) {
-; CHECK: f2offset:
+; CHECK-LABEL: f2offset:
 ; CHECK: vldr{{.*}}, #4]
         %addr = getelementptr float* %v, i32 1
         %tmp = load float* %addr
@@ -24,7 +24,7 @@ define float @f2offset(float* %v, float %u) {
 }
 
 define float @f2noffset(float* %v, float %u) {
-; CHECK: f2noffset:
+; CHECK-LABEL: f2noffset:
 ; CHECK: vldr{{.*}}, #-4]
         %addr = getelementptr float* %v, i32 -1
         %tmp = load float* %addr
@@ -33,7 +33,7 @@ define float @f2noffset(float* %v, float %u) {
 }
 
 define void @f3(float %a, float %b, float* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: vstr{{.*}}[
         %tmp = fadd float %a, %b         ; <float> [#uses=1]
         store float %tmp, float* %v
diff --git a/test/CodeGen/ARM/fptoint.ll b/test/CodeGen/ARM/fptoint.ll
index 299cb8f81..7408687 100644
--- a/test/CodeGen/ARM/fptoint.ll
+++ b/test/CodeGen/ARM/fptoint.ll
@@ -44,6 +44,6 @@ define void @foo9(double %x) {
 	store i16 %tmp, i16* null
 	ret void
 }
-; CHECK: foo9:
+; CHECK-LABEL: foo9:
 ; CHECK: 	vmov	r0, s0
 
diff --git a/test/CodeGen/ARM/fusedMAC.ll b/test/CodeGen/ARM/fusedMAC.ll
index 303d165..e29f291 100644
--- a/test/CodeGen/ARM/fusedMAC.ll
+++ b/test/CodeGen/ARM/fusedMAC.ll
@@ -2,7 +2,7 @@
 ; Check generated fused MAC and MLS.
 
 define double @fusedMACTest1(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest1:
+;CHECK-LABEL: fusedMACTest1:
 ;CHECK: vfma.f64
   %1 = fmul double %d1, %d2
   %2 = fadd double %1, %d3
@@ -10,7 +10,7 @@ define double @fusedMACTest1(double %d1, double %d2, double %d3) {
 }
 
 define float @fusedMACTest2(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest2:
+;CHECK-LABEL: fusedMACTest2:
 ;CHECK: vfma.f32
   %1 = fmul float %f1, %f2
   %2 = fadd float %1, %f3
@@ -18,7 +18,7 @@ define float @fusedMACTest2(float %f1, float %f2, float %f3) {
 }
 
 define double @fusedMACTest3(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest3:
+;CHECK-LABEL: fusedMACTest3:
 ;CHECK: vfms.f64
   %1 = fmul double %d2, %d3
   %2 = fsub double %d1, %1
@@ -26,7 +26,7 @@ define double @fusedMACTest3(double %d1, double %d2, double %d3) {
 }
 
 define float @fusedMACTest4(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest4:
+;CHECK-LABEL: fusedMACTest4:
 ;CHECK: vfms.f32
   %1 = fmul float %f2, %f3
   %2 = fsub float %f1, %1
@@ -34,7 +34,7 @@ define float @fusedMACTest4(float %f1, float %f2, float %f3) {
 }
 
 define double @fusedMACTest5(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest5:
+;CHECK-LABEL: fusedMACTest5:
 ;CHECK: vfnma.f64
   %1 = fmul double %d1, %d2
   %2 = fsub double -0.0, %1
@@ -43,7 +43,7 @@ define double @fusedMACTest5(double %d1, double %d2, double %d3) {
 }
 
 define float @fusedMACTest6(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest6:
+;CHECK-LABEL: fusedMACTest6:
 ;CHECK: vfnma.f32
   %1 = fmul float %f1, %f2
   %2 = fsub float -0.0, %1
@@ -52,7 +52,7 @@ define float @fusedMACTest6(float %f1, float %f2, float %f3) {
 }
 
 define double @fusedMACTest7(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest7:
+;CHECK-LABEL: fusedMACTest7:
 ;CHECK: vfnms.f64
   %1 = fmul double %d1, %d2
   %2 = fsub double %1, %d3
@@ -60,7 +60,7 @@ define double @fusedMACTest7(double %d1, double %d2, double %d3) {
 }
 
 define float @fusedMACTest8(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest8:
+;CHECK-LABEL: fusedMACTest8:
 ;CHECK: vfnms.f32
   %1 = fmul float %f1, %f2
   %2 = fsub float %1, %f3
@@ -68,7 +68,7 @@ define float @fusedMACTest8(float %f1, float %f2, float %f3) {
 }
 
 define <2 x float> @fusedMACTest9(<2 x float> %a, <2 x float> %b) {
-;CHECK: fusedMACTest9:
+;CHECK-LABEL: fusedMACTest9:
 ;CHECK: vfma.f32
   %mul = fmul <2 x float> %a, %b
   %add = fadd <2 x float> %mul, %a
@@ -76,7 +76,7 @@ define <2 x float> @fusedMACTest9(<2 x float> %a, <2 x float> %b) {
 }
 
 define <2 x float> @fusedMACTest10(<2 x float> %a, <2 x float> %b) {
-;CHECK: fusedMACTest10:
+;CHECK-LABEL: fusedMACTest10:
 ;CHECK: vfms.f32
   %mul = fmul <2 x float> %a, %b
   %sub = fsub <2 x float> %a, %mul
@@ -84,7 +84,7 @@ define <2 x float> @fusedMACTest10(<2 x float> %a, <2 x float> %b) {
 }
 
 define <4 x float> @fusedMACTest11(<4 x float> %a, <4 x float> %b) {
-;CHECK: fusedMACTest11:
+;CHECK-LABEL: fusedMACTest11:
 ;CHECK: vfma.f32
   %mul = fmul <4 x float> %a, %b
   %add = fadd <4 x float> %mul, %a
@@ -92,7 +92,7 @@ define <4 x float> @fusedMACTest11(<4 x float> %a, <4 x float> %b) {
 }
 
 define <4 x float> @fusedMACTest12(<4 x float> %a, <4 x float> %b) {
-;CHECK: fusedMACTest12:
+;CHECK-LABEL: fusedMACTest12:
 ;CHECK: vfms.f32
   %mul = fmul <4 x float> %a, %b
   %sub = fsub <4 x float> %a, %mul
diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll
index eb71149..3101500 100644
--- a/test/CodeGen/ARM/globals.ll
+++ b/test/CodeGen/ARM/globals.ll
@@ -57,7 +57,7 @@ define i32 @test1() {
 
 
 
-; LinuxPIC: test1:
+; LinuxPIC-LABEL: test1:
 ; LinuxPIC: 	ldr r0, .LCPI0_0
 ; LinuxPIC: 	ldr r1, .LCPI0_1
 	
diff --git a/test/CodeGen/ARM/hidden-vis-2.ll b/test/CodeGen/ARM/hidden-vis-2.ll
index 8bb2c6e..18d38d4 100644
--- a/test/CodeGen/ARM/hidden-vis-2.ll
+++ b/test/CodeGen/ARM/hidden-vis-2.ll
@@ -4,7 +4,7 @@
 
 define i32 @t() nounwind readonly {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: ldr
 ; CHECK-NEXT: ldr
 	%0 = load i32* @x, align 4		; <i32> [#uses=1]
diff --git a/test/CodeGen/ARM/hidden-vis.ll b/test/CodeGen/ARM/hidden-vis.ll
index 3544ae8..ce2ce2c 100644
--- a/test/CodeGen/ARM/hidden-vis.ll
+++ b/test/CodeGen/ARM/hidden-vis.ll
@@ -6,18 +6,18 @@
 
 define weak hidden void @t1() nounwind {
 ; LINUX: .hidden t1
-; LINUX: t1:
+; LINUX-LABEL: t1:
 
 ; DARWIN: .private_extern _t1
-; DARWIN: t1:
+; DARWIN-LABEL: t1:
   ret void
 }
 
 define weak void @t2() nounwind {
-; LINUX: t2:
+; LINUX-LABEL: t2:
 ; LINUX: .hidden a
 
-; DARWIN: t2:
+; DARWIN-LABEL: t2:
 ; DARWIN: .private_extern _a
   ret void
 }
diff --git a/test/CodeGen/ARM/ifcvt1.ll b/test/CodeGen/ARM/ifcvt1.ll
index fd83144..5a55653 100644
--- a/test/CodeGen/ARM/ifcvt1.ll
+++ b/test/CodeGen/ARM/ifcvt1.ll
@@ -2,8 +2,8 @@
 ; RUN: llc < %s -march=arm -mcpu=swift     | FileCheck %s -check-prefix=SWIFT
 
 define i32 @t1(i32 %a, i32 %b) {
-; A8: t1:
-; SWIFT: t1:
+; A8-LABEL: t1:
+; SWIFT-LABEL: t1:
 	%tmp2 = icmp eq i32 %a, 0
 	br i1 %tmp2, label %cond_false, label %cond_true
 
diff --git a/test/CodeGen/ARM/ifcvt10.ll b/test/CodeGen/ARM/ifcvt10.ll
index a5082d8..26c7272 100644
--- a/test/CodeGen/ARM/ifcvt10.ll
+++ b/test/CodeGen/ARM/ifcvt10.ll
@@ -6,7 +6,7 @@
 
 define void @t(double %a, double %b, double %c, double %d, i32* nocapture %solutions, double* nocapture %x) nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: vpop {d8}
 ; CHECK-NOT: vpopne
 ; CHECK: pop {r7, pc}
diff --git a/test/CodeGen/ARM/ifcvt11.ll b/test/CodeGen/ARM/ifcvt11.ll
index 0f142ee..dba8a3f 100644
--- a/test/CodeGen/ARM/ifcvt11.ll
+++ b/test/CodeGen/ARM/ifcvt11.ll
@@ -6,7 +6,7 @@
 %struct.xyz_t = type { double, double, double }
 
 define i32 @effie(i32 %tsets, %struct.xyz_t* nocapture %p, i32 %a, i32 %b, i32 %c) nounwind readonly noinline {
-; CHECK: effie:
+; CHECK-LABEL: effie:
 entry:
   %0 = icmp sgt i32 %tsets, 0
   br i1 %0, label %bb.nph, label %bb6
diff --git a/test/CodeGen/ARM/ifcvt12.ll b/test/CodeGen/ARM/ifcvt12.ll
index 77bdca5..b61f4e1 100644
--- a/test/CodeGen/ARM/ifcvt12.ll
+++ b/test/CodeGen/ARM/ifcvt12.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s
 define i32 @f1(i32 %a, i32 %b, i32 %c) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mlsne r0, r0, r1, r2
     %tmp1 = icmp eq i32 %a, 0
     br i1 %tmp1, label %cond_false, label %cond_true
diff --git a/test/CodeGen/ARM/ifcvt2.ll b/test/CodeGen/ARM/ifcvt2.ll
index 1bca10a..e34edec 100644
--- a/test/CodeGen/ARM/ifcvt2.ll
+++ b/test/CodeGen/ARM/ifcvt2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s
 
 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: bxlt lr
 	%tmp2 = icmp sgt i32 %c, 10
 	%tmp5 = icmp slt i32 %d, 4
@@ -19,7 +19,7 @@ UnifiedReturnBlock:
 }
 
 define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: bxgt lr
 ; CHECK: cmp
 ; CHECK: addge
diff --git a/test/CodeGen/ARM/ifcvt3.ll b/test/CodeGen/ARM/ifcvt3.ll
index eef4de0..fa7d618 100644
--- a/test/CodeGen/ARM/ifcvt3.ll
+++ b/test/CodeGen/ARM/ifcvt3.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 2
 
 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: cmp r2, #1
 ; CHECK: cmpne r2, #7
 	switch i32 %c, label %cond_next [
diff --git a/test/CodeGen/ARM/ifcvt4.ll b/test/CodeGen/ARM/ifcvt4.ll
index d247f14..53c789d 100644
--- a/test/CodeGen/ARM/ifcvt4.ll
+++ b/test/CodeGen/ARM/ifcvt4.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 
 ; Do not if-convert when branches go to the different loops.
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK-NOT: subgt
 ; CHECK-NOT: suble
 ; Don't use
diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll
index 5081791..31e3e00 100644
--- a/test/CodeGen/ARM/ifcvt5.ll
+++ b/test/CodeGen/ARM/ifcvt5.ll
@@ -12,10 +12,10 @@ entry:
 }
 
 define i32 @t1(i32 %a, i32 %b) {
-; A8: t1:
+; A8-LABEL: t1:
 ; A8: poplt {r7, pc}
 
-; SWIFT: t1:
+; SWIFT-LABEL: t1:
 ; SWIFT: pop {r7, pc}
 ; SWIFT: pop {r7, pc}
 entry:
diff --git a/test/CodeGen/ARM/indirect-reg-input.ll b/test/CodeGen/ARM/indirect-reg-input.ll
index 86728fa..b936455 100644
--- a/test/CodeGen/ARM/indirect-reg-input.ll
+++ b/test/CodeGen/ARM/indirect-reg-input.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mcpu=cortex-a8 2>&1 | FileCheck %s
+; RUN: not llc < %s -march=arm -mcpu=cortex-a8 2>&1 | FileCheck %s
 
 ; Check for error message:
 ; CHECK: error: inline asm not supported yet: don't know how to handle tied indirect register inputs
diff --git a/test/CodeGen/ARM/indirectbr-2.ll b/test/CodeGen/ARM/indirectbr-2.ll
index 084f520..0c41da6 100644
--- a/test/CodeGen/ARM/indirectbr-2.ll
+++ b/test/CodeGen/ARM/indirectbr-2.ll
@@ -8,7 +8,7 @@
 ; The indirect branch has the two destinations as successors. The lone PHI
 ; statement shouldn't be implicitly defined.
 
-; CHECK:      func:
+; CHECK-LABEL:      func:
 ; CHECK:      Ltmp1:    @ Block address taken
 ; CHECK-NOT:            @ implicit-def: R0
 ; CHECK:                @ 4-byte Reload
diff --git a/test/CodeGen/ARM/indirectbr-3.ll b/test/CodeGen/ARM/indirectbr-3.ll
new file mode 100644
index 0000000..5a9c459
--- /dev/null
+++ b/test/CodeGen/ARM/indirectbr-3.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
+
+; If ARMBaseInstrInfo::AnalyzeBlocks returns the wrong value, which was possible
+; for blocks with indirect branches, the IfConverter could end up deleting
+; blocks that were the destinations of indirect branches, leaving branches to
+; nowhere.
+; <rdar://problem/14464830>
+
+define i32 @preserve_blocks(i32 %x) {
+; preserve_blocks:
+; CHECK: Block address taken
+; CHECK: movs r0, #2
+; CHECK: movs r0, #1
+; CHECK-NOT: Address of block that was removed by CodeGen
+entry:
+  %c2 = icmp slt i32 %x, 3
+  %blockaddr = select i1 %c2, i8* blockaddress(@preserve_blocks, %ibt1), i8* blockaddress(@preserve_blocks, %ibt2)
+  %c1 = icmp eq i32 %x, 0
+  br i1 %c1, label %pre_ib, label %nextblock
+
+nextblock:
+  ret i32 3
+
+ibt1:
+  ret i32 2
+
+ibt2:
+  ret i32 1
+
+pre_ib:
+  indirectbr i8* %blockaddr, [ label %ibt1, label %ibt2 ]
+}
diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll
index 341c33f..99e84a6 100644
--- a/test/CodeGen/ARM/indirectbr.ll
+++ b/test/CodeGen/ARM/indirectbr.ll
@@ -6,9 +6,9 @@
 @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
 
 define internal i32 @foo(i32 %i) nounwind {
-; ARM: foo:
-; THUMB: foo:
-; THUMB2: foo:
+; ARM-LABEL: foo:
+; THUMB-LABEL: foo:
+; THUMB2-LABEL: foo:
 entry:
   %0 = load i8** @nextaddr, align 4               ; <i8*> [#uses=2]
   %1 = icmp eq i8* %0, null                       ; <i1> [#uses=1]
@@ -51,12 +51,12 @@ L1:                                               ; preds = %L2, %bb2
 ; ARM: ldr [[R1:r[0-9]+]], LCPI
 ; ARM: add [[R1b:r[0-9]+]], pc, [[R1]]
 ; ARM: str [[R1b]]
-; THUMB: ldr.n
+; THUMB: ldr
 ; THUMB: add
-; THUMB: ldr.n [[R2:r[0-9]+]], LCPI
+; THUMB: ldr [[R2:r[0-9]+]], LCPI
 ; THUMB: add [[R2]], pc
 ; THUMB: str [[R2]]
-; THUMB2: ldr.n [[R2:r[0-9]+]], LCPI
+; THUMB2: ldr [[R2:r[0-9]+]], LCPI
 ; THUMB2-NEXT: str{{(.w)?}} [[R2]]
   store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
   ret i32 %res.3
diff --git a/test/CodeGen/ARM/inlineasm-64bit.ll b/test/CodeGen/ARM/inlineasm-64bit.ll
index be5eb81..b23db10 100644
--- a/test/CodeGen/ARM/inlineasm-64bit.ll
+++ b/test/CodeGen/ARM/inlineasm-64bit.ll
@@ -1,8 +1,8 @@
 ; RUN: llc < %s -O3  -mtriple=arm-linux-gnueabi | FileCheck %s
-
+; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s
 ; check if regs are passing correctly
 define void @i64_write(i64* %p, i64 %val) nounwind {
-; CHECK: i64_write:
+; CHECK-LABEL: i64_write:
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
 ; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
   %1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A teq $0, #0\0A bne 1b", "=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %val) nounwind
@@ -12,7 +12,7 @@ define void @i64_write(i64* %p, i64 %val) nounwind {
 ; check if register allocation can reuse the registers
 define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind {
 entry:
-; CHECK: multi_writes:
+; CHECK-LABEL: multi_writes:
 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
@@ -44,11 +44,44 @@ entry:
 
 ; check if callee-saved registers used by inline asm are saved/restored
 define void @foo(i64* %p, i64 %i) nounwind {
-; CHECK:foo:
-; CHECK: push {{{r[4-9]|r10|r11}}
+; CHECK-LABEL:foo:
+; CHECK: {{push|push.w}} {{{r[4-9]|r10|r11}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
 ; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
-; CHECK: pop {{{r[4-9]|r10|r11}}
+; CHECK: {{pop|pop.w}} {{{r[4-9]|r10|r11}}
   %1 = tail call { i64, i64 } asm sideeffect "@ atomic64_set\0A1: ldrexd $0, ${0:H}, [$3]\0Aldrexd $1, ${1:H}, [$3]\0A strexd $0, $4, ${4:H}, [$3]\0A teq $0, #0\0A bne 1b", "=&r,=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %i) nounwind
   ret void
 }
+
+; return *p;
+define i64 @ldrd_test(i64* %p) nounwind {
+; CHECK-LABEL: ldrd_test:
+  %1 = tail call i64 asm "ldrd $0, ${0:H}, [$1]", "=r,r"(i64* %p) nounwind
+  ret i64 %1
+}
+
+define i64 @QR_test(i64* %p) nounwind {
+; CHECK-LABEL: QR_test:
+; CHECK: ldrd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
+  %1 = tail call i64 asm "ldrd ${0:Q}, ${0:R}, [$1]", "=r,r"(i64* %p) nounwind
+  ret i64 %1
+}
+
+define i64 @defuse_test(i64 %p) nounwind {
+; CHECK-LABEL: defuse_test:
+; CHECK: add {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, #1
+  %1 = tail call i64 asm "add $0, ${0:H}, #1", "=r,0"(i64 %p) nounwind
+  ret i64 %1
+}
+
+; *p = (hi << 32) | lo;
+define void @strd_test(i64* %p, i32 %lo, i32 %hi) nounwind {
+; CHECK-LABEL: strd_test:
+; CHECK: strd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
+  %1 = zext i32 %hi to i64
+  %2 = shl nuw i64 %1, 32
+  %3 = sext i32 %lo to i64
+  %4 = or i64 %2, %3
+  tail call void asm sideeffect "strd $0, ${0:H}, [$1]", "r,r"(i64 %4, i64* %p) nounwind
+  ret void
+}
diff --git a/test/CodeGen/ARM/inlineasm4.ll b/test/CodeGen/ARM/inlineasm4.ll
index 9ed4b99..4a1bcca 100644
--- a/test/CodeGen/ARM/inlineasm4.ll
+++ b/test/CodeGen/ARM/inlineasm4.ll
@@ -4,7 +4,7 @@ define double @f(double %x) {
 entry:
   %0 = tail call double asm "mov     ${0:R}, #4\0A", "=&r"()
   ret double %0
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK:	mov     r1, #4
 }
 
@@ -12,6 +12,6 @@ define double @g(double %x) {
 entry:
   %0 = tail call double asm "mov     ${0:Q}, #4\0A", "=&r"()
   ret double %0
-; CHECK: g:
+; CHECK-LABEL: g:
 ; CHECK:	mov     r0, #4
 }
diff --git a/test/CodeGen/ARM/ldm.ll b/test/CodeGen/ARM/ldm.ll
index db78fd0..d5b805c 100644
--- a/test/CodeGen/ARM/ldm.ll
+++ b/test/CodeGen/ARM/ldm.ll
@@ -4,9 +4,9 @@
 @X = external global [0 x i32]          ; <[0 x i32]*> [#uses=5]
 
 define i32 @t1() {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: pop
-; V4T: t1:
+; V4T-LABEL: t1:
 ; V4T: pop
         %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0)            ; <i32> [#uses=1]
         %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1)           ; <i32> [#uses=1]
@@ -15,9 +15,9 @@ define i32 @t1() {
 }
 
 define i32 @t2() {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: pop
-; V4T: t2:
+; V4T-LABEL: t2:
 ; V4T: pop
         %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2)            ; <i32> [#uses=1]
         %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3)           ; <i32> [#uses=1]
@@ -27,10 +27,10 @@ define i32 @t2() {
 }
 
 define i32 @t3() {
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: ldmib
 ; CHECK: pop
-; V4T: t3:
+; V4T-LABEL: t3:
 ; V4T: ldmib
 ; V4T: pop
 ; V4T-NEXT: bx lr
diff --git a/test/CodeGen/ARM/ldr.ll b/test/CodeGen/ARM/ldr.ll
index 011e61c..e4c695b 100644
--- a/test/CodeGen/ARM/ldr.ll
+++ b/test/CodeGen/ARM/ldr.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 
 define i32 @f1(i32* %v) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldr r0
 entry:
         %tmp = load i32* %v
@@ -9,7 +9,7 @@ entry:
 }
 
 define i32 @f2(i32* %v) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldr r0
 entry:
         %tmp2 = getelementptr i32* %v, i32 1023
@@ -18,7 +18,7 @@ entry:
 }
 
 define i32 @f3(i32* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov
 ; CHECK: ldr r0
 entry:
@@ -28,7 +28,7 @@ entry:
 }
 
 define i32 @f4(i32 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: mvn
 ; CHECK: ldr r0
 entry:
@@ -39,7 +39,7 @@ entry:
 }
 
 define i32 @f5(i32 %base, i32 %offset) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldr r0
 entry:
         %tmp1 = add i32 %base, %offset
@@ -49,7 +49,7 @@ entry:
 }
 
 define i32 @f6(i32 %base, i32 %offset) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ldr r0{{.*}}lsl{{.*}}
 entry:
         %tmp1 = shl i32 %offset, 2
@@ -60,7 +60,7 @@ entry:
 }
 
 define i32 @f7(i32 %base, i32 %offset) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ldr r0{{.*}}lsr{{.*}}
 entry:
         %tmp1 = lshr i32 %offset, 2
diff --git a/test/CodeGen/ARM/ldr_post.ll b/test/CodeGen/ARM/ldr_post.ll
index a6ca434..f5ff7dd 100644
--- a/test/CodeGen/ARM/ldr_post.ll
+++ b/test/CodeGen/ARM/ldr_post.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 ; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: ldr {{.*, \[.*]}}, -r2
 ; CHECK-NOT: ldr
 define i32 @test1(i32 %a, i32 %b, i32 %c) {
@@ -13,7 +13,7 @@ define i32 @test1(i32 %a, i32 %b, i32 %c) {
         ret i32 %tmp5
 }
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: ldr {{.*, \[.*\]}}, #-16
 ; CHECK-NOT: ldr
 define i32 @test2(i32 %a, i32 %b) {
diff --git a/test/CodeGen/ARM/ldr_pre.ll b/test/CodeGen/ARM/ldr_pre.ll
index 6c40ad7..8281827 100644
--- a/test/CodeGen/ARM/ldr_pre.ll
+++ b/test/CodeGen/ARM/ldr_pre.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 ; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: ldr {{.*!}}
 ; CHECK-NOT: ldr
 define i32* @test1(i32* %X, i32* %dest) {
@@ -11,7 +11,7 @@ define i32* @test1(i32* %X, i32* %dest) {
         ret i32* %Y
 }
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: ldr {{.*!}}
 ; CHECK-NOT: ldr
 define i32 @test2(i32 %a, i32 %b, i32 %c) {
diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll
index 73b546d..864d18a 100644
--- a/test/CodeGen/ARM/ldrd.ll
+++ b/test/CodeGen/ARM/ldrd.ll
@@ -13,10 +13,10 @@
 
 define i64 @t(i64 %a) nounwind readonly {
 entry:
-; A8: t:
+; A8-LABEL: t:
 ; A8:   ldrd r2, r3, [r2]
 
-; M3: t:
+; M3-LABEL: t:
 ; M3-NOT: ldrd
 
 	%0 = load i64** @b, align 4
@@ -67,3 +67,31 @@ bb:                                               ; preds = %bb, %entry
 return:                                           ; preds = %bb, %entry
   ret void
 }
+
+; rdar://13978317
+; Pair of loads not formed when lifetime markers are set.
+%struct.Test = type { i32, i32, i32 }
+
+@TestVar = external global %struct.Test
+
+define void @Func1() nounwind ssp {
+; CHECK: @Func1
+entry: 
+; A8: movw [[BASE:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}}
+; A8: movt [[BASE]], :upper16:{{.*}}TestVar{{.*}}
+; A8: ldrd [[FIELD1:r[0-9]+]], [[FIELD2:r[0-9]+]], {{\[}}[[BASE]], #4]
+; A8-NEXT: add [[FIELD1]], [[FIELD2]]
+; A8-NEXT: str [[FIELD1]], {{\[}}[[BASE]]{{\]}}
+  %orig_blocks = alloca [256 x i16], align 2
+  %0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start(i64 512, i8* %0) nounwind
+  %tmp1 = load i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 1), align 4
+  %tmp2 = load i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 2), align 4
+  %add = add nsw i32 %tmp2, %tmp1
+  store i32 %add, i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 0), align 4
+  call void @llvm.lifetime.end(i64 512, i8* %0) nounwind
+  ret void
+}
+
+
+declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
+declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind
diff --git a/test/CodeGen/ARM/ldst-f32-2-i32.ll b/test/CodeGen/ARM/ldst-f32-2-i32.ll
index 1c69e15..61c459c 100644
--- a/test/CodeGen/ARM/ldst-f32-2-i32.ll
+++ b/test/CodeGen/ARM/ldst-f32-2-i32.ll
@@ -3,7 +3,7 @@
 ; rdar://8944252
 
 define void @t(i32 %width, float* nocapture %src, float* nocapture %dst, i32 %index) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 entry:
   %src6 = bitcast float* %src to i8*
   %0 = icmp eq i32 %width, 0
diff --git a/test/CodeGen/ARM/ldstrex.ll b/test/CodeGen/ARM/ldstrex.ll
new file mode 100644
index 0000000..5eaae53
--- /dev/null
+++ b/test/CodeGen/ARM/ldstrex.ll
@@ -0,0 +1,139 @@
+; RUN: llc < %s -mtriple=armv7-apple-darwin   | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin > %t
+; RUN: FileCheck %s < %t
+; RUN: FileCheck %s < %t --check-prefix=CHECK-T2ADDRMODE
+
+%0 = type { i32, i32 }
+
+; CHECK-LABEL: f0:
+; CHECK: ldrexd
+define i64 @f0(i8* %p) nounwind readonly {
+entry:
+  %ldrexd = tail call %0 @llvm.arm.ldrexd(i8* %p)
+  %0 = extractvalue %0 %ldrexd, 1
+  %1 = extractvalue %0 %ldrexd, 0
+  %2 = zext i32 %0 to i64
+  %3 = zext i32 %1 to i64
+  %shl = shl nuw i64 %2, 32
+  %4 = or i64 %shl, %3
+  ret i64 %4
+}
+
+; CHECK-LABEL: f1:
+; CHECK: strexd
+define i32 @f1(i8* %ptr, i64 %val) nounwind {
+entry:
+  %tmp4 = trunc i64 %val to i32
+  %tmp6 = lshr i64 %val, 32
+  %tmp7 = trunc i64 %tmp6 to i32
+  %strexd = tail call i32 @llvm.arm.strexd(i32 %tmp4, i32 %tmp7, i8* %ptr)
+  ret i32 %strexd
+}
+
+declare %0 @llvm.arm.ldrexd(i8*) nounwind readonly
+declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
+
+; CHECK-LABEL: test_load_i8:
+; CHECK: ldrexb r0, [r0]
+; CHECK-NOT: uxtb
+define i32 @test_load_i8(i8* %addr) {
+  %val = call i32 @llvm.arm.ldrex.p0i8(i8* %addr)
+  ret i32 %val
+}
+
+; CHECK-LABEL: test_load_i16:
+; CHECK: ldrexh r0, [r0]
+; CHECK-NOT: uxth
+define i32 @test_load_i16(i16* %addr) {
+  %val = call i32 @llvm.arm.ldrex.p0i16(i16* %addr)
+  ret i32 %val
+}
+
+; CHECK-LABEL: test_load_i32:
+; CHECK: ldrex r0, [r0]
+define i32 @test_load_i32(i32* %addr) {
+  %val = call i32 @llvm.arm.ldrex.p0i32(i32* %addr)
+  ret i32 %val
+}
+
+declare i32 @llvm.arm.ldrex.p0i8(i8*) nounwind readonly
+declare i32 @llvm.arm.ldrex.p0i16(i16*) nounwind readonly
+declare i32 @llvm.arm.ldrex.p0i32(i32*) nounwind readonly
+
+; CHECK-LABEL: test_store_i8:
+; CHECK-NOT: uxtb
+; CHECK: strexb r0, r1, [r2]
+define i32 @test_store_i8(i32, i8 %val, i8* %addr) {
+  %extval = zext i8 %val to i32
+  %res = call i32 @llvm.arm.strex.p0i8(i32 %extval, i8* %addr)
+  ret i32 %res
+}
+
+; CHECK-LABEL: test_store_i16:
+; CHECK-NOT: uxth
+; CHECK: strexh r0, r1, [r2]
+define i32 @test_store_i16(i32, i16 %val, i16* %addr) {
+  %extval = zext i16 %val to i32
+  %res = call i32 @llvm.arm.strex.p0i16(i32 %extval, i16* %addr)
+  ret i32 %res
+}
+
+; CHECK-LABEL: test_store_i32:
+; CHECK: strex r0, r1, [r2]
+define i32 @test_store_i32(i32, i32 %val, i32* %addr) {
+  %res = call i32 @llvm.arm.strex.p0i32(i32 %val, i32* %addr)
+  ret i32 %res
+}
+
+declare i32 @llvm.arm.strex.p0i8(i32, i8*) nounwind
+declare i32 @llvm.arm.strex.p0i16(i32, i16*) nounwind
+declare i32 @llvm.arm.strex.p0i32(i32, i32*) nounwind
+
+; CHECK-LABEL: test_clear:
+; CHECK: clrex
+define void @test_clear() {
+  call void @llvm.arm.clrex()
+  ret void
+}
+
+declare void @llvm.arm.clrex() nounwind
+
+@base = global i32* null
+
+define void @excl_addrmode() {
+; CHECK-T2ADDRMODE-LABEL: excl_addrmode:
+  %base1020 = load i32** @base
+  %offset1020 = getelementptr i32* %base1020, i32 255
+  call i32 @llvm.arm.ldrex.p0i32(i32* %offset1020)
+  call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1020)
+; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [{{r[0-9]+}}, #1020]
+; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}, #1020]
+
+  %base1024 = load i32** @base
+  %offset1024 = getelementptr i32* %base1024, i32 256
+  call i32 @llvm.arm.ldrex.p0i32(i32* %offset1024)
+  call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1024)
+; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], {{r[0-9]+}}, #1024
+; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
+; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
+
+  %base1 = load i32** @base
+  %addr8 = bitcast i32* %base1 to i8*
+  %offset1_8 = getelementptr i8* %addr8, i32 1
+  %offset1 = bitcast i8* %offset1_8 to i32*
+  call i32 @llvm.arm.ldrex.p0i32(i32* %offset1)
+  call i32 @llvm.arm.strex.p0i32(i32 0, i32* %offset1)
+; CHECK-T2ADDRMODE: adds r[[ADDR:[0-9]+]], #1
+; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
+; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
+
+  %local = alloca i8, i32 1024
+  %local32 = bitcast i8* %local to i32*
+  call i32 @llvm.arm.ldrex.p0i32(i32* %local32)
+  call i32 @llvm.arm.strex.p0i32(i32 0, i32* %local32)
+; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp
+; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]
+; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
+
+  ret void
+}
diff --git a/test/CodeGen/ARM/ldstrexd.ll b/test/CodeGen/ARM/ldstrexd.ll
deleted file mode 100644
index 0c0911a..0000000
--- a/test/CodeGen/ARM/ldstrexd.ll
+++ /dev/null
@@ -1,33 +0,0 @@
-; RUN: llc < %s -mtriple=armv7-apple-darwin   | FileCheck %s
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
-
-%0 = type { i32, i32 }
-
-; CHECK: f0:
-; CHECK: ldrexd
-define i64 @f0(i8* %p) nounwind readonly {
-entry:
-  %ldrexd = tail call %0 @llvm.arm.ldrexd(i8* %p)
-  %0 = extractvalue %0 %ldrexd, 1
-  %1 = extractvalue %0 %ldrexd, 0
-  %2 = zext i32 %0 to i64
-  %3 = zext i32 %1 to i64
-  %shl = shl nuw i64 %2, 32
-  %4 = or i64 %shl, %3
-  ret i64 %4
-}
-
-; CHECK: f1:
-; CHECK: strexd
-define i32 @f1(i8* %ptr, i64 %val) nounwind {
-entry:
-  %tmp4 = trunc i64 %val to i32
-  %tmp6 = lshr i64 %val, 32
-  %tmp7 = trunc i64 %tmp6 to i32
-  %strexd = tail call i32 @llvm.arm.strexd(i32 %tmp4, i32 %tmp7, i8* %ptr)
-  ret i32 %strexd
-}
-
-declare %0 @llvm.arm.ldrexd(i8*) nounwind readonly
-declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
-
diff --git a/test/CodeGen/ARM/load-address-masked.ll b/test/CodeGen/ARM/load-address-masked.ll
index 43c98e4..65cc311 100644
--- a/test/CodeGen/ARM/load-address-masked.ll
+++ b/test/CodeGen/ARM/load-address-masked.ll
@@ -10,5 +10,5 @@ entry:
   ret i32 and (i32 ptrtoint (i32* @a to i32), i32 255)
 }
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: ldrb    r0, .LCPI0_0
diff --git a/test/CodeGen/ARM/load-global.ll b/test/CodeGen/ARM/load-global.ll
index 15a415d..00ca2e8 100644
--- a/test/CodeGen/ARM/load-global.ll
+++ b/test/CodeGen/ARM/load-global.ll
@@ -26,7 +26,7 @@ define i32 @test1() {
 ; PIC: .long L_G$non_lazy_ptr-(LPC0_0+8)
 
 ; PIC_T: _test1
-; PIC_T: ldr.n r0, LCPI0_0
+; PIC_T: ldr r0, LCPI0_0
 ; PIC_T: add r0, pc
 ; PIC_T: ldr r0, [r0]
 ; PIC_T: ldr r0, [r0]
diff --git a/test/CodeGen/ARM/load_i1_select.ll b/test/CodeGen/ARM/load_i1_select.ll
index bdd4081..7a208ea 100644
--- a/test/CodeGen/ARM/load_i1_select.ll
+++ b/test/CodeGen/ARM/load_i1_select.ll
@@ -6,7 +6,7 @@ target triple = "thumbv7-apple-ios0.0.0"
 ; Codegen should only compare one bit of the loaded value.
 ; rdar://10887484
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: ldrb r[[R0:[0-9]+]], [r0]
 ; CHECK: tst.w r[[R0]], #1
 define void @foo(i8* %call, double* %p) nounwind {
diff --git a/test/CodeGen/ARM/long.ll b/test/CodeGen/ARM/long.ll
index 0f1c7be..7fffc81 100644
--- a/test/CodeGen/ARM/long.ll
+++ b/test/CodeGen/ARM/long.ll
@@ -1,33 +1,33 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 entry:
         ret i64 0
 }
 
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 entry:
         ret i64 1
 }
 
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvn r0, #-2147483648
 entry:
         ret i64 2147483647
 }
 
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mov r0, #-2147483648
 entry:
         ret i64 2147483648
 }
 
 define i64 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvn r0, #0
 ; CHECK: mvn r1, #-2147483648
 entry:
@@ -35,7 +35,7 @@ entry:
 }
 
 define i64 @f6(i64 %x, i64 %y) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: adds
 ; CHECK: adc
 entry:
@@ -44,7 +44,7 @@ entry:
 }
 
 define void @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 entry:
         %tmp = call i64 @f8( )          ; <i64> [#uses=0]
         ret void
@@ -53,7 +53,7 @@ entry:
 declare i64 @f8()
 
 define i64 @f9(i64 %a, i64 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: subs r
 ; CHECK: sbc
 entry:
@@ -62,7 +62,7 @@ entry:
 }
 
 define i64 @f(i32 %a, i32 %b) {
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: smull
 entry:
         %tmp = sext i32 %a to i64               ; <i64> [#uses=1]
@@ -72,7 +72,7 @@ entry:
 }
 
 define i64 @g(i32 %a, i32 %b) {
-; CHECK: g:
+; CHECK-LABEL: g:
 ; CHECK: umull
 entry:
         %tmp = zext i32 %a to i64               ; <i64> [#uses=1]
@@ -82,7 +82,7 @@ entry:
 }
 
 define i64 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 entry:
         %a = alloca i64, align 8                ; <i64*> [#uses=1]
         %retval = load i64* %a          ; <i64> [#uses=1]
diff --git a/test/CodeGen/ARM/longMAC.ll b/test/CodeGen/ARM/longMAC.ll
index e4a00e9..2cf91c3 100644
--- a/test/CodeGen/ARM/longMAC.ll
+++ b/test/CodeGen/ARM/longMAC.ll
@@ -2,7 +2,7 @@
 ; Check generated signed and unsigned multiply accumulate long.
 
 define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
-;CHECK: MACLongTest1:
+;CHECK-LABEL: MACLongTest1:
 ;CHECK: umlal
   %conv = zext i32 %a to i64
   %conv1 = zext i32 %b to i64
@@ -12,7 +12,7 @@ define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
 }
 
 define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c)  {
-;CHECK: MACLongTest2:
+;CHECK-LABEL: MACLongTest2:
 ;CHECK: smlal
   %conv = sext i32 %a to i64
   %conv1 = sext i32 %b to i64
@@ -22,7 +22,7 @@ define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c)  {
 }
 
 define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {
-;CHECK: MACLongTest3:
+;CHECK-LABEL: MACLongTest3:
 ;CHECK: umlal
   %conv = zext i32 %b to i64
   %conv1 = zext i32 %a to i64
@@ -33,7 +33,7 @@ define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {
 }
 
 define i64 @MACLongTest4(i32 %a, i32 %b, i32 %c) {
-;CHECK: MACLongTest4:
+;CHECK-LABEL: MACLongTest4:
 ;CHECK: smlal
   %conv = sext i32 %b to i64
   %conv1 = sext i32 %a to i64
diff --git a/test/CodeGen/ARM/lsr-icmp-imm.ll b/test/CodeGen/ARM/lsr-icmp-imm.ll
index 248c4bd..103642b 100644
--- a/test/CodeGen/ARM/lsr-icmp-imm.ll
+++ b/test/CodeGen/ARM/lsr-icmp-imm.ll
@@ -4,7 +4,7 @@
 ; LSR should compare against the post-incremented induction variable.
 ; In this case, the immediate value is -2 which requires a cmn instruction.
 ;
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: %for.body
 ; CHECK: sub{{.*}}[[IV:r[0-9]+]], #2
 ; CHECK: cmn{{.*}}[[IV]], #2
diff --git a/test/CodeGen/ARM/lsr-unfolded-offset.ll b/test/CodeGen/ARM/lsr-unfolded-offset.ll
index 9b0f3e5..26d4be2 100644
--- a/test/CodeGen/ARM/lsr-unfolded-offset.ll
+++ b/test/CodeGen/ARM/lsr-unfolded-offset.ll
@@ -7,8 +7,7 @@
 ; CHECK: sub sp, #{{40|32|28|24}}
 
 ; CHECK: %for.inc
-; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
-; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
+; CHECK-NOT: ldr
 ; CHECK: add
 
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
diff --git a/test/CodeGen/ARM/machine-cse-cmp.ll b/test/CodeGen/ARM/machine-cse-cmp.ll
index 03abd76..7e4b309 100644
--- a/test/CodeGen/ARM/machine-cse-cmp.ll
+++ b/test/CodeGen/ARM/machine-cse-cmp.ll
@@ -6,7 +6,7 @@
 
 define i32 @f1(i32 %cond1, i32 %x1, i32 %x2, i32 %x3) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cmp
 ; CHECK: moveq
 ; CHECK-NOT: cmp
@@ -25,7 +25,7 @@ entry:
 ; rdar://10660865
 define void @f2() nounwind ssp {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cmp
 ; CHECK: poplt
 ; CHECK-NOT: cmp
@@ -49,7 +49,7 @@ declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
 ; rdar://12462006
 define i8* @f3(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: sub
 ; CHECK: cmp
 ; CHECK: blt
diff --git a/test/CodeGen/ARM/machine-licm.ll b/test/CodeGen/ARM/machine-licm.ll
index 8656c5b..fc9b226 100644
--- a/test/CodeGen/ARM/machine-licm.ll
+++ b/test/CodeGen/ARM/machine-licm.ll
@@ -12,7 +12,7 @@
 
 define void @t(i32* nocapture %vals, i32 %c) nounwind {
 entry:
-; ARM: t:
+; ARM-LABEL: t:
 ; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0
 ; Unfortunately currently ARM codegen doesn't cse the ldr from constantpool.
 ; The issue is it can be read by an "add pc" or a "ldr [pc]" so it's messy
@@ -23,14 +23,14 @@ entry:
 ; ARM: ldr r{{[0-9]+}}, [pc, [[REGISTER_1]]]
 ; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
 
-; MOVT: t:
+; MOVT-LABEL: t:
 ; MOVT: movw [[REGISTER_2:r[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+8))
 ; MOVT: movt [[REGISTER_2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+8))
 ; MOVT: LPC0_0:
 ; MOVT: ldr r{{[0-9]+}}, [pc, [[REGISTER_2]]]
 ; MOVT: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
 
-; THUMB: t:
+; THUMB-LABEL: t:
   %0 = icmp eq i32 %c, 0                          ; <i1> [#uses=1]
   br i1 %0, label %return, label %bb.nph
 
@@ -40,7 +40,7 @@ bb.nph:                                           ; preds = %entry
 ; ARM: .section
 
 ; THUMB: BB#1
-; THUMB: ldr.n r2, LCPI0_0
+; THUMB: ldr r2, LCPI0_0
 ; THUMB: add r2, pc
 ; THUMB: ldr r{{[0-9]+}}, [r2]
 ; THUMB: LBB0_2
diff --git a/test/CodeGen/ARM/memcpy-inline.ll b/test/CodeGen/ARM/memcpy-inline.ll
index d846e5c..946c63e 100644
--- a/test/CodeGen/ARM/memcpy-inline.ll
+++ b/test/CodeGen/ARM/memcpy-inline.ll
@@ -15,7 +15,7 @@
 
 define i32 @t0() {
 entry:
-; CHECK: t0:
+; CHECK-LABEL: t0:
 ; CHECK: vldr [[REG1:d[0-9]+]],
 ; CHECK: vstr [[REG1]], 
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false)
@@ -24,7 +24,7 @@ entry:
 
 define void @t1(i8* nocapture %C) nounwind {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
 ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
 ; CHECK: adds r0, #15
@@ -37,7 +37,7 @@ entry:
 
 define void @t2(i8* nocapture %C) nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: ldr [[REG2:r[0-9]+]], [r1, #32]
 ; CHECK: str [[REG2]], [r0, #32]
 ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
@@ -52,7 +52,7 @@ entry:
 
 define void @t3(i8* nocapture %C) nounwind {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
 ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
 ; CHECK: adds r0, #16
@@ -65,7 +65,7 @@ entry:
 
 define void @t4(i8* nocapture %C) nounwind {
 entry:
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: vld1.8 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1]
 ; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
@@ -74,7 +74,7 @@ entry:
 
 define void @t5(i8* nocapture %C) nounwind {
 entry:
-; CHECK: t5:
+; CHECK-LABEL: t5:
 ; CHECK: movs [[REG5:r[0-9]+]], #0
 ; CHECK: strb [[REG5]], [r0, #6]
 ; CHECK: movw [[REG6:r[0-9]+]], #21587
@@ -87,7 +87,7 @@ entry:
 
 define void @t6() nounwind {
 entry:
-; CHECK: t6:
+; CHECK-LABEL: t6:
 ; CHECK: vld1.8 {[[REG8:d[0-9]+]]}, [r0]
 ; CHECK: vstr [[REG8]], [r1]
 ; CHECK: adds r1, #6
diff --git a/test/CodeGen/ARM/memset-inline.ll b/test/CodeGen/ARM/memset-inline.ll
index ee8c364..4e86d05 100644
--- a/test/CodeGen/ARM/memset-inline.ll
+++ b/test/CodeGen/ARM/memset-inline.ll
@@ -2,7 +2,7 @@
 
 define void @t1(i8* nocapture %c) nounwind optsize {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: movs r1, #0
 ; CHECK: str r1, [r0]
 ; CHECK: str r1, [r0, #4]
@@ -13,7 +13,7 @@ entry:
 
 define void @t2() nounwind ssp {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: add.w r1, r0, #10
 ; CHECK: vmov.i32 {{q[0-9]+}}, #0x0
 ; CHECK: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
diff --git a/test/CodeGen/ARM/misched-copy-arm.ll b/test/CodeGen/ARM/misched-copy-arm.ll
index 4b15326..c274545 100644
--- a/test/CodeGen/ARM/misched-copy-arm.ll
+++ b/test/CodeGen/ARM/misched-copy-arm.ll
@@ -1,5 +1,5 @@
 ; REQUIRES: asserts
-; RUN: llc < %s -march=thumb -mcpu=swift -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
+; RUN: llc < %s -march=thumb -mcpu=swift -pre-RA-sched=source -join-globalcopies -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
 ;
 ; Loop counter copies should be eliminated.
 ; There is also a MUL here, but we don't care where it is scheduled.
@@ -28,3 +28,56 @@ for.end:                                          ; preds = %for.body, %entry
   %s.0.lcssa = phi i32 [ 0, %entry ], [ %mul, %for.body ]
   ret i32 %s.0.lcssa
 }
+
+
+; This case was a crasher in constrainLocalCopy.
+; The problem was the t2LDR_PRE defining both the global and local lrg.
+; CHECK-LABEL: *** Final schedule for BB#5 ***
+; CHECK: %[[R4:vreg[0-9]+]]<def>, %[[R1:vreg[0-9]+]]<def,tied2> = t2LDR_PRE %[[R1]]<tied1>
+; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R1]]
+; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R4]]
+; CHECK-LABEL: MACHINEINSTRS
+%struct.rtx_def = type { [4 x i8], [1 x %union.rtunion_def] }
+%union.rtunion_def = type { i64 }
+
+; Function Attrs: nounwind ssp
+declare hidden fastcc void @df_ref_record(i32* nocapture, %struct.rtx_def*, %struct.rtx_def**, %struct.rtx_def*, i32, i32) #0
+
+; Function Attrs: nounwind ssp
+define hidden fastcc void @df_def_record_1(i32* nocapture %df, %struct.rtx_def* %x, %struct.rtx_def* %insn) #0 {
+entry:
+  br label %while.cond
+
+while.cond:                                       ; preds = %if.end28, %entry
+  %loc.0 = phi %struct.rtx_def** [ %rtx31, %if.end28 ], [ undef, %entry ]
+  %dst.0 = phi %struct.rtx_def* [ %0, %if.end28 ], [ undef, %entry ]
+  switch i32 undef, label %if.end47 [
+    i32 61, label %if.then46
+    i32 64, label %if.then24
+    i32 132, label %if.end28
+    i32 133, label %if.end28
+  ]
+
+if.then24:                                        ; preds = %while.cond
+  br label %if.end28
+
+if.end28:                                         ; preds = %if.then24, %while.cond, %while.cond
+  %dst.1 = phi %struct.rtx_def* [ undef, %if.then24 ], [ %dst.0, %while.cond ], [ %dst.0, %while.cond ]
+  %arrayidx30 = getelementptr inbounds %struct.rtx_def* %dst.1, i32 0, i32 1, i32 0
+  %rtx31 = bitcast %union.rtunion_def* %arrayidx30 to %struct.rtx_def**
+  %0 = load %struct.rtx_def** %rtx31, align 4, !tbaa !0
+  br label %while.cond
+
+if.then46:                                        ; preds = %while.cond
+  tail call fastcc void @df_ref_record(i32* %df, %struct.rtx_def* %dst.0, %struct.rtx_def** %loc.0, %struct.rtx_def* %insn, i32 0, i32 undef)
+  unreachable
+
+if.end47:                                         ; preds = %while.cond
+  ret void
+}
+
+attributes #0 = { nounwind ssp }
+
+!0 = metadata !{metadata !"any pointer", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA"}
diff --git a/test/CodeGen/ARM/mls.ll b/test/CodeGen/ARM/mls.ll
index 066bf98..8f0d3a8 100644
--- a/test/CodeGen/ARM/mls.ll
+++ b/test/CodeGen/ARM/mls.ll
@@ -14,15 +14,15 @@ define i32 @f2(i32 %a, i32 %b, i32 %c) {
     ret i32 %tmp2
 }
 
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mls	r0, r0, r1, r2
-; NO_MULOPS: f1:
+; NO_MULOPS-LABEL: f1:
 ; NO_MULOPS: mul r0, r0, r1
 ; NO_MULOPS-NEXT: sub r0, r2, r0
 
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mul r0, r0, r1
 ; CHECK-NEXT: sub r0, r0, r2
-; NO_MULOPS: f2:
+; NO_MULOPS-LABEL: f2:
 ; NO_MULOPS: mul r0, r0, r1
 ; NO_MULOPS-NEXT: sub r0, r0, r2
diff --git a/test/CodeGen/ARM/movt.ll b/test/CodeGen/ARM/movt.ll
index e82aca0..25c1bfe 100644
--- a/test/CodeGen/ARM/movt.ll
+++ b/test/CodeGen/ARM/movt.ll
@@ -2,7 +2,7 @@
 ; rdar://7317664
 
 define i32 @t(i32 %X) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movt r0, #65535
 entry:
 	%0 = or i32 %X, -65536
@@ -10,7 +10,7 @@ entry:
 }
 
 define i32 @t2(i32 %X) nounwind {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: movt r0, #65534
 entry:
 	%0 = or i32 %X, -131072
diff --git a/test/CodeGen/ARM/mul_const.ll b/test/CodeGen/ARM/mul_const.ll
index c50a233..482d8f2 100644
--- a/test/CodeGen/ARM/mul_const.ll
+++ b/test/CodeGen/ARM/mul_const.ll
@@ -2,7 +2,7 @@
 
 define i32 @t9(i32 %v) nounwind readnone {
 entry:
-; CHECK: t9:
+; CHECK-LABEL: t9:
 ; CHECK: add r0, r0, r0, lsl #3
 	%0 = mul i32 %v, 9
 	ret i32 %0
@@ -10,7 +10,7 @@ entry:
 
 define i32 @t7(i32 %v) nounwind readnone {
 entry:
-; CHECK: t7:
+; CHECK-LABEL: t7:
 ; CHECK: rsb r0, r0, r0, lsl #3
 	%0 = mul i32 %v, 7
 	ret i32 %0
@@ -18,7 +18,7 @@ entry:
 
 define i32 @t5(i32 %v) nounwind readnone {
 entry:
-; CHECK: t5:
+; CHECK-LABEL: t5:
 ; CHECK: add r0, r0, r0, lsl #2
         %0 = mul i32 %v, 5
         ret i32 %0
@@ -26,7 +26,7 @@ entry:
 
 define i32 @t3(i32 %v) nounwind readnone {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: add r0, r0, r0, lsl #1
         %0 = mul i32 %v, 3
         ret i32 %0
@@ -34,7 +34,7 @@ entry:
 
 define i32 @t12288(i32 %v) nounwind readnone {
 entry:
-; CHECK: t12288:
+; CHECK-LABEL: t12288:
 ; CHECK: add r0, r0, r0, lsl #1
 ; CHECK: lsl{{.*}}#12
         %0 = mul i32 %v, 12288
@@ -43,7 +43,7 @@ entry:
 
 define i32 @tn9(i32 %v) nounwind readnone {
 entry:
-; CHECK: tn9:
+; CHECK-LABEL: tn9:
 ; CHECK: add	r0, r0, r0, lsl #3
 ; CHECK: rsb	r0, r0, #0
         %0 = mul i32 %v, -9
@@ -52,7 +52,7 @@ entry:
 
 define i32 @tn7(i32 %v) nounwind readnone {
 entry:
-; CHECK: tn7:
+; CHECK-LABEL: tn7:
 ; CHECK: sub r0, r0, r0, lsl #3
 	%0 = mul i32 %v, -7
 	ret i32 %0
@@ -60,7 +60,7 @@ entry:
 
 define i32 @tn5(i32 %v) nounwind readnone {
 entry:
-; CHECK: tn5:
+; CHECK-LABEL: tn5:
 ; CHECK: add r0, r0, r0, lsl #2
 ; CHECK: rsb r0, r0, #0
         %0 = mul i32 %v, -5
@@ -69,7 +69,7 @@ entry:
 
 define i32 @tn3(i32 %v) nounwind readnone {
 entry:
-; CHECK: tn3:
+; CHECK-LABEL: tn3:
 ; CHECK: sub r0, r0, r0, lsl #2
         %0 = mul i32 %v, -3
         ret i32 %0
@@ -77,7 +77,7 @@ entry:
 
 define i32 @tn12288(i32 %v) nounwind readnone {
 entry:
-; CHECK: tn12288:
+; CHECK-LABEL: tn12288:
 ; CHECK: sub r0, r0, r0, lsl #2
 ; CHECK: lsl{{.*}}#12
         %0 = mul i32 %v, -12288
diff --git a/test/CodeGen/ARM/mulhi.ll b/test/CodeGen/ARM/mulhi.ll
index 932004c..63705c5 100644
--- a/test/CodeGen/ARM/mulhi.ll
+++ b/test/CodeGen/ARM/mulhi.ll
@@ -3,13 +3,13 @@
 ; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=M3
 
 define i32 @smulhi(i32 %x, i32 %y) nounwind {
-; V6: smulhi:
+; V6-LABEL: smulhi:
 ; V6: smmul
 
-; V4: smulhi:
+; V4-LABEL: smulhi:
 ; V4: smull
 
-; M3: smulhi:
+; M3-LABEL: smulhi:
 ; M3: smull
         %tmp = sext i32 %x to i64               ; <i64> [#uses=1]
         %tmp1 = sext i32 %y to i64              ; <i64> [#uses=1]
@@ -20,13 +20,13 @@ define i32 @smulhi(i32 %x, i32 %y) nounwind {
 }
 
 define i32 @umulhi(i32 %x, i32 %y) nounwind {
-; V6: umulhi:
+; V6-LABEL: umulhi:
 ; V6: umull
 
-; V4: umulhi:
+; V4-LABEL: umulhi:
 ; V4: umull
 
-; M3: umulhi:
+; M3-LABEL: umulhi:
 ; M3: umull
         %tmp = zext i32 %x to i64               ; <i64> [#uses=1]
         %tmp1 = zext i32 %y to i64              ; <i64> [#uses=1]
@@ -38,13 +38,13 @@ define i32 @umulhi(i32 %x, i32 %y) nounwind {
 
 ; rdar://r10152911
 define i32 @t3(i32 %a) nounwind {
-; V6: t3:
+; V6-LABEL: t3:
 ; V6: smmla
 
-; V4: t3:
+; V4-LABEL: t3:
 ; V4: smull
 
-; M3: t3:
+; M3-LABEL: t3:
 ; M3-NOT: smmla
 ; M3: smull
 entry:
diff --git a/test/CodeGen/ARM/mvn.ll b/test/CodeGen/ARM/mvn.ll
index 571c21a..2c5ccd7 100644
--- a/test/CodeGen/ARM/mvn.ll
+++ b/test/CodeGen/ARM/mvn.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm | grep mvn | count 8
+; RUN: llc < %s -march=arm | grep mvn | count 9
 
 define i32 @f1() {
 entry:
diff --git a/test/CodeGen/ARM/neon-spfp.ll b/test/CodeGen/ARM/neon-spfp.ll
index c00f0d1..5385668 100644
--- a/test/CodeGen/ARM/neon-spfp.ll
+++ b/test/CodeGen/ARM/neon-spfp.ll
@@ -21,21 +21,21 @@
 
 @.str = private unnamed_addr constant [12 x i8] c"S317\09%.5g \0A\00", align 1
 
-; CHECK-LINUXA5: main:
-; CHECK-LINUXA8: main:
-; CHECK-LINUXA9: main:
-; CHECK-LINUXA15: main:
-; CHECK-LINUXSWIFT: main:
-; CHECK-UNSAFEA5: main:
-; CHECK-UNSAFEA8: main:
-; CHECK-UNSAFEA9: main:
-; CHECK-UNSAFEA15: main:
-; CHECK-UNSAFESWIFT: main:
-; CHECK-DARWINA5: main:
-; CHECK-DARWINA8: main:
-; CHECK-DARWINA9: main:
-; CHECK-DARWINA15: main:
-; CHECK-DARWINSWIFT: main:
+; CHECK-LINUXA5-LABEL: main:
+; CHECK-LINUXA8-LABEL: main:
+; CHECK-LINUXA9-LABEL: main:
+; CHECK-LINUXA15-LABEL: main:
+; CHECK-LINUXSWIFT-LABEL: main:
+; CHECK-UNSAFEA5-LABEL: main:
+; CHECK-UNSAFEA8-LABEL: main:
+; CHECK-UNSAFEA9-LABEL: main:
+; CHECK-UNSAFEA15-LABEL: main:
+; CHECK-UNSAFESWIFT-LABEL: main:
+; CHECK-DARWINA5-LABEL: main:
+; CHECK-DARWINA8-LABEL: main:
+; CHECK-DARWINA9-LABEL: main:
+; CHECK-DARWINA15-LABEL: main:
+; CHECK-DARWINSWIFT-LABEL: main:
 define i32 @main() {
 entry:
   br label %for.body
diff --git a/test/CodeGen/ARM/neon_minmax.ll b/test/CodeGen/ARM/neon_minmax.ll
index 0a7c8b2..2e45919 100644
--- a/test/CodeGen/ARM/neon_minmax.ll
+++ b/test/CodeGen/ARM/neon_minmax.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
 
 define float @fmin_ole(float %x) nounwind {
-;CHECK: fmin_ole:
+;CHECK-LABEL: fmin_ole:
 ;CHECK: vmin.f32
   %cond = fcmp ole float 1.0, %x
   %min1 = select i1 %cond, float 1.0, float %x
@@ -9,7 +9,7 @@ define float @fmin_ole(float %x) nounwind {
 }
 
 define float @fmin_ole_zero(float %x) nounwind {
-;CHECK: fmin_ole_zero:
+;CHECK-LABEL: fmin_ole_zero:
 ;CHECK-NOT: vmin.f32
   %cond = fcmp ole float 0.0, %x
   %min1 = select i1 %cond, float 0.0, float %x
@@ -17,7 +17,7 @@ define float @fmin_ole_zero(float %x) nounwind {
 }
 
 define float @fmin_ult(float %x) nounwind {
-;CHECK: fmin_ult:
+;CHECK-LABEL: fmin_ult:
 ;CHECK: vmin.f32
   %cond = fcmp ult float %x, 1.0
   %min1 = select i1 %cond, float %x, float 1.0
@@ -25,7 +25,7 @@ define float @fmin_ult(float %x) nounwind {
 }
 
 define float @fmax_ogt(float %x) nounwind {
-;CHECK: fmax_ogt:
+;CHECK-LABEL: fmax_ogt:
 ;CHECK: vmax.f32
   %cond = fcmp ogt float 1.0, %x
   %max1 = select i1 %cond, float 1.0, float %x
@@ -33,7 +33,7 @@ define float @fmax_ogt(float %x) nounwind {
 }
 
 define float @fmax_uge(float %x) nounwind {
-;CHECK: fmax_uge:
+;CHECK-LABEL: fmax_uge:
 ;CHECK: vmax.f32
   %cond = fcmp uge float %x, 1.0
   %max1 = select i1 %cond, float %x, float 1.0
@@ -41,7 +41,7 @@ define float @fmax_uge(float %x) nounwind {
 }
 
 define float @fmax_uge_zero(float %x) nounwind {
-;CHECK: fmax_uge_zero:
+;CHECK-LABEL: fmax_uge_zero:
 ;CHECK-NOT: vmax.f32
   %cond = fcmp uge float %x, 0.0
   %max1 = select i1 %cond, float %x, float 0.0
@@ -49,7 +49,7 @@ define float @fmax_uge_zero(float %x) nounwind {
 }
 
 define float @fmax_olt_reverse(float %x) nounwind {
-;CHECK: fmax_olt_reverse:
+;CHECK-LABEL: fmax_olt_reverse:
 ;CHECK: vmax.f32
   %cond = fcmp olt float %x, 1.0
   %max1 = select i1 %cond, float 1.0, float %x
@@ -57,7 +57,7 @@ define float @fmax_olt_reverse(float %x) nounwind {
 }
 
 define float @fmax_ule_reverse(float %x) nounwind {
-;CHECK: fmax_ule_reverse:
+;CHECK-LABEL: fmax_ule_reverse:
 ;CHECK: vmax.f32
   %cond = fcmp ult float 1.0, %x
   %max1 = select i1 %cond, float %x, float 1.0
@@ -65,7 +65,7 @@ define float @fmax_ule_reverse(float %x) nounwind {
 }
 
 define float @fmin_oge_reverse(float %x) nounwind {
-;CHECK: fmin_oge_reverse:
+;CHECK-LABEL: fmin_oge_reverse:
 ;CHECK: vmin.f32
   %cond = fcmp oge float %x, 1.0
   %min1 = select i1 %cond, float 1.0, float %x
@@ -73,7 +73,7 @@ define float @fmin_oge_reverse(float %x) nounwind {
 }
 
 define float @fmin_ugt_reverse(float %x) nounwind {
-;CHECK: fmin_ugt_reverse:
+;CHECK-LABEL: fmin_ugt_reverse:
 ;CHECK: vmin.f32
   %cond = fcmp ugt float 1.0, %x
   %min1 = select i1 %cond, float %x, float 1.0
diff --git a/test/CodeGen/ARM/neon_vabs.ll b/test/CodeGen/ARM/neon_vabs.ll
index bf2770b..76b6044 100644
--- a/test/CodeGen/ARM/neon_vabs.ll
+++ b/test/CodeGen/ARM/neon_vabs.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <4 x i32> @test1(<4 x i32> %a) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: vabs.s32 q
         %tmp1neg = sub <4 x i32> zeroinitializer, %a
         %b = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -10,7 +10,7 @@ define <4 x i32> @test1(<4 x i32> %a) nounwind {
 }
 
 define <4 x i32> @test2(<4 x i32> %a) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: vabs.s32 q
         %tmp1neg = sub <4 x i32> zeroinitializer, %a
         %b = icmp sge <4 x i32> %a, zeroinitializer
@@ -19,7 +19,7 @@ define <4 x i32> @test2(<4 x i32> %a) nounwind {
 }
 
 define <8 x i16> @test3(<8 x i16> %a) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: vabs.s16 q
         %tmp1neg = sub <8 x i16> zeroinitializer, %a
         %b = icmp sgt <8 x i16> %a, zeroinitializer
@@ -28,7 +28,7 @@ define <8 x i16> @test3(<8 x i16> %a) nounwind {
 }
 
 define <16 x i8> @test4(<16 x i8> %a) nounwind {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: vabs.s8 q
         %tmp1neg = sub <16 x i8> zeroinitializer, %a
         %b = icmp slt <16 x i8> %a, zeroinitializer
@@ -37,7 +37,7 @@ define <16 x i8> @test4(<16 x i8> %a) nounwind {
 }
 
 define <4 x i32> @test5(<4 x i32> %a) nounwind {
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: vabs.s32 q
         %tmp1neg = sub <4 x i32> zeroinitializer, %a
         %b = icmp sle <4 x i32> %a, zeroinitializer
@@ -46,7 +46,7 @@ define <4 x i32> @test5(<4 x i32> %a) nounwind {
 }
 
 define <2 x i32> @test6(<2 x i32> %a) nounwind {
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: vabs.s32 d
         %tmp1neg = sub <2 x i32> zeroinitializer, %a
         %b = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
@@ -55,7 +55,7 @@ define <2 x i32> @test6(<2 x i32> %a) nounwind {
 }
 
 define <2 x i32> @test7(<2 x i32> %a) nounwind {
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: vabs.s32 d
         %tmp1neg = sub <2 x i32> zeroinitializer, %a
         %b = icmp sge <2 x i32> %a, zeroinitializer
@@ -64,7 +64,7 @@ define <2 x i32> @test7(<2 x i32> %a) nounwind {
 }
 
 define <4 x i16> @test8(<4 x i16> %a) nounwind {
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: vabs.s16 d
         %tmp1neg = sub <4 x i16> zeroinitializer, %a
         %b = icmp sgt <4 x i16> %a, zeroinitializer
@@ -73,7 +73,7 @@ define <4 x i16> @test8(<4 x i16> %a) nounwind {
 }
 
 define <8 x i8> @test9(<8 x i8> %a) nounwind {
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: vabs.s8 d
         %tmp1neg = sub <8 x i8> zeroinitializer, %a
         %b = icmp slt <8 x i8> %a, zeroinitializer
@@ -82,7 +82,7 @@ define <8 x i8> @test9(<8 x i8> %a) nounwind {
 }
 
 define <2 x i32> @test10(<2 x i32> %a) nounwind {
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: vabs.s32 d
         %tmp1neg = sub <2 x i32> zeroinitializer, %a
         %b = icmp sle <2 x i32> %a, zeroinitializer
diff --git a/test/CodeGen/ARM/pack.ll b/test/CodeGen/ARM/pack.ll
index 9015176..fbc1155 100644
--- a/test/CodeGen/ARM/pack.ll
+++ b/test/CodeGen/ARM/pack.ll
@@ -78,11 +78,34 @@ define i32 @test7(i32 %X, i32 %Y) {
 	ret i32 %tmp57
 }
 
+; Arithmetic and logic right shift does not have the same semantics if shifting
+; by more than 16 in this context.
+
 ; CHECK: test8
-; CHECK: pkhtb   r0, r0, r1, asr #22
+; CHECK-NOT: pkhtb   r0, r0, r1, asr #22
 define i32 @test8(i32 %X, i32 %Y) {
 	%tmp1 = and i32 %X, -65536
 	%tmp3 = lshr i32 %Y, 22
 	%tmp57 = or i32 %tmp3, %tmp1
 	ret i32 %tmp57
 }
+
+; CHECK-LABEL: test9:
+; CHECK: pkhtb r0, r0, r1, asr #16
+define i32 @test9(i32 %src1, i32 %src2) {
+entry:
+    %tmp = and i32 %src1, -65536
+    %tmp2 = lshr i32 %src2, 16
+    %tmp3 = or i32 %tmp, %tmp2
+    ret i32 %tmp3
+}
+
+; CHECK-LABEL: test10:
+; CHECK: pkhtb r0, r0, r1, asr #17
+define i32 @test10(i32 %src1, i32 %src2) {
+entry:
+    %tmp = and i32 %src1, -65536
+    %tmp2 = ashr i32 %src2, 17
+    %tmp3 = or i32 %tmp, %tmp2
+    ret i32 %tmp3
+}
diff --git a/test/CodeGen/ARM/peephole-bitcast.ll b/test/CodeGen/ARM/peephole-bitcast.ll
index e72d51f..3c6a187 100644
--- a/test/CodeGen/ARM/peephole-bitcast.ll
+++ b/test/CodeGen/ARM/peephole-bitcast.ll
@@ -10,7 +10,7 @@
 
 define void @t(float %x) nounwind ssp {
 entry:
-; CHECK:     t:
+; CHECK-LABEL:     t:
 ; CHECK-NOT: vmov
 ; CHECK:     bl
   %0 = bitcast float %x to i32
diff --git a/test/CodeGen/ARM/popcnt.ll b/test/CodeGen/ARM/popcnt.ll
index 0b9c946..bdf793d 100644
--- a/test/CodeGen/ARM/popcnt.ll
+++ b/test/CodeGen/ARM/popcnt.ll
@@ -2,7 +2,7 @@
 ; Implement ctpop with vcnt
 
 define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
-;CHECK: vcnt8:
+;CHECK-LABEL: vcnt8:
 ;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)
@@ -10,7 +10,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
 }
 
 define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
-;CHECK: vcntQ8:
+;CHECK-LABEL: vcntQ8:
 ;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)
@@ -18,7 +18,7 @@ define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vcnt16(<4 x i16>* %A) nounwind {
-; CHECK: vcnt16:
+; CHECK-LABEL: vcnt16:
 ; CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
 ; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
 ; CHECK: vadd.i8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@@ -30,7 +30,7 @@ define <4 x i16> @vcnt16(<4 x i16>* %A) nounwind {
 }
 
 define <8 x i16> @vcntQ16(<8 x i16>* %A) nounwind {
-; CHECK: vcntQ16:
+; CHECK-LABEL: vcntQ16:
 ; CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
 ; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
 ; CHECK: vadd.i8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
@@ -42,7 +42,7 @@ define <8 x i16> @vcntQ16(<8 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vcnt32(<2 x i32>* %A) nounwind {
-; CHECK: vcnt32:
+; CHECK-LABEL: vcnt32:
 ; CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
 ; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
 ; CHECK: vadd.i8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@@ -57,7 +57,7 @@ define <2 x i32> @vcnt32(<2 x i32>* %A) nounwind {
 }
 
 define <4 x i32> @vcntQ32(<4 x i32>* %A) nounwind {
-; CHECK: vcntQ32:
+; CHECK-LABEL: vcntQ32:
 ; CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
 ; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
 ; CHECK: vadd.i8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
@@ -79,7 +79,7 @@ declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone
 declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
 
 define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
-;CHECK: vclz8:
+;CHECK-LABEL: vclz8:
 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
@@ -87,7 +87,7 @@ define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
-;CHECK: vclz16:
+;CHECK-LABEL: vclz16:
 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
@@ -95,7 +95,7 @@ define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
-;CHECK: vclz32:
+;CHECK-LABEL: vclz32:
 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
@@ -103,7 +103,7 @@ define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
 }
 
 define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
-;CHECK: vclzQ8:
+;CHECK-LABEL: vclzQ8:
 ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
@@ -111,7 +111,7 @@ define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
-;CHECK: vclzQ16:
+;CHECK-LABEL: vclzQ16:
 ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
@@ -119,7 +119,7 @@ define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
-;CHECK: vclzQ32:
+;CHECK-LABEL: vclzQ32:
 ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
@@ -135,7 +135,7 @@ declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
 
 define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
-;CHECK: vclss8:
+;CHECK-LABEL: vclss8:
 ;CHECK: vcls.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
@@ -143,7 +143,7 @@ define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
-;CHECK: vclss16:
+;CHECK-LABEL: vclss16:
 ;CHECK: vcls.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
@@ -151,7 +151,7 @@ define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
-;CHECK: vclss32:
+;CHECK-LABEL: vclss32:
 ;CHECK: vcls.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
@@ -159,7 +159,7 @@ define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
 }
 
 define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vclsQs8:
+;CHECK-LABEL: vclsQs8:
 ;CHECK: vcls.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
@@ -167,7 +167,7 @@ define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vclsQs16:
+;CHECK-LABEL: vclsQs16:
 ;CHECK: vcls.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
@@ -175,7 +175,7 @@ define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vclsQs32:
+;CHECK-LABEL: vclsQs32:
 ;CHECK: vcls.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
diff --git a/test/CodeGen/ARM/prefetch.ll b/test/CodeGen/ARM/prefetch.ll
index 9c8ff2b..5badb31 100644
--- a/test/CodeGen/ARM/prefetch.ll
+++ b/test/CodeGen/ARM/prefetch.ll
@@ -6,15 +6,15 @@
 
 define void @t1(i8* %ptr) nounwind  {
 entry:
-; ARM: t1:
+; ARM-LABEL: t1:
 ; ARM-NOT: pldw [r0]
 ; ARM: pld [r0]
 
-; ARM-MP: t1:
+; ARM-MP-LABEL: t1:
 ; ARM-MP: pldw [r0]
 ; ARM-MP: pld [r0]
 
-; THUMB2: t1:
+; THUMB2-LABEL: t1:
 ; THUMB2-NOT: pldw [r0]
 ; THUMB2: pld [r0]
   tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 )
@@ -24,10 +24,10 @@ entry:
 
 define void @t2(i8* %ptr) nounwind  {
 entry:
-; ARM: t2:
+; ARM-LABEL: t2:
 ; ARM: pld [r0, #1023]
 
-; THUMB2: t2:
+; THUMB2-LABEL: t2:
 ; THUMB2: pld [r0, #1023]
   %tmp = getelementptr i8* %ptr, i32 1023
   tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3, i32 1 )
@@ -36,10 +36,10 @@ entry:
 
 define void @t3(i32 %base, i32 %offset) nounwind  {
 entry:
-; ARM: t3:
+; ARM-LABEL: t3:
 ; ARM: pld [r0, r1, lsr #2]
 
-; THUMB2: t3:
+; THUMB2-LABEL: t3:
 ; THUMB2: lsrs r1, r1, #2
 ; THUMB2: pld [r0, r1]
   %tmp1 = lshr i32 %offset, 2
@@ -51,10 +51,10 @@ entry:
 
 define void @t4(i32 %base, i32 %offset) nounwind  {
 entry:
-; ARM: t4:
+; ARM-LABEL: t4:
 ; ARM: pld [r0, r1, lsl #2]
 
-; THUMB2: t4:
+; THUMB2-LABEL: t4:
 ; THUMB2: pld [r0, r1, lsl #2]
   %tmp1 = shl i32 %offset, 2
   %tmp2 = add i32 %base, %tmp1
@@ -67,10 +67,10 @@ declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
 
 define void @t5(i8* %ptr) nounwind  {
 entry:
-; ARM: t5:
+; ARM-LABEL: t5:
 ; ARM: pli [r0]
 
-; THUMB2: t5:
+; THUMB2-LABEL: t5:
 ; THUMB2: pli [r0]
   tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 0 )
   ret void
diff --git a/test/CodeGen/ARM/private.ll b/test/CodeGen/ARM/private.ll
index 94578d8..e48c292 100644
--- a/test/CodeGen/ARM/private.ll
+++ b/test/CodeGen/ARM/private.ll
@@ -2,7 +2,7 @@
 ;
 ; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
 ; CHECK: .Lfoo:
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: bl .Lfoo
 ; CHECK: .long .Lbaz
 ; CHECK: .Lbaz:
diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll
index fd2083c..3fe2bb8 100644
--- a/test/CodeGen/ARM/reg_sequence.ll
+++ b/test/CodeGen/ARM/reg_sequence.ll
@@ -11,7 +11,7 @@
 
 define void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind {
 entry:
-; CHECK:        t1:
+; CHECK-LABEL:        t1:
 ; CHECK:        vld1.16
 ; CHECK-NOT:    vmov d
 ; CHECK:        vmovl.s16
@@ -44,7 +44,7 @@ entry:
 
 define void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind {
 entry:
-; CHECK:        t2:
+; CHECK-LABEL:        t2:
 ; CHECK:        vld1.16
 ; CHECK-NOT:    vmov
 ; CHECK:        vmul.i16
@@ -73,7 +73,7 @@ entry:
 }
 
 define <8 x i8> @t3(i8* %A, i8* %B) nounwind {
-; CHECK:        t3:
+; CHECK-LABEL:        t3:
 ; CHECK:        vld3.8
 ; CHECK:        vmul.i8
 ; CHECK:        vmov r
@@ -92,7 +92,7 @@ define <8 x i8> @t3(i8* %A, i8* %B) nounwind {
 
 define void @t4(i32* %in, i32* %out) nounwind {
 entry:
-; CHECK:        t4:
+; CHECK-LABEL:        t4:
 ; CHECK:        vld2.32
 ; CHECK-NOT:    vmov
 ; CHECK:        vld2.32
@@ -135,7 +135,7 @@ return2:
 }
 
 define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind {
-; CHECK:        t5:
+; CHECK-LABEL:        t5:
 ; CHECK:        vld1.32
 ; How can FileCheck match Q and D registers? We need a lisp interpreter.
 ; CHECK:        vorr {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
@@ -153,7 +153,7 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind {
-; CHECK:        t6:
+; CHECK-LABEL:        t6:
 ; CHECK:        vldr
 ; CHECK:        vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]]
 ; CHECK-NEXT:   vld2.8 {d[[D1]][1], d[[D0]][1]}
@@ -167,7 +167,7 @@ define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind {
 
 define void @t7(i32* %iptr, i32* %optr) nounwind {
 entry:
-; CHECK:        t7:
+; CHECK-LABEL:        t7:
 ; CHECK:        vld2.32
 ; CHECK:        vst2.32
 ; CHECK:        vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}},
@@ -189,7 +189,7 @@ entry:
 
 ; PR7156
 define arm_aapcs_vfpcc i32 @t8() nounwind {
-; CHECK: t8:
+; CHECK-LABEL: t8:
 ; CHECK: vrsqrte.f32 q8, q8
 bb.nph55.bb.nph55.split_crit_edge:
   br label %bb3
@@ -238,7 +238,7 @@ bb14:                                             ; preds = %bb6
 
 ; PR7157
 define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind {
-; CHECK:        t9:
+; CHECK-LABEL:        t9:
 ; CHECK:        vldr
 ; CHECK-NOT:    vmov d{{.*}}, d16
 ; CHECK:        vmov.i32 d17
@@ -270,7 +270,7 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind {
 ; PR7162
 define arm_aapcs_vfpcc i32 @t10() nounwind {
 entry:
-; CHECK: t10:
+; CHECK-LABEL: t10:
 ; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3f000000
 ; CHECK: vmul.f32 q8, q8, d[[DREG:[0-1]+]]
 ; CHECK: vadd.f32 q8, q8, q8
diff --git a/test/CodeGen/ARM/ret_sret_vector.ll b/test/CodeGen/ARM/ret_sret_vector.ll
index 9bb3519..f9c4626 100644
--- a/test/CodeGen/ARM/ret_sret_vector.ll
+++ b/test/CodeGen/ARM/ret_sret_vector.ll
@@ -6,7 +6,7 @@ target triple = "thumbv7-apple-ios3.0.0"
 define <4 x double> @PR14337(<4 x double> %a, <4 x double> %b) {
   %foo = fadd <4 x double>  %a, %b
   ret <4 x double> %foo
-; CHECK: PR14337:
+; CHECK-LABEL: PR14337:
 ; CHECK: vst1.64
 ; CHECK: vst1.64
 }
diff --git a/test/CodeGen/ARM/returned-ext.ll b/test/CodeGen/ARM/returned-ext.ll
index 670b12f..d2cdeb0 100644
--- a/test/CodeGen/ARM/returned-ext.ll
+++ b/test/CodeGen/ARM/returned-ext.ll
@@ -10,13 +10,13 @@ declare zeroext i16 @bothzext16(i16 zeroext returned %x)
 ; The zeroext param attribute below is meant to have no effect
 define i16 @test_identity(i16 zeroext %x) {
 entry:
-; CHECKELF: test_identity:
+; CHECKELF-LABEL: test_identity:
 ; CHECKELF: mov [[SAVEX:r[0-9]+]], r0
 ; CHECKELF: bl identity16
 ; CHECKELF: uxth r0, r0
 ; CHECKELF: bl identity32
 ; CHECKELF: mov r0, [[SAVEX]]
-; CHECKT2D: test_identity:
+; CHECKT2D-LABEL: test_identity:
 ; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0
 ; CHECKT2D: blx _identity16
 ; CHECKT2D: uxth r0, r0
@@ -32,7 +32,7 @@ entry:
 ; x is not considered equal to %call (see SelectionDAGBuilder.cpp)
 define i16 @test_matched_ret(i16 %x) {
 entry:
-; CHECKELF: test_matched_ret:
+; CHECKELF-LABEL: test_matched_ret:
 
 ; This shouldn't be required
 ; CHECKELF: mov [[SAVEX:r[0-9]+]], r0
@@ -44,7 +44,7 @@ entry:
 ; This shouldn't be required
 ; CHECKELF: mov r0, [[SAVEX]]
 
-; CHECKT2D: test_matched_ret:
+; CHECKT2D-LABEL: test_matched_ret:
 
 ; This shouldn't be required
 ; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0
@@ -64,13 +64,13 @@ entry:
 
 define i16 @test_mismatched_ret(i16 %x) {
 entry:
-; CHECKELF: test_mismatched_ret:
+; CHECKELF-LABEL: test_mismatched_ret:
 ; CHECKELF: mov [[SAVEX:r[0-9]+]], r0
 ; CHECKELF: bl retzext16
 ; CHECKELF: sxth r0, {{r[0-9]+}}
 ; CHECKELF: bl identity32
 ; CHECKELF: mov r0, [[SAVEX]]
-; CHECKT2D: test_mismatched_ret:
+; CHECKT2D-LABEL: test_mismatched_ret:
 ; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0
 ; CHECKT2D: blx _retzext16
 ; CHECKT2D: sxth r0, {{r[0-9]+}}
@@ -84,13 +84,13 @@ entry:
 
 define i16 @test_matched_paramext(i16 %x) {
 entry:
-; CHECKELF: test_matched_paramext:
+; CHECKELF-LABEL: test_matched_paramext:
 ; CHECKELF: uxth r0, r0
 ; CHECKELF: bl paramzext16
 ; CHECKELF: uxth r0, r0
 ; CHECKELF: bl identity32
 ; CHECKELF: b paramzext16
-; CHECKT2D: test_matched_paramext:
+; CHECKT2D-LABEL: test_matched_paramext:
 ; CHECKT2D: uxth r0, r0
 ; CHECKT2D: blx _paramzext16
 ; CHECKT2D: uxth r0, r0
@@ -113,11 +113,11 @@ entry:
 ; optimization, don't bother checking: just verify that the calls are made
 ; in the correct order as a basic sanity check
 
-; CHECKELF: test_matched_paramext2:
+; CHECKELF-LABEL: test_matched_paramext2:
 ; CHECKELF: bl paramzext16
 ; CHECKELF: bl identity32
 ; CHECKELF: b paramzext16
-; CHECKT2D: test_matched_paramext2:
+; CHECKT2D-LABEL: test_matched_paramext2:
 ; CHECKT2D: blx _paramzext16
 ; CHECKT2D: blx _identity32
 ; CHECKT2D: b.w _paramzext16
@@ -133,7 +133,7 @@ entry:
 
 define i16 @test_matched_bothext(i16 %x) {
 entry:
-; CHECKELF: test_matched_bothext:
+; CHECKELF-LABEL: test_matched_bothext:
 ; CHECKELF: uxth r0, r0
 ; CHECKELF: bl bothzext16
 ; CHECKELF-NOT: uxth r0, r0
@@ -141,7 +141,7 @@ entry:
 ; FIXME: Tail call should be OK here
 ; CHECKELF: bl identity32
 
-; CHECKT2D: test_matched_bothext:
+; CHECKT2D-LABEL: test_matched_bothext:
 ; CHECKT2D: uxth r0, r0
 ; CHECKT2D: blx _bothzext16
 ; CHECKT2D-NOT: uxth r0, r0
@@ -157,14 +157,14 @@ entry:
 
 define i16 @test_mismatched_bothext(i16 %x) {
 entry:
-; CHECKELF: test_mismatched_bothext:
+; CHECKELF-LABEL: test_mismatched_bothext:
 ; CHECKELF: mov [[SAVEX:r[0-9]+]], r0
 ; CHECKELF: uxth r0, {{r[0-9]+}}
 ; CHECKELF: bl bothzext16
 ; CHECKELF: sxth r0, [[SAVEX]]
 ; CHECKELF: bl identity32
 ; CHECKELF: mov r0, [[SAVEX]]
-; CHECKT2D: test_mismatched_bothext:
+; CHECKT2D-LABEL: test_mismatched_bothext:
 ; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0
 ; CHECKT2D: uxth r0, {{r[0-9]+}}
 ; CHECKT2D: blx _bothzext16
diff --git a/test/CodeGen/ARM/returned-trunc-tail-calls.ll b/test/CodeGen/ARM/returned-trunc-tail-calls.ll
new file mode 100644
index 0000000..5946727
--- /dev/null
+++ b/test/CodeGen/ARM/returned-trunc-tail-calls.ll
@@ -0,0 +1,111 @@
+; RUN: llc < %s -mtriple=armv7 -arm-tail-calls | FileCheck %s
+
+declare i16 @ret16(i16 returned)
+declare i32 @ret32(i32 returned)
+
+define i32 @test1(i32 %val) {
+; CHECK-LABEL: test1:
+; CHECK: bl {{_?}}ret16
+  %in = trunc i32 %val to i16
+  tail call i16 @ret16(i16 returned %in)
+  ret i32 %val
+}
+
+define i16 @test2(i32 %val) {
+; CHECK-LABEL: test2:
+; CHECK: b {{_?}}ret16
+  %in = trunc i32 %val to i16
+  tail call i16 @ret16(i16 returned %in)
+  ret i16 %in
+}
+
+declare {i32, i8} @take_i32_i8({i32, i8} returned)
+define { i8, i8 } @test_nocommon_value({i32, i32} %in) {
+; CHECK-LABEL: test_nocommon_value:
+; CHECK: b {{_?}}take_i32_i8
+
+  %first = extractvalue {i32, i32} %in, 0
+  %first.trunc = trunc i32 %first to i8
+
+  %second = extractvalue {i32, i32} %in, 1
+  %second.trunc = trunc i32 %second to i8
+
+  %tmp = insertvalue {i32, i8} undef, i32 %first, 0
+  %callval = insertvalue {i32, i8} %tmp, i8 %second.trunc, 1
+  tail call {i32, i8} @take_i32_i8({i32, i8} returned %callval)
+
+  %restmp = insertvalue {i8, i8} undef, i8 %first.trunc, 0
+  %res = insertvalue {i8, i8} %restmp, i8 %second.trunc, 1
+  ret {i8, i8} %res
+}
+
+declare {i32, {i32, i32}} @give_i32_i32_i32()
+define {{i32, i32}, i32} @test_structs_different_shape() {
+; CHECK-LABEL: test_structs_different_shape:
+; CHECK: b {{_?}}give_i32_i32_i32
+  %val = tail call {i32, {i32, i32}} @give_i32_i32_i32()
+
+  %first = extractvalue {i32, {i32, i32}} %val, 0
+  %second = extractvalue {i32, {i32, i32}} %val, 1, 0
+  %third = extractvalue {i32, {i32, i32}} %val, 1, 1
+
+  %restmp = insertvalue {{i32, i32}, i32} undef, i32 %first, 0, 0
+  %reseventmper = insertvalue {{i32, i32}, i32} %restmp, i32 %second, 0, 1
+  %res = insertvalue {{i32, i32}, i32} %reseventmper, i32 %third, 1
+
+  ret {{i32, i32}, i32} %res
+}
+
+define i32 @test_undef_asymmetry() {
+; CHECK: test_undef_asymmetry:
+; CHECK: bl {{_?}}ret32
+; CHECK-NOT: jmp
+  tail call i32 @ret32(i32 returned undef)
+  ret i32 2
+}
+
+define {{}, {{}, i32, {}}, [1 x i32]} @evil_empty_aggregates() {
+; CHECK-LABEL: evil_empty_aggregates:
+; CHECK: b {{_?}}give_i32_i32_i32
+  %agg = tail call {i32, {i32, i32}} @give_i32_i32_i32()
+
+  %first = extractvalue {i32, {i32, i32}} %agg, 0
+  %second = extractvalue {i32, {i32, i32}} %agg, 1, 0
+
+  %restmp = insertvalue {{}, {{}, i32, {}}, [1 x i32]} undef, i32 %first, 1, 1
+  %res = insertvalue {{}, {{}, i32, {}}, [1 x i32]} %restmp, i32 %second, 2, 0
+  ret {{}, {{}, i32, {}}, [1 x i32]} %res
+}
+
+define i32 @structure_is_unimportant() {
+; CHECK-LABEL: structure_is_unimportant:
+; CHECK: b {{_?}}give_i32_i32_i32
+  %val = tail call {i32, {i32, i32}} @give_i32_i32_i32()
+
+  %res = extractvalue {i32, {i32, i32}} %val, 0
+  ret i32 %res
+}
+
+declare i64 @give_i64()
+define i64 @direct_i64_ok() {
+; CHECK-LABEL: direct_i64_ok:
+; CHECK: b {{_?}}give_i64
+  %val = tail call i64 @give_i64()
+  ret i64 %val
+}
+
+declare {i64, i32} @give_i64_i32()
+define {i32, i32} @trunc_i64_not_ok() {
+; CHECK-LABEL: trunc_i64_not_ok:
+; CHECK: bl {{_?}}give_i64_i32
+  %agg = tail call {i64, i32} @give_i64_i32()
+
+  %first = extractvalue {i64, i32} %agg, 0
+  %second = extractvalue {i64, i32} %agg, 1
+  %first.trunc = trunc i64 %first to i32
+
+  %tmp = insertvalue {i32, i32} undef, i32 %first.trunc, 0
+  %ret = insertvalue {i32, i32} %tmp, i32 %second, 1
+
+  ret {i32, i32} %ret
+}
diff --git a/test/CodeGen/ARM/rev.ll b/test/CodeGen/ARM/rev.ll
index 6bb6743..6c380ae 100644
--- a/test/CodeGen/ARM/rev.ll
+++ b/test/CodeGen/ARM/rev.ll
@@ -32,7 +32,7 @@ define i32 @test2(i32 %X) nounwind {
 ; rdar://9147637
 define i32 @test3(i16 zeroext %a) nounwind {
 entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: revsh r0, r0
   %0 = tail call i16 @llvm.bswap.i16(i16 %a)
   %1 = sext i16 %0 to i32
@@ -43,7 +43,7 @@ declare i16 @llvm.bswap.i16(i16) nounwind readnone
 
 define i32 @test4(i16 zeroext %a) nounwind {
 entry:
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: revsh r0, r0
   %conv = zext i16 %a to i32
   %shr9 = lshr i16 %a, 8
diff --git a/test/CodeGen/ARM/sbfx.ll b/test/CodeGen/ARM/sbfx.ll
index d29693e..36fbd19 100644
--- a/test/CodeGen/ARM/sbfx.ll
+++ b/test/CodeGen/ARM/sbfx.ll
@@ -2,7 +2,7 @@
 
 define i32 @f1(i32 %a) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sbfx r0, r0, #0, #20
     %tmp = shl i32 %a, 12
     %tmp2 = ashr i32 %tmp, 12
@@ -11,7 +11,7 @@ entry:
 
 define i32 @f2(i32 %a) {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: bfc	r0, #20, #12
     %tmp = shl i32 %a, 12
     %tmp2 = lshr i32 %tmp, 12
@@ -20,7 +20,7 @@ entry:
 
 define i32 @f3(i32 %a) {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sbfx r0, r0, #5, #3
     %tmp = shl i32 %a, 24
     %tmp2 = ashr i32 %tmp, 29
@@ -29,7 +29,7 @@ entry:
 
 define i32 @f4(i32 %a) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ubfx r0, r0, #5, #3
     %tmp = shl i32 %a, 24
     %tmp2 = lshr i32 %tmp, 29
@@ -38,7 +38,7 @@ entry:
 
 define i32 @f5(i32 %a) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: sbfx
 ; CHECK: bx
     %tmp = shl i32 %a, 3
diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll
index c9ac66a..5e7506a 100644
--- a/test/CodeGen/ARM/select-imm.ll
+++ b/test/CodeGen/ARM/select-imm.ll
@@ -4,18 +4,18 @@
 
 define i32 @t1(i32 %c) nounwind readnone {
 entry:
-; ARM: t1:
+; ARM-LABEL: t1:
 ; ARM: mov [[R1:r[0-9]+]], #101
 ; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256
-; ARM: movgt r0, #123
+; ARM: movgt {{r[0-1]}}, #123
 
-; ARMT2: t1:
-; ARMT2: movw r0, #357
-; ARMT2: movgt r0, #123
+; ARMT2-LABEL: t1:
+; ARMT2: movw [[R:r[0-1]]], #357
+; ARMT2: movgt [[R]], #123
 
-; THUMB2: t1:
-; THUMB2: movw r0, #357
-; THUMB2: movgt r0, #123
+; THUMB2-LABEL: t1:
+; THUMB2: movw [[R:r[0-1]]], #357
+; THUMB2: movgt [[R]], #123
 
   %0 = icmp sgt i32 %c, 1
   %1 = select i1 %0, i32 123, i32 357
@@ -24,18 +24,18 @@ entry:
 
 define i32 @t2(i32 %c) nounwind readnone {
 entry:
-; ARM: t2:
-; ARM: mov r0, #123
-; ARM: movgt r0, #101
-; ARM: orrgt r0, r0, #256
+; ARM-LABEL: t2:
+; ARM: mov [[R:r[0-1]]], #123
+; ARM: movgt [[R]], #101
+; ARM: orrgt [[R]], [[R]], #256
 
-; ARMT2: t2:
-; ARMT2: mov r0, #123
-; ARMT2: movwgt r0, #357
+; ARMT2-LABEL: t2:
+; ARMT2: mov [[R:r[0-1]]], #123
+; ARMT2: movwgt [[R]], #357
 
-; THUMB2: t2:
-; THUMB2: mov{{(s|\.w)}} r0, #123
-; THUMB2: movwgt r0, #357
+; THUMB2-LABEL: t2:
+; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #123
+; THUMB2: movwgt [[R]], #357
 
   %0 = icmp sgt i32 %c, 1
   %1 = select i1 %0, i32 357, i32 123
@@ -44,17 +44,17 @@ entry:
 
 define i32 @t3(i32 %a) nounwind readnone {
 entry:
-; ARM: t3:
-; ARM: mov r0, #0
-; ARM: moveq r0, #1
+; ARM-LABEL: t3:
+; ARM: mov [[R:r[0-1]]], #0
+; ARM: moveq [[R]], #1
 
-; ARMT2: t3:
-; ARMT2: mov r0, #0
-; ARMT2: moveq r0, #1
+; ARMT2-LABEL: t3:
+; ARMT2: mov [[R:r[0-1]]], #0
+; ARMT2: moveq [[R]], #1
 
-; THUMB2: t3:
-; THUMB2: mov{{(s|\.w)}} r0, #0
-; THUMB2: moveq r0, #1
+; THUMB2-LABEL: t3:
+; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #0
+; THUMB2: moveq [[R]], #1
   %0 = icmp eq i32 %a, 160
   %1 = zext i1 %0 to i32
   ret i32 %1
@@ -62,15 +62,15 @@ entry:
 
 define i32 @t4(i32 %a, i32 %b, i32 %x) nounwind {
 entry:
-; ARM: t4:
+; ARM-LABEL: t4:
 ; ARM: ldr
 ; ARM: mov{{lt|ge}}
 
-; ARMT2: t4:
+; ARMT2-LABEL: t4:
 ; ARMT2: movwlt [[R0:r[0-9]+]], #65365
 ; ARMT2: movtlt [[R0]], #65365
 
-; THUMB2: t4:
+; THUMB2-LABEL: t4:
 ; THUMB2: mvnlt [[R0:r[0-9]+]], #11141290
   %0 = icmp slt i32 %a, %b
   %1 = select i1 %0, i32 4283826005, i32 %x
@@ -80,13 +80,13 @@ entry:
 ; rdar://9758317
 define i32 @t5(i32 %a) nounwind {
 entry:
-; ARM: t5:
+; ARM-LABEL: t5:
 ; ARM-NOT: mov
 ; ARM: cmp r0, #1
 ; ARM-NOT: mov
 ; ARM: movne r0, #0
 
-; THUMB2: t5:
+; THUMB2-LABEL: t5:
 ; THUMB2-NOT: mov
 ; THUMB2: cmp r0, #1
 ; THUMB2: it ne
@@ -98,12 +98,12 @@ entry:
 
 define i32 @t6(i32 %a) nounwind {
 entry:
-; ARM: t6:
+; ARM-LABEL: t6:
 ; ARM-NOT: mov
 ; ARM: cmp r0, #0
 ; ARM: movne r0, #1
 
-; THUMB2: t6:
+; THUMB2-LABEL: t6:
 ; THUMB2-NOT: mov
 ; THUMB2: cmp r0, #0
 ; THUMB2: it ne
diff --git a/test/CodeGen/ARM/select.ll b/test/CodeGen/ARM/select.ll
index 62708ed..d5c3a27 100644
--- a/test/CodeGen/ARM/select.ll
+++ b/test/CodeGen/ARM/select.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mattr=+neon,+thumb2 -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=CHECK-NEON
 
 define i32 @f1(i32 %a.s) {
-;CHECK: f1:
+;CHECK-LABEL: f1:
 ;CHECK: moveq
 entry:
     %tmp = icmp eq i32 %a.s, 4
@@ -12,7 +12,7 @@ entry:
 }
 
 define i32 @f2(i32 %a.s) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
 ;CHECK: movgt
 entry:
     %tmp = icmp sgt i32 %a.s, 4
@@ -21,7 +21,7 @@ entry:
 }
 
 define i32 @f3(i32 %a.s, i32 %b.s) {
-;CHECK: f3:
+;CHECK-LABEL: f3:
 ;CHECK: movlt
 entry:
     %tmp = icmp slt i32 %a.s, %b.s
@@ -30,7 +30,7 @@ entry:
 }
 
 define i32 @f4(i32 %a.s, i32 %b.s) {
-;CHECK: f4:
+;CHECK-LABEL: f4:
 ;CHECK: movle
 entry:
     %tmp = icmp sle i32 %a.s, %b.s
@@ -39,7 +39,7 @@ entry:
 }
 
 define i32 @f5(i32 %a.u, i32 %b.u) {
-;CHECK: f5:
+;CHECK-LABEL: f5:
 ;CHECK: movls
 entry:
     %tmp = icmp ule i32 %a.u, %b.u
@@ -48,7 +48,7 @@ entry:
 }
 
 define i32 @f6(i32 %a.u, i32 %b.u) {
-;CHECK: f6:
+;CHECK-LABEL: f6:
 ;CHECK: movhi
 entry:
     %tmp = icmp ugt i32 %a.u, %b.u
@@ -57,10 +57,10 @@ entry:
 }
 
 define double @f7(double %a, double %b) {
-;CHECK: f7:
+;CHECK-LABEL: f7:
 ;CHECK: movlt
 ;CHECK: movlt
-;CHECK-VFP: f7:
+;CHECK-VFP-LABEL: f7:
 ;CHECK-VFP: vmovmi
     %tmp = fcmp olt double %a, 1.234e+00
     %tmp1 = select i1 %tmp, double -1.000e+00, double %b
@@ -94,7 +94,7 @@ define arm_apcscc float @f8(i32 %a) nounwind {
 ; Glue values can only have a single use, but the following test exposed a
 ; case where a SELECT was lowered with 2 uses of a comparison, causing the
 ; scheduler to assert.
-; CHECK-VFP: f9:
+; CHECK-VFP-LABEL: f9:
 
 declare i8* @objc_msgSend(i8*, i8*, ...)
 define void @f9() optsize {
diff --git a/test/CodeGen/ARM/select_xform.ll b/test/CodeGen/ARM/select_xform.ll
index 7507808..e13504a 100644
--- a/test/CodeGen/ARM/select_xform.ll
+++ b/test/CodeGen/ARM/select_xform.ll
@@ -3,11 +3,11 @@
 ; rdar://8662825
 
 define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
-; ARM: t1:
+; ARM-LABEL: t1:
 ; ARM: suble r1, r1, #-2147483647
 ; ARM: mov r0, r1
 
-; T2: t1:
+; T2-LABEL: t1:
 ; T2: mvn r0, #-2147483648
 ; T2: addle r1, r0
 ; T2: mov r0, r1
@@ -18,11 +18,11 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
 }
 
 define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; ARM: t2:
+; ARM-LABEL: t2:
 ; ARM: suble r1, r1, #10
 ; ARM: mov r0, r1
 
-; T2: t2:
+; T2-LABEL: t2:
 ; T2: suble r1, #10
 ; T2: mov r0, r1
   %tmp1 = icmp sgt i32 %c, 10
@@ -32,11 +32,11 @@ define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
 }
 
 define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
-; ARM: t3:
+; ARM-LABEL: t3:
 ; ARM: andge r3, r3, r2
 ; ARM: mov r0, r3
 
-; T2: t3:
+; T2-LABEL: t3:
 ; T2: andge r3, r2
 ; T2: mov r0, r3
   %cond = icmp slt i32 %a, %b
@@ -46,11 +46,11 @@ define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
 }
 
 define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
-; ARM: t4:
+; ARM-LABEL: t4:
 ; ARM: orrge r3, r3, r2
 ; ARM: mov r0, r3
 
-; T2: t4:
+; T2-LABEL: t4:
 ; T2: orrge r3, r2
 ; T2: mov r0, r3
   %cond = icmp slt i32 %a, %b
@@ -61,11 +61,11 @@ define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
 
 define i32 @t5(i32 %a, i32 %b, i32 %c) nounwind {
 entry:
-; ARM: t5:
+; ARM-LABEL: t5:
 ; ARM-NOT: moveq
 ; ARM: orreq r2, r2, #1
 
-; T2: t5:
+; T2-LABEL: t5:
 ; T2-NOT: moveq
 ; T2: orreq r2, r2, #1
   %tmp1 = icmp eq i32 %a, %b
@@ -75,11 +75,11 @@ entry:
 }
 
 define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; ARM: t6:
+; ARM-LABEL: t6:
 ; ARM-NOT: movge
 ; ARM: eorlt r3, r3, r2
 
-; T2: t6:
+; T2-LABEL: t6:
 ; T2-NOT: movge
 ; T2: eorlt r3, r2
   %cond = icmp slt i32 %a, %b
@@ -90,11 +90,11 @@ define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
 
 define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind {
 entry:
-; ARM: t7:
+; ARM-LABEL: t7:
 ; ARM-NOT: lsleq
 ; ARM: andeq r2, r2, r2, lsl #1
 
-; T2: t7:
+; T2-LABEL: t7:
 ; T2-NOT: lsleq.w
 ; T2: andeq.w r2, r2, r2, lsl #1
   %tmp1 = shl i32 %c, 1
@@ -106,11 +106,11 @@ entry:
 
 ; Fold ORRri into movcc.
 define i32 @t8(i32 %a, i32 %b) nounwind {
-; ARM: t8:
+; ARM-LABEL: t8:
 ; ARM: cmp r0, r1
 ; ARM: orrge r0, r1, #1
 
-; T2: t8:
+; T2-LABEL: t8:
 ; T2: cmp r0, r1
 ; T2: orrge r0, r1, #1
   %x = or i32 %b, 1
@@ -121,11 +121,11 @@ define i32 @t8(i32 %a, i32 %b) nounwind {
 
 ; Fold ANDrr into movcc.
 define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind {
-; ARM: t9:
+; ARM-LABEL: t9:
 ; ARM: cmp r0, r1
 ; ARM: andge r0, r1, r2
 
-; T2: t9:
+; T2-LABEL: t9:
 ; T2: cmp r0, r1
 ; T2: andge.w r0, r1, r2
   %x = and i32 %b, %c
@@ -136,11 +136,11 @@ define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind {
 
 ; Fold EORrs into movcc.
 define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; ARM: t10:
+; ARM-LABEL: t10:
 ; ARM: cmp r0, r1
 ; ARM: eorge r0, r1, r2, lsl #7
 
-; T2: t10:
+; T2-LABEL: t10:
 ; T2: cmp r0, r1
 ; T2: eorge.w r0, r1, r2, lsl #7
   %s = shl i32 %c, 7
@@ -152,11 +152,11 @@ define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
 
 ; Fold ORRri into movcc, reversing the condition.
 define i32 @t11(i32 %a, i32 %b) nounwind {
-; ARM: t11:
+; ARM-LABEL: t11:
 ; ARM: cmp r0, r1
 ; ARM: orrlt r0, r1, #1
 
-; T2: t11:
+; T2-LABEL: t11:
 ; T2: cmp r0, r1
 ; T2: orrlt r0, r1, #1
   %x = or i32 %b, 1
@@ -167,11 +167,11 @@ define i32 @t11(i32 %a, i32 %b) nounwind {
 
 ; Fold ADDri12 into movcc
 define i32 @t12(i32 %a, i32 %b) nounwind {
-; ARM: t12:
+; ARM-LABEL: t12:
 ; ARM: cmp r0, r1
 ; ARM: addge r0, r1,
 
-; T2: t12:
+; T2-LABEL: t12:
 ; T2: cmp r0, r1
 ; T2: addwge r0, r1, #3000
   %x = add i32 %b, 3000
diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll
index eb971ff..f14adca 100644
--- a/test/CodeGen/ARM/shifter_operand.ll
+++ b/test/CodeGen/ARM/shifter_operand.ll
@@ -4,10 +4,10 @@
 
 
 define i32 @test1(i32 %X, i32 %Y, i8 %sh) {
-; A8: test1:
+; A8-LABEL: test1:
 ; A8: add r0, r0, r1, lsl r2
 
-; A9: test1:
+; A9-LABEL: test1:
 ; A9: add r0, r0, r1, lsl r2
         %shift.upgrd.1 = zext i8 %sh to i32
         %A = shl i32 %Y, %shift.upgrd.1
@@ -16,10 +16,10 @@ define i32 @test1(i32 %X, i32 %Y, i8 %sh) {
 }
 
 define i32 @test2(i32 %X, i32 %Y, i8 %sh) {
-; A8: test2:
+; A8-LABEL: test2:
 ; A8: bic r0, r0, r1, asr r2
 
-; A9: test2:
+; A9-LABEL: test2:
 ; A9: bic r0, r0, r1, asr r2
         %shift.upgrd.2 = zext i8 %sh to i32
         %A = ashr i32 %Y, %shift.upgrd.2
@@ -30,12 +30,12 @@ define i32 @test2(i32 %X, i32 %Y, i8 %sh) {
 
 define i32 @test3(i32 %base, i32 %base2, i32 %offset) {
 entry:
-; A8: test3:
+; A8-LABEL: test3:
 ; A8: ldr r0, [r0, r2, lsl #2]
 ; A8: ldr r1, [r1, r2, lsl #2]
 
 ; lsl #2 is free
-; A9: test3:
+; A9-LABEL: test3:
 ; A9: ldr r0, [r0, r2, lsl #2]
 ; A9: ldr r1, [r1, r2, lsl #2]
         %tmp1 = shl i32 %offset, 2
@@ -53,13 +53,13 @@ declare i8* @malloc(...)
 
 define fastcc void @test4(i16 %addr) nounwind {
 entry:
-; A8: test4:
+; A8-LABEL: test4:
 ; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
 ; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
 ; A8: str [[REG]], [r0, r1, lsl #2]
 ; A8-NOT: str [[REG]], [r0]
 
-; A9: test4:
+; A9-LABEL: test4:
 ; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
 ; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
 ; A9: str [[REG]], [r0, r1, lsl #2]
diff --git a/test/CodeGen/ARM/spill-q.ll b/test/CodeGen/ARM/spill-q.ll
index e93cdbc..b924663 100644
--- a/test/CodeGen/ARM/spill-q.ll
+++ b/test/CodeGen/ARM/spill-q.ll
@@ -10,7 +10,7 @@
 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
 
 define void @aaa(%quuz* %this, i8* %block) {
-; CHECK: aaa:
+; CHECK-LABEL: aaa:
 ; CHECK: bic {{.*}}, #15
 ; CHECK: vst1.64 {{.*}}sp:128
 ; CHECK: vld1.64 {{.*}}sp:128
diff --git a/test/CodeGen/ARM/str_post.ll b/test/CodeGen/ARM/str_post.ll
index 97916f1..32e3b85 100644
--- a/test/CodeGen/ARM/str_post.ll
+++ b/test/CodeGen/ARM/str_post.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 
 define i16 @test1(i32* %X, i16* %A) {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: strh {{.*}}[{{.*}}], #-4
         %Y = load i32* %X               ; <i32> [#uses=1]
         %tmp1 = trunc i32 %Y to i16             ; <i16> [#uses=1]
@@ -12,7 +12,7 @@ define i16 @test1(i32* %X, i16* %A) {
 }
 
 define i32 @test2(i32* %X, i32* %A) {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: str {{.*}}[{{.*}}],
         %Y = load i32* %X               ; <i32> [#uses=1]
         store i32 %Y, i32* %A
diff --git a/test/CodeGen/ARM/struct-byval-frame-index.ll b/test/CodeGen/ARM/struct-byval-frame-index.ll
new file mode 100644
index 0000000..ae68ce5
--- /dev/null
+++ b/test/CodeGen/ARM/struct-byval-frame-index.ll
@@ -0,0 +1,225 @@
+; RUN: llc < %s -mcpu=cortex-a15 -verify-machineinstrs | FileCheck %s
+
+; Check a spill right after a function call with large struct byval is correctly
+; generated.
+; PR16393
+
+; CHECK: set_stored_macroblock_parameters
+; CHECK: str r{{.*}}, [sp, [[SLOT:#[0-9]+]]] @ 4-byte Spill
+; CHECK: bl RestoreMVBlock8x8
+; CHECK: bl RestoreMVBlock8x8
+; CHECK: bl RestoreMVBlock8x8
+; CHECK: ldr r{{.*}}, [sp, [[SLOT]]] @ 4-byte Reload
+
+target triple = "armv7l-unknown-linux-gnueabihf"
+
+%structA = type { double, [16 x [16 x i16]], [16 x [16 x i16]], [16 x [16 x i16]], i32****, i32***, i32, i16, [4 x i32], [4 x i32], i8**, [16 x i8], [16 x i8], i32, i64, i32, i16******, i16******, [2 x [4 x [4 x i8]]], i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+%structB = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8**, i8**, i32, i32***, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [9 x [16 x [16 x i16]]], [5 x [16 x [16 x i16]]], [9 x [8 x [8 x i16]]], [2 x [4 x [16 x [16 x i16]]]], [16 x [16 x i16]], [16 x [16 x i32]], i32****, i32***, i32***, i32***, i32****, i32****, %structC*, %structD*, %structK*, i32*, i32*, i32, i32, i32, i32, [4 x [4 x i32]], i32, i32, i32, i32, i32, double, i32, i32, i32, i32, i16******, i16******, i16******, i16******, [15 x i16], i32, i32, i32, i32, i32, i32, i32, i32, [6 x [32 x i32]], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [1 x i32], i32, i32, [2 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %structL*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, double**, double***, i32***, double**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x [2 x i32]], [2 x i32], i32, i32, i16, i32, i32, i32, i32, i32 }
+%structC = type { i32, i32, [100 x %structD*], i32, float, float, float }
+%structD = type { i32, i32, i32, i32, i32, i32, %structE*, %structH*, %structJ*, i32, i32*, i32*, i32*, i32, i32*, i32*, i32*, i32 (i32)*, [3 x [2 x i32]] }
+%structE = type { %structF*, %structG, %structG }
+%structF = type { i32, i32, i8, i32, i32, i8, i8, i32, i32, i8*, i32 }
+%structG = type { i32, i32, i32, i32, i32, i8*, i32*, i32, i32 }
+%structH = type { [3 x [11 x %structI]], [2 x [9 x %structI]], [2 x [10 x %structI]], [2 x [6 x %structI]], [4 x %structI], [4 x %structI], [3 x %structI] }
+%structI = type { i16, i8, i32 }
+%structJ = type { [2 x %structI], [4 x %structI], [3 x [4 x %structI]], [10 x [4 x %structI]], [10 x [15 x %structI]], [10 x [15 x %structI]], [10 x [5 x %structI]], [10 x [5 x %structI]], [10 x [15 x %structI]], [10 x [15 x %structI]] }
+%structK = type { i32, i32, i32, [2 x i32], i32, [8 x i32], %structK*, %structK*, i32, [2 x [4 x [4 x [2 x i32]]]], [16 x i8], [16 x i8], i32, i64, [4 x i32], [4 x i32], i64, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16, double, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+%structL = type { i32, i32, i32, i32, i32, %structL* }
+%structM = type { i32, i32, i32, i32, i32, i32, [6 x [33 x i64]], [6 x [33 x i64]], [6 x [33 x i64]], [6 x [33 x i64]], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i16**, i16****, i16****, i16*****, i16***, i8*, i8***, i64***, i64***, i16****, i8**, i8**, %structM*, %structM*, %structM*, i32, i32, i32, i32, i32, i32, i32 }
+%structN = type { i32, [16 x [16 x i32]], [16 x [16 x i32]], [16 x [16 x i32]], [3 x [16 x [16 x i32]]], [4 x i16], [4 x i8], [4 x i8], [4 x i8], [16 x [16 x i16]], [16 x [16 x i16]], [16 x [16 x i32]] }
+
+@cofAC = external global i32****, align 4
+@cofDC = external global i32***, align 4
+@rdopt = external global %structA*, align 4
+@img = external global %structB*
+@enc_picture = external global %structM*
+@si_frame_indicator = external global i32, align 4
+@sp2_frame_indicator = external global i32, align 4
+@lrec = external global i32**, align 4
+@tr8x8 = external global %structN, align 4
+@best_mode = external global i16, align 2
+@best_c_imode = external global i32, align 4
+@best_i16offset = external global i32, align 4
+@bi_pred_me = external global i16, align 2
+@b8mode = external global [4 x i32], align 4
+@b8pdir = external global [4 x i32], align 4
+@b4_intra_pred_modes = external global [16 x i8], align 1
+@b8_intra_pred_modes8x8 = external global [16 x i8], align 1
+@b4_ipredmode = external global [16 x i8], align 1
+@b8_ipredmode8x8 = external global [4 x [4 x i8]], align 1
+@rec_mbY = external global [16 x [16 x i16]], align 2
+@lrec_rec = external global [16 x [16 x i32]], align 4
+@rec_mbU = external global [16 x [16 x i16]], align 2
+@rec_mbV = external global [16 x [16 x i16]], align 2
+@lrec_rec_U = external global [16 x [16 x i32]], align 4
+@lrec_uv = external global i32***, align 4
+@lrec_rec_V = external global [16 x [16 x i32]], align 4
+@cbp = external global i32, align 4
+@cbp_blk = external global i64, align 8
+@luma_transform_size_8x8_flag = external global i32, align 4
+@frefframe = external global [4 x [4 x i8]], align 1
+@brefframe = external global [4 x [4 x i8]], align 1
+
+; Function Attrs: nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) #0
+
+; Function Attrs: nounwind
+declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) #0
+
+; Function Attrs: nounwind
+declare void @SetMotionVectorsMB(%structK* nocapture, i32) #1
+
+; Function Attrs: nounwind
+define void @set_stored_macroblock_parameters() #1 {
+entry:
+  %0 = load %structB** @img, align 4, !tbaa !0
+  %1 = load i32* undef, align 4, !tbaa !3
+  %mb_data = getelementptr inbounds %structB* %0, i32 0, i32 61
+  %2 = load %structK** %mb_data, align 4, !tbaa !0
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  br i1 undef, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  br i1 undef, label %for.body20, label %if.end
+
+for.body20:                                       ; preds = %for.end
+  unreachable
+
+if.end:                                           ; preds = %for.end
+  br i1 undef, label %if.end40, label %for.cond31.preheader
+
+for.cond31.preheader:                             ; preds = %if.end
+  unreachable
+
+if.end40:                                         ; preds = %if.end
+  br i1 undef, label %if.end43, label %if.then42
+
+if.then42:                                        ; preds = %if.end40
+  br label %if.end43
+
+if.end43:                                         ; preds = %if.then42, %if.end40
+  br i1 undef, label %if.end164, label %for.cond47.preheader
+
+for.cond47.preheader:                             ; preds = %if.end43
+  br i1 undef, label %for.body119, label %if.end164
+
+for.body119:                                      ; preds = %for.body119, %for.cond47.preheader
+  br i1 undef, label %for.body119, label %if.end164
+
+if.end164:                                        ; preds = %for.body119, %for.cond47.preheader, %if.end43
+  store i32*** null, i32**** @cofDC, align 4, !tbaa !0
+  %mb_type = getelementptr inbounds %structK* %2, i32 %1, i32 8
+  br i1 undef, label %if.end230, label %if.then169
+
+if.then169:                                       ; preds = %if.end164
+  br i1 undef, label %for.cond185.preheader, label %for.cond210.preheader
+
+for.cond185.preheader:                            ; preds = %if.then169
+  unreachable
+
+for.cond210.preheader:                            ; preds = %if.then169
+  unreachable
+
+if.end230:                                        ; preds = %if.end164
+  tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* bitcast ([4 x i32]* @b8mode to i8*), i32 16, i32 4, i1 false)
+  %b8pdir = getelementptr inbounds %structK* %2, i32 %1, i32 15
+  %3 = bitcast [4 x i32]* %b8pdir to i8*
+  tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %3, i8* bitcast ([4 x i32]* @b8pdir to i8*), i32 16, i32 4, i1 false)
+  br i1 undef, label %if.end236, label %if.then233
+
+if.then233:                                       ; preds = %if.end230
+  unreachable
+
+if.end236:                                        ; preds = %if.end230
+  %cmp242 = icmp ne i16 undef, 8
+  %4 = load i32* @luma_transform_size_8x8_flag, align 4, !tbaa !3
+  %tobool245 = icmp ne i32 %4, 0
+  %or.cond812 = or i1 %cmp242, %tobool245
+  br i1 %or.cond812, label %if.end249, label %land.lhs.true246
+
+land.lhs.true246:                                 ; preds = %if.end236
+  br i1 undef, label %if.end249, label %if.then248
+
+if.then248:                                       ; preds = %land.lhs.true246
+  tail call void asm sideeffect "", "~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11}"() nounwind
+  tail call void @RestoreMVBlock8x8(i32 1, i32 0, %structN* byval @tr8x8, i32 0) #0
+  tail call void @RestoreMVBlock8x8(i32 1, i32 2, %structN* byval @tr8x8, i32 0) #0
+  tail call void @RestoreMVBlock8x8(i32 1, i32 3, %structN* byval @tr8x8, i32 0) #0
+  br label %if.end249
+
+if.end249:                                        ; preds = %if.then248, %land.lhs.true246, %if.end236
+  %5 = load i32* @luma_transform_size_8x8_flag, align 4, !tbaa !3
+  %6 = load %structA** @rdopt, align 4, !tbaa !0
+  %luma_transform_size_8x8_flag264 = getelementptr inbounds %structA* %6, i32 0, i32 21
+  store i32 %5, i32* %luma_transform_size_8x8_flag264, align 4, !tbaa !3
+  %7 = load i32* undef, align 4, !tbaa !3
+  %add281 = add nsw i32 %7, 0
+  br label %for.body285
+
+for.body285:                                      ; preds = %for.inc503, %if.end249
+  %8 = phi %structB* [ undef, %if.end249 ], [ %.pre1155, %for.inc503 ]
+  %i.21103 = phi i32 [ 0, %if.end249 ], [ %inc504, %for.inc503 ]
+  %block_x286 = getelementptr inbounds %structB* %8, i32 0, i32 37
+  %9 = load i32* %block_x286, align 4, !tbaa !3
+  %add287 = add nsw i32 %9, %i.21103
+  %shr289 = ashr i32 %i.21103, 1
+  %add290 = add nsw i32 %shr289, 0
+  %arrayidx292 = getelementptr inbounds %structK* %2, i32 %1, i32 15, i32 %add290
+  %10 = load %structM** @enc_picture, align 4, !tbaa !0
+  %ref_idx = getelementptr inbounds %structM* %10, i32 0, i32 35
+  %11 = load i8**** %ref_idx, align 4, !tbaa !0
+  %12 = load i8*** %11, align 4, !tbaa !0
+  %arrayidx313 = getelementptr inbounds i8** %12, i32 %add281
+  %13 = load i8** %arrayidx313, align 4, !tbaa !0
+  %arrayidx314 = getelementptr inbounds i8* %13, i32 %add287
+  store i8 -1, i8* %arrayidx314, align 1, !tbaa !1
+  %14 = load %structB** @img, align 4, !tbaa !0
+  %MbaffFrameFlag327 = getelementptr inbounds %structB* %14, i32 0, i32 100
+  %15 = load i32* %MbaffFrameFlag327, align 4, !tbaa !3
+  %tobool328 = icmp eq i32 %15, 0
+  br i1 %tobool328, label %if.end454, label %if.then329
+
+if.then329:                                       ; preds = %for.body285
+  %16 = load %structA** @rdopt, align 4, !tbaa !0
+  br label %if.end454
+
+if.end454:                                        ; preds = %if.then329, %for.body285
+  %17 = load i32* %arrayidx292, align 4, !tbaa !3
+  %cmp457 = icmp eq i32 %17, 0
+  br i1 %cmp457, label %if.then475, label %lor.lhs.false459
+
+lor.lhs.false459:                                 ; preds = %if.end454
+  %18 = load i32* %mb_type, align 4, !tbaa !3
+  switch i32 %18, label %for.inc503 [
+    i32 9, label %if.then475
+    i32 10, label %if.then475
+    i32 13, label %if.then475
+    i32 14, label %if.then475
+  ]
+
+if.then475:                                       ; preds = %lor.lhs.false459, %lor.lhs.false459, %lor.lhs.false459, %lor.lhs.false459, %if.end454
+  store i16 0, i16* undef, align 2, !tbaa !4
+  br label %for.inc503
+
+for.inc503:                                       ; preds = %if.then475, %lor.lhs.false459
+  %inc504 = add nsw i32 %i.21103, 1
+  %.pre1155 = load %structB** @img, align 4, !tbaa !0
+  br label %for.body285
+}
+
+; Function Attrs: nounwind
+declare void @update_offset_params(i32, i32) #1
+
+; Function Attrs: nounwind
+declare void @RestoreMVBlock8x8(i32, i32, %structN* byval nocapture, i32) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!0 = metadata !{metadata !"any pointer", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA"}
+!3 = metadata !{metadata !"int", metadata !1}
+!4 = metadata !{metadata !"short", metadata !1}
diff --git a/test/CodeGen/ARM/struct_byval.ll b/test/CodeGen/ARM/struct_byval.ll
index e9541c2..012b994 100644
--- a/test/CodeGen/ARM/struct_byval.ll
+++ b/test/CodeGen/ARM/struct_byval.ll
@@ -6,7 +6,7 @@
 
 define i32 @f() nounwind ssp {
 entry:
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: ldr
 ; CHECK: str
 ; CHECK-NOT:bne
@@ -18,7 +18,7 @@ entry:
 ; Generate a loop for large struct byval
 define i32 @g() nounwind ssp {
 entry:
-; CHECK: g:
+; CHECK-LABEL: g:
 ; CHECK: ldr
 ; CHECK: sub
 ; CHECK: str
@@ -31,7 +31,7 @@ entry:
 ; Generate a loop using NEON instructions
 define i32 @h() nounwind ssp {
 entry:
-; CHECK: h:
+; CHECK-LABEL: h:
 ; CHECK: vld1
 ; CHECK: sub
 ; CHECK: vst1
diff --git a/test/CodeGen/ARM/sub-cmp-peephole.ll b/test/CodeGen/ARM/sub-cmp-peephole.ll
index 2961b94..1b411e3 100644
--- a/test/CodeGen/ARM/sub-cmp-peephole.ll
+++ b/test/CodeGen/ARM/sub-cmp-peephole.ll
@@ -2,7 +2,7 @@
 
 define i32 @f(i32 %a, i32 %b) nounwind ssp {
 entry:
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: subs
 ; CHECK-NOT: cmp
   %cmp = icmp sgt i32 %a, %b
@@ -13,7 +13,7 @@ entry:
 
 define i32 @g(i32 %a, i32 %b) nounwind ssp {
 entry:
-; CHECK: g:
+; CHECK-LABEL: g:
 ; CHECK: subs
 ; CHECK-NOT: cmp
   %cmp = icmp slt i32 %a, %b
@@ -24,7 +24,7 @@ entry:
 
 define i32 @h(i32 %a, i32 %b) nounwind ssp {
 entry:
-; CHECK: h:
+; CHECK-LABEL: h:
 ; CHECK: subs
 ; CHECK-NOT: cmp
   %cmp = icmp sgt i32 %a, 3
@@ -36,7 +36,7 @@ entry:
 ; rdar://11725965
 define i32 @i(i32 %a, i32 %b) nounwind readnone ssp {
 entry:
-; CHECK: i:
+; CHECK-LABEL: i:
 ; CHECK: subs
 ; CHECK-NOT: cmp
   %cmp = icmp ult i32 %a, %b
@@ -48,7 +48,7 @@ entry:
 ; a swapped sub.
 define i32 @j(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: j:
+; CHECK-LABEL: j:
 ; CHECK: sub
 ; CHECK: cmp
   %cmp = icmp eq i32 %b, %a
diff --git a/test/CodeGen/ARM/swift-atomics.ll b/test/CodeGen/ARM/swift-atomics.ll
new file mode 100644
index 0000000..1d71815
--- /dev/null
+++ b/test/CodeGen/ARM/swift-atomics.ll
@@ -0,0 +1,45 @@
+; RUN: llc -mtriple=armv7-apple-ios6.0 -mcpu=swift < %s | FileCheck %s
+; RUN: llc -mtriple=armv7-apple-ios6.0 < %s | FileCheck %s --check-prefix=CHECK-STRICT-ATOMIC
+
+; Release operations only need the store barrier provided by a "dmb ishst",
+
+define void @test_store_release(i32* %p, i32 %v) {
+; CHECK-LABEL: test_store_release:
+; CHECK: dmb ishst
+; CHECK: str
+
+; CHECK-STRICT-ATOMIC: dmb {{ish$}}
+  store atomic i32 %v, i32* %p release, align 4
+  ret void
+}
+
+; However, if sequential consistency is needed *something* must ensure a release
+; followed by an acquire does not get reordered. In that case a "dmb ishst" is
+; not adequate.
+define i32 @test_seq_cst(i32* %p, i32 %v) {
+; CHECK-LABEL: test_seq_cst:
+; CHECK: dmb ishst
+; CHECK: str
+; CHECK: dmb {{ish$}}
+; CHECK: ldr
+; CHECK: dmb {{ish$}}
+
+; CHECK-STRICT-ATOMIC: dmb {{ish$}}
+; CHECK-STRICT-ATOMIC: dmb {{ish$}}
+
+  store atomic i32 %v, i32* %p seq_cst, align 4
+  %val = load atomic i32* %p seq_cst, align 4
+  ret i32 %val
+}
+
+; Also, pure acquire operations should definitely not have an ishst barrier.
+
+define i32 @test_acq(i32* %addr) {
+; CHECK-LABEL: test_acq:
+; CHECK: ldr
+; CHECK: dmb {{ish$}}
+
+; CHECK-STRICT-ATOMIC: dmb {{ish$}}
+  %val = load atomic i32* %addr acquire, align 4
+  ret i32 %val
+}
diff --git a/test/CodeGen/ARM/tail-dup.ll b/test/CodeGen/ARM/tail-dup.ll
index eb4d0ba..d654056 100644
--- a/test/CodeGen/ARM/tail-dup.ll
+++ b/test/CodeGen/ARM/tail-dup.ll
@@ -2,7 +2,7 @@
 
 ; We should be able to tail-duplicate the basic block containing the indirectbr
 ; into all of its predecessors.
-; CHECK: fn:
+; CHECK-LABEL: fn:
 ; CHECK: mov pc
 ; CHECK: mov pc
 ; CHECK: mov pc
diff --git a/test/CodeGen/ARM/tail-opts.ll b/test/CodeGen/ARM/tail-opts.ll
index 220b0f1..37e9a4a 100644
--- a/test/CodeGen/ARM/tail-opts.ll
+++ b/test/CodeGen/ARM/tail-opts.ll
@@ -14,7 +14,7 @@ declare i8* @choose(i8*, i8*)
 ; BranchFolding should tail-duplicate the indirect jump to avoid
 ; redundant branching.
 
-; CHECK: tail_duplicate_me:
+; CHECK-LABEL: tail_duplicate_me:
 ; CHECK:      qux
 ; CHECK:      movw r{{[0-9]+}}, :lower16:_GHJK
 ; CHECK:      movt r{{[0-9]+}}, :upper16:_GHJK
diff --git a/test/CodeGen/ARM/test-sharedidx.ll b/test/CodeGen/ARM/test-sharedidx.ll
index 93340c3..9203f16 100644
--- a/test/CodeGen/ARM/test-sharedidx.ll
+++ b/test/CodeGen/ARM/test-sharedidx.ll
@@ -14,7 +14,7 @@
 ; rdar://10674430
 define void @sharedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c, i32 %s, i32 %len) nounwind ssp {
 entry:
-; CHECK: sharedidx:
+; CHECK-LABEL: sharedidx:
   %cmp8 = icmp eq i32 %len, 0
   br i1 %cmp8, label %for.end, label %for.body
 
diff --git a/test/CodeGen/ARM/this-return.ll b/test/CodeGen/ARM/this-return.ll
index f06e4a4..cb42de6 100644
--- a/test/CodeGen/ARM/this-return.ll
+++ b/test/CodeGen/ARM/this-return.ll
@@ -17,12 +17,12 @@ declare %struct.B* @B_ctor_complete_nothisret(%struct.B*, i32)
 
 define %struct.C* @C_ctor_base(%struct.C* returned %this, i32 %x) {
 entry:
-; CHECKELF: C_ctor_base:
+; CHECKELF-LABEL: C_ctor_base:
 ; CHECKELF-NOT: mov {{r[0-9]+}}, r0
 ; CHECKELF: bl A_ctor_base
 ; CHECKELF-NOT: mov r0, {{r[0-9]+}}
 ; CHECKELF: b B_ctor_base
-; CHECKT2D: C_ctor_base:
+; CHECKT2D-LABEL: C_ctor_base:
 ; CHECKT2D-NOT: mov {{r[0-9]+}}, r0
 ; CHECKT2D: blx _A_ctor_base
 ; CHECKT2D-NOT: mov r0, {{r[0-9]+}}
@@ -36,12 +36,12 @@ entry:
 
 define %struct.C* @C_ctor_base_nothisret(%struct.C* %this, i32 %x) {
 entry:
-; CHECKELF: C_ctor_base_nothisret:
+; CHECKELF-LABEL: C_ctor_base_nothisret:
 ; CHECKELF: mov [[SAVETHIS:r[0-9]+]], r0
 ; CHECKELF: bl A_ctor_base_nothisret
 ; CHECKELF: mov r0, [[SAVETHIS]]
 ; CHECKELF-NOT: b B_ctor_base_nothisret
-; CHECKT2D: C_ctor_base_nothisret:
+; CHECKT2D-LABEL: C_ctor_base_nothisret:
 ; CHECKT2D: mov [[SAVETHIS:r[0-9]+]], r0
 ; CHECKT2D: blx _A_ctor_base_nothisret
 ; CHECKT2D: mov r0, [[SAVETHIS]]
@@ -55,9 +55,9 @@ entry:
 
 define %struct.C* @C_ctor_complete(%struct.C* %this, i32 %x) {
 entry:
-; CHECKELF: C_ctor_complete:
+; CHECKELF-LABEL: C_ctor_complete:
 ; CHECKELF: b C_ctor_base
-; CHECKT2D: C_ctor_complete:
+; CHECKT2D-LABEL: C_ctor_complete:
 ; CHECKT2D: b.w _C_ctor_base
   %call = tail call %struct.C* @C_ctor_base(%struct.C* %this, i32 %x)
   ret %struct.C* %this
@@ -65,9 +65,9 @@ entry:
 
 define %struct.C* @C_ctor_complete_nothisret(%struct.C* %this, i32 %x) {
 entry:
-; CHECKELF: C_ctor_complete_nothisret:
+; CHECKELF-LABEL: C_ctor_complete_nothisret:
 ; CHECKELF-NOT: b C_ctor_base_nothisret
-; CHECKT2D: C_ctor_complete_nothisret:
+; CHECKT2D-LABEL: C_ctor_complete_nothisret:
 ; CHECKT2D-NOT: b.w _C_ctor_base_nothisret
   %call = tail call %struct.C* @C_ctor_base_nothisret(%struct.C* %this, i32 %x)
   ret %struct.C* %this
@@ -75,12 +75,12 @@ entry:
 
 define %struct.D* @D_ctor_base(%struct.D* %this, i32 %x) {
 entry:
-; CHECKELF: D_ctor_base:
+; CHECKELF-LABEL: D_ctor_base:
 ; CHECKELF-NOT: mov {{r[0-9]+}}, r0
 ; CHECKELF: bl B_ctor_complete
 ; CHECKELF-NOT: mov r0, {{r[0-9]+}}
 ; CHECKELF: b B_ctor_complete
-; CHECKT2D: D_ctor_base:
+; CHECKT2D-LABEL: D_ctor_base:
 ; CHECKT2D-NOT: mov {{r[0-9]+}}, r0
 ; CHECKT2D: blx _B_ctor_complete
 ; CHECKT2D-NOT: mov r0, {{r[0-9]+}}
@@ -93,9 +93,9 @@ entry:
 
 define %struct.E* @E_ctor_base(%struct.E* %this, i32 %x) {
 entry:
-; CHECKELF: E_ctor_base:
+; CHECKELF-LABEL: E_ctor_base:
 ; CHECKELF-NOT: b B_ctor_complete
-; CHECKT2D: E_ctor_base:
+; CHECKT2D-LABEL: E_ctor_base:
 ; CHECKT2D-NOT: b.w _B_ctor_complete
   %b = getelementptr inbounds %struct.E* %this, i32 0, i32 0
   %call = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x)
diff --git a/test/CodeGen/ARM/thumb1-varalloc.ll b/test/CodeGen/ARM/thumb1-varalloc.ll
index aa88ae0..e07e8aa 100644
--- a/test/CodeGen/ARM/thumb1-varalloc.ll
+++ b/test/CodeGen/ARM/thumb1-varalloc.ll
@@ -39,4 +39,4 @@ bb3:
 }
 
 declare noalias i8* @strdup(i8* nocapture) nounwind
-declare i32 @_called_func(i8*, i32*) nounwind
\ No newline at end of file
+declare i32 @_called_func(i8*, i32*) nounwind
diff --git a/test/CodeGen/ARM/tls-models.ll b/test/CodeGen/ARM/tls-models.ll
index a5f3c90..ccc9032 100644
--- a/test/CodeGen/ARM/tls-models.ll
+++ b/test/CodeGen/ARM/tls-models.ll
@@ -21,9 +21,9 @@ entry:
   ret i32* @external_gd
 
   ; Non-PIC code can use initial-exec, PIC code has to use general dynamic.
-  ; CHECK-NONPIC:   f1:
+  ; CHECK-NONPIC-LABEL:   f1:
   ; CHECK-NONPIC:   external_gd(gottpoff)
-  ; CHECK-PIC:      f1:
+  ; CHECK-PIC-LABEL:      f1:
   ; CHECK-PIC:      external_gd(tlsgd)
 }
 
@@ -33,9 +33,9 @@ entry:
 
   ; Non-PIC code can use local exec, PIC code can use local dynamic,
   ; but that is not implemented, so falls back to general dynamic.
-  ; CHECK-NONPIC:   f2:
+  ; CHECK-NONPIC-LABEL:   f2:
   ; CHECK-NONPIC:   internal_gd(tpoff)
-  ; CHECK-PIC:      f2:
+  ; CHECK-PIC-LABEL:      f2:
   ; CHECK-PIC:      internal_gd(tlsgd)
 }
 
@@ -48,9 +48,9 @@ entry:
 
   ; Non-PIC code can use initial exec, PIC should use local dynamic,
   ; but that is not implemented, so falls back to general dynamic.
-  ; CHECK-NONPIC:   f3:
+  ; CHECK-NONPIC-LABEL:   f3:
   ; CHECK-NONPIC:   external_ld(gottpoff)
-  ; CHECK-PIC:      f3:
+  ; CHECK-PIC-LABEL:      f3:
   ; CHECK-PIC:      external_ld(tlsgd)
 }
 
@@ -60,9 +60,9 @@ entry:
 
   ; Non-PIC code can use local exec, PIC code can use local dynamic,
   ; but that is not implemented, so it falls back to general dynamic.
-  ; CHECK-NONPIC:   f4:
+  ; CHECK-NONPIC-LABEL:   f4:
   ; CHECK-NONPIC:   internal_ld(tpoff)
-  ; CHECK-PIC:      f4:
+  ; CHECK-PIC-LABEL:      f4:
   ; CHECK-PIC:      internal_ld(tlsgd)
 }
 
@@ -74,9 +74,9 @@ entry:
   ret i32* @external_ie
 
   ; Non-PIC and PIC code will use initial exec as specified.
-  ; CHECK-NONPIC:   f5:
+  ; CHECK-NONPIC-LABEL:   f5:
   ; CHECK-NONPIC:   external_ie(gottpoff)
-  ; CHECK-PIC:      f5:
+  ; CHECK-PIC-LABEL:      f5:
   ; CHECK-PIC:      external_ie(gottpoff)
 }
 
@@ -85,9 +85,9 @@ entry:
   ret i32* @internal_ie
 
   ; Non-PIC code can use local exec, PIC code use initial exec as specified.
-  ; CHECK-NONPIC:   f6:
+  ; CHECK-NONPIC-LABEL:   f6:
   ; CHECK-NONPIC:   internal_ie(tpoff)
-  ; CHECK-PIC:      f6:
+  ; CHECK-PIC-LABEL:      f6:
   ; CHECK-PIC:      internal_ie(gottpoff)
 }
 
@@ -99,9 +99,9 @@ entry:
   ret i32* @external_le
 
   ; Non-PIC and PIC code will use local exec as specified.
-  ; CHECK-NONPIC:   f7:
+  ; CHECK-NONPIC-LABEL:   f7:
   ; CHECK-NONPIC:   external_le(tpoff)
-  ; CHECK-PIC:      f7:
+  ; CHECK-PIC-LABEL:      f7:
   ; CHECK-PIC:      external_le(tpoff)
 }
 
@@ -110,8 +110,8 @@ entry:
   ret i32* @internal_le
 
   ; Non-PIC and PIC code will use local exec as specified.
-  ; CHECK-NONPIC:   f8:
+  ; CHECK-NONPIC-LABEL:   f8:
   ; CHECK-NONPIC:   internal_le(tpoff)
-  ; CHECK-PIC:      f8:
+  ; CHECK-PIC-LABEL:      f8:
   ; CHECK-PIC:      internal_le(tpoff)
 }
diff --git a/test/CodeGen/ARM/tls2.ll b/test/CodeGen/ARM/tls2.ll
index 57370c4..f048125 100644
--- a/test/CodeGen/ARM/tls2.ll
+++ b/test/CodeGen/ARM/tls2.ll
@@ -6,10 +6,10 @@
 @i = external thread_local global i32		; <i32*> [#uses=2]
 
 define i32 @f() {
-; CHECK-NONPIC: f:
+; CHECK-NONPIC-LABEL: f:
 ; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}]
 ; CHECK-NONPIC: i(gottpoff)
-; CHECK-PIC: f:
+; CHECK-PIC-LABEL: f:
 ; CHECK-PIC: __tls_get_addr
 entry:
 	%tmp1 = load i32* @i		; <i32> [#uses=1]
@@ -17,10 +17,10 @@ entry:
 }
 
 define i32* @g() {
-; CHECK-NONPIC: g:
+; CHECK-NONPIC-LABEL: g:
 ; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}]
 ; CHECK-NONPIC: i(gottpoff)
-; CHECK-PIC: g:
+; CHECK-PIC-LABEL: g:
 ; CHECK-PIC: __tls_get_addr
 entry:
 	ret i32* @i
diff --git a/test/CodeGen/ARM/trap.ll b/test/CodeGen/ARM/trap.ll
index a4e3c3c..db88a03 100644
--- a/test/CodeGen/ARM/trap.ll
+++ b/test/CodeGen/ARM/trap.ll
@@ -23,10 +23,10 @@
 
 define void @t() nounwind {
 entry:
-; INSTR: t:
+; INSTR-LABEL: t:
 ; INSTR: trap
 
-; FUNC: t:
+; FUNC-LABEL: t:
 ; FUNC: bl __trap
 
 ; ENCODING-NACL: f0 de fe e7
@@ -39,10 +39,10 @@ entry:
 
 define void @t2() nounwind {
 entry:
-; INSTR: t2:
+; INSTR-LABEL: t2:
 ; INSTR: trap
 
-; FUNC: t2:
+; FUNC-LABEL: t2:
 ; FUNC: bl __trap
 
 ; ENCODING-NACL: f0 de fe e7
diff --git a/test/CodeGen/ARM/twoaddrinstr.ll b/test/CodeGen/ARM/twoaddrinstr.ll
index fc2aa1e..2172f6b 100644
--- a/test/CodeGen/ARM/twoaddrinstr.ll
+++ b/test/CodeGen/ARM/twoaddrinstr.ll
@@ -3,7 +3,7 @@
 
 define void @PR13378() nounwind {
 ; This was orriginally a crasher trying to schedule the instructions.
-; CHECK:      PR13378:
+; CHECK-LABEL:      PR13378:
 ; CHECK:        vld1.32
 ; CHECK-NEXT:   vst1.32
 ; CHECK-NEXT:   vst1.32
diff --git a/test/CodeGen/ARM/umulo-32.ll b/test/CodeGen/ARM/umulo-32.ll
index fa5c016..19875ce 100644
--- a/test/CodeGen/ARM/umulo-32.ll
+++ b/test/CodeGen/ARM/umulo-32.ll
@@ -2,8 +2,8 @@
 
 %umul.ty = type { i32, i1 }
 
-define i32 @func(i32 %a) nounwind {
-; CHECK: func
+define i32 @test1(i32 %a) nounwind {
+; CHECK: test1:
 ; CHECK: muldi3
   %tmp0 = tail call %umul.ty @llvm.umul.with.overflow.i32(i32 %a, i32 37)
   %tmp1 = extractvalue %umul.ty %tmp0, 0
@@ -13,8 +13,8 @@ define i32 @func(i32 %a) nounwind {
 
 declare %umul.ty @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
 
-define i32 @f(i32 %argc, i8** %argv) ssp {
-; CHECK: func
+define i32 @test2(i32 %argc, i8** %argv) ssp {
+; CHECK: test2:
 ; CHECK: str     r0
 ; CHECK: movs    r2
 ; CHECK: mov     r1
diff --git a/test/CodeGen/ARM/unaligned_load_store.ll b/test/CodeGen/ARM/unaligned_load_store.ll
index 3064202..e7ff63f 100644
--- a/test/CodeGen/ARM/unaligned_load_store.ll
+++ b/test/CodeGen/ARM/unaligned_load_store.ll
@@ -7,7 +7,7 @@
 
 define void @t(i8* nocapture %a, i8* nocapture %b) nounwind {
 entry:
-; EXPANDED: t:
+; EXPANDED-LABEL: t:
 ; EXPANDED: ldrb [[R2:r[0-9]+]]
 ; EXPANDED: ldrb [[R3:r[0-9]+]]
 ; EXPANDED: ldrb [[R12:r[0-9]+]]
@@ -17,7 +17,7 @@ entry:
 ; EXPANDED: strb [[R3]]
 ; EXPANDED: strb [[R2]]
 
-; UNALIGNED: t:
+; UNALIGNED-LABEL: t:
 ; UNALIGNED: ldr r1
 ; UNALIGNED: str r1
 
@@ -30,13 +30,13 @@ entry:
 
 define void @hword(double* %a, double* %b) nounwind {
 entry:
-; EXPANDED: hword:
+; EXPANDED-LABEL: hword:
 ; EXPANDED-NOT: vld1
 ; EXPANDED: ldrh
 ; EXPANDED-NOT: str1
 ; EXPANDED: strh
 
-; UNALIGNED: hword:
+; UNALIGNED-LABEL: hword:
 ; UNALIGNED: vld1.16
 ; UNALIGNED: vst1.16
   %tmp = load double* %a, align 2
@@ -46,13 +46,13 @@ entry:
 
 define void @byte(double* %a, double* %b) nounwind {
 entry:
-; EXPANDED: byte:
+; EXPANDED-LABEL: byte:
 ; EXPANDED-NOT: vld1
 ; EXPANDED: ldrb
 ; EXPANDED-NOT: str1
 ; EXPANDED: strb
 
-; UNALIGNED: byte:
+; UNALIGNED-LABEL: byte:
 ; UNALIGNED: vld1.8
 ; UNALIGNED: vst1.8
   %tmp = load double* %a, align 1
@@ -62,11 +62,11 @@ entry:
 
 define void @byte_word_ops(i32* %a, i32* %b) nounwind {
 entry:
-; EXPANDED: byte_word_ops:
+; EXPANDED-LABEL: byte_word_ops:
 ; EXPANDED: ldrb
 ; EXPANDED: strb
 
-; UNALIGNED: byte_word_ops:
+; UNALIGNED-LABEL: byte_word_ops:
 ; UNALIGNED-NOT: ldrb
 ; UNALIGNED: ldr
 ; UNALIGNED-NOT: strb
diff --git a/test/CodeGen/ARM/unaligned_load_store_vector.ll b/test/CodeGen/ARM/unaligned_load_store_vector.ll
index 25ae651..968a2c7 100644
--- a/test/CodeGen/ARM/unaligned_load_store_vector.ll
+++ b/test/CodeGen/ARM/unaligned_load_store_vector.ll
@@ -4,7 +4,7 @@
 ;SIZE  = 64
 ;TYPE  = <8 x i8>
 define void @v64_v8i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v8i8_1:
+;CHECK-LABEL: v64_v8i8_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -22,7 +22,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <4 x i16>
 define void @v64_v4i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v4i16_1:
+;CHECK-LABEL: v64_v4i16_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -40,7 +40,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <2 x i32>
 define void @v64_v2i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2i32_1:
+;CHECK-LABEL: v64_v2i32_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -58,7 +58,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <2 x float>
 define void @v64_v2f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2f32_1:
+;CHECK-LABEL: v64_v2f32_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -76,7 +76,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <16 x i8>
 define void @v128_v16i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v16i8_1:
+;CHECK-LABEL: v128_v16i8_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -94,7 +94,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <8 x i16>
 define void @v128_v8i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v8i16_1:
+;CHECK-LABEL: v128_v8i16_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -112,7 +112,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <4 x i32>
 define void @v128_v4i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4i32_1:
+;CHECK-LABEL: v128_v4i32_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -130,7 +130,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <2 x i64>
 define void @v128_v2i64_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v2i64_1:
+;CHECK-LABEL: v128_v2i64_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -148,7 +148,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <4 x float>
 define void @v128_v4f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4f32_1:
+;CHECK-LABEL: v128_v4f32_1:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -166,7 +166,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <8 x i8>
 define void @v64_v8i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v8i8_2:
+;CHECK-LABEL: v64_v8i8_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -184,7 +184,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <4 x i16>
 define void @v64_v4i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v4i16_2:
+;CHECK-LABEL: v64_v4i16_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -202,7 +202,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <2 x i32>
 define void @v64_v2i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2i32_2:
+;CHECK-LABEL: v64_v2i32_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -220,7 +220,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <2 x float>
 define void @v64_v2f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2f32_2:
+;CHECK-LABEL: v64_v2f32_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -238,7 +238,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <16 x i8>
 define void @v128_v16i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v16i8_2:
+;CHECK-LABEL: v128_v16i8_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -256,7 +256,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <8 x i16>
 define void @v128_v8i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v8i16_2:
+;CHECK-LABEL: v128_v8i16_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -274,7 +274,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <4 x i32>
 define void @v128_v4i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4i32_2:
+;CHECK-LABEL: v128_v4i32_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -292,7 +292,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <2 x i64>
 define void @v128_v2i64_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v2i64_2:
+;CHECK-LABEL: v128_v2i64_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -310,7 +310,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <4 x float>
 define void @v128_v4f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4f32_2:
+;CHECK-LABEL: v128_v4f32_2:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -328,7 +328,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <8 x i8>
 define void @v64_v8i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v8i8_4:
+;CHECK-LABEL: v64_v8i8_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -346,7 +346,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <4 x i16>
 define void @v64_v4i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v4i16_4:
+;CHECK-LABEL: v64_v4i16_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -364,7 +364,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <2 x i32>
 define void @v64_v2i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2i32_4:
+;CHECK-LABEL: v64_v2i32_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -382,7 +382,7 @@ entry:
 ;SIZE  = 64
 ;TYPE  = <2 x float>
 define void @v64_v2f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2f32_4:
+;CHECK-LABEL: v64_v2f32_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -400,7 +400,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <16 x i8>
 define void @v128_v16i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v16i8_4:
+;CHECK-LABEL: v128_v16i8_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -418,7 +418,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <8 x i16>
 define void @v128_v8i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v8i16_4:
+;CHECK-LABEL: v128_v8i16_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -436,7 +436,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <4 x i32>
 define void @v128_v4i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4i32_4:
+;CHECK-LABEL: v128_v4i32_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -454,7 +454,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <2 x i64>
 define void @v128_v2i64_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v2i64_4:
+;CHECK-LABEL: v128_v2i64_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
@@ -472,7 +472,7 @@ entry:
 ;SIZE  = 128
 ;TYPE  = <4 x float>
 define void @v128_v4f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4f32_4:
+;CHECK-LABEL: v128_v4f32_4:
 entry:
   %po = getelementptr i8* %out, i32 0
   %pi = getelementptr i8* %in,  i32 0
diff --git a/test/CodeGen/ARM/undef-sext.ll b/test/CodeGen/ARM/undef-sext.ll
index 2c28da3..c6d76d0 100644
--- a/test/CodeGen/ARM/undef-sext.ll
+++ b/test/CodeGen/ARM/undef-sext.ll
@@ -4,7 +4,7 @@
 
 define i32 @t(i32* %a) nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: ldr r0, [r0]
 ; CHECK: bx lr
   %0 = sext i16 undef to i32
diff --git a/test/CodeGen/ARM/unwind-init.ll b/test/CodeGen/ARM/unwind-init.ll
new file mode 100644
index 0000000..1e12f55
--- /dev/null
+++ b/test/CodeGen/ARM/unwind-init.ll
@@ -0,0 +1,18 @@
+; RUN: llc -mtriple=armv7-unknown-linux-gnueabi < %s | FileCheck %s
+; Check that all callee-saved registers are saved and restored in functions
+; that call __builtin_unwind_init(). This is its undocumented behavior in gcc,
+; and it is used in compiling libgcc_eh.
+; See also PR8541
+
+declare void @llvm.eh.unwind.init()
+
+define void @calls_unwind_init() {
+  call void @llvm.eh.unwind.init()
+  ret void
+}
+
+; CHECK-LABEL: calls_unwind_init:
+; CHECK: push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK: vpush   {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK: vpop    {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK: pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}
diff --git a/test/CodeGen/ARM/v1-constant-fold.ll b/test/CodeGen/ARM/v1-constant-fold.ll
index b86d5db..eb49a81 100644
--- a/test/CodeGen/ARM/v1-constant-fold.ll
+++ b/test/CodeGen/ARM/v1-constant-fold.ll
@@ -2,7 +2,7 @@
 
 ; PR15611. Check that we don't crash when constant folding v1i32 types.
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 define void @foo(i32 %arg) {
 bb:
   %tmp = insertelement <4 x i32> undef, i32 %arg, i32 0
diff --git a/test/CodeGen/ARM/va_arg.ll b/test/CodeGen/ARM/va_arg.ll
index af477b4..f18b498 100644
--- a/test/CodeGen/ARM/va_arg.ll
+++ b/test/CodeGen/ARM/va_arg.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s
 ; Test that we correctly align elements when using va_arg
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: bfc
 ; CHECK: add	[[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
 ; CHECK: bfc	[[REG]], #0, #3
@@ -17,7 +17,7 @@ entry:
   ret i64 %0
 }
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK-NOT: bfc
 ; CHECK: add	[[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
 ; CHECK: bfc	[[REG]], #0, #3
diff --git a/test/CodeGen/ARM/vaba.ll b/test/CodeGen/ARM/vaba.ll
index 4fe1c43..97139e9 100644
--- a/test/CodeGen/ARM/vaba.ll
+++ b/test/CodeGen/ARM/vaba.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabas8:
+;CHECK-LABEL: vabas8:
 ;CHECK: vaba.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabas16:
+;CHECK-LABEL: vabas16:
 ;CHECK: vaba.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -23,7 +23,7 @@ define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabas32:
+;CHECK-LABEL: vabas32:
 ;CHECK: vaba.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -34,7 +34,7 @@ define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabau8:
+;CHECK-LABEL: vabau8:
 ;CHECK: vaba.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -45,7 +45,7 @@ define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabau16:
+;CHECK-LABEL: vabau16:
 ;CHECK: vaba.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -56,7 +56,7 @@ define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabau32:
+;CHECK-LABEL: vabau32:
 ;CHECK: vaba.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -67,7 +67,7 @@ define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: vabaQs8:
+;CHECK-LABEL: vabaQs8:
 ;CHECK: vaba.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -78,7 +78,7 @@ define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
 }
 
 define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vabaQs16:
+;CHECK-LABEL: vabaQs16:
 ;CHECK: vaba.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -89,7 +89,7 @@ define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
 }
 
 define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vabaQs32:
+;CHECK-LABEL: vabaQs32:
 ;CHECK: vaba.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind
 }
 
 define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: vabaQu8:
+;CHECK-LABEL: vabaQu8:
 ;CHECK: vaba.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -111,7 +111,7 @@ define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
 }
 
 define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vabaQu16:
+;CHECK-LABEL: vabaQu16:
 ;CHECK: vaba.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -122,7 +122,7 @@ define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
 }
 
 define <4 x i32> @vabaQu32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vabaQu32:
+;CHECK-LABEL: vabaQu32:
 ;CHECK: vaba.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -149,7 +149,7 @@ declare <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16>, <8 x i16>) nounwind read
 declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabals8:
+;CHECK-LABEL: vabals8:
 ;CHECK: vabal.s8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -161,7 +161,7 @@ define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabals16:
+;CHECK-LABEL: vabals16:
 ;CHECK: vabal.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -173,7 +173,7 @@ define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabals32:
+;CHECK-LABEL: vabals32:
 ;CHECK: vabal.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -185,7 +185,7 @@ define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabalu8:
+;CHECK-LABEL: vabalu8:
 ;CHECK: vabal.u8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -197,7 +197,7 @@ define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabalu16:
+;CHECK-LABEL: vabalu16:
 ;CHECK: vabal.u16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -209,7 +209,7 @@ define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i64> @vabalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabalu32:
+;CHECK-LABEL: vabalu32:
 ;CHECK: vabal.u32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
diff --git a/test/CodeGen/ARM/vabd.ll b/test/CodeGen/ARM/vabd.ll
index 9ec734f..2eb6d93 100644
--- a/test/CodeGen/ARM/vabd.ll
+++ b/test/CodeGen/ARM/vabd.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabds8:
+;CHECK-LABEL: vabds8:
 ;CHECK: vabd.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vabds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabds16:
+;CHECK-LABEL: vabds16:
 ;CHECK: vabd.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vabds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vabds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabds32:
+;CHECK-LABEL: vabds32:
 ;CHECK: vabd.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vabds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vabdu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabdu8:
+;CHECK-LABEL: vabdu8:
 ;CHECK: vabd.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vabdu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vabdu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabdu16:
+;CHECK-LABEL: vabdu16:
 ;CHECK: vabd.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @vabdu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vabdu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabdu32:
+;CHECK-LABEL: vabdu32:
 ;CHECK: vabd.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <2 x i32> @vabdu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vabdf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vabdf32:
+;CHECK-LABEL: vabdf32:
 ;CHECK: vabd.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -64,7 +64,7 @@ define <2 x float> @vabdf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vabdQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vabdQs8:
+;CHECK-LABEL: vabdQs8:
 ;CHECK: vabd.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -73,7 +73,7 @@ define <16 x i8> @vabdQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vabdQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vabdQs16:
+;CHECK-LABEL: vabdQs16:
 ;CHECK: vabd.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -82,7 +82,7 @@ define <8 x i16> @vabdQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vabdQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vabdQs32:
+;CHECK-LABEL: vabdQs32:
 ;CHECK: vabd.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -91,7 +91,7 @@ define <4 x i32> @vabdQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vabdQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vabdQu8:
+;CHECK-LABEL: vabdQu8:
 ;CHECK: vabd.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -100,7 +100,7 @@ define <16 x i8> @vabdQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vabdQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vabdQu16:
+;CHECK-LABEL: vabdQu16:
 ;CHECK: vabd.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -109,7 +109,7 @@ define <8 x i16> @vabdQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vabdQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vabdQu32:
+;CHECK-LABEL: vabdQu32:
 ;CHECK: vabd.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -118,7 +118,7 @@ define <4 x i32> @vabdQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vabdQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vabdQf32:
+;CHECK-LABEL: vabdQf32:
 ;CHECK: vabd.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -147,7 +147,7 @@ declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind read
 declare <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float>, <4 x float>) nounwind readnone
 
 define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabdls8:
+;CHECK-LABEL: vabdls8:
 ;CHECK: vabdl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -157,7 +157,7 @@ define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabdls16:
+;CHECK-LABEL: vabdls16:
 ;CHECK: vabdl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -167,7 +167,7 @@ define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabdls32:
+;CHECK-LABEL: vabdls32:
 ;CHECK: vabdl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -177,7 +177,7 @@ define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabdlu8:
+;CHECK-LABEL: vabdlu8:
 ;CHECK: vabdl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -187,7 +187,7 @@ define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabdlu16:
+;CHECK-LABEL: vabdlu16:
 ;CHECK: vabdl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -197,7 +197,7 @@ define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vabdlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabdlu32:
+;CHECK-LABEL: vabdlu32:
 ;CHECK: vabdl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
diff --git a/test/CodeGen/ARM/vabs.ll b/test/CodeGen/ARM/vabs.ll
index 18ba61f..96dd38e 100644
--- a/test/CodeGen/ARM/vabs.ll
+++ b/test/CodeGen/ARM/vabs.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
-;CHECK: vabss8:
+;CHECK-LABEL: vabss8:
 ;CHECK: vabs.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1)
@@ -9,7 +9,7 @@ define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
-;CHECK: vabss16:
+;CHECK-LABEL: vabss16:
 ;CHECK: vabs.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1)
@@ -17,7 +17,7 @@ define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
-;CHECK: vabss32:
+;CHECK-LABEL: vabss32:
 ;CHECK: vabs.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1)
@@ -25,7 +25,7 @@ define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
 }
 
 define <2 x float> @vabsf32(<2 x float>* %A) nounwind {
-;CHECK: vabsf32:
+;CHECK-LABEL: vabsf32:
 ;CHECK: vabs.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = call <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float> %tmp1)
@@ -33,7 +33,7 @@ define <2 x float> @vabsf32(<2 x float>* %A) nounwind {
 }
 
 define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vabsQs8:
+;CHECK-LABEL: vabsQs8:
 ;CHECK: vabs.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1)
@@ -41,7 +41,7 @@ define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vabsQs16:
+;CHECK-LABEL: vabsQs16:
 ;CHECK: vabs.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1)
@@ -49,7 +49,7 @@ define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vabsQs32:
+;CHECK-LABEL: vabsQs32:
 ;CHECK: vabs.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1)
@@ -57,7 +57,7 @@ define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind {
 }
 
 define <4 x float> @vabsQf32(<4 x float>* %A) nounwind {
-;CHECK: vabsQf32:
+;CHECK-LABEL: vabsQf32:
 ;CHECK: vabs.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float> %tmp1)
@@ -75,7 +75,7 @@ declare <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32>) nounwind readnone
 declare <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float>) nounwind readnone
 
 define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind {
-;CHECK: vqabss8:
+;CHECK-LABEL: vqabss8:
 ;CHECK: vqabs.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1)
@@ -83,7 +83,7 @@ define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind {
-;CHECK: vqabss16:
+;CHECK-LABEL: vqabss16:
 ;CHECK: vqabs.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1)
@@ -91,7 +91,7 @@ define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind {
-;CHECK: vqabss32:
+;CHECK-LABEL: vqabss32:
 ;CHECK: vqabs.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1)
@@ -99,7 +99,7 @@ define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind {
 }
 
 define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vqabsQs8:
+;CHECK-LABEL: vqabsQs8:
 ;CHECK: vqabs.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1)
@@ -107,7 +107,7 @@ define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vqabsQs16:
+;CHECK-LABEL: vqabsQs16:
 ;CHECK: vqabs.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1)
@@ -115,7 +115,7 @@ define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vqabsQs32:
+;CHECK-LABEL: vqabsQs32:
 ;CHECK: vqabs.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1)
diff --git a/test/CodeGen/ARM/vadd.ll b/test/CodeGen/ARM/vadd.ll
index a830e96..a1ad37b 100644
--- a/test/CodeGen/ARM/vadd.ll
+++ b/test/CodeGen/ARM/vadd.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddi8:
+;CHECK-LABEL: vaddi8:
 ;CHECK: vadd.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddi16:
+;CHECK-LABEL: vaddi16:
 ;CHECK: vadd.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddi32:
+;CHECK-LABEL: vaddi32:
 ;CHECK: vadd.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vaddi64:
+;CHECK-LABEL: vaddi64:
 ;CHECK: vadd.i64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vaddf32:
+;CHECK-LABEL: vaddf32:
 ;CHECK: vadd.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -46,7 +46,7 @@ define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vaddQi8:
+;CHECK-LABEL: vaddQi8:
 ;CHECK: vadd.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -55,7 +55,7 @@ define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vaddQi16:
+;CHECK-LABEL: vaddQi16:
 ;CHECK: vadd.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -64,7 +64,7 @@ define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vaddQi32:
+;CHECK-LABEL: vaddQi32:
 ;CHECK: vadd.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -73,7 +73,7 @@ define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vaddQi64:
+;CHECK-LABEL: vaddQi64:
 ;CHECK: vadd.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -82,7 +82,7 @@ define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vaddQf32:
+;CHECK-LABEL: vaddQf32:
 ;CHECK: vadd.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -91,7 +91,7 @@ define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 }
 
 define <8 x i8> @vaddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vaddhni16:
+;CHECK-LABEL: vaddhni16:
 ;CHECK: vaddhn.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -100,7 +100,7 @@ define <8 x i8> @vaddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i16> @vaddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vaddhni32:
+;CHECK-LABEL: vaddhni32:
 ;CHECK: vaddhn.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -109,7 +109,7 @@ define <4 x i16> @vaddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vaddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vaddhni64:
+;CHECK-LABEL: vaddhni64:
 ;CHECK: vaddhn.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -122,7 +122,7 @@ declare <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32>, <4 x i32>) nounwind rea
 declare <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vraddhni16:
+;CHECK-LABEL: vraddhni16:
 ;CHECK: vraddhn.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -131,7 +131,7 @@ define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vraddhni32:
+;CHECK-LABEL: vraddhni32:
 ;CHECK: vraddhn.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -140,7 +140,7 @@ define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vraddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vraddhni64:
+;CHECK-LABEL: vraddhni64:
 ;CHECK: vraddhn.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -153,7 +153,7 @@ declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) nounwind re
 declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddls8:
+;CHECK-LABEL: vaddls8:
 ;CHECK: vaddl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -164,7 +164,7 @@ define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddls16:
+;CHECK-LABEL: vaddls16:
 ;CHECK: vaddl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -175,7 +175,7 @@ define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddls32:
+;CHECK-LABEL: vaddls32:
 ;CHECK: vaddl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -186,7 +186,7 @@ define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddlu8:
+;CHECK-LABEL: vaddlu8:
 ;CHECK: vaddl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -197,7 +197,7 @@ define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddlu16:
+;CHECK-LABEL: vaddlu16:
 ;CHECK: vaddl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -208,7 +208,7 @@ define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddlu32:
+;CHECK-LABEL: vaddlu32:
 ;CHECK: vaddl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -219,7 +219,7 @@ define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddws8:
+;CHECK-LABEL: vaddws8:
 ;CHECK: vaddw.s8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -229,7 +229,7 @@ define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddws16:
+;CHECK-LABEL: vaddws16:
 ;CHECK: vaddw.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -239,7 +239,7 @@ define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddws32:
+;CHECK-LABEL: vaddws32:
 ;CHECK: vaddw.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -249,7 +249,7 @@ define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddwu8:
+;CHECK-LABEL: vaddwu8:
 ;CHECK: vaddw.u8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -259,7 +259,7 @@ define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddwu16:
+;CHECK-LABEL: vaddwu16:
 ;CHECK: vaddw.u16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -269,7 +269,7 @@ define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vaddwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddwu32:
+;CHECK-LABEL: vaddwu32:
 ;CHECK: vaddw.u32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
diff --git a/test/CodeGen/ARM/vbits.ll b/test/CodeGen/ARM/vbits.ll
index 51f9bdf..7b48441 100644
--- a/test/CodeGen/ARM/vbits.ll
+++ b/test/CodeGen/ARM/vbits.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon -mcpu=cortex-a8 | FileCheck %s
 
 define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_andi8:
+;CHECK-LABEL: v_andi8:
 ;CHECK: vand
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_andi16:
+;CHECK-LABEL: v_andi16:
 ;CHECK: vand
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_andi32:
+;CHECK-LABEL: v_andi32:
 ;CHECK: vand
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_andi64:
+;CHECK-LABEL: v_andi64:
 ;CHECK: vand
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_andQi8:
+;CHECK-LABEL: v_andQi8:
 ;CHECK: vand
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -46,7 +46,7 @@ define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_andQi16:
+;CHECK-LABEL: v_andQi16:
 ;CHECK: vand
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -55,7 +55,7 @@ define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_andQi32:
+;CHECK-LABEL: v_andQi32:
 ;CHECK: vand
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -64,7 +64,7 @@ define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_andQi64:
+;CHECK-LABEL: v_andQi64:
 ;CHECK: vand
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -73,7 +73,7 @@ define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_bici8:
+;CHECK-LABEL: v_bici8:
 ;CHECK: vbic
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -83,7 +83,7 @@ define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_bici16:
+;CHECK-LABEL: v_bici16:
 ;CHECK: vbic
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -93,7 +93,7 @@ define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_bici32:
+;CHECK-LABEL: v_bici32:
 ;CHECK: vbic
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -103,7 +103,7 @@ define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_bici64:
+;CHECK-LABEL: v_bici64:
 ;CHECK: vbic
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -113,7 +113,7 @@ define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_bicQi8:
+;CHECK-LABEL: v_bicQi8:
 ;CHECK: vbic
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -123,7 +123,7 @@ define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_bicQi16:
+;CHECK-LABEL: v_bicQi16:
 ;CHECK: vbic
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -133,7 +133,7 @@ define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_bicQi32:
+;CHECK-LABEL: v_bicQi32:
 ;CHECK: vbic
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -143,7 +143,7 @@ define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_bicQi64:
+;CHECK-LABEL: v_bicQi64:
 ;CHECK: vbic
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -153,7 +153,7 @@ define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_eori8:
+;CHECK-LABEL: v_eori8:
 ;CHECK: veor
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -162,7 +162,7 @@ define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_eori16:
+;CHECK-LABEL: v_eori16:
 ;CHECK: veor
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -171,7 +171,7 @@ define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_eori32:
+;CHECK-LABEL: v_eori32:
 ;CHECK: veor
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -180,7 +180,7 @@ define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_eori64:
+;CHECK-LABEL: v_eori64:
 ;CHECK: veor
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -189,7 +189,7 @@ define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_eorQi8:
+;CHECK-LABEL: v_eorQi8:
 ;CHECK: veor
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -198,7 +198,7 @@ define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_eorQi16:
+;CHECK-LABEL: v_eorQi16:
 ;CHECK: veor
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -207,7 +207,7 @@ define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_eorQi32:
+;CHECK-LABEL: v_eorQi32:
 ;CHECK: veor
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -216,7 +216,7 @@ define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_eorQi64:
+;CHECK-LABEL: v_eorQi64:
 ;CHECK: veor
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -225,7 +225,7 @@ define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind {
-;CHECK: v_mvni8:
+;CHECK-LABEL: v_mvni8:
 ;CHECK: vmvn
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
@@ -233,7 +233,7 @@ define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind {
-;CHECK: v_mvni16:
+;CHECK-LABEL: v_mvni16:
 ;CHECK: vmvn
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 >
@@ -241,7 +241,7 @@ define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind {
-;CHECK: v_mvni32:
+;CHECK-LABEL: v_mvni32:
 ;CHECK: vmvn
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 >
@@ -249,7 +249,7 @@ define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind {
-;CHECK: v_mvni64:
+;CHECK-LABEL: v_mvni64:
 ;CHECK: vmvn
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = xor <1 x i64> %tmp1, < i64 -1 >
@@ -257,7 +257,7 @@ define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind {
-;CHECK: v_mvnQi8:
+;CHECK-LABEL: v_mvnQi8:
 ;CHECK: vmvn
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
@@ -265,7 +265,7 @@ define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind {
-;CHECK: v_mvnQi16:
+;CHECK-LABEL: v_mvnQi16:
 ;CHECK: vmvn
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
@@ -273,7 +273,7 @@ define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind {
-;CHECK: v_mvnQi32:
+;CHECK-LABEL: v_mvnQi32:
 ;CHECK: vmvn
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 >
@@ -281,7 +281,7 @@ define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind {
-;CHECK: v_mvnQi64:
+;CHECK-LABEL: v_mvnQi64:
 ;CHECK: vmvn
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 >
@@ -289,7 +289,7 @@ define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_orri8:
+;CHECK-LABEL: v_orri8:
 ;CHECK: vorr
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -298,7 +298,7 @@ define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_orri16:
+;CHECK-LABEL: v_orri16:
 ;CHECK: vorr
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -307,7 +307,7 @@ define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_orri32:
+;CHECK-LABEL: v_orri32:
 ;CHECK: vorr
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -316,7 +316,7 @@ define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_orri64:
+;CHECK-LABEL: v_orri64:
 ;CHECK: vorr
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -325,7 +325,7 @@ define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_orrQi8:
+;CHECK-LABEL: v_orrQi8:
 ;CHECK: vorr
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -334,7 +334,7 @@ define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_orrQi16:
+;CHECK-LABEL: v_orrQi16:
 ;CHECK: vorr
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -343,7 +343,7 @@ define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_orrQi32:
+;CHECK-LABEL: v_orrQi32:
 ;CHECK: vorr
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -352,7 +352,7 @@ define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_orrQi64:
+;CHECK-LABEL: v_orrQi64:
 ;CHECK: vorr
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -361,7 +361,7 @@ define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_orni8:
+;CHECK-LABEL: v_orni8:
 ;CHECK: vorn
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -371,7 +371,7 @@ define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_orni16:
+;CHECK-LABEL: v_orni16:
 ;CHECK: vorn
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -381,7 +381,7 @@ define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_orni32:
+;CHECK-LABEL: v_orni32:
 ;CHECK: vorn
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -391,7 +391,7 @@ define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_orni64:
+;CHECK-LABEL: v_orni64:
 ;CHECK: vorn
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -401,7 +401,7 @@ define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_ornQi8:
+;CHECK-LABEL: v_ornQi8:
 ;CHECK: vorn
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -411,7 +411,7 @@ define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_ornQi16:
+;CHECK-LABEL: v_ornQi16:
 ;CHECK: vorn
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -421,7 +421,7 @@ define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_ornQi32:
+;CHECK-LABEL: v_ornQi32:
 ;CHECK: vorn
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -431,7 +431,7 @@ define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_ornQi64:
+;CHECK-LABEL: v_ornQi64:
 ;CHECK: vorn
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -441,7 +441,7 @@ define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtsti8:
+;CHECK-LABEL: vtsti8:
 ;CHECK: vtst.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -452,7 +452,7 @@ define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vtsti16:
+;CHECK-LABEL: vtsti16:
 ;CHECK: vtst.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -463,7 +463,7 @@ define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vtsti32:
+;CHECK-LABEL: vtsti32:
 ;CHECK: vtst.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -474,7 +474,7 @@ define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vtstQi8:
+;CHECK-LABEL: vtstQi8:
 ;CHECK: vtst.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -485,7 +485,7 @@ define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vtstQi16:
+;CHECK-LABEL: vtstQi16:
 ;CHECK: vtst.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -496,7 +496,7 @@ define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vtstQi32:
+;CHECK-LABEL: vtstQi32:
 ;CHECK: vtst.32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -507,7 +507,7 @@ define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind {
-; CHECK: v_orrimm:
+; CHECK-LABEL: v_orrimm:
 ; CHECK-NOT: vmov
 ; CHECK-NOT: vmvn
 ; CHECK: vorr
@@ -527,7 +527,7 @@ define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
-; CHECK: v_bicimm:
+; CHECK-LABEL: v_bicimm:
 ; CHECK-NOT: vmov
 ; CHECK-NOT: vmvn
 ; CHECK: vbic
@@ -537,7 +537,7 @@ define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
 }
 
 define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
-; CHECK: v_bicimmQ:
+; CHECK-LABEL: v_bicimmQ:
 ; CHECK-NOT: vmov
 ; CHECK-NOT: vmvn
 ; CHECK: vbic
diff --git a/test/CodeGen/ARM/vbsl-constant.ll b/test/CodeGen/ARM/vbsl-constant.ll
index ffda0a5..5e033fe 100644
--- a/test/CodeGen/ARM/vbsl-constant.ll
+++ b/test/CodeGen/ARM/vbsl-constant.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+neon | FileCheck %s
 
 define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: v_bsli8:
+;CHECK-LABEL: v_bsli8:
 ;CHECK: vldr
 ;CHECK: vldr
 ;CHECK: vbsl
@@ -15,7 +15,7 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: v_bsli16:
+;CHECK-LABEL: v_bsli16:
 ;CHECK: vldr
 ;CHECK: vldr
 ;CHECK: vbsl
@@ -29,7 +29,7 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: v_bsli32:
+;CHECK-LABEL: v_bsli32:
 ;CHECK: vldr
 ;CHECK: vldr
 ;CHECK: vbsl
@@ -43,7 +43,7 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
-;CHECK: v_bsli64:
+;CHECK-LABEL: v_bsli64:
 ;CHECK: vldr
 ;CHECK: vldr
 ;CHECK: vldr
@@ -58,7 +58,7 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind
 }
 
 define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: v_bslQi8:
+;CHECK-LABEL: v_bslQi8:
 ;CHECK: vld1.32
 ;CHECK: vld1.32
 ;CHECK: vbsl
@@ -72,7 +72,7 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
 }
 
 define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: v_bslQi16:
+;CHECK-LABEL: v_bslQi16:
 ;CHECK: vld1.32
 ;CHECK: vld1.32
 ;CHECK: vbsl
@@ -86,7 +86,7 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwin
 }
 
 define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: v_bslQi32:
+;CHECK-LABEL: v_bslQi32:
 ;CHECK: vld1.32
 ;CHECK: vld1.32
 ;CHECK: vbsl
@@ -100,7 +100,7 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwin
 }
 
 define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
-;CHECK: v_bslQi64:
+;CHECK-LABEL: v_bslQi64:
 ;CHECK: vld1.32
 ;CHECK: vld1.32
 ;CHECK: vld1.64
diff --git a/test/CodeGen/ARM/vbsl.ll b/test/CodeGen/ARM/vbsl.ll
index 750fb0d..1e53e51 100644
--- a/test/CodeGen/ARM/vbsl.ll
+++ b/test/CodeGen/ARM/vbsl.ll
@@ -3,7 +3,7 @@
 ; rdar://12471808
 
 define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: v_bsli8:
+;CHECK-LABEL: v_bsli8:
 ;CHECK: vbsl
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -16,7 +16,7 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: v_bsli16:
+;CHECK-LABEL: v_bsli16:
 ;CHECK: vbsl
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -29,7 +29,7 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: v_bsli32:
+;CHECK-LABEL: v_bsli32:
 ;CHECK: vbsl
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -42,7 +42,7 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
-;CHECK: v_bsli64:
+;CHECK-LABEL: v_bsli64:
 ;CHECK: vbsl
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -55,7 +55,7 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind
 }
 
 define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: v_bslQi8:
+;CHECK-LABEL: v_bslQi8:
 ;CHECK: vbsl
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -68,7 +68,7 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind
 }
 
 define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: v_bslQi16:
+;CHECK-LABEL: v_bslQi16:
 ;CHECK: vbsl
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -81,7 +81,7 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwin
 }
 
 define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: v_bslQi32:
+;CHECK-LABEL: v_bslQi32:
 ;CHECK: vbsl
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -94,7 +94,7 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwin
 }
 
 define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
-;CHECK: v_bslQi64:
+;CHECK-LABEL: v_bslQi64:
 ;CHECK: vbsl
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -107,84 +107,84 @@ define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwin
 }
 
 define <8 x i8> @f1(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind readnone optsize ssp {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: vbsl
   %vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind
   ret <8 x i8> %vbsl.i
 }
 
 define <4 x i16> @f2(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: vbsl
   %vbsl3.i = tail call <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind
   ret <4 x i16> %vbsl3.i
 }
 
 define <2 x i32> @f3(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: vbsl
   %vbsl3.i = tail call <2 x i32> @llvm.arm.neon.vbsl.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind
   ret <2 x i32> %vbsl3.i
 }
 
 define <2 x float> @f4(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone optsize ssp {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: vbsl
   %vbsl4.i = tail call <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind
   ret <2 x float> %vbsl4.i
 }
 
 define <16 x i8> @g1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind readnone optsize ssp {
-; CHECK: g1:
+; CHECK-LABEL: g1:
 ; CHECK: vbsl
   %vbsl.i = tail call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind
   ret <16 x i8> %vbsl.i
 }
 
 define <8 x i16> @g2(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind readnone optsize ssp {
-; CHECK: g2:
+; CHECK-LABEL: g2:
 ; CHECK: vbsl
   %vbsl3.i = tail call <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind
   ret <8 x i16> %vbsl3.i
 }
 
 define <4 x i32> @g3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
-; CHECK: g3:
+; CHECK-LABEL: g3:
 ; CHECK: vbsl
   %vbsl3.i = tail call <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind
   ret <4 x i32> %vbsl3.i
 }
 
 define <4 x float> @g4(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone optsize ssp {
-; CHECK: g4:
+; CHECK-LABEL: g4:
 ; CHECK: vbsl
   %vbsl4.i = tail call <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind
   ret <4 x float> %vbsl4.i
 }
 
 define <1 x i64> @test_vbsl_s64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
-; CHECK: test_vbsl_s64:
+; CHECK-LABEL: test_vbsl_s64:
 ; CHECK: vbsl d
   %vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
   ret <1 x i64> %vbsl3.i
 }
 
 define <1 x i64> @test_vbsl_u64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
-; CHECK: test_vbsl_u64:
+; CHECK-LABEL: test_vbsl_u64:
 ; CHECK: vbsl d
   %vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
   ret <1 x i64> %vbsl3.i
 }
 
 define <2 x i64> @test_vbslq_s64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
-; CHECK: test_vbslq_s64:
+; CHECK-LABEL: test_vbslq_s64:
 ; CHECK: vbsl q
   %vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
   ret <2 x i64> %vbsl3.i
 }
 
 define <2 x i64> @test_vbslq_u64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
-; CHECK: test_vbslq_u64:
+; CHECK-LABEL: test_vbslq_u64:
 ; CHECK: vbsl q
   %vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
   ret <2 x i64> %vbsl3.i
diff --git a/test/CodeGen/ARM/vceq.ll b/test/CodeGen/ARM/vceq.ll
index 051c349..0a1f2eb 100644
--- a/test/CodeGen/ARM/vceq.ll
+++ b/test/CodeGen/ARM/vceq.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vceqi8:
+;CHECK-LABEL: vceqi8:
 ;CHECK: vceq.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -11,7 +11,7 @@ define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vceqi16:
+;CHECK-LABEL: vceqi16:
 ;CHECK: vceq.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -21,7 +21,7 @@ define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vceqi32:
+;CHECK-LABEL: vceqi32:
 ;CHECK: vceq.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -31,7 +31,7 @@ define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vceqf32:
+;CHECK-LABEL: vceqf32:
 ;CHECK: vceq.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -41,7 +41,7 @@ define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vceqQi8:
+;CHECK-LABEL: vceqQi8:
 ;CHECK: vceq.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -51,7 +51,7 @@ define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vceqQi16:
+;CHECK-LABEL: vceqQi16:
 ;CHECK: vceq.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -61,7 +61,7 @@ define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vceqQi32:
+;CHECK-LABEL: vceqQi32:
 ;CHECK: vceq.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -71,7 +71,7 @@ define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vceqQf32:
+;CHECK-LABEL: vceqQf32:
 ;CHECK: vceq.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -81,7 +81,7 @@ define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 }
 
 define <8 x i8> @vceqi8Z(<8 x i8>* %A) nounwind {
-;CHECK: vceqi8Z:
+;CHECK-LABEL: vceqi8Z:
 ;CHECK-NOT: vmov
 ;CHECK-NOT: vmvn
 ;CHECK: vceq.i8
diff --git a/test/CodeGen/ARM/vcge.ll b/test/CodeGen/ARM/vcge.ll
index bf5f0b9..81a59db 100644
--- a/test/CodeGen/ARM/vcge.ll
+++ b/test/CodeGen/ARM/vcge.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcges8:
+;CHECK-LABEL: vcges8:
 ;CHECK: vcge.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -11,7 +11,7 @@ define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcges16:
+;CHECK-LABEL: vcges16:
 ;CHECK: vcge.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -21,7 +21,7 @@ define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcges32:
+;CHECK-LABEL: vcges32:
 ;CHECK: vcge.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -31,7 +31,7 @@ define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcgeu8:
+;CHECK-LABEL: vcgeu8:
 ;CHECK: vcge.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -41,7 +41,7 @@ define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcgeu16:
+;CHECK-LABEL: vcgeu16:
 ;CHECK: vcge.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -51,7 +51,7 @@ define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcgeu32:
+;CHECK-LABEL: vcgeu32:
 ;CHECK: vcge.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -61,7 +61,7 @@ define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcgef32:
+;CHECK-LABEL: vcgef32:
 ;CHECK: vcge.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -71,7 +71,7 @@ define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgeQs8:
+;CHECK-LABEL: vcgeQs8:
 ;CHECK: vcge.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -81,7 +81,7 @@ define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgeQs16:
+;CHECK-LABEL: vcgeQs16:
 ;CHECK: vcge.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgeQs32:
+;CHECK-LABEL: vcgeQs32:
 ;CHECK: vcge.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -101,7 +101,7 @@ define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgeQu8:
+;CHECK-LABEL: vcgeQu8:
 ;CHECK: vcge.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -111,7 +111,7 @@ define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgeQu16:
+;CHECK-LABEL: vcgeQu16:
 ;CHECK: vcge.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -121,7 +121,7 @@ define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgeQu32:
+;CHECK-LABEL: vcgeQu32:
 ;CHECK: vcge.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -131,7 +131,7 @@ define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vcgeQf32:
+;CHECK-LABEL: vcgeQf32:
 ;CHECK: vcge.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -141,7 +141,7 @@ define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 }
 
 define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vacgef32:
+;CHECK-LABEL: vacgef32:
 ;CHECK: vacge.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -150,7 +150,7 @@ define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vacgeQf32:
+;CHECK-LABEL: vacgeQf32:
 ;CHECK: vacge.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -162,7 +162,7 @@ declare <2 x i32> @llvm.arm.neon.vacged(<2 x float>, <2 x float>) nounwind readn
 declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>) nounwind readnone
 
 define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind {
-;CHECK: vcgei8Z:
+;CHECK-LABEL: vcgei8Z:
 ;CHECK-NOT: vmov
 ;CHECK-NOT: vmvn
 ;CHECK: vcge.s8
@@ -173,7 +173,7 @@ define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind {
 }
 
 define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind {
-;CHECK: vclei8Z:
+;CHECK-LABEL: vclei8Z:
 ;CHECK-NOT: vmov
 ;CHECK-NOT: vmvn
 ;CHECK: vcle.s8
@@ -187,7 +187,7 @@ define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind {
 ; Floating-point comparisons against zero produce results with integer
 ; elements, not floating-point elements.
 define void @test_vclez_fp() nounwind optsize {
-;CHECK: test_vclez_fp
+;CHECK-LABEL: test_vclez_fp:
 ;CHECK: vcle.f32
 entry:
   %0 = fcmp ole <4 x float> undef, zeroinitializer
diff --git a/test/CodeGen/ARM/vcgt.ll b/test/CodeGen/ARM/vcgt.ll
index 2243bac..056866f 100644
--- a/test/CodeGen/ARM/vcgt.ll
+++ b/test/CodeGen/ARM/vcgt.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
 
 define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcgts8:
+;CHECK-LABEL: vcgts8:
 ;CHECK: vcgt.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcgts16:
+;CHECK-LABEL: vcgts16:
 ;CHECK: vcgt.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -22,7 +22,7 @@ define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcgts32:
+;CHECK-LABEL: vcgts32:
 ;CHECK: vcgt.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -32,7 +32,7 @@ define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcgtu8:
+;CHECK-LABEL: vcgtu8:
 ;CHECK: vcgt.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -42,7 +42,7 @@ define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcgtu16:
+;CHECK-LABEL: vcgtu16:
 ;CHECK: vcgt.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -52,7 +52,7 @@ define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcgtu32:
+;CHECK-LABEL: vcgtu32:
 ;CHECK: vcgt.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -62,7 +62,7 @@ define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcgtf32:
+;CHECK-LABEL: vcgtf32:
 ;CHECK: vcgt.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -72,7 +72,7 @@ define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgtQs8:
+;CHECK-LABEL: vcgtQs8:
 ;CHECK: vcgt.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgtQs16:
+;CHECK-LABEL: vcgtQs16:
 ;CHECK: vcgt.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -92,7 +92,7 @@ define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgtQs32:
+;CHECK-LABEL: vcgtQs32:
 ;CHECK: vcgt.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -102,7 +102,7 @@ define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgtQu8:
+;CHECK-LABEL: vcgtQu8:
 ;CHECK: vcgt.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -112,7 +112,7 @@ define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgtQu16:
+;CHECK-LABEL: vcgtQu16:
 ;CHECK: vcgt.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -122,7 +122,7 @@ define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgtQu32:
+;CHECK-LABEL: vcgtQu32:
 ;CHECK: vcgt.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -132,7 +132,7 @@ define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vcgtQf32:
+;CHECK-LABEL: vcgtQf32:
 ;CHECK: vcgt.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -142,7 +142,7 @@ define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 }
 
 define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vacgtf32:
+;CHECK-LABEL: vacgtf32:
 ;CHECK: vacgt.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -151,7 +151,7 @@ define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vacgtQf32:
+;CHECK-LABEL: vacgtQf32:
 ;CHECK: vacgt.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -161,7 +161,7 @@ define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 
 ; rdar://7923010
 define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vcgt_zext:
+;CHECK-LABEL: vcgt_zext:
 ;CHECK: vmov.i32 [[Q0:q[0-9]+]], #0x1
 ;CHECK: vcgt.f32 [[Q1:q[0-9]+]]
 ;CHECK: vand [[Q2:q[0-9]+]], [[Q1]], [[Q0]]
@@ -176,7 +176,7 @@ declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>) nounwind readn
 declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone
 
 define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind {
-;CHECK: vcgti8Z:
+;CHECK-LABEL: vcgti8Z:
 ;CHECK-NOT: vmov
 ;CHECK-NOT: vmvn
 ;CHECK: vcgt.s8
@@ -187,7 +187,7 @@ define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind {
 }
 
 define <8 x i8> @vclti8Z(<8 x i8>* %A) nounwind {
-;CHECK: vclti8Z:
+;CHECK-LABEL: vclti8Z:
 ;CHECK-NOT: vmov
 ;CHECK-NOT: vmvn
 ;CHECK: vclt.s8
diff --git a/test/CodeGen/ARM/vcnt.ll b/test/CodeGen/ARM/vcnt.ll
index 9f55c24..0b53979 100644
--- a/test/CodeGen/ARM/vcnt.ll
+++ b/test/CodeGen/ARM/vcnt.ll
@@ -2,7 +2,7 @@
 ; NB: this tests vcnt, vclz, and vcls
 
 define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
-;CHECK: vcnt8:
+;CHECK-LABEL: vcnt8:
 ;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)
@@ -10,7 +10,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
 }
 
 define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
-;CHECK: vcntQ8:
+;CHECK-LABEL: vcntQ8:
 ;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)
@@ -21,7 +21,7 @@ declare <8 x i8>  @llvm.ctpop.v8i8(<8 x i8>) nounwind readnone
 declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone
 
 define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
-;CHECK: vclz8:
+;CHECK-LABEL: vclz8:
 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
@@ -29,7 +29,7 @@ define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
-;CHECK: vclz16:
+;CHECK-LABEL: vclz16:
 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
@@ -37,7 +37,7 @@ define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
-;CHECK: vclz32:
+;CHECK-LABEL: vclz32:
 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
@@ -45,7 +45,7 @@ define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
 }
 
 define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
-;CHECK: vclzQ8:
+;CHECK-LABEL: vclzQ8:
 ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
@@ -53,7 +53,7 @@ define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
-;CHECK: vclzQ16:
+;CHECK-LABEL: vclzQ16:
 ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
@@ -61,7 +61,7 @@ define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
-;CHECK: vclzQ32:
+;CHECK-LABEL: vclzQ32:
 ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
@@ -77,7 +77,7 @@ declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
 declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
 
 define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
-;CHECK: vclss8:
+;CHECK-LABEL: vclss8:
 ;CHECK: vcls.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
@@ -85,7 +85,7 @@ define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
-;CHECK: vclss16:
+;CHECK-LABEL: vclss16:
 ;CHECK: vcls.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
@@ -93,7 +93,7 @@ define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
-;CHECK: vclss32:
+;CHECK-LABEL: vclss32:
 ;CHECK: vcls.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
@@ -101,7 +101,7 @@ define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
 }
 
 define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vclsQs8:
+;CHECK-LABEL: vclsQs8:
 ;CHECK: vcls.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
@@ -109,7 +109,7 @@ define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vclsQs16:
+;CHECK-LABEL: vclsQs16:
 ;CHECK: vcls.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
@@ -117,7 +117,7 @@ define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vclsQs32:
+;CHECK-LABEL: vclsQs32:
 ;CHECK: vcls.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
diff --git a/test/CodeGen/ARM/vcvt-cost.ll b/test/CodeGen/ARM/vcvt-cost.ll
index 0d45c40..5e56a5b 100644
--- a/test/CodeGen/ARM/vcvt-cost.ll
+++ b/test/CodeGen/ARM/vcvt-cost.ll
@@ -4,7 +4,7 @@
 ; RUN: opt < %s  -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST
 %T0_5 = type <8 x i8>
 %T1_5 = type <8 x i32>
-; CHECK: func_cvt5:
+; CHECK-LABEL: func_cvt5:
 define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
 ; CHECK: vmovl.s8
 ; CHECK: vmovl.s16
@@ -20,7 +20,7 @@ define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
 ;; is improved the cost needs to change.
 %TA0_5 = type <8 x i8>
 %TA1_5 = type <8 x i32>
-; CHECK: func_cvt1:
+; CHECK-LABEL: func_cvt1:
 define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) {
 ; CHECK: vmovl.u8
 ; CHECK: vmovl.u16
@@ -35,7 +35,7 @@ define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) {
 
 %T0_51 = type <8 x i32>
 %T1_51 = type <8 x i8>
-; CHECK: func_cvt51:
+; CHECK-LABEL: func_cvt51:
 define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) {
 ; CHECK: vmovn.i32
 ; CHECK: vmovn.i32
@@ -50,7 +50,7 @@ define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) {
 
 %TT0_5 = type <16 x i8>
 %TT1_5 = type <16 x i32>
-; CHECK: func_cvt52:
+; CHECK-LABEL: func_cvt52:
 define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
 ; CHECK: vmovl.s16
 ; CHECK: vmovl.s16
@@ -67,7 +67,7 @@ define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
 ;; is improved the cost needs to change.
 %TTA0_5 = type <16 x i8>
 %TTA1_5 = type <16 x i32>
-; CHECK: func_cvt12:
+; CHECK-LABEL: func_cvt12:
 define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) {
 ; CHECK: vmovl.u16
 ; CHECK: vmovl.u16
@@ -83,7 +83,7 @@ define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) {
 
 %TT0_51 = type <16 x i32>
 %TT1_51 = type <16 x i8>
-; CHECK: func_cvt512:
+; CHECK-LABEL: func_cvt512:
 define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) {
 ; CHECK: vmovn.i32
 ; CHECK: vmovn.i32
@@ -99,7 +99,7 @@ define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) {
   ret void
 }
 
-; CHECK: sext_v4i16_v4i64:
+; CHECK-LABEL: sext_v4i16_v4i64:
 define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
 ; CHECK: vmovl.s32
 ; CHECK: vmovl.s32
@@ -111,7 +111,7 @@ define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
   ret void
 }
 
-; CHECK: zext_v4i16_v4i64:
+; CHECK-LABEL: zext_v4i16_v4i64:
 define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
 ; CHECK: vmovl.u32
 ; CHECK: vmovl.u32
@@ -123,7 +123,7 @@ define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
   ret void
 }
 
-; CHECK: sext_v8i16_v8i64:
+; CHECK-LABEL: sext_v8i16_v8i64:
 define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
 ; CHECK: vmovl.s32
 ; CHECK: vmovl.s32
@@ -137,7 +137,7 @@ define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
   ret void
 }
 
-; CHECK: zext_v8i16_v8i64:
+; CHECK-LABEL: zext_v8i16_v8i64:
 define void @zext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
 ; CHECK: vmovl.u32
 ; CHECK: vmovl.u32
diff --git a/test/CodeGen/ARM/vcvt-v8.ll b/test/CodeGen/ARM/vcvt-v8.ll
new file mode 100644
index 0000000..c449009
--- /dev/null
+++ b/test/CodeGen/ARM/vcvt-v8.ll
@@ -0,0 +1,145 @@
+; RUN: llc < %s -mtriple=armv8 -mattr=+neon | FileCheck %s
+define <4 x i32> @vcvtasq(<4 x float>* %A) {
+; CHECK: vcvtasq
+; CHECK: vcvta.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
+  %tmp1 = load <4 x float>* %A
+  %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float> %tmp1)
+  ret <4 x i32> %tmp2
+}
+
+define <2 x i32> @vcvtasd(<2 x float>* %A) {
+; CHECK: vcvtasd
+; CHECK: vcvta.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
+  %tmp1 = load <2 x float>* %A
+  %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float> %tmp1)
+  ret <2 x i32> %tmp2
+}
+
+define <4 x i32> @vcvtnsq(<4 x float>* %A) {
+; CHECK: vcvtnsq
+; CHECK: vcvtn.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
+  %tmp1 = load <4 x float>* %A
+  %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float> %tmp1)
+  ret <4 x i32> %tmp2
+}
+
+define <2 x i32> @vcvtnsd(<2 x float>* %A) {
+; CHECK: vcvtnsd
+; CHECK: vcvtn.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
+  %tmp1 = load <2 x float>* %A
+  %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float> %tmp1)
+  ret <2 x i32> %tmp2
+}
+
+define <4 x i32> @vcvtpsq(<4 x float>* %A) {
+; CHECK: vcvtpsq
+; CHECK: vcvtp.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
+  %tmp1 = load <4 x float>* %A
+  %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float> %tmp1)
+  ret <4 x i32> %tmp2
+}
+
+define <2 x i32> @vcvtpsd(<2 x float>* %A) {
+; CHECK: vcvtpsd
+; CHECK: vcvtp.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
+  %tmp1 = load <2 x float>* %A
+  %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float> %tmp1)
+  ret <2 x i32> %tmp2
+}
+
+define <4 x i32> @vcvtmsq(<4 x float>* %A) {
+; CHECK: vcvtmsq
+; CHECK: vcvtm.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}
+  %tmp1 = load <4 x float>* %A
+  %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float> %tmp1)
+  ret <4 x i32> %tmp2
+}
+
+define <2 x i32> @vcvtmsd(<2 x float>* %A) {
+; CHECK: vcvtmsd
+; CHECK: vcvtm.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
+  %tmp1 = load <2 x float>* %A
+  %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float> %tmp1)
+  ret <2 x i32> %tmp2
+}
+
+define <4 x i32> @vcvtauq(<4 x float>* %A) {
+; CHECK: vcvtauq
+; CHECK: vcvta.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
+  %tmp1 = load <4 x float>* %A
+  %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float> %tmp1)
+  ret <4 x i32> %tmp2
+}
+
+define <2 x i32> @vcvtaud(<2 x float>* %A) {
+; CHECK: vcvtaud
+; CHECK: vcvta.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
+  %tmp1 = load <2 x float>* %A
+  %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float> %tmp1)
+  ret <2 x i32> %tmp2
+}
+
+define <4 x i32> @vcvtnuq(<4 x float>* %A) {
+; CHECK: vcvtnuq
+; CHECK: vcvtn.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
+  %tmp1 = load <4 x float>* %A
+  %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float> %tmp1)
+  ret <4 x i32> %tmp2
+}
+
+define <2 x i32> @vcvtnud(<2 x float>* %A) {
+; CHECK: vcvtnud
+; CHECK: vcvtn.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
+  %tmp1 = load <2 x float>* %A
+  %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float> %tmp1)
+  ret <2 x i32> %tmp2
+}
+
+define <4 x i32> @vcvtpuq(<4 x float>* %A) {
+; CHECK: vcvtpuq
+; CHECK: vcvtp.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
+  %tmp1 = load <4 x float>* %A
+  %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float> %tmp1)
+  ret <4 x i32> %tmp2
+}
+
+define <2 x i32> @vcvtpud(<2 x float>* %A) {
+; CHECK: vcvtpud
+; CHECK: vcvtp.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
+  %tmp1 = load <2 x float>* %A
+  %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float> %tmp1)
+  ret <2 x i32> %tmp2
+}
+
+define <4 x i32> @vcvtmuq(<4 x float>* %A) {
+; CHECK: vcvtmuq
+; CHECK: vcvtm.u32.f32 q{{[0-9]+}}, q{{[0-9]+}}
+  %tmp1 = load <4 x float>* %A
+  %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float> %tmp1)
+  ret <4 x i32> %tmp2
+}
+
+define <2 x i32> @vcvtmud(<2 x float>* %A) {
+; CHECK: vcvtmud
+; CHECK: vcvtm.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}
+  %tmp1 = load <2 x float>* %A
+  %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtmu.v2i32.v2f32(<2 x float> %tmp1)
+  ret <2 x i32> %tmp2
+}
+
+declare <4 x i32> @llvm.arm.neon.vcvtas.v4i32.v4f32(<4 x float>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vcvtas.v2i32.v2f32(<2 x float>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vcvtns.v4i32.v4f32(<4 x float>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vcvtns.v2i32.v2f32(<2 x float>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vcvtps.v4i32.v4f32(<4 x float>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vcvtps.v2i32.v2f32(<2 x float>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vcvtms.v4i32.v4f32(<4 x float>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vcvtms.v2i32.v2f32(<2 x float>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vcvtau.v4i32.v4f32(<4 x float>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vcvtau.v2i32.v2f32(<2 x float>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vcvtnu.v4i32.v4f32(<4 x float>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vcvtnu.v2i32.v2f32(<2 x float>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vcvtpu.v4i32.v4f32(<4 x float>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vcvtpu.v2i32.v2f32(<2 x float>) nounwind readnone
+declare <4 x i32> @llvm.arm.neon.vcvtmu.v4i32.v4f32(<4 x float>) nounwind readnone
+declare <2 x i32> @llvm.arm.neon.vcvtmu.v2i32.v2f32(<2 x float>) nounwind readnone
diff --git a/test/CodeGen/ARM/vcvt.ll b/test/CodeGen/ARM/vcvt.ll
index c078f49..4f17dc5 100644
--- a/test/CodeGen/ARM/vcvt.ll
+++ b/test/CodeGen/ARM/vcvt.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon,+fp16 | FileCheck %s
 
 define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_f32tos32:
+;CHECK-LABEL: vcvt_f32tos32:
 ;CHECK: vcvt.s32.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = fptosi <2 x float> %tmp1 to <2 x i32>
@@ -9,7 +9,7 @@ define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
 }
 
 define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_f32tou32:
+;CHECK-LABEL: vcvt_f32tou32:
 ;CHECK: vcvt.u32.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = fptoui <2 x float> %tmp1 to <2 x i32>
@@ -17,7 +17,7 @@ define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
 }
 
 define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_s32tof32:
+;CHECK-LABEL: vcvt_s32tof32:
 ;CHECK: vcvt.f32.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = sitofp <2 x i32> %tmp1 to <2 x float>
@@ -25,7 +25,7 @@ define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
 }
 
 define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_u32tof32:
+;CHECK-LABEL: vcvt_u32tof32:
 ;CHECK: vcvt.f32.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = uitofp <2 x i32> %tmp1 to <2 x float>
@@ -33,7 +33,7 @@ define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
 }
 
 define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_f32tos32:
+;CHECK-LABEL: vcvtQ_f32tos32:
 ;CHECK: vcvt.s32.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = fptosi <4 x float> %tmp1 to <4 x i32>
@@ -41,7 +41,7 @@ define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
 }
 
 define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_f32tou32:
+;CHECK-LABEL: vcvtQ_f32tou32:
 ;CHECK: vcvt.u32.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = fptoui <4 x float> %tmp1 to <4 x i32>
@@ -49,7 +49,7 @@ define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
 }
 
 define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_s32tof32:
+;CHECK-LABEL: vcvtQ_s32tof32:
 ;CHECK: vcvt.f32.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = sitofp <4 x i32> %tmp1 to <4 x float>
@@ -57,7 +57,7 @@ define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
 }
 
 define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_u32tof32:
+;CHECK-LABEL: vcvtQ_u32tof32:
 ;CHECK: vcvt.f32.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = uitofp <4 x i32> %tmp1 to <4 x float>
@@ -65,7 +65,7 @@ define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_n_f32tos32:
+;CHECK-LABEL: vcvt_n_f32tos32:
 ;CHECK: vcvt.s32.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
@@ -73,7 +73,7 @@ define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
 }
 
 define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_n_f32tou32:
+;CHECK-LABEL: vcvt_n_f32tou32:
 ;CHECK: vcvt.u32.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
@@ -81,7 +81,7 @@ define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
 }
 
 define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_n_s32tof32:
+;CHECK-LABEL: vcvt_n_s32tof32:
 ;CHECK: vcvt.f32.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
@@ -89,7 +89,7 @@ define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
 }
 
 define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_n_u32tof32:
+;CHECK-LABEL: vcvt_n_u32tof32:
 ;CHECK: vcvt.f32.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
@@ -102,7 +102,7 @@ declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwi
 declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
 
 define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_n_f32tos32:
+;CHECK-LABEL: vcvtQ_n_f32tos32:
 ;CHECK: vcvt.s32.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
@@ -110,7 +110,7 @@ define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
 }
 
 define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_n_f32tou32:
+;CHECK-LABEL: vcvtQ_n_f32tou32:
 ;CHECK: vcvt.u32.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
@@ -118,7 +118,7 @@ define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
 }
 
 define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_n_s32tof32:
+;CHECK-LABEL: vcvtQ_n_s32tof32:
 ;CHECK: vcvt.f32.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
@@ -126,7 +126,7 @@ define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
 }
 
 define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_n_u32tof32:
+;CHECK-LABEL: vcvtQ_n_u32tof32:
 ;CHECK: vcvt.f32.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
@@ -139,7 +139,7 @@ declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwi
 declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
 
 define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind {
-;CHECK: vcvt_f16tof32:
+;CHECK-LABEL: vcvt_f16tof32:
 ;CHECK: vcvt.f32.f16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %tmp1)
@@ -147,7 +147,7 @@ define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind {
-;CHECK: vcvt_f32tof16:
+;CHECK-LABEL: vcvt_f32tof16:
 ;CHECK: vcvt.f16.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %tmp1)
@@ -156,3 +156,44 @@ define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind {
 
 declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) nounwind readnone
 declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone
+
+
+define <4 x i16> @fix_float_to_i16(<4 x float> %in) {
+; CHECK-LABEL: fix_float_to_i16:
+; CHECK: vcvt.u32.f32 [[TMP:q[0-9]+]], {{q[0-9]+}}, #1
+; CHECK: vmovn.i32 {{d[0-9]+}}, [[TMP]]
+
+  %scale = fmul <4 x float> %in, <float 2.0, float 2.0, float 2.0, float 2.0>
+  %conv = fptoui <4 x float> %scale to <4 x i16>
+  ret <4 x i16> %conv
+}
+
+define <2 x i64> @fix_float_to_i64(<2 x float> %in) {
+; CHECK-LABEL: fix_float_to_i64:
+; CHECK: bl
+; CHECK: bl
+
+  %scale = fmul <2 x float> %in, <float 2.0, float 2.0>
+  %conv = fptoui <2 x float> %scale to <2 x i64>
+  ret <2 x i64> %conv
+}
+
+define <4 x i16> @fix_double_to_i16(<4 x double> %in) {
+; CHECK-LABEL: fix_double_to_i16:
+; CHECK: vcvt.s32.f64
+; CHECK: vcvt.s32.f64
+
+  %scale = fmul <4 x double> %in, <double 2.0, double 2.0, double 2.0, double 2.0>
+  %conv = fptoui <4 x double> %scale to <4 x i16>
+  ret <4 x i16> %conv
+}
+
+define <2 x i64> @fix_double_to_i64(<2 x double> %in) {
+; CHECK-LABEL: fix_double_to_i64:
+; CHECK: bl
+; CHECK: bl
+  %scale = fmul <2 x double> %in, <double 2.0, double 2.0>
+  %conv = fptoui <2 x double> %scale to <2 x i64>
+  ret <2 x i64> %conv
+}
+
diff --git a/test/CodeGen/ARM/vdiv_combine.ll b/test/CodeGen/ARM/vdiv_combine.ll
index e6f1338..96807f7 100644
--- a/test/CodeGen/ARM/vdiv_combine.ll
+++ b/test/CodeGen/ARM/vdiv_combine.ll
@@ -95,3 +95,44 @@ entry:
 }
 
 declare void @foo_float32x4_t(<4 x float>)
+
+define <4 x float> @fix_unsigned_i16_to_float(<4 x i16> %in) {
+; CHECK-LABEL: fix_unsigned_i16_to_float:
+; CHECK: vmovl.u16 [[TMP:q[0-9]+]], {{d[0-9]+}}
+; CHECK: vcvt.f32.u32 {{q[0-9]+}}, [[TMP]], #1
+
+    %conv = uitofp <4 x i16> %in to <4 x float>
+    %shift = fdiv <4 x float> %conv, <float 2.0, float 2.0, float 2.0, float 2.0>
+    ret <4 x float> %shift
+}
+
+define <4 x float> @fix_signed_i16_to_float(<4 x i16> %in) {
+; CHECK-LABEL: fix_signed_i16_to_float:
+; CHECK: vmovl.s16 [[TMP:q[0-9]+]], {{d[0-9]+}}
+; CHECK: vcvt.f32.s32 {{q[0-9]+}}, [[TMP]], #1
+
+    %conv = sitofp <4 x i16> %in to <4 x float>
+    %shift = fdiv <4 x float> %conv, <float 2.0, float 2.0, float 2.0, float 2.0>
+    ret <4 x float> %shift
+}
+
+define <2 x float> @fix_i64_to_float(<2 x i64> %in) {
+; CHECK-LABEL: fix_i64_to_float:
+; CHECK: bl
+; CHECK: bl
+
+    %conv = uitofp <2 x i64> %in to <2 x float>
+    %shift = fdiv <2 x float> %conv, <float 2.0, float 2.0>
+    ret <2 x float> %shift
+}
+
+define <2 x double> @fix_i64_to_double(<2 x i64> %in) {
+; CHECK-LABEL: fix_i64_to_double:
+; CHECK: bl
+; CHECK: bl
+
+    %conv = uitofp <2 x i64> %in to <2 x double>
+    %shift = fdiv <2 x double> %conv, <double 2.0, double 2.0>
+    ret <2 x double> %shift
+}
+
diff --git a/test/CodeGen/ARM/vdup.ll b/test/CodeGen/ARM/vdup.ll
index 2cf94d6..b24be26 100644
--- a/test/CodeGen/ARM/vdup.ll
+++ b/test/CodeGen/ARM/vdup.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @v_dup8(i8 %A) nounwind {
-;CHECK: v_dup8:
+;CHECK-LABEL: v_dup8:
 ;CHECK: vdup.8
 	%tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
 	%tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1
@@ -15,7 +15,7 @@ define <8 x i8> @v_dup8(i8 %A) nounwind {
 }
 
 define <4 x i16> @v_dup16(i16 %A) nounwind {
-;CHECK: v_dup16:
+;CHECK-LABEL: v_dup16:
 ;CHECK: vdup.16
 	%tmp1 = insertelement <4 x i16> zeroinitializer, i16 %A, i32 0
 	%tmp2 = insertelement <4 x i16> %tmp1, i16 %A, i32 1
@@ -25,7 +25,7 @@ define <4 x i16> @v_dup16(i16 %A) nounwind {
 }
 
 define <2 x i32> @v_dup32(i32 %A) nounwind {
-;CHECK: v_dup32:
+;CHECK-LABEL: v_dup32:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <2 x i32> zeroinitializer, i32 %A, i32 0
 	%tmp2 = insertelement <2 x i32> %tmp1, i32 %A, i32 1
@@ -33,7 +33,7 @@ define <2 x i32> @v_dup32(i32 %A) nounwind {
 }
 
 define <2 x float> @v_dupfloat(float %A) nounwind {
-;CHECK: v_dupfloat:
+;CHECK-LABEL: v_dupfloat:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <2 x float> zeroinitializer, float %A, i32 0
 	%tmp2 = insertelement <2 x float> %tmp1, float %A, i32 1
@@ -41,7 +41,7 @@ define <2 x float> @v_dupfloat(float %A) nounwind {
 }
 
 define <16 x i8> @v_dupQ8(i8 %A) nounwind {
-;CHECK: v_dupQ8:
+;CHECK-LABEL: v_dupQ8:
 ;CHECK: vdup.8
 	%tmp1 = insertelement <16 x i8> zeroinitializer, i8 %A, i32 0
 	%tmp2 = insertelement <16 x i8> %tmp1, i8 %A, i32 1
@@ -63,7 +63,7 @@ define <16 x i8> @v_dupQ8(i8 %A) nounwind {
 }
 
 define <8 x i16> @v_dupQ16(i16 %A) nounwind {
-;CHECK: v_dupQ16:
+;CHECK-LABEL: v_dupQ16:
 ;CHECK: vdup.16
 	%tmp1 = insertelement <8 x i16> zeroinitializer, i16 %A, i32 0
 	%tmp2 = insertelement <8 x i16> %tmp1, i16 %A, i32 1
@@ -77,7 +77,7 @@ define <8 x i16> @v_dupQ16(i16 %A) nounwind {
 }
 
 define <4 x i32> @v_dupQ32(i32 %A) nounwind {
-;CHECK: v_dupQ32:
+;CHECK-LABEL: v_dupQ32:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %A, i32 0
 	%tmp2 = insertelement <4 x i32> %tmp1, i32 %A, i32 1
@@ -87,7 +87,7 @@ define <4 x i32> @v_dupQ32(i32 %A) nounwind {
 }
 
 define <4 x float> @v_dupQfloat(float %A) nounwind {
-;CHECK: v_dupQfloat:
+;CHECK-LABEL: v_dupQfloat:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <4 x float> zeroinitializer, float %A, i32 0
 	%tmp2 = insertelement <4 x float> %tmp1, float %A, i32 1
@@ -99,7 +99,7 @@ define <4 x float> @v_dupQfloat(float %A) nounwind {
 ; Check to make sure it works with shuffles, too.
 
 define <8 x i8> @v_shuffledup8(i8 %A) nounwind {
-;CHECK: v_shuffledup8:
+;CHECK-LABEL: v_shuffledup8:
 ;CHECK: vdup.8
 	%tmp1 = insertelement <8 x i8> undef, i8 %A, i32 0
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
@@ -107,7 +107,7 @@ define <8 x i8> @v_shuffledup8(i8 %A) nounwind {
 }
 
 define <4 x i16> @v_shuffledup16(i16 %A) nounwind {
-;CHECK: v_shuffledup16:
+;CHECK-LABEL: v_shuffledup16:
 ;CHECK: vdup.16
 	%tmp1 = insertelement <4 x i16> undef, i16 %A, i32 0
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
@@ -115,7 +115,7 @@ define <4 x i16> @v_shuffledup16(i16 %A) nounwind {
 }
 
 define <2 x i32> @v_shuffledup32(i32 %A) nounwind {
-;CHECK: v_shuffledup32:
+;CHECK-LABEL: v_shuffledup32:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <2 x i32> undef, i32 %A, i32 0
 	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
@@ -123,7 +123,7 @@ define <2 x i32> @v_shuffledup32(i32 %A) nounwind {
 }
 
 define <2 x float> @v_shuffledupfloat(float %A) nounwind {
-;CHECK: v_shuffledupfloat:
+;CHECK-LABEL: v_shuffledupfloat:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <2 x float> undef, float %A, i32 0
 	%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
@@ -131,7 +131,7 @@ define <2 x float> @v_shuffledupfloat(float %A) nounwind {
 }
 
 define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind {
-;CHECK: v_shuffledupQ8:
+;CHECK-LABEL: v_shuffledupQ8:
 ;CHECK: vdup.8
 	%tmp1 = insertelement <16 x i8> undef, i8 %A, i32 0
 	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> zeroinitializer
@@ -139,7 +139,7 @@ define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind {
 }
 
 define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind {
-;CHECK: v_shuffledupQ16:
+;CHECK-LABEL: v_shuffledupQ16:
 ;CHECK: vdup.16
 	%tmp1 = insertelement <8 x i16> undef, i16 %A, i32 0
 	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> zeroinitializer
@@ -147,7 +147,7 @@ define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind {
 }
 
 define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind {
-;CHECK: v_shuffledupQ32:
+;CHECK-LABEL: v_shuffledupQ32:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <4 x i32> undef, i32 %A, i32 0
 	%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> zeroinitializer
@@ -155,7 +155,7 @@ define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind {
 }
 
 define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
-;CHECK: v_shuffledupQfloat:
+;CHECK-LABEL: v_shuffledupQfloat:
 ;CHECK: vdup.32
 	%tmp1 = insertelement <4 x float> undef, float %A, i32 0
 	%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
@@ -163,7 +163,7 @@ define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
 }
 
 define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
-;CHECK: vduplane8:
+;CHECK-LABEL: vduplane8:
 ;CHECK: vdup.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
@@ -171,7 +171,7 @@ define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
-;CHECK: vduplane16:
+;CHECK-LABEL: vduplane16:
 ;CHECK: vdup.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
@@ -179,7 +179,7 @@ define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
-;CHECK: vduplane32:
+;CHECK-LABEL: vduplane32:
 ;CHECK: vdup.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
@@ -187,7 +187,7 @@ define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
 }
 
 define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
-;CHECK: vduplanefloat:
+;CHECK-LABEL: vduplanefloat:
 ;CHECK: vdup.32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 >
@@ -195,7 +195,7 @@ define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
 }
 
 define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
-;CHECK: vduplaneQ8:
+;CHECK-LABEL: vduplaneQ8:
 ;CHECK: vdup.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
@@ -203,7 +203,7 @@ define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
-;CHECK: vduplaneQ16:
+;CHECK-LABEL: vduplaneQ16:
 ;CHECK: vdup.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
@@ -211,7 +211,7 @@ define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
-;CHECK: vduplaneQ32:
+;CHECK-LABEL: vduplaneQ32:
 ;CHECK: vdup.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
@@ -219,7 +219,7 @@ define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
 }
 
 define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
-;CHECK: vduplaneQfloat:
+;CHECK-LABEL: vduplaneQfloat:
 ;CHECK: vdup.32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
@@ -251,7 +251,7 @@ entry:
 }
 
 ; Radar 7373643
-;CHECK: redundantVdup:
+;CHECK-LABEL: redundantVdup:
 ;CHECK: vmov.i8
 ;CHECK-NOT: vdup.8
 ;CHECK: vstr
@@ -263,7 +263,7 @@ define void @redundantVdup(<8 x i8>* %ptr) nounwind {
 }
 
 define <4 x i32> @tdupi(i32 %x, i32 %y) {
-;CHECK: tdupi
+;CHECK-LABEL: tdupi:
 ;CHECK: vdup.32
   %1 = insertelement <4 x i32> undef, i32 %x, i32 0
   %2 = insertelement <4 x i32> %1, i32 %x, i32 1
@@ -273,7 +273,7 @@ define <4 x i32> @tdupi(i32 %x, i32 %y) {
 }
 
 define <4 x float> @tdupf(float %x, float %y) {
-;CHECK: tdupf
+;CHECK-LABEL: tdupf:
 ;CHECK: vdup.32
   %1 = insertelement <4 x float> undef, float %x, i32 0
   %2 = insertelement <4 x float> %1, float %x, i32 1
@@ -285,7 +285,7 @@ define <4 x float> @tdupf(float %x, float %y) {
 ; This test checks that when splatting an element from a vector into another,
 ; the value isn't moved out to GPRs first.
 define <4 x i32> @tduplane(<4 x i32> %invec) {
-;CHECK: tduplane
+;CHECK-LABEL: tduplane:
 ;CHECK-NOT: vmov {{.*}}, d16[1]
 ;CHECK: vdup.32 {{.*}}, d16[1]
   %in = extractelement <4 x i32> %invec, i32 1
@@ -297,7 +297,7 @@ define <4 x i32> @tduplane(<4 x i32> %invec) {
 }
 
 define <2 x float> @check_f32(<4 x float> %v) nounwind {
-;CHECK: check_f32:
+;CHECK-LABEL: check_f32:
 ;CHECK: vdup.32 {{.*}}, d{{..}}[1]
   %x = extractelement <4 x float> %v, i32 3
   %1 = insertelement  <2 x float> undef, float %x, i32 0
@@ -306,7 +306,7 @@ define <2 x float> @check_f32(<4 x float> %v) nounwind {
 }
 
 define <2 x i32> @check_i32(<4 x i32> %v) nounwind {
-;CHECK: check_i32:
+;CHECK-LABEL: check_i32:
 ;CHECK: vdup.32 {{.*}}, d{{..}}[1]
   %x = extractelement <4 x i32> %v, i32 3
   %1 = insertelement  <2 x i32> undef, i32 %x, i32 0
@@ -315,7 +315,7 @@ define <2 x i32> @check_i32(<4 x i32> %v) nounwind {
 }
 
 define <4 x i16> @check_i16(<8 x i16> %v) nounwind {
-;CHECK: check_i16:
+;CHECK-LABEL: check_i16:
 ;CHECK: vdup.16 {{.*}}, d{{..}}[3]
   %x = extractelement <8 x i16> %v, i32 3
   %1 = insertelement  <4 x i16> undef, i16 %x, i32 0
@@ -324,7 +324,7 @@ define <4 x i16> @check_i16(<8 x i16> %v) nounwind {
 }
 
 define <8 x i8> @check_i8(<16 x i8> %v) nounwind {
-;CHECK: check_i8:
+;CHECK-LABEL: check_i8:
 ;CHECK: vdup.8 {{.*}}, d{{..}}[3]
   %x = extractelement <16 x i8> %v, i32 3
   %1 = insertelement  <8  x i8> undef, i8 %x, i32 0
diff --git a/test/CodeGen/ARM/vector-DAGCombine.ll b/test/CodeGen/ARM/vector-DAGCombine.ll
index 42964de..4221c98 100644
--- a/test/CodeGen/ARM/vector-DAGCombine.ll
+++ b/test/CodeGen/ARM/vector-DAGCombine.ll
@@ -160,3 +160,67 @@ define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) {
   store <16 x i8> %v1, <16 x i8>* %storeaddr
   ret void
 }
+
+; <rdar://problem/14170854>.
+; vldr cannot handle unaligned loads.
+; Fall back to vld1.32, which can, instead of using the general purpose loads
+; followed by a costly sequence of instructions to build the vector register.
+; CHECK: t3
+; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}
+; CHECK: vld1.32 {[[REG]][1]}
+; CHECK: vmull.u8 q{{[0-9]+}}, [[REG]], [[REG]]
+define <8 x i16> @t3(i8 zeroext %xf, i8* nocapture %sp0, i8* nocapture %sp1, i32* nocapture %outp) {
+entry:
+  %pix_sp0.0.cast = bitcast i8* %sp0 to i32*
+  %pix_sp0.0.copyload = load i32* %pix_sp0.0.cast, align 1
+  %pix_sp1.0.cast = bitcast i8* %sp1 to i32*
+  %pix_sp1.0.copyload = load i32* %pix_sp1.0.cast, align 1
+  %vecinit = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
+  %vecinit1 = insertelement <2 x i32> %vecinit, i32 %pix_sp1.0.copyload, i32 1
+  %0 = bitcast <2 x i32> %vecinit1 to <8 x i8>
+  %vmull.i = tail call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %0, <8 x i8> %0)
+  ret <8 x i16> %vmull.i
+}
+
+; Function Attrs: nounwind readnone
+declare <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8>, <8 x i8>)
+
+; Check that (insert_vector_elt (load)) => (vector_load).
+; Thus, check that scalar_to_vector do not interfer with that.
+define <8 x i16> @t4(i8* nocapture %sp0) {
+; CHECK: t4
+; CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r0]
+entry:
+  %pix_sp0.0.cast = bitcast i8* %sp0 to i32*
+  %pix_sp0.0.copyload = load i32* %pix_sp0.0.cast, align 1
+  %vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
+  %0 = bitcast <2 x i32> %vec to <8 x i8>
+  %vmull.i = tail call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %0, <8 x i8> %0)
+  ret <8 x i16> %vmull.i
+}
+
+; Make sure vector load is used for all three loads.
+; Lowering to build vector was breaking the single use property of the load of
+;  %pix_sp0.0.copyload.
+; CHECK: t5
+; CHECK: vld1.32 {[[REG1:d[0-9]+]][1]}, [r0]
+; CHECK: vorr [[REG2:d[0-9]+]], [[REG1]], [[REG1]]
+; CHECK: vld1.32 {[[REG1]][0]}, [r1]
+; CHECK: vld1.32 {[[REG2]][0]}, [r2]
+; CHECK: vmull.u8 q{{[0-9]+}}, [[REG1]], [[REG2]]
+define <8 x i16> @t5(i8* nocapture %sp0, i8* nocapture %sp1, i8* nocapture %sp2) {
+entry:
+  %pix_sp0.0.cast = bitcast i8* %sp0 to i32*
+  %pix_sp0.0.copyload = load i32* %pix_sp0.0.cast, align 1
+  %pix_sp1.0.cast = bitcast i8* %sp1 to i32*
+  %pix_sp1.0.copyload = load i32* %pix_sp1.0.cast, align 1
+  %pix_sp2.0.cast = bitcast i8* %sp2 to i32*
+  %pix_sp2.0.copyload = load i32* %pix_sp2.0.cast, align 1
+  %vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 1
+  %vecinit1 = insertelement <2 x i32> %vec, i32 %pix_sp1.0.copyload, i32 0
+  %vecinit2 = insertelement <2 x i32> %vec, i32 %pix_sp2.0.copyload, i32 0
+  %0 = bitcast <2 x i32> %vecinit1 to <8 x i8>
+  %1 = bitcast <2 x i32> %vecinit2 to <8 x i8>
+  %vmull.i = tail call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %0, <8 x i8> %1)
+  ret <8 x i16> %vmull.i
+}
diff --git a/test/CodeGen/ARM/vector-extend-narrow.ll b/test/CodeGen/ARM/vector-extend-narrow.ll
index 22af797..f321896 100644
--- a/test/CodeGen/ARM/vector-extend-narrow.ll
+++ b/test/CodeGen/ARM/vector-extend-narrow.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
 
-; CHECK: f:
+; CHECK-LABEL: f:
 define float @f(<4 x i16>* nocapture %in) {
   ; CHECK: vldr
   ; CHECK: vmovl.u16
@@ -18,7 +18,7 @@ define float @f(<4 x i16>* nocapture %in) {
   ret float %7
 }
 
-; CHECK: g:
+; CHECK-LABEL: g:
 define float @g(<4 x i8>* nocapture %in) {
 ; Note: vld1 here is reasonably important. Mixing VFP and NEON
 ; instructions is bad on some cores
@@ -39,7 +39,7 @@ define float @g(<4 x i8>* nocapture %in) {
   ret float %7
 }
 
-; CHECK: h:
+; CHECK-LABEL: h:
 define <4 x i8> @h(<4 x float> %v) {
   ; CHECK: vcvt.{{[us]}}32.f32
   ; CHECK: vmovn.i32
@@ -47,7 +47,7 @@ define <4 x i8> @h(<4 x float> %v) {
   ret <4 x i8> %1
 }
 
-; CHECK: i:
+; CHECK-LABEL: i:
 define <4 x i8> @i(<4 x i8>* %x) {
 ; Note: vld1 here is reasonably important. Mixing VFP and NEON
 ; instructions is bad on some cores
@@ -62,7 +62,7 @@ define <4 x i8> @i(<4 x i8>* %x) {
   %2 = sdiv <4 x i8> zeroinitializer, %1
   ret <4 x i8> %2
 }
-; CHECK: j:
+; CHECK-LABEL: j:
 define <4 x i32> @j(<4 x i8>* %in) nounwind {
   ; CHECK: vld1
   ; CHECK: vmovl.u8
diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll
index f404eb8..5555a47 100644
--- a/test/CodeGen/ARM/vext.ll
+++ b/test/CodeGen/ARM/vext.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: test_vextd:
+;CHECK-LABEL: test_vextd:
 ;CHECK: vext
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: test_vextRd:
+;CHECK-LABEL: test_vextRd:
 ;CHECK: vext
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -19,7 +19,7 @@ define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: test_vextq:
+;CHECK-LABEL: test_vextq:
 ;CHECK: vext
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -28,7 +28,7 @@ define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: test_vextRq:
+;CHECK-LABEL: test_vextRq:
 ;CHECK: vext
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -37,7 +37,7 @@ define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: test_vextd16:
+;CHECK-LABEL: test_vextd16:
 ;CHECK: vext
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: test_vextq32:
+;CHECK-LABEL: test_vextq32:
 ;CHECK: vext
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -57,7 +57,7 @@ define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ; Undef shuffle indices should not prevent matching to VEXT:
 
 define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: test_vextd_undef:
+;CHECK-LABEL: test_vextd_undef:
 ;CHECK: vext
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -66,7 +66,7 @@ define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: test_vextRq_undef:
+;CHECK-LABEL: test_vextRq_undef:
 ;CHECK: vext
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -75,7 +75,7 @@ define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <16 x i8> @test_vextq_undef_op2(<16 x i8> %a) nounwind {
-;CHECK: test_vextq_undef_op2:
+;CHECK-LABEL: test_vextq_undef_op2:
 ;CHECK: vext
 entry:
   %tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>
@@ -83,7 +83,7 @@ entry:
 }
 
 define <8 x i8> @test_vextd_undef_op2(<8 x i8> %a) nounwind {
-;CHECK: test_vextd_undef_op2:
+;CHECK-LABEL: test_vextd_undef_op2:
 ;CHECK: vext
 entry:
   %tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>
@@ -92,7 +92,7 @@ entry:
 
 
 define <16 x i8> @test_vextq_undef_op2_undef(<16 x i8> %a) nounwind {
-;CHECK: test_vextq_undef_op2_undef:
+;CHECK-LABEL: test_vextq_undef_op2_undef:
 ;CHECK: vext
 entry:
   %tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>
@@ -100,7 +100,7 @@ entry:
 }
 
 define <8 x i8> @test_vextd_undef_op2_undef(<8 x i8> %a) nounwind {
-;CHECK: test_vextd_undef_op2_undef:
+;CHECK-LABEL: test_vextd_undef_op2_undef:
 ;CHECK: vext
 entry:
   %tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 1>
@@ -114,7 +114,7 @@ entry:
 ; Also checks interleaving of sources is handled correctly.
 ; Essence: a vext is used on %A and something saner than stack load/store for final result.
 define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: test_interleaved:
+;CHECK-LABEL: test_interleaved:
 ;CHECK: vext.16
 ;CHECK-NOT: vext.16
 ;CHECK: vzip.16
@@ -126,7 +126,7 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 
 ; An undef in the shuffle list should still be optimizable
 define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: test_undef:
+;CHECK-LABEL: test_undef:
 ;CHECK: vzip.16
         %tmp1 = load <8 x i16>* %A
         %tmp2 = load <8 x i16>* %B
@@ -136,20 +136,26 @@ define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 
 ; We should ignore a build_vector with more than two sources.
 ; Use illegal <32 x i16> type to produce such a shuffle after legalizing types.
-; Try to look for fallback to stack expansion.
+; Try to look for fallback to by-element inserts.
 define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind {
-;CHECK: test_multisource:
-;CHECK: vst1.16
+;CHECK-LABEL: test_multisource:
+;CHECK: vmov.16 [[REG:d[0-9]+]][0]
+;CHECK: vmov.16 [[REG]][1]
+;CHECK: vmov.16 [[REG]][2]
+;CHECK: vmov.16 [[REG]][3]
         %tmp1 = load <32 x i16>* %B
         %tmp2 = shufflevector <32 x i16> %tmp1, <32 x i16> undef, <4 x i32> <i32 0, i32 8, i32 16, i32 24>
         ret <4 x i16> %tmp2
 }
 
 ; We don't handle shuffles using more than half of a 128-bit vector.
-; Again, test for fallback to stack expansion
+; Again, test for fallback to by-element inserts.
 define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
-;CHECK: test_largespan:
-;CHECK: vst1.16
+;CHECK-LABEL: test_largespan:
+;CHECK: vmov.16 [[REG:d[0-9]+]][0]
+;CHECK: vmov.16 [[REG]][1]
+;CHECK: vmov.16 [[REG]][2]
+;CHECK: vmov.16 [[REG]][3]
         %tmp1 = load <8 x i16>* %B
         %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
         ret <4 x i16> %tmp2
@@ -159,8 +165,15 @@ define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
 ; this rather than blindly emitting a VECTOR_SHUFFLE (infinite
 ; lowering loop can result otherwise).
 define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: test_illegal:
-;CHECK: vst1.16
+;CHECK-LABEL: test_illegal:
+;CHECK: vmov.16 [[REG:d[0-9]+]][0]
+;CHECK: vmov.16 [[REG]][1]
+;CHECK: vmov.16 [[REG]][2]
+;CHECK: vmov.16 [[REG]][3]
+;CHECK: vmov.16 [[REG2:d[0-9]+]][0]
+;CHECK: vmov.16 [[REG2]][1]
+;CHECK: vmov.16 [[REG2]][2]
+;CHECK: vmov.16 [[REG2]][3]
        %tmp1 = load <8 x i16>* %A
        %tmp2 = load <8 x i16>* %B
        %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9>
@@ -170,7 +183,7 @@ define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ; PR11129
 ; Make sure this doesn't crash
 define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind {
-; CHECK: test_elem_mismatch:
+; CHECK-LABEL: test_elem_mismatch:
 ; CHECK: vstr
   %tmp0 = load <2 x i64>* %src, align 16
   %tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32>
diff --git a/test/CodeGen/ARM/vfcmp.ll b/test/CodeGen/ARM/vfcmp.ll
index 6946d02..a23db7b 100644
--- a/test/CodeGen/ARM/vfcmp.ll
+++ b/test/CodeGen/ARM/vfcmp.ll
@@ -4,7 +4,7 @@
 
 ; une is implemented with VCEQ/VMVN
 define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcunef32:
+;CHECK-LABEL: vcunef32:
 ;CHECK: vceq.f32
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <2 x float>* %A
@@ -16,7 +16,7 @@ define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; olt is implemented with VCGT
 define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcoltf32:
+;CHECK-LABEL: vcoltf32:
 ;CHECK: vcgt.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -27,7 +27,7 @@ define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; ole is implemented with VCGE
 define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcolef32:
+;CHECK-LABEL: vcolef32:
 ;CHECK: vcge.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -38,7 +38,7 @@ define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; uge is implemented with VCGT/VMVN
 define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcugef32:
+;CHECK-LABEL: vcugef32:
 ;CHECK: vcgt.f32
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <2 x float>* %A
@@ -50,7 +50,7 @@ define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; ule is implemented with VCGT/VMVN
 define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vculef32:
+;CHECK-LABEL: vculef32:
 ;CHECK: vcgt.f32
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <2 x float>* %A
@@ -62,7 +62,7 @@ define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; ugt is implemented with VCGE/VMVN
 define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcugtf32:
+;CHECK-LABEL: vcugtf32:
 ;CHECK: vcge.f32
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <2 x float>* %A
@@ -74,7 +74,7 @@ define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; ult is implemented with VCGE/VMVN
 define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcultf32:
+;CHECK-LABEL: vcultf32:
 ;CHECK: vcge.f32
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <2 x float>* %A
@@ -86,7 +86,7 @@ define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; ueq is implemented with VCGT/VCGT/VORR/VMVN
 define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcueqf32:
+;CHECK-LABEL: vcueqf32:
 ;CHECK: vcgt.f32
 ;CHECK-NEXT: vcgt.f32
 ;CHECK-NEXT: vorr
@@ -100,7 +100,7 @@ define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; one is implemented with VCGT/VCGT/VORR
 define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vconef32:
+;CHECK-LABEL: vconef32:
 ;CHECK: vcgt.f32
 ;CHECK-NEXT: vcgt.f32
 ;CHECK-NEXT: vorr
@@ -113,7 +113,7 @@ define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; uno is implemented with VCGT/VCGE/VORR/VMVN
 define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcunof32:
+;CHECK-LABEL: vcunof32:
 ;CHECK: vcge.f32
 ;CHECK-NEXT: vcgt.f32
 ;CHECK-NEXT: vorr
@@ -127,7 +127,7 @@ define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind {
 
 ; ord is implemented with VCGT/VCGE/VORR
 define <2 x i32> @vcordf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcordf32:
+;CHECK-LABEL: vcordf32:
 ;CHECK: vcge.f32
 ;CHECK-NEXT: vcgt.f32
 ;CHECK-NEXT: vorr
diff --git a/test/CodeGen/ARM/vfp.ll b/test/CodeGen/ARM/vfp.ll
index 7a4b34f..5d2943c 100644
--- a/test/CodeGen/ARM/vfp.ll
+++ b/test/CodeGen/ARM/vfp.ll
@@ -14,7 +14,7 @@ declare float @fabsf(float)
 declare double @fabs(double)
 
 define void @test_abs(float* %P, double* %D) {
-;CHECK: test_abs:
+;CHECK-LABEL: test_abs:
 	%a = load float* %P		; <float> [#uses=1]
 ;CHECK: vabs.f32
 	%b = call float @fabsf( float %a ) readnone	; <float> [#uses=1]
@@ -27,7 +27,7 @@ define void @test_abs(float* %P, double* %D) {
 }
 
 define void @test_add(float* %P, double* %D) {
-;CHECK: test_add:
+;CHECK-LABEL: test_add:
 	%a = load float* %P		; <float> [#uses=2]
 	%b = fadd float %a, %a		; <float> [#uses=1]
 	store float %b, float* %P
@@ -38,7 +38,7 @@ define void @test_add(float* %P, double* %D) {
 }
 
 define void @test_ext_round(float* %P, double* %D) {
-;CHECK: test_ext_round:
+;CHECK-LABEL: test_ext_round:
 	%a = load float* %P		; <float> [#uses=1]
 ;CHECK: vcvt.f64.f32
 ;CHECK: vcvt.f32.f64
@@ -51,7 +51,7 @@ define void @test_ext_round(float* %P, double* %D) {
 }
 
 define void @test_fma(float* %P1, float* %P2, float* %P3) {
-;CHECK: test_fma:
+;CHECK-LABEL: test_fma:
 	%a1 = load float* %P1		; <float> [#uses=1]
 	%a2 = load float* %P2		; <float> [#uses=1]
 	%a3 = load float* %P3		; <float> [#uses=1]
@@ -63,7 +63,7 @@ define void @test_fma(float* %P1, float* %P2, float* %P3) {
 }
 
 define i32 @test_ftoi(float* %P1) {
-;CHECK: test_ftoi:
+;CHECK-LABEL: test_ftoi:
 	%a1 = load float* %P1		; <float> [#uses=1]
 ;CHECK: vcvt.s32.f32
 	%b1 = fptosi float %a1 to i32		; <i32> [#uses=1]
@@ -71,7 +71,7 @@ define i32 @test_ftoi(float* %P1) {
 }
 
 define i32 @test_ftou(float* %P1) {
-;CHECK: test_ftou:
+;CHECK-LABEL: test_ftou:
 	%a1 = load float* %P1		; <float> [#uses=1]
 ;CHECK: vcvt.u32.f32
 	%b1 = fptoui float %a1 to i32		; <i32> [#uses=1]
@@ -79,7 +79,7 @@ define i32 @test_ftou(float* %P1) {
 }
 
 define i32 @test_dtoi(double* %P1) {
-;CHECK: test_dtoi:
+;CHECK-LABEL: test_dtoi:
 	%a1 = load double* %P1		; <double> [#uses=1]
 ;CHECK: vcvt.s32.f64
 	%b1 = fptosi double %a1 to i32		; <i32> [#uses=1]
@@ -87,7 +87,7 @@ define i32 @test_dtoi(double* %P1) {
 }
 
 define i32 @test_dtou(double* %P1) {
-;CHECK: test_dtou:
+;CHECK-LABEL: test_dtou:
 	%a1 = load double* %P1		; <double> [#uses=1]
 ;CHECK: vcvt.u32.f64
 	%b1 = fptoui double %a1 to i32		; <i32> [#uses=1]
@@ -95,7 +95,7 @@ define i32 @test_dtou(double* %P1) {
 }
 
 define void @test_utod(double* %P1, i32 %X) {
-;CHECK: test_utod:
+;CHECK-LABEL: test_utod:
 ;CHECK: vcvt.f64.u32
 	%b1 = uitofp i32 %X to double		; <double> [#uses=1]
 	store double %b1, double* %P1
@@ -103,7 +103,7 @@ define void @test_utod(double* %P1, i32 %X) {
 }
 
 define void @test_utod2(double* %P1, i8 %X) {
-;CHECK: test_utod2:
+;CHECK-LABEL: test_utod2:
 ;CHECK: vcvt.f64.u32
 	%b1 = uitofp i8 %X to double		; <double> [#uses=1]
 	store double %b1, double* %P1
@@ -111,7 +111,7 @@ define void @test_utod2(double* %P1, i8 %X) {
 }
 
 define void @test_cmp(float* %glob, i32 %X) {
-;CHECK: test_cmp:
+;CHECK-LABEL: test_cmp:
 entry:
 	%tmp = load float* %glob		; <float> [#uses=2]
 	%tmp3 = getelementptr float* %glob, i32 2		; <float*> [#uses=1]
@@ -139,7 +139,7 @@ declare i32 @bar(...)
 declare i32 @baz(...)
 
 define void @test_cmpfp0(float* %glob, i32 %X) {
-;CHECK: test_cmpfp0:
+;CHECK-LABEL: test_cmpfp0:
 entry:
 	%tmp = load float* %glob		; <float> [#uses=1]
 ;CHECK: vcmpe.f32
diff --git a/test/CodeGen/ARM/vget_lane.ll b/test/CodeGen/ARM/vget_lane.ll
index c9ce3b7..2518ee2 100644
--- a/test/CodeGen/ARM/vget_lane.ll
+++ b/test/CodeGen/ARM/vget_lane.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-
 target triple = "thumbv7-elf"
 
 define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
-;CHECK: vget_lanes8:
+;CHECK-LABEL: vget_lanes8:
 ;CHECK: vmov.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = extractelement <8 x i8> %tmp1, i32 1
@@ -12,7 +12,7 @@ define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
 }
 
 define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
-;CHECK: vget_lanes16:
+;CHECK-LABEL: vget_lanes16:
 ;CHECK: vmov.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = extractelement <4 x i16> %tmp1, i32 1
@@ -21,7 +21,7 @@ define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
 }
 
 define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
-;CHECK: vget_laneu8:
+;CHECK-LABEL: vget_laneu8:
 ;CHECK: vmov.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = extractelement <8 x i8> %tmp1, i32 1
@@ -30,7 +30,7 @@ define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
 }
 
 define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
-;CHECK: vget_laneu16:
+;CHECK-LABEL: vget_laneu16:
 ;CHECK: vmov.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = extractelement <4 x i16> %tmp1, i32 1
@@ -40,7 +40,7 @@ define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
 
 ; Do a vector add to keep the extraction from being done directly from memory.
 define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
-;CHECK: vget_lanei32:
+;CHECK-LABEL: vget_lanei32:
 ;CHECK: vmov.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = add <2 x i32> %tmp1, %tmp1
@@ -49,7 +49,7 @@ define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
 }
 
 define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
-;CHECK: vgetQ_lanes8:
+;CHECK-LABEL: vgetQ_lanes8:
 ;CHECK: vmov.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = extractelement <16 x i8> %tmp1, i32 1
@@ -58,7 +58,7 @@ define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
 }
 
 define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
-;CHECK: vgetQ_lanes16:
+;CHECK-LABEL: vgetQ_lanes16:
 ;CHECK: vmov.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = extractelement <8 x i16> %tmp1, i32 1
@@ -67,7 +67,7 @@ define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
 }
 
 define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
-;CHECK: vgetQ_laneu8:
+;CHECK-LABEL: vgetQ_laneu8:
 ;CHECK: vmov.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = extractelement <16 x i8> %tmp1, i32 1
@@ -76,7 +76,7 @@ define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
 }
 
 define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
-;CHECK: vgetQ_laneu16:
+;CHECK-LABEL: vgetQ_laneu16:
 ;CHECK: vmov.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = extractelement <8 x i16> %tmp1, i32 1
@@ -86,7 +86,7 @@ define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
 
 ; Do a vector add to keep the extraction from being done directly from memory.
 define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind {
-;CHECK: vgetQ_lanei32:
+;CHECK-LABEL: vgetQ_lanei32:
 ;CHECK: vmov.32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = add <4 x i32> %tmp1, %tmp1
@@ -159,7 +159,7 @@ return:                                           ; preds = %entry
 }
 
 define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind {
-;CHECK: vset_lane8:
+;CHECK-LABEL: vset_lane8:
 ;CHECK: vmov.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = insertelement <8 x i8> %tmp1, i8 %B, i32 1
@@ -167,7 +167,7 @@ define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind {
 }
 
 define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind {
-;CHECK: vset_lane16:
+;CHECK-LABEL: vset_lane16:
 ;CHECK: vmov.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = insertelement <4 x i16> %tmp1, i16 %B, i32 1
@@ -175,7 +175,7 @@ define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind {
 }
 
 define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind {
-;CHECK: vset_lane32:
+;CHECK-LABEL: vset_lane32:
 ;CHECK: vmov.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = insertelement <2 x i32> %tmp1, i32 %B, i32 1
@@ -183,7 +183,7 @@ define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind {
 }
 
 define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind {
-;CHECK: vsetQ_lane8:
+;CHECK-LABEL: vsetQ_lane8:
 ;CHECK: vmov.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = insertelement <16 x i8> %tmp1, i8 %B, i32 1
@@ -191,7 +191,7 @@ define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind {
 }
 
 define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind {
-;CHECK: vsetQ_lane16:
+;CHECK-LABEL: vsetQ_lane16:
 ;CHECK: vmov.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = insertelement <8 x i16> %tmp1, i16 %B, i32 1
@@ -199,7 +199,7 @@ define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind {
 }
 
 define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
-;CHECK: vsetQ_lane32:
+;CHECK-LABEL: vsetQ_lane32:
 ;CHECK: vmov.32 d{{.*}}[1], r1
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1
@@ -207,7 +207,7 @@ define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
 }
 
 define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind {
-;CHECK: test_vset_lanef32:
+;CHECK-LABEL: test_vset_lanef32:
 ;CHECK: vmov.f32 s3, s0
 ;CHECK: vmov.f64 d0, d1
 entry:
diff --git a/test/CodeGen/ARM/vhadd.ll b/test/CodeGen/ARM/vhadd.ll
index 379e062..9c2ed57 100644
--- a/test/CodeGen/ARM/vhadd.ll
+++ b/test/CodeGen/ARM/vhadd.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhadds8:
+;CHECK-LABEL: vhadds8:
 ;CHECK: vhadd.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhadds16:
+;CHECK-LABEL: vhadds16:
 ;CHECK: vhadd.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhadds32:
+;CHECK-LABEL: vhadds32:
 ;CHECK: vhadd.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhaddu8:
+;CHECK-LABEL: vhaddu8:
 ;CHECK: vhadd.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhaddu16:
+;CHECK-LABEL: vhaddu16:
 ;CHECK: vhadd.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhaddu32:
+;CHECK-LABEL: vhaddu32:
 ;CHECK: vhadd.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhaddQs8:
+;CHECK-LABEL: vhaddQs8:
 ;CHECK: vhadd.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -64,7 +64,7 @@ define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhaddQs16:
+;CHECK-LABEL: vhaddQs16:
 ;CHECK: vhadd.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -73,7 +73,7 @@ define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhaddQs32:
+;CHECK-LABEL: vhaddQs32:
 ;CHECK: vhadd.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -82,7 +82,7 @@ define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhaddQu8:
+;CHECK-LABEL: vhaddQu8:
 ;CHECK: vhadd.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -91,7 +91,7 @@ define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhaddQu16:
+;CHECK-LABEL: vhaddQu16:
 ;CHECK: vhadd.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -100,7 +100,7 @@ define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhaddQu32:
+;CHECK-LABEL: vhaddQu32:
 ;CHECK: vhadd.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -125,7 +125,7 @@ declare <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16>, <8 x i16>) nounwind rea
 declare <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <8 x i8> @vrhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrhadds8:
+;CHECK-LABEL: vrhadds8:
 ;CHECK: vrhadd.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -134,7 +134,7 @@ define <8 x i8> @vrhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vrhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrhadds16:
+;CHECK-LABEL: vrhadds16:
 ;CHECK: vrhadd.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -143,7 +143,7 @@ define <4 x i16> @vrhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vrhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrhadds32:
+;CHECK-LABEL: vrhadds32:
 ;CHECK: vrhadd.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -152,7 +152,7 @@ define <2 x i32> @vrhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vrhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrhaddu8:
+;CHECK-LABEL: vrhaddu8:
 ;CHECK: vrhadd.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -161,7 +161,7 @@ define <8 x i8> @vrhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vrhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrhaddu16:
+;CHECK-LABEL: vrhaddu16:
 ;CHECK: vrhadd.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -170,7 +170,7 @@ define <4 x i16> @vrhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vrhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrhaddu32:
+;CHECK-LABEL: vrhaddu32:
 ;CHECK: vrhadd.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -179,7 +179,7 @@ define <2 x i32> @vrhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vrhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrhaddQs8:
+;CHECK-LABEL: vrhaddQs8:
 ;CHECK: vrhadd.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -188,7 +188,7 @@ define <16 x i8> @vrhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vrhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrhaddQs16:
+;CHECK-LABEL: vrhaddQs16:
 ;CHECK: vrhadd.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -197,7 +197,7 @@ define <8 x i16> @vrhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vrhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrhaddQs32:
+;CHECK-LABEL: vrhaddQs32:
 ;CHECK: vrhadd.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -206,7 +206,7 @@ define <4 x i32> @vrhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vrhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrhaddQu8:
+;CHECK-LABEL: vrhaddQu8:
 ;CHECK: vrhadd.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -215,7 +215,7 @@ define <16 x i8> @vrhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vrhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrhaddQu16:
+;CHECK-LABEL: vrhaddQu16:
 ;CHECK: vrhadd.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -224,7 +224,7 @@ define <8 x i16> @vrhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vrhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrhaddQu32:
+;CHECK-LABEL: vrhaddQu32:
 ;CHECK: vrhadd.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
diff --git a/test/CodeGen/ARM/vhsub.ll b/test/CodeGen/ARM/vhsub.ll
index 0f0d027..4bc2e87 100644
--- a/test/CodeGen/ARM/vhsub.ll
+++ b/test/CodeGen/ARM/vhsub.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhsubs8:
+;CHECK-LABEL: vhsubs8:
 ;CHECK: vhsub.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhsubs16:
+;CHECK-LABEL: vhsubs16:
 ;CHECK: vhsub.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhsubs32:
+;CHECK-LABEL: vhsubs32:
 ;CHECK: vhsub.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhsubu8:
+;CHECK-LABEL: vhsubu8:
 ;CHECK: vhsub.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhsubu16:
+;CHECK-LABEL: vhsubu16:
 ;CHECK: vhsub.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhsubu32:
+;CHECK-LABEL: vhsubu32:
 ;CHECK: vhsub.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhsubQs8:
+;CHECK-LABEL: vhsubQs8:
 ;CHECK: vhsub.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -64,7 +64,7 @@ define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhsubQs16:
+;CHECK-LABEL: vhsubQs16:
 ;CHECK: vhsub.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -73,7 +73,7 @@ define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhsubQs32:
+;CHECK-LABEL: vhsubQs32:
 ;CHECK: vhsub.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -82,7 +82,7 @@ define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhsubQu8:
+;CHECK-LABEL: vhsubQu8:
 ;CHECK: vhsub.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -91,7 +91,7 @@ define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhsubQu16:
+;CHECK-LABEL: vhsubQu16:
 ;CHECK: vhsub.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -100,7 +100,7 @@ define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vhsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhsubQu32:
+;CHECK-LABEL: vhsubQu32:
 ;CHECK: vhsub.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
diff --git a/test/CodeGen/ARM/vicmp.ll b/test/CodeGen/ARM/vicmp.ll
index 2d8cb89..0a8f103 100644
--- a/test/CodeGen/ARM/vicmp.ll
+++ b/test/CodeGen/ARM/vicmp.ll
@@ -7,7 +7,7 @@
 ; the other operations.
 
 define <8 x i8> @vcnei8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcnei8:
+;CHECK-LABEL: vcnei8:
 ;CHECK: vceq.i8
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <8 x i8>* %A
@@ -18,7 +18,7 @@ define <8 x i8> @vcnei8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vcnei16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcnei16:
+;CHECK-LABEL: vcnei16:
 ;CHECK: vceq.i16
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <4 x i16>* %A
@@ -29,7 +29,7 @@ define <4 x i16> @vcnei16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vcnei32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcnei32:
+;CHECK-LABEL: vcnei32:
 ;CHECK: vceq.i32
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <2 x i32>* %A
@@ -40,7 +40,7 @@ define <2 x i32> @vcnei32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vcneQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcneQi8:
+;CHECK-LABEL: vcneQi8:
 ;CHECK: vceq.i8
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <16 x i8>* %A
@@ -51,7 +51,7 @@ define <16 x i8> @vcneQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vcneQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcneQi16:
+;CHECK-LABEL: vcneQi16:
 ;CHECK: vceq.i16
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <8 x i16>* %A
@@ -62,7 +62,7 @@ define <8 x i16> @vcneQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcneQi32:
+;CHECK-LABEL: vcneQi32:
 ;CHECK: vceq.i32
 ;CHECK-NEXT: vmvn
 	%tmp1 = load <4 x i32>* %A
@@ -73,7 +73,7 @@ define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcltQs8:
+;CHECK-LABEL: vcltQs8:
 ;CHECK: vcgt.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -83,7 +83,7 @@ define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcles16:
+;CHECK-LABEL: vcles16:
 ;CHECK: vcge.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -93,7 +93,7 @@ define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcltu16:
+;CHECK-LABEL: vcltu16:
 ;CHECK: vcgt.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -103,7 +103,7 @@ define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vcleQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcleQu32:
+;CHECK-LABEL: vcleQu32:
 ;CHECK: vcge.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll
index 994f05d..444d0d5 100644
--- a/test/CodeGen/ARM/vld1.ll
+++ b/test/CodeGen/ARM/vld1.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
 
 define <8 x i8> @vld1i8(i8* %A) nounwind {
-;CHECK: vld1i8:
+;CHECK-LABEL: vld1i8:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld1.8 {d16}, [r0:64]
 	%tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16)
@@ -10,7 +10,7 @@ define <8 x i8> @vld1i8(i8* %A) nounwind {
 }
 
 define <4 x i16> @vld1i16(i16* %A) nounwind {
-;CHECK: vld1i16:
+;CHECK-LABEL: vld1i16:
 ;CHECK: vld1.16
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1)
@@ -19,7 +19,7 @@ define <4 x i16> @vld1i16(i16* %A) nounwind {
 
 ;Check for a post-increment updating load. 
 define <4 x i16> @vld1i16_update(i16** %ptr) nounwind {
-;CHECK: vld1i16_update:
+;CHECK-LABEL: vld1i16_update:
 ;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]!
 	%A = load i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
@@ -30,7 +30,7 @@ define <4 x i16> @vld1i16_update(i16** %ptr) nounwind {
 }
 
 define <2 x i32> @vld1i32(i32* %A) nounwind {
-;CHECK: vld1i32:
+;CHECK-LABEL: vld1i32:
 ;CHECK: vld1.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1)
@@ -39,7 +39,7 @@ define <2 x i32> @vld1i32(i32* %A) nounwind {
 
 ;Check for a post-increment updating load with register increment.
 define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind {
-;CHECK: vld1i32_update:
+;CHECK-LABEL: vld1i32_update:
 ;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}}
 	%A = load i32** %ptr
 	%tmp0 = bitcast i32* %A to i8*
@@ -50,7 +50,7 @@ define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind {
 }
 
 define <2 x float> @vld1f(float* %A) nounwind {
-;CHECK: vld1f:
+;CHECK-LABEL: vld1f:
 ;CHECK: vld1.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %tmp0, i32 1)
@@ -58,7 +58,7 @@ define <2 x float> @vld1f(float* %A) nounwind {
 }
 
 define <1 x i64> @vld1i64(i64* %A) nounwind {
-;CHECK: vld1i64:
+;CHECK-LABEL: vld1i64:
 ;CHECK: vld1.64
 	%tmp0 = bitcast i64* %A to i8*
 	%tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %tmp0, i32 1)
@@ -66,7 +66,7 @@ define <1 x i64> @vld1i64(i64* %A) nounwind {
 }
 
 define <16 x i8> @vld1Qi8(i8* %A) nounwind {
-;CHECK: vld1Qi8:
+;CHECK-LABEL: vld1Qi8:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vld1.8 {d16, d17}, [r0:64]
 	%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
@@ -75,7 +75,7 @@ define <16 x i8> @vld1Qi8(i8* %A) nounwind {
 
 ;Check for a post-increment updating load.
 define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
-;CHECK: vld1Qi8_update:
+;CHECK-LABEL: vld1Qi8_update:
 ;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}:64]!
 	%A = load i8** %ptr
 	%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
@@ -85,7 +85,7 @@ define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
 }
 
 define <8 x i16> @vld1Qi16(i16* %A) nounwind {
-;CHECK: vld1Qi16:
+;CHECK-LABEL: vld1Qi16:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vld1.16 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -94,7 +94,7 @@ define <8 x i16> @vld1Qi16(i16* %A) nounwind {
 }
 
 define <4 x i32> @vld1Qi32(i32* %A) nounwind {
-;CHECK: vld1Qi32:
+;CHECK-LABEL: vld1Qi32:
 ;CHECK: vld1.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %tmp0, i32 1)
@@ -102,7 +102,7 @@ define <4 x i32> @vld1Qi32(i32* %A) nounwind {
 }
 
 define <4 x float> @vld1Qf(float* %A) nounwind {
-;CHECK: vld1Qf:
+;CHECK-LABEL: vld1Qf:
 ;CHECK: vld1.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %tmp0, i32 1)
@@ -110,7 +110,7 @@ define <4 x float> @vld1Qf(float* %A) nounwind {
 }
 
 define <2 x i64> @vld1Qi64(i64* %A) nounwind {
-;CHECK: vld1Qi64:
+;CHECK-LABEL: vld1Qi64:
 ;CHECK: vld1.64
 	%tmp0 = bitcast i64* %A to i8*
 	%tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0, i32 1)
diff --git a/test/CodeGen/ARM/vld2.ll b/test/CodeGen/ARM/vld2.ll
index caa016e..fddafea 100644
--- a/test/CodeGen/ARM/vld2.ll
+++ b/test/CodeGen/ARM/vld2.ll
@@ -12,7 +12,7 @@
 %struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
 
 define <8 x i8> @vld2i8(i8* %A) nounwind {
-;CHECK: vld2i8:
+;CHECK-LABEL: vld2i8:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vld2.8 {d16, d17}, [r0:64]
 	%tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 8)
@@ -23,7 +23,7 @@ define <8 x i8> @vld2i8(i8* %A) nounwind {
 }
 
 define <4 x i16> @vld2i16(i16* %A) nounwind {
-;CHECK: vld2i16:
+;CHECK-LABEL: vld2i16:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vld2.16 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -35,7 +35,7 @@ define <4 x i16> @vld2i16(i16* %A) nounwind {
 }
 
 define <2 x i32> @vld2i32(i32* %A) nounwind {
-;CHECK: vld2i32:
+;CHECK-LABEL: vld2i32:
 ;CHECK: vld2.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8* %tmp0, i32 1)
@@ -46,7 +46,7 @@ define <2 x i32> @vld2i32(i32* %A) nounwind {
 }
 
 define <2 x float> @vld2f(float* %A) nounwind {
-;CHECK: vld2f:
+;CHECK-LABEL: vld2f:
 ;CHECK: vld2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 1)
@@ -58,7 +58,7 @@ define <2 x float> @vld2f(float* %A) nounwind {
 
 ;Check for a post-increment updating load. 
 define <2 x float> @vld2f_update(float** %ptr) nounwind {
-;CHECK: vld2f_update:
+;CHECK-LABEL: vld2f_update:
 ;CHECK: vld2.32 {d16, d17}, [r1]!
 	%A = load float** %ptr
 	%tmp0 = bitcast float* %A to i8*
@@ -72,7 +72,7 @@ define <2 x float> @vld2f_update(float** %ptr) nounwind {
 }
 
 define <1 x i64> @vld2i64(i64* %A) nounwind {
-;CHECK: vld2i64:
+;CHECK-LABEL: vld2i64:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vld1.64 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i64* %A to i8*
@@ -84,7 +84,7 @@ define <1 x i64> @vld2i64(i64* %A) nounwind {
 }
 
 define <16 x i8> @vld2Qi8(i8* %A) nounwind {
-;CHECK: vld2Qi8:
+;CHECK-LABEL: vld2Qi8:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64]
 	%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 8)
@@ -96,7 +96,7 @@ define <16 x i8> @vld2Qi8(i8* %A) nounwind {
 
 ;Check for a post-increment updating load with register increment.
 define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind {
-;CHECK: vld2Qi8_update:
+;CHECK-LABEL: vld2Qi8_update:
 ;CHECK: vld2.8 {d16, d17, d18, d19}, [r2:128], r1
 	%A = load i8** %ptr
 	%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 16)
@@ -109,7 +109,7 @@ define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind {
 }
 
 define <8 x i16> @vld2Qi16(i16* %A) nounwind {
-;CHECK: vld2Qi16:
+;CHECK-LABEL: vld2Qi16:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -121,7 +121,7 @@ define <8 x i16> @vld2Qi16(i16* %A) nounwind {
 }
 
 define <4 x i32> @vld2Qi32(i32* %A) nounwind {
-;CHECK: vld2Qi32:
+;CHECK-LABEL: vld2Qi32:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256]
 	%tmp0 = bitcast i32* %A to i8*
@@ -133,7 +133,7 @@ define <4 x i32> @vld2Qi32(i32* %A) nounwind {
 }
 
 define <4 x float> @vld2Qf(float* %A) nounwind {
-;CHECK: vld2Qf:
+;CHECK-LABEL: vld2Qf:
 ;CHECK: vld2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32(i8* %tmp0, i32 1)
diff --git a/test/CodeGen/ARM/vld3.ll b/test/CodeGen/ARM/vld3.ll
index ad63e1f..400541f 100644
--- a/test/CodeGen/ARM/vld3.ll
+++ b/test/CodeGen/ARM/vld3.ll
@@ -13,7 +13,7 @@
 %struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
 
 define <8 x i8> @vld3i8(i8* %A) nounwind {
-;CHECK: vld3i8:
+;CHECK-LABEL: vld3i8:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld3.8 {d16, d17, d18}, [r0:64]
 	%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32)
@@ -24,7 +24,7 @@ define <8 x i8> @vld3i8(i8* %A) nounwind {
 }
 
 define <4 x i16> @vld3i16(i16* %A) nounwind {
-;CHECK: vld3i16:
+;CHECK-LABEL: vld3i16:
 ;CHECK: vld3.16
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1)
@@ -36,7 +36,7 @@ define <4 x i16> @vld3i16(i16* %A) nounwind {
 
 ;Check for a post-increment updating load with register increment.
 define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind {
-;CHECK: vld3i16_update:
+;CHECK-LABEL: vld3i16_update:
 ;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}}
 	%A = load i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
@@ -50,7 +50,7 @@ define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind {
 }
 
 define <2 x i32> @vld3i32(i32* %A) nounwind {
-;CHECK: vld3i32:
+;CHECK-LABEL: vld3i32:
 ;CHECK: vld3.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %tmp0, i32 1)
@@ -61,7 +61,7 @@ define <2 x i32> @vld3i32(i32* %A) nounwind {
 }
 
 define <2 x float> @vld3f(float* %A) nounwind {
-;CHECK: vld3f:
+;CHECK-LABEL: vld3f:
 ;CHECK: vld3.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8* %tmp0, i32 1)
@@ -72,7 +72,7 @@ define <2 x float> @vld3f(float* %A) nounwind {
 }
 
 define <1 x i64> @vld3i64(i64* %A) nounwind {
-;CHECK: vld3i64:
+;CHECK-LABEL: vld3i64:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld1.64 {d16, d17, d18}, [r0:64]
 	%tmp0 = bitcast i64* %A to i8*
@@ -84,7 +84,7 @@ define <1 x i64> @vld3i64(i64* %A) nounwind {
 }
 
 define <16 x i8> @vld3Qi8(i8* %A) nounwind {
-;CHECK: vld3Qi8:
+;CHECK-LABEL: vld3Qi8:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld3.8 {d16, d18, d20}, [r0:64]!
 ;CHECK: vld3.8 {d17, d19, d21}, [r0:64]
@@ -96,7 +96,7 @@ define <16 x i8> @vld3Qi8(i8* %A) nounwind {
 }
 
 define <8 x i16> @vld3Qi16(i16* %A) nounwind {
-;CHECK: vld3Qi16:
+;CHECK-LABEL: vld3Qi16:
 ;CHECK: vld3.16
 ;CHECK: vld3.16
 	%tmp0 = bitcast i16* %A to i8*
@@ -108,7 +108,7 @@ define <8 x i16> @vld3Qi16(i16* %A) nounwind {
 }
 
 define <4 x i32> @vld3Qi32(i32* %A) nounwind {
-;CHECK: vld3Qi32:
+;CHECK-LABEL: vld3Qi32:
 ;CHECK: vld3.32
 ;CHECK: vld3.32
 	%tmp0 = bitcast i32* %A to i8*
@@ -121,7 +121,7 @@ define <4 x i32> @vld3Qi32(i32* %A) nounwind {
 
 ;Check for a post-increment updating load. 
 define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind {
-;CHECK: vld3Qi32_update:
+;CHECK-LABEL: vld3Qi32_update:
 ;CHECK: vld3.32 {d16, d18, d20}, [r[[R:[0-9]+]]]!
 ;CHECK: vld3.32 {d17, d19, d21}, [r[[R]]]!
 	%A = load i32** %ptr
@@ -136,7 +136,7 @@ define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind {
 }
 
 define <4 x float> @vld3Qf(float* %A) nounwind {
-;CHECK: vld3Qf:
+;CHECK-LABEL: vld3Qf:
 ;CHECK: vld3.32
 ;CHECK: vld3.32
 	%tmp0 = bitcast float* %A to i8*
diff --git a/test/CodeGen/ARM/vld4.ll b/test/CodeGen/ARM/vld4.ll
index 9ee5fe4..f7376b5 100644
--- a/test/CodeGen/ARM/vld4.ll
+++ b/test/CodeGen/ARM/vld4.ll
@@ -12,7 +12,7 @@
 %struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
 
 define <8 x i8> @vld4i8(i8* %A) nounwind {
-;CHECK: vld4i8:
+;CHECK-LABEL: vld4i8:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64]
 	%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 8)
@@ -24,7 +24,7 @@ define <8 x i8> @vld4i8(i8* %A) nounwind {
 
 ;Check for a post-increment updating load with register increment.
 define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind {
-;CHECK: vld4i8_update:
+;CHECK-LABEL: vld4i8_update:
 ;CHECK: vld4.8 {d16, d17, d18, d19}, [r2:128], r1
 	%A = load i8** %ptr
 	%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16)
@@ -37,7 +37,7 @@ define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind {
 }
 
 define <4 x i16> @vld4i16(i16* %A) nounwind {
-;CHECK: vld4i16:
+;CHECK-LABEL: vld4i16:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -49,7 +49,7 @@ define <4 x i16> @vld4i16(i16* %A) nounwind {
 }
 
 define <2 x i32> @vld4i32(i32* %A) nounwind {
-;CHECK: vld4i32:
+;CHECK-LABEL: vld4i32:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256]
 	%tmp0 = bitcast i32* %A to i8*
@@ -61,7 +61,7 @@ define <2 x i32> @vld4i32(i32* %A) nounwind {
 }
 
 define <2 x float> @vld4f(float* %A) nounwind {
-;CHECK: vld4f:
+;CHECK-LABEL: vld4f:
 ;CHECK: vld4.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8* %tmp0, i32 1)
@@ -72,7 +72,7 @@ define <2 x float> @vld4f(float* %A) nounwind {
 }
 
 define <1 x i64> @vld4i64(i64* %A) nounwind {
-;CHECK: vld4i64:
+;CHECK-LABEL: vld4i64:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld1.64 {d16, d17, d18, d19}, [r0:256]
 	%tmp0 = bitcast i64* %A to i8*
@@ -84,7 +84,7 @@ define <1 x i64> @vld4i64(i64* %A) nounwind {
 }
 
 define <16 x i8> @vld4Qi8(i8* %A) nounwind {
-;CHECK: vld4Qi8:
+;CHECK-LABEL: vld4Qi8:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]!
 ;CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256]
@@ -96,7 +96,7 @@ define <16 x i8> @vld4Qi8(i8* %A) nounwind {
 }
 
 define <8 x i16> @vld4Qi16(i16* %A) nounwind {
-;CHECK: vld4Qi16:
+;CHECK-LABEL: vld4Qi16:
 ;Check for no alignment specifier.
 ;CHECK: vld4.16 {d16, d18, d20, d22}, [r0]!
 ;CHECK: vld4.16 {d17, d19, d21, d23}, [r0]
@@ -110,7 +110,7 @@ define <8 x i16> @vld4Qi16(i16* %A) nounwind {
 
 ;Check for a post-increment updating load. 
 define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind {
-;CHECK: vld4Qi16_update:
+;CHECK-LABEL: vld4Qi16_update:
 ;CHECK: vld4.16 {d16, d18, d20, d22}, [r1:64]!
 ;CHECK: vld4.16 {d17, d19, d21, d23}, [r1:64]!
 	%A = load i16** %ptr
@@ -125,7 +125,7 @@ define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind {
 }
 
 define <4 x i32> @vld4Qi32(i32* %A) nounwind {
-;CHECK: vld4Qi32:
+;CHECK-LABEL: vld4Qi32:
 ;CHECK: vld4.32
 ;CHECK: vld4.32
 	%tmp0 = bitcast i32* %A to i8*
@@ -137,7 +137,7 @@ define <4 x i32> @vld4Qi32(i32* %A) nounwind {
 }
 
 define <4 x float> @vld4Qf(float* %A) nounwind {
-;CHECK: vld4Qf:
+;CHECK-LABEL: vld4Qf:
 ;CHECK: vld4.32
 ;CHECK: vld4.32
 	%tmp0 = bitcast float* %A to i8*
diff --git a/test/CodeGen/ARM/vlddup.ll b/test/CodeGen/ARM/vlddup.ll
index 7c7319c..5509f3e 100644
--- a/test/CodeGen/ARM/vlddup.ll
+++ b/test/CodeGen/ARM/vlddup.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vld1dupi8(i8* %A) nounwind {
-;CHECK: vld1dupi8:
+;CHECK-LABEL: vld1dupi8:
 ;Check the (default) alignment value.
 ;CHECK: vld1.8 {d16[]}, [r0]
 	%tmp1 = load i8* %A, align 8
@@ -11,7 +11,7 @@ define <8 x i8> @vld1dupi8(i8* %A) nounwind {
 }
 
 define <4 x i16> @vld1dupi16(i16* %A) nounwind {
-;CHECK: vld1dupi16:
+;CHECK-LABEL: vld1dupi16:
 ;Check the alignment value.  Max for this instruction is 16 bits:
 ;CHECK: vld1.16 {d16[]}, [r0:16]
 	%tmp1 = load i16* %A, align 8
@@ -21,7 +21,7 @@ define <4 x i16> @vld1dupi16(i16* %A) nounwind {
 }
 
 define <2 x i32> @vld1dupi32(i32* %A) nounwind {
-;CHECK: vld1dupi32:
+;CHECK-LABEL: vld1dupi32:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vld1.32 {d16[]}, [r0:32]
 	%tmp1 = load i32* %A, align 8
@@ -31,7 +31,7 @@ define <2 x i32> @vld1dupi32(i32* %A) nounwind {
 }
 
 define <2 x float> @vld1dupf(float* %A) nounwind {
-;CHECK: vld1dupf:
+;CHECK-LABEL: vld1dupf:
 ;CHECK: vld1.32 {d16[]}, [r0:32]
 	%tmp0 = load float* %A
         %tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
@@ -40,7 +40,7 @@ define <2 x float> @vld1dupf(float* %A) nounwind {
 }
 
 define <16 x i8> @vld1dupQi8(i8* %A) nounwind {
-;CHECK: vld1dupQi8:
+;CHECK-LABEL: vld1dupQi8:
 ;Check the (default) alignment value.
 ;CHECK: vld1.8 {d16[], d17[]}, [r0]
 	%tmp1 = load i8* %A, align 8
@@ -50,7 +50,7 @@ define <16 x i8> @vld1dupQi8(i8* %A) nounwind {
 }
 
 define <4 x float> @vld1dupQf(float* %A) nounwind {
-;CHECK: vld1dupQf:
+;CHECK-LABEL: vld1dupQf:
 ;CHECK: vld1.32 {d16[], d17[]}, [r0:32]
         %tmp0 = load float* %A
         %tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
@@ -63,7 +63,7 @@ define <4 x float> @vld1dupQf(float* %A) nounwind {
 %struct.__neon_int2x32x2_t = type { <2 x i32>, <2 x i32> }
 
 define <8 x i8> @vld2dupi8(i8* %A) nounwind {
-;CHECK: vld2dupi8:
+;CHECK-LABEL: vld2dupi8:
 ;Check the (default) alignment value.
 ;CHECK: vld2.8 {d16[], d17[]}, [r0]
 	%tmp0 = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
@@ -76,7 +76,7 @@ define <8 x i8> @vld2dupi8(i8* %A) nounwind {
 }
 
 define <4 x i16> @vld2dupi16(i8* %A) nounwind {
-;CHECK: vld2dupi16:
+;CHECK-LABEL: vld2dupi16:
 ;Check that a power-of-two alignment smaller than the total size of the memory
 ;being loaded is ignored.
 ;CHECK: vld2.16 {d16[], d17[]}, [r0]
@@ -91,7 +91,7 @@ define <4 x i16> @vld2dupi16(i8* %A) nounwind {
 
 ;Check for a post-increment updating load. 
 define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind {
-;CHECK: vld2dupi16_update:
+;CHECK-LABEL: vld2dupi16_update:
 ;CHECK: vld2.16 {d16[], d17[]}, [r1]!
 	%A = load i16** %ptr
         %A2 = bitcast i16* %A to i8*
@@ -107,7 +107,7 @@ define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind {
 }
 
 define <2 x i32> @vld2dupi32(i8* %A) nounwind {
-;CHECK: vld2dupi32:
+;CHECK-LABEL: vld2dupi32:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld2.32 {d16[], d17[]}, [r0:64]
 	%tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16)
@@ -128,7 +128,7 @@ declare %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i8*, <2 x i32>,
 
 ;Check for a post-increment updating load with register increment.
 define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind {
-;CHECK: vld3dupi8_update:
+;CHECK-LABEL: vld3dupi8_update:
 ;CHECK: vld3.8 {d16[], d17[], d18[]}, [r2], r1
 	%A = load i8** %ptr
 	%tmp0 = tail call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 8)
@@ -146,7 +146,7 @@ define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind {
 }
 
 define <4 x i16> @vld3dupi16(i8* %A) nounwind {
-;CHECK: vld3dupi16:
+;CHECK-LABEL: vld3dupi16:
 ;Check the (default) alignment value. VLD3 does not support alignment.
 ;CHECK: vld3.16 {d16[], d17[], d18[]}, [r0]
 	%tmp0 = tail call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 8)
@@ -169,7 +169,7 @@ declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8*, <4 x i16>,
 
 ;Check for a post-increment updating load.
 define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind {
-;CHECK: vld4dupi16_update:
+;CHECK-LABEL: vld4dupi16_update:
 ;CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r1]!
 	%A = load i16** %ptr
         %A2 = bitcast i16* %A to i8*
@@ -191,7 +191,7 @@ define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind {
 }
 
 define <2 x i32> @vld4dupi32(i8* %A) nounwind {
-;CHECK: vld4dupi32:
+;CHECK-LABEL: vld4dupi32:
 ;Check the alignment value.  An 8-byte alignment is allowed here even though
 ;it is smaller than the total size of the memory being loaded.
 ;CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r0:64]
diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll
index f35fa92..7a83a4c 100644
--- a/test/CodeGen/ARM/vldlane.ll
+++ b/test/CodeGen/ARM/vldlane.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
 
 define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld1lanei8:
+;CHECK-LABEL: vld1lanei8:
 ;Check the (default) alignment value.
 ;CHECK: vld1.8 {d16[3]}, [r0]
 	%tmp1 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld1lanei16:
+;CHECK-LABEL: vld1lanei16:
 ;Check the alignment value.  Max for this instruction is 16 bits:
 ;CHECK: vld1.16 {d16[2]}, [r0:16]
 	%tmp1 = load <4 x i16>* %B
@@ -22,7 +22,7 @@ define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld1lanei32:
+;CHECK-LABEL: vld1lanei32:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vld1.32 {d16[1]}, [r0:32]
 	%tmp1 = load <2 x i32>* %B
@@ -32,7 +32,7 @@ define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld1lanei32a32:
+;CHECK-LABEL: vld1lanei32a32:
 ;Check the alignment value.  Legal values are none or :32.
 ;CHECK: vld1.32 {d16[1]}, [r0:32]
 	%tmp1 = load <2 x i32>* %B
@@ -42,7 +42,7 @@ define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld1lanef:
+;CHECK-LABEL: vld1lanef:
 ;CHECK: vld1.32 {d16[1]}, [r0:32]
 	%tmp1 = load <2 x float>* %B
 	%tmp2 = load float* %A, align 4
@@ -51,7 +51,7 @@ define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vld1laneQi8:
+;CHECK-LABEL: vld1laneQi8:
 ;CHECK: vld1.8 {d17[1]}, [r0]
 	%tmp1 = load <16 x i8>* %B
 	%tmp2 = load i8* %A, align 8
@@ -60,7 +60,7 @@ define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld1laneQi16:
+;CHECK-LABEL: vld1laneQi16:
 ;CHECK: vld1.16 {d17[1]}, [r0:16]
 	%tmp1 = load <8 x i16>* %B
 	%tmp2 = load i16* %A, align 8
@@ -69,7 +69,7 @@ define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld1laneQi32:
+;CHECK-LABEL: vld1laneQi32:
 ;CHECK: vld1.32 {d17[1]}, [r0:32]
 	%tmp1 = load <4 x i32>* %B
 	%tmp2 = load i32* %A, align 8
@@ -78,7 +78,7 @@ define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld1laneQf:
+;CHECK-LABEL: vld1laneQf:
 ;CHECK: vld1.32 {d16[0]}, [r0:32]
 	%tmp1 = load <4 x float>* %B
 	%tmp2 = load float* %A
@@ -96,7 +96,7 @@ define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind {
 %struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
 
 define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld2lanei8:
+;CHECK-LABEL: vld2lanei8:
 ;Check the alignment value.  Max for this instruction is 16 bits:
 ;CHECK: vld2.8 {d16[1], d17[1]}, [r0:16]
 	%tmp1 = load <8 x i8>* %B
@@ -108,7 +108,7 @@ define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld2lanei16:
+;CHECK-LABEL: vld2lanei16:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vld2.16 {d16[1], d17[1]}, [r0:32]
 	%tmp0 = bitcast i16* %A to i8*
@@ -121,7 +121,7 @@ define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld2lanei32:
+;CHECK-LABEL: vld2lanei32:
 ;CHECK: vld2.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <2 x i32>* %B
@@ -134,7 +134,7 @@ define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind {
 
 ;Check for a post-increment updating load.
 define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind {
-;CHECK: vld2lanei32_update:
+;CHECK-LABEL: vld2lanei32_update:
 ;CHECK: vld2.32 {d16[1], d17[1]}, [{{r[0-9]+}}]!
 	%A = load i32** %ptr
 	%tmp0 = bitcast i32* %A to i8*
@@ -149,7 +149,7 @@ define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld2lanef:
+;CHECK-LABEL: vld2lanef:
 ;CHECK: vld2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -161,7 +161,7 @@ define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld2laneQi16:
+;CHECK-LABEL: vld2laneQi16:
 ;Check the (default) alignment.
 ;CHECK: vld2.16 {d17[1], d19[1]}, [{{r[0-9]+}}]
 	%tmp0 = bitcast i16* %A to i8*
@@ -174,7 +174,7 @@ define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld2laneQi32:
+;CHECK-LABEL: vld2laneQi32:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld2.32 {d17[0], d19[0]}, [{{r[0-9]+}}:64]
 	%tmp0 = bitcast i32* %A to i8*
@@ -187,7 +187,7 @@ define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld2laneQf:
+;CHECK-LABEL: vld2laneQf:
 ;CHECK: vld2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
@@ -217,7 +217,7 @@ declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8*, <4 x flo
 %struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
 
 define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld3lanei8:
+;CHECK-LABEL: vld3lanei8:
 ;CHECK: vld3.8
 	%tmp1 = load <8 x i8>* %B
 	%tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
@@ -230,7 +230,7 @@ define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld3lanei16:
+;CHECK-LABEL: vld3lanei16:
 ;Check the (default) alignment value.  VLD3 does not support alignment.
 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}]
 	%tmp0 = bitcast i16* %A to i8*
@@ -245,7 +245,7 @@ define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld3lanei32:
+;CHECK-LABEL: vld3lanei32:
 ;CHECK: vld3.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <2 x i32>* %B
@@ -259,7 +259,7 @@ define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld3lanef:
+;CHECK-LABEL: vld3lanef:
 ;CHECK: vld3.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -273,7 +273,7 @@ define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld3laneQi16:
+;CHECK-LABEL: vld3laneQi16:
 ;Check the (default) alignment value.  VLD3 does not support alignment.
 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}]
 	%tmp0 = bitcast i16* %A to i8*
@@ -289,7 +289,7 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 
 ;Check for a post-increment updating load with register increment.
 define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
-;CHECK: vld3laneQi16_update:
+;CHECK-LABEL: vld3laneQi16_update:
 ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}], {{r[0-9]+}}
 	%A = load i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
@@ -306,7 +306,7 @@ define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounw
 }
 
 define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld3laneQi32:
+;CHECK-LABEL: vld3laneQi32:
 ;CHECK: vld3.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <4 x i32>* %B
@@ -320,7 +320,7 @@ define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld3laneQf:
+;CHECK-LABEL: vld3laneQf:
 ;CHECK: vld3.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
@@ -352,7 +352,7 @@ declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8*, <4 x flo
 %struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
 
 define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld4lanei8:
+;CHECK-LABEL: vld4lanei8:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vld4.8 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}:32]
 	%tmp1 = load <8 x i8>* %B
@@ -369,7 +369,7 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
 
 ;Check for a post-increment updating load.
 define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
-;CHECK: vld4lanei8_update:
+;CHECK-LABEL: vld4lanei8_update:
 ;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:32]!
 	%A = load i8** %ptr
 	%tmp1 = load <8 x i8>* %B
@@ -387,7 +387,7 @@ define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld4lanei16:
+;CHECK-LABEL: vld4lanei16:
 ;Check that a power-of-two alignment smaller than the total size of the memory
 ;being loaded is ignored.
 ;CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}]
@@ -405,7 +405,7 @@ define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld4lanei32:
+;CHECK-LABEL: vld4lanei32:
 ;Check the alignment value.  An 8-byte alignment is allowed here even though
 ;it is smaller than the total size of the memory being loaded.
 ;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:64]
@@ -423,7 +423,7 @@ define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld4lanef:
+;CHECK-LABEL: vld4lanef:
 ;CHECK: vld4.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -439,7 +439,7 @@ define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld4laneQi16:
+;CHECK-LABEL: vld4laneQi16:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [{{r[0-9]+}}:64]
 	%tmp0 = bitcast i16* %A to i8*
@@ -456,7 +456,7 @@ define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld4laneQi32:
+;CHECK-LABEL: vld4laneQi32:
 ;Check the (default) alignment.
 ;CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [{{r[0-9]+}}]
 	%tmp0 = bitcast i32* %A to i8*
@@ -473,7 +473,7 @@ define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld4laneQf:
+;CHECK-LABEL: vld4laneQf:
 ;CHECK: vld4.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
@@ -502,7 +502,7 @@ declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8*, <4 x flo
 ; we don't currently have a QQQQ_VFP2 super-regclass.  (The "0" for the low
 ; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.)
 define <8 x i16> @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind {
-;CHECK: test_qqqq_regsequence_subreg
+;CHECK-LABEL: test_qqqq_regsequence_subreg:
 ;CHECK: vld3.16
   %tmp63 = extractvalue [6 x i64] %b, 5
   %tmp64 = zext i64 %tmp63 to i128
diff --git a/test/CodeGen/ARM/vminmax.ll b/test/CodeGen/ARM/vminmax.ll
index e3527c1..81f4578 100644
--- a/test/CodeGen/ARM/vminmax.ll
+++ b/test/CodeGen/ARM/vminmax.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmins8:
+;CHECK-LABEL: vmins8:
 ;CHECK: vmin.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmins16:
+;CHECK-LABEL: vmins16:
 ;CHECK: vmin.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmins32:
+;CHECK-LABEL: vmins32:
 ;CHECK: vmin.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vminu8:
+;CHECK-LABEL: vminu8:
 ;CHECK: vmin.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vminu16:
+;CHECK-LABEL: vminu16:
 ;CHECK: vmin.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vminu32:
+;CHECK-LABEL: vminu32:
 ;CHECK: vmin.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vminf32:
+;CHECK-LABEL: vminf32:
 ;CHECK: vmin.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -64,7 +64,7 @@ define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vminQs8:
+;CHECK-LABEL: vminQs8:
 ;CHECK: vmin.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -73,7 +73,7 @@ define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vminQs16:
+;CHECK-LABEL: vminQs16:
 ;CHECK: vmin.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -82,7 +82,7 @@ define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vminQs32:
+;CHECK-LABEL: vminQs32:
 ;CHECK: vmin.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -91,7 +91,7 @@ define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vminQu8:
+;CHECK-LABEL: vminQu8:
 ;CHECK: vmin.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -100,7 +100,7 @@ define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vminQu16:
+;CHECK-LABEL: vminQu16:
 ;CHECK: vmin.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -109,7 +109,7 @@ define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vminQu32:
+;CHECK-LABEL: vminQu32:
 ;CHECK: vmin.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -118,7 +118,7 @@ define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vminQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vminQf32:
+;CHECK-LABEL: vminQf32:
 ;CHECK: vmin.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -147,7 +147,7 @@ declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>) nounwind read
 declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
 
 define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmaxs8:
+;CHECK-LABEL: vmaxs8:
 ;CHECK: vmax.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -156,7 +156,7 @@ define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmaxs16:
+;CHECK-LABEL: vmaxs16:
 ;CHECK: vmax.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -165,7 +165,7 @@ define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmaxs32:
+;CHECK-LABEL: vmaxs32:
 ;CHECK: vmax.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -174,7 +174,7 @@ define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmaxu8:
+;CHECK-LABEL: vmaxu8:
 ;CHECK: vmax.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -183,7 +183,7 @@ define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmaxu16:
+;CHECK-LABEL: vmaxu16:
 ;CHECK: vmax.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -192,7 +192,7 @@ define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmaxu32:
+;CHECK-LABEL: vmaxu32:
 ;CHECK: vmax.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -201,7 +201,7 @@ define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vmaxf32:
+;CHECK-LABEL: vmaxf32:
 ;CHECK: vmax.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -210,7 +210,7 @@ define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmaxQs8:
+;CHECK-LABEL: vmaxQs8:
 ;CHECK: vmax.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -219,7 +219,7 @@ define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vmaxQs16:
+;CHECK-LABEL: vmaxQs16:
 ;CHECK: vmax.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -228,7 +228,7 @@ define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vmaxQs32:
+;CHECK-LABEL: vmaxQs32:
 ;CHECK: vmax.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -237,7 +237,7 @@ define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmaxQu8:
+;CHECK-LABEL: vmaxQu8:
 ;CHECK: vmax.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -246,7 +246,7 @@ define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vmaxQu16:
+;CHECK-LABEL: vmaxQu16:
 ;CHECK: vmax.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -255,7 +255,7 @@ define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vmaxQu32:
+;CHECK-LABEL: vmaxQu32:
 ;CHECK: vmax.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -264,7 +264,7 @@ define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vmaxQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vmaxQf32:
+;CHECK-LABEL: vmaxQf32:
 ;CHECK: vmax.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
diff --git a/test/CodeGen/ARM/vminmaxnm.ll b/test/CodeGen/ARM/vminmaxnm.ll
new file mode 100644
index 0000000..afa73b9
--- /dev/null
+++ b/test/CodeGen/ARM/vminmaxnm.ll
@@ -0,0 +1,42 @@
+; RUN: llc < %s -mtriple armv8 -mattr=+neon | FileCheck %s
+
+define <4 x float> @vmaxnmq(<4 x float>* %A, <4 x float>* %B) nounwind {
+; CHECK: vmaxnmq
+; CHECK: vmaxnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
+  %tmp1 = load <4 x float>* %A
+  %tmp2 = load <4 x float>* %B
+  %tmp3 = call <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+  ret <4 x float> %tmp3
+}
+
+define <2 x float> @vmaxnmd(<2 x float>* %A, <2 x float>* %B) nounwind {
+; CHECK: vmaxnmd
+; CHECK: vmaxnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+  %tmp1 = load <2 x float>* %A
+  %tmp2 = load <2 x float>* %B
+  %tmp3 = call <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+  ret <2 x float> %tmp3
+}
+
+define <4 x float> @vminnmq(<4 x float>* %A, <4 x float>* %B) nounwind {
+; CHECK: vminnmq
+; CHECK: vminnm.f32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}}
+  %tmp1 = load <4 x float>* %A
+  %tmp2 = load <4 x float>* %B
+  %tmp3 = call <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
+  ret <4 x float> %tmp3
+}
+
+define <2 x float> @vminnmd(<2 x float>* %A, <2 x float>* %B) nounwind {
+; CHECK: vminnmd
+; CHECK: vminnm.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
+  %tmp1 = load <2 x float>* %A
+  %tmp2 = load <2 x float>* %B
+  %tmp3 = call <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
+  ret <2 x float> %tmp3
+}
+
+declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
+declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
+declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone
+declare <2 x float> @llvm.arm.neon.vmaxnm.v2f32(<2 x float>, <2 x float>) nounwind readnone
diff --git a/test/CodeGen/ARM/vmla.ll b/test/CodeGen/ARM/vmla.ll
index 9c6b210..caf6556 100644
--- a/test/CodeGen/ARM/vmla.ll
+++ b/test/CodeGen/ARM/vmla.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
-;CHECK: vmlai8:
+;CHECK-LABEL: vmlai8:
 ;CHECK: vmla.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
 }
 
 define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlai16:
+;CHECK-LABEL: vmlai16:
 ;CHECK: vmla.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -23,7 +23,7 @@ define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlai32:
+;CHECK-LABEL: vmlai32:
 ;CHECK: vmla.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -34,7 +34,7 @@ define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK: vmlaf32:
+;CHECK-LABEL: vmlaf32:
 ;CHECK: vmla.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -45,7 +45,7 @@ define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n
 }
 
 define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
-;CHECK: vmlaQi8:
+;CHECK-LABEL: vmlaQi8:
 ;CHECK: vmla.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -56,7 +56,7 @@ define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind
 }
 
 define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vmlaQi16:
+;CHECK-LABEL: vmlaQi16:
 ;CHECK: vmla.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -67,7 +67,7 @@ define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
 }
 
 define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vmlaQi32:
+;CHECK-LABEL: vmlaQi32:
 ;CHECK: vmla.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -78,7 +78,7 @@ define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind
 }
 
 define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK: vmlaQf32:
+;CHECK-LABEL: vmlaQf32:
 ;CHECK: vmla.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -89,7 +89,7 @@ define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C)
 }
 
 define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlals8:
+;CHECK-LABEL: vmlals8:
 ;CHECK: vmlal.s8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -102,7 +102,7 @@ define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlals16:
+;CHECK-LABEL: vmlals16:
 ;CHECK: vmlal.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -115,7 +115,7 @@ define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlals32:
+;CHECK-LABEL: vmlals32:
 ;CHECK: vmlal.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -128,7 +128,7 @@ define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlalu8:
+;CHECK-LABEL: vmlalu8:
 ;CHECK: vmlal.u8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -141,7 +141,7 @@ define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlalu16:
+;CHECK-LABEL: vmlalu16:
 ;CHECK: vmlal.u16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -154,7 +154,7 @@ define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i64> @vmlalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlalu32:
+;CHECK-LABEL: vmlalu32:
 ;CHECK: vmlal.u32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
diff --git a/test/CodeGen/ARM/vmls.ll b/test/CodeGen/ARM/vmls.ll
index 65e7fe4..61f3424 100644
--- a/test/CodeGen/ARM/vmls.ll
+++ b/test/CodeGen/ARM/vmls.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
-;CHECK: vmlsi8:
+;CHECK-LABEL: vmlsi8:
 ;CHECK: vmls.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
 }
 
 define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlsi16:
+;CHECK-LABEL: vmlsi16:
 ;CHECK: vmls.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -23,7 +23,7 @@ define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlsi32:
+;CHECK-LABEL: vmlsi32:
 ;CHECK: vmls.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -34,7 +34,7 @@ define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK: vmlsf32:
+;CHECK-LABEL: vmlsf32:
 ;CHECK: vmls.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -45,7 +45,7 @@ define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n
 }
 
 define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
-;CHECK: vmlsQi8:
+;CHECK-LABEL: vmlsQi8:
 ;CHECK: vmls.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -56,7 +56,7 @@ define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind
 }
 
 define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vmlsQi16:
+;CHECK-LABEL: vmlsQi16:
 ;CHECK: vmls.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -67,7 +67,7 @@ define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind
 }
 
 define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vmlsQi32:
+;CHECK-LABEL: vmlsQi32:
 ;CHECK: vmls.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -78,7 +78,7 @@ define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind
 }
 
 define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK: vmlsQf32:
+;CHECK-LABEL: vmlsQf32:
 ;CHECK: vmls.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -89,7 +89,7 @@ define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C)
 }
 
 define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlsls8:
+;CHECK-LABEL: vmlsls8:
 ;CHECK: vmlsl.s8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -102,7 +102,7 @@ define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlsls16:
+;CHECK-LABEL: vmlsls16:
 ;CHECK: vmlsl.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -115,7 +115,7 @@ define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlsls32:
+;CHECK-LABEL: vmlsls32:
 ;CHECK: vmlsl.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -128,7 +128,7 @@ define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind
 }
 
 define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlslu8:
+;CHECK-LABEL: vmlslu8:
 ;CHECK: vmlsl.u8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -141,7 +141,7 @@ define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlslu16:
+;CHECK-LABEL: vmlslu16:
 ;CHECK: vmlsl.u16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -154,7 +154,7 @@ define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind
 }
 
 define <2 x i64> @vmlslu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlslu32:
+;CHECK-LABEL: vmlslu32:
 ;CHECK: vmlsl.u32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll
index 0c23879..8b63138 100644
--- a/test/CodeGen/ARM/vmov.ll
+++ b/test/CodeGen/ARM/vmov.ll
@@ -1,169 +1,169 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @v_movi8() nounwind {
-;CHECK: v_movi8:
+;CHECK-LABEL: v_movi8:
 ;CHECK: vmov.i8 d{{.*}}, #0x8
 	ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
 }
 
 define <4 x i16> @v_movi16a() nounwind {
-;CHECK: v_movi16a:
+;CHECK-LABEL: v_movi16a:
 ;CHECK: vmov.i16 d{{.*}}, #0x10
 	ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
 }
 
 define <4 x i16> @v_movi16b() nounwind {
-;CHECK: v_movi16b:
+;CHECK-LABEL: v_movi16b:
 ;CHECK: vmov.i16 d{{.*}}, #0x1000
 	ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
 }
 
 define <4 x i16> @v_mvni16a() nounwind {
-;CHECK: v_mvni16a:
+;CHECK-LABEL: v_mvni16a:
 ;CHECK: vmvn.i16 d{{.*}}, #0x10
 	ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
 }
 
 define <4 x i16> @v_mvni16b() nounwind {
-;CHECK: v_mvni16b:
+;CHECK-LABEL: v_mvni16b:
 ;CHECK: vmvn.i16 d{{.*}}, #0x1000
 	ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
 }
 
 define <2 x i32> @v_movi32a() nounwind {
-;CHECK: v_movi32a:
+;CHECK-LABEL: v_movi32a:
 ;CHECK: vmov.i32 d{{.*}}, #0x20
 	ret <2 x i32> < i32 32, i32 32 >
 }
 
 define <2 x i32> @v_movi32b() nounwind {
-;CHECK: v_movi32b:
+;CHECK-LABEL: v_movi32b:
 ;CHECK: vmov.i32 d{{.*}}, #0x2000
 	ret <2 x i32> < i32 8192, i32 8192 >
 }
 
 define <2 x i32> @v_movi32c() nounwind {
-;CHECK: v_movi32c:
+;CHECK-LABEL: v_movi32c:
 ;CHECK: vmov.i32 d{{.*}}, #0x200000
 	ret <2 x i32> < i32 2097152, i32 2097152 >
 }
 
 define <2 x i32> @v_movi32d() nounwind {
-;CHECK: v_movi32d:
+;CHECK-LABEL: v_movi32d:
 ;CHECK: vmov.i32 d{{.*}}, #0x20000000
 	ret <2 x i32> < i32 536870912, i32 536870912 >
 }
 
 define <2 x i32> @v_movi32e() nounwind {
-;CHECK: v_movi32e:
+;CHECK-LABEL: v_movi32e:
 ;CHECK: vmov.i32 d{{.*}}, #0x20ff
 	ret <2 x i32> < i32 8447, i32 8447 >
 }
 
 define <2 x i32> @v_movi32f() nounwind {
-;CHECK: v_movi32f:
+;CHECK-LABEL: v_movi32f:
 ;CHECK: vmov.i32 d{{.*}}, #0x20ffff
 	ret <2 x i32> < i32 2162687, i32 2162687 >
 }
 
 define <2 x i32> @v_mvni32a() nounwind {
-;CHECK: v_mvni32a:
+;CHECK-LABEL: v_mvni32a:
 ;CHECK: vmvn.i32 d{{.*}}, #0x20
 	ret <2 x i32> < i32 4294967263, i32 4294967263 >
 }
 
 define <2 x i32> @v_mvni32b() nounwind {
-;CHECK: v_mvni32b:
+;CHECK-LABEL: v_mvni32b:
 ;CHECK: vmvn.i32 d{{.*}}, #0x2000
 	ret <2 x i32> < i32 4294959103, i32 4294959103 >
 }
 
 define <2 x i32> @v_mvni32c() nounwind {
-;CHECK: v_mvni32c:
+;CHECK-LABEL: v_mvni32c:
 ;CHECK: vmvn.i32 d{{.*}}, #0x200000
 	ret <2 x i32> < i32 4292870143, i32 4292870143 >
 }
 
 define <2 x i32> @v_mvni32d() nounwind {
-;CHECK: v_mvni32d:
+;CHECK-LABEL: v_mvni32d:
 ;CHECK: vmvn.i32 d{{.*}}, #0x20000000
 	ret <2 x i32> < i32 3758096383, i32 3758096383 >
 }
 
 define <2 x i32> @v_mvni32e() nounwind {
-;CHECK: v_mvni32e:
+;CHECK-LABEL: v_mvni32e:
 ;CHECK: vmvn.i32 d{{.*}}, #0x20ff
 	ret <2 x i32> < i32 4294958848, i32 4294958848 >
 }
 
 define <2 x i32> @v_mvni32f() nounwind {
-;CHECK: v_mvni32f:
+;CHECK-LABEL: v_mvni32f:
 ;CHECK: vmvn.i32 d{{.*}}, #0x20ffff
 	ret <2 x i32> < i32 4292804608, i32 4292804608 >
 }
 
 define <1 x i64> @v_movi64() nounwind {
-;CHECK: v_movi64:
+;CHECK-LABEL: v_movi64:
 ;CHECK: vmov.i64 d{{.*}}, #0xff0000ff0000ffff
 	ret <1 x i64> < i64 18374687574888349695 >
 }
 
 define <16 x i8> @v_movQi8() nounwind {
-;CHECK: v_movQi8:
+;CHECK-LABEL: v_movQi8:
 ;CHECK: vmov.i8 q{{.*}}, #0x8
 	ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
 }
 
 define <8 x i16> @v_movQi16a() nounwind {
-;CHECK: v_movQi16a:
+;CHECK-LABEL: v_movQi16a:
 ;CHECK: vmov.i16 q{{.*}}, #0x10
 	ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
 }
 
 define <8 x i16> @v_movQi16b() nounwind {
-;CHECK: v_movQi16b:
+;CHECK-LABEL: v_movQi16b:
 ;CHECK: vmov.i16 q{{.*}}, #0x1000
 	ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
 }
 
 define <4 x i32> @v_movQi32a() nounwind {
-;CHECK: v_movQi32a:
+;CHECK-LABEL: v_movQi32a:
 ;CHECK: vmov.i32 q{{.*}}, #0x20
 	ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
 }
 
 define <4 x i32> @v_movQi32b() nounwind {
-;CHECK: v_movQi32b:
+;CHECK-LABEL: v_movQi32b:
 ;CHECK: vmov.i32 q{{.*}}, #0x2000
 	ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
 }
 
 define <4 x i32> @v_movQi32c() nounwind {
-;CHECK: v_movQi32c:
+;CHECK-LABEL: v_movQi32c:
 ;CHECK: vmov.i32 q{{.*}}, #0x200000
 	ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
 }
 
 define <4 x i32> @v_movQi32d() nounwind {
-;CHECK: v_movQi32d:
+;CHECK-LABEL: v_movQi32d:
 ;CHECK: vmov.i32 q{{.*}}, #0x20000000
 	ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
 }
 
 define <4 x i32> @v_movQi32e() nounwind {
-;CHECK: v_movQi32e:
+;CHECK-LABEL: v_movQi32e:
 ;CHECK: vmov.i32 q{{.*}}, #0x20ff
 	ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
 }
 
 define <4 x i32> @v_movQi32f() nounwind {
-;CHECK: v_movQi32f:
+;CHECK-LABEL: v_movQi32f:
 ;CHECK: vmov.i32 q{{.*}}, #0x20ffff
 	ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
 }
 
 define <2 x i64> @v_movQi64() nounwind {
-;CHECK: v_movQi64:
+;CHECK-LABEL: v_movQi64:
 ;CHECK: vmov.i64 q{{.*}}, #0xff0000ff0000ffff
 	ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
 }
@@ -172,7 +172,7 @@ define <2 x i64> @v_movQi64() nounwind {
 %struct.int8x8_t = type { <8 x i8> }
 define void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
 entry:
-;CHECK: vdupn128:
+;CHECK-LABEL: vdupn128:
 ;CHECK: vmov.i8 d{{.*}}, #0x80
   %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
   store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, <8 x i8>* %0, align 8
@@ -181,7 +181,7 @@ entry:
 
 define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
 entry:
-;CHECK: vdupnneg75:
+;CHECK-LABEL: vdupnneg75:
 ;CHECK: vmov.i8 d{{.*}}, #0xb5
   %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
   store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, <8 x i8>* %0, align 8
@@ -189,7 +189,7 @@ entry:
 }
 
 define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
-;CHECK: vmovls8:
+;CHECK-LABEL: vmovls8:
 ;CHECK: vmovl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
@@ -197,7 +197,7 @@ define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
-;CHECK: vmovls16:
+;CHECK-LABEL: vmovls16:
 ;CHECK: vmovl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
@@ -205,7 +205,7 @@ define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
-;CHECK: vmovls32:
+;CHECK-LABEL: vmovls32:
 ;CHECK: vmovl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
@@ -213,7 +213,7 @@ define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
 }
 
 define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
-;CHECK: vmovlu8:
+;CHECK-LABEL: vmovlu8:
 ;CHECK: vmovl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
@@ -221,7 +221,7 @@ define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
-;CHECK: vmovlu16:
+;CHECK-LABEL: vmovlu16:
 ;CHECK: vmovl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
@@ -229,7 +229,7 @@ define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
-;CHECK: vmovlu32:
+;CHECK-LABEL: vmovlu32:
 ;CHECK: vmovl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
@@ -237,7 +237,7 @@ define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
 }
 
 define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
-;CHECK: vmovni16:
+;CHECK-LABEL: vmovni16:
 ;CHECK: vmovn.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = trunc <8 x i16> %tmp1 to <8 x i8>
@@ -245,7 +245,7 @@ define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
-;CHECK: vmovni32:
+;CHECK-LABEL: vmovni32:
 ;CHECK: vmovn.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
@@ -253,7 +253,7 @@ define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
-;CHECK: vmovni64:
+;CHECK-LABEL: vmovni64:
 ;CHECK: vmovn.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>
@@ -261,7 +261,7 @@ define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
-;CHECK: vqmovns16:
+;CHECK-LABEL: vqmovns16:
 ;CHECK: vqmovn.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
@@ -269,7 +269,7 @@ define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
-;CHECK: vqmovns32:
+;CHECK-LABEL: vqmovns32:
 ;CHECK: vqmovn.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
@@ -277,7 +277,7 @@ define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
-;CHECK: vqmovns64:
+;CHECK-LABEL: vqmovns64:
 ;CHECK: vqmovn.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
@@ -285,7 +285,7 @@ define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
-;CHECK: vqmovnu16:
+;CHECK-LABEL: vqmovnu16:
 ;CHECK: vqmovn.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
@@ -293,7 +293,7 @@ define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
-;CHECK: vqmovnu32:
+;CHECK-LABEL: vqmovnu32:
 ;CHECK: vqmovn.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
@@ -301,7 +301,7 @@ define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
-;CHECK: vqmovnu64:
+;CHECK-LABEL: vqmovnu64:
 ;CHECK: vqmovn.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
@@ -309,7 +309,7 @@ define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
-;CHECK: vqmovuns16:
+;CHECK-LABEL: vqmovuns16:
 ;CHECK: vqmovun.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
@@ -317,7 +317,7 @@ define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
-;CHECK: vqmovuns32:
+;CHECK-LABEL: vqmovuns32:
 ;CHECK: vqmovun.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
@@ -325,7 +325,7 @@ define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
-;CHECK: vqmovuns64:
+;CHECK-LABEL: vqmovuns64:
 ;CHECK: vqmovun.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
@@ -358,7 +358,7 @@ define void @noTruncStore(<4 x i32>* %a, <4 x i16>* %b) nounwind {
 ; rdar://10437054
 define void @v_mov_v2f32(<2 x float>* nocapture %p) nounwind {
 entry:
-;CHECK: v_mov_v2f32:
+;CHECK-LABEL: v_mov_v2f32:
 ;CHECK: vmov.f32 d{{.*}}, #-1.600000e+01
   store <2 x float> <float -1.600000e+01, float -1.600000e+01>, <2 x float>* %p, align 4
   ret void
@@ -366,7 +366,7 @@ entry:
 
 define void @v_mov_v4f32(<4 x float>* nocapture %p) nounwind {
 entry:
-;CHECK: v_mov_v4f32:
+;CHECK-LABEL: v_mov_v4f32:
 ;CHECK: vmov.f32 q{{.*}}, #3.100000e+01
   store <4 x float> <float 3.100000e+01, float 3.100000e+01, float 3.100000e+01, float 3.100000e+01>, <4 x float>* %p, align 4
   ret void
@@ -374,7 +374,7 @@ entry:
 
 define void @v_mov_v4f32_undef(<4 x float> * nocapture %p) nounwind {
 entry:
-;CHECK: v_mov_v4f32_undef:
+;CHECK-LABEL: v_mov_v4f32_undef:
 ;CHECK: vmov.f32 q{{.*}}, #1.000000e+00
   %a = load <4 x float> *%p
   %b = fadd <4 x float> %a, <float undef, float 1.0, float 1.0, float 1.0>
@@ -386,7 +386,7 @@ entry:
 ; rdar://10723651
 define void @any_extend(<4 x i1> %x, <4 x i32> %y) nounwind ssp {
 entry:
-;CHECK: any_extend
+;CHECK-LABEL: any_extend:
 ;CHECK: vmovl
   %and.i186 = zext <4 x i1> %x to <4 x i32>
   %add.i185 = sub <4 x i32> %and.i186, %y
diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll
index eb5ad8f..6210ad3 100644
--- a/test/CodeGen/ARM/vmul.ll
+++ b/test/CodeGen/ARM/vmul.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
 
 define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmuli8:
+;CHECK-LABEL: vmuli8:
 ;CHECK: vmul.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmuli16:
+;CHECK-LABEL: vmuli16:
 ;CHECK: vmul.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmuli32:
+;CHECK-LABEL: vmuli32:
 ;CHECK: vmul.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vmulf32:
+;CHECK-LABEL: vmulf32:
 ;CHECK: vmul.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -37,7 +37,7 @@ define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmulp8:
+;CHECK-LABEL: vmulp8:
 ;CHECK: vmul.p8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -46,7 +46,7 @@ define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmulQi8:
+;CHECK-LABEL: vmulQi8:
 ;CHECK: vmul.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -55,7 +55,7 @@ define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vmulQi16:
+;CHECK-LABEL: vmulQi16:
 ;CHECK: vmul.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -64,7 +64,7 @@ define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vmulQi32:
+;CHECK-LABEL: vmulQi32:
 ;CHECK: vmul.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -73,7 +73,7 @@ define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vmulQf32:
+;CHECK-LABEL: vmulQf32:
 ;CHECK: vmul.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -82,7 +82,7 @@ define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vmulQp8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmulQp8:
+;CHECK-LABEL: vmulQp8:
 ;CHECK: vmul.p8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -95,7 +95,7 @@ declare <16 x i8>  @llvm.arm.neon.vmulp.v16i8(<16 x i8>, <16 x i8>) nounwind rea
 
 define arm_aapcs_vfpcc <2 x float> @test_vmul_lanef32(<2 x float> %arg0_float32x2_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
 entry:
-; CHECK: test_vmul_lanef32:
+; CHECK-LABEL: test_vmul_lanef32:
 ; CHECK: vmul.f32 d0, d0, d1[0]
   %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <2 x i32> zeroinitializer ; <<2 x float>> [#uses=1]
   %1 = fmul <2 x float> %0, %arg0_float32x2_t     ; <<2 x float>> [#uses=1]
@@ -104,7 +104,7 @@ entry:
 
 define arm_aapcs_vfpcc <4 x i16> @test_vmul_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
 entry:
-; CHECK: test_vmul_lanes16:
+; CHECK-LABEL: test_vmul_lanes16:
 ; CHECK: vmul.i16 d0, d0, d1[1]
   %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses$
   %1 = mul <4 x i16> %0, %arg0_int16x4_t          ; <<4 x i16>> [#uses=1]
@@ -113,7 +113,7 @@ entry:
 
 define arm_aapcs_vfpcc <2 x i32> @test_vmul_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
 entry:
-; CHECK: test_vmul_lanes32:
+; CHECK-LABEL: test_vmul_lanes32:
 ; CHECK: vmul.i32 d0, d0, d1[1]
   %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
   %1 = mul <2 x i32> %0, %arg0_int32x2_t          ; <<2 x i32>> [#uses=1]
@@ -122,7 +122,7 @@ entry:
 
 define arm_aapcs_vfpcc <4 x float> @test_vmulQ_lanef32(<4 x float> %arg0_float32x4_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
 entry:
-; CHECK: test_vmulQ_lanef32:
+; CHECK-LABEL: test_vmulQ_lanef32:
 ; CHECK: vmul.f32 q0, q0, d2[1]
   %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>$
   %1 = fmul <4 x float> %0, %arg0_float32x4_t     ; <<4 x float>> [#uses=1]
@@ -131,7 +131,7 @@ entry:
 
 define arm_aapcs_vfpcc <8 x i16> @test_vmulQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
 entry:
-; CHECK: test_vmulQ_lanes16:
+; CHECK-LABEL: test_vmulQ_lanes16:
 ; CHECK: vmul.i16 q0, q0, d2[1]
   %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
   %1 = mul <8 x i16> %0, %arg0_int16x8_t          ; <<8 x i16>> [#uses=1]
@@ -140,7 +140,7 @@ entry:
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmulQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
 entry:
-; CHECK: test_vmulQ_lanes32:
+; CHECK-LABEL: test_vmulQ_lanes32:
 ; CHECK: vmul.i32 q0, q0, d2[1]
   %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses$
   %1 = mul <4 x i32> %0, %arg0_int32x4_t          ; <<4 x i32>> [#uses=1]
@@ -148,7 +148,7 @@ entry:
 }
 
 define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmulls8:
+;CHECK-LABEL: vmulls8:
 ;CHECK: vmull.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -159,7 +159,7 @@ define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vmulls8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmulls8_int:
+;CHECK-LABEL: vmulls8_int:
 ;CHECK: vmull.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -168,7 +168,7 @@ define <8 x i16> @vmulls8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmulls16:
+;CHECK-LABEL: vmulls16:
 ;CHECK: vmull.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -179,7 +179,7 @@ define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vmulls16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmulls16_int:
+;CHECK-LABEL: vmulls16_int:
 ;CHECK: vmull.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -188,7 +188,7 @@ define <4 x i32> @vmulls16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmulls32:
+;CHECK-LABEL: vmulls32:
 ;CHECK: vmull.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -199,7 +199,7 @@ define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vmulls32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmulls32_int:
+;CHECK-LABEL: vmulls32_int:
 ;CHECK: vmull.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -208,7 +208,7 @@ define <2 x i64> @vmulls32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmullu8:
+;CHECK-LABEL: vmullu8:
 ;CHECK: vmull.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -219,7 +219,7 @@ define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vmullu8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmullu8_int:
+;CHECK-LABEL: vmullu8_int:
 ;CHECK: vmull.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -228,7 +228,7 @@ define <8 x i16> @vmullu8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmullu16:
+;CHECK-LABEL: vmullu16:
 ;CHECK: vmull.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -239,7 +239,7 @@ define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vmullu16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmullu16_int:
+;CHECK-LABEL: vmullu16_int:
 ;CHECK: vmull.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -248,7 +248,7 @@ define <4 x i32> @vmullu16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmullu32:
+;CHECK-LABEL: vmullu32:
 ;CHECK: vmull.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -259,7 +259,7 @@ define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vmullu32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmullu32_int:
+;CHECK-LABEL: vmullu32_int:
 ;CHECK: vmull.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -268,7 +268,7 @@ define <2 x i64> @vmullu32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmullp8:
+;CHECK-LABEL: vmullp8:
 ;CHECK: vmull.p8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -441,7 +441,7 @@ define <2 x i64> @vmull_extvec_u32(<2 x i32> %arg) nounwind {
 ; rdar://9197392
 define void @distribute(i16* %dst, i8* %src, i32 %mul) nounwind {
 entry:
-; CHECK: distribute:
+; CHECK-LABEL: distribute:
 ; CHECK: vmull.u8 [[REG1:(q[0-9]+)]], d{{.*}}, [[REG2:(d[0-9]+)]]
 ; CHECK: vmlal.u8 [[REG1]], d{{.*}}, [[REG2]]
   %0 = trunc i32 %mul to i8
diff --git a/test/CodeGen/ARM/vneg.ll b/test/CodeGen/ARM/vneg.ll
index 4a10732..1be4f74 100644
--- a/test/CodeGen/ARM/vneg.ll
+++ b/test/CodeGen/ARM/vneg.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
-;CHECK: vnegs8:
+;CHECK-LABEL: vnegs8:
 ;CHECK: vneg.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = sub <8 x i8> zeroinitializer, %tmp1
@@ -9,7 +9,7 @@ define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
-;CHECK: vnegs16:
+;CHECK-LABEL: vnegs16:
 ;CHECK: vneg.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = sub <4 x i16> zeroinitializer, %tmp1
@@ -17,7 +17,7 @@ define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
-;CHECK: vnegs32:
+;CHECK-LABEL: vnegs32:
 ;CHECK: vneg.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = sub <2 x i32> zeroinitializer, %tmp1
@@ -25,7 +25,7 @@ define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
 }
 
 define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
-;CHECK: vnegf32:
+;CHECK-LABEL: vnegf32:
 ;CHECK: vneg.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = fsub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1
@@ -33,7 +33,7 @@ define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
 }
 
 define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
-;CHECK: vnegQs8:
+;CHECK-LABEL: vnegQs8:
 ;CHECK: vneg.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = sub <16 x i8> zeroinitializer, %tmp1
@@ -41,7 +41,7 @@ define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
-;CHECK: vnegQs16:
+;CHECK-LABEL: vnegQs16:
 ;CHECK: vneg.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = sub <8 x i16> zeroinitializer, %tmp1
@@ -49,7 +49,7 @@ define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
-;CHECK: vnegQs32:
+;CHECK-LABEL: vnegQs32:
 ;CHECK: vneg.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = sub <4 x i32> zeroinitializer, %tmp1
@@ -57,7 +57,7 @@ define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
 }
 
 define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
-;CHECK: vnegQf32:
+;CHECK-LABEL: vnegQf32:
 ;CHECK: vneg.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1
@@ -65,7 +65,7 @@ define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
 }
 
 define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind {
-;CHECK: vqnegs8:
+;CHECK-LABEL: vqnegs8:
 ;CHECK: vqneg.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1)
@@ -73,7 +73,7 @@ define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
-;CHECK: vqnegs16:
+;CHECK-LABEL: vqnegs16:
 ;CHECK: vqneg.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)
@@ -81,7 +81,7 @@ define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind {
-;CHECK: vqnegs32:
+;CHECK-LABEL: vqnegs32:
 ;CHECK: vqneg.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1)
@@ -89,7 +89,7 @@ define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind {
 }
 
 define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind {
-;CHECK: vqnegQs8:
+;CHECK-LABEL: vqnegQs8:
 ;CHECK: vqneg.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1)
@@ -97,7 +97,7 @@ define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
-;CHECK: vqnegQs16:
+;CHECK-LABEL: vqnegQs16:
 ;CHECK: vqneg.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)
@@ -105,7 +105,7 @@ define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind {
-;CHECK: vqnegQs32:
+;CHECK-LABEL: vqnegQs32:
 ;CHECK: vqneg.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1)
diff --git a/test/CodeGen/ARM/vpadal.ll b/test/CodeGen/ARM/vpadal.ll
index 7296e936..a616a8d 100644
--- a/test/CodeGen/ARM/vpadal.ll
+++ b/test/CodeGen/ARM/vpadal.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpadals8:
+;CHECK-LABEL: vpadals8:
 ;CHECK: vpadal.s8
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpadals16:
+;CHECK-LABEL: vpadals16:
 ;CHECK: vpadal.s16
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpadals32:
+;CHECK-LABEL: vpadals32:
 ;CHECK: vpadal.s32
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpadalu8:
+;CHECK-LABEL: vpadalu8:
 ;CHECK: vpadal.u8
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpadalu16:
+;CHECK-LABEL: vpadalu16:
 ;CHECK: vpadal.u16
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpadalu32:
+;CHECK-LABEL: vpadalu32:
 ;CHECK: vpadal.u32
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vpadalQs8:
+;CHECK-LABEL: vpadalQs8:
 ;CHECK: vpadal.s8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -64,7 +64,7 @@ define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vpadalQs16:
+;CHECK-LABEL: vpadalQs16:
 ;CHECK: vpadal.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -73,7 +73,7 @@ define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vpadalQs32:
+;CHECK-LABEL: vpadalQs32:
 ;CHECK: vpadal.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -82,7 +82,7 @@ define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vpadalQu8:
+;CHECK-LABEL: vpadalQu8:
 ;CHECK: vpadal.u8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vpadalQu16:
+;CHECK-LABEL: vpadalQu16:
 ;CHECK: vpadal.u16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vpadalQu32:
+;CHECK-LABEL: vpadalQu32:
 ;CHECK: vpadal.u32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <4 x i32>* %B
diff --git a/test/CodeGen/ARM/vpadd.ll b/test/CodeGen/ARM/vpadd.ll
index 1ba68f5..f84721f 100644
--- a/test/CodeGen/ARM/vpadd.ll
+++ b/test/CodeGen/ARM/vpadd.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpaddi8:
+;CHECK-LABEL: vpaddi8:
 ;CHECK: vpadd.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpaddi16:
+;CHECK-LABEL: vpaddi16:
 ;CHECK: vpadd.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpaddi32:
+;CHECK-LABEL: vpaddi32:
 ;CHECK: vpadd.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vpaddf32:
+;CHECK-LABEL: vpaddf32:
 ;CHECK: vpadd.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -43,7 +43,7 @@ declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind read
 declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
 
 define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
-;CHECK: vpaddls8:
+;CHECK-LABEL: vpaddls8:
 ;CHECK: vpaddl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1)
@@ -51,7 +51,7 @@ define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
 }
 
 define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
-;CHECK: vpaddls16:
+;CHECK-LABEL: vpaddls16:
 ;CHECK: vpaddl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1)
@@ -59,7 +59,7 @@ define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
 }
 
 define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
-;CHECK: vpaddls32:
+;CHECK-LABEL: vpaddls32:
 ;CHECK: vpaddl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1)
@@ -67,7 +67,7 @@ define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
 }
 
 define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
-;CHECK: vpaddlu8:
+;CHECK-LABEL: vpaddlu8:
 ;CHECK: vpaddl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1)
@@ -75,7 +75,7 @@ define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
 }
 
 define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
-;CHECK: vpaddlu16:
+;CHECK-LABEL: vpaddlu16:
 ;CHECK: vpaddl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1)
@@ -83,7 +83,7 @@ define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
 }
 
 define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
-;CHECK: vpaddlu32:
+;CHECK-LABEL: vpaddlu32:
 ;CHECK: vpaddl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1)
@@ -91,7 +91,7 @@ define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
 }
 
 define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
-;CHECK: vpaddlQs8:
+;CHECK-LABEL: vpaddlQs8:
 ;CHECK: vpaddl.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1)
@@ -99,7 +99,7 @@ define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
 }
 
 define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
-;CHECK: vpaddlQs16:
+;CHECK-LABEL: vpaddlQs16:
 ;CHECK: vpaddl.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1)
@@ -107,7 +107,7 @@ define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
 }
 
 define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
-;CHECK: vpaddlQs32:
+;CHECK-LABEL: vpaddlQs32:
 ;CHECK: vpaddl.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1)
@@ -115,7 +115,7 @@ define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
 }
 
 define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
-;CHECK: vpaddlQu8:
+;CHECK-LABEL: vpaddlQu8:
 ;CHECK: vpaddl.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1)
@@ -123,7 +123,7 @@ define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
 }
 
 define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
-;CHECK: vpaddlQu16:
+;CHECK-LABEL: vpaddlQu16:
 ;CHECK: vpaddl.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1)
@@ -131,7 +131,7 @@ define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
 }
 
 define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind {
-;CHECK: vpaddlQu32:
+;CHECK-LABEL: vpaddlQu32:
 ;CHECK: vpaddl.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)
diff --git a/test/CodeGen/ARM/vpminmax.ll b/test/CodeGen/ARM/vpminmax.ll
index b75bcc9..c68b319 100644
--- a/test/CodeGen/ARM/vpminmax.ll
+++ b/test/CodeGen/ARM/vpminmax.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpmins8:
+;CHECK-LABEL: vpmins8:
 ;CHECK: vpmin.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpmins16:
+;CHECK-LABEL: vpmins16:
 ;CHECK: vpmin.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpmins32:
+;CHECK-LABEL: vpmins32:
 ;CHECK: vpmin.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpminu8:
+;CHECK-LABEL: vpminu8:
 ;CHECK: vpmin.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpminu16:
+;CHECK-LABEL: vpminu16:
 ;CHECK: vpmin.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpminu32:
+;CHECK-LABEL: vpminu32:
 ;CHECK: vpmin.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -55,7 +55,7 @@ define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vpminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vpminf32:
+;CHECK-LABEL: vpminf32:
 ;CHECK: vpmin.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -74,7 +74,7 @@ declare <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32>, <2 x i32>) nounwind rea
 declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
 
 define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpmaxs8:
+;CHECK-LABEL: vpmaxs8:
 ;CHECK: vpmax.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -83,7 +83,7 @@ define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpmaxs16:
+;CHECK-LABEL: vpmaxs16:
 ;CHECK: vpmax.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -92,7 +92,7 @@ define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpmaxs32:
+;CHECK-LABEL: vpmaxs32:
 ;CHECK: vpmax.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -101,7 +101,7 @@ define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpmaxu8:
+;CHECK-LABEL: vpmaxu8:
 ;CHECK: vpmax.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -110,7 +110,7 @@ define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpmaxu16:
+;CHECK-LABEL: vpmaxu16:
 ;CHECK: vpmax.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -119,7 +119,7 @@ define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpmaxu32:
+;CHECK-LABEL: vpmaxu32:
 ;CHECK: vpmax.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -128,7 +128,7 @@ define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vpmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vpmaxf32:
+;CHECK-LABEL: vpmaxf32:
 ;CHECK: vpmax.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
diff --git a/test/CodeGen/ARM/vqadd.ll b/test/CodeGen/ARM/vqadd.ll
index a1669b6..7840766 100644
--- a/test/CodeGen/ARM/vqadd.ll
+++ b/test/CodeGen/ARM/vqadd.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqadds8:
+;CHECK-LABEL: vqadds8:
 ;CHECK: vqadd.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqadds16:
+;CHECK-LABEL: vqadds16:
 ;CHECK: vqadd.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqadds32:
+;CHECK-LABEL: vqadds32:
 ;CHECK: vqadd.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqadds64:
+;CHECK-LABEL: vqadds64:
 ;CHECK: vqadd.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqaddu8:
+;CHECK-LABEL: vqaddu8:
 ;CHECK: vqadd.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -46,7 +46,7 @@ define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqaddu16:
+;CHECK-LABEL: vqaddu16:
 ;CHECK: vqadd.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -55,7 +55,7 @@ define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqaddu32:
+;CHECK-LABEL: vqaddu32:
 ;CHECK: vqadd.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -64,7 +64,7 @@ define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqaddu64:
+;CHECK-LABEL: vqaddu64:
 ;CHECK: vqadd.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -73,7 +73,7 @@ define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqaddQs8:
+;CHECK-LABEL: vqaddQs8:
 ;CHECK: vqadd.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqaddQs16:
+;CHECK-LABEL: vqaddQs16:
 ;CHECK: vqadd.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqaddQs32:
+;CHECK-LABEL: vqaddQs32:
 ;CHECK: vqadd.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqaddQs64:
+;CHECK-LABEL: vqaddQs64:
 ;CHECK: vqadd.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -109,7 +109,7 @@ define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqaddQu8:
+;CHECK-LABEL: vqaddQu8:
 ;CHECK: vqadd.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -118,7 +118,7 @@ define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqaddQu16:
+;CHECK-LABEL: vqaddQu16:
 ;CHECK: vqadd.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -127,7 +127,7 @@ define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqaddQu32:
+;CHECK-LABEL: vqaddQu32:
 ;CHECK: vqadd.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -136,7 +136,7 @@ define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqaddQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqaddQu64:
+;CHECK-LABEL: vqaddQu64:
 ;CHECK: vqadd.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
diff --git a/test/CodeGen/ARM/vqdmul.ll b/test/CodeGen/ARM/vqdmul.ll
index 08e7d2b..a28cae9 100644
--- a/test/CodeGen/ARM/vqdmul.ll
+++ b/test/CodeGen/ARM/vqdmul.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-
 target triple = "thumbv7-elf"
 
 define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqdmulhs16:
+;CHECK-LABEL: vqdmulhs16:
 ;CHECK: vqdmulh.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -12,7 +12,7 @@ define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqdmulhs32:
+;CHECK-LABEL: vqdmulhs32:
 ;CHECK: vqdmulh.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -21,7 +21,7 @@ define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqdmulhQs16:
+;CHECK-LABEL: vqdmulhQs16:
 ;CHECK: vqdmulh.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -30,7 +30,7 @@ define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqdmulhQs32:
+;CHECK-LABEL: vqdmulhQs32:
 ;CHECK: vqdmulh.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -81,7 +81,7 @@ declare <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind re
 declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqrdmulhs16:
+;CHECK-LABEL: vqrdmulhs16:
 ;CHECK: vqrdmulh.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -90,7 +90,7 @@ define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqrdmulhs32:
+;CHECK-LABEL: vqrdmulhs32:
 ;CHECK: vqrdmulh.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -99,7 +99,7 @@ define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqrdmulhQs16:
+;CHECK-LABEL: vqrdmulhQs16:
 ;CHECK: vqrdmulh.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -108,7 +108,7 @@ define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqrdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqrdmulhQs32:
+;CHECK-LABEL: vqrdmulhQs32:
 ;CHECK: vqrdmulh.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -159,7 +159,7 @@ declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind r
 declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
 
 define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqdmulls16:
+;CHECK-LABEL: vqdmulls16:
 ;CHECK: vqdmull.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -168,7 +168,7 @@ define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vqdmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqdmulls32:
+;CHECK-LABEL: vqdmulls32:
 ;CHECK: vqdmull.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -198,7 +198,7 @@ declare <4 x i32>  @llvm.arm.neon.vqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind r
 declare <2 x i64>  @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
 
 define <4 x i32> @vqdmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vqdmlals16:
+;CHECK-LABEL: vqdmlals16:
 ;CHECK: vqdmlal.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -208,7 +208,7 @@ define <4 x i32> @vqdmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwi
 }
 
 define <2 x i64> @vqdmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vqdmlals32:
+;CHECK-LABEL: vqdmlals32:
 ;CHECK: vqdmlal.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -239,7 +239,7 @@ declare <4 x i32>  @llvm.arm.neon.vqdmlal.v4i32(<4 x i32>, <4 x i16>, <4 x i16>)
 declare <2 x i64>  @llvm.arm.neon.vqdmlal.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
 
 define <4 x i32> @vqdmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vqdmlsls16:
+;CHECK-LABEL: vqdmlsls16:
 ;CHECK: vqdmlsl.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -249,7 +249,7 @@ define <4 x i32> @vqdmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwi
 }
 
 define <2 x i64> @vqdmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vqdmlsls32:
+;CHECK-LABEL: vqdmlsls32:
 ;CHECK: vqdmlsl.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
diff --git a/test/CodeGen/ARM/vqshl.ll b/test/CodeGen/ARM/vqshl.ll
index e4d29a3..b5cd716 100644
--- a/test/CodeGen/ARM/vqshl.ll
+++ b/test/CodeGen/ARM/vqshl.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqshls8:
+;CHECK-LABEL: vqshls8:
 ;CHECK: vqshl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqshls16:
+;CHECK-LABEL: vqshls16:
 ;CHECK: vqshl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqshls32:
+;CHECK-LABEL: vqshls32:
 ;CHECK: vqshl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqshls64:
+;CHECK-LABEL: vqshls64:
 ;CHECK: vqshl.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqshlu8:
+;CHECK-LABEL: vqshlu8:
 ;CHECK: vqshl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -46,7 +46,7 @@ define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqshlu16:
+;CHECK-LABEL: vqshlu16:
 ;CHECK: vqshl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -55,7 +55,7 @@ define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqshlu32:
+;CHECK-LABEL: vqshlu32:
 ;CHECK: vqshl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -64,7 +64,7 @@ define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqshlu64:
+;CHECK-LABEL: vqshlu64:
 ;CHECK: vqshl.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -73,7 +73,7 @@ define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqshlQs8:
+;CHECK-LABEL: vqshlQs8:
 ;CHECK: vqshl.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqshlQs16:
+;CHECK-LABEL: vqshlQs16:
 ;CHECK: vqshl.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqshlQs32:
+;CHECK-LABEL: vqshlQs32:
 ;CHECK: vqshl.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqshlQs64:
+;CHECK-LABEL: vqshlQs64:
 ;CHECK: vqshl.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -109,7 +109,7 @@ define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqshlQu8:
+;CHECK-LABEL: vqshlQu8:
 ;CHECK: vqshl.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -118,7 +118,7 @@ define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqshlQu16:
+;CHECK-LABEL: vqshlQu16:
 ;CHECK: vqshl.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -127,7 +127,7 @@ define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqshlQu32:
+;CHECK-LABEL: vqshlQu32:
 ;CHECK: vqshl.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -136,7 +136,7 @@ define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqshlQu64:
+;CHECK-LABEL: vqshlQu64:
 ;CHECK: vqshl.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -145,7 +145,7 @@ define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind {
-;CHECK: vqshls_n8:
+;CHECK-LABEL: vqshls_n8:
 ;CHECK: vqshl.s8{{.*#7}}
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -153,7 +153,7 @@ define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind {
-;CHECK: vqshls_n16:
+;CHECK-LABEL: vqshls_n16:
 ;CHECK: vqshl.s16{{.*#15}}
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -161,7 +161,7 @@ define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind {
-;CHECK: vqshls_n32:
+;CHECK-LABEL: vqshls_n32:
 ;CHECK: vqshl.s32{{.*#31}}
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -169,7 +169,7 @@ define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind {
-;CHECK: vqshls_n64:
+;CHECK-LABEL: vqshls_n64:
 ;CHECK: vqshl.s64{{.*#63}}
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
@@ -177,7 +177,7 @@ define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind {
-;CHECK: vqshlu_n8:
+;CHECK-LABEL: vqshlu_n8:
 ;CHECK: vqshl.u8{{.*#7}}
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -185,7 +185,7 @@ define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind {
-;CHECK: vqshlu_n16:
+;CHECK-LABEL: vqshlu_n16:
 ;CHECK: vqshl.u16{{.*#15}}
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -193,7 +193,7 @@ define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind {
-;CHECK: vqshlu_n32:
+;CHECK-LABEL: vqshlu_n32:
 ;CHECK: vqshl.u32{{.*#31}}
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -201,7 +201,7 @@ define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind {
-;CHECK: vqshlu_n64:
+;CHECK-LABEL: vqshlu_n64:
 ;CHECK: vqshl.u64{{.*#63}}
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
@@ -209,7 +209,7 @@ define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind {
-;CHECK: vqshlsu_n8:
+;CHECK-LABEL: vqshlsu_n8:
 ;CHECK: vqshlu.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -217,7 +217,7 @@ define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind {
-;CHECK: vqshlsu_n16:
+;CHECK-LABEL: vqshlsu_n16:
 ;CHECK: vqshlu.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -225,7 +225,7 @@ define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind {
-;CHECK: vqshlsu_n32:
+;CHECK-LABEL: vqshlsu_n32:
 ;CHECK: vqshlu.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -233,7 +233,7 @@ define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind {
-;CHECK: vqshlsu_n64:
+;CHECK-LABEL: vqshlsu_n64:
 ;CHECK: vqshlu.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
@@ -241,7 +241,7 @@ define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind {
-;CHECK: vqshlQs_n8:
+;CHECK-LABEL: vqshlQs_n8:
 ;CHECK: vqshl.s8{{.*#7}}
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -249,7 +249,7 @@ define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind {
-;CHECK: vqshlQs_n16:
+;CHECK-LABEL: vqshlQs_n16:
 ;CHECK: vqshl.s16{{.*#15}}
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
@@ -257,7 +257,7 @@ define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind {
-;CHECK: vqshlQs_n32:
+;CHECK-LABEL: vqshlQs_n32:
 ;CHECK: vqshl.s32{{.*#31}}
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
@@ -265,7 +265,7 @@ define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind {
-;CHECK: vqshlQs_n64:
+;CHECK-LABEL: vqshlQs_n64:
 ;CHECK: vqshl.s64{{.*#63}}
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
@@ -273,7 +273,7 @@ define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind {
-;CHECK: vqshlQu_n8:
+;CHECK-LABEL: vqshlQu_n8:
 ;CHECK: vqshl.u8{{.*#7}}
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -281,7 +281,7 @@ define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind {
-;CHECK: vqshlQu_n16:
+;CHECK-LABEL: vqshlQu_n16:
 ;CHECK: vqshl.u16{{.*#15}}
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
@@ -289,7 +289,7 @@ define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind {
-;CHECK: vqshlQu_n32:
+;CHECK-LABEL: vqshlQu_n32:
 ;CHECK: vqshl.u32{{.*#31}}
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
@@ -297,7 +297,7 @@ define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind {
-;CHECK: vqshlQu_n64:
+;CHECK-LABEL: vqshlQu_n64:
 ;CHECK: vqshl.u64{{.*#63}}
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
@@ -305,7 +305,7 @@ define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind {
-;CHECK: vqshlQsu_n8:
+;CHECK-LABEL: vqshlQsu_n8:
 ;CHECK: vqshlu.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -313,7 +313,7 @@ define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind {
-;CHECK: vqshlQsu_n16:
+;CHECK-LABEL: vqshlQsu_n16:
 ;CHECK: vqshlu.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
@@ -321,7 +321,7 @@ define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind {
-;CHECK: vqshlQsu_n32:
+;CHECK-LABEL: vqshlQsu_n32:
 ;CHECK: vqshlu.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
@@ -329,7 +329,7 @@ define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vqshlQsu_n64(<2 x i64>* %A) nounwind {
-;CHECK: vqshlQsu_n64:
+;CHECK-LABEL: vqshlQsu_n64:
 ;CHECK: vqshlu.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
@@ -367,7 +367,7 @@ declare <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32>, <4 x i32>) nounwind
 declare <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqrshls8:
+;CHECK-LABEL: vqrshls8:
 ;CHECK: vqrshl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -376,7 +376,7 @@ define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqrshls16:
+;CHECK-LABEL: vqrshls16:
 ;CHECK: vqrshl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -385,7 +385,7 @@ define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqrshls32:
+;CHECK-LABEL: vqrshls32:
 ;CHECK: vqrshl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -394,7 +394,7 @@ define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqrshls64:
+;CHECK-LABEL: vqrshls64:
 ;CHECK: vqrshl.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -403,7 +403,7 @@ define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqrshlu8:
+;CHECK-LABEL: vqrshlu8:
 ;CHECK: vqrshl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -412,7 +412,7 @@ define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqrshlu16:
+;CHECK-LABEL: vqrshlu16:
 ;CHECK: vqrshl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -421,7 +421,7 @@ define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqrshlu32:
+;CHECK-LABEL: vqrshlu32:
 ;CHECK: vqrshl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -430,7 +430,7 @@ define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqrshlu64:
+;CHECK-LABEL: vqrshlu64:
 ;CHECK: vqrshl.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -439,7 +439,7 @@ define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqrshlQs8:
+;CHECK-LABEL: vqrshlQs8:
 ;CHECK: vqrshl.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -448,7 +448,7 @@ define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqrshlQs16:
+;CHECK-LABEL: vqrshlQs16:
 ;CHECK: vqrshl.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -457,7 +457,7 @@ define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqrshlQs32:
+;CHECK-LABEL: vqrshlQs32:
 ;CHECK: vqrshl.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -466,7 +466,7 @@ define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqrshlQs64:
+;CHECK-LABEL: vqrshlQs64:
 ;CHECK: vqrshl.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -475,7 +475,7 @@ define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqrshlQu8:
+;CHECK-LABEL: vqrshlQu8:
 ;CHECK: vqrshl.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -484,7 +484,7 @@ define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqrshlQu16:
+;CHECK-LABEL: vqrshlQu16:
 ;CHECK: vqrshl.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -493,7 +493,7 @@ define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqrshlQu32:
+;CHECK-LABEL: vqrshlQu32:
 ;CHECK: vqrshl.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -502,7 +502,7 @@ define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqrshlQu64:
+;CHECK-LABEL: vqrshlQu64:
 ;CHECK: vqrshl.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
diff --git a/test/CodeGen/ARM/vqshrn.ll b/test/CodeGen/ARM/vqshrn.ll
index 5da7943..4abae70 100644
--- a/test/CodeGen/ARM/vqshrn.ll
+++ b/test/CodeGen/ARM/vqshrn.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vqshrns8:
+;CHECK-LABEL: vqshrns8:
 ;CHECK: vqshrn.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -9,7 +9,7 @@ define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vqshrns16:
+;CHECK-LABEL: vqshrns16:
 ;CHECK: vqshrn.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -17,7 +17,7 @@ define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vqshrns32:
+;CHECK-LABEL: vqshrns32:
 ;CHECK: vqshrn.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -25,7 +25,7 @@ define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
-;CHECK: vqshrnu8:
+;CHECK-LABEL: vqshrnu8:
 ;CHECK: vqshrn.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -33,7 +33,7 @@ define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
-;CHECK: vqshrnu16:
+;CHECK-LABEL: vqshrnu16:
 ;CHECK: vqshrn.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -41,7 +41,7 @@ define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
-;CHECK: vqshrnu32:
+;CHECK-LABEL: vqshrnu32:
 ;CHECK: vqshrn.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -49,7 +49,7 @@ define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
-;CHECK: vqshruns8:
+;CHECK-LABEL: vqshruns8:
 ;CHECK: vqshrun.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -57,7 +57,7 @@ define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
-;CHECK: vqshruns16:
+;CHECK-LABEL: vqshruns16:
 ;CHECK: vqshrun.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -65,7 +65,7 @@ define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind {
-;CHECK: vqshruns32:
+;CHECK-LABEL: vqshruns32:
 ;CHECK: vqshrun.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -85,7 +85,7 @@ declare <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind
 declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vqrshrns8:
+;CHECK-LABEL: vqrshrns8:
 ;CHECK: vqrshrn.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -93,7 +93,7 @@ define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vqrshrns16:
+;CHECK-LABEL: vqrshrns16:
 ;CHECK: vqrshrn.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -101,7 +101,7 @@ define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vqrshrns32:
+;CHECK-LABEL: vqrshrns32:
 ;CHECK: vqrshrn.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -109,7 +109,7 @@ define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
-;CHECK: vqrshrnu8:
+;CHECK-LABEL: vqrshrnu8:
 ;CHECK: vqrshrn.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -117,7 +117,7 @@ define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
-;CHECK: vqrshrnu16:
+;CHECK-LABEL: vqrshrnu16:
 ;CHECK: vqrshrn.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -125,7 +125,7 @@ define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
-;CHECK: vqrshrnu32:
+;CHECK-LABEL: vqrshrnu32:
 ;CHECK: vqrshrn.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -133,7 +133,7 @@ define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
-;CHECK: vqrshruns8:
+;CHECK-LABEL: vqrshruns8:
 ;CHECK: vqrshrun.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -141,7 +141,7 @@ define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
-;CHECK: vqrshruns16:
+;CHECK-LABEL: vqrshruns16:
 ;CHECK: vqrshrun.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -149,7 +149,7 @@ define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind {
-;CHECK: vqrshruns32:
+;CHECK-LABEL: vqrshruns32:
 ;CHECK: vqrshrun.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
diff --git a/test/CodeGen/ARM/vqsub.ll b/test/CodeGen/ARM/vqsub.ll
index 4231fca..90bc349 100644
--- a/test/CodeGen/ARM/vqsub.ll
+++ b/test/CodeGen/ARM/vqsub.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqsubs8:
+;CHECK-LABEL: vqsubs8:
 ;CHECK: vqsub.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqsubs16:
+;CHECK-LABEL: vqsubs16:
 ;CHECK: vqsub.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqsubs32:
+;CHECK-LABEL: vqsubs32:
 ;CHECK: vqsub.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqsubs64:
+;CHECK-LABEL: vqsubs64:
 ;CHECK: vqsub.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqsubu8:
+;CHECK-LABEL: vqsubu8:
 ;CHECK: vqsub.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -46,7 +46,7 @@ define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqsubu16:
+;CHECK-LABEL: vqsubu16:
 ;CHECK: vqsub.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -55,7 +55,7 @@ define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqsubu32:
+;CHECK-LABEL: vqsubu32:
 ;CHECK: vqsub.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -64,7 +64,7 @@ define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqsubu64:
+;CHECK-LABEL: vqsubu64:
 ;CHECK: vqsub.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -73,7 +73,7 @@ define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqsubQs8:
+;CHECK-LABEL: vqsubQs8:
 ;CHECK: vqsub.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqsubQs16:
+;CHECK-LABEL: vqsubQs16:
 ;CHECK: vqsub.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqsubQs32:
+;CHECK-LABEL: vqsubQs32:
 ;CHECK: vqsub.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqsubQs64:
+;CHECK-LABEL: vqsubQs64:
 ;CHECK: vqsub.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -109,7 +109,7 @@ define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqsubQu8:
+;CHECK-LABEL: vqsubQu8:
 ;CHECK: vqsub.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -118,7 +118,7 @@ define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqsubQu16:
+;CHECK-LABEL: vqsubQu16:
 ;CHECK: vqsub.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -127,7 +127,7 @@ define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqsubQu32:
+;CHECK-LABEL: vqsubQu32:
 ;CHECK: vqsub.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -136,7 +136,7 @@ define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vqsubQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqsubQu64:
+;CHECK-LABEL: vqsubQu64:
 ;CHECK: vqsub.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
diff --git a/test/CodeGen/ARM/vrec.ll b/test/CodeGen/ARM/vrec.ll
index 99989e9..c0deca9 100644
--- a/test/CodeGen/ARM/vrec.ll
+++ b/test/CodeGen/ARM/vrec.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind {
-;CHECK: vrecpei32:
+;CHECK-LABEL: vrecpei32:
 ;CHECK: vrecpe.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
@@ -9,7 +9,7 @@ define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind {
 }
 
 define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind {
-;CHECK: vrecpeQi32:
+;CHECK-LABEL: vrecpeQi32:
 ;CHECK: vrecpe.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
@@ -17,7 +17,7 @@ define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x float> @vrecpef32(<2 x float>* %A) nounwind {
-;CHECK: vrecpef32:
+;CHECK-LABEL: vrecpef32:
 ;CHECK: vrecpe.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
@@ -25,7 +25,7 @@ define <2 x float> @vrecpef32(<2 x float>* %A) nounwind {
 }
 
 define <4 x float> @vrecpeQf32(<4 x float>* %A) nounwind {
-;CHECK: vrecpeQf32:
+;CHECK-LABEL: vrecpeQf32:
 ;CHECK: vrecpe.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
@@ -39,7 +39,7 @@ declare <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float>) nounwind readnone
 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
 
 define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vrecpsf32:
+;CHECK-LABEL: vrecpsf32:
 ;CHECK: vrecps.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -48,7 +48,7 @@ define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <4 x float> @vrecpsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vrecpsQf32:
+;CHECK-LABEL: vrecpsQf32:
 ;CHECK: vrecps.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -60,7 +60,7 @@ declare <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float>, <2 x float>) nounwi
 declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
 
 define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind {
-;CHECK: vrsqrtei32:
+;CHECK-LABEL: vrsqrtei32:
 ;CHECK: vrsqrte.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
@@ -68,7 +68,7 @@ define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind {
 }
 
 define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind {
-;CHECK: vrsqrteQi32:
+;CHECK-LABEL: vrsqrteQi32:
 ;CHECK: vrsqrte.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
@@ -76,7 +76,7 @@ define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind {
-;CHECK: vrsqrtef32:
+;CHECK-LABEL: vrsqrtef32:
 ;CHECK: vrsqrte.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
@@ -84,7 +84,7 @@ define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind {
 }
 
 define <4 x float> @vrsqrteQf32(<4 x float>* %A) nounwind {
-;CHECK: vrsqrteQf32:
+;CHECK-LABEL: vrsqrteQf32:
 ;CHECK: vrsqrte.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
@@ -98,7 +98,7 @@ declare <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float>) nounwind readnone
 declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
 
 define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vrsqrtsf32:
+;CHECK-LABEL: vrsqrtsf32:
 ;CHECK: vrsqrts.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -107,7 +107,7 @@ define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <4 x float> @vrsqrtsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vrsqrtsQf32:
+;CHECK-LABEL: vrsqrtsQf32:
 ;CHECK: vrsqrts.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
diff --git a/test/CodeGen/ARM/vrev.ll b/test/CodeGen/ARM/vrev.ll
index 122ec03..b6da694 100644
--- a/test/CodeGen/ARM/vrev.ll
+++ b/test/CodeGen/ARM/vrev.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev64D8:
+;CHECK-LABEL: test_vrev64D8:
 ;CHECK: vrev64.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
@@ -9,7 +9,7 @@ define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
-;CHECK: test_vrev64D16:
+;CHECK-LABEL: test_vrev64D16:
 ;CHECK: vrev64.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
@@ -17,7 +17,7 @@ define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
-;CHECK: test_vrev64D32:
+;CHECK-LABEL: test_vrev64D32:
 ;CHECK: vrev64.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
@@ -25,7 +25,7 @@ define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
 }
 
 define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
-;CHECK: test_vrev64Df:
+;CHECK-LABEL: test_vrev64Df:
 ;CHECK: vrev64.32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
@@ -33,7 +33,7 @@ define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
 }
 
 define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
-;CHECK: test_vrev64Q8:
+;CHECK-LABEL: test_vrev64Q8:
 ;CHECK: vrev64.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
@@ -41,7 +41,7 @@ define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
-;CHECK: test_vrev64Q16:
+;CHECK-LABEL: test_vrev64Q16:
 ;CHECK: vrev64.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
@@ -49,7 +49,7 @@ define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
-;CHECK: test_vrev64Q32:
+;CHECK-LABEL: test_vrev64Q32:
 ;CHECK: vrev64.32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
@@ -57,7 +57,7 @@ define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
 }
 
 define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
-;CHECK: test_vrev64Qf:
+;CHECK-LABEL: test_vrev64Qf:
 ;CHECK: vrev64.32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
@@ -65,7 +65,7 @@ define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
 }
 
 define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev32D8:
+;CHECK-LABEL: test_vrev32D8:
 ;CHECK: vrev32.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
@@ -73,7 +73,7 @@ define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
-;CHECK: test_vrev32D16:
+;CHECK-LABEL: test_vrev32D16:
 ;CHECK: vrev32.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
@@ -81,7 +81,7 @@ define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
 }
 
 define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
-;CHECK: test_vrev32Q8:
+;CHECK-LABEL: test_vrev32Q8:
 ;CHECK: vrev32.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
@@ -89,7 +89,7 @@ define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
-;CHECK: test_vrev32Q16:
+;CHECK-LABEL: test_vrev32Q16:
 ;CHECK: vrev32.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
@@ -97,7 +97,7 @@ define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
 }
 
 define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev16D8:
+;CHECK-LABEL: test_vrev16D8:
 ;CHECK: vrev16.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
@@ -105,7 +105,7 @@ define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
 }
 
 define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
-;CHECK: test_vrev16Q8:
+;CHECK-LABEL: test_vrev16Q8:
 ;CHECK: vrev16.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
@@ -115,7 +115,7 @@ define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
 ; Undef shuffle indices should not prevent matching to VREV:
 
 define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev64D8_undef:
+;CHECK-LABEL: test_vrev64D8_undef:
 ;CHECK: vrev64.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
@@ -123,7 +123,7 @@ define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
-;CHECK: test_vrev32Q16_undef:
+;CHECK-LABEL: test_vrev32Q16_undef:
 ;CHECK: vrev32.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
@@ -133,7 +133,7 @@ define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
 ; A vcombine feeding a VREV should not obscure things.  Radar 8597007.
 
 define void @test_with_vcombine(<4 x float>* %v) nounwind {
-;CHECK: test_with_vcombine:
+;CHECK-LABEL: test_with_vcombine:
 ;CHECK-NOT: vext
 ;CHECK: vrev64.32
   %tmp1 = load <4 x float>* %v, align 16
@@ -151,7 +151,7 @@ define void @test_with_vcombine(<4 x float>* %v) nounwind {
 ; The type <2 x i16> is legalized to <2 x i32> and need to be trunc-stored
 ; to <2 x i16> when stored to memory.
 define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
-; CHECK: test_vrev64:
+; CHECK-LABEL: test_vrev64:
 ; CHECK: vst1.32
 entry:
   %0 = bitcast <4 x i16>* %source to <8 x i16>*
diff --git a/test/CodeGen/ARM/vselect_imax.ll b/test/CodeGen/ARM/vselect_imax.ll
index 7e79d6c..9ea56a4 100644
--- a/test/CodeGen/ARM/vselect_imax.ll
+++ b/test/CodeGen/ARM/vselect_imax.ll
@@ -1,3 +1,4 @@
+; RUN: opt < %s  -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 ; Make sure that ARM backend with NEON handles vselect.
 
@@ -14,17 +15,14 @@ define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) {
 ; lowering we also need to adjust the cost.
 %T0_10 = type <16 x i16>
 %T1_10 = type <16 x i1>
-; CHECK: func_blend10:
+; CHECK-LABEL: func_blend10:
 define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2,
                            %T1_10* %blend, %T0_10* %storeaddr) {
   %v0 = load %T0_10* %loadaddr
   %v1 = load %T0_10* %loadaddr2
   %c = icmp slt %T0_10 %v0, %v1
-; CHECK: vst1
-; CHECK: vst1
-; CHECK: vst1
-; CHECK: vst1
-; CHECK: vld
+; CHECK: vbsl
+; CHECK: vbsl
 ; COST: func_blend10
 ; COST: cost of 40 {{.*}} select
   %r = select %T1_10 %c, %T0_10 %v0, %T0_10 %v1
@@ -33,16 +31,14 @@ define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2,
 }
 %T0_14 = type <8 x i32>
 %T1_14 = type <8 x i1>
-; CHECK: func_blend14:
+; CHECK-LABEL: func_blend14:
 define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2,
                            %T1_14* %blend, %T0_14* %storeaddr) {
   %v0 = load %T0_14* %loadaddr
   %v1 = load %T0_14* %loadaddr2
   %c = icmp slt %T0_14 %v0, %v1
-; CHECK: strb
-; CHECK: strb
-; CHECK: strb
-; CHECK: strb
+; CHECK: vbsl
+; CHECK: vbsl
 ; COST: func_blend14
 ; COST: cost of 41 {{.*}} select
   %r = select %T1_14 %c, %T0_14 %v0, %T0_14 %v1
@@ -51,16 +47,14 @@ define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2,
 }
 %T0_15 = type <16 x i32>
 %T1_15 = type <16 x i1>
-; CHECK: func_blend15:
+; CHECK-LABEL: func_blend15:
 define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2,
                            %T1_15* %blend, %T0_15* %storeaddr) {
+; CHECK: vbsl
+; CHECK: vbsl
   %v0 = load %T0_15* %loadaddr
   %v1 = load %T0_15* %loadaddr2
   %c = icmp slt %T0_15 %v0, %v1
-; CHECK: strb
-; CHECK: strb
-; CHECK: strb
-; CHECK: strb
 ; COST: func_blend15
 ; COST: cost of 82 {{.*}} select
   %r = select %T1_15 %c, %T0_15 %v0, %T0_15 %v1
@@ -69,16 +63,14 @@ define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2,
 }
 %T0_18 = type <4 x i64>
 %T1_18 = type <4 x i1>
-; CHECK: func_blend18:
+; CHECK-LABEL: func_blend18:
 define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2,
                            %T1_18* %blend, %T0_18* %storeaddr) {
+; CHECK: vbsl
+; CHECK: vbsl
   %v0 = load %T0_18* %loadaddr
   %v1 = load %T0_18* %loadaddr2
   %c = icmp slt %T0_18 %v0, %v1
-; CHECK: strh
-; CHECK: strh
-; CHECK: strh
-; CHECK: strh
 ; COST: func_blend18
 ; COST: cost of 19 {{.*}} select
   %r = select %T1_18 %c, %T0_18 %v0, %T0_18 %v1
@@ -87,16 +79,16 @@ define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2,
 }
 %T0_19 = type <8 x i64>
 %T1_19 = type <8 x i1>
-; CHECK: func_blend19:
+; CHECK-LABEL: func_blend19:
 define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2,
                            %T1_19* %blend, %T0_19* %storeaddr) {
+; CHECK: vbsl
+; CHECK: vbsl
+; CHECK: vbsl
+; CHECK: vbsl
   %v0 = load %T0_19* %loadaddr
   %v1 = load %T0_19* %loadaddr2
   %c = icmp slt %T0_19 %v0, %v1
-; CHECK: strb
-; CHECK: strb
-; CHECK: strb
-; CHECK: strb
 ; COST: func_blend19
 ; COST: cost of 50 {{.*}} select
   %r = select %T1_19 %c, %T0_19 %v0, %T0_19 %v1
@@ -105,16 +97,20 @@ define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2,
 }
 %T0_20 = type <16 x i64>
 %T1_20 = type <16 x i1>
-; CHECK: func_blend20:
+; CHECK-LABEL: func_blend20:
 define void @func_blend20(%T0_20* %loadaddr, %T0_20* %loadaddr2,
                            %T1_20* %blend, %T0_20* %storeaddr) {
+; CHECK: vbsl
+; CHECK: vbsl
+; CHECK: vbsl
+; CHECK: vbsl
+; CHECK: vbsl
+; CHECK: vbsl
+; CHECK: vbsl
+; CHECK: vbsl
   %v0 = load %T0_20* %loadaddr
   %v1 = load %T0_20* %loadaddr2
   %c = icmp slt %T0_20 %v0, %v1
-; CHECK: strb
-; CHECK: strb
-; CHECK: strb
-; CHECK: strb
 ; COST: func_blend20
 ; COST: cost of 100 {{.*}} select
   %r = select %T1_20 %c, %T0_20 %v0, %T0_20 %v1
diff --git a/test/CodeGen/ARM/vshift.ll b/test/CodeGen/ARM/vshift.ll
index f3cbec7..de380d3 100644
--- a/test/CodeGen/ARM/vshift.ll
+++ b/test/CodeGen/ARM/vshift.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vshls8:
+;CHECK-LABEL: vshls8:
 ;CHECK: vshl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vshls16:
+;CHECK-LABEL: vshls16:
 ;CHECK: vshl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vshls32:
+;CHECK-LABEL: vshls32:
 ;CHECK: vshl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vshls64:
+;CHECK-LABEL: vshls64:
 ;CHECK: vshl.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
-;CHECK: vshli8:
+;CHECK-LABEL: vshli8:
 ;CHECK: vshl.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
@@ -45,7 +45,7 @@ define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
-;CHECK: vshli16:
+;CHECK-LABEL: vshli16:
 ;CHECK: vshl.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = shl <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >
@@ -53,7 +53,7 @@ define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
-;CHECK: vshli32:
+;CHECK-LABEL: vshli32:
 ;CHECK: vshl.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = shl <2 x i32> %tmp1, < i32 31, i32 31 >
@@ -61,7 +61,7 @@ define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
-;CHECK: vshli64:
+;CHECK-LABEL: vshli64:
 ;CHECK: vshl.i64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = shl <1 x i64> %tmp1, < i64 63 >
@@ -69,7 +69,7 @@ define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vshlQs8:
+;CHECK-LABEL: vshlQs8:
 ;CHECK: vshl.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -78,7 +78,7 @@ define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vshlQs16:
+;CHECK-LABEL: vshlQs16:
 ;CHECK: vshl.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -87,7 +87,7 @@ define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vshlQs32:
+;CHECK-LABEL: vshlQs32:
 ;CHECK: vshl.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -96,7 +96,7 @@ define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vshlQs64:
+;CHECK-LABEL: vshlQs64:
 ;CHECK: vshl.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -105,7 +105,7 @@ define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
-;CHECK: vshlQi8:
+;CHECK-LABEL: vshlQi8:
 ;CHECK: vshl.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = shl <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
@@ -113,7 +113,7 @@ define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
-;CHECK: vshlQi16:
+;CHECK-LABEL: vshlQi16:
 ;CHECK: vshl.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = shl <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
@@ -121,7 +121,7 @@ define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
-;CHECK: vshlQi32:
+;CHECK-LABEL: vshlQi32:
 ;CHECK: vshl.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = shl <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >
@@ -129,7 +129,7 @@ define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
-;CHECK: vshlQi64:
+;CHECK-LABEL: vshlQi64:
 ;CHECK: vshl.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 >
@@ -137,7 +137,7 @@ define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vlshru8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vlshru8:
+;CHECK-LABEL: vlshru8:
 ;CHECK: vneg.s8
 ;CHECK: vshl.u8
 	%tmp1 = load <8 x i8>* %A
@@ -147,7 +147,7 @@ define <8 x i8> @vlshru8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vlshru16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vlshru16:
+;CHECK-LABEL: vlshru16:
 ;CHECK: vneg.s16
 ;CHECK: vshl.u16
 	%tmp1 = load <4 x i16>* %A
@@ -157,7 +157,7 @@ define <4 x i16> @vlshru16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vlshru32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vlshru32:
+;CHECK-LABEL: vlshru32:
 ;CHECK: vneg.s32
 ;CHECK: vshl.u32
 	%tmp1 = load <2 x i32>* %A
@@ -167,7 +167,7 @@ define <2 x i32> @vlshru32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vlshru64:
+;CHECK-LABEL: vlshru64:
 ;CHECK: vsub.i64
 ;CHECK: vshl.u64
 	%tmp1 = load <1 x i64>* %A
@@ -177,7 +177,7 @@ define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind {
-;CHECK: vlshri8:
+;CHECK-LABEL: vlshri8:
 ;CHECK: vshr.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = lshr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
@@ -185,7 +185,7 @@ define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind {
-;CHECK: vlshri16:
+;CHECK-LABEL: vlshri16:
 ;CHECK: vshr.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = lshr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
@@ -193,7 +193,7 @@ define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind {
-;CHECK: vlshri32:
+;CHECK-LABEL: vlshri32:
 ;CHECK: vshr.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = lshr <2 x i32> %tmp1, < i32 32, i32 32 >
@@ -201,7 +201,7 @@ define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vlshri64(<1 x i64>* %A) nounwind {
-;CHECK: vlshri64:
+;CHECK-LABEL: vlshri64:
 ;CHECK: vshr.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = lshr <1 x i64> %tmp1, < i64 64 >
@@ -209,7 +209,7 @@ define <1 x i64> @vlshri64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vlshrQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vlshrQu8:
+;CHECK-LABEL: vlshrQu8:
 ;CHECK: vneg.s8
 ;CHECK: vshl.u8
 	%tmp1 = load <16 x i8>* %A
@@ -219,7 +219,7 @@ define <16 x i8> @vlshrQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vlshrQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vlshrQu16:
+;CHECK-LABEL: vlshrQu16:
 ;CHECK: vneg.s16
 ;CHECK: vshl.u16
 	%tmp1 = load <8 x i16>* %A
@@ -229,7 +229,7 @@ define <8 x i16> @vlshrQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vlshrQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vlshrQu32:
+;CHECK-LABEL: vlshrQu32:
 ;CHECK: vneg.s32
 ;CHECK: vshl.u32
 	%tmp1 = load <4 x i32>* %A
@@ -239,7 +239,7 @@ define <4 x i32> @vlshrQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vlshrQu64:
+;CHECK-LABEL: vlshrQu64:
 ;CHECK: vsub.i64
 ;CHECK: vshl.u64
 	%tmp1 = load <2 x i64>* %A
@@ -249,7 +249,7 @@ define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind {
-;CHECK: vlshrQi8:
+;CHECK-LABEL: vlshrQi8:
 ;CHECK: vshr.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = lshr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
@@ -257,7 +257,7 @@ define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind {
-;CHECK: vlshrQi16:
+;CHECK-LABEL: vlshrQi16:
 ;CHECK: vshr.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = lshr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
@@ -265,7 +265,7 @@ define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind {
-;CHECK: vlshrQi32:
+;CHECK-LABEL: vlshrQi32:
 ;CHECK: vshr.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = lshr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
@@ -273,7 +273,7 @@ define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vlshrQi64(<2 x i64>* %A) nounwind {
-;CHECK: vlshrQi64:
+;CHECK-LABEL: vlshrQi64:
 ;CHECK: vshr.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = lshr <2 x i64> %tmp1, < i64 64, i64 64 >
@@ -288,7 +288,7 @@ entry:
 }
 
 define <8 x i8> @vashrs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vashrs8:
+;CHECK-LABEL: vashrs8:
 ;CHECK: vneg.s8
 ;CHECK: vshl.s8
 	%tmp1 = load <8 x i8>* %A
@@ -298,7 +298,7 @@ define <8 x i8> @vashrs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vashrs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vashrs16:
+;CHECK-LABEL: vashrs16:
 ;CHECK: vneg.s16
 ;CHECK: vshl.s16
 	%tmp1 = load <4 x i16>* %A
@@ -308,7 +308,7 @@ define <4 x i16> @vashrs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vashrs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vashrs32:
+;CHECK-LABEL: vashrs32:
 ;CHECK: vneg.s32
 ;CHECK: vshl.s32
 	%tmp1 = load <2 x i32>* %A
@@ -318,7 +318,7 @@ define <2 x i32> @vashrs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vashrs64:
+;CHECK-LABEL: vashrs64:
 ;CHECK: vsub.i64
 ;CHECK: vshl.s64
 	%tmp1 = load <1 x i64>* %A
@@ -328,7 +328,7 @@ define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vashri8(<8 x i8>* %A) nounwind {
-;CHECK: vashri8:
+;CHECK-LABEL: vashri8:
 ;CHECK: vshr.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = ashr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
@@ -336,7 +336,7 @@ define <8 x i8> @vashri8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vashri16(<4 x i16>* %A) nounwind {
-;CHECK: vashri16:
+;CHECK-LABEL: vashri16:
 ;CHECK: vshr.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = ashr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
@@ -344,7 +344,7 @@ define <4 x i16> @vashri16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vashri32(<2 x i32>* %A) nounwind {
-;CHECK: vashri32:
+;CHECK-LABEL: vashri32:
 ;CHECK: vshr.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = ashr <2 x i32> %tmp1, < i32 32, i32 32 >
@@ -352,7 +352,7 @@ define <2 x i32> @vashri32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vashri64(<1 x i64>* %A) nounwind {
-;CHECK: vashri64:
+;CHECK-LABEL: vashri64:
 ;CHECK: vshr.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = ashr <1 x i64> %tmp1, < i64 64 >
@@ -360,7 +360,7 @@ define <1 x i64> @vashri64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vashrQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vashrQs8:
+;CHECK-LABEL: vashrQs8:
 ;CHECK: vneg.s8
 ;CHECK: vshl.s8
 	%tmp1 = load <16 x i8>* %A
@@ -370,7 +370,7 @@ define <16 x i8> @vashrQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vashrQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vashrQs16:
+;CHECK-LABEL: vashrQs16:
 ;CHECK: vneg.s16
 ;CHECK: vshl.s16
 	%tmp1 = load <8 x i16>* %A
@@ -380,7 +380,7 @@ define <8 x i16> @vashrQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vashrQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vashrQs32:
+;CHECK-LABEL: vashrQs32:
 ;CHECK: vneg.s32
 ;CHECK: vshl.s32
 	%tmp1 = load <4 x i32>* %A
@@ -390,7 +390,7 @@ define <4 x i32> @vashrQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vashrQs64:
+;CHECK-LABEL: vashrQs64:
 ;CHECK: vsub.i64
 ;CHECK: vshl.s64
 	%tmp1 = load <2 x i64>* %A
@@ -400,7 +400,7 @@ define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind {
-;CHECK: vashrQi8:
+;CHECK-LABEL: vashrQi8:
 ;CHECK: vshr.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = ashr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
@@ -408,7 +408,7 @@ define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind {
-;CHECK: vashrQi16:
+;CHECK-LABEL: vashrQi16:
 ;CHECK: vshr.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = ashr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
@@ -416,7 +416,7 @@ define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind {
-;CHECK: vashrQi32:
+;CHECK-LABEL: vashrQi32:
 ;CHECK: vshr.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = ashr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
@@ -424,7 +424,7 @@ define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vashrQi64(<2 x i64>* %A) nounwind {
-;CHECK: vashrQi64:
+;CHECK-LABEL: vashrQi64:
 ;CHECK: vshr.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = ashr <2 x i64> %tmp1, < i64 64, i64 64 >
diff --git a/test/CodeGen/ARM/vshiftins.ll b/test/CodeGen/ARM/vshiftins.ll
index 3a4f857..27610bf 100644
--- a/test/CodeGen/ARM/vshiftins.ll
+++ b/test/CodeGen/ARM/vshiftins.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsli8:
+;CHECK-LABEL: vsli8:
 ;CHECK: vsli.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsli16:
+;CHECK-LABEL: vsli16:
 ;CHECK: vsli.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsli32:
+;CHECK-LABEL: vsli32:
 ;CHECK: vsli.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsli64:
+;CHECK-LABEL: vsli64:
 ;CHECK: vsli.64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsliQ8:
+;CHECK-LABEL: vsliQ8:
 ;CHECK: vsli.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -46,7 +46,7 @@ define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsliQ16:
+;CHECK-LABEL: vsliQ16:
 ;CHECK: vsli.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -55,7 +55,7 @@ define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsliQ32:
+;CHECK-LABEL: vsliQ32:
 ;CHECK: vsli.32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -64,7 +64,7 @@ define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsliQ64:
+;CHECK-LABEL: vsliQ64:
 ;CHECK: vsli.64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -73,7 +73,7 @@ define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsri8:
+;CHECK-LABEL: vsri8:
 ;CHECK: vsri.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -82,7 +82,7 @@ define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsri16:
+;CHECK-LABEL: vsri16:
 ;CHECK: vsri.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -91,7 +91,7 @@ define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsri32:
+;CHECK-LABEL: vsri32:
 ;CHECK: vsri.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -100,7 +100,7 @@ define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsri64:
+;CHECK-LABEL: vsri64:
 ;CHECK: vsri.64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -109,7 +109,7 @@ define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsriQ8:
+;CHECK-LABEL: vsriQ8:
 ;CHECK: vsri.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -118,7 +118,7 @@ define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsriQ16:
+;CHECK-LABEL: vsriQ16:
 ;CHECK: vsri.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -127,7 +127,7 @@ define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsriQ32:
+;CHECK-LABEL: vsriQ32:
 ;CHECK: vsri.32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -136,7 +136,7 @@ define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsriQ64:
+;CHECK-LABEL: vsriQ64:
 ;CHECK: vsri.64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
diff --git a/test/CodeGen/ARM/vshl.ll b/test/CodeGen/ARM/vshl.ll
index 818e71b..462f7fe 100644
--- a/test/CodeGen/ARM/vshl.ll
+++ b/test/CodeGen/ARM/vshl.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vshls8:
+;CHECK-LABEL: vshls8:
 ;CHECK: vshl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vshls16:
+;CHECK-LABEL: vshls16:
 ;CHECK: vshl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vshls32:
+;CHECK-LABEL: vshls32:
 ;CHECK: vshl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vshls64:
+;CHECK-LABEL: vshls64:
 ;CHECK: vshl.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vshlu8:
+;CHECK-LABEL: vshlu8:
 ;CHECK: vshl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -46,7 +46,7 @@ define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vshlu16:
+;CHECK-LABEL: vshlu16:
 ;CHECK: vshl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -55,7 +55,7 @@ define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vshlu32:
+;CHECK-LABEL: vshlu32:
 ;CHECK: vshl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -64,7 +64,7 @@ define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vshlu64:
+;CHECK-LABEL: vshlu64:
 ;CHECK: vshl.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -73,7 +73,7 @@ define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vshlQs8:
+;CHECK-LABEL: vshlQs8:
 ;CHECK: vshl.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vshlQs16:
+;CHECK-LABEL: vshlQs16:
 ;CHECK: vshl.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -91,7 +91,7 @@ define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vshlQs32:
+;CHECK-LABEL: vshlQs32:
 ;CHECK: vshl.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vshlQs64:
+;CHECK-LABEL: vshlQs64:
 ;CHECK: vshl.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -109,7 +109,7 @@ define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vshlQu8:
+;CHECK-LABEL: vshlQu8:
 ;CHECK: vshl.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -118,7 +118,7 @@ define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vshlQu16:
+;CHECK-LABEL: vshlQu16:
 ;CHECK: vshl.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -127,7 +127,7 @@ define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vshlQu32:
+;CHECK-LABEL: vshlQu32:
 ;CHECK: vshl.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -136,7 +136,7 @@ define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vshlQu64:
+;CHECK-LABEL: vshlQu64:
 ;CHECK: vshl.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -148,7 +148,7 @@ define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 ; Test a mix of both signed and unsigned intrinsics.
 
 define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
-;CHECK: vshli8:
+;CHECK-LABEL: vshli8:
 ;CHECK: vshl.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -156,7 +156,7 @@ define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
-;CHECK: vshli16:
+;CHECK-LABEL: vshli16:
 ;CHECK: vshl.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -164,7 +164,7 @@ define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
-;CHECK: vshli32:
+;CHECK-LABEL: vshli32:
 ;CHECK: vshl.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -172,7 +172,7 @@ define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
-;CHECK: vshli64:
+;CHECK-LABEL: vshli64:
 ;CHECK: vshl.i64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
@@ -180,7 +180,7 @@ define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
-;CHECK: vshlQi8:
+;CHECK-LABEL: vshlQi8:
 ;CHECK: vshl.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -188,7 +188,7 @@ define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
-;CHECK: vshlQi16:
+;CHECK-LABEL: vshlQi16:
 ;CHECK: vshl.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
@@ -196,7 +196,7 @@ define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
-;CHECK: vshlQi32:
+;CHECK-LABEL: vshlQi32:
 ;CHECK: vshl.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
@@ -204,7 +204,7 @@ define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
-;CHECK: vshlQi64:
+;CHECK-LABEL: vshlQi64:
 ;CHECK: vshl.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
@@ -214,7 +214,7 @@ define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
 ; Right shift by immediate:
 
 define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind {
-;CHECK: vshrs8:
+;CHECK-LABEL: vshrs8:
 ;CHECK: vshr.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -222,7 +222,7 @@ define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind {
-;CHECK: vshrs16:
+;CHECK-LABEL: vshrs16:
 ;CHECK: vshr.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -230,7 +230,7 @@ define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind {
-;CHECK: vshrs32:
+;CHECK-LABEL: vshrs32:
 ;CHECK: vshr.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
@@ -238,7 +238,7 @@ define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind {
-;CHECK: vshrs64:
+;CHECK-LABEL: vshrs64:
 ;CHECK: vshr.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
@@ -246,7 +246,7 @@ define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vshru8(<8 x i8>* %A) nounwind {
-;CHECK: vshru8:
+;CHECK-LABEL: vshru8:
 ;CHECK: vshr.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -254,7 +254,7 @@ define <8 x i8> @vshru8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vshru16(<4 x i16>* %A) nounwind {
-;CHECK: vshru16:
+;CHECK-LABEL: vshru16:
 ;CHECK: vshr.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -262,7 +262,7 @@ define <4 x i16> @vshru16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vshru32(<2 x i32>* %A) nounwind {
-;CHECK: vshru32:
+;CHECK-LABEL: vshru32:
 ;CHECK: vshr.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
@@ -270,7 +270,7 @@ define <2 x i32> @vshru32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vshru64(<1 x i64>* %A) nounwind {
-;CHECK: vshru64:
+;CHECK-LABEL: vshru64:
 ;CHECK: vshr.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
@@ -278,7 +278,7 @@ define <1 x i64> @vshru64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind {
-;CHECK: vshrQs8:
+;CHECK-LABEL: vshrQs8:
 ;CHECK: vshr.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -286,7 +286,7 @@ define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind {
-;CHECK: vshrQs16:
+;CHECK-LABEL: vshrQs16:
 ;CHECK: vshr.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -294,7 +294,7 @@ define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind {
-;CHECK: vshrQs32:
+;CHECK-LABEL: vshrQs32:
 ;CHECK: vshr.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
@@ -302,7 +302,7 @@ define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind {
-;CHECK: vshrQs64:
+;CHECK-LABEL: vshrQs64:
 ;CHECK: vshr.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
@@ -310,7 +310,7 @@ define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind {
-;CHECK: vshrQu8:
+;CHECK-LABEL: vshrQu8:
 ;CHECK: vshr.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -318,7 +318,7 @@ define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind {
-;CHECK: vshrQu16:
+;CHECK-LABEL: vshrQu16:
 ;CHECK: vshr.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -326,7 +326,7 @@ define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind {
-;CHECK: vshrQu32:
+;CHECK-LABEL: vshrQu32:
 ;CHECK: vshr.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
@@ -334,7 +334,7 @@ define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vshrQu64(<2 x i64>* %A) nounwind {
-;CHECK: vshrQu64:
+;CHECK-LABEL: vshrQu64:
 ;CHECK: vshr.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
@@ -362,7 +362,7 @@ declare <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind re
 declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i8> @vrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrshls8:
+;CHECK-LABEL: vrshls8:
 ;CHECK: vrshl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -371,7 +371,7 @@ define <8 x i8> @vrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrshls16:
+;CHECK-LABEL: vrshls16:
 ;CHECK: vrshl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -380,7 +380,7 @@ define <4 x i16> @vrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrshls32:
+;CHECK-LABEL: vrshls32:
 ;CHECK: vrshl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -389,7 +389,7 @@ define <2 x i32> @vrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrshls64:
+;CHECK-LABEL: vrshls64:
 ;CHECK: vrshl.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -398,7 +398,7 @@ define <1 x i64> @vrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrshlu8:
+;CHECK-LABEL: vrshlu8:
 ;CHECK: vrshl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -407,7 +407,7 @@ define <8 x i8> @vrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrshlu16:
+;CHECK-LABEL: vrshlu16:
 ;CHECK: vrshl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -416,7 +416,7 @@ define <4 x i16> @vrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrshlu32:
+;CHECK-LABEL: vrshlu32:
 ;CHECK: vrshl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -425,7 +425,7 @@ define <2 x i32> @vrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrshlu64:
+;CHECK-LABEL: vrshlu64:
 ;CHECK: vrshl.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -434,7 +434,7 @@ define <1 x i64> @vrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrshlQs8:
+;CHECK-LABEL: vrshlQs8:
 ;CHECK: vrshl.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -443,7 +443,7 @@ define <16 x i8> @vrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrshlQs16:
+;CHECK-LABEL: vrshlQs16:
 ;CHECK: vrshl.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -452,7 +452,7 @@ define <8 x i16> @vrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrshlQs32:
+;CHECK-LABEL: vrshlQs32:
 ;CHECK: vrshl.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -461,7 +461,7 @@ define <4 x i32> @vrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrshlQs64:
+;CHECK-LABEL: vrshlQs64:
 ;CHECK: vrshl.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -470,7 +470,7 @@ define <2 x i64> @vrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrshlQu8:
+;CHECK-LABEL: vrshlQu8:
 ;CHECK: vrshl.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -479,7 +479,7 @@ define <16 x i8> @vrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrshlQu16:
+;CHECK-LABEL: vrshlQu16:
 ;CHECK: vrshl.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -488,7 +488,7 @@ define <8 x i16> @vrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrshlQu32:
+;CHECK-LABEL: vrshlQu32:
 ;CHECK: vrshl.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -497,7 +497,7 @@ define <4 x i32> @vrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrshlQu64:
+;CHECK-LABEL: vrshlQu64:
 ;CHECK: vrshl.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -506,7 +506,7 @@ define <2 x i64> @vrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vrshrs8(<8 x i8>* %A) nounwind {
-;CHECK: vrshrs8:
+;CHECK-LABEL: vrshrs8:
 ;CHECK: vrshr.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -514,7 +514,7 @@ define <8 x i8> @vrshrs8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vrshrs16(<4 x i16>* %A) nounwind {
-;CHECK: vrshrs16:
+;CHECK-LABEL: vrshrs16:
 ;CHECK: vrshr.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -522,7 +522,7 @@ define <4 x i16> @vrshrs16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vrshrs32(<2 x i32>* %A) nounwind {
-;CHECK: vrshrs32:
+;CHECK-LABEL: vrshrs32:
 ;CHECK: vrshr.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
@@ -530,7 +530,7 @@ define <2 x i32> @vrshrs32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vrshrs64(<1 x i64>* %A) nounwind {
-;CHECK: vrshrs64:
+;CHECK-LABEL: vrshrs64:
 ;CHECK: vrshr.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
@@ -538,7 +538,7 @@ define <1 x i64> @vrshrs64(<1 x i64>* %A) nounwind {
 }
 
 define <8 x i8> @vrshru8(<8 x i8>* %A) nounwind {
-;CHECK: vrshru8:
+;CHECK-LABEL: vrshru8:
 ;CHECK: vrshr.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -546,7 +546,7 @@ define <8 x i8> @vrshru8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @vrshru16(<4 x i16>* %A) nounwind {
-;CHECK: vrshru16:
+;CHECK-LABEL: vrshru16:
 ;CHECK: vrshr.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -554,7 +554,7 @@ define <4 x i16> @vrshru16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @vrshru32(<2 x i32>* %A) nounwind {
-;CHECK: vrshru32:
+;CHECK-LABEL: vrshru32:
 ;CHECK: vrshr.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
@@ -562,7 +562,7 @@ define <2 x i32> @vrshru32(<2 x i32>* %A) nounwind {
 }
 
 define <1 x i64> @vrshru64(<1 x i64>* %A) nounwind {
-;CHECK: vrshru64:
+;CHECK-LABEL: vrshru64:
 ;CHECK: vrshr.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
@@ -570,7 +570,7 @@ define <1 x i64> @vrshru64(<1 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vrshrQs8(<16 x i8>* %A) nounwind {
-;CHECK: vrshrQs8:
+;CHECK-LABEL: vrshrQs8:
 ;CHECK: vrshr.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -578,7 +578,7 @@ define <16 x i8> @vrshrQs8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vrshrQs16(<8 x i16>* %A) nounwind {
-;CHECK: vrshrQs16:
+;CHECK-LABEL: vrshrQs16:
 ;CHECK: vrshr.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -586,7 +586,7 @@ define <8 x i16> @vrshrQs16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vrshrQs32(<4 x i32>* %A) nounwind {
-;CHECK: vrshrQs32:
+;CHECK-LABEL: vrshrQs32:
 ;CHECK: vrshr.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
@@ -594,7 +594,7 @@ define <4 x i32> @vrshrQs32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vrshrQs64(<2 x i64>* %A) nounwind {
-;CHECK: vrshrQs64:
+;CHECK-LABEL: vrshrQs64:
 ;CHECK: vrshr.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
@@ -602,7 +602,7 @@ define <2 x i64> @vrshrQs64(<2 x i64>* %A) nounwind {
 }
 
 define <16 x i8> @vrshrQu8(<16 x i8>* %A) nounwind {
-;CHECK: vrshrQu8:
+;CHECK-LABEL: vrshrQu8:
 ;CHECK: vrshr.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
@@ -610,7 +610,7 @@ define <16 x i8> @vrshrQu8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @vrshrQu16(<8 x i16>* %A) nounwind {
-;CHECK: vrshrQu16:
+;CHECK-LABEL: vrshrQu16:
 ;CHECK: vrshr.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
@@ -618,7 +618,7 @@ define <8 x i16> @vrshrQu16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @vrshrQu32(<4 x i32>* %A) nounwind {
-;CHECK: vrshrQu32:
+;CHECK-LABEL: vrshrQu32:
 ;CHECK: vrshr.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
@@ -626,7 +626,7 @@ define <4 x i32> @vrshrQu32(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i64> @vrshrQu64(<2 x i64>* %A) nounwind {
-;CHECK: vrshrQu64:
+;CHECK-LABEL: vrshrQu64:
 ;CHECK: vrshr.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
diff --git a/test/CodeGen/ARM/vshll.ll b/test/CodeGen/ARM/vshll.ll
index 8e85b98..ae80664 100644
--- a/test/CodeGen/ARM/vshll.ll
+++ b/test/CodeGen/ARM/vshll.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind {
-;CHECK: vshlls8:
+;CHECK-LABEL: vshlls8:
 ;CHECK: vshll.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -9,7 +9,7 @@ define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind {
-;CHECK: vshlls16:
+;CHECK-LABEL: vshlls16:
 ;CHECK: vshll.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -17,7 +17,7 @@ define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind {
-;CHECK: vshlls32:
+;CHECK-LABEL: vshlls32:
 ;CHECK: vshll.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -25,7 +25,7 @@ define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind {
 }
 
 define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind {
-;CHECK: vshllu8:
+;CHECK-LABEL: vshllu8:
 ;CHECK: vshll.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
@@ -33,7 +33,7 @@ define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind {
-;CHECK: vshllu16:
+;CHECK-LABEL: vshllu16:
 ;CHECK: vshll.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
@@ -41,7 +41,7 @@ define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind {
-;CHECK: vshllu32:
+;CHECK-LABEL: vshllu32:
 ;CHECK: vshll.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
@@ -51,7 +51,7 @@ define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind {
 ; The following tests use the maximum shift count, so the signedness is
 ; irrelevant.  Test both signed and unsigned versions.
 define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind {
-;CHECK: vshlli8:
+;CHECK-LABEL: vshlli8:
 ;CHECK: vshll.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >)
@@ -59,7 +59,7 @@ define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind {
-;CHECK: vshlli16:
+;CHECK-LABEL: vshlli16:
 ;CHECK: vshll.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 16, i16 16, i16 16, i16 16 >)
@@ -67,7 +67,7 @@ define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i64> @vshlli32(<2 x i32>* %A) nounwind {
-;CHECK: vshlli32:
+;CHECK-LABEL: vshlli32:
 ;CHECK: vshll.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >)
diff --git a/test/CodeGen/ARM/vshrn.ll b/test/CodeGen/ARM/vshrn.ll
index e2544f4..40a94fe 100644
--- a/test/CodeGen/ARM/vshrn.ll
+++ b/test/CodeGen/ARM/vshrn.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vshrns8:
+;CHECK-LABEL: vshrns8:
 ;CHECK: vshrn.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -9,7 +9,7 @@ define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vshrns16:
+;CHECK-LABEL: vshrns16:
 ;CHECK: vshrn.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -17,7 +17,7 @@ define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vshrns32:
+;CHECK-LABEL: vshrns32:
 ;CHECK: vshrn.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
@@ -29,7 +29,7 @@ declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind re
 declare <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vrshrns8:
+;CHECK-LABEL: vrshrns8:
 ;CHECK: vrshrn.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
@@ -37,7 +37,7 @@ define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vrshrns16:
+;CHECK-LABEL: vrshrns16:
 ;CHECK: vrshrn.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
@@ -45,7 +45,7 @@ define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind {
 }
 
 define <2 x i32> @vrshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vrshrns32:
+;CHECK-LABEL: vrshrns32:
 ;CHECK: vrshrn.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
diff --git a/test/CodeGen/ARM/vsra.ll b/test/CodeGen/ARM/vsra.ll
index acb672d..7a211c3 100644
--- a/test/CodeGen/ARM/vsra.ll
+++ b/test/CodeGen/ARM/vsra.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsras8:
+;CHECK-LABEL: vsras8:
 ;CHECK: vsra.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -11,7 +11,7 @@ define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsras16:
+;CHECK-LABEL: vsras16:
 ;CHECK: vsra.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -21,7 +21,7 @@ define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsras32:
+;CHECK-LABEL: vsras32:
 ;CHECK: vsra.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -31,7 +31,7 @@ define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsras64:
+;CHECK-LABEL: vsras64:
 ;CHECK: vsra.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -41,7 +41,7 @@ define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsraQs8:
+;CHECK-LABEL: vsraQs8:
 ;CHECK: vsra.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -51,7 +51,7 @@ define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsraQs16:
+;CHECK-LABEL: vsraQs16:
 ;CHECK: vsra.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -61,7 +61,7 @@ define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsraQs32:
+;CHECK-LABEL: vsraQs32:
 ;CHECK: vsra.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -71,7 +71,7 @@ define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsraQs64:
+;CHECK-LABEL: vsraQs64:
 ;CHECK: vsra.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -81,7 +81,7 @@ define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsrau8:
+;CHECK-LABEL: vsrau8:
 ;CHECK: vsra.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -91,7 +91,7 @@ define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsrau16:
+;CHECK-LABEL: vsrau16:
 ;CHECK: vsra.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -101,7 +101,7 @@ define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsrau32:
+;CHECK-LABEL: vsrau32:
 ;CHECK: vsra.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -111,7 +111,7 @@ define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsrau64:
+;CHECK-LABEL: vsrau64:
 ;CHECK: vsra.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -121,7 +121,7 @@ define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsraQu8:
+;CHECK-LABEL: vsraQu8:
 ;CHECK: vsra.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -131,7 +131,7 @@ define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsraQu16:
+;CHECK-LABEL: vsraQu16:
 ;CHECK: vsra.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -141,7 +141,7 @@ define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsraQu32:
+;CHECK-LABEL: vsraQu32:
 ;CHECK: vsra.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -151,7 +151,7 @@ define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsraQu64:
+;CHECK-LABEL: vsraQu64:
 ;CHECK: vsra.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -161,7 +161,7 @@ define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrsras8:
+;CHECK-LABEL: vrsras8:
 ;CHECK: vrsra.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -171,7 +171,7 @@ define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrsras16:
+;CHECK-LABEL: vrsras16:
 ;CHECK: vrsra.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -181,7 +181,7 @@ define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrsras32:
+;CHECK-LABEL: vrsras32:
 ;CHECK: vrsra.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -191,7 +191,7 @@ define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrsras64:
+;CHECK-LABEL: vrsras64:
 ;CHECK: vrsra.s64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -201,7 +201,7 @@ define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrsrau8:
+;CHECK-LABEL: vrsrau8:
 ;CHECK: vrsra.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -211,7 +211,7 @@ define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrsrau16:
+;CHECK-LABEL: vrsrau16:
 ;CHECK: vrsra.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -221,7 +221,7 @@ define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrsrau32:
+;CHECK-LABEL: vrsrau32:
 ;CHECK: vrsra.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -231,7 +231,7 @@ define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrsrau64:
+;CHECK-LABEL: vrsrau64:
 ;CHECK: vrsra.u64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -241,7 +241,7 @@ define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrsraQs8:
+;CHECK-LABEL: vrsraQs8:
 ;CHECK: vrsra.s8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -251,7 +251,7 @@ define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrsraQs16:
+;CHECK-LABEL: vrsraQs16:
 ;CHECK: vrsra.s16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -261,7 +261,7 @@ define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrsraQs32:
+;CHECK-LABEL: vrsraQs32:
 ;CHECK: vrsra.s32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -271,7 +271,7 @@ define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrsraQs64:
+;CHECK-LABEL: vrsraQs64:
 ;CHECK: vrsra.s64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -281,7 +281,7 @@ define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrsraQu8:
+;CHECK-LABEL: vrsraQu8:
 ;CHECK: vrsra.u8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -291,7 +291,7 @@ define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrsraQu16:
+;CHECK-LABEL: vrsraQu16:
 ;CHECK: vrsra.u16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -301,7 +301,7 @@ define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrsraQu32:
+;CHECK-LABEL: vrsraQu32:
 ;CHECK: vrsra.u32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -311,7 +311,7 @@ define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vrsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrsraQu64:
+;CHECK-LABEL: vrsraQu64:
 ;CHECK: vrsra.u64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
diff --git a/test/CodeGen/ARM/vst1.ll b/test/CodeGen/ARM/vst1.ll
index e1f3e88..36439fd 100644
--- a/test/CodeGen/ARM/vst1.ll
+++ b/test/CodeGen/ARM/vst1.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst1i8:
+;CHECK-LABEL: vst1i8:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vst1.8 {d16}, [r0:64]
 	%tmp1 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
 }
 
 define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst1i16:
+;CHECK-LABEL: vst1i16:
 ;CHECK: vst1.16
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst1i32:
+;CHECK-LABEL: vst1i32:
 ;CHECK: vst1.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define void @vst1f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst1f:
+;CHECK-LABEL: vst1f:
 ;CHECK: vst1.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -38,7 +38,7 @@ define void @vst1f(float* %A, <2 x float>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind {
-;CHECK: vst1f_update:
+;CHECK-LABEL: vst1f_update:
 ;CHECK: vst1.32 {d16}, [r1]!
 	%A = load float** %ptr
 	%tmp0 = bitcast float* %A to i8*
@@ -50,7 +50,7 @@ define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind {
 }
 
 define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst1i64:
+;CHECK-LABEL: vst1i64:
 ;CHECK: vst1.64
 	%tmp0 = bitcast i64* %A to i8*
 	%tmp1 = load <1 x i64>* %B
@@ -59,7 +59,7 @@ define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind {
 }
 
 define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst1Qi8:
+;CHECK-LABEL: vst1Qi8:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst1.8 {d16, d17}, [r0:64]
 	%tmp1 = load <16 x i8>* %B
@@ -68,7 +68,7 @@ define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind {
 }
 
 define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst1Qi16:
+;CHECK-LABEL: vst1Qi16:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst1.16 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -79,7 +79,7 @@ define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
 
 ;Check for a post-increment updating store with register increment.
 define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
-;CHECK: vst1Qi16_update:
+;CHECK-LABEL: vst1Qi16_update:
 ;CHECK: vst1.16 {d16, d17}, [r1:64], r2
 	%A = load i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
@@ -91,7 +91,7 @@ define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
 }
 
 define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst1Qi32:
+;CHECK-LABEL: vst1Qi32:
 ;CHECK: vst1.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <4 x i32>* %B
@@ -100,7 +100,7 @@ define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define void @vst1Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst1Qf:
+;CHECK-LABEL: vst1Qf:
 ;CHECK: vst1.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
@@ -109,7 +109,7 @@ define void @vst1Qf(float* %A, <4 x float>* %B) nounwind {
 }
 
 define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind {
-;CHECK: vst1Qi64:
+;CHECK-LABEL: vst1Qi64:
 ;CHECK: vst1.64
 	%tmp0 = bitcast i64* %A to i8*
 	%tmp1 = load <2 x i64>* %B
diff --git a/test/CodeGen/ARM/vst2.ll b/test/CodeGen/ARM/vst2.ll
index a31f863..7551a56 100644
--- a/test/CodeGen/ARM/vst2.ll
+++ b/test/CodeGen/ARM/vst2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst2i8:
+;CHECK-LABEL: vst2i8:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst2.8 {d16, d17}, [r0:64]
 	%tmp1 = load <8 x i8>* %B
@@ -11,7 +11,7 @@ define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
 
 ;Check for a post-increment updating store with register increment.
 define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
-;CHECK: vst2i8_update:
+;CHECK-LABEL: vst2i8_update:
 ;CHECK: vst2.8 {d16, d17}, [r1], r2
 	%A = load i8** %ptr
 	%tmp1 = load <8 x i8>* %B
@@ -22,7 +22,7 @@ define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
 }
 
 define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst2i16:
+;CHECK-LABEL: vst2i16:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst2.16 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -32,7 +32,7 @@ define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst2i32:
+;CHECK-LABEL: vst2i32:
 ;CHECK: vst2.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <2 x i32>* %B
@@ -41,7 +41,7 @@ define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define void @vst2f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst2f:
+;CHECK-LABEL: vst2f:
 ;CHECK: vst2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -50,7 +50,7 @@ define void @vst2f(float* %A, <2 x float>* %B) nounwind {
 }
 
 define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst2i64:
+;CHECK-LABEL: vst2i64:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst1.64 {d16, d17}, [r0:128]
 	%tmp0 = bitcast i64* %A to i8*
@@ -61,7 +61,7 @@ define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind {
-;CHECK: vst2i64_update:
+;CHECK-LABEL: vst2i64_update:
 ;CHECK: vst1.64 {d16, d17}, [r1:64]!
 	%A = load i64** %ptr
 	%tmp0 = bitcast i64* %A to i8*
@@ -73,7 +73,7 @@ define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind {
 }
 
 define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst2Qi8:
+;CHECK-LABEL: vst2Qi8:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64]
 	%tmp1 = load <16 x i8>* %B
@@ -82,7 +82,7 @@ define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind {
 }
 
 define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst2Qi16:
+;CHECK-LABEL: vst2Qi16:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -92,7 +92,7 @@ define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst2Qi32:
+;CHECK-LABEL: vst2Qi32:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256]
 	%tmp0 = bitcast i32* %A to i8*
@@ -102,7 +102,7 @@ define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define void @vst2Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst2Qf:
+;CHECK-LABEL: vst2Qf:
 ;CHECK: vst2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
@@ -111,7 +111,7 @@ define void @vst2Qf(float* %A, <4 x float>* %B) nounwind {
 }
 
 define i8* @vst2update(i8* %out, <4 x i16>* %B) nounwind {
-;CHECK: vst2update
+;CHECK-LABEL: vst2update:
 ;CHECK: vst2.16 {d16, d17}, [r0]!
 	%tmp1 = load <4 x i16>* %B
 	tail call void @llvm.arm.neon.vst2.v4i16(i8* %out, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 2)
@@ -120,7 +120,7 @@ define i8* @vst2update(i8* %out, <4 x i16>* %B) nounwind {
 }
 
 define i8* @vst2update2(i8 * %out, <4 x float> * %this) nounwind optsize ssp align 2 {
-;CHECK: vst2update2
+;CHECK-LABEL: vst2update2:
 ;CHECK: vst2.32 {d16, d17, d18, d19}, [r0]!
   %tmp1 = load <4 x float>* %this
   call void @llvm.arm.neon.vst2.v4f32(i8* %out, <4 x float> %tmp1, <4 x float> %tmp1, i32 4) nounwind
diff --git a/test/CodeGen/ARM/vst3.ll b/test/CodeGen/ARM/vst3.ll
index 281bb73..91eb7fc 100644
--- a/test/CodeGen/ARM/vst3.ll
+++ b/test/CodeGen/ARM/vst3.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon -fast-isel=0 -O0 | FileCheck %s
 
 define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst3i8:
+;CHECK-LABEL: vst3i8:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;This test runs at -O0 so do not check for specific register numbers.
 ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
@@ -11,7 +11,7 @@ define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind {
 }
 
 define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst3i16:
+;CHECK-LABEL: vst3i16:
 ;CHECK: vst3.16
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = load <4 x i16>* %B
@@ -20,7 +20,7 @@ define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst3i32:
+;CHECK-LABEL: vst3i32:
 ;CHECK: vst3.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <2 x i32>* %B
@@ -30,7 +30,7 @@ define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst3i32_update(i32** %ptr, <2 x i32>* %B) nounwind {
-;CHECK: vst3i32_update:
+;CHECK-LABEL: vst3i32_update:
 ;CHECK: vst3.32 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
 	%A = load i32** %ptr
 	%tmp0 = bitcast i32* %A to i8*
@@ -42,7 +42,7 @@ define void @vst3i32_update(i32** %ptr, <2 x i32>* %B) nounwind {
 }
 
 define void @vst3f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst3f:
+;CHECK-LABEL: vst3f:
 ;CHECK: vst3.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -51,7 +51,7 @@ define void @vst3f(float* %A, <2 x float>* %B) nounwind {
 }
 
 define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst3i64:
+;CHECK-LABEL: vst3i64:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;This test runs at -O0 so do not check for specific register numbers.
 ;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
@@ -62,7 +62,7 @@ define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind {
 }
 
 define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst3Qi8:
+;CHECK-LABEL: vst3Qi8:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;This test runs at -O0 so do not check for specific register numbers.
 ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]!
@@ -73,7 +73,7 @@ define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind {
 }
 
 define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst3Qi16:
+;CHECK-LABEL: vst3Qi16:
 ;CHECK: vst3.16
 ;CHECK: vst3.16
 	%tmp0 = bitcast i16* %A to i8*
@@ -84,7 +84,7 @@ define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst3Qi16_update(i16** %ptr, <8 x i16>* %B) nounwind {
-;CHECK: vst3Qi16_update:
+;CHECK-LABEL: vst3Qi16_update:
 ;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
 ;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
 	%A = load i16** %ptr
@@ -97,7 +97,7 @@ define void @vst3Qi16_update(i16** %ptr, <8 x i16>* %B) nounwind {
 }
 
 define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst3Qi32:
+;CHECK-LABEL: vst3Qi32:
 ;CHECK: vst3.32
 ;CHECK: vst3.32
 	%tmp0 = bitcast i32* %A to i8*
@@ -107,7 +107,7 @@ define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define void @vst3Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst3Qf:
+;CHECK-LABEL: vst3Qf:
 ;CHECK: vst3.32
 ;CHECK: vst3.32
 	%tmp0 = bitcast float* %A to i8*
diff --git a/test/CodeGen/ARM/vst4.ll b/test/CodeGen/ARM/vst4.ll
index 7dedb2f..ef5c83a 100644
--- a/test/CodeGen/ARM/vst4.ll
+++ b/test/CodeGen/ARM/vst4.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst4i8:
+;CHECK-LABEL: vst4i8:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64]
 	%tmp1 = load <8 x i8>* %B
@@ -11,7 +11,7 @@ define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
 
 ;Check for a post-increment updating store with register increment.
 define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
-;CHECK: vst4i8_update:
+;CHECK-LABEL: vst4i8_update:
 ;CHECK: vst4.8 {d16, d17, d18, d19}, [r1:128], r2
 	%A = load i8** %ptr
 	%tmp1 = load <8 x i8>* %B
@@ -22,7 +22,7 @@ define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
 }
 
 define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst4i16:
+;CHECK-LABEL: vst4i16:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128]
 	%tmp0 = bitcast i16* %A to i8*
@@ -32,7 +32,7 @@ define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst4i32:
+;CHECK-LABEL: vst4i32:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst4.32 {d16, d17, d18, d19}, [r0:256]
 	%tmp0 = bitcast i32* %A to i8*
@@ -42,7 +42,7 @@ define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define void @vst4f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst4f:
+;CHECK-LABEL: vst4f:
 ;CHECK: vst4.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -51,7 +51,7 @@ define void @vst4f(float* %A, <2 x float>* %B) nounwind {
 }
 
 define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst4i64:
+;CHECK-LABEL: vst4i64:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst1.64 {d16, d17, d18, d19}, [r0:256]
 	%tmp0 = bitcast i64* %A to i8*
@@ -61,7 +61,7 @@ define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind {
 }
 
 define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst4Qi8:
+;CHECK-LABEL: vst4Qi8:
 ;Check the alignment value.  Max for this instruction is 256 bits:
 ;CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]!
 ;CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]
@@ -71,7 +71,7 @@ define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind {
 }
 
 define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst4Qi16:
+;CHECK-LABEL: vst4Qi16:
 ;Check for no alignment specifier.
 ;CHECK: vst4.16 {d16, d18, d20, d22}, [r0]!
 ;CHECK: vst4.16 {d17, d19, d21, d23}, [r0]
@@ -82,7 +82,7 @@ define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst4Qi32:
+;CHECK-LABEL: vst4Qi32:
 ;CHECK: vst4.32
 ;CHECK: vst4.32
 	%tmp0 = bitcast i32* %A to i8*
@@ -92,7 +92,7 @@ define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define void @vst4Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst4Qf:
+;CHECK-LABEL: vst4Qf:
 ;CHECK: vst4.32
 ;CHECK: vst4.32
 	%tmp0 = bitcast float* %A to i8*
@@ -103,7 +103,7 @@ define void @vst4Qf(float* %A, <4 x float>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst4Qf_update(float** %ptr, <4 x float>* %B) nounwind {
-;CHECK: vst4Qf_update:
+;CHECK-LABEL: vst4Qf_update:
 ;CHECK: vst4.32 {d16, d18, d20, d22}, [r1]!
 ;CHECK: vst4.32 {d17, d19, d21, d23}, [r1]!
 	%A = load float** %ptr
diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll
index 67f251f..651b6d5 100644
--- a/test/CodeGen/ARM/vstlane.ll
+++ b/test/CodeGen/ARM/vstlane.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst1lanei8:
+;CHECK-LABEL: vst1lanei8:
 ;Check the (default) alignment.
 ;CHECK: vst1.8 {d16[3]}, [r0]
 	%tmp1 = load <8 x i8>* %B
@@ -12,7 +12,7 @@ define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
-;CHECK: vst1lanei8_update:
+;CHECK-LABEL: vst1lanei8_update:
 ;CHECK: vst1.8 {d16[3]}, [r2]!
 	%A = load i8** %ptr
 	%tmp1 = load <8 x i8>* %B
@@ -24,7 +24,7 @@ define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
 }
 
 define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst1lanei16:
+;CHECK-LABEL: vst1lanei16:
 ;Check the alignment value.  Max for this instruction is 16 bits:
 ;CHECK: vst1.16 {d16[2]}, [r0:16]
 	%tmp1 = load <4 x i16>* %B
@@ -34,7 +34,7 @@ define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst1lanei32:
+;CHECK-LABEL: vst1lanei32:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vst1.32 {d16[1]}, [r0:32]
 	%tmp1 = load <2 x i32>* %B
@@ -44,7 +44,7 @@ define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define void @vst1lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst1lanef:
+;CHECK-LABEL: vst1lanef:
 ;CHECK: vst1.32 {d16[1]}, [r0:32]
 	%tmp1 = load <2 x float>* %B
         %tmp2 = extractelement <2 x float> %tmp1, i32 1
@@ -53,7 +53,7 @@ define void @vst1lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst1laneQi8:
+;CHECK-LABEL: vst1laneQi8:
 ; // Can use scalar load. No need to use vectors.
 ; // CHE-CK: vst1.8 {d17[1]}, [r0]
 	%tmp1 = load <16 x i8>* %B
@@ -63,7 +63,7 @@ define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
 }
 
 define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst1laneQi16:
+;CHECK-LABEL: vst1laneQi16:
 ;CHECK: vst1.16 {d17[1]}, [r0:16]
 	%tmp1 = load <8 x i16>* %B
         %tmp2 = extractelement <8 x i16> %tmp1, i32 5
@@ -72,7 +72,7 @@ define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst1laneQi32:
+;CHECK-LABEL: vst1laneQi32:
 ; // Can use scalar load. No need to use vectors.
 ; // CHE-CK: vst1.32 {d17[1]}, [r0:32]
 	%tmp1 = load <4 x i32>* %B
@@ -83,7 +83,7 @@ define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
-;CHECK: vst1laneQi32_update:
+;CHECK-LABEL: vst1laneQi32_update:
 ; // Can use scalar load. No need to use vectors.
 ; // CHE-CK: vst1.32 {d17[1]}, [r1:32]!
 	%A = load i32** %ptr
@@ -96,7 +96,7 @@ define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
 }
 
 define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst1laneQf:
+;CHECK-LABEL: vst1laneQf:
 ; // Can use scalar load. No need to use vectors.
 ; // CHE-CK: vst1.32 {d17[1]}, [r0]
 	%tmp1 = load <4 x float>* %B
@@ -106,7 +106,7 @@ define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind {
 }
 
 define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst2lanei8:
+;CHECK-LABEL: vst2lanei8:
 ;Check the alignment value.  Max for this instruction is 16 bits:
 ;CHECK: vst2.8 {d16[1], d17[1]}, [r0:16]
 	%tmp1 = load <8 x i8>* %B
@@ -115,7 +115,7 @@ define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
 }
 
 define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst2lanei16:
+;CHECK-LABEL: vst2lanei16:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vst2.16 {d16[1], d17[1]}, [r0:32]
 	%tmp0 = bitcast i16* %A to i8*
@@ -126,7 +126,7 @@ define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
 
 ;Check for a post-increment updating store with register increment.
 define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind {
-;CHECK: vst2lanei16_update:
+;CHECK-LABEL: vst2lanei16_update:
 ;CHECK: vst2.16 {d16[1], d17[1]}, [r1], r2
 	%A = load i16** %ptr
 	%tmp0 = bitcast i16* %A to i8*
@@ -138,7 +138,7 @@ define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind {
 }
 
 define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst2lanei32:
+;CHECK-LABEL: vst2lanei32:
 ;CHECK: vst2.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <2 x i32>* %B
@@ -147,7 +147,7 @@ define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define void @vst2lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst2lanef:
+;CHECK-LABEL: vst2lanef:
 ;CHECK: vst2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -156,7 +156,7 @@ define void @vst2lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst2laneQi16:
+;CHECK-LABEL: vst2laneQi16:
 ;Check the (default) alignment.
 ;CHECK: vst2.16 {d17[1], d19[1]}, [r0]
 	%tmp0 = bitcast i16* %A to i8*
@@ -166,7 +166,7 @@ define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst2laneQi32:
+;CHECK-LABEL: vst2laneQi32:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vst2.32 {d17[0], d19[0]}, [r0:64]
 	%tmp0 = bitcast i32* %A to i8*
@@ -176,7 +176,7 @@ define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define void @vst2laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst2laneQf:
+;CHECK-LABEL: vst2laneQf:
 ;CHECK: vst2.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
@@ -194,7 +194,7 @@ declare void @llvm.arm.neon.vst2lane.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32)
 declare void @llvm.arm.neon.vst2lane.v4f32(i8*, <4 x float>, <4 x float>, i32, i32) nounwind
 
 define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst3lanei8:
+;CHECK-LABEL: vst3lanei8:
 ;CHECK: vst3.8
 	%tmp1 = load <8 x i8>* %B
 	call void @llvm.arm.neon.vst3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
@@ -202,7 +202,7 @@ define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind {
 }
 
 define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst3lanei16:
+;CHECK-LABEL: vst3lanei16:
 ;Check the (default) alignment value.  VST3 does not support alignment.
 ;CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0]
 	%tmp0 = bitcast i16* %A to i8*
@@ -212,7 +212,7 @@ define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst3lanei32:
+;CHECK-LABEL: vst3lanei32:
 ;CHECK: vst3.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <2 x i32>* %B
@@ -221,7 +221,7 @@ define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define void @vst3lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst3lanef:
+;CHECK-LABEL: vst3lanef:
 ;CHECK: vst3.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -230,7 +230,7 @@ define void @vst3lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst3laneQi16:
+;CHECK-LABEL: vst3laneQi16:
 ;Check the (default) alignment value.  VST3 does not support alignment.
 ;CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0]
 	%tmp0 = bitcast i16* %A to i8*
@@ -240,7 +240,7 @@ define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst3laneQi32:
+;CHECK-LABEL: vst3laneQi32:
 ;CHECK: vst3.32
 	%tmp0 = bitcast i32* %A to i8*
 	%tmp1 = load <4 x i32>* %B
@@ -250,7 +250,7 @@ define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
-;CHECK: vst3laneQi32_update:
+;CHECK-LABEL: vst3laneQi32_update:
 ;CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r1]!
 	%A = load i32** %ptr
 	%tmp0 = bitcast i32* %A to i8*
@@ -262,7 +262,7 @@ define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
 }
 
 define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst3laneQf:
+;CHECK-LABEL: vst3laneQf:
 ;CHECK: vst3.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
@@ -281,7 +281,7 @@ declare void @llvm.arm.neon.vst3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x f
 
 
 define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst4lanei8:
+;CHECK-LABEL: vst4lanei8:
 ;Check the alignment value.  Max for this instruction is 32 bits:
 ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]
 	%tmp1 = load <8 x i8>* %B
@@ -291,7 +291,7 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
 
 ;Check for a post-increment updating store.
 define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
-;CHECK: vst4lanei8_update:
+;CHECK-LABEL: vst4lanei8_update:
 ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!
 	%A = load i8** %ptr
 	%tmp1 = load <8 x i8>* %B
@@ -302,7 +302,7 @@ define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
 }
 
 define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst4lanei16:
+;CHECK-LABEL: vst4lanei16:
 ;CHECK: vst4.16
 	%tmp0 = bitcast i16* %A to i8*
 	%tmp1 = load <4 x i16>* %B
@@ -311,7 +311,7 @@ define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
 }
 
 define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst4lanei32:
+;CHECK-LABEL: vst4lanei32:
 ;Check the alignment value.  Max for this instruction is 128 bits:
 ;CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]
 	%tmp0 = bitcast i32* %A to i8*
@@ -321,7 +321,7 @@ define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
 }
 
 define void @vst4lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst4lanef:
+;CHECK-LABEL: vst4lanef:
 ;CHECK: vst4.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <2 x float>* %B
@@ -330,7 +330,7 @@ define void @vst4lanef(float* %A, <2 x float>* %B) nounwind {
 }
 
 define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst4laneQi16:
+;CHECK-LABEL: vst4laneQi16:
 ;Check the alignment value.  Max for this instruction is 64 bits:
 ;CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64]
 	%tmp0 = bitcast i16* %A to i8*
@@ -340,7 +340,7 @@ define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
 }
 
 define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst4laneQi32:
+;CHECK-LABEL: vst4laneQi32:
 ;Check the (default) alignment.
 ;CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
 	%tmp0 = bitcast i32* %A to i8*
@@ -350,7 +350,7 @@ define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
 }
 
 define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst4laneQf:
+;CHECK-LABEL: vst4laneQf:
 ;CHECK: vst4.32
 	%tmp0 = bitcast float* %A to i8*
 	%tmp1 = load <4 x float>* %B
@@ -360,7 +360,7 @@ define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind {
 
 ; Make sure this doesn't crash; PR10258
 define <8 x i16> @variable_insertelement(<8 x i16> %a, i16 %b, i32 %c) nounwind readnone {
-;CHECK: variable_insertelement:
+;CHECK-LABEL: variable_insertelement:
     %r = insertelement <8 x i16> %a, i16 %b, i32 %c
     ret <8 x i16> %r
 }
diff --git a/test/CodeGen/ARM/vsub.ll b/test/CodeGen/ARM/vsub.ll
index df77bb3..89c3095 100644
--- a/test/CodeGen/ARM/vsub.ll
+++ b/test/CodeGen/ARM/vsub.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubi8:
+;CHECK-LABEL: vsubi8:
 ;CHECK: vsub.i8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubi16:
+;CHECK-LABEL: vsubi16:
 ;CHECK: vsub.i16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -19,7 +19,7 @@ define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubi32:
+;CHECK-LABEL: vsubi32:
 ;CHECK: vsub.i32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -28,7 +28,7 @@ define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsubi64:
+;CHECK-LABEL: vsubi64:
 ;CHECK: vsub.i64
 	%tmp1 = load <1 x i64>* %A
 	%tmp2 = load <1 x i64>* %B
@@ -37,7 +37,7 @@ define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
 }
 
 define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vsubf32:
+;CHECK-LABEL: vsubf32:
 ;CHECK: vsub.f32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = load <2 x float>* %B
@@ -46,7 +46,7 @@ define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsubQi8:
+;CHECK-LABEL: vsubQi8:
 ;CHECK: vsub.i8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -55,7 +55,7 @@ define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsubQi16:
+;CHECK-LABEL: vsubQi16:
 ;CHECK: vsub.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -64,7 +64,7 @@ define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsubQi32:
+;CHECK-LABEL: vsubQi32:
 ;CHECK: vsub.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -73,7 +73,7 @@ define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsubQi64:
+;CHECK-LABEL: vsubQi64:
 ;CHECK: vsub.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -82,7 +82,7 @@ define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
 }
 
 define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vsubQf32:
+;CHECK-LABEL: vsubQf32:
 ;CHECK: vsub.f32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = load <4 x float>* %B
@@ -91,7 +91,7 @@ define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
 }
 
 define <8 x i8> @vsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsubhni16:
+;CHECK-LABEL: vsubhni16:
 ;CHECK: vsubhn.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -100,7 +100,7 @@ define <8 x i8> @vsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i16> @vsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsubhni32:
+;CHECK-LABEL: vsubhni32:
 ;CHECK: vsubhn.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -109,7 +109,7 @@ define <4 x i16> @vsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsubhni64:
+;CHECK-LABEL: vsubhni64:
 ;CHECK: vsubhn.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -122,7 +122,7 @@ declare <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind rea
 declare <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrsubhni16:
+;CHECK-LABEL: vrsubhni16:
 ;CHECK: vrsubhn.i16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i16>* %B
@@ -131,7 +131,7 @@ define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrsubhni32:
+;CHECK-LABEL: vrsubhni32:
 ;CHECK: vrsubhn.i32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -140,7 +140,7 @@ define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <2 x i32> @vrsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrsubhni64:
+;CHECK-LABEL: vrsubhni64:
 ;CHECK: vrsubhn.i64
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i64>* %B
@@ -153,7 +153,7 @@ declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind re
 declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
 
 define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubls8:
+;CHECK-LABEL: vsubls8:
 ;CHECK: vsubl.s8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -164,7 +164,7 @@ define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubls16:
+;CHECK-LABEL: vsubls16:
 ;CHECK: vsubl.s16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -175,7 +175,7 @@ define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubls32:
+;CHECK-LABEL: vsubls32:
 ;CHECK: vsubl.s32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -186,7 +186,7 @@ define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsublu8:
+;CHECK-LABEL: vsublu8:
 ;CHECK: vsubl.u8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -197,7 +197,7 @@ define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsublu16:
+;CHECK-LABEL: vsublu16:
 ;CHECK: vsubl.u16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -208,7 +208,7 @@ define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsublu32:
+;CHECK-LABEL: vsublu32:
 ;CHECK: vsubl.u32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -219,7 +219,7 @@ define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubws8:
+;CHECK-LABEL: vsubws8:
 ;CHECK: vsubw.s8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -229,7 +229,7 @@ define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubws16:
+;CHECK-LABEL: vsubws16:
 ;CHECK: vsubw.s16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -239,7 +239,7 @@ define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubws32:
+;CHECK-LABEL: vsubws32:
 ;CHECK: vsubw.s32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
@@ -249,7 +249,7 @@ define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubwu8:
+;CHECK-LABEL: vsubwu8:
 ;CHECK: vsubw.u8
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -259,7 +259,7 @@ define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubwu16:
+;CHECK-LABEL: vsubwu16:
 ;CHECK: vsubw.u16
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -269,7 +269,7 @@ define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubwu32:
+;CHECK-LABEL: vsubwu32:
 ;CHECK: vsubw.u32
 	%tmp1 = load <2 x i64>* %A
 	%tmp2 = load <2 x i32>* %B
diff --git a/test/CodeGen/ARM/vtbl.ll b/test/CodeGen/ARM/vtbl.ll
index 9264987..21614b0 100644
--- a/test/CodeGen/ARM/vtbl.ll
+++ b/test/CodeGen/ARM/vtbl.ll
@@ -5,7 +5,7 @@
 %struct.__neon_int8x8x4_t = type { <8 x i8>,  <8 x i8>,  <8 x i8>, <8 x i8> }
 
 define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtbl1:
+;CHECK-LABEL: vtbl1:
 ;CHECK: vtbl.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -14,7 +14,7 @@ define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind {
-;CHECK: vtbl2:
+;CHECK-LABEL: vtbl2:
 ;CHECK: vtbl.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load %struct.__neon_int8x8x2_t* %B
@@ -25,7 +25,7 @@ define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind {
 }
 
 define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind {
-;CHECK: vtbl3:
+;CHECK-LABEL: vtbl3:
 ;CHECK: vtbl.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load %struct.__neon_int8x8x3_t* %B
@@ -37,7 +37,7 @@ define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind {
 }
 
 define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind {
-;CHECK: vtbl4:
+;CHECK-LABEL: vtbl4:
 ;CHECK: vtbl.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load %struct.__neon_int8x8x4_t* %B
@@ -50,7 +50,7 @@ define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind {
 }
 
 define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx1:
+;CHECK-LABEL: vtbx1:
 ;CHECK: vtbx.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -60,7 +60,7 @@ define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 }
 
 define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx2:
+;CHECK-LABEL: vtbx2:
 ;CHECK: vtbx.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load %struct.__neon_int8x8x2_t* %B
@@ -72,7 +72,7 @@ define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C
 }
 
 define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx3:
+;CHECK-LABEL: vtbx3:
 ;CHECK: vtbx.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load %struct.__neon_int8x8x3_t* %B
@@ -85,7 +85,7 @@ define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C
 }
 
 define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx4:
+;CHECK-LABEL: vtbx4:
 ;CHECK: vtbx.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load %struct.__neon_int8x8x4_t* %B
diff --git a/test/CodeGen/ARM/vtrn.ll b/test/CodeGen/ARM/vtrn.ll
index b1c2f93..7d101bc 100644
--- a/test/CodeGen/ARM/vtrn.ll
+++ b/test/CodeGen/ARM/vtrn.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtrni8:
+;CHECK-LABEL: vtrni8:
 ;CHECK: vtrn.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <8 x i8>* %A
@@ -13,7 +13,7 @@ define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vtrni16:
+;CHECK-LABEL: vtrni16:
 ;CHECK: vtrn.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <4 x i16>* %A
@@ -25,7 +25,7 @@ define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vtrni32:
+;CHECK-LABEL: vtrni32:
 ;CHECK: vtrn.32
 ;CHECK-NEXT: vadd.i32
 	%tmp1 = load <2 x i32>* %A
@@ -37,7 +37,7 @@ define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 }
 
 define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vtrnf:
+;CHECK-LABEL: vtrnf:
 ;CHECK: vtrn.32
 ;CHECK-NEXT: vadd.f32
 	%tmp1 = load <2 x float>* %A
@@ -49,7 +49,7 @@ define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
 }
 
 define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vtrnQi8:
+;CHECK-LABEL: vtrnQi8:
 ;CHECK: vtrn.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <16 x i8>* %A
@@ -61,7 +61,7 @@ define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vtrnQi16:
+;CHECK-LABEL: vtrnQi16:
 ;CHECK: vtrn.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <8 x i16>* %A
@@ -73,7 +73,7 @@ define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vtrnQi32:
+;CHECK-LABEL: vtrnQi32:
 ;CHECK: vtrn.32
 ;CHECK-NEXT: vadd.i32
 	%tmp1 = load <4 x i32>* %A
@@ -85,7 +85,7 @@ define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vtrnQf:
+;CHECK-LABEL: vtrnQf:
 ;CHECK: vtrn.32
 ;CHECK-NEXT: vadd.f32
 	%tmp1 = load <4 x float>* %A
@@ -99,7 +99,7 @@ define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
 ; Undef shuffle indices should not prevent matching to VTRN:
 
 define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtrni8_undef:
+;CHECK-LABEL: vtrni8_undef:
 ;CHECK: vtrn.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <8 x i8>* %A
@@ -111,7 +111,7 @@ define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vtrnQi16_undef:
+;CHECK-LABEL: vtrnQi16_undef:
 ;CHECK: vtrn.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <8 x i16>* %A
diff --git a/test/CodeGen/ARM/vuzp.ll b/test/CodeGen/ARM/vuzp.ll
index 9130f62..2d193c1 100644
--- a/test/CodeGen/ARM/vuzp.ll
+++ b/test/CodeGen/ARM/vuzp.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vuzpi8:
+;CHECK-LABEL: vuzpi8:
 ;CHECK: vuzp.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <8 x i8>* %A
@@ -13,7 +13,7 @@ define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vuzpi16:
+;CHECK-LABEL: vuzpi16:
 ;CHECK: vuzp.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <4 x i16>* %A
@@ -27,7 +27,7 @@ define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
 
 define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vuzpQi8:
+;CHECK-LABEL: vuzpQi8:
 ;CHECK: vuzp.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <16 x i8>* %A
@@ -39,7 +39,7 @@ define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vuzpQi16:
+;CHECK-LABEL: vuzpQi16:
 ;CHECK: vuzp.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <8 x i16>* %A
@@ -51,7 +51,7 @@ define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vuzpQi32:
+;CHECK-LABEL: vuzpQi32:
 ;CHECK: vuzp.32
 ;CHECK-NEXT: vadd.i32
 	%tmp1 = load <4 x i32>* %A
@@ -63,7 +63,7 @@ define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vuzpQf:
+;CHECK-LABEL: vuzpQf:
 ;CHECK: vuzp.32
 ;CHECK-NEXT: vadd.f32
 	%tmp1 = load <4 x float>* %A
@@ -77,7 +77,7 @@ define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
 ; Undef shuffle indices should not prevent matching to VUZP:
 
 define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vuzpi8_undef:
+;CHECK-LABEL: vuzpi8_undef:
 ;CHECK: vuzp.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <8 x i8>* %A
@@ -89,7 +89,7 @@ define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vuzpQi16_undef:
+;CHECK-LABEL: vuzpQi16_undef:
 ;CHECK: vuzp.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <8 x i16>* %A
diff --git a/test/CodeGen/ARM/vzip.ll b/test/CodeGen/ARM/vzip.ll
index 926970a..f71aef7 100644
--- a/test/CodeGen/ARM/vzip.ll
+++ b/test/CodeGen/ARM/vzip.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vzipi8:
+;CHECK-LABEL: vzipi8:
 ;CHECK: vzip.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <8 x i8>* %A
@@ -13,7 +13,7 @@ define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vzipi16:
+;CHECK-LABEL: vzipi16:
 ;CHECK: vzip.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <4 x i16>* %A
@@ -27,7 +27,7 @@ define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
 
 define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vzipQi8:
+;CHECK-LABEL: vzipQi8:
 ;CHECK: vzip.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <16 x i8>* %A
@@ -39,7 +39,7 @@ define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vzipQi16:
+;CHECK-LABEL: vzipQi16:
 ;CHECK: vzip.16
 ;CHECK-NEXT: vadd.i16
 	%tmp1 = load <8 x i16>* %A
@@ -51,7 +51,7 @@ define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vzipQi32:
+;CHECK-LABEL: vzipQi32:
 ;CHECK: vzip.32
 ;CHECK-NEXT: vadd.i32
 	%tmp1 = load <4 x i32>* %A
@@ -63,7 +63,7 @@ define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 }
 
 define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vzipQf:
+;CHECK-LABEL: vzipQf:
 ;CHECK: vzip.32
 ;CHECK-NEXT: vadd.f32
 	%tmp1 = load <4 x float>* %A
@@ -77,7 +77,7 @@ define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
 ; Undef shuffle indices should not prevent matching to VZIP:
 
 define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vzipi8_undef:
+;CHECK-LABEL: vzipi8_undef:
 ;CHECK: vzip.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <8 x i8>* %A
@@ -89,7 +89,7 @@ define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vzipQi8_undef:
+;CHECK-LABEL: vzipQi8_undef:
 ;CHECK: vzip.8
 ;CHECK-NEXT: vadd.i8
 	%tmp1 = load <16 x i8>* %A
diff --git a/test/CodeGen/Generic/dbg_value.ll b/test/CodeGen/Generic/dbg_value.ll
index ce3364d..840eeb0 100644
--- a/test/CodeGen/Generic/dbg_value.ll
+++ b/test/CodeGen/Generic/dbg_value.ll
@@ -10,4 +10,5 @@ define void @t(%0*, i32, i32, i32, i32) nounwind {
 
 declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
-!0 = metadata !{i32 0} ;
+; !0 should conform to the format of DIVariable.
+!0 = metadata !{i32 786689, null, metadata !"a", null, i32 0, null, i32 0, i32 0} ;
diff --git a/test/CodeGen/Hexagon/adde.ll b/test/CodeGen/Hexagon/adde.ll
index 9cee3e2..6d060c1 100644
--- a/test/CodeGen/Hexagon/adde.ll
+++ b/test/CodeGen/Hexagon/adde.ll
@@ -31,4 +31,4 @@ entry:
         %tmp2122 = trunc i128 %tmp21 to i64
         store i64 %tmp2122, i64* %RH
         ret void
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/Hexagon/hwloop-dbg.ll b/test/CodeGen/Hexagon/hwloop-dbg.ll
index 17fe7b9..fce6d19 100644
--- a/test/CodeGen/Hexagon/hwloop-dbg.ll
+++ b/test/CodeGen/Hexagon/hwloop-dbg.ll
@@ -34,28 +34,29 @@ for.end:                                          ; preds = %for.body
 declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 
-!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"hwloop-dbg.c", metadata !"/usr2/kparzysz/s.hex/t", metadata !"QuIC LLVM Hexagon Clang version 6.1-pre-unknown, (git://git-hexagon-aus.quicinc.com/llvm/clang-mainline.git e9382867661454cdf44addb39430741578e9765c) (llvm/llvm-mainline.git 36412bb1fcf03ed426d4437b41198bae066675ac)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c] [DW_LANG_C99]
-!1 = metadata !{metadata !2}
+!llvm.dbg.cu = !{!0}
+
+!0 = metadata !{i32 786449, metadata !28, i32 12, metadata !"QuIC LLVM Hexagon Clang version 6.1-pre-unknown, (git://git-hexagon-aus.quicinc.com/llvm/clang-mainline.git e9382867661454cdf44addb39430741578e9765c) (llvm/llvm-mainline.git 36412bb1fcf03ed426d4437b41198bae066675ac)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, null, metadata !""} ; [ DW_TAG_compile_unit ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c] [DW_LANG_C99]
 !2 = metadata !{i32 0}
-!3 = metadata !{metadata !4}
-!4 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, i32 0, metadata !6, metadata !"foo", metadata !"foo", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void (i32*, i32*)* @foo, null, null, metadata !11, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
-!6 = metadata !{i32 786473, metadata !"hwloop-dbg.c", metadata !"/usr2/kparzysz/s.hex/t", null} ; [ DW_TAG_file_type ]
+!3 = metadata !{metadata !5}
+!5 = metadata !{i32 786478, metadata !28, null, metadata !"foo", metadata !"foo", metadata !"", i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void (i32*, i32*)* @foo, null, null, metadata !11, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
+!6 = metadata !{i32 786473, metadata !28} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !8 = metadata !{null, metadata !9, metadata !9}
-!9 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from int]
-!10 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from int]
+!10 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
 !11 = metadata !{metadata !12}
 !12 = metadata !{metadata !13, metadata !14, metadata !15}
 !13 = metadata !{i32 786689, metadata !5, metadata !"a", metadata !6, i32 16777217, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [a] [line 1]
 !14 = metadata !{i32 786689, metadata !5, metadata !"b", metadata !6, i32 33554433, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [b] [line 1]
 !15 = metadata !{i32 786688, metadata !16, metadata !"i", metadata !6, i32 2, metadata !10, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 2]
-!16 = metadata !{i32 786443, metadata !5, i32 1, i32 26, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c]
+!16 = metadata !{i32 786443, metadata !28, metadata !5, i32 1, i32 26, i32 0} ; [ DW_TAG_lexical_block ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c]
 !17 = metadata !{i32 1, i32 15, metadata !5, null}
 !18 = metadata !{i32 1, i32 23, metadata !5, null}
 !19 = metadata !{i32 3, i32 8, metadata !20, null}
-!20 = metadata !{i32 786443, metadata !16, i32 3, i32 3, metadata !6, i32 1} ; [ DW_TAG_lexical_block ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c]
+!20 = metadata !{i32 786443, metadata !28, metadata !16, i32 3, i32 3, i32 1} ; [ DW_TAG_lexical_block ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c]
 !21 = metadata !{i32 4, i32 5, metadata !22, null}
-!22 = metadata !{i32 786443, metadata !20, i32 3, i32 28, metadata !6, i32 2} ; [ DW_TAG_lexical_block ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c]
+!22 = metadata !{i32 786443, metadata !28, metadata !20, i32 3, i32 28, i32 2} ; [ DW_TAG_lexical_block ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c]
 !26 = metadata !{i32 3, i32 23, metadata !20, null}
 !27 = metadata !{i32 6, i32 1, metadata !16, null}
+!28 = metadata !{metadata !"hwloop-dbg.c", metadata !"/usr2/kparzysz/s.hex/t"}
diff --git a/test/CodeGen/Hexagon/i16_VarArg.ll b/test/CodeGen/Hexagon/i16_VarArg.ll
index eb44c29..c5d05a5 100644
--- a/test/CodeGen/Hexagon/i16_VarArg.ll
+++ b/test/CodeGen/Hexagon/i16_VarArg.ll
@@ -37,4 +37,4 @@ define i32 @main() {
         %ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0
         call i32 (i8*, ...)* @printf( i8* %lt_s, i16 %val1 )
         ret i32 0
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/Hexagon/i1_VarArg.ll b/test/CodeGen/Hexagon/i1_VarArg.ll
index 7dbfb25..37f2778 100644
--- a/test/CodeGen/Hexagon/i1_VarArg.ll
+++ b/test/CodeGen/Hexagon/i1_VarArg.ll
@@ -41,4 +41,4 @@ define i32 @main() {
         call i32 (i8*, ...)* @printf( i8* %eq_s, i1 %eq_r )
         call i32 (i8*, ...)* @printf( i8* %ne_s, i1 %ne_r )
         ret i32 0
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/Hexagon/i8_VarArg.ll b/test/CodeGen/Hexagon/i8_VarArg.ll
index 687b178..6f056ff 100644
--- a/test/CodeGen/Hexagon/i8_VarArg.ll
+++ b/test/CodeGen/Hexagon/i8_VarArg.ll
@@ -37,4 +37,4 @@ define i32 @main() {
         %ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0
         call i32 (i8*, ...)* @printf( i8* %lt_s, i8 %val1 )
         ret i32 0
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/Hexagon/indirect-br.ll b/test/CodeGen/Hexagon/indirect-br.ll
index 919e501..188eebf 100644
--- a/test/CodeGen/Hexagon/indirect-br.ll
+++ b/test/CodeGen/Hexagon/indirect-br.ll
@@ -11,4 +11,4 @@ test_label:
 
 ret:
         ret i32 -1
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/Hexagon/sube.ll b/test/CodeGen/Hexagon/sube.ll
index 84172e9..735ac9e 100644
--- a/test/CodeGen/Hexagon/sube.ll
+++ b/test/CodeGen/Hexagon/sube.ll
@@ -26,4 +26,4 @@ entry:
         %tmp2122 = trunc i128 %tmp21 to i64
         store i64 %tmp2122, i64* %RH
         ret void
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/Hexagon/tail-call-trunc.ll b/test/CodeGen/Hexagon/tail-call-trunc.ll
new file mode 100644
index 0000000..98214c7
--- /dev/null
+++ b/test/CodeGen/Hexagon/tail-call-trunc.ll
@@ -0,0 +1,28 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+declare i32 @ret_i32()
+
+define i8 @test_i8() {
+; CHECK-LABEL: test_i8:
+; CHECK: jump ret_i32
+  %res = tail call i32 @ret_i32()
+  %val = trunc i32 %res to i8
+  ret i8 %val
+}
+
+define i16 @test_i16() {
+; CHECK-LABEL: test_i16:
+; CHECK: jump ret_i32
+  %res = tail call i32 @ret_i32()
+  %val = trunc i32 %res to i16
+  ret i16 %val
+}
+
+declare i64 @ret_i64()
+define i32 @test_i32() {
+; CHECK-LABEL: test_i32:
+; CHECK: call ret_i64
+  %res = tail call i64 @ret_i64()
+  %val = trunc i64 %res to i32
+  ret i32 42
+}
diff --git a/test/CodeGen/Hexagon/zextloadi1.ll b/test/CodeGen/Hexagon/zextloadi1.ll
index cb6e6fd..b58d933 100644
--- a/test/CodeGen/Hexagon/zextloadi1.ll
+++ b/test/CodeGen/Hexagon/zextloadi1.ll
@@ -22,4 +22,4 @@ define void @i65_ls() nounwind  {
         %tmp = load i65* @i65_l
         store i65 %tmp, i65* @i65_s
         ret void
-}
\ No newline at end of file
+}
diff --git a/test/CodeGen/Inputs/DbgValueOtherTargets.ll b/test/CodeGen/Inputs/DbgValueOtherTargets.ll
index d5162b9..f35a5d1 100644
--- a/test/CodeGen/Inputs/DbgValueOtherTargets.ll
+++ b/test/CodeGen/Inputs/DbgValueOtherTargets.ll
@@ -13,15 +13,15 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !12, metadata !1, metadata !"main", metadata !"main", metadata !"", i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !12} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 2.9 (trunk 120996)", i1 false, metadata !"", i32 0, null, null, metadata !11, null, null} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 786449, metadata !12, i32 12, metadata !"clang version 2.9 (trunk 120996)", i1 false, metadata !"", i32 0, metadata !6, metadata !6, metadata !11, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !12, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 786468, metadata !12, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !6 = metadata !{i32 0}
 !7 = metadata !{i32 786688, metadata !8, metadata !"i", metadata !1, i32 3, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!8 = metadata !{i32 786443, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ]
+!8 = metadata !{i32 786443, metadata !12, metadata !0, i32 2, i32 12, i32 0} ; [ DW_TAG_lexical_block ]
 !9 = metadata !{i32 3, i32 11, metadata !8, null}
 !10 = metadata !{i32 4, i32 2, metadata !8, null}
 !11 = metadata !{metadata !0}
diff --git a/test/CodeGen/MBlaze/DbgValueOtherTargets.test b/test/CodeGen/MBlaze/DbgValueOtherTargets.test
deleted file mode 100644
index 8b850f5..0000000
--- a/test/CodeGen/MBlaze/DbgValueOtherTargets.test
+++ /dev/null
@@ -1 +0,0 @@
-RUN: llc -O0 -march=mblaze -asm-verbose < %S/../Inputs/DbgValueOtherTargets.ll | FileCheck %S/../Inputs/DbgValueOtherTargets.ll
diff --git a/test/CodeGen/MBlaze/brind.ll b/test/CodeGen/MBlaze/brind.ll
deleted file mode 100644
index 2229a87..0000000
--- a/test/CodeGen/MBlaze/brind.ll
+++ /dev/null
@@ -1,72 +0,0 @@
-; Ensure that the select instruction is supported and is lowered to 
-; some sort of branch instruction.
-;
-; RUN: llc < %s -march=mblaze -mattr=+mul,+fpu,+barrel | FileCheck %s
-
-declare i32 @printf(i8*, ...)
-@MSG = internal constant [13 x i8] c"Message: %d\0A\00"
-
-@BLKS = private constant [5 x i8*]
-    [ i8* blockaddress(@brind, %L1),
-      i8* blockaddress(@brind, %L2),
-      i8* blockaddress(@brind, %L3),
-      i8* blockaddress(@brind, %L4),
-      i8* blockaddress(@brind, %L5) ]
-
-define i32 @brind(i32 %a, i32 %b)
-{
-    ; CHECK:        brind:
-entry:
-    br label %loop
-
-loop:
-    %tmp.0 = phi i32 [ 0, %entry ], [ %tmp.8, %finish ]
-    %dst.0 = getelementptr [5 x i8*]* @BLKS, i32 0, i32 %tmp.0
-    %dst.1 = load i8** %dst.0
-    indirectbr i8* %dst.1, [ label %L1,
-                             label %L2,
-                             label %L3,
-                             label %L4,
-                             label %L5 ]
-    ; CHECK:        brad {{r[0-9]*}}
-
-L1:
-    %tmp.1 = add i32 %a, %b
-    br label %finish
-    ; CHECK:        brid
-
-L2:
-    %tmp.2 = sub i32 %a, %b
-    br label %finish
-    ; CHECK:        brid
-
-L3:
-    %tmp.3 = mul i32 %a, %b
-    br label %finish
-    ; CHECK:        brid
-
-L4:
-    %tmp.4 = sdiv i32 %a, %b
-    br label %finish
-    ; CHECK:        brid
-
-L5:
-    %tmp.5 = srem i32 %a, %b
-    br label %finish
-
-finish:
-    %tmp.6 = phi i32 [ %tmp.1, %L1 ],
-                     [ %tmp.2, %L2 ],
-                     [ %tmp.3, %L3 ],
-                     [ %tmp.4, %L4 ],
-                     [ %tmp.5, %L5 ]
-
-    call i32 (i8*,...)* @printf( i8* getelementptr([13 x i8]* @MSG,i32 0,i32 0),
-                                 i32 %tmp.6)
-
-    %tmp.7 = add i32 %tmp.0, 1
-    %tmp.8 = urem i32 %tmp.7, 5
-
-    br label %loop
-    ; CHECK:        brad {{r[0-9]*}}
-}
diff --git a/test/CodeGen/MBlaze/callind.ll b/test/CodeGen/MBlaze/callind.ll
deleted file mode 100644
index bfc8d00..0000000
--- a/test/CodeGen/MBlaze/callind.ll
+++ /dev/null
@@ -1,80 +0,0 @@
-; Ensure that indirect calls work and that they are lowered to some
-; sort of branch and link instruction.
-;
-; RUN: llc < %s -march=mblaze -mattr=+mul,+fpu,+barrel | FileCheck %s
-
-declare i32 @printf(i8*, ...)
-@MSG = internal constant [13 x i8] c"Message: %d\0A\00"
-
-@FUNS = private constant [5 x i32 (i32,i32)*]
-    [ i32 (i32,i32)* @doadd,
-      i32 (i32,i32)* @dosub,
-      i32 (i32,i32)* @domul,
-      i32 (i32,i32)* @dodiv,
-      i32 (i32,i32)* @dorem ]
-
-define i32 @doadd(i32 %a, i32 %b)
-{
-    ; CHECK:        doadd:
-    %tmp.0 = add i32 %a, %b
-    ret i32 %tmp.0
-    ; CHECK:        rtsd
-}
-
-define i32 @dosub(i32 %a, i32 %b)
-{
-    ; CHECK:        dosub:
-    %tmp.0 = sub i32 %a, %b
-    ret i32 %tmp.0
-    ; CHECK:        rtsd
-}
-
-define i32 @domul(i32 %a, i32 %b)
-{
-    ; CHECK:        domul:
-    %tmp.0 = mul i32 %a, %b
-    ret i32 %tmp.0
-    ; CHECK:        rtsd
-}
-
-define i32 @dodiv(i32 %a, i32 %b)
-{
-    ; CHECK:        dodiv:
-    %tmp.0 = sdiv i32 %a, %b
-    ret i32 %tmp.0
-    ; CHECK:        rtsd
-}
-
-define i32 @dorem(i32 %a, i32 %b)
-{
-    ; CHECK:        dorem:
-    %tmp.0 = srem i32 %a, %b
-    ret i32 %tmp.0
-    ; CHECK:        rtsd
-}
-
-define i32 @callind(i32 %a, i32 %b)
-{
-    ; CHECK:        callind:
-entry:
-    br label %loop
-
-loop:
-    %tmp.0 = phi i32 [ 0, %entry ], [ %tmp.3, %loop ]
-    %dst.0 = getelementptr [5 x i32 (i32,i32)*]* @FUNS, i32 0, i32 %tmp.0
-    %dst.1 = load i32 (i32,i32)** %dst.0
-    %tmp.1 = call i32 %dst.1(i32 %a, i32 %b)
-    ; CHECK-NOT:    brli
-    ; CHECK-NOT:    brlai
-    ; CHECK:        brl
-
-    call i32 (i8*,...)* @printf( i8* getelementptr([13 x i8]* @MSG,i32 0,i32 0),
-                                 i32 %tmp.1)
-    ; CHECK:        brl
-
-    %tmp.2 = add i32 %tmp.0, 1
-    %tmp.3 = urem i32 %tmp.2, 5
-
-    br label %loop
-    ; CHECK:        br
-}
diff --git a/test/CodeGen/MBlaze/cc.ll b/test/CodeGen/MBlaze/cc.ll
deleted file mode 100644
index 827fd32..0000000
--- a/test/CodeGen/MBlaze/cc.ll
+++ /dev/null
@@ -1,266 +0,0 @@
-; Test some of the calling convention lowering done by the MBlaze backend.
-; We test that integer values are passed in the correct registers and
-; returned in the correct registers. Additionally, we test that the stack
-; is used as appropriate for passing arguments that cannot be placed into
-; registers.
-;
-; RUN: llc < %s -march=mblaze | FileCheck %s
-
-declare i32 @printf(i8*, ...)
-@MSG = internal constant [13 x i8] c"Message: %d\0A\00"
-
-define void @params0_noret() {
-    ; CHECK:        params0_noret:
-    ret void
-    ; CHECK-NOT:    {{.* r3, .*, .*}}
-    ; CHECK-NOT:    {{.* r4, .*, .*}}
-    ; CHECK:        rtsd
-}
-
-define i8 @params0_8bitret() {
-    ; CHECK:        params0_8bitret:
-    ret i8 1
-    ; CHECK-NOT:    {{.* r3, .*, .*}}
-    ; CHECK-NOT:    {{.* r4, .*, .*}}
-    ; CHECK:        rtsd
-    ; CHECK:        {{.* r3, r0, 1}}
-}
-
-define i16 @params0_16bitret() {
-    ; CHECK:        params0_16bitret:
-    ret i16 1
-    ; CHECK:        rtsd
-    ; CHECK:        {{.* r3, r0, 1}}
-    ; CHECK-NOT:    {{.* r4, .*, .*}}
-}
-
-define i32 @params0_32bitret() {
-    ; CHECK:        params0_32bitret:
-    ret i32 1
-    ; CHECK-NOT:    {{.* r4, .*, .*}}
-    ; CHECK:        rtsd
-    ; CHECK:        {{.* r3, r0, 1}}
-}
-
-define i64 @params0_64bitret() {
-    ; CHECK:        params0_64bitret:
-    ret i64 1
-    ; CHECK:        {{.* r3, r0, .*}}
-    ; CHECK:        rtsd
-    ; CHECK:        {{.* r4, r0, 1}}
-}
-
-define i32 @params1_32bitret(i32 %a) {
-    ; CHECK:        params1_32bitret:
-    ret i32 %a
-    ; CHECK-NOT:    {{.* r3, .*, .*}}
-    ; CHECK-NOT:    {{.* r4, .*, .*}}
-    ; CHECK:        rtsd
-    ; CHECK:        {{.* r3, r5, r0}}
-}
-
-define i32 @params2_32bitret(i32 %a, i32 %b) {
-    ; CHECK:        params2_32bitret:
-    ret i32 %b
-    ; CHECK-NOT:    {{.* r3, .*, .*}}
-    ; CHECK-NOT:    {{.* r4, .*, .*}}
-    ; CHECK:        rtsd
-    ; CHECK:        {{.* r3, r6, r0}}
-}
-
-define i32 @params3_32bitret(i32 %a, i32 %b, i32 %c) {
-    ; CHECK:        params3_32bitret:
-    ret i32 %c
-    ; CHECK-NOT:    {{.* r3, .*, .*}}
-    ; CHECK-NOT:    {{.* r4, .*, .*}}
-    ; CHECK:        rtsd
-    ; CHECK:        {{.* r3, r7, r0}}
-}
-
-define i32 @params4_32bitret(i32 %a, i32 %b, i32 %c, i32 %d) {
-    ; CHECK:        params4_32bitret:
-    ret i32 %d
-    ; CHECK-NOT:    {{.* r3, .*, .*}}
-    ; CHECK-NOT:    {{.* r4, .*, .*}}
-    ; CHECK:        rtsd
-    ; CHECK:        {{.* r3, r8, r0}}
-}
-
-define i32 @params5_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
-    ; CHECK:        params5_32bitret:
-    ret i32 %e
-    ; CHECK-NOT:    {{.* r3, .*, .*}}
-    ; CHECK-NOT:    {{.* r4, .*, .*}}
-    ; CHECK:        rtsd
-    ; CHECK:        {{.* r3, r9, r0}}
-}
-
-define i32 @params6_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) {
-    ; CHECK:        params6_32bitret:
-    ret i32 %f
-    ; CHECK-NOT:    {{.* r3, .*, .*}}
-    ; CHECK-NOT:    {{.* r4, .*, .*}}
-    ; CHECK:        rtsd
-    ; CHECK:        {{.* r3, r10, r0}}
-}
-
-define i32 @params7_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
-                             i32 %g) {
-    ; CHECK:        params7_32bitret:
-    ret i32 %g
-    ; CHECK:        {{lwi? r3, r1, 32}}
-    ; CHECK-NOT:    {{.* r4, .*, .*}}
-    ; CHECK:        rtsd
-}
-
-define i32 @params8_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
-                             i32 %g, i32 %h) {
-    ; CHECK:        params8_32bitret:
-    ret i32 %h
-    ; CHECK:        {{lwi? r3, r1, 36}}
-    ; CHECK-NOT:    {{.* r4, .*, .*}}
-    ; CHECK:        rtsd
-}
-
-define i32 @params9_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
-                             i32 %g, i32 %h, i32 %i) {
-    ; CHECK:        params9_32bitret:
-    ret i32 %i
-    ; CHECK:        {{lwi? r3, r1, 40}}
-    ; CHECK-NOT:    {{.* r4, .*, .*}}
-    ; CHECK:        rtsd
-}
-
-define i32 @params10_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
-                              i32 %g, i32 %h, i32 %i, i32 %j) {
-    ; CHECK:        params10_32bitret:
-    ret i32 %j
-    ; CHECK:        {{lwi? r3, r1, 44}}
-    ; CHECK-NOT:    {{.* r4, .*, .*}}
-    ; CHECK:        rtsd
-}
-
-define void @testing() {
-    %MSG.1 = getelementptr [13 x i8]* @MSG, i32 0, i32 0
-
-    call void @params0_noret()
-    ; CHECK:        brlid
-
-    %tmp.1 = call i8 @params0_8bitret()
-    ; CHECK:        brlid
-    call i32 (i8*,...)* @printf(i8* %MSG.1, i8 %tmp.1)
-
-    %tmp.2 = call i16 @params0_16bitret()
-    ; CHECK:        brlid
-    call i32 (i8*,...)* @printf(i8* %MSG.1, i16 %tmp.2)
-
-    %tmp.3 = call i32 @params0_32bitret()
-    ; CHECK:        brlid
-    call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.3)
-
-    %tmp.4 = call i64 @params0_64bitret()
-    ; CHECK:        brlid
-    call i32 (i8*,...)* @printf(i8* %MSG.1, i64 %tmp.4)
-
-    %tmp.5 = call i32 @params1_32bitret(i32 1)
-    ; CHECK:        {{.* r5, .*, .*}}
-    ; CHECK:        brlid
-    call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.5)
-
-    %tmp.6 = call i32 @params2_32bitret(i32 1, i32 2)
-    ; CHECK:        {{.* r5, .*, .*}}
-    ; CHECK:        {{.* r6, .*, .*}}
-    ; CHECK:        brlid
-    call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.6)
-
-    %tmp.7 = call i32 @params3_32bitret(i32 1, i32 2, i32 3)
-    ; CHECK:        {{.* r5, .*, .*}}
-    ; CHECK:        {{.* r6, .*, .*}}
-    ; CHECK:        {{.* r7, .*, .*}}
-    ; CHECK:        brlid
-    call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.7)
-
-    %tmp.8 = call i32 @params4_32bitret(i32 1, i32 2, i32 3, i32 4)
-    ; CHECK:        {{.* r5, .*, .*}}
-    ; CHECK:        {{.* r6, .*, .*}}
-    ; CHECK:        {{.* r7, .*, .*}}
-    ; CHECK:        {{.* r8, .*, .*}}
-    ; CHECK:        brlid
-    call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.8)
-
-    %tmp.9 = call i32 @params5_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5)
-    ; CHECK:        {{.* r5, .*, .*}}
-    ; CHECK:        {{.* r6, .*, .*}}
-    ; CHECK:        {{.* r7, .*, .*}}
-    ; CHECK:        {{.* r8, .*, .*}}
-    ; CHECK:        {{.* r9, .*, .*}}
-    ; CHECK:        brlid
-    call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.9)
-
-    %tmp.10 = call i32 @params6_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
-                                         i32 6)
-    ; CHECK:        {{.* r5, .*, .*}}
-    ; CHECK:        {{.* r6, .*, .*}}
-    ; CHECK:        {{.* r7, .*, .*}}
-    ; CHECK:        {{.* r8, .*, .*}}
-    ; CHECK:        {{.* r9, .*, .*}}
-    ; CHECK:        {{.* r10, .*, .*}}
-    ; CHECK:        brlid
-    call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.10)
-
-    %tmp.11 = call i32 @params7_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
-                                         i32 6, i32 7)
-    ; CHECK:        {{swi? .*, r1, 28}}
-    ; CHECK:        {{.* r5, .*, .*}}
-    ; CHECK:        {{.* r6, .*, .*}}
-    ; CHECK:        {{.* r7, .*, .*}}
-    ; CHECK:        {{.* r8, .*, .*}}
-    ; CHECK:        {{.* r9, .*, .*}}
-    ; CHECK:        {{.* r10, .*, .*}}
-    ; CHECK:        brlid
-    call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.11)
-
-    %tmp.12 = call i32 @params8_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
-                                         i32 6, i32 7, i32 8)
-    ; CHECK:        {{swi? .*, r1, 32}}
-    ; CHECK:        {{swi? .*, r1, 28}}
-    ; CHECK:        {{.* r5, .*, .*}}
-    ; CHECK:        {{.* r6, .*, .*}}
-    ; CHECK:        {{.* r7, .*, .*}}
-    ; CHECK:        {{.* r8, .*, .*}}
-    ; CHECK:        {{.* r9, .*, .*}}
-    ; CHECK:        {{.* r10, .*, .*}}
-    ; CHECK:        brlid
-    call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.12)
-
-    %tmp.13 = call i32 @params9_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
-                                         i32 6, i32 7, i32 8, i32 9)
-    ; CHECK:        {{swi? .*, r1, 36}}
-    ; CHECK:        {{swi? .*, r1, 32}}
-    ; CHECK:        {{swi? .*, r1, 28}}
-    ; CHECK:        {{.* r5, .*, .*}}
-    ; CHECK:        {{.* r6, .*, .*}}
-    ; CHECK:        {{.* r7, .*, .*}}
-    ; CHECK:        {{.* r8, .*, .*}}
-    ; CHECK:        {{.* r9, .*, .*}}
-    ; CHECK:        {{.* r10, .*, .*}}
-    ; CHECK:        brlid
-    call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.13)
-
-    %tmp.14 = call i32 @params10_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
-                                          i32 6, i32 7, i32 8, i32 9, i32 10)
-    ; CHECK:        {{swi? .*, r1, 40}}
-    ; CHECK:        {{swi? .*, r1, 36}}
-    ; CHECK:        {{swi? .*, r1, 32}}
-    ; CHECK:        {{swi? .*, r1, 28}}
-    ; CHECK:        {{.* r5, .*, .*}}
-    ; CHECK:        {{.* r6, .*, .*}}
-    ; CHECK:        {{.* r7, .*, .*}}
-    ; CHECK:        {{.* r8, .*, .*}}
-    ; CHECK:        {{.* r9, .*, .*}}
-    ; CHECK:        {{.* r10, .*, .*}}
-    ; CHECK:        brlid
-    call i32 (i8*,...)* @printf(i8* %MSG.1, i32 %tmp.14)
-
-    ret void
-}
diff --git a/test/CodeGen/MBlaze/div.ll b/test/CodeGen/MBlaze/div.ll
deleted file mode 100644
index 621784a..0000000
--- a/test/CodeGen/MBlaze/div.ll
+++ /dev/null
@@ -1,75 +0,0 @@
-; Ensure that multiplication is lowered to function calls when the multiplier
-; unit is not available in the hardware and that function calls are not used
-; when the multiplier unit is available in the hardware.
-;
-; RUN: llc < %s -march=mblaze | FileCheck -check-prefix=FUN %s
-; RUN: llc < %s -march=mblaze -mattr=+div | FileCheck -check-prefix=DIV %s
-
-define i8 @test_i8(i8 %a, i8 %b) {
-    ; FUN:        test_i8:
-    ; DIV:        test_i8:
-
-    %tmp.1 = udiv i8 %a, %b
-    ; FUN-NOT:    idiv
-    ; FUN:        brlid
-    ; DIV-NOT:    brlid
-    ; DIV:        idiv
-
-    %tmp.2 = sdiv i8 %a, %b
-    ; FUN-NOT:    idiv
-    ; FUN:        brlid
-    ; DIV-NOT:    brlid
-    ; DIV-NOT:    idiv
-    ; DIV:        idivu
-
-    %tmp.3 = add i8 %tmp.1, %tmp.2
-    ret i8 %tmp.3
-    ; FUN:        rtsd
-    ; DIV:        rtsd
-}
-
-define i16 @test_i16(i16 %a, i16 %b) {
-    ; FUN:        test_i16:
-    ; DIV:        test_i16:
-
-    %tmp.1 = udiv i16 %a, %b
-    ; FUN-NOT:    idiv
-    ; FUN:        brlid
-    ; DIV-NOT:    brlid
-    ; DIV:        idiv
-
-    %tmp.2 = sdiv i16 %a, %b
-    ; FUN-NOT:    idiv
-    ; FUN:        brlid
-    ; DIV-NOT:    brlid
-    ; DIV-NOT:    idiv
-    ; DIV:        idivu
-
-    %tmp.3 = add i16 %tmp.1, %tmp.2
-    ret i16 %tmp.3
-    ; FUN:        rtsd
-    ; DIV:        rtsd
-}
-
-define i32 @test_i32(i32 %a, i32 %b) {
-    ; FUN:        test_i32:
-    ; DIV:        test_i32:
-
-    %tmp.1 = udiv i32 %a, %b
-    ; FUN-NOT:    idiv
-    ; FUN:        brlid
-    ; DIV-NOT:    brlid
-    ; DIV:        idiv
-
-    %tmp.2 = sdiv i32 %a, %b
-    ; FUN-NOT:    idiv
-    ; FUN:        brlid
-    ; DIV-NOT:    brlid
-    ; DIV-NOT:    idiv
-    ; DIV:        idivu
-
-    %tmp.3 = add i32 %tmp.1, %tmp.2
-    ret i32 %tmp.3
-    ; FUN:        rtsd
-    ; DIV:        rtsd
-}
diff --git a/test/CodeGen/MBlaze/fpu.ll b/test/CodeGen/MBlaze/fpu.ll
deleted file mode 100644
index 2aef4fd..0000000
--- a/test/CodeGen/MBlaze/fpu.ll
+++ /dev/null
@@ -1,66 +0,0 @@
-; Ensure that floating point operations are lowered to function calls when the
-; FPU is not available in the hardware and that function calls are not used
-; when the FPU is available in the hardware.
-;
-; RUN: llc < %s -march=mblaze | FileCheck -check-prefix=FUN %s
-; RUN: llc < %s -march=mblaze -mattr=+fpu | FileCheck -check-prefix=FPU %s
-
-define float @test_add(float %a, float %b) {
-    ; FUN:        test_add:
-    ; FPU:        test_add:
-
-    %tmp.1 = fadd float %a, %b
-    ; FUN:        brlid
-    ; FPU-NOT:    brlid
-
-    ret float %tmp.1
-    ; FUN:        rtsd
-    ; FPU:        rtsd
-    ; FUN-NOT:    fadd
-    ; FPU-NEXT:   fadd
-}
-
-define float @test_sub(float %a, float %b) {
-    ; FUN:        test_sub:
-    ; FPU:        test_sub:
-
-    %tmp.1 = fsub float %a, %b
-    ; FUN:        brlid
-    ; FPU-NOT:    brlid
-
-    ret float %tmp.1
-    ; FUN:        rtsd
-    ; FPU:        rtsd
-    ; FUN-NOT:    frsub
-    ; FPU-NEXT:   frsub
-}
-
-define float @test_mul(float %a, float %b) {
-    ; FUN:        test_mul:
-    ; FPU:        test_mul:
-
-    %tmp.1 = fmul float %a, %b
-    ; FUN:        brlid
-    ; FPU-NOT:    brlid
-
-    ret float %tmp.1
-    ; FUN:        rtsd
-    ; FPU:        rtsd
-    ; FUN-NOT:    fmul
-    ; FPU-NEXT:   fmul
-}
-
-define float @test_div(float %a, float %b) {
-    ; FUN:        test_div:
-    ; FPU:        test_div:
-
-    %tmp.1 = fdiv float %a, %b
-    ; FUN:        brlid
-    ; FPU-NOT:    brlid
-
-    ret float %tmp.1
-    ; FUN:        rtsd
-    ; FPU:        rtsd
-    ; FUN-NOT:    fdiv
-    ; FPU-NEXT:   fdiv
-}
diff --git a/test/CodeGen/MBlaze/fsl.ll b/test/CodeGen/MBlaze/fsl.ll
deleted file mode 100644
index 5444f82..0000000
--- a/test/CodeGen/MBlaze/fsl.ll
+++ /dev/null
@@ -1,319 +0,0 @@
-; Ensure that the FSL instrinsic instruction generate single FSL instructions
-; at the machine level. Additionally, ensure that dynamic values use the
-; dynamic version of the instructions and that constant values use the
-; constant version of the instructions.
-;
-; RUN: llc -O3 < %s -march=mblaze | FileCheck %s
-
-declare i32 @llvm.mblaze.fsl.get(i32 %port)
-declare i32 @llvm.mblaze.fsl.aget(i32 %port)
-declare i32 @llvm.mblaze.fsl.cget(i32 %port)
-declare i32 @llvm.mblaze.fsl.caget(i32 %port)
-declare i32 @llvm.mblaze.fsl.eget(i32 %port)
-declare i32 @llvm.mblaze.fsl.eaget(i32 %port)
-declare i32 @llvm.mblaze.fsl.ecget(i32 %port)
-declare i32 @llvm.mblaze.fsl.ecaget(i32 %port)
-declare i32 @llvm.mblaze.fsl.nget(i32 %port)
-declare i32 @llvm.mblaze.fsl.naget(i32 %port)
-declare i32 @llvm.mblaze.fsl.ncget(i32 %port)
-declare i32 @llvm.mblaze.fsl.ncaget(i32 %port)
-declare i32 @llvm.mblaze.fsl.neget(i32 %port)
-declare i32 @llvm.mblaze.fsl.neaget(i32 %port)
-declare i32 @llvm.mblaze.fsl.necget(i32 %port)
-declare i32 @llvm.mblaze.fsl.necaget(i32 %port)
-declare i32 @llvm.mblaze.fsl.tget(i32 %port)
-declare i32 @llvm.mblaze.fsl.taget(i32 %port)
-declare i32 @llvm.mblaze.fsl.tcget(i32 %port)
-declare i32 @llvm.mblaze.fsl.tcaget(i32 %port)
-declare i32 @llvm.mblaze.fsl.teget(i32 %port)
-declare i32 @llvm.mblaze.fsl.teaget(i32 %port)
-declare i32 @llvm.mblaze.fsl.tecget(i32 %port)
-declare i32 @llvm.mblaze.fsl.tecaget(i32 %port)
-declare i32 @llvm.mblaze.fsl.tnget(i32 %port)
-declare i32 @llvm.mblaze.fsl.tnaget(i32 %port)
-declare i32 @llvm.mblaze.fsl.tncget(i32 %port)
-declare i32 @llvm.mblaze.fsl.tncaget(i32 %port)
-declare i32 @llvm.mblaze.fsl.tneget(i32 %port)
-declare i32 @llvm.mblaze.fsl.tneaget(i32 %port)
-declare i32 @llvm.mblaze.fsl.tnecget(i32 %port)
-declare i32 @llvm.mblaze.fsl.tnecaget(i32 %port)
-
-declare void @llvm.mblaze.fsl.put(i32 %value, i32 %port)
-declare void @llvm.mblaze.fsl.aput(i32 %value, i32 %port)
-declare void @llvm.mblaze.fsl.cput(i32 %value, i32 %port)
-declare void @llvm.mblaze.fsl.caput(i32 %value, i32 %port)
-declare void @llvm.mblaze.fsl.nput(i32 %value, i32 %port)
-declare void @llvm.mblaze.fsl.naput(i32 %value, i32 %port)
-declare void @llvm.mblaze.fsl.ncput(i32 %value, i32 %port)
-declare void @llvm.mblaze.fsl.ncaput(i32 %value, i32 %port)
-declare void @llvm.mblaze.fsl.tput(i32 %port)
-declare void @llvm.mblaze.fsl.taput(i32 %port)
-declare void @llvm.mblaze.fsl.tcput(i32 %port)
-declare void @llvm.mblaze.fsl.tcaput(i32 %port)
-declare void @llvm.mblaze.fsl.tnput(i32 %port)
-declare void @llvm.mblaze.fsl.tnaput(i32 %port)
-declare void @llvm.mblaze.fsl.tncput(i32 %port)
-declare void @llvm.mblaze.fsl.tncaput(i32 %port)
-
-define void @fsl_get(i32 %port) {
-    ; CHECK:        fsl_get:
-    %v0  = call i32 @llvm.mblaze.fsl.get(i32 %port)
-    ; CHECK:        getd
-    %v1  = call i32 @llvm.mblaze.fsl.aget(i32 %port)
-    ; CHECK-NEXT:   agetd
-    %v2  = call i32 @llvm.mblaze.fsl.cget(i32 %port)
-    ; CHECK-NEXT:   cgetd
-    %v3  = call i32 @llvm.mblaze.fsl.caget(i32 %port)
-    ; CHECK-NEXT:   cagetd
-    %v4  = call i32 @llvm.mblaze.fsl.eget(i32 %port)
-    ; CHECK-NEXT:   egetd
-    %v5  = call i32 @llvm.mblaze.fsl.eaget(i32 %port)
-    ; CHECK-NEXT:   eagetd
-    %v6  = call i32 @llvm.mblaze.fsl.ecget(i32 %port)
-    ; CHECK-NEXT:   ecgetd
-    %v7  = call i32 @llvm.mblaze.fsl.ecaget(i32 %port)
-    ; CHECK-NEXT:   ecagetd
-    %v8  = call i32 @llvm.mblaze.fsl.nget(i32 %port)
-    ; CHECK-NEXT:   ngetd
-    %v9  = call i32 @llvm.mblaze.fsl.naget(i32 %port)
-    ; CHECK-NEXT:   nagetd
-    %v10 = call i32 @llvm.mblaze.fsl.ncget(i32 %port)
-    ; CHECK-NEXT:   ncgetd
-    %v11 = call i32 @llvm.mblaze.fsl.ncaget(i32 %port)
-    ; CHECK-NEXT:   ncagetd
-    %v12 = call i32 @llvm.mblaze.fsl.neget(i32 %port)
-    ; CHECK-NEXT:   negetd
-    %v13 = call i32 @llvm.mblaze.fsl.neaget(i32 %port)
-    ; CHECK-NEXT:   neagetd
-    %v14 = call i32 @llvm.mblaze.fsl.necget(i32 %port)
-    ; CHECK-NEXT:   necgetd
-    %v15 = call i32 @llvm.mblaze.fsl.necaget(i32 %port)
-    ; CHECK-NEXT:   necagetd
-    %v16 = call i32 @llvm.mblaze.fsl.tget(i32 %port)
-    ; CHECK-NEXT:   tgetd
-    %v17 = call i32 @llvm.mblaze.fsl.taget(i32 %port)
-    ; CHECK-NEXT:   tagetd
-    %v18 = call i32 @llvm.mblaze.fsl.tcget(i32 %port)
-    ; CHECK-NEXT:   tcgetd
-    %v19 = call i32 @llvm.mblaze.fsl.tcaget(i32 %port)
-    ; CHECK-NEXT:   tcagetd
-    %v20 = call i32 @llvm.mblaze.fsl.teget(i32 %port)
-    ; CHECK-NEXT:   tegetd
-    %v21 = call i32 @llvm.mblaze.fsl.teaget(i32 %port)
-    ; CHECK-NEXT:   teagetd
-    %v22 = call i32 @llvm.mblaze.fsl.tecget(i32 %port)
-    ; CHECK-NEXT:   tecgetd
-    %v23 = call i32 @llvm.mblaze.fsl.tecaget(i32 %port)
-    ; CHECK-NEXT:   tecagetd
-    %v24 = call i32 @llvm.mblaze.fsl.tnget(i32 %port)
-    ; CHECK-NEXT:   tngetd
-    %v25 = call i32 @llvm.mblaze.fsl.tnaget(i32 %port)
-    ; CHECK-NEXT:   tnagetd
-    %v26 = call i32 @llvm.mblaze.fsl.tncget(i32 %port)
-    ; CHECK-NEXT:   tncgetd
-    %v27 = call i32 @llvm.mblaze.fsl.tncaget(i32 %port)
-    ; CHECK-NEXT:   tncagetd
-    %v28 = call i32 @llvm.mblaze.fsl.tneget(i32 %port)
-    ; CHECK-NEXT:   tnegetd
-    %v29 = call i32 @llvm.mblaze.fsl.tneaget(i32 %port)
-    ; CHECK-NEXT:   tneagetd
-    %v30 = call i32 @llvm.mblaze.fsl.tnecget(i32 %port)
-    ; CHECK-NEXT:   tnecgetd
-    %v31 = call i32 @llvm.mblaze.fsl.tnecaget(i32 %port)
-    ; CHECK-NEXT:   tnecagetd
-    ret void
-    ; CHECK:        rtsd
-}
-
-define void @fslc_get() {
-    ; CHECK:        fslc_get:
-    %v0  = call i32 @llvm.mblaze.fsl.get(i32 1)
-    ; CHECK:        get
-    %v1  = call i32 @llvm.mblaze.fsl.aget(i32 1)
-    ; CHECK-NOT:    agetd
-    ; CHECK:        aget
-    %v2  = call i32 @llvm.mblaze.fsl.cget(i32 1)
-    ; CHECK-NOT:    cgetd
-    ; CHECK:        cget
-    %v3  = call i32 @llvm.mblaze.fsl.caget(i32 1)
-    ; CHECK-NOT:    cagetd
-    ; CHECK:        caget
-    %v4  = call i32 @llvm.mblaze.fsl.eget(i32 1)
-    ; CHECK-NOT:    egetd
-    ; CHECK:        eget
-    %v5  = call i32 @llvm.mblaze.fsl.eaget(i32 1)
-    ; CHECK-NOT:    eagetd
-    ; CHECK:        eaget
-    %v6  = call i32 @llvm.mblaze.fsl.ecget(i32 1)
-    ; CHECK-NOT:    ecgetd
-    ; CHECK:        ecget
-    %v7  = call i32 @llvm.mblaze.fsl.ecaget(i32 1)
-    ; CHECK-NOT:    ecagetd
-    ; CHECK:        ecaget
-    %v8  = call i32 @llvm.mblaze.fsl.nget(i32 1)
-    ; CHECK-NOT:    ngetd
-    ; CHECK:        nget
-    %v9  = call i32 @llvm.mblaze.fsl.naget(i32 1)
-    ; CHECK-NOT:    nagetd
-    ; CHECK:        naget
-    %v10 = call i32 @llvm.mblaze.fsl.ncget(i32 1)
-    ; CHECK-NOT:    ncgetd
-    ; CHECK:        ncget
-    %v11 = call i32 @llvm.mblaze.fsl.ncaget(i32 1)
-    ; CHECK-NOT:    ncagetd
-    ; CHECK:        ncaget
-    %v12 = call i32 @llvm.mblaze.fsl.neget(i32 1)
-    ; CHECK-NOT:    negetd
-    ; CHECK:        neget
-    %v13 = call i32 @llvm.mblaze.fsl.neaget(i32 1)
-    ; CHECK-NOT:    neagetd
-    ; CHECK:        neaget
-    %v14 = call i32 @llvm.mblaze.fsl.necget(i32 1)
-    ; CHECK-NOT:    necgetd
-    ; CHECK:        necget
-    %v15 = call i32 @llvm.mblaze.fsl.necaget(i32 1)
-    ; CHECK-NOT:    necagetd
-    ; CHECK:        necaget
-    %v16 = call i32 @llvm.mblaze.fsl.tget(i32 1)
-    ; CHECK-NOT:    tgetd
-    ; CHECK:        tget
-    %v17 = call i32 @llvm.mblaze.fsl.taget(i32 1)
-    ; CHECK-NOT:    tagetd
-    ; CHECK:        taget
-    %v18 = call i32 @llvm.mblaze.fsl.tcget(i32 1)
-    ; CHECK-NOT:    tcgetd
-    ; CHECK:        tcget
-    %v19 = call i32 @llvm.mblaze.fsl.tcaget(i32 1)
-    ; CHECK-NOT:    tcagetd
-    ; CHECK:        tcaget
-    %v20 = call i32 @llvm.mblaze.fsl.teget(i32 1)
-    ; CHECK-NOT:    tegetd
-    ; CHECK:        teget
-    %v21 = call i32 @llvm.mblaze.fsl.teaget(i32 1)
-    ; CHECK-NOT:    teagetd
-    ; CHECK:        teaget
-    %v22 = call i32 @llvm.mblaze.fsl.tecget(i32 1)
-    ; CHECK-NOT:    tecgetd
-    ; CHECK:        tecget
-    %v23 = call i32 @llvm.mblaze.fsl.tecaget(i32 1)
-    ; CHECK-NOT:    tecagetd
-    ; CHECK:        tecaget
-    %v24 = call i32 @llvm.mblaze.fsl.tnget(i32 1)
-    ; CHECK-NOT:    tngetd
-    ; CHECK:        tnget
-    %v25 = call i32 @llvm.mblaze.fsl.tnaget(i32 1)
-    ; CHECK-NOT:    tnagetd
-    ; CHECK:        tnaget
-    %v26 = call i32 @llvm.mblaze.fsl.tncget(i32 1)
-    ; CHECK-NOT:    tncgetd
-    ; CHECK:        tncget
-    %v27 = call i32 @llvm.mblaze.fsl.tncaget(i32 1)
-    ; CHECK-NOT:    tncagetd
-    ; CHECK:        tncaget
-    %v28 = call i32 @llvm.mblaze.fsl.tneget(i32 1)
-    ; CHECK-NOT:    tnegetd
-    ; CHECK:        tneget
-    %v29 = call i32 @llvm.mblaze.fsl.tneaget(i32 1)
-    ; CHECK-NOT:    tneagetd
-    ; CHECK:        tneaget
-    %v30 = call i32 @llvm.mblaze.fsl.tnecget(i32 1)
-    ; CHECK-NOT:    tnecgetd
-    ; CHECK:        tnecget
-    %v31 = call i32 @llvm.mblaze.fsl.tnecaget(i32 1)
-    ; CHECK-NOT:    tnecagetd
-    ; CHECK:        tnecaget
-    ret void
-    ; CHECK:        rtsd
-}
-
-define void @putfsl(i32 %value, i32 %port) {
-    ; CHECK:        putfsl:
-    call void @llvm.mblaze.fsl.put(i32 %value, i32 %port)
-    ; CHECK:        putd
-    call void @llvm.mblaze.fsl.aput(i32 %value, i32 %port)
-    ; CHECK-NEXT:   aputd
-    call void @llvm.mblaze.fsl.cput(i32 %value, i32 %port)
-    ; CHECK-NEXT:   cputd
-    call void @llvm.mblaze.fsl.caput(i32 %value, i32 %port)
-    ; CHECK-NEXT:   caputd
-    call void @llvm.mblaze.fsl.nput(i32 %value, i32 %port)
-    ; CHECK-NEXT:   nputd
-    call void @llvm.mblaze.fsl.naput(i32 %value, i32 %port)
-    ; CHECK-NEXT:   naputd
-    call void @llvm.mblaze.fsl.ncput(i32 %value, i32 %port)
-    ; CHECK-NEXT:   ncputd
-    call void @llvm.mblaze.fsl.ncaput(i32 %value, i32 %port)
-    ; CHECK-NEXT:   ncaputd
-    call void @llvm.mblaze.fsl.tput(i32 %port)
-    ; CHECK-NEXT:   tputd
-    call void @llvm.mblaze.fsl.taput(i32 %port)
-    ; CHECK-NEXT:   taputd
-    call void @llvm.mblaze.fsl.tcput(i32 %port)
-    ; CHECK-NEXT:   tcputd
-    call void @llvm.mblaze.fsl.tcaput(i32 %port)
-    ; CHECK-NEXT:   tcaputd
-    call void @llvm.mblaze.fsl.tnput(i32 %port)
-    ; CHECK-NEXT:   tnputd
-    call void @llvm.mblaze.fsl.tnaput(i32 %port)
-    ; CHECK-NEXT:   tnaputd
-    call void @llvm.mblaze.fsl.tncput(i32 %port)
-    ; CHECK-NEXT:   tncputd
-    call void @llvm.mblaze.fsl.tncaput(i32 %port)
-    ; CHECK-NEXT:   tncaputd
-    ret void
-    ; CHECK:        rtsd
-}
-
-define void @putfsl_const(i32 %value) {
-    ; CHECK:        putfsl_const:
-    call void @llvm.mblaze.fsl.put(i32 %value, i32 1)
-    ; CHECK-NOT:    putd
-    ; CHECK:        put
-    call void @llvm.mblaze.fsl.aput(i32 %value, i32 1)
-    ; CHECK-NOT:    aputd
-    ; CHECK:        aput
-    call void @llvm.mblaze.fsl.cput(i32 %value, i32 1)
-    ; CHECK-NOT:    cputd
-    ; CHECK:        cput
-    call void @llvm.mblaze.fsl.caput(i32 %value, i32 1)
-    ; CHECK-NOT:    caputd
-    ; CHECK:        caput
-    call void @llvm.mblaze.fsl.nput(i32 %value, i32 1)
-    ; CHECK-NOT:    nputd
-    ; CHECK:        nput
-    call void @llvm.mblaze.fsl.naput(i32 %value, i32 1)
-    ; CHECK-NOT:    naputd
-    ; CHECK:        naput
-    call void @llvm.mblaze.fsl.ncput(i32 %value, i32 1)
-    ; CHECK-NOT:    ncputd
-    ; CHECK:        ncput
-    call void @llvm.mblaze.fsl.ncaput(i32 %value, i32 1)
-    ; CHECK-NOT:    ncaputd
-    ; CHECK:        ncaput
-    call void @llvm.mblaze.fsl.tput(i32 1)
-    ; CHECK-NOT:    tputd
-    ; CHECK:        tput
-    call void @llvm.mblaze.fsl.taput(i32 1)
-    ; CHECK-NOT:    taputd
-    ; CHECK:        taput
-    call void @llvm.mblaze.fsl.tcput(i32 1)
-    ; CHECK-NOT:    tcputd
-    ; CHECK:        tcput
-    call void @llvm.mblaze.fsl.tcaput(i32 1)
-    ; CHECK-NOT:    tcaputd
-    ; CHECK:        tcaput
-    call void @llvm.mblaze.fsl.tnput(i32 1)
-    ; CHECK-NOT:    tnputd
-    ; CHECK:        tnput
-    call void @llvm.mblaze.fsl.tnaput(i32 1)
-    ; CHECK-NOT:    tnaputd
-    ; CHECK:        tnaput
-    call void @llvm.mblaze.fsl.tncput(i32 1)
-    ; CHECK-NOT:    tncputd
-    ; CHECK:        tncput
-    call void @llvm.mblaze.fsl.tncaput(i32 1)
-    ; CHECK-NOT:    tncaputd
-    ; CHECK:        tncaput
-    ret void
-    ; CHECK:        rtsd
-}
diff --git a/test/CodeGen/MBlaze/imm.ll b/test/CodeGen/MBlaze/imm.ll
deleted file mode 100644
index 6effd3e..0000000
--- a/test/CodeGen/MBlaze/imm.ll
+++ /dev/null
@@ -1,70 +0,0 @@
-; Ensure that all immediate values that are 32-bits or less can be loaded 
-; using a single instruction and that immediate values 64-bits or less can
-; be loaded using two instructions.
-;
-; RUN: llc < %s -march=mblaze | FileCheck %s
-; RUN: llc < %s -march=mblaze -mattr=+fpu | FileCheck -check-prefix=FPU %s
-
-define i8 @retimm_i8() {
-    ; CHECK:        retimm_i8:
-    ; CHECK:        rtsd
-    ; CHECK-NEXT:   add
-    ; FPU:          retimm_i8:
-    ; FPU:          rtsd
-    ; FPU-NEXT:     add
-    ret i8 123
-}
-
-define i16 @retimm_i16() {
-    ; CHECK:        retimm_i16:
-    ; CHECK:        rtsd
-    ; CHECK-NEXT:   add
-    ; FPU:          retimm_i16:
-    ; FPU:          rtsd
-    ; FPU-NEXT:     add
-    ret i16 31212
-}
-
-define i32 @retimm_i32() {
-    ; CHECK:        retimm_i32:
-    ; CHECK:        add
-    ; CHECK-NEXT:   rtsd
-    ; FPU:          retimm_i32:
-    ; FPU:          add
-    ; FPU-NEXT:     rtsd
-    ret i32 2938128
-}
-
-define i64 @retimm_i64() {
-    ; CHECK:        retimm_i64:
-    ; CHECK:        add
-    ; CHECK-NEXT:   rtsd
-    ; CHECK-NEXT:   add
-    ; FPU:          retimm_i64:
-    ; FPU:          add
-    ; FPU-NEXT:     rtsd
-    ; FPU-NEXT:     add
-    ret i64 94581823
-}
-
-define float @retimm_float() {
-    ; CHECK:        retimm_float:
-    ; CHECK:        add
-    ; CHECK-NEXT:   rtsd
-    ; FPU:          retimm_float:
-    ; FPU:          or
-    ; FPU-NEXT:     rtsd
-    ret float 12.0
-}
-
-define double @retimm_double() {
-    ; CHECK:        retimm_double:
-    ; CHECK:        add
-    ; CHECK-NEXT:   add
-    ; CHECK-NEXT:   rtsd
-    ; FPU:          retimm_double:
-    ; FPU:          add
-    ; FPU-NEXT:     add
-    ; FPU-NEXT:     rtsd
-    ret double 598382.39283873
-}
diff --git a/test/CodeGen/MBlaze/intr.ll b/test/CodeGen/MBlaze/intr.ll
deleted file mode 100644
index 79c6bff..0000000
--- a/test/CodeGen/MBlaze/intr.ll
+++ /dev/null
@@ -1,48 +0,0 @@
-; Ensure that the MBlaze interrupt_handler calling convention (cc73) is handled
-; correctly correctly by the MBlaze backend.
-;
-; RUN: llc < %s -march=mblaze | FileCheck %s
-
-@.str = private constant [28 x i8] c"The interrupt has gone off\0A\00"
-@_interrupt_handler = alias void ()* @myintr
-
-define cc73 void @myintr() nounwind noinline {
-  ; CHECK:        myintr:
-  ; CHECK:        swi   r3, r1
-  ; CHECK:        swi   r4, r1
-  ; CHECK:        swi   r5, r1
-  ; CHECK:        swi   r6, r1
-  ; CHECK:        swi   r7, r1
-  ; CHECK:        swi   r8, r1
-  ; CHECK:        swi   r9, r1
-  ; CHECK:        swi   r10, r1
-  ; CHECK:        swi   r11, r1
-  ; CHECK:        swi   r12, r1
-  ; CHECK:        swi   r17, r1
-  ; CHECK:        swi   r18, r1
-  ; CHECK:        mfs   r11, rmsr
-  ; CHECK:        swi   r11, r1
-  entry:
-    %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([28 x i8]* @.str, i32 0, i32 0))
-      ret void
-
-  ; CHECK:        lwi   r11, r1
-  ; CHECK:        mts   rmsr, r11
-  ; CHECK:        lwi   r18, r1
-  ; CHECK:        lwi   r17, r1
-  ; CHECK:        lwi   r12, r1
-  ; CHECK:        lwi   r11, r1
-  ; CHECK:        lwi   r10, r1
-  ; CHECK:        lwi   r9, r1
-  ; CHECK:        lwi   r8, r1
-  ; CHECK:        lwi   r7, r1
-  ; CHECK:        lwi   r6, r1
-  ; CHECK:        lwi   r5, r1
-  ; CHECK:        lwi   r4, r1
-  ; CHECK:        lwi   r3, r1
-  ; CHECK:        rtid  r14, 0
-}
-
-  ; CHECK:    .globl  _interrupt_handler
-  ; CHECK:    _interrupt_handler = myintr
-declare i32 @printf(i8*, ...)
diff --git a/test/CodeGen/MBlaze/jumptable.ll b/test/CodeGen/MBlaze/jumptable.ll
deleted file mode 100644
index 299084d..0000000
--- a/test/CodeGen/MBlaze/jumptable.ll
+++ /dev/null
@@ -1,79 +0,0 @@
-; Ensure that jump tables can be handled by the mblaze backend. The
-; jump table should be lowered to a "br" instruction using one of the
-; available registers.
-;
-; RUN: llc < %s -march=mblaze | FileCheck %s
-
-define i32 @jmptable(i32 %arg)
-{
-    ; CHECK:        jmptable:
-    switch i32 %arg, label %DEFAULT [ i32 0, label %L0
-                                      i32 1, label %L1
-                                      i32 2, label %L2
-                                      i32 3, label %L3
-                                      i32 4, label %L4
-                                      i32 5, label %L5
-                                      i32 6, label %L6
-                                      i32 7, label %L7
-                                      i32 8, label %L8
-                                      i32 9, label %L9 ]
-
-    ; CHECK:        lw   [[REG:r[0-9]*]]
-    ; CHECK:        brad [[REG]]
-L0:
-    %var0 = add i32 %arg, 0
-    br label %DONE
-
-L1:
-    %var1 = add i32 %arg, 1
-    br label %DONE
-
-L2:
-    %var2 = add i32 %arg, 2
-    br label %DONE
-
-L3:
-    %var3 = add i32 %arg, 3
-    br label %DONE
-
-L4:
-    %var4 = add i32 %arg, 4
-    br label %DONE
-
-L5:
-    %var5 = add i32 %arg, 5
-    br label %DONE
-
-L6:
-    %var6 = add i32 %arg, 6
-    br label %DONE
-
-L7:
-    %var7 = add i32 %arg, 7
-    br label %DONE
-
-L8:
-    %var8 = add i32 %arg, 8
-    br label %DONE
-
-L9:
-    %var9 = add i32 %arg, 9
-    br label %DONE
-
-DEFAULT:
-    unreachable
-
-DONE:
-    %rval = phi i32 [ %var0, %L0 ],
-                    [ %var1, %L1 ],
-                    [ %var2, %L2 ],
-                    [ %var3, %L3 ],
-                    [ %var4, %L4 ],
-                    [ %var5, %L5 ],
-                    [ %var6, %L6 ],
-                    [ %var7, %L7 ],
-                    [ %var8, %L8 ],
-                    [ %var9, %L9 ]
-    ret i32 %rval
-    ; CHECK:        rtsd
-}
diff --git a/test/CodeGen/MBlaze/lit.local.cfg b/test/CodeGen/MBlaze/lit.local.cfg
deleted file mode 100644
index ff4928d..0000000
--- a/test/CodeGen/MBlaze/lit.local.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-config.suffixes = ['.ll', '.c', '.cpp', '.test']
-
-targets = set(config.root.targets_to_build.split())
-if not 'MBlaze' in targets:
-    config.unsupported = True
-
diff --git a/test/CodeGen/MBlaze/loop.ll b/test/CodeGen/MBlaze/loop.ll
deleted file mode 100644
index 7439d0b..0000000
--- a/test/CodeGen/MBlaze/loop.ll
+++ /dev/null
@@ -1,44 +0,0 @@
-; Test some complicated looping constructs to ensure that they
-; compile successfully and that some sort of branching is used
-; in the resulting code.
-;
-; RUN: llc < %s -march=mblaze -mattr=+mul,+fpu,+barrel | FileCheck %s
-
-declare i32 @printf(i8*, ...)
-@MSG = internal constant [19 x i8] c"Message: %d %d %d\0A\00"
-
-define i32 @loop(i32 %a, i32 %b)
-{
-    ; CHECK:        loop:
-entry:
-    br label %loop_outer
-
-loop_outer:
-    %outer.0 = phi i32 [ 0, %entry ], [ %outer.2, %loop_outer_finish ]
-    br label %loop_inner
-
-loop_inner:
-    %inner.0 = phi i32 [ %a, %loop_outer ], [ %inner.3, %loop_inner_finish ]
-    %inner.1 = phi i32 [ %b, %loop_outer ], [ %inner.4, %loop_inner_finish ]
-    %inner.2 = phi i32 [  0, %loop_outer ], [ %inner.5, %loop_inner_finish ]
-    %inner.3 = add i32 %inner.0, %inner.1
-    %inner.4 = mul i32 %inner.2, 11
-    br label %loop_inner_finish
-
-loop_inner_finish:
-    %inner.5 = add i32 %inner.2, 1
-    call i32 (i8*,...)* @printf( i8* getelementptr([19 x i8]* @MSG,i32 0,i32 0),
-                                 i32 %inner.0, i32 %inner.1, i32 %inner.2 )
-
-    %inner.6 = icmp eq i32 %inner.5, 100
-    ; CHECK:        cmp [[REG:r[0-9]*]]
-
-    br i1 %inner.6, label %loop_inner, label %loop_outer_finish
-    ; CHECK:        {{beqid|bneid}} [[REG]]
-
-loop_outer_finish:
-    %outer.1 = add i32 %outer.0, 1
-    %outer.2 = urem i32 %outer.1, 1500
-    br label %loop_outer
-    ; CHECK:        br
-}
diff --git a/test/CodeGen/MBlaze/mul.ll b/test/CodeGen/MBlaze/mul.ll
deleted file mode 100644
index cefdb8d..0000000
--- a/test/CodeGen/MBlaze/mul.ll
+++ /dev/null
@@ -1,51 +0,0 @@
-; Ensure that multiplication is lowered to function calls when the multiplier
-; unit is not available in the hardware and that function calls are not used
-; when the multiplier unit is available in the hardware.
-;
-; RUN: llc < %s -march=mblaze | FileCheck -check-prefix=FUN %s
-; RUN: llc < %s -march=mblaze -mattr=+mul | FileCheck -check-prefix=MUL %s
-
-define i8 @test_i8(i8 %a, i8 %b) {
-    ; FUN:        test_i8:
-    ; MUL:        test_i8:
-
-    %tmp.1 = mul i8 %a, %b
-    ; FUN-NOT:    mul
-    ; FUN:        brlid
-    ; MUL-NOT:    brlid
-
-    ret i8 %tmp.1
-    ; FUN:        rtsd
-    ; MUL:        rtsd
-    ; MUL:        mul
-}
-
-define i16 @test_i16(i16 %a, i16 %b) {
-    ; FUN:        test_i16:
-    ; MUL:        test_i16:
-
-    %tmp.1 = mul i16 %a, %b
-    ; FUN-NOT:    mul
-    ; FUN:        brlid
-    ; MUL-NOT:    brlid
-
-    ret i16 %tmp.1
-    ; FUN:        rtsd
-    ; MUL:        rtsd
-    ; MUL:        mul
-}
-
-define i32 @test_i32(i32 %a, i32 %b) {
-    ; FUN:        test_i32:
-    ; MUL:        test_i32:
-
-    %tmp.1 = mul i32 %a, %b
-    ; FUN-NOT:    mul
-    ; FUN:        brlid
-    ; MUL-NOT:    brlid
-
-    ret i32 %tmp.1
-    ; FUN:        rtsd
-    ; MUL:        rtsd
-    ; MUL:        mul
-}
diff --git a/test/CodeGen/MBlaze/mul64.ll b/test/CodeGen/MBlaze/mul64.ll
deleted file mode 100644
index e0ef413..0000000
--- a/test/CodeGen/MBlaze/mul64.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; Ensure that multiplication is lowered to function calls when the 64-bit
-; multiplier unit is not available in the hardware and that function calls
-; are not used when the 64-bit multiplier unit is available in the hardware.
-;
-; RUN: llc < %s -march=mblaze | FileCheck -check-prefix=FUN %s
-; RUN: llc < %s -march=mblaze -mattr=+mul,+mul64 | \
-; RUN:      FileCheck -check-prefix=MUL %s
-
-define i64 @test_i64(i64 %a, i64 %b) {
-    ; FUN:        test_i64:
-    ; MUL:        test_i64:
-
-    %tmp.1 = mul i64 %a, %b
-    ; FUN-NOT:    mul
-    ; FUN:        brlid
-    ; MUL-NOT:    brlid
-    ; MUL:        mulh
-    ; MUL:        mul
-
-    ret i64 %tmp.1
-    ; FUN:        rtsd
-    ; MUL:        rtsd
-}
diff --git a/test/CodeGen/MBlaze/select.ll b/test/CodeGen/MBlaze/select.ll
deleted file mode 100644
index 47a88a1..0000000
--- a/test/CodeGen/MBlaze/select.ll
+++ /dev/null
@@ -1,15 +0,0 @@
-; Ensure that the select instruction is supported and is lowered to 
-; some sort of branch instruction.
-;
-; RUN: llc < %s -march=mblaze | FileCheck %s
-
-define i32 @testsel(i32 %a, i32 %b)
-{
-    ; CHECK:        testsel:
-    %tmp.1 = icmp eq i32 %a, %b
-    ; CHECK:        cmp
-    %tmp.2 = select i1 %tmp.1, i32 %a, i32 %b
-    ; CHECK:        {{bne|beq}}
-    ret i32 %tmp.2
-    ; CHECK:        rtsd
-}
diff --git a/test/CodeGen/MBlaze/shift.ll b/test/CodeGen/MBlaze/shift.ll
deleted file mode 100644
index 99f0519..0000000
--- a/test/CodeGen/MBlaze/shift.ll
+++ /dev/null
@@ -1,115 +0,0 @@
-; Ensure that shifts are lowered to loops when the barrel shifter unit is
-; not available in the hardware and that loops are not used when the
-; barrel shifter unit is available in the hardware.
-;
-; RUN: llc < %s -march=mblaze | FileCheck -check-prefix=FUN %s
-; RUN: llc < %s -march=mblaze -mattr=+barrel | FileCheck -check-prefix=SHT %s
-
-define i8 @test_i8(i8 %a, i8 %b) {
-    ; FUN:        test_i8:
-    ; SHT:        test_i8:
-
-    %tmp.1 = shl i8 %a, %b
-    ; FUN:        andi
-    ; FUN:        add
-    ; FUN:        bnei
-    ; SHT-NOT:    bnei
-
-    ret i8 %tmp.1
-    ; FUN:        rtsd
-    ; SHT:        rtsd
-    ; FUN-NOT:    bsll
-    ; SHT-NEXT:   bsll
-}
-
-define i8 @testc_i8(i8 %a, i8 %b) {
-    ; FUN:        testc_i8:
-    ; SHT:        testc_i8:
-
-    %tmp.1 = shl i8 %a, 5
-    ; FUN:        andi
-    ; FUN:        add
-    ; FUN:        bnei
-    ; SHT-NOT:    andi
-    ; SHT-NOT:    add
-    ; SHT-NOT:    bnei
-
-    ret i8 %tmp.1
-    ; FUN:        rtsd
-    ; SHT:        rtsd
-    ; FUN-NOT:    bsll
-    ; SHT-NEXT:   bslli
-}
-
-define i16 @test_i16(i16 %a, i16 %b) {
-    ; FUN:        test_i16:
-    ; SHT:        test_i16:
-
-    %tmp.1 = shl i16 %a, %b
-    ; FUN:        andi
-    ; FUN:        add
-    ; FUN:        bnei
-    ; SHT-NOT:    bnei
-
-    ret i16 %tmp.1
-    ; FUN:        rtsd
-    ; SHT:        rtsd
-    ; FUN-NOT:    bsll
-    ; SHT-NEXT:   bsll
-}
-
-define i16 @testc_i16(i16 %a, i16 %b) {
-    ; FUN:        testc_i16:
-    ; SHT:        testc_i16:
-
-    %tmp.1 = shl i16 %a, 5
-    ; FUN:        andi
-    ; FUN:        add
-    ; FUN:        bnei
-    ; SHT-NOT:    andi
-    ; SHT-NOT:    add
-    ; SHT-NOT:    bnei
-
-    ret i16 %tmp.1
-    ; FUN:        rtsd
-    ; SHT:        rtsd
-    ; FUN-NOT:    bsll
-    ; SHT-NEXT:   bslli
-}
-
-define i32 @test_i32(i32 %a, i32 %b) {
-    ; FUN:        test_i32:
-    ; SHT:        test_i32:
-
-    %tmp.1 = shl i32 %a, %b
-    ; FUN:        andi
-    ; FUN:        add
-    ; FUN:        bnei
-    ; SHT-NOT:    andi
-    ; SHT-NOT:    bnei
-
-    ret i32 %tmp.1
-    ; FUN:        rtsd
-    ; SHT:        rtsd
-    ; FUN-NOT:    bsll
-    ; SHT-NEXT:   bsll
-}
-
-define i32 @testc_i32(i32 %a, i32 %b) {
-    ; FUN:        testc_i32:
-    ; SHT:        testc_i32:
-
-    %tmp.1 = shl i32 %a, 5
-    ; FUN:        andi
-    ; FUN:        add
-    ; FUN:        bnei
-    ; SHT-NOT:    andi
-    ; SHT-NOT:    add
-    ; SHT-NOT:    bnei
-
-    ret i32 %tmp.1
-    ; FUN:        rtsd
-    ; SHT:        rtsd
-    ; FUN-NOT:    bsll
-    ; SHT-NEXT:   bslli
-}
diff --git a/test/CodeGen/MBlaze/svol.ll b/test/CodeGen/MBlaze/svol.ll
deleted file mode 100644
index c1e9620..0000000
--- a/test/CodeGen/MBlaze/svol.ll
+++ /dev/null
@@ -1,80 +0,0 @@
-; Ensure that the MBlaze save_volatiles calling convention (cc74) is handled
-; correctly correctly by the MBlaze backend.
-;
-; RUN: llc < %s -march=mblaze | FileCheck %s
-
-@.str = private constant [28 x i8] c"The interrupt has gone off\0A\00"
-
-define cc74 void @mysvol() nounwind noinline {
-  ; CHECK:        mysvol:
-  ; CHECK:        swi   r3, r1
-  ; CHECK:        swi   r4, r1
-  ; CHECK:        swi   r5, r1
-  ; CHECK:        swi   r6, r1
-  ; CHECK:        swi   r7, r1
-  ; CHECK:        swi   r8, r1
-  ; CHECK:        swi   r9, r1
-  ; CHECK:        swi   r10, r1
-  ; CHECK:        swi   r11, r1
-  ; CHECK:        swi   r12, r1
-  ; CHECK:        swi   r17, r1
-  ; CHECK:        swi   r18, r1
-  ; CHECK-NOT:    mfs   r11, rmsr
-  entry:
-    %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([28 x i8]* @.str, i32 0, i32 0))
-      ret void
-
-  ; CHECK-NOT:    mts   rmsr, r11
-  ; CHECK:        lwi   r18, r1
-  ; CHECK:        lwi   r17, r1
-  ; CHECK:        lwi   r12, r1
-  ; CHECK:        lwi   r11, r1
-  ; CHECK:        lwi   r10, r1
-  ; CHECK:        lwi   r9, r1
-  ; CHECK:        lwi   r8, r1
-  ; CHECK:        lwi   r7, r1
-  ; CHECK:        lwi   r6, r1
-  ; CHECK:        lwi   r5, r1
-  ; CHECK:        lwi   r4, r1
-  ; CHECK:        lwi   r3, r1
-  ; CHECK:        rtsd  r15, 8
-}
-
-define cc74 void @mysvol2() nounwind noinline {
-  ; CHECK:        mysvol2:
-  ; CHECK-NOT:    swi   r3, r1
-  ; CHECK-NOT:    swi   r4, r1
-  ; CHECK-NOT:    swi   r5, r1
-  ; CHECK-NOT:    swi   r6, r1
-  ; CHECK-NOT:    swi   r7, r1
-  ; CHECK-NOT:    swi   r8, r1
-  ; CHECK-NOT:    swi   r9, r1
-  ; CHECK-NOT:    swi   r10, r1
-  ; CHECK-NOT:    swi   r11, r1
-  ; CHECK-NOT:    swi   r12, r1
-  ; CHECK:        swi   r17, r1
-  ; CHECK:        swi   r18, r1
-  ; CHECK-NOT:    mfs   r11, rmsr
-entry:
-
-  ; CHECK-NOT:    mts   rmsr, r11
-  ; CHECK:        lwi   r18, r1
-  ; CHECK:        lwi   r17, r1
-  ; CHECK-NOT:    lwi   r12, r1
-  ; CHECK-NOT:    lwi   r11, r1
-  ; CHECK-NOT:    lwi   r10, r1
-  ; CHECK-NOT:    lwi   r9, r1
-  ; CHECK-NOT:    lwi   r8, r1
-  ; CHECK-NOT:    lwi   r7, r1
-  ; CHECK-NOT:    lwi   r6, r1
-  ; CHECK-NOT:    lwi   r5, r1
-  ; CHECK-NOT:    lwi   r4, r1
-  ; CHECK-NOT:    lwi   r3, r1
-  ; CHECK:        rtsd  r15, 8
-  ret void
-}
-
-  ; CHECK-NOT:    .globl  _interrupt_handler
-  ; CHECK-NOT:    _interrupt_handler = mysvol
-  ; CHECK-NOT:    _interrupt_handler = mysvol2
-declare i32 @printf(i8*, ...)
diff --git a/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll b/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll
index 94fe5c7..dce9d25 100644
--- a/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll
+++ b/test/CodeGen/MSP430/2009-11-05-8BitLibcalls.ll
@@ -7,7 +7,7 @@ target triple = "msp430-elf"
 
 define signext i8 @foo(i8 signext %_si1, i8 signext %_si2) nounwind readnone {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: call #__mulqi3
   %mul = mul i8 %_si2, %_si1                      ; <i8> [#uses=1]
   ret i8 %mul
diff --git a/test/CodeGen/MSP430/AddrMode-bis-rx.ll b/test/CodeGen/MSP430/AddrMode-bis-rx.ll
index c7ecb5a..44c92eb 100644
--- a/test/CodeGen/MSP430/AddrMode-bis-rx.ll
+++ b/test/CodeGen/MSP430/AddrMode-bis-rx.ll
@@ -7,7 +7,7 @@ define i16 @am1(i16 %x, i16* %a) nounwind {
 	%2 = or i16 %1,%x
 	ret i16 %2
 }
-; CHECK: am1:
+; CHECK-LABEL: am1:
 ; CHECK:		bis.w	0(r14), r15
 
 @foo = external global i16
@@ -17,7 +17,7 @@ define i16 @am2(i16 %x) nounwind {
 	%2 = or i16 %1,%x
 	ret i16 %2
 }
-; CHECK: am2:
+; CHECK-LABEL: am2:
 ; CHECK:		bis.w	&foo, r15
 
 @bar = internal constant [2 x i8] [ i8 32, i8 64 ]
@@ -28,7 +28,7 @@ define i8 @am3(i8 %x, i16 %n) nounwind {
 	%3 = or i8 %2,%x
 	ret i8 %3
 }
-; CHECK: am3:
+; CHECK-LABEL: am3:
 ; CHECK:		bis.b	bar(r14), r15
 
 define i16 @am4(i16 %x) nounwind {
@@ -36,7 +36,7 @@ define i16 @am4(i16 %x) nounwind {
 	%2 = or i16 %1,%x
 	ret i16 %2
 }
-; CHECK: am4:
+; CHECK-LABEL: am4:
 ; CHECK:		bis.w	&32, r15
 
 define i16 @am5(i16 %x, i16* %a) nounwind {
@@ -45,7 +45,7 @@ define i16 @am5(i16 %x, i16* %a) nounwind {
 	%3 = or i16 %2,%x
 	ret i16 %3
 }
-; CHECK: am5:
+; CHECK-LABEL: am5:
 ; CHECK:		bis.w	4(r14), r15
 
 %S = type { i16, i16 }
@@ -56,7 +56,7 @@ define i16 @am6(i16 %x) nounwind {
 	%2 = or i16 %1,%x
 	ret i16 %2
 }
-; CHECK: am6:
+; CHECK-LABEL: am6:
 ; CHECK:		bis.w	&baz+2, r15
 
 %T = type { i16, [2 x i8] }
@@ -69,6 +69,6 @@ define i8 @am7(i8 %x, i16 %n) nounwind {
 	%4 = or i8 %3,%x
 	ret i8 %4
 }
-; CHECK: am7:
+; CHECK-LABEL: am7:
 ; CHECK:		bis.b	duh+2(r14), r15
 
diff --git a/test/CodeGen/MSP430/AddrMode-bis-xr.ll b/test/CodeGen/MSP430/AddrMode-bis-xr.ll
index 727c29f..06a3d32 100644
--- a/test/CodeGen/MSP430/AddrMode-bis-xr.ll
+++ b/test/CodeGen/MSP430/AddrMode-bis-xr.ll
@@ -8,7 +8,7 @@ define void @am1(i16* %a, i16 %x) nounwind {
 	store i16 %2, i16* %a
 	ret void
 }
-; CHECK: am1:
+; CHECK-LABEL: am1:
 ; CHECK:		bis.w	r14, 0(r15)
 
 @foo = external global i16
@@ -19,7 +19,7 @@ define void @am2(i16 %x) nounwind {
 	store i16 %2, i16* @foo
 	ret void
 }
-; CHECK: am2:
+; CHECK-LABEL: am2:
 ; CHECK:		bis.w	r15, &foo
 
 @bar = external global [2 x i8]
@@ -31,7 +31,7 @@ define void @am3(i16 %i, i8 %x) nounwind {
 	store i8 %3, i8* %1
 	ret void
 }
-; CHECK: am3:
+; CHECK-LABEL: am3:
 ; CHECK:		bis.b	r14, bar(r15)
 
 define void @am4(i16 %x) nounwind {
@@ -40,7 +40,7 @@ define void @am4(i16 %x) nounwind {
 	store volatile i16 %2, i16* inttoptr(i16 32 to i16*)
 	ret void
 }
-; CHECK: am4:
+; CHECK-LABEL: am4:
 ; CHECK:		bis.w	r15, &32
 
 define void @am5(i16* %a, i16 %x) readonly {
@@ -50,7 +50,7 @@ define void @am5(i16* %a, i16 %x) readonly {
 	store i16 %3, i16* %1
 	ret void
 }
-; CHECK: am5:
+; CHECK-LABEL: am5:
 ; CHECK:		bis.w	r14, 4(r15)
 
 %S = type { i16, i16 }
@@ -62,7 +62,7 @@ define void @am6(i16 %x) nounwind {
 	store i16 %2, i16* getelementptr (%S* @baz, i32 0, i32 1)
 	ret void
 }
-; CHECK: am6:
+; CHECK-LABEL: am6:
 ; CHECK:		bis.w	r15, &baz+2
 
 %T = type { i16, [2 x i8] }
@@ -76,6 +76,6 @@ define void @am7(i16 %n, i8 %x) nounwind {
 	store i8 %4, i8* %2
 	ret void
 }
-; CHECK: am7:
+; CHECK-LABEL: am7:
 ; CHECK:		bis.b	r14, duh+2(r15)
 
diff --git a/test/CodeGen/MSP430/AddrMode-mov-rx.ll b/test/CodeGen/MSP430/AddrMode-mov-rx.ll
index 7cd345b..378b7ae 100644
--- a/test/CodeGen/MSP430/AddrMode-mov-rx.ll
+++ b/test/CodeGen/MSP430/AddrMode-mov-rx.ll
@@ -6,7 +6,7 @@ define i16 @am1(i16* %a) nounwind {
 	%1 = load i16* %a
 	ret i16 %1
 }
-; CHECK: am1:
+; CHECK-LABEL: am1:
 ; CHECK:		mov.w	0(r15), r15
 
 @foo = external global i16
@@ -15,7 +15,7 @@ define i16 @am2() nounwind {
 	%1 = load i16* @foo
 	ret i16 %1
 }
-; CHECK: am2:
+; CHECK-LABEL: am2:
 ; CHECK:		mov.w	&foo, r15
 
 @bar = internal constant [2 x i8] [ i8 32, i8 64 ]
@@ -25,14 +25,14 @@ define i8 @am3(i16 %n) nounwind {
 	%2 = load i8* %1
 	ret i8 %2
 }
-; CHECK: am3:
+; CHECK-LABEL: am3:
 ; CHECK:		mov.b	bar(r15), r15
 
 define i16 @am4() nounwind {
 	%1 = load volatile i16* inttoptr(i16 32 to i16*)
 	ret i16 %1
 }
-; CHECK: am4:
+; CHECK-LABEL: am4:
 ; CHECK:		mov.w	&32, r15
 
 define i16 @am5(i16* %a) nounwind {
@@ -40,7 +40,7 @@ define i16 @am5(i16* %a) nounwind {
 	%2 = load i16* %1
 	ret i16 %2
 }
-; CHECK: am5:
+; CHECK-LABEL: am5:
 ; CHECK:		mov.w	4(r15), r15
 
 %S = type { i16, i16 }
@@ -50,7 +50,7 @@ define i16 @am6() nounwind {
 	%1 = load i16* getelementptr (%S* @baz, i32 0, i32 1)
 	ret i16 %1
 }
-; CHECK: am6:
+; CHECK-LABEL: am6:
 ; CHECK:		mov.w	&baz+2, r15
 
 %T = type { i16, [2 x i8] }
@@ -62,6 +62,6 @@ define i8 @am7(i16 %n) nounwind {
 	%3= load i8* %2
 	ret i8 %3
 }
-; CHECK: am7:
+; CHECK-LABEL: am7:
 ; CHECK:		mov.b	duh+2(r15), r15
 
diff --git a/test/CodeGen/MSP430/AddrMode-mov-xr.ll b/test/CodeGen/MSP430/AddrMode-mov-xr.ll
index 5eeb02f..f55fd54 100644
--- a/test/CodeGen/MSP430/AddrMode-mov-xr.ll
+++ b/test/CodeGen/MSP430/AddrMode-mov-xr.ll
@@ -6,7 +6,7 @@ define void @am1(i16* %a, i16 %b) nounwind {
 	store i16 %b, i16* %a
 	ret void
 }
-; CHECK: am1:
+; CHECK-LABEL: am1:
 ; CHECK:		mov.w	r14, 0(r15)
 
 @foo = external global i16
@@ -15,7 +15,7 @@ define void @am2(i16 %a) nounwind {
 	store i16 %a, i16* @foo
 	ret void
 }
-; CHECK: am2:
+; CHECK-LABEL: am2:
 ; CHECK:		mov.w	r15, &foo
 
 @bar = external global [2 x i8]
@@ -25,14 +25,14 @@ define void @am3(i16 %i, i8 %a) nounwind {
 	store i8 %a, i8* %1
 	ret void
 }
-; CHECK: am3:
+; CHECK-LABEL: am3:
 ; CHECK:		mov.b	r14, bar(r15)
 
 define void @am4(i16 %a) nounwind {
 	store volatile i16 %a, i16* inttoptr(i16 32 to i16*)
 	ret void
 }
-; CHECK: am4:
+; CHECK-LABEL: am4:
 ; CHECK:		mov.w	r15, &32
 
 define void @am5(i16* nocapture %p, i16 %a) nounwind readonly {
@@ -40,7 +40,7 @@ define void @am5(i16* nocapture %p, i16 %a) nounwind readonly {
 	store i16 %a, i16* %1
 	ret void
 }
-; CHECK: am5:
+; CHECK-LABEL: am5:
 ; CHECK:		mov.w	r14, 4(r15)
 
 %S = type { i16, i16 }
@@ -50,7 +50,7 @@ define void @am6(i16 %a) nounwind {
 	store i16 %a, i16* getelementptr (%S* @baz, i32 0, i32 1)
 	ret void
 }
-; CHECK: am6:
+; CHECK-LABEL: am6:
 ; CHECK:		mov.w	r15, &baz+2
 
 %T = type { i16, [2 x i8] }
@@ -62,6 +62,6 @@ define void @am7(i16 %n, i8 %a) nounwind {
 	store i8 %a, i8* %2
 	ret void
 }
-; CHECK: am7:
+; CHECK-LABEL: am7:
 ; CHECK:		mov.b	r14, duh+2(r15)
 
diff --git a/test/CodeGen/MSP430/Inst16mi.ll b/test/CodeGen/MSP430/Inst16mi.ll
index 33d7aa4..e9ab75c 100644
--- a/test/CodeGen/MSP430/Inst16mi.ll
+++ b/test/CodeGen/MSP430/Inst16mi.ll
@@ -5,14 +5,14 @@ target triple = "msp430-generic-generic"
 @foo = common global i16 0, align 2
 
 define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.w	#2, &foo
 	store i16 2, i16 * @foo
 	ret void
 }
 
 define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.w	#2, &foo
 	%1 = load i16* @foo
 	%2 = add i16 %1, 2
@@ -21,7 +21,7 @@ define void @add() nounwind {
 }
 
 define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w	#2, &foo
 	%1 = load i16* @foo
 	%2 = and i16 %1, 2
@@ -30,7 +30,7 @@ define void @and() nounwind {
 }
 
 define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.w	#2, &foo
 	%1 = load i16* @foo
 	%2 = or i16 %1, 2
@@ -39,7 +39,7 @@ define void @bis() nounwind {
 }
 
 define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w	#2, &foo
 	%1 = load i16* @foo
 	%2 = xor i16 %1, 2
diff --git a/test/CodeGen/MSP430/Inst16mm.ll b/test/CodeGen/MSP430/Inst16mm.ll
index d4ae811..5c93e37 100644
--- a/test/CodeGen/MSP430/Inst16mm.ll
+++ b/test/CodeGen/MSP430/Inst16mm.ll
@@ -5,7 +5,7 @@ target triple = "msp430-generic-generic"
 @bar = common global i16 0, align 2
 
 define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.w	&bar, &foo
         %1 = load i16* @bar
         store i16 %1, i16* @foo
@@ -13,7 +13,7 @@ define void @mov() nounwind {
 }
 
 define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.w	&bar, &foo
 	%1 = load i16* @bar
 	%2 = load i16* @foo
@@ -23,7 +23,7 @@ define void @add() nounwind {
 }
 
 define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w	&bar, &foo
 	%1 = load i16* @bar
 	%2 = load i16* @foo
@@ -33,7 +33,7 @@ define void @and() nounwind {
 }
 
 define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.w	&bar, &foo
 	%1 = load i16* @bar
 	%2 = load i16* @foo
@@ -43,7 +43,7 @@ define void @bis() nounwind {
 }
 
 define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w	&bar, &foo
 	%1 = load i16* @bar
 	%2 = load i16* @foo
@@ -63,7 +63,7 @@ entry:
  store i16 0, i16* %retval
  %0 = load i16* %retval                          ; <i16> [#uses=1]
  ret i16 %0
-; CHECK: mov2:
+; CHECK-LABEL: mov2:
 ; CHECK:	mov.w	2(r1), 6(r1)
 ; CHECK:	mov.w	0(r1), 4(r1)
 }
diff --git a/test/CodeGen/MSP430/Inst16mr.ll b/test/CodeGen/MSP430/Inst16mr.ll
index 2613f01..2010048 100644
--- a/test/CodeGen/MSP430/Inst16mr.ll
+++ b/test/CodeGen/MSP430/Inst16mr.ll
@@ -4,14 +4,14 @@ target triple = "msp430-generic-generic"
 @foo = common global i16 0, align 2
 
 define void @mov(i16 %a) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.w	r15, &foo
 	store i16 %a, i16* @foo
 	ret void
 }
 
 define void @add(i16 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.w	r15, &foo
 	%1 = load i16* @foo
 	%2 = add i16 %a, %1
@@ -20,7 +20,7 @@ define void @add(i16 %a) nounwind {
 }
 
 define void @and(i16 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w	r15, &foo
 	%1 = load i16* @foo
 	%2 = and i16 %a, %1
@@ -29,7 +29,7 @@ define void @and(i16 %a) nounwind {
 }
 
 define void @bis(i16 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.w	r15, &foo
 	%1 = load i16* @foo
 	%2 = or i16 %a, %1
@@ -38,7 +38,7 @@ define void @bis(i16 %a) nounwind {
 }
 
 define void @bic(i16 zeroext %m) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
 ; CHECK: bic.w   r15, &foo
         %1 = xor i16 %m, -1
         %2 = load i16* @foo
@@ -48,7 +48,7 @@ define void @bic(i16 zeroext %m) nounwind {
 }
 
 define void @xor(i16 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w	r15, &foo
 	%1 = load i16* @foo
 	%2 = xor i16 %a, %1
diff --git a/test/CodeGen/MSP430/Inst16ri.ll b/test/CodeGen/MSP430/Inst16ri.ll
index 5115a23..f89f686 100644
--- a/test/CodeGen/MSP430/Inst16ri.ll
+++ b/test/CodeGen/MSP430/Inst16ri.ll
@@ -3,34 +3,34 @@ target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i16 @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.w	#1, r15
 	ret i16 1
 }
 
 define i16 @add(i16 %a, i16 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.w	#1, r15
 	%1 = add i16 %a, 1
 	ret i16 %1
 }
 
 define i16 @and(i16 %a, i16 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w	#1, r15
 	%1 = and i16 %a, 1
 	ret i16 %1
 }
 
 define i16 @bis(i16 %a, i16 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.w	#1, r15
 	%1 = or i16 %a, 1
 	ret i16 %1
 }
 
 define i16 @xor(i16 %a, i16 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w	#1, r15
 	%1 = xor i16 %a, 1
 	ret i16 %1
diff --git a/test/CodeGen/MSP430/Inst16rm.ll b/test/CodeGen/MSP430/Inst16rm.ll
index 02e89c7..e6c5261 100644
--- a/test/CodeGen/MSP430/Inst16rm.ll
+++ b/test/CodeGen/MSP430/Inst16rm.ll
@@ -4,7 +4,7 @@ target triple = "msp430-generic-generic"
 @foo = common global i16 0, align 2
 
 define i16 @add(i16 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.w	&foo, r15
 	%1 = load i16* @foo
 	%2 = add i16 %a, %1
@@ -12,7 +12,7 @@ define i16 @add(i16 %a) nounwind {
 }
 
 define i16 @and(i16 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w	&foo, r15
 	%1 = load i16* @foo
 	%2 = and i16 %a, %1
@@ -20,7 +20,7 @@ define i16 @and(i16 %a) nounwind {
 }
 
 define i16 @bis(i16 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.w	&foo, r15
 	%1 = load i16* @foo
 	%2 = or i16 %a, %1
@@ -28,7 +28,7 @@ define i16 @bis(i16 %a) nounwind {
 }
 
 define i16  @bic(i16 %a) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
 ; CHECK: bic.w	&foo, r15
         %1 = load i16* @foo
         %2 = xor i16 %1, -1
@@ -37,7 +37,7 @@ define i16  @bic(i16 %a) nounwind {
 }
 
 define i16 @xor(i16 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w	&foo, r15
 	%1 = load i16* @foo
 	%2 = xor i16 %a, %1
diff --git a/test/CodeGen/MSP430/Inst16rr.ll b/test/CodeGen/MSP430/Inst16rr.ll
index 2f1ba5b..d74bfae 100644
--- a/test/CodeGen/MSP430/Inst16rr.ll
+++ b/test/CodeGen/MSP430/Inst16rr.ll
@@ -3,34 +3,34 @@ target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i16 @mov(i16 %a, i16 %b) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.w	r14, r15
 	ret i16 %b
 }
 
 define i16 @add(i16 %a, i16 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.w	r14, r15
 	%1 = add i16 %a, %b
 	ret i16 %1
 }
 
 define i16 @and(i16 %a, i16 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w	r14, r15
 	%1 = and i16 %a, %b
 	ret i16 %1
 }
 
 define i16 @bis(i16 %a, i16 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.w	r14, r15
 	%1 = or i16 %a, %b
 	ret i16 %1
 }
 
 define i16 @bic(i16 %a, i16 %b) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
 ; CHECK: bic.w	r14, r15
         %1 = xor i16 %b, -1
         %2 = and i16 %a, %1
@@ -38,7 +38,7 @@ define i16 @bic(i16 %a, i16 %b) nounwind {
 }
 
 define i16 @xor(i16 %a, i16 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w	r14, r15
 	%1 = xor i16 %a, %b
 	ret i16 %1
diff --git a/test/CodeGen/MSP430/Inst8mi.ll b/test/CodeGen/MSP430/Inst8mi.ll
index ef318ce..a2c7b71 100644
--- a/test/CodeGen/MSP430/Inst8mi.ll
+++ b/test/CodeGen/MSP430/Inst8mi.ll
@@ -4,14 +4,14 @@ target triple = "msp430-generic-generic"
 @foo = common global i8 0, align 1
 
 define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.b	#2, &foo
 	store i8 2, i8 * @foo
 	ret void
 }
 
 define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.b	#2, &foo
 	%1 = load i8* @foo
 	%2 = add i8 %1, 2
@@ -20,7 +20,7 @@ define void @add() nounwind {
 }
 
 define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.b	#2, &foo
 	%1 = load i8* @foo
 	%2 = and i8 %1, 2
@@ -29,7 +29,7 @@ define void @and() nounwind {
 }
 
 define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.b	#2, &foo
 	%1 = load i8* @foo
 	%2 = or i8 %1, 2
@@ -38,7 +38,7 @@ define void @bis() nounwind {
 }
 
 define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.b	#2, &foo
 	%1 = load i8* @foo
 	%2 = xor i8 %1, 2
diff --git a/test/CodeGen/MSP430/Inst8mm.ll b/test/CodeGen/MSP430/Inst8mm.ll
index a2987ac..d1ce8bc 100644
--- a/test/CodeGen/MSP430/Inst8mm.ll
+++ b/test/CodeGen/MSP430/Inst8mm.ll
@@ -6,7 +6,7 @@ target triple = "msp430-generic-generic"
 @bar = common global i8 0, align 1
 
 define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.b	&bar, &foo
         %1 = load i8* @bar
         store i8 %1, i8* @foo
@@ -14,7 +14,7 @@ define void @mov() nounwind {
 }
 
 define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.b	&bar, &foo
 	%1 = load i8* @bar
 	%2 = load i8* @foo
@@ -24,7 +24,7 @@ define void @add() nounwind {
 }
 
 define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.b	&bar, &foo
 	%1 = load i8* @bar
 	%2 = load i8* @foo
@@ -34,7 +34,7 @@ define void @and() nounwind {
 }
 
 define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.b	&bar, &foo
 	%1 = load i8* @bar
 	%2 = load i8* @foo
@@ -44,7 +44,7 @@ define void @bis() nounwind {
 }
 
 define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.b	&bar, &foo
 	%1 = load i8* @bar
 	%2 = load i8* @foo
diff --git a/test/CodeGen/MSP430/Inst8mr.ll b/test/CodeGen/MSP430/Inst8mr.ll
index 428d1fa..0b35667 100644
--- a/test/CodeGen/MSP430/Inst8mr.ll
+++ b/test/CodeGen/MSP430/Inst8mr.ll
@@ -4,14 +4,14 @@ target triple = "msp430-generic-generic"
 @foo = common global i8 0, align 1
 
 define void @mov(i8 %a) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.b	r15, &foo
 	store i8 %a, i8* @foo
 	ret void
 }
 
 define void @and(i8 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.b	r15, &foo
 	%1 = load i8* @foo
 	%2 = and i8 %a, %1
@@ -20,7 +20,7 @@ define void @and(i8 %a) nounwind {
 }
 
 define void @add(i8 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.b	r15, &foo
 	%1 = load i8* @foo
 	%2 = add i8 %a, %1
@@ -29,7 +29,7 @@ define void @add(i8 %a) nounwind {
 }
 
 define void @bis(i8 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.b	r15, &foo
 	%1 = load i8* @foo
 	%2 = or i8 %a, %1
@@ -38,7 +38,7 @@ define void @bis(i8 %a) nounwind {
 }
 
 define void @bic(i8 zeroext %m) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
 ; CHECK: bic.b   r15, &foo
         %1 = xor i8 %m, -1
         %2 = load i8* @foo
@@ -48,7 +48,7 @@ define void @bic(i8 zeroext %m) nounwind {
 }
 
 define void @xor(i8 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.b	r15, &foo
 	%1 = load i8* @foo
 	%2 = xor i8 %a, %1
diff --git a/test/CodeGen/MSP430/Inst8ri.ll b/test/CodeGen/MSP430/Inst8ri.ll
index ac3418a..ec0dff9 100644
--- a/test/CodeGen/MSP430/Inst8ri.ll
+++ b/test/CodeGen/MSP430/Inst8ri.ll
@@ -3,34 +3,34 @@ target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i8 @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.b	#1, r15
 	ret i8 1
 }
 
 define i8 @add(i8 %a, i8 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.b	#1, r15
 	%1 = add i8 %a, 1
 	ret i8 %1
 }
 
 define i8 @and(i8 %a, i8 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.b	#1, r15
 	%1 = and i8 %a, 1
 	ret i8 %1
 }
 
 define i8 @bis(i8 %a, i8 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.b	#1, r15
 	%1 = or i8 %a, 1
 	ret i8 %1
 }
 
 define i8 @xor(i8 %a, i8 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.b	#1, r15
 	%1 = xor i8 %a, 1
 	ret i8 %1
diff --git a/test/CodeGen/MSP430/Inst8rm.ll b/test/CodeGen/MSP430/Inst8rm.ll
index c062f04..308163e 100644
--- a/test/CodeGen/MSP430/Inst8rm.ll
+++ b/test/CodeGen/MSP430/Inst8rm.ll
@@ -4,7 +4,7 @@ target triple = "msp430-generic-generic"
 @foo = common global i8 0, align 1
 
 define i8 @add(i8 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.b	&foo, r15
 	%1 = load i8* @foo
 	%2 = add i8 %a, %1
@@ -12,7 +12,7 @@ define i8 @add(i8 %a) nounwind {
 }
 
 define i8 @and(i8 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.b	&foo, r15
 	%1 = load i8* @foo
 	%2 = and i8 %a, %1
@@ -20,7 +20,7 @@ define i8 @and(i8 %a) nounwind {
 }
 
 define i8 @bis(i8 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.b	&foo, r15
 	%1 = load i8* @foo
 	%2 = or i8 %a, %1
@@ -28,7 +28,7 @@ define i8 @bis(i8 %a) nounwind {
 }
 
 define i8  @bic(i8 %a) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
 ; CHECK: bic.b  &foo, r15
         %1 = load i8* @foo
         %2 = xor i8 %1, -1
@@ -37,7 +37,7 @@ define i8  @bic(i8 %a) nounwind {
 }
 
 define i8 @xor(i8 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.b	&foo, r15
 	%1 = load i8* @foo
 	%2 = xor i8 %a, %1
diff --git a/test/CodeGen/MSP430/Inst8rr.ll b/test/CodeGen/MSP430/Inst8rr.ll
index b9c17d9..76e8d19 100644
--- a/test/CodeGen/MSP430/Inst8rr.ll
+++ b/test/CodeGen/MSP430/Inst8rr.ll
@@ -3,34 +3,34 @@ target datalayout = "e-p:16:8:8-i8:8:8-i8:8:8-i32:8:8"
 target triple = "msp430-generic-generic"
 
 define i8 @mov(i8 %a, i8 %b) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
 ; CHECK: mov.{{[bw]}} r14, r15
 	ret i8 %b
 }
 
 define i8 @add(i8 %a, i8 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.b
 	%1 = add i8 %a, %b
 	ret i8 %1
 }
 
 define i8 @and(i8 %a, i8 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w	r14, r15
 	%1 = and i8 %a, %b
 	ret i8 %1
 }
 
 define i8 @bis(i8 %a, i8 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
 ; CHECK: bis.w	r14, r15
 	%1 = or i8 %a, %b
 	ret i8 %1
 }
 
 define i8 @bic(i8 %a, i8 %b) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
 ; CHECK: bic.b  r14, r15
         %1 = xor i8 %b, -1
         %2 = and i8 %a, %1
@@ -38,7 +38,7 @@ define i8 @bic(i8 %a, i8 %b) nounwind {
 }
 
 define i8 @xor(i8 %a, i8 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w	r14, r15
 	%1 = xor i8 %a, %b
 	ret i8 %1
diff --git a/test/CodeGen/MSP430/bit.ll b/test/CodeGen/MSP430/bit.ll
index 03d672b..2ffc191 100644
--- a/test/CodeGen/MSP430/bit.ll
+++ b/test/CodeGen/MSP430/bit.ll
@@ -11,7 +11,7 @@ define i8 @bitbrr(i8 %a, i8 %b) nounwind {
 	%t3 = zext i1 %t2 to i8
 	ret i8 %t3
 }
-; CHECK: bitbrr:
+; CHECK-LABEL: bitbrr:
 ; CHECK: bit.b	r14, r15
 
 define i8 @bitbri(i8 %a) nounwind {
@@ -20,7 +20,7 @@ define i8 @bitbri(i8 %a) nounwind {
 	%t3 = zext i1 %t2 to i8
 	ret i8 %t3
 }
-; CHECK: bitbri:
+; CHECK-LABEL: bitbri:
 ; CHECK: bit.b	#15, r15
 
 define i8 @bitbir(i8 %a) nounwind {
@@ -29,7 +29,7 @@ define i8 @bitbir(i8 %a) nounwind {
 	%t3 = zext i1 %t2 to i8
 	ret i8 %t3
 }
-; CHECK: bitbir:
+; CHECK-LABEL: bitbir:
 ; CHECK: bit.b	#15, r15
 
 define i8 @bitbmi() nounwind {
@@ -39,7 +39,7 @@ define i8 @bitbmi() nounwind {
 	%t4 = zext i1 %t3 to i8
 	ret i8 %t4
 }
-; CHECK: bitbmi:
+; CHECK-LABEL: bitbmi:
 ; CHECK: bit.b	#15, &foo8
 
 define i8 @bitbim() nounwind {
@@ -49,7 +49,7 @@ define i8 @bitbim() nounwind {
 	%t4 = zext i1 %t3 to i8
 	ret i8 %t4
 }
-; CHECK: bitbim:
+; CHECK-LABEL: bitbim:
 ; CHECK: bit.b	#15, &foo8
 
 define i8 @bitbrm(i8 %a) nounwind {
@@ -59,7 +59,7 @@ define i8 @bitbrm(i8 %a) nounwind {
 	%t4 = zext i1 %t3 to i8
 	ret i8 %t4
 }
-; CHECK: bitbrm:
+; CHECK-LABEL: bitbrm:
 ; CHECK: bit.b	&foo8, r15
 
 define i8 @bitbmr(i8 %a) nounwind {
@@ -69,7 +69,7 @@ define i8 @bitbmr(i8 %a) nounwind {
 	%t4 = zext i1 %t3 to i8
 	ret i8 %t4
 }
-; CHECK: bitbmr:
+; CHECK-LABEL: bitbmr:
 ; CHECK: bit.b	r15, &foo8
 
 define i8 @bitbmm() nounwind {
@@ -80,7 +80,7 @@ define i8 @bitbmm() nounwind {
 	%t5 = zext i1 %t4 to i8
 	ret i8 %t5
 }
-; CHECK: bitbmm:
+; CHECK-LABEL: bitbmm:
 ; CHECK: bit.b	&bar8, &foo8
 
 @foo16 = external global i16
@@ -92,7 +92,7 @@ define i16 @bitwrr(i16 %a, i16 %b) nounwind {
 	%t3 = zext i1 %t2 to i16
 	ret i16 %t3
 }
-; CHECK: bitwrr:
+; CHECK-LABEL: bitwrr:
 ; CHECK: bit.w	r14, r15
 
 define i16 @bitwri(i16 %a) nounwind {
@@ -101,7 +101,7 @@ define i16 @bitwri(i16 %a) nounwind {
 	%t3 = zext i1 %t2 to i16
 	ret i16 %t3
 }
-; CHECK: bitwri:
+; CHECK-LABEL: bitwri:
 ; CHECK: bit.w	#4080, r15
 
 define i16 @bitwir(i16 %a) nounwind {
@@ -110,7 +110,7 @@ define i16 @bitwir(i16 %a) nounwind {
 	%t3 = zext i1 %t2 to i16
 	ret i16 %t3
 }
-; CHECK: bitwir:
+; CHECK-LABEL: bitwir:
 ; CHECK: bit.w	#4080, r15
 
 define i16 @bitwmi() nounwind {
@@ -120,7 +120,7 @@ define i16 @bitwmi() nounwind {
 	%t4 = zext i1 %t3 to i16
 	ret i16 %t4
 }
-; CHECK: bitwmi:
+; CHECK-LABEL: bitwmi:
 ; CHECK: bit.w	#4080, &foo16
 
 define i16 @bitwim() nounwind {
@@ -130,7 +130,7 @@ define i16 @bitwim() nounwind {
 	%t4 = zext i1 %t3 to i16
 	ret i16 %t4
 }
-; CHECK: bitwim:
+; CHECK-LABEL: bitwim:
 ; CHECK: bit.w	#4080, &foo16
 
 define i16 @bitwrm(i16 %a) nounwind {
@@ -140,7 +140,7 @@ define i16 @bitwrm(i16 %a) nounwind {
 	%t4 = zext i1 %t3 to i16
 	ret i16 %t4
 }
-; CHECK: bitwrm:
+; CHECK-LABEL: bitwrm:
 ; CHECK: bit.w	&foo16, r15
 
 define i16 @bitwmr(i16 %a) nounwind {
@@ -150,7 +150,7 @@ define i16 @bitwmr(i16 %a) nounwind {
 	%t4 = zext i1 %t3 to i16
 	ret i16 %t4
 }
-; CHECK: bitwmr:
+; CHECK-LABEL: bitwmr:
 ; CHECK: bit.w	r15, &foo16
 
 define i16 @bitwmm() nounwind {
@@ -161,6 +161,6 @@ define i16 @bitwmm() nounwind {
 	%t5 = zext i1 %t4 to i16
 	ret i16 %t5
 }
-; CHECK: bitwmm:
+; CHECK-LABEL: bitwmm:
 ; CHECK: bit.w	&bar16, &foo16
 
diff --git a/test/CodeGen/MSP430/byval.ll b/test/CodeGen/MSP430/byval.ll
index 9dda0a0..bd38e95 100644
--- a/test/CodeGen/MSP430/byval.ll
+++ b/test/CodeGen/MSP430/byval.ll
@@ -8,7 +8,7 @@ target triple = "msp430---elf"
 
 define i16 @callee(%struct.Foo* byval %f) nounwind {
 entry:
-; CHECK: callee:
+; CHECK-LABEL: callee:
 ; CHECK: mov.w 2(r1), r15
   %0 = getelementptr inbounds %struct.Foo* %f, i32 0, i32 0
   %1 = load i16* %0, align 2
@@ -17,7 +17,7 @@ entry:
 
 define void @caller() nounwind {
 entry:
-; CHECK: caller:
+; CHECK-LABEL: caller:
 ; CHECK: mov.w &foo+4, 4(r1)
 ; CHECK-NEXT: mov.w &foo+2, 2(r1)
 ; CHECK-NEXT: mov.w &foo, 0(r1)
diff --git a/test/CodeGen/MSP430/fp.ll b/test/CodeGen/MSP430/fp.ll
index c3273ef..0180905 100644
--- a/test/CodeGen/MSP430/fp.ll
+++ b/test/CodeGen/MSP430/fp.ll
@@ -5,7 +5,7 @@ target triple = "msp430---elf"
 
 define void @fp() nounwind {
 entry:
-; CHECK: fp:
+; CHECK-LABEL: fp:
 ; CHECK: push.w r4
 ; CHECK: mov.w r1, r4
 ; CHECK: sub.w #2, r1
diff --git a/test/CodeGen/MSP430/indirectbr2.ll b/test/CodeGen/MSP430/indirectbr2.ll
index dc2abf5..93788b6 100644
--- a/test/CodeGen/MSP430/indirectbr2.ll
+++ b/test/CodeGen/MSP430/indirectbr2.ll
@@ -5,7 +5,7 @@ define internal i16 @foo(i16 %i) nounwind {
 entry:
   %tmp1 = getelementptr inbounds [5 x i8*]* @C.0.2070, i16 0, i16 %i ; <i8**> [#uses=1]
   %gotovar.4.0 = load i8** %tmp1, align 4        ; <i8*> [#uses=1]
-; CHECK: mov.w   .LC.0.2070(r12), pc
+; CHECK: br .LC.0.2070(r12)
   indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
 
 L5:                                               ; preds = %bb2
diff --git a/test/CodeGen/MSP430/jumptable.ll b/test/CodeGen/MSP430/jumptable.ll
new file mode 100644
index 0000000..239d79e
--- /dev/null
+++ b/test/CodeGen/MSP430/jumptable.ll
@@ -0,0 +1,54 @@
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
+target triple = "msp430---elf"
+
+; Function Attrs: nounwind
+define i16 @test(i16 %i) #0 {
+entry:
+; CHECK-LABEL: test:
+  %retval = alloca i16, align 2
+  %i.addr = alloca i16, align 2
+  store i16 %i, i16* %i.addr, align 2
+  %0 = load i16* %i.addr, align 2
+; CHECK: mov.w #2, r14
+; CHECK: call #__mulhi3hw_noint
+; CHECK: br .LJTI0_0(r15)
+  switch i16 %0, label %sw.default [
+    i16 0, label %sw.bb
+    i16 1, label %sw.bb1
+    i16 2, label %sw.bb2
+    i16 3, label %sw.bb3
+  ]
+
+sw.bb:                                            ; preds = %entry
+  store i16 0, i16* %retval
+  br label %return
+
+sw.bb1:                                           ; preds = %entry
+  store i16 1, i16* %retval
+  br label %return
+
+sw.bb2:                                           ; preds = %entry
+  store i16 2, i16* %retval
+  br label %return
+
+sw.bb3:                                           ; preds = %entry
+  store i16 3, i16* %retval
+  br label %return
+
+sw.default:                                       ; preds = %entry
+  store i16 2, i16* %retval
+  br label %return
+
+return:                                           ; preds = %sw.default, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb
+  %1 = load i16* %retval
+  ret i16 %1
+; CHECK: ret
+}
+
+; CHECK: .LJTI0_0:
+; CHECK-NEXT: .short .LBB0_2
+; CHECK-NEXT: .short .LBB0_4
+; CHECK-NEXT: .short .LBB0_3
+; CHECK-NEXT: .short .LBB0_5
diff --git a/test/CodeGen/MSP430/postinc.ll b/test/CodeGen/MSP430/postinc.ll
index 8f01b83..8d55fd3 100644
--- a/test/CodeGen/MSP430/postinc.ll
+++ b/test/CodeGen/MSP430/postinc.ll
@@ -11,7 +11,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
   %arrayidx = getelementptr i16* %a, i16 %i.010   ; <i16*> [#uses=1]
-; CHECK: add:
+; CHECK-LABEL: add:
 ; CHECK: add.w @r{{[0-9]+}}+, r{{[0-9]+}}
   %tmp4 = load i16* %arrayidx                     ; <i16> [#uses=1]
   %add = add i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
@@ -33,7 +33,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
   %arrayidx = getelementptr i16* %a, i16 %i.010   ; <i16*> [#uses=1]
-; CHECK: sub:
+; CHECK-LABEL: sub:
 ; CHECK: sub.w @r{{[0-9]+}}+, r{{[0-9]+}}
   %tmp4 = load i16* %arrayidx                     ; <i16> [#uses=1]
   %add = sub i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
@@ -55,7 +55,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
   %arrayidx = getelementptr i16* %a, i16 %i.010   ; <i16*> [#uses=1]
-; CHECK: or:
+; CHECK-LABEL: or:
 ; CHECK: bis.w @r{{[0-9]+}}+, r{{[0-9]+}}
   %tmp4 = load i16* %arrayidx                     ; <i16> [#uses=1]
   %add = or i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
@@ -77,7 +77,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
   %arrayidx = getelementptr i16* %a, i16 %i.010   ; <i16*> [#uses=1]
-; CHECK: xor:
+; CHECK-LABEL: xor:
 ; CHECK: xor.w @r{{[0-9]+}}+, r{{[0-9]+}}
   %tmp4 = load i16* %arrayidx                     ; <i16> [#uses=1]
   %add = xor i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
@@ -99,7 +99,7 @@ for.body:                                         ; preds = %for.body, %entry
   %i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
   %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
   %arrayidx = getelementptr i16* %a, i16 %i.010   ; <i16*> [#uses=1]
-; CHECK: and:
+; CHECK-LABEL: and:
 ; CHECK: and.w @r{{[0-9]+}}+, r{{[0-9]+}}
   %tmp4 = load i16* %arrayidx                     ; <i16> [#uses=1]
   %add = and i16 %tmp4, %sum.09                   ; <i16> [#uses=2]
diff --git a/test/CodeGen/MSP430/setcc.ll b/test/CodeGen/MSP430/setcc.ll
index 05f9acd..d5a8057 100644
--- a/test/CodeGen/MSP430/setcc.ll
+++ b/test/CodeGen/MSP430/setcc.ll
@@ -8,7 +8,7 @@ define i16 @sccweqand(i16 %a, i16 %b) nounwind {
 	%t3 = zext i1 %t2 to i16
 	ret i16 %t3
 }
-; CHECK: sccweqand:
+; CHECK-LABEL: sccweqand:
 ; CHECK:	bit.w	r14, r15
 ; CHECK:	mov.w	r2, r15
 ; CHECK:	rra.w   r15
@@ -20,7 +20,7 @@ define i16 @sccwneand(i16 %a, i16 %b) nounwind {
 	%t3 = zext i1 %t2 to i16
 	ret i16 %t3
 }
-; CHECK: sccwneand:
+; CHECK-LABEL: sccwneand:
 ; CHECK: 	bit.w	r14, r15
 ; CHECK:	mov.w	r2, r15
 ; CHECK:	and.w	#1, r15
@@ -30,7 +30,7 @@ define i16 @sccwne(i16 %a, i16 %b) nounwind {
 	%t2 = zext i1 %t1 to i16
 	ret i16 %t2
 }
-; CHECK:sccwne:
+; CHECK-LABEL:sccwne:
 ; CHECK:	cmp.w	r14, r15
 ; CHECK:	mov.w	r2, r12
 ; CHECK:	rra.w	r12
@@ -42,7 +42,7 @@ define i16 @sccweq(i16 %a, i16 %b) nounwind {
 	%t2 = zext i1 %t1 to i16
 	ret i16 %t2
 }
-; CHECK:sccweq:
+; CHECK-LABEL:sccweq:
 ; CHECK:	cmp.w	r14, r15
 ; CHECK:	mov.w	r2, r15
 ; CHECK:	rra.w	r15
@@ -53,7 +53,7 @@ define i16 @sccwugt(i16 %a, i16 %b) nounwind {
 	%t2 = zext i1 %t1 to i16
 	ret i16 %t2
 }
-; CHECK:sccwugt:
+; CHECK-LABEL:sccwugt:
 ; CHECK:	cmp.w	r15, r14
 ; CHECK:	mov.w	#1, r15
 ; CHECK:	bic.w	r2, r15
@@ -63,7 +63,7 @@ define i16 @sccwuge(i16 %a, i16 %b) nounwind {
 	%t2 = zext i1 %t1 to i16
 	ret i16 %t2
 }
-; CHECK:sccwuge:
+; CHECK-LABEL:sccwuge:
 ; CHECK:	cmp.w	r14, r15
 ; CHECK:	mov.w	r2, r15
 ; CHECK:	and.w	#1, r15
@@ -73,7 +73,7 @@ define i16 @sccwult(i16 %a, i16 %b) nounwind {
 	%t2 = zext i1 %t1 to i16
 	ret i16 %t2
 }
-; CHECK:sccwult:
+; CHECK-LABEL:sccwult:
 ; CHECK:	cmp.w	r14, r15
 ; CHECK:	mov.w	#1, r15
 ; CHECK:	bic.w	r2, r15
@@ -83,7 +83,7 @@ define i16 @sccwule(i16 %a, i16 %b) nounwind {
 	%t2 = zext i1 %t1 to i16
 	ret i16 %t2
 }
-; CHECK:sccwule:
+; CHECK-LABEL:sccwule:
 ; CHECK:	cmp.w	r15, r14
 ; CHECK:	mov.w	r2, r15
 ; CHECK:	and.w	#1, r15
diff --git a/test/CodeGen/MSP430/shifts.ll b/test/CodeGen/MSP430/shifts.ll
index b5b3054..22ae59e 100644
--- a/test/CodeGen/MSP430/shifts.ll
+++ b/test/CodeGen/MSP430/shifts.ll
@@ -4,7 +4,7 @@ target triple = "msp430-elf"
 
 define zeroext i8 @lshr8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
 entry:
-; CHECK: lshr8:
+; CHECK-LABEL: lshr8:
 ; CHECK: rrc.b
   %shr = lshr i8 %a, %cnt
   ret i8 %shr
@@ -12,7 +12,7 @@ entry:
 
 define signext i8 @ashr8(i8 signext %a, i8 zeroext %cnt) nounwind readnone {
 entry:
-; CHECK: ashr8:
+; CHECK-LABEL: ashr8:
 ; CHECK: rra.b
   %shr = ashr i8 %a, %cnt
   ret i8 %shr
@@ -28,7 +28,7 @@ entry:
 
 define zeroext i16 @lshr16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
 entry:
-; CHECK: lshr16:
+; CHECK-LABEL: lshr16:
 ; CHECK: rrc.w
   %shr = lshr i16 %a, %cnt
   ret i16 %shr
@@ -36,7 +36,7 @@ entry:
 
 define signext i16 @ashr16(i16 signext %a, i16 zeroext %cnt) nounwind readnone {
 entry:
-; CHECK: ashr16:
+; CHECK-LABEL: ashr16:
 ; CHECK: rra.w
   %shr = ashr i16 %a, %cnt
   ret i16 %shr
@@ -44,7 +44,7 @@ entry:
 
 define zeroext i16 @shl16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
 entry:
-; CHECK: shl16:
+; CHECK-LABEL: shl16:
 ; CHECK: rla.w
   %shl = shl i16 %a, %cnt
   ret i16 %shl
diff --git a/test/CodeGen/MSP430/vararg.ll b/test/CodeGen/MSP430/vararg.ll
index 603d3ec..9e511fc 100644
--- a/test/CodeGen/MSP430/vararg.ll
+++ b/test/CodeGen/MSP430/vararg.ll
@@ -9,7 +9,7 @@ declare void @llvm.va_copy(i8*, i8*) nounwind
 
 define void @va_start(i16 %a, ...) nounwind {
 entry:
-; CHECK: va_start:
+; CHECK-LABEL: va_start:
 ; CHECK: sub.w #2, r1
   %vl = alloca i8*, align 2
   %vl1 = bitcast i8** %vl to i8*
@@ -23,7 +23,7 @@ entry:
 
 define i16 @va_arg(i8* %vl) nounwind {
 entry:
-; CHECK: va_arg:
+; CHECK-LABEL: va_arg:
   %vl.addr = alloca i8*, align 2
 ; CHECK: mov.w r15, 0(r1)
   store i8* %vl, i8** %vl.addr, align 2
@@ -37,7 +37,7 @@ entry:
 
 define void @va_copy(i8* %vl) nounwind {
 entry:
-; CHECK: va_copy:
+; CHECK-LABEL: va_copy:
   %vl.addr = alloca i8*, align 2
   %vl2 = alloca i8*, align 2
 ; CHECK: mov.w r15, 2(r1)
diff --git a/test/CodeGen/Mips/align16.ll b/test/CodeGen/Mips/align16.ll
index 99139ab..267cff5 100644
--- a/test/CodeGen/Mips/align16.ll
+++ b/test/CodeGen/Mips/align16.ll
@@ -25,7 +25,7 @@ entry:
   call void @p(i32* %arrayidx1)
   ret void
 }
-; 16:	save	$ra, $s0, $s1, 2040
-; 16:	addiu	$sp, -48 # 16 bit inst
-; 16:	addiu	$sp, 48 # 16 bit inst
-; 16:	restore	$ra,  $s0, $s1, 2040
\ No newline at end of file
+; 16:	save	$ra, $s0, $s1, $s2, 2040
+; 16:	addiu	$sp, -56 # 16 bit inst
+; 16:	addiu	$sp, 56 # 16 bit inst
+; 16:	restore	$ra,  $s0, $s1, $s2, 2040
diff --git a/test/CodeGen/Mips/alloca16.ll b/test/CodeGen/Mips/alloca16.ll
index 5ae9a84..017665f 100644
--- a/test/CodeGen/Mips/alloca16.ll
+++ b/test/CodeGen/Mips/alloca16.ll
@@ -19,8 +19,8 @@ entry:
 
 define void @test() nounwind {
 entry:
-; 16: 	.frame	$16,24,$ra
-; 16: 	save 	$ra, $s0, $s1, 24
+; 16: 	.frame	$sp,24,$ra
+; 16: 	save 	$ra, $s0, $s1, $s2, 24
 ; 16: 	move	$16, $sp
 ; 16:	move	${{[0-9]+}}, $sp
 ; 16:	subu	$[[REGISTER:[0-9]+]], ${{[0-9]+}}, ${{[0-9]+}}
diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll
index 6bc9ce2..0e60fe1 100644
--- a/test/CodeGen/Mips/atomic.ll
+++ b/test/CodeGen/Mips/atomic.ll
@@ -8,21 +8,21 @@ entry:
   %0 = atomicrmw add i32* @x, i32 %incr monotonic
   ret i32 %0
 
-; CHECK-EL:   AtomicLoadAdd32:
+; CHECK-EL-LABEL:   AtomicLoadAdd32:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EL:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EL:   ll      $[[R1:[0-9]+]], 0($[[R0]])
 ; CHECK-EL:   addu    $[[R2:[0-9]+]], $[[R1]], $4
 ; CHECK-EL:   sc      $[[R2]], 0($[[R0]])
-; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R2]], $[[BB0]]
 
-; CHECK-EB:   AtomicLoadAdd32:
+; CHECK-EB-LABEL:   AtomicLoadAdd32:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EB:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EB:   ll      $[[R1:[0-9]+]], 0($[[R0]])
 ; CHECK-EB:   addu    $[[R2:[0-9]+]], $[[R1]], $4
 ; CHECK-EB:   sc      $[[R2]], 0($[[R0]])
-; CHECK-EB:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R2]], $[[BB0]]
 }
 
 define i32 @AtomicLoadNand32(i32 %incr) nounwind {
@@ -30,23 +30,23 @@ entry:
   %0 = atomicrmw nand i32* @x, i32 %incr monotonic
   ret i32 %0
 
-; CHECK-EL:   AtomicLoadNand32:
+; CHECK-EL-LABEL:   AtomicLoadNand32:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EL:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EL:   ll      $[[R1:[0-9]+]], 0($[[R0]])
 ; CHECK-EL:   and     $[[R3:[0-9]+]], $[[R1]], $4
 ; CHECK-EL:   nor     $[[R2:[0-9]+]], $zero, $[[R3]]
 ; CHECK-EL:   sc      $[[R2]], 0($[[R0]])
-; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R2]], $[[BB0]]
 
-; CHECK-EB:   AtomicLoadNand32:
+; CHECK-EB-LABEL:   AtomicLoadNand32:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EB:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EB:   ll      $[[R1:[0-9]+]], 0($[[R0]])
 ; CHECK-EB:   and     $[[R3:[0-9]+]], $[[R1]], $4
 ; CHECK-EB:   nor     $[[R2:[0-9]+]], $zero, $[[R3]]
 ; CHECK-EB:   sc      $[[R2]], 0($[[R0]])
-; CHECK-EB:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R2]], $[[BB0]]
 }
 
 define i32 @AtomicSwap32(i32 %newval) nounwind {
@@ -57,19 +57,19 @@ entry:
   %0 = atomicrmw xchg i32* @x, i32 %tmp monotonic
   ret i32 %0
 
-; CHECK-EL:   AtomicSwap32:
+; CHECK-EL-LABEL:   AtomicSwap32:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EL:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EL:   ll      ${{[0-9]+}}, 0($[[R0]])
 ; CHECK-EL:   sc      $[[R2:[0-9]+]], 0($[[R0]])
-; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R2]], $[[BB0]]
 
-; CHECK-EB:   AtomicSwap32:
+; CHECK-EB-LABEL:   AtomicSwap32:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EB:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EB:   ll      ${{[0-9]+}}, 0($[[R0]])
 ; CHECK-EB:   sc      $[[R2:[0-9]+]], 0($[[R0]])
-; CHECK-EB:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R2]], $[[BB0]]
 }
 
 define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind {
@@ -80,22 +80,22 @@ entry:
   %0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic
   ret i32 %0
 
-; CHECK-EL:   AtomicCmpSwap32:
+; CHECK-EL-LABEL:   AtomicCmpSwap32:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EL:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EL:   ll      $2, 0($[[R0]])
 ; CHECK-EL:   bne     $2, $4, $[[BB1:[A-Z_0-9]+]]
 ; CHECK-EL:   sc      $[[R2:[0-9]+]], 0($[[R0]])
-; CHECK-EL:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R2]], $[[BB0]]
 ; CHECK-EL:   $[[BB1]]:
 
-; CHECK-EB:   AtomicCmpSwap32:
+; CHECK-EB-LABEL:   AtomicCmpSwap32:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(x)
 ; CHECK-EB:   $[[BB0:[A-Z_0-9]+]]:
 ; CHECK-EB:   ll      $2, 0($[[R0]])
 ; CHECK-EB:   bne     $2, $4, $[[BB1:[A-Z_0-9]+]]
 ; CHECK-EB:   sc      $[[R2:[0-9]+]], 0($[[R0]])
-; CHECK-EB:   beq     $[[R2]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R2]], $[[BB0]]
 ; CHECK-EB:   $[[BB1]]:
 }
 
@@ -108,7 +108,7 @@ entry:
   %0 = atomicrmw add i8* @y, i8 %incr monotonic
   ret i8 %0
 
-; CHECK-EL:   AtomicLoadAdd8:
+; CHECK-EL-LABEL:   AtomicLoadAdd8:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EL:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EL:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -126,14 +126,14 @@ entry:
 ; CHECK-EL:   and     $[[R13:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EL:   or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; CHECK-EL:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EL:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EL:   and     $[[R15:[0-9]+]], $[[R10]], $[[R6]]
 ; CHECK-EL:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R4]]
 ; CHECK-EL:   sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; CHECK-EL:   sra     $2, $[[R17]], 24
 
-; CHECK-EB:   AtomicLoadAdd8:
+; CHECK-EB-LABEL:   AtomicLoadAdd8:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EB:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EB:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -152,7 +152,7 @@ entry:
 ; CHECK-EB:   and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
 ; CHECK-EB:   or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; CHECK-EB:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EB:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EB:   and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EB:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@@ -165,7 +165,7 @@ entry:
   %0 = atomicrmw sub i8* @y, i8 %incr monotonic
   ret i8 %0
 
-; CHECK-EL:   AtomicLoadSub8:
+; CHECK-EL-LABEL:   AtomicLoadSub8:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EL:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EL:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -183,14 +183,14 @@ entry:
 ; CHECK-EL:   and     $[[R13:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EL:   or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; CHECK-EL:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EL:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EL:   and     $[[R15:[0-9]+]], $[[R10]], $[[R6]]
 ; CHECK-EL:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R4]]
 ; CHECK-EL:   sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; CHECK-EL:   sra     $2, $[[R17]], 24
 
-; CHECK-EB:   AtomicLoadSub8:
+; CHECK-EB-LABEL:   AtomicLoadSub8:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EB:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EB:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -209,7 +209,7 @@ entry:
 ; CHECK-EB:   and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
 ; CHECK-EB:   or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; CHECK-EB:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EB:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EB:   and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EB:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@@ -222,7 +222,7 @@ entry:
   %0 = atomicrmw nand i8* @y, i8 %incr monotonic
   ret i8 %0
 
-; CHECK-EL:   AtomicLoadNand8:
+; CHECK-EL-LABEL:   AtomicLoadNand8:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EL:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EL:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -241,14 +241,14 @@ entry:
 ; CHECK-EL:   and     $[[R13:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EL:   or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; CHECK-EL:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EL:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EL:   and     $[[R15:[0-9]+]], $[[R10]], $[[R6]]
 ; CHECK-EL:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R4]]
 ; CHECK-EL:   sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; CHECK-EL:   sra     $2, $[[R17]], 24
 
-; CHECK-EB:   AtomicLoadNand8:
+; CHECK-EB-LABEL:   AtomicLoadNand8:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EB:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EB:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -268,7 +268,7 @@ entry:
 ; CHECK-EB:   and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
 ; CHECK-EB:   or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
 ; CHECK-EB:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EB:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EB:   and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EB:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@@ -281,7 +281,7 @@ entry:
   %0 = atomicrmw xchg i8* @y, i8 %newval monotonic
   ret i8 %0
 
-; CHECK-EL:   AtomicSwap8:
+; CHECK-EL-LABEL:   AtomicSwap8:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EL:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EL:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -298,14 +298,14 @@ entry:
 ; CHECK-EL:   and     $[[R13:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EL:   or      $[[R14:[0-9]+]], $[[R13]], $[[R18]]
 ; CHECK-EL:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EL:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EL:   and     $[[R15:[0-9]+]], $[[R10]], $[[R6]]
 ; CHECK-EL:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R4]]
 ; CHECK-EL:   sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; CHECK-EL:   sra     $2, $[[R17]], 24
 
-; CHECK-EB:   AtomicSwap8:
+; CHECK-EB-LABEL:   AtomicSwap8:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EB:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EB:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -323,7 +323,7 @@ entry:
 ; CHECK-EB:   and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
 ; CHECK-EB:   or      $[[R14:[0-9]+]], $[[R13]], $[[R18]]
 ; CHECK-EB:   sc      $[[R14]], 0($[[R2]])
-; CHECK-EB:   beq     $[[R14]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R14]], $[[BB0]]
 
 ; CHECK-EB:   and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
 ; CHECK-EB:   srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@@ -336,7 +336,7 @@ entry:
   %0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic
   ret i8 %0
 
-; CHECK-EL:   AtomicCmpSwap8:
+; CHECK-EL-LABEL:   AtomicCmpSwap8:
 ; CHECK-EL:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EL:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EL:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -358,14 +358,14 @@ entry:
 ; CHECK-EL:   and     $[[R14:[0-9]+]], $[[R12]], $[[R7]]
 ; CHECK-EL:   or      $[[R15:[0-9]+]], $[[R14]], $[[R11]]
 ; CHECK-EL:   sc      $[[R15]], 0($[[R2]])
-; CHECK-EL:   beq     $[[R15]], $zero, $[[BB0]]
+; CHECK-EL:   beqz    $[[R15]], $[[BB0]]
 
 ; CHECK-EL:   $[[BB1]]:
 ; CHECK-EL:   srlv    $[[R16:[0-9]+]], $[[R13]], $[[R4]]
 ; CHECK-EL:   sll     $[[R17:[0-9]+]], $[[R16]], 24
 ; CHECK-EL:   sra     $2, $[[R17]], 24
 
-; CHECK-EB:   AtomicCmpSwap8:
+; CHECK-EB-LABEL:   AtomicCmpSwap8:
 ; CHECK-EB:   lw      $[[R0:[0-9]+]], %got(y)
 ; CHECK-EB:   addiu   $[[R1:[0-9]+]], $zero, -4
 ; CHECK-EB:   and     $[[R2:[0-9]+]], $[[R0]], $[[R1]]
@@ -388,7 +388,7 @@ entry:
 ; CHECK-EB:   and     $[[R15:[0-9]+]], $[[R13]], $[[R8]]
 ; CHECK-EB:   or      $[[R16:[0-9]+]], $[[R15]], $[[R12]]
 ; CHECK-EB:   sc      $[[R16]], 0($[[R2]])
-; CHECK-EB:   beq     $[[R16]], $zero, $[[BB0]]
+; CHECK-EB:   beqz    $[[R16]], $[[BB0]]
 
 ; CHECK-EB:   $[[BB1]]:
 ; CHECK-EB:   srlv    $[[R17:[0-9]+]], $[[R14]], $[[R5]]
@@ -403,14 +403,14 @@ entry:
   %0 = atomicrmw add i32* @countsint, i32 %v seq_cst
   ret i32 %0 
 
-; CHECK-EL:   CheckSync:
+; CHECK-EL-LABEL:   CheckSync:
 ; CHECK-EL:   sync 0
 ; CHECK-EL:   ll
 ; CHECK-EL:   sc
 ; CHECK-EL:   beq
 ; CHECK-EL:   sync 0
 
-; CHECK-EB:   CheckSync:
+; CHECK-EB-LABEL:   CheckSync:
 ; CHECK-EB:   sync 0
 ; CHECK-EB:   ll
 ; CHECK-EB:   sc
diff --git a/test/CodeGen/Mips/atomicops.ll b/test/CodeGen/Mips/atomicops.ll
index b9c3804..0f0f01a 100644
--- a/test/CodeGen/Mips/atomicops.ll
+++ b/test/CodeGen/Mips/atomicops.ll
@@ -7,7 +7,7 @@ entry:
   %0 = atomicrmw add i32* %mem, i32 %val seq_cst
   %add = add nsw i32 %0, %c
   ret i32 %add
-; 16: foo:
+; 16-LABEL: foo:
 ; 16:	lw	${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
 ; 16: 	lw	${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
 }
@@ -26,7 +26,7 @@ entry:
   %4 = atomicrmw xchg i32* %x, i32 1 seq_cst
   %5 = load volatile i32* %x, align 4
   %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %4, i32 %5) nounwind
-; 16: main:
+; 16-LABEL: main:
 ; 16:	lw	${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
 ; 16: 	lw	${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
 ; 16:	lw	${{[0-9]+}}, %call16(__sync_val_compare_and_swap_4)(${{[0-9]+}})
diff --git a/test/CodeGen/Mips/biggot.ll b/test/CodeGen/Mips/biggot.ll
index c4ad851..da287ee 100644
--- a/test/CodeGen/Mips/biggot.ll
+++ b/test/CodeGen/Mips/biggot.ll
@@ -31,12 +31,12 @@ declare void @foo0(i32)
 
 define void @foo2(i32* nocapture %d, i32* nocapture %s, i32 %n) nounwind {
 entry:
-; O32: foo2:
+; O32-LABEL: foo2:
 ; O32: lui $[[R2:[0-9]+]], %call_hi(memcpy)
 ; O32: addu  $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
 ; O32: lw  ${{[0-9]+}}, %call_lo(memcpy)($[[R3]])
 
-; N64: foo2:
+; N64-LABEL: foo2:
 ; N64: lui $[[R2:[0-9]+]], %call_hi(memcpy)
 ; N64: daddu  $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
 ; N64: ld  ${{[0-9]+}}, %call_lo(memcpy)($[[R3]])
diff --git a/test/CodeGen/Mips/blez_bgez.ll b/test/CodeGen/Mips/blez_bgez.ll
index 52765af..f6a5e4f 100644
--- a/test/CodeGen/Mips/blez_bgez.ll
+++ b/test/CodeGen/Mips/blez_bgez.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -march=mipsel < %s | FileCheck %s
 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
 
-; CHECK: test_blez:
+; CHECK-LABEL: test_blez:
 ; CHECK: blez ${{[0-9]+}}, $BB
 
 define void @test_blez(i32 %a) {
@@ -19,7 +19,7 @@ if.end:
 
 declare void @foo1()
 
-; CHECK: test_bgez:
+; CHECK-LABEL: test_bgez:
 ; CHECK: bgez ${{[0-9]+}}, $BB
 
 define void @test_bgez(i32 %a) {
diff --git a/test/CodeGen/Mips/brdelayslot.ll b/test/CodeGen/Mips/brdelayslot.ll
index d076f74..869ecd9 100644
--- a/test/CodeGen/Mips/brdelayslot.ll
+++ b/test/CodeGen/Mips/brdelayslot.ll
@@ -31,7 +31,7 @@ declare void @foo2(i32)
 ;
 define void @foo3(i32 %a) nounwind {
 entry:
-; Default:     foo3:
+; Default-LABEL:     foo3:
 ; Default:     jalr
 ; Default:     cvt.d.w
 
@@ -49,7 +49,7 @@ declare void @foo4(double)
 ; Check that branch delay slot can be filled with an instruction with operand
 ; $1.
 ;
-; Default:     foo5:
+; Default-LABEL:     foo5:
 ; Default-NOT: nop
 
 define void @foo5(i32 %a) nounwind {
@@ -76,7 +76,7 @@ if.end:
 
 ; Check that delay slot filler can place mov.s or mov.d in delay slot.
 ;
-; Default:     foo6:
+; Default-LABEL:     foo6:
 ; Default-NOT: nop
 ; Default:     .end foo6
 
@@ -90,7 +90,7 @@ declare void @foo7(double, float)
 
 ; Check that a store can move past other memory instructions.
 ;
-; STATICO1:      foo8:
+; STATICO1-LABEL:      foo8:
 ; STATICO1:      jalr ${{[0-9]+}}
 ; STATICO1-NEXT: sw ${{[0-9]+}}, %lo(g1)
 
@@ -109,7 +109,7 @@ entry:
 ; Test searchForward. Check that the second jal's slot is filled with another
 ; instruction in the same block.
 ;
-; FORWARD:     foo10:
+; FORWARD-LABEL:     foo10:
 ; FORWARD:     jal foo11
 ; FORWARD:     jal foo11
 ; FORWARD-NOT: nop
@@ -130,10 +130,10 @@ declare void @foo11()
 ; Check that delay slots of branches in both the entry block and loop body are
 ; filled.
 ;
-; SUCCBB:      succbbs_loop1:
+; SUCCBB-LABEL:      succbbs_loop1:
 ; SUCCBB:      blez $5, $BB
 ; SUCCBB-NEXT: addiu
-; SUCCBB:      bne ${{[0-9]+}}, $zero, $BB
+; SUCCBB:      bnez ${{[0-9]+}}, $BB
 ; SUCCBB-NEXT: addiu
 
 define i32 @succbbs_loop1(i32* nocapture %a, i32 %n) {
@@ -158,8 +158,8 @@ for.end:                                          ; preds = %for.body, %entry
 
 ; Check that the first branch has its slot filled.
 ;
-; SUCCBB:      succbbs_br1:
-; SUCCBB:      beq ${{[0-9]+}}, $zero, $BB
+; SUCCBB-LABEL:      succbbs_br1:
+; SUCCBB:      beqz ${{[0-9]+}}, $BB
 ; SUCCBB-NEXT: lw $25, %call16(foo100)
 
 define void @succbbs_br1(i32 %a) {
diff --git a/test/CodeGen/Mips/bswap.ll b/test/CodeGen/Mips/bswap.ll
index a8fc2cd..0da2d2b 100644
--- a/test/CodeGen/Mips/bswap.ll
+++ b/test/CodeGen/Mips/bswap.ll
@@ -3,7 +3,7 @@
 
 define i32 @bswap32(i32 %x) nounwind readnone {
 entry:
-; MIPS32: bswap32:
+; MIPS32-LABEL: bswap32:
 ; MIPS32: wsbh $[[R0:[0-9]+]]
 ; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
   %or.3 = call i32 @llvm.bswap.i32(i32 %x)
@@ -12,7 +12,7 @@ entry:
 
 define i64 @bswap64(i64 %x) nounwind readnone {
 entry:
-; MIPS64: bswap64:
+; MIPS64-LABEL: bswap64:
 ; MIPS64: dsbh $[[R0:[0-9]+]]
 ; MIPS64: dshd ${{[0-9]+}}, $[[R0]]
   %or.7 = call i64 @llvm.bswap.i64(i64 %x)
diff --git a/test/CodeGen/Mips/check-noat.ll b/test/CodeGen/Mips/check-noat.ll
index bfeff67..cfcd367 100644
--- a/test/CodeGen/Mips/check-noat.ll
+++ b/test/CodeGen/Mips/check-noat.ll
@@ -2,7 +2,7 @@
 
 define void @f() nounwind readnone {
 entry:
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: .set  noat
 ; CHECK: .set  at
 
diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll
index 81925a4..c24c5ac 100644
--- a/test/CodeGen/Mips/cmov.ll
+++ b/test/CodeGen/Mips/cmov.ll
@@ -5,12 +5,12 @@
 @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
 @i3 = common global i32* null, align 4
 
-; O32:  lw $[[R0:[0-9]+]], %got(i3)
-; O32:  addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1) 
-; O32:  movn $[[R0]], $[[R1]], ${{[0-9]+}} 
-; N64:  ldr $[[R0:[0-9]+]] 
-; N64:  ld $[[R1:[0-9]+]], %got_disp(i1)
-; N64:  movn $[[R0]], $[[R1]], ${{[0-9]+}} 
+; O32-DAG:  lw $[[R0:[0-9]+]], %got(i3)
+; O32-DAG:  addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1)
+; O32:      movn $[[R0]], $[[R1]], ${{[0-9]+}}
+; N64-DAG:  ldr $[[R0:[0-9]+]]
+; N64-DAG:  ld $[[R1:[0-9]+]], %got_disp(i1)
+; N64:      movn $[[R0]], $[[R1]], ${{[0-9]+}}
 define i32* @cmov1(i32 %s) nounwind readonly {
 entry:
   %tobool = icmp ne i32 %s, 0
@@ -22,11 +22,11 @@ entry:
 @c = global i32 1, align 4
 @d = global i32 0, align 4
 
-; O32: cmov2:
+; O32-LABEL: cmov2:
 ; O32: addiu $[[R1:[0-9]+]], ${{[a-z0-9]+}}, %got(d)
 ; O32: addiu $[[R0:[0-9]+]], ${{[a-z0-9]+}}, %got(c)
 ; O32: movn  $[[R1]], $[[R0]], ${{[0-9]+}}
-; N64: cmov2:
+; N64-LABEL: cmov2:
 ; N64: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
 ; N64: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)
 ; N64: movn  $[[R1]], $[[R0]], ${{[0-9]+}}
@@ -39,7 +39,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: cmov3:
+; O32-LABEL: cmov3:
 ; O32: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 define i32 @cmov3(i32 %a, i32 %b, i32 %c) nounwind readnone {
@@ -49,7 +49,7 @@ entry:
   ret i32 %cond
 }
 
-; N64: cmov4:
+; N64-LABEL: cmov4:
 ; N64: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
 ; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 define i64 @cmov4(i32 %a, i64 %b, i64 %c) nounwind readnone {
@@ -67,7 +67,7 @@ entry:
 ;  (movz t, (setlt a, N + 1), f)
 ; if N + 1 fits in 16-bit.
 
-; O32: slti0:
+; O32-LABEL: slti0:
 ; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -78,7 +78,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: slti1:
+; O32-LABEL: slti1:
 ; O32: slt ${{[0-9]+}}
 
 define i32 @slti1(i32 %a) {
@@ -88,7 +88,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: slti2:
+; O32-LABEL: slti2:
 ; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -99,7 +99,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: slti3:
+; O32-LABEL: slti3:
 ; O32: slt ${{[0-9]+}}
 
 define i32 @slti3(i32 %a) {
@@ -111,7 +111,7 @@ entry:
 
 ; 64-bit patterns.
 
-; N64: slti64_0:
+; N64-LABEL: slti64_0:
 ; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
 ; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -122,7 +122,7 @@ entry:
   ret i64 %conv
 }
 
-; N64: slti64_1:
+; N64-LABEL: slti64_1:
 ; N64: slt ${{[0-9]+}}
 
 define i64 @slti64_1(i64 %a) {
@@ -132,7 +132,7 @@ entry:
   ret i64 %conv
 }
 
-; N64: slti64_2:
+; N64-LABEL: slti64_2:
 ; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
 ; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -143,7 +143,7 @@ entry:
   ret i64 %conv
 }
 
-; N64: slti64_3:
+; N64-LABEL: slti64_3:
 ; N64: slt ${{[0-9]+}}
 
 define i64 @slti64_3(i64 %a) {
@@ -155,7 +155,7 @@ entry:
 
 ; sltiu instructions.
 
-; O32: sltiu0:
+; O32-LABEL: sltiu0:
 ; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -166,7 +166,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: sltiu1:
+; O32-LABEL: sltiu1:
 ; O32: sltu ${{[0-9]+}}
 
 define i32 @sltiu1(i32 %a) {
@@ -176,7 +176,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: sltiu2:
+; O32-LABEL: sltiu2:
 ; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
 
@@ -187,7 +187,7 @@ entry:
   ret i32 %cond
 }
 
-; O32: sltiu3:
+; O32-LABEL: sltiu3:
 ; O32: sltu ${{[0-9]+}}
 
 define i32 @sltiu3(i32 %a) {
diff --git a/test/CodeGen/Mips/cmplarge.ll b/test/CodeGen/Mips/cmplarge.ll
index b16eab1..b082fa3 100644
--- a/test/CodeGen/Mips/cmplarge.ll
+++ b/test/CodeGen/Mips/cmplarge.ll
@@ -1,6406 +1,42 @@
 ; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=cmp16
 
-%union.yystype = type { i32 }
-%struct.LIST_HELP = type { %struct.LIST_HELP*, i8* }
-%struct._IO_FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct._IO_FILE*, i32, i32, i32, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i32, i32, [40 x i8] }
-%struct._IO_marker = type { %struct._IO_marker*, %struct._IO_FILE*, i32 }
-%struct.MEMORY_RESOURCEHELP = type { i8*, i8*, i8*, i8*, i32, i32, i32 }
-%struct.signature = type { i8*, i32, i32, i32, i32, i32, %struct.LIST_HELP* }
-%union.yyalloc = type { %union.yystype }
-%struct.term = type { i32, %union.anon, %struct.LIST_HELP*, i32, i32 }
-%union.anon = type { %struct.LIST_HELP* }
-%struct.CLAUSE_HELP = type { i32, i32, i32, i32, i32*, i32, %struct.LIST_HELP*, %struct.LIST_HELP*, i32, i32, %struct.LITERAL_HELP**, i32, i32, i32, i32 }
-%struct.LITERAL_HELP = type { i32, i32, i32, %struct.CLAUSE_HELP*, %struct.term* }
-%struct.DFG_VARENTRY = type { i8*, i32 }
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"
+target triple = "mipsel--linux-gnu"
 
-@dfg_nerrs = common global i32 0, align 4
-@dfg_char = common global i32 0, align 4
-@yypact = internal unnamed_addr constant [477 x i16] [i16 9, i16 -32, i16 35, i16 232, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -6, i16 13, i16 67, i16 20, i16 45, i16 53, i16 30, i16 -356, i16 110, i16 46, i16 118, i16 121, i16 -12, i16 73, i16 -356, i16 91, i16 84, i16 113, i16 112, i16 141, i16 123, i16 128, i16 132, i16 -356, i16 -356, i16 175, i16 152, i16 161, i16 155, i16 191, i16 2, i16 162, i16 180, i16 -356, i16 204, i16 232, i16 214, i16 173, i16 -356, i16 252, i16 176, i16 206, i16 209, i16 213, i16 226, i16 232, i16 47, i16 -356, i16 -356, i16 80, i16 218, i16 254, i16 224, i16 -14, i16 -356, i16 -356, i16 230, i16 233, i16 -356, i16 234, i16 241, i16 232, i16 242, i16 -356, i16 -356, i16 -356, i16 243, i16 237, i16 21, i16 244, i16 -356, i16 260, i16 -356, i16 246, i16 245, i16 250, i16 251, i16 294, i16 247, i16 248, i16 2, i16 232, i16 93, i16 -356, i16 -356, i16 232, i16 255, i16 272, i16 232, i16 253, i16 -356, i16 256, i16 -356, i16 232, i16 257, i16 232, i16 290, i16 232, i16 232, i16 -356, i16 -356, i16 -356, i16 258, i16 21, i16 261, i16 -356, i16 271, i16 -356, i16 262, i16 264, i16 14, i16 263, i16 317, i16 108, i16 -356, i16 -356, i16 265, i16 266, i16 80, i16 119, i16 -356, i16 85, i16 268, i16 312, i16 -356, i16 124, i16 -356, i16 270, i16 273, i16 269, i16 -356, i16 274, i16 -356, i16 309, i16 275, i16 -356, i16 -52, i16 276, i16 277, i16 232, i16 279, i16 -356, i16 -356, i16 281, i16 -356, i16 -356, i16 -356, i16 284, i16 287, i16 288, i16 321, i16 -356, i16 -356, i16 286, i16 108, i16 -356, i16 -356, i16 289, i16 232, i16 232, i16 138, i16 -356, i16 -356, i16 156, i16 291, i16 293, i16 232, i16 -17, i16 232, i16 232, i16 232, i16 232, i16 346, i16 232, i16 -356, i16 232, i16 -356, i16 40, i16 296, i16 -356, i16 -356, i16 297, i16 299, i16 302, i16 300, i16 -356, i16 303, i16 -356, i16 -356, i16 285, i16 301, i16 85, i16 232, i16 143, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 337, i16 16, i16 304, i16 298, i16 306, i16 -356, i16 32, i16 -356, i16 311, i16 305, i16 -356, i16 56, i16 308, i16 314, i16 310, i16 -356, i16 -356, i16 315, i16 318, i16 -356, i16 -356, i16 108, i16 -356, i16 -356, i16 313, i16 319, i16 156, i16 -2, i16 320, i16 -356, i16 -356, i16 232, i16 232, i16 316, i16 322, i16 232, i16 232, i16 323, i16 324, i16 307, i16 325, i16 326, i16 -356, i16 240, i16 -356, i16 327, i16 329, i16 108, i16 -356, i16 -356, i16 -356, i16 331, i16 332, i16 334, i16 333, i16 -356, i16 335, i16 -356, i16 336, i16 -356, i16 -356, i16 145, i16 -356, i16 -356, i16 -356, i16 96, i16 -356, i16 -356, i16 -356, i16 338, i16 340, i16 -356, i16 -356, i16 342, i16 232, i16 163, i16 339, i16 -356, i16 -356, i16 239, i16 343, i16 232, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 344, i16 -356, i16 -356, i16 341, i16 347, i16 348, i16 350, i16 -356, i16 3, i16 -356, i16 -15, i16 -356, i16 -356, i16 -356, i16 42, i16 232, i16 -356, i16 43, i16 -356, i16 349, i16 351, i16 -356, i16 -356, i16 96, i16 232, i16 352, i16 96, i16 96, i16 353, i16 355, i16 357, i16 57, i16 358, i16 361, i16 -356, i16 359, i16 -356, i16 163, i16 108, i16 360, i16 362, i16 -356, i16 363, i16 364, i16 -356, i16 44, i16 -356, i16 -13, i16 -356, i16 366, i16 365, i16 -356, i16 168, i16 372, i16 -356, i16 369, i16 -356, i16 -356, i16 -356, i16 96, i16 -356, i16 96, i16 232, i16 371, i16 373, i16 341, i16 -356, i16 -356, i16 0, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 367, i16 -356, i16 370, i16 -356, i16 375, i16 -356, i16 306, i16 374, i16 228, i16 377, i16 379, i16 380, i16 341, i16 -356, i16 -356, i16 50, i16 381, i16 376, i16 382, i16 -356, i16 383, i16 -356, i16 384, i16 66, i16 -356, i16 -356, i16 386, i16 228, i16 387, i16 385, i16 -356, i16 -356, i16 388, i16 7, i16 -356, i16 -356, i16 -356, i16 389, i16 232, i16 239, i16 -356, i16 228, i16 -356, i16 69, i16 239, i16 393, i16 232, i16 232, i16 90, i16 96, i16 306, i16 390, i16 -356, i16 -356, i16 153, i16 -356, i16 -356, i16 391, i16 179, i16 -356, i16 396, i16 395, i16 -356, i16 397, i16 239, i16 398, i16 401, i16 -356, i16 402, i16 399, i16 -356, i16 168, i16 96, i16 409, i16 408, i16 185, i16 -356, i16 410, i16 411, i16 -356, i16 405, i16 168, i16 -356, i16 -356, i16 400, i16 412, i16 -356, i16 168, i16 413, i16 198, i16 345, i16 -356, i16 -356, i16 168, i16 168, i16 394, i16 -356, i16 168, i16 -356], align 2
-@yytranslate = internal unnamed_addr constant [319 x i8] c"\00\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02@A\02\02E\02B\02\02\02\02\02\02\02\02\02\02\02F\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02C\02D\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\02\01\02\03\04\05\06\07\08\09\0A\0B\0C\0D\0E\0F\10\11\12\13\14\15\16\17\18\19\1A\1B\1C\1D\1E\1F !\22#$%&'()*+,-./0123456789:;<=>?", align 1
-@yycheck = internal unnamed_addr constant [507 x i16] [i16 3, i16 46, i16 103, i16 3, i16 19, i16 19, i16 361, i16 9, i16 20, i16 276, i16 3, i16 8, i16 164, i16 65, i16 27, i16 6, i16 18, i16 69, i16 32, i16 31, i16 18, i16 38, i16 19, i16 23, i16 364, i16 18, i16 5, i16 40, i16 21, i16 22, i16 23, i16 24, i16 64, i16 12, i16 27, i16 0, i16 48, i16 40, i16 53, i16 41, i16 33, i16 34, i16 45, i16 41, i16 37, i16 47, i16 63, i16 40, i16 41, i16 47, i16 390, i16 11, i16 55, i16 3, i16 47, i16 322, i16 59, i16 17, i16 325, i16 65, i16 46, i16 416, i16 60, i16 56, i16 62, i16 8, i16 64, i16 60, i16 71, i16 62, i16 425, i16 57, i16 58, i16 23, i16 67, i16 19, i16 19, i16 27, i16 179, i16 66, i16 232, i16 65, i16 26, i16 16, i16 185, i16 69, i16 66, i16 90, i16 91, i16 36, i16 40, i16 358, i16 95, i16 360, i16 49, i16 98, i16 66, i16 65, i16 18, i16 3, i16 103, i16 69, i16 105, i16 18, i16 107, i16 108, i16 258, i16 65, i16 65, i16 65, i16 64, i16 69, i16 69, i16 69, i16 18, i16 68, i16 69, i16 21, i16 22, i16 23, i16 24, i16 41, i16 4, i16 27, i16 14, i16 128, i16 41, i16 47, i16 131, i16 33, i16 34, i16 65, i16 47, i16 37, i16 65, i16 69, i16 40, i16 41, i16 69, i16 66, i16 60, i16 449, i16 62, i16 47, i16 64, i16 60, i16 149, i16 62, i16 64, i16 64, i16 29, i16 459, i16 56, i16 254, i16 63, i16 65, i16 60, i16 465, i16 62, i16 69, i16 427, i16 68, i16 69, i16 471, i16 472, i16 168, i16 169, i16 475, i16 60, i16 61, i16 173, i16 3, i16 59, i16 176, i16 18, i16 178, i16 179, i16 180, i16 181, i16 67, i16 183, i16 18, i16 185, i16 450, i16 43, i16 337, i16 18, i16 68, i16 69, i16 66, i16 22, i16 23, i16 68, i16 69, i16 66, i16 27, i16 64, i16 41, i16 201, i16 202, i16 25, i16 33, i16 34, i16 47, i16 41, i16 37, i16 68, i16 69, i16 40, i16 41, i16 47, i16 68, i16 69, i16 68, i16 69, i16 47, i16 60, i16 65, i16 62, i16 64, i16 64, i16 68, i16 69, i16 60, i16 63, i16 62, i16 35, i16 64, i16 60, i16 67, i16 62, i16 51, i16 18, i16 19, i16 237, i16 21, i16 32, i16 64, i16 24, i16 242, i16 243, i16 27, i16 66, i16 246, i16 247, i16 290, i16 18, i16 68, i16 69, i16 21, i16 18, i16 254, i16 24, i16 68, i16 69, i16 41, i16 42, i16 18, i16 18, i16 19, i16 21, i16 47, i16 10, i16 24, i16 50, i16 37, i16 68, i16 69, i16 54, i16 41, i16 56, i16 65, i16 63, i16 41, i16 60, i16 47, i16 62, i16 64, i16 52, i16 47, i16 41, i16 41, i16 285, i16 286, i16 56, i16 67, i16 47, i16 47, i16 60, i16 292, i16 62, i16 67, i16 60, i16 39, i16 62, i16 56, i16 66, i16 64, i16 64, i16 60, i16 60, i16 62, i16 62, i16 66, i16 44, i16 64, i16 64, i16 64, i16 64, i16 15, i16 65, i16 314, i16 66, i16 63, i16 66, i16 64, i16 69, i16 45, i16 28, i16 66, i16 323, i16 65, i16 67, i16 65, i16 67, i16 64, i16 55, i16 64, i16 66, i16 65, i16 13, i16 19, i16 66, i16 336, i16 69, i16 67, i16 66, i16 64, i16 69, i16 30, i16 19, i16 386, i16 66, i16 69, i16 69, i16 66, i16 69, i16 66, i16 351, i16 65, i16 63, i16 65, i16 64, i16 7, i16 69, i16 66, i16 19, i16 66, i16 361, i16 66, i16 405, i16 65, i16 64, i16 66, i16 65, i16 63, i16 66, i16 66, i16 65, i16 65, i16 65, i16 64, i16 417, i16 65, i16 419, i16 69, i16 66, i16 422, i16 67, i16 65, i16 113, i16 66, i16 69, i16 65, i16 68, i16 66, i16 66, i16 128, i16 66, i16 66, i16 66, i16 66, i16 66, i16 66, i16 65, i16 64, i16 64, i16 442, i16 64, i16 66, i16 65, i16 62, i16 3, i16 201, i16 66, i16 69, i16 66, i16 65, i16 64, i16 66, i16 69, i16 64, i16 64, i16 416, i16 64, i16 70, i16 65, i16 65, i16 69, i16 64, i16 67, i16 424, i16 425, i16 66, i16 66, i16 64, i16 66, i16 65, i16 69, i16 66, i16 64, i16 66, i16 60, i16 69, i16 65, i16 64, i16 69, i16 64, i16 62, i16 69, i16 65, i16 67, i16 65, i16 64, i16 64, i16 64, i16 449, i16 65, i16 64, i16 40, i16 65, i16 68, i16 66, i16 237, i16 67, i16 65, i16 459, i16 69, i16 69, i16 66, i16 69, i16 65, i16 465, i16 68, i16 70, i16 67, i16 69, i16 67, i16 471, i16 472, i16 69, i16 69, i16 475, i16 65, i16 69, i16 65, i16 65, i16 65, i16 243, i16 66, i16 393, i16 411, i16 90, i16 405, i16 451, i16 393, i16 447, i16 419, i16 63, i16 -1, i16 336, i16 -1, i16 285, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 178], align 2
-@yytable = internal unnamed_addr constant [507 x i16] [i16 10, i16 77, i16 139, i16 388, i16 331, i16 99, i16 384, i16 261, i16 30, i16 301, i16 293, i16 328, i16 196, i16 184, i16 362, i16 1, i16 262, i16 185, i16 62, i16 31, i16 5, i16 209, i16 329, i16 389, i16 387, i16 5, i16 110, i16 363, i16 67, i16 294, i16 295, i16 68, i16 3, i16 111, i16 296, i16 4, i16 32, i16 58, i16 332, i16 263, i16 297, i16 298, i16 65, i16 6, i16 299, i16 264, i16 210, i16 300, i16 6, i16 7, i16 407, i16 223, i16 88, i16 388, i16 7, i16 339, i16 94, i16 224, i16 342, i16 11, i16 154, i16 428, i16 8, i16 73, i16 9, i16 348, i16 55, i16 8, i16 106, i16 9, i16 436, i16 155, i16 156, i16 389, i16 425, i16 249, i16 349, i16 362, i16 213, i16 12, i16 257, i16 240, i16 250, i16 13, i16 221, i16 185, i16 15, i16 58, i16 126, i16 19, i16 363, i16 382, i16 130, i16 383, i16 16, i16 134, i16 21, i16 245, i16 5, i16 293, i16 138, i16 246, i16 141, i16 5, i16 144, i16 138, i16 284, i16 333, i16 335, i16 359, i16 25, i16 176, i16 336, i16 360, i16 5, i16 89, i16 90, i16 67, i16 294, i16 295, i16 68, i16 6, i16 26, i16 296, i16 23, i16 94, i16 6, i16 7, i16 172, i16 297, i16 298, i16 418, i16 7, i16 299, i16 431, i16 419, i16 300, i16 6, i16 419, i16 34, i16 8, i16 454, i16 9, i16 7, i16 91, i16 8, i16 188, i16 9, i16 37, i16 169, i16 28, i16 464, i16 73, i16 281, i16 36, i16 437, i16 8, i16 468, i16 9, i16 360, i16 438, i16 127, i16 128, i16 473, i16 474, i16 198, i16 199, i16 476, i16 161, i16 162, i16 205, i16 369, i16 38, i16 208, i16 5, i16 138, i16 138, i16 214, i16 218, i16 40, i16 220, i16 5, i16 138, i16 455, i16 41, i16 354, i16 5, i16 167, i16 168, i16 43, i16 370, i16 371, i16 175, i16 176, i16 44, i16 372, i16 45, i16 6, i16 172, i16 235, i16 47, i16 373, i16 374, i16 7, i16 6, i16 375, i16 200, i16 201, i16 376, i16 6, i16 7, i16 236, i16 237, i16 291, i16 292, i16 7, i16 8, i16 50, i16 9, i16 52, i16 202, i16 441, i16 442, i16 8, i16 51, i16 9, i16 53, i16 314, i16 8, i16 59, i16 9, i16 60, i16 5, i16 66, i16 205, i16 67, i16 62, i16 78, i16 68, i16 267, i16 214, i16 69, i16 82, i16 271, i16 273, i16 319, i16 5, i16 444, i16 243, i16 67, i16 5, i16 138, i16 68, i16 458, i16 459, i16 6, i16 70, i16 5, i16 5, i16 280, i16 67, i16 7, i16 79, i16 68, i16 71, i16 400, i16 470, i16 471, i16 72, i16 6, i16 73, i16 83, i16 84, i16 6, i16 8, i16 7, i16 9, i16 85, i16 86, i16 7, i16 6, i16 6, i16 134, i16 315, i16 73, i16 95, i16 7, i16 7, i16 8, i16 321, i16 9, i16 98, i16 8, i16 96, i16 9, i16 73, i16 102, i16 103, i16 104, i16 8, i16 8, i16 9, i16 9, i16 109, i16 114, i16 105, i16 107, i16 108, i16 113, i16 121, i16 118, i16 334, i16 117, i16 119, i16 124, i16 120, i16 123, i16 132, i16 142, i16 136, i16 340, i16 137, i16 131, i16 147, i16 140, i16 149, i16 150, i16 158, i16 152, i16 153, i16 159, i16 174, i16 165, i16 315, i16 164, i16 173, i16 177, i16 178, i16 179, i16 182, i16 194, i16 403, i16 186, i16 181, i16 183, i16 189, i16 187, i16 190, i16 377, i16 191, i16 192, i16 195, i16 193, i16 219, i16 232, i16 197, i16 239, i16 206, i16 214, i16 207, i16 403, i16 225, i16 242, i16 227, i16 228, i16 229, i16 230, i16 233, i16 231, i16 241, i16 248, i16 276, i16 429, i16 251, i16 403, i16 243, i16 253, i16 433, i16 247, i16 252, i16 148, i16 255, i16 258, i16 256, i16 269, i16 259, i16 266, i16 166, i16 270, i16 274, i16 275, i16 277, i16 278, i16 282, i16 283, i16 285, i16 286, i16 448, i16 287, i16 288, i16 289, i16 318, i16 388, i16 234, i16 310, i16 290, i16 311, i16 312, i16 322, i16 320, i16 323, i16 325, i16 326, i16 214, i16 327, i16 472, i16 338, i16 341, i16 337, i16 346, i16 345, i16 435, i16 214, i16 347, i16 350, i16 351, i16 355, i16 356, i16 352, i16 357, i16 367, i16 368, i16 380, i16 358, i16 381, i16 385, i16 393, i16 386, i16 413, i16 395, i16 397, i16 399, i16 404, i16 405, i16 406, i16 411, i16 377, i16 414, i16 417, i16 363, i16 423, i16 415, i16 420, i16 260, i16 422, i16 440, i16 377, i16 424, i16 427, i16 434, i16 443, i16 445, i16 377, i16 446, i16 475, i16 449, i16 447, i16 465, i16 377, i16 377, i16 450, i16 451, i16 377, i16 457, i16 462, i16 460, i16 461, i16 466, i16 268, i16 469, i16 408, i16 426, i16 125, i16 421, i16 456, i16 409, i16 452, i16 430, i16 100, i16 0, i16 353, i16 0, i16 313, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 212], align 2
-@dfg_lval = common global %union.yystype zeroinitializer, align 4
-@yydefact = internal unnamed_addr constant [477 x i8] c"\00\00\00\00\01bca`_\00\00\00\00\12\00\00\AE2\00\00\14\00\00G\00\00\08\00\1A\00\00\00\AF4h\00\00\00\0A\00\00 \02\00\00\00\00H\8C\00\00\00\00\00\00\00\16\18\00\00$\00\00\C0\B1\00\00~\00\00\00\00}56|\00\00\00i\A8\04\00\00\00\00\00\00\00\00\00\00\1C\1E\00\00*\00\00\C1\003\00\00\00>\00\008EF\00\00\00\8D\11\05\00\00\00\00\0C\00\15\17\00\00\00\00\22\00\00\00\C3\00\B0\00\88\00:\00?\00\00\8A\00\00\00\00\00\A9\09\00\0E\10\0F\00\00\00\0010\00\00\1B\1D\00\00\00\00&(\00\00\00\00\00\00\00\00\00\00\00\80\00I\00\00\AA\0B\00\00\00\00\19\00!#\00\00\00\00\00,.\13\C2\C4\B5\B3\00\00\00f;d\00B\00\00\8B\00\00\00\00\AC\06\00\00\03\1F\00%'\00\00\00\00\00\89\7F\00\00\00\00\00\00\00\00\00\00\00\8E\00\07\00\00\00+-\B4\00\00\00\00\B2\00e\009C\00@7DTmk\90\00\00\0D)\00\00\00\00\B6g\00\00\00[X]^YZ\00\5CUK\00\00\00M\00\81\00\AB\AD/\00\00\BC\00\BA\00\00=A\00\00\00\00\00\00\00\00\00\00\00\B8\00\B7\00\00\00\00L\00\00V\00Qoj\00\00\8F\00\00\BB\00<NJ\00P\00\00\00\00Kpq\83l\9F\9C\A2\A1\9D\9E\9B\A0\9A\00\98\BE\B9\00WR\00\00\00\00\00K\84\85\00\A3\00\00O\00r\00\00vx\00\00\00\00\A6\A7\00\00\99\BF\BD\00\00\00u\00n\00\00\00\00\00\00\00s\00w\87\00z\82\00\00\A4\00\00y\00\00\00\00S\00\00{\00\00\00\00\00\92\00\00\86\94\00\A5t\00\00\93\00\00\00\00\91\95\00\00\00\96\00\97", align 1
-@yyr2 = internal unnamed_addr constant [197 x i8] c"\00\02\0A\0B\05\05\05\05\00\05\00\05\00\05\01\01\01\06\00\09\00\05\01\03\01\05\00\05\01\03\01\05\00\05\01\03\00\05\01\03\01\05\00\05\01\03\01\05\01\01\00\05\00\02\01\07\02\07\00\00\0B\09\00\01\01\03\01\03\08\01\01\00\02\00\07\00\02\01\04\06\04\00\00\0A\00\01\01\03\01\01\01\01\01\01\01\01\01\01\01\01\01\03\01\04\00\02\0A\00\0B\00\07\00\01\01\00\00\0A\04\01\03\01\04\01\03\01\01\01\06\04\00\07\00\01\01\08\04\01\04\01\03\00\02\00\09\00\0F\01\03\00\04\03\05\00\03\01\01\01\01\01\01\01\01\01\00\03\07\01\01\00\02\00\06\00\03\00\02\05\00\09\01\03\00\03\04\04\06\01\03\01\06\00\02\01\02\05\01\03", align 1
-@dfg_DESC.0 = internal unnamed_addr global i8* null
-@dfg_DESC.1 = internal unnamed_addr global i8* null
-@dfg_DESC.2 = internal unnamed_addr global i8* null
-@dfg_DESC.3 = internal unnamed_addr global i8* null
-@dfg_DESC.4 = internal unnamed_addr global i32 0
-@dfg_DESC.5 = internal unnamed_addr global i8* null
-@dfg_DESC.6 = internal unnamed_addr global i8* null
-@dfg_SORTDECLLIST = internal unnamed_addr global %struct.LIST_HELP* null, align 4
-@dfg_AXIOMLIST = internal unnamed_addr global %struct.LIST_HELP* null, align 4
-@dfg_CONJECLIST = internal unnamed_addr global %struct.LIST_HELP* null, align 4
-@dfg_IGNORE = internal unnamed_addr global i32 0, align 4
-@.str = private unnamed_addr constant [9 x i8] c"set_flag\00", align 1
-@.str1 = private unnamed_addr constant [12 x i8] c"set_DomPred\00", align 1
-@.str2 = private unnamed_addr constant [15 x i8] c"set_precedence\00", align 1
-@stdout = external global %struct._IO_FILE*
-@.str3 = private unnamed_addr constant [38 x i8] c"\0A Line %d: Symbol is not a variable.\0A\00", align 1
-@dfg_LINENUMBER = common global i32 0, align 4
-@.str4 = private unnamed_addr constant [39 x i8] c"\0A Line %d: Symbol is not a predicate.\0A\00", align 1
-@dfg_AXCLAUSES = internal unnamed_addr global %struct.LIST_HELP* null, align 4
-@dfg_CONCLAUSES = internal unnamed_addr global %struct.LIST_HELP* null, align 4
-@.str5 = private unnamed_addr constant [6 x i8] c"SPASS\00", align 1
-@dfg_PROOFLIST = internal unnamed_addr global %struct.LIST_HELP* null, align 4
-@.str6 = private unnamed_addr constant [11 x i8] c"splitlevel\00", align 1
-@dfg_TERMLIST = internal unnamed_addr global %struct.LIST_HELP* null, align 4
-@dfg_IGNORETEXT = common global i32 0, align 4
-@.str7 = private unnamed_addr constant [22 x i8] c"\0A Undefined symbol %s\00", align 1
-@.str8 = private unnamed_addr constant [19 x i8] c" in DomPred list.\0A\00", align 1
-@.str9 = private unnamed_addr constant [30 x i8] c"\0A Symbol %s isn't a predicate\00", align 1
-@.str10 = private unnamed_addr constant [24 x i8] c"\0A Found unknown flag %s\00", align 1
-@dfg_FLAGS = internal unnamed_addr global i32* null, align 4
-@.str11 = private unnamed_addr constant [23 x i8] c"\0A Undefined symbol %s \00", align 1
-@.str12 = private unnamed_addr constant [22 x i8] c" in precedence list.\0A\00", align 1
-@dfg_PRECEDENCE = internal unnamed_addr global i32* null, align 4
-@dfg_USERPRECEDENCE = internal unnamed_addr global %struct.LIST_HELP* null, align 4
-@.str13 = private unnamed_addr constant [21 x i8] c"in precedence list.\0A\00", align 1
-@.str14 = private unnamed_addr constant [27 x i8] c"\0A Invalid symbol status %s\00", align 1
-@.str15 = private unnamed_addr constant [21 x i8] c" in precedence list.\00", align 1
-@yyr1 = internal unnamed_addr constant [197 x i8] c"\00GHIJKLMNNOOPPQQQRSSTTUUVVWWXXYYZZ[[\5C\5C]]^^__``aabbccddeeeefgehiijjkklmmnnooppqqqqrsqttuuvvvwwxxyyyyyzz{{||}~}\7F\7F\80\80\81\82\83\81\84\85\85\86\86\87\87\88\88\88\88\88\89\89\8A\8A\8B\8B\8C\8D\8D\8E\8E\8F\8F\91\90\92\92\93\93\94\94\95\95\97\96\98\98\98\98\98\98\98\98\98\99\99\99\9A\9A\9B\9B\9D\9C\9E\9E\9F\9F\A0\A1\A0\A2\A2\A3\A3\A4\A4\A4\A5\A5\A6\A6\A7\A7\A8\A8\A9\AA\AA", align 1
-@yypgoto = internal unnamed_addr constant [100 x i16] [i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 392, i16 -356, i16 -356, i16 259, i16 -356, i16 -356, i16 -356, i16 -356, i16 202, i16 -356, i16 -356, i16 216, i16 -152, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 267, i16 -356, i16 -356, i16 -340, i16 -267, i16 -356, i16 -356, i16 -356, i16 70, i16 -356, i16 -356, i16 -356, i16 -3, i16 -355, i16 235, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 87, i16 -356, i16 -356, i16 33, i16 78, i16 68, i16 -356, i16 -45, i16 -356, i16 -356, i16 92, i16 39, i16 -101, i16 328, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -308, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 -356, i16 154, i16 -356, i16 -356, i16 425, i16 207], align 2
-@yydefgoto = internal unnamed_addr constant [100 x i16] [i16 -1, i16 2, i16 14, i16 20, i16 27, i16 87, i16 122, i16 39, i16 54, i16 160, i16 157, i16 17, i16 18, i16 29, i16 56, i16 57, i16 42, i16 92, i16 93, i16 61, i16 129, i16 97, i16 170, i16 171, i16 133, i16 203, i16 204, i16 163, i16 24, i16 46, i16 74, i16 180, i16 244, i16 75, i16 143, i16 272, i16 217, i16 48, i16 112, i16 35, i16 222, i16 324, i16 343, i16 361, i16 398, i16 302, i16 344, i16 303, i16 304, i16 305, i16 76, i16 215, i16 216, i16 49, i16 80, i16 308, i16 307, i16 364, i16 365, i16 416, i16 439, i16 366, i16 401, i16 402, i16 432, i16 306, i16 330, i16 390, i16 391, i16 392, i16 145, i16 146, i16 81, i16 115, i16 279, i16 309, i16 453, i16 463, i16 467, i16 378, i16 394, i16 379, i16 412, i16 410, i16 116, i16 151, i16 226, i16 254, i16 22, i16 33, i16 101, i16 211, i16 238, i16 265, i16 316, i16 317, i16 396, i16 63, i16 64, i16 135], align 2
-@yytname = internal unnamed_addr constant [172 x i8*] [i8* getelementptr inbounds ([5 x i8]* @.str60, i32 0, i32 0), i8* getelementptr inbounds ([6 x i8]* @.str61, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str62, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @.str63, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str64, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str65, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str66, i32 0, i32 0), i8* getelementptr inbounds ([7 x i8]* @.str67, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str68, i32 0, i32 0), i8* getelementptr inbounds ([15 x i8]* @.str69, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str70, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @.str71, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str72, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str73, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8]* @.str74, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str75, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8]* @.str76, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @.str77, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str78, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str79, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str80, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str81, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str82, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str83, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str84, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8]* @.str85, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str86, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str87, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str88, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str89, i32 0, i32 0), i8* getelementptr inbounds ([14 x i8]* @.str90, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str91, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str92, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str93, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str94, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str95, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str96, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @.str97, i32 0, i32 0), i8* getelementptr inbounds ([14 x i8]* @.str98, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str99, i32 0, i32 0), i8* getelementptr inbounds ([7 x i8]* @.str100, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str101, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str102, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str103, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str104, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str105, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str106, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str107, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8]* @.str108, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str109, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str110, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str111, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str112, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str113, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str114, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8]* @.str115, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str116, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str117, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str118, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str119, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @.str120, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str121, i32 0, i32 0), i8* getelementptr inbounds ([7 x i8]* @.str122, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str123, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @.str124, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @.str125, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @.str126, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @.str127, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @.str128, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @.str129, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @.str130, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @.str131, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @.str132, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str133, i32 0, i32 0), i8* getelementptr inbounds ([5 x i8]* @.str134, i32 0, i32 0), i8* getelementptr inbounds ([7 x i8]* @.str135, i32 0, i32 0), i8* getelementptr inbounds ([7 x i8]* @.str136, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str137, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str138, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str139, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @.str140, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str141, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str142, i32 0, i32 0), i8* getelementptr inbounds ([14 x i8]* @.str143, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8]* @.str144, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8]* @.str145, i32 0, i32 0), i8* getelementptr inbounds ([5 x i8]* @.str146, i32 0, i32 0), i8* getelementptr inbounds ([14 x i8]* @.str147, i32 0, i32 0), i8* getelementptr inbounds ([14 x i8]* @.str148, i32 0, i32 0), i8* getelementptr inbounds ([5 x i8]* @.str149, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str150, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str151, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8]* @.str152, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8]* @.str153, i32 0, i32 0), i8* getelementptr inbounds ([3 x i8]* @.str154, i32 0, i32 0), i8* getelementptr inbounds ([15 x i8]* @.str155, i32 0, i32 0), i8* getelementptr inbounds ([15 x i8]* @.str156, i32 0, i32 0), i8* getelementptr inbounds ([6 x i8]* @.str157, i32 0, i32 0), i8* getelementptr inbounds ([7 x i8]* @.str158, i32 0, i32 0), i8* getelementptr inbounds ([19 x i8]* @.str159, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str160, i32 0, i32 0), i8* getelementptr inbounds ([5 x i8]* @.str161, i32 0, i32 0), i8* getelementptr inbounds ([3 x i8]* @.str162, i32 0, i32 0), i8* getelementptr inbounds ([3 x i8]* @.str163, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @.str164, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str165, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str166, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str167, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str168, i32 0, i32 0), i8* getelementptr inbounds ([7 x i8]* @.str169, i32 0, i32 0), i8* getelementptr inbounds ([16 x i8]* @.str170, i32 0, i32 0), i8* getelementptr inbounds ([15 x i8]* @.str171, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str172, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @.str173, i32 0, i32 0), i8* getelementptr inbounds ([3 x i8]* @.str174, i32 0, i32 0), i8* getelementptr inbounds ([3 x i8]* @.str175, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str176, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @.str177, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str178, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @.str179, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str180, i32 0, i32 0), i8* getelementptr inbounds ([3 x i8]* @.str181, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str182, i32 0, i32 0), i8* getelementptr inbounds ([6 x i8]* @.str183, i32 0, i32 0), i8* getelementptr inbounds ([15 x i8]* @.str184, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str185, i32 0, i32 0), i8* getelementptr inbounds ([3 x i8]* @.str186, i32 0, i32 0), i8* getelementptr inbounds ([14 x i8]* @.str187, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8]* @.str188, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str189, i32 0, i32 0), i8* getelementptr inbounds ([3 x i8]* @.str190, i32 0, i32 0), i8* getelementptr inbounds ([3 x i8]* @.str191, i32 0, i32 0), i8* getelementptr inbounds ([14 x i8]* @.str192, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @.str193, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @.str194, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str195, i32 0, i32 0), i8* getelementptr inbounds ([5 x i8]* @.str196, i32 0, i32 0), i8* getelementptr inbounds ([14 x i8]* @.str197, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8]* @.str198, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str199, i32 0, i32 0), i8* getelementptr inbounds ([14 x i8]* @.str200, i32 0, i32 0), i8* getelementptr inbounds ([5 x i8]* @.str201, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str202, i32 0, i32 0), i8* getelementptr inbounds ([14 x i8]* @.str203, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str204, i32 0, i32 0), i8* getelementptr inbounds ([3 x i8]* @.str205, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8]* @.str206, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str207, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8]* @.str208, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str209, i32 0, i32 0), i8* getelementptr inbounds ([14 x i8]* @.str210, i32 0, i32 0), i8* getelementptr inbounds ([3 x i8]* @.str211, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str212, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @.str213, i32 0, i32 0), i8* getelementptr inbounds ([7 x i8]* @.str214, i32 0, i32 0), i8* getelementptr inbounds ([15 x i8]* @.str215, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str216, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @.str217, i32 0, i32 0), i8* getelementptr inbounds ([6 x i8]* @.str218, i32 0, i32 0), i8* getelementptr inbounds ([16 x i8]* @.str219, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str220, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @.str221, i32 0, i32 0), i8* getelementptr inbounds ([6 x i8]* @.str222, i32 0, i32 0), i8* getelementptr inbounds ([11 x i8]* @.str223, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str224, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str225, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str226, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8]* @.str227, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str228, i32 0, i32 0), i8* getelementptr inbounds ([9 x i8]* @.str229, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @.str230, i32 0, i32 0), i8* null], align 4
-@.str16 = private unnamed_addr constant [25 x i8] c"parse error, unexpected \00", align 1
-@.str17 = private unnamed_addr constant [13 x i8] c", expecting \00", align 1
-@.str18 = private unnamed_addr constant [5 x i8] c" or \00", align 1
-@.str20 = private unnamed_addr constant [12 x i8] c"parse error\00", align 1
-@.str21 = private unnamed_addr constant [22 x i8] c"parser stack overflow\00", align 1
-@.str22 = private unnamed_addr constant [15 x i8] c"\0A Line %i: %s\0A\00", align 1
-@.str24 = private unnamed_addr constant [12 x i8] c"satisfiable\00", align 1
-@.str25 = private unnamed_addr constant [14 x i8] c"unsatisfiable\00", align 1
-@.str26 = private unnamed_addr constant [8 x i8] c"unknown\00", align 1
-@stderr = external global %struct._IO_FILE*
-@.str27 = private unnamed_addr constant [31 x i8] c"\0A\09Error in file %s at line %d\0A\00", align 1
-@.str28 = private unnamed_addr constant [12 x i8] c"dfgparser.y\00", align 1
-@.str29 = private unnamed_addr constant [47 x i8] c"\0A In dfg_ProblemStatusString: Invalid status.\0A\00", align 1
-@.str30 = private unnamed_addr constant [133 x i8] c"\0A Please report this error via email to spass@mpi-sb.mpg.de including\0A the SPASS version, input problem, options, operating system.\0A\00", align 1
-@.str31 = private unnamed_addr constant [30 x i8] c"list_of_descriptions.\0A  name(\00", align 1
-@.str32 = private unnamed_addr constant [6 x i8] c"{* *}\00", align 1
-@.str33 = private unnamed_addr constant [13 x i8] c").\0A  author(\00", align 1
-@.str34 = private unnamed_addr constant [4 x i8] c").\0A\00", align 1
-@.str35 = private unnamed_addr constant [11 x i8] c"  version(\00", align 1
-@.str36 = private unnamed_addr constant [9 x i8] c"  logic(\00", align 1
-@.str37 = private unnamed_addr constant [10 x i8] c"  status(\00", align 1
-@.str38 = private unnamed_addr constant [18 x i8] c").\0A  description(\00", align 1
-@.str39 = private unnamed_addr constant [8 x i8] c"  date(\00", align 1
-@.str40 = private unnamed_addr constant [13 x i8] c"end_of_list.\00", align 1
-@dfg_VARLIST = internal unnamed_addr global %struct.LIST_HELP* null, align 4
-@.str41 = private unnamed_addr constant [55 x i8] c"\0A In dfg_VarCheck: List of variables should be empty!\0A\00", align 1
-@symbol_STANDARDVARCOUNTER = external global i32
-@memory_FREEDBYTES = external global i32
-@memory_ARRAY = external global [0 x %struct.MEMORY_RESOURCEHELP*]
-@dfg_VARDECL = internal unnamed_addr global i1 false
-@dfg_SYMBOLLIST = internal unnamed_addr global %struct.LIST_HELP* null, align 4
-@symbol_TYPESTATBITS = external constant i32
-@symbol_SIGNATURE = external global %struct.signature**
-@.str42 = private unnamed_addr constant [44 x i8] c"\0A Line %d: Symbol is not a sort predicate.\0A\00", align 1
-@.str43 = private unnamed_addr constant [33 x i8] c"\0A Line %d: undefined symbol %s.\0A\00", align 1
-@.str44 = private unnamed_addr constant [38 x i8] c"\0A Line %d: Symbol is not a function.\0A\00", align 1
-@symbol_TYPEMASK = external constant i32
-@fol_FALSE = external global i32
-@fol_TRUE = external global i32
-@.str45 = private unnamed_addr constant [33 x i8] c"\0A Line %d: Undefined symbol %s.\0A\00", align 1
-@.str46 = private unnamed_addr constant [30 x i8] c"\0A Line %u: Free Variable %s.\0A\00", align 1
-@.str47 = private unnamed_addr constant [11 x i8] c"\0A Line %u:\00", align 1
-@.str48 = private unnamed_addr constant [21 x i8] c" The actual arity %u\00", align 1
-@.str49 = private unnamed_addr constant [22 x i8] c" of symbol %s differs\00", align 1
-@.str50 = private unnamed_addr constant [30 x i8] c" from the previous arity %u.\0A\00", align 1
-@.str51 = private unnamed_addr constant [50 x i8] c"\0A Line %u: Symbol %s was declared with arity %u.\0A\00", align 1
-@.str52 = private unnamed_addr constant [58 x i8] c"\0A Line %u: symbols with arbitrary arity are not allowed.\0A\00", align 1
-@.str53 = private unnamed_addr constant [46 x i8] c"\0A Line %u: symbol %s was already declared as \00", align 1
-@.str54 = private unnamed_addr constant [11 x i8] c"function.\0A\00", align 1
-@.str55 = private unnamed_addr constant [12 x i8] c"predicate.\0A\00", align 1
-@.str56 = private unnamed_addr constant [10 x i8] c"junctor.\0A\00", align 1
-@.str57 = private unnamed_addr constant [15 x i8] c"unknown type.\0A\00", align 1
-@.str58 = private unnamed_addr constant [57 x i8] c"\0A Line %u: symbol %s was already declared with arity %d\0A\00", align 1
-@stack_POINTER = external global i32
-@dfg_in = external global %struct._IO_FILE*
-@.str59 = private unnamed_addr constant [3 x i8] c"\0A\0A\00", align 1
-@.str60 = private unnamed_addr constant [5 x i8] c"$end\00", align 1
-@.str61 = private unnamed_addr constant [6 x i8] c"error\00", align 1
-@.str62 = private unnamed_addr constant [11 x i8] c"$undefined\00", align 1
-@.str63 = private unnamed_addr constant [8 x i8] c"DFG_AND\00", align 1
-@.str64 = private unnamed_addr constant [11 x i8] c"DFG_AUTHOR\00", align 1
-@.str65 = private unnamed_addr constant [11 x i8] c"DFG_AXIOMS\00", align 1
-@.str66 = private unnamed_addr constant [12 x i8] c"DFG_BEGPROB\00", align 1
-@.str67 = private unnamed_addr constant [7 x i8] c"DFG_BY\00", align 1
-@.str68 = private unnamed_addr constant [11 x i8] c"DFG_CLAUSE\00", align 1
-@.str69 = private unnamed_addr constant [15 x i8] c"DFG_CLOSEBRACE\00", align 1
-@.str70 = private unnamed_addr constant [12 x i8] c"DFG_CLSLIST\00", align 1
-@.str71 = private unnamed_addr constant [8 x i8] c"DFG_CNF\00", align 1
-@.str72 = private unnamed_addr constant [12 x i8] c"DFG_CONJECS\00", align 1
-@.str73 = private unnamed_addr constant [9 x i8] c"DFG_DATE\00", align 1
-@.str74 = private unnamed_addr constant [13 x i8] c"DFG_DECLLIST\00", align 1
-@.str75 = private unnamed_addr constant [9 x i8] c"DFG_DESC\00", align 1
-@.str76 = private unnamed_addr constant [13 x i8] c"DFG_DESCLIST\00", align 1
-@.str77 = private unnamed_addr constant [8 x i8] c"DFG_DNF\00", align 1
-@.str78 = private unnamed_addr constant [12 x i8] c"DFG_DOMPRED\00", align 1
-@.str79 = private unnamed_addr constant [12 x i8] c"DFG_ENDLIST\00", align 1
-@.str80 = private unnamed_addr constant [12 x i8] c"DFG_ENDPROB\00", align 1
-@.str81 = private unnamed_addr constant [10 x i8] c"DFG_EQUAL\00", align 1
-@.str82 = private unnamed_addr constant [10 x i8] c"DFG_EQUIV\00", align 1
-@.str83 = private unnamed_addr constant [11 x i8] c"DFG_EXISTS\00", align 1
-@.str84 = private unnamed_addr constant [10 x i8] c"DFG_FALSE\00", align 1
-@.str85 = private unnamed_addr constant [13 x i8] c"DFG_FORMLIST\00", align 1
-@.str86 = private unnamed_addr constant [12 x i8] c"DFG_FORMULA\00", align 1
-@.str87 = private unnamed_addr constant [11 x i8] c"DFG_FORALL\00", align 1
-@.str88 = private unnamed_addr constant [11 x i8] c"DFG_FREELY\00", align 1
-@.str89 = private unnamed_addr constant [9 x i8] c"DFG_FUNC\00", align 1
-@.str90 = private unnamed_addr constant [14 x i8] c"DFG_GENERATED\00", align 1
-@.str91 = private unnamed_addr constant [11 x i8] c"DFG_GENSET\00", align 1
-@.str92 = private unnamed_addr constant [11 x i8] c"DFG_HYPOTH\00", align 1
-@.str93 = private unnamed_addr constant [12 x i8] c"DFG_IMPLIED\00", align 1
-@.str94 = private unnamed_addr constant [12 x i8] c"DFG_IMPLIES\00", align 1
-@.str95 = private unnamed_addr constant [10 x i8] c"DFG_LOGIC\00", align 1
-@.str96 = private unnamed_addr constant [9 x i8] c"DFG_NAME\00", align 1
-@.str97 = private unnamed_addr constant [8 x i8] c"DFG_NOT\00", align 1
-@.str98 = private unnamed_addr constant [14 x i8] c"DFG_OPENBRACE\00", align 1
-@.str99 = private unnamed_addr constant [11 x i8] c"DFG_OPERAT\00", align 1
-@.str100 = private unnamed_addr constant [7 x i8] c"DFG_OR\00", align 1
-@.str101 = private unnamed_addr constant [9 x i8] c"DFG_PREC\00", align 1
-@.str102 = private unnamed_addr constant [9 x i8] c"DFG_PRED\00", align 1
-@.str103 = private unnamed_addr constant [12 x i8] c"DFG_PRDICAT\00", align 1
-@.str104 = private unnamed_addr constant [12 x i8] c"DFG_PRFLIST\00", align 1
-@.str105 = private unnamed_addr constant [12 x i8] c"DFG_QUANTIF\00", align 1
-@.str106 = private unnamed_addr constant [10 x i8] c"DFG_SATIS\00", align 1
-@.str107 = private unnamed_addr constant [12 x i8] c"DFG_SETFLAG\00", align 1
-@.str108 = private unnamed_addr constant [13 x i8] c"DFG_SETTINGS\00", align 1
-@.str109 = private unnamed_addr constant [12 x i8] c"DFG_SYMLIST\00", align 1
-@.str110 = private unnamed_addr constant [9 x i8] c"DFG_SORT\00", align 1
-@.str111 = private unnamed_addr constant [10 x i8] c"DFG_SORTS\00", align 1
-@.str112 = private unnamed_addr constant [11 x i8] c"DFG_STATUS\00", align 1
-@.str113 = private unnamed_addr constant [9 x i8] c"DFG_STEP\00", align 1
-@.str114 = private unnamed_addr constant [12 x i8] c"DFG_SUBSORT\00", align 1
-@.str115 = private unnamed_addr constant [13 x i8] c"DFG_TERMLIST\00", align 1
-@.str116 = private unnamed_addr constant [9 x i8] c"DFG_TRUE\00", align 1
-@.str117 = private unnamed_addr constant [12 x i8] c"DFG_UNKNOWN\00", align 1
-@.str118 = private unnamed_addr constant [12 x i8] c"DFG_UNSATIS\00", align 1
-@.str119 = private unnamed_addr constant [12 x i8] c"DFG_VERSION\00", align 1
-@.str120 = private unnamed_addr constant [8 x i8] c"DFG_NUM\00", align 1
-@.str121 = private unnamed_addr constant [11 x i8] c"DFG_MINUS1\00", align 1
-@.str122 = private unnamed_addr constant [7 x i8] c"DFG_ID\00", align 1
-@.str123 = private unnamed_addr constant [9 x i8] c"DFG_TEXT\00", align 1
-@.str124 = private unnamed_addr constant [4 x i8] c"'('\00", align 1
-@.str125 = private unnamed_addr constant [4 x i8] c"')'\00", align 1
-@.str126 = private unnamed_addr constant [4 x i8] c"'.'\00", align 1
-@.str127 = private unnamed_addr constant [4 x i8] c"'['\00", align 1
-@.str128 = private unnamed_addr constant [4 x i8] c"']'\00", align 1
-@.str129 = private unnamed_addr constant [4 x i8] c"','\00", align 1
-@.str130 = private unnamed_addr constant [4 x i8] c"':'\00", align 1
-@.str131 = private unnamed_addr constant [8 x i8] c"$accept\00", align 1
-@.str132 = private unnamed_addr constant [8 x i8] c"problem\00", align 1
-@.str133 = private unnamed_addr constant [12 x i8] c"description\00", align 1
-@.str134 = private unnamed_addr constant [5 x i8] c"name\00", align 1
-@.str135 = private unnamed_addr constant [7 x i8] c"author\00", align 1
-@.str136 = private unnamed_addr constant [7 x i8] c"status\00", align 1
-@.str137 = private unnamed_addr constant [9 x i8] c"desctext\00", align 1
-@.str138 = private unnamed_addr constant [11 x i8] c"versionopt\00", align 1
-@.str139 = private unnamed_addr constant [9 x i8] c"logicopt\00", align 1
-@.str140 = private unnamed_addr constant [8 x i8] c"dateopt\00", align 1
-@.str141 = private unnamed_addr constant [10 x i8] c"log_state\00", align 1
-@.str142 = private unnamed_addr constant [12 x i8] c"logicalpart\00", align 1
-@.str143 = private unnamed_addr constant [14 x i8] c"symbollistopt\00", align 1
-@.str144 = private unnamed_addr constant [13 x i8] c"functionsopt\00", align 1
-@.str145 = private unnamed_addr constant [13 x i8] c"functionlist\00", align 1
-@.str146 = private unnamed_addr constant [5 x i8] c"func\00", align 1
-@.str147 = private unnamed_addr constant [14 x i8] c"predicatesopt\00", align 1
-@.str148 = private unnamed_addr constant [14 x i8] c"predicatelist\00", align 1
-@.str149 = private unnamed_addr constant [5 x i8] c"pred\00", align 1
-@.str150 = private unnamed_addr constant [9 x i8] c"sortsopt\00", align 1
-@.str151 = private unnamed_addr constant [9 x i8] c"sortlist\00", align 1
-@.str152 = private unnamed_addr constant [13 x i8] c"operatorsopt\00", align 1
-@.str153 = private unnamed_addr constant [13 x i8] c"operatorlist\00", align 1
-@.str154 = private unnamed_addr constant [3 x i8] c"op\00", align 1
-@.str155 = private unnamed_addr constant [15 x i8] c"quantifiersopt\00", align 1
-@.str156 = private unnamed_addr constant [15 x i8] c"quantifierlist\00", align 1
-@.str157 = private unnamed_addr constant [6 x i8] c"quant\00", align 1
-@.str158 = private unnamed_addr constant [7 x i8] c"number\00", align 1
-@.str159 = private unnamed_addr constant [19 x i8] c"declarationlistopt\00", align 1
-@.str160 = private unnamed_addr constant [12 x i8] c"decllistopt\00", align 1
-@.str161 = private unnamed_addr constant [5 x i8] c"decl\00", align 1
-@.str162 = private unnamed_addr constant [3 x i8] c"@1\00", align 1
-@.str163 = private unnamed_addr constant [3 x i8] c"@2\00", align 1
-@.str164 = private unnamed_addr constant [8 x i8] c"gendecl\00", align 1
-@.str165 = private unnamed_addr constant [10 x i8] c"freelyopt\00", align 1
-@.str166 = private unnamed_addr constant [9 x i8] c"funclist\00", align 1
-@.str167 = private unnamed_addr constant [9 x i8] c"sortdecl\00", align 1
-@.str168 = private unnamed_addr constant [12 x i8] c"formulalist\00", align 1
-@.str169 = private unnamed_addr constant [7 x i8] c"origin\00", align 1
-@.str170 = private unnamed_addr constant [16 x i8] c"formulalistsopt\00", align 1
-@.str171 = private unnamed_addr constant [15 x i8] c"formulalistopt\00", align 1
-@.str172 = private unnamed_addr constant [9 x i8] c"labelopt\00", align 1
-@.str173 = private unnamed_addr constant [8 x i8] c"formula\00", align 1
-@.str174 = private unnamed_addr constant [3 x i8] c"@3\00", align 1
-@.str175 = private unnamed_addr constant [3 x i8] c"@4\00", align 1
-@.str176 = private unnamed_addr constant [11 x i8] c"formulaopt\00", align 1
-@.str177 = private unnamed_addr constant [8 x i8] c"arglist\00", align 1
-@.str178 = private unnamed_addr constant [10 x i8] c"binsymbol\00", align 1
-@.str179 = private unnamed_addr constant [8 x i8] c"nsymbol\00", align 1
-@.str180 = private unnamed_addr constant [12 x i8] c"quantsymbol\00", align 1
-@.str181 = private unnamed_addr constant [3 x i8] c"id\00", align 1
-@.str182 = private unnamed_addr constant [10 x i8] c"qtermlist\00", align 1
-@.str183 = private unnamed_addr constant [6 x i8] c"qterm\00", align 1
-@.str184 = private unnamed_addr constant [15 x i8] c"clauselistsopt\00", align 1
-@.str185 = private unnamed_addr constant [11 x i8] c"clauselist\00", align 1
-@.str186 = private unnamed_addr constant [3 x i8] c"@5\00", align 1
-@.str187 = private unnamed_addr constant [14 x i8] c"cnfclausesopt\00", align 1
-@.str188 = private unnamed_addr constant [13 x i8] c"cnfclauseopt\00", align 1
-@.str189 = private unnamed_addr constant [10 x i8] c"cnfclause\00", align 1
-@.str190 = private unnamed_addr constant [3 x i8] c"@6\00", align 1
-@.str191 = private unnamed_addr constant [3 x i8] c"@7\00", align 1
-@.str192 = private unnamed_addr constant [14 x i8] c"cnfclausebody\00", align 1
-@.str193 = private unnamed_addr constant [8 x i8] c"litlist\00", align 1
-@.str194 = private unnamed_addr constant [4 x i8] c"lit\00", align 1
-@.str195 = private unnamed_addr constant [9 x i8] c"atomlist\00", align 1
-@.str196 = private unnamed_addr constant [5 x i8] c"atom\00", align 1
-@.str197 = private unnamed_addr constant [14 x i8] c"dnfclausesopt\00", align 1
-@.str198 = private unnamed_addr constant [13 x i8] c"dnfclauseopt\00", align 1
-@.str199 = private unnamed_addr constant [10 x i8] c"dnfclause\00", align 1
-@.str200 = private unnamed_addr constant [14 x i8] c"dnfclausebody\00", align 1
-@.str201 = private unnamed_addr constant [5 x i8] c"term\00", align 1
-@.str202 = private unnamed_addr constant [9 x i8] c"termlist\00", align 1
-@.str203 = private unnamed_addr constant [14 x i8] c"prooflistsopt\00", align 1
-@.str204 = private unnamed_addr constant [10 x i8] c"prooflist\00", align 1
-@.str205 = private unnamed_addr constant [3 x i8] c"@8\00", align 1
-@.str206 = private unnamed_addr constant [13 x i8] c"prooflistopt\00", align 1
-@.str207 = private unnamed_addr constant [11 x i8] c"parentlist\00", align 1
-@.str208 = private unnamed_addr constant [13 x i8] c"assoclistopt\00", align 1
-@.str209 = private unnamed_addr constant [10 x i8] c"assoclist\00", align 1
-@.str210 = private unnamed_addr constant [14 x i8] c"id_or_formula\00", align 1
-@.str211 = private unnamed_addr constant [3 x i8] c"@9\00", align 1
-@.str212 = private unnamed_addr constant [10 x i8] c"anysymbol\00", align 1
-@.str213 = private unnamed_addr constant [8 x i8] c"optargs\00", align 1
-@.str214 = private unnamed_addr constant [7 x i8] c"clause\00", align 1
-@.str215 = private unnamed_addr constant [15 x i8] c"listOfTermsopt\00", align 1
-@.str216 = private unnamed_addr constant [12 x i8] c"listOfTerms\00", align 1
-@.str217 = private unnamed_addr constant [4 x i8] c"@10\00", align 1
-@.str218 = private unnamed_addr constant [6 x i8] c"terms\00", align 1
-@.str219 = private unnamed_addr constant [16 x i8] c"settinglistsopt\00", align 1
-@.str220 = private unnamed_addr constant [12 x i8] c"settinglist\00", align 1
-@.str221 = private unnamed_addr constant [4 x i8] c"@11\00", align 1
-@.str222 = private unnamed_addr constant [6 x i8] c"flags\00", align 1
-@.str223 = private unnamed_addr constant [11 x i8] c"spassflags\00", align 1
-@.str224 = private unnamed_addr constant [10 x i8] c"spassflag\00", align 1
-@.str225 = private unnamed_addr constant [9 x i8] c"preclist\00", align 1
-@.str226 = private unnamed_addr constant [9 x i8] c"precitem\00", align 1
-@.str227 = private unnamed_addr constant [8 x i8] c"statopt\00", align 1
-@.str228 = private unnamed_addr constant [10 x i8] c"gsettings\00", align 1
-@.str229 = private unnamed_addr constant [9 x i8] c"gsetting\00", align 1
-@.str230 = private unnamed_addr constant [10 x i8] c"labellist\00", align 1
-@.str231 = private unnamed_addr constant [50 x i8] c"\0A Error: Flag value %d is too small for flag %s.\0A\00", align 1
-@.str232 = private unnamed_addr constant [50 x i8] c"\0A Error: Flag value %d is too large for flag %s.\0A\00", align 1
-@.str233 = private unnamed_addr constant [31 x i8] c"\0A Line %d: is not a function.\0A\00", align 1
-@fol_EQUALITY = external global i32
-@stack_STACK = external global [10000 x i8*]
-@fol_EXIST = external global i32
-@fol_OR = external global i32
-@fol_AND = external global i32
-@fol_IMPLIES = external global i32
-@fol_IMPLIED = external global i32
-@fol_EQUIV = external global i32
-@fol_NOT = external global i32
-@fol_ALL = external global i32
+%struct.StorablePicture = type { i32, i32, i32, i32 }
 
-; Function Attrs: nounwind
-define i32 @dfg_parse() #0 {
-entry:
-  %yyssa = alloca [200 x i16], align 2
-  %yyvsa = alloca [200 x %union.yystype], align 4
-  %yyval = alloca %union.yystype, align 4
-  %0 = bitcast [200 x i16]* %yyssa to i8*
-  call void @llvm.lifetime.start(i64 400, i8* %0) #1
-  %arraydecay = getelementptr inbounds [200 x i16]* %yyssa, i32 0, i32 0
-  %1 = bitcast [200 x %union.yystype]* %yyvsa to i8*
-  call void @llvm.lifetime.start(i64 800, i8* %1) #1
-  %arraydecay1 = getelementptr inbounds [200 x %union.yystype]* %yyvsa, i32 0, i32 0
-  store i32 0, i32* @dfg_nerrs, align 4
-  store i32 -2, i32* @dfg_char, align 4
-  %2 = getelementptr inbounds %union.yystype* %yyval, i32 0, i32 0
-  %3 = load i32* @symbol_TYPEMASK, align 4
-  %4 = load i32* @symbol_TYPESTATBITS, align 4
-  br label %yysetstate
-
-yynewstate:                                       ; preds = %if.then1223, %if.else1226, %if.end100
-  %yyvsp.0 = phi %union.yystype* [ %incdec.ptr1204, %if.then1223 ], [ %incdec.ptr1204, %if.else1226 ], [ %incdec.ptr101, %if.end100 ]
-  %yyssp.0 = phi i16* [ %add.ptr1203, %if.then1223 ], [ %add.ptr1203, %if.else1226 ], [ %yyssp.2, %if.end100 ]
-  %yystate.0 = phi i32 [ %conv1225, %if.then1223 ], [ %conv1229, %if.else1226 ], [ %conv81, %if.end100 ]
-  %incdec.ptr = getelementptr inbounds i16* %yyssp.0, i32 1
-  br label %yysetstate
-
-yysetstate:                                       ; preds = %yynewstate, %entry
-  %yystacksize.0 = phi i32 [ 200, %entry ], [ %yystacksize.1, %yynewstate ]
-  %yyvsp.1 = phi %union.yystype* [ %arraydecay1, %entry ], [ %yyvsp.0, %yynewstate ]
-  %yyvs.0 = phi %union.yystype* [ %arraydecay1, %entry ], [ %yyvs.1, %yynewstate ]
-  %yyssp.1 = phi i16* [ %arraydecay, %entry ], [ %incdec.ptr, %yynewstate ]
-  %yyss.0 = phi i16* [ %arraydecay, %entry ], [ %yyss.1, %yynewstate ]
-  %yystate.1 = phi i32 [ 0, %entry ], [ %yystate.0, %yynewstate ]
-  %conv = trunc i32 %yystate.1 to i16
-  store i16 %conv, i16* %yyssp.1, align 2
-  %add.ptr.sum = add i32 %yystacksize.0, -1
-  %add.ptr2 = getelementptr inbounds i16* %yyss.0, i32 %add.ptr.sum
-  %cmp = icmp ult i16* %yyssp.1, %add.ptr2
-  br i1 %cmp, label %yybackup, label %if.then
-
-if.then:                                          ; preds = %yysetstate
-  %sub.ptr.lhs.cast = ptrtoint i16* %yyssp.1 to i32
-  %sub.ptr.rhs.cast = ptrtoint i16* %yyss.0 to i32
-  %sub.ptr.sub = sub i32 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast
-  %sub.ptr.div = ashr exact i32 %sub.ptr.sub, 1
-  %add = add nsw i32 %sub.ptr.div, 1
-  %cmp4 = icmp ugt i32 %yystacksize.0, 9999
-  br i1 %cmp4, label %yyoverflowlab, label %if.end
-
-if.end:                                           ; preds = %if.then
-  %mul = shl i32 %yystacksize.0, 1
-  %cmp7 = icmp ugt i32 %mul, 10000
-  %.mul = select i1 %cmp7, i32 10000, i32 %mul
-  %mul11 = mul i32 %.mul, 6
-  %add121756 = or i32 %mul11, 3
-  %5 = alloca i8, i32 %add121756, align 4
-  %6 = bitcast i8* %5 to %union.yyalloc*
-  %yyss15 = bitcast i8* %5 to i16*
-  %7 = bitcast i16* %yyss.0 to i8*
-  %mul16 = shl i32 %add, 1
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %5, i8* %7, i32 %mul16, i32 2, i1 false)
-  %8 = lshr exact i32 %.mul, 1
-  %div = and i32 %8, 1073741823
-  %yyvs23 = getelementptr inbounds %union.yyalloc* %6, i32 %div, i32 0
-  %9 = bitcast %union.yystype* %yyvs23 to i8*
-  %10 = bitcast %union.yystype* %yyvs.0 to i8*
-  %mul24 = shl i32 %add, 2
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %9, i8* %10, i32 %mul24, i32 4, i1 false)
-  %add.ptr41 = getelementptr inbounds i16* %yyss15, i32 %sub.ptr.div
-  %add.ptr43 = getelementptr inbounds %union.yystype* %yyvs23, i32 %sub.ptr.div
-  %add.ptr44.sum = add i32 %.mul, -1
-  %cmp46 = icmp slt i32 %sub.ptr.div, %add.ptr44.sum
-  br i1 %cmp46, label %yybackup, label %yyreturn
-
-yybackup:                                         ; preds = %if.end, %yysetstate
-  %yystacksize.1 = phi i32 [ %.mul, %if.end ], [ %yystacksize.0, %yysetstate ]
-  %yyvsp.2 = phi %union.yystype* [ %add.ptr43, %if.end ], [ %yyvsp.1, %yysetstate ]
-  %yyvs.1 = phi %union.yystype* [ %yyvs23, %if.end ], [ %yyvs.0, %yysetstate ]
-  %yyssp.2 = phi i16* [ %add.ptr41, %if.end ], [ %yyssp.1, %yysetstate ]
-  %yyss.1 = phi i16* [ %yyss15, %if.end ], [ %yyss.0, %yysetstate ]
-  %arrayidx = getelementptr inbounds [477 x i16]* @yypact, i32 0, i32 %yystate.1
-  %11 = load i16* %arrayidx, align 2
-  %conv51 = sext i16 %11 to i32
-  %cmp52 = icmp eq i16 %11, -356
-  br i1 %cmp52, label %yydefault, label %if.end55
-
-if.end55:                                         ; preds = %yybackup
-  %12 = load i32* @dfg_char, align 4
-  %cmp56 = icmp eq i32 %12, -2
-  br i1 %cmp56, label %if.then58, label %if.end59
-
-if.then58:                                        ; preds = %if.end55
-  %call = call i32 @dfg_lex() #1
-  store i32 %call, i32* @dfg_char, align 4
-  br label %if.end59
-
-if.end59:                                         ; preds = %if.then58, %if.end55
-  %13 = phi i32 [ %call, %if.then58 ], [ %12, %if.end55 ]
-  %cmp60 = icmp slt i32 %13, 1
-  br i1 %cmp60, label %if.then62, label %if.else
-
-if.then62:                                        ; preds = %if.end59
-  store i32 0, i32* @dfg_char, align 4
-  br label %if.end67
-
-if.else:                                          ; preds = %if.end59
-  %cmp63 = icmp ult i32 %13, 319
-  br i1 %cmp63, label %cond.true, label %if.end67
-
-cond.true:                                        ; preds = %if.else
-  %arrayidx65 = getelementptr inbounds [319 x i8]* @yytranslate, i32 0, i32 %13
-  %14 = load i8* %arrayidx65, align 1
-  %conv66 = zext i8 %14 to i32
-  br label %if.end67
-
-if.end67:                                         ; preds = %cond.true, %if.else, %if.then62
-  %15 = phi i32 [ 0, %if.then62 ], [ %13, %cond.true ], [ %13, %if.else ]
-  %yychar1.2 = phi i32 [ 0, %if.then62 ], [ %conv66, %cond.true ], [ 2, %if.else ]
-  %add68 = add nsw i32 %yychar1.2, %conv51
-  %16 = icmp ugt i32 %add68, 506
-  br i1 %16, label %yydefault, label %lor.lhs.false73
-
-lor.lhs.false73:                                  ; preds = %if.end67
-  %arrayidx74 = getelementptr inbounds [507 x i16]* @yycheck, i32 0, i32 %add68
-  %17 = load i16* %arrayidx74, align 2
-  %conv75 = sext i16 %17 to i32
-  %cmp76 = icmp eq i32 %conv75, %yychar1.2
-  br i1 %cmp76, label %if.end79, label %yydefault
-
-if.end79:                                         ; preds = %lor.lhs.false73
-  %arrayidx80 = getelementptr inbounds [507 x i16]* @yytable, i32 0, i32 %add68
-  %18 = load i16* %arrayidx80, align 2
-  %conv81 = zext i16 %18 to i32
-  %cmp82 = icmp eq i16 %18, 0
-  br i1 %cmp82, label %if.then1232, label %if.end92
-
-if.end92:                                         ; preds = %if.end79
-  %cmp93 = icmp eq i32 %add68, 35
-  br i1 %cmp93, label %yyreturn, label %if.end96
-
-if.end96:                                         ; preds = %if.end92
-  %cmp97 = icmp eq i32 %15, 0
-  br i1 %cmp97, label %if.end100, label %if.then99
-
-if.then99:                                        ; preds = %if.end96
-  store i32 -2, i32* @dfg_char, align 4
-  br label %if.end100
-
-if.end100:                                        ; preds = %if.end96, %if.then99
-  %incdec.ptr101 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 1
-  %19 = load i32* getelementptr inbounds (%union.yystype* @dfg_lval, i32 0, i32 0), align 4
-  %20 = getelementptr inbounds %union.yystype* %incdec.ptr101, i32 0, i32 0
-  store i32 %19, i32* %20, align 4
-  br label %yynewstate
-
-yydefault:                                        ; preds = %lor.lhs.false73, %if.end67, %yybackup
-  %arrayidx105 = getelementptr inbounds [477 x i8]* @yydefact, i32 0, i32 %yystate.1
-  %21 = load i8* %arrayidx105, align 1
-  %conv106 = zext i8 %21 to i32
-  %cmp107 = icmp eq i8 %21, 0
-  br i1 %cmp107, label %if.then1232, label %yyreduce
-
-yyreduce:                                         ; preds = %yydefault
-  %arrayidx111 = getelementptr inbounds [197 x i8]* @yyr2, i32 0, i32 %conv106
-  %22 = load i8* %arrayidx111, align 1
-  %conv112 = zext i8 %22 to i32
-  %sub113 = sub i32 1, %conv112
-  %23 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 %sub113, i32 0
-  %24 = load i32* %23, align 4
-  store i32 %24, i32* %2, align 4
-  switch i32 %conv106, label %sw.epilog1200 [
-    i32 2, label %sw.bb
-    i32 4, label %sw.bb116
-    i32 5, label %sw.bb119
-    i32 6, label %sw.bb122
-    i32 7, label %sw.bb124
-    i32 9, label %sw.bb127
-    i32 11, label %sw.bb130
-    i32 13, label %sw.bb133
-    i32 14, label %sw.bb136
-    i32 15, label %sw.bb138
-    i32 16, label %sw.bb140
-    i32 24, label %sw.bb142
-    i32 25, label %sw.bb145
-    i32 30, label %sw.bb149
-    i32 31, label %sw.bb152
-    i32 34, label %sw.bb157
-    i32 35, label %sw.bb160
-    i32 40, label %sw.bb163
-    i32 41, label %sw.bb166
-    i32 46, label %sw.bb171
-    i32 47, label %sw.bb174
-    i32 48, label %sw.bb179
-    i32 49, label %sw.bb181
-    i32 55, label %sw.bb185
-    i32 56, label %sw.bb190
-    i32 57, label %sw.bb195
-    i32 58, label %sw.bb198
-    i32 59, label %sw.bb199
-    i32 60, label %sw.bb200
-    i32 61, label %sw.bb210
-    i32 62, label %sw.bb217
-    i32 63, label %sw.bb219
-    i32 64, label %sw.bb221
-    i32 65, label %sw.bb226
-    i32 66, label %sw.bb233
-    i32 67, label %sw.bb236
-    i32 68, label %sw.bb239
-    i32 69, label %sw.bb255
-    i32 70, label %sw.bb257
-    i32 73, label %sw.bb259
-    i32 74, label %sw.bb262
-    i32 75, label %sw.bb290
-    i32 76, label %sw.bb292
-    i32 77, label %sw.bb296
-    i32 78, label %sw.bb300
-    i32 79, label %sw.bb312
-    i32 80, label %sw.bb327
-    i32 81, label %sw.bb339
-    i32 82, label %sw.bb340
-    i32 83, label %sw.bb341
-    i32 84, label %sw.bb355
-    i32 85, label %sw.bb357
-    i32 86, label %sw.bb361
-    i32 87, label %sw.bb372
-    i32 88, label %sw.bb387
-    i32 89, label %sw.bb390
-    i32 90, label %sw.bb393
-    i32 91, label %sw.bb396
-    i32 92, label %sw.bb399
-    i32 93, label %sw.bb402
-    i32 94, label %sw.bb405
-    i32 95, label %sw.bb408
-    i32 96, label %sw.bb419
-    i32 97, label %sw.bb429
-    i32 98, label %sw.bb437
-    i32 99, label %sw.bb445
-    i32 100, label %sw.bb453
-    i32 101, label %sw.bb464
-    i32 102, label %sw.bb479
-    i32 103, label %sw.bb494
-    i32 106, label %sw.bb519
-    i32 107, label %sw.bb535
-    i32 108, label %sw.bb536
-    i32 109, label %sw.bb538
-    i32 110, label %sw.bb541
-    i32 111, label %sw.bb570
-    i32 112, label %sw.bb572
-    i32 113, label %sw.bb576
-    i32 114, label %sw.bb580
-    i32 115, label %sw.bb581
-    i32 116, label %sw.bb582
-    i32 117, label %sw.bb595
-    i32 118, label %sw.bb606
-    i32 119, label %sw.bb617
-    i32 120, label %sw.bb632
-    i32 121, label %sw.bb636
-    i32 122, label %sw.bb650
-    i32 123, label %sw.bb655
-    i32 124, label %sw.bb663
-    i32 125, label %sw.bb674
-    i32 126, label %sw.bb684
-    i32 127, label %sw.bb694
-    i32 128, label %sw.bb709
-    i32 136, label %sw.bb721
-    i32 137, label %sw.bb732
-    i32 138, label %sw.bb744
-    i32 139, label %sw.bb755
-    i32 142, label %sw.bb770
-    i32 143, label %sw.bb777
-    i32 145, label %sw.bb787
-    i32 146, label %sw.bb851
-    i32 147, label %sw.bb867
-    i32 148, label %sw.bb887
-    i32 149, label %sw.bb889
-    i32 150, label %sw.bb893
-    i32 151, label %sw.bb934
-    i32 152, label %sw.bb977
-    i32 153, label %sw.bb978
-    i32 154, label %sw.bb998
-    i32 155, label %sw.bb1002
-    i32 156, label %sw.bb1004
-    i32 157, label %sw.bb1006
-    i32 158, label %sw.bb1008
-    i32 159, label %sw.bb1010
-    i32 160, label %sw.bb1012
-    i32 161, label %sw.bb1014
-    i32 162, label %sw.bb1016
-    i32 163, label %sw.bb1018
-    i32 164, label %sw.bb1020
-    i32 165, label %sw.bb1022
-    i32 166, label %sw.bb1024
-    i32 167, label %sw.bb1028
-    i32 170, label %sw.bb1030
-    i32 171, label %sw.bb1031
-    i32 173, label %sw.bb1032
-    i32 177, label %sw.bb1037
-    i32 178, label %sw.bb1046
-    i32 179, label %sw.bb1047
-    i32 184, label %for.cond.preheader
-    i32 185, label %sw.bb1084
-    i32 188, label %sw.bb1099
-    i32 189, label %sw.bb1114
-    i32 190, label %sw.bb1138
-    i32 191, label %sw.bb1140
-    i32 194, label %sw.bb1184
-    i32 195, label %sw.bb1187
-    i32 196, label %sw.bb1192
-  ]
-
-for.cond.preheader:                               ; preds = %yyreduce
-  %arrayidx1052 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1
-  %list1053 = bitcast %union.yystype* %arrayidx1052 to %struct.LIST_HELP**
-  %25 = load %struct.LIST_HELP** %list1053, align 4
-  %cmp.i21612226 = icmp eq %struct.LIST_HELP* %25, null
-  br i1 %cmp.i21612226, label %sw.epilog1200, label %for.body.lr.ph
-
-for.body.lr.ph:                                   ; preds = %for.cond.preheader
-  %26 = getelementptr inbounds %union.yystype* %arrayidx1052, i32 0, i32 0
-  br label %for.body
-
-sw.bb:                                            ; preds = %yyreduce
-  %arrayidx115 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -7
-  %string = bitcast %union.yystype* %arrayidx115 to i8**
-  %27 = load i8** %string, align 4
-  call void @string_StringFree(i8* %27) #1
-  br label %yyreturn
-
-sw.bb116:
-  %arrayidx117 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %string118 = bitcast %union.yystype* %arrayidx117 to i8**
-  %28 = load i8** %string118, align 4
-  store i8* %28, i8** @dfg_DESC.0, align 4
-  br label %sw.epilog1200
-
-sw.bb119:                                         ; preds = %yyreduce
-  %arrayidx120 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %string121 = bitcast %union.yystype* %arrayidx120 to i8**
-  %29 = load i8** %string121, align 4
-  store i8* %29, i8** @dfg_DESC.1, align 4
-  br label %sw.epilog1200
-
-sw.bb122:                                         ; preds = %yyreduce
-  %state = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2, i32 0
-  %30 = load i32* %state, align 4
-  store i32 %30, i32* @dfg_DESC.4, align 4
-  br label %sw.epilog1200
-
-sw.bb124:                                         ; preds = %yyreduce
-  %arrayidx125 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %string126 = bitcast %union.yystype* %arrayidx125 to i8**
-  %31 = load i8** %string126, align 4
-  store i8* %31, i8** @dfg_DESC.5, align 4
-  br label %sw.epilog1200
-
-sw.bb127:                                         ; preds = %yyreduce
-  %arrayidx128 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %string129 = bitcast %union.yystype* %arrayidx128 to i8**
-  %32 = load i8** %string129, align 4
-  store i8* %32, i8** @dfg_DESC.2, align 4
-  br label %sw.epilog1200
-
-sw.bb130:                                         ; preds = %yyreduce
-  %arrayidx131 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %string132 = bitcast %union.yystype* %arrayidx131 to i8**
-  %33 = load i8** %string132, align 4
-  store i8* %33, i8** @dfg_DESC.3, align 4
-  br label %sw.epilog1200
-
-sw.bb133:                                         ; preds = %yyreduce
-  %arrayidx134 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %string135 = bitcast %union.yystype* %arrayidx134 to i8**
-  %34 = load i8** %string135, align 4
-  store i8* %34, i8** @dfg_DESC.6, align 4
-  br label %sw.epilog1200
-
-sw.bb136:                                         ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb138:                                         ; preds = %yyreduce
-  store i32 1, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb140:                                         ; preds = %yyreduce
-  store i32 2, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb142:                                         ; preds = %yyreduce
-  %string144 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %35 = load i8** %string144, align 4
-  call fastcc void @dfg_SymbolDecl(i32 284, i8* %35, i32 -2)
-  br label %sw.epilog1200
-
-sw.bb145:                                         ; preds = %yyreduce
-  %arrayidx146 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -3
-  %string147 = bitcast %union.yystype* %arrayidx146 to i8**
-  %36 = load i8** %string147, align 4
-  %number = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1, i32 0
-  %37 = load i32* %number, align 4
-  call fastcc void @dfg_SymbolDecl(i32 284, i8* %36, i32 %37)
-  br label %sw.epilog1200
-
-sw.bb149:                                         ; preds = %yyreduce
-  %string151 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %38 = load i8** %string151, align 4
-  call fastcc void @dfg_SymbolDecl(i32 298, i8* %38, i32 -2)
-  br label %sw.epilog1200
-
-sw.bb152:                                         ; preds = %yyreduce
-  %arrayidx153 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -3
-  %string154 = bitcast %union.yystype* %arrayidx153 to i8**
-  %39 = load i8** %string154, align 4
-  %number156 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1, i32 0
-  %40 = load i32* %number156, align 4
-  call fastcc void @dfg_SymbolDecl(i32 298, i8* %39, i32 %40)
-  br label %sw.epilog1200
-
-sw.bb157:                                         ; preds = %yyreduce
-  %string159 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %41 = load i8** %string159, align 4
-  call fastcc void @dfg_SymbolDecl(i32 298, i8* %41, i32 1)
-  br label %sw.epilog1200
-
-sw.bb160:                                         ; preds = %yyreduce
-  %string162 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %42 = load i8** %string162, align 4
-  call fastcc void @dfg_SymbolDecl(i32 298, i8* %42, i32 1)
-  br label %sw.epilog1200
-
-sw.bb163:                                         ; preds = %yyreduce
-  %string165 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %43 = load i8** %string165, align 4
-  call fastcc void @dfg_SymbolDecl(i32 294, i8* %43, i32 -2)
-  br label %sw.epilog1200
-
-sw.bb166:                                         ; preds = %yyreduce
-  %arrayidx167 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -3
-  %string168 = bitcast %union.yystype* %arrayidx167 to i8**
-  %44 = load i8** %string168, align 4
-  %number170 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1, i32 0
-  %45 = load i32* %number170, align 4
-  call fastcc void @dfg_SymbolDecl(i32 294, i8* %44, i32 %45)
-  br label %sw.epilog1200
-
-sw.bb171:                                         ; preds = %yyreduce
-  %string173 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %46 = load i8** %string173, align 4
-  call fastcc void @dfg_SymbolDecl(i32 300, i8* %46, i32 -2)
-  br label %sw.epilog1200
-
-sw.bb174:                                         ; preds = %yyreduce
-  %arrayidx175 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -3
-  %string176 = bitcast %union.yystype* %arrayidx175 to i8**
-  %47 = load i8** %string176, align 4
-  %number178 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1, i32 0
-  %48 = load i32* %number178, align 4
-  call fastcc void @dfg_SymbolDecl(i32 300, i8* %47, i32 %48)
-  br label %sw.epilog1200
-
-sw.bb179:                                         ; preds = %yyreduce
-  store i32 -1, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb181:                                         ; preds = %yyreduce
-  %number183 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 0, i32 0
-  %49 = load i32* %number183, align 4
-  store i32 %49, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb185:                                         ; preds = %yyreduce
-  %arrayidx186 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -4
-  %string187 = bitcast %union.yystype* %arrayidx186 to i8**
-  %50 = load i8** %string187, align 4
-  %arrayidx188 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %string189 = bitcast %union.yystype* %arrayidx188 to i8**
-  %51 = load i8** %string189, align 4
-  %call.i = call fastcc i32 @dfg_Symbol(i8* %50, i32 1) #1
-  %call1.i = call fastcc i32 @dfg_Symbol(i8* %51, i32 1) #1
-  %tobool.i.i = icmp sgt i32 %call.i, -1
-  br i1 %tobool.i.i, label %if.then.i, label %land.rhs.i.i
-
-land.rhs.i.i:                                     ; preds = %sw.bb185
-  %sub.i.i.i = sub nsw i32 0, %call.i
-  %and.i.i.i = and i32 %3, %sub.i.i.i
-  %cmp.i.i = icmp eq i32 %and.i.i.i, 2
-  br i1 %cmp.i.i, label %if.end.i, label %if.then.i
-
-if.then.i:                                        ; preds = %land.rhs.i.i, %sw.bb185
-  %52 = load %struct._IO_FILE** @stdout, align 4
-  %call3.i = call i32 @fflush(%struct._IO_FILE* %52) #1
-  %53 = load i32* @dfg_LINENUMBER, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([44 x i8]* @.str42, i32 0, i32 0), i32 %53) #1
-  call fastcc void @misc_Error() #1
-  unreachable
-
-if.end.i:                                         ; preds = %land.rhs.i.i
-  %tobool.i34.i = icmp sgt i32 %call1.i, -1
-  br i1 %tobool.i34.i, label %if.then6.i, label %land.rhs.i38.i
-
-land.rhs.i38.i:                                   ; preds = %if.end.i
-  %sub.i.i35.i = sub nsw i32 0, %call1.i
-  %and.i.i36.i = and i32 %3, %sub.i.i35.i
-  %cmp.i37.i = icmp eq i32 %and.i.i36.i, 2
-  br i1 %cmp.i37.i, label %if.end8.i, label %if.then6.i
-
-if.then6.i:                                       ; preds = %land.rhs.i38.i, %if.end.i
-  %54 = load %struct._IO_FILE** @stdout, align 4
-  %call7.i = call i32 @fflush(%struct._IO_FILE* %54) #1
-  %55 = load i32* @dfg_LINENUMBER, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([44 x i8]* @.str42, i32 0, i32 0), i32 %55) #1
-  call fastcc void @misc_Error() #1
-  unreachable
-
-if.end8.i:                                        ; preds = %land.rhs.i38.i
-  %56 = load i32* @symbol_STANDARDVARCOUNTER, align 4
-  %inc.i.i = add nsw i32 %56, 1
-  store i32 %inc.i.i, i32* @symbol_STANDARDVARCOUNTER, align 4
-  %call11.i = call %struct.term* @term_Create(i32 %inc.i.i, %struct.LIST_HELP* null) #1
-  store i32 0, i32* @symbol_STANDARDVARCOUNTER, align 4
-  %57 = bitcast %struct.term* %call11.i to i8*
-  %call.i.i50.i = call i8* @memory_Malloc(i32 8) #1
-  %58 = bitcast i8* %call.i.i50.i to %struct.LIST_HELP*
-  %car.i.i51.i = getelementptr inbounds i8* %call.i.i50.i, i32 4
-  %59 = bitcast i8* %car.i.i51.i to i8**
-  store i8* %57, i8** %59, align 4
-  %cdr.i.i52.i = bitcast i8* %call.i.i50.i to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i52.i, align 4
-  %call13.i = call %struct.term* @term_Create(i32 %call.i, %struct.LIST_HELP* %58) #1
-  %call14.i = call %struct.term* @term_Copy(%struct.term* %call11.i) #1
-  %60 = bitcast %struct.term* %call14.i to i8*
-  %call.i.i53.i = call i8* @memory_Malloc(i32 8) #1
-  %61 = bitcast i8* %call.i.i53.i to %struct.LIST_HELP*
-  %car.i.i54.i = getelementptr inbounds i8* %call.i.i53.i, i32 4
-  %62 = bitcast i8* %car.i.i54.i to i8**
-  store i8* %60, i8** %62, align 4
-  %cdr.i.i55.i = bitcast i8* %call.i.i53.i to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i55.i, align 4
-  %call16.i = call %struct.term* @term_Create(i32 %call1.i, %struct.LIST_HELP* %61) #1
-  %63 = load i32* @fol_IMPLIES, align 4
-  %64 = bitcast %struct.term* %call13.i to i8*
-  %65 = bitcast %struct.term* %call16.i to i8*
-  %call.i.i56.i = call i8* @memory_Malloc(i32 8) #1
-  %66 = bitcast i8* %call.i.i56.i to %struct.LIST_HELP*
-  %car.i.i57.i = getelementptr inbounds i8* %call.i.i56.i, i32 4
-  %67 = bitcast i8* %car.i.i57.i to i8**
-  store i8* %65, i8** %67, align 4
-  %cdr.i.i58.i = bitcast i8* %call.i.i56.i to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i58.i, align 4
-  %call.i.i = call i8* @memory_Malloc(i32 8) #1
-  %68 = bitcast i8* %call.i.i to %struct.LIST_HELP*
-  %car.i.i = getelementptr inbounds i8* %call.i.i, i32 4
-  %69 = bitcast i8* %car.i.i to i8**
-  store i8* %64, i8** %69, align 4
-  %cdr.i.i = bitcast i8* %call.i.i to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %66, %struct.LIST_HELP** %cdr.i.i, align 4
-  %call20.i = call %struct.term* @term_Create(i32 %63, %struct.LIST_HELP* %68) #1
-  %70 = load i32* @fol_ALL, align 4
-  %call22.i = call %struct.term* @term_Copy(%struct.term* %call11.i) #1
-  %71 = bitcast %struct.term* %call22.i to i8*
-  %call.i.i47.i = call i8* @memory_Malloc(i32 8) #1
-  %72 = bitcast i8* %call.i.i47.i to %struct.LIST_HELP*
-  %car.i.i48.i = getelementptr inbounds i8* %call.i.i47.i, i32 4
-  %73 = bitcast i8* %car.i.i48.i to i8**
-  store i8* %71, i8** %73, align 4
-  %cdr.i.i49.i = bitcast i8* %call.i.i47.i to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i49.i, align 4
-  %74 = bitcast %struct.term* %call20.i to i8*
-  %call.i.i44.i = call i8* @memory_Malloc(i32 8) #1
-  %75 = bitcast i8* %call.i.i44.i to %struct.LIST_HELP*
-  %car.i.i45.i = getelementptr inbounds i8* %call.i.i44.i, i32 4
-  %76 = bitcast i8* %car.i.i45.i to i8**
-  store i8* %74, i8** %76, align 4
-  %cdr.i.i46.i = bitcast i8* %call.i.i44.i to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i46.i, align 4
-  %call25.i = call %struct.term* @fol_CreateQuantifier(i32 %70, %struct.LIST_HELP* %72, %struct.LIST_HELP* %75) #1
-  %77 = load %struct.LIST_HELP** @dfg_SORTDECLLIST, align 4
-  %78 = bitcast %struct.term* %call25.i to %struct.LIST_HELP*
-  %call.i.i41.i = call i8* @memory_Malloc(i32 8) #1
-  %car.i.i42.i = getelementptr inbounds i8* %call.i.i41.i, i32 4
-  %79 = bitcast i8* %car.i.i42.i to i8**
-  store i8* null, i8** %79, align 4
-  %cdr.i.i43.i = bitcast i8* %call.i.i41.i to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %78, %struct.LIST_HELP** %cdr.i.i43.i, align 4
-  %call.i.i.i = call i8* @memory_Malloc(i32 8) #1
-  %80 = bitcast i8* %call.i.i.i to %struct.LIST_HELP*
-  %car.i.i.i = getelementptr inbounds i8* %call.i.i.i, i32 4
-  %81 = bitcast i8* %car.i.i.i to i8**
-  store i8* %call.i.i41.i, i8** %81, align 4
-  %cdr.i.i.i = bitcast i8* %call.i.i.i to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i.i, align 4
-  %cmp.i.i.i = icmp eq %struct.LIST_HELP* %77, null
-  br i1 %cmp.i.i.i, label %dfg_SubSort.exit, label %if.end.i.i
-
-if.end.i.i:                                       ; preds = %if.end8.i
-  %cmp.i18.i.i = icmp eq i8* %call.i.i.i, null
-  br i1 %cmp.i18.i.i, label %dfg_SubSort.exit, label %for.cond.i.i
-
-for.cond.i.i:                                     ; preds = %if.end.i.i, %for.cond.i.i
-  %List1.addr.0.i.i = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i.i, %for.cond.i.i ], [ %77, %if.end.i.i ]
-  %List1.addr.0.idx15.i.i = getelementptr %struct.LIST_HELP* %List1.addr.0.i.i, i32 0, i32 0
-  %List1.addr.0.idx15.val.i.i = load %struct.LIST_HELP** %List1.addr.0.idx15.i.i, align 4
-  %cmp.i16.i.i = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i.i, null
-  br i1 %cmp.i16.i.i, label %for.end.i.i, label %for.cond.i.i
-
-for.end.i.i:                                      ; preds = %for.cond.i.i
-  store %struct.LIST_HELP* %80, %struct.LIST_HELP** %List1.addr.0.idx15.i.i, align 4
-  br label %dfg_SubSort.exit
-
-dfg_SubSort.exit:                                 ; preds = %if.end8.i, %if.end.i.i, %for.end.i.i
-  %retval.0.i.i = phi %struct.LIST_HELP* [ %77, %for.end.i.i ], [ %80, %if.end8.i ], [ %77, %if.end.i.i ]
-  store %struct.LIST_HELP* %retval.0.i.i, %struct.LIST_HELP** @dfg_SORTDECLLIST, align 4
-  br label %sw.epilog1200
-
-sw.bb190:                                         ; preds = %yyreduce
-  %82 = load %struct.LIST_HELP** @dfg_SORTDECLLIST, align 4
-  %arrayidx191 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1
-  %term = bitcast %union.yystype* %arrayidx191 to %struct.term**
-  %83 = load %struct.term** %term, align 4
-  %84 = bitcast %struct.term* %83 to %struct.LIST_HELP*
-  %call.i.i1761 = call i8* @memory_Malloc(i32 8) #1
-  %car.i.i1762 = getelementptr inbounds i8* %call.i.i1761, i32 4
-  %85 = bitcast i8* %car.i.i1762 to i8**
-  store i8* null, i8** %85, align 4
-  %cdr.i.i1763 = bitcast i8* %call.i.i1761 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %84, %struct.LIST_HELP** %cdr.i.i1763, align 4
-  %call.i.i1764 = call i8* @memory_Malloc(i32 8) #1
-  %86 = bitcast i8* %call.i.i1764 to %struct.LIST_HELP*
-  %car.i.i1765 = getelementptr inbounds i8* %call.i.i1764, i32 4
-  %87 = bitcast i8* %car.i.i1765 to i8**
-  store i8* %call.i.i1761, i8** %87, align 4
-  %cdr.i.i1766 = bitcast i8* %call.i.i1764 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i1766, align 4
-  %cmp.i.i1767 = icmp eq %struct.LIST_HELP* %82, null
-  br i1 %cmp.i.i1767, label %list_Nconc.exit, label %if.end.i1768
-
-if.end.i1768:                                     ; preds = %sw.bb190
-  %cmp.i18.i = icmp eq i8* %call.i.i1764, null
-  br i1 %cmp.i18.i, label %list_Nconc.exit, label %for.cond.i
-
-for.cond.i:                                       ; preds = %if.end.i1768, %for.cond.i
-  %List1.addr.0.i = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i, %for.cond.i ], [ %82, %if.end.i1768 ]
-  %List1.addr.0.idx15.i = getelementptr %struct.LIST_HELP* %List1.addr.0.i, i32 0, i32 0
-  %List1.addr.0.idx15.val.i = load %struct.LIST_HELP** %List1.addr.0.idx15.i, align 4
-  %cmp.i16.i = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i, null
-  br i1 %cmp.i16.i, label %for.end.i, label %for.cond.i
-
-for.end.i:                                        ; preds = %for.cond.i
-  store %struct.LIST_HELP* %86, %struct.LIST_HELP** %List1.addr.0.idx15.i, align 4
-  br label %list_Nconc.exit
-
-list_Nconc.exit:                                  ; preds = %sw.bb190, %if.end.i1768, %for.end.i
-  %retval.0.i = phi %struct.LIST_HELP* [ %82, %for.end.i ], [ %86, %sw.bb190 ], [ %82, %if.end.i1768 ]
-  store %struct.LIST_HELP* %retval.0.i, %struct.LIST_HELP** @dfg_SORTDECLLIST, align 4
-  br label %sw.epilog1200
-
-sw.bb195:                                         ; preds = %yyreduce
-  %arrayidx196 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -4
-  %string197 = bitcast %union.yystype* %arrayidx196 to i8**
-  %88 = load i8** %string197, align 4
-  call void @string_StringFree(i8* %88) #1
-  br label %sw.epilog1200
-
-sw.bb198:                                         ; preds = %yyreduce
-  %89 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %call.i.i.i1769 = call i8* @memory_Malloc(i32 8) #1
-  %90 = bitcast i8* %call.i.i.i1769 to %struct.LIST_HELP*
-  %car.i.i.i1770 = getelementptr inbounds i8* %call.i.i.i1769, i32 4
-  %91 = bitcast i8* %car.i.i.i1770 to i8**
-  store i8* null, i8** %91, align 4
-  %cdr.i.i.i1771 = bitcast i8* %call.i.i.i1769 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %89, %struct.LIST_HELP** %cdr.i.i.i1771, align 4
-  store %struct.LIST_HELP* %90, %struct.LIST_HELP** @dfg_VARLIST, align 4
-  store i1 true, i1* @dfg_VARDECL, align 1
-  br label %sw.epilog1200
-
-sw.bb199:                                         ; preds = %yyreduce
-  store i1 false, i1* @dfg_VARDECL, align 1
-  br label %sw.epilog1200
-
-sw.bb200:                                         ; preds = %yyreduce
-  %92 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %.idx.i = getelementptr %struct.LIST_HELP* %92, i32 0, i32 1
-  %.idx.val.i = load i8** %.idx.i, align 4
-  %93 = bitcast i8* %.idx.val.i to %struct.LIST_HELP*
-  call void @list_DeleteWithElement(%struct.LIST_HELP* %93, void (i8*)* bitcast (void (%struct.DFG_VARENTRY*)* @dfg_VarFree to void (i8*)*)) #1
-  %94 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %L.idx.i.i = getelementptr %struct.LIST_HELP* %94, i32 0, i32 0
-  %L.idx.val.i.i = load %struct.LIST_HELP** %L.idx.i.i, align 4
-  %95 = bitcast %struct.LIST_HELP* %94 to i8*
-  %96 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %96, i32 0, i32 4
-  %97 = load i32* %total_size.i.i.i.i, align 4
-  %98 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i = add i32 %98, %97
-  store i32 %add24.i.i.i.i, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %96, i32 0, i32 0
-  %99 = load i8** %free.i.i.i.i, align 4
-  %.c.i.i.i = bitcast i8* %99 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i, %struct.LIST_HELP** %L.idx.i.i, align 4
-  %100 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %100, i32 0, i32 0
-  store i8* %95, i8** %free27.i.i.i.i, align 4
-  store %struct.LIST_HELP* %L.idx.val.i.i, %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %cmp.i.i1772 = icmp eq %struct.LIST_HELP* %L.idx.val.i.i, null
-  br i1 %cmp.i.i1772, label %dfg_VarCheck.exit, label %if.then.i1774
-
-if.then.i1774:                                    ; preds = %sw.bb200
-  %101 = load %struct._IO_FILE** @stdout, align 4
-  %call1.i1773 = call i32 @fflush(%struct._IO_FILE* %101) #1
-  %102 = load %struct._IO_FILE** @stderr, align 4
-  %call2.i = call i32 (%struct._IO_FILE*, i8*, ...)* @fprintf(%struct._IO_FILE* %102, i8* getelementptr inbounds ([31 x i8]* @.str27, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str28, i32 0, i32 0), i32 1881) #1
-  call void (i8*, ...)* @misc_ErrorReport(i8* getelementptr inbounds ([55 x i8]* @.str41, i32 0, i32 0)) #1
-  %103 = load %struct._IO_FILE** @stderr, align 4
-  %104 = call i32 @fwrite(i8* getelementptr inbounds ([133 x i8]* @.str30, i32 0, i32 0), i32 132, i32 1, %struct._IO_FILE* %103) #1
-  call fastcc void @misc_DumpCore() #1
-  unreachable
-
-dfg_VarCheck.exit:                                ; preds = %sw.bb200
-  store i32 0, i32* @symbol_STANDARDVARCOUNTER, align 4
-  %105 = load i32* @fol_ALL, align 4
-  %arrayidx203 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -6
-  %list = bitcast %union.yystype* %arrayidx203 to %struct.LIST_HELP**
-  %106 = load %struct.LIST_HELP** %list, align 4
-  %arrayidx204 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %term205 = bitcast %union.yystype* %arrayidx204 to %struct.term**
-  %107 = load %struct.term** %term205, align 4
-  %call206 = call %struct.term* @dfg_CreateQuantifier(i32 %105, %struct.LIST_HELP* %106, %struct.term* %107)
-  %108 = load %struct.LIST_HELP** @dfg_SORTDECLLIST, align 4
-  %109 = bitcast %struct.term* %call206 to %struct.LIST_HELP*
-  %call.i.i1776 = call i8* @memory_Malloc(i32 8) #1
-  %car.i.i1777 = getelementptr inbounds i8* %call.i.i1776, i32 4
-  %110 = bitcast i8* %car.i.i1777 to i8**
-  store i8* null, i8** %110, align 4
-  %cdr.i.i1778 = bitcast i8* %call.i.i1776 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %109, %struct.LIST_HELP** %cdr.i.i1778, align 4
-  %call.i.i1779 = call i8* @memory_Malloc(i32 8) #1
-  %111 = bitcast i8* %call.i.i1779 to %struct.LIST_HELP*
-  %car.i.i1780 = getelementptr inbounds i8* %call.i.i1779, i32 4
-  %112 = bitcast i8* %car.i.i1780 to i8**
-  store i8* %call.i.i1776, i8** %112, align 4
-  %cdr.i.i1781 = bitcast i8* %call.i.i1779 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i1781, align 4
-  %cmp.i.i1782 = icmp eq %struct.LIST_HELP* %108, null
-  br i1 %cmp.i.i1782, label %list_Nconc.exit1792, label %if.end.i1784
-
-if.end.i1784:                                     ; preds = %dfg_VarCheck.exit
-  %cmp.i18.i1783 = icmp eq i8* %call.i.i1779, null
-  br i1 %cmp.i18.i1783, label %list_Nconc.exit1792, label %for.cond.i1789
-
-for.cond.i1789:                                   ; preds = %if.end.i1784, %for.cond.i1789
-  %List1.addr.0.i1785 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i1787, %for.cond.i1789 ], [ %108, %if.end.i1784 ]
-  %List1.addr.0.idx15.i1786 = getelementptr %struct.LIST_HELP* %List1.addr.0.i1785, i32 0, i32 0
-  %List1.addr.0.idx15.val.i1787 = load %struct.LIST_HELP** %List1.addr.0.idx15.i1786, align 4
-  %cmp.i16.i1788 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i1787, null
-  br i1 %cmp.i16.i1788, label %for.end.i1790, label %for.cond.i1789
-
-for.end.i1790:                                    ; preds = %for.cond.i1789
-  store %struct.LIST_HELP* %111, %struct.LIST_HELP** %List1.addr.0.idx15.i1786, align 4
-  br label %list_Nconc.exit1792
-
-list_Nconc.exit1792:                              ; preds = %dfg_VarCheck.exit, %if.end.i1784, %for.end.i1790
-  %retval.0.i1791 = phi %struct.LIST_HELP* [ %108, %for.end.i1790 ], [ %111, %dfg_VarCheck.exit ], [ %108, %if.end.i1784 ]
-  store %struct.LIST_HELP* %retval.0.i1791, %struct.LIST_HELP** @dfg_SORTDECLLIST, align 4
-  br label %sw.epilog1200
-
-sw.bb210:                                         ; preds = %yyreduce
-  %arrayidx211 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -7
-  %string212 = bitcast %union.yystype* %arrayidx211 to i8**
-  %113 = load i8** %string212, align 4
-  %call213 = call fastcc i32 @dfg_Symbol(i8* %113, i32 1)
-  %bool = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -6, i32 0
-  %114 = load i32* %bool, align 4
-  %arrayidx215 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %list216 = bitcast %union.yystype* %arrayidx215 to %struct.LIST_HELP**
-  %115 = load %struct.LIST_HELP** %list216, align 4
-  %tobool.i.i1793 = icmp sgt i32 %call213, -1
-  br i1 %tobool.i.i1793, label %if.then.i1799, label %land.rhs.i.i1797
-
-land.rhs.i.i1797:                                 ; preds = %sw.bb210
-  %sub.i.i.i1794 = sub nsw i32 0, %call213
-  %and.i.i.i1795 = and i32 %3, %sub.i.i.i1794
-  %cmp.i.i1796 = icmp eq i32 %and.i.i.i1795, 2
-  br i1 %cmp.i.i1796, label %if.end.i1800, label %if.then.i1799
-
-if.then.i1799:                                    ; preds = %land.rhs.i.i1797, %sw.bb210
-  %116 = load %struct._IO_FILE** @stdout, align 4
-  %call1.i1798 = call i32 @fflush(%struct._IO_FILE* %116) #1
-  %117 = load i32* @dfg_LINENUMBER, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([44 x i8]* @.str42, i32 0, i32 0), i32 %117) #1
-  call fastcc void @misc_Error() #1
-  unreachable
-
-if.end.i1800:                                     ; preds = %land.rhs.i.i1797
-  %shr.i.i54.i = ashr i32 %sub.i.i.i1794, %4
-  %118 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i55.i = getelementptr inbounds %struct.signature** %118, i32 %shr.i.i54.i
-  %119 = load %struct.signature** %arrayidx.i.i55.i, align 4
-  %props.i56.i = getelementptr inbounds %struct.signature* %119, i32 0, i32 4
-  %120 = load i32* %props.i56.i, align 4
-  %and.i.i = and i32 %120, 512
-  %tobool.i57.i = icmp eq i32 %and.i.i, 0
-  br i1 %tobool.i57.i, label %symbol_RemoveProperty.exit.i, label %if.then.i.i
-
-if.then.i.i:                                      ; preds = %if.end.i1800
-  %sub.i.i = add i32 %120, -512
-  store i32 %sub.i.i, i32* %props.i56.i, align 4
-  %.pre.i = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i63.phi.trans.insert.i = getelementptr inbounds %struct.signature** %.pre.i, i32 %shr.i.i54.i
-  %.pre93.i = load %struct.signature** %arrayidx.i.i63.phi.trans.insert.i, align 4
-  %props.i64.phi.trans.insert.i = getelementptr inbounds %struct.signature* %.pre93.i, i32 0, i32 4
-  %.pre94.i = load i32* %props.i64.phi.trans.insert.i, align 4
-  br label %symbol_RemoveProperty.exit.i
-
-symbol_RemoveProperty.exit.i:                     ; preds = %if.then.i.i, %if.end.i1800
-  %121 = phi i32 [ %120, %if.end.i1800 ], [ %.pre94.i, %if.then.i.i ]
-  %122 = phi %struct.signature* [ %119, %if.end.i1800 ], [ %.pre93.i, %if.then.i.i ]
-  %and.i65.i = and i32 %121, 256
-  %tobool.i66.i = icmp eq i32 %and.i65.i, 0
-  br i1 %tobool.i66.i, label %symbol_RemoveProperty.exit69.i, label %if.then.i68.i
-
-if.then.i68.i:                                    ; preds = %symbol_RemoveProperty.exit.i
-  %props.i64.i = getelementptr inbounds %struct.signature* %122, i32 0, i32 4
-  %sub.i67.i = add i32 %121, -256
-  store i32 %sub.i67.i, i32* %props.i64.i, align 4
-  %.pre95.i = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i83.phi.trans.insert.i = getelementptr inbounds %struct.signature** %.pre95.i, i32 %shr.i.i54.i
-  %.pre96.i = load %struct.signature** %arrayidx.i.i83.phi.trans.insert.i, align 4
-  br label %symbol_RemoveProperty.exit69.i
-
-symbol_RemoveProperty.exit69.i:                   ; preds = %if.then.i68.i, %symbol_RemoveProperty.exit.i
-  %123 = phi %struct.signature* [ %122, %symbol_RemoveProperty.exit.i ], [ %.pre96.i, %if.then.i68.i ]
-  %generatedBy.i84.i = getelementptr inbounds %struct.signature* %123, i32 0, i32 6
-  %124 = load %struct.LIST_HELP** %generatedBy.i84.i, align 4
-  %cmp.i5.i.i = icmp eq %struct.LIST_HELP* %124, null
-  br i1 %cmp.i5.i.i, label %list_Delete.exit.i, label %while.body.i.i
-
-while.body.i.i:                                   ; preds = %symbol_RemoveProperty.exit69.i, %while.body.i.i
-  %L.addr.06.i.i = phi %struct.LIST_HELP* [ %L.addr.0.idx.val.i.i, %while.body.i.i ], [ %124, %symbol_RemoveProperty.exit69.i ]
-  %L.addr.0.idx.i.i = getelementptr %struct.LIST_HELP* %L.addr.06.i.i, i32 0, i32 0
-  %L.addr.0.idx.val.i.i = load %struct.LIST_HELP** %L.addr.0.idx.i.i, align 4
-  %125 = bitcast %struct.LIST_HELP* %L.addr.06.i.i to i8*
-  %126 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i1801 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %126, i32 0, i32 4
-  %127 = load i32* %total_size.i.i.i.i1801, align 4
-  %128 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i1802 = add i32 %128, %127
-  store i32 %add24.i.i.i.i1802, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i1803 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %126, i32 0, i32 0
-  %129 = load i8** %free.i.i.i.i1803, align 4
-  %.c.i.i.i1804 = bitcast i8* %129 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i1804, %struct.LIST_HELP** %L.addr.0.idx.i.i, align 4
-  %130 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i1805 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %130, i32 0, i32 0
-  store i8* %125, i8** %free27.i.i.i.i1805, align 4
-  %cmp.i.i.i1806 = icmp eq %struct.LIST_HELP* %L.addr.0.idx.val.i.i, null
-  br i1 %cmp.i.i.i1806, label %list_Delete.exit.loopexit.i, label %while.body.i.i
-
-list_Delete.exit.loopexit.i:                      ; preds = %while.body.i.i
-  %.pre97.i = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i78.phi.trans.insert.i = getelementptr inbounds %struct.signature** %.pre97.i, i32 %shr.i.i54.i
-  %.pre98.i = load %struct.signature** %arrayidx.i.i78.phi.trans.insert.i, align 4
-  br label %list_Delete.exit.i
-
-list_Delete.exit.i:                               ; preds = %list_Delete.exit.loopexit.i, %symbol_RemoveProperty.exit69.i
-  %131 = phi %struct.signature* [ %.pre98.i, %list_Delete.exit.loopexit.i ], [ %123, %symbol_RemoveProperty.exit69.i ]
-  %props.i79.i = getelementptr inbounds %struct.signature* %131, i32 0, i32 4
-  %132 = load i32* %props.i79.i, align 4
-  %or.i80.i = or i32 %132, 512
-  store i32 %or.i80.i, i32* %props.i79.i, align 4
-  %tobool3.i = icmp ne i32 %114, 0
-  br i1 %tobool3.i, label %if.then4.i, label %for.cond.preheader.i
-
-if.then4.i:                                       ; preds = %list_Delete.exit.i
-  %133 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i73.i = getelementptr inbounds %struct.signature** %133, i32 %shr.i.i54.i
-  %134 = load %struct.signature** %arrayidx.i.i73.i, align 4
-  %props.i74.i = getelementptr inbounds %struct.signature* %134, i32 0, i32 4
-  %135 = load i32* %props.i74.i, align 4
-  %or.i75.i = or i32 %135, 256
-  store i32 %or.i75.i, i32* %props.i74.i, align 4
-  br label %for.cond.preheader.i
-
-for.cond.preheader.i:                             ; preds = %if.then4.i, %list_Delete.exit.i
-  %cmp.i7086.i = icmp eq %struct.LIST_HELP* %115, null
-  br i1 %cmp.i7086.i, label %dfg_SymbolGenerated.exit, label %for.body.lr.ph.i
-
-for.body.lr.ph.i:                                 ; preds = %for.cond.preheader.i
-  br i1 %tobool3.i, label %for.body.us.i, label %for.body.i
-
-for.body.us.i:                                    ; preds = %for.body.lr.ph.i, %for.inc.us.i
-  %scan.087.us.i = phi %struct.LIST_HELP* [ %scan.0.idx43.val.us.i, %for.inc.us.i ], [ %115, %for.body.lr.ph.i ]
-  %scan.0.idx42.us.i = getelementptr %struct.LIST_HELP* %scan.087.us.i, i32 0, i32 1
-  %scan.0.idx42.val.us.i = load i8** %scan.0.idx42.us.i, align 4
-  %call9.us.i = call i32 @symbol_Lookup(i8* %scan.0.idx42.val.us.i) #1
-  %cmp.us.i = icmp eq i32 %call9.us.i, 0
-  br i1 %cmp.us.i, label %if.then10.i, label %if.else.us.i
-
-if.else.us.i:                                     ; preds = %for.body.us.i
-  %tobool.i58.us.i = icmp sgt i32 %call9.us.i, -1
-  br i1 %tobool.i58.us.i, label %if.then15.i, label %land.rhs.i59.us.i
-
-land.rhs.i59.us.i:                                ; preds = %if.else.us.i
-  %sub.i6.i.us.i = sub nsw i32 0, %call9.us.i
-  %and.i7.i.us.i = and i32 %3, %sub.i6.i.us.i
-  %136 = icmp ult i32 %and.i7.i.us.i, 2
-  br i1 %136, label %for.inc.us.i, label %if.then15.i
-
-for.inc.us.i:                                     ; preds = %land.rhs.i59.us.i
-  %scan.0.idx.val.us.i = load i8** %scan.0.idx42.us.i, align 4
-  call void @string_StringFree(i8* %scan.0.idx.val.us.i) #1
-  %137 = inttoptr i32 %call9.us.i to i8*
-  store i8* %137, i8** %scan.0.idx42.us.i, align 4
-  %shr.i.i49.us.i = ashr i32 %sub.i6.i.us.i, %4
-  %138 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i50.us.i = getelementptr inbounds %struct.signature** %138, i32 %shr.i.i49.us.i
-  %139 = load %struct.signature** %arrayidx.i.i50.us.i, align 4
-  %props.i51.us.i = getelementptr inbounds %struct.signature* %139, i32 0, i32 4
-  %140 = load i32* %props.i51.us.i, align 4
-  %or.i52.us.i = or i32 %140, 512
-  store i32 %or.i52.us.i, i32* %props.i51.us.i, align 4
-  %141 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i47.us.i = getelementptr inbounds %struct.signature** %141, i32 %shr.i.i49.us.i
-  %142 = load %struct.signature** %arrayidx.i.i47.us.i, align 4
-  %props.i.us.i = getelementptr inbounds %struct.signature* %142, i32 0, i32 4
-  %143 = load i32* %props.i.us.i, align 4
-  %or.i.us.i = or i32 %143, 256
-  store i32 %or.i.us.i, i32* %props.i.us.i, align 4
-  %scan.0.idx43.us.i = getelementptr %struct.LIST_HELP* %scan.087.us.i, i32 0, i32 0
-  %scan.0.idx43.val.us.i = load %struct.LIST_HELP** %scan.0.idx43.us.i, align 4
-  %cmp.i70.us.i = icmp eq %struct.LIST_HELP* %scan.0.idx43.val.us.i, null
-  br i1 %cmp.i70.us.i, label %dfg_SymbolGenerated.exit, label %for.body.us.i
-
-for.body.i:                                       ; preds = %for.body.lr.ph.i, %for.inc.i
-  %scan.087.i = phi %struct.LIST_HELP* [ %scan.0.idx43.val.i, %for.inc.i ], [ %115, %for.body.lr.ph.i ]
-  %scan.0.idx42.i = getelementptr %struct.LIST_HELP* %scan.087.i, i32 0, i32 1
-  %scan.0.idx42.val.i = load i8** %scan.0.idx42.i, align 4
-  %call9.i = call i32 @symbol_Lookup(i8* %scan.0.idx42.val.i) #1
-  %cmp.i = icmp eq i32 %call9.i, 0
-  br i1 %cmp.i, label %if.then10.i, label %if.else.i
-
-if.then10.i:                                      ; preds = %for.body.us.i, %for.body.i
-  %scan.0.idx42.lcssa.i = phi i8** [ %scan.0.idx42.i, %for.body.i ], [ %scan.0.idx42.us.i, %for.body.us.i ]
-  %144 = load %struct._IO_FILE** @stdout, align 4
-  %call11.i1807 = call i32 @fflush(%struct._IO_FILE* %144) #1
-  %145 = load i32* @dfg_LINENUMBER, align 4
-  %scan.0.idx41.val.i = load i8** %scan.0.idx42.lcssa.i, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([33 x i8]* @.str43, i32 0, i32 0), i32 %145, i8* %scan.0.idx41.val.i) #1
-  call fastcc void @misc_Error() #1
-  unreachable
-
-if.else.i:                                        ; preds = %for.body.i
-  %tobool.i58.i = icmp sgt i32 %call9.i, -1
-  br i1 %tobool.i58.i, label %if.then15.i, label %land.rhs.i59.i
-
-land.rhs.i59.i:                                   ; preds = %if.else.i
-  %sub.i6.i.i = sub nsw i32 0, %call9.i
-  %and.i7.i.i = and i32 %3, %sub.i6.i.i
-  %146 = icmp ult i32 %and.i7.i.i, 2
-  br i1 %146, label %for.inc.i, label %if.then15.i
-
-if.then15.i:                                      ; preds = %land.rhs.i59.us.i, %if.else.us.i, %land.rhs.i59.i, %if.else.i
-  %147 = load %struct._IO_FILE** @stdout, align 4
-  %call16.i1808 = call i32 @fflush(%struct._IO_FILE* %147) #1
-  %148 = load i32* @dfg_LINENUMBER, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([38 x i8]* @.str44, i32 0, i32 0), i32 %148) #1
-  call fastcc void @misc_Error() #1
-  unreachable
-
-for.inc.i:                                        ; preds = %land.rhs.i59.i
-  %scan.0.idx.val.i = load i8** %scan.0.idx42.i, align 4
-  call void @string_StringFree(i8* %scan.0.idx.val.i) #1
-  %149 = inttoptr i32 %call9.i to i8*
-  store i8* %149, i8** %scan.0.idx42.i, align 4
-  %shr.i.i49.i = ashr i32 %sub.i6.i.i, %4
-  %150 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i50.i = getelementptr inbounds %struct.signature** %150, i32 %shr.i.i49.i
-  %151 = load %struct.signature** %arrayidx.i.i50.i, align 4
-  %props.i51.i = getelementptr inbounds %struct.signature* %151, i32 0, i32 4
-  %152 = load i32* %props.i51.i, align 4
-  %or.i52.i = or i32 %152, 512
-  store i32 %or.i52.i, i32* %props.i51.i, align 4
-  %scan.0.idx43.i = getelementptr %struct.LIST_HELP* %scan.087.i, i32 0, i32 0
-  %scan.0.idx43.val.i = load %struct.LIST_HELP** %scan.0.idx43.i, align 4
-  %cmp.i70.i = icmp eq %struct.LIST_HELP* %scan.0.idx43.val.i, null
-  br i1 %cmp.i70.i, label %dfg_SymbolGenerated.exit, label %for.body.i
-
-dfg_SymbolGenerated.exit:                         ; preds = %for.inc.us.i, %for.inc.i, %for.cond.preheader.i
-  %153 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i.i = getelementptr inbounds %struct.signature** %153, i32 %shr.i.i54.i
-  %154 = load %struct.signature** %arrayidx.i.i.i, align 4
-  %generatedBy.i.i = getelementptr inbounds %struct.signature* %154, i32 0, i32 6
-  store %struct.LIST_HELP* %115, %struct.LIST_HELP** %generatedBy.i.i, align 4
-  br label %sw.epilog1200
-
-sw.bb217:                                         ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb219:                                         ; preds = %yyreduce
-  store i32 1, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb221:                                         ; preds = %yyreduce
-  %string223 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %155 = load i8** %string223, align 4
-  %call.i.i1810 = call i8* @memory_Malloc(i32 8) #1
-  %car.i.i1811 = getelementptr inbounds i8* %call.i.i1810, i32 4
-  %156 = bitcast i8* %car.i.i1811 to i8**
-  store i8* %155, i8** %156, align 4
-  %cdr.i.i1812 = bitcast i8* %call.i.i1810 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i1812, align 4
-  %call224.c = ptrtoint i8* %call.i.i1810 to i32
-  store i32 %call224.c, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb226:                                         ; preds = %yyreduce
-  %string228 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %157 = load i8** %string228, align 4
-  %arrayidx229 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %list230 = bitcast %union.yystype* %arrayidx229 to %struct.LIST_HELP**
-  %158 = load %struct.LIST_HELP** %list230, align 4
-  %call.i1813 = call i8* @memory_Malloc(i32 8) #1
-  %car.i = getelementptr inbounds i8* %call.i1813, i32 4
-  %159 = bitcast i8* %car.i to i8**
-  store i8* %157, i8** %159, align 4
-  %cdr.i = bitcast i8* %call.i1813 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %158, %struct.LIST_HELP** %cdr.i, align 4
-  %call231.c = ptrtoint i8* %call.i1813 to i32
-  store i32 %call231.c, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb233:                                         ; preds = %yyreduce
-  %string235 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %160 = load i8** %string235, align 4
-  call void @string_StringFree(i8* %160) #1
-  br label %sw.epilog1200
-
-sw.bb236:                                         ; preds = %yyreduce
-  %string238 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %161 = load i8** %string238, align 4
-  call void @string_StringFree(i8* %161) #1
-  br label %sw.epilog1200
-
-sw.bb239:                                         ; preds = %yyreduce
-  %arrayidx240 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %list241 = bitcast %union.yystype* %arrayidx240 to %struct.LIST_HELP**
-  %162 = load %struct.LIST_HELP** %list241, align 4
-  %call242 = call %struct.LIST_HELP* @list_NReverse(%struct.LIST_HELP* %162) #1
-  %bool244 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -5, i32 0
-  %163 = load i32* %bool244, align 4
-  %tobool245 = icmp eq i32 %163, 0
-  br i1 %tobool245, label %if.else250, label %if.then246
-
-if.then246:                                       ; preds = %sw.bb239
-  %164 = load %struct.LIST_HELP** @dfg_AXIOMLIST, align 4
-  %165 = load %struct.LIST_HELP** %list241, align 4
-  %cmp.i.i1814 = icmp eq %struct.LIST_HELP* %164, null
-  br i1 %cmp.i.i1814, label %list_Nconc.exit1824, label %if.end.i1816
-
-if.end.i1816:                                     ; preds = %if.then246
-  %cmp.i18.i1815 = icmp eq %struct.LIST_HELP* %165, null
-  br i1 %cmp.i18.i1815, label %list_Nconc.exit1824, label %for.cond.i1821
-
-for.cond.i1821:                                   ; preds = %if.end.i1816, %for.cond.i1821
-  %List1.addr.0.i1817 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i1819, %for.cond.i1821 ], [ %164, %if.end.i1816 ]
-  %List1.addr.0.idx15.i1818 = getelementptr %struct.LIST_HELP* %List1.addr.0.i1817, i32 0, i32 0
-  %List1.addr.0.idx15.val.i1819 = load %struct.LIST_HELP** %List1.addr.0.idx15.i1818, align 4
-  %cmp.i16.i1820 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i1819, null
-  br i1 %cmp.i16.i1820, label %for.end.i1822, label %for.cond.i1821
-
-for.end.i1822:                                    ; preds = %for.cond.i1821
-  store %struct.LIST_HELP* %165, %struct.LIST_HELP** %List1.addr.0.idx15.i1818, align 4
-  br label %list_Nconc.exit1824
-
-list_Nconc.exit1824:                              ; preds = %if.then246, %if.end.i1816, %for.end.i1822
-  %retval.0.i1823 = phi %struct.LIST_HELP* [ %164, %for.end.i1822 ], [ %165, %if.then246 ], [ %164, %if.end.i1816 ]
-  store %struct.LIST_HELP* %retval.0.i1823, %struct.LIST_HELP** @dfg_AXIOMLIST, align 4
-  br label %sw.epilog1200
-
-if.else250:                                       ; preds = %sw.bb239
-  %166 = load %struct.LIST_HELP** @dfg_CONJECLIST, align 4
-  %167 = load %struct.LIST_HELP** %list241, align 4
-  %cmp.i.i1825 = icmp eq %struct.LIST_HELP* %166, null
-  br i1 %cmp.i.i1825, label %list_Nconc.exit1835, label %if.end.i1827
-
-if.end.i1827:                                     ; preds = %if.else250
-  %cmp.i18.i1826 = icmp eq %struct.LIST_HELP* %167, null
-  br i1 %cmp.i18.i1826, label %list_Nconc.exit1835, label %for.cond.i1832
-
-for.cond.i1832:                                   ; preds = %if.end.i1827, %for.cond.i1832
-  %List1.addr.0.i1828 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i1830, %for.cond.i1832 ], [ %166, %if.end.i1827 ]
-  %List1.addr.0.idx15.i1829 = getelementptr %struct.LIST_HELP* %List1.addr.0.i1828, i32 0, i32 0
-  %List1.addr.0.idx15.val.i1830 = load %struct.LIST_HELP** %List1.addr.0.idx15.i1829, align 4
-  %cmp.i16.i1831 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i1830, null
-  br i1 %cmp.i16.i1831, label %for.end.i1833, label %for.cond.i1832
-
-for.end.i1833:                                    ; preds = %for.cond.i1832
-  store %struct.LIST_HELP* %167, %struct.LIST_HELP** %List1.addr.0.idx15.i1829, align 4
-  br label %list_Nconc.exit1835
-
-list_Nconc.exit1835:                              ; preds = %if.else250, %if.end.i1827, %for.end.i1833
-  %retval.0.i1834 = phi %struct.LIST_HELP* [ %166, %for.end.i1833 ], [ %167, %if.else250 ], [ %166, %if.end.i1827 ]
-  store %struct.LIST_HELP* %retval.0.i1834, %struct.LIST_HELP** @dfg_CONJECLIST, align 4
-  br label %sw.epilog1200
-
-sw.bb255:                                         ; preds = %yyreduce
-  store i32 1, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb257:                                         ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb259:                                         ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb262:                                         ; preds = %yyreduce
-  %arrayidx263 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -3
-  %term264 = bitcast %union.yystype* %arrayidx263 to %struct.term**
-  %168 = load %struct.term** %term264, align 4
-  %cmp265 = icmp eq %struct.term* %168, null
-  %arrayidx268 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %string269 = bitcast %union.yystype* %arrayidx268 to i8**
-  %169 = load i8** %string269, align 4
-  br i1 %cmp265, label %if.then267, label %if.else279
-
-if.then267:                                       ; preds = %sw.bb262
-  %cmp270 = icmp eq i8* %169, null
-  br i1 %cmp270, label %if.end275, label %if.then272
-
-if.then272:                                       ; preds = %if.then267
-  call void @string_StringFree(i8* %169) #1
-  br label %if.end275
-
-if.end275:                                        ; preds = %if.then267, %if.then272
-  %arrayidx276 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -6
-  %list277 = bitcast %union.yystype* %arrayidx276 to %struct.LIST_HELP**
-  %170 = load %struct.LIST_HELP** %list277, align 4
-  %.c1755 = ptrtoint %struct.LIST_HELP* %170 to i32
-  br label %if.end289
-
-if.else279:                                       ; preds = %sw.bb262
-  %171 = bitcast %struct.term* %168 to %struct.LIST_HELP*
-  %call.i.i1836 = call i8* @memory_Malloc(i32 8) #1
-  %car.i.i1837 = getelementptr inbounds i8* %call.i.i1836, i32 4
-  %172 = bitcast i8* %car.i.i1837 to i8**
-  store i8* %169, i8** %172, align 4
-  %cdr.i.i1838 = bitcast i8* %call.i.i1836 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %171, %struct.LIST_HELP** %cdr.i.i1838, align 4
-  %arrayidx285 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -6
-  %list286 = bitcast %union.yystype* %arrayidx285 to %struct.LIST_HELP**
-  %173 = load %struct.LIST_HELP** %list286, align 4
-  %call.i1839 = call i8* @memory_Malloc(i32 8) #1
-  %car.i1840 = getelementptr inbounds i8* %call.i1839, i32 4
-  %174 = bitcast i8* %car.i1840 to i8**
-  store i8* %call.i.i1836, i8** %174, align 4
-  %cdr.i1841 = bitcast i8* %call.i1839 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %173, %struct.LIST_HELP** %cdr.i1841, align 4
-  %call287.c = ptrtoint i8* %call.i1839 to i32
-  br label %if.end289
-
-if.end289:                                        ; preds = %if.else279, %if.end275
-  %storemerge2213 = phi i32 [ %call287.c, %if.else279 ], [ %.c1755, %if.end275 ]
-  store i32 %storemerge2213, i32* %2, align 4
-  %175 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %cmp.i.i1842 = icmp eq %struct.LIST_HELP* %175, null
-  br i1 %cmp.i.i1842, label %dfg_VarCheck.exit1847, label %if.then.i1845
-
-if.then.i1845:                                    ; preds = %if.end289
-  %176 = load %struct._IO_FILE** @stdout, align 4
-  %call1.i1843 = call i32 @fflush(%struct._IO_FILE* %176) #1
-  %177 = load %struct._IO_FILE** @stderr, align 4
-  %call2.i1844 = call i32 (%struct._IO_FILE*, i8*, ...)* @fprintf(%struct._IO_FILE* %177, i8* getelementptr inbounds ([31 x i8]* @.str27, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str28, i32 0, i32 0), i32 1881) #1
-  call void (i8*, ...)* @misc_ErrorReport(i8* getelementptr inbounds ([55 x i8]* @.str41, i32 0, i32 0)) #1
-  %178 = load %struct._IO_FILE** @stderr, align 4
-  %179 = call i32 @fwrite(i8* getelementptr inbounds ([133 x i8]* @.str30, i32 0, i32 0), i32 132, i32 1, %struct._IO_FILE* %178) #1
-  call fastcc void @misc_DumpCore() #1
-  unreachable
-
-dfg_VarCheck.exit1847:                            ; preds = %if.end289
-  store i32 0, i32* @symbol_STANDARDVARCOUNTER, align 4
-  br label %sw.epilog1200
-
-sw.bb290:                                         ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb292:                                         ; preds = %yyreduce
-  %string294 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %180 = load i8** %string294, align 4
-  %.c1754 = ptrtoint i8* %180 to i32
-  store i32 %.c1754, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb296:                                         ; preds = %yyreduce
-  %term298 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %181 = load %struct.term** %term298, align 4
-  %.c1753 = ptrtoint %struct.term* %181 to i32
-  store i32 %.c1753, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb300:                                         ; preds = %yyreduce
-  %182 = load i32* @dfg_IGNORE, align 4
-  %tobool301 = icmp eq i32 %182, 0
-  br i1 %tobool301, label %cond.false303, label %cond.end309
-
-cond.false303:                                    ; preds = %sw.bb300
-  %183 = load i32* @fol_NOT, align 4
-  %arrayidx305 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1
-  %term306 = bitcast %union.yystype* %arrayidx305 to %struct.term**
-  %184 = load %struct.term** %term306, align 4
-  %185 = bitcast %struct.term* %184 to i8*
-  %call.i.i1848 = call i8* @memory_Malloc(i32 8) #1
-  %186 = bitcast i8* %call.i.i1848 to %struct.LIST_HELP*
-  %car.i.i1849 = getelementptr inbounds i8* %call.i.i1848, i32 4
-  %187 = bitcast i8* %car.i.i1849 to i8**
-  store i8* %185, i8** %187, align 4
-  %cdr.i.i1850 = bitcast i8* %call.i.i1848 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i1850, align 4
-  %call308 = call %struct.term* @term_Create(i32 %183, %struct.LIST_HELP* %186) #1
-  %phitmp1752 = ptrtoint %struct.term* %call308 to i32
-  br label %cond.end309
-
-cond.end309:                                      ; preds = %sw.bb300, %cond.false303
-  %cond310 = phi i32 [ %phitmp1752, %cond.false303 ], [ 0, %sw.bb300 ]
-  store i32 %cond310, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb312:                                         ; preds = %yyreduce
-  %188 = load i32* @dfg_IGNORE, align 4
-  %tobool313 = icmp eq i32 %188, 0
-  br i1 %tobool313, label %cond.false315, label %cond.end324
-
-cond.false315:                                    ; preds = %sw.bb312
-  %symbol = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -5, i32 0
-  %189 = load i32* %symbol, align 4
-  %arrayidx317 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -3
-  %term318 = bitcast %union.yystype* %arrayidx317 to %struct.term**
-  %190 = load %struct.term** %term318, align 4
-  %191 = bitcast %struct.term* %190 to i8*
-  %arrayidx319 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1
-  %term320 = bitcast %union.yystype* %arrayidx319 to %struct.term**
-  %192 = load %struct.term** %term320, align 4
-  %193 = bitcast %struct.term* %192 to i8*
-  %call.i.i1851 = call i8* @memory_Malloc(i32 8) #1
-  %194 = bitcast i8* %call.i.i1851 to %struct.LIST_HELP*
-  %car.i.i1852 = getelementptr inbounds i8* %call.i.i1851, i32 4
-  %195 = bitcast i8* %car.i.i1852 to i8**
-  store i8* %193, i8** %195, align 4
-  %cdr.i.i1853 = bitcast i8* %call.i.i1851 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i1853, align 4
-  %call.i1854 = call i8* @memory_Malloc(i32 8) #1
-  %196 = bitcast i8* %call.i1854 to %struct.LIST_HELP*
-  %car.i1855 = getelementptr inbounds i8* %call.i1854, i32 4
-  %197 = bitcast i8* %car.i1855 to i8**
-  store i8* %191, i8** %197, align 4
-  %cdr.i1856 = bitcast i8* %call.i1854 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %194, %struct.LIST_HELP** %cdr.i1856, align 4
-  %call323 = call %struct.term* @term_Create(i32 %189, %struct.LIST_HELP* %196) #1
-  %phitmp1751 = ptrtoint %struct.term* %call323 to i32
-  br label %cond.end324
-
-cond.end324:                                      ; preds = %sw.bb312, %cond.false315
-  %cond325 = phi i32 [ %phitmp1751, %cond.false315 ], [ 0, %sw.bb312 ]
-  store i32 %cond325, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb327:                                         ; preds = %yyreduce
-  %198 = load i32* @dfg_IGNORE, align 4
-  %tobool328 = icmp eq i32 %198, 0
-  br i1 %tobool328, label %cond.false330, label %cond.end336
-
-cond.false330:                                    ; preds = %sw.bb327
-  %symbol332 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -3, i32 0
-  %199 = load i32* %symbol332, align 4
-  %arrayidx333 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1
-  %list334 = bitcast %union.yystype* %arrayidx333 to %struct.LIST_HELP**
-  %200 = load %struct.LIST_HELP** %list334, align 4
-  %call335 = call %struct.term* @term_Create(i32 %199, %struct.LIST_HELP* %200) #1
-  %phitmp1750 = ptrtoint %struct.term* %call335 to i32
-  br label %cond.end336
-
-cond.end336:                                      ; preds = %sw.bb327, %cond.false330
-  %cond337 = phi i32 [ %phitmp1750, %cond.false330 ], [ 0, %sw.bb327 ]
-  store i32 %cond337, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb339:                                         ; preds = %yyreduce
-  %201 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %call.i.i.i1857 = call i8* @memory_Malloc(i32 8) #1
-  %202 = bitcast i8* %call.i.i.i1857 to %struct.LIST_HELP*
-  %car.i.i.i1858 = getelementptr inbounds i8* %call.i.i.i1857, i32 4
-  %203 = bitcast i8* %car.i.i.i1858 to i8**
-  store i8* null, i8** %203, align 4
-  %cdr.i.i.i1859 = bitcast i8* %call.i.i.i1857 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %201, %struct.LIST_HELP** %cdr.i.i.i1859, align 4
-  store %struct.LIST_HELP* %202, %struct.LIST_HELP** @dfg_VARLIST, align 4
-  store i1 true, i1* @dfg_VARDECL, align 1
-  br label %sw.epilog1200
-
-sw.bb340:                                         ; preds = %yyreduce
-  store i1 false, i1* @dfg_VARDECL, align 1
-  br label %sw.epilog1200
-
-sw.bb341:                                         ; preds = %yyreduce
-  %204 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %.idx.i1860 = getelementptr %struct.LIST_HELP* %204, i32 0, i32 1
-  %.idx.val.i1861 = load i8** %.idx.i1860, align 4
-  %205 = bitcast i8* %.idx.val.i1861 to %struct.LIST_HELP*
-  call void @list_DeleteWithElement(%struct.LIST_HELP* %205, void (i8*)* bitcast (void (%struct.DFG_VARENTRY*)* @dfg_VarFree to void (i8*)*)) #1
-  %206 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %L.idx.i.i1862 = getelementptr %struct.LIST_HELP* %206, i32 0, i32 0
-  %L.idx.val.i.i1863 = load %struct.LIST_HELP** %L.idx.i.i1862, align 4
-  %207 = bitcast %struct.LIST_HELP* %206 to i8*
-  %208 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i1864 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %208, i32 0, i32 4
-  %209 = load i32* %total_size.i.i.i.i1864, align 4
-  %210 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i1865 = add i32 %210, %209
-  store i32 %add24.i.i.i.i1865, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i1866 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %208, i32 0, i32 0
-  %211 = load i8** %free.i.i.i.i1866, align 4
-  %.c.i.i.i1867 = bitcast i8* %211 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i1867, %struct.LIST_HELP** %L.idx.i.i1862, align 4
-  %212 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i1868 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %212, i32 0, i32 0
-  store i8* %207, i8** %free27.i.i.i.i1868, align 4
-  store %struct.LIST_HELP* %L.idx.val.i.i1863, %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %213 = load i32* @dfg_IGNORE, align 4
-  %tobool342 = icmp eq i32 %213, 0
-  br i1 %tobool342, label %cond.false344, label %cond.end352
-
-cond.false344:                                    ; preds = %sw.bb341
-  %symbol346 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -9, i32 0
-  %214 = load i32* %symbol346, align 4
-  %arrayidx347 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -5
-  %list348 = bitcast %union.yystype* %arrayidx347 to %struct.LIST_HELP**
-  %215 = load %struct.LIST_HELP** %list348, align 4
-  %arrayidx349 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1
-  %term350 = bitcast %union.yystype* %arrayidx349 to %struct.term**
-  %216 = load %struct.term** %term350, align 4
-  %call351 = call %struct.term* @dfg_CreateQuantifier(i32 %214, %struct.LIST_HELP* %215, %struct.term* %216)
-  %phitmp1749 = ptrtoint %struct.term* %call351 to i32
-  br label %cond.end352
-
-cond.end352:                                      ; preds = %sw.bb341, %cond.false344
-  %cond353 = phi i32 [ %phitmp1749, %cond.false344 ], [ 0, %sw.bb341 ]
-  store i32 %cond353, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb355:                                         ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb357:                                         ; preds = %yyreduce
-  %term359 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %217 = load %struct.term** %term359, align 4
-  %.c1748 = ptrtoint %struct.term* %217 to i32
-  store i32 %.c1748, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb361:                                         ; preds = %yyreduce
-  %218 = load i32* @dfg_IGNORE, align 4
-  %tobool362 = icmp eq i32 %218, 0
-  br i1 %tobool362, label %cond.false365, label %cond.end369
-
-cond.false365:                                    ; preds = %sw.bb361
-  %term367 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %219 = load %struct.term** %term367, align 4
-  %220 = bitcast %struct.term* %219 to i8*
-  %call.i.i1869 = call i8* @memory_Malloc(i32 8) #1
-  %car.i.i1870 = getelementptr inbounds i8* %call.i.i1869, i32 4
-  %221 = bitcast i8* %car.i.i1870 to i8**
-  store i8* %220, i8** %221, align 4
-  %cdr.i.i1871 = bitcast i8* %call.i.i1869 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i1871, align 4
-  %phitmp1747 = ptrtoint i8* %call.i.i1869 to i32
-  br label %cond.end369
-
-cond.end369:                                      ; preds = %sw.bb361, %cond.false365
-  %cond370 = phi i32 [ %phitmp1747, %cond.false365 ], [ 0, %sw.bb361 ]
-  store i32 %cond370, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb372:                                         ; preds = %yyreduce
-  %222 = load i32* @dfg_IGNORE, align 4
-  %tobool373 = icmp eq i32 %222, 0
-  %arrayidx375 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %list376 = bitcast %union.yystype* %arrayidx375 to %struct.LIST_HELP**
-  %223 = load %struct.LIST_HELP** %list376, align 4
-  br i1 %tobool373, label %cond.false377, label %cond.end384
-
-cond.false377:                                    ; preds = %sw.bb372
-  %term381 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %224 = load %struct.term** %term381, align 4
-  %225 = bitcast %struct.term* %224 to i8*
-  %call.i.i1872 = call i8* @memory_Malloc(i32 8) #1
-  %226 = bitcast i8* %call.i.i1872 to %struct.LIST_HELP*
-  %car.i.i1873 = getelementptr inbounds i8* %call.i.i1872, i32 4
-  %227 = bitcast i8* %car.i.i1873 to i8**
-  store i8* %225, i8** %227, align 4
-  %cdr.i.i1874 = bitcast i8* %call.i.i1872 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i1874, align 4
-  %cmp.i.i1875 = icmp eq %struct.LIST_HELP* %223, null
-  br i1 %cmp.i.i1875, label %cond.end384, label %if.end.i1877
-
-if.end.i1877:                                     ; preds = %cond.false377
-  %cmp.i18.i1876 = icmp eq i8* %call.i.i1872, null
-  br i1 %cmp.i18.i1876, label %cond.end384, label %for.cond.i1882
-
-for.cond.i1882:                                   ; preds = %if.end.i1877, %for.cond.i1882
-  %List1.addr.0.i1878 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i1880, %for.cond.i1882 ], [ %223, %if.end.i1877 ]
-  %List1.addr.0.idx15.i1879 = getelementptr %struct.LIST_HELP* %List1.addr.0.i1878, i32 0, i32 0
-  %List1.addr.0.idx15.val.i1880 = load %struct.LIST_HELP** %List1.addr.0.idx15.i1879, align 4
-  %cmp.i16.i1881 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i1880, null
-  br i1 %cmp.i16.i1881, label %for.end.i1883, label %for.cond.i1882
-
-for.end.i1883:                                    ; preds = %for.cond.i1882
-  store %struct.LIST_HELP* %226, %struct.LIST_HELP** %List1.addr.0.idx15.i1879, align 4
-  br label %cond.end384
-
-cond.end384:                                      ; preds = %for.end.i1883, %if.end.i1877, %cond.false377, %sw.bb372
-  %cond385 = phi %struct.LIST_HELP* [ %223, %sw.bb372 ], [ %223, %for.end.i1883 ], [ %226, %cond.false377 ], [ %223, %if.end.i1877 ]
-  %cond385.c = ptrtoint %struct.LIST_HELP* %cond385 to i32
-  store i32 %cond385.c, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb387:                                         ; preds = %yyreduce
-  %228 = load i32* @fol_EQUIV, align 4
-  store i32 %228, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb390:                                         ; preds = %yyreduce
-  %229 = load i32* @fol_IMPLIED, align 4
-  store i32 %229, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb393:                                         ; preds = %yyreduce
-  %230 = load i32* @fol_IMPLIES, align 4
-  store i32 %230, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb396:                                         ; preds = %yyreduce
-  %231 = load i32* @fol_AND, align 4
-  store i32 %231, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb399:                                         ; preds = %yyreduce
-  %232 = load i32* @fol_OR, align 4
-  store i32 %232, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb402:                                         ; preds = %yyreduce
-  %233 = load i32* @fol_EXIST, align 4
-  store i32 %233, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb405:                                         ; preds = %yyreduce
-  %234 = load i32* @fol_ALL, align 4
-  store i32 %234, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb408:                                         ; preds = %yyreduce
-  %235 = load i32* @dfg_IGNORE, align 4
-  %tobool409 = icmp eq i32 %235, 0
-  %string412 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %236 = load i8** %string412, align 4
-  br i1 %tobool409, label %if.else414, label %if.then410
-
-if.then410:                                       ; preds = %sw.bb408
-  call void @string_StringFree(i8* %236) #1
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-if.else414:                                       ; preds = %sw.bb408
-  %.c1746 = ptrtoint i8* %236 to i32
-  store i32 %.c1746, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb419:                                         ; preds = %yyreduce
-  %237 = load i32* @dfg_IGNORE, align 4
-  %tobool420 = icmp eq i32 %237, 0
-  br i1 %tobool420, label %cond.false422, label %cond.end426
-
-cond.false422:                                    ; preds = %sw.bb419
-  %number424 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 0, i32 0
-  %238 = load i32* %number424, align 4
-  %call425 = call i8* @string_IntToString(i32 %238) #1
-  %phitmp1745 = ptrtoint i8* %call425 to i32
-  br label %cond.end426
-
-cond.end426:                                      ; preds = %sw.bb419, %cond.false422
-  %cond427 = phi i32 [ %phitmp1745, %cond.false422 ], [ 0, %sw.bb419 ]
-  store i32 %cond427, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb429:                                         ; preds = %yyreduce
-  %239 = load i32* @dfg_IGNORE, align 4
-  %tobool430 = icmp eq i32 %239, 0
-  br i1 %tobool430, label %cond.false432, label %cond.end434
-
-cond.false432:                                    ; preds = %sw.bb429
-  %call433 = call i8* @string_StringCopy(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0)) #1
-  %phitmp1744 = ptrtoint i8* %call433 to i32
-  br label %cond.end434
-
-cond.end434:                                      ; preds = %sw.bb429, %cond.false432
-  %cond435 = phi i32 [ %phitmp1744, %cond.false432 ], [ 0, %sw.bb429 ]
-  store i32 %cond435, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb437:                                         ; preds = %yyreduce
-  %240 = load i32* @dfg_IGNORE, align 4
-  %tobool438 = icmp eq i32 %240, 0
-  br i1 %tobool438, label %cond.false440, label %cond.end442
-
-cond.false440:                                    ; preds = %sw.bb437
-  %call441 = call i8* @string_StringCopy(i8* getelementptr inbounds ([12 x i8]* @.str1, i32 0, i32 0)) #1
-  %phitmp1743 = ptrtoint i8* %call441 to i32
-  br label %cond.end442
-
-cond.end442:                                      ; preds = %sw.bb437, %cond.false440
-  %cond443 = phi i32 [ %phitmp1743, %cond.false440 ], [ 0, %sw.bb437 ]
-  store i32 %cond443, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb445:                                         ; preds = %yyreduce
-  %241 = load i32* @dfg_IGNORE, align 4
-  %tobool446 = icmp eq i32 %241, 0
-  br i1 %tobool446, label %cond.false448, label %cond.end450
-
-cond.false448:                                    ; preds = %sw.bb445
-  %call449 = call i8* @string_StringCopy(i8* getelementptr inbounds ([15 x i8]* @.str2, i32 0, i32 0)) #1
-  %phitmp1742 = ptrtoint i8* %call449 to i32
-  br label %cond.end450
-
-cond.end450:                                      ; preds = %sw.bb445, %cond.false448
-  %cond451 = phi i32 [ %phitmp1742, %cond.false448 ], [ 0, %sw.bb445 ]
-  store i32 %cond451, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb453:                                         ; preds = %yyreduce
-  %242 = load i32* @dfg_IGNORE, align 4
-  %tobool454 = icmp eq i32 %242, 0
-  br i1 %tobool454, label %cond.false457, label %cond.end461
-
-cond.false457:                                    ; preds = %sw.bb453
-  %term459 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %243 = load %struct.term** %term459, align 4
-  %244 = bitcast %struct.term* %243 to i8*
-  %call.i.i1886 = call i8* @memory_Malloc(i32 8) #1
-  %car.i.i1887 = getelementptr inbounds i8* %call.i.i1886, i32 4
-  %245 = bitcast i8* %car.i.i1887 to i8**
-  store i8* %244, i8** %245, align 4
-  %cdr.i.i1888 = bitcast i8* %call.i.i1886 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i1888, align 4
-  %phitmp1741 = ptrtoint i8* %call.i.i1886 to i32
-  br label %cond.end461
-
-cond.end461:                                      ; preds = %sw.bb453, %cond.false457
-  %cond462 = phi i32 [ %phitmp1741, %cond.false457 ], [ 0, %sw.bb453 ]
-  store i32 %cond462, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb464:                                         ; preds = %yyreduce
-  %246 = load i32* @dfg_IGNORE, align 4
-  %tobool465 = icmp eq i32 %246, 0
-  %arrayidx467 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %list468 = bitcast %union.yystype* %arrayidx467 to %struct.LIST_HELP**
-  %247 = load %struct.LIST_HELP** %list468, align 4
-  br i1 %tobool465, label %cond.false469, label %cond.end476
-
-cond.false469:                                    ; preds = %sw.bb464
-  %term473 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %248 = load %struct.term** %term473, align 4
-  %249 = bitcast %struct.term* %248 to i8*
-  %call.i.i1889 = call i8* @memory_Malloc(i32 8) #1
-  %250 = bitcast i8* %call.i.i1889 to %struct.LIST_HELP*
-  %car.i.i1890 = getelementptr inbounds i8* %call.i.i1889, i32 4
-  %251 = bitcast i8* %car.i.i1890 to i8**
-  store i8* %249, i8** %251, align 4
-  %cdr.i.i1891 = bitcast i8* %call.i.i1889 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i1891, align 4
-  %cmp.i.i1892 = icmp eq %struct.LIST_HELP* %247, null
-  br i1 %cmp.i.i1892, label %cond.end476, label %if.end.i1894
-
-if.end.i1894:                                     ; preds = %cond.false469
-  %cmp.i18.i1893 = icmp eq i8* %call.i.i1889, null
-  br i1 %cmp.i18.i1893, label %cond.end476, label %for.cond.i1899
-
-for.cond.i1899:                                   ; preds = %if.end.i1894, %for.cond.i1899
-  %List1.addr.0.i1895 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i1897, %for.cond.i1899 ], [ %247, %if.end.i1894 ]
-  %List1.addr.0.idx15.i1896 = getelementptr %struct.LIST_HELP* %List1.addr.0.i1895, i32 0, i32 0
-  %List1.addr.0.idx15.val.i1897 = load %struct.LIST_HELP** %List1.addr.0.idx15.i1896, align 4
-  %cmp.i16.i1898 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i1897, null
-  br i1 %cmp.i16.i1898, label %for.end.i1900, label %for.cond.i1899
-
-for.end.i1900:                                    ; preds = %for.cond.i1899
-  store %struct.LIST_HELP* %250, %struct.LIST_HELP** %List1.addr.0.idx15.i1896, align 4
-  br label %cond.end476
-
-cond.end476:                                      ; preds = %for.end.i1900, %if.end.i1894, %cond.false469, %sw.bb464
-  %cond477 = phi %struct.LIST_HELP* [ %247, %sw.bb464 ], [ %247, %for.end.i1900 ], [ %250, %cond.false469 ], [ %247, %if.end.i1894 ]
-  %cond477.c = ptrtoint %struct.LIST_HELP* %cond477 to i32
-  store i32 %cond477.c, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb479:                                         ; preds = %yyreduce
-  %252 = load i32* @dfg_IGNORE, align 4
-  %tobool480 = icmp eq i32 %252, 0
-  br i1 %tobool480, label %if.then481, label %sw.epilog1200
-
-if.then481:                                       ; preds = %sw.bb479
-  %string483 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %253 = load i8** %string483, align 4
-  %call484 = call fastcc i32 @dfg_Symbol(i8* %253, i32 0)
-  %cmp.i1903 = icmp sgt i32 %call484, 0
-  br i1 %cmp.i1903, label %if.end489, label %if.then487
-
-if.then487:                                       ; preds = %if.then481
-  %254 = load %struct._IO_FILE** @stdout, align 4
-  %call488 = call i32 @fflush(%struct._IO_FILE* %254) #1
-  %255 = load i32* @dfg_LINENUMBER, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([38 x i8]* @.str3, i32 0, i32 0), i32 %255) #1
-  call fastcc void @misc_Error()
-  unreachable
-
-if.end489:                                        ; preds = %if.then481
-  %call491 = call %struct.term* @term_Create(i32 %call484, %struct.LIST_HELP* null) #1
-  %call491.c = ptrtoint %struct.term* %call491 to i32
-  store i32 %call491.c, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb494:                                         ; preds = %yyreduce
-  %256 = load i32* @dfg_IGNORE, align 4
-  %tobool495 = icmp eq i32 %256, 0
-  br i1 %tobool495, label %if.then496, label %sw.epilog1200
-
-if.then496:                                       ; preds = %sw.bb494
-  %arrayidx497 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -3
-  %string498 = bitcast %union.yystype* %arrayidx497 to i8**
-  %257 = load i8** %string498, align 4
-  %call499 = call fastcc i32 @dfg_Symbol(i8* %257, i32 1)
-  %tobool.i = icmp sgt i32 %call499, -1
-  br i1 %tobool.i, label %if.then502, label %land.rhs.i
-
-land.rhs.i:                                       ; preds = %if.then496
-  %sub.i.i1904 = sub nsw i32 0, %call499
-  %and.i.i1905 = and i32 %3, %sub.i.i1904
-  %cmp.i1906 = icmp eq i32 %and.i.i1905, 2
-  br i1 %cmp.i1906, label %if.end504, label %if.then502
-
-if.then502:                                       ; preds = %if.then496, %land.rhs.i
-  %258 = load %struct._IO_FILE** @stdout, align 4
-  %call503 = call i32 @fflush(%struct._IO_FILE* %258) #1
-  %259 = load i32* @dfg_LINENUMBER, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([39 x i8]* @.str4, i32 0, i32 0), i32 %259) #1
-  call fastcc void @misc_Error()
-  unreachable
-
-if.end504:                                        ; preds = %land.rhs.i
-  %arrayidx505 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1
-  %string506 = bitcast %union.yystype* %arrayidx505 to i8**
-  %260 = load i8** %string506, align 4
-  %call507 = call fastcc i32 @dfg_Symbol(i8* %260, i32 0)
-  %cmp.i1907 = icmp sgt i32 %call507, 0
-  br i1 %cmp.i1907, label %if.end512, label %if.then510
-
-if.then510:                                       ; preds = %if.end504
-  %261 = load %struct._IO_FILE** @stdout, align 4
-  %call511 = call i32 @fflush(%struct._IO_FILE* %261) #1
-  %262 = load i32* @dfg_LINENUMBER, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([38 x i8]* @.str3, i32 0, i32 0), i32 %262) #1
-  call fastcc void @misc_Error()
-  unreachable
-
-if.end512:                                        ; preds = %if.end504
-  %call514 = call %struct.term* @term_Create(i32 %call507, %struct.LIST_HELP* null) #1
-  %263 = bitcast %struct.term* %call514 to i8*
-  %call.i.i1909 = call i8* @memory_Malloc(i32 8) #1
-  %264 = bitcast i8* %call.i.i1909 to %struct.LIST_HELP*
-  %car.i.i1910 = getelementptr inbounds i8* %call.i.i1909, i32 4
-  %265 = bitcast i8* %car.i.i1910 to i8**
-  store i8* %263, i8** %265, align 4
-  %cdr.i.i1911 = bitcast i8* %call.i.i1909 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i1911, align 4
-  %call516 = call %struct.term* @term_Create(i32 %call499, %struct.LIST_HELP* %264) #1
-  %call516.c = ptrtoint %struct.term* %call516 to i32
-  store i32 %call516.c, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb519:                                         ; preds = %yyreduce
-  %arrayidx520 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %list521 = bitcast %union.yystype* %arrayidx520 to %struct.LIST_HELP**
-  %266 = load %struct.LIST_HELP** %list521, align 4
-  %call522 = call %struct.LIST_HELP* @list_NReverse(%struct.LIST_HELP* %266) #1
-  %bool524 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -7, i32 0
-  %267 = load i32* %bool524, align 4
-  %tobool525 = icmp eq i32 %267, 0
-  br i1 %tobool525, label %if.else530, label %if.then526
-
-if.then526:                                       ; preds = %sw.bb519
-  %268 = load %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  %269 = load %struct.LIST_HELP** %list521, align 4
-  %cmp.i.i1912 = icmp eq %struct.LIST_HELP* %268, null
-  br i1 %cmp.i.i1912, label %list_Nconc.exit1922, label %if.end.i1914
-
-if.end.i1914:                                     ; preds = %if.then526
-  %cmp.i18.i1913 = icmp eq %struct.LIST_HELP* %269, null
-  br i1 %cmp.i18.i1913, label %list_Nconc.exit1922, label %for.cond.i1919
-
-for.cond.i1919:                                   ; preds = %if.end.i1914, %for.cond.i1919
-  %List1.addr.0.i1915 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i1917, %for.cond.i1919 ], [ %268, %if.end.i1914 ]
-  %List1.addr.0.idx15.i1916 = getelementptr %struct.LIST_HELP* %List1.addr.0.i1915, i32 0, i32 0
-  %List1.addr.0.idx15.val.i1917 = load %struct.LIST_HELP** %List1.addr.0.idx15.i1916, align 4
-  %cmp.i16.i1918 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i1917, null
-  br i1 %cmp.i16.i1918, label %for.end.i1920, label %for.cond.i1919
-
-for.end.i1920:                                    ; preds = %for.cond.i1919
-  store %struct.LIST_HELP* %269, %struct.LIST_HELP** %List1.addr.0.idx15.i1916, align 4
-  br label %list_Nconc.exit1922
-
-list_Nconc.exit1922:                              ; preds = %if.then526, %if.end.i1914, %for.end.i1920
-  %retval.0.i1921 = phi %struct.LIST_HELP* [ %268, %for.end.i1920 ], [ %269, %if.then526 ], [ %268, %if.end.i1914 ]
-  store %struct.LIST_HELP* %retval.0.i1921, %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  br label %sw.epilog1200
-
-if.else530:                                       ; preds = %sw.bb519
-  %270 = load %struct.LIST_HELP** @dfg_CONCLAUSES, align 4
-  %271 = load %struct.LIST_HELP** %list521, align 4
-  %cmp.i.i1923 = icmp eq %struct.LIST_HELP* %270, null
-  br i1 %cmp.i.i1923, label %list_Nconc.exit1933, label %if.end.i1925
-
-if.end.i1925:                                     ; preds = %if.else530
-  %cmp.i18.i1924 = icmp eq %struct.LIST_HELP* %271, null
-  br i1 %cmp.i18.i1924, label %list_Nconc.exit1933, label %for.cond.i1930
-
-for.cond.i1930:                                   ; preds = %if.end.i1925, %for.cond.i1930
-  %List1.addr.0.i1926 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i1928, %for.cond.i1930 ], [ %270, %if.end.i1925 ]
-  %List1.addr.0.idx15.i1927 = getelementptr %struct.LIST_HELP* %List1.addr.0.i1926, i32 0, i32 0
-  %List1.addr.0.idx15.val.i1928 = load %struct.LIST_HELP** %List1.addr.0.idx15.i1927, align 4
-  %cmp.i16.i1929 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i1928, null
-  br i1 %cmp.i16.i1929, label %for.end.i1931, label %for.cond.i1930
-
-for.end.i1931:                                    ; preds = %for.cond.i1930
-  store %struct.LIST_HELP* %271, %struct.LIST_HELP** %List1.addr.0.idx15.i1927, align 4
-  br label %list_Nconc.exit1933
-
-list_Nconc.exit1933:                              ; preds = %if.else530, %if.end.i1925, %for.end.i1931
-  %retval.0.i1932 = phi %struct.LIST_HELP* [ %270, %for.end.i1931 ], [ %271, %if.else530 ], [ %270, %if.end.i1925 ]
-  store %struct.LIST_HELP* %retval.0.i1932, %struct.LIST_HELP** @dfg_CONCLAUSES, align 4
-  br label %sw.epilog1200
-
-sw.bb535:                                         ; preds = %yyreduce
-  %272 = load i32* @dfg_IGNORE, align 4
-  %273 = inttoptr i32 %272 to i8*
-  %274 = load i32* @stack_POINTER, align 4
-  %inc.i = add i32 %274, 1
-  store i32 %inc.i, i32* @stack_POINTER, align 4
-  %arrayidx.i = getelementptr inbounds [10000 x i8*]* @stack_STACK, i32 0, i32 %274
-  store i8* %273, i8** %arrayidx.i, align 4
-  store i32 1, i32* @dfg_IGNORE, align 4
-  br label %sw.epilog1200
-
-sw.bb536:                                         ; preds = %yyreduce
-  %275 = load i32* @stack_POINTER, align 4
-  %dec.i = add i32 %275, -1
-  store i32 %dec.i, i32* @stack_POINTER, align 4
-  %arrayidx.i1934 = getelementptr inbounds [10000 x i8*]* @stack_STACK, i32 0, i32 %dec.i
-  %276 = load i8** %arrayidx.i1934, align 4
-  %277 = ptrtoint i8* %276 to i32
-  store i32 %277, i32* @dfg_IGNORE, align 4
-  br label %sw.epilog1200
-
-sw.bb538:                                         ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb541:                                         ; preds = %yyreduce
-  %arrayidx543 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -3
-  %term544 = bitcast %union.yystype* %arrayidx543 to %struct.term**
-  %278 = load %struct.term** %term544, align 4
-  %cmp545 = icmp eq %struct.term* %278, null
-  %arrayidx548 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %string549 = bitcast %union.yystype* %arrayidx548 to i8**
-  %279 = load i8** %string549, align 4
-  br i1 %cmp545, label %if.then547, label %if.else559
-
-if.then547:                                       ; preds = %sw.bb541
-  %cmp550 = icmp eq i8* %279, null
-  br i1 %cmp550, label %if.end555, label %if.then552
-
-if.then552:                                       ; preds = %if.then547
-  call void @string_StringFree(i8* %279) #1
-  br label %if.end555
-
-if.end555:                                        ; preds = %if.then547, %if.then552
-  %arrayidx556 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -6
-  %list557 = bitcast %union.yystype* %arrayidx556 to %struct.LIST_HELP**
-  %280 = load %struct.LIST_HELP** %list557, align 4
-  %.c1740 = ptrtoint %struct.LIST_HELP* %280 to i32
-  br label %if.end569
-
-if.else559:                                       ; preds = %sw.bb541
-  %281 = bitcast %struct.term* %278 to %struct.LIST_HELP*
-  %call.i.i1935 = call i8* @memory_Malloc(i32 8) #1
-  %car.i.i1936 = getelementptr inbounds i8* %call.i.i1935, i32 4
-  %282 = bitcast i8* %car.i.i1936 to i8**
-  store i8* %279, i8** %282, align 4
-  %cdr.i.i1937 = bitcast i8* %call.i.i1935 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %281, %struct.LIST_HELP** %cdr.i.i1937, align 4
-  %arrayidx565 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -6
-  %list566 = bitcast %union.yystype* %arrayidx565 to %struct.LIST_HELP**
-  %283 = load %struct.LIST_HELP** %list566, align 4
-  %call.i1938 = call i8* @memory_Malloc(i32 8) #1
-  %car.i1939 = getelementptr inbounds i8* %call.i1938, i32 4
-  %284 = bitcast i8* %car.i1939 to i8**
-  store i8* %call.i.i1935, i8** %284, align 4
-  %cdr.i1940 = bitcast i8* %call.i1938 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %283, %struct.LIST_HELP** %cdr.i1940, align 4
-  %call567.c = ptrtoint i8* %call.i1938 to i32
-  br label %if.end569
-
-if.end569:                                        ; preds = %if.else559, %if.end555
-  %storemerge = phi i32 [ %call567.c, %if.else559 ], [ %.c1740, %if.end555 ]
-  store i32 %storemerge, i32* %2, align 4
-  %285 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %cmp.i.i1941 = icmp eq %struct.LIST_HELP* %285, null
-  br i1 %cmp.i.i1941, label %dfg_VarCheck.exit1946, label %if.then.i1944
-
-if.then.i1944:                                    ; preds = %if.end569
-  %286 = load %struct._IO_FILE** @stdout, align 4
-  %call1.i1942 = call i32 @fflush(%struct._IO_FILE* %286) #1
-  %287 = load %struct._IO_FILE** @stderr, align 4
-  %call2.i1943 = call i32 (%struct._IO_FILE*, i8*, ...)* @fprintf(%struct._IO_FILE* %287, i8* getelementptr inbounds ([31 x i8]* @.str27, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str28, i32 0, i32 0), i32 1881) #1
-  call void (i8*, ...)* @misc_ErrorReport(i8* getelementptr inbounds ([55 x i8]* @.str41, i32 0, i32 0)) #1
-  %288 = load %struct._IO_FILE** @stderr, align 4
-  %289 = call i32 @fwrite(i8* getelementptr inbounds ([133 x i8]* @.str30, i32 0, i32 0), i32 132, i32 1, %struct._IO_FILE* %288) #1
-  call fastcc void @misc_DumpCore() #1
-  unreachable
-
-dfg_VarCheck.exit1946:                            ; preds = %if.end569
-  store i32 0, i32* @symbol_STANDARDVARCOUNTER, align 4
-  br label %sw.epilog1200
-
-sw.bb570:                                         ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb572:                                         ; preds = %yyreduce
-  %term574 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %290 = load %struct.term** %term574, align 4
-  %.c1739 = ptrtoint %struct.term* %290 to i32
-  store i32 %.c1739, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb576:                                         ; preds = %yyreduce
-  %term578 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %291 = load %struct.term** %term578, align 4
-  %.c1738 = ptrtoint %struct.term* %291 to i32
-  store i32 %.c1738, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb580:                                         ; preds = %yyreduce
-  %292 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %call.i.i.i1947 = call i8* @memory_Malloc(i32 8) #1
-  %293 = bitcast i8* %call.i.i.i1947 to %struct.LIST_HELP*
-  %car.i.i.i1948 = getelementptr inbounds i8* %call.i.i.i1947, i32 4
-  %294 = bitcast i8* %car.i.i.i1948 to i8**
-  store i8* null, i8** %294, align 4
-  %cdr.i.i.i1949 = bitcast i8* %call.i.i.i1947 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %292, %struct.LIST_HELP** %cdr.i.i.i1949, align 4
-  store %struct.LIST_HELP* %293, %struct.LIST_HELP** @dfg_VARLIST, align 4
-  store i1 true, i1* @dfg_VARDECL, align 1
-  br label %sw.epilog1200
-
-sw.bb581:                                         ; preds = %yyreduce
-  store i1 false, i1* @dfg_VARDECL, align 1
-  br label %sw.epilog1200
-
-sw.bb582:                                         ; preds = %yyreduce
-  %295 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %.idx.i1950 = getelementptr %struct.LIST_HELP* %295, i32 0, i32 1
-  %.idx.val.i1951 = load i8** %.idx.i1950, align 4
-  %296 = bitcast i8* %.idx.val.i1951 to %struct.LIST_HELP*
-  call void @list_DeleteWithElement(%struct.LIST_HELP* %296, void (i8*)* bitcast (void (%struct.DFG_VARENTRY*)* @dfg_VarFree to void (i8*)*)) #1
-  %297 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %L.idx.i.i1952 = getelementptr %struct.LIST_HELP* %297, i32 0, i32 0
-  %L.idx.val.i.i1953 = load %struct.LIST_HELP** %L.idx.i.i1952, align 4
-  %298 = bitcast %struct.LIST_HELP* %297 to i8*
-  %299 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i1954 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %299, i32 0, i32 4
-  %300 = load i32* %total_size.i.i.i.i1954, align 4
-  %301 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i1955 = add i32 %301, %300
-  store i32 %add24.i.i.i.i1955, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i1956 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %299, i32 0, i32 0
-  %302 = load i8** %free.i.i.i.i1956, align 4
-  %.c.i.i.i1957 = bitcast i8* %302 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i1957, %struct.LIST_HELP** %L.idx.i.i1952, align 4
-  %303 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i1958 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %303, i32 0, i32 0
-  store i8* %298, i8** %free27.i.i.i.i1958, align 4
-  store %struct.LIST_HELP* %L.idx.val.i.i1953, %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %304 = load i32* @dfg_IGNORE, align 4
-  %tobool583 = icmp eq i32 %304, 0
-  br i1 %tobool583, label %cond.false585, label %cond.end592
-
-cond.false585:                                    ; preds = %sw.bb582
-  %305 = load i32* @fol_ALL, align 4
-  %arrayidx587 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -5
-  %list588 = bitcast %union.yystype* %arrayidx587 to %struct.LIST_HELP**
-  %306 = load %struct.LIST_HELP** %list588, align 4
-  %arrayidx589 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1
-  %term590 = bitcast %union.yystype* %arrayidx589 to %struct.term**
-  %307 = load %struct.term** %term590, align 4
-  %call591 = call %struct.term* @dfg_CreateQuantifier(i32 %305, %struct.LIST_HELP* %306, %struct.term* %307)
-  %phitmp1737 = ptrtoint %struct.term* %call591 to i32
-  br label %cond.end592
-
-cond.end592:                                      ; preds = %sw.bb582, %cond.false585
-  %cond593 = phi i32 [ %phitmp1737, %cond.false585 ], [ 0, %sw.bb582 ]
-  store i32 %cond593, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb595:                                         ; preds = %yyreduce
-  %308 = load i32* @dfg_IGNORE, align 4
-  %tobool596 = icmp eq i32 %308, 0
-  br i1 %tobool596, label %cond.false598, label %cond.end603
-
-cond.false598:                                    ; preds = %sw.bb595
-  %309 = load i32* @fol_OR, align 4
-  %arrayidx600 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1
-  %list601 = bitcast %union.yystype* %arrayidx600 to %struct.LIST_HELP**
-  %310 = load %struct.LIST_HELP** %list601, align 4
-  %call602 = call %struct.term* @term_Create(i32 %309, %struct.LIST_HELP* %310) #1
-  %phitmp1736 = ptrtoint %struct.term* %call602 to i32
-  br label %cond.end603
-
-cond.end603:                                      ; preds = %sw.bb595, %cond.false598
-  %cond604 = phi i32 [ %phitmp1736, %cond.false598 ], [ 0, %sw.bb595 ]
-  store i32 %cond604, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb606:                                         ; preds = %yyreduce
-  %311 = load i32* @dfg_IGNORE, align 4
-  %tobool607 = icmp eq i32 %311, 0
-  br i1 %tobool607, label %cond.false610, label %cond.end614
-
-cond.false610:                                    ; preds = %sw.bb606
-  %term612 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %312 = load %struct.term** %term612, align 4
-  %313 = bitcast %struct.term* %312 to i8*
-  %call.i.i1959 = call i8* @memory_Malloc(i32 8) #1
-  %car.i.i1960 = getelementptr inbounds i8* %call.i.i1959, i32 4
-  %314 = bitcast i8* %car.i.i1960 to i8**
-  store i8* %313, i8** %314, align 4
-  %cdr.i.i1961 = bitcast i8* %call.i.i1959 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i1961, align 4
-  %phitmp1735 = ptrtoint i8* %call.i.i1959 to i32
-  br label %cond.end614
-
-cond.end614:                                      ; preds = %sw.bb606, %cond.false610
-  %cond615 = phi i32 [ %phitmp1735, %cond.false610 ], [ 0, %sw.bb606 ]
-  store i32 %cond615, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb617:                                         ; preds = %yyreduce
-  %315 = load i32* @dfg_IGNORE, align 4
-  %tobool618 = icmp eq i32 %315, 0
-  %arrayidx620 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %list621 = bitcast %union.yystype* %arrayidx620 to %struct.LIST_HELP**
-  %316 = load %struct.LIST_HELP** %list621, align 4
-  br i1 %tobool618, label %cond.false622, label %cond.end629
-
-cond.false622:                                    ; preds = %sw.bb617
-  %term626 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %317 = load %struct.term** %term626, align 4
-  %318 = bitcast %struct.term* %317 to i8*
-  %call.i.i1962 = call i8* @memory_Malloc(i32 8) #1
-  %319 = bitcast i8* %call.i.i1962 to %struct.LIST_HELP*
-  %car.i.i1963 = getelementptr inbounds i8* %call.i.i1962, i32 4
-  %320 = bitcast i8* %car.i.i1963 to i8**
-  store i8* %318, i8** %320, align 4
-  %cdr.i.i1964 = bitcast i8* %call.i.i1962 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i1964, align 4
-  %cmp.i.i1965 = icmp eq %struct.LIST_HELP* %316, null
-  br i1 %cmp.i.i1965, label %cond.end629, label %if.end.i1967
-
-if.end.i1967:                                     ; preds = %cond.false622
-  %cmp.i18.i1966 = icmp eq i8* %call.i.i1962, null
-  br i1 %cmp.i18.i1966, label %cond.end629, label %for.cond.i1972
-
-for.cond.i1972:                                   ; preds = %if.end.i1967, %for.cond.i1972
-  %List1.addr.0.i1968 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i1970, %for.cond.i1972 ], [ %316, %if.end.i1967 ]
-  %List1.addr.0.idx15.i1969 = getelementptr %struct.LIST_HELP* %List1.addr.0.i1968, i32 0, i32 0
-  %List1.addr.0.idx15.val.i1970 = load %struct.LIST_HELP** %List1.addr.0.idx15.i1969, align 4
-  %cmp.i16.i1971 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i1970, null
-  br i1 %cmp.i16.i1971, label %for.end.i1973, label %for.cond.i1972
-
-for.end.i1973:                                    ; preds = %for.cond.i1972
-  store %struct.LIST_HELP* %319, %struct.LIST_HELP** %List1.addr.0.idx15.i1969, align 4
-  br label %cond.end629
-
-cond.end629:                                      ; preds = %for.end.i1973, %if.end.i1967, %cond.false622, %sw.bb617
-  %cond630 = phi %struct.LIST_HELP* [ %316, %sw.bb617 ], [ %316, %for.end.i1973 ], [ %319, %cond.false622 ], [ %316, %if.end.i1967 ]
-  %cond630.c = ptrtoint %struct.LIST_HELP* %cond630 to i32
-  store i32 %cond630.c, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb632:                                         ; preds = %yyreduce
-  %term634 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %321 = load %struct.term** %term634, align 4
-  %.c1734 = ptrtoint %struct.term* %321 to i32
-  store i32 %.c1734, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb636:                                         ; preds = %yyreduce
-  %322 = load i32* @dfg_IGNORE, align 4
-  %tobool637 = icmp eq i32 %322, 0
-  br i1 %tobool637, label %cond.false641, label %cond.true638
-
-cond.true638:                                     ; preds = %sw.bb636
-  %arrayidx639 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1
-  %term640 = bitcast %union.yystype* %arrayidx639 to %struct.term**
-  %323 = load %struct.term** %term640, align 4
-  br label %cond.end647
-
-cond.false641:                                    ; preds = %sw.bb636
-  %324 = load i32* @fol_NOT, align 4
-  %arrayidx643 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1
-  %term644 = bitcast %union.yystype* %arrayidx643 to %struct.term**
-  %325 = load %struct.term** %term644, align 4
-  %326 = bitcast %struct.term* %325 to i8*
-  %call.i.i1976 = call i8* @memory_Malloc(i32 8) #1
-  %327 = bitcast i8* %call.i.i1976 to %struct.LIST_HELP*
-  %car.i.i1977 = getelementptr inbounds i8* %call.i.i1976, i32 4
-  %328 = bitcast i8* %car.i.i1977 to i8**
-  store i8* %326, i8** %328, align 4
-  %cdr.i.i1978 = bitcast i8* %call.i.i1976 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i1978, align 4
-  %call646 = call %struct.term* @term_Create(i32 %324, %struct.LIST_HELP* %327) #1
-  br label %cond.end647
-
-cond.end647:                                      ; preds = %cond.false641, %cond.true638
-  %cond648 = phi %struct.term* [ %323, %cond.true638 ], [ %call646, %cond.false641 ]
-  %cond648.c = ptrtoint %struct.term* %cond648 to i32
-  store i32 %cond648.c, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb650:                                         ; preds = %yyreduce
-  %term652 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %329 = load %struct.term** %term652, align 4
-  %330 = bitcast %struct.term* %329 to i8*
-  %call.i.i1979 = call i8* @memory_Malloc(i32 8) #1
-  %car.i.i1980 = getelementptr inbounds i8* %call.i.i1979, i32 4
-  %331 = bitcast i8* %car.i.i1980 to i8**
-  store i8* %330, i8** %331, align 4
-  %cdr.i.i1981 = bitcast i8* %call.i.i1979 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i1981, align 4
-  %call653.c = ptrtoint i8* %call.i.i1979 to i32
-  store i32 %call653.c, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb655:                                         ; preds = %yyreduce
-  %arrayidx656 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %list657 = bitcast %union.yystype* %arrayidx656 to %struct.LIST_HELP**
-  %332 = load %struct.LIST_HELP** %list657, align 4
-  %term659 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %333 = load %struct.term** %term659, align 4
-  %334 = bitcast %struct.term* %333 to i8*
-  %call.i.i1982 = call i8* @memory_Malloc(i32 8) #1
-  %335 = bitcast i8* %call.i.i1982 to %struct.LIST_HELP*
-  %car.i.i1983 = getelementptr inbounds i8* %call.i.i1982, i32 4
-  %336 = bitcast i8* %car.i.i1983 to i8**
-  store i8* %334, i8** %336, align 4
-  %cdr.i.i1984 = bitcast i8* %call.i.i1982 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i1984, align 4
-  %cmp.i.i1985 = icmp eq %struct.LIST_HELP* %332, null
-  br i1 %cmp.i.i1985, label %list_Nconc.exit1995, label %if.end.i1987
-
-if.end.i1987:                                     ; preds = %sw.bb655
-  %cmp.i18.i1986 = icmp eq i8* %call.i.i1982, null
-  br i1 %cmp.i18.i1986, label %list_Nconc.exit1995, label %for.cond.i1992
-
-for.cond.i1992:                                   ; preds = %if.end.i1987, %for.cond.i1992
-  %List1.addr.0.i1988 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i1990, %for.cond.i1992 ], [ %332, %if.end.i1987 ]
-  %List1.addr.0.idx15.i1989 = getelementptr %struct.LIST_HELP* %List1.addr.0.i1988, i32 0, i32 0
-  %List1.addr.0.idx15.val.i1990 = load %struct.LIST_HELP** %List1.addr.0.idx15.i1989, align 4
-  %cmp.i16.i1991 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i1990, null
-  br i1 %cmp.i16.i1991, label %for.end.i1993, label %for.cond.i1992
-
-for.end.i1993:                                    ; preds = %for.cond.i1992
-  store %struct.LIST_HELP* %335, %struct.LIST_HELP** %List1.addr.0.idx15.i1989, align 4
-  br label %list_Nconc.exit1995
-
-list_Nconc.exit1995:                              ; preds = %sw.bb655, %if.end.i1987, %for.end.i1993
-  %retval.0.i1994 = phi %struct.LIST_HELP* [ %332, %for.end.i1993 ], [ %335, %sw.bb655 ], [ %332, %if.end.i1987 ]
-  %call661.c = ptrtoint %struct.LIST_HELP* %retval.0.i1994 to i32
-  store i32 %call661.c, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb663:                                         ; preds = %yyreduce
-  %337 = load i32* @dfg_IGNORE, align 4
-  %tobool664 = icmp eq i32 %337, 0
-  br i1 %tobool664, label %cond.false666, label %cond.end671
-
-cond.false666:                                    ; preds = %sw.bb663
-  %string668 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %338 = load i8** %string668, align 4
-  %call.i1996 = call i32 @list_Length(%struct.LIST_HELP* null) #1
-  %call1.i1997 = call fastcc i32 @dfg_Symbol(i8* %338, i32 %call.i1996) #1
-  %tobool.i.i1998 = icmp sgt i32 %call1.i1997, -1
-  br i1 %tobool.i.i1998, label %if.then.i2002, label %land.rhs.i.i2001
-
-land.rhs.i.i2001:                                 ; preds = %cond.false666
-  %sub.i.i.i1999 = sub nsw i32 0, %call1.i1997
-  %and.i.i.i2000 = and i32 %3, %sub.i.i.i1999
-  %cmp.i10.i = icmp eq i32 %and.i.i.i2000, 2
-  br i1 %cmp.i10.i, label %dfg_AtomCreate.exit, label %if.then.i2002
-
-if.then.i2002:                                    ; preds = %land.rhs.i.i2001, %cond.false666
-  %339 = load %struct._IO_FILE** @stdout, align 4
-  %call5.i = call i32 @fflush(%struct._IO_FILE* %339) #1
-  %340 = load i32* @dfg_LINENUMBER, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([39 x i8]* @.str4, i32 0, i32 0), i32 %340) #1
-  call fastcc void @misc_Error() #1
-  unreachable
-
-dfg_AtomCreate.exit:                              ; preds = %land.rhs.i.i2001
-  %call6.i = call %struct.term* @term_Create(i32 %call1.i1997, %struct.LIST_HELP* null) #1
-  %phitmp1733 = ptrtoint %struct.term* %call6.i to i32
-  br label %cond.end671
-
-cond.end671:                                      ; preds = %sw.bb663, %dfg_AtomCreate.exit
-  %cond672 = phi i32 [ %phitmp1733, %dfg_AtomCreate.exit ], [ 0, %sw.bb663 ]
-  store i32 %cond672, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb674:                                         ; preds = %yyreduce
-  %341 = load i32* @dfg_IGNORE, align 4
-  %tobool675 = icmp eq i32 %341, 0
-  br i1 %tobool675, label %cond.false677, label %cond.end681
-
-cond.false677:                                    ; preds = %sw.bb674
-  %342 = load i32* @fol_TRUE, align 4
-  %call680 = call %struct.term* @term_Create(i32 %342, %struct.LIST_HELP* null) #1
-  %phitmp1732 = ptrtoint %struct.term* %call680 to i32
-  br label %cond.end681
-
-cond.end681:                                      ; preds = %sw.bb674, %cond.false677
-  %cond682 = phi i32 [ %phitmp1732, %cond.false677 ], [ 0, %sw.bb674 ]
-  store i32 %cond682, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb684:                                         ; preds = %yyreduce
-  %343 = load i32* @dfg_IGNORE, align 4
-  %tobool685 = icmp eq i32 %343, 0
-  br i1 %tobool685, label %cond.false687, label %cond.end691
-
-cond.false687:                                    ; preds = %sw.bb684
-  %344 = load i32* @fol_FALSE, align 4
-  %call690 = call %struct.term* @term_Create(i32 %344, %struct.LIST_HELP* null) #1
-  %phitmp1731 = ptrtoint %struct.term* %call690 to i32
-  br label %cond.end691
-
-cond.end691:                                      ; preds = %sw.bb684, %cond.false687
-  %cond692 = phi i32 [ %phitmp1731, %cond.false687 ], [ 0, %sw.bb684 ]
-  store i32 %cond692, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb694:                                         ; preds = %yyreduce
-  %345 = load i32* @dfg_IGNORE, align 4
-  %tobool695 = icmp eq i32 %345, 0
-  br i1 %tobool695, label %cond.false697, label %cond.end706
-
-cond.false697:                                    ; preds = %sw.bb694
-  %346 = load i32* @fol_EQUALITY, align 4
-  %arrayidx699 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -3
-  %term700 = bitcast %union.yystype* %arrayidx699 to %struct.term**
-  %347 = load %struct.term** %term700, align 4
-  %348 = bitcast %struct.term* %347 to i8*
-  %arrayidx701 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1
-  %term702 = bitcast %union.yystype* %arrayidx701 to %struct.term**
-  %349 = load %struct.term** %term702, align 4
-  %350 = bitcast %struct.term* %349 to i8*
-  %call.i.i2004 = call i8* @memory_Malloc(i32 8) #1
-  %351 = bitcast i8* %call.i.i2004 to %struct.LIST_HELP*
-  %car.i.i2005 = getelementptr inbounds i8* %call.i.i2004, i32 4
-  %352 = bitcast i8* %car.i.i2005 to i8**
-  store i8* %350, i8** %352, align 4
-  %cdr.i.i2006 = bitcast i8* %call.i.i2004 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i2006, align 4
-  %call.i2007 = call i8* @memory_Malloc(i32 8) #1
-  %353 = bitcast i8* %call.i2007 to %struct.LIST_HELP*
-  %car.i2008 = getelementptr inbounds i8* %call.i2007, i32 4
-  %354 = bitcast i8* %car.i2008 to i8**
-  store i8* %348, i8** %354, align 4
-  %cdr.i2009 = bitcast i8* %call.i2007 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %351, %struct.LIST_HELP** %cdr.i2009, align 4
-  %call705 = call %struct.term* @term_Create(i32 %346, %struct.LIST_HELP* %353) #1
-  %phitmp1730 = ptrtoint %struct.term* %call705 to i32
-  br label %cond.end706
-
-cond.end706:                                      ; preds = %sw.bb694, %cond.false697
-  %cond707 = phi i32 [ %phitmp1730, %cond.false697 ], [ 0, %sw.bb694 ]
-  store i32 %cond707, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb709:                                         ; preds = %yyreduce
-  %355 = load i32* @dfg_IGNORE, align 4
-  %tobool710 = icmp eq i32 %355, 0
-  br i1 %tobool710, label %cond.false712, label %cond.end718
-
-cond.false712:                                    ; preds = %sw.bb709
-  %arrayidx713 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -3
-  %string714 = bitcast %union.yystype* %arrayidx713 to i8**
-  %356 = load i8** %string714, align 4
-  %arrayidx715 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1
-  %list716 = bitcast %union.yystype* %arrayidx715 to %struct.LIST_HELP**
-  %357 = load %struct.LIST_HELP** %list716, align 4
-  %call.i2010 = call i32 @list_Length(%struct.LIST_HELP* %357) #1
-  %call1.i2011 = call fastcc i32 @dfg_Symbol(i8* %356, i32 %call.i2010) #1
-  %tobool.i.i2012 = icmp sgt i32 %call1.i2011, -1
-  br i1 %tobool.i.i2012, label %if.then.i2018, label %land.rhs.i.i2016
-
-land.rhs.i.i2016:                                 ; preds = %cond.false712
-  %sub.i.i.i2013 = sub nsw i32 0, %call1.i2011
-  %and.i.i.i2014 = and i32 %3, %sub.i.i.i2013
-  %cmp.i10.i2015 = icmp eq i32 %and.i.i.i2014, 2
-  br i1 %cmp.i10.i2015, label %dfg_AtomCreate.exit2021, label %if.then.i2018
-
-if.then.i2018:                                    ; preds = %land.rhs.i.i2016, %cond.false712
-  %358 = load %struct._IO_FILE** @stdout, align 4
-  %call5.i2017 = call i32 @fflush(%struct._IO_FILE* %358) #1
-  %359 = load i32* @dfg_LINENUMBER, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([39 x i8]* @.str4, i32 0, i32 0), i32 %359) #1
-  call fastcc void @misc_Error() #1
-  unreachable
-
-dfg_AtomCreate.exit2021:                          ; preds = %land.rhs.i.i2016
-  %call6.i2019 = call %struct.term* @term_Create(i32 %call1.i2011, %struct.LIST_HELP* %357) #1
-  %phitmp1729 = ptrtoint %struct.term* %call6.i2019 to i32
-  br label %cond.end718
-
-cond.end718:                                      ; preds = %sw.bb709, %dfg_AtomCreate.exit2021
-  %cond719 = phi i32 [ %phitmp1729, %dfg_AtomCreate.exit2021 ], [ 0, %sw.bb709 ]
-  store i32 %cond719, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb721:                                         ; preds = %yyreduce
-  %360 = load i32* @dfg_IGNORE, align 4
-  %tobool722 = icmp eq i32 %360, 0
-  br i1 %tobool722, label %cond.false724, label %cond.end729
-
-cond.false724:                                    ; preds = %sw.bb721
-  %string726 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %361 = load i8** %string726, align 4
-  %call.i2022 = call i32 @list_Length(%struct.LIST_HELP* null) #1
-  %call1.i2023 = call fastcc i32 @dfg_Symbol(i8* %361, i32 %call.i2022) #1
-  %cmp.i.i2024 = icmp sgt i32 %call1.i2023, 0
-  br i1 %cmp.i.i2024, label %dfg_TermCreate.exit, label %land.lhs.true.i
-
-land.lhs.true.i:                                  ; preds = %cond.false724
-  %tobool.i.i2025 = icmp sgt i32 %call1.i2023, -1
-  br i1 %tobool.i.i2025, label %if.then.i2030, label %land.rhs.i.i2028
-
-land.rhs.i.i2028:                                 ; preds = %land.lhs.true.i
-  %sub.i6.i.i2026 = sub nsw i32 0, %call1.i2023
-  %and.i7.i.i2027 = and i32 %3, %sub.i6.i.i2026
-  %362 = icmp ult i32 %and.i7.i.i2027, 2
-  br i1 %362, label %dfg_TermCreate.exit, label %if.then.i2030
-
-if.then.i2030:                                    ; preds = %land.rhs.i.i2028, %land.lhs.true.i
-  %363 = load %struct._IO_FILE** @stdout, align 4
-  %call5.i2029 = call i32 @fflush(%struct._IO_FILE* %363) #1
-  %364 = load i32* @dfg_LINENUMBER, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([31 x i8]* @.str233, i32 0, i32 0), i32 %364) #1
-  call fastcc void @misc_Error() #1
-  unreachable
-
-dfg_TermCreate.exit:                              ; preds = %cond.false724, %land.rhs.i.i2028
-  %call6.i2031 = call %struct.term* @term_Create(i32 %call1.i2023, %struct.LIST_HELP* null) #1
-  %phitmp1728 = ptrtoint %struct.term* %call6.i2031 to i32
-  br label %cond.end729
-
-cond.end729:                                      ; preds = %sw.bb721, %dfg_TermCreate.exit
-  %cond730 = phi i32 [ %phitmp1728, %dfg_TermCreate.exit ], [ 0, %sw.bb721 ]
-  store i32 %cond730, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb732:                                         ; preds = %yyreduce
-  %365 = load i32* @dfg_IGNORE, align 4
-  %tobool733 = icmp eq i32 %365, 0
-  br i1 %tobool733, label %cond.false735, label %cond.end741
-
-cond.false735:                                    ; preds = %sw.bb732
-  %arrayidx736 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -3
-  %string737 = bitcast %union.yystype* %arrayidx736 to i8**
-  %366 = load i8** %string737, align 4
-  %arrayidx738 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1
-  %list739 = bitcast %union.yystype* %arrayidx738 to %struct.LIST_HELP**
-  %367 = load %struct.LIST_HELP** %list739, align 4
-  %call.i2033 = call i32 @list_Length(%struct.LIST_HELP* %367) #1
-  %call1.i2034 = call fastcc i32 @dfg_Symbol(i8* %366, i32 %call.i2033) #1
-  %cmp.i.i2035 = icmp sgt i32 %call1.i2034, 0
-  br i1 %cmp.i.i2035, label %dfg_TermCreate.exit2045, label %land.lhs.true.i2037
-
-land.lhs.true.i2037:                              ; preds = %cond.false735
-  %tobool.i.i2036 = icmp sgt i32 %call1.i2034, -1
-  br i1 %tobool.i.i2036, label %if.then.i2042, label %land.rhs.i.i2040
-
-land.rhs.i.i2040:                                 ; preds = %land.lhs.true.i2037
-  %sub.i6.i.i2038 = sub nsw i32 0, %call1.i2034
-  %and.i7.i.i2039 = and i32 %3, %sub.i6.i.i2038
-  %368 = icmp ult i32 %and.i7.i.i2039, 2
-  br i1 %368, label %dfg_TermCreate.exit2045, label %if.then.i2042
-
-if.then.i2042:                                    ; preds = %land.rhs.i.i2040, %land.lhs.true.i2037
-  %369 = load %struct._IO_FILE** @stdout, align 4
-  %call5.i2041 = call i32 @fflush(%struct._IO_FILE* %369) #1
-  %370 = load i32* @dfg_LINENUMBER, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([31 x i8]* @.str233, i32 0, i32 0), i32 %370) #1
-  call fastcc void @misc_Error() #1
-  unreachable
-
-dfg_TermCreate.exit2045:                          ; preds = %cond.false735, %land.rhs.i.i2040
-  %call6.i2043 = call %struct.term* @term_Create(i32 %call1.i2034, %struct.LIST_HELP* %367) #1
-  %phitmp1727 = ptrtoint %struct.term* %call6.i2043 to i32
-  br label %cond.end741
-
-cond.end741:                                      ; preds = %sw.bb732, %dfg_TermCreate.exit2045
-  %cond742 = phi i32 [ %phitmp1727, %dfg_TermCreate.exit2045 ], [ 0, %sw.bb732 ]
-  store i32 %cond742, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb744:                                         ; preds = %yyreduce
-  %371 = load i32* @dfg_IGNORE, align 4
-  %tobool745 = icmp eq i32 %371, 0
-  br i1 %tobool745, label %cond.false748, label %cond.end752
-
-cond.false748:                                    ; preds = %sw.bb744
-  %term750 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %372 = load %struct.term** %term750, align 4
-  %373 = bitcast %struct.term* %372 to i8*
-  %call.i.i2046 = call i8* @memory_Malloc(i32 8) #1
-  %car.i.i2047 = getelementptr inbounds i8* %call.i.i2046, i32 4
-  %374 = bitcast i8* %car.i.i2047 to i8**
-  store i8* %373, i8** %374, align 4
-  %cdr.i.i2048 = bitcast i8* %call.i.i2046 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i2048, align 4
-  %phitmp1726 = ptrtoint i8* %call.i.i2046 to i32
-  br label %cond.end752
-
-cond.end752:                                      ; preds = %sw.bb744, %cond.false748
-  %cond753 = phi i32 [ %phitmp1726, %cond.false748 ], [ 0, %sw.bb744 ]
-  store i32 %cond753, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb755:                                         ; preds = %yyreduce
-  %375 = load i32* @dfg_IGNORE, align 4
-  %tobool756 = icmp eq i32 %375, 0
-  %arrayidx758 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %list759 = bitcast %union.yystype* %arrayidx758 to %struct.LIST_HELP**
-  %376 = load %struct.LIST_HELP** %list759, align 4
-  br i1 %tobool756, label %cond.false760, label %cond.end767
-
-cond.false760:                                    ; preds = %sw.bb755
-  %term764 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %377 = load %struct.term** %term764, align 4
-  %378 = bitcast %struct.term* %377 to i8*
-  %call.i.i2049 = call i8* @memory_Malloc(i32 8) #1
-  %379 = bitcast i8* %call.i.i2049 to %struct.LIST_HELP*
-  %car.i.i2050 = getelementptr inbounds i8* %call.i.i2049, i32 4
-  %380 = bitcast i8* %car.i.i2050 to i8**
-  store i8* %378, i8** %380, align 4
-  %cdr.i.i2051 = bitcast i8* %call.i.i2049 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i2051, align 4
-  %cmp.i.i2052 = icmp eq %struct.LIST_HELP* %376, null
-  br i1 %cmp.i.i2052, label %cond.end767, label %if.end.i2054
-
-if.end.i2054:                                     ; preds = %cond.false760
-  %cmp.i18.i2053 = icmp eq i8* %call.i.i2049, null
-  br i1 %cmp.i18.i2053, label %cond.end767, label %for.cond.i2059
-
-for.cond.i2059:                                   ; preds = %if.end.i2054, %for.cond.i2059
-  %List1.addr.0.i2055 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i2057, %for.cond.i2059 ], [ %376, %if.end.i2054 ]
-  %List1.addr.0.idx15.i2056 = getelementptr %struct.LIST_HELP* %List1.addr.0.i2055, i32 0, i32 0
-  %List1.addr.0.idx15.val.i2057 = load %struct.LIST_HELP** %List1.addr.0.idx15.i2056, align 4
-  %cmp.i16.i2058 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i2057, null
-  br i1 %cmp.i16.i2058, label %for.end.i2060, label %for.cond.i2059
-
-for.end.i2060:                                    ; preds = %for.cond.i2059
-  store %struct.LIST_HELP* %379, %struct.LIST_HELP** %List1.addr.0.idx15.i2056, align 4
-  br label %cond.end767
-
-cond.end767:                                      ; preds = %for.end.i2060, %if.end.i2054, %cond.false760, %sw.bb755
-  %cond768 = phi %struct.LIST_HELP* [ %376, %sw.bb755 ], [ %376, %for.end.i2060 ], [ %379, %cond.false760 ], [ %376, %if.end.i2054 ]
-  %cond768.c = ptrtoint %struct.LIST_HELP* %cond768 to i32
-  store i32 %cond768.c, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb770:                                         ; preds = %yyreduce
-  %arrayidx771 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %string772 = bitcast %union.yystype* %arrayidx771 to i8**
-  %381 = load i8** %string772, align 4
-  %call.i2063 = call i32 @strcmp(i8* %381, i8* getelementptr inbounds ([6 x i8]* @.str5, i32 0, i32 0)) #1
-  %cmp.i2064 = icmp eq i32 %call.i2063, 0
-  br i1 %cmp.i2064, label %sw.epilog1200, label %if.then775
-
-if.then775:                                       ; preds = %sw.bb770
-  %382 = load i32* @dfg_IGNORE, align 4
-  %383 = inttoptr i32 %382 to i8*
-  %384 = load i32* @stack_POINTER, align 4
-  %inc.i2066 = add i32 %384, 1
-  store i32 %inc.i2066, i32* @stack_POINTER, align 4
-  %arrayidx.i2067 = getelementptr inbounds [10000 x i8*]* @stack_STACK, i32 0, i32 %384
-  store i8* %383, i8** %arrayidx.i2067, align 4
-  store i32 1, i32* @dfg_IGNORE, align 4
-  br label %sw.epilog1200
-
-sw.bb777:                                         ; preds = %yyreduce
-  %arrayidx778 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -6
-  %string779 = bitcast %union.yystype* %arrayidx778 to i8**
-  %385 = load i8** %string779, align 4
-  %call.i2068 = call i32 @strcmp(i8* %385, i8* getelementptr inbounds ([6 x i8]* @.str5, i32 0, i32 0)) #1
-  %cmp.i2069 = icmp eq i32 %call.i2068, 0
-  br i1 %cmp.i2069, label %if.end784, label %if.then782
-
-if.then782:                                       ; preds = %sw.bb777
-  %386 = load i32* @stack_POINTER, align 4
-  %dec.i2071 = add i32 %386, -1
-  store i32 %dec.i2071, i32* @stack_POINTER, align 4
-  %arrayidx.i2072 = getelementptr inbounds [10000 x i8*]* @stack_STACK, i32 0, i32 %dec.i2071
-  %387 = load i8** %arrayidx.i2072, align 4
-  %388 = ptrtoint i8* %387 to i32
-  store i32 %388, i32* @dfg_IGNORE, align 4
-  %.pre = load i8** %string779, align 4
-  br label %if.end784
-
-if.end784:                                        ; preds = %sw.bb777, %if.then782
-  %389 = phi i8* [ %385, %sw.bb777 ], [ %.pre, %if.then782 ]
-  call void @string_StringFree(i8* %389) #1
-  br label %sw.epilog1200
-
-sw.bb787:                                         ; preds = %yyreduce
-  %390 = load i32* @dfg_IGNORE, align 4
-  %tobool788 = icmp eq i32 %390, 0
-  %arrayidx789 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -11
-  %string790 = bitcast %union.yystype* %arrayidx789 to i8**
-  %391 = load i8** %string790, align 4
-  br i1 %tobool788, label %land.lhs.true, label %if.else823
-
-land.lhs.true:                                    ; preds = %sw.bb787
-  %cmp791 = icmp eq i8* %391, null
-  br i1 %cmp791, label %if.end831, label %land.lhs.true793
-
-land.lhs.true793:                                 ; preds = %land.lhs.true
-  %arrayidx794 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -9
-  %term795 = bitcast %union.yystype* %arrayidx794 to %struct.term**
-  %392 = load %struct.term** %term795, align 4
-  %cmp796 = icmp eq %struct.term* %392, null
-  br i1 %cmp796, label %if.then828, label %land.lhs.true798
-
-land.lhs.true798:                                 ; preds = %land.lhs.true793
-  %arrayidx799 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -4
-  %list800 = bitcast %union.yystype* %arrayidx799 to %struct.LIST_HELP**
-  %393 = load %struct.LIST_HELP** %list800, align 4
-  %cmp.i2073 = icmp eq %struct.LIST_HELP* %393, null
-  br i1 %cmp.i2073, label %if.else823, label %if.then803
-
-if.then803:                                       ; preds = %land.lhs.true798
-  %arrayidx804 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -7
-  %string805 = bitcast %union.yystype* %arrayidx804 to i8**
-  %394 = load i8** %string805, align 4
-  %call806 = call i32 @clause_GetOriginFromString(i8* %394) #1
-  %395 = load i8** %string805, align 4
-  call void @string_StringFree(i8* %395) #1
-  %number810 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2, i32 0
-  %396 = load i32* %number810, align 4
-  %397 = inttoptr i32 %396 to i8*
-  %398 = inttoptr i32 %call806 to i8*
-  %call.i.i2075 = call i8* @memory_Malloc(i32 8) #1
-  %399 = bitcast i8* %call.i.i2075 to %struct.LIST_HELP*
-  %car.i.i2076 = getelementptr inbounds i8* %call.i.i2075, i32 4
-  %400 = bitcast i8* %car.i.i2076 to i8**
-  store i8* %398, i8** %400, align 4
-  %cdr.i.i2077 = bitcast i8* %call.i.i2075 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i2077, align 4
-  %call.i2078 = call i8* @memory_Malloc(i32 8) #1
-  %401 = bitcast i8* %call.i2078 to %struct.LIST_HELP*
-  %car.i2079 = getelementptr inbounds i8* %call.i2078, i32 4
-  %402 = bitcast i8* %car.i2079 to i8**
-  store i8* %397, i8** %402, align 4
-  %cdr.i2080 = bitcast i8* %call.i2078 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %399, %struct.LIST_HELP** %cdr.i2080, align 4
-  %403 = load i8** %string790, align 4
-  %404 = load %struct.term** %term795, align 4
-  %405 = bitcast %struct.term* %404 to i8*
-  %406 = load %struct.LIST_HELP** %list800, align 4
-  %407 = bitcast %struct.LIST_HELP* %406 to i8*
-  %call.i2081 = call i8* @memory_Malloc(i32 8) #1
-  %408 = bitcast i8* %call.i2081 to %struct.LIST_HELP*
-  %car.i2082 = getelementptr inbounds i8* %call.i2081, i32 4
-  %409 = bitcast i8* %car.i2082 to i8**
-  store i8* %407, i8** %409, align 4
-  %cdr.i2083 = bitcast i8* %call.i2081 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %401, %struct.LIST_HELP** %cdr.i2083, align 4
-  %call.i2084 = call i8* @memory_Malloc(i32 8) #1
-  %410 = bitcast i8* %call.i2084 to %struct.LIST_HELP*
-  %car.i2085 = getelementptr inbounds i8* %call.i2084, i32 4
-  %411 = bitcast i8* %car.i2085 to i8**
-  store i8* %405, i8** %411, align 4
-  %cdr.i2086 = bitcast i8* %call.i2084 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %408, %struct.LIST_HELP** %cdr.i2086, align 4
-  %call.i2087 = call i8* @memory_Malloc(i32 8) #1
-  %car.i2088 = getelementptr inbounds i8* %call.i2087, i32 4
-  %412 = bitcast i8* %car.i2088 to i8**
-  store i8* %403, i8** %412, align 4
-  %cdr.i2089 = bitcast i8* %call.i2087 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %410, %struct.LIST_HELP** %cdr.i2089, align 4
-  %413 = load %struct.LIST_HELP** @dfg_PROOFLIST, align 4
-  %call.i2090 = call i8* @memory_Malloc(i32 8) #1
-  %414 = bitcast i8* %call.i2090 to %struct.LIST_HELP*
-  %car.i2091 = getelementptr inbounds i8* %call.i2090, i32 4
-  %415 = bitcast i8* %car.i2091 to i8**
-  store i8* %call.i2087, i8** %415, align 4
-  %cdr.i2092 = bitcast i8* %call.i2090 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %413, %struct.LIST_HELP** %cdr.i2092, align 4
-  store %struct.LIST_HELP* %414, %struct.LIST_HELP** @dfg_PROOFLIST, align 4
-  br label %if.end850
-
-if.else823:                                       ; preds = %sw.bb787, %land.lhs.true798
-  %cmp826 = icmp eq i8* %391, null
-  br i1 %cmp826, label %if.end831, label %if.then828
-
-if.then828:                                       ; preds = %land.lhs.true793, %if.else823
-  call void @string_StringFree(i8* %391) #1
-  br label %if.end831
-
-if.end831:                                        ; preds = %land.lhs.true, %if.else823, %if.then828
-  %arrayidx832 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -9
-  %term833 = bitcast %union.yystype* %arrayidx832 to %struct.term**
-  %416 = load %struct.term** %term833, align 4
-  %cmp834 = icmp eq %struct.term* %416, null
-  br i1 %cmp834, label %if.end839, label %if.then836
-
-if.then836:                                       ; preds = %if.end831
-  call void @term_Delete(%struct.term* %416) #1
-  br label %if.end839
-
-if.end839:                                        ; preds = %if.end831, %if.then836
-  %arrayidx840 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -7
-  %string841 = bitcast %union.yystype* %arrayidx840 to i8**
-  %417 = load i8** %string841, align 4
-  %cmp842 = icmp eq i8* %417, null
-  br i1 %cmp842, label %if.end847, label %if.then844
-
-if.then844:                                       ; preds = %if.end839
-  call void @string_StringFree(i8* %417) #1
-  br label %if.end847
-
-if.end847:                                        ; preds = %if.end839, %if.then844
-  %arrayidx848 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -4
-  %list849 = bitcast %union.yystype* %arrayidx848 to %struct.LIST_HELP**
-  %418 = load %struct.LIST_HELP** %list849, align 4
-  call void @list_DeleteWithElement(%struct.LIST_HELP* %418, void (i8*)* @string_StringFree) #1
-  br label %if.end850
-
-if.end850:                                        ; preds = %if.end847, %if.then803
-  %419 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %cmp.i.i2093 = icmp eq %struct.LIST_HELP* %419, null
-  br i1 %cmp.i.i2093, label %dfg_VarCheck.exit2098, label %if.then.i2096
-
-if.then.i2096:                                    ; preds = %if.end850
-  %420 = load %struct._IO_FILE** @stdout, align 4
-  %call1.i2094 = call i32 @fflush(%struct._IO_FILE* %420) #1
-  %421 = load %struct._IO_FILE** @stderr, align 4
-  %call2.i2095 = call i32 (%struct._IO_FILE*, i8*, ...)* @fprintf(%struct._IO_FILE* %421, i8* getelementptr inbounds ([31 x i8]* @.str27, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str28, i32 0, i32 0), i32 1881) #1
-  call void (i8*, ...)* @misc_ErrorReport(i8* getelementptr inbounds ([55 x i8]* @.str41, i32 0, i32 0)) #1
-  %422 = load %struct._IO_FILE** @stderr, align 4
-  %423 = call i32 @fwrite(i8* getelementptr inbounds ([133 x i8]* @.str30, i32 0, i32 0), i32 132, i32 1, %struct._IO_FILE* %422) #1
-  call fastcc void @misc_DumpCore() #1
-  unreachable
-
-dfg_VarCheck.exit2098:                            ; preds = %if.end850
-  store i32 0, i32* @symbol_STANDARDVARCOUNTER, align 4
-  br label %sw.epilog1200
-
-sw.bb851:                                         ; preds = %yyreduce
-  %424 = load i32* @dfg_IGNORE, align 4
-  %tobool852 = icmp eq i32 %424, 0
-  br i1 %tobool852, label %lor.lhs.false853, label %cond.end864
-
-lor.lhs.false853:                                 ; preds = %sw.bb851
-  %string855 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %425 = load i8** %string855, align 4
-  %cmp856 = icmp eq i8* %425, null
-  br i1 %cmp856, label %cond.end864, label %cond.false860
-
-cond.false860:                                    ; preds = %lor.lhs.false853
-  %call.i.i2099 = call i8* @memory_Malloc(i32 8) #1
-  %car.i.i2100 = getelementptr inbounds i8* %call.i.i2099, i32 4
-  %426 = bitcast i8* %car.i.i2100 to i8**
-  store i8* %425, i8** %426, align 4
-  %cdr.i.i2101 = bitcast i8* %call.i.i2099 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i2101, align 4
-  %phitmp = ptrtoint i8* %call.i.i2099 to i32
-  br label %cond.end864
-
-cond.end864:                                      ; preds = %lor.lhs.false853, %sw.bb851, %cond.false860
-  %cond865 = phi i32 [ %phitmp, %cond.false860 ], [ 0, %sw.bb851 ], [ 0, %lor.lhs.false853 ]
-  store i32 %cond865, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb867:                                         ; preds = %yyreduce
-  %427 = load i32* @dfg_IGNORE, align 4
-  %tobool868 = icmp eq i32 %427, 0
-  br i1 %tobool868, label %lor.lhs.false869, label %cond.true874
-
-lor.lhs.false869:                                 ; preds = %sw.bb867
-  %string871 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %428 = load i8** %string871, align 4
-  %cmp872 = icmp eq i8* %428, null
-  br i1 %cmp872, label %cond.true874, label %cond.false877
-
-cond.true874:                                     ; preds = %sw.bb867, %lor.lhs.false869
-  %arrayidx875 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %list876 = bitcast %union.yystype* %arrayidx875 to %struct.LIST_HELP**
-  %429 = load %struct.LIST_HELP** %list876, align 4
-  br label %cond.end884
-
-cond.false877:                                    ; preds = %lor.lhs.false869
-  %arrayidx878 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %list879 = bitcast %union.yystype* %arrayidx878 to %struct.LIST_HELP**
-  %430 = load %struct.LIST_HELP** %list879, align 4
-  %call.i.i2102 = call i8* @memory_Malloc(i32 8) #1
-  %431 = bitcast i8* %call.i.i2102 to %struct.LIST_HELP*
-  %car.i.i2103 = getelementptr inbounds i8* %call.i.i2102, i32 4
-  %432 = bitcast i8* %car.i.i2103 to i8**
-  store i8* %428, i8** %432, align 4
-  %cdr.i.i2104 = bitcast i8* %call.i.i2102 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i2104, align 4
-  %cmp.i.i2105 = icmp eq %struct.LIST_HELP* %430, null
-  br i1 %cmp.i.i2105, label %cond.end884, label %if.end.i2107
-
-if.end.i2107:                                     ; preds = %cond.false877
-  %cmp.i18.i2106 = icmp eq i8* %call.i.i2102, null
-  br i1 %cmp.i18.i2106, label %cond.end884, label %for.cond.i2112
-
-for.cond.i2112:                                   ; preds = %if.end.i2107, %for.cond.i2112
-  %List1.addr.0.i2108 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i2110, %for.cond.i2112 ], [ %430, %if.end.i2107 ]
-  %List1.addr.0.idx15.i2109 = getelementptr %struct.LIST_HELP* %List1.addr.0.i2108, i32 0, i32 0
-  %List1.addr.0.idx15.val.i2110 = load %struct.LIST_HELP** %List1.addr.0.idx15.i2109, align 4
-  %cmp.i16.i2111 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i2110, null
-  br i1 %cmp.i16.i2111, label %for.end.i2113, label %for.cond.i2112
-
-for.end.i2113:                                    ; preds = %for.cond.i2112
-  store %struct.LIST_HELP* %431, %struct.LIST_HELP** %List1.addr.0.idx15.i2109, align 4
-  br label %cond.end884
-
-cond.end884:                                      ; preds = %for.end.i2113, %if.end.i2107, %cond.false877, %cond.true874
-  %cond885 = phi %struct.LIST_HELP* [ %429, %cond.true874 ], [ %430, %for.end.i2113 ], [ %431, %cond.false877 ], [ %430, %if.end.i2107 ]
-  %cond885.c = ptrtoint %struct.LIST_HELP* %cond885 to i32
-  store i32 %cond885.c, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb887:                                         ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb889:                                         ; preds = %yyreduce
-  %number891 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1, i32 0
-  %433 = load i32* %number891, align 4
-  store i32 %433, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb893:                                         ; preds = %yyreduce
-  %434 = load i32* @dfg_IGNORE, align 4
-  %tobool894 = icmp eq i32 %434, 0
-  %arrayidx896 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %string897 = bitcast %union.yystype* %arrayidx896 to i8**
-  br i1 %tobool894, label %land.lhs.true895, label %if.else915
-
-land.lhs.true895:                                 ; preds = %sw.bb893
-  %435 = load i8** %string897, align 4
-  %cmp898 = icmp eq i8* %435, null
-  br i1 %cmp898, label %if.else915, label %land.lhs.true900
-
-land.lhs.true900:                                 ; preds = %land.lhs.true895
-  %string902 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %436 = load i8** %string902, align 4
-  %cmp903 = icmp eq i8* %436, null
-  br i1 %cmp903, label %if.else915, label %land.lhs.true905
-
-land.lhs.true905:                                 ; preds = %land.lhs.true900
-  %call.i2116 = call i32 @strcmp(i8* %435, i8* getelementptr inbounds ([11 x i8]* @.str6, i32 0, i32 0)) #1
-  %cmp.i2117 = icmp eq i32 %call.i2116, 0
-  br i1 %cmp.i2117, label %if.then910, label %if.else915
-
-if.then910:                                       ; preds = %land.lhs.true905
-  %call914 = call i32 @string_StringToInt(i8* %436, i32 1, i32* %2) #1
-  br label %if.end917
-
-if.else915:                                       ; preds = %sw.bb893, %land.lhs.true905, %land.lhs.true900, %land.lhs.true895
-  store i32 0, i32* %2, align 4
-  br label %if.end917
-
-if.end917:                                        ; preds = %if.else915, %if.then910
-  %437 = load i8** %string897, align 4
-  %cmp920 = icmp eq i8* %437, null
-  br i1 %cmp920, label %if.end925, label %if.then922
-
-if.then922:                                       ; preds = %if.end917
-  call void @string_StringFree(i8* %437) #1
-  br label %if.end925
-
-if.end925:                                        ; preds = %if.end917, %if.then922
-  %string927 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %438 = load i8** %string927, align 4
-  %cmp928 = icmp eq i8* %438, null
-  br i1 %cmp928, label %sw.epilog1200, label %if.then930
-
-if.then930:                                       ; preds = %if.end925
-  call void @string_StringFree(i8* %438) #1
-  br label %sw.epilog1200
-
-sw.bb934:                                         ; preds = %yyreduce
-  %439 = load i32* @dfg_IGNORE, align 4
-  %tobool935 = icmp eq i32 %439, 0
-  %arrayidx937 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %string938 = bitcast %union.yystype* %arrayidx937 to i8**
-  br i1 %tobool935, label %land.lhs.true936, label %if.else956
-
-land.lhs.true936:                                 ; preds = %sw.bb934
-  %440 = load i8** %string938, align 4
-  %cmp939 = icmp eq i8* %440, null
-  br i1 %cmp939, label %if.else956, label %land.lhs.true941
-
-land.lhs.true941:                                 ; preds = %land.lhs.true936
-  %string943 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %441 = load i8** %string943, align 4
-  %cmp944 = icmp eq i8* %441, null
-  br i1 %cmp944, label %if.else956, label %land.lhs.true946
-
-land.lhs.true946:                                 ; preds = %land.lhs.true941
-  %call.i2119 = call i32 @strcmp(i8* %440, i8* getelementptr inbounds ([11 x i8]* @.str6, i32 0, i32 0)) #1
-  %cmp.i2120 = icmp eq i32 %call.i2119, 0
-  br i1 %cmp.i2120, label %if.then951, label %if.else956
-
-if.then951:                                       ; preds = %land.lhs.true946
-  %call955 = call i32 @string_StringToInt(i8* %441, i32 1, i32* %2) #1
-  br label %if.end960
-
-if.else956:                                       ; preds = %sw.bb934, %land.lhs.true946, %land.lhs.true941, %land.lhs.true936
-  %number958 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -4, i32 0
-  %442 = load i32* %number958, align 4
-  store i32 %442, i32* %2, align 4
-  br label %if.end960
-
-if.end960:                                        ; preds = %if.else956, %if.then951
-  %443 = load i8** %string938, align 4
-  %cmp963 = icmp eq i8* %443, null
-  br i1 %cmp963, label %if.end968, label %if.then965
-
-if.then965:                                       ; preds = %if.end960
-  call void @string_StringFree(i8* %443) #1
-  br label %if.end968
-
-if.end968:                                        ; preds = %if.end960, %if.then965
-  %string970 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %444 = load i8** %string970, align 4
-  %cmp971 = icmp eq i8* %444, null
-  br i1 %cmp971, label %sw.epilog1200, label %if.then973
-
-if.then973:                                       ; preds = %if.end968
-  call void @string_StringFree(i8* %444) #1
-  br label %sw.epilog1200
-
-sw.bb977:                                         ; preds = %yyreduce
-  %445 = load i32* @dfg_IGNORE, align 4
-  %446 = inttoptr i32 %445 to i8*
-  %447 = load i32* @stack_POINTER, align 4
-  %inc.i2122 = add i32 %447, 1
-  store i32 %inc.i2122, i32* @stack_POINTER, align 4
-  %arrayidx.i2123 = getelementptr inbounds [10000 x i8*]* @stack_STACK, i32 0, i32 %447
-  store i8* %446, i8** %arrayidx.i2123, align 4
-  store i32 1, i32* @dfg_IGNORE, align 4
-  br label %sw.epilog1200
-
-sw.bb978:                                         ; preds = %yyreduce
-  %448 = load i32* @stack_POINTER, align 4
-  %dec.i2124 = add i32 %448, -1
-  store i32 %dec.i2124, i32* @stack_POINTER, align 4
-  %arrayidx.i2125 = getelementptr inbounds [10000 x i8*]* @stack_STACK, i32 0, i32 %dec.i2124
-  %449 = load i8** %arrayidx.i2125, align 4
-  %450 = ptrtoint i8* %449 to i32
-  store i32 %450, i32* @dfg_IGNORE, align 4
-  %bool981 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 0, i32 0
-  %451 = load i32* %bool981, align 4
-  %tobool982 = icmp eq i32 %451, 0
-  %arrayidx984 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %string985 = bitcast %union.yystype* %arrayidx984 to i8**
-  %452 = load i8** %string985, align 4
-  br i1 %tobool982, label %if.else993, label %if.then983
-
-if.then983:                                       ; preds = %sw.bb978
-  %cmp986 = icmp eq i8* %452, null
-  br i1 %cmp986, label %if.end991, label %if.then988
-
-if.then988:                                       ; preds = %if.then983
-  call void @string_StringFree(i8* %452) #1
-  br label %if.end991
-
-if.end991:                                        ; preds = %if.then983, %if.then988
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-if.else993:                                       ; preds = %sw.bb978
-  %.c1725 = ptrtoint i8* %452 to i32
-  store i32 %.c1725, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb998:                                         ; preds = %yyreduce
-  %string1000 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %453 = load i8** %string1000, align 4
-  %.c1724 = ptrtoint i8* %453 to i32
-  store i32 %.c1724, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb1002:                                        ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb1004:                                        ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb1006:                                        ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb1008:                                        ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb1010:                                        ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb1012:                                        ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb1014:                                        ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb1016:                                        ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb1018:                                        ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb1020:                                        ; preds = %yyreduce
-  store i32 1, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb1022:                                        ; preds = %yyreduce
-  store i32 1, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb1024:                                        ; preds = %yyreduce
-  %term1026 = bitcast %union.yystype* %yyvsp.2 to %struct.term**
-  %454 = load %struct.term** %term1026, align 4
-  %.c = ptrtoint %struct.term* %454 to i32
-  store i32 %.c, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb1028:                                        ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb1030:                                        ; preds = %yyreduce
-  %455 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %call.i.i.i2126 = call i8* @memory_Malloc(i32 8) #1
-  %456 = bitcast i8* %call.i.i.i2126 to %struct.LIST_HELP*
-  %car.i.i.i2127 = getelementptr inbounds i8* %call.i.i.i2126, i32 4
-  %457 = bitcast i8* %car.i.i.i2127 to i8**
-  store i8* null, i8** %457, align 4
-  %cdr.i.i.i2128 = bitcast i8* %call.i.i.i2126 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %455, %struct.LIST_HELP** %cdr.i.i.i2128, align 4
-  store %struct.LIST_HELP* %456, %struct.LIST_HELP** @dfg_VARLIST, align 4
-  store i1 true, i1* @dfg_VARDECL, align 1
-  br label %sw.epilog1200
-
-sw.bb1031:                                        ; preds = %yyreduce
-  store i1 false, i1* @dfg_VARDECL, align 1
-  %458 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %.idx.i2129 = getelementptr %struct.LIST_HELP* %458, i32 0, i32 1
-  %.idx.val.i2130 = load i8** %.idx.i2129, align 4
-  %459 = bitcast i8* %.idx.val.i2130 to %struct.LIST_HELP*
-  call void @list_DeleteWithElement(%struct.LIST_HELP* %459, void (i8*)* bitcast (void (%struct.DFG_VARENTRY*)* @dfg_VarFree to void (i8*)*)) #1
-  %460 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %L.idx.i.i2131 = getelementptr %struct.LIST_HELP* %460, i32 0, i32 0
-  %L.idx.val.i.i2132 = load %struct.LIST_HELP** %L.idx.i.i2131, align 4
-  %461 = bitcast %struct.LIST_HELP* %460 to i8*
-  %462 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i2133 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %462, i32 0, i32 4
-  %463 = load i32* %total_size.i.i.i.i2133, align 4
-  %464 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i2134 = add i32 %464, %463
-  store i32 %add24.i.i.i.i2134, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i2135 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %462, i32 0, i32 0
-  %465 = load i8** %free.i.i.i.i2135, align 4
-  %.c.i.i.i2136 = bitcast i8* %465 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i2136, %struct.LIST_HELP** %L.idx.i.i2131, align 4
-  %466 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i2137 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %466, i32 0, i32 0
-  store i8* %461, i8** %free27.i.i.i.i2137, align 4
-  store %struct.LIST_HELP* %L.idx.val.i.i2132, %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %cmp.i.i2138 = icmp eq %struct.LIST_HELP* %L.idx.val.i.i2132, null
-  br i1 %cmp.i.i2138, label %dfg_VarCheck.exit2143, label %if.then.i2141
-
-if.then.i2141:                                    ; preds = %sw.bb1031
-  %467 = load %struct._IO_FILE** @stdout, align 4
-  %call1.i2139 = call i32 @fflush(%struct._IO_FILE* %467) #1
-  %468 = load %struct._IO_FILE** @stderr, align 4
-  %call2.i2140 = call i32 (%struct._IO_FILE*, i8*, ...)* @fprintf(%struct._IO_FILE* %468, i8* getelementptr inbounds ([31 x i8]* @.str27, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str28, i32 0, i32 0), i32 1881) #1
-  call void (i8*, ...)* @misc_ErrorReport(i8* getelementptr inbounds ([55 x i8]* @.str41, i32 0, i32 0)) #1
-  %469 = load %struct._IO_FILE** @stderr, align 4
-  %470 = call i32 @fwrite(i8* getelementptr inbounds ([133 x i8]* @.str30, i32 0, i32 0), i32 132, i32 1, %struct._IO_FILE* %469) #1
-  call fastcc void @misc_DumpCore() #1
-  unreachable
-
-dfg_VarCheck.exit2143:                            ; preds = %sw.bb1031
-  store i32 0, i32* @symbol_STANDARDVARCOUNTER, align 4
-  br label %sw.epilog1200
-
-sw.bb1032:                                        ; preds = %yyreduce
-  %471 = load %struct.LIST_HELP** @dfg_TERMLIST, align 4
-  %arrayidx1033 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1
-  %term1034 = bitcast %union.yystype* %arrayidx1033 to %struct.term**
-  %472 = load %struct.term** %term1034, align 4
-  %473 = bitcast %struct.term* %472 to i8*
-  %call.i.i2144 = call i8* @memory_Malloc(i32 8) #1
-  %474 = bitcast i8* %call.i.i2144 to %struct.LIST_HELP*
-  %car.i.i2145 = getelementptr inbounds i8* %call.i.i2144, i32 4
-  %475 = bitcast i8* %car.i.i2145 to i8**
-  store i8* %473, i8** %475, align 4
-  %cdr.i.i2146 = bitcast i8* %call.i.i2144 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i2146, align 4
-  %cmp.i.i2147 = icmp eq %struct.LIST_HELP* %471, null
-  br i1 %cmp.i.i2147, label %list_Nconc.exit2157, label %if.end.i2149
-
-if.end.i2149:                                     ; preds = %sw.bb1032
-  %cmp.i18.i2148 = icmp eq i8* %call.i.i2144, null
-  br i1 %cmp.i18.i2148, label %list_Nconc.exit2157, label %for.cond.i2154
-
-for.cond.i2154:                                   ; preds = %if.end.i2149, %for.cond.i2154
-  %List1.addr.0.i2150 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i2152, %for.cond.i2154 ], [ %471, %if.end.i2149 ]
-  %List1.addr.0.idx15.i2151 = getelementptr %struct.LIST_HELP* %List1.addr.0.i2150, i32 0, i32 0
-  %List1.addr.0.idx15.val.i2152 = load %struct.LIST_HELP** %List1.addr.0.idx15.i2151, align 4
-  %cmp.i16.i2153 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i2152, null
-  br i1 %cmp.i16.i2153, label %for.end.i2155, label %for.cond.i2154
-
-for.end.i2155:                                    ; preds = %for.cond.i2154
-  store %struct.LIST_HELP* %474, %struct.LIST_HELP** %List1.addr.0.idx15.i2151, align 4
-  br label %list_Nconc.exit2157
-
-list_Nconc.exit2157:                              ; preds = %sw.bb1032, %if.end.i2149, %for.end.i2155
-  %retval.0.i2156 = phi %struct.LIST_HELP* [ %471, %for.end.i2155 ], [ %474, %sw.bb1032 ], [ %471, %if.end.i2149 ]
-  store %struct.LIST_HELP* %retval.0.i2156, %struct.LIST_HELP** @dfg_TERMLIST, align 4
-  br label %sw.epilog1200
-
-sw.bb1037:                                        ; preds = %yyreduce
-  %string1039 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %476 = load i8** %string1039, align 4
-  %call.i2158 = call i32 @strcmp(i8* %476, i8* getelementptr inbounds ([6 x i8]* @.str5, i32 0, i32 0)) #1
-  %cmp.i2159 = icmp eq i32 %call.i2158, 0
-  br i1 %cmp.i2159, label %if.then1042, label %if.end1043
-
-if.then1042:                                      ; preds = %sw.bb1037
-  store i32 0, i32* @dfg_IGNORETEXT, align 4
-  %.pre2536 = load i8** %string1039, align 4
-  br label %if.end1043
-
-if.end1043:                                       ; preds = %sw.bb1037, %if.then1042
-  %477 = phi i8* [ %476, %sw.bb1037 ], [ %.pre2536, %if.then1042 ]
-  call void @string_StringFree(i8* %477) #1
-  br label %sw.epilog1200
-
-sw.bb1046:                                        ; preds = %yyreduce
-  store i32 1, i32* @dfg_IGNORETEXT, align 4
-  br label %sw.epilog1200
-
-sw.bb1047:                                        ; preds = %yyreduce
-  %string1049 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %478 = load i8** %string1049, align 4
-  call void @string_StringFree(i8* %478) #1
-  br label %sw.epilog1200
-
-for.body:                                         ; preds = %for.body.lr.ph, %if.end1075
-  %479 = phi %struct.LIST_HELP* [ %25, %for.body.lr.ph ], [ %L.idx.val.i, %if.end1075 ]
-  %.idx1760 = getelementptr %struct.LIST_HELP* %479, i32 0, i32 1
-  %.idx1760.val = load i8** %.idx1760, align 4
-  %call1059 = call i32 @symbol_Lookup(i8* %.idx1760.val) #1
-  %cmp1060 = icmp eq i32 %call1059, 0
-  br i1 %cmp1060, label %if.then1062, label %if.end1067
-
-if.then1062:                                      ; preds = %for.body
-  %480 = load %struct._IO_FILE** @stdout, align 4
-  %call1063 = call i32 @fflush(%struct._IO_FILE* %480) #1
-  %481 = load %struct.LIST_HELP** %list1053, align 4
-  %.idx1759 = getelementptr %struct.LIST_HELP* %481, i32 0, i32 1
-  %.idx1759.val = load i8** %.idx1759, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([22 x i8]* @.str7, i32 0, i32 0), i8* %.idx1759.val) #1
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([19 x i8]* @.str8, i32 0, i32 0)) #1
-  call fastcc void @misc_Error()
-  unreachable
-
-if.end1067:                                       ; preds = %for.body
-  %tobool.i2163 = icmp sgt i32 %call1059, -1
-  br i1 %tobool.i2163, label %if.then1070, label %land.rhs.i2167
-
-land.rhs.i2167:                                   ; preds = %if.end1067
-  %sub.i.i2164 = sub nsw i32 0, %call1059
-  %and.i.i2165 = and i32 %3, %sub.i.i2164
-  %cmp.i2166 = icmp eq i32 %and.i.i2165, 2
-  br i1 %cmp.i2166, label %if.end1075, label %if.then1070
-
-if.then1070:                                      ; preds = %if.end1067, %land.rhs.i2167
-  %482 = load %struct._IO_FILE** @stdout, align 4
-  %call1071 = call i32 @fflush(%struct._IO_FILE* %482) #1
-  %483 = load %struct.LIST_HELP** %list1053, align 4
-  %.idx1758 = getelementptr %struct.LIST_HELP* %483, i32 0, i32 1
-  %.idx1758.val = load i8** %.idx1758, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([30 x i8]* @.str9, i32 0, i32 0), i8* %.idx1758.val) #1
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([19 x i8]* @.str8, i32 0, i32 0)) #1
-  call fastcc void @misc_Error()
-  unreachable
-
-if.end1075:                                       ; preds = %land.rhs.i2167
-  %484 = load %struct.LIST_HELP** %list1053, align 4
-  %.idx = getelementptr %struct.LIST_HELP* %484, i32 0, i32 1
-  %.idx.val = load i8** %.idx, align 4
-  call void @string_StringFree(i8* %.idx.val) #1
-  %shr.i.i = ashr i32 %sub.i.i2164, %4
-  %485 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i = getelementptr inbounds %struct.signature** %485, i32 %shr.i.i
-  %486 = load %struct.signature** %arrayidx.i.i, align 4
-  %props.i = getelementptr inbounds %struct.signature* %486, i32 0, i32 4
-  %487 = load i32* %props.i, align 4
-  %or.i = or i32 %487, 64
-  store i32 %or.i, i32* %props.i, align 4
-  %488 = load %struct.LIST_HELP** %list1053, align 4
-  %L.idx.i = getelementptr %struct.LIST_HELP* %488, i32 0, i32 0
-  %L.idx.val.i = load %struct.LIST_HELP** %L.idx.i, align 4
-  %489 = bitcast %struct.LIST_HELP* %488 to i8*
-  %490 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %490, i32 0, i32 4
-  %491 = load i32* %total_size.i.i.i, align 4
-  %492 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i = add i32 %492, %491
-  store i32 %add24.i.i.i, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %490, i32 0, i32 0
-  %493 = load i8** %free.i.i.i, align 4
-  %.c.i.i = bitcast i8* %493 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i, %struct.LIST_HELP** %L.idx.i, align 4
-  %494 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %494, i32 0, i32 0
-  store i8* %489, i8** %free27.i.i.i, align 4
-  %call1081.c = ptrtoint %struct.LIST_HELP* %L.idx.val.i to i32
-  store i32 %call1081.c, i32* %26, align 4
-  %cmp.i2161 = icmp eq %struct.LIST_HELP* %L.idx.val.i, null
-  br i1 %cmp.i2161, label %sw.epilog1200, label %for.body
-
-sw.bb1084:                                        ; preds = %yyreduce
-  %arrayidx1085 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -3
-  %string1086 = bitcast %union.yystype* %arrayidx1085 to i8**
-  %495 = load i8** %string1086, align 4
-  %call1087 = call i32 @flag_Id(i8* %495) #1
-  %cmp1088 = icmp eq i32 %call1087, -1
-  br i1 %cmp1088, label %if.then1090, label %if.end1094
-
-if.then1090:                                      ; preds = %sw.bb1084
-  %496 = load %struct._IO_FILE** @stdout, align 4
-  %call1091 = call i32 @fflush(%struct._IO_FILE* %496) #1
-  %497 = load i8** %string1086, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([24 x i8]* @.str10, i32 0, i32 0), i8* %497) #1
-  call fastcc void @misc_Error()
-  unreachable
-
-if.end1094:                                       ; preds = %sw.bb1084
-  %498 = load i8** %string1086, align 4
-  call void @string_StringFree(i8* %498) #1
-  %499 = load i32** @dfg_FLAGS, align 4
-  %number1098 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1, i32 0
-  %500 = load i32* %number1098, align 4
-  %call.i.i2171 = call i32 @flag_Minimum(i32 %call1087) #1
-  %cmp.i.i2172 = icmp slt i32 %call.i.i2171, %500
-  br i1 %cmp.i.i2172, label %if.else.i.i, label %if.then.i.i2173
-
-if.then.i.i2173:                                  ; preds = %if.end1094
-  %501 = load %struct._IO_FILE** @stdout, align 4
-  %call1.i.i = call i32 @fflush(%struct._IO_FILE* %501) #1
-  %call2.i.i = call i8* @flag_Name(i32 %call1087) #1
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([50 x i8]* @.str231, i32 0, i32 0), i32 %500, i8* %call2.i.i) #1
-  call fastcc void @misc_Error() #1
-  unreachable
-
-if.else.i.i:                                      ; preds = %if.end1094
-  %call3.i.i = call i32 @flag_Maximum(i32 %call1087) #1
-  %cmp4.i.i = icmp sgt i32 %call3.i.i, %500
-  br i1 %cmp4.i.i, label %flag_SetFlagValue.exit, label %if.then5.i.i
-
-if.then5.i.i:                                     ; preds = %if.else.i.i
-  %502 = load %struct._IO_FILE** @stdout, align 4
-  %call6.i.i = call i32 @fflush(%struct._IO_FILE* %502) #1
-  %call7.i.i = call i8* @flag_Name(i32 %call1087) #1
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([50 x i8]* @.str232, i32 0, i32 0), i32 %500, i8* %call7.i.i) #1
-  call fastcc void @misc_Error() #1
-  unreachable
-
-flag_SetFlagValue.exit:                           ; preds = %if.else.i.i
-  %arrayidx.i2174 = getelementptr inbounds i32* %499, i32 %call1087
-  store i32 %500, i32* %arrayidx.i2174, align 4
-  br label %sw.epilog1200
-
-sw.bb1099:                                        ; preds = %yyreduce
-  %string1102 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %503 = load i8** %string1102, align 4
-  %call1103 = call i32 @symbol_Lookup(i8* %503) #1
-  %cmp1104 = icmp eq i32 %call1103, 0
-  br i1 %cmp1104, label %if.then1106, label %if.end1110
-
-if.then1106:                                      ; preds = %sw.bb1099
-  %504 = load %struct._IO_FILE** @stdout, align 4
-  %call1107 = call i32 @fflush(%struct._IO_FILE* %504) #1
-  %505 = load i8** %string1102, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([23 x i8]* @.str11, i32 0, i32 0), i8* %505) #1
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([22 x i8]* @.str12, i32 0, i32 0)) #1
-  call fastcc void @misc_Error()
-  unreachable
-
-if.end1110:                                       ; preds = %sw.bb1099
-  %506 = load i8** %string1102, align 4
-  call void @string_StringFree(i8* %506) #1
-  %507 = load i32** @dfg_PRECEDENCE, align 4
-  %call.i2175 = call i32 @symbol_GetIncreasedOrderingCounter() #1
-  %sub.i.i.i2176 = sub nsw i32 0, %call1103
-  %shr.i.i.i = ashr i32 %sub.i.i.i2176, %4
-  %arrayidx.i.i2177 = getelementptr inbounds i32* %507, i32 %shr.i.i.i
-  store i32 %call.i2175, i32* %arrayidx.i.i2177, align 4
-  %508 = inttoptr i32 %call1103 to i8*
-  %509 = load %struct.LIST_HELP** @dfg_USERPRECEDENCE, align 4
-  %call.i2178 = call i8* @memory_Malloc(i32 8) #1
-  %510 = bitcast i8* %call.i2178 to %struct.LIST_HELP*
-  %car.i2179 = getelementptr inbounds i8* %call.i2178, i32 4
-  %511 = bitcast i8* %car.i2179 to i8**
-  store i8* %508, i8** %511, align 4
-  %cdr.i2180 = bitcast i8* %call.i2178 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %509, %struct.LIST_HELP** %cdr.i2180, align 4
-  store %struct.LIST_HELP* %510, %struct.LIST_HELP** @dfg_USERPRECEDENCE, align 4
-  br label %sw.epilog1200
-
-sw.bb1114:                                        ; preds = %yyreduce
-  %arrayidx1116 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -4
-  %string1117 = bitcast %union.yystype* %arrayidx1116 to i8**
-  %512 = load i8** %string1117, align 4
-  %call1118 = call i32 @symbol_Lookup(i8* %512) #1
-  %cmp1119 = icmp eq i32 %call1118, 0
-  br i1 %cmp1119, label %if.then1121, label %if.end1125
-
-if.then1121:                                      ; preds = %sw.bb1114
-  %513 = load %struct._IO_FILE** @stdout, align 4
-  %call1122 = call i32 @fflush(%struct._IO_FILE* %513) #1
-  %514 = load i8** %string1117, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([22 x i8]* @.str7, i32 0, i32 0), i8* %514) #1
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([21 x i8]* @.str13, i32 0, i32 0)) #1
-  call fastcc void @misc_Error()
-  unreachable
-
-if.end1125:                                       ; preds = %sw.bb1114
-  %515 = load i8** %string1117, align 4
-  call void @string_StringFree(i8* %515) #1
-  %516 = load i32** @dfg_PRECEDENCE, align 4
-  %call.i2181 = call i32 @symbol_GetIncreasedOrderingCounter() #1
-  %sub.i.i.i2182 = sub nsw i32 0, %call1118
-  %shr.i.i.i2183 = ashr i32 %sub.i.i.i2182, %4
-  %arrayidx.i.i2184 = getelementptr inbounds i32* %516, i32 %shr.i.i.i2183
-  store i32 %call.i2181, i32* %arrayidx.i.i2184, align 4
-  %517 = inttoptr i32 %call1118 to i8*
-  %518 = load %struct.LIST_HELP** @dfg_USERPRECEDENCE, align 4
-  %call.i2185 = call i8* @memory_Malloc(i32 8) #1
-  %519 = bitcast i8* %call.i2185 to %struct.LIST_HELP*
-  %car.i2186 = getelementptr inbounds i8* %call.i2185, i32 4
-  %520 = bitcast i8* %car.i2186 to i8**
-  store i8* %517, i8** %520, align 4
-  %cdr.i2187 = bitcast i8* %call.i2185 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %518, %struct.LIST_HELP** %cdr.i2187, align 4
-  store %struct.LIST_HELP* %519, %struct.LIST_HELP** @dfg_USERPRECEDENCE, align 4
-  %number1130 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2, i32 0
-  %521 = load i32* %number1130, align 4
-  %522 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i2190 = getelementptr inbounds %struct.signature** %522, i32 %shr.i.i.i2183
-  %523 = load %struct.signature** %arrayidx.i.i2190, align 4
-  %weight.i = getelementptr inbounds %struct.signature* %523, i32 0, i32 2
-  store i32 %521, i32* %weight.i, align 4
-  %property = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -1, i32 0
-  %524 = load i32* %property, align 4
-  %cmp1132 = icmp eq i32 %524, 0
-  br i1 %cmp1132, label %sw.epilog1200, label %if.then1134
-
-if.then1134:                                      ; preds = %if.end1125
-  %525 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i2193 = getelementptr inbounds %struct.signature** %525, i32 %shr.i.i.i2183
-  %526 = load %struct.signature** %arrayidx.i.i2193, align 4
-  %props.i2194 = getelementptr inbounds %struct.signature* %526, i32 0, i32 4
-  %527 = load i32* %props.i2194, align 4
-  %or.i2195 = or i32 %527, %524
-  store i32 %or.i2195, i32* %props.i2194, align 4
-  br label %sw.epilog1200
-
-sw.bb1138:                                        ; preds = %yyreduce
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog1200
 
-sw.bb1140:                                        ; preds = %yyreduce
-  %string1142 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %528 = load i8** %string1142, align 4
-  %arrayidx1143 = getelementptr inbounds i8* %528, i32 1
-  %529 = load i8* %arrayidx1143, align 1
-  %cmp1145 = icmp eq i8 %529, 0
-  br i1 %cmp1145, label %lor.lhs.false1147, label %if.then1168
 
-lor.lhs.false1147:                                ; preds = %sw.bb1140
-  %530 = load i8* %528, align 1
-  switch i8 %530, label %if.then1168 [
-    i8 108, label %if.end1172
-    i8 109, label %if.end1172
-    i8 114, label %if.end1172
-  ]
-
-if.then1168:                                      ; preds = %lor.lhs.false1147, %sw.bb1140
-  %531 = load %struct._IO_FILE** @stdout, align 4
-  %call1169 = call i32 @fflush(%struct._IO_FILE* %531) #1
-  %532 = load i8** %string1142, align 4
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([27 x i8]* @.str14, i32 0, i32 0), i8* %532) #1
-  call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([21 x i8]* @.str15, i32 0, i32 0)) #1
-  call fastcc void @misc_Error()
-  unreachable
-
-if.end1172:                                       ; preds = %lor.lhs.false1147, %lor.lhs.false1147, %lor.lhs.false1147
-  %conv1176 = sext i8 %530 to i32
-  switch i32 %conv1176, label %sw.default [
-    i32 109, label %sw.bb1177
-    i32 114, label %sw.bb1179
-  ]
-
-sw.bb1177:                                        ; preds = %if.end1172
-  store i32 16, i32* %2, align 4
-  br label %sw.epilog
-
-sw.bb1179:                                        ; preds = %if.end1172
-  store i32 8, i32* %2, align 4
-  br label %sw.epilog
-
-sw.default:                                       ; preds = %if.end1172
-  store i32 0, i32* %2, align 4
-  br label %sw.epilog
-
-sw.epilog:                                        ; preds = %sw.default, %sw.bb1179, %sw.bb1177
-  %533 = load i8** %string1142, align 4
-  call void @string_StringFree(i8* %533) #1
-  br label %sw.epilog1200
-
-sw.bb1184:                                        ; preds = %yyreduce
-  %arrayidx1185 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %list1186 = bitcast %union.yystype* %arrayidx1185 to %struct.LIST_HELP**
-  %534 = load %struct.LIST_HELP** %list1186, align 4
-  call void @list_DeleteWithElement(%struct.LIST_HELP* %534, void (i8*)* @string_StringFree) #1
-  br label %sw.epilog1200
-
-sw.bb1187:                                        ; preds = %yyreduce
-  %string1189 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %535 = load i8** %string1189, align 4
-  %call.i.i2196 = call i8* @memory_Malloc(i32 8) #1
-  %car.i.i2197 = getelementptr inbounds i8* %call.i.i2196, i32 4
-  %536 = bitcast i8* %car.i.i2197 to i8**
-  store i8* %535, i8** %536, align 4
-  %cdr.i.i2198 = bitcast i8* %call.i.i2196 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i2198, align 4
-  %call1190.c = ptrtoint i8* %call.i.i2196 to i32
-  store i32 %call1190.c, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.bb1192:                                        ; preds = %yyreduce
-  %arrayidx1193 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 -2
-  %list1194 = bitcast %union.yystype* %arrayidx1193 to %struct.LIST_HELP**
-  %537 = load %struct.LIST_HELP** %list1194, align 4
-  %string1196 = bitcast %union.yystype* %yyvsp.2 to i8**
-  %538 = load i8** %string1196, align 4
-  %call.i.i2199 = call i8* @memory_Malloc(i32 8) #1
-  %539 = bitcast i8* %call.i.i2199 to %struct.LIST_HELP*
-  %car.i.i2200 = getelementptr inbounds i8* %call.i.i2199, i32 4
-  %540 = bitcast i8* %car.i.i2200 to i8**
-  store i8* %538, i8** %540, align 4
-  %cdr.i.i2201 = bitcast i8* %call.i.i2199 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i2201, align 4
-  %cmp.i.i2202 = icmp eq %struct.LIST_HELP* %537, null
-  br i1 %cmp.i.i2202, label %list_Nconc.exit2212, label %if.end.i2204
-
-if.end.i2204:                                     ; preds = %sw.bb1192
-  %cmp.i18.i2203 = icmp eq i8* %call.i.i2199, null
-  br i1 %cmp.i18.i2203, label %list_Nconc.exit2212, label %for.cond.i2209
-
-for.cond.i2209:                                   ; preds = %if.end.i2204, %for.cond.i2209
-  %List1.addr.0.i2205 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i2207, %for.cond.i2209 ], [ %537, %if.end.i2204 ]
-  %List1.addr.0.idx15.i2206 = getelementptr %struct.LIST_HELP* %List1.addr.0.i2205, i32 0, i32 0
-  %List1.addr.0.idx15.val.i2207 = load %struct.LIST_HELP** %List1.addr.0.idx15.i2206, align 4
-  %cmp.i16.i2208 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i2207, null
-  br i1 %cmp.i16.i2208, label %for.end.i2210, label %for.cond.i2209
-
-for.end.i2210:                                    ; preds = %for.cond.i2209
-  store %struct.LIST_HELP* %539, %struct.LIST_HELP** %List1.addr.0.idx15.i2206, align 4
-  br label %list_Nconc.exit2212
-
-list_Nconc.exit2212:                              ; preds = %sw.bb1192, %if.end.i2204, %for.end.i2210
-  %retval.0.i2211 = phi %struct.LIST_HELP* [ %537, %for.end.i2210 ], [ %539, %sw.bb1192 ], [ %537, %if.end.i2204 ]
-  %call1198.c = ptrtoint %struct.LIST_HELP* %retval.0.i2211 to i32
-  store i32 %call1198.c, i32* %2, align 4
-  br label %sw.epilog1200
-
-sw.epilog1200:                                    ; preds = %for.cond.preheader, %if.end1075, %sw.bb770, %sw.bb479, %sw.bb494, %if.end925, %if.end968, %if.end1125, %if.then1134, %if.end991, %if.else993, %if.then973, %if.then930, %if.then775, %list_Nconc.exit1922, %list_Nconc.exit1933, %if.end512, %if.end489, %if.then410, %if.else414, %list_Nconc.exit1824, %list_Nconc.exit1835, %yyreduce, %list_Nconc.exit2212, %sw.bb1187, %sw.bb1184, %sw.epilog, %sw.bb1138, %if.end1110, %flag_SetFlagValue.exit, %sw.bb1047, %sw.bb1046, %if.end1043, %list_Nconc.exit2157, %dfg_VarCheck.exit2143, %sw.bb1030, %sw.bb1028, %sw.bb1024, %sw.bb1022, %sw.bb1020, %sw.bb1018, %sw.bb1016, %sw.bb1014, %sw.bb1012, %sw.bb1010, %sw.bb1008, %sw.bb1006, %sw.bb1004, %sw.bb1002, %sw.bb998, %sw.bb977, %sw.bb889, %sw.bb887, %cond.end884, %cond.end864, %dfg_VarCheck.exit2098, %if.end784, %cond.end767, %cond.end752, %cond.end741, %cond.end729, %cond.end718, %cond.end706, %cond.end691, %cond.end681, %cond.end671, %list_Nconc.exit1995, %sw.bb650, %cond.end647, %sw.bb632, %cond.end629, %cond.end614, %cond.end603, %cond.end592, %sw.bb581, %sw.bb580, %sw.bb576, %sw.bb572, %sw.bb570, %dfg_VarCheck.exit1946, %sw.bb538, %sw.bb536, %sw.bb535, %cond.end476, %cond.end461, %cond.end450, %cond.end442, %cond.end434, %cond.end426, %sw.bb405, %sw.bb402, %sw.bb399, %sw.bb396, %sw.bb393, %sw.bb390, %sw.bb387, %cond.end384, %cond.end369, %sw.bb357, %sw.bb355, %cond.end352, %sw.bb340, %sw.bb339, %cond.end336, %cond.end324, %cond.end309, %sw.bb296, %sw.bb292, %sw.bb290, %dfg_VarCheck.exit1847, %sw.bb259, %sw.bb257, %sw.bb255, %sw.bb236, %sw.bb233, %sw.bb226, %sw.bb221, %sw.bb219, %sw.bb217, %dfg_SymbolGenerated.exit, %list_Nconc.exit1792, %sw.bb199, %sw.bb198, %sw.bb195, %list_Nconc.exit, %dfg_SubSort.exit, %sw.bb181, %sw.bb179, %sw.bb174, %sw.bb171, %sw.bb166, %sw.bb163, %sw.bb160, %sw.bb157, %sw.bb152, %sw.bb149, %sw.bb145, %sw.bb142, %sw.bb140, %sw.bb138, %sw.bb136, %sw.bb133, %sw.bb130, %sw.bb127, %sw.bb124, %sw.bb122, %sw.bb119, %sw.bb116
-  %idx.neg = sub i32 0, %conv112
-  %add.ptr1203 = getelementptr inbounds i16* %yyssp.2, i32 %idx.neg
-  %incdec.ptr1204 = getelementptr inbounds %union.yystype* %yyvsp.2, i32 %sub113
-  %541 = load i32* %2, align 4
-  %542 = getelementptr inbounds %union.yystype* %incdec.ptr1204, i32 0, i32 0
-  store i32 %541, i32* %542, align 4
-  %arrayidx1205 = getelementptr inbounds [197 x i8]* @yyr1, i32 0, i32 %conv106
-  %543 = load i8* %arrayidx1205, align 1
-  %conv1206 = zext i8 %543 to i32
-  %sub1207 = add nsw i32 %conv1206, -71
-  %arrayidx1208 = getelementptr inbounds [100 x i16]* @yypgoto, i32 0, i32 %sub1207
-  %544 = load i16* %arrayidx1208, align 2
-  %conv1209 = sext i16 %544 to i32
-  %545 = load i16* %add.ptr1203, align 2
-  %conv1210 = sext i16 %545 to i32
-  %add1211 = add nsw i32 %conv1210, %conv1209
-  %546 = icmp ult i32 %add1211, 507
-  br i1 %546, label %land.lhs.true1217, label %if.else1226
-
-land.lhs.true1217:                                ; preds = %sw.epilog1200
-  %arrayidx1218 = getelementptr inbounds [507 x i16]* @yycheck, i32 0, i32 %add1211
-  %547 = load i16* %arrayidx1218, align 2
-  %cmp1221 = icmp eq i16 %547, %545
-  br i1 %cmp1221, label %if.then1223, label %if.else1226
-
-if.then1223:                                      ; preds = %land.lhs.true1217
-  %arrayidx1224 = getelementptr inbounds [507 x i16]* @yytable, i32 0, i32 %add1211
-  %548 = load i16* %arrayidx1224, align 2
-  %conv1225 = zext i16 %548 to i32
-  br label %yynewstate
-
-if.else1226:                                      ; preds = %land.lhs.true1217, %sw.epilog1200
-  %arrayidx1228 = getelementptr inbounds [100 x i16]* @yydefgoto, i32 0, i32 %sub1207
-  %549 = load i16* %arrayidx1228, align 2
-  %conv1229 = sext i16 %549 to i32
-  br label %yynewstate
-
-if.then1232:                                      ; preds = %yydefault, %if.end79
-  %550 = load i32* @dfg_nerrs, align 4
-  %inc = add nsw i32 %550, 1
-  store i32 %inc, i32* @dfg_nerrs, align 4
-  %cmp1235 = icmp sgt i16 %11, -356
-  br i1 %cmp1235, label %if.then1240, label %if.else1329
-
-if.then1240:                                      ; preds = %if.then1232
-  %551 = load i32* @dfg_char, align 4
-  %cmp1242 = icmp ult i32 %551, 319
-  br i1 %cmp1242, label %cond.true1244, label %cond.end1248
-
-cond.true1244:                                    ; preds = %if.then1240
-  %arrayidx1245 = getelementptr inbounds [319 x i8]* @yytranslate, i32 0, i32 %551
-  %552 = load i8* %arrayidx1245, align 1
-  %conv1246 = zext i8 %552 to i32
-  br label %cond.end1248
-
-cond.end1248:                                     ; preds = %if.then1240, %cond.true1244
-  %cond1249 = phi i32 [ %conv1246, %cond.true1244 ], [ 2, %if.then1240 ]
-  %cmp1250 = icmp slt i16 %11, 0
-  %sub1253 = sub nsw i32 0, %conv51
-  %sub1253. = select i1 %cmp1250, i32 %sub1253, i32 0
-  %cmp12582218 = icmp slt i32 %sub1253., 172
-  br i1 %cmp12582218, label %for.body1260, label %for.end1278
-
-for.body1260:                                     ; preds = %cond.end1248, %for.inc1276
-  %yycount.02221 = phi i32 [ %yycount.1, %for.inc1276 ], [ 0, %cond.end1248 ]
-  %yyx.02220 = phi i32 [ %inc1277, %for.inc1276 ], [ %sub1253., %cond.end1248 ]
-  %yysize1241.02219 = phi i32 [ %yysize1241.1, %for.inc1276 ], [ 0, %cond.end1248 ]
-  %add1261 = add nsw i32 %yyx.02220, %conv51
-  %arrayidx1262 = getelementptr inbounds [507 x i16]* @yycheck, i32 0, i32 %add1261
-  %553 = load i16* %arrayidx1262, align 2
-  %conv1263 = sext i16 %553 to i32
-  %cmp1264 = icmp eq i32 %conv1263, %yyx.02220
-  %cmp1267 = icmp ne i32 %yyx.02220, 1
-  %or.cond1400 = and i1 %cmp1264, %cmp1267
-  br i1 %or.cond1400, label %if.then1269, label %for.inc1276
-
-if.then1269:                                      ; preds = %for.body1260
-  %arrayidx1270 = getelementptr inbounds [172 x i8*]* @yytname, i32 0, i32 %yyx.02220
-  %554 = load i8** %arrayidx1270, align 4
-  %call1271 = call i32 @strlen(i8* %554) #6
-  %add1272 = add i32 %yysize1241.02219, 15
-  %add1273 = add i32 %add1272, %call1271
-  %inc1274 = add nsw i32 %yycount.02221, 1
-  br label %for.inc1276
-
-for.inc1276:                                      ; preds = %for.body1260, %if.then1269
-  %yysize1241.1 = phi i32 [ %add1273, %if.then1269 ], [ %yysize1241.02219, %for.body1260 ]
-  %yycount.1 = phi i32 [ %inc1274, %if.then1269 ], [ %yycount.02221, %for.body1260 ]
-  %inc1277 = add nsw i32 %yyx.02220, 1
-  %exitcond2382 = icmp eq i32 %inc1277, 172
-  br i1 %exitcond2382, label %for.end1278, label %for.body1260
-
-for.end1278:                                      ; preds = %for.inc1276, %cond.end1248
-  %yycount.0.lcssa = phi i32 [ 0, %cond.end1248 ], [ %yycount.1, %for.inc1276 ]
-  %yysize1241.0.lcssa = phi i32 [ 0, %cond.end1248 ], [ %yysize1241.1, %for.inc1276 ]
-  %add1279 = add i32 %yysize1241.0.lcssa, 25
-  %arrayidx1280 = getelementptr inbounds [172 x i8*]* @yytname, i32 0, i32 %cond1249
-  %555 = load i8** %arrayidx1280, align 4
-  %call1281 = call i32 @strlen(i8* %555) #6
-  %add1282 = add i32 %add1279, %call1281
-  %556 = alloca i8, i32 %add1282, align 4
-  %557 = getelementptr i8* %556, i32 24
-  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %556, i8* getelementptr inbounds ([25 x i8]* @.str16, i32 0, i32 0), i32 25, i32 1, i1 false)
-  %call1288 = call i8* @stpcpy(i8* %557, i8* %555) #1
-  %cmp1289.not = icmp sgt i32 %yycount.0.lcssa, 4
-  %cmp12582218.not = xor i1 %cmp12582218, true
-  %brmerge = or i1 %cmp1289.not, %cmp12582218.not
-  br i1 %brmerge, label %if.end1323, label %for.body1302
-
-for.body1302:                                     ; preds = %for.end1278, %for.inc1320
-  %yyp.02217 = phi i8* [ %yyp.1, %for.inc1320 ], [ %call1288, %for.end1278 ]
-  %yycount.22216 = phi i32 [ %yycount.3, %for.inc1320 ], [ 0, %for.end1278 ]
-  %yyx.12215 = phi i32 [ %inc1321, %for.inc1320 ], [ %sub1253., %for.end1278 ]
-  %add1303 = add nsw i32 %yyx.12215, %conv51
-  %arrayidx1304 = getelementptr inbounds [507 x i16]* @yycheck, i32 0, i32 %add1303
-  %558 = load i16* %arrayidx1304, align 2
-  %conv1305 = sext i16 %558 to i32
-  %cmp1306 = icmp eq i32 %conv1305, %yyx.12215
-  %cmp1309 = icmp ne i32 %yyx.12215, 1
-  %or.cond1401 = and i1 %cmp1306, %cmp1309
-  br i1 %or.cond1401, label %if.then1311, label %for.inc1320
-
-if.then1311:                                      ; preds = %for.body1302
-  %lnot1313 = icmp eq i32 %yycount.22216, 0
-  %cond1314 = select i1 %lnot1313, i8* getelementptr inbounds ([13 x i8]* @.str17, i32 0, i32 0), i8* getelementptr inbounds ([5 x i8]* @.str18, i32 0, i32 0)
-  %call1315 = call i8* @stpcpy(i8* %yyp.02217, i8* %cond1314) #1
-  %arrayidx1316 = getelementptr inbounds [172 x i8*]* @yytname, i32 0, i32 %yyx.12215
-  %559 = load i8** %arrayidx1316, align 4
-  %call1317 = call i8* @stpcpy(i8* %call1315, i8* %559) #1
-  %inc1318 = add nsw i32 %yycount.22216, 1
-  br label %for.inc1320
-
-for.inc1320:                                      ; preds = %for.body1302, %if.then1311
-  %yycount.3 = phi i32 [ %inc1318, %if.then1311 ], [ %yycount.22216, %for.body1302 ]
-  %yyp.1 = phi i8* [ %call1317, %if.then1311 ], [ %yyp.02217, %for.body1302 ]
-  %inc1321 = add nsw i32 %yyx.12215, 1
-  %exitcond = icmp eq i32 %inc1321, 172
-  br i1 %exitcond, label %if.end1323, label %for.body1302
-
-if.end1323:                                       ; preds = %for.end1278, %for.inc1320
-  call void @dfg_error(i8* %556)
-  unreachable
-
-if.else1329:                                      ; preds = %if.then1232
-  call void @dfg_error(i8* getelementptr inbounds ([12 x i8]* @.str20, i32 0, i32 0))
-  unreachable
-
-yyoverflowlab:                                    ; preds = %if.then
-  call void @dfg_error(i8* getelementptr inbounds ([22 x i8]* @.str21, i32 0, i32 0))
-  unreachable
-
-yyreturn:                                         ; preds = %if.end, %if.end92, %sw.bb
-  %yyresult.0 = phi i32 [ 0, %sw.bb ], [ 1, %if.end ], [ 0, %if.end92 ]
-  call void @llvm.lifetime.end(i64 800, i8* %1) #1
-  call void @llvm.lifetime.end(i64 400, i8* %0) #1
-  ret i32 %yyresult.0
-}
-
-; Function Attrs: nounwind
-declare void @llvm.lifetime.start(i64, i8* nocapture) #1
-
-; Function Attrs: nounwind
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) #1
-
-declare i32 @dfg_lex() #2
-
-declare void @string_StringFree(i8*) #2
-
-; cmp16: 	.ent	dfg_parse
-; cmp16:	.end	dfg_parse 
-
-; Function Attrs: nounwind
-define internal fastcc void @dfg_SymbolDecl(i32 %SymbolType, i8* %Name, i32 %Arity) #0 {
+define void @getSubImagesLuma(%struct.StorablePicture* nocapture %s) #0 {
 entry:
-  switch i32 %Arity, label %sw.default [
-    i32 -2, label %sw.epilog
-    i32 -1, label %sw.bb1
-  ]
-
-sw.bb1:                                           ; preds = %entry
-  %0 = load %struct._IO_FILE** @stdout, align 4
-  %call = tail call i32 @fflush(%struct._IO_FILE* %0) #1
-  %1 = load i32* @dfg_LINENUMBER, align 4
-  tail call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([58 x i8]* @.str52, i32 0, i32 0), i32 %1) #1
-  tail call fastcc void @misc_Error()
-  unreachable
-
-sw.default:                                       ; preds = %entry
-  br label %sw.epilog
-
-sw.epilog:                                        ; preds = %entry, %sw.default
-  %arity.0 = phi i32 [ %Arity, %sw.default ], [ 0, %entry ]
-  %call2 = tail call i32 @strlen(i8* %Name) #6
-  %cmp = icmp ugt i32 %call2, 63
-  br i1 %cmp, label %if.then, label %if.end
-
-if.then:                                          ; preds = %sw.epilog
-  %arrayidx = getelementptr inbounds i8* %Name, i32 63
-  store i8 0, i8* %arrayidx, align 1
-  br label %if.end
-
-if.end:                                           ; preds = %if.then, %sw.epilog
-  %call3 = tail call i32 @symbol_Lookup(i8* %Name) #1
-  %cmp4 = icmp eq i32 %call3, 0
-  br i1 %cmp4, label %if.else, label %if.then5
-
-if.then5:                                         ; preds = %if.end
-  switch i32 %SymbolType, label %if.end27 [
-    i32 284, label %land.lhs.true
-    i32 298, label %land.lhs.true9
-    i32 300, label %land.lhs.true16
-    i32 294, label %land.lhs.true16
-  ]
-
-land.lhs.true:                                    ; preds = %if.then5
-  %tobool.i = icmp sgt i32 %call3, -1
-  br i1 %tobool.i, label %if.then19, label %land.rhs.i
-
-land.rhs.i:                                       ; preds = %land.lhs.true
-  %sub.i6.i = sub nsw i32 0, %call3
-  %2 = load i32* @symbol_TYPEMASK, align 4
-  %and.i7.i = and i32 %2, %sub.i6.i
-  %3 = icmp ult i32 %and.i7.i, 2
-  br i1 %3, label %if.end27, label %if.then19
-
-land.lhs.true9:                                   ; preds = %if.then5
-  %tobool.i77 = icmp sgt i32 %call3, -1
-  br i1 %tobool.i77, label %if.then19, label %land.rhs.i78
-
-land.rhs.i78:                                     ; preds = %land.lhs.true9
-  %sub.i.i = sub nsw i32 0, %call3
-  %4 = load i32* @symbol_TYPEMASK, align 4
-  %and.i.i = and i32 %4, %sub.i.i
-  %cmp.i = icmp eq i32 %and.i.i, 2
-  br i1 %cmp.i, label %lor.lhs.false12, label %if.then19
-
-lor.lhs.false12:                                  ; preds = %land.rhs.i78
-  switch i32 %SymbolType, label %if.end27 [
-    i32 300, label %land.lhs.true16
-    i32 294, label %land.lhs.true16
-  ]
-
-land.lhs.true16:                                  ; preds = %if.then5, %if.then5, %lor.lhs.false12, %lor.lhs.false12
-  %tobool.i80 = icmp sgt i32 %call3, -1
-  br i1 %tobool.i80, label %if.then19, label %land.rhs.i84
+  %size_y = getelementptr inbounds %struct.StorablePicture* %s, i32 0, i32 1
+  %0 = load i32* %size_y, align 4, !tbaa !0
+  %sub = add nsw i32 %0, -1
+  %add5 = add nsw i32 %0, 20
+  %cmp6 = icmp sgt i32 %add5, -20
+  br i1 %cmp6, label %for.body, label %for.end
 
-land.rhs.i84:                                     ; preds = %land.lhs.true16
-  %sub.i.i81 = sub nsw i32 0, %call3
-  %5 = load i32* @symbol_TYPEMASK, align 4
-  %and.i.i82 = and i32 %5, %sub.i.i81
-  %cmp.i83 = icmp eq i32 %and.i.i82, 3
-  br i1 %cmp.i83, label %if.end27, label %if.then19
+for.body:                                         ; preds = %entry, %for.body
+  %j.07 = phi i32 [ %inc, %for.body ], [ -20, %entry ]
+  %call = tail call i32 bitcast (i32 (...)* @iClip3 to i32 (i32, i32, i32)*)(i32 0, i32 %sub, i32 %j.07) #2
+  %inc = add nsw i32 %j.07, 1
+  %1 = load i32* %size_y, align 4, !tbaa !0
+  %add = add nsw i32 %1, 20
+  %cmp = icmp slt i32 %inc, %add
+  br i1 %cmp, label %for.body, label %for.end
 
-if.then19:                                        ; preds = %land.lhs.true16, %land.lhs.true9, %land.lhs.true, %land.rhs.i, %land.rhs.i78, %land.rhs.i84
-  %6 = load %struct._IO_FILE** @stdout, align 4
-  %call20 = tail call i32 @fflush(%struct._IO_FILE* %6) #1
-  %7 = load i32* @dfg_LINENUMBER, align 4
-  tail call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([46 x i8]* @.str53, i32 0, i32 0), i32 %7, i8* %Name) #1
-  %sub.i = sub nsw i32 0, %call3
-  %8 = load i32* @symbol_TYPEMASK, align 4
-  %and.i = and i32 %8, %sub.i
-  switch i32 %and.i, label %sw.default25 [
-    i32 0, label %sw.bb22
-    i32 1, label %sw.bb22
-    i32 2, label %sw.bb23
-    i32 3, label %sw.bb24
-  ]
-
-sw.bb22:                                          ; preds = %if.then19, %if.then19
-  tail call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([11 x i8]* @.str54, i32 0, i32 0)) #1
-  br label %sw.epilog26
-
-sw.bb23:                                          ; preds = %if.then19
-  tail call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([12 x i8]* @.str55, i32 0, i32 0)) #1
-  br label %sw.epilog26
-
-sw.bb24:                                          ; preds = %if.then19
-  tail call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([10 x i8]* @.str56, i32 0, i32 0)) #1
-  br label %sw.epilog26
-
-sw.default25:                                     ; preds = %if.then19
-  tail call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([15 x i8]* @.str57, i32 0, i32 0)) #1
-  br label %sw.epilog26
-
-sw.epilog26:                                      ; preds = %sw.default25, %sw.bb24, %sw.bb23, %sw.bb22
-  tail call fastcc void @misc_Error()
-  unreachable
-
-if.end27:                                         ; preds = %land.rhs.i, %land.rhs.i84, %if.then5, %lor.lhs.false12
-  %cmp28 = icmp eq i32 %Arity, -2
-  br i1 %cmp28, label %if.end46, label %land.lhs.true29
-
-land.lhs.true29:                                  ; preds = %if.end27
-  %sub.i.i88 = sub nsw i32 0, %call3
-  %9 = load i32* @symbol_TYPESTATBITS, align 4
-  %shr.i.i89 = ashr i32 %sub.i.i88, %9
-  %10 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i90 = getelementptr inbounds %struct.signature** %10, i32 %shr.i.i89
-  %11 = load %struct.signature** %arrayidx.i.i90, align 4
-  %arity.i91 = getelementptr inbounds %struct.signature* %11, i32 0, i32 3
-  %12 = load i32* %arity.i91, align 4
-  %cmp31 = icmp eq i32 %12, %Arity
-  br i1 %cmp31, label %if.end46, label %if.then32
-
-if.then32:                                        ; preds = %land.lhs.true29
-  %13 = load %struct._IO_FILE** @stdout, align 4
-  %call33 = tail call i32 @fflush(%struct._IO_FILE* %13) #1
-  %14 = load i32* @dfg_LINENUMBER, align 4
-  %15 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i = getelementptr inbounds %struct.signature** %15, i32 %shr.i.i89
-  %16 = load %struct.signature** %arrayidx.i.i, align 4
-  %arity.i87 = getelementptr inbounds %struct.signature* %16, i32 0, i32 3
-  %17 = load i32* %arity.i87, align 4
-  tail call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([57 x i8]* @.str58, i32 0, i32 0), i32 %14, i8* %Name, i32 %17) #1
-  tail call fastcc void @misc_Error()
-  unreachable
-
-if.else:                                          ; preds = %if.end
-  switch i32 %SymbolType, label %sw.default40 [
-    i32 284, label %sw.bb36
-    i32 298, label %sw.bb38
-  ]
-
-sw.bb36:                                          ; preds = %if.else
-  %18 = load i32** @dfg_PRECEDENCE, align 4
-  %call37 = tail call i32 @symbol_CreateFunction(i8* %Name, i32 %arity.0, i32 0, i32* %18) #1
-  br label %sw.epilog42
-
-sw.bb38:                                          ; preds = %if.else
-  %19 = load i32** @dfg_PRECEDENCE, align 4
-  %call39 = tail call i32 @symbol_CreatePredicate(i8* %Name, i32 %arity.0, i32 0, i32* %19) #1
-  br label %sw.epilog42
-
-sw.default40:                                     ; preds = %if.else
-  %20 = load i32** @dfg_PRECEDENCE, align 4
-  %call41 = tail call i32 @symbol_CreateJunctor(i8* %Name, i32 %arity.0, i32 0, i32* %20) #1
-  br label %sw.epilog42
-
-sw.epilog42:                                      ; preds = %sw.default40, %sw.bb38, %sw.bb36
-  %symbol.0 = phi i32 [ %call41, %sw.default40 ], [ %call39, %sw.bb38 ], [ %call37, %sw.bb36 ]
-  %cmp43 = icmp eq i32 %Arity, -2
-  br i1 %cmp43, label %if.then44, label %if.end46
-
-if.then44:                                        ; preds = %sw.epilog42
-  %call.i.i = tail call i8* @memory_Malloc(i32 12) #1
-  %symbol.i = bitcast i8* %call.i.i to i32*
-  store i32 %symbol.0, i32* %symbol.i, align 4
-  %valid.i = getelementptr inbounds i8* %call.i.i, i32 4
-  %21 = bitcast i8* %valid.i to i32*
-  store i32 0, i32* %21, align 4
-  %arity.i = getelementptr inbounds i8* %call.i.i, i32 8
-  %22 = bitcast i8* %arity.i to i32*
-  store i32 0, i32* %22, align 4
-  %23 = load %struct.LIST_HELP** @dfg_SYMBOLLIST, align 4
-  %call.i5.i = tail call i8* @memory_Malloc(i32 8) #1
-  %24 = bitcast i8* %call.i5.i to %struct.LIST_HELP*
-  %car.i.i = getelementptr inbounds i8* %call.i5.i, i32 4
-  %25 = bitcast i8* %car.i.i to i8**
-  store i8* %call.i.i, i8** %25, align 4
-  %cdr.i.i = bitcast i8* %call.i5.i to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %23, %struct.LIST_HELP** %cdr.i.i, align 4
-  store %struct.LIST_HELP* %24, %struct.LIST_HELP** @dfg_SYMBOLLIST, align 4
-  br label %if.end46
-
-if.end46:                                         ; preds = %land.lhs.true29, %if.end27, %sw.epilog42, %if.then44
-  br i1 %cmp, label %if.then48, label %if.end50
-
-if.then48:                                        ; preds = %if.end46
-  %arrayidx49 = getelementptr inbounds i8* %Name, i32 63
-  store i8 32, i8* %arrayidx49, align 1
-  br label %if.end50
-
-if.end50:                                         ; preds = %if.then48, %if.end46
-  tail call void @string_StringFree(i8* %Name) #1
+for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
-; Function Attrs: nounwind
-define %struct.term* @dfg_CreateQuantifier(i32 %Symbol, %struct.LIST_HELP* %VarTermList, %struct.term* %Term) #0 {
-entry:
-  %cmp.i240 = icmp eq %struct.LIST_HELP* %VarTermList, null
-  br i1 %cmp.i240, label %for.end, label %for.body
-
-for.body:                                         ; preds = %entry, %for.inc
-  %VarTermList.addr.0243 = phi %struct.LIST_HELP* [ %L.idx.val.i, %for.inc ], [ %VarTermList, %entry ]
-  %sortlist.0242 = phi %struct.LIST_HELP* [ %sortlist.1, %for.inc ], [ null, %entry ]
-  %varlist.0241 = phi %struct.LIST_HELP* [ %varlist.1, %for.inc ], [ null, %entry ]
-  %VarTermList.addr.0.idx = getelementptr %struct.LIST_HELP* %VarTermList.addr.0243, i32 0, i32 1
-  %VarTermList.addr.0.idx.val = load i8** %VarTermList.addr.0.idx, align 4
-  %0 = bitcast i8* %VarTermList.addr.0.idx.val to %struct.term*
-  %.idx135 = bitcast i8* %VarTermList.addr.0.idx.val to i32*
-  %.idx135.val = load i32* %.idx135, align 4
-  %cmp.i.i157 = icmp sgt i32 %.idx135.val, 0
-  br i1 %cmp.i.i157, label %if.then, label %if.else
-
-if.then:                                          ; preds = %for.body
-  %1 = inttoptr i32 %.idx135.val to i8*
-  %call.i.i165 = tail call i8* @memory_Malloc(i32 8) #1
-  %2 = bitcast i8* %call.i.i165 to %struct.LIST_HELP*
-  %car.i.i166 = getelementptr inbounds i8* %call.i.i165, i32 4
-  %3 = bitcast i8* %car.i.i166 to i8**
-  store i8* %1, i8** %3, align 4
-  %cdr.i.i167 = bitcast i8* %call.i.i165 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i167, align 4
-  %cmp.i.i168 = icmp eq %struct.LIST_HELP* %varlist.0241, null
-  br i1 %cmp.i.i168, label %list_Nconc.exit178, label %if.end.i170
-
-if.end.i170:                                      ; preds = %if.then
-  %cmp.i18.i169 = icmp eq i8* %call.i.i165, null
-  br i1 %cmp.i18.i169, label %list_Nconc.exit178, label %for.cond.i175
-
-for.cond.i175:                                    ; preds = %if.end.i170, %for.cond.i175
-  %List1.addr.0.i171 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i173, %for.cond.i175 ], [ %varlist.0241, %if.end.i170 ]
-  %List1.addr.0.idx15.i172 = getelementptr %struct.LIST_HELP* %List1.addr.0.i171, i32 0, i32 0
-  %List1.addr.0.idx15.val.i173 = load %struct.LIST_HELP** %List1.addr.0.idx15.i172, align 4
-  %cmp.i16.i174 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i173, null
-  br i1 %cmp.i16.i174, label %for.end.i176, label %for.cond.i175
-
-for.end.i176:                                     ; preds = %for.cond.i175
-  store %struct.LIST_HELP* %2, %struct.LIST_HELP** %List1.addr.0.idx15.i172, align 4
-  br label %list_Nconc.exit178
-
-list_Nconc.exit178:                               ; preds = %if.then, %if.end.i170, %for.end.i176
-  %retval.0.i177 = phi %struct.LIST_HELP* [ %varlist.0241, %for.end.i176 ], [ %2, %if.then ], [ %varlist.0241, %if.end.i170 ]
-  tail call void @term_Delete(%struct.term* %0) #1
-  br label %for.inc
-
-if.else:                                          ; preds = %for.body
-  %.idx136 = getelementptr i8* %VarTermList.addr.0.idx.val, i32 8
-  %4 = bitcast i8* %.idx136 to %struct.LIST_HELP**
-  %.idx136.val = load %struct.LIST_HELP** %4, align 4
-  %.idx136.val.idx = getelementptr %struct.LIST_HELP* %.idx136.val, i32 0, i32 1
-  %.idx136.val.idx.val = load i8** %.idx136.val.idx, align 4
-  %call8.idx = bitcast i8* %.idx136.val.idx.val to i32*
-  %call8.idx.val = load i32* %call8.idx, align 4
-  %5 = inttoptr i32 %call8.idx.val to i8*
-  %call.i.i233 = tail call i8* @memory_Malloc(i32 8) #1
-  %6 = bitcast i8* %call.i.i233 to %struct.LIST_HELP*
-  %car.i.i234 = getelementptr inbounds i8* %call.i.i233, i32 4
-  %7 = bitcast i8* %car.i.i234 to i8**
-  store i8* %5, i8** %7, align 4
-  %cdr.i.i235 = bitcast i8* %call.i.i233 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i235, align 4
-  %cmp.i.i222 = icmp eq %struct.LIST_HELP* %varlist.0241, null
-  br i1 %cmp.i.i222, label %list_Nconc.exit232, label %if.end.i224
-
-if.end.i224:                                      ; preds = %if.else
-  %cmp.i18.i223 = icmp eq i8* %call.i.i233, null
-  br i1 %cmp.i18.i223, label %list_Nconc.exit232, label %for.cond.i229
-
-for.cond.i229:                                    ; preds = %if.end.i224, %for.cond.i229
-  %List1.addr.0.i225 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i227, %for.cond.i229 ], [ %varlist.0241, %if.end.i224 ]
-  %List1.addr.0.idx15.i226 = getelementptr %struct.LIST_HELP* %List1.addr.0.i225, i32 0, i32 0
-  %List1.addr.0.idx15.val.i227 = load %struct.LIST_HELP** %List1.addr.0.idx15.i226, align 4
-  %cmp.i16.i228 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i227, null
-  br i1 %cmp.i16.i228, label %for.end.i230, label %for.cond.i229
-
-for.end.i230:                                     ; preds = %for.cond.i229
-  store %struct.LIST_HELP* %6, %struct.LIST_HELP** %List1.addr.0.idx15.i226, align 4
-  br label %list_Nconc.exit232
-
-list_Nconc.exit232:                               ; preds = %if.else, %if.end.i224, %for.end.i230
-  %retval.0.i231 = phi %struct.LIST_HELP* [ %varlist.0241, %for.end.i230 ], [ %6, %if.else ], [ %varlist.0241, %if.end.i224 ]
-  %call.i.i219 = tail call i8* @memory_Malloc(i32 8) #1
-  %8 = bitcast i8* %call.i.i219 to %struct.LIST_HELP*
-  %car.i.i220 = getelementptr inbounds i8* %call.i.i219, i32 4
-  %9 = bitcast i8* %car.i.i220 to i8**
-  store i8* %VarTermList.addr.0.idx.val, i8** %9, align 4
-  %cdr.i.i221 = bitcast i8* %call.i.i219 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i221, align 4
-  %cmp.i.i208 = icmp eq %struct.LIST_HELP* %sortlist.0242, null
-  br i1 %cmp.i.i208, label %for.inc, label %if.end.i210
-
-if.end.i210:                                      ; preds = %list_Nconc.exit232
-  %cmp.i18.i209 = icmp eq i8* %call.i.i219, null
-  br i1 %cmp.i18.i209, label %for.inc, label %for.cond.i215
-
-for.cond.i215:                                    ; preds = %if.end.i210, %for.cond.i215
-  %List1.addr.0.i211 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i213, %for.cond.i215 ], [ %sortlist.0242, %if.end.i210 ]
-  %List1.addr.0.idx15.i212 = getelementptr %struct.LIST_HELP* %List1.addr.0.i211, i32 0, i32 0
-  %List1.addr.0.idx15.val.i213 = load %struct.LIST_HELP** %List1.addr.0.idx15.i212, align 4
-  %cmp.i16.i214 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i213, null
-  br i1 %cmp.i16.i214, label %for.end.i216, label %for.cond.i215
-
-for.end.i216:                                     ; preds = %for.cond.i215
-  store %struct.LIST_HELP* %8, %struct.LIST_HELP** %List1.addr.0.idx15.i212, align 4
-  br label %for.inc
-
-for.inc:                                          ; preds = %for.end.i216, %if.end.i210, %list_Nconc.exit232, %list_Nconc.exit178
-  %varlist.1 = phi %struct.LIST_HELP* [ %retval.0.i177, %list_Nconc.exit178 ], [ %retval.0.i231, %list_Nconc.exit232 ], [ %retval.0.i231, %if.end.i210 ], [ %retval.0.i231, %for.end.i216 ]
-  %sortlist.1 = phi %struct.LIST_HELP* [ %sortlist.0242, %list_Nconc.exit178 ], [ %8, %list_Nconc.exit232 ], [ %sortlist.0242, %if.end.i210 ], [ %sortlist.0242, %for.end.i216 ]
-  %L.idx.i = getelementptr %struct.LIST_HELP* %VarTermList.addr.0243, i32 0, i32 0
-  %L.idx.val.i = load %struct.LIST_HELP** %L.idx.i, align 4
-  %10 = bitcast %struct.LIST_HELP* %VarTermList.addr.0243 to i8*
-  %11 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %11, i32 0, i32 4
-  %12 = load i32* %total_size.i.i.i, align 4
-  %13 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i = add i32 %13, %12
-  store i32 %add24.i.i.i, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %11, i32 0, i32 0
-  %14 = load i8** %free.i.i.i, align 4
-  %.c.i.i = bitcast i8* %14 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i, %struct.LIST_HELP** %L.idx.i, align 4
-  %15 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %15, i32 0, i32 0
-  store i8* %10, i8** %free27.i.i.i, align 4
-  %cmp.i = icmp eq %struct.LIST_HELP* %L.idx.val.i, null
-  br i1 %cmp.i, label %for.end, label %for.body
-
-for.end:                                          ; preds = %for.inc, %entry
-  %sortlist.0.lcssa = phi %struct.LIST_HELP* [ null, %entry ], [ %sortlist.1, %for.inc ]
-  %varlist.0.lcssa = phi %struct.LIST_HELP* [ null, %entry ], [ %varlist.1, %for.inc ]
-  %call15 = tail call %struct.LIST_HELP* @list_PointerDeleteDuplicates(%struct.LIST_HELP* %varlist.0.lcssa) #1
-  %cmp.i206238 = icmp eq %struct.LIST_HELP* %call15, null
-  br i1 %cmp.i206238, label %for.end26, label %for.body20
-
-for.body20:                                       ; preds = %for.end, %for.body20
-  %scan.0239 = phi %struct.LIST_HELP* [ %scan.0.idx133.val, %for.body20 ], [ %call15, %for.end ]
-  %scan.0.idx = getelementptr %struct.LIST_HELP* %scan.0239, i32 0, i32 1
-  %scan.0.idx.val = load i8** %scan.0.idx, align 4
-  %16 = ptrtoint i8* %scan.0.idx.val to i32
-  %call23 = tail call %struct.term* @term_Create(i32 %16, %struct.LIST_HELP* null) #1
-  %17 = bitcast %struct.term* %call23 to i8*
-  store i8* %17, i8** %scan.0.idx, align 4
-  %scan.0.idx133 = getelementptr %struct.LIST_HELP* %scan.0239, i32 0, i32 0
-  %scan.0.idx133.val = load %struct.LIST_HELP** %scan.0.idx133, align 4
-  %cmp.i206 = icmp eq %struct.LIST_HELP* %scan.0.idx133.val, null
-  br i1 %cmp.i206, label %for.end26, label %for.body20
-
-for.end26:                                        ; preds = %for.body20, %for.end
-  %cmp.i203 = icmp eq %struct.LIST_HELP* %sortlist.0.lcssa, null
-  br i1 %cmp.i203, label %if.end90, label %if.then29
-
-if.then29:                                        ; preds = %for.end26
-  %18 = load i32* @fol_ALL, align 4
-  %cmp.i201 = icmp eq i32 %18, %Symbol
-  br i1 %cmp.i201, label %if.then33, label %if.else70
-
-if.then33:                                        ; preds = %if.then29
-  %19 = load i32* @fol_OR, align 4
-  %Term.idx134 = getelementptr %struct.term* %Term, i32 0, i32 0
-  %Term.idx134.val = load i32* %Term.idx134, align 4
-  %cmp.i199 = icmp eq i32 %19, %Term.idx134.val
-  br i1 %cmp.i199, label %for.body43, label %if.else53
-
-for.body43:                                       ; preds = %if.then33, %for.body43
-  %scan.1237 = phi %struct.LIST_HELP* [ %scan.1.idx132.val, %for.body43 ], [ %sortlist.0.lcssa, %if.then33 ]
-  %20 = load i32* @fol_NOT, align 4
-  %scan.1.idx = getelementptr %struct.LIST_HELP* %scan.1237, i32 0, i32 1
-  %scan.1.idx.val = load i8** %scan.1.idx, align 4
-  %call.i.i194 = tail call i8* @memory_Malloc(i32 8) #1
-  %21 = bitcast i8* %call.i.i194 to %struct.LIST_HELP*
-  %car.i.i195 = getelementptr inbounds i8* %call.i.i194, i32 4
-  %22 = bitcast i8* %car.i.i195 to i8**
-  store i8* %scan.1.idx.val, i8** %22, align 4
-  %cdr.i.i196 = bitcast i8* %call.i.i194 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i196, align 4
-  %call47 = tail call %struct.term* @term_Create(i32 %20, %struct.LIST_HELP* %21) #1
-  %23 = bitcast %struct.term* %call47 to i8*
-  store i8* %23, i8** %scan.1.idx, align 4
-  %scan.1.idx132 = getelementptr %struct.LIST_HELP* %scan.1237, i32 0, i32 0
-  %scan.1.idx132.val = load %struct.LIST_HELP** %scan.1.idx132, align 4
-  %cmp.i197 = icmp eq %struct.LIST_HELP* %scan.1.idx132.val, null
-  br i1 %cmp.i197, label %if.end.i184, label %for.body43
-
-if.end.i184:                                      ; preds = %for.body43
-  %Term.idx138 = getelementptr %struct.term* %Term, i32 0, i32 2
-  %Term.idx138.val = load %struct.LIST_HELP** %Term.idx138, align 4
-  %cmp.i18.i183 = icmp eq %struct.LIST_HELP* %Term.idx138.val, null
-  br i1 %cmp.i18.i183, label %list_Nconc.exit192, label %for.cond.i189
-
-for.cond.i189:                                    ; preds = %if.end.i184, %for.cond.i189
-  %List1.addr.0.i185 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i187, %for.cond.i189 ], [ %sortlist.0.lcssa, %if.end.i184 ]
-  %List1.addr.0.idx15.i186 = getelementptr %struct.LIST_HELP* %List1.addr.0.i185, i32 0, i32 0
-  %List1.addr.0.idx15.val.i187 = load %struct.LIST_HELP** %List1.addr.0.idx15.i186, align 4
-  %cmp.i16.i188 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i187, null
-  br i1 %cmp.i16.i188, label %for.end.i190, label %for.cond.i189
-
-for.end.i190:                                     ; preds = %for.cond.i189
-  store %struct.LIST_HELP* %Term.idx138.val, %struct.LIST_HELP** %List1.addr.0.idx15.i186, align 4
-  br label %list_Nconc.exit192
-
-list_Nconc.exit192:                               ; preds = %if.end.i184, %for.end.i190
-  store %struct.LIST_HELP* %sortlist.0.lcssa, %struct.LIST_HELP** %Term.idx138, align 4
-  br label %if.end90
-
-if.else53:                                        ; preds = %if.then33
-  %sortlist.0.idx = getelementptr %struct.LIST_HELP* %sortlist.0.lcssa, i32 0, i32 0
-  %sortlist.0.idx.val = load %struct.LIST_HELP** %sortlist.0.idx, align 4
-  %cmp.i179 = icmp eq %struct.LIST_HELP* %sortlist.0.idx.val, null
-  br i1 %cmp.i179, label %if.then57, label %if.else61
-
-if.then57:                                        ; preds = %if.else53
-  %24 = bitcast %struct.term* %Term to i8*
-  %call.i.i162 = tail call i8* @memory_Malloc(i32 8) #1
-  %25 = bitcast i8* %call.i.i162 to %struct.LIST_HELP*
-  %car.i.i163 = getelementptr inbounds i8* %call.i.i162, i32 4
-  %26 = bitcast i8* %car.i.i163 to i8**
-  store i8* %24, i8** %26, align 4
-  %cdr.i.i164 = bitcast i8* %call.i.i162 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i164, align 4
-  store %struct.LIST_HELP* %25, %struct.LIST_HELP** %sortlist.0.idx, align 4
-  %27 = load i32* @fol_IMPLIES, align 4
-  %call60 = tail call %struct.term* @term_Create(i32 %27, %struct.LIST_HELP* %sortlist.0.lcssa) #1
-  br label %if.end90
-
-if.else61:                                        ; preds = %if.else53
-  %28 = load i32* @fol_AND, align 4
-  %call63 = tail call %struct.term* @term_Create(i32 %28, %struct.LIST_HELP* %sortlist.0.lcssa) #1
-  %29 = load i32* @fol_IMPLIES, align 4
-  %30 = bitcast %struct.term* %call63 to i8*
-  %31 = bitcast %struct.term* %Term to i8*
-  %call.i.i158 = tail call i8* @memory_Malloc(i32 8) #1
-  %32 = bitcast i8* %call.i.i158 to %struct.LIST_HELP*
-  %car.i.i159 = getelementptr inbounds i8* %call.i.i158, i32 4
-  %33 = bitcast i8* %car.i.i159 to i8**
-  store i8* %31, i8** %33, align 4
-  %cdr.i.i160 = bitcast i8* %call.i.i158 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i160, align 4
-  %call.i = tail call i8* @memory_Malloc(i32 8) #1
-  %34 = bitcast i8* %call.i to %struct.LIST_HELP*
-  %car.i = getelementptr inbounds i8* %call.i, i32 4
-  %35 = bitcast i8* %car.i to i8**
-  store i8* %30, i8** %35, align 4
-  %cdr.i = bitcast i8* %call.i to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %32, %struct.LIST_HELP** %cdr.i, align 4
-  %call67 = tail call %struct.term* @term_Create(i32 %29, %struct.LIST_HELP* %34) #1
-  br label %if.end90
-
-if.else70:                                        ; preds = %if.then29
-  %36 = load i32* @fol_EXIST, align 4
-  %cmp.i155 = icmp eq i32 %36, %Symbol
-  br i1 %cmp.i155, label %if.then74, label %if.end90
-
-if.then74:                                        ; preds = %if.else70
-  %37 = load i32* @fol_AND, align 4
-  %Term.idx = getelementptr %struct.term* %Term, i32 0, i32 0
-  %Term.idx.val = load i32* %Term.idx, align 4
-  %cmp.i153 = icmp eq i32 %37, %Term.idx.val
-  br i1 %cmp.i153, label %if.end.i144, label %if.end.i
-
-if.end.i144:                                      ; preds = %if.then74
-  %Term.idx137 = getelementptr %struct.term* %Term, i32 0, i32 2
-  %Term.idx137.val = load %struct.LIST_HELP** %Term.idx137, align 4
-  %cmp.i18.i143 = icmp eq %struct.LIST_HELP* %Term.idx137.val, null
-  br i1 %cmp.i18.i143, label %list_Nconc.exit152, label %for.cond.i149
-
-for.cond.i149:                                    ; preds = %if.end.i144, %for.cond.i149
-  %List1.addr.0.i145 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i147, %for.cond.i149 ], [ %sortlist.0.lcssa, %if.end.i144 ]
-  %List1.addr.0.idx15.i146 = getelementptr %struct.LIST_HELP* %List1.addr.0.i145, i32 0, i32 0
-  %List1.addr.0.idx15.val.i147 = load %struct.LIST_HELP** %List1.addr.0.idx15.i146, align 4
-  %cmp.i16.i148 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i147, null
-  br i1 %cmp.i16.i148, label %for.end.i150, label %for.cond.i149
-
-for.end.i150:                                     ; preds = %for.cond.i149
-  store %struct.LIST_HELP* %Term.idx137.val, %struct.LIST_HELP** %List1.addr.0.idx15.i146, align 4
-  br label %list_Nconc.exit152
-
-list_Nconc.exit152:                               ; preds = %if.end.i144, %for.end.i150
-  store %struct.LIST_HELP* %sortlist.0.lcssa, %struct.LIST_HELP** %Term.idx137, align 4
-  br label %if.end90
-
-if.end.i:                                         ; preds = %if.then74
-  %38 = bitcast %struct.term* %Term to i8*
-  %call.i.i139 = tail call i8* @memory_Malloc(i32 8) #1
-  %39 = bitcast i8* %call.i.i139 to %struct.LIST_HELP*
-  %car.i.i140 = getelementptr inbounds i8* %call.i.i139, i32 4
-  %40 = bitcast i8* %car.i.i140 to i8**
-  store i8* %38, i8** %40, align 4
-  %cdr.i.i141 = bitcast i8* %call.i.i139 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i141, align 4
-  %cmp.i18.i = icmp eq i8* %call.i.i139, null
-  br i1 %cmp.i18.i, label %list_Nconc.exit, label %for.cond.i
-
-for.cond.i:                                       ; preds = %if.end.i, %for.cond.i
-  %List1.addr.0.i = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i, %for.cond.i ], [ %sortlist.0.lcssa, %if.end.i ]
-  %List1.addr.0.idx15.i = getelementptr %struct.LIST_HELP* %List1.addr.0.i, i32 0, i32 0
-  %List1.addr.0.idx15.val.i = load %struct.LIST_HELP** %List1.addr.0.idx15.i, align 4
-  %cmp.i16.i = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i, null
-  br i1 %cmp.i16.i, label %for.end.i, label %for.cond.i
-
-for.end.i:                                        ; preds = %for.cond.i
-  store %struct.LIST_HELP* %39, %struct.LIST_HELP** %List1.addr.0.idx15.i, align 4
-  br label %list_Nconc.exit
-
-list_Nconc.exit:                                  ; preds = %if.end.i, %for.end.i
-  %41 = load i32* @fol_AND, align 4
-  %call86 = tail call %struct.term* @term_Create(i32 %41, %struct.LIST_HELP* %sortlist.0.lcssa) #1
-  br label %if.end90
-
-if.end90:                                         ; preds = %if.else70, %for.end26, %if.then57, %if.else61, %list_Nconc.exit192, %list_Nconc.exit152, %list_Nconc.exit
-  %Term.addr.0 = phi %struct.term* [ %Term, %for.end26 ], [ %Term, %list_Nconc.exit192 ], [ %call60, %if.then57 ], [ %call67, %if.else61 ], [ %Term, %list_Nconc.exit152 ], [ %call86, %list_Nconc.exit ], [ %Term, %if.else70 ]
-  %42 = bitcast %struct.term* %Term.addr.0 to i8*
-  %call.i.i = tail call i8* @memory_Malloc(i32 8) #1
-  %43 = bitcast i8* %call.i.i to %struct.LIST_HELP*
-  %car.i.i = getelementptr inbounds i8* %call.i.i, i32 4
-  %44 = bitcast i8* %car.i.i to i8**
-  store i8* %42, i8** %44, align 4
-  %cdr.i.i = bitcast i8* %call.i.i to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i, align 4
-  %call92 = tail call %struct.term* @fol_CreateQuantifier(i32 %Symbol, %struct.LIST_HELP* %call15, %struct.LIST_HELP* %43) #1
-  ret %struct.term* %call92
-}
-
-; Function Attrs: nounwind
-define internal fastcc i32 @dfg_Symbol(i8* %Name, i32 %Arity) #0 {
-entry:
-  %call = tail call i32 @strlen(i8* %Name) #6
-  %cmp = icmp ugt i32 %call, 63
-  br i1 %cmp, label %if.then4, label %if.end
-
-if.end:                                           ; preds = %entry
-  %call2 = tail call i32 @symbol_Lookup(i8* %Name) #1
-  br label %if.end6
-
-if.then4:                                         ; preds = %entry
-  %arrayidx = getelementptr inbounds i8* %Name, i32 63
-  %0 = load i8* %arrayidx, align 1
-  store i8 0, i8* %arrayidx, align 1
-  %call234 = tail call i32 @symbol_Lookup(i8* %Name) #1
-  store i8 %0, i8* %arrayidx, align 1
-  br label %if.end6
-
-if.end6:                                          ; preds = %if.end, %if.then4
-  %call236 = phi i32 [ %call234, %if.then4 ], [ %call2, %if.end ]
-  %cmp7 = icmp eq i32 %call236, 0
-  br i1 %cmp7, label %if.else, label %if.then8
-
-if.then8:                                         ; preds = %if.end6
-  tail call void @string_StringFree(i8* %Name) #1
-  %scan.047.i = load %struct.LIST_HELP** @dfg_SYMBOLLIST, align 4
-  %cmp.i48.i = icmp eq %struct.LIST_HELP* %scan.047.i, null
-  br i1 %cmp.i48.i, label %while.end.i, label %while.body.i
-
-while.cond.i:                                     ; preds = %while.body.i
-  %scan.0.idx35.i = getelementptr %struct.LIST_HELP* %scan.049.i, i32 0, i32 0
-  %scan.0.i = load %struct.LIST_HELP** %scan.0.idx35.i, align 4
-  %cmp.i.i = icmp eq %struct.LIST_HELP* %scan.0.i, null
-  br i1 %cmp.i.i, label %while.end.i, label %while.body.i
-
-while.body.i:                                     ; preds = %if.then8, %while.cond.i
-  %scan.049.i = phi %struct.LIST_HELP* [ %scan.0.i, %while.cond.i ], [ %scan.047.i, %if.then8 ]
-  %scan.0.idx.i = getelementptr %struct.LIST_HELP* %scan.049.i, i32 0, i32 1
-  %scan.0.idx.val.i = load i8** %scan.0.idx.i, align 4
-  %symbol.i = bitcast i8* %scan.0.idx.val.i to i32*
-  %1 = load i32* %symbol.i, align 4
-  %cmp.i = icmp eq i32 %1, %call236
-  br i1 %cmp.i, label %if.then.i, label %while.cond.i
-
-if.then.i:                                        ; preds = %while.body.i
-  %valid.i = getelementptr inbounds i8* %scan.0.idx.val.i, i32 4
-  %2 = bitcast i8* %valid.i to i32*
-  %3 = load i32* %2, align 4
-  %tobool2.i = icmp eq i32 %3, 0
-  %arity9.i = getelementptr inbounds i8* %scan.0.idx.val.i, i32 8
-  %4 = bitcast i8* %arity9.i to i32*
-  br i1 %tobool2.i, label %if.else.i, label %if.then3.i
-
-if.then3.i:                                       ; preds = %if.then.i
-  %5 = load i32* %4, align 4
-  %cmp4.i = icmp eq i32 %5, %Arity
-  br i1 %cmp4.i, label %if.end14, label %if.then5.i
-
-if.then5.i:                                       ; preds = %if.then3.i
-  %6 = load %struct._IO_FILE** @stdout, align 4
-  %call6.i = tail call i32 @fflush(%struct._IO_FILE* %6) #1
-  %7 = load i32* @dfg_LINENUMBER, align 4
-  tail call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([11 x i8]* @.str47, i32 0, i32 0), i32 %7) #1
-  tail call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([21 x i8]* @.str48, i32 0, i32 0), i32 %Arity) #1
-  %sub.i.i43.i = sub nsw i32 0, %call236
-  %8 = load i32* @symbol_TYPESTATBITS, align 4
-  %shr.i.i44.i = ashr i32 %sub.i.i43.i, %8
-  %9 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i45.i = getelementptr inbounds %struct.signature** %9, i32 %shr.i.i44.i
-  %10 = load %struct.signature** %arrayidx.i.i45.i, align 4
-  %name.i46.i = getelementptr inbounds %struct.signature* %10, i32 0, i32 0
-  %11 = load i8** %name.i46.i, align 4
-  tail call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([22 x i8]* @.str49, i32 0, i32 0), i8* %11) #1
-  %12 = load i32* %4, align 4
-  tail call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([30 x i8]* @.str50, i32 0, i32 0), i32 %12) #1
-  tail call fastcc void @misc_Error() #1
-  unreachable
-
-if.else.i:                                        ; preds = %if.then.i
-  store i32 %Arity, i32* %4, align 4
-  store i32 1, i32* %2, align 4
-  br label %if.end14
-
-while.end.i:                                      ; preds = %while.cond.i, %if.then8
-  %sub.i.i39.i = sub nsw i32 0, %call236
-  %13 = load i32* @symbol_TYPESTATBITS, align 4
-  %shr.i.i40.i = ashr i32 %sub.i.i39.i, %13
-  %14 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i41.i = getelementptr inbounds %struct.signature** %14, i32 %shr.i.i40.i
-  %15 = load %struct.signature** %arrayidx.i.i41.i, align 4
-  %arity.i42.i = getelementptr inbounds %struct.signature* %15, i32 0, i32 3
-  %16 = load i32* %arity.i42.i, align 4
-  %cmp15.i = icmp eq i32 %16, %Arity
-  br i1 %cmp15.i, label %if.end14, label %if.then16.i
-
-if.then16.i:                                      ; preds = %while.end.i
-  %17 = load %struct._IO_FILE** @stdout, align 4
-  %call17.i = tail call i32 @fflush(%struct._IO_FILE* %17) #1
-  %18 = load i32* @dfg_LINENUMBER, align 4
-  %19 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i38.i = getelementptr inbounds %struct.signature** %19, i32 %shr.i.i40.i
-  %20 = load %struct.signature** %arrayidx.i.i38.i, align 4
-  %name.i.i = getelementptr inbounds %struct.signature* %20, i32 0, i32 0
-  %21 = load i8** %name.i.i, align 4
-  %arity.i.i = getelementptr inbounds %struct.signature* %20, i32 0, i32 3
-  %22 = load i32* %arity.i.i, align 4
-  tail call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([50 x i8]* @.str51, i32 0, i32 0), i32 %18, i8* %21, i32 %22) #1
-  tail call fastcc void @misc_Error() #1
-  unreachable
-
-if.else:                                          ; preds = %if.end6
-  %cmp9 = icmp eq i32 %Arity, 0
-  br i1 %cmp9, label %if.end12, label %if.then10
-
-if.then10:                                        ; preds = %if.else
-  %23 = load %struct._IO_FILE** @stdout, align 4
-  %call11 = tail call i32 @fflush(%struct._IO_FILE* %23) #1
-  %24 = load i32* @dfg_LINENUMBER, align 4
-  tail call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([33 x i8]* @.str45, i32 0, i32 0), i32 %24, i8* %Name) #1
-  tail call fastcc void @misc_Error()
-  unreachable
-
-if.end12:                                         ; preds = %if.else
-  %scan.064.i = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %cmp.i65.i = icmp eq %struct.LIST_HELP* %scan.064.i, null
-  br i1 %cmp.i65.i, label %if.else.i33, label %while.body.i28
-
-while.body.i28:                                   ; preds = %if.end12, %while.end.i31
-  %scan.066.i = phi %struct.LIST_HELP* [ %scan.0.i29, %while.end.i31 ], [ %scan.064.i, %if.end12 ]
-  %scan.0.idx.i26 = getelementptr %struct.LIST_HELP* %scan.066.i, i32 0, i32 1
-  %scan.0.idx.val.i27 = load i8** %scan.0.idx.i26, align 4
-  %25 = bitcast i8* %scan.0.idx.val.i27 to %struct.LIST_HELP*
-  %cmp.i6062.i = icmp eq i8* %scan.0.idx.val.i27, null
-  br i1 %cmp.i6062.i, label %while.end.i31, label %land.rhs9.i
-
-land.rhs9.i:                                      ; preds = %while.body.i28, %while.body15.i
-  %scan2.163.i = phi %struct.LIST_HELP* [ %scan2.1.idx48.val.i, %while.body15.i ], [ %25, %while.body.i28 ]
-  %scan2.1.idx.i = getelementptr %struct.LIST_HELP* %scan2.163.i, i32 0, i32 1
-  %scan2.1.idx.val.i = load i8** %scan2.1.idx.i, align 4
-  %.idx49.i = bitcast i8* %scan2.1.idx.val.i to i8**
-  %.idx49.val.i = load i8** %.idx49.i, align 4
-  %call.i57.i = tail call i32 @strcmp(i8* %.idx49.val.i, i8* %Name) #1
-  %cmp.i58.i = icmp eq i32 %call.i57.i, 0
-  br i1 %cmp.i58.i, label %while.end.i31, label %while.body15.i
-
-while.body15.i:                                   ; preds = %land.rhs9.i
-  %scan2.1.idx48.i = getelementptr %struct.LIST_HELP* %scan2.163.i, i32 0, i32 0
-  %scan2.1.idx48.val.i = load %struct.LIST_HELP** %scan2.1.idx48.i, align 4
-  %cmp.i60.i = icmp eq %struct.LIST_HELP* %scan2.1.idx48.val.i, null
-  br i1 %cmp.i60.i, label %while.end.i31, label %land.rhs9.i
-
-while.end.i31:                                    ; preds = %while.body15.i, %land.rhs9.i, %while.body.i28
-  %scan2.1.lcssa.i = phi %struct.LIST_HELP* [ %25, %while.body.i28 ], [ null, %while.body15.i ], [ %scan2.163.i, %land.rhs9.i ]
-  %scan.0.idx47.i = getelementptr %struct.LIST_HELP* %scan.066.i, i32 0, i32 0
-  %scan.0.i29 = load %struct.LIST_HELP** %scan.0.idx47.i, align 4
-  %cmp.i.i30 = icmp ne %struct.LIST_HELP* %scan.0.i29, null
-  %cmp.i53.i = icmp eq %struct.LIST_HELP* %scan2.1.lcssa.i, null
-  %or.cond.i = and i1 %cmp.i.i30, %cmp.i53.i
-  br i1 %or.cond.i, label %while.body.i28, label %while.end18.i
-
-while.end18.i:                                    ; preds = %while.end.i31
-  br i1 %cmp.i53.i, label %if.else.i33, label %if.then.i32
-
-if.then.i32:                                      ; preds = %while.end18.i
-  tail call void @string_StringFree(i8* %Name) #1
-  %scan2.0.idx.i = getelementptr %struct.LIST_HELP* %scan2.1.lcssa.i, i32 0, i32 1
-  %scan2.0.idx.val.i = load i8** %scan2.0.idx.i, align 4
-  br label %dfg_VarLookup.exit
-
-if.else.i33:                                      ; preds = %while.end18.i, %if.end12
-  %.b.i = load i1* @dfg_VARDECL, align 1
-  br i1 %.b.i, label %if.then24.i, label %if.else31.i
-
-if.then24.i:                                      ; preds = %if.else.i33
-  %call.i52.i = tail call i8* @memory_Malloc(i32 8) #1
-  %name.i = bitcast i8* %call.i52.i to i8**
-  store i8* %Name, i8** %name.i, align 4
-  %26 = load i32* @symbol_STANDARDVARCOUNTER, align 4
-  %inc.i.i = add nsw i32 %26, 1
-  store i32 %inc.i.i, i32* @symbol_STANDARDVARCOUNTER, align 4
-  %symbol27.i = getelementptr inbounds i8* %call.i52.i, i32 4
-  %27 = bitcast i8* %symbol27.i to i32*
-  store i32 %inc.i.i, i32* %27, align 4
-  %28 = load %struct.LIST_HELP** @dfg_VARLIST, align 4
-  %.idx.i = getelementptr %struct.LIST_HELP* %28, i32 0, i32 1
-  %.idx.val.i = load i8** %.idx.i, align 4
-  %29 = bitcast i8* %.idx.val.i to %struct.LIST_HELP*
-  %call.i.i = tail call i8* @memory_Malloc(i32 8) #1
-  %car.i51.i = getelementptr inbounds i8* %call.i.i, i32 4
-  %30 = bitcast i8* %car.i51.i to i8**
-  store i8* %call.i52.i, i8** %30, align 4
-  %cdr.i.i = bitcast i8* %call.i.i to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %29, %struct.LIST_HELP** %cdr.i.i, align 4
-  store i8* %call.i.i, i8** %.idx.i, align 4
-  br label %dfg_VarLookup.exit
-
-if.else31.i:                                      ; preds = %if.else.i33
-  %31 = load %struct._IO_FILE** @stdout, align 4
-  %call32.i = tail call i32 @fflush(%struct._IO_FILE* %31) #1
-  %32 = load i32* @dfg_LINENUMBER, align 4
-  tail call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([30 x i8]* @.str46, i32 0, i32 0), i32 %32, i8* %Name) #1
-  tail call fastcc void @misc_Error() #1
-  unreachable
-
-dfg_VarLookup.exit:                               ; preds = %if.then.i32, %if.then24.i
-  %call.i52.pn.i = phi i8* [ %call.i52.i, %if.then24.i ], [ %scan2.0.idx.val.i, %if.then.i32 ]
-  %symbol.0.in.in.i = getelementptr i8* %call.i52.pn.i, i32 4
-  %symbol.0.in.i = bitcast i8* %symbol.0.in.in.i to i32*
-  %symbol.0.i = load i32* %symbol.0.in.i, align 4
-  br label %if.end14
-
-if.end14:                                         ; preds = %while.end.i, %if.else.i, %if.then3.i, %dfg_VarLookup.exit
-  %symbol.0 = phi i32 [ %symbol.0.i, %dfg_VarLookup.exit ], [ %call236, %if.then3.i ], [ %call236, %if.else.i ], [ %call236, %while.end.i ]
-  ret i32 %symbol.0
-}
-
-declare %struct.LIST_HELP* @list_NReverse(%struct.LIST_HELP*) #2
-
-declare %struct.term* @term_Create(i32, %struct.LIST_HELP*) #2
-
-declare i8* @string_IntToString(i32) #2
-
-declare i8* @string_StringCopy(i8*) #2
-
-; Function Attrs: nounwind
-declare i32 @fflush(%struct._IO_FILE* nocapture) #0
-
-declare void @misc_UserErrorReport(i8*, ...) #2
-
-; Function Attrs: inlinehint noreturn nounwind
-define internal fastcc void @misc_Error() #3 {
-entry:
-  %0 = load %struct._IO_FILE** @stderr, align 4
-  %call = tail call i32 @fflush(%struct._IO_FILE* %0) #1
-  %1 = load %struct._IO_FILE** @stdout, align 4
-  %call1 = tail call i32 @fflush(%struct._IO_FILE* %1) #1
-  %2 = load %struct._IO_FILE** @stderr, align 4
-  %call2 = tail call i32 @fflush(%struct._IO_FILE* %2) #1
-  tail call void @exit(i32 1) #7
-  unreachable
-}
-
-declare i32 @clause_GetOriginFromString(i8*) #2
-
-declare void @term_Delete(%struct.term*) #2
-
-declare i32 @string_StringToInt(i8*, i32, i32*) #2
-
-declare i32 @symbol_Lookup(i8*) #2
-
-declare i32 @flag_Id(i8*) #2
-
-; Function Attrs: nounwind readonly
-declare i32 @strlen(i8* nocapture) #4
-
-; Function Attrs: nounwind
-declare i8* @stpcpy(i8*, i8* nocapture) #0
-
-; Function Attrs: noreturn nounwind
-define void @dfg_error(i8* %s) #5 {
-entry:
-  %0 = load %struct._IO_FILE** @stdout, align 4
-  %call = tail call i32 @fflush(%struct._IO_FILE* %0) #1
-  %1 = load i32* @dfg_LINENUMBER, align 4
-  tail call void (i8*, ...)* @misc_UserErrorReport(i8* getelementptr inbounds ([15 x i8]* @.str22, i32 0, i32 0), i32 %1, i8* %s) #1
-  tail call fastcc void @misc_Error()
-  unreachable
-}
-
-; Function Attrs: nounwind
-declare void @llvm.lifetime.end(i64, i8* nocapture) #1
-
-; Function Attrs: nounwind
-define void @dfg_Free() #0 {
-entry:
-  %0 = load i8** @dfg_DESC.0, align 4
-  %cmp = icmp eq i8* %0, null
-  br i1 %cmp, label %if.end, label %if.then
-
-if.then:                                          ; preds = %entry
-  tail call void @string_StringFree(i8* %0) #1
-  br label %if.end
-
-if.end:                                           ; preds = %entry, %if.then
-  %1 = load i8** @dfg_DESC.1, align 4
-  %cmp1 = icmp eq i8* %1, null
-  br i1 %cmp1, label %if.end3, label %if.then2
-
-if.then2:                                         ; preds = %if.end
-  tail call void @string_StringFree(i8* %1) #1
-  br label %if.end3
-
-if.end3:                                          ; preds = %if.end, %if.then2
-  %2 = load i8** @dfg_DESC.2, align 4
-  %cmp4 = icmp eq i8* %2, null
-  br i1 %cmp4, label %if.end6, label %if.then5
-
-if.then5:                                         ; preds = %if.end3
-  tail call void @string_StringFree(i8* %2) #1
-  br label %if.end6
-
-if.end6:                                          ; preds = %if.end3, %if.then5
-  %3 = load i8** @dfg_DESC.3, align 4
-  %cmp7 = icmp eq i8* %3, null
-  br i1 %cmp7, label %if.end9, label %if.then8
-
-if.then8:                                         ; preds = %if.end6
-  tail call void @string_StringFree(i8* %3) #1
-  br label %if.end9
-
-if.end9:                                          ; preds = %if.end6, %if.then8
-  %4 = load i8** @dfg_DESC.5, align 4
-  %cmp10 = icmp eq i8* %4, null
-  br i1 %cmp10, label %if.end12, label %if.then11
-
-if.then11:                                        ; preds = %if.end9
-  tail call void @string_StringFree(i8* %4) #1
-  br label %if.end12
-
-if.end12:                                         ; preds = %if.end9, %if.then11
-  %5 = load i8** @dfg_DESC.6, align 4
-  %cmp13 = icmp eq i8* %5, null
-  br i1 %cmp13, label %if.end15, label %if.then14
-
-if.then14:                                        ; preds = %if.end12
-  tail call void @string_StringFree(i8* %5) #1
-  br label %if.end15
-
-if.end15:                                         ; preds = %if.end12, %if.then14
-  ret void
-}
-
-; Function Attrs: nounwind readonly
-define i8* @dfg_ProblemName() #4 {
-entry:
-  %0 = load i8** @dfg_DESC.0, align 4
-  ret i8* %0
-}
-
-; Function Attrs: nounwind readonly
-define i8* @dfg_ProblemAuthor() #4 {
-entry:
-  %0 = load i8** @dfg_DESC.1, align 4
-  ret i8* %0
-}
-
-; Function Attrs: nounwind readonly
-define i8* @dfg_ProblemVersion() #4 {
-entry:
-  %0 = load i8** @dfg_DESC.2, align 4
-  ret i8* %0
-}
-
-; Function Attrs: nounwind readonly
-define i8* @dfg_ProblemLogic() #4 {
-entry:
-  %0 = load i8** @dfg_DESC.3, align 4
-  ret i8* %0
-}
-
-; Function Attrs: nounwind readonly
-define i32 @dfg_ProblemStatus() #4 {
-entry:
-  %0 = load i32* @dfg_DESC.4, align 4
-  ret i32 %0
-}
-
-; Function Attrs: nounwind
-define i8* @dfg_ProblemStatusString() #0 {
-entry:
-  %0 = load i32* @dfg_DESC.4, align 4
-  switch i32 %0, label %sw.default [
-    i32 0, label %sw.epilog
-    i32 1, label %sw.bb1
-    i32 2, label %sw.bb2
-  ]
-
-sw.bb1:                                           ; preds = %entry
-  br label %sw.epilog
-
-sw.bb2:                                           ; preds = %entry
-  br label %sw.epilog
-
-sw.default:                                       ; preds = %entry
-  %1 = load %struct._IO_FILE** @stdout, align 4
-  %call = tail call i32 @fflush(%struct._IO_FILE* %1) #1
-  %2 = load %struct._IO_FILE** @stderr, align 4
-  %call3 = tail call i32 (%struct._IO_FILE*, i8*, ...)* @fprintf(%struct._IO_FILE* %2, i8* getelementptr inbounds ([31 x i8]* @.str27, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str28, i32 0, i32 0), i32 1025) #1
-  tail call void (i8*, ...)* @misc_ErrorReport(i8* getelementptr inbounds ([47 x i8]* @.str29, i32 0, i32 0)) #1
-  %3 = load %struct._IO_FILE** @stderr, align 4
-  %4 = tail call i32 @fwrite(i8* getelementptr inbounds ([133 x i8]* @.str30, i32 0, i32 0), i32 132, i32 1, %struct._IO_FILE* %3)
-  tail call fastcc void @misc_DumpCore()
-  unreachable
-
-sw.epilog:                                        ; preds = %entry, %sw.bb2, %sw.bb1
-  %result.0 = phi i8* [ getelementptr inbounds ([8 x i8]* @.str26, i32 0, i32 0), %sw.bb2 ], [ getelementptr inbounds ([14 x i8]* @.str25, i32 0, i32 0), %sw.bb1 ], [ getelementptr inbounds ([12 x i8]* @.str24, i32 0, i32 0), %entry ]
-  ret i8* %result.0
-}
-
-; Function Attrs: nounwind
-declare i32 @fprintf(%struct._IO_FILE* nocapture, i8* nocapture, ...) #0
-
-declare void @misc_ErrorReport(i8*, ...) #2
-
-; Function Attrs: nounwind
-declare i32 @fputs(i8* nocapture, %struct._IO_FILE* nocapture) #0
-
-; Function Attrs: inlinehint noreturn nounwind
-define internal fastcc void @misc_DumpCore() #3 {
-entry:
-  %0 = load %struct._IO_FILE** @stderr, align 4
-  %1 = tail call i32 @fwrite(i8* getelementptr inbounds ([3 x i8]* @.str59, i32 0, i32 0), i32 2, i32 1, %struct._IO_FILE* %0)
-  %2 = load %struct._IO_FILE** @stderr, align 4
-  %call1 = tail call i32 @fflush(%struct._IO_FILE* %2) #1
-  %3 = load %struct._IO_FILE** @stdout, align 4
-  %call2 = tail call i32 @fflush(%struct._IO_FILE* %3) #1
-  %4 = load %struct._IO_FILE** @stderr, align 4
-  %call3 = tail call i32 @fflush(%struct._IO_FILE* %4) #1
-  tail call void @abort() #7
-  unreachable
-}
-
-; Function Attrs: nounwind readonly
-define i8* @dfg_ProblemDescription() #4 {
-entry:
-  %0 = load i8** @dfg_DESC.5, align 4
-  ret i8* %0
-}
-
-; Function Attrs: nounwind readonly
-define i8* @dfg_ProblemDate() #4 {
-entry:
-  %0 = load i8** @dfg_DESC.6, align 4
-  ret i8* %0
-}
-
-; Function Attrs: nounwind
-define void @dfg_FPrintDescription(%struct._IO_FILE* %File) #0 {
-entry:
-  %0 = tail call i32 @fwrite(i8* getelementptr inbounds ([30 x i8]* @.str31, i32 0, i32 0), i32 29, i32 1, %struct._IO_FILE* %File)
-  %1 = load i8** @dfg_DESC.0, align 4
-  %cmp = icmp eq i8* %1, null
-  br i1 %cmp, label %if.else, label %if.then
-
-if.then:                                          ; preds = %entry
-  %call1 = tail call i32 @fputs(i8* %1, %struct._IO_FILE* %File) #1
-  br label %if.end
-
-if.else:                                          ; preds = %entry
-  %2 = tail call i32 @fwrite(i8* getelementptr inbounds ([6 x i8]* @.str32, i32 0, i32 0), i32 5, i32 1, %struct._IO_FILE* %File)
-  br label %if.end
-
-if.end:                                           ; preds = %if.else, %if.then
-  %3 = tail call i32 @fwrite(i8* getelementptr inbounds ([13 x i8]* @.str33, i32 0, i32 0), i32 12, i32 1, %struct._IO_FILE* %File)
-  %4 = load i8** @dfg_DESC.1, align 4
-  %cmp4 = icmp eq i8* %4, null
-  br i1 %cmp4, label %if.else7, label %if.then5
-
-if.then5:                                         ; preds = %if.end
-  %call6 = tail call i32 @fputs(i8* %4, %struct._IO_FILE* %File) #1
-  br label %if.end9
-
-if.else7:                                         ; preds = %if.end
-  %5 = tail call i32 @fwrite(i8* getelementptr inbounds ([6 x i8]* @.str32, i32 0, i32 0), i32 5, i32 1, %struct._IO_FILE* %File)
-  br label %if.end9
-
-if.end9:                                          ; preds = %if.else7, %if.then5
-  %6 = tail call i32 @fwrite(i8* getelementptr inbounds ([4 x i8]* @.str34, i32 0, i32 0), i32 3, i32 1, %struct._IO_FILE* %File)
-  %7 = load i8** @dfg_DESC.2, align 4
-  %cmp11 = icmp eq i8* %7, null
-  br i1 %cmp11, label %if.end16, label %if.then12
-
-if.then12:                                        ; preds = %if.end9
-  %8 = tail call i32 @fwrite(i8* getelementptr inbounds ([11 x i8]* @.str35, i32 0, i32 0), i32 10, i32 1, %struct._IO_FILE* %File)
-  %9 = load i8** @dfg_DESC.2, align 4
-  %call14 = tail call i32 @fputs(i8* %9, %struct._IO_FILE* %File) #1
-  %10 = tail call i32 @fwrite(i8* getelementptr inbounds ([4 x i8]* @.str34, i32 0, i32 0), i32 3, i32 1, %struct._IO_FILE* %File)
-  br label %if.end16
-
-if.end16:                                         ; preds = %if.end9, %if.then12
-  %11 = load i8** @dfg_DESC.3, align 4
-  %cmp17 = icmp eq i8* %11, null
-  br i1 %cmp17, label %if.end22, label %if.then18
-
-if.then18:                                        ; preds = %if.end16
-  %12 = tail call i32 @fwrite(i8* getelementptr inbounds ([9 x i8]* @.str36, i32 0, i32 0), i32 8, i32 1, %struct._IO_FILE* %File)
-  %13 = load i8** @dfg_DESC.3, align 4
-  %call20 = tail call i32 @fputs(i8* %13, %struct._IO_FILE* %File) #1
-  %14 = tail call i32 @fwrite(i8* getelementptr inbounds ([4 x i8]* @.str34, i32 0, i32 0), i32 3, i32 1, %struct._IO_FILE* %File)
-  br label %if.end22
-
-if.end22:                                         ; preds = %if.end16, %if.then18
-  %15 = tail call i32 @fwrite(i8* getelementptr inbounds ([10 x i8]* @.str37, i32 0, i32 0), i32 9, i32 1, %struct._IO_FILE* %File)
-  %16 = load i32* @dfg_DESC.4, align 4
-  switch i32 %16, label %sw.default.i [
-    i32 0, label %dfg_ProblemStatusString.exit
-    i32 1, label %sw.bb1.i
-    i32 2, label %sw.bb2.i
-  ]
-
-sw.bb1.i:                                         ; preds = %if.end22
-  br label %dfg_ProblemStatusString.exit
-
-sw.bb2.i:                                         ; preds = %if.end22
-  br label %dfg_ProblemStatusString.exit
-
-sw.default.i:                                     ; preds = %if.end22
-  %17 = load %struct._IO_FILE** @stdout, align 4
-  %call.i = tail call i32 @fflush(%struct._IO_FILE* %17) #1
-  %18 = load %struct._IO_FILE** @stderr, align 4
-  %call3.i = tail call i32 (%struct._IO_FILE*, i8*, ...)* @fprintf(%struct._IO_FILE* %18, i8* getelementptr inbounds ([31 x i8]* @.str27, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8]* @.str28, i32 0, i32 0), i32 1025) #1
-  tail call void (i8*, ...)* @misc_ErrorReport(i8* getelementptr inbounds ([47 x i8]* @.str29, i32 0, i32 0)) #1
-  %19 = load %struct._IO_FILE** @stderr, align 4
-  %20 = tail call i32 @fwrite(i8* getelementptr inbounds ([133 x i8]* @.str30, i32 0, i32 0), i32 132, i32 1, %struct._IO_FILE* %19) #1
-  tail call fastcc void @misc_DumpCore() #1
-  unreachable
-
-dfg_ProblemStatusString.exit:                     ; preds = %if.end22, %sw.bb1.i, %sw.bb2.i
-  %result.0.i = phi i8* [ getelementptr inbounds ([8 x i8]* @.str26, i32 0, i32 0), %sw.bb2.i ], [ getelementptr inbounds ([14 x i8]* @.str25, i32 0, i32 0), %sw.bb1.i ], [ getelementptr inbounds ([12 x i8]* @.str24, i32 0, i32 0), %if.end22 ]
-  %call25 = tail call i32 @fputs(i8* %result.0.i, %struct._IO_FILE* %File) #1
-  %21 = tail call i32 @fwrite(i8* getelementptr inbounds ([18 x i8]* @.str38, i32 0, i32 0), i32 17, i32 1, %struct._IO_FILE* %File)
-  %22 = load i8** @dfg_DESC.5, align 4
-  %cmp27 = icmp eq i8* %22, null
-  br i1 %cmp27, label %if.else30, label %if.then28
-
-if.then28:                                        ; preds = %dfg_ProblemStatusString.exit
-  %call29 = tail call i32 @fputs(i8* %22, %struct._IO_FILE* %File) #1
-  br label %if.end32
-
-if.else30:                                        ; preds = %dfg_ProblemStatusString.exit
-  %23 = tail call i32 @fwrite(i8* getelementptr inbounds ([6 x i8]* @.str32, i32 0, i32 0), i32 5, i32 1, %struct._IO_FILE* %File)
-  br label %if.end32
-
-if.end32:                                         ; preds = %if.else30, %if.then28
-  %24 = tail call i32 @fwrite(i8* getelementptr inbounds ([4 x i8]* @.str34, i32 0, i32 0), i32 3, i32 1, %struct._IO_FILE* %File)
-  %25 = load i8** @dfg_DESC.6, align 4
-  %cmp34 = icmp eq i8* %25, null
-  br i1 %cmp34, label %if.end39, label %if.then35
-
-if.then35:                                        ; preds = %if.end32
-  %26 = tail call i32 @fwrite(i8* getelementptr inbounds ([8 x i8]* @.str39, i32 0, i32 0), i32 7, i32 1, %struct._IO_FILE* %File)
-  %27 = load i8** @dfg_DESC.6, align 4
-  %call37 = tail call i32 @fputs(i8* %27, %struct._IO_FILE* %File) #1
-  %28 = tail call i32 @fwrite(i8* getelementptr inbounds ([4 x i8]* @.str34, i32 0, i32 0), i32 3, i32 1, %struct._IO_FILE* %File)
-  br label %if.end39
-
-if.end39:                                         ; preds = %if.end32, %if.then35
-  %29 = tail call i32 @fwrite(i8* getelementptr inbounds ([13 x i8]* @.str40, i32 0, i32 0), i32 12, i32 1, %struct._IO_FILE* %File)
-  ret void
-}
-
-; Function Attrs: nounwind
-define %struct.LIST_HELP* @dfg_DFGParser(%struct._IO_FILE* %File, i32* %Flags, i32* %Precedence, %struct.LIST_HELP** nocapture %Axioms, %struct.LIST_HELP** nocapture %Conjectures, %struct.LIST_HELP** nocapture %SortDecl, %struct.LIST_HELP** nocapture %UserDefinedPrecedence) #0 {
-entry:
-  store %struct._IO_FILE* %File, %struct._IO_FILE** @dfg_in, align 4
-  store i32 1, i32* @dfg_LINENUMBER, align 4
-  store i32 1, i32* @dfg_IGNORETEXT, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_AXIOMLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_CONJECLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_SORTDECLLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_USERPRECEDENCE, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_CONCLAUSES, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_PROOFLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_TERMLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_SYMBOLLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_VARLIST, align 4
-  store i1 false, i1* @dfg_VARDECL, align 1
-  store i32 0, i32* @dfg_IGNORE, align 4
-  store i32* %Flags, i32** @dfg_FLAGS, align 4
-  store i32* %Precedence, i32** @dfg_PRECEDENCE, align 4
-  store i8* null, i8** @dfg_DESC.0, align 4
-  store i8* null, i8** @dfg_DESC.1, align 4
-  store i8* null, i8** @dfg_DESC.2, align 4
-  store i8* null, i8** @dfg_DESC.3, align 4
-  store i32 2, i32* @dfg_DESC.4, align 4
-  store i8* null, i8** @dfg_DESC.5, align 4
-  store i8* null, i8** @dfg_DESC.6, align 4
-  %call1 = tail call i32 @dfg_parse()
-  %0 = load %struct.LIST_HELP** @dfg_SYMBOLLIST, align 4
-  %cmp.i13.i = icmp eq %struct.LIST_HELP* %0, null
-  br i1 %cmp.i13.i, label %for.cond.preheader, label %while.body.lr.ph.i
-
-while.body.lr.ph.i:                               ; preds = %entry
-  %1 = load i32* @symbol_TYPESTATBITS, align 4
-  br label %while.body.i
-
-while.body.i:                                     ; preds = %if.end.i109, %while.body.lr.ph.i
-  %2 = phi %struct.LIST_HELP* [ %0, %while.body.lr.ph.i ], [ %L.idx.val.i.i, %if.end.i109 ]
-  %.idx.i = getelementptr %struct.LIST_HELP* %2, i32 0, i32 1
-  %.idx.val.i = load i8** %.idx.i, align 4
-  %symbol.i = bitcast i8* %.idx.val.i to i32*
-  %3 = load i32* %symbol.i, align 4
-  %arity.i = getelementptr inbounds i8* %.idx.val.i, i32 8
-  %4 = bitcast i8* %arity.i to i32*
-  %5 = load i32* %4, align 4
-  %sub.i.i9.i = sub nsw i32 0, %3
-  %shr.i.i10.i = ashr i32 %sub.i.i9.i, %1
-  %6 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i11.i = getelementptr inbounds %struct.signature** %6, i32 %shr.i.i10.i
-  %7 = load %struct.signature** %arrayidx.i.i11.i, align 4
-  %arity.i12.i = getelementptr inbounds %struct.signature* %7, i32 0, i32 3
-  %8 = load i32* %arity.i12.i, align 4
-  %cmp.i = icmp eq i32 %5, %8
-  br i1 %cmp.i, label %if.end.i109, label %if.then.i
-
-if.then.i:                                        ; preds = %while.body.i
-  store i32 %5, i32* %arity.i12.i, align 4
-  br label %if.end.i109
-
-if.end.i109:                                      ; preds = %if.then.i, %while.body.i
-  %9 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 12), align 4
-  %total_size.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %9, i32 0, i32 4
-  %10 = load i32* %total_size.i.i.i, align 4
-  %11 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i = add i32 %11, %10
-  store i32 %add24.i.i.i, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %9, i32 0, i32 0
-  %12 = load i8** %free.i.i.i, align 4
-  %.c.i.i = ptrtoint i8* %12 to i32
-  store i32 %.c.i.i, i32* %symbol.i, align 4
-  %13 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 12), align 4
-  %free27.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %13, i32 0, i32 0
-  store i8* %.idx.val.i, i8** %free27.i.i.i, align 4
-  %14 = load %struct.LIST_HELP** @dfg_SYMBOLLIST, align 4
-  %L.idx.i.i = getelementptr %struct.LIST_HELP* %14, i32 0, i32 0
-  %L.idx.val.i.i = load %struct.LIST_HELP** %L.idx.i.i, align 4
-  %15 = bitcast %struct.LIST_HELP* %14 to i8*
-  %16 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %16, i32 0, i32 4
-  %17 = load i32* %total_size.i.i.i.i, align 4
-  %18 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i = add i32 %18, %17
-  store i32 %add24.i.i.i.i, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %16, i32 0, i32 0
-  %19 = load i8** %free.i.i.i.i, align 4
-  %.c.i.i.i = bitcast i8* %19 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i, %struct.LIST_HELP** %L.idx.i.i, align 4
-  %20 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %20, i32 0, i32 0
-  store i8* %15, i8** %free27.i.i.i.i, align 4
-  store %struct.LIST_HELP* %L.idx.val.i.i, %struct.LIST_HELP** @dfg_SYMBOLLIST, align 4
-  %cmp.i.i108 = icmp eq %struct.LIST_HELP* %L.idx.val.i.i, null
-  br i1 %cmp.i.i108, label %for.cond.preheader, label %while.body.i
-
-for.cond.preheader:                               ; preds = %if.end.i109, %entry
-  %scan.0127 = load %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  %cmp.i115128 = icmp eq %struct.LIST_HELP* %scan.0127, null
-  br i1 %cmp.i115128, label %for.end, label %for.body
-
-for.body:                                         ; preds = %for.cond.preheader, %if.end
-  %scan.0129 = phi %struct.LIST_HELP* [ %scan.0, %if.end ], [ %scan.0127, %for.cond.preheader ]
-  %scan.0.idx = getelementptr %struct.LIST_HELP* %scan.0129, i32 0, i32 1
-  %scan.0.idx.val = load i8** %scan.0.idx, align 4
-  %.idx59 = bitcast i8* %scan.0.idx.val to %struct.LIST_HELP**
-  %.idx59.val = load %struct.LIST_HELP** %.idx59, align 4
-  %21 = bitcast %struct.LIST_HELP* %.idx59.val to %struct.term*
-  %call5 = tail call %struct.CLAUSE_HELP* @dfg_CreateClauseFromTerm(%struct.term* %21, i32 1, i32* %Flags, i32* %Precedence)
-  %22 = bitcast %struct.CLAUSE_HELP* %call5 to i8*
-  store i8* %22, i8** %scan.0.idx, align 4
-  %.idx63 = getelementptr i8* %scan.0.idx.val, i32 4
-  %23 = bitcast i8* %.idx63 to i8**
-  %.idx63.val = load i8** %23, align 4
-  %cmp = icmp eq i8* %.idx63.val, null
-  br i1 %cmp, label %if.end, label %if.then
-
-if.then:                                          ; preds = %for.body
-  tail call void @string_StringFree(i8* %.idx63.val) #1
-  br label %if.end
-
-if.end:                                           ; preds = %for.body, %if.then
-  %24 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i118 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %24, i32 0, i32 4
-  %25 = load i32* %total_size.i.i.i118, align 4
-  %26 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i119 = add i32 %26, %25
-  store i32 %add24.i.i.i119, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i120 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %24, i32 0, i32 0
-  %27 = load i8** %free.i.i.i120, align 4
-  %.c.i.i121 = bitcast i8* %27 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i121, %struct.LIST_HELP** %.idx59, align 4
-  %28 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i122 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %28, i32 0, i32 0
-  store i8* %scan.0.idx.val, i8** %free27.i.i.i122, align 4
-  %scan.0.idx58 = getelementptr %struct.LIST_HELP* %scan.0129, i32 0, i32 0
-  %scan.0 = load %struct.LIST_HELP** %scan.0.idx58, align 4
-  %cmp.i115 = icmp eq %struct.LIST_HELP* %scan.0, null
-  br i1 %cmp.i115, label %for.cond.for.end_crit_edge, label %for.body
-
-for.cond.for.end_crit_edge:                       ; preds = %if.end
-  %.pre = load %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  br label %for.end
-
-for.end:                                          ; preds = %for.cond.for.end_crit_edge, %for.cond.preheader
-  %29 = phi %struct.LIST_HELP* [ %.pre, %for.cond.for.end_crit_edge ], [ null, %for.cond.preheader ]
-  %call9 = tail call %struct.LIST_HELP* @list_PointerDeleteElement(%struct.LIST_HELP* %29, i8* null) #1
-  store %struct.LIST_HELP* %call9, %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  %scan.1124 = load %struct.LIST_HELP** @dfg_CONCLAUSES, align 4
-  %cmp.i116125 = icmp eq %struct.LIST_HELP* %scan.1124, null
-  br i1 %cmp.i116125, label %for.end25, label %for.body14
-
-for.body14:                                       ; preds = %for.end, %if.end22
-  %scan.1126 = phi %struct.LIST_HELP* [ %scan.1, %if.end22 ], [ %scan.1124, %for.end ]
-  %scan.1.idx = getelementptr %struct.LIST_HELP* %scan.1126, i32 0, i32 1
-  %scan.1.idx.val = load i8** %scan.1.idx, align 4
-  %.idx = bitcast i8* %scan.1.idx.val to %struct.LIST_HELP**
-  %.idx.val = load %struct.LIST_HELP** %.idx, align 4
-  %30 = bitcast %struct.LIST_HELP* %.idx.val to %struct.term*
-  %call17 = tail call %struct.CLAUSE_HELP* @dfg_CreateClauseFromTerm(%struct.term* %30, i32 0, i32* %Flags, i32* %Precedence)
-  %31 = bitcast %struct.CLAUSE_HELP* %call17 to i8*
-  store i8* %31, i8** %scan.1.idx, align 4
-  %.idx61 = getelementptr i8* %scan.1.idx.val, i32 4
-  %32 = bitcast i8* %.idx61 to i8**
-  %.idx61.val = load i8** %32, align 4
-  %cmp19 = icmp eq i8* %.idx61.val, null
-  br i1 %cmp19, label %if.end22, label %if.then20
-
-if.then20:                                        ; preds = %for.body14
-  tail call void @string_StringFree(i8* %.idx61.val) #1
-  br label %if.end22
-
-if.end22:                                         ; preds = %for.body14, %if.then20
-  %33 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i110 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %33, i32 0, i32 4
-  %34 = load i32* %total_size.i.i.i110, align 4
-  %35 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i111 = add i32 %35, %34
-  store i32 %add24.i.i.i111, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i112 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %33, i32 0, i32 0
-  %36 = load i8** %free.i.i.i112, align 4
-  %.c.i.i113 = bitcast i8* %36 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i113, %struct.LIST_HELP** %.idx, align 4
-  %37 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i114 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %37, i32 0, i32 0
-  store i8* %scan.1.idx.val, i8** %free27.i.i.i114, align 4
-  %scan.1.idx57 = getelementptr %struct.LIST_HELP* %scan.1126, i32 0, i32 0
-  %scan.1 = load %struct.LIST_HELP** %scan.1.idx57, align 4
-  %cmp.i116 = icmp eq %struct.LIST_HELP* %scan.1, null
-  br i1 %cmp.i116, label %for.cond10.for.end25_crit_edge, label %for.body14
-
-for.cond10.for.end25_crit_edge:                   ; preds = %if.end22
-  %.pre130 = load %struct.LIST_HELP** @dfg_CONCLAUSES, align 4
-  br label %for.end25
-
-for.end25:                                        ; preds = %for.cond10.for.end25_crit_edge, %for.end
-  %38 = phi %struct.LIST_HELP* [ %.pre130, %for.cond10.for.end25_crit_edge ], [ null, %for.end ]
-  %call26 = tail call %struct.LIST_HELP* @list_PointerDeleteElement(%struct.LIST_HELP* %38, i8* null) #1
-  store %struct.LIST_HELP* %call26, %struct.LIST_HELP** @dfg_CONCLAUSES, align 4
-  %39 = load %struct.LIST_HELP** @dfg_PROOFLIST, align 4
-  tail call void @dfg_DeleteProofList(%struct.LIST_HELP* %39)
-  %40 = load %struct.LIST_HELP** @dfg_TERMLIST, align 4
-  tail call void @list_DeleteWithElement(%struct.LIST_HELP* %40, void (i8*)* bitcast (void (%struct.term*)* @term_Delete to void (i8*)*)) #1
-  %41 = load %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  %42 = load %struct.LIST_HELP** @dfg_CONCLAUSES, align 4
-  %cmp.i.i97 = icmp eq %struct.LIST_HELP* %41, null
-  br i1 %cmp.i.i97, label %list_Nconc.exit107, label %if.end.i99
-
-if.end.i99:                                       ; preds = %for.end25
-  %cmp.i18.i98 = icmp eq %struct.LIST_HELP* %42, null
-  br i1 %cmp.i18.i98, label %list_Nconc.exit107, label %for.cond.i104
-
-for.cond.i104:                                    ; preds = %if.end.i99, %for.cond.i104
-  %List1.addr.0.i100 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i102, %for.cond.i104 ], [ %41, %if.end.i99 ]
-  %List1.addr.0.idx15.i101 = getelementptr %struct.LIST_HELP* %List1.addr.0.i100, i32 0, i32 0
-  %List1.addr.0.idx15.val.i102 = load %struct.LIST_HELP** %List1.addr.0.idx15.i101, align 4
-  %cmp.i16.i103 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i102, null
-  br i1 %cmp.i16.i103, label %for.end.i105, label %for.cond.i104
-
-for.end.i105:                                     ; preds = %for.cond.i104
-  store %struct.LIST_HELP* %42, %struct.LIST_HELP** %List1.addr.0.idx15.i101, align 4
-  br label %list_Nconc.exit107
-
-list_Nconc.exit107:                               ; preds = %for.end25, %if.end.i99, %for.end.i105
-  %retval.0.i106 = phi %struct.LIST_HELP* [ %41, %for.end.i105 ], [ %42, %for.end25 ], [ %41, %if.end.i99 ]
-  %43 = load %struct.LIST_HELP** %Axioms, align 4
-  %44 = load %struct.LIST_HELP** @dfg_AXIOMLIST, align 4
-  %cmp.i.i86 = icmp eq %struct.LIST_HELP* %43, null
-  br i1 %cmp.i.i86, label %list_Nconc.exit96, label %if.end.i88
-
-if.end.i88:                                       ; preds = %list_Nconc.exit107
-  %cmp.i18.i87 = icmp eq %struct.LIST_HELP* %44, null
-  br i1 %cmp.i18.i87, label %list_Nconc.exit96, label %for.cond.i93
-
-for.cond.i93:                                     ; preds = %if.end.i88, %for.cond.i93
-  %List1.addr.0.i89 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i91, %for.cond.i93 ], [ %43, %if.end.i88 ]
-  %List1.addr.0.idx15.i90 = getelementptr %struct.LIST_HELP* %List1.addr.0.i89, i32 0, i32 0
-  %List1.addr.0.idx15.val.i91 = load %struct.LIST_HELP** %List1.addr.0.idx15.i90, align 4
-  %cmp.i16.i92 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i91, null
-  br i1 %cmp.i16.i92, label %for.end.i94, label %for.cond.i93
-
-for.end.i94:                                      ; preds = %for.cond.i93
-  store %struct.LIST_HELP* %44, %struct.LIST_HELP** %List1.addr.0.idx15.i90, align 4
-  br label %list_Nconc.exit96
-
-list_Nconc.exit96:                                ; preds = %list_Nconc.exit107, %if.end.i88, %for.end.i94
-  %retval.0.i95 = phi %struct.LIST_HELP* [ %43, %for.end.i94 ], [ %44, %list_Nconc.exit107 ], [ %43, %if.end.i88 ]
-  store %struct.LIST_HELP* %retval.0.i95, %struct.LIST_HELP** %Axioms, align 4
-  %45 = load %struct.LIST_HELP** %Conjectures, align 4
-  %46 = load %struct.LIST_HELP** @dfg_CONJECLIST, align 4
-  %cmp.i.i75 = icmp eq %struct.LIST_HELP* %45, null
-  br i1 %cmp.i.i75, label %list_Nconc.exit85, label %if.end.i77
-
-if.end.i77:                                       ; preds = %list_Nconc.exit96
-  %cmp.i18.i76 = icmp eq %struct.LIST_HELP* %46, null
-  br i1 %cmp.i18.i76, label %list_Nconc.exit85, label %for.cond.i82
-
-for.cond.i82:                                     ; preds = %if.end.i77, %for.cond.i82
-  %List1.addr.0.i78 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i80, %for.cond.i82 ], [ %45, %if.end.i77 ]
-  %List1.addr.0.idx15.i79 = getelementptr %struct.LIST_HELP* %List1.addr.0.i78, i32 0, i32 0
-  %List1.addr.0.idx15.val.i80 = load %struct.LIST_HELP** %List1.addr.0.idx15.i79, align 4
-  %cmp.i16.i81 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i80, null
-  br i1 %cmp.i16.i81, label %for.end.i83, label %for.cond.i82
-
-for.end.i83:                                      ; preds = %for.cond.i82
-  store %struct.LIST_HELP* %46, %struct.LIST_HELP** %List1.addr.0.idx15.i79, align 4
-  br label %list_Nconc.exit85
-
-list_Nconc.exit85:                                ; preds = %list_Nconc.exit96, %if.end.i77, %for.end.i83
-  %retval.0.i84 = phi %struct.LIST_HELP* [ %45, %for.end.i83 ], [ %46, %list_Nconc.exit96 ], [ %45, %if.end.i77 ]
-  store %struct.LIST_HELP* %retval.0.i84, %struct.LIST_HELP** %Conjectures, align 4
-  %47 = load %struct.LIST_HELP** %SortDecl, align 4
-  %48 = load %struct.LIST_HELP** @dfg_SORTDECLLIST, align 4
-  %cmp.i.i64 = icmp eq %struct.LIST_HELP* %47, null
-  br i1 %cmp.i.i64, label %list_Nconc.exit74, label %if.end.i66
-
-if.end.i66:                                       ; preds = %list_Nconc.exit85
-  %cmp.i18.i65 = icmp eq %struct.LIST_HELP* %48, null
-  br i1 %cmp.i18.i65, label %list_Nconc.exit74, label %for.cond.i71
-
-for.cond.i71:                                     ; preds = %if.end.i66, %for.cond.i71
-  %List1.addr.0.i67 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i69, %for.cond.i71 ], [ %47, %if.end.i66 ]
-  %List1.addr.0.idx15.i68 = getelementptr %struct.LIST_HELP* %List1.addr.0.i67, i32 0, i32 0
-  %List1.addr.0.idx15.val.i69 = load %struct.LIST_HELP** %List1.addr.0.idx15.i68, align 4
-  %cmp.i16.i70 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i69, null
-  br i1 %cmp.i16.i70, label %for.end.i72, label %for.cond.i71
-
-for.end.i72:                                      ; preds = %for.cond.i71
-  store %struct.LIST_HELP* %48, %struct.LIST_HELP** %List1.addr.0.idx15.i68, align 4
-  br label %list_Nconc.exit74
-
-list_Nconc.exit74:                                ; preds = %list_Nconc.exit85, %if.end.i66, %for.end.i72
-  %retval.0.i73 = phi %struct.LIST_HELP* [ %47, %for.end.i72 ], [ %48, %list_Nconc.exit85 ], [ %47, %if.end.i66 ]
-  store %struct.LIST_HELP* %retval.0.i73, %struct.LIST_HELP** %SortDecl, align 4
-  %49 = load %struct.LIST_HELP** @dfg_USERPRECEDENCE, align 4
-  %call31 = tail call %struct.LIST_HELP* @list_NReverse(%struct.LIST_HELP* %49) #1
-  %50 = load %struct.LIST_HELP** %UserDefinedPrecedence, align 4
-  %51 = load %struct.LIST_HELP** @dfg_USERPRECEDENCE, align 4
-  %cmp.i.i = icmp eq %struct.LIST_HELP* %50, null
-  br i1 %cmp.i.i, label %list_Nconc.exit, label %if.end.i
-
-if.end.i:                                         ; preds = %list_Nconc.exit74
-  %cmp.i18.i = icmp eq %struct.LIST_HELP* %51, null
-  br i1 %cmp.i18.i, label %list_Nconc.exit, label %for.cond.i
-
-for.cond.i:                                       ; preds = %if.end.i, %for.cond.i
-  %List1.addr.0.i = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i, %for.cond.i ], [ %50, %if.end.i ]
-  %List1.addr.0.idx15.i = getelementptr %struct.LIST_HELP* %List1.addr.0.i, i32 0, i32 0
-  %List1.addr.0.idx15.val.i = load %struct.LIST_HELP** %List1.addr.0.idx15.i, align 4
-  %cmp.i16.i = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i, null
-  br i1 %cmp.i16.i, label %for.end.i, label %for.cond.i
-
-for.end.i:                                        ; preds = %for.cond.i
-  store %struct.LIST_HELP* %51, %struct.LIST_HELP** %List1.addr.0.idx15.i, align 4
-  br label %list_Nconc.exit
-
-list_Nconc.exit:                                  ; preds = %list_Nconc.exit74, %if.end.i, %for.end.i
-  %retval.0.i = phi %struct.LIST_HELP* [ %50, %for.end.i ], [ %51, %list_Nconc.exit74 ], [ %50, %if.end.i ]
-  store %struct.LIST_HELP* %retval.0.i, %struct.LIST_HELP** %UserDefinedPrecedence, align 4
-  ret %struct.LIST_HELP* %retval.0.i106
-}
-
-; Function Attrs: nounwind
-define %struct.CLAUSE_HELP* @dfg_CreateClauseFromTerm(%struct.term* %Clause, i32 %IsAxiom, i32* %Flags, i32* %Precedence) #0 {
-entry:
-  %Clause.idx = getelementptr %struct.term* %Clause, i32 0, i32 0
-  %Clause.idx.val = load i32* %Clause.idx, align 4
-  %0 = load i32* @fol_ALL, align 4
-  %cmp = icmp eq i32 %Clause.idx.val, %0
-  %Clause.idx66 = getelementptr %struct.term* %Clause, i32 0, i32 2
-  %Clause.idx66.val = load %struct.LIST_HELP** %Clause.idx66, align 4
-  br i1 %cmp, label %if.then, label %if.else
-
-if.then:                                          ; preds = %entry
-  %Clause.idx66.val.idx = getelementptr %struct.LIST_HELP* %Clause.idx66.val, i32 0, i32 0
-  %Clause.idx66.val.idx.val = load %struct.LIST_HELP** %Clause.idx66.val.idx, align 4
-  %Clause.idx66.val.idx.val.idx = getelementptr %struct.LIST_HELP* %Clause.idx66.val.idx.val, i32 0, i32 1
-  %Clause.idx66.val.idx.val.idx.val = load i8** %Clause.idx66.val.idx.val.idx, align 4
-  %call2.idx = getelementptr i8* %Clause.idx66.val.idx.val.idx.val, i32 8
-  %1 = bitcast i8* %call2.idx to %struct.LIST_HELP**
-  %call2.idx.val = load %struct.LIST_HELP** %1, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %1, align 4
-  br label %if.end
-
-if.else:                                          ; preds = %entry
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %Clause.idx66, align 4
-  br label %if.end
-
-if.end:                                           ; preds = %if.else, %if.then
-  %literals.0 = phi %struct.LIST_HELP* [ %call2.idx.val, %if.then ], [ %Clause.idx66.val, %if.else ]
-  tail call void @term_Delete(%struct.term* %Clause) #1
-  %cmp.i7880 = icmp eq %struct.LIST_HELP* %literals.0, null
-  br i1 %cmp.i7880, label %for.end, label %for.body.lr.ph
-
-for.body.lr.ph:                                   ; preds = %if.end
-  %car.i = getelementptr inbounds %struct.LIST_HELP* %literals.0, i32 0, i32 1
-  %2 = load i32* @symbol_TYPEMASK, align 4
-  br label %for.body
-
-for.body:                                         ; preds = %for.body.lr.ph, %for.inc
-  %scan.081 = phi %struct.LIST_HELP* [ %literals.0, %for.body.lr.ph ], [ %scan.0.idx62.val, %for.inc ]
-  %scan.0.idx = getelementptr %struct.LIST_HELP* %scan.081, i32 0, i32 1
-  %scan.0.idx.val = load i8** %scan.0.idx, align 4
-  %3 = bitcast i8* %scan.0.idx.val to %struct.term*
-  %.idx = bitcast i8* %scan.0.idx.val to i32*
-  %.idx.val = load i32* %.idx, align 4
-  %tobool.i = icmp sgt i32 %.idx.val, -1
-  br i1 %tobool.i, label %if.else24, label %land.rhs.i
-
-land.rhs.i:                                       ; preds = %for.body
-  %sub.i.i = sub nsw i32 0, %.idx.val
-  %and.i.i = and i32 %2, %sub.i.i
-  %cmp.i = icmp eq i32 %and.i.i, 2
-  br i1 %cmp.i, label %if.then13, label %if.else24
-
-if.then13:                                        ; preds = %land.rhs.i
-  %4 = load i32* @fol_TRUE, align 4
-  %cmp.i.i76 = icmp eq i32 %4, %.idx.val
-  br i1 %cmp.i.i76, label %if.then16, label %if.else18
-
-if.then16:                                        ; preds = %if.then13
-  %call17 = tail call %struct.LIST_HELP* @list_PointerDeleteElement(%struct.LIST_HELP* %literals.0, i8* null) #1
-  tail call void @list_DeleteWithElement(%struct.LIST_HELP* %literals.0, void (i8*)* bitcast (void (%struct.term*)* @term_Delete to void (i8*)*)) #1
-  br label %return
-
-if.else18:                                        ; preds = %if.then13
-  %5 = load i32* @fol_FALSE, align 4
-  %cmp.i.i74 = icmp eq i32 %5, %.idx.val
-  br i1 %cmp.i.i74, label %if.then21, label %for.inc
-
-if.then21:                                        ; preds = %if.else18
-  tail call void @term_Delete(%struct.term* %3) #1
-  store i8* null, i8** %scan.0.idx, align 4
-  br label %for.inc
-
-if.else24:                                        ; preds = %for.body, %land.rhs.i
-  %.idx63 = getelementptr i8* %scan.0.idx.val, i32 8
-  %6 = bitcast i8* %.idx63 to %struct.LIST_HELP**
-  %.idx63.val = load %struct.LIST_HELP** %6, align 4
-  %.idx63.val.idx = getelementptr %struct.LIST_HELP* %.idx63.val, i32 0, i32 1
-  %.idx63.val.idx.val = load i8** %.idx63.val.idx, align 4
-  %call25.idx68 = bitcast i8* %.idx63.val.idx.val to i32*
-  %call25.idx68.val = load i32* %call25.idx68, align 4
-  %7 = load i32* @fol_FALSE, align 4
-  %cmp.i.i71 = icmp eq i32 %7, %call25.idx68.val
-  br i1 %cmp.i.i71, label %if.then28, label %if.else30
-
-if.then28:                                        ; preds = %if.else24
-  %call29 = tail call %struct.LIST_HELP* @list_PointerDeleteElement(%struct.LIST_HELP* %literals.0, i8* null) #1
-  tail call void @list_DeleteWithElement(%struct.LIST_HELP* %literals.0, void (i8*)* bitcast (void (%struct.term*)* @term_Delete to void (i8*)*)) #1
-  br label %return
-
-if.else30:                                        ; preds = %if.else24
-  %8 = load i32* @fol_TRUE, align 4
-  %cmp.i.i70 = icmp eq i32 %8, %call25.idx68.val
-  br i1 %cmp.i.i70, label %if.then33, label %for.inc
-
-if.then33:                                        ; preds = %if.else30
-  tail call void @term_Delete(%struct.term* %3) #1
-  store i8* null, i8** %car.i, align 4
-  br label %for.inc
-
-for.inc:                                          ; preds = %if.else30, %if.else18, %if.then21, %if.then33
-  %scan.0.idx62 = getelementptr %struct.LIST_HELP* %scan.081, i32 0, i32 0
-  %scan.0.idx62.val = load %struct.LIST_HELP** %scan.0.idx62, align 4
-  %cmp.i78 = icmp eq %struct.LIST_HELP* %scan.0.idx62.val, null
-  br i1 %cmp.i78, label %for.end, label %for.body
-
-for.end:                                          ; preds = %for.inc, %if.end
-  %call38 = tail call %struct.LIST_HELP* @list_PointerDeleteElement(%struct.LIST_HELP* %literals.0, i8* null) #1
-  %lnot40 = icmp eq i32 %IsAxiom, 0
-  %lnot.ext = zext i1 %lnot40 to i32
-  %call41 = tail call %struct.CLAUSE_HELP* @clause_CreateFromLiterals(%struct.LIST_HELP* %call38, i32 0, i32 %lnot.ext, i32 0, i32* %Flags, i32* %Precedence) #1
-  %cmp.i5.i = icmp eq %struct.LIST_HELP* %call38, null
-  br i1 %cmp.i5.i, label %return, label %while.body.i
-
-while.body.i:                                     ; preds = %for.end, %while.body.i
-  %L.addr.06.i = phi %struct.LIST_HELP* [ %L.addr.0.idx.val.i, %while.body.i ], [ %call38, %for.end ]
-  %L.addr.0.idx.i = getelementptr %struct.LIST_HELP* %L.addr.06.i, i32 0, i32 0
-  %L.addr.0.idx.val.i = load %struct.LIST_HELP** %L.addr.0.idx.i, align 4
-  %9 = bitcast %struct.LIST_HELP* %L.addr.06.i to i8*
-  %10 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %10, i32 0, i32 4
-  %11 = load i32* %total_size.i.i.i, align 4
-  %12 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i = add i32 %12, %11
-  store i32 %add24.i.i.i, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %10, i32 0, i32 0
-  %13 = load i8** %free.i.i.i, align 4
-  %.c.i.i = bitcast i8* %13 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i, %struct.LIST_HELP** %L.addr.0.idx.i, align 4
-  %14 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %14, i32 0, i32 0
-  store i8* %9, i8** %free27.i.i.i, align 4
-  %cmp.i.i = icmp eq %struct.LIST_HELP* %L.addr.0.idx.val.i, null
-  br i1 %cmp.i.i, label %return, label %while.body.i
-
-return:                                           ; preds = %while.body.i, %for.end, %if.then28, %if.then16
-  %retval.0 = phi %struct.CLAUSE_HELP* [ null, %if.then16 ], [ null, %if.then28 ], [ %call41, %for.end ], [ %call41, %while.body.i ]
-  ret %struct.CLAUSE_HELP* %retval.0
-}
-
-declare %struct.LIST_HELP* @list_PointerDeleteElement(%struct.LIST_HELP*, i8*) #2
-
-; Function Attrs: nounwind
-define void @dfg_DeleteProofList(%struct.LIST_HELP* %Proof) #0 {
-entry:
-  %cmp.i18 = icmp eq %struct.LIST_HELP* %Proof, null
-  br i1 %cmp.i18, label %for.end, label %for.body
-
-for.body:                                         ; preds = %entry, %list_Delete.exit
-  %Proof.addr.019 = phi %struct.LIST_HELP* [ %L.idx.val.i, %list_Delete.exit ], [ %Proof, %entry ]
-  %Proof.addr.0.idx = getelementptr %struct.LIST_HELP* %Proof.addr.019, i32 0, i32 1
-  %Proof.addr.0.idx.val = load i8** %Proof.addr.0.idx, align 4
-  %.idx = getelementptr i8* %Proof.addr.0.idx.val, i32 4
-  %0 = bitcast i8* %.idx to i8**
-  %.idx.val = load i8** %0, align 4
-  tail call void @string_StringFree(i8* %.idx.val) #1
-  %.idx11 = bitcast i8* %Proof.addr.0.idx.val to %struct.LIST_HELP**
-  %.idx11.val = load %struct.LIST_HELP** %.idx11, align 4
-  %.idx11.val.idx = getelementptr %struct.LIST_HELP* %.idx11.val, i32 0, i32 1
-  %.idx11.val.idx.val = load i8** %.idx11.val.idx, align 4
-  %1 = bitcast i8* %.idx11.val.idx.val to %struct.term*
-  tail call void @term_Delete(%struct.term* %1) #1
-  %.idx12.val = load %struct.LIST_HELP** %.idx11, align 4
-  %.idx12.val.idx = getelementptr %struct.LIST_HELP* %.idx12.val, i32 0, i32 0
-  %.idx12.val.idx.val = load %struct.LIST_HELP** %.idx12.val.idx, align 4
-  %.idx12.val.idx.val.idx = getelementptr %struct.LIST_HELP* %.idx12.val.idx.val, i32 0, i32 1
-  %.idx12.val.idx.val.idx.val = load i8** %.idx12.val.idx.val.idx, align 4
-  %2 = bitcast i8* %.idx12.val.idx.val.idx.val to %struct.LIST_HELP*
-  tail call void @list_DeleteWithElement(%struct.LIST_HELP* %2, void (i8*)* @string_StringFree) #1
-  %cmp.i5.i = icmp eq i8* %Proof.addr.0.idx.val, null
-  br i1 %cmp.i5.i, label %list_Delete.exit, label %while.body.i.preheader
-
-while.body.i.preheader:                           ; preds = %for.body
-  %3 = bitcast i8* %Proof.addr.0.idx.val to %struct.LIST_HELP*
-  br label %while.body.i
-
-while.body.i:                                     ; preds = %while.body.i.preheader, %while.body.i
-  %L.addr.06.i = phi %struct.LIST_HELP* [ %L.addr.0.idx.val.i, %while.body.i ], [ %3, %while.body.i.preheader ]
-  %L.addr.0.idx.i = getelementptr %struct.LIST_HELP* %L.addr.06.i, i32 0, i32 0
-  %L.addr.0.idx.val.i = load %struct.LIST_HELP** %L.addr.0.idx.i, align 4
-  %4 = bitcast %struct.LIST_HELP* %L.addr.06.i to i8*
-  %5 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i13 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %5, i32 0, i32 4
-  %6 = load i32* %total_size.i.i.i13, align 4
-  %7 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i14 = add i32 %7, %6
-  store i32 %add24.i.i.i14, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i15 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %5, i32 0, i32 0
-  %8 = load i8** %free.i.i.i15, align 4
-  %.c.i.i16 = bitcast i8* %8 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i16, %struct.LIST_HELP** %L.addr.0.idx.i, align 4
-  %9 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i17 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %9, i32 0, i32 0
-  store i8* %4, i8** %free27.i.i.i17, align 4
-  %cmp.i.i = icmp eq %struct.LIST_HELP* %L.addr.0.idx.val.i, null
-  br i1 %cmp.i.i, label %list_Delete.exit, label %while.body.i
-
-list_Delete.exit:                                 ; preds = %while.body.i, %for.body
-  %L.idx.i = getelementptr %struct.LIST_HELP* %Proof.addr.019, i32 0, i32 0
-  %L.idx.val.i = load %struct.LIST_HELP** %L.idx.i, align 4
-  %10 = bitcast %struct.LIST_HELP* %Proof.addr.019 to i8*
-  %11 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %11, i32 0, i32 4
-  %12 = load i32* %total_size.i.i.i, align 4
-  %13 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i = add i32 %13, %12
-  store i32 %add24.i.i.i, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %11, i32 0, i32 0
-  %14 = load i8** %free.i.i.i, align 4
-  %.c.i.i = bitcast i8* %14 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i, %struct.LIST_HELP** %L.idx.i, align 4
-  %15 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %15, i32 0, i32 0
-  store i8* %10, i8** %free27.i.i.i, align 4
-  %cmp.i = icmp eq %struct.LIST_HELP* %L.idx.val.i, null
-  br i1 %cmp.i, label %for.end, label %for.body
-
-for.end:                                          ; preds = %list_Delete.exit, %entry
-  ret void
-}
-
-; Function Attrs: nounwind
-define %struct.LIST_HELP* @dfg_ProofParser(%struct._IO_FILE* %File, i32* %Flags, i32* %Precedence) #0 {
-entry:
-  store %struct._IO_FILE* %File, %struct._IO_FILE** @dfg_in, align 4
-  store i32 1, i32* @dfg_LINENUMBER, align 4
-  store i32 1, i32* @dfg_IGNORETEXT, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_AXIOMLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_CONJECLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_SORTDECLLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_USERPRECEDENCE, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_CONCLAUSES, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_PROOFLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_TERMLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_SYMBOLLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_VARLIST, align 4
-  store i1 false, i1* @dfg_VARDECL, align 1
-  store i32 0, i32* @dfg_IGNORE, align 4
-  store i32* %Flags, i32** @dfg_FLAGS, align 4
-  store i32* %Precedence, i32** @dfg_PRECEDENCE, align 4
-  store i8* null, i8** @dfg_DESC.0, align 4
-  store i8* null, i8** @dfg_DESC.1, align 4
-  store i8* null, i8** @dfg_DESC.2, align 4
-  store i8* null, i8** @dfg_DESC.3, align 4
-  store i32 2, i32* @dfg_DESC.4, align 4
-  store i8* null, i8** @dfg_DESC.5, align 4
-  store i8* null, i8** @dfg_DESC.6, align 4
-  %call1 = tail call i32 @dfg_parse()
-  %0 = load %struct.LIST_HELP** @dfg_SYMBOLLIST, align 4
-  %cmp.i13.i = icmp eq %struct.LIST_HELP* %0, null
-  br i1 %cmp.i13.i, label %dfg_SymCleanUp.exit, label %while.body.lr.ph.i
-
-while.body.lr.ph.i:                               ; preds = %entry
-  %1 = load i32* @symbol_TYPESTATBITS, align 4
-  br label %while.body.i
-
-while.body.i:                                     ; preds = %if.end.i42, %while.body.lr.ph.i
-  %2 = phi %struct.LIST_HELP* [ %0, %while.body.lr.ph.i ], [ %L.idx.val.i.i35, %if.end.i42 ]
-  %.idx.i30 = getelementptr %struct.LIST_HELP* %2, i32 0, i32 1
-  %.idx.val.i31 = load i8** %.idx.i30, align 4
-  %symbol.i = bitcast i8* %.idx.val.i31 to i32*
-  %3 = load i32* %symbol.i, align 4
-  %arity.i = getelementptr inbounds i8* %.idx.val.i31, i32 8
-  %4 = bitcast i8* %arity.i to i32*
-  %5 = load i32* %4, align 4
-  %sub.i.i9.i = sub nsw i32 0, %3
-  %shr.i.i10.i = ashr i32 %sub.i.i9.i, %1
-  %6 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i11.i = getelementptr inbounds %struct.signature** %6, i32 %shr.i.i10.i
-  %7 = load %struct.signature** %arrayidx.i.i11.i, align 4
-  %arity.i12.i = getelementptr inbounds %struct.signature* %7, i32 0, i32 3
-  %8 = load i32* %arity.i12.i, align 4
-  %cmp.i32 = icmp eq i32 %5, %8
-  br i1 %cmp.i32, label %if.end.i42, label %if.then.i33
-
-if.then.i33:                                      ; preds = %while.body.i
-  store i32 %5, i32* %arity.i12.i, align 4
-  br label %if.end.i42
-
-if.end.i42:                                       ; preds = %if.then.i33, %while.body.i
-  %9 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 12), align 4
-  %total_size.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %9, i32 0, i32 4
-  %10 = load i32* %total_size.i.i.i, align 4
-  %11 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i = add i32 %11, %10
-  store i32 %add24.i.i.i, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %9, i32 0, i32 0
-  %12 = load i8** %free.i.i.i, align 4
-  %.c.i.i = ptrtoint i8* %12 to i32
-  store i32 %.c.i.i, i32* %symbol.i, align 4
-  %13 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 12), align 4
-  %free27.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %13, i32 0, i32 0
-  store i8* %.idx.val.i31, i8** %free27.i.i.i, align 4
-  %14 = load %struct.LIST_HELP** @dfg_SYMBOLLIST, align 4
-  %L.idx.i.i34 = getelementptr %struct.LIST_HELP* %14, i32 0, i32 0
-  %L.idx.val.i.i35 = load %struct.LIST_HELP** %L.idx.i.i34, align 4
-  %15 = bitcast %struct.LIST_HELP* %14 to i8*
-  %16 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i36 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %16, i32 0, i32 4
-  %17 = load i32* %total_size.i.i.i.i36, align 4
-  %18 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i37 = add i32 %18, %17
-  store i32 %add24.i.i.i.i37, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i38 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %16, i32 0, i32 0
-  %19 = load i8** %free.i.i.i.i38, align 4
-  %.c.i.i.i39 = bitcast i8* %19 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i39, %struct.LIST_HELP** %L.idx.i.i34, align 4
-  %20 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i40 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %20, i32 0, i32 0
-  store i8* %15, i8** %free27.i.i.i.i40, align 4
-  store %struct.LIST_HELP* %L.idx.val.i.i35, %struct.LIST_HELP** @dfg_SYMBOLLIST, align 4
-  %cmp.i.i41 = icmp eq %struct.LIST_HELP* %L.idx.val.i.i35, null
-  br i1 %cmp.i.i41, label %dfg_SymCleanUp.exit, label %while.body.i
-
-dfg_SymCleanUp.exit:                              ; preds = %if.end.i42, %entry
-  %21 = load %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  %22 = load %struct.LIST_HELP** @dfg_CONCLAUSES, align 4
-  %cmp.i.i43 = icmp eq %struct.LIST_HELP* %21, null
-  br i1 %cmp.i.i43, label %list_Nconc.exit53, label %if.end.i45
-
-if.end.i45:                                       ; preds = %dfg_SymCleanUp.exit
-  %cmp.i18.i44 = icmp eq %struct.LIST_HELP* %22, null
-  br i1 %cmp.i18.i44, label %list_Nconc.exit53.thread, label %for.cond.i50
-
-list_Nconc.exit53.thread:                         ; preds = %if.end.i45
-  store %struct.LIST_HELP* %21, %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_CONCLAUSES, align 4
-  br label %for.body
-
-for.cond.i50:                                     ; preds = %if.end.i45, %for.cond.i50
-  %List1.addr.0.i46 = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i48, %for.cond.i50 ], [ %21, %if.end.i45 ]
-  %List1.addr.0.idx15.i47 = getelementptr %struct.LIST_HELP* %List1.addr.0.i46, i32 0, i32 0
-  %List1.addr.0.idx15.val.i48 = load %struct.LIST_HELP** %List1.addr.0.idx15.i47, align 4
-  %cmp.i16.i49 = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i48, null
-  br i1 %cmp.i16.i49, label %for.end.i51, label %for.cond.i50
-
-for.end.i51:                                      ; preds = %for.cond.i50
-  store %struct.LIST_HELP* %22, %struct.LIST_HELP** %List1.addr.0.idx15.i47, align 4
-  br label %list_Nconc.exit53
-
-list_Nconc.exit53:                                ; preds = %dfg_SymCleanUp.exit, %for.end.i51
-  %retval.0.i52 = phi %struct.LIST_HELP* [ %21, %for.end.i51 ], [ %22, %dfg_SymCleanUp.exit ]
-  store %struct.LIST_HELP* %retval.0.i52, %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_CONCLAUSES, align 4
-  %cmp.i81122 = icmp eq %struct.LIST_HELP* %retval.0.i52, null
-  br i1 %cmp.i81122, label %for.end, label %for.body
-
-for.body:                                         ; preds = %list_Nconc.exit53, %list_Nconc.exit53.thread, %for.inc
-  %scan.0123 = phi %struct.LIST_HELP* [ %scan.0.idx24.val, %for.inc ], [ %21, %list_Nconc.exit53.thread ], [ %retval.0.i52, %list_Nconc.exit53 ]
-  %scan.0.idx = getelementptr %struct.LIST_HELP* %scan.0123, i32 0, i32 1
-  %scan.0.idx.val = load i8** %scan.0.idx, align 4
-  %.idx = bitcast i8* %scan.0.idx.val to %struct.LIST_HELP**
-  %.idx.val = load %struct.LIST_HELP** %.idx, align 4
-  %.idx25 = getelementptr i8* %scan.0.idx.val, i32 4
-  %23 = bitcast i8* %.idx25 to i8**
-  %.idx25.val = load i8** %23, align 4
-  %cmp = icmp eq i8* %.idx25.val, null
-  br i1 %cmp, label %if.then, label %if.else
-
-if.then:                                          ; preds = %for.body
-  %24 = bitcast %struct.LIST_HELP* %.idx.val to %struct.term*
-  tail call void @term_Delete(%struct.term* %24) #1
-  %25 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i113 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %25, i32 0, i32 4
-  %26 = load i32* %total_size.i.i.i113, align 4
-  %27 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i114 = add i32 %27, %26
-  store i32 %add24.i.i.i114, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i115 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %25, i32 0, i32 0
-  %28 = load i8** %free.i.i.i115, align 4
-  %.c.i.i116 = bitcast i8* %28 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i116, %struct.LIST_HELP** %.idx, align 4
-  %29 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i117 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %29, i32 0, i32 0
-  store i8* %scan.0.idx.val, i8** %free27.i.i.i117, align 4
-  store i8* null, i8** %scan.0.idx, align 4
-  br label %for.inc
-
-if.else:                                          ; preds = %for.body
-  %30 = bitcast %struct.LIST_HELP* %.idx.val to i8*
-  %call.i.i = tail call i8* @memory_Malloc(i32 8) #1
-  %31 = bitcast i8* %call.i.i to %struct.LIST_HELP*
-  %car.i.i = getelementptr inbounds i8* %call.i.i, i32 4
-  %32 = bitcast i8* %car.i.i to i8**
-  store i8* inttoptr (i32 16 to i8*), i8** %32, align 4
-  %cdr.i.i = bitcast i8* %call.i.i to %struct.LIST_HELP**
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** %cdr.i.i, align 4
-  %call.i118 = tail call i8* @memory_Malloc(i32 8) #1
-  %33 = bitcast i8* %call.i118 to %struct.LIST_HELP*
-  %car.i119 = getelementptr inbounds i8* %call.i118, i32 4
-  %34 = bitcast i8* %car.i119 to i8**
-  store i8* null, i8** %34, align 4
-  %cdr.i120 = bitcast i8* %call.i118 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %31, %struct.LIST_HELP** %cdr.i120, align 4
-  %call.i110 = tail call i8* @memory_Malloc(i32 8) #1
-  %35 = bitcast i8* %call.i110 to %struct.LIST_HELP*
-  %car.i111 = getelementptr inbounds i8* %call.i110, i32 4
-  %36 = bitcast i8* %car.i111 to i8**
-  store i8* null, i8** %36, align 4
-  %cdr.i112 = bitcast i8* %call.i110 to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %33, %struct.LIST_HELP** %cdr.i112, align 4
-  %call.i = tail call i8* @memory_Malloc(i32 8) #1
-  %37 = bitcast i8* %call.i to %struct.LIST_HELP*
-  %car.i = getelementptr inbounds i8* %call.i, i32 4
-  %38 = bitcast i8* %car.i to i8**
-  store i8* %30, i8** %38, align 4
-  %cdr.i109 = bitcast i8* %call.i to %struct.LIST_HELP**
-  store %struct.LIST_HELP* %35, %struct.LIST_HELP** %cdr.i109, align 4
-  store %struct.LIST_HELP* %37, %struct.LIST_HELP** %.idx, align 4
-  br label %for.inc
-
-for.inc:                                          ; preds = %if.then, %if.else
-  %scan.0.idx24 = getelementptr %struct.LIST_HELP* %scan.0123, i32 0, i32 0
-  %scan.0.idx24.val = load %struct.LIST_HELP** %scan.0.idx24, align 4
-  %cmp.i81 = icmp eq %struct.LIST_HELP* %scan.0.idx24.val, null
-  br i1 %cmp.i81, label %for.cond.for.end_crit_edge, label %for.body
-
-for.cond.for.end_crit_edge:                       ; preds = %for.inc
-  %.pre = load %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  br label %for.end
-
-for.end:                                          ; preds = %for.cond.for.end_crit_edge, %list_Nconc.exit53
-  %39 = phi %struct.LIST_HELP* [ %.pre, %for.cond.for.end_crit_edge ], [ null, %list_Nconc.exit53 ]
-  %call14 = tail call %struct.LIST_HELP* @list_PointerDeleteElement(%struct.LIST_HELP* %39, i8* null) #1
-  store %struct.LIST_HELP* %call14, %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  %40 = load %struct.LIST_HELP** @dfg_AXIOMLIST, align 4
-  %cmp.i18.i82 = icmp eq %struct.LIST_HELP* %40, null
-  br i1 %cmp.i18.i82, label %dfg_DeleteFormulaPairList.exit108, label %for.body.i91
-
-for.body.i91:                                     ; preds = %for.end, %if.end.i106
-  %FormulaPairs.addr.019.i83 = phi %struct.LIST_HELP* [ %L.idx.val.i.i99, %if.end.i106 ], [ %40, %for.end ]
-  %FormulaPairs.addr.0.idx.i84 = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i83, i32 0, i32 1
-  %FormulaPairs.addr.0.idx.val.i85 = load i8** %FormulaPairs.addr.0.idx.i84, align 4
-  %.idx.i86 = bitcast i8* %FormulaPairs.addr.0.idx.val.i85 to %struct.LIST_HELP**
-  %.idx.val.i87 = load %struct.LIST_HELP** %.idx.i86, align 4
-  %41 = bitcast %struct.LIST_HELP* %.idx.val.i87 to %struct.term*
-  tail call void @term_Delete(%struct.term* %41) #1
-  %.idx12.i88 = getelementptr i8* %FormulaPairs.addr.0.idx.val.i85, i32 4
-  %42 = bitcast i8* %.idx12.i88 to i8**
-  %.idx12.val.i89 = load i8** %42, align 4
-  %cmp.i90 = icmp eq i8* %.idx12.val.i89, null
-  br i1 %cmp.i90, label %if.end.i106, label %if.then.i92
-
-if.then.i92:                                      ; preds = %for.body.i91
-  tail call void @string_StringFree(i8* %.idx12.val.i89) #1
-  br label %if.end.i106
-
-if.end.i106:                                      ; preds = %if.then.i92, %for.body.i91
-  %43 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i13.i93 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %43, i32 0, i32 4
-  %44 = load i32* %total_size.i.i.i13.i93, align 4
-  %45 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i14.i94 = add i32 %45, %44
-  store i32 %add24.i.i.i14.i94, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i15.i95 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %43, i32 0, i32 0
-  %46 = load i8** %free.i.i.i15.i95, align 4
-  %.c.i.i16.i96 = bitcast i8* %46 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i16.i96, %struct.LIST_HELP** %.idx.i86, align 4
-  %47 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i17.i97 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %47, i32 0, i32 0
-  store i8* %FormulaPairs.addr.0.idx.val.i85, i8** %free27.i.i.i17.i97, align 4
-  %L.idx.i.i98 = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i83, i32 0, i32 0
-  %L.idx.val.i.i99 = load %struct.LIST_HELP** %L.idx.i.i98, align 4
-  %48 = bitcast %struct.LIST_HELP* %FormulaPairs.addr.019.i83 to i8*
-  %49 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i100 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %49, i32 0, i32 4
-  %50 = load i32* %total_size.i.i.i.i100, align 4
-  %51 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i101 = add i32 %51, %50
-  store i32 %add24.i.i.i.i101, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i102 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %49, i32 0, i32 0
-  %52 = load i8** %free.i.i.i.i102, align 4
-  %.c.i.i.i103 = bitcast i8* %52 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i103, %struct.LIST_HELP** %L.idx.i.i98, align 4
-  %53 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i104 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %53, i32 0, i32 0
-  store i8* %48, i8** %free27.i.i.i.i104, align 4
-  %cmp.i.i105 = icmp eq %struct.LIST_HELP* %L.idx.val.i.i99, null
-  br i1 %cmp.i.i105, label %dfg_DeleteFormulaPairList.exit108, label %for.body.i91
-
-dfg_DeleteFormulaPairList.exit108:                ; preds = %if.end.i106, %for.end
-  %54 = load %struct.LIST_HELP** @dfg_CONJECLIST, align 4
-  %cmp.i18.i54 = icmp eq %struct.LIST_HELP* %54, null
-  br i1 %cmp.i18.i54, label %dfg_DeleteFormulaPairList.exit80, label %for.body.i63
-
-for.body.i63:                                     ; preds = %dfg_DeleteFormulaPairList.exit108, %if.end.i78
-  %FormulaPairs.addr.019.i55 = phi %struct.LIST_HELP* [ %L.idx.val.i.i71, %if.end.i78 ], [ %54, %dfg_DeleteFormulaPairList.exit108 ]
-  %FormulaPairs.addr.0.idx.i56 = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i55, i32 0, i32 1
-  %FormulaPairs.addr.0.idx.val.i57 = load i8** %FormulaPairs.addr.0.idx.i56, align 4
-  %.idx.i58 = bitcast i8* %FormulaPairs.addr.0.idx.val.i57 to %struct.LIST_HELP**
-  %.idx.val.i59 = load %struct.LIST_HELP** %.idx.i58, align 4
-  %55 = bitcast %struct.LIST_HELP* %.idx.val.i59 to %struct.term*
-  tail call void @term_Delete(%struct.term* %55) #1
-  %.idx12.i60 = getelementptr i8* %FormulaPairs.addr.0.idx.val.i57, i32 4
-  %56 = bitcast i8* %.idx12.i60 to i8**
-  %.idx12.val.i61 = load i8** %56, align 4
-  %cmp.i62 = icmp eq i8* %.idx12.val.i61, null
-  br i1 %cmp.i62, label %if.end.i78, label %if.then.i64
-
-if.then.i64:                                      ; preds = %for.body.i63
-  tail call void @string_StringFree(i8* %.idx12.val.i61) #1
-  br label %if.end.i78
-
-if.end.i78:                                       ; preds = %if.then.i64, %for.body.i63
-  %57 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i13.i65 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %57, i32 0, i32 4
-  %58 = load i32* %total_size.i.i.i13.i65, align 4
-  %59 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i14.i66 = add i32 %59, %58
-  store i32 %add24.i.i.i14.i66, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i15.i67 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %57, i32 0, i32 0
-  %60 = load i8** %free.i.i.i15.i67, align 4
-  %.c.i.i16.i68 = bitcast i8* %60 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i16.i68, %struct.LIST_HELP** %.idx.i58, align 4
-  %61 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i17.i69 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %61, i32 0, i32 0
-  store i8* %FormulaPairs.addr.0.idx.val.i57, i8** %free27.i.i.i17.i69, align 4
-  %L.idx.i.i70 = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i55, i32 0, i32 0
-  %L.idx.val.i.i71 = load %struct.LIST_HELP** %L.idx.i.i70, align 4
-  %62 = bitcast %struct.LIST_HELP* %FormulaPairs.addr.019.i55 to i8*
-  %63 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i72 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %63, i32 0, i32 4
-  %64 = load i32* %total_size.i.i.i.i72, align 4
-  %65 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i73 = add i32 %65, %64
-  store i32 %add24.i.i.i.i73, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i74 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %63, i32 0, i32 0
-  %66 = load i8** %free.i.i.i.i74, align 4
-  %.c.i.i.i75 = bitcast i8* %66 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i75, %struct.LIST_HELP** %L.idx.i.i70, align 4
-  %67 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i76 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %67, i32 0, i32 0
-  store i8* %62, i8** %free27.i.i.i.i76, align 4
-  %cmp.i.i77 = icmp eq %struct.LIST_HELP* %L.idx.val.i.i71, null
-  br i1 %cmp.i.i77, label %dfg_DeleteFormulaPairList.exit80, label %for.body.i63
-
-dfg_DeleteFormulaPairList.exit80:                 ; preds = %if.end.i78, %dfg_DeleteFormulaPairList.exit108
-  %68 = load %struct.LIST_HELP** @dfg_SORTDECLLIST, align 4
-  %cmp.i18.i26 = icmp eq %struct.LIST_HELP* %68, null
-  br i1 %cmp.i18.i26, label %dfg_DeleteFormulaPairList.exit, label %for.body.i
-
-for.body.i:                                       ; preds = %dfg_DeleteFormulaPairList.exit80, %if.end.i28
-  %FormulaPairs.addr.019.i = phi %struct.LIST_HELP* [ %L.idx.val.i.i, %if.end.i28 ], [ %68, %dfg_DeleteFormulaPairList.exit80 ]
-  %FormulaPairs.addr.0.idx.i = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i, i32 0, i32 1
-  %FormulaPairs.addr.0.idx.val.i = load i8** %FormulaPairs.addr.0.idx.i, align 4
-  %.idx.i = bitcast i8* %FormulaPairs.addr.0.idx.val.i to %struct.LIST_HELP**
-  %.idx.val.i = load %struct.LIST_HELP** %.idx.i, align 4
-  %69 = bitcast %struct.LIST_HELP* %.idx.val.i to %struct.term*
-  tail call void @term_Delete(%struct.term* %69) #1
-  %.idx12.i = getelementptr i8* %FormulaPairs.addr.0.idx.val.i, i32 4
-  %70 = bitcast i8* %.idx12.i to i8**
-  %.idx12.val.i = load i8** %70, align 4
-  %cmp.i = icmp eq i8* %.idx12.val.i, null
-  br i1 %cmp.i, label %if.end.i28, label %if.then.i
-
-if.then.i:                                        ; preds = %for.body.i
-  tail call void @string_StringFree(i8* %.idx12.val.i) #1
-  br label %if.end.i28
-
-if.end.i28:                                       ; preds = %if.then.i, %for.body.i
-  %71 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i13.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %71, i32 0, i32 4
-  %72 = load i32* %total_size.i.i.i13.i, align 4
-  %73 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i14.i = add i32 %73, %72
-  store i32 %add24.i.i.i14.i, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i15.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %71, i32 0, i32 0
-  %74 = load i8** %free.i.i.i15.i, align 4
-  %.c.i.i16.i = bitcast i8* %74 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i16.i, %struct.LIST_HELP** %.idx.i, align 4
-  %75 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i17.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %75, i32 0, i32 0
-  store i8* %FormulaPairs.addr.0.idx.val.i, i8** %free27.i.i.i17.i, align 4
-  %L.idx.i.i = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i, i32 0, i32 0
-  %L.idx.val.i.i = load %struct.LIST_HELP** %L.idx.i.i, align 4
-  %76 = bitcast %struct.LIST_HELP* %FormulaPairs.addr.019.i to i8*
-  %77 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %77, i32 0, i32 4
-  %78 = load i32* %total_size.i.i.i.i, align 4
-  %79 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i = add i32 %79, %78
-  store i32 %add24.i.i.i.i, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %77, i32 0, i32 0
-  %80 = load i8** %free.i.i.i.i, align 4
-  %.c.i.i.i = bitcast i8* %80 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i, %struct.LIST_HELP** %L.idx.i.i, align 4
-  %81 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %81, i32 0, i32 0
-  store i8* %76, i8** %free27.i.i.i.i, align 4
-  %cmp.i.i27 = icmp eq %struct.LIST_HELP* %L.idx.val.i.i, null
-  br i1 %cmp.i.i27, label %dfg_DeleteFormulaPairList.exit, label %for.body.i
-
-dfg_DeleteFormulaPairList.exit:                   ; preds = %if.end.i28, %dfg_DeleteFormulaPairList.exit80
-  %82 = load %struct.LIST_HELP** @dfg_TERMLIST, align 4
-  tail call void @list_DeleteWithElement(%struct.LIST_HELP* %82, void (i8*)* bitcast (void (%struct.term*)* @term_Delete to void (i8*)*)) #1
-  %83 = load %struct.LIST_HELP** @dfg_PROOFLIST, align 4
-  %call15 = tail call %struct.LIST_HELP* @list_NReverse(%struct.LIST_HELP* %83) #1
-  store %struct.LIST_HELP* %call15, %struct.LIST_HELP** @dfg_PROOFLIST, align 4
-  %84 = load %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  %cmp.i.i = icmp eq %struct.LIST_HELP* %84, null
-  br i1 %cmp.i.i, label %list_Nconc.exit, label %if.end.i
-
-if.end.i:                                         ; preds = %dfg_DeleteFormulaPairList.exit
-  %cmp.i18.i = icmp eq %struct.LIST_HELP* %call15, null
-  br i1 %cmp.i18.i, label %list_Nconc.exit, label %for.cond.i
-
-for.cond.i:                                       ; preds = %if.end.i, %for.cond.i
-  %List1.addr.0.i = phi %struct.LIST_HELP* [ %List1.addr.0.idx15.val.i, %for.cond.i ], [ %84, %if.end.i ]
-  %List1.addr.0.idx15.i = getelementptr %struct.LIST_HELP* %List1.addr.0.i, i32 0, i32 0
-  %List1.addr.0.idx15.val.i = load %struct.LIST_HELP** %List1.addr.0.idx15.i, align 4
-  %cmp.i16.i = icmp eq %struct.LIST_HELP* %List1.addr.0.idx15.val.i, null
-  br i1 %cmp.i16.i, label %for.end.i, label %for.cond.i
-
-for.end.i:                                        ; preds = %for.cond.i
-  store %struct.LIST_HELP* %call15, %struct.LIST_HELP** %List1.addr.0.idx15.i, align 4
-  br label %list_Nconc.exit
-
-list_Nconc.exit:                                  ; preds = %dfg_DeleteFormulaPairList.exit, %if.end.i, %for.end.i
-  %retval.0.i = phi %struct.LIST_HELP* [ %84, %for.end.i ], [ %call15, %dfg_DeleteFormulaPairList.exit ], [ %84, %if.end.i ]
-  store %struct.LIST_HELP* %retval.0.i, %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  ret %struct.LIST_HELP* %retval.0.i
-}
-
-; Function Attrs: nounwind
-define void @dfg_DeleteFormulaPairList(%struct.LIST_HELP* %FormulaPairs) #0 {
-entry:
-  %cmp.i18 = icmp eq %struct.LIST_HELP* %FormulaPairs, null
-  br i1 %cmp.i18, label %for.end, label %for.body
-
-for.body:                                         ; preds = %entry, %if.end
-  %FormulaPairs.addr.019 = phi %struct.LIST_HELP* [ %L.idx.val.i, %if.end ], [ %FormulaPairs, %entry ]
-  %FormulaPairs.addr.0.idx = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019, i32 0, i32 1
-  %FormulaPairs.addr.0.idx.val = load i8** %FormulaPairs.addr.0.idx, align 4
-  %.idx = bitcast i8* %FormulaPairs.addr.0.idx.val to %struct.LIST_HELP**
-  %.idx.val = load %struct.LIST_HELP** %.idx, align 4
-  %0 = bitcast %struct.LIST_HELP* %.idx.val to %struct.term*
-  tail call void @term_Delete(%struct.term* %0) #1
-  %.idx12 = getelementptr i8* %FormulaPairs.addr.0.idx.val, i32 4
-  %1 = bitcast i8* %.idx12 to i8**
-  %.idx12.val = load i8** %1, align 4
-  %cmp = icmp eq i8* %.idx12.val, null
-  br i1 %cmp, label %if.end, label %if.then
-
-if.then:                                          ; preds = %for.body
-  tail call void @string_StringFree(i8* %.idx12.val) #1
-  br label %if.end
-
-if.end:                                           ; preds = %for.body, %if.then
-  %2 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i13 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %2, i32 0, i32 4
-  %3 = load i32* %total_size.i.i.i13, align 4
-  %4 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i14 = add i32 %4, %3
-  store i32 %add24.i.i.i14, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i15 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %2, i32 0, i32 0
-  %5 = load i8** %free.i.i.i15, align 4
-  %.c.i.i16 = bitcast i8* %5 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i16, %struct.LIST_HELP** %.idx, align 4
-  %6 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i17 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %6, i32 0, i32 0
-  store i8* %FormulaPairs.addr.0.idx.val, i8** %free27.i.i.i17, align 4
-  %L.idx.i = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019, i32 0, i32 0
-  %L.idx.val.i = load %struct.LIST_HELP** %L.idx.i, align 4
-  %7 = bitcast %struct.LIST_HELP* %FormulaPairs.addr.019 to i8*
-  %8 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %8, i32 0, i32 4
-  %9 = load i32* %total_size.i.i.i, align 4
-  %10 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i = add i32 %10, %9
-  store i32 %add24.i.i.i, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %8, i32 0, i32 0
-  %11 = load i8** %free.i.i.i, align 4
-  %.c.i.i = bitcast i8* %11 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i, %struct.LIST_HELP** %L.idx.i, align 4
-  %12 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %12, i32 0, i32 0
-  store i8* %7, i8** %free27.i.i.i, align 4
-  %cmp.i = icmp eq %struct.LIST_HELP* %L.idx.val.i, null
-  br i1 %cmp.i, label %for.end, label %for.body
-
-for.end:                                          ; preds = %if.end, %entry
-  ret void
-}
-
-; Function Attrs: nounwind
-define %struct.LIST_HELP* @dfg_TermParser(%struct._IO_FILE* %File, i32* %Flags, i32* %Precedence) #0 {
-entry:
-  store %struct._IO_FILE* %File, %struct._IO_FILE** @dfg_in, align 4
-  store i32 1, i32* @dfg_LINENUMBER, align 4
-  store i32 1, i32* @dfg_IGNORETEXT, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_AXIOMLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_CONJECLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_SORTDECLLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_USERPRECEDENCE, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_CONCLAUSES, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_PROOFLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_TERMLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_SYMBOLLIST, align 4
-  store %struct.LIST_HELP* null, %struct.LIST_HELP** @dfg_VARLIST, align 4
-  store i1 false, i1* @dfg_VARDECL, align 1
-  store i32 0, i32* @dfg_IGNORE, align 4
-  store i32* %Flags, i32** @dfg_FLAGS, align 4
-  store i32* %Precedence, i32** @dfg_PRECEDENCE, align 4
-  store i8* null, i8** @dfg_DESC.0, align 4
-  store i8* null, i8** @dfg_DESC.1, align 4
-  store i8* null, i8** @dfg_DESC.2, align 4
-  store i8* null, i8** @dfg_DESC.3, align 4
-  store i32 2, i32* @dfg_DESC.4, align 4
-  store i8* null, i8** @dfg_DESC.5, align 4
-  store i8* null, i8** @dfg_DESC.6, align 4
-  %call1 = tail call i32 @dfg_parse()
-  %0 = load %struct.LIST_HELP** @dfg_SYMBOLLIST, align 4
-  %cmp.i13.i = icmp eq %struct.LIST_HELP* %0, null
-  br i1 %cmp.i13.i, label %dfg_SymCleanUp.exit, label %while.body.lr.ph.i
-
-while.body.lr.ph.i:                               ; preds = %entry
-  %1 = load i32* @symbol_TYPESTATBITS, align 4
-  br label %while.body.i
-
-while.body.i:                                     ; preds = %if.end.i14, %while.body.lr.ph.i
-  %2 = phi %struct.LIST_HELP* [ %0, %while.body.lr.ph.i ], [ %L.idx.val.i.i7, %if.end.i14 ]
-  %.idx.i2 = getelementptr %struct.LIST_HELP* %2, i32 0, i32 1
-  %.idx.val.i3 = load i8** %.idx.i2, align 4
-  %symbol.i = bitcast i8* %.idx.val.i3 to i32*
-  %3 = load i32* %symbol.i, align 4
-  %arity.i = getelementptr inbounds i8* %.idx.val.i3, i32 8
-  %4 = bitcast i8* %arity.i to i32*
-  %5 = load i32* %4, align 4
-  %sub.i.i9.i = sub nsw i32 0, %3
-  %shr.i.i10.i = ashr i32 %sub.i.i9.i, %1
-  %6 = load %struct.signature*** @symbol_SIGNATURE, align 4
-  %arrayidx.i.i11.i = getelementptr inbounds %struct.signature** %6, i32 %shr.i.i10.i
-  %7 = load %struct.signature** %arrayidx.i.i11.i, align 4
-  %arity.i12.i = getelementptr inbounds %struct.signature* %7, i32 0, i32 3
-  %8 = load i32* %arity.i12.i, align 4
-  %cmp.i4 = icmp eq i32 %5, %8
-  br i1 %cmp.i4, label %if.end.i14, label %if.then.i5
-
-if.then.i5:                                       ; preds = %while.body.i
-  store i32 %5, i32* %arity.i12.i, align 4
-  br label %if.end.i14
-
-if.end.i14:                                       ; preds = %if.then.i5, %while.body.i
-  %9 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 12), align 4
-  %total_size.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %9, i32 0, i32 4
-  %10 = load i32* %total_size.i.i.i, align 4
-  %11 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i = add i32 %11, %10
-  store i32 %add24.i.i.i, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %9, i32 0, i32 0
-  %12 = load i8** %free.i.i.i, align 4
-  %.c.i.i = ptrtoint i8* %12 to i32
-  store i32 %.c.i.i, i32* %symbol.i, align 4
-  %13 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 12), align 4
-  %free27.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %13, i32 0, i32 0
-  store i8* %.idx.val.i3, i8** %free27.i.i.i, align 4
-  %14 = load %struct.LIST_HELP** @dfg_SYMBOLLIST, align 4
-  %L.idx.i.i6 = getelementptr %struct.LIST_HELP* %14, i32 0, i32 0
-  %L.idx.val.i.i7 = load %struct.LIST_HELP** %L.idx.i.i6, align 4
-  %15 = bitcast %struct.LIST_HELP* %14 to i8*
-  %16 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i8 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %16, i32 0, i32 4
-  %17 = load i32* %total_size.i.i.i.i8, align 4
-  %18 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i9 = add i32 %18, %17
-  store i32 %add24.i.i.i.i9, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i10 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %16, i32 0, i32 0
-  %19 = load i8** %free.i.i.i.i10, align 4
-  %.c.i.i.i11 = bitcast i8* %19 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i11, %struct.LIST_HELP** %L.idx.i.i6, align 4
-  %20 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i12 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %20, i32 0, i32 0
-  store i8* %15, i8** %free27.i.i.i.i12, align 4
-  store %struct.LIST_HELP* %L.idx.val.i.i7, %struct.LIST_HELP** @dfg_SYMBOLLIST, align 4
-  %cmp.i.i13 = icmp eq %struct.LIST_HELP* %L.idx.val.i.i7, null
-  br i1 %cmp.i.i13, label %dfg_SymCleanUp.exit, label %while.body.i
-
-dfg_SymCleanUp.exit:                              ; preds = %if.end.i14, %entry
-  %21 = load %struct.LIST_HELP** @dfg_AXCLAUSES, align 4
-  %cmp.i18.i15 = icmp eq %struct.LIST_HELP* %21, null
-  br i1 %cmp.i18.i15, label %dfg_DeleteFormulaPairList.exit40, label %for.body.i24
-
-for.body.i24:                                     ; preds = %dfg_SymCleanUp.exit, %if.end.i39
-  %FormulaPairs.addr.019.i16 = phi %struct.LIST_HELP* [ %L.idx.val.i.i32, %if.end.i39 ], [ %21, %dfg_SymCleanUp.exit ]
-  %FormulaPairs.addr.0.idx.i17 = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i16, i32 0, i32 1
-  %FormulaPairs.addr.0.idx.val.i18 = load i8** %FormulaPairs.addr.0.idx.i17, align 4
-  %.idx.i19 = bitcast i8* %FormulaPairs.addr.0.idx.val.i18 to %struct.LIST_HELP**
-  %.idx.val.i20 = load %struct.LIST_HELP** %.idx.i19, align 4
-  %22 = bitcast %struct.LIST_HELP* %.idx.val.i20 to %struct.term*
-  tail call void @term_Delete(%struct.term* %22) #1
-  %.idx12.i21 = getelementptr i8* %FormulaPairs.addr.0.idx.val.i18, i32 4
-  %23 = bitcast i8* %.idx12.i21 to i8**
-  %.idx12.val.i22 = load i8** %23, align 4
-  %cmp.i23 = icmp eq i8* %.idx12.val.i22, null
-  br i1 %cmp.i23, label %if.end.i39, label %if.then.i25
-
-if.then.i25:                                      ; preds = %for.body.i24
-  tail call void @string_StringFree(i8* %.idx12.val.i22) #1
-  br label %if.end.i39
-
-if.end.i39:                                       ; preds = %if.then.i25, %for.body.i24
-  %24 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i13.i26 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %24, i32 0, i32 4
-  %25 = load i32* %total_size.i.i.i13.i26, align 4
-  %26 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i14.i27 = add i32 %26, %25
-  store i32 %add24.i.i.i14.i27, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i15.i28 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %24, i32 0, i32 0
-  %27 = load i8** %free.i.i.i15.i28, align 4
-  %.c.i.i16.i29 = bitcast i8* %27 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i16.i29, %struct.LIST_HELP** %.idx.i19, align 4
-  %28 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i17.i30 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %28, i32 0, i32 0
-  store i8* %FormulaPairs.addr.0.idx.val.i18, i8** %free27.i.i.i17.i30, align 4
-  %L.idx.i.i31 = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i16, i32 0, i32 0
-  %L.idx.val.i.i32 = load %struct.LIST_HELP** %L.idx.i.i31, align 4
-  %29 = bitcast %struct.LIST_HELP* %FormulaPairs.addr.019.i16 to i8*
-  %30 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i33 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %30, i32 0, i32 4
-  %31 = load i32* %total_size.i.i.i.i33, align 4
-  %32 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i34 = add i32 %32, %31
-  store i32 %add24.i.i.i.i34, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i35 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %30, i32 0, i32 0
-  %33 = load i8** %free.i.i.i.i35, align 4
-  %.c.i.i.i36 = bitcast i8* %33 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i36, %struct.LIST_HELP** %L.idx.i.i31, align 4
-  %34 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i37 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %34, i32 0, i32 0
-  store i8* %29, i8** %free27.i.i.i.i37, align 4
-  %cmp.i.i38 = icmp eq %struct.LIST_HELP* %L.idx.val.i.i32, null
-  br i1 %cmp.i.i38, label %dfg_DeleteFormulaPairList.exit40, label %for.body.i24
-
-dfg_DeleteFormulaPairList.exit40:                 ; preds = %if.end.i39, %dfg_SymCleanUp.exit
-  %35 = load %struct.LIST_HELP** @dfg_CONCLAUSES, align 4
-  %cmp.i18.i41 = icmp eq %struct.LIST_HELP* %35, null
-  br i1 %cmp.i18.i41, label %dfg_DeleteFormulaPairList.exit66, label %for.body.i50
-
-for.body.i50:                                     ; preds = %dfg_DeleteFormulaPairList.exit40, %if.end.i65
-  %FormulaPairs.addr.019.i42 = phi %struct.LIST_HELP* [ %L.idx.val.i.i58, %if.end.i65 ], [ %35, %dfg_DeleteFormulaPairList.exit40 ]
-  %FormulaPairs.addr.0.idx.i43 = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i42, i32 0, i32 1
-  %FormulaPairs.addr.0.idx.val.i44 = load i8** %FormulaPairs.addr.0.idx.i43, align 4
-  %.idx.i45 = bitcast i8* %FormulaPairs.addr.0.idx.val.i44 to %struct.LIST_HELP**
-  %.idx.val.i46 = load %struct.LIST_HELP** %.idx.i45, align 4
-  %36 = bitcast %struct.LIST_HELP* %.idx.val.i46 to %struct.term*
-  tail call void @term_Delete(%struct.term* %36) #1
-  %.idx12.i47 = getelementptr i8* %FormulaPairs.addr.0.idx.val.i44, i32 4
-  %37 = bitcast i8* %.idx12.i47 to i8**
-  %.idx12.val.i48 = load i8** %37, align 4
-  %cmp.i49 = icmp eq i8* %.idx12.val.i48, null
-  br i1 %cmp.i49, label %if.end.i65, label %if.then.i51
-
-if.then.i51:                                      ; preds = %for.body.i50
-  tail call void @string_StringFree(i8* %.idx12.val.i48) #1
-  br label %if.end.i65
-
-if.end.i65:                                       ; preds = %if.then.i51, %for.body.i50
-  %38 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i13.i52 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %38, i32 0, i32 4
-  %39 = load i32* %total_size.i.i.i13.i52, align 4
-  %40 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i14.i53 = add i32 %40, %39
-  store i32 %add24.i.i.i14.i53, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i15.i54 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %38, i32 0, i32 0
-  %41 = load i8** %free.i.i.i15.i54, align 4
-  %.c.i.i16.i55 = bitcast i8* %41 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i16.i55, %struct.LIST_HELP** %.idx.i45, align 4
-  %42 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i17.i56 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %42, i32 0, i32 0
-  store i8* %FormulaPairs.addr.0.idx.val.i44, i8** %free27.i.i.i17.i56, align 4
-  %L.idx.i.i57 = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i42, i32 0, i32 0
-  %L.idx.val.i.i58 = load %struct.LIST_HELP** %L.idx.i.i57, align 4
-  %43 = bitcast %struct.LIST_HELP* %FormulaPairs.addr.019.i42 to i8*
-  %44 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i59 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %44, i32 0, i32 4
-  %45 = load i32* %total_size.i.i.i.i59, align 4
-  %46 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i60 = add i32 %46, %45
-  store i32 %add24.i.i.i.i60, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i61 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %44, i32 0, i32 0
-  %47 = load i8** %free.i.i.i.i61, align 4
-  %.c.i.i.i62 = bitcast i8* %47 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i62, %struct.LIST_HELP** %L.idx.i.i57, align 4
-  %48 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i63 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %48, i32 0, i32 0
-  store i8* %43, i8** %free27.i.i.i.i63, align 4
-  %cmp.i.i64 = icmp eq %struct.LIST_HELP* %L.idx.val.i.i58, null
-  br i1 %cmp.i.i64, label %dfg_DeleteFormulaPairList.exit66, label %for.body.i50
-
-dfg_DeleteFormulaPairList.exit66:                 ; preds = %if.end.i65, %dfg_DeleteFormulaPairList.exit40
-  %49 = load %struct.LIST_HELP** @dfg_AXIOMLIST, align 4
-  %cmp.i18.i67 = icmp eq %struct.LIST_HELP* %49, null
-  br i1 %cmp.i18.i67, label %dfg_DeleteFormulaPairList.exit92, label %for.body.i76
-
-for.body.i76:                                     ; preds = %dfg_DeleteFormulaPairList.exit66, %if.end.i91
-  %FormulaPairs.addr.019.i68 = phi %struct.LIST_HELP* [ %L.idx.val.i.i84, %if.end.i91 ], [ %49, %dfg_DeleteFormulaPairList.exit66 ]
-  %FormulaPairs.addr.0.idx.i69 = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i68, i32 0, i32 1
-  %FormulaPairs.addr.0.idx.val.i70 = load i8** %FormulaPairs.addr.0.idx.i69, align 4
-  %.idx.i71 = bitcast i8* %FormulaPairs.addr.0.idx.val.i70 to %struct.LIST_HELP**
-  %.idx.val.i72 = load %struct.LIST_HELP** %.idx.i71, align 4
-  %50 = bitcast %struct.LIST_HELP* %.idx.val.i72 to %struct.term*
-  tail call void @term_Delete(%struct.term* %50) #1
-  %.idx12.i73 = getelementptr i8* %FormulaPairs.addr.0.idx.val.i70, i32 4
-  %51 = bitcast i8* %.idx12.i73 to i8**
-  %.idx12.val.i74 = load i8** %51, align 4
-  %cmp.i75 = icmp eq i8* %.idx12.val.i74, null
-  br i1 %cmp.i75, label %if.end.i91, label %if.then.i77
-
-if.then.i77:                                      ; preds = %for.body.i76
-  tail call void @string_StringFree(i8* %.idx12.val.i74) #1
-  br label %if.end.i91
-
-if.end.i91:                                       ; preds = %if.then.i77, %for.body.i76
-  %52 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i13.i78 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %52, i32 0, i32 4
-  %53 = load i32* %total_size.i.i.i13.i78, align 4
-  %54 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i14.i79 = add i32 %54, %53
-  store i32 %add24.i.i.i14.i79, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i15.i80 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %52, i32 0, i32 0
-  %55 = load i8** %free.i.i.i15.i80, align 4
-  %.c.i.i16.i81 = bitcast i8* %55 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i16.i81, %struct.LIST_HELP** %.idx.i71, align 4
-  %56 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i17.i82 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %56, i32 0, i32 0
-  store i8* %FormulaPairs.addr.0.idx.val.i70, i8** %free27.i.i.i17.i82, align 4
-  %L.idx.i.i83 = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i68, i32 0, i32 0
-  %L.idx.val.i.i84 = load %struct.LIST_HELP** %L.idx.i.i83, align 4
-  %57 = bitcast %struct.LIST_HELP* %FormulaPairs.addr.019.i68 to i8*
-  %58 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i85 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %58, i32 0, i32 4
-  %59 = load i32* %total_size.i.i.i.i85, align 4
-  %60 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i86 = add i32 %60, %59
-  store i32 %add24.i.i.i.i86, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i87 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %58, i32 0, i32 0
-  %61 = load i8** %free.i.i.i.i87, align 4
-  %.c.i.i.i88 = bitcast i8* %61 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i88, %struct.LIST_HELP** %L.idx.i.i83, align 4
-  %62 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i89 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %62, i32 0, i32 0
-  store i8* %57, i8** %free27.i.i.i.i89, align 4
-  %cmp.i.i90 = icmp eq %struct.LIST_HELP* %L.idx.val.i.i84, null
-  br i1 %cmp.i.i90, label %dfg_DeleteFormulaPairList.exit92, label %for.body.i76
-
-dfg_DeleteFormulaPairList.exit92:                 ; preds = %if.end.i91, %dfg_DeleteFormulaPairList.exit66
-  %63 = load %struct.LIST_HELP** @dfg_CONJECLIST, align 4
-  %cmp.i18.i93 = icmp eq %struct.LIST_HELP* %63, null
-  br i1 %cmp.i18.i93, label %dfg_DeleteFormulaPairList.exit118, label %for.body.i102
-
-for.body.i102:                                    ; preds = %dfg_DeleteFormulaPairList.exit92, %if.end.i117
-  %FormulaPairs.addr.019.i94 = phi %struct.LIST_HELP* [ %L.idx.val.i.i110, %if.end.i117 ], [ %63, %dfg_DeleteFormulaPairList.exit92 ]
-  %FormulaPairs.addr.0.idx.i95 = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i94, i32 0, i32 1
-  %FormulaPairs.addr.0.idx.val.i96 = load i8** %FormulaPairs.addr.0.idx.i95, align 4
-  %.idx.i97 = bitcast i8* %FormulaPairs.addr.0.idx.val.i96 to %struct.LIST_HELP**
-  %.idx.val.i98 = load %struct.LIST_HELP** %.idx.i97, align 4
-  %64 = bitcast %struct.LIST_HELP* %.idx.val.i98 to %struct.term*
-  tail call void @term_Delete(%struct.term* %64) #1
-  %.idx12.i99 = getelementptr i8* %FormulaPairs.addr.0.idx.val.i96, i32 4
-  %65 = bitcast i8* %.idx12.i99 to i8**
-  %.idx12.val.i100 = load i8** %65, align 4
-  %cmp.i101 = icmp eq i8* %.idx12.val.i100, null
-  br i1 %cmp.i101, label %if.end.i117, label %if.then.i103
-
-if.then.i103:                                     ; preds = %for.body.i102
-  tail call void @string_StringFree(i8* %.idx12.val.i100) #1
-  br label %if.end.i117
-
-if.end.i117:                                      ; preds = %if.then.i103, %for.body.i102
-  %66 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i13.i104 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %66, i32 0, i32 4
-  %67 = load i32* %total_size.i.i.i13.i104, align 4
-  %68 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i14.i105 = add i32 %68, %67
-  store i32 %add24.i.i.i14.i105, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i15.i106 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %66, i32 0, i32 0
-  %69 = load i8** %free.i.i.i15.i106, align 4
-  %.c.i.i16.i107 = bitcast i8* %69 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i16.i107, %struct.LIST_HELP** %.idx.i97, align 4
-  %70 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i17.i108 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %70, i32 0, i32 0
-  store i8* %FormulaPairs.addr.0.idx.val.i96, i8** %free27.i.i.i17.i108, align 4
-  %L.idx.i.i109 = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i94, i32 0, i32 0
-  %L.idx.val.i.i110 = load %struct.LIST_HELP** %L.idx.i.i109, align 4
-  %71 = bitcast %struct.LIST_HELP* %FormulaPairs.addr.019.i94 to i8*
-  %72 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i111 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %72, i32 0, i32 4
-  %73 = load i32* %total_size.i.i.i.i111, align 4
-  %74 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i112 = add i32 %74, %73
-  store i32 %add24.i.i.i.i112, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i113 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %72, i32 0, i32 0
-  %75 = load i8** %free.i.i.i.i113, align 4
-  %.c.i.i.i114 = bitcast i8* %75 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i114, %struct.LIST_HELP** %L.idx.i.i109, align 4
-  %76 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i115 = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %76, i32 0, i32 0
-  store i8* %71, i8** %free27.i.i.i.i115, align 4
-  %cmp.i.i116 = icmp eq %struct.LIST_HELP* %L.idx.val.i.i110, null
-  br i1 %cmp.i.i116, label %dfg_DeleteFormulaPairList.exit118, label %for.body.i102
-
-dfg_DeleteFormulaPairList.exit118:                ; preds = %if.end.i117, %dfg_DeleteFormulaPairList.exit92
-  %77 = load %struct.LIST_HELP** @dfg_PROOFLIST, align 4
-  tail call void @dfg_DeleteProofList(%struct.LIST_HELP* %77)
-  %78 = load %struct.LIST_HELP** @dfg_SORTDECLLIST, align 4
-  %cmp.i18.i = icmp eq %struct.LIST_HELP* %78, null
-  br i1 %cmp.i18.i, label %dfg_DeleteFormulaPairList.exit, label %for.body.i
-
-for.body.i:                                       ; preds = %dfg_DeleteFormulaPairList.exit118, %if.end.i
-  %FormulaPairs.addr.019.i = phi %struct.LIST_HELP* [ %L.idx.val.i.i, %if.end.i ], [ %78, %dfg_DeleteFormulaPairList.exit118 ]
-  %FormulaPairs.addr.0.idx.i = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i, i32 0, i32 1
-  %FormulaPairs.addr.0.idx.val.i = load i8** %FormulaPairs.addr.0.idx.i, align 4
-  %.idx.i = bitcast i8* %FormulaPairs.addr.0.idx.val.i to %struct.LIST_HELP**
-  %.idx.val.i = load %struct.LIST_HELP** %.idx.i, align 4
-  %79 = bitcast %struct.LIST_HELP* %.idx.val.i to %struct.term*
-  tail call void @term_Delete(%struct.term* %79) #1
-  %.idx12.i = getelementptr i8* %FormulaPairs.addr.0.idx.val.i, i32 4
-  %80 = bitcast i8* %.idx12.i to i8**
-  %.idx12.val.i = load i8** %80, align 4
-  %cmp.i = icmp eq i8* %.idx12.val.i, null
-  br i1 %cmp.i, label %if.end.i, label %if.then.i
-
-if.then.i:                                        ; preds = %for.body.i
-  tail call void @string_StringFree(i8* %.idx12.val.i) #1
-  br label %if.end.i
-
-if.end.i:                                         ; preds = %if.then.i, %for.body.i
-  %81 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i13.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %81, i32 0, i32 4
-  %82 = load i32* %total_size.i.i.i13.i, align 4
-  %83 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i14.i = add i32 %83, %82
-  store i32 %add24.i.i.i14.i, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i15.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %81, i32 0, i32 0
-  %84 = load i8** %free.i.i.i15.i, align 4
-  %.c.i.i16.i = bitcast i8* %84 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i16.i, %struct.LIST_HELP** %.idx.i, align 4
-  %85 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i17.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %85, i32 0, i32 0
-  store i8* %FormulaPairs.addr.0.idx.val.i, i8** %free27.i.i.i17.i, align 4
-  %L.idx.i.i = getelementptr %struct.LIST_HELP* %FormulaPairs.addr.019.i, i32 0, i32 0
-  %L.idx.val.i.i = load %struct.LIST_HELP** %L.idx.i.i, align 4
-  %86 = bitcast %struct.LIST_HELP* %FormulaPairs.addr.019.i to i8*
-  %87 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %87, i32 0, i32 4
-  %88 = load i32* %total_size.i.i.i.i, align 4
-  %89 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i.i = add i32 %89, %88
-  store i32 %add24.i.i.i.i, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %87, i32 0, i32 0
-  %90 = load i8** %free.i.i.i.i, align 4
-  %.c.i.i.i = bitcast i8* %90 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i.i, %struct.LIST_HELP** %L.idx.i.i, align 4
-  %91 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %91, i32 0, i32 0
-  store i8* %86, i8** %free27.i.i.i.i, align 4
-  %cmp.i.i = icmp eq %struct.LIST_HELP* %L.idx.val.i.i, null
-  br i1 %cmp.i.i, label %dfg_DeleteFormulaPairList.exit, label %for.body.i
-
-dfg_DeleteFormulaPairList.exit:                   ; preds = %if.end.i, %dfg_DeleteFormulaPairList.exit118
-  %92 = load %struct.LIST_HELP** @dfg_TERMLIST, align 4
-  ret %struct.LIST_HELP* %92
-}
-
-; Function Attrs: nounwind
-define void @dfg_StripLabelsFromList(%struct.LIST_HELP* %FormulaPairs) #0 {
-entry:
-  %cmp.i15 = icmp eq %struct.LIST_HELP* %FormulaPairs, null
-  br i1 %cmp.i15, label %for.end, label %for.body
-
-for.body:                                         ; preds = %entry, %if.end
-  %scan.016 = phi %struct.LIST_HELP* [ %scan.0.idx12.val, %if.end ], [ %FormulaPairs, %entry ]
-  %scan.0.idx = getelementptr %struct.LIST_HELP* %scan.016, i32 0, i32 1
-  %scan.0.idx.val = load i8** %scan.0.idx, align 4
-  %.idx = bitcast i8* %scan.0.idx.val to %struct.LIST_HELP**
-  %.idx.val = load %struct.LIST_HELP** %.idx, align 4
-  %0 = bitcast %struct.LIST_HELP* %.idx.val to i8*
-  store i8* %0, i8** %scan.0.idx, align 4
-  %.idx14 = getelementptr i8* %scan.0.idx.val, i32 4
-  %1 = bitcast i8* %.idx14 to i8**
-  %.idx14.val = load i8** %1, align 4
-  %cmp = icmp eq i8* %.idx14.val, null
-  br i1 %cmp, label %if.end, label %if.then
-
-if.then:                                          ; preds = %for.body
-  tail call void @string_StringFree(i8* %.idx14.val) #1
-  br label %if.end
-
-if.end:                                           ; preds = %for.body, %if.then
-  %2 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %2, i32 0, i32 4
-  %3 = load i32* %total_size.i.i.i, align 4
-  %4 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i.i.i = add i32 %4, %3
-  store i32 %add24.i.i.i, i32* @memory_FREEDBYTES, align 4
-  %free.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %2, i32 0, i32 0
-  %5 = load i8** %free.i.i.i, align 4
-  %.c.i.i = bitcast i8* %5 to %struct.LIST_HELP*
-  store %struct.LIST_HELP* %.c.i.i, %struct.LIST_HELP** %.idx, align 4
-  %6 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i.i.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %6, i32 0, i32 0
-  store i8* %scan.0.idx.val, i8** %free27.i.i.i, align 4
-  %scan.0.idx12 = getelementptr %struct.LIST_HELP* %scan.016, i32 0, i32 0
-  %scan.0.idx12.val = load %struct.LIST_HELP** %scan.0.idx12, align 4
-  %cmp.i = icmp eq %struct.LIST_HELP* %scan.0.idx12.val, null
-  br i1 %cmp.i, label %for.end, label %for.body
-
-for.end:                                          ; preds = %if.end, %entry
-  ret void
-}
-
-declare %struct.LIST_HELP* @list_PointerDeleteDuplicates(%struct.LIST_HELP*) #2
-
-declare %struct.term* @fol_CreateQuantifier(i32, %struct.LIST_HELP*, %struct.LIST_HELP*) #2
-
-declare %struct.CLAUSE_HELP* @clause_CreateFromLiterals(%struct.LIST_HELP*, i32, i32, i32, i32*, i32*) #2
-
-declare void @list_DeleteWithElement(%struct.LIST_HELP*, void (i8*)*) #2
-
-; Function Attrs: nounwind
-define internal void @dfg_VarFree(%struct.DFG_VARENTRY* %Entry) #0 {
-entry:
-  %name = getelementptr inbounds %struct.DFG_VARENTRY* %Entry, i32 0, i32 0
-  %0 = load i8** %name, align 4
-  tail call void @string_StringFree(i8* %0) #1
-  %1 = bitcast %struct.DFG_VARENTRY* %Entry to i8*
-  %2 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %total_size.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %2, i32 0, i32 4
-  %3 = load i32* %total_size.i, align 4
-  %4 = load i32* @memory_FREEDBYTES, align 4
-  %add24.i = add i32 %4, %3
-  store i32 %add24.i, i32* @memory_FREEDBYTES, align 4
-  %free.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %2, i32 0, i32 0
-  %5 = load i8** %free.i, align 4
-  store i8* %5, i8** %name, align 4
-  %6 = load %struct.MEMORY_RESOURCEHELP** getelementptr inbounds ([0 x %struct.MEMORY_RESOURCEHELP*]* @memory_ARRAY, i32 0, i32 8), align 4
-  %free27.i = getelementptr inbounds %struct.MEMORY_RESOURCEHELP* %6, i32 0, i32 0
-  store i8* %1, i8** %free27.i, align 4
-  ret void
-}
-
-declare %struct.term* @term_Copy(%struct.term*) #2
-
-declare i8* @memory_Malloc(i32) #2
-
-declare i32 @symbol_CreateFunction(i8*, i32, i32, i32*) #2
-
-declare i32 @symbol_CreatePredicate(i8*, i32, i32, i32*) #2
-
-declare i32 @symbol_CreateJunctor(i8*, i32, i32, i32*) #2
-
-; Function Attrs: noreturn nounwind
-declare void @abort() #5
-
-declare i32 @symbol_GetIncreasedOrderingCounter() #2
-
-declare i32 @flag_Minimum(i32) #2
-
-declare i8* @flag_Name(i32) #2
-
-declare i32 @flag_Maximum(i32) #2
-
-; Function Attrs: nounwind readonly
-declare i32 @strcmp(i8* nocapture, i8* nocapture) #4
-
-declare i32 @list_Length(%struct.LIST_HELP*) #2
-
-; Function Attrs: noreturn nounwind
-declare void @exit(i32) #5
-
-; Function Attrs: nounwind
-declare i32 @fwrite(i8* nocapture, i32, i32, %struct._IO_FILE* nocapture) #1
+; cmp16: 	.ent	getSubImagesLuma
+; cmp16:	.end	getSubImagesLuma
+declare i32 @iClip3(...) #1
 
-attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="true" }
-attributes #1 = { nounwind }
-attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="true" }
-attributes #3 = { inlinehint noreturn nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="true" }
-attributes #4 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="true" }
-attributes #5 = { noreturn nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="true" }
-attributes #6 = { nounwind readonly }
-attributes #7 = { noreturn nounwind }
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind }
 
+!0 = metadata !{metadata !"int", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA"}
diff --git a/test/CodeGen/Mips/const-mult.ll b/test/CodeGen/Mips/const-mult.ll
new file mode 100644
index 0000000..8c0cbe3
--- /dev/null
+++ b/test/CodeGen/Mips/const-mult.ll
@@ -0,0 +1,49 @@
+; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=CHECK
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK
+; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK64
+
+; CHECK-LABEL: mul5_32:
+; CHECK: sll $[[R0:[0-9]+]], $4, 2
+; CHECK: addu ${{[0-9]+}}, $[[R0]], $4
+
+define i32 @mul5_32(i32 %a) {
+entry:
+  %mul = mul nsw i32 %a, 5
+  ret i32 %mul
+}
+
+; CHECK-LABEL:     mul27_32:
+; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
+; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
+; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 5
+; CHECK:     subu ${{[0-9]+}}, $[[R2]], $[[R1]]
+
+define i32 @mul27_32(i32 %a) {
+entry:
+  %mul = mul nsw i32 %a, 27
+  ret i32 %mul
+}
+
+; CHECK-LABEL:     muln2147483643_32:
+; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
+; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
+; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 31
+; CHECK:     addu ${{[0-9]+}}, $[[R2]], $[[R1]]
+
+define i32 @muln2147483643_32(i32 %a) {
+entry:
+  %mul = mul nsw i32 %a, -2147483643
+  ret i32 %mul
+}
+
+; CHECK64-LABEL:     muln9223372036854775805_64:
+; CHECK64-DAG: dsll $[[R0:[0-9]+]], $4, 1
+; CHECK64-DAG: daddu $[[R1:[0-9]+]], $[[R0]], $4
+; CHECK64-DAG: dsll $[[R2:[0-9]+]], $4, 63
+; CHECK64:     daddu ${{[0-9]+}}, $[[R2]], $[[R1]]
+
+define i64 @muln9223372036854775805_64(i64 %a) {
+entry:
+  %mul = mul nsw i64 %a, -9223372036854775805
+  ret i64 %mul
+}
diff --git a/test/CodeGen/Mips/divrem.ll b/test/CodeGen/Mips/divrem.ll
index 47cebbe..a983c46 100644
--- a/test/CodeGen/Mips/divrem.ll
+++ b/test/CodeGen/Mips/divrem.ll
@@ -2,12 +2,12 @@
 ; RUN: llc -march=mips -mno-check-zero-division < %s |\
 ; RUN: FileCheck %s -check-prefix=NOCHECK
 
-; TRAP: sdiv1:
+; TRAP-LABEL: sdiv1:
 ; TRAP: div $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; TRAP: teq $[[R0]], $zero, 7
 ; TRAP: mflo
 
-; NOCHECK: sdiv1:
+; NOCHECK-LABEL: sdiv1:
 ; NOCHECK-NOT: teq
 ; NOCHECK: .end sdiv1
 
@@ -17,7 +17,7 @@ entry:
   ret i32 %div
 }
 
-; TRAP: srem1:
+; TRAP-LABEL: srem1:
 ; TRAP: div $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; TRAP: teq $[[R0]], $zero, 7
 ; TRAP: mfhi
@@ -28,7 +28,7 @@ entry:
   ret i32 %rem
 }
 
-; TRAP: udiv1:
+; TRAP-LABEL: udiv1:
 ; TRAP: divu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; TRAP: teq $[[R0]], $zero, 7
 ; TRAP: mflo
@@ -39,7 +39,7 @@ entry:
   ret i32 %div
 }
 
-; TRAP: urem1:
+; TRAP-LABEL: urem1:
 ; TRAP: divu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; TRAP: teq $[[R0]], $zero, 7
 ; TRAP: mfhi
diff --git a/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll b/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
index 9f2f066..a5fe34c 100644
--- a/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
+++ b/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s
 
-; CHECK: select_v2q15_eq_:
+; CHECK-LABEL: select_v2q15_eq_:
 ; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.ph ${{[0-9]+}}, $6, $7
 
@@ -17,7 +17,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2q15_lt_:
+; CHECK-LABEL: select_v2q15_lt_:
 ; CHECK: cmp.lt.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, $6, $7
 
@@ -34,7 +34,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2q15_le_:
+; CHECK-LABEL: select_v2q15_le_:
 ; CHECK: cmp.le.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, $6, $7
 
@@ -51,7 +51,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2q15_ne_:
+; CHECK-LABEL: select_v2q15_ne_:
 ; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.ph ${{[0-9]+}}, $7, $6
 
@@ -68,7 +68,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2q15_gt_:
+; CHECK-LABEL: select_v2q15_gt_:
 ; CHECK: cmp.le.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, $7, $6
 
@@ -85,7 +85,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2q15_ge_:
+; CHECK-LABEL: select_v2q15_ge_:
 ; CHECK: cmp.lt.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, $7, $6
 
@@ -102,7 +102,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_eq_:
+; CHECK-LABEL: select_v4ui8_eq_:
 ; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.qb ${{[0-9]+}}, $6, $7
 
@@ -119,7 +119,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_lt_:
+; CHECK-LABEL: select_v4ui8_lt_:
 ; CHECK: cmpu.lt.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, $6, $7
 
@@ -136,7 +136,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_le_:
+; CHECK-LABEL: select_v4ui8_le_:
 ; CHECK: cmpu.le.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, $6, $7
 
@@ -153,7 +153,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_ne_:
+; CHECK-LABEL: select_v4ui8_ne_:
 ; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.qb ${{[0-9]+}}, $7, $6
 
@@ -170,7 +170,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_gt_:
+; CHECK-LABEL: select_v4ui8_gt_:
 ; CHECK: cmpu.le.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, $7, $6
 
@@ -187,7 +187,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4ui8_ge_:
+; CHECK-LABEL: select_v4ui8_ge_:
 ; CHECK: cmpu.lt.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, $7, $6
 
@@ -204,7 +204,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2ui16_lt_:
+; CHECK-LABEL: select_v2ui16_lt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -221,7 +221,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2ui16_le_:
+; CHECK-LABEL: select_v2ui16_le_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -238,7 +238,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2ui16_gt_:
+; CHECK-LABEL: select_v2ui16_gt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -255,7 +255,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v2ui16_ge_:
+; CHECK-LABEL: select_v2ui16_ge_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -272,7 +272,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4i8_lt_:
+; CHECK-LABEL: select_v4i8_lt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -289,7 +289,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4i8_le_:
+; CHECK-LABEL: select_v4i8_le_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -306,7 +306,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4i8_gt_:
+; CHECK-LABEL: select_v4i8_gt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -323,7 +323,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: select_v4i8_ge_:
+; CHECK-LABEL: select_v4i8_ge_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -340,7 +340,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_eq_:
+; CHECK-LABEL: compare_v2q15_eq_:
 ; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -355,7 +355,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_lt_:
+; CHECK-LABEL: compare_v2q15_lt_:
 ; CHECK: cmp.lt.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -370,7 +370,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_le_:
+; CHECK-LABEL: compare_v2q15_le_:
 ; CHECK: cmp.le.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -385,7 +385,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_ne_:
+; CHECK-LABEL: compare_v2q15_ne_:
 ; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -400,7 +400,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_gt_:
+; CHECK-LABEL: compare_v2q15_gt_:
 ; CHECK: cmp.le.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -415,7 +415,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2q15_ge_:
+; CHECK-LABEL: compare_v2q15_ge_:
 ; CHECK: cmp.lt.ph $4, $5
 ; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -430,7 +430,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_eq_:
+; CHECK-LABEL: compare_v4ui8_eq_:
 ; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -445,7 +445,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_lt_:
+; CHECK-LABEL: compare_v4ui8_lt_:
 ; CHECK: cmpu.lt.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -460,7 +460,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_le_:
+; CHECK-LABEL: compare_v4ui8_le_:
 ; CHECK: cmpu.le.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -475,7 +475,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_ne_:
+; CHECK-LABEL: compare_v4ui8_ne_:
 ; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -490,7 +490,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_gt_:
+; CHECK-LABEL: compare_v4ui8_gt_:
 ; CHECK: cmpu.le.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -505,7 +505,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4ui8_ge_:
+; CHECK-LABEL: compare_v4ui8_ge_:
 ; CHECK: cmpu.lt.qb $4, $5
 ; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
 
@@ -520,7 +520,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2ui16_lt_:
+; CHECK-LABEL: compare_v2ui16_lt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -535,7 +535,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2ui16_le_:
+; CHECK-LABEL: compare_v2ui16_le_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -550,7 +550,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2ui16_gt_:
+; CHECK-LABEL: compare_v2ui16_gt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -565,7 +565,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v2ui16_ge_:
+; CHECK-LABEL: compare_v2ui16_ge_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -580,7 +580,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4i8_lt_:
+; CHECK-LABEL: compare_v4i8_lt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -595,7 +595,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4i8_le_:
+; CHECK-LABEL: compare_v4i8_le_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -610,7 +610,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4i8_gt_:
+; CHECK-LABEL: compare_v4i8_gt_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
@@ -625,7 +625,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; CHECK: compare_v4i8_ge_:
+; CHECK-LABEL: compare_v4i8_ge_:
 ; CHECK-NOT: cmp
 ; CHECK-NOT: pick
 
diff --git a/test/CodeGen/Mips/dsp-patterns.ll b/test/CodeGen/Mips/dsp-patterns.ll
index eeb7140..f5bb3ab 100644
--- a/test/CodeGen/Mips/dsp-patterns.ll
+++ b/test/CodeGen/Mips/dsp-patterns.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=R1
 ; RUN: llc -march=mips -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2
 
-; R1: test_lbux:
+; R1-LABEL: test_lbux:
 ; R1: lbux ${{[0-9]+}}
 
 define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) {
@@ -11,7 +11,7 @@ entry:
   ret i8 %0
 }
 
-; R1: test_lhx:
+; R1-LABEL: test_lhx:
 ; R1: lhx ${{[0-9]+}}
 
 define signext i16 @test_lhx(i16* nocapture %b, i32 %i) {
@@ -21,7 +21,7 @@ entry:
   ret i16 %0
 }
 
-; R1: test_lwx:
+; R1-LABEL: test_lwx:
 ; R1: lwx ${{[0-9]+}}
 
 define i32 @test_lwx(i32* nocapture %b, i32 %i) {
@@ -31,7 +31,7 @@ entry:
   ret i32 %0
 }
 
-; R1: test_add_v2q15_:
+; R1-LABEL: test_add_v2q15_:
 ; R1: addq.ph ${{[0-9]+}}
 
 define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) {
@@ -44,7 +44,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: test_sub_v2q15_:
+; R1-LABEL: test_sub_v2q15_:
 ; R1: subq.ph ${{[0-9]+}}
 
 define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) {
@@ -57,11 +57,11 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R2: test_mul_v2q15_:
+; R2-LABEL: test_mul_v2q15_:
 ; R2: mul.ph ${{[0-9]+}}
 
 ; mul.ph is an R2 instruction. Check that multiply node gets expanded.
-; R1: test_mul_v2q15_:
+; R1-LABEL: test_mul_v2q15_:
 ; R1: mul ${{[0-9]+}}
 ; R1: mul ${{[0-9]+}}
 
@@ -75,7 +75,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: test_add_v4i8_:
+; R1-LABEL: test_add_v4i8_:
 ; R1: addu.qb ${{[0-9]+}}
 
 define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) {
@@ -88,7 +88,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: test_sub_v4i8_:
+; R1-LABEL: test_sub_v4i8_:
 ; R1: subu.qb ${{[0-9]+}}
 
 define { i32 } @test_sub_v4i8_(i32 %a.coerce, i32 %b.coerce) {
@@ -102,7 +102,7 @@ entry:
 }
 
 ; DSP-ASE doesn't have a v4i8 multiply instruction. Check that multiply node gets expanded.
-; R2: test_mul_v4i8_:
+; R2-LABEL: test_mul_v4i8_:
 ; R2: mul ${{[0-9]+}}
 ; R2: mul ${{[0-9]+}}
 ; R2: mul ${{[0-9]+}}
@@ -118,7 +118,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: test_addsc:
+; R1-LABEL: test_addsc:
 ; R1: addsc ${{[0-9]+}}
 ; R1: addwc ${{[0-9]+}}
 
@@ -128,7 +128,7 @@ entry:
   ret i64 %add
 }
 
-; R1: shift1_v2i16_shl_:
+; R1-LABEL: shift1_v2i16_shl_:
 ; R1: shll.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
 
 define { i32 } @shift1_v2i16_shl_(i32 %a0.coerce) {
@@ -140,7 +140,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: shift1_v2i16_sra_:
+; R1-LABEL: shift1_v2i16_sra_:
 ; R1: shra.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
 
 define { i32 } @shift1_v2i16_sra_(i32 %a0.coerce) {
@@ -152,9 +152,9 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: shift1_v2ui16_srl_:
+; R1-LABEL: shift1_v2ui16_srl_:
 ; R1-NOT: shrl.ph
-; R2: shift1_v2ui16_srl_:
+; R2-LABEL: shift1_v2ui16_srl_:
 ; R2: shrl.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
 
 define { i32 } @shift1_v2ui16_srl_(i32 %a0.coerce) {
@@ -166,7 +166,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: shift1_v4i8_shl_:
+; R1-LABEL: shift1_v4i8_shl_:
 ; R1: shll.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
 
 define { i32 } @shift1_v4i8_shl_(i32 %a0.coerce) {
@@ -178,9 +178,9 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: shift1_v4i8_sra_:
+; R1-LABEL: shift1_v4i8_sra_:
 ; R1-NOT: shra.qb
-; R2: shift1_v4i8_sra_:
+; R2-LABEL: shift1_v4i8_sra_:
 ; R2: shra.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
 
 define { i32 } @shift1_v4i8_sra_(i32 %a0.coerce) {
@@ -192,7 +192,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: shift1_v4ui8_srl_:
+; R1-LABEL: shift1_v4ui8_srl_:
 ; R1: shrl.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
 
 define { i32 } @shift1_v4ui8_srl_(i32 %a0.coerce) {
@@ -206,7 +206,7 @@ entry:
 
 ; Check that shift node is expanded if splat element size is not 16-bit.
 ;
-; R1: test_vector_splat_imm_v2q15:
+; R1-LABEL: test_vector_splat_imm_v2q15:
 ; R1-NOT: shll.ph
 
 define { i32 } @test_vector_splat_imm_v2q15(i32 %a.coerce) {
@@ -220,7 +220,7 @@ entry:
 
 ; Check that shift node is expanded if splat element size is not 8-bit.
 ;
-; R1: test_vector_splat_imm_v4i8:
+; R1-LABEL: test_vector_splat_imm_v4i8:
 ; R1-NOT: shll.qb
 
 define { i32 } @test_vector_splat_imm_v4i8(i32 %a.coerce) {
@@ -234,7 +234,7 @@ entry:
 
 ; Check that shift node is expanded if shift amount doesn't fit in 4-bit sa field.
 ;
-; R1: test_shift_amount_v2q15:
+; R1-LABEL: test_shift_amount_v2q15:
 ; R1-NOT: shll.ph
 
 define { i32 } @test_shift_amount_v2q15(i32 %a.coerce) {
@@ -248,7 +248,7 @@ entry:
 
 ; Check that shift node is expanded if shift amount doesn't fit in 3-bit sa field.
 ;
-; R1: test_shift_amount_v4i8:
+; R1-LABEL: test_shift_amount_v4i8:
 ; R1-NOT: shll.qb
 
 define { i32 } @test_shift_amount_v4i8(i32 %a.coerce) {
diff --git a/test/CodeGen/Mips/dsp-vec-load-store.ll b/test/CodeGen/Mips/dsp-vec-load-store.ll
new file mode 100644
index 0000000..7e4a8fe
--- /dev/null
+++ b/test/CodeGen/Mips/dsp-vec-load-store.ll
@@ -0,0 +1,11 @@
+; RUN: llc -march=mipsel -mattr=+dsp < %s
+
+@g1 = common global <2 x i8> zeroinitializer, align 2
+@g0 = common global <2 x i8> zeroinitializer, align 2
+
+define void @extend_load_trunc_store_v2i8() {
+entry:
+  %0 = load <2 x i8>* @g1, align 2
+  store <2 x i8> %0, <2 x i8>* @g0, align 2
+  ret void
+}
diff --git a/test/CodeGen/Mips/ex2.ll b/test/CodeGen/Mips/ex2.ll
index 74bdb6c..c5535e7 100644
--- a/test/CodeGen/Mips/ex2.ll
+++ b/test/CodeGen/Mips/ex2.ll
@@ -4,12 +4,13 @@
 @_ZTIPKc = external constant i8*
 
 define i32 @main() {
-; 16: main:
+; 16-LABEL: main:
 ; 16: 	.cfi_startproc
-; 16: 	save	$ra, $s0, $s1, 32
-; 16:   .cfi_def_cfa_offset 32
-; 16:   .cfi_offset 17, -8
-; 16: 	.cfi_offset 16, -12
+; 16: 	save	$ra, $s0, $s1, $s2, 40
+; 16:   .cfi_def_cfa_offset 40
+; 16:   .cfi_offset 18, -8
+; 16:   .cfi_offset 17, -12
+; 16: 	.cfi_offset 16, -16
 ; 16: 	.cfi_offset 31, -4
 ; 16:   .cfi_endproc
 entry:
diff --git a/test/CodeGen/Mips/fcopysign-f32-f64.ll b/test/CodeGen/Mips/fcopysign-f32-f64.ll
index b36473d..9f88d0c 100644
--- a/test/CodeGen/Mips/fcopysign-f32-f64.ll
+++ b/test/CodeGen/Mips/fcopysign-f32-f64.ll
@@ -7,14 +7,15 @@ declare float @copysignf(float, float) nounwind readnone
 
 define float @func2(float %d, double %f) nounwind readnone {
 entry:
-; 64: func2
-; 64: lui  $[[T0:[0-9]+]], 32767
-; 64: ori  $[[MSK0:[0-9]+]], $[[T0]], 65535
-; 64: and  $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
-; 64: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 63
-; 64: sll  $[[SLL:[0-9]+]], ${{[0-9]+}}, 31
-; 64: or   $[[OR:[0-9]+]], $[[AND0]], $[[SLL]]
-; 64: mtc1 $[[OR]], $f0
+; 64:     func2
+; 64-DAG: lui  $[[T0:[0-9]+]], 32767
+; 64-DAG: ori  $[[MSK0:[0-9]+]], $[[T0]], 65535
+; 64-DAG: and  $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
+; 64-DAG: dsrl $[[DSRL:[0-9]+]], ${{[0-9]+}}, 63
+; 64-DAG: sll  $[[SLL0:[0-9]+]], $[[DSRL]], 0
+; 64-DAG: sll  $[[SLL1:[0-9]+]], $[[SLL0]], 31
+; 64:     or   $[[OR:[0-9]+]], $[[AND0]], $[[SLL1]]
+; 64:     mtc1 $[[OR]], $f0
 
 ; 64R2: dext ${{[0-9]+}}, ${{[0-9]+}}, 63, 1
 ; 64R2: ins  $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1
@@ -29,14 +30,16 @@ entry:
 define double @func3(double %d, float %f) nounwind readnone {
 entry:
 
-; 64: daddiu $[[T0:[0-9]+]], $zero, 1
-; 64: dsll   $[[T1:[0-9]+]], $[[T0]], 63
-; 64: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1
-; 64: and    $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
-; 64: srl    ${{[0-9]+}}, ${{[0-9]+}}, 31
-; 64: dsll   $[[DSLL:[0-9]+]], ${{[0-9]+}}, 63
-; 64: or     $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
-; 64: dmtc1  $[[OR]], $f0
+; 64:     func3
+; 64-DAG: daddiu $[[T0:[0-9]+]], $zero, 1
+; 64-DAG: dsll   $[[T1:[0-9]+]], $[[T0]], 63
+; 64-DAG: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1
+; 64-DAG: and    $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
+; 64-DAG: srl    $[[SRL:[0-9]+]], ${{[0-9]+}}, 31
+; 64-DAG: sll    $[[SLL:[0-9]+]], $[[SRL]], 0
+; 64-DAG: dsll   $[[DSLL:[0-9]+]], $[[SLL]], 63
+; 64:     or     $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
+; 64:     dmtc1  $[[OR]], $f0
 
 ; 64R2: ext   ${{[0-9]+}}, ${{[0-9]+}}, 31, 1
 ; 64R2: dins  $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1
diff --git a/test/CodeGen/Mips/fp16instrinsmc.ll b/test/CodeGen/Mips/fp16instrinsmc.ll
new file mode 100644
index 0000000..3c01d56
--- /dev/null
+++ b/test/CodeGen/Mips/fp16instrinsmc.ll
@@ -0,0 +1,368 @@
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic < %s | FileCheck %s -check-prefix=pic
+
+@x = global float 1.500000e+00, align 4
+@xn = global float -1.900000e+01, align 4
+@negone = global float -1.000000e+00, align 4
+@one = global float 1.000000e+00, align 4
+@xd = global double 0x40048B0A8EA4481E, align 8
+@xdn = global double 0xC0311F9ADD373963, align 8
+@negoned = global double -1.000000e+00, align 8
+@oned = global float 1.000000e+00, align 4
+@y = common global float 0.000000e+00, align 4
+@yd = common global double 0.000000e+00, align 8
+
+; Function Attrs: nounwind
+define void @foo1() #0 {
+entry:
+  %0 = load float* @x, align 4
+  %1 = load float* @one, align 4
+  %call = call float @copysignf(float %0, float %1) #2
+  store float %call, float* @y, align 4
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare float @copysignf(float, float) #1
+
+; Function Attrs: nounwind
+define void @foo2() #0 {
+entry:
+  %0 = load float* @x, align 4
+  %1 = load float* @negone, align 4
+  %call = call float @copysignf(float %0, float %1) #2
+  store float %call, float* @y, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @foo3() #0 {
+entry:
+  %0 = load double* @xd, align 8
+  %1 = load float* @oned, align 4
+  %conv = fpext float %1 to double
+  %call = call double @copysign(double %0, double %conv) #2
+  store double %call, double* @yd, align 8
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare double @copysign(double, double) #1
+
+; Function Attrs: nounwind
+define void @foo4() #0 {
+entry:
+  %0 = load double* @xd, align 8
+  %1 = load double* @negoned, align 8
+  %call = call double @copysign(double %0, double %1) #2
+  store double %call, double* @yd, align 8
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @foo5() #0 {
+entry:
+  %0 = load float* @xn, align 4
+  %call = call float @fabsf(float %0) #2
+  store float %call, float* @y, align 4
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare float @fabsf(float) #1
+
+; Function Attrs: nounwind
+define void @foo6() #0 {
+entry:
+  %0 = load double* @xdn, align 8
+  %call = call double @fabs(double %0) #2
+  store double %call, double* @yd, align 8
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare double @fabs(double) #1
+
+; Function Attrs: nounwind
+define void @foo7() #0 {
+entry:
+  %0 = load float* @x, align 4
+  %call = call float @sinf(float %0) #3
+;pic:	lw	${{[0-9]+}}, %call16(sinf)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
+  store float %call, float* @y, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+declare float @sinf(float) #0
+
+; Function Attrs: nounwind
+define void @foo8() #0 {
+entry:
+  %0 = load double* @xd, align 8
+  %call = call double @sin(double %0) #3
+;pic:	lw	${{[0-9]+}}, %call16(sin)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
+  store double %call, double* @yd, align 8
+  ret void
+}
+
+; Function Attrs: nounwind
+declare double @sin(double) #0
+
+; Function Attrs: nounwind
+define void @foo9() #0 {
+entry:
+  %0 = load float* @x, align 4
+  %call = call float @cosf(float %0) #3
+;pic:	lw	${{[0-9]+}}, %call16(cosf)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
+  store float %call, float* @y, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+declare float @cosf(float) #0
+
+; Function Attrs: nounwind
+define void @foo10() #0 {
+entry:
+  %0 = load double* @xd, align 8
+  %call = call double @cos(double %0) #3
+;pic:	lw	${{[0-9]+}}, %call16(cos)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
+  store double %call, double* @yd, align 8
+  ret void
+}
+
+; Function Attrs: nounwind
+declare double @cos(double) #0
+
+; Function Attrs: nounwind
+define void @foo11() #0 {
+entry:
+  %0 = load float* @x, align 4
+  %call = call float @sqrtf(float %0) #3
+;pic:	lw	${{[0-9]+}}, %call16(sqrtf)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
+  store float %call, float* @y, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+declare float @sqrtf(float) #0
+
+; Function Attrs: nounwind
+define void @foo12() #0 {
+entry:
+  %0 = load double* @xd, align 8
+  %call = call double @sqrt(double %0) #3
+;pic:	lw	${{[0-9]+}}, %call16(sqrt)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
+  store double %call, double* @yd, align 8
+  ret void
+}
+
+; Function Attrs: nounwind
+declare double @sqrt(double) #0
+
+; Function Attrs: nounwind
+define void @foo13() #0 {
+entry:
+  %0 = load float* @x, align 4
+  %call = call float @floorf(float %0) #2
+;pic:	lw	${{[0-9]+}}, %call16(floorf)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
+  store float %call, float* @y, align 4
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare float @floorf(float) #1
+
+; Function Attrs: nounwind
+define void @foo14() #0 {
+entry:
+  %0 = load double* @xd, align 8
+  %call = call double @floor(double %0) #2
+;pic:	lw	${{[0-9]+}}, %call16(floor)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
+  store double %call, double* @yd, align 8
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare double @floor(double) #1
+
+; Function Attrs: nounwind
+define void @foo15() #0 {
+entry:
+  %0 = load float* @x, align 4
+  %call = call float @nearbyintf(float %0) #2
+;pic:	lw	${{[0-9]+}}, %call16(nearbyintf)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
+  store float %call, float* @y, align 4
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare float @nearbyintf(float) #1
+
+; Function Attrs: nounwind
+define void @foo16() #0 {
+entry:
+  %0 = load double* @xd, align 8
+  %call = call double @nearbyint(double %0) #2
+;pic:	lw	${{[0-9]+}}, %call16(nearbyint)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
+  store double %call, double* @yd, align 8
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare double @nearbyint(double) #1
+
+; Function Attrs: nounwind
+define void @foo17() #0 {
+entry:
+  %0 = load float* @x, align 4
+  %call = call float @ceilf(float %0) #2
+;pic:	lw	${{[0-9]+}}, %call16(ceilf)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
+  store float %call, float* @y, align 4
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare float @ceilf(float) #1
+
+; Function Attrs: nounwind
+define void @foo18() #0 {
+entry:
+  %0 = load double* @xd, align 8
+  %call = call double @ceil(double %0) #2
+;pic:	lw	${{[0-9]+}}, %call16(ceil)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
+  store double %call, double* @yd, align 8
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare double @ceil(double) #1
+
+; Function Attrs: nounwind
+define void @foo19() #0 {
+entry:
+  %0 = load float* @x, align 4
+  %call = call float @rintf(float %0) #2
+;pic:	lw	${{[0-9]+}}, %call16(rintf)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
+  store float %call, float* @y, align 4
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare float @rintf(float) #1
+
+; Function Attrs: nounwind
+define void @foo20() #0 {
+entry:
+  %0 = load double* @xd, align 8
+  %call = call double @rint(double %0) #2
+;pic:	lw	${{[0-9]+}}, %call16(rint)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
+  store double %call, double* @yd, align 8
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare double @rint(double) #1
+
+; Function Attrs: nounwind
+define void @foo21() #0 {
+entry:
+  %0 = load float* @x, align 4
+  %call = call float @truncf(float %0) #2
+;pic:	lw	${{[0-9]+}}, %call16(truncf)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
+  store float %call, float* @y, align 4
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare float @truncf(float) #1
+
+; Function Attrs: nounwind
+define void @foo22() #0 {
+entry:
+  %0 = load double* @xd, align 8
+  %call = call double @trunc(double %0) #2
+;pic:	lw	${{[0-9]+}}, %call16(trunc)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
+  store double %call, double* @yd, align 8
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare double @trunc(double) #1
+
+; Function Attrs: nounwind
+define void @foo23() #0 {
+entry:
+  %0 = load float* @x, align 4
+  %call = call float @log2f(float %0) #3
+;pic:	lw	${{[0-9]+}}, %call16(log2f)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
+  store float %call, float* @y, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+declare float @log2f(float) #0
+
+; Function Attrs: nounwind
+define void @foo24() #0 {
+entry:
+  %0 = load double* @xd, align 8
+  %call = call double @log2(double %0) #3
+;pic:	lw	${{[0-9]+}}, %call16(log2)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
+  store double %call, double* @yd, align 8
+  ret void
+}
+
+; Function Attrs: nounwind
+declare double @log2(double) #0
+
+; Function Attrs: nounwind
+define void @foo25() #0 {
+entry:
+  %0 = load float* @x, align 4
+  %call = call float @exp2f(float %0) #3
+;pic:	lw	${{[0-9]+}}, %call16(exp2f)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_sf_1)(${{[0-9]+}})
+  store float %call, float* @y, align 4
+  ret void
+}
+
+; Function Attrs: nounwind
+declare float @exp2f(float) #0
+
+; Function Attrs: nounwind
+define void @foo26() #0 {
+entry:
+  %0 = load double* @xd, align 8
+  %call = call double @exp2(double %0) #3
+;pic:	lw	${{[0-9]+}}, %call16(exp2)(${{[0-9]+}})
+;pic:	lw	${{[0-9]+}}, %got(__mips16_call_stub_df_2)(${{[0-9]+}})
+  store double %call, double* @yd, align 8
+  ret void
+}
+
+; Function Attrs: nounwind
+declare double @exp2(double) #0
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" }
+attributes #1 = { nounwind readnone "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" }
+attributes #2 = { nounwind readnone }
+attributes #3 = { nounwind }
diff --git a/test/CodeGen/Mips/helloworld.ll b/test/CodeGen/Mips/helloworld.ll
index 56ee607..83c88ae 100644
--- a/test/CodeGen/Mips/helloworld.ll
+++ b/test/CodeGen/Mips/helloworld.ll
@@ -25,7 +25,7 @@ entry:
 ; SR32:  .set noreorder
 ; SR32:  .set nomacro
 ; SR32:  .set noat
-; SR:	save 	$ra, $s0, $s1, [[FS:[0-9]+]]
+; SR:	save 	$ra, $s0, $s1, $s2, [[FS:[0-9]+]]
 ; PE:	li	$[[T1:[0-9]+]], %hi(_gp_disp)
 ; PE: 	addiu	$[[T2:[0-9]+]], $pc, %lo(_gp_disp)
 ; PE:	sll	$[[T3:[0-9]+]], $[[T1]], 16
@@ -35,7 +35,7 @@ entry:
 ; C2:	move	$25, ${{[0-9]+}}
 ; C1:	move 	$gp, ${{[0-9]+}}
 ; C1:	jalrc 	${{[0-9]+}}
-; SR:	restore 	$ra, $s0, $s1, [[FS]]
+; SR:	restore 	$ra, $s0, $s1, $s2, [[FS]]
 ; PE:	li	$2, 0
 ; PE:	jrc 	$ra
 
diff --git a/test/CodeGen/Mips/hf16call32.ll b/test/CodeGen/Mips/hf16call32.ll
index 41249e1..934cf06 100644
--- a/test/CodeGen/Mips/hf16call32.ll
+++ b/test/CodeGen/Mips/hf16call32.ll
@@ -752,60 +752,62 @@ land.end289:                                      ; preds = %land.rhs286, %land.
 
 declare void @v_sf(float) #1
 ; stel: .section	.mips16.call.fp.v_sf,"ax",@progbits
-; stel:	.ent	__call_stub_v_sf
+; stel:	.ent	__call_stub_fp_v_sf
 ; stel:	mtc1 $4,$f12
 ; stel:	lui  $25,%hi(v_sf)
 ; stel:	addiu  $25,$25,%lo(v_sf)
 ; stel:	jr $25
-; stel:	.end	__call_stub_v_sf
+; stel:	.end	__call_stub_fp_v_sf
 
 declare i32 @printf(i8*, ...) #1
 
 declare void @v_df(double) #1
 ; stel: .section	.mips16.call.fp.v_df,"ax",@progbits
-; stel:	.ent	__call_stub_v_df
+; stel:	.ent	__call_stub_fp_v_df
+; stel: #APP
+; setl: .set reorder
 ; stel:	mtc1 $4,$f12
 ; stel:	mtc1 $5,$f13
 ; stel:	lui  $25,%hi(v_df)
 ; stel:	addiu  $25,$25,%lo(v_df)
 ; stel:	jr $25
-; stel:	.end	__call_stub_v_df
+; stel:	.end	__call_stub_fp_v_df
 
 declare void @v_sf_sf(float, float) #1
 ; stel: .section	.mips16.call.fp.v_sf_sf,"ax",@progbits
-; stel:	.ent	__call_stub_v_sf_sf
+; stel:	.ent	__call_stub_fp_v_sf_sf
 ; stel:	mtc1 $4,$f12
 ; stel:	mtc1 $5,$f14
 ; stel:	lui  $25,%hi(v_sf_sf)
 ; stel:	addiu  $25,$25,%lo(v_sf_sf)
 ; stel:	jr $25
-; stel:	.end	__call_stub_v_sf_sf
+; stel:	.end	__call_stub_fp_v_sf_sf
 
 declare void @v_sf_df(float, double) #1
 ; stel: .section	.mips16.call.fp.v_sf_df,"ax",@progbits
-; stel:	.ent	__call_stub_v_sf_df
+; stel:	.ent	__call_stub_fp_v_sf_df
 ; stel:	mtc1 $4,$f12
 ; stel:	mtc1 $6,$f14
 ; stel:	mtc1 $7,$f15
 ; stel:	lui  $25,%hi(v_sf_df)
 ; stel:	addiu  $25,$25,%lo(v_sf_df)
 ; stel:	jr $25
-; stel:	.end	__call_stub_v_sf_df
+; stel:	.end	__call_stub_fp_v_sf_df
 
 declare void @v_df_sf(double, float) #1
 ; stel: .section	.mips16.call.fp.v_df_sf,"ax",@progbits
-; stel:	.ent	__call_stub_v_df_sf
+; stel:	.ent	__call_stub_fp_v_df_sf
 ; stel:	mtc1 $4,$f12
 ; stel:	mtc1 $5,$f13
 ; stel:	mtc1 $6,$f14
 ; stel:	lui  $25,%hi(v_df_sf)
 ; stel:	addiu  $25,$25,%lo(v_df_sf)
 ; stel:	jr $25
-; stel:	.end	__call_stub_v_df_sf
+; stel:	.end	__call_stub_fp_v_df_sf
 
 declare void @v_df_df(double, double) #1
 ; stel: .section	.mips16.call.fp.v_df_df,"ax",@progbits
-; stel:	.ent	__call_stub_v_df_df
+; stel:	.ent	__call_stub_fp_v_df_df
 ; stel:	mtc1 $4,$f12
 ; stel:	mtc1 $5,$f13
 ; stel:	mtc1 $6,$f14
@@ -813,52 +815,52 @@ declare void @v_df_df(double, double) #1
 ; stel:	lui  $25,%hi(v_df_df)
 ; stel:	addiu  $25,$25,%lo(v_df_df)
 ; stel:	jr $25
-; stel:	.end	__call_stub_v_df_df
+; stel:	.end	__call_stub_fp_v_df_df
 
 declare float @sf_v() #1
 ; stel: .section	.mips16.call.fp.sf_v,"ax",@progbits
-; stel:	.ent	__call_stub_sf_v
+; stel:	.ent	__call_stub_fp_sf_v
 ; stel: move $18, $31
 ; stel: jal sf_v
 ; stel:	mfc1 $2,$f0
 ; stel:	jr $18
-; stel:	.end	__call_stub_sf_v
+; stel:	.end	__call_stub_fp_sf_v
 
 declare float @sf_sf(float) #1
 ; stel: .section	.mips16.call.fp.sf_sf,"ax",@progbits
-; stel:	.ent	__call_stub_sf_sf
+; stel:	.ent	__call_stub_fp_sf_sf
 ; stel: mtc1 $4,$f12
 ; stel: move $18, $31
 ; stel: jal sf_sf
 ; stel:	mfc1 $2,$f0
 ; stel:	jr $18
-; stel:	.end	__call_stub_sf_sf
+; stel:	.end	__call_stub_fp_sf_sf
 
 declare float @sf_df(double) #1
 ; stel: .section	.mips16.call.fp.sf_df,"ax",@progbits
-; stel:	.ent	__call_stub_sf_df
+; stel:	.ent	__call_stub_fp_sf_df
 ; stel: mtc1 $4,$f12
 ; stel: mtc1 $5,$f13
 ; stel: move $18, $31
 ; stel: jal sf_df
 ; stel:	mfc1 $2,$f0
 ; stel:	jr $18
-; stel:	.end	__call_stub_sf_df
+; stel:	.end	__call_stub_fp_sf_df
 
 declare float @sf_sf_sf(float, float) #1
 ; stel: .section	.mips16.call.fp.sf_sf_sf,"ax",@progbits
-; stel:	.ent	__call_stub_sf_sf_sf
+; stel:	.ent	__call_stub_fp_sf_sf_sf
 ; stel: mtc1 $4,$f12
 ; stel: mtc1 $5,$f14
 ; stel: move $18, $31
 ; stel: jal sf_sf_sf
 ; stel:	mfc1 $2,$f0
 ; stel:	jr $18
-; stel:	.end	__call_stub_sf_sf_sf
+; stel:	.end	__call_stub_fp_sf_sf_sf
 
 declare float @sf_sf_df(float, double) #1
 ; stel: .section	.mips16.call.fp.sf_sf_df,"ax",@progbits
-; stel:	.ent	__call_stub_sf_sf_df
+; stel:	.ent	__call_stub_fp_sf_sf_df
 ; stel: mtc1 $4,$f12
 ; stel: mtc1 $6,$f14
 ; stel: mtc1 $7,$f15
@@ -866,11 +868,11 @@ declare float @sf_sf_df(float, double) #1
 ; stel: jal sf_sf_df
 ; stel:	mfc1 $2,$f0
 ; stel:	jr $18
-; stel:	.end	__call_stub_sf_sf_df
+; stel:	.end	__call_stub_fp_sf_sf_df
 
 declare float @sf_df_sf(double, float) #1
 ; stel: .section	.mips16.call.fp.sf_df_sf,"ax",@progbits
-; stel:	.ent	__call_stub_sf_df_sf
+; stel:	.ent	__call_stub_fp_sf_df_sf
 ; stel: mtc1 $4,$f12
 ; stel: mtc1 $5,$f13
 ; stel: mtc1 $6,$f14
@@ -878,11 +880,11 @@ declare float @sf_df_sf(double, float) #1
 ; stel: jal sf_df_sf
 ; stel:	mfc1 $2,$f0
 ; stel:	jr $18
-; stel:	.end	__call_stub_sf_df_sf
+; stel:	.end	__call_stub_fp_sf_df_sf
 
 declare float @sf_df_df(double, double) #1
 ; stel: .section	.mips16.call.fp.sf_df_df,"ax",@progbits
-; stel:	.ent	__call_stub_sf_df_df
+; stel:	.ent	__call_stub_fp_sf_df_df
 ; stel: mtc1 $4,$f12
 ; stel: mtc1 $5,$f13
 ; stel: mtc1 $6,$f14
@@ -891,32 +893,32 @@ declare float @sf_df_df(double, double) #1
 ; stel: jal sf_df_df
 ; stel:	mfc1 $2,$f0
 ; stel:	jr $18
-; stel:	.end	__call_stub_sf_df_df
+; stel:	.end	__call_stub_fp_sf_df_df
 
 declare double @df_v() #1
 ; stel: .section	.mips16.call.fp.df_v,"ax",@progbits
-; stel:	.ent	__call_stub_df_v
+; stel:	.ent	__call_stub_fp_df_v
 ; stel: move $18, $31
 ; stel: jal df_v
 ; stel:	mfc1 $2,$f0
 ; stel:	mfc1 $3,$f1
 ; stel:	jr $18
-; stel:	.end	__call_stub_df_v
+; stel:	.end	__call_stub_fp_df_v
 
 declare double @df_sf(float) #1
 ; stel: .section	.mips16.call.fp.df_sf,"ax",@progbits
-; stel:	.ent	__call_stub_df_sf
+; stel:	.ent	__call_stub_fp_df_sf
 ; stel: mtc1 $4,$f12
 ; stel: move $18, $31
 ; stel: jal df_sf
 ; stel:	mfc1 $2,$f0
 ; stel:	mfc1 $3,$f1
 ; stel:	jr $18
-; stel:	.end	__call_stub_df_sf
+; stel:	.end	__call_stub_fp_df_sf
 
 declare double @df_df(double) #1
 ; stel: .section	.mips16.call.fp.df_df,"ax",@progbits
-; stel:	.ent	__call_stub_df_df
+; stel:	.ent	__call_stub_fp_df_df
 ; stel: mtc1 $4,$f12
 ; stel: mtc1 $5,$f13
 ; stel: move $18, $31
@@ -924,11 +926,11 @@ declare double @df_df(double) #1
 ; stel:	mfc1 $2,$f0
 ; stel:	mfc1 $3,$f1
 ; stel:	jr $18
-; stel:	.end	__call_stub_df_df
+; stel:	.end	__call_stub_fp_df_df
 
 declare double @df_sf_sf(float, float) #1
 ; stel: .section	.mips16.call.fp.df_sf_sf,"ax",@progbits
-; stel:	.ent	__call_stub_df_sf_sf
+; stel:	.ent	__call_stub_fp_df_sf_sf
 ; stel: mtc1 $4,$f12
 ; stel: mtc1 $5,$f14
 ; stel: move $18, $31
@@ -936,11 +938,11 @@ declare double @df_sf_sf(float, float) #1
 ; stel:	mfc1 $2,$f0
 ; stel:	mfc1 $3,$f1
 ; stel:	jr $18
-; stel:	.end	__call_stub_df_sf_sf
+; stel:	.end	__call_stub_fp_df_sf_sf
 
 declare double @df_sf_df(float, double) #1
 ; stel: .section	.mips16.call.fp.df_sf_df,"ax",@progbits
-; stel:	.ent	__call_stub_df_sf_df
+; stel:	.ent	__call_stub_fp_df_sf_df
 ; stel: mtc1 $4,$f12
 ; stel: mtc1 $6,$f14
 ; stel: mtc1 $7,$f15
@@ -949,11 +951,11 @@ declare double @df_sf_df(float, double) #1
 ; stel:	mfc1 $2,$f0
 ; stel:	mfc1 $3,$f1
 ; stel:	jr $18
-; stel:	.end	__call_stub_df_sf_df
+; stel:	.end	__call_stub_fp_df_sf_df
 
 declare double @df_df_sf(double, float) #1
 ; stel: .section	.mips16.call.fp.df_df_sf,"ax",@progbits
-; stel:	.ent	__call_stub_df_df_sf
+; stel:	.ent	__call_stub_fp_df_df_sf
 ; stel: mtc1 $4,$f12
 ; stel: mtc1 $5,$f13
 ; stel: mtc1 $6,$f14
@@ -962,11 +964,11 @@ declare double @df_df_sf(double, float) #1
 ; stel:	mfc1 $2,$f0
 ; stel:	mfc1 $3,$f1
 ; stel:	jr $18
-; stel:	.end	__call_stub_df_df_sf
+; stel:	.end	__call_stub_fp_df_df_sf
 
 declare double @df_df_df(double, double) #1
 ; stel: .section	.mips16.call.fp.df_df_df,"ax",@progbits
-; stel:	.ent	__call_stub_df_df_df
+; stel:	.ent	__call_stub_fp_df_df_df
 ; stel: mtc1 $4,$f12
 ; stel: mtc1 $5,$f13
 ; stel: mtc1 $6,$f14
@@ -976,32 +978,32 @@ declare double @df_df_df(double, double) #1
 ; stel:	mfc1 $2,$f0
 ; stel:	mfc1 $3,$f1
 ; stel:	jr $18
-; stel:	.end	__call_stub_df_df_df
+; stel:	.end	__call_stub_fp_df_df_df
 
 declare { float, float } @sc_v() #1
 ; stel: .section	.mips16.call.fp.sc_v,"ax",@progbits
-; stel:	.ent	__call_stub_sc_v
+; stel:	.ent	__call_stub_fp_sc_v
 ; stel: move $18, $31
 ; stel: jal sc_v
 ; stel:	mfc1 $2,$f0
 ; stel:	mfc1 $3,$f2
 ; stel:	jr $18
-; stel:	.end	__call_stub_sc_v
+; stel:	.end	__call_stub_fp_sc_v
 
 declare { float, float } @sc_sf(float) #1
 ; stel: .section	.mips16.call.fp.sc_sf,"ax",@progbits
-; stel:	.ent	__call_stub_sc_sf
+; stel:	.ent	__call_stub_fp_sc_sf
 ; stel: mtc1 $4,$f12
 ; stel: move $18, $31
 ; stel: jal sc_sf
 ; stel:	mfc1 $2,$f0
 ; stel:	mfc1 $3,$f2
 ; stel:	jr $18
-; stel:	.end	__call_stub_sc_sf
+; stel:	.end	__call_stub_fp_sc_sf
 
 declare { double, double } @dc_v() #1
 ; stel: .section	.mips16.call.fp.dc_v,"ax",@progbits
-; stel:	.ent	__call_stub_dc_v
+; stel:	.ent	__call_stub_fp_dc_v
 ; stel: move $18, $31
 ; stel: jal dc_v
 ; stel:	mfc1 $4,$f2
@@ -1009,11 +1011,11 @@ declare { double, double } @dc_v() #1
 ; stel:	mfc1 $2,$f0
 ; stel:	mfc1 $3,$f1
 ; stel:	jr $18
-; stel:	.end	__call_stub_dc_v
+; stel:	.end	__call_stub_fp_dc_v
 
 declare { double, double } @dc_sf(float) #1
 ; stel: .section	.mips16.call.fp.dc_sf,"ax",@progbits
-; stel:	.ent	__call_stub_dc_sf
+; stel:	.ent	__call_stub_fp_dc_sf
 ; stel: mtc1 $4,$f12
 ; stel: move $18, $31
 ; stel: jal dc_sf
@@ -1022,7 +1024,7 @@ declare { double, double } @dc_sf(float) #1
 ; stel:	mfc1 $2,$f0
 ; stel:	mfc1 $3,$f1
 ; stel:	jr $18
-; stel:	.end	__call_stub_dc_sf
+; stel:	.end	__call_stub_fp_dc_sf
 
 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/CodeGen/Mips/i64arg.ll b/test/CodeGen/Mips/i64arg.ll
index 704014c..0b16424 100644
--- a/test/CodeGen/Mips/i64arg.ll
+++ b/test/CodeGen/Mips/i64arg.ll
@@ -17,12 +17,12 @@ entry:
 ; CHECK: jalr $25
   tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind
   %sub = add nsw i32 %i, -1
-; CHECK: lw $25, %call16(ff3)
-; CHECK: sw $[[R1]], 28($sp)
-; CHECK: sw $[[R0]], 24($sp)
-; CHECK: move $6, $[[R2]]
-; CHECK: move $7, $[[R3]]
-; CHECK: jalr $25
+; CHECK-DAG: lw $25, %call16(ff3)
+; CHECK-DAG: sw $[[R1]], 28($sp)
+; CHECK-DAG: sw $[[R0]], 24($sp)
+; CHECK-DAG: move $6, $[[R2]]
+; CHECK-DAG: move $7, $[[R3]]
+; CHECK:     jalr $25
   tail call void @ff3(i32 %i, i64 %ll, i32 %sub, i64 %ll1) nounwind
   ret void
 }
diff --git a/test/CodeGen/Mips/inlineasm-operand-code.ll b/test/CodeGen/Mips/inlineasm-operand-code.ll
index 0197899..7bb4adc 100644
--- a/test/CodeGen/Mips/inlineasm-operand-code.ll
+++ b/test/CodeGen/Mips/inlineasm-operand-code.ll
@@ -10,7 +10,7 @@
 ; X with -3
 define i32 @constraint_X() nounwind {
 entry:
-;CHECK_LITTLE_32:   constraint_X:
+;CHECK_LITTLE_32-LABEL:   constraint_X:
 ;CHECK_LITTLE_32: #APP
 ;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd
 ;CHECK_LITTLE_32: #NO_APP
@@ -21,7 +21,7 @@ entry:
 ; x with -3
 define i32 @constraint_x() nounwind {
 entry:
-;CHECK_LITTLE_32:   constraint_x:
+;CHECK_LITTLE_32-LABEL:   constraint_x:
 ;CHECK_LITTLE_32: #APP
 ;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},0xfffd
 ;CHECK_LITTLE_32: #NO_APP
@@ -32,7 +32,7 @@ entry:
 ; d with -3
 define i32 @constraint_d() nounwind {
 entry:
-;CHECK_LITTLE_32:   constraint_d:
+;CHECK_LITTLE_32-LABEL:   constraint_d:
 ;CHECK_LITTLE_32:   #APP
 ;CHECK_LITTLE_32:   addi ${{[0-9]+}},${{[0-9]+}},-3
 ;CHECK_LITTLE_32:   #NO_APP
@@ -43,7 +43,7 @@ entry:
 ; m with -3
 define i32 @constraint_m() nounwind {
 entry:
-;CHECK_LITTLE_32:   constraint_m:
+;CHECK_LITTLE_32-LABEL:   constraint_m:
 ;CHECK_LITTLE_32:   #APP
 ;CHECK_LITTLE_32:   addi ${{[0-9]+}},${{[0-9]+}},-4
 ;CHECK_LITTLE_32:   #NO_APP
@@ -54,7 +54,7 @@ entry:
 ; z with -3
 define i32 @constraint_z() nounwind {
 entry:
-;CHECK_LITTLE_32: constraint_z:
+;CHECK_LITTLE_32-LABEL: constraint_z:
 ;CHECK_LITTLE_32:    #APP
 ;CHECK_LITTLE_32:    addi ${{[0-9]+}},${{[0-9]+}},-3
 ;CHECK_LITTLE_32:    #NO_APP
@@ -71,7 +71,7 @@ entry:
 ; a long long in 32 bit mode (use to assert)
 define i32 @constraint_longlong() nounwind {
 entry:
-;CHECK_LITTLE_32: constraint_longlong:
+;CHECK_LITTLE_32-LABEL: constraint_longlong:
 ;CHECK_LITTLE_32:    #APP
 ;CHECK_LITTLE_32:    addi ${{[0-9]+}},${{[0-9]+}},3
 ;CHECK_LITTLE_32:    #NO_APP
@@ -82,7 +82,7 @@ entry:
 ; D, in little endian the source reg will be 4 bytes into the long long
 define i32 @constraint_D() nounwind {
 entry:
-;CHECK_LITTLE_32: constraint_D:
+;CHECK_LITTLE_32-LABEL: constraint_D:
 ;CHECK_LITTLE_32:    lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_LITTLE_32:    lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_LITTLE_32:    lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -91,7 +91,7 @@ entry:
 ;CHECK_LITTLE_32:    #NO_APP
 
 ; D, in big endian the source reg will also be 4 bytes into the long long
-;CHECK_BIG_32:    constraint_D:
+;CHECK_BIG_32-LABEL:    constraint_D:
 ;CHECK_BIG_32:       lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_BIG_32:       lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_BIG_32:       lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -107,7 +107,7 @@ entry:
 ; L, in little endian the source reg will be 0 bytes into the long long
 define i32 @constraint_L() nounwind {
 entry:
-;CHECK_LITTLE_32: constraint_L:
+;CHECK_LITTLE_32-LABEL: constraint_L:
 ;CHECK_LITTLE_32:    lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_LITTLE_32:    lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_LITTLE_32:    lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -115,7 +115,7 @@ entry:
 ;CHECK_LITTLE_32:    or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
 ;CHECK_LITTLE_32:    #NO_APP
 ; L, in big endian the source reg will be 4 bytes into the long long
-;CHECK_BIG_32: constraint_L:
+;CHECK_BIG_32-LABEL: constraint_L:
 ;CHECK_BIG_32:       lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_BIG_32:       lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_BIG_32:       lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -131,7 +131,7 @@ entry:
 ; M, in little endian the source reg will be 4 bytes into the long long
 define i32 @constraint_M() nounwind {
 entry:
-;CHECK_LITTLE_32: constraint_M:
+;CHECK_LITTLE_32-LABEL: constraint_M:
 ;CHECK_LITTLE_32:    lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_LITTLE_32:    lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_LITTLE_32:    lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
@@ -139,7 +139,7 @@ entry:
 ;CHECK_LITTLE_32:    or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
 ;CHECK_LITTLE_32:    #NO_APP
 ; M, in big endian the source reg will be 0 bytes into the long long
-;CHECK_BIG_32:    constraint_M:
+;CHECK_BIG_32-LABEL:    constraint_M:
 ;CHECK_BIG_32:       lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
 ;CHECK_BIG_32:       lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
 ;CHECK_BIG_32:       lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
diff --git a/test/CodeGen/Mips/int-to-float-conversion.ll b/test/CodeGen/Mips/int-to-float-conversion.ll
index 2a7dfdd..c2baf44 100644
--- a/test/CodeGen/Mips/int-to-float-conversion.ll
+++ b/test/CodeGen/Mips/int-to-float-conversion.ll
@@ -4,7 +4,7 @@
 @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
 @i3 = common global i32* null, align 4
 
-; 32: test_float_int_:
+; 32-LABEL: test_float_int_:
 ; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
 ; 32: cvt.s.w $f{{[0-9]+}}, $f[[R0]]
 
@@ -14,10 +14,10 @@ entry:
   ret float %conv
 }
 
-; 32: test_double_int_:
+; 32-LABEL: test_double_int_:
 ; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
 ; 32: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
-; 64: test_double_int_:
+; 64-LABEL: test_double_int_:
 ; 64: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
 ; 64: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
 
@@ -27,7 +27,7 @@ entry:
   ret double %conv
 }
 
-; 64: test_float_LL_:
+; 64-LABEL: test_float_LL_:
 ; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
 ; 64: cvt.s.l $f{{[0-9]+}}, $f[[R0]]
 
@@ -37,7 +37,7 @@ entry:
   ret float %conv
 }
 
-; 64: test_double_LL_:
+; 64-LABEL: test_double_LL_:
 ; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
 ; 64: cvt.d.l $f{{[0-9]+}}, $f[[R0]]
 
diff --git a/test/CodeGen/Mips/largefr1.ll b/test/CodeGen/Mips/largefr1.ll
index 0fe89f7..9a5fd08 100644
--- a/test/CodeGen/Mips/largefr1.ll
+++ b/test/CodeGen/Mips/largefr1.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -march=mipsel -mcpu=mips16 -mips16-hard-float -soft-float -relocation-model=static < %s | FileCheck %s -check-prefix=1
 
+
 @i = common global i32 0, align 4
 @j = common global i32 0, align 4
 @.str = private unnamed_addr constant [8 x i8] c"%i %i \0A\00", align 1
@@ -22,22 +23,34 @@ entry:
 
 define i32 @main() nounwind {
 entry:
-; 1: main: 
-; 1: 1: 	.word	-797992
-; 1:            li ${{[0-9]+}}, 12
-; 1:            sll ${{[0-9]+}}, ${{[0-9]+}}, 16
+; 1-LABEL: main:
+; 1: 1: 	.word	-798000
+; 1:            lw ${{[0-9]+}}, 1f
+; 1:            b 2f
+; 1:            .align 2
+; 1:            .word	800020
+
+; 1:            b 2f
+; 1:            .align 2
+; 1:            .word	400020
+
+; 1:            move ${{[0-9]+}}, $sp
 ; 1:            addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
-; 2:            move $sp, ${{[0-9]+}}
-; 2:            addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
-; 1:            li ${{[0-9]+}}, 6
-; 1:            sll ${{[0-9]+}}, ${{[0-9]+}}, 16
+; 1:            addiu ${{[0-9]+}}, ${{[0-9]+}}, 0
+
+
+
+; 1:            b 2f
+; 1:            .align 2
+; 1:            .word	400220
+
+; 1:            move ${{[0-9]+}}, $sp
 ; 1:            addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
-; 2:            move $sp, ${{[0-9]+}}
-; 2:            addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
-; 1:          	addiu	${{[0-9]+}}, ${{[0-9]+}}, 6800
-; 1: 	        li	${{[0-9]+}}, 1
-; 1:	        sll	${{[0-9]+}}, ${{[0-9]+}}, 16
-; 2: 	        li	${{[0-9]+}}, 34463
+; 1:           	lw	${{[0-9]+}}, 0(${{[0-9]+}})
+
+
+
+
   %retval = alloca i32, align 4
   %one = alloca [100000 x i32], align 4
   %two = alloca [100000 x i32], align 4
diff --git a/test/CodeGen/Mips/mips16_fpret.ll b/test/CodeGen/Mips/mips16_fpret.ll
index 9113329..c132f63 100644
--- a/test/CodeGen/Mips/mips16_fpret.ll
+++ b/test/CodeGen/Mips/mips16_fpret.ll
@@ -62,10 +62,10 @@ entry:
   %0 = load { double, double }* %retval
   ret { double, double } %0
 ; 1: 	.ent	foodcx
-; 1: 	lw	$2, %lo(dcx)(${{[0-9]+}})
+; 1: 	lw	${{[0-9]}}, %lo(dcx)(${{[0-9]+}})
 ; 1:	jal	__mips16_ret_dc
 ; 2: 	.ent	foodcx
-; 2:	lw	$3, 4(${{[0-9]+}})
+; 2:	lw	${{[0-9]}}, 4(${{[0-9]+}})
 ; 2:	jal	__mips16_ret_dc
 ; 3: 	.ent	foodcx
 ; 3:	lw	$4, 8(${{[0-9]+}})
@@ -74,4 +74,3 @@ entry:
 ; 4:	lw	$5, 12(${{[0-9]+}})
 ; 4:	jal	__mips16_ret_dc
 }
-
diff --git a/test/CodeGen/Mips/mips16fpe.ll b/test/CodeGen/Mips/mips16fpe.ll
index 4335436..10c5163 100644
--- a/test/CodeGen/Mips/mips16fpe.ll
+++ b/test/CodeGen/Mips/mips16fpe.ll
@@ -41,7 +41,7 @@
 
 define void @test_addsf3() nounwind {
 entry:
-;16hf: test_addsf3:
+;16hf-LABEL: test_addsf3:
   %0 = load float* @x, align 4
   %1 = load float* @y, align 4
   %add = fadd float %0, %1
@@ -52,7 +52,7 @@ entry:
 
 define void @test_adddf3() nounwind {
 entry:
-;16hf: test_adddf3:
+;16hf-LABEL: test_adddf3:
   %0 = load double* @xd, align 8
   %1 = load double* @yd, align 8
   %add = fadd double %0, %1
@@ -63,7 +63,7 @@ entry:
 
 define void @test_subsf3() nounwind {
 entry:
-;16hf: test_subsf3:
+;16hf-LABEL: test_subsf3:
   %0 = load float* @x, align 4
   %1 = load float* @y, align 4
   %sub = fsub float %0, %1
@@ -74,7 +74,7 @@ entry:
 
 define void @test_subdf3() nounwind {
 entry:
-;16hf: test_subdf3:
+;16hf-LABEL: test_subdf3:
   %0 = load double* @xd, align 8
   %1 = load double* @yd, align 8
   %sub = fsub double %0, %1
@@ -85,7 +85,7 @@ entry:
 
 define void @test_mulsf3() nounwind {
 entry:
-;16hf: test_mulsf3:
+;16hf-LABEL: test_mulsf3:
   %0 = load float* @x, align 4
   %1 = load float* @y, align 4
   %mul = fmul float %0, %1
@@ -96,7 +96,7 @@ entry:
 
 define void @test_muldf3() nounwind {
 entry:
-;16hf: test_muldf3:
+;16hf-LABEL: test_muldf3:
   %0 = load double* @xd, align 8
   %1 = load double* @yd, align 8
   %mul = fmul double %0, %1
@@ -107,7 +107,7 @@ entry:
 
 define void @test_divsf3() nounwind {
 entry:
-;16hf: test_divsf3:
+;16hf-LABEL: test_divsf3:
   %0 = load float* @y, align 4
   %1 = load float* @x, align 4
   %div = fdiv float %0, %1
@@ -118,7 +118,7 @@ entry:
 
 define void @test_divdf3() nounwind {
 entry:
-;16hf: test_divdf3:
+;16hf-LABEL: test_divdf3:
   %0 = load double* @yd, align 8
   %mul = fmul double %0, 2.000000e+00
   %1 = load double* @xd, align 8
@@ -130,7 +130,7 @@ entry:
 
 define void @test_extendsfdf2() nounwind {
 entry:
-;16hf: test_extendsfdf2:
+;16hf-LABEL: test_extendsfdf2:
   %0 = load float* @x, align 4
   %conv = fpext float %0 to double
   store double %conv, double* @extendsfdf2_result, align 8
@@ -140,7 +140,7 @@ entry:
 
 define void @test_truncdfsf2() nounwind {
 entry:
-;16hf: test_truncdfsf2:
+;16hf-LABEL: test_truncdfsf2:
   %0 = load double* @xd2, align 8
   %conv = fptrunc double %0 to float
   store float %conv, float* @truncdfsf2_result, align 4
@@ -150,7 +150,7 @@ entry:
 
 define void @test_fix_truncsfsi() nounwind {
 entry:
-;16hf: test_fix_truncsfsi:
+;16hf-LABEL: test_fix_truncsfsi:
   %0 = load float* @x, align 4
   %conv = fptosi float %0 to i32
   store i32 %conv, i32* @fix_truncsfsi_result, align 4
@@ -160,7 +160,7 @@ entry:
 
 define void @test_fix_truncdfsi() nounwind {
 entry:
-;16hf: test_fix_truncdfsi:
+;16hf-LABEL: test_fix_truncdfsi:
   %0 = load double* @xd, align 8
   %conv = fptosi double %0 to i32
   store i32 %conv, i32* @fix_truncdfsi_result, align 4
@@ -170,7 +170,7 @@ entry:
 
 define void @test_floatsisf() nounwind {
 entry:
-;16hf: test_floatsisf:
+;16hf-LABEL: test_floatsisf:
   %0 = load i32* @si, align 4
   %conv = sitofp i32 %0 to float
   store float %conv, float* @floatsisf_result, align 4
@@ -180,7 +180,7 @@ entry:
 
 define void @test_floatsidf() nounwind {
 entry:
-;16hf: test_floatsidf:
+;16hf-LABEL: test_floatsidf:
   %0 = load i32* @si, align 4
   %conv = sitofp i32 %0 to double
   store double %conv, double* @floatsidf_result, align 8
@@ -190,7 +190,7 @@ entry:
 
 define void @test_floatunsisf() nounwind {
 entry:
-;16hf: test_floatunsisf:
+;16hf-LABEL: test_floatunsisf:
   %0 = load i32* @ui, align 4
   %conv = uitofp i32 %0 to float
   store float %conv, float* @floatunsisf_result, align 4
@@ -200,7 +200,7 @@ entry:
 
 define void @test_floatunsidf() nounwind {
 entry:
-;16hf: test_floatunsidf:
+;16hf-LABEL: test_floatunsidf:
   %0 = load i32* @ui, align 4
   %conv = uitofp i32 %0 to double
   store double %conv, double* @floatunsidf_result, align 8
@@ -210,7 +210,7 @@ entry:
 
 define void @test_eqsf2() nounwind {
 entry:
-;16hf: test_eqsf2:
+;16hf-LABEL: test_eqsf2:
   %0 = load float* @x, align 4
   %1 = load float* @xx, align 4
   %cmp = fcmp oeq float %0, %1
@@ -222,7 +222,7 @@ entry:
 
 define void @test_eqdf2() nounwind {
 entry:
-;16hf: test_eqdf2:
+;16hf-LABEL: test_eqdf2:
   %0 = load double* @xd, align 8
   %1 = load double* @xxd, align 8
   %cmp = fcmp oeq double %0, %1
@@ -234,7 +234,7 @@ entry:
 
 define void @test_nesf2() nounwind {
 entry:
-;16hf: test_nesf2:
+;16hf-LABEL: test_nesf2:
   %0 = load float* @x, align 4
   %1 = load float* @y, align 4
   %cmp = fcmp une float %0, %1
@@ -246,7 +246,7 @@ entry:
 
 define void @test_nedf2() nounwind {
 entry:
-;16hf: test_nedf2:
+;16hf-LABEL: test_nedf2:
   %0 = load double* @xd, align 8
   %1 = load double* @yd, align 8
   %cmp = fcmp une double %0, %1
@@ -258,7 +258,7 @@ entry:
 
 define void @test_gesf2() nounwind {
 entry:
-;16hf: test_gesf2:
+;16hf-LABEL: test_gesf2:
   %0 = load float* @x, align 4
   %1 = load float* @xx, align 4
   %cmp = fcmp oge float %0, %1
@@ -273,7 +273,7 @@ entry:
 
 define void @test_gedf2() nounwind {
 entry:
-;16hf: test_gedf2:
+;16hf-LABEL: test_gedf2:
   %0 = load double* @xd, align 8
   %1 = load double* @xxd, align 8
   %cmp = fcmp oge double %0, %1
@@ -288,7 +288,7 @@ entry:
 
 define void @test_ltsf2() nounwind {
 entry:
-;16hf: test_ltsf2:
+;16hf-LABEL: test_ltsf2:
   %0 = load float* @x, align 4
   %1 = load float* @xx, align 4
   %lnot = fcmp uge float %0, %1
@@ -304,7 +304,7 @@ entry:
 
 define void @test_ltdf2() nounwind {
 entry:
-;16hf: test_ltdf2:
+;16hf-LABEL: test_ltdf2:
   %0 = load double* @xd, align 8
   %1 = load double* @xxd, align 8
   %lnot = fcmp uge double %0, %1
@@ -320,7 +320,7 @@ entry:
 
 define void @test_lesf2() nounwind {
 entry:
-;16hf: test_lesf2:
+;16hf-LABEL: test_lesf2:
   %0 = load float* @x, align 4
   %1 = load float* @xx, align 4
   %cmp = fcmp ole float %0, %1
@@ -335,7 +335,7 @@ entry:
 
 define void @test_ledf2() nounwind {
 entry:
-;16hf: test_ledf2:
+;16hf-LABEL: test_ledf2:
   %0 = load double* @xd, align 8
   %1 = load double* @xxd, align 8
   %cmp = fcmp ole double %0, %1
@@ -350,7 +350,7 @@ entry:
 
 define void @test_gtsf2() nounwind {
 entry:
-;16hf: test_gtsf2:
+;16hf-LABEL: test_gtsf2:
   %0 = load float* @x, align 4
   %1 = load float* @xx, align 4
   %lnot = fcmp ule float %0, %1
@@ -365,7 +365,7 @@ entry:
 
 define void @test_gtdf2() nounwind {
 entry:
-;16hf: test_gtdf2:
+;16hf-LABEL: test_gtdf2:
   %0 = load double* @xd, align 8
   %1 = load double* @xxd, align 8
   %lnot = fcmp ule double %0, %1
diff --git a/test/CodeGen/Mips/mips64-f128.ll b/test/CodeGen/Mips/mips64-f128.ll
index 5892cab..dc8bbfd 100644
--- a/test/CodeGen/Mips/mips64-f128.ll
+++ b/test/CodeGen/Mips/mips64-f128.ll
@@ -7,7 +7,7 @@
 @gf1 = external global float
 @gd1 = external global double
 
-; CHECK: addLD:
+; CHECK-LABEL: addLD:
 ; CHECK: ld $25, %call16(__addtf3)
 
 define fp128 @addLD() {
@@ -18,7 +18,7 @@ entry:
   ret fp128 %add
 }
 
-; CHECK: subLD:
+; CHECK-LABEL: subLD:
 ; CHECK: ld $25, %call16(__subtf3)
 
 define fp128 @subLD() {
@@ -29,7 +29,7 @@ entry:
   ret fp128 %sub
 }
 
-; CHECK: mulLD:
+; CHECK-LABEL: mulLD:
 ; CHECK: ld $25, %call16(__multf3)
 
 define fp128 @mulLD() {
@@ -40,7 +40,7 @@ entry:
   ret fp128 %mul
 }
 
-; CHECK: divLD:
+; CHECK-LABEL: divLD:
 ; CHECK: ld $25, %call16(__divtf3)
 
 define fp128 @divLD() {
@@ -51,7 +51,7 @@ entry:
   ret fp128 %div
 }
 
-; CHECK: conv_LD_char:
+; CHECK-LABEL: conv_LD_char:
 ; CHECK: ld $25, %call16(__floatsitf)
 
 define fp128 @conv_LD_char(i8 signext %a) {
@@ -60,7 +60,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_short:
+; CHECK-LABEL: conv_LD_short:
 ; CHECK: ld $25, %call16(__floatsitf)
 
 define fp128 @conv_LD_short(i16 signext %a) {
@@ -69,7 +69,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_int:
+; CHECK-LABEL: conv_LD_int:
 ; CHECK: ld $25, %call16(__floatsitf)
 
 define fp128 @conv_LD_int(i32 %a) {
@@ -78,7 +78,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_LL:
+; CHECK-LABEL: conv_LD_LL:
 ; CHECK: ld $25, %call16(__floatditf)
 
 define fp128 @conv_LD_LL(i64 %a) {
@@ -87,7 +87,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_UChar:
+; CHECK-LABEL: conv_LD_UChar:
 ; CHECK: ld $25, %call16(__floatunsitf)
 
 define fp128 @conv_LD_UChar(i8 zeroext %a) {
@@ -96,7 +96,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_UShort:
+; CHECK-LABEL: conv_LD_UShort:
 ; CHECK: ld $25, %call16(__floatunsitf)
 
 define fp128 @conv_LD_UShort(i16 zeroext %a) {
@@ -105,7 +105,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_UInt:
+; CHECK-LABEL: conv_LD_UInt:
 ; CHECK: ld $25, %call16(__floatunsitf)
 
 define fp128 @conv_LD_UInt(i32 %a) {
@@ -114,7 +114,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_ULL:
+; CHECK-LABEL: conv_LD_ULL:
 ; CHECK: ld $25, %call16(__floatunditf)
 
 define fp128 @conv_LD_ULL(i64 %a) {
@@ -123,7 +123,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_char_LD:
+; CHECK-LABEL: conv_char_LD:
 ; CHECK: ld $25, %call16(__fixtfsi)
 
 define signext i8 @conv_char_LD(fp128 %a) {
@@ -132,7 +132,7 @@ entry:
   ret i8 %conv
 }
 
-; CHECK: conv_short_LD:
+; CHECK-LABEL: conv_short_LD:
 ; CHECK: ld $25, %call16(__fixtfsi)
 
 define signext i16 @conv_short_LD(fp128 %a) {
@@ -141,7 +141,7 @@ entry:
   ret i16 %conv
 }
 
-; CHECK: conv_int_LD:
+; CHECK-LABEL: conv_int_LD:
 ; CHECK: ld $25, %call16(__fixtfsi)
 
 define i32 @conv_int_LD(fp128 %a) {
@@ -150,7 +150,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: conv_LL_LD:
+; CHECK-LABEL: conv_LL_LD:
 ; CHECK: ld $25, %call16(__fixtfdi)
 
 define i64 @conv_LL_LD(fp128 %a) {
@@ -159,7 +159,7 @@ entry:
   ret i64 %conv
 }
 
-; CHECK: conv_UChar_LD:
+; CHECK-LABEL: conv_UChar_LD:
 ; CHECK: ld $25, %call16(__fixtfsi)
 
 define zeroext i8 @conv_UChar_LD(fp128 %a) {
@@ -168,7 +168,7 @@ entry:
   ret i8 %conv
 }
 
-; CHECK: conv_UShort_LD:
+; CHECK-LABEL: conv_UShort_LD:
 ; CHECK: ld $25, %call16(__fixtfsi)
 
 define zeroext i16 @conv_UShort_LD(fp128 %a) {
@@ -177,7 +177,7 @@ entry:
   ret i16 %conv
 }
 
-; CHECK: conv_UInt_LD:
+; CHECK-LABEL: conv_UInt_LD:
 ; CHECK: ld $25, %call16(__fixunstfsi)
 
 define i32 @conv_UInt_LD(fp128 %a) {
@@ -186,7 +186,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: conv_ULL_LD:
+; CHECK-LABEL: conv_ULL_LD:
 ; CHECK: ld $25, %call16(__fixunstfdi)
 
 define i64 @conv_ULL_LD(fp128 %a) {
@@ -195,7 +195,7 @@ entry:
   ret i64 %conv
 }
 
-; CHECK: conv_LD_float:
+; CHECK-LABEL: conv_LD_float:
 ; CHECK: ld $25, %call16(__extendsftf2)
 
 define fp128 @conv_LD_float(float %a) {
@@ -204,7 +204,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_LD_double:
+; CHECK-LABEL: conv_LD_double:
 ; CHECK: ld $25, %call16(__extenddftf2)
 
 define fp128 @conv_LD_double(double %a) {
@@ -213,7 +213,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: conv_float_LD:
+; CHECK-LABEL: conv_float_LD:
 ; CHECK: ld $25, %call16(__trunctfsf2)
 
 define float @conv_float_LD(fp128 %a) {
@@ -222,7 +222,7 @@ entry:
   ret float %conv
 }
 
-; CHECK: conv_double_LD:
+; CHECK-LABEL: conv_double_LD:
 ; CHECK: ld $25, %call16(__trunctfdf2)
 
 define double @conv_double_LD(fp128 %a) {
@@ -231,13 +231,13 @@ entry:
   ret double %conv
 }
 
-; CHECK: libcall1_fabsl:
-; CHECK: ld      $[[R0:[0-9]+]], 8($[[R4:[0-9]+]])
-; CHECK: daddiu  $[[R1:[0-9]+]], $zero, 1
-; CHECK: dsll    $[[R2:[0-9]+]], $[[R1]], 63
-; CHECK: daddiu  $[[R3:[0-9]+]], $[[R2]], -1
-; CHECK: and     $4, $[[R0]], $[[R3]]
-; CHECK: ld      $2, 0($[[R4]])
+; CHECK-LABEL:             libcall1_fabsl:
+; CHECK-DAG: ld      $[[R0:[0-9]+]], 8($[[R4:[0-9]+]])
+; CHECK-DAG: daddiu  $[[R1:[0-9]+]], $zero, 1
+; CHECK-DAG: dsll    $[[R2:[0-9]+]], $[[R1]], 63
+; CHECK-DAG: daddiu  $[[R3:[0-9]+]], $[[R2]], -1
+; CHECK-DAG: and     $4, $[[R0]], $[[R3]]
+; CHECK-DAG: ld      $2, 0($[[R4]])
 
 define fp128 @libcall1_fabsl() {
 entry:
@@ -248,7 +248,7 @@ entry:
 
 declare fp128 @fabsl(fp128) #1
 
-; CHECK: libcall1_ceill:
+; CHECK-LABEL: libcall1_ceill:
 ; CHECK: ld $25, %call16(ceill)
 
 define fp128 @libcall1_ceill() {
@@ -260,7 +260,7 @@ entry:
 
 declare fp128 @ceill(fp128) #1
 
-; CHECK: libcall1_sinl:
+; CHECK-LABEL: libcall1_sinl:
 ; CHECK: ld $25, %call16(sinl)
 
 define fp128 @libcall1_sinl() {
@@ -272,7 +272,7 @@ entry:
 
 declare fp128 @sinl(fp128) #2
 
-; CHECK: libcall1_cosl:
+; CHECK-LABEL: libcall1_cosl:
 ; CHECK: ld $25, %call16(cosl)
 
 define fp128 @libcall1_cosl() {
@@ -284,7 +284,7 @@ entry:
 
 declare fp128 @cosl(fp128) #2
 
-; CHECK: libcall1_expl:
+; CHECK-LABEL: libcall1_expl:
 ; CHECK: ld $25, %call16(expl)
 
 define fp128 @libcall1_expl() {
@@ -296,7 +296,7 @@ entry:
 
 declare fp128 @expl(fp128) #2
 
-; CHECK: libcall1_exp2l:
+; CHECK-LABEL: libcall1_exp2l:
 ; CHECK: ld $25, %call16(exp2l)
 
 define fp128 @libcall1_exp2l() {
@@ -308,7 +308,7 @@ entry:
 
 declare fp128 @exp2l(fp128) #2
 
-; CHECK: libcall1_logl:
+; CHECK-LABEL: libcall1_logl:
 ; CHECK: ld $25, %call16(logl)
 
 define fp128 @libcall1_logl() {
@@ -320,7 +320,7 @@ entry:
 
 declare fp128 @logl(fp128) #2
 
-; CHECK: libcall1_log2l:
+; CHECK-LABEL: libcall1_log2l:
 ; CHECK: ld $25, %call16(log2l)
 
 define fp128 @libcall1_log2l() {
@@ -332,7 +332,7 @@ entry:
 
 declare fp128 @log2l(fp128) #2
 
-; CHECK: libcall1_log10l:
+; CHECK-LABEL: libcall1_log10l:
 ; CHECK: ld $25, %call16(log10l)
 
 define fp128 @libcall1_log10l() {
@@ -344,7 +344,7 @@ entry:
 
 declare fp128 @log10l(fp128) #2
 
-; CHECK: libcall1_nearbyintl:
+; CHECK-LABEL: libcall1_nearbyintl:
 ; CHECK: ld $25, %call16(nearbyintl)
 
 define fp128 @libcall1_nearbyintl() {
@@ -356,7 +356,7 @@ entry:
 
 declare fp128 @nearbyintl(fp128) #1
 
-; CHECK: libcall1_floorl:
+; CHECK-LABEL: libcall1_floorl:
 ; CHECK: ld $25, %call16(floorl)
 
 define fp128 @libcall1_floorl() {
@@ -368,7 +368,7 @@ entry:
 
 declare fp128 @floorl(fp128) #1
 
-; CHECK: libcall1_sqrtl:
+; CHECK-LABEL: libcall1_sqrtl:
 ; CHECK: ld $25, %call16(sqrtl)
 
 define fp128 @libcall1_sqrtl() {
@@ -380,7 +380,7 @@ entry:
 
 declare fp128 @sqrtl(fp128) #2
 
-; CHECK: libcall1_rintl:
+; CHECK-LABEL: libcall1_rintl:
 ; CHECK: ld $25, %call16(rintl)
 
 define fp128 @libcall1_rintl() {
@@ -392,7 +392,7 @@ entry:
 
 declare fp128 @rintl(fp128) #1
 
-; CHECK: libcall_powil:
+; CHECK-LABEL: libcall_powil:
 ; CHECK: ld $25, %call16(__powitf2)
 
 define fp128 @libcall_powil(fp128 %a, i32 %b) {
@@ -403,18 +403,18 @@ entry:
 
 declare fp128 @llvm.powi.f128(fp128, i32) #3
 
-; CHECK: libcall2_copysignl:
-; CHECK: daddiu $[[R2:[0-9]+]], $zero, 1
-; CHECK: dsll   $[[R3:[0-9]+]], $[[R2]], 63
-; CHECK: ld     $[[R0:[0-9]+]], %got_disp(gld1)
-; CHECK: ld     $[[R1:[0-9]+]], 8($[[R0]])
-; CHECK: and    $[[R4:[0-9]+]], $[[R1]], $[[R3]]
-; CHECK: ld     $[[R5:[0-9]+]], %got_disp(gld0)
-; CHECK: ld     $[[R6:[0-9]+]], 8($[[R5]])
-; CHECK: daddiu $[[R7:[0-9]+]], $[[R3]], -1
-; CHECK: and    $[[R8:[0-9]+]], $[[R6]], $[[R7]]
-; CHECK: or     $4, $[[R8]], $[[R4]]
-; CHECK: ld     $2, 0($[[R5]])
+; CHECK-LABEL:     libcall2_copysignl:
+; CHECK-DAG: daddiu $[[R2:[0-9]+]], $zero, 1
+; CHECK-DAG: dsll   $[[R3:[0-9]+]], $[[R2]], 63
+; CHECK-DAG: ld     $[[R0:[0-9]+]], %got_disp(gld1)
+; CHECK-DAG: ld     $[[R1:[0-9]+]], 8($[[R0]])
+; CHECK-DAG: and    $[[R4:[0-9]+]], $[[R1]], $[[R3]]
+; CHECK-DAG: ld     $[[R5:[0-9]+]], %got_disp(gld0)
+; CHECK-DAG: ld     $[[R6:[0-9]+]], 8($[[R5]])
+; CHECK-DAG: daddiu $[[R7:[0-9]+]], $[[R3]], -1
+; CHECK-DAG: and    $[[R8:[0-9]+]], $[[R6]], $[[R7]]
+; CHECK-DAG: or     $4, $[[R8]], $[[R4]]
+; CHECK-DAG: ld     $2, 0($[[R5]])
 
 define fp128 @libcall2_copysignl() {
 entry:
@@ -426,7 +426,7 @@ entry:
 
 declare fp128 @copysignl(fp128, fp128) #1
 
-; CHECK: libcall2_powl:
+; CHECK-LABEL: libcall2_powl:
 ; CHECK: ld $25, %call16(powl)
 
 define fp128 @libcall2_powl() {
@@ -439,7 +439,7 @@ entry:
 
 declare fp128 @powl(fp128, fp128) #2
 
-; CHECK: libcall2_fmodl:
+; CHECK-LABEL: libcall2_fmodl:
 ; CHECK: ld $25, %call16(fmodl)
 
 define fp128 @libcall2_fmodl() {
@@ -452,7 +452,7 @@ entry:
 
 declare fp128 @fmodl(fp128, fp128) #2
 
-; CHECK: libcall3_fmal:
+; CHECK-LABEL: libcall3_fmal:
 ; CHECK: ld $25, %call16(fmal)
 
 define fp128 @libcall3_fmal() {
@@ -466,7 +466,7 @@ entry:
 
 declare fp128 @llvm.fma.f128(fp128, fp128, fp128) #4
 
-; CHECK: cmp_lt:
+; CHECK-LABEL: cmp_lt:
 ; CHECK: ld $25, %call16(__lttf2)
 
 define i32 @cmp_lt(fp128 %a, fp128 %b) {
@@ -476,7 +476,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: cmp_le:
+; CHECK-LABEL: cmp_le:
 ; CHECK: ld $25, %call16(__letf2)
 
 define i32 @cmp_le(fp128 %a, fp128 %b) {
@@ -486,7 +486,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: cmp_gt:
+; CHECK-LABEL: cmp_gt:
 ; CHECK: ld $25, %call16(__gttf2)
 
 define i32 @cmp_gt(fp128 %a, fp128 %b) {
@@ -496,7 +496,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: cmp_ge:
+; CHECK-LABEL: cmp_ge:
 ; CHECK: ld $25, %call16(__getf2)
 
 define i32 @cmp_ge(fp128 %a, fp128 %b) {
@@ -506,7 +506,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: cmp_eq:
+; CHECK-LABEL: cmp_eq:
 ; CHECK: ld $25, %call16(__eqtf2)
 
 define i32 @cmp_eq(fp128 %a, fp128 %b) {
@@ -516,7 +516,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: cmp_ne:
+; CHECK-LABEL: cmp_ne:
 ; CHECK: ld $25, %call16(__netf2)
 
 define i32 @cmp_ne(fp128 %a, fp128 %b) {
@@ -526,7 +526,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: load_LD_LD:
+; CHECK-LABEL: load_LD_LD:
 ; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1)
 ; CHECK: ld $2, 0($[[R0]])
 ; CHECK: ld $4, 8($[[R0]])
@@ -537,7 +537,7 @@ entry:
   ret fp128 %0
 }
 
-; CHECK: load_LD_float:
+; CHECK-LABEL: load_LD_float:
 ; CHECK: ld   $[[R0:[0-9]+]], %got_disp(gf1)
 ; CHECK: lw   $4, 0($[[R0]])
 ; CHECK: ld   $25, %call16(__extendsftf2)
@@ -550,7 +550,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: load_LD_double:
+; CHECK-LABEL: load_LD_double:
 ; CHECK: ld   $[[R0:[0-9]+]], %got_disp(gd1)
 ; CHECK: ld   $4, 0($[[R0]])
 ; CHECK: ld   $25, %call16(__extenddftf2)
@@ -563,7 +563,7 @@ entry:
   ret fp128 %conv
 }
 
-; CHECK: store_LD_LD:
+; CHECK-LABEL: store_LD_LD:
 ; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1)
 ; CHECK: ld $[[R1:[0-9]+]], 0($[[R0]])
 ; CHECK: ld $[[R2:[0-9]+]], 8($[[R0]])
@@ -578,7 +578,7 @@ entry:
   ret void
 }
 
-; CHECK: store_LD_float:
+; CHECK-LABEL: store_LD_float:
 ; CHECK: ld   $[[R0:[0-9]+]], %got_disp(gld1)
 ; CHECK: ld   $4, 0($[[R0]])
 ; CHECK: ld   $5, 8($[[R0]])
@@ -595,7 +595,7 @@ entry:
   ret void
 }
 
-; CHECK: store_LD_double:
+; CHECK-LABEL: store_LD_double:
 ; CHECK: ld   $[[R0:[0-9]+]], %got_disp(gld1)
 ; CHECK: ld   $4, 0($[[R0]])
 ; CHECK: ld   $5, 8($[[R0]])
@@ -612,7 +612,7 @@ entry:
   ret void
 }
 
-; CHECK: select_LD:
+; CHECK-LABEL: select_LD:
 ; CHECK: movn $8, $6, $4
 ; CHECK: movn $9, $7, $4
 ; CHECK: move $2, $8
@@ -625,7 +625,7 @@ entry:
   ret fp128 %cond
 }
 
-; CHECK: selectCC_LD:
+; CHECK-LABEL: selectCC_LD:
 ; CHECK: move $[[R0:[0-9]+]], $11
 ; CHECK: move $[[R1:[0-9]+]], $10
 ; CHECK: move $[[R2:[0-9]+]], $9
diff --git a/test/CodeGen/Mips/mips64-libcall.ll b/test/CodeGen/Mips/mips64-libcall.ll
index d54598b..290baaf 100644
--- a/test/CodeGen/Mips/mips64-libcall.ll
+++ b/test/CodeGen/Mips/mips64-libcall.ll
@@ -5,7 +5,7 @@
 
 ; Check that %add is not passed in an integer register.
 ;
-; HARD: callfloor:
+; HARD-LABEL: callfloor:
 ; HARD-NOT: dmfc1 $4
 
 define double @callfloor(double %d) nounwind readnone {
@@ -19,7 +19,7 @@ declare double @floor(double) nounwind readnone
 
 ; Check call16.
 ;
-; SOFT: f64add:
+; SOFT-LABEL: f64add:
 ; SOFT: ld $25, %call16(__adddf3)
 
 define double @f64add(double %a, double %b) {
diff --git a/test/CodeGen/Mips/mips64instrs.ll b/test/CodeGen/Mips/mips64instrs.ll
index 2e3df3a..7b06c2d 100644
--- a/test/CodeGen/Mips/mips64instrs.ll
+++ b/test/CodeGen/Mips/mips64instrs.ll
@@ -86,7 +86,7 @@ entry:
 
 define i64 @f14(i64 %a, i64 %b) nounwind readnone {
 entry:
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; CHECK: teq $[[R0]], $zero, 7
 ; CHECK: mflo
@@ -96,7 +96,7 @@ entry:
 
 define i64 @f15(i64 %a, i64 %b) nounwind readnone {
 entry:
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; CHECK: teq $[[R0]], $zero, 7
 ; CHECK: mflo
@@ -106,7 +106,7 @@ entry:
 
 define i64 @f16(i64 %a, i64 %b) nounwind readnone {
 entry:
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; CHECK: teq $[[R0]], $zero, 7
 ; CHECK: mfhi
@@ -116,7 +116,7 @@ entry:
 
 define i64 @f17(i64 %a, i64 %b) nounwind readnone {
 entry:
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
 ; CHECK: teq $[[R0]], $zero, 7
 ; CHECK: mfhi
diff --git a/test/CodeGen/Mips/misha.ll b/test/CodeGen/Mips/misha.ll
index 80637ed..65d3b7b 100644
--- a/test/CodeGen/Mips/misha.ll
+++ b/test/CodeGen/Mips/misha.ll
@@ -25,10 +25,10 @@ for.body:                                         ; preds = %for.body.lr.ph, %fo
   %inc = add nsw i32 %i.010, 1
   %cmp = icmp eq i32 %inc, %conv
   br i1 %cmp, label %for.end, label %for.body
-; 16: sumc:
+; 16-LABEL: sumc:
 ; 16: 	lbu	${{[0-9]+}}, 0(${{[0-9]+}})
 ; 16: 	lbu	${{[0-9]+}}, 0(${{[0-9]+}})
-; 16: sum:
+; 16-LABEL: sum:
 ; 16: 	lhu	${{[0-9]+}}, 0(${{[0-9]+}})
 ; 16: 	lhu	${{[0-9]+}}, 0(${{[0-9]+}})
 
diff --git a/test/CodeGen/Mips/mno-ldc1-sdc1.ll b/test/CodeGen/Mips/mno-ldc1-sdc1.ll
index eae9a22..be9d0b6 100644
--- a/test/CodeGen/Mips/mno-ldc1-sdc1.ll
+++ b/test/CodeGen/Mips/mno-ldc1-sdc1.ll
@@ -8,16 +8,16 @@
 
 @g0 = common global double 0.000000e+00, align 8
 
-; LE-PIC: test_ldc1:
+; LE-PIC-LABEL: test_ldc1:
 ; LE-PIC: lwc1 $f0, 0(${{[0-9]+}})
 ; LE-PIC: lwc1 $f1, 4(${{[0-9]+}})
-; LE-STATIC: test_ldc1:
+; LE-STATIC-LABEL: test_ldc1:
 ; LE-STATIC: lwc1 $f0, %lo(g0)(${{[0-9]+}})
 ; LE-STATIC: lwc1 $f1, %lo(g0+4)(${{[0-9]+}})
-; BE-PIC: test_ldc1:
+; BE-PIC-LABEL: test_ldc1:
 ; BE-PIC: lwc1 $f1, 0(${{[0-9]+}})
 ; BE-PIC: lwc1 $f0, 4(${{[0-9]+}})
-; CHECK-LDC1-SDC1: test_ldc1:
+; CHECK-LDC1-SDC1-LABEL: test_ldc1:
 ; CHECK-LDC1-SDC1: ldc1 $f{{[0-9]+}}
 
 define double @test_ldc1() {
@@ -26,16 +26,16 @@ entry:
   ret double %0
 }
 
-; LE-PIC: test_sdc1:
+; LE-PIC-LABEL: test_sdc1:
 ; LE-PIC: swc1 $f12, 0(${{[0-9]+}})
 ; LE-PIC: swc1 $f13, 4(${{[0-9]+}})
-; LE-STATIC: test_sdc1:
+; LE-STATIC-LABEL: test_sdc1:
 ; LE-STATIC: swc1 $f12, %lo(g0)(${{[0-9]+}})
 ; LE-STATIC: swc1 $f13, %lo(g0+4)(${{[0-9]+}})
-; BE-PIC: test_sdc1:
+; BE-PIC-LABEL: test_sdc1:
 ; BE-PIC: swc1 $f13, 0(${{[0-9]+}})
 ; BE-PIC: swc1 $f12, 4(${{[0-9]+}})
-; CHECK-LDC1-SDC1: test_sdc1:
+; CHECK-LDC1-SDC1-LABEL: test_sdc1:
 ; CHECK-LDC1-SDC1: sdc1 $f{{[0-9]+}}
 
 define void @test_sdc1(double %a) {
diff --git a/test/CodeGen/Mips/o32_cc_vararg.ll b/test/CodeGen/Mips/o32_cc_vararg.ll
index 35332b6..10972e8 100644
--- a/test/CodeGen/Mips/o32_cc_vararg.ll
+++ b/test/CodeGen/Mips/o32_cc_vararg.ll
@@ -27,7 +27,7 @@ entry:
   %tmp = load i32* %b, align 4
   ret i32 %tmp
 
-; CHECK: va1:
+; CHECK-LABEL: va1:
 ; CHECK: addiu   $sp, $sp, -16
 ; CHECK: sw      $7, 28($sp)
 ; CHECK: sw      $6, 24($sp)
@@ -53,7 +53,7 @@ entry:
   %tmp = load double* %b, align 8
   ret double %tmp
 
-; CHECK: va2:
+; CHECK-LABEL: va2:
 ; CHECK: addiu   $sp, $sp, -16
 ; CHECK: sw      $7, 28($sp)
 ; CHECK: sw      $6, 24($sp)
@@ -81,7 +81,7 @@ entry:
   %tmp = load i32* %b, align 4
   ret i32 %tmp
 
-; CHECK: va3:
+; CHECK-LABEL: va3:
 ; CHECK: addiu   $sp, $sp, -16
 ; CHECK: sw      $7, 28($sp)
 ; CHECK: sw      $6, 24($sp)
@@ -104,7 +104,7 @@ entry:
   %tmp = load double* %b, align 8
   ret double %tmp
 
-; CHECK: va4:
+; CHECK-LABEL: va4:
 ; CHECK: addiu   $sp, $sp, -24
 ; CHECK: sw      $7, 36($sp)
 ; CHECK: sw      $6, 32($sp)
@@ -132,7 +132,7 @@ entry:
   %tmp = load i32* %d, align 4
   ret i32 %tmp
 
-; CHECK: va5:
+; CHECK-LABEL: va5:
 ; CHECK: addiu   $sp, $sp, -24
 ; CHECK: sw      $7, 36($sp)
 ; CHECK: lw      $2, 36($sp)
@@ -158,7 +158,7 @@ entry:
   %tmp = load double* %d, align 8
   ret double %tmp
 
-; CHECK: va6:
+; CHECK-LABEL: va6:
 ; CHECK: addiu   $sp, $sp, -24
 ; CHECK: sw      $7, 36($sp)
 ; CHECK: addiu   $[[R0:[0-9]+]], $sp, 36
@@ -186,7 +186,7 @@ entry:
   %tmp = load i32* %c, align 4
   ret i32 %tmp
 
-; CHECK: va7:
+; CHECK-LABEL: va7:
 ; CHECK: addiu   $sp, $sp, -24
 ; CHECK: lw      $2, 40($sp)
 }
@@ -209,7 +209,7 @@ entry:
   %tmp = load double* %c, align 8
   ret double %tmp
 
-; CHECK: va8:
+; CHECK-LABEL: va8:
 ; CHECK: addiu   $sp, $sp, -32
 ; CHECK: addiu   ${{[0-9]+}}, $sp, 48
 ; CHECK: ldc1    $f0, 48($sp)
@@ -235,7 +235,7 @@ entry:
   %tmp = load i32* %d, align 4
   ret i32 %tmp
 
-; CHECK: va9:
+; CHECK-LABEL: va9:
 ; CHECK: addiu   $sp, $sp, -32
 ; CHECK: lw      $2, 52($sp)
 }
@@ -260,7 +260,7 @@ entry:
   %tmp = load double* %d, align 8
   ret double %tmp
 
-; CHECK: va10:
+; CHECK-LABEL: va10:
 ; CHECK: addiu   $sp, $sp, -32
 ; CHECK: addiu   $[[R0:[0-9]+]], $sp, 52
 ; CHECK: addiu   $[[R1:[0-9]+]], $[[R0]], 7
diff --git a/test/CodeGen/Mips/optimize-fp-math.ll b/test/CodeGen/Mips/optimize-fp-math.ll
index 9348d3c..8b71dc4 100644
--- a/test/CodeGen/Mips/optimize-fp-math.ll
+++ b/test/CodeGen/Mips/optimize-fp-math.ll
@@ -1,10 +1,10 @@
 ; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
 
-; 32: test_sqrtf_float_:
+; 32-LABEL: test_sqrtf_float_:
 ; 32: sqrt.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 32: c.un.s $f[[R0]], $f[[R0]]
-; 64: test_sqrtf_float_:
+; 64-LABEL: test_sqrtf_float_:
 ; 64: sqrt.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 64: c.un.s $f[[R0]], $f[[R0]]
 
@@ -16,10 +16,10 @@ entry:
 
 declare float @sqrtf(float)
 
-; 32: test_sqrt_double_:
+; 32-LABEL: test_sqrt_double_:
 ; 32: sqrt.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 32: c.un.d $f[[R0]], $f[[R0]]
-; 64: test_sqrt_double_:
+; 64-LABEL: test_sqrt_double_:
 ; 64: sqrt.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 64: c.un.d $f[[R0]], $f[[R0]]
 
diff --git a/test/CodeGen/Mips/private.ll b/test/CodeGen/Mips/private.ll
index d1a67fd..058db0b 100644
--- a/test/CodeGen/Mips/private.ll
+++ b/test/CodeGen/Mips/private.ll
@@ -3,14 +3,14 @@
 ; RUN: llc -march=mips < %s | FileCheck %s
 
 define private void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
   ret void
 }
 
 @baz = private global i32 4
 
 define i32 @bar() {
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: call16($foo)
 ; CHECK: lw $[[R0:[0-9]+]], %got($baz)($
 ; CHECK: lw ${{[0-9]+}}, %lo($baz)($[[R0]])
diff --git a/test/CodeGen/Mips/return-vector.ll b/test/CodeGen/Mips/return-vector.ll
index 739c43c..0e0d515 100644
--- a/test/CodeGen/Mips/return-vector.ll
+++ b/test/CodeGen/Mips/return-vector.ll
@@ -30,7 +30,7 @@ entry:
   %add7 = add i32 %add5, %add6
   ret i32 %add7
 
-; CHECK:        call_i8:
+; CHECK-LABEL:        call_i8:
 ; CHECK:        call16(i8)
 ; CHECK:        addiu   $4, $sp, 32
 ; CHECK:        lw      $[[R0:[a-z0-9]+]], 60($sp)
@@ -56,7 +56,7 @@ entry:
   %add3 = fadd float %add1, %add2
   ret float %add3
 
-; CHECK:        call_f4:
+; CHECK-LABEL:        call_f4:
 ; CHECK:        call16(f4)
 ; CHECK:        addiu   $4, $sp, 16
 ; CHECK:        lwc1    $[[R0:[a-z0-9]+]], 28($sp)
@@ -78,7 +78,7 @@ entry:
   %add3 = fadd double %add1, %add2
   ret double %add3
 
-; CHECK:        call_d4:
+; CHECK-LABEL:        call_d4:
 ; CHECK:        call16(d4)
 ; CHECK:        addiu   $4, $sp, 32
 ; CHECK:        ldc1    $[[R0:[a-z0-9]+]], 56($sp)
@@ -109,7 +109,7 @@ entry:
   %add3 = add i32 %add1, %add2
   ret i32 %add3
 
-; CHECK:        call_i4:
+; CHECK-LABEL:        call_i4:
 ; CHECK:        call16(i4)
 ; CHECK-NOT:    lw
 ; CHECK:        addu    $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
@@ -126,7 +126,7 @@ entry:
   %add1 = fadd float %v0, %v1
   ret float %add1
 
-; CHECK:        call_f2:
+; CHECK-LABEL:        call_f2:
 ; CHECK:        call16(f2)
 ; CHECK-NOT:    lwc1
 ; CHECK:        add.s    $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
@@ -141,7 +141,7 @@ entry:
   %add1 = fadd double %v0, %v1
   ret double %add1
 
-; CHECK:        call_d2:
+; CHECK-LABEL:        call_d2:
 ; CHECK:        call16(d2)
 ; CHECK-NOT:    ldc1
 ; CHECK:        add.d    $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
@@ -158,7 +158,7 @@ define <8 x i32> @return_i8() {
 entry:
   ret <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
 
-; CHECK:        return_i8:
+; CHECK-LABEL:        return_i8:
 ; CHECK:        sw      $[[R0:[a-z0-9]+]], 28($4)
 ; CHECK:        sw      $[[R1:[a-z0-9]+]], 24($4)
 ; CHECK:        sw      $[[R2:[a-z0-9]+]], 20($4)
@@ -178,12 +178,12 @@ entry:
   %vecins4 = insertelement <4 x float> %vecins3, float %d, i32 3
   ret <4 x float> %vecins4
 
-; CHECK:        return_f4:
-; CHECK:        lwc1    $[[R0:[a-z0-9]+]], 16($sp)
-; CHECK:        swc1    $[[R0]], 12($4)
-; CHECK:        sw      $7, 8($4)
-; CHECK:        sw      $6, 4($4)
-; CHECK:        sw      $5, 0($4)
+; CHECK-LABEL:        return_f4:
+; CHECK-DAG:    lwc1    $[[R0:[a-z0-9]+]], 16($sp)
+; CHECK-DAG:    swc1    $[[R0]], 12($4)
+; CHECK-DAG:    sw      $7, 8($4)
+; CHECK-DAG:    sw      $6, 4($4)
+; CHECK-DAG:    sw      $5, 0($4)
 }
 
 
@@ -195,11 +195,11 @@ entry:
   %vecins4 = insertelement <4 x double> %vecins3, double %d, i32 3
   ret <4 x double> %vecins4
 
-; CHECK:        return_d4:
-; CHECK:        sdc1    $[[R0:[a-z0-9]+]], 24($4)
-; CHECK:        sdc1    $[[R1:[a-z0-9]+]], 16($4)
-; CHECK:        sdc1    $[[R2:[a-z0-9]+]], 8($4)
-; CHECK:        sdc1    $[[R3:[a-z0-9]+]], 0($4)
+; CHECK-LABEL:            return_d4:
+; CHECK-DAG:        sdc1    $[[R0:[a-z0-9]+]], 24($4)
+; CHECK-DAG:        sdc1    $[[R1:[a-z0-9]+]], 16($4)
+; CHECK-DAG:        sdc1    $[[R2:[a-z0-9]+]], 8($4)
+; CHECK-DAG:        sdc1    $[[R3:[a-z0-9]+]], 0($4)
 }
 
 
@@ -212,7 +212,7 @@ define <4 x i32> @return_i4() {
 entry:
   ret <4 x i32> <i32 0, i32 1, i32 2, i32 3>
 
-; CHECK:        return_i4:
+; CHECK-LABEL:        return_i4:
 ; CHECK:        addiu   $2, $zero, 0
 ; CHECK:        addiu   $3, $zero, 1
 ; CHECK:        addiu   $4, $zero, 2
@@ -226,7 +226,7 @@ entry:
   %vecins2 = insertelement <2 x float> %vecins1, float %b, i32 1
   ret <2 x float> %vecins2
 
-; CHECK:        return_f2:
+; CHECK-LABEL:        return_f2:
 ; CHECK:        mov.s   $f0, $f12
 ; CHECK:        mov.s   $f2, $f14
 }
@@ -238,7 +238,7 @@ entry:
   %vecins2 = insertelement <2 x double> %vecins1, double %b, i32 1
   ret <2 x double> %vecins2
 
-; CHECK:        return_d2:
+; CHECK-LABEL:        return_d2:
 ; CHECK:        mov.d   $f0, $f12
 ; CHECK:        mov.d   $f2, $f14
 }
diff --git a/test/CodeGen/Mips/selnek.ll b/test/CodeGen/Mips/selnek.ll
index 2601552..64834b2 100644
--- a/test/CodeGen/Mips/selnek.ll
+++ b/test/CodeGen/Mips/selnek.ll
@@ -104,4 +104,4 @@ attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" }
 ; 16:	bteqz	$BB{{[0-9]+}}_{{[0-9]}}
 
 ; 16:	cmpi	${{[0-9]+}}, 1000
-; 16:	bteqz	$BB{{[0-9]+}}_{{[0-9]}}
\ No newline at end of file
+; 16:	bteqz	$BB{{[0-9]+}}_{{[0-9]}}
diff --git a/test/CodeGen/Mips/setcc-se.ll b/test/CodeGen/Mips/setcc-se.ll
index 284cd35..99071c4 100644
--- a/test/CodeGen/Mips/setcc-se.ll
+++ b/test/CodeGen/Mips/setcc-se.ll
@@ -2,7 +2,7 @@
 
 @g1 = external global i32
 
-; CHECK: seteq0:
+; CHECK-LABEL: seteq0:
 ; CHECK: sltiu ${{[0-9]+}}, $4, 1
 
 define i32 @seteq0(i32 %a) {
@@ -12,7 +12,7 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: setne0:
+; CHECK-LABEL: setne0:
 ; CHECK: sltu ${{[0-9]+}}, $zero, $4
 
 define i32 @setne0(i32 %a) {
@@ -22,9 +22,9 @@ entry:
   ret i32 %conv
 }
 
-; CHECK: slti_beq0:
+; CHECK-LABEL: slti_beq0:
 ; CHECK: slti $[[R0:[0-9]+]], $4, -32768
-; CHECK: beq $[[R0]], $zero
+; CHECK: beqz $[[R0]]
 
 define void @slti_beq0(i32 %a) {
 entry:
@@ -39,7 +39,7 @@ if.end:
   ret void
 }
 
-; CHECK: slti_beq1:
+; CHECK-LABEL: slti_beq1:
 ; CHECK: slt ${{[0-9]+}}
 
 define void @slti_beq1(i32 %a) {
@@ -55,9 +55,9 @@ if.end:
   ret void
 }
 
-; CHECK: slti_beq2:
+; CHECK-LABEL: slti_beq2:
 ; CHECK: slti $[[R0:[0-9]+]], $4, 32767
-; CHECK: beq $[[R0]], $zero
+; CHECK: beqz $[[R0]]
 
 define void @slti_beq2(i32 %a) {
 entry:
@@ -72,7 +72,7 @@ if.end:
   ret void
 }
 
-; CHECK: slti_beq3:
+; CHECK-LABEL: slti_beq3:
 ; CHECK: slt ${{[0-9]+}}
 
 define void @slti_beq3(i32 %a) {
@@ -88,9 +88,9 @@ if.end:
   ret void
 }
 
-; CHECK: sltiu_beq0:
+; CHECK-LABEL: sltiu_beq0:
 ; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
-; CHECK: beq $[[R0]], $zero
+; CHECK: beqz $[[R0]]
 
 define void @sltiu_beq0(i32 %a) {
 entry:
@@ -105,7 +105,7 @@ if.end:
   ret void
 }
 
-; CHECK: sltiu_beq1:
+; CHECK-LABEL: sltiu_beq1:
 ; CHECK: sltu ${{[0-9]+}}
 
 define void @sltiu_beq1(i32 %a) {
@@ -121,9 +121,9 @@ if.end:
   ret void
 }
 
-; CHECK: sltiu_beq2:
+; CHECK-LABEL: sltiu_beq2:
 ; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
-; CHECK: beq $[[R0]], $zero
+; CHECK: beqz $[[R0]]
 
 define void @sltiu_beq2(i32 %a) {
 entry:
@@ -138,7 +138,7 @@ if.end:
   ret void
 }
 
-; CHECK: sltiu_beq3:
+; CHECK-LABEL: sltiu_beq3:
 ; CHECK: sltu ${{[0-9]+}}
 
 define void @sltiu_beq3(i32 %a) {
diff --git a/test/CodeGen/Mips/sint-fp-store_pattern.ll b/test/CodeGen/Mips/sint-fp-store_pattern.ll
index 23a8aea..c44ea08 100644
--- a/test/CodeGen/Mips/sint-fp-store_pattern.ll
+++ b/test/CodeGen/Mips/sint-fp-store_pattern.ll
@@ -4,7 +4,7 @@
 @gint_ = external global i32
 @gLL_ = external global i64
 
-; 32: store_int_float_:
+; 32-LABEL: store_int_float_:
 ; 32: trunc.w.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 32: swc1 $f[[R0]],
 
@@ -15,10 +15,10 @@ entry:
   ret void
 }
 
-; 32: store_int_double_:
+; 32-LABEL: store_int_double_:
 ; 32: trunc.w.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 32: swc1 $f[[R0]],
-; 64: store_int_double_:
+; 64-LABEL: store_int_double_:
 ; 64: trunc.w.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 64: swc1 $f[[R0]],
 
@@ -29,7 +29,7 @@ entry:
   ret void
 }
 
-; 64: store_LL_float_:
+; 64-LABEL: store_LL_float_:
 ; 64: trunc.l.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 64: sdc1 $f[[R0]],
 
@@ -40,7 +40,7 @@ entry:
   ret void
 }
 
-; 64: store_LL_double_:
+; 64-LABEL: store_LL_double_:
 ; 64: trunc.l.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 64: sdc1 $f[[R0]],
 
diff --git a/test/CodeGen/Mips/stackcoloring.ll b/test/CodeGen/Mips/stackcoloring.ll
index 76cc086..4987dad 100644
--- a/test/CodeGen/Mips/stackcoloring.ll
+++ b/test/CodeGen/Mips/stackcoloring.ll
@@ -2,7 +2,7 @@
 
 @g1 = external global i32*
 
-; CHECK: foo1:
+; CHECK-LABEL: foo1:
 ; CHECK: lw ${{[0-9]+}}, %got(g1)
 ; CHECK: # %for.body
 ; CHECK: # %for.end
diff --git a/test/CodeGen/Mips/stchar.ll b/test/CodeGen/Mips/stchar.ll
index c00c9fd..12eae34 100644
--- a/test/CodeGen/Mips/stchar.ll
+++ b/test/CodeGen/Mips/stchar.ll
@@ -50,8 +50,8 @@ entry:
   %conv1.i = sext i8 %3 to i32
   %call.i = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i32 %conv.i, i32 %conv1.i) nounwind
   ret void
-; 16_b: test:
-; 16_h: test:
+; 16_b-LABEL: test:
+; 16_h-LABEL: test:
 ; 16_b:	sb	${{[0-9]+}}, [[offset1:[0-9]+]](${{[0-9]+}})
 ; 16_b: lb      ${{[0-9]+}}, [[offset1]](${{[0-9]+}})
 ; 16_h:	sh	${{[0-9]+}}, [[offset2:[0-9]+]](${{[0-9]+}})
diff --git a/test/CodeGen/Mips/tls-alias.ll b/test/CodeGen/Mips/tls-alias.ll
index ce98cc8..3c81054 100644
--- a/test/CodeGen/Mips/tls-alias.ll
+++ b/test/CodeGen/Mips/tls-alias.ll
@@ -4,7 +4,7 @@
 @bar = hidden alias i32* @foo
 
 define i32* @zed() {
-; CHECK: __tls_get_addr
-; CHECK-NEXT: %tlsgd(bar)
+; CHECK-DAG: __tls_get_addr
+; CHECK-DAG: %tlsgd(bar)
        ret i32* @bar
 }
diff --git a/test/CodeGen/Mips/tls-models.ll b/test/CodeGen/Mips/tls-models.ll
index 8f5789e..1a958dc 100644
--- a/test/CodeGen/Mips/tls-models.ll
+++ b/test/CodeGen/Mips/tls-models.ll
@@ -20,9 +20,9 @@ entry:
   ret i32* @external_gd
 
   ; Non-PIC code can use initial-exec, PIC code has to use general dynamic.
-  ; CHECK-NONPIC:   f1:
+  ; CHECK-NONPIC-LABEL:   f1:
   ; CHECK-NONPIC:   %gottprel
-  ; CHECK-PIC:      f1:
+  ; CHECK-PIC-LABEL:      f1:
   ; CHECK-PIC:      %tlsgd
 }
 
@@ -31,9 +31,9 @@ entry:
   ret i32* @internal_gd
 
   ; Non-PIC code can use local exec, PIC code can use local dynamic.
-  ; CHECK-NONPIC:   f2:
+  ; CHECK-NONPIC-LABEL:   f2:
   ; CHECK-NONPIC:   %tprel_hi
-  ; CHECK-PIC:      f2:
+  ; CHECK-PIC-LABEL:      f2:
   ; CHECK-PIC:      %tlsldm
 }
 
@@ -45,9 +45,9 @@ entry:
   ret i32* @external_ld
 
   ; Non-PIC code can use initial exec, PIC should use local dynamic.
-  ; CHECK-NONPIC:   f3:
+  ; CHECK-NONPIC-LABEL:   f3:
   ; CHECK-NONPIC:   %gottprel
-  ; CHECK-PIC:      f3:
+  ; CHECK-PIC-LABEL:      f3:
   ; CHECK-PIC:      %tlsldm
 }
 
@@ -56,9 +56,9 @@ entry:
   ret i32* @internal_ld
 
   ; Non-PIC code can use local exec, PIC code can use local dynamic.
-  ; CHECK-NONPIC:   f4:
+  ; CHECK-NONPIC-LABEL:   f4:
   ; CHECK-NONPIC:   %tprel_hi
-  ; CHECK-PIC:      f4:
+  ; CHECK-PIC-LABEL:      f4:
   ; CHECK-PIC:      %tlsldm
 }
 
@@ -70,9 +70,9 @@ entry:
   ret i32* @external_ie
 
   ; Non-PIC and PIC code will use initial exec as specified.
-  ; CHECK-NONPIC:   f5:
+  ; CHECK-NONPIC-LABEL:   f5:
   ; CHECK-NONPIC:   %gottprel
-  ; CHECK-PIC:      f5:
+  ; CHECK-PIC-LABEL:      f5:
   ; CHECK-PIC:      %gottprel
 }
 
@@ -81,9 +81,9 @@ entry:
   ret i32* @internal_ie
 
   ; Non-PIC code can use local exec, PIC code use initial exec as specified.
-  ; CHECK-NONPIC:   f6:
+  ; CHECK-NONPIC-LABEL:   f6:
   ; CHECK-NONPIC:   %tprel_hi
-  ; CHECK-PIC:      f6:
+  ; CHECK-PIC-LABEL:      f6:
   ; CHECK-PIC:      %gottprel
 }
 
@@ -95,9 +95,9 @@ entry:
   ret i32* @external_le
 
   ; Non-PIC and PIC code will use local exec as specified.
-  ; CHECK-NONPIC:   f7:
+  ; CHECK-NONPIC-LABEL:   f7:
   ; CHECK-NONPIC:   %tprel_hi
-  ; CHECK-PIC:      f7:
+  ; CHECK-PIC-LABEL:      f7:
   ; CHECK-PIC:      %tprel_hi
 }
 
@@ -106,8 +106,8 @@ entry:
   ret i32* @internal_le
 
   ; Non-PIC and PIC code will use local exec as specified.
-  ; CHECK-NONPIC:   f8:
+  ; CHECK-NONPIC-LABEL:   f8:
   ; CHECK-NONPIC:   %tprel_hi
-  ; CHECK-PIC:      f8:
+  ; CHECK-PIC-LABEL:      f8:
   ; CHECK-PIC:      %tprel_hi
 }
diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll
index b86d25e..23a8f93 100644
--- a/test/CodeGen/Mips/tls.ll
+++ b/test/CodeGen/Mips/tls.ll
@@ -13,14 +13,14 @@ entry:
   %tmp = load i32* @t1, align 4
   ret i32 %tmp
 
-; CHECK: f1:
-
-; PIC:   addu    $[[R0:[a-z0-9]+]], $2, $25
-; PIC:   lw      $25, %call16(__tls_get_addr)($[[R0]])
-; PIC:   addiu   $4, $[[R0]], %tlsgd(t1)
-; PIC:   jalr    $25
-; PIC:   lw      $2, 0($2)
-
+; PIC-LABEL:       f1:
+; PIC-DAG:   addu    $[[R0:[a-z0-9]+]], $2, $25
+; PIC-DAG:   lw      $25, %call16(__tls_get_addr)($[[R0]])
+; PIC-DAG:   addiu   $4, $[[R0]], %tlsgd(t1)
+; PIC-DAG:   jalr    $25
+; PIC-DAG:   lw      $2, 0($2)
+
+; STATIC-LABEL:   f1:
 ; STATIC:   lui     $[[R0:[0-9]+]], %tprel_hi(t1)
 ; STATIC:   addiu   $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
 ; STATIC:   rdhwr   $3, $29
@@ -36,17 +36,19 @@ entry:
   %tmp = load i32* @t2, align 4
   ret i32 %tmp
 
-; CHECK: f2:
-
-; PIC:   addu    $[[R0:[a-z0-9]+]], $2, $25
-; PIC:   lw      $25, %call16(__tls_get_addr)($[[R0]])
-; PIC:   addiu   $4, $[[R0]], %tlsgd(t2)
-; PIC:   jalr    $25
-; PIC:   lw      $2, 0($2)
+; PIC-LABEL:       f2:
+; PIC-DAG:   addu    $[[R0:[a-z0-9]+]], $2, $25
+; PIC-DAG:   lw      $25, %call16(__tls_get_addr)($[[R0]])
+; PIC-DAG:   addiu   $4, $[[R0]], %tlsgd(t2)
+; PIC-DAG:   jalr    $25
+; PIC-DAG:   lw      $2, 0($2)
 
+; STATICGP-LABEL: f2:
 ; STATICGP: lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
 ; STATICGP: addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
 ; STATICGP: lw      ${{[0-9]+}}, %gottprel(t2)($[[GP]])
+
+; STATIC-LABEL:   f2:
 ; STATIC:   lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
 ; STATIC:   addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
 ; STATIC:   rdhwr   $3, $29
@@ -59,7 +61,7 @@ entry:
 
 define i32 @f3() nounwind {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 
 ; PIC:   addiu   $4, ${{[a-z0-9]+}}, %tlsldm(f3.i)
 ; PIC:   jalr    $25
diff --git a/test/CodeGen/Mips/tnaked.ll b/test/CodeGen/Mips/tnaked.ll
index f5bdd91..edf1ecf 100644
--- a/test/CodeGen/Mips/tnaked.ll
+++ b/test/CodeGen/Mips/tnaked.ll
@@ -7,7 +7,7 @@ entry:
 }
 
 ; CHECK: 	.ent	tnaked
-; CHECK:          tnaked: 
+; CHECK-LABEL:          tnaked:
 ; CHECK-NOT:	.frame	{{.*}}
 ; CHECK-NOT:     .mask 	{{.*}}
 ; CHECK-NOT:	.fmask	{{.*}}
@@ -19,7 +19,7 @@ entry:
 }
 
 ; CHECK: 	.ent	tnonaked
-; CHECK:         tnonaked: 
+; CHECK-LABEL:         tnonaked:
 ; CHECK:	.frame	$fp,8,$ra
 ; CHECK:        .mask 	0x40000000,-4
 ; CHECK:	.fmask	0x00000000,0
diff --git a/test/CodeGen/Mips/trap.ll b/test/CodeGen/Mips/trap.ll
new file mode 100644
index 0000000..beb4b89
--- /dev/null
+++ b/test/CodeGen/Mips/trap.ll
@@ -0,0 +1,11 @@
+; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s
+
+declare void @llvm.trap()
+
+define void @f1() {
+entry:
+  call void @llvm.trap()
+  unreachable
+
+; CHECK:        break
+}
diff --git a/test/CodeGen/Mips/trap1.ll b/test/CodeGen/Mips/trap1.ll
new file mode 100644
index 0000000..bfcd7fe
--- /dev/null
+++ b/test/CodeGen/Mips/trap1.ll
@@ -0,0 +1,13 @@
+; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic < %s | FileCheck %s -check-prefix=pic
+
+declare void @llvm.trap()
+
+; Function Attrs: nounwind optsize readnone
+define i32 @main()  {
+entry:
+  call void @llvm.trap()
+  unreachable
+; pic: break 0
+  ret i32 0
+}
+
diff --git a/test/CodeGen/Mips/unalignedload.ll b/test/CodeGen/Mips/unalignedload.ll
index 7f880b6..19f3af7 100644
--- a/test/CodeGen/Mips/unalignedload.ll
+++ b/test/CodeGen/Mips/unalignedload.ll
@@ -9,17 +9,17 @@
 
 define void @foo1() nounwind {
 entry:
-; CHECK-EL: lbu ${{[0-9]+}}, 2($[[R0:[0-9]+]])
-; CHECK-EL: lbu ${{[0-9]+}}, 3($[[R0]])
-; CHECK-EL: jalr
-; CHECK-EL: lwl $[[R1:[0-9]+]], 3($[[R2:[0-9]+]])
-; CHECK-EL: lwr $[[R1]], 0($[[R2]])
+; CHECK-EL-DAG: lbu ${{[0-9]+}}, 2($[[R0:[0-9]+]])
+; CHECK-EL-DAG: lbu ${{[0-9]+}}, 3($[[R0]])
+; CHECK-EL:     jalr
+; CHECK-EL-DAG: lwl $[[R1:[0-9]+]], 3($[[R2:[0-9]+]])
+; CHECK-EL-DAG: lwr $[[R1]], 0($[[R2]])
 
-; CHECK-EB: lbu ${{[0-9]+}}, 3($[[R0:[0-9]+]])
-; CHECK-EB: lbu ${{[0-9]+}}, 2($[[R0]])
-; CHECK-EB: jalr
-; CHECK-EB: lwl $[[R1:[0-9]+]], 0($[[R2:[0-9]+]])
-; CHECK-BE: lwr $[[R1]], 3($[[R2]])
+; CHECK-EB-DAG: lbu ${{[0-9]+}}, 3($[[R0:[0-9]+]])
+; CHECK-EB-DAG: lbu ${{[0-9]+}}, 2($[[R0]])
+; CHECK-EB:     jalr
+; CHECK-EB-DAG: lwl $[[R1:[0-9]+]], 0($[[R2:[0-9]+]])
+; CHECK-EB-DAG: lwr $[[R1]], 3($[[R2]])
 
   tail call void @foo2(%struct.S1* byval getelementptr inbounds (%struct.S2* @s2, i32 0, i32 1)) nounwind
   tail call void @foo4(%struct.S4* byval @s4) nounwind
diff --git a/test/CodeGen/NVPTX/add-128bit.ll b/test/CodeGen/NVPTX/add-128bit.ll
new file mode 100644
index 0000000..29e3cdf
--- /dev/null
+++ b/test/CodeGen/NVPTX/add-128bit.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+
+
+define void @foo(i64 %a, i64 %add, i128* %retptr) {
+; CHECK:        add.s64
+; CHECK:        setp.lt.u64
+; CHECK:        setp.lt.u64
+; CHECK:        selp.b64
+; CHECK:        selp.b64
+; CHECK:        add.s64
+  %t1 = sext i64 %a to i128
+  %add2 = zext i64 %add to i128
+  %val = add i128 %t1, %add2
+  store i128 %val, i128* %retptr
+  ret void
+}
diff --git a/test/CodeGen/NVPTX/compare-int.ll b/test/CodeGen/NVPTX/compare-int.ll
index 16af0a3..c595f21 100644
--- a/test/CodeGen/NVPTX/compare-int.ll
+++ b/test/CodeGen/NVPTX/compare-int.ll
@@ -195,7 +195,7 @@ define i32 @icmp_sle_i32(i32 %a, i32 %b) {
 
 define i16 @icmp_eq_i16(i16 %a, i16 %b) {
 ; CHECK: setp.eq.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
-; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp eq i16 %a, %b
   %ret = zext i1 %cmp to i16
@@ -204,7 +204,7 @@ define i16 @icmp_eq_i16(i16 %a, i16 %b) {
 
 define i16 @icmp_ne_i16(i16 %a, i16 %b) {
 ; CHECK: setp.ne.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
-; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp ne i16 %a, %b
   %ret = zext i1 %cmp to i16
@@ -213,7 +213,7 @@ define i16 @icmp_ne_i16(i16 %a, i16 %b) {
 
 define i16 @icmp_ugt_i16(i16 %a, i16 %b) {
 ; CHECK: setp.gt.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
-; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp ugt i16 %a, %b
   %ret = zext i1 %cmp to i16
@@ -222,7 +222,7 @@ define i16 @icmp_ugt_i16(i16 %a, i16 %b) {
 
 define i16 @icmp_uge_i16(i16 %a, i16 %b) {
 ; CHECK: setp.ge.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
-; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp uge i16 %a, %b
   %ret = zext i1 %cmp to i16
@@ -231,7 +231,7 @@ define i16 @icmp_uge_i16(i16 %a, i16 %b) {
 
 define i16 @icmp_ult_i16(i16 %a, i16 %b) {
 ; CHECK: setp.lt.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
-; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp ult i16 %a, %b
   %ret = zext i1 %cmp to i16
@@ -240,7 +240,7 @@ define i16 @icmp_ult_i16(i16 %a, i16 %b) {
 
 define i16 @icmp_ule_i16(i16 %a, i16 %b) {
 ; CHECK: setp.le.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
-; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp ule i16 %a, %b
   %ret = zext i1 %cmp to i16
@@ -249,7 +249,7 @@ define i16 @icmp_ule_i16(i16 %a, i16 %b) {
 
 define i16 @icmp_sgt_i16(i16 %a, i16 %b) {
 ; CHECK: setp.gt.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
-; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp sgt i16 %a, %b
   %ret = zext i1 %cmp to i16
@@ -258,7 +258,7 @@ define i16 @icmp_sgt_i16(i16 %a, i16 %b) {
 
 define i16 @icmp_sge_i16(i16 %a, i16 %b) {
 ; CHECK: setp.ge.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
-; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp sge i16 %a, %b
   %ret = zext i1 %cmp to i16
@@ -267,7 +267,7 @@ define i16 @icmp_sge_i16(i16 %a, i16 %b) {
 
 define i16 @icmp_slt_i16(i16 %a, i16 %b) {
 ; CHECK: setp.lt.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
-; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp slt i16 %a, %b
   %ret = zext i1 %cmp to i16
@@ -276,7 +276,7 @@ define i16 @icmp_slt_i16(i16 %a, i16 %b) {
 
 define i16 @icmp_sle_i16(i16 %a, i16 %b) {
 ; CHECK: setp.le.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
-; CHECK: selp.u16 %rs{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp sle i16 %a, %b
   %ret = zext i1 %cmp to i16
@@ -288,8 +288,8 @@ define i16 @icmp_sle_i16(i16 %a, i16 %b) {
 
 define i8 @icmp_eq_i8(i8 %a, i8 %b) {
 ; Comparison happens in 16-bit
-; CHECK: setp.eq.s16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}}
-; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: setp.eq.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp eq i8 %a, %b
   %ret = zext i1 %cmp to i8
@@ -298,8 +298,8 @@ define i8 @icmp_eq_i8(i8 %a, i8 %b) {
 
 define i8 @icmp_ne_i8(i8 %a, i8 %b) {
 ; Comparison happens in 16-bit
-; CHECK: setp.ne.s16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}}
-; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: setp.ne.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp ne i8 %a, %b
   %ret = zext i1 %cmp to i8
@@ -308,8 +308,8 @@ define i8 @icmp_ne_i8(i8 %a, i8 %b) {
 
 define i8 @icmp_ugt_i8(i8 %a, i8 %b) {
 ; Comparison happens in 16-bit
-; CHECK: setp.gt.u16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}}
-; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: setp.gt.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp ugt i8 %a, %b
   %ret = zext i1 %cmp to i8
@@ -318,8 +318,8 @@ define i8 @icmp_ugt_i8(i8 %a, i8 %b) {
 
 define i8 @icmp_uge_i8(i8 %a, i8 %b) {
 ; Comparison happens in 16-bit
-; CHECK: setp.ge.u16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}}
-; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: setp.ge.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp uge i8 %a, %b
   %ret = zext i1 %cmp to i8
@@ -328,8 +328,8 @@ define i8 @icmp_uge_i8(i8 %a, i8 %b) {
 
 define i8 @icmp_ult_i8(i8 %a, i8 %b) {
 ; Comparison happens in 16-bit
-; CHECK: setp.lt.u16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}}
-; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: setp.lt.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp ult i8 %a, %b
   %ret = zext i1 %cmp to i8
@@ -338,8 +338,8 @@ define i8 @icmp_ult_i8(i8 %a, i8 %b) {
 
 define i8 @icmp_ule_i8(i8 %a, i8 %b) {
 ; Comparison happens in 16-bit
-; CHECK: setp.le.u16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}}
-; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: setp.le.u16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp ule i8 %a, %b
   %ret = zext i1 %cmp to i8
@@ -348,8 +348,8 @@ define i8 @icmp_ule_i8(i8 %a, i8 %b) {
 
 define i8 @icmp_sgt_i8(i8 %a, i8 %b) {
 ; Comparison happens in 16-bit
-; CHECK: setp.gt.s16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}}
-; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: setp.gt.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp sgt i8 %a, %b
   %ret = zext i1 %cmp to i8
@@ -358,8 +358,8 @@ define i8 @icmp_sgt_i8(i8 %a, i8 %b) {
 
 define i8 @icmp_sge_i8(i8 %a, i8 %b) {
 ; Comparison happens in 16-bit
-; CHECK: setp.ge.s16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}}
-; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: setp.ge.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp sge i8 %a, %b
   %ret = zext i1 %cmp to i8
@@ -368,8 +368,8 @@ define i8 @icmp_sge_i8(i8 %a, i8 %b) {
 
 define i8 @icmp_slt_i8(i8 %a, i8 %b) {
 ; Comparison happens in 16-bit
-; CHECK: setp.lt.s16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}}
-; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: setp.lt.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp slt i8 %a, %b
   %ret = zext i1 %cmp to i8
@@ -378,8 +378,8 @@ define i8 @icmp_slt_i8(i8 %a, i8 %b) {
 
 define i8 @icmp_sle_i8(i8 %a, i8 %b) {
 ; Comparison happens in 16-bit
-; CHECK: setp.le.s16 %p[[P0:[0-9]+]], %temp{{[0-9]+}}, %temp{{[0-9]+}}
-; CHECK: selp.u16 %rc{{[0-9]+}}, 1, 0, %p[[P0]]
+; CHECK: setp.le.s16 %p[[P0:[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
+; CHECK: selp.u32 %r{{[0-9]+}}, 1, 0, %p[[P0]]
 ; CHECK: ret
   %cmp = icmp sle i8 %a, %b
   %ret = zext i1 %cmp to i8
diff --git a/test/CodeGen/NVPTX/convert-int-sm20.ll b/test/CodeGen/NVPTX/convert-int-sm20.ll
index fad240e..227cd31 100644
--- a/test/CodeGen/NVPTX/convert-int-sm20.ll
+++ b/test/CodeGen/NVPTX/convert-int-sm20.ll
@@ -8,16 +8,16 @@
 ; i16
 
 define i16 @cvt_i16_i32(i32 %x) {
-; CHECK: ld.param.u16 %rs[[R0:[0-9]+]], [cvt_i16_i32_param_{{[0-9]+}}]
-; CHECK: st.param.b16 [func_retval{{[0-9]+}}+0], %rs[[R0]]
+; CHECK: ld.param.u16 %r[[R0:[0-9]+]], [cvt_i16_i32_param_{{[0-9]+}}]
+; CHECK: st.param.b32 [func_retval{{[0-9]+}}+0], %r[[R0]]
 ; CHECK: ret
   %a = trunc i32 %x to i16
   ret i16 %a
 }
 
 define i16 @cvt_i16_i64(i64 %x) {
-; CHECK: ld.param.u16 %rs[[R0:[0-9]+]], [cvt_i16_i64_param_{{[0-9]+}}]
-; CHECK: st.param.b16 [func_retval{{[0-9]+}}+0], %rs[[R0]]
+; CHECK: ld.param.u16 %r[[R0:[0-9]+]], [cvt_i16_i64_param_{{[0-9]+}}]
+; CHECK: st.param.b32 [func_retval{{[0-9]+}}+0], %r[[R0]]
 ; CHECK: ret
   %a = trunc i64 %x to i16
   ret i16 %a
diff --git a/test/CodeGen/NVPTX/ctlz.ll b/test/CodeGen/NVPTX/ctlz.ll
new file mode 100644
index 0000000..bed15a9
--- /dev/null
+++ b/test/CodeGen/NVPTX/ctlz.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+declare i16 @llvm.ctlz.i16(i16, i1) readnone
+declare i32 @llvm.ctlz.i32(i32, i1) readnone
+declare i64 @llvm.ctlz.i64(i64, i1) readnone
+
+define i32 @myctpop(i32 %a) {
+; CHECK: clz.b32
+  %val = call i32 @llvm.ctlz.i32(i32 %a, i1 false) readnone
+  ret i32 %val
+}
+
+define i16 @myctpop16(i16 %a) {
+; CHECK: clz.b32
+  %val = call i16 @llvm.ctlz.i16(i16 %a, i1 false) readnone
+  ret i16 %val
+}
+
+define i64 @myctpop64(i64 %a) {
+; CHECK: clz.b64
+  %val = call i64 @llvm.ctlz.i64(i64 %a, i1 false) readnone
+  ret i64 %val
+}
+
+
+define i32 @myctpop_2(i32 %a) {
+; CHECK: clz.b32
+  %val = call i32 @llvm.ctlz.i32(i32 %a, i1 true) readnone
+  ret i32 %val
+}
+
+define i16 @myctpop16_2(i16 %a) {
+; CHECK: clz.b32
+  %val = call i16 @llvm.ctlz.i16(i16 %a, i1 true) readnone
+  ret i16 %val
+}
+
+define i64 @myctpop64_2(i64 %a) {
+; CHECK: clz.b64
+  %val = call i64 @llvm.ctlz.i64(i64 %a, i1 true) readnone
+  ret i64 %val
+}
diff --git a/test/CodeGen/NVPTX/ctpop.ll b/test/CodeGen/NVPTX/ctpop.ll
new file mode 100644
index 0000000..b961d4d
--- /dev/null
+++ b/test/CodeGen/NVPTX/ctpop.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+define i32 @myctpop(i32 %a) {
+; CHECK: popc.b32
+  %val = tail call i32 @llvm.ctpop.i32(i32 %a)
+  ret i32 %val
+}
+
+define i16 @myctpop16(i16 %a) {
+; CHECK: popc.b32
+  %val = tail call i16 @llvm.ctpop.i16(i16 %a)
+  ret i16 %val
+}
+
+define i64 @myctpop64(i64 %a) {
+; CHECK: popc.b64
+  %val = tail call i64 @llvm.ctpop.i64(i64 %a)
+  ret i64 %val
+}
+
+declare i16 @llvm.ctpop.i16(i16)
+declare i32 @llvm.ctpop.i32(i32)
+declare i64 @llvm.ctpop.i64(i64)
diff --git a/test/CodeGen/NVPTX/cttz.ll b/test/CodeGen/NVPTX/cttz.ll
new file mode 100644
index 0000000..124ba9d
--- /dev/null
+++ b/test/CodeGen/NVPTX/cttz.ll
@@ -0,0 +1,45 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+declare i16 @llvm.cttz.i16(i16, i1) readnone
+declare i32 @llvm.cttz.i32(i32, i1) readnone
+declare i64 @llvm.cttz.i64(i64, i1) readnone
+
+define i32 @myctpop(i32 %a) {
+; CHECK: popc.b32
+  %val = call i32 @llvm.cttz.i32(i32 %a, i1 false) readnone
+  ret i32 %val
+}
+
+define i16 @myctpop16(i16 %a) {
+; CHECK: popc.b32
+  %val = call i16 @llvm.cttz.i16(i16 %a, i1 false) readnone
+  ret i16 %val
+}
+
+define i64 @myctpop64(i64 %a) {
+; CHECK: popc.b64
+  %val = call i64 @llvm.cttz.i64(i64 %a, i1 false) readnone
+  ret i64 %val
+}
+
+
+define i32 @myctpop_2(i32 %a) {
+; CHECK: popc.b32
+  %val = call i32 @llvm.cttz.i32(i32 %a, i1 true) readnone
+  ret i32 %val
+}
+
+define i16 @myctpop16_2(i16 %a) {
+; CHECK: popc.b32
+  %val = call i16 @llvm.cttz.i16(i16 %a, i1 true) readnone
+  ret i16 %val
+}
+
+define i64 @myctpop64_2(i64 %a) {
+; CHECK: popc.b64
+  %val = call i64 @llvm.cttz.i64(i64 %a, i1 true) readnone
+  ret i64 %val
+}
diff --git a/test/CodeGen/NVPTX/fast-math.ll b/test/CodeGen/NVPTX/fast-math.ll
new file mode 100644
index 0000000..9da26ad
--- /dev/null
+++ b/test/CodeGen/NVPTX/fast-math.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+
+declare float @llvm.nvvm.sqrt.f(float)
+
+
+; CHECK: sqrt_div
+; CHECK: sqrt.rn.f32
+; CHECK: div.rn.f32
+define float @sqrt_div(float %a, float %b) {
+  %t1 = tail call float @llvm.nvvm.sqrt.f(float %a)
+  %t2 = fdiv float %t1, %b
+  ret float %t2
+}
+
+; CHECK: sqrt_div_fast
+; CHECK: sqrt.approx.f32
+; CHECK: div.approx.f32
+define float @sqrt_div_fast(float %a, float %b) #0 {
+  %t1 = tail call float @llvm.nvvm.sqrt.f(float %a)
+  %t2 = fdiv float %t1, %b
+  ret float %t2
+}
+
+
+; CHECK: fadd
+; CHECK: add.f32
+define float @fadd(float %a, float %b) {
+  %t1 = fadd float %a, %b
+  ret float %t1
+}
+
+; CHECK: fadd_ftz
+; CHECK: add.ftz.f32
+define float @fadd_ftz(float %a, float %b) #1 {
+  %t1 = fadd float %a, %b
+  ret float %t1
+}
+
+
+
+attributes #0 = { "unsafe-fp-math" = "true" }
+attributes #1 = { "nvptx-f32ftz" = "true" }
diff --git a/test/CodeGen/NVPTX/fp-literals.ll b/test/CodeGen/NVPTX/fp-literals.ll
new file mode 100644
index 0000000..0cc2413
--- /dev/null
+++ b/test/CodeGen/NVPTX/fp-literals.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+; Make sure we can properly differentiate between single-precision and
+; double-precision FP literals.
+
+; CHECK: myaddf
+; CHECK: add.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, 0f3F800000
+define float @myaddf(float %a) {
+  %ret = fadd float %a, 1.0
+  ret float %ret
+}
+
+; CHECK: myaddd
+; CHECK: add.f64 %fl{{[0-9]+}}, %fl{{[0-9]+}}, 0d3FF0000000000000
+define double @myaddd(double %a) {
+  %ret = fadd double %a, 1.0
+  ret double %ret
+}
diff --git a/test/CodeGen/NVPTX/generic-to-nvvm.ll b/test/CodeGen/NVPTX/generic-to-nvvm.ll
index c9cb2f7..2a52798 100644
--- a/test/CodeGen/NVPTX/generic-to-nvvm.ll
+++ b/test/CodeGen/NVPTX/generic-to-nvvm.ll
@@ -1,6 +1,7 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+target triple = "nvptx-nvidia-cuda"
 
 ; Ensure global variables in address space 0 are promoted to address space 1
 
diff --git a/test/CodeGen/NVPTX/i1-global.ll b/test/CodeGen/NVPTX/i1-global.ll
index 0595325..1dd8ae4 100644
--- a/test/CodeGen/NVPTX/i1-global.ll
+++ b/test/CodeGen/NVPTX/i1-global.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
-
+target triple = "nvptx-nvidia-cuda"
 
 ; CHECK: .visible .global .align 1 .u8 mypred
 @mypred = addrspace(1) global i1 true, align 1
diff --git a/test/CodeGen/NVPTX/i1-int-to-fp.ll b/test/CodeGen/NVPTX/i1-int-to-fp.ll
new file mode 100644
index 0000000..3979179
--- /dev/null
+++ b/test/CodeGen/NVPTX/i1-int-to-fp.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+; CHECK-LABEL: foo
+; CHECK: setp
+; CHECK: selp
+; CHECK: cvt.rn.f32.u32
+define float @foo(i1 %a) {
+  %ret = uitofp i1 %a to float
+  ret float %ret
+}
+
+; CHECK-LABEL: foo2
+; CHECK: setp
+; CHECK: selp
+; CHECK: cvt.rn.f32.s32
+define float @foo2(i1 %a) {
+  %ret = sitofp i1 %a to float
+  ret float %ret
+}
+
+; CHECK-LABEL: foo3
+; CHECK: setp
+; CHECK: selp
+; CHECK: cvt.rn.f64.u32
+define double @foo3(i1 %a) {
+  %ret = uitofp i1 %a to double
+  ret double %ret
+}
+
+; CHECK-LABEL: foo4
+; CHECK: setp
+; CHECK: selp
+; CHECK: cvt.rn.f64.s32
+define double @foo4(i1 %a) {
+  %ret = sitofp i1 %a to double
+  ret double %ret
+}
diff --git a/test/CodeGen/NVPTX/i1-param.ll b/test/CodeGen/NVPTX/i1-param.ll
index fabd61a..f4df874 100644
--- a/test/CodeGen/NVPTX/i1-param.ll
+++ b/test/CodeGen/NVPTX/i1-param.ll
@@ -1,6 +1,7 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+target triple = "nvptx-nvidia-cuda"
 
 ; Make sure predicate (i1) operands to kernels get expanded out to .u8
 
diff --git a/test/CodeGen/NVPTX/i8-param.ll b/test/CodeGen/NVPTX/i8-param.ll
new file mode 100644
index 0000000..84daa9f
--- /dev/null
+++ b/test/CodeGen/NVPTX/i8-param.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+; CHECK: .visible .func  (.param .b32 func_retval0) callee
+define i8 @callee(i8 %a) {
+; CHECK: ld.param.u8
+  %ret = add i8 %a, 42
+; CHECK: st.param.b32
+  ret i8 %ret
+}
+
+; CHECK: .visible .func caller
+define void @caller(i8* %a) {
+; CHECK: ld.u8
+  %val = load i8* %a
+  %ret = tail call i8 @callee(i8 %val)
+; CHECK: ld.param.b32
+  store i8 %ret, i8* %a
+  ret void
+}
+
+  
diff --git a/test/CodeGen/NVPTX/ld-addrspace.ll b/test/CodeGen/NVPTX/ld-addrspace.ll
index 3265868..133ef09 100644
--- a/test/CodeGen/NVPTX/ld-addrspace.ll
+++ b/test/CodeGen/NVPTX/ld-addrspace.ll
@@ -4,27 +4,27 @@
 
 ;; i8
 define i8 @ld_global_i8(i8 addrspace(1)* %ptr) {
-; PTX32: ld.global.u8 %rc{{[0-9]+}}, [%r{{[0-9]+}}]
+; PTX32: ld.global.u8 %r{{[0-9]+}}, [%r{{[0-9]+}}]
 ; PTX32: ret
-; PTX64: ld.global.u8 %rc{{[0-9]+}}, [%rl{{[0-9]+}}]
+; PTX64: ld.global.u8 %r{{[0-9]+}}, [%rl{{[0-9]+}}]
 ; PTX64: ret
   %a = load i8 addrspace(1)* %ptr
   ret i8 %a
 }
 
 define i8 @ld_shared_i8(i8 addrspace(3)* %ptr) {
-; PTX32: ld.shared.u8 %rc{{[0-9]+}}, [%r{{[0-9]+}}]
+; PTX32: ld.shared.u8 %r{{[0-9]+}}, [%r{{[0-9]+}}]
 ; PTX32: ret
-; PTX64: ld.shared.u8 %rc{{[0-9]+}}, [%rl{{[0-9]+}}]
+; PTX64: ld.shared.u8 %r{{[0-9]+}}, [%rl{{[0-9]+}}]
 ; PTX64: ret
   %a = load i8 addrspace(3)* %ptr
   ret i8 %a
 }
 
 define i8 @ld_local_i8(i8 addrspace(5)* %ptr) {
-; PTX32: ld.local.u8 %rc{{[0-9]+}}, [%r{{[0-9]+}}]
+; PTX32: ld.local.u8 %r{{[0-9]+}}, [%r{{[0-9]+}}]
 ; PTX32: ret
-; PTX64: ld.local.u8 %rc{{[0-9]+}}, [%rl{{[0-9]+}}]
+; PTX64: ld.local.u8 %r{{[0-9]+}}, [%rl{{[0-9]+}}]
 ; PTX64: ret
   %a = load i8 addrspace(5)* %ptr
   ret i8 %a
@@ -32,27 +32,27 @@ define i8 @ld_local_i8(i8 addrspace(5)* %ptr) {
 
 ;; i16
 define i16 @ld_global_i16(i16 addrspace(1)* %ptr) {
-; PTX32: ld.global.u16 %rs{{[0-9]+}}, [%r{{[0-9]+}}]
+; PTX32: ld.global.u16 %r{{[0-9]+}}, [%r{{[0-9]+}}]
 ; PTX32: ret
-; PTX64: ld.global.u16 %rs{{[0-9]+}}, [%rl{{[0-9]+}}]
+; PTX64: ld.global.u16 %r{{[0-9]+}}, [%rl{{[0-9]+}}]
 ; PTX64: ret
   %a = load i16 addrspace(1)* %ptr
   ret i16 %a
 }
 
 define i16 @ld_shared_i16(i16 addrspace(3)* %ptr) {
-; PTX32: ld.shared.u16 %rs{{[0-9]+}}, [%r{{[0-9]+}}]
+; PTX32: ld.shared.u16 %r{{[0-9]+}}, [%r{{[0-9]+}}]
 ; PTX32: ret
-; PTX64: ld.shared.u16 %rs{{[0-9]+}}, [%rl{{[0-9]+}}]
+; PTX64: ld.shared.u16 %r{{[0-9]+}}, [%rl{{[0-9]+}}]
 ; PTX64: ret
   %a = load i16 addrspace(3)* %ptr
   ret i16 %a
 }
 
 define i16 @ld_local_i16(i16 addrspace(5)* %ptr) {
-; PTX32: ld.local.u16 %rs{{[0-9]+}}, [%r{{[0-9]+}}]
+; PTX32: ld.local.u16 %r{{[0-9]+}}, [%r{{[0-9]+}}]
 ; PTX32: ret
-; PTX64: ld.local.u16 %rs{{[0-9]+}}, [%rl{{[0-9]+}}]
+; PTX64: ld.local.u16 %r{{[0-9]+}}, [%rl{{[0-9]+}}]
 ; PTX64: ret
   %a = load i16 addrspace(5)* %ptr
   ret i16 %a
diff --git a/test/CodeGen/NVPTX/ld-generic.ll b/test/CodeGen/NVPTX/ld-generic.ll
index 81a5216..3728268 100644
--- a/test/CodeGen/NVPTX/ld-generic.ll
+++ b/test/CodeGen/NVPTX/ld-generic.ll
@@ -4,9 +4,9 @@
 
 ;; i8
 define i8 @ld_global_i8(i8 addrspace(0)* %ptr) {
-; PTX32: ld.u8 %rc{{[0-9]+}}, [%r{{[0-9]+}}]
+; PTX32: ld.u8 %r{{[0-9]+}}, [%r{{[0-9]+}}]
 ; PTX32: ret
-; PTX64: ld.u8 %rc{{[0-9]+}}, [%rl{{[0-9]+}}]
+; PTX64: ld.u8 %r{{[0-9]+}}, [%rl{{[0-9]+}}]
 ; PTX64: ret
   %a = load i8 addrspace(0)* %ptr
   ret i8 %a
@@ -14,9 +14,9 @@ define i8 @ld_global_i8(i8 addrspace(0)* %ptr) {
 
 ;; i16
 define i16 @ld_global_i16(i16 addrspace(0)* %ptr) {
-; PTX32: ld.u16 %rs{{[0-9]+}}, [%r{{[0-9]+}}]
+; PTX32: ld.u16 %r{{[0-9]+}}, [%r{{[0-9]+}}]
 ; PTX32: ret
-; PTX64: ld.u16 %rs{{[0-9]+}}, [%rl{{[0-9]+}}]
+; PTX64: ld.u16 %r{{[0-9]+}}, [%rl{{[0-9]+}}]
 ; PTX64: ret
   %a = load i16 addrspace(0)* %ptr
   ret i16 %a
diff --git a/test/CodeGen/NVPTX/ldu-i8.ll b/test/CodeGen/NVPTX/ldu-i8.ll
new file mode 100644
index 0000000..81a82b2
--- /dev/null
+++ b/test/CodeGen/NVPTX/ldu-i8.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+declare i8 @llvm.nvvm.ldu.global.i.i8(i8*)
+
+define i8 @foo(i8* %a) {
+; Ensure we properly truncate off the high-order 24 bits
+; CHECK:        ldu.global.u8
+; CHECK:        cvt.u32.u16
+; CHECK:        and.b32         %r{{[0-9]+}}, %r{{[0-9]+}}, 255
+  %val = tail call i8 @llvm.nvvm.ldu.global.i.i8(i8* %a)
+  ret i8 %val
+}
diff --git a/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll b/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
new file mode 100644
index 0000000..26cadc4
--- /dev/null
+++ b/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+
+define void @reg_plus_offset(i32* %a) {
+; CHECK:        ldu.global.u32  %r{{[0-9]+}}, [%r{{[0-9]+}}+32];
+; CHECK:        ldu.global.u32  %r{{[0-9]+}}, [%r{{[0-9]+}}+36];
+  %p2 = getelementptr i32* %a, i32 8
+  %t1 = call i32 @llvm.nvvm.ldu.global.i.i32(i32* %p2), !align !1
+  %p3 = getelementptr i32* %a, i32 9
+  %t2 = call i32 @llvm.nvvm.ldu.global.i.i32(i32* %p3), !align !1
+  %t3 = mul i32 %t1, %t2
+  store i32 %t3, i32* %a
+  ret void
+}
+
+!1 = metadata !{ i32 4 }
+
+declare i32 @llvm.nvvm.ldu.global.i.i32(i32*)
+declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
diff --git a/test/CodeGen/NVPTX/load-sext-i1.ll b/test/CodeGen/NVPTX/load-sext-i1.ll
index c9b2e97..d836740 100644
--- a/test/CodeGen/NVPTX/load-sext-i1.ll
+++ b/test/CodeGen/NVPTX/load-sext-i1.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
-
+target triple = "nvptx-nvidia-cuda"
 
 define void @main(i1* %a1, i32 %a2, i32* %arg3) {
 ; CHECK: ld.u8
diff --git a/test/CodeGen/NVPTX/local-stack-frame.ll b/test/CodeGen/NVPTX/local-stack-frame.ll
new file mode 100644
index 0000000..178dff1
--- /dev/null
+++ b/test/CodeGen/NVPTX/local-stack-frame.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
+
+; Ensure we access the local stack properly
+
+; PTX32:        mov.u32         %r{{[0-9]+}}, __local_depot{{[0-9]+}};
+; PTX32:        cvta.local.u32  %SP, %r{{[0-9]+}};
+; PTX32:        ld.param.u32    %r{{[0-9]+}}, [foo_param_0];
+; PTX32:        st.u32  [%SP+0], %r{{[0-9]+}};
+; PTX64:        mov.u64         %rl{{[0-9]+}}, __local_depot{{[0-9]+}};
+; PTX64:        cvta.local.u64  %SP, %rl{{[0-9]+}};
+; PTX64:        ld.param.u32    %r{{[0-9]+}}, [foo_param_0];
+; PTX64:        st.u32  [%SP+0], %r{{[0-9]+}};
+define void @foo(i32 %a) {
+  %local = alloca i32, align 4
+  store i32 %a, i32* %local
+  ret void
+}
diff --git a/test/CodeGen/NVPTX/module-inline-asm.ll b/test/CodeGen/NVPTX/module-inline-asm.ll
new file mode 100644
index 0000000..cdbcf20
--- /dev/null
+++ b/test/CodeGen/NVPTX/module-inline-asm.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+; CHECK: .global .b32 val;
+module asm ".global .b32 val;"
+
+define void @foo() {
+  ret void
+}
diff --git a/test/CodeGen/NVPTX/pr13291-i1-store.ll b/test/CodeGen/NVPTX/pr13291-i1-store.ll
index 779f779..e7a81be 100644
--- a/test/CodeGen/NVPTX/pr13291-i1-store.ll
+++ b/test/CodeGen/NVPTX/pr13291-i1-store.ll
@@ -2,22 +2,22 @@
 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
 
 define ptx_kernel void @t1(i1* %a) {
-; PTX32:      mov.u16 %rc{{[0-9]+}}, 0;
-; PTX32-NEXT: st.u8 [%r{{[0-9]+}}], %rc{{[0-9]+}};
-; PTX64:      mov.u16 %rc{{[0-9]+}}, 0;
-; PTX64-NEXT: st.u8 [%rl{{[0-9]+}}], %rc{{[0-9]+}};
+; PTX32:      mov.u16 %rs{{[0-9]+}}, 0;
+; PTX32-NEXT: st.u8 [%r{{[0-9]+}}], %rs{{[0-9]+}};
+; PTX64:      mov.u16 %rs{{[0-9]+}}, 0;
+; PTX64-NEXT: st.u8 [%rl{{[0-9]+}}], %rs{{[0-9]+}};
   store i1 false, i1* %a
   ret void
 }
 
 
 define ptx_kernel void @t2(i1* %a, i8* %b) {
-; PTX32: ld.u8 %rc{{[0-9]+}}, [%r{{[0-9]+}}]
-; PTX32: and.b16 temp, %rc{{[0-9]+}}, 1;
-; PTX32: setp.b16.eq %p{{[0-9]+}}, temp, 1;
-; PTX64: ld.u8 %rc{{[0-9]+}}, [%rl{{[0-9]+}}]
-; PTX64: and.b16 temp, %rc{{[0-9]+}}, 1;
-; PTX64: setp.b16.eq %p{{[0-9]+}}, temp, 1;
+; PTX32: ld.u8 %rs{{[0-9]+}}, [%r{{[0-9]+}}]
+; PTX32: and.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, 1;
+; PTX32: setp.eq.b16 %p{{[0-9]+}}, %rs{{[0-9]+}}, 1;
+; PTX64: ld.u8 %rs{{[0-9]+}}, [%rl{{[0-9]+}}]
+; PTX64: and.b16 %rs{{[0-9]+}}, %rs{{[0-9]+}}, 1;
+; PTX64: setp.eq.b16 %p{{[0-9]+}}, %rs{{[0-9]+}}, 1;
 
   %t1 = load i1* %a
   %t2 = select i1 %t1, i8 1, i8 2
diff --git a/test/CodeGen/NVPTX/refl1.ll b/test/CodeGen/NVPTX/refl1.ll
index 5a9dac1..4aeff09 100644
--- a/test/CodeGen/NVPTX/refl1.ll
+++ b/test/CodeGen/NVPTX/refl1.ll
@@ -1,4 +1,6 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target triple = "nvptx-nvidia-cuda"
 
 ; Function Attrs: nounwind
 ; CHECK: .entry foo
diff --git a/test/CodeGen/NVPTX/rsqrt.ll b/test/CodeGen/NVPTX/rsqrt.ll
new file mode 100644
index 0000000..3a52a49
--- /dev/null
+++ b/test/CodeGen/NVPTX/rsqrt.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-prec-divf32=1 -nvptx-prec-sqrtf32=0 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+declare float @llvm.nvvm.sqrt.f(float)
+
+define float @foo(float %a) {
+; CHECK: rsqrt.approx.f32
+  %val = tail call float @llvm.nvvm.sqrt.f(float %a)
+  %ret = fdiv float 1.0, %val
+  ret float %ret
+}
+  
diff --git a/test/CodeGen/NVPTX/sext-in-reg.ll b/test/CodeGen/NVPTX/sext-in-reg.ll
new file mode 100644
index 0000000..b516dfa
--- /dev/null
+++ b/test/CodeGen/NVPTX/sext-in-reg.ll
@@ -0,0 +1,111 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+
+define void @one(i64 %a, i64 %b, i64* %p1, i64* %p2) {
+; CHECK: cvt.s64.s8
+; CHECK: cvt.s64.s8
+entry:
+  %sext = shl i64 %a, 56
+  %conv1 = ashr exact i64 %sext, 56
+  %sext1 = shl i64 %b, 56
+  %conv4 = ashr exact i64 %sext1, 56
+  %shr = ashr i64 %a, 16
+  %shr9 = ashr i64 %b, 16
+  %add = add nsw i64 %conv4, %conv1
+  store i64 %add, i64* %p1, align 8
+  %add17 = add nsw i64 %shr9, %shr
+  store i64 %add17, i64* %p2, align 8
+  ret void
+}
+
+
+define void @two(i64 %a, i64 %b, i64* %p1, i64* %p2) {
+entry:
+; CHECK: cvt.s64.s32
+; CHECK: cvt.s64.s32
+  %sext = shl i64 %a, 32
+  %conv1 = ashr exact i64 %sext, 32
+  %sext1 = shl i64 %b, 32
+  %conv4 = ashr exact i64 %sext1, 32
+  %shr = ashr i64 %a, 16
+  %shr9 = ashr i64 %b, 16
+  %add = add nsw i64 %conv4, %conv1
+  store i64 %add, i64* %p1, align 8
+  %add17 = add nsw i64 %shr9, %shr
+  store i64 %add17, i64* %p2, align 8
+  ret void
+}
+
+
+define void @three(i64 %a, i64 %b, i64* %p1, i64* %p2) {
+entry:
+; CHECK: cvt.s64.s16
+; CHECK: cvt.s64.s16
+  %sext = shl i64 %a, 48
+  %conv1 = ashr exact i64 %sext, 48
+  %sext1 = shl i64 %b, 48
+  %conv4 = ashr exact i64 %sext1, 48
+  %shr = ashr i64 %a, 16
+  %shr9 = ashr i64 %b, 16
+  %add = add nsw i64 %conv4, %conv1
+  store i64 %add, i64* %p1, align 8
+  %add17 = add nsw i64 %shr9, %shr
+  store i64 %add17, i64* %p2, align 8
+  ret void
+}
+
+
+define void @four(i32 %a, i32 %b, i32* %p1, i32* %p2) {
+entry:
+; CHECK: cvt.s32.s8
+; CHECK: cvt.s32.s8
+  %sext = shl i32 %a, 24
+  %conv1 = ashr exact i32 %sext, 24
+  %sext1 = shl i32 %b, 24
+  %conv4 = ashr exact i32 %sext1, 24
+  %shr = ashr i32 %a, 16
+  %shr9 = ashr i32 %b, 16
+  %add = add nsw i32 %conv4, %conv1
+  store i32 %add, i32* %p1, align 4
+  %add17 = add nsw i32 %shr9, %shr
+  store i32 %add17, i32* %p2, align 4
+  ret void
+}
+
+
+define void @five(i32 %a, i32 %b, i32* %p1, i32* %p2) {
+entry:
+; CHECK: cvt.s32.s16
+; CHECK: cvt.s32.s16
+  %sext = shl i32 %a, 16
+  %conv1 = ashr exact i32 %sext, 16
+  %sext1 = shl i32 %b, 16
+  %conv4 = ashr exact i32 %sext1, 16
+  %shr = ashr i32 %a, 16
+  %shr9 = ashr i32 %b, 16
+  %add = add nsw i32 %conv4, %conv1
+  store i32 %add, i32* %p1, align 4
+  %add17 = add nsw i32 %shr9, %shr
+  store i32 %add17, i32* %p2, align 4
+  ret void
+}
+
+
+define void @six(i16 %a, i16 %b, i16* %p1, i16* %p2) {
+entry:
+; CHECK: cvt.s16.s8
+; CHECK: cvt.s16.s8
+  %sext = shl i16 %a, 8
+  %conv1 = ashr exact i16 %sext, 8
+  %sext1 = shl i16 %b, 8
+  %conv4 = ashr exact i16 %sext1, 8
+  %shr = ashr i16 %a, 8
+  %shr9 = ashr i16 %b, 8
+  %add = add nsw i16 %conv4, %conv1
+  store i16 %add, i16* %p1, align 4
+  %add17 = add nsw i16 %shr9, %shr
+  store i16 %add17, i16* %p2, align 4
+  ret void
+}
diff --git a/test/CodeGen/NVPTX/sext-params.ll b/test/CodeGen/NVPTX/sext-params.ll
new file mode 100644
index 0000000..a559630
--- /dev/null
+++ b/test/CodeGen/NVPTX/sext-params.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+
+define i8 @foo(i8 signext %a) {
+; CHECK: ld.param.s8
+  %ret = add i8 %a, 3
+  ret i8 %ret
+}
+
+define i8 @bar(i8 zeroext %a) {
+; CHECK: ld.param.u8
+  %ret = add i8 %a, 3
+  ret i8 %ret
+}
diff --git a/test/CodeGen/NVPTX/st-addrspace.ll b/test/CodeGen/NVPTX/st-addrspace.ll
index 0b26d80..68c09fe 100644
--- a/test/CodeGen/NVPTX/st-addrspace.ll
+++ b/test/CodeGen/NVPTX/st-addrspace.ll
@@ -5,27 +5,27 @@
 ;; i8
 
 define void @st_global_i8(i8 addrspace(1)* %ptr, i8 %a) {
-; PTX32: st.global.u8 [%r{{[0-9]+}}], %rc{{[0-9]+}}
+; PTX32: st.global.u8 [%r{{[0-9]+}}], %rs{{[0-9]+}}
 ; PTX32: ret
-; PTX64: st.global.u8 [%rl{{[0-9]+}}], %rc{{[0-9]+}}
+; PTX64: st.global.u8 [%rl{{[0-9]+}}], %rs{{[0-9]+}}
 ; PTX64: ret
   store i8 %a, i8 addrspace(1)* %ptr
   ret void
 }
 
 define void @st_shared_i8(i8 addrspace(3)* %ptr, i8 %a) {
-; PTX32: st.shared.u8 [%r{{[0-9]+}}], %rc{{[0-9]+}}
+; PTX32: st.shared.u8 [%r{{[0-9]+}}], %rs{{[0-9]+}}
 ; PTX32: ret
-; PTX64: st.shared.u8 [%rl{{[0-9]+}}], %rc{{[0-9]+}}
+; PTX64: st.shared.u8 [%rl{{[0-9]+}}], %rs{{[0-9]+}}
 ; PTX64: ret
   store i8 %a, i8 addrspace(3)* %ptr
   ret void
 }
 
 define void @st_local_i8(i8 addrspace(5)* %ptr, i8 %a) {
-; PTX32: st.local.u8 [%r{{[0-9]+}}], %rc{{[0-9]+}}
+; PTX32: st.local.u8 [%r{{[0-9]+}}], %rs{{[0-9]+}}
 ; PTX32: ret
-; PTX64: st.local.u8 [%rl{{[0-9]+}}], %rc{{[0-9]+}}
+; PTX64: st.local.u8 [%rl{{[0-9]+}}], %rs{{[0-9]+}}
 ; PTX64: ret
   store i8 %a, i8 addrspace(5)* %ptr
   ret void
diff --git a/test/CodeGen/NVPTX/st-generic.ll b/test/CodeGen/NVPTX/st-generic.ll
index 59a1fe0..b9c616f 100644
--- a/test/CodeGen/NVPTX/st-generic.ll
+++ b/test/CodeGen/NVPTX/st-generic.ll
@@ -5,9 +5,9 @@
 ;; i8
 
 define void @st_global_i8(i8 addrspace(0)* %ptr, i8 %a) {
-; PTX32: st.u8 [%r{{[0-9]+}}], %rc{{[0-9]+}}
+; PTX32: st.u8 [%r{{[0-9]+}}], %rs{{[0-9]+}}
 ; PTX32: ret
-; PTX64: st.u8 [%rl{{[0-9]+}}], %rc{{[0-9]+}}
+; PTX64: st.u8 [%rl{{[0-9]+}}], %rs{{[0-9]+}}
 ; PTX64: ret
   store i8 %a, i8 addrspace(0)* %ptr
   ret void
diff --git a/test/CodeGen/NVPTX/vec-param-load.ll b/test/CodeGen/NVPTX/vec-param-load.ll
new file mode 100644
index 0000000..a384348
--- /dev/null
+++ b/test/CodeGen/NVPTX/vec-param-load.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
+
+
+define <16 x float> @foo(<16 x float> %a) {
+; Make sure we index into vectors properly
+; CHECK: ld.param.v4.f32         {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}, [foo_param_0];
+; CHECK: ld.param.v4.f32         {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}, [foo_param_0+16];
+; CHECK: ld.param.v4.f32         {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}, [foo_param_0+32];
+; CHECK: ld.param.v4.f32         {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}, [foo_param_0+48];
+  ret <16 x float> %a
+}
diff --git a/test/CodeGen/NVPTX/vector-args.ll b/test/CodeGen/NVPTX/vector-args.ll
index 80deae4..c6c8e73 100644
--- a/test/CodeGen/NVPTX/vector-args.ll
+++ b/test/CodeGen/NVPTX/vector-args.ll
@@ -4,8 +4,7 @@
 define float @foo(<2 x float> %a) {
 ; CHECK: .func (.param .b32 func_retval0) foo
 ; CHECK: .param .align 8 .b8 foo_param_0[8]
-; CHECK: ld.param.f32 %f{{[0-9]+}}
-; CHECK: ld.param.f32 %f{{[0-9]+}}
+; CHECK: ld.param.v2.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}}
   %t1 = fmul <2 x float> %a, %a
   %t2 = extractelement <2 x float> %t1, i32 0
   %t3 = extractelement <2 x float> %t1, i32 1
@@ -17,11 +16,20 @@ define float @foo(<2 x float> %a) {
 define float @bar(<4 x float> %a) {
 ; CHECK: .func (.param .b32 func_retval0) bar
 ; CHECK: .param .align 16 .b8 bar_param_0[16]
-; CHECK: ld.param.f32 %f{{[0-9]+}}
-; CHECK: ld.param.f32 %f{{[0-9]+}}
+; CHECK: ld.param.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
   %t1 = fmul <4 x float> %a, %a
   %t2 = extractelement <4 x float> %t1, i32 0
   %t3 = extractelement <4 x float> %t1, i32 1
   %t4 = fadd float %t2, %t3
   ret float %t4
 }
+
+
+define <4 x float> @baz(<4 x float> %a) {
+; CHECK: .func  (.param .align 16 .b8 func_retval0[16]) baz
+; CHECK: .param .align 16 .b8 baz_param_0[16]
+; CHECK: ld.param.v4.f32 {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
+; CHECK: st.param.v4.f32 [func_retval0+0], {%f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}, %f{{[0-9]+}}}
+  %t1 = fmul <4 x float> %a, %a
+  ret <4 x float> %t1
+}
diff --git a/test/CodeGen/NVPTX/vector-stores.ll b/test/CodeGen/NVPTX/vector-stores.ll
new file mode 100644
index 0000000..4941812
--- /dev/null
+++ b/test/CodeGen/NVPTX/vector-stores.ll
@@ -0,0 +1,30 @@
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+
+; CHECK: .visible .func foo1
+; CHECK: st.v2.f32
+define void @foo1(<2 x float> %val, <2 x float>* %ptr) {
+  store <2 x float> %val, <2 x float>* %ptr
+  ret void
+}
+
+; CHECK: .visible .func foo2
+; CHECK: st.v4.f32
+define void @foo2(<4 x float> %val, <4 x float>* %ptr) {
+  store <4 x float> %val, <4 x float>* %ptr
+  ret void
+}
+
+; CHECK: .visible .func foo3
+; CHECK: st.v2.u32
+define void @foo3(<2 x i32> %val, <2 x i32>* %ptr) {
+  store <2 x i32> %val, <2 x i32>* %ptr
+  ret void
+}
+
+; CHECK: .visible .func foo4
+; CHECK: st.v4.u32
+define void @foo4(<4 x i32> %val, <4 x i32>* %ptr) {
+  store <4 x i32> %val, <4 x i32>* %ptr
+  ret void
+}
+
diff --git a/test/CodeGen/PowerPC/2009-09-18-carrybit.ll b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll
index 6c23a61..8d5ea8a 100644
--- a/test/CodeGen/PowerPC/2009-09-18-carrybit.ll
+++ b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll
@@ -5,7 +5,7 @@ target triple = "powerpc-apple-darwin9.6"
 
 define i64 @foo(i64 %r.0.ph, i64 %q.0.ph, i32 %sr1.1.ph) nounwind {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: subfc
 ; CHECK: subfe
 ; CHECK: subfc
diff --git a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
index d1a3c9f..a25ce07 100644
--- a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
+++ b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
@@ -6,7 +6,7 @@ target triple = "powerpc-apple-darwin9.8"
 define i32 @main() nounwind {
 entry:
 ; Make sure we're generating references using the red zone
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK: stw r2, -12(r1)
   %retval = alloca i32
   %0 = alloca i32
diff --git a/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll b/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll
index a18829e..b1cbb36 100644
--- a/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll
+++ b/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll
@@ -9,7 +9,7 @@ entry:
   store i64 %z2, i64* %xx, align 4
   ret void
 
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: sldi {{.*}}, {{.*}}, 32
 ; Note: it's okay if someday CodeGen gets smart enough to optimize out
 ; the shift.
diff --git a/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.ll b/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.ll
new file mode 100644
index 0000000..635062b
--- /dev/null
+++ b/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -verify-machineinstrs | FileCheck %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+@g_51 = external global [8 x i32], align 4
+
+; CHECK: func_7
+
+; Function Attrs: nounwind
+define fastcc void @func_7() #0 {
+entry:
+  %arrayidx638 = getelementptr inbounds [3 x [1 x i32]]* undef, i64 0, i64 1, i64 0
+  br i1 undef, label %for.cond940, label %if.end1018
+
+for.cond940:                                      ; preds = %for.cond940, %if.else876
+  %l_655.1 = phi i32* [ getelementptr inbounds ([8 x i32]* @g_51, i64 0, i64 6), %entry ], [ %l_654.0, %for.cond940 ]
+  %l_654.0 = phi i32* [ null, %entry ], [ %arrayidx638, %for.cond940 ]
+  %exitcond = icmp eq i32 undef, 20
+  br i1 %exitcond, label %if.end1018, label %for.cond940
+
+if.end1018:                                       ; preds = %for.end957, %for.end834
+  %l_655.3.ph33 = phi i32* [ %l_655.1, %for.cond940 ], [ getelementptr inbounds ([8 x i32]* @g_51, i64 0, i64 6), %entry ]
+  store i32 0, i32* %l_655.3.ph33, align 4
+  ret void
+}
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/CodeGen/PowerPC/addc.ll b/test/CodeGen/PowerPC/addc.ll
index 8c928ce..500d126 100644
--- a/test/CodeGen/PowerPC/addc.ll
+++ b/test/CodeGen/PowerPC/addc.ll
@@ -5,7 +5,7 @@ define i64 @add_ll(i64 %a, i64 %b) nounwind {
 entry:
         %tmp.2 = add i64 %b, %a         ; <i64> [#uses=1]
         ret i64 %tmp.2
-; CHECK: add_ll:
+; CHECK-LABEL: add_ll:
 ; CHECK: addc r4, r6, r4
 ; CHECK: adde r3, r5, r3
 ; CHECK: blr
@@ -15,7 +15,7 @@ define i64 @add_l_5(i64 %a) nounwind {
 entry:
         %tmp.1 = add i64 %a, 5          ; <i64> [#uses=1]
         ret i64 %tmp.1
-; CHECK: add_l_5:
+; CHECK-LABEL: add_l_5:
 ; CHECK: addic r4, r4, 5
 ; CHECK: addze r3, r3
 ; CHECK: blr
@@ -25,7 +25,7 @@ define i64 @add_l_m5(i64 %a) nounwind {
 entry:
         %tmp.1 = add i64 %a, -5         ; <i64> [#uses=1]
         ret i64 %tmp.1
-; CHECK: add_l_m5:
+; CHECK-LABEL: add_l_m5:
 ; CHECK: addic r4, r4, -5
 ; CHECK: addme r3, r3
 ; CHECK: blr
diff --git a/test/CodeGen/PowerPC/altivec-ord.ll b/test/CodeGen/PowerPC/altivec-ord.ll
new file mode 100644
index 0000000..6aea843
--- /dev/null
+++ b/test/CodeGen/PowerPC/altivec-ord.ll
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
+target triple = "powerpc64-unknown-linux-gnu"
+
+define <4 x i16> @test(<4 x float> %f, <4 x float> %g) {
+entry:
+	%r = fcmp ord <4 x float> %f, %g
+	%s = sext <4 x i1> %r to <4 x i16>
+	ret <4 x i16> %s
+}
+
+define <4 x i16> @test2(<4 x float> %f, <4 x float> %g) {
+entry:
+	%r = fcmp one <4 x float> %f, %g
+	%s = sext <4 x i1> %r to <4 x i16>
+	ret <4 x i16> %s
+}
+
diff --git a/test/CodeGen/PowerPC/anon_aggr.ll b/test/CodeGen/PowerPC/anon_aggr.ll
index 78c0911..1525e05 100644
--- a/test/CodeGen/PowerPC/anon_aggr.ll
+++ b/test/CodeGen/PowerPC/anon_aggr.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s
 ; RUN: llc -O0 -mcpu=g4 -mtriple=powerpc-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN32 %s
 ; RUN: llc -O0 -mcpu=ppc970 -mtriple=powerpc64-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN64 %s
 
@@ -20,10 +20,10 @@ unequal:
   ret i8* %ptr
 }
 
-; CHECK: func1:
+; CHECK-LABEL: func1:
 ; CHECK: cmpld {{[0-9]+}}, 4, 5
-; CHECK: std 4, -[[OFFSET1:[0-9]+]]
-; CHECK: std 5, -[[OFFSET2:[0-9]+]]
+; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]]
+; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]]
 ; CHECK: ld 3, -[[OFFSET1]](1)
 ; CHECK: ld 3, -[[OFFSET2]](1)
 
@@ -61,12 +61,12 @@ unequal:
   ret i8* %array2_ptr
 }
 
-; CHECK: func2:
+; CHECK-LABEL: func2:
 ; CHECK: addi [[REG1:[0-9]+]], 1, 64
 ; CHECK: ld [[REG2:[0-9]+]], 8([[REG1]])
 ; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]]
-; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]]
-; CHECK: std 4, -[[OFFSET2:[0-9]+]]
+; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]]
+; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]]
 ; CHECK: ld 3, -[[OFFSET2]](1)
 ; CHECK: ld 3, -[[OFFSET1]](1)
 
@@ -107,7 +107,7 @@ unequal:
   ret i8* %array2_ptr
 }
 
-; CHECK: func3:
+; CHECK-LABEL: func3:
 ; CHECK: addi [[REG1:[0-9]+]], 1, 64
 ; CHECK: addi [[REG2:[0-9]+]], 1, 48
 ; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]])
@@ -156,7 +156,7 @@ unequal:
   ret i8* %array2_ptr
 }
 
-; CHECK: func4:
+; CHECK-LABEL: func4:
 ; CHECK: addi [[REG1:[0-9]+]], 1, 128
 ; CHECK: ld [[REG2:[0-9]+]], 120(1)
 ; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]])
diff --git a/test/CodeGen/PowerPC/ashr-neg1.ll b/test/CodeGen/PowerPC/ashr-neg1.ll
new file mode 100644
index 0000000..28e74f4
--- /dev/null
+++ b/test/CodeGen/PowerPC/ashr-neg1.ll
@@ -0,0 +1,18 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
+target triple = "powerpc64-unknown-linux-gnu"
+
+define void @autogen_SD30723(i32) {
+BB:
+  br label %CF80
+
+CF80:                                             ; preds = %CF80, %BB
+  %B = ashr i32 %0, -1
+  br i1 undef, label %CF80, label %CF84
+
+CF84:                                             ; preds = %CF84, %CF80
+  %Cmp62 = icmp sge i32 undef, %B
+  br i1 %Cmp62, label %CF84, label %CF85
+
+CF85:                                             ; preds = %CF85, %CF84
+  br label %CF85
+}
diff --git a/test/CodeGen/PowerPC/asm-dialect.ll b/test/CodeGen/PowerPC/asm-dialect.ll
new file mode 100644
index 0000000..e8fd251
--- /dev/null
+++ b/test/CodeGen/PowerPC/asm-dialect.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-apple-darwin | FileCheck %s
+
+; This test verifies that we choose "assembler variant 1" (which GCC
+; uses for "new-style mnemonics" as opposed to POWER mnemonics) when
+; processing multi-variant inline asm statements, on all subtargets.
+
+; CHECK: subfe
+; CHECK-NOT: sfe
+
+define i32 @test(i32 %in1, i32 %in2) {
+entry:
+  %0 = tail call i32 asm "$(sfe$|subfe$) $0,$1,$2", "=r,r,r"(i32 %in1, i32 %in2)
+  ret i32 %0
+}
+
diff --git a/test/CodeGen/PowerPC/atomic-1.ll b/test/CodeGen/PowerPC/atomic-1.ll
index 838db20..1737916 100644
--- a/test/CodeGen/PowerPC/atomic-1.ll
+++ b/test/CodeGen/PowerPC/atomic-1.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 |  FileCheck %s
 
 define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind {
-; CHECK: exchange_and_add:
+; CHECK-LABEL: exchange_and_add:
 ; CHECK: lwarx {{r[0-9]+}}, 0, {{r[0-9]+}}
   %tmp = atomicrmw add i32* %mem, i32 %val monotonic
 ; CHECK: stwcx. {{r[0-9]+}}, 0, {{r[0-9]+}}
@@ -9,7 +9,7 @@ define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind {
 }
 
 define i32 @exchange_and_cmp(i32* %mem) nounwind {
-; CHECK: exchange_and_cmp:
+; CHECK-LABEL: exchange_and_cmp:
 ; CHECK: lwarx
   %tmp = cmpxchg i32* %mem, i32 0, i32 1 monotonic
 ; CHECK: stwcx.
@@ -18,7 +18,7 @@ define i32 @exchange_and_cmp(i32* %mem) nounwind {
 }
 
 define i32 @exchange(i32* %mem, i32 %val) nounwind {
-; CHECK: exchange:
+; CHECK-LABEL: exchange:
 ; CHECK: lwarx
   %tmp = atomicrmw xchg i32* %mem, i32 1 monotonic
 ; CHECK: stwcx.
diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll
index 40b4a2e..e56a779 100644
--- a/test/CodeGen/PowerPC/atomic-2.ll
+++ b/test/CodeGen/PowerPC/atomic-2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=ppc64 | FileCheck %s
 
 define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
-; CHECK: exchange_and_add:
+; CHECK-LABEL: exchange_and_add:
 ; CHECK: ldarx
   %tmp = atomicrmw add i64* %mem, i64 %val monotonic
 ; CHECK: stdcx.
@@ -9,7 +9,7 @@ define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
 }
 
 define i64 @exchange_and_cmp(i64* %mem) nounwind {
-; CHECK: exchange_and_cmp:
+; CHECK-LABEL: exchange_and_cmp:
 ; CHECK: ldarx
   %tmp = cmpxchg i64* %mem, i64 0, i64 1 monotonic
 ; CHECK: stdcx.
@@ -18,7 +18,7 @@ define i64 @exchange_and_cmp(i64* %mem) nounwind {
 }
 
 define i64 @exchange(i64* %mem, i64 %val) nounwind {
-; CHECK: exchange:
+; CHECK-LABEL: exchange:
 ; CHECK: ldarx
   %tmp = atomicrmw xchg i64* %mem, i64 1 monotonic
 ; CHECK: stdcx.
diff --git a/test/CodeGen/PowerPC/bv-pres-v8i1.ll b/test/CodeGen/PowerPC/bv-pres-v8i1.ll
new file mode 100644
index 0000000..5bf84ed
--- /dev/null
+++ b/test/CodeGen/PowerPC/bv-pres-v8i1.ll
@@ -0,0 +1,39 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
+target triple = "powerpc64-unknown-linux-gnu"
+
+define void @autogen_SD70() {
+BB:
+  br label %CF78
+
+CF78:                                             ; preds = %CF87, %CF78, %BB
+  br i1 undef, label %CF78, label %CF87
+
+CF87:                                             ; preds = %CF78
+  %Cmp19 = icmp sge <8 x i1> zeroinitializer, zeroinitializer
+  %Cmp26 = icmp slt i32 -1, undef
+  br i1 %Cmp26, label %CF78, label %CF79
+
+CF79:                                             ; preds = %CF79, %CF87
+  br i1 undef, label %CF79, label %CF82
+
+CF82:                                             ; preds = %CF82, %CF79
+  br i1 undef, label %CF82, label %CF84
+
+CF84:                                             ; preds = %CF82
+  br label %CF
+
+CF:                                               ; preds = %CF88, %CF, %CF84
+  br i1 undef, label %CF, label %CF85
+
+CF85:                                             ; preds = %CF85, %CF
+  %I52 = insertelement <8 x i1> %Cmp19, i1 %Cmp26, i32 6
+  %Cmp61 = icmp ult i32 477567, undef
+  br i1 %Cmp61, label %CF85, label %CF88
+
+CF88:                                             ; preds = %CF85
+  %E63 = extractelement <8 x i1> %I52, i32 5
+  br i1 %E63, label %CF, label %CF80
+
+CF80:                                             ; preds = %CF80, %CF88
+  br label %CF80
+}
diff --git a/test/CodeGen/PowerPC/bv-widen-undef.ll b/test/CodeGen/PowerPC/bv-widen-undef.ll
new file mode 100644
index 0000000..9e58f0d
--- /dev/null
+++ b/test/CodeGen/PowerPC/bv-widen-undef.ll
@@ -0,0 +1,23 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
+target triple = "powerpc64-unknown-linux-gnu"
+
+define void @autogen_SD4357(i8) {
+BB:
+  br label %CF
+
+CF:                                               ; preds = %CF, %BB
+  br i1 undef, label %CF, label %CF77
+
+CF77:                                             ; preds = %CF81, %CF77, %CF
+  %Shuff12 = shufflevector <2 x i8> <i8 -1, i8 -1>, <2 x i8> <i8 -1, i8 -1>, <2 x i32> <i32 0, i32 undef>
+  br i1 undef, label %CF77, label %CF80
+
+CF80:                                             ; preds = %CF80, %CF77
+  %B21 = mul <2 x i8> %Shuff12, <i8 -1, i8 -1>
+  %Cmp24 = fcmp une ppc_fp128 0xM00000000000000000000000000000000, 0xM00000000000000000000000000000000
+  br i1 %Cmp24, label %CF80, label %CF81
+
+CF81:                                             ; preds = %CF80
+  %I36 = insertelement <2 x i8> %B21, i8 %0, i32 0
+  br label %CF77
+}
diff --git a/test/CodeGen/PowerPC/complex-return.ll b/test/CodeGen/PowerPC/complex-return.ll
index f12152f..3eb30e9 100644
--- a/test/CodeGen/PowerPC/complex-return.ll
+++ b/test/CodeGen/PowerPC/complex-return.ll
@@ -23,7 +23,7 @@ entry:
   ret { ppc_fp128, ppc_fp128 } %0
 }
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: lfd 3
 ; CHECK: lfd 4
 ; CHECK: lfd 2
@@ -49,7 +49,7 @@ entry:
   ret { float, float } %0
 }
 
-; CHECK: oof:
+; CHECK-LABEL: oof:
 ; CHECK: lfs 2
 ; CHECK: lfs 1
 
diff --git a/test/CodeGen/PowerPC/crsave.ll b/test/CodeGen/PowerPC/crsave.ll
index b15011d..a9b4b36 100644
--- a/test/CodeGen/PowerPC/crsave.ll
+++ b/test/CodeGen/PowerPC/crsave.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32
-; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC64
+; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC32
+; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC64
 
 declare void @foo()
 
@@ -18,7 +18,7 @@ entry:
 ; PPC32: mfcr 12
 ; PPC32-NEXT: stw 12, 24(31)
 ; PPC32: lwz 12, 24(31)
-; PPC32-NEXT: mtcrf 32, 12
+; PPC32-NEXT: mtocrf 32, 12
 
 ; PPC64: .cfi_startproc
 ; PPC64: mfcr 12
@@ -29,7 +29,7 @@ entry:
 ; PPC64: .cfi_offset cr2, 8
 ; PPC64: addi 1, 1, [[AMT]]
 ; PPC64: lwz 12, 8(1)
-; PPC64: mtcrf 32, 12
+; PPC64: mtocrf 32, 12
 ; PPC64: .cfi_endproc
 
 define i32 @test_cr234() nounwind {
@@ -47,16 +47,16 @@ entry:
 ; PPC32: mfcr 12
 ; PPC32-NEXT: stw 12, 24(31)
 ; PPC32: lwz 12, 24(31)
-; PPC32-NEXT: mtcrf 32, 12
-; PPC32-NEXT: mtcrf 16, 12
-; PPC32-NEXT: mtcrf 8, 12
+; PPC32-NEXT: mtocrf 32, 12
+; PPC32-NEXT: mtocrf 16, 12
+; PPC32-NEXT: mtocrf 8, 12
 
 ; PPC64: mfcr 12
 ; PPC64: stw 12, 8(1)
 ; PPC64: stdu 1, -[[AMT:[0-9]+]](1)
 ; PPC64: addi 1, 1, [[AMT]]
 ; PPC64: lwz 12, 8(1)
-; PPC64: mtcrf 32, 12
-; PPC64: mtcrf 16, 12
-; PPC64: mtcrf 8, 12
+; PPC64: mtocrf 32, 12
+; PPC64: mtocrf 16, 12
+; PPC64: mtocrf 8, 12
 
diff --git a/test/CodeGen/PowerPC/ctrloop-large-ec.ll b/test/CodeGen/PowerPC/ctrloop-large-ec.ll
new file mode 100644
index 0000000..c18bdab
--- /dev/null
+++ b/test/CodeGen/PowerPC/ctrloop-large-ec.ll
@@ -0,0 +1,23 @@
+; RUN: llc -mcpu=ppc32 < %s
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"
+target triple = "powerpc-unknown-linux-gnu"
+
+define void @fn1() {
+entry:
+  br i1 undef, label %for.end, label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %inc3 = phi i64 [ %inc, %for.body ], [ undef, %entry ]
+  %inc = add nsw i64 %inc3, 1
+  %tobool = icmp eq i64 %inc, 0
+  br i1 %tobool, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+; On PPC32, CTR is also 32 bits, and so cannot hold a 64-bit count.
+; CHECK: @fn1
+; CHECK-NOT: mtctr
+; CHECK: blr
+
diff --git a/test/CodeGen/PowerPC/dbg.ll b/test/CodeGen/PowerPC/dbg.ll
index 21e3661..30fe19e 100644
--- a/test/CodeGen/PowerPC/dbg.ll
+++ b/test/CodeGen/PowerPC/dbg.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -break-anti-dependencies=all -march=ppc64 -mcpu=g5 | FileCheck %s
-; CHECK: main:
+; CHECK-LABEL: main:
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
@@ -16,17 +16,17 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 720913, i32 12, metadata !6, metadata !"clang version 3.1", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 720913, metadata !21, i32 12, metadata !"clang version 3.1", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !"", metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 720942, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !13} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 720937, metadata !"dbg.c", metadata !"/src", null} ; [ DW_TAG_file_type ]
-!7 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!5 = metadata !{i32 720942, metadata !21, null, metadata !"main", metadata !"main", metadata !"", i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !13, i32 0} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 720937, metadata !21} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 720917, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{metadata !9, metadata !9, metadata !10}
-!9 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!10 = metadata !{i32 720911, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ]
-!11 = metadata !{i32 720911, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ]
-!12 = metadata !{i32 720932, null, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 720932, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!10 = metadata !{i32 720911, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ]
+!11 = metadata !{i32 720911, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ]
+!12 = metadata !{i32 720932, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ]
 !13 = metadata !{metadata !14}
 !14 = metadata !{metadata !15, metadata !16}
 !15 = metadata !{i32 721153, metadata !5, metadata !"argc", metadata !6, i32 16777217, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
@@ -34,5 +34,5 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !17 = metadata !{i32 1, i32 14, metadata !5, null}
 !18 = metadata !{i32 1, i32 26, metadata !5, null}
 !19 = metadata !{i32 2, i32 3, metadata !20, null}
-!20 = metadata !{i32 720907, metadata !5, i32 1, i32 34, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
-
+!20 = metadata !{i32 720907, metadata !21, metadata !5, i32 1, i32 34, i32 0} ; [ DW_TAG_lexical_block ]
+!21 = metadata !{metadata !"dbg.c", metadata !"/src"}
diff --git a/test/CodeGen/PowerPC/dyn-alloca-aligned.ll b/test/CodeGen/PowerPC/dyn-alloca-aligned.ll
new file mode 100644
index 0000000..a18ada7
--- /dev/null
+++ b/test/CodeGen/PowerPC/dyn-alloca-aligned.ll
@@ -0,0 +1,39 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.s = type { i32, i32 }
+
+declare void @bar(i32*, i32*) #0
+
+define void @goo(%struct.s* byval nocapture readonly %a, i32 signext %n) #0 {
+entry:
+  %0 = zext i32 %n to i64
+  %vla = alloca i32, i64 %0, align 128
+  %vla1 = alloca i32, i64 %0, align 128
+  %a2 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
+  %1 = load i32* %a2, align 4, !tbaa !0
+  store i32 %1, i32* %vla1, align 128, !tbaa !0
+  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
+  %2 = load i32* %b, align 4, !tbaa !0
+  %arrayidx3 = getelementptr inbounds i32* %vla1, i64 1
+  store i32 %2, i32* %arrayidx3, align 4, !tbaa !0
+  call void @bar(i32* %vla1, i32* %vla) #0
+  ret void
+
+; CHECK-LABEL: @goo
+
+; CHECK-DAG: li [[REG1:[0-9]+]], -128
+; CHECK-DAG: neg [[REG2:[0-9]+]],
+; CHECK: and [[REG1]], [[REG2]], [[REG1]]
+; CHECK: stdux {{[0-9]+}}, 1, [[REG1]]
+
+; CHECK: blr
+
+}
+
+attributes #0 = { nounwind }
+
+!0 = metadata !{metadata !"int", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA"}
diff --git a/test/CodeGen/PowerPC/emptystruct.ll b/test/CodeGen/PowerPC/emptystruct.ll
index 36b4abd..47cfadd 100644
--- a/test/CodeGen/PowerPC/emptystruct.ll
+++ b/test/CodeGen/PowerPC/emptystruct.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s
 
 ; This tests correct handling of empty aggregate parameters and return values.
 ; An empty parameter passed by value does not consume a protocol register or
@@ -25,9 +25,8 @@ entry:
   ret void
 }
 
-; CHECK: callee:
+; CHECK-LABEL: callee:
 ; CHECK: std 4,
-; CHECK: std 3,
 ; CHECK-NOT: std 5,
 ; CHECK-NOT: std 6,
 ; CHECK: blr
@@ -43,9 +42,8 @@ entry:
   ret void
 }
 
-; CHECK: caller:
+; CHECK-LABEL: caller:
 ; CHECK: addi 4,
-; CHECK: std 3,
 ; CHECK-NOT: std 5,
 ; CHECK-NOT: std 6,
 ; CHECK: bl callee
diff --git a/test/CodeGen/PowerPC/floatPSA.ll b/test/CodeGen/PowerPC/floatPSA.ll
index b5631a1..f14c736 100644
--- a/test/CodeGen/PowerPC/floatPSA.ll
+++ b/test/CodeGen/PowerPC/floatPSA.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -fast-isel=false < %s | FileCheck %s
 
 ; This verifies that single-precision floating point values that can't
 ; be passed in registers are stored in the rightmost word of the parameter
diff --git a/test/CodeGen/PowerPC/fma.ll b/test/CodeGen/PowerPC/fma.ll
index a173c91..db19761 100644
--- a/test/CodeGen/PowerPC/fma.ll
+++ b/test/CodeGen/PowerPC/fma.ll
@@ -4,7 +4,7 @@ define double @test_FMADD1(double %A, double %B, double %C) {
 	%D = fmul double %A, %B		; <double> [#uses=1]
 	%E = fadd double %D, %C		; <double> [#uses=1]
 	ret double %E
-; CHECK: test_FMADD1:
+; CHECK-LABEL: test_FMADD1:
 ; CHECK: fmadd
 ; CHECK-NEXT: blr
 }
@@ -13,7 +13,7 @@ define double @test_FMADD2(double %A, double %B, double %C) {
 	%D = fmul double %A, %B		; <double> [#uses=1]
 	%E = fadd double %D, %C		; <double> [#uses=1]
 	ret double %E
-; CHECK: test_FMADD2:
+; CHECK-LABEL: test_FMADD2:
 ; CHECK: fmadd
 ; CHECK-NEXT: blr
 }
@@ -22,7 +22,7 @@ define double @test_FMSUB(double %A, double %B, double %C) {
 	%D = fmul double %A, %B		; <double> [#uses=1]
 	%E = fsub double %D, %C		; <double> [#uses=1]
 	ret double %E
-; CHECK: test_FMSUB:
+; CHECK-LABEL: test_FMSUB:
 ; CHECK: fmsub
 ; CHECK-NEXT: blr
 }
@@ -32,7 +32,7 @@ define double @test_FNMADD1(double %A, double %B, double %C) {
 	%E = fadd double %D, %C		; <double> [#uses=1]
 	%F = fsub double -0.000000e+00, %E		; <double> [#uses=1]
 	ret double %F
-; CHECK: test_FNMADD1:
+; CHECK-LABEL: test_FNMADD1:
 ; CHECK: fnmadd
 ; CHECK-NEXT: blr
 }
@@ -42,7 +42,7 @@ define double @test_FNMADD2(double %A, double %B, double %C) {
 	%E = fadd double %C, %D		; <double> [#uses=1]
 	%F = fsub double -0.000000e+00, %E		; <double> [#uses=1]
 	ret double %F
-; CHECK: test_FNMADD2:
+; CHECK-LABEL: test_FNMADD2:
 ; CHECK: fnmadd
 ; CHECK-NEXT: blr
 }
@@ -51,7 +51,7 @@ define double @test_FNMSUB1(double %A, double %B, double %C) {
 	%D = fmul double %A, %B		; <double> [#uses=1]
 	%E = fsub double %C, %D		; <double> [#uses=1]
 	ret double %E
-; CHECK: test_FNMSUB1:
+; CHECK-LABEL: test_FNMSUB1:
 ; CHECK: fnmsub
 ; CHECK-NEXT: blr
 }
@@ -61,7 +61,7 @@ define double @test_FNMSUB2(double %A, double %B, double %C) {
 	%E = fsub double %D, %C		; <double> [#uses=1]
 	%F = fsub double -0.000000e+00, %E		; <double> [#uses=1]
 	ret double %F
-; CHECK: test_FNMSUB2:
+; CHECK-LABEL: test_FNMSUB2:
 ; CHECK: fnmsub
 ; CHECK-NEXT: blr
 }
@@ -71,7 +71,7 @@ define float @test_FNMSUBS(float %A, float %B, float %C) {
 	%E = fsub float %D, %C		; <float> [#uses=1]
 	%F = fsub float -0.000000e+00, %E		; <float> [#uses=1]
 	ret float %F
-; CHECK: test_FNMSUBS:
+; CHECK-LABEL: test_FNMSUBS:
 ; CHECK: fnmsubs
 ; CHECK-NEXT: blr
 }
diff --git a/test/CodeGen/PowerPC/indirectbr.ll b/test/CodeGen/PowerPC/indirectbr.ll
index 4b6f88b..fd06fd9 100644
--- a/test/CodeGen/PowerPC/indirectbr.ll
+++ b/test/CodeGen/PowerPC/indirectbr.ll
@@ -6,9 +6,9 @@
 @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
 
 define internal i32 @foo(i32 %i) nounwind {
-; PIC: foo:
-; STATIC: foo:
-; PPC64: foo:
+; PIC-LABEL: foo:
+; STATIC-LABEL: foo:
+; PPC64-LABEL: foo:
 entry:
   %0 = load i8** @nextaddr, align 4               ; <i8*> [#uses=2]
   %1 = icmp eq i8* %0, null                       ; <i1> [#uses=1]
diff --git a/test/CodeGen/PowerPC/inlineasm-i64-reg.ll b/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
new file mode 100644
index 0000000..fa9aa45
--- /dev/null
+++ b/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
@@ -0,0 +1,65 @@
+; RUN: llc -mtriple=powerpc64-bgq-linux -mcpu=a2 < %s | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+%struct.BG_CoordinateMapping_t = type { [4 x i8] }
+
+; Function Attrs: alwaysinline inlinehint nounwind
+define zeroext i32 @Kernel_RanksToCoords(i64 %mapsize, %struct.BG_CoordinateMapping_t* %map, i64* %numentries) #0 {
+entry:
+  %mapsize.addr = alloca i64, align 8
+  %map.addr = alloca %struct.BG_CoordinateMapping_t*, align 8
+  %numentries.addr = alloca i64*, align 8
+  %r0 = alloca i64, align 8
+  %r3 = alloca i64, align 8
+  %r4 = alloca i64, align 8
+  %r5 = alloca i64, align 8
+  %tmp = alloca i64, align 8
+  store i64 %mapsize, i64* %mapsize.addr, align 8
+  store %struct.BG_CoordinateMapping_t* %map, %struct.BG_CoordinateMapping_t** %map.addr, align 8
+  store i64* %numentries, i64** %numentries.addr, align 8
+  store i64 1055, i64* %r0, align 8
+  %0 = load i64* %mapsize.addr, align 8
+  store i64 %0, i64* %r3, align 8
+  %1 = load %struct.BG_CoordinateMapping_t** %map.addr, align 8
+  %2 = ptrtoint %struct.BG_CoordinateMapping_t* %1 to i64
+  store i64 %2, i64* %r4, align 8
+  %3 = load i64** %numentries.addr, align 8
+  %4 = ptrtoint i64* %3 to i64
+  store i64 %4, i64* %r5, align 8
+  %5 = load i64* %r0, align 8
+  %6 = load i64* %r3, align 8
+  %7 = load i64* %r4, align 8
+  %8 = load i64* %r5, align 8
+  %9 = call { i64, i64, i64, i64 } asm sideeffect "sc", "={r0},={r3},={r4},={r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 %5, i64 %6, i64 %7, i64 %8) #1, !srcloc !0
+
+; CHECK-LABEL: @Kernel_RanksToCoords
+
+; These need to be 64-bit loads, not 32-bit loads (not lwz).
+; CHECK-NOT: lwz
+
+; CHECK: #APP
+; CHECK: sc
+; CHECK: #NO_APP
+
+; CHECK: blr
+
+  %asmresult = extractvalue { i64, i64, i64, i64 } %9, 0
+  %asmresult1 = extractvalue { i64, i64, i64, i64 } %9, 1
+  %asmresult2 = extractvalue { i64, i64, i64, i64 } %9, 2
+  %asmresult3 = extractvalue { i64, i64, i64, i64 } %9, 3
+  store i64 %asmresult, i64* %r0, align 8
+  store i64 %asmresult1, i64* %r3, align 8
+  store i64 %asmresult2, i64* %r4, align 8
+  store i64 %asmresult3, i64* %r5, align 8
+  %10 = load i64* %r3, align 8
+  store i64 %10, i64* %tmp
+  %11 = load i64* %tmp
+  %conv = trunc i64 %11 to i32
+  ret i32 %conv
+}
+
+attributes #0 = { alwaysinline inlinehint nounwind }
+attributes #1 = { nounwind }
+
+!0 = metadata !{i32 -2146895770}
diff --git a/test/CodeGen/PowerPC/isel-rc-nox0.ll b/test/CodeGen/PowerPC/isel-rc-nox0.ll
new file mode 100644
index 0000000..7d425cc
--- /dev/null
+++ b/test/CodeGen/PowerPC/isel-rc-nox0.ll
@@ -0,0 +1,50 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+@g_62 = external global [1 x [9 x i32]], align 4
+
+; Function Attrs: nounwind
+define void @main() #0 {
+entry:
+  br i1 undef, label %cond.true, label %for.cond1.preheader.i
+
+cond.true:                                        ; preds = %entry
+  br label %for.cond1.preheader.i
+
+for.cond1.preheader.i:                            ; preds = %for.cond1.preheader.i, %cond.true, %entry
+  br i1 undef, label %crc32_gentab.exit, label %for.cond1.preheader.i
+
+crc32_gentab.exit:                                ; preds = %for.cond1.preheader.i
+  %tobool.i19.i.i = icmp eq i32 undef, 0
+  %retval.0.i.i.i = select i1 %tobool.i19.i.i, i32* getelementptr inbounds ([1 x [9 x i32]]* @g_62, i64 0, i64 0, i64 6), i32* getelementptr inbounds ([1 x [9 x i32]]* @g_62, i64 0, i64 0, i64 8)
+  br label %for.cond1.preheader.i2961.i
+
+for.cond1.preheader.i2961.i:                      ; preds = %for.inc44.i2977.i, %crc32_gentab.exit
+  call void @llvm.memset.p0i8.i64(i8* bitcast ([1 x [9 x i32]]* @g_62 to i8*), i8 -1, i64 36, i32 4, i1 false) #1
+  %0 = load i32* %retval.0.i.i.i, align 4, !tbaa !0
+  %tobool.i2967.i = icmp eq i32 %0, 0
+  br label %for.body21.i2968.i
+
+for.body21.i2968.i:                               ; preds = %safe_mod_func_int32_t_s_s.exit.i2974.i, %for.cond1.preheader.i2961.i
+  br i1 %tobool.i2967.i, label %safe_mod_func_int32_t_s_s.exit.i2974.i, label %for.inc44.i2977.i
+
+safe_mod_func_int32_t_s_s.exit.i2974.i:           ; preds = %for.body21.i2968.i
+  br i1 undef, label %for.body21.i2968.i, label %for.inc44.i2977.i
+
+for.inc44.i2977.i:                                ; preds = %safe_mod_func_int32_t_s_s.exit.i2974.i, %for.body21.i2968.i
+  br i1 undef, label %func_80.exit2978.i, label %for.cond1.preheader.i2961.i
+
+func_80.exit2978.i:                               ; preds = %for.inc44.i2977.i
+  unreachable
+}
+
+; Function Attrs: nounwind
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "ssp-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind }
+
+!0 = metadata !{metadata !"int", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA"}
diff --git a/test/CodeGen/PowerPC/jaggedstructs.ll b/test/CodeGen/PowerPC/jaggedstructs.ll
index a10c5dd..82d4fef 100644
--- a/test/CodeGen/PowerPC/jaggedstructs.ll
+++ b/test/CodeGen/PowerPC/jaggedstructs.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s
 
 ; This tests receiving and re-passing parameters consisting of structures
 ; of size 3, 5, 6, and 7.  They are to be found/placed right-adjusted in
@@ -18,25 +18,25 @@ entry:
   ret void
 }
 
-; CHECK: std 6, 216(1)
-; CHECK: std 5, 208(1)
-; CHECK: std 4, 200(1)
-; CHECK: std 3, 192(1)
-; CHECK: lbz {{[0-9]+}}, 199(1)
-; CHECK: lhz {{[0-9]+}}, 197(1)
+; CHECK: std 6, 184(1)
+; CHECK: std 5, 176(1)
+; CHECK: std 4, 168(1)
+; CHECK: std 3, 160(1)
+; CHECK: lbz {{[0-9]+}}, 167(1)
+; CHECK: lhz {{[0-9]+}}, 165(1)
 ; CHECK: stb {{[0-9]+}}, 55(1)
 ; CHECK: sth {{[0-9]+}}, 53(1)
-; CHECK: lbz {{[0-9]+}}, 207(1)
-; CHECK: lwz {{[0-9]+}}, 203(1)
+; CHECK: lbz {{[0-9]+}}, 175(1)
+; CHECK: lwz {{[0-9]+}}, 171(1)
 ; CHECK: stb {{[0-9]+}}, 63(1)
 ; CHECK: stw {{[0-9]+}}, 59(1)
-; CHECK: lhz {{[0-9]+}}, 214(1)
-; CHECK: lwz {{[0-9]+}}, 210(1)
+; CHECK: lhz {{[0-9]+}}, 182(1)
+; CHECK: lwz {{[0-9]+}}, 178(1)
 ; CHECK: sth {{[0-9]+}}, 70(1)
 ; CHECK: stw {{[0-9]+}}, 66(1)
-; CHECK: lbz {{[0-9]+}}, 223(1)
-; CHECK: lhz {{[0-9]+}}, 221(1)
-; CHECK: lwz {{[0-9]+}}, 217(1)
+; CHECK: lbz {{[0-9]+}}, 191(1)
+; CHECK: lhz {{[0-9]+}}, 189(1)
+; CHECK: lwz {{[0-9]+}}, 185(1)
 ; CHECK: stb {{[0-9]+}}, 79(1)
 ; CHECK: sth {{[0-9]+}}, 77(1)
 ; CHECK: stw {{[0-9]+}}, 73(1)
diff --git a/test/CodeGen/PowerPC/mcm-1.ll b/test/CodeGen/PowerPC/mcm-1.ll
index a57fb9d..4e31550 100644
--- a/test/CodeGen/PowerPC/mcm-1.ll
+++ b/test/CodeGen/PowerPC/mcm-1.ll
@@ -17,7 +17,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/mcm-10.ll b/test/CodeGen/PowerPC/mcm-10.ll
index 4bec3e1..b479559 100644
--- a/test/CodeGen/PowerPC/mcm-10.ll
+++ b/test/CodeGen/PowerPC/mcm-10.ll
@@ -16,7 +16,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_fn_static:
+; CHECK-LABEL: test_fn_static:
 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; CHECK: lwz {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
 ; CHECK: stw {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
diff --git a/test/CodeGen/PowerPC/mcm-11.ll b/test/CodeGen/PowerPC/mcm-11.ll
index f2bc4c9..c49e865 100644
--- a/test/CodeGen/PowerPC/mcm-11.ll
+++ b/test/CodeGen/PowerPC/mcm-11.ll
@@ -16,7 +16,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_file_static:
+; CHECK-LABEL: test_file_static:
 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; CHECK: lwz {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
 ; CHECK: stw {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
diff --git a/test/CodeGen/PowerPC/mcm-12.ll b/test/CodeGen/PowerPC/mcm-12.ll
index 911305d..b31b605 100644
--- a/test/CodeGen/PowerPC/mcm-12.ll
+++ b/test/CodeGen/PowerPC/mcm-12.ll
@@ -13,6 +13,6 @@ entry:
 
 ; CHECK: [[VAR:[a-z0-9A-Z_.]+]]:
 ; CHECK: .quad 4562098671269285104
-; CHECK: test_double_const:
+; CHECK-LABEL: test_double_const:
 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
diff --git a/test/CodeGen/PowerPC/mcm-2.ll b/test/CodeGen/PowerPC/mcm-2.ll
index f0dff4c..d4f40f7 100644
--- a/test/CodeGen/PowerPC/mcm-2.ll
+++ b/test/CodeGen/PowerPC/mcm-2.ll
@@ -17,7 +17,7 @@ entry:
   ret i32 %0
 }
 
-; MEDIUM: test_fn_static:
+; MEDIUM-LABEL: test_fn_static:
 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
@@ -26,7 +26,7 @@ entry:
 ; MEDIUM: .local [[VAR]]
 ; MEDIUM: .comm [[VAR]],4,4
 
-; LARGE: test_fn_static:
+; LARGE-LABEL: test_fn_static:
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
 ; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/mcm-3.ll b/test/CodeGen/PowerPC/mcm-3.ll
index b790550..ce151fb 100644
--- a/test/CodeGen/PowerPC/mcm-3.ll
+++ b/test/CodeGen/PowerPC/mcm-3.ll
@@ -17,7 +17,7 @@ entry:
   ret i32 %0
 }
 
-; MEDIUM: test_file_static:
+; MEDIUM-LABEL: test_file_static:
 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
@@ -28,7 +28,7 @@ entry:
 ; MEDIUM: [[VAR]]:
 ; MEDIUM: .long 5
 
-; LARGE: test_file_static:
+; LARGE-LABEL: test_file_static:
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
 ; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/mcm-4.ll b/test/CodeGen/PowerPC/mcm-4.ll
index 47c60c9..7d7b132 100644
--- a/test/CodeGen/PowerPC/mcm-4.ll
+++ b/test/CodeGen/PowerPC/mcm-4.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck -check-prefix=MEDIUM %s
-; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck -check-prefix=LARGE %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false <%s | FileCheck -check-prefix=MEDIUM %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false <%s | FileCheck -check-prefix=LARGE %s
 
 ; Test correct code generation for medium and large code model
 ; for loading a value from the constant pool (TOC-relative).
@@ -14,14 +14,14 @@ entry:
 
 ; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]:
 ; MEDIUM: .quad 4562098671269285104
-; MEDIUM: test_double_const:
+; MEDIUM-LABEL: test_double_const:
 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
 
 ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
 ; LARGE: .quad 4562098671269285104
-; LARGE: test_double_const:
+; LARGE-LABEL: test_double_const:
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
 ; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/mcm-5.ll b/test/CodeGen/PowerPC/mcm-5.ll
index 1be27b7..92ddeca 100644
--- a/test/CodeGen/PowerPC/mcm-5.ll
+++ b/test/CodeGen/PowerPC/mcm-5.ll
@@ -51,7 +51,7 @@ sw.epilog:                                        ; preds = %sw.bb3, %sw.default
   ret i32 %5
 }
 
-; CHECK: test_jump_table:
+; CHECK-LABEL: test_jump_table:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: ldx {{[0-9]+}}, {{[0-9]+}}, [[REG2]]
diff --git a/test/CodeGen/PowerPC/mcm-6.ll b/test/CodeGen/PowerPC/mcm-6.ll
index 35efaaa..f7838b4 100644
--- a/test/CodeGen/PowerPC/mcm-6.ll
+++ b/test/CodeGen/PowerPC/mcm-6.ll
@@ -17,7 +17,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_tentative:
+; CHECK-LABEL: test_tentative:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/mcm-7.ll b/test/CodeGen/PowerPC/mcm-7.ll
index 0dd39ee..7caa13b 100644
--- a/test/CodeGen/PowerPC/mcm-7.ll
+++ b/test/CodeGen/PowerPC/mcm-7.ll
@@ -18,7 +18,7 @@ entry:
 
 declare signext i32 @foo(i32 signext)
 
-; CHECK: test_fnaddr:
+; CHECK-LABEL: test_fnaddr:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: .section .toc
diff --git a/test/CodeGen/PowerPC/mcm-8.ll b/test/CodeGen/PowerPC/mcm-8.ll
index 3ece786..643548f 100644
--- a/test/CodeGen/PowerPC/mcm-8.ll
+++ b/test/CodeGen/PowerPC/mcm-8.ll
@@ -16,7 +16,7 @@ entry:
   ret i8 %1
 }
 
-; CHECK: test_avext:
+; CHECK-LABEL: test_avext:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lbz {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/mcm-9.ll b/test/CodeGen/PowerPC/mcm-9.ll
index f366f45..e587f61 100644
--- a/test/CodeGen/PowerPC/mcm-9.ll
+++ b/test/CodeGen/PowerPC/mcm-9.ll
@@ -18,7 +18,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/mcm-default.ll b/test/CodeGen/PowerPC/mcm-default.ll
index 19de253..8d4ff14 100644
--- a/test/CodeGen/PowerPC/mcm-default.ll
+++ b/test/CodeGen/PowerPC/mcm-default.ll
@@ -16,7 +16,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/mcm-obj.ll b/test/CodeGen/PowerPC/mcm-obj.ll
index 4550c39..d3d05eb 100644
--- a/test/CodeGen/PowerPC/mcm-obj.ll
+++ b/test/CodeGen/PowerPC/mcm-obj.ll
@@ -1,6 +1,6 @@
-; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj %s -o - | \
+; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj -fast-isel=false %s -o - | \
 ; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM %s
-; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj %s -o - | \
+; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj -fast-isel=false %s -o - | \
 ; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE %s
 
 ; FIXME: When asm-parse is available, could make this an assembly test.
diff --git a/test/CodeGen/PowerPC/misched-inorder-latency.ll b/test/CodeGen/PowerPC/misched-inorder-latency.ll
index 8fae7ad..b259ff1 100644
--- a/test/CodeGen/PowerPC/misched-inorder-latency.ll
+++ b/test/CodeGen/PowerPC/misched-inorder-latency.ll
@@ -6,7 +6,7 @@ target triple = "powerpc64-bgq-linux"
 
 ; %val1 is a load live out of %entry. It should be hoisted
 ; above the add.
-; CHECK: testload:
+; CHECK-LABEL: testload:
 ; CHECK: %entry
 ; CHECK: lwz
 ; CHECK: addi
@@ -34,7 +34,7 @@ end:
 ; The prefetch gets a default latency of 3 cycles and should be hoisted
 ; above the add.
 ;
-; CHECK: testprefetch:
+; CHECK-LABEL: testprefetch:
 ; CHECK: %entry
 ; CHECK: dcbt
 ; CHECK: addi
diff --git a/test/CodeGen/PowerPC/mulli64.ll b/test/CodeGen/PowerPC/mulli64.ll
new file mode 100644
index 0000000..21bc9cc
--- /dev/null
+++ b/test/CodeGen/PowerPC/mulli64.ll
@@ -0,0 +1,16 @@
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define i64 @foo(i64 %a) #0 {
+entry:
+  %mul = mul nsw i64 %a, 3
+  ret i64 %mul
+}
+
+; CHECK-LABEL: @foo
+; CHECK: mulli 3, 3, 3
+; CHECK: blr
+
+attributes #0 = { nounwind readnone }
+
diff --git a/test/CodeGen/PowerPC/ppc32-vacopy.ll b/test/CodeGen/PowerPC/ppc32-vacopy.ll
new file mode 100644
index 0000000..bc39412
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc32-vacopy.ll
@@ -0,0 +1,24 @@
+; RUN: llc -mtriple="powerpc-unknown-linux-gnu" < %s | FileCheck %s
+; PR15286
+
+%va_list = type {i8, i8, i16, i8*, i8*}
+declare void @llvm.va_copy(i8*, i8*)
+
+define void @test_vacopy() nounwind {
+entry:
+	%0 = alloca %va_list
+	%1 = alloca %va_list
+	%2 = bitcast %va_list* %0 to i8*
+	%3 = bitcast %va_list* %1 to i8*
+
+	call void @llvm.va_copy(i8* %3, i8* %2)
+
+	ret void
+}
+; CHECK: test_vacopy:
+; CHECK: lwz [[REG1:[0-9]+]], {{.*}}
+; CHECK: lwz [[REG2:[0-9]+]], {{.*}}
+; CHECK: lwz [[REG3:[0-9]+]], {{.*}}
+; CHECK: stw [[REG1]], {{.*}}
+; CHECK: stw [[REG2]], {{.*}}
+; CHECK: stw [[REG3]], {{.*}}
diff --git a/test/CodeGen/PowerPC/ppc64-align-long-double.ll b/test/CodeGen/PowerPC/ppc64-align-long-double.ll
index 10b70d0..764d3ce 100644
--- a/test/CodeGen/PowerPC/ppc64-align-long-double.ll
+++ b/test/CodeGen/PowerPC/ppc64-align-long-double.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s
 
 ; Verify internal alignment of long double in a struct.  The double
 ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain
diff --git a/test/CodeGen/PowerPC/ppc64-calls.ll b/test/CodeGen/PowerPC/ppc64-calls.ll
index c382edb..1f3bb71 100644
--- a/test/CodeGen/PowerPC/ppc64-calls.ll
+++ b/test/CodeGen/PowerPC/ppc64-calls.ll
@@ -12,7 +12,7 @@ define weak void @foo_weak() nounwind {
 
 ; Calls to local function does not require the TOC restore 'nop'
 define void @test_direct() nounwind readnone {
-; CHECK: test_direct:
+; CHECK-LABEL: test_direct:
   tail call void @foo() nounwind
 ; CHECK: bl foo
 ; CHECK-NOT: nop
@@ -22,7 +22,7 @@ define void @test_direct() nounwind readnone {
 ; Calls to weak function requires a TOC restore 'nop' because they
 ; may be overridden in a different module.
 define void @test_weak() nounwind readnone {
-; CHECK: test_weak:
+; CHECK-LABEL: test_weak:
   tail call void @foo_weak() nounwind
 ; CHECK: bl foo
 ; CHECK-NEXT: nop
@@ -31,7 +31,7 @@ define void @test_weak() nounwind readnone {
 
 ; Indirect calls requires a full stub creation
 define void @test_indirect(void ()* nocapture %fp) nounwind {
-; CHECK: test_indirect:
+; CHECK-LABEL: test_indirect:
   tail call void %fp() nounwind
 ; CHECK: ld [[FP:[0-9]+]], 0(3)
 ; CHECK: ld 11, 16(3)
@@ -44,7 +44,7 @@ define void @test_indirect(void ()* nocapture %fp) nounwind {
 
 ; Absolute vales should be have the TOC restore 'nop'
 define void @test_abs() nounwind {
-; CHECK: test_abs:
+; CHECK-LABEL: test_abs:
   tail call void inttoptr (i64 1024 to void ()*)() nounwind
 ; CHECK: bla 1024
 ; CHECK-NEXT: nop
@@ -55,7 +55,7 @@ declare double @sin(double) nounwind
 
 ; External functions call should also have a 'nop'
 define double @test_external(double %x) nounwind {
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
   %call = tail call double @sin(double %x) nounwind
 ; CHECK: bl sin
 ; CHECK-NEXT: nop
diff --git a/test/CodeGen/PowerPC/ppc64-toc.ll b/test/CodeGen/PowerPC/ppc64-toc.ll
index 7f30ef8..f349919 100644
--- a/test/CodeGen/PowerPC/ppc64-toc.ll
+++ b/test/CodeGen/PowerPC/ppc64-toc.ll
@@ -8,7 +8,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define i64 @access_int64(i64 %a) nounwind readonly {
 entry:
-; CHECK: access_int64:
+; CHECK-LABEL: access_int64:
 ; CHECK-NEXT: .align  3
 ; CHECK-NEXT: .quad   .L.access_int64
 ; CHECK-NEXT: .quad   .TOC.@tocbase
@@ -23,7 +23,7 @@ entry:
 
 define i64 @internal_static_var(i64 %a) nounwind {
 entry:
-; CHECK: internal_static_var:
+; CHECK-LABEL: internal_static_var:
 ; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
   %0 = load i64* @internal_static_var.x, align 8
   %cmp = icmp eq i64 %0, %a
@@ -33,7 +33,7 @@ entry:
 
 define i32 @access_double(double %a) nounwind readnone {
 entry:
-; CHECK: access_double:
+; CHECK-LABEL: access_double:
 ; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
   %cmp = fcmp oeq double %a, 2.000000e+00
   %conv = zext i1 %cmp to i32 
@@ -43,7 +43,7 @@ entry:
 
 define i32 @access_double_array(double %a, i32 %i) nounwind readonly {
 entry:
-; CHECK: access_double_array:
+; CHECK-LABEL: access_double_array:
   %idxprom = sext i32 %i to i64
   %arrayidx = getelementptr inbounds [32 x double]* @double_array, i64 0, i64 %idxprom
   %0 = load double* %arrayidx, align 8
diff --git a/test/CodeGen/PowerPC/pr13891.ll b/test/CodeGen/PowerPC/pr13891.ll
index 3ae7385..4be65dd 100644
--- a/test/CodeGen/PowerPC/pr13891.ll
+++ b/test/CodeGen/PowerPC/pr13891.ll
@@ -5,7 +5,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 %struct.foo = type { i8, i8 }
 
 define void @_Z5check3foos(%struct.foo* nocapture byval %f, i16 signext %i) noinline {
-; CHECK: _Z5check3foos:
+; CHECK-LABEL: _Z5check3foos:
 ; CHECK: sth 3, {{[0-9]+}}(1)
 ; CHECK: lha {{[0-9]+}}, {{[0-9]+}}(1)
 entry:
diff --git a/test/CodeGen/PowerPC/pr16556-2.ll b/test/CodeGen/PowerPC/pr16556-2.ll
new file mode 100644
index 0000000..e2dae45
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr16556-2.ll
@@ -0,0 +1,41 @@
+; RUN: llc < %s
+
+; This test formerly failed because of wrong custom lowering for
+; fptosi of ppc_fp128.
+
+target datalayout = "E-p:32:32:32-S0-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:64:128-v64:64:64-v128:128:128-a0:0:64-n32"
+target triple = "powerpc-unknown-linux-gnu"
+
+%core.time.TickDuration = type { i64 }
+
+@_D4core4time12TickDuration11ticksPerSecyl = global i64 0
+@.str5 = internal unnamed_addr constant [40 x i8] c"..\5Cldc\5Cruntime\5Cdruntime\5Csrc\5Ccore\5Ctime.d\00"
+@.str83 = internal constant [10 x i8] c"null this\00"
+@.modulefilename = internal constant { i32, i8* } { i32 39, i8* getelementptr inbounds ([40 x i8]* @.str5, i32 0, i32 0) }
+
+declare i8* @_d_assert_msg({ i32, i8* }, { i32, i8* }, i32)
+
+
+define weak_odr fastcc i64 @_D4core4time12TickDuration30__T2toVAyaa7_7365636f6e6473TlZ2toMxFNaNbNfZl(%core.time.TickDuration* %.this_arg) {
+entry:
+  %unitsPerSec = alloca i64, align 8
+  %tmp = icmp ne %core.time.TickDuration* %.this_arg, null
+  br i1 %tmp, label %noassert, label %assert
+
+assert:                                           ; preds = %entry
+  %tmp1 = load { i32, i8* }* @.modulefilename
+  %0 = call i8* @_d_assert_msg({ i32, i8* } { i32 9, i8* getelementptr inbounds ([10 x i8]* @.str83, i32 0, i32 0) }, { i32, i8* } %tmp1, i32 1586)
+  unreachable
+
+noassert:                                         ; preds = %entry
+  %tmp2 = getelementptr %core.time.TickDuration* %.this_arg, i32 0, i32 0
+  %tmp3 = load i64* %tmp2
+  %tmp4 = sitofp i64 %tmp3 to ppc_fp128
+  %tmp5 = load i64* @_D4core4time12TickDuration11ticksPerSecyl
+  %tmp6 = sitofp i64 %tmp5 to ppc_fp128
+  %tmp7 = fdiv ppc_fp128 %tmp6, 0xM80000000000000000000000000000000
+  %tmp8 = fdiv ppc_fp128 %tmp4, %tmp7
+  %tmp9 = fptosi ppc_fp128 %tmp8 to i64
+  ret i64 %tmp9
+}
+
diff --git a/test/CodeGen/PowerPC/pr16556.ll b/test/CodeGen/PowerPC/pr16556.ll
new file mode 100644
index 0000000..dc36f0b
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr16556.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s
+
+; This test formerly failed due to no handling for a ppc_fp128 undef.
+
+target datalayout = "E-p:32:32:32-S0-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:64:128-v64:64:64-v128:128:128-a0:0:64-n32"
+target triple = "powerpc-unknown-linux-gnu"
+
+%core.time.TickDuration.37.125 = type { i64 }
+
+define weak_odr fastcc i64 @_D4core4time12TickDuration30__T2toVAyaa7_7365636f6e6473TlZ2toMxFNaNbNfZl(%core.time.TickDuration.37.125* %.this_arg) {
+entry:
+  br i1 undef, label %noassert, label %assert
+
+assert:                                           ; preds = %entry
+  unreachable
+
+noassert:                                         ; preds = %entry
+  %tmp9 = fptosi ppc_fp128 undef to i64
+  ret i64 %tmp9
+}
diff --git a/test/CodeGen/PowerPC/pr16573.ll b/test/CodeGen/PowerPC/pr16573.ll
new file mode 100644
index 0000000..7a7a8de
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr16573.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "powerpc64-unknown-linux-gnu"
+
+define double @test() {
+  %1 = fptrunc ppc_fp128 0xM818F2887B9295809800000000032D000 to double
+  ret double %1
+}
+
+; CHECK: .quad -9111018957755033591
+
diff --git a/test/CodeGen/PowerPC/reloc-align.ll b/test/CodeGen/PowerPC/reloc-align.ll
new file mode 100644
index 0000000..bd5c4d6
--- /dev/null
+++ b/test/CodeGen/PowerPC/reloc-align.ll
@@ -0,0 +1,34 @@
+; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s
+
+; This test verifies that the peephole optimization of address accesses
+; does not produce a load or store with a relocation that can't be
+; satisfied for a given instruction encoding.  Reduced from a test supplied
+; by Hal Finkel.
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.S1 = type { [8 x i8] }
+
+@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1
+
+; Function Attrs: nounwind readonly
+define signext i32 @main() #0 {
+entry:
+  %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*))
+; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l
+  ret i32 %call
+}
+
+; Function Attrs: nounwind readonly
+define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 {
+entry:
+  %0 = bitcast %struct.S1* %p_91 to i64*
+  %bf.load = load i64* %0, align 1
+  %bf.shl = shl i64 %bf.load, 26
+  %bf.ashr = ashr i64 %bf.shl, 54
+  %bf.cast = trunc i64 %bf.ashr to i32
+  ret i32 %bf.cast
+}
+
+attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/CodeGen/PowerPC/remap-crash.ll b/test/CodeGen/PowerPC/remap-crash.ll
new file mode 100644
index 0000000..515f720
--- /dev/null
+++ b/test/CodeGen/PowerPC/remap-crash.ll
@@ -0,0 +1,57 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
+target triple = "powerpc64-unknown-linux-gnu"
+
+define void @autogen_SD13() {
+BB:
+  br label %CF78
+
+CF78:                                             ; preds = %CF87, %CF86, %CF78, %BB
+  %Cmp = icmp ule <16 x i64> zeroinitializer, zeroinitializer
+  br i1 undef, label %CF78, label %CF86
+
+CF86:                                             ; preds = %CF78
+  br i1 undef, label %CF78, label %CF84
+
+CF84:                                             ; preds = %CF84, %CF86
+  br i1 undef, label %CF84, label %CF87
+
+CF87:                                             ; preds = %CF84
+  br i1 undef, label %CF78, label %CF82
+
+CF82:                                             ; preds = %CF82, %CF87
+  br i1 undef, label %CF82, label %CF83
+
+CF83:                                             ; preds = %CF82
+  br label %CF
+
+CF:                                               ; preds = %CF80, %CF81, %CF, %CF83
+  br i1 undef, label %CF, label %CF81
+
+CF81:                                             ; preds = %CF
+  %Se = sext <16 x i1> %Cmp to <16 x i16>
+  br i1 undef, label %CF, label %CF80
+
+CF80:                                             ; preds = %CF81
+  br i1 undef, label %CF, label %CF76
+
+CF76:                                             ; preds = %CF76, %CF80
+  %Sl58 = select i1 undef, <16 x i16> %Se, <16 x i16> %Se
+  br label %CF76
+}
+
+define void @autogen_SD1067() {
+BB:
+  %FC = sitofp <4 x i32> zeroinitializer to <4 x ppc_fp128>
+  br label %CF77
+
+CF77:                                             ; preds = %CF77, %BB
+  %brmerge = or i1 false, undef
+  br i1 %brmerge, label %CF77, label %CF85
+
+CF85:                                             ; preds = %CF77
+  %Shuff19 = shufflevector <4 x ppc_fp128> %FC, <4 x ppc_fp128> %FC, <4 x i32> <i32 7, i32 1, i32 3, i32 5>
+  br label %CF75
+
+CF75:                                             ; preds = %CF75, %CF85
+  br label %CF75
+}
diff --git a/test/CodeGen/PowerPC/rlwimi-and.ll b/test/CodeGen/PowerPC/rlwimi-and.ll
new file mode 100644
index 0000000..e20a13f
--- /dev/null
+++ b/test/CodeGen/PowerPC/rlwimi-and.ll
@@ -0,0 +1,44 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+define void @test() align 2 {
+entry:
+  br i1 undef, label %codeRepl1, label %codeRepl31
+
+codeRepl1:                                        ; preds = %entry
+  br i1 undef, label %codeRepl4, label %codeRepl29
+
+codeRepl4:                                        ; preds = %codeRepl1
+  br i1 undef, label %codeRepl12, label %codeRepl17
+
+codeRepl12:                                       ; preds = %codeRepl4
+  unreachable
+
+codeRepl17:                                       ; preds = %codeRepl4
+  %0 = load i8* undef, align 2
+  %1 = and i8 %0, 1
+  %not.tobool.i.i.i = icmp eq i8 %1, 0
+  %2 = select i1 %not.tobool.i.i.i, i16 0, i16 256
+  %3 = load i8* undef, align 1
+  %4 = and i8 %3, 1
+  %not.tobool.i.1.i.i = icmp eq i8 %4, 0
+  %rvml38.sroa.1.1.insert.ext = select i1 %not.tobool.i.1.i.i, i16 0, i16 1
+  %rvml38.sroa.0.0.insert.insert = or i16 %rvml38.sroa.1.1.insert.ext, %2
+  store i16 %rvml38.sroa.0.0.insert.insert, i16* undef, align 2
+  unreachable
+
+; CHECK: @test
+; CHECK-DAG: slwi [[R1:[0-9]+]],
+; CHECK-DAG: rlwinm [[R2:[0-9]+]],
+; CHECK-DAG: srawi [[R3:[0-9]+]], [[R1]]
+; CHECK-DAG: rlwinm [[R4:[0-9]+]], [[R3]], 0, 23, 23
+; CHECK: rlwimi [[R4]], [[R2]], 0,
+
+codeRepl29:                                       ; preds = %codeRepl1
+  unreachable
+
+codeRepl31:                                       ; preds = %entry
+  ret void
+}
+
diff --git a/test/CodeGen/PowerPC/rounding-ops.ll b/test/CodeGen/PowerPC/rounding-ops.ll
index 2b5e1c9..2c02900 100644
--- a/test/CodeGen/PowerPC/rounding-ops.ll
+++ b/test/CodeGen/PowerPC/rounding-ops.ll
@@ -7,10 +7,10 @@ define float @test1(float %x) nounwind  {
   %call = tail call float @floorf(float %x) nounwind readnone
   ret float %call
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: frim 1, 1
 
-; CHECK-FM: test1:
+; CHECK-FM-LABEL: test1:
 ; CHECK-FM: frim 1, 1
 }
 
@@ -20,10 +20,10 @@ define double @test2(double %x) nounwind  {
   %call = tail call double @floor(double %x) nounwind readnone
   ret double %call
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: frim 1, 1
 
-; CHECK-FM: test2:
+; CHECK-FM-LABEL: test2:
 ; CHECK-FM: frim 1, 1
 }
 
@@ -33,10 +33,10 @@ define float @test3(float %x) nounwind  {
   %call = tail call float @nearbyintf(float %x) nounwind readnone
   ret float %call
 
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK-NOT: frin
 
-; CHECK-FM: test3:
+; CHECK-FM-LABEL: test3:
 ; CHECK-FM: frin 1, 1
 }
 
@@ -46,10 +46,10 @@ define double @test4(double %x) nounwind  {
   %call = tail call double @nearbyint(double %x) nounwind readnone
   ret double %call
 
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK-NOT: frin
 
-; CHECK-FM: test4:
+; CHECK-FM-LABEL: test4:
 ; CHECK-FM: frin 1, 1
 }
 
@@ -59,10 +59,10 @@ define float @test5(float %x) nounwind  {
   %call = tail call float @ceilf(float %x) nounwind readnone
   ret float %call
 
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: frip 1, 1
 
-; CHECK-FM: test5:
+; CHECK-FM-LABEL: test5:
 ; CHECK-FM: frip 1, 1
 }
 
@@ -72,10 +72,10 @@ define double @test6(double %x) nounwind  {
   %call = tail call double @ceil(double %x) nounwind readnone
   ret double %call
 
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: frip 1, 1
 
-; CHECK-FM: test6:
+; CHECK-FM-LABEL: test6:
 ; CHECK-FM: frip 1, 1
 }
 
@@ -85,10 +85,10 @@ define float @test9(float %x) nounwind  {
   %call = tail call float @truncf(float %x) nounwind readnone
   ret float %call
 
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: friz 1, 1
 
-; CHECK-FM: test9:
+; CHECK-FM-LABEL: test9:
 ; CHECK-FM: friz 1, 1
 }
 
@@ -98,10 +98,10 @@ define double @test10(double %x) nounwind  {
   %call = tail call double @trunc(double %x) nounwind readnone
   ret double %call
 
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: friz 1, 1
 
-; CHECK-FM: test10:
+; CHECK-FM-LABEL: test10:
 ; CHECK-FM: friz 1, 1
 }
 
@@ -112,10 +112,10 @@ define void @test11(float %x, float* %y) nounwind  {
   store float %call, float* %y
   ret void
 
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK-NOT: frin
 
-; CHECK-FM: test11:
+; CHECK-FM-LABEL: test11:
 ; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]]
 ; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]]
 ; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2
@@ -131,10 +131,10 @@ define void @test12(double %x, double* %y) nounwind  {
   store double %call, double* %y
   ret void
 
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK-NOT: frin
 
-; CHECK-FM: test12:
+; CHECK-FM-LABEL: test12:
 ; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]]
 ; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]]
 ; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2
diff --git a/test/CodeGen/PowerPC/rs-undef-use.ll b/test/CodeGen/PowerPC/rs-undef-use.ll
new file mode 100644
index 0000000..24dd5fd
--- /dev/null
+++ b/test/CodeGen/PowerPC/rs-undef-use.ll
@@ -0,0 +1,48 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
+target triple = "powerpc64-unknown-linux-gnu"
+
+define void @autogen_SD156869(i8*, i64*) {
+BB:
+  %A3 = alloca <2 x i1>
+  %A2 = alloca <8 x i32>
+  br label %CF
+
+CF:                                               ; preds = %CF85, %CF, %BB
+  br i1 undef, label %CF, label %CF82.critedge
+
+CF82.critedge:                                    ; preds = %CF
+  store i8 -59, i8* %0
+  br label %CF82
+
+CF82:                                             ; preds = %CF82, %CF82.critedge
+  %L17 = load i8* %0
+  %E18 = extractelement <2 x i64> undef, i32 0
+  %PC = bitcast <2 x i1>* %A3 to i64*
+  br i1 undef, label %CF82, label %CF84.critedge
+
+CF84.critedge:                                    ; preds = %CF82
+  store i64 455385, i64* %PC
+  br label %CF84
+
+CF84:                                             ; preds = %CF84, %CF84.critedge
+  %L40 = load i64* %PC
+  store i64 -1, i64* %PC
+  %Sl46 = select i1 undef, i1 undef, i1 false
+  br i1 %Sl46, label %CF84, label %CF85
+
+CF85:                                             ; preds = %CF84
+  %L47 = load i64* %PC
+  store i64 %E18, i64* %PC
+  %PC52 = bitcast <8 x i32>* %A2 to ppc_fp128*
+  store ppc_fp128 0xM4D436562A0416DE00000000000000000, ppc_fp128* %PC52
+  %PC59 = bitcast i64* %1 to i8*
+  %Cmp61 = icmp slt i64 %L47, %L40
+  br i1 %Cmp61, label %CF, label %CF77
+
+CF77:                                             ; preds = %CF77, %CF85
+  br i1 undef, label %CF77, label %CF81
+
+CF81:                                             ; preds = %CF77
+  store i8 %L17, i8* %PC59
+  ret void
+}
diff --git a/test/CodeGen/PowerPC/set0-v8i16.ll b/test/CodeGen/PowerPC/set0-v8i16.ll
new file mode 100644
index 0000000..13d51df
--- /dev/null
+++ b/test/CodeGen/PowerPC/set0-v8i16.ll
@@ -0,0 +1,18 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
+target triple = "powerpc64-unknown-linux-gnu"
+
+define void @autogen_SD367951() {
+BB:
+  %Shuff = shufflevector <16 x i16> zeroinitializer, <16 x i16> zeroinitializer, <16 x i32> <i32 26, i32 28, i32 30, i32 undef, i32 2, i32 4, i32 undef, i32 undef, i32 10, i32 undef, i32 14, i32 16, i32 undef, i32 20, i32 undef, i32 24>
+  %Shuff7 = shufflevector <16 x i16> zeroinitializer, <16 x i16> %Shuff, <16 x i32> <i32 20, i32 undef, i32 24, i32 26, i32 28, i32 undef, i32 0, i32 undef, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18>
+  %Cmp11 = icmp ugt <16 x i16> %Shuff7, zeroinitializer
+  %E27 = extractelement <16 x i1> %Cmp11, i32 5
+  br label %CF76
+
+CF76:                                             ; preds = %CF80, %CF76, %BB
+  br i1 undef, label %CF76, label %CF80
+
+CF80:                                             ; preds = %CF76
+  %Sl37 = select i1 %E27, <16 x i16> undef, <16 x i16> %Shuff
+  br label %CF76
+}
diff --git a/test/CodeGen/PowerPC/sj-ctr-loop.ll b/test/CodeGen/PowerPC/sj-ctr-loop.ll
new file mode 100644
index 0000000..1866bcd
--- /dev/null
+++ b/test/CodeGen/PowerPC/sj-ctr-loop.ll
@@ -0,0 +1,50 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.__jmp_buf_tag.1.15.17.21.25.49.53.55 = type { [64 x i64], i32, %struct.__sigset_t.0.14.16.20.24.48.52.54, [8 x i8] }
+%struct.__sigset_t.0.14.16.20.24.48.52.54 = type { [16 x i64] }
+
+@env_sigill = external global [1 x %struct.__jmp_buf_tag.1.15.17.21.25.49.53.55], align 16
+
+; CHECK-LABEL: @main
+; CHECK-NOT: mtctr
+
+; Function Attrs: nounwind
+define void @main() #0 {
+entry:
+  br i1 undef, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  br i1 undef, label %for.body.lr.ph, label %for.end.thread
+
+for.end.thread:                                   ; preds = %if.end
+  br label %return
+
+for.body.lr.ph:                                   ; preds = %if.end
+  br label %for.body
+
+for.cond:                                         ; preds = %for.body
+  %cmp2 = icmp slt i32 %inc, undef
+  br i1 %cmp2, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond, %for.body.lr.ph
+  %i.032 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.cond ]
+  %0 = call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([1 x %struct.__jmp_buf_tag.1.15.17.21.25.49.53.55]* @env_sigill to i8*))
+  %inc = add nsw i32 %i.032, 1
+  br i1 false, label %if.else, label %for.cond
+
+if.else:                                          ; preds = %for.body
+  unreachable
+
+for.end:                                          ; preds = %for.cond
+  unreachable
+
+return:                                           ; preds = %for.end.thread, %entry
+  ret void
+}
+
+; Function Attrs: nounwind
+declare i32 @llvm.eh.sjlj.setjmp(i8*) #0
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/PowerPC/sjlj.ll b/test/CodeGen/PowerPC/sjlj.ll
index 7ea35da..571f3b2 100644
--- a/test/CodeGen/PowerPC/sjlj.ll
+++ b/test/CodeGen/PowerPC/sjlj.ll
@@ -20,6 +20,7 @@ entry:
 ; CHECK: ld [[REG2:[0-9]+]], 8([[REG]])
 ; CHECK: ld 1, 16([[REG]])
 ; CHECK: mtctr [[REG2]]
+; CHECK: ld 30, 32([[REG]])
 ; CHECK: ld 2, 24([[REG]])
 ; CHECK: bctr
 
@@ -99,6 +100,52 @@ return:                                           ; preds = %if.end, %if.then
 ; CHECK-NOAV: blr
 }
 
+define signext i32 @main2() #0 {
+entry:
+  %a = alloca i8, align 64
+  call void @bar(i8* %a)
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = call i8* @llvm.frameaddress(i32 0)
+  store i8* %0, i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**)
+  %1 = call i8* @llvm.stacksave()
+  store i8* %1, i8** getelementptr (i8** bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8**), i32 2)
+  %2 = call i32 @llvm.eh.sjlj.setjmp(i8* bitcast ([1 x %struct.__jmp_buf_tag]* @env_sigill to i8*))
+  %tobool = icmp ne i32 %2, 0
+  br i1 %tobool, label %if.then, label %if.else
+
+if.then:                                          ; preds = %entry
+  store i32 1, i32* %retval
+  br label %return
+
+if.else:                                          ; preds = %entry
+  call void @foo()
+  br label %if.end
+
+if.end:                                           ; preds = %if.else
+  store i32 0, i32* %retval
+  br label %return
+
+return:                                           ; preds = %if.end, %if.then
+  %3 = load i32* %retval
+  ret i32 %3
+
+; CHECK: @main2
+
+; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha
+; CHECK: std 31, env_sigill@toc@l([[REG]])
+; CHECK: addi [[REG]], [[REG]], env_sigill@toc@l
+; CHECK: std [[REG]], [[OFF:[0-9]+]](31)                  # 8-byte Folded Spill
+; CHECK: std 1, 16([[REG]])
+; CHECK: std 2, 24([[REG]])
+; CHECK: std 30, 32([[REG]])
+; CHECK: bcl 20, 31,
+
+; CHECK: blr
+}
+
+declare void @bar(i8*) #3
+
 declare i8* @llvm.frameaddress(i32) #2
 
 declare i8* @llvm.stacksave() #3
diff --git a/test/CodeGen/PowerPC/stack-protector.ll b/test/CodeGen/PowerPC/stack-protector.ll
index 810630f..b81d941 100644
--- a/test/CodeGen/PowerPC/stack-protector.ll
+++ b/test/CodeGen/PowerPC/stack-protector.ll
@@ -1,5 +1,6 @@
-; RUN: llc -march=ppc32 < %s -o - | grep "__stack_chk_guard"
-; RUN: llc -march=ppc32 < %s -o - | grep "__stack_chk_fail"
+; RUN: llc -march=ppc32 -mtriple=ppc32-unknown-linux < %s | FileCheck %s
+; CHECK: __stack_chk_guard
+; CHECK: __stack_chk_fail
 
 @"\01LC" = internal constant [11 x i8] c"buf == %s\0A\00"		; <[11 x i8]*> [#uses=1]
 
diff --git a/test/CodeGen/PowerPC/stack-realign.ll b/test/CodeGen/PowerPC/stack-realign.ll
new file mode 100644
index 0000000..f7b6d19
--- /dev/null
+++ b/test/CodeGen/PowerPC/stack-realign.ll
@@ -0,0 +1,151 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -disable-fp-elim < %s | FileCheck -check-prefix=CHECK-FP %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.s = type { i32, i32 }
+
+declare void @bar(i32*)
+
+define void @goo(%struct.s* byval nocapture readonly %a) {
+entry:
+  %x = alloca [2 x i32], align 32
+  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
+  %0 = load i32* %a1, align 4, !tbaa !0
+  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
+  store i32 %0, i32* %arrayidx, align 32, !tbaa !0
+  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
+  %1 = load i32* %b, align 4, !tbaa !0
+  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
+  store i32 %1, i32* %arrayidx2, align 4, !tbaa !0
+  call void @bar(i32* %arrayidx)
+  ret void
+}
+
+; CHECK-LABEL: @goo
+
+; CHECK-DAG: mflr 0
+; CHECK-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59
+; CHECK-DAG: std 30, -16(1)
+; CHECK-DAG: mr 30, 1
+; CHECK-DAG: std 0, 16(1)
+; CHECK-DAG: subfic 0, [[REG]], -160
+; CHECK: stdux 1, 1, 0
+
+; CHECK: .cfi_offset r30, -16
+; CHECK: .cfi_offset lr, 16
+
+; CHECK: std 3, 48(30)
+
+; CHECK: ld 1, 0(1)
+; CHECK-DAG: ld 0, 16(1)
+; CHECK-DAG: ld 30, -16(1)
+; CHECK-DAG: mtlr 0
+; CHECK: blr
+
+; CHECK-FP-LABEL: @goo
+
+; CHECK-FP-DAG: mflr 0
+; CHECK-FP-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59
+; CHECK-FP-DAG: std 31, -8(1)
+; CHECK-FP-DAG: std 30, -16(1)
+; CHECK-FP-DAG: mr 30, 1
+; CHECK-FP-DAG: std 0, 16(1)
+; CHECK-FP-DAG: subfic 0, [[REG]], -160
+; CHECK-FP: stdux 1, 1, 0
+
+; CHECK-FP: .cfi_offset r31, -8
+; CHECK-FP: .cfi_offset r30, -16
+; CHECK-FP: .cfi_offset lr, 16
+
+; CHECK-FP: mr 31, 1
+
+; CHECK-FP: std 3, 48(30)
+
+; CHECK-FP: ld 1, 0(1)
+; CHECK-FP-DAG: ld 0, 16(1)
+; CHECK-FP-DAG: ld 31, -8(1)
+; CHECK-FP-DAG: ld 30, -16(1)
+; CHECK-FP-DAG: mtlr 0
+; CHECK-FP: blr
+
+; The large-frame-size case.
+define void @hoo(%struct.s* byval nocapture readonly %a) {
+entry:
+  %x = alloca [200000 x i32], align 32
+  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
+  %0 = load i32* %a1, align 4, !tbaa !0
+  %arrayidx = getelementptr inbounds [200000 x i32]* %x, i64 0, i64 0
+  store i32 %0, i32* %arrayidx, align 32, !tbaa !0
+  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
+  %1 = load i32* %b, align 4, !tbaa !0
+  %arrayidx2 = getelementptr inbounds [200000 x i32]* %x, i64 0, i64 1
+  store i32 %1, i32* %arrayidx2, align 4, !tbaa !0
+  call void @bar(i32* %arrayidx)
+  ret void
+}
+
+; CHECK-LABEL: @hoo
+
+; CHECK-DAG: lis [[REG1:[0-9]+]], -13
+; CHECK-DAG: rldicl [[REG3:[0-9]+]], 1, 0, 59
+; CHECK-DAG: mflr 0
+; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51808
+; CHECK-DAG: std 30, -16(1)
+; CHECK-DAG: mr 30, 1
+; CHECK-DAG: std 0, 16(1)
+; CHECK-DAG: subfc 0, [[REG3]], [[REG2]]
+; CHECK: stdux 1, 1, 0
+
+; CHECK: blr
+
+; Make sure that the FP save area is still allocated correctly relative to
+; where r30 is saved.
+define void @loo(%struct.s* byval nocapture readonly %a) {
+entry:
+  %x = alloca [2 x i32], align 32
+  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
+  %0 = load i32* %a1, align 4, !tbaa !0
+  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
+  store i32 %0, i32* %arrayidx, align 32, !tbaa !0
+  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
+  %1 = load i32* %b, align 4, !tbaa !0
+  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
+  store i32 %1, i32* %arrayidx2, align 4, !tbaa !0
+  call void @bar(i32* %arrayidx)
+  call void asm sideeffect "", "~{f30}"() nounwind
+  ret void
+}
+
+; CHECK-LABEL: @loo
+
+; CHECK-DAG: mflr 0
+; CHECK-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59
+; CHECK-DAG: std 30, -32(1)
+; CHECK-DAG: mr 30, 1
+; CHECK-DAG: std 0, 16(1)
+; CHECK-DAG: subfic 0, [[REG]], -192
+; CHECK: stdux 1, 1, 0
+
+; CHECK: stfd 30, -16(30)
+
+; CHECK: blr
+
+; CHECK-FP-LABEL: @loo
+
+; CHECK-FP-DAG: mflr 0
+; CHECK-FP-DAG: rldicl [[REG:[0-9]+]], 1, 0, 59
+; CHECK-FP-DAG: std 31, -24(1)
+; CHECK-FP-DAG: std 30, -32(1)
+; CHECK-FP-DAG: mr 30, 1
+; CHECK-FP-DAG: std 0, 16(1)
+; CHECK-FP-DAG: subfic 0, [[REG]], -192
+; CHECK-FP: stdux 1, 1, 0
+
+; CHECK-FP: stfd 30, -16(30)
+
+; CHECK-FP: blr
+
+!0 = metadata !{metadata !"int", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA"}
diff --git a/test/CodeGen/PowerPC/std-unal-fi.ll b/test/CodeGen/PowerPC/std-unal-fi.ll
new file mode 100644
index 0000000..8b9606e
--- /dev/null
+++ b/test/CodeGen/PowerPC/std-unal-fi.ll
@@ -0,0 +1,119 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
+target triple = "powerpc64-unknown-linux-gnu"
+
+define void @autogen_SD4932(i8) {
+BB:
+  %A4 = alloca i8
+  %A = alloca <1 x ppc_fp128>
+  %Shuff = shufflevector <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> <i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 undef, i32 29, i32 31, i32 1, i32 3, i32 5>
+  br label %CF
+
+CF:                                               ; preds = %CF80, %CF, %BB
+  %L5 = load i64* undef
+  store i8 %0, i8* %A4
+  %Shuff7 = shufflevector <16 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <16 x i32> %Shuff, <16 x i32> <i32 28, i32 30, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 undef, i32 20, i32 22, i32 24, i32 26>
+  %PC10 = bitcast i8* %A4 to ppc_fp128*
+  br i1 undef, label %CF, label %CF77
+
+CF77:                                             ; preds = %CF81, %CF83, %CF77, %CF
+  br i1 undef, label %CF77, label %CF82
+
+CF82:                                             ; preds = %CF82, %CF77
+  %L19 = load i64* undef
+  store <1 x ppc_fp128> zeroinitializer, <1 x ppc_fp128>* %A
+  store i8 -65, i8* %A4
+  br i1 undef, label %CF82, label %CF83
+
+CF83:                                             ; preds = %CF82
+  %L34 = load i64* undef
+  br i1 undef, label %CF77, label %CF81
+
+CF81:                                             ; preds = %CF83
+  %Shuff43 = shufflevector <16 x i32> %Shuff7, <16 x i32> undef, <16 x i32> <i32 15, i32 17, i32 19, i32 21, i32 23, i32 undef, i32 undef, i32 29, i32 31, i32 undef, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13>
+  store ppc_fp128 0xM00000000000000000000000000000000, ppc_fp128* %PC10
+  br i1 undef, label %CF77, label %CF78
+
+CF78:                                             ; preds = %CF78, %CF81
+  br i1 undef, label %CF78, label %CF79
+
+CF79:                                             ; preds = %CF79, %CF78
+  br i1 undef, label %CF79, label %CF80
+
+CF80:                                             ; preds = %CF79
+  store i64 %L19, i64* undef
+  %Cmp75 = icmp uge i32 206779, undef
+  br i1 %Cmp75, label %CF, label %CF76
+
+CF76:                                             ; preds = %CF80
+  store i64 %L5, i64* undef
+  store i64 %L34, i64* undef
+  ret void
+}
+
+define void @autogen_SD88042(i8*, i32*, i8) {
+BB:
+  %A4 = alloca <2 x i1>
+  %A = alloca <16 x float>
+  %L = load i8* %0
+  %Sl = select i1 false, <16 x float>* %A, <16 x float>* %A
+  %PC = bitcast <2 x i1>* %A4 to i64*
+  %Sl27 = select i1 false, i8 undef, i8 %L
+  br label %CF
+
+CF:                                               ; preds = %CF78, %CF, %BB
+  %PC33 = bitcast i32* %1 to i32*
+  br i1 undef, label %CF, label %CF77
+
+CF77:                                             ; preds = %CF80, %CF77, %CF
+  store <16 x float> zeroinitializer, <16 x float>* %Sl
+  %L58 = load i32* %PC33
+  store i8 0, i8* %0
+  br i1 undef, label %CF77, label %CF80
+
+CF80:                                             ; preds = %CF77
+  store i64 0, i64* %PC
+  %E67 = extractelement <8 x i1> zeroinitializer, i32 1
+  br i1 %E67, label %CF77, label %CF78
+
+CF78:                                             ; preds = %CF80
+  %Cmp73 = icmp eq i32 189865, %L58
+  br i1 %Cmp73, label %CF, label %CF76
+
+CF76:                                             ; preds = %CF78
+  store i8 %2, i8* %0
+  store i8 %Sl27, i8* %0
+  ret void
+}
+
+define void @autogen_SD37497(i8*, i32*, i64*) {
+BB:
+  %A1 = alloca i1
+  %I8 = insertelement <1 x i32> <i32 -1>, i32 454855, i32 0
+  %Cmp = icmp ult <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, undef
+  %L10 = load i64* %2
+  %E11 = extractelement <4 x i1> %Cmp, i32 2
+  br label %CF72
+
+CF72:                                             ; preds = %CF74, %CF72, %BB
+  store double 0xB47BB29A53790718, double* undef
+  %E18 = extractelement <1 x i32> <i32 -1>, i32 0
+  %FC22 = sitofp <1 x i32> %I8 to <1 x float>
+  br i1 undef, label %CF72, label %CF74
+
+CF74:                                             ; preds = %CF72
+  store i8 0, i8* %0
+  %PC = bitcast i1* %A1 to i64*
+  %L31 = load i64* %PC
+  store i64 477323, i64* %PC
+  %Sl37 = select i1 false, i32* undef, i32* %1
+  %Cmp38 = icmp ugt i1 undef, undef
+  br i1 %Cmp38, label %CF72, label %CF73
+
+CF73:                                             ; preds = %CF74
+  store i64 %L31, i64* %PC
+  %B55 = fdiv <1 x float> undef, %FC22
+  %Sl63 = select i1 %E11, i32* undef, i32* %Sl37
+  store i32 %E18, i32* %Sl63
+  store i64 %L10, i64* %PC
+  ret void
+}
diff --git a/test/CodeGen/PowerPC/store-update.ll b/test/CodeGen/PowerPC/store-update.ll
index 538ed24..7b9e8f7 100644
--- a/test/CodeGen/PowerPC/store-update.ll
+++ b/test/CodeGen/PowerPC/store-update.ll
@@ -3,166 +3,166 @@
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
-define i8* @stbu(i8* %base, i8 zeroext %val) nounwind {
+define i8* @test_stbu(i8* %base, i8 zeroext %val) nounwind {
 entry:
   %arrayidx = getelementptr inbounds i8* %base, i64 16
   store i8 %val, i8* %arrayidx, align 1
   ret i8* %arrayidx
 }
-; CHECK: @stbu
+; CHECK: @test_stbu
 ; CHECK: %entry
 ; CHECK-NEXT: stbu
 ; CHECK-NEXT: blr
 
-define i8* @stbux(i8* %base, i8 zeroext %val, i64 %offset) nounwind {
+define i8* @test_stbux(i8* %base, i8 zeroext %val, i64 %offset) nounwind {
 entry:
   %arrayidx = getelementptr inbounds i8* %base, i64 %offset
   store i8 %val, i8* %arrayidx, align 1
   ret i8* %arrayidx
 }
-; CHECK: @stbux
+; CHECK: @test_stbux
 ; CHECK: %entry
 ; CHECK-NEXT: stbux
 ; CHECK-NEXT: blr
 
-define i16* @sthu(i16* %base, i16 zeroext %val) nounwind {
+define i16* @test_sthu(i16* %base, i16 zeroext %val) nounwind {
 entry:
   %arrayidx = getelementptr inbounds i16* %base, i64 16
   store i16 %val, i16* %arrayidx, align 2
   ret i16* %arrayidx
 }
-; CHECK: @sthu
+; CHECK: @test_sthu
 ; CHECK: %entry
 ; CHECK-NEXT: sthu
 ; CHECK-NEXT: blr
 
-define i16* @sthux(i16* %base, i16 zeroext %val, i64 %offset) nounwind {
+define i16* @test_sthux(i16* %base, i16 zeroext %val, i64 %offset) nounwind {
 entry:
   %arrayidx = getelementptr inbounds i16* %base, i64 %offset
   store i16 %val, i16* %arrayidx, align 2
   ret i16* %arrayidx
 }
-; CHECK: @sthux
+; CHECK: @test_sthux
 ; CHECK: %entry
 ; CHECK-NEXT: sldi
 ; CHECK-NEXT: sthux
 ; CHECK-NEXT: blr
 
-define i32* @stwu(i32* %base, i32 zeroext %val) nounwind {
+define i32* @test_stwu(i32* %base, i32 zeroext %val) nounwind {
 entry:
   %arrayidx = getelementptr inbounds i32* %base, i64 16
   store i32 %val, i32* %arrayidx, align 4
   ret i32* %arrayidx
 }
-; CHECK: @stwu
+; CHECK: @test_stwu
 ; CHECK: %entry
 ; CHECK-NEXT: stwu
 ; CHECK-NEXT: blr
 
-define i32* @stwux(i32* %base, i32 zeroext %val, i64 %offset) nounwind {
+define i32* @test_stwux(i32* %base, i32 zeroext %val, i64 %offset) nounwind {
 entry:
   %arrayidx = getelementptr inbounds i32* %base, i64 %offset
   store i32 %val, i32* %arrayidx, align 4
   ret i32* %arrayidx
 }
-; CHECK: @stwux
+; CHECK: @test_stwux
 ; CHECK: %entry
 ; CHECK-NEXT: sldi
 ; CHECK-NEXT: stwux
 ; CHECK-NEXT: blr
 
-define i8* @stbu8(i8* %base, i64 %val) nounwind {
+define i8* @test_stbu8(i8* %base, i64 %val) nounwind {
 entry:
   %conv = trunc i64 %val to i8
   %arrayidx = getelementptr inbounds i8* %base, i64 16
   store i8 %conv, i8* %arrayidx, align 1
   ret i8* %arrayidx
 }
-; CHECK: @stbu
+; CHECK: @test_stbu8
 ; CHECK: %entry
 ; CHECK-NEXT: stbu
 ; CHECK-NEXT: blr
 
-define i8* @stbux8(i8* %base, i64 %val, i64 %offset) nounwind {
+define i8* @test_stbux8(i8* %base, i64 %val, i64 %offset) nounwind {
 entry:
   %conv = trunc i64 %val to i8
   %arrayidx = getelementptr inbounds i8* %base, i64 %offset
   store i8 %conv, i8* %arrayidx, align 1
   ret i8* %arrayidx
 }
-; CHECK: @stbux
+; CHECK: @test_stbux8
 ; CHECK: %entry
 ; CHECK-NEXT: stbux
 ; CHECK-NEXT: blr
 
-define i16* @sthu8(i16* %base, i64 %val) nounwind {
+define i16* @test_sthu8(i16* %base, i64 %val) nounwind {
 entry:
   %conv = trunc i64 %val to i16
   %arrayidx = getelementptr inbounds i16* %base, i64 16
   store i16 %conv, i16* %arrayidx, align 2
   ret i16* %arrayidx
 }
-; CHECK: @sthu
+; CHECK: @test_sthu
 ; CHECK: %entry
 ; CHECK-NEXT: sthu
 ; CHECK-NEXT: blr
 
-define i16* @sthux8(i16* %base, i64 %val, i64 %offset) nounwind {
+define i16* @test_sthux8(i16* %base, i64 %val, i64 %offset) nounwind {
 entry:
   %conv = trunc i64 %val to i16
   %arrayidx = getelementptr inbounds i16* %base, i64 %offset
   store i16 %conv, i16* %arrayidx, align 2
   ret i16* %arrayidx
 }
-; CHECK: @sthux
+; CHECK: @test_sthux
 ; CHECK: %entry
 ; CHECK-NEXT: sldi
 ; CHECK-NEXT: sthux
 ; CHECK-NEXT: blr
 
-define i32* @stwu8(i32* %base, i64 %val) nounwind {
+define i32* @test_stwu8(i32* %base, i64 %val) nounwind {
 entry:
   %conv = trunc i64 %val to i32
   %arrayidx = getelementptr inbounds i32* %base, i64 16
   store i32 %conv, i32* %arrayidx, align 4
   ret i32* %arrayidx
 }
-; CHECK: @stwu
+; CHECK: @test_stwu
 ; CHECK: %entry
 ; CHECK-NEXT: stwu
 ; CHECK-NEXT: blr
 
-define i32* @stwux8(i32* %base, i64 %val, i64 %offset) nounwind {
+define i32* @test_stwux8(i32* %base, i64 %val, i64 %offset) nounwind {
 entry:
   %conv = trunc i64 %val to i32
   %arrayidx = getelementptr inbounds i32* %base, i64 %offset
   store i32 %conv, i32* %arrayidx, align 4
   ret i32* %arrayidx
 }
-; CHECK: @stwux
+; CHECK: @test_stwux
 ; CHECK: %entry
 ; CHECK-NEXT: sldi
 ; CHECK-NEXT: stwux
 ; CHECK-NEXT: blr
 
-define i64* @stdu(i64* %base, i64 %val) nounwind {
+define i64* @test_stdu(i64* %base, i64 %val) nounwind {
 entry:
   %arrayidx = getelementptr inbounds i64* %base, i64 16
   store i64 %val, i64* %arrayidx, align 8
   ret i64* %arrayidx
 }
-; CHECK: @stdu
+; CHECK: @test_stdu
 ; CHECK: %entry
 ; CHECK-NEXT: stdu
 ; CHECK-NEXT: blr
 
-define i64* @stdux(i64* %base, i64 %val, i64 %offset) nounwind {
+define i64* @test_stdux(i64* %base, i64 %val, i64 %offset) nounwind {
 entry:
   %arrayidx = getelementptr inbounds i64* %base, i64 %offset
   store i64 %val, i64* %arrayidx, align 8
   ret i64* %arrayidx
 }
-; CHECK: @stdux
+; CHECK: @test_stdux
 ; CHECK: %entry
 ; CHECK-NEXT: sldi
 ; CHECK-NEXT: stdux
diff --git a/test/CodeGen/PowerPC/structsinmem.ll b/test/CodeGen/PowerPC/structsinmem.ll
index 2a17e74..5b8dead 100644
--- a/test/CodeGen/PowerPC/structsinmem.ll
+++ b/test/CodeGen/PowerPC/structsinmem.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
diff --git a/test/CodeGen/PowerPC/structsinregs.ll b/test/CodeGen/PowerPC/structsinregs.ll
index 54de606..fb3bd7c 100644
--- a/test/CodeGen/PowerPC/structsinregs.ll
+++ b/test/CodeGen/PowerPC/structsinregs.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -disable-fp-elim -fast-isel=false < %s | FileCheck %s
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
diff --git a/test/CodeGen/PowerPC/sub-bv-types.ll b/test/CodeGen/PowerPC/sub-bv-types.ll
new file mode 100644
index 0000000..c72fae6
--- /dev/null
+++ b/test/CodeGen/PowerPC/sub-bv-types.ll
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
+target triple = "powerpc64-unknown-linux-gnu"
+
+define void @autogen_SD10521() {
+BB:
+  %Shuff7 = shufflevector <16 x i16> zeroinitializer, <16 x i16> zeroinitializer, <16 x i32> <i32 undef, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 undef, i32 22, i32 undef, i32 26, i32 undef, i32 30>
+  br label %CF
+
+CF:                                               ; preds = %CF78, %CF, %BB
+  %I27 = insertelement <16 x i16> %Shuff7, i16 1360, i32 8
+  %B28 = sub <16 x i16> %I27, %Shuff7
+  br i1 undef, label %CF, label %CF78
+
+CF78:                                             ; preds = %CF
+  %B42 = xor <16 x i16> %B28, %Shuff7
+  br label %CF
+}
diff --git a/test/CodeGen/PowerPC/svr4-redzone.ll b/test/CodeGen/PowerPC/svr4-redzone.ll
index 91ff579..7c51b67 100644
--- a/test/CodeGen/PowerPC/svr4-redzone.ll
+++ b/test/CodeGen/PowerPC/svr4-redzone.ll
@@ -7,11 +7,11 @@ entry:
 	%0 = add i32 1, 2
 	ret void
 }
-; PPC32: regalloc:
+; PPC32-LABEL: regalloc:
 ; PPC32-NOT: stwu 1, -{{[0-9]+}}(1)
 ; PPC32: blr
 
-; PPC64: regalloc:
+; PPC64-LABEL: regalloc:
 ; PPC64-NOT: stdu 1, -{{[0-9]+}}(1)
 ; PPC64: blr
 
@@ -20,10 +20,10 @@ entry:
 	%0 = alloca i8, i32 4
 	ret void
 }
-; PPC32: smallstack:
+; PPC32-LABEL: smallstack:
 ; PPC32: stwu 1, -16(1)
 
-; PPC64: smallstack:
+; PPC64-LABEL: smallstack:
 ; PPC64-NOT: stdu 1, -{{[0-9]+}}(1)
 ; PPC64: blr
 
@@ -32,8 +32,8 @@ entry:
 	%0 = alloca i8, i32 230
 	ret void
 }
-; PPC32: bigstack:
+; PPC32-LABEL: bigstack:
 ; PPC32: stwu 1, -240(1)
 
-; PPC64: bigstack:
+; PPC64-LABEL: bigstack:
 ; PPC64: stdu 1, -352(1)
diff --git a/test/CodeGen/PowerPC/tls-2.ll b/test/CodeGen/PowerPC/tls-2.ll
index 20d8fe4..c2faf90 100644
--- a/test/CodeGen/PowerPC/tls-2.ll
+++ b/test/CodeGen/PowerPC/tls-2.ll
@@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-freebsd10.0"
 
 @a = thread_local global i32 0, align 4
 
-;CHECK:          localexec:
+;CHECK-LABEL:          localexec:
 define i32 @localexec() nounwind {
 entry:
 ;CHECK:          addis [[REG1:[0-9]+]], 13, a@tprel@ha
diff --git a/test/CodeGen/PowerPC/tls.ll b/test/CodeGen/PowerPC/tls.ll
index 2daa60a..4e0a822 100644
--- a/test/CodeGen/PowerPC/tls.ll
+++ b/test/CodeGen/PowerPC/tls.ll
@@ -5,8 +5,8 @@ target triple = "powerpc64-unknown-freebsd10.0"
 
 @a = thread_local global i32 0, align 4
 
-;OPT0:          localexec:
-;OPT1:          localexec:
+;OPT0-LABEL:          localexec:
+;OPT1-LABEL:          localexec:
 define i32 @localexec() nounwind {
 entry:
 ;OPT0:          addis [[REG1:[0-9]+]], 13, a@tprel@ha
diff --git a/test/CodeGen/PowerPC/unwind-dw2-g.ll b/test/CodeGen/PowerPC/unwind-dw2-g.ll
new file mode 100644
index 0000000..2baac76
--- /dev/null
+++ b/test/CodeGen/PowerPC/unwind-dw2-g.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define void @foo() #0 {
+entry:
+  call void @llvm.eh.unwind.init(), !dbg !9
+  ret void, !dbg !10
+}
+
+; CHECK: @foo
+; CHECK-NOT: .cfi_offset vrsave
+; CHECK: blr
+
+; Function Attrs: nounwind
+declare void @llvm.eh.unwind.init() #0
+
+attributes #0 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!8}
+
+!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.4", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/unwind-dw2.c] [DW_LANG_C99]
+!1 = metadata !{metadata !"/tmp/unwind-dw2.c", metadata !"/tmp"}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"foo", metadata !"foo", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void ()* @foo, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [foo]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [/tmp/unwind-dw2.c]
+!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{null}
+!8 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}
+!9 = metadata !{i32 2, i32 0, metadata !4, null}
+!10 = metadata !{i32 3, i32 0, metadata !4, null}
diff --git a/test/CodeGen/PowerPC/unwind-dw2.ll b/test/CodeGen/PowerPC/unwind-dw2.ll
new file mode 100644
index 0000000..e58edff
--- /dev/null
+++ b/test/CodeGen/PowerPC/unwind-dw2.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define void @foo() #0 {
+entry:
+  call void @llvm.eh.unwind.init()
+  ret void
+}
+
+; Function Attrs: nounwind
+declare void @llvm.eh.unwind.init() #0
+
+attributes #0 = { nounwind }
diff --git a/test/CodeGen/PowerPC/vaddsplat.ll b/test/CodeGen/PowerPC/vaddsplat.ll
index e65148a..4236fab 100644
--- a/test/CodeGen/PowerPC/vaddsplat.ll
+++ b/test/CodeGen/PowerPC/vaddsplat.ll
@@ -16,7 +16,7 @@ define void @test_v4i32_pos_even(%v4i32* %P, %v4i32* %S) {
        ret void
 }
 
-; CHECK: test_v4i32_pos_even:
+; CHECK-LABEL: test_v4i32_pos_even:
 ; CHECK: vspltisw [[REG1:[0-9]+]], 9
 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -27,7 +27,7 @@ define void @test_v4i32_neg_even(%v4i32* %P, %v4i32* %S) {
        ret void
 }
 
-; CHECK: test_v4i32_neg_even:
+; CHECK-LABEL: test_v4i32_neg_even:
 ; CHECK: vspltisw [[REG1:[0-9]+]], -14
 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -38,7 +38,7 @@ define void @test_v8i16_pos_even(%v8i16* %P, %v8i16* %S) {
        ret void
 }
 
-; CHECK: test_v8i16_pos_even:
+; CHECK-LABEL: test_v8i16_pos_even:
 ; CHECK: vspltish [[REG1:[0-9]+]], 15
 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -49,7 +49,7 @@ define void @test_v8i16_neg_even(%v8i16* %P, %v8i16* %S) {
        ret void
 }
 
-; CHECK: test_v8i16_neg_even:
+; CHECK-LABEL: test_v8i16_neg_even:
 ; CHECK: vspltish [[REG1:[0-9]+]], -16
 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -60,7 +60,7 @@ define void @test_v16i8_pos_even(%v16i8* %P, %v16i8* %S) {
        ret void
 }
 
-; CHECK: test_v16i8_pos_even:
+; CHECK-LABEL: test_v16i8_pos_even:
 ; CHECK: vspltisb [[REG1:[0-9]+]], 8
 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -71,7 +71,7 @@ define void @test_v16i8_neg_even(%v16i8* %P, %v16i8* %S) {
        ret void
 }
 
-; CHECK: test_v16i8_neg_even:
+; CHECK-LABEL: test_v16i8_neg_even:
 ; CHECK: vspltisb [[REG1:[0-9]+]], -9
 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -82,7 +82,7 @@ define void @test_v4i32_pos_odd(%v4i32* %P, %v4i32* %S) {
        ret void
 }
 
-; CHECK: test_v4i32_pos_odd:
+; CHECK-LABEL: test_v4i32_pos_odd:
 ; CHECK: vspltisw [[REG2:[0-9]+]], -16
 ; CHECK: vspltisw [[REG1:[0-9]+]], 11
 ; CHECK: vsubuwm {{[0-9]+}}, [[REG1]], [[REG2]]
@@ -94,7 +94,7 @@ define void @test_v4i32_neg_odd(%v4i32* %P, %v4i32* %S) {
        ret void
 }
 
-; CHECK: test_v4i32_neg_odd:
+; CHECK-LABEL: test_v4i32_neg_odd:
 ; CHECK: vspltisw [[REG2:[0-9]+]], -16
 ; CHECK: vspltisw [[REG1:[0-9]+]], -11
 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG2]]
@@ -106,7 +106,7 @@ define void @test_v8i16_pos_odd(%v8i16* %P, %v8i16* %S) {
        ret void
 }
 
-; CHECK: test_v8i16_pos_odd:
+; CHECK-LABEL: test_v8i16_pos_odd:
 ; CHECK: vspltish [[REG2:[0-9]+]], -16
 ; CHECK: vspltish [[REG1:[0-9]+]], 15
 ; CHECK: vsubuhm {{[0-9]+}}, [[REG1]], [[REG2]]
@@ -118,7 +118,7 @@ define void @test_v8i16_neg_odd(%v8i16* %P, %v8i16* %S) {
        ret void
 }
 
-; CHECK: test_v8i16_neg_odd:
+; CHECK-LABEL: test_v8i16_neg_odd:
 ; CHECK: vspltish [[REG2:[0-9]+]], -16
 ; CHECK: vspltish [[REG1:[0-9]+]], -15
 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG2]]
@@ -130,7 +130,7 @@ define void @test_v16i8_pos_odd(%v16i8* %P, %v16i8* %S) {
        ret void
 }
 
-; CHECK: test_v16i8_pos_odd:
+; CHECK-LABEL: test_v16i8_pos_odd:
 ; CHECK: vspltisb [[REG2:[0-9]+]], -16
 ; CHECK: vspltisb [[REG1:[0-9]+]], 1
 ; CHECK: vsububm {{[0-9]+}}, [[REG1]], [[REG2]]
@@ -142,7 +142,7 @@ define void @test_v16i8_neg_odd(%v16i8* %P, %v16i8* %S) {
        ret void
 }
 
-; CHECK: test_v16i8_neg_odd:
+; CHECK-LABEL: test_v16i8_neg_odd:
 ; CHECK: vspltisb [[REG2:[0-9]+]], -16
 ; CHECK: vspltisb [[REG1:[0-9]+]], -1
 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG2]]
diff --git a/test/CodeGen/PowerPC/varargs.ll b/test/CodeGen/PowerPC/varargs.ll
index 90f0480..dfd2056 100644
--- a/test/CodeGen/PowerPC/varargs.ll
+++ b/test/CodeGen/PowerPC/varargs.ll
@@ -7,14 +7,14 @@ define i8* @test1(i8** %foo) nounwind {
   ret i8* %A
 }
 
-; P32: test1:
+; P32-LABEL: test1:
 ; P32: lwz r2, 0(r3)
 ; P32: addi r4, r2, 4
 ; P32: stw r4, 0(r3)
 ; P32: lwz r3, 0(r2)
 ; P32: blr 
 
-; P64: test1:
+; P64-LABEL: test1:
 ; P64: ld r2, 0(r3)
 ; P64: addi r4, r2, 8
 ; P64: std r4, 0(r3)
diff --git a/test/CodeGen/PowerPC/vec_cmp.ll b/test/CodeGen/PowerPC/vec_cmp.ll
index eb41667..83e0e02 100644
--- a/test/CodeGen/PowerPC/vec_cmp.ll
+++ b/test/CodeGen/PowerPC/vec_cmp.ll
@@ -14,7 +14,7 @@ define <2 x i8> @v2si8_cmp(<2 x i8> %x, <2 x i8> %y) nounwind readnone {
   %sext = sext <2 x i1> %cmp to <2 x i8>
   ret <2 x i8> %sext
 }
-; CHECK: v2si8_cmp:
+; CHECK-LABEL: v2si8_cmp:
 ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -23,7 +23,7 @@ define <4 x i8> @v4si8_cmp(<4 x i8> %x, <4 x i8> %y) nounwind readnone {
   %sext = sext <4 x i1> %cmp to <4 x i8>
   ret <4 x i8> %sext
 }
-; CHECK: v4si8_cmp:
+; CHECK-LABEL: v4si8_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -32,7 +32,7 @@ define <8 x i8> @v8si8_cmp(<8 x i8> %x, <8 x i8> %y) nounwind readnone {
   %sext = sext <8 x i1> %cmp to <8 x i8>
   ret <8 x i8> %sext
 }
-; CHECK: v8si8_cmp:
+; CHECK-LABEL: v8si8_cmp:
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -43,7 +43,7 @@ define <16 x i8> @v16si8_cmp_eq(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK: v16si8_cmp_eq:
+; CHECK-LABEL: v16si8_cmp_eq:
 ; CHECK: vcmpequb 2, 2, 3
 
 define <16 x i8> @v16si8_cmp_ne(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -52,7 +52,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK:     v16si8_cmp_ne:
+; CHECK-LABEL:     v16si8_cmp_ne:
 ; CHECK:     vcmpequb [[RET:[0-9]+]], 2, 3
 ; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
 
@@ -62,7 +62,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK:      v16si8_cmp_le:
+; CHECK-LABEL:      v16si8_cmp_le:
 ; CHECK:      vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsb [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -73,7 +73,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK:      v16ui8_cmp_le:
+; CHECK-LABEL:      v16ui8_cmp_le:
 ; CHECK:      vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtub [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -84,7 +84,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK: v16si8_cmp_lt:
+; CHECK-LABEL: v16si8_cmp_lt:
 ; CHECK: vcmpgtsb 2, 3, 2
 
 define <16 x i8> @v16ui8_cmp_lt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -93,7 +93,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK: v16ui8_cmp_lt:
+; CHECK-LABEL: v16ui8_cmp_lt:
 ; CHECK: vcmpgtub 2, 3, 2
 
 define <16 x i8> @v16si8_cmp_gt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -102,7 +102,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK: v16si8_cmp_gt:
+; CHECK-LABEL: v16si8_cmp_gt:
 ; CHECK: vcmpgtsb 2, 2, 3
 
 define <16 x i8> @v16ui8_cmp_gt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -111,7 +111,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK: v16ui8_cmp_gt:
+; CHECK-LABEL: v16ui8_cmp_gt:
 ; CHECK: vcmpgtub 2, 2, 3
 
 define <16 x i8> @v16si8_cmp_ge(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -120,7 +120,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK:      v16si8_cmp_ge:
+; CHECK-LABEL:      v16si8_cmp_ge:
 ; CHECK:      vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsb [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -131,7 +131,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK:      v16ui8_cmp_ge:
+; CHECK-LABEL:      v16ui8_cmp_ge:
 ; CHECK:      vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtub [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -142,7 +142,7 @@ define <32 x i8> @v32si8_cmp(<32 x i8> %x, <32 x i8> %y) nounwind readnone {
   %sext = sext <32 x i1> %cmp to <32 x i8>
   ret <32 x i8> %sext
 }
-; CHECK: v32si8_cmp:
+; CHECK-LABEL: v32si8_cmp:
 ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
@@ -152,7 +152,7 @@ define <2 x i16> @v2si16_cmp(<2 x i16> %x, <2 x i16> %y) nounwind readnone {
   %sext = sext <2 x i1> %cmp to <2 x i16>
   ret <2 x i16> %sext
 }
-; CHECK: v2si16_cmp:
+; CHECK-LABEL: v2si16_cmp:
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -161,7 +161,7 @@ define <4 x i16> @v4si16_cmp(<4 x i16> %x, <4 x i16> %y) nounwind readnone {
   %sext = sext <4 x i1> %cmp to <4 x i16>
   ret <4 x i16> %sext
 }
-; CHECK: v4si16_cmp:
+; CHECK-LABEL: v4si16_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -173,7 +173,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK: v8si16_cmp_eq:
+; CHECK-LABEL: v8si16_cmp_eq:
 ; CHECK: vcmpequh 2, 2, 3
 
 define <8 x i16> @v8si16_cmp_ne(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -182,7 +182,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK:      v8si16_cmp_ne:
+; CHECK-LABEL:      v8si16_cmp_ne:
 ; CHECK:      vcmpequh [[RET:[0-9]+]], 2, 3
 ; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
 
@@ -192,7 +192,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK:      v8si16_cmp_le:
+; CHECK-LABEL:      v8si16_cmp_le:
 ; CHECK:      vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsh [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -203,7 +203,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK:      v8ui16_cmp_le:
+; CHECK-LABEL:      v8ui16_cmp_le:
 ; CHECK:      vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtuh [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -214,7 +214,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK: v8si16_cmp_lt:
+; CHECK-LABEL: v8si16_cmp_lt:
 ; CHECK: vcmpgtsh 2, 3, 2
 
 define <8 x i16> @v8ui16_cmp_lt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -223,7 +223,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK: v8ui16_cmp_lt:
+; CHECK-LABEL: v8ui16_cmp_lt:
 ; CHECK: vcmpgtuh 2, 3, 2
 
 define <8 x i16> @v8si16_cmp_gt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -232,7 +232,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK: v8si16_cmp_gt:
+; CHECK-LABEL: v8si16_cmp_gt:
 ; CHECK: vcmpgtsh 2, 2, 3
 
 define <8 x i16> @v8ui16_cmp_gt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -241,7 +241,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK: v8ui16_cmp_gt:
+; CHECK-LABEL: v8ui16_cmp_gt:
 ; CHECK: vcmpgtuh 2, 2, 3
 
 define <8 x i16> @v8si16_cmp_ge(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -250,7 +250,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK:      v8si16_cmp_ge:
+; CHECK-LABEL:      v8si16_cmp_ge:
 ; CHECK:      vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsh [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -261,7 +261,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK:      v8ui16_cmp_ge:
+; CHECK-LABEL:      v8ui16_cmp_ge:
 ; CHECK:      vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtuh [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -272,7 +272,7 @@ define <16 x i16> @v16si16_cmp(<16 x i16> %x, <16 x i16> %y) nounwind readnone {
   %sext = sext <16 x i1> %cmp to <16 x i16>
   ret <16 x i16> %sext
 }
-; CHECK: v16si16_cmp:
+; CHECK-LABEL: v16si16_cmp:
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
@@ -282,7 +282,7 @@ define <32 x i16> @v32si16_cmp(<32 x i16> %x, <32 x i16> %y) nounwind readnone {
   %sext = sext <32 x i1> %cmp to <32 x i16>
   ret <32 x i16> %sext
 }
-; CHECK: v32si16_cmp:
+; CHECK-LABEL: v32si16_cmp:
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -294,7 +294,7 @@ define <2 x i32> @v2si32_cmp(<2 x i32> %x, <2 x i32> %y) nounwind readnone {
   %sext = sext <2 x i1> %cmp to <2 x i32>
   ret <2 x i32> %sext
 }
-; CHECK: v2si32_cmp:
+; CHECK-LABEL: v2si32_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -306,7 +306,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK: v4si32_cmp_eq:
+; CHECK-LABEL: v4si32_cmp_eq:
 ; CHECK: vcmpequw 2, 2, 3
 
 define <4 x i32> @v4si32_cmp_ne(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -315,7 +315,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK:      v4si32_cmp_ne:
+; CHECK-LABEL:      v4si32_cmp_ne:
 ; CHECK:      vcmpequw [[RCMP:[0-9]+]], 2, 3
 ; CHECK-NEXT: vnor     2, [[RCMP]], [[RCMP]]
 
@@ -325,7 +325,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK:      v4si32_cmp_le:
+; CHECK-LABEL:      v4si32_cmp_le:
 ; CHECK:      vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsw [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -336,7 +336,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK:      v4ui32_cmp_le:
+; CHECK-LABEL:      v4ui32_cmp_le:
 ; CHECK:      vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtuw [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -347,7 +347,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK: v4si32_cmp_lt:
+; CHECK-LABEL: v4si32_cmp_lt:
 ; CHECK: vcmpgtsw 2, 3, 2
 
 define <4 x i32> @v4ui32_cmp_lt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -356,7 +356,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK: v4ui32_cmp_lt:
+; CHECK-LABEL: v4ui32_cmp_lt:
 ; CHECK: vcmpgtuw 2, 3, 2
 
 define <4 x i32> @v4si32_cmp_gt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -365,7 +365,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK: v4si32_cmp_gt:
+; CHECK-LABEL: v4si32_cmp_gt:
 ; CHECK: vcmpgtsw 2, 2, 3
 
 define <4 x i32> @v4ui32_cmp_gt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -374,7 +374,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK: v4ui32_cmp_gt:
+; CHECK-LABEL: v4ui32_cmp_gt:
 ; CHECK: vcmpgtuw 2, 2, 3
 
 define <4 x i32> @v4si32_cmp_ge(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -383,7 +383,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK:      v4si32_cmp_ge:
+; CHECK-LABEL:      v4si32_cmp_ge:
 ; CHECK:      vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsw [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -394,7 +394,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK:      v4ui32_cmp_ge:
+; CHECK-LABEL:      v4ui32_cmp_ge:
 ; CHECK:      vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtuw [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -405,7 +405,7 @@ define <8 x i32> @v8si32_cmp(<8 x i32> %x, <8 x i32> %y) nounwind readnone {
   %sext = sext <8 x i1> %cmp to <8 x i32>
   ret <8 x i32> %sext
 }
-; CHECK: v8si32_cmp:
+; CHECK-LABEL: v8si32_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
@@ -415,7 +415,7 @@ define <16 x i32> @v16si32_cmp(<16 x i32> %x, <16 x i32> %y) nounwind readnone {
   %sext = sext <16 x i1> %cmp to <16 x i32>
   ret <16 x i32> %sext
 }
-; CHECK: v16si32_cmp:
+; CHECK-LABEL: v16si32_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -427,7 +427,7 @@ define <32 x i32> @v32si32_cmp(<32 x i32> %x, <32 x i32> %y) nounwind readnone {
   %sext = sext <32 x i1> %cmp to <32 x i32>
   ret <32 x i32> %sext
 }
-; CHECK: v32si32_cmp:
+; CHECK-LABEL: v32si32_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -445,7 +445,7 @@ entry:
   %0 = bitcast <2 x i32> %sext to <2 x float>
   ret <2 x float> %0
 }
-; CHECK: v2f32_cmp:
+; CHECK-LABEL: v2f32_cmp:
 ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -458,7 +458,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK: v4f32_cmp_eq:
+; CHECK-LABEL: v4f32_cmp_eq:
 ; CHECK: vcmpeqfp 2, 2, 3
 
 define <4 x float> @v4f32_cmp_ne(<4 x float> %x, <4 x float> %y) nounwind readnone {
@@ -468,7 +468,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK:      v4f32_cmp_ne:
+; CHECK-LABEL:      v4f32_cmp_ne:
 ; CHECK:      vcmpeqfp [[RET:[0-9]+]], 2, 3
 ; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
 
@@ -479,7 +479,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK:      v4f32_cmp_le:
+; CHECK-LABEL:      v4f32_cmp_le:
 ; CHECK:      vcmpeqfp [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtfp [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -491,7 +491,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK: v4f32_cmp_lt:
+; CHECK-LABEL: v4f32_cmp_lt:
 ; CHECK: vcmpgtfp 2, 3, 2
 
 define <4 x float> @v4f32_cmp_ge(<4 x float> %x, <4 x float> %y) nounwind readnone {
@@ -501,7 +501,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK: v4f32_cmp_ge:
+; CHECK-LABEL: v4f32_cmp_ge:
 ; CHECK: vcmpgefp 2, 2, 3
 
 define <4 x float> @v4f32_cmp_gt(<4 x float> %x, <4 x float> %y) nounwind readnone {
@@ -511,7 +511,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK: v4f32_cmp_gt:
+; CHECK-LABEL: v4f32_cmp_gt:
 ; CHECK: vcmpgtfp 2, 2, 3
 
 
@@ -522,6 +522,6 @@ entry:
   %0 = bitcast <8 x i32> %sext to <8 x float>
   ret <8 x float> %0
 }
-; CHECK: v8f32_cmp:
+; CHECK-LABEL: v8f32_cmp:
 ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll
index e4799e5..f16b9f5 100644
--- a/test/CodeGen/PowerPC/vec_constants.ll
+++ b/test/CodeGen/PowerPC/vec_constants.ll
@@ -17,14 +17,14 @@ define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind {
 	store <4 x float> %tmp13, <4 x float>* %P3
 	ret void
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: CPI
 }
 
 define <4 x i32> @test_30() nounwind {
 	ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >
 
-; CHECK: test_30:
+; CHECK-LABEL: test_30:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vadduwm
 ; CHECK-NEXT: blr
@@ -33,7 +33,7 @@ define <4 x i32> @test_30() nounwind {
 define <4 x i32> @test_29() nounwind {
 	ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >
 
-; CHECK: test_29:
+; CHECK-LABEL: test_29:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vspltisw
 ; CHECK-NEXT: vsubuwm
@@ -43,7 +43,7 @@ define <4 x i32> @test_29() nounwind {
 define <8 x i16> @test_n30() nounwind {
 	ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >
 
-; CHECK: test_n30:
+; CHECK-LABEL: test_n30:
 ; CHECK: vspltish
 ; CHECK-NEXT: vadduhm
 ; CHECK-NEXT: blr
@@ -52,7 +52,7 @@ define <8 x i16> @test_n30() nounwind {
 define <16 x i8> @test_n104() nounwind {
 	ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >
 
-; CHECK: test_n104:
+; CHECK-LABEL: test_n104:
 ; CHECK: vspltisb
 ; CHECK-NEXT: vslb
 ; CHECK-NEXT: blr
@@ -61,7 +61,7 @@ define <16 x i8> @test_n104() nounwind {
 define <4 x i32> @test_vsldoi() nounwind {
 	ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >
 
-; CHECK: test_vsldoi:
+; CHECK-LABEL: test_vsldoi:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vsldoi
 ; CHECK-NEXT: blr
@@ -70,7 +70,7 @@ define <4 x i32> @test_vsldoi() nounwind {
 define <8 x i16> @test_vsldoi_65023() nounwind {
 	ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 >
 
-; CHECK: test_vsldoi_65023:
+; CHECK-LABEL: test_vsldoi_65023:
 ; CHECK: vspltish
 ; CHECK-NEXT: vsldoi
 ; CHECK-NEXT: blr
@@ -79,7 +79,7 @@ define <8 x i16> @test_vsldoi_65023() nounwind {
 define <4 x i32> @test_rol() nounwind {
 	ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
 
-; CHECK: test_rol:
+; CHECK-LABEL: test_rol:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vrlw
 ; CHECK-NEXT: blr
diff --git a/test/CodeGen/PowerPC/vec_conv.ll b/test/CodeGen/PowerPC/vec_conv.ll
index a475e94..a39ae91 100644
--- a/test/CodeGen/PowerPC/vec_conv.ll
+++ b/test/CodeGen/PowerPC/vec_conv.ll
@@ -17,7 +17,7 @@ entry:
   store <4 x i32> %1, <4 x i32>* %y, align 16
   ret void
 }
-;CHECK: v4f32_to_v4i32:
+;CHECK-LABEL: v4f32_to_v4i32:
 ;CHECK: vctsxs {{[0-9]+}}, {{[0-9]+}}, 0
 
 
@@ -29,7 +29,7 @@ entry:
   store <4 x i32> %1, <4 x i32>* %y, align 16
   ret void
 }
-;CHECK: v4f32_to_v4u32:
+;CHECK-LABEL: v4f32_to_v4u32:
 ;CHECK: vctuxs {{[0-9]+}}, {{[0-9]+}}, 0
 
 
@@ -41,7 +41,7 @@ entry:
   store <4 x float> %1, <4 x float>* %y, align 16
   ret void
 }
-;CHECK: v4i32_to_v4f32:
+;CHECK-LABEL: v4i32_to_v4f32:
 ;CHECK: vcfsx {{[0-9]+}}, {{[0-9]+}}, 0
 
 
@@ -53,5 +53,5 @@ entry:
   store <4 x float> %1, <4 x float>* %y, align 16
   ret void
 }
-;CHECK: v4u32_to_v4f32:
+;CHECK-LABEL: v4u32_to_v4f32:
 ;CHECK: vcfux {{[0-9]+}}, {{[0-9]+}}, 0
diff --git a/test/CodeGen/PowerPC/vec_extload.ll b/test/CodeGen/PowerPC/vec_extload.ll
index 998645d..6373a26 100644
--- a/test/CodeGen/PowerPC/vec_extload.ll
+++ b/test/CodeGen/PowerPC/vec_extload.ll
@@ -14,7 +14,7 @@ define <16 x i8> @v16si8_sext_in_reg(<16 x i8> %a) {
   %c = sext <16 x i4> %b to <16 x i8>
   ret <16 x i8> %c
 }
-; CHECK: v16si8_sext_in_reg:
+; CHECK-LABEL: v16si8_sext_in_reg:
 ; CHECK: vslb
 ; CHECK: vsrab
 ; CHECK: blr 
@@ -26,7 +26,7 @@ define <16 x i8> @v16si8_zext_in_reg(<16 x i8> %a) {
   %c = zext <16 x i4> %b to <16 x i8>
   ret <16 x i8> %c
 }
-; CHECK:      v16si8_zext_in_reg:
+; CHECK-LABEL:      v16si8_zext_in_reg:
 ; CHECK:      vspltisb [[VMASK:[0-9]+]], 15
 ; CHECK-NEXT: vand 2, 2, [[VMASK]]
 
@@ -36,7 +36,7 @@ define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) {
   %c = sext <8 x i8> %b to <8 x i16>
   ret <8 x i16> %c
 }
-; CHECK: v8si16_sext_in_reg:
+; CHECK-LABEL: v8si16_sext_in_reg:
 ; CHECK: vslh
 ; CHECK: vsrah
 ; CHECK: blr 
@@ -48,7 +48,7 @@ define <8 x i16> @v8si16_zext_in_reg(<8 x i16> %a) {
   %c = zext <8 x i8> %b to <8 x i16>
   ret <8 x i16> %c
 }
-; CHECK:      v8si16_zext_in_reg:
+; CHECK-LABEL:      v8si16_zext_in_reg:
 ; CHECK:      ld [[RMASKTOC:[0-9]+]], .LC{{[0-9]+}}@toc(2)
 ; CHECK-NEXT: lvx [[VMASK:[0-9]+]], {{[0-9]+}}, [[RMASKTOC]]
 ; CHECK-NEXT: vand 2, 2, [[VMASK]]
@@ -60,7 +60,7 @@ define <4 x i32> @v4si32_sext_in_reg(<4 x i32> %a) {
   %c = sext <4 x i16> %b to <4 x i32>
   ret <4 x i32> %c
 }
-; CHECK: v4si32_sext_in_reg:
+; CHECK-LABEL: v4si32_sext_in_reg:
 ; CHECK: vslw
 ; CHECK: vsraw
 ; CHECK: blr 
@@ -71,7 +71,7 @@ define <4 x i32> @v4si32_zext_in_reg(<4 x i32> %a) {
   %c = zext <4 x i16> %b to <4 x i32>
   ret <4 x i32> %c
 }
-; CHECK:      v4si32_zext_in_reg:
+; CHECK-LABEL:      v4si32_zext_in_reg:
 ; CHECK:      vspltisw [[VMASK:[0-9]+]], -16
 ; CHECK-NEXT: vsrw [[VMASK]], [[VMASK]], [[VMASK]]
 ; CHECK-NEXT: vand 2, 2, [[VMASK]]
diff --git a/test/CodeGen/PowerPC/vec_fmuladd.ll b/test/CodeGen/PowerPC/vec_fmuladd.ll
new file mode 100644
index 0000000..5683b60
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_fmuladd.ll
@@ -0,0 +1,56 @@
+; RUN: llc -mcpu=pwr6 -mattr=+altivec < %s | FileCheck %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+declare <2 x float> @llvm.fmuladd.v2f32(<2 x float> %val, <2 x float>, <2 x float>)
+declare <4 x float> @llvm.fmuladd.v4f32(<4 x float> %val, <4 x float>, <4 x float>)
+declare <8 x float> @llvm.fmuladd.v8f32(<8 x float> %val, <8 x float>, <8 x float>)
+declare <2 x double> @llvm.fmuladd.v2f64(<2 x double> %val, <2 x double>, <2 x double>)
+declare <4 x double> @llvm.fmuladd.v4f64(<4 x double> %val, <4 x double>, <4 x double>)
+
+define <2 x float> @v2f32_fmuladd(<2 x float> %x) nounwind readnone {
+entry:
+  %fmuladd = call <2 x float> @llvm.fmuladd.v2f32 (<2 x float> %x, <2 x float> %x, <2 x float> %x)
+  ret <2 x float> %fmuladd
+}
+; fmuladd (<2 x float>) is promoted to fmuladd (<4 x float>)
+; CHECK-LABEL: v2f32_fmuladd:
+; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+define <4 x float> @v4f32_fmuladd(<4 x float> %x) nounwind readnone {
+entry:
+  %fmuladd = call <4 x float> @llvm.fmuladd.v4f32 (<4 x float> %x, <4 x float> %x, <4 x float> %x)
+  ret <4 x float> %fmuladd
+}
+; CHECK-LABEL: v4f32_fmuladd:
+; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+define <8 x float> @v8f32_fmuladd(<8 x float> %x) nounwind readnone {
+entry:
+  %fmuladd = call <8 x float> @llvm.fmuladd.v8f32 (<8 x float> %x, <8 x float> %x, <8 x float> %x)
+  ret <8 x float> %fmuladd
+}
+; CHECK-LABEL: v8f32_fmuladd:
+; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vmaddfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+define <2 x double> @v2f64_fmuladd(<2 x double> %x) nounwind readnone {
+entry:
+  %fmuladd = call <2 x double> @llvm.fmuladd.v2f64 (<2 x double> %x, <2 x double> %x, <2 x double> %x)
+  ret <2 x double> %fmuladd
+}
+; CHECK-LABEL: v2f64_fmuladd:
+; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+
+define <4 x double> @v4f64_fmuladd(<4 x double> %x) nounwind readnone {
+entry:
+  %fmuladd = call <4 x double> @llvm.fmuladd.v4f64 (<4 x double> %x, <4 x double> %x, <4 x double> %x)
+  ret <4 x double> %fmuladd
+}
+; CHECK-LABEL: v4f64_fmuladd:
+; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} 
+; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} 
+; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} 
+; CHECK: fmadd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} 
diff --git a/test/CodeGen/PowerPC/vec_mul.ll b/test/CodeGen/PowerPC/vec_mul.ll
index 53bc75d..c376751 100644
--- a/test/CodeGen/PowerPC/vec_mul.ll
+++ b/test/CodeGen/PowerPC/vec_mul.ll
@@ -6,7 +6,7 @@ define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
 	%tmp3 = mul <4 x i32> %tmp, %tmp2		; <<4 x i32>> [#uses=1]
 	ret <4 x i32> %tmp3
 }
-; CHECK: test_v4i32:
+; CHECK-LABEL: test_v4i32:
 ; CHECK: vmsumuhm
 ; CHECK-NOT: mullw
 
@@ -16,7 +16,7 @@ define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) {
 	%tmp3 = mul <8 x i16> %tmp, %tmp2		; <<8 x i16>> [#uses=1]
 	ret <8 x i16> %tmp3
 }
-; CHECK: test_v8i16:
+; CHECK-LABEL: test_v8i16:
 ; CHECK: vmladduhm
 ; CHECK-NOT: mullw
 
@@ -26,7 +26,7 @@ define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) {
 	%tmp3 = mul <16 x i8> %tmp, %tmp2		; <<16 x i8>> [#uses=1]
 	ret <16 x i8> %tmp3
 }
-; CHECK: test_v16i8:
+; CHECK-LABEL: test_v16i8:
 ; CHECK: vmuloub
 ; CHECK: vmuleub
 ; CHECK-NOT: mullw
@@ -40,7 +40,7 @@ define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) {
 ; Check the creation of a negative zero float vector by creating a vector of
 ; all bits set and shifting it 31 bits to left, resulting a an vector of 
 ; 4 x 0x80000000 (-0.0 as float).
-; CHECK: test_float:
+; CHECK-LABEL: test_float:
 ; CHECK: vspltisw [[ZNEG:[0-9]+]], -1
 ; CHECK: vslw     {{[0-9]+}}, [[ZNEG]], [[ZNEG]]
 ; CHECK: vmaddfp
diff --git a/test/CodeGen/PowerPC/vec_rounding.ll b/test/CodeGen/PowerPC/vec_rounding.ll
index 7c55638..ace187b 100644
--- a/test/CodeGen/PowerPC/vec_rounding.ll
+++ b/test/CodeGen/PowerPC/vec_rounding.ll
@@ -12,7 +12,7 @@ define <2 x double> @floor_v2f64(<2 x double> %p)
   %t = call <2 x double> @llvm.floor.v2f64(<2 x double> %p)
   ret <2 x double> %t
 }
-; CHECK: floor_v2f64:
+; CHECK-LABEL: floor_v2f64:
 ; CHECK: frim
 ; CHECK: frim
 
@@ -22,7 +22,7 @@ define <4 x double> @floor_v4f64(<4 x double> %p)
   %t = call <4 x double> @llvm.floor.v4f64(<4 x double> %p)
   ret <4 x double> %t
 }
-; CHECK: floor_v4f64:
+; CHECK-LABEL: floor_v4f64:
 ; CHECK: frim
 ; CHECK: frim
 ; CHECK: frim
@@ -34,7 +34,7 @@ define <2 x double> @ceil_v2f64(<2 x double> %p)
   %t = call <2 x double> @llvm.ceil.v2f64(<2 x double> %p)
   ret <2 x double> %t
 }
-; CHECK: ceil_v2f64:
+; CHECK-LABEL: ceil_v2f64:
 ; CHECK: frip
 ; CHECK: frip
 
@@ -44,7 +44,7 @@ define <4 x double> @ceil_v4f64(<4 x double> %p)
   %t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
   ret <4 x double> %t
 }
-; CHECK: ceil_v4f64:
+; CHECK-LABEL: ceil_v4f64:
 ; CHECK: frip
 ; CHECK: frip
 ; CHECK: frip
@@ -56,7 +56,7 @@ define <2 x double> @trunc_v2f64(<2 x double> %p)
   %t = call <2 x double> @llvm.trunc.v2f64(<2 x double> %p)
   ret <2 x double> %t
 }
-; CHECK: trunc_v2f64:
+; CHECK-LABEL: trunc_v2f64:
 ; CHECK: friz
 ; CHECK: friz
 
@@ -66,7 +66,7 @@ define <4 x double> @trunc_v4f64(<4 x double> %p)
   %t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
   ret <4 x double> %t
 }
-; CHECK: trunc_v4f64:
+; CHECK-LABEL: trunc_v4f64:
 ; CHECK: friz
 ; CHECK: friz
 ; CHECK: friz
@@ -78,7 +78,7 @@ define <2 x double> @nearbyint_v2f64(<2 x double> %p)
   %t = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p)
   ret <2 x double> %t
 }
-; CHECK: nearbyint_v2f64:
+; CHECK-LABEL: nearbyint_v2f64:
 ; CHECK: bl nearbyint
 ; CHECK: bl nearbyint
 
@@ -88,7 +88,7 @@ define <4 x double> @nearbyint_v4f64(<4 x double> %p)
   %t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
   ret <4 x double> %t
 }
-; CHECK: nearbyint_v4f64:
+; CHECK-LABEL: nearbyint_v4f64:
 ; CHECK: bl nearbyint
 ; CHECK: bl nearbyint
 ; CHECK: bl nearbyint
@@ -101,7 +101,7 @@ define <4 x float> @floor_v4f32(<4 x float> %p)
   %t = call <4 x float> @llvm.floor.v4f32(<4 x float> %p)
   ret <4 x float> %t
 }
-; CHECK: floor_v4f32:
+; CHECK-LABEL: floor_v4f32:
 ; CHECK: vrfim
 
 declare <8 x float> @llvm.floor.v8f32(<8 x float> %p)
@@ -110,7 +110,7 @@ define <8 x float> @floor_v8f32(<8 x float> %p)
   %t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p)
   ret <8 x float> %t
 }
-; CHECK: floor_v8f32:
+; CHECK-LABEL: floor_v8f32:
 ; CHECK: vrfim
 ; CHECK: vrfim
 
@@ -120,7 +120,7 @@ define <4 x float> @ceil_v4f32(<4 x float> %p)
   %t = call <4 x float> @llvm.ceil.v4f32(<4 x float> %p)
   ret <4 x float> %t
 }
-; CHECK: ceil_v4f32:
+; CHECK-LABEL: ceil_v4f32:
 ; CHECK: vrfip
 
 declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
@@ -129,7 +129,7 @@ define <8 x float> @ceil_v8f32(<8 x float> %p)
   %t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
   ret <8 x float> %t
 }
-; CHECK: ceil_v8f32:
+; CHECK-LABEL: ceil_v8f32:
 ; CHECK: vrfip
 ; CHECK: vrfip
 
@@ -139,7 +139,7 @@ define <4 x float> @trunc_v4f32(<4 x float> %p)
   %t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %p)
   ret <4 x float> %t
 }
-; CHECK: trunc_v4f32:
+; CHECK-LABEL: trunc_v4f32:
 ; CHECK: vrfiz
 
 declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
@@ -148,7 +148,7 @@ define <8 x float> @trunc_v8f32(<8 x float> %p)
   %t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
   ret <8 x float> %t
 }
-; CHECK: trunc_v8f32:
+; CHECK-LABEL: trunc_v8f32:
 ; CHECK: vrfiz
 ; CHECK: vrfiz
 
@@ -158,7 +158,7 @@ define <4 x float> @nearbyint_v4f32(<4 x float> %p)
   %t = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p)
   ret <4 x float> %t
 }
-; CHECK: nearbyint_v4f32:
+; CHECK-LABEL: nearbyint_v4f32:
 ; CHECK: vrfin
 
 declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
@@ -167,6 +167,6 @@ define <8 x float> @nearbyint_v8f32(<8 x float> %p)
   %t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
   ret <8 x float> %t
 }
-; CHECK: nearbyint_v8f32:
+; CHECK-LABEL: nearbyint_v8f32:
 ; CHECK: vrfin
 ; CHECK: vrfin
diff --git a/test/CodeGen/PowerPC/vec_sqrt.ll b/test/CodeGen/PowerPC/vec_sqrt.ll
index 055da1a..a85c3ff 100644
--- a/test/CodeGen/PowerPC/vec_sqrt.ll
+++ b/test/CodeGen/PowerPC/vec_sqrt.ll
@@ -18,7 +18,7 @@ entry:
   ret <2 x float> %sqrt
 }
 ; sqrt (<2 x float>) is promoted to sqrt (<4 x float>)
-; CHECK: v2f32_sqrt:
+; CHECK-LABEL: v2f32_sqrt:
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
@@ -29,7 +29,7 @@ entry:
   %sqrt = call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %x)
   ret <4 x float> %sqrt
 }
-; CHECK: v4f32_sqrt:
+; CHECK-LABEL: v4f32_sqrt:
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
@@ -40,7 +40,7 @@ entry:
   %sqrt = call <8 x float> @llvm.sqrt.v8f32 (<8 x float> %x)
   ret <8 x float> %sqrt
 }
-; CHECK: v8f32_sqrt:
+; CHECK-LABEL: v8f32_sqrt:
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
@@ -55,7 +55,7 @@ entry:
   %sqrt = call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %x)
   ret <2 x double> %sqrt
 }
-; CHECK: v2f64_sqrt:
+; CHECK-LABEL: v2f64_sqrt:
 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
 
@@ -64,7 +64,7 @@ entry:
   %sqrt = call <4 x double> @llvm.sqrt.v4f64 (<4 x double> %x)
   ret <4 x double> %sqrt
 }
-; CHECK: v4f64_sqrt:
+; CHECK-LABEL: v4f64_sqrt:
 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
diff --git a/test/CodeGen/PowerPC/vector.ll b/test/CodeGen/PowerPC/vector.ll
index e4c3b0d..859a85a 100644
--- a/test/CodeGen/PowerPC/vector.ll
+++ b/test/CodeGen/PowerPC/vector.ll
@@ -59,6 +59,14 @@ define void @test_div(%f8* %P, %f8* %Q, %f8* %S) {
         ret void
 }
 
+define void @test_rem(%f8* %P, %f8* %Q, %f8* %S) {
+        %p = load %f8* %P               ; <%f8> [#uses=1]
+        %q = load %f8* %Q               ; <%f8> [#uses=1]
+        %R = frem %f8 %p, %q            ; <%f8> [#uses=1]
+        store %f8 %R, %f8* %S
+        ret void
+}
+
 ;;; TEST VECTOR CONSTRUCTS
 
 define void @test_cst(%f4* %P, %f4* %S) {
diff --git a/test/CodeGen/PowerPC/vrspill.ll b/test/CodeGen/PowerPC/vrspill.ll
index 9fb3d03..c3d1bf8 100644
--- a/test/CodeGen/PowerPC/vrspill.ll
+++ b/test/CodeGen/PowerPC/vrspill.ll
@@ -1,5 +1,5 @@
-; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs  < %s | FileCheck %s
-; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs -fast-isel=false < %s | FileCheck %s
 
 ; This verifies that we generate correct spill/reload code for vector regs.
 
@@ -13,7 +13,6 @@ entry:
   ret void
 }
 
-; CHECK: stvx 2, 1,
-; CHECK: lvx 2, 1,
+; CHECK: stvx 2,
 
 declare void @foo(i32*)
diff --git a/test/CodeGen/PowerPC/zero-not-run.ll b/test/CodeGen/PowerPC/zero-not-run.ll
new file mode 100644
index 0000000..04c4277
--- /dev/null
+++ b/test/CodeGen/PowerPC/zero-not-run.ll
@@ -0,0 +1,27 @@
+; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+define internal i32* @func_65(i32* %p_66) #0 {
+entry:
+  br i1 undef, label %for.body, label %for.end731
+
+for.body:                                         ; preds = %entry
+  %0 = load i32* undef, align 4
+  %or31 = or i32 %0, 319143828
+  store i32 %or31, i32* undef, align 4
+  %cmp32 = icmp eq i32 319143828, %or31
+  %conv33 = zext i1 %cmp32 to i32
+  %conv34 = sext i32 %conv33 to i64
+  %call35 = call i64 @safe_mod_func_uint64_t_u_u(i64 %conv34, i64 -10)
+  unreachable
+
+for.end731:                                       ; preds = %entry
+  ret i32* undef
+}
+
+; Function Attrs: nounwind
+declare i64 @safe_mod_func_uint64_t_u_u(i64, i64) #0
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/CodeGen/R600/128bit-kernel-args.ll b/test/CodeGen/R600/128bit-kernel-args.ll
index 114f9e7..5c14270 100644
--- a/test/CodeGen/R600/128bit-kernel-args.ll
+++ b/test/CodeGen/R600/128bit-kernel-args.ll
@@ -1,16 +1,26 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-; CHECK: @v4i32_kernel_arg
-; CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 40
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
 
+; R600-CHECK: @v4i32_kernel_arg
+; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y
+; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].Y, KC0[3].Z
+; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W
+; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].W, KC0[4].X
+; SI-CHECK: @v4i32_kernel_arg
+; SI-CHECK: BUFFER_STORE_DWORDX4
 define void @v4i32_kernel_arg(<4 x i32> addrspace(1)* %out, <4 x i32>  %in) {
 entry:
   store <4 x i32> %in, <4 x i32> addrspace(1)* %out
   ret void
 }
 
-; CHECK: @v4f32_kernel_arg
-; CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 40
+; R600-CHECK: @v4f32_kernel_arg
+; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR:[0-9]]].X, KC0[3].Y
+; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].Y, KC0[3].Z
+; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].Z, KC0[3].W
+; R600-CHECK-DAG: MOV {{[* ]*}}T[[GPR]].W, KC0[4].X
+; SI-CHECK: @v4f32_kernel_arg
+; SI-CHECK: BUFFER_STORE_DWORDX4
 define void @v4f32_kernel_args(<4 x float> addrspace(1)* %out, <4 x float>  %in) {
 entry:
   store <4 x float> %in, <4 x float> addrspace(1)* %out
diff --git a/test/CodeGen/R600/64bit-kernel-args.ll b/test/CodeGen/R600/64bit-kernel-args.ll
new file mode 100644
index 0000000..34a0a87
--- /dev/null
+++ b/test/CodeGen/R600/64bit-kernel-args.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s --check-prefix=SI-CHECK
+
+; SI-CHECK: @f64_kernel_arg
+; SI-CHECK-DAG: S_LOAD_DWORDX2 SGPR{{[0-9]}}_SGPR{{[0-9]}}, SGPR0_SGPR1, 9
+; SI-CHECK-DAG: S_LOAD_DWORDX2 SGPR{{[0-9]}}_SGPR{{[0-9]}}, SGPR0_SGPR1, 11
+; SI-CHECK: BUFFER_STORE_DWORDX2
+define void @f64_kernel_arg(double addrspace(1)* %out, double  %in) {
+entry:
+  store double %in, double addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/add.ll b/test/CodeGen/R600/add.ll
index 185998b..16f7f97 100644
--- a/test/CodeGen/R600/add.ll
+++ b/test/CodeGen/R600/add.ll
@@ -1,11 +1,36 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
 
-;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: @test2
+;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+;SI-CHECK: @test2
+;SI-CHECK: V_ADD_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ADD_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %result = add <2 x i32> %a, %b
+  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+;EG-CHECK: @test4
+;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @test4
+;SI-CHECK: V_ADD_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ADD_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ADD_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ADD_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
   %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
   %a = load <4 x i32> addrspace(1) * %in
   %b = load <4 x i32> addrspace(1) * %b_ptr
diff --git a/test/CodeGen/R600/alu-split.ll b/test/CodeGen/R600/alu-split.ll
deleted file mode 100644
index 48496f6..0000000
--- a/test/CodeGen/R600/alu-split.ll
+++ /dev/null
@@ -1,851 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-
-;CHECK: ALU
-;CHECK: ALU
-;CHECK: ALU
-;CHECK-NOT: ALU
-;CHECK: CF_END
-
-define void @main() #0 {
-main_body:
-  %0 = call float @llvm.R600.load.input(i32 4)
-  %1 = call float @llvm.R600.load.input(i32 5)
-  %2 = call float @llvm.R600.load.input(i32 6)
-  %3 = call float @llvm.R600.load.input(i32 7)
-  %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16)
-  %5 = extractelement <4 x float> %4, i32 0
-  %6 = fcmp une float 0x4016F2B020000000, %5
-  %7 = select i1 %6, float 1.000000e+00, float 0.000000e+00
-  %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16)
-  %9 = extractelement <4 x float> %8, i32 1
-  %10 = fcmp une float 0x401FDCC640000000, %9
-  %11 = select i1 %10, float 1.000000e+00, float 0.000000e+00
-  %12 = fsub float -0.000000e+00, %7
-  %13 = fptosi float %12 to i32
-  %14 = fsub float -0.000000e+00, %11
-  %15 = fptosi float %14 to i32
-  %16 = bitcast i32 %13 to float
-  %17 = bitcast i32 %15 to float
-  %18 = bitcast float %16 to i32
-  %19 = bitcast float %17 to i32
-  %20 = or i32 %18, %19
-  %21 = bitcast i32 %20 to float
-  %22 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17)
-  %23 = extractelement <4 x float> %22, i32 0
-  %24 = fcmp une float 0xC00574BC60000000, %23
-  %25 = select i1 %24, float 1.000000e+00, float 0.000000e+00
-  %26 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 17)
-  %27 = extractelement <4 x float> %26, i32 1
-  %28 = fcmp une float 0x40210068E0000000, %27
-  %29 = select i1 %28, float 1.000000e+00, float 0.000000e+00
-  %30 = fsub float -0.000000e+00, %25
-  %31 = fptosi float %30 to i32
-  %32 = fsub float -0.000000e+00, %29
-  %33 = fptosi float %32 to i32
-  %34 = bitcast i32 %31 to float
-  %35 = bitcast i32 %33 to float
-  %36 = bitcast float %34 to i32
-  %37 = bitcast float %35 to i32
-  %38 = or i32 %36, %37
-  %39 = bitcast i32 %38 to float
-  %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18)
-  %41 = extractelement <4 x float> %40, i32 0
-  %42 = fcmp une float 0xBFC9A6B500000000, %41
-  %43 = select i1 %42, float 1.000000e+00, float 0.000000e+00
-  %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 18)
-  %45 = extractelement <4 x float> %44, i32 1
-  %46 = fcmp une float 0xC0119BDA60000000, %45
-  %47 = select i1 %46, float 1.000000e+00, float 0.000000e+00
-  %48 = fsub float -0.000000e+00, %43
-  %49 = fptosi float %48 to i32
-  %50 = fsub float -0.000000e+00, %47
-  %51 = fptosi float %50 to i32
-  %52 = bitcast i32 %49 to float
-  %53 = bitcast i32 %51 to float
-  %54 = bitcast float %52 to i32
-  %55 = bitcast float %53 to i32
-  %56 = or i32 %54, %55
-  %57 = bitcast i32 %56 to float
-  %58 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19)
-  %59 = extractelement <4 x float> %58, i32 0
-  %60 = fcmp une float 0xC02085D640000000, %59
-  %61 = select i1 %60, float 1.000000e+00, float 0.000000e+00
-  %62 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 19)
-  %63 = extractelement <4 x float> %62, i32 1
-  %64 = fcmp une float 0xBFD7C1BDA0000000, %63
-  %65 = select i1 %64, float 1.000000e+00, float 0.000000e+00
-  %66 = fsub float -0.000000e+00, %61
-  %67 = fptosi float %66 to i32
-  %68 = fsub float -0.000000e+00, %65
-  %69 = fptosi float %68 to i32
-  %70 = bitcast i32 %67 to float
-  %71 = bitcast i32 %69 to float
-  %72 = bitcast float %70 to i32
-  %73 = bitcast float %71 to i32
-  %74 = or i32 %72, %73
-  %75 = bitcast i32 %74 to float
-  %76 = insertelement <4 x float> undef, float %21, i32 0
-  %77 = insertelement <4 x float> %76, float %39, i32 1
-  %78 = insertelement <4 x float> %77, float %57, i32 2
-  %79 = insertelement <4 x float> %78, float %75, i32 3
-  %80 = insertelement <4 x float> undef, float %21, i32 0
-  %81 = insertelement <4 x float> %80, float %39, i32 1
-  %82 = insertelement <4 x float> %81, float %57, i32 2
-  %83 = insertelement <4 x float> %82, float %75, i32 3
-  %84 = call float @llvm.AMDGPU.dp4(<4 x float> %79, <4 x float> %83)
-  %85 = bitcast float %84 to i32
-  %86 = icmp ne i32 %85, 0
-  %87 = sext i1 %86 to i32
-  %88 = bitcast i32 %87 to float
-  %89 = bitcast float %88 to i32
-  %90 = xor i32 %89, -1
-  %91 = bitcast i32 %90 to float
-  %92 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20)
-  %93 = extractelement <4 x float> %92, i32 0
-  %94 = fcmp une float 0x401FDCC640000000, %93
-  %95 = select i1 %94, float 1.000000e+00, float 0.000000e+00
-  %96 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 20)
-  %97 = extractelement <4 x float> %96, i32 1
-  %98 = fcmp une float 0xC00574BC60000000, %97
-  %99 = select i1 %98, float 1.000000e+00, float 0.000000e+00
-  %100 = fsub float -0.000000e+00, %95
-  %101 = fptosi float %100 to i32
-  %102 = fsub float -0.000000e+00, %99
-  %103 = fptosi float %102 to i32
-  %104 = bitcast i32 %101 to float
-  %105 = bitcast i32 %103 to float
-  %106 = bitcast float %104 to i32
-  %107 = bitcast float %105 to i32
-  %108 = or i32 %106, %107
-  %109 = bitcast i32 %108 to float
-  %110 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21)
-  %111 = extractelement <4 x float> %110, i32 0
-  %112 = fcmp une float 0x40210068E0000000, %111
-  %113 = select i1 %112, float 1.000000e+00, float 0.000000e+00
-  %114 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 21)
-  %115 = extractelement <4 x float> %114, i32 1
-  %116 = fcmp une float 0xBFC9A6B500000000, %115
-  %117 = select i1 %116, float 1.000000e+00, float 0.000000e+00
-  %118 = fsub float -0.000000e+00, %113
-  %119 = fptosi float %118 to i32
-  %120 = fsub float -0.000000e+00, %117
-  %121 = fptosi float %120 to i32
-  %122 = bitcast i32 %119 to float
-  %123 = bitcast i32 %121 to float
-  %124 = bitcast float %122 to i32
-  %125 = bitcast float %123 to i32
-  %126 = or i32 %124, %125
-  %127 = bitcast i32 %126 to float
-  %128 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22)
-  %129 = extractelement <4 x float> %128, i32 0
-  %130 = fcmp une float 0xC0119BDA60000000, %129
-  %131 = select i1 %130, float 1.000000e+00, float 0.000000e+00
-  %132 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 22)
-  %133 = extractelement <4 x float> %132, i32 1
-  %134 = fcmp une float 0xC02085D640000000, %133
-  %135 = select i1 %134, float 1.000000e+00, float 0.000000e+00
-  %136 = fsub float -0.000000e+00, %131
-  %137 = fptosi float %136 to i32
-  %138 = fsub float -0.000000e+00, %135
-  %139 = fptosi float %138 to i32
-  %140 = bitcast i32 %137 to float
-  %141 = bitcast i32 %139 to float
-  %142 = bitcast float %140 to i32
-  %143 = bitcast float %141 to i32
-  %144 = or i32 %142, %143
-  %145 = bitcast i32 %144 to float
-  %146 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23)
-  %147 = extractelement <4 x float> %146, i32 0
-  %148 = fcmp une float 0xBFD7C1BDA0000000, %147
-  %149 = select i1 %148, float 1.000000e+00, float 0.000000e+00
-  %150 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23)
-  %151 = extractelement <4 x float> %150, i32 1
-  %152 = fcmp une float 0x401E1D7DC0000000, %151
-  %153 = select i1 %152, float 1.000000e+00, float 0.000000e+00
-  %154 = fsub float -0.000000e+00, %149
-  %155 = fptosi float %154 to i32
-  %156 = fsub float -0.000000e+00, %153
-  %157 = fptosi float %156 to i32
-  %158 = bitcast i32 %155 to float
-  %159 = bitcast i32 %157 to float
-  %160 = bitcast float %158 to i32
-  %161 = bitcast float %159 to i32
-  %162 = or i32 %160, %161
-  %163 = bitcast i32 %162 to float
-  %164 = insertelement <4 x float> undef, float %109, i32 0
-  %165 = insertelement <4 x float> %164, float %127, i32 1
-  %166 = insertelement <4 x float> %165, float %145, i32 2
-  %167 = insertelement <4 x float> %166, float %163, i32 3
-  %168 = insertelement <4 x float> undef, float %109, i32 0
-  %169 = insertelement <4 x float> %168, float %127, i32 1
-  %170 = insertelement <4 x float> %169, float %145, i32 2
-  %171 = insertelement <4 x float> %170, float %163, i32 3
-  %172 = call float @llvm.AMDGPU.dp4(<4 x float> %167, <4 x float> %171)
-  %173 = bitcast float %172 to i32
-  %174 = icmp ne i32 %173, 0
-  %175 = sext i1 %174 to i32
-  %176 = bitcast i32 %175 to float
-  %177 = bitcast float %176 to i32
-  %178 = xor i32 %177, -1
-  %179 = bitcast i32 %178 to float
-  %180 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
-  %181 = extractelement <4 x float> %180, i32 0
-  %182 = fcmp une float 0x401FDCC640000000, %181
-  %183 = select i1 %182, float 1.000000e+00, float 0.000000e+00
-  %184 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
-  %185 = extractelement <4 x float> %184, i32 1
-  %186 = fcmp une float 0xC00574BC60000000, %185
-  %187 = select i1 %186, float 1.000000e+00, float 0.000000e+00
-  %188 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8)
-  %189 = extractelement <4 x float> %188, i32 2
-  %190 = fcmp une float 0x40210068E0000000, %189
-  %191 = select i1 %190, float 1.000000e+00, float 0.000000e+00
-  %192 = fsub float -0.000000e+00, %183
-  %193 = fptosi float %192 to i32
-  %194 = fsub float -0.000000e+00, %187
-  %195 = fptosi float %194 to i32
-  %196 = fsub float -0.000000e+00, %191
-  %197 = fptosi float %196 to i32
-  %198 = bitcast i32 %193 to float
-  %199 = bitcast i32 %195 to float
-  %200 = bitcast i32 %197 to float
-  %201 = bitcast float %199 to i32
-  %202 = bitcast float %200 to i32
-  %203 = or i32 %201, %202
-  %204 = bitcast i32 %203 to float
-  %205 = bitcast float %198 to i32
-  %206 = bitcast float %204 to i32
-  %207 = or i32 %205, %206
-  %208 = bitcast i32 %207 to float
-  %209 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
-  %210 = extractelement <4 x float> %209, i32 0
-  %211 = fcmp une float 0xBFC9A6B500000000, %210
-  %212 = select i1 %211, float 1.000000e+00, float 0.000000e+00
-  %213 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
-  %214 = extractelement <4 x float> %213, i32 1
-  %215 = fcmp une float 0xC0119BDA60000000, %214
-  %216 = select i1 %215, float 1.000000e+00, float 0.000000e+00
-  %217 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
-  %218 = extractelement <4 x float> %217, i32 2
-  %219 = fcmp une float 0xC02085D640000000, %218
-  %220 = select i1 %219, float 1.000000e+00, float 0.000000e+00
-  %221 = fsub float -0.000000e+00, %212
-  %222 = fptosi float %221 to i32
-  %223 = fsub float -0.000000e+00, %216
-  %224 = fptosi float %223 to i32
-  %225 = fsub float -0.000000e+00, %220
-  %226 = fptosi float %225 to i32
-  %227 = bitcast i32 %222 to float
-  %228 = bitcast i32 %224 to float
-  %229 = bitcast i32 %226 to float
-  %230 = bitcast float %228 to i32
-  %231 = bitcast float %229 to i32
-  %232 = or i32 %230, %231
-  %233 = bitcast i32 %232 to float
-  %234 = bitcast float %227 to i32
-  %235 = bitcast float %233 to i32
-  %236 = or i32 %234, %235
-  %237 = bitcast i32 %236 to float
-  %238 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
-  %239 = extractelement <4 x float> %238, i32 0
-  %240 = fcmp une float 0xBFD7C1BDA0000000, %239
-  %241 = select i1 %240, float 1.000000e+00, float 0.000000e+00
-  %242 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
-  %243 = extractelement <4 x float> %242, i32 1
-  %244 = fcmp une float 0x401E1D7DC0000000, %243
-  %245 = select i1 %244, float 1.000000e+00, float 0.000000e+00
-  %246 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10)
-  %247 = extractelement <4 x float> %246, i32 2
-  %248 = fcmp une float 0xC019893740000000, %247
-  %249 = select i1 %248, float 1.000000e+00, float 0.000000e+00
-  %250 = fsub float -0.000000e+00, %241
-  %251 = fptosi float %250 to i32
-  %252 = fsub float -0.000000e+00, %245
-  %253 = fptosi float %252 to i32
-  %254 = fsub float -0.000000e+00, %249
-  %255 = fptosi float %254 to i32
-  %256 = bitcast i32 %251 to float
-  %257 = bitcast i32 %253 to float
-  %258 = bitcast i32 %255 to float
-  %259 = bitcast float %257 to i32
-  %260 = bitcast float %258 to i32
-  %261 = or i32 %259, %260
-  %262 = bitcast i32 %261 to float
-  %263 = bitcast float %256 to i32
-  %264 = bitcast float %262 to i32
-  %265 = or i32 %263, %264
-  %266 = bitcast i32 %265 to float
-  %267 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
-  %268 = extractelement <4 x float> %267, i32 0
-  %269 = fcmp une float 0x40220F0D80000000, %268
-  %270 = select i1 %269, float 1.000000e+00, float 0.000000e+00
-  %271 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
-  %272 = extractelement <4 x float> %271, i32 1
-  %273 = fcmp une float 0xC018E2EB20000000, %272
-  %274 = select i1 %273, float 1.000000e+00, float 0.000000e+00
-  %275 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11)
-  %276 = extractelement <4 x float> %275, i32 2
-  %277 = fcmp une float 0xBFEA8DB8C0000000, %276
-  %278 = select i1 %277, float 1.000000e+00, float 0.000000e+00
-  %279 = fsub float -0.000000e+00, %270
-  %280 = fptosi float %279 to i32
-  %281 = fsub float -0.000000e+00, %274
-  %282 = fptosi float %281 to i32
-  %283 = fsub float -0.000000e+00, %278
-  %284 = fptosi float %283 to i32
-  %285 = bitcast i32 %280 to float
-  %286 = bitcast i32 %282 to float
-  %287 = bitcast i32 %284 to float
-  %288 = bitcast float %286 to i32
-  %289 = bitcast float %287 to i32
-  %290 = or i32 %288, %289
-  %291 = bitcast i32 %290 to float
-  %292 = bitcast float %285 to i32
-  %293 = bitcast float %291 to i32
-  %294 = or i32 %292, %293
-  %295 = bitcast i32 %294 to float
-  %296 = insertelement <4 x float> undef, float %208, i32 0
-  %297 = insertelement <4 x float> %296, float %237, i32 1
-  %298 = insertelement <4 x float> %297, float %266, i32 2
-  %299 = insertelement <4 x float> %298, float %295, i32 3
-  %300 = insertelement <4 x float> undef, float %208, i32 0
-  %301 = insertelement <4 x float> %300, float %237, i32 1
-  %302 = insertelement <4 x float> %301, float %266, i32 2
-  %303 = insertelement <4 x float> %302, float %295, i32 3
-  %304 = call float @llvm.AMDGPU.dp4(<4 x float> %299, <4 x float> %303)
-  %305 = bitcast float %304 to i32
-  %306 = icmp ne i32 %305, 0
-  %307 = sext i1 %306 to i32
-  %308 = bitcast i32 %307 to float
-  %309 = bitcast float %308 to i32
-  %310 = xor i32 %309, -1
-  %311 = bitcast i32 %310 to float
-  %312 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12)
-  %313 = extractelement <4 x float> %312, i32 0
-  %314 = fcmp une float 0xC00574BC60000000, %313
-  %315 = select i1 %314, float 1.000000e+00, float 0.000000e+00
-  %316 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12)
-  %317 = extractelement <4 x float> %316, i32 1
-  %318 = fcmp une float 0x40210068E0000000, %317
-  %319 = select i1 %318, float 1.000000e+00, float 0.000000e+00
-  %320 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12)
-  %321 = extractelement <4 x float> %320, i32 2
-  %322 = fcmp une float 0xBFC9A6B500000000, %321
-  %323 = select i1 %322, float 1.000000e+00, float 0.000000e+00
-  %324 = fsub float -0.000000e+00, %315
-  %325 = fptosi float %324 to i32
-  %326 = fsub float -0.000000e+00, %319
-  %327 = fptosi float %326 to i32
-  %328 = fsub float -0.000000e+00, %323
-  %329 = fptosi float %328 to i32
-  %330 = bitcast i32 %325 to float
-  %331 = bitcast i32 %327 to float
-  %332 = bitcast i32 %329 to float
-  %333 = bitcast float %331 to i32
-  %334 = bitcast float %332 to i32
-  %335 = or i32 %333, %334
-  %336 = bitcast i32 %335 to float
-  %337 = bitcast float %330 to i32
-  %338 = bitcast float %336 to i32
-  %339 = or i32 %337, %338
-  %340 = bitcast i32 %339 to float
-  %341 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13)
-  %342 = extractelement <4 x float> %341, i32 0
-  %343 = fcmp une float 0xC0119BDA60000000, %342
-  %344 = select i1 %343, float 1.000000e+00, float 0.000000e+00
-  %345 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13)
-  %346 = extractelement <4 x float> %345, i32 1
-  %347 = fcmp une float 0xC02085D640000000, %346
-  %348 = select i1 %347, float 1.000000e+00, float 0.000000e+00
-  %349 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 13)
-  %350 = extractelement <4 x float> %349, i32 2
-  %351 = fcmp une float 0xBFD7C1BDA0000000, %350
-  %352 = select i1 %351, float 1.000000e+00, float 0.000000e+00
-  %353 = fsub float -0.000000e+00, %344
-  %354 = fptosi float %353 to i32
-  %355 = fsub float -0.000000e+00, %348
-  %356 = fptosi float %355 to i32
-  %357 = fsub float -0.000000e+00, %352
-  %358 = fptosi float %357 to i32
-  %359 = bitcast i32 %354 to float
-  %360 = bitcast i32 %356 to float
-  %361 = bitcast i32 %358 to float
-  %362 = bitcast float %360 to i32
-  %363 = bitcast float %361 to i32
-  %364 = or i32 %362, %363
-  %365 = bitcast i32 %364 to float
-  %366 = bitcast float %359 to i32
-  %367 = bitcast float %365 to i32
-  %368 = or i32 %366, %367
-  %369 = bitcast i32 %368 to float
-  %370 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
-  %371 = extractelement <4 x float> %370, i32 0
-  %372 = fcmp une float 0x401E1D7DC0000000, %371
-  %373 = select i1 %372, float 1.000000e+00, float 0.000000e+00
-  %374 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
-  %375 = extractelement <4 x float> %374, i32 1
-  %376 = fcmp une float 0xC019893740000000, %375
-  %377 = select i1 %376, float 1.000000e+00, float 0.000000e+00
-  %378 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14)
-  %379 = extractelement <4 x float> %378, i32 2
-  %380 = fcmp une float 0x40220F0D80000000, %379
-  %381 = select i1 %380, float 1.000000e+00, float 0.000000e+00
-  %382 = fsub float -0.000000e+00, %373
-  %383 = fptosi float %382 to i32
-  %384 = fsub float -0.000000e+00, %377
-  %385 = fptosi float %384 to i32
-  %386 = fsub float -0.000000e+00, %381
-  %387 = fptosi float %386 to i32
-  %388 = bitcast i32 %383 to float
-  %389 = bitcast i32 %385 to float
-  %390 = bitcast i32 %387 to float
-  %391 = bitcast float %389 to i32
-  %392 = bitcast float %390 to i32
-  %393 = or i32 %391, %392
-  %394 = bitcast i32 %393 to float
-  %395 = bitcast float %388 to i32
-  %396 = bitcast float %394 to i32
-  %397 = or i32 %395, %396
-  %398 = bitcast i32 %397 to float
-  %399 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15)
-  %400 = extractelement <4 x float> %399, i32 0
-  %401 = fcmp une float 0xC018E2EB20000000, %400
-  %402 = select i1 %401, float 1.000000e+00, float 0.000000e+00
-  %403 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15)
-  %404 = extractelement <4 x float> %403, i32 1
-  %405 = fcmp une float 0xBFEA8DB8C0000000, %404
-  %406 = select i1 %405, float 1.000000e+00, float 0.000000e+00
-  %407 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15)
-  %408 = extractelement <4 x float> %407, i32 2
-  %409 = fcmp une float 0x4015236E20000000, %408
-  %410 = select i1 %409, float 1.000000e+00, float 0.000000e+00
-  %411 = fsub float -0.000000e+00, %402
-  %412 = fptosi float %411 to i32
-  %413 = fsub float -0.000000e+00, %406
-  %414 = fptosi float %413 to i32
-  %415 = fsub float -0.000000e+00, %410
-  %416 = fptosi float %415 to i32
-  %417 = bitcast i32 %412 to float
-  %418 = bitcast i32 %414 to float
-  %419 = bitcast i32 %416 to float
-  %420 = bitcast float %418 to i32
-  %421 = bitcast float %419 to i32
-  %422 = or i32 %420, %421
-  %423 = bitcast i32 %422 to float
-  %424 = bitcast float %417 to i32
-  %425 = bitcast float %423 to i32
-  %426 = or i32 %424, %425
-  %427 = bitcast i32 %426 to float
-  %428 = insertelement <4 x float> undef, float %340, i32 0
-  %429 = insertelement <4 x float> %428, float %369, i32 1
-  %430 = insertelement <4 x float> %429, float %398, i32 2
-  %431 = insertelement <4 x float> %430, float %427, i32 3
-  %432 = insertelement <4 x float> undef, float %340, i32 0
-  %433 = insertelement <4 x float> %432, float %369, i32 1
-  %434 = insertelement <4 x float> %433, float %398, i32 2
-  %435 = insertelement <4 x float> %434, float %427, i32 3
-  %436 = call float @llvm.AMDGPU.dp4(<4 x float> %431, <4 x float> %435)
-  %437 = bitcast float %436 to i32
-  %438 = icmp ne i32 %437, 0
-  %439 = sext i1 %438 to i32
-  %440 = bitcast i32 %439 to float
-  %441 = bitcast float %440 to i32
-  %442 = xor i32 %441, -1
-  %443 = bitcast i32 %442 to float
-  %444 = load <4 x float> addrspace(8)* null
-  %445 = extractelement <4 x float> %444, i32 0
-  %446 = fcmp une float 0xC00574BC60000000, %445
-  %447 = select i1 %446, float 1.000000e+00, float 0.000000e+00
-  %448 = load <4 x float> addrspace(8)* null
-  %449 = extractelement <4 x float> %448, i32 1
-  %450 = fcmp une float 0x40210068E0000000, %449
-  %451 = select i1 %450, float 1.000000e+00, float 0.000000e+00
-  %452 = load <4 x float> addrspace(8)* null
-  %453 = extractelement <4 x float> %452, i32 2
-  %454 = fcmp une float 0xBFC9A6B500000000, %453
-  %455 = select i1 %454, float 1.000000e+00, float 0.000000e+00
-  %456 = load <4 x float> addrspace(8)* null
-  %457 = extractelement <4 x float> %456, i32 3
-  %458 = fcmp une float 0xC0119BDA60000000, %457
-  %459 = select i1 %458, float 1.000000e+00, float 0.000000e+00
-  %460 = fsub float -0.000000e+00, %447
-  %461 = fptosi float %460 to i32
-  %462 = fsub float -0.000000e+00, %451
-  %463 = fptosi float %462 to i32
-  %464 = fsub float -0.000000e+00, %455
-  %465 = fptosi float %464 to i32
-  %466 = fsub float -0.000000e+00, %459
-  %467 = fptosi float %466 to i32
-  %468 = bitcast i32 %461 to float
-  %469 = bitcast i32 %463 to float
-  %470 = bitcast i32 %465 to float
-  %471 = bitcast i32 %467 to float
-  %472 = bitcast float %468 to i32
-  %473 = bitcast float %469 to i32
-  %474 = or i32 %472, %473
-  %475 = bitcast i32 %474 to float
-  %476 = bitcast float %470 to i32
-  %477 = bitcast float %471 to i32
-  %478 = or i32 %476, %477
-  %479 = bitcast i32 %478 to float
-  %480 = bitcast float %475 to i32
-  %481 = bitcast float %479 to i32
-  %482 = or i32 %480, %481
-  %483 = bitcast i32 %482 to float
-  %484 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
-  %485 = extractelement <4 x float> %484, i32 0
-  %486 = fcmp une float 0xC02085D640000000, %485
-  %487 = select i1 %486, float 1.000000e+00, float 0.000000e+00
-  %488 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
-  %489 = extractelement <4 x float> %488, i32 1
-  %490 = fcmp une float 0xBFD7C1BDA0000000, %489
-  %491 = select i1 %490, float 1.000000e+00, float 0.000000e+00
-  %492 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
-  %493 = extractelement <4 x float> %492, i32 2
-  %494 = fcmp une float 0x401E1D7DC0000000, %493
-  %495 = select i1 %494, float 1.000000e+00, float 0.000000e+00
-  %496 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
-  %497 = extractelement <4 x float> %496, i32 3
-  %498 = fcmp une float 0xC019893740000000, %497
-  %499 = select i1 %498, float 1.000000e+00, float 0.000000e+00
-  %500 = fsub float -0.000000e+00, %487
-  %501 = fptosi float %500 to i32
-  %502 = fsub float -0.000000e+00, %491
-  %503 = fptosi float %502 to i32
-  %504 = fsub float -0.000000e+00, %495
-  %505 = fptosi float %504 to i32
-  %506 = fsub float -0.000000e+00, %499
-  %507 = fptosi float %506 to i32
-  %508 = bitcast i32 %501 to float
-  %509 = bitcast i32 %503 to float
-  %510 = bitcast i32 %505 to float
-  %511 = bitcast i32 %507 to float
-  %512 = bitcast float %508 to i32
-  %513 = bitcast float %509 to i32
-  %514 = or i32 %512, %513
-  %515 = bitcast i32 %514 to float
-  %516 = bitcast float %510 to i32
-  %517 = bitcast float %511 to i32
-  %518 = or i32 %516, %517
-  %519 = bitcast i32 %518 to float
-  %520 = bitcast float %515 to i32
-  %521 = bitcast float %519 to i32
-  %522 = or i32 %520, %521
-  %523 = bitcast i32 %522 to float
-  %524 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
-  %525 = extractelement <4 x float> %524, i32 0
-  %526 = fcmp une float 0x40220F0D80000000, %525
-  %527 = select i1 %526, float 1.000000e+00, float 0.000000e+00
-  %528 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
-  %529 = extractelement <4 x float> %528, i32 1
-  %530 = fcmp une float 0xC018E2EB20000000, %529
-  %531 = select i1 %530, float 1.000000e+00, float 0.000000e+00
-  %532 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
-  %533 = extractelement <4 x float> %532, i32 2
-  %534 = fcmp une float 0xBFEA8DB8C0000000, %533
-  %535 = select i1 %534, float 1.000000e+00, float 0.000000e+00
-  %536 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
-  %537 = extractelement <4 x float> %536, i32 3
-  %538 = fcmp une float 0x4015236E20000000, %537
-  %539 = select i1 %538, float 1.000000e+00, float 0.000000e+00
-  %540 = fsub float -0.000000e+00, %527
-  %541 = fptosi float %540 to i32
-  %542 = fsub float -0.000000e+00, %531
-  %543 = fptosi float %542 to i32
-  %544 = fsub float -0.000000e+00, %535
-  %545 = fptosi float %544 to i32
-  %546 = fsub float -0.000000e+00, %539
-  %547 = fptosi float %546 to i32
-  %548 = bitcast i32 %541 to float
-  %549 = bitcast i32 %543 to float
-  %550 = bitcast i32 %545 to float
-  %551 = bitcast i32 %547 to float
-  %552 = bitcast float %548 to i32
-  %553 = bitcast float %549 to i32
-  %554 = or i32 %552, %553
-  %555 = bitcast i32 %554 to float
-  %556 = bitcast float %550 to i32
-  %557 = bitcast float %551 to i32
-  %558 = or i32 %556, %557
-  %559 = bitcast i32 %558 to float
-  %560 = bitcast float %555 to i32
-  %561 = bitcast float %559 to i32
-  %562 = or i32 %560, %561
-  %563 = bitcast i32 %562 to float
-  %564 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
-  %565 = extractelement <4 x float> %564, i32 0
-  %566 = fcmp une float 0x4016ED5D00000000, %565
-  %567 = select i1 %566, float 1.000000e+00, float 0.000000e+00
-  %568 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
-  %569 = extractelement <4 x float> %568, i32 1
-  %570 = fcmp une float 0x402332FEC0000000, %569
-  %571 = select i1 %570, float 1.000000e+00, float 0.000000e+00
-  %572 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
-  %573 = extractelement <4 x float> %572, i32 2
-  %574 = fcmp une float 0xC01484B5E0000000, %573
-  %575 = select i1 %574, float 1.000000e+00, float 0.000000e+00
-  %576 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
-  %577 = extractelement <4 x float> %576, i32 3
-  %578 = fcmp une float 0x400179A6C0000000, %577
-  %579 = select i1 %578, float 1.000000e+00, float 0.000000e+00
-  %580 = fsub float -0.000000e+00, %567
-  %581 = fptosi float %580 to i32
-  %582 = fsub float -0.000000e+00, %571
-  %583 = fptosi float %582 to i32
-  %584 = fsub float -0.000000e+00, %575
-  %585 = fptosi float %584 to i32
-  %586 = fsub float -0.000000e+00, %579
-  %587 = fptosi float %586 to i32
-  %588 = bitcast i32 %581 to float
-  %589 = bitcast i32 %583 to float
-  %590 = bitcast i32 %585 to float
-  %591 = bitcast i32 %587 to float
-  %592 = bitcast float %588 to i32
-  %593 = bitcast float %589 to i32
-  %594 = or i32 %592, %593
-  %595 = bitcast i32 %594 to float
-  %596 = bitcast float %590 to i32
-  %597 = bitcast float %591 to i32
-  %598 = or i32 %596, %597
-  %599 = bitcast i32 %598 to float
-  %600 = bitcast float %595 to i32
-  %601 = bitcast float %599 to i32
-  %602 = or i32 %600, %601
-  %603 = bitcast i32 %602 to float
-  %604 = insertelement <4 x float> undef, float %483, i32 0
-  %605 = insertelement <4 x float> %604, float %523, i32 1
-  %606 = insertelement <4 x float> %605, float %563, i32 2
-  %607 = insertelement <4 x float> %606, float %603, i32 3
-  %608 = insertelement <4 x float> undef, float %483, i32 0
-  %609 = insertelement <4 x float> %608, float %523, i32 1
-  %610 = insertelement <4 x float> %609, float %563, i32 2
-  %611 = insertelement <4 x float> %610, float %603, i32 3
-  %612 = call float @llvm.AMDGPU.dp4(<4 x float> %607, <4 x float> %611)
-  %613 = bitcast float %612 to i32
-  %614 = icmp ne i32 %613, 0
-  %615 = sext i1 %614 to i32
-  %616 = bitcast i32 %615 to float
-  %617 = bitcast float %616 to i32
-  %618 = xor i32 %617, -1
-  %619 = bitcast i32 %618 to float
-  %620 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
-  %621 = extractelement <4 x float> %620, i32 0
-  %622 = fcmp une float 0x40210068E0000000, %621
-  %623 = select i1 %622, float 1.000000e+00, float 0.000000e+00
-  %624 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
-  %625 = extractelement <4 x float> %624, i32 1
-  %626 = fcmp une float 0xBFC9A6B500000000, %625
-  %627 = select i1 %626, float 1.000000e+00, float 0.000000e+00
-  %628 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
-  %629 = extractelement <4 x float> %628, i32 2
-  %630 = fcmp une float 0xC0119BDA60000000, %629
-  %631 = select i1 %630, float 1.000000e+00, float 0.000000e+00
-  %632 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
-  %633 = extractelement <4 x float> %632, i32 3
-  %634 = fcmp une float 0xC02085D640000000, %633
-  %635 = select i1 %634, float 1.000000e+00, float 0.000000e+00
-  %636 = fsub float -0.000000e+00, %623
-  %637 = fptosi float %636 to i32
-  %638 = fsub float -0.000000e+00, %627
-  %639 = fptosi float %638 to i32
-  %640 = fsub float -0.000000e+00, %631
-  %641 = fptosi float %640 to i32
-  %642 = fsub float -0.000000e+00, %635
-  %643 = fptosi float %642 to i32
-  %644 = bitcast i32 %637 to float
-  %645 = bitcast i32 %639 to float
-  %646 = bitcast i32 %641 to float
-  %647 = bitcast i32 %643 to float
-  %648 = bitcast float %644 to i32
-  %649 = bitcast float %645 to i32
-  %650 = or i32 %648, %649
-  %651 = bitcast i32 %650 to float
-  %652 = bitcast float %646 to i32
-  %653 = bitcast float %647 to i32
-  %654 = or i32 %652, %653
-  %655 = bitcast i32 %654 to float
-  %656 = bitcast float %651 to i32
-  %657 = bitcast float %655 to i32
-  %658 = or i32 %656, %657
-  %659 = bitcast i32 %658 to float
-  %660 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
-  %661 = extractelement <4 x float> %660, i32 0
-  %662 = fcmp une float 0xBFD7C1BDA0000000, %661
-  %663 = select i1 %662, float 1.000000e+00, float 0.000000e+00
-  %664 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
-  %665 = extractelement <4 x float> %664, i32 1
-  %666 = fcmp une float 0x401E1D7DC0000000, %665
-  %667 = select i1 %666, float 1.000000e+00, float 0.000000e+00
-  %668 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
-  %669 = extractelement <4 x float> %668, i32 2
-  %670 = fcmp une float 0xC019893740000000, %669
-  %671 = select i1 %670, float 1.000000e+00, float 0.000000e+00
-  %672 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
-  %673 = extractelement <4 x float> %672, i32 3
-  %674 = fcmp une float 0x40220F0D80000000, %673
-  %675 = select i1 %674, float 1.000000e+00, float 0.000000e+00
-  %676 = fsub float -0.000000e+00, %663
-  %677 = fptosi float %676 to i32
-  %678 = fsub float -0.000000e+00, %667
-  %679 = fptosi float %678 to i32
-  %680 = fsub float -0.000000e+00, %671
-  %681 = fptosi float %680 to i32
-  %682 = fsub float -0.000000e+00, %675
-  %683 = fptosi float %682 to i32
-  %684 = bitcast i32 %677 to float
-  %685 = bitcast i32 %679 to float
-  %686 = bitcast i32 %681 to float
-  %687 = bitcast i32 %683 to float
-  %688 = bitcast float %684 to i32
-  %689 = bitcast float %685 to i32
-  %690 = or i32 %688, %689
-  %691 = bitcast i32 %690 to float
-  %692 = bitcast float %686 to i32
-  %693 = bitcast float %687 to i32
-  %694 = or i32 %692, %693
-  %695 = bitcast i32 %694 to float
-  %696 = bitcast float %691 to i32
-  %697 = bitcast float %695 to i32
-  %698 = or i32 %696, %697
-  %699 = bitcast i32 %698 to float
-  %700 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
-  %701 = extractelement <4 x float> %700, i32 0
-  %702 = fcmp une float 0xC018E2EB20000000, %701
-  %703 = select i1 %702, float 1.000000e+00, float 0.000000e+00
-  %704 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
-  %705 = extractelement <4 x float> %704, i32 1
-  %706 = fcmp une float 0xBFEA8DB8C0000000, %705
-  %707 = select i1 %706, float 1.000000e+00, float 0.000000e+00
-  %708 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
-  %709 = extractelement <4 x float> %708, i32 2
-  %710 = fcmp une float 0x4015236E20000000, %709
-  %711 = select i1 %710, float 1.000000e+00, float 0.000000e+00
-  %712 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
-  %713 = extractelement <4 x float> %712, i32 3
-  %714 = fcmp une float 0x4016ED5D00000000, %713
-  %715 = select i1 %714, float 1.000000e+00, float 0.000000e+00
-  %716 = fsub float -0.000000e+00, %703
-  %717 = fptosi float %716 to i32
-  %718 = fsub float -0.000000e+00, %707
-  %719 = fptosi float %718 to i32
-  %720 = fsub float -0.000000e+00, %711
-  %721 = fptosi float %720 to i32
-  %722 = fsub float -0.000000e+00, %715
-  %723 = fptosi float %722 to i32
-  %724 = bitcast i32 %717 to float
-  %725 = bitcast i32 %719 to float
-  %726 = bitcast i32 %721 to float
-  %727 = bitcast i32 %723 to float
-  %728 = bitcast float %724 to i32
-  %729 = bitcast float %725 to i32
-  %730 = or i32 %728, %729
-  %731 = bitcast i32 %730 to float
-  %732 = bitcast float %726 to i32
-  %733 = bitcast float %727 to i32
-  %734 = or i32 %732, %733
-  %735 = bitcast i32 %734 to float
-  %736 = bitcast float %731 to i32
-  %737 = bitcast float %735 to i32
-  %738 = or i32 %736, %737
-  %739 = bitcast i32 %738 to float
-  %740 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
-  %741 = extractelement <4 x float> %740, i32 0
-  %742 = fcmp une float 0x402332FEC0000000, %741
-  %743 = select i1 %742, float 1.000000e+00, float 0.000000e+00
-  %744 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
-  %745 = extractelement <4 x float> %744, i32 1
-  %746 = fcmp une float 0xC01484B5E0000000, %745
-  %747 = select i1 %746, float 1.000000e+00, float 0.000000e+00
-  %748 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
-  %749 = extractelement <4 x float> %748, i32 2
-  %750 = fcmp une float 0x400179A6C0000000, %749
-  %751 = select i1 %750, float 1.000000e+00, float 0.000000e+00
-  %752 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
-  %753 = extractelement <4 x float> %752, i32 3
-  %754 = fcmp une float 0xBFEE752540000000, %753
-  %755 = select i1 %754, float 1.000000e+00, float 0.000000e+00
-  %756 = fsub float -0.000000e+00, %743
-  %757 = fptosi float %756 to i32
-  %758 = fsub float -0.000000e+00, %747
-  %759 = fptosi float %758 to i32
-  %760 = fsub float -0.000000e+00, %751
-  %761 = fptosi float %760 to i32
-  %762 = fsub float -0.000000e+00, %755
-  %763 = fptosi float %762 to i32
-  %764 = bitcast i32 %757 to float
-  %765 = bitcast i32 %759 to float
-  %766 = bitcast i32 %761 to float
-  %767 = bitcast i32 %763 to float
-  %768 = bitcast float %764 to i32
-  %769 = bitcast float %765 to i32
-  %770 = or i32 %768, %769
-  %771 = bitcast i32 %770 to float
-  %772 = bitcast float %766 to i32
-  %773 = bitcast float %767 to i32
-  %774 = or i32 %772, %773
-  %775 = bitcast i32 %774 to float
-  %776 = bitcast float %771 to i32
-  %777 = bitcast float %775 to i32
-  %778 = or i32 %776, %777
-  %779 = bitcast i32 %778 to float
-  %780 = insertelement <4 x float> undef, float %659, i32 0
-  %781 = insertelement <4 x float> %780, float %699, i32 1
-  %782 = insertelement <4 x float> %781, float %739, i32 2
-  %783 = insertelement <4 x float> %782, float %779, i32 3
-  %784 = insertelement <4 x float> undef, float %659, i32 0
-  %785 = insertelement <4 x float> %784, float %699, i32 1
-  %786 = insertelement <4 x float> %785, float %739, i32 2
-  %787 = insertelement <4 x float> %786, float %779, i32 3
-  %788 = call float @llvm.AMDGPU.dp4(<4 x float> %783, <4 x float> %787)
-  %789 = bitcast float %788 to i32
-  %790 = icmp ne i32 %789, 0
-  %791 = sext i1 %790 to i32
-  %792 = bitcast i32 %791 to float
-  %793 = bitcast float %792 to i32
-  %794 = xor i32 %793, -1
-  %795 = bitcast i32 %794 to float
-  %796 = bitcast float %91 to i32
-  %797 = bitcast float %179 to i32
-  %798 = and i32 %796, %797
-  %799 = bitcast i32 %798 to float
-  %800 = bitcast float %311 to i32
-  %801 = bitcast float %443 to i32
-  %802 = and i32 %800, %801
-  %803 = bitcast i32 %802 to float
-  %804 = bitcast float %799 to i32
-  %805 = bitcast float %803 to i32
-  %806 = and i32 %804, %805
-  %807 = bitcast i32 %806 to float
-  %808 = bitcast float %619 to i32
-  %809 = bitcast float %795 to i32
-  %810 = and i32 %808, %809
-  %811 = bitcast i32 %810 to float
-  %812 = bitcast float %807 to i32
-  %813 = bitcast float %811 to i32
-  %814 = and i32 %812, %813
-  %815 = bitcast i32 %814 to float
-  %816 = bitcast float %815 to i32
-  %817 = icmp ne i32 %816, 0
-  %. = select i1 %817, float 1.000000e+00, float 0.000000e+00
-  %.32 = select i1 %817, float 0.000000e+00, float 1.000000e+00
-  %818 = insertelement <4 x float> undef, float %0, i32 0
-  %819 = insertelement <4 x float> %818, float %1, i32 1
-  %820 = insertelement <4 x float> %819, float %2, i32 2
-  %821 = insertelement <4 x float> %820, float %3, i32 3
-  call void @llvm.R600.store.swizzle(<4 x float> %821, i32 60, i32 1)
-  %822 = insertelement <4 x float> undef, float %.32, i32 0
-  %823 = insertelement <4 x float> %822, float %., i32 1
-  %824 = insertelement <4 x float> %823, float 0.000000e+00, i32 2
-  %825 = insertelement <4 x float> %824, float 1.000000e+00, i32 3
-  call void @llvm.R600.store.swizzle(<4 x float> %825, i32 0, i32 2)
-  ret void
-}
-
-declare float @llvm.R600.load.input(i32) #1
-
-declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
-
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { "ShaderType"="1" }
-attributes #1 = { readnone }
diff --git a/test/CodeGen/R600/and.ll b/test/CodeGen/R600/and.ll
index 166af2d..44c21bd 100644
--- a/test/CodeGen/R600/and.ll
+++ b/test/CodeGen/R600/and.ll
@@ -1,11 +1,36 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
 
-;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: @test2
+;EG-CHECK: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+;SI-CHECK: @test2
+;SI-CHECK: V_AND_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_AND_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %result = and <2 x i32> %a, %b
+  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+;EG-CHECK: @test4
+;EG-CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @test4
+;SI-CHECK: V_AND_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_AND_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_AND_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_AND_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
   %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
   %a = load <4 x i32> addrspace(1) * %in
   %b = load <4 x i32> addrspace(1) * %b_ptr
diff --git a/test/CodeGen/R600/bfi_int.ll b/test/CodeGen/R600/bfi_int.ll
index a1bd09a..cdccdfa 100644
--- a/test/CodeGen/R600/bfi_int.ll
+++ b/test/CodeGen/R600/bfi_int.ll
@@ -36,9 +36,9 @@ entry:
 ; SHA-256 Ma function
 ; ((x & z) | (y & (x | z)))
 ; R600-CHECK: @bfi_sha256_ma
-; R600-CHECK: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-CHECK: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; SI-CHECK: V_XOR_B32_e64 [[DST:VGPR[0-9]+]], {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}
+; R600-CHECK: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W
+; R600-CHECK: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, KC0[3].X, KC0[2].W
+; SI-CHECK: V_XOR_B32_e64 [[DST:VGPR[0-9]+]], {{[SV]GPR[0-9]+, VGPR[0-9]+}}
 ; SI-CHECK: V_BFI_B32 {{VGPR[0-9]+}}, [[DST]], {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}
 
 define void @bfi_sha256_ma(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
diff --git a/test/CodeGen/R600/build_vector.ll b/test/CodeGen/R600/build_vector.ll
new file mode 100644
index 0000000..9b738a2
--- /dev/null
+++ b/test/CodeGen/R600/build_vector.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
+
+; R600-CHECK: @build_vector2
+; R600-CHECK: MOV
+; R600-CHECK: MOV
+; R600-CHECK-NOT: MOV
+; SI-CHECK: @build_vector2
+; SI-CHECK-DAG: V_MOV_B32_e32 [[X:VGPR[0-9]]], 5
+; SI-CHECK-DAG: V_MOV_B32_e32 [[Y:VGPR[0-9]]], 6
+; SI-CHECK: BUFFER_STORE_DWORDX2 [[X]]_[[Y]]
+define void @build_vector2 (<2 x i32> addrspace(1)* %out) {
+entry:
+  store <2 x i32> <i32 5, i32 6>, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+; R600-CHECK: @build_vector4
+; R600-CHECK: MOV
+; R600-CHECK: MOV
+; R600-CHECK: MOV
+; R600-CHECK: MOV
+; R600-CHECK-NOT: MOV
+; SI-CHECK: @build_vector4
+; SI-CHECK-DAG: V_MOV_B32_e32 [[X:VGPR[0-9]]], 5
+; SI-CHECK-DAG: V_MOV_B32_e32 [[Y:VGPR[0-9]]], 6
+; SI-CHECK-DAG: V_MOV_B32_e32 [[Z:VGPR[0-9]]], 7
+; SI-CHECK-DAG: V_MOV_B32_e32 [[W:VGPR[0-9]]], 8
+; SI-CHECK: BUFFER_STORE_DWORDX4 [[X]]_[[Y]]_[[Z]]_[[W]]
+define void @build_vector4 (<4 x i32> addrspace(1)* %out) {
+entry:
+  store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/fabs.ll b/test/CodeGen/R600/fabs.ll
index 85f2882..78ffd57 100644
--- a/test/CodeGen/R600/fabs.ll
+++ b/test/CodeGen/R600/fabs.ll
@@ -1,16 +1,22 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
 
-;CHECK: MOV * T{{[0-9]+\.[XYZW], \|T[0-9]+\.[XYZW]\|}}
+; DAGCombiner will transform:
+; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
+; unless isFabsFree returns true
 
-define void @test() {
-   %r0 = call float @llvm.R600.load.input(i32 0)
-   %r1 = call float @fabs( float %r0)
-   call void @llvm.AMDGPU.store.output(float %r1, i32 0)
-   ret void
-}
-
-declare float @llvm.R600.load.input(i32) readnone
+; R600-CHECK: @fabs_free
+; R600-CHECK-NOT: AND
+; R600-CHECK: |PV.{{[XYZW]}}|
+; SI-CHECK: @fabs_free
+; SI-CHECK: V_ADD_F32_e64 VGPR{{[0-9]}}, SGPR{{[0-9]}}, 0, 1, 0, 0, 0
 
-declare void @llvm.AMDGPU.store.output(float, i32)
+define void @fabs_free(float addrspace(1)* %out, i32 %in) {
+entry:
+  %0 = bitcast i32 %in to float
+  %1 = call float @fabs(float %0)
+  store float %1, float addrspace(1)* %out
+  ret void
+}
 
 declare float @fabs(float ) readnone
diff --git a/test/CodeGen/R600/fadd.ll b/test/CodeGen/R600/fadd.ll
index 9a67232..97dbe44 100644
--- a/test/CodeGen/R600/fadd.ll
+++ b/test/CodeGen/R600/fadd.ll
@@ -15,6 +15,16 @@ declare float @llvm.R600.load.input(i32) readnone
 
 declare void @llvm.AMDGPU.store.output(float, i32)
 
+; CHECK: @fadd_v2f32
+; CHECK-DAG: ADD * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
+; CHECK-DAG: ADD * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
+define void @fadd_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
+entry:
+  %0 = fadd <2 x float> %a, %b
+  store <2 x float> %0, <2 x float> addrspace(1)* %out
+  ret void
+}
+
 ; CHECK: @fadd_v4f32
 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
diff --git a/test/CodeGen/R600/fadd64.ll b/test/CodeGen/R600/fadd64.ll
new file mode 100644
index 0000000..130302f
--- /dev/null
+++ b/test/CodeGen/R600/fadd64.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s
+
+; CHECK: @fadd_f64
+; CHECK: V_ADD_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}
+
+define void @fadd_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
+                      double addrspace(1)* %in2) {
+   %r0 = load double addrspace(1)* %in1
+   %r1 = load double addrspace(1)* %in2
+   %r2 = fadd double %r0, %r1
+   store double %r2, double addrspace(1)* %out
+   ret void
+}
diff --git a/test/CodeGen/R600/fcmp64.ll b/test/CodeGen/R600/fcmp64.ll
new file mode 100644
index 0000000..8f2513b
--- /dev/null
+++ b/test/CodeGen/R600/fcmp64.ll
@@ -0,0 +1,79 @@
+; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s
+
+; CHECK: @flt_f64
+; CHECK: V_CMP_LT_F64_e64 {{SGPR[0-9]+_SGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}
+
+define void @flt_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
+                     double addrspace(1)* %in2) {
+   %r0 = load double addrspace(1)* %in1
+   %r1 = load double addrspace(1)* %in2
+   %r2 = fcmp ult double %r0, %r1
+   %r3 = select i1 %r2, double %r0, double %r1
+   store double %r3, double addrspace(1)* %out
+   ret void
+}
+
+; CHECK: @fle_f64
+; CHECK: V_CMP_LE_F64_e64 {{SGPR[0-9]+_SGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}
+
+define void @fle_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
+                     double addrspace(1)* %in2) {
+   %r0 = load double addrspace(1)* %in1
+   %r1 = load double addrspace(1)* %in2
+   %r2 = fcmp ule double %r0, %r1
+   %r3 = select i1 %r2, double %r0, double %r1
+   store double %r3, double addrspace(1)* %out
+   ret void
+}
+
+; CHECK: @fgt_f64
+; CHECK: V_CMP_GT_F64_e64 {{SGPR[0-9]+_SGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}
+
+define void @fgt_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
+                     double addrspace(1)* %in2) {
+   %r0 = load double addrspace(1)* %in1
+   %r1 = load double addrspace(1)* %in2
+   %r2 = fcmp ugt double %r0, %r1
+   %r3 = select i1 %r2, double %r0, double %r1
+   store double %r3, double addrspace(1)* %out
+   ret void
+}
+
+; CHECK: @fge_f64
+; CHECK: V_CMP_GE_F64_e64 {{SGPR[0-9]+_SGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}
+
+define void @fge_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
+                     double addrspace(1)* %in2) {
+   %r0 = load double addrspace(1)* %in1
+   %r1 = load double addrspace(1)* %in2
+   %r2 = fcmp uge double %r0, %r1
+   %r3 = select i1 %r2, double %r0, double %r1
+   store double %r3, double addrspace(1)* %out
+   ret void
+}
+
+; CHECK: @fne_f64
+; CHECK: V_CMP_NEQ_F64_e64 {{SGPR[0-9]+_SGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}
+
+define void @fne_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
+                     double addrspace(1)* %in2) {
+   %r0 = load double addrspace(1)* %in1
+   %r1 = load double addrspace(1)* %in2
+   %r2 = fcmp une double %r0, %r1
+   %r3 = select i1 %r2, double %r0, double %r1
+   store double %r3, double addrspace(1)* %out
+   ret void
+}
+
+; CHECK: @feq_f64
+; CHECK: V_CMP_EQ_F64_e64 {{SGPR[0-9]+_SGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}
+
+define void @feq_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
+                     double addrspace(1)* %in2) {
+   %r0 = load double addrspace(1)* %in1
+   %r1 = load double addrspace(1)* %in2
+   %r2 = fcmp ueq double %r0, %r1
+   %r3 = select i1 %r2, double %r0, double %r1
+   store double %r3, double addrspace(1)* %out
+   ret void
+}
diff --git a/test/CodeGen/R600/fconst64.ll b/test/CodeGen/R600/fconst64.ll
new file mode 100644
index 0000000..2402a9c
--- /dev/null
+++ b/test/CodeGen/R600/fconst64.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s
+
+; CHECK: @fconst_f64
+; CHECK: V_MOV_B32_e32 {{VGPR[0-9]+}}, 0.000000e+00
+; CHECK-NEXT: V_MOV_B32_e32 {{VGPR[0-9]+}}, 2.312500e+00
+
+define void @fconst_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
+   %r1 = load double addrspace(1)* %in
+   %r2 = fadd double %r1, 5.000000e+00
+   store double %r2, double addrspace(1)* %out
+   ret void
+}
diff --git a/test/CodeGen/R600/fdiv.ll b/test/CodeGen/R600/fdiv.ll
index 003590b..6798eac 100644
--- a/test/CodeGen/R600/fdiv.ll
+++ b/test/CodeGen/R600/fdiv.ll
@@ -1,15 +1,32 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; These tests check that fdiv is expanded correctly and also test that the
+; scheduler is scheduling the RECIP_IEEE and MUL_IEEE instructions in separate
+; instruction groups.
 
-define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
+; CHECK: @fdiv_v2f32
+; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
+; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
+; CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
+; CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
+define void @fdiv_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
+entry:
+  %0 = fdiv <2 x float> %a, %b
+  store <2 x float> %0, <2 x float> addrspace(1)* %out
+  ret void
+}
+
+; CHECK: @fdiv_v4f32
+; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
+; CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
+; CHECK-DAG: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
+; CHECK-DAG: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
+
+define void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
   %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
   %a = load <4 x float> addrspace(1) * %in
   %b = load <4 x float> addrspace(1) * %b_ptr
diff --git a/test/CodeGen/R600/fdiv64.ll b/test/CodeGen/R600/fdiv64.ll
new file mode 100644
index 0000000..76c5ca3
--- /dev/null
+++ b/test/CodeGen/R600/fdiv64.ll
@@ -0,0 +1,14 @@
+; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s
+
+; CHECK: @fdiv_f64
+; CHECK: V_RCP_F64_e32 {{VGPR[0-9]+_VGPR[0-9]+}}
+; CHECK: V_MUL_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}
+
+define void @fdiv_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
+                      double addrspace(1)* %in2) {
+   %r0 = load double addrspace(1)* %in1
+   %r1 = load double addrspace(1)* %in2
+   %r2 = fdiv double %r0, %r1
+   store double %r2, double addrspace(1)* %out
+   ret void
+}
diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll
index a40e818..6ef3a11 100644
--- a/test/CodeGen/R600/fmul.ll
+++ b/test/CodeGen/R600/fmul.ll
@@ -15,6 +15,16 @@ declare float @llvm.R600.load.input(i32) readnone
 
 declare void @llvm.AMDGPU.store.output(float, i32)
 
+; CHECK: @fmul_v2f32
+; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
+; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW]}}
+define void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
+entry:
+  %0 = fmul <2 x float> %a, %b
+  store <2 x float> %0, <2 x float> addrspace(1)* %out
+  ret void
+}
+
 ; CHECK: @fmul_v4f32
 ; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
diff --git a/test/CodeGen/R600/fmul64.ll b/test/CodeGen/R600/fmul64.ll
new file mode 100644
index 0000000..8a57d4a
--- /dev/null
+++ b/test/CodeGen/R600/fmul64.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s
+
+; CHECK: @fmul_f64
+; CHECK: V_MUL_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}
+
+define void @fmul_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
+                      double addrspace(1)* %in2) {
+   %r0 = load double addrspace(1)* %in1
+   %r1 = load double addrspace(1)* %in2
+   %r2 = fmul double %r0, %r1
+   store double %r2, double addrspace(1)* %out
+   ret void
+}
diff --git a/test/CodeGen/R600/fneg.ll b/test/CodeGen/R600/fneg.ll
new file mode 100644
index 0000000..799db0c
--- /dev/null
+++ b/test/CodeGen/R600/fneg.ll
@@ -0,0 +1,38 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+; CHECK: @fneg_v2
+; CHECK: -PV
+; CHECK: -PV
+define void @fneg_v2(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
+entry:
+  %0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
+  store <2 x float> %0, <2 x float> addrspace(1)* %out
+  ret void
+}
+
+; CHECK: @fneg_v4
+; CHECK: -PV
+; CHECK: -PV
+; CHECK: -PV
+; CHECK: -PV
+define void @fneg_v4(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
+entry:
+  %0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
+  store <4 x float> %0, <4 x float> addrspace(1)* %out
+  ret void
+}
+
+; DAGCombiner will transform:
+; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000))
+; unless the target returns true for isNegFree()
+
+; CHECK-NOT: XOR
+; CHECK: -KC0[2].Z
+
+define void @fneg_free(float addrspace(1)* %out, i32 %in) {
+entry:
+  %0 = bitcast i32 %in to float
+  %1 = fsub float 0.0, %0
+  store float %1, float addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/fp_to_sint.ll b/test/CodeGen/R600/fp_to_sint.ll
index f5716e1..6471270 100644
--- a/test/CodeGen/R600/fp_to_sint.ll
+++ b/test/CodeGen/R600/fp_to_sint.ll
@@ -1,11 +1,28 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
 
-; CHECK: @fp_to_sint_v4i32
-; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; R600-CHECK: @fp_to_sint_v2i32
+; R600-CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; SI-CHECK: @fp_to_sint_v2i32
+; SI-CHECK: V_CVT_I32_F32_e32
+; SI-CHECK: V_CVT_I32_F32_e32
+define void @fp_to_sint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
+  %result = fptosi <2 x float> %in to <2 x i32>
+  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+  ret void
+}
 
+; R600-CHECK: @fp_to_sint_v4i32
+; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; SI-CHECK: @fp_to_sint_v4i32
+; SI-CHECK: V_CVT_I32_F32_e32
+; SI-CHECK: V_CVT_I32_F32_e32
+; SI-CHECK: V_CVT_I32_F32_e32
+; SI-CHECK: V_CVT_I32_F32_e32
 define void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
   %value = load <4 x float> addrspace(1) * %in
   %result = fptosi <4 x float> %value to <4 x i32>
diff --git a/test/CodeGen/R600/fp_to_uint.ll b/test/CodeGen/R600/fp_to_uint.ll
index 1c3c0c6..2a365f9 100644
--- a/test/CodeGen/R600/fp_to_uint.ll
+++ b/test/CodeGen/R600/fp_to_uint.ll
@@ -1,10 +1,20 @@
 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
+; CHECK: @fp_to_uint_v2i32
+; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+
+define void @fp_to_uint_v2i32(<2 x i32> addrspace(1)* %out, <2 x float> %in) {
+  %result = fptoui <2 x float> %in to <2 x i32>
+  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
 ; CHECK: @fp_to_uint_v4i32
-; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
 
 define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
   %value = load <4 x float> addrspace(1) * %in
diff --git a/test/CodeGen/R600/fsqrt.ll b/test/CodeGen/R600/fsqrt.ll
new file mode 100644
index 0000000..2613805
--- /dev/null
+++ b/test/CodeGen/R600/fsqrt.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s
+
+; CHECK: @fsqrt_f32
+; CHECK: V_SQRT_F32_e32 {{VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @fsqrt_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
+   %r0 = load float addrspace(1)* %in
+   %r1 = call float @llvm.sqrt.f32(float %r0)
+   store float %r1, float addrspace(1)* %out
+   ret void
+}
+
+; CHECK: @fsqrt_f64
+; CHECK: V_SQRT_F64_e32 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}
+
+define void @fsqrt_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
+   %r0 = load double addrspace(1)* %in
+   %r1 = call double @llvm.sqrt.f64(double %r0)
+   store double %r1, double addrspace(1)* %out
+   ret void
+}
+
+declare float @llvm.sqrt.f32(float %Val)
+declare double @llvm.sqrt.f64(double %Val)
diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll
index f784cde..0fc5860 100644
--- a/test/CodeGen/R600/fsub.ll
+++ b/test/CodeGen/R600/fsub.ll
@@ -15,12 +15,21 @@ declare float @llvm.R600.load.input(i32) readnone
 
 declare void @llvm.AMDGPU.store.output(float, i32)
 
-; CHECK: @fsub_v4f32
-; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: @fsub_v2f32
+; CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z
+; CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y
+define void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) {
+entry:
+  %0 = fsub <2 x float> %a, %b
+  store <2 x float> %0, <2 x float> addrspace(1)* %out
+  ret void
+}
 
+; CHECK: @fsub_v4f32
+; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
+; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
+; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
+; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}}
 define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
   %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1
   %a = load <4 x float> addrspace(1) * %in
diff --git a/test/CodeGen/R600/fsub64.ll b/test/CodeGen/R600/fsub64.ll
new file mode 100644
index 0000000..fa59dcc
--- /dev/null
+++ b/test/CodeGen/R600/fsub64.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s
+
+; CHECK: @fsub_f64
+; CHECK: V_ADD_F64 {{VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+, VGPR[0-9]+_VGPR[0-9]+}}, 0, 0, 0, 0, 2
+
+define void @fsub_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
+                      double addrspace(1)* %in2) {
+   %r0 = load double addrspace(1)* %in1
+   %r1 = load double addrspace(1)* %in2
+   %r2 = fsub double %r0, %r1
+   store double %r2, double addrspace(1)* %out
+   ret void
+}
diff --git a/test/CodeGen/R600/indirect-addressing-si.ll b/test/CodeGen/R600/indirect-addressing-si.ll
new file mode 100644
index 0000000..ba5de22
--- /dev/null
+++ b/test/CodeGen/R600/indirect-addressing-si.ll
@@ -0,0 +1,48 @@
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+
+; Tests for indirect addressing on SI, which is implemented using dynamic
+; indexing of vectors.
+
+; CHECK: extract_w_offset
+; CHECK: S_MOV_B32 M0
+; CHECK-NEXT: V_MOVRELS_B32_e32
+define void @extract_w_offset(float addrspace(1)* %out, i32 %in) {
+entry:
+  %0 = add i32 %in, 1
+  %1 = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %0
+  store float %1, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK: extract_wo_offset
+; CHECK: S_MOV_B32 M0
+; CHECK-NEXT: V_MOVRELS_B32_e32
+define void @extract_wo_offset(float addrspace(1)* %out, i32 %in) {
+entry:
+  %0 = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %in
+  store float %0, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK: insert_w_offset
+; CHECK: S_MOV_B32 M0
+; CHECK-NEXT: V_MOVRELD_B32_e32
+define void @insert_w_offset(float addrspace(1)* %out, i32 %in) {
+entry:
+  %0 = add i32 %in, 1
+  %1 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %0
+  %2 = extractelement <4 x float> %1, i32 2
+  store float %2, float addrspace(1)* %out
+  ret void
+}
+
+; CHECK: insert_wo_offset
+; CHECK: S_MOV_B32 M0
+; CHECK-NEXT: V_MOVRELD_B32_e32
+define void @insert_wo_offset(float addrspace(1)* %out, i32 %in) {
+entry:
+  %0 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %in
+  %1 = extractelement <4 x float> %0, i32 2
+  store float %1, float addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/jump-address.ll b/test/CodeGen/R600/jump-address.ll
index ae9c8bb..26c298b 100644
--- a/test/CodeGen/R600/jump-address.ll
+++ b/test/CodeGen/R600/jump-address.ll
@@ -1,6 +1,6 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-; CHECK: JUMP @3
+; CHECK: JUMP @5
 ; CHECK: EXPORT
 ; CHECK-NOT: EXPORT
 
diff --git a/test/CodeGen/R600/literals.ll b/test/CodeGen/R600/literals.ll
index 21e5d4c..77b168e 100644
--- a/test/CodeGen/R600/literals.ll
+++ b/test/CodeGen/R600/literals.ll
@@ -2,12 +2,12 @@
 
 ; Test using an integer literal constant.
 ; Generated ASM should be:
-; ADD_INT REG literal.x, 5
+; ADD_INT KC0[2].Z literal.x, 5
 ; or
-; ADD_INT literal.x REG, 5
+; ADD_INT literal.x KC0[2].Z, 5
 
 ; CHECK: @i32_literal
-; CHECK: ADD_INT * {{[A-Z0-9,. ]*}}literal.x
+; CHECK: ADD_INT * T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
 ; CHECK-NEXT: 5
 define void @i32_literal(i32 addrspace(1)* %out, i32 %in) {
 entry:
@@ -18,12 +18,12 @@ entry:
 
 ; Test using a float literal constant.
 ; Generated ASM should be:
-; ADD REG literal.x, 5.0
+; ADD KC0[2].Z literal.x, 5.0
 ; or
-; ADD literal.x REG, 5.0
+; ADD literal.x KC0[2].Z, 5.0
 
 ; CHECK: @float_literal
-; CHECK: ADD * {{[A-Z0-9,. ]*}}literal.x
+; CHECK: ADD * T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
 ; CHECK-NEXT: 1084227584(5.0
 define void @float_literal(float addrspace(1)* %out, float %in) {
 entry:
@@ -31,169 +31,3 @@ entry:
   store float %0, float addrspace(1)* %out
   ret void
 }
-
-; CHECK: @main
-; CHECK: -2147483648
-; CHECK-NEXT-NOT: -2147483648
-
-define void @main() #0 {
-main_body:
-  %0 = call float @llvm.R600.load.input(i32 4)
-  %1 = call float @llvm.R600.load.input(i32 5)
-  %2 = call float @llvm.R600.load.input(i32 6)
-  %3 = call float @llvm.R600.load.input(i32 7)
-  %4 = call float @llvm.R600.load.input(i32 8)
-  %5 = call float @llvm.R600.load.input(i32 9)
-  %6 = call float @llvm.R600.load.input(i32 10)
-  %7 = call float @llvm.R600.load.input(i32 11)
-  %8 = call float @llvm.R600.load.input(i32 12)
-  %9 = call float @llvm.R600.load.input(i32 13)
-  %10 = call float @llvm.R600.load.input(i32 14)
-  %11 = call float @llvm.R600.load.input(i32 15)
-  %12 = load <4 x float> addrspace(8)* null
-  %13 = extractelement <4 x float> %12, i32 0
-  %14 = fsub float -0.000000e+00, %13
-  %15 = fadd float %0, %14
-  %16 = load <4 x float> addrspace(8)* null
-  %17 = extractelement <4 x float> %16, i32 1
-  %18 = fsub float -0.000000e+00, %17
-  %19 = fadd float %1, %18
-  %20 = load <4 x float> addrspace(8)* null
-  %21 = extractelement <4 x float> %20, i32 2
-  %22 = fsub float -0.000000e+00, %21
-  %23 = fadd float %2, %22
-  %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
-  %25 = extractelement <4 x float> %24, i32 0
-  %26 = fmul float %25, %0
-  %27 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
-  %28 = extractelement <4 x float> %27, i32 1
-  %29 = fmul float %28, %0
-  %30 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
-  %31 = extractelement <4 x float> %30, i32 2
-  %32 = fmul float %31, %0
-  %33 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
-  %34 = extractelement <4 x float> %33, i32 3
-  %35 = fmul float %34, %0
-  %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
-  %37 = extractelement <4 x float> %36, i32 0
-  %38 = fmul float %37, %1
-  %39 = fadd float %38, %26
-  %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
-  %41 = extractelement <4 x float> %40, i32 1
-  %42 = fmul float %41, %1
-  %43 = fadd float %42, %29
-  %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
-  %45 = extractelement <4 x float> %44, i32 2
-  %46 = fmul float %45, %1
-  %47 = fadd float %46, %32
-  %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
-  %49 = extractelement <4 x float> %48, i32 3
-  %50 = fmul float %49, %1
-  %51 = fadd float %50, %35
-  %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
-  %53 = extractelement <4 x float> %52, i32 0
-  %54 = fmul float %53, %2
-  %55 = fadd float %54, %39
-  %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
-  %57 = extractelement <4 x float> %56, i32 1
-  %58 = fmul float %57, %2
-  %59 = fadd float %58, %43
-  %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
-  %61 = extractelement <4 x float> %60, i32 2
-  %62 = fmul float %61, %2
-  %63 = fadd float %62, %47
-  %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
-  %65 = extractelement <4 x float> %64, i32 3
-  %66 = fmul float %65, %2
-  %67 = fadd float %66, %51
-  %68 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
-  %69 = extractelement <4 x float> %68, i32 0
-  %70 = fmul float %69, %3
-  %71 = fadd float %70, %55
-  %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
-  %73 = extractelement <4 x float> %72, i32 1
-  %74 = fmul float %73, %3
-  %75 = fadd float %74, %59
-  %76 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
-  %77 = extractelement <4 x float> %76, i32 2
-  %78 = fmul float %77, %3
-  %79 = fadd float %78, %63
-  %80 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
-  %81 = extractelement <4 x float> %80, i32 3
-  %82 = fmul float %81, %3
-  %83 = fadd float %82, %67
-  %84 = insertelement <4 x float> undef, float %15, i32 0
-  %85 = insertelement <4 x float> %84, float %19, i32 1
-  %86 = insertelement <4 x float> %85, float %23, i32 2
-  %87 = insertelement <4 x float> %86, float 0.000000e+00, i32 3
-  %88 = insertelement <4 x float> undef, float %15, i32 0
-  %89 = insertelement <4 x float> %88, float %19, i32 1
-  %90 = insertelement <4 x float> %89, float %23, i32 2
-  %91 = insertelement <4 x float> %90, float 0.000000e+00, i32 3
-  %92 = call float @llvm.AMDGPU.dp4(<4 x float> %87, <4 x float> %91)
-  %93 = call float @fabs(float %92)
-  %94 = call float @llvm.AMDGPU.rsq(float %93)
-  %95 = fmul float %15, %94
-  %96 = fmul float %19, %94
-  %97 = fmul float %23, %94
-  %98 = insertelement <4 x float> undef, float %4, i32 0
-  %99 = insertelement <4 x float> %98, float %5, i32 1
-  %100 = insertelement <4 x float> %99, float %6, i32 2
-  %101 = insertelement <4 x float> %100, float 0.000000e+00, i32 3
-  %102 = insertelement <4 x float> undef, float %4, i32 0
-  %103 = insertelement <4 x float> %102, float %5, i32 1
-  %104 = insertelement <4 x float> %103, float %6, i32 2
-  %105 = insertelement <4 x float> %104, float 0.000000e+00, i32 3
-  %106 = call float @llvm.AMDGPU.dp4(<4 x float> %101, <4 x float> %105)
-  %107 = call float @fabs(float %106)
-  %108 = call float @llvm.AMDGPU.rsq(float %107)
-  %109 = fmul float %4, %108
-  %110 = fmul float %5, %108
-  %111 = fmul float %6, %108
-  %112 = insertelement <4 x float> undef, float %95, i32 0
-  %113 = insertelement <4 x float> %112, float %96, i32 1
-  %114 = insertelement <4 x float> %113, float %97, i32 2
-  %115 = insertelement <4 x float> %114, float 0.000000e+00, i32 3
-  %116 = insertelement <4 x float> undef, float %109, i32 0
-  %117 = insertelement <4 x float> %116, float %110, i32 1
-  %118 = insertelement <4 x float> %117, float %111, i32 2
-  %119 = insertelement <4 x float> %118, float 0.000000e+00, i32 3
-  %120 = call float @llvm.AMDGPU.dp4(<4 x float> %115, <4 x float> %119)
-  %121 = fsub float -0.000000e+00, %120
-  %122 = fcmp uge float 0.000000e+00, %121
-  %123 = select i1 %122, float 0.000000e+00, float %121
-  %124 = insertelement <4 x float> undef, float %8, i32 0
-  %125 = insertelement <4 x float> %124, float %9, i32 1
-  %126 = insertelement <4 x float> %125, float 5.000000e-01, i32 2
-  %127 = insertelement <4 x float> %126, float 1.000000e+00, i32 3
-  call void @llvm.R600.store.swizzle(<4 x float> %127, i32 60, i32 1)
-  %128 = insertelement <4 x float> undef, float %71, i32 0
-  %129 = insertelement <4 x float> %128, float %75, i32 1
-  %130 = insertelement <4 x float> %129, float %79, i32 2
-  %131 = insertelement <4 x float> %130, float %83, i32 3
-  call void @llvm.R600.store.swizzle(<4 x float> %131, i32 0, i32 2)
-  %132 = insertelement <4 x float> undef, float %123, i32 0
-  %133 = insertelement <4 x float> %132, float %96, i32 1
-  %134 = insertelement <4 x float> %133, float %97, i32 2
-  %135 = insertelement <4 x float> %134, float 0.000000e+00, i32 3
-  call void @llvm.R600.store.swizzle(<4 x float> %135, i32 1, i32 2)
-  ret void
-}
-
-; Function Attrs: readnone
-declare float @llvm.R600.load.input(i32) #1
-
-; Function Attrs: readnone
-declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
-
-; Function Attrs: readonly
-declare float @fabs(float) #2
-
-; Function Attrs: readnone
-declare float @llvm.AMDGPU.rsq(float) #1
-
-declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
-
-attributes #0 = { "ShaderType"="1" }
-attributes #1 = { readnone }
-attributes #2 = { readonly }
diff --git a/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll b/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll
new file mode 100644
index 0000000..8d3c9ca
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.barrier.local.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+; CHECK: GROUP_BARRIER
+
+define void @test(i32 addrspace(1)* %out) {
+entry:
+  %0 = call i32 @llvm.r600.read.tidig.x()
+  %1 = getelementptr i32 addrspace(1)* %out, i32 %0
+  store i32 %0, i32 addrspace(1)* %1
+  call void @llvm.AMDGPU.barrier.local()
+  %2 = call i32 @llvm.r600.read.local.size.x()
+  %3 = sub i32 %2, 1
+  %4 = sub i32 %3, %0
+  %5 = getelementptr i32 addrspace(1)* %out, i32 %4
+  %6 = load i32 addrspace(1)* %5
+  store i32 %6, i32 addrspace(1)* %1
+  ret void
+}
+
+declare i32 @llvm.r600.read.tidig.x() #0
+declare void @llvm.AMDGPU.barrier.local()
+declare i32 @llvm.r600.read.local.size.x() #0
+
+attributes #0 = { readnone }
diff --git a/test/CodeGen/R600/llvm.AMDGPU.cube.ll b/test/CodeGen/R600/llvm.AMDGPU.cube.ll
new file mode 100644
index 0000000..110bbfd
--- /dev/null
+++ b/test/CodeGen/R600/llvm.AMDGPU.cube.ll
@@ -0,0 +1,59 @@
+
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+; CHECK: @cube
+; CHECK: CUBE T{{[0-9]}}.X
+; CHECK: CUBE T{{[0-9]}}.Y
+; CHECK: CUBE T{{[0-9]}}.Z
+; CHECK: CUBE * T{{[0-9]}}.W
+define void @cube() #0 {
+main_body:
+  %0 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+  %1 = extractelement <4 x float> %0, i32 3
+  %2 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+  %3 = extractelement <4 x float> %2, i32 0
+  %4 = fdiv float %3, %1
+  %5 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+  %6 = extractelement <4 x float> %5, i32 1
+  %7 = fdiv float %6, %1
+  %8 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9)
+  %9 = extractelement <4 x float> %8, i32 2
+  %10 = fdiv float %9, %1
+  %11 = insertelement <4 x float> undef, float %4, i32 0
+  %12 = insertelement <4 x float> %11, float %7, i32 1
+  %13 = insertelement <4 x float> %12, float %10, i32 2
+  %14 = insertelement <4 x float> %13, float 1.000000e+00, i32 3
+  %15 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %14)
+  %16 = extractelement <4 x float> %15, i32 0
+  %17 = extractelement <4 x float> %15, i32 1
+  %18 = extractelement <4 x float> %15, i32 2
+  %19 = extractelement <4 x float> %15, i32 3
+  %20 = call float @fabs(float %18)
+  %21 = fdiv float 1.000000e+00, %20
+  %22 = fmul float %16, %21
+  %23 = fadd float %22, 1.500000e+00
+  %24 = fmul float %17, %21
+  %25 = fadd float %24, 1.500000e+00
+  %26 = insertelement <4 x float> undef, float %25, i32 0
+  %27 = insertelement <4 x float> %26, float %23, i32 1
+  %28 = insertelement <4 x float> %27, float %19, i32 2
+  %29 = insertelement <4 x float> %28, float %25, i32 3
+  %30 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %29, i32 16, i32 0, i32 4)
+  call void @llvm.R600.store.swizzle(<4 x float> %30, i32 0, i32 0)
+  ret void
+}
+
+; Function Attrs: readnone
+declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #1
+
+; Function Attrs: readnone
+declare float @fabs(float) #1
+
+; Function Attrs: readnone
+declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1
+
+declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
+
+attributes #0 = { "ShaderType"="0" }
+attributes #1 = { readnone }
+
diff --git a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
index cdc03f8..7627783 100644
--- a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
 
 ; R600-CHECK: @amdgpu_trunc
-; R600-CHECK: TRUNC * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; R600-CHECK: TRUNC * T{{[0-9]+\.[XYZW]}}, KC0[2].Z
 ; SI-CHECK: @amdgpu_trunc
 ; SI-CHECK: V_TRUNC_F32
 
diff --git a/test/CodeGen/R600/llvm.SI.imageload.ll b/test/CodeGen/R600/llvm.SI.imageload.ll
index 6b321f0..0adcdfc 100644
--- a/test/CodeGen/R600/llvm.SI.imageload.ll
+++ b/test/CodeGen/R600/llvm.SI.imageload.ll
@@ -1,15 +1,15 @@
 ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
 
-;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15, 0, 0, -1
-;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 3, 0, 0, 0
-;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 2, 0, 0, 0
-;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 1, 0, 0, 0
-;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 4, 0, 0, 0
-;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 8, 0, 0, 0
-;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 5, 0, 0, 0
-;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 12, 0, 0, -1
-;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7, 0, 0, 0
-;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 8, 0, 0, -1
+;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15, 0, 0, -1
+;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 3, 0, 0, 0
+;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 2, 0, 0, 0
+;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 1, 0, 0, 0
+;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 4, 0, 0, 0
+;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 8, 0, 0, 0
+;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 5, 0, 0, 0
+;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 12, 0, 0, -1
+;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7, 0, 0, 0
+;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 8, 0, 0, -1
 
 define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
    %v1 = insertelement <4 x i32> undef, i32 %a1, i32 0
diff --git a/test/CodeGen/R600/llvm.SI.sample.ll b/test/CodeGen/R600/llvm.SI.sample.ll
index de06354..7655996 100644
--- a/test/CodeGen/R600/llvm.SI.sample.ll
+++ b/test/CodeGen/R600/llvm.SI.sample.ll
@@ -1,21 +1,21 @@
 ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
 
-;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15
-;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 3
-;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 2
-;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 1
-;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 4
-;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 8
-;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 5
-;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 9
-;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 6
-;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 10
-;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 12
-;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7
-;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 11
-;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 13
-;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 14
-;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 8
+;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15
+;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 3
+;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+}}, 2
+;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+}}, 1
+;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+}}, 4
+;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+}}, 8
+;CHECK-DAG: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 5
+;CHECK-DAG: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 9
+;CHECK-DAG: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 6
+;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 10
+;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 12
+;CHECK-DAG: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7
+;CHECK-DAG: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 11
+;CHECK-DAG: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 13
+;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 14
+;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+}}, 8
 
 define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
    %v1 = insertelement <4 x i32> undef, i32 %a1, i32 0
diff --git a/test/CodeGen/R600/llvm.SI.sampled.ll b/test/CodeGen/R600/llvm.SI.sampled.ll
new file mode 100644
index 0000000..3b05551
--- /dev/null
+++ b/test/CodeGen/R600/llvm.SI.sampled.ll
@@ -0,0 +1,140 @@
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
+
+;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15
+;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+}}, 3
+;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 2
+;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 1
+;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 4
+;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 8
+;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+}}, 5
+;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+}}, 9
+;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+}}, 6
+;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+}}, 10
+;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+}}, 12
+;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7
+;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 11
+;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 13
+;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 14
+;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 8
+
+define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
+   %v1 = insertelement <4 x i32> undef, i32 %a1, i32 0
+   %v2 = insertelement <4 x i32> undef, i32 %a1, i32 1
+   %v3 = insertelement <4 x i32> undef, i32 %a1, i32 2
+   %v4 = insertelement <4 x i32> undef, i32 %a1, i32 3
+   %v5 = insertelement <4 x i32> undef, i32 %a2, i32 0
+   %v6 = insertelement <4 x i32> undef, i32 %a2, i32 1
+   %v7 = insertelement <4 x i32> undef, i32 %a2, i32 2
+   %v8 = insertelement <4 x i32> undef, i32 %a2, i32 3
+   %v9 = insertelement <4 x i32> undef, i32 %a3, i32 0
+   %v10 = insertelement <4 x i32> undef, i32 %a3, i32 1
+   %v11 = insertelement <4 x i32> undef, i32 %a3, i32 2
+   %v12 = insertelement <4 x i32> undef, i32 %a3, i32 3
+   %v13 = insertelement <4 x i32> undef, i32 %a4, i32 0
+   %v14 = insertelement <4 x i32> undef, i32 %a4, i32 1
+   %v15 = insertelement <4 x i32> undef, i32 %a4, i32 2
+   %v16 = insertelement <4 x i32> undef, i32 %a4, i32 3
+   %res1 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v1,
+      <8 x i32> undef, <4 x i32> undef, i32 1)
+   %res2 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v2,
+      <8 x i32> undef, <4 x i32> undef, i32 2)
+   %res3 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v3,
+      <8 x i32> undef, <4 x i32> undef, i32 3)
+   %res4 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v4,
+      <8 x i32> undef, <4 x i32> undef, i32 4)
+   %res5 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v5,
+      <8 x i32> undef, <4 x i32> undef, i32 5)
+   %res6 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v6,
+      <8 x i32> undef, <4 x i32> undef, i32 6)
+   %res7 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v7,
+      <8 x i32> undef, <4 x i32> undef, i32 7)
+   %res8 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v8,
+      <8 x i32> undef, <4 x i32> undef, i32 8)
+   %res9 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v9,
+      <8 x i32> undef, <4 x i32> undef, i32 9)
+   %res10 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v10,
+      <8 x i32> undef, <4 x i32> undef, i32 10)
+   %res11 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v11,
+      <8 x i32> undef, <4 x i32> undef, i32 11)
+   %res12 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v12,
+      <8 x i32> undef, <4 x i32> undef, i32 12)
+   %res13 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v13,
+      <8 x i32> undef, <4 x i32> undef, i32 13)
+   %res14 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v14,
+      <8 x i32> undef, <4 x i32> undef, i32 14)
+   %res15 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v15,
+      <8 x i32> undef, <4 x i32> undef, i32 15)
+   %res16 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v16,
+      <8 x i32> undef, <4 x i32> undef, i32 16)
+   %e1 = extractelement <4 x float> %res1, i32 0
+   %e2 = extractelement <4 x float> %res2, i32 1
+   %e3 = extractelement <4 x float> %res3, i32 2
+   %e4 = extractelement <4 x float> %res4, i32 3
+   %t0 = extractelement <4 x float> %res5, i32 0
+   %t1 = extractelement <4 x float> %res5, i32 1
+   %e5 = fadd float %t0, %t1
+   %t2 = extractelement <4 x float> %res6, i32 0
+   %t3 = extractelement <4 x float> %res6, i32 2
+   %e6 = fadd float %t2, %t3
+   %t4 = extractelement <4 x float> %res7, i32 0
+   %t5 = extractelement <4 x float> %res7, i32 3
+   %e7 = fadd float %t4, %t5
+   %t6 = extractelement <4 x float> %res8, i32 1
+   %t7 = extractelement <4 x float> %res8, i32 2
+   %e8 = fadd float %t6, %t7
+   %t8 = extractelement <4 x float> %res9, i32 1
+   %t9 = extractelement <4 x float> %res9, i32 3
+   %e9 = fadd float %t8, %t9
+   %t10 = extractelement <4 x float> %res10, i32 2
+   %t11 = extractelement <4 x float> %res10, i32 3
+   %e10 = fadd float %t10, %t11
+   %t12 = extractelement <4 x float> %res11, i32 0
+   %t13 = extractelement <4 x float> %res11, i32 1
+   %t14 = extractelement <4 x float> %res11, i32 2
+   %t15 = fadd float %t12, %t13
+   %e11 = fadd float %t14, %t15
+   %t16 = extractelement <4 x float> %res12, i32 0
+   %t17 = extractelement <4 x float> %res12, i32 1
+   %t18 = extractelement <4 x float> %res12, i32 3
+   %t19 = fadd float %t16, %t17
+   %e12 = fadd float %t18, %t19
+   %t20 = extractelement <4 x float> %res13, i32 0
+   %t21 = extractelement <4 x float> %res13, i32 2
+   %t22 = extractelement <4 x float> %res13, i32 3
+   %t23 = fadd float %t20, %t21
+   %e13 = fadd float %t22, %t23
+   %t24 = extractelement <4 x float> %res14, i32 1
+   %t25 = extractelement <4 x float> %res14, i32 2
+   %t26 = extractelement <4 x float> %res14, i32 3
+   %t27 = fadd float %t24, %t25
+   %e14 = fadd float %t26, %t27
+   %t28 = extractelement <4 x float> %res15, i32 0
+   %t29 = extractelement <4 x float> %res15, i32 1
+   %t30 = extractelement <4 x float> %res15, i32 2
+   %t31 = extractelement <4 x float> %res15, i32 3
+   %t32 = fadd float %t28, %t29
+   %t33 = fadd float %t30, %t31
+   %e15 = fadd float %t32, %t33
+   %e16 = extractelement <4 x float> %res16, i32 3
+   %s1 = fadd float %e1, %e2
+   %s2 = fadd float %s1, %e3
+   %s3 = fadd float %s2, %e4
+   %s4 = fadd float %s3, %e5
+   %s5 = fadd float %s4, %e6
+   %s6 = fadd float %s5, %e7
+   %s7 = fadd float %s6, %e8
+   %s8 = fadd float %s7, %e9
+   %s9 = fadd float %s8, %e10
+   %s10 = fadd float %s9, %e11
+   %s11 = fadd float %s10, %e12
+   %s12 = fadd float %s11, %e13
+   %s13 = fadd float %s12, %e14
+   %s14 = fadd float %s13, %e15
+   %s15 = fadd float %s14, %e16
+   call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %s15, float %s15, float %s15, float %s15)
+   ret void
+}
+
+declare <4 x float> @llvm.SI.sampled.(<4 x i32>, <8 x i32>, <4 x i32>, i32) readnone
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
diff --git a/test/CodeGen/R600/llvm.SI.tid.ll b/test/CodeGen/R600/llvm.SI.tid.ll
new file mode 100644
index 0000000..238d9f2
--- /dev/null
+++ b/test/CodeGen/R600/llvm.SI.tid.ll
@@ -0,0 +1,16 @@
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
+
+;CHECK: V_MBCNT_LO_U32_B32_e64
+;CHECK: V_MBCNT_HI_U32_B32_e32
+
+define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" {
+main_body:
+  %4 = call i32 @llvm.SI.tid()
+  %5 = bitcast i32 %4 to float
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %5, float %5, float %5)
+  ret void
+}
+
+declare i32 @llvm.SI.tid() readnone
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
diff --git a/test/CodeGen/R600/llvm.cos.ll b/test/CodeGen/R600/llvm.cos.ll
index 9b28167..8fb4559 100644
--- a/test/CodeGen/R600/llvm.cos.ll
+++ b/test/CodeGen/R600/llvm.cos.ll
@@ -1,6 +1,9 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-;CHECK: COS * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: MULADD_IEEE *
+;CHECK: FRACT *
+;CHECK: ADD *
+;CHECK: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
 
 define void @test() {
    %r0 = call float @llvm.R600.load.input(i32 0)
diff --git a/test/CodeGen/R600/llvm.pow.ll b/test/CodeGen/R600/llvm.pow.ll
index 1422083..0f51cf4 100644
--- a/test/CodeGen/R600/llvm.pow.ll
+++ b/test/CodeGen/R600/llvm.pow.ll
@@ -1,8 +1,8 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
 ;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}
+;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
 
 define void @test() {
    %r0 = call float @llvm.R600.load.input(i32 0)
diff --git a/test/CodeGen/R600/llvm.sin.ll b/test/CodeGen/R600/llvm.sin.ll
index 803dc2d..e94c2ba 100644
--- a/test/CodeGen/R600/llvm.sin.ll
+++ b/test/CodeGen/R600/llvm.sin.ll
@@ -1,6 +1,9 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-;CHECK: SIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: MULADD_IEEE *
+;CHECK: FRACT *
+;CHECK: ADD *
+;CHECK: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
 
 define void @test() {
    %r0 = call float @llvm.R600.load.input(i32 0)
diff --git a/test/CodeGen/R600/load.ll b/test/CodeGen/R600/load.ll
index ff774ec..f478ef5 100644
--- a/test/CodeGen/R600/load.ll
+++ b/test/CodeGen/R600/load.ll
@@ -1,6 +1,11 @@
 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
+; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600-CHECK %s
 ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK  %s
 
+;===------------------------------------------------------------------------===;
+; GLOBAL ADDRESS SPACE
+;===------------------------------------------------------------------------===;
+
 ; Load an i8 value from the global address space.
 ; R600-CHECK: @load_i8
 ; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
@@ -14,6 +19,51 @@ define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
   ret void
 }
 
+; R600-CHECK: @load_i8_sext
+; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
+; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
+; R600-CHECK: 24
+; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
+; R600-CHECK: 24
+; SI-CHECK: @load_i8_sext
+; SI-CHECK: BUFFER_LOAD_SBYTE
+define void @load_i8_sext(i32 addrspace(1)* %out, i8 addrspace(1)* %in) {
+entry:
+  %0 = load i8 addrspace(1)* %in
+  %1 = sext i8 %0 to i32
+  store i32 %1, i32 addrspace(1)* %out
+  ret void
+}
+
+; Load an i16 value from the global address space.
+; R600-CHECK: @load_i16
+; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
+; SI-CHECK: @load_i16
+; SI-CHECK: BUFFER_LOAD_USHORT
+define void @load_i16(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
+entry:
+  %0 = load i16	 addrspace(1)* %in
+  %1 = zext i16 %0 to i32
+  store i32 %1, i32 addrspace(1)* %out
+  ret void
+}
+
+; R600-CHECK: @load_i16_sext
+; R600-CHECK: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]]
+; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
+; R600-CHECK: 16
+; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
+; R600-CHECK: 16
+; SI-CHECK: @load_i16_sext
+; SI-CHECK: BUFFER_LOAD_SSHORT
+define void @load_i16_sext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) {
+entry:
+  %0 = load i16 addrspace(1)* %in
+  %1 = sext i16 %0 to i32
+  store i32 %1, i32 addrspace(1)* %out
+  ret void
+}
+
 ; load an i32 value from the global address space.
 ; R600-CHECK: @load_i32
 ; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
@@ -40,6 +90,153 @@ entry:
   ret void
 }
 
+; load a v2f32 value from the global address space
+; R600-CHECK: @load_v2f32
+; R600-CHECK: VTX_READ_64
+
+; SI-CHECK: @load_v2f32
+; SI-CHECK: BUFFER_LOAD_DWORDX2
+define void @load_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) {
+entry:
+  %0 = load <2 x float> addrspace(1)* %in
+  store <2 x float> %0, <2 x float> addrspace(1)* %out
+  ret void
+}
+
+; R600-CHECK: @load_i64
+; R600-CHECK: RAT
+; R600-CHECK: RAT
+
+; SI-CHECK: @load_i64
+; SI-CHECK: BUFFER_LOAD_DWORDX2
+define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
+entry:
+  %0 = load i64 addrspace(1)* %in
+  store i64 %0, i64 addrspace(1)* %out
+  ret void
+}
+
+; R600-CHECK: @load_i64_sext
+; R600-CHECK: RAT
+; R600-CHECK: RAT
+; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}},  literal.x
+; R600-CHECK: 31
+; SI-CHECK: @load_i64_sext
+; SI-CHECK: BUFFER_LOAD_DWORDX2 [[VAL:VGPR[0-9]_VGPR[0-9]]]
+; SI-CHECK: V_LSHL_B64 [[LSHL:VGPR[0-9]_VGPR[0-9]]], [[VAL]], 32
+; SI-CHECK: V_ASHR_I64 VGPR{{[0-9]}}_VGPR{{[0-9]}}, [[LSHL]], 32
+
+define void @load_i64_sext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
+entry:
+  %0 = load i32 addrspace(1)* %in
+  %1 = sext i32 %0 to i64
+  store i64 %1, i64 addrspace(1)* %out
+  ret void
+}
+
+; R600-CHECK: @load_i64_zext
+; R600-CHECK: RAT
+; R600-CHECK: RAT
+define void @load_i64_zext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
+entry:
+  %0 = load i32 addrspace(1)* %in
+  %1 = zext i32 %0 to i64
+  store i64 %1, i64 addrspace(1)* %out
+  ret void
+}
+
+;===------------------------------------------------------------------------===;
+; CONSTANT ADDRESS SPACE
+;===------------------------------------------------------------------------===;
+
+; Load a sign-extended i8 value
+; R600-CHECK: @load_const_i8_sext
+; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
+; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
+; R600-CHECK: 24
+; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
+; R600-CHECK: 24
+; SI-CHECK: @load_const_i8_sext
+; SI-CHECK: BUFFER_LOAD_SBYTE VGPR{{[0-9]+}},
+define void @load_const_i8_sext(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
+entry:
+  %0 = load i8 addrspace(2)* %in
+  %1 = sext i8 %0 to i32
+  store i32 %1, i32 addrspace(1)* %out
+  ret void
+}
+
+; Load an aligned i8 value
+; R600-CHECK: @load_const_i8_aligned
+; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
+; SI-CHECK: @load_const_i8_aligned
+; SI-CHECK: BUFFER_LOAD_UBYTE VGPR{{[0-9]+}},
+define void @load_const_i8_aligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
+entry:
+  %0 = load i8 addrspace(2)* %in
+  %1 = zext i8 %0 to i32
+  store i32 %1, i32 addrspace(1)* %out
+  ret void
+}
+
+; Load an un-aligned i8 value
+; R600-CHECK: @load_const_i8_unaligned
+; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
+; SI-CHECK: @load_const_i8_unaligned
+; SI-CHECK: BUFFER_LOAD_UBYTE VGPR{{[0-9]+}},
+define void @load_const_i8_unaligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
+entry:
+  %0 = getelementptr i8 addrspace(2)* %in, i32 1
+  %1 = load i8 addrspace(2)* %0
+  %2 = zext i8 %1 to i32
+  store i32 %2, i32 addrspace(1)* %out
+  ret void
+}
+
+; Load a sign-extended i16 value
+; R600-CHECK: @load_const_i16_sext
+; R600-CHECK: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]]
+; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
+; R600-CHECK: 16
+; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
+; R600-CHECK: 16
+; SI-CHECK: @load_const_i16_sext
+; SI-CHECK: BUFFER_LOAD_SSHORT
+define void @load_const_i16_sext(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
+entry:
+  %0 = load i16 addrspace(2)* %in
+  %1 = sext i16 %0 to i32
+  store i32 %1, i32 addrspace(1)* %out
+  ret void
+}
+
+; Load an aligned i16 value
+; R600-CHECK: @load_const_i16_aligned
+; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
+; SI-CHECK: @load_const_i16_aligned
+; SI-CHECK: BUFFER_LOAD_USHORT
+define void @load_const_i16_aligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
+entry:
+  %0 = load i16 addrspace(2)* %in
+  %1 = zext i16 %0 to i32
+  store i32 %1, i32 addrspace(1)* %out
+  ret void
+}
+
+; Load an un-aligned i16 value
+; R600-CHECK: @load_const_i16_unaligned
+; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
+; SI-CHECK: @load_const_i16_unaligned
+; SI-CHECK: BUFFER_LOAD_USHORT
+define void @load_const_i16_unaligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
+entry:
+  %0 = getelementptr i16 addrspace(2)* %in, i32 1
+  %1 = load i16 addrspace(2)* %0
+  %2 = zext i16 %1 to i32
+  store i32 %2, i32 addrspace(1)* %out
+  ret void
+}
+
 ; Load an i32 value from the constant address space.
 ; R600-CHECK: @load_const_addrspace_i32
 ; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
@@ -64,3 +261,4 @@ define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(
   store float %1, float addrspace(1)* %out
   ret void
 }
+
diff --git a/test/CodeGen/R600/load.vec.ll b/test/CodeGen/R600/load.vec.ll
new file mode 100644
index 0000000..8cba0b6
--- /dev/null
+++ b/test/CodeGen/R600/load.vec.ll
@@ -0,0 +1,24 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK  %s
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK  %s
+
+; load a v2i32 value from the global address space.
+; EG-CHECK: @load_v2i32
+; EG-CHECK: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0
+; SI-CHECK: @load_v2i32
+; SI-CHECK: BUFFER_LOAD_DWORDX2 VGPR{{[0-9]+}}
+define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+  %a = load <2 x i32> addrspace(1) * %in
+  store <2 x i32> %a, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+; load a v4i32 value from the global address space.
+; EG-CHECK: @load_v4i32
+; EG-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0
+; SI-CHECK: @load_v4i32
+; SI-CHECK: BUFFER_LOAD_DWORDX4 VGPR{{[0-9]+}}
+define void @load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+  %a = load <4 x i32> addrspace(1) * %in
+  store <4 x i32> %a, <4 x i32> addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/load64.ll b/test/CodeGen/R600/load64.ll
new file mode 100644
index 0000000..3b4a8f8
--- /dev/null
+++ b/test/CodeGen/R600/load64.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s
+
+; load a f64 value from the global address space.
+; CHECK: @load_f64
+; CHECK: BUFFER_LOAD_DWORDX2 VGPR{{[0-9]+}}
+define void @load_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
+entry:
+  %0 = load double addrspace(1)* %in
+  store double %0, double addrspace(1)* %out
+  ret void
+}
+
+; Load a f64 value from the constant address space.
+; CHECK: @load_const_addrspace_f64
+; CHECK: S_LOAD_DWORDX2 SGPR{{[0-9]+}}
+define void @load_const_addrspace_f64(double addrspace(1)* %out, double addrspace(2)* %in) {
+  %1 = load double addrspace(2)* %in
+  store double %1, double addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/local-memory-two-objects.ll b/test/CodeGen/R600/local-memory-two-objects.ll
new file mode 100644
index 0000000..6d3610e
--- /dev/null
+++ b/test/CodeGen/R600/local-memory-two-objects.ll
@@ -0,0 +1,51 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+; TODO: Add RUN and CHECK lines for SI once this test works there
+
+@local_memory_two_objects.local_mem0 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4
+@local_memory_two_objects.local_mem1 = internal addrspace(3) unnamed_addr global [4 x i32] zeroinitializer, align 4
+
+; CHECK: @local_memory_two_objects
+
+; Check that the LDS size emitted correctly
+; CHECK: .long 166120
+; CHECK-NEXT: .long 8
+
+; Make sure the lds writes are using different addresses.
+; CHECK: LDS_WRITE {{[*]*}} {{PV|T}}[[ADDRW:[0-9]*\.[XYZW]]]
+; CHECK-NOT: LDS_WRITE {{[*]*}} T[[ADDRW]]
+
+; GROUP_BARRIER must be the last instruction in a clause
+; CHECK: GROUP_BARRIER
+; CHECK-NEXT: ALU clause
+
+; Make sure the lds reads are using different addresses.
+; CHECK: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
+; CHECK-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
+
+define void @local_memory_two_objects(i32 addrspace(1)* %out) {
+entry:
+  %x.i = call i32 @llvm.r600.read.tidig.x() #0
+  %arrayidx = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i
+  store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4
+  %mul = shl nsw i32 %x.i, 1
+  %arrayidx1 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i
+  store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4
+  %sub = sub nsw i32 3, %x.i
+  call void @llvm.AMDGPU.barrier.local()
+  %arrayidx2 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub
+  %0 = load i32 addrspace(3)* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds i32 addrspace(1)* %out, i32 %x.i
+  store i32 %0, i32 addrspace(1)* %arrayidx3, align 4
+  %arrayidx4 = getelementptr inbounds [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub
+  %1 = load i32 addrspace(3)* %arrayidx4, align 4
+  %add = add nsw i32 %x.i, 4
+  %arrayidx5 = getelementptr inbounds i32 addrspace(1)* %out, i32 %add
+  store i32 %1, i32 addrspace(1)* %arrayidx5, align 4
+  ret void
+}
+
+declare i32 @llvm.r600.read.tidig.x() #0
+declare void @llvm.AMDGPU.barrier.local()
+
+attributes #0 = { readnone }
diff --git a/test/CodeGen/R600/local-memory.ll b/test/CodeGen/R600/local-memory.ll
new file mode 100644
index 0000000..5458fb9
--- /dev/null
+++ b/test/CodeGen/R600/local-memory.ll
@@ -0,0 +1,45 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
+
+@local_memory.local_mem = internal addrspace(3) unnamed_addr global [16 x i32] zeroinitializer, align 4
+
+; EG-CHECK: @local_memory
+; SI-CHECK: @local_memory
+
+; Check that the LDS size emitted correctly
+; EG-CHECK: .long 166120
+; EG-CHECK-NEXT: .long 16
+; SI-CHECK: .long 47180
+; SI-CHECK-NEXT: .long 32768
+
+; EG-CHECK: LDS_WRITE
+; SI-CHECK: DS_WRITE_B32
+
+; GROUP_BARRIER must be the last instruction in a clause
+; EG-CHECK: GROUP_BARRIER
+; EG-CHECK-NEXT: ALU clause
+; SI-CHECK: S_BARRIER
+
+; EG-CHECK: LDS_READ_RET
+; SI-CHECK: DS_READ_B32
+
+define void @local_memory(i32 addrspace(1)* %out) {
+entry:
+  %y.i = call i32 @llvm.r600.read.tidig.x() #0
+  %arrayidx = getelementptr inbounds [16 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %y.i
+  store i32 %y.i, i32 addrspace(3)* %arrayidx, align 4
+  %add = add nsw i32 %y.i, 1
+  %cmp = icmp eq i32 %add, 16
+  %.add = select i1 %cmp, i32 0, i32 %add
+  call void @llvm.AMDGPU.barrier.local()
+  %arrayidx1 = getelementptr inbounds [16 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %.add
+  %0 = load i32 addrspace(3)* %arrayidx1, align 4
+  %arrayidx2 = getelementptr inbounds i32 addrspace(1)* %out, i32 %y.i
+  store i32 %0, i32 addrspace(1)* %arrayidx2, align 4
+  ret void
+}
+
+declare i32 @llvm.r600.read.tidig.x() #0
+declare void @llvm.AMDGPU.barrier.local()
+
+attributes #0 = { readnone }
diff --git a/test/CodeGen/R600/loop-address.ll b/test/CodeGen/R600/loop-address.ll
index 8a5458b..b46d8e9 100644
--- a/test/CodeGen/R600/loop-address.ll
+++ b/test/CodeGen/R600/loop-address.ll
@@ -1,13 +1,9 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-;CHECK: TEX
 ;CHECK: ALU_PUSH
-;CHECK: JUMP @4
-;CHECK: ELSE @16
-;CHECK: TEX
-;CHECK: LOOP_START_DX10 @15
-;CHECK: LOOP_BREAK @14
-;CHECK: POP @16
+;CHECK: LOOP_START_DX10 @11
+;CHECK: LOOP_BREAK @10
+;CHECK: POP @10
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64"
 target triple = "r600--"
diff --git a/test/CodeGen/R600/lshl.ll b/test/CodeGen/R600/lshl.ll
index 9e29b0d..806e681 100644
--- a/test/CodeGen/R600/lshl.ll
+++ b/test/CodeGen/R600/lshl.ll
@@ -1,6 +1,6 @@
 ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
 
-;CHECK: V_LSHL_B32_e64 VGPR{{[0-9]+}}, {{[SV]GPR[0-9]+}}, 1
+;CHECK: V_LSHL_B32_e64 VGPR{{[0-9]}}, SGPR{{[0-9]}}, 1
 
 define void @test(i32 %p) {
    %i = mul i32 %p, 2
diff --git a/test/CodeGen/R600/lshr.ll b/test/CodeGen/R600/lshr.ll
index eab3fbf..cfbcc34 100644
--- a/test/CodeGen/R600/lshr.ll
+++ b/test/CodeGen/R600/lshr.ll
@@ -1,6 +1,6 @@
 ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
 
-;CHECK: V_LSHR_B32_e64 {{VGPR[0-9]+}}, {{[SV]GPR[0-9]+}}, 1
+;CHECK: V_LSHR_B32_e64 {{VGPR[0-9]}}, SGPR{{[0-9]}}, 1
 
 define void @test(i32 %p) {
    %i = udiv i32 %p, 2
diff --git a/test/CodeGen/R600/mad_int24.ll b/test/CodeGen/R600/mad_int24.ll
new file mode 100644
index 0000000..ce42ae7
--- /dev/null
+++ b/test/CodeGen/R600/mad_int24.ll
@@ -0,0 +1,20 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
+; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
+
+; EG-CHECK: @i32_mad24
+; Signed 24-bit multiply is not supported on pre-Cayman GPUs.
+; EG-CHECK: MULLO_INT
+; CM-CHECK: MULADD_INT24 {{[ *]*}}T{{[0-9].[XYZW]}}, KC0[2].Z, KC0[2].W, KC0[3].X
+; SI-CHECK: V_MAD_I32_I24
+define void @i32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
+entry:
+  %0 = shl i32 %a, 8
+  %a_24 = ashr i32 %0, 8
+  %1 = shl i32 %b, 8
+  %b_24 = ashr i32 %1, 8
+  %2 = mul i32 %a_24, %b_24
+  %3 = add i32 %2, %c
+  store i32 %3, i32 addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/mad_uint24.ll b/test/CodeGen/R600/mad_uint24.ll
new file mode 100644
index 0000000..00aa64a
--- /dev/null
+++ b/test/CodeGen/R600/mad_uint24.ll
@@ -0,0 +1,70 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
+; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
+
+; EG-CHECK: @u32_mad24
+; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W, KC0[3].X
+; SI-CHECK: @u32_mad24
+; SI-CHECK: V_MAD_U32_U24
+
+define void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
+entry:
+  %0 = shl i32 %a, 8
+  %a_24 = lshr i32 %0, 8
+  %1 = shl i32 %b, 8
+  %b_24 = lshr i32 %1, 8
+  %2 = mul i32 %a_24, %b_24
+  %3 = add i32 %2, %c
+  store i32 %3, i32 addrspace(1)* %out
+  ret void
+}
+
+; EG-CHECK: @i16_mad24
+; EG-CHECK-DAG: VTX_READ_16 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40
+; EG-CHECK-DAG: VTX_READ_16 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44
+; EG-CHECK-DAG: VTX_READ_16 [[C:T[0-9]\.X]], T{{[0-9]}}.X, 48
+; The order of A and B does not matter.
+; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]], [[A]], [[B]], [[C]]
+; The result must be sign-extended
+; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MAD_CHAN]], literal.x
+; EG-CHECK: 16
+; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x
+; EG-CHECK: 16
+; SI-CHECK: @i16_mad24
+; SI-CHECK: V_MAD_U32_U24 [[MAD:VGPR[0-9]]], {{[SV]GPR[0-9], [SV]GPR[0-9]}}
+; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:VGPR[0-9]]], 16, [[MAD]]
+; SI-CHECK: V_ASHRREV_I32_e32 VGPR{{[0-9]}}, 16, [[LSHL]]
+
+define void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) {
+entry:
+  %0 = mul i16 %a, %b
+  %1 = add i16 %0, %c
+  %2 = sext i16 %1 to i32
+  store i32 %2, i32 addrspace(1)* %out
+  ret void
+}
+
+; EG-CHECK: @i8_mad24
+; EG-CHECK-DAG: VTX_READ_8 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40
+; EG-CHECK-DAG: VTX_READ_8 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44
+; EG-CHECK-DAG: VTX_READ_8 [[C:T[0-9]\.X]], T{{[0-9]}}.X, 48
+; The order of A and B does not matter.
+; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]], [[A]], [[B]], [[C]]
+; The result must be sign-extended
+; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MAD_CHAN]], literal.x
+; EG-CHECK: 24
+; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x
+; EG-CHECK: 24
+; SI-CHECK: @i8_mad24
+; SI-CHECK: V_MAD_U32_U24 [[MUL:VGPR[0-9]]], {{[SV]GPR[0-9], [SV]GPR[0-9]}}
+; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:VGPR[0-9]]], 24, [[MUL]]
+; SI-CHECK: V_ASHRREV_I32_e32 VGPR{{[0-9]}}, 24, [[LSHL]]
+
+define void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) {
+entry:
+  %0 = mul i8 %a, %b
+  %1 = add i8 %0, %c
+  %2 = sext i8 %1 to i32
+  store i32 %2, i32 addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/max-literals.ll b/test/CodeGen/R600/max-literals.ll
new file mode 100644
index 0000000..c31b7c0
--- /dev/null
+++ b/test/CodeGen/R600/max-literals.ll
@@ -0,0 +1,68 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+; CHECK: @main
+; CHECK: ADD *
+
+define void @main() #0 {
+main_body:
+  %0 = call float @llvm.R600.load.input(i32 4)
+  %1 = call float @llvm.R600.load.input(i32 5)
+  %2 = call float @llvm.R600.load.input(i32 6)
+  %3 = call float @llvm.R600.load.input(i32 7)
+  %4 = call float @llvm.R600.load.input(i32 8)
+  %5 = fadd float %0, 2.0
+  %6 = fadd float %1, 3.0
+  %7 = fadd float %2, 4.0
+  %8 = fadd float %3, 5.0
+  %9 = bitcast float %4 to i32
+  %10 = mul i32 %9, 6
+  %11 = bitcast i32 %10 to float
+  %12 = insertelement <4 x float> undef, float %5, i32 0
+  %13 = insertelement <4 x float> %12, float %6, i32 1
+  %14 = insertelement <4 x float> %13, float %7, i32 2
+  %15 = insertelement <4 x float> %14, float %8, i32 3
+  %16 = insertelement <4 x float> %15, float %11, i32 3
+
+  %17 = call float @llvm.AMDGPU.dp4(<4 x float> %15,<4 x float> %16)
+  %18 = insertelement <4 x float> undef, float %17, i32 0
+  call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2)
+  ret void
+}
+
+; CHECK: @main
+; CHECK-NOT: ADD *
+
+define void @main2() #0 {
+main_body:
+  %0 = call float @llvm.R600.load.input(i32 4)
+  %1 = call float @llvm.R600.load.input(i32 5)
+  %2 = call float @llvm.R600.load.input(i32 6)
+  %3 = call float @llvm.R600.load.input(i32 7)
+  %4 = call float @llvm.R600.load.input(i32 8)
+  %5 = fadd float %0, 2.0
+  %6 = fadd float %1, 3.0
+  %7 = fadd float %2, 4.0
+  %8 = fadd float %3, 2.0
+  %9 = bitcast float %4 to i32
+  %10 = mul i32 %9, 6
+  %11 = bitcast i32 %10 to float
+  %12 = insertelement <4 x float> undef, float %5, i32 0
+  %13 = insertelement <4 x float> %12, float %6, i32 1
+  %14 = insertelement <4 x float> %13, float %7, i32 2
+  %15 = insertelement <4 x float> %14, float %8, i32 3
+  %16 = insertelement <4 x float> %15, float %11, i32 3
+
+  %17 = call float @llvm.AMDGPU.dp4(<4 x float> %15,<4 x float> %16)
+  %18 = insertelement <4 x float> undef, float %17, i32 0
+  call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2)
+  ret void
+}
+
+; Function Attrs: readnone
+declare float @llvm.R600.load.input(i32) #1
+declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
+
+declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
+
+attributes #0 = { "ShaderType"="1" }
+attributes #1 = { readnone }
diff --git a/test/CodeGen/R600/mul.ll b/test/CodeGen/R600/mul.ll
index 7278e90..18a17b6 100644
--- a/test/CodeGen/R600/mul.ll
+++ b/test/CodeGen/R600/mul.ll
@@ -1,12 +1,38 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
 
 ; mul24 and mad24 are affected
-;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+;EG-CHECK: @test2
+;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @test2
+;SI-CHECK: V_MUL_LO_I32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_MUL_LO_I32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %result = mul <2 x i32> %a, %b
+  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+;EG-CHECK: @test4
+;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: MULLO_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @test4
+;SI-CHECK: V_MUL_LO_I32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_MUL_LO_I32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_MUL_LO_I32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_MUL_LO_I32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
   %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
   %a = load <4 x i32> addrspace(1) * %in
   %b = load <4 x i32> addrspace(1) * %b_ptr
diff --git a/test/CodeGen/R600/mul_int24.ll b/test/CodeGen/R600/mul_int24.ll
new file mode 100644
index 0000000..16ae760
--- /dev/null
+++ b/test/CodeGen/R600/mul_int24.ll
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
+; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
+
+; EG-CHECK: @i32_mul24
+; Signed 24-bit multiply is not supported on pre-Cayman GPUs.
+; EG-CHECK: MULLO_INT
+; CM-CHECK: MUL_INT24 {{[ *]*}}T{{[0-9].[XYZW]}}, KC0[2].Z, KC0[2].W
+; SI-CHECK: V_MUL_I32_I24
+define void @i32_mul24(i32 addrspace(1)* %out, i32 %a, i32 %b) {
+entry:
+  %0 = shl i32 %a, 8
+  %a_24 = ashr i32 %0, 8
+  %1 = shl i32 %b, 8
+  %b_24 = ashr i32 %1, 8
+  %2 = mul i32 %a_24, %b_24
+  store i32 %2, i32 addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/mul_uint24.ll b/test/CodeGen/R600/mul_uint24.ll
new file mode 100644
index 0000000..b1a7f94
--- /dev/null
+++ b/test/CodeGen/R600/mul_uint24.ll
@@ -0,0 +1,65 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
+; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
+
+; EG-CHECK: @u32_mul24
+; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W
+; SI-CHECK: @u32_mul24
+; SI-CHECK: V_MUL_U32_U24
+
+define void @u32_mul24(i32 addrspace(1)* %out, i32 %a, i32 %b) {
+entry:
+  %0 = shl i32 %a, 8
+  %a_24 = lshr i32 %0, 8
+  %1 = shl i32 %b, 8
+  %b_24 = lshr i32 %1, 8
+  %2 = mul i32 %a_24, %b_24
+  store i32 %2, i32 addrspace(1)* %out
+  ret void
+}
+
+; EG-CHECK: @i16_mul24
+; EG-CHECK-DAG: VTX_READ_16 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40
+; EG-CHECK-DAG: VTX_READ_16 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44
+; The order of A and B does not matter.
+; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]}}.[[MUL_CHAN:[XYZW]]], [[A]], [[B]]
+; The result must be sign-extended
+; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MUL_CHAN]], literal.x
+; EG-CHECK: 16
+; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x
+; EG-CHECK: 16
+; SI-CHECK: @i16_mul24
+; SI-CHECK: V_MUL_U32_U24_e{{(32|64)}} [[MUL:VGPR[0-9]]], {{[SV]GPR[0-9], [SV]GPR[0-9]}}
+; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:VGPR[0-9]]], 16, [[MUL]]
+; SI-CHECK: V_ASHRREV_I32_e32 VGPR{{[0-9]}}, 16, [[LSHL]]
+
+define void @i16_mul24(i32 addrspace(1)* %out, i16 %a, i16 %b) {
+entry:
+  %0 = mul i16 %a, %b
+  %1 = sext i16 %0 to i32
+  store i32 %1, i32 addrspace(1)* %out
+  ret void
+}
+
+; EG-CHECK: @i8_mul24
+; EG-CHECK-DAG: VTX_READ_8 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40
+; EG-CHECK-DAG: VTX_READ_8 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44
+; The order of A and B does not matter.
+; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]}}.[[MUL_CHAN:[XYZW]]], [[A]], [[B]]
+; The result must be sign-extended
+; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MUL_CHAN]], literal.x
+; EG-CHECK: 24
+; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x
+; EG-CHECK: 24
+; SI-CHECK: @i8_mul24
+; SI-CHECK: V_MUL_U32_U24_e{{(32|64)}} [[MUL:VGPR[0-9]]], {{[SV]GPR[0-9], [SV]GPR[0-9]}}
+; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:VGPR[0-9]]], 24, [[MUL]]
+; SI-CHECK: V_ASHRREV_I32_e32 VGPR{{[0-9]}}, 24, [[LSHL]]
+
+define void @i8_mul24(i32 addrspace(1)* %out, i8 %a, i8 %b) {
+entry:
+  %0 = mul i8 %a, %b
+  %1 = sext i8 %0 to i32
+  store i32 %1, i32 addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/or.ll b/test/CodeGen/R600/or.ll
index b0dbb02..4a4e892 100644
--- a/test/CodeGen/R600/or.ll
+++ b/test/CodeGen/R600/or.ll
@@ -1,12 +1,39 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
 
-; CHECK: @or_v4i32
-; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; EG-CHECK: @or_v2i32
+; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
-define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) {
+;SI-CHECK: @or_v2i32
+;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %result = or <2 x i32> %a, %b
+  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+; EG-CHECK: @or_v4i32
+; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; EG-CHECK: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @or_v4i32
+;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_OR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
+  %a = load <4 x i32> addrspace(1) * %in
+  %b = load <4 x i32> addrspace(1) * %b_ptr
   %result = or <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/packetizer.ll b/test/CodeGen/R600/packetizer.ll
new file mode 100644
index 0000000..0a405c5
--- /dev/null
+++ b/test/CodeGen/R600/packetizer.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s
+
+; CHECK: @test
+; CHECK: BIT_ALIGN_INT T{{[0-9]}}.X
+; CHECK: BIT_ALIGN_INT T{{[0-9]}}.Y
+; CHECK: BIT_ALIGN_INT T{{[0-9]}}.Z
+; CHECK: BIT_ALIGN_INT * T{{[0-9]}}.W
+
+define void @test(i32 addrspace(1)* %out, i32 %x_arg, i32 %y_arg, i32 %z_arg, i32 %w_arg, i32 %e) {
+entry:
+  %shl = sub i32 32, %e
+  %x = add i32 %x_arg, 1
+  %x.0 = shl i32 %x, %shl
+  %x.1 = lshr i32 %x, %e
+  %x.2 = or i32 %x.0, %x.1
+  %y = add i32 %y_arg, 1
+  %y.0 = shl i32 %y, %shl
+  %y.1 = lshr i32 %y, %e
+  %y.2 = or i32 %y.0, %y.1
+  %z = add i32 %z_arg, 1
+  %z.0 = shl i32 %z, %shl
+  %z.1 = lshr i32 %z, %e
+  %z.2 = or i32 %z.0, %z.1
+  %w = add i32 %w_arg, 1
+  %w.0 = shl i32 %w, %shl
+  %w.1 = lshr i32 %w, %e
+  %w.2 = or i32 %w.0, %w.1
+  %xy = or i32 %x.2, %y.2
+  %zw = or i32 %z.2, %w.2
+  %xyzw = or i32 %xy, %zw
+  store i32 %xyzw, i32 addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/parallelandifcollapse.ll b/test/CodeGen/R600/parallelandifcollapse.ll
new file mode 100644
index 0000000..4afaf68
--- /dev/null
+++ b/test/CodeGen/R600/parallelandifcollapse.ll
@@ -0,0 +1,54 @@
+; Function Attrs: nounwind
+; RUN: llc < %s -march=r600 -mcpu=redwood  | FileCheck %s
+;
+; CFG flattening should use parallel-and mode to generate branch conditions and
+; then merge if-regions with the same bodies.
+;
+; CHECK: AND_INT
+; CHECK-NEXT: AND_INT
+; CHECK-NEXT: OR_INT
+define void @_Z9chk1D_512v() #0 {
+entry:
+  %a0 = alloca i32, align 4
+  %b0 = alloca i32, align 4
+  %c0 = alloca i32, align 4
+  %d0 = alloca i32, align 4
+  %a1 = alloca i32, align 4
+  %b1 = alloca i32, align 4
+  %c1 = alloca i32, align 4
+  %d1 = alloca i32, align 4
+  %data = alloca i32, align 4
+  %0 = load i32* %a0, align 4
+  %1 = load i32* %b0, align 4
+  %cmp = icmp ne i32 %0, %1
+  br i1 %cmp, label %land.lhs.true, label %if.end
+
+land.lhs.true:                                    ; preds = %entry
+  %2 = load i32* %c0, align 4
+  %3 = load i32* %d0, align 4
+  %cmp1 = icmp ne i32 %2, %3
+  br i1 %cmp1, label %if.then, label %if.end
+
+if.then:                                          ; preds = %land.lhs.true
+  store i32 1, i32* %data, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %land.lhs.true, %entry
+  %4 = load i32* %a1, align 4
+  %5 = load i32* %b1, align 4
+  %cmp2 = icmp ne i32 %4, %5
+  br i1 %cmp2, label %land.lhs.true3, label %if.end6
+
+land.lhs.true3:                                   ; preds = %if.end
+  %6 = load i32* %c1, align 4
+  %7 = load i32* %d1, align 4
+  %cmp4 = icmp ne i32 %6, %7
+  br i1 %cmp4, label %if.then5, label %if.end6
+
+if.then5:                                         ; preds = %land.lhs.true3
+  store i32 1, i32* %data, align 4
+  br label %if.end6
+
+if.end6:                                          ; preds = %if.then5, %land.lhs.true3, %if.end
+  ret void
+}
diff --git a/test/CodeGen/R600/parallelorifcollapse.ll b/test/CodeGen/R600/parallelorifcollapse.ll
new file mode 100644
index 0000000..b0db7cd
--- /dev/null
+++ b/test/CodeGen/R600/parallelorifcollapse.ll
@@ -0,0 +1,61 @@
+; Function Attrs: nounwind
+; RUN: llc < %s -march=r600 -mcpu=redwood  | FileCheck %s
+;
+; CFG flattening should use parallel-or to generate branch conditions and
+; then merge if-regions with the same bodies.
+;
+; CHECK: OR_INT
+; CHECK-NEXT: OR_INT
+; CHECK-NEXT: OR_INT
+define void @_Z9chk1D_512v() #0 {
+entry:
+  %a0 = alloca i32, align 4
+  %b0 = alloca i32, align 4
+  %c0 = alloca i32, align 4
+  %d0 = alloca i32, align 4
+  %a1 = alloca i32, align 4
+  %b1 = alloca i32, align 4
+  %c1 = alloca i32, align 4
+  %d1 = alloca i32, align 4
+  %data = alloca i32, align 4
+  %0 = load i32* %a0, align 4
+  %1 = load i32* %b0, align 4
+  %cmp = icmp ne i32 %0, %1
+  br i1 %cmp, label %land.lhs.true, label %if.else
+
+land.lhs.true:                                    ; preds = %entry
+  %2 = load i32* %c0, align 4
+  %3 = load i32* %d0, align 4
+  %cmp1 = icmp ne i32 %2, %3
+  br i1 %cmp1, label %if.then, label %if.else
+
+if.then:                                          ; preds = %land.lhs.true
+  br label %if.end
+
+if.else:                                          ; preds = %land.lhs.true, %entry
+  store i32 1, i32* %data, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  %4 = load i32* %a1, align 4
+  %5 = load i32* %b1, align 4
+  %cmp2 = icmp ne i32 %4, %5
+  br i1 %cmp2, label %land.lhs.true3, label %if.else6
+
+land.lhs.true3:                                   ; preds = %if.end
+  %6 = load i32* %c1, align 4
+  %7 = load i32* %d1, align 4
+  %cmp4 = icmp ne i32 %6, %7
+  br i1 %cmp4, label %if.then5, label %if.else6
+
+if.then5:                                         ; preds = %land.lhs.true3
+  br label %if.end7
+
+if.else6:                                         ; preds = %land.lhs.true3, %if.end
+  store i32 1, i32* %data, align 4
+  br label %if.end7
+
+if.end7:                                          ; preds = %if.else6, %if.then5
+  ret void
+}
+
diff --git a/test/CodeGen/R600/pv-packing.ll b/test/CodeGen/R600/pv-packing.ll
new file mode 100644
index 0000000..03fc204
--- /dev/null
+++ b/test/CodeGen/R600/pv-packing.ll
@@ -0,0 +1,50 @@
+; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s
+
+;CHECK: DOT4  T{{[0-9]\.X}}
+;CHECK: MULADD_IEEE * T{{[0-9]\.W}}
+
+define void @main() #0 {
+main_body:
+  %0 = call float @llvm.R600.load.input(i32 4)
+  %1 = call float @llvm.R600.load.input(i32 5)
+  %2 = call float @llvm.R600.load.input(i32 6)
+  %3 = call float @llvm.R600.load.input(i32 8)
+  %4 = call float @llvm.R600.load.input(i32 9)
+  %5 = call float @llvm.R600.load.input(i32 10)
+  %6 = call float @llvm.R600.load.input(i32 12)
+  %7 = call float @llvm.R600.load.input(i32 13)
+  %8 = call float @llvm.R600.load.input(i32 14)
+  %9 = load <4 x float> addrspace(8)* null
+  %10 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %11 = call float @llvm.AMDGPU.dp4(<4 x float> %9, <4 x float> %9)
+  %12 = fmul float %0, %3
+  %13 = fadd float %12, %6
+  %14 = fmul float %1, %4
+  %15 = fadd float %14, %7
+  %16 = fmul float %2, %5
+  %17 = fadd float %16, %8
+  %18 = fmul float %11, %11
+  %19 = fadd float %18, %0
+  %20 = insertelement <4 x float> undef, float %13, i32 0
+  %21 = insertelement <4 x float> %20, float %15, i32 1
+  %22 = insertelement <4 x float> %21, float %17, i32 2
+  %23 = insertelement <4 x float> %22, float %19, i32 3
+  %24 = call float @llvm.AMDGPU.dp4(<4 x float> %23, <4 x float> %10)
+  %25 = insertelement <4 x float> undef, float %24, i32 0
+  call void @llvm.R600.store.swizzle(<4 x float> %25, i32 0, i32 2)
+  ret void
+}
+
+; Function Attrs: readnone
+declare float @llvm.R600.load.input(i32) #1
+
+; Function Attrs: readnone
+declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
+
+
+declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
+
+attributes #0 = { "ShaderType"="1" }
+attributes #1 = { readnone }
+attributes #2 = { readonly }
+attributes #3 = { nounwind readonly }
diff --git a/test/CodeGen/R600/r600cfg.ll b/test/CodeGen/R600/r600cfg.ll
new file mode 100644
index 0000000..895ad5e
--- /dev/null
+++ b/test/CodeGen/R600/r600cfg.ll
@@ -0,0 +1,124 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood
+;REQUIRES: asserts
+
+define void @main() #0 {
+main_body:
+  %0 = call float @llvm.R600.load.input(i32 4)
+  %1 = call float @llvm.R600.load.input(i32 5)
+  %2 = call float @llvm.R600.load.input(i32 6)
+  %3 = call float @llvm.R600.load.input(i32 7)
+  %4 = bitcast float %0 to i32
+  %5 = icmp eq i32 %4, 0
+  %6 = sext i1 %5 to i32
+  %7 = bitcast i32 %6 to float
+  %8 = bitcast float %7 to i32
+  %9 = icmp ne i32 %8, 0
+  %. = select i1 %9, float 0x36A0000000000000, float %0
+  br label %LOOP
+
+LOOP:                                             ; preds = %LOOP47, %main_body
+  %temp12.0 = phi float [ 0x36A0000000000000, %main_body ], [ %temp12.1, %LOOP47 ]
+  %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %38, %LOOP47 ]
+  %temp4.1 = phi float [ %., %main_body ], [ %52, %LOOP47 ]
+  %10 = bitcast float %temp4.1 to i32
+  %11 = icmp eq i32 %10, 1
+  %12 = sext i1 %11 to i32
+  %13 = bitcast i32 %12 to float
+  %14 = bitcast float %13 to i32
+  %15 = icmp ne i32 %14, 0
+  br i1 %15, label %IF41, label %ENDIF40
+
+IF41:                                             ; preds = %LOOP
+  %16 = insertelement <4 x float> undef, float %0, i32 0
+  %17 = insertelement <4 x float> %16, float %temp8.0, i32 1
+  %18 = insertelement <4 x float> %17, float %temp12.0, i32 2
+  %19 = insertelement <4 x float> %18, float 0.000000e+00, i32 3
+  call void @llvm.R600.store.stream.output(<4 x float> %19, i32 0, i32 0, i32 1)
+  %20 = insertelement <4 x float> undef, float %0, i32 0
+  %21 = insertelement <4 x float> %20, float %temp8.0, i32 1
+  %22 = insertelement <4 x float> %21, float %temp12.0, i32 2
+  %23 = insertelement <4 x float> %22, float 0.000000e+00, i32 3
+  call void @llvm.R600.store.stream.output(<4 x float> %23, i32 0, i32 0, i32 2)
+  %24 = insertelement <4 x float> undef, float %0, i32 0
+  %25 = insertelement <4 x float> %24, float %temp8.0, i32 1
+  %26 = insertelement <4 x float> %25, float %temp12.0, i32 2
+  %27 = insertelement <4 x float> %26, float 0.000000e+00, i32 3
+  call void @llvm.R600.store.stream.output(<4 x float> %27, i32 0, i32 0, i32 4)
+  %28 = insertelement <4 x float> undef, float 0.000000e+00, i32 0
+  %29 = insertelement <4 x float> %28, float 0.000000e+00, i32 1
+  %30 = insertelement <4 x float> %29, float 0.000000e+00, i32 2
+  %31 = insertelement <4 x float> %30, float 0.000000e+00, i32 3
+  call void @llvm.R600.store.swizzle(<4 x float> %31, i32 60, i32 1)
+  %32 = insertelement <4 x float> undef, float %0, i32 0
+  %33 = insertelement <4 x float> %32, float %temp8.0, i32 1
+  %34 = insertelement <4 x float> %33, float %temp12.0, i32 2
+  %35 = insertelement <4 x float> %34, float 0.000000e+00, i32 3
+  call void @llvm.R600.store.swizzle(<4 x float> %35, i32 0, i32 2)
+  ret void
+
+ENDIF40:                                          ; preds = %LOOP
+  %36 = bitcast float %temp8.0 to i32
+  %37 = add i32 %36, 1
+  %38 = bitcast i32 %37 to float
+  %39 = bitcast float %temp4.1 to i32
+  %40 = urem i32 %39, 2
+  %41 = bitcast i32 %40 to float
+  %42 = bitcast float %41 to i32
+  %43 = icmp eq i32 %42, 0
+  %44 = sext i1 %43 to i32
+  %45 = bitcast i32 %44 to float
+  %46 = bitcast float %45 to i32
+  %47 = icmp ne i32 %46, 0
+  %48 = bitcast float %temp4.1 to i32
+  br i1 %47, label %IF44, label %ELSE45
+
+IF44:                                             ; preds = %ENDIF40
+  %49 = udiv i32 %48, 2
+  br label %ENDIF43
+
+ELSE45:                                           ; preds = %ENDIF40
+  %50 = mul i32 3, %48
+  %51 = add i32 %50, 1
+  br label %ENDIF43
+
+ENDIF43:                                          ; preds = %ELSE45, %IF44
+  %.sink = phi i32 [ %49, %IF44 ], [ %51, %ELSE45 ]
+  %52 = bitcast i32 %.sink to float
+  %53 = load <4 x float> addrspace(8)* null
+  %54 = extractelement <4 x float> %53, i32 0
+  %55 = bitcast float %54 to i32
+  br label %LOOP47
+
+LOOP47:                                           ; preds = %ENDIF48, %ENDIF43
+  %temp12.1 = phi float [ %temp12.0, %ENDIF43 ], [ %67, %ENDIF48 ]
+  %temp28.0 = phi float [ 0.000000e+00, %ENDIF43 ], [ %70, %ENDIF48 ]
+  %56 = bitcast float %temp28.0 to i32
+  %57 = icmp uge i32 %56, %55
+  %58 = sext i1 %57 to i32
+  %59 = bitcast i32 %58 to float
+  %60 = bitcast float %59 to i32
+  %61 = icmp ne i32 %60, 0
+  br i1 %61, label %LOOP, label %ENDIF48
+
+ENDIF48:                                          ; preds = %LOOP47
+  %62 = bitcast float %temp12.1 to i32
+  %63 = mul i32 %62, 2
+  %64 = bitcast i32 %63 to float
+  %65 = bitcast float %64 to i32
+  %66 = urem i32 %65, 2147483647
+  %67 = bitcast i32 %66 to float
+  %68 = bitcast float %temp28.0 to i32
+  %69 = add i32 %68, 1
+  %70 = bitcast i32 %69 to float
+  br label %LOOP47
+}
+
+; Function Attrs: readnone
+declare float @llvm.R600.load.input(i32) #1
+
+declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32)
+
+declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
+
+attributes #0 = { "ShaderType"="1" }
+attributes #1 = { readnone }
diff --git a/test/CodeGen/R600/rotr.ll b/test/CodeGen/R600/rotr.ll
index 960d30d..5c4c4e9 100644
--- a/test/CodeGen/R600/rotr.ll
+++ b/test/CodeGen/R600/rotr.ll
@@ -19,7 +19,7 @@ entry:
 ; R600-CHECK: @rotl
 ; R600-CHECK: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x
 ; R600-CHECK-NEXT: 32
-; R600-CHECK: BIT_ALIGN_INT {{\** T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PV.[XYZW]}}
+; R600-CHECK: BIT_ALIGN_INT {{\** T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}}
 
 ; SI-CHECK: @rotl
 ; SI-CHECK: V_SUB_I32_e64 [[DST:VGPR[0-9]+]], 32, {{[SV]GPR[0-9]+}}
diff --git a/test/CodeGen/R600/rv7x0_count3.ll b/test/CodeGen/R600/rv7x0_count3.ll
new file mode 100644
index 0000000..474d6ba
--- /dev/null
+++ b/test/CodeGen/R600/rv7x0_count3.ll
@@ -0,0 +1,44 @@
+; RUN: llc < %s -march=r600 -show-mc-encoding  -mcpu=rv710 | FileCheck %s
+
+; CHECK: TEX 9 @4 ;  encoding: [0x04,0x00,0x00,0x00,0x00,0x04,0x88,0x80]
+
+define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) {
+   %1 = call float @llvm.R600.load.input(i32 4)
+   %2 = call float @llvm.R600.load.input(i32 5)
+   %3 = call float @llvm.R600.load.input(i32 6)
+   %4 = call float @llvm.R600.load.input(i32 7)
+   %5 = insertelement <4 x float> undef, float %1, i32 0
+   %6 = insertelement <4 x float> %5, float %2, i32 1
+   %7 = insertelement <4 x float> %6, float %3, i32 2
+   %8 = insertelement <4 x float> %7, float %4, i32 3
+   %9 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1)
+   %10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 1, i32 0, i32 1)
+   %11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 2, i32 0, i32 1)
+   %12 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 3, i32 0, i32 1)
+   %13 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 4, i32 0, i32 1)
+   %14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 5, i32 0, i32 1)
+   %15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 6, i32 0, i32 1)
+   %16 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 7, i32 0, i32 1)
+   %17 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 8, i32 0, i32 1)
+   %18 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 9, i32 0, i32 1)
+   %19 = fadd <4 x float> %9, %10
+   %20 = fadd <4 x float> %19, %11
+   %21 = fadd <4 x float> %20, %12
+   %22 = fadd <4 x float> %21, %13
+   %23 = fadd <4 x float> %22, %14
+   %24 = fadd <4 x float> %23, %15
+   %25 = fadd <4 x float> %24, %16
+   %26 = fadd <4 x float> %25, %17
+   %27 = fadd <4 x float> %26, %18
+   call void @llvm.R600.store.swizzle(<4 x float> %27, i32 0, i32 2)
+   ret void
+}
+
+declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone
+
+; Function Attrs: readnone
+declare float @llvm.R600.load.input(i32) #1
+
+
+declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
+attributes #1 = { readnone }
diff --git a/test/CodeGen/R600/selectcc-opt.ll b/test/CodeGen/R600/selectcc-opt.ll
index 7f568fc..7e2d559 100644
--- a/test/CodeGen/R600/selectcc-opt.ll
+++ b/test/CodeGen/R600/selectcc-opt.ll
@@ -29,7 +29,6 @@ ENDIF:
 ; for the icmp instruction
 
 ; CHECK: @test_b
-; CHECK: VTX_READ
 ; CHECK: SET{{[GTEQN]+}}_DX10
 ; CHECK-NEXT: PRED_
 ; CHECK-NEXT: ALU clause starting
diff --git a/test/CodeGen/R600/set-dx10.ll b/test/CodeGen/R600/set-dx10.ll
index eb6e9d2..291a7bd 100644
--- a/test/CodeGen/R600/set-dx10.ll
+++ b/test/CodeGen/R600/set-dx10.ll
@@ -5,7 +5,7 @@
 ; SET*DX10 instructions.
 
 ; CHECK: @fcmp_une_select_fptosi
-; CHECK: SETNE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
+; CHECK: SETNE_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
 ; CHECK-NEXT: 1084227584(5.000000e+00)
 define void @fcmp_une_select_fptosi(i32 addrspace(1)* %out, float %in) {
 entry:
@@ -18,7 +18,7 @@ entry:
 }
 
 ; CHECK: @fcmp_une_select_i32
-; CHECK: SETNE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
+; CHECK: SETNE_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
 ; CHECK-NEXT: 1084227584(5.000000e+00)
 define void @fcmp_une_select_i32(i32 addrspace(1)* %out, float %in) {
 entry:
@@ -29,7 +29,7 @@ entry:
 }
 
 ; CHECK: @fcmp_ueq_select_fptosi
-; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
+; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
 ; CHECK-NEXT: 1084227584(5.000000e+00)
 define void @fcmp_ueq_select_fptosi(i32 addrspace(1)* %out, float %in) {
 entry:
@@ -42,7 +42,7 @@ entry:
 }
 
 ; CHECK: @fcmp_ueq_select_i32
-; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
+; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
 ; CHECK-NEXT: 1084227584(5.000000e+00)
 define void @fcmp_ueq_select_i32(i32 addrspace(1)* %out, float %in) {
 entry:
@@ -53,7 +53,7 @@ entry:
 }
 
 ; CHECK: @fcmp_ugt_select_fptosi
-; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
+; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
 ; CHECK-NEXT: 1084227584(5.000000e+00)
 define void @fcmp_ugt_select_fptosi(i32 addrspace(1)* %out, float %in) {
 entry:
@@ -66,7 +66,7 @@ entry:
 }
 
 ; CHECK: @fcmp_ugt_select_i32
-; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
+; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
 ; CHECK-NEXT: 1084227584(5.000000e+00)
 define void @fcmp_ugt_select_i32(i32 addrspace(1)* %out, float %in) {
 entry:
@@ -77,7 +77,7 @@ entry:
 }
 
 ; CHECK: @fcmp_uge_select_fptosi
-; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
+; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
 ; CHECK-NEXT: 1084227584(5.000000e+00)
 define void @fcmp_uge_select_fptosi(i32 addrspace(1)* %out, float %in) {
 entry:
@@ -90,7 +90,7 @@ entry:
 }
 
 ; CHECK: @fcmp_uge_select_i32
-; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x,
+; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
 ; CHECK-NEXT: 1084227584(5.000000e+00)
 define void @fcmp_uge_select_i32(i32 addrspace(1)* %out, float %in) {
 entry:
@@ -101,7 +101,7 @@ entry:
 }
 
 ; CHECK: @fcmp_ule_select_fptosi
-; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}},
+; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
 ; CHECK-NEXT: 1084227584(5.000000e+00)
 define void @fcmp_ule_select_fptosi(i32 addrspace(1)* %out, float %in) {
 entry:
@@ -114,7 +114,7 @@ entry:
 }
 
 ; CHECK: @fcmp_ule_select_i32
-; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}},
+; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
 ; CHECK-NEXT: 1084227584(5.000000e+00)
 define void @fcmp_ule_select_i32(i32 addrspace(1)* %out, float %in) {
 entry:
@@ -125,7 +125,7 @@ entry:
 }
 
 ; CHECK: @fcmp_ult_select_fptosi
-; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}},
+; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
 ; CHECK-NEXT: 1084227584(5.000000e+00)
 define void @fcmp_ult_select_fptosi(i32 addrspace(1)* %out, float %in) {
 entry:
@@ -138,7 +138,7 @@ entry:
 }
 
 ; CHECK: @fcmp_ult_select_i32
-; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}},
+; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
 ; CHECK-NEXT: 1084227584(5.000000e+00)
 define void @fcmp_ult_select_i32(i32 addrspace(1)* %out, float %in) {
 entry:
diff --git a/test/CodeGen/R600/setcc.ll b/test/CodeGen/R600/setcc.ll
index 0752f2e..992de70 100644
--- a/test/CodeGen/R600/setcc.ll
+++ b/test/CodeGen/R600/setcc.ll
@@ -1,7 +1,23 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-;CHECK: SETE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
 
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+; CHECK: @setcc_v2i32
+; EG-CHECK-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[3].X, KC0[3].Z
+; EG-CHECK-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[2].W, KC0[3].Y
+
+define void @setcc_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) {
+  %result = icmp eq <2 x i32> %a, %b
+  %sext = sext <2 x i1> %result to <2 x i32>
+  store <2 x i32> %sext, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+; CHECK: @setcc_v4i32
+; EG-CHECK-DAG: SETE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; EG-CHECK-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; EG-CHECK-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; EG-CHECK-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+define void @setcc_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
   %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
   %a = load <4 x i32> addrspace(1) * %in
   %b = load <4 x i32> addrspace(1) * %b_ptr
diff --git a/test/CodeGen/R600/sgpr-copy.ll b/test/CodeGen/R600/sgpr-copy.ll
new file mode 100644
index 0000000..b0d4549
--- /dev/null
+++ b/test/CodeGen/R600/sgpr-copy.ll
@@ -0,0 +1,84 @@
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
+
+; This test checks that no VGPR to SGPR copies are created by the register
+; allocator.
+; CHECK: @main
+; CHECK: S_BUFFER_LOAD_DWORD [[DST:SGPR[0-9]]], {{[SGPR_[0-9]+}}, 0
+; CHECK: V_MOV_B32_e32 VGPR{{[0-9]}}, [[DST]]
+
+define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
+main_body:
+  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
+  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
+  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
+  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
+  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
+  %25 = fptosi float %23 to i32
+  %26 = icmp ne i32 %25, 0
+  br i1 %26, label %ENDIF, label %ELSE
+
+ELSE:                                             ; preds = %main_body
+  %27 = fsub float -0.000000e+00, %22
+  br label %ENDIF
+
+ENDIF:                                            ; preds = %main_body, %ELSE
+  %temp.0 = phi float [ %27, %ELSE ], [ %22, %main_body ]
+  %28 = fadd float %temp.0, %24
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %28, float %28, float 0.000000e+00, float 1.000000e+00)
+  ret void
+}
+
+; We just want ot make sure the program doesn't crash
+; CHECK: @loop
+
+define void @loop(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
+main_body:
+  %20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
+  %21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
+  %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
+  %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
+  %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
+  %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
+  %26 = fptosi float %25 to i32
+  %27 = bitcast i32 %26 to float
+  %28 = bitcast float %27 to i32
+  br label %LOOP
+
+LOOP:                                             ; preds = %ENDIF, %main_body
+  %temp4.0 = phi float [ %22, %main_body ], [ %temp5.0, %ENDIF ]
+  %temp5.0 = phi float [ %23, %main_body ], [ %temp6.0, %ENDIF ]
+  %temp6.0 = phi float [ %24, %main_body ], [ %temp4.0, %ENDIF ]
+  %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %37, %ENDIF ]
+  %29 = bitcast float %temp8.0 to i32
+  %30 = icmp sge i32 %29, %28
+  %31 = sext i1 %30 to i32
+  %32 = bitcast i32 %31 to float
+  %33 = bitcast float %32 to i32
+  %34 = icmp ne i32 %33, 0
+  br i1 %34, label %IF, label %ENDIF
+
+IF:                                               ; preds = %LOOP
+  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00)
+  ret void
+
+ENDIF:                                            ; preds = %LOOP
+  %35 = bitcast float %temp8.0 to i32
+  %36 = add i32 %35, 1
+  %37 = bitcast i32 %36 to float
+  br label %LOOP
+}
+
+; Function Attrs: nounwind readnone
+declare float @llvm.SI.load.const(<16 x i8>, i32) #1
+
+; Function Attrs: readonly
+declare float @fabs(float) #2
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
+
+attributes #0 = { "ShaderType"="0" }
+attributes #1 = { nounwind readnone }
+attributes #2 = { readonly }
+
+!0 = metadata !{metadata !"const", null, i32 1}
+
diff --git a/test/CodeGen/R600/shl.ll b/test/CodeGen/R600/shl.ll
index db970e9..d99e325 100644
--- a/test/CodeGen/R600/shl.ll
+++ b/test/CodeGen/R600/shl.ll
@@ -1,12 +1,39 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
 
-; CHECK: @shl_v4i32
-; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: @shl_v2i32
+;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
-define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) {
+;SI-CHECK: @shl_v2i32
+;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %result = shl <2 x i32> %a, %b
+  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+;EG-CHECK: @shl_v4i32
+;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @shl_v4i32
+;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHL_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
+  %a = load <4 x i32> addrspace(1) * %in
+  %b = load <4 x i32> addrspace(1) * %b_ptr
   %result = shl <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/short-args.ll b/test/CodeGen/R600/short-args.ll
index b69e327..20d0ae4 100644
--- a/test/CodeGen/R600/short-args.ll
+++ b/test/CodeGen/R600/short-args.ll
@@ -1,7 +1,10 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
+; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
 
-; CHECK: @i8_arg
-; CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
+; EG-CHECK: @i8_arg
+; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
+; SI-CHECK: BUFFER_LOAD_UBYTE
 
 define void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind {
 entry:
@@ -10,8 +13,9 @@ entry:
   ret void
 }
 
-; CHECK: @i8_zext_arg
-; CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
+; EG-CHECK: @i8_zext_arg
+; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
+; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]}}, SGPR0_SGPR1, 11
 
 define void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind {
 entry:
@@ -20,8 +24,20 @@ entry:
   ret void
 }
 
-; CHECK: @i16_arg
-; CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
+; EG-CHECK: @i8_sext_arg
+; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
+; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]}}, SGPR0_SGPR1, 11
+
+define void @i8_sext_arg(i32 addrspace(1)* nocapture %out, i8 signext %in) nounwind {
+entry:
+  %0 = sext i8 %in to i32
+  store i32 %0, i32 addrspace(1)* %out, align 4
+  ret void
+}
+
+; EG-CHECK: @i16_arg
+; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
+; SI-CHECK: BUFFER_LOAD_USHORT
 
 define void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind {
 entry:
@@ -30,8 +46,9 @@ entry:
   ret void
 }
 
-; CHECK: @i16_zext_arg
-; CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
+; EG-CHECK: @i16_zext_arg
+; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
+; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]}}, SGPR0_SGPR1, 11
 
 define void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind {
 entry:
@@ -39,3 +56,14 @@ entry:
   store i32 %0, i32 addrspace(1)* %out, align 4
   ret void
 }
+
+; EG-CHECK: @i16_sext_arg
+; EG-CHECK: MOV {{[ *]*}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
+; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]}}, SGPR0_SGPR1, 11
+
+define void @i16_sext_arg(i32 addrspace(1)* nocapture %out, i16 signext %in) nounwind {
+entry:
+  %0 = sext i16 %in to i32
+  store i32 %0, i32 addrspace(1)* %out, align 4
+  ret void
+}
diff --git a/test/CodeGen/R600/sint_to_fp.ll b/test/CodeGen/R600/sint_to_fp.ll
index 91a8eb7..4e88494 100644
--- a/test/CodeGen/R600/sint_to_fp.ll
+++ b/test/CodeGen/R600/sint_to_fp.ll
@@ -1,11 +1,28 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
 
-; CHECK: @sint_to_fp_v4i32
-; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; R600-CHECK: @sint_to_fp_v2i32
+; R600-CHECK-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W
+; R600-CHECK-DAG: INT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X
+; SI-CHECK: @sint_to_fp_v2i32
+; SI-CHECK: V_CVT_F32_I32_e32
+; SI-CHECK: V_CVT_F32_I32_e32
+define void @sint_to_fp_v2i32(<2 x float> addrspace(1)* %out, <2 x i32> %in) {
+  %result = sitofp <2 x i32> %in to <2 x float>
+  store <2 x float> %result, <2 x float> addrspace(1)* %out
+  ret void
+}
 
+; R600-CHECK: @sint_to_fp_v4i32
+; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; R600-CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; SI-CHECK: @sint_to_fp_v4i32
+; SI-CHECK: V_CVT_F32_I32_e32
+; SI-CHECK: V_CVT_F32_I32_e32
+; SI-CHECK: V_CVT_F32_I32_e32
+; SI-CHECK: V_CVT_F32_I32_e32
 define void @sint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
   %value = load <4 x i32> addrspace(1) * %in
   %result = sitofp <4 x i32> %value to <4 x float>
diff --git a/test/CodeGen/R600/sra.ll b/test/CodeGen/R600/sra.ll
index 972542d..5220a96 100644
--- a/test/CodeGen/R600/sra.ll
+++ b/test/CodeGen/R600/sra.ll
@@ -1,13 +1,54 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
 
-; CHECK: @ashr_v4i32
-; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: @ashr_v2i32
+;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
-define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) {
+;SI-CHECK: @ashr_v2i32
+;SI-CHECK: V_ASHR_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ASHR_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %result = ashr <2 x i32> %a, %b
+  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+;EG-CHECK: @ashr_v4i32
+;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @ashr_v4i32
+;SI-CHECK: V_ASHR_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ASHR_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ASHR_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_ASHR_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
+  %a = load <4 x i32> addrspace(1) * %in
+  %b = load <4 x i32> addrspace(1) * %b_ptr
   %result = ashr <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
 }
+
+;EG-CHECK: @ashr_i64
+;EG-CHECK: ASHR
+
+;SI-CHECK: @ashr_i64
+;SI-CHECK: V_ASHR_I64
+define void @ashr_i64(i64 addrspace(1)* %out, i32 %in) {
+entry:
+  %0 = sext i32 %in to i64
+  %1 = ashr i64 %0, 8
+  store i64 %1, i64 addrspace(1)* %out
+  ret void
+}
+
diff --git a/test/CodeGen/R600/srl.ll b/test/CodeGen/R600/srl.ll
index 5f63600..d1dcd7f 100644
--- a/test/CodeGen/R600/srl.ll
+++ b/test/CodeGen/R600/srl.ll
@@ -1,12 +1,40 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
 
-; CHECK: @lshr_v4i32
-; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: @lshr_v2i32
+;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
-define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) {
+;SI-CHECK: @lshr_v2i32
+;SI-CHECK: V_LSHR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @lshr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %result = lshr <2 x i32> %a, %b
+  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+
+;EG-CHECK: @lshr_v4i32
+;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: LSHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @lshr_v4i32
+;SI-CHECK: V_LSHR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_LSHR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+  %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
+  %a = load <4 x i32> addrspace(1) * %in
+  %b = load <4 x i32> addrspace(1) * %b_ptr
   %result = lshr <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll
index 4d673f3..1bda5e6 100644
--- a/test/CodeGen/R600/store.ll
+++ b/test/CodeGen/R600/store.ll
@@ -1,9 +1,12 @@
 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s
 ; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
 
 ; floating-point store
 ; EG-CHECK: @store_f32
 ; EG-CHECK: RAT_WRITE_CACHELESS_32_eg T{{[0-9]+\.X, T[0-9]+\.X}}, 1
+; CM-CHECK: @store_f32
+; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
 ; SI-CHECK: @store_f32
 ; SI-CHECK: BUFFER_STORE_DWORD
 
@@ -11,3 +14,49 @@ define void @store_f32(float addrspace(1)* %out, float %in) {
   store float %in, float addrspace(1)* %out
   ret void
 }
+
+; vec2 floating-point stores
+; EG-CHECK: @store_v2f32
+; EG-CHECK: RAT_WRITE_CACHELESS_64_eg
+; CM-CHECK: @store_v2f32
+; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD
+; SI-CHECK: @store_v2f32
+; SI-CHECK: BUFFER_STORE_DWORDX2
+
+define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) {
+entry:
+  %0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0
+  %1 = insertelement <2 x float> %0, float %b, i32 0
+  store <2 x float> %1, <2 x float> addrspace(1)* %out
+  ret void
+}
+
+; The stores in this function are combined by the optimizer to create a
+; 64-bit store with 32-bit alignment.  This is legal for SI and the legalizer
+; should not try to split the 64-bit store back into 2 32-bit stores.
+;
+; Evergreen / Northern Islands don't support 64-bit stores yet, so there should
+; be two 32-bit stores.
+
+; EG-CHECK: @vecload2
+; EG-CHECK: RAT_WRITE_CACHELESS_64_eg
+; CM-CHECK: @vecload2
+; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD
+; SI-CHECK: @vecload2
+; SI-CHECK: BUFFER_STORE_DWORDX2
+define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
+entry:
+  %0 = load i32 addrspace(2)* %mem, align 4, !tbaa !5
+  %arrayidx1.i = getelementptr inbounds i32 addrspace(2)* %mem, i64 1
+  %1 = load i32 addrspace(2)* %arrayidx1.i, align 4, !tbaa !5
+  store i32 %0, i32 addrspace(1)* %out, align 4, !tbaa !5
+  %arrayidx1 = getelementptr inbounds i32 addrspace(1)* %out, i64 1
+  store i32 %1, i32 addrspace(1)* %arrayidx1, align 4, !tbaa !5
+  ret void
+}
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!5 = metadata !{metadata !"int", metadata !6}
+!6 = metadata !{metadata !"omnipotent char", metadata !7}
+!7 = metadata !{metadata !"Simple C/C++ TBAA"}
diff --git a/test/CodeGen/R600/sub.ll b/test/CodeGen/R600/sub.ll
index 12bfba3..3bd4cb8 100644
--- a/test/CodeGen/R600/sub.ll
+++ b/test/CodeGen/R600/sub.ll
@@ -1,11 +1,36 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
 
-;CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: @test2
+;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+;SI-CHECK: @test2
+;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %result = sub <2 x i32> %a, %b
+  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+;EG-CHECK: @test4
+;EG-CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @test4
+;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
   %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
   %a = load <4 x i32> addrspace(1) * %in
   %b = load <4 x i32> addrspace(1) * %b_ptr
diff --git a/test/CodeGen/R600/swizzle-export.ll b/test/CodeGen/R600/swizzle-export.ll
new file mode 100644
index 0000000..b2175af
--- /dev/null
+++ b/test/CodeGen/R600/swizzle-export.ll
@@ -0,0 +1,134 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+
+;EG-CHECK: @main
+;EG-CHECK: EXPORT T{{[0-9]+}}.XYXX
+;EG-CHECK: EXPORT T{{[0-9]+}}.ZXXX
+;EG-CHECK: EXPORT T{{[0-9]+}}.XXWX
+;EG-CHECK: EXPORT T{{[0-9]+}}.XXXW
+
+define void @main() #0 {
+main_body:
+  %0 = call float @llvm.R600.load.input(i32 4)
+  %1 = call float @llvm.R600.load.input(i32 5)
+  %2 = call float @llvm.R600.load.input(i32 6)
+  %3 = call float @llvm.R600.load.input(i32 7)
+  %4 = load <4 x float> addrspace(8)* null
+  %5 = extractelement <4 x float> %4, i32 1
+  %6 = load <4 x float> addrspace(8)* null
+  %7 = extractelement <4 x float> %6, i32 2
+  %8 = load <4 x float> addrspace(8)* null
+  %9 = extractelement <4 x float> %8, i32 0
+  %10 = fmul float 0.000000e+00, %9
+  %11 = load <4 x float> addrspace(8)* null
+  %12 = extractelement <4 x float> %11, i32 0
+  %13 = fmul float %5, %12
+  %14 = load <4 x float> addrspace(8)* null
+  %15 = extractelement <4 x float> %14, i32 0
+  %16 = fmul float 0.000000e+00, %15
+  %17 = load <4 x float> addrspace(8)* null
+  %18 = extractelement <4 x float> %17, i32 0
+  %19 = fmul float 0.000000e+00, %18
+  %20 = load <4 x float> addrspace(8)* null
+  %21 = extractelement <4 x float> %20, i32 0
+  %22 = fmul float %7, %21
+  %23 = load <4 x float> addrspace(8)* null
+  %24 = extractelement <4 x float> %23, i32 0
+  %25 = fmul float 0.000000e+00, %24
+  %26 = load <4 x float> addrspace(8)* null
+  %27 = extractelement <4 x float> %26, i32 0
+  %28 = fmul float 0.000000e+00, %27
+  %29 = load <4 x float> addrspace(8)* null
+  %30 = extractelement <4 x float> %29, i32 0
+  %31 = fmul float 0.000000e+00, %30
+  %32 = load <4 x float> addrspace(8)* null
+  %33 = extractelement <4 x float> %32, i32 0
+  %34 = fmul float 0.000000e+00, %33
+  %35 = load <4 x float> addrspace(8)* null
+  %36 = extractelement <4 x float> %35, i32 0
+  %37 = fmul float 0.000000e+00, %36
+  %38 = load <4 x float> addrspace(8)* null
+  %39 = extractelement <4 x float> %38, i32 0
+  %40 = fmul float 1.000000e+00, %39
+  %41 = load <4 x float> addrspace(8)* null
+  %42 = extractelement <4 x float> %41, i32 0
+  %43 = fmul float 0.000000e+00, %42
+  %44 = load <4 x float> addrspace(8)* null
+  %45 = extractelement <4 x float> %44, i32 0
+  %46 = fmul float 0.000000e+00, %45
+  %47 = load <4 x float> addrspace(8)* null
+  %48 = extractelement <4 x float> %47, i32 0
+  %49 = fmul float 0.000000e+00, %48
+  %50 = load <4 x float> addrspace(8)* null
+  %51 = extractelement <4 x float> %50, i32 0
+  %52 = fmul float 0.000000e+00, %51
+  %53 = load <4 x float> addrspace(8)* null
+  %54 = extractelement <4 x float> %53, i32 0
+  %55 = fmul float 1.000000e+00, %54
+  %56 = insertelement <4 x float> undef, float %0, i32 0
+  %57 = insertelement <4 x float> %56, float %1, i32 1
+  %58 = insertelement <4 x float> %57, float %2, i32 2
+  %59 = insertelement <4 x float> %58, float %3, i32 3
+  call void @llvm.R600.store.swizzle(<4 x float> %59, i32 60, i32 1)
+  %60 = insertelement <4 x float> undef, float %10, i32 0
+  %61 = insertelement <4 x float> %60, float %13, i32 1
+  %62 = insertelement <4 x float> %61, float %16, i32 2
+  %63 = insertelement <4 x float> %62, float %19, i32 3
+  call void @llvm.R600.store.swizzle(<4 x float> %63, i32 0, i32 2)
+  %64 = insertelement <4 x float> undef, float %22, i32 0
+  %65 = insertelement <4 x float> %64, float %25, i32 1
+  %66 = insertelement <4 x float> %65, float %28, i32 2
+  %67 = insertelement <4 x float> %66, float %31, i32 3
+  call void @llvm.R600.store.swizzle(<4 x float> %67, i32 1, i32 2)
+  %68 = insertelement <4 x float> undef, float %34, i32 0
+  %69 = insertelement <4 x float> %68, float %37, i32 1
+  %70 = insertelement <4 x float> %69, float %40, i32 2
+  %71 = insertelement <4 x float> %70, float %43, i32 3
+  call void @llvm.R600.store.swizzle(<4 x float> %71, i32 2, i32 2)
+  %72 = insertelement <4 x float> undef, float %46, i32 0
+  %73 = insertelement <4 x float> %72, float %49, i32 1
+  %74 = insertelement <4 x float> %73, float %52, i32 2
+  %75 = insertelement <4 x float> %74, float %55, i32 3
+  call void @llvm.R600.store.swizzle(<4 x float> %75, i32 3, i32 2)
+  ret void
+}
+
+; EG-CHECK: @main2
+; EG-CHECK: T{{[0-9]+}}.ZXY0
+
+define void @main2() #0 {
+main_body:
+  %0 = call float @llvm.R600.load.input(i32 4)
+  %1 = call float @llvm.R600.load.input(i32 5)
+  %2 = call float @llvm.R600.load.input(i32 6)
+  %3 = call float @llvm.R600.load.input(i32 7)
+  %4 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1)
+  %5 = extractelement <4 x float> %4, i32 0
+  %6 = call float @llvm.cos.f32(float %5)
+  %7 = load <4 x float> addrspace(8)* null
+  %8 = extractelement <4 x float> %7, i32 0
+  %9 = load <4 x float> addrspace(8)* null
+  %10 = extractelement <4 x float> %9, i32 1
+  %11 = insertelement <4 x float> undef, float %0, i32 0
+  %12 = insertelement <4 x float> %11, float %1, i32 1
+  %13 = insertelement <4 x float> %12, float %2, i32 2
+  %14 = insertelement <4 x float> %13, float %3, i32 3
+  call void @llvm.R600.store.swizzle(<4 x float> %14, i32 60, i32 1)
+  %15 = insertelement <4 x float> undef, float %6, i32 0
+  %16 = insertelement <4 x float> %15, float %8, i32 1
+  %17 = insertelement <4 x float> %16, float %10, i32 2
+  %18 = insertelement <4 x float> %17, float 0.000000e+00, i32 3
+  call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2)
+  ret void
+}
+
+; Function Attrs: readnone
+declare float @llvm.R600.load.input(i32) #1
+
+; Function Attrs: nounwind readonly
+declare float @llvm.cos.f32(float) #2
+
+declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
+
+attributes #0 = { "ShaderType"="1" }
+attributes #1 = { readnone }
+attributes #2 = { nounwind readonly }
diff --git a/test/CodeGen/R600/udiv.ll b/test/CodeGen/R600/udiv.ll
index b81e366..08fe2ef 100644
--- a/test/CodeGen/R600/udiv.ll
+++ b/test/CodeGen/R600/udiv.ll
@@ -1,11 +1,30 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
 
 ;The code generated by udiv is long and complex and may frequently change.
 ;The goal of this test is to make sure the ISel doesn't fail when it gets
 ;a v4i32 udiv
-;CHECK: CF_END
 
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+;EG-CHECK: @test2
+;EG-CHECK: CF_END
+;SI-CHECK: @test2
+;SI-CHECK: S_ENDPGM
+
+define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %result = udiv <2 x i32> %a, %b
+  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+;EG-CHECK: @test4
+;EG-CHECK: CF_END
+;SI-CHECK: @test4
+;SI-CHECK: S_ENDPGM
+
+define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
   %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
   %a = load <4 x i32> addrspace(1) * %in
   %b = load <4 x i32> addrspace(1) * %b_ptr
diff --git a/test/CodeGen/R600/uint_to_fp.ll b/test/CodeGen/R600/uint_to_fp.ll
index 9054fc4..faac77a 100644
--- a/test/CodeGen/R600/uint_to_fp.ll
+++ b/test/CodeGen/R600/uint_to_fp.ll
@@ -1,11 +1,28 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
 
-; CHECK: @uint_to_fp_v4i32
-; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; R600-CHECK: @uint_to_fp_v2i32
+; R600-CHECK-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W
+; R600-CHECK-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X
+; SI-CHECK: @uint_to_fp_v2i32
+; SI-CHECK: V_CVT_F32_U32_e32
+; SI-CHECK: V_CVT_F32_U32_e32
+define void @uint_to_fp_v2i32(<2 x float> addrspace(1)* %out, <2 x i32> %in) {
+  %result = uitofp <2 x i32> %in to <2 x float>
+  store <2 x float> %result, <2 x float> addrspace(1)* %out
+  ret void
+}
 
+; R600-CHECK: @uint_to_fp_v4i32
+; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; R600-CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; SI-CHECK: @uint_to_fp_v4i32
+; SI-CHECK: V_CVT_F32_U32_e32
+; SI-CHECK: V_CVT_F32_U32_e32
+; SI-CHECK: V_CVT_F32_U32_e32
+; SI-CHECK: V_CVT_F32_U32_e32
 define void @uint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
   %value = load <4 x i32> addrspace(1) * %in
   %result = uitofp <4 x i32> %value to <4 x float>
diff --git a/test/CodeGen/R600/uitofp.ll b/test/CodeGen/R600/uitofp.ll
deleted file mode 100644
index 6cf9e6a..0000000
--- a/test/CodeGen/R600/uitofp.ll
+++ /dev/null
@@ -1,16 +0,0 @@
-;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
-
-;CHECK: V_CVT_F32_U32_e32
-
-define void @main(i32 %p) #0 {
-main_body:
-  %0 = uitofp i32 %p to float
-  call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %0, float %0, float %0, float %0)
-  ret void
-}
-
-declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
-
-attributes #0 = { "ShaderType"="0" }
-
-!0 = metadata !{metadata !"const", null, i32 1}
diff --git a/test/CodeGen/R600/unsupported-cc.ll b/test/CodeGen/R600/unsupported-cc.ll
index b311f4c..cf29833 100644
--- a/test/CodeGen/R600/unsupported-cc.ll
+++ b/test/CodeGen/R600/unsupported-cc.ll
@@ -3,7 +3,7 @@
 ; These tests are for condition codes that are not supported by the hardware
 
 ; CHECK: @slt
-; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
+; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
 ; CHECK-NEXT: 5(7.006492e-45)
 define void @slt(i32 addrspace(1)* %out, i32 %in) {
 entry:
@@ -14,7 +14,7 @@ entry:
 }
 
 ; CHECK: @ult_i32
-; CHECK: SETGT_UINT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
+; CHECK: SETGT_UINT * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
 ; CHECK-NEXT: 5(7.006492e-45)
 define void @ult_i32(i32 addrspace(1)* %out, i32 %in) {
 entry:
@@ -25,7 +25,7 @@ entry:
 }
 
 ; CHECK: @ult_float
-; CHECK: SETGT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
+; CHECK: SETGT * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
 ; CHECK-NEXT: 1084227584(5.000000e+00)
 define void @ult_float(float addrspace(1)* %out, float %in) {
 entry:
@@ -36,7 +36,7 @@ entry:
 }
 
 ; CHECK: @olt
-; CHECK: SETGT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
+; CHECK: SETGT * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
 ;CHECK-NEXT: 1084227584(5.000000e+00)
 define void @olt(float addrspace(1)* %out, float %in) {
 entry:
@@ -47,7 +47,7 @@ entry:
 }
 
 ; CHECK: @sle
-; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
+; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
 ; CHECK-NEXT: 6(8.407791e-45)
 define void @sle(i32 addrspace(1)* %out, i32 %in) {
 entry:
@@ -58,7 +58,7 @@ entry:
 }
 
 ; CHECK: @ule_i32
-; CHECK: SETGT_UINT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
+; CHECK: SETGT_UINT * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
 ; CHECK-NEXT: 6(8.407791e-45)
 define void @ule_i32(i32 addrspace(1)* %out, i32 %in) {
 entry:
@@ -69,7 +69,7 @@ entry:
 }
 
 ; CHECK: @ule_float
-; CHECK: SETGE * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
+; CHECK: SETGE * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
 ; CHECK-NEXT: 1084227584(5.000000e+00)
 define void @ule_float(float addrspace(1)* %out, float %in) {
 entry:
@@ -80,7 +80,7 @@ entry:
 }
 
 ; CHECK: @ole
-; CHECK: SETGE * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}},
+; CHECK: SETGE * T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
 ; CHECK-NEXT:1084227584(5.000000e+00)
 define void @ole(float addrspace(1)* %out, float %in) {
 entry:
diff --git a/test/CodeGen/R600/urem.ll b/test/CodeGen/R600/urem.ll
index a2cc0bd..cf3474c 100644
--- a/test/CodeGen/R600/urem.ll
+++ b/test/CodeGen/R600/urem.ll
@@ -1,11 +1,30 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
 
 ;The code generated by urem is long and complex and may frequently change.
 ;The goal of this test is to make sure the ISel doesn't fail when it gets
-;a v4i32 urem
-;CHECK: CF_END
+;a v2i32/v4i32 urem
 
-define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+;EG-CHECK: @test2
+;EG-CHECK: CF_END
+;SI-CHECK: @test2
+;SI-CHECK: S_ENDPGM
+
+define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
+  %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
+  %a = load <2 x i32> addrspace(1) * %in
+  %b = load <2 x i32> addrspace(1) * %b_ptr
+  %result = urem <2 x i32> %a, %b
+  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+;EG-CHECK: @test4
+;EG-CHECK: CF_END
+;SI-CHECK: @test4
+;SI-CHECK: S_ENDPGM
+
+define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
   %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
   %a = load <4 x i32> addrspace(1) * %in
   %b = load <4 x i32> addrspace(1) * %b_ptr
diff --git a/test/CodeGen/R600/vertex-fetch-encoding.ll b/test/CodeGen/R600/vertex-fetch-encoding.ll
new file mode 100644
index 0000000..d892229
--- /dev/null
+++ b/test/CodeGen/R600/vertex-fetch-encoding.ll
@@ -0,0 +1,25 @@
+; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=barts | FileCheck --check-prefix=NI-CHECK %s
+; RUN: not llc < %s -march=r600 -show-mc-encoding -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s
+
+; NI-CHECK: @vtx_fetch32
+; NI-CHECK: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00
+; CM-CHECK: @vtx_fetch32
+; CM-CHECK: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0 ; encoding: [0x40,0x01,0x0[[GPR]],0x00,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x00,0x00
+
+define void @vtx_fetch32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
+entry:
+  %0 = load i32 addrspace(1)* %in
+  store i32 %0, i32 addrspace(1)* %out
+  ret void
+}
+
+; NI-CHECK: @vtx_fetch128
+; NI-CHECK: VTX_READ_128 T[[DST:[0-9]]].XYZW, T[[SRC:[0-9]]].X, 0 ; encoding: [0x40,0x01,0x0[[SRC]],0x40,0x0[[DST]],0x10,0x8d,0x18,0x00,0x00,0x08,0x00
+; XXX: Add a case for Cayman when v4i32 stores are supported.
+
+define void @vtx_fetch128(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
+entry:
+  %0 = load <4 x i32> addrspace(1)* %in
+  store <4 x i32> %0, <4 x i32> addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/vselect.ll b/test/CodeGen/R600/vselect.ll
index edd7ba0..72a9084 100644
--- a/test/CodeGen/R600/vselect.ll
+++ b/test/CodeGen/R600/vselect.ll
@@ -1,10 +1,53 @@
-;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s
 
-; CHECK: @test_select_v4i32
-; CHECK: CNDE_INT T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: CNDE_INT T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: @test_select_v2i32
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @test_select_v2i32
+;SI-CHECK: V_CNDMASK_B32_e64
+;SI-CHECK: V_CNDMASK_B32_e64
+
+define void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) {
+entry:
+  %0 = load <2 x i32> addrspace(1)* %in0
+  %1 = load <2 x i32> addrspace(1)* %in1
+  %cmp = icmp ne <2 x i32> %0, %1
+  %result = select <2 x i1> %cmp, <2 x i32> %0, <2 x i32> %1
+  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+;EG-CHECK: @test_select_v2f32
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @test_select_v2f32
+;SI-CHECK: V_CNDMASK_B32_e64
+;SI-CHECK: V_CNDMASK_B32_e64
+
+define void @test_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in0, <2 x float> addrspace(1)* %in1) {
+entry:
+  %0 = load <2 x float> addrspace(1)* %in0
+  %1 = load <2 x float> addrspace(1)* %in1
+  %cmp = fcmp one <2 x float> %0, %1
+  %result = select <2 x i1> %cmp, <2 x float> %0, <2 x float> %1
+  store <2 x float> %result, <2 x float> addrspace(1)* %out
+  ret void
+}
+
+;EG-CHECK: @test_select_v4i32
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @test_select_v4i32
+;SI-CHECK: V_CNDMASK_B32_e64
+;SI-CHECK: V_CNDMASK_B32_e64
+;SI-CHECK: V_CNDMASK_B32_e64
+;SI-CHECK: V_CNDMASK_B32_e64
 
 define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) {
 entry:
@@ -15,3 +58,19 @@ entry:
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
 }
+
+;EG-CHECK: @test_select_v4f32
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: CNDE_INT {{\*? *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+define void @test_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in0, <4 x float> addrspace(1)* %in1) {
+entry:
+  %0 = load <4 x float> addrspace(1)* %in0
+  %1 = load <4 x float> addrspace(1)* %in1
+  %cmp = fcmp one <4 x float> %0, %1
+  %result = select <4 x i1> %cmp, <4 x float> %0, <4 x float> %1
+  store <4 x float> %result, <4 x float> addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/R600/vtx-schedule.ll b/test/CodeGen/R600/vtx-schedule.ll
index a0c79e3..97d37ed 100644
--- a/test/CodeGen/R600/vtx-schedule.ll
+++ b/test/CodeGen/R600/vtx-schedule.ll
@@ -6,17 +6,13 @@
 
 ; CHECK: @test
 ; CHECK: Fetch clause
-; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 40
-; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 44
-; CHECK: Fetch clause
 ; CHECK_VTX_READ_32 [[IN0:T[0-9]+\.X]], [[IN0]], 0
+; CHECK: Fetch clause
 ; CHECK_VTX_READ_32 [[IN1:T[0-9]+\.X]], [[IN1]], 0
-define void @test(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in0, i32 addrspace(1)* nocapture %in1) {
+define void @test(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* addrspace(1)* nocapture %in0) {
 entry:
-  %0 = load i32 addrspace(1)* %in0, align 4
-  %1 = load i32 addrspace(1)* %in1, align 4
-  %cmp.i = icmp slt i32 %0, %1
-  %cond.i = select i1 %cmp.i, i32 %0, i32 %1
-  store i32 %cond.i, i32 addrspace(1)* %out, align 4
+  %0 = load i32 addrspace(1)* addrspace(1)* %in0
+  %1 = load i32 addrspace(1)* %0
+  store i32 %1, i32 addrspace(1)* %out
   ret void
 }
diff --git a/test/CodeGen/R600/work-item-intrinsics.ll b/test/CodeGen/R600/work-item-intrinsics.ll
index 46e3e54..7998983 100644
--- a/test/CodeGen/R600/work-item-intrinsics.ll
+++ b/test/CodeGen/R600/work-item-intrinsics.ll
@@ -3,7 +3,7 @@
 
 ; R600-CHECK: @ngroups_x
 ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
-; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 0
+; R600-CHECK: MOV * [[VAL]], KC0[0].X
 ; SI-CHECK: @ngroups_x
 ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 0
 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
@@ -17,7 +17,7 @@ entry:
 
 ; R600-CHECK: @ngroups_y
 ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
-; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 4
+; R600-CHECK: MOV * [[VAL]], KC0[0].Y
 ; SI-CHECK: @ngroups_y
 ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 1
 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
@@ -31,7 +31,7 @@ entry:
 
 ; R600-CHECK: @ngroups_z
 ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
-; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 8
+; R600-CHECK: MOV * [[VAL]], KC0[0].Z
 ; SI-CHECK: @ngroups_z
 ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 2
 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
@@ -45,7 +45,7 @@ entry:
 
 ; R600-CHECK: @global_size_x
 ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
-; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 12
+; R600-CHECK: MOV * [[VAL]], KC0[0].W
 ; SI-CHECK: @global_size_x
 ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 3
 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
@@ -59,7 +59,7 @@ entry:
 
 ; R600-CHECK: @global_size_y
 ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
-; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 16
+; R600-CHECK: MOV * [[VAL]], KC0[1].X
 ; SI-CHECK: @global_size_y
 ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 4
 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
@@ -73,7 +73,7 @@ entry:
 
 ; R600-CHECK: @global_size_z
 ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
-; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 20
+; R600-CHECK: MOV * [[VAL]], KC0[1].Y
 ; SI-CHECK: @global_size_z
 ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 5
 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
@@ -87,7 +87,7 @@ entry:
 
 ; R600-CHECK: @local_size_x
 ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
-; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 24
+; R600-CHECK: MOV * [[VAL]], KC0[1].Z
 ; SI-CHECK: @local_size_x
 ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 6
 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
@@ -101,7 +101,7 @@ entry:
 
 ; R600-CHECK: @local_size_y
 ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
-; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 28
+; R600-CHECK: MOV * [[VAL]], KC0[1].W
 ; SI-CHECK: @local_size_y
 ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 7
 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
@@ -115,7 +115,7 @@ entry:
 
 ; R600-CHECK: @local_size_z
 ; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
-; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 32
+; R600-CHECK: MOV * [[VAL]], KC0[2].X
 ; SI-CHECK: @local_size_z
 ; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 8
 ; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
diff --git a/test/CodeGen/R600/xor.ll b/test/CodeGen/R600/xor.ll
index cf612e0..f52729d 100644
--- a/test/CodeGen/R600/xor.ll
+++ b/test/CodeGen/R600/xor.ll
@@ -1,12 +1,38 @@
-; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
+;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
 
-; CHECK: @xor_v4i32
-; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: @xor_v2i32
+;EG-CHECK: XOR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: XOR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
-define void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) {
+;SI-CHECK: @xor_v2i32
+;SI-CHECK: V_XOR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_XOR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+
+define void @xor_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) {
+  %a = load <2 x i32> addrspace(1) * %in0
+  %b = load <2 x i32> addrspace(1) * %in1
+  %result = xor <2 x i32> %a, %b
+  store <2 x i32> %result, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+;EG-CHECK: @xor_v4i32
+;EG-CHECK: XOR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: XOR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: XOR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;EG-CHECK: XOR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+;SI-CHECK: @xor_v4i32
+;SI-CHECK: V_XOR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_XOR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_XOR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+;SI-CHECK: V_XOR_B32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}}
+
+define void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) {
+  %a = load <4 x i32> addrspace(1) * %in0
+  %b = load <4 x i32> addrspace(1) * %in1
   %result = xor <4 x i32> %a, %b
   store <4 x i32> %result, <4 x i32> addrspace(1)* %out
   ret void
diff --git a/test/CodeGen/R600/zero_extend.ll b/test/CodeGen/R600/zero_extend.ll
new file mode 100644
index 0000000..413b849
--- /dev/null
+++ b/test/CodeGen/R600/zero_extend.ll
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
+; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
+
+; R600-CHECK: @test
+; R600-CHECK: RAT_WRITE_CACHELESS_32_eg
+; R600-CHECK: RAT_WRITE_CACHELESS_32_eg
+
+; SI-CHECK: @test
+; SI-CHECK: V_MOV_B32_e32 [[ZERO:VGPR[0-9]]], 0
+; SI-CHECK: BUFFER_STORE_DWORDX2 VGPR0_[[ZERO]]
+define void @test(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
+entry:
+  %0 = mul i32 %a, %b
+  %1 = add i32 %0, %c
+  %2 = zext i32 %1 to i64
+  store i64 %2, i64 addrspace(1)* %out
+  ret void
+}
diff --git a/test/CodeGen/SPARC/2011-01-11-CC.ll b/test/CodeGen/SPARC/2011-01-11-CC.ll
index 599b451..edbcb49 100644
--- a/test/CodeGen/SPARC/2011-01-11-CC.ll
+++ b/test/CodeGen/SPARC/2011-01-11-CC.ll
@@ -63,10 +63,10 @@ entry:
 
 define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noinline {
 entry:
-;V8: test_select_int_fcc
+;V8-LABEL: test_select_int_fcc:
 ;V8: fcmps
 ;V8: {{fbe|fbne}}
-;V9: test_select_int_fcc
+;V9-LABEL: test_select_int_fcc:
 ;V9: fcmps
 ;V9-NOT: {{fbe|fbne}}
 ;V9: mov{{e|ne}} %fcc0
@@ -78,10 +78,10 @@ entry:
 
 define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readnone noinline {
 entry:
-;V8: test_select_fp_fcc
+;V8-LABEL: test_select_fp_fcc:
 ;V8: fcmps
 ;V8: {{fbe|fbne}}
-;V9: test_select_fp_fcc
+;V9-LABEL: test_select_fp_fcc:
 ;V9: fcmps
 ;V9-NOT: {{fbe|fbne}}
 ;V9: fmovs{{e|ne}} %fcc0
@@ -92,10 +92,10 @@ entry:
 
 define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind readnone noinline {
 entry:
-;V8: test_select_dfp_fcc
+;V8-LABEL: test_select_dfp_fcc:
 ;V8: fcmpd
 ;V8: {{fbne|fbe}}
-;V9: test_select_dfp_fcc
+;V9-LABEL: test_select_dfp_fcc:
 ;V9: fcmpd
 ;V9-NOT: {{fbne|fbe}}
 ;V9: fmovd{{e|ne}} %fcc0
diff --git a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
index 5fd5687..7cc7868 100644
--- a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
+++ b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
@@ -6,12 +6,12 @@
 
 define i8* @frameaddr() nounwind readnone {
 entry:
-;V8: frameaddr
+;V8-LABEL: frameaddr:
 ;V8: save %sp, -96, %sp
 ;V8: jmp %i7+8
 ;V8: restore %g0, %fp, %o0
 
-;V9: frameaddr
+;V9-LABEL: frameaddr:
 ;V9: save %sp, -96, %sp
 ;V9: jmp %i7+8
 ;V9: restore %g0, %fp, %o0
@@ -21,13 +21,13 @@ entry:
 
 define i8* @frameaddr2() nounwind readnone {
 entry:
-;V8: frameaddr2
+;V8-LABEL: frameaddr2:
 ;V8: ta 3
 ;V8: ld [%fp+56], {{.+}}
 ;V8: ld [{{.+}}+56], {{.+}}
 ;V8: ld [{{.+}}+56], {{.+}}
 
-;V9: frameaddr2
+;V9-LABEL: frameaddr2:
 ;V9: flushw
 ;V9: ld [%fp+56], {{.+}}
 ;V9: ld [{{.+}}+56], {{.+}}
@@ -42,10 +42,10 @@ declare i8* @llvm.frameaddress(i32) nounwind readnone
 
 define i8* @retaddr() nounwind readnone {
 entry:
-;V8: retaddr
+;V8-LABEL: retaddr:
 ;V8: or %g0, %o7, {{.+}}
 
-;V9: retaddr
+;V9-LABEL: retaddr:
 ;V9: or %g0, %o7, {{.+}}
 
   %0 = tail call i8* @llvm.returnaddress(i32 0)
@@ -54,25 +54,25 @@ entry:
 
 define i8* @retaddr2() nounwind readnone {
 entry:
-;V8: retaddr2
+;V8-LABEL: retaddr2:
 ;V8: ta 3
 ;V8: ld [%fp+56], {{.+}}
 ;V8: ld [{{.+}}+56], {{.+}}
 ;V8: ld [{{.+}}+60], {{.+}}
 
-;V9: retaddr2
+;V9-LABEL: retaddr2:
 ;V9: flushw
 ;V9: ld [%fp+56], {{.+}}
 ;V9: ld [{{.+}}+56], {{.+}}
 ;V9: ld [{{.+}}+60], {{.+}}
 
-;V8LEAF: retaddr2
+;V8LEAF-LABEL: retaddr2:
 ;V8LEAF: ta 3
 ;V8LEAF: ld [%fp+56], %[[R:[goli][0-7]]]
 ;V8LEAF: ld [%[[R]]+56], %[[R1:[goli][0-7]]]
 ;V8LEAF: ld [%[[R1]]+60], {{.+}}
 
-;V9LEAF: retaddr2
+;V9LEAF-LABEL: retaddr2:
 ;V9LEAF: flushw
 ;V9LEAF: ld [%fp+56], %[[R:[goli][0-7]]]
 ;V9LEAF: ld [%[[R]]+56], %[[R1:[goli][0-7]]]
diff --git a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
index b39c355..c71e7c0 100644
--- a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
+++ b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
@@ -54,12 +54,12 @@ bb5:                                              ; preds = %bb, %entry
 
 define i32 @test_inlineasm(i32 %a) nounwind {
 entry:
-;CHECK:      test_inlineasm
+;CHECK-LABEL:      test_inlineasm:
 ;CHECK:      sethi
 ;CHECK:      !NO_APP
 ;CHECK-NEXT: cmp
 ;CHECK-NEXT: bg
-;CHECK-NEXT: nop
+;CHECK-NEXT: or
   tail call void asm sideeffect "sethi 0, %g0", ""() nounwind
   %0 = icmp slt i32 %a, 0
   br i1 %0, label %bb, label %bb1
@@ -80,7 +80,7 @@ declare i32 @bar(i32)
 
 define i32 @test_implicit_def() nounwind {
 entry:
-;UNOPT:       test_implicit_def
+;UNOPT-LABEL:       test_implicit_def:
 ;UNOPT:       call func
 ;UNOPT-NEXT:  nop
   %0 = tail call i32 @func(i32* undef) nounwind
@@ -89,7 +89,7 @@ entry:
 
 define i32 @prevent_o7_in_call_delay_slot(i32 %i0) {
 entry:
-;CHECK:       prevent_o7_in_call_delay_slot
+;CHECK-LABEL:       prevent_o7_in_call_delay_slot:
 ;CHECK:       add %i0, 2, %o5
 ;CHECK:       add %i0, 3, %o7
 ;CHECK:       add %o5, %o7, %o0
@@ -109,7 +109,7 @@ declare i32 @func(i32*)
 
 define i32 @restore_add(i32 %a, i32 %b) {
 entry:
-;CHECK:  restore_add:
+;CHECK-LABEL:  restore_add:
 ;CHECK:  jmp %i7+8
 ;CHECK:  restore %o0, %i1, %o0
   %0 = tail call i32 @bar(i32 %a) nounwind
@@ -119,7 +119,7 @@ entry:
 
 define i32 @restore_add_imm(i32 %a) {
 entry:
-;CHECK:  restore_add_imm:
+;CHECK-LABEL:  restore_add_imm:
 ;CHECK:  jmp %i7+8
 ;CHECK:  restore %o0, 20, %o0
   %0 = tail call i32 @bar(i32 %a) nounwind
@@ -129,7 +129,7 @@ entry:
 
 define i32 @restore_or(i32 %a) {
 entry:
-;CHECK:  restore_or:
+;CHECK-LABEL:  restore_or:
 ;CHECK:  jmp %i7+8
 ;CHECK:  restore %g0, %o0, %o0
   %0 = tail call i32 @bar(i32 %a) nounwind
@@ -138,7 +138,7 @@ entry:
 
 define i32 @restore_or_imm(i32 %a) {
 entry:
-;CHECK:  restore_or_imm:
+;CHECK-LABEL:  restore_or_imm:
 ;CHECK:  or %o0, 20, %i0
 ;CHECK:  jmp %i7+8
 ;CHECK:  restore %g0, %g0, %g0
@@ -150,7 +150,7 @@ entry:
 
 define i32 @restore_sethi(i32 %a) {
 entry:
-;CHECK: restore_sethi
+;CHECK-LABEL: restore_sethi:
 ;CHECK-NOT: sethi  3
 ;CHECK: restore %g0, 3072, %o0
   %0 = tail call i32 @bar(i32 %a) nounwind
@@ -161,7 +161,7 @@ entry:
 
 define i32 @restore_sethi_3bit(i32 %a) {
 entry:
-;CHECK: restore_sethi
+;CHECK-LABEL: restore_sethi_3bit:
 ;CHECK: sethi  6
 ;CHECK-NOT: restore %g0, 6144, %o0
   %0 = tail call i32 @bar(i32 %a) nounwind
@@ -172,7 +172,7 @@ entry:
 
 define i32 @restore_sethi_large(i32 %a) {
 entry:
-;CHECK: restore_sethi
+;CHECK-LABEL: restore_sethi_large:
 ;CHECK: sethi  4000, %i0
 ;CHECK: restore %g0, %g0, %g0
   %0 = tail call i32 @bar(i32 %a) nounwind
diff --git a/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll b/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll
index 85c16e4..408b13d 100644
--- a/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll
+++ b/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll
@@ -6,7 +6,7 @@
 
 define i32 @test() nounwind {
 entry:
-;CHECK:     test
+;CHECK-LABEL:     test:
 ;CHECK:     st
 ;CHECK:     st
 ;CHECK:     st
diff --git a/test/CodeGen/SPARC/2011-01-22-SRet.ll b/test/CodeGen/SPARC/2011-01-22-SRet.ll
index 942971b..fc44bc4 100644
--- a/test/CodeGen/SPARC/2011-01-22-SRet.ll
+++ b/test/CodeGen/SPARC/2011-01-22-SRet.ll
@@ -4,7 +4,7 @@
 
 define weak void @make_foo(%struct.foo_t* noalias sret %agg.result, i32 %a, i32 %b, i32 %c) nounwind {
 entry:
-;CHECK: make_foo
+;CHECK-LABEL: make_foo:
 ;CHECK: ld [%sp+64], {{.+}}
 ;CHECK: jmp %o7+12
   %0 = getelementptr inbounds %struct.foo_t* %agg.result, i32 0, i32 0
@@ -18,9 +18,9 @@ entry:
 
 define i32 @test() nounwind {
 entry:
-;CHECK: test
+;CHECK-LABEL: test:
 ;CHECK: st {{.+}}, [%sp+64]
-;CHECK: make_foo
+;CHECK: call make_foo
 ;CHECK: unimp 12
   %f = alloca %struct.foo_t, align 8
   call void @make_foo(%struct.foo_t* noalias sret %f, i32 10, i32 20, i32 30) nounwind
diff --git a/test/CodeGen/SPARC/64bit.ll b/test/CodeGen/SPARC/64bit.ll
index a5ea4d9..f778f9d 100644
--- a/test/CodeGen/SPARC/64bit.ll
+++ b/test/CodeGen/SPARC/64bit.ll
@@ -1,10 +1,10 @@
 ; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s
 ; RUN: llc < %s -march=sparcv9  | FileCheck %s -check-prefix=OPT
 
-; CHECK: ret2:
+; CHECK-LABEL: ret2:
 ; CHECK: or %g0, %i1, %i0
 
-; OPT: ret2:
+; OPT-LABEL: ret2:
 ; OPT: jmp %o7+8
 ; OPT: or %g0, %o1, %o0
 define i64 @ret2(i64 %a, i64 %b) {
@@ -14,7 +14,7 @@ define i64 @ret2(i64 %a, i64 %b) {
 ; CHECK: shl_imm
 ; CHECK: sllx %i0, 7, %i0
 
-; OPT: shl_imm:
+; OPT-LABEL: shl_imm:
 ; OPT: jmp %o7+8
 ; OPT: sllx %o0, 7, %o0
 define i64 @shl_imm(i64 %a) {
@@ -25,7 +25,7 @@ define i64 @shl_imm(i64 %a) {
 ; CHECK: sra_reg
 ; CHECK: srax %i0, %i1, %i0
 
-; OPT: sra_reg:
+; OPT-LABEL: sra_reg:
 ; OPT: jmp %o7+8
 ; OPT: srax %o0, %o1, %o0
 define i64 @sra_reg(i64 %a, i64 %b) {
@@ -271,11 +271,11 @@ define double @bitcast_f64_i64(i64 %x) {
   ret double %y
 }
 
-; CHECK: store_zero:
+; CHECK-LABEL: store_zero:
 ; CHECK: stx %g0, [%i0]
 ; CHECK: stx %g0, [%i1+8]
 
-; OPT:  store_zero:
+; OPT-LABEL:  store_zero:
 ; OPT:  stx %g0, [%o0]
 ; OPT:  stx %g0, [%o1+8]
 define i64 @store_zero(i64* nocapture %a, i64* nocapture %b) {
diff --git a/test/CodeGen/SPARC/64cond.ll b/test/CodeGen/SPARC/64cond.ll
index a586bce..bdc5e70 100644
--- a/test/CodeGen/SPARC/64cond.ll
+++ b/test/CodeGen/SPARC/64cond.ll
@@ -102,7 +102,7 @@ entry:
 ; The MOVXCC instruction can't use %g0 for its tied operand.
 ; CHECK: select_consti64_xcc
 ; CHECK: cmp
-; CHECK: movg %xcc, 123, %i0
+; CHECK: movg %xcc, 123, %i{{[0-2]}}
 define i64 @select_consti64_xcc(i64 %x, i64 %y) {
 entry:
   %tobool = icmp sgt i64 %x, %y
diff --git a/test/CodeGen/SPARC/basictest.ll b/test/CodeGen/SPARC/basictest.ll
index ce60653..ba85825 100644
--- a/test/CodeGen/SPARC/basictest.ll
+++ b/test/CodeGen/SPARC/basictest.ll
@@ -3,7 +3,7 @@
 define i32 @test0(i32 %X) {
 	%tmp.1 = add i32 %X, 1
 	ret i32 %tmp.1
-; CHECK: test0:
+; CHECK-LABEL: test0:
 ; CHECK: add %o0, 1, %o0
 }
 
@@ -13,7 +13,7 @@ define i32 @test1(i32 %X, i32 %Y) {
         %A = xor i32 %X, %Y
         %B = xor i32 %A, -1
         ret i32 %B
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: xnor %o0, %o1, %o0
 }
 
@@ -21,11 +21,11 @@ define i32 @test2(i32 %X, i32 %Y) {
         %A = xor i32 %X, -1
         %B = xor i32 %A, %Y
         ret i32 %B
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: xnor %o0, %o1, %o0
 }
 
-; CHECK: store_zero:
+; CHECK-LABEL: store_zero:
 ; CHECK: st   %g0, [%o0]
 ; CHECK: st   %g0, [%o1+4]
 define i32 @store_zero(i32* %a, i32* %b) {
diff --git a/test/CodeGen/SPARC/blockaddr.ll b/test/CodeGen/SPARC/blockaddr.ll
index a7e85fe..c3d5270 100644
--- a/test/CodeGen/SPARC/blockaddr.ll
+++ b/test/CodeGen/SPARC/blockaddr.ll
@@ -15,13 +15,13 @@ entry:
   ret i8* %x
 }
 
-; abs32: func_block_addr:
+; abs32-LABEL: func_block_addr:
 ; abs32: sethi %hi([[BLK:.+]]), [[R:%[gilo][0-7]]]
 ; abs32: call dummy
 ; abs32: add  [[R]], %lo([[BLK]]), %o0
 ; abs32: jmp %o0
 
-; abs44: func_block_addr:
+; abs44-LABEL: func_block_addr:
 ; abs44: sethi %h44([[BLK:.+]]), [[R:%[gilo][0-7]]]
 ; abs44: add [[R]], %m44([[BLK]]), [[R1:%[gilo][0-7]]]
 ; abs44: sllx [[R1]], 12, [[R2:%[gilo][0-7]]]
@@ -29,7 +29,7 @@ entry:
 ; abs44: add [[R2]], %l44([[BLK]]), %o0
 ; abs44: jmp %o0
 
-; abs64: func_block_addr:
+; abs64-LABEL: func_block_addr:
 ; abs64: sethi %hi([[BLK:.+]]), [[R:%[gilo][0-7]]]
 ; abs64: add [[R]], %lo([[BLK]]), [[R1:%[gilo][0-7]]]
 ; abs64: sethi %hh([[BLK]]), [[R2:%[gilo][0-7]]]
diff --git a/test/CodeGen/SPARC/float.ll b/test/CodeGen/SPARC/float.ll
index ab46fb3..8dfd371 100644
--- a/test/CodeGen/SPARC/float.ll
+++ b/test/CodeGen/SPARC/float.ll
@@ -3,17 +3,17 @@
 ; RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9
 
 
-; V8:     test_neg:
+; V8-LABEL:     test_neg:
 ; V8:     call get_double
 ; V8:     fnegs %f0, %f0
 
-; V8-UNOPT:     test_neg:
+; V8-UNOPT-LABEL:     test_neg:
 ; V8-UNOPT:     fnegs
 ; V8-UNOPT:     ! implicit-def
 ; V8-UNOPT:     fmovs {{.+}}, %f0
 ; V8-UNOPT:     fmovs {{.+}}, %f1
 
-; V9:     test_neg:
+; V9-LABEL:     test_neg:
 ; V9:     fnegd %f0, %f0
 
 define double @test_neg() {
@@ -23,16 +23,16 @@ entry:
   ret double %1
 }
 
-; V8:     test_abs:
+; V8-LABEL:     test_abs:
 ; V8:     fabss %f0, %f0
 
-; V8-UNOPT:     test_abs:
+; V8-UNOPT-LABEL:     test_abs:
 ; V8-UNOPT:     fabss
 ; V8-UNOPT:     ! implicit-def
 ; V8-UNOPT:     fmovs {{.+}}, %f0
 ; V8-UNOPT:     fmovs {{.+}}, %f1
 
-; V9:     test_abs:
+; V9-LABEL:     test_abs:
 ; V9:     fabsd %f0, %f0
 
 define double @test_abs() {
diff --git a/test/CodeGen/SPARC/leafproc.ll b/test/CodeGen/SPARC/leafproc.ll
index a162df1..0a7ae08 100644
--- a/test/CodeGen/SPARC/leafproc.ll
+++ b/test/CodeGen/SPARC/leafproc.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=sparc -disable-sparc-leaf-proc=0 < %s | FileCheck %s
 
-; CHECK:      func_nobody:
+; CHECK-LABEL:      func_nobody:
 ; CHECK:      jmp %o7+8
 ; CHECK-NEXT: nop
 define void @func_nobody() {
@@ -9,7 +9,7 @@ entry:
 }
 
 
-; CHECK:      return_int_const:
+; CHECK-LABEL:      return_int_const:
 ; CHECK:      jmp %o7+8
 ; CHECK-NEXT: or %g0, 1729, %o0
 define i32 @return_int_const() {
@@ -17,7 +17,7 @@ entry:
   ret i32 1729
 }
 
-; CHECK:      return_double_const:
+; CHECK-LABEL:      return_double_const:
 ; CHECK:      sethi
 ; CHECK:      jmp %o7+8
 ; CHECK-NEXT: ldd {{.*}}, %f0
@@ -27,7 +27,7 @@ entry:
   ret double 0.000000e+00
 }
 
-; CHECK:      leaf_proc_with_args:
+; CHECK-LABEL:      leaf_proc_with_args:
 ; CHECK:      add {{%o[0-1]}}, {{%o[0-1]}}, [[R:%[go][0-7]]]
 ; CHECK:      jmp %o7+8
 ; CHECK-NEXT: add [[R]], %o2, %o0
@@ -39,7 +39,7 @@ entry:
   ret i32 %1
 }
 
-; CHECK:     leaf_proc_with_args_in_stack:
+; CHECK-LABEL:     leaf_proc_with_args_in_stack:
 ; CHECK-DAG: ld [%sp+92], {{%[go][0-7]}}
 ; CHECK-DAG: ld [%sp+96], {{%[go][0-7]}}
 ; CHECK:     jmp %o7+8
@@ -56,7 +56,7 @@ entry:
   ret i32 %6
 }
 
-; CHECK:      leaf_proc_with_local_array:
+; CHECK-LABEL:      leaf_proc_with_local_array:
 ; CHECK:      add %sp, -104, %sp
 ; CHECK:      or %g0, 1, [[R1:%[go][0-7]]]
 ; CHECK:      st [[R1]], [%sp+96]
diff --git a/test/CodeGen/SystemZ/Large/branch-range-07.py b/test/CodeGen/SystemZ/Large/branch-range-07.py
new file mode 100644
index 0000000..90c4420
--- /dev/null
+++ b/test/CodeGen/SystemZ/Large/branch-range-07.py
@@ -0,0 +1,68 @@
+# Test 32-bit BRANCH RELATIVE ON COUNT in cases where some branches are out
+# of range.
+# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
+
+# Construct:
+#
+# loopN:
+#   load of countN
+#   ...
+# loop0:
+#   0xffd8 bytes, from MVIY instructions
+#   conditional branch to main
+# after0:
+#   ...
+#   decrement of countN
+#   conditional branch to loopN
+# afterN:
+#
+# Each load occupies 4 bytes.  Each decrement and branch occupies 4
+# bytes if BRCT can be used, otherwise it occupies 10 bytes (AHI + BRCL).
+# This means that loop 6 contains 5 * 4 + 0xffd8 + 5 * 4 == 0x10000 bytes
+# and is therefore (just) in range.  Loop 7 is out of range.
+#
+# CHECK: brct {{%r[0-9]+}}
+# CHECK: brct {{%r[0-9]+}}
+# CHECK: brct {{%r[0-9]+}}
+# CHECK: brct {{%r[0-9]+}}
+# CHECK: brct {{%r[0-9]+}}
+# CHECK: brct {{%r[0-9]+}}
+# CHECK: ahi {{%r[0-9]+}}, -1
+# CHECK: jglh
+# CHECK: ahi {{%r[0-9]+}}, -1
+# CHECK: jglh
+
+branch_blocks = 8
+main_size = 0xffd8
+
+print 'define void @f1(i8 *%base, i32 *%counts) {'
+print 'entry:'
+
+for i in xrange(branch_blocks - 1, -1, -1):
+    print '  %%countptr%d = getelementptr i32 *%%counts, i64 %d' % (i, i)
+    print '  %%initcount%d = load i32 *%%countptr%d' % (i, i)
+    print '  br label %%loop%d' % i
+    
+    print 'loop%d:' % i
+    block1 = 'entry' if i == branch_blocks - 1 else 'loop%d' % (i + 1)
+    block2 = 'loop0' if i == 0 else 'after%d' % (i - 1)
+    print ('  %%count%d = phi i32 [ %%initcount%d, %%%s ],'
+           ' [ %%nextcount%d, %%%s ]' % (i, i, block1, i, block2))
+
+a, b = 1, 1
+for i in xrange(0, main_size, 6):
+    a, b = b, a + b
+    offset = 4096 + b % 500000
+    value = a % 256
+    print '  %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset)
+    print '  store volatile i8 %d, i8 *%%ptr%d' % (value, i)
+
+for i in xrange(branch_blocks):
+    print '  %%nextcount%d = add i32 %%count%d, -1' % (i, i)
+    print '  %%test%d = icmp ne i32 %%nextcount%d, 0' % (i, i)
+    print '  br i1 %%test%d, label %%loop%d, label %%after%d' % (i, i, i)
+    print ''
+    print 'after%d:' % i
+
+print '  ret void'
+print '}'
diff --git a/test/CodeGen/SystemZ/Large/branch-range-08.py b/test/CodeGen/SystemZ/Large/branch-range-08.py
new file mode 100644
index 0000000..ac1b137
--- /dev/null
+++ b/test/CodeGen/SystemZ/Large/branch-range-08.py
@@ -0,0 +1,69 @@
+# Test 64-bit BRANCH RELATIVE ON COUNT in cases where some branches are out
+# of range.
+# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
+
+# Construct:
+#
+# loopN:
+#   load of countN
+#   ...
+# loop0:
+#   0xffd8 bytes, from MVIY instructions
+#   conditional branch to main
+# after0:
+#   ...
+#   decrement of countN
+#   conditional branch to loopN
+# afterN:
+#
+# Each load occupies 6 bytes.  Each decrement and branch occupies 4
+# bytes if BRCTG can be used, otherwise it occupies 10 bytes (AGHI + BRCL).
+# This means that loop 5 contains 4 * 6 + 0xffd8 + 4 * 4 == 0x10000 bytes
+# and is therefore (just) in range.  Loop 6 is out of range.
+#
+# CHECK: brctg {{%r[0-9]+}}
+# CHECK: brctg {{%r[0-9]+}}
+# CHECK: brctg {{%r[0-9]+}}
+# CHECK: brctg {{%r[0-9]+}}
+# CHECK: brctg {{%r[0-9]+}}
+# CHECK: aghi {{%r[0-9]+}}, -1
+# CHECK: jglh
+# CHECK: aghi {{%r[0-9]+}}, -1
+# CHECK: jglh
+# CHECK: aghi {{%r[0-9]+}}, -1
+# CHECK: jglh
+
+branch_blocks = 8
+main_size = 0xffd8
+
+print 'define void @f1(i8 *%base, i64 *%counts) {'
+print 'entry:'
+
+for i in xrange(branch_blocks - 1, -1, -1):
+    print '  %%countptr%d = getelementptr i64 *%%counts, i64 %d' % (i, i)
+    print '  %%initcount%d = load i64 *%%countptr%d' % (i, i)
+    print '  br label %%loop%d' % i
+    
+    print 'loop%d:' % i
+    block1 = 'entry' if i == branch_blocks - 1 else 'loop%d' % (i + 1)
+    block2 = 'loop0' if i == 0 else 'after%d' % (i - 1)
+    print ('  %%count%d = phi i64 [ %%initcount%d, %%%s ],'
+           ' [ %%nextcount%d, %%%s ]' % (i, i, block1, i, block2))
+
+a, b = 1, 1
+for i in xrange(0, main_size, 6):
+    a, b = b, a + b
+    offset = 4096 + b % 500000
+    value = a % 256
+    print '  %%ptr%d = getelementptr i8 *%%base, i64 %d' % (i, offset)
+    print '  store volatile i8 %d, i8 *%%ptr%d' % (value, i)
+
+for i in xrange(branch_blocks):
+    print '  %%nextcount%d = add i64 %%count%d, -1' % (i, i)
+    print '  %%test%d = icmp ne i64 %%nextcount%d, 0' % (i, i)
+    print '  br i1 %%test%d, label %%loop%d, label %%after%d' % (i, i, i)
+    print ''
+    print 'after%d:' % i
+
+print '  ret void'
+print '}'
diff --git a/test/CodeGen/SystemZ/Large/spill-01.py b/test/CodeGen/SystemZ/Large/spill-01.py
new file mode 100644
index 0000000..3c1d0b6
--- /dev/null
+++ b/test/CodeGen/SystemZ/Large/spill-01.py
@@ -0,0 +1,40 @@
+# Test cases where MVC is used for spill slots that end up being out of range.
+# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
+
+# There are 8 usable call-saved GPRs, two of which are needed for the base
+# registers.  The first 160 bytes of the frame are needed for the ABI
+# call frame, and a further 8 bytes are needed for the emergency spill slot.
+# That means we will have at least one out-of-range slot if:
+#
+#    count == (4096 - 168) / 8 + 6 + 1 == 498
+#
+# Add in some extra room and check both %r15+4096 (the first out-of-range slot)
+# and %r15+4104.
+#
+# CHECK: f1:
+# CHECK: lay [[REG:%r[0-5]]], 4096(%r15)
+# CHECK: mvc 0(8,[[REG]]), {{[0-9]+}}({{%r[0-9]+}})
+# CHECK: brasl %r14, foo@PLT
+# CHECK: lay [[REG:%r[0-5]]], 4096(%r15)
+# CHECK: mvc {{[0-9]+}}(8,{{%r[0-9]+}}), 8([[REG]])
+# CHECK: br %r14
+count = 500
+
+print 'declare void @foo()'
+print ''
+print 'define void @f1(i64 *%base0, i64 *%base1) {'
+
+for i in range(count):
+    print '  %%ptr%d = getelementptr i64 *%%base%d, i64 %d' % (i, i % 2, i / 2)
+    print '  %%val%d = load i64 *%%ptr%d' % (i, i)
+    print ''
+
+print '  call void @foo()'
+print ''
+
+for i in range(count):
+    print '  store i64 %%val%d, i64 *%%ptr%d' % (i, i)
+
+print ''
+print '  ret void'
+print '}'
diff --git a/test/CodeGen/SystemZ/Large/spill-02.py b/test/CodeGen/SystemZ/Large/spill-02.py
new file mode 100644
index 0000000..0aa43d1
--- /dev/null
+++ b/test/CodeGen/SystemZ/Large/spill-02.py
@@ -0,0 +1,73 @@
+# Test cases where we spill from one frame index to another, both of which
+# are out of range of MVC, and both of which need emergency spill slots.
+# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
+
+# CHECK: f1:
+# CHECK: %fallthru
+# CHECK-DAG: stg [[REG1:%r[0-9]+]], 8168(%r15)
+# CHECK-DAG: stg [[REG2:%r[0-9]+]], 8176(%r15)
+# CHECK-DAG: lay [[REG3:%r[0-9]+]], 8192(%r15)
+# CHECK-DAG: lay [[REG4:%r[0-9]+]], 4096(%r15)
+# CHECK: mvc 0(8,[[REG3]]), 4088([[REG4]])
+# CHECK-DAG: lg [[REG1]], 8168(%r15)
+# CHECK-DAG: lg [[REG2]], 8176(%r15)
+# CHECK: %skip
+# CHECK: br %r14
+
+# Arrange for %foo's spill slot to be at 8184(%r15) and the alloca area to be at
+# 8192(%r15).  The two emergency spill slots live below that, so this requires
+# the first 8168 bytes to be used for the call.  160 of these bytes are
+# allocated for the ABI frame.  There are also 5 argument registers, one of
+# which is used as a base pointer.
+args = (8168 - 160) / 8 + (5 - 1)
+
+print 'declare i64 *@foo(i64 *%s)' % (', i64' * args)
+print 'declare void @bar(i64 *)'
+print ''
+print 'define i64 @f1(i64 %foo) {'
+print 'entry:'
+
+# Make the allocation big, so that it goes at the top of the frame.
+print '  %array = alloca [1000 x i64]'
+print '  %area = getelementptr [1000 x i64] *%array, i64 0, i64 0'
+print '  %%base = call i64 *@foo(i64 *%%area%s)' % (', i64 0' * args)
+print ''
+
+# Make sure all GPRs are used.  One is needed for the stack pointer and
+# another for %base, so we need 14 live values.
+count = 14
+for i in range(count):
+    print '  %%ptr%d = getelementptr i64 *%%base, i64 %d' % (i, i / 2)
+    print '  %%val%d = load volatile i64 *%%ptr%d' % (i, i)
+    print ''
+
+# Encourage the register allocator to give preference to these %vals
+# by using them several times.
+for j in range(4):
+    for i in range(count):
+        print '  store volatile i64 %%val%d, i64 *%%ptr%d' % (i, i)
+    print ''
+
+# Copy the incoming argument, which we expect to be spilled, to the frame
+# index for the alloca area.  Also throw in a volatile store, so that this
+# block cannot be reordered with the surrounding code.
+print '  %cond = icmp eq i64 %val0, %val1'
+print '  br i1 %cond, label %skip, label %fallthru'
+print ''
+print 'fallthru:'
+print '  store i64 %foo, i64 *%area'
+print '  store volatile i64 %val0, i64 *%ptr0'
+print '  br label %skip'
+print ''
+print 'skip:'
+
+# Use each %val a few more times to emphasise the point, and to make sure
+# that they are live across the store of %foo.
+for j in range(4):
+    for i in range(count):
+        print '  store volatile i64 %%val%d, i64 *%%ptr%d' % (i, i)
+    print ''
+
+print '  call void @bar(i64 *%area)'
+print '  ret i64 0'
+print '}'
diff --git a/test/CodeGen/SystemZ/addr-01.ll b/test/CodeGen/SystemZ/addr-01.ll
index c125ffa..d0960cd 100644
--- a/test/CodeGen/SystemZ/addr-01.ll
+++ b/test/CodeGen/SystemZ/addr-01.ll
@@ -5,7 +5,7 @@
 
 ; A simple index address.
 define void @f1(i64 %addr, i64 %index) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lb %r0, 0(%r3,%r2)
 ; CHECK: br %r14
   %add = add i64 %addr, %index
@@ -16,7 +16,7 @@ define void @f1(i64 %addr, i64 %index) {
 
 ; An address with an index and a displacement (order 1).
 define void @f2(i64 %addr, i64 %index) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lb %r0, 100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, %index
@@ -28,7 +28,7 @@ define void @f2(i64 %addr, i64 %index) {
 
 ; An address with an index and a displacement (order 2).
 define void @f3(i64 %addr, i64 %index) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lb %r0, 100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, 100
@@ -40,7 +40,7 @@ define void @f3(i64 %addr, i64 %index) {
 
 ; An address with an index and a subtracted displacement (order 1).
 define void @f4(i64 %addr, i64 %index) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lb %r0, -100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, %index
@@ -52,7 +52,7 @@ define void @f4(i64 %addr, i64 %index) {
 
 ; An address with an index and a subtracted displacement (order 2).
 define void @f5(i64 %addr, i64 %index) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lb %r0, -100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = sub i64 %addr, 100
@@ -64,7 +64,7 @@ define void @f5(i64 %addr, i64 %index) {
 
 ; An address with an index and a displacement added using OR.
 define void @f6(i64 %addr, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nill %r2, 65528
 ; CHECK: lb %r0, 6(%r3,%r2)
 ; CHECK: br %r14
@@ -78,7 +78,7 @@ define void @f6(i64 %addr, i64 %index) {
 
 ; Like f6, but without the masking.  This OR doesn't count as a displacement.
 define void @f7(i64 %addr, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oill %r2, 6
 ; CHECK: lb %r0, 0(%r3,%r2)
 ; CHECK: br %r14
@@ -92,7 +92,7 @@ define void @f7(i64 %addr, i64 %index) {
 ; Like f6, but with the OR applied after the index.  We don't know anything
 ; about the alignment of %add here.
 define void @f8(i64 %addr, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: nill %r2, 65528
 ; CHECK: agr %r2, %r3
 ; CHECK: oill %r2, 6
diff --git a/test/CodeGen/SystemZ/addr-02.ll b/test/CodeGen/SystemZ/addr-02.ll
index 6772c1d..56c4879 100644
--- a/test/CodeGen/SystemZ/addr-02.ll
+++ b/test/CodeGen/SystemZ/addr-02.ll
@@ -6,7 +6,7 @@
 
 ; A simple index address.
 define void @f1(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lb %r0, 0(%r3,%r2)
 ; CHECK: br %r14
   %add = add i64 %addr, %index
@@ -18,7 +18,7 @@ define void @f1(i64 %addr, i64 %index, i8 **%dst) {
 
 ; An address with an index and a displacement (order 1).
 define void @f2(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lb %r0, 100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, %index
@@ -31,7 +31,7 @@ define void @f2(i64 %addr, i64 %index, i8 **%dst) {
 
 ; An address with an index and a displacement (order 2).
 define void @f3(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lb %r0, 100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, 100
@@ -44,7 +44,7 @@ define void @f3(i64 %addr, i64 %index, i8 **%dst) {
 
 ; An address with an index and a subtracted displacement (order 1).
 define void @f4(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lb %r0, -100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %addr, %index
@@ -57,7 +57,7 @@ define void @f4(i64 %addr, i64 %index, i8 **%dst) {
 
 ; An address with an index and a subtracted displacement (order 2).
 define void @f5(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lb %r0, -100(%r3,%r2)
 ; CHECK: br %r14
   %add1 = sub i64 %addr, 100
@@ -70,7 +70,7 @@ define void @f5(i64 %addr, i64 %index, i8 **%dst) {
 
 ; An address with an index and a displacement added using OR.
 define void @f6(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nill %r2, 65528
 ; CHECK: lb %r0, 6(%r3,%r2)
 ; CHECK: br %r14
@@ -85,7 +85,7 @@ define void @f6(i64 %addr, i64 %index, i8 **%dst) {
 
 ; Like f6, but without the masking.  This OR doesn't count as a displacement.
 define void @f7(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oill %r2, 6
 ; CHECK: lb %r0, 0(%r3,%r2)
 ; CHECK: br %r14
@@ -100,7 +100,7 @@ define void @f7(i64 %addr, i64 %index, i8 **%dst) {
 ; Like f6, but with the OR applied after the index.  We don't know anything
 ; about the alignment of %add here.
 define void @f8(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: nill %r2, 65528
 ; CHECK: agr %r2, %r3
 ; CHECK: oill %r2, 6
diff --git a/test/CodeGen/SystemZ/addr-03.ll b/test/CodeGen/SystemZ/addr-03.ll
index dbdb9f1..1146926 100644
--- a/test/CodeGen/SystemZ/addr-03.ll
+++ b/test/CodeGen/SystemZ/addr-03.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lb %r0, 0
 ; CHECK: br %r14
   %ptr = inttoptr i64 0 to i8 *
@@ -12,7 +12,7 @@ define void @f1() {
 }
 
 define void @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lb %r0, -524288
 ; CHECK: br %r14
   %ptr = inttoptr i64 -524288 to i8 *
@@ -21,7 +21,7 @@ define void @f2() {
 }
 
 define void @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: lb %r0, -524289
 ; CHECK: br %r14
   %ptr = inttoptr i64 -524289 to i8 *
@@ -30,7 +30,7 @@ define void @f3() {
 }
 
 define void @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lb %r0, 524287
 ; CHECK: br %r14
   %ptr = inttoptr i64 524287 to i8 *
@@ -39,7 +39,7 @@ define void @f4() {
 }
 
 define void @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: lb %r0, 524288
 ; CHECK: br %r14
   %ptr = inttoptr i64 524288 to i8 *
diff --git a/test/CodeGen/SystemZ/alloca-01.ll b/test/CodeGen/SystemZ/alloca-01.ll
index 1852c91..2ddefd7 100644
--- a/test/CodeGen/SystemZ/alloca-01.ll
+++ b/test/CodeGen/SystemZ/alloca-01.ll
@@ -1,8 +1,7 @@
 ; Test variable-sized allocas and addresses based on them in cases where
 ; stack arguments are needed.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK1
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK2
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-A
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-B
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-C
@@ -15,17 +14,6 @@ declare i64 @bar(i8 *%a, i8 *%b, i8 *%c, i8 *%d, i8 *%e, i64 %f, i64 %g)
 ; There are two stack arguments, so an offset of 160 + 2 * 8 == 176
 ; is added to the copy of %r15.
 define i64 @f1(i64 %length, i64 %index) {
-; The full allocation sequence is:
-;
-;    la %r0, 7(%r2)      1
-;    nill %r0, 0xfff8    1
-;    lgr %r1, %r15         2
-;    sgr %r1, %r0        1 2
-;    lgr %r15, %r1         2
-;
-; The third instruction does not depend on the first two, so check for
-; two fully-ordered sequences.
-;
 ; FIXME: a better sequence would be:
 ;
 ;    lgr %r1, %r15
@@ -33,38 +21,34 @@ define i64 @f1(i64 %length, i64 %index) {
 ;    nill %r1, 0xfff8
 ;    lgr %r15, %r1
 ;
-; CHECK1: f1:
-; CHECK1: la %r0, 7(%r2)
-; CHECK1: nill %r0, 65528
-; CHECK1: sgr %r1, %r0
-; CHECK1: lgr %r15, %r1
-;
-; CHECK2: f1:
-; CHECK2: lgr %r1, %r15
-; CHECK2: sgr %r1, %r0
-; CHECK2: lgr %r15, %r1
+; CHECK-LABEL: f1:
+; CHECK-DAG: la [[REG1:%r[0-5]]], 7(%r2)
+; CHECK-DAG: nill [[REG1]], 65528
+; CHECK-DAG: lgr [[REG2:%r[0-5]]], %r15
+; CHECK: sgr [[REG2]], [[REG1]]
+; CHECK: lgr %r15, [[REG2]]
 ;
-; CHECK-A: f1:
+; CHECK-A-LABEL: f1:
 ; CHECK-A: lgr %r15, %r1
 ; CHECK-A: la %r2, 176(%r1)
 ;
-; CHECK-B: f1:
+; CHECK-B-LABEL: f1:
 ; CHECK-B: lgr %r15, %r1
 ; CHECK-B: la %r3, 177(%r1)
 ;
-; CHECK-C: f1:
+; CHECK-C-LABEL: f1:
 ; CHECK-C: lgr %r15, %r1
 ; CHECK-C: la %r4, 4095({{%r3,%r1|%r1,%r3}})
 ;
-; CHECK-D: f1:
+; CHECK-D-LABEL: f1:
 ; CHECK-D: lgr %r15, %r1
 ; CHECK-D: lay %r5, 4096({{%r3,%r1|%r1,%r3}})
 ;
-; CHECK-E: f1:
+; CHECK-E-LABEL: f1:
 ; CHECK-E: lgr %r15, %r1
 ; CHECK-E: lay %r6, 4271({{%r3,%r1|%r1,%r3}})
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: lgr %r11, %r15
 ; CHECK-FP: lmg %r6, %r15, 224(%r11)
   %a = alloca i8, i64 %length
diff --git a/test/CodeGen/SystemZ/alloca-02.ll b/test/CodeGen/SystemZ/alloca-02.ll
index 41c987a..b6ed7f7 100644
--- a/test/CodeGen/SystemZ/alloca-02.ll
+++ b/test/CodeGen/SystemZ/alloca-02.ll
@@ -9,27 +9,27 @@
 declare i64 @bar(i8 *%a)
 
 define i64 @f1(i64 %length, i64 %index) {
-; CHECK-A: f1:
+; CHECK-A-LABEL: f1:
 ; CHECK-A: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-A: la %r2, 160([[ADDR]])
 ; CHECK-A: mvi 0(%r2), 0
 ;
-; CHECK-B: f1:
+; CHECK-B-LABEL: f1:
 ; CHECK-B: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-B: la %r2, 160([[ADDR]])
 ; CHECK-B: mvi 4095(%r2), 1
 ;
-; CHECK-C: f1:
+; CHECK-C-LABEL: f1:
 ; CHECK-C: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-C: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
 ; CHECK-C: mvi 0([[TMP]]), 2
 ;
-; CHECK-D: f1:
+; CHECK-D-LABEL: f1:
 ; CHECK-D: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-D: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
 ; CHECK-D: mvi 4095([[TMP]]), 3
 ;
-; CHECK-E: f1:
+; CHECK-E-LABEL: f1:
 ; CHECK-E: lgr %r15, [[ADDR:%r[1-5]]]
 ; CHECK-E: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
 ; CHECK-E: mviy 4096([[TMP]]), 4
diff --git a/test/CodeGen/SystemZ/and-01.ll b/test/CodeGen/SystemZ/and-01.ll
index 8dd106b..3b230ba 100644
--- a/test/CodeGen/SystemZ/and-01.ll
+++ b/test/CodeGen/SystemZ/and-01.ll
@@ -1,10 +1,13 @@
 ; Test 32-bit ANDs in which the second operand is variable.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i32 @foo()
 
 ; Check NR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: nr %r2, %r3
 ; CHECK: br %r14
   %and = and i32 %a, %b
@@ -13,7 +16,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the N range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: n %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -23,7 +26,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned N range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: n %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -34,7 +37,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use NY instead of N.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ny %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -45,7 +48,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned NY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ny %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -57,7 +60,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: n %r2, 0(%r3)
 ; CHECK: br %r14
@@ -69,7 +72,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned NY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ny %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -80,7 +83,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the NY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ny %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -92,7 +95,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: n %r2, 0(%r3)
 ; CHECK: br %r14
@@ -104,7 +107,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that N allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: n %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -117,7 +120,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that NY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: ny %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -127,3 +130,46 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
   %and = and i32 %a, %b
   ret i32 %and
 }
+
+; Check that ANDs of spilled values can use N rather than NR.
+define i32 @f12(i32 *%ptr0) {
+; CHECK-LABEL: f12:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: n %r2, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32 *%ptr0, i64 18
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+  %val9 = load i32 *%ptr9
+
+  %ret = call i32 @foo()
+
+  %and0 = and i32 %ret, %val0
+  %and1 = and i32 %and0, %val1
+  %and2 = and i32 %and1, %val2
+  %and3 = and i32 %and2, %val3
+  %and4 = and i32 %and3, %val4
+  %and5 = and i32 %and4, %val5
+  %and6 = and i32 %and5, %val6
+  %and7 = and i32 %and6, %val7
+  %and8 = and i32 %and7, %val8
+  %and9 = and i32 %and8, %val9
+
+  ret i32 %and9
+}
diff --git a/test/CodeGen/SystemZ/and-02.ll b/test/CodeGen/SystemZ/and-02.ll
index a0fff81..a7f08b7 100644
--- a/test/CodeGen/SystemZ/and-02.ll
+++ b/test/CodeGen/SystemZ/and-02.ll
@@ -1,93 +1,226 @@
 ; Test 32-bit ANDs in which the second operand is constant.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
 
-; Check the lowest useful NILF value.
+; ANDs with 1 can use NILF.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: nilf %r2, 1
 ; CHECK: br %r14
   %and = and i32 %a, 1
   ret i32 %and
 }
 
+; ...but RISBLG is available as a three-address form.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: risblg %r2, %r3, 31, 159, 0
+; CHECK: br %r14
+  %and = and i32 %b, 1
+  ret i32 %and
+}
+
+; ...same for 4.
+define i32 @f3(i32 %a, i32 %b) {
+; CHECK-LABEL: f3:
+; CHECK: risblg %r2, %r3, 29, 157, 0
+; CHECK: br %r14
+  %and = and i32 %b, 4
+  ret i32 %and
+}
+
+; ANDs with 5 must use NILF.
+define i32 @f4(i32 %a) {
+; CHECK-LABEL: f4:
+; CHECK: nilf %r2, 5
+; CHECK: br %r14
+  %and = and i32 %a, 5
+  ret i32 %and
+}
+
+; ...a single RISBLG isn't enough.
+define i32 @f5(i32 %a, i32 %b) {
+; CHECK-LABEL: f5:
+; CHECK-NOT: risb
+; CHECK: br %r14
+  %and = and i32 %b, 5
+  ret i32 %and
+}
+
 ; Check the highest 16-bit constant that must be handled by NILF.
-define i32 @f2(i32 %a) {
-; CHECK: f2:
+define i32 @f6(i32 %a) {
+; CHECK-LABEL: f6:
+; CHECK: nilf %r2, 65533
+; CHECK: br %r14
+  %and = and i32 %a, 65533
+  ret i32 %and
+}
+
+; ...a single RISBLG isn't enough.
+define i32 @f7(i32 %a, i32 %b) {
+; CHECK-LABEL: f7:
+; CHECK-NOT: risb
+; CHECK: br %r14
+  %and = and i32 %b, 65533
+  ret i32 %and
+}
+
+; Check the next highest value, which can use NILF.
+define i32 @f8(i32 %a) {
+; CHECK-LABEL: f8:
 ; CHECK: nilf %r2, 65534
 ; CHECK: br %r14
   %and = and i32 %a, 65534
   ret i32 %and
 }
 
+; ...although the three-address case should use RISBLG.
+define i32 @f9(i32 %a, i32 %b) {
+; CHECK-LABEL: f9:
+; CHECK: risblg %r2, %r3, 16, 158, 0
+; CHECK: br %r14
+  %and = and i32 %b, 65534
+  ret i32 %and
+}
+
 ; ANDs of 0xffff are zero extensions from i16.
-define i32 @f3(i32 %a) {
-; CHECK: f3:
-; CHECK: llhr %r2, %r2
+define i32 @f10(i32 %a, i32 %b) {
+; CHECK-LABEL: f10:
+; CHECK: llhr %r2, %r3
 ; CHECK: br %r14
-  %and = and i32 %a, 65535
+  %and = and i32 %b, 65535
   ret i32 %and
 }
 
 ; Check the next value up, which must again use NILF.
-define i32 @f4(i32 %a) {
-; CHECK: f4:
+define i32 @f11(i32 %a) {
+; CHECK-LABEL: f11:
 ; CHECK: nilf %r2, 65536
 ; CHECK: br %r14
   %and = and i32 %a, 65536
   ret i32 %and
 }
 
-; Check the lowest useful NILH value.  (LLHR is used instead of NILH of 0.)
-define i32 @f5(i32 %a) {
-; CHECK: f5:
+; ...but the three-address case can use RISBLG.
+define i32 @f12(i32 %a, i32 %b) {
+; CHECK-LABEL: f12:
+; CHECK: risblg %r2, %r3, 15, 143, 0
+; CHECK: br %r14
+  %and = and i32 %b, 65536
+  ret i32 %and
+}
+
+; Check the lowest useful NILH value.
+define i32 @f13(i32 %a) {
+; CHECK-LABEL: f13:
 ; CHECK: nilh %r2, 1
 ; CHECK: br %r14
   %and = and i32 %a, 131071
   ret i32 %and
 }
 
+; ...but RISBLG is OK in the three-address case.
+define i32 @f14(i32 %a, i32 %b) {
+; CHECK-LABEL: f14:
+; CHECK: risblg %r2, %r3, 15, 159, 0
+; CHECK: br %r14
+  %and = and i32 %b, 131071
+  ret i32 %and
+}
+
 ; Check the highest useful NILF value.
-define i32 @f6(i32 %a) {
-; CHECK: f6:
+define i32 @f15(i32 %a) {
+; CHECK-LABEL: f15:
 ; CHECK: nilf %r2, 4294901758
 ; CHECK: br %r14
   %and = and i32 %a, -65538
   ret i32 %and
 }
 
-; Check the highest useful NILH value, which is one up from the above.
-define i32 @f7(i32 %a) {
-; CHECK: f7:
+; Check the next value up, which is the highest useful NILH value.
+define i32 @f16(i32 %a) {
+; CHECK-LABEL: f16:
 ; CHECK: nilh %r2, 65534
 ; CHECK: br %r14
   %and = and i32 %a, -65537
   ret i32 %and
 }
 
-; Check the low end of the NILL range, which is one up again.
-define i32 @f8(i32 %a) {
-; CHECK: f8:
+; Check the next value up, which is the first useful NILL value.
+define i32 @f17(i32 %a) {
+; CHECK-LABEL: f17:
 ; CHECK: nill %r2, 0
 ; CHECK: br %r14
   %and = and i32 %a, -65536
   ret i32 %and
 }
 
-; Check the next value up.
-define i32 @f9(i32 %a) {
-; CHECK: f9:
+; ...although the three-address case should use RISBLG.
+define i32 @f18(i32 %a, i32 %b) {
+; CHECK-LABEL: f18:
+; CHECK: risblg %r2, %r3, 0, 143, 0
+; CHECK: br %r14
+  %and = and i32 %b, -65536
+  ret i32 %and
+}
+
+; Check the next value up again, which can still use NILL.
+define i32 @f19(i32 %a) {
+; CHECK-LABEL: f19:
 ; CHECK: nill %r2, 1
 ; CHECK: br %r14
   %and = and i32 %a, -65535
   ret i32 %and
 }
 
-; Check the highest useful NILL value.
-define i32 @f10(i32 %a) {
-; CHECK: f10:
+; Check the next value up again, which cannot use RISBLG.
+define i32 @f20(i32 %a, i32 %b) {
+; CHECK-LABEL: f20:
+; CHECK-NOT: risb
+; CHECK: br %r14
+  %and = and i32 %b, -65534
+  ret i32 %and
+}
+
+; Check the last useful mask, which can use NILL.
+define i32 @f21(i32 %a) {
+; CHECK-LABEL: f21:
 ; CHECK: nill %r2, 65534
 ; CHECK: br %r14
   %and = and i32 %a, -2
   ret i32 %and
 }
+
+; ...or RISBLG for the three-address case.
+define i32 @f22(i32 %a, i32 %b) {
+; CHECK-LABEL: f22:
+; CHECK: risblg %r2, %r3, 0, 158, 0
+; CHECK: br %r14
+  %and = and i32 %b, -2
+  ret i32 %and
+}
+
+; Test that RISBLG can be used when inserting a non-wraparound mask
+; into another register.
+define i64 @f23(i64 %a, i32 %b) {
+; CHECK-LABEL: f23:
+; CHECK: risblg %r2, %r3, 30, 158, 0
+; CHECK: br %r14
+  %and1 = and i64 %a, -4294967296
+  %and2 = and i32 %b, 2
+  %ext = zext i32 %and2 to i64
+  %or = or i64 %and1, %ext
+  ret i64 %or
+}
+
+; ...and when inserting a wrap-around mask.
+define i64 @f24(i64 %a, i32 %b) {
+; CHECK-LABEL: f24:
+; CHECK: risblg %r2, %r3, 30, 156
+; CHECK: br %r14
+  %and1 = and i64 %a, -4294967296
+  %and2 = and i32 %b, -5
+  %ext = zext i32 %and2 to i64
+  %or = or i64 %and1, %ext
+  ret i64 %or
+}
diff --git a/test/CodeGen/SystemZ/and-03.ll b/test/CodeGen/SystemZ/and-03.ll
index 3fe8d3c..a0560d4 100644
--- a/test/CodeGen/SystemZ/and-03.ll
+++ b/test/CodeGen/SystemZ/and-03.ll
@@ -1,10 +1,13 @@
 ; Test 64-bit ANDs in which the second operand is variable.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i64 @foo()
 
 ; Check NGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ngr %r2, %r3
 ; CHECK: br %r14
   %and = and i64 %a, %b
@@ -13,7 +16,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check NG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ng %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -23,7 +26,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned NG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ng %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -35,7 +38,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ng %r2, 0(%r3)
 ; CHECK: br %r14
@@ -47,7 +50,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned NG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ng %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -58,7 +61,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the NG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ng %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -70,7 +73,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: ng %r2, 0(%r3)
 ; CHECK: br %r14
@@ -82,7 +85,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that NG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ng %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -92,3 +95,46 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %and = and i64 %a, %b
   ret i64 %and
 }
+
+; Check that ANDs of spilled values can use NG rather than NGR.
+define i64 @f9(i64 *%ptr0) {
+; CHECK-LABEL: f9:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: ng %r2, 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64 *%ptr0, i64 18
+
+  %val0 = load i64 *%ptr0
+  %val1 = load i64 *%ptr1
+  %val2 = load i64 *%ptr2
+  %val3 = load i64 *%ptr3
+  %val4 = load i64 *%ptr4
+  %val5 = load i64 *%ptr5
+  %val6 = load i64 *%ptr6
+  %val7 = load i64 *%ptr7
+  %val8 = load i64 *%ptr8
+  %val9 = load i64 *%ptr9
+
+  %ret = call i64 @foo()
+
+  %and0 = and i64 %ret, %val0
+  %and1 = and i64 %and0, %val1
+  %and2 = and i64 %and1, %val2
+  %and3 = and i64 %and2, %val3
+  %and4 = and i64 %and3, %val4
+  %and5 = and i64 %and4, %val5
+  %and6 = and i64 %and5, %val6
+  %and7 = and i64 %and6, %val7
+  %and8 = and i64 %and7, %val8
+  %and9 = and i64 %and8, %val9
+
+  ret i64 %and9
+}
diff --git a/test/CodeGen/SystemZ/and-04.ll b/test/CodeGen/SystemZ/and-04.ll
index 62def60..efb21f3 100644
--- a/test/CodeGen/SystemZ/and-04.ll
+++ b/test/CodeGen/SystemZ/and-04.ll
@@ -2,13 +2,10 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-; There is no 64-bit AND instruction for a mask of 1.
-; FIXME: we ought to be able to require "ngr %r2, %r0", but at the moment,
-; two-address optimisations force "ngr %r0, %r2; lgr %r2, %r0" instead.
+; Use RISBG for a single bit.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
-; CHECK: lghi %r0, 1
-; CHECK: ngr
+; CHECK-LABEL: f1:
+; CHECK: risbg %r2, %r2, 63, 191, 0
 ; CHECK: br %r14
   %and = and i64 %a, 1
   ret i64 %and
@@ -16,165 +13,171 @@ define i64 @f1(i64 %a) {
 
 ; Likewise 0xfffe.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
-; CHECK: llill %r0, 65534
-; CHECK: ngr
+; CHECK-LABEL: f2:
+; CHECK: risbg %r2, %r2, 48, 190, 0
 ; CHECK: br %r14
   %and = and i64 %a, 65534
   ret i64 %and
 }
 
 ; ...but 0xffff is a 16-bit zero extension.
-define i64 @f3(i64 %a) {
-; CHECK: f3:
-; CHECK: llghr %r2, %r2
+define i64 @f3(i64 %a, i64 %b) {
+; CHECK-LABEL: f3:
+; CHECK: llghr %r2, %r3
 ; CHECK: br %r14
-  %and = and i64 %a, 65535
+  %and = and i64 %b, 65535
   ret i64 %and
 }
 
-; Check the next value up, which again has no dedicated instruction.
+; Check the next value up, which can again use RISBG.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
-; CHECK: llilh %r0, 1
-; CHECK: ngr
+; CHECK-LABEL: f4:
+; CHECK: risbg %r2, %r2, 47, 175, 0
 ; CHECK: br %r14
   %and = and i64 %a, 65536
   ret i64 %and
 }
 
-; Check 0xfffffffe.
+; Check 0xfffffffe, which can also use RISBG.
 define i64 @f5(i64 %a) {
-; CHECK: f5:
-; CHECK: lilf %r0, 4294967294
-; CHECK: ngr
+; CHECK-LABEL: f5:
+; CHECK: risbg %r2, %r2, 32, 190, 0
 ; CHECK: br %r14
   %and = and i64 %a, 4294967294
   ret i64 %and
 }
 
 ; Check the next value up, which is a 32-bit zero extension.
-define i64 @f6(i64 %a) {
-; CHECK: f6:
-; CHECK: llgfr %r2, %r2
+define i64 @f6(i64 %a, i64 %b) {
+; CHECK-LABEL: f6:
+; CHECK: llgfr %r2, %r3
 ; CHECK: br %r14
-  %and = and i64 %a, 4294967295
+  %and = and i64 %b, 4294967295
   ret i64 %and
 }
 
 ; Check the lowest useful NIHF value (0x00000001_ffffffff).
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: nihf %r2, 1
 ; CHECK: br %r14
   %and = and i64 %a, 8589934591
   ret i64 %and
 }
 
-; Check the low end of the NIHH range (0x0000ffff_ffffffff).
-define i64 @f8(i64 %a) {
-; CHECK: f8:
-; CHECK: nihh %r2, 0
+; ...but RISBG can be used if a three-address form is useful.
+define i64 @f8(i64 %a, i64 %b) {
+; CHECK-LABEL: f8:
+; CHECK: risbg %r2, %r3, 31, 191, 0
 ; CHECK: br %r14
-  %and = and i64 %a, 281474976710655
+  %and = and i64 %b, 8589934591
   ret i64 %and
 }
 
-; Check the highest useful NIHH value (0xfffeffff_ffffffff).
+; Check the lowest NIHH value outside the RISBG range (0x0002ffff_ffffffff).
 define i64 @f9(i64 %a) {
-; CHECK: f9:
-; CHECK: nihh %r2, 65534
+; CHECK-LABEL: f9:
+; CHECK: nihh %r2, 2
 ; CHECK: br %r14
-  %and = and i64 %a, -281474976710657
+  %and = and i64 %a, 844424930131967
   ret i64 %and
 }
 
-; Check the highest useful NIHF value (0xfffefffe_ffffffff).
+; Check the highest NIHH value outside the RISBG range (0xfffaffff_ffffffff).
 define i64 @f10(i64 %a) {
-; CHECK: f10:
-; CHECK: nihf %r2, 4294901758
+; CHECK-LABEL: f10:
+; CHECK: nihh %r2, 65530
 ; CHECK: br %r14
-  %and = and i64 %a, -281479271677953
+  %and = and i64 %a, -1407374883553281
   ret i64 %and
 }
 
-; Check the low end of the NIHL range (0xffff0000_ffffffff).
+; Check the highest useful NIHF value (0xfffefffe_ffffffff).
 define i64 @f11(i64 %a) {
-; CHECK: f11:
-; CHECK: nihl %r2, 0
+; CHECK-LABEL: f11:
+; CHECK: nihf %r2, 4294901758
 ; CHECK: br %r14
-  %and = and i64 %a, -281470681743361
+  %and = and i64 %a, -281479271677953
   ret i64 %and
 }
 
-; Check the highest useful NIHL value (0xfffffffe_ffffffff).
+; Check the lowest NIHL value outside the RISBG range (0xffff0002_ffffffff).
 define i64 @f12(i64 %a) {
-; CHECK: f12:
-; CHECK: nihl %r2, 65534
+; CHECK-LABEL: f12:
+; CHECK: nihl %r2, 2
 ; CHECK: br %r14
-  %and = and i64 %a, -4294967297
+  %and = and i64 %a, -281462091808769
   ret i64 %and
 }
 
-; Check the low end of the NILF range (0xffffffff_00000000).
+; Check the highest NIHL value outside the RISBG range (0xfffffffa_ffffffff).
 define i64 @f13(i64 %a) {
-; CHECK: f13:
-; CHECK: nilf %r2, 0
+; CHECK-LABEL: f13:
+; CHECK: nihl %r2, 65530
 ; CHECK: br %r14
-  %and = and i64 %a, -4294967296
+  %and = and i64 %a, -21474836481
   ret i64 %and
 }
 
-; Check the low end of the NILH range (0xffffffff_0000ffff).
+; Check the lowest NILF value outside the RISBG range (0xffffffff_00000002).
 define i64 @f14(i64 %a) {
-; CHECK: f14:
-; CHECK: nilh %r2, 0
+; CHECK-LABEL: f14:
+; CHECK: nilf %r2, 2
 ; CHECK: br %r14
-  %and = and i64 %a, -4294901761
+  %and = and i64 %a, -4294967294
   ret i64 %and
 }
 
-; Check the next value up, which must use NILF.
+; Check the lowest NILH value outside the RISBG range (0xffffffff_0002ffff).
 define i64 @f15(i64 %a) {
-; CHECK: f15:
-; CHECK: nilf %r2, 65536
+; CHECK-LABEL: f15:
+; CHECK: nilh %r2, 2
 ; CHECK: br %r14
-  %and = and i64 %a, -4294901760
+  %and = and i64 %a, -4294770689
   ret i64 %and
 }
 
-; Check the maximum useful NILF value (0xffffffff_fffefffe).
+; Check the next value up, which must use NILF.
 define i64 @f16(i64 %a) {
-; CHECK: f16:
-; CHECK: nilf %r2, 4294901758
+; CHECK-LABEL: f16:
+; CHECK: nilf %r2, 196608
 ; CHECK: br %r14
-  %and = and i64 %a, -65538
+  %and = and i64 %a, -4294770688
   ret i64 %and
 }
 
-; Check the highest useful NILH value, which is one greater than the above.
+; Check the highest NILH value outside the RISBG range (0xffffffff_fffaffff).
 define i64 @f17(i64 %a) {
-; CHECK: f17:
-; CHECK: nilh %r2, 65534
+; CHECK-LABEL: f17:
+; CHECK: nilh %r2, 65530
 ; CHECK: br %r14
-  %and = and i64 %a, -65537
+  %and = and i64 %a, -327681
   ret i64 %and
 }
 
-; Check the low end of the NILL range, which is one greater again.
+; Check the maximum useful NILF value (0xffffffff_fffefffe).
 define i64 @f18(i64 %a) {
-; CHECK: f18:
-; CHECK: nill %r2, 0
+; CHECK-LABEL: f18:
+; CHECK: nilf %r2, 4294901758
 ; CHECK: br %r14
-  %and = and i64 %a, -65536
+  %and = and i64 %a, -65538
   ret i64 %and
 }
 
-; Check the highest useful NILL value.
+; Check the lowest NILL value outside the RISBG range (0xffffffff_ffff0002).
 define i64 @f19(i64 %a) {
-; CHECK: f19:
-; CHECK: nill %r2, 65534
+; CHECK-LABEL: f19:
+; CHECK: nill %r2, 2
+; CHECK: br %r14
+  %and = and i64 %a, -65534
+  ret i64 %and
+}
+
+; Check the highest NILL value outside the RISBG range.
+define i64 @f20(i64 %a) {
+; CHECK-LABEL: f20:
+; CHECK: nill %r2, 65530
 ; CHECK: br %r14
-  %and = and i64 %a, -2
+  %and = and i64 %a, -6
   ret i64 %and
 }
diff --git a/test/CodeGen/SystemZ/and-05.ll b/test/CodeGen/SystemZ/and-05.ll
index 4573911..dafd9d5 100644
--- a/test/CodeGen/SystemZ/and-05.ll
+++ b/test/CodeGen/SystemZ/and-05.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful constant, expressed as a signed integer.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ni 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a signed integer.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -26,7 +26,7 @@ define void @f2(i8 *%ptr) {
 
 ; Check the lowest useful constant, expressed as an unsigned integer.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ni 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -37,7 +37,7 @@ define void @f3(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a unsigned integer.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -48,7 +48,7 @@ define void @f4(i8 *%ptr) {
 
 ; Check the high end of the NI range.
 define void @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ni 4095(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -60,7 +60,7 @@ define void @f5(i8 *%src) {
 
 ; Check the next byte up, which should use NIY instead of NI.
 define void @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: niy 4096(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -72,7 +72,7 @@ define void @f6(i8 *%src) {
 
 ; Check the high end of the NIY range.
 define void @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: niy 524287(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -85,7 +85,7 @@ define void @f7(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, 524288
 ; CHECK: ni 0(%r2), 127
 ; CHECK: br %r14
@@ -98,7 +98,7 @@ define void @f8(i8 *%src) {
 
 ; Check the high end of the negative NIY range.
 define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: niy -1(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -110,7 +110,7 @@ define void @f9(i8 *%src) {
 
 ; Check the low end of the NIY range.
 define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: niy -524288(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -123,7 +123,7 @@ define void @f10(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r2, -524289
 ; CHECK: ni 0(%r2), 127
 ; CHECK: br %r14
@@ -136,7 +136,7 @@ define void @f11(i8 *%src) {
 
 ; Check that NI does not allow an index
 define void @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agr %r2, %r3
 ; CHECK: ni 4095(%r2), 127
 ; CHECK: br %r14
@@ -151,7 +151,7 @@ define void @f12(i64 %src, i64 %index) {
 
 ; Check that NIY does not allow an index
 define void @f13(i64 %src, i64 %index) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agr %r2, %r3
 ; CHECK: niy 4096(%r2), 127
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/and-06.ll b/test/CodeGen/SystemZ/and-06.ll
index bbb5e7b..f796618 100644
--- a/test/CodeGen/SystemZ/and-06.ll
+++ b/test/CodeGen/SystemZ/and-06.ll
@@ -5,7 +5,7 @@
 
 ; Zero extension to 32 bits, negative constant.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -18,7 +18,7 @@ define void @f1(i8 *%ptr) {
 
 ; Zero extension to 64 bits, negative constant.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -31,7 +31,7 @@ define void @f2(i8 *%ptr) {
 
 ; Zero extension to 32 bits, positive constant.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define void @f3(i8 *%ptr) {
 
 ; Zero extension to 64 bits, positive constant.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -57,7 +57,7 @@ define void @f4(i8 *%ptr) {
 
 ; Sign extension to 32 bits, negative constant.
 define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -70,7 +70,7 @@ define void @f5(i8 *%ptr) {
 
 ; Sign extension to 64 bits, negative constant.
 define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -83,7 +83,7 @@ define void @f6(i8 *%ptr) {
 
 ; Sign extension to 32 bits, positive constant.
 define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -96,7 +96,7 @@ define void @f7(i8 *%ptr) {
 
 ; Sign extension to 64 bits, positive constant.
 define void @f8(i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ni 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/and-07.ll b/test/CodeGen/SystemZ/and-07.ll
new file mode 100644
index 0000000..ad4c4af
--- /dev/null
+++ b/test/CodeGen/SystemZ/and-07.ll
@@ -0,0 +1,39 @@
+; Test the three-operand forms of AND.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check NRK.
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f1:
+; CHECK: nrk %r2, %r3, %r4
+; CHECK: br %r14
+  %and = and i32 %b, %c
+  ret i32 %and
+}
+
+; Check that we can still use NR in obvious cases.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: nr %r2, %r3
+; CHECK: br %r14
+  %and = and i32 %a, %b
+  ret i32 %and
+}
+
+; Check NGRK.
+define i64 @f3(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f3:
+; CHECK: ngrk %r2, %r3, %r4
+; CHECK: br %r14
+  %and = and i64 %b, %c
+  ret i64 %and
+}
+
+; Check that we can still use NGR in obvious cases.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: ngr %r2, %r3
+; CHECK: br %r14
+  %and = and i64 %a, %b
+  ret i64 %and
+}
diff --git a/test/CodeGen/SystemZ/args-01.ll b/test/CodeGen/SystemZ/args-01.ll
index a6b80c5..3105503 100644
--- a/test/CodeGen/SystemZ/args-01.ll
+++ b/test/CodeGen/SystemZ/args-01.ll
@@ -17,43 +17,42 @@ declare void @bar(i8, i16, i32, i64, float, double, fp128, i64,
 ; normally use %f0/%f2 as the first available 128-bit pair.  This choice
 ; is hard-coded in the FP128 tests.
 ;
-; The order of the CHECK-INT loads doesn't matter.  The same goes for the
-; CHECK_FP128-* stores and the CHECK-STACK stores.  It would be OK to reorder
+; The order of the CHECK-STACK stores doesn't matter.  It would be OK to reorder
 ; them in response to future code changes.
 define void @foo() {
-; CHECK-INT: foo:
-; CHECK-INT: lhi %r2, 1
-; CHECK-INT: lhi %r3, 2
-; CHECK-INT: lhi %r4, 3
-; CHECK-INT: lghi %r5, 4
-; CHECK-INT: la %r6, {{224|240}}(%r15)
+; CHECK-INT-LABEL: foo:
+; CHECK-INT-DAG: lhi %r2, 1
+; CHECK-INT-DAG: lhi %r3, 2
+; CHECK-INT-DAG: lhi %r4, 3
+; CHECK-INT-DAG: lghi %r5, 4
+; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
 ; CHECK-INT: brasl %r14, bar@PLT
 ;
-; CHECK-FLOAT: foo:
+; CHECK-FLOAT-LABEL: foo:
 ; CHECK-FLOAT: lzer %f0
 ; CHECK-FLOAT: lcebr %f4, %f0
 ; CHECK-FLOAT: brasl %r14, bar@PLT
 ;
-; CHECK-DOUBLE: foo:
+; CHECK-DOUBLE-LABEL: foo:
 ; CHECK-DOUBLE: lzdr %f2
 ; CHECK-DOUBLE: lcdbr %f6, %f2
 ; CHECK-DOUBLE: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-1: foo:
+; CHECK-FP128-1-LABEL: foo:
 ; CHECK-FP128-1: aghi %r15, -256
 ; CHECK-FP128-1: lzxr %f0
-; CHECK-FP128-1: std %f0, 224(%r15)
-; CHECK-FP128-1: std %f2, 232(%r15)
+; CHECK-FP128-1-DAG: std %f0, 224(%r15)
+; CHECK-FP128-1-DAG: std %f2, 232(%r15)
 ; CHECK-FP128-1: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-2: foo:
+; CHECK-FP128-2-LABEL: foo:
 ; CHECK-FP128-2: aghi %r15, -256
 ; CHECK-FP128-2: lzxr %f0
-; CHECK-FP128-2: std %f0, 240(%r15)
-; CHECK-FP128-2: std %f2, 248(%r15)
+; CHECK-FP128-2-DAG: std %f0, 240(%r15)
+; CHECK-FP128-2-DAG: std %f2, 248(%r15)
 ; CHECK-FP128-2: brasl %r14, bar@PLT
 ;
-; CHECK-STACK: foo:
+; CHECK-STACK-LABEL: foo:
 ; CHECK-STACK: aghi %r15, -256
 ; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15)
 ; CHECK-STACK: stg [[REGISTER]], 216(%r15)
diff --git a/test/CodeGen/SystemZ/args-02.ll b/test/CodeGen/SystemZ/args-02.ll
index 9ea111c..8686df8 100644
--- a/test/CodeGen/SystemZ/args-02.ll
+++ b/test/CodeGen/SystemZ/args-02.ll
@@ -18,43 +18,42 @@ declare void @bar(i8 signext, i16 signext, i32 signext, i64, float, double,
 ; normally use %f0/%f2 as the first available 128-bit pair.  This choice
 ; is hard-coded in the FP128 tests.
 ;
-; The order of the CHECK-INT loads doesn't matter.  The same goes for the
-; CHECK_FP128-* stores and the CHECK-STACK stores.  It would be OK to reorder
+; The order of the CHECK-STACK stores doesn't matter.  It would be OK to reorder
 ; them in response to future code changes.
 define void @foo() {
-; CHECK-INT: foo:
-; CHECK-INT: lghi %r2, -1
-; CHECK-INT: lghi %r3, -2
-; CHECK-INT: lghi %r4, -3
-; CHECK-INT: lghi %r5, -4
-; CHECK-INT: la %r6, {{224|240}}(%r15)
+; CHECK-INT-LABEL: foo:
+; CHECK-INT-DAG: lghi %r2, -1
+; CHECK-INT-DAG: lghi %r3, -2
+; CHECK-INT-DAG: lghi %r4, -3
+; CHECK-INT-DAG: lghi %r5, -4
+; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
 ; CHECK-INT: brasl %r14, bar@PLT
 ;
-; CHECK-FLOAT: foo:
+; CHECK-FLOAT-LABEL: foo:
 ; CHECK-FLOAT: lzer %f0
 ; CHECK-FLOAT: lcebr %f4, %f0
 ; CHECK-FLOAT: brasl %r14, bar@PLT
 ;
-; CHECK-DOUBLE: foo:
+; CHECK-DOUBLE-LABEL: foo:
 ; CHECK-DOUBLE: lzdr %f2
 ; CHECK-DOUBLE: lcdbr %f6, %f2
 ; CHECK-DOUBLE: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-1: foo:
+; CHECK-FP128-1-LABEL: foo:
 ; CHECK-FP128-1: aghi %r15, -256
 ; CHECK-FP128-1: lzxr %f0
-; CHECK-FP128-1: std %f0, 224(%r15)
-; CHECK-FP128-1: std %f2, 232(%r15)
+; CHECK-FP128-1-DAG: std %f0, 224(%r15)
+; CHECK-FP128-1-DAG: std %f2, 232(%r15)
 ; CHECK-FP128-1: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-2: foo:
+; CHECK-FP128-2-LABEL: foo:
 ; CHECK-FP128-2: aghi %r15, -256
 ; CHECK-FP128-2: lzxr %f0
-; CHECK-FP128-2: std %f0, 240(%r15)
-; CHECK-FP128-2: std %f2, 248(%r15)
+; CHECK-FP128-2-DAG: std %f0, 240(%r15)
+; CHECK-FP128-2-DAG: std %f2, 248(%r15)
 ; CHECK-FP128-2: brasl %r14, bar@PLT
 ;
-; CHECK-STACK: foo:
+; CHECK-STACK-LABEL: foo:
 ; CHECK-STACK: aghi %r15, -256
 ; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15)
 ; CHECK-STACK: stg [[REGISTER]], 216(%r15)
diff --git a/test/CodeGen/SystemZ/args-03.ll b/test/CodeGen/SystemZ/args-03.ll
index f954d58..d7d3ea1 100644
--- a/test/CodeGen/SystemZ/args-03.ll
+++ b/test/CodeGen/SystemZ/args-03.ll
@@ -18,43 +18,42 @@ declare void @bar(i8 zeroext, i16 zeroext, i32 zeroext, i64, float, double,
 ; normally use %f0/%f2 as the first available 128-bit pair.  This choice
 ; is hard-coded in the FP128 tests.
 ;
-; The order of the CHECK-INT loads doesn't matter.  The same goes for the
-; CHECK_FP128-* stores and the CHECK-STACK stores.  It would be OK to reorder
+; The order of the CHECK-STACK stores doesn't matter.  It would be OK to reorder
 ; them in response to future code changes.
 define void @foo() {
-; CHECK-INT: foo:
-; CHECK-INT: lghi %r2, 255
-; CHECK-INT: llill %r3, 65534
-; CHECK-INT: llilf %r4, 4294967293
-; CHECK-INT: lghi %r5, -4
-; CHECK-INT: la %r6, {{224|240}}(%r15)
+; CHECK-INT-LABEL: foo:
+; CHECK-INT-DAG: lghi %r2, 255
+; CHECK-INT-DAG: llill %r3, 65534
+; CHECK-INT-DAG: llilf %r4, 4294967293
+; CHECK-INT-DAG: lghi %r5, -4
+; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
 ; CHECK-INT: brasl %r14, bar@PLT
 ;
-; CHECK-FLOAT: foo:
+; CHECK-FLOAT-LABEL: foo:
 ; CHECK-FLOAT: lzer %f0
 ; CHECK-FLOAT: lcebr %f4, %f0
 ; CHECK-FLOAT: brasl %r14, bar@PLT
 ;
-; CHECK-DOUBLE: foo:
+; CHECK-DOUBLE-LABEL: foo:
 ; CHECK-DOUBLE: lzdr %f2
 ; CHECK-DOUBLE: lcdbr %f6, %f2
 ; CHECK-DOUBLE: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-1: foo:
+; CHECK-FP128-1-LABEL: foo:
 ; CHECK-FP128-1: aghi %r15, -256
 ; CHECK-FP128-1: lzxr %f0
-; CHECK-FP128-1: std %f0, 224(%r15)
-; CHECK-FP128-1: std %f2, 232(%r15)
+; CHECK-FP128-1-DAG: std %f0, 224(%r15)
+; CHECK-FP128-1-DAG: std %f2, 232(%r15)
 ; CHECK-FP128-1: brasl %r14, bar@PLT
 ;
-; CHECK-FP128-2: foo:
+; CHECK-FP128-2-LABEL: foo:
 ; CHECK-FP128-2: aghi %r15, -256
 ; CHECK-FP128-2: lzxr %f0
-; CHECK-FP128-2: std %f0, 240(%r15)
-; CHECK-FP128-2: std %f2, 248(%r15)
+; CHECK-FP128-2-DAG: std %f0, 240(%r15)
+; CHECK-FP128-2-DAG: std %f2, 248(%r15)
 ; CHECK-FP128-2: brasl %r14, bar@PLT
 ;
-; CHECK-STACK: foo:
+; CHECK-STACK-LABEL: foo:
 ; CHECK-STACK: aghi %r15, -256
 ; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15)
 ; CHECK-STACK: stg [[REGISTER]], 216(%r15)
diff --git a/test/CodeGen/SystemZ/args-04.ll b/test/CodeGen/SystemZ/args-04.ll
index 8340494..1178bb4 100644
--- a/test/CodeGen/SystemZ/args-04.ll
+++ b/test/CodeGen/SystemZ/args-04.ll
@@ -5,7 +5,7 @@
 
 ; Do some arithmetic so that we can see the register being used.
 define i8 @f1(i8 %r2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ahi %r2, 1
 ; CHECK: br %r14
   %y = add i8 %r2, 1
@@ -13,21 +13,21 @@ define i8 @f1(i8 %r2) {
 }
 
 define i16 @f2(i8 %r2, i16 %r3) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: {{lr|lgr}} %r2, %r3
 ; CHECK: br %r14
   ret i16 %r3
 }
 
 define i32 @f3(i8 %r2, i16 %r3, i32 %r4) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: {{lr|lgr}} %r2, %r4
 ; CHECK: br %r14
   ret i32 %r4
 }
 
 define i64 @f4(i8 %r2, i16 %r3, i32 %r4, i64 %r5) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: {{lr|lgr}} %r2, %r5
 ; CHECK: br %r14
   ret i64 %r5
@@ -35,7 +35,7 @@ define i64 @f4(i8 %r2, i16 %r3, i32 %r4, i64 %r5) {
 
 ; Do some arithmetic so that we can see the register being used.
 define float @f5(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aebr %f0, %f0
 ; CHECK: br %r14
   %y = fadd float %f0, %f0
@@ -43,7 +43,7 @@ define float @f5(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0) {
 }
 
 define double @f6(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   ret double %f2
@@ -54,7 +54,7 @@ define double @f6(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2) {
 ; be copied.
 define void @f7(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                 fp128 %r6) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ld %f0, 0(%r6)
 ; CHECK: ld %f2, 8(%r6)
 ; CHECK: axbr %f0, %f0
@@ -68,7 +68,7 @@ define void @f7(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 
 define i64 @f8(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                fp128 %r6, i64 %s1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lg %r2, 160(%r15)
 ; CHECK: br %r14
   ret i64 %s1
@@ -76,7 +76,7 @@ define i64 @f8(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 
 define float @f9(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                  fp128 %r6, i64 %s1, float %f4) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ler %f0, %f4
 ; CHECK: br %r14
   ret float %f4
@@ -84,7 +84,7 @@ define float @f9(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 
 define double @f10(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                    fp128 %r6, i64 %s1, float %f4, double %f6) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ldr %f0, %f6
 ; CHECK: br %r14
   ret double %f6
@@ -92,7 +92,7 @@ define double @f10(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 
 define i64 @f11(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                 fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: lg %r2, 168(%r15)
 ; CHECK: br %r14
   ret i64 %s2
@@ -102,7 +102,7 @@ define i64 @f11(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 define float @f12(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                   fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2,
                   float %s3) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: le %f0, 180(%r15)
 ; CHECK: br %r14
   ret float %s3
@@ -112,7 +112,7 @@ define float @f12(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
 define void @f13(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
                  fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2,
                  float %s3, fp128 %s4) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: lg [[REGISTER:%r[1-5]+]], 184(%r15)
 ; CHECK: ld %f0, 0([[REGISTER]])
 ; CHECK: ld %f2, 8([[REGISTER]])
diff --git a/test/CodeGen/SystemZ/args-05.ll b/test/CodeGen/SystemZ/args-05.ll
index 9fa193a..8a6ef4c 100644
--- a/test/CodeGen/SystemZ/args-05.ll
+++ b/test/CodeGen/SystemZ/args-05.ll
@@ -4,7 +4,7 @@
 
 ; Zero extension of something that is already zero-extended.
 define void @f1(i32 zeroext %r2, i64 *%r3) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r2
 ; CHECK: stg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define void @f1(i32 zeroext %r2, i64 *%r3) {
 
 ; Sign extension of something that is already sign-extended.
 define void @f2(i32 signext %r2, i64 *%r3) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r2
 ; CHECK: stg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define void @f2(i32 signext %r2, i64 *%r3) {
 
 ; Sign extension of something that is already zero-extended.
 define void @f3(i32 zeroext %r2, i64 *%r3) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgfr [[REGISTER:%r[0-5]+]], %r2
 ; CHECK: stg [[REGISTER]], 0(%r3)
 ; CHECK: br %r14
@@ -37,7 +37,7 @@ define void @f3(i32 zeroext %r2, i64 *%r3) {
 
 ; Zero extension of something that is already sign-extended.
 define void @f4(i32 signext %r2, i64 *%r3) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgfr [[REGISTER:%r[0-5]+]], %r2
 ; CHECK: stg [[REGISTER]], 0(%r3)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/args-06.ll b/test/CodeGen/SystemZ/args-06.ll
index b2f8bee..a89fe9b 100644
--- a/test/CodeGen/SystemZ/args-06.ll
+++ b/test/CodeGen/SystemZ/args-06.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i8 @f1(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ar %r2, %r3
 ; CHECK: ar %r2, %r4
 ; CHECK: ar %r2, %r5
@@ -22,7 +22,7 @@ define i8 @f1(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g) {
 }
 
 define i16 @f2(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ar %r2, %r3
 ; CHECK: ar %r2, %r4
 ; CHECK: ar %r2, %r5
@@ -40,7 +40,7 @@ define i16 @f2(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g) {
 }
 
 define i32 @f3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ar %r2, %r3
 ; CHECK: ar %r2, %r4
 ; CHECK: ar %r2, %r5
@@ -58,7 +58,7 @@ define i32 @f3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) {
 }
 
 define i64 @f4(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agr %r2, %r3
 ; CHECK: agr %r2, %r4
 ; CHECK: agr %r2, %r5
diff --git a/test/CodeGen/SystemZ/asm-01.ll b/test/CodeGen/SystemZ/asm-01.ll
index 016d04c..801378c 100644
--- a/test/CodeGen/SystemZ/asm-01.ll
+++ b/test/CodeGen/SystemZ/asm-01.ll
@@ -5,7 +5,7 @@
 
 ; Check the lowest range.
 define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
@@ -15,7 +15,7 @@ define void @f1(i64 %base) {
 
 ; Check the next lowest byte.
 define void @f2(i64 %base) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r2, -1
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ define void @f2(i64 %base) {
 
 ; Check the highest range.
 define void @f3(i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah 4095(%r2)
 ; CHECK: br %r14
   %add = add i64 %base, 4095
@@ -38,7 +38,7 @@ define void @f3(i64 %base) {
 
 ; Check the next highest byte.
 define void @f4(i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define void @f4(i64 %base) {
 
 ; Check that indices aren't allowed
 define void @f5(i64 %base, i64 %index) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agr %r2, %r3
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-02.ll b/test/CodeGen/SystemZ/asm-02.ll
index 12d8bec..ad1e35b 100644
--- a/test/CodeGen/SystemZ/asm-02.ll
+++ b/test/CodeGen/SystemZ/asm-02.ll
@@ -5,7 +5,7 @@
 
 ; Check the lowest range.
 define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
@@ -15,7 +15,7 @@ define void @f1(i64 %base) {
 
 ; Check the next lowest byte.
 define void @f2(i64 %base) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r2, -1
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ define void @f2(i64 %base) {
 
 ; Check the highest range.
 define void @f3(i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah 4095(%r2)
 ; CHECK: br %r14
   %add = add i64 %base, 4095
@@ -38,7 +38,7 @@ define void @f3(i64 %base) {
 
 ; Check the next highest byte.
 define void @f4(i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-03.ll b/test/CodeGen/SystemZ/asm-03.ll
index a6f3f2a..fa3e1a7 100644
--- a/test/CodeGen/SystemZ/asm-03.ll
+++ b/test/CodeGen/SystemZ/asm-03.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
diff --git a/test/CodeGen/SystemZ/asm-04.ll b/test/CodeGen/SystemZ/asm-04.ll
index 0560949..af7ea9f 100644
--- a/test/CodeGen/SystemZ/asm-04.ll
+++ b/test/CodeGen/SystemZ/asm-04.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
diff --git a/test/CodeGen/SystemZ/asm-05.ll b/test/CodeGen/SystemZ/asm-05.ll
index dae90b0..e18cb75 100644
--- a/test/CodeGen/SystemZ/asm-05.ll
+++ b/test/CodeGen/SystemZ/asm-05.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: blah 0(%r2)
 ; CHECK: br %r14
   %addr = inttoptr i64 %base to i64 *
diff --git a/test/CodeGen/SystemZ/asm-06.ll b/test/CodeGen/SystemZ/asm-06.ll
index c0e24a3..f9848a2 100644
--- a/test/CodeGen/SystemZ/asm-06.ll
+++ b/test/CodeGen/SystemZ/asm-06.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r1, 1
 ; CHECK: blah %r2 %r1
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define i64 @f1() {
 }
 
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi %r1, 2
 ; CHECK: blah %r2 %r1
 ; CHECK: br %r14
@@ -21,7 +21,7 @@ define i64 @f2() {
 }
 
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lhi %r1, 3
 ; CHECK: blah %r2 %r1
 ; CHECK: br %r14
@@ -30,7 +30,7 @@ define i64 @f3() {
 }
 
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lghi %r1, 4
 ; CHECK: blah %r2 %r1
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-07.ll b/test/CodeGen/SystemZ/asm-07.ll
index e07286d..bf63150 100644
--- a/test/CodeGen/SystemZ/asm-07.ll
+++ b/test/CodeGen/SystemZ/asm-07.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r0, 1
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define i64 @f1() {
 }
 
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi %r0, 2
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -21,7 +21,7 @@ define i64 @f2() {
 }
 
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lhi %r0, 3
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -30,7 +30,7 @@ define i64 @f3() {
 }
 
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lghi %r0, 4
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-08.ll b/test/CodeGen/SystemZ/asm-08.ll
index 15abc4d..1662337 100644
--- a/test/CodeGen/SystemZ/asm-08.ll
+++ b/test/CodeGen/SystemZ/asm-08.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r0, 1
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define i64 @f1() {
 }
 
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi %r0, 2
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -21,7 +21,7 @@ define i64 @f2() {
 }
 
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lhi %r0, 3
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
@@ -30,7 +30,7 @@ define i64 @f3() {
 }
 
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lghi %r0, 4
 ; CHECK: blah %r2 %r0
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-09.ll b/test/CodeGen/SystemZ/asm-09.ll
index 1541170..5cd7efb 100644
--- a/test/CodeGen/SystemZ/asm-09.ll
+++ b/test/CodeGen/SystemZ/asm-09.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i32 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r0, 100
 ; CHECK: blah %r0
 ; CHECK: st %r0, 0(%r2)
@@ -14,7 +14,7 @@ define void @f1(i32 *%dst) {
 }
 
 define void @f2(i32 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi %r0, 101
 ; CHECK: blah %r0
 ; CHECK: st %r0, 0(%r2)
@@ -25,7 +25,7 @@ define void @f2(i32 *%dst) {
 }
 
 define void @f3(i32 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lhi %r0, 102
 ; CHECK: blah %r0
 ; CHECK: st %r0, 0(%r2)
@@ -37,7 +37,7 @@ define void @f3(i32 *%dst) {
 
 ; FIXME: this uses "lhi %r0, 103", but should use "lghi %r0, 103".
 define void @f4(i32 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: blah %r0
 ; CHECK: st %r0, 0(%r2)
 ; CHECK: br %r14
@@ -47,7 +47,7 @@ define void @f4(i32 *%dst) {
 }
 
 define i64 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lghi %r2, 104
 ; CHECK: blah %r2
 ; CHECK: br %r14
@@ -56,7 +56,7 @@ define i64 @f5() {
 }
 
 define i64 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lghi %r2, 105
 ; CHECK: blah %r2
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define i64 @f6() {
 }
 
 define i64 @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lghi %r2, 106
 ; CHECK: blah %r2
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define i64 @f7() {
 }
 
 define i64 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lghi %r2, 107
 ; CHECK: blah %r2
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-10.ll b/test/CodeGen/SystemZ/asm-10.ll
index 676c202..0eccc19 100644
--- a/test/CodeGen/SystemZ/asm-10.ll
+++ b/test/CodeGen/SystemZ/asm-10.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lzer %f1
 ; CHECK: blah %f0 %f1
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define float @f1() {
 }
 
 define double @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lzdr %f1
 ; CHECK: blah %f0 %f1
 ; CHECK: br %r14
@@ -21,7 +21,7 @@ define double @f2() {
 }
 
 define double @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lzxr %f1
 ; CHECK: blah %f0 %f1
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-11.ll b/test/CodeGen/SystemZ/asm-11.ll
index 9bd8d7c..8aeb784 100644
--- a/test/CodeGen/SystemZ/asm-11.ll
+++ b/test/CodeGen/SystemZ/asm-11.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the first valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi [[REG:%r[0-5]]], -1
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 0
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rI" (i32 0)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test the last valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah %r2 255
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rI" (i32 255)
@@ -32,7 +32,7 @@ define i32 @f3() {
 
 ; Test 1 above the last valid value.
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lhi [[REG:%r[0-5]]], 256
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-12.ll b/test/CodeGen/SystemZ/asm-12.ll
index dd920f1..feecbac 100644
--- a/test/CodeGen/SystemZ/asm-12.ll
+++ b/test/CodeGen/SystemZ/asm-12.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the first valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi [[REG:%r[0-5]]], -1
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 0
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 0)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test the last valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah %r2 4095
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 4095)
@@ -32,7 +32,7 @@ define i32 @f3() {
 
 ; Test 1 above the last valid value.
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lhi [[REG:%r[0-5]]], 4096
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-13.ll b/test/CodeGen/SystemZ/asm-13.ll
index af3fdb3..b881700 100644
--- a/test/CodeGen/SystemZ/asm-13.ll
+++ b/test/CodeGen/SystemZ/asm-13.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the first valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: iilf [[REG:%r[0-5]]], 4294934527
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 -32768
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rK" (i32 -32768)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test the last valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah %r2 32767
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rK" (i32 32767)
@@ -32,7 +32,7 @@ define i32 @f3() {
 
 ; Test 1 above the last valid value.
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llill [[REG:%r[0-5]]], 32768
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-14.ll b/test/CodeGen/SystemZ/asm-14.ll
index b6b28d6..bcd8b1e 100644
--- a/test/CodeGen/SystemZ/asm-14.ll
+++ b/test/CodeGen/SystemZ/asm-14.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the first valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: iilf [[REG:%r[0-5]]], 4294443007
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 -524288
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rL" (i32 -524288)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test the last valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blah %r2 524287
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rL" (i32 524287)
@@ -32,7 +32,7 @@ define i32 @f3() {
 
 ; Test 1 above the last valid value.
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llilh [[REG:%r[0-5]]], 8
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-15.ll b/test/CodeGen/SystemZ/asm-15.ll
index 4d0e2b4..886ee0e 100644
--- a/test/CodeGen/SystemZ/asm-15.ll
+++ b/test/CodeGen/SystemZ/asm-15.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: iilf [[REG:%r[0-5]]], 2147483646
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 2147483647
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483647)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test 1 above the valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llilh [[REG:%r[0-5]]], 32768
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-16.ll b/test/CodeGen/SystemZ/asm-16.ll
index 4d0e2b4..886ee0e 100644
--- a/test/CodeGen/SystemZ/asm-16.ll
+++ b/test/CodeGen/SystemZ/asm-16.ll
@@ -4,7 +4,7 @@
 
 ; Test 1 below the valid value.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: iilf [[REG:%r[0-5]]], 2147483646
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
@@ -14,7 +14,7 @@ define i32 @f1() {
 
 ; Test the first valid value.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: blah %r2 2147483647
 ; CHECK: br %r14
   %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483647)
@@ -23,7 +23,7 @@ define i32 @f2() {
 
 ; Test 1 above the valid value.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llilh [[REG:%r[0-5]]], 32768
 ; CHECK: blah %r2 [[REG]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/asm-17.ll b/test/CodeGen/SystemZ/asm-17.ll
new file mode 100644
index 0000000..33234fc
--- /dev/null
+++ b/test/CodeGen/SystemZ/asm-17.ll
@@ -0,0 +1,82 @@
+; Test explicit register names.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+; Test i32 GPRs.
+define i32 @f1() {
+; CHECK-LABEL: f1:
+; CHECK: lhi %r4, 1
+; CHECK: blah %r4
+; CHECK: lr %r2, %r4
+; CHECK: br %r14
+  %ret = call i32 asm "blah $0", "={r4},0" (i32 1)
+  ret i32 %ret
+}
+
+; Test i64 GPRs.
+define i64 @f2() {
+; CHECK-LABEL: f2:
+; CHECK: lghi %r4, 1
+; CHECK: blah %r4
+; CHECK: lgr %r2, %r4
+; CHECK: br %r14
+  %ret = call i64 asm "blah $0", "={r4},0" (i64 1)
+  ret i64 %ret
+}
+
+; Test i32 FPRs.
+define float @f3() {
+; CHECK-LABEL: f3:
+; CHECK: lzer %f4
+; CHECK: blah %f4
+; CHECK: ler %f0, %f4
+; CHECK: br %r14
+  %ret = call float asm "blah $0", "={f4},0" (float 0.0)
+  ret float %ret
+}
+
+; Test i64 FPRs.
+define double @f4() {
+; CHECK-LABEL: f4:
+; CHECK: lzdr %f4
+; CHECK: blah %f4
+; CHECK: ldr %f0, %f4
+; CHECK: br %r14
+  %ret = call double asm "blah $0", "={f4},0" (double 0.0)
+  ret double %ret
+}
+
+; Test i128 FPRs.
+define void @f5(fp128 *%dest) {
+; CHECK-LABEL: f5:
+; CHECK: lzxr %f4
+; CHECK: blah %f4
+; CHECK-DAG: std %f4, 0(%r2)
+; CHECK-DAG: std %f6, 8(%r2)
+; CHECK: br %r14
+  %ret = call fp128 asm "blah $0", "={f4},0" (fp128 0xL00000000000000000000000000000000)
+  store fp128 %ret, fp128 *%dest
+  ret void
+}
+
+; Test clobbers of GPRs and CC.
+define i32 @f6(i32 %in) {
+; CHECK-LABEL: f6:
+; CHECK: lr [[REG:%r[01345]]], %r2
+; CHECK: blah
+; CHECK: lr %r2, [[REG]]
+; CHECK: br %r14
+  call void asm sideeffect "blah", "~{r2},~{cc}"()
+  ret i32 %in
+}
+
+; Test clobbers of FPRs and CC.
+define float @f7(float %in) {
+; CHECK-LABEL: f7:
+; CHECK: ler [[REG:%f[1-7]]], %f0
+; CHECK: blah
+; CHECK: ler %f0, [[REG]]
+; CHECK: br %r14
+  call void asm sideeffect "blah", "~{f0},~{cc}"()
+  ret float %in
+}
diff --git a/test/CodeGen/SystemZ/atomic-load-01.ll b/test/CodeGen/SystemZ/atomic-load-01.ll
index 3e86bcf..a5bc883 100644
--- a/test/CodeGen/SystemZ/atomic-load-01.ll
+++ b/test/CodeGen/SystemZ/atomic-load-01.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that loads are handled.
 ; The CS-based sequence is probably far too conservative.
 define i8 @f1(i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cs
 ; CHECK: br %r14
   %val = load atomic i8 *%src seq_cst, align 1
diff --git a/test/CodeGen/SystemZ/atomic-load-02.ll b/test/CodeGen/SystemZ/atomic-load-02.ll
index d6168ce..2c9bbdb 100644
--- a/test/CodeGen/SystemZ/atomic-load-02.ll
+++ b/test/CodeGen/SystemZ/atomic-load-02.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that loads are handled.
 ; The CS-based sequence is probably far too conservative.
 define i16 @f1(i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cs
 ; CHECK: br %r14
   %val = load atomic i16 *%src seq_cst, align 2
diff --git a/test/CodeGen/SystemZ/atomic-load-03.ll b/test/CodeGen/SystemZ/atomic-load-03.ll
index fcf0cf3..1fb41f5 100644
--- a/test/CodeGen/SystemZ/atomic-load-03.ll
+++ b/test/CodeGen/SystemZ/atomic-load-03.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that loads are handled.
 ; Using CS is probably too conservative.
 define i32 @f1(i32 %dummy, i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r2, 0
 ; CHECK: cs %r2, %r2, 0(%r3)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomic-load-04.ll b/test/CodeGen/SystemZ/atomic-load-04.ll
index 9593d35..92cac40 100644
--- a/test/CodeGen/SystemZ/atomic-load-04.ll
+++ b/test/CodeGen/SystemZ/atomic-load-04.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that loads are handled.
 ; Using CSG is probably too conservative.
 define i64 @f1(i64 %dummy, i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lghi %r2, 0
 ; CHECK: csg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomic-store-01.ll b/test/CodeGen/SystemZ/atomic-store-01.ll
index b316e5c..53ed24f 100644
--- a/test/CodeGen/SystemZ/atomic-store-01.ll
+++ b/test/CodeGen/SystemZ/atomic-store-01.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that stores are handled.
 ; The CS-based sequence is probably far too conservative.
 define void @f1(i8 %val, i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cs
 ; CHECK: br %r14
   store atomic i8 %val, i8 *%src seq_cst, align 1
diff --git a/test/CodeGen/SystemZ/atomic-store-02.ll b/test/CodeGen/SystemZ/atomic-store-02.ll
index c761714..42d6695 100644
--- a/test/CodeGen/SystemZ/atomic-store-02.ll
+++ b/test/CodeGen/SystemZ/atomic-store-02.ll
@@ -5,7 +5,7 @@
 ; This is just a placeholder to make sure that stores are handled.
 ; The CS-based sequence is probably far too conservative.
 define void @f1(i16 %val, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cs
 ; CHECK: br %r14
   store atomic i16 %val, i16 *%src seq_cst, align 2
diff --git a/test/CodeGen/SystemZ/atomic-store-03.ll b/test/CodeGen/SystemZ/atomic-store-03.ll
index cbf1e51..846c86f 100644
--- a/test/CodeGen/SystemZ/atomic-store-03.ll
+++ b/test/CodeGen/SystemZ/atomic-store-03.ll
@@ -5,11 +5,11 @@
 ; This is just a placeholder to make sure that stores are handled.
 ; Using CS is probably too conservative.
 define void @f1(i32 %val, i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r0, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: cs %r0, %r2, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   store atomic i32 %val, i32 *%src seq_cst, align 4
   ret void
diff --git a/test/CodeGen/SystemZ/atomic-store-04.ll b/test/CodeGen/SystemZ/atomic-store-04.ll
index a2d83c5..24615b1 100644
--- a/test/CodeGen/SystemZ/atomic-store-04.ll
+++ b/test/CodeGen/SystemZ/atomic-store-04.ll
@@ -5,11 +5,11 @@
 ; This is just a placeholder to make sure that stores are handled.
 ; Using CS is probably too conservative.
 define void @f1(i64 %val, i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r0, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: csg %r0, %r2, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   store atomic i64 %val, i64 *%src seq_cst, align 8
   ret void
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-01.ll b/test/CodeGen/SystemZ/atomicrmw-add-01.ll
index 615b292..25f71f3 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-01.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -22,11 +22,11 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: ar [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: ar {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -56,11 +56,11 @@ define i8 @f2(i8 *%src) {
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
 
 ; Check addition of -1.  We add 0xff000000 to the rotated word.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: afi [[ROT]], -16777216
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 -1 seq_cst
   ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
 
 ; Check addition of 1.  We add 0x01000000 to the rotated word.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi [[ROT]], 16777216
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We add 0x7f000000 to the rotated word.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi [[ROT]], 2130706432
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
 ; Check addition of a large unsigned value.  We add 0xfe000000 to the
 ; rotated word, expressed as a negative AFI operand.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi [[ROT]], -33554432
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i8 *%src, i8 254 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-02.ll b/test/CodeGen/SystemZ/atomicrmw-add-02.ll
index 95fb02a..cd4e478 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-02.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -22,11 +22,11 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: ar [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: ar {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -56,11 +56,11 @@ define i16 @f2(i16 *%src) {
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
 
 ; Check addition of -1.  We add 0xffff0000 to the rotated word.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: afi [[ROT]], -65536
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 -1 seq_cst
   ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
 
 ; Check addition of 1.  We add 0x00010000 to the rotated word.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi [[ROT]], 65536
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We add 0x7fff0000 to the rotated word.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi [[ROT]], 2147418112
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
 ; Check addition of a large unsigned value.  We add 0xfffe0000 to the
 ; rotated word, expressed as a negative AFI operand.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi [[ROT]], -131072
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw add i16 *%src, i16 65534 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-03.ll b/test/CodeGen/SystemZ/atomicrmw-add-03.ll
index e319057..a81af72 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-03.ll
@@ -1,16 +1,16 @@
 ; Test 32-bit atomic additions.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check addition of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lr %r0, %r2
 ; CHECK: ar %r0, %r4
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -18,13 +18,13 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check addition of 1, which can use AHI.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lr %r0, %r2
 ; CHECK: ahi %r0, 1
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 1 seq_cst
   ret i32 %res
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check the high end of the AHI range.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ahi %r0, 32767
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 32767 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which must use AFI.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi %r0, 32768
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 32768 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
 
 ; Check the high end of the AFI range.
 define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi %r0, 2147483647
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 2147483647 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which gets treated as a negative operand.
 define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi %r0, -2147483648
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 2147483648 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
 
 ; Check addition of -1, which can use AHI.
 define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ahi %r0, -1
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 -1 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
 
 ; Check the low end of the AHI range.
 define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ahi %r0, -32768
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 -32768 seq_cst
@@ -86,7 +86,7 @@ define i32 @f8(i32 %dummy, i32 *%src) {
 
 ; Check the next value down, which must use AFI instead.
 define i32 @f9(i32 %dummy, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: afi %r0, -32769
 ; CHECK: br %r14
   %res = atomicrmw add i32 *%src, i32 -32769 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-add-04.ll b/test/CodeGen/SystemZ/atomicrmw-add-04.ll
index b2cbaca..e790549 100644
--- a/test/CodeGen/SystemZ/atomicrmw-add-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-add-04.ll
@@ -1,16 +1,16 @@
 ; Test 64-bit atomic additions.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check addition of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
 ; CHECK: agr %r0, %r4
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -18,13 +18,13 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check addition of 1, which can use AGHI.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
 ; CHECK: aghi %r0, 1
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 1 seq_cst
   ret i64 %res
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the AGHI range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r0, 32767
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 32767 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use AGFI.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r0, 32768
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 32768 seq_cst
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the AGFI range.
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r0, 2147483647
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 2147483647 seq_cst
@@ -59,7 +59,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register addition.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agr
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 2147483648 seq_cst
@@ -68,7 +68,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check addition of -1, which can use AGHI.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: aghi %r0, -1
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 -1 seq_cst
@@ -77,7 +77,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the AGHI range.
 define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r0, -32768
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 -32768 seq_cst
@@ -86,7 +86,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
 
 ; Check the next value down, which must use AGFI instead.
 define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r0, -32769
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 -32769 seq_cst
@@ -95,7 +95,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the AGFI range.
 define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r0, -2147483648
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 -2147483648 seq_cst
@@ -104,7 +104,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
 
 ; Check the next value down, which must use a register addition.
 define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agr
 ; CHECK: br %r14
   %res = atomicrmw add i64 *%src, i64 -2147483649 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-01.ll b/test/CodeGen/SystemZ/atomicrmw-and-01.ll
index 6d66df3..6d2f541 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-01.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -22,11 +22,11 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: nr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: oilf %r3, 16777215
 ; CHECK-SHIFT2: rll
@@ -48,7 +48,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We AND the rotated word with 0x80ffffff.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -57,11 +57,11 @@ define i8 @f2(i8 *%src) {
 ; CHECK: nilh [[ROT]], 33023
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -69,7 +69,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -77,13 +77,13 @@ define i8 @f2(i8 *%src) {
 
 ; Check ANDs of -2 (-1 isn't useful).  We AND the rotated word with 0xfeffffff.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh [[ROT]], 65279
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 -2 seq_cst
   ret i8 %res
@@ -91,13 +91,13 @@ define i8 @f3(i8 *%src) {
 
 ; Check ANDs of 1.  We AND the rotated word with 0x01ffffff.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilh [[ROT]], 511
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -105,13 +105,13 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We AND the rotated word with 0x7fffffff.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nilh [[ROT]], 32767
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -120,13 +120,13 @@ define i8 @f5(i8 *%src) {
 ; Check ANDs of a large unsigned value.  We AND the rotated word with
 ; 0xfdffffff.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nilh [[ROT]], 65023
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i8 *%src, i8 253 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-02.ll b/test/CodeGen/SystemZ/atomicrmw-and-02.ll
index 76e33bb..572b224 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-02.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -22,11 +22,11 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: nr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: oill %r3, 65535
 ; CHECK-SHIFT2: rll
@@ -48,7 +48,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We AND the rotated word with 0x8000ffff.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -57,11 +57,11 @@ define i16 @f2(i16 *%src) {
 ; CHECK: nilh [[ROT]], 32768
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -69,7 +69,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -77,13 +77,13 @@ define i16 @f2(i16 *%src) {
 
 ; Check ANDs of -2 (-1 isn't useful).  We AND the rotated word with 0xfffeffff.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh [[ROT]], 65534
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 -2 seq_cst
   ret i16 %res
@@ -91,13 +91,13 @@ define i16 @f3(i16 *%src) {
 
 ; Check ANDs of 1.  We AND the rotated word with 0x0001ffff.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilh [[ROT]], 1
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -105,13 +105,13 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We AND the rotated word with 0x7fffffff.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nilh [[ROT]], 32767
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -120,13 +120,13 @@ define i16 @f5(i16 *%src) {
 ; Check ANDs of a large unsigned value.  We AND the rotated word with
 ; 0xfffdffff.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nilh [[ROT]], 65533
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw and i16 *%src, i16 65533 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-03.ll b/test/CodeGen/SystemZ/atomicrmw-and-03.ll
index 8449a7c..8d813a1 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-03.ll
@@ -1,16 +1,16 @@
 ; Test 32-bit atomic ANDs.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check ANDs of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
 ; CHECK: nr %r0, %r4
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -18,13 +18,13 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check ANDs of 1.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
 ; CHECK: nilf %r0, 1
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 1 seq_cst
   ret i32 %res
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check ANDs of the low end of the NILH range.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 65535 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which must use NILF.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilf %r0, 65536
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 65536 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
 
 ; Check the largest useful NILL value.
 define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nill %r0, 65534
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 -2 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
 
 ; Check the low end of the NILL range.
 define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nill %r0, 0
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 -65536 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
 
 ; Check the largest useful NILH value, which is one less than the above.
 define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: nilh %r0, 65534
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 -65537 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
 
 ; Check the highest useful NILF value, which is one less than the above.
 define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: nilf %r0, 4294901758
 ; CHECK: br %r14
   %res = atomicrmw and i32 *%src, i32 -65538 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-and-04.ll b/test/CodeGen/SystemZ/atomicrmw-and-04.ll
index ade7617..89899a6 100644
--- a/test/CodeGen/SystemZ/atomicrmw-and-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-and-04.ll
@@ -1,156 +1,170 @@
 ; Test 64-bit atomic ANDs.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check ANDs of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
 ; CHECK: ngr %r0, %r4
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 %b seq_cst
   ret i64 %res
 }
 
-; Check ANDs of 1, which must be done using a register.
+; Check ANDs of 1, which are done using a register.  (We could use RISBG
+; instead, but that isn't implemented yet.)
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ngr
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 1 seq_cst
   ret i64 %res
 }
 
-; Check the low end of the NIHF range.
+; Check the equivalent of NIHF with 1, which can use RISBG instead.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
-; CHECK: lgr %r0, %r2
-; CHECK: nihf %r0, 0
+; CHECK: risbg %r0, %r2, 31, 191, 0
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
-  %res = atomicrmw and i64 *%src, i64 4294967295 seq_cst
+  %res = atomicrmw and i64 *%src, i64 8589934591 seq_cst
   ret i64 %res
 }
 
-; Check the next value up, which must use a register.
+; Check the lowest NIHF value outside the range of RISBG.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
-; CHECK: ngr
+; CHECK-LABEL: f4:
+; CHECK: lg %r2, 0(%r3)
+; CHECK: [[LABEL:\.[^:]*]]:
+; CHECK: lgr %r0, %r2
+; CHECK: nihf %r0, 2
+; CHECK: csg %r2, %r0, 0(%r3)
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
-  %res = atomicrmw and i64 *%src, i64 4294967296 seq_cst
+  %res = atomicrmw and i64 *%src, i64 12884901887 seq_cst
   ret i64 %res
 }
 
-; Check the low end of the NIHH range.
+; Check the next value up, which must use a register.
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
-; CHECK: nihh %r0, 0
+; CHECK-LABEL: f5:
+; CHECK: ngr
 ; CHECK: br %r14
-  %res = atomicrmw and i64 *%src, i64 281474976710655 seq_cst
+  %res = atomicrmw and i64 *%src, i64 12884901888 seq_cst
   ret i64 %res
 }
 
-; Check the next value up, which must use a register.
+; Check the lowest NIHH value outside the range of RISBG.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
-; CHECK: ngr
+; CHECK-LABEL: f6:
+; CHECK: nihh {{%r[0-5]}}, 2
 ; CHECK: br %r14
-  %res = atomicrmw and i64 *%src, i64 281474976710656 seq_cst
+  %res = atomicrmw and i64 *%src, i64 844424930131967 seq_cst
   ret i64 %res
 }
 
-; Check the highest useful NILL value.
+; Check the next value up, which must use a register.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
-; CHECK: nill %r0, 65534
+; CHECK-LABEL: f7:
+; CHECK: ngr
 ; CHECK: br %r14
-  %res = atomicrmw and i64 *%src, i64 -2 seq_cst
+  %res = atomicrmw and i64 *%src, i64 281474976710656 seq_cst
   ret i64 %res
 }
 
-; Check the low end of the NILL range.
+; Check the highest NILL value outside the range of RISBG.
 define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
-; CHECK: nill %r0, 0
+; CHECK-LABEL: f8:
+; CHECK: nill {{%r[0-5]}}, 65530
 ; CHECK: br %r14
-  %res = atomicrmw and i64 *%src, i64 -65536 seq_cst
+  %res = atomicrmw and i64 *%src, i64 -6 seq_cst
   ret i64 %res
 }
 
-; Check the highest useful NILH value, which is one less than the above.
+; Check the lowest NILL value outside the range of RISBG.
 define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
-; CHECK: nilh %r0, 65534
+; CHECK-LABEL: f9:
+; CHECK: nill {{%r[0-5]}}, 2
 ; CHECK: br %r14
-  %res = atomicrmw and i64 *%src, i64 -65537 seq_cst
+  %res = atomicrmw and i64 *%src, i64 -65534 seq_cst
   ret i64 %res
 }
 
-; Check the highest useful NILF value, which is one less than the above.
+; Check the highest useful NILF value.
 define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
-; CHECK: nilf %r0, 4294901758
+; CHECK-LABEL: f10:
+; CHECK: nilf {{%r[0-5]}}, 4294901758
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -65538 seq_cst
   ret i64 %res
 }
 
-; Check the low end of the NILH range.
+; Check the highest NILH value outside the range of RISBG.
 define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
-; CHECK: nilh %r0, 0
+; CHECK-LABEL: f11:
+; CHECK: nilh {{%r[0-5]}}, 65530
 ; CHECK: br %r14
-  %res = atomicrmw and i64 *%src, i64 -4294901761 seq_cst
+  %res = atomicrmw and i64 *%src, i64 -327681 seq_cst
   ret i64 %res
 }
 
-; Check the low end of the NILF range.
+; Check the lowest NILH value outside the range of RISBG.
 define i64 @f12(i64 %dummy, i64 *%src) {
-; CHECK: f12:
-; CHECK: nilf %r0, 0
+; CHECK-LABEL: f12:
+; CHECK: nilh {{%r[0-5]}}, 2
 ; CHECK: br %r14
-  %res = atomicrmw and i64 *%src, i64 -4294967296 seq_cst
+  %res = atomicrmw and i64 *%src, i64 -4294770689 seq_cst
   ret i64 %res
 }
 
-; Check the highest useful NIHL value, which is one less than the above.
+; Check the lowest NILF value outside the range of RISBG.
 define i64 @f13(i64 %dummy, i64 *%src) {
-; CHECK: f13:
-; CHECK: nihl %r0, 65534
+; CHECK-LABEL: f13:
+; CHECK: nilf {{%r[0-5]}}, 2
 ; CHECK: br %r14
-  %res = atomicrmw and i64 *%src, i64 -4294967297 seq_cst
+  %res = atomicrmw and i64 *%src, i64 -4294967294 seq_cst
   ret i64 %res
 }
 
-; Check the low end of the NIHL range.
+; Check the highest NIHL value outside the range of RISBG.
 define i64 @f14(i64 %dummy, i64 *%src) {
-; CHECK: f14:
-; CHECK: nihl %r0, 0
+; CHECK-LABEL: f14:
+; CHECK: nihl {{%r[0-5]}}, 65530
 ; CHECK: br %r14
-  %res = atomicrmw and i64 *%src, i64 -281470681743361 seq_cst
+  %res = atomicrmw and i64 *%src, i64 -21474836481 seq_cst
   ret i64 %res
 }
 
-; Check the highest useful NIHH value, which is 1<<32 less than the above.
+; Check the lowest NIHL value outside the range of RISBG.
 define i64 @f15(i64 %dummy, i64 *%src) {
-; CHECK: f15:
-; CHECK: nihh %r0, 65534
+; CHECK-LABEL: f15:
+; CHECK: nihl {{%r[0-5]}}, 2
 ; CHECK: br %r14
-  %res = atomicrmw and i64 *%src, i64 -281474976710657 seq_cst
+  %res = atomicrmw and i64 *%src, i64 -281462091808769 seq_cst
   ret i64 %res
 }
 
-; Check the highest useful NIHF value, which is 1<<32 less than the above.
+; Check the highest NIHH value outside the range of RISBG.
 define i64 @f16(i64 %dummy, i64 *%src) {
-; CHECK: f16:
-; CHECK: nihf %r0, 4294901758
+; CHECK-LABEL: f16:
+; CHECK: nihh {{%r[0-5]}}, 65530
+; CHECK: br %r14
+  %res = atomicrmw and i64 *%src, i64 -1407374883553281 seq_cst
+  ret i64 %res
+}
+
+; Check the highest useful NIHF value.
+define i64 @f17(i64 %dummy, i64 *%src) {
+; CHECK-LABEL: f17:
+; CHECK: nihf {{%r[0-5]}}, 4294901758
 ; CHECK: br %r14
   %res = atomicrmw and i64 *%src, i64 -281479271677953 seq_cst
   ret i64 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
index bf490d8..a15fe57 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -24,11 +24,11 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -36,7 +36,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: crjle {{%r[0-9]+}}, %r3
@@ -49,7 +49,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check signed maximum.
 define i8 @f2(i8 *%src, i8 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -60,11 +60,11 @@ define i8 @f2(i8 *%src, i8 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -72,7 +72,7 @@ define i8 @f2(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: crjhe {{%r[0-9]+}}, %r3
@@ -85,7 +85,7 @@ define i8 @f2(i8 *%src, i8 %b) {
 
 ; Check unsigned minimum.
 define i8 @f3(i8 *%src, i8 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -97,11 +97,11 @@ define i8 @f3(i8 *%src, i8 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -109,7 +109,7 @@ define i8 @f3(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -122,7 +122,7 @@ define i8 @f3(i8 *%src, i8 %b) {
 
 ; Check unsigned maximum.
 define i8 @f4(i8 *%src, i8 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -134,11 +134,11 @@ define i8 @f4(i8 *%src, i8 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -146,7 +146,7 @@ define i8 @f4(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -160,15 +160,15 @@ define i8 @f4(i8 *%src, i8 %b) {
 ; Check the lowest useful signed minimum value.  We need to load 0x81000000
 ; into the source register.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 33024
 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw min i8 *%src, i8 -127 seq_cst
   ret i8 %res
@@ -177,15 +177,15 @@ define i8 @f5(i8 *%src) {
 ; Check the highest useful signed maximum value.  We need to load 0x7e000000
 ; into the source register.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32256
 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw max i8 *%src, i8 126 seq_cst
   ret i8 %res
@@ -194,15 +194,15 @@ define i8 @f6(i8 *%src) {
 ; Check the lowest useful unsigned minimum value.  We need to load 0x01000000
 ; into the source register.
 define i8 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 256
 ; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f7:
+; CHECK-SHIFT1-LABEL: f7:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f7:
+; CHECK-SHIFT2-LABEL: f7:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw umin i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -211,15 +211,15 @@ define i8 @f7(i8 *%src) {
 ; Check the highest useful unsigned maximum value.  We need to load 0xfe000000
 ; into the source register.
 define i8 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65024
 ; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f8:
+; CHECK-SHIFT1-LABEL: f8:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f8:
+; CHECK-SHIFT2-LABEL: f8:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw umax i8 *%src, i8 254 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
index b2c7bc9..c0ae883 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -24,11 +24,11 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -36,7 +36,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: crjle {{%r[0-9]+}}, %r3
@@ -49,7 +49,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check signed maximum.
 define i16 @f2(i16 *%src, i16 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -60,11 +60,11 @@ define i16 @f2(i16 *%src, i16 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -72,7 +72,7 @@ define i16 @f2(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: crjhe {{%r[0-9]+}}, %r3
@@ -85,7 +85,7 @@ define i16 @f2(i16 *%src, i16 %b) {
 
 ; Check unsigned minimum.
 define i16 @f3(i16 *%src, i16 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -97,11 +97,11 @@ define i16 @f3(i16 *%src, i16 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -109,7 +109,7 @@ define i16 @f3(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -122,7 +122,7 @@ define i16 @f3(i16 *%src, i16 %b) {
 
 ; Check unsigned maximum.
 define i16 @f4(i16 *%src, i16 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -134,11 +134,11 @@ define i16 @f4(i16 *%src, i16 %b) {
 ; CHECK: [[KEEP]]:
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -146,7 +146,7 @@ define i16 @f4(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
@@ -160,15 +160,15 @@ define i16 @f4(i16 *%src, i16 %b) {
 ; Check the lowest useful signed minimum value.  We need to load 0x80010000
 ; into the source register.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32769
 ; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw min i16 *%src, i16 -32767 seq_cst
   ret i16 %res
@@ -177,15 +177,15 @@ define i16 @f5(i16 *%src) {
 ; Check the highest useful signed maximum value.  We need to load 0x7ffe0000
 ; into the source register.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 32766
 ; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw max i16 *%src, i16 32766 seq_cst
   ret i16 %res
@@ -194,15 +194,15 @@ define i16 @f6(i16 *%src) {
 ; Check the lowest useful unsigned maximum value.  We need to load 0x00010000
 ; into the source register.
 define i16 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 1
 ; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f7:
+; CHECK-SHIFT1-LABEL: f7:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f7:
+; CHECK-SHIFT2-LABEL: f7:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw umin i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -211,15 +211,15 @@ define i16 @f7(i16 *%src) {
 ; Check the highest useful unsigned maximum value.  We need to load 0xfffe0000
 ; into the source register.
 define i16 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llilh [[SRC2:%r[0-9]+]], 65534
 ; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
 ; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f8:
+; CHECK-SHIFT1-LABEL: f8:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f8:
+; CHECK-SHIFT2-LABEL: f8:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw umax i16 *%src, i16 65534 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
index 4f7d820..3a9485a 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
@@ -4,14 +4,14 @@
 
 ; Check signed minium.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lr [[NEW:%r[0-9]+]], %r2
 ; CHECK: crjle %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lr [[NEW]], %r4
 ; CHECK: cs %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw min i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -19,14 +19,14 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check signed maximum.
 define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lr [[NEW:%r[0-9]+]], %r2
 ; CHECK: crjhe %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lr [[NEW]], %r4
 ; CHECK: cs %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw max i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -34,7 +34,7 @@ define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check unsigned minimum.
 define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: clr %r2, %r4
@@ -42,7 +42,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: jle [[KEEP:\..*]]
 ; CHECK: lr [[NEW]], %r4
 ; CHECK: cs %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw umin i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -50,7 +50,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check unsigned maximum.
 define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: clr %r2, %r4
@@ -58,7 +58,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
 ; CHECK: jhe [[KEEP:\..*]]
 ; CHECK: lr [[NEW]], %r4
 ; CHECK: cs %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw umax i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -66,7 +66,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the aligned CS range.
 define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: l %r2, 4092(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
 ; CHECK: br %r14
@@ -77,7 +77,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word up, which requires CSY.
 define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ly %r2, 4096(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
 ; CHECK: br %r14
@@ -88,7 +88,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the aligned CSY range.
 define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ly %r2, 524284(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
 ; CHECK: br %r14
@@ -99,7 +99,7 @@ define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word up, which needs separate address logic.
 define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, 524288
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -111,7 +111,7 @@ define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the negative aligned CSY range.
 define i32 @f9(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ly %r2, -4(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define i32 @f9(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the low end of the CSY range.
 define i32 @f10(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ly %r2, -524288(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
@@ -133,7 +133,7 @@ define i32 @f10(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word down, which needs separate address logic.
 define i32 @f11(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r3, -524292
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -145,7 +145,7 @@ define i32 @f11(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check that indexed addresses are not allowed.
 define i32 @f12(i32 %dummy, i64 %base, i64 %index, i32 %b) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agr %r3, %r4
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -156,17 +156,17 @@ define i32 @f12(i32 %dummy, i64 %base, i64 %index, i32 %b) {
   ret i32 %res
 }
 
-; Check that constants are forced into a register.
+; Check that constants are handled.
 define i32 @f13(i32 %dummy, i32 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: lhi [[LIMIT:%r[0-9]+]], 42
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lr [[NEW:%r[0-9]+]], %r2
 ; CHECK: crjle %r2, [[LIMIT]], [[KEEP:\..*]]
-; CHECK: lr [[NEW]], [[LIMIT]]
+; CHECK: lhi [[NEW]], 42
 ; CHECK: cs %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw min i32 *%ptr, i32 42 seq_cst
   ret i32 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
index cd35ab0..ebed147 100644
--- a/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
@@ -4,14 +4,14 @@
 
 ; Check signed minium.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lgr [[NEW:%r[0-9]+]], %r2
 ; CHECK: cgrjle %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lgr [[NEW]], %r4
 ; CHECK: csg %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw min i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -19,14 +19,14 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check signed maximum.
 define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lgr [[NEW:%r[0-9]+]], %r2
 ; CHECK: cgrjhe %r2, %r4, [[KEEP:\..*]]
 ; CHECK: lgr [[NEW]], %r4
 ; CHECK: csg %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw max i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -34,7 +34,7 @@ define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check unsigned minimum.
 define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: clgr %r2, %r4
@@ -42,7 +42,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: jle [[KEEP:\..*]]
 ; CHECK: lgr [[NEW]], %r4
 ; CHECK: csg %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw umin i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -50,7 +50,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check unsigned maximum.
 define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: clgr %r2, %r4
@@ -58,7 +58,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: jhe [[KEEP:\..*]]
 ; CHECK: lgr [[NEW]], %r4
 ; CHECK: csg %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw umax i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -66,7 +66,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the high end of the aligned CSG range.
 define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lg %r2, 524280(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3)
 ; CHECK: br %r14
@@ -77,7 +77,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the next doubleword up, which requires separate address logic.
 define i64 @f6(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -89,7 +89,7 @@ define i64 @f6(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the low end of the CSG range.
 define i64 @f7(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lg %r2, -524288(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
@@ -100,7 +100,7 @@ define i64 @f7(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the next doubleword down, which requires separate address logic.
 define i64 @f8(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524296
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -112,7 +112,7 @@ define i64 @f8(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check that indexed addresses are not allowed.
 define i64 @f9(i64 %dummy, i64 %base, i64 %index, i64 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agr %r3, %r4
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -123,17 +123,17 @@ define i64 @f9(i64 %dummy, i64 %base, i64 %index, i64 %b) {
   ret i64 %res
 }
 
-; Check that constants are forced into a register.
+; Check that constants are handled.
 define i64 @f10(i64 %dummy, i64 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lghi [[LIMIT:%r[0-9]+]], 42
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LOOP:\.[^:]*]]:
 ; CHECK: lgr [[NEW:%r[0-9]+]], %r2
 ; CHECK: cgrjle %r2, [[LIMIT]], [[KEEP:\..*]]
-; CHECK: lgr [[NEW]], [[LIMIT]]
+; CHECK: lghi [[NEW]], 42
 ; CHECK: csg %r2, [[NEW]], 0(%r3)
-; CHECK: jlh [[LOOP]]
+; CHECK: jl [[LOOP]]
 ; CHECK: br %r14
   %res = atomicrmw min i64 *%ptr, i64 42 seq_cst
   ret i64 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-01.ll b/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
index b5f2c10..db5bb8f 100644
--- a/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-nand-01.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -23,11 +23,11 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -35,7 +35,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: oilf %r3, 16777215
 ; CHECK-SHIFT2: rll
@@ -49,7 +49,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We AND the rotated word with 0x80ffffff.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -59,11 +59,11 @@ define i8 @f2(i8 *%src) {
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -71,7 +71,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -79,14 +79,14 @@ define i8 @f2(i8 *%src) {
 
 ; Check NANDs of -2 (-1 isn't useful).  We AND the rotated word with 0xfeffffff.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh [[ROT]], 65279
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 -2 seq_cst
   ret i8 %res
@@ -94,14 +94,14 @@ define i8 @f3(i8 *%src) {
 
 ; Check NANDs of 1.  We AND the rotated word with 0x01ffffff.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilh [[ROT]], 511
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -109,14 +109,14 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We AND the rotated word with 0x7fffffff.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nilh [[ROT]], 32767
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -125,14 +125,14 @@ define i8 @f5(i8 *%src) {
 ; Check NANDs of a large unsigned value.  We AND the rotated word with
 ; 0xfdffffff.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nilh [[ROT]], 65023
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i8 *%src, i8 253 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-02.ll b/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
index 7a37a38..6141543 100644
--- a/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-nand-02.ll
@@ -13,7 +13,7 @@
 ;   before being used, and that the low bits are set to 1.  This sequence is
 ;   independent of the other loop prologue instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -23,11 +23,11 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -35,7 +35,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: oill %r3, 65535
 ; CHECK-SHIFT2: rll
@@ -49,7 +49,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We AND the rotated word with 0x8000ffff.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -59,11 +59,11 @@ define i16 @f2(i16 *%src) {
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -71,7 +71,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -79,14 +79,14 @@ define i16 @f2(i16 *%src) {
 
 ; Check NANDs of -2 (-1 isn't useful).  We AND the rotated word with 0xfffeffff.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh [[ROT]], 65534
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 -2 seq_cst
   ret i16 %res
@@ -94,14 +94,14 @@ define i16 @f3(i16 *%src) {
 
 ; Check ANDs of 1.  We AND the rotated word with 0x0001ffff.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilh [[ROT]], 1
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -109,14 +109,14 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We AND the rotated word with 0x7fffffff.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nilh [[ROT]], 32767
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -125,14 +125,14 @@ define i16 @f5(i16 *%src) {
 ; Check NANDs of a large unsigned value.  We AND the rotated word with
 ; 0xfffdffff.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nilh [[ROT]], 65533
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw nand i16 *%src, i16 65533 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-03.ll b/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
index 56c2416..c7a6691 100644
--- a/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-nand-03.ll
@@ -1,17 +1,17 @@
 ; Test 32-bit atomic NANDs.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check NANDs of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
 ; CHECK: nr %r0, %r4
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw nand i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -19,14 +19,14 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check NANDs of 1.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
 ; CHECK: nilf %r0, 1
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw nand i32 *%src, i32 1 seq_cst
   ret i32 %res
@@ -34,7 +34,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check NANDs of the low end of the NILH range.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nilh %r0, 0
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which must use NILF.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nilf %r0, 65536
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
@@ -54,7 +54,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
 
 ; Check the largest useful NILL value.
 define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: nill %r0, 65534
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
 
 ; Check the low end of the NILL range.
 define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: nill %r0, 0
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
@@ -74,7 +74,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
 
 ; Check the largest useful NILH value, which is one less than the above.
 define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: nilh %r0, 65534
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
 
 ; Check the highest useful NILF value, which is one less than the above.
 define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: nilf %r0, 4294901758
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-04.ll b/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
index dee661c..91fe639 100644
--- a/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-nand-04.ll
@@ -1,10 +1,10 @@
 ; Test 64-bit atomic NANDs.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check NANDs of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
@@ -12,171 +12,165 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw nand i64 *%src, i64 %b seq_cst
   ret i64 %res
 }
 
-; Check NANDs of 1, which must be done using a register.
+; Check NANDs of 1, which are done using a register.  (We could use RISBG
+; instead, but that isn't implemented yet.)
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ngr
 ; CHECK: br %r14
   %res = atomicrmw nand i64 *%src, i64 1 seq_cst
   ret i64 %res
 }
 
-; Check the low end of the NIHF range.
+; Check the equivalent of NIHF with 1, which can use RISBG instead.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
-; CHECK: lgr %r0, %r2
-; CHECK: nihf %r0, 0
+; CHECK: risbg %r0, %r2, 31, 191, 0
 ; CHECK: lcgr %r0, %r0
 ; CHECK: aghi %r0, -1
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
-  %res = atomicrmw nand i64 *%src, i64 4294967295 seq_cst
+  %res = atomicrmw nand i64 *%src, i64 8589934591 seq_cst
   ret i64 %res
 }
 
-; Check the next value up, which must use a register.
+; Check the lowest NIHF value outside the range of RISBG.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
-; CHECK: ngr
+; CHECK-LABEL: f4:
+; CHECK: lg %r2, 0(%r3)
+; CHECK: [[LABEL:\.[^:]*]]:
+; CHECK: lgr %r0, %r2
+; CHECK: nihf %r0, 2
+; CHECK: lcgr %r0, %r0
+; CHECK: aghi %r0, -1
+; CHECK: csg %r2, %r0, 0(%r3)
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
-  %res = atomicrmw nand i64 *%src, i64 4294967296 seq_cst
+  %res = atomicrmw nand i64 *%src, i64 12884901887 seq_cst
   ret i64 %res
 }
 
-; Check the low end of the NIHH range.
+; Check the next value up, which must use a register.
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
-; CHECK: nihh %r0, 0
-; CHECK: lcgr %r0, %r0
-; CHECK: aghi %r0, -1
+; CHECK-LABEL: f5:
+; CHECK: ngr
 ; CHECK: br %r14
-  %res = atomicrmw nand i64 *%src, i64 281474976710655 seq_cst
+  %res = atomicrmw nand i64 *%src, i64 12884901888 seq_cst
   ret i64 %res
 }
 
-; Check the next value up, which must use a register.
+; Check the lowest NIHH value outside the range of RISBG.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
-; CHECK: ngr
+; CHECK-LABEL: f6:
+; CHECK: nihh {{%r[0-5]}}, 2
 ; CHECK: br %r14
-  %res = atomicrmw nand i64 *%src, i64 281474976710656 seq_cst
+  %res = atomicrmw nand i64 *%src, i64 844424930131967 seq_cst
   ret i64 %res
 }
 
-; Check the highest useful NILL value.
+; Check the next value up, which must use a register.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
-; CHECK: nill %r0, 65534
-; CHECK: lcgr %r0, %r0
-; CHECK: aghi %r0, -1
+; CHECK-LABEL: f7:
+; CHECK: ngr
 ; CHECK: br %r14
-  %res = atomicrmw nand i64 *%src, i64 -2 seq_cst
+  %res = atomicrmw nand i64 *%src, i64 281474976710656 seq_cst
   ret i64 %res
 }
 
-; Check the low end of the NILL range.
+; Check the highest NILL value outside the range of RISBG.
 define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
-; CHECK: nill %r0, 0
-; CHECK: lcgr %r0, %r0
-; CHECK: aghi %r0, -1
+; CHECK-LABEL: f8:
+; CHECK: nill {{%r[0-5]}}, 65530
 ; CHECK: br %r14
-  %res = atomicrmw nand i64 *%src, i64 -65536 seq_cst
+  %res = atomicrmw nand i64 *%src, i64 -6 seq_cst
   ret i64 %res
 }
 
-; Check the highest useful NILH value, which is one less than the above.
+; Check the lowest NILL value outside the range of RISBG.
 define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
-; CHECK: nilh %r0, 65534
-; CHECK: lcgr %r0, %r0
-; CHECK: aghi %r0, -1
+; CHECK-LABEL: f9:
+; CHECK: nill {{%r[0-5]}}, 2
 ; CHECK: br %r14
-  %res = atomicrmw nand i64 *%src, i64 -65537 seq_cst
+  %res = atomicrmw nand i64 *%src, i64 -65534 seq_cst
   ret i64 %res
 }
 
-; Check the highest useful NILF value, which is one less than the above.
+; Check the highest useful NILF value.
 define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
-; CHECK: nilf %r0, 4294901758
-; CHECK: lcgr %r0, %r0
-; CHECK: aghi %r0, -1
+; CHECK-LABEL: f10:
+; CHECK: nilf {{%r[0-5]}}, 4294901758
 ; CHECK: br %r14
   %res = atomicrmw nand i64 *%src, i64 -65538 seq_cst
   ret i64 %res
 }
 
-; Check the low end of the NILH range.
+; Check the highest NILH value outside the range of RISBG.
 define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
-; CHECK: nilh %r0, 0
-; CHECK: lcgr %r0, %r0
-; CHECK: aghi %r0, -1
+; CHECK-LABEL: f11:
+; CHECK: nilh {{%r[0-5]}}, 65530
 ; CHECK: br %r14
-  %res = atomicrmw nand i64 *%src, i64 -4294901761 seq_cst
+  %res = atomicrmw nand i64 *%src, i64 -327681 seq_cst
   ret i64 %res
 }
 
-; Check the low end of the NILF range.
+; Check the lowest NILH value outside the range of RISBG.
 define i64 @f12(i64 %dummy, i64 *%src) {
-; CHECK: f12:
-; CHECK: nilf %r0, 0
-; CHECK: lcgr %r0, %r0
-; CHECK: aghi %r0, -1
+; CHECK-LABEL: f12:
+; CHECK: nilh {{%r[0-5]}}, 2
 ; CHECK: br %r14
-  %res = atomicrmw nand i64 *%src, i64 -4294967296 seq_cst
+  %res = atomicrmw nand i64 *%src, i64 -4294770689 seq_cst
   ret i64 %res
 }
 
-; Check the highest useful NIHL value, which is one less than the above.
+; Check the lowest NILF value outside the range of RISBG.
 define i64 @f13(i64 %dummy, i64 *%src) {
-; CHECK: f13:
-; CHECK: nihl %r0, 65534
-; CHECK: lcgr %r0, %r0
-; CHECK: aghi %r0, -1
+; CHECK-LABEL: f13:
+; CHECK: nilf {{%r[0-5]}}, 2
 ; CHECK: br %r14
-  %res = atomicrmw nand i64 *%src, i64 -4294967297 seq_cst
+  %res = atomicrmw nand i64 *%src, i64 -4294967294 seq_cst
   ret i64 %res
 }
 
-; Check the low end of the NIHL range.
+; Check the highest NIHL value outside the range of RISBG.
 define i64 @f14(i64 %dummy, i64 *%src) {
-; CHECK: f14:
-; CHECK: nihl %r0, 0
-; CHECK: lcgr %r0, %r0
-; CHECK: aghi %r0, -1
+; CHECK-LABEL: f14:
+; CHECK: nihl {{%r[0-5]}}, 65530
 ; CHECK: br %r14
-  %res = atomicrmw nand i64 *%src, i64 -281470681743361 seq_cst
+  %res = atomicrmw nand i64 *%src, i64 -21474836481 seq_cst
   ret i64 %res
 }
 
-; Check the highest useful NIHH value, which is 1<<32 less than the above.
+; Check the lowest NIHL value outside the range of RISBG.
 define i64 @f15(i64 %dummy, i64 *%src) {
-; CHECK: f15:
-; CHECK: nihh %r0, 65534
-; CHECK: lcgr %r0, %r0
-; CHECK: aghi %r0, -1
+; CHECK-LABEL: f15:
+; CHECK: nihl {{%r[0-5]}}, 2
 ; CHECK: br %r14
-  %res = atomicrmw nand i64 *%src, i64 -281474976710657 seq_cst
+  %res = atomicrmw nand i64 *%src, i64 -281462091808769 seq_cst
   ret i64 %res
 }
 
-; Check the highest useful NIHF value, which is 1<<32 less than the above.
+; Check the highest NIHH value outside the range of RISBG.
 define i64 @f16(i64 %dummy, i64 *%src) {
-; CHECK: f16:
-; CHECK: nihf %r0, 4294901758
-; CHECK: lcgr %r0, %r0
-; CHECK: aghi %r0, -1
+; CHECK-LABEL: f16:
+; CHECK: nihh {{%r[0-5]}}, 65530
+; CHECK: br %r14
+  %res = atomicrmw nand i64 *%src, i64 -1407374883553281 seq_cst
+  ret i64 %res
+}
+
+; Check the highest useful NIHF value.
+define i64 @f17(i64 %dummy, i64 *%src) {
+; CHECK-LABEL: f17:
+; CHECK: nihf {{%r[0-5]}}, 4294901758
 ; CHECK: br %r14
   %res = atomicrmw nand i64 *%src, i64 -281479271677953 seq_cst
   ret i64 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-01.ll b/test/CodeGen/SystemZ/atomicrmw-or-01.ll
index f0313d6..caba621 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-01.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -22,11 +22,11 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: or [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: or {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We OR the rotated word with 0x80000000.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -56,11 +56,11 @@ define i8 @f2(i8 *%src) {
 ; CHECK: oilh [[ROT]], 32768
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
 
 ; Check ORs of -2 (-1 isn't useful).  We OR the rotated word with 0xfe000000.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oilh [[ROT]], 65024
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 -2 seq_cst
   ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
 
 ; Check ORs of 1.  We OR the rotated word with 0x01000000.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilh [[ROT]], 256
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We OR the rotated word with 0x7f000000.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilh [[ROT]], 32512
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
 ; Check ORs of a large unsigned value.  We OR the rotated word with
 ; 0xfd000000.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilh [[ROT]], 64768
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i8 *%src, i8 253 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-02.ll b/test/CodeGen/SystemZ/atomicrmw-or-02.ll
index 5c3f286..877c642 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-02.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -22,11 +22,11 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: or [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: or {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We OR the rotated word with 0x80000000.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -56,11 +56,11 @@ define i16 @f2(i16 *%src) {
 ; CHECK: oilh [[ROT]], 32768
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
 
 ; Check ORs of -2 (-1 isn't useful).  We OR the rotated word with 0xfffe0000.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oilh [[ROT]], 65534
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 -2 seq_cst
   ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
 
 ; Check ORs of 1.  We OR the rotated word with 0x00010000.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilh [[ROT]], 1
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We OR the rotated word with 0x7fff0000.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilh [[ROT]], 32767
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
 ; Check ORs of a large unsigned value.  We OR the rotated word with
 ; 0xfffd0000.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilh [[ROT]], 65533
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw or i16 *%src, i16 65533 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-03.ll b/test/CodeGen/SystemZ/atomicrmw-or-03.ll
index 1def200..9a0aa86 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-03.ll
@@ -1,16 +1,16 @@
 ; Test 32-bit atomic ORs.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check ORs of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
 ; CHECK: or %r0, %r4
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -18,13 +18,13 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the lowest useful OILL value.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
 ; CHECK: oill %r0, 1
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 1 seq_cst
   ret i32 %res
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check the high end of the OILL range.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oill %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 65535 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check the lowest useful OILH value, which is the next value up.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilh %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 65536 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
 
 ; Check the lowest useful OILF value, which is the next value up.
 define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilf %r0, 65537
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 65537 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
 
 ; Check the high end of the OILH range.
 define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilh %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 -65536 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which must use OILF.
 define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oilf %r0, 4294901761
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 -65535 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
 
 ; Check the largest useful OILF value.
 define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: oilf %r0, 4294967294
 ; CHECK: br %r14
   %res = atomicrmw or i32 *%src, i32 -2 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-or-04.ll b/test/CodeGen/SystemZ/atomicrmw-or-04.ll
index be0b23c..dbc0f11 100644
--- a/test/CodeGen/SystemZ/atomicrmw-or-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-or-04.ll
@@ -1,16 +1,16 @@
 ; Test 64-bit atomic ORs.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check ORs of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lgr %r0, %r2
 ; CHECK: ogr %r0, %r4
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -18,13 +18,13 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the lowest useful OILL value.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lgr %r0, %r2
 ; CHECK: oill %r0, 1
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 1 seq_cst
   ret i64 %res
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OILL range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oill %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 65535 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful OILH value, which is the next value up.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilh %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 65536 seq_cst
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful OILF value, which is the next value up again.
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilf %r0, 65537
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 65537 seq_cst
@@ -59,7 +59,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OILH range.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilh %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 4294901760 seq_cst
@@ -68,7 +68,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use OILF.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oilf %r0, 4294901761
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 4294901761 seq_cst
@@ -77,7 +77,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OILF range.
 define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: oilf %r0, 4294967295
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 4294967295 seq_cst
@@ -86,7 +86,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful OIHL value, which is one greater than above.
 define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: oihl %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 4294967296 seq_cst
@@ -96,7 +96,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
 ; Check the next value up, which must use a register.  (We could use
 ; combinations of OIH* and OIL* instead, but that isn't implemented.)
 define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ogr
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 4294967297 seq_cst
@@ -105,7 +105,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OIHL range.
 define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: oihl %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 281470681743360 seq_cst
@@ -114,7 +114,7 @@ define i64 @f11(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful OIHH value, which is 1<<32 greater than above.
 define i64 @f12(i64 %dummy, i64 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: oihh %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 281474976710656 seq_cst
@@ -123,7 +123,7 @@ define i64 @f12(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful OIHF value, which is 1<<32 greater again.
 define i64 @f13(i64 %dummy, i64 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: oihf %r0, 65537
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 281479271677952 seq_cst
@@ -132,7 +132,7 @@ define i64 @f13(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OIHH range.
 define i64 @f14(i64 %dummy, i64 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: oihh %r0, 65535
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 18446462598732840960 seq_cst
@@ -141,7 +141,7 @@ define i64 @f14(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register.
 define i64 @f15(i64 %dummy, i64 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: ogr
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 18446462598732840961 seq_cst
@@ -150,7 +150,7 @@ define i64 @f15(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the OIHF range.
 define i64 @f16(i64 %dummy, i64 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: oihf %r0, 4294967295
 ; CHECK: br %r14
   %res = atomicrmw or i64 *%src, i64 -4294967296 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-01.ll b/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
index 31cbdf5..2c08ebd 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-01.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -22,11 +22,11 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: sr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: sr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -56,11 +56,11 @@ define i8 @f2(i8 *%src) {
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
 
 ; Check subtraction of -1.  We add 0x01000000 to the rotated word.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: afi [[ROT]], 16777216
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 -1 seq_cst
   ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
 
 ; Check subtraction of -1.  We add 0xff000000 to the rotated word.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi [[ROT]], -16777216
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We add 0x81000000 to the rotated word.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi [[ROT]], -2130706432
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
 ; Check subtraction of a large unsigned value.  We add 0x02000000 to the
 ; rotated word.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi [[ROT]], 33554432
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i8 *%src, i8 254 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-02.ll b/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
index f72bf4a..f82ebd9 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-02.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -22,11 +22,11 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: sr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: sr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We add 0x80000000 to the rotated word.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -56,11 +56,11 @@ define i16 @f2(i16 *%src) {
 ; CHECK: afi [[ROT]], -2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
 
 ; Check subtraction of -1.  We add 0x00010000 to the rotated word.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: afi [[ROT]], 65536
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 -1 seq_cst
   ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
 
 ; Check subtraction of 1.  We add 0xffff0000 to the rotated word.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi [[ROT]], -65536
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We add 0x80010000 to the rotated word.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi [[ROT]], -2147418112
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
 ; Check subtraction of a large unsigned value.  We add 0x00020000 to the
 ; rotated word.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi [[ROT]], 131072
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw sub i16 *%src, i16 65534 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-03.ll b/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
index c2821ad..a3031c6 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-03.ll
@@ -1,16 +1,16 @@
 ; Test 32-bit atomic subtractions.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check subtraction of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lr %r0, %r2
 ; CHECK: sr %r0, %r4
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -18,13 +18,13 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check subtraction of 1, which can use AHI.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lr %r0, %r2
 ; CHECK: ahi %r0, -1
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 1 seq_cst
   ret i32 %res
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check the low end of the AHI range.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ahi %r0, -32768
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 32768 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check the next value down, which must use AFI.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi %r0, -32769
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 32769 seq_cst
@@ -50,7 +50,7 @@ define i32 @f4(i32 %dummy, i32 *%src) {
 
 ; Check the low end of the AFI range.
 define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi %r0, -2147483648
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 2147483648 seq_cst
@@ -59,7 +59,7 @@ define i32 @f5(i32 %dummy, i32 *%src) {
 
 ; Check the next value up, which gets treated as a positive operand.
 define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: afi %r0, 2147483647
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 2147483649 seq_cst
@@ -68,7 +68,7 @@ define i32 @f6(i32 %dummy, i32 *%src) {
 
 ; Check subtraction of -1, which can use AHI.
 define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ahi %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 -1 seq_cst
@@ -77,7 +77,7 @@ define i32 @f7(i32 %dummy, i32 *%src) {
 
 ; Check the high end of the AHI range.
 define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ahi %r0, 32767
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 -32767 seq_cst
@@ -86,7 +86,7 @@ define i32 @f8(i32 %dummy, i32 *%src) {
 
 ; Check the next value down, which must use AFI instead.
 define i32 @f9(i32 %dummy, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: afi %r0, 32768
 ; CHECK: br %r14
   %res = atomicrmw sub i32 *%src, i32 -32768 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-04.ll b/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
index 6b3e1c9..911648b 100644
--- a/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-sub-04.ll
@@ -1,16 +1,16 @@
 ; Test 64-bit atomic subtractions.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check subtraction of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
 ; CHECK: sgr %r0, %r4
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -18,13 +18,13 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check subtraction of 1, which can use AGHI.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: lgr %r0, %r2
 ; CHECK: aghi %r0, -1
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 1 seq_cst
   ret i64 %res
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the AGHI range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r0, -32768
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 32768 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use AGFI.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r0, -32769
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 32769 seq_cst
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 
 ; Check the low end of the AGFI range.
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r0, -2147483648
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 2147483648 seq_cst
@@ -59,7 +59,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register operation.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sgr
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 2147483649 seq_cst
@@ -68,7 +68,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check subtraction of -1, which can use AGHI.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: aghi %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 -1 seq_cst
@@ -77,7 +77,7 @@ define i64 @f7(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the AGHI range.
 define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r0, 32767
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 -32767 seq_cst
@@ -86,7 +86,7 @@ define i64 @f8(i64 %dummy, i64 *%src) {
 
 ; Check the next value down, which must use AGFI instead.
 define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r0, 32768
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 -32768 seq_cst
@@ -95,7 +95,7 @@ define i64 @f9(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the AGFI range.
 define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r0, 2147483647
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 -2147483647 seq_cst
@@ -104,7 +104,7 @@ define i64 @f10(i64 %dummy, i64 *%src) {
 
 ; Check the next value down, which must use a register operation.
 define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sgr
 ; CHECK: br %r14
   %res = atomicrmw sub i64 *%src, i64 -2147483648 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
index 502fa2f..52575c6 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll
@@ -11,7 +11,7 @@
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -20,11 +20,11 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: risbg [[ROT]], %r3, 32, 39, 24
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
 ; CHECK-SHIFT-NOT: %r3
 ; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT-NOT: %r3
@@ -43,12 +43,12 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; Check exchange with a constant.  We should force the constant into
 ; a register and use the sequence above.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi [[VALUE:%r[0-9]+]], 88
 ; CHECK: risbg {{%r[0-9]+}}, [[VALUE]], 32, 39, 24
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
 ; CHECK-SHIFT: br %r14
   %res = atomicrmw xchg i8 *%src, i8 88 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
index 55ede41..04be623 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll
@@ -11,7 +11,7 @@
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -20,11 +20,11 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: risbg [[ROT]], %r3, 32, 47, 16
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
 ; CHECK-SHIFT-NOT: %r3
 ; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT-NOT: %r3
@@ -43,12 +43,12 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; Check exchange with a constant.  We should force the constant into
 ; a register and use the sequence above.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi [[VALUE:%r[0-9]+]], -25536
 ; CHECK: risbg {{%r[0-9]+}}, [[VALUE]], 32, 47, 16
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
 ; CHECK-SHIFT: br %r14
   %res = atomicrmw xchg i16 *%src, i16 40000 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
index 4a48826..a602a02 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll
@@ -4,11 +4,11 @@
 
 ; Check register exchange.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: cs %r2, %r4, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xchg i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -16,7 +16,7 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the aligned CS range.
 define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 4092(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word up, which requires CSY.
 define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ly %r2, 4096(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
 ; CHECK: br %r14
@@ -38,7 +38,7 @@ define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the aligned CSY range.
 define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ly %r2, 524284(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word up, which needs separate address logic.
 define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, 524288
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -61,7 +61,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the high end of the negative aligned CSY range.
 define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ly %r2, -4(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
 ; CHECK: br %r14
@@ -72,7 +72,7 @@ define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the low end of the CSY range.
 define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ly %r2, -524288(%r3)
 ; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the next word down, which needs separate address logic.
 define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524292
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -95,7 +95,7 @@ define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check that indexed addresses are not allowed.
 define i32 @f9(i32 %dummy, i64 %base, i64 %index, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agr %r3, %r4
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
@@ -109,12 +109,12 @@ define i32 @f9(i32 %dummy, i64 %base, i64 %index, i32 %b) {
 ; Check exchange of a constant.  We should force it into a register and
 ; use the sequence above.
 define i32 @f10(i32 %dummy, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llill [[VALUE:%r[0-9+]]], 40000
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: cs %r2, [[VALUE]], 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xchg i32 *%src, i32 40000 seq_cst
   ret i32 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
index ac1f6cd..80c0eeb 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll
@@ -4,11 +4,11 @@
 
 ; Check register exchange.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: csg %r2, %r4, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xchg i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -16,7 +16,7 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the high end of the aligned CSG range.
 define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 524280(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3)
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the next doubleword up, which requires separate address logic.
 define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r3, 524288
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -39,7 +39,7 @@ define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the low end of the CSG range.
 define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lg %r2, -524288(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3)
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the next doubleword down, which requires separate address logic.
 define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, -524296
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -62,7 +62,7 @@ define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check that indexed addresses are not allowed.
 define i64 @f6(i64 %dummy, i64 %base, i64 %index, i64 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agr %r3, %r4
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
@@ -76,12 +76,12 @@ define i64 @f6(i64 %dummy, i64 %base, i64 %index, i64 %b) {
 ; Check exchange of a constant.  We should force it into a register and
 ; use the sequence above.
 define i64 @f7(i64 %dummy, i64 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llilf [[VALUE:%r[0-9+]]], 3000000000
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^:]*]]:
 ; CHECK: csg %r2, [[VALUE]], 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xchg i64 *%ptr, i64 3000000000 seq_cst
   ret i64 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-01.ll b/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
index 4801e80..e8fef2d 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-01.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -22,11 +22,11 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK: xr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 24
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: xr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i8 @f1(i8 *%src, i8 %b) {
 
 ; Check the minimum signed value.  We XOR the rotated word with 0x80000000.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -56,11 +56,11 @@ define i8 @f2(i8 *%src) {
 ; CHECK: xilf [[ROT]], 2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i8 @f2(i8 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 -128 seq_cst
   ret i8 %res
@@ -76,13 +76,13 @@ define i8 @f2(i8 *%src) {
 
 ; Check XORs of -1.  We XOR the rotated word with 0xff000000.
 define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xilf [[ROT]], 4278190080
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 -1 seq_cst
   ret i8 %res
@@ -90,13 +90,13 @@ define i8 @f3(i8 *%src) {
 
 ; Check XORs of 1.  We XOR the rotated word with 0x01000000.
 define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xilf [[ROT]], 16777216
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 1 seq_cst
   ret i8 %res
@@ -104,13 +104,13 @@ define i8 @f4(i8 *%src) {
 
 ; Check the maximum signed value.  We XOR the rotated word with 0x7f000000.
 define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xilf [[ROT]], 2130706432
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 127 seq_cst
   ret i8 %res
@@ -119,13 +119,13 @@ define i8 @f5(i8 *%src) {
 ; Check XORs of a large unsigned value.  We XOR the rotated word with
 ; 0xfd000000.
 define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xilf [[ROT]], 4244635648
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i8 *%src, i8 253 seq_cst
   ret i8 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-02.ll b/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
index 7a525a8..9405c2e 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-02.ll
@@ -13,7 +13,7 @@
 ;   before being used.  This shift is independent of the other loop prologue
 ;   instructions.
 define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -22,11 +22,11 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK: xr [[ROT]], %r3
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -34,7 +34,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
 ; CHECK-SHIFT2: sll %r3, 16
 ; CHECK-SHIFT2: rll
 ; CHECK-SHIFT2: xr {{%r[0-9]+}}, %r3
@@ -47,7 +47,7 @@ define i16 @f1(i16 *%src, i16 %b) {
 
 ; Check the minimum signed value.  We XOR the rotated word with 0x80000000.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK: nill %r2, 65532
 ; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
@@ -56,11 +56,11 @@ define i16 @f2(i16 *%src) {
 ; CHECK: xilf [[ROT]], 2147483648
 ; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
 ; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
 ; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT1: rll
@@ -68,7 +68,7 @@ define i16 @f2(i16 *%src) {
 ; CHECK-SHIFT1: rll
 ; CHECK-SHIFT1: br %r14
 ;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 -32768 seq_cst
   ret i16 %res
@@ -76,13 +76,13 @@ define i16 @f2(i16 *%src) {
 
 ; Check XORs of -1.  We XOR the rotated word with 0xffff0000.
 define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xilf [[ROT]], 4294901760
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 -1 seq_cst
   ret i16 %res
@@ -90,13 +90,13 @@ define i16 @f3(i16 *%src) {
 
 ; Check XORs of 1.  We XOR the rotated word with 0x00010000.
 define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xilf [[ROT]], 65536
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 1 seq_cst
   ret i16 %res
@@ -104,13 +104,13 @@ define i16 @f4(i16 *%src) {
 
 ; Check the maximum signed value.  We XOR the rotated word with 0x7fff0000.
 define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xilf [[ROT]], 2147418112
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 32767 seq_cst
   ret i16 %res
@@ -119,13 +119,13 @@ define i16 @f5(i16 *%src) {
 ; Check XORs of a large unsigned value.  We XOR the rotated word with
 ; 0xfffd0000.
 define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xilf [[ROT]], 4294770688
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
 ; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
 ; CHECK-SHIFT2: br %r14
   %res = atomicrmw xor i16 *%src, i16 65533 seq_cst
   ret i16 %res
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-03.ll b/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
index 0c19515..d719d0b 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-03.ll
@@ -1,16 +1,16 @@
 ; Test 32-bit atomic XORs.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check XORs of a variable.
 define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
 ; CHECK: xr %r0, %r4
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xor i32 *%src, i32 %b seq_cst
   ret i32 %res
@@ -18,13 +18,13 @@ define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Check the lowest useful constant.
 define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lr %r0, %r2
 ; CHECK: xilf %r0, 1
 ; CHECK: cs %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xor i32 *%src, i32 1 seq_cst
   ret i32 %res
@@ -32,7 +32,7 @@ define i32 @f2(i32 %dummy, i32 *%src) {
 
 ; Check an arbitrary constant.
 define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xilf %r0, 3000000000
 ; CHECK: br %r14
   %res = atomicrmw xor i32 *%src, i32 3000000000 seq_cst
@@ -41,7 +41,7 @@ define i32 @f3(i32 %dummy, i32 *%src) {
 
 ; Check bitwise negation.
 define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
   %res = atomicrmw xor i32 *%src, i32 -1 seq_cst
diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-04.ll b/test/CodeGen/SystemZ/atomicrmw-xor-04.ll
index 6487b88..c17a879 100644
--- a/test/CodeGen/SystemZ/atomicrmw-xor-04.ll
+++ b/test/CodeGen/SystemZ/atomicrmw-xor-04.ll
@@ -1,16 +1,16 @@
 ; Test 64-bit atomic XORs.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check XORs of a variable.
 define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lgr %r0, %r2
 ; CHECK: xgr %r0, %r4
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 %b seq_cst
   ret i64 %res
@@ -18,13 +18,13 @@ define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
 
 ; Check the lowest useful XILF value.
 define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 0(%r3)
 ; CHECK: [[LABEL:\.[^ ]*]]:
 ; CHECK: lgr %r0, %r2
 ; CHECK: xilf %r0, 1
 ; CHECK: csg %r2, %r0, 0(%r3)
-; CHECK: jlh [[LABEL]]
+; CHECK: jl [[LABEL]]
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 1 seq_cst
   ret i64 %res
@@ -32,7 +32,7 @@ define i64 @f2(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the XILF range.
 define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xilf %r0, 4294967295
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 4294967295 seq_cst
@@ -41,7 +41,7 @@ define i64 @f3(i64 %dummy, i64 *%src) {
 
 ; Check the lowest useful XIHF value, which is one greater than above.
 define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xihf %r0, 1
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 4294967296 seq_cst
@@ -51,7 +51,7 @@ define i64 @f4(i64 %dummy, i64 *%src) {
 ; Check the next value up, which must use a register.  (We could use
 ; combinations of XIH* and XIL* instead, but that isn't implemented.)
 define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xgr
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 4294967297 seq_cst
@@ -60,7 +60,7 @@ define i64 @f5(i64 %dummy, i64 *%src) {
 
 ; Check the high end of the XIHF range.
 define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xihf %r0, 4294967295
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 -4294967296 seq_cst
@@ -69,7 +69,7 @@ define i64 @f6(i64 %dummy, i64 *%src) {
 
 ; Check the next value up, which must use a register.
 define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: xgr
 ; CHECK: br %r14
   %res = atomicrmw xor i64 *%src, i64 -4294967295 seq_cst
diff --git a/test/CodeGen/SystemZ/branch-01.ll b/test/CodeGen/SystemZ/branch-01.ll
index f201ddd..12ed2d3 100644
--- a/test/CodeGen/SystemZ/branch-01.ll
+++ b/test/CodeGen/SystemZ/branch-01.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i8 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: mvi 0(%r2), 1
 ; CHECK: j .L[[LABEL]]
diff --git a/test/CodeGen/SystemZ/branch-02.ll b/test/CodeGen/SystemZ/branch-02.ll
index 9f71c05..38b5d27 100644
--- a/test/CodeGen/SystemZ/branch-02.ll
+++ b/test/CodeGen/SystemZ/branch-02.ll
@@ -5,7 +5,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(i32 *%src, i32 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
@@ -20,7 +20,7 @@ exit:
 }
 
 define void @f2(i32 *%src, i32 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
@@ -35,7 +35,7 @@ exit:
 }
 
 define void @f3(i32 *%src, i32 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
@@ -50,7 +50,7 @@ exit:
 }
 
 define void @f4(i32 *%src, i32 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
@@ -65,7 +65,7 @@ exit:
 }
 
 define void @f5(i32 *%src, i32 %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
@@ -80,7 +80,7 @@ exit:
 }
 
 define void @f6(i32 *%src, i32 %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: c %r3, 0(%r2)
diff --git a/test/CodeGen/SystemZ/branch-03.ll b/test/CodeGen/SystemZ/branch-03.ll
index 9d00f6e..ef31a9c 100644
--- a/test/CodeGen/SystemZ/branch-03.ll
+++ b/test/CodeGen/SystemZ/branch-03.ll
@@ -3,7 +3,7 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 define void @f1(i32 *%src, i32 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cl %r3, 0(%r2)
@@ -18,7 +18,7 @@ exit:
 }
 
 define void @f2(i32 *%src, i32 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cl %r3, 0(%r2)
@@ -33,7 +33,7 @@ exit:
 }
 
 define void @f3(i32 *%src, i32 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cl %r3, 0(%r2)
@@ -48,7 +48,7 @@ exit:
 }
 
 define void @f4(i32 *%src, i32 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cl %r3, 0(%r2)
diff --git a/test/CodeGen/SystemZ/branch-04.ll b/test/CodeGen/SystemZ/branch-04.ll
index d6826fb..fafb234 100644
--- a/test/CodeGen/SystemZ/branch-04.ll
+++ b/test/CodeGen/SystemZ/branch-04.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define void @f1(float *%src, float %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -19,7 +19,7 @@ exit:
 }
 
 define void @f2(float *%src, float %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -34,7 +34,7 @@ exit:
 }
 
 define void @f3(float *%src, float %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -49,7 +49,7 @@ exit:
 }
 
 define void @f4(float *%src, float %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -64,7 +64,7 @@ exit:
 }
 
 define void @f5(float *%src, float %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -79,7 +79,7 @@ exit:
 }
 
 define void @f6(float *%src, float %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -94,7 +94,7 @@ exit:
 }
 
 define void @f7(float *%src, float %target) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -109,7 +109,7 @@ exit:
 }
 
 define void @f8(float *%src, float %target) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -124,7 +124,7 @@ exit:
 }
 
 define void @f9(float *%src, float %target) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -139,7 +139,7 @@ exit:
 }
 
 define void @f10(float *%src, float %target) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -154,7 +154,7 @@ exit:
 }
 
 define void @f11(float *%src, float %target) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -169,7 +169,7 @@ exit:
 }
 
 define void @f12(float *%src, float %target) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -186,7 +186,7 @@ exit:
 ; "jno" == "jump if no overflow", which corresponds to "jump if ordered"
 ; rather than "jump if not ordered" after a floating-point comparison.
 define void @f13(float *%src, float %target) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
@@ -203,7 +203,7 @@ exit:
 ; "jo" == "jump if overflow", which corresponds to "jump if not ordered"
 ; rather than "jump if ordered" after a floating-point comparison.
 define void @f14(float *%src, float %target) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: .cfi_startproc
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: ceb %f0, 0(%r2)
diff --git a/test/CodeGen/SystemZ/branch-05.ll b/test/CodeGen/SystemZ/branch-05.ll
index 268692a..d657c9b 100644
--- a/test/CodeGen/SystemZ/branch-05.ll
+++ b/test/CodeGen/SystemZ/branch-05.ll
@@ -3,7 +3,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 define i32 @f1(i32 %x, i32 %y, i32 %op) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ahi %r4, -1
 ; CHECK: clfi %r4, 5
 ; CHECK-NEXT: jh
diff --git a/test/CodeGen/SystemZ/branch-06.ll b/test/CodeGen/SystemZ/branch-06.ll
index 3854045..13e5a84 100644
--- a/test/CodeGen/SystemZ/branch-06.ll
+++ b/test/CodeGen/SystemZ/branch-06.ll
@@ -2,10 +2,10 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-declare i32 @foo();
+declare i32 @foo()
 
 define void @f1(i32 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crje %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -19,7 +19,7 @@ exit:
 }
 
 define void @f2(i32 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crjlh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -33,7 +33,7 @@ exit:
 }
 
 define void @f3(i32 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crjle %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -47,7 +47,7 @@ exit:
 }
 
 define void @f4(i32 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crjl %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -61,7 +61,7 @@ exit:
 }
 
 define void @f5(i32 %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crjh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -75,7 +75,7 @@ exit:
 }
 
 define void @f6(i32 %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: crjhe %r2, {{%r[0-9]+}}, .L[[LABEL]]
diff --git a/test/CodeGen/SystemZ/branch-07.ll b/test/CodeGen/SystemZ/branch-07.ll
index 1cab6ff..b715a05 100644
--- a/test/CodeGen/SystemZ/branch-07.ll
+++ b/test/CodeGen/SystemZ/branch-07.ll
@@ -2,10 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
-declare i64 @foo();
+declare i64 @foo()
 
+; Test EQ.
 define void @f1(i64 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrje %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -18,8 +19,9 @@ exit:
   ret void
 }
 
+; Test NE.
 define void @f2(i64 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrjlh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -32,8 +34,9 @@ exit:
   ret void
 }
 
+; Test SLE.
 define void @f3(i64 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrjle %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -46,8 +49,9 @@ exit:
   ret void
 }
 
+; Test SLT.
 define void @f4(i64 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrjl %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -60,8 +64,9 @@ exit:
   ret void
 }
 
+; Test SGT.
 define void @f5(i64 %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrjh %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -74,8 +79,9 @@ exit:
   ret void
 }
 
+; Test SGE.
 define void @f6(i64 %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: .cfi_def_cfa_offset
 ; CHECK: .L[[LABEL:.*]]:
 ; CHECK: cgrjhe %r2, {{%r[0-9]+}}, .L[[LABEL]]
@@ -87,3 +93,67 @@ loop:
 exit:
   ret void
 }
+
+; Test a vector of 0/-1 results for i32 EQ.
+define i64 @f7(i64 %a, i64 %b) {
+; CHECK-LABEL: f7:
+; CHECK: lhi [[REG:%r[0-5]]], -1
+; CHECK: crje {{%r[0-5]}}
+; CHECK: lhi [[REG]], 0
+; CHECK-NOT: sra
+; CHECK: br %r14
+  %avec = bitcast i64 %a to <2 x i32>
+  %bvec = bitcast i64 %b to <2 x i32>
+  %cmp = icmp eq <2 x i32> %avec, %bvec
+  %ext = sext <2 x i1> %cmp to <2 x i32>
+  %ret = bitcast <2 x i32> %ext to i64
+  ret i64 %ret
+}
+
+; Test a vector of 0/-1 results for i32 NE.
+define i64 @f8(i64 %a, i64 %b) {
+; CHECK-LABEL: f8:
+; CHECK: lhi [[REG:%r[0-5]]], -1
+; CHECK: crjlh {{%r[0-5]}}
+; CHECK: lhi [[REG]], 0
+; CHECK-NOT: sra
+; CHECK: br %r14
+  %avec = bitcast i64 %a to <2 x i32>
+  %bvec = bitcast i64 %b to <2 x i32>
+  %cmp = icmp ne <2 x i32> %avec, %bvec
+  %ext = sext <2 x i1> %cmp to <2 x i32>
+  %ret = bitcast <2 x i32> %ext to i64
+  ret i64 %ret
+}
+
+; Test a vector of 0/-1 results for i64 EQ.
+define void @f9(i64 %a, i64 %b, <2 x i64> *%dest) {
+; CHECK-LABEL: f9:
+; CHECK: lghi [[REG:%r[0-5]]], -1
+; CHECK: crje {{%r[0-5]}}
+; CHECK: lghi [[REG]], 0
+; CHECK-NOT: sra
+; CHECK: br %r14
+  %avec = bitcast i64 %a to <2 x i32>
+  %bvec = bitcast i64 %b to <2 x i32>
+  %cmp = icmp eq <2 x i32> %avec, %bvec
+  %ext = sext <2 x i1> %cmp to <2 x i64>
+  store <2 x i64> %ext, <2 x i64> *%dest
+  ret void
+}
+
+; Test a vector of 0/-1 results for i64 NE.
+define void @f10(i64 %a, i64 %b, <2 x i64> *%dest) {
+; CHECK-LABEL: f10:
+; CHECK: lghi [[REG:%r[0-5]]], -1
+; CHECK: crjlh {{%r[0-5]}}
+; CHECK: lghi [[REG]], 0
+; CHECK-NOT: sra
+; CHECK: br %r14
+  %avec = bitcast i64 %a to <2 x i32>
+  %bvec = bitcast i64 %b to <2 x i32>
+  %cmp = icmp ne <2 x i32> %avec, %bvec
+  %ext = sext <2 x i1> %cmp to <2 x i64>
+  store <2 x i64> %ext, <2 x i64> *%dest
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/branch-08.ll b/test/CodeGen/SystemZ/branch-08.ll
new file mode 100644
index 0000000..c4dc467
--- /dev/null
+++ b/test/CodeGen/SystemZ/branch-08.ll
@@ -0,0 +1,45 @@
+; Test SystemZInstrInfo::AnalyzeBranch and SystemZInstrInfo::InsertBranch.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare void @foo() noreturn
+
+; Check a case where a separate branch is needed and where the original
+; order should be reversed.
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK-LABEL: f1:
+; CHECK: clr %r2, %r3
+; CHECK: jl .L[[LABEL:.*]]
+; CHECK: br %r14
+; CHECK: .L[[LABEL]]:
+; CHECK: brasl %r14, foo@PLT
+entry:
+  %cmp = icmp ult i32 %a, %b
+  br i1 %cmp, label %callit, label %return
+
+callit:
+  call void @foo()
+  unreachable
+
+return:
+  ret i32 1
+}
+
+; Same again with a fused compare and branch.
+define i32 @f2(i32 %a) {
+; CHECK-LABEL: f2:
+; CHECK: cije %r2, 0, .L[[LABEL:.*]]
+; CHECK: br %r14
+; CHECK: .L[[LABEL]]:
+; CHECK: brasl %r14, foo@PLT
+entry:
+  %cmp = icmp eq i32 %a, 0
+  br i1 %cmp, label %callit, label %return
+
+callit:
+  call void @foo()
+  unreachable
+
+return:
+  ret i32 1
+}
diff --git a/test/CodeGen/SystemZ/bswap-01.ll b/test/CodeGen/SystemZ/bswap-01.ll
index 952903d..7e6c83a 100644
--- a/test/CodeGen/SystemZ/bswap-01.ll
+++ b/test/CodeGen/SystemZ/bswap-01.ll
@@ -7,18 +7,18 @@ declare i64 @llvm.bswap.i64(i64 %a)
 
 ; Check 32-bit register-to-register byteswaps.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lrvr [[REGISTER:%r[0-5]]], %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %swapped
 }
 
 ; Check 64-bit register-to-register byteswaps.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lrvgr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %swapped
 }
diff --git a/test/CodeGen/SystemZ/bswap-02.ll b/test/CodeGen/SystemZ/bswap-02.ll
index 8b99077..db69ea5 100644
--- a/test/CodeGen/SystemZ/bswap-02.ll
+++ b/test/CodeGen/SystemZ/bswap-02.ll
@@ -6,7 +6,7 @@ declare i32 @llvm.bswap.i32(i32 %a)
 
 ; Check LRV with no displacement.
 define i32 @f1(i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lrv %r2, 0(%r2)
 ; CHECK: br %r14
   %a = load i32 *%src
@@ -16,7 +16,7 @@ define i32 @f1(i32 *%src) {
 
 ; Check the high end of the aligned LRV range.
 define i32 @f2(i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lrv %r2, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -28,7 +28,7 @@ define i32 @f2(i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f3(i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lrv %r2, 0(%r2)
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define i32 @f3(i32 *%src) {
 
 ; Check the high end of the negative aligned LRV range.
 define i32 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lrv %r2, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -51,7 +51,7 @@ define i32 @f4(i32 *%src) {
 
 ; Check the low end of the LRV range.
 define i32 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lrv %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -63,7 +63,7 @@ define i32 @f5(i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524292
 ; CHECK: lrv %r2, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define i32 @f6(i32 *%src) {
 
 ; Check that LRV allows an index.
 define i32 @f7(i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lrv %r2, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define i32 @f7(i64 %src, i64 %index) {
 ; Check that volatile accesses do not use LRV, which might access the
 ; storage multple times.
 define i32 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: l [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: lrvr %r2, [[REG]]
 ; CHECK: br %r14
@@ -97,3 +97,80 @@ define i32 @f8(i32 *%src) {
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %swapped
 }
+
+; Test a case where we spill the source of at least one LRVR.  We want
+; to use LRV if possible.
+define void @f9(i32 *%ptr) {
+; CHECK-LABEL: f9:
+; CHECK: lrv {{%r[0-9]+}}, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %val0 = load volatile i32 *%ptr
+  %val1 = load volatile i32 *%ptr
+  %val2 = load volatile i32 *%ptr
+  %val3 = load volatile i32 *%ptr
+  %val4 = load volatile i32 *%ptr
+  %val5 = load volatile i32 *%ptr
+  %val6 = load volatile i32 *%ptr
+  %val7 = load volatile i32 *%ptr
+  %val8 = load volatile i32 *%ptr
+  %val9 = load volatile i32 *%ptr
+  %val10 = load volatile i32 *%ptr
+  %val11 = load volatile i32 *%ptr
+  %val12 = load volatile i32 *%ptr
+  %val13 = load volatile i32 *%ptr
+  %val14 = load volatile i32 *%ptr
+  %val15 = load volatile i32 *%ptr
+
+  %swapped0 = call i32 @llvm.bswap.i32(i32 %val0)
+  %swapped1 = call i32 @llvm.bswap.i32(i32 %val1)
+  %swapped2 = call i32 @llvm.bswap.i32(i32 %val2)
+  %swapped3 = call i32 @llvm.bswap.i32(i32 %val3)
+  %swapped4 = call i32 @llvm.bswap.i32(i32 %val4)
+  %swapped5 = call i32 @llvm.bswap.i32(i32 %val5)
+  %swapped6 = call i32 @llvm.bswap.i32(i32 %val6)
+  %swapped7 = call i32 @llvm.bswap.i32(i32 %val7)
+  %swapped8 = call i32 @llvm.bswap.i32(i32 %val8)
+  %swapped9 = call i32 @llvm.bswap.i32(i32 %val9)
+  %swapped10 = call i32 @llvm.bswap.i32(i32 %val10)
+  %swapped11 = call i32 @llvm.bswap.i32(i32 %val11)
+  %swapped12 = call i32 @llvm.bswap.i32(i32 %val12)
+  %swapped13 = call i32 @llvm.bswap.i32(i32 %val13)
+  %swapped14 = call i32 @llvm.bswap.i32(i32 %val14)
+  %swapped15 = call i32 @llvm.bswap.i32(i32 %val15)
+
+  store volatile i32 %val0, i32 *%ptr
+  store volatile i32 %val1, i32 *%ptr
+  store volatile i32 %val2, i32 *%ptr
+  store volatile i32 %val3, i32 *%ptr
+  store volatile i32 %val4, i32 *%ptr
+  store volatile i32 %val5, i32 *%ptr
+  store volatile i32 %val6, i32 *%ptr
+  store volatile i32 %val7, i32 *%ptr
+  store volatile i32 %val8, i32 *%ptr
+  store volatile i32 %val9, i32 *%ptr
+  store volatile i32 %val10, i32 *%ptr
+  store volatile i32 %val11, i32 *%ptr
+  store volatile i32 %val12, i32 *%ptr
+  store volatile i32 %val13, i32 *%ptr
+  store volatile i32 %val14, i32 *%ptr
+  store volatile i32 %val15, i32 *%ptr
+
+  store volatile i32 %swapped0, i32 *%ptr
+  store volatile i32 %swapped1, i32 *%ptr
+  store volatile i32 %swapped2, i32 *%ptr
+  store volatile i32 %swapped3, i32 *%ptr
+  store volatile i32 %swapped4, i32 *%ptr
+  store volatile i32 %swapped5, i32 *%ptr
+  store volatile i32 %swapped6, i32 *%ptr
+  store volatile i32 %swapped7, i32 *%ptr
+  store volatile i32 %swapped8, i32 *%ptr
+  store volatile i32 %swapped9, i32 *%ptr
+  store volatile i32 %swapped10, i32 *%ptr
+  store volatile i32 %swapped11, i32 *%ptr
+  store volatile i32 %swapped12, i32 *%ptr
+  store volatile i32 %swapped13, i32 *%ptr
+  store volatile i32 %swapped14, i32 *%ptr
+  store volatile i32 %swapped15, i32 *%ptr
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/bswap-03.ll b/test/CodeGen/SystemZ/bswap-03.ll
index df6624e..d9e5ad1 100644
--- a/test/CodeGen/SystemZ/bswap-03.ll
+++ b/test/CodeGen/SystemZ/bswap-03.ll
@@ -6,7 +6,7 @@ declare i64 @llvm.bswap.i64(i64 %a)
 
 ; Check LRVG with no displacement.
 define i64 @f1(i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lrvg %r2, 0(%r2)
 ; CHECK: br %r14
   %a = load i64 *%src
@@ -16,7 +16,7 @@ define i64 @f1(i64 *%src) {
 
 ; Check the high end of the aligned LRVG range.
 define i64 @f2(i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lrvg %r2, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -28,7 +28,7 @@ define i64 @f2(i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f3(i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lrvg %r2, 0(%r2)
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define i64 @f3(i64 *%src) {
 
 ; Check the high end of the negative aligned LRVG range.
 define i64 @f4(i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lrvg %r2, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -51,7 +51,7 @@ define i64 @f4(i64 *%src) {
 
 ; Check the low end of the LRVG range.
 define i64 @f5(i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lrvg %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -63,7 +63,7 @@ define i64 @f5(i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524296
 ; CHECK: lrvg %r2, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define i64 @f6(i64 *%src) {
 
 ; Check that LRVG allows an index.
 define i64 @f7(i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lrvg %r2, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define i64 @f7(i64 %src, i64 %index) {
 ; Check that volatile accesses do not use LRVG, which might access the
 ; storage multple times.
 define i64 @f8(i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lg [[REG:%r[0-5]]], 0(%r2)
 ; CHECK: lrvgr %r2, [[REG]]
 ; CHECK: br %r14
@@ -97,3 +97,80 @@ define i64 @f8(i64 *%src) {
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
   ret i64 %swapped
 }
+
+; Test a case where we spill the source of at least one LRVGR.  We want
+; to use LRVG if possible.
+define void @f9(i64 *%ptr) {
+; CHECK-LABEL: f9:
+; CHECK: lrvg {{%r[0-9]+}}, 160(%r15)
+; CHECK: br %r14
+  %val0 = load volatile i64 *%ptr
+  %val1 = load volatile i64 *%ptr
+  %val2 = load volatile i64 *%ptr
+  %val3 = load volatile i64 *%ptr
+  %val4 = load volatile i64 *%ptr
+  %val5 = load volatile i64 *%ptr
+  %val6 = load volatile i64 *%ptr
+  %val7 = load volatile i64 *%ptr
+  %val8 = load volatile i64 *%ptr
+  %val9 = load volatile i64 *%ptr
+  %val10 = load volatile i64 *%ptr
+  %val11 = load volatile i64 *%ptr
+  %val12 = load volatile i64 *%ptr
+  %val13 = load volatile i64 *%ptr
+  %val14 = load volatile i64 *%ptr
+  %val15 = load volatile i64 *%ptr
+
+  %swapped0 = call i64 @llvm.bswap.i64(i64 %val0)
+  %swapped1 = call i64 @llvm.bswap.i64(i64 %val1)
+  %swapped2 = call i64 @llvm.bswap.i64(i64 %val2)
+  %swapped3 = call i64 @llvm.bswap.i64(i64 %val3)
+  %swapped4 = call i64 @llvm.bswap.i64(i64 %val4)
+  %swapped5 = call i64 @llvm.bswap.i64(i64 %val5)
+  %swapped6 = call i64 @llvm.bswap.i64(i64 %val6)
+  %swapped7 = call i64 @llvm.bswap.i64(i64 %val7)
+  %swapped8 = call i64 @llvm.bswap.i64(i64 %val8)
+  %swapped9 = call i64 @llvm.bswap.i64(i64 %val9)
+  %swapped10 = call i64 @llvm.bswap.i64(i64 %val10)
+  %swapped11 = call i64 @llvm.bswap.i64(i64 %val11)
+  %swapped12 = call i64 @llvm.bswap.i64(i64 %val12)
+  %swapped13 = call i64 @llvm.bswap.i64(i64 %val13)
+  %swapped14 = call i64 @llvm.bswap.i64(i64 %val14)
+  %swapped15 = call i64 @llvm.bswap.i64(i64 %val15)
+
+  store volatile i64 %val0, i64 *%ptr
+  store volatile i64 %val1, i64 *%ptr
+  store volatile i64 %val2, i64 *%ptr
+  store volatile i64 %val3, i64 *%ptr
+  store volatile i64 %val4, i64 *%ptr
+  store volatile i64 %val5, i64 *%ptr
+  store volatile i64 %val6, i64 *%ptr
+  store volatile i64 %val7, i64 *%ptr
+  store volatile i64 %val8, i64 *%ptr
+  store volatile i64 %val9, i64 *%ptr
+  store volatile i64 %val10, i64 *%ptr
+  store volatile i64 %val11, i64 *%ptr
+  store volatile i64 %val12, i64 *%ptr
+  store volatile i64 %val13, i64 *%ptr
+  store volatile i64 %val14, i64 *%ptr
+  store volatile i64 %val15, i64 *%ptr
+
+  store volatile i64 %swapped0, i64 *%ptr
+  store volatile i64 %swapped1, i64 *%ptr
+  store volatile i64 %swapped2, i64 *%ptr
+  store volatile i64 %swapped3, i64 *%ptr
+  store volatile i64 %swapped4, i64 *%ptr
+  store volatile i64 %swapped5, i64 *%ptr
+  store volatile i64 %swapped6, i64 *%ptr
+  store volatile i64 %swapped7, i64 *%ptr
+  store volatile i64 %swapped8, i64 *%ptr
+  store volatile i64 %swapped9, i64 *%ptr
+  store volatile i64 %swapped10, i64 *%ptr
+  store volatile i64 %swapped11, i64 *%ptr
+  store volatile i64 %swapped12, i64 *%ptr
+  store volatile i64 %swapped13, i64 *%ptr
+  store volatile i64 %swapped14, i64 *%ptr
+  store volatile i64 %swapped15, i64 *%ptr
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/bswap-04.ll b/test/CodeGen/SystemZ/bswap-04.ll
index 63b2020..29d5a7b 100644
--- a/test/CodeGen/SystemZ/bswap-04.ll
+++ b/test/CodeGen/SystemZ/bswap-04.ll
@@ -6,7 +6,7 @@ declare i32 @llvm.bswap.i32(i32 %a)
 
 ; Check STRV with no displacement.
 define void @f1(i32 *%dst, i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: strv %r3, 0(%r2)
 ; CHECK: br %r14
   %swapped = call i32 @llvm.bswap.i32(i32 %a)
@@ -16,7 +16,7 @@ define void @f1(i32 *%dst, i32 %a) {
 
 ; Check the high end of the aligned STRV range.
 define void @f2(i32 *%dst, i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: strv %r3, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 131071
@@ -28,7 +28,7 @@ define void @f2(i32 *%dst, i32 %a) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f3(i32 *%dst, i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: strv %r3, 0(%r2)
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define void @f3(i32 *%dst, i32 %a) {
 
 ; Check the high end of the negative aligned STRV range.
 define void @f4(i32 *%dst, i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: strv %r3, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 -1
@@ -51,7 +51,7 @@ define void @f4(i32 *%dst, i32 %a) {
 
 ; Check the low end of the STRV range.
 define void @f5(i32 *%dst, i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: strv %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 -131072
@@ -63,7 +63,7 @@ define void @f5(i32 *%dst, i32 %a) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i32 *%dst, i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524292
 ; CHECK: strv %r3, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f6(i32 *%dst, i32 %a) {
 
 ; Check that STRV allows an index.
 define void @f7(i64 %src, i64 %index, i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: strv %r4, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define void @f7(i64 %src, i64 %index, i32 %a) {
 ; Check that volatile stores do not use STRV, which might access the
 ; storage multple times.
 define void @f8(i32 *%dst, i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lrvr [[REG:%r[0-5]]], %r3
 ; CHECK: st [[REG]], 0(%r2)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/bswap-05.ll b/test/CodeGen/SystemZ/bswap-05.ll
index 6f25d3c..5c8361e 100644
--- a/test/CodeGen/SystemZ/bswap-05.ll
+++ b/test/CodeGen/SystemZ/bswap-05.ll
@@ -6,7 +6,7 @@ declare i64 @llvm.bswap.i64(i64 %a)
 
 ; Check STRVG with no displacement.
 define void @f1(i64 *%dst, i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: strvg %r3, 0(%r2)
 ; CHECK: br %r14
   %swapped = call i64 @llvm.bswap.i64(i64 %a)
@@ -16,7 +16,7 @@ define void @f1(i64 *%dst, i64 %a) {
 
 ; Check the high end of the aligned STRVG range.
 define void @f2(i64 *%dst, i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: strvg %r3, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 65535
@@ -28,7 +28,7 @@ define void @f2(i64 *%dst, i64 %a) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f3(i64 *%dst, i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: strvg %r3, 0(%r2)
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define void @f3(i64 *%dst, i64 %a) {
 
 ; Check the high end of the negative aligned STRVG range.
 define void @f4(i64 *%dst, i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: strvg %r3, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 -1
@@ -51,7 +51,7 @@ define void @f4(i64 *%dst, i64 %a) {
 
 ; Check the low end of the STRVG range.
 define void @f5(i64 *%dst, i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: strvg %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 -65536
@@ -63,7 +63,7 @@ define void @f5(i64 *%dst, i64 %a) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 *%dst, i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524296
 ; CHECK: strvg %r3, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f6(i64 *%dst, i64 %a) {
 
 ; Check that STRVG allows an index.
 define void @f7(i64 %src, i64 %index, i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: strvg %r4, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -89,7 +89,7 @@ define void @f7(i64 %src, i64 %index, i64 %a) {
 ; Check that volatile stores do not use STRVG, which might access the
 ; storage multple times.
 define void @f8(i64 *%dst, i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lrvgr [[REG:%r[0-5]]], %r3
 ; CHECK: stg [[REG]], 0(%r2)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/call-01.ll b/test/CodeGen/SystemZ/call-01.ll
index 1b9172b..42b6afd 100644
--- a/test/CodeGen/SystemZ/call-01.ll
+++ b/test/CodeGen/SystemZ/call-01.ll
@@ -6,7 +6,7 @@ declare i64 @bar()
 
 ; We must allocate 160 bytes for the callee and save and restore %r14.
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: aghi %r15, -160
 ; CHECK: brasl %r14, bar@PLT
diff --git a/test/CodeGen/SystemZ/call-02.ll b/test/CodeGen/SystemZ/call-02.ll
index 07dd67b..5f14d12 100644
--- a/test/CodeGen/SystemZ/call-02.ll
+++ b/test/CodeGen/SystemZ/call-02.ll
@@ -4,7 +4,7 @@
 
 ; We must allocate 160 bytes for the callee and save and restore %r14.
 define i64 @f1(i64() *%bar) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: aghi %r15, -160
 ; CHECK: basr %r14, %r2
diff --git a/test/CodeGen/SystemZ/cmpxchg-01.ll b/test/CodeGen/SystemZ/cmpxchg-01.ll
index 03fabee..d5ea977 100644
--- a/test/CodeGen/SystemZ/cmpxchg-01.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-01.ll
@@ -11,7 +11,7 @@
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
-; CHECK-MAIN: f1:
+; CHECK-MAIN-LABEL: f1:
 ; CHECK-MAIN: sllg [[SHIFT:%r[1-9]+]], %r3, 3
 ; CHECK-MAIN: nill %r3, 65532
 ; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0(%r3)
@@ -22,12 +22,12 @@ define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
 ; CHECK-MAIN: risbg %r5, %r2, 32, 55, 0
 ; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -8({{%r[1-9]+}})
 ; CHECK-MAIN: cs [[OLD]], [[NEW]], 0(%r3)
-; CHECK-MAIN: jlh [[LOOP]]
+; CHECK-MAIN: jl [[LOOP]]
 ; CHECK-MAIN: [[EXIT]]:
 ; CHECK-MAIN-NOT: %r2
 ; CHECK-MAIN: br %r14
 ;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
 ; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r3, 3
 ; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT: rll
@@ -39,13 +39,13 @@ define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
 ; Check compare and swap with constants.  We should force the constants into
 ; registers and use the sequence above.
 define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi [[CMP:%r[0-9]+]], 42
 ; CHECK: risbg [[CMP]], {{%r[0-9]+}}, 32, 55, 0
 ; CHECK: risbg
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
 ; CHECK-SHIFT: lhi [[SWAP:%r[0-9]+]], 88
 ; CHECK-SHIFT: risbg
 ; CHECK-SHIFT: risbg [[SWAP]], {{%r[0-9]+}}, 32, 55, 0
diff --git a/test/CodeGen/SystemZ/cmpxchg-02.ll b/test/CodeGen/SystemZ/cmpxchg-02.ll
index b5005bb..08c79d7 100644
--- a/test/CodeGen/SystemZ/cmpxchg-02.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-02.ll
@@ -11,7 +11,7 @@
 ;   being used in the RISBG (in contrast to things like atomic addition,
 ;   which shift %r3 left so that %b is at the high end of the word).
 define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
-; CHECK-MAIN: f1:
+; CHECK-MAIN-LABEL: f1:
 ; CHECK-MAIN: sllg [[SHIFT:%r[1-9]+]], %r3, 3
 ; CHECK-MAIN: nill %r3, 65532
 ; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0(%r3)
@@ -22,12 +22,12 @@ define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
 ; CHECK-MAIN: risbg %r5, %r2, 32, 47, 0
 ; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -16({{%r[1-9]+}})
 ; CHECK-MAIN: cs [[OLD]], [[NEW]], 0(%r3)
-; CHECK-MAIN: jlh [[LOOP]]
+; CHECK-MAIN: jl [[LOOP]]
 ; CHECK-MAIN: [[EXIT]]:
 ; CHECK-MAIN-NOT: %r2
 ; CHECK-MAIN: br %r14
 ;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
 ; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r3, 3
 ; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
 ; CHECK-SHIFT: rll
@@ -39,13 +39,13 @@ define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
 ; Check compare and swap with constants.  We should force the constants into
 ; registers and use the sequence above.
 define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi [[CMP:%r[0-9]+]], 42
 ; CHECK: risbg [[CMP]], {{%r[0-9]+}}, 32, 47, 0
 ; CHECK: risbg
 ; CHECK: br %r14
 ;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
 ; CHECK-SHIFT: lhi [[SWAP:%r[0-9]+]], 88
 ; CHECK-SHIFT: risbg
 ; CHECK-SHIFT: risbg [[SWAP]], {{%r[0-9]+}}, 32, 47, 0
diff --git a/test/CodeGen/SystemZ/cmpxchg-03.ll b/test/CodeGen/SystemZ/cmpxchg-03.ll
index 45e224e..3917979 100644
--- a/test/CodeGen/SystemZ/cmpxchg-03.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-03.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the CS range.
 define i32 @f1(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
   %val = cmpxchg i32 *%src, i32 %cmp, i32 %swap seq_cst
@@ -13,7 +13,7 @@ define i32 @f1(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check the high end of the aligned CS range.
 define i32 @f2(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cs %r2, %r3, 4092(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -23,7 +23,7 @@ define i32 @f2(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check the next word up, which should use CSY instead of CS.
 define i32 @f3(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: csy %r2, %r3, 4096(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -33,7 +33,7 @@ define i32 @f3(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check the high end of the aligned CSY range.
 define i32 @f4(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: csy %r2, %r3, 524284(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -44,7 +44,7 @@ define i32 @f4(i32 %cmp, i32 %swap, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r4, 524288
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define i32 @f5(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check the high end of the negative aligned CSY range.
 define i32 @f6(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: csy %r2, %r3, -4(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i32 @f6(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check the low end of the CSY range.
 define i32 @f7(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: csy %r2, %r3, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -76,7 +76,7 @@ define i32 @f7(i32 %cmp, i32 %swap, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r4, -524292
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define i32 @f8(i32 %cmp, i32 %swap, i32 *%src) {
 
 ; Check that CS does not allow an index.
 define i32 @f9(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agr %r4, %r5
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -99,7 +99,7 @@ define i32 @f9(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
 
 ; Check that CSY does not allow an index.
 define i32 @f10(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr %r4, %r5
 ; CHECK: csy %r2, %r3, 4096(%r4)
 ; CHECK: br %r14
@@ -112,7 +112,7 @@ define i32 @f10(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
 
 ; Check that a constant %cmp value is loaded into a register first.
 define i32 @f11(i32 %dummy, i32 %swap, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: lhi %r2, 1001
 ; CHECK: cs %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define i32 @f11(i32 %dummy, i32 %swap, i32 *%ptr) {
 
 ; Check that a constant %swap value is loaded into a register first.
 define i32 @f12(i32 %cmp, i32 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: lhi [[SWAP:%r[0-9]+]], 1002
 ; CHECK: cs %r2, [[SWAP]], 0(%r3)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/cmpxchg-04.ll b/test/CodeGen/SystemZ/cmpxchg-04.ll
index f8969ee..f58868f 100644
--- a/test/CodeGen/SystemZ/cmpxchg-04.ll
+++ b/test/CodeGen/SystemZ/cmpxchg-04.ll
@@ -4,7 +4,7 @@
 
 ; Check CSG without a displacement.
 define i64 @f1(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
   %val = cmpxchg i64 *%src, i64 %cmp, i64 %swap seq_cst
@@ -13,7 +13,7 @@ define i64 @f1(i64 %cmp, i64 %swap, i64 *%src) {
 
 ; Check the high end of the aligned CSG range.
 define i64 @f2(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: csg %r2, %r3, 524280(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -24,7 +24,7 @@ define i64 @f2(i64 %cmp, i64 %swap, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f3(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r4, 524288
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define i64 @f3(i64 %cmp, i64 %swap, i64 *%src) {
 
 ; Check the high end of the negative aligned CSG range.
 define i64 @f4(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: csg %r2, %r3, -8(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -45,7 +45,7 @@ define i64 @f4(i64 %cmp, i64 %swap, i64 *%src) {
 
 ; Check the low end of the CSG range.
 define i64 @f5(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: csg %r2, %r3, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -56,7 +56,7 @@ define i64 @f5(i64 %cmp, i64 %swap, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r4, -524296
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i64 @f6(i64 %cmp, i64 %swap, i64 *%src) {
 
 ; Check that CSG does not allow an index.
 define i64 @f7(i64 %cmp, i64 %swap, i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agr %r4, %r5
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -79,7 +79,7 @@ define i64 @f7(i64 %cmp, i64 %swap, i64 %src, i64 %index) {
 
 ; Check that a constant %cmp value is loaded into a register first.
 define i64 @f8(i64 %dummy, i64 %swap, i64 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lghi %r2, 1001
 ; CHECK: csg %r2, %r3, 0(%r4)
 ; CHECK: br %r14
@@ -89,7 +89,7 @@ define i64 @f8(i64 %dummy, i64 %swap, i64 *%ptr) {
 
 ; Check that a constant %swap value is loaded into a register first.
 define i64 @f9(i64 %cmp, i64 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lghi [[SWAP:%r[0-9]+]], 1002
 ; CHECK: csg %r2, [[SWAP]], 0(%r3)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/cond-load-01.ll b/test/CodeGen/SystemZ/cond-load-01.ll
new file mode 100644
index 0000000..1030226
--- /dev/null
+++ b/test/CodeGen/SystemZ/cond-load-01.ll
@@ -0,0 +1,130 @@
+; Test LOC.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i32 @foo(i32 *)
+
+; Test the simple case.
+define i32 @f1(i32 %easy, i32 *%ptr, i32 %limit) {
+; CHECK-LABEL: f1:
+; CHECK: clfi %r4, 42
+; CHECK: loche %r2, 0(%r3)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %other = load i32 *%ptr
+  %res = select i1 %cond, i32 %easy, i32 %other
+  ret i32 %res
+}
+
+; ...and again with the operands swapped.
+define i32 @f2(i32 %easy, i32 *%ptr, i32 %limit) {
+; CHECK-LABEL: f2:
+; CHECK: clfi %r4, 42
+; CHECK: locl %r2, 0(%r3)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %other = load i32 *%ptr
+  %res = select i1 %cond, i32 %other, i32 %easy
+  ret i32 %res
+}
+
+; Check the high end of the aligned LOC range.
+define i32 @f3(i32 %easy, i32 *%base, i32 %limit) {
+; CHECK-LABEL: f3:
+; CHECK: clfi %r4, 42
+; CHECK: loche %r2, 524284(%r3)
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 131071
+  %cond = icmp ult i32 %limit, 42
+  %other = load i32 *%ptr
+  %res = select i1 %cond, i32 %easy, i32 %other
+  ret i32 %res
+}
+
+; Check the next word up.  Other sequences besides this one would be OK.
+define i32 @f4(i32 %easy, i32 *%base, i32 %limit) {
+; CHECK-LABEL: f4:
+; CHECK: agfi %r3, 524288
+; CHECK: clfi %r4, 42
+; CHECK: loche %r2, 0(%r3)
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 131072
+  %cond = icmp ult i32 %limit, 42
+  %other = load i32 *%ptr
+  %res = select i1 %cond, i32 %easy, i32 %other
+  ret i32 %res
+}
+
+; Check the low end of the LOC range.
+define i32 @f5(i32 %easy, i32 *%base, i32 %limit) {
+; CHECK-LABEL: f5:
+; CHECK: clfi %r4, 42
+; CHECK: loche %r2, -524288(%r3)
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 -131072
+  %cond = icmp ult i32 %limit, 42
+  %other = load i32 *%ptr
+  %res = select i1 %cond, i32 %easy, i32 %other
+  ret i32 %res
+}
+
+; Check the next word down, with the same comments as f4.
+define i32 @f6(i32 %easy, i32 *%base, i32 %limit) {
+; CHECK-LABEL: f6:
+; CHECK: agfi %r3, -524292
+; CHECK: clfi %r4, 42
+; CHECK: loche %r2, 0(%r3)
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 -131073
+  %cond = icmp ult i32 %limit, 42
+  %other = load i32 *%ptr
+  %res = select i1 %cond, i32 %easy, i32 %other
+  ret i32 %res
+}
+
+; Try a frame index base.
+define i32 @f7(i32 %alt, i32 %limit) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: loche %r2, {{[0-9]+}}(%r15)
+; CHECK: br %r14
+  %ptr = alloca i32
+  %easy = call i32 @foo(i32 *%ptr)
+  %cond = icmp ult i32 %limit, 42
+  %other = load i32 *%ptr
+  %res = select i1 %cond, i32 %easy, i32 %other
+  ret i32 %res
+}
+
+; Try a case when an index is involved.
+define i32 @f8(i32 %easy, i32 %limit, i64 %base, i64 %index) {
+; CHECK-LABEL: f8:
+; CHECK: clfi %r3, 42
+; CHECK: loche %r2, 0({{%r[1-5]}})
+; CHECK: br %r14
+  %add = add i64 %base, %index
+  %ptr = inttoptr i64 %add to i32 *
+  %cond = icmp ult i32 %limit, 42
+  %other = load i32 *%ptr
+  %res = select i1 %cond, i32 %easy, i32 %other
+  ret i32 %res
+}
+
+; Test that conditionally-executed loads do not use LOC, since it is allowed
+; to trap even when the condition is false.
+define i32 @f9(i32 %easy, i32 %limit, i32 *%ptr) {
+; CHECK-LABEL: f9:
+; CHECK-NOT: loc
+; CHECK: br %r14
+entry:
+  %cmp = icmp ule i32 %easy, %limit
+  br i1 %cmp, label %load, label %exit
+
+load:
+  %other = load i32 *%ptr
+  br label %exit
+
+exit:
+  %res = phi i32 [ %easy, %entry ], [ %other, %load ]
+  ret i32 %res
+}
diff --git a/test/CodeGen/SystemZ/cond-load-02.ll b/test/CodeGen/SystemZ/cond-load-02.ll
new file mode 100644
index 0000000..e97f472
--- /dev/null
+++ b/test/CodeGen/SystemZ/cond-load-02.ll
@@ -0,0 +1,130 @@
+; Test LOCG.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i64 @foo(i64 *)
+
+; Test the simple case.
+define i64 @f1(i64 %easy, i64 *%ptr, i64 %limit) {
+; CHECK-LABEL: f1:
+; CHECK: clgfi %r4, 42
+; CHECK: locghe %r2, 0(%r3)
+; CHECK: br %r14
+  %cond = icmp ult i64 %limit, 42
+  %other = load i64 *%ptr
+  %res = select i1 %cond, i64 %easy, i64 %other
+  ret i64 %res
+}
+
+; ...and again with the operands swapped.
+define i64 @f2(i64 %easy, i64 *%ptr, i64 %limit) {
+; CHECK-LABEL: f2:
+; CHECK: clgfi %r4, 42
+; CHECK: locgl %r2, 0(%r3)
+; CHECK: br %r14
+  %cond = icmp ult i64 %limit, 42
+  %other = load i64 *%ptr
+  %res = select i1 %cond, i64 %other, i64 %easy
+  ret i64 %res
+}
+
+; Check the high end of the aligned LOCG range.
+define i64 @f3(i64 %easy, i64 *%base, i64 %limit) {
+; CHECK-LABEL: f3:
+; CHECK: clgfi %r4, 42
+; CHECK: locghe %r2, 524280(%r3)
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 65535
+  %cond = icmp ult i64 %limit, 42
+  %other = load i64 *%ptr
+  %res = select i1 %cond, i64 %easy, i64 %other
+  ret i64 %res
+}
+
+; Check the next doubleword up.  Other sequences besides this one would be OK.
+define i64 @f4(i64 %easy, i64 *%base, i64 %limit) {
+; CHECK-LABEL: f4:
+; CHECK: agfi %r3, 524288
+; CHECK: clgfi %r4, 42
+; CHECK: locghe %r2, 0(%r3)
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 65536
+  %cond = icmp ult i64 %limit, 42
+  %other = load i64 *%ptr
+  %res = select i1 %cond, i64 %easy, i64 %other
+  ret i64 %res
+}
+
+; Check the low end of the LOCG range.
+define i64 @f5(i64 %easy, i64 *%base, i64 %limit) {
+; CHECK-LABEL: f5:
+; CHECK: clgfi %r4, 42
+; CHECK: locghe %r2, -524288(%r3)
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 -65536
+  %cond = icmp ult i64 %limit, 42
+  %other = load i64 *%ptr
+  %res = select i1 %cond, i64 %easy, i64 %other
+  ret i64 %res
+}
+
+; Check the next doubleword down, with the same comments as f4.
+define i64 @f6(i64 %easy, i64 *%base, i64 %limit) {
+; CHECK-LABEL: f6:
+; CHECK: agfi %r3, -524296
+; CHECK: clgfi %r4, 42
+; CHECK: locghe %r2, 0(%r3)
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 -65537
+  %cond = icmp ult i64 %limit, 42
+  %other = load i64 *%ptr
+  %res = select i1 %cond, i64 %easy, i64 %other
+  ret i64 %res
+}
+
+; Try a frame index base.
+define i64 @f7(i64 %alt, i64 %limit) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: locghe %r2, {{[0-9]+}}(%r15)
+; CHECK: br %r14
+  %ptr = alloca i64
+  %easy = call i64 @foo(i64 *%ptr)
+  %cond = icmp ult i64 %limit, 42
+  %other = load i64 *%ptr
+  %res = select i1 %cond, i64 %easy, i64 %other
+  ret i64 %res
+}
+
+; Try a case when an index is involved.
+define i64 @f8(i64 %easy, i64 %limit, i64 %base, i64 %index) {
+; CHECK-LABEL: f8:
+; CHECK: clgfi %r3, 42
+; CHECK: locghe %r2, 0({{%r[1-5]}})
+; CHECK: br %r14
+  %add = add i64 %base, %index
+  %ptr = inttoptr i64 %add to i64 *
+  %cond = icmp ult i64 %limit, 42
+  %other = load i64 *%ptr
+  %res = select i1 %cond, i64 %easy, i64 %other
+  ret i64 %res
+}
+
+; Test that conditionally-executed loads do not use LOCG, since it is allowed
+; to trap even when the condition is false.
+define i64 @f9(i64 %easy, i64 %limit, i64 *%ptr) {
+; CHECK-LABEL: f9:
+; CHECK-NOT: locg
+; CHECK: br %r14
+entry:
+  %cmp = icmp ule i64 %easy, %limit
+  br i1 %cmp, label %load, label %exit
+
+load:
+  %other = load i64 *%ptr
+  br label %exit
+
+exit:
+  %res = phi i64 [ %easy, %entry ], [ %other, %load ]
+  ret i64 %res
+}
diff --git a/test/CodeGen/SystemZ/cond-move-01.ll b/test/CodeGen/SystemZ/cond-move-01.ll
new file mode 100644
index 0000000..088dee0
--- /dev/null
+++ b/test/CodeGen/SystemZ/cond-move-01.ll
@@ -0,0 +1,48 @@
+; Test LOCR and LOCGR.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Test LOCR.
+define i32 @f1(i32 %a, i32 %b, i32 %limit) {
+; CHECK-LABEL: f1:
+; CHECK: clfi %r4, 42
+; CHECK: locrhe %r2, %r3
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %res = select i1 %cond, i32 %a, i32 %b
+  ret i32 %res
+}
+
+; Test LOCGR.
+define i64 @f2(i64 %a, i64 %b, i64 %limit) {
+; CHECK-LABEL: f2:
+; CHECK: clgfi %r4, 42
+; CHECK: locgrhe %r2, %r3
+; CHECK: br %r14
+  %cond = icmp ult i64 %limit, 42
+  %res = select i1 %cond, i64 %a, i64 %b
+  ret i64 %res
+}
+
+; Test LOCR in a case that could use COMPARE AND BRANCH.  We prefer using
+; LOCR if possible.
+define i32 @f3(i32 %a, i32 %b, i32 %limit) {
+; CHECK-LABEL: f3:
+; CHECK: chi %r4, 42
+; CHECK: locrlh %r2, %r3
+; CHECK: br %r14
+  %cond = icmp eq i32 %limit, 42
+  %res = select i1 %cond, i32 %a, i32 %b
+  ret i32 %res
+}
+
+; ...and again for LOCGR.
+define i64 @f4(i64 %a, i64 %b, i64 %limit) {
+; CHECK-LABEL: f4:
+; CHECK: cghi %r4, 42
+; CHECK: locgrlh %r2, %r3
+; CHECK: br %r14
+  %cond = icmp eq i64 %limit, 42
+  %res = select i1 %cond, i64 %a, i64 %b
+  ret i64 %res
+}
diff --git a/test/CodeGen/SystemZ/cond-store-01.ll b/test/CodeGen/SystemZ/cond-store-01.ll
new file mode 100644
index 0000000..80e6d91
--- /dev/null
+++ b/test/CodeGen/SystemZ/cond-store-01.ll
@@ -0,0 +1,397 @@
+; Test 8-bit conditional stores that are presented as selects.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare void @foo(i8 *)
+
+; Test the simple case, with the loaded value first.
+define void @f1(i8 *%ptr, i8 %alt, i32 %limit) {
+; CHECK-LABEL: f1:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stc %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %res = select i1 %cond, i8 %orig, i8 %alt
+  store i8 %res, i8 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f2(i8 *%ptr, i8 %alt, i32 %limit) {
+; CHECK-LABEL: f2:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stc %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %res = select i1 %cond, i8 %alt, i8 %orig
+  store i8 %res, i8 *%ptr
+  ret void
+}
+
+; Test cases where the value is explicitly sign-extended to 32 bits, with the
+; loaded value first.
+define void @f3(i8 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f3:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stc %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %ext = sext i8 %orig to i32
+  %res = select i1 %cond, i32 %ext, i32 %alt
+  %trunc = trunc i32 %res to i8
+  store i8 %trunc, i8 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f4(i8 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f4:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stc %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %ext = sext i8 %orig to i32
+  %res = select i1 %cond, i32 %alt, i32 %ext
+  %trunc = trunc i32 %res to i8
+  store i8 %trunc, i8 *%ptr
+  ret void
+}
+
+; Test cases where the value is explicitly zero-extended to 32 bits, with the
+; loaded value first.
+define void @f5(i8 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f5:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stc %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %ext = zext i8 %orig to i32
+  %res = select i1 %cond, i32 %ext, i32 %alt
+  %trunc = trunc i32 %res to i8
+  store i8 %trunc, i8 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f6(i8 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f6:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stc %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %ext = zext i8 %orig to i32
+  %res = select i1 %cond, i32 %alt, i32 %ext
+  %trunc = trunc i32 %res to i8
+  store i8 %trunc, i8 *%ptr
+  ret void
+}
+
+; Test cases where the value is explicitly sign-extended to 64 bits, with the
+; loaded value first.
+define void @f7(i8 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f7:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stc %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %ext = sext i8 %orig to i64
+  %res = select i1 %cond, i64 %ext, i64 %alt
+  %trunc = trunc i64 %res to i8
+  store i8 %trunc, i8 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f8(i8 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f8:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stc %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %ext = sext i8 %orig to i64
+  %res = select i1 %cond, i64 %alt, i64 %ext
+  %trunc = trunc i64 %res to i8
+  store i8 %trunc, i8 *%ptr
+  ret void
+}
+
+; Test cases where the value is explicitly zero-extended to 64 bits, with the
+; loaded value first.
+define void @f9(i8 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f9:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stc %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %ext = zext i8 %orig to i64
+  %res = select i1 %cond, i64 %ext, i64 %alt
+  %trunc = trunc i64 %res to i8
+  store i8 %trunc, i8 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f10(i8 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f10:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stc %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %ext = zext i8 %orig to i64
+  %res = select i1 %cond, i64 %alt, i64 %ext
+  %trunc = trunc i64 %res to i8
+  store i8 %trunc, i8 *%ptr
+  ret void
+}
+
+; Check the high end of the STC range.
+define void @f11(i8 *%base, i8 %alt, i32 %limit) {
+; CHECK-LABEL: f11:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stc %r3, 4095(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i8 *%base, i64 4095
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %res = select i1 %cond, i8 %orig, i8 %alt
+  store i8 %res, i8 *%ptr
+  ret void
+}
+
+; Check the next byte up, which should use STCY instead of STC.
+define void @f12(i8 *%base, i8 %alt, i32 %limit) {
+; CHECK-LABEL: f12:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stcy %r3, 4096(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i8 *%base, i64 4096
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %res = select i1 %cond, i8 %orig, i8 %alt
+  store i8 %res, i8 *%ptr
+  ret void
+}
+
+; Check the high end of the STCY range.
+define void @f13(i8 *%base, i8 %alt, i32 %limit) {
+; CHECK-LABEL: f13:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stcy %r3, 524287(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i8 *%base, i64 524287
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %res = select i1 %cond, i8 %orig, i8 %alt
+  store i8 %res, i8 *%ptr
+  ret void
+}
+
+; Check the next byte up, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define void @f14(i8 *%base, i8 %alt, i32 %limit) {
+; CHECK-LABEL: f14:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: agfi %r2, 524288
+; CHECK: stc %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i8 *%base, i64 524288
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %res = select i1 %cond, i8 %orig, i8 %alt
+  store i8 %res, i8 *%ptr
+  ret void
+}
+
+; Check the low end of the STCY range.
+define void @f15(i8 *%base, i8 %alt, i32 %limit) {
+; CHECK-LABEL: f15:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stcy %r3, -524288(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i8 *%base, i64 -524288
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %res = select i1 %cond, i8 %orig, i8 %alt
+  store i8 %res, i8 *%ptr
+  ret void
+}
+
+; Check the next byte down, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define void @f16(i8 *%base, i8 %alt, i32 %limit) {
+; CHECK-LABEL: f16:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: agfi %r2, -524289
+; CHECK: stc %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i8 *%base, i64 -524289
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %res = select i1 %cond, i8 %orig, i8 %alt
+  store i8 %res, i8 *%ptr
+  ret void
+}
+
+; Check that STCY allows an index.
+define void @f17(i64 %base, i64 %index, i8 %alt, i32 %limit) {
+; CHECK-LABEL: f17:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stcy %r4, 4096(%r3,%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %add1 = add i64 %base, %index
+  %add2 = add i64 %add1, 4096
+  %ptr = inttoptr i64 %add2 to i8 *
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %res = select i1 %cond, i8 %orig, i8 %alt
+  store i8 %res, i8 *%ptr
+  ret void
+}
+
+; Check that volatile loads are not matched.
+define void @f18(i8 *%ptr, i8 %alt, i32 %limit) {
+; CHECK-LABEL: f18:
+; CHECK: lb {{%r[0-5]}}, 0(%r2)
+; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
+; CHECK: [[LABEL]]:
+; CHECK: stc {{%r[0-5]}}, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load volatile i8 *%ptr
+  %res = select i1 %cond, i8 %orig, i8 %alt
+  store i8 %res, i8 *%ptr
+  ret void
+}
+
+; ...likewise stores.  In this case we should have a conditional load into %r3.
+define void @f19(i8 *%ptr, i8 %alt, i32 %limit) {
+; CHECK-LABEL: f19:
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: lb %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: stc %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %res = select i1 %cond, i8 %orig, i8 %alt
+  store volatile i8 %res, i8 *%ptr
+  ret void
+}
+
+; Check that atomic loads are not matched.  The transformation is OK for
+; the "unordered" case tested here, but since we don't try to handle atomic
+; operations at all in this context, it seems better to assert that than
+; to restrict the test to a stronger ordering.
+define void @f20(i8 *%ptr, i8 %alt, i32 %limit) {
+; FIXME: should use a normal load instead of CS.
+; CHECK-LABEL: f20:
+; CHECK: cs {{%r[0-9]+}},
+; CHECK: jl
+; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
+; CHECK: [[LABEL]]:
+; CHECK: stc {{%r[0-9]+}},
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load atomic i8 *%ptr unordered, align 1
+  %res = select i1 %cond, i8 %orig, i8 %alt
+  store i8 %res, i8 *%ptr
+  ret void
+}
+
+; ...likewise stores.
+define void @f21(i8 *%ptr, i8 %alt, i32 %limit) {
+; FIXME: should use a normal store instead of CS.
+; CHECK-LABEL: f21:
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: lb %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: cs {{%r[0-9]+}},
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %res = select i1 %cond, i8 %orig, i8 %alt
+  store atomic i8 %res, i8 *%ptr unordered, align 1
+  ret void
+}
+
+; Try a frame index base.
+define void @f22(i8 %alt, i32 %limit) {
+; CHECK-LABEL: f22:
+; CHECK: brasl %r14, foo@PLT
+; CHECK-NOT: %r15
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r15
+; CHECK: stc {{%r[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: [[LABEL]]:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: br %r14
+  %ptr = alloca i8
+  call void @foo(i8 *%ptr)
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i8 *%ptr
+  %res = select i1 %cond, i8 %orig, i8 %alt
+  store i8 %res, i8 *%ptr
+  call void @foo(i8 *%ptr)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/cond-store-02.ll b/test/CodeGen/SystemZ/cond-store-02.ll
new file mode 100644
index 0000000..e01a853
--- /dev/null
+++ b/test/CodeGen/SystemZ/cond-store-02.ll
@@ -0,0 +1,397 @@
+; Test 16-bit conditional stores that are presented as selects.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare void @foo(i16 *)
+
+; Test the simple case, with the loaded value first.
+define void @f1(i16 *%ptr, i16 %alt, i32 %limit) {
+; CHECK-LABEL: f1:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sth %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %res = select i1 %cond, i16 %orig, i16 %alt
+  store i16 %res, i16 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f2(i16 *%ptr, i16 %alt, i32 %limit) {
+; CHECK-LABEL: f2:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sth %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %res = select i1 %cond, i16 %alt, i16 %orig
+  store i16 %res, i16 *%ptr
+  ret void
+}
+
+; Test cases where the value is explicitly sign-extended to 32 bits, with the
+; loaded value first.
+define void @f3(i16 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f3:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sth %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %ext = sext i16 %orig to i32
+  %res = select i1 %cond, i32 %ext, i32 %alt
+  %trunc = trunc i32 %res to i16
+  store i16 %trunc, i16 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f4(i16 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f4:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sth %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %ext = sext i16 %orig to i32
+  %res = select i1 %cond, i32 %alt, i32 %ext
+  %trunc = trunc i32 %res to i16
+  store i16 %trunc, i16 *%ptr
+  ret void
+}
+
+; Test cases where the value is explicitly zero-extended to 32 bits, with the
+; loaded value first.
+define void @f5(i16 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f5:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sth %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %ext = zext i16 %orig to i32
+  %res = select i1 %cond, i32 %ext, i32 %alt
+  %trunc = trunc i32 %res to i16
+  store i16 %trunc, i16 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f6(i16 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f6:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sth %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %ext = zext i16 %orig to i32
+  %res = select i1 %cond, i32 %alt, i32 %ext
+  %trunc = trunc i32 %res to i16
+  store i16 %trunc, i16 *%ptr
+  ret void
+}
+
+; Test cases where the value is explicitly sign-extended to 64 bits, with the
+; loaded value first.
+define void @f7(i16 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f7:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sth %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %ext = sext i16 %orig to i64
+  %res = select i1 %cond, i64 %ext, i64 %alt
+  %trunc = trunc i64 %res to i16
+  store i16 %trunc, i16 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f8(i16 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f8:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sth %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %ext = sext i16 %orig to i64
+  %res = select i1 %cond, i64 %alt, i64 %ext
+  %trunc = trunc i64 %res to i16
+  store i16 %trunc, i16 *%ptr
+  ret void
+}
+
+; Test cases where the value is explicitly zero-extended to 64 bits, with the
+; loaded value first.
+define void @f9(i16 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f9:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sth %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %ext = zext i16 %orig to i64
+  %res = select i1 %cond, i64 %ext, i64 %alt
+  %trunc = trunc i64 %res to i16
+  store i16 %trunc, i16 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f10(i16 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f10:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sth %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %ext = zext i16 %orig to i64
+  %res = select i1 %cond, i64 %alt, i64 %ext
+  %trunc = trunc i64 %res to i16
+  store i16 %trunc, i16 *%ptr
+  ret void
+}
+
+; Check the high end of the aligned STH range.
+define void @f11(i16 *%base, i16 %alt, i32 %limit) {
+; CHECK-LABEL: f11:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sth %r3, 4094(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i16 *%base, i64 2047
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %res = select i1 %cond, i16 %orig, i16 %alt
+  store i16 %res, i16 *%ptr
+  ret void
+}
+
+; Check the next halfword up, which should use STHY instead of STH.
+define void @f12(i16 *%base, i16 %alt, i32 %limit) {
+; CHECK-LABEL: f12:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sthy %r3, 4096(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i16 *%base, i64 2048
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %res = select i1 %cond, i16 %orig, i16 %alt
+  store i16 %res, i16 *%ptr
+  ret void
+}
+
+; Check the high end of the aligned STHY range.
+define void @f13(i16 *%base, i16 %alt, i32 %limit) {
+; CHECK-LABEL: f13:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sthy %r3, 524286(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i16 *%base, i64 262143
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %res = select i1 %cond, i16 %orig, i16 %alt
+  store i16 %res, i16 *%ptr
+  ret void
+}
+
+; Check the next halfword up, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define void @f14(i16 *%base, i16 %alt, i32 %limit) {
+; CHECK-LABEL: f14:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: agfi %r2, 524288
+; CHECK: sth %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i16 *%base, i64 262144
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %res = select i1 %cond, i16 %orig, i16 %alt
+  store i16 %res, i16 *%ptr
+  ret void
+}
+
+; Check the low end of the STHY range.
+define void @f15(i16 *%base, i16 %alt, i32 %limit) {
+; CHECK-LABEL: f15:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sthy %r3, -524288(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i16 *%base, i64 -262144
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %res = select i1 %cond, i16 %orig, i16 %alt
+  store i16 %res, i16 *%ptr
+  ret void
+}
+
+; Check the next halfword down, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define void @f16(i16 *%base, i16 %alt, i32 %limit) {
+; CHECK-LABEL: f16:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: agfi %r2, -524290
+; CHECK: sth %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i16 *%base, i64 -262145
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %res = select i1 %cond, i16 %orig, i16 %alt
+  store i16 %res, i16 *%ptr
+  ret void
+}
+
+; Check that STHY allows an index.
+define void @f17(i64 %base, i64 %index, i16 %alt, i32 %limit) {
+; CHECK-LABEL: f17:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sthy %r4, 4096(%r3,%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %add1 = add i64 %base, %index
+  %add2 = add i64 %add1, 4096
+  %ptr = inttoptr i64 %add2 to i16 *
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %res = select i1 %cond, i16 %orig, i16 %alt
+  store i16 %res, i16 *%ptr
+  ret void
+}
+
+; Check that volatile loads are not matched.
+define void @f18(i16 *%ptr, i16 %alt, i32 %limit) {
+; CHECK-LABEL: f18:
+; CHECK: lh {{%r[0-5]}}, 0(%r2)
+; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
+; CHECK: [[LABEL]]:
+; CHECK: sth {{%r[0-5]}}, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load volatile i16 *%ptr
+  %res = select i1 %cond, i16 %orig, i16 %alt
+  store i16 %res, i16 *%ptr
+  ret void
+}
+
+; ...likewise stores.  In this case we should have a conditional load into %r3.
+define void @f19(i16 *%ptr, i16 %alt, i32 %limit) {
+; CHECK-LABEL: f19:
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: lh %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: sth %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %res = select i1 %cond, i16 %orig, i16 %alt
+  store volatile i16 %res, i16 *%ptr
+  ret void
+}
+
+; Check that atomic loads are not matched.  The transformation is OK for
+; the "unordered" case tested here, but since we don't try to handle atomic
+; operations at all in this context, it seems better to assert that than
+; to restrict the test to a stronger ordering.
+define void @f20(i16 *%ptr, i16 %alt, i32 %limit) {
+; FIXME: should use a normal load instead of CS.
+; CHECK-LABEL: f20:
+; CHECK: cs {{%r[0-9]+}},
+; CHECK: jl
+; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
+; CHECK: [[LABEL]]:
+; CHECK: sth {{%r[0-9]+}},
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load atomic i16 *%ptr unordered, align 2
+  %res = select i1 %cond, i16 %orig, i16 %alt
+  store i16 %res, i16 *%ptr
+  ret void
+}
+
+; ...likewise stores.
+define void @f21(i16 *%ptr, i16 %alt, i32 %limit) {
+; FIXME: should use a normal store instead of CS.
+; CHECK-LABEL: f21:
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: lh %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: cs {{%r[0-9]+}},
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %res = select i1 %cond, i16 %orig, i16 %alt
+  store atomic i16 %res, i16 *%ptr unordered, align 2
+  ret void
+}
+
+; Try a frame index base.
+define void @f22(i16 %alt, i32 %limit) {
+; CHECK-LABEL: f22:
+; CHECK: brasl %r14, foo@PLT
+; CHECK-NOT: %r15
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r15
+; CHECK: sth {{%r[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: [[LABEL]]:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: br %r14
+  %ptr = alloca i16
+  call void @foo(i16 *%ptr)
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i16 *%ptr
+  %res = select i1 %cond, i16 %orig, i16 %alt
+  store i16 %res, i16 *%ptr
+  call void @foo(i16 *%ptr)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/cond-store-03.ll b/test/CodeGen/SystemZ/cond-store-03.ll
new file mode 100644
index 0000000..e122bc2
--- /dev/null
+++ b/test/CodeGen/SystemZ/cond-store-03.ll
@@ -0,0 +1,322 @@
+; Test 32-bit conditional stores that are presented as selects.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+
+declare void @foo(i32 *)
+
+; Test the simple case, with the loaded value first.
+define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f1:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: st %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f2:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: st %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %alt, i32 %orig
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Test cases where the value is explicitly sign-extended to 64 bits, with the
+; loaded value first.
+define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f3:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: st %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %ext = sext i32 %orig to i64
+  %res = select i1 %cond, i64 %ext, i64 %alt
+  %trunc = trunc i64 %res to i32
+  store i32 %trunc, i32 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f4:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: st %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %ext = sext i32 %orig to i64
+  %res = select i1 %cond, i64 %alt, i64 %ext
+  %trunc = trunc i64 %res to i32
+  store i32 %trunc, i32 *%ptr
+  ret void
+}
+
+; Test cases where the value is explicitly zero-extended to 32 bits, with the
+; loaded value first.
+define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f5:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: st %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %ext = zext i32 %orig to i64
+  %res = select i1 %cond, i64 %ext, i64 %alt
+  %trunc = trunc i64 %res to i32
+  store i32 %trunc, i32 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f6:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: st %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %ext = zext i32 %orig to i64
+  %res = select i1 %cond, i64 %alt, i64 %ext
+  %trunc = trunc i64 %res to i32
+  store i32 %trunc, i32 *%ptr
+  ret void
+}
+
+; Check the high end of the aligned ST range.
+define void @f7(i32 *%base, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f7:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: st %r3, 4092(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 1023
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Check the next word up, which should use STY instead of ST.
+define void @f8(i32 *%base, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f8:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sty %r3, 4096(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 1024
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Check the high end of the aligned STY range.
+define void @f9(i32 *%base, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f9:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sty %r3, 524284(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 131071
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Check the next word up, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define void @f10(i32 *%base, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f10:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: agfi %r2, 524288
+; CHECK: st %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 131072
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Check the low end of the STY range.
+define void @f11(i32 *%base, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f11:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sty %r3, -524288(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 -131072
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Check the next word down, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define void @f12(i32 *%base, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f12:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: agfi %r2, -524292
+; CHECK: st %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 -131073
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Check that STY allows an index.
+define void @f13(i64 %base, i64 %index, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f13:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: sty %r4, 4096(%r3,%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %add1 = add i64 %base, %index
+  %add2 = add i64 %add1, 4096
+  %ptr = inttoptr i64 %add2 to i32 *
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Check that volatile loads are not matched.
+define void @f14(i32 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f14:
+; CHECK: l {{%r[0-5]}}, 0(%r2)
+; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
+; CHECK: [[LABEL]]:
+; CHECK: st {{%r[0-5]}}, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load volatile i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; ...likewise stores.  In this case we should have a conditional load into %r3.
+define void @f15(i32 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f15:
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: l %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: st %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store volatile i32 %res, i32 *%ptr
+  ret void
+}
+
+; Check that atomic loads are not matched.  The transformation is OK for
+; the "unordered" case tested here, but since we don't try to handle atomic
+; operations at all in this context, it seems better to assert that than
+; to restrict the test to a stronger ordering.
+define void @f16(i32 *%ptr, i32 %alt, i32 %limit) {
+; FIXME: should use a normal load instead of CS.
+; CHECK-LABEL: f16:
+; CHECK: cs {{%r[0-5]}}, {{%r[0-5]}}, 0(%r2)
+; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
+; CHECK: [[LABEL]]:
+; CHECK: st {{%r[0-5]}}, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load atomic i32 *%ptr unordered, align 4
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; ...likewise stores.
+define void @f17(i32 *%ptr, i32 %alt, i32 %limit) {
+; FIXME: should use a normal store instead of CS.
+; CHECK-LABEL: f17:
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: l %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: cs {{%r[0-5]}}, %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store atomic i32 %res, i32 *%ptr unordered, align 4
+  ret void
+}
+
+; Try a frame index base.
+define void @f18(i32 %alt, i32 %limit) {
+; CHECK-LABEL: f18:
+; CHECK: brasl %r14, foo@PLT
+; CHECK-NOT: %r15
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r15
+; CHECK: st {{%r[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: [[LABEL]]:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: br %r14
+  %ptr = alloca i32
+  call void @foo(i32 *%ptr)
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  call void @foo(i32 *%ptr)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/cond-store-04.ll b/test/CodeGen/SystemZ/cond-store-04.ll
new file mode 100644
index 0000000..4ed23a3
--- /dev/null
+++ b/test/CodeGen/SystemZ/cond-store-04.ll
@@ -0,0 +1,214 @@
+; Test 64-bit conditional stores that are presented as selects.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+
+declare void @foo(i64 *)
+
+; Test with the loaded value first.
+define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f1:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stg %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f2:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stg %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %alt, i64 %orig
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Check the high end of the aligned STG range.
+define void @f3(i64 *%base, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f3:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stg %r3, 524280(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 65535
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Check the next doubleword up, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define void @f4(i64 *%base, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f4:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: agfi %r2, 524288
+; CHECK: stg %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 65536
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Check the low end of the STG range.
+define void @f5(i64 *%base, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f5:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stg %r3, -524288(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 -65536
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Check the next doubleword down, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define void @f6(i64 *%base, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f6:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: agfi %r2, -524296
+; CHECK: stg %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 -65537
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Check that STG allows an index.
+define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f7:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stg %r4, 524287(%r3,%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %add1 = add i64 %base, %index
+  %add2 = add i64 %add1, 524287
+  %ptr = inttoptr i64 %add2 to i64 *
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Check that volatile loads are not matched.
+define void @f8(i64 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f8:
+; CHECK: lg {{%r[0-5]}}, 0(%r2)
+; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
+; CHECK: [[LABEL]]:
+; CHECK: stg {{%r[0-5]}}, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load volatile i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; ...likewise stores.  In this case we should have a conditional load into %r3.
+define void @f9(i64 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f9:
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: lg %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: stg %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store volatile i64 %res, i64 *%ptr
+  ret void
+}
+
+; Check that atomic loads are not matched.  The transformation is OK for
+; the "unordered" case tested here, but since we don't try to handle atomic
+; operations at all in this context, it seems better to assert that than
+; to restrict the test to a stronger ordering.
+define void @f10(i64 *%ptr, i64 %alt, i32 %limit) {
+; FIXME: should use a normal load instead of CSG.
+; CHECK-LABEL: f10:
+; CHECK: csg {{%r[0-5]}}, {{%r[0-5]}}, 0(%r2)
+; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
+; CHECK: [[LABEL]]:
+; CHECK: stg {{%r[0-5]}}, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load atomic i64 *%ptr unordered, align 8
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; ...likewise stores.
+define void @f11(i64 *%ptr, i64 %alt, i32 %limit) {
+; FIXME: should use a normal store instead of CSG.
+; CHECK-LABEL: f11:
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: lg %r3, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: csg {{%r[0-5]}}, %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store atomic i64 %res, i64 *%ptr unordered, align 8
+  ret void
+}
+
+; Try a frame index base.
+define void @f12(i64 %alt, i32 %limit) {
+; CHECK-LABEL: f12:
+; CHECK: brasl %r14, foo@PLT
+; CHECK-NOT: %r15
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r15
+; CHECK: stg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: [[LABEL]]:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: br %r14
+  %ptr = alloca i64
+  call void @foo(i64 *%ptr)
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  call void @foo(i64 *%ptr)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/cond-store-05.ll b/test/CodeGen/SystemZ/cond-store-05.ll
new file mode 100644
index 0000000..e41c8fe
--- /dev/null
+++ b/test/CodeGen/SystemZ/cond-store-05.ll
@@ -0,0 +1,213 @@
+; Test f32 conditional stores that are presented as selects.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare void @foo(float *)
+
+; Test with the loaded value first.
+define void @f1(float *%ptr, float %alt, i32 %limit) {
+; CHECK-LABEL: f1:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: ste %f0, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load float *%ptr
+  %res = select i1 %cond, float %orig, float %alt
+  store float %res, float *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f2(float *%ptr, float %alt, i32 %limit) {
+; CHECK-LABEL: f2:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: ste %f0, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load float *%ptr
+  %res = select i1 %cond, float %alt, float %orig
+  store float %res, float *%ptr
+  ret void
+}
+
+; Check the high end of the aligned STE range.
+define void @f3(float *%base, float %alt, i32 %limit) {
+; CHECK-LABEL: f3:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: ste %f0, 4092(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr float *%base, i64 1023
+  %cond = icmp ult i32 %limit, 42
+  %orig = load float *%ptr
+  %res = select i1 %cond, float %orig, float %alt
+  store float %res, float *%ptr
+  ret void
+}
+
+; Check the next word up, which should use STEY instead of STE.
+define void @f4(float *%base, float %alt, i32 %limit) {
+; CHECK-LABEL: f4:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stey %f0, 4096(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr float *%base, i64 1024
+  %cond = icmp ult i32 %limit, 42
+  %orig = load float *%ptr
+  %res = select i1 %cond, float %orig, float %alt
+  store float %res, float *%ptr
+  ret void
+}
+
+; Check the high end of the aligned STEY range.
+define void @f5(float *%base, float %alt, i32 %limit) {
+; CHECK-LABEL: f5:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stey %f0, 524284(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr float *%base, i64 131071
+  %cond = icmp ult i32 %limit, 42
+  %orig = load float *%ptr
+  %res = select i1 %cond, float %orig, float %alt
+  store float %res, float *%ptr
+  ret void
+}
+
+; Check the next word up, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define void @f6(float *%base, float %alt, i32 %limit) {
+; CHECK-LABEL: f6:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: agfi %r2, 524288
+; CHECK: ste %f0, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr float *%base, i64 131072
+  %cond = icmp ult i32 %limit, 42
+  %orig = load float *%ptr
+  %res = select i1 %cond, float %orig, float %alt
+  store float %res, float *%ptr
+  ret void
+}
+
+; Check the low end of the STEY range.
+define void @f7(float *%base, float %alt, i32 %limit) {
+; CHECK-LABEL: f7:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stey %f0, -524288(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr float *%base, i64 -131072
+  %cond = icmp ult i32 %limit, 42
+  %orig = load float *%ptr
+  %res = select i1 %cond, float %orig, float %alt
+  store float %res, float *%ptr
+  ret void
+}
+
+; Check the next word down, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define void @f8(float *%base, float %alt, i32 %limit) {
+; CHECK-LABEL: f8:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: agfi %r2, -524292
+; CHECK: ste %f0, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr float *%base, i64 -131073
+  %cond = icmp ult i32 %limit, 42
+  %orig = load float *%ptr
+  %res = select i1 %cond, float %orig, float %alt
+  store float %res, float *%ptr
+  ret void
+}
+
+; Check that STEY allows an index.
+define void @f9(i64 %base, i64 %index, float %alt, i32 %limit) {
+; CHECK-LABEL: f9:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stey %f0, 4096(%r3,%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %add1 = add i64 %base, %index
+  %add2 = add i64 %add1, 4096
+  %ptr = inttoptr i64 %add2 to float *
+  %cond = icmp ult i32 %limit, 42
+  %orig = load float *%ptr
+  %res = select i1 %cond, float %orig, float %alt
+  store float %res, float *%ptr
+  ret void
+}
+
+; Check that volatile loads are not matched.
+define void @f10(float *%ptr, float %alt, i32 %limit) {
+; CHECK-LABEL: f10:
+; CHECK: le {{%f[0-5]}}, 0(%r2)
+; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
+; CHECK: [[LABEL]]:
+; CHECK: ste {{%f[0-5]}}, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load volatile float *%ptr
+  %res = select i1 %cond, float %orig, float %alt
+  store float %res, float *%ptr
+  ret void
+}
+
+; ...likewise stores.  In this case we should have a conditional load into %f0.
+define void @f11(float *%ptr, float %alt, i32 %limit) {
+; CHECK-LABEL: f11:
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: le %f0, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: ste %f0, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load float *%ptr
+  %res = select i1 %cond, float %orig, float %alt
+  store volatile float %res, float *%ptr
+  ret void
+}
+
+; Try a frame index base.
+define void @f12(float %alt, i32 %limit) {
+; CHECK-LABEL: f12:
+; CHECK: brasl %r14, foo@PLT
+; CHECK-NOT: %r15
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r15
+; CHECK: ste {{%f[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: [[LABEL]]:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: br %r14
+  %ptr = alloca float
+  call void @foo(float *%ptr)
+  %cond = icmp ult i32 %limit, 42
+  %orig = load float *%ptr
+  %res = select i1 %cond, float %orig, float %alt
+  store float %res, float *%ptr
+  call void @foo(float *%ptr)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/cond-store-06.ll b/test/CodeGen/SystemZ/cond-store-06.ll
new file mode 100644
index 0000000..759a3e0
--- /dev/null
+++ b/test/CodeGen/SystemZ/cond-store-06.ll
@@ -0,0 +1,213 @@
+; Test f64 conditional stores that are presented as selects.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare void @foo(double *)
+
+; Test with the loaded value first.
+define void @f1(double *%ptr, double %alt, i32 %limit) {
+; CHECK-LABEL: f1:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: std %f0, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load double *%ptr
+  %res = select i1 %cond, double %orig, double %alt
+  store double %res, double *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f2(double *%ptr, double %alt, i32 %limit) {
+; CHECK-LABEL: f2:
+; CHECK-NOT: %r2
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: std %f0, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load double *%ptr
+  %res = select i1 %cond, double %alt, double %orig
+  store double %res, double *%ptr
+  ret void
+}
+
+; Check the high end of the aligned STD range.
+define void @f3(double *%base, double %alt, i32 %limit) {
+; CHECK-LABEL: f3:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: std %f0, 4088(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr double *%base, i64 511
+  %cond = icmp ult i32 %limit, 42
+  %orig = load double *%ptr
+  %res = select i1 %cond, double %orig, double %alt
+  store double %res, double *%ptr
+  ret void
+}
+
+; Check the next doubleword up, which should use STDY instead of STD.
+define void @f4(double *%base, double %alt, i32 %limit) {
+; CHECK-LABEL: f4:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stdy %f0, 4096(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr double *%base, i64 512
+  %cond = icmp ult i32 %limit, 42
+  %orig = load double *%ptr
+  %res = select i1 %cond, double %orig, double %alt
+  store double %res, double *%ptr
+  ret void
+}
+
+; Check the high end of the aligned STDY range.
+define void @f5(double *%base, double %alt, i32 %limit) {
+; CHECK-LABEL: f5:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stdy %f0, 524280(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr double *%base, i64 65535
+  %cond = icmp ult i32 %limit, 42
+  %orig = load double *%ptr
+  %res = select i1 %cond, double %orig, double %alt
+  store double %res, double *%ptr
+  ret void
+}
+
+; Check the next doubleword up, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define void @f6(double *%base, double %alt, i32 %limit) {
+; CHECK-LABEL: f6:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: agfi %r2, 524288
+; CHECK: std %f0, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr double *%base, i64 65536
+  %cond = icmp ult i32 %limit, 42
+  %orig = load double *%ptr
+  %res = select i1 %cond, double %orig, double %alt
+  store double %res, double *%ptr
+  ret void
+}
+
+; Check the low end of the STDY range.
+define void @f7(double *%base, double %alt, i32 %limit) {
+; CHECK-LABEL: f7:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stdy %f0, -524288(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr double *%base, i64 -65536
+  %cond = icmp ult i32 %limit, 42
+  %orig = load double *%ptr
+  %res = select i1 %cond, double %orig, double %alt
+  store double %res, double *%ptr
+  ret void
+}
+
+; Check the next doubleword down, which needs separate address logic.
+; Other sequences besides this one would be OK.
+define void @f8(double *%base, double %alt, i32 %limit) {
+; CHECK-LABEL: f8:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: agfi %r2, -524296
+; CHECK: std %f0, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %ptr = getelementptr double *%base, i64 -65537
+  %cond = icmp ult i32 %limit, 42
+  %orig = load double *%ptr
+  %res = select i1 %cond, double %orig, double %alt
+  store double %res, double *%ptr
+  ret void
+}
+
+; Check that STDY allows an index.
+define void @f9(i64 %base, i64 %index, double %alt, i32 %limit) {
+; CHECK-LABEL: f9:
+; CHECK-NOT: %r2
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r2
+; CHECK: stdy %f0, 524287(%r3,%r2)
+; CHECK: [[LABEL]]:
+; CHECK: br %r14
+  %add1 = add i64 %base, %index
+  %add2 = add i64 %add1, 524287
+  %ptr = inttoptr i64 %add2 to double *
+  %cond = icmp ult i32 %limit, 42
+  %orig = load double *%ptr
+  %res = select i1 %cond, double %orig, double %alt
+  store double %res, double *%ptr
+  ret void
+}
+
+; Check that volatile loads are not matched.
+define void @f10(double *%ptr, double %alt, i32 %limit) {
+; CHECK-LABEL: f10:
+; CHECK: ld {{%f[0-5]}}, 0(%r2)
+; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
+; CHECK: [[LABEL]]:
+; CHECK: std {{%f[0-5]}}, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load volatile double *%ptr
+  %res = select i1 %cond, double %orig, double %alt
+  store double %res, double *%ptr
+  ret void
+}
+
+; ...likewise stores.  In this case we should have a conditional load into %f0.
+define void @f11(double *%ptr, double %alt, i32 %limit) {
+; CHECK-LABEL: f11:
+; CHECK: jhe [[LABEL:[^ ]*]]
+; CHECK: ld %f0, 0(%r2)
+; CHECK: [[LABEL]]:
+; CHECK: std %f0, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load double *%ptr
+  %res = select i1 %cond, double %orig, double %alt
+  store volatile double %res, double *%ptr
+  ret void
+}
+
+; Try a frame index base.
+define void @f12(double %alt, i32 %limit) {
+; CHECK-LABEL: f12:
+; CHECK: brasl %r14, foo@PLT
+; CHECK-NOT: %r15
+; CHECK: jl [[LABEL:[^ ]*]]
+; CHECK-NOT: %r15
+; CHECK: std {{%f[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: [[LABEL]]:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: br %r14
+  %ptr = alloca double
+  call void @foo(double *%ptr)
+  %cond = icmp ult i32 %limit, 42
+  %orig = load double *%ptr
+  %res = select i1 %cond, double %orig, double %alt
+  store double %res, double *%ptr
+  call void @foo(double *%ptr)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/cond-store-07.ll b/test/CodeGen/SystemZ/cond-store-07.ll
new file mode 100644
index 0000000..b1df525
--- /dev/null
+++ b/test/CodeGen/SystemZ/cond-store-07.ll
@@ -0,0 +1,186 @@
+; Test STOCs that are presented as selects.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare void @foo(i32 *)
+
+; Test the simple case, with the loaded value first.
+define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f1:
+; CHECK: clfi %r4, 42
+; CHECK: stoche %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f2:
+; CHECK: clfi %r4, 42
+; CHECK: stocl %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %alt, i32 %orig
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Test cases where the value is explicitly sign-extended to 64 bits, with the
+; loaded value first.
+define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f3:
+; CHECK: clfi %r4, 42
+; CHECK: stoche %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %ext = sext i32 %orig to i64
+  %res = select i1 %cond, i64 %ext, i64 %alt
+  %trunc = trunc i64 %res to i32
+  store i32 %trunc, i32 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f4:
+; CHECK: clfi %r4, 42
+; CHECK: stocl %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %ext = sext i32 %orig to i64
+  %res = select i1 %cond, i64 %alt, i64 %ext
+  %trunc = trunc i64 %res to i32
+  store i32 %trunc, i32 *%ptr
+  ret void
+}
+
+; Test cases where the value is explicitly zero-extended to 32 bits, with the
+; loaded value first.
+define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f5:
+; CHECK: clfi %r4, 42
+; CHECK: stoche %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %ext = zext i32 %orig to i64
+  %res = select i1 %cond, i64 %ext, i64 %alt
+  %trunc = trunc i64 %res to i32
+  store i32 %trunc, i32 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f6:
+; CHECK: clfi %r4, 42
+; CHECK: stocl %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %ext = zext i32 %orig to i64
+  %res = select i1 %cond, i64 %alt, i64 %ext
+  %trunc = trunc i64 %res to i32
+  store i32 %trunc, i32 *%ptr
+  ret void
+}
+
+; Check the high end of the aligned STOC range.
+define void @f7(i32 *%base, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f7:
+; CHECK: clfi %r4, 42
+; CHECK: stoche %r3, 524284(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 131071
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Check the next word up.  Other sequences besides this one would be OK.
+define void @f8(i32 *%base, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f8:
+; CHECK: agfi %r2, 524288
+; CHECK: clfi %r4, 42
+; CHECK: stoche %r3, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 131072
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Check the low end of the STOC range.
+define void @f9(i32 *%base, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f9:
+; CHECK: clfi %r4, 42
+; CHECK: stoche %r3, -524288(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 -131072
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Check the next word down, with the same comments as f8.
+define void @f10(i32 *%base, i32 %alt, i32 %limit) {
+; CHECK-LABEL: f10:
+; CHECK: agfi %r2, -524292
+; CHECK: clfi %r4, 42
+; CHECK: stoche %r3, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i32 *%base, i64 -131073
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  ret void
+}
+
+; Try a frame index base.
+define void @f11(i32 %alt, i32 %limit) {
+; CHECK-LABEL: f11:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: stoche {{%r[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: brasl %r14, foo@PLT
+; CHECK: br %r14
+  %ptr = alloca i32
+  call void @foo(i32 *%ptr)
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i32 *%ptr
+  %res = select i1 %cond, i32 %orig, i32 %alt
+  store i32 %res, i32 *%ptr
+  call void @foo(i32 *%ptr)
+  ret void
+}
+
+; Test that conditionally-executed stores do not use STOC, since STOC
+; is allowed to trap even when the condition is false.
+define void @f12(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f12:
+; CHECK-NOT: stoc
+; CHECK: br %r14
+entry:
+  %cmp = icmp ule i32 %a, %b
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/cond-store-08.ll b/test/CodeGen/SystemZ/cond-store-08.ll
new file mode 100644
index 0000000..56dc7ee
--- /dev/null
+++ b/test/CodeGen/SystemZ/cond-store-08.ll
@@ -0,0 +1,124 @@
+; Test STOCGs that are presented as selects.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare void @foo(i64 *)
+
+; Test with the loaded value first.
+define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f1:
+; CHECK: clfi %r4, 42
+; CHECK: stocghe %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; ...and with the loaded value second
+define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f2:
+; CHECK: clfi %r4, 42
+; CHECK: stocgl %r3, 0(%r2)
+; CHECK: br %r14
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %alt, i64 %orig
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Check the high end of the aligned STOCG range.
+define void @f3(i64 *%base, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f3:
+; CHECK: clfi %r4, 42
+; CHECK: stocghe %r3, 524280(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 65535
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Check the next doubleword up.  Other sequences besides this one would be OK.
+define void @f4(i64 *%base, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f4:
+; CHECK: agfi %r2, 524288
+; CHECK: clfi %r4, 42
+; CHECK: stocghe %r3, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 65536
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Check the low end of the STOCG range.
+define void @f5(i64 *%base, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f5:
+; CHECK: clfi %r4, 42
+; CHECK: stocghe %r3, -524288(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 -65536
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Check the next doubleword down, with the same comments as f4.
+define void @f6(i64 *%base, i64 %alt, i32 %limit) {
+; CHECK-LABEL: f6:
+; CHECK: agfi %r2, -524296
+; CHECK: clfi %r4, 42
+; CHECK: stocghe %r3, 0(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64 *%base, i64 -65537
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  ret void
+}
+
+; Try a frame index base.
+define void @f7(i64 %alt, i32 %limit) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: stocghe {{%r[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: brasl %r14, foo@PLT
+; CHECK: br %r14
+  %ptr = alloca i64
+  call void @foo(i64 *%ptr)
+  %cond = icmp ult i32 %limit, 42
+  %orig = load i64 *%ptr
+  %res = select i1 %cond, i64 %orig, i64 %alt
+  store i64 %res, i64 *%ptr
+  call void @foo(i64 *%ptr)
+  ret void
+}
+
+; Test that conditionally-executed stores do not use STOC, since STOC
+; is allowed to trap even when the condition is false.
+define void @f8(i64 %a, i64 %b, i64 *%dest) {
+; CHECK-LABEL: f8:
+; CHECK-NOT: stocg %r3, 0(%r4)
+; CHECK: br %r14
+entry:
+  %cmp = icmp ule i64 %a, %b
+  br i1 %cmp, label %store, label %exit
+
+store:
+  store i64 %b, i64 *%dest
+  br label %exit
+
+exit:
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/fp-abs-01.ll b/test/CodeGen/SystemZ/fp-abs-01.ll
index 81b3fb2..0b4067d 100644
--- a/test/CodeGen/SystemZ/fp-abs-01.ll
+++ b/test/CodeGen/SystemZ/fp-abs-01.ll
@@ -5,7 +5,7 @@
 ; Test f32.
 declare float @llvm.fabs.f32(float %f)
 define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lpebr %f0, %f0
 ; CHECK: br %r14
   %res = call float @llvm.fabs.f32(float %f)
@@ -15,7 +15,7 @@ define float @f1(float %f) {
 ; Test f64.
 declare double @llvm.fabs.f64(double %f)
 define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lpdbr %f0, %f0
 ; CHECK: br %r14
   %res = call double @llvm.fabs.f64(double %f)
@@ -27,7 +27,7 @@ define double @f2(double %f) {
 ; processing so that using FPRs is unequivocally better.
 declare fp128 @llvm.fabs.f128(fp128 %f)
 define void @f3(fp128 *%ptr, fp128 *%ptr2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lpxbr
 ; CHECK: dxbr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-abs-02.ll b/test/CodeGen/SystemZ/fp-abs-02.ll
index 513d49c..909c48a 100644
--- a/test/CodeGen/SystemZ/fp-abs-02.ll
+++ b/test/CodeGen/SystemZ/fp-abs-02.ll
@@ -5,7 +5,7 @@
 ; Test f32.
 declare float @llvm.fabs.f32(float %f)
 define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lnebr %f0, %f0
 ; CHECK: br %r14
   %abs = call float @llvm.fabs.f32(float %f)
@@ -16,7 +16,7 @@ define float @f1(float %f) {
 ; Test f64.
 declare double @llvm.fabs.f64(double %f)
 define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lndbr %f0, %f0
 ; CHECK: br %r14
   %abs = call double @llvm.fabs.f64(double %f)
@@ -29,7 +29,7 @@ define double @f2(double %f) {
 ; extra processing so that using FPRs is unequivocally better.
 declare fp128 @llvm.fabs.f128(fp128 %f)
 define void @f3(fp128 *%ptr, fp128 *%ptr2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lnxbr
 ; CHECK: dxbr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-add-01.ll b/test/CodeGen/SystemZ/fp-add-01.ll
index 7ce0777..28a2128 100644
--- a/test/CodeGen/SystemZ/fp-add-01.ll
+++ b/test/CodeGen/SystemZ/fp-add-01.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare float @foo()
+
 ; Check register addition.
 define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aebr %f0, %f2
 ; CHECK: br %r14
   %res = fadd float %f1, %f2
@@ -13,7 +15,7 @@ define float @f1(float %f1, float %f2) {
 
 ; Check the low end of the AEB range.
 define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aeb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load float *%ptr
@@ -23,7 +25,7 @@ define float @f2(float %f1, float *%ptr) {
 
 ; Check the high end of the aligned AEB range.
 define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aeb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -35,7 +37,7 @@ define float @f3(float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: aeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -47,7 +49,7 @@ define float @f4(float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: aeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -59,7 +61,7 @@ define float @f5(float %f1, float *%base) {
 
 ; Check that AEB allows indices.
 define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: aeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -69,3 +71,49 @@ define float @f6(float %f1, float *%base, i64 %index) {
   %res = fadd float %f1, %f2
   ret float %res
 }
+
+; Check that additions of spilled values can use AEB rather than AEBR.
+define float @f7(float *%ptr0) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: aeb %f0, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr float *%ptr0, i64 2
+  %ptr2 = getelementptr float *%ptr0, i64 4
+  %ptr3 = getelementptr float *%ptr0, i64 6
+  %ptr4 = getelementptr float *%ptr0, i64 8
+  %ptr5 = getelementptr float *%ptr0, i64 10
+  %ptr6 = getelementptr float *%ptr0, i64 12
+  %ptr7 = getelementptr float *%ptr0, i64 14
+  %ptr8 = getelementptr float *%ptr0, i64 16
+  %ptr9 = getelementptr float *%ptr0, i64 18
+  %ptr10 = getelementptr float *%ptr0, i64 20
+
+  %val0 = load float *%ptr0
+  %val1 = load float *%ptr1
+  %val2 = load float *%ptr2
+  %val3 = load float *%ptr3
+  %val4 = load float *%ptr4
+  %val5 = load float *%ptr5
+  %val6 = load float *%ptr6
+  %val7 = load float *%ptr7
+  %val8 = load float *%ptr8
+  %val9 = load float *%ptr9
+  %val10 = load float *%ptr10
+
+  %ret = call float @foo()
+
+  %add0 = fadd float %ret, %val0
+  %add1 = fadd float %add0, %val1
+  %add2 = fadd float %add1, %val2
+  %add3 = fadd float %add2, %val3
+  %add4 = fadd float %add3, %val4
+  %add5 = fadd float %add4, %val5
+  %add6 = fadd float %add5, %val6
+  %add7 = fadd float %add6, %val7
+  %add8 = fadd float %add7, %val8
+  %add9 = fadd float %add8, %val9
+  %add10 = fadd float %add9, %val10
+
+  ret float %add10
+}
diff --git a/test/CodeGen/SystemZ/fp-add-02.ll b/test/CodeGen/SystemZ/fp-add-02.ll
index 08eb90e..067c747 100644
--- a/test/CodeGen/SystemZ/fp-add-02.ll
+++ b/test/CodeGen/SystemZ/fp-add-02.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare double @foo()
+
 ; Check register addition.
 define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: adbr %f0, %f2
 ; CHECK: br %r14
   %res = fadd double %f1, %f2
@@ -13,7 +15,7 @@ define double @f1(double %f1, double %f2) {
 
 ; Check the low end of the ADB range.
 define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: adb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load double *%ptr
@@ -23,7 +25,7 @@ define double @f2(double %f1, double *%ptr) {
 
 ; Check the high end of the aligned ADB range.
 define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: adb %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%base, i64 511
@@ -35,7 +37,7 @@ define double @f3(double %f1, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: adb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -47,7 +49,7 @@ define double @f4(double %f1, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: adb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -59,7 +61,7 @@ define double @f5(double %f1, double *%base) {
 
 ; Check that ADB allows indices.
 define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: adb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
@@ -69,3 +71,49 @@ define double @f6(double %f1, double *%base, i64 %index) {
   %res = fadd double %f1, %f2
   ret double %res
 }
+
+; Check that additions of spilled values can use ADB rather than ADBR.
+define double @f7(double *%ptr0) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: adb %f0, 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr double *%ptr0, i64 2
+  %ptr2 = getelementptr double *%ptr0, i64 4
+  %ptr3 = getelementptr double *%ptr0, i64 6
+  %ptr4 = getelementptr double *%ptr0, i64 8
+  %ptr5 = getelementptr double *%ptr0, i64 10
+  %ptr6 = getelementptr double *%ptr0, i64 12
+  %ptr7 = getelementptr double *%ptr0, i64 14
+  %ptr8 = getelementptr double *%ptr0, i64 16
+  %ptr9 = getelementptr double *%ptr0, i64 18
+  %ptr10 = getelementptr double *%ptr0, i64 20
+
+  %val0 = load double *%ptr0
+  %val1 = load double *%ptr1
+  %val2 = load double *%ptr2
+  %val3 = load double *%ptr3
+  %val4 = load double *%ptr4
+  %val5 = load double *%ptr5
+  %val6 = load double *%ptr6
+  %val7 = load double *%ptr7
+  %val8 = load double *%ptr8
+  %val9 = load double *%ptr9
+  %val10 = load double *%ptr10
+
+  %ret = call double @foo()
+
+  %add0 = fadd double %ret, %val0
+  %add1 = fadd double %add0, %val1
+  %add2 = fadd double %add1, %val2
+  %add3 = fadd double %add2, %val3
+  %add4 = fadd double %add3, %val4
+  %add5 = fadd double %add4, %val5
+  %add6 = fadd double %add5, %val6
+  %add7 = fadd double %add6, %val7
+  %add8 = fadd double %add7, %val8
+  %add9 = fadd double %add8, %val9
+  %add10 = fadd double %add9, %val10
+
+  ret double %add10
+}
diff --git a/test/CodeGen/SystemZ/fp-add-03.ll b/test/CodeGen/SystemZ/fp-add-03.ll
index 13ffb02..cb4042e 100644
--- a/test/CodeGen/SystemZ/fp-add-03.ll
+++ b/test/CodeGen/SystemZ/fp-add-03.ll
@@ -4,7 +4,7 @@
 
 ; There is no memory form of 128-bit addition.
 define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r2)
 ; CHECK: ld %f3, 8(%r2)
diff --git a/test/CodeGen/SystemZ/fp-cmp-01.ll b/test/CodeGen/SystemZ/fp-cmp-01.ll
index cb2a6be..6a9598e 100644
--- a/test/CodeGen/SystemZ/fp-cmp-01.ll
+++ b/test/CodeGen/SystemZ/fp-cmp-01.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare float @foo()
+
 ; Check comparison with registers.
 define i64 @f1(i64 %a, i64 %b, float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cebr %f0, %f2
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -16,7 +18,7 @@ define i64 @f1(i64 %a, i64 %b, float %f1, float %f2) {
 
 ; Check the low end of the CEB range.
 define i64 @f2(i64 %a, i64 %b, float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ceb %f0, 0(%r4)
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -29,7 +31,7 @@ define i64 @f2(i64 %a, i64 %b, float %f1, float *%ptr) {
 
 ; Check the high end of the aligned CEB range.
 define i64 @f3(i64 %a, i64 %b, float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ceb %f0, 4092(%r4)
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -44,7 +46,7 @@ define i64 @f3(i64 %a, i64 %b, float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 %b, float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r4, 4096
 ; CHECK: ceb %f0, 0(%r4)
 ; CHECK-NEXT: je
@@ -59,7 +61,7 @@ define i64 @f4(i64 %a, i64 %b, float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define i64 @f5(i64 %a, i64 %b, float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r4, -4
 ; CHECK: ceb %f0, 0(%r4)
 ; CHECK-NEXT: je
@@ -74,7 +76,7 @@ define i64 @f5(i64 %a, i64 %b, float %f1, float *%base) {
 
 ; Check that CEB allows indices.
 define i64 @f6(i64 %a, i64 %b, float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r5, 2
 ; CHECK: ceb %f0, 400(%r1,%r4)
 ; CHECK-NEXT: je
@@ -87,3 +89,73 @@ define i64 @f6(i64 %a, i64 %b, float %f1, float *%base, i64 %index) {
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
+
+; Check that comparisons of spilled values can use CEB rather than CEBR.
+define float @f7(float *%ptr0) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: ceb {{%f[0-9]+}}, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr float *%ptr0, i64 2
+  %ptr2 = getelementptr float *%ptr0, i64 4
+  %ptr3 = getelementptr float *%ptr0, i64 6
+  %ptr4 = getelementptr float *%ptr0, i64 8
+  %ptr5 = getelementptr float *%ptr0, i64 10
+  %ptr6 = getelementptr float *%ptr0, i64 12
+  %ptr7 = getelementptr float *%ptr0, i64 14
+  %ptr8 = getelementptr float *%ptr0, i64 16
+  %ptr9 = getelementptr float *%ptr0, i64 18
+  %ptr10 = getelementptr float *%ptr0, i64 20
+
+  %val0 = load float *%ptr0
+  %val1 = load float *%ptr1
+  %val2 = load float *%ptr2
+  %val3 = load float *%ptr3
+  %val4 = load float *%ptr4
+  %val5 = load float *%ptr5
+  %val6 = load float *%ptr6
+  %val7 = load float *%ptr7
+  %val8 = load float *%ptr8
+  %val9 = load float *%ptr9
+  %val10 = load float *%ptr10
+
+  %ret = call float @foo()
+
+  %cmp0 = fcmp olt float %ret, %val0
+  %cmp1 = fcmp olt float %ret, %val1
+  %cmp2 = fcmp olt float %ret, %val2
+  %cmp3 = fcmp olt float %ret, %val3
+  %cmp4 = fcmp olt float %ret, %val4
+  %cmp5 = fcmp olt float %ret, %val5
+  %cmp6 = fcmp olt float %ret, %val6
+  %cmp7 = fcmp olt float %ret, %val7
+  %cmp8 = fcmp olt float %ret, %val8
+  %cmp9 = fcmp olt float %ret, %val9
+  %cmp10 = fcmp olt float %ret, %val10
+
+  %sel0 = select i1 %cmp0, float %ret, float 0.0
+  %sel1 = select i1 %cmp1, float %sel0, float 1.0
+  %sel2 = select i1 %cmp2, float %sel1, float 2.0
+  %sel3 = select i1 %cmp3, float %sel2, float 3.0
+  %sel4 = select i1 %cmp4, float %sel3, float 4.0
+  %sel5 = select i1 %cmp5, float %sel4, float 5.0
+  %sel6 = select i1 %cmp6, float %sel5, float 6.0
+  %sel7 = select i1 %cmp7, float %sel6, float 7.0
+  %sel8 = select i1 %cmp8, float %sel7, float 8.0
+  %sel9 = select i1 %cmp9, float %sel8, float 9.0
+  %sel10 = select i1 %cmp10, float %sel9, float 10.0
+
+  ret float %sel10
+}
+
+; Check comparison with zero.
+define i64 @f8(i64 %a, i64 %b, float %f) {
+; CHECK-LABEL: f8:
+; CHECK: ltebr %f0, %f0
+; CHECK-NEXT: je
+; CHECK: lgr %r2, %r3
+; CHECK: br %r14
+  %cond = fcmp oeq float %f, 0.0
+  %res = select i1 %cond, i64 %a, i64 %b
+  ret i64 %res
+}
diff --git a/test/CodeGen/SystemZ/fp-cmp-02.ll b/test/CodeGen/SystemZ/fp-cmp-02.ll
index 2987d50..309d12e 100644
--- a/test/CodeGen/SystemZ/fp-cmp-02.ll
+++ b/test/CodeGen/SystemZ/fp-cmp-02.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare double @foo()
+
 ; Check comparison with registers.
 define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cdbr %f0, %f2
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -16,7 +18,7 @@ define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) {
 
 ; Check the low end of the CDB range.
 define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cdb %f0, 0(%r4)
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -29,7 +31,7 @@ define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) {
 
 ; Check the high end of the aligned CDB range.
 define i64 @f3(i64 %a, i64 %b, double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cdb %f0, 4088(%r4)
 ; CHECK-NEXT: je
 ; CHECK: lgr %r2, %r3
@@ -44,7 +46,7 @@ define i64 @f3(i64 %a, i64 %b, double %f1, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 %b, double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r4, 4096
 ; CHECK: cdb %f0, 0(%r4)
 ; CHECK-NEXT: je
@@ -59,7 +61,7 @@ define i64 @f4(i64 %a, i64 %b, double %f1, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define i64 @f5(i64 %a, i64 %b, double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r4, -8
 ; CHECK: cdb %f0, 0(%r4)
 ; CHECK-NEXT: je
@@ -74,7 +76,7 @@ define i64 @f5(i64 %a, i64 %b, double %f1, double *%base) {
 
 ; Check that CDB allows indices.
 define i64 @f6(i64 %a, i64 %b, double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r5, 3
 ; CHECK: cdb %f0, 800(%r1,%r4)
 ; CHECK-NEXT: je
@@ -87,3 +89,73 @@ define i64 @f6(i64 %a, i64 %b, double %f1, double *%base, i64 %index) {
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
+
+; Check that comparisons of spilled values can use CDB rather than CDBR.
+define double @f7(double *%ptr0) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: cdb {{%f[0-9]+}}, 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr double *%ptr0, i64 2
+  %ptr2 = getelementptr double *%ptr0, i64 4
+  %ptr3 = getelementptr double *%ptr0, i64 6
+  %ptr4 = getelementptr double *%ptr0, i64 8
+  %ptr5 = getelementptr double *%ptr0, i64 10
+  %ptr6 = getelementptr double *%ptr0, i64 12
+  %ptr7 = getelementptr double *%ptr0, i64 14
+  %ptr8 = getelementptr double *%ptr0, i64 16
+  %ptr9 = getelementptr double *%ptr0, i64 18
+  %ptr10 = getelementptr double *%ptr0, i64 20
+
+  %val0 = load double *%ptr0
+  %val1 = load double *%ptr1
+  %val2 = load double *%ptr2
+  %val3 = load double *%ptr3
+  %val4 = load double *%ptr4
+  %val5 = load double *%ptr5
+  %val6 = load double *%ptr6
+  %val7 = load double *%ptr7
+  %val8 = load double *%ptr8
+  %val9 = load double *%ptr9
+  %val10 = load double *%ptr10
+
+  %ret = call double @foo()
+
+  %cmp0 = fcmp olt double %ret, %val0
+  %cmp1 = fcmp olt double %ret, %val1
+  %cmp2 = fcmp olt double %ret, %val2
+  %cmp3 = fcmp olt double %ret, %val3
+  %cmp4 = fcmp olt double %ret, %val4
+  %cmp5 = fcmp olt double %ret, %val5
+  %cmp6 = fcmp olt double %ret, %val6
+  %cmp7 = fcmp olt double %ret, %val7
+  %cmp8 = fcmp olt double %ret, %val8
+  %cmp9 = fcmp olt double %ret, %val9
+  %cmp10 = fcmp olt double %ret, %val10
+
+  %sel0 = select i1 %cmp0, double %ret, double 0.0
+  %sel1 = select i1 %cmp1, double %sel0, double 1.0
+  %sel2 = select i1 %cmp2, double %sel1, double 2.0
+  %sel3 = select i1 %cmp3, double %sel2, double 3.0
+  %sel4 = select i1 %cmp4, double %sel3, double 4.0
+  %sel5 = select i1 %cmp5, double %sel4, double 5.0
+  %sel6 = select i1 %cmp6, double %sel5, double 6.0
+  %sel7 = select i1 %cmp7, double %sel6, double 7.0
+  %sel8 = select i1 %cmp8, double %sel7, double 8.0
+  %sel9 = select i1 %cmp9, double %sel8, double 9.0
+  %sel10 = select i1 %cmp10, double %sel9, double 10.0
+
+  ret double %sel10
+}
+
+; Check comparison with zero.
+define i64 @f8(i64 %a, i64 %b, double %f) {
+; CHECK-LABEL: f8:
+; CHECK: ltdbr %f0, %f0
+; CHECK-NEXT: je
+; CHECK: lgr %r2, %r3
+; CHECK: br %r14
+  %cond = fcmp oeq double %f, 0.0
+  %res = select i1 %cond, i64 %a, i64 %b
+  ret i64 %res
+}
diff --git a/test/CodeGen/SystemZ/fp-cmp-03.ll b/test/CodeGen/SystemZ/fp-cmp-03.ll
index 1a5009e..0f71f4e 100644
--- a/test/CodeGen/SystemZ/fp-cmp-03.ll
+++ b/test/CodeGen/SystemZ/fp-cmp-03.ll
@@ -4,7 +4,7 @@
 
 ; There is no memory form of 128-bit comparison.
 define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r4)
 ; CHECK: ld %f3, 8(%r4)
@@ -18,3 +18,18 @@ define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) {
   %res = select i1 %cond, i64 %a, i64 %b
   ret i64 %res
 }
+
+; Check comparison with zero.
+define i64 @f2(i64 %a, i64 %b, fp128 *%ptr) {
+; CHECK-LABEL: f2:
+; CHECK: ld %f0, 0(%r4)
+; CHECK: ld %f2, 8(%r4)
+; CHECK: ltxbr %f0, %f0
+; CHECK-NEXT: je
+; CHECK: lgr %r2, %r3
+; CHECK: br %r14
+  %f = load fp128 *%ptr
+  %cond = fcmp oeq fp128 %f, 0xL00000000000000000000000000000000
+  %res = select i1 %cond, i64 %a, i64 %b
+  ret i64 %res
+}
diff --git a/test/CodeGen/SystemZ/fp-cmp-04.ll b/test/CodeGen/SystemZ/fp-cmp-04.ll
new file mode 100644
index 0000000..8d84216
--- /dev/null
+++ b/test/CodeGen/SystemZ/fp-cmp-04.ll
@@ -0,0 +1,348 @@
+; Test that floating-point compares are ommitted if CC already has the
+; right value.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+
+declare float @llvm.fabs.f32(float %f)
+
+; Test addition followed by EQ, which can use the CC result of the addition.
+define float @f1(float %a, float %b, float *%dest) {
+; CHECK-LABEL: f1:
+; CHECK: aebr %f0, %f2
+; CHECK-NEXT: je .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = fadd float %a, %b
+  %cmp = fcmp oeq float %res, 0.0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store float %b, float *%dest
+  br label %exit
+
+exit:
+  ret float %res
+}
+
+; ...and again with LT.
+define float @f2(float %a, float %b, float *%dest) {
+; CHECK-LABEL: f2:
+; CHECK: aebr %f0, %f2
+; CHECK-NEXT: jl .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = fadd float %a, %b
+  %cmp = fcmp olt float %res, 0.0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store float %b, float *%dest
+  br label %exit
+
+exit:
+  ret float %res
+}
+
+; ...and again with GT.
+define float @f3(float %a, float %b, float *%dest) {
+; CHECK-LABEL: f3:
+; CHECK: aebr %f0, %f2
+; CHECK-NEXT: jh .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = fadd float %a, %b
+  %cmp = fcmp ogt float %res, 0.0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store float %b, float *%dest
+  br label %exit
+
+exit:
+  ret float %res
+}
+
+; ...and again with UEQ.
+define float @f4(float %a, float %b, float *%dest) {
+; CHECK-LABEL: f4:
+; CHECK: aebr %f0, %f2
+; CHECK-NEXT: jnlh .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = fadd float %a, %b
+  %cmp = fcmp ueq float %res, 0.0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store float %b, float *%dest
+  br label %exit
+
+exit:
+  ret float %res
+}
+
+; Subtraction also provides a zero-based CC value.
+define float @f5(float %a, float %b, float *%dest) {
+; CHECK-LABEL: f5:
+; CHECK: seb %f0, 0(%r2)
+; CHECK-NEXT: jnhe .L{{.*}}
+; CHECK: br %r14
+entry:
+  %cur = load float *%dest
+  %res = fsub float %a, %cur
+  %cmp = fcmp ult float %res, 0.0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store float %b, float *%dest
+  br label %exit
+
+exit:
+  ret float %res
+}
+
+; Test the result of LOAD POSITIVE.
+define float @f6(float %dummy, float %a, float *%dest) {
+; CHECK-LABEL: f6:
+; CHECK: lpebr %f0, %f2
+; CHECK-NEXT: jh .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = call float @llvm.fabs.f32(float %a)
+  %cmp = fcmp ogt float %res, 0.0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store float %res, float *%dest
+  br label %exit
+
+exit:
+  ret float %res
+}
+
+; Test the result of LOAD NEGATIVE.
+define float @f7(float %dummy, float %a, float *%dest) {
+; CHECK-LABEL: f7:
+; CHECK: lnebr %f0, %f2
+; CHECK-NEXT: jl .L{{.*}}
+; CHECK: br %r14
+entry:
+  %abs = call float @llvm.fabs.f32(float %a)
+  %res = fsub float -0.0, %abs
+  %cmp = fcmp olt float %res, 0.0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store float %res, float *%dest
+  br label %exit
+
+exit:
+  ret float %res
+}
+
+; Test the result of LOAD COMPLEMENT.
+define float @f8(float %dummy, float %a, float *%dest) {
+; CHECK-LABEL: f8:
+; CHECK: lcebr %f0, %f2
+; CHECK-NEXT: jle .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = fsub float -0.0, %a
+  %cmp = fcmp ole float %res, 0.0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store float %res, float *%dest
+  br label %exit
+
+exit:
+  ret float %res
+}
+
+; Multiplication (for example) does not modify CC.
+define float @f9(float %a, float %b, float *%dest) {
+; CHECK-LABEL: f9:
+; CHECK: meebr %f0, %f2
+; CHECK-NEXT: ltebr %f0, %f0
+; CHECK-NEXT: jlh .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = fmul float %a, %b
+  %cmp = fcmp one float %res, 0.0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store float %b, float *%dest
+  br label %exit
+
+exit:
+  ret float %res
+}
+
+; Test a combination involving a CC-setting instruction followed by
+; a non-CC-setting instruction.
+define float @f10(float %a, float %b, float %c, float *%dest) {
+; CHECK-LABEL: f10:
+; CHECK: aebr %f0, %f2
+; CHECK-NEXT: debr %f0, %f4
+; CHECK-NEXT: ltebr %f0, %f0
+; CHECK-NEXT: jne .L{{.*}}
+; CHECK: br %r14
+entry:
+  %add = fadd float %a, %b
+  %res = fdiv float %add, %c
+  %cmp = fcmp une float %res, 0.0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store float %b, float *%dest
+  br label %exit
+
+exit:
+  ret float %res
+}
+
+; Test a case where CC is set based on a different register from the
+; compare input.
+define float @f11(float %a, float %b, float %c, float *%dest1, float *%dest2) {
+; CHECK-LABEL: f11:
+; CHECK: aebr %f0, %f2
+; CHECK-NEXT: sebr %f4, %f0
+; CHECK-NEXT: ste %f4, 0(%r2)
+; CHECK-NEXT: ltebr %f0, %f0
+; CHECK-NEXT: je .L{{.*}}
+; CHECK: br %r14
+entry:
+  %add = fadd float %a, %b
+  %sub = fsub float %c, %add
+  store float %sub, float *%dest1
+  %cmp = fcmp oeq float %add, 0.0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store float %sub, float *%dest2
+  br label %exit
+
+exit:
+  ret float %add
+}
+
+; Test that LER gets converted to LTEBR where useful.
+define float @f12(float %dummy, float %val, float *%dest) {
+; CHECK-LABEL: f12:
+; CHECK: ltebr %f0, %f2
+; CHECK-NEXT: #APP
+; CHECK-NEXT: blah %f0
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jl .L{{.*}}
+; CHECK: br %r14
+entry:
+  call void asm sideeffect "blah $0", "{f0}"(float %val)
+  %cmp = fcmp olt float %val, 0.0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store float %val, float *%dest
+  br label %exit
+
+exit:
+  ret float %val
+}
+
+; Test that LDR gets converted to LTDBR where useful.
+define double @f13(double %dummy, double %val, double *%dest) {
+; CHECK-LABEL: f13:
+; CHECK: ltdbr %f0, %f2
+; CHECK-NEXT: #APP
+; CHECK-NEXT: blah %f0
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jl .L{{.*}}
+; CHECK: br %r14
+entry:
+  call void asm sideeffect "blah $0", "{f0}"(double %val)
+  %cmp = fcmp olt double %val, 0.0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store double %val, double *%dest
+  br label %exit
+
+exit:
+  ret double %val
+}
+
+; Test that LXR gets converted to LTXBR where useful.
+define void @f14(fp128 *%ptr1, fp128 *%ptr2) {
+; CHECK-LABEL: f14:
+; CHECK: ltxbr
+; CHECK-NEXT: dxbr
+; CHECK-NEXT: std
+; CHECK-NEXT: std
+; CHECK-NEXT: mxbr
+; CHECK-NEXT: std
+; CHECK-NEXT: std
+; CHECK-NEXT: jl .L{{.*}}
+; CHECK: br %r14
+entry:
+  %val1 = load fp128 *%ptr1
+  %val2 = load fp128 *%ptr2
+  %div = fdiv fp128 %val1, %val2
+  store fp128 %div, fp128 *%ptr1
+  %mul = fmul fp128 %val1, %val2
+  store fp128 %mul, fp128 *%ptr2
+  %cmp = fcmp olt fp128 %val1, 0xL00000000000000000000000000000000
+  br i1 %cmp, label %exit, label %store
+
+store:
+  call void asm sideeffect "blah", ""()
+  br label %exit
+
+exit:
+  ret void
+}
+
+; Test a case where it is the source rather than destination of LER that
+; we need.
+define float @f15(float %val, float %dummy, float *%dest) {
+; CHECK-LABEL: f15:
+; CHECK: ltebr %f2, %f0
+; CHECK-NEXT: #APP
+; CHECK-NEXT: blah %f2
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jl .L{{.*}}
+; CHECK: br %r14
+entry:
+  call void asm sideeffect "blah $0", "{f2}"(float %val)
+  %cmp = fcmp olt float %val, 0.0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store float %val, float *%dest
+  br label %exit
+
+exit:
+  ret float %val
+}
+
+; Test a case where it is the source rather than destination of LDR that
+; we need.
+define double @f16(double %val, double %dummy, double *%dest) {
+; CHECK-LABEL: f16:
+; CHECK: ltdbr %f2, %f0
+; CHECK-NEXT: #APP
+; CHECK-NEXT: blah %f2
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jl .L{{.*}}
+; CHECK: br %r14
+entry:
+  call void asm sideeffect "blah $0", "{f2}"(double %val)
+  %cmp = fcmp olt double %val, 0.0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store double %val, double *%dest
+  br label %exit
+
+exit:
+  ret double %val
+}
diff --git a/test/CodeGen/SystemZ/fp-const-01.ll b/test/CodeGen/SystemZ/fp-const-01.ll
index 65209d6..3a4ddf0 100644
--- a/test/CodeGen/SystemZ/fp-const-01.ll
+++ b/test/CodeGen/SystemZ/fp-const-01.ll
@@ -4,7 +4,7 @@
 
 ; Test f32.
 define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lzer %f0
 ; CHECK: br %r14
   ret float 0.0
@@ -12,7 +12,7 @@ define float @f1() {
 
 ; Test f64.
 define double @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lzdr %f0
 ; CHECK: br %r14
   ret double 0.0
@@ -20,7 +20,7 @@ define double @f2() {
 
 ; Test f128.
 define void @f3(fp128 *%x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lzxr %f0
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
diff --git a/test/CodeGen/SystemZ/fp-const-02.ll b/test/CodeGen/SystemZ/fp-const-02.ll
index 2dedf54..96f8578 100644
--- a/test/CodeGen/SystemZ/fp-const-02.ll
+++ b/test/CodeGen/SystemZ/fp-const-02.ll
@@ -4,7 +4,7 @@
 
 ; Test f32.
 define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lzer [[REGISTER:%f[0-5]+]]
 ; CHECK: lcebr %f0, [[REGISTER]]
 ; CHECK: br %r14
@@ -13,7 +13,7 @@ define float @f1() {
 
 ; Test f64.
 define double @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lzdr [[REGISTER:%f[0-5]+]]
 ; CHECK: lcdbr %f0, [[REGISTER]]
 ; CHECK: br %r14
@@ -22,7 +22,7 @@ define double @f2() {
 
 ; Test f128.
 define void @f3(fp128 *%x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lzxr [[REGISTER:%f[0-5]+]]
 ; CHECK: lcxbr %f0, [[REGISTER]]
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-const-03.ll b/test/CodeGen/SystemZ/fp-const-03.ll
index 4c287e4..b2ae94d 100644
--- a/test/CodeGen/SystemZ/fp-const-03.ll
+++ b/test/CodeGen/SystemZ/fp-const-03.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]]], {{.*}}
 ; CHECK: le %f0, 0([[REGISTER]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-const-04.ll b/test/CodeGen/SystemZ/fp-const-04.ll
index 847c380..d552688 100644
--- a/test/CodeGen/SystemZ/fp-const-04.ll
+++ b/test/CodeGen/SystemZ/fp-const-04.ll
@@ -5,7 +5,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define double @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]]], {{.*}}
 ; CHECK: ldeb %f0, 0([[REGISTER]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-const-05.ll b/test/CodeGen/SystemZ/fp-const-05.ll
index 48f84ce..d81e3db 100644
--- a/test/CodeGen/SystemZ/fp-const-05.ll
+++ b/test/CodeGen/SystemZ/fp-const-05.ll
@@ -5,7 +5,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: lxeb %f0, 0([[REGISTER]])
 ; CHECK: std %f0, 0(%r2)
diff --git a/test/CodeGen/SystemZ/fp-const-06.ll b/test/CodeGen/SystemZ/fp-const-06.ll
index 1da3d5e..088810b 100644
--- a/test/CodeGen/SystemZ/fp-const-06.ll
+++ b/test/CodeGen/SystemZ/fp-const-06.ll
@@ -4,7 +4,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define double @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: ld %f0, 0([[REGISTER]])
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-const-07.ll b/test/CodeGen/SystemZ/fp-const-07.ll
index 5a10845..87e8f68 100644
--- a/test/CodeGen/SystemZ/fp-const-07.ll
+++ b/test/CodeGen/SystemZ/fp-const-07.ll
@@ -5,7 +5,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: lxdb %f0, 0([[REGISTER]])
 ; CHECK: std %f0, 0(%r2)
diff --git a/test/CodeGen/SystemZ/fp-const-08.ll b/test/CodeGen/SystemZ/fp-const-08.ll
index 6a8a1ab..8845adb 100644
--- a/test/CodeGen/SystemZ/fp-const-08.ll
+++ b/test/CodeGen/SystemZ/fp-const-08.ll
@@ -6,7 +6,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: ld %f0, 0([[REGISTER]])
 ; CHECK: ld %f2, 8([[REGISTER]])
diff --git a/test/CodeGen/SystemZ/fp-const-09.ll b/test/CodeGen/SystemZ/fp-const-09.ll
index 435dcba..0c7d726 100644
--- a/test/CodeGen/SystemZ/fp-const-09.ll
+++ b/test/CodeGen/SystemZ/fp-const-09.ll
@@ -5,7 +5,7 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
 
 define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
 ; CHECK: ld %f0, 0([[REGISTER]])
 ; CHECK: ld %f2, 8([[REGISTER]])
diff --git a/test/CodeGen/SystemZ/fp-conv-01.ll b/test/CodeGen/SystemZ/fp-conv-01.ll
index 6c8ef48..49ed43b 100644
--- a/test/CodeGen/SystemZ/fp-conv-01.ll
+++ b/test/CodeGen/SystemZ/fp-conv-01.ll
@@ -4,7 +4,7 @@
 
 ; Test f64->f32.
 define float @f1(double %d1, double %d2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ledbr %f0, %f2
 ; CHECK: br %r14
   %res = fptrunc double %d2 to float
@@ -13,7 +13,7 @@ define float @f1(double %d1, double %d2) {
 
 ; Test f128->f32.
 define float @f2(fp128 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lexbr %f0, %f0
 ; CHECK: br %r14
   %val = load fp128 *%ptr
@@ -24,7 +24,7 @@ define float @f2(fp128 *%ptr) {
 ; Make sure that we don't use %f0 as the destination of LEXBR when %f2
 ; is still live.
 define void @f3(float *%dst, fp128 *%ptr, float %d1, float %d2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lexbr %f1, %f1
 ; CHECK: aebr %f1, %f2
 ; CHECK: ste %f1, 0(%r2)
@@ -38,7 +38,7 @@ define void @f3(float *%dst, fp128 *%ptr, float %d1, float %d2) {
 
 ; Test f128->f64.
 define double @f4(fp128 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldxbr %f0, %f0
 ; CHECK: br %r14
   %val = load fp128 *%ptr
@@ -48,7 +48,7 @@ define double @f4(fp128 *%ptr) {
 
 ; Like f3, but for f128->f64.
 define void @f5(double *%dst, fp128 *%ptr, double %d1, double %d2) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldxbr %f1, %f1
 ; CHECK: adbr %f1, %f2
 ; CHECK: std %f1, 0(%r2)
diff --git a/test/CodeGen/SystemZ/fp-conv-02.ll b/test/CodeGen/SystemZ/fp-conv-02.ll
index f284e1d..93fb7c8 100644
--- a/test/CodeGen/SystemZ/fp-conv-02.ll
+++ b/test/CodeGen/SystemZ/fp-conv-02.ll
@@ -4,7 +4,7 @@
 
 ; Check register extension.
 define double @f1(float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldebr %f0, %f0
 ; CHECK: br %r14
   %res = fpext float %val to double
@@ -13,7 +13,7 @@ define double @f1(float %val) {
 
 ; Check the low end of the LDEB range.
 define double @f2(float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldeb %f0, 0(%r2)
 ; CHECK: br %r14
   %val = load float *%ptr
@@ -23,7 +23,7 @@ define double @f2(float *%ptr) {
 
 ; Check the high end of the aligned LDEB range.
 define double @f3(float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ldeb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -35,7 +35,7 @@ define double @f3(float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: ldeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -47,7 +47,7 @@ define double @f4(float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: ldeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -59,7 +59,7 @@ define double @f5(float *%base) {
 
 ; Check that LDEB allows indices.
 define double @f6(float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: ldeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -69,3 +69,84 @@ define double @f6(float *%base, i64 %index) {
   %res = fpext float %val to double
   ret double %res
 }
+
+; Test a case where we spill the source of at least one LDEBR.  We want
+; to use LDEB if possible.
+define void @f7(double *%ptr1, float *%ptr2) {
+; CHECK-LABEL: f7:
+; CHECK: ldeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %val0 = load volatile float *%ptr2
+  %val1 = load volatile float *%ptr2
+  %val2 = load volatile float *%ptr2
+  %val3 = load volatile float *%ptr2
+  %val4 = load volatile float *%ptr2
+  %val5 = load volatile float *%ptr2
+  %val6 = load volatile float *%ptr2
+  %val7 = load volatile float *%ptr2
+  %val8 = load volatile float *%ptr2
+  %val9 = load volatile float *%ptr2
+  %val10 = load volatile float *%ptr2
+  %val11 = load volatile float *%ptr2
+  %val12 = load volatile float *%ptr2
+  %val13 = load volatile float *%ptr2
+  %val14 = load volatile float *%ptr2
+  %val15 = load volatile float *%ptr2
+  %val16 = load volatile float *%ptr2
+
+  %ext0 = fpext float %val0 to double
+  %ext1 = fpext float %val1 to double
+  %ext2 = fpext float %val2 to double
+  %ext3 = fpext float %val3 to double
+  %ext4 = fpext float %val4 to double
+  %ext5 = fpext float %val5 to double
+  %ext6 = fpext float %val6 to double
+  %ext7 = fpext float %val7 to double
+  %ext8 = fpext float %val8 to double
+  %ext9 = fpext float %val9 to double
+  %ext10 = fpext float %val10 to double
+  %ext11 = fpext float %val11 to double
+  %ext12 = fpext float %val12 to double
+  %ext13 = fpext float %val13 to double
+  %ext14 = fpext float %val14 to double
+  %ext15 = fpext float %val15 to double
+  %ext16 = fpext float %val16 to double
+
+  store volatile float %val0, float *%ptr2
+  store volatile float %val1, float *%ptr2
+  store volatile float %val2, float *%ptr2
+  store volatile float %val3, float *%ptr2
+  store volatile float %val4, float *%ptr2
+  store volatile float %val5, float *%ptr2
+  store volatile float %val6, float *%ptr2
+  store volatile float %val7, float *%ptr2
+  store volatile float %val8, float *%ptr2
+  store volatile float %val9, float *%ptr2
+  store volatile float %val10, float *%ptr2
+  store volatile float %val11, float *%ptr2
+  store volatile float %val12, float *%ptr2
+  store volatile float %val13, float *%ptr2
+  store volatile float %val14, float *%ptr2
+  store volatile float %val15, float *%ptr2
+  store volatile float %val16, float *%ptr2
+
+  store volatile double %ext0, double *%ptr1
+  store volatile double %ext1, double *%ptr1
+  store volatile double %ext2, double *%ptr1
+  store volatile double %ext3, double *%ptr1
+  store volatile double %ext4, double *%ptr1
+  store volatile double %ext5, double *%ptr1
+  store volatile double %ext6, double *%ptr1
+  store volatile double %ext7, double *%ptr1
+  store volatile double %ext8, double *%ptr1
+  store volatile double %ext9, double *%ptr1
+  store volatile double %ext10, double *%ptr1
+  store volatile double %ext11, double *%ptr1
+  store volatile double %ext12, double *%ptr1
+  store volatile double %ext13, double *%ptr1
+  store volatile double %ext14, double *%ptr1
+  store volatile double %ext15, double *%ptr1
+  store volatile double %ext16, double *%ptr1
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/fp-conv-03.ll b/test/CodeGen/SystemZ/fp-conv-03.ll
index 703a141..d42ce66 100644
--- a/test/CodeGen/SystemZ/fp-conv-03.ll
+++ b/test/CodeGen/SystemZ/fp-conv-03.ll
@@ -4,7 +4,7 @@
 
 ; Check register extension.
 define void @f1(fp128 *%dst, float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -16,7 +16,7 @@ define void @f1(fp128 *%dst, float %val) {
 
 ; Check the low end of the LXEB range.
 define void @f2(fp128 *%dst, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lxeb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -29,7 +29,7 @@ define void @f2(fp128 *%dst, float *%ptr) {
 
 ; Check the high end of the aligned LXEB range.
 define void @f3(fp128 *%dst, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lxeb %f0, 4092(%r3)
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -44,7 +44,7 @@ define void @f3(fp128 *%dst, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f4(fp128 *%dst, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r3, 4096
 ; CHECK: lxeb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -59,7 +59,7 @@ define void @f4(fp128 *%dst, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f5(fp128 *%dst, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r3, -4
 ; CHECK: lxeb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -74,7 +74,7 @@ define void @f5(fp128 *%dst, float *%base) {
 
 ; Check that LXEB allows indices.
 define void @f6(fp128 *%dst, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r4, 2
 ; CHECK: lxeb %f0, 400(%r1,%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -87,3 +87,84 @@ define void @f6(fp128 *%dst, float *%base, i64 %index) {
   store fp128 %res, fp128 *%dst
   ret void
 }
+
+; Test a case where we spill the source of at least one LXEBR.  We want
+; to use LXEB if possible.
+define void @f7(fp128 *%ptr1, float *%ptr2) {
+; CHECK-LABEL: f7:
+; CHECK: lxeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %val0 = load volatile float *%ptr2
+  %val1 = load volatile float *%ptr2
+  %val2 = load volatile float *%ptr2
+  %val3 = load volatile float *%ptr2
+  %val4 = load volatile float *%ptr2
+  %val5 = load volatile float *%ptr2
+  %val6 = load volatile float *%ptr2
+  %val7 = load volatile float *%ptr2
+  %val8 = load volatile float *%ptr2
+  %val9 = load volatile float *%ptr2
+  %val10 = load volatile float *%ptr2
+  %val11 = load volatile float *%ptr2
+  %val12 = load volatile float *%ptr2
+  %val13 = load volatile float *%ptr2
+  %val14 = load volatile float *%ptr2
+  %val15 = load volatile float *%ptr2
+  %val16 = load volatile float *%ptr2
+
+  %ext0 = fpext float %val0 to fp128
+  %ext1 = fpext float %val1 to fp128
+  %ext2 = fpext float %val2 to fp128
+  %ext3 = fpext float %val3 to fp128
+  %ext4 = fpext float %val4 to fp128
+  %ext5 = fpext float %val5 to fp128
+  %ext6 = fpext float %val6 to fp128
+  %ext7 = fpext float %val7 to fp128
+  %ext8 = fpext float %val8 to fp128
+  %ext9 = fpext float %val9 to fp128
+  %ext10 = fpext float %val10 to fp128
+  %ext11 = fpext float %val11 to fp128
+  %ext12 = fpext float %val12 to fp128
+  %ext13 = fpext float %val13 to fp128
+  %ext14 = fpext float %val14 to fp128
+  %ext15 = fpext float %val15 to fp128
+  %ext16 = fpext float %val16 to fp128
+
+  store volatile float %val0, float *%ptr2
+  store volatile float %val1, float *%ptr2
+  store volatile float %val2, float *%ptr2
+  store volatile float %val3, float *%ptr2
+  store volatile float %val4, float *%ptr2
+  store volatile float %val5, float *%ptr2
+  store volatile float %val6, float *%ptr2
+  store volatile float %val7, float *%ptr2
+  store volatile float %val8, float *%ptr2
+  store volatile float %val9, float *%ptr2
+  store volatile float %val10, float *%ptr2
+  store volatile float %val11, float *%ptr2
+  store volatile float %val12, float *%ptr2
+  store volatile float %val13, float *%ptr2
+  store volatile float %val14, float *%ptr2
+  store volatile float %val15, float *%ptr2
+  store volatile float %val16, float *%ptr2
+
+  store volatile fp128 %ext0, fp128 *%ptr1
+  store volatile fp128 %ext1, fp128 *%ptr1
+  store volatile fp128 %ext2, fp128 *%ptr1
+  store volatile fp128 %ext3, fp128 *%ptr1
+  store volatile fp128 %ext4, fp128 *%ptr1
+  store volatile fp128 %ext5, fp128 *%ptr1
+  store volatile fp128 %ext6, fp128 *%ptr1
+  store volatile fp128 %ext7, fp128 *%ptr1
+  store volatile fp128 %ext8, fp128 *%ptr1
+  store volatile fp128 %ext9, fp128 *%ptr1
+  store volatile fp128 %ext10, fp128 *%ptr1
+  store volatile fp128 %ext11, fp128 *%ptr1
+  store volatile fp128 %ext12, fp128 *%ptr1
+  store volatile fp128 %ext13, fp128 *%ptr1
+  store volatile fp128 %ext14, fp128 *%ptr1
+  store volatile fp128 %ext15, fp128 *%ptr1
+  store volatile fp128 %ext16, fp128 *%ptr1
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/fp-conv-04.ll b/test/CodeGen/SystemZ/fp-conv-04.ll
index b7b5166..518d6c2 100644
--- a/test/CodeGen/SystemZ/fp-conv-04.ll
+++ b/test/CodeGen/SystemZ/fp-conv-04.ll
@@ -4,7 +4,7 @@
 
 ; Check register extension.
 define void @f1(fp128 *%dst, double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxdbr %f0, %f0
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -16,7 +16,7 @@ define void @f1(fp128 *%dst, double %val) {
 
 ; Check the low end of the LXDB range.
 define void @f2(fp128 *%dst, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lxdb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -29,7 +29,7 @@ define void @f2(fp128 *%dst, double *%ptr) {
 
 ; Check the high end of the aligned LXDB range.
 define void @f3(fp128 *%dst, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lxdb %f0, 4088(%r3)
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -44,7 +44,7 @@ define void @f3(fp128 *%dst, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f4(fp128 *%dst, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r3, 4096
 ; CHECK: lxdb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -59,7 +59,7 @@ define void @f4(fp128 *%dst, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f5(fp128 *%dst, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r3, -8
 ; CHECK: lxdb %f0, 0(%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -74,7 +74,7 @@ define void @f5(fp128 *%dst, double *%base) {
 
 ; Check that LXDB allows indices.
 define void @f6(fp128 *%dst, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r4, 3
 ; CHECK: lxdb %f0, 800(%r1,%r3)
 ; CHECK: std %f0, 0(%r2)
@@ -87,3 +87,84 @@ define void @f6(fp128 *%dst, double *%base, i64 %index) {
   store fp128 %res, fp128 *%dst
   ret void
 }
+
+; Test a case where we spill the source of at least one LXDBR.  We want
+; to use LXDB if possible.
+define void @f7(fp128 *%ptr1, double *%ptr2) {
+; CHECK-LABEL: f7:
+; CHECK: lxdb {{%f[0-9]+}}, 160(%r15)
+; CHECK: br %r14
+  %val0 = load volatile double *%ptr2
+  %val1 = load volatile double *%ptr2
+  %val2 = load volatile double *%ptr2
+  %val3 = load volatile double *%ptr2
+  %val4 = load volatile double *%ptr2
+  %val5 = load volatile double *%ptr2
+  %val6 = load volatile double *%ptr2
+  %val7 = load volatile double *%ptr2
+  %val8 = load volatile double *%ptr2
+  %val9 = load volatile double *%ptr2
+  %val10 = load volatile double *%ptr2
+  %val11 = load volatile double *%ptr2
+  %val12 = load volatile double *%ptr2
+  %val13 = load volatile double *%ptr2
+  %val14 = load volatile double *%ptr2
+  %val15 = load volatile double *%ptr2
+  %val16 = load volatile double *%ptr2
+
+  %ext0 = fpext double %val0 to fp128
+  %ext1 = fpext double %val1 to fp128
+  %ext2 = fpext double %val2 to fp128
+  %ext3 = fpext double %val3 to fp128
+  %ext4 = fpext double %val4 to fp128
+  %ext5 = fpext double %val5 to fp128
+  %ext6 = fpext double %val6 to fp128
+  %ext7 = fpext double %val7 to fp128
+  %ext8 = fpext double %val8 to fp128
+  %ext9 = fpext double %val9 to fp128
+  %ext10 = fpext double %val10 to fp128
+  %ext11 = fpext double %val11 to fp128
+  %ext12 = fpext double %val12 to fp128
+  %ext13 = fpext double %val13 to fp128
+  %ext14 = fpext double %val14 to fp128
+  %ext15 = fpext double %val15 to fp128
+  %ext16 = fpext double %val16 to fp128
+
+  store volatile double %val0, double *%ptr2
+  store volatile double %val1, double *%ptr2
+  store volatile double %val2, double *%ptr2
+  store volatile double %val3, double *%ptr2
+  store volatile double %val4, double *%ptr2
+  store volatile double %val5, double *%ptr2
+  store volatile double %val6, double *%ptr2
+  store volatile double %val7, double *%ptr2
+  store volatile double %val8, double *%ptr2
+  store volatile double %val9, double *%ptr2
+  store volatile double %val10, double *%ptr2
+  store volatile double %val11, double *%ptr2
+  store volatile double %val12, double *%ptr2
+  store volatile double %val13, double *%ptr2
+  store volatile double %val14, double *%ptr2
+  store volatile double %val15, double *%ptr2
+  store volatile double %val16, double *%ptr2
+
+  store volatile fp128 %ext0, fp128 *%ptr1
+  store volatile fp128 %ext1, fp128 *%ptr1
+  store volatile fp128 %ext2, fp128 *%ptr1
+  store volatile fp128 %ext3, fp128 *%ptr1
+  store volatile fp128 %ext4, fp128 *%ptr1
+  store volatile fp128 %ext5, fp128 *%ptr1
+  store volatile fp128 %ext6, fp128 *%ptr1
+  store volatile fp128 %ext7, fp128 *%ptr1
+  store volatile fp128 %ext8, fp128 *%ptr1
+  store volatile fp128 %ext9, fp128 *%ptr1
+  store volatile fp128 %ext10, fp128 *%ptr1
+  store volatile fp128 %ext11, fp128 *%ptr1
+  store volatile fp128 %ext12, fp128 *%ptr1
+  store volatile fp128 %ext13, fp128 *%ptr1
+  store volatile fp128 %ext14, fp128 *%ptr1
+  store volatile fp128 %ext15, fp128 *%ptr1
+  store volatile fp128 %ext16, fp128 *%ptr1
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/fp-conv-05.ll b/test/CodeGen/SystemZ/fp-conv-05.ll
index 2d88732..deeffbf 100644
--- a/test/CodeGen/SystemZ/fp-conv-05.ll
+++ b/test/CodeGen/SystemZ/fp-conv-05.ll
@@ -4,7 +4,7 @@
 
 ; Check i32->f32.
 define float @f1(i32 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cefbr %f0, %r2
 ; CHECK: br %r14
   %conv = sitofp i32 %i to float
@@ -13,7 +13,7 @@ define float @f1(i32 %i) {
 
 ; Check i32->f64.
 define double @f2(i32 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cdfbr %f0, %r2
 ; CHECK: br %r14
   %conv = sitofp i32 %i to double
@@ -22,7 +22,7 @@ define double @f2(i32 %i) {
 
 ; Check i32->f128.
 define void @f3(i32 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cxfbr %f0, %r2
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
diff --git a/test/CodeGen/SystemZ/fp-conv-06.ll b/test/CodeGen/SystemZ/fp-conv-06.ll
index 1b39b67..466c145 100644
--- a/test/CodeGen/SystemZ/fp-conv-06.ll
+++ b/test/CodeGen/SystemZ/fp-conv-06.ll
@@ -5,7 +5,7 @@
 ; Check i32->f32.  There is no native instruction, so we must promote
 ; to i64 first.
 define float @f1(i32 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
 ; CHECK: cegbr %f0, [[REGISTER]]
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define float @f1(i32 %i) {
 
 ; Check i32->f64.
 define double @f2(i32 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
 ; CHECK: cdgbr %f0, [[REGISTER]]
 ; CHECK: br %r14
@@ -25,7 +25,7 @@ define double @f2(i32 %i) {
 
 ; Check i32->f128.
 define void @f3(i32 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
 ; CHECK: cxgbr %f0, [[REGISTER]]
 ; CHECK: std %f0, 0(%r3)
diff --git a/test/CodeGen/SystemZ/fp-conv-07.ll b/test/CodeGen/SystemZ/fp-conv-07.ll
index 0ebbd37..aba5c4c 100644
--- a/test/CodeGen/SystemZ/fp-conv-07.ll
+++ b/test/CodeGen/SystemZ/fp-conv-07.ll
@@ -4,7 +4,7 @@
 
 ; Test i64->f32.
 define float @f1(i64 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cegbr %f0, %r2
 ; CHECK: br %r14
   %conv = sitofp i64 %i to float
@@ -13,7 +13,7 @@ define float @f1(i64 %i) {
 
 ; Test i64->f64.
 define double @f2(i64 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cdgbr %f0, %r2
 ; CHECK: br %r14
   %conv = sitofp i64 %i to double
@@ -22,7 +22,7 @@ define double @f2(i64 %i) {
 
 ; Test i64->f128.
 define void @f3(i64 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cxgbr %f0, %r2
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
diff --git a/test/CodeGen/SystemZ/fp-conv-08.ll b/test/CodeGen/SystemZ/fp-conv-08.ll
index 20c4e30..69b2d13 100644
--- a/test/CodeGen/SystemZ/fp-conv-08.ll
+++ b/test/CodeGen/SystemZ/fp-conv-08.ll
@@ -5,7 +5,7 @@
 ; Test i64->f32.  There's no native support for unsigned i64-to-fp conversions,
 ; but we should be able to implement them using signed i64-to-fp conversions.
 define float @f1(i64 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cegbr
 ; CHECK: aebr
 ; CHECK: br %r14
@@ -15,9 +15,9 @@ define float @f1(i64 %i) {
 
 ; Test i64->f64.
 define double @f2(i64 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldgr
-; CHECL: adbr
+; CHECK: adbr
 ; CHECK: br %r14
   %conv = uitofp i64 %i to double
   ret double %conv
@@ -25,7 +25,7 @@ define double @f2(i64 %i) {
 
 ; Test i64->f128.
 define void @f3(i64 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cxgbr
 ; CHECK: axbr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-conv-09.ll b/test/CodeGen/SystemZ/fp-conv-09.ll
index e3c0352..6aee736 100644
--- a/test/CodeGen/SystemZ/fp-conv-09.ll
+++ b/test/CodeGen/SystemZ/fp-conv-09.ll
@@ -4,7 +4,7 @@
 
 ; Test f32->i32.
 define i32 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cfebr %r2, 5, %f0
 ; CHECK: br %r14
   %conv = fptosi float %f to i32
@@ -13,7 +13,7 @@ define i32 @f1(float %f) {
 
 ; Test f64->i32.
 define i32 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cfdbr %r2, 5, %f0
 ; CHECK: br %r14
   %conv = fptosi double %f to i32
@@ -22,7 +22,7 @@ define i32 @f2(double %f) {
 
 ; Test f128->i32.
 define i32 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: ld %f2, 8(%r2)
 ; CHECK: cfxbr %r2, 5, %f0
diff --git a/test/CodeGen/SystemZ/fp-conv-10.ll b/test/CodeGen/SystemZ/fp-conv-10.ll
index bb8878b..723d19d 100644
--- a/test/CodeGen/SystemZ/fp-conv-10.ll
+++ b/test/CodeGen/SystemZ/fp-conv-10.ll
@@ -9,7 +9,7 @@
 
 ; Test f32->i32.
 define i32 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cebr
 ; CHECK: sebr
 ; CHECK: cfebr
@@ -21,7 +21,7 @@ define i32 @f1(float %f) {
 
 ; Test f64->i32.
 define i32 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cdbr
 ; CHECK: sdbr
 ; CHECK: cfdbr
@@ -33,7 +33,7 @@ define i32 @f2(double %f) {
 
 ; Test f128->i32.
 define i32 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cxbr
 ; CHECK: sxbr
 ; CHECK: cfxbr
diff --git a/test/CodeGen/SystemZ/fp-conv-11.ll b/test/CodeGen/SystemZ/fp-conv-11.ll
index 2a36cb9..46f4cb3 100644
--- a/test/CodeGen/SystemZ/fp-conv-11.ll
+++ b/test/CodeGen/SystemZ/fp-conv-11.ll
@@ -4,7 +4,7 @@
 
 ; Test f32->i64.
 define i64 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgebr %r2, 5, %f0
 ; CHECK: br %r14
   %conv = fptosi float %f to i64
@@ -13,7 +13,7 @@ define i64 @f1(float %f) {
 
 ; Test f64->i64.
 define i64 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cgdbr %r2, 5, %f0
 ; CHECK: br %r14
   %conv = fptosi double %f to i64
@@ -22,7 +22,7 @@ define i64 @f2(double %f) {
 
 ; Test f128->i64.
 define i64 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: ld %f2, 8(%r2)
 ; CHECK: cgxbr %r2, 5, %f0
diff --git a/test/CodeGen/SystemZ/fp-conv-12.ll b/test/CodeGen/SystemZ/fp-conv-12.ll
index 4445b14..6cc343a 100644
--- a/test/CodeGen/SystemZ/fp-conv-12.ll
+++ b/test/CodeGen/SystemZ/fp-conv-12.ll
@@ -8,7 +8,7 @@
 
 ; Test f32->i64.
 define i64 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cebr
 ; CHECK: sebr
 ; CHECK: cgebr
@@ -20,7 +20,7 @@ define i64 @f1(float %f) {
 
 ; Test f64->i64.
 define i64 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cdbr
 ; CHECK: sdbr
 ; CHECK: cgdbr
@@ -32,7 +32,7 @@ define i64 @f2(double %f) {
 
 ; Test f128->i64.
 define i64 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cxbr
 ; CHECK: sxbr
 ; CHECK: cgxbr
diff --git a/test/CodeGen/SystemZ/fp-copysign-01.ll b/test/CodeGen/SystemZ/fp-copysign-01.ll
index 458d475..50177e5 100644
--- a/test/CodeGen/SystemZ/fp-copysign-01.ll
+++ b/test/CodeGen/SystemZ/fp-copysign-01.ll
@@ -9,7 +9,7 @@ declare fp128 @copysignl(fp128, fp128) readnone
 
 ; Test f32 copies in which the sign comes from an f32.
 define float @f1(float %a, float %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %f2
 ; CHECK: cpsdr %f0, %f0, %f2
 ; CHECK: br %r14
@@ -19,7 +19,7 @@ define float @f1(float %a, float %b) {
 
 ; Test f32 copies in which the sign comes from an f64.
 define float @f2(float %a, double %bd) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %f2
 ; CHECK: cpsdr %f0, %f0, %f2
 ; CHECK: br %r14
@@ -30,7 +30,7 @@ define float @f2(float %a, double %bd) {
 
 ; Test f32 copies in which the sign comes from an f128.
 define float @f3(float %a, fp128 *%bptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r2)
 ; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2)
 ; CHECK: cpsdr %f0, %f0, [[BHIGH]]
@@ -43,7 +43,7 @@ define float @f3(float %a, fp128 *%bptr) {
 
 ; Test f64 copies in which the sign comes from an f32.
 define double @f4(double %a, float %bf) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %f2
 ; CHECK: cpsdr %f0, %f0, %f2
 ; CHECK: br %r14
@@ -54,7 +54,7 @@ define double @f4(double %a, float %bf) {
 
 ; Test f64 copies in which the sign comes from an f64.
 define double @f5(double %a, double %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %f2
 ; CHECK: cpsdr %f0, %f0, %f2
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ define double @f5(double %a, double %b) {
 
 ; Test f64 copies in which the sign comes from an f128.
 define double @f6(double %a, fp128 *%bptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r2)
 ; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2)
 ; CHECK: cpsdr %f0, %f0, [[BHIGH]]
@@ -79,7 +79,7 @@ define double @f6(double %a, fp128 *%bptr) {
 ; need any register shuffling here; %a should be tied to %c, with CPSDR
 ; just changing the high register.
 define void @f7(fp128 *%cptr, fp128 *%aptr, float %bf) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3)
 ; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3)
 ; CHECK: cpsdr [[AHIGH]], [[AHIGH]], %f0
@@ -95,7 +95,7 @@ define void @f7(fp128 *%cptr, fp128 *%aptr, float %bf) {
 
 ; As above, but the sign comes from an f64.
 define void @f8(fp128 *%cptr, fp128 *%aptr, double %bd) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3)
 ; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3)
 ; CHECK: cpsdr [[AHIGH]], [[AHIGH]], %f0
@@ -112,7 +112,7 @@ define void @f8(fp128 *%cptr, fp128 *%aptr, double %bd) {
 ; As above, but the sign comes from an f128.  Don't require the low part
 ; of %b to be loaded, since it isn't used.
 define void @f9(fp128 *%cptr, fp128 *%aptr, fp128 *%bptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3)
 ; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3)
 ; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r4)
diff --git a/test/CodeGen/SystemZ/fp-div-01.ll b/test/CodeGen/SystemZ/fp-div-01.ll
index 080d45e..1b99463 100644
--- a/test/CodeGen/SystemZ/fp-div-01.ll
+++ b/test/CodeGen/SystemZ/fp-div-01.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare float @foo()
+
 ; Check register division.
 define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: debr %f0, %f2
 ; CHECK: br %r14
   %res = fdiv float %f1, %f2
@@ -13,7 +15,7 @@ define float @f1(float %f1, float %f2) {
 
 ; Check the low end of the DEB range.
 define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: deb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load float *%ptr
@@ -23,7 +25,7 @@ define float @f2(float %f1, float *%ptr) {
 
 ; Check the high end of the aligned DEB range.
 define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: deb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -35,7 +37,7 @@ define float @f3(float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: deb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -47,7 +49,7 @@ define float @f4(float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: deb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -59,7 +61,7 @@ define float @f5(float %f1, float *%base) {
 
 ; Check that DEB allows indices.
 define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: deb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -69,3 +71,49 @@ define float @f6(float %f1, float *%base, i64 %index) {
   %res = fdiv float %f1, %f2
   ret float %res
 }
+
+; Check that divisions of spilled values can use DEB rather than DEBR.
+define float @f7(float *%ptr0) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: deb %f0, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr float *%ptr0, i64 2
+  %ptr2 = getelementptr float *%ptr0, i64 4
+  %ptr3 = getelementptr float *%ptr0, i64 6
+  %ptr4 = getelementptr float *%ptr0, i64 8
+  %ptr5 = getelementptr float *%ptr0, i64 10
+  %ptr6 = getelementptr float *%ptr0, i64 12
+  %ptr7 = getelementptr float *%ptr0, i64 14
+  %ptr8 = getelementptr float *%ptr0, i64 16
+  %ptr9 = getelementptr float *%ptr0, i64 18
+  %ptr10 = getelementptr float *%ptr0, i64 20
+
+  %val0 = load float *%ptr0
+  %val1 = load float *%ptr1
+  %val2 = load float *%ptr2
+  %val3 = load float *%ptr3
+  %val4 = load float *%ptr4
+  %val5 = load float *%ptr5
+  %val6 = load float *%ptr6
+  %val7 = load float *%ptr7
+  %val8 = load float *%ptr8
+  %val9 = load float *%ptr9
+  %val10 = load float *%ptr10
+
+  %ret = call float @foo()
+
+  %div0 = fdiv float %ret, %val0
+  %div1 = fdiv float %div0, %val1
+  %div2 = fdiv float %div1, %val2
+  %div3 = fdiv float %div2, %val3
+  %div4 = fdiv float %div3, %val4
+  %div5 = fdiv float %div4, %val5
+  %div6 = fdiv float %div5, %val6
+  %div7 = fdiv float %div6, %val7
+  %div8 = fdiv float %div7, %val8
+  %div9 = fdiv float %div8, %val9
+  %div10 = fdiv float %div9, %val10
+
+  ret float %div10
+}
diff --git a/test/CodeGen/SystemZ/fp-div-02.ll b/test/CodeGen/SystemZ/fp-div-02.ll
index c5cae15..513664b 100644
--- a/test/CodeGen/SystemZ/fp-div-02.ll
+++ b/test/CodeGen/SystemZ/fp-div-02.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare double @foo()
+
 ; Check register division.
 define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ddbr %f0, %f2
 ; CHECK: br %r14
   %res = fdiv double %f1, %f2
@@ -13,7 +15,7 @@ define double @f1(double %f1, double %f2) {
 
 ; Check the low end of the DDB range.
 define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ddb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load double *%ptr
@@ -23,7 +25,7 @@ define double @f2(double %f1, double *%ptr) {
 
 ; Check the high end of the aligned DDB range.
 define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ddb %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%base, i64 511
@@ -35,7 +37,7 @@ define double @f3(double %f1, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: ddb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -47,7 +49,7 @@ define double @f4(double %f1, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: ddb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -59,7 +61,7 @@ define double @f5(double %f1, double *%base) {
 
 ; Check that DDB allows indices.
 define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: ddb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
@@ -69,3 +71,49 @@ define double @f6(double %f1, double *%base, i64 %index) {
   %res = fdiv double %f1, %f2
   ret double %res
 }
+
+; Check that divisions of spilled values can use DDB rather than DDBR.
+define double @f7(double *%ptr0) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: ddb %f0, 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr double *%ptr0, i64 2
+  %ptr2 = getelementptr double *%ptr0, i64 4
+  %ptr3 = getelementptr double *%ptr0, i64 6
+  %ptr4 = getelementptr double *%ptr0, i64 8
+  %ptr5 = getelementptr double *%ptr0, i64 10
+  %ptr6 = getelementptr double *%ptr0, i64 12
+  %ptr7 = getelementptr double *%ptr0, i64 14
+  %ptr8 = getelementptr double *%ptr0, i64 16
+  %ptr9 = getelementptr double *%ptr0, i64 18
+  %ptr10 = getelementptr double *%ptr0, i64 20
+
+  %val0 = load double *%ptr0
+  %val1 = load double *%ptr1
+  %val2 = load double *%ptr2
+  %val3 = load double *%ptr3
+  %val4 = load double *%ptr4
+  %val5 = load double *%ptr5
+  %val6 = load double *%ptr6
+  %val7 = load double *%ptr7
+  %val8 = load double *%ptr8
+  %val9 = load double *%ptr9
+  %val10 = load double *%ptr10
+
+  %ret = call double @foo()
+
+  %div0 = fdiv double %ret, %val0
+  %div1 = fdiv double %div0, %val1
+  %div2 = fdiv double %div1, %val2
+  %div3 = fdiv double %div2, %val3
+  %div4 = fdiv double %div3, %val4
+  %div5 = fdiv double %div4, %val5
+  %div6 = fdiv double %div5, %val6
+  %div7 = fdiv double %div6, %val7
+  %div8 = fdiv double %div7, %val8
+  %div9 = fdiv double %div8, %val9
+  %div10 = fdiv double %div9, %val10
+
+  ret double %div10
+}
diff --git a/test/CodeGen/SystemZ/fp-div-03.ll b/test/CodeGen/SystemZ/fp-div-03.ll
index 18f2d74..079b349 100644
--- a/test/CodeGen/SystemZ/fp-div-03.ll
+++ b/test/CodeGen/SystemZ/fp-div-03.ll
@@ -4,7 +4,7 @@
 
 ; There is no memory form of 128-bit division.
 define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r2)
 ; CHECK: ld %f3, 8(%r2)
diff --git a/test/CodeGen/SystemZ/fp-move-01.ll b/test/CodeGen/SystemZ/fp-move-01.ll
index 73cd978..d16502f 100644
--- a/test/CodeGen/SystemZ/fp-move-01.ll
+++ b/test/CodeGen/SystemZ/fp-move-01.ll
@@ -4,14 +4,14 @@
 
 ; Test f32 moves.
 define float @f1(float %a, float %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ler %f0, %f2
   ret float %b
 }
 
 ; Test f64 moves.
 define double @f2(double %a, double %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldr %f0, %f2
   ret double %b
 }
@@ -19,7 +19,7 @@ define double @f2(double %a, double %b) {
 ; Test f128 moves.  Since f128s are passed by reference, we need to force
 ; a copy by other means.
 define void @f3(fp128 *%x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lxr
 ; CHECK: axbr
   %val = load volatile fp128 *%x
diff --git a/test/CodeGen/SystemZ/fp-move-02.ll b/test/CodeGen/SystemZ/fp-move-02.ll
index 9d87797..b4f0428 100644
--- a/test/CodeGen/SystemZ/fp-move-02.ll
+++ b/test/CodeGen/SystemZ/fp-move-02.ll
@@ -2,10 +2,15 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i64 @foo()
+declare double @bar()
+@dptr = external global double
+@iptr = external global i64
+
 ; Test 32-bit moves from GPRs to FPRs.  The GPR must be moved into the high
 ; 32 bits of the FPR.
 define float @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 32
 ; CHECK: ldgr %f0, [[REGISTER]]
   %res = bitcast i32 %a to float
@@ -15,8 +20,8 @@ define float @f1(i32 %a) {
 ; Like f1, but create a situation where the shift can be folded with
 ; surrounding code.
 define float @f2(i64 %big) {
-; CHECK: f2:
-; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 31
+; CHECK-LABEL: f2:
+; CHECK: risbg [[REGISTER:%r[0-5]]], %r2, 0, 159, 31
 ; CHECK: ldgr %f0, [[REGISTER]]
   %shift = lshr i64 %big, 1
   %a = trunc i64 %shift to i32
@@ -26,8 +31,8 @@ define float @f2(i64 %big) {
 
 ; Another example of the same thing.
 define float @f3(i64 %big) {
-; CHECK: f3:
-; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 2
+; CHECK-LABEL: f3:
+; CHECK: risbg [[REGISTER:%r[0-5]]], %r2, 0, 159, 2
 ; CHECK: ldgr %f0, [[REGISTER]]
   %shift = ashr i64 %big, 30
   %a = trunc i64 %shift to i32
@@ -37,7 +42,7 @@ define float @f3(i64 %big) {
 
 ; Like f1, but the value to transfer is already in the high 32 bits.
 define float @f4(i64 %big) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r2
 ; CHECK: nilf %r2, 0
 ; CHECK-NOT: %r2
@@ -50,7 +55,7 @@ define float @f4(i64 %big) {
 
 ; Test 64-bit moves from GPRs to FPRs.
 define double @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldgr %f0, %r2
   %res = bitcast i64 %a to double
   ret double %res
@@ -58,12 +63,13 @@ define double @f5(i64 %a) {
 
 ; Test 128-bit moves from GPRs to FPRs.  i128 isn't a legitimate type,
 ; so this goes through memory.
+; FIXME: it would be better to use one MVC here.
 define void @f6(fp128 *%a, i128 *%b) {
-; CHECK: f6:
-; CHECK: lg
+; CHECK-LABEL: f6:
 ; CHECK: lg
+; CHECK: mvc
 ; CHECK: stg
-; CHECK: stg
+; CHECK: br %r14
   %val = load i128 *%b
   %res = bitcast i128 %val to fp128
   store fp128 %res, fp128 *%a
@@ -73,7 +79,7 @@ define void @f6(fp128 *%a, i128 *%b) {
 ; Test 32-bit moves from FPRs to GPRs.  The high 32 bits of the FPR should
 ; be moved into the low 32 bits of the GPR.
 define i32 @f7(float %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgdr [[REGISTER:%r[0-5]]], %f0
 ; CHECK: srlg %r2, [[REGISTER]], 32
   %res = bitcast float %a to i32
@@ -82,7 +88,7 @@ define i32 @f7(float %a) {
 
 ; Test 64-bit moves from FPRs to GPRs.
 define i64 @f8(double %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lgdr %r2, %f0
   %res = bitcast double %a to i64
   ret i64 %res
@@ -90,7 +96,7 @@ define i64 @f8(double %a) {
 
 ; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6.
 define void @f9(fp128 *%a, i128 *%b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ld
 ; CHECK: ld
 ; CHECK: std
@@ -101,3 +107,286 @@ define void @f9(fp128 *%a, i128 *%b) {
   ret void
 }
 
+; Test cases where the destination of an LGDR needs to be spilled.
+; We shouldn't have any integer stack stores or floating-point loads.
+define void @f10(double %extra) {
+; CHECK-LABEL: f10:
+; CHECK: dptr
+; CHECK-NOT: stg {{.*}}(%r15)
+; CHECK: %loop
+; CHECK-NOT: ld {{.*}}(%r15)
+; CHECK: %exit
+; CHECK: br %r14
+entry:
+  %double0 = load volatile double *@dptr
+  %biased0 = fadd double %double0, %extra
+  %int0 = bitcast double %biased0 to i64
+  %double1 = load volatile double *@dptr
+  %biased1 = fadd double %double1, %extra
+  %int1 = bitcast double %biased1 to i64
+  %double2 = load volatile double *@dptr
+  %biased2 = fadd double %double2, %extra
+  %int2 = bitcast double %biased2 to i64
+  %double3 = load volatile double *@dptr
+  %biased3 = fadd double %double3, %extra
+  %int3 = bitcast double %biased3 to i64
+  %double4 = load volatile double *@dptr
+  %biased4 = fadd double %double4, %extra
+  %int4 = bitcast double %biased4 to i64
+  %double5 = load volatile double *@dptr
+  %biased5 = fadd double %double5, %extra
+  %int5 = bitcast double %biased5 to i64
+  %double6 = load volatile double *@dptr
+  %biased6 = fadd double %double6, %extra
+  %int6 = bitcast double %biased6 to i64
+  %double7 = load volatile double *@dptr
+  %biased7 = fadd double %double7, %extra
+  %int7 = bitcast double %biased7 to i64
+  %double8 = load volatile double *@dptr
+  %biased8 = fadd double %double8, %extra
+  %int8 = bitcast double %biased8 to i64
+  %double9 = load volatile double *@dptr
+  %biased9 = fadd double %double9, %extra
+  %int9 = bitcast double %biased9 to i64
+  br label %loop
+
+loop:
+  %start = call i64 @foo()
+  %or0 = or i64 %start, %int0
+  %or1 = or i64 %or0, %int1
+  %or2 = or i64 %or1, %int2
+  %or3 = or i64 %or2, %int3
+  %or4 = or i64 %or3, %int4
+  %or5 = or i64 %or4, %int5
+  %or6 = or i64 %or5, %int6
+  %or7 = or i64 %or6, %int7
+  %or8 = or i64 %or7, %int8
+  %or9 = or i64 %or8, %int9
+  store i64 %or9, i64 *@iptr
+  %cont = icmp ne i64 %start, 1
+  br i1 %cont, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+; ...likewise LDGR, with the requirements the other way around.
+define void @f11(i64 %mask) {
+; CHECK-LABEL: f11:
+; CHECK: iptr
+; CHECK-NOT: std {{.*}}(%r15)
+; CHECK: %loop
+; CHECK-NOT: lg {{.*}}(%r15)
+; CHECK: %exit
+; CHECK: br %r14
+entry:
+  %int0 = load volatile i64 *@iptr
+  %masked0 = and i64 %int0, %mask
+  %double0 = bitcast i64 %masked0 to double
+  %int1 = load volatile i64 *@iptr
+  %masked1 = and i64 %int1, %mask
+  %double1 = bitcast i64 %masked1 to double
+  %int2 = load volatile i64 *@iptr
+  %masked2 = and i64 %int2, %mask
+  %double2 = bitcast i64 %masked2 to double
+  %int3 = load volatile i64 *@iptr
+  %masked3 = and i64 %int3, %mask
+  %double3 = bitcast i64 %masked3 to double
+  %int4 = load volatile i64 *@iptr
+  %masked4 = and i64 %int4, %mask
+  %double4 = bitcast i64 %masked4 to double
+  %int5 = load volatile i64 *@iptr
+  %masked5 = and i64 %int5, %mask
+  %double5 = bitcast i64 %masked5 to double
+  %int6 = load volatile i64 *@iptr
+  %masked6 = and i64 %int6, %mask
+  %double6 = bitcast i64 %masked6 to double
+  %int7 = load volatile i64 *@iptr
+  %masked7 = and i64 %int7, %mask
+  %double7 = bitcast i64 %masked7 to double
+  %int8 = load volatile i64 *@iptr
+  %masked8 = and i64 %int8, %mask
+  %double8 = bitcast i64 %masked8 to double
+  %int9 = load volatile i64 *@iptr
+  %masked9 = and i64 %int9, %mask
+  %double9 = bitcast i64 %masked9 to double
+  br label %loop
+
+loop:
+  %start = call double @bar()
+  %add0 = fadd double %start, %double0
+  %add1 = fadd double %add0, %double1
+  %add2 = fadd double %add1, %double2
+  %add3 = fadd double %add2, %double3
+  %add4 = fadd double %add3, %double4
+  %add5 = fadd double %add4, %double5
+  %add6 = fadd double %add5, %double6
+  %add7 = fadd double %add6, %double7
+  %add8 = fadd double %add7, %double8
+  %add9 = fadd double %add8, %double9
+  store double %add9, double *@dptr
+  %cont = fcmp one double %start, 1.0
+  br i1 %cont, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+; Test cases where the source of an LDGR needs to be spilled.
+; We shouldn't have any integer stack stores or floating-point loads.
+define void @f12() {
+; CHECK-LABEL: f12:
+; CHECK: %loop
+; CHECK-NOT: std {{.*}}(%r15)
+; CHECK: %exit
+; CHECK: foo@PLT
+; CHECK-NOT: lg {{.*}}(%r15)
+; CHECK: foo@PLT
+; CHECK: br %r14
+entry:
+  br label %loop
+
+loop:
+  %int0 = phi i64 [ 0, %entry ], [ %add0, %loop ]
+  %int1 = phi i64 [ 0, %entry ], [ %add1, %loop ]
+  %int2 = phi i64 [ 0, %entry ], [ %add2, %loop ]
+  %int3 = phi i64 [ 0, %entry ], [ %add3, %loop ]
+  %int4 = phi i64 [ 0, %entry ], [ %add4, %loop ]
+  %int5 = phi i64 [ 0, %entry ], [ %add5, %loop ]
+  %int6 = phi i64 [ 0, %entry ], [ %add6, %loop ]
+  %int7 = phi i64 [ 0, %entry ], [ %add7, %loop ]
+  %int8 = phi i64 [ 0, %entry ], [ %add8, %loop ]
+  %int9 = phi i64 [ 0, %entry ], [ %add9, %loop ]
+
+  %bias = call i64 @foo()
+  %add0 = add i64 %int0, %bias
+  %add1 = add i64 %int1, %bias
+  %add2 = add i64 %int2, %bias
+  %add3 = add i64 %int3, %bias
+  %add4 = add i64 %int4, %bias
+  %add5 = add i64 %int5, %bias
+  %add6 = add i64 %int6, %bias
+  %add7 = add i64 %int7, %bias
+  %add8 = add i64 %int8, %bias
+  %add9 = add i64 %int9, %bias
+  %cont = icmp ne i64 %bias, 1
+  br i1 %cont, label %loop, label %exit
+
+exit:
+  %unused1 = call i64 @foo()
+  %factor = load volatile double *@dptr
+
+  %conv0 = bitcast i64 %add0 to double
+  %mul0 = fmul double %conv0, %factor
+  store volatile double %mul0, double *@dptr
+  %conv1 = bitcast i64 %add1 to double
+  %mul1 = fmul double %conv1, %factor
+  store volatile double %mul1, double *@dptr
+  %conv2 = bitcast i64 %add2 to double
+  %mul2 = fmul double %conv2, %factor
+  store volatile double %mul2, double *@dptr
+  %conv3 = bitcast i64 %add3 to double
+  %mul3 = fmul double %conv3, %factor
+  store volatile double %mul3, double *@dptr
+  %conv4 = bitcast i64 %add4 to double
+  %mul4 = fmul double %conv4, %factor
+  store volatile double %mul4, double *@dptr
+  %conv5 = bitcast i64 %add5 to double
+  %mul5 = fmul double %conv5, %factor
+  store volatile double %mul5, double *@dptr
+  %conv6 = bitcast i64 %add6 to double
+  %mul6 = fmul double %conv6, %factor
+  store volatile double %mul6, double *@dptr
+  %conv7 = bitcast i64 %add7 to double
+  %mul7 = fmul double %conv7, %factor
+  store volatile double %mul7, double *@dptr
+  %conv8 = bitcast i64 %add8 to double
+  %mul8 = fmul double %conv8, %factor
+  store volatile double %mul8, double *@dptr
+  %conv9 = bitcast i64 %add9 to double
+  %mul9 = fmul double %conv9, %factor
+  store volatile double %mul9, double *@dptr
+
+  %unused2 = call i64 @foo()
+
+  ret void
+}
+
+; ...likewise LGDR, with the requirements the other way around.
+define void @f13() {
+; CHECK-LABEL: f13:
+; CHECK: %loop
+; CHECK-NOT: stg {{.*}}(%r15)
+; CHECK: %exit
+; CHECK: foo@PLT
+; CHECK-NOT: ld {{.*}}(%r15)
+; CHECK: foo@PLT
+; CHECK: br %r14
+entry:
+  br label %loop
+
+loop:
+  %double0 = phi double [ 1.0, %entry ], [ %mul0, %loop ]
+  %double1 = phi double [ 1.0, %entry ], [ %mul1, %loop ]
+  %double2 = phi double [ 1.0, %entry ], [ %mul2, %loop ]
+  %double3 = phi double [ 1.0, %entry ], [ %mul3, %loop ]
+  %double4 = phi double [ 1.0, %entry ], [ %mul4, %loop ]
+  %double5 = phi double [ 1.0, %entry ], [ %mul5, %loop ]
+  %double6 = phi double [ 1.0, %entry ], [ %mul6, %loop ]
+  %double7 = phi double [ 1.0, %entry ], [ %mul7, %loop ]
+  %double8 = phi double [ 1.0, %entry ], [ %mul8, %loop ]
+  %double9 = phi double [ 1.0, %entry ], [ %mul9, %loop ]
+
+  %factor = call double @bar()
+  %mul0 = fmul double %double0, %factor
+  %mul1 = fmul double %double1, %factor
+  %mul2 = fmul double %double2, %factor
+  %mul3 = fmul double %double3, %factor
+  %mul4 = fmul double %double4, %factor
+  %mul5 = fmul double %double5, %factor
+  %mul6 = fmul double %double6, %factor
+  %mul7 = fmul double %double7, %factor
+  %mul8 = fmul double %double8, %factor
+  %mul9 = fmul double %double9, %factor
+  %cont = fcmp one double %factor, 1.0
+  br i1 %cont, label %loop, label %exit
+
+exit:
+  %unused1 = call i64 @foo()
+  %bias = load volatile i64 *@iptr
+
+  %conv0 = bitcast double %mul0 to i64
+  %add0 = add i64 %conv0, %bias
+  store volatile i64 %add0, i64 *@iptr
+  %conv1 = bitcast double %mul1 to i64
+  %add1 = add i64 %conv1, %bias
+  store volatile i64 %add1, i64 *@iptr
+  %conv2 = bitcast double %mul2 to i64
+  %add2 = add i64 %conv2, %bias
+  store volatile i64 %add2, i64 *@iptr
+  %conv3 = bitcast double %mul3 to i64
+  %add3 = add i64 %conv3, %bias
+  store volatile i64 %add3, i64 *@iptr
+  %conv4 = bitcast double %mul4 to i64
+  %add4 = add i64 %conv4, %bias
+  store volatile i64 %add4, i64 *@iptr
+  %conv5 = bitcast double %mul5 to i64
+  %add5 = add i64 %conv5, %bias
+  store volatile i64 %add5, i64 *@iptr
+  %conv6 = bitcast double %mul6 to i64
+  %add6 = add i64 %conv6, %bias
+  store volatile i64 %add6, i64 *@iptr
+  %conv7 = bitcast double %mul7 to i64
+  %add7 = add i64 %conv7, %bias
+  store volatile i64 %add7, i64 *@iptr
+  %conv8 = bitcast double %mul8 to i64
+  %add8 = add i64 %conv8, %bias
+  store volatile i64 %add8, i64 *@iptr
+  %conv9 = bitcast double %mul9 to i64
+  %add9 = add i64 %conv9, %bias
+  store volatile i64 %add9, i64 *@iptr
+
+  %unused2 = call i64 @foo()
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/fp-move-03.ll b/test/CodeGen/SystemZ/fp-move-03.ll
index 37dbdfa..1273358 100644
--- a/test/CodeGen/SystemZ/fp-move-03.ll
+++ b/test/CodeGen/SystemZ/fp-move-03.ll
@@ -4,7 +4,7 @@
 
 ; Test the low end of the LE range.
 define float @f1(float *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: le %f0, 0(%r2)
 ; CHECK: br %r14
   %val = load float *%src
@@ -13,7 +13,7 @@ define float @f1(float *%src) {
 
 ; Test the high end of the LE range.
 define float @f2(float *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: le %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 1023
@@ -23,7 +23,7 @@ define float @f2(float *%src) {
 
 ; Check the next word up, which should use LEY instead of LE.
 define float @f3(float *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ley %f0, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 1024
@@ -33,7 +33,7 @@ define float @f3(float *%src) {
 
 ; Check the high end of the aligned LEY range.
 define float @f4(float *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ley %f0, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 131071
@@ -44,7 +44,7 @@ define float @f4(float *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f5(float *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: le %f0, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define float @f5(float *%src) {
 
 ; Check the high end of the negative aligned LEY range.
 define float @f6(float *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ley %f0, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 -1
@@ -65,7 +65,7 @@ define float @f6(float *%src) {
 
 ; Check the low end of the LEY range.
 define float @f7(float *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ley %f0, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 -131072
@@ -76,7 +76,7 @@ define float @f7(float *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f8(float *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524292
 ; CHECK: le %f0, 0(%r2)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define float @f8(float *%src) {
 
 ; Check that LE allows an index.
 define float @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: le %f0, 4092({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -99,7 +99,7 @@ define float @f9(i64 %src, i64 %index) {
 
 ; Check that LEY allows an index.
 define float @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ley %f0, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/fp-move-04.ll b/test/CodeGen/SystemZ/fp-move-04.ll
index 72e90d1..1b0278f 100644
--- a/test/CodeGen/SystemZ/fp-move-04.ll
+++ b/test/CodeGen/SystemZ/fp-move-04.ll
@@ -4,7 +4,7 @@
 
 ; Test the low end of the LD range.
 define double @f1(double *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: br %r14
   %val = load double *%src
@@ -13,7 +13,7 @@ define double @f1(double *%src) {
 
 ; Test the high end of the LD range.
 define double @f2(double *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ld %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 511
@@ -23,7 +23,7 @@ define double @f2(double *%src) {
 
 ; Check the next doubleword up, which should use LDY instead of LD.
 define double @f3(double *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ldy %f0, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 512
@@ -33,7 +33,7 @@ define double @f3(double *%src) {
 
 ; Check the high end of the aligned LDY range.
 define double @f4(double *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldy %f0, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 65535
@@ -44,7 +44,7 @@ define double @f4(double *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f5(double *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define double @f5(double *%src) {
 
 ; Check the high end of the negative aligned LDY range.
 define double @f6(double *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ldy %f0, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 -1
@@ -65,7 +65,7 @@ define double @f6(double *%src) {
 
 ; Check the low end of the LDY range.
 define double @f7(double *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ldy %f0, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 -65536
@@ -76,7 +76,7 @@ define double @f7(double *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f8(double *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524296
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define double @f8(double *%src) {
 
 ; Check that LD allows an index.
 define double @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ld %f0, 4095({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -99,7 +99,7 @@ define double @f9(i64 %src, i64 %index) {
 
 ; Check that LDY allows an index.
 define double @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ldy %f0, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/fp-move-05.ll b/test/CodeGen/SystemZ/fp-move-05.ll
index 66ad048..d302a0f 100644
--- a/test/CodeGen/SystemZ/fp-move-05.ll
+++ b/test/CodeGen/SystemZ/fp-move-05.ll
@@ -4,7 +4,7 @@
 
 ; Check loads with no offset.
 define double @f1(i64 %src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: ld %f2, 8(%r2)
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define double @f1(i64 %src) {
 
 ; Check the highest aligned offset that allows LD for both halves.
 define double @f2(i64 %src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ld %f0, 4080(%r2)
 ; CHECK: ld %f2, 4088(%r2)
 ; CHECK: br %r14
@@ -29,7 +29,7 @@ define double @f2(i64 %src) {
 
 ; Check the next doubleword up, which requires a mixture of LD and LDY.
 define double @f3(i64 %src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ld %f0, 4088(%r2)
 ; CHECK: ldy %f2, 4096(%r2)
 ; CHECK: br %r14
@@ -42,7 +42,7 @@ define double @f3(i64 %src) {
 
 ; Check the next doubleword after that, which requires LDY for both halves.
 define double @f4(i64 %src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldy %f0, 4096(%r2)
 ; CHECK: ldy %f2, 4104(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define double @f4(i64 %src) {
 
 ; Check the highest aligned offset that allows LDY for both halves.
 define double @f5(i64 %src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldy %f0, 524272(%r2)
 ; CHECK: ldy %f2, 524280(%r2)
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(i64 %src) {
 ; Check the next doubleword up, which requires separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f6(i64 %src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lay %r1, 524280(%r2)
 ; CHECK: ld %f0, 0(%r1)
 ; CHECK: ld %f2, 8(%r1)
@@ -84,7 +84,7 @@ define double @f6(i64 %src) {
 ; Check the highest aligned negative offset, which needs a combination of
 ; LDY and LD.
 define double @f7(i64 %src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ldy %f0, -8(%r2)
 ; CHECK: ld %f2, 0(%r2)
 ; CHECK: br %r14
@@ -97,7 +97,7 @@ define double @f7(i64 %src) {
 
 ; Check the next doubleword down, which requires LDY for both halves.
 define double @f8(i64 %src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ldy %f0, -16(%r2)
 ; CHECK: ldy %f2, -8(%r2)
 ; CHECK: br %r14
@@ -110,7 +110,7 @@ define double @f8(i64 %src) {
 
 ; Check the lowest offset that allows LDY for both halves.
 define double @f9(i64 %src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ldy %f0, -524288(%r2)
 ; CHECK: ldy %f2, -524280(%r2)
 ; CHECK: br %r14
@@ -124,7 +124,7 @@ define double @f9(i64 %src) {
 ; Check the next doubleword down, which requires separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f10(i64 %src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524296
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: ld %f2, 8(%r2)
@@ -138,7 +138,7 @@ define double @f10(i64 %src) {
 
 ; Check that indices are allowed.
 define double @f11(i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: ld %f0, 4088({{%r2,%r3|%r3,%r2}})
 ; CHECK: ldy %f2, 4096({{%r2,%r3|%r3,%r2}})
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-move-06.ll b/test/CodeGen/SystemZ/fp-move-06.ll
index b660c2a..da67691 100644
--- a/test/CodeGen/SystemZ/fp-move-06.ll
+++ b/test/CodeGen/SystemZ/fp-move-06.ll
@@ -4,7 +4,7 @@
 
 ; Test the low end of the STE range.
 define void @f1(float *%ptr, float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ste %f0, 0(%r2)
 ; CHECK: br %r14
   store float %val, float *%ptr
@@ -13,7 +13,7 @@ define void @f1(float *%ptr, float %val) {
 
 ; Test the high end of the STE range.
 define void @f2(float *%src, float %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ste %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 1023
@@ -23,7 +23,7 @@ define void @f2(float *%src, float %val) {
 
 ; Check the next word up, which should use STEY instead of STE.
 define void @f3(float *%src, float %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stey %f0, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 1024
@@ -33,7 +33,7 @@ define void @f3(float *%src, float %val) {
 
 ; Check the high end of the aligned STEY range.
 define void @f4(float *%src, float %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stey %f0, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 131071
@@ -44,7 +44,7 @@ define void @f4(float *%src, float %val) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f5(float *%src, float %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: ste %f0, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define void @f5(float *%src, float %val) {
 
 ; Check the high end of the negative aligned STEY range.
 define void @f6(float *%src, float %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: stey %f0, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 -1
@@ -65,7 +65,7 @@ define void @f6(float *%src, float %val) {
 
 ; Check the low end of the STEY range.
 define void @f7(float *%src, float %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: stey %f0, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%src, i64 -131072
@@ -76,7 +76,7 @@ define void @f7(float *%src, float %val) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(float *%src, float %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524292
 ; CHECK: ste %f0, 0(%r2)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define void @f8(float *%src, float %val) {
 
 ; Check that STE allows an index.
 define void @f9(i64 %src, i64 %index, float %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ste %f0, 4092({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -99,7 +99,7 @@ define void @f9(i64 %src, i64 %index, float %val) {
 
 ; Check that STEY allows an index.
 define void @f10(i64 %src, i64 %index, float %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: stey %f0, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/fp-move-07.ll b/test/CodeGen/SystemZ/fp-move-07.ll
index 0cb0474..a4f1820 100644
--- a/test/CodeGen/SystemZ/fp-move-07.ll
+++ b/test/CodeGen/SystemZ/fp-move-07.ll
@@ -4,7 +4,7 @@
 
 ; Test the low end of the STD range.
 define void @f1(double *%src, double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: br %r14
   store double %val, double *%src
@@ -13,7 +13,7 @@ define void @f1(double *%src, double %val) {
 
 ; Test the high end of the STD range.
 define void @f2(double *%src, double %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: std %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 511
@@ -23,7 +23,7 @@ define void @f2(double *%src, double %val) {
 
 ; Check the next doubleword up, which should use STDY instead of STD.
 define void @f3(double *%src, double %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stdy %f0, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 512
@@ -33,7 +33,7 @@ define void @f3(double *%src, double %val) {
 
 ; Check the high end of the aligned STDY range.
 define void @f4(double *%src, double %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stdy %f0, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 65535
@@ -44,7 +44,7 @@ define void @f4(double *%src, double %val) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f5(double *%src, double %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define void @f5(double *%src, double %val) {
 
 ; Check the high end of the negative aligned STDY range.
 define void @f6(double *%src, double %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: stdy %f0, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 -1
@@ -65,7 +65,7 @@ define void @f6(double *%src, double %val) {
 
 ; Check the low end of the STDY range.
 define void @f7(double *%src, double %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: stdy %f0, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%src, i64 -65536
@@ -76,7 +76,7 @@ define void @f7(double *%src, double %val) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(double *%src, double %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524296
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define void @f8(double *%src, double %val) {
 
 ; Check that STD allows an index.
 define void @f9(i64 %src, i64 %index, double %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: std %f0, 4095({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -99,7 +99,7 @@ define void @f9(i64 %src, i64 %index, double %val) {
 
 ; Check that STDY allows an index.
 define void @f10(i64 %src, i64 %index, double %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: stdy %f0, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/fp-move-08.ll b/test/CodeGen/SystemZ/fp-move-08.ll
index 448d2ac..88038ab 100644
--- a/test/CodeGen/SystemZ/fp-move-08.ll
+++ b/test/CodeGen/SystemZ/fp-move-08.ll
@@ -4,7 +4,7 @@
 
 ; Check stores with no offset.
 define void @f1(i64 %src, double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define void @f1(i64 %src, double %val) {
 
 ; Check the highest aligned offset that allows STD for both halves.
 define void @f2(i64 %src, double %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: std %f0, 4080(%r2)
 ; CHECK: std %f2, 4088(%r2)
 ; CHECK: br %r14
@@ -29,7 +29,7 @@ define void @f2(i64 %src, double %val) {
 
 ; Check the next doubleword up, which requires a mixture of STD and STDY.
 define void @f3(i64 %src, double %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: std %f0, 4088(%r2)
 ; CHECK: stdy %f2, 4096(%r2)
 ; CHECK: br %r14
@@ -42,7 +42,7 @@ define void @f3(i64 %src, double %val) {
 
 ; Check the next doubleword after that, which requires STDY for both halves.
 define void @f4(i64 %src, double %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stdy %f0, 4096(%r2)
 ; CHECK: stdy %f2, 4104(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define void @f4(i64 %src, double %val) {
 
 ; Check the highest aligned offset that allows STDY for both halves.
 define void @f5(i64 %src, double %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: stdy %f0, 524272(%r2)
 ; CHECK: stdy %f2, 524280(%r2)
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define void @f5(i64 %src, double %val) {
 ; Check the next doubleword up, which requires separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 %src, double %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lay %r1, 524280(%r2)
 ; CHECK: std %f0, 0(%r1)
 ; CHECK: std %f2, 8(%r1)
@@ -84,7 +84,7 @@ define void @f6(i64 %src, double %val) {
 ; Check the highest aligned negative offset, which needs a combination of
 ; STDY and STD.
 define void @f7(i64 %src, double %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: stdy %f0, -8(%r2)
 ; CHECK: std %f2, 0(%r2)
 ; CHECK: br %r14
@@ -97,7 +97,7 @@ define void @f7(i64 %src, double %val) {
 
 ; Check the next doubleword down, which requires STDY for both halves.
 define void @f8(i64 %src, double %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: stdy %f0, -16(%r2)
 ; CHECK: stdy %f2, -8(%r2)
 ; CHECK: br %r14
@@ -110,7 +110,7 @@ define void @f8(i64 %src, double %val) {
 
 ; Check the lowest offset that allows STDY for both halves.
 define void @f9(i64 %src, double %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: stdy %f0, -524288(%r2)
 ; CHECK: stdy %f2, -524280(%r2)
 ; CHECK: br %r14
@@ -124,7 +124,7 @@ define void @f9(i64 %src, double %val) {
 ; Check the next doubleword down, which requires separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f10(i64 %src, double %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524296
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -138,7 +138,7 @@ define void @f10(i64 %src, double %val) {
 
 ; Check that indices are allowed.
 define void @f11(i64 %src, i64 %index, double %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: std %f0, 4088({{%r2,%r3|%r3,%r2}})
 ; CHECK: stdy %f2, 4096({{%r2,%r3|%r3,%r2}})
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-mul-01.ll b/test/CodeGen/SystemZ/fp-mul-01.ll
index 68c78ee..7562d6b 100644
--- a/test/CodeGen/SystemZ/fp-mul-01.ll
+++ b/test/CodeGen/SystemZ/fp-mul-01.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare float @foo()
+
 ; Check register multiplication.
 define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: meebr %f0, %f2
 ; CHECK: br %r14
   %res = fmul float %f1, %f2
@@ -13,7 +15,7 @@ define float @f1(float %f1, float %f2) {
 
 ; Check the low end of the MEEB range.
 define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: meeb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load float *%ptr
@@ -23,7 +25,7 @@ define float @f2(float %f1, float *%ptr) {
 
 ; Check the high end of the aligned MEEB range.
 define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: meeb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -35,7 +37,7 @@ define float @f3(float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: meeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -47,7 +49,7 @@ define float @f4(float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: meeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -59,7 +61,7 @@ define float @f5(float %f1, float *%base) {
 
 ; Check that MEEB allows indices.
 define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: meeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -69,3 +71,49 @@ define float @f6(float %f1, float *%base, i64 %index) {
   %res = fmul float %f1, %f2
   ret float %res
 }
+
+; Check that multiplications of spilled values can use MEEB rather than MEEBR.
+define float @f7(float *%ptr0) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: meeb %f0, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr float *%ptr0, i64 2
+  %ptr2 = getelementptr float *%ptr0, i64 4
+  %ptr3 = getelementptr float *%ptr0, i64 6
+  %ptr4 = getelementptr float *%ptr0, i64 8
+  %ptr5 = getelementptr float *%ptr0, i64 10
+  %ptr6 = getelementptr float *%ptr0, i64 12
+  %ptr7 = getelementptr float *%ptr0, i64 14
+  %ptr8 = getelementptr float *%ptr0, i64 16
+  %ptr9 = getelementptr float *%ptr0, i64 18
+  %ptr10 = getelementptr float *%ptr0, i64 20
+
+  %val0 = load float *%ptr0
+  %val1 = load float *%ptr1
+  %val2 = load float *%ptr2
+  %val3 = load float *%ptr3
+  %val4 = load float *%ptr4
+  %val5 = load float *%ptr5
+  %val6 = load float *%ptr6
+  %val7 = load float *%ptr7
+  %val8 = load float *%ptr8
+  %val9 = load float *%ptr9
+  %val10 = load float *%ptr10
+
+  %ret = call float @foo()
+
+  %mul0 = fmul float %ret, %val0
+  %mul1 = fmul float %mul0, %val1
+  %mul2 = fmul float %mul1, %val2
+  %mul3 = fmul float %mul2, %val3
+  %mul4 = fmul float %mul3, %val4
+  %mul5 = fmul float %mul4, %val5
+  %mul6 = fmul float %mul5, %val6
+  %mul7 = fmul float %mul6, %val7
+  %mul8 = fmul float %mul7, %val8
+  %mul9 = fmul float %mul8, %val9
+  %mul10 = fmul float %mul9, %val10
+
+  ret float %mul10
+}
diff --git a/test/CodeGen/SystemZ/fp-mul-02.ll b/test/CodeGen/SystemZ/fp-mul-02.ll
index ec51a4c..cf4448f 100644
--- a/test/CodeGen/SystemZ/fp-mul-02.ll
+++ b/test/CodeGen/SystemZ/fp-mul-02.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare float @foo()
+
 ; Check register multiplication.
 define double @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mdebr %f0, %f2
 ; CHECK: br %r14
   %f1x = fpext float %f1 to double
@@ -15,7 +17,7 @@ define double @f1(float %f1, float %f2) {
 
 ; Check the low end of the MDEB range.
 define double @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mdeb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load float *%ptr
@@ -27,7 +29,7 @@ define double @f2(float %f1, float *%ptr) {
 
 ; Check the high end of the aligned MDEB range.
 define double @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mdeb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -41,7 +43,7 @@ define double @f3(float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mdeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +57,7 @@ define double @f4(float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: mdeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -69,7 +71,7 @@ define double @f5(float %f1, float *%base) {
 
 ; Check that MDEB allows indices.
 define double @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: mdeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -81,3 +83,121 @@ define double @f6(float %f1, float *%base, i64 %index) {
   %res = fmul double %f1x, %f2x
   ret double %res
 }
+
+; Check that multiplications of spilled values can use MDEB rather than MDEBR.
+define float @f7(float *%ptr0) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: mdeb %f0, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr float *%ptr0, i64 2
+  %ptr2 = getelementptr float *%ptr0, i64 4
+  %ptr3 = getelementptr float *%ptr0, i64 6
+  %ptr4 = getelementptr float *%ptr0, i64 8
+  %ptr5 = getelementptr float *%ptr0, i64 10
+  %ptr6 = getelementptr float *%ptr0, i64 12
+  %ptr7 = getelementptr float *%ptr0, i64 14
+  %ptr8 = getelementptr float *%ptr0, i64 16
+  %ptr9 = getelementptr float *%ptr0, i64 18
+  %ptr10 = getelementptr float *%ptr0, i64 20
+
+  %val0 = load float *%ptr0
+  %val1 = load float *%ptr1
+  %val2 = load float *%ptr2
+  %val3 = load float *%ptr3
+  %val4 = load float *%ptr4
+  %val5 = load float *%ptr5
+  %val6 = load float *%ptr6
+  %val7 = load float *%ptr7
+  %val8 = load float *%ptr8
+  %val9 = load float *%ptr9
+  %val10 = load float *%ptr10
+
+  %frob0 = fadd float %val0, %val0
+  %frob1 = fadd float %val1, %val1
+  %frob2 = fadd float %val2, %val2
+  %frob3 = fadd float %val3, %val3
+  %frob4 = fadd float %val4, %val4
+  %frob5 = fadd float %val5, %val5
+  %frob6 = fadd float %val6, %val6
+  %frob7 = fadd float %val7, %val7
+  %frob8 = fadd float %val8, %val8
+  %frob9 = fadd float %val9, %val9
+  %frob10 = fadd float %val9, %val10
+
+  store float %frob0, float *%ptr0
+  store float %frob1, float *%ptr1
+  store float %frob2, float *%ptr2
+  store float %frob3, float *%ptr3
+  store float %frob4, float *%ptr4
+  store float %frob5, float *%ptr5
+  store float %frob6, float *%ptr6
+  store float %frob7, float *%ptr7
+  store float %frob8, float *%ptr8
+  store float %frob9, float *%ptr9
+  store float %frob10, float *%ptr10
+
+  %ret = call float @foo()
+
+  %accext0 = fpext float %ret to double
+  %ext0 = fpext float %frob0 to double
+  %mul0 = fmul double %accext0, %ext0
+  %extra0 = fmul double %mul0, 1.01
+  %trunc0 = fptrunc double %extra0 to float
+
+  %accext1 = fpext float %trunc0 to double
+  %ext1 = fpext float %frob1 to double
+  %mul1 = fmul double %accext1, %ext1
+  %extra1 = fmul double %mul1, 1.11
+  %trunc1 = fptrunc double %extra1 to float
+
+  %accext2 = fpext float %trunc1 to double
+  %ext2 = fpext float %frob2 to double
+  %mul2 = fmul double %accext2, %ext2
+  %extra2 = fmul double %mul2, 1.21
+  %trunc2 = fptrunc double %extra2 to float
+
+  %accext3 = fpext float %trunc2 to double
+  %ext3 = fpext float %frob3 to double
+  %mul3 = fmul double %accext3, %ext3
+  %extra3 = fmul double %mul3, 1.31
+  %trunc3 = fptrunc double %extra3 to float
+
+  %accext4 = fpext float %trunc3 to double
+  %ext4 = fpext float %frob4 to double
+  %mul4 = fmul double %accext4, %ext4
+  %extra4 = fmul double %mul4, 1.41
+  %trunc4 = fptrunc double %extra4 to float
+
+  %accext5 = fpext float %trunc4 to double
+  %ext5 = fpext float %frob5 to double
+  %mul5 = fmul double %accext5, %ext5
+  %extra5 = fmul double %mul5, 1.51
+  %trunc5 = fptrunc double %extra5 to float
+
+  %accext6 = fpext float %trunc5 to double
+  %ext6 = fpext float %frob6 to double
+  %mul6 = fmul double %accext6, %ext6
+  %extra6 = fmul double %mul6, 1.61
+  %trunc6 = fptrunc double %extra6 to float
+
+  %accext7 = fpext float %trunc6 to double
+  %ext7 = fpext float %frob7 to double
+  %mul7 = fmul double %accext7, %ext7
+  %extra7 = fmul double %mul7, 1.71
+  %trunc7 = fptrunc double %extra7 to float
+
+  %accext8 = fpext float %trunc7 to double
+  %ext8 = fpext float %frob8 to double
+  %mul8 = fmul double %accext8, %ext8
+  %extra8 = fmul double %mul8, 1.81
+  %trunc8 = fptrunc double %extra8 to float
+
+  %accext9 = fpext float %trunc8 to double
+  %ext9 = fpext float %frob9 to double
+  %mul9 = fmul double %accext9, %ext9
+  %extra9 = fmul double %mul9, 1.91
+  %trunc9 = fptrunc double %extra9 to float
+
+  ret float %trunc9
+}
diff --git a/test/CodeGen/SystemZ/fp-mul-03.ll b/test/CodeGen/SystemZ/fp-mul-03.ll
index 9849247..6d296f0 100644
--- a/test/CodeGen/SystemZ/fp-mul-03.ll
+++ b/test/CodeGen/SystemZ/fp-mul-03.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare double @foo()
+
 ; Check register multiplication.
 define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mdbr %f0, %f2
 ; CHECK: br %r14
   %res = fmul double %f1, %f2
@@ -13,7 +15,7 @@ define double @f1(double %f1, double %f2) {
 
 ; Check the low end of the MDB range.
 define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mdb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load double *%ptr
@@ -23,7 +25,7 @@ define double @f2(double %f1, double *%ptr) {
 
 ; Check the high end of the aligned MDB range.
 define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mdb %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%base, i64 511
@@ -35,7 +37,7 @@ define double @f3(double %f1, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -47,7 +49,7 @@ define double @f4(double %f1, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: mdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -59,7 +61,7 @@ define double @f5(double %f1, double *%base) {
 
 ; Check that MDB allows indices.
 define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: mdb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
@@ -69,3 +71,49 @@ define double @f6(double %f1, double *%base, i64 %index) {
   %res = fmul double %f1, %f2
   ret double %res
 }
+
+; Check that multiplications of spilled values can use MDB rather than MDBR.
+define double @f7(double *%ptr0) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: mdb %f0, 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr double *%ptr0, i64 2
+  %ptr2 = getelementptr double *%ptr0, i64 4
+  %ptr3 = getelementptr double *%ptr0, i64 6
+  %ptr4 = getelementptr double *%ptr0, i64 8
+  %ptr5 = getelementptr double *%ptr0, i64 10
+  %ptr6 = getelementptr double *%ptr0, i64 12
+  %ptr7 = getelementptr double *%ptr0, i64 14
+  %ptr8 = getelementptr double *%ptr0, i64 16
+  %ptr9 = getelementptr double *%ptr0, i64 18
+  %ptr10 = getelementptr double *%ptr0, i64 20
+
+  %val0 = load double *%ptr0
+  %val1 = load double *%ptr1
+  %val2 = load double *%ptr2
+  %val3 = load double *%ptr3
+  %val4 = load double *%ptr4
+  %val5 = load double *%ptr5
+  %val6 = load double *%ptr6
+  %val7 = load double *%ptr7
+  %val8 = load double *%ptr8
+  %val9 = load double *%ptr9
+  %val10 = load double *%ptr10
+
+  %ret = call double @foo()
+
+  %mul0 = fmul double %ret, %val0
+  %mul1 = fmul double %mul0, %val1
+  %mul2 = fmul double %mul1, %val2
+  %mul3 = fmul double %mul2, %val3
+  %mul4 = fmul double %mul3, %val4
+  %mul5 = fmul double %mul4, %val5
+  %mul6 = fmul double %mul5, %val6
+  %mul7 = fmul double %mul6, %val7
+  %mul8 = fmul double %mul7, %val8
+  %mul9 = fmul double %mul8, %val9
+  %mul10 = fmul double %mul9, %val10
+
+  ret double %mul10
+}
diff --git a/test/CodeGen/SystemZ/fp-mul-04.ll b/test/CodeGen/SystemZ/fp-mul-04.ll
index 712ead8..3c4325e 100644
--- a/test/CodeGen/SystemZ/fp-mul-04.ll
+++ b/test/CodeGen/SystemZ/fp-mul-04.ll
@@ -2,11 +2,13 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare double @foo()
+
 ; Check register multiplication.  "mxdbr %f0, %f2" is not valid from LLVM's
 ; point of view, because %f2 is the low register of the FP128 %f0.  Pass the
 ; multiplier in %f4 instead.
 define void @f1(double %f1, double %dummy, double %f2, fp128 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mxdbr %f0, %f4
 ; CHECK: std %f0, 0(%r2)
 ; CHECK: std %f2, 8(%r2)
@@ -20,7 +22,7 @@ define void @f1(double %f1, double %dummy, double %f2, fp128 *%dst) {
 
 ; Check the low end of the MXDB range.
 define void @f2(double %f1, double *%ptr, fp128 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mxdb %f0, 0(%r2)
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
@@ -35,7 +37,7 @@ define void @f2(double %f1, double *%ptr, fp128 *%dst) {
 
 ; Check the high end of the aligned MXDB range.
 define void @f3(double %f1, double *%base, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mxdb %f0, 4088(%r2)
 ; CHECK: std %f0, 0(%r3)
 ; CHECK: std %f2, 8(%r3)
@@ -52,7 +54,7 @@ define void @f3(double %f1, double *%base, fp128 *%dst) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f4(double %f1, double *%base, fp128 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mxdb %f0, 0(%r2)
 ; CHECK: std %f0, 0(%r3)
@@ -69,7 +71,7 @@ define void @f4(double %f1, double *%base, fp128 *%dst) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f5(double %f1, double *%base, fp128 *%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: mxdb %f0, 0(%r2)
 ; CHECK: std %f0, 0(%r3)
@@ -86,7 +88,7 @@ define void @f5(double %f1, double *%base, fp128 *%dst) {
 
 ; Check that MXDB allows indices.
 define void @f6(double %f1, double *%base, i64 %index, fp128 *%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: mxdb %f0, 800(%r1,%r2)
 ; CHECK: std %f0, 0(%r4)
@@ -101,3 +103,131 @@ define void @f6(double %f1, double *%base, i64 %index, fp128 *%dst) {
   store fp128 %res, fp128 *%dst
   ret void
 }
+
+; Check that multiplications of spilled values can use MXDB rather than MXDBR.
+define double @f7(double *%ptr0) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: mxdb %f0, 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr double *%ptr0, i64 2
+  %ptr2 = getelementptr double *%ptr0, i64 4
+  %ptr3 = getelementptr double *%ptr0, i64 6
+  %ptr4 = getelementptr double *%ptr0, i64 8
+  %ptr5 = getelementptr double *%ptr0, i64 10
+  %ptr6 = getelementptr double *%ptr0, i64 12
+  %ptr7 = getelementptr double *%ptr0, i64 14
+  %ptr8 = getelementptr double *%ptr0, i64 16
+  %ptr9 = getelementptr double *%ptr0, i64 18
+  %ptr10 = getelementptr double *%ptr0, i64 20
+
+  %val0 = load double *%ptr0
+  %val1 = load double *%ptr1
+  %val2 = load double *%ptr2
+  %val3 = load double *%ptr3
+  %val4 = load double *%ptr4
+  %val5 = load double *%ptr5
+  %val6 = load double *%ptr6
+  %val7 = load double *%ptr7
+  %val8 = load double *%ptr8
+  %val9 = load double *%ptr9
+  %val10 = load double *%ptr10
+
+  %frob0 = fadd double %val0, %val0
+  %frob1 = fadd double %val1, %val1
+  %frob2 = fadd double %val2, %val2
+  %frob3 = fadd double %val3, %val3
+  %frob4 = fadd double %val4, %val4
+  %frob5 = fadd double %val5, %val5
+  %frob6 = fadd double %val6, %val6
+  %frob7 = fadd double %val7, %val7
+  %frob8 = fadd double %val8, %val8
+  %frob9 = fadd double %val9, %val9
+  %frob10 = fadd double %val9, %val10
+
+  store double %frob0, double *%ptr0
+  store double %frob1, double *%ptr1
+  store double %frob2, double *%ptr2
+  store double %frob3, double *%ptr3
+  store double %frob4, double *%ptr4
+  store double %frob5, double *%ptr5
+  store double %frob6, double *%ptr6
+  store double %frob7, double *%ptr7
+  store double %frob8, double *%ptr8
+  store double %frob9, double *%ptr9
+  store double %frob10, double *%ptr10
+
+  %ret = call double @foo()
+
+  %accext0 = fpext double %ret to fp128
+  %ext0 = fpext double %frob0 to fp128
+  %mul0 = fmul fp128 %accext0, %ext0
+  %const0 = fpext double 1.01 to fp128
+  %extra0 = fmul fp128 %mul0, %const0
+  %trunc0 = fptrunc fp128 %extra0 to double
+
+  %accext1 = fpext double %trunc0 to fp128
+  %ext1 = fpext double %frob1 to fp128
+  %mul1 = fmul fp128 %accext1, %ext1
+  %const1 = fpext double 1.11 to fp128
+  %extra1 = fmul fp128 %mul1, %const1
+  %trunc1 = fptrunc fp128 %extra1 to double
+
+  %accext2 = fpext double %trunc1 to fp128
+  %ext2 = fpext double %frob2 to fp128
+  %mul2 = fmul fp128 %accext2, %ext2
+  %const2 = fpext double 1.21 to fp128
+  %extra2 = fmul fp128 %mul2, %const2
+  %trunc2 = fptrunc fp128 %extra2 to double
+
+  %accext3 = fpext double %trunc2 to fp128
+  %ext3 = fpext double %frob3 to fp128
+  %mul3 = fmul fp128 %accext3, %ext3
+  %const3 = fpext double 1.31 to fp128
+  %extra3 = fmul fp128 %mul3, %const3
+  %trunc3 = fptrunc fp128 %extra3 to double
+
+  %accext4 = fpext double %trunc3 to fp128
+  %ext4 = fpext double %frob4 to fp128
+  %mul4 = fmul fp128 %accext4, %ext4
+  %const4 = fpext double 1.41 to fp128
+  %extra4 = fmul fp128 %mul4, %const4
+  %trunc4 = fptrunc fp128 %extra4 to double
+
+  %accext5 = fpext double %trunc4 to fp128
+  %ext5 = fpext double %frob5 to fp128
+  %mul5 = fmul fp128 %accext5, %ext5
+  %const5 = fpext double 1.51 to fp128
+  %extra5 = fmul fp128 %mul5, %const5
+  %trunc5 = fptrunc fp128 %extra5 to double
+
+  %accext6 = fpext double %trunc5 to fp128
+  %ext6 = fpext double %frob6 to fp128
+  %mul6 = fmul fp128 %accext6, %ext6
+  %const6 = fpext double 1.61 to fp128
+  %extra6 = fmul fp128 %mul6, %const6
+  %trunc6 = fptrunc fp128 %extra6 to double
+
+  %accext7 = fpext double %trunc6 to fp128
+  %ext7 = fpext double %frob7 to fp128
+  %mul7 = fmul fp128 %accext7, %ext7
+  %const7 = fpext double 1.71 to fp128
+  %extra7 = fmul fp128 %mul7, %const7
+  %trunc7 = fptrunc fp128 %extra7 to double
+
+  %accext8 = fpext double %trunc7 to fp128
+  %ext8 = fpext double %frob8 to fp128
+  %mul8 = fmul fp128 %accext8, %ext8
+  %const8 = fpext double 1.81 to fp128
+  %extra8 = fmul fp128 %mul8, %const8
+  %trunc8 = fptrunc fp128 %extra8 to double
+
+  %accext9 = fpext double %trunc8 to fp128
+  %ext9 = fpext double %frob9 to fp128
+  %mul9 = fmul fp128 %accext9, %ext9
+  %const9 = fpext double 1.91 to fp128
+  %extra9 = fmul fp128 %mul9, %const9
+  %trunc9 = fptrunc fp128 %extra9 to double
+
+  ret double %trunc9
+}
diff --git a/test/CodeGen/SystemZ/fp-mul-05.ll b/test/CodeGen/SystemZ/fp-mul-05.ll
index df5bc4e..0be1fe8 100644
--- a/test/CodeGen/SystemZ/fp-mul-05.ll
+++ b/test/CodeGen/SystemZ/fp-mul-05.ll
@@ -4,7 +4,7 @@
 
 ; There is no memory form of 128-bit multiplication.
 define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r2)
 ; CHECK: ld %f3, 8(%r2)
diff --git a/test/CodeGen/SystemZ/fp-mul-06.ll b/test/CodeGen/SystemZ/fp-mul-06.ll
index 8124c68..3f631a6 100644
--- a/test/CodeGen/SystemZ/fp-mul-06.ll
+++ b/test/CodeGen/SystemZ/fp-mul-06.ll
@@ -3,7 +3,7 @@
 declare float @llvm.fma.f32(float %f1, float %f2, float %f3)
 
 define float @f1(float %f1, float %f2, float %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: maebr %f4, %f0, %f2
 ; CHECK: ler %f0, %f4
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define float @f1(float %f1, float %f2, float %acc) {
 }
 
 define float @f2(float %f1, float *%ptr, float %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: maeb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
@@ -22,7 +22,7 @@ define float @f2(float %f1, float *%ptr, float %acc) {
 }
 
 define float @f3(float %f1, float *%base, float %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: maeb %f2, %f0, 4092(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
@@ -36,7 +36,7 @@ define float @f4(float %f1, float *%base, float %acc) {
 ; The important thing here is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: maeb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
@@ -51,7 +51,7 @@ define float @f5(float %f1, float *%base, float %acc) {
 ; Here too the important thing is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: maeb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
@@ -63,7 +63,7 @@ define float @f5(float %f1, float *%base, float %acc) {
 }
 
 define float @f6(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: maeb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ler %f0, %f2
@@ -75,7 +75,7 @@ define float @f6(float %f1, float *%base, i64 %index, float %acc) {
 }
 
 define float @f7(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: maeb %f2, %f0, 4092({{%r1,%r2|%r2,%r1}})
 ; CHECK: ler %f0, %f2
@@ -88,7 +88,7 @@ define float @f7(float %f1, float *%base, i64 %index, float %acc) {
 }
 
 define float @f8(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
 ; CHECK: maeb %f2, %f0, 0(%r1)
diff --git a/test/CodeGen/SystemZ/fp-mul-07.ll b/test/CodeGen/SystemZ/fp-mul-07.ll
index b8e4483..e4f5904 100644
--- a/test/CodeGen/SystemZ/fp-mul-07.ll
+++ b/test/CodeGen/SystemZ/fp-mul-07.ll
@@ -3,7 +3,7 @@
 declare double @llvm.fma.f64(double %f1, double %f2, double %f3)
 
 define double @f1(double %f1, double %f2, double %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: madbr %f4, %f0, %f2
 ; CHECK: ldr %f0, %f4
 ; CHECK: br %r14
@@ -12,7 +12,7 @@ define double @f1(double %f1, double %f2, double %acc) {
 }
 
 define double @f2(double %f1, double *%ptr, double %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: madb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -22,7 +22,7 @@ define double @f2(double %f1, double *%ptr, double %acc) {
 }
 
 define double @f3(double %f1, double *%base, double %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: madb %f2, %f0, 4088(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -36,7 +36,7 @@ define double @f4(double %f1, double *%base, double %acc) {
 ; The important thing here is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: madb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
@@ -51,7 +51,7 @@ define double @f5(double %f1, double *%base, double %acc) {
 ; Here too the important thing is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: madb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
@@ -63,7 +63,7 @@ define double @f5(double %f1, double *%base, double %acc) {
 }
 
 define double @f6(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: madb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ldr %f0, %f2
@@ -75,7 +75,7 @@ define double @f6(double %f1, double *%base, i64 %index, double %acc) {
 }
 
 define double @f7(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: madb %f2, %f0, 4088({{%r1,%r2|%r2,%r1}})
 ; CHECK: ldr %f0, %f2
@@ -88,7 +88,7 @@ define double @f7(double %f1, double *%base, i64 %index, double %acc) {
 }
 
 define double @f8(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
 ; CHECK: madb %f2, %f0, 0(%r1)
diff --git a/test/CodeGen/SystemZ/fp-mul-08.ll b/test/CodeGen/SystemZ/fp-mul-08.ll
index 5c14740..ab5fcb2 100644
--- a/test/CodeGen/SystemZ/fp-mul-08.ll
+++ b/test/CodeGen/SystemZ/fp-mul-08.ll
@@ -3,7 +3,7 @@
 declare float @llvm.fma.f32(float %f1, float %f2, float %f3)
 
 define float @f1(float %f1, float %f2, float %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msebr %f4, %f0, %f2
 ; CHECK: ler %f0, %f4
 ; CHECK: br %r14
@@ -13,7 +13,7 @@ define float @f1(float %f1, float %f2, float %acc) {
 }
 
 define float @f2(float %f1, float *%ptr, float %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mseb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
@@ -24,7 +24,7 @@ define float @f2(float %f1, float *%ptr, float %acc) {
 }
 
 define float @f3(float %f1, float *%base, float %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mseb %f2, %f0, 4092(%r2)
 ; CHECK: ler %f0, %f2
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define float @f4(float %f1, float *%base, float %acc) {
 ; The important thing here is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mseb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
@@ -55,7 +55,7 @@ define float @f5(float %f1, float *%base, float %acc) {
 ; Here too the important thing is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: mseb %f2, %f0, 0(%r2)
 ; CHECK: ler %f0, %f2
@@ -68,7 +68,7 @@ define float @f5(float %f1, float *%base, float %acc) {
 }
 
 define float @f6(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: mseb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ler %f0, %f2
@@ -81,7 +81,7 @@ define float @f6(float %f1, float *%base, i64 %index, float %acc) {
 }
 
 define float @f7(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: mseb %f2, %f0, 4092({{%r1,%r2|%r2,%r1}})
 ; CHECK: ler %f0, %f2
@@ -95,7 +95,7 @@ define float @f7(float %f1, float *%base, i64 %index, float %acc) {
 }
 
 define float @f8(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
 ; CHECK: mseb %f2, %f0, 0(%r1)
diff --git a/test/CodeGen/SystemZ/fp-mul-09.ll b/test/CodeGen/SystemZ/fp-mul-09.ll
index bcae1e3..7e74096 100644
--- a/test/CodeGen/SystemZ/fp-mul-09.ll
+++ b/test/CodeGen/SystemZ/fp-mul-09.ll
@@ -3,7 +3,7 @@
 declare double @llvm.fma.f64(double %f1, double %f2, double %f3)
 
 define double @f1(double %f1, double %f2, double %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msdbr %f4, %f0, %f2
 ; CHECK: ldr %f0, %f4
 ; CHECK: br %r14
@@ -13,7 +13,7 @@ define double @f1(double %f1, double %f2, double %acc) {
 }
 
 define double @f2(double %f1, double *%ptr, double %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: msdb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -24,7 +24,7 @@ define double @f2(double %f1, double *%ptr, double %acc) {
 }
 
 define double @f3(double %f1, double *%base, double %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: msdb %f2, %f0, 4088(%r2)
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define double @f4(double %f1, double *%base, double %acc) {
 ; The important thing here is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: msdb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
@@ -55,7 +55,7 @@ define double @f5(double %f1, double *%base, double %acc) {
 ; Here too the important thing is that we don't generate an out-of-range
 ; displacement.  Other sequences besides this one would be OK.
 ;
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: msdb %f2, %f0, 0(%r2)
 ; CHECK: ldr %f0, %f2
@@ -68,7 +68,7 @@ define double @f5(double %f1, double *%base, double %acc) {
 }
 
 define double @f6(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: msdb %f2, %f0, 0(%r1,%r2)
 ; CHECK: ldr %f0, %f2
@@ -81,7 +81,7 @@ define double @f6(double %f1, double *%base, i64 %index, double %acc) {
 }
 
 define double @f7(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: msdb %f2, %f0, 4088({{%r1,%r2|%r2,%r1}})
 ; CHECK: ldr %f0, %f2
@@ -95,7 +95,7 @@ define double @f7(double %f1, double *%base, i64 %index, double %acc) {
 }
 
 define double @f8(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
 ; CHECK: msdb %f2, %f0, 0(%r1)
diff --git a/test/CodeGen/SystemZ/fp-neg-01.ll b/test/CodeGen/SystemZ/fp-neg-01.ll
index 09a4a53..1cc6d81 100644
--- a/test/CodeGen/SystemZ/fp-neg-01.ll
+++ b/test/CodeGen/SystemZ/fp-neg-01.ll
@@ -4,7 +4,7 @@
 
 ; Test f32.
 define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lcebr %f0, %f0
 ; CHECK: br %r14
   %res = fsub float -0.0, %f
@@ -13,7 +13,7 @@ define float @f1(float %f) {
 
 ; Test f64.
 define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lcdbr %f0, %f0
 ; CHECK: br %r14
   %res = fsub double -0.0, %f
@@ -24,7 +24,7 @@ define double @f2(double %f) {
 ; be better implemented using an XI on the upper byte.  Do some extra
 ; processing so that using FPRs is unequivocally better.
 define void @f3(fp128 *%ptr, fp128 *%ptr2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lcxbr
 ; CHECK: dxbr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/fp-round-01.ll b/test/CodeGen/SystemZ/fp-round-01.ll
index 20325c3..f2530dc 100644
--- a/test/CodeGen/SystemZ/fp-round-01.ll
+++ b/test/CodeGen/SystemZ/fp-round-01.ll
@@ -6,7 +6,7 @@
 ; Test f32.
 declare float @llvm.rint.f32(float %f)
 define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: fiebr %f0, 0, %f0
 ; CHECK: br %r14
   %res = call float @llvm.rint.f32(float %f)
@@ -16,7 +16,7 @@ define float @f1(float %f) {
 ; Test f64.
 declare double @llvm.rint.f64(double %f)
 define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: fidbr %f0, 0, %f0
 ; CHECK: br %r14
   %res = call double @llvm.rint.f64(double %f)
@@ -26,7 +26,7 @@ define double @f2(double %f) {
 ; Test f128.
 declare fp128 @llvm.rint.f128(fp128 %f)
 define void @f3(fp128 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: fixbr %f0, 0, %f0
 ; CHECK: br %r14
   %src = load fp128 *%ptr
diff --git a/test/CodeGen/SystemZ/fp-sqrt-01.ll b/test/CodeGen/SystemZ/fp-sqrt-01.ll
index 7ed27f5..b6568d6 100644
--- a/test/CodeGen/SystemZ/fp-sqrt-01.ll
+++ b/test/CodeGen/SystemZ/fp-sqrt-01.ll
@@ -6,7 +6,7 @@ declare float @llvm.sqrt.f32(float %f)
 
 ; Check register square root.
 define float @f1(float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sqebr %f0, %f0
 ; CHECK: br %r14
   %res = call float @llvm.sqrt.f32(float %val)
@@ -15,7 +15,7 @@ define float @f1(float %val) {
 
 ; Check the low end of the SQEB range.
 define float @f2(float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sqeb %f0, 0(%r2)
 ; CHECK: br %r14
   %val = load float *%ptr
@@ -25,7 +25,7 @@ define float @f2(float *%ptr) {
 
 ; Check the high end of the aligned SQEB range.
 define float @f3(float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sqeb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -37,7 +37,7 @@ define float @f3(float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f4(float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: sqeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define float @f4(float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define float @f5(float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: sqeb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define float @f5(float *%base) {
 
 ; Check that SQEB allows indices.
 define float @f6(float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: sqeb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -71,3 +71,84 @@ define float @f6(float *%base, i64 %index) {
   %res = call float @llvm.sqrt.f32(float %val)
   ret float %res
 }
+
+; Test a case where we spill the source of at least one SQEBR.  We want
+; to use SQEB if possible.
+define void @f7(float *%ptr) {
+; CHECK-LABEL: f7:
+; CHECK: sqeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %val0 = load volatile float *%ptr
+  %val1 = load volatile float *%ptr
+  %val2 = load volatile float *%ptr
+  %val3 = load volatile float *%ptr
+  %val4 = load volatile float *%ptr
+  %val5 = load volatile float *%ptr
+  %val6 = load volatile float *%ptr
+  %val7 = load volatile float *%ptr
+  %val8 = load volatile float *%ptr
+  %val9 = load volatile float *%ptr
+  %val10 = load volatile float *%ptr
+  %val11 = load volatile float *%ptr
+  %val12 = load volatile float *%ptr
+  %val13 = load volatile float *%ptr
+  %val14 = load volatile float *%ptr
+  %val15 = load volatile float *%ptr
+  %val16 = load volatile float *%ptr
+
+  %sqrt0 = call float @llvm.sqrt.f32(float %val0)
+  %sqrt1 = call float @llvm.sqrt.f32(float %val1)
+  %sqrt2 = call float @llvm.sqrt.f32(float %val2)
+  %sqrt3 = call float @llvm.sqrt.f32(float %val3)
+  %sqrt4 = call float @llvm.sqrt.f32(float %val4)
+  %sqrt5 = call float @llvm.sqrt.f32(float %val5)
+  %sqrt6 = call float @llvm.sqrt.f32(float %val6)
+  %sqrt7 = call float @llvm.sqrt.f32(float %val7)
+  %sqrt8 = call float @llvm.sqrt.f32(float %val8)
+  %sqrt9 = call float @llvm.sqrt.f32(float %val9)
+  %sqrt10 = call float @llvm.sqrt.f32(float %val10)
+  %sqrt11 = call float @llvm.sqrt.f32(float %val11)
+  %sqrt12 = call float @llvm.sqrt.f32(float %val12)
+  %sqrt13 = call float @llvm.sqrt.f32(float %val13)
+  %sqrt14 = call float @llvm.sqrt.f32(float %val14)
+  %sqrt15 = call float @llvm.sqrt.f32(float %val15)
+  %sqrt16 = call float @llvm.sqrt.f32(float %val16)
+
+  store volatile float %val0, float *%ptr
+  store volatile float %val1, float *%ptr
+  store volatile float %val2, float *%ptr
+  store volatile float %val3, float *%ptr
+  store volatile float %val4, float *%ptr
+  store volatile float %val5, float *%ptr
+  store volatile float %val6, float *%ptr
+  store volatile float %val7, float *%ptr
+  store volatile float %val8, float *%ptr
+  store volatile float %val9, float *%ptr
+  store volatile float %val10, float *%ptr
+  store volatile float %val11, float *%ptr
+  store volatile float %val12, float *%ptr
+  store volatile float %val13, float *%ptr
+  store volatile float %val14, float *%ptr
+  store volatile float %val15, float *%ptr
+  store volatile float %val16, float *%ptr
+
+  store volatile float %sqrt0, float *%ptr
+  store volatile float %sqrt1, float *%ptr
+  store volatile float %sqrt2, float *%ptr
+  store volatile float %sqrt3, float *%ptr
+  store volatile float %sqrt4, float *%ptr
+  store volatile float %sqrt5, float *%ptr
+  store volatile float %sqrt6, float *%ptr
+  store volatile float %sqrt7, float *%ptr
+  store volatile float %sqrt8, float *%ptr
+  store volatile float %sqrt9, float *%ptr
+  store volatile float %sqrt10, float *%ptr
+  store volatile float %sqrt11, float *%ptr
+  store volatile float %sqrt12, float *%ptr
+  store volatile float %sqrt13, float *%ptr
+  store volatile float %sqrt14, float *%ptr
+  store volatile float %sqrt15, float *%ptr
+  store volatile float %sqrt16, float *%ptr
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/fp-sqrt-02.ll b/test/CodeGen/SystemZ/fp-sqrt-02.ll
index 22a91ad..b07a2c6 100644
--- a/test/CodeGen/SystemZ/fp-sqrt-02.ll
+++ b/test/CodeGen/SystemZ/fp-sqrt-02.ll
@@ -6,7 +6,7 @@ declare double @llvm.sqrt.f64(double %f)
 
 ; Check register square root.
 define double @f1(double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sqdbr %f0, %f0
 ; CHECK: br %r14
   %res = call double @llvm.sqrt.f64(double %val)
@@ -15,7 +15,7 @@ define double @f1(double %val) {
 
 ; Check the low end of the SQDB range.
 define double @f2(double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sqdb %f0, 0(%r2)
 ; CHECK: br %r14
   %val = load double *%ptr
@@ -25,7 +25,7 @@ define double @f2(double *%ptr) {
 
 ; Check the high end of the aligned SQDB range.
 define double @f3(double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sqdb %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%base, i64 511
@@ -37,7 +37,7 @@ define double @f3(double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: sqdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -49,7 +49,7 @@ define double @f4(double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: sqdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define double @f5(double *%base) {
 
 ; Check that SQDB allows indices.
 define double @f6(double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: sqdb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
@@ -71,3 +71,84 @@ define double @f6(double *%base, i64 %index) {
   %res = call double @llvm.sqrt.f64(double %val)
   ret double %res
 }
+
+; Test a case where we spill the source of at least one SQDBR.  We want
+; to use SQDB if possible.
+define void @f7(double *%ptr) {
+; CHECK-LABEL: f7:
+; CHECK: sqdb {{%f[0-9]+}}, 160(%r15)
+; CHECK: br %r14
+  %val0 = load volatile double *%ptr
+  %val1 = load volatile double *%ptr
+  %val2 = load volatile double *%ptr
+  %val3 = load volatile double *%ptr
+  %val4 = load volatile double *%ptr
+  %val5 = load volatile double *%ptr
+  %val6 = load volatile double *%ptr
+  %val7 = load volatile double *%ptr
+  %val8 = load volatile double *%ptr
+  %val9 = load volatile double *%ptr
+  %val10 = load volatile double *%ptr
+  %val11 = load volatile double *%ptr
+  %val12 = load volatile double *%ptr
+  %val13 = load volatile double *%ptr
+  %val14 = load volatile double *%ptr
+  %val15 = load volatile double *%ptr
+  %val16 = load volatile double *%ptr
+
+  %sqrt0 = call double @llvm.sqrt.f64(double %val0)
+  %sqrt1 = call double @llvm.sqrt.f64(double %val1)
+  %sqrt2 = call double @llvm.sqrt.f64(double %val2)
+  %sqrt3 = call double @llvm.sqrt.f64(double %val3)
+  %sqrt4 = call double @llvm.sqrt.f64(double %val4)
+  %sqrt5 = call double @llvm.sqrt.f64(double %val5)
+  %sqrt6 = call double @llvm.sqrt.f64(double %val6)
+  %sqrt7 = call double @llvm.sqrt.f64(double %val7)
+  %sqrt8 = call double @llvm.sqrt.f64(double %val8)
+  %sqrt9 = call double @llvm.sqrt.f64(double %val9)
+  %sqrt10 = call double @llvm.sqrt.f64(double %val10)
+  %sqrt11 = call double @llvm.sqrt.f64(double %val11)
+  %sqrt12 = call double @llvm.sqrt.f64(double %val12)
+  %sqrt13 = call double @llvm.sqrt.f64(double %val13)
+  %sqrt14 = call double @llvm.sqrt.f64(double %val14)
+  %sqrt15 = call double @llvm.sqrt.f64(double %val15)
+  %sqrt16 = call double @llvm.sqrt.f64(double %val16)
+
+  store volatile double %val0, double *%ptr
+  store volatile double %val1, double *%ptr
+  store volatile double %val2, double *%ptr
+  store volatile double %val3, double *%ptr
+  store volatile double %val4, double *%ptr
+  store volatile double %val5, double *%ptr
+  store volatile double %val6, double *%ptr
+  store volatile double %val7, double *%ptr
+  store volatile double %val8, double *%ptr
+  store volatile double %val9, double *%ptr
+  store volatile double %val10, double *%ptr
+  store volatile double %val11, double *%ptr
+  store volatile double %val12, double *%ptr
+  store volatile double %val13, double *%ptr
+  store volatile double %val14, double *%ptr
+  store volatile double %val15, double *%ptr
+  store volatile double %val16, double *%ptr
+
+  store volatile double %sqrt0, double *%ptr
+  store volatile double %sqrt1, double *%ptr
+  store volatile double %sqrt2, double *%ptr
+  store volatile double %sqrt3, double *%ptr
+  store volatile double %sqrt4, double *%ptr
+  store volatile double %sqrt5, double *%ptr
+  store volatile double %sqrt6, double *%ptr
+  store volatile double %sqrt7, double *%ptr
+  store volatile double %sqrt8, double *%ptr
+  store volatile double %sqrt9, double *%ptr
+  store volatile double %sqrt10, double *%ptr
+  store volatile double %sqrt11, double *%ptr
+  store volatile double %sqrt12, double *%ptr
+  store volatile double %sqrt13, double *%ptr
+  store volatile double %sqrt14, double *%ptr
+  store volatile double %sqrt15, double *%ptr
+  store volatile double %sqrt16, double *%ptr
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/fp-sqrt-03.ll b/test/CodeGen/SystemZ/fp-sqrt-03.ll
index 1b49af4..7142644 100644
--- a/test/CodeGen/SystemZ/fp-sqrt-03.ll
+++ b/test/CodeGen/SystemZ/fp-sqrt-03.ll
@@ -6,7 +6,7 @@ declare fp128 @llvm.sqrt.f128(fp128 %f)
 
 ; There's no memory form of SQXBR.
 define void @f1(fp128 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ld %f0, 0(%r2)
 ; CHECK: ld %f2, 8(%r2)
 ; CHECK: sqxbr %f0, %f0
diff --git a/test/CodeGen/SystemZ/fp-sub-01.ll b/test/CodeGen/SystemZ/fp-sub-01.ll
index b03f04b..76f46f6 100644
--- a/test/CodeGen/SystemZ/fp-sub-01.ll
+++ b/test/CodeGen/SystemZ/fp-sub-01.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare float @foo()
+
 ; Check register subtraction.
 define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sebr %f0, %f2
 ; CHECK: br %r14
   %res = fsub float %f1, %f2
@@ -13,7 +15,7 @@ define float @f1(float %f1, float %f2) {
 
 ; Check the low end of the SEB range.
 define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: seb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load float *%ptr
@@ -23,7 +25,7 @@ define float @f2(float %f1, float *%ptr) {
 
 ; Check the high end of the aligned SEB range.
 define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: seb %f0, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr float *%base, i64 1023
@@ -35,7 +37,7 @@ define float @f3(float %f1, float *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: seb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -47,7 +49,7 @@ define float @f4(float %f1, float *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -4
 ; CHECK: seb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -59,7 +61,7 @@ define float @f5(float %f1, float *%base) {
 
 ; Check that SEB allows indices.
 define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 2
 ; CHECK: seb %f0, 400(%r1,%r2)
 ; CHECK: br %r14
@@ -69,3 +71,49 @@ define float @f6(float %f1, float *%base, i64 %index) {
   %res = fsub float %f1, %f2
   ret float %res
 }
+
+; Check that subtractions of spilled values can use SEB rather than SEBR.
+define float @f7(float *%ptr0) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: seb %f0, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr float *%ptr0, i64 2
+  %ptr2 = getelementptr float *%ptr0, i64 4
+  %ptr3 = getelementptr float *%ptr0, i64 6
+  %ptr4 = getelementptr float *%ptr0, i64 8
+  %ptr5 = getelementptr float *%ptr0, i64 10
+  %ptr6 = getelementptr float *%ptr0, i64 12
+  %ptr7 = getelementptr float *%ptr0, i64 14
+  %ptr8 = getelementptr float *%ptr0, i64 16
+  %ptr9 = getelementptr float *%ptr0, i64 18
+  %ptr10 = getelementptr float *%ptr0, i64 20
+
+  %val0 = load float *%ptr0
+  %val1 = load float *%ptr1
+  %val2 = load float *%ptr2
+  %val3 = load float *%ptr3
+  %val4 = load float *%ptr4
+  %val5 = load float *%ptr5
+  %val6 = load float *%ptr6
+  %val7 = load float *%ptr7
+  %val8 = load float *%ptr8
+  %val9 = load float *%ptr9
+  %val10 = load float *%ptr10
+
+  %ret = call float @foo()
+
+  %sub0 = fsub float %ret, %val0
+  %sub1 = fsub float %sub0, %val1
+  %sub2 = fsub float %sub1, %val2
+  %sub3 = fsub float %sub2, %val3
+  %sub4 = fsub float %sub3, %val4
+  %sub5 = fsub float %sub4, %val5
+  %sub6 = fsub float %sub5, %val6
+  %sub7 = fsub float %sub6, %val7
+  %sub8 = fsub float %sub7, %val8
+  %sub9 = fsub float %sub8, %val9
+  %sub10 = fsub float %sub9, %val10
+
+  ret float %sub10
+}
diff --git a/test/CodeGen/SystemZ/fp-sub-02.ll b/test/CodeGen/SystemZ/fp-sub-02.ll
index bf9848c..99cafed 100644
--- a/test/CodeGen/SystemZ/fp-sub-02.ll
+++ b/test/CodeGen/SystemZ/fp-sub-02.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare double @foo()
+
 ; Check register subtraction.
 define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sdbr %f0, %f2
 ; CHECK: br %r14
   %res = fsub double %f1, %f2
@@ -13,7 +15,7 @@ define double @f1(double %f1, double %f2) {
 
 ; Check the low end of the SDB range.
 define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sdb %f0, 0(%r2)
 ; CHECK: br %r14
   %f2 = load double *%ptr
@@ -23,7 +25,7 @@ define double @f2(double %f1, double *%ptr) {
 
 ; Check the high end of the aligned SDB range.
 define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sdb %f0, 4088(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr double *%base, i64 511
@@ -35,7 +37,7 @@ define double @f3(double %f1, double *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: sdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -47,7 +49,7 @@ define double @f4(double %f1, double *%base) {
 
 ; Check negative displacements, which also need separate address logic.
 define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -8
 ; CHECK: sdb %f0, 0(%r2)
 ; CHECK: br %r14
@@ -59,7 +61,7 @@ define double @f5(double %f1, double *%base) {
 
 ; Check that SDB allows indices.
 define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r1, %r3, 3
 ; CHECK: sdb %f0, 800(%r1,%r2)
 ; CHECK: br %r14
@@ -69,3 +71,49 @@ define double @f6(double %f1, double *%base, i64 %index) {
   %res = fsub double %f1, %f2
   ret double %res
 }
+
+; Check that subtractions of spilled values can use SDB rather than SDBR.
+define double @f7(double *%ptr0) {
+; CHECK-LABEL: f7:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: sdb %f0, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr double *%ptr0, i64 2
+  %ptr2 = getelementptr double *%ptr0, i64 4
+  %ptr3 = getelementptr double *%ptr0, i64 6
+  %ptr4 = getelementptr double *%ptr0, i64 8
+  %ptr5 = getelementptr double *%ptr0, i64 10
+  %ptr6 = getelementptr double *%ptr0, i64 12
+  %ptr7 = getelementptr double *%ptr0, i64 14
+  %ptr8 = getelementptr double *%ptr0, i64 16
+  %ptr9 = getelementptr double *%ptr0, i64 18
+  %ptr10 = getelementptr double *%ptr0, i64 20
+
+  %val0 = load double *%ptr0
+  %val1 = load double *%ptr1
+  %val2 = load double *%ptr2
+  %val3 = load double *%ptr3
+  %val4 = load double *%ptr4
+  %val5 = load double *%ptr5
+  %val6 = load double *%ptr6
+  %val7 = load double *%ptr7
+  %val8 = load double *%ptr8
+  %val9 = load double *%ptr9
+  %val10 = load double *%ptr10
+
+  %ret = call double @foo()
+
+  %sub0 = fsub double %ret, %val0
+  %sub1 = fsub double %sub0, %val1
+  %sub2 = fsub double %sub1, %val2
+  %sub3 = fsub double %sub2, %val3
+  %sub4 = fsub double %sub3, %val4
+  %sub5 = fsub double %sub4, %val5
+  %sub6 = fsub double %sub5, %val6
+  %sub7 = fsub double %sub6, %val7
+  %sub8 = fsub double %sub7, %val8
+  %sub9 = fsub double %sub8, %val9
+  %sub10 = fsub double %sub9, %val10
+
+  ret double %sub10
+}
diff --git a/test/CodeGen/SystemZ/fp-sub-03.ll b/test/CodeGen/SystemZ/fp-sub-03.ll
index 82bb94d..a1404c4 100644
--- a/test/CodeGen/SystemZ/fp-sub-03.ll
+++ b/test/CodeGen/SystemZ/fp-sub-03.ll
@@ -4,7 +4,7 @@
 
 ; There is no memory form of 128-bit subtraction.
 define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lxebr %f0, %f0
 ; CHECK: ld %f1, 0(%r2)
 ; CHECK: ld %f3, 8(%r2)
diff --git a/test/CodeGen/SystemZ/frame-01.ll b/test/CodeGen/SystemZ/frame-01.ll
index 0d34312..f61836c 100644
--- a/test/CodeGen/SystemZ/frame-01.ll
+++ b/test/CodeGen/SystemZ/frame-01.ll
@@ -3,9 +3,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare void @foo(i32 *)
+
 ; The CFA offset is 160 (the caller-allocated part of the frame) + 168.
 define void @f1(i64 %x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aghi %r15, -168
 ; CHECK: .cfi_def_cfa_offset 328
 ; CHECK: stg %r2, 160(%r15)
@@ -18,18 +20,18 @@ define void @f1(i64 %x) {
 
 ; Check frames of size 32760, which is the largest size that can be both
 ; allocated and freed using AGHI.  This size is big enough to require
-; an emergency spill slot at 160(%r15), for instructions with unsigned
+; two emergency spill slots at 160(%r15), for instructions with unsigned
 ; 12-bit offsets that end up being out of range.  Fill the remaining
-; 32760 - 168 bytes by allocating (32760 - 168) / 8 = 4074 doublewords.
+; 32760 - 176 bytes by allocating (32760 - 176) / 8 = 4073 doublewords.
 define void @f2(i64 %x) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r15, -32760
 ; CHECK: .cfi_def_cfa_offset 32920
-; CHECK: stg %r2, 168(%r15)
+; CHECK: stg %r2, 176(%r15)
 ; CHECK: aghi %r15, 32760
 ; CHECK: br %r14
-  %y = alloca [4074 x i64], align 8
-  %ptr = getelementptr inbounds [4074 x i64]* %y, i64 0, i64 0
+  %y = alloca [4073 x i64], align 8
+  %ptr = getelementptr inbounds [4073 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
@@ -37,14 +39,14 @@ define void @f2(i64 %x) {
 ; Allocate one more doubleword.  This is the one frame size that we can
 ; allocate using AGHI but must free using AGFI.
 define void @f3(i64 %x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r15, -32768
 ; CHECK: .cfi_def_cfa_offset 32928
-; CHECK: stg %r2, 168(%r15)
+; CHECK: stg %r2, 176(%r15)
 ; CHECK: agfi %r15, 32768
 ; CHECK: br %r14
-  %y = alloca [4075 x i64], align 8
-  %ptr = getelementptr inbounds [4075 x i64]* %y, i64 0, i64 0
+  %y = alloca [4074 x i64], align 8
+  %ptr = getelementptr inbounds [4074 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
@@ -52,14 +54,14 @@ define void @f3(i64 %x) {
 ; Allocate another doubleword on top of that.  The allocation and free
 ; must both use AGFI.
 define void @f4(i64 %x) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r15, -32776
 ; CHECK: .cfi_def_cfa_offset 32936
-; CHECK: stg %r2, 168(%r15)
+; CHECK: stg %r2, 176(%r15)
 ; CHECK: agfi %r15, 32776
 ; CHECK: br %r14
-  %y = alloca [4076 x i64], align 8
-  %ptr = getelementptr inbounds [4076 x i64]* %y, i64 0, i64 0
+  %y = alloca [4075 x i64], align 8
+  %ptr = getelementptr inbounds [4075 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
@@ -67,13 +69,13 @@ define void @f4(i64 %x) {
 ; The largest size that can be both allocated and freed using AGFI.
 ; At this point the frame is too big to represent properly in the CFI.
 define void @f5(i64 %x) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r15, -2147483640
-; CHECK: stg %r2, 168(%r15)
+; CHECK: stg %r2, 176(%r15)
 ; CHECK: agfi %r15, 2147483640
 ; CHECK: br %r14
-  %y = alloca [268435434 x i64], align 8
-  %ptr = getelementptr inbounds [268435434 x i64]* %y, i64 0, i64 0
+  %y = alloca [268435433 x i64], align 8
+  %ptr = getelementptr inbounds [268435433 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
@@ -81,14 +83,14 @@ define void @f5(i64 %x) {
 ; The only frame size that can be allocated using a single AGFI but which
 ; must be freed using two instructions.
 define void @f6(i64 %x) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r15, -2147483648
-; CHECK: stg %r2, 168(%r15)
+; CHECK: stg %r2, 176(%r15)
 ; CHECK: agfi %r15, 2147483640
 ; CHECK: aghi %r15, 8
 ; CHECK: br %r14
-  %y = alloca [268435435 x i64], align 8
-  %ptr = getelementptr inbounds [268435435 x i64]* %y, i64 0, i64 0
+  %y = alloca [268435434 x i64], align 8
+  %ptr = getelementptr inbounds [268435434 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
@@ -96,15 +98,29 @@ define void @f6(i64 %x) {
 ; The smallest frame size that needs two instructions to both allocate
 ; and free the frame.
 define void @f7(i64 %x) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r15, -2147483648
 ; CHECK: aghi %r15, -8
-; CHECK: stg %r2, 168(%r15)
+; CHECK: stg %r2, 176(%r15)
 ; CHECK: agfi %r15, 2147483640
 ; CHECK: aghi %r15, 16
 ; CHECK: br %r14
-  %y = alloca [268435436 x i64], align 8
-  %ptr = getelementptr inbounds [268435436 x i64]* %y, i64 0, i64 0
+  %y = alloca [268435435 x i64], align 8
+  %ptr = getelementptr inbounds [268435435 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
+
+; Make sure that LA can be rematerialized.
+define void @f8() {
+; CHECK-LABEL: f8:
+; CHECK: la %r2, 164(%r15)
+; CHECK: brasl %r14, foo@PLT
+; CHECK: la %r2, 164(%r15)
+; CHECK: brasl %r14, foo@PLT
+; CHECK: br %r14
+  %ptr = alloca i32
+  call void @foo(i32 *%ptr)
+  call void @foo(i32 *%ptr)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/frame-02.ll b/test/CodeGen/SystemZ/frame-02.ll
index 589703e..9a7f8ea 100644
--- a/test/CodeGen/SystemZ/frame-02.ll
+++ b/test/CodeGen/SystemZ/frame-02.ll
@@ -7,7 +7,7 @@
 ; should be exactly 160 + 8 * 8 = 224.  The CFA offset is 160
 ; (the caller-allocated part of the frame) + 224.
 define void @f1(float *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aghi %r15, -224
 ; CHECK: .cfi_def_cfa_offset 384
 ; CHECK: std %f8, 216(%r15)
@@ -91,7 +91,7 @@ define void @f1(float *%ptr) {
 ; Like f1, but requires one fewer FPR.  We allocate in numerical order,
 ; so %f15 is the one that gets dropped.
 define void @f2(float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r15, -216
 ; CHECK: .cfi_def_cfa_offset 376
 ; CHECK: std %f8, 208(%r15)
@@ -169,7 +169,7 @@ define void @f2(float *%ptr) {
 
 ; Like f1, but should require only one call-saved FPR.
 define void @f3(float *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r15, -168
 ; CHECK: .cfi_def_cfa_offset 328
 ; CHECK: std %f8, 160(%r15)
@@ -218,7 +218,7 @@ define void @f3(float *%ptr) {
 ; This function should use all call-clobbered FPRs but no call-saved ones.
 ; It shouldn't need to create a frame.
 define void @f4(float *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %f8
 ; CHECK-NOT: %f9
diff --git a/test/CodeGen/SystemZ/frame-03.ll b/test/CodeGen/SystemZ/frame-03.ll
index 3c4a499..db146c7 100644
--- a/test/CodeGen/SystemZ/frame-03.ll
+++ b/test/CodeGen/SystemZ/frame-03.ll
@@ -9,7 +9,7 @@
 ; should be exactly 160 + 8 * 8 = 224.  The CFA offset is 160
 ; (the caller-allocated part of the frame) + 224.
 define void @f1(double *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aghi %r15, -224
 ; CHECK: .cfi_def_cfa_offset 384
 ; CHECK: std %f8, 216(%r15)
@@ -93,7 +93,7 @@ define void @f1(double *%ptr) {
 ; Like f1, but requires one fewer FPR.  We allocate in numerical order,
 ; so %f15 is the one that gets dropped.
 define void @f2(double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r15, -216
 ; CHECK: .cfi_def_cfa_offset 376
 ; CHECK: std %f8, 208(%r15)
@@ -171,7 +171,7 @@ define void @f2(double *%ptr) {
 
 ; Like f1, but should require only one call-saved FPR.
 define void @f3(double *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r15, -168
 ; CHECK: .cfi_def_cfa_offset 328
 ; CHECK: std %f8, 160(%r15)
@@ -220,7 +220,7 @@ define void @f3(double *%ptr) {
 ; This function should use all call-clobbered FPRs but no call-saved ones.
 ; It shouldn't need to create a frame.
 define void @f4(double *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %f8
 ; CHECK-NOT: %f9
diff --git a/test/CodeGen/SystemZ/frame-04.ll b/test/CodeGen/SystemZ/frame-04.ll
index 360f85c..93c59a3 100644
--- a/test/CodeGen/SystemZ/frame-04.ll
+++ b/test/CodeGen/SystemZ/frame-04.ll
@@ -8,7 +8,7 @@
 ; should be exactly 160 + 8 * 8 = 224.  The CFA offset is 160
 ; (the caller-allocated part of the frame) + 224.
 define void @f1(fp128 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aghi %r15, -224
 ; CHECK: .cfi_def_cfa_offset 384
 ; CHECK: std %f8, 216(%r15)
@@ -68,7 +68,7 @@ define void @f1(fp128 *%ptr) {
 ; Like f1, but requires one fewer FPR pair.  We allocate in numerical order,
 ; so %f13+%f15 is the pair that gets dropped.
 define void @f2(fp128 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r15, -208
 ; CHECK: .cfi_def_cfa_offset 368
 ; CHECK: std %f8, 200(%r15)
@@ -121,7 +121,7 @@ define void @f2(fp128 *%ptr) {
 ; Like f1, but requires only one call-saved FPR pair.  We allocate in
 ; numerical order so the pair should be %f8+%f10.
 define void @f3(fp128 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r15, -176
 ; CHECK: .cfi_def_cfa_offset 336
 ; CHECK: std %f8, 168(%r15)
@@ -160,7 +160,7 @@ define void @f3(fp128 *%ptr) {
 ; This function should use all call-clobbered FPRs but no call-saved ones.
 ; It shouldn't need to create a frame.
 define void @f4(fp128 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %f8
 ; CHECK-NOT: %f9
diff --git a/test/CodeGen/SystemZ/frame-05.ll b/test/CodeGen/SystemZ/frame-05.ll
index 3a159fc..f95284d 100644
--- a/test/CodeGen/SystemZ/frame-05.ll
+++ b/test/CodeGen/SystemZ/frame-05.ll
@@ -14,7 +14,7 @@
 ; Use a different address for the final store, so that we can check that
 ; %r15 isn't referenced again until after that.
 define void @f1(i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r6, -112
@@ -82,7 +82,7 @@ define void @f1(i32 *%ptr) {
 ; from %r14 down, so that the STMG/LMG sequences aren't any longer than
 ; they need to be.
 define void @f2(i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stmg %r7, %r15, 56(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r7, -104
@@ -145,7 +145,7 @@ define void @f2(i32 *%ptr) {
 
 ; Like f1, but only needs one call-saved GPR, which ought to be %r14.
 define void @f3(i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r14, -48
@@ -188,7 +188,7 @@ define void @f3(i32 *%ptr) {
 ; This function should use all call-clobbered GPRs but no call-saved ones.
 ; It shouldn't need to touch the stack at all.
 define void @f4(i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %r6
 ; CHECK-NOT: %r7
diff --git a/test/CodeGen/SystemZ/frame-06.ll b/test/CodeGen/SystemZ/frame-06.ll
index 4c361f1..ad22f10 100644
--- a/test/CodeGen/SystemZ/frame-06.ll
+++ b/test/CodeGen/SystemZ/frame-06.ll
@@ -11,7 +11,7 @@
 ; Use a different address for the final store, so that we can check that
 ; %r15 isn't referenced again until after that.
 define void @f1(i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r6, -112
@@ -79,7 +79,7 @@ define void @f1(i64 *%ptr) {
 ; from %r14 down, so that the STMG/LMG sequences aren't any longer than
 ; they need to be.
 define void @f2(i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stmg %r7, %r15, 56(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r7, -104
@@ -142,7 +142,7 @@ define void @f2(i64 *%ptr) {
 
 ; Like f1, but only needs one call-saved GPR, which ought to be %r14.
 define void @f3(i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK-NOT: %r15
 ; CHECK: .cfi_offset %r14, -48
@@ -185,7 +185,7 @@ define void @f3(i64 *%ptr) {
 ; This function should use all call-clobbered GPRs but no call-saved ones.
 ; It shouldn't need to touch the stack at all.
 define void @f4(i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %r6
 ; CHECK-NOT: %r7
diff --git a/test/CodeGen/SystemZ/frame-07.ll b/test/CodeGen/SystemZ/frame-07.ll
index cfe9f86..eab3137 100644
--- a/test/CodeGen/SystemZ/frame-07.ll
+++ b/test/CodeGen/SystemZ/frame-07.ll
@@ -5,11 +5,11 @@
 
 ; Test a frame size that requires some FPRs to be saved and loaded using
 ; the 20-bit STDY and LDY while others can use the 12-bit STD and LD.
-; The frame is big enough to require an emergency spill slot at 160(%r15),
+; The frame is big enough to require two emergency spill slots at 160(%r15),
 ; as well as the 8 FPR save slots.  Get a frame of size 4128 by allocating
-; (4128 - 168 - 8 * 8) / 8 = 487 extra doublewords.
+; (4128 - 176 - 8 * 8) / 8 = 486 extra doublewords.
 define void @f1(double *%ptr, i64 %x) {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
 ; CHECK-NOFP: aghi %r15, -4128
 ; CHECK-NOFP: .cfi_def_cfa_offset 4288
 ; CHECK-NOFP: stdy %f8, 4120(%r15)
@@ -40,7 +40,7 @@ define void @f1(double *%ptr, i64 %x) {
 ; CHECK-NOFP: aghi %r15, 4128
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: stmg %r11, %r15, 88(%r15)
 ; CHECK-FP: aghi %r15, -4128
 ; CHECK-FP: .cfi_def_cfa_offset 4288
@@ -65,8 +65,8 @@ define void @f1(double *%ptr, i64 %x) {
 ; CHECK-FP: ld %f15, 4064(%r11)
 ; CHECK-FP: lmg %r11, %r15, 4216(%r11)
 ; CHECK-FP: br %r14
-  %y = alloca [487 x i64], align 8
-  %elem = getelementptr inbounds [487 x i64]* %y, i64 0, i64 0
+  %y = alloca [486 x i64], align 8
+  %elem = getelementptr inbounds [486 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %elem
   %l0 = load volatile double *%ptr
   %l1 = load volatile double *%ptr
@@ -127,9 +127,9 @@ define void @f1(double *%ptr, i64 %x) {
 ; good optimisation but is really a different test.
 ;
 ; As above, get a frame of size 524320 by allocating
-; (524320 - 168 - 8 * 8) / 8 = 65511 extra doublewords.
+; (524320 - 176 - 8 * 8) / 8 = 65510 extra doublewords.
 define void @f2(double *%ptr, i64 %x) {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
 ; CHECK-NOFP: agfi %r15, -524320
 ; CHECK-NOFP: .cfi_def_cfa_offset 524480
 ; CHECK-NOFP: llilh [[INDEX:%r[1-5]]], 8
@@ -161,7 +161,7 @@ define void @f2(double *%ptr, i64 %x) {
 ; CHECK-NOFP: agfi %r15, 524320
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
 ; CHECK-FP: stmg %r11, %r15, 88(%r15)
 ; CHECK-FP: agfi %r15, -524320
 ; CHECK-FP: .cfi_def_cfa_offset 524480
@@ -194,8 +194,8 @@ define void @f2(double *%ptr, i64 %x) {
 ; CHECK-FP: aghi %r11, 128
 ; CHECK-FP: lmg %r11, %r15, 524280(%r11)
 ; CHECK-FP: br %r14
-  %y = alloca [65511 x i64], align 8
-  %elem = getelementptr inbounds [65511 x i64]* %y, i64 0, i64 0
+  %y = alloca [65510 x i64], align 8
+  %elem = getelementptr inbounds [65510 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %elem
   %l0 = load volatile double *%ptr
   %l1 = load volatile double *%ptr
diff --git a/test/CodeGen/SystemZ/frame-08.ll b/test/CodeGen/SystemZ/frame-08.ll
index 6cf6378..da2a614 100644
--- a/test/CodeGen/SystemZ/frame-08.ll
+++ b/test/CodeGen/SystemZ/frame-08.ll
@@ -3,11 +3,11 @@
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
 ; This is the largest frame size that can use a plain LMG for %r6 and above.
-; It is big enough to require an emergency spill slot at 160(%r15),
-; so get a frame of size 524232 by allocating (524232 - 168) / 8 = 65508
+; It is big enough to require two emergency spill slots at 160(%r15),
+; so get a frame of size 524232 by allocating (524232 - 176) / 8 = 65507
 ; extra doublewords.
 define void @f1(i32 *%ptr, i64 %x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK: .cfi_offset %r6, -112
 ; CHECK: .cfi_offset %r7, -104
@@ -64,18 +64,18 @@ define void @f1(i32 *%ptr, i64 %x) {
   store volatile i32 %add12, i32 *%ptr
   store volatile i32 %add13, i32 *%ptr
   store volatile i32 %add14, i32 *%ptr
-  %y = alloca [65508 x i64], align 8
-  %entry = getelementptr inbounds [65508 x i64]* %y, i64 0, i64 0
+  %y = alloca [65507 x i64], align 8
+  %entry = getelementptr inbounds [65507 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %entry
   ret void
 }
 
 ; This is the largest frame size that can use a plain LMG for %r14 and above
-; It is big enough to require an emergency spill slot at 160(%r15),
-; so get a frame of size 524168 by allocating (524168 - 168) / 8 = 65500
+; It is big enough to require two emergency spill slots at 160(%r15),
+; so get a frame of size 524168 by allocating (524168 - 176) / 8 = 65499
 ; extra doublewords.
 define void @f2(i32 *%ptr, i64 %x) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: .cfi_offset %r14, -48
 ; CHECK: .cfi_offset %r15, -40
@@ -100,8 +100,8 @@ define void @f2(i32 *%ptr, i64 %x) {
   store volatile i32 %add4, i32 *%ptr
   store volatile i32 %add5, i32 *%ptr
   store volatile i32 %add14, i32 *%ptr
-  %y = alloca [65500 x i64], align 8
-  %entry = getelementptr inbounds [65500 x i64]* %y, i64 0, i64 0
+  %y = alloca [65499 x i64], align 8
+  %entry = getelementptr inbounds [65499 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %entry
   ret void
 }
@@ -110,7 +110,7 @@ define void @f2(i32 *%ptr, i64 %x) {
 ; frame size that needs two instructions to perform the final LMG for
 ; %r6 and above.
 define void @f3(i32 *%ptr, i64 %x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK: .cfi_offset %r6, -112
 ; CHECK: .cfi_offset %r7, -104
@@ -167,8 +167,8 @@ define void @f3(i32 *%ptr, i64 %x) {
   store volatile i32 %add12, i32 *%ptr
   store volatile i32 %add13, i32 *%ptr
   store volatile i32 %add14, i32 *%ptr
-  %y = alloca [65509 x i64], align 8
-  %entry = getelementptr inbounds [65509 x i64]* %y, i64 0, i64 0
+  %y = alloca [65508 x i64], align 8
+  %entry = getelementptr inbounds [65508 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %entry
   ret void
 }
@@ -177,7 +177,7 @@ define void @f3(i32 *%ptr, i64 %x) {
 ; frame size that needs two instructions to perform the final LMG for
 ; %r14 and %r15.
 define void @f4(i32 *%ptr, i64 %x) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: .cfi_offset %r14, -48
 ; CHECK: .cfi_offset %r15, -40
@@ -202,8 +202,8 @@ define void @f4(i32 *%ptr, i64 %x) {
   store volatile i32 %add4, i32 *%ptr
   store volatile i32 %add5, i32 *%ptr
   store volatile i32 %add14, i32 *%ptr
-  %y = alloca [65501 x i64], align 8
-  %entry = getelementptr inbounds [65501 x i64]* %y, i64 0, i64 0
+  %y = alloca [65500 x i64], align 8
+  %entry = getelementptr inbounds [65500 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %entry
   ret void
 }
@@ -211,7 +211,7 @@ define void @f4(i32 *%ptr, i64 %x) {
 ; This is the largest frame size for which the prepatory increment for
 ; "lmg %r14, %r15, ..." can be done using AGHI.
 define void @f5(i32 *%ptr, i64 %x) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: .cfi_offset %r14, -48
 ; CHECK: .cfi_offset %r15, -40
@@ -236,8 +236,8 @@ define void @f5(i32 *%ptr, i64 %x) {
   store volatile i32 %add4, i32 *%ptr
   store volatile i32 %add5, i32 *%ptr
   store volatile i32 %add14, i32 *%ptr
-  %y = alloca [69595 x i64], align 8
-  %entry = getelementptr inbounds [69595 x i64]* %y, i64 0, i64 0
+  %y = alloca [69594 x i64], align 8
+  %entry = getelementptr inbounds [69594 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %entry
   ret void
 }
@@ -245,7 +245,7 @@ define void @f5(i32 *%ptr, i64 %x) {
 ; This is the smallest frame size for which the prepatory increment for
 ; "lmg %r14, %r15, ..." needs to be done using AGFI.
 define void @f6(i32 *%ptr, i64 %x) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: stmg %r14, %r15, 112(%r15)
 ; CHECK: .cfi_offset %r14, -48
 ; CHECK: .cfi_offset %r15, -40
@@ -270,8 +270,8 @@ define void @f6(i32 *%ptr, i64 %x) {
   store volatile i32 %add4, i32 *%ptr
   store volatile i32 %add5, i32 *%ptr
   store volatile i32 %add14, i32 *%ptr
-  %y = alloca [69596 x i64], align 8
-  %entry = getelementptr inbounds [69596 x i64]* %y, i64 0, i64 0
+  %y = alloca [69595 x i64], align 8
+  %entry = getelementptr inbounds [69595 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %entry
   ret void
 }
diff --git a/test/CodeGen/SystemZ/frame-09.ll b/test/CodeGen/SystemZ/frame-09.ll
index eac6336..8a4f99c 100644
--- a/test/CodeGen/SystemZ/frame-09.ll
+++ b/test/CodeGen/SystemZ/frame-09.ll
@@ -6,7 +6,7 @@
 ; We don't need to allocate any more than the caller-provided 160-byte
 ; area though.
 define i32 @f1(i32 %x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: .cfi_offset %r11, -72
 ; CHECK: .cfi_offset %r15, -40
@@ -22,7 +22,7 @@ define i32 @f1(i32 %x) {
 ; Make sure that frame accesses after the initial allocation are relative
 ; to %r11 rather than %r15.
 define void @f2(i64 %x) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: .cfi_offset %r11, -72
 ; CHECK: .cfi_offset %r15, -40
@@ -41,7 +41,7 @@ define void @f2(i64 %x) {
 ; This function should require all GPRs but no other spill slots.
 ; It shouldn't need to allocate its own frame.
 define void @f3(i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK-NOT: %r15
 ; CHECK-NOT: %r11
@@ -107,11 +107,11 @@ define void @f3(i32 *%ptr) {
   ret void
 }
 
-; The largest frame for which the LMG is in range.  This frame has an
-; emergency spill slot at 160(%r11), so create a frame of size 524192
-; by allocating (524192 - 168) / 8 = 65503 doublewords.
+; The largest frame for which the LMG is in range.  This frame has two
+; emergency spill slots at 160(%r11), so create a frame of size 524192
+; by allocating (524192 - 176) / 8 = 65502 doublewords.
 define void @f4(i64 %x) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: .cfi_offset %r11, -72
 ; CHECK: .cfi_offset %r15, -40
@@ -119,19 +119,19 @@ define void @f4(i64 %x) {
 ; CHECK: .cfi_def_cfa_offset 524352
 ; CHECK: lgr %r11, %r15
 ; CHECK: .cfi_def_cfa_register %r11
-; CHECK: stg %r2, 168(%r11)
+; CHECK: stg %r2, 176(%r11)
 ; CHECK-NOT: ag
 ; CHECK: lmg %r11, %r15, 524280(%r11)
 ; CHECK: br %r14
-  %y = alloca [65503 x i64], align 8
-  %ptr = getelementptr inbounds [65503 x i64]* %y, i64 0, i64 0
+  %y = alloca [65502 x i64], align 8
+  %ptr = getelementptr inbounds [65502 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
 
 ; The next frame size larger than f4.
 define void @f5(i64 %x) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: .cfi_offset %r11, -72
 ; CHECK: .cfi_offset %r15, -40
@@ -139,12 +139,12 @@ define void @f5(i64 %x) {
 ; CHECK: .cfi_def_cfa_offset 524360
 ; CHECK: lgr %r11, %r15
 ; CHECK: .cfi_def_cfa_register %r11
-; CHECK: stg %r2, 168(%r11)
+; CHECK: stg %r2, 176(%r11)
 ; CHECK: aghi %r11, 8
 ; CHECK: lmg %r11, %r15, 524280(%r11)
 ; CHECK: br %r14
-  %y = alloca [65504 x i64], align 8
-  %ptr = getelementptr inbounds [65504 x i64]* %y, i64 0, i64 0
+  %y = alloca [65503 x i64], align 8
+  %ptr = getelementptr inbounds [65503 x i64]* %y, i64 0, i64 0
   store volatile i64 %x, i64* %ptr
   ret void
 }
diff --git a/test/CodeGen/SystemZ/frame-10.ll b/test/CodeGen/SystemZ/frame-10.ll
index 399a412..b96973a 100644
--- a/test/CodeGen/SystemZ/frame-10.ll
+++ b/test/CodeGen/SystemZ/frame-10.ll
@@ -5,7 +5,7 @@
 declare i8 *@llvm.stacksave()
 
 define void @f1(i8 **%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stg %r15, 0(%r2)
 ; CHECK: br %r14
   %addr = call i8 *@llvm.stacksave()
diff --git a/test/CodeGen/SystemZ/frame-11.ll b/test/CodeGen/SystemZ/frame-11.ll
index 8422205..5145b4d 100644
--- a/test/CodeGen/SystemZ/frame-11.ll
+++ b/test/CodeGen/SystemZ/frame-11.ll
@@ -7,7 +7,7 @@ declare void @llvm.stackrestore(i8 *)
 ; we should use a frame pointer and tear down the frame based on %r11
 ; rather than %r15.
 define void @f1(i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r11, %r15, 88(%r15)
 ; CHECK: lgr %r11, %r15
 ; CHECK: lgr %r15, %r2
diff --git a/test/CodeGen/SystemZ/frame-13.ll b/test/CodeGen/SystemZ/frame-13.ll
index fa6b845..1d38354 100644
--- a/test/CodeGen/SystemZ/frame-13.ll
+++ b/test/CodeGen/SystemZ/frame-13.ll
@@ -17,22 +17,22 @@
 ; First check the highest in-range offset after conversion, which is 4092
 ; for word-addressing instructions like MVHI.
 ;
-; The last in-range doubleword offset is 4088.  Since the frame has an
-; emergency spill slot at 160(%r15), the amount that we need to allocate
-; in order to put another object at offset 4088 is (4088 - 168) / 4 = 980
+; The last in-range doubleword offset is 4088.  Since the frame has two
+; emergency spill slots at 160(%r15), the amount that we need to allocate
+; in order to put another object at offset 4088 is (4088 - 176) / 4 = 978
 ; words.
 define void @f1() {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
 ; CHECK-NOFP: mvhi 4092(%r15), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: mvhi 4092(%r11), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [980 x i32], align 8
-  %region2 = alloca [980 x i32], align 8
-  %ptr1 = getelementptr inbounds [980 x i32]* %region1, i64 0, i64 1
-  %ptr2 = getelementptr inbounds [980 x i32]* %region2, i64 0, i64 1
+  %region1 = alloca [978 x i32], align 8
+  %region2 = alloca [978 x i32], align 8
+  %ptr1 = getelementptr inbounds [978 x i32]* %region1, i64 0, i64 1
+  %ptr2 = getelementptr inbounds [978 x i32]* %region2, i64 0, i64 1
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -40,19 +40,19 @@ define void @f1() {
 
 ; Test the first out-of-range offset.  We cannot use an index register here.
 define void @f2() {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
 ; CHECK-NOFP: lay %r1, 4096(%r15)
 ; CHECK-NOFP: mvhi 0(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
 ; CHECK-FP: lay %r1, 4096(%r11)
 ; CHECK-FP: mvhi 0(%r1), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [980 x i32], align 8
-  %region2 = alloca [980 x i32], align 8
-  %ptr1 = getelementptr inbounds [980 x i32]* %region1, i64 0, i64 2
-  %ptr2 = getelementptr inbounds [980 x i32]* %region2, i64 0, i64 2
+  %region1 = alloca [978 x i32], align 8
+  %region2 = alloca [978 x i32], align 8
+  %ptr1 = getelementptr inbounds [978 x i32]* %region1, i64 0, i64 2
+  %ptr2 = getelementptr inbounds [978 x i32]* %region2, i64 0, i64 2
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -60,19 +60,19 @@ define void @f2() {
 
 ; Test the next offset after that.
 define void @f3() {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
 ; CHECK-NOFP: lay %r1, 4096(%r15)
 ; CHECK-NOFP: mvhi 4(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
 ; CHECK-FP: lay %r1, 4096(%r11)
 ; CHECK-FP: mvhi 4(%r1), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [980 x i32], align 8
-  %region2 = alloca [980 x i32], align 8
-  %ptr1 = getelementptr inbounds [980 x i32]* %region1, i64 0, i64 3
-  %ptr2 = getelementptr inbounds [980 x i32]* %region2, i64 0, i64 3
+  %region1 = alloca [978 x i32], align 8
+  %region2 = alloca [978 x i32], align 8
+  %ptr1 = getelementptr inbounds [978 x i32]* %region1, i64 0, i64 3
+  %ptr2 = getelementptr inbounds [978 x i32]* %region2, i64 0, i64 3
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -80,19 +80,19 @@ define void @f3() {
 
 ; Add 4096 bytes (1024 words) to the size of each object and repeat.
 define void @f4() {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
 ; CHECK-NOFP: lay %r1, 4096(%r15)
 ; CHECK-NOFP: mvhi 4092(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
 ; CHECK-FP: lay %r1, 4096(%r11)
 ; CHECK-FP: mvhi 4092(%r1), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [2004 x i32], align 8
-  %region2 = alloca [2004 x i32], align 8
-  %ptr1 = getelementptr inbounds [2004 x i32]* %region1, i64 0, i64 1
-  %ptr2 = getelementptr inbounds [2004 x i32]* %region2, i64 0, i64 1
+  %region1 = alloca [2002 x i32], align 8
+  %region2 = alloca [2002 x i32], align 8
+  %ptr1 = getelementptr inbounds [2002 x i32]* %region1, i64 0, i64 1
+  %ptr2 = getelementptr inbounds [2002 x i32]* %region2, i64 0, i64 1
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -100,19 +100,19 @@ define void @f4() {
 
 ; ...as above.
 define void @f5() {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
 ; CHECK-NOFP: lay %r1, 8192(%r15)
 ; CHECK-NOFP: mvhi 0(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
 ; CHECK-FP: lay %r1, 8192(%r11)
 ; CHECK-FP: mvhi 0(%r1), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [2004 x i32], align 8
-  %region2 = alloca [2004 x i32], align 8
-  %ptr1 = getelementptr inbounds [2004 x i32]* %region1, i64 0, i64 2
-  %ptr2 = getelementptr inbounds [2004 x i32]* %region2, i64 0, i64 2
+  %region1 = alloca [2002 x i32], align 8
+  %region2 = alloca [2002 x i32], align 8
+  %ptr1 = getelementptr inbounds [2002 x i32]* %region1, i64 0, i64 2
+  %ptr2 = getelementptr inbounds [2002 x i32]* %region2, i64 0, i64 2
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -120,41 +120,41 @@ define void @f5() {
 
 ; ...as above.
 define void @f6() {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
 ; CHECK-NOFP: lay %r1, 8192(%r15)
 ; CHECK-NOFP: mvhi 4(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
 ; CHECK-FP: lay %r1, 8192(%r11)
 ; CHECK-FP: mvhi 4(%r1), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [2004 x i32], align 8
-  %region2 = alloca [2004 x i32], align 8
-  %ptr1 = getelementptr inbounds [2004 x i32]* %region1, i64 0, i64 3
-  %ptr2 = getelementptr inbounds [2004 x i32]* %region2, i64 0, i64 3
+  %region1 = alloca [2002 x i32], align 8
+  %region2 = alloca [2002 x i32], align 8
+  %ptr1 = getelementptr inbounds [2002 x i32]* %region1, i64 0, i64 3
+  %ptr2 = getelementptr inbounds [2002 x i32]* %region2, i64 0, i64 3
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
 }
 
 ; Now try an offset of 4092 from the start of the object, with the object
-; being at offset 8192.  This time we need objects of (8192 - 168) / 4 = 2006
+; being at offset 8192.  This time we need objects of (8192 - 176) / 4 = 2004
 ; words.
 define void @f7() {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
 ; CHECK-NOFP: lay %r1, 8192(%r15)
 ; CHECK-NOFP: mvhi 4092(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
 ; CHECK-FP: lay %r1, 8192(%r11)
 ; CHECK-FP: mvhi 4092(%r1), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [2006 x i32], align 8
-  %region2 = alloca [2006 x i32], align 8
-  %ptr1 = getelementptr inbounds [2006 x i32]* %region1, i64 0, i64 1023
-  %ptr2 = getelementptr inbounds [2006 x i32]* %region2, i64 0, i64 1023
+  %region1 = alloca [2004 x i32], align 8
+  %region2 = alloca [2004 x i32], align 8
+  %ptr1 = getelementptr inbounds [2004 x i32]* %region1, i64 0, i64 1023
+  %ptr2 = getelementptr inbounds [2004 x i32]* %region2, i64 0, i64 1023
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -163,19 +163,19 @@ define void @f7() {
 ; Keep the object-relative offset the same but bump the size of the
 ; objects by one doubleword.
 define void @f8() {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
 ; CHECK-NOFP: lay %r1, 12288(%r15)
 ; CHECK-NOFP: mvhi 4(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
 ; CHECK-FP: lay %r1, 12288(%r11)
 ; CHECK-FP: mvhi 4(%r1), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [2008 x i32], align 8
-  %region2 = alloca [2008 x i32], align 8
-  %ptr1 = getelementptr inbounds [2008 x i32]* %region1, i64 0, i64 1023
-  %ptr2 = getelementptr inbounds [2008 x i32]* %region2, i64 0, i64 1023
+  %region1 = alloca [2006 x i32], align 8
+  %region2 = alloca [2006 x i32], align 8
+  %ptr1 = getelementptr inbounds [2006 x i32]* %region1, i64 0, i64 1023
+  %ptr2 = getelementptr inbounds [2006 x i32]* %region2, i64 0, i64 1023
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
@@ -185,50 +185,50 @@ define void @f8() {
 ; should force an LAY from the outset.  We don't yet do any kind of anchor
 ; optimization, so there should be no offset on the MVHI itself.
 define void @f9() {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
 ; CHECK-NOFP: lay %r1, 12296(%r15)
 ; CHECK-NOFP: mvhi 0(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
 ; CHECK-FP: lay %r1, 12296(%r11)
 ; CHECK-FP: mvhi 0(%r1), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [2008 x i32], align 8
-  %region2 = alloca [2008 x i32], align 8
-  %ptr1 = getelementptr inbounds [2008 x i32]* %region1, i64 0, i64 1024
-  %ptr2 = getelementptr inbounds [2008 x i32]* %region2, i64 0, i64 1024
+  %region1 = alloca [2006 x i32], align 8
+  %region2 = alloca [2006 x i32], align 8
+  %ptr1 = getelementptr inbounds [2006 x i32]* %region1, i64 0, i64 1024
+  %ptr2 = getelementptr inbounds [2006 x i32]* %region2, i64 0, i64 1024
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   ret void
 }
 
-; Repeat f2 in a case that needs the emergency spill slot (because all
+; Repeat f2 in a case that needs the emergency spill slots (because all
 ; call-clobbered registers are live and no call-saved ones have been
 ; allocated).
 define void @f10(i32 *%vptr) {
-; CHECK-NOFP: f10:
-; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15)
+; CHECK-NOFP-LABEL: f10:
+; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: lay [[REGISTER]], 4096(%r15)
 ; CHECK-NOFP: mvhi 0([[REGISTER]]), 42
-; CHECK-NOFP: lg [[REGISTER]], 160(%r15)
+; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f10:
-; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11)
+; CHECK-FP-LABEL: f10:
+; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: lay [[REGISTER]], 4096(%r11)
 ; CHECK-FP: mvhi 0([[REGISTER]]), 42
-; CHECK-FP: lg [[REGISTER]], 160(%r11)
+; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
 ; CHECK-FP: br %r14
   %i0 = load volatile i32 *%vptr
   %i1 = load volatile i32 *%vptr
   %i3 = load volatile i32 *%vptr
   %i4 = load volatile i32 *%vptr
   %i5 = load volatile i32 *%vptr
-  %region1 = alloca [980 x i32], align 8
-  %region2 = alloca [980 x i32], align 8
-  %ptr1 = getelementptr inbounds [980 x i32]* %region1, i64 0, i64 2
-  %ptr2 = getelementptr inbounds [980 x i32]* %region2, i64 0, i64 2
+  %region1 = alloca [978 x i32], align 8
+  %region2 = alloca [978 x i32], align 8
+  %ptr1 = getelementptr inbounds [978 x i32]* %region1, i64 0, i64 2
+  %ptr2 = getelementptr inbounds [978 x i32]* %region2, i64 0, i64 2
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   store volatile i32 %i0, i32 *%vptr
@@ -239,26 +239,26 @@ define void @f10(i32 *%vptr) {
   ret void
 }
 
-; And again with maximum register pressure.  The only spill slot that the
-; NOFP case needs is the emergency one, so the offsets are the same as for f2.
+; And again with maximum register pressure.  The only spill slots that the
+; NOFP case needs are the emergency ones, so the offsets are the same as for f2.
 ; However, the FP case uses %r11 as the frame pointer and must therefore
 ; spill a second register.  This leads to an extra displacement of 8.
 define void @f11(i32 *%vptr) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
 ; CHECK-NOFP: stmg %r6, %r15,
-; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15)
+; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: lay [[REGISTER]], 4096(%r15)
 ; CHECK-NOFP: mvhi 0([[REGISTER]]), 42
-; CHECK-NOFP: lg [[REGISTER]], 160(%r15)
+; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: lmg %r6, %r15,
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
 ; CHECK-FP: stmg %r6, %r15,
-; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11)
+; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: lay [[REGISTER]], 4096(%r11)
 ; CHECK-FP: mvhi 8([[REGISTER]]), 42
-; CHECK-FP: lg [[REGISTER]], 160(%r11)
+; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
 ; CHECK-FP: lmg %r6, %r15,
 ; CHECK-FP: br %r14
   %i0 = load volatile i32 *%vptr
@@ -275,10 +275,10 @@ define void @f11(i32 *%vptr) {
   %i12 = load volatile i32 *%vptr
   %i13 = load volatile i32 *%vptr
   %i14 = load volatile i32 *%vptr
-  %region1 = alloca [980 x i32], align 8
-  %region2 = alloca [980 x i32], align 8
-  %ptr1 = getelementptr inbounds [980 x i32]* %region1, i64 0, i64 2
-  %ptr2 = getelementptr inbounds [980 x i32]* %region2, i64 0, i64 2
+  %region1 = alloca [978 x i32], align 8
+  %region2 = alloca [978 x i32], align 8
+  %ptr1 = getelementptr inbounds [978 x i32]* %region1, i64 0, i64 2
+  %ptr2 = getelementptr inbounds [978 x i32]* %region2, i64 0, i64 2
   store volatile i32 42, i32 *%ptr1
   store volatile i32 42, i32 *%ptr2
   store volatile i32 %i0, i32 *%vptr
diff --git a/test/CodeGen/SystemZ/frame-14.ll b/test/CodeGen/SystemZ/frame-14.ll
index d8ff0a5..22a45ee 100644
--- a/test/CodeGen/SystemZ/frame-14.ll
+++ b/test/CodeGen/SystemZ/frame-14.ll
@@ -16,21 +16,21 @@
 
 ; First check the highest offset that is in range of the 12-bit form.
 ;
-; The last in-range doubleword offset is 4088.  Since the frame has an
-; emergency spill slot at 160(%r15), the amount that we need to allocate
-; in order to put another object at offset 4088 is 4088 - 168 = 3920 bytes.
+; The last in-range doubleword offset is 4088.  Since the frame has two
+; emergency spill slots at 160(%r15), the amount that we need to allocate
+; in order to put another object at offset 4088 is 4088 - 176 = 3912 bytes.
 define void @f1() {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
 ; CHECK-NOFP: mvi 4095(%r15), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: mvi 4095(%r11), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [3920 x i8], align 8
-  %region2 = alloca [3920 x i8], align 8
-  %ptr1 = getelementptr inbounds [3920 x i8]* %region1, i64 0, i64 7
-  %ptr2 = getelementptr inbounds [3920 x i8]* %region2, i64 0, i64 7
+  %region1 = alloca [3912 x i8], align 8
+  %region2 = alloca [3912 x i8], align 8
+  %ptr1 = getelementptr inbounds [3912 x i8]* %region1, i64 0, i64 7
+  %ptr2 = getelementptr inbounds [3912 x i8]* %region2, i64 0, i64 7
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -38,17 +38,17 @@ define void @f1() {
 
 ; Test the first offset that is out-of-range of the 12-bit form.
 define void @f2() {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
 ; CHECK-NOFP: mviy 4096(%r15), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
 ; CHECK-FP: mviy 4096(%r11), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [3920 x i8], align 8
-  %region2 = alloca [3920 x i8], align 8
-  %ptr1 = getelementptr inbounds [3920 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [3920 x i8]* %region2, i64 0, i64 8
+  %region1 = alloca [3912 x i8], align 8
+  %region2 = alloca [3912 x i8], align 8
+  %ptr1 = getelementptr inbounds [3912 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [3912 x i8]* %region2, i64 0, i64 8
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -57,19 +57,19 @@ define void @f2() {
 ; Test the last offset that is in range of the 20-bit form.
 ;
 ; The last in-range doubleword offset is 524280, so by the same reasoning
-; as above, we need to allocate objects of 524280 - 168 = 524122 bytes.
+; as above, we need to allocate objects of 524280 - 176 = 524104 bytes.
 define void @f3() {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
 ; CHECK-NOFP: mviy 524287(%r15), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
 ; CHECK-FP: mviy 524287(%r11), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [524112 x i8], align 8
-  %region2 = alloca [524112 x i8], align 8
-  %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 7
-  %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 7
+  %region1 = alloca [524104 x i8], align 8
+  %region2 = alloca [524104 x i8], align 8
+  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 7
+  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 7
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -79,21 +79,21 @@ define void @f3() {
 ; and the offset is also out of LAY's range, so expect a constant load
 ; followed by an addition.
 define void @f4() {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: mvi 0(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: mvi 0(%r1), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [524112 x i8], align 8
-  %region2 = alloca [524112 x i8], align 8
-  %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 8
+  %region1 = alloca [524104 x i8], align 8
+  %region2 = alloca [524104 x i8], align 8
+  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -102,21 +102,21 @@ define void @f4() {
 ; Add 4095 to the previous offset, to test the other end of the MVI range.
 ; The instruction will actually be STCY before frame lowering.
 define void @f5() {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: mvi 4095(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: mvi 4095(%r1), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [524112 x i8], align 8
-  %region2 = alloca [524112 x i8], align 8
-  %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 4103
-  %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 4103
+  %region1 = alloca [524104 x i8], align 8
+  %region2 = alloca [524104 x i8], align 8
+  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 4103
+  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 4103
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -124,21 +124,21 @@ define void @f5() {
 
 ; Test the next offset after that, which uses MVIY instead of MVI.
 define void @f6() {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: mviy 4096(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: mviy 4096(%r1), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [524112 x i8], align 8
-  %region2 = alloca [524112 x i8], align 8
-  %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 4104
-  %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 4104
+  %region1 = alloca [524104 x i8], align 8
+  %region2 = alloca [524104 x i8], align 8
+  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 4104
+  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 4104
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -149,21 +149,21 @@ define void @f6() {
 ; anchors 0x10000 bytes apart, so that the high part can be loaded using
 ; LLILH while still using MVI in more cases than 0x40000 anchors would.
 define void @f7() {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
 ; CHECK-NOFP: llilh %r1, 23
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: mviy 65535(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
 ; CHECK-FP: llilh %r1, 23
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: mviy 65535(%r1), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [1048408 x i8], align 8
-  %region2 = alloca [1048408 x i8], align 8
-  %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524287
-  %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524287
+  %region1 = alloca [1048400 x i8], align 8
+  %region2 = alloca [1048400 x i8], align 8
+  %ptr1 = getelementptr inbounds [1048400 x i8]* %region1, i64 0, i64 524287
+  %ptr2 = getelementptr inbounds [1048400 x i8]* %region2, i64 0, i64 524287
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -172,21 +172,21 @@ define void @f7() {
 ; Keep the object-relative offset the same but bump the size of the
 ; objects by one doubleword.
 define void @f8() {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
 ; CHECK-NOFP: llilh %r1, 24
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: mvi 7(%r1), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
 ; CHECK-FP: llilh %r1, 24
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: mvi 7(%r1), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [1048416 x i8], align 8
-  %region2 = alloca [1048416 x i8], align 8
-  %ptr1 = getelementptr inbounds [1048416 x i8]* %region1, i64 0, i64 524287
-  %ptr2 = getelementptr inbounds [1048416 x i8]* %region2, i64 0, i64 524287
+  %region1 = alloca [1048408 x i8], align 8
+  %region2 = alloca [1048408 x i8], align 8
+  %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524287
+  %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524287
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
@@ -200,56 +200,56 @@ define void @f8() {
 ; The LA then gets lowered into the LLILH/LA form.  The exact sequence
 ; isn't that important though.
 define void @f9() {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
 ; CHECK-NOFP: llilh [[R1:%r[1-5]]], 16
 ; CHECK-NOFP: la [[R2:%r[1-5]]], 8([[R1]],%r15)
 ; CHECK-NOFP: agfi [[R2]], 524288
 ; CHECK-NOFP: mvi 0([[R2]]), 42
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
 ; CHECK-FP: llilh [[R1:%r[1-5]]], 16
 ; CHECK-FP: la [[R2:%r[1-5]]], 8([[R1]],%r11)
 ; CHECK-FP: agfi [[R2]], 524288
 ; CHECK-FP: mvi 0([[R2]]), 42
 ; CHECK-FP: br %r14
-  %region1 = alloca [1048416 x i8], align 8
-  %region2 = alloca [1048416 x i8], align 8
-  %ptr1 = getelementptr inbounds [1048416 x i8]* %region1, i64 0, i64 524288
-  %ptr2 = getelementptr inbounds [1048416 x i8]* %region2, i64 0, i64 524288
+  %region1 = alloca [1048408 x i8], align 8
+  %region2 = alloca [1048408 x i8], align 8
+  %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524288
+  %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524288
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   ret void
 }
 
-; Repeat f4 in a case that needs the emergency spill slot (because all
+; Repeat f4 in a case that needs the emergency spill slots (because all
 ; call-clobbered registers are live and no call-saved ones have been
 ; allocated).
 define void @f10(i32 *%vptr) {
-; CHECK-NOFP: f10:
-; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15)
+; CHECK-NOFP-LABEL: f10:
+; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: llilh [[REGISTER]], 8
 ; CHECK-NOFP: agr [[REGISTER]], %r15
 ; CHECK-NOFP: mvi 0([[REGISTER]]), 42
-; CHECK-NOFP: lg [[REGISTER]], 160(%r15)
+; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f10:
-; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11)
+; CHECK-FP-LABEL: f10:
+; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: llilh [[REGISTER]], 8
 ; CHECK-FP: agr [[REGISTER]], %r11
 ; CHECK-FP: mvi 0([[REGISTER]]), 42
-; CHECK-FP: lg [[REGISTER]], 160(%r11)
+; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
 ; CHECK-FP: br %r14
   %i0 = load volatile i32 *%vptr
   %i1 = load volatile i32 *%vptr
   %i3 = load volatile i32 *%vptr
   %i4 = load volatile i32 *%vptr
   %i5 = load volatile i32 *%vptr
-  %region1 = alloca [524112 x i8], align 8
-  %region2 = alloca [524112 x i8], align 8
-  %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 8
+  %region1 = alloca [524104 x i8], align 8
+  %region2 = alloca [524104 x i8], align 8
+  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   store volatile i32 %i0, i32 *%vptr
@@ -260,28 +260,28 @@ define void @f10(i32 *%vptr) {
   ret void
 }
 
-; And again with maximum register pressure.  The only spill slot that the
-; NOFP case needs is the emergency one, so the offsets are the same as for f4.
+; And again with maximum register pressure.  The only spill slots that the
+; NOFP case needs are the emergency ones, so the offsets are the same as for f4.
 ; However, the FP case uses %r11 as the frame pointer and must therefore
 ; spill a second register.  This leads to an extra displacement of 8.
 define void @f11(i32 *%vptr) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
 ; CHECK-NOFP: stmg %r6, %r15,
-; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15)
+; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: llilh [[REGISTER]], 8
 ; CHECK-NOFP: agr [[REGISTER]], %r15
 ; CHECK-NOFP: mvi 0([[REGISTER]]), 42
-; CHECK-NOFP: lg [[REGISTER]], 160(%r15)
+; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: lmg %r6, %r15,
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
 ; CHECK-FP: stmg %r6, %r15,
-; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11)
+; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: llilh [[REGISTER]], 8
 ; CHECK-FP: agr [[REGISTER]], %r11
 ; CHECK-FP: mvi 8([[REGISTER]]), 42
-; CHECK-FP: lg [[REGISTER]], 160(%r11)
+; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
 ; CHECK-FP: lmg %r6, %r15,
 ; CHECK-FP: br %r14
   %i0 = load volatile i32 *%vptr
@@ -298,10 +298,10 @@ define void @f11(i32 *%vptr) {
   %i12 = load volatile i32 *%vptr
   %i13 = load volatile i32 *%vptr
   %i14 = load volatile i32 *%vptr
-  %region1 = alloca [524112 x i8], align 8
-  %region2 = alloca [524112 x i8], align 8
-  %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 8
+  %region1 = alloca [524104 x i8], align 8
+  %region2 = alloca [524104 x i8], align 8
+  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8
   store volatile i8 42, i8 *%ptr1
   store volatile i8 42, i8 *%ptr2
   store volatile i32 %i0, i32 *%vptr
diff --git a/test/CodeGen/SystemZ/frame-15.ll b/test/CodeGen/SystemZ/frame-15.ll
index bc87e17..d8b291d 100644
--- a/test/CodeGen/SystemZ/frame-15.ll
+++ b/test/CodeGen/SystemZ/frame-15.ll
@@ -19,25 +19,25 @@ declare void @foo(float *%ptr1, float *%ptr2)
 ; First check the highest in-range offset after conversion, which is 4092
 ; for word-addressing instructions like LDEB.
 ;
-; The last in-range doubleword offset is 4088.  Since the frame has an
-; emergency spill slot at 160(%r15), the amount that we need to allocate
-; in order to put another object at offset 4088 is (4088 - 168) / 4 = 980
+; The last in-range doubleword offset is 4088.  Since the frame has two
+; emergency spill slots at 160(%r15), the amount that we need to allocate
+; in order to put another object at offset 4088 is (4088 - 176) / 4 = 978
 ; words.
 define void @f1(double *%dst) {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4092(%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [980 x float], align 8
-  %region2 = alloca [980 x float], align 8
-  %start1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 0
+  %region1 = alloca [978 x float], align 8
+  %region2 = alloca [978 x float], align 8
+  %start1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 1
-  %ptr2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 1
+  %ptr1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 1
+  %ptr2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 1
   %float1 = load float *%ptr1
   %float2 = load float *%ptr2
   %double1 = fpext float %float1 to double
@@ -49,22 +49,22 @@ define void @f1(double *%dst) {
 
 ; Test the first out-of-range offset.
 define void @f2(double *%dst) {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
 ; CHECK-NOFP: lghi %r1, 4096
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 0(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
 ; CHECK-FP: lghi %r1, 4096
 ; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1,%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [980 x float], align 8
-  %region2 = alloca [980 x float], align 8
-  %start1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 0
+  %region1 = alloca [978 x float], align 8
+  %region2 = alloca [978 x float], align 8
+  %start1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 2
-  %ptr2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 2
+  %ptr1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 2
+  %ptr2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 2
   %float1 = load float *%ptr1
   %float2 = load float *%ptr2
   %double1 = fpext float %float1 to double
@@ -76,22 +76,22 @@ define void @f2(double *%dst) {
 
 ; Test the next offset after that.
 define void @f3(double *%dst) {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
 ; CHECK-NOFP: lghi %r1, 4096
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
 ; CHECK-FP: lghi %r1, 4096
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [980 x float], align 8
-  %region2 = alloca [980 x float], align 8
-  %start1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 0
+  %region1 = alloca [978 x float], align 8
+  %region2 = alloca [978 x float], align 8
+  %start1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 3
-  %ptr2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 3
+  %ptr1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 3
+  %ptr2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 3
   %float1 = load float *%ptr1
   %float2 = load float *%ptr2
   %double1 = fpext float %float1 to double
@@ -103,22 +103,22 @@ define void @f3(double *%dst) {
 
 ; Add 4096 bytes (1024 words) to the size of each object and repeat.
 define void @f4(double *%dst) {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
 ; CHECK-NOFP: lghi %r1, 4096
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4092(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
 ; CHECK-FP: lghi %r1, 4096
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r1,%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [2004 x float], align 8
-  %region2 = alloca [2004 x float], align 8
-  %start1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 0
+  %region1 = alloca [2002 x float], align 8
+  %region2 = alloca [2002 x float], align 8
+  %start1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 1
-  %ptr2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 1
+  %ptr1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 1
+  %ptr2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 1
   %float1 = load float *%ptr1
   %float2 = load float *%ptr2
   %double1 = fpext float %float1 to double
@@ -130,22 +130,22 @@ define void @f4(double *%dst) {
 
 ; ...as above.
 define void @f5(double *%dst) {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
 ; CHECK-NOFP: lghi %r1, 8192
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 0(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
 ; CHECK-FP: lghi %r1, 8192
 ; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1,%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [2004 x float], align 8
-  %region2 = alloca [2004 x float], align 8
-  %start1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 0
+  %region1 = alloca [2002 x float], align 8
+  %region2 = alloca [2002 x float], align 8
+  %start1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 2
-  %ptr2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 2
+  %ptr1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 2
+  %ptr2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 2
   %float1 = load float *%ptr1
   %float2 = load float *%ptr2
   %double1 = fpext float %float1 to double
@@ -157,22 +157,22 @@ define void @f5(double *%dst) {
 
 ; ...as above.
 define void @f6(double *%dst) {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
 ; CHECK-NOFP: lghi %r1, 8192
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
 ; CHECK-FP: lghi %r1, 8192
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [2004 x float], align 8
-  %region2 = alloca [2004 x float], align 8
-  %start1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 0
+  %region1 = alloca [2002 x float], align 8
+  %region2 = alloca [2002 x float], align 8
+  %start1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 3
-  %ptr2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 3
+  %ptr1 = getelementptr inbounds [2002 x float]* %region1, i64 0, i64 3
+  %ptr2 = getelementptr inbounds [2002 x float]* %region2, i64 0, i64 3
   %float1 = load float *%ptr1
   %float2 = load float *%ptr2
   %double1 = fpext float %float1 to double
@@ -183,25 +183,25 @@ define void @f6(double *%dst) {
 }
 
 ; Now try an offset of 4092 from the start of the object, with the object
-; being at offset 8192.  This time we need objects of (8192 - 168) / 4 = 2006
+; being at offset 8192.  This time we need objects of (8192 - 168) / 4 = 2004
 ; words.
 define void @f7(double *%dst) {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
 ; CHECK-NOFP: lghi %r1, 8192
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4092(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
 ; CHECK-FP: lghi %r1, 8192
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r1,%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [2006 x float], align 8
-  %region2 = alloca [2006 x float], align 8
-  %start1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 0
+  %region1 = alloca [2004 x float], align 8
+  %region2 = alloca [2004 x float], align 8
+  %start1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 1023
-  %ptr2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 1023
+  %ptr1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 1023
+  %ptr2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 1023
   %float1 = load float *%ptr1
   %float2 = load float *%ptr2
   %double1 = fpext float %float1 to double
@@ -214,22 +214,22 @@ define void @f7(double *%dst) {
 ; Keep the object-relative offset the same but bump the size of the
 ; objects by one doubleword.
 define void @f8(double *%dst) {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
 ; CHECK-NOFP: lghi %r1, 12288
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 4(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
 ; CHECK-FP: lghi %r1, 12288
 ; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [2008 x float], align 8
-  %region2 = alloca [2008 x float], align 8
-  %start1 = getelementptr inbounds [2008 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [2008 x float]* %region2, i64 0, i64 0
+  %region1 = alloca [2006 x float], align 8
+  %region2 = alloca [2006 x float], align 8
+  %start1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [2008 x float]* %region1, i64 0, i64 1023
-  %ptr2 = getelementptr inbounds [2008 x float]* %region2, i64 0, i64 1023
+  %ptr1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 1023
+  %ptr2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 1023
   %float1 = load float *%ptr1
   %float2 = load float *%ptr2
   %double1 = fpext float %float1 to double
@@ -243,22 +243,22 @@ define void @f8(double *%dst) {
 ; should force an LAY from the outset.  We don't yet do any kind of anchor
 ; optimization, so there should be no offset on the LDEB itself.
 define void @f9(double *%dst) {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
 ; CHECK-NOFP: lay %r1, 12296(%r15)
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 0(%r1)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
 ; CHECK-FP: lay %r1, 12296(%r11)
 ; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1)
 ; CHECK-FP: br %r14
-  %region1 = alloca [2008 x float], align 8
-  %region2 = alloca [2008 x float], align 8
-  %start1 = getelementptr inbounds [2008 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [2008 x float]* %region2, i64 0, i64 0
+  %region1 = alloca [2006 x float], align 8
+  %region2 = alloca [2006 x float], align 8
+  %start1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [2008 x float]* %region1, i64 0, i64 1024
-  %ptr2 = getelementptr inbounds [2008 x float]* %region2, i64 0, i64 1024
+  %ptr1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 1024
+  %ptr2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 1024
   %float1 = load float *%ptr1
   %float2 = load float *%ptr2
   %double1 = fpext float %float1 to double
@@ -268,31 +268,31 @@ define void @f9(double *%dst) {
   ret void
 }
 
-; Repeat f2 in a case that needs the emergency spill slot, because all
+; Repeat f2 in a case that needs the emergency spill slots, because all
 ; call-clobbered and allocated call-saved registers are live.  Note that
 ; %vptr and %dst are copied to call-saved registers, freeing up %r2 and
 ; %r3 during the main test.
 define void @f10(i32 *%vptr, double *%dst) {
-; CHECK-NOFP: f10:
-; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15)
+; CHECK-NOFP-LABEL: f10:
+; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: lghi [[REGISTER]], 4096
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r15)
-; CHECK-NOFP: lg [[REGISTER]], 160(%r15)
+; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f10:
-; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11)
+; CHECK-FP-LABEL: f10:
+; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: lghi [[REGISTER]], 4096
 ; CHECK-FP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r11)
-; CHECK-FP: lg [[REGISTER]], 160(%r11)
+; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [980 x float], align 8
-  %region2 = alloca [980 x float], align 8
-  %start1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 0
+  %region1 = alloca [978 x float], align 8
+  %region2 = alloca [978 x float], align 8
+  %start1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %ptr1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 2
-  %ptr2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 2
+  %ptr1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 2
+  %ptr2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 2
   %i0 = load volatile i32 *%vptr
   %i1 = load volatile i32 *%vptr
   %i2 = load volatile i32 *%vptr
@@ -318,24 +318,24 @@ define void @f10(i32 *%vptr, double *%dst) {
 
 ; Repeat f2 in a case where the index register is already occupied.
 define void @f11(double *%dst, i64 %index) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
 ; CHECK-NOFP: lgr [[REGISTER:%r[1-9][0-5]?]], %r3
 ; CHECK-NOFP: lay %r1, 4096(%r15)
 ; CHECK-NOFP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r1)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
 ; CHECK-FP: lgr [[REGISTER:%r[1-9][0-5]?]], %r3
 ; CHECK-FP: lay %r1, 4096(%r11)
 ; CHECK-FP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r1)
 ; CHECK-FP: br %r14
-  %region1 = alloca [980 x float], align 8
-  %region2 = alloca [980 x float], align 8
-  %start1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 0
-  %start2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 0
+  %region1 = alloca [978 x float], align 8
+  %region2 = alloca [978 x float], align 8
+  %start1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 0
+  %start2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 0
   call void @foo(float *%start1, float *%start2)
-  %elem1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 2
-  %elem2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 2
+  %elem1 = getelementptr inbounds [978 x float]* %region1, i64 0, i64 2
+  %elem2 = getelementptr inbounds [978 x float]* %region2, i64 0, i64 2
   %base1 = ptrtoint float *%elem1 to i64
   %base2 = ptrtoint float *%elem2 to i64
   %addr1 = add i64 %base1, %index
diff --git a/test/CodeGen/SystemZ/frame-16.ll b/test/CodeGen/SystemZ/frame-16.ll
index cc5529f..9f43b49 100644
--- a/test/CodeGen/SystemZ/frame-16.ll
+++ b/test/CodeGen/SystemZ/frame-16.ll
@@ -16,21 +16,21 @@
 
 ; First check the highest offset that is in range of the 12-bit form.
 ;
-; The last in-range doubleword offset is 4088.  Since the frame has an
-; emergency spill slot at 160(%r15), the amount that we need to allocate
-; in order to put another object at offset 4088 is 4088 - 168 = 3920 bytes.
+; The last in-range doubleword offset is 4088.  Since the frame has two
+; emergency spill slots at 160(%r15), the amount that we need to allocate
+; in order to put another object at offset 4088 is 4088 - 176 = 3912 bytes.
 define void @f1(i8 %byte) {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
 ; CHECK-NOFP: stc %r2, 4095(%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
 ; CHECK-FP: stc %r2, 4095(%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [3920 x i8], align 8
-  %region2 = alloca [3920 x i8], align 8
-  %ptr1 = getelementptr inbounds [3920 x i8]* %region1, i64 0, i64 7
-  %ptr2 = getelementptr inbounds [3920 x i8]* %region2, i64 0, i64 7
+  %region1 = alloca [3912 x i8], align 8
+  %region2 = alloca [3912 x i8], align 8
+  %ptr1 = getelementptr inbounds [3912 x i8]* %region1, i64 0, i64 7
+  %ptr2 = getelementptr inbounds [3912 x i8]* %region2, i64 0, i64 7
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -38,17 +38,17 @@ define void @f1(i8 %byte) {
 
 ; Test the first offset that is out-of-range of the 12-bit form.
 define void @f2(i8 %byte) {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
 ; CHECK-NOFP: stcy %r2, 4096(%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
 ; CHECK-FP: stcy %r2, 4096(%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [3920 x i8], align 8
-  %region2 = alloca [3920 x i8], align 8
-  %ptr1 = getelementptr inbounds [3920 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [3920 x i8]* %region2, i64 0, i64 8
+  %region1 = alloca [3912 x i8], align 8
+  %region2 = alloca [3912 x i8], align 8
+  %ptr1 = getelementptr inbounds [3912 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [3912 x i8]* %region2, i64 0, i64 8
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -57,19 +57,19 @@ define void @f2(i8 %byte) {
 ; Test the last offset that is in range of the 20-bit form.
 ;
 ; The last in-range doubleword offset is 524280, so by the same reasoning
-; as above, we need to allocate objects of 524280 - 168 = 524122 bytes.
+; as above, we need to allocate objects of 524280 - 176 = 524104 bytes.
 define void @f3(i8 %byte) {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
 ; CHECK-NOFP: stcy %r2, 524287(%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
 ; CHECK-FP: stcy %r2, 524287(%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [524112 x i8], align 8
-  %region2 = alloca [524112 x i8], align 8
-  %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 7
-  %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 7
+  %region1 = alloca [524104 x i8], align 8
+  %region2 = alloca [524104 x i8], align 8
+  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 7
+  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 7
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -79,19 +79,19 @@ define void @f3(i8 %byte) {
 ; and the offset is also out of LAY's range, so expect a constant load
 ; followed by an addition.
 define void @f4(i8 %byte) {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: stc %r2, 0(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: stc %r2, 0(%r1,%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [524112 x i8], align 8
-  %region2 = alloca [524112 x i8], align 8
-  %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 8
+  %region1 = alloca [524104 x i8], align 8
+  %region2 = alloca [524104 x i8], align 8
+  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -100,19 +100,19 @@ define void @f4(i8 %byte) {
 ; Add 4095 to the previous offset, to test the other end of the STC range.
 ; The instruction will actually be STCY before frame lowering.
 define void @f5(i8 %byte) {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: stc %r2, 4095(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: stc %r2, 4095(%r1,%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [524112 x i8], align 8
-  %region2 = alloca [524112 x i8], align 8
-  %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 4103
-  %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 4103
+  %region1 = alloca [524104 x i8], align 8
+  %region2 = alloca [524104 x i8], align 8
+  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 4103
+  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 4103
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -120,19 +120,19 @@ define void @f5(i8 %byte) {
 
 ; Test the next offset after that, which uses STCY instead of STC.
 define void @f6(i8 %byte) {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: stcy %r2, 4096(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: stcy %r2, 4096(%r1,%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [524112 x i8], align 8
-  %region2 = alloca [524112 x i8], align 8
-  %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 4104
-  %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 4104
+  %region1 = alloca [524104 x i8], align 8
+  %region2 = alloca [524104 x i8], align 8
+  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 4104
+  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 4104
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -143,19 +143,19 @@ define void @f6(i8 %byte) {
 ; anchors 0x10000 bytes apart, so that the high part can be loaded using
 ; LLILH while still using STC in more cases than 0x40000 anchors would.
 define void @f7(i8 %byte) {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
 ; CHECK-NOFP: llilh %r1, 23
 ; CHECK-NOFP: stcy %r2, 65535(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
 ; CHECK-FP: llilh %r1, 23
 ; CHECK-FP: stcy %r2, 65535(%r1,%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [1048408 x i8], align 8
-  %region2 = alloca [1048408 x i8], align 8
-  %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524287
-  %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524287
+  %region1 = alloca [1048400 x i8], align 8
+  %region2 = alloca [1048400 x i8], align 8
+  %ptr1 = getelementptr inbounds [1048400 x i8]* %region1, i64 0, i64 524287
+  %ptr2 = getelementptr inbounds [1048400 x i8]* %region2, i64 0, i64 524287
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -164,19 +164,19 @@ define void @f7(i8 %byte) {
 ; Keep the object-relative offset the same but bump the size of the
 ; objects by one doubleword.
 define void @f8(i8 %byte) {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
 ; CHECK-NOFP: llilh %r1, 24
 ; CHECK-NOFP: stc %r2, 7(%r1,%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
 ; CHECK-FP: llilh %r1, 24
 ; CHECK-FP: stc %r2, 7(%r1,%r11)
 ; CHECK-FP: br %r14
-  %region1 = alloca [1048416 x i8], align 8
-  %region2 = alloca [1048416 x i8], align 8
-  %ptr1 = getelementptr inbounds [1048416 x i8]* %region1, i64 0, i64 524287
-  %ptr2 = getelementptr inbounds [1048416 x i8]* %region2, i64 0, i64 524287
+  %region1 = alloca [1048408 x i8], align 8
+  %region2 = alloca [1048408 x i8], align 8
+  %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524287
+  %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524287
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
@@ -190,53 +190,53 @@ define void @f8(i8 %byte) {
 ; The LA then gets lowered into the LLILH/LA form.  The exact sequence
 ; isn't that important though.
 define void @f9(i8 %byte) {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
 ; CHECK-NOFP: llilh [[R1:%r[1-5]]], 16
 ; CHECK-NOFP: la [[R2:%r[1-5]]], 8([[R1]],%r15)
 ; CHECK-NOFP: agfi [[R2]], 524288
 ; CHECK-NOFP: stc %r2, 0([[R2]])
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
 ; CHECK-FP: llilh [[R1:%r[1-5]]], 16
 ; CHECK-FP: la [[R2:%r[1-5]]], 8([[R1]],%r11)
 ; CHECK-FP: agfi [[R2]], 524288
 ; CHECK-FP: stc %r2, 0([[R2]])
 ; CHECK-FP: br %r14
-  %region1 = alloca [1048416 x i8], align 8
-  %region2 = alloca [1048416 x i8], align 8
-  %ptr1 = getelementptr inbounds [1048416 x i8]* %region1, i64 0, i64 524288
-  %ptr2 = getelementptr inbounds [1048416 x i8]* %region2, i64 0, i64 524288
+  %region1 = alloca [1048408 x i8], align 8
+  %region2 = alloca [1048408 x i8], align 8
+  %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524288
+  %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524288
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
 }
 
-; Repeat f4 in a case that needs the emergency spill slot (because all
+; Repeat f4 in a case that needs the emergency spill slots (because all
 ; call-clobbered registers are live and no call-saved ones have been
 ; allocated).
 define void @f10(i32 *%vptr, i8 %byte) {
-; CHECK-NOFP: f10:
-; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15)
+; CHECK-NOFP-LABEL: f10:
+; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: llilh [[REGISTER]], 8
 ; CHECK-NOFP: stc %r3, 0([[REGISTER]],%r15)
-; CHECK-NOFP: lg [[REGISTER]], 160(%r15)
+; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f10:
-; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11)
+; CHECK-FP-LABEL: f10:
+; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: llilh [[REGISTER]], 8
 ; CHECK-FP: stc %r3, 0([[REGISTER]],%r11)
-; CHECK-FP: lg [[REGISTER]], 160(%r11)
+; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
 ; CHECK-FP: br %r14
   %i0 = load volatile i32 *%vptr
   %i1 = load volatile i32 *%vptr
   %i4 = load volatile i32 *%vptr
   %i5 = load volatile i32 *%vptr
-  %region1 = alloca [524112 x i8], align 8
-  %region2 = alloca [524112 x i8], align 8
-  %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 8
+  %region1 = alloca [524104 x i8], align 8
+  %region2 = alloca [524104 x i8], align 8
+  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   store volatile i32 %i0, i32 *%vptr
@@ -246,26 +246,26 @@ define void @f10(i32 *%vptr, i8 %byte) {
   ret void
 }
 
-; And again with maximum register pressure.  The only spill slot that the
-; NOFP case needs is the emergency one, so the offsets are the same as for f4.
+; And again with maximum register pressure.  The only spill slots that the
+; NOFP case needs are the emergency ones, so the offsets are the same as for f4.
 ; However, the FP case uses %r11 as the frame pointer and must therefore
 ; spill a second register.  This leads to an extra displacement of 8.
 define void @f11(i32 *%vptr, i8 %byte) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
 ; CHECK-NOFP: stmg %r6, %r15,
-; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15)
+; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
 ; CHECK-NOFP: llilh [[REGISTER]], 8
 ; CHECK-NOFP: stc %r3, 0([[REGISTER]],%r15)
-; CHECK-NOFP: lg [[REGISTER]], 160(%r15)
+; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
 ; CHECK-NOFP: lmg %r6, %r15,
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
 ; CHECK-FP: stmg %r6, %r15,
-; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11)
+; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
 ; CHECK-FP: llilh [[REGISTER]], 8
 ; CHECK-FP: stc %r3, 8([[REGISTER]],%r11)
-; CHECK-FP: lg [[REGISTER]], 160(%r11)
+; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11)
 ; CHECK-FP: lmg %r6, %r15,
 ; CHECK-FP: br %r14
   %i0 = load volatile i32 *%vptr
@@ -281,10 +281,10 @@ define void @f11(i32 *%vptr, i8 %byte) {
   %i12 = load volatile i32 *%vptr
   %i13 = load volatile i32 *%vptr
   %i14 = load volatile i32 *%vptr
-  %region1 = alloca [524112 x i8], align 8
-  %region2 = alloca [524112 x i8], align 8
-  %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 8
-  %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 8
+  %region1 = alloca [524104 x i8], align 8
+  %region2 = alloca [524104 x i8], align 8
+  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 8
+  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 8
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   store volatile i32 %i0, i32 *%vptr
@@ -305,22 +305,22 @@ define void @f11(i32 *%vptr, i8 %byte) {
 
 ; Repeat f4 in a case where the index register is already occupied.
 define void @f12(i8 %byte, i64 %index) {
-; CHECK-NOFP: f12:
+; CHECK-NOFP-LABEL: f12:
 ; CHECK-NOFP: llilh %r1, 8
 ; CHECK-NOFP: agr %r1, %r15
 ; CHECK-NOFP: stc %r2, 0(%r3,%r1)
 ; CHECK-NOFP: br %r14
 ;
-; CHECK-FP: f12:
+; CHECK-FP-LABEL: f12:
 ; CHECK-FP: llilh %r1, 8
 ; CHECK-FP: agr %r1, %r11
 ; CHECK-FP: stc %r2, 0(%r3,%r1)
 ; CHECK-FP: br %r14
-  %region1 = alloca [524112 x i8], align 8
-  %region2 = alloca [524112 x i8], align 8
+  %region1 = alloca [524104 x i8], align 8
+  %region2 = alloca [524104 x i8], align 8
   %index1 = add i64 %index, 8
-  %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 %index1
-  %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 %index1
+  %ptr1 = getelementptr inbounds [524104 x i8]* %region1, i64 0, i64 %index1
+  %ptr2 = getelementptr inbounds [524104 x i8]* %region2, i64 0, i64 %index1
   store volatile i8 %byte, i8 *%ptr1
   store volatile i8 %byte, i8 *%ptr2
   ret void
diff --git a/test/CodeGen/SystemZ/frame-17.ll b/test/CodeGen/SystemZ/frame-17.ll
index 613d9f8..97cf83d 100644
--- a/test/CodeGen/SystemZ/frame-17.ll
+++ b/test/CodeGen/SystemZ/frame-17.ll
@@ -6,7 +6,7 @@
 ; 4-byte spill slot, rounded to 8 bytes.  The frame size should be exactly
 ; 160 + 8 * 8 = 232.
 define void @f1(float *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: aghi %r15, -232
 ; CHECK: std %f8, 224(%r15)
 ; CHECK: std %f9, 216(%r15)
@@ -70,7 +70,7 @@ define void @f1(float *%ptr) {
 
 ; Same for doubles, except that the full spill slot is used.
 define void @f2(double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r15, -232
 ; CHECK: std %f8, 224(%r15)
 ; CHECK: std %f9, 216(%r15)
@@ -131,7 +131,7 @@ define void @f2(double *%ptr) {
 
 ; The long double case needs a 16-byte spill slot.
 define void @f3(fp128 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: aghi %r15, -240
 ; CHECK: std %f8, 232(%r15)
 ; CHECK: std %f9, 224(%r15)
diff --git a/test/CodeGen/SystemZ/frame-18.ll b/test/CodeGen/SystemZ/frame-18.ll
index a9977ed..57d6f7d 100644
--- a/test/CodeGen/SystemZ/frame-18.ll
+++ b/test/CodeGen/SystemZ/frame-18.ll
@@ -5,7 +5,7 @@
 ; We need to allocate a 4-byte spill slot, rounded to 8 bytes.  The frame
 ; size should be exactly 160 + 8 = 168.
 define void @f1(i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK: aghi %r15, -168
 ; CHECK-NOT: 160(%r15)
@@ -50,7 +50,7 @@ define void @f1(i32 *%ptr) {
 
 ; Same for i64, except that the full spill slot is used.
 define void @f2(i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stmg %r6, %r15, 48(%r15)
 ; CHECK: aghi %r15, -168
 ; CHECK: stg [[REGISTER:%r[0-9]+]], 160(%r15)
diff --git a/test/CodeGen/SystemZ/insert-01.ll b/test/CodeGen/SystemZ/insert-01.ll
index 98ddf56..0b54e85 100644
--- a/test/CodeGen/SystemZ/insert-01.ll
+++ b/test/CodeGen/SystemZ/insert-01.ll
@@ -5,7 +5,7 @@
 ; Check a plain insertion with (or (and ... -0xff) (zext (load ....))).
 ; The whole sequence can be performed by IC.
 define i32 @f1(i32 %orig, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define i32 @f1(i32 %orig, i8 *%ptr) {
 
 ; Like f1, but with the operands reversed.
 define i32 @f2(i32 %orig, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -32,7 +32,7 @@ define i32 @f2(i32 %orig, i8 *%ptr) {
 ; Check a case where more bits than lower 8 are masked out of the
 ; register value.  We can use IC but must keep the original mask.
 define i32 @f3(i32 %orig, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nill %r2, 65024
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -45,7 +45,7 @@ define i32 @f3(i32 %orig, i8 *%ptr) {
 
 ; Like f3, but with the operands reversed.
 define i32 @f4(i32 %orig, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nill %r2, 65024
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -58,7 +58,7 @@ define i32 @f4(i32 %orig, i8 *%ptr) {
 
 ; Check a case where the low 8 bits are cleared by a shift left.
 define i32 @f5(i32 %orig, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sll %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i32 @f5(i32 %orig, i8 *%ptr) {
 
 ; Like f5, but with the operands reversed.
 define i32 @f6(i32 %orig, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sll %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i32 @f6(i32 %orig, i8 *%ptr) {
 
 ; Check insertions into a constant.
 define i32 @f7(i32 %orig, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lhi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -96,7 +96,7 @@ define i32 @f7(i32 %orig, i8 *%ptr) {
 
 ; Like f7, but with the operands reversed.
 define i32 @f8(i32 %orig, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lhi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define i32 @f8(i32 %orig, i8 *%ptr) {
 
 ; Check the high end of the IC range.
 define i32 @f9(i32 %orig, i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ic %r2, 4095(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -121,7 +121,7 @@ define i32 @f9(i32 %orig, i8 *%src) {
 
 ; Check the next byte up, which should use ICY instead of IC.
 define i32 @f10(i32 %orig, i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: icy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -134,7 +134,7 @@ define i32 @f10(i32 %orig, i8 *%src) {
 
 ; Check the high end of the ICY range.
 define i32 @f11(i32 %orig, i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: icy %r2, 524287(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -148,7 +148,7 @@ define i32 @f11(i32 %orig, i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f12(i32 %orig, i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -162,7 +162,7 @@ define i32 @f12(i32 %orig, i8 *%src) {
 
 ; Check the high end of the negative ICY range.
 define i32 @f13(i32 %orig, i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: icy %r2, -1(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -175,7 +175,7 @@ define i32 @f13(i32 %orig, i8 *%src) {
 
 ; Check the low end of the ICY range.
 define i32 @f14(i32 %orig, i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: icy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -189,7 +189,7 @@ define i32 @f14(i32 %orig, i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f15(i32 %orig, i8 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: agfi %r3, -524289
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -203,7 +203,7 @@ define i32 @f15(i32 %orig, i8 *%src) {
 
 ; Check that IC allows an index.
 define i32 @f16(i32 %orig, i8 *%src, i64 %index) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: ic %r2, 4095({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %ptr1 = getelementptr i8 *%src, i64 %index
@@ -217,7 +217,7 @@ define i32 @f16(i32 %orig, i8 *%src, i64 %index) {
 
 ; Check that ICY allows an index.
 define i32 @f17(i32 %orig, i8 *%src, i64 %index) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: icy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %ptr1 = getelementptr i8 *%src, i64 %index
diff --git a/test/CodeGen/SystemZ/insert-02.ll b/test/CodeGen/SystemZ/insert-02.ll
index 471889d..7a85b0b 100644
--- a/test/CodeGen/SystemZ/insert-02.ll
+++ b/test/CodeGen/SystemZ/insert-02.ll
@@ -5,7 +5,7 @@
 ; Check a plain insertion with (or (and ... -0xff) (zext (load ....))).
 ; The whole sequence can be performed by IC.
 define i64 @f1(i64 %orig, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define i64 @f1(i64 %orig, i8 *%ptr) {
 
 ; Like f1, but with the operands reversed.
 define i64 @f2(i64 %orig, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: ni
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -32,7 +32,7 @@ define i64 @f2(i64 %orig, i8 *%ptr) {
 ; Check a case where more bits than lower 8 are masked out of the
 ; register value.  We can use IC but must keep the original mask.
 define i64 @f3(i64 %orig, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: nill %r2, 65024
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -45,7 +45,7 @@ define i64 @f3(i64 %orig, i8 *%ptr) {
 
 ; Like f3, but with the operands reversed.
 define i64 @f4(i64 %orig, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: nill %r2, 65024
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -58,7 +58,7 @@ define i64 @f4(i64 %orig, i8 *%ptr) {
 
 ; Check a case where the low 8 bits are cleared by a shift left.
 define i64 @f5(i64 %orig, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sllg %r2, %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i64 @f5(i64 %orig, i8 *%ptr) {
 
 ; Like f5, but with the operands reversed.
 define i64 @f6(i64 %orig, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r2, %r2, 8
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -84,7 +84,7 @@ define i64 @f6(i64 %orig, i8 *%ptr) {
 
 ; Check insertions into a constant.
 define i64 @f7(i64 %orig, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lghi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -96,7 +96,7 @@ define i64 @f7(i64 %orig, i8 *%ptr) {
 
 ; Like f7, but with the operands reversed.
 define i64 @f8(i64 %orig, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lghi %r2, 256
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define i64 @f8(i64 %orig, i8 *%ptr) {
 
 ; Check the high end of the IC range.
 define i64 @f9(i64 %orig, i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ic %r2, 4095(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -121,7 +121,7 @@ define i64 @f9(i64 %orig, i8 *%src) {
 
 ; Check the next byte up, which should use ICY instead of IC.
 define i64 @f10(i64 %orig, i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: icy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -134,7 +134,7 @@ define i64 @f10(i64 %orig, i8 *%src) {
 
 ; Check the high end of the ICY range.
 define i64 @f11(i64 %orig, i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: icy %r2, 524287(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -148,7 +148,7 @@ define i64 @f11(i64 %orig, i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f12(i64 %orig, i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -162,7 +162,7 @@ define i64 @f12(i64 %orig, i8 *%src) {
 
 ; Check the high end of the negative ICY range.
 define i64 @f13(i64 %orig, i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: icy %r2, -1(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -175,7 +175,7 @@ define i64 @f13(i64 %orig, i8 *%src) {
 
 ; Check the low end of the ICY range.
 define i64 @f14(i64 %orig, i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: icy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -189,7 +189,7 @@ define i64 @f14(i64 %orig, i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f15(i64 %orig, i8 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: agfi %r3, -524289
 ; CHECK: ic %r2, 0(%r3)
 ; CHECK: br %r14
@@ -203,7 +203,7 @@ define i64 @f15(i64 %orig, i8 *%src) {
 
 ; Check that IC allows an index.
 define i64 @f16(i64 %orig, i8 *%src, i64 %index) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: ic %r2, 4095({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %ptr1 = getelementptr i8 *%src, i64 %index
@@ -217,7 +217,7 @@ define i64 @f16(i64 %orig, i8 *%src, i64 %index) {
 
 ; Check that ICY allows an index.
 define i64 @f17(i64 %orig, i8 *%src, i64 %index) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: icy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %ptr1 = getelementptr i8 *%src, i64 %index
diff --git a/test/CodeGen/SystemZ/insert-03.ll b/test/CodeGen/SystemZ/insert-03.ll
index 261eabd..c3c1ae3 100644
--- a/test/CodeGen/SystemZ/insert-03.ll
+++ b/test/CodeGen/SystemZ/insert-03.ll
@@ -5,7 +5,7 @@
 ; Check the lowest useful IILL value.  (We use NILL rather than IILL
 ; to clear 16 bits.)
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 1
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define i32 @f1(i32 %a) {
 
 ; Check a middle value.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 32769
 ; CHECK: br %r14
@@ -28,7 +28,7 @@ define i32 @f2(i32 %a) {
 ; Check the highest useful IILL value.  (We use OILL rather than IILL
 ; to set 16 bits.)
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 65534
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define i32 @f3(i32 %a) {
 
 ; Check the lowest useful IILH value.
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 1
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define i32 @f4(i32 %a) {
 
 ; Check a middle value.
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 32767
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define i32 @f5(i32 %a) {
 
 ; Check the highest useful IILH value.
 define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 65534
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/insert-04.ll b/test/CodeGen/SystemZ/insert-04.ll
index 07f88b9..5ce99df 100644
--- a/test/CodeGen/SystemZ/insert-04.ll
+++ b/test/CodeGen/SystemZ/insert-04.ll
@@ -5,7 +5,7 @@
 ; Check the lowest useful IILL value.  (We use NILL rather than IILL
 ; to clear 16 bits.)
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 1
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a) {
 
 ; Check a middle value.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 32769
 ; CHECK: br %r14
@@ -28,7 +28,7 @@ define i64 @f2(i64 %a) {
 ; Check the highest useful IILL value.  (We use OILL rather than IILL
 ; to set 16 bits.)
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: ni
 ; CHECK: iill %r2, 65534
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define i64 @f3(i64 %a) {
 
 ; Check the lowest useful IILH value.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 1
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define i64 @f4(i64 %a) {
 
 ; Check a middle value.
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 32767
 ; CHECK: br %r14
@@ -61,7 +61,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the highest useful IILH value.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: ni
 ; CHECK: iilh %r2, 65534
 ; CHECK: br %r14
@@ -72,7 +72,7 @@ define i64 @f6(i64 %a) {
 
 ; Check the lowest useful IIHL value.
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: ni
 ; CHECK: iihl %r2, 1
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define i64 @f7(i64 %a) {
 
 ; Check a middle value.
 define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: ni
 ; CHECK: iihl %r2, 32767
 ; CHECK: br %r14
@@ -94,7 +94,7 @@ define i64 @f8(i64 %a) {
 
 ; Check the highest useful IIHL value.
 define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: ni
 ; CHECK: iihl %r2, 65534
 ; CHECK: br %r14
@@ -105,7 +105,7 @@ define i64 @f9(i64 %a) {
 
 ; Check the lowest useful IIHH value.
 define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: ni
 ; CHECK: iihh %r2, 1
 ; CHECK: br %r14
@@ -116,7 +116,7 @@ define i64 @f10(i64 %a) {
 
 ; Check a middle value.
 define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: ni
 ; CHECK: iihh %r2, 32767
 ; CHECK: br %r14
@@ -127,7 +127,7 @@ define i64 @f11(i64 %a) {
 
 ; Check the highest useful IIHH value.
 define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: ni
 ; CHECK: iihh %r2, 65534
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/insert-05.ll b/test/CodeGen/SystemZ/insert-05.ll
index da51676..b76859a 100644
--- a/test/CodeGen/SystemZ/insert-05.ll
+++ b/test/CodeGen/SystemZ/insert-05.ll
@@ -4,7 +4,7 @@
 
 ; Prefer LHI over IILF for signed 16-bit constants.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: ni
 ; CHECK: lhi %r2, 1
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the LHI range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: ni
 ; CHECK: lhi %r2, 32767
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define i64 @f2(i64 %a) {
 
 ; Check the next value up, which should use IILF instead.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: ni
 ; CHECK: iilf %r2, 32768
 ; CHECK: br %r14
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a) {
 
 ; Check a value in which the lower 16 bits are clear.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: ni
 ; CHECK: iilf %r2, 65536
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define i64 @f4(i64 %a) {
 
 ; Check the highest useful IILF value (-0x8001).
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: ni
 ; CHECK: iilf %r2, 4294934527
 ; CHECK: br %r14
@@ -59,7 +59,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the next value up, which should use LHI instead.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: ni
 ; CHECK: lhi %r2, -32768
 ; CHECK: br %r14
@@ -71,7 +71,7 @@ define i64 @f6(i64 %a) {
 ; Check the highest useful LHI value.  (We use OILF for -1 instead, although
 ; LHI might be better there too.)
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: ni
 ; CHECK: lhi %r2, -2
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define i64 @f7(i64 %a) {
 ; Check that SRLG is still used if some of the high bits are known to be 0
 ; (and so might be removed from the mask).
 define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: srlg %r2, %r2, 1
 ; CHECK-NEXT: iilf %r2, 32768
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f8(i64 %a) {
 
 ; Repeat f8 with addition, which is known to be equivalent to OR in this case.
 define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: srlg %r2, %r2, 1
 ; CHECK-NEXT: iilf %r2, 32768
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define i64 @f9(i64 %a) {
 
 ; Repeat f8 with already-zero bits removed from the mask.
 define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: srlg %r2, %r2, 1
 ; CHECK-NEXT: iilf %r2, 32768
 ; CHECK: br %r14
@@ -119,7 +119,7 @@ define i64 @f10(i64 %a) {
 
 ; Repeat f10 with addition, which is known to be equivalent to OR in this case.
 define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: srlg %r2, %r2, 1
 ; CHECK-NEXT: iilf %r2, 32768
 ; CHECK: br %r14
@@ -131,7 +131,7 @@ define i64 @f11(i64 %a) {
 
 ; Check the lowest useful IIHF value.
 define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: ni
 ; CHECK: iihf %r2, 1
 ; CHECK: br %r14
@@ -142,7 +142,7 @@ define i64 @f12(i64 %a) {
 
 ; Check a value in which the lower 16 bits are clear.
 define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK-NOT: ni
 ; CHECK: iihf %r2, 2147483648
 ; CHECK: br %r14
@@ -153,7 +153,7 @@ define i64 @f13(i64 %a) {
 
 ; Check the highest useful IIHF value (0xfffffffe).
 define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: ni
 ; CHECK: iihf %r2, 4294967294
 ; CHECK: br %r14
@@ -165,7 +165,7 @@ define i64 @f14(i64 %a) {
 ; Check a case in which some of the low 32 bits are known to be clear,
 ; and so could be removed from the AND mask.
 define i64 @f15(i64 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: sllg %r2, %r2, 1
 ; CHECK-NEXT: iihf %r2, 1
 ; CHECK: br %r14
@@ -177,7 +177,7 @@ define i64 @f15(i64 %a) {
 
 ; Repeat f15 with the zero bits explicitly removed from the mask.
 define i64 @f16(i64 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: sllg %r2, %r2, 1
 ; CHECK-NEXT: iihf %r2, 1
 ; CHECK: br %r14
@@ -189,7 +189,7 @@ define i64 @f16(i64 %a) {
 
 ; Check concatenation of two i32s.
 define i64 @f17(i32 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: msr %r2, %r2
 ; CHECK-NEXT: iihf %r2, 1
 ; CHECK: br %r14
@@ -201,7 +201,7 @@ define i64 @f17(i32 %a) {
 
 ; Repeat f17 with the operands reversed.
 define i64 @f18(i32 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: msr %r2, %r2
 ; CHECK-NEXT: iihf %r2, 1
 ; CHECK: br %r14
@@ -213,7 +213,7 @@ define i64 @f18(i32 %a) {
 
 ; The truncation here isn't free; we need an explicit zero extension.
 define i64 @f19(i32 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: llgcr %r2, %r2
 ; CHECK: oihl %r2, 1
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/insert-06.ll b/test/CodeGen/SystemZ/insert-06.ll
index 4a13ef4..8366b2c 100644
--- a/test/CodeGen/SystemZ/insert-06.ll
+++ b/test/CodeGen/SystemZ/insert-06.ll
@@ -4,7 +4,7 @@
 
 ; Insertion of an i32 can be done using LR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; ... and again with the operands reversed.
 define i64 @f2(i64 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -28,7 +28,7 @@ define i64 @f2(i64 %a, i32 %b) {
 
 ; Like f1, but with "in register" zero extension.
 define i64 @f3(i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define i64 @f3(i64 %a, i64 %b) {
 
 ; ... and again with the operands reversed.
 define i64 @f4(i64 %a, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -52,7 +52,7 @@ define i64 @f4(i64 %a, i64 %b) {
 
 ; Unary operations can be done directly into the low half.
 define i64 @f5(i64 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lcr %r2, %r3
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define i64 @f5(i64 %a, i32 %b) {
 
 ; ...likewise three-operand binary operations like RLL.
 define i64 @f6(i64 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: rll %r2, %r3, 1
 ; CHECK: br %r14
@@ -81,7 +81,7 @@ define i64 @f6(i64 %a, i32 %b) {
 ; Loads can be done directly into the low half.  The range of L is checked
 ; in the move tests.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: l %r2, 0(%r3)
 ; CHECK: br %r14
@@ -94,7 +94,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; ...likewise extending loads.
 define i64 @f8(i64 %a, i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: {{%r[23]}}
 ; CHECK: lb %r2, 0(%r3)
 ; CHECK: br %r14
@@ -110,7 +110,7 @@ define i64 @f8(i64 %a, i8 *%src) {
 ; that the upper half of one OR operand and the lower half of the other are
 ; both clear.
 define i64 @f9(i64 %a, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: sllg %r2, %r2, 32
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define i64 @f9(i64 %a, i32 %b) {
 
 ; ...and again with the operands reversed.
 define i64 @f10(i64 %a, i32 %b) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: sllg %r2, %r2, 32
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
@@ -134,7 +134,7 @@ define i64 @f10(i64 %a, i32 %b) {
 
 ; Like f9, but with "in register" zero extension.
 define i64 @f11(i64 %a, i64 %b) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
   %shift = shl i64 %a, 32
@@ -145,7 +145,7 @@ define i64 @f11(i64 %a, i64 %b) {
 
 ; ...and again with the operands reversed.
 define i64 @f12(i64 %a, i64 %b) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
   %shift = shl i64 %a, 32
@@ -156,7 +156,7 @@ define i64 @f12(i64 %a, i64 %b) {
 
 ; Like f9, but for larger shifts than 32.
 define i64 @f13(i64 %a, i32 %b) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: sllg %r2, %r2, 60
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-01.ll b/test/CodeGen/SystemZ/int-add-01.ll
index d12ac22..4114686 100644
--- a/test/CodeGen/SystemZ/int-add-01.ll
+++ b/test/CodeGen/SystemZ/int-add-01.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the AH range.
 define i32 @f1(i32 %lhs, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ah %r2, 0(%r3)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -16,7 +16,7 @@ define i32 @f1(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned AH range.
 define i32 @f2(i32 %lhs, i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ah %r2, 4094(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2047
@@ -28,7 +28,7 @@ define i32 @f2(i32 %lhs, i16 *%src) {
 
 ; Check the next halfword up, which should use AHY instead of AH.
 define i32 @f3(i32 %lhs, i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ahy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2048
@@ -40,7 +40,7 @@ define i32 @f3(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned AHY range.
 define i32 @f4(i32 %lhs, i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ahy %r2, 524286(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -53,7 +53,7 @@ define i32 @f4(i32 %lhs, i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i32 %lhs, i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ah %r2, 0(%r3)
 ; CHECK: br %r14
@@ -66,7 +66,7 @@ define i32 @f5(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the negative aligned AHY range.
 define i32 @f6(i32 %lhs, i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ahy %r2, -2(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -78,7 +78,7 @@ define i32 @f6(i32 %lhs, i16 *%src) {
 
 ; Check the low end of the AHY range.
 define i32 @f7(i32 %lhs, i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ahy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -91,7 +91,7 @@ define i32 @f7(i32 %lhs, i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 %lhs, i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524290
 ; CHECK: ah %r2, 0(%r3)
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f8(i32 %lhs, i16 *%src) {
 
 ; Check that AH allows an index.
 define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ah %r2, 4094({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -118,7 +118,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
 
 ; Check that AHY allows an index.
 define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ahy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/int-add-02.ll b/test/CodeGen/SystemZ/int-add-02.ll
index 568ad1c..4386b5a 100644
--- a/test/CodeGen/SystemZ/int-add-02.ll
+++ b/test/CodeGen/SystemZ/int-add-02.ll
@@ -1,10 +1,13 @@
 ; Test 32-bit addition in which the second operand is variable.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i32 @foo()
 
 ; Check AR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ar %r2, %r3
 ; CHECK: br %r14
   %add = add i32 %a, %b
@@ -13,7 +16,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the A range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: a %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -23,7 +26,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned A range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: a %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -34,7 +37,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use AY instead of A.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ay %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -45,7 +48,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned AY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ay %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -57,7 +60,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: a %r2, 0(%r3)
 ; CHECK: br %r14
@@ -69,7 +72,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned AY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ay %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -80,7 +83,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the AY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ay %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -92,7 +95,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: a %r2, 0(%r3)
 ; CHECK: br %r14
@@ -104,7 +107,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that A allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: a %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -117,7 +120,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that AY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: ay %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -127,3 +130,46 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
   %add = add i32 %a, %b
   ret i32 %add
 }
+
+; Check that additions of spilled values can use A rather than AR.
+define i32 @f12(i32 *%ptr0) {
+; CHECK-LABEL: f12:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: a %r2, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32 *%ptr0, i64 18
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+  %val9 = load i32 *%ptr9
+
+  %ret = call i32 @foo()
+
+  %add0 = add i32 %ret, %val0
+  %add1 = add i32 %add0, %val1
+  %add2 = add i32 %add1, %val2
+  %add3 = add i32 %add2, %val3
+  %add4 = add i32 %add3, %val4
+  %add5 = add i32 %add4, %val5
+  %add6 = add i32 %add5, %val6
+  %add7 = add i32 %add6, %val7
+  %add8 = add i32 %add7, %val8
+  %add9 = add i32 %add8, %val9
+
+  ret i32 %add9
+}
diff --git a/test/CodeGen/SystemZ/int-add-03.ll b/test/CodeGen/SystemZ/int-add-03.ll
index 4610357..56000a8 100644
--- a/test/CodeGen/SystemZ/int-add-03.ll
+++ b/test/CodeGen/SystemZ/int-add-03.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i64 @foo()
+
 ; Check AGFR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: agfr %r2, %r3
 ; CHECK: br %r14
   %bext = sext i32 %b to i64
@@ -14,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; Check AGF with no displacement.
 define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: agf %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +27,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 
 ; Check the high end of the aligned AGF range.
 define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agf %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -38,7 +40,7 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: agf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -51,7 +53,7 @@ define i64 @f4(i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned AGF range.
 define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agf %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -63,7 +65,7 @@ define i64 @f5(i64 %a, i32 *%src) {
 
 ; Check the low end of the AGF range.
 define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agf %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -76,7 +78,7 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524292
 ; CHECK: agf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -89,7 +91,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; Check that AGF allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -100,3 +102,79 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %add = add i64 %a, %bext
   ret i64 %add
 }
+
+; Check that additions of spilled values can use AGF rather than AGFR.
+define i64 @f9(i32 *%ptr0) {
+; CHECK-LABEL: f9:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: agf %r2, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32 *%ptr0, i64 18
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+  %val9 = load i32 *%ptr9
+
+  %frob0 = add i32 %val0, 100
+  %frob1 = add i32 %val1, 100
+  %frob2 = add i32 %val2, 100
+  %frob3 = add i32 %val3, 100
+  %frob4 = add i32 %val4, 100
+  %frob5 = add i32 %val5, 100
+  %frob6 = add i32 %val6, 100
+  %frob7 = add i32 %val7, 100
+  %frob8 = add i32 %val8, 100
+  %frob9 = add i32 %val9, 100
+
+  store i32 %frob0, i32 *%ptr0
+  store i32 %frob1, i32 *%ptr1
+  store i32 %frob2, i32 *%ptr2
+  store i32 %frob3, i32 *%ptr3
+  store i32 %frob4, i32 *%ptr4
+  store i32 %frob5, i32 *%ptr5
+  store i32 %frob6, i32 *%ptr6
+  store i32 %frob7, i32 *%ptr7
+  store i32 %frob8, i32 *%ptr8
+  store i32 %frob9, i32 *%ptr9
+
+  %ret = call i64 @foo()
+
+  %ext0 = sext i32 %frob0 to i64
+  %ext1 = sext i32 %frob1 to i64
+  %ext2 = sext i32 %frob2 to i64
+  %ext3 = sext i32 %frob3 to i64
+  %ext4 = sext i32 %frob4 to i64
+  %ext5 = sext i32 %frob5 to i64
+  %ext6 = sext i32 %frob6 to i64
+  %ext7 = sext i32 %frob7 to i64
+  %ext8 = sext i32 %frob8 to i64
+  %ext9 = sext i32 %frob9 to i64
+
+  %add0 = add i64 %ret, %ext0
+  %add1 = add i64 %add0, %ext1
+  %add2 = add i64 %add1, %ext2
+  %add3 = add i64 %add2, %ext3
+  %add4 = add i64 %add3, %ext4
+  %add5 = add i64 %add4, %ext5
+  %add6 = add i64 %add5, %ext6
+  %add7 = add i64 %add6, %ext7
+  %add8 = add i64 %add7, %ext8
+  %add9 = add i64 %add8, %ext9
+
+  ret i64 %add9
+}
diff --git a/test/CodeGen/SystemZ/int-add-04.ll b/test/CodeGen/SystemZ/int-add-04.ll
index 1c2dc76..675e36b 100644
--- a/test/CodeGen/SystemZ/int-add-04.ll
+++ b/test/CodeGen/SystemZ/int-add-04.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i64 @foo()
+
 ; Check ALGFR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: algfr %r2, %r3
 ; CHECK: br %r14
   %bext = zext i32 %b to i64
@@ -14,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; Check ALGF with no displacement.
 define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: algf %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +27,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 
 ; Check the high end of the aligned ALGF range.
 define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: algf %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -38,7 +40,7 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: algf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -51,7 +53,7 @@ define i64 @f4(i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned ALGF range.
 define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: algf %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -63,7 +65,7 @@ define i64 @f5(i64 %a, i32 *%src) {
 
 ; Check the low end of the ALGF range.
 define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: algf %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -76,7 +78,7 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524292
 ; CHECK: algf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -89,7 +91,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; Check that ALGF allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: algf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -100,3 +102,79 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %add = add i64 %a, %bext
   ret i64 %add
 }
+
+; Check that additions of spilled values can use ALGF rather than ALGFR.
+define i64 @f9(i32 *%ptr0) {
+; CHECK-LABEL: f9:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: algf %r2, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32 *%ptr0, i64 18
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+  %val9 = load i32 *%ptr9
+
+  %frob0 = add i32 %val0, 100
+  %frob1 = add i32 %val1, 100
+  %frob2 = add i32 %val2, 100
+  %frob3 = add i32 %val3, 100
+  %frob4 = add i32 %val4, 100
+  %frob5 = add i32 %val5, 100
+  %frob6 = add i32 %val6, 100
+  %frob7 = add i32 %val7, 100
+  %frob8 = add i32 %val8, 100
+  %frob9 = add i32 %val9, 100
+
+  store i32 %frob0, i32 *%ptr0
+  store i32 %frob1, i32 *%ptr1
+  store i32 %frob2, i32 *%ptr2
+  store i32 %frob3, i32 *%ptr3
+  store i32 %frob4, i32 *%ptr4
+  store i32 %frob5, i32 *%ptr5
+  store i32 %frob6, i32 *%ptr6
+  store i32 %frob7, i32 *%ptr7
+  store i32 %frob8, i32 *%ptr8
+  store i32 %frob9, i32 *%ptr9
+
+  %ret = call i64 @foo()
+
+  %ext0 = zext i32 %frob0 to i64
+  %ext1 = zext i32 %frob1 to i64
+  %ext2 = zext i32 %frob2 to i64
+  %ext3 = zext i32 %frob3 to i64
+  %ext4 = zext i32 %frob4 to i64
+  %ext5 = zext i32 %frob5 to i64
+  %ext6 = zext i32 %frob6 to i64
+  %ext7 = zext i32 %frob7 to i64
+  %ext8 = zext i32 %frob8 to i64
+  %ext9 = zext i32 %frob9 to i64
+
+  %add0 = add i64 %ret, %ext0
+  %add1 = add i64 %add0, %ext1
+  %add2 = add i64 %add1, %ext2
+  %add3 = add i64 %add2, %ext3
+  %add4 = add i64 %add3, %ext4
+  %add5 = add i64 %add4, %ext5
+  %add6 = add i64 %add5, %ext6
+  %add7 = add i64 %add6, %ext7
+  %add8 = add i64 %add7, %ext8
+  %add9 = add i64 %add8, %ext9
+
+  ret i64 %add9
+}
diff --git a/test/CodeGen/SystemZ/int-add-05.ll b/test/CodeGen/SystemZ/int-add-05.ll
index ae32cc4..a05fdd9 100644
--- a/test/CodeGen/SystemZ/int-add-05.ll
+++ b/test/CodeGen/SystemZ/int-add-05.ll
@@ -1,10 +1,13 @@
 ; Test 64-bit addition in which the second operand is variable.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i64 @foo()
 
 ; Check AGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: agr %r2, %r3
 ; CHECK: br %r14
   %add = add i64 %a, %b
@@ -13,7 +16,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check AG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ag %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -23,7 +26,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned AG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ag %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -35,7 +38,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ag %r2, 0(%r3)
 ; CHECK: br %r14
@@ -47,7 +50,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned AG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ag %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -58,7 +61,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the AG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ag %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -70,7 +73,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: ag %r2, 0(%r3)
 ; CHECK: br %r14
@@ -82,7 +85,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that AG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: ag %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -92,3 +95,46 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %add = add i64 %a, %b
   ret i64 %add
 }
+
+; Check that additions of spilled values can use AG rather than AGR.
+define i64 @f9(i64 *%ptr0) {
+; CHECK-LABEL: f9:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: ag %r2, 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64 *%ptr0, i64 18
+
+  %val0 = load i64 *%ptr0
+  %val1 = load i64 *%ptr1
+  %val2 = load i64 *%ptr2
+  %val3 = load i64 *%ptr3
+  %val4 = load i64 *%ptr4
+  %val5 = load i64 *%ptr5
+  %val6 = load i64 *%ptr6
+  %val7 = load i64 *%ptr7
+  %val8 = load i64 *%ptr8
+  %val9 = load i64 *%ptr9
+
+  %ret = call i64 @foo()
+
+  %add0 = add i64 %ret, %val0
+  %add1 = add i64 %add0, %val1
+  %add2 = add i64 %add1, %val2
+  %add3 = add i64 %add2, %val3
+  %add4 = add i64 %add3, %val4
+  %add5 = add i64 %add4, %val5
+  %add6 = add i64 %add5, %val6
+  %add7 = add i64 %add6, %val7
+  %add8 = add i64 %add7, %val8
+  %add9 = add i64 %add8, %val9
+
+  ret i64 %add9
+}
diff --git a/test/CodeGen/SystemZ/int-add-06.ll b/test/CodeGen/SystemZ/int-add-06.ll
index 3a9c698..142c755 100644
--- a/test/CodeGen/SystemZ/int-add-06.ll
+++ b/test/CodeGen/SystemZ/int-add-06.ll
@@ -4,7 +4,7 @@
 
 ; Check additions of 1.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ahi %r2, 1
 ; CHECK: br %r14
   %add = add i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the AHI range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ahi %r2, 32767
 ; CHECK: br %r14
   %add = add i32 %a, 32767
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; Check the next value up, which must use AFI instead.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: afi %r2, 32768
 ; CHECK: br %r14
   %add = add i32 %a, 32768
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; Check the high end of the signed 32-bit range.
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: afi %r2, 2147483647
 ; CHECK: br %r14
   %add = add i32 %a, 2147483647
@@ -40,7 +40,7 @@ define i32 @f4(i32 %a) {
 
 ; Check the next value up, which is treated as a negative value.
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: afi %r2, -2147483648
 ; CHECK: br %r14
   %add = add i32 %a, 2147483648
@@ -49,7 +49,7 @@ define i32 @f5(i32 %a) {
 
 ; Check the high end of the negative AHI range.
 define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ahi %r2, -1
 ; CHECK: br %r14
   %add = add i32 %a, -1
@@ -58,7 +58,7 @@ define i32 @f6(i32 %a) {
 
 ; Check the low end of the AHI range.
 define i32 @f7(i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ahi %r2, -32768
 ; CHECK: br %r14
   %add = add i32 %a, -32768
@@ -67,7 +67,7 @@ define i32 @f7(i32 %a) {
 
 ; Check the next value down, which must use AFI instead.
 define i32 @f8(i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: afi %r2, -32769
 ; CHECK: br %r14
   %add = add i32 %a, -32769
@@ -76,7 +76,7 @@ define i32 @f8(i32 %a) {
 
 ; Check the low end of the signed 32-bit range.
 define i32 @f9(i32 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: afi %r2, -2147483648
 ; CHECK: br %r14
   %add = add i32 %a, -2147483648
@@ -85,7 +85,7 @@ define i32 @f9(i32 %a) {
 
 ; Check the next value down, which is treated as a positive value.
 define i32 @f10(i32 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: afi %r2, 2147483647
 ; CHECK: br %r14
   %add = add i32 %a, -2147483649
diff --git a/test/CodeGen/SystemZ/int-add-07.ll b/test/CodeGen/SystemZ/int-add-07.ll
index a065bb2..e9e0212 100644
--- a/test/CodeGen/SystemZ/int-add-07.ll
+++ b/test/CodeGen/SystemZ/int-add-07.ll
@@ -4,7 +4,7 @@
 
 ; Check additions of 1.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: {{aghi %r2, 1|la %r[0-5], 1\(%r2\)}}
 ; CHECK: br %r14
   %add = add i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the AGHI range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: aghi %r2, 32767
 ; CHECK: br %r14
   %add = add i64 %a, 32767
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; Check the next value up, which must use AGFI instead.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: {{agfi %r2, 32768|lay %r[0-5], 32768\(%r2\)}}
 ; CHECK: br %r14
   %add = add i64 %a, 32768
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check the high end of the AGFI range.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r2, 2147483647
 ; CHECK: br %r14
   %add = add i64 %a, 2147483647
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a) {
 
 ; Check the next value up, which must use ALGFI instead.
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: algfi %r2, 2147483648
 ; CHECK: br %r14
   %add = add i64 %a, 2147483648
@@ -49,7 +49,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the high end of the ALGFI range.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: algfi %r2, 4294967295
 ; CHECK: br %r14
   %add = add i64 %a, 4294967295
@@ -58,7 +58,7 @@ define i64 @f6(i64 %a) {
 
 ; Check the next value up, which must be loaded into a register first.
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llihl %r0, 1
 ; CHECK: agr
 ; CHECK: br %r14
@@ -68,7 +68,7 @@ define i64 @f7(i64 %a) {
 
 ; Check the high end of the negative AGHI range.
 define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, -1
 ; CHECK: br %r14
   %add = add i64 %a, -1
@@ -77,7 +77,7 @@ define i64 @f8(i64 %a) {
 
 ; Check the low end of the AGHI range.
 define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -32768
 ; CHECK: br %r14
   %add = add i64 %a, -32768
@@ -86,7 +86,7 @@ define i64 @f9(i64 %a) {
 
 ; Check the next value down, which must use AGFI instead.
 define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: {{agfi %r2, -32769|lay %r[0-5]+, -32769\(%r2\)}}
 ; CHECK: br %r14
   %add = add i64 %a, -32769
@@ -95,7 +95,7 @@ define i64 @f10(i64 %a) {
 
 ; Check the low end of the AGFI range.
 define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r2, -2147483648
 ; CHECK: br %r14
   %add = add i64 %a, -2147483648
@@ -104,7 +104,7 @@ define i64 @f11(i64 %a) {
 
 ; Check the next value down, which must use SLGFI instead.
 define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: slgfi %r2, 2147483649
 ; CHECK: br %r14
   %add = add i64 %a, -2147483649
@@ -113,7 +113,7 @@ define i64 @f12(i64 %a) {
 
 ; Check the low end of the SLGFI range.
 define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: slgfi %r2, 4294967295
 ; CHECK: br %r14
   %add = add i64 %a, -4294967295
@@ -122,7 +122,7 @@ define i64 @f13(i64 %a) {
 
 ; Check the next value down, which must use register addition instead.
 define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: llihf %r0, 4294967295
 ; CHECK: agr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-08.ll b/test/CodeGen/SystemZ/int-add-08.ll
index b1f820f..bcef914 100644
--- a/test/CodeGen/SystemZ/int-add-08.ll
+++ b/test/CodeGen/SystemZ/int-add-08.ll
@@ -1,10 +1,13 @@
 ; Test 128-bit addition in which the second operand is variable.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i128 *@foo()
 
 ; Test register addition.
 define void @f1(i128 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: algr
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -17,7 +20,7 @@ define void @f1(i128 *%ptr) {
 ; Test memory addition with no offset.  Making the load of %a volatile
 ; should force the memory operand to be %b.
 define void @f2(i128 *%aptr, i64 %addr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: alg {{%r[0-5]}}, 8(%r3)
 ; CHECK: alcg {{%r[0-5]}}, 0(%r3)
 ; CHECK: br %r14
@@ -31,7 +34,7 @@ define void @f2(i128 *%aptr, i64 %addr) {
 
 ; Test the highest aligned offset that is in range of both ALG and ALCG.
 define void @f3(i128 *%aptr, i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: alg {{%r[0-5]}}, 524280(%r3)
 ; CHECK: alcg {{%r[0-5]}}, 524272(%r3)
 ; CHECK: br %r14
@@ -46,7 +49,7 @@ define void @f3(i128 *%aptr, i64 %base) {
 
 ; Test the next doubleword up, which requires separate address logic for ALG.
 define void @f4(i128 *%aptr, i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgr [[BASE:%r[1-5]]], %r3
 ; CHECK: agfi [[BASE]], 524288
 ; CHECK: alg {{%r[0-5]}}, 0([[BASE]])
@@ -65,7 +68,7 @@ define void @f4(i128 *%aptr, i64 %base) {
 ; both instructions.  It would be better to create an anchor at 524288
 ; that both instructions can use, but that isn't implemented yet.
 define void @f5(i128 *%aptr, i64 %base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: alg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: br %r14
@@ -80,7 +83,7 @@ define void @f5(i128 *%aptr, i64 %base) {
 
 ; Test the lowest displacement that is in range of both ALG and ALCG.
 define void @f6(i128 *%aptr, i64 %base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: alg {{%r[0-5]}}, -524280(%r3)
 ; CHECK: alcg {{%r[0-5]}}, -524288(%r3)
 ; CHECK: br %r14
@@ -95,7 +98,7 @@ define void @f6(i128 *%aptr, i64 %base) {
 
 ; Test the next doubleword down, which is out of range of the ALCG.
 define void @f7(i128 *%aptr, i64 %base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: alg {{%r[0-5]}}, -524288(%r3)
 ; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: br %r14
@@ -108,3 +111,34 @@ define void @f7(i128 *%aptr, i64 %base) {
   ret void
 }
 
+; Check that additions of spilled values can use ALG and ALCG rather than
+; ALGR and ALCGR.
+define void @f8(i128 *%ptr0) {
+; CHECK-LABEL: f8:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: alg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: alcg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i128 *%ptr0, i128 2
+  %ptr2 = getelementptr i128 *%ptr0, i128 4
+  %ptr3 = getelementptr i128 *%ptr0, i128 6
+  %ptr4 = getelementptr i128 *%ptr0, i128 8
+
+  %val0 = load i128 *%ptr0
+  %val1 = load i128 *%ptr1
+  %val2 = load i128 *%ptr2
+  %val3 = load i128 *%ptr3
+  %val4 = load i128 *%ptr4
+
+  %retptr = call i128 *@foo()
+
+  %ret = load i128 *%retptr
+  %add0 = add i128 %ret, %val0
+  %add1 = add i128 %add0, %val1
+  %add2 = add i128 %add1, %val2
+  %add3 = add i128 %add2, %val3
+  %add4 = add i128 %add3, %val4
+  store i128 %add4, i128 *%retptr
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/int-add-09.ll b/test/CodeGen/SystemZ/int-add-09.ll
index bfe6338..717fed0 100644
--- a/test/CodeGen/SystemZ/int-add-09.ll
+++ b/test/CodeGen/SystemZ/int-add-09.ll
@@ -1,11 +1,11 @@
 ; Test 128-bit addition in which the second operand is constant.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
 
 ; Check additions of 1.  The XOR ensures that we don't instead load the
 ; constant into a register and use memory addition.
 define void @f1(i128 *%aptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: algfi {{%r[0-5]}}, 1
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define void @f1(i128 *%aptr) {
 
 ; Check the high end of the ALGFI range.
 define void @f2(i128 *%aptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: algfi {{%r[0-5]}}, 4294967295
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define void @f2(i128 *%aptr) {
 
 ; Check the next value up, which must use register addition.
 define void @f3(i128 *%aptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: algr
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ define void @f3(i128 *%aptr) {
 
 ; Check addition of -1, which must also use register addition.
 define void @f4(i128 *%aptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: algr
 ; CHECK: alcgr
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-10.ll b/test/CodeGen/SystemZ/int-add-10.ll
index 17cfdbe..66a275b 100644
--- a/test/CodeGen/SystemZ/int-add-10.ll
+++ b/test/CodeGen/SystemZ/int-add-10.ll
@@ -5,7 +5,7 @@
 ; Check register additions.  The XOR ensures that we don't instead zero-extend
 ; %b into a register and use memory addition.
 define void @f1(i128 *%aptr, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: algfr {{%r[0-5]}}, %r3
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -19,7 +19,7 @@ define void @f1(i128 *%aptr, i32 %b) {
 
 ; Like f1, but using an "in-register" extension.
 define void @f2(i128 *%aptr, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: algfr {{%r[0-5]}}, %r3
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define void @f2(i128 *%aptr, i64 %b) {
 ; Test register addition in cases where the second operand is zero extended
 ; from i64 rather than i32, but is later masked to i32 range.
 define void @f3(i128 *%aptr, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: algfr {{%r[0-5]}}, %r3
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define void @f3(i128 *%aptr, i64 %b) {
 
 ; Test ALGF with no offset.
 define void @f4(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: algf {{%r[0-5]}}, 0(%r3)
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define void @f4(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the high end of the ALGF range.
 define void @f5(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: algf {{%r[0-5]}}, 524284(%r3)
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -82,7 +82,7 @@ define void @f5(i128 *%aptr, i32 *%bsrc) {
 ; Check the next word up, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: algf {{%r[0-5]}}, 0(%r3)
 ; CHECK: alcgr
@@ -99,7 +99,7 @@ define void @f6(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the high end of the negative aligned ALGF range.
 define void @f7(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: algf {{%r[0-5]}}, -4(%r3)
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -115,7 +115,7 @@ define void @f7(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the low end of the ALGF range.
 define void @f8(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: algf {{%r[0-5]}}, -524288(%r3)
 ; CHECK: alcgr
 ; CHECK: br %r14
@@ -132,7 +132,7 @@ define void @f8(i128 *%aptr, i32 *%bsrc) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: algf {{%r[0-5]}}, 0(%r3)
 ; CHECK: alcgr
@@ -149,7 +149,7 @@ define void @f9(i128 *%aptr, i32 *%bsrc) {
 
 ; Check that ALGF allows an index.
 define void @f10(i128 *%aptr, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: algf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %a = load i128 *%aptr
diff --git a/test/CodeGen/SystemZ/int-add-11.ll b/test/CodeGen/SystemZ/int-add-11.ll
index 47a776e..6c617ba 100644
--- a/test/CodeGen/SystemZ/int-add-11.ll
+++ b/test/CodeGen/SystemZ/int-add-11.ll
@@ -4,7 +4,7 @@
 
 ; Check additions of 1.
 define void @f1(i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: asi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i32 *%ptr) {
 
 ; Check the high end of the constant range.
 define void @f2(i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: asi 0(%r2), 127
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -27,7 +27,7 @@ define void @f2(i32 *%ptr) {
 ; Check the next constant up, which must use an addition and a store.
 ; Both L/AHI and LHI/A would be OK.
 define void @f3(i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: asi
 ; CHECK: st %r0, 0(%r2)
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define void @f3(i32 *%ptr) {
 
 ; Check the low end of the constant range.
 define void @f4(i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: asi 0(%r2), -128
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -50,7 +50,7 @@ define void @f4(i32 *%ptr) {
 
 ; Check the next value down, with the same comment as f3.
 define void @f5(i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: asi
 ; CHECK: st %r0, 0(%r2)
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define void @f5(i32 *%ptr) {
 
 ; Check the high end of the aligned ASI range.
 define void @f6(i32 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: asi 524284(%r2), 1
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%base, i64 131071
@@ -75,7 +75,7 @@ define void @f6(i32 *%base) {
 ; Check the next word up, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f7(i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r2, 524288
 ; CHECK: asi 0(%r2), 1
 ; CHECK: br %r14
@@ -88,7 +88,7 @@ define void @f7(i32 *%base) {
 
 ; Check the low end of the ASI range.
 define void @f8(i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: asi -524288(%r2), 1
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%base, i64 -131072
@@ -101,7 +101,7 @@ define void @f8(i32 *%base) {
 ; Check the next word down, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524292
 ; CHECK: asi 0(%r2), 1
 ; CHECK: br %r14
@@ -114,7 +114,7 @@ define void @f9(i32 *%base) {
 
 ; Check that ASI does not allow indices.
 define void @f10(i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr %r2, %r3
 ; CHECK: asi 4(%r2), 1
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-12.ll b/test/CodeGen/SystemZ/int-add-12.ll
index ae1c1f7..ef4dc39 100644
--- a/test/CodeGen/SystemZ/int-add-12.ll
+++ b/test/CodeGen/SystemZ/int-add-12.ll
@@ -4,7 +4,7 @@
 
 ; Check additions of 1.
 define void @f1(i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: agsi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i64 *%ptr) {
 
 ; Check the high end of the constant range.
 define void @f2(i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: agsi 0(%r2), 127
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -27,7 +27,7 @@ define void @f2(i64 *%ptr) {
 ; Check the next constant up, which must use an addition and a store.
 ; Both LG/AGHI and LGHI/AG would be OK.
 define void @f3(i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: agsi
 ; CHECK: stg %r0, 0(%r2)
 ; CHECK: br %r14
@@ -39,7 +39,7 @@ define void @f3(i64 *%ptr) {
 
 ; Check the low end of the constant range.
 define void @f4(i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agsi 0(%r2), -128
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -50,7 +50,7 @@ define void @f4(i64 *%ptr) {
 
 ; Check the next value down, with the same comment as f3.
 define void @f5(i64 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: agsi
 ; CHECK: stg %r0, 0(%r2)
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define void @f5(i64 *%ptr) {
 
 ; Check the high end of the aligned AGSI range.
 define void @f6(i64 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agsi 524280(%r2), 1
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%base, i64 65535
@@ -75,7 +75,7 @@ define void @f6(i64 *%base) {
 ; Check the next doubleword up, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f7(i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r2, 524288
 ; CHECK: agsi 0(%r2), 1
 ; CHECK: br %r14
@@ -88,7 +88,7 @@ define void @f7(i64 *%base) {
 
 ; Check the low end of the AGSI range.
 define void @f8(i64 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agsi -524288(%r2), 1
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%base, i64 -65536
@@ -101,7 +101,7 @@ define void @f8(i64 *%base) {
 ; Check the next doubleword down, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i64 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524296
 ; CHECK: agsi 0(%r2), 1
 ; CHECK: br %r14
@@ -114,7 +114,7 @@ define void @f9(i64 *%base) {
 
 ; Check that AGSI does not allow indices.
 define void @f10(i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr %r2, %r3
 ; CHECK: agsi 8(%r2), 1
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-add-13.ll b/test/CodeGen/SystemZ/int-add-13.ll
new file mode 100644
index 0000000..7dfabbc
--- /dev/null
+++ b/test/CodeGen/SystemZ/int-add-13.ll
@@ -0,0 +1,39 @@
+; Test the three-operand forms of addition.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check ARK.
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f1:
+; CHECK: ark %r2, %r3, %r4
+; CHECK: br %r14
+  %add = add i32 %b, %c
+  ret i32 %add
+}
+
+; Check that we can still use AR in obvious cases.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: ar %r2, %r3
+; CHECK: br %r14
+  %add = add i32 %a, %b
+  ret i32 %add
+}
+
+; Check AGRK.
+define i64 @f3(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f3:
+; CHECK: agrk %r2, %r3, %r4
+; CHECK: br %r14
+  %add = add i64 %b, %c
+  ret i64 %add
+}
+
+; Check that we can still use AGR in obvious cases.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: agr %r2, %r3
+; CHECK: br %r14
+  %add = add i64 %a, %b
+  ret i64 %add
+}
diff --git a/test/CodeGen/SystemZ/int-add-14.ll b/test/CodeGen/SystemZ/int-add-14.ll
new file mode 100644
index 0000000..0732378
--- /dev/null
+++ b/test/CodeGen/SystemZ/int-add-14.ll
@@ -0,0 +1,67 @@
+; Test 32-bit addition in which the second operand is constant and in which
+; three-operand forms are available.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check additions of 1.
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK-LABEL: f1:
+; CHECK: ahik %r2, %r3, 1
+; CHECK: br %r14
+  %add = add i32 %b, 1
+  ret i32 %add
+}
+
+; Check the high end of the AHIK range.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: ahik %r2, %r3, 32767
+; CHECK: br %r14
+  %add = add i32 %b, 32767
+  ret i32 %add
+}
+
+; Check the next value up, which must use AFI instead.
+define i32 @f3(i32 %a, i32 %b) {
+; CHECK-LABEL: f3:
+; CHECK: afi {{%r[0-5]}}, 32768
+; CHECK: br %r14
+  %add = add i32 %b, 32768
+  ret i32 %add
+}
+
+; Check the high end of the negative AHIK range.
+define i32 @f4(i32 %a, i32 %b) {
+; CHECK-LABEL: f4:
+; CHECK: ahik %r2, %r3, -1
+; CHECK: br %r14
+  %add = add i32 %b, -1
+  ret i32 %add
+}
+
+; Check the low end of the AHIK range.
+define i32 @f5(i32 %a, i32 %b) {
+; CHECK-LABEL: f5:
+; CHECK: ahik %r2, %r3, -32768
+; CHECK: br %r14
+  %add = add i32 %b, -32768
+  ret i32 %add
+}
+
+; Check the next value down, which must use AFI instead.
+define i32 @f6(i32 %a, i32 %b) {
+; CHECK-LABEL: f6:
+; CHECK: afi {{%r[0-5]}}, -32769
+; CHECK: br %r14
+  %add = add i32 %b, -32769
+  ret i32 %add
+}
+
+; Check that AHI is still used in obvious cases.
+define i32 @f7(i32 %a) {
+; CHECK-LABEL: f7:
+; CHECK: ahi %r2, 1
+; CHECK: br %r14
+  %add = add i32 %a, 1
+  ret i32 %add
+}
diff --git a/test/CodeGen/SystemZ/int-add-15.ll b/test/CodeGen/SystemZ/int-add-15.ll
new file mode 100644
index 0000000..041ec19
--- /dev/null
+++ b/test/CodeGen/SystemZ/int-add-15.ll
@@ -0,0 +1,67 @@
+; Test 64-bit addition in which the second operand is constant and in which
+; three-operand forms are available.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check additions of 1.
+define i64 @f1(i64 %a, i64 %b) {
+; CHECK-LABEL: f1:
+; CHECK: {{aghik %r2, %r3, 1|la %r2, 1\(%r3\)}}
+; CHECK: br %r14
+  %add = add i64 %b, 1
+  ret i64 %add
+}
+
+; Check the high end of the AGHIK range.
+define i64 @f2(i64 %a, i64 %b) {
+; CHECK-LABEL: f2:
+; CHECK: aghik %r2, %r3, 32767
+; CHECK: br %r14
+  %add = add i64 %b, 32767
+  ret i64 %add
+}
+
+; Check the next value up, which must use AGFI instead.
+define i64 @f3(i64 %a, i64 %b) {
+; CHECK-LABEL: f3:
+; CHECK: {{agfi %r[0-5], 32768|lay %r2, 32768\(%r3\)}}
+; CHECK: br %r14
+  %add = add i64 %b, 32768
+  ret i64 %add
+}
+
+; Check the high end of the negative AGHIK range.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: aghik %r2, %r3, -1
+; CHECK: br %r14
+  %add = add i64 %b, -1
+  ret i64 %add
+}
+
+; Check the low end of the AGHIK range.
+define i64 @f5(i64 %a, i64 %b) {
+; CHECK-LABEL: f5:
+; CHECK: aghik %r2, %r3, -32768
+; CHECK: br %r14
+  %add = add i64 %b, -32768
+  ret i64 %add
+}
+
+; Check the next value down, which must use AGFI instead.
+define i64 @f6(i64 %a, i64 %b) {
+; CHECK-LABEL: f6:
+; CHECK: {{agfi %r[0-5], -32769|lay %r2, -32769\(%r3\)}}
+; CHECK: br %r14
+  %add = add i64 %b, -32769
+  ret i64 %add
+}
+
+; Check that AGHI is still used in obvious cases.
+define i64 @f7(i64 %a) {
+; CHECK-LABEL: f7:
+; CHECK: aghi %r2, 32000
+; CHECK: br %r14
+  %add = add i64 %a, 32000
+  ret i64 %add
+}
diff --git a/test/CodeGen/SystemZ/int-add-16.ll b/test/CodeGen/SystemZ/int-add-16.ll
new file mode 100644
index 0000000..36cc13e
--- /dev/null
+++ b/test/CodeGen/SystemZ/int-add-16.ll
@@ -0,0 +1,93 @@
+; Test 128-bit addition when the distinct-operands facility is available.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Test the case where both operands are in registers.
+define i64 @f1(i64 %a, i64 %b, i64 %c, i64 %d, i64 *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: algrk %r2, %r4, %r5
+; CHECK: alcgr
+; CHECK: br %r14
+  %x1 = insertelement <2 x i64> undef, i64 %b, i32 0
+  %x2 = insertelement <2 x i64> %x1, i64 %c, i32 1
+  %x = bitcast <2 x i64> %x2 to i128
+  %y2 = insertelement <2 x i64> %x1, i64 %d, i32 1
+  %y = bitcast <2 x i64> %y2 to i128
+  %add = add i128 %x, %y
+  %addv = bitcast i128 %add to <2 x i64>
+  %high = extractelement <2 x i64> %addv, i32 0
+  store i64 %high, i64 *%ptr
+  %low = extractelement <2 x i64> %addv, i32 1
+  ret i64 %low
+}
+
+; Test addition of 1.
+define void @f2(i64 %a, i64 %b, i128 *%ptr) {
+; CHECK-LABEL: f2:
+; CHECK: alghsik {{%r[0-5]}}, %r3, 1
+; CHECK: alcgr
+; CHECK: br %r14
+  %x1 = insertelement <2 x i64> undef, i64 %a, i32 0
+  %x2 = insertelement <2 x i64> %x1, i64 %b, i32 1
+  %x = bitcast <2 x i64> %x2 to i128
+  %add = add i128 %x, 1
+  store i128 %add, i128 *%ptr
+  ret void
+}
+
+; Test the upper end of the ALGHSIK range.
+define void @f3(i64 %a, i64 %b, i128 *%ptr) {
+; CHECK-LABEL: f3:
+; CHECK: alghsik {{%r[0-5]}}, %r3, 32767
+; CHECK: alcgr
+; CHECK: br %r14
+  %x1 = insertelement <2 x i64> undef, i64 %a, i32 0
+  %x2 = insertelement <2 x i64> %x1, i64 %b, i32 1
+  %x = bitcast <2 x i64> %x2 to i128
+  %add = add i128 %x, 32767
+  store i128 %add, i128 *%ptr
+  ret void
+}
+
+; Test the next value up, which should use ALGFI instead.
+define void @f4(i64 %a, i64 %b, i128 *%ptr) {
+; CHECK-LABEL: f4:
+; CHECK: algfi %r3, 32768
+; CHECK: alcgr
+; CHECK: br %r14
+  %x1 = insertelement <2 x i64> undef, i64 %a, i32 0
+  %x2 = insertelement <2 x i64> %x1, i64 %b, i32 1
+  %x = bitcast <2 x i64> %x2 to i128
+  %add = add i128 %x, 32768
+  store i128 %add, i128 *%ptr
+  ret void
+}
+
+; Test the lower end of the ALGHSIK range.
+define void @f5(i64 %a, i64 %b, i128 *%ptr) {
+; CHECK-LABEL: f5:
+; CHECK: alghsik {{%r[0-5]}}, %r3, -32768
+; CHECK: alcgr
+; CHECK: br %r14
+  %x1 = insertelement <2 x i64> undef, i64 %a, i32 0
+  %x2 = insertelement <2 x i64> %x1, i64 %b, i32 1
+  %x = bitcast <2 x i64> %x2 to i128
+  %add = add i128 %x, -32768
+  store i128 %add, i128 *%ptr
+  ret void
+}
+
+; Test the next value down, which cannot use either ALGHSIK or ALGFI.
+define void @f6(i64 %a, i64 %b, i128 *%ptr) {
+; CHECK-LABEL: f6:
+; CHECK-NOT: alghsik
+; CHECK-NOT: algfi
+; CHECK: alcgr
+; CHECK: br %r14
+  %x1 = insertelement <2 x i64> undef, i64 %a, i32 0
+  %x2 = insertelement <2 x i64> %x1, i64 %b, i32 1
+  %x = bitcast <2 x i64> %x2 to i128
+  %add = add i128 %x, -32769
+  store i128 %add, i128 *%ptr
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/int-cmp-01.ll b/test/CodeGen/SystemZ/int-cmp-01.ll
index aa432f0..dbfe0df 100644
--- a/test/CodeGen/SystemZ/int-cmp-01.ll
+++ b/test/CodeGen/SystemZ/int-cmp-01.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the CH range.
 define void @f1(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ch %r2, 0(%r3)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -18,7 +18,7 @@ define void @f1(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check the high end of the aligned CH range.
 define void @f2(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ch %r2, 4094(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2047
@@ -32,7 +32,7 @@ define void @f2(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check the next halfword up, which should use CHY instead of CH.
 define void @f3(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: chy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2048
@@ -46,7 +46,7 @@ define void @f3(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check the high end of the aligned CHY range.
 define void @f4(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: chy %r2, 524286(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -61,7 +61,7 @@ define void @f4(i32 %lhs, i16 *%src, i32 *%dst) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f5(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ch %r2, 0(%r3)
 ; CHECK: br %r14
@@ -76,7 +76,7 @@ define void @f5(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check the high end of the negative aligned CHY range.
 define void @f6(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: chy %r2, -2(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -90,7 +90,7 @@ define void @f6(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check the low end of the CHY range.
 define void @f7(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: chy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -105,7 +105,7 @@ define void @f7(i32 %lhs, i16 *%src, i32 *%dst) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524290
 ; CHECK: ch %r2, 0(%r3)
 ; CHECK: br %r14
@@ -120,7 +120,7 @@ define void @f8(i32 %lhs, i16 *%src, i32 *%dst) {
 
 ; Check that CH allows an index.
 define void @f9(i32 %lhs, i64 %base, i64 %index, i32 *%dst) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ch %r2, 4094({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
@@ -136,7 +136,7 @@ define void @f9(i32 %lhs, i64 %base, i64 %index, i32 *%dst) {
 
 ; Check that CHY allows an index.
 define void @f10(i32 %lhs, i64 %base, i64 %index, i32 *%dst) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: chy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
diff --git a/test/CodeGen/SystemZ/int-cmp-02.ll b/test/CodeGen/SystemZ/int-cmp-02.ll
index b98661e..26e1391 100644
--- a/test/CodeGen/SystemZ/int-cmp-02.ll
+++ b/test/CodeGen/SystemZ/int-cmp-02.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i32 @foo()
+
 ; Check register comparison.
 define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: crjl %r2, %r3
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +17,7 @@ define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
 
 ; Check the low end of the C range.
 define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: c %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -28,7 +30,7 @@ define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
 
 ; Check the high end of the aligned C range.
 define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: c %r2, 4092(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -42,7 +44,7 @@ define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the next word up, which should use CY instead of C.
 define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cy %r2, 4096(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -56,7 +58,7 @@ define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the high end of the aligned CY range.
 define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cy %r2, 524284(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -71,7 +73,7 @@ define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: c %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -86,7 +88,7 @@ define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the high end of the negative aligned CY range.
 define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cy %r2, -4(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -100,7 +102,7 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the low end of the CY range.
 define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cy %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -115,7 +117,7 @@ define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: c %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -130,7 +132,7 @@ define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check that C allows an index.
 define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: c %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -146,7 +148,7 @@ define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
 
 ; Check that CY allows an index.
 define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -159,3 +161,23 @@ define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
+
+; The first branch here got recreated by InsertBranch while splitting the
+; critical edge %entry->%while.body, which lost the kills information for CC.
+define void @f12(i32 %a, i32 %b) {
+; CHECK-LABEL: f12:
+; CHECK: cije %r2, 0
+; CHECK: crjlh %r2,
+; CHECK: br %r14
+entry:
+  %cmp11 = icmp eq i32 %a, 0
+  br i1 %cmp11, label %while.end, label %while.body
+
+while.body:
+  %c = call i32 @foo()
+  %cmp12 = icmp eq i32 %c, %b
+  br i1 %cmp12, label %while.end, label %while.body
+
+while.end:
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/int-cmp-03.ll b/test/CodeGen/SystemZ/int-cmp-03.ll
index bd802bc..2d679cf 100644
--- a/test/CodeGen/SystemZ/int-cmp-03.ll
+++ b/test/CodeGen/SystemZ/int-cmp-03.ll
@@ -4,7 +4,7 @@
 
 ; Check register comparison.
 define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clr %r2, %r3
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -16,7 +16,7 @@ define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
 
 ; Check the low end of the CL range.
 define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cl %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -29,7 +29,7 @@ define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
 
 ; Check the high end of the aligned CL range.
 define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cl %r2, 4092(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the next word up, which should use CLY instead of CL.
 define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cly %r2, 4096(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -57,7 +57,7 @@ define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the high end of the aligned CLY range.
 define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cly %r2, 524284(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -72,7 +72,7 @@ define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cl %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -87,7 +87,7 @@ define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the high end of the negative aligned CLY range.
 define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cly %r2, -4(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -101,7 +101,7 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the low end of the CLY range.
 define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cly %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -116,7 +116,7 @@ define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: cl %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -131,7 +131,7 @@ define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check that CL allows an index.
 define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cl %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -147,7 +147,7 @@ define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
 
 ; Check that CLY allows an index.
 define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cly %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-04.ll b/test/CodeGen/SystemZ/int-cmp-04.ll
index d0625fb..54c4b5b 100644
--- a/test/CodeGen/SystemZ/int-cmp-04.ll
+++ b/test/CodeGen/SystemZ/int-cmp-04.ll
@@ -5,7 +5,7 @@
 
 ; Check CGH with no displacement.
 define void @f1(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgh %r2, 0(%r3)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -18,7 +18,7 @@ define void @f1(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check the high end of the aligned CGH range.
 define void @f2(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cgh %r2, 524286(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -33,7 +33,7 @@ define void @f2(i64 %lhs, i16 *%src, i64 *%dst) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f3(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cgh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define void @f3(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check the high end of the negative aligned CGH range.
 define void @f4(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cgh %r2, -2(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -62,7 +62,7 @@ define void @f4(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check the low end of the CGH range.
 define void @f5(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cgh %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -77,7 +77,7 @@ define void @f5(i64 %lhs, i16 *%src, i64 *%dst) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, -524290
 ; CHECK: cgh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -92,7 +92,7 @@ define void @f6(i64 %lhs, i16 *%src, i64 *%dst) {
 
 ; Check that CGH allows an index.
 define void @f7(i64 %lhs, i64 %base, i64 %index, i64 *%dst) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cgh %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %base, %index
diff --git a/test/CodeGen/SystemZ/int-cmp-05.ll b/test/CodeGen/SystemZ/int-cmp-05.ll
index 38cd1a5..36d12a5 100644
--- a/test/CodeGen/SystemZ/int-cmp-05.ll
+++ b/test/CodeGen/SystemZ/int-cmp-05.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i64 @foo()
+
 ; Check signed register comparison.
 define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgfr %r2, %r3
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -17,7 +19,7 @@ define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; Check unsigned register comparison, which can't use CGFR.
 define double @f2(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: cgfr
 ; CHECK: br %r14
   %i2 = sext i32 %unext to i64
@@ -28,7 +30,7 @@ define double @f2(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; Check register equality.
 define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cgfr %r2, %r3
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -41,7 +43,7 @@ define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; Check register inequality.
 define double @f4(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cgfr %r2, %r3
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -54,7 +56,7 @@ define double @f4(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; Check signed comparisonn with memory.
 define double @f5(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -68,7 +70,7 @@ define double @f5(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check unsigned comparison with memory.
 define double @f6(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: cgf
 ; CHECK: br %r14
   %unext = load i32 *%ptr
@@ -80,7 +82,7 @@ define double @f6(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check memory equality.
 define double @f7(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cgf %r2, 0(%r3)
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -94,7 +96,7 @@ define double @f7(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check memory inequality.
 define double @f8(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cgf %r2, 0(%r3)
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -108,7 +110,7 @@ define double @f8(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check the high end of the aligned CGF range.
 define double @f9(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cgf %r2, 524284(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -124,7 +126,7 @@ define double @f9(double %a, double %b, i64 %i1, i32 *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f10(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -140,7 +142,7 @@ define double @f10(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check the high end of the negative aligned CGF range.
 define double @f11(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cgf %r2, -4(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -155,7 +157,7 @@ define double @f11(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check the low end of the CGF range.
 define double @f12(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cgf %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -171,7 +173,7 @@ define double @f12(double %a, double %b, i64 %i1, i32 *%base) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agfi %r3, -524292
 ; CHECK: cgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -187,7 +189,7 @@ define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check that CGF allows an index.
 define double @f14(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cgf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -201,3 +203,90 @@ define double @f14(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
+
+; Check that comparisons of spilled values can use CGF rather than CGFR.
+define i64 @f15(i32 *%ptr0) {
+; CHECK-LABEL: f15:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: cgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32 *%ptr0, i64 18
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+  %val9 = load i32 *%ptr9
+
+  %frob0 = add i32 %val0, 100
+  %frob1 = add i32 %val1, 100
+  %frob2 = add i32 %val2, 100
+  %frob3 = add i32 %val3, 100
+  %frob4 = add i32 %val4, 100
+  %frob5 = add i32 %val5, 100
+  %frob6 = add i32 %val6, 100
+  %frob7 = add i32 %val7, 100
+  %frob8 = add i32 %val8, 100
+  %frob9 = add i32 %val9, 100
+
+  store i32 %frob0, i32 *%ptr0
+  store i32 %frob1, i32 *%ptr1
+  store i32 %frob2, i32 *%ptr2
+  store i32 %frob3, i32 *%ptr3
+  store i32 %frob4, i32 *%ptr4
+  store i32 %frob5, i32 *%ptr5
+  store i32 %frob6, i32 *%ptr6
+  store i32 %frob7, i32 *%ptr7
+  store i32 %frob8, i32 *%ptr8
+  store i32 %frob9, i32 *%ptr9
+
+  %ret = call i64 @foo()
+
+  %ext0 = sext i32 %frob0 to i64
+  %ext1 = sext i32 %frob1 to i64
+  %ext2 = sext i32 %frob2 to i64
+  %ext3 = sext i32 %frob3 to i64
+  %ext4 = sext i32 %frob4 to i64
+  %ext5 = sext i32 %frob5 to i64
+  %ext6 = sext i32 %frob6 to i64
+  %ext7 = sext i32 %frob7 to i64
+  %ext8 = sext i32 %frob8 to i64
+  %ext9 = sext i32 %frob9 to i64
+
+  %cmp0 = icmp slt i64 %ret, %ext0
+  %cmp1 = icmp slt i64 %ret, %ext1
+  %cmp2 = icmp slt i64 %ret, %ext2
+  %cmp3 = icmp slt i64 %ret, %ext3
+  %cmp4 = icmp slt i64 %ret, %ext4
+  %cmp5 = icmp slt i64 %ret, %ext5
+  %cmp6 = icmp slt i64 %ret, %ext6
+  %cmp7 = icmp slt i64 %ret, %ext7
+  %cmp8 = icmp slt i64 %ret, %ext8
+  %cmp9 = icmp slt i64 %ret, %ext9
+
+  %sel0 = select i1 %cmp0, i64 %ret, i64 0
+  %sel1 = select i1 %cmp1, i64 %sel0, i64 1
+  %sel2 = select i1 %cmp2, i64 %sel1, i64 2
+  %sel3 = select i1 %cmp3, i64 %sel2, i64 3
+  %sel4 = select i1 %cmp4, i64 %sel3, i64 4
+  %sel5 = select i1 %cmp5, i64 %sel4, i64 5
+  %sel6 = select i1 %cmp6, i64 %sel5, i64 6
+  %sel7 = select i1 %cmp7, i64 %sel6, i64 7
+  %sel8 = select i1 %cmp8, i64 %sel7, i64 8
+  %sel9 = select i1 %cmp9, i64 %sel8, i64 9
+
+  ret i64 %sel9
+}
diff --git a/test/CodeGen/SystemZ/int-cmp-06.ll b/test/CodeGen/SystemZ/int-cmp-06.ll
index efb6ad8..cdd6114 100644
--- a/test/CodeGen/SystemZ/int-cmp-06.ll
+++ b/test/CodeGen/SystemZ/int-cmp-06.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i64 @foo()
+
 ; Check unsigned register comparison.
 define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -17,7 +19,7 @@ define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; ...and again with a different representation.
 define double @f2(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -30,7 +32,7 @@ define double @f2(double %a, double %b, i64 %i1, i64 %unext) {
 
 ; Check signed register comparison, which can't use CLGFR.
 define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clgfr
 ; CHECK: br %r14
   %i2 = zext i32 %unext to i64
@@ -41,7 +43,7 @@ define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; ...and again with a different representation
 define double @f4(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: clgfr
 ; CHECK: br %r14
   %i2 = and i64 %unext, 4294967295
@@ -52,7 +54,7 @@ define double @f4(double %a, double %b, i64 %i1, i64 %unext) {
 
 ; Check register equality.
 define double @f5(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -65,7 +67,7 @@ define double @f5(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; ...and again with a different representation
 define double @f6(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -78,7 +80,7 @@ define double @f6(double %a, double %b, i64 %i1, i64 %unext) {
 
 ; Check register inequality.
 define double @f7(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -91,7 +93,7 @@ define double @f7(double %a, double %b, i64 %i1, i32 %unext) {
 
 ; ...and again with a different representation
 define double @f8(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clgfr %r2, %r3
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -104,7 +106,7 @@ define double @f8(double %a, double %b, i64 %i1, i64 %unext) {
 
 ; Check unsigned comparisonn with memory.
 define double @f9(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: clgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -118,7 +120,7 @@ define double @f9(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check signed comparison with memory.
 define double @f10(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: clgf
 ; CHECK: br %r14
   %unext = load i32 *%ptr
@@ -130,7 +132,7 @@ define double @f10(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check memory equality.
 define double @f11(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: clgf %r2, 0(%r3)
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -144,7 +146,7 @@ define double @f11(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check memory inequality.
 define double @f12(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: clgf %r2, 0(%r3)
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -158,7 +160,7 @@ define double @f12(double %a, double %b, i64 %i1, i32 *%ptr) {
 
 ; Check the high end of the aligned CLGF range.
 define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: clgf %r2, 524284(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -174,7 +176,7 @@ define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f14(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: agfi %r3, 524288
 ; CHECK: clgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -190,7 +192,7 @@ define double @f14(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check the high end of the negative aligned CLGF range.
 define double @f15(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: clgf %r2, -4(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -205,7 +207,7 @@ define double @f15(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check the low end of the CLGF range.
 define double @f16(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: clgf %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -221,7 +223,7 @@ define double @f16(double %a, double %b, i64 %i1, i32 *%base) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f17(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: agfi %r3, -524292
 ; CHECK: clgf %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -237,7 +239,7 @@ define double @f17(double %a, double %b, i64 %i1, i32 *%base) {
 
 ; Check that CLGF allows an index.
 define double @f18(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: clgf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -251,3 +253,90 @@ define double @f18(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
+
+; Check that comparisons of spilled values can use CLGF rather than CLGFR.
+define i64 @f19(i32 *%ptr0) {
+; CHECK-LABEL: f19:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: clgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32 *%ptr0, i64 18
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+  %val9 = load i32 *%ptr9
+
+  %frob0 = add i32 %val0, 100
+  %frob1 = add i32 %val1, 100
+  %frob2 = add i32 %val2, 100
+  %frob3 = add i32 %val3, 100
+  %frob4 = add i32 %val4, 100
+  %frob5 = add i32 %val5, 100
+  %frob6 = add i32 %val6, 100
+  %frob7 = add i32 %val7, 100
+  %frob8 = add i32 %val8, 100
+  %frob9 = add i32 %val9, 100
+
+  store i32 %frob0, i32 *%ptr0
+  store i32 %frob1, i32 *%ptr1
+  store i32 %frob2, i32 *%ptr2
+  store i32 %frob3, i32 *%ptr3
+  store i32 %frob4, i32 *%ptr4
+  store i32 %frob5, i32 *%ptr5
+  store i32 %frob6, i32 *%ptr6
+  store i32 %frob7, i32 *%ptr7
+  store i32 %frob8, i32 *%ptr8
+  store i32 %frob9, i32 *%ptr9
+
+  %ret = call i64 @foo()
+
+  %ext0 = zext i32 %frob0 to i64
+  %ext1 = zext i32 %frob1 to i64
+  %ext2 = zext i32 %frob2 to i64
+  %ext3 = zext i32 %frob3 to i64
+  %ext4 = zext i32 %frob4 to i64
+  %ext5 = zext i32 %frob5 to i64
+  %ext6 = zext i32 %frob6 to i64
+  %ext7 = zext i32 %frob7 to i64
+  %ext8 = zext i32 %frob8 to i64
+  %ext9 = zext i32 %frob9 to i64
+
+  %cmp0 = icmp ult i64 %ret, %ext0
+  %cmp1 = icmp ult i64 %ret, %ext1
+  %cmp2 = icmp ult i64 %ret, %ext2
+  %cmp3 = icmp ult i64 %ret, %ext3
+  %cmp4 = icmp ult i64 %ret, %ext4
+  %cmp5 = icmp ult i64 %ret, %ext5
+  %cmp6 = icmp ult i64 %ret, %ext6
+  %cmp7 = icmp ult i64 %ret, %ext7
+  %cmp8 = icmp ult i64 %ret, %ext8
+  %cmp9 = icmp ult i64 %ret, %ext9
+
+  %sel0 = select i1 %cmp0, i64 %ret, i64 0
+  %sel1 = select i1 %cmp1, i64 %sel0, i64 1
+  %sel2 = select i1 %cmp2, i64 %sel1, i64 2
+  %sel3 = select i1 %cmp3, i64 %sel2, i64 3
+  %sel4 = select i1 %cmp4, i64 %sel3, i64 4
+  %sel5 = select i1 %cmp5, i64 %sel4, i64 5
+  %sel6 = select i1 %cmp6, i64 %sel5, i64 6
+  %sel7 = select i1 %cmp7, i64 %sel6, i64 7
+  %sel8 = select i1 %cmp8, i64 %sel7, i64 8
+  %sel9 = select i1 %cmp9, i64 %sel8, i64 9
+
+  ret i64 %sel9
+}
diff --git a/test/CodeGen/SystemZ/int-cmp-07.ll b/test/CodeGen/SystemZ/int-cmp-07.ll
index 48ccf5c..3308cb0 100644
--- a/test/CodeGen/SystemZ/int-cmp-07.ll
+++ b/test/CodeGen/SystemZ/int-cmp-07.ll
@@ -4,7 +4,7 @@
 
 ; Check CGR.
 define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgrjl %r2, %r3
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
 
 ; Check CG with no displacement.
 define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cg %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -28,7 +28,7 @@ define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
 
 ; Check the high end of the aligned CG range.
 define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cg %r2, 524280(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: cg %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -58,7 +58,7 @@ define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the high end of the negative aligned CG range.
 define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cg %r2, -8(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -72,7 +72,7 @@ define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the low end of the CG range.
 define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cg %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -87,7 +87,7 @@ define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: cg %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -102,7 +102,7 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check that CG allows an index.
 define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cg %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-08.ll b/test/CodeGen/SystemZ/int-cmp-08.ll
index b091ba6..e68a0fe 100644
--- a/test/CodeGen/SystemZ/int-cmp-08.ll
+++ b/test/CodeGen/SystemZ/int-cmp-08.ll
@@ -4,7 +4,7 @@
 
 ; Check CLGR.
 define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clgr %r2, %r3
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -16,7 +16,7 @@ define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
 
 ; Check CLG with no displacement.
 define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clg %r2, 0(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -29,7 +29,7 @@ define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
 
 ; Check the high end of the aligned CLG range.
 define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clg %r2, 524280(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: clg %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -59,7 +59,7 @@ define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the high end of the negative aligned CLG range.
 define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clg %r2, -8(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -73,7 +73,7 @@ define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the low end of the CLG range.
 define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clg %r2, -524288(%r3)
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -88,7 +88,7 @@ define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: clg %r2, 0(%r3)
 ; CHECK-NEXT: jl
@@ -103,7 +103,7 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check that CLG allows an index.
 define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clg %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-09.ll b/test/CodeGen/SystemZ/int-cmp-09.ll
index 8fb0e7c..0eb8c66 100644
--- a/test/CodeGen/SystemZ/int-cmp-09.ll
+++ b/test/CodeGen/SystemZ/int-cmp-09.ll
@@ -4,7 +4,7 @@
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i32 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cijl %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -13,20 +13,20 @@ define double @f1(double %a, double %b, i32 %i1) {
   ret double %res
 }
 
-; Check comparisons with 1.
+; Check comparisons with 2.
 define double @f2(double %a, double %b, i32 %i1) {
-; CHECK: f2:
-; CHECK: cijl %r2, 1
+; CHECK-LABEL: f2:
+; CHECK: cijl %r2, 2
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
-  %cond = icmp slt i32 %i1, 1
+  %cond = icmp slt i32 %i1, 2
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
 
 ; Check the high end of the CIJ range.
 define double @f3(double %a, double %b, i32 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cijl %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -37,7 +37,7 @@ define double @f3(double %a, double %b, i32 %i1) {
 
 ; Check the next value up, which must use CHI instead.
 define double @f4(double %a, double %b, i32 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: chi %r2, 128
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -49,7 +49,7 @@ define double @f4(double %a, double %b, i32 %i1) {
 
 ; Check the high end of the CHI range.
 define double @f5(double %a, double %b, i32 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: chi %r2, 32767
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -61,7 +61,7 @@ define double @f5(double %a, double %b, i32 %i1) {
 
 ; Check the next value up, which must use CFI.
 define double @f6(double %a, double %b, i32 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cfi %r2, 32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i32 %i1) {
 
 ; Check the high end of the signed 32-bit range.
 define double @f7(double %a, double %b, i32 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cfi %r2, 2147483647
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -85,7 +85,7 @@ define double @f7(double %a, double %b, i32 %i1) {
 
 ; Check the next value up, which should be treated as a negative value.
 define double @f8(double %a, double %b, i32 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cfi %r2, -2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -97,7 +97,7 @@ define double @f8(double %a, double %b, i32 %i1) {
 
 ; Check the high end of the negative CIJ range.
 define double @f9(double %a, double %b, i32 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cijl %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f9(double %a, double %b, i32 %i1) {
 
 ; Check the low end of the CIJ range.
 define double @f10(double %a, double %b, i32 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cijl %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -119,7 +119,7 @@ define double @f10(double %a, double %b, i32 %i1) {
 
 ; Check the next value down, which must use CHI instead.
 define double @f11(double %a, double %b, i32 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: chi %r2, -129
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -131,7 +131,7 @@ define double @f11(double %a, double %b, i32 %i1) {
 
 ; Check the low end of the CHI range.
 define double @f12(double %a, double %b, i32 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: chi %r2, -32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -143,7 +143,7 @@ define double @f12(double %a, double %b, i32 %i1) {
 
 ; Check the next value down, which must use CFI instead.
 define double @f13(double %a, double %b, i32 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cfi %r2, -32769
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -155,7 +155,7 @@ define double @f13(double %a, double %b, i32 %i1) {
 
 ; Check the low end of the signed 32-bit range.
 define double @f14(double %a, double %b, i32 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cfi %r2, -2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -167,7 +167,7 @@ define double @f14(double %a, double %b, i32 %i1) {
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f15(double %a, double %b, i32 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cfi %r2, 2147483647
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -176,3 +176,47 @@ define double @f15(double %a, double %b, i32 %i1) {
   %res = select i1 %cond, double %a, double %b
   ret double %res
 }
+
+; Check that < 1 becomes <= 0.
+define double @f16(double %a, double %b, i32 %i1) {
+; CHECK-LABEL: f16:
+; CHECK: cijle %r2, 0
+; CHECK: ldr %f0, %f2
+; CHECK: br %r14
+  %cond = icmp slt i32 %i1, 1
+  %res = select i1 %cond, double %a, double %b
+  ret double %res
+}
+
+; Check that >= 1 becomes > 0.
+define double @f17(double %a, double %b, i32 %i1) {
+; CHECK-LABEL: f17:
+; CHECK: cijh %r2, 0
+; CHECK: ldr %f0, %f2
+; CHECK: br %r14
+  %cond = icmp sge i32 %i1, 1
+  %res = select i1 %cond, double %a, double %b
+  ret double %res
+}
+
+; Check that > -1 becomes >= 0.
+define double @f18(double %a, double %b, i32 %i1) {
+; CHECK-LABEL: f18:
+; CHECK: cijhe %r2, 0
+; CHECK: ldr %f0, %f2
+; CHECK: br %r14
+  %cond = icmp sgt i32 %i1, -1
+  %res = select i1 %cond, double %a, double %b
+  ret double %res
+}
+
+; Check that <= -1 becomes < 0.
+define double @f19(double %a, double %b, i32 %i1) {
+; CHECK-LABEL: f19:
+; CHECK: cijl %r2, 0
+; CHECK: ldr %f0, %f2
+; CHECK: br %r14
+  %cond = icmp sle i32 %i1, -1
+  %res = select i1 %cond, double %a, double %b
+  ret double %res
+}
diff --git a/test/CodeGen/SystemZ/int-cmp-10.ll b/test/CodeGen/SystemZ/int-cmp-10.ll
index 937b1bc..e30e014 100644
--- a/test/CodeGen/SystemZ/int-cmp-10.ll
+++ b/test/CodeGen/SystemZ/int-cmp-10.ll
@@ -5,7 +5,7 @@
 ; Check a value near the low end of the range.  We use CFI for comparisons
 ; with zero, or things that are equivalent to them.
 define double @f1(double %a, double %b, i32 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clfi %r2, 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i32 %i1) {
 
 ; Check a value near the high end of the range.
 define double @f2(double %a, double %b, i32 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clfi %r2, 4294967280
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-11.ll b/test/CodeGen/SystemZ/int-cmp-11.ll
index a0f598e..c74135a 100644
--- a/test/CodeGen/SystemZ/int-cmp-11.ll
+++ b/test/CodeGen/SystemZ/int-cmp-11.ll
@@ -4,7 +4,7 @@
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgijl %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,8 +15,8 @@ define double @f1(double %a, double %b, i64 %i1) {
 
 ; Check comparisons with 1.
 define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
-; CHECK: cgijl %r2, 1
+; CHECK-LABEL: f2:
+; CHECK: cgijle %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %cond = icmp slt i64 %i1, 1
@@ -26,7 +26,7 @@ define double @f2(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGIJ range.
 define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cgijl %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -37,7 +37,7 @@ define double @f3(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGHI instead.
 define double @f4(double %a, double %b, i64 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cghi %r2, 128
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -49,7 +49,7 @@ define double @f4(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGHI range.
 define double @f5(double %a, double %b, i64 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cghi %r2, 32767
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -61,7 +61,7 @@ define double @f5(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGFI.
 define double @f6(double %a, double %b, i64 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cgfi %r2, 32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -73,7 +73,7 @@ define double @f6(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGFI range.
 define double @f7(double %a, double %b, i64 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cgfi %r2, 2147483647
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -85,7 +85,7 @@ define double @f7(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use register comparison.
 define double @f8(double %a, double %b, i64 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cgrjl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -96,7 +96,7 @@ define double @f8(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the negative CGIJ range.
 define double @f9(double %a, double %b, i64 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cgijl %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define double @f9(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGIJ range.
 define double @f10(double %a, double %b, i64 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cgijl %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -118,7 +118,7 @@ define double @f10(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGHI instead.
 define double @f11(double %a, double %b, i64 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cghi %r2, -129
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -130,7 +130,7 @@ define double @f11(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGHI range.
 define double @f12(double %a, double %b, i64 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cghi %r2, -32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -142,7 +142,7 @@ define double @f12(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGFI instead.
 define double @f13(double %a, double %b, i64 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cgfi %r2, -32769
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -154,7 +154,7 @@ define double @f13(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGFI range.
 define double @f14(double %a, double %b, i64 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cgfi %r2, -2147483648
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -166,7 +166,7 @@ define double @f14(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use register comparison.
 define double @f15(double %a, double %b, i64 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cgrjl
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-12.ll b/test/CodeGen/SystemZ/int-cmp-12.ll
index 74d16cc..f57f6ec 100644
--- a/test/CodeGen/SystemZ/int-cmp-12.ll
+++ b/test/CodeGen/SystemZ/int-cmp-12.ll
@@ -5,7 +5,7 @@
 ; Check a value near the low end of the range.  We use CGFI for comparisons
 ; with zero, or things that are equivalent to them.
 define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clgfi %r2, 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CLGFI range.
 define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clgfi %r2, 4294967295
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -29,7 +29,7 @@ define double @f2(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use a register comparison.
 define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clgr %r2,
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-13.ll b/test/CodeGen/SystemZ/int-cmp-13.ll
index 19bceec..53af0c8 100644
--- a/test/CodeGen/SystemZ/int-cmp-13.ll
+++ b/test/CodeGen/SystemZ/int-cmp-13.ll
@@ -4,7 +4,7 @@
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgije %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define double @f1(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGIJ range.
 define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cgije %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define double @f2(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGHI instead.
 define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cghi %r2, 128
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -38,7 +38,7 @@ define double @f3(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGHI range.
 define double @f4(double %a, double %b, i64 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cghi %r2, 32767
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -50,7 +50,7 @@ define double @f4(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGFI.
 define double @f5(double %a, double %b, i64 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cgfi %r2, 32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -62,7 +62,7 @@ define double @f5(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGFI range.
 define double @f6(double %a, double %b, i64 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cgfi %r2, 2147483647
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -74,7 +74,7 @@ define double @f6(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which should use CLGFI instead.
 define double @f7(double %a, double %b, i64 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: clgfi %r2, 2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CLGFI range.
 define double @f8(double %a, double %b, i64 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clgfi %r2, 4294967295
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -98,7 +98,7 @@ define double @f8(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use a register comparison.
 define double @f9(double %a, double %b, i64 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cgrje %r2,
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -109,7 +109,7 @@ define double @f9(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the negative CGIJ range.
 define double @f10(double %a, double %b, i64 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cgije %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -120,7 +120,7 @@ define double @f10(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGIJ range.
 define double @f11(double %a, double %b, i64 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cgije %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -131,7 +131,7 @@ define double @f11(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGHI instead.
 define double @f12(double %a, double %b, i64 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cghi %r2, -129
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -143,7 +143,7 @@ define double @f12(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGHI range.
 define double @f13(double %a, double %b, i64 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cghi %r2, -32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -155,7 +155,7 @@ define double @f13(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGFI instead.
 define double @f14(double %a, double %b, i64 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cgfi %r2, -32769
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -167,7 +167,7 @@ define double @f14(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGFI range.
 define double @f15(double %a, double %b, i64 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cgfi %r2, -2147483648
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -179,7 +179,7 @@ define double @f15(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use register comparison.
 define double @f16(double %a, double %b, i64 %i1) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cgrje
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-14.ll b/test/CodeGen/SystemZ/int-cmp-14.ll
index 11b56ad..4dbd0ec 100644
--- a/test/CodeGen/SystemZ/int-cmp-14.ll
+++ b/test/CodeGen/SystemZ/int-cmp-14.ll
@@ -4,7 +4,7 @@
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgijlh %r2, 0
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -15,7 +15,7 @@ define double @f1(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGIJ range.
 define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cgijlh %r2, 127
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ define double @f2(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGHI instead.
 define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cghi %r2, 128
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -38,7 +38,7 @@ define double @f3(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGHI range.
 define double @f4(double %a, double %b, i64 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cghi %r2, 32767
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -50,7 +50,7 @@ define double @f4(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use CGFI.
 define double @f5(double %a, double %b, i64 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cgfi %r2, 32768
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -62,7 +62,7 @@ define double @f5(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CGFI range.
 define double @f6(double %a, double %b, i64 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cgfi %r2, 2147483647
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -74,7 +74,7 @@ define double @f6(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which should use CLGFI instead.
 define double @f7(double %a, double %b, i64 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: clgfi %r2, 2147483648
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -86,7 +86,7 @@ define double @f7(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the CLGFI range.
 define double @f8(double %a, double %b, i64 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clgfi %r2, 4294967295
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -98,7 +98,7 @@ define double @f8(double %a, double %b, i64 %i1) {
 
 ; Check the next value up, which must use a register comparison.
 define double @f9(double %a, double %b, i64 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cgrjlh %r2,
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -109,7 +109,7 @@ define double @f9(double %a, double %b, i64 %i1) {
 
 ; Check the high end of the negative CGIJ range.
 define double @f10(double %a, double %b, i64 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cgijlh %r2, -1
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -120,7 +120,7 @@ define double @f10(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGIJ range.
 define double @f11(double %a, double %b, i64 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cgijlh %r2, -128
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
@@ -131,7 +131,7 @@ define double @f11(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGHI instead.
 define double @f12(double %a, double %b, i64 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cghi %r2, -129
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -143,7 +143,7 @@ define double @f12(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGHI range.
 define double @f13(double %a, double %b, i64 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cghi %r2, -32768
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -155,7 +155,7 @@ define double @f13(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use CGFI instead.
 define double @f14(double %a, double %b, i64 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cgfi %r2, -32769
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -167,7 +167,7 @@ define double @f14(double %a, double %b, i64 %i1) {
 
 ; Check the low end of the CGFI range.
 define double @f15(double %a, double %b, i64 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cgfi %r2, -2147483648
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -179,7 +179,7 @@ define double @f15(double %a, double %b, i64 %i1) {
 
 ; Check the next value down, which must use register comparison.
 define double @f16(double %a, double %b, i64 %i1) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cgrjlh
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-15.ll b/test/CodeGen/SystemZ/int-cmp-15.ll
index 1868c57..48a068e 100644
--- a/test/CodeGen/SystemZ/int-cmp-15.ll
+++ b/test/CodeGen/SystemZ/int-cmp-15.ll
@@ -4,7 +4,7 @@
 
 ; Check ordered comparisons near the low end of the unsigned 8-bit range.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -16,7 +16,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 
 ; Check ordered comparisons near the high end of the unsigned 8-bit range.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -28,7 +28,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for negative bytes.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -40,7 +40,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 
 ; ...and an alternative form.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -52,7 +52,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for non-negative bytes.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 
 ; ...and an alternative form.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -76,7 +76,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 
 ; Check equality comparisons at the low end of the signed 8-bit range.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -88,7 +88,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 
 ; Check equality comparisons at the low end of the unsigned 8-bit range.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -100,7 +100,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 
 ; Check equality comparisons at the high end of the signed 8-bit range.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -112,7 +112,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 
 ; Check equality comparisons at the high end of the unsigned 8-bit range.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -124,7 +124,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the CLI range.
 define double @f11(double %a, double %b, i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: cli 4095(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -136,7 +136,7 @@ define double @f11(double %a, double %b, i8 *%src) {
 
 ; Check the next byte up, which should use CLIY instead of CLI.
 define double @f12(double %a, double %b, i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cliy 4096(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -148,7 +148,7 @@ define double @f12(double %a, double %b, i8 *%src) {
 
 ; Check the high end of the CLIY range.
 define double @f13(double %a, double %b, i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cliy 524287(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -161,7 +161,7 @@ define double @f13(double %a, double %b, i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f14(double %a, double %b, i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: agfi %r2, 524288
 ; CHECK: cli 0(%r2), 127
 ; CHECK: br %r14
@@ -174,7 +174,7 @@ define double @f14(double %a, double %b, i8 *%src) {
 
 ; Check the high end of the negative CLIY range.
 define double @f15(double %a, double %b, i8 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cliy -1(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -186,7 +186,7 @@ define double @f15(double %a, double %b, i8 *%src) {
 
 ; Check the low end of the CLIY range.
 define double @f16(double %a, double %b, i8 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cliy -524288(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -199,7 +199,7 @@ define double @f16(double %a, double %b, i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define double @f17(double %a, double %b, i8 *%src) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: agfi %r2, -524289
 ; CHECK: cli 0(%r2), 127
 ; CHECK: br %r14
@@ -212,7 +212,7 @@ define double @f17(double %a, double %b, i8 *%src) {
 
 ; Check that CLI does not allow an index
 define double @f18(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: agr %r2, %r3
 ; CHECK: cli 4095(%r2), 127
 ; CHECK: br %r14
@@ -227,7 +227,7 @@ define double @f18(double %a, double %b, i64 %base, i64 %index) {
 
 ; Check that CLIY does not allow an index
 define double @f19(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: agr %r2, %r3
 ; CHECK: cliy 4096(%r2), 127
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-16.ll b/test/CodeGen/SystemZ/int-cmp-16.ll
index a2c9e87..be206d9 100644
--- a/test/CodeGen/SystemZ/int-cmp-16.ll
+++ b/test/CodeGen/SystemZ/int-cmp-16.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-17.ll b/test/CodeGen/SystemZ/int-cmp-17.ll
index 83e4d2d..3df4ecc 100644
--- a/test/CodeGen/SystemZ/int-cmp-17.ll
+++ b/test/CodeGen/SystemZ/int-cmp-17.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-18.ll b/test/CodeGen/SystemZ/int-cmp-18.ll
index 99cf68a..d03d6ac 100644
--- a/test/CodeGen/SystemZ/int-cmp-18.ll
+++ b/test/CodeGen/SystemZ/int-cmp-18.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-19.ll b/test/CodeGen/SystemZ/int-cmp-19.ll
index 4f84687..b5f0856 100644
--- a/test/CodeGen/SystemZ/int-cmp-19.ll
+++ b/test/CodeGen/SystemZ/int-cmp-19.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 8-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the 8-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cli 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 
 ; Check the high end of the signed 8-bit range, using sign extension.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 255
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 
 ; Check the low end of the signed 8-bit range, using sign extension.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-20.ll b/test/CodeGen/SystemZ/int-cmp-20.ll
index eb21bd1..7ecde77 100644
--- a/test/CodeGen/SystemZ/int-cmp-20.ll
+++ b/test/CodeGen/SystemZ/int-cmp-20.ll
@@ -6,7 +6,7 @@
 ; Check unsigned comparison near the low end of the CLI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the low end of the CLI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -34,7 +34,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the high end of the CLI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the high end of the CLI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison above the high end of the CLI range, using zero
 ; extension.  The condition is always true.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -78,7 +78,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 ; unlikely to occur in practice, we don't bother optimizing the second case,
 ; and simply ignore CLI for this range.  First check the low end of the range.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -90,7 +90,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 
 ; ...and then the high end.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -103,7 +103,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the low end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -117,7 +117,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the low end of the CLI range, using sign
 ; extension.  This cannot use CLI.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -130,7 +130,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the high end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -144,7 +144,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the high end of the CLI range, using sign
 ; extension.  This cannot use CLI.
 define double @f11(double %a, double %b, i8 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -157,7 +157,7 @@ define double @f11(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison above the high end of the CLI range, using zero
 ; extension.  The condition is always true.
 define double @f12(double %a, double %b, i8 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -169,7 +169,7 @@ define double @f12(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for nonnegative values.
 define double @f13(double %a, double %b, i8 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -182,7 +182,7 @@ define double @f13(double %a, double %b, i8 *%ptr) {
 
 ; ...and another form
 define double @f14(double %a, double %b, i8 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -195,7 +195,7 @@ define double @f14(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for negative values.
 define double @f15(double %a, double %b, i8 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -208,7 +208,7 @@ define double @f15(double %a, double %b, i8 *%ptr) {
 
 ; ...and another form
 define double @f16(double %a, double %b, i8 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-21.ll b/test/CodeGen/SystemZ/int-cmp-21.ll
index 9f81ad8..ca9225d 100644
--- a/test/CodeGen/SystemZ/int-cmp-21.ll
+++ b/test/CodeGen/SystemZ/int-cmp-21.ll
@@ -6,7 +6,7 @@
 ; Check unsigned comparison near the low end of the CLI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the low end of the CLI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -34,7 +34,7 @@ define double @f2(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the high end of the CLI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define double @f3(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison near the high end of the CLI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define double @f4(double %a, double %b, i8 *%ptr) {
 ; Check unsigned comparison above the high end of the CLI range, using zero
 ; extension.  The condition is always true.
 define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -78,7 +78,7 @@ define double @f5(double %a, double %b, i8 *%ptr) {
 ; unlikely to occur in practice, we don't bother optimizing the second case,
 ; and simply ignore CLI for this range.  First check the low end of the range.
 define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -90,7 +90,7 @@ define double @f6(double %a, double %b, i8 *%ptr) {
 
 ; ...and then the high end.
 define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -103,7 +103,7 @@ define double @f7(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the low end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cli 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -117,7 +117,7 @@ define double @f8(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the low end of the CLI range, using sign
 ; extension.  This cannot use CLI.
 define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -130,7 +130,7 @@ define double @f9(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the high end of the CLI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cli 0(%r2), 254
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -144,7 +144,7 @@ define double @f10(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison near the high end of the CLI range, using sign
 ; extension.  This cannot use CLI.
 define double @f11(double %a, double %b, i8 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -157,7 +157,7 @@ define double @f11(double %a, double %b, i8 *%ptr) {
 ; Check signed comparison above the high end of the CLI range, using zero
 ; extension.  The condition is always true.
 define double @f12(double %a, double %b, i8 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -169,7 +169,7 @@ define double @f12(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for nonnegative values.
 define double @f13(double %a, double %b, i8 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -182,7 +182,7 @@ define double @f13(double %a, double %b, i8 *%ptr) {
 
 ; ...and another form
 define double @f14(double %a, double %b, i8 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: cli 0(%r2), 128
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -195,7 +195,7 @@ define double @f14(double %a, double %b, i8 *%ptr) {
 
 ; Check tests for negative values.
 define double @f15(double %a, double %b, i8 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -208,7 +208,7 @@ define double @f15(double %a, double %b, i8 *%ptr) {
 
 ; ...and another form
 define double @f16(double %a, double %b, i8 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: cli 0(%r2), 127
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-cmp-22.ll b/test/CodeGen/SystemZ/int-cmp-22.ll
index 7cecacb..43daec9 100644
--- a/test/CodeGen/SystemZ/int-cmp-22.ll
+++ b/test/CodeGen/SystemZ/int-cmp-22.ll
@@ -4,7 +4,7 @@
 
 ; Check comparisons with 0.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: chhsi 0(%r2), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -17,9 +17,9 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with 1.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
-; CHECK: chhsi 0(%r2), 1
-; CHECK-NEXT: jl
+; CHECK-LABEL: f2:
+; CHECK: chhsi 0(%r2), 0
+; CHECK-NEXT: jle
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check a value near the high end of the signed 16-bit range.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: chhsi 0(%r2), 32766
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with -1.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: chhsi 0(%r2), -1
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 
 ; Check a value near the low end of the 16-bit signed range.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: chhsi 0(%r2), -32766
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the CHHSI range.
 define double @f6(double %a, double %b, i16 %i1, i16 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: chhsi 4094(%r3), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i16 %i1, i16 *%base) {
 
 ; Check the next halfword up, which needs separate address logic,
 define double @f7(double %a, double %b, i16 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: aghi %r2, 4096
 ; CHECK: chhsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -98,7 +98,7 @@ define double @f7(double %a, double %b, i16 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f8(double %a, double %b, i16 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, -2
 ; CHECK: chhsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -113,7 +113,7 @@ define double @f8(double %a, double %b, i16 *%base) {
 
 ; Check that CHHSI does not allow indices.
 define double @f9(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: chhsi 0({{%r[23]}}), 0
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-23.ll b/test/CodeGen/SystemZ/int-cmp-23.ll
index 2ca89c5..99fe74b 100644
--- a/test/CodeGen/SystemZ/int-cmp-23.ll
+++ b/test/CodeGen/SystemZ/int-cmp-23.ll
@@ -4,7 +4,7 @@
 
 ; Check a value near the low end of the unsigned 16-bit range.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check a value near the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the CLHHSI range.
 define double @f3(double %a, double %b, i16 %i1, i16 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhhsi 4094(%r3), 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i16 %i1, i16 *%base) {
 
 ; Check the next halfword up, which needs separate address logic,
 define double @f4(double %a, double %b, i16 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: aghi %r2, 4096
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
@@ -59,7 +59,7 @@ define double @f4(double %a, double %b, i16 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f5(double %a, double %b, i16 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: aghi %r2, -2
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
@@ -74,7 +74,7 @@ define double @f5(double %a, double %b, i16 *%base) {
 
 ; Check that CLHHSI does not allow indices.
 define double @f6(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: clhhsi 0({{%r[23]}}), 1
 ; CHECK-NEXT: jh
diff --git a/test/CodeGen/SystemZ/int-cmp-24.ll b/test/CodeGen/SystemZ/int-cmp-24.ll
index 01cc7b3..1a8e587 100644
--- a/test/CodeGen/SystemZ/int-cmp-24.ll
+++ b/test/CodeGen/SystemZ/int-cmp-24.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the unsigned 16-bit range.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-25.ll b/test/CodeGen/SystemZ/int-cmp-25.ll
index 8ea8d6c..50803df 100644
--- a/test/CodeGen/SystemZ/int-cmp-25.ll
+++ b/test/CodeGen/SystemZ/int-cmp-25.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the unsigned 16-bit range.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -17,7 +17,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: jlh
 ; CHECK: ldr %f0, %f2
diff --git a/test/CodeGen/SystemZ/int-cmp-26.ll b/test/CodeGen/SystemZ/int-cmp-26.ll
index 9eb02f4..6077865 100644
--- a/test/CodeGen/SystemZ/int-cmp-26.ll
+++ b/test/CodeGen/SystemZ/int-cmp-26.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-27.ll b/test/CodeGen/SystemZ/int-cmp-27.ll
index 3a16e9e..3102f5c 100644
--- a/test/CodeGen/SystemZ/int-cmp-27.ll
+++ b/test/CodeGen/SystemZ/int-cmp-27.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-28.ll b/test/CodeGen/SystemZ/int-cmp-28.ll
index d40a95d..c3b9059 100644
--- a/test/CodeGen/SystemZ/int-cmp-28.ll
+++ b/test/CodeGen/SystemZ/int-cmp-28.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-29.ll b/test/CodeGen/SystemZ/int-cmp-29.ll
index 221bbcf..1b40d8c 100644
--- a/test/CodeGen/SystemZ/int-cmp-29.ll
+++ b/test/CodeGen/SystemZ/int-cmp-29.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the 16-bit unsigned range, with zero extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the 16-bit unsigned range, with zero extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 
 ; Check the next value up, with zero extension.  The condition is always false.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -44,7 +44,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check comparisons with -1, with zero extension.
 ; This condition is also always false.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with 0, using sign extension.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clhhsi 0(%r2), 0
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 
 ; Check the high end of the signed 16-bit range, using sign extension.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: clhhsi 0(%r2), 32767
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 ; Check the next value up, using sign extension.
 ; The condition is always false.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -95,7 +95,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 
 ; Check comparisons with -1, using sign extension.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 65535
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -108,7 +108,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 
 ; Check the low end of the signed 16-bit range, using sign extension.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: clhhsi 0(%r2), 32768
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -122,7 +122,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check the next value down, using sign extension.
 ; The condition is always false.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-30.ll b/test/CodeGen/SystemZ/int-cmp-30.ll
index 507191b..6c9498c 100644
--- a/test/CodeGen/SystemZ/int-cmp-30.ll
+++ b/test/CodeGen/SystemZ/int-cmp-30.ll
@@ -6,7 +6,7 @@
 ; Check unsigned comparison near the low end of the CLHHSI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the low end of the CLHHSI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -34,7 +34,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the high end of the CLHHSI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the high end of the CLHHSI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison above the high end of the CLHHSI range, using zero
 ; extension.  The condition is always true.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -79,7 +79,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 ; and simply ignore CLHHSI for this range.  First check the low end of the
 ; range.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -91,7 +91,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 
 ; ...and then the high end.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -104,7 +104,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -118,7 +118,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: chhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -132,7 +132,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -146,7 +146,7 @@ define double @f10(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f11(double %a, double %b, i16 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: chhsi 0(%r2), -2
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -160,7 +160,7 @@ define double @f11(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison above the high end of the CLHHSI range, using zero
 ; extension.  The condition is always true.
 define double @f12(double %a, double %b, i16 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -173,7 +173,7 @@ define double @f12(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CHHSI range, using sign
 ; extension.
 define double @f13(double %a, double %b, i16 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: chhsi 0(%r2), 32766
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -187,7 +187,7 @@ define double @f13(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison above the high end of the CHHSI range, using sign
 ; extension.  This condition is always true.
 define double @f14(double %a, double %b, i16 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -200,7 +200,7 @@ define double @f14(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CHHSI range, using sign
 ; extension.
 define double @f15(double %a, double %b, i16 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: chhsi 0(%r2), -32767
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -214,7 +214,7 @@ define double @f15(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison below the low end of the CHHSI range, using sign
 ; extension.  This condition is always true.
 define double @f16(double %a, double %b, i16 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-31.ll b/test/CodeGen/SystemZ/int-cmp-31.ll
index a70ce2b..21539f2 100644
--- a/test/CodeGen/SystemZ/int-cmp-31.ll
+++ b/test/CodeGen/SystemZ/int-cmp-31.ll
@@ -6,7 +6,7 @@
 ; Check unsigned comparison near the low end of the CLHHSI range, using zero
 ; extension.
 define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -20,7 +20,7 @@ define double @f1(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the low end of the CLHHSI range, using sign
 ; extension.
 define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -34,7 +34,7 @@ define double @f2(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the high end of the CLHHSI range, using zero
 ; extension.
 define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -48,7 +48,7 @@ define double @f3(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison near the high end of the CLHHSI range, using sign
 ; extension.
 define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define double @f4(double %a, double %b, i16 *%ptr) {
 ; Check unsigned comparison above the high end of the CLHHSI range, using zero
 ; extension.  The condition is always true.
 define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -79,7 +79,7 @@ define double @f5(double %a, double %b, i16 *%ptr) {
 ; and simply ignore CLHHSI for this range.  First check the low end of the
 ; range.
 define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -91,7 +91,7 @@ define double @f6(double %a, double %b, i16 *%ptr) {
 
 ; ...and then the high end.
 define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: clhhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -104,7 +104,7 @@ define double @f7(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: clhhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -118,7 +118,7 @@ define double @f8(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: chhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -132,7 +132,7 @@ define double @f9(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CLHHSI range, using zero
 ; extension.  This is equivalent to unsigned comparison.
 define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: clhhsi 0(%r2), 65534
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -146,7 +146,7 @@ define double @f10(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CLHHSI range, using sign
 ; extension.  This should use CHHSI instead.
 define double @f11(double %a, double %b, i16 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: chhsi 0(%r2), -2
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -160,7 +160,7 @@ define double @f11(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison above the high end of the CLHHSI range, using zero
 ; extension.  The condition is always true.
 define double @f12(double %a, double %b, i16 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK-NOT: cli
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -173,7 +173,7 @@ define double @f12(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the high end of the CHHSI range, using sign
 ; extension.
 define double @f13(double %a, double %b, i16 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: chhsi 0(%r2), 32766
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -187,7 +187,7 @@ define double @f13(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison above the high end of the CHHSI range, using sign
 ; extension.  This condition is always true.
 define double @f14(double %a, double %b, i16 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
@@ -200,7 +200,7 @@ define double @f14(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison near the low end of the CHHSI range, using sign
 ; extension.
 define double @f15(double %a, double %b, i16 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: chhsi 0(%r2), -32767
 ; CHECK-NEXT: jh
 ; CHECK: br %r14
@@ -214,7 +214,7 @@ define double @f15(double %a, double %b, i16 *%ptr) {
 ; Check signed comparison below the low end of the CHHSI range, using sign
 ; extension.  This condition is always true.
 define double @f16(double %a, double %b, i16 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK-NOT: chhsi
 ; CHECK: br %r14
   %val = load i16 *%ptr
diff --git a/test/CodeGen/SystemZ/int-cmp-32.ll b/test/CodeGen/SystemZ/int-cmp-32.ll
index f79182b..6596f9f 100644
--- a/test/CodeGen/SystemZ/int-cmp-32.ll
+++ b/test/CodeGen/SystemZ/int-cmp-32.ll
@@ -4,7 +4,7 @@
 
 ; Check ordered comparisons with 0.
 define double @f1(double %a, double %b, i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: chsi 0(%r2), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -17,9 +17,9 @@ define double @f1(double %a, double %b, i32 *%ptr) {
 
 ; Check ordered comparisons with 1.
 define double @f2(double %a, double %b, i32 *%ptr) {
-; CHECK: f2:
-; CHECK: chsi 0(%r2), 1
-; CHECK-NEXT: jl
+; CHECK-LABEL: f2:
+; CHECK: chsi 0(%r2), 0
+; CHECK-NEXT: jle
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i32 *%ptr) {
 
 ; Check ordered comparisons with the high end of the signed 16-bit range.
 define double @f3(double %a, double %b, i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: chsi 0(%r2), 32767
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value up, which can't use CHSI.
 define double @f4(double %a, double %b, i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -54,7 +54,7 @@ define double @f4(double %a, double %b, i32 *%ptr) {
 
 ; Check ordered comparisons with -1.
 define double @f5(double %a, double %b, i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: chsi 0(%r2), -1
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -67,7 +67,7 @@ define double @f5(double %a, double %b, i32 *%ptr) {
 
 ; Check ordered comparisons with the low end of the 16-bit signed range.
 define double @f6(double %a, double %b, i32 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: chsi 0(%r2), -32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -80,7 +80,7 @@ define double @f6(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value down, which can't use CHSI.
 define double @f7(double %a, double %b, i32 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -91,7 +91,7 @@ define double @f7(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with 0.
 define double @f8(double %a, double %b, i32 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: chsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -104,7 +104,7 @@ define double @f8(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with 1.
 define double @f9(double %a, double %b, i32 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: chsi 0(%r2), 1
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -117,7 +117,7 @@ define double @f9(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with the high end of the signed 16-bit range.
 define double @f10(double %a, double %b, i32 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: chsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -130,7 +130,7 @@ define double @f10(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value up, which can't use CHSI.
 define double @f11(double %a, double %b, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -141,7 +141,7 @@ define double @f11(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with -1.
 define double @f12(double %a, double %b, i32 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: chsi 0(%r2), -1
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -154,7 +154,7 @@ define double @f12(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with the low end of the 16-bit signed range.
 define double @f13(double %a, double %b, i32 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: chsi 0(%r2), -32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -167,7 +167,7 @@ define double @f13(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f14(double %a, double %b, i32 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: chsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -178,7 +178,7 @@ define double @f14(double %a, double %b, i32 *%ptr) {
 
 ; Check the high end of the CHSI range.
 define double @f15(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: chsi 4092(%r3), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -192,7 +192,7 @@ define double @f15(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the next word up, which needs separate address logic,
 define double @f16(double %a, double %b, i32 *%base) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: aghi %r2, 4096
 ; CHECK: chsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -207,7 +207,7 @@ define double @f16(double %a, double %b, i32 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f17(double %a, double %b, i32 *%base) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: aghi %r2, -4
 ; CHECK: chsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -222,7 +222,7 @@ define double @f17(double %a, double %b, i32 *%base) {
 
 ; Check that CHSI does not allow indices.
 define double @f18(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: chsi 0({{%r[23]}}), 0
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-33.ll b/test/CodeGen/SystemZ/int-cmp-33.ll
index 2c1a26e..e5a653b 100644
--- a/test/CodeGen/SystemZ/int-cmp-33.ll
+++ b/test/CodeGen/SystemZ/int-cmp-33.ll
@@ -5,7 +5,7 @@
 ; Check ordered comparisons with a constant near the low end of the unsigned
 ; 16-bit range.
 define double @f1(double %a, double %b, i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clfhsi 0(%r2), 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i32 *%ptr) {
 
 ; Check ordered comparisons with the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clfhsi 0(%r2), 65535
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value up, which can't use CLFHSI.
 define double @f3(double %a, double %b, i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clfhsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i32 *%ptr) {
 ; Check equality comparisons with 32768, the lowest value for which
 ; we prefer CLFHSI to CHSI.
 define double @f4(double %a, double %b, i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clfhsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i32 *%ptr) {
 
 ; Check equality comparisons with the high end of the unsigned 16-bit range.
 define double @f5(double %a, double %b, i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clfhsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i32 *%ptr) {
 
 ; Check the next value up, which can't use CLFHSI.
 define double @f6(double %a, double %b, i32 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: clfhsi
 ; CHECK: br %r14
   %val = load i32 *%ptr
@@ -80,7 +80,7 @@ define double @f6(double %a, double %b, i32 *%ptr) {
 
 ; Check the high end of the CLFHSI range.
 define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: clfhsi 4092(%r3), 1
 ; CHECK-NEXT: jh
 ; CHECK: ldr %f0, %f2
@@ -94,7 +94,7 @@ define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
 
 ; Check the next word up, which needs separate address logic,
 define double @f8(double %a, double %b, i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, 4096
 ; CHECK: clfhsi 0(%r2), 1
 ; CHECK-NEXT: jh
@@ -109,7 +109,7 @@ define double @f8(double %a, double %b, i32 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f9(double %a, double %b, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -4
 ; CHECK: clfhsi 0(%r2), 1
 ; CHECK-NEXT: jh
@@ -124,7 +124,7 @@ define double @f9(double %a, double %b, i32 *%base) {
 
 ; Check that CLFHSI does not allow indices.
 define double @f10(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: clfhsi 0({{%r[23]}}), 1
 ; CHECK-NEXT: jh
diff --git a/test/CodeGen/SystemZ/int-cmp-34.ll b/test/CodeGen/SystemZ/int-cmp-34.ll
index ff0914a..8a02197 100644
--- a/test/CodeGen/SystemZ/int-cmp-34.ll
+++ b/test/CodeGen/SystemZ/int-cmp-34.ll
@@ -4,7 +4,7 @@
 
 ; Check ordered comparisons with 0.
 define double @f1(double %a, double %b, i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cghsi 0(%r2), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -17,9 +17,9 @@ define double @f1(double %a, double %b, i64 *%ptr) {
 
 ; Check ordered comparisons with 1.
 define double @f2(double %a, double %b, i64 *%ptr) {
-; CHECK: f2:
-; CHECK: cghsi 0(%r2), 1
-; CHECK-NEXT: jl
+; CHECK-LABEL: f2:
+; CHECK: cghsi 0(%r2), 0
+; CHECK-NEXT: jle
 ; CHECK: ldr %f0, %f2
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -30,7 +30,7 @@ define double @f2(double %a, double %b, i64 *%ptr) {
 
 ; Check ordered comparisons with the high end of the signed 16-bit range.
 define double @f3(double %a, double %b, i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cghsi 0(%r2), 32767
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value up, which can't use CGHSI.
 define double @f4(double %a, double %b, i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -54,7 +54,7 @@ define double @f4(double %a, double %b, i64 *%ptr) {
 
 ; Check ordered comparisons with -1.
 define double @f5(double %a, double %b, i64 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cghsi 0(%r2), -1
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -67,7 +67,7 @@ define double @f5(double %a, double %b, i64 *%ptr) {
 
 ; Check ordered comparisons with the low end of the 16-bit signed range.
 define double @f6(double %a, double %b, i64 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cghsi 0(%r2), -32768
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -80,7 +80,7 @@ define double @f6(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f7(double %a, double %b, i64 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -91,7 +91,7 @@ define double @f7(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with 0.
 define double @f8(double %a, double %b, i64 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cghsi 0(%r2), 0
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -104,7 +104,7 @@ define double @f8(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with 1.
 define double @f9(double %a, double %b, i64 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cghsi 0(%r2), 1
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -117,7 +117,7 @@ define double @f9(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with the high end of the signed 16-bit range.
 define double @f10(double %a, double %b, i64 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: cghsi 0(%r2), 32767
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -130,7 +130,7 @@ define double @f10(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value up, which can't use CGHSI.
 define double @f11(double %a, double %b, i64 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -141,7 +141,7 @@ define double @f11(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with -1.
 define double @f12(double %a, double %b, i64 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: cghsi 0(%r2), -1
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -154,7 +154,7 @@ define double @f12(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with the low end of the 16-bit signed range.
 define double @f13(double %a, double %b, i64 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: cghsi 0(%r2), -32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -167,7 +167,7 @@ define double @f13(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value down, which should be treated as a positive value.
 define double @f14(double %a, double %b, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK-NOT: cghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -178,7 +178,7 @@ define double @f14(double %a, double %b, i64 *%ptr) {
 
 ; Check the high end of the CGHSI range.
 define double @f15(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: cghsi 4088(%r3), 0
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -192,7 +192,7 @@ define double @f15(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the next doubleword up, which needs separate address logic,
 define double @f16(double %a, double %b, i64 *%base) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: aghi %r2, 4096
 ; CHECK: cghsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -207,7 +207,7 @@ define double @f16(double %a, double %b, i64 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f17(double %a, double %b, i64 *%base) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: aghi %r2, -8
 ; CHECK: cghsi 0(%r2), 0
 ; CHECK-NEXT: jl
@@ -222,7 +222,7 @@ define double @f17(double %a, double %b, i64 *%base) {
 
 ; Check that CGHSI does not allow indices.
 define double @f18(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: cghsi 0({{%r[23]}}), 0
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-35.ll b/test/CodeGen/SystemZ/int-cmp-35.ll
index b74d67e..539248a 100644
--- a/test/CodeGen/SystemZ/int-cmp-35.ll
+++ b/test/CodeGen/SystemZ/int-cmp-35.ll
@@ -5,7 +5,7 @@
 ; Check ordered comparisons with a constant near the low end of the unsigned
 ; 16-bit range.
 define double @f1(double %a, double %b, i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clghsi 0(%r2), 2
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -18,7 +18,7 @@ define double @f1(double %a, double %b, i64 *%ptr) {
 
 ; Check ordered comparisons with the high end of the unsigned 16-bit range.
 define double @f2(double %a, double %b, i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clghsi 0(%r2), 65535
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -31,7 +31,7 @@ define double @f2(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value up, which can't use CLGHSI.
 define double @f3(double %a, double %b, i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: clghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -43,7 +43,7 @@ define double @f3(double %a, double %b, i64 *%ptr) {
 ; Check equality comparisons with 32768, the lowest value for which
 ; we prefer CLGHSI to CGHSI.
 define double @f4(double %a, double %b, i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clghsi 0(%r2), 32768
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -56,7 +56,7 @@ define double @f4(double %a, double %b, i64 *%ptr) {
 
 ; Check equality comparisons with the high end of the unsigned 16-bit range.
 define double @f5(double %a, double %b, i64 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: clghsi 0(%r2), 65535
 ; CHECK-NEXT: je
 ; CHECK: ldr %f0, %f2
@@ -69,7 +69,7 @@ define double @f5(double %a, double %b, i64 *%ptr) {
 
 ; Check the next value up, which can't use CLGHSI.
 define double @f6(double %a, double %b, i64 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: clghsi
 ; CHECK: br %r14
   %val = load i64 *%ptr
@@ -80,7 +80,7 @@ define double @f6(double %a, double %b, i64 *%ptr) {
 
 ; Check the high end of the CLGHSI range.
 define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: clghsi 4088(%r3), 2
 ; CHECK-NEXT: jl
 ; CHECK: ldr %f0, %f2
@@ -94,7 +94,7 @@ define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
 
 ; Check the next doubleword up, which needs separate address logic,
 define double @f8(double %a, double %b, i64 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, 4096
 ; CHECK: clghsi 0(%r2), 2
 ; CHECK-NEXT: jl
@@ -109,7 +109,7 @@ define double @f8(double %a, double %b, i64 *%base) {
 
 ; Check negative offsets, which also need separate address logic.
 define double @f9(double %a, double %b, i64 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -8
 ; CHECK: clghsi 0(%r2), 2
 ; CHECK-NEXT: jl
@@ -124,7 +124,7 @@ define double @f9(double %a, double %b, i64 *%base) {
 
 ; Check that CLGHSI does not allow indices.
 define double @f10(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr {{%r2, %r3|%r3, %r2}}
 ; CHECK: clghsi 0({{%r[23]}}), 2
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-36.ll b/test/CodeGen/SystemZ/int-cmp-36.ll
index df0e337..831b05f 100644
--- a/test/CodeGen/SystemZ/int-cmp-36.ll
+++ b/test/CodeGen/SystemZ/int-cmp-36.ll
@@ -8,7 +8,7 @@
 
 ; Check signed comparison.
 define i32 @f1(i32 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: chrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check unsigned comparison, which cannot use CHRL.
 define i32 @f2(i32 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: chrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i32 @f3(i32 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: chrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i32 @f4(i32 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: chrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i32 @f5(i32 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: ch %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-37.ll b/test/CodeGen/SystemZ/int-cmp-37.ll
index 272df71..97d210e 100644
--- a/test/CodeGen/SystemZ/int-cmp-37.ll
+++ b/test/CodeGen/SystemZ/int-cmp-37.ll
@@ -8,7 +8,7 @@
 
 ; Check unsigned comparison.
 define i32 @f1(i32 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check signed comparison.
 define i32 @f2(i32 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: clhrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i32 @f3(i32 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i32 @f4(i32 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clhrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i32 @f5(i32 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: llh [[VAL:%r[0-5]]], 0([[REG]])
 ; CHECK: clr %r2, [[VAL]]
diff --git a/test/CodeGen/SystemZ/int-cmp-38.ll b/test/CodeGen/SystemZ/int-cmp-38.ll
index 54f325e..d5a852c 100644
--- a/test/CodeGen/SystemZ/int-cmp-38.ll
+++ b/test/CodeGen/SystemZ/int-cmp-38.ll
@@ -8,7 +8,7 @@
 
 ; Check signed comparisons.
 define i32 @f1(i32 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: crl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ exit:
 
 ; Check unsigned comparisons.
 define i32 @f2(i32 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ exit:
 
 ; Check equality, which can use CRL or CLRL.
 define i32 @f3(i32 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: c{{l?}}rl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ exit:
 
 ; ...likewise inequality.
 define i32 @f4(i32 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: c{{l?}}rl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i32 @f5(i32 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: c %r2, 0([[REG]])
 ; CHECK-NEXT: jl
@@ -99,7 +99,7 @@ exit:
 
 ; Repeat f2 with an unaligned address.
 define i32 @f6(i32 %src1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: cl %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-39.ll b/test/CodeGen/SystemZ/int-cmp-39.ll
index e99b240..d442058 100644
--- a/test/CodeGen/SystemZ/int-cmp-39.ll
+++ b/test/CodeGen/SystemZ/int-cmp-39.ll
@@ -8,7 +8,7 @@
 
 ; Check signed comparison.
 define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cghrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check unsigned comparison, which cannot use CHRL.
 define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: cghrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cghrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cghrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: cgh %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-40.ll b/test/CodeGen/SystemZ/int-cmp-40.ll
index 2d33c8f..6dab2db 100644
--- a/test/CodeGen/SystemZ/int-cmp-40.ll
+++ b/test/CodeGen/SystemZ/int-cmp-40.ll
@@ -8,7 +8,7 @@
 
 ; Check unsigned comparison.
 define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check signed comparison.
 define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: clghrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clghrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
 ; CHECK: llgh [[VAL:%r[0-5]]], 0([[REG]])
 ; CHECK: clgr %r2, [[VAL]]
diff --git a/test/CodeGen/SystemZ/int-cmp-41.ll b/test/CodeGen/SystemZ/int-cmp-41.ll
index f68638a..099681d 100644
--- a/test/CodeGen/SystemZ/int-cmp-41.ll
+++ b/test/CodeGen/SystemZ/int-cmp-41.ll
@@ -8,7 +8,7 @@
 
 ; Check signed comparison.
 define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgfrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check unsigned comparison, which cannot use CHRL.
 define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: cgfrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cgfrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cgfrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: cgf %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-42.ll b/test/CodeGen/SystemZ/int-cmp-42.ll
index dd3cb4a..26a268d 100644
--- a/test/CodeGen/SystemZ/int-cmp-42.ll
+++ b/test/CodeGen/SystemZ/int-cmp-42.ll
@@ -8,7 +8,7 @@
 
 ; Check unsigned comparison.
 define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clgfrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -27,7 +27,7 @@ exit:
 
 ; Check signed comparison.
 define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: clgfrl
 ; CHECK: br %r14
 entry:
@@ -45,7 +45,7 @@ exit:
 
 ; Check equality.
 define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: clgfrl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -64,7 +64,7 @@ exit:
 
 ; Check inequality.
 define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: clgfrl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -83,7 +83,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: clgf %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-43.ll b/test/CodeGen/SystemZ/int-cmp-43.ll
index 7d4adca..e5e1390 100644
--- a/test/CodeGen/SystemZ/int-cmp-43.ll
+++ b/test/CodeGen/SystemZ/int-cmp-43.ll
@@ -8,7 +8,7 @@
 
 ; Check signed comparisons.
 define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cgrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -26,7 +26,7 @@ exit:
 
 ; Check unsigned comparisons.
 define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: clgrl %r2, g
 ; CHECK-NEXT: jl
 ; CHECK: br %r14
@@ -44,7 +44,7 @@ exit:
 
 ; Check equality, which can use CRL or CLRL.
 define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: c{{l?}}grl %r2, g
 ; CHECK-NEXT: je
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ exit:
 
 ; ...likewise inequality.
 define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: c{{l?}}grl %r2, g
 ; CHECK-NEXT: jlh
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ exit:
 
 ; Repeat f1 with an unaligned address.
 define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: larl [[REG:%r[0-5]]], h
 ; CHECK: cg %r2, 0([[REG]])
 ; CHECK-NEXT: jl
diff --git a/test/CodeGen/SystemZ/int-cmp-44.ll b/test/CodeGen/SystemZ/int-cmp-44.ll
new file mode 100644
index 0000000..b94f482
--- /dev/null
+++ b/test/CodeGen/SystemZ/int-cmp-44.ll
@@ -0,0 +1,799 @@
+; Test that compares are ommitted if CC already has the right value
+; (z10 version).
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+
+declare void @foo()
+
+; Addition provides enough for equality comparisons with zero.  First teest
+; the EQ case.
+define i32 @f1(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f1:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: je .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = add i32 %a, 1000000
+  %cmp = icmp eq i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; ...and again with NE.
+define i32 @f2(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f2:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: jne .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = add i32 %a, 1000000
+  %cmp = icmp ne i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; SLT requires a comparison.
+define i32 @f3(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f3:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: cijl %r2, 0, .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = add i32 %a, 1000000
+  %cmp = icmp slt i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; ...SLE too.
+define i32 @f4(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f4:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: cijle %r2, 0, .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = add i32 %a, 1000000
+  %cmp = icmp sle i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; ...SGT too.
+define i32 @f5(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f5:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: cijh %r2, 0, .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = add i32 %a, 1000000
+  %cmp = icmp sgt i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; ...SGE too.
+define i32 @f6(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f6:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: cijhe %r2, 0, .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = add i32 %a, 1000000
+  %cmp = icmp sge i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; Subtraction also provides enough for equality comparisons with zero.
+define i32 @f7(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f7:
+; CHECK: s %r2, 0(%r4)
+; CHECK-NEXT: jne .L{{.*}}
+; CHECK: br %r14
+entry:
+  %cur = load i32 *%dest
+  %res = sub i32 %a, %cur
+  %cmp = icmp ne i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; ...but not for ordered comparisons.
+define i32 @f8(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f8:
+; CHECK: s %r2, 0(%r4)
+; CHECK-NEXT: cijl %r2, 0, .L{{.*}}
+; CHECK: br %r14
+entry:
+  %cur = load i32 *%dest
+  %res = sub i32 %a, %cur
+  %cmp = icmp slt i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; Logic register-register instructions also provide enough for equality
+; comparisons with zero.
+define i32 @f9(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f9:
+; CHECK: nr %r2, %r3
+; CHECK-NEXT: jl .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = and i32 %a, %b
+  %cmp = icmp ne i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; ...but not for ordered comparisons.
+define i32 @f10(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f10:
+; CHECK: nr %r2, %r3
+; CHECK-NEXT: cijl %r2, 0, .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = and i32 %a, %b
+  %cmp = icmp slt i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; Logic register-immediate instructions also provide enough for equality
+; comparisons with zero if the immediate covers the whole register.
+define i32 @f11(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f11:
+; CHECK: nilf %r2, 100
+; CHECK-NEXT: jl .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = and i32 %a, 100
+  %cmp = icmp ne i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; Partial logic register-immediate instructions do not provide simple
+; zero results.
+define i32 @f12(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f12:
+; CHECK: nill %r2, 65436
+; CHECK-NEXT: cijlh %r2, 0, .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = and i32 %a, -100
+  %cmp = icmp ne i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; SRA provides the same CC result as a comparison with zero.
+define i32 @f13(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f13:
+; CHECK: sra %r2, 0(%r3)
+; CHECK-NEXT: je .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = ashr i32 %a, %b
+  %cmp = icmp eq i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; ...and again with NE.
+define i32 @f14(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f14:
+; CHECK: sra %r2, 0(%r3)
+; CHECK-NEXT: jlh .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = ashr i32 %a, %b
+  %cmp = icmp ne i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; ...and SLT.
+define i32 @f15(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f15:
+; CHECK: sra %r2, 0(%r3)
+; CHECK-NEXT: jl .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = ashr i32 %a, %b
+  %cmp = icmp slt i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; ...and SLE.
+define i32 @f16(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f16:
+; CHECK: sra %r2, 0(%r3)
+; CHECK-NEXT: jle .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = ashr i32 %a, %b
+  %cmp = icmp sle i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; ...and SGT.
+define i32 @f17(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f17:
+; CHECK: sra %r2, 0(%r3)
+; CHECK-NEXT: jh .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = ashr i32 %a, %b
+  %cmp = icmp sgt i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; ...and SGE.
+define i32 @f18(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f18:
+; CHECK: sra %r2, 0(%r3)
+; CHECK-NEXT: jhe .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = ashr i32 %a, %b
+  %cmp = icmp sge i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; RISBG provides the same result as a comparison against zero.
+; Test the EQ case.
+define i64 @f19(i64 %a, i64 %b, i64 *%dest) {
+; CHECK-LABEL: f19:
+; CHECK: risbg %r2, %r3, 0, 190, 0
+; CHECK-NEXT: je .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = and i64 %b, -2
+  %cmp = icmp eq i64 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i64 %b, i64 *%dest
+  br label %exit
+
+exit:
+  ret i64 %res
+}
+
+; ...and the SLT case.
+define i64 @f20(i64 %a, i64 %b, i64 *%dest) {
+; CHECK-LABEL: f20:
+; CHECK: risbg %r2, %r3, 0, 190, 0
+; CHECK-NEXT: jl .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = and i64 %b, -2
+  %cmp = icmp slt i64 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i64 %b, i64 *%dest
+  br label %exit
+
+exit:
+  ret i64 %res
+}
+
+; Test a case where the register we're testing is set by a non-CC-clobbering
+; instruction.
+define i32 @f21(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f21:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: #APP
+; CHECK-NEXT: blah %r2
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: cije %r2, 0, .L{{.*}}
+; CHECK: br %r14
+entry:
+  %add = add i32 %a, 1000000
+  %res = call i32 asm "blah $0", "=r,0" (i32 %add)
+  %cmp = icmp eq i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; ...and again with a CC-clobbering instruction.
+define i32 @f22(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f22:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: #APP
+; CHECK-NEXT: blah %r2
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: cije %r2, 0, .L{{.*}}
+; CHECK: br %r14
+entry:
+  %add = add i32 %a, 1000000
+  %res = call i32 asm "blah $0", "=r,0,~{cc}" (i32 %add)
+  %cmp = icmp eq i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; Check that stores do not interfere.
+define i32 @f23(i32 %a, i32 %b, i32 *%dest1, i32 *%dest2) {
+; CHECK-LABEL: f23:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: st %r2, 0(%r4)
+; CHECK-NEXT: jne .L{{.*}}
+; CHECK: br %r14
+entry:
+  %res = add i32 %a, 1000000
+  store i32 %res, i32 *%dest1
+  %cmp = icmp ne i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %b, i32 *%dest2
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; Check that calls do interfere.
+define void @f24(i32 *%ptr) {
+; CHECK-LABEL: f24:
+; CHECK: afi [[REG:%r[0-9]+]], 1000000
+; CHECK-NEXT: brasl %r14, foo@PLT
+; CHECK-NEXT: cijlh [[REG]], 0, .L{{.*}}
+; CHECK: br %r14
+entry:
+  %val = load i32 *%ptr
+  %xor = xor i32 %val, 1
+  %add = add i32 %xor, 1000000
+  call void @foo()
+  %cmp = icmp ne i32 %add, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %add, i32 *%ptr
+  br label %exit
+
+exit:
+  ret void
+}
+
+; Check that inline asms don't interfere if they don't clobber CC.
+define void @f25(i32 %a, i32 *%ptr) {
+; CHECK-LABEL: f25:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: #APP
+; CHECK-NEXT: blah
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jne .L{{.*}}
+; CHECK: br %r14
+entry:
+  %add = add i32 %a, 1000000
+  call void asm sideeffect "blah", "r"(i32 %add)
+  %cmp = icmp ne i32 %add, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %add, i32 *%ptr
+  br label %exit
+
+exit:
+  ret void
+}
+
+; ...but do interfere if they do clobber CC.
+define void @f26(i32 %a, i32 *%ptr) {
+; CHECK-LABEL: f26:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: #APP
+; CHECK-NEXT: blah
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: cijlh %r2, 0, .L{{.*}}
+; CHECK: br %r14
+entry:
+  %add = add i32 %a, 1000000
+  call void asm sideeffect "blah", "r,~{cc}"(i32 %add)
+  %cmp = icmp ne i32 %add, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %add, i32 *%ptr
+  br label %exit
+
+exit:
+  ret void
+}
+
+; Test a case where CC is set based on a different register from the
+; compare input.
+define i32 @f27(i32 %a, i32 %b, i32 *%dest1, i32 *%dest2) {
+; CHECK-LABEL: f27:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: sr %r3, %r2
+; CHECK-NEXT: st %r3, 0(%r4)
+; CHECK-NEXT: cije %r2, 0, .L{{.*}}
+; CHECK: br %r14
+entry:
+  %add = add i32 %a, 1000000
+  %sub = sub i32 %b, %add
+  store i32 %sub, i32 *%dest1
+  %cmp = icmp eq i32 %add, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %sub, i32 *%dest2
+  br label %exit
+
+exit:
+  ret i32 %add
+}
+
+; Make sure that we don't confuse a base register for a destination.
+define void @f28(i64 %a, i64 *%dest) {
+; CHECK-LABEL: f28:
+; CHECK: xi 0(%r2), 15
+; CHECK: cgije %r2, 0, .L{{.*}}
+; CHECK: br %r14
+entry:
+  %ptr = inttoptr i64 %a to i8 *
+  %val = load i8 *%ptr
+  %xor = xor i8 %val, 15
+  store i8 %xor, i8 *%ptr
+  %cmp = icmp eq i64 %a, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i64 %a, i64 *%dest
+  br label %exit
+
+exit:
+  ret void
+}
+
+; Test that L gets converted to LT where useful.
+define i32 @f29(i64 %base, i64 %index, i32 *%dest) {
+; CHECK-LABEL: f29:
+; CHECK: lt %r2, 0({{%r2,%r3|%r3,%r2}})
+; CHECK-NEXT: jle .L{{.*}}
+; CHECK: br %r14
+entry:
+  %add = add i64 %base, %index
+  %ptr = inttoptr i64 %add to i32 *
+  %res = load i32 *%ptr
+  %cmp = icmp sle i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %res, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; Test that LY gets converted to LT where useful.
+define i32 @f30(i64 %base, i64 %index, i32 *%dest) {
+; CHECK-LABEL: f30:
+; CHECK: lt %r2, 100000({{%r2,%r3|%r3,%r2}})
+; CHECK-NEXT: jle .L{{.*}}
+; CHECK: br %r14
+entry:
+  %add1 = add i64 %base, %index
+  %add2 = add i64 %add1, 100000
+  %ptr = inttoptr i64 %add2 to i32 *
+  %res = load i32 *%ptr
+  %cmp = icmp sle i32 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %res, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %res
+}
+
+; Test that LG gets converted to LTG where useful.
+define i64 @f31(i64 %base, i64 %index, i64 *%dest) {
+; CHECK-LABEL: f31:
+; CHECK: ltg %r2, 0({{%r2,%r3|%r3,%r2}})
+; CHECK-NEXT: jhe .L{{.*}}
+; CHECK: br %r14
+entry:
+  %add = add i64 %base, %index
+  %ptr = inttoptr i64 %add to i64 *
+  %res = load i64 *%ptr
+  %cmp = icmp sge i64 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i64 %res, i64 *%dest
+  br label %exit
+
+exit:
+  ret i64 %res
+}
+
+; Test that LGF gets converted to LTGF where useful.
+define i64 @f32(i64 %base, i64 %index, i64 *%dest) {
+; CHECK-LABEL: f32:
+; CHECK: ltgf %r2, 0({{%r2,%r3|%r3,%r2}})
+; CHECK-NEXT: jh .L{{.*}}
+; CHECK: br %r14
+entry:
+  %add = add i64 %base, %index
+  %ptr = inttoptr i64 %add to i32 *
+  %val = load i32 *%ptr
+  %res = sext i32 %val to i64
+  %cmp = icmp sgt i64 %res, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i64 %res, i64 *%dest
+  br label %exit
+
+exit:
+  ret i64 %res
+}
+
+; Test that LR gets converted to LTR where useful.
+define i32 @f33(i32 %dummy, i32 %val, i32 *%dest) {
+; CHECK-LABEL: f33:
+; CHECK: ltr %r2, %r3
+; CHECK-NEXT: #APP
+; CHECK-NEXT: blah %r2
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jl .L{{.*}}
+; CHECK: br %r14
+entry:
+  call void asm sideeffect "blah $0", "{r2}"(i32 %val)
+  %cmp = icmp slt i32 %val, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %val, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %val
+}
+
+; Test that LGR gets converted to LTGR where useful.
+define i64 @f34(i64 %dummy, i64 %val, i64 *%dest) {
+; CHECK-LABEL: f34:
+; CHECK: ltgr %r2, %r3
+; CHECK-NEXT: #APP
+; CHECK-NEXT: blah %r2
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jh .L{{.*}}
+; CHECK: br %r14
+entry:
+  call void asm sideeffect "blah $0", "{r2}"(i64 %val)
+  %cmp = icmp sgt i64 %val, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i64 %val, i64 *%dest
+  br label %exit
+
+exit:
+  ret i64 %val
+}
+
+; Test that LGFR gets converted to LTGFR where useful.
+define i64 @f35(i64 %dummy, i32 %val, i64 *%dest) {
+; CHECK-LABEL: f35:
+; CHECK: ltgfr %r2, %r3
+; CHECK-NEXT: #APP
+; CHECK-NEXT: blah %r2
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jh .L{{.*}}
+; CHECK: br %r14
+entry:
+  %ext = sext i32 %val to i64
+  call void asm sideeffect "blah $0", "{r2}"(i64 %ext)
+  %cmp = icmp sgt i64 %ext, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i64 %ext, i64 *%dest
+  br label %exit
+
+exit:
+  ret i64 %ext
+}
+
+; Test a case where it is the source rather than destination of LR that
+; we need.
+define i32 @f36(i32 %val, i32 %dummy, i32 *%dest) {
+; CHECK-LABEL: f36:
+; CHECK: ltr %r3, %r2
+; CHECK-NEXT: #APP
+; CHECK-NEXT: blah %r3
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jl .L{{.*}}
+; CHECK: br %r14
+entry:
+  call void asm sideeffect "blah $0", "{r3}"(i32 %val)
+  %cmp = icmp slt i32 %val, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %val, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %val
+}
+
+; Test a case where it is the source rather than destination of LGR that
+; we need.
+define i64 @f37(i64 %val, i64 %dummy, i64 *%dest) {
+; CHECK-LABEL: f37:
+; CHECK: ltgr %r3, %r2
+; CHECK-NEXT: #APP
+; CHECK-NEXT: blah %r3
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jl .L{{.*}}
+; CHECK: br %r14
+entry:
+  call void asm sideeffect "blah $0", "{r3}"(i64 %val)
+  %cmp = icmp slt i64 %val, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i64 %val, i64 *%dest
+  br label %exit
+
+exit:
+  ret i64 %val
+}
+
+; Test a case where it is the source rather than destination of LGFR that
+; we need.
+define i32 @f38(i32 %val, i64 %dummy, i32 *%dest) {
+; CHECK-LABEL: f38:
+; CHECK: ltgfr %r3, %r2
+; CHECK-NEXT: #APP
+; CHECK-NEXT: blah %r3
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jl .L{{.*}}
+; CHECK: br %r14
+entry:
+  %ext = sext i32 %val to i64
+  call void asm sideeffect "blah $0", "{r3}"(i64 %ext)
+  %cmp = icmp slt i32 %val, 0
+  br i1 %cmp, label %exit, label %store
+
+store:
+  store i32 %val, i32 *%dest
+  br label %exit
+
+exit:
+  ret i32 %val
+}
diff --git a/test/CodeGen/SystemZ/int-cmp-45.ll b/test/CodeGen/SystemZ/int-cmp-45.ll
new file mode 100644
index 0000000..753a528
--- /dev/null
+++ b/test/CodeGen/SystemZ/int-cmp-45.ll
@@ -0,0 +1,115 @@
+; Test that compares are ommitted if CC already has the right value
+; (z196 version).
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Addition provides enough for equality comparisons with zero.  First teest
+; the EQ case with LOC.
+define i32 @f1(i32 %a, i32 %b, i32 *%cptr) {
+; CHECK-LABEL: f1:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: loce %r3, 0(%r4)
+; CHECK: br %r14
+  %add = add i32 %a, 1000000
+  %cmp = icmp eq i32 %add, 0
+  %c = load i32 *%cptr
+  %arg = select i1 %cmp, i32 %c, i32 %b
+  call void asm sideeffect "blah $0", "{r3}"(i32 %arg)
+  ret i32 %add
+}
+
+; ...and again with STOC.
+define i32 @f2(i32 %a, i32 %b, i32 *%cptr) {
+; CHECK-LABEL: f2:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: stoce %r3, 0(%r4)
+; CHECK: br %r14
+  %add = add i32 %a, 1000000
+  %cmp = icmp eq i32 %add, 0
+  %c = load i32 *%cptr
+  %newval = select i1 %cmp, i32 %b, i32 %c
+  store i32 %newval, i32 *%cptr
+  ret i32 %add
+}
+
+; Reverse the select order and test with LOCR.
+define i32 @f3(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f3:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: locrne %r3, %r4
+; CHECK: br %r14
+  %add = add i32 %a, 1000000
+  %cmp = icmp eq i32 %add, 0
+  %arg = select i1 %cmp, i32 %b, i32 %c
+  call void asm sideeffect "blah $0", "{r3}"(i32 %arg)
+  ret i32 %add
+}
+
+; ...and again with LOC.
+define i32 @f4(i32 %a, i32 %b, i32 *%cptr) {
+; CHECK-LABEL: f4:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: locne %r3, 0(%r4)
+; CHECK: br %r14
+  %add = add i32 %a, 1000000
+  %cmp = icmp eq i32 %add, 0
+  %c = load i32 *%cptr
+  %arg = select i1 %cmp, i32 %b, i32 %c
+  call void asm sideeffect "blah $0", "{r3}"(i32 %arg)
+  ret i32 %add
+}
+
+; ...and again with STOC.
+define i32 @f5(i32 %a, i32 %b, i32 *%cptr) {
+; CHECK-LABEL: f5:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: stocne %r3, 0(%r4)
+; CHECK: br %r14
+  %add = add i32 %a, 1000000
+  %cmp = icmp eq i32 %add, 0
+  %c = load i32 *%cptr
+  %newval = select i1 %cmp, i32 %c, i32 %b
+  store i32 %newval, i32 *%cptr
+  ret i32 %add
+}
+
+; Change the EQ in f3 to NE.
+define i32 @f6(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f6:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: locre %r3, %r4
+; CHECK: br %r14
+  %add = add i32 %a, 1000000
+  %cmp = icmp ne i32 %add, 0
+  %arg = select i1 %cmp, i32 %b, i32 %c
+  call void asm sideeffect "blah $0", "{r3}"(i32 %arg)
+  ret i32 %add
+}
+
+; ...and again with LOC.
+define i32 @f7(i32 %a, i32 %b, i32 *%cptr) {
+; CHECK-LABEL: f7:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: loce %r3, 0(%r4)
+; CHECK: br %r14
+  %add = add i32 %a, 1000000
+  %cmp = icmp ne i32 %add, 0
+  %c = load i32 *%cptr
+  %arg = select i1 %cmp, i32 %b, i32 %c
+  call void asm sideeffect "blah $0", "{r3}"(i32 %arg)
+  ret i32 %add
+}
+
+; ...and again with STOC.
+define i32 @f8(i32 %a, i32 %b, i32 *%cptr) {
+; CHECK-LABEL: f8:
+; CHECK: afi %r2, 1000000
+; CHECK-NEXT: stoce %r3, 0(%r4)
+; CHECK: br %r14
+  %add = add i32 %a, 1000000
+  %cmp = icmp ne i32 %add, 0
+  %c = load i32 *%cptr
+  %newval = select i1 %cmp, i32 %c, i32 %b
+  store i32 %newval, i32 *%cptr
+  ret i32 %add
+}
diff --git a/test/CodeGen/SystemZ/int-const-01.ll b/test/CodeGen/SystemZ/int-const-01.ll
index a580154..e94c058 100644
--- a/test/CodeGen/SystemZ/int-const-01.ll
+++ b/test/CodeGen/SystemZ/int-const-01.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare void @foo(i32, i32, i32, i32)
+
 ; Check 0.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhi %r2, 0
 ; CHECK: br %r14
   ret i32 0
@@ -12,7 +14,7 @@ define i32 @f1() {
 
 ; Check the high end of the LHI range.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhi %r2, 32767
 ; CHECK: br %r14
   ret i32 32767
@@ -20,7 +22,7 @@ define i32 @f2() {
 
 ; Check the next value up, which must use LLILL instead.
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llill %r2, 32768
 ; CHECK: br %r14
   ret i32 32768
@@ -28,7 +30,7 @@ define i32 @f3() {
 
 ; Check the high end of the LLILL range.
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llill %r2, 65535
 ; CHECK: br %r14
   ret i32 65535
@@ -36,7 +38,7 @@ define i32 @f4() {
 
 ; Check the first useful LLILH value, which is the next one up.
 define i32 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llilh %r2, 1
 ; CHECK: br %r14
   ret i32 65536
@@ -44,7 +46,7 @@ define i32 @f5() {
 
 ; Check the first useful IILF value, which is the next one up again.
 define i32 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: iilf %r2, 65537
 ; CHECK: br %r14
   ret i32 65537
@@ -52,7 +54,7 @@ define i32 @f6() {
 
 ; Check the high end of the LLILH range.
 define i32 @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llilh %r2, 65535
 ; CHECK: br %r14
   ret i32 -65536
@@ -60,7 +62,7 @@ define i32 @f7() {
 
 ; Check the next value up, which must use IILF.
 define i32 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: iilf %r2, 4294901761
 ; CHECK: br %r14
   ret i32 -65535
@@ -68,7 +70,7 @@ define i32 @f8() {
 
 ; Check the highest useful IILF value, 0xffff7fff
 define i32 @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: iilf %r2, 4294934527
 ; CHECK: br %r14
   ret i32 -32769
@@ -76,7 +78,7 @@ define i32 @f9() {
 
 ; Check the next value up, which should use LHI.
 define i32 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: lhi %r2, -32768
 ; CHECK: br %r14
   ret i32 -32768
@@ -84,8 +86,28 @@ define i32 @f10() {
 
 ; Check -1.
 define i32 @f11() {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: lhi %r2, -1
 ; CHECK: br %r14
   ret i32 -1
 }
+
+; Check that constant loads are rematerialized.
+define i32 @f12() {
+; CHECK-LABEL: f12:
+; CHECK-DAG: lhi %r2, 42
+; CHECK-DAG: llill %r3, 32768
+; CHECK-DAG: llilh %r4, 1
+; CHECK-DAG: iilf %r5, 65537
+; CHECK: brasl %r14, foo@PLT
+; CHECK-DAG: lhi %r2, 42
+; CHECK-DAG: llill %r3, 32768
+; CHECK-DAG: llilh %r4, 1
+; CHECK-DAG: iilf %r5, 65537
+; CHECK: brasl %r14, foo@PLT
+; CHECK: lhi %r2, 42
+; CHECK: br %r14
+  call void @foo(i32 42, i32 32768, i32 65536, i32 65537)
+  call void @foo(i32 42, i32 32768, i32 65536, i32 65537)
+  ret i32 42
+}
diff --git a/test/CodeGen/SystemZ/int-const-02.ll b/test/CodeGen/SystemZ/int-const-02.ll
index b345e3f..e71abc6 100644
--- a/test/CodeGen/SystemZ/int-const-02.ll
+++ b/test/CodeGen/SystemZ/int-const-02.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare void @foo(i64, i64, i64, i64)
+
 ; Check 0.
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lghi %r2, 0
 ; CHECK-NEXT: br %r14
   ret i64 0
@@ -12,7 +14,7 @@ define i64 @f1() {
 
 ; Check the high end of the LGHI range.
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lghi %r2, 32767
 ; CHECK-NEXT: br %r14
   ret i64 32767
@@ -20,7 +22,7 @@ define i64 @f2() {
 
 ; Check the next value up, which must use LLILL instead.
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llill %r2, 32768
 ; CHECK-NEXT: br %r14
   ret i64 32768
@@ -28,7 +30,7 @@ define i64 @f3() {
 
 ; Check the high end of the LLILL range.
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llill %r2, 65535
 ; CHECK-NEXT: br %r14
   ret i64 65535
@@ -36,7 +38,7 @@ define i64 @f4() {
 
 ; Check the first useful LLILH value, which is the next one up.
 define i64 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llilh %r2, 1
 ; CHECK-NEXT: br %r14
   ret i64 65536
@@ -44,7 +46,7 @@ define i64 @f5() {
 
 ; Check the first useful LGFI value, which is the next one up again.
 define i64 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgfi %r2, 65537
 ; CHECK-NEXT: br %r14
   ret i64 65537
@@ -52,7 +54,7 @@ define i64 @f6() {
 
 ; Check the high end of the LGFI range.
 define i64 @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgfi %r2, 2147483647
 ; CHECK-NEXT: br %r14
   ret i64 2147483647
@@ -60,7 +62,7 @@ define i64 @f7() {
 
 ; Check the next value up, which should use LLILH instead.
 define i64 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llilh %r2, 32768
 ; CHECK-NEXT: br %r14
   ret i64 2147483648
@@ -68,7 +70,7 @@ define i64 @f8() {
 
 ; Check the next value up again, which should use LLILF.
 define i64 @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: llilf %r2, 2147483649
 ; CHECK-NEXT: br %r14
   ret i64 2147483649
@@ -76,7 +78,7 @@ define i64 @f9() {
 
 ; Check the high end of the LLILH range.
 define i64 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llilh %r2, 65535
 ; CHECK-NEXT: br %r14
   ret i64 4294901760
@@ -84,7 +86,7 @@ define i64 @f10() {
 
 ; Check the next value up, which must use LLILF.
 define i64 @f11() {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: llilf %r2, 4294901761
 ; CHECK-NEXT: br %r14
   ret i64 4294901761
@@ -92,7 +94,7 @@ define i64 @f11() {
 
 ; Check the high end of the LLILF range.
 define i64 @f12() {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: llilf %r2, 4294967295
 ; CHECK-NEXT: br %r14
   ret i64 4294967295
@@ -100,7 +102,7 @@ define i64 @f12() {
 
 ; Check the lowest useful LLIHL value, which is the next one up.
 define i64 @f13() {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: br %r14
   ret i64 4294967296
@@ -108,7 +110,7 @@ define i64 @f13() {
 
 ; Check the next value up, which must use a combination of two instructions.
 define i64 @f14() {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oill %r2, 1
 ; CHECK-NEXT: br %r14
@@ -117,7 +119,7 @@ define i64 @f14() {
 
 ; Check the high end of the OILL range.
 define i64 @f15() {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oill %r2, 65535
 ; CHECK-NEXT: br %r14
@@ -126,7 +128,7 @@ define i64 @f15() {
 
 ; Check the next value up, which should use OILH instead.
 define i64 @f16() {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oilh %r2, 1
 ; CHECK-NEXT: br %r14
@@ -135,7 +137,7 @@ define i64 @f16() {
 
 ; Check the next value up again, which should use OILF.
 define i64 @f17() {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oilf %r2, 65537
 ; CHECK-NEXT: br %r14
@@ -144,7 +146,7 @@ define i64 @f17() {
 
 ; Check the high end of the OILH range.
 define i64 @f18() {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oilh %r2, 65535
 ; CHECK-NEXT: br %r14
@@ -153,7 +155,7 @@ define i64 @f18() {
 
 ; Check the high end of the OILF range.
 define i64 @f19() {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: llihl %r2, 1
 ; CHECK-NEXT: oilf %r2, 4294967295
 ; CHECK-NEXT: br %r14
@@ -162,7 +164,7 @@ define i64 @f19() {
 
 ; Check the high end of the LLIHL range.
 define i64 @f20() {
-; CHECK: f20:
+; CHECK-LABEL: f20:
 ; CHECK: llihl %r2, 65535
 ; CHECK-NEXT: br %r14
   ret i64 281470681743360
@@ -170,7 +172,7 @@ define i64 @f20() {
 
 ; Check the lowest useful LLIHH value, which is 1<<32 greater than the above.
 define i64 @f21() {
-; CHECK: f21:
+; CHECK-LABEL: f21:
 ; CHECK: llihh %r2, 1
 ; CHECK-NEXT: br %r14
   ret i64 281474976710656
@@ -178,7 +180,7 @@ define i64 @f21() {
 
 ; Check the lowest useful LLIHF value, which is 1<<32 greater again.
 define i64 @f22() {
-; CHECK: f22:
+; CHECK-LABEL: f22:
 ; CHECK: llihf %r2, 65537
 ; CHECK-NEXT: br %r14
   ret i64 281479271677952
@@ -186,7 +188,7 @@ define i64 @f22() {
 
 ; Check the highest end of the LLIHH range.
 define i64 @f23() {
-; CHECK: f23:
+; CHECK-LABEL: f23:
 ; CHECK: llihh %r2, 65535
 ; CHECK-NEXT: br %r14
   ret i64 -281474976710656
@@ -194,7 +196,7 @@ define i64 @f23() {
 
 ; Check the next value up, which must use OILL too.
 define i64 @f24() {
-; CHECK: f24:
+; CHECK-LABEL: f24:
 ; CHECK: llihh %r2, 65535
 ; CHECK-NEXT: oill %r2, 1
 ; CHECK-NEXT: br %r14
@@ -203,7 +205,7 @@ define i64 @f24() {
 
 ; Check the high end of the LLIHF range.
 define i64 @f25() {
-; CHECK: f25:
+; CHECK-LABEL: f25:
 ; CHECK: llihf %r2, 4294967295
 ; CHECK-NEXT: br %r14
   ret i64 -4294967296
@@ -211,7 +213,7 @@ define i64 @f25() {
 
 ; Check -1.
 define i64 @f26() {
-; CHECK: f26:
+; CHECK-LABEL: f26:
 ; CHECK: lghi %r2, -1
 ; CHECK-NEXT: br %r14
   ret i64 -1
@@ -219,7 +221,7 @@ define i64 @f26() {
 
 ; Check the low end of the LGHI range.
 define i64 @f27() {
-; CHECK: f27:
+; CHECK-LABEL: f27:
 ; CHECK: lghi %r2, -32768
 ; CHECK-NEXT: br %r14
   ret i64 -32768
@@ -227,7 +229,7 @@ define i64 @f27() {
 
 ; Check the next value down, which must use LGFI instead.
 define i64 @f28() {
-; CHECK: f28:
+; CHECK-LABEL: f28:
 ; CHECK: lgfi %r2, -32769
 ; CHECK-NEXT: br %r14
   ret i64 -32769
@@ -235,7 +237,7 @@ define i64 @f28() {
 
 ; Check the low end of the LGFI range.
 define i64 @f29() {
-; CHECK: f29:
+; CHECK-LABEL: f29:
 ; CHECK: lgfi %r2, -2147483648
 ; CHECK-NEXT: br %r14
   ret i64 -2147483648
@@ -243,9 +245,41 @@ define i64 @f29() {
 
 ; Check the next value down, which needs a two-instruction sequence.
 define i64 @f30() {
-; CHECK: f30:
+; CHECK-LABEL: f30:
 ; CHECK: llihf %r2, 4294967295
 ; CHECK-NEXT: oilf %r2, 2147483647
 ; CHECK-NEXT: br %r14
   ret i64 -2147483649
 }
+
+; Check that constant loads are rematerialized.
+define i64 @f31() {
+; CHECK-LABEL: f31:
+; CHECK-DAG: lghi %r2, 42
+; CHECK-DAG: lgfi %r3, 65537
+; CHECK-DAG: llilf %r4, 2147483649
+; CHECK-DAG: llihf %r5, 65537
+; CHECK: brasl %r14, foo@PLT
+; CHECK-DAG: llill %r2, 32768
+; CHECK-DAG: llilh %r3, 1
+; CHECK-DAG: llihl %r4, 1
+; CHECK-DAG: llihh %r5, 1
+; CHECK: brasl %r14, foo@PLT
+; CHECK-DAG: lghi %r2, 42
+; CHECK-DAG: lgfi %r3, 65537
+; CHECK-DAG: llilf %r4, 2147483649
+; CHECK-DAG: llihf %r5, 65537
+; CHECK: brasl %r14, foo@PLT
+; CHECK-DAG: llill %r2, 32768
+; CHECK-DAG: llilh %r3, 1
+; CHECK-DAG: llihl %r4, 1
+; CHECK-DAG: llihh %r5, 1
+; CHECK: brasl %r14, foo@PLT
+; CHECK: lghi %r2, 42
+; CHECK: br %r14
+  call void @foo(i64 42, i64 65537, i64 2147483649, i64 281479271677952)
+  call void @foo(i64 32768, i64 65536, i64 4294967296, i64 281474976710656)
+  call void @foo(i64 42, i64 65537, i64 2147483649, i64 281479271677952)
+  call void @foo(i64 32768, i64 65536, i64 4294967296, i64 281474976710656)
+  ret i64 42
+}
diff --git a/test/CodeGen/SystemZ/int-const-03.ll b/test/CodeGen/SystemZ/int-const-03.ll
index 807b7e4..78db963 100644
--- a/test/CodeGen/SystemZ/int-const-03.ll
+++ b/test/CodeGen/SystemZ/int-const-03.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the unsigned range.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvi 0(%r2), 0
 ; CHECK: br %r14
   store i8 0, i8 *%ptr
@@ -13,7 +13,7 @@ define void @f1(i8 *%ptr) {
 
 ; Check the high end of the signed range.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvi 0(%r2), 127
 ; CHECK: br %r14
   store i8 127, i8 *%ptr
@@ -22,7 +22,7 @@ define void @f2(i8 *%ptr) {
 
 ; Check the next value up.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: br %r14
   store i8 -128, i8 *%ptr
@@ -31,7 +31,7 @@ define void @f3(i8 *%ptr) {
 
 ; Check the high end of the unsigned range.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: br %r14
   store i8 255, i8 *%ptr
@@ -40,7 +40,7 @@ define void @f4(i8 *%ptr) {
 
 ; Check -1.
 define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvi 0(%r2), 255
 ; CHECK: br %r14
   store i8 -1, i8 *%ptr
@@ -49,7 +49,7 @@ define void @f5(i8 *%ptr) {
 
 ; Check the low end of the signed range.
 define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvi 0(%r2), 128
 ; CHECK: br %r14
   store i8 -128, i8 *%ptr
@@ -58,7 +58,7 @@ define void @f6(i8 *%ptr) {
 
 ; Check the next value down.
 define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvi 0(%r2), 127
 ; CHECK: br %r14
   store i8 -129, i8 *%ptr
@@ -67,7 +67,7 @@ define void @f7(i8 *%ptr) {
 
 ; Check the high end of the MVI range.
 define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: mvi 4095(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -77,7 +77,7 @@ define void @f8(i8 *%src) {
 
 ; Check the next byte up, which should use MVIY instead of MVI.
 define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: mviy 4096(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -87,7 +87,7 @@ define void @f9(i8 *%src) {
 
 ; Check the high end of the MVIY range.
 define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: mviy 524287(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -98,7 +98,7 @@ define void @f10(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r2, 524288
 ; CHECK: mvi 0(%r2), 42
 ; CHECK: br %r14
@@ -109,7 +109,7 @@ define void @f11(i8 *%src) {
 
 ; Check the high end of the negative MVIY range.
 define void @f12(i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mviy -1(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -119,7 +119,7 @@ define void @f12(i8 *%src) {
 
 ; Check the low end of the MVIY range.
 define void @f13(i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: mviy -524288(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -130,7 +130,7 @@ define void @f13(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f14(i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: agfi %r2, -524289
 ; CHECK: mvi 0(%r2), 42
 ; CHECK: br %r14
@@ -141,7 +141,7 @@ define void @f14(i8 *%src) {
 
 ; Check that MVI does not allow an index
 define void @f15(i64 %src, i64 %index) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: agr %r2, %r3
 ; CHECK: mvi 4095(%r2), 42
 ; CHECK: br %r14
@@ -154,7 +154,7 @@ define void @f15(i64 %src, i64 %index) {
 
 ; Check that MVIY does not allow an index
 define void @f16(i64 %src, i64 %index) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: agr %r2, %r3
 ; CHECK: mviy 4096(%r2), 42
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-const-04.ll b/test/CodeGen/SystemZ/int-const-04.ll
index 41c7306..c109faa 100644
--- a/test/CodeGen/SystemZ/int-const-04.ll
+++ b/test/CodeGen/SystemZ/int-const-04.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the unsigned range.
 define void @f1(i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvhhi 0(%r2), 0
 ; CHECK: br %r14
   store i16 0, i16 *%ptr
@@ -13,7 +13,7 @@ define void @f1(i16 *%ptr) {
 
 ; Check the high end of the signed range.
 define void @f2(i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvhhi 0(%r2), 32767
 ; CHECK: br %r14
   store i16 32767, i16 *%ptr
@@ -22,7 +22,7 @@ define void @f2(i16 *%ptr) {
 
 ; Check the next value up.
 define void @f3(i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvhhi 0(%r2), -32768
 ; CHECK: br %r14
   store i16 -32768, i16 *%ptr
@@ -31,7 +31,7 @@ define void @f3(i16 *%ptr) {
 
 ; Check the high end of the unsigned range.
 define void @f4(i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvhhi 0(%r2), -1
 ; CHECK: br %r14
   store i16 65535, i16 *%ptr
@@ -40,7 +40,7 @@ define void @f4(i16 *%ptr) {
 
 ; Check -1.
 define void @f5(i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvhhi 0(%r2), -1
 ; CHECK: br %r14
   store i16 -1, i16 *%ptr
@@ -49,7 +49,7 @@ define void @f5(i16 *%ptr) {
 
 ; Check the low end of the signed range.
 define void @f6(i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvhhi 0(%r2), -32768
 ; CHECK: br %r14
   store i16 -32768, i16 *%ptr
@@ -58,7 +58,7 @@ define void @f6(i16 *%ptr) {
 
 ; Check the next value down.
 define void @f7(i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvhhi 0(%r2), 32767
 ; CHECK: br %r14
   store i16 -32769, i16 *%ptr
@@ -67,7 +67,7 @@ define void @f7(i16 *%ptr) {
 
 ; Check the high end of the MVHHI range.
 define void @f8(i16 *%a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: mvhhi 4094(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%a, i64 2047
@@ -78,7 +78,7 @@ define void @f8(i16 *%a) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i16 *%a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mvhhi 0(%r2), 42
 ; CHECK: br %r14
@@ -89,7 +89,7 @@ define void @f9(i16 *%a) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f10(i16 *%a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: aghi %r2, -2
 ; CHECK: mvhhi 0(%r2), 42
 ; CHECK: br %r14
@@ -100,7 +100,7 @@ define void @f10(i16 *%a) {
 
 ; Check that MVHHI does not allow an index
 define void @f11(i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agr %r2, %r3
 ; CHECK: mvhhi 0(%r2), 42
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-const-05.ll b/test/CodeGen/SystemZ/int-const-05.ll
index b85fd6b..d0c8569 100644
--- a/test/CodeGen/SystemZ/int-const-05.ll
+++ b/test/CodeGen/SystemZ/int-const-05.ll
@@ -4,7 +4,7 @@
 
 ; Check moves of zero.
 define void @f1(i32 *%a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvhi 0(%r2), 0
 ; CHECK: br %r14
   store i32 0, i32 *%a
@@ -13,7 +13,7 @@ define void @f1(i32 *%a) {
 
 ; Check the high end of the signed 16-bit range.
 define void @f2(i32 *%a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvhi 0(%r2), 32767
 ; CHECK: br %r14
   store i32 32767, i32 *%a
@@ -22,7 +22,7 @@ define void @f2(i32 *%a) {
 
 ; Check the next value up, which can't use MVHI.
 define void @f3(i32 *%a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: mvhi
 ; CHECK: br %r14
   store i32 32768, i32 *%a
@@ -31,7 +31,7 @@ define void @f3(i32 *%a) {
 
 ; Check moves of -1.
 define void @f4(i32 *%a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvhi 0(%r2), -1
 ; CHECK: br %r14
   store i32 -1, i32 *%a
@@ -40,7 +40,7 @@ define void @f4(i32 *%a) {
 
 ; Check the low end of the MVHI range.
 define void @f5(i32 *%a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvhi 0(%r2), -32768
 ; CHECK: br %r14
   store i32 -32768, i32 *%a
@@ -49,7 +49,7 @@ define void @f5(i32 *%a) {
 
 ; Check the next value down, which can't use MVHI.
 define void @f6(i32 *%a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: mvhi
 ; CHECK: br %r14
   store i32 -32769, i32 *%a
@@ -58,7 +58,7 @@ define void @f6(i32 *%a) {
 
 ; Check the high end of the MVHI range.
 define void @f7(i32 *%a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvhi 4092(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%a, i64 1023
@@ -69,7 +69,7 @@ define void @f7(i32 *%a) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i32 *%a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mvhi 0(%r2), 42
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ define void @f8(i32 *%a) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f9(i32 *%a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -4
 ; CHECK: mvhi 0(%r2), 42
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define void @f9(i32 *%a) {
 
 ; Check that MVHI does not allow an index
 define void @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr %r2, %r3
 ; CHECK: mvhi 0(%r2), 42
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-const-06.ll b/test/CodeGen/SystemZ/int-const-06.ll
index 9f14347..12a555c 100644
--- a/test/CodeGen/SystemZ/int-const-06.ll
+++ b/test/CodeGen/SystemZ/int-const-06.ll
@@ -4,7 +4,7 @@
 
 ; Check moves of zero.
 define void @f1(i64 *%a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvghi 0(%r2), 0
 ; CHECK: br %r14
   store i64 0, i64 *%a
@@ -13,7 +13,7 @@ define void @f1(i64 *%a) {
 
 ; Check the high end of the signed 16-bit range.
 define void @f2(i64 *%a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvghi 0(%r2), 32767
 ; CHECK: br %r14
   store i64 32767, i64 *%a
@@ -22,7 +22,7 @@ define void @f2(i64 *%a) {
 
 ; Check the next value up, which can't use MVGHI.
 define void @f3(i64 *%a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: mvghi
 ; CHECK: br %r14
   store i64 32768, i64 *%a
@@ -31,7 +31,7 @@ define void @f3(i64 *%a) {
 
 ; Check moves of -1.
 define void @f4(i64 *%a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mvghi 0(%r2), -1
 ; CHECK: br %r14
   store i64 -1, i64 *%a
@@ -40,7 +40,7 @@ define void @f4(i64 *%a) {
 
 ; Check the low end of the MVGHI range.
 define void @f5(i64 *%a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvghi 0(%r2), -32768
 ; CHECK: br %r14
   store i64 -32768, i64 *%a
@@ -49,7 +49,7 @@ define void @f5(i64 *%a) {
 
 ; Check the next value down, which can't use MVGHI.
 define void @f6(i64 *%a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: mvghi
 ; CHECK: br %r14
   store i64 -32769, i64 *%a
@@ -58,7 +58,7 @@ define void @f6(i64 *%a) {
 
 ; Check the high end of the MVGHI range.
 define void @f7(i64 *%a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvghi 4088(%r2), 42
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%a, i64 511
@@ -69,7 +69,7 @@ define void @f7(i64 *%a) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i64 *%a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: aghi %r2, 4096
 ; CHECK: mvghi 0(%r2), 42
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ define void @f8(i64 *%a) {
 
 ; Check negative displacements, which also need separate address logic.
 define void @f9(i64 *%a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: aghi %r2, -8
 ; CHECK: mvghi 0(%r2), 42
 ; CHECK: br %r14
@@ -91,7 +91,7 @@ define void @f9(i64 *%a) {
 
 ; Check that MVGHI does not allow an index
 define void @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agr %r2, %r3
 ; CHECK: mvghi 0(%r2), 42
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/int-conv-01.ll b/test/CodeGen/SystemZ/int-conv-01.ll
index 643ac6a..e5c411c 100644
--- a/test/CodeGen/SystemZ/int-conv-01.ll
+++ b/test/CodeGen/SystemZ/int-conv-01.ll
@@ -4,9 +4,9 @@
 
 ; Test register extension, starting with an i32.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lbr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %byte = trunc i32 %a to i8
   %ext = sext i8 %byte to i32
   ret i32 %ext
@@ -14,9 +14,9 @@ define i32 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lbr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %byte = trunc i64 %a to i8
   %ext = sext i8 %byte to i32
   ret i32 %ext
@@ -24,7 +24,7 @@ define i32 @f2(i64 %a) {
 
 ; Check LB with no displacement.
 define i32 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lb %r2, 0(%r2)
 ; CHECK: br %r14
   %byte = load i8 *%src
@@ -34,7 +34,7 @@ define i32 @f3(i8 *%src) {
 
 ; Check the high end of the LB range.
 define i32 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lb %r2, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -46,7 +46,7 @@ define i32 @f4(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lb %r2, 0(%r2)
 ; CHECK: br %r14
@@ -58,7 +58,7 @@ define i32 @f5(i8 *%src) {
 
 ; Check the high end of the negative LB range.
 define i32 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lb %r2, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -69,7 +69,7 @@ define i32 @f6(i8 *%src) {
 
 ; Check the low end of the LB range.
 define i32 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lb %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -81,7 +81,7 @@ define i32 @f7(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524289
 ; CHECK: lb %r2, 0(%r2)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i32 @f8(i8 *%src) {
 
 ; Check that LB allows an index
 define i32 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lb %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -103,3 +103,97 @@ define i32 @f9(i64 %src, i64 %index) {
   %ext = sext i8 %byte to i32
   ret i32 %ext
 }
+
+; Test a case where we spill the source of at least one LBR.  We want
+; to use LB if possible.
+define void @f10(i32 *%ptr) {
+; CHECK-LABEL: f10:
+; CHECK: lb {{%r[0-9]+}}, 16{{[37]}}(%r15)
+; CHECK: br %r14
+  %val0 = load volatile i32 *%ptr
+  %val1 = load volatile i32 *%ptr
+  %val2 = load volatile i32 *%ptr
+  %val3 = load volatile i32 *%ptr
+  %val4 = load volatile i32 *%ptr
+  %val5 = load volatile i32 *%ptr
+  %val6 = load volatile i32 *%ptr
+  %val7 = load volatile i32 *%ptr
+  %val8 = load volatile i32 *%ptr
+  %val9 = load volatile i32 *%ptr
+  %val10 = load volatile i32 *%ptr
+  %val11 = load volatile i32 *%ptr
+  %val12 = load volatile i32 *%ptr
+  %val13 = load volatile i32 *%ptr
+  %val14 = load volatile i32 *%ptr
+  %val15 = load volatile i32 *%ptr
+
+  %trunc0 = trunc i32 %val0 to i8
+  %trunc1 = trunc i32 %val1 to i8
+  %trunc2 = trunc i32 %val2 to i8
+  %trunc3 = trunc i32 %val3 to i8
+  %trunc4 = trunc i32 %val4 to i8
+  %trunc5 = trunc i32 %val5 to i8
+  %trunc6 = trunc i32 %val6 to i8
+  %trunc7 = trunc i32 %val7 to i8
+  %trunc8 = trunc i32 %val8 to i8
+  %trunc9 = trunc i32 %val9 to i8
+  %trunc10 = trunc i32 %val10 to i8
+  %trunc11 = trunc i32 %val11 to i8
+  %trunc12 = trunc i32 %val12 to i8
+  %trunc13 = trunc i32 %val13 to i8
+  %trunc14 = trunc i32 %val14 to i8
+  %trunc15 = trunc i32 %val15 to i8
+
+  %ext0 = sext i8 %trunc0 to i32
+  %ext1 = sext i8 %trunc1 to i32
+  %ext2 = sext i8 %trunc2 to i32
+  %ext3 = sext i8 %trunc3 to i32
+  %ext4 = sext i8 %trunc4 to i32
+  %ext5 = sext i8 %trunc5 to i32
+  %ext6 = sext i8 %trunc6 to i32
+  %ext7 = sext i8 %trunc7 to i32
+  %ext8 = sext i8 %trunc8 to i32
+  %ext9 = sext i8 %trunc9 to i32
+  %ext10 = sext i8 %trunc10 to i32
+  %ext11 = sext i8 %trunc11 to i32
+  %ext12 = sext i8 %trunc12 to i32
+  %ext13 = sext i8 %trunc13 to i32
+  %ext14 = sext i8 %trunc14 to i32
+  %ext15 = sext i8 %trunc15 to i32
+
+  store volatile i32 %val0, i32 *%ptr
+  store volatile i32 %val1, i32 *%ptr
+  store volatile i32 %val2, i32 *%ptr
+  store volatile i32 %val3, i32 *%ptr
+  store volatile i32 %val4, i32 *%ptr
+  store volatile i32 %val5, i32 *%ptr
+  store volatile i32 %val6, i32 *%ptr
+  store volatile i32 %val7, i32 *%ptr
+  store volatile i32 %val8, i32 *%ptr
+  store volatile i32 %val9, i32 *%ptr
+  store volatile i32 %val10, i32 *%ptr
+  store volatile i32 %val11, i32 *%ptr
+  store volatile i32 %val12, i32 *%ptr
+  store volatile i32 %val13, i32 *%ptr
+  store volatile i32 %val14, i32 *%ptr
+  store volatile i32 %val15, i32 *%ptr
+
+  store volatile i32 %ext0, i32 *%ptr
+  store volatile i32 %ext1, i32 *%ptr
+  store volatile i32 %ext2, i32 *%ptr
+  store volatile i32 %ext3, i32 *%ptr
+  store volatile i32 %ext4, i32 *%ptr
+  store volatile i32 %ext5, i32 *%ptr
+  store volatile i32 %ext6, i32 *%ptr
+  store volatile i32 %ext7, i32 *%ptr
+  store volatile i32 %ext8, i32 *%ptr
+  store volatile i32 %ext9, i32 *%ptr
+  store volatile i32 %ext10, i32 *%ptr
+  store volatile i32 %ext11, i32 *%ptr
+  store volatile i32 %ext12, i32 *%ptr
+  store volatile i32 %ext13, i32 *%ptr
+  store volatile i32 %ext14, i32 *%ptr
+  store volatile i32 %ext15, i32 *%ptr
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/int-conv-02.ll b/test/CodeGen/SystemZ/int-conv-02.ll
index 86144d3..18cfd4a 100644
--- a/test/CodeGen/SystemZ/int-conv-02.ll
+++ b/test/CodeGen/SystemZ/int-conv-02.ll
@@ -4,9 +4,9 @@
 
 ; Test register extension, starting with an i32.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llcr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %byte = trunc i32 %a to i8
   %ext = zext i8 %byte to i32
   ret i32 %ext
@@ -14,9 +14,9 @@ define i32 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llcr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %byte = trunc i64 %a to i8
   %ext = zext i8 %byte to i32
   ret i32 %ext
@@ -24,16 +24,16 @@ define i32 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llcr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %ext = and i32 %a, 255
   ret i32 %ext
 }
 
 ; Check LLC with no displacement.
 define i32 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llc %r2, 0(%r2)
 ; CHECK: br %r14
   %byte = load i8 *%src
@@ -43,7 +43,7 @@ define i32 @f4(i8 *%src) {
 
 ; Check the high end of the LLC range.
 define i32 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llc %r2, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -55,7 +55,7 @@ define i32 @f5(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llc %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i32 @f6(i8 *%src) {
 
 ; Check the high end of the negative LLC range.
 define i32 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llc %r2, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -78,7 +78,7 @@ define i32 @f7(i8 *%src) {
 
 ; Check the low end of the LLC range.
 define i32 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llc %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -90,7 +90,7 @@ define i32 @f8(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524289
 ; CHECK: llc %r2, 0(%r2)
 ; CHECK: br %r14
@@ -102,7 +102,7 @@ define i32 @f9(i8 *%src) {
 
 ; Check that LLC allows an index
 define i32 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llc %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -112,3 +112,97 @@ define i32 @f10(i64 %src, i64 %index) {
   %ext = zext i8 %byte to i32
   ret i32 %ext
 }
+
+; Test a case where we spill the source of at least one LLCR.  We want
+; to use LLC if possible.
+define void @f11(i32 *%ptr) {
+; CHECK-LABEL: f11:
+; CHECK: llc {{%r[0-9]+}}, 16{{[37]}}(%r15)
+; CHECK: br %r14
+  %val0 = load volatile i32 *%ptr
+  %val1 = load volatile i32 *%ptr
+  %val2 = load volatile i32 *%ptr
+  %val3 = load volatile i32 *%ptr
+  %val4 = load volatile i32 *%ptr
+  %val5 = load volatile i32 *%ptr
+  %val6 = load volatile i32 *%ptr
+  %val7 = load volatile i32 *%ptr
+  %val8 = load volatile i32 *%ptr
+  %val9 = load volatile i32 *%ptr
+  %val10 = load volatile i32 *%ptr
+  %val11 = load volatile i32 *%ptr
+  %val12 = load volatile i32 *%ptr
+  %val13 = load volatile i32 *%ptr
+  %val14 = load volatile i32 *%ptr
+  %val15 = load volatile i32 *%ptr
+
+  %trunc0 = trunc i32 %val0 to i8
+  %trunc1 = trunc i32 %val1 to i8
+  %trunc2 = trunc i32 %val2 to i8
+  %trunc3 = trunc i32 %val3 to i8
+  %trunc4 = trunc i32 %val4 to i8
+  %trunc5 = trunc i32 %val5 to i8
+  %trunc6 = trunc i32 %val6 to i8
+  %trunc7 = trunc i32 %val7 to i8
+  %trunc8 = trunc i32 %val8 to i8
+  %trunc9 = trunc i32 %val9 to i8
+  %trunc10 = trunc i32 %val10 to i8
+  %trunc11 = trunc i32 %val11 to i8
+  %trunc12 = trunc i32 %val12 to i8
+  %trunc13 = trunc i32 %val13 to i8
+  %trunc14 = trunc i32 %val14 to i8
+  %trunc15 = trunc i32 %val15 to i8
+
+  %ext0 = zext i8 %trunc0 to i32
+  %ext1 = zext i8 %trunc1 to i32
+  %ext2 = zext i8 %trunc2 to i32
+  %ext3 = zext i8 %trunc3 to i32
+  %ext4 = zext i8 %trunc4 to i32
+  %ext5 = zext i8 %trunc5 to i32
+  %ext6 = zext i8 %trunc6 to i32
+  %ext7 = zext i8 %trunc7 to i32
+  %ext8 = zext i8 %trunc8 to i32
+  %ext9 = zext i8 %trunc9 to i32
+  %ext10 = zext i8 %trunc10 to i32
+  %ext11 = zext i8 %trunc11 to i32
+  %ext12 = zext i8 %trunc12 to i32
+  %ext13 = zext i8 %trunc13 to i32
+  %ext14 = zext i8 %trunc14 to i32
+  %ext15 = zext i8 %trunc15 to i32
+
+  store volatile i32 %val0, i32 *%ptr
+  store volatile i32 %val1, i32 *%ptr
+  store volatile i32 %val2, i32 *%ptr
+  store volatile i32 %val3, i32 *%ptr
+  store volatile i32 %val4, i32 *%ptr
+  store volatile i32 %val5, i32 *%ptr
+  store volatile i32 %val6, i32 *%ptr
+  store volatile i32 %val7, i32 *%ptr
+  store volatile i32 %val8, i32 *%ptr
+  store volatile i32 %val9, i32 *%ptr
+  store volatile i32 %val10, i32 *%ptr
+  store volatile i32 %val11, i32 *%ptr
+  store volatile i32 %val12, i32 *%ptr
+  store volatile i32 %val13, i32 *%ptr
+  store volatile i32 %val14, i32 *%ptr
+  store volatile i32 %val15, i32 *%ptr
+
+  store volatile i32 %ext0, i32 *%ptr
+  store volatile i32 %ext1, i32 *%ptr
+  store volatile i32 %ext2, i32 *%ptr
+  store volatile i32 %ext3, i32 *%ptr
+  store volatile i32 %ext4, i32 *%ptr
+  store volatile i32 %ext5, i32 *%ptr
+  store volatile i32 %ext6, i32 *%ptr
+  store volatile i32 %ext7, i32 *%ptr
+  store volatile i32 %ext8, i32 *%ptr
+  store volatile i32 %ext9, i32 *%ptr
+  store volatile i32 %ext10, i32 *%ptr
+  store volatile i32 %ext11, i32 *%ptr
+  store volatile i32 %ext12, i32 *%ptr
+  store volatile i32 %ext13, i32 *%ptr
+  store volatile i32 %ext14, i32 *%ptr
+  store volatile i32 %ext15, i32 *%ptr
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/int-conv-03.ll b/test/CodeGen/SystemZ/int-conv-03.ll
index 73b8dbb..cad9581 100644
--- a/test/CodeGen/SystemZ/int-conv-03.ll
+++ b/test/CodeGen/SystemZ/int-conv-03.ll
@@ -4,9 +4,9 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lgbr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %byte = trunc i32 %a to i8
   %ext = sext i8 %byte to i64
   ret i64 %ext
@@ -14,9 +14,9 @@ define i64 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lgbr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %byte = trunc i64 %a to i8
   %ext = sext i8 %byte to i64
   ret i64 %ext
@@ -24,7 +24,7 @@ define i64 @f2(i64 %a) {
 
 ; Check LGB with no displacement.
 define i64 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgb %r2, 0(%r2)
 ; CHECK: br %r14
   %byte = load i8 *%src
@@ -34,7 +34,7 @@ define i64 @f3(i8 *%src) {
 
 ; Check the high end of the LGB range.
 define i64 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgb %r2, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -46,7 +46,7 @@ define i64 @f4(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lgb %r2, 0(%r2)
 ; CHECK: br %r14
@@ -58,7 +58,7 @@ define i64 @f5(i8 *%src) {
 
 ; Check the high end of the negative LGB range.
 define i64 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgb %r2, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -69,7 +69,7 @@ define i64 @f6(i8 *%src) {
 
 ; Check the low end of the LGB range.
 define i64 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgb %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -81,7 +81,7 @@ define i64 @f7(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524289
 ; CHECK: lgb %r2, 0(%r2)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i64 @f8(i8 *%src) {
 
 ; Check that LGB allows an index
 define i64 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lgb %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -103,3 +103,97 @@ define i64 @f9(i64 %src, i64 %index) {
   %ext = sext i8 %byte to i64
   ret i64 %ext
 }
+
+; Test a case where we spill the source of at least one LGBR.  We want
+; to use LGB if possible.
+define void @f10(i64 *%ptr) {
+; CHECK-LABEL: f10:
+; CHECK: lgb {{%r[0-9]+}}, 167(%r15)
+; CHECK: br %r14
+  %val0 = load volatile i64 *%ptr
+  %val1 = load volatile i64 *%ptr
+  %val2 = load volatile i64 *%ptr
+  %val3 = load volatile i64 *%ptr
+  %val4 = load volatile i64 *%ptr
+  %val5 = load volatile i64 *%ptr
+  %val6 = load volatile i64 *%ptr
+  %val7 = load volatile i64 *%ptr
+  %val8 = load volatile i64 *%ptr
+  %val9 = load volatile i64 *%ptr
+  %val10 = load volatile i64 *%ptr
+  %val11 = load volatile i64 *%ptr
+  %val12 = load volatile i64 *%ptr
+  %val13 = load volatile i64 *%ptr
+  %val14 = load volatile i64 *%ptr
+  %val15 = load volatile i64 *%ptr
+
+  %trunc0 = trunc i64 %val0 to i8
+  %trunc1 = trunc i64 %val1 to i8
+  %trunc2 = trunc i64 %val2 to i8
+  %trunc3 = trunc i64 %val3 to i8
+  %trunc4 = trunc i64 %val4 to i8
+  %trunc5 = trunc i64 %val5 to i8
+  %trunc6 = trunc i64 %val6 to i8
+  %trunc7 = trunc i64 %val7 to i8
+  %trunc8 = trunc i64 %val8 to i8
+  %trunc9 = trunc i64 %val9 to i8
+  %trunc10 = trunc i64 %val10 to i8
+  %trunc11 = trunc i64 %val11 to i8
+  %trunc12 = trunc i64 %val12 to i8
+  %trunc13 = trunc i64 %val13 to i8
+  %trunc14 = trunc i64 %val14 to i8
+  %trunc15 = trunc i64 %val15 to i8
+
+  %ext0 = sext i8 %trunc0 to i64
+  %ext1 = sext i8 %trunc1 to i64
+  %ext2 = sext i8 %trunc2 to i64
+  %ext3 = sext i8 %trunc3 to i64
+  %ext4 = sext i8 %trunc4 to i64
+  %ext5 = sext i8 %trunc5 to i64
+  %ext6 = sext i8 %trunc6 to i64
+  %ext7 = sext i8 %trunc7 to i64
+  %ext8 = sext i8 %trunc8 to i64
+  %ext9 = sext i8 %trunc9 to i64
+  %ext10 = sext i8 %trunc10 to i64
+  %ext11 = sext i8 %trunc11 to i64
+  %ext12 = sext i8 %trunc12 to i64
+  %ext13 = sext i8 %trunc13 to i64
+  %ext14 = sext i8 %trunc14 to i64
+  %ext15 = sext i8 %trunc15 to i64
+
+  store volatile i64 %val0, i64 *%ptr
+  store volatile i64 %val1, i64 *%ptr
+  store volatile i64 %val2, i64 *%ptr
+  store volatile i64 %val3, i64 *%ptr
+  store volatile i64 %val4, i64 *%ptr
+  store volatile i64 %val5, i64 *%ptr
+  store volatile i64 %val6, i64 *%ptr
+  store volatile i64 %val7, i64 *%ptr
+  store volatile i64 %val8, i64 *%ptr
+  store volatile i64 %val9, i64 *%ptr
+  store volatile i64 %val10, i64 *%ptr
+  store volatile i64 %val11, i64 *%ptr
+  store volatile i64 %val12, i64 *%ptr
+  store volatile i64 %val13, i64 *%ptr
+  store volatile i64 %val14, i64 *%ptr
+  store volatile i64 %val15, i64 *%ptr
+
+  store volatile i64 %ext0, i64 *%ptr
+  store volatile i64 %ext1, i64 *%ptr
+  store volatile i64 %ext2, i64 *%ptr
+  store volatile i64 %ext3, i64 *%ptr
+  store volatile i64 %ext4, i64 *%ptr
+  store volatile i64 %ext5, i64 *%ptr
+  store volatile i64 %ext6, i64 *%ptr
+  store volatile i64 %ext7, i64 *%ptr
+  store volatile i64 %ext8, i64 *%ptr
+  store volatile i64 %ext9, i64 *%ptr
+  store volatile i64 %ext10, i64 *%ptr
+  store volatile i64 %ext11, i64 *%ptr
+  store volatile i64 %ext12, i64 *%ptr
+  store volatile i64 %ext13, i64 *%ptr
+  store volatile i64 %ext14, i64 *%ptr
+  store volatile i64 %ext15, i64 *%ptr
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/int-conv-04.ll b/test/CodeGen/SystemZ/int-conv-04.ll
index 4cec524..1c6be7b 100644
--- a/test/CodeGen/SystemZ/int-conv-04.ll
+++ b/test/CodeGen/SystemZ/int-conv-04.ll
@@ -4,9 +4,9 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llgcr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %byte = trunc i32 %a to i8
   %ext = zext i8 %byte to i64
   ret i64 %ext
@@ -14,9 +14,9 @@ define i64 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llgcr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %byte = trunc i64 %a to i8
   %ext = zext i8 %byte to i64
   ret i64 %ext
@@ -24,16 +24,16 @@ define i64 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llgcr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %ext = and i64 %a, 255
   ret i64 %ext
 }
 
 ; Check LLGC with no displacement.
 define i64 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
   %byte = load i8 *%src
@@ -43,7 +43,7 @@ define i64 @f4(i8 *%src) {
 
 ; Check the high end of the LLGC range.
 define i64 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llgc %r2, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -55,7 +55,7 @@ define i64 @f5(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i64 @f6(i8 *%src) {
 
 ; Check the high end of the negative LLGC range.
 define i64 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llgc %r2, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -78,7 +78,7 @@ define i64 @f7(i8 *%src) {
 
 ; Check the low end of the LLGC range.
 define i64 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llgc %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -90,7 +90,7 @@ define i64 @f8(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524289
 ; CHECK: llgc %r2, 0(%r2)
 ; CHECK: br %r14
@@ -102,7 +102,7 @@ define i64 @f9(i8 *%src) {
 
 ; Check that LLGC allows an index
 define i64 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llgc %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -112,3 +112,97 @@ define i64 @f10(i64 %src, i64 %index) {
   %ext = zext i8 %byte to i64
   ret i64 %ext
 }
+
+; Test a case where we spill the source of at least one LLGCR.  We want
+; to use LLGC if possible.
+define void @f11(i64 *%ptr) {
+; CHECK-LABEL: f11:
+; CHECK: llgc {{%r[0-9]+}}, 167(%r15)
+; CHECK: br %r14
+  %val0 = load volatile i64 *%ptr
+  %val1 = load volatile i64 *%ptr
+  %val2 = load volatile i64 *%ptr
+  %val3 = load volatile i64 *%ptr
+  %val4 = load volatile i64 *%ptr
+  %val5 = load volatile i64 *%ptr
+  %val6 = load volatile i64 *%ptr
+  %val7 = load volatile i64 *%ptr
+  %val8 = load volatile i64 *%ptr
+  %val9 = load volatile i64 *%ptr
+  %val10 = load volatile i64 *%ptr
+  %val11 = load volatile i64 *%ptr
+  %val12 = load volatile i64 *%ptr
+  %val13 = load volatile i64 *%ptr
+  %val14 = load volatile i64 *%ptr
+  %val15 = load volatile i64 *%ptr
+
+  %trunc0 = trunc i64 %val0 to i8
+  %trunc1 = trunc i64 %val1 to i8
+  %trunc2 = trunc i64 %val2 to i8
+  %trunc3 = trunc i64 %val3 to i8
+  %trunc4 = trunc i64 %val4 to i8
+  %trunc5 = trunc i64 %val5 to i8
+  %trunc6 = trunc i64 %val6 to i8
+  %trunc7 = trunc i64 %val7 to i8
+  %trunc8 = trunc i64 %val8 to i8
+  %trunc9 = trunc i64 %val9 to i8
+  %trunc10 = trunc i64 %val10 to i8
+  %trunc11 = trunc i64 %val11 to i8
+  %trunc12 = trunc i64 %val12 to i8
+  %trunc13 = trunc i64 %val13 to i8
+  %trunc14 = trunc i64 %val14 to i8
+  %trunc15 = trunc i64 %val15 to i8
+
+  %ext0 = zext i8 %trunc0 to i64
+  %ext1 = zext i8 %trunc1 to i64
+  %ext2 = zext i8 %trunc2 to i64
+  %ext3 = zext i8 %trunc3 to i64
+  %ext4 = zext i8 %trunc4 to i64
+  %ext5 = zext i8 %trunc5 to i64
+  %ext6 = zext i8 %trunc6 to i64
+  %ext7 = zext i8 %trunc7 to i64
+  %ext8 = zext i8 %trunc8 to i64
+  %ext9 = zext i8 %trunc9 to i64
+  %ext10 = zext i8 %trunc10 to i64
+  %ext11 = zext i8 %trunc11 to i64
+  %ext12 = zext i8 %trunc12 to i64
+  %ext13 = zext i8 %trunc13 to i64
+  %ext14 = zext i8 %trunc14 to i64
+  %ext15 = zext i8 %trunc15 to i64
+
+  store volatile i64 %val0, i64 *%ptr
+  store volatile i64 %val1, i64 *%ptr
+  store volatile i64 %val2, i64 *%ptr
+  store volatile i64 %val3, i64 *%ptr
+  store volatile i64 %val4, i64 *%ptr
+  store volatile i64 %val5, i64 *%ptr
+  store volatile i64 %val6, i64 *%ptr
+  store volatile i64 %val7, i64 *%ptr
+  store volatile i64 %val8, i64 *%ptr
+  store volatile i64 %val9, i64 *%ptr
+  store volatile i64 %val10, i64 *%ptr
+  store volatile i64 %val11, i64 *%ptr
+  store volatile i64 %val12, i64 *%ptr
+  store volatile i64 %val13, i64 *%ptr
+  store volatile i64 %val14, i64 *%ptr
+  store volatile i64 %val15, i64 *%ptr
+
+  store volatile i64 %ext0, i64 *%ptr
+  store volatile i64 %ext1, i64 *%ptr
+  store volatile i64 %ext2, i64 *%ptr
+  store volatile i64 %ext3, i64 *%ptr
+  store volatile i64 %ext4, i64 *%ptr
+  store volatile i64 %ext5, i64 *%ptr
+  store volatile i64 %ext6, i64 *%ptr
+  store volatile i64 %ext7, i64 *%ptr
+  store volatile i64 %ext8, i64 *%ptr
+  store volatile i64 %ext9, i64 *%ptr
+  store volatile i64 %ext10, i64 *%ptr
+  store volatile i64 %ext11, i64 *%ptr
+  store volatile i64 %ext12, i64 *%ptr
+  store volatile i64 %ext13, i64 *%ptr
+  store volatile i64 %ext14, i64 *%ptr
+  store volatile i64 %ext15, i64 *%ptr
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/int-conv-05.ll b/test/CodeGen/SystemZ/int-conv-05.ll
index 5358f7d..5eade93 100644
--- a/test/CodeGen/SystemZ/int-conv-05.ll
+++ b/test/CodeGen/SystemZ/int-conv-05.ll
@@ -4,9 +4,9 @@
 
 ; Test register extension, starting with an i32.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %half = trunc i32 %a to i16
   %ext = sext i16 %half to i32
   ret i32 %ext
@@ -14,9 +14,9 @@ define i32 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lhr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %half = trunc i64 %a to i16
   %ext = sext i16 %half to i32
   ret i32 %ext
@@ -24,7 +24,7 @@ define i32 @f2(i64 %a) {
 
 ; Check the low end of the LH range.
 define i32 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -34,7 +34,7 @@ define i32 @f3(i16 *%src) {
 
 ; Check the high end of the LH range.
 define i32 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lh %r2, 4094(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2047
@@ -45,7 +45,7 @@ define i32 @f4(i16 *%src) {
 
 ; Check the next halfword up, which needs LHY rather than LH.
 define i32 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lhy %r2, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2048
@@ -56,7 +56,7 @@ define i32 @f5(i16 *%src) {
 
 ; Check the high end of the LHY range.
 define i32 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lhy %r2, 524286(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -68,7 +68,7 @@ define i32 @f6(i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -80,7 +80,7 @@ define i32 @f7(i16 *%src) {
 
 ; Check the high end of the negative LHY range.
 define i32 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lhy %r2, -2(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -91,7 +91,7 @@ define i32 @f8(i16 *%src) {
 
 ; Check the low end of the LHY range.
 define i32 @f9(i16 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lhy %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -103,7 +103,7 @@ define i32 @f9(i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f10(i16 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524290
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -115,7 +115,7 @@ define i32 @f10(i16 *%src) {
 
 ; Check that LH allows an index
 define i32 @f11(i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: lh %r2, 4094(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -128,7 +128,7 @@ define i32 @f11(i64 %src, i64 %index) {
 
 ; Check that LH allows an index
 define i32 @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: lhy %r2, 4096(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -138,3 +138,97 @@ define i32 @f12(i64 %src, i64 %index) {
   %ext = sext i16 %half to i32
   ret i32 %ext
 }
+
+; Test a case where we spill the source of at least one LHR.  We want
+; to use LH if possible.
+define void @f13(i32 *%ptr) {
+; CHECK-LABEL: f13:
+; CHECK: lh {{%r[0-9]+}}, 16{{[26]}}(%r15)
+; CHECK: br %r14
+  %val0 = load volatile i32 *%ptr
+  %val1 = load volatile i32 *%ptr
+  %val2 = load volatile i32 *%ptr
+  %val3 = load volatile i32 *%ptr
+  %val4 = load volatile i32 *%ptr
+  %val5 = load volatile i32 *%ptr
+  %val6 = load volatile i32 *%ptr
+  %val7 = load volatile i32 *%ptr
+  %val8 = load volatile i32 *%ptr
+  %val9 = load volatile i32 *%ptr
+  %val10 = load volatile i32 *%ptr
+  %val11 = load volatile i32 *%ptr
+  %val12 = load volatile i32 *%ptr
+  %val13 = load volatile i32 *%ptr
+  %val14 = load volatile i32 *%ptr
+  %val15 = load volatile i32 *%ptr
+
+  %trunc0 = trunc i32 %val0 to i16
+  %trunc1 = trunc i32 %val1 to i16
+  %trunc2 = trunc i32 %val2 to i16
+  %trunc3 = trunc i32 %val3 to i16
+  %trunc4 = trunc i32 %val4 to i16
+  %trunc5 = trunc i32 %val5 to i16
+  %trunc6 = trunc i32 %val6 to i16
+  %trunc7 = trunc i32 %val7 to i16
+  %trunc8 = trunc i32 %val8 to i16
+  %trunc9 = trunc i32 %val9 to i16
+  %trunc10 = trunc i32 %val10 to i16
+  %trunc11 = trunc i32 %val11 to i16
+  %trunc12 = trunc i32 %val12 to i16
+  %trunc13 = trunc i32 %val13 to i16
+  %trunc14 = trunc i32 %val14 to i16
+  %trunc15 = trunc i32 %val15 to i16
+
+  %ext0 = sext i16 %trunc0 to i32
+  %ext1 = sext i16 %trunc1 to i32
+  %ext2 = sext i16 %trunc2 to i32
+  %ext3 = sext i16 %trunc3 to i32
+  %ext4 = sext i16 %trunc4 to i32
+  %ext5 = sext i16 %trunc5 to i32
+  %ext6 = sext i16 %trunc6 to i32
+  %ext7 = sext i16 %trunc7 to i32
+  %ext8 = sext i16 %trunc8 to i32
+  %ext9 = sext i16 %trunc9 to i32
+  %ext10 = sext i16 %trunc10 to i32
+  %ext11 = sext i16 %trunc11 to i32
+  %ext12 = sext i16 %trunc12 to i32
+  %ext13 = sext i16 %trunc13 to i32
+  %ext14 = sext i16 %trunc14 to i32
+  %ext15 = sext i16 %trunc15 to i32
+
+  store volatile i32 %val0, i32 *%ptr
+  store volatile i32 %val1, i32 *%ptr
+  store volatile i32 %val2, i32 *%ptr
+  store volatile i32 %val3, i32 *%ptr
+  store volatile i32 %val4, i32 *%ptr
+  store volatile i32 %val5, i32 *%ptr
+  store volatile i32 %val6, i32 *%ptr
+  store volatile i32 %val7, i32 *%ptr
+  store volatile i32 %val8, i32 *%ptr
+  store volatile i32 %val9, i32 *%ptr
+  store volatile i32 %val10, i32 *%ptr
+  store volatile i32 %val11, i32 *%ptr
+  store volatile i32 %val12, i32 *%ptr
+  store volatile i32 %val13, i32 *%ptr
+  store volatile i32 %val14, i32 *%ptr
+  store volatile i32 %val15, i32 *%ptr
+
+  store volatile i32 %ext0, i32 *%ptr
+  store volatile i32 %ext1, i32 *%ptr
+  store volatile i32 %ext2, i32 *%ptr
+  store volatile i32 %ext3, i32 *%ptr
+  store volatile i32 %ext4, i32 *%ptr
+  store volatile i32 %ext5, i32 *%ptr
+  store volatile i32 %ext6, i32 *%ptr
+  store volatile i32 %ext7, i32 *%ptr
+  store volatile i32 %ext8, i32 *%ptr
+  store volatile i32 %ext9, i32 *%ptr
+  store volatile i32 %ext10, i32 *%ptr
+  store volatile i32 %ext11, i32 *%ptr
+  store volatile i32 %ext12, i32 *%ptr
+  store volatile i32 %ext13, i32 *%ptr
+  store volatile i32 %ext14, i32 *%ptr
+  store volatile i32 %ext15, i32 *%ptr
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/int-conv-06.ll b/test/CodeGen/SystemZ/int-conv-06.ll
index 64af612..9c95bad 100644
--- a/test/CodeGen/SystemZ/int-conv-06.ll
+++ b/test/CodeGen/SystemZ/int-conv-06.ll
@@ -4,9 +4,9 @@
 
 ; Test register extension, starting with an i32.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llhr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %half = trunc i32 %a to i16
   %ext = zext i16 %half to i32
   ret i32 %ext
@@ -14,9 +14,9 @@ define i32 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llhr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %half = trunc i64 %a to i16
   %ext = zext i16 %half to i32
   ret i32 %ext
@@ -24,16 +24,16 @@ define i32 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llhr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %ext = and i32 %a, 65535
   ret i32 %ext
 }
 
 ; Check LLH with no displacement.
 define i32 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llh %r2, 0(%r2)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -43,7 +43,7 @@ define i32 @f4(i16 *%src) {
 
 ; Check the high end of the LLH range.
 define i32 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llh %r2, 524286(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -55,7 +55,7 @@ define i32 @f5(i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i32 @f6(i16 *%src) {
 
 ; Check the high end of the negative LLH range.
 define i32 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llh %r2, -2(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -78,7 +78,7 @@ define i32 @f7(i16 *%src) {
 
 ; Check the low end of the LLH range.
 define i32 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llh %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -90,7 +90,7 @@ define i32 @f8(i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i16 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524290
 ; CHECK: llh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -102,7 +102,7 @@ define i32 @f9(i16 *%src) {
 
 ; Check that LLH allows an index
 define i32 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llh %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -112,3 +112,97 @@ define i32 @f10(i64 %src, i64 %index) {
   %ext = zext i16 %half to i32
   ret i32 %ext
 }
+
+; Test a case where we spill the source of at least one LLHR.  We want
+; to use LLH if possible.
+define void @f11(i32 *%ptr) {
+; CHECK-LABEL: f11:
+; CHECK: llh {{%r[0-9]+}}, 16{{[26]}}(%r15)
+; CHECK: br %r14
+  %val0 = load volatile i32 *%ptr
+  %val1 = load volatile i32 *%ptr
+  %val2 = load volatile i32 *%ptr
+  %val3 = load volatile i32 *%ptr
+  %val4 = load volatile i32 *%ptr
+  %val5 = load volatile i32 *%ptr
+  %val6 = load volatile i32 *%ptr
+  %val7 = load volatile i32 *%ptr
+  %val8 = load volatile i32 *%ptr
+  %val9 = load volatile i32 *%ptr
+  %val10 = load volatile i32 *%ptr
+  %val11 = load volatile i32 *%ptr
+  %val12 = load volatile i32 *%ptr
+  %val13 = load volatile i32 *%ptr
+  %val14 = load volatile i32 *%ptr
+  %val15 = load volatile i32 *%ptr
+
+  %trunc0 = trunc i32 %val0 to i16
+  %trunc1 = trunc i32 %val1 to i16
+  %trunc2 = trunc i32 %val2 to i16
+  %trunc3 = trunc i32 %val3 to i16
+  %trunc4 = trunc i32 %val4 to i16
+  %trunc5 = trunc i32 %val5 to i16
+  %trunc6 = trunc i32 %val6 to i16
+  %trunc7 = trunc i32 %val7 to i16
+  %trunc8 = trunc i32 %val8 to i16
+  %trunc9 = trunc i32 %val9 to i16
+  %trunc10 = trunc i32 %val10 to i16
+  %trunc11 = trunc i32 %val11 to i16
+  %trunc12 = trunc i32 %val12 to i16
+  %trunc13 = trunc i32 %val13 to i16
+  %trunc14 = trunc i32 %val14 to i16
+  %trunc15 = trunc i32 %val15 to i16
+
+  %ext0 = zext i16 %trunc0 to i32
+  %ext1 = zext i16 %trunc1 to i32
+  %ext2 = zext i16 %trunc2 to i32
+  %ext3 = zext i16 %trunc3 to i32
+  %ext4 = zext i16 %trunc4 to i32
+  %ext5 = zext i16 %trunc5 to i32
+  %ext6 = zext i16 %trunc6 to i32
+  %ext7 = zext i16 %trunc7 to i32
+  %ext8 = zext i16 %trunc8 to i32
+  %ext9 = zext i16 %trunc9 to i32
+  %ext10 = zext i16 %trunc10 to i32
+  %ext11 = zext i16 %trunc11 to i32
+  %ext12 = zext i16 %trunc12 to i32
+  %ext13 = zext i16 %trunc13 to i32
+  %ext14 = zext i16 %trunc14 to i32
+  %ext15 = zext i16 %trunc15 to i32
+
+  store volatile i32 %val0, i32 *%ptr
+  store volatile i32 %val1, i32 *%ptr
+  store volatile i32 %val2, i32 *%ptr
+  store volatile i32 %val3, i32 *%ptr
+  store volatile i32 %val4, i32 *%ptr
+  store volatile i32 %val5, i32 *%ptr
+  store volatile i32 %val6, i32 *%ptr
+  store volatile i32 %val7, i32 *%ptr
+  store volatile i32 %val8, i32 *%ptr
+  store volatile i32 %val9, i32 *%ptr
+  store volatile i32 %val10, i32 *%ptr
+  store volatile i32 %val11, i32 *%ptr
+  store volatile i32 %val12, i32 *%ptr
+  store volatile i32 %val13, i32 *%ptr
+  store volatile i32 %val14, i32 *%ptr
+  store volatile i32 %val15, i32 *%ptr
+
+  store volatile i32 %ext0, i32 *%ptr
+  store volatile i32 %ext1, i32 *%ptr
+  store volatile i32 %ext2, i32 *%ptr
+  store volatile i32 %ext3, i32 *%ptr
+  store volatile i32 %ext4, i32 *%ptr
+  store volatile i32 %ext5, i32 *%ptr
+  store volatile i32 %ext6, i32 *%ptr
+  store volatile i32 %ext7, i32 *%ptr
+  store volatile i32 %ext8, i32 *%ptr
+  store volatile i32 %ext9, i32 *%ptr
+  store volatile i32 %ext10, i32 *%ptr
+  store volatile i32 %ext11, i32 *%ptr
+  store volatile i32 %ext12, i32 *%ptr
+  store volatile i32 %ext13, i32 *%ptr
+  store volatile i32 %ext14, i32 *%ptr
+  store volatile i32 %ext15, i32 *%ptr
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/int-conv-07.ll b/test/CodeGen/SystemZ/int-conv-07.ll
index 041caa2..4b78c77 100644
--- a/test/CodeGen/SystemZ/int-conv-07.ll
+++ b/test/CodeGen/SystemZ/int-conv-07.ll
@@ -4,9 +4,9 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lghr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %half = trunc i64 %a to i16
   %ext = sext i16 %half to i64
   ret i64 %ext
@@ -14,9 +14,9 @@ define i64 @f1(i64 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lghr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %half = trunc i32 %a to i16
   %ext = sext i16 %half to i64
   ret i64 %ext
@@ -24,7 +24,7 @@ define i64 @f2(i32 %a) {
 
 ; Check LGH with no displacement.
 define i64 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgh %r2, 0(%r2)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -34,7 +34,7 @@ define i64 @f3(i16 *%src) {
 
 ; Check the high end of the LGH range.
 define i64 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgh %r2, 524286(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -46,7 +46,7 @@ define i64 @f4(i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lgh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -58,7 +58,7 @@ define i64 @f5(i16 *%src) {
 
 ; Check the high end of the negative LGH range.
 define i64 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgh %r2, -2(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -69,7 +69,7 @@ define i64 @f6(i16 *%src) {
 
 ; Check the low end of the LGH range.
 define i64 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgh %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -81,7 +81,7 @@ define i64 @f7(i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524290
 ; CHECK: lgh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i64 @f8(i16 *%src) {
 
 ; Check that LGH allows an index.
 define i64 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lgh %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -103,3 +103,97 @@ define i64 @f9(i64 %src, i64 %index) {
   %ext = sext i16 %half to i64
   ret i64 %ext
 }
+
+; Test a case where we spill the source of at least one LGHR.  We want
+; to use LGH if possible.
+define void @f10(i64 *%ptr) {
+; CHECK-LABEL: f10:
+; CHECK: lgh {{%r[0-9]+}}, 166(%r15)
+; CHECK: br %r14
+  %val0 = load volatile i64 *%ptr
+  %val1 = load volatile i64 *%ptr
+  %val2 = load volatile i64 *%ptr
+  %val3 = load volatile i64 *%ptr
+  %val4 = load volatile i64 *%ptr
+  %val5 = load volatile i64 *%ptr
+  %val6 = load volatile i64 *%ptr
+  %val7 = load volatile i64 *%ptr
+  %val8 = load volatile i64 *%ptr
+  %val9 = load volatile i64 *%ptr
+  %val10 = load volatile i64 *%ptr
+  %val11 = load volatile i64 *%ptr
+  %val12 = load volatile i64 *%ptr
+  %val13 = load volatile i64 *%ptr
+  %val14 = load volatile i64 *%ptr
+  %val15 = load volatile i64 *%ptr
+
+  %trunc0 = trunc i64 %val0 to i16
+  %trunc1 = trunc i64 %val1 to i16
+  %trunc2 = trunc i64 %val2 to i16
+  %trunc3 = trunc i64 %val3 to i16
+  %trunc4 = trunc i64 %val4 to i16
+  %trunc5 = trunc i64 %val5 to i16
+  %trunc6 = trunc i64 %val6 to i16
+  %trunc7 = trunc i64 %val7 to i16
+  %trunc8 = trunc i64 %val8 to i16
+  %trunc9 = trunc i64 %val9 to i16
+  %trunc10 = trunc i64 %val10 to i16
+  %trunc11 = trunc i64 %val11 to i16
+  %trunc12 = trunc i64 %val12 to i16
+  %trunc13 = trunc i64 %val13 to i16
+  %trunc14 = trunc i64 %val14 to i16
+  %trunc15 = trunc i64 %val15 to i16
+
+  %ext0 = sext i16 %trunc0 to i64
+  %ext1 = sext i16 %trunc1 to i64
+  %ext2 = sext i16 %trunc2 to i64
+  %ext3 = sext i16 %trunc3 to i64
+  %ext4 = sext i16 %trunc4 to i64
+  %ext5 = sext i16 %trunc5 to i64
+  %ext6 = sext i16 %trunc6 to i64
+  %ext7 = sext i16 %trunc7 to i64
+  %ext8 = sext i16 %trunc8 to i64
+  %ext9 = sext i16 %trunc9 to i64
+  %ext10 = sext i16 %trunc10 to i64
+  %ext11 = sext i16 %trunc11 to i64
+  %ext12 = sext i16 %trunc12 to i64
+  %ext13 = sext i16 %trunc13 to i64
+  %ext14 = sext i16 %trunc14 to i64
+  %ext15 = sext i16 %trunc15 to i64
+
+  store volatile i64 %val0, i64 *%ptr
+  store volatile i64 %val1, i64 *%ptr
+  store volatile i64 %val2, i64 *%ptr
+  store volatile i64 %val3, i64 *%ptr
+  store volatile i64 %val4, i64 *%ptr
+  store volatile i64 %val5, i64 *%ptr
+  store volatile i64 %val6, i64 *%ptr
+  store volatile i64 %val7, i64 *%ptr
+  store volatile i64 %val8, i64 *%ptr
+  store volatile i64 %val9, i64 *%ptr
+  store volatile i64 %val10, i64 *%ptr
+  store volatile i64 %val11, i64 *%ptr
+  store volatile i64 %val12, i64 *%ptr
+  store volatile i64 %val13, i64 *%ptr
+  store volatile i64 %val14, i64 *%ptr
+  store volatile i64 %val15, i64 *%ptr
+
+  store volatile i64 %ext0, i64 *%ptr
+  store volatile i64 %ext1, i64 *%ptr
+  store volatile i64 %ext2, i64 *%ptr
+  store volatile i64 %ext3, i64 *%ptr
+  store volatile i64 %ext4, i64 *%ptr
+  store volatile i64 %ext5, i64 *%ptr
+  store volatile i64 %ext6, i64 *%ptr
+  store volatile i64 %ext7, i64 *%ptr
+  store volatile i64 %ext8, i64 *%ptr
+  store volatile i64 %ext9, i64 *%ptr
+  store volatile i64 %ext10, i64 *%ptr
+  store volatile i64 %ext11, i64 *%ptr
+  store volatile i64 %ext12, i64 *%ptr
+  store volatile i64 %ext13, i64 *%ptr
+  store volatile i64 %ext14, i64 *%ptr
+  store volatile i64 %ext15, i64 *%ptr
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/int-conv-08.ll b/test/CodeGen/SystemZ/int-conv-08.ll
index 3d7f966..6b6cb67 100644
--- a/test/CodeGen/SystemZ/int-conv-08.ll
+++ b/test/CodeGen/SystemZ/int-conv-08.ll
@@ -4,9 +4,9 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llghr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %half = trunc i32 %a to i16
   %ext = zext i16 %half to i64
   ret i64 %ext
@@ -14,9 +14,9 @@ define i64 @f1(i32 %a) {
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llghr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %half = trunc i64 %a to i16
   %ext = zext i16 %half to i64
   ret i64 %ext
@@ -24,16 +24,16 @@ define i64 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llghr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %ext = and i64 %a, 65535
   ret i64 %ext
 }
 
 ; Check LLGH with no displacement.
 define i64 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgh %r2, 0(%r2)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -43,7 +43,7 @@ define i64 @f4(i16 *%src) {
 
 ; Check the high end of the LLGH range.
 define i64 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llgh %r2, 524286(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -55,7 +55,7 @@ define i64 @f5(i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llgh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i64 @f6(i16 *%src) {
 
 ; Check the high end of the negative LLGH range.
 define i64 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llgh %r2, -2(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -78,7 +78,7 @@ define i64 @f7(i16 *%src) {
 
 ; Check the low end of the LLGH range.
 define i64 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llgh %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -90,7 +90,7 @@ define i64 @f8(i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f9(i16 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524290
 ; CHECK: llgh %r2, 0(%r2)
 ; CHECK: br %r14
@@ -102,7 +102,7 @@ define i64 @f9(i16 *%src) {
 
 ; Check that LLGH allows an index
 define i64 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llgh %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -112,3 +112,97 @@ define i64 @f10(i64 %src, i64 %index) {
   %ext = zext i16 %half to i64
   ret i64 %ext
 }
+
+; Test a case where we spill the source of at least one LLGHR.  We want
+; to use LLGH if possible.
+define void @f11(i64 *%ptr) {
+; CHECK-LABEL: f11:
+; CHECK: llgh {{%r[0-9]+}}, 166(%r15)
+; CHECK: br %r14
+  %val0 = load volatile i64 *%ptr
+  %val1 = load volatile i64 *%ptr
+  %val2 = load volatile i64 *%ptr
+  %val3 = load volatile i64 *%ptr
+  %val4 = load volatile i64 *%ptr
+  %val5 = load volatile i64 *%ptr
+  %val6 = load volatile i64 *%ptr
+  %val7 = load volatile i64 *%ptr
+  %val8 = load volatile i64 *%ptr
+  %val9 = load volatile i64 *%ptr
+  %val10 = load volatile i64 *%ptr
+  %val11 = load volatile i64 *%ptr
+  %val12 = load volatile i64 *%ptr
+  %val13 = load volatile i64 *%ptr
+  %val14 = load volatile i64 *%ptr
+  %val15 = load volatile i64 *%ptr
+
+  %trunc0 = trunc i64 %val0 to i16
+  %trunc1 = trunc i64 %val1 to i16
+  %trunc2 = trunc i64 %val2 to i16
+  %trunc3 = trunc i64 %val3 to i16
+  %trunc4 = trunc i64 %val4 to i16
+  %trunc5 = trunc i64 %val5 to i16
+  %trunc6 = trunc i64 %val6 to i16
+  %trunc7 = trunc i64 %val7 to i16
+  %trunc8 = trunc i64 %val8 to i16
+  %trunc9 = trunc i64 %val9 to i16
+  %trunc10 = trunc i64 %val10 to i16
+  %trunc11 = trunc i64 %val11 to i16
+  %trunc12 = trunc i64 %val12 to i16
+  %trunc13 = trunc i64 %val13 to i16
+  %trunc14 = trunc i64 %val14 to i16
+  %trunc15 = trunc i64 %val15 to i16
+
+  %ext0 = zext i16 %trunc0 to i64
+  %ext1 = zext i16 %trunc1 to i64
+  %ext2 = zext i16 %trunc2 to i64
+  %ext3 = zext i16 %trunc3 to i64
+  %ext4 = zext i16 %trunc4 to i64
+  %ext5 = zext i16 %trunc5 to i64
+  %ext6 = zext i16 %trunc6 to i64
+  %ext7 = zext i16 %trunc7 to i64
+  %ext8 = zext i16 %trunc8 to i64
+  %ext9 = zext i16 %trunc9 to i64
+  %ext10 = zext i16 %trunc10 to i64
+  %ext11 = zext i16 %trunc11 to i64
+  %ext12 = zext i16 %trunc12 to i64
+  %ext13 = zext i16 %trunc13 to i64
+  %ext14 = zext i16 %trunc14 to i64
+  %ext15 = zext i16 %trunc15 to i64
+
+  store volatile i64 %val0, i64 *%ptr
+  store volatile i64 %val1, i64 *%ptr
+  store volatile i64 %val2, i64 *%ptr
+  store volatile i64 %val3, i64 *%ptr
+  store volatile i64 %val4, i64 *%ptr
+  store volatile i64 %val5, i64 *%ptr
+  store volatile i64 %val6, i64 *%ptr
+  store volatile i64 %val7, i64 *%ptr
+  store volatile i64 %val8, i64 *%ptr
+  store volatile i64 %val9, i64 *%ptr
+  store volatile i64 %val10, i64 *%ptr
+  store volatile i64 %val11, i64 *%ptr
+  store volatile i64 %val12, i64 *%ptr
+  store volatile i64 %val13, i64 *%ptr
+  store volatile i64 %val14, i64 *%ptr
+  store volatile i64 %val15, i64 *%ptr
+
+  store volatile i64 %ext0, i64 *%ptr
+  store volatile i64 %ext1, i64 *%ptr
+  store volatile i64 %ext2, i64 *%ptr
+  store volatile i64 %ext3, i64 *%ptr
+  store volatile i64 %ext4, i64 *%ptr
+  store volatile i64 %ext5, i64 *%ptr
+  store volatile i64 %ext6, i64 *%ptr
+  store volatile i64 %ext7, i64 *%ptr
+  store volatile i64 %ext8, i64 *%ptr
+  store volatile i64 %ext9, i64 *%ptr
+  store volatile i64 %ext10, i64 *%ptr
+  store volatile i64 %ext11, i64 *%ptr
+  store volatile i64 %ext12, i64 *%ptr
+  store volatile i64 %ext13, i64 *%ptr
+  store volatile i64 %ext14, i64 *%ptr
+  store volatile i64 %ext15, i64 *%ptr
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/int-conv-09.ll b/test/CodeGen/SystemZ/int-conv-09.ll
index 6e93886..db4c333 100644
--- a/test/CodeGen/SystemZ/int-conv-09.ll
+++ b/test/CodeGen/SystemZ/int-conv-09.ll
@@ -4,18 +4,18 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lgfr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %ext = sext i32 %a to i64
   ret i64 %ext
 }
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lgfr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %word = trunc i64 %a to i32
   %ext = sext i32 %word to i64
   ret i64 %ext
@@ -23,7 +23,7 @@ define i64 @f2(i64 %a) {
 
 ; Check LGF with no displacement.
 define i64 @f3(i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgf %r2, 0(%r2)
 ; CHECK: br %r14
   %word = load i32 *%src
@@ -33,7 +33,7 @@ define i64 @f3(i32 *%src) {
 
 ; Check the high end of the LGF range.
 define i64 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgf %r2, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -45,7 +45,7 @@ define i64 @f4(i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lgf %r2, 0(%r2)
 ; CHECK: br %r14
@@ -57,7 +57,7 @@ define i64 @f5(i32 *%src) {
 
 ; Check the high end of the negative LGF range.
 define i64 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgf %r2, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -68,7 +68,7 @@ define i64 @f6(i32 *%src) {
 
 ; Check the low end of the LGF range.
 define i64 @f7(i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgf %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -80,7 +80,7 @@ define i64 @f7(i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524292
 ; CHECK: lgf %r2, 0(%r2)
 ; CHECK: br %r14
@@ -92,7 +92,7 @@ define i64 @f8(i32 *%src) {
 
 ; Check that LGF allows an index.
 define i64 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lgf %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -102,3 +102,80 @@ define i64 @f9(i64 %src, i64 %index) {
   %ext = sext i32 %word to i64
   ret i64 %ext
 }
+
+; Test a case where we spill the source of at least one LGFR.  We want
+; to use LGF if possible.
+define void @f10(i64 *%ptr1, i32 *%ptr2) {
+; CHECK-LABEL: f10:
+; CHECK: lgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %val0 = load volatile i32 *%ptr2
+  %val1 = load volatile i32 *%ptr2
+  %val2 = load volatile i32 *%ptr2
+  %val3 = load volatile i32 *%ptr2
+  %val4 = load volatile i32 *%ptr2
+  %val5 = load volatile i32 *%ptr2
+  %val6 = load volatile i32 *%ptr2
+  %val7 = load volatile i32 *%ptr2
+  %val8 = load volatile i32 *%ptr2
+  %val9 = load volatile i32 *%ptr2
+  %val10 = load volatile i32 *%ptr2
+  %val11 = load volatile i32 *%ptr2
+  %val12 = load volatile i32 *%ptr2
+  %val13 = load volatile i32 *%ptr2
+  %val14 = load volatile i32 *%ptr2
+  %val15 = load volatile i32 *%ptr2
+
+  %ext0 = sext i32 %val0 to i64
+  %ext1 = sext i32 %val1 to i64
+  %ext2 = sext i32 %val2 to i64
+  %ext3 = sext i32 %val3 to i64
+  %ext4 = sext i32 %val4 to i64
+  %ext5 = sext i32 %val5 to i64
+  %ext6 = sext i32 %val6 to i64
+  %ext7 = sext i32 %val7 to i64
+  %ext8 = sext i32 %val8 to i64
+  %ext9 = sext i32 %val9 to i64
+  %ext10 = sext i32 %val10 to i64
+  %ext11 = sext i32 %val11 to i64
+  %ext12 = sext i32 %val12 to i64
+  %ext13 = sext i32 %val13 to i64
+  %ext14 = sext i32 %val14 to i64
+  %ext15 = sext i32 %val15 to i64
+
+  store volatile i32 %val0, i32 *%ptr2
+  store volatile i32 %val1, i32 *%ptr2
+  store volatile i32 %val2, i32 *%ptr2
+  store volatile i32 %val3, i32 *%ptr2
+  store volatile i32 %val4, i32 *%ptr2
+  store volatile i32 %val5, i32 *%ptr2
+  store volatile i32 %val6, i32 *%ptr2
+  store volatile i32 %val7, i32 *%ptr2
+  store volatile i32 %val8, i32 *%ptr2
+  store volatile i32 %val9, i32 *%ptr2
+  store volatile i32 %val10, i32 *%ptr2
+  store volatile i32 %val11, i32 *%ptr2
+  store volatile i32 %val12, i32 *%ptr2
+  store volatile i32 %val13, i32 *%ptr2
+  store volatile i32 %val14, i32 *%ptr2
+  store volatile i32 %val15, i32 *%ptr2
+
+  store volatile i64 %ext0, i64 *%ptr1
+  store volatile i64 %ext1, i64 *%ptr1
+  store volatile i64 %ext2, i64 *%ptr1
+  store volatile i64 %ext3, i64 *%ptr1
+  store volatile i64 %ext4, i64 *%ptr1
+  store volatile i64 %ext5, i64 *%ptr1
+  store volatile i64 %ext6, i64 *%ptr1
+  store volatile i64 %ext7, i64 *%ptr1
+  store volatile i64 %ext8, i64 *%ptr1
+  store volatile i64 %ext9, i64 *%ptr1
+  store volatile i64 %ext10, i64 *%ptr1
+  store volatile i64 %ext11, i64 *%ptr1
+  store volatile i64 %ext12, i64 *%ptr1
+  store volatile i64 %ext13, i64 *%ptr1
+  store volatile i64 %ext14, i64 *%ptr1
+  store volatile i64 %ext15, i64 *%ptr1
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/int-conv-10.ll b/test/CodeGen/SystemZ/int-conv-10.ll
index 918bc1d..f2f71d9 100644
--- a/test/CodeGen/SystemZ/int-conv-10.ll
+++ b/test/CodeGen/SystemZ/int-conv-10.ll
@@ -4,18 +4,18 @@
 
 ; Test register extension, starting with an i32.
 define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: llgfr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %ext = zext i32 %a to i64
   ret i64 %ext
 }
 
 ; ...and again with an i64.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llgfr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %word = trunc i64 %a to i32
   %ext = zext i32 %word to i64
   ret i64 %ext
@@ -23,16 +23,16 @@ define i64 @f2(i64 %a) {
 
 ; Check ANDs that are equivalent to zero extension.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: llgfr %r2, %r2
-; CHECk: br %r14
+; CHECK: br %r14
   %ext = and i64 %a, 4294967295
   ret i64 %ext
 }
 
 ; Check LLGF with no displacement.
 define i64 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgf %r2, 0(%r2)
 ; CHECK: br %r14
   %word = load i32 *%src
@@ -42,7 +42,7 @@ define i64 @f4(i32 *%src) {
 
 ; Check the high end of the LLGF range.
 define i64 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: llgf %r2, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -54,7 +54,7 @@ define i64 @f5(i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: llgf %r2, 0(%r2)
 ; CHECK: br %r14
@@ -66,7 +66,7 @@ define i64 @f6(i32 *%src) {
 
 ; Check the high end of the negative LLGF range.
 define i64 @f7(i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: llgf %r2, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -77,7 +77,7 @@ define i64 @f7(i32 *%src) {
 
 ; Check the low end of the LLGF range.
 define i64 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: llgf %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -89,7 +89,7 @@ define i64 @f8(i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f9(i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524292
 ; CHECK: llgf %r2, 0(%r2)
 ; CHECK: br %r14
@@ -101,7 +101,7 @@ define i64 @f9(i32 *%src) {
 
 ; Check that LLGF allows an index.
 define i64 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: llgf %r2, 524287(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -111,3 +111,80 @@ define i64 @f10(i64 %src, i64 %index) {
   %ext = zext i32 %word to i64
   ret i64 %ext
 }
+
+; Test a case where we spill the source of at least one LLGFR.  We want
+; to use LLGF if possible.
+define void @f11(i64 *%ptr1, i32 *%ptr2) {
+; CHECK-LABEL: f11:
+; CHECK: llgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %val0 = load volatile i32 *%ptr2
+  %val1 = load volatile i32 *%ptr2
+  %val2 = load volatile i32 *%ptr2
+  %val3 = load volatile i32 *%ptr2
+  %val4 = load volatile i32 *%ptr2
+  %val5 = load volatile i32 *%ptr2
+  %val6 = load volatile i32 *%ptr2
+  %val7 = load volatile i32 *%ptr2
+  %val8 = load volatile i32 *%ptr2
+  %val9 = load volatile i32 *%ptr2
+  %val10 = load volatile i32 *%ptr2
+  %val11 = load volatile i32 *%ptr2
+  %val12 = load volatile i32 *%ptr2
+  %val13 = load volatile i32 *%ptr2
+  %val14 = load volatile i32 *%ptr2
+  %val15 = load volatile i32 *%ptr2
+
+  %ext0 = zext i32 %val0 to i64
+  %ext1 = zext i32 %val1 to i64
+  %ext2 = zext i32 %val2 to i64
+  %ext3 = zext i32 %val3 to i64
+  %ext4 = zext i32 %val4 to i64
+  %ext5 = zext i32 %val5 to i64
+  %ext6 = zext i32 %val6 to i64
+  %ext7 = zext i32 %val7 to i64
+  %ext8 = zext i32 %val8 to i64
+  %ext9 = zext i32 %val9 to i64
+  %ext10 = zext i32 %val10 to i64
+  %ext11 = zext i32 %val11 to i64
+  %ext12 = zext i32 %val12 to i64
+  %ext13 = zext i32 %val13 to i64
+  %ext14 = zext i32 %val14 to i64
+  %ext15 = zext i32 %val15 to i64
+
+  store volatile i32 %val0, i32 *%ptr2
+  store volatile i32 %val1, i32 *%ptr2
+  store volatile i32 %val2, i32 *%ptr2
+  store volatile i32 %val3, i32 *%ptr2
+  store volatile i32 %val4, i32 *%ptr2
+  store volatile i32 %val5, i32 *%ptr2
+  store volatile i32 %val6, i32 *%ptr2
+  store volatile i32 %val7, i32 *%ptr2
+  store volatile i32 %val8, i32 *%ptr2
+  store volatile i32 %val9, i32 *%ptr2
+  store volatile i32 %val10, i32 *%ptr2
+  store volatile i32 %val11, i32 *%ptr2
+  store volatile i32 %val12, i32 *%ptr2
+  store volatile i32 %val13, i32 *%ptr2
+  store volatile i32 %val14, i32 *%ptr2
+  store volatile i32 %val15, i32 *%ptr2
+
+  store volatile i64 %ext0, i64 *%ptr1
+  store volatile i64 %ext1, i64 *%ptr1
+  store volatile i64 %ext2, i64 *%ptr1
+  store volatile i64 %ext3, i64 *%ptr1
+  store volatile i64 %ext4, i64 *%ptr1
+  store volatile i64 %ext5, i64 *%ptr1
+  store volatile i64 %ext6, i64 *%ptr1
+  store volatile i64 %ext7, i64 *%ptr1
+  store volatile i64 %ext8, i64 *%ptr1
+  store volatile i64 %ext9, i64 *%ptr1
+  store volatile i64 %ext10, i64 *%ptr1
+  store volatile i64 %ext11, i64 *%ptr1
+  store volatile i64 %ext12, i64 *%ptr1
+  store volatile i64 %ext13, i64 *%ptr1
+  store volatile i64 %ext14, i64 *%ptr1
+  store volatile i64 %ext15, i64 *%ptr1
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/int-div-01.ll b/test/CodeGen/SystemZ/int-div-01.ll
index 492ece9..2c21186 100644
--- a/test/CodeGen/SystemZ/int-div-01.ll
+++ b/test/CodeGen/SystemZ/int-div-01.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i32 @foo()
+
 ; Test register division.  The result is in the second of the two registers.
 define void @f1(i32 *%dest, i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lgfr %r1, %r3
 ; CHECK: dsgfr %r0, %r4
 ; CHECK: st %r1, 0(%r2)
@@ -16,7 +18,7 @@ define void @f1(i32 *%dest, i32 %a, i32 %b) {
 
 ; Test register remainder.  The result is in the first of the two registers.
 define void @f2(i32 *%dest, i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lgfr %r1, %r3
 ; CHECK: dsgfr %r0, %r4
 ; CHECK: st %r0, 0(%r2)
@@ -28,7 +30,7 @@ define void @f2(i32 *%dest, i32 %a, i32 %b) {
 
 ; Test that division and remainder use a single instruction.
 define i32 @f3(i32 %dummy, i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r2
 ; CHECK: lgfr %r3, %r3
 ; CHECK-NOT: %r2
@@ -45,7 +47,7 @@ define i32 @f3(i32 %dummy, i32 %a, i32 %b) {
 ; Check that the sign extension of the dividend is elided when the argument
 ; is already sign-extended.
 define i32 @f4(i32 %dummy, i32 signext %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgfr %r2, %r4
 ; CHECK-NOT: dsgfr
@@ -59,7 +61,7 @@ define i32 @f4(i32 %dummy, i32 signext %a, i32 %b) {
 
 ; Test that memory dividends are loaded using sign extension (LGF).
 define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r2
 ; CHECK: lgf %r3, 0(%r3)
 ; CHECK-NOT: %r2
@@ -76,7 +78,7 @@ define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
 
 ; Test memory division with no displacement.
 define void @f6(i32 *%dest, i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgfr %r1, %r3
 ; CHECK: dsgf %r0, 0(%r4)
 ; CHECK: st %r1, 0(%r2)
@@ -89,7 +91,7 @@ define void @f6(i32 *%dest, i32 %a, i32 *%src) {
 
 ; Test memory remainder with no displacement.
 define void @f7(i32 *%dest, i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgfr %r1, %r3
 ; CHECK: dsgf %r0, 0(%r4)
 ; CHECK: st %r0, 0(%r2)
@@ -102,7 +104,7 @@ define void @f7(i32 *%dest, i32 %a, i32 *%src) {
 
 ; Test both memory division and memory remainder.
 define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: %r2
 ; CHECK: lgfr %r3, %r3
 ; CHECK-NOT: %r2
@@ -119,7 +121,7 @@ define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the high end of the DSGF range.
 define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: dsgf %r2, 524284(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -131,7 +133,7 @@ define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r4, 524288
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
@@ -143,7 +145,7 @@ define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned DSGF range.
 define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: dsgf %r2, -4(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -154,7 +156,7 @@ define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the low end of the DSGF range.
 define i32 @f12(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: dsgf %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -166,7 +168,7 @@ define i32 @f12(i32 %dummy, i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f13(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agfi %r4, -524292
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
@@ -178,7 +180,7 @@ define i32 @f13(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check that DSGF allows an index.
 define i32 @f14(i32 %dummy, i32 %a, i64 %src, i64 %index) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: dsgf %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -188,3 +190,62 @@ define i32 @f14(i32 %dummy, i32 %a, i64 %src, i64 %index) {
   %rem = srem i32 %a, %b
   ret i32 %rem
 }
+
+; Make sure that we still use DSGFR rather than DSGR in cases where
+; a load and division cannot be combined.
+define void @f15(i32 *%dest, i32 *%src) {
+; CHECK-LABEL: f15:
+; CHECK: l [[B:%r[0-9]+]], 0(%r3)
+; CHECK: brasl %r14, foo@PLT
+; CHECK: lgfr %r1, %r2
+; CHECK: dsgfr %r0, [[B]]
+; CHECK: br %r14
+  %b = load i32 *%src
+  %a = call i32 @foo()
+  %div = sdiv i32 %a, %b
+  store i32 %div, i32 *%dest
+  ret void
+}
+
+; Check that divisions of spilled values can use DSGF rather than DSGFR.
+define i32 @f16(i32 *%ptr0) {
+; CHECK-LABEL: f16:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: dsgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32 *%ptr0, i64 18
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+  %val9 = load i32 *%ptr9
+
+  %ret = call i32 @foo()
+
+  %div0 = sdiv i32 %ret, %val0
+  %div1 = sdiv i32 %div0, %val1
+  %div2 = sdiv i32 %div1, %val2
+  %div3 = sdiv i32 %div2, %val3
+  %div4 = sdiv i32 %div3, %val4
+  %div5 = sdiv i32 %div4, %val5
+  %div6 = sdiv i32 %div5, %val6
+  %div7 = sdiv i32 %div6, %val7
+  %div8 = sdiv i32 %div7, %val8
+  %div9 = sdiv i32 %div8, %val9
+
+  ret i32 %div9
+}
diff --git a/test/CodeGen/SystemZ/int-div-02.ll b/test/CodeGen/SystemZ/int-div-02.ll
index 7954384..f3287a5 100644
--- a/test/CodeGen/SystemZ/int-div-02.ll
+++ b/test/CodeGen/SystemZ/int-div-02.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i32 @foo()
+
 ; Test register division.  The result is in the second of the two registers.
 define void @f1(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -18,7 +20,7 @@ define void @f1(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
 
 ; Test register remainder.  The result is in the first of the two registers.
 define void @f2(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -32,7 +34,7 @@ define void @f2(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
 
 ; Test that division and remainder use a single instruction.
 define i32 @f3(i32 %dummy1, i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -48,7 +50,7 @@ define i32 @f3(i32 %dummy1, i32 %a, i32 %b) {
 
 ; Test memory division with no displacement.
 define void @f4(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -63,7 +65,7 @@ define void @f4(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
 
 ; Test memory remainder with no displacement.
 define void @f5(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -78,7 +80,7 @@ define void @f5(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
 
 ; Test both memory division and memory remainder.
 define i32 @f6(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lhi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -95,7 +97,7 @@ define i32 @f6(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the high end of the DL range.
 define i32 @f7(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: dl %r2, 524284(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -107,7 +109,7 @@ define i32 @f7(i32 %dummy, i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r4, 524288
 ; CHECK: dl %r2, 0(%r4)
 ; CHECK: br %r14
@@ -119,7 +121,7 @@ define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned DL range.
 define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: dl %r2, -4(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -130,7 +132,7 @@ define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check the low end of the DL range.
 define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: dl %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -142,7 +144,7 @@ define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r4, -524292
 ; CHECK: dl %r2, 0(%r4)
 ; CHECK: br %r14
@@ -154,7 +156,7 @@ define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
 
 ; Check that DL allows an index.
 define i32 @f12(i32 %dummy, i32 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: dl %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -164,3 +166,46 @@ define i32 @f12(i32 %dummy, i32 %a, i64 %src, i64 %index) {
   %rem = urem i32 %a, %b
   ret i32 %rem
 }
+
+; Check that divisions of spilled values can use DL rather than DLR.
+define i32 @f13(i32 *%ptr0) {
+; CHECK-LABEL: f13:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: dl {{%r[0-9]+}}, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32 *%ptr0, i64 18
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+  %val9 = load i32 *%ptr9
+
+  %ret = call i32 @foo()
+
+  %div0 = udiv i32 %ret, %val0
+  %div1 = udiv i32 %div0, %val1
+  %div2 = udiv i32 %div1, %val2
+  %div3 = udiv i32 %div2, %val3
+  %div4 = udiv i32 %div3, %val4
+  %div5 = udiv i32 %div4, %val5
+  %div6 = udiv i32 %div5, %val6
+  %div7 = udiv i32 %div6, %val7
+  %div8 = udiv i32 %div7, %val8
+  %div9 = udiv i32 %div8, %val9
+
+  ret i32 %div9
+}
diff --git a/test/CodeGen/SystemZ/int-div-03.ll b/test/CodeGen/SystemZ/int-div-03.ll
index b950f2b..7c04090 100644
--- a/test/CodeGen/SystemZ/int-div-03.ll
+++ b/test/CodeGen/SystemZ/int-div-03.ll
@@ -3,9 +3,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i64 @foo()
+
 ; Test register division.  The result is in the second of the two registers.
 define void @f1(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgfr %r2, %r4
 ; CHECK: stg %r3, 0(%r5)
@@ -18,7 +20,7 @@ define void @f1(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
 
 ; Test register remainder.  The result is in the first of the two registers.
 define void @f2(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgfr %r2, %r4
 ; CHECK: stg %r2, 0(%r5)
@@ -31,7 +33,7 @@ define void @f2(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
 
 ; Test that division and remainder use a single instruction.
 define i64 @f3(i64 %dummy, i64 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgfr %r2, %r4
 ; CHECK: ogr %r2, %r3
@@ -46,7 +48,7 @@ define i64 @f3(i64 %dummy, i64 %a, i32 %b) {
 ; Test register division when the dividend is zero rather than sign extended.
 ; We can't use dsgfr here
 define void @f4(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: dsgfr
 ; CHECK: br %r14
   %bext = zext i32 %b to i64
@@ -57,7 +59,7 @@ define void @f4(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
 
 ; ...likewise remainder.
 define void @f5(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: dsgfr
 ; CHECK: br %r14
   %bext = zext i32 %b to i64
@@ -68,7 +70,7 @@ define void @f5(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
 
 ; Test memory division with no displacement.
 define void @f6(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: stg %r3, 0(%r5)
@@ -82,7 +84,7 @@ define void @f6(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
 
 ; Test memory remainder with no displacement.
 define void @f7(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: stg %r2, 0(%r5)
@@ -96,7 +98,7 @@ define void @f7(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
 
 ; Test both memory division and memory remainder.
 define i64 @f8(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK-NOT: {{dsgf|dsgfr}}
@@ -112,7 +114,7 @@ define i64 @f8(i64 %dummy, i64 %a, i32 *%src) {
 
 ; Check the high end of the DSGF range.
 define i64 @f9(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: dsgf %r2, 524284(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -125,7 +127,7 @@ define i64 @f9(i64 %dummy, i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f10(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r4, 524288
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
@@ -138,7 +140,7 @@ define i64 @f10(i64 %dummy, i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned DSGF range.
 define i64 @f11(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: dsgf %r2, -4(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -150,7 +152,7 @@ define i64 @f11(i64 %dummy, i64 %a, i32 *%src) {
 
 ; Check the low end of the DSGF range.
 define i64 @f12(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: dsgf %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -163,7 +165,7 @@ define i64 @f12(i64 %dummy, i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f13(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agfi %r4, -524292
 ; CHECK: dsgf %r2, 0(%r4)
 ; CHECK: br %r14
@@ -176,7 +178,7 @@ define i64 @f13(i64 %dummy, i64 %a, i32 *%src) {
 
 ; Check that DSGF allows an index.
 define i64 @f14(i64 %dummy, i64 %a, i64 %src, i64 %index) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: dsgf %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -187,3 +189,20 @@ define i64 @f14(i64 %dummy, i64 %a, i64 %src, i64 %index) {
   %rem = srem i64 %a, %bext
   ret i64 %rem
 }
+
+; Make sure that we still use DSGFR rather than DSGR in cases where
+; a load and division cannot be combined.
+define void @f15(i64 *%dest, i32 *%src) {
+; CHECK-LABEL: f15:
+; CHECK: l [[B:%r[0-9]+]], 0(%r3)
+; CHECK: brasl %r14, foo@PLT
+; CHECK: lgr %r1, %r2
+; CHECK: dsgfr %r0, [[B]]
+; CHECK: br %r14
+  %b = load i32 *%src
+  %a = call i64 @foo()
+  %ext = sext i32 %b to i64
+  %div = sdiv i64 %a, %ext
+  store i64 %div, i64 *%dest
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/int-div-04.ll b/test/CodeGen/SystemZ/int-div-04.ll
index 3f72be9..87f1e10 100644
--- a/test/CodeGen/SystemZ/int-div-04.ll
+++ b/test/CodeGen/SystemZ/int-div-04.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i64 @foo()
+
 ; Testg register division.  The result is in the second of the two registers.
 define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgr %r2, %r4
 ; CHECK: stg %r3, 0(%r5)
@@ -16,7 +18,7 @@ define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
 
 ; Testg register remainder.  The result is in the first of the two registers.
 define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgr %r2, %r4
 ; CHECK: stg %r2, 0(%r5)
@@ -28,7 +30,7 @@ define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
 
 ; Testg that division and remainder use a single instruction.
 define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsgr %r2, %r4
 ; CHECK-NOT: dsgr
@@ -42,7 +44,7 @@ define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
 
 ; Testg memory division with no displacement.
 define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: stg %r3, 0(%r5)
@@ -55,7 +57,7 @@ define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 
 ; Testg memory remainder with no displacement.
 define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: stg %r2, 0(%r5)
@@ -68,7 +70,7 @@ define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 
 ; Testg both memory division and memory remainder.
 define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK-NOT: {{dsg|dsgr}}
@@ -83,7 +85,7 @@ define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the DSG range.
 define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: dsg %r2, 524280(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -95,7 +97,7 @@ define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r4, 524288
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -107,7 +109,7 @@ define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned DSG range.
 define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: dsg %r2, -8(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -118,7 +120,7 @@ define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the low end of the DSG range.
 define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: dsg %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -130,7 +132,7 @@ define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r4, -524296
 ; CHECK: dsg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -142,7 +144,7 @@ define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check that DSG allows an index.
 define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: dsg %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -152,3 +154,49 @@ define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
   %rem = srem i64 %a, %b
   ret i64 %rem
 }
+
+; Check that divisions of spilled values can use DSG rather than DSGR.
+define i64 @f13(i64 *%ptr0) {
+; CHECK-LABEL: f13:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: dsg {{%r[0-9]+}}, 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64 *%ptr0, i64 18
+  %ptr10 = getelementptr i64 *%ptr0, i64 20
+
+  %val0 = load i64 *%ptr0
+  %val1 = load i64 *%ptr1
+  %val2 = load i64 *%ptr2
+  %val3 = load i64 *%ptr3
+  %val4 = load i64 *%ptr4
+  %val5 = load i64 *%ptr5
+  %val6 = load i64 *%ptr6
+  %val7 = load i64 *%ptr7
+  %val8 = load i64 *%ptr8
+  %val9 = load i64 *%ptr9
+  %val10 = load i64 *%ptr10
+
+  %ret = call i64 @foo()
+
+  %div0 = sdiv i64 %ret, %val0
+  %div1 = sdiv i64 %div0, %val1
+  %div2 = sdiv i64 %div1, %val2
+  %div3 = sdiv i64 %div2, %val3
+  %div4 = sdiv i64 %div3, %val4
+  %div5 = sdiv i64 %div4, %val5
+  %div6 = sdiv i64 %div5, %val6
+  %div7 = sdiv i64 %div6, %val7
+  %div8 = sdiv i64 %div7, %val8
+  %div9 = sdiv i64 %div8, %val9
+  %div10 = sdiv i64 %div9, %val10
+
+  ret i64 %div10
+}
diff --git a/test/CodeGen/SystemZ/int-div-05.ll b/test/CodeGen/SystemZ/int-div-05.ll
index 04f622b..8179830 100644
--- a/test/CodeGen/SystemZ/int-div-05.ll
+++ b/test/CodeGen/SystemZ/int-div-05.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i64 @foo()
+
 ; Testg register division.  The result is in the second of the two registers.
 define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -18,7 +20,7 @@ define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
 
 ; Testg register remainder.  The result is in the first of the two registers.
 define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -32,7 +34,7 @@ define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
 
 ; Testg that division and remainder use a single instruction.
 define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -48,7 +50,7 @@ define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
 
 ; Testg memory division with no displacement.
 define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -63,7 +65,7 @@ define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 
 ; Testg memory remainder with no displacement.
 define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -78,7 +80,7 @@ define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
 
 ; Testg both memory division and memory remainder.
 define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: %r3
 ; CHECK: {{llill|lghi}} %r2, 0
 ; CHECK-NOT: %r3
@@ -95,7 +97,7 @@ define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the DLG range.
 define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: dlg %r2, 524280(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -107,7 +109,7 @@ define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r4, 524288
 ; CHECK: dlg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -119,7 +121,7 @@ define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned DLG range.
 define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: dlg %r2, -8(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -130,7 +132,7 @@ define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the low end of the DLG range.
 define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: dlg %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -142,7 +144,7 @@ define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r4, -524296
 ; CHECK: dlg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -154,7 +156,7 @@ define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check that DLG allows an index.
 define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: dlg %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -164,3 +166,49 @@ define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
   %rem = urem i64 %a, %b
   ret i64 %rem
 }
+
+; Check that divisions of spilled values can use DLG rather than DLGR.
+define i64 @f13(i64 *%ptr0) {
+; CHECK-LABEL: f13:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: dlg {{%r[0-9]+}}, 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64 *%ptr0, i64 18
+  %ptr10 = getelementptr i64 *%ptr0, i64 20
+
+  %val0 = load i64 *%ptr0
+  %val1 = load i64 *%ptr1
+  %val2 = load i64 *%ptr2
+  %val3 = load i64 *%ptr3
+  %val4 = load i64 *%ptr4
+  %val5 = load i64 *%ptr5
+  %val6 = load i64 *%ptr6
+  %val7 = load i64 *%ptr7
+  %val8 = load i64 *%ptr8
+  %val9 = load i64 *%ptr9
+  %val10 = load i64 *%ptr10
+
+  %ret = call i64 @foo()
+
+  %div0 = udiv i64 %ret, %val0
+  %div1 = udiv i64 %div0, %val1
+  %div2 = udiv i64 %div1, %val2
+  %div3 = udiv i64 %div2, %val3
+  %div4 = udiv i64 %div3, %val4
+  %div5 = udiv i64 %div4, %val5
+  %div6 = udiv i64 %div5, %val6
+  %div7 = udiv i64 %div6, %val7
+  %div8 = udiv i64 %div7, %val8
+  %div9 = udiv i64 %div8, %val9
+  %div10 = udiv i64 %div9, %val10
+
+  ret i64 %div10
+}
diff --git a/test/CodeGen/SystemZ/int-move-01.ll b/test/CodeGen/SystemZ/int-move-01.ll
index ae890ad..038e688 100644
--- a/test/CodeGen/SystemZ/int-move-01.ll
+++ b/test/CodeGen/SystemZ/int-move-01.ll
@@ -4,7 +4,7 @@
 
 ; Test 8-bit moves, which should get promoted to i32.
 define i8 @f1(i8 %a, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
   ret i8 %b
@@ -12,7 +12,7 @@ define i8 @f1(i8 %a, i8 %b) {
 
 ; Test 16-bit moves, which again should get promoted to i32.
 define i16 @f2(i16 %a, i16 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
   ret i16 %b
@@ -20,7 +20,7 @@ define i16 @f2(i16 %a, i16 %b) {
 
 ; Test 32-bit moves.
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lr %r2, %r3
 ; CHECK: br %r14
   ret i32 %b
@@ -28,7 +28,7 @@ define i32 @f3(i32 %a, i32 %b) {
 
 ; Test 64-bit moves.
 define i64 @f4(i64 %a, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgr %r2, %r3
 ; CHECK: br %r14
   ret i64 %b
diff --git a/test/CodeGen/SystemZ/int-move-02.ll b/test/CodeGen/SystemZ/int-move-02.ll
index 467e22d..5fc0843 100644
--- a/test/CodeGen/SystemZ/int-move-02.ll
+++ b/test/CodeGen/SystemZ/int-move-02.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the L range.
 define i32 @f1(i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: br %r14
   %val = load i32 *%src
@@ -13,7 +13,7 @@ define i32 @f1(i32 *%src) {
 
 ; Check the high end of the aligned L range.
 define i32 @f2(i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: l %r2, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -23,7 +23,7 @@ define i32 @f2(i32 *%src) {
 
 ; Check the next word up, which should use LY instead of L.
 define i32 @f3(i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ly %r2, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -33,7 +33,7 @@ define i32 @f3(i32 *%src) {
 
 ; Check the high end of the aligned LY range.
 define i32 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ly %r2, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -44,7 +44,7 @@ define i32 @f4(i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r2, 524288
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: br %r14
@@ -55,7 +55,7 @@ define i32 @f5(i32 *%src) {
 
 ; Check the high end of the negative aligned LY range.
 define i32 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ly %r2, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -65,7 +65,7 @@ define i32 @f6(i32 *%src) {
 
 ; Check the low end of the LY range.
 define i32 @f7(i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: ly %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -76,7 +76,7 @@ define i32 @f7(i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, -524292
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define i32 @f8(i32 *%src) {
 
 ; Check that L allows an index.
 define i32 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: l %r2, 4095({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -99,7 +99,7 @@ define i32 @f9(i64 %src, i64 %index) {
 
 ; Check that LY allows an index.
 define i32 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ly %r2, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/int-move-03.ll b/test/CodeGen/SystemZ/int-move-03.ll
index 97c70a2..2894512 100644
--- a/test/CodeGen/SystemZ/int-move-03.ll
+++ b/test/CodeGen/SystemZ/int-move-03.ll
@@ -4,7 +4,7 @@
 
 ; Check LG with no displacement.
 define i64 @f1(i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: br %r14
   %val = load i64 *%src
@@ -13,7 +13,7 @@ define i64 @f1(i64 *%src) {
 
 ; Check the high end of the aligned LG range.
 define i64 @f2(i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lg %r2, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -24,7 +24,7 @@ define i64 @f2(i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f3(i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define i64 @f3(i64 *%src) {
 
 ; Check the high end of the negative aligned LG range.
 define i64 @f4(i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lg %r2, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -45,7 +45,7 @@ define i64 @f4(i64 *%src) {
 
 ; Check the low end of the LG range.
 define i64 @f5(i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lg %r2, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -56,7 +56,7 @@ define i64 @f5(i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f6(i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524296
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define i64 @f6(i64 *%src) {
 
 ; Check that LG allows an index.
 define i64 @f7(i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lg %r2, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/int-move-04.ll b/test/CodeGen/SystemZ/int-move-04.ll
index 9736657..d97ed2f 100644
--- a/test/CodeGen/SystemZ/int-move-04.ll
+++ b/test/CodeGen/SystemZ/int-move-04.ll
@@ -4,7 +4,7 @@
 
 ; Test an i8 store, which should get converted into an i32 truncation.
 define void @f1(i8 *%dst, i8 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
   store i8 %val, i8 *%dst
@@ -13,7 +13,7 @@ define void @f1(i8 *%dst, i8 %val) {
 
 ; Test an i32 truncating store.
 define void @f2(i8 *%dst, i32 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
   %trunc = trunc i32 %val to i8
@@ -23,7 +23,7 @@ define void @f2(i8 *%dst, i32 %val) {
 
 ; Test an i64 truncating store.
 define void @f3(i8 *%dst, i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
   %trunc = trunc i64 %val to i8
@@ -33,7 +33,7 @@ define void @f3(i8 *%dst, i64 %val) {
 
 ; Check the high end of the STC range.
 define void @f4(i8 *%dst, i8 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stc %r3, 4095(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%dst, i64 4095
@@ -43,7 +43,7 @@ define void @f4(i8 *%dst, i8 %val) {
 
 ; Check the next byte up, which should use STCY instead of STC.
 define void @f5(i8 *%dst, i8 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: stcy %r3, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%dst, i64 4096
@@ -53,7 +53,7 @@ define void @f5(i8 *%dst, i8 %val) {
 
 ; Check the high end of the STCY range.
 define void @f6(i8 *%dst, i8 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: stcy %r3, 524287(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%dst, i64 524287
@@ -64,7 +64,7 @@ define void @f6(i8 *%dst, i8 %val) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f7(i8 *%dst, i8 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r2, 524288
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f7(i8 *%dst, i8 %val) {
 
 ; Check the high end of the negative STCY range.
 define void @f8(i8 *%dst, i8 %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: stcy %r3, -1(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%dst, i64 -1
@@ -85,7 +85,7 @@ define void @f8(i8 *%dst, i8 %val) {
 
 ; Check the low end of the STCY range.
 define void @f9(i8 *%dst, i8 %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: stcy %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%dst, i64 -524288
@@ -96,7 +96,7 @@ define void @f9(i8 *%dst, i8 %val) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f10(i8 *%dst, i8 %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524289
 ; CHECK: stc %r3, 0(%r2)
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define void @f10(i8 *%dst, i8 %val) {
 
 ; Check that STC allows an index.
 define void @f11(i64 %dst, i64 %index, i8 %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: stc %r4, 4095(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
@@ -119,7 +119,7 @@ define void @f11(i64 %dst, i64 %index, i8 %val) {
 
 ; Check that STCY allows an index.
 define void @f12(i64 %dst, i64 %index, i8 %val) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: stcy %r4, 4096(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
diff --git a/test/CodeGen/SystemZ/int-move-05.ll b/test/CodeGen/SystemZ/int-move-05.ll
index f61477e..c21b88a 100644
--- a/test/CodeGen/SystemZ/int-move-05.ll
+++ b/test/CodeGen/SystemZ/int-move-05.ll
@@ -4,7 +4,7 @@
 
 ; Test an i16 store, which should get converted into an i32 truncation.
 define void @f1(i16 *%dst, i16 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
   store i16 %val, i16 *%dst
@@ -13,7 +13,7 @@ define void @f1(i16 *%dst, i16 %val) {
 
 ; Test an i32 truncating store.
 define void @f2(i16 *%dst, i32 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
   %trunc = trunc i32 %val to i16
@@ -23,7 +23,7 @@ define void @f2(i16 *%dst, i32 %val) {
 
 ; Test an i64 truncating store.
 define void @f3(i16 *%dst, i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
   %trunc = trunc i64 %val to i16
@@ -33,7 +33,7 @@ define void @f3(i16 *%dst, i64 %val) {
 
 ; Check the high end of the STH range.
 define void @f4(i16 *%dst, i16 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sth %r3, 4094(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%dst, i64 2047
@@ -43,7 +43,7 @@ define void @f4(i16 *%dst, i16 %val) {
 
 ; Check the next halfword up, which should use STHY instead of STH.
 define void @f5(i16 *%dst, i16 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sthy %r3, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%dst, i64 2048
@@ -53,7 +53,7 @@ define void @f5(i16 *%dst, i16 %val) {
 
 ; Check the high end of the aligned STHY range.
 define void @f6(i16 *%dst, i16 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sthy %r3, 524286(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%dst, i64 262143
@@ -64,7 +64,7 @@ define void @f6(i16 *%dst, i16 %val) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f7(i16 *%dst, i16 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r2, 524288
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
@@ -75,7 +75,7 @@ define void @f7(i16 *%dst, i16 %val) {
 
 ; Check the high end of the negative aligned STHY range.
 define void @f8(i16 *%dst, i16 %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sthy %r3, -2(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%dst, i64 -1
@@ -85,7 +85,7 @@ define void @f8(i16 *%dst, i16 %val) {
 
 ; Check the low end of the STHY range.
 define void @f9(i16 *%dst, i16 %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: sthy %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%dst, i64 -262144
@@ -96,7 +96,7 @@ define void @f9(i16 *%dst, i16 %val) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f10(i16 *%dst, i16 %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: agfi %r2, -524290
 ; CHECK: sth %r3, 0(%r2)
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define void @f10(i16 *%dst, i16 %val) {
 
 ; Check that STH allows an index.
 define void @f11(i64 %dst, i64 %index, i16 %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sth %r4, 4094({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
@@ -119,7 +119,7 @@ define void @f11(i64 %dst, i64 %index, i16 %val) {
 
 ; Check that STHY allows an index.
 define void @f12(i64 %dst, i64 %index, i16 %val) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: sthy %r4, 4096({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
diff --git a/test/CodeGen/SystemZ/int-move-06.ll b/test/CodeGen/SystemZ/int-move-06.ll
index 5b35a32..b8c6f53 100644
--- a/test/CodeGen/SystemZ/int-move-06.ll
+++ b/test/CodeGen/SystemZ/int-move-06.ll
@@ -4,7 +4,7 @@
 
 ; Test an i32 store.
 define void @f1(i32 *%dst, i32 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: br %r14
   store i32 %val, i32 *%dst
@@ -20,7 +20,7 @@ define void @f2(i32 *%dst, i64 %val) {
 
 ; Check the high end of the aligned ST range.
 define void @f3(i32 *%dst, i32 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: st %r3, 4092(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 1023
@@ -30,7 +30,7 @@ define void @f3(i32 *%dst, i32 %val) {
 
 ; Check the next word up, which should use STY instead of ST.
 define void @f4(i32 *%dst, i32 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sty %r3, 4096(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 1024
@@ -40,7 +40,7 @@ define void @f4(i32 *%dst, i32 %val) {
 
 ; Check the high end of the aligned STY range.
 define void @f5(i32 *%dst, i32 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sty %r3, 524284(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 131071
@@ -51,7 +51,7 @@ define void @f5(i32 *%dst, i32 %val) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i32 *%dst, i32 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, 524288
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: br %r14
@@ -62,7 +62,7 @@ define void @f6(i32 *%dst, i32 %val) {
 
 ; Check the high end of the negative aligned STY range.
 define void @f7(i32 *%dst, i32 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sty %r3, -4(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 -1
@@ -72,7 +72,7 @@ define void @f7(i32 *%dst, i32 %val) {
 
 ; Check the low end of the STY range.
 define void @f8(i32 *%dst, i32 %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sty %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%dst, i64 -131072
@@ -83,7 +83,7 @@ define void @f8(i32 *%dst, i32 %val) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i32 *%dst, i32 %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r2, -524292
 ; CHECK: st %r3, 0(%r2)
 ; CHECK: br %r14
@@ -94,7 +94,7 @@ define void @f9(i32 *%dst, i32 %val) {
 
 ; Check that ST allows an index.
 define void @f10(i64 %dst, i64 %index, i32 %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: st %r4, 4095(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
@@ -106,7 +106,7 @@ define void @f10(i64 %dst, i64 %index, i32 %val) {
 
 ; Check that STY allows an index.
 define void @f11(i64 %dst, i64 %index, i32 %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sty %r4, 4096(%r3,%r2)
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
diff --git a/test/CodeGen/SystemZ/int-move-07.ll b/test/CodeGen/SystemZ/int-move-07.ll
index ab21ab0..5cac1e5 100644
--- a/test/CodeGen/SystemZ/int-move-07.ll
+++ b/test/CodeGen/SystemZ/int-move-07.ll
@@ -4,7 +4,7 @@
 
 ; Check STG with no displacement.
 define void @f1(i64 *%dst, i64 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: br %r14
   store i64 %val, i64 *%dst
@@ -13,7 +13,7 @@ define void @f1(i64 *%dst, i64 %val) {
 
 ; Check the high end of the aligned STG range.
 define void @f2(i64 *%dst, i64 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: stg %r3, 524280(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 65535
@@ -24,7 +24,7 @@ define void @f2(i64 *%dst, i64 %val) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f3(i64 *%dst, i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: agfi %r2, 524288
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define void @f3(i64 *%dst, i64 %val) {
 
 ; Check the high end of the negative aligned STG range.
 define void @f4(i64 *%dst, i64 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: stg %r3, -8(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 -1
@@ -45,7 +45,7 @@ define void @f4(i64 *%dst, i64 %val) {
 
 ; Check the low end of the STG range.
 define void @f5(i64 *%dst, i64 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: stg %r3, -524288(%r2)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%dst, i64 -65536
@@ -56,7 +56,7 @@ define void @f5(i64 *%dst, i64 %val) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i64 *%dst, i64 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r2, -524296
 ; CHECK: stg %r3, 0(%r2)
 ; CHECK: br %r14
@@ -67,7 +67,7 @@ define void @f6(i64 *%dst, i64 %val) {
 
 ; Check that STG allows an index.
 define void @f7(i64 %dst, i64 %index, i64 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: stg %r4, 524287({{%r3,%r2|%r2,%r3}})
 ; CHECK: br %r14
   %add1 = add i64 %dst, %index
diff --git a/test/CodeGen/SystemZ/int-move-08.ll b/test/CodeGen/SystemZ/int-move-08.ll
index e6022aa..f16dd8e 100644
--- a/test/CodeGen/SystemZ/int-move-08.ll
+++ b/test/CodeGen/SystemZ/int-move-08.ll
@@ -13,7 +13,7 @@
 
 ; Check sign-extending loads from i16.
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lhrl %r2, gsrc16
 ; CHECK: br %r14
   %val = load i16 *@gsrc16
@@ -23,7 +23,7 @@ define i32 @f1() {
 
 ; Check zero-extending loads from i16.
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llhrl %r2, gsrc16
 ; CHECK: br %r14
   %val = load i16 *@gsrc16
@@ -33,7 +33,7 @@ define i32 @f2() {
 
 ; Check truncating 16-bit stores.
 define void @f3(i32 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sthrl %r2, gdst16
 ; CHECK: br %r14
   %half = trunc i32 %val to i16
@@ -43,7 +43,7 @@ define void @f3(i32 %val) {
 
 ; Check plain loads and stores.
 define void @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lrl %r0, gsrc32
 ; CHECK: strl %r0, gdst32
 ; CHECK: br %r14
@@ -54,7 +54,7 @@ define void @f4() {
 
 ; Repeat f1 with an unaligned variable.
 define i32 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
 ; CHECK: lh %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define i32 @f5() {
 
 ; Repeat f2 with an unaligned variable.
 define i32 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
 ; CHECK: llh %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -76,7 +76,7 @@ define i32 @f6() {
 
 ; Repeat f3 with an unaligned variable.
 define void @f7(i32 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgrl [[REG:%r[0-5]]], gdst16u
 ; CHECK: sth %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define void @f7(i32 %val) {
 
 ; Repeat f4 with unaligned variables.
 define void @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: l [[VAL:%r[0-5]]], 0([[REG]])
 ; CHECK: larl [[REG:%r[0-5]]], gdst32u
diff --git a/test/CodeGen/SystemZ/int-move-09.ll b/test/CodeGen/SystemZ/int-move-09.ll
index 9167405..b5c9cb1 100644
--- a/test/CodeGen/SystemZ/int-move-09.ll
+++ b/test/CodeGen/SystemZ/int-move-09.ll
@@ -17,7 +17,7 @@
 
 ; Check sign-extending loads from i16.
 define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lghrl %r2, gsrc16
 ; CHECK: br %r14
   %val = load i16 *@gsrc16
@@ -27,7 +27,7 @@ define i64 @f1() {
 
 ; Check zero-extending loads from i16.
 define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: llghrl %r2, gsrc16
 ; CHECK: br %r14
   %val = load i16 *@gsrc16
@@ -37,7 +37,7 @@ define i64 @f2() {
 
 ; Check sign-extending loads from i32.
 define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgfrl %r2, gsrc32
 ; CHECK: br %r14
   %val = load i32 *@gsrc32
@@ -47,7 +47,7 @@ define i64 @f3() {
 
 ; Check zero-extending loads from i32.
 define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: llgfrl %r2, gsrc32
 ; CHECK: br %r14
   %val = load i32 *@gsrc32
@@ -57,7 +57,7 @@ define i64 @f4() {
 
 ; Check truncating 16-bit stores.
 define void @f5(i64 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sthrl %r2, gdst16
 ; CHECK: br %r14
   %half = trunc i64 %val to i16
@@ -67,7 +67,7 @@ define void @f5(i64 %val) {
 
 ; Check truncating 32-bit stores.
 define void @f6(i64 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: strl %r2, gdst32
 ; CHECK: br %r14
   %word = trunc i64 %val to i32
@@ -77,7 +77,7 @@ define void @f6(i64 %val) {
 
 ; Check plain loads and stores.
 define void @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgrl %r0, gsrc64
 ; CHECK: stgrl %r0, gdst64
 ; CHECK: br %r14
@@ -88,7 +88,7 @@ define void @f7() {
 
 ; Repeat f1 with an unaligned variable.
 define i64 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
 ; CHECK: lgh %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -99,7 +99,7 @@ define i64 @f8() {
 
 ; Repeat f2 with an unaligned variable.
 define i64 @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
 ; CHECK: llgh %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -110,7 +110,7 @@ define i64 @f9() {
 
 ; Repeat f3 with an unaligned variable.
 define i64 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: lgf %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -121,7 +121,7 @@ define i64 @f10() {
 
 ; Repeat f4 with an unaligned variable.
 define i64 @f11() {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: llgf %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -132,7 +132,7 @@ define i64 @f11() {
 
 ; Repeat f5 with an unaligned variable.
 define void @f12(i64 %val) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: lgrl [[REG:%r[0-5]]], gdst16u@GOT
 ; CHECK: sth %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -143,7 +143,7 @@ define void @f12(i64 %val) {
 
 ; Repeat f6 with an unaligned variable.
 define void @f13(i64 %val) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: larl [[REG:%r[0-5]]], gdst32u
 ; CHECK: st %r2, 0([[REG]])
 ; CHECK: br %r14
@@ -154,7 +154,7 @@ define void @f13(i64 %val) {
 
 ; Repeat f7 with unaligned variables.
 define void @f14() {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: larl [[REG:%r[0-5]]], gsrc64u
 ; CHECK: lg [[VAL:%r[0-5]]], 0([[REG]])
 ; CHECK: larl [[REG:%r[0-5]]], gdst64u
diff --git a/test/CodeGen/SystemZ/int-mul-01.ll b/test/CodeGen/SystemZ/int-mul-01.ll
index e1246e2..d5f7155 100644
--- a/test/CodeGen/SystemZ/int-mul-01.ll
+++ b/test/CodeGen/SystemZ/int-mul-01.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the MH range.
 define i32 @f1(i32 %lhs, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mh %r2, 0(%r3)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -16,7 +16,7 @@ define i32 @f1(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned MH range.
 define i32 @f2(i32 %lhs, i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mh %r2, 4094(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2047
@@ -28,7 +28,7 @@ define i32 @f2(i32 %lhs, i16 *%src) {
 
 ; Check the next halfword up, which should use MHY instead of MH.
 define i32 @f3(i32 %lhs, i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mhy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2048
@@ -40,7 +40,7 @@ define i32 @f3(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned MHY range.
 define i32 @f4(i32 %lhs, i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mhy %r2, 524286(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -53,7 +53,7 @@ define i32 @f4(i32 %lhs, i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i32 %lhs, i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, 524288
 ; CHECK: mh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -66,7 +66,7 @@ define i32 @f5(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the negative aligned MHY range.
 define i32 @f6(i32 %lhs, i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mhy %r2, -2(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -78,7 +78,7 @@ define i32 @f6(i32 %lhs, i16 *%src) {
 
 ; Check the low end of the MHY range.
 define i32 @f7(i32 %lhs, i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mhy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -91,7 +91,7 @@ define i32 @f7(i32 %lhs, i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 %lhs, i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524290
 ; CHECK: mh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f8(i32 %lhs, i16 *%src) {
 
 ; Check that MH allows an index.
 define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: mh %r2, 4094({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -118,7 +118,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
 
 ; Check that MHY allows an index.
 define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: mhy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/int-mul-02.ll b/test/CodeGen/SystemZ/int-mul-02.ll
index d39c4dd..d002a7f 100644
--- a/test/CodeGen/SystemZ/int-mul-02.ll
+++ b/test/CodeGen/SystemZ/int-mul-02.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i32 @foo()
+
 ; Check MSR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msr %r2, %r3
 ; CHECK: br %r14
   %mul = mul i32 %a, %b
@@ -13,7 +15,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the MS range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ms %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -23,7 +25,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned MS range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ms %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -34,7 +36,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use MSY instead of MS.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: msy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -45,7 +47,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned MSY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: msy %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -57,7 +59,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: ms %r2, 0(%r3)
 ; CHECK: br %r14
@@ -69,7 +71,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned MSY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: msy %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -80,7 +82,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the MSY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: msy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -92,7 +94,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: ms %r2, 0(%r3)
 ; CHECK: br %r14
@@ -104,7 +106,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that MS allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ms %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -117,7 +119,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that MSY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: msy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -127,3 +129,46 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
   %mul = mul i32 %a, %b
   ret i32 %mul
 }
+
+; Check that multiplications of spilled values can use MS rather than MSR.
+define i32 @f12(i32 *%ptr0) {
+; CHECK-LABEL: f12:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: ms %r2, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32 *%ptr0, i64 18
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+  %val9 = load i32 *%ptr9
+
+  %ret = call i32 @foo()
+
+  %mul0 = mul i32 %ret, %val0
+  %mul1 = mul i32 %mul0, %val1
+  %mul2 = mul i32 %mul1, %val2
+  %mul3 = mul i32 %mul2, %val3
+  %mul4 = mul i32 %mul3, %val4
+  %mul5 = mul i32 %mul4, %val5
+  %mul6 = mul i32 %mul5, %val6
+  %mul7 = mul i32 %mul6, %val7
+  %mul8 = mul i32 %mul7, %val8
+  %mul9 = mul i32 %mul8, %val9
+
+  ret i32 %mul9
+}
diff --git a/test/CodeGen/SystemZ/int-mul-03.ll b/test/CodeGen/SystemZ/int-mul-03.ll
index ab4ef9e..df18050 100644
--- a/test/CodeGen/SystemZ/int-mul-03.ll
+++ b/test/CodeGen/SystemZ/int-mul-03.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i64 @foo()
+
 ; Check MSGFR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msgfr %r2, %r3
 ; CHECK: br %r14
   %bext = sext i32 %b to i64
@@ -14,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; Check MSGF with no displacement.
 define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: msgf %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +27,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 
 ; Check the high end of the aligned MSGF range.
 define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: msgf %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -38,7 +40,7 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: msgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -51,7 +53,7 @@ define i64 @f4(i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned MSGF range.
 define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: msgf %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -63,7 +65,7 @@ define i64 @f5(i64 %a, i32 *%src) {
 
 ; Check the low end of the MSGF range.
 define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: msgf %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -76,7 +78,7 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524292
 ; CHECK: msgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -89,7 +91,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; Check that MSGF allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: msgf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -100,3 +102,79 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %mul = mul i64 %a, %bext
   ret i64 %mul
 }
+
+; Check that multiplications of spilled values can use MSGF rather than MSGFR.
+define i64 @f9(i32 *%ptr0) {
+; CHECK-LABEL: f9:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: msgf %r2, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32 *%ptr0, i64 18
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+  %val9 = load i32 *%ptr9
+
+  %frob0 = add i32 %val0, 100
+  %frob1 = add i32 %val1, 100
+  %frob2 = add i32 %val2, 100
+  %frob3 = add i32 %val3, 100
+  %frob4 = add i32 %val4, 100
+  %frob5 = add i32 %val5, 100
+  %frob6 = add i32 %val6, 100
+  %frob7 = add i32 %val7, 100
+  %frob8 = add i32 %val8, 100
+  %frob9 = add i32 %val9, 100
+
+  store i32 %frob0, i32 *%ptr0
+  store i32 %frob1, i32 *%ptr1
+  store i32 %frob2, i32 *%ptr2
+  store i32 %frob3, i32 *%ptr3
+  store i32 %frob4, i32 *%ptr4
+  store i32 %frob5, i32 *%ptr5
+  store i32 %frob6, i32 *%ptr6
+  store i32 %frob7, i32 *%ptr7
+  store i32 %frob8, i32 *%ptr8
+  store i32 %frob9, i32 *%ptr9
+
+  %ret = call i64 @foo()
+
+  %ext0 = sext i32 %frob0 to i64
+  %ext1 = sext i32 %frob1 to i64
+  %ext2 = sext i32 %frob2 to i64
+  %ext3 = sext i32 %frob3 to i64
+  %ext4 = sext i32 %frob4 to i64
+  %ext5 = sext i32 %frob5 to i64
+  %ext6 = sext i32 %frob6 to i64
+  %ext7 = sext i32 %frob7 to i64
+  %ext8 = sext i32 %frob8 to i64
+  %ext9 = sext i32 %frob9 to i64
+
+  %mul0 = mul i64 %ret, %ext0
+  %mul1 = mul i64 %mul0, %ext1
+  %mul2 = mul i64 %mul1, %ext2
+  %mul3 = mul i64 %mul2, %ext3
+  %mul4 = mul i64 %mul3, %ext4
+  %mul5 = mul i64 %mul4, %ext5
+  %mul6 = mul i64 %mul5, %ext6
+  %mul7 = mul i64 %mul6, %ext7
+  %mul8 = mul i64 %mul7, %ext8
+  %mul9 = mul i64 %mul8, %ext9
+
+  ret i64 %mul9
+}
diff --git a/test/CodeGen/SystemZ/int-mul-04.ll b/test/CodeGen/SystemZ/int-mul-04.ll
index 94c2639..183a9a7 100644
--- a/test/CodeGen/SystemZ/int-mul-04.ll
+++ b/test/CodeGen/SystemZ/int-mul-04.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i64 @foo()
+
 ; Check MSGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msgr %r2, %r3
 ; CHECK: br %r14
   %mul = mul i64 %a, %b
@@ -13,7 +15,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check MSG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: msg %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -23,7 +25,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned MSG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: msg %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -35,7 +37,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: msg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -47,7 +49,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned MSG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: msg %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -58,7 +60,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the MSG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: msg %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -70,7 +72,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: msg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -82,7 +84,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that MSG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: msg %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -92,3 +94,46 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %mul = mul i64 %a, %b
   ret i64 %mul
 }
+
+; Check that multiplications of spilled values can use MSG rather than MSGR.
+define i64 @f9(i64 *%ptr0) {
+; CHECK-LABEL: f9:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: msg %r2, 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64 *%ptr0, i64 18
+
+  %val0 = load i64 *%ptr0
+  %val1 = load i64 *%ptr1
+  %val2 = load i64 *%ptr2
+  %val3 = load i64 *%ptr3
+  %val4 = load i64 *%ptr4
+  %val5 = load i64 *%ptr5
+  %val6 = load i64 *%ptr6
+  %val7 = load i64 *%ptr7
+  %val8 = load i64 *%ptr8
+  %val9 = load i64 *%ptr9
+
+  %ret = call i64 @foo()
+
+  %mul0 = mul i64 %ret, %val0
+  %mul1 = mul i64 %mul0, %val1
+  %mul2 = mul i64 %mul1, %val2
+  %mul3 = mul i64 %mul2, %val3
+  %mul4 = mul i64 %mul3, %val4
+  %mul5 = mul i64 %mul4, %val5
+  %mul6 = mul i64 %mul5, %val6
+  %mul7 = mul i64 %mul6, %val7
+  %mul8 = mul i64 %mul7, %val8
+  %mul9 = mul i64 %mul8, %val9
+
+  ret i64 %mul9
+}
diff --git a/test/CodeGen/SystemZ/int-mul-05.ll b/test/CodeGen/SystemZ/int-mul-05.ll
index 5e4031b..93f140d 100644
--- a/test/CodeGen/SystemZ/int-mul-05.ll
+++ b/test/CodeGen/SystemZ/int-mul-05.ll
@@ -4,7 +4,7 @@
 
 ; Check multiplication by 2, which should use shifts.
 define i32 @f1(i32 %a, i32 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sll %r2, 1
 ; CHECK: br %r14
   %mul = mul i32 %a, 2
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a, i32 *%dest) {
 
 ; Check multiplication by 3.
 define i32 @f2(i32 %a, i32 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mhi %r2, 3
 ; CHECK: br %r14
   %mul = mul i32 %a, 3
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a, i32 *%dest) {
 
 ; Check the high end of the MHI range.
 define i32 @f3(i32 %a, i32 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mhi %r2, 32767
 ; CHECK: br %r14
   %mul = mul i32 %a, 32767
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a, i32 *%dest) {
 
 ; Check the next value up, which should use shifts.
 define i32 @f4(i32 %a, i32 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sll %r2, 15
 ; CHECK: br %r14
   %mul = mul i32 %a, 32768
@@ -40,7 +40,7 @@ define i32 @f4(i32 %a, i32 *%dest) {
 
 ; Check the next value up again, which can use MSFI.
 define i32 @f5(i32 %a, i32 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: msfi %r2, 32769
 ; CHECK: br %r14
   %mul = mul i32 %a, 32769
@@ -49,7 +49,7 @@ define i32 @f5(i32 %a, i32 *%dest) {
 
 ; Check the high end of the MSFI range.
 define i32 @f6(i32 %a, i32 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: msfi %r2, 2147483647
 ; CHECK: br %r14
   %mul = mul i32 %a, 2147483647
@@ -58,7 +58,7 @@ define i32 @f6(i32 %a, i32 *%dest) {
 
 ; Check the next value up, which should use shifts.
 define i32 @f7(i32 %a, i32 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sll %r2, 31
 ; CHECK: br %r14
   %mul = mul i32 %a, 2147483648
@@ -67,7 +67,7 @@ define i32 @f7(i32 %a, i32 *%dest) {
 
 ; Check the next value up again, which is treated as a negative value.
 define i32 @f8(i32 %a, i32 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: msfi %r2, -2147483647
 ; CHECK: br %r14
   %mul = mul i32 %a, 2147483649
@@ -76,7 +76,7 @@ define i32 @f8(i32 %a, i32 *%dest) {
 
 ; Check multiplication by -1, which is a negation.
 define i32 @f9(i32 %a, i32 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lcr %r2, %r2
 ; CHECK: br %r14
   %mul = mul i32 %a, -1
@@ -85,7 +85,7 @@ define i32 @f9(i32 %a, i32 *%dest) {
 
 ; Check multiplication by -2, which should use shifts.
 define i32 @f10(i32 %a, i32 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: sll %r2, 1
 ; CHECK: lcr %r2, %r2
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i32 @f10(i32 %a, i32 *%dest) {
 
 ; Check multiplication by -3.
 define i32 @f11(i32 %a, i32 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: mhi %r2, -3
 ; CHECK: br %r14
   %mul = mul i32 %a, -3
@@ -104,7 +104,7 @@ define i32 @f11(i32 %a, i32 *%dest) {
 
 ; Check the lowest useful MHI value.
 define i32 @f12(i32 %a, i32 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mhi %r2, -32767
 ; CHECK: br %r14
   %mul = mul i32 %a, -32767
@@ -113,7 +113,7 @@ define i32 @f12(i32 %a, i32 *%dest) {
 
 ; Check the next value down, which should use shifts.
 define i32 @f13(i32 %a, i32 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: sll %r2, 15
 ; CHECK: lcr %r2, %r2
 ; CHECK: br %r14
@@ -123,7 +123,7 @@ define i32 @f13(i32 %a, i32 *%dest) {
 
 ; Check the next value down again, which can use MSFI.
 define i32 @f14(i32 %a, i32 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: msfi %r2, -32769
 ; CHECK: br %r14
   %mul = mul i32 %a, -32769
@@ -132,7 +132,7 @@ define i32 @f14(i32 %a, i32 *%dest) {
 
 ; Check the lowest useful MSFI value.
 define i32 @f15(i32 %a, i32 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: msfi %r2, -2147483647
 ; CHECK: br %r14
   %mul = mul i32 %a, -2147483647
@@ -141,7 +141,7 @@ define i32 @f15(i32 %a, i32 *%dest) {
 
 ; Check the next value down, which should use shifts.
 define i32 @f16(i32 %a, i32 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: sll %r2, 31
 ; CHECK-NOT: lcr
 ; CHECK: br %r14
@@ -151,7 +151,7 @@ define i32 @f16(i32 %a, i32 *%dest) {
 
 ; Check the next value down again, which is treated as a positive value.
 define i32 @f17(i32 %a, i32 *%dest) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: msfi %r2, 2147483647
 ; CHECK: br %r14
   %mul = mul i32 %a, -2147483649
diff --git a/test/CodeGen/SystemZ/int-mul-06.ll b/test/CodeGen/SystemZ/int-mul-06.ll
index a354605..ae9f9c6 100644
--- a/test/CodeGen/SystemZ/int-mul-06.ll
+++ b/test/CodeGen/SystemZ/int-mul-06.ll
@@ -4,7 +4,7 @@
 
 ; Check multiplication by 2, which should use shifts.
 define i64 @f1(i64 %a, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg %r2, %r2, 1
 ; CHECK: br %r14
   %mul = mul i64 %a, 2
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a, i64 *%dest) {
 
 ; Check multiplication by 3.
 define i64 @f2(i64 %a, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mghi %r2, 3
 ; CHECK: br %r14
   %mul = mul i64 %a, 3
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a, i64 *%dest) {
 
 ; Check the high end of the MGHI range.
 define i64 @f3(i64 %a, i64 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mghi %r2, 32767
 ; CHECK: br %r14
   %mul = mul i64 %a, 32767
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a, i64 *%dest) {
 
 ; Check the next value up, which should use shifts.
 define i64 @f4(i64 %a, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sllg %r2, %r2, 15
 ; CHECK: br %r14
   %mul = mul i64 %a, 32768
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a, i64 *%dest) {
 
 ; Check the next value up again, which can use MSGFI.
 define i64 @f5(i64 %a, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: msgfi %r2, 32769
 ; CHECK: br %r14
   %mul = mul i64 %a, 32769
@@ -49,7 +49,7 @@ define i64 @f5(i64 %a, i64 *%dest) {
 
 ; Check the high end of the MSGFI range.
 define i64 @f6(i64 %a, i64 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: msgfi %r2, 2147483647
 ; CHECK: br %r14
   %mul = mul i64 %a, 2147483647
@@ -58,7 +58,7 @@ define i64 @f6(i64 %a, i64 *%dest) {
 
 ; Check the next value up, which should use shifts.
 define i64 @f7(i64 %a, i64 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r2, %r2, 31
 ; CHECK: br %r14
   %mul = mul i64 %a, 2147483648
@@ -67,7 +67,7 @@ define i64 @f7(i64 %a, i64 *%dest) {
 
 ; Check the next value up again, which cannot use a constant multiplicatoin.
 define i64 @f8(i64 %a, i64 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK-NOT: msgfi
 ; CHECK: br %r14
   %mul = mul i64 %a, 2147483649
@@ -76,7 +76,7 @@ define i64 @f8(i64 %a, i64 *%dest) {
 
 ; Check multiplication by -1, which is a negation.
 define i64 @f9(i64 %a, i64 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: lcgr {{%r[0-5]}}, %r2
 ; CHECK: br %r14
   %mul = mul i64 %a, -1
@@ -85,7 +85,7 @@ define i64 @f9(i64 %a, i64 *%dest) {
 
 ; Check multiplication by -2, which should use shifts.
 define i64 @f10(i64 %a, i64 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: sllg [[SHIFTED:%r[0-5]]], %r2, 1
 ; CHECK: lcgr %r2, [[SHIFTED]]
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f10(i64 %a, i64 *%dest) {
 
 ; Check multiplication by -3.
 define i64 @f11(i64 %a, i64 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: mghi %r2, -3
 ; CHECK: br %r14
   %mul = mul i64 %a, -3
@@ -104,7 +104,7 @@ define i64 @f11(i64 %a, i64 *%dest) {
 
 ; Check the lowest useful MGHI value.
 define i64 @f12(i64 %a, i64 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mghi %r2, -32767
 ; CHECK: br %r14
   %mul = mul i64 %a, -32767
@@ -113,7 +113,7 @@ define i64 @f12(i64 %a, i64 *%dest) {
 
 ; Check the next value down, which should use shifts.
 define i64 @f13(i64 %a, i64 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: sllg [[SHIFTED:%r[0-5]]], %r2, 15
 ; CHECK: lcgr %r2, [[SHIFTED]]
 ; CHECK: br %r14
@@ -123,7 +123,7 @@ define i64 @f13(i64 %a, i64 *%dest) {
 
 ; Check the next value down again, which can use MSGFI.
 define i64 @f14(i64 %a, i64 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: msgfi %r2, -32769
 ; CHECK: br %r14
   %mul = mul i64 %a, -32769
@@ -132,7 +132,7 @@ define i64 @f14(i64 %a, i64 *%dest) {
 
 ; Check the lowest useful MSGFI value.
 define i64 @f15(i64 %a, i64 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: msgfi %r2, -2147483647
 ; CHECK: br %r14
   %mul = mul i64 %a, -2147483647
@@ -141,7 +141,7 @@ define i64 @f15(i64 %a, i64 *%dest) {
 
 ; Check the next value down, which should use shifts.
 define i64 @f16(i64 %a, i64 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: sllg [[SHIFTED:%r[0-5]]], %r2, 31
 ; CHECK: lcgr %r2, [[SHIFTED]]
 ; CHECK: br %r14
@@ -151,7 +151,7 @@ define i64 @f16(i64 %a, i64 *%dest) {
 
 ; Check the next value down again, which cannot use constant multiplication
 define i64 @f17(i64 %a, i64 *%dest) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK-NOT: msgfi
 ; CHECK: br %r14
   %mul = mul i64 %a, -2147483649
diff --git a/test/CodeGen/SystemZ/int-mul-07.ll b/test/CodeGen/SystemZ/int-mul-07.ll
index 2459cc3..874f43d 100644
--- a/test/CodeGen/SystemZ/int-mul-07.ll
+++ b/test/CodeGen/SystemZ/int-mul-07.ll
@@ -7,7 +7,7 @@
 
 ; Check zero-extended multiplication in which only the high part is used.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: msgr
 ; CHECK: br %r14
   %ax = zext i32 %a to i64
@@ -20,7 +20,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check sign-extended multiplication in which only the high part is used.
 define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: msgfr
 ; CHECK: br %r14
   %ax = sext i32 %a to i64
@@ -34,7 +34,7 @@ define i32 @f2(i32 %a, i32 %b) {
 ; Check zero-extended multiplication in which the result is split into
 ; high and low halves.
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: msgr
 ; CHECK: br %r14
   %ax = zext i32 %a to i64
@@ -50,7 +50,7 @@ define i32 @f3(i32 %a, i32 %b) {
 ; Check sign-extended multiplication in which the result is split into
 ; high and low halves.
 define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: msgfr
 ; CHECK: br %r14
   %ax = sext i32 %a to i64
diff --git a/test/CodeGen/SystemZ/int-mul-08.ll b/test/CodeGen/SystemZ/int-mul-08.ll
index 09ebe7a..a245760 100644
--- a/test/CodeGen/SystemZ/int-mul-08.ll
+++ b/test/CodeGen/SystemZ/int-mul-08.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i64 @foo()
+
 ; Check zero-extended multiplication in which only the high part is used.
 define i64 @f1(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: mlgr %r2, %r4
 ; CHECK: br %r14
@@ -19,7 +21,7 @@ define i64 @f1(i64 %dummy, i64 %a, i64 %b) {
 ; Check sign-extended multiplication in which only the high part is used.
 ; This needs a rather convoluted sequence.
 define i64 @f2(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mlgr
 ; CHECK: agr
 ; CHECK: agr
@@ -35,7 +37,7 @@ define i64 @f2(i64 %dummy, i64 %a, i64 %b) {
 ; Check zero-extended multiplication in which only part of the high half
 ; is used.
 define i64 @f3(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: mlgr %r2, %r4
 ; CHECK: srlg %r2, %r2, 3
@@ -51,7 +53,7 @@ define i64 @f3(i64 %dummy, i64 %a, i64 %b) {
 ; Check zero-extended multiplication in which the result is split into
 ; high and low halves.
 define i64 @f4(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: mlgr %r2, %r4
 ; CHECK: ogr %r2, %r3
@@ -68,7 +70,7 @@ define i64 @f4(i64 %dummy, i64 %a, i64 %b) {
 
 ; Check division by a constant, which should use multiplication instead.
 define i64 @f5(i64 %dummy, i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mlgr %r2,
 ; CHECK: srlg %r2, %r2,
 ; CHECK: br %r14
@@ -78,7 +80,7 @@ define i64 @f5(i64 %dummy, i64 %a) {
 
 ; Check MLG with no displacement.
 define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: {{%r[234]}}
 ; CHECK: mlg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -93,7 +95,7 @@ define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned MLG range.
 define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mlg %r2, 524280(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -109,7 +111,7 @@ define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword up, which requires separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r4, 524288
 ; CHECK: mlg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -125,7 +127,7 @@ define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned MLG range.
 define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: mlg %r2, -8(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -140,7 +142,7 @@ define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
 
 ; Check the low end of the MLG range.
 define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: mlg %r2, -524288(%r4)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -156,7 +158,7 @@ define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f11(i64 *%dest, i64 %a, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r4, -524296
 ; CHECK: mlg %r2, 0(%r4)
 ; CHECK: br %r14
@@ -172,7 +174,7 @@ define i64 @f11(i64 *%dest, i64 %a, i64 *%src) {
 
 ; Check that MLG allows an index.
 define i64 @f12(i64 *%dest, i64 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: mlg %r2, 524287(%r5,%r4)
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -186,3 +188,77 @@ define i64 @f12(i64 *%dest, i64 %a, i64 %src, i64 %index) {
   %high = trunc i128 %highx to i64
   ret i64 %high
 }
+
+; Check that multiplications of spilled values can use MLG rather than MLGR.
+define i64 @f13(i64 *%ptr0) {
+; CHECK-LABEL: f13:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: mlg {{%r[0-9]+}}, 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64 *%ptr0, i64 18
+
+  %val0 = load i64 *%ptr0
+  %val1 = load i64 *%ptr1
+  %val2 = load i64 *%ptr2
+  %val3 = load i64 *%ptr3
+  %val4 = load i64 *%ptr4
+  %val5 = load i64 *%ptr5
+  %val6 = load i64 *%ptr6
+  %val7 = load i64 *%ptr7
+  %val8 = load i64 *%ptr8
+  %val9 = load i64 *%ptr9
+
+  %ret = call i64 @foo()
+
+  %retx = zext i64 %ret to i128
+  %val0x = zext i64 %val0 to i128
+  %mul0d = mul i128 %retx, %val0x
+  %mul0x = lshr i128 %mul0d, 64
+
+  %val1x = zext i64 %val1 to i128
+  %mul1d = mul i128 %mul0x, %val1x
+  %mul1x = lshr i128 %mul1d, 64
+
+  %val2x = zext i64 %val2 to i128
+  %mul2d = mul i128 %mul1x, %val2x
+  %mul2x = lshr i128 %mul2d, 64
+
+  %val3x = zext i64 %val3 to i128
+  %mul3d = mul i128 %mul2x, %val3x
+  %mul3x = lshr i128 %mul3d, 64
+
+  %val4x = zext i64 %val4 to i128
+  %mul4d = mul i128 %mul3x, %val4x
+  %mul4x = lshr i128 %mul4d, 64
+
+  %val5x = zext i64 %val5 to i128
+  %mul5d = mul i128 %mul4x, %val5x
+  %mul5x = lshr i128 %mul5d, 64
+
+  %val6x = zext i64 %val6 to i128
+  %mul6d = mul i128 %mul5x, %val6x
+  %mul6x = lshr i128 %mul6d, 64
+
+  %val7x = zext i64 %val7 to i128
+  %mul7d = mul i128 %mul6x, %val7x
+  %mul7x = lshr i128 %mul7d, 64
+
+  %val8x = zext i64 %val8 to i128
+  %mul8d = mul i128 %mul7x, %val8x
+  %mul8x = lshr i128 %mul8d, 64
+
+  %val9x = zext i64 %val9 to i128
+  %mul9d = mul i128 %mul8x, %val9x
+  %mul9x = lshr i128 %mul9d, 64
+
+  %mul9 = trunc i128 %mul9x to i64
+  ret i64 %mul9
+}
diff --git a/test/CodeGen/SystemZ/int-neg-01.ll b/test/CodeGen/SystemZ/int-neg-01.ll
index 6114f4e..a342fa7 100644
--- a/test/CodeGen/SystemZ/int-neg-01.ll
+++ b/test/CodeGen/SystemZ/int-neg-01.ll
@@ -4,7 +4,7 @@
 
 ; Test i32->i32 negation.
 define i32 @f1(i32 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lcr %r2, %r2
 ; CHECK: br %r14
   %neg = sub i32 0, %val
@@ -13,7 +13,7 @@ define i32 @f1(i32 %val) {
 
 ; Test i32->i64 negation.
 define i64 @f2(i32 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lcgfr %r2, %r2
 ; CHECK: br %r14
   %ext = sext i32 %val to i64
@@ -23,7 +23,7 @@ define i64 @f2(i32 %val) {
 
 ; Test i32->i64 negation that uses an "in-register" form of sign extension.
 define i64 @f3(i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lcgfr %r2, %r2
 ; CHECK: br %r14
   %trunc = trunc i64 %val to i32
@@ -34,7 +34,7 @@ define i64 @f3(i64 %val) {
 
 ; Test i64 negation.
 define i64 @f4(i64 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lcgr %r2, %r2
 ; CHECK: br %r14
   %neg = sub i64 0, %val
diff --git a/test/CodeGen/SystemZ/int-sub-01.ll b/test/CodeGen/SystemZ/int-sub-01.ll
index 9a73814..8d1e56d 100644
--- a/test/CodeGen/SystemZ/int-sub-01.ll
+++ b/test/CodeGen/SystemZ/int-sub-01.ll
@@ -1,10 +1,13 @@
 ; Test 32-bit subtraction.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i32 @foo()
 
 ; Check SR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sr %r2, %r3
 ; CHECK: br %r14
   %sub = sub i32 %a, %b
@@ -13,7 +16,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the S range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -23,7 +26,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned S range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: s %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -34,7 +37,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use SY instead of S.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -45,7 +48,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned SY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sy %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -57,7 +60,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: br %r14
@@ -69,7 +72,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned SY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sy %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -80,7 +83,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the SY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -92,7 +95,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: br %r14
@@ -104,7 +107,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that S allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: s %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -117,7 +120,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that SY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -127,3 +130,46 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
   %sub = sub i32 %a, %b
   ret i32 %sub
 }
+
+; Check that subtractions of spilled values can use S rather than SR.
+define i32 @f12(i32 *%ptr0) {
+; CHECK-LABEL: f12:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: s %r2, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32 *%ptr0, i64 18
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+  %val9 = load i32 *%ptr9
+
+  %ret = call i32 @foo()
+
+  %sub0 = sub i32 %ret, %val0
+  %sub1 = sub i32 %sub0, %val1
+  %sub2 = sub i32 %sub1, %val2
+  %sub3 = sub i32 %sub2, %val3
+  %sub4 = sub i32 %sub3, %val4
+  %sub5 = sub i32 %sub4, %val5
+  %sub6 = sub i32 %sub5, %val6
+  %sub7 = sub i32 %sub6, %val7
+  %sub8 = sub i32 %sub7, %val8
+  %sub9 = sub i32 %sub8, %val9
+
+  ret i32 %sub9
+}
diff --git a/test/CodeGen/SystemZ/int-sub-02.ll b/test/CodeGen/SystemZ/int-sub-02.ll
index 5150a96..a1c5ec5 100644
--- a/test/CodeGen/SystemZ/int-sub-02.ll
+++ b/test/CodeGen/SystemZ/int-sub-02.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i64 @foo()
+
 ; Check SGFR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sgfr %r2, %r3
 ; CHECK: br %r14
   %bext = sext i32 %b to i64
@@ -14,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; Check SGF with no displacement.
 define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sgf %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +27,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 
 ; Check the high end of the aligned SGF range.
 define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sgf %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -38,7 +40,7 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: sgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -51,7 +53,7 @@ define i64 @f4(i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned SGF range.
 define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sgf %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -63,7 +65,7 @@ define i64 @f5(i64 %a, i32 *%src) {
 
 ; Check the low end of the SGF range.
 define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sgf %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -76,7 +78,7 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524292
 ; CHECK: sgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -89,7 +91,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; Check that SGF allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sgf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -100,3 +102,79 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %sub = sub i64 %a, %bext
   ret i64 %sub
 }
+
+; Check that subtractions of spilled values can use SGF rather than SGFR.
+define i64 @f9(i32 *%ptr0) {
+; CHECK-LABEL: f9:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: sgf %r2, 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32 *%ptr0, i64 18
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+  %val9 = load i32 *%ptr9
+
+  %frob0 = add i32 %val0, 100
+  %frob1 = add i32 %val1, 100
+  %frob2 = add i32 %val2, 100
+  %frob3 = add i32 %val3, 100
+  %frob4 = add i32 %val4, 100
+  %frob5 = add i32 %val5, 100
+  %frob6 = add i32 %val6, 100
+  %frob7 = add i32 %val7, 100
+  %frob8 = add i32 %val8, 100
+  %frob9 = add i32 %val9, 100
+
+  store i32 %frob0, i32 *%ptr0
+  store i32 %frob1, i32 *%ptr1
+  store i32 %frob2, i32 *%ptr2
+  store i32 %frob3, i32 *%ptr3
+  store i32 %frob4, i32 *%ptr4
+  store i32 %frob5, i32 *%ptr5
+  store i32 %frob6, i32 *%ptr6
+  store i32 %frob7, i32 *%ptr7
+  store i32 %frob8, i32 *%ptr8
+  store i32 %frob9, i32 *%ptr9
+
+  %ret = call i64 @foo()
+
+  %ext0 = sext i32 %frob0 to i64
+  %ext1 = sext i32 %frob1 to i64
+  %ext2 = sext i32 %frob2 to i64
+  %ext3 = sext i32 %frob3 to i64
+  %ext4 = sext i32 %frob4 to i64
+  %ext5 = sext i32 %frob5 to i64
+  %ext6 = sext i32 %frob6 to i64
+  %ext7 = sext i32 %frob7 to i64
+  %ext8 = sext i32 %frob8 to i64
+  %ext9 = sext i32 %frob9 to i64
+
+  %sub0 = sub i64 %ret, %ext0
+  %sub1 = sub i64 %sub0, %ext1
+  %sub2 = sub i64 %sub1, %ext2
+  %sub3 = sub i64 %sub2, %ext3
+  %sub4 = sub i64 %sub3, %ext4
+  %sub5 = sub i64 %sub4, %ext5
+  %sub6 = sub i64 %sub5, %ext6
+  %sub7 = sub i64 %sub6, %ext7
+  %sub8 = sub i64 %sub7, %ext8
+  %sub9 = sub i64 %sub8, %ext9
+
+  ret i64 %sub9
+}
diff --git a/test/CodeGen/SystemZ/int-sub-03.ll b/test/CodeGen/SystemZ/int-sub-03.ll
index 73571b3..44edd84 100644
--- a/test/CodeGen/SystemZ/int-sub-03.ll
+++ b/test/CodeGen/SystemZ/int-sub-03.ll
@@ -2,9 +2,11 @@
 ;
 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
 
+declare i64 @foo()
+
 ; Check SLGFR.
 define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: slgfr %r2, %r3
 ; CHECK: br %r14
   %bext = zext i32 %b to i64
@@ -14,7 +16,7 @@ define i64 @f1(i64 %a, i32 %b) {
 
 ; Check SLGF with no displacement.
 define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: slgf %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -25,7 +27,7 @@ define i64 @f2(i64 %a, i32 *%src) {
 
 ; Check the high end of the aligned SLGF range.
 define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: slgf %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -38,7 +40,7 @@ define i64 @f3(i64 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: slgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -51,7 +53,7 @@ define i64 @f4(i64 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned SLGF range.
 define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: slgf %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -63,7 +65,7 @@ define i64 @f5(i64 %a, i32 *%src) {
 
 ; Check the low end of the SLGF range.
 define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: slgf %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -76,7 +78,7 @@ define i64 @f6(i64 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524292
 ; CHECK: slgf %r2, 0(%r3)
 ; CHECK: br %r14
@@ -89,7 +91,7 @@ define i64 @f7(i64 %a, i32 *%src) {
 
 ; Check that SLGF allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: slgf %r2, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -100,3 +102,79 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %sub = sub i64 %a, %bext
   ret i64 %sub
 }
+
+; Check that subtractions of spilled values can use SLGF rather than SLGFR.
+define i64 @f9(i32 *%ptr0) {
+; CHECK-LABEL: f9:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: slgf %r2, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32 *%ptr0, i64 18
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+  %val9 = load i32 *%ptr9
+
+  %frob0 = add i32 %val0, 100
+  %frob1 = add i32 %val1, 100
+  %frob2 = add i32 %val2, 100
+  %frob3 = add i32 %val3, 100
+  %frob4 = add i32 %val4, 100
+  %frob5 = add i32 %val5, 100
+  %frob6 = add i32 %val6, 100
+  %frob7 = add i32 %val7, 100
+  %frob8 = add i32 %val8, 100
+  %frob9 = add i32 %val9, 100
+
+  store i32 %frob0, i32 *%ptr0
+  store i32 %frob1, i32 *%ptr1
+  store i32 %frob2, i32 *%ptr2
+  store i32 %frob3, i32 *%ptr3
+  store i32 %frob4, i32 *%ptr4
+  store i32 %frob5, i32 *%ptr5
+  store i32 %frob6, i32 *%ptr6
+  store i32 %frob7, i32 *%ptr7
+  store i32 %frob8, i32 *%ptr8
+  store i32 %frob9, i32 *%ptr9
+
+  %ret = call i64 @foo()
+
+  %ext0 = zext i32 %frob0 to i64
+  %ext1 = zext i32 %frob1 to i64
+  %ext2 = zext i32 %frob2 to i64
+  %ext3 = zext i32 %frob3 to i64
+  %ext4 = zext i32 %frob4 to i64
+  %ext5 = zext i32 %frob5 to i64
+  %ext6 = zext i32 %frob6 to i64
+  %ext7 = zext i32 %frob7 to i64
+  %ext8 = zext i32 %frob8 to i64
+  %ext9 = zext i32 %frob9 to i64
+
+  %sub0 = sub i64 %ret, %ext0
+  %sub1 = sub i64 %sub0, %ext1
+  %sub2 = sub i64 %sub1, %ext2
+  %sub3 = sub i64 %sub2, %ext3
+  %sub4 = sub i64 %sub3, %ext4
+  %sub5 = sub i64 %sub4, %ext5
+  %sub6 = sub i64 %sub5, %ext6
+  %sub7 = sub i64 %sub6, %ext7
+  %sub8 = sub i64 %sub7, %ext8
+  %sub9 = sub i64 %sub8, %ext9
+
+  ret i64 %sub9
+}
diff --git a/test/CodeGen/SystemZ/int-sub-04.ll b/test/CodeGen/SystemZ/int-sub-04.ll
index 545d342..8510453 100644
--- a/test/CodeGen/SystemZ/int-sub-04.ll
+++ b/test/CodeGen/SystemZ/int-sub-04.ll
@@ -1,10 +1,13 @@
 ; Test 64-bit subtraction in which the second operand is variable.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i64 @foo()
 
 ; Check SGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sgr %r2, %r3
 ; CHECK: br %r14
   %sub = sub i64 %a, %b
@@ -13,7 +16,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check SG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -23,7 +26,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned SG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sg %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -35,7 +38,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -47,7 +50,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned SG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sg %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -58,7 +61,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the SG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sg %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -70,7 +73,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -82,7 +85,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that SG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sg %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -92,3 +95,46 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %sub = sub i64 %a, %b
   ret i64 %sub
 }
+
+; Check that subtractions of spilled values can use SG rather than SGR.
+define i64 @f9(i64 *%ptr0) {
+; CHECK-LABEL: f9:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: sg %r2, 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64 *%ptr0, i64 18
+
+  %val0 = load i64 *%ptr0
+  %val1 = load i64 *%ptr1
+  %val2 = load i64 *%ptr2
+  %val3 = load i64 *%ptr3
+  %val4 = load i64 *%ptr4
+  %val5 = load i64 *%ptr5
+  %val6 = load i64 *%ptr6
+  %val7 = load i64 *%ptr7
+  %val8 = load i64 *%ptr8
+  %val9 = load i64 *%ptr9
+
+  %ret = call i64 @foo()
+
+  %sub0 = sub i64 %ret, %val0
+  %sub1 = sub i64 %sub0, %val1
+  %sub2 = sub i64 %sub1, %val2
+  %sub3 = sub i64 %sub2, %val3
+  %sub4 = sub i64 %sub3, %val4
+  %sub5 = sub i64 %sub4, %val5
+  %sub6 = sub i64 %sub5, %val6
+  %sub7 = sub i64 %sub6, %val7
+  %sub8 = sub i64 %sub7, %val8
+  %sub9 = sub i64 %sub8, %val9
+
+  ret i64 %sub9
+}
diff --git a/test/CodeGen/SystemZ/int-sub-05.ll b/test/CodeGen/SystemZ/int-sub-05.ll
index 1475b24..85ea14c 100644
--- a/test/CodeGen/SystemZ/int-sub-05.ll
+++ b/test/CodeGen/SystemZ/int-sub-05.ll
@@ -1,10 +1,13 @@
-; Test 128-bit addition in which the second operand is variable.
+; Test 128-bit subtraction in which the second operand is variable.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i128 *@foo()
 
 ; Test register addition.
 define void @f1(i128 *%ptr, i64 %high, i64 %low) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: slgr {{%r[0-5]}}, %r4
 ; CHECK: slbgr {{%r[0-5]}}, %r3
 ; CHECK: br %r14
@@ -20,7 +23,7 @@ define void @f1(i128 *%ptr, i64 %high, i64 %low) {
 
 ; Test memory addition with no offset.
 define void @f2(i64 %addr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: slg {{%r[0-5]}}, 8(%r2)
 ; CHECK: slbg {{%r[0-5]}}, 0(%r2)
 ; CHECK: br %r14
@@ -35,7 +38,7 @@ define void @f2(i64 %addr) {
 
 ; Test the highest aligned offset that is in range of both SLG and SLBG.
 define void @f3(i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: slg {{%r[0-5]}}, 524280(%r2)
 ; CHECK: slbg {{%r[0-5]}}, 524272(%r2)
 ; CHECK: br %r14
@@ -51,7 +54,7 @@ define void @f3(i64 %base) {
 
 ; Test the next doubleword up, which requires separate address logic for SLG.
 define void @f4(i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgr [[BASE:%r[1-5]]], %r2
 ; CHECK: agfi [[BASE]], 524288
 ; CHECK: slg {{%r[0-5]}}, 0([[BASE]])
@@ -71,7 +74,7 @@ define void @f4(i64 %base) {
 ; both instructions.  It would be better to create an anchor at 524288
 ; that both instructions can use, but that isn't implemented yet.
 define void @f5(i64 %base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: slg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: slbg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: br %r14
@@ -87,7 +90,7 @@ define void @f5(i64 %base) {
 
 ; Test the lowest displacement that is in range of both SLG and SLBG.
 define void @f6(i64 %base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: slg {{%r[0-5]}}, -524280(%r2)
 ; CHECK: slbg {{%r[0-5]}}, -524288(%r2)
 ; CHECK: br %r14
@@ -103,7 +106,7 @@ define void @f6(i64 %base) {
 
 ; Test the next doubleword down, which is out of range of the SLBG.
 define void @f7(i64 %base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: slg {{%r[0-5]}}, -524288(%r2)
 ; CHECK: slbg {{%r[0-5]}}, 0({{%r[1-5]}})
 ; CHECK: br %r14
@@ -116,3 +119,35 @@ define void @f7(i64 %base) {
   store i128 %sub, i128 *%aptr
   ret void
 }
+
+; Check that subtractions of spilled values can use SLG and SLBG rather than
+; SLGR and SLBGR.
+define void @f8(i128 *%ptr0) {
+; CHECK-LABEL: f8:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: slg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: slbg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i128 *%ptr0, i128 2
+  %ptr2 = getelementptr i128 *%ptr0, i128 4
+  %ptr3 = getelementptr i128 *%ptr0, i128 6
+  %ptr4 = getelementptr i128 *%ptr0, i128 8
+
+  %val0 = load i128 *%ptr0
+  %val1 = load i128 *%ptr1
+  %val2 = load i128 *%ptr2
+  %val3 = load i128 *%ptr3
+  %val4 = load i128 *%ptr4
+
+  %retptr = call i128 *@foo()
+
+  %ret = load i128 *%retptr
+  %sub0 = sub i128 %ret, %val0
+  %sub1 = sub i128 %sub0, %val1
+  %sub2 = sub i128 %sub1, %val2
+  %sub3 = sub i128 %sub2, %val3
+  %sub4 = sub i128 %sub3, %val4
+  store i128 %sub4, i128 *%retptr
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/int-sub-06.ll b/test/CodeGen/SystemZ/int-sub-06.ll
index 0e04d51..395d584 100644
--- a/test/CodeGen/SystemZ/int-sub-06.ll
+++ b/test/CodeGen/SystemZ/int-sub-06.ll
@@ -5,7 +5,7 @@
 ; Check register additions.  The XOR ensures that we don't instead zero-extend
 ; %b into a register and use memory addition.
 define void @f1(i128 *%aptr, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: slgfr {{%r[0-5]}}, %r3
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -19,7 +19,7 @@ define void @f1(i128 *%aptr, i32 %b) {
 
 ; Like f1, but using an "in-register" extension.
 define void @f2(i128 *%aptr, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: slgfr {{%r[0-5]}}, %r3
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -35,7 +35,7 @@ define void @f2(i128 *%aptr, i64 %b) {
 ; Test register addition in cases where the second operand is zero extended
 ; from i64 rather than i32, but is later masked to i32 range.
 define void @f3(i128 *%aptr, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: slgfr {{%r[0-5]}}, %r3
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -50,7 +50,7 @@ define void @f3(i128 *%aptr, i64 %b) {
 
 ; Test SLGF with no offset.
 define void @f4(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: slgf {{%r[0-5]}}, 0(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -65,7 +65,7 @@ define void @f4(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the high end of the SLGF range.
 define void @f5(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: slgf {{%r[0-5]}}, 524284(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -82,7 +82,7 @@ define void @f5(i128 *%aptr, i32 *%bsrc) {
 ; Check the next word up, which must use separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f6(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: slgf {{%r[0-5]}}, 0(%r3)
 ; CHECK: slbgr
@@ -99,7 +99,7 @@ define void @f6(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the high end of the negative aligned SLGF range.
 define void @f7(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: slgf {{%r[0-5]}}, -4(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -115,7 +115,7 @@ define void @f7(i128 *%aptr, i32 *%bsrc) {
 
 ; Check the low end of the SLGF range.
 define void @f8(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: slgf {{%r[0-5]}}, -524288(%r3)
 ; CHECK: slbgr
 ; CHECK: br %r14
@@ -132,7 +132,7 @@ define void @f8(i128 *%aptr, i32 *%bsrc) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f9(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: slgf {{%r[0-5]}}, 0(%r3)
 ; CHECK: slbgr
@@ -149,7 +149,7 @@ define void @f9(i128 *%aptr, i32 *%bsrc) {
 
 ; Check that SLGF allows an index.
 define void @f10(i128 *%aptr, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: slgf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %a = load i128 *%aptr
diff --git a/test/CodeGen/SystemZ/int-sub-07.ll b/test/CodeGen/SystemZ/int-sub-07.ll
index 9bf5ed9..5c1f42c 100644
--- a/test/CodeGen/SystemZ/int-sub-07.ll
+++ b/test/CodeGen/SystemZ/int-sub-07.ll
@@ -5,7 +5,7 @@
 
 ; Check the low end of the SH range.
 define i32 @f1(i32 %lhs, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sh %r2, 0(%r3)
 ; CHECK: br %r14
   %half = load i16 *%src
@@ -16,7 +16,7 @@ define i32 @f1(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned SH range.
 define i32 @f2(i32 %lhs, i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sh %r2, 4094(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2047
@@ -28,7 +28,7 @@ define i32 @f2(i32 %lhs, i16 *%src) {
 
 ; Check the next halfword up, which should use SHY instead of SH.
 define i32 @f3(i32 %lhs, i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: shy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 2048
@@ -40,7 +40,7 @@ define i32 @f3(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the aligned SHY range.
 define i32 @f4(i32 %lhs, i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: shy %r2, 524286(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 262143
@@ -53,7 +53,7 @@ define i32 @f4(i32 %lhs, i16 *%src) {
 ; Check the next halfword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f5(i32 %lhs, i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: agfi %r3, 524288
 ; CHECK: sh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -66,7 +66,7 @@ define i32 @f5(i32 %lhs, i16 *%src) {
 
 ; Check the high end of the negative aligned SHY range.
 define i32 @f6(i32 %lhs, i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: shy %r2, -2(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -1
@@ -78,7 +78,7 @@ define i32 @f6(i32 %lhs, i16 *%src) {
 
 ; Check the low end of the SHY range.
 define i32 @f7(i32 %lhs, i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: shy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i16 *%src, i64 -262144
@@ -91,7 +91,7 @@ define i32 @f7(i32 %lhs, i16 *%src) {
 ; Check the next halfword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f8(i32 %lhs, i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r3, -524290
 ; CHECK: sh %r2, 0(%r3)
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f8(i32 %lhs, i16 *%src) {
 
 ; Check that SH allows an index.
 define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: sh %r2, 4094({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %sub1 = add i64 %src, %index
@@ -118,7 +118,7 @@ define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
 
 ; Check that SHY allows an index.
 define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: shy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %sub1 = add i64 %src, %index
diff --git a/test/CodeGen/SystemZ/int-sub-08.ll b/test/CodeGen/SystemZ/int-sub-08.ll
new file mode 100644
index 0000000..f0a5e1e
--- /dev/null
+++ b/test/CodeGen/SystemZ/int-sub-08.ll
@@ -0,0 +1,39 @@
+; Test the three-operand forms of subtraction.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check SRK.
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f1:
+; CHECK: srk %r2, %r3, %r4
+; CHECK: br %r14
+  %sub = sub i32 %b, %c
+  ret i32 %sub
+}
+
+; Check that we can still use SR in obvious cases.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: sr %r2, %r3
+; CHECK: br %r14
+  %sub = sub i32 %a, %b
+  ret i32 %sub
+}
+
+; Check SGRK.
+define i64 @f3(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f3:
+; CHECK: sgrk %r2, %r3, %r4
+; CHECK: br %r14
+  %sub = sub i64 %b, %c
+  ret i64 %sub
+}
+
+; Check that we can still use SGR in obvious cases.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: sgr %r2, %r3
+; CHECK: br %r14
+  %sub = sub i64 %a, %b
+  ret i64 %sub
+}
diff --git a/test/CodeGen/SystemZ/int-sub-09.ll b/test/CodeGen/SystemZ/int-sub-09.ll
new file mode 100644
index 0000000..00a60d3
--- /dev/null
+++ b/test/CodeGen/SystemZ/int-sub-09.ll
@@ -0,0 +1,22 @@
+; Test 128-bit subtraction when the distinct-operands facility is available.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Test the case where both operands are in registers.
+define i64 @f1(i64 %a, i64 %b, i64 %c, i64 %d, i64 *%ptr) {
+; CHECK-LABEL: f1:
+; CHECK: slgrk %r2, %r4, %r5
+; CHECK: slbgr
+; CHECK: br %r14
+  %x1 = insertelement <2 x i64> undef, i64 %b, i32 0
+  %x2 = insertelement <2 x i64> %x1, i64 %c, i32 1
+  %x = bitcast <2 x i64> %x2 to i128
+  %y2 = insertelement <2 x i64> %x1, i64 %d, i32 1
+  %y = bitcast <2 x i64> %y2 to i128
+  %sub = sub i128 %x, %y
+  %subv = bitcast i128 %sub to <2 x i64>
+  %high = extractelement <2 x i64> %subv, i32 0
+  store i64 %high, i64 *%ptr
+  %low = extractelement <2 x i64> %subv, i32 1
+  ret i64 %low
+}
diff --git a/test/CodeGen/SystemZ/la-01.ll b/test/CodeGen/SystemZ/la-01.ll
index b43e3f8..31d2041 100644
--- a/test/CodeGen/SystemZ/la-01.ll
+++ b/test/CodeGen/SystemZ/la-01.ll
@@ -15,9 +15,11 @@ define void @df() {
   ret void
 }
 
+declare void @foo(i32 *)
+
 ; Test a load of a fully-aligned external variable.
 define i32 *@f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: larl %r2, e4
 ; CHECK-NEXT: br %r14
   ret i32 *@e4
@@ -25,7 +27,7 @@ define i32 *@f1() {
 
 ; Test a load of a fully-aligned local variable.
 define i32 *@f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: larl %r2, d4
 ; CHECK-NEXT: br %r14
   ret i32 *@d4
@@ -33,7 +35,7 @@ define i32 *@f2() {
 
 ; Test a load of a 2-byte-aligned external variable.
 define i32 *@f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: larl %r2, e2
 ; CHECK-NEXT: br %r14
   ret i32 *@e2
@@ -41,7 +43,7 @@ define i32 *@f3() {
 
 ; Test a load of a 2-byte-aligned local variable.
 define i32 *@f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: larl %r2, d2
 ; CHECK-NEXT: br %r14
   ret i32 *@d2
@@ -49,7 +51,7 @@ define i32 *@f4() {
 
 ; Test a load of an unaligned external variable, which must go via the GOT.
 define i32 *@f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl %r2, e1@GOT
 ; CHECK-NEXT: br %r14
   ret i32 *@e1
@@ -57,7 +59,7 @@ define i32 *@f5() {
 
 ; Test a load of an unaligned local variable, which must go via the GOT.
 define i32 *@f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgrl %r2, d1@GOT
 ; CHECK-NEXT: br %r14
   ret i32 *@d1
@@ -65,7 +67,7 @@ define i32 *@f6() {
 
 ; Test a load of an external function.
 define void() *@f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: larl %r2, ef
 ; CHECK-NEXT: br %r14
   ret void() *@ef
@@ -73,8 +75,21 @@ define void() *@f7() {
 
 ; Test a load of a local function.
 define void() *@f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: larl %r2, df
 ; CHECK-NEXT: br %r14
   ret void() *@df
 }
+
+; Test that LARL can be rematerialized.
+define i32 @f9() {
+; CHECK-LABEL: f9:
+; CHECK: larl %r2, d2
+; CHECK: brasl %r14, foo@PLT
+; CHECK: larl %r2, d2
+; CHECK: brasl %r14, foo@PLT
+; CHECK: br %r14
+  call void @foo(i32 *@d2)
+  call void @foo(i32 *@d2)
+  ret i32 0
+}
diff --git a/test/CodeGen/SystemZ/la-02.ll b/test/CodeGen/SystemZ/la-02.ll
index 4c5374a..d7362d6 100644
--- a/test/CodeGen/SystemZ/la-02.ll
+++ b/test/CodeGen/SystemZ/la-02.ll
@@ -23,7 +23,7 @@ define hidden void @hf() {
 ; Test loads of external variables.  There is no guarantee that the
 ; variable will be in range of LARL.
 define i32 *@f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lgrl %r2, ev@GOT
 ; CHECK: br %r14
   ret i32 *@ev
@@ -31,7 +31,7 @@ define i32 *@f1() {
 
 ; ...likewise locally-defined normal-visibility variables.
 define i32 *@f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lgrl %r2, dv@GOT
 ; CHECK: br %r14
   ret i32 *@dv
@@ -39,7 +39,7 @@ define i32 *@f2() {
 
 ; ...likewise protected variables.
 define i32 *@f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: lgrl %r2, pv@GOT
 ; CHECK: br %r14
   ret i32 *@pv
@@ -47,7 +47,7 @@ define i32 *@f3() {
 
 ; ...likewise hidden variables.
 define i32 *@f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lgrl %r2, hv@GOT
 ; CHECK: br %r14
   ret i32 *@hv
@@ -56,7 +56,7 @@ define i32 *@f4() {
 ; Check loads of external functions.  This could use LARL, but we don't have
 ; code to detect that yet.
 define void() *@f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl %r2, ef@GOT
 ; CHECK: br %r14
   ret void() *@ef
@@ -64,7 +64,7 @@ define void() *@f5() {
 
 ; ...likewise locally-defined normal-visibility functions.
 define void() *@f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgrl %r2, df@GOT
 ; CHECK: br %r14
   ret void() *@df
@@ -72,7 +72,7 @@ define void() *@f6() {
 
 ; ...likewise protected functions.
 define void() *@f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lgrl %r2, pf@GOT
 ; CHECK: br %r14
   ret void() *@pf
@@ -80,7 +80,7 @@ define void() *@f7() {
 
 ; ...likewise hidden functions.
 define void() *@f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: lgrl %r2, hf@GOT
 ; CHECK: br %r14
   ret void() *@hf
diff --git a/test/CodeGen/SystemZ/la-03.ll b/test/CodeGen/SystemZ/la-03.ll
index 9449b2b..1ff3fef 100644
--- a/test/CodeGen/SystemZ/la-03.ll
+++ b/test/CodeGen/SystemZ/la-03.ll
@@ -20,7 +20,7 @@ define hidden void @hf() {
 
 ; Test loads of external variables, which must go via the GOT.
 define i32 *@f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lgrl %r2, ev@GOT
 ; CHECK: br %r14
   ret i32 *@ev
@@ -29,7 +29,7 @@ define i32 *@f1() {
 ; Check loads of locally-defined normal-visibility variables, which might
 ; be overridden.  The load must go via the GOT.
 define i32 *@f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lgrl %r2, dv@GOT
 ; CHECK: br %r14
   ret i32 *@dv
@@ -38,7 +38,7 @@ define i32 *@f2() {
 ; Check loads of protected variables, which in the small code model
 ; must be in range of LARL.
 define i32 *@f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: larl %r2, pv
 ; CHECK: br %r14
   ret i32 *@pv
@@ -46,7 +46,7 @@ define i32 *@f3() {
 
 ; ...likewise hidden variables.
 define i32 *@f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: larl %r2, hv
 ; CHECK: br %r14
   ret i32 *@hv
@@ -54,7 +54,7 @@ define i32 *@f4() {
 
 ; Like f1, but for functions.
 define void() *@f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: lgrl %r2, ef@GOT
 ; CHECK: br %r14
   ret void() *@ef
@@ -62,7 +62,7 @@ define void() *@f5() {
 
 ; Like f2, but for functions.
 define void() *@f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: lgrl %r2, df@GOT
 ; CHECK: br %r14
   ret void() *@df
@@ -70,7 +70,7 @@ define void() *@f6() {
 
 ; Like f3, but for functions.
 define void() *@f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: larl %r2, pf
 ; CHECK: br %r14
   ret void() *@pf
@@ -78,7 +78,7 @@ define void() *@f7() {
 
 ; Like f4, but for functions.
 define void() *@f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: larl %r2, hf
 ; CHECK: br %r14
   ret void() *@hf
diff --git a/test/CodeGen/SystemZ/la-04.ll b/test/CodeGen/SystemZ/la-04.ll
index 4c36364..4d47308 100644
--- a/test/CodeGen/SystemZ/la-04.ll
+++ b/test/CodeGen/SystemZ/la-04.ll
@@ -4,7 +4,7 @@
 
 ; Do some arbitrary work and return the address of the following label.
 define i8 *@f1(i8 *%addr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvi 0(%r2), 1
 ; CHECK: [[LABEL:\.L.*]]:
 ; CHECK: larl %r2, [[LABEL]]
diff --git a/test/CodeGen/SystemZ/loop-01.ll b/test/CodeGen/SystemZ/loop-01.ll
new file mode 100644
index 0000000..5800801
--- /dev/null
+++ b/test/CodeGen/SystemZ/loop-01.ll
@@ -0,0 +1,124 @@
+; Test loop tuning.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+
+; Test that strength reduction is applied to addresses with a scale factor,
+; but that indexed addressing can still be used.
+define void @f1(i32 *%dest, i32 %a) {
+; CHECK-LABEL: f1:
+; CHECK-NOT: sllg
+; CHECK: st %r3, 0({{%r[1-5],%r[1-5]}})
+; CHECK: br %r14
+entry:
+  br label %loop
+
+loop:
+  %index = phi i64 [ 0, %entry ], [ %next, %loop ]
+  %ptr = getelementptr i32 *%dest, i64 %index
+  store i32 %a, i32 *%ptr
+  %next = add i64 %index, 1
+  %cmp = icmp ne i64 %next, 100
+  br i1 %cmp, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+; Test a loop that should be converted into dbr form and then use BRCT.
+define void @f2(i32 *%src, i32 *%dest) {
+; CHECK-LABEL: f2:
+; CHECK: lhi [[REG:%r[0-5]]], 100
+; CHECK: [[LABEL:\.[^:]*]]:{{.*}} %loop
+; CHECK: brct [[REG]], [[LABEL]]
+; CHECK: br %r14
+entry:
+  br label %loop
+
+loop:
+  %count = phi i32 [ 0, %entry ], [ %next, %loop.next ]
+  %next = add i32 %count, 1
+  %val = load volatile i32 *%src
+  %cmp = icmp eq i32 %val, 0
+  br i1 %cmp, label %loop.next, label %loop.store
+
+loop.store:
+  %add = add i32 %val, 1
+  store volatile i32 %add, i32 *%dest
+  br label %loop.next
+
+loop.next:
+  %cont = icmp ne i32 %next, 100
+  br i1 %cont, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+; Like f2, but for BRCTG.
+define void @f3(i64 *%src, i64 *%dest) {
+; CHECK-LABEL: f3:
+; CHECK: lghi [[REG:%r[0-5]]], 100
+; CHECK: [[LABEL:\.[^:]*]]:{{.*}} %loop
+; CHECK: brctg [[REG]], [[LABEL]]
+; CHECK: br %r14
+entry:
+  br label %loop
+
+loop:
+  %count = phi i64 [ 0, %entry ], [ %next, %loop.next ]
+  %next = add i64 %count, 1
+  %val = load volatile i64 *%src
+  %cmp = icmp eq i64 %val, 0
+  br i1 %cmp, label %loop.next, label %loop.store
+
+loop.store:
+  %add = add i64 %val, 1
+  store volatile i64 %add, i64 *%dest
+  br label %loop.next
+
+loop.next:
+  %cont = icmp ne i64 %next, 100
+  br i1 %cont, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+; Test a loop with a 64-bit decremented counter in which the 32-bit
+; low part of the counter is used after the decrement.  This is an example
+; of a subregister use being the only thing that blocks a conversion to BRCTG.
+define void @f4(i32 *%src, i32 *%dest, i64 *%dest2, i64 %count) {
+; CHECK-LABEL: f4:
+; CHECK: aghi [[REG:%r[0-5]]], -1
+; CHECK: lr [[REG2:%r[0-5]]], [[REG]]
+; CHECK: stg [[REG2]],
+; CHECK: jne {{\..*}}
+; CHECK: br %r14
+entry:
+  br label %loop
+
+loop:
+  %left = phi i64 [ %count, %entry ], [ %next, %loop.next ]
+  store volatile i64 %left, i64 *%dest2
+  %val = load volatile i32 *%src
+  %cmp = icmp eq i32 %val, 0
+  br i1 %cmp, label %loop.next, label %loop.store
+
+loop.store:
+  %add = add i32 %val, 1
+  store volatile i32 %add, i32 *%dest
+  br label %loop.next
+
+loop.next:
+  %next = add i64 %left, -1
+  %ext = zext i32 %val to i64
+  %shl = shl i64 %ext, 32
+  %and = and i64 %next, 4294967295
+  %or = or i64 %shl, %and
+  store volatile i64 %or, i64 *%dest2
+  %cont = icmp ne i64 %next, 0
+  br i1 %cont, label %loop, label %exit
+
+exit:
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/memcpy-01.ll b/test/CodeGen/SystemZ/memcpy-01.ll
new file mode 100644
index 0000000..7cb58b3
--- /dev/null
+++ b/test/CodeGen/SystemZ/memcpy-01.ll
@@ -0,0 +1,82 @@
+; Test memcpy using MVC.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8 *nocapture, i8 *nocapture, i32, i32, i1) nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8 *nocapture, i8 *nocapture, i64, i32, i1) nounwind
+
+define void @f1(i8 *%dest, i8 *%src) {
+; CHECK-LABEL: f1:
+; CHECK-NOT: %r2
+; CHECK-NOT: %r3
+; CHECK: br %r14
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8 *%dest, i8 *%src, i32 0, i32 1,
+                                       i1 false)
+  ret void
+}
+
+define void @f2(i8 *%dest, i8 *%src) {
+; CHECK-LABEL: f2:
+; CHECK-NOT: %r2
+; CHECK-NOT: %r3
+; CHECK: br %r14
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 0, i32 1,
+                                       i1 false)
+  ret void
+}
+
+define void @f3(i8 *%dest, i8 *%src) {
+; CHECK-LABEL: f3:
+; CHECK: mvc 0(1,%r2), 0(%r3)
+; CHECK: br %r14
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8 *%dest, i8 *%src, i32 1, i32 1,
+                                       i1 false)
+  ret void
+}
+
+define void @f4(i8 *%dest, i8 *%src) {
+; CHECK-LABEL: f4:
+; CHECK: mvc 0(1,%r2), 0(%r3)
+; CHECK: br %r14
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 1, i32 1,
+                                       i1 false)
+  ret void
+}
+
+define void @f5(i8 *%dest, i8 *%src) {
+; CHECK-LABEL: f5:
+; CHECK: mvc 0(256,%r2), 0(%r3)
+; CHECK: br %r14
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8 *%dest, i8 *%src, i32 256, i32 1,
+                                       i1 false)
+  ret void
+}
+
+define void @f6(i8 *%dest, i8 *%src) {
+; CHECK-LABEL: f6:
+; CHECK: mvc 0(256,%r2), 0(%r3)
+; CHECK: br %r14
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 256, i32 1,
+                                       i1 false)
+  ret void
+}
+
+; 257 bytes is too big for a single MVC.  For now expect none, so that
+; the test fails and gets updated when large copies are implemented.
+define void @f7(i8 *%dest, i8 *%src) {
+; CHECK-LABEL: f7:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8 *%dest, i8 *%src, i32 257, i32 1,
+                                       i1 false)
+  ret void
+}
+
+define void @f8(i8 *%dest, i8 *%src) {
+; CHECK-LABEL: f8:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 257, i32 1,
+                                       i1 false)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/memcpy-02.ll b/test/CodeGen/SystemZ/memcpy-02.ll
new file mode 100644
index 0000000..83b2cd8
--- /dev/null
+++ b/test/CodeGen/SystemZ/memcpy-02.ll
@@ -0,0 +1,417 @@
+; Test load/store pairs that act as memcpys.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+@g1 = global i8 1
+@g2 = global i16 2
+@g3 = global i32 3
+@g4 = global i64 4
+@g5 = external global fp128, align 16
+
+; Test the simple i8 case.
+define void @f1(i8 *%ptr1) {
+; CHECK-LABEL: f1:
+; CHECK: mvc 1(1,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr i8 *%ptr1, i64 1
+  %val = load i8 *%ptr1
+  store i8 %val, i8 *%ptr2
+  ret void
+}
+
+; Test i8 cases where the value is zero-extended to 32 bits.
+define void @f2(i8 *%ptr1) {
+; CHECK-LABEL: f2:
+; CHECK: mvc 1(1,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr i8 *%ptr1, i64 1
+  %val = load i8 *%ptr1
+  %ext = zext i8 %val to i32
+  %trunc = trunc i32 %ext to i8
+  store i8 %trunc, i8 *%ptr2
+  ret void
+}
+
+; Test i8 cases where the value is zero-extended to 64 bits.
+define void @f3(i8 *%ptr1) {
+; CHECK-LABEL: f3:
+; CHECK: mvc 1(1,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr i8 *%ptr1, i64 1
+  %val = load i8 *%ptr1
+  %ext = zext i8 %val to i64
+  %trunc = trunc i64 %ext to i8
+  store i8 %trunc, i8 *%ptr2
+  ret void
+}
+
+; Test i8 cases where the value is sign-extended to 32 bits.
+define void @f4(i8 *%ptr1) {
+; CHECK-LABEL: f4:
+; CHECK: mvc 1(1,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr i8 *%ptr1, i64 1
+  %val = load i8 *%ptr1
+  %ext = sext i8 %val to i32
+  %trunc = trunc i32 %ext to i8
+  store i8 %trunc, i8 *%ptr2
+  ret void
+}
+
+; Test i8 cases where the value is sign-extended to 64 bits.
+define void @f5(i8 *%ptr1) {
+; CHECK-LABEL: f5:
+; CHECK: mvc 1(1,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr i8 *%ptr1, i64 1
+  %val = load i8 *%ptr1
+  %ext = sext i8 %val to i64
+  %trunc = trunc i64 %ext to i8
+  store i8 %trunc, i8 *%ptr2
+  ret void
+}
+
+; Test the simple i16 case.
+define void @f6(i16 *%ptr1) {
+; CHECK-LABEL: f6:
+; CHECK: mvc 2(2,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr i16 *%ptr1, i64 1
+  %val = load i16 *%ptr1
+  store i16 %val, i16 *%ptr2
+  ret void
+}
+
+; Test i16 cases where the value is zero-extended to 32 bits.
+define void @f7(i16 *%ptr1) {
+; CHECK-LABEL: f7:
+; CHECK: mvc 2(2,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr i16 *%ptr1, i64 1
+  %val = load i16 *%ptr1
+  %ext = zext i16 %val to i32
+  %trunc = trunc i32 %ext to i16
+  store i16 %trunc, i16 *%ptr2
+  ret void
+}
+
+; Test i16 cases where the value is zero-extended to 64 bits.
+define void @f8(i16 *%ptr1) {
+; CHECK-LABEL: f8:
+; CHECK: mvc 2(2,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr i16 *%ptr1, i64 1
+  %val = load i16 *%ptr1
+  %ext = zext i16 %val to i64
+  %trunc = trunc i64 %ext to i16
+  store i16 %trunc, i16 *%ptr2
+  ret void
+}
+
+; Test i16 cases where the value is sign-extended to 32 bits.
+define void @f9(i16 *%ptr1) {
+; CHECK-LABEL: f9:
+; CHECK: mvc 2(2,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr i16 *%ptr1, i64 1
+  %val = load i16 *%ptr1
+  %ext = sext i16 %val to i32
+  %trunc = trunc i32 %ext to i16
+  store i16 %trunc, i16 *%ptr2
+  ret void
+}
+
+; Test i16 cases where the value is sign-extended to 64 bits.
+define void @f10(i16 *%ptr1) {
+; CHECK-LABEL: f10:
+; CHECK: mvc 2(2,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr i16 *%ptr1, i64 1
+  %val = load i16 *%ptr1
+  %ext = sext i16 %val to i64
+  %trunc = trunc i64 %ext to i16
+  store i16 %trunc, i16 *%ptr2
+  ret void
+}
+
+; Test the simple i32 case.
+define void @f11(i32 *%ptr1) {
+; CHECK-LABEL: f11:
+; CHECK: mvc 4(4,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr i32 *%ptr1, i64 1
+  %val = load i32 *%ptr1
+  store i32 %val, i32 *%ptr2
+  ret void
+}
+
+; Test i32 cases where the value is zero-extended to 64 bits.
+define void @f12(i32 *%ptr1) {
+; CHECK-LABEL: f12:
+; CHECK: mvc 4(4,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr i32 *%ptr1, i64 1
+  %val = load i32 *%ptr1
+  %ext = zext i32 %val to i64
+  %trunc = trunc i64 %ext to i32
+  store i32 %trunc, i32 *%ptr2
+  ret void
+}
+
+; Test i32 cases where the value is sign-extended to 64 bits.
+define void @f13(i32 *%ptr1) {
+; CHECK-LABEL: f13:
+; CHECK: mvc 4(4,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr i32 *%ptr1, i64 1
+  %val = load i32 *%ptr1
+  %ext = sext i32 %val to i64
+  %trunc = trunc i64 %ext to i32
+  store i32 %trunc, i32 *%ptr2
+  ret void
+}
+
+; Test the i64 case.
+define void @f14(i64 *%ptr1) {
+; CHECK-LABEL: f14:
+; CHECK: mvc 8(8,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr i64 *%ptr1, i64 1
+  %val = load i64 *%ptr1
+  store i64 %val, i64 *%ptr2
+  ret void
+}
+
+; Test the f32 case.
+define void @f15(float *%ptr1) {
+; CHECK-LABEL: f15:
+; CHECK: mvc 4(4,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr float *%ptr1, i64 1
+  %val = load float *%ptr1
+  store float %val, float *%ptr2
+  ret void
+}
+
+; Test the f64 case.
+define void @f16(double *%ptr1) {
+; CHECK-LABEL: f16:
+; CHECK: mvc 8(8,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr double *%ptr1, i64 1
+  %val = load double *%ptr1
+  store double %val, double *%ptr2
+  ret void
+}
+
+; Test the f128 case.
+define void @f17(fp128 *%ptr1) {
+; CHECK-LABEL: f17:
+; CHECK: mvc 16(16,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr fp128 *%ptr1, i64 1
+  %val = load fp128 *%ptr1
+  store fp128 %val, fp128 *%ptr2
+  ret void
+}
+
+; Make sure that we don't use MVC if the load is volatile.
+define void @f18(i64 *%ptr1) {
+; CHECK-LABEL: f18:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  %ptr2 = getelementptr i64 *%ptr1, i64 1
+  %val = load volatile i64 *%ptr1
+  store i64 %val, i64 *%ptr2
+  ret void
+}
+
+; ...likewise the store.
+define void @f19(i64 *%ptr1) {
+; CHECK-LABEL: f19:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  %ptr2 = getelementptr i64 *%ptr1, i64 1
+  %val = load i64 *%ptr1
+  store volatile i64 %val, i64 *%ptr2
+  ret void
+}
+
+; Test that MVC is used for aligned loads and stores, even if there is
+; no way of telling whether they alias.
+define void @f20(i64 *%ptr1, i64 *%ptr2) {
+; CHECK-LABEL: f20:
+; CHECK: mvc 0(8,%r3), 0(%r2)
+; CHECK: br %r14
+  %val = load i64 *%ptr1
+  store i64 %val, i64 *%ptr2
+  ret void
+}
+
+; ...but if the loads aren't aligned, we can't be sure.
+define void @f21(i64 *%ptr1, i64 *%ptr2) {
+; CHECK-LABEL: f21:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  %val = load i64 *%ptr1, align 2
+  store i64 %val, i64 *%ptr2, align 2
+  ret void
+}
+
+; Test a case where there is definite overlap.
+define void @f22(i64 %base) {
+; CHECK-LABEL: f22:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  %add = add i64 %base, 1
+  %ptr1 = inttoptr i64 %base to i64 *
+  %ptr2 = inttoptr i64 %add to i64 *
+  %val = load i64 *%ptr1, align 1
+  store i64 %val, i64 *%ptr2, align 1
+  ret void
+}
+
+; Test that we can use MVC for global addresses for i8.
+define void @f23(i8 *%ptr) {
+; CHECK-LABEL: f23:
+; CHECK: larl [[REG:%r[0-5]]], g1
+; CHECK: mvc 0(1,%r2), 0([[REG]])
+; CHECK: br %r14
+  %val = load i8 *@g1
+  store i8 %val, i8 *%ptr
+  ret void
+}
+
+; ...and again with the global on the store.
+define void @f24(i8 *%ptr) {
+; CHECK-LABEL: f24:
+; CHECK: larl [[REG:%r[0-5]]], g1
+; CHECK: mvc 0(1,[[REG]]), 0(%r2)
+; CHECK: br %r14
+  %val = load i8 *%ptr
+  store i8 %val, i8 *@g1
+  ret void
+}
+
+; Test that we use LHRL for i16.
+define void @f25(i16 *%ptr) {
+; CHECK-LABEL: f25:
+; CHECK: lhrl [[REG:%r[0-5]]], g2
+; CHECK: sth [[REG]], 0(%r2)
+; CHECK: br %r14
+  %val = load i16 *@g2
+  store i16 %val, i16 *%ptr
+  ret void
+}
+
+; ...likewise STHRL.
+define void @f26(i16 *%ptr) {
+; CHECK-LABEL: f26:
+; CHECK: lh [[REG:%r[0-5]]], 0(%r2)
+; CHECK: sthrl [[REG]], g2
+; CHECK: br %r14
+  %val = load i16 *%ptr
+  store i16 %val, i16 *@g2
+  ret void
+}
+
+; Test that we use LRL for i32.
+define void @f27(i32 *%ptr) {
+; CHECK-LABEL: f27:
+; CHECK: lrl [[REG:%r[0-5]]], g3
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  %val = load i32 *@g3
+  store i32 %val, i32 *%ptr
+  ret void
+}
+
+; ...likewise STRL.
+define void @f28(i32 *%ptr) {
+; CHECK-LABEL: f28:
+; CHECK: l [[REG:%r[0-5]]], 0(%r2)
+; CHECK: strl [[REG]], g3
+; CHECK: br %r14
+  %val = load i32 *%ptr
+  store i32 %val, i32 *@g3
+  ret void
+}
+
+; Test that we use LGRL for i64.
+define void @f29(i64 *%ptr) {
+; CHECK-LABEL: f29:
+; CHECK: lgrl [[REG:%r[0-5]]], g4
+; CHECK: stg [[REG]], 0(%r2)
+; CHECK: br %r14
+  %val = load i64 *@g4
+  store i64 %val, i64 *%ptr
+  ret void
+}
+
+; ...likewise STGRL.
+define void @f30(i64 *%ptr) {
+; CHECK-LABEL: f30:
+; CHECK: lg [[REG:%r[0-5]]], 0(%r2)
+; CHECK: stgrl [[REG]], g4
+; CHECK: br %r14
+  %val = load i64 *%ptr
+  store i64 %val, i64 *@g4
+  ret void
+}
+
+; Test that we can use MVC for global addresses for fp128.
+define void @f31(fp128 *%ptr) {
+; CHECK-LABEL: f31:
+; CHECK: larl [[REG:%r[0-5]]], g5
+; CHECK: mvc 0(16,%r2), 0([[REG]])
+; CHECK: br %r14
+  %val = load fp128 *@g5, align 16
+  store fp128 %val, fp128 *%ptr, align 16
+  ret void
+}
+
+; ...and again with the global on the store.
+define void @f32(fp128 *%ptr) {
+; CHECK-LABEL: f32:
+; CHECK: larl [[REG:%r[0-5]]], g5
+; CHECK: mvc 0(16,[[REG]]), 0(%r2)
+; CHECK: br %r14
+  %val = load fp128 *%ptr, align 16
+  store fp128 %val, fp128 *@g5, align 16
+  ret void
+}
+
+; Test a case where offset disambiguation is enough.
+define void @f33(i64 *%ptr1) {
+; CHECK-LABEL: f33:
+; CHECK: mvc 8(8,%r2), 0(%r2)
+; CHECK: br %r14
+  %ptr2 = getelementptr i64 *%ptr1, i64 1
+  %val = load i64 *%ptr1, align 1
+  store i64 %val, i64 *%ptr2, align 1
+  ret void
+}
+
+; Test f21 in cases where TBAA tells us there is no alias.
+define void @f34(i64 *%ptr1, i64 *%ptr2) {
+; CHECK-LABEL: f34:
+; CHECK: mvc 0(8,%r3), 0(%r2)
+; CHECK: br %r14
+  %val = load i64 *%ptr1, align 2, !tbaa !1
+  store i64 %val, i64 *%ptr2, align 2, !tbaa !2
+  ret void
+}
+
+; Test f21 in cases where TBAA is present but doesn't help.
+define void @f35(i64 *%ptr1, i64 *%ptr2) {
+; CHECK-LABEL: f35:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  %val = load i64 *%ptr1, align 2, !tbaa !1
+  store i64 %val, i64 *%ptr2, align 2, !tbaa !1
+  ret void
+}
+
+!0 = metadata !{ metadata !"root" }
+!1 = metadata !{ metadata !"set1", metadata !0 }
+!2 = metadata !{ metadata !"set2", metadata !0 }
diff --git a/test/CodeGen/SystemZ/memset-01.ll b/test/CodeGen/SystemZ/memset-01.ll
new file mode 100644
index 0000000..b272a5b
--- /dev/null
+++ b/test/CodeGen/SystemZ/memset-01.ll
@@ -0,0 +1,124 @@
+; Test memset in cases where the set value is variable.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare void @llvm.memset.p0i8.i32(i8 *nocapture, i8, i32, i32, i1) nounwind
+declare void @llvm.memset.p0i8.i64(i8 *nocapture, i8, i64, i32, i1) nounwind
+
+; No bytes, i32 version.
+define void @f1(i8 *%dest, i8 %val) {
+; CHECK-LABEL: f1:
+; CHECK-NOT: %r2
+; CHECK-NOT: %r3
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 %val, i32 0, i32 1, i1 false)
+  ret void
+}
+
+; No bytes, i64 version.
+define void @f2(i8 *%dest, i8 %val) {
+; CHECK-LABEL: f2:
+; CHECK-NOT: %r2
+; CHECK-NOT: %r3
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 %val, i64 0, i32 1, i1 false)
+  ret void
+}
+
+; 1 byte, i32 version.
+define void @f3(i8 *%dest, i8 %val) {
+; CHECK-LABEL: f3:
+; CHECK: stc %r3, 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 %val, i32 1, i32 1, i1 false)
+  ret void
+}
+
+; 1 byte, i64 version.
+define void @f4(i8 *%dest, i8 %val) {
+; CHECK-LABEL: f4:
+; CHECK: stc %r3, 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 %val, i64 1, i32 1, i1 false)
+  ret void
+}
+
+; 2 bytes, i32 version.
+define void @f5(i8 *%dest, i8 %val) {
+; CHECK-LABEL: f5:
+; CHECK-DAG: stc %r3, 0(%r2)
+; CHECK-DAG: stc %r3, 1(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 %val, i32 2, i32 1, i1 false)
+  ret void
+}
+
+; 2 bytes, i64 version.
+define void @f6(i8 *%dest, i8 %val) {
+; CHECK-LABEL: f6:
+; CHECK-DAG: stc %r3, 0(%r2)
+; CHECK-DAG: stc %r3, 1(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 %val, i64 2, i32 1, i1 false)
+  ret void
+}
+
+; 3 bytes, i32 version.
+define void @f7(i8 *%dest, i8 %val) {
+; CHECK-LABEL: f7:
+; CHECK: stc %r3, 0(%r2)
+; CHECK: mvc 1(2,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 %val, i32 3, i32 1, i1 false)
+  ret void
+}
+
+; 3 bytes, i64 version.
+define void @f8(i8 *%dest, i8 %val) {
+; CHECK-LABEL: f8:
+; CHECK: stc %r3, 0(%r2)
+; CHECK: mvc 1(2,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 %val, i64 3, i32 1, i1 false)
+  ret void
+}
+
+; 257 bytes, i32 version.
+define void @f9(i8 *%dest, i8 %val) {
+; CHECK-LABEL: f9:
+; CHECK: stc %r3, 0(%r2)
+; CHECK: mvc 1(256,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 %val, i32 257, i32 1, i1 false)
+  ret void
+}
+
+; 257 bytes, i64 version.
+define void @f10(i8 *%dest, i8 %val) {
+; CHECK-LABEL: f10:
+; CHECK: stc %r3, 0(%r2)
+; CHECK: mvc 1(256,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 %val, i64 257, i32 1, i1 false)
+  ret void
+}
+
+; 258 bytes, i32 version.  258 bytes is too big for a single MVC.
+; For now expect none, so that the test fails and gets updated when
+; large copies are implemented.
+define void @f11(i8 *%dest, i8 %val) {
+; CHECK-LABEL: f11:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 %val, i32 258, i32 1, i1 false)
+  ret void
+}
+
+; 258 bytes, i64 version, with the same comments as above.
+define void @f12(i8 *%dest, i8 %val) {
+; CHECK-LABEL: f12:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 %val, i64 258, i32 1, i1 false)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/memset-02.ll b/test/CodeGen/SystemZ/memset-02.ll
new file mode 100644
index 0000000..b74d907
--- /dev/null
+++ b/test/CodeGen/SystemZ/memset-02.ll
@@ -0,0 +1,160 @@
+; Test memset in cases where the set value is a constant other than 0 and -1.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare void @llvm.memset.p0i8.i32(i8 *nocapture, i8, i32, i32, i1) nounwind
+declare void @llvm.memset.p0i8.i64(i8 *nocapture, i8, i64, i32, i1) nounwind
+
+; No bytes, i32 version.
+define void @f1(i8 *%dest) {
+; CHECK-LABEL: f1:
+; CHECK-NOT: %r2
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 0, i32 1, i1 false)
+  ret void
+}
+
+; No bytes, i64 version.
+define void @f2(i8 *%dest) {
+; CHECK-LABEL: f2:
+; CHECK-NOT: %r2
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 0, i32 1, i1 false)
+  ret void
+}
+
+; 1 byte, i32 version.
+define void @f3(i8 *%dest) {
+; CHECK-LABEL: f3:
+; CHECK: mvi 0(%r2), 128
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 1, i32 1, i1 false)
+  ret void
+}
+
+; 1 byte, i64 version.
+define void @f4(i8 *%dest) {
+; CHECK-LABEL: f4:
+; CHECK: mvi 0(%r2), 128
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 1, i32 1, i1 false)
+  ret void
+}
+
+; 2 bytes, i32 version.
+define void @f5(i8 *%dest) {
+; CHECK-LABEL: f5:
+; CHECK: mvhhi 0(%r2), -32640
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 2, i32 1, i1 false)
+  ret void
+}
+
+; 2 bytes, i64 version.
+define void @f6(i8 *%dest) {
+; CHECK-LABEL: f6:
+; CHECK: mvhhi 0(%r2), -32640
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 2, i32 1, i1 false)
+  ret void
+}
+
+; 3 bytes, i32 version.
+define void @f7(i8 *%dest) {
+; CHECK-LABEL: f7:
+; CHECK-DAG: mvhhi 0(%r2), -32640
+; CHECK-DAG: mvi 2(%r2), 128
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 3, i32 1, i1 false)
+  ret void
+}
+
+; 3 bytes, i64 version.
+define void @f8(i8 *%dest) {
+; CHECK-LABEL: f8:
+; CHECK-DAG: mvhhi 0(%r2), -32640
+; CHECK-DAG: mvi 2(%r2), 128
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 3, i32 1, i1 false)
+  ret void
+}
+
+; 4 bytes, i32 version.
+define void @f9(i8 *%dest) {
+; CHECK-LABEL: f9:
+; CHECK: iilf [[REG:%r[0-5]]], 2155905152
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 4, i32 1, i1 false)
+  ret void
+}
+
+; 4 bytes, i64 version.
+define void @f10(i8 *%dest) {
+; CHECK-LABEL: f10:
+; CHECK: iilf [[REG:%r[0-5]]], 2155905152
+; CHECK: st [[REG]], 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 4, i32 1, i1 false)
+  ret void
+}
+
+; 5 bytes, i32 version.
+define void @f11(i8 *%dest) {
+; CHECK-LABEL: f11:
+; CHECK: mvi 0(%r2), 128
+; CHECK: mvc 1(4,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 5, i32 1, i1 false)
+  ret void
+}
+
+; 5 bytes, i64 version.
+define void @f12(i8 *%dest) {
+; CHECK-LABEL: f12:
+; CHECK: mvi 0(%r2), 128
+; CHECK: mvc 1(4,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 5, i32 1, i1 false)
+  ret void
+}
+
+; 257 bytes, i32 version.
+define void @f13(i8 *%dest) {
+; CHECK-LABEL: f13:
+; CHECK: mvi 0(%r2), 128
+; CHECK: mvc 1(256,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 257, i32 1, i1 false)
+  ret void
+}
+
+; 257 bytes, i64 version.
+define void @f14(i8 *%dest) {
+; CHECK-LABEL: f14:
+; CHECK: mvi 0(%r2), 128
+; CHECK: mvc 1(256,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 257, i32 1, i1 false)
+  ret void
+}
+
+; 258 bytes, i32 version.  258 bytes is too big for a single MVC.
+; For now expect none, so that the test fails and gets updated when
+; large copies are implemented.
+define void @f15(i8 *%dest) {
+; CHECK-LABEL: f15:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 258, i32 1, i1 false)
+  ret void
+}
+
+; 258 bytes, i64 version, with the same comments as above.
+define void @f16(i8 *%dest) {
+; CHECK-LABEL: f16:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 258, i32 1, i1 false)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/memset-03.ll b/test/CodeGen/SystemZ/memset-03.ll
new file mode 100644
index 0000000..1d48f1a
--- /dev/null
+++ b/test/CodeGen/SystemZ/memset-03.ll
@@ -0,0 +1,396 @@
+; Test memsets that clear all bits.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare void @llvm.memset.p0i8.i32(i8 *nocapture, i8, i32, i32, i1) nounwind
+declare void @llvm.memset.p0i8.i64(i8 *nocapture, i8, i64, i32, i1) nounwind
+
+; No bytes, i32 version.
+define void @f1(i8 *%dest) {
+; CHECK-LABEL: f1:
+; CHECK-NOT: %r2
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 0, i32 1, i1 false)
+  ret void
+}
+
+; No bytes, i64 version.
+define void @f2(i8 *%dest) {
+; CHECK-LABEL: f2:
+; CHECK-NOT: %r2
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 0, i32 1, i1 false)
+  ret void
+}
+
+; 1 byte, i32 version.
+define void @f3(i8 *%dest) {
+; CHECK-LABEL: f3:
+; CHECK: mvi 0(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 1, i32 1, i1 false)
+  ret void
+}
+
+; 1 byte, i64 version.
+define void @f4(i8 *%dest) {
+; CHECK-LABEL: f4:
+; CHECK: mvi 0(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 1, i32 1, i1 false)
+  ret void
+}
+
+; 2 bytes, i32 version.
+define void @f5(i8 *%dest) {
+; CHECK-LABEL: f5:
+; CHECK: mvhhi 0(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 2, i32 1, i1 false)
+  ret void
+}
+
+; 2 bytes, i64 version.
+define void @f6(i8 *%dest) {
+; CHECK-LABEL: f6:
+; CHECK: mvhhi 0(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 2, i32 1, i1 false)
+  ret void
+}
+
+; 3 bytes, i32 version.
+define void @f7(i8 *%dest) {
+; CHECK-LABEL: f7:
+; CHECK-DAG: mvhhi 0(%r2), 0
+; CHECK-DAG: mvi 2(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 3, i32 1, i1 false)
+  ret void
+}
+
+; 3 bytes, i64 version.
+define void @f8(i8 *%dest) {
+; CHECK-LABEL: f8:
+; CHECK-DAG: mvhhi 0(%r2), 0
+; CHECK-DAG: mvi 2(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 3, i32 1, i1 false)
+  ret void
+}
+
+; 4 bytes, i32 version.
+define void @f9(i8 *%dest) {
+; CHECK-LABEL: f9:
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 4, i32 1, i1 false)
+  ret void
+}
+
+; 4 bytes, i64 version.
+define void @f10(i8 *%dest) {
+; CHECK-LABEL: f10:
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 4, i32 1, i1 false)
+  ret void
+}
+
+; 5 bytes, i32 version.
+define void @f11(i8 *%dest) {
+; CHECK-LABEL: f11:
+; CHECK-DAG: mvhi 0(%r2), 0
+; CHECK-DAG: mvi 4(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 5, i32 1, i1 false)
+  ret void
+}
+
+; 5 bytes, i64 version.
+define void @f12(i8 *%dest) {
+; CHECK-LABEL: f12:
+; CHECK-DAG: mvhi 0(%r2), 0
+; CHECK-DAG: mvi 4(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 5, i32 1, i1 false)
+  ret void
+}
+
+; 6 bytes, i32 version.
+define void @f13(i8 *%dest) {
+; CHECK-LABEL: f13:
+; CHECK-DAG: mvhi 0(%r2), 0
+; CHECK-DAG: mvhhi 4(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 6, i32 1, i1 false)
+  ret void
+}
+
+; 6 bytes, i64 version.
+define void @f14(i8 *%dest) {
+; CHECK-LABEL: f14:
+; CHECK-DAG: mvhi 0(%r2), 0
+; CHECK-DAG: mvhhi 4(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 6, i32 1, i1 false)
+  ret void
+}
+
+; 7 bytes, i32 version.
+define void @f15(i8 *%dest) {
+; CHECK-LABEL: f15:
+; CHECK: mvi 0(%r2), 0
+; CHECK: mvc 1(6,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 7, i32 1, i1 false)
+  ret void
+}
+
+; 7 bytes, i64 version.
+define void @f16(i8 *%dest) {
+; CHECK-LABEL: f16:
+; CHECK: mvi 0(%r2), 0
+; CHECK: mvc 1(6,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 7, i32 1, i1 false)
+  ret void
+}
+
+; 8 bytes, i32 version.
+define void @f17(i8 *%dest) {
+; CHECK-LABEL: f17:
+; CHECK: mvghi 0(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 8, i32 1, i1 false)
+  ret void
+}
+
+; 8 bytes, i64 version.
+define void @f18(i8 *%dest) {
+; CHECK-LABEL: f18:
+; CHECK: mvghi 0(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 8, i32 1, i1 false)
+  ret void
+}
+
+; 9 bytes, i32 version.
+define void @f19(i8 *%dest) {
+; CHECK-LABEL: f19:
+; CHECK-DAG: mvghi 0(%r2), 0
+; CHECK-DAG: mvi 8(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 9, i32 1, i1 false)
+  ret void
+}
+
+; 9 bytes, i64 version.
+define void @f20(i8 *%dest) {
+; CHECK-LABEL: f20:
+; CHECK-DAG: mvghi 0(%r2), 0
+; CHECK-DAG: mvi 8(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 9, i32 1, i1 false)
+  ret void
+}
+
+; 10 bytes, i32 version.
+define void @f21(i8 *%dest) {
+; CHECK-LABEL: f21:
+; CHECK-DAG: mvghi 0(%r2), 0
+; CHECK-DAG: mvhhi 8(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 10, i32 1, i1 false)
+  ret void
+}
+
+; 10 bytes, i64 version.
+define void @f22(i8 *%dest) {
+; CHECK-LABEL: f22:
+; CHECK-DAG: mvghi 0(%r2), 0
+; CHECK-DAG: mvhhi 8(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 10, i32 1, i1 false)
+  ret void
+}
+
+; 11 bytes, i32 version.
+define void @f23(i8 *%dest) {
+; CHECK-LABEL: f23:
+; CHECK: mvi 0(%r2), 0
+; CHECK: mvc 1(10,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 11, i32 1, i1 false)
+  ret void
+}
+
+; 11 bytes, i64 version.
+define void @f24(i8 *%dest) {
+; CHECK-LABEL: f24:
+; CHECK: mvi 0(%r2), 0
+; CHECK: mvc 1(10,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 11, i32 1, i1 false)
+  ret void
+}
+
+; 12 bytes, i32 version.
+define void @f25(i8 *%dest) {
+; CHECK-LABEL: f25:
+; CHECK-DAG: mvghi 0(%r2), 0
+; CHECK-DAG: mvhi 8(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 12, i32 1, i1 false)
+  ret void
+}
+
+; 12 bytes, i64 version.
+define void @f26(i8 *%dest) {
+; CHECK-LABEL: f26:
+; CHECK-DAG: mvghi 0(%r2), 0
+; CHECK-DAG: mvhi 8(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 12, i32 1, i1 false)
+  ret void
+}
+
+; 13 bytes, i32 version.
+define void @f27(i8 *%dest) {
+; CHECK-LABEL: f27:
+; CHECK: mvi 0(%r2), 0
+; CHECK: mvc 1(12,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 13, i32 1, i1 false)
+  ret void
+}
+
+; 13 bytes, i64 version.
+define void @f28(i8 *%dest) {
+; CHECK-LABEL: f28:
+; CHECK: mvi 0(%r2), 0
+; CHECK: mvc 1(12,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 13, i32 1, i1 false)
+  ret void
+}
+
+; 14 bytes, i32 version.
+define void @f29(i8 *%dest) {
+; CHECK-LABEL: f29:
+; CHECK: mvi 0(%r2), 0
+; CHECK: mvc 1(13,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 14, i32 1, i1 false)
+  ret void
+}
+
+; 14 bytes, i64 version.
+define void @f30(i8 *%dest) {
+; CHECK-LABEL: f30:
+; CHECK: mvi 0(%r2), 0
+; CHECK: mvc 1(13,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 14, i32 1, i1 false)
+  ret void
+}
+
+; 15 bytes, i32 version.
+define void @f31(i8 *%dest) {
+; CHECK-LABEL: f31:
+; CHECK: mvi 0(%r2), 0
+; CHECK: mvc 1(14,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 15, i32 1, i1 false)
+  ret void
+}
+
+; 15 bytes, i64 version.
+define void @f32(i8 *%dest) {
+; CHECK-LABEL: f32:
+; CHECK: mvi 0(%r2), 0
+; CHECK: mvc 1(14,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 15, i32 1, i1 false)
+  ret void
+}
+
+; 16 bytes, i32 version.
+define void @f33(i8 *%dest) {
+; CHECK-LABEL: f33:
+; CHECK-DAG: mvghi 0(%r2), 0
+; CHECK-DAG: mvghi 8(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 16, i32 1, i1 false)
+  ret void
+}
+
+; 16 bytes, i64 version.
+define void @f34(i8 *%dest) {
+; CHECK-LABEL: f34:
+; CHECK-DAG: mvghi 0(%r2), 0
+; CHECK-DAG: mvghi 8(%r2), 0
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 16, i32 1, i1 false)
+  ret void
+}
+
+; 17 bytes, i32 version.
+define void @f35(i8 *%dest) {
+; CHECK-LABEL: f35:
+; CHECK: mvi 0(%r2), 0
+; CHECK: mvc 1(16,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 17, i32 1, i1 false)
+  ret void
+}
+
+; 17 bytes, i64 version.
+define void @f36(i8 *%dest) {
+; CHECK-LABEL: f36:
+; CHECK: mvi 0(%r2), 0
+; CHECK: mvc 1(16,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 17, i32 1, i1 false)
+  ret void
+}
+
+; 257 bytes, i32 version.
+define void @f37(i8 *%dest) {
+; CHECK-LABEL: f37:
+; CHECK: mvi 0(%r2), 0
+; CHECK: mvc 1(256,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 257, i32 1, i1 false)
+  ret void
+}
+
+; 257 bytes, i64 version.
+define void @f38(i8 *%dest) {
+; CHECK-LABEL: f38:
+; CHECK: mvi 0(%r2), 0
+; CHECK: mvc 1(256,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 257, i32 1, i1 false)
+  ret void
+}
+
+; 258 bytes, i32 version.  258 bytes is too big for a single MVC.
+; For now expect none, so that the test fails and gets updated when
+; large copies are implemented.
+define void @f39(i8 *%dest) {
+; CHECK-LABEL: f39:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 258, i32 1, i1 false)
+  ret void
+}
+
+; 258 bytes, i64 version, with the same comments as above.
+define void @f40(i8 *%dest) {
+; CHECK-LABEL: f40:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 258, i32 1, i1 false)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/memset-04.ll b/test/CodeGen/SystemZ/memset-04.ll
new file mode 100644
index 0000000..9288692
--- /dev/null
+++ b/test/CodeGen/SystemZ/memset-04.ll
@@ -0,0 +1,396 @@
+; Test memsets that set all bits.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare void @llvm.memset.p0i8.i32(i8 *nocapture, i8, i32, i32, i1) nounwind
+declare void @llvm.memset.p0i8.i64(i8 *nocapture, i8, i64, i32, i1) nounwind
+
+; No bytes, i32 version.
+define void @f1(i8 *%dest) {
+; CHECK-LABEL: f1:
+; CHECK-NOT: %r2
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 0, i32 1, i1 false)
+  ret void
+}
+
+; No bytes, i64 version.
+define void @f2(i8 *%dest) {
+; CHECK-LABEL: f2:
+; CHECK-NOT: %r2
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 0, i32 1, i1 false)
+  ret void
+}
+
+; 1 byte, i32 version.
+define void @f3(i8 *%dest) {
+; CHECK-LABEL: f3:
+; CHECK: mvi 0(%r2), 255
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 1, i32 1, i1 false)
+  ret void
+}
+
+; 1 byte, i64 version.
+define void @f4(i8 *%dest) {
+; CHECK-LABEL: f4:
+; CHECK: mvi 0(%r2), 255
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 1, i32 1, i1 false)
+  ret void
+}
+
+; 2 bytes, i32 version.
+define void @f5(i8 *%dest) {
+; CHECK-LABEL: f5:
+; CHECK: mvhhi 0(%r2), -1
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 2, i32 1, i1 false)
+  ret void
+}
+
+; 2 bytes, i64 version.
+define void @f6(i8 *%dest) {
+; CHECK-LABEL: f6:
+; CHECK: mvhhi 0(%r2), -1
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 2, i32 1, i1 false)
+  ret void
+}
+
+; 3 bytes, i32 version.
+define void @f7(i8 *%dest) {
+; CHECK-LABEL: f7:
+; CHECK-DAG: mvhhi 0(%r2), -1
+; CHECK-DAG: mvi 2(%r2), 255
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 3, i32 1, i1 false)
+  ret void
+}
+
+; 3 bytes, i64 version.
+define void @f8(i8 *%dest) {
+; CHECK-LABEL: f8:
+; CHECK-DAG: mvhhi 0(%r2), -1
+; CHECK-DAG: mvi 2(%r2), 255
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 3, i32 1, i1 false)
+  ret void
+}
+
+; 4 bytes, i32 version.
+define void @f9(i8 *%dest) {
+; CHECK-LABEL: f9:
+; CHECK: mvhi 0(%r2), -1
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 4, i32 1, i1 false)
+  ret void
+}
+
+; 4 bytes, i64 version.
+define void @f10(i8 *%dest) {
+; CHECK-LABEL: f10:
+; CHECK: mvhi 0(%r2), -1
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 4, i32 1, i1 false)
+  ret void
+}
+
+; 5 bytes, i32 version.
+define void @f11(i8 *%dest) {
+; CHECK-LABEL: f11:
+; CHECK-DAG: mvhi 0(%r2), -1
+; CHECK-DAG: mvi 4(%r2), 255
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 5, i32 1, i1 false)
+  ret void
+}
+
+; 5 bytes, i64 version.
+define void @f12(i8 *%dest) {
+; CHECK-LABEL: f12:
+; CHECK-DAG: mvhi 0(%r2), -1
+; CHECK-DAG: mvi 4(%r2), 255
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 5, i32 1, i1 false)
+  ret void
+}
+
+; 6 bytes, i32 version.
+define void @f13(i8 *%dest) {
+; CHECK-LABEL: f13:
+; CHECK-DAG: mvhi 0(%r2), -1
+; CHECK-DAG: mvhhi 4(%r2), -1
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 6, i32 1, i1 false)
+  ret void
+}
+
+; 6 bytes, i64 version.
+define void @f14(i8 *%dest) {
+; CHECK-LABEL: f14:
+; CHECK-DAG: mvhi 0(%r2), -1
+; CHECK-DAG: mvhhi 4(%r2), -1
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 6, i32 1, i1 false)
+  ret void
+}
+
+; 7 bytes, i32 version.
+define void @f15(i8 *%dest) {
+; CHECK-LABEL: f15:
+; CHECK: mvi 0(%r2), 255
+; CHECK: mvc 1(6,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 7, i32 1, i1 false)
+  ret void
+}
+
+; 7 bytes, i64 version.
+define void @f16(i8 *%dest) {
+; CHECK-LABEL: f16:
+; CHECK: mvi 0(%r2), 255
+; CHECK: mvc 1(6,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 7, i32 1, i1 false)
+  ret void
+}
+
+; 8 bytes, i32 version.
+define void @f17(i8 *%dest) {
+; CHECK-LABEL: f17:
+; CHECK: mvghi 0(%r2), -1
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 8, i32 1, i1 false)
+  ret void
+}
+
+; 8 bytes, i64 version.
+define void @f18(i8 *%dest) {
+; CHECK-LABEL: f18:
+; CHECK: mvghi 0(%r2), -1
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 8, i32 1, i1 false)
+  ret void
+}
+
+; 9 bytes, i32 version.
+define void @f19(i8 *%dest) {
+; CHECK-LABEL: f19:
+; CHECK-DAG: mvghi 0(%r2), -1
+; CHECK-DAG: mvi 8(%r2), 255
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 9, i32 1, i1 false)
+  ret void
+}
+
+; 9 bytes, i64 version.
+define void @f20(i8 *%dest) {
+; CHECK-LABEL: f20:
+; CHECK-DAG: mvghi 0(%r2), -1
+; CHECK-DAG: mvi 8(%r2), 255
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 9, i32 1, i1 false)
+  ret void
+}
+
+; 10 bytes, i32 version.
+define void @f21(i8 *%dest) {
+; CHECK-LABEL: f21:
+; CHECK-DAG: mvghi 0(%r2), -1
+; CHECK-DAG: mvhhi 8(%r2), -1
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 10, i32 1, i1 false)
+  ret void
+}
+
+; 10 bytes, i64 version.
+define void @f22(i8 *%dest) {
+; CHECK-LABEL: f22:
+; CHECK-DAG: mvghi 0(%r2), -1
+; CHECK-DAG: mvhhi 8(%r2), -1
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 10, i32 1, i1 false)
+  ret void
+}
+
+; 11 bytes, i32 version.
+define void @f23(i8 *%dest) {
+; CHECK-LABEL: f23:
+; CHECK: mvi 0(%r2), 255
+; CHECK: mvc 1(10,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 11, i32 1, i1 false)
+  ret void
+}
+
+; 11 bytes, i64 version.
+define void @f24(i8 *%dest) {
+; CHECK-LABEL: f24:
+; CHECK: mvi 0(%r2), 255
+; CHECK: mvc 1(10,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 11, i32 1, i1 false)
+  ret void
+}
+
+; 12 bytes, i32 version.
+define void @f25(i8 *%dest) {
+; CHECK-LABEL: f25:
+; CHECK-DAG: mvghi 0(%r2), -1
+; CHECK-DAG: mvhi 8(%r2), -1
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 12, i32 1, i1 false)
+  ret void
+}
+
+; 12 bytes, i64 version.
+define void @f26(i8 *%dest) {
+; CHECK-LABEL: f26:
+; CHECK-DAG: mvghi 0(%r2), -1
+; CHECK-DAG: mvhi 8(%r2), -1
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 12, i32 1, i1 false)
+  ret void
+}
+
+; 13 bytes, i32 version.
+define void @f27(i8 *%dest) {
+; CHECK-LABEL: f27:
+; CHECK: mvi 0(%r2), 255
+; CHECK: mvc 1(12,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 13, i32 1, i1 false)
+  ret void
+}
+
+; 13 bytes, i64 version.
+define void @f28(i8 *%dest) {
+; CHECK-LABEL: f28:
+; CHECK: mvi 0(%r2), 255
+; CHECK: mvc 1(12,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 13, i32 1, i1 false)
+  ret void
+}
+
+; 14 bytes, i32 version.
+define void @f29(i8 *%dest) {
+; CHECK-LABEL: f29:
+; CHECK: mvi 0(%r2), 255
+; CHECK: mvc 1(13,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 14, i32 1, i1 false)
+  ret void
+}
+
+; 14 bytes, i64 version.
+define void @f30(i8 *%dest) {
+; CHECK-LABEL: f30:
+; CHECK: mvi 0(%r2), 255
+; CHECK: mvc 1(13,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 14, i32 1, i1 false)
+  ret void
+}
+
+; 15 bytes, i32 version.
+define void @f31(i8 *%dest) {
+; CHECK-LABEL: f31:
+; CHECK: mvi 0(%r2), 255
+; CHECK: mvc 1(14,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 15, i32 1, i1 false)
+  ret void
+}
+
+; 15 bytes, i64 version.
+define void @f32(i8 *%dest) {
+; CHECK-LABEL: f32:
+; CHECK: mvi 0(%r2), 255
+; CHECK: mvc 1(14,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 15, i32 1, i1 false)
+  ret void
+}
+
+; 16 bytes, i32 version.
+define void @f33(i8 *%dest) {
+; CHECK-LABEL: f33:
+; CHECK-DAG: mvghi 0(%r2), -1
+; CHECK-DAG: mvghi 8(%r2), -1
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 16, i32 1, i1 false)
+  ret void
+}
+
+; 16 bytes, i64 version.
+define void @f34(i8 *%dest) {
+; CHECK-LABEL: f34:
+; CHECK-DAG: mvghi 0(%r2), -1
+; CHECK-DAG: mvghi 8(%r2), -1
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 16, i32 1, i1 false)
+  ret void
+}
+
+; 17 bytes, i32 version.
+define void @f35(i8 *%dest) {
+; CHECK-LABEL: f35:
+; CHECK: mvi 0(%r2), 255
+; CHECK: mvc 1(16,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 17, i32 1, i1 false)
+  ret void
+}
+
+; 17 bytes, i64 version.
+define void @f36(i8 *%dest) {
+; CHECK-LABEL: f36:
+; CHECK: mvi 0(%r2), 255
+; CHECK: mvc 1(16,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 17, i32 1, i1 false)
+  ret void
+}
+
+; 257 bytes, i32 version.
+define void @f37(i8 *%dest) {
+; CHECK-LABEL: f37:
+; CHECK: mvi 0(%r2), 255
+; CHECK: mvc 1(256,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 257, i32 1, i1 false)
+  ret void
+}
+
+; 257 bytes, i64 version.
+define void @f38(i8 *%dest) {
+; CHECK-LABEL: f38:
+; CHECK: mvi 0(%r2), 255
+; CHECK: mvc 1(256,%r2), 0(%r2)
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 257, i32 1, i1 false)
+  ret void
+}
+
+; 258 bytes, i32 version.  258 bytes is too big for a single MVC.
+; For now expect none, so that the test fails and gets updated when
+; large copies are implemented.
+define void @f39(i8 *%dest) {
+; CHECK-LABEL: f39:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 258, i32 1, i1 false)
+  ret void
+}
+
+; 258 bytes, i64 version, with the same comments as above.
+define void @f40(i8 *%dest) {
+; CHECK-LABEL: f40:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 258, i32 1, i1 false)
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/or-01.ll b/test/CodeGen/SystemZ/or-01.ll
index 20c9312..23946d3 100644
--- a/test/CodeGen/SystemZ/or-01.ll
+++ b/test/CodeGen/SystemZ/or-01.ll
@@ -1,10 +1,13 @@
 ; Test 32-bit ORs in which the second operand is variable.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i32 @foo()
 
 ; Check OR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: or %r2, %r3
 ; CHECK: br %r14
   %or = or i32 %a, %b
@@ -13,7 +16,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the O range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: o %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -23,7 +26,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned O range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: o %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -34,7 +37,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use OY instead of O.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -45,7 +48,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned OY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oy %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -57,7 +60,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: o %r2, 0(%r3)
 ; CHECK: br %r14
@@ -69,7 +72,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned OY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oy %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -80,7 +83,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the OY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: oy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -92,7 +95,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: o %r2, 0(%r3)
 ; CHECK: br %r14
@@ -104,7 +107,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that O allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: o %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -117,7 +120,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that OY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: oy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -127,3 +130,46 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
   %or = or i32 %a, %b
   ret i32 %or
 }
+
+; Check that ORs of spilled values can use O rather than OR.
+define i32 @f12(i32 *%ptr0) {
+; CHECK-LABEL: f12:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: o %r2, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32 *%ptr0, i64 18
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+  %val9 = load i32 *%ptr9
+
+  %ret = call i32 @foo()
+
+  %or0 = or i32 %ret, %val0
+  %or1 = or i32 %or0, %val1
+  %or2 = or i32 %or1, %val2
+  %or3 = or i32 %or2, %val3
+  %or4 = or i32 %or3, %val4
+  %or5 = or i32 %or4, %val5
+  %or6 = or i32 %or5, %val6
+  %or7 = or i32 %or6, %val7
+  %or8 = or i32 %or7, %val8
+  %or9 = or i32 %or8, %val9
+
+  ret i32 %or9
+}
diff --git a/test/CodeGen/SystemZ/or-02.ll b/test/CodeGen/SystemZ/or-02.ll
index 377a3e6..267be20 100644
--- a/test/CodeGen/SystemZ/or-02.ll
+++ b/test/CodeGen/SystemZ/or-02.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful OILL value.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: oill %r2, 1
 ; CHECK: br %r14
   %or = or i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the OILL range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: oill %r2, 65535
 ; CHECK: br %r14
   %or = or i32 %a, 65535
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; Check the lowest useful OILH range, which is the next value up.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oilh %r2, 1
 ; CHECK: br %r14
   %or = or i32 %a, 65536
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; Check the lowest useful OILF value, which is the next value up again.
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilf %r2, 65537
 ; CHECK: br %r14
   %or = or i32 %a, 65537
@@ -40,7 +40,7 @@ define i32 @f4(i32 %a) {
 
 ; Check the high end of the OILH range.
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilh %r2, 65535
 ; CHECK: br %r14
   %or = or i32 %a, -65536
@@ -49,7 +49,7 @@ define i32 @f5(i32 %a) {
 
 ; Check the next value up, which must use OILF instead.
 define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilf %r2, 4294901761
 ; CHECK: br %r14
   %or = or i32 %a, -65535
@@ -58,7 +58,7 @@ define i32 @f6(i32 %a) {
 
 ; Check the highest useful OILF value.
 define i32 @f7(i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oilf %r2, 4294967294
 ; CHECK: br %r14
   %or = or i32 %a, -2
diff --git a/test/CodeGen/SystemZ/or-03.ll b/test/CodeGen/SystemZ/or-03.ll
index 16f84f1..5fdbdfd 100644
--- a/test/CodeGen/SystemZ/or-03.ll
+++ b/test/CodeGen/SystemZ/or-03.ll
@@ -1,10 +1,13 @@
 ; Test 64-bit ORs in which the second operand is variable.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i64 @foo()
 
 ; Check OGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ogr %r2, %r3
 ; CHECK: br %r14
   %or = or i64 %a, %b
@@ -13,7 +16,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check OG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: og %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -23,7 +26,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned OG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: og %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -35,7 +38,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: og %r2, 0(%r3)
 ; CHECK: br %r14
@@ -47,7 +50,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned OG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: og %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -58,7 +61,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the OG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: og %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -70,7 +73,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: og %r2, 0(%r3)
 ; CHECK: br %r14
@@ -82,7 +85,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that OG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: og %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -92,3 +95,46 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %or = or i64 %a, %b
   ret i64 %or
 }
+
+; Check that ORs of spilled values can use OG rather than OGR.
+define i64 @f9(i64 *%ptr0) {
+; CHECK-LABEL: f9:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: og %r2, 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64 *%ptr0, i64 18
+
+  %val0 = load i64 *%ptr0
+  %val1 = load i64 *%ptr1
+  %val2 = load i64 *%ptr2
+  %val3 = load i64 *%ptr3
+  %val4 = load i64 *%ptr4
+  %val5 = load i64 *%ptr5
+  %val6 = load i64 *%ptr6
+  %val7 = load i64 *%ptr7
+  %val8 = load i64 *%ptr8
+  %val9 = load i64 *%ptr9
+
+  %ret = call i64 @foo()
+
+  %or0 = or i64 %ret, %val0
+  %or1 = or i64 %or0, %val1
+  %or2 = or i64 %or1, %val2
+  %or3 = or i64 %or2, %val3
+  %or4 = or i64 %or3, %val4
+  %or5 = or i64 %or4, %val5
+  %or6 = or i64 %or5, %val6
+  %or7 = or i64 %or6, %val7
+  %or8 = or i64 %or7, %val8
+  %or9 = or i64 %or8, %val9
+
+  ret i64 %or9
+}
diff --git a/test/CodeGen/SystemZ/or-04.ll b/test/CodeGen/SystemZ/or-04.ll
index a827842..87a30d5 100644
--- a/test/CodeGen/SystemZ/or-04.ll
+++ b/test/CodeGen/SystemZ/or-04.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful OILL value.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: oill %r2, 1
 ; CHECK: br %r14
   %or = or i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the OILL range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: oill %r2, 65535
 ; CHECK: br %r14
   %or = or i64 %a, 65535
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; Check the lowest useful OILH value, which is the next value up.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oilh %r2, 1
 ; CHECK: br %r14
   %or = or i64 %a, 65536
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check the lowest useful OILF value, which is the next value up again.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oilf %r2, 4294901759
 ; CHECK: br %r14
   %or = or i64 %a, 4294901759
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a) {
 
 ; Check the high end of the OILH range.
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oilh %r2, 65535
 ; CHECK: br %r14
   %or = or i64 %a, 4294901760
@@ -49,7 +49,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the high end of the OILF range.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oilf %r2, 4294967295
 ; CHECK: br %r14
   %or = or i64 %a, 4294967295
@@ -58,7 +58,7 @@ define i64 @f6(i64 %a) {
 
 ; Check the lowest useful OIHL value, which is the next value up.
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oihl %r2, 1
 ; CHECK: br %r14
   %or = or i64 %a, 4294967296
@@ -67,7 +67,7 @@ define i64 @f7(i64 %a) {
 
 ; Check the next value up again, which must use two ORs.
 define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: oihl %r2, 1
 ; CHECK: oill %r2, 1
 ; CHECK: br %r14
@@ -77,7 +77,7 @@ define i64 @f8(i64 %a) {
 
 ; Check the high end of the OILL range.
 define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: oihl %r2, 1
 ; CHECK: oill %r2, 65535
 ; CHECK: br %r14
@@ -87,7 +87,7 @@ define i64 @f9(i64 %a) {
 
 ; Check the next value up, which must use OILH
 define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: oihl %r2, 1
 ; CHECK: oilh %r2, 1
 ; CHECK: br %r14
@@ -97,7 +97,7 @@ define i64 @f10(i64 %a) {
 
 ; Check the next value up again, which must use OILF
 define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: oihl %r2, 1
 ; CHECK: oilf %r2, 65537
 ; CHECK: br %r14
@@ -107,7 +107,7 @@ define i64 @f11(i64 %a) {
 
 ; Check the high end of the OIHL range.
 define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: oihl %r2, 65535
 ; CHECK: br %r14
   %or = or i64 %a, 281470681743360
@@ -117,7 +117,7 @@ define i64 @f12(i64 %a) {
 ; Check a combination of the high end of the OIHL range and the high end
 ; of the OILF range.
 define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: oihl %r2, 65535
 ; CHECK: oilf %r2, 4294967295
 ; CHECK: br %r14
@@ -127,7 +127,7 @@ define i64 @f13(i64 %a) {
 
 ; Check the lowest useful OIHH value.
 define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: oihh %r2, 1
 ; CHECK: br %r14
   %or = or i64 %a, 281474976710656
@@ -136,7 +136,7 @@ define i64 @f14(i64 %a) {
 
 ; Check the next value up, which needs two ORs.
 define i64 @f15(i64 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
 ; CHECK: oihh %r2, 1
 ; CHECK: oill %r2, 1
 ; CHECK: br %r14
@@ -146,7 +146,7 @@ define i64 @f15(i64 %a) {
 
 ; Check the lowest useful OIHF value.
 define i64 @f16(i64 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
 ; CHECK: oihf %r2, 65537
 ; CHECK: br %r14
   %or = or i64 %a, 281479271677952
@@ -155,7 +155,7 @@ define i64 @f16(i64 %a) {
 
 ; Check the high end of the OIHH range.
 define i64 @f17(i64 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
 ; CHECK: oihh %r2, 65535
 ; CHECK: br %r14
   %or = or i64 %a, 18446462598732840960
@@ -164,7 +164,7 @@ define i64 @f17(i64 %a) {
 
 ; Check the high end of the OIHF range.
 define i64 @f18(i64 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
 ; CHECK: oihf %r2, 4294967295
 ; CHECK: br %r14
   %or = or i64 %a, -4294967296
@@ -173,7 +173,7 @@ define i64 @f18(i64 %a) {
 
 ; Check the highest useful OR value.
 define i64 @f19(i64 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
 ; CHECK: oihf %r2, 4294967295
 ; CHECK: oilf %r2, 4294967294
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/or-05.ll b/test/CodeGen/SystemZ/or-05.ll
index 9b6c10d..d905891 100644
--- a/test/CodeGen/SystemZ/or-05.ll
+++ b/test/CodeGen/SystemZ/or-05.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful constant, expressed as a signed integer.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: oi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a signed integer.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -26,7 +26,7 @@ define void @f2(i8 *%ptr) {
 
 ; Check the lowest useful constant, expressed as an unsigned integer.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -37,7 +37,7 @@ define void @f3(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a unsigned integer.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -48,7 +48,7 @@ define void @f4(i8 *%ptr) {
 
 ; Check the high end of the OI range.
 define void @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oi 4095(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -60,7 +60,7 @@ define void @f5(i8 *%src) {
 
 ; Check the next byte up, which should use OIY instead of OI.
 define void @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oiy 4096(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -72,7 +72,7 @@ define void @f6(i8 *%src) {
 
 ; Check the high end of the OIY range.
 define void @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oiy 524287(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -85,7 +85,7 @@ define void @f7(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, 524288
 ; CHECK: oi 0(%r2), 127
 ; CHECK: br %r14
@@ -98,7 +98,7 @@ define void @f8(i8 *%src) {
 
 ; Check the high end of the negative OIY range.
 define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: oiy -1(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -110,7 +110,7 @@ define void @f9(i8 *%src) {
 
 ; Check the low end of the OIY range.
 define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: oiy -524288(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -123,7 +123,7 @@ define void @f10(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r2, -524289
 ; CHECK: oi 0(%r2), 127
 ; CHECK: br %r14
@@ -136,7 +136,7 @@ define void @f11(i8 *%src) {
 
 ; Check that OI does not allow an index
 define void @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agr %r2, %r3
 ; CHECK: oi 4095(%r2), 127
 ; CHECK: br %r14
@@ -151,7 +151,7 @@ define void @f12(i64 %src, i64 %index) {
 
 ; Check that OIY does not allow an index
 define void @f13(i64 %src, i64 %index) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agr %r2, %r3
 ; CHECK: oiy 4096(%r2), 127
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/or-06.ll b/test/CodeGen/SystemZ/or-06.ll
index a24a18a..0a865d3 100644
--- a/test/CodeGen/SystemZ/or-06.ll
+++ b/test/CodeGen/SystemZ/or-06.ll
@@ -5,7 +5,7 @@
 
 ; Zero extension to 32 bits, negative constant.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -18,7 +18,7 @@ define void @f1(i8 *%ptr) {
 
 ; Zero extension to 64 bits, negative constant.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -31,7 +31,7 @@ define void @f2(i8 *%ptr) {
 
 ; Zero extension to 32 bits, positive constant.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define void @f3(i8 *%ptr) {
 
 ; Zero extension to 64 bits, positive constant.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -57,7 +57,7 @@ define void @f4(i8 *%ptr) {
 
 ; Sign extension to 32 bits, negative constant.
 define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -70,7 +70,7 @@ define void @f5(i8 *%ptr) {
 
 ; Sign extension to 64 bits, negative constant.
 define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -83,7 +83,7 @@ define void @f6(i8 *%ptr) {
 
 ; Sign extension to 32 bits, positive constant.
 define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -96,7 +96,7 @@ define void @f7(i8 *%ptr) {
 
 ; Sign extension to 64 bits, positive constant.
 define void @f8(i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: oi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/or-07.ll b/test/CodeGen/SystemZ/or-07.ll
new file mode 100644
index 0000000..9fff88e
--- /dev/null
+++ b/test/CodeGen/SystemZ/or-07.ll
@@ -0,0 +1,39 @@
+; Test the three-operand forms of OR.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check XRK.
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f1:
+; CHECK: ork %r2, %r3, %r4
+; CHECK: br %r14
+  %or = or i32 %b, %c
+  ret i32 %or
+}
+
+; Check that we can still use OR in obvious cases.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: or %r2, %r3
+; CHECK: br %r14
+  %or = or i32 %a, %b
+  ret i32 %or
+}
+
+; Check OGRK.
+define i64 @f3(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f3:
+; CHECK: ogrk %r2, %r3, %r4
+; CHECK: br %r14
+  %or = or i64 %b, %c
+  ret i64 %or
+}
+
+; Check that we can still use OGR in obvious cases.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: ogr %r2, %r3
+; CHECK: br %r14
+  %or = or i64 %a, %b
+  ret i64 %or
+}
diff --git a/test/CodeGen/SystemZ/risbg-01.ll b/test/CodeGen/SystemZ/risbg-01.ll
new file mode 100644
index 0000000..85de6dc
--- /dev/null
+++ b/test/CodeGen/SystemZ/risbg-01.ll
@@ -0,0 +1,457 @@
+; Test sequences that can use RISBG with a zeroed first operand.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+; Test an extraction of bit 0 from a right-shifted value.
+define i32 @f1(i32 %foo) {
+; CHECK-LABEL: f1:
+; CHECK: risbg %r2, %r2, 63, 191, 54
+; CHECK: br %r14
+  %shr = lshr i32 %foo, 10
+  %and = and i32 %shr, 1
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f2(i64 %foo) {
+; CHECK-LABEL: f2:
+; CHECK: risbg %r2, %r2, 63, 191, 54
+; CHECK: br %r14
+  %shr = lshr i64 %foo, 10
+  %and = and i64 %shr, 1
+  ret i64 %and
+}
+
+; Test an extraction of other bits from a right-shifted value.
+define i32 @f3(i32 %foo) {
+; CHECK-LABEL: f3:
+; CHECK: risbg %r2, %r2, 60, 189, 42
+; CHECK: br %r14
+  %shr = lshr i32 %foo, 22
+  %and = and i32 %shr, 12
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f4(i64 %foo) {
+; CHECK-LABEL: f4:
+; CHECK: risbg %r2, %r2, 60, 189, 42
+; CHECK: br %r14
+  %shr = lshr i64 %foo, 22
+  %and = and i64 %shr, 12
+  ret i64 %and
+}
+
+; Test an extraction of most bits from a right-shifted value.
+; The range should be reduced to exclude the zeroed high bits.
+define i32 @f5(i32 %foo) {
+; CHECK-LABEL: f5:
+; CHECK: risbg %r2, %r2, 34, 188, 62
+; CHECK: br %r14
+  %shr = lshr i32 %foo, 2
+  %and = and i32 %shr, -8
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f6(i64 %foo) {
+; CHECK-LABEL: f6:
+; CHECK: risbg %r2, %r2, 2, 188, 62
+; CHECK: br %r14
+  %shr = lshr i64 %foo, 2
+  %and = and i64 %shr, -8
+  ret i64 %and
+}
+
+; Try the next value up (mask ....1111001).  This needs a separate shift
+; and mask.
+define i32 @f7(i32 %foo) {
+; CHECK-LABEL: f7:
+; CHECK: srl %r2, 2
+; CHECK: nill %r2, 65529
+; CHECK: br %r14
+  %shr = lshr i32 %foo, 2
+  %and = and i32 %shr, -7
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f8(i64 %foo) {
+; CHECK-LABEL: f8:
+; CHECK: srlg %r2, %r2, 2
+; CHECK: nill %r2, 65529
+; CHECK: br %r14
+  %shr = lshr i64 %foo, 2
+  %and = and i64 %shr, -7
+  ret i64 %and
+}
+
+; Test an extraction of bits from a left-shifted value.  The range should
+; be reduced to exclude the zeroed low bits.
+define i32 @f9(i32 %foo) {
+; CHECK-LABEL: f9:
+; CHECK: risbg %r2, %r2, 56, 189, 2
+; CHECK: br %r14
+  %shr = shl i32 %foo, 2
+  %and = and i32 %shr, 255
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f10(i64 %foo) {
+; CHECK-LABEL: f10:
+; CHECK: risbg %r2, %r2, 56, 189, 2
+; CHECK: br %r14
+  %shr = shl i64 %foo, 2
+  %and = and i64 %shr, 255
+  ret i64 %and
+}
+
+; Try a wrap-around mask (mask ....111100001111).  This needs a separate shift
+; and mask.
+define i32 @f11(i32 %foo) {
+; CHECK-LABEL: f11:
+; CHECK: sll %r2, 2
+; CHECK: nill %r2, 65295
+; CHECK: br %r14
+  %shr = shl i32 %foo, 2
+  %and = and i32 %shr, -241
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f12(i64 %foo) {
+; CHECK-LABEL: f12:
+; CHECK: sllg %r2, %r2, 2
+; CHECK: nill %r2, 65295
+; CHECK: br %r14
+  %shr = shl i64 %foo, 2
+  %and = and i64 %shr, -241
+  ret i64 %and
+}
+
+; Test an extraction from a rotated value, no mask wraparound.
+; This is equivalent to the lshr case, because the bits from the
+; shl are not used.
+define i32 @f13(i32 %foo) {
+; CHECK-LABEL: f13:
+; CHECK: risbg %r2, %r2, 56, 188, 46
+; CHECK: br %r14
+  %parta = shl i32 %foo, 14
+  %partb = lshr i32 %foo, 18
+  %rotl = or i32 %parta, %partb
+  %and = and i32 %rotl, 248
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f14(i64 %foo) {
+; CHECK-LABEL: f14:
+; CHECK: risbg %r2, %r2, 56, 188, 14
+; CHECK: br %r14
+  %parta = shl i64 %foo, 14
+  %partb = lshr i64 %foo, 50
+  %rotl = or i64 %parta, %partb
+  %and = and i64 %rotl, 248
+  ret i64 %and
+}
+
+; Try a case in which only the bits from the shl are used.
+define i32 @f15(i32 %foo) {
+; CHECK-LABEL: f15:
+; CHECK: risbg %r2, %r2, 47, 177, 14
+; CHECK: br %r14
+  %parta = shl i32 %foo, 14
+  %partb = lshr i32 %foo, 18
+  %rotl = or i32 %parta, %partb
+  %and = and i32 %rotl, 114688
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f16(i64 %foo) {
+; CHECK-LABEL: f16:
+; CHECK: risbg %r2, %r2, 47, 177, 14
+; CHECK: br %r14
+  %parta = shl i64 %foo, 14
+  %partb = lshr i64 %foo, 50
+  %rotl = or i64 %parta, %partb
+  %and = and i64 %rotl, 114688
+  ret i64 %and
+}
+
+; Test a 32-bit rotate in which both parts of the OR are needed.
+; This needs a separate shift and mask.
+define i32 @f17(i32 %foo) {
+; CHECK-LABEL: f17:
+; CHECK: rll %r2, %r2, 4
+; CHECK: nilf %r2, 126
+; CHECK: br %r14
+  %parta = shl i32 %foo, 4
+  %partb = lshr i32 %foo, 28
+  %rotl = or i32 %parta, %partb
+  %and = and i32 %rotl, 126
+  ret i32 %and
+}
+
+; ...and for i64, where RISBG should do the rotate too.
+define i64 @f18(i64 %foo) {
+; CHECK-LABEL: f18:
+; CHECK: risbg %r2, %r2, 57, 190, 4
+; CHECK: br %r14
+  %parta = shl i64 %foo, 4
+  %partb = lshr i64 %foo, 60
+  %rotl = or i64 %parta, %partb
+  %and = and i64 %rotl, 126
+  ret i64 %and
+}
+
+; Test an arithmetic shift right in which some of the sign bits are kept.
+; This needs a separate shift and mask.
+define i32 @f19(i32 %foo) {
+; CHECK-LABEL: f19:
+; CHECK: sra %r2, 28
+; CHECK: nilf %r2, 30
+; CHECK: br %r14
+  %shr = ashr i32 %foo, 28
+  %and = and i32 %shr, 30
+  ret i32 %and
+}
+
+; ...and again with i64.  In this case RISBG is the best way of doing the AND.
+define i64 @f20(i64 %foo) {
+; CHECK-LABEL: f20:
+; CHECK: srag [[REG:%r[0-5]]], %r2, 60
+; CHECK: risbg %r2, [[REG]], 59, 190, 0
+; CHECK: br %r14
+  %shr = ashr i64 %foo, 60
+  %and = and i64 %shr, 30
+  ret i64 %and
+}
+
+; Now try an arithmetic right shift in which the sign bits aren't needed.
+; Introduce a second use of %shr so that the ashr doesn't decompose to
+; an lshr.
+define i32 @f21(i32 %foo, i32 *%dest) {
+; CHECK-LABEL: f21:
+; CHECK: risbg %r2, %r2, 60, 190, 36
+; CHECK: br %r14
+  %shr = ashr i32 %foo, 28
+  store i32 %shr, i32 *%dest
+  %and = and i32 %shr, 14
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f22(i64 %foo, i64 *%dest) {
+; CHECK-LABEL: f22:
+; CHECK: risbg %r2, %r2, 60, 190, 4
+; CHECK: br %r14
+  %shr = ashr i64 %foo, 60
+  store i64 %shr, i64 *%dest
+  %and = and i64 %shr, 14
+  ret i64 %and
+}
+
+; Check that we use RISBG for shifted values even if the AND is a
+; natural zero extension.
+define i64 @f23(i64 %foo) {
+; CHECK-LABEL: f23:
+; CHECK: risbg %r2, %r2, 56, 191, 62
+; CHECK: br %r14
+  %shr = lshr i64 %foo, 2
+  %and = and i64 %shr, 255
+  ret i64 %and
+}
+
+; Test a case where the AND comes before a rotate.  This needs a separate
+; mask and rotate.
+define i32 @f24(i32 %foo) {
+; CHECK-LABEL: f24:
+; CHECK: nilf %r2, 14
+; CHECK: rll %r2, %r2, 3
+; CHECK: br %r14
+  %and = and i32 %foo, 14
+  %parta = shl i32 %and, 3
+  %partb = lshr i32 %and, 29
+  %rotl = or i32 %parta, %partb
+  ret i32 %rotl
+}
+
+; ...and again with i64, where a single RISBG is enough.
+define i64 @f25(i64 %foo) {
+; CHECK-LABEL: f25:
+; CHECK: risbg %r2, %r2, 57, 187, 3
+; CHECK: br %r14
+  %and = and i64 %foo, 14
+  %parta = shl i64 %and, 3
+  %partb = lshr i64 %and, 61
+  %rotl = or i64 %parta, %partb
+  ret i64 %rotl
+}
+
+; Test a wrap-around case in which the AND comes before a rotate.
+; This again needs a separate mask and rotate.
+define i32 @f26(i32 %foo) {
+; CHECK-LABEL: f26:
+; CHECK: nill %r2, 65487
+; CHECK: rll %r2, %r2, 5
+; CHECK: br %r14
+  %and = and i32 %foo, -49
+  %parta = shl i32 %and, 5
+  %partb = lshr i32 %and, 27
+  %rotl = or i32 %parta, %partb
+  ret i32 %rotl
+}
+
+; ...and again with i64, where a single RISBG is OK.
+define i64 @f27(i64 %foo) {
+; CHECK-LABEL: f27:
+; CHECK: risbg %r2, %r2, 55, 180, 5
+; CHECK: br %r14
+  %and = and i64 %foo, -49
+  %parta = shl i64 %and, 5
+  %partb = lshr i64 %and, 59
+  %rotl = or i64 %parta, %partb
+  ret i64 %rotl
+}
+
+; Test a case where the AND comes before a shift left.
+define i32 @f28(i32 %foo) {
+; CHECK-LABEL: f28:
+; CHECK: risbg %r2, %r2, 32, 173, 17
+; CHECK: br %r14
+  %and = and i32 %foo, 32766
+  %shl = shl i32 %and, 17
+  ret i32 %shl
+}
+
+; ...and again with i64.
+define i64 @f29(i64 %foo) {
+; CHECK-LABEL: f29:
+; CHECK: risbg %r2, %r2, 0, 141, 49
+; CHECK: br %r14
+  %and = and i64 %foo, 32766
+  %shl = shl i64 %and, 49
+  ret i64 %shl
+}
+
+; Test the next shift up from f28, in which the mask should get shortened.
+define i32 @f30(i32 %foo) {
+; CHECK-LABEL: f30:
+; CHECK: risbg %r2, %r2, 32, 172, 18
+; CHECK: br %r14
+  %and = and i32 %foo, 32766
+  %shl = shl i32 %and, 18
+  ret i32 %shl
+}
+
+; ...and again with i64.
+define i64 @f31(i64 %foo) {
+; CHECK-LABEL: f31:
+; CHECK: risbg %r2, %r2, 0, 140, 50
+; CHECK: br %r14
+  %and = and i64 %foo, 32766
+  %shl = shl i64 %and, 50
+  ret i64 %shl
+}
+
+; Test a wrap-around case in which the shift left comes after the AND.
+; We can't use RISBG for the shift in that case.
+define i32 @f32(i32 %foo) {
+; CHECK-LABEL: f32:
+; CHECK: sll %r2
+; CHECK: br %r14
+  %and = and i32 %foo, -7
+  %shl = shl i32 %and, 10
+  ret i32 %shl
+}
+
+; ...and again with i64.
+define i64 @f33(i64 %foo) {
+; CHECK-LABEL: f33:
+; CHECK: sllg %r2
+; CHECK: br %r14
+  %and = and i64 %foo, -7
+  %shl = shl i64 %and, 10
+  ret i64 %shl
+}
+
+; Test a case where the AND comes before a shift right.
+define i32 @f34(i32 %foo) {
+; CHECK-LABEL: f34:
+; CHECK: risbg %r2, %r2, 57, 191, 55
+; CHECK: br %r14
+  %and = and i32 %foo, 65535
+  %shl = lshr i32 %and, 9
+  ret i32 %shl
+}
+
+; ...and again with i64.
+define i64 @f35(i64 %foo) {
+; CHECK-LABEL: f35:
+; CHECK: risbg %r2, %r2, 57, 191, 55
+; CHECK: br %r14
+  %and = and i64 %foo, 65535
+  %shl = lshr i64 %and, 9
+  ret i64 %shl
+}
+
+; Test a wrap-around case where the AND comes before a shift right.
+; We can't use RISBG for the shift in that case.
+define i32 @f36(i32 %foo) {
+; CHECK-LABEL: f36:
+; CHECK: srl %r2
+; CHECK: br %r14
+  %and = and i32 %foo, -25
+  %shl = lshr i32 %and, 1
+  ret i32 %shl
+}
+
+; ...and again with i64.
+define i64 @f37(i64 %foo) {
+; CHECK-LABEL: f37:
+; CHECK: srlg %r2
+; CHECK: br %r14
+  %and = and i64 %foo, -25
+  %shl = lshr i64 %and, 1
+  ret i64 %shl
+}
+
+; Test a combination involving a large ASHR and a shift left.  We can't
+; use RISBG there.
+define i64 @f38(i64 %foo) {
+; CHECK-LABEL: f38:
+; CHECK: srag {{%r[0-5]}}
+; CHECK: sllg {{%r[0-5]}}
+; CHECK: br %r14
+  %ashr = ashr i64 %foo, 32
+  %shl = shl i64 %ashr, 5
+  ret i64 %shl
+}
+
+; Try a similar thing in which no shifted sign bits are kept.
+define i64 @f39(i64 %foo, i64 *%dest) {
+; CHECK-LABEL: f39:
+; CHECK: srag [[REG:%r[01345]]], %r2, 35
+; CHECK: risbg %r2, %r2, 33, 189, 31
+; CHECK: br %r14
+  %ashr = ashr i64 %foo, 35
+  store i64 %ashr, i64 *%dest
+  %shl = shl i64 %ashr, 2
+  %and = and i64 %shl, 2147483647
+  ret i64 %and
+}
+
+; ...and again with the next highest shift value, where one sign bit is kept.
+define i64 @f40(i64 %foo, i64 *%dest) {
+; CHECK-LABEL: f40:
+; CHECK: srag [[REG:%r[01345]]], %r2, 36
+; CHECK: risbg %r2, [[REG]], 33, 189, 2
+; CHECK: br %r14
+  %ashr = ashr i64 %foo, 36
+  store i64 %ashr, i64 *%dest
+  %shl = shl i64 %ashr, 2
+  %and = and i64 %shl, 2147483647
+  ret i64 %and
+}
diff --git a/test/CodeGen/SystemZ/risbg-02.ll b/test/CodeGen/SystemZ/risbg-02.ll
new file mode 100644
index 0000000..5ccfab0
--- /dev/null
+++ b/test/CodeGen/SystemZ/risbg-02.ll
@@ -0,0 +1,93 @@
+; Test sequences that can use RISBG with a normal first operand.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+; Test a case with two ANDs.
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK-LABEL: f1:
+; CHECK: risbg %r2, %r3, 60, 62, 0
+; CHECK: br %r14
+  %anda = and i32 %a, -15
+  %andb = and i32 %b, 14
+  %or = or i32 %anda, %andb
+  ret i32 %or
+}
+
+; ...and again with i64.
+define i64 @f2(i64 %a, i64 %b) {
+; CHECK-LABEL: f2:
+; CHECK: risbg %r2, %r3, 60, 62, 0
+; CHECK: br %r14
+  %anda = and i64 %a, -15
+  %andb = and i64 %b, 14
+  %or = or i64 %anda, %andb
+  ret i64 %or
+}
+
+; Test a case with two ANDs and a shift.
+define i32 @f3(i32 %a, i32 %b) {
+; CHECK-LABEL: f3:
+; CHECK: risbg %r2, %r3, 60, 63, 56
+; CHECK: br %r14
+  %anda = and i32 %a, -16
+  %shr = lshr i32 %b, 8
+  %andb = and i32 %shr, 15
+  %or = or i32 %anda, %andb
+  ret i32 %or
+}
+
+; ...and again with i64.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: risbg %r2, %r3, 60, 63, 56
+; CHECK: br %r14
+  %anda = and i64 %a, -16
+  %shr = lshr i64 %b, 8
+  %andb = and i64 %shr, 15
+  %or = or i64 %anda, %andb
+  ret i64 %or
+}
+
+; Test a case with a single AND and a left shift.
+define i32 @f5(i32 %a, i32 %b) {
+; CHECK-LABEL: f5:
+; CHECK: risbg %r2, %r3, 32, 53, 10
+; CHECK: br %r14
+  %anda = and i32 %a, 1023
+  %shlb = shl i32 %b, 10
+  %or = or i32 %anda, %shlb
+  ret i32 %or
+}
+
+; ...and again with i64.
+define i64 @f6(i64 %a, i64 %b) {
+; CHECK-LABEL: f6:
+; CHECK: risbg %r2, %r3, 0, 53, 10
+; CHECK: br %r14
+  %anda = and i64 %a, 1023
+  %shlb = shl i64 %b, 10
+  %or = or i64 %anda, %shlb
+  ret i64 %or
+}
+
+; Test a case with a single AND and a right shift.
+define i32 @f7(i32 %a, i32 %b) {
+; CHECK-LABEL: f7:
+; CHECK: risbg %r2, %r3, 40, 63, 56
+; CHECK: br %r14
+  %anda = and i32 %a, -16777216
+  %shrb = lshr i32 %b, 8
+  %or = or i32 %anda, %shrb
+  ret i32 %or
+}
+
+; ...and again with i64.
+define i64 @f8(i64 %a, i64 %b) {
+; CHECK-LABEL: f8:
+; CHECK: risbg %r2, %r3, 8, 63, 56
+; CHECK: br %r14
+  %anda = and i64 %a, -72057594037927936
+  %shrb = lshr i64 %b, 8
+  %or = or i64 %anda, %shrb
+  ret i64 %or
+}
diff --git a/test/CodeGen/SystemZ/rnsbg-01.ll b/test/CodeGen/SystemZ/rnsbg-01.ll
new file mode 100644
index 0000000..666aeb2
--- /dev/null
+++ b/test/CodeGen/SystemZ/rnsbg-01.ll
@@ -0,0 +1,257 @@
+; Test sequences that can use RNSBG.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+; Test a simple mask, which is a wrap-around case.
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK-LABEL: f1:
+; CHECK: rnsbg %r2, %r3, 59, 56, 0
+; CHECK: br %r14
+  %orb = or i32 %b, 96
+  %and = and i32 %a, %orb
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f2(i64 %a, i64 %b) {
+; CHECK-LABEL: f2:
+; CHECK: rnsbg %r2, %r3, 59, 56, 0
+; CHECK: br %r14
+  %orb = or i64 %b, 96
+  %and = and i64 %a, %orb
+  ret i64 %and
+}
+
+; Test a case where no wraparound is needed.
+define i32 @f3(i32 %a, i32 %b) {
+; CHECK-LABEL: f3:
+; CHECK: rnsbg %r2, %r3, 58, 61, 0
+; CHECK: br %r14
+  %orb = or i32 %b, -61
+  %and = and i32 %a, %orb
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: rnsbg %r2, %r3, 58, 61, 0
+; CHECK: br %r14
+  %orb = or i64 %b, -61
+  %and = and i64 %a, %orb
+  ret i64 %and
+}
+
+; Test a case with just a left shift.  This can't use RNSBG.
+define i32 @f6(i32 %a, i32 %b) {
+; CHECK-LABEL: f6:
+; CHECK: sll {{%r[0-5]}}
+; CHECK: nr {{%r[0-5]}}
+; CHECK: br %r14
+  %shrb = shl i32 %b, 20
+  %and = and i32 %a, %shrb
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f7(i64 %a, i64 %b) {
+; CHECK-LABEL: f7:
+; CHECK: sllg {{%r[0-5]}}
+; CHECK: ngr {{%r[0-5]}}
+; CHECK: br %r14
+  %shrb = shl i64 %b, 20
+  %and = and i64 %a, %shrb
+  ret i64 %and
+}
+
+; Test a case with just a rotate.  This can't use RNSBG.
+define i32 @f8(i32 %a, i32 %b) {
+; CHECK-LABEL: f8:
+; CHECK: rll {{%r[0-5]}}
+; CHECK: nr {{%r[0-5]}}
+; CHECK: br %r14
+  %shlb = shl i32 %b, 22
+  %shrb = lshr i32 %b, 10
+  %rotlb = or i32 %shlb, %shrb
+  %and = and i32 %a, %rotlb
+  ret i32 %and
+}
+
+; ...and again with i64, which can.
+define i64 @f9(i64 %a, i64 %b) {
+; CHECK-LABEL: f9:
+; CHECK: rnsbg %r2, %r3, 0, 63, 44
+; CHECK: br %r14
+  %shlb = shl i64 %b, 44
+  %shrb = lshr i64 %b, 20
+  %rotlb = or i64 %shlb, %shrb
+  %and = and i64 %a, %rotlb
+  ret i64 %and
+}
+
+; Test a case with a left shift and OR, where the OR covers all shifted bits.
+; We can do the whole thing using RNSBG.
+define i32 @f10(i32 %a, i32 %b) {
+; CHECK-LABEL: f10:
+; CHECK: rnsbg %r2, %r3, 32, 56, 7
+; CHECK: br %r14
+  %shlb = shl i32 %b, 7
+  %orb = or i32 %shlb, 127
+  %and = and i32 %a, %orb
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f11(i64 %a, i64 %b) {
+; CHECK-LABEL: f11:
+; CHECK: rnsbg %r2, %r3, 0, 56, 7
+; CHECK: br %r14
+  %shlb = shl i64 %b, 7
+  %orb = or i64 %shlb, 127
+  %and = and i64 %a, %orb
+  ret i64 %and
+}
+
+; Test a case with a left shift and OR, where the OR doesn't cover all
+; shifted bits.  We can't use RNSBG for the shift, but we can for the OR
+; and AND.
+define i32 @f12(i32 %a, i32 %b) {
+; CHECK-LABEL: f12:
+; CHECK: sll %r3, 7
+; CHECK: rnsbg %r2, %r3, 32, 57, 0
+; CHECK: br %r14
+  %shlb = shl i32 %b, 7
+  %orb = or i32 %shlb, 63
+  %and = and i32 %a, %orb
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f13(i64 %a, i64 %b) {
+; CHECK-LABEL: f13:
+; CHECK: sllg [[REG:%r[01345]]], %r3, 7
+; CHECK: rnsbg %r2, [[REG]], 0, 57, 0
+; CHECK: br %r14
+  %shlb = shl i64 %b, 7
+  %orb = or i64 %shlb, 63
+  %and = and i64 %a, %orb
+  ret i64 %and
+}
+
+; Test a case with a right shift and OR, where the OR covers all the shifted
+; bits.  The whole thing can be done using RNSBG.
+define i32 @f14(i32 %a, i32 %b) {
+; CHECK-LABEL: f14:
+; CHECK: rnsbg %r2, %r3, 60, 63, 37
+; CHECK: br %r14
+  %shrb = lshr i32 %b, 27
+  %orb = or i32 %shrb, -16
+  %and = and i32 %a, %orb
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f15(i64 %a, i64 %b) {
+; CHECK-LABEL: f15:
+; CHECK: rnsbg %r2, %r3, 60, 63, 5
+; CHECK: br %r14
+  %shrb = lshr i64 %b, 59
+  %orb = or i64 %shrb, -16
+  %and = and i64 %a, %orb
+  ret i64 %and
+}
+
+; Test a case with a right shift and OR, where the OR doesn't cover all the
+; shifted bits.  The shift needs to be done separately, but the OR and AND
+; can use RNSBG.
+define i32 @f16(i32 %a, i32 %b) {
+; CHECK-LABEL: f16:
+; CHECK: srl %r3, 29
+; CHECK: rnsbg %r2, %r3, 60, 63, 0
+; CHECK: br %r14
+  %shrb = lshr i32 %b, 29
+  %orb = or i32 %shrb, -16
+  %and = and i32 %a, %orb
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f17(i64 %a, i64 %b) {
+; CHECK-LABEL: f17:
+; CHECK: srlg [[REG:%r[01345]]], %r3, 61
+; CHECK: rnsbg %r2, [[REG]], 60, 63, 0
+; CHECK: br %r14
+  %shrb = lshr i64 %b, 61
+  %orb = or i64 %shrb, -16
+  %and = and i64 %a, %orb
+  ret i64 %and
+}
+
+; Test a combination involving an ASHR in which the sign bits matter.
+; We can't use RNSBG for the ASHR in that case, but we can for the rest.
+define i32 @f18(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f18:
+; CHECK: sra %r3, 4
+; CHECK: rnsbg %r2, %r3, 32, 62, 1
+; CHECK: br %r14
+  %ashrb = ashr i32 %b, 4
+  store i32 %ashrb, i32 *%dest
+  %shlb = shl i32 %ashrb, 1
+  %orb = or i32 %shlb, 1
+  %and = and i32 %a, %orb
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f19(i64 %a, i64 %b, i64 *%dest) {
+; CHECK-LABEL: f19:
+; CHECK: srag [[REG:%r[0145]]], %r3, 34
+; CHECK: rnsbg %r2, [[REG]], 0, 62, 1
+; CHECK: br %r14
+  %ashrb = ashr i64 %b, 34
+  store i64 %ashrb, i64 *%dest
+  %shlb = shl i64 %ashrb, 1
+  %orb = or i64 %shlb, 1
+  %and = and i64 %a, %orb
+  ret i64 %and
+}
+
+; Test a combination involving an ASHR in which the sign bits don't matter.
+define i32 @f20(i32 %a, i32 %b, i32 *%dest) {
+; CHECK-LABEL: f20:
+; CHECK: rnsbg %r2, %r3, 48, 62, 48
+; CHECK: br %r14
+  %ashrb = ashr i32 %b, 17
+  store i32 %ashrb, i32 *%dest
+  %shlb = shl i32 %ashrb, 1
+  %orb = or i32 %shlb, -65535
+  %and = and i32 %a, %orb
+  ret i32 %and
+}
+
+; ...and again with i64.
+define i64 @f21(i64 %a, i64 %b, i64 *%dest) {
+; CHECK-LABEL: f21:
+; CHECK: rnsbg %r2, %r3, 48, 62, 16
+; CHECK: br %r14
+  %ashrb = ashr i64 %b, 49
+  store i64 %ashrb, i64 *%dest
+  %shlb = shl i64 %ashrb, 1
+  %orb = or i64 %shlb, -65535
+  %and = and i64 %a, %orb
+  ret i64 %and
+}
+
+; Test a case with a shift, OR, and rotate where the OR covers all shifted bits.
+define i64 @f22(i64 %a, i64 %b) {
+; CHECK-LABEL: f22:
+; CHECK: rnsbg %r2, %r3, 60, 54, 9
+; CHECK: br %r14
+  %shlb = shl i64 %b, 5
+  %orb = or i64 %shlb, 31
+  %shlorb = shl i64 %orb, 4
+  %shrorb = lshr i64 %orb, 60
+  %rotlorb = or i64 %shlorb, %shrorb
+  %and = and i64 %a, %rotlorb
+  ret i64 %and
+}
diff --git a/test/CodeGen/SystemZ/rosbg-01.ll b/test/CodeGen/SystemZ/rosbg-01.ll
new file mode 100644
index 0000000..0abaccc
--- /dev/null
+++ b/test/CodeGen/SystemZ/rosbg-01.ll
@@ -0,0 +1,110 @@
+; Test sequences that can use ROSBG.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+; Test the simple case.
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK-LABEL: f1:
+; CHECK: rosbg %r2, %r3, 59, 59, 0
+; CHECK: br %r14
+  %andb = and i32 %b, 16
+  %or = or i32 %a, %andb
+  ret i32 %or
+}
+
+; ...and again with i64.
+define i64 @f2(i64 %a, i64 %b) {
+; CHECK-LABEL: f2:
+; CHECK: rosbg %r2, %r3, 59, 59, 0
+; CHECK: br %r14
+  %andb = and i64 %b, 16
+  %or = or i64 %a, %andb
+  ret i64 %or
+}
+
+; Test a case where wraparound is needed.
+define i32 @f3(i32 %a, i32 %b) {
+; CHECK-LABEL: f3:
+; CHECK: rosbg %r2, %r3, 63, 60, 0
+; CHECK: br %r14
+  %andb = and i32 %b, -7
+  %or = or i32 %a, %andb
+  ret i32 %or
+}
+
+; ...and again with i64.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: rosbg %r2, %r3, 63, 60, 0
+; CHECK: br %r14
+  %andb = and i64 %b, -7
+  %or = or i64 %a, %andb
+  ret i64 %or
+}
+
+; Test a case with just a shift.
+define i32 @f6(i32 %a, i32 %b) {
+; CHECK-LABEL: f6:
+; CHECK: rosbg %r2, %r3, 32, 51, 12
+; CHECK: br %r14
+  %shrb = shl i32 %b, 12
+  %or = or i32 %a, %shrb
+  ret i32 %or
+}
+
+; ...and again with i64.
+define i64 @f7(i64 %a, i64 %b) {
+; CHECK-LABEL: f7:
+; CHECK: rosbg %r2, %r3, 0, 51, 12
+; CHECK: br %r14
+  %shrb = shl i64 %b, 12
+  %or = or i64 %a, %shrb
+  ret i64 %or
+}
+
+; Test a case with just a rotate.  This can't use ROSBG.
+define i32 @f8(i32 %a, i32 %b) {
+; CHECK-LABEL: f8:
+; CHECK: rll {{%r[0-5]}}
+; CHECK: or {{%r[0-5]}}
+; CHECK: br %r14
+  %shlb = shl i32 %b, 30
+  %shrb = lshr i32 %b, 2
+  %rotlb = or i32 %shlb, %shrb
+  %or = or i32 %a, %rotlb
+  ret i32 %or
+}
+
+; ...and again with i64, which can.
+define i64 @f9(i64 %a, i64 %b) {
+; CHECK-LABEL: f9:
+; CHECK: rosbg %r2, %r3, 0, 63, 47
+; CHECK: br %r14
+  %shlb = shl i64 %b, 47
+  %shrb = lshr i64 %b, 17
+  %rotlb = or i64 %shlb, %shrb
+  %or = or i64 %a, %rotlb
+  ret i64 %or
+}
+
+; Test a case with a shift and AND.
+define i32 @f10(i32 %a, i32 %b) {
+; CHECK-LABEL: f10:
+; CHECK: rosbg %r2, %r3, 56, 59, 4
+; CHECK: br %r14
+  %shrb = shl i32 %b, 4
+  %andb = and i32 %shrb, 240
+  %or = or i32 %a, %andb
+  ret i32 %or
+}
+
+; ...and again with i64.
+define i64 @f11(i64 %a, i64 %b) {
+; CHECK-LABEL: f11:
+; CHECK: rosbg %r2, %r3, 56, 59, 4
+; CHECK: br %r14
+  %shrb = shl i64 %b, 4
+  %andb = and i64 %shrb, 240
+  %or = or i64 %a, %andb
+  ret i64 %or
+}
diff --git a/test/CodeGen/SystemZ/rxsbg-01.ll b/test/CodeGen/SystemZ/rxsbg-01.ll
new file mode 100644
index 0000000..5491bff
--- /dev/null
+++ b/test/CodeGen/SystemZ/rxsbg-01.ll
@@ -0,0 +1,112 @@
+; Test sequences that can use RXSBG.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+; Test the simple case.
+define i32 @f1(i32 %a, i32 %b) {
+; CHECK-LABEL: f1:
+; CHECK: rxsbg %r2, %r3, 59, 59, 0
+; CHECK: br %r14
+  %andb = and i32 %b, 16
+  %xor = xor i32 %a, %andb
+  ret i32 %xor
+}
+
+; ...and again with i64.
+define i64 @f2(i64 %a, i64 %b) {
+; CHECK-LABEL: f2:
+; CHECK: rxsbg %r2, %r3, 59, 59, 0
+; CHECK: br %r14
+  %andb = and i64 %b, 16
+  %xor = xor i64 %a, %andb
+  ret i64 %xor
+}
+
+; Test a case where wraparound is needed.
+define i32 @f3(i32 %a, i32 %b) {
+; CHECK-LABEL: f3:
+; CHECK: rxsbg %r2, %r3, 63, 60, 0
+; CHECK: br %r14
+  %andb = and i32 %b, -7
+  %xor = xor i32 %a, %andb
+  ret i32 %xor
+}
+
+; ...and again with i64.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: rxsbg %r2, %r3, 63, 60, 0
+; CHECK: br %r14
+  %andb = and i64 %b, -7
+  %xor = xor i64 %a, %andb
+  ret i64 %xor
+}
+
+; Test a case with just a shift.
+define i32 @f6(i32 %a, i32 %b) {
+; CHECK-LABEL: f6:
+; CHECK: rxsbg %r2, %r3, 32, 51, 12
+; CHECK: br %r14
+  %shlb = shl i32 %b, 12
+  %xor = xor i32 %a, %shlb
+  ret i32 %xor
+}
+
+; ...and again with i64.
+define i64 @f7(i64 %a, i64 %b) {
+; CHECK-LABEL: f7:
+; CHECK: rxsbg %r2, %r3, 0, 51, 12
+; CHECK: br %r14
+  %shlb = shl i64 %b, 12
+  %xor = xor i64 %a, %shlb
+  ret i64 %xor
+}
+
+; Test a case with just a rotate (using XOR for the rotate combination too,
+; to test that this kind of rotate does get recognised by the target-
+; independent code).  This can't use RXSBG.
+define i32 @f8(i32 %a, i32 %b) {
+; CHECK-LABEL: f8:
+; CHECK: rll {{%r[0-5]}}
+; CHECK: xr {{%r[0-5]}}
+; CHECK: br %r14
+  %shlb = shl i32 %b, 30
+  %shrb = lshr i32 %b, 2
+  %rotlb = xor i32 %shlb, %shrb
+  %xor = xor i32 %a, %rotlb
+  ret i32 %xor
+}
+
+; ...and again with i64, which can use RXSBG for the rotate.
+define i64 @f9(i64 %a, i64 %b) {
+; CHECK-LABEL: f9:
+; CHECK: rxsbg %r2, %r3, 0, 63, 47
+; CHECK: br %r14
+  %shlb = shl i64 %b, 47
+  %shrb = lshr i64 %b, 17
+  %rotlb = xor i64 %shlb, %shrb
+  %xor = xor i64 %a, %rotlb
+  ret i64 %xor
+}
+
+; Test a case with a shift and AND.
+define i32 @f10(i32 %a, i32 %b) {
+; CHECK-LABEL: f10:
+; CHECK: rxsbg %r2, %r3, 56, 59, 4
+; CHECK: br %r14
+  %shlb = shl i32 %b, 4
+  %andb = and i32 %shlb, 240
+  %xor = xor i32 %a, %andb
+  ret i32 %xor
+}
+
+; ...and again with i64.
+define i64 @f11(i64 %a, i64 %b) {
+; CHECK-LABEL: f11:
+; CHECK: rxsbg %r2, %r3, 56, 59, 4
+; CHECK: br %r14
+  %shlb = shl i64 %b, 4
+  %andb = and i64 %shlb, 240
+  %xor = xor i64 %a, %andb
+  ret i64 %xor
+}
diff --git a/test/CodeGen/SystemZ/shift-01.ll b/test/CodeGen/SystemZ/shift-01.ll
index e5a459a..5dab36b 100644
--- a/test/CodeGen/SystemZ/shift-01.ll
+++ b/test/CodeGen/SystemZ/shift-01.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SLL range.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sll %r2, 1
 ; CHECK: br %r14
   %shift = shl i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the defined SLL range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sll %r2, 31
 ; CHECK: br %r14
   %shift = shl i32 %a, 31
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: sll %r2, 32
 ; CHECK: br %r14
   %shift = shl i32 %a, 32
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; Make sure that we don't generate negative shift amounts.
 define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: sll %r2, -1{{.*}}
 ; CHECK: br %r14
   %sub = sub i32 %amt, 1
@@ -41,7 +41,7 @@ define i32 @f4(i32 %a, i32 %amt) {
 
 ; Check variable shifts.
 define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sll %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = shl i32 %a, %amt
@@ -50,7 +50,7 @@ define i32 @f5(i32 %a, i32 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i32 @f6(i32 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sll %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -60,7 +60,7 @@ define i32 @f6(i32 %a, i32 %amt) {
 
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sll %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -72,7 +72,7 @@ define i32 @f7(i32 %a, i64 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sll %r2, 4095(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 4095
@@ -82,7 +82,7 @@ define i32 @f8(i32 %a, i32 %amt) {
 
 ; Check the next value up.  Again, we could mask the amount instead.
 define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ahi %r3, 4096
 ; CHECK: sll %r2, 0(%r3)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i32 @f9(i32 %a, i32 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f10(i32 %a, i32 %b, i32 %c) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ar {{%r3, %r4|%r4, %r3}}
 ; CHECK: sll %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f11(i32 %a, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: sll %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-02.ll b/test/CodeGen/SystemZ/shift-02.ll
index 38093a8..27e73cd 100644
--- a/test/CodeGen/SystemZ/shift-02.ll
+++ b/test/CodeGen/SystemZ/shift-02.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SRL range.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: srl %r2, 1
 ; CHECK: br %r14
   %shift = lshr i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the defined SRL range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: srl %r2, 31
 ; CHECK: br %r14
   %shift = lshr i32 %a, 31
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: srl %r2, 32
 ; CHECK: br %r14
   %shift = lshr i32 %a, 32
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; Make sure that we don't generate negative shift amounts.
 define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: srl %r2, -1{{.*}}
 ; CHECK: br %r14
   %sub = sub i32 %amt, 1
@@ -41,7 +41,7 @@ define i32 @f4(i32 %a, i32 %amt) {
 
 ; Check variable shifts.
 define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: srl %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = lshr i32 %a, %amt
@@ -50,7 +50,7 @@ define i32 @f5(i32 %a, i32 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i32 @f6(i32 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: srl %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -60,7 +60,7 @@ define i32 @f6(i32 %a, i32 %amt) {
 
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: srl %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -72,7 +72,7 @@ define i32 @f7(i32 %a, i64 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: srl %r2, 4095(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 4095
@@ -82,7 +82,7 @@ define i32 @f8(i32 %a, i32 %amt) {
 
 ; Check the next value up.  Again, we could mask the amount instead.
 define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ahi %r3, 4096
 ; CHECK: srl %r2, 0(%r3)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i32 @f9(i32 %a, i32 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f10(i32 %a, i32 %b, i32 %c) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ar {{%r3, %r4|%r4, %r3}}
 ; CHECK: srl %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f11(i32 %a, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: srl %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-03.ll b/test/CodeGen/SystemZ/shift-03.ll
index ca510f3..c45ae48 100644
--- a/test/CodeGen/SystemZ/shift-03.ll
+++ b/test/CodeGen/SystemZ/shift-03.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SRA range.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sra %r2, 1
 ; CHECK: br %r14
   %shift = ashr i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the defined SRA range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sra %r2, 31
 ; CHECK: br %r14
   %shift = ashr i32 %a, 31
@@ -22,7 +22,7 @@ define i32 @f2(i32 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: sra %r2, 32
 ; CHECK: br %r14
   %shift = ashr i32 %a, 32
@@ -31,7 +31,7 @@ define i32 @f3(i32 %a) {
 
 ; Make sure that we don't generate negative shift amounts.
 define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NOT: sra %r2, -1{{.*}}
 ; CHECK: br %r14
   %sub = sub i32 %amt, 1
@@ -41,7 +41,7 @@ define i32 @f4(i32 %a, i32 %amt) {
 
 ; Check variable shifts.
 define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sra %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = ashr i32 %a, %amt
@@ -50,7 +50,7 @@ define i32 @f5(i32 %a, i32 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i32 @f6(i32 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sra %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -60,7 +60,7 @@ define i32 @f6(i32 %a, i32 %amt) {
 
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sra %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -72,7 +72,7 @@ define i32 @f7(i32 %a, i64 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sra %r2, 4095(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 4095
@@ -82,7 +82,7 @@ define i32 @f8(i32 %a, i32 %amt) {
 
 ; Check the next value up.  Again, we could mask the amount instead.
 define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: ahi %r3, 4096
 ; CHECK: sra %r2, 0(%r3)
 ; CHECK: br %r14
@@ -93,7 +93,7 @@ define i32 @f9(i32 %a, i32 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f10(i32 %a, i32 %b, i32 %c) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: ar {{%r3, %r4|%r4, %r3}}
 ; CHECK: sra %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -104,7 +104,7 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f11(i32 %a, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: sra %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-04.ll b/test/CodeGen/SystemZ/shift-04.ll
index 0146a86..04b39d0 100644
--- a/test/CodeGen/SystemZ/shift-04.ll
+++ b/test/CodeGen/SystemZ/shift-04.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the RLL range.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: rll %r2, %r2, 1
 ; CHECK: br %r14
   %parta = shl i32 %a, 1
@@ -15,7 +15,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the defined RLL range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: rll %r2, %r2, 31
 ; CHECK: br %r14
   %parta = shl i32 %a, 31
@@ -26,7 +26,7 @@ define i32 @f2(i32 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: rll
 ; CHECK: br %r14
   %parta = shl i32 %a, 32
@@ -37,7 +37,7 @@ define i32 @f3(i32 %a) {
 
 ; Check variable shifts.
 define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: rll %r2, %r2, 0(%r3)
 ; CHECK: br %r14
   %amtb = sub i32 32, %amt
@@ -49,7 +49,7 @@ define i32 @f4(i32 %a, i32 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: rll %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -62,7 +62,7 @@ define i32 @f5(i32 %a, i32 %amt) {
 
 ; ...and again with a truncated 64-bit shift amount.
 define i32 @f6(i32 %a, i64 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: rll %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -76,7 +76,7 @@ define i32 @f6(i32 %a, i64 %amt) {
 
 ; ...and again with a different truncation representation.
 define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: rll %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -92,7 +92,7 @@ define i32 @f7(i32 %a, i64 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: rll %r2, %r2, 524287(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 524287
@@ -106,7 +106,7 @@ define i32 @f8(i32 %a, i32 %amt) {
 ; Check the next value up, which without masking must use a separate
 ; addition.
 define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: afi %r3, 524288
 ; CHECK: rll %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -120,7 +120,7 @@ define i32 @f9(i32 %a, i32 %amt) {
 
 ; Check cases where 1 is subtracted from the shift amount.
 define i32 @f10(i32 %a, i32 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: rll %r2, %r2, -1(%r3)
 ; CHECK: br %r14
   %suba = sub i32 %amt, 1
@@ -134,7 +134,7 @@ define i32 @f10(i32 %a, i32 %amt) {
 ; Check the lowest value that can be subtracted from the shift amount.
 ; Again, we could mask the shift amount instead.
 define i32 @f11(i32 %a, i32 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: rll %r2, %r2, -524288(%r3)
 ; CHECK: br %r14
   %suba = sub i32 %amt, 524288
@@ -148,7 +148,7 @@ define i32 @f11(i32 %a, i32 %amt) {
 ; Check the next value down, which without masking must use a separate
 ; addition.
 define i32 @f12(i32 %a, i32 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: afi %r3, -524289
 ; CHECK: rll %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -162,7 +162,7 @@ define i32 @f12(i32 %a, i32 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i32 @f13(i32 %a, i32 %b, i32 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: ar {{%r3, %r4|%r4, %r3}}
 ; CHECK: rll %r2, %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -176,7 +176,7 @@ define i32 @f13(i32 %a, i32 %b, i32 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i32 @f14(i32 %a, i32 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l %r1, 0(%r3)
 ; CHECK: rll %r2, %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-05.ll b/test/CodeGen/SystemZ/shift-05.ll
index 8c0ca93..833b2fb 100644
--- a/test/CodeGen/SystemZ/shift-05.ll
+++ b/test/CodeGen/SystemZ/shift-05.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SLLG range.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: sllg %r2, %r2, 1
 ; CHECK: br %r14
   %shift = shl i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the defined SLLG range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sllg %r2, %r2, 63
 ; CHECK: br %r14
   %shift = shl i64 %a, 63
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: sllg
 ; CHECK: br %r14
   %shift = shl i64 %a, 64
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = shl i64 %a, %amt
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a, i64 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -50,7 +50,7 @@ define i64 @f5(i64 %a, i64 %amt) {
 
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: sllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -61,7 +61,7 @@ define i64 @f6(i64 %a, i32 %amt) {
 
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: sllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -73,7 +73,7 @@ define i64 @f7(i64 %a, i32 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: sllg %r2, %r2, 524287(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 524287
@@ -84,7 +84,7 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; Check the next value up, which without masking must use a separate
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: a{{g?}}fi %r3, 524288
 ; CHECK: sllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f9(i64 %a, i64 %amt) {
 
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: sllg %r2, %r2, -1(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 1
@@ -106,7 +106,7 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Check the lowest value that can be subtracted from the shift amount.
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: sllg %r2, %r2, -524288(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 524288
@@ -117,7 +117,7 @@ define i64 @f11(i64 %a, i64 %amt) {
 ; Check the next value down, which without masking must use a separate
 ; addition.
 define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: a{{g?}}fi %r3, -524289
 ; CHECK: sllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -128,7 +128,7 @@ define i64 @f12(i64 %a, i64 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
 ; CHECK: sllg %r2, %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -139,7 +139,7 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: sllg %r2, %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-06.ll b/test/CodeGen/SystemZ/shift-06.ll
index 5f600b4..74cae12 100644
--- a/test/CodeGen/SystemZ/shift-06.ll
+++ b/test/CodeGen/SystemZ/shift-06.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SRLG range.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: srlg %r2, %r2, 1
 ; CHECK: br %r14
   %shift = lshr i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the defined SRLG range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: srlg %r2, %r2, 63
 ; CHECK: br %r14
   %shift = lshr i64 %a, 63
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: srlg
 ; CHECK: br %r14
   %shift = lshr i64 %a, 64
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: srlg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = lshr i64 %a, %amt
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a, i64 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: srlg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -50,7 +50,7 @@ define i64 @f5(i64 %a, i64 %amt) {
 
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: srlg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -61,7 +61,7 @@ define i64 @f6(i64 %a, i32 %amt) {
 
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: srlg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -73,7 +73,7 @@ define i64 @f7(i64 %a, i32 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: srlg %r2, %r2, 524287(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 524287
@@ -84,7 +84,7 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; Check the next value up, which without masking must use a separate
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: a{{g?}}fi %r3, 524288
 ; CHECK: srlg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f9(i64 %a, i64 %amt) {
 
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: srlg %r2, %r2, -1(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 1
@@ -106,7 +106,7 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Check the lowest value that can be subtracted from the shift amount.
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: srlg %r2, %r2, -524288(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 524288
@@ -117,7 +117,7 @@ define i64 @f11(i64 %a, i64 %amt) {
 ; Check the next value down, which without masking must use a separate
 ; addition.
 define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: a{{g?}}fi %r3, -524289
 ; CHECK: srlg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -128,7 +128,7 @@ define i64 @f12(i64 %a, i64 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
 ; CHECK: srlg %r2, %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -139,7 +139,7 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: srlg %r2, %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-07.ll b/test/CodeGen/SystemZ/shift-07.ll
index ef583e8..712849d 100644
--- a/test/CodeGen/SystemZ/shift-07.ll
+++ b/test/CodeGen/SystemZ/shift-07.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the SRAG range.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: srag %r2, %r2, 1
 ; CHECK: br %r14
   %shift = ashr i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the defined SRAG range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: srag %r2, %r2, 63
 ; CHECK: br %r14
   %shift = ashr i64 %a, 63
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: srag
 ; CHECK: br %r14
   %shift = ashr i64 %a, 64
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: srag %r2, %r2, 0(%r3)
 ; CHECK: br %r14
   %shift = ashr i64 %a, %amt
@@ -40,7 +40,7 @@ define i64 @f4(i64 %a, i64 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: srag %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -50,7 +50,7 @@ define i64 @f5(i64 %a, i64 %amt) {
 
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: srag %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -61,7 +61,7 @@ define i64 @f6(i64 %a, i32 %amt) {
 
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: srag %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -73,7 +73,7 @@ define i64 @f7(i64 %a, i32 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: srag %r2, %r2, 524287(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 524287
@@ -84,7 +84,7 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; Check the next value up, which without masking must use a separate
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: a{{g?}}fi %r3, 524288
 ; CHECK: srag %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -95,7 +95,7 @@ define i64 @f9(i64 %a, i64 %amt) {
 
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: srag %r2, %r2, -1(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 1
@@ -106,7 +106,7 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Check the lowest value that can be subtracted from the shift amount.
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: srag %r2, %r2, -524288(%r3)
 ; CHECK: br %r14
   %sub = sub i64 %amt, 524288
@@ -117,7 +117,7 @@ define i64 @f11(i64 %a, i64 %amt) {
 ; Check the next value down, which without masking must use a separate
 ; addition.
 define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: a{{g?}}fi %r3, -524289
 ; CHECK: srag %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -128,7 +128,7 @@ define i64 @f12(i64 %a, i64 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
 ; CHECK: srag %r2, %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -139,7 +139,7 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: srag %r2, %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-08.ll b/test/CodeGen/SystemZ/shift-08.ll
index 0688a06..47283b5 100644
--- a/test/CodeGen/SystemZ/shift-08.ll
+++ b/test/CodeGen/SystemZ/shift-08.ll
@@ -4,7 +4,7 @@
 
 ; Check the low end of the RLLG range.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: rllg %r2, %r2, 1
 ; CHECK: br %r14
   %parta = shl i64 %a, 1
@@ -15,7 +15,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the defined RLLG range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: rllg %r2, %r2, 63
 ; CHECK: br %r14
   %parta = shl i64 %a, 63
@@ -26,7 +26,7 @@ define i64 @f2(i64 %a) {
 
 ; We don't generate shifts by out-of-range values.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NOT: rllg
 ; CHECK: br %r14
   %parta = shl i64 %a, 64
@@ -37,7 +37,7 @@ define i64 @f3(i64 %a) {
 
 ; Check variable shifts.
 define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: rllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
   %amtb = sub i64 64, %amt
@@ -49,7 +49,7 @@ define i64 @f4(i64 %a, i64 %amt) {
 
 ; Check shift amounts that have a constant term.
 define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: rllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 10
@@ -62,7 +62,7 @@ define i64 @f5(i64 %a, i64 %amt) {
 
 ; ...and again with a sign-extended 32-bit shift amount.
 define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: rllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -77,7 +77,7 @@ define i64 @f6(i64 %a, i32 %amt) {
 
 ; ...and now with a zero-extended 32-bit shift amount.
 define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: rllg %r2, %r2, 10(%r3)
 ; CHECK: br %r14
   %add = add i32 %amt, 10
@@ -93,7 +93,7 @@ define i64 @f7(i64 %a, i32 %amt) {
 ; Check shift amounts that have the largest in-range constant term.  We could
 ; mask the amount instead.
 define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: rllg %r2, %r2, 524287(%r3)
 ; CHECK: br %r14
   %add = add i64 %amt, 524287
@@ -107,7 +107,7 @@ define i64 @f8(i64 %a, i64 %amt) {
 ; Check the next value up, which without masking must use a separate
 ; addition.
 define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: a{{g?}}fi %r3, 524288
 ; CHECK: rllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -121,7 +121,7 @@ define i64 @f9(i64 %a, i64 %amt) {
 
 ; Check cases where 1 is subtracted from the shift amount.
 define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: rllg %r2, %r2, -1(%r3)
 ; CHECK: br %r14
   %suba = sub i64 %amt, 1
@@ -135,7 +135,7 @@ define i64 @f10(i64 %a, i64 %amt) {
 ; Check the lowest value that can be subtracted from the shift amount.
 ; Again, we could mask the shift amount instead.
 define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: rllg %r2, %r2, -524288(%r3)
 ; CHECK: br %r14
   %suba = sub i64 %amt, 524288
@@ -149,7 +149,7 @@ define i64 @f11(i64 %a, i64 %amt) {
 ; Check the next value down, which without masking must use a separate
 ; addition.
 define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: a{{g?}}fi %r3, -524289
 ; CHECK: rllg %r2, %r2, 0(%r3)
 ; CHECK: br %r14
@@ -163,7 +163,7 @@ define i64 @f12(i64 %a, i64 %amt) {
 
 ; Check that we don't try to generate "indexed" shifts.
 define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
 ; CHECK: rllg %r2, %r2, 0({{%r[34]}})
 ; CHECK: br %r14
@@ -177,7 +177,7 @@ define i64 @f13(i64 %a, i64 %b, i64 %c) {
 
 ; Check that the shift amount uses an address register.  It cannot be in %r0.
 define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
 ; CHECK: l %r1, 4(%r3)
 ; CHECK: rllg %r2, %r2, 0(%r1)
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/shift-09.ll b/test/CodeGen/SystemZ/shift-09.ll
new file mode 100644
index 0000000..c87cf0d
--- /dev/null
+++ b/test/CodeGen/SystemZ/shift-09.ll
@@ -0,0 +1,63 @@
+; Test three-operand shifts.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check that we use SLLK over SLL where useful.
+define i32 @f1(i32 %a, i32 %b, i32 %amt) {
+; CHECK-LABEL: f1:
+; CHECK: sllk %r2, %r3, 15(%r4)
+; CHECK: br %r14
+  %add = add i32 %amt, 15
+  %shift = shl i32 %b, %add
+  ret i32 %shift
+}
+
+; Check that we use SLL over SLLK where possible.
+define i32 @f2(i32 %a, i32 %amt) {
+; CHECK-LABEL: f2:
+; CHECK: sll %r2, 15(%r3)
+; CHECK: br %r14
+  %add = add i32 %amt, 15
+  %shift = shl i32 %a, %add
+  ret i32 %shift
+}
+
+; Check that we use SRLK over SRL where useful.
+define i32 @f3(i32 %a, i32 %b, i32 %amt) {
+; CHECK-LABEL: f3:
+; CHECK: srlk %r2, %r3, 15(%r4)
+; CHECK: br %r14
+  %add = add i32 %amt, 15
+  %shift = lshr i32 %b, %add
+  ret i32 %shift
+}
+
+; Check that we use SRL over SRLK where possible.
+define i32 @f4(i32 %a, i32 %amt) {
+; CHECK-LABEL: f4:
+; CHECK: srl %r2, 15(%r3)
+; CHECK: br %r14
+  %add = add i32 %amt, 15
+  %shift = lshr i32 %a, %add
+  ret i32 %shift
+}
+
+; Check that we use SRAK over SRA where useful.
+define i32 @f5(i32 %a, i32 %b, i32 %amt) {
+; CHECK-LABEL: f5:
+; CHECK: srak %r2, %r3, 15(%r4)
+; CHECK: br %r14
+  %add = add i32 %amt, 15
+  %shift = ashr i32 %b, %add
+  ret i32 %shift
+}
+
+; Check that we use SRA over SRAK where possible.
+define i32 @f6(i32 %a, i32 %amt) {
+; CHECK-LABEL: f6:
+; CHECK: sra %r2, 15(%r3)
+; CHECK: br %r14
+  %add = add i32 %amt, 15
+  %shift = ashr i32 %a, %add
+  ret i32 %shift
+}
diff --git a/test/CodeGen/SystemZ/spill-01.ll b/test/CodeGen/SystemZ/spill-01.ll
new file mode 100644
index 0000000..9de89d6
--- /dev/null
+++ b/test/CodeGen/SystemZ/spill-01.ll
@@ -0,0 +1,547 @@
+; Test spilling using MVC.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare void @foo()
+
+@g0 = global i32 0
+@g1 = global i32 1
+@g2 = global i32 2
+@g3 = global i32 3
+@g4 = global i32 4
+@g5 = global i32 5
+@g6 = global i32 6
+@g7 = global i32 7
+@g8 = global i32 8
+@g9 = global i32 9
+
+@h0 = global i64 0
+@h1 = global i64 1
+@h2 = global i64 2
+@h3 = global i64 3
+@h4 = global i64 4
+@h5 = global i64 5
+@h6 = global i64 6
+@h7 = global i64 7
+@h8 = global i64 8
+@h9 = global i64 9
+
+; This function shouldn't spill anything
+define void @f1(i32 *%ptr0) {
+; CHECK-LABEL: f1:
+; CHECK: stmg
+; CHECK: aghi %r15, -160
+; CHECK-NOT: %r15
+; CHECK: brasl %r14, foo@PLT
+; CHECK-NOT: %r15
+; CHECK: lmg
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i32 2
+  %ptr2 = getelementptr i32 *%ptr0, i32 4
+  %ptr3 = getelementptr i32 *%ptr0, i32 6
+  %ptr4 = getelementptr i32 *%ptr0, i32 8
+  %ptr5 = getelementptr i32 *%ptr0, i32 10
+  %ptr6 = getelementptr i32 *%ptr0, i32 12
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+
+  call void @foo()
+
+  store i32 %val0, i32 *%ptr0
+  store i32 %val1, i32 *%ptr1
+  store i32 %val2, i32 *%ptr2
+  store i32 %val3, i32 *%ptr3
+  store i32 %val4, i32 *%ptr4
+  store i32 %val5, i32 *%ptr5
+  store i32 %val6, i32 *%ptr6
+
+  ret void
+}
+
+; Test a case where at least one i32 load and at least one i32 store
+; need spills.
+define void @f2(i32 *%ptr0) {
+; CHECK-LABEL: f2:
+; CHECK: mvc [[OFFSET1:16[04]]](4,%r15), [[OFFSET2:[0-9]+]]({{%r[0-9]+}})
+; CHECK: brasl %r14, foo@PLT
+; CHECK: mvc [[OFFSET2]](4,{{%r[0-9]+}}), [[OFFSET1]](%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+
+  call void @foo()
+
+  store i32 %val0, i32 *%ptr0
+  store i32 %val1, i32 *%ptr1
+  store i32 %val2, i32 *%ptr2
+  store i32 %val3, i32 *%ptr3
+  store i32 %val4, i32 *%ptr4
+  store i32 %val5, i32 *%ptr5
+  store i32 %val6, i32 *%ptr6
+  store i32 %val7, i32 *%ptr7
+  store i32 %val8, i32 *%ptr8
+
+  ret void
+}
+
+; Test a case where at least one i64 load and at least one i64 store
+; need spills.
+define void @f3(i64 *%ptr0) {
+; CHECK-LABEL: f3:
+; CHECK: mvc 160(8,%r15), [[OFFSET:[0-9]+]]({{%r[0-9]+}})
+; CHECK: brasl %r14, foo@PLT
+; CHECK: mvc [[OFFSET]](8,{{%r[0-9]+}}), 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64 *%ptr0, i64 16
+
+  %val0 = load i64 *%ptr0
+  %val1 = load i64 *%ptr1
+  %val2 = load i64 *%ptr2
+  %val3 = load i64 *%ptr3
+  %val4 = load i64 *%ptr4
+  %val5 = load i64 *%ptr5
+  %val6 = load i64 *%ptr6
+  %val7 = load i64 *%ptr7
+  %val8 = load i64 *%ptr8
+
+  call void @foo()
+
+  store i64 %val0, i64 *%ptr0
+  store i64 %val1, i64 *%ptr1
+  store i64 %val2, i64 *%ptr2
+  store i64 %val3, i64 *%ptr3
+  store i64 %val4, i64 *%ptr4
+  store i64 %val5, i64 *%ptr5
+  store i64 %val6, i64 *%ptr6
+  store i64 %val7, i64 *%ptr7
+  store i64 %val8, i64 *%ptr8
+
+  ret void
+}
+
+
+; Test a case where at least at least one f32 load and at least one f32 store
+; need spills.  The 8 call-saved FPRs could be used for 8 of the %vals
+; (and are at the time of writing), but it would really be better to use
+; MVC for all 10.
+define void @f4(float *%ptr0) {
+; CHECK-LABEL: f4:
+; CHECK: mvc [[OFFSET1:16[04]]](4,%r15), [[OFFSET2:[0-9]+]]({{%r[0-9]+}})
+; CHECK: brasl %r14, foo@PLT
+; CHECK: mvc [[OFFSET2]](4,{{%r[0-9]+}}), [[OFFSET1]](%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr float *%ptr0, i64 2
+  %ptr2 = getelementptr float *%ptr0, i64 4
+  %ptr3 = getelementptr float *%ptr0, i64 6
+  %ptr4 = getelementptr float *%ptr0, i64 8
+  %ptr5 = getelementptr float *%ptr0, i64 10
+  %ptr6 = getelementptr float *%ptr0, i64 12
+  %ptr7 = getelementptr float *%ptr0, i64 14
+  %ptr8 = getelementptr float *%ptr0, i64 16
+  %ptr9 = getelementptr float *%ptr0, i64 18
+
+  %val0 = load float *%ptr0
+  %val1 = load float *%ptr1
+  %val2 = load float *%ptr2
+  %val3 = load float *%ptr3
+  %val4 = load float *%ptr4
+  %val5 = load float *%ptr5
+  %val6 = load float *%ptr6
+  %val7 = load float *%ptr7
+  %val8 = load float *%ptr8
+  %val9 = load float *%ptr9
+
+  call void @foo()
+
+  store float %val0, float *%ptr0
+  store float %val1, float *%ptr1
+  store float %val2, float *%ptr2
+  store float %val3, float *%ptr3
+  store float %val4, float *%ptr4
+  store float %val5, float *%ptr5
+  store float %val6, float *%ptr6
+  store float %val7, float *%ptr7
+  store float %val8, float *%ptr8
+  store float %val9, float *%ptr9
+
+  ret void
+}
+
+; Similarly for f64.
+define void @f5(double *%ptr0) {
+; CHECK-LABEL: f5:
+; CHECK: mvc 160(8,%r15), [[OFFSET:[0-9]+]]({{%r[0-9]+}})
+; CHECK: brasl %r14, foo@PLT
+; CHECK: mvc [[OFFSET]](8,{{%r[0-9]+}}), 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr double *%ptr0, i64 2
+  %ptr2 = getelementptr double *%ptr0, i64 4
+  %ptr3 = getelementptr double *%ptr0, i64 6
+  %ptr4 = getelementptr double *%ptr0, i64 8
+  %ptr5 = getelementptr double *%ptr0, i64 10
+  %ptr6 = getelementptr double *%ptr0, i64 12
+  %ptr7 = getelementptr double *%ptr0, i64 14
+  %ptr8 = getelementptr double *%ptr0, i64 16
+  %ptr9 = getelementptr double *%ptr0, i64 18
+
+  %val0 = load double *%ptr0
+  %val1 = load double *%ptr1
+  %val2 = load double *%ptr2
+  %val3 = load double *%ptr3
+  %val4 = load double *%ptr4
+  %val5 = load double *%ptr5
+  %val6 = load double *%ptr6
+  %val7 = load double *%ptr7
+  %val8 = load double *%ptr8
+  %val9 = load double *%ptr9
+
+  call void @foo()
+
+  store double %val0, double *%ptr0
+  store double %val1, double *%ptr1
+  store double %val2, double *%ptr2
+  store double %val3, double *%ptr3
+  store double %val4, double *%ptr4
+  store double %val5, double *%ptr5
+  store double %val6, double *%ptr6
+  store double %val7, double *%ptr7
+  store double %val8, double *%ptr8
+  store double %val9, double *%ptr9
+
+  ret void
+}
+
+; Repeat f2 with atomic accesses.  We shouldn't use MVC here.
+define void @f6(i32 *%ptr0) {
+; CHECK-LABEL: f6:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+
+  %val0 = load atomic i32 *%ptr0 unordered, align 4
+  %val1 = load atomic i32 *%ptr1 unordered, align 4
+  %val2 = load atomic i32 *%ptr2 unordered, align 4
+  %val3 = load atomic i32 *%ptr3 unordered, align 4
+  %val4 = load atomic i32 *%ptr4 unordered, align 4
+  %val5 = load atomic i32 *%ptr5 unordered, align 4
+  %val6 = load atomic i32 *%ptr6 unordered, align 4
+  %val7 = load atomic i32 *%ptr7 unordered, align 4
+  %val8 = load atomic i32 *%ptr8 unordered, align 4
+
+  call void @foo()
+
+  store atomic i32 %val0, i32 *%ptr0 unordered, align 4
+  store atomic i32 %val1, i32 *%ptr1 unordered, align 4
+  store atomic i32 %val2, i32 *%ptr2 unordered, align 4
+  store atomic i32 %val3, i32 *%ptr3 unordered, align 4
+  store atomic i32 %val4, i32 *%ptr4 unordered, align 4
+  store atomic i32 %val5, i32 *%ptr5 unordered, align 4
+  store atomic i32 %val6, i32 *%ptr6 unordered, align 4
+  store atomic i32 %val7, i32 *%ptr7 unordered, align 4
+  store atomic i32 %val8, i32 *%ptr8 unordered, align 4
+
+  ret void
+}
+
+; ...likewise volatile accesses.
+define void @f7(i32 *%ptr0) {
+; CHECK-LABEL: f7:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+
+  %val0 = load volatile i32 *%ptr0
+  %val1 = load volatile i32 *%ptr1
+  %val2 = load volatile i32 *%ptr2
+  %val3 = load volatile i32 *%ptr3
+  %val4 = load volatile i32 *%ptr4
+  %val5 = load volatile i32 *%ptr5
+  %val6 = load volatile i32 *%ptr6
+  %val7 = load volatile i32 *%ptr7
+  %val8 = load volatile i32 *%ptr8
+
+  call void @foo()
+
+  store volatile i32 %val0, i32 *%ptr0
+  store volatile i32 %val1, i32 *%ptr1
+  store volatile i32 %val2, i32 *%ptr2
+  store volatile i32 %val3, i32 *%ptr3
+  store volatile i32 %val4, i32 *%ptr4
+  store volatile i32 %val5, i32 *%ptr5
+  store volatile i32 %val6, i32 *%ptr6
+  store volatile i32 %val7, i32 *%ptr7
+  store volatile i32 %val8, i32 *%ptr8
+
+  ret void
+}
+
+; Check that LRL and STRL are not converted.
+define void @f8() {
+; CHECK-LABEL: f8:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  %val0 = load i32 *@g0
+  %val1 = load i32 *@g1
+  %val2 = load i32 *@g2
+  %val3 = load i32 *@g3
+  %val4 = load i32 *@g4
+  %val5 = load i32 *@g5
+  %val6 = load i32 *@g6
+  %val7 = load i32 *@g7
+  %val8 = load i32 *@g8
+  %val9 = load i32 *@g9
+
+  call void @foo()
+
+  store i32 %val0, i32 *@g0
+  store i32 %val1, i32 *@g1
+  store i32 %val2, i32 *@g2
+  store i32 %val3, i32 *@g3
+  store i32 %val4, i32 *@g4
+  store i32 %val5, i32 *@g5
+  store i32 %val6, i32 *@g6
+  store i32 %val7, i32 *@g7
+  store i32 %val8, i32 *@g8
+  store i32 %val9, i32 *@g9
+
+  ret void
+}
+
+; Likewise LGRL and STGRL.
+define void @f9() {
+; CHECK-LABEL: f9:
+; CHECK-NOT: mvc
+; CHECK: br %r14
+  %val0 = load i64 *@h0
+  %val1 = load i64 *@h1
+  %val2 = load i64 *@h2
+  %val3 = load i64 *@h3
+  %val4 = load i64 *@h4
+  %val5 = load i64 *@h5
+  %val6 = load i64 *@h6
+  %val7 = load i64 *@h7
+  %val8 = load i64 *@h8
+  %val9 = load i64 *@h9
+
+  call void @foo()
+
+  store i64 %val0, i64 *@h0
+  store i64 %val1, i64 *@h1
+  store i64 %val2, i64 *@h2
+  store i64 %val3, i64 *@h3
+  store i64 %val4, i64 *@h4
+  store i64 %val5, i64 *@h5
+  store i64 %val6, i64 *@h6
+  store i64 %val7, i64 *@h7
+  store i64 %val8, i64 *@h8
+  store i64 %val9, i64 *@h9
+
+  ret void
+}
+
+; This showed a problem with the way stack coloring updated instructions.
+; The copy from %val9 to %newval8 can be done using an MVC, which then
+; has two frame index operands.  Stack coloring chose a valid renumbering
+; [FI0, FI1] -> [FI1, FI2], but applied it in the form FI0 -> FI1 -> FI2,
+; so that both operands ended up being the same.
+define void @f10() {
+; CHECK-LABEL: f10:
+; CHECK: lgrl [[REG:%r[0-9]+]], h9
+; CHECK: stg [[REG]], [[VAL9:[0-9]+]](%r15)
+; CHECK: brasl %r14, foo@PLT
+; CHECK: brasl %r14, foo@PLT
+; CHECK: mvc [[NEWVAL8:[0-9]+]](8,%r15), [[VAL9]](%r15)
+; CHECK: brasl %r14, foo@PLT
+; CHECK: lg [[REG:%r[0-9]+]], [[NEWVAL8]](%r15)
+; CHECK: stgrl [[REG]], h8
+; CHECK: br %r14
+entry:
+  %val0 = load volatile i64 *@h0
+  %val1 = load volatile i64 *@h1
+  %val2 = load volatile i64 *@h2
+  %val3 = load volatile i64 *@h3
+  %val4 = load volatile i64 *@h4
+  %val5 = load volatile i64 *@h5
+  %val6 = load volatile i64 *@h6
+  %val7 = load volatile i64 *@h7
+  %val8 = load volatile i64 *@h8
+  %val9 = load volatile i64 *@h9
+
+  call void @foo()
+
+  store volatile i64 %val0, i64 *@h0
+  store volatile i64 %val1, i64 *@h1
+  store volatile i64 %val2, i64 *@h2
+  store volatile i64 %val3, i64 *@h3
+  store volatile i64 %val4, i64 *@h4
+  store volatile i64 %val5, i64 *@h5
+  store volatile i64 %val6, i64 *@h6
+  store volatile i64 %val7, i64 *@h7
+
+  %check = load volatile i64 *@h0
+  %cond = icmp eq i64 %check, 0
+  br i1 %cond, label %skip, label %fallthru
+
+fallthru:
+  call void @foo()
+
+  store volatile i64 %val0, i64 *@h0
+  store volatile i64 %val1, i64 *@h1
+  store volatile i64 %val2, i64 *@h2
+  store volatile i64 %val3, i64 *@h3
+  store volatile i64 %val4, i64 *@h4
+  store volatile i64 %val5, i64 *@h5
+  store volatile i64 %val6, i64 *@h6
+  store volatile i64 %val7, i64 *@h7
+  store volatile i64 %val8, i64 *@h8
+  br label %skip
+
+skip:
+  %newval8 = phi i64 [ %val8, %entry ], [ %val9, %fallthru ]
+  call void @foo()
+
+  store volatile i64 %val0, i64 *@h0
+  store volatile i64 %val1, i64 *@h1
+  store volatile i64 %val2, i64 *@h2
+  store volatile i64 %val3, i64 *@h3
+  store volatile i64 %val4, i64 *@h4
+  store volatile i64 %val5, i64 *@h5
+  store volatile i64 %val6, i64 *@h6
+  store volatile i64 %val7, i64 *@h7
+  store volatile i64 %newval8, i64 *@h8
+  store volatile i64 %val9, i64 *@h9
+
+  ret void
+}
+
+; This used to generate a no-op MVC.  It is very sensitive to spill heuristics.
+define void @f11() {
+; CHECK-LABEL: f11:
+; CHECK-NOT: mvc [[OFFSET:[0-9]+]](8,%r15), [[OFFSET]](%r15)
+; CHECK: br %r14
+entry:
+  %val0 = load volatile i64 *@h0
+  %val1 = load volatile i64 *@h1
+  %val2 = load volatile i64 *@h2
+  %val3 = load volatile i64 *@h3
+  %val4 = load volatile i64 *@h4
+  %val5 = load volatile i64 *@h5
+  %val6 = load volatile i64 *@h6
+  %val7 = load volatile i64 *@h7
+
+  %altval0 = load volatile i64 *@h0
+  %altval1 = load volatile i64 *@h1
+
+  call void @foo()
+
+  store volatile i64 %val0, i64 *@h0
+  store volatile i64 %val1, i64 *@h1
+  store volatile i64 %val2, i64 *@h2
+  store volatile i64 %val3, i64 *@h3
+  store volatile i64 %val4, i64 *@h4
+  store volatile i64 %val5, i64 *@h5
+  store volatile i64 %val6, i64 *@h6
+  store volatile i64 %val7, i64 *@h7
+
+  %check = load volatile i64 *@h0
+  %cond = icmp eq i64 %check, 0
+  br i1 %cond, label %a1, label %b1
+
+a1:
+  call void @foo()
+  br label %join1
+
+b1:
+  call void @foo()
+  br label %join1
+
+join1:
+  %newval0 = phi i64 [ %val0, %a1 ], [ %altval0, %b1 ]
+
+  call void @foo()
+
+  store volatile i64 %val1, i64 *@h1
+  store volatile i64 %val2, i64 *@h2
+  store volatile i64 %val3, i64 *@h3
+  store volatile i64 %val4, i64 *@h4
+  store volatile i64 %val5, i64 *@h5
+  store volatile i64 %val6, i64 *@h6
+  store volatile i64 %val7, i64 *@h7
+  br i1 %cond, label %a2, label %b2
+
+a2:
+  call void @foo()
+  br label %join2
+
+b2:
+  call void @foo()
+  br label %join2
+
+join2:
+  %newval1 = phi i64 [ %val1, %a2 ], [ %altval1, %b2 ]
+
+  call void @foo()
+
+  store volatile i64 %val2, i64 *@h2
+  store volatile i64 %val3, i64 *@h3
+  store volatile i64 %val4, i64 *@h4
+  store volatile i64 %val5, i64 *@h5
+  store volatile i64 %val6, i64 *@h6
+  store volatile i64 %val7, i64 *@h7
+
+  call void @foo()
+
+  store volatile i64 %newval0, i64 *@h0
+  store volatile i64 %newval1, i64 *@h1
+  store volatile i64 %val2, i64 *@h2
+  store volatile i64 %val3, i64 *@h3
+  store volatile i64 %val4, i64 *@h4
+  store volatile i64 %val5, i64 *@h5
+  store volatile i64 %val6, i64 *@h6
+  store volatile i64 %val7, i64 *@h7
+
+  ret void
+}
diff --git a/test/CodeGen/SystemZ/tls-01.ll b/test/CodeGen/SystemZ/tls-01.ll
index 49037ad..16bc8f6 100644
--- a/test/CodeGen/SystemZ/tls-01.ll
+++ b/test/CodeGen/SystemZ/tls-01.ll
@@ -11,7 +11,7 @@ define i32 *@foo() {
 ; CHECK-CP: .LCP{{.*}}:
 ; CHECK-CP: .quad x@NTPOFF
 ;
-; CHECK-MAIN: foo:
+; CHECK-MAIN-LABEL: foo:
 ; CHECK-MAIN: ear [[HIGH:%r[0-5]]], %a0
 ; CHECK-MAIN: sllg %r2, [[HIGH]], 32
 ; CHECK-MAIN: ear %r2, %a1
diff --git a/test/CodeGen/SystemZ/unaligned-01.ll b/test/CodeGen/SystemZ/unaligned-01.ll
index be237ac..621069d 100644
--- a/test/CodeGen/SystemZ/unaligned-01.ll
+++ b/test/CodeGen/SystemZ/unaligned-01.ll
@@ -21,7 +21,7 @@ define void @f1(i8 *%ptr) {
 
 ; Check that unaligned 2-byte accesses are allowed.
 define i16 @f2(i16 *%src, i16 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: lh %r2, 0(%r2)
 ; CHECK: sth %r2, 0(%r3)
 ; CHECK: br %r14
@@ -32,7 +32,7 @@ define i16 @f2(i16 *%src, i16 *%dst) {
 
 ; Check that unaligned 4-byte accesses are allowed.
 define i32 @f3(i32 *%src1, i32 *%src2, i32 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: l %r2, 0(%r2)
 ; CHECK: s %r2, 0(%r3)
 ; CHECK: st %r2, 0(%r4)
@@ -46,7 +46,7 @@ define i32 @f3(i32 *%src1, i32 *%src2, i32 *%dst) {
 
 ; Check that unaligned 8-byte accesses are allowed.
 define i64 @f4(i64 *%src1, i64 *%src2, i64 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: lg %r2, 0(%r2)
 ; CHECK: sg %r2, 0(%r3)
 ; CHECK: stg %r2, 0(%r4)
diff --git a/test/CodeGen/SystemZ/xor-01.ll b/test/CodeGen/SystemZ/xor-01.ll
index 30bdbe7..185d6bb 100644
--- a/test/CodeGen/SystemZ/xor-01.ll
+++ b/test/CodeGen/SystemZ/xor-01.ll
@@ -1,10 +1,13 @@
 ; Test 32-bit XORs in which the second operand is variable.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i32 @foo()
 
 ; Check XR.
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xr %r2, %r3
 ; CHECK: br %r14
   %xor = xor i32 %a, %b
@@ -13,7 +16,7 @@ define i32 @f1(i32 %a, i32 %b) {
 
 ; Check the low end of the X range.
 define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: x %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i32 *%src
@@ -23,7 +26,7 @@ define i32 @f2(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned X range.
 define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: x %r2, 4092(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1023
@@ -34,7 +37,7 @@ define i32 @f3(i32 %a, i32 *%src) {
 
 ; Check the next word up, which should use XY instead of X.
 define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xy %r2, 4096(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 1024
@@ -45,7 +48,7 @@ define i32 @f4(i32 %a, i32 *%src) {
 
 ; Check the high end of the aligned XY range.
 define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xy %r2, 524284(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 131071
@@ -57,7 +60,7 @@ define i32 @f5(i32 %a, i32 *%src) {
 ; Check the next word up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: agfi %r3, 524288
 ; CHECK: x %r2, 0(%r3)
 ; CHECK: br %r14
@@ -69,7 +72,7 @@ define i32 @f6(i32 %a, i32 *%src) {
 
 ; Check the high end of the negative aligned XY range.
 define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: xy %r2, -4(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -1
@@ -80,7 +83,7 @@ define i32 @f7(i32 %a, i32 *%src) {
 
 ; Check the low end of the XY range.
 define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: xy %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i32 *%src, i64 -131072
@@ -92,7 +95,7 @@ define i32 @f8(i32 %a, i32 *%src) {
 ; Check the next word down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: agfi %r3, -524292
 ; CHECK: x %r2, 0(%r3)
 ; CHECK: br %r14
@@ -104,7 +107,7 @@ define i32 @f9(i32 %a, i32 *%src) {
 
 ; Check that X allows an index.
 define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: x %r2, 4092({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -117,7 +120,7 @@ define i32 @f10(i32 %a, i64 %src, i64 %index) {
 
 ; Check that XY allows an index.
 define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: xy %r2, 4096({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -127,3 +130,46 @@ define i32 @f11(i32 %a, i64 %src, i64 %index) {
   %xor = xor i32 %a, %b
   ret i32 %xor
 }
+
+; Check that XORs of spilled values can use X rather than XR.
+define i32 @f12(i32 *%ptr0) {
+; CHECK-LABEL: f12:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: x %r2, 16{{[04]}}(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i32 *%ptr0, i64 2
+  %ptr2 = getelementptr i32 *%ptr0, i64 4
+  %ptr3 = getelementptr i32 *%ptr0, i64 6
+  %ptr4 = getelementptr i32 *%ptr0, i64 8
+  %ptr5 = getelementptr i32 *%ptr0, i64 10
+  %ptr6 = getelementptr i32 *%ptr0, i64 12
+  %ptr7 = getelementptr i32 *%ptr0, i64 14
+  %ptr8 = getelementptr i32 *%ptr0, i64 16
+  %ptr9 = getelementptr i32 *%ptr0, i64 18
+
+  %val0 = load i32 *%ptr0
+  %val1 = load i32 *%ptr1
+  %val2 = load i32 *%ptr2
+  %val3 = load i32 *%ptr3
+  %val4 = load i32 *%ptr4
+  %val5 = load i32 *%ptr5
+  %val6 = load i32 *%ptr6
+  %val7 = load i32 *%ptr7
+  %val8 = load i32 *%ptr8
+  %val9 = load i32 *%ptr9
+
+  %ret = call i32 @foo()
+
+  %xor0 = xor i32 %ret, %val0
+  %xor1 = xor i32 %xor0, %val1
+  %xor2 = xor i32 %xor1, %val2
+  %xor3 = xor i32 %xor2, %val3
+  %xor4 = xor i32 %xor3, %val4
+  %xor5 = xor i32 %xor4, %val5
+  %xor6 = xor i32 %xor5, %val6
+  %xor7 = xor i32 %xor6, %val7
+  %xor8 = xor i32 %xor7, %val8
+  %xor9 = xor i32 %xor8, %val9
+
+  ret i32 %xor9
+}
diff --git a/test/CodeGen/SystemZ/xor-02.ll b/test/CodeGen/SystemZ/xor-02.ll
index c2b52b9..7e28e23 100644
--- a/test/CodeGen/SystemZ/xor-02.ll
+++ b/test/CodeGen/SystemZ/xor-02.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful XILF value.
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xilf %r2, 1
 ; CHECK: br %r14
   %xor = xor i32 %a, 1
@@ -13,7 +13,7 @@ define i32 @f1(i32 %a) {
 
 ; Check the high end of the signed range.
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: xilf %r2, 2147483647
 ; CHECK: br %r14
   %xor = xor i32 %a, 2147483647
@@ -23,7 +23,7 @@ define i32 @f2(i32 %a) {
 ; Check the low end of the signed range, which should be treated
 ; as a positive value.
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xilf %r2, 2147483648
 ; CHECK: br %r14
   %xor = xor i32 %a, -2147483648
@@ -32,7 +32,7 @@ define i32 @f3(i32 %a) {
 
 ; Check the high end of the XILF range.
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xilf %r2, 4294967295
 ; CHECK: br %r14
   %xor = xor i32 %a, 4294967295
diff --git a/test/CodeGen/SystemZ/xor-03.ll b/test/CodeGen/SystemZ/xor-03.ll
index a4851b3..ab7f258 100644
--- a/test/CodeGen/SystemZ/xor-03.ll
+++ b/test/CodeGen/SystemZ/xor-03.ll
@@ -1,10 +1,13 @@
 ; Test 64-bit XORs in which the second operand is variable.
 ;
-; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+declare i64 @foo()
 
 ; Check XGR.
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xgr %r2, %r3
 ; CHECK: br %r14
   %xor = xor i64 %a, %b
@@ -13,7 +16,7 @@ define i64 @f1(i64 %a, i64 %b) {
 
 ; Check XG with no displacement.
 define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: xg %r2, 0(%r3)
 ; CHECK: br %r14
   %b = load i64 *%src
@@ -23,7 +26,7 @@ define i64 @f2(i64 %a, i64 *%src) {
 
 ; Check the high end of the aligned XG range.
 define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xg %r2, 524280(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 65535
@@ -35,7 +38,7 @@ define i64 @f3(i64 %a, i64 *%src) {
 ; Check the next doubleword up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: agfi %r3, 524288
 ; CHECK: xg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -47,7 +50,7 @@ define i64 @f4(i64 %a, i64 *%src) {
 
 ; Check the high end of the negative aligned XG range.
 define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xg %r2, -8(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -1
@@ -58,7 +61,7 @@ define i64 @f5(i64 %a, i64 *%src) {
 
 ; Check the low end of the XG range.
 define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xg %r2, -524288(%r3)
 ; CHECK: br %r14
   %ptr = getelementptr i64 *%src, i64 -65536
@@ -70,7 +73,7 @@ define i64 @f6(i64 %a, i64 *%src) {
 ; Check the next doubleword down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: agfi %r3, -524296
 ; CHECK: xg %r2, 0(%r3)
 ; CHECK: br %r14
@@ -82,7 +85,7 @@ define i64 @f7(i64 %a, i64 *%src) {
 
 ; Check that XG allows an index.
 define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: xg %r2, 524280({{%r4,%r3|%r3,%r4}})
 ; CHECK: br %r14
   %add1 = add i64 %src, %index
@@ -92,3 +95,46 @@ define i64 @f8(i64 %a, i64 %src, i64 %index) {
   %xor = xor i64 %a, %b
   ret i64 %xor
 }
+
+; Check that XORs of spilled values can use OG rather than OGR.
+define i64 @f9(i64 *%ptr0) {
+; CHECK-LABEL: f9:
+; CHECK: brasl %r14, foo@PLT
+; CHECK: xg %r2, 160(%r15)
+; CHECK: br %r14
+  %ptr1 = getelementptr i64 *%ptr0, i64 2
+  %ptr2 = getelementptr i64 *%ptr0, i64 4
+  %ptr3 = getelementptr i64 *%ptr0, i64 6
+  %ptr4 = getelementptr i64 *%ptr0, i64 8
+  %ptr5 = getelementptr i64 *%ptr0, i64 10
+  %ptr6 = getelementptr i64 *%ptr0, i64 12
+  %ptr7 = getelementptr i64 *%ptr0, i64 14
+  %ptr8 = getelementptr i64 *%ptr0, i64 16
+  %ptr9 = getelementptr i64 *%ptr0, i64 18
+
+  %val0 = load i64 *%ptr0
+  %val1 = load i64 *%ptr1
+  %val2 = load i64 *%ptr2
+  %val3 = load i64 *%ptr3
+  %val4 = load i64 *%ptr4
+  %val5 = load i64 *%ptr5
+  %val6 = load i64 *%ptr6
+  %val7 = load i64 *%ptr7
+  %val8 = load i64 *%ptr8
+  %val9 = load i64 *%ptr9
+
+  %ret = call i64 @foo()
+
+  %xor0 = xor i64 %ret, %val0
+  %xor1 = xor i64 %xor0, %val1
+  %xor2 = xor i64 %xor1, %val2
+  %xor3 = xor i64 %xor2, %val3
+  %xor4 = xor i64 %xor3, %val4
+  %xor5 = xor i64 %xor4, %val5
+  %xor6 = xor i64 %xor5, %val6
+  %xor7 = xor i64 %xor6, %val7
+  %xor8 = xor i64 %xor7, %val8
+  %xor9 = xor i64 %xor8, %val9
+
+  ret i64 %xor9
+}
diff --git a/test/CodeGen/SystemZ/xor-04.ll b/test/CodeGen/SystemZ/xor-04.ll
index cc141d3..44f0a4c 100644
--- a/test/CodeGen/SystemZ/xor-04.ll
+++ b/test/CodeGen/SystemZ/xor-04.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful XILF value.
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xilf %r2, 1
 ; CHECK: br %r14
   %xor = xor i64 %a, 1
@@ -13,7 +13,7 @@ define i64 @f1(i64 %a) {
 
 ; Check the high end of the XILF range.
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: xilf %r2, 4294967295
 ; CHECK: br %r14
   %xor = xor i64 %a, 4294967295
@@ -22,7 +22,7 @@ define i64 @f2(i64 %a) {
 
 ; Check the lowest useful XIHF value, which is one up from the above.
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xihf %r2, 1
 ; CHECK: br %r14
   %xor = xor i64 %a, 4294967296
@@ -31,7 +31,7 @@ define i64 @f3(i64 %a) {
 
 ; Check the next value up again, which needs a combination of XIHF and XILF.
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xihf %r2, 1
 ; CHECK: xilf %r2, 4294967295
 ; CHECK: br %r14
@@ -41,7 +41,7 @@ define i64 @f4(i64 %a) {
 
 ; Check the high end of the XIHF range.
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xihf %r2, 4294967295
 ; CHECK: br %r14
   %xor = xor i64 %a, -4294967296
@@ -50,7 +50,7 @@ define i64 @f5(i64 %a) {
 
 ; Check the next value up, which again must use XIHF and XILF.
 define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xihf %r2, 4294967295
 ; CHECK: xilf %r2, 1
 ; CHECK: br %r14
@@ -60,7 +60,7 @@ define i64 @f6(i64 %a) {
 
 ; Check full bitwise negation
 define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: xihf %r2, 4294967295
 ; CHECK: xilf %r2, 4294967295
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/xor-05.ll b/test/CodeGen/SystemZ/xor-05.ll
index 9ef0d20..fbd5660 100644
--- a/test/CodeGen/SystemZ/xor-05.ll
+++ b/test/CodeGen/SystemZ/xor-05.ll
@@ -4,7 +4,7 @@
 
 ; Check the lowest useful constant, expressed as a signed integer.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -15,7 +15,7 @@ define void @f1(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a signed integer.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -26,7 +26,7 @@ define void @f2(i8 *%ptr) {
 
 ; Check the lowest useful constant, expressed as an unsigned integer.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xi 0(%r2), 1
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -37,7 +37,7 @@ define void @f3(i8 *%ptr) {
 
 ; Check the highest useful constant, expressed as a unsigned integer.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -48,7 +48,7 @@ define void @f4(i8 *%ptr) {
 
 ; Check the high end of the XI range.
 define void @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xi 4095(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4095
@@ -60,7 +60,7 @@ define void @f5(i8 *%src) {
 
 ; Check the next byte up, which should use XIY instead of XI.
 define void @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xiy 4096(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 4096
@@ -72,7 +72,7 @@ define void @f6(i8 *%src) {
 
 ; Check the high end of the XIY range.
 define void @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: xiy 524287(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 524287
@@ -85,7 +85,7 @@ define void @f7(i8 *%src) {
 ; Check the next byte up, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: agfi %r2, 524288
 ; CHECK: xi 0(%r2), 127
 ; CHECK: br %r14
@@ -98,7 +98,7 @@ define void @f8(i8 *%src) {
 
 ; Check the high end of the negative XIY range.
 define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: xiy -1(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -1
@@ -110,7 +110,7 @@ define void @f9(i8 *%src) {
 
 ; Check the low end of the XIY range.
 define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: xiy -524288(%r2), 127
 ; CHECK: br %r14
   %ptr = getelementptr i8 *%src, i64 -524288
@@ -123,7 +123,7 @@ define void @f10(i8 *%src) {
 ; Check the next byte down, which needs separate address logic.
 ; Other sequences besides this one would be OK.
 define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: agfi %r2, -524289
 ; CHECK: xi 0(%r2), 127
 ; CHECK: br %r14
@@ -136,7 +136,7 @@ define void @f11(i8 *%src) {
 
 ; Check that XI does not allow an index
 define void @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: agr %r2, %r3
 ; CHECK: xi 4095(%r2), 127
 ; CHECK: br %r14
@@ -151,7 +151,7 @@ define void @f12(i64 %src, i64 %index) {
 
 ; Check that XIY does not allow an index
 define void @f13(i64 %src, i64 %index) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
 ; CHECK: agr %r2, %r3
 ; CHECK: xiy 4096(%r2), 127
 ; CHECK: br %r14
diff --git a/test/CodeGen/SystemZ/xor-06.ll b/test/CodeGen/SystemZ/xor-06.ll
index 0ffff47..f39c0fe 100644
--- a/test/CodeGen/SystemZ/xor-06.ll
+++ b/test/CodeGen/SystemZ/xor-06.ll
@@ -5,7 +5,7 @@
 
 ; Zero extension to 32 bits, negative constant.
 define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -18,7 +18,7 @@ define void @f1(i8 *%ptr) {
 
 ; Zero extension to 64 bits, negative constant.
 define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -31,7 +31,7 @@ define void @f2(i8 *%ptr) {
 
 ; Zero extension to 32 bits, positive constant.
 define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -44,7 +44,7 @@ define void @f3(i8 *%ptr) {
 
 ; Zero extension to 64 bits, positive constant.
 define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -57,7 +57,7 @@ define void @f4(i8 *%ptr) {
 
 ; Sign extension to 32 bits, negative constant.
 define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -70,7 +70,7 @@ define void @f5(i8 *%ptr) {
 
 ; Sign extension to 64 bits, negative constant.
 define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -83,7 +83,7 @@ define void @f6(i8 *%ptr) {
 
 ; Sign extension to 32 bits, positive constant.
 define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
@@ -96,7 +96,7 @@ define void @f7(i8 *%ptr) {
 
 ; Sign extension to 64 bits, positive constant.
 define void @f8(i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: xi 0(%r2), 254
 ; CHECK: br %r14
   %val = load i8 *%ptr
diff --git a/test/CodeGen/SystemZ/xor-07.ll b/test/CodeGen/SystemZ/xor-07.ll
new file mode 100644
index 0000000..ec2a038
--- /dev/null
+++ b/test/CodeGen/SystemZ/xor-07.ll
@@ -0,0 +1,39 @@
+; Test the three-operand forms of XOR.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s
+
+; Check XRK.
+define i32 @f1(i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: f1:
+; CHECK: xrk %r2, %r3, %r4
+; CHECK: br %r14
+  %xor = xor i32 %b, %c
+  ret i32 %xor
+}
+
+; Check that we can still use XR in obvious cases.
+define i32 @f2(i32 %a, i32 %b) {
+; CHECK-LABEL: f2:
+; CHECK: xr %r2, %r3
+; CHECK: br %r14
+  %xor = xor i32 %a, %b
+  ret i32 %xor
+}
+
+; Check XGRK.
+define i64 @f3(i64 %a, i64 %b, i64 %c) {
+; CHECK-LABEL: f3:
+; CHECK: xgrk %r2, %r3, %r4
+; CHECK: br %r14
+  %xor = xor i64 %b, %c
+  ret i64 %xor
+}
+
+; Check that we can still use XGR in obvious cases.
+define i64 @f4(i64 %a, i64 %b) {
+; CHECK-LABEL: f4:
+; CHECK: xgr %r2, %r3
+; CHECK: br %r14
+  %xor = xor i64 %a, %b
+  ret i64 %xor
+}
diff --git a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
index 7876557..414b76d 100644
--- a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
+++ b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll
@@ -10,7 +10,7 @@
 @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (%struct.asl_file_t*, i64, i64*)* @t to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
 
 define i32 @t(%struct.asl_file_t* %s, i64 %off, i64* %out) nounwind optsize {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: adds {{r[0-7]}}, #8
 entry:
   %val = alloca i64, align 4                      ; <i64*> [#uses=3]
diff --git a/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll b/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll
index d6b6495..f5b3739 100644
--- a/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll
+++ b/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll
@@ -46,102 +46,108 @@ declare double @sqrt(double) nounwind readonly
 
 declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
+!llvm.dbg.cu = !{!5}
 !0 = metadata !{i32 46, i32 0, metadata !1, null}
-!1 = metadata !{i32 524299, metadata !4, metadata !2, i32 44, i32 0} ; [ DW_TAG_lexical_block ]
-!2 = metadata !{i32 524299, metadata !4, metadata !3, i32 44, i32 0} ; [ DW_TAG_lexical_block ]
-!3 = metadata !{i32 524334, i32 0, metadata !4, metadata !"getClosestDiagonal3", metadata !"getClosestDiagonal3", metadata !"_Z19getClosestDiagonal3ii", metadata !4, i32 44, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!4 = metadata !{i32 524329, metadata !"ggEdgeDiscrepancy.cc", metadata !"/Volumes/Home/grosbaj/sources/llvm-externals/speccpu2000/benchspec/CINT2000/252.eon/src", metadata !5} ; [ DW_TAG_file_type ]
-!5 = metadata !{i32 524305, i32 0, i32 4, metadata !"ggEdgeDiscrepancy.cc", metadata !"/Volumes/Home/grosbaj/sources/llvm-externals/speccpu2000/benchspec/CINT2000/252.eon/src", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!6 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!1 = metadata !{i32 524299, metadata !101, metadata !2, i32 44, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!2 = metadata !{i32 524299, metadata !101, metadata !3, i32 44, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!3 = metadata !{i32 524334, metadata !101, null, metadata !"getClosestDiagonal3", metadata !"getClosestDiagonal3", metadata !"_Z19getClosestDiagonal3ii", i32 44, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!4 = metadata !{i32 524329, metadata !101} ; [ DW_TAG_file_type ]
+!5 = metadata !{i32 524305, metadata !101, i32 4, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)", i1 true, metadata !"", i32 0, metadata !102, metadata !102, metadata !103, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!6 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !7 = metadata !{metadata !8, metadata !22, metadata !22}
-!8 = metadata !{i32 524307, metadata !4, metadata !"ggVector3", metadata !9, i32 66, i64 192, i64 32, i64 0, i32 0, null, metadata !10, i32 0, null} ; [ DW_TAG_structure_type ]
+!8 = metadata !{i32 524307, metadata !99, null, metadata !"ggVector3", i32 66, i64 192, i64 32, i64 0, i32 0, null, metadata !10, i32 0, null} ; [ DW_TAG_structure_type ]
 !9 = metadata !{i32 524329, metadata !"ggVector3.h", metadata !"/Volumes/Home/grosbaj/sources/llvm-externals/speccpu2000/benchspec/CINT2000/252.eon/src", metadata !5} ; [ DW_TAG_file_type ]
+!99 = metadata !{metadata !"ggVector3.h", metadata !"/Volumes/Home/grosbaj/sources/llvm-externals/speccpu2000/benchspec/CINT2000/252.eon/src"}
 !10 = metadata !{metadata !11, metadata !16, metadata !23, metadata !26, metadata !29, metadata !30, metadata !35, metadata !36, metadata !37, metadata !41, metadata !42, metadata !43, metadata !46, metadata !47, metadata !48, metadata !52, metadata !53, metadata !54, metadata !57, metadata !60, metadata !63, metadata !66, metadata !70, metadata !71, metadata !74, metadata !75, metadata !76, metadata !77, metadata !78, metadata !81, metadata !82, metadata !83, metadata !84, metadata !85, metadata !88, metadata !89, metadata !90}
-!11 = metadata !{i32 524301, metadata !8, metadata !"e", metadata !9, i32 160, i64 192, i64 32, i64 0, i32 0, metadata !12} ; [ DW_TAG_member ]
-!12 = metadata !{i32 524289, metadata !4, metadata !"", metadata !4, i32 0, i64 192, i64 32, i64 0, i32 0, metadata !13, metadata !14, i32 0, null} ; [ DW_TAG_array_type ]
-!13 = metadata !{i32 524324, metadata !4, metadata !"double", metadata !4, i32 0, i64 64, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
+!11 = metadata !{i32 524301, metadata !99, metadata !8, metadata !"e", i32 160, i64 192, i64 32, i64 0, i32 0, metadata !12} ; [ DW_TAG_member ]
+!12 = metadata !{i32 524289, metadata !101, metadata !4, metadata !"", i32 0, i64 192, i64 32, i64 0, i32 0, metadata !13, metadata !14, i32 0, null} ; [ DW_TAG_array_type ]
+!13 = metadata !{i32 524324, metadata !101, metadata !4, metadata !"double", i32 0, i64 64, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
 !14 = metadata !{metadata !15}
 !15 = metadata !{i32 524321, i64 0, i64 3}        ; [ DW_TAG_subrange_type ]
-!16 = metadata !{i32 524334, i32 0, metadata !8, metadata !"ggVector3", metadata !"ggVector3", metadata !"", metadata !9, i32 72, metadata !17, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!17 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !18, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!16 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"ggVector3", metadata !"ggVector3", metadata !"", i32 72, metadata !17, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!17 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !18, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !18 = metadata !{null, metadata !19, metadata !20}
-!19 = metadata !{i32 524303, metadata !4, metadata !"", metadata !4, i32 0, i64 32, i64 32, i64 0, i32 64, metadata !8} ; [ DW_TAG_pointer_type ]
-!20 = metadata !{i32 524310, metadata !21, metadata !"ggBoolean", metadata !21, i32 478, i64 0, i64 0, i64 0, i32 0, metadata !22} ; [ DW_TAG_typedef ]
+!19 = metadata !{i32 524303, metadata !101, metadata !4, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 64, metadata !8} ; [ DW_TAG_pointer_type ]
+!20 = metadata !{i32 524310, metadata !100, null, metadata !"ggBoolean", i32 478, i64 0, i64 0, i64 0, i32 0, metadata !22} ; [ DW_TAG_typedef ]
 !21 = metadata !{i32 524329, metadata !"math.h", metadata !"/Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS4.2.Internal.sdk/usr/include/architecture/arm", metadata !5} ; [ DW_TAG_file_type ]
-!22 = metadata !{i32 524324, metadata !4, metadata !"int", metadata !4, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!23 = metadata !{i32 524334, i32 0, metadata !8, metadata !"ggVector3", metadata !"ggVector3", metadata !"", metadata !9, i32 73, metadata !24, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!24 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !25, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!100 = metadata !{metadata !"math.h", metadata !"/Developer/Platforms/iPhoneOS.platform/Developer/SDKs/iPhoneOS4.2.Internal.sdk/usr/include/architecture/arm"}
+!22 = metadata !{i32 524324, metadata !101, metadata !4, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!23 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"ggVector3", metadata !"ggVector3", metadata !"", i32 73, metadata !24, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!24 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !25, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !25 = metadata !{null, metadata !19}
-!26 = metadata !{i32 524334, i32 0, metadata !8, metadata !"ggVector3", metadata !"ggVector3", metadata !"", metadata !9, i32 74, metadata !27, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!27 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !28, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!26 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"ggVector3", metadata !"ggVector3", metadata !"", i32 74, metadata !27, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!27 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !28, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !28 = metadata !{null, metadata !19, metadata !13, metadata !13, metadata !13}
-!29 = metadata !{i32 524334, i32 0, metadata !8, metadata !"Set", metadata !"Set", metadata !"_ZN9ggVector33SetEddd", metadata !9, i32 81, metadata !27, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!30 = metadata !{i32 524334, i32 0, metadata !8, metadata !"x", metadata !"x", metadata !"_ZNK9ggVector31xEv", metadata !9, i32 82, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!31 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !32, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!29 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"Set", metadata !"Set", metadata !"_ZN9ggVector33SetEddd", i32 81, metadata !27, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!30 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"x", metadata !"x", metadata !"_ZNK9ggVector31xEv", i32 82, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!31 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !32, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !32 = metadata !{metadata !13, metadata !33}
-!33 = metadata !{i32 524303, metadata !4, metadata !"", metadata !4, i32 0, i64 32, i64 32, i64 0, i32 64, metadata !34} ; [ DW_TAG_pointer_type ]
-!34 = metadata !{i32 524326, metadata !4, metadata !"", metadata !4, i32 0, i64 192, i64 32, i64 0, i32 0, metadata !8} ; [ DW_TAG_const_type ]
-!35 = metadata !{i32 524334, i32 0, metadata !8, metadata !"y", metadata !"y", metadata !"_ZNK9ggVector31yEv", metadata !9, i32 83, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!36 = metadata !{i32 524334, i32 0, metadata !8, metadata !"z", metadata !"z", metadata !"_ZNK9ggVector31zEv", metadata !9, i32 84, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!37 = metadata !{i32 524334, i32 0, metadata !8, metadata !"x", metadata !"x", metadata !"_ZN9ggVector31xEv", metadata !9, i32 85, metadata !38, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!38 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !39, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!33 = metadata !{i32 524303, metadata !101, metadata !4, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 64, metadata !34} ; [ DW_TAG_pointer_type ]
+!34 = metadata !{i32 524326, metadata !101, metadata !4, metadata !"", i32 0, i64 192, i64 32, i64 0, i32 0, metadata !8} ; [ DW_TAG_const_type ]
+!35 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"y", metadata !"y", metadata !"_ZNK9ggVector31yEv", i32 83, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!36 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"z", metadata !"z", metadata !"_ZNK9ggVector31zEv", i32 84, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!37 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"x", metadata !"x", metadata !"_ZN9ggVector31xEv", i32 85, metadata !38, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!38 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !39, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !39 = metadata !{metadata !40, metadata !19}
-!40 = metadata !{i32 524304, metadata !4, metadata !"double", metadata !4, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !13} ; [ DW_TAG_reference_type ]
-!41 = metadata !{i32 524334, i32 0, metadata !8, metadata !"y", metadata !"y", metadata !"_ZN9ggVector31yEv", metadata !9, i32 86, metadata !38, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!42 = metadata !{i32 524334, i32 0, metadata !8, metadata !"z", metadata !"z", metadata !"_ZN9ggVector31zEv", metadata !9, i32 87, metadata !38, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!43 = metadata !{i32 524334, i32 0, metadata !8, metadata !"SetX", metadata !"SetX", metadata !"_ZN9ggVector34SetXEd", metadata !9, i32 88, metadata !44, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!44 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !45, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!40 = metadata !{i32 524304, metadata !101, metadata !4, metadata !"double", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !13} ; [ DW_TAG_reference_type ]
+!41 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"y", metadata !"y", metadata !"_ZN9ggVector31yEv", i32 86, metadata !38, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!42 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"z", metadata !"z", metadata !"_ZN9ggVector31zEv", i32 87, metadata !38, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!43 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"SetX", metadata !"SetX", metadata !"_ZN9ggVector34SetXEd", i32 88, metadata !44, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!44 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !45, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !45 = metadata !{null, metadata !19, metadata !13}
-!46 = metadata !{i32 524334, i32 0, metadata !8, metadata !"SetY", metadata !"SetY", metadata !"_ZN9ggVector34SetYEd", metadata !9, i32 89, metadata !44, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!47 = metadata !{i32 524334, i32 0, metadata !8, metadata !"SetZ", metadata !"SetZ", metadata !"_ZN9ggVector34SetZEd", metadata !9, i32 90, metadata !44, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!48 = metadata !{i32 524334, i32 0, metadata !8, metadata !"ggVector3", metadata !"ggVector3", metadata !"", metadata !9, i32 92, metadata !49, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!49 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !50, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!46 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"SetY", metadata !"SetY", metadata !"_ZN9ggVector34SetYEd", i32 89, metadata !44, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!47 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"SetZ", metadata !"SetZ", metadata !"_ZN9ggVector34SetZEd", i32 90, metadata !44, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!48 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"ggVector3", metadata !"ggVector3", metadata !"", i32 92, metadata !49, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!49 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !50, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !50 = metadata !{null, metadata !19, metadata !51}
-!51 = metadata !{i32 524304, metadata !4, metadata !"", metadata !4, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !34} ; [ DW_TAG_reference_type ]
-!52 = metadata !{i32 524334, i32 0, metadata !8, metadata !"tolerance", metadata !"tolerance", metadata !"_ZNK9ggVector39toleranceEv", metadata !9, i32 100, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!53 = metadata !{i32 524334, i32 0, metadata !8, metadata !"tolerance", metadata !"tolerance", metadata !"_ZN9ggVector39toleranceEv", metadata !9, i32 101, metadata !38, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!54 = metadata !{i32 524334, i32 0, metadata !8, metadata !"operator+", metadata !"operator+", metadata !"_ZNK9ggVector3psEv", metadata !9, i32 107, metadata !55, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!55 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !56, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!51 = metadata !{i32 524304, metadata !101, metadata !4, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !34} ; [ DW_TAG_reference_type ]
+!52 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"tolerance", metadata !"tolerance", metadata !"_ZNK9ggVector39toleranceEv", i32 100, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!53 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"tolerance", metadata !"tolerance", metadata !"_ZN9ggVector39toleranceEv", i32 101, metadata !38, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!54 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"operator+", metadata !"operator+", metadata !"_ZNK9ggVector3psEv", i32 107, metadata !55, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!55 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !56, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !56 = metadata !{metadata !51, metadata !33}
-!57 = metadata !{i32 524334, i32 0, metadata !8, metadata !"operator-", metadata !"operator-", metadata !"_ZNK9ggVector3ngEv", metadata !9, i32 108, metadata !58, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!58 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !59, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!57 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"operator-", metadata !"operator-", metadata !"_ZNK9ggVector3ngEv", i32 108, metadata !58, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!58 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !59, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !59 = metadata !{metadata !8, metadata !33}
-!60 = metadata !{i32 524334, i32 0, metadata !8, metadata !"operator[]", metadata !"operator[]", metadata !"_ZNK9ggVector3ixEi", metadata !9, i32 290, metadata !61, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!61 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !62, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!60 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"operator[]", metadata !"operator[]", metadata !"_ZNK9ggVector3ixEi", i32 290, metadata !61, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!61 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !62, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !62 = metadata !{metadata !13, metadata !33, metadata !22}
-!63 = metadata !{i32 524334, i32 0, metadata !8, metadata !"operator[]", metadata !"operator[]", metadata !"_ZN9ggVector3ixEi", metadata !9, i32 278, metadata !64, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!64 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !65, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!63 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"operator[]", metadata !"operator[]", metadata !"_ZN9ggVector3ixEi", i32 278, metadata !64, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!64 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !65, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !65 = metadata !{metadata !40, metadata !19, metadata !22}
-!66 = metadata !{i32 524334, i32 0, metadata !8, metadata !"operator+=", metadata !"operator+=", metadata !"_ZN9ggVector3pLERKS_", metadata !9, i32 303, metadata !67, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!67 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !68, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!66 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"operator+=", metadata !"operator+=", metadata !"_ZN9ggVector3pLERKS_", i32 303, metadata !67, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!67 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !68, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !68 = metadata !{metadata !69, metadata !19, metadata !51}
-!69 = metadata !{i32 524304, metadata !4, metadata !"ggVector3", metadata !4, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !8} ; [ DW_TAG_reference_type ]
-!70 = metadata !{i32 524334, i32 0, metadata !8, metadata !"operator-=", metadata !"operator-=", metadata !"_ZN9ggVector3mIERKS_", metadata !9, i32 310, metadata !67, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!71 = metadata !{i32 524334, i32 0, metadata !8, metadata !"operator*=", metadata !"operator*=", metadata !"_ZN9ggVector3mLEd", metadata !9, i32 317, metadata !72, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!72 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !73, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!69 = metadata !{i32 524304, metadata !101, metadata !4, metadata !"ggVector3", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !8} ; [ DW_TAG_reference_type ]
+!70 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"operator-=", metadata !"operator-=", metadata !"_ZN9ggVector3mIERKS_", i32 310, metadata !67, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!71 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"operator*=", metadata !"operator*=", metadata !"_ZN9ggVector3mLEd", i32 317, metadata !72, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!72 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !73, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !73 = metadata !{metadata !69, metadata !19, metadata !13}
-!74 = metadata !{i32 524334, i32 0, metadata !8, metadata !"operator/=", metadata !"operator/=", metadata !"_ZN9ggVector3dVEd", metadata !9, i32 324, metadata !72, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!75 = metadata !{i32 524334, i32 0, metadata !8, metadata !"length", metadata !"length", metadata !"_ZNK9ggVector36lengthEv", metadata !9, i32 121, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!76 = metadata !{i32 524334, i32 0, metadata !8, metadata !"squaredLength", metadata !"squaredLength", metadata !"_ZNK9ggVector313squaredLengthEv", metadata !9, i32 122, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!77 = metadata !{i32 524334, i32 0, metadata !8, metadata !"MakeUnitVector", metadata !"MakeUnitVector", metadata !"_ZN9ggVector314MakeUnitVectorEv", metadata !9, i32 217, metadata !24, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!78 = metadata !{i32 524334, i32 0, metadata !8, metadata !"Perturb", metadata !"Perturb", metadata !"_ZNK9ggVector37PerturbEdd", metadata !9, i32 126, metadata !79, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!79 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !80, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!74 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"operator/=", metadata !"operator/=", metadata !"_ZN9ggVector3dVEd", i32 324, metadata !72, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!75 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"length", metadata !"length", metadata !"_ZNK9ggVector36lengthEv", i32 121, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!76 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"squaredLength", metadata !"squaredLength", metadata !"_ZNK9ggVector313squaredLengthEv", i32 122, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!77 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"MakeUnitVector", metadata !"MakeUnitVector", metadata !"_ZN9ggVector314MakeUnitVectorEv", i32 217, metadata !24, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!78 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"Perturb", metadata !"Perturb", metadata !"_ZNK9ggVector37PerturbEdd", i32 126, metadata !79, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!79 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !80, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !80 = metadata !{metadata !8, metadata !33, metadata !13, metadata !13}
-!81 = metadata !{i32 524334, i32 0, metadata !8, metadata !"maxComponent", metadata !"maxComponent", metadata !"_ZNK9ggVector312maxComponentEv", metadata !9, i32 128, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!82 = metadata !{i32 524334, i32 0, metadata !8, metadata !"minComponent", metadata !"minComponent", metadata !"_ZNK9ggVector312minComponentEv", metadata !9, i32 129, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!83 = metadata !{i32 524334, i32 0, metadata !8, metadata !"maxAbsComponent", metadata !"maxAbsComponent", metadata !"_ZNK9ggVector315maxAbsComponentEv", metadata !9, i32 131, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!84 = metadata !{i32 524334, i32 0, metadata !8, metadata !"minAbsComponent", metadata !"minAbsComponent", metadata !"_ZNK9ggVector315minAbsComponentEv", metadata !9, i32 132, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!85 = metadata !{i32 524334, i32 0, metadata !8, metadata !"indexOfMinComponent", metadata !"indexOfMinComponent", metadata !"_ZNK9ggVector319indexOfMinComponentEv", metadata !9, i32 133, metadata !86, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!86 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !87, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!81 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"maxComponent", metadata !"maxComponent", metadata !"_ZNK9ggVector312maxComponentEv", i32 128, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!82 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"minComponent", metadata !"minComponent", metadata !"_ZNK9ggVector312minComponentEv", i32 129, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!83 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"maxAbsComponent", metadata !"maxAbsComponent", metadata !"_ZNK9ggVector315maxAbsComponentEv", i32 131, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!84 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"minAbsComponent", metadata !"minAbsComponent", metadata !"_ZNK9ggVector315minAbsComponentEv", i32 132, metadata !31, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!85 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"indexOfMinComponent", metadata !"indexOfMinComponent", metadata !"_ZNK9ggVector319indexOfMinComponentEv", i32 133, metadata !86, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!86 = metadata !{i32 524309, metadata !101, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !87, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !87 = metadata !{metadata !22, metadata !33}
-!88 = metadata !{i32 524334, i32 0, metadata !8, metadata !"indexOfMinAbsComponent", metadata !"indexOfMinAbsComponent", metadata !"_ZNK9ggVector322indexOfMinAbsComponentEv", metadata !9, i32 137, metadata !86, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!89 = metadata !{i32 524334, i32 0, metadata !8, metadata !"indexOfMaxComponent", metadata !"indexOfMaxComponent", metadata !"_ZNK9ggVector319indexOfMaxComponentEv", metadata !9, i32 146, metadata !86, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!90 = metadata !{i32 524334, i32 0, metadata !8, metadata !"indexOfMaxAbsComponent", metadata !"indexOfMaxAbsComponent", metadata !"_ZNK9ggVector322indexOfMaxAbsComponentEv", metadata !9, i32 150, metadata !86, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
+!88 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"indexOfMinAbsComponent", metadata !"indexOfMinAbsComponent", metadata !"_ZNK9ggVector322indexOfMinAbsComponentEv", i32 137, metadata !86, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!89 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"indexOfMaxComponent", metadata !"indexOfMaxComponent", metadata !"_ZNK9ggVector319indexOfMaxComponentEv", i32 146, metadata !86, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!90 = metadata !{i32 524334, metadata !9, metadata !8, metadata !"indexOfMaxAbsComponent", metadata !"indexOfMaxAbsComponent", metadata !"_ZNK9ggVector322indexOfMaxAbsComponentEv", i32 150, metadata !86, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !91 = metadata !{i32 524544, metadata !1, metadata !"vx", metadata !4, i32 46, metadata !13} ; [ DW_TAG_auto_variable ]
 !92 = metadata !{i32 48, i32 0, metadata !1, null}
 !93 = metadata !{i32 218, i32 0, metadata !94, metadata !96}
-!94 = metadata !{i32 524299, metadata !4, metadata !95, i32 217, i32 0} ; [ DW_TAG_lexical_block ]
-!95 = metadata !{i32 524299, metadata !4, metadata !77, i32 217, i32 0} ; [ DW_TAG_lexical_block ]
+!94 = metadata !{i32 524299, metadata !101, metadata !95, i32 217, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!95 = metadata !{i32 524299, metadata !101, metadata !77, i32 217, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !96 = metadata !{i32 51, i32 0, metadata !1, null}
 !97 = metadata !{i32 227, i32 0, metadata !94, metadata !96}
 !98 = metadata !{i32 52, i32 0, metadata !1, null}
+!101 = metadata !{metadata !"ggEdgeDiscrepancy.cc", metadata !"/Volumes/Home/grosbaj/sources/llvm-externals/speccpu2000/benchspec/CINT2000/252.eon/src"}
+!102 = metadata !{i32 0}
+!103 = metadata !{metadata !3}
diff --git a/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll b/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll
index a4c05d2..b39978b 100644
--- a/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll
+++ b/test/CodeGen/Thumb/2012-04-26-M0ISelBug.ll
@@ -3,7 +3,7 @@
 ; rdar://11331541
 
 define i32 @t(i32 %a) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: asrs [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], #31
 ; CHECK: eors [[REG1]], [[REG2]]
   %tmp0 = ashr i32 %a, 31
diff --git a/test/CodeGen/Thumb/barrier.ll b/test/CodeGen/Thumb/barrier.ll
index 50d138f..8fca273 100644
--- a/test/CodeGen/Thumb/barrier.ll
+++ b/test/CodeGen/Thumb/barrier.ll
@@ -3,10 +3,10 @@
 ; RUN: llc < %s -march=thumb -mcpu=cortex-m0   | FileCheck %s -check-prefix=V6M
 
 define void @t1() {
-; V6: t1:
+; V6-LABEL: t1:
 ; V6: blx {{_*}}sync_synchronize
 
-; V6M: t1:
+; V6M-LABEL: t1:
 ; V6M: dmb ish
   fence seq_cst
   ret void
diff --git a/test/CodeGen/Thumb/dyn-stackalloc.ll b/test/CodeGen/Thumb/dyn-stackalloc.ll
index f3f0834..6c6de55 100644
--- a/test/CodeGen/Thumb/dyn-stackalloc.ll
+++ b/test/CodeGen/Thumb/dyn-stackalloc.ll
@@ -5,7 +5,7 @@
 	%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
 
 define void @t1(%struct.state* %v) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: push
 ; CHECK: add r7, sp, #12
 ; CHECK: lsls r[[R0:[0-9]+]]
@@ -39,7 +39,7 @@ declare fastcc void @f2(float*, float*, float*, i32)
 @str215 = external global [2 x i8]
 
 define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: push
 ; CHECK: add r7, sp, #12
 ; CHECK: sub sp, #
diff --git a/test/CodeGen/Thumb/ispositive.ll b/test/CodeGen/Thumb/ispositive.ll
index eac3ef2..7b28227 100644
--- a/test/CodeGen/Thumb/ispositive.ll
+++ b/test/CodeGen/Thumb/ispositive.ll
@@ -2,7 +2,7 @@
 
 define i32 @test1(i32 %X) {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: lsrs r0, r0, #31
         icmp slt i32 %X, 0              ; <i1>:0 [#uses=1]
         zext i1 %0 to i32               ; <i32>:1 [#uses=1]
diff --git a/test/CodeGen/Thumb/large-stack.ll b/test/CodeGen/Thumb/large-stack.ll
index 680976e..fb6daa4 100644
--- a/test/CodeGen/Thumb/large-stack.ll
+++ b/test/CodeGen/Thumb/large-stack.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=thumb-apple-ios | FileCheck %s
 
 define void @test1() {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: sub sp, #256
 ; CHECK: add sp, #256
     %tmp = alloca [ 64 x i32 ] , align 4
@@ -9,8 +9,8 @@ define void @test1() {
 }
 
 define void @test2() {
-; CHECK: test2:
-; CHECK: ldr.n r0, LCPI
+; CHECK-LABEL: test2:
+; CHECK: ldr r0, LCPI
 ; CHECK: add sp, r0
 ; CHECK: subs r4, r7, #4
 ; CHECK: mov sp, r4
@@ -19,10 +19,10 @@ define void @test2() {
 }
 
 define i32 @test3() {
-; CHECK: test3:
-; CHECK: ldr.n r1, LCPI
+; CHECK-LABEL: test3:
+; CHECK: ldr r1, LCPI
 ; CHECK: add sp, r1
-; CHECK: ldr.n r1, LCPI
+; CHECK: ldr r1, LCPI
 ; CHECK: add r1, sp
 ; CHECK: subs r4, r7, #4
 ; CHECK: mov sp, r4
diff --git a/test/CodeGen/Thumb/ldr_frame.ll b/test/CodeGen/Thumb/ldr_frame.ll
index 81782cd..6c58638 100644
--- a/test/CodeGen/Thumb/ldr_frame.ll
+++ b/test/CodeGen/Thumb/ldr_frame.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb | FileCheck %s
 
 define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldr r0
 	%buf = alloca [32 x i32], align 4
 	%tmp = getelementptr [32 x i32]* %buf, i32 0, i32 0
@@ -10,7 +10,7 @@ define i32 @f1() {
 }
 
 define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mov r0
 ; CHECK: ldrb
 	%buf = alloca [32 x i8], align 4
@@ -21,7 +21,7 @@ define i32 @f2() {
 }
 
 define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ldr r0
 	%buf = alloca [32 x i32], align 4
 	%tmp = getelementptr [32 x i32]* %buf, i32 0, i32 32
@@ -30,7 +30,7 @@ define i32 @f3() {
 }
 
 define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mov r0
 ; CHECK: ldrb
 	%buf = alloca [32 x i8], align 4
diff --git a/test/CodeGen/Thumb/pop.ll b/test/CodeGen/Thumb/pop.ll
index 63f2feb..1e45c7f 100644
--- a/test/CodeGen/Thumb/pop.ll
+++ b/test/CodeGen/Thumb/pop.ll
@@ -2,7 +2,7 @@
 ; rdar://7268481
 
 define void @t(i8* %a, ...) nounwind {
-; CHECK:      t:
+; CHECK-LABEL:      t:
 ; CHECK:      pop {r3}
 ; CHECK-NEXT: add sp, #12
 ; CHECK-NEXT: bx r3
diff --git a/test/CodeGen/Thumb/push.ll b/test/CodeGen/Thumb/push.ll
index 94ef8e9..62229c6 100644
--- a/test/CodeGen/Thumb/push.ll
+++ b/test/CodeGen/Thumb/push.ll
@@ -2,7 +2,7 @@
 ; rdar://7268481
 
 define void @t() nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: push {r7}
 entry:
   call void asm sideeffect alignstack ".long 0xe7ffdefe", ""() nounwind
diff --git a/test/CodeGen/Thumb/rev.ll b/test/CodeGen/Thumb/rev.ll
index 5e163f8..dcba00e 100644
--- a/test/CodeGen/Thumb/rev.ll
+++ b/test/CodeGen/Thumb/rev.ll
@@ -32,7 +32,7 @@ define i32 @test2(i32 %X) nounwind {
 ; rdar://9147637
 define i32 @test3(i16 zeroext %a) nounwind {
 entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: revsh r0, r0
   %0 = tail call i16 @llvm.bswap.i16(i16 %a)
   %1 = sext i16 %0 to i32
@@ -43,7 +43,7 @@ declare i16 @llvm.bswap.i16(i16) nounwind readnone
 
 define i32 @test4(i16 zeroext %a) nounwind {
 entry:
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: revsh r0, r0
   %conv = zext i16 %a to i32
   %shr9 = lshr i16 %a, 8
diff --git a/test/CodeGen/Thumb/select.ll b/test/CodeGen/Thumb/select.ll
index 3f10b05..fe69a39 100644
--- a/test/CodeGen/Thumb/select.ll
+++ b/test/CodeGen/Thumb/select.ll
@@ -7,9 +7,9 @@ entry:
     %tmp1.s = select i1 %tmp, i32 2, i32 3
     ret i32 %tmp1.s
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: beq
-; CHECK-EABI: f1:
+; CHECK-EABI-LABEL: f1:
 ; CHECK-EABI: beq
 
 define i32 @f2(i32 %a.s) {
@@ -18,9 +18,9 @@ entry:
     %tmp1.s = select i1 %tmp, i32 2, i32 3
     ret i32 %tmp1.s
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: bgt
-; CHECK-EABI: f2:
+; CHECK-EABI-LABEL: f2:
 ; CHECK-EABI: bgt
 
 define i32 @f3(i32 %a.s, i32 %b.s) {
@@ -29,9 +29,9 @@ entry:
     %tmp1.s = select i1 %tmp, i32 2, i32 3
     ret i32 %tmp1.s
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: blt
-; CHECK-EABI: f3:
+; CHECK-EABI-LABEL: f3:
 ; CHECK-EABI: blt
 
 define i32 @f4(i32 %a.s, i32 %b.s) {
@@ -40,9 +40,9 @@ entry:
     %tmp1.s = select i1 %tmp, i32 2, i32 3
     ret i32 %tmp1.s
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ble
-; CHECK-EABI: f4:
+; CHECK-EABI-LABEL: f4:
 ; CHECK-EABI: ble
 
 define i32 @f5(i32 %a.u, i32 %b.u) {
@@ -51,9 +51,9 @@ entry:
     %tmp1.s = select i1 %tmp, i32 2, i32 3
     ret i32 %tmp1.s
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: bls
-; CHECK-EABI: f5:
+; CHECK-EABI-LABEL: f5:
 ; CHECK-EABI: bls
 
 define i32 @f6(i32 %a.u, i32 %b.u) {
@@ -62,9 +62,9 @@ entry:
     %tmp1.s = select i1 %tmp, i32 2, i32 3
     ret i32 %tmp1.s
 }
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: bhi
-; CHECK-EABI: f6:
+; CHECK-EABI-LABEL: f6:
 ; CHECK-EABI: bhi
 
 define double @f7(double %a, double %b) {
@@ -72,11 +72,11 @@ define double @f7(double %a, double %b) {
     %tmp1 = select i1 %tmp, double -1.000e+00, double %b
     ret double %tmp1
 }
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: blt
 ; CHECK: blt
 ; CHECK: __ltdf2
-; CHECK-EABI: f7:
+; CHECK-EABI-LABEL: f7:
 ; CHECK-EABI: __aeabi_dcmplt
 ; CHECK-EABI: bne
 ; CHECK-EABI: bne
diff --git a/test/CodeGen/Thumb/trap.ll b/test/CodeGen/Thumb/trap.ll
index 04cd3ee..e04059c 100644
--- a/test/CodeGen/Thumb/trap.ll
+++ b/test/CodeGen/Thumb/trap.ll
@@ -3,7 +3,7 @@
 
 define void @t() nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: trap
   call void @llvm.trap()
   unreachable
diff --git a/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll b/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
index 4616dcf..4abeca9 100644
--- a/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
+++ b/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll
@@ -5,7 +5,7 @@
 
 define i32 @t(i32, ...) nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: add r7, sp, #12
 	%1 = load i8** undef, align 4		; <i8*> [#uses=3]
 	%2 = getelementptr i8* %1, i32 4		; <i8*> [#uses=1]
diff --git a/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll b/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
index 095aecc..e014453 100644
--- a/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
+++ b/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
@@ -7,7 +7,7 @@
 @sep = external global [20 x i32]		; <[20 x i32]*> [#uses=1]
 
 define void @main(i32 %argc, i8** %argv) noreturn nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK: ldrb
 entry:
 	%nb.i.i.i = alloca [25 x i8], align 1		; <[25 x i8]*> [#uses=0]
diff --git a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
index ff68e66..940cfd1 100644
--- a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
+++ b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
@@ -4,7 +4,7 @@
 
 define hidden i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind {
 entry:
-; CHECK: __gcov_execlp:
+; CHECK-LABEL: __gcov_execlp:
 ; CHECK: sub sp, #8
 ; CHECK: push
 ; CHECK: add r7, sp, #4
diff --git a/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll b/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
index ac3e80a..52066d3 100644
--- a/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
+++ b/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
@@ -5,7 +5,7 @@
 @getNeighbour = external global void (i32, i32, i32, i32, %struct.pix_pos*)*, align 4 ; <void (i32, i32, i32, i32, %struct.pix_pos*)**> [#uses=2]
 
 define void @t() nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK:      it eq
 ; CHECK-NEXT: cmpeq
 entry:
diff --git a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
index 18c2e0b..04d46e6 100644
--- a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
+++ b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
@@ -10,7 +10,7 @@
 
 
 define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) {
-; CHECK: _ZNKSs7compareERKSs:
+; CHECK-LABEL: _ZNKSs7compareERKSs:
 ; CHECK:      it  eq
 ; CHECK-NEXT: subeq{{(.w)?}} r0, r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK-NEXT: pop.w
diff --git a/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll b/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll
index c153092..c662620 100644
--- a/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll
+++ b/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll
@@ -2,7 +2,7 @@
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
 
 define i32 @test(i32 %n) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: mov
 ; CHECK: return
 entry:
@@ -30,7 +30,7 @@ return:                                           ; preds = %bb, %entry
 }
 
 define i32 @test_dead_cycle(i32 %n) nounwind {
-; CHECK: test_dead_cycle:
+; CHECK-LABEL: test_dead_cycle:
 ; CHECK: blx
 ; CHECK-NOT: mov
 ; CHECK: blx
diff --git a/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll b/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll
index 2246de3..486c064 100644
--- a/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll
+++ b/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll
@@ -6,7 +6,7 @@
 
 define void @t() nounwind ssp {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
   %size = mul i32 8, 2
 ; CHECK:  subs  r0, #16
 ; CHECK:  mov sp, r0
diff --git a/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll b/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll
index 47d7a9c..547950f 100644
--- a/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll
+++ b/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll
@@ -4,7 +4,7 @@
 
 define internal fastcc i32 @Callee(i32 %i) nounwind {
 entry:
-; CHECK: Callee:
+; CHECK-LABEL: Callee:
 ; CHECK: push
 ; CHECK: mov r4, sp
 ; CHECK: sub.w [[R12:r[0-9]+]], r4, #1000
@@ -33,7 +33,7 @@ bb2:                                              ; preds = %entry
 declare i32 @__sprintf_chk(i8*, i32, i32, i8*, ...) nounwind
 
 define i32 @main() nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
 bb.nph:
   br label %bb
 
diff --git a/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll b/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
index 5cb266b..75f5439 100644
--- a/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
+++ b/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
@@ -6,7 +6,7 @@
 declare void @bar() nounwind optsize
 
 define void @foo() nounwind optsize {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: push
 ; CHECK: mov r7, sp
 ; CHECK: sub sp, #4
diff --git a/test/CodeGen/Thumb2/2011-04-21-FILoweringBug.ll b/test/CodeGen/Thumb2/2011-04-21-FILoweringBug.ll
index 604a352..9878ae8 100644
--- a/test/CodeGen/Thumb2/2011-04-21-FILoweringBug.ll
+++ b/test/CodeGen/Thumb2/2011-04-21-FILoweringBug.ll
@@ -7,7 +7,7 @@
 
 define i32 @t() nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: sub sp, #12
 ; CHECK-NOT: sub
 ; CHECK: add r0, sp, #4
diff --git a/test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll b/test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll
index 4acdd9e..5008715 100644
--- a/test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll
+++ b/test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll
@@ -12,7 +12,7 @@
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
 
 define hidden fastcc void @rdictionary_lookup(%struct.Dict_node_struct* %dn, i8* nocapture %s) nounwind ssp {
-; CHECK: rdictionary_lookup:
+; CHECK-LABEL: rdictionary_lookup:
 entry:
   br label %tailrecurse
 
diff --git a/test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll b/test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll
index 203815f..974fade 100644
--- a/test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll
+++ b/test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll
@@ -3,7 +3,7 @@
 ; Testing that these don't crash/assert. The loop vectorizer can end up
 ; with odd constructs like this. The code actually generated is incidental.
 define <1 x i64> @test_zext(i32 %a) nounwind {
-; CHECK: test_zext:
+; CHECK-LABEL: test_zext:
   %Cmp = icmp uge i32 %a, 42
   %vec = insertelement <1 x i1> zeroinitializer, i1 %Cmp, i32 0
   %Se = zext <1 x i1> %vec to <1 x i64>
@@ -11,7 +11,7 @@ define <1 x i64> @test_zext(i32 %a) nounwind {
 }
 
 define <1 x i64> @test_sext(i32 %a) nounwind {
-; CHECK: test_sext:
+; CHECK-LABEL: test_sext:
   %Cmp = icmp uge i32 %a, 42
   %vec = insertelement <1 x i1> zeroinitializer, i1 %Cmp, i32 0
   %Se = sext <1 x i1> %vec to <1 x i64>
diff --git a/test/CodeGen/Thumb2/buildvector-crash.ll b/test/CodeGen/Thumb2/buildvector-crash.ll
index ce42f4b..8a3c895 100644
--- a/test/CodeGen/Thumb2/buildvector-crash.ll
+++ b/test/CodeGen/Thumb2/buildvector-crash.ll
@@ -12,6 +12,6 @@ bb8:                                              ; preds = %bb8, %bb.nph372
   %3 = fadd <4 x float> undef, %2
   store <4 x float> %3, <4 x float>* undef, align 4
   br label %bb8
-; CHECK: RotateStarsFP_Vec:
+; CHECK-LABEL: RotateStarsFP_Vec:
 ; CHECK: vld1.64
 }
diff --git a/test/CodeGen/Thumb2/carry.ll b/test/CodeGen/Thumb2/carry.ll
index 85b4370..da1902b 100644
--- a/test/CodeGen/Thumb2/carry.ll
+++ b/test/CodeGen/Thumb2/carry.ll
@@ -2,7 +2,7 @@
 
 define i64 @f1(i64 %a, i64 %b) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: subs r0, r0, r2
 ; CHECK: sbcs r1, r3
 	%tmp = sub i64 %a, %b
@@ -11,7 +11,7 @@ entry:
 
 define i64 @f2(i64 %a, i64 %b) {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: adds r0, r0, r0
 ; CHECK: adcs r1, r1
 ; CHECK: subs r0, r0, r2
@@ -24,7 +24,7 @@ entry:
 ; rdar://12559385
 define i64 @f3(i32 %vi) {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: movw [[REG:r[0-9]+]], #36102
 ; CHECK: sbcs r{{[0-9]+}}, [[REG]]
     %v0 = zext i32 %vi to i64
diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
index edbf834..a9f948c 100644
--- a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
+++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | FileCheck %s
 
 define void @fht(float* nocapture %fz, i16 signext %n) nounwind {
-; CHECK: fht:
+; CHECK-LABEL: fht:
 entry:
   br label %bb5
 
diff --git a/test/CodeGen/Thumb2/large-stack.ll b/test/CodeGen/Thumb2/large-stack.ll
index 68b5d1c..36f3ce2 100644
--- a/test/CodeGen/Thumb2/large-stack.ll
+++ b/test/CodeGen/Thumb2/large-stack.ll
@@ -2,19 +2,19 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=LINUX
 
 define void @test1() {
-; DARWIN: test1:
+; DARWIN-LABEL: test1:
 ; DARWIN: sub sp, #256
-; LINUX: test1:
+; LINUX-LABEL: test1:
 ; LINUX: sub sp, #256
     %tmp = alloca [ 64 x i32 ] , align 4
     ret void
 }
 
 define void @test2() {
-; DARWIN: test2:
+; DARWIN-LABEL: test2:
 ; DARWIN: sub.w sp, sp, #4160
 ; DARWIN: sub sp, #8
-; LINUX: test2:
+; LINUX-LABEL: test2:
 ; LINUX: sub.w sp, sp, #4160
 ; LINUX: sub sp, #8
     %tmp = alloca [ 4168 x i8 ] , align 4
@@ -22,11 +22,11 @@ define void @test2() {
 }
 
 define i32 @test3() {
-; DARWIN: test3:
+; DARWIN-LABEL: test3:
 ; DARWIN: push    {r4, r7, lr}
 ; DARWIN: sub.w sp, sp, #805306368
 ; DARWIN: sub sp, #20
-; LINUX: test3:
+; LINUX-LABEL: test3:
 ; LINUX: push.w {r4, r7, r11, lr}
 ; LINUX: sub.w sp, sp, #805306368
 ; LINUX: sub sp, #16
diff --git a/test/CodeGen/Thumb2/longMACt.ll b/test/CodeGen/Thumb2/longMACt.ll
index beefd60..a457333 100644
--- a/test/CodeGen/Thumb2/longMACt.ll
+++ b/test/CodeGen/Thumb2/longMACt.ll
@@ -2,7 +2,7 @@
 ; Check generated signed and unsigned multiply accumulate long.
 
 define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
-;CHECK: MACLongTest1:
+;CHECK-LABEL: MACLongTest1:
 ;CHECK: umlal
   %conv = zext i32 %a to i64
   %conv1 = zext i32 %b to i64
@@ -12,7 +12,7 @@ define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
 }
 
 define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c)  {
-;CHECK: MACLongTest2:
+;CHECK-LABEL: MACLongTest2:
 ;CHECK: smlal
   %conv = sext i32 %a to i64
   %conv1 = sext i32 %b to i64
@@ -22,7 +22,7 @@ define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c)  {
 }
 
 define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {
-;CHECK: MACLongTest3:
+;CHECK-LABEL: MACLongTest3:
 ;CHECK: umlal
   %conv = zext i32 %b to i64
   %conv1 = zext i32 %a to i64
@@ -33,7 +33,7 @@ define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {
 }
 
 define i64 @MACLongTest4(i32 %a, i32 %b, i32 %c) {
-;CHECK: MACLongTest4:
+;CHECK-LABEL: MACLongTest4:
 ;CHECK: smlal
   %conv = sext i32 %b to i64
   %conv1 = sext i32 %a to i64
diff --git a/test/CodeGen/Thumb2/lsr-deficiency.ll b/test/CodeGen/Thumb2/lsr-deficiency.ll
index 9aaa821..7ce6768 100644
--- a/test/CodeGen/Thumb2/lsr-deficiency.ll
+++ b/test/CodeGen/Thumb2/lsr-deficiency.ll
@@ -7,7 +7,7 @@
 @array = external global i32*                     ; <i32**> [#uses=1]
 
 define void @t() nounwind optsize {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: mov{{.*}}, #1000
 entry:
   %.pre = load i32* @G, align 4                   ; <i32> [#uses=1]
diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll
index 01df373..d9da846 100644
--- a/test/CodeGen/Thumb2/machine-licm.ll
+++ b/test/CodeGen/Thumb2/machine-licm.ll
@@ -7,7 +7,7 @@
 
 define void @t1(i32* nocapture %vals, i32 %c) nounwind {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: bxeq lr
 
   %0 = icmp eq i32 %c, 0                          ; <i1> [#uses=1]
@@ -50,7 +50,7 @@ return:                                           ; preds = %bb, %entry
 ; rdar://8001136
 define void @t2(i8* %ptr1, i8* %ptr2) nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: vmov.f32 q{{.*}}, #1.000000e+00
   br i1 undef, label %bb1, label %bb2
 
@@ -82,7 +82,7 @@ declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwin
 ; rdar://8241368
 ; isel should not fold immediate into eor's which would have prevented LICM.
 define zeroext i16 @t3(i8 zeroext %data, i16 zeroext %crc) nounwind readnone {
-; CHECK: t3:
+; CHECK-LABEL: t3:
 bb.nph:
 ; CHECK: bb.nph
 ; CHECK: movw {{(r[0-9])|(lr)}}, #32768
diff --git a/test/CodeGen/Thumb2/mul_const.ll b/test/CodeGen/Thumb2/mul_const.ll
index 9a2ec93..488f4d1 100644
--- a/test/CodeGen/Thumb2/mul_const.ll
+++ b/test/CodeGen/Thumb2/mul_const.ll
@@ -3,7 +3,7 @@
 
 define i32 @t1(i32 %v) nounwind readnone {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: add.w r0, r0, r0, lsl #3
 	%0 = mul i32 %v, 9
 	ret i32 %0
@@ -11,7 +11,7 @@ entry:
 
 define i32 @t2(i32 %v) nounwind readnone {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: rsb r0, r0, r0, lsl #3
 	%0 = mul i32 %v, 7
 	ret i32 %0
diff --git a/test/CodeGen/Thumb2/pic-load.ll b/test/CodeGen/Thumb2/pic-load.ll
index 35a03e7..b22fd1d 100644
--- a/test/CodeGen/Thumb2/pic-load.ll
+++ b/test/CodeGen/Thumb2/pic-load.ll
@@ -7,7 +7,7 @@
 
 define hidden i32 @atexit(void ()* %func) nounwind {
 entry:
-; CHECK: atexit:
+; CHECK-LABEL: atexit:
 ; CHECK: add r0, pc
 	%r = alloca %struct.one_atexit_routine, align 4		; <%struct.one_atexit_routine*> [#uses=3]
 	%0 = getelementptr %struct.one_atexit_routine* %r, i32 0, i32 0, i32 0		; <void ()**> [#uses=1]
diff --git a/test/CodeGen/Thumb2/thumb2-adc.ll b/test/CodeGen/Thumb2/thumb2-adc.ll
index 702df91..7c34cfd 100644
--- a/test/CodeGen/Thumb2/thumb2-adc.ll
+++ b/test/CodeGen/Thumb2/thumb2-adc.ll
@@ -2,7 +2,7 @@
 
 ; 734439407618 = 0x000000ab00000002
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: adds r0, #2
     %tmp = add i64 %a, 734439407618
     ret i64 %tmp
@@ -10,7 +10,7 @@ define i64 @f1(i64 %a) {
 
 ; 5066626890203138 = 0x0012001200000002
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: adds r0, #2
     %tmp = add i64 %a, 5066626890203138
     ret i64 %tmp
@@ -18,7 +18,7 @@ define i64 @f2(i64 %a) {
 
 ; 3747052064576897026 = 0x3400340000000002
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: adds r0, #2
     %tmp = add i64 %a, 3747052064576897026
     ret i64 %tmp
@@ -26,7 +26,7 @@ define i64 @f3(i64 %a) {
 
 ; 6221254862626095106 = 0x5656565600000002
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: adds r0, #2
     %tmp = add i64 %a, 6221254862626095106 
     ret i64 %tmp
@@ -34,14 +34,14 @@ define i64 @f4(i64 %a) {
 
 ; 287104476244869122 = 0x03fc000000000002
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: adds r0, #2
     %tmp = add i64 %a, 287104476244869122
     ret i64 %tmp
 }
 
 define i64 @f6(i64 %a, i64 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: adds r0, r0, r2
     %tmp = add i64 %a, %b
     ret i64 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-add.ll b/test/CodeGen/Thumb2/thumb2-add.ll
index 66fca13..c23c74a 100644
--- a/test/CodeGen/Thumb2/thumb2-add.ll
+++ b/test/CodeGen/Thumb2/thumb2-add.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s 
 
 define i32 @t2ADDrc_255(i32 %lhs) {
-; CHECK: t2ADDrc_255:
+; CHECK-LABEL: t2ADDrc_255:
 ; CHECK-NOT: bx lr
 ; CHECK: add{{.*}} #255
 ; CHECK: bx lr
@@ -11,7 +11,7 @@ define i32 @t2ADDrc_255(i32 %lhs) {
 }
 
 define i32 @t2ADDrc_256(i32 %lhs) {
-; CHECK: t2ADDrc_256:
+; CHECK-LABEL: t2ADDrc_256:
 ; CHECK-NOT: bx lr
 ; CHECK: add{{.*}} #256
 ; CHECK: bx lr
@@ -21,7 +21,7 @@ define i32 @t2ADDrc_256(i32 %lhs) {
 }
 
 define i32 @t2ADDrc_257(i32 %lhs) {
-; CHECK: t2ADDrc_257:
+; CHECK-LABEL: t2ADDrc_257:
 ; CHECK-NOT: bx lr
 ; CHECK: add{{.*}} #257
 ; CHECK: bx lr
@@ -31,7 +31,7 @@ define i32 @t2ADDrc_257(i32 %lhs) {
 }
 
 define i32 @t2ADDrc_4094(i32 %lhs) {
-; CHECK: t2ADDrc_4094:
+; CHECK-LABEL: t2ADDrc_4094:
 ; CHECK-NOT: bx lr
 ; CHECK: add{{.*}} #4094
 ; CHECK: bx lr
@@ -41,7 +41,7 @@ define i32 @t2ADDrc_4094(i32 %lhs) {
 }
 
 define i32 @t2ADDrc_4095(i32 %lhs) {
-; CHECK: t2ADDrc_4095:
+; CHECK-LABEL: t2ADDrc_4095:
 ; CHECK-NOT: bx lr
 ; CHECK: add{{.*}} #4095
 ; CHECK: bx lr
@@ -51,7 +51,7 @@ define i32 @t2ADDrc_4095(i32 %lhs) {
 }
 
 define i32 @t2ADDrc_4096(i32 %lhs) {
-; CHECK: t2ADDrc_4096:
+; CHECK-LABEL: t2ADDrc_4096:
 ; CHECK-NOT: bx lr
 ; CHECK: add{{.*}} #4096
 ; CHECK: bx lr
@@ -61,7 +61,7 @@ define i32 @t2ADDrc_4096(i32 %lhs) {
 }
 
 define i32 @t2ADDrr(i32 %lhs, i32 %rhs) {
-; CHECK: t2ADDrr:
+; CHECK-LABEL: t2ADDrr:
 ; CHECK-NOT: bx lr
 ; CHECK: add
 ; CHECK: bx lr
@@ -71,7 +71,7 @@ define i32 @t2ADDrr(i32 %lhs, i32 %rhs) {
 }
 
 define i32 @t2ADDrs(i32 %lhs, i32 %rhs) {
-; CHECK: t2ADDrs:
+; CHECK-LABEL: t2ADDrs:
 ; CHECK-NOT: bx lr
 ; CHECK: add{{.*}} lsl #8
 ; CHECK: bx lr
diff --git a/test/CodeGen/Thumb2/thumb2-add2.ll b/test/CodeGen/Thumb2/thumb2-add2.ll
index e496654..3bbc3bf 100644
--- a/test/CodeGen/Thumb2/thumb2-add2.ll
+++ b/test/CodeGen/Thumb2/thumb2-add2.ll
@@ -2,7 +2,7 @@
 
 ; 171 = 0x000000ab
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: adds r0, #171
     %tmp = add i32 %a, 171
     ret i32 %tmp
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
 
 ; 1179666 = 0x00120012
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: add.w r0, r0, #1179666
     %tmp = add i32 %a, 1179666
     ret i32 %tmp
@@ -18,7 +18,7 @@ define i32 @f2(i32 %a) {
 
 ; 872428544 = 0x34003400
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: add.w r0, r0, #872428544
     %tmp = add i32 %a, 872428544
     ret i32 %tmp
@@ -26,7 +26,7 @@ define i32 @f3(i32 %a) {
 
 ; 1448498774 = 0x56565656
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: add.w r0, r0, #1448498774
     %tmp = add i32 %a, 1448498774
     ret i32 %tmp
@@ -34,7 +34,7 @@ define i32 @f4(i32 %a) {
 
 ; 510 = 0x000001fe
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: add.w r0, r0, #510
     %tmp = add i32 %a, 510
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-add3.ll b/test/CodeGen/Thumb2/thumb2-add3.ll
index 58fc333..6cd818c 100644
--- a/test/CodeGen/Thumb2/thumb2-add3.ll
+++ b/test/CodeGen/Thumb2/thumb2-add3.ll
@@ -5,5 +5,5 @@ define i32 @f1(i32 %a) {
     ret i32 %tmp
 }
 
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	addw	r0, r0, #4095
diff --git a/test/CodeGen/Thumb2/thumb2-add4.ll b/test/CodeGen/Thumb2/thumb2-add4.ll
index b94e84d..8b95711 100644
--- a/test/CodeGen/Thumb2/thumb2-add4.ll
+++ b/test/CodeGen/Thumb2/thumb2-add4.ll
@@ -2,7 +2,7 @@
 
 ; 171 = 0x000000ab
 define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: adds r0, #171
 ; CHECK: adc r1, r1, #0
     %tmp = add i64 %a, 171
@@ -11,7 +11,7 @@ define i64 @f1(i64 %a) {
 
 ; 1179666 = 0x00120012
 define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: adds.w r0, r0, #1179666
 ; CHECK: adc r1, r1, #0
     %tmp = add i64 %a, 1179666
@@ -20,7 +20,7 @@ define i64 @f2(i64 %a) {
 
 ; 872428544 = 0x34003400
 define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: adds.w r0, r0, #872428544
 ; CHECK: adc r1, r1, #0
     %tmp = add i64 %a, 872428544
@@ -29,7 +29,7 @@ define i64 @f3(i64 %a) {
 
 ; 1448498774 = 0x56565656
 define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: adds.w r0, r0, #1448498774
 ; CHECK: adc r1, r1, #0
     %tmp = add i64 %a, 1448498774
@@ -38,7 +38,7 @@ define i64 @f4(i64 %a) {
 
 ; 66846720 = 0x03fc0000
 define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: adds.w r0, r0, #66846720
 ; CHECK: adc r1, r1, #0
     %tmp = add i64 %a, 66846720
diff --git a/test/CodeGen/Thumb2/thumb2-add5.ll b/test/CodeGen/Thumb2/thumb2-add5.ll
index 8b3a4f6..beaa09e 100644
--- a/test/CodeGen/Thumb2/thumb2-add5.ll
+++ b/test/CodeGen/Thumb2/thumb2-add5.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: add r0, r1
     %tmp = add i32 %a, %b
     ret i32 %tmp
 }
 
 define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: add.w r0, r0, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp1 = add i32 %a, %tmp
@@ -16,7 +16,7 @@ define i32 @f2(i32 %a, i32 %b) {
 }
 
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: add.w r0, r0, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp1 = add i32 %a, %tmp
@@ -24,7 +24,7 @@ define i32 @f3(i32 %a, i32 %b) {
 }
 
 define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: add.w r0, r0, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp1 = add i32 %a, %tmp
@@ -32,7 +32,7 @@ define i32 @f4(i32 %a, i32 %b) {
 }
 
 define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: add.w r0, r0, r0, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/thumb2-add6.ll b/test/CodeGen/Thumb2/thumb2-add6.ll
index 0ecaa79..0d2f122 100644
--- a/test/CodeGen/Thumb2/thumb2-add6.ll
+++ b/test/CodeGen/Thumb2/thumb2-add6.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: adds r0, r0, r2
 ; CHECK: adcs r1, r3
     %tmp = add i64 %a, %b
diff --git a/test/CodeGen/Thumb2/thumb2-and.ll b/test/CodeGen/Thumb2/thumb2-and.ll
index 8e2245a..c9578d9 100644
--- a/test/CodeGen/Thumb2/thumb2-and.ll
+++ b/test/CodeGen/Thumb2/thumb2-and.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ands r0, r1
     %tmp = and i32 %a, %b
     ret i32 %tmp
 }
 
 define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: and.w r0, r0, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp1 = and i32 %a, %tmp
@@ -16,7 +16,7 @@ define i32 @f2(i32 %a, i32 %b) {
 }
 
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: and.w r0, r0, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp1 = and i32 %a, %tmp
@@ -24,7 +24,7 @@ define i32 @f3(i32 %a, i32 %b) {
 }
 
 define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: and.w r0, r0, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp1 = and i32 %a, %tmp
@@ -32,7 +32,7 @@ define i32 @f4(i32 %a, i32 %b) {
 }
 
 define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: and.w r0, r0, r0, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/thumb2-and2.ll b/test/CodeGen/Thumb2/thumb2-and2.ll
index 7b0432d..c0501ab 100644
--- a/test/CodeGen/Thumb2/thumb2-and2.ll
+++ b/test/CodeGen/Thumb2/thumb2-and2.ll
@@ -5,7 +5,7 @@ define i32 @f1(i32 %a) {
     %tmp = and i32 %a, 171
     ret i32 %tmp
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	and	r0, r0, #171
 
 ; 1179666 = 0x00120012
@@ -13,7 +13,7 @@ define i32 @f2(i32 %a) {
     %tmp = and i32 %a, 1179666
     ret i32 %tmp
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	and	r0, r0, #1179666
 
 ; 872428544 = 0x34003400
@@ -21,7 +21,7 @@ define i32 @f3(i32 %a) {
     %tmp = and i32 %a, 872428544
     ret i32 %tmp
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	and	r0, r0, #872428544
 
 ; 1448498774 = 0x56565656
@@ -29,7 +29,7 @@ define i32 @f4(i32 %a) {
     %tmp = and i32 %a, 1448498774
     ret i32 %tmp
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: bic r0, r0, #-1448498775
 
 ; 66846720 = 0x03fc0000
@@ -37,5 +37,5 @@ define i32 @f5(i32 %a) {
     %tmp = and i32 %a, 66846720
     ret i32 %tmp
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: 	and	r0, r0, #66846720
diff --git a/test/CodeGen/Thumb2/thumb2-asr.ll b/test/CodeGen/Thumb2/thumb2-asr.ll
index a0a60e6..ba782dd 100644
--- a/test/CodeGen/Thumb2/thumb2-asr.ll
+++ b/test/CodeGen/Thumb2/thumb2-asr.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: asrs r0, r1
     %tmp = ashr i32 %a, %b
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-asr2.ll b/test/CodeGen/Thumb2/thumb2-asr2.ll
index 9c8634f..3685bad 100644
--- a/test/CodeGen/Thumb2/thumb2-asr2.ll
+++ b/test/CodeGen/Thumb2/thumb2-asr2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: asrs r0, r0, #17
     %tmp = ashr i32 %a, 17
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-bcc.ll b/test/CodeGen/Thumb2/thumb2-bcc.ll
index 4a2d600..81f7de9 100644
--- a/test/CodeGen/Thumb2/thumb2-bcc.ll
+++ b/test/CodeGen/Thumb2/thumb2-bcc.ll
@@ -4,7 +4,7 @@
 ; happen and we get actual branches.
 
 define i32 @t1(i32 %a, i32 %b, i32 %c) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: cbz
   %tmp2 = icmp eq i32 %a, 0
   br i1 %tmp2, label %cond_false, label %cond_true
diff --git a/test/CodeGen/Thumb2/thumb2-bfc.ll b/test/CodeGen/Thumb2/thumb2-bfc.ll
index b486045..327b6d1 100644
--- a/test/CodeGen/Thumb2/thumb2-bfc.ll
+++ b/test/CodeGen/Thumb2/thumb2-bfc.ll
@@ -2,7 +2,7 @@
 
 ; 4278190095 = 0xff00000f
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: bfc r
     %tmp = and i32 %a, 4278190095
     ret i32 %tmp
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
 
 ; 4286578688 = 0xff800000
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: bfc r
     %tmp = and i32 %a, 4286578688
     ret i32 %tmp
@@ -18,7 +18,7 @@ define i32 @f2(i32 %a) {
 
 ; 4095 = 0x00000fff
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: bfc r
     %tmp = and i32 %a, 4095
     ret i32 %tmp
@@ -26,7 +26,7 @@ define i32 @f3(i32 %a) {
 
 ; 2147483646 = 0x7ffffffe   not implementable w/ BFC
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
     %tmp = and i32 %a, 2147483646
     ret i32 %tmp
 }
diff --git a/test/CodeGen/Thumb2/thumb2-bic.ll b/test/CodeGen/Thumb2/thumb2-bic.ll
index 4e35383..5938fa1 100644
--- a/test/CodeGen/Thumb2/thumb2-bic.ll
+++ b/test/CodeGen/Thumb2/thumb2-bic.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: bics r0, r1
     %tmp = xor i32 %b, 4294967295
     %tmp1 = and i32 %a, %tmp
@@ -9,7 +9,7 @@ define i32 @f1(i32 %a, i32 %b) {
 }
 
 define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: bics r0, r1
     %tmp = xor i32 %b, 4294967295
     %tmp1 = and i32 %tmp, %a
@@ -17,7 +17,7 @@ define i32 @f2(i32 %a, i32 %b) {
 }
 
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: bics r0, r1
     %tmp = xor i32 4294967295, %b
     %tmp1 = and i32 %a, %tmp
@@ -25,7 +25,7 @@ define i32 @f3(i32 %a, i32 %b) {
 }
 
 define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: bics r0, r1
     %tmp = xor i32 4294967295, %b
     %tmp1 = and i32 %tmp, %a
@@ -33,7 +33,7 @@ define i32 @f4(i32 %a, i32 %b) {
 }
 
 define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: bic.w r0, r0, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp1 = xor i32 4294967295, %tmp
@@ -42,7 +42,7 @@ define i32 @f5(i32 %a, i32 %b) {
 }
 
 define i32 @f6(i32 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: bic.w r0, r0, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp1 = xor i32 %tmp, 4294967295
@@ -51,7 +51,7 @@ define i32 @f6(i32 %a, i32 %b) {
 }
 
 define i32 @f7(i32 %a, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: bic.w r0, r0, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp1 = xor i32 %tmp, 4294967295
@@ -60,7 +60,7 @@ define i32 @f7(i32 %a, i32 %b) {
 }
 
 define i32 @f8(i32 %a, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: bic.w r0, r0, r0, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
@@ -75,7 +75,7 @@ define i32 @f9(i32 %a) {
     %tmp = and i32 %a, 4294967108
     ret i32 %tmp
     
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: bic r0, r0, #187
 }
 
@@ -84,7 +84,7 @@ define i32 @f10(i32 %a) {
     %tmp = and i32 %a, 4283826005
     ret i32 %tmp
     
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: bic r0, r0, #11141290
 }
 
@@ -92,7 +92,7 @@ define i32 @f10(i32 %a) {
 define i32 @f11(i32 %a) {
     %tmp = and i32 %a, 872363007
     ret i32 %tmp
-; CHECK: f11:
+; CHECK-LABEL: f11:
 ; CHECK: bic r0, r0, #-872363008
 }
 
@@ -100,6 +100,6 @@ define i32 @f11(i32 %a) {
 define i32 @f12(i32 %a) {
     %tmp = and i32 %a, 4293853183
     ret i32 %tmp
-; CHECK: f12:
+; CHECK-LABEL: f12:
 ; CHECK: bic r0, r0, #1114112
 }
diff --git a/test/CodeGen/Thumb2/thumb2-branch.ll b/test/CodeGen/Thumb2/thumb2-branch.ll
index f1c097c..a00b22d 100644
--- a/test/CodeGen/Thumb2/thumb2-branch.ll
+++ b/test/CodeGen/Thumb2/thumb2-branch.ll
@@ -1,72 +1,74 @@
 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
-; If-conversion defeats the purpose of this test, which is to check conditional
-; branch generation, so use memory barrier instruction to make sure it doesn't
+; If-conversion defeats the purpose of this test, which is to check
+; conditional branch generation, so a call to make sure it doesn't
 ; happen and we get actual branches.
 
+declare void @foo()
+
 define i32 @f1(i32 %a, i32 %b, i32* %v) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: bne LBB
         %tmp = icmp eq i32 %a, %b               ; <i1> [#uses=1]
         br i1 %tmp, label %cond_true, label %return
 
 cond_true:              ; preds = %entry
-        fence seq_cst
+        call void @foo()
         store i32 0, i32* %v
         ret i32 0
 
 return:         ; preds = %entry
-        fence seq_cst
+        call void @foo()
         ret i32 1
 }
 
 define i32 @f2(i32 %a, i32 %b, i32* %v) {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: bge LBB
         %tmp = icmp slt i32 %a, %b              ; <i1> [#uses=1]
         br i1 %tmp, label %cond_true, label %return
 
 cond_true:              ; preds = %entry
-        fence seq_cst
+        call void @foo()
         store i32 0, i32* %v
         ret i32 0
 
 return:         ; preds = %entry
-        fence seq_cst
+        call void @foo()
         ret i32 1
 }
 
 define i32 @f3(i32 %a, i32 %b, i32* %v) {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: bhs LBB
         %tmp = icmp ult i32 %a, %b              ; <i1> [#uses=1]
         br i1 %tmp, label %cond_true, label %return
 
 cond_true:              ; preds = %entry
-        fence seq_cst
+        call void @foo()
         store i32 0, i32* %v
         ret i32 0
 
 return:         ; preds = %entry
-        fence seq_cst
+        call void @foo()
         ret i32 1
 }
 
 define i32 @f4(i32 %a, i32 %b, i32* %v) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: blo LBB
         %tmp = icmp uge i32 %a, %b              ; <i1> [#uses=1]
         br i1 %tmp, label %cond_true, label %return
 
 cond_true:              ; preds = %entry
-        fence seq_cst
+        call void @foo()
         store i32 0, i32* %v
         ret i32 0
 
 return:         ; preds = %entry
-        fence seq_cst
+        call void @foo()
         ret i32 1
 }
diff --git a/test/CodeGen/Thumb2/thumb2-call-tc.ll b/test/CodeGen/Thumb2/thumb2-call-tc.ll
index 2e4da1b..2902949 100644
--- a/test/CodeGen/Thumb2/thumb2-call-tc.ll
+++ b/test/CodeGen/Thumb2/thumb2-call-tc.ll
@@ -7,20 +7,20 @@
 declare void @g(i32, i32, i32, i32)
 
 define void @f() {
-; DARWIN: f:
+; DARWIN-LABEL: f:
 ; DARWIN: blx _g
 
-; LINUX: f:
+; LINUX-LABEL: f:
 ; LINUX: bl g
         tail call void @g( i32 1, i32 2, i32 3, i32 4 )
         ret void
 }
 
 define void @h() {
-; DARWIN: h:
+; DARWIN-LABEL: h:
 ; DARWIN: bx r0 @ TAILCALL
 
-; LINUX: h:
+; LINUX-LABEL: h:
 ; LINUX: bx r0 @ TAILCALL
         %tmp = load i32 ()** @t         ; <i32 ()*> [#uses=1]
         %tmp.upgrd.2 = tail call i32 %tmp( )            ; <i32> [#uses=0]
@@ -28,10 +28,10 @@ define void @h() {
 }
 
 define void @j() {
-; DARWIN: j:
+; DARWIN-LABEL: j:
 ; DARWIN: b.w _f  @ TAILCALL
 
-; LINUX: j:
+; LINUX-LABEL: j:
 ; LINUX: b.w f  @ TAILCALL
         tail call void @f()
         ret void
diff --git a/test/CodeGen/Thumb2/thumb2-call.ll b/test/CodeGen/Thumb2/thumb2-call.ll
index 8513cfb..1d2eaa7 100644
--- a/test/CodeGen/Thumb2/thumb2-call.ll
+++ b/test/CodeGen/Thumb2/thumb2-call.ll
@@ -6,20 +6,20 @@
 declare void @g(i32, i32, i32, i32)
 
 define void @f() {
-; DARWIN: f:
+; DARWIN-LABEL: f:
 ; DARWIN: blx _g
 
-; LINUX: f:
+; LINUX-LABEL: f:
 ; LINUX: bl g
         call void @g( i32 1, i32 2, i32 3, i32 4 )
         ret void
 }
 
 define void @h() {
-; DARWIN: h:
+; DARWIN-LABEL: h:
 ; DARWIN: blx r0
 
-; LINUX: h:
+; LINUX-LABEL: h:
 ; LINUX: blx r0
         %tmp = load i32 ()** @t         ; <i32 ()*> [#uses=1]
         %tmp.upgrd.2 = call i32 %tmp( )            ; <i32> [#uses=0]
diff --git a/test/CodeGen/Thumb2/thumb2-clz.ll b/test/CodeGen/Thumb2/thumb2-clz.ll
index f7e9665..dbdaae2 100644
--- a/test/CodeGen/Thumb2/thumb2-clz.ll
+++ b/test/CodeGen/Thumb2/thumb2-clz.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7 | FileCheck %s
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: clz r
     %tmp = tail call i32 @llvm.ctlz.i32(i32 %a, i1 true)
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-cmn.ll b/test/CodeGen/Thumb2/thumb2-cmn.ll
index 67b07e6..8bcaa7e 100644
--- a/test/CodeGen/Thumb2/thumb2-cmn.ll
+++ b/test/CodeGen/Thumb2/thumb2-cmn.ll
@@ -8,7 +8,7 @@ define i1 @f1(i32 %a, i32 %b) {
     %tmp = icmp ne i32 %a, %nb
     ret i1 %tmp
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	cmn	{{.*}}, r1
 
 define i1 @f2(i32 %a, i32 %b) {
@@ -16,7 +16,7 @@ define i1 @f2(i32 %a, i32 %b) {
     %tmp = icmp ne i32 %nb, %a
     ret i1 %tmp
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	cmn	{{.*}}, r1
 
 define i1 @f3(i32 %a, i32 %b) {
@@ -24,7 +24,7 @@ define i1 @f3(i32 %a, i32 %b) {
     %tmp = icmp eq i32 %a, %nb
     ret i1 %tmp
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	cmn	{{.*}}, r1
 
 define i1 @f4(i32 %a, i32 %b) {
@@ -32,7 +32,7 @@ define i1 @f4(i32 %a, i32 %b) {
     %tmp = icmp eq i32 %nb, %a
     ret i1 %tmp
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: 	cmn	{{.*}}, r1
 
 define i1 @f5(i32 %a, i32 %b) {
@@ -41,7 +41,7 @@ define i1 @f5(i32 %a, i32 %b) {
     %tmp1 = icmp eq i32 %nb, %a
     ret i1 %tmp1
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: 	cmn.w	{{.*}}, r1, lsl #5
 
 define i1 @f6(i32 %a, i32 %b) {
@@ -50,7 +50,7 @@ define i1 @f6(i32 %a, i32 %b) {
     %tmp1 = icmp ne i32 %nb, %a
     ret i1 %tmp1
 }
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: 	cmn.w	{{.*}}, r1, lsr #6
 
 define i1 @f7(i32 %a, i32 %b) {
@@ -59,7 +59,7 @@ define i1 @f7(i32 %a, i32 %b) {
     %tmp1 = icmp eq i32 %a, %nb
     ret i1 %tmp1
 }
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: 	cmn.w	{{.*}}, r1, asr #7
 
 define i1 @f8(i32 %a, i32 %b) {
@@ -70,7 +70,7 @@ define i1 @f8(i32 %a, i32 %b) {
     %tmp1 = icmp ne i32 %a, %nb
     ret i1 %tmp1
 }
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: 	cmn.w	{{.*}}, {{.*}}, ror #8
 
 
@@ -81,5 +81,5 @@ define void @f9(i32 %a, i32 %b) nounwind optsize {
 
 !0 = metadata !{i32 81}
 
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: 	cmn.w	r0, r1
diff --git a/test/CodeGen/Thumb2/thumb2-cmn2.ll b/test/CodeGen/Thumb2/thumb2-cmn2.ll
index c0e19f6..f5db728 100644
--- a/test/CodeGen/Thumb2/thumb2-cmn2.ll
+++ b/test/CodeGen/Thumb2/thumb2-cmn2.ll
@@ -2,7 +2,7 @@
 
 ; -0x000000bb = 4294967109
 define i1 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cmn.w {{r.*}}, #187
     %tmp = icmp ne i32 %a, 4294967109
     ret i1 %tmp
@@ -10,7 +10,7 @@ define i1 @f1(i32 %a) {
 
 ; -0x00aa00aa = 4283826006
 define i1 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cmn.w {{r.*}}, #11141290
     %tmp = icmp eq i32 %a, 4283826006
     ret i1 %tmp
@@ -18,7 +18,7 @@ define i1 @f2(i32 %a) {
 
 ; -0xcc00cc00 = 872363008
 define i1 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cmn.w {{r.*}}, #-872363008
     %tmp = icmp ne i32 %a, 872363008
     ret i1 %tmp
@@ -26,7 +26,7 @@ define i1 @f3(i32 %a) {
 
 ; -0x00110000 = 4293853184
 define i1 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cmn.w {{r.*}}, #1114112
     %tmp = icmp eq i32 %a, 4293853184
     ret i1 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-cmp.ll b/test/CodeGen/Thumb2/thumb2-cmp.ll
index 4ce7acc..8741344 100644
--- a/test/CodeGen/Thumb2/thumb2-cmp.ll
+++ b/test/CodeGen/Thumb2/thumb2-cmp.ll
@@ -5,7 +5,7 @@
 
 ; 0x000000bb = 187
 define i1 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cmp {{.*}}, #187
     %tmp = icmp ne i32 %a, 187
     ret i1 %tmp
@@ -13,7 +13,7 @@ define i1 @f1(i32 %a) {
 
 ; 0x00aa00aa = 11141290
 define i1 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cmp.w {{.*}}, #11141290
     %tmp = icmp eq i32 %a, 11141290 
     ret i1 %tmp
@@ -21,7 +21,7 @@ define i1 @f2(i32 %a) {
 
 ; 0xcc00cc00 = 3422604288
 define i1 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: cmp.w {{.*}}, #-872363008
     %tmp = icmp ne i32 %a, 3422604288
     ret i1 %tmp
@@ -29,7 +29,7 @@ define i1 @f3(i32 %a) {
 
 ; 0xdddddddd = 3722304989
 define i1 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: cmp.w {{.*}}, #-572662307
     %tmp = icmp ne i32 %a, 3722304989
     ret i1 %tmp
@@ -37,7 +37,7 @@ define i1 @f4(i32 %a) {
 
 ; 0x00110000 = 1114112
 define i1 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: cmp.w {{.*}}, #1114112
     %tmp = icmp eq i32 %a, 1114112
     ret i1 %tmp
@@ -45,7 +45,7 @@ define i1 @f5(i32 %a) {
 
 ; Check that we don't do an invalid (a > b) --> !(a < b + 1) transform.
 ;
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK-NOT: cmp.w {{.*}}, #-2147483648
 ; CHECK: bx lr
 define i32 @f6(i32 %a) {
diff --git a/test/CodeGen/Thumb2/thumb2-cmp2.ll b/test/CodeGen/Thumb2/thumb2-cmp2.ll
index f6790de..5b880f1 100644
--- a/test/CodeGen/Thumb2/thumb2-cmp2.ll
+++ b/test/CodeGen/Thumb2/thumb2-cmp2.ll
@@ -4,21 +4,21 @@
 ; test as 'mov.w r0, #0'.
 
 define i1 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: cmp {{.*}}, r1
     %tmp = icmp ne i32 %a, %b
     ret i1 %tmp
 }
 
 define i1 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: cmp {{.*}}, r1
     %tmp = icmp eq i32 %a, %b
     ret i1 %tmp
 }
 
 define i1 @f6(i32 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: cmp.w {{.*}}, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp1 = icmp eq i32 %tmp, %a
@@ -26,7 +26,7 @@ define i1 @f6(i32 %a, i32 %b) {
 }
 
 define i1 @f7(i32 %a, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: cmp.w {{.*}}, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp1 = icmp ne i32 %tmp, %a
@@ -34,7 +34,7 @@ define i1 @f7(i32 %a, i32 %b) {
 }
 
 define i1 @f8(i32 %a, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: cmp.w {{.*}}, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp1 = icmp eq i32 %a, %tmp
@@ -42,7 +42,7 @@ define i1 @f8(i32 %a, i32 %b) {
 }
 
 define i1 @f9(i32 %a, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: cmp.w {{.*}}, {{.*}}, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/thumb2-eor.ll b/test/CodeGen/Thumb2/thumb2-eor.ll
index 116a1a3..b3e323c 100644
--- a/test/CodeGen/Thumb2/thumb2-eor.ll
+++ b/test/CodeGen/Thumb2/thumb2-eor.ll
@@ -1,28 +1,28 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: eors r0, r1
     %tmp = xor i32 %a, %b
     ret i32 %tmp
 }
 
 define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: eors r0, r1
     %tmp = xor i32 %b, %a
     ret i32 %tmp
 }
 
 define i32 @f2b(i32 %a, i32 %b, i32 %c) {
-; CHECK: f2b:
+; CHECK-LABEL: f2b:
 ; CHECK: eor.w r0, r1, r2
     %tmp = xor i32 %b, %c
     ret i32 %tmp
 }
 
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: eor.w r0, r0, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp1 = xor i32 %a, %tmp
@@ -30,7 +30,7 @@ define i32 @f3(i32 %a, i32 %b) {
 }
 
 define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: eor.w r0, r0, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp1 = xor i32 %tmp, %a
@@ -38,7 +38,7 @@ define i32 @f4(i32 %a, i32 %b) {
 }
 
 define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: eor.w r0, r0, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp1 = xor i32 %a, %tmp
@@ -46,7 +46,7 @@ define i32 @f5(i32 %a, i32 %b) {
 }
 
 define i32 @f6(i32 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: eor.w r0, r0, r0, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/thumb2-eor2.ll b/test/CodeGen/Thumb2/thumb2-eor2.ll
index 6b2e9dc..5daa13d 100644
--- a/test/CodeGen/Thumb2/thumb2-eor2.ll
+++ b/test/CodeGen/Thumb2/thumb2-eor2.ll
@@ -2,7 +2,7 @@
 
 ; 0x000000bb = 187
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: eor {{.*}}#187
     %tmp = xor i32 %a, 187
     ret i32 %tmp
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
 
 ; 0x00aa00aa = 11141290
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: eor {{.*}}#11141290
     %tmp = xor i32 %a, 11141290 
     ret i32 %tmp
@@ -18,7 +18,7 @@ define i32 @f2(i32 %a) {
 
 ; 0xcc00cc00 = 3422604288
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: eor {{.*}}#-872363008
     %tmp = xor i32 %a, 3422604288
     ret i32 %tmp
@@ -26,7 +26,7 @@ define i32 @f3(i32 %a) {
 
 ; 0xdddddddd = 3722304989
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: eor {{.*}}#-572662307
     %tmp = xor i32 %a, 3722304989
     ret i32 %tmp
@@ -34,7 +34,7 @@ define i32 @f4(i32 %a) {
 
 ; 0x00110000 = 1114112
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: eor {{.*}}#1114112
     %tmp = xor i32 %a, 1114112
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll b/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll
index 5315535..d86a897 100644
--- a/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll
@@ -2,7 +2,7 @@
 ; XFAIL: *
 
 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: it ne
 ; CHECK: cmpne
 	switch i32 %c, label %cond_next [
@@ -23,7 +23,7 @@ cond_next:
 ; FIXME: Check for # of unconditional branch after adding branch folding post ifcvt.
 define i32 @t2(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: ite gt
 ; CHECK: subgt
 ; CHECK: suble
@@ -71,7 +71,7 @@ entry:
 ; Tail call prevents use of ifcvt in this one.  Seems like a win though.
 define void @t3(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK-NOT: it lt
 ; CHECK-NOT: poplt
 ; CHECK: b.w _foo @ TAILCALL
diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
index af8fcc6..85943cf 100644
--- a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
 
 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: ittt ne
 ; CHECK: cmpne
 ; CHECK: addne
@@ -24,7 +24,7 @@ cond_next:
 define i32 @t2(i32 %a, i32 %b) nounwind {
 entry:
 ; Do not if-convert when branches go to the different loops.
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK-NOT: ite gt
 ; CHECK-NOT: subgt
 ; CHECK-NOT: suble
@@ -71,7 +71,7 @@ entry:
 
 define void @t3(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: itt ge
 ; CHECK: movge r0, r1
 ; CHECK: blge  _foo
diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
index 5aa9a73..788fa06 100644
--- a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
@@ -2,7 +2,7 @@
 
 define void @foo(i32 %X, i32 %Y) {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: it ne
 ; CHECK: cmpne
 ; CHECK: it hi
@@ -28,14 +28,14 @@ declare i32 @bar(...)
 
 define fastcc i32 @CountTree(%struct.quad_struct* %tree) {
 entry:
-; CHECK: CountTree:
-; CHECK: itt eq
-; CHECK: moveq
-; CHECK: popeq
+; CHECK-LABEL: CountTree:
 ; CHECK: bne
 ; CHECK: cmp
 ; CHECK: it eq
 ; CHECK: cmpeq
+; CHECK: itt eq
+; CHECK: moveq
+; CHECK: popeq
 	br label %tailrecurse
 
 tailrecurse:		; preds = %bb, %entry
@@ -65,7 +65,7 @@ declare void @abort()
 
 define fastcc void @t1(%struct.SString* %word, i8 signext  %c) {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: it ne
 ; CHECK: popne {r7, pc}
 	%tmp1 = icmp eq %struct.SString* %word, null		; <i1> [#uses=1]
@@ -81,7 +81,7 @@ cond_false:		; preds = %entry
 
 define fastcc void @t2() nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: cmp r0, #0
 ; CHECK: %growMapping.exit
 	br i1 undef, label %bb.i.i3, label %growMapping.exit
diff --git a/test/CodeGen/Thumb2/thumb2-ldm.ll b/test/CodeGen/Thumb2/thumb2-ldm.ll
index b2328e7..8716d80 100644
--- a/test/CodeGen/Thumb2/thumb2-ldm.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldm.ll
@@ -3,7 +3,7 @@
 @X = external global [0 x i32]          ; <[0 x i32]*> [#uses=5]
 
 define i32 @t1() {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: push {r7, lr}
 ; CHECK: pop {r7, pc}
         %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0)            ; <i32> [#uses=1]
@@ -13,7 +13,7 @@ define i32 @t1() {
 }
 
 define i32 @t2() {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: push {r7, lr}
 ; CHECK: ldm
 ; CHECK: pop {r7, pc}
@@ -25,7 +25,7 @@ define i32 @t2() {
 }
 
 define i32 @t3() {
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: push {r7, lr}
 ; CHECK: pop {r7, pc}
         %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1)            ; <i32> [#uses=1]
diff --git a/test/CodeGen/Thumb2/thumb2-ldr.ll b/test/CodeGen/Thumb2/thumb2-ldr.ll
index 88434f1..7f68f66 100644
--- a/test/CodeGen/Thumb2/thumb2-ldr.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldr.ll
@@ -2,7 +2,7 @@
 
 define i32 @f1(i32* %v) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldr r0, [r0]
         %tmp = load i32* %v
         ret i32 %tmp
@@ -10,7 +10,7 @@ entry:
 
 define i32 @f2(i32* %v) {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldr.w r0, [r0, #4092]
         %tmp2 = getelementptr i32* %v, i32 1023
         %tmp = load i32* %tmp2
@@ -19,7 +19,7 @@ entry:
 
 define i32 @f3(i32* %v) {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov.w r1, #4096
 ; CHECK: ldr r0, [r0, r1]
         %tmp2 = getelementptr i32* %v, i32 1024
@@ -29,7 +29,7 @@ entry:
 
 define i32 @f4(i32 %base) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldr r0, [r0, #-128]
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i32*
@@ -39,7 +39,7 @@ entry:
 
 define i32 @f5(i32 %base, i32 %offset) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldr r0, [r0, r1]
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i32*
@@ -49,7 +49,7 @@ entry:
 
 define i32 @f6(i32 %base, i32 %offset) {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ldr.w r0, [r0, r1, lsl #2]
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
@@ -60,7 +60,7 @@ entry:
 
 define i32 @f7(i32 %base, i32 %offset) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lsrs r1, r1, #2
 ; CHECK: ldr r0, [r0, r1]
 
diff --git a/test/CodeGen/Thumb2/thumb2-ldrb.ll b/test/CodeGen/Thumb2/thumb2-ldrb.ll
index bf10097..c135eff 100644
--- a/test/CodeGen/Thumb2/thumb2-ldrb.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldrb.ll
@@ -2,7 +2,7 @@
 
 define i8 @f1(i8* %v) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldrb r0, [r0]
         %tmp = load i8* %v
         ret i8 %tmp
@@ -10,7 +10,7 @@ entry:
 
 define i8 @f2(i8* %v) {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldrb r0, [r0, #-1]
         %tmp2 = getelementptr i8* %v, i8 1023
         %tmp = load i8* %tmp2
@@ -19,7 +19,7 @@ entry:
 
 define i8 @f3(i32 %base) {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov.w r1, #4096
 ; CHECK: ldrb r0, [r0, r1]
         %tmp1 = add i32 %base, 4096
@@ -30,7 +30,7 @@ entry:
 
 define i8 @f4(i32 %base) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldrb r0, [r0, #-128]
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i8*
@@ -40,7 +40,7 @@ entry:
 
 define i8 @f5(i32 %base, i32 %offset) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldrb r0, [r0, r1]
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i8*
@@ -50,7 +50,7 @@ entry:
 
 define i8 @f6(i32 %base, i32 %offset) {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ldrb.w r0, [r0, r1, lsl #2]
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
@@ -61,7 +61,7 @@ entry:
 
 define i8 @f7(i32 %base, i32 %offset) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lsrs r1, r1, #2
 ; CHECK: ldrb r0, [r0, r1]
         %tmp1 = lshr i32 %offset, 2
diff --git a/test/CodeGen/Thumb2/thumb2-ldrh.ll b/test/CodeGen/Thumb2/thumb2-ldrh.ll
index fee97bf..99f6aba 100644
--- a/test/CodeGen/Thumb2/thumb2-ldrh.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldrh.ll
@@ -2,7 +2,7 @@
 
 define i16 @f1(i16* %v) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldrh r0, [r0]
         %tmp = load i16* %v
         ret i16 %tmp
@@ -10,7 +10,7 @@ entry:
 
 define i16 @f2(i16* %v) {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldrh.w r0, [r0, #2046]
         %tmp2 = getelementptr i16* %v, i16 1023
         %tmp = load i16* %tmp2
@@ -19,7 +19,7 @@ entry:
 
 define i16 @f3(i16* %v) {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov.w r1, #4096
 ; CHECK: ldrh r0, [r0, r1]
         %tmp2 = getelementptr i16* %v, i16 2048
@@ -29,7 +29,7 @@ entry:
 
 define i16 @f4(i32 %base) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldrh r0, [r0, #-128]
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i16*
@@ -39,7 +39,7 @@ entry:
 
 define i16 @f5(i32 %base, i32 %offset) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldrh r0, [r0, r1]
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i16*
@@ -49,7 +49,7 @@ entry:
 
 define i16 @f6(i32 %base, i32 %offset) {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: ldrh.w r0, [r0, r1, lsl #2]
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
@@ -60,7 +60,7 @@ entry:
 
 define i16 @f7(i32 %base, i32 %offset) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lsrs r1, r1, #2
 ; CHECK: ldrh r0, [r0, r1]
         %tmp1 = lshr i32 %offset, 2
diff --git a/test/CodeGen/Thumb2/thumb2-lsl.ll b/test/CodeGen/Thumb2/thumb2-lsl.ll
index 6b0818a..1b48538 100644
--- a/test/CodeGen/Thumb2/thumb2-lsl.ll
+++ b/test/CodeGen/Thumb2/thumb2-lsl.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lsls r0, r0, #5
     %tmp = shl i32 %a, 5
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-lsl2.ll b/test/CodeGen/Thumb2/thumb2-lsl2.ll
index f283eef..bc0978e 100644
--- a/test/CodeGen/Thumb2/thumb2-lsl2.ll
+++ b/test/CodeGen/Thumb2/thumb2-lsl2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lsls r0, r1
     %tmp = shl i32 %a, %b
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-lsr.ll b/test/CodeGen/Thumb2/thumb2-lsr.ll
index 7cbee54..a3b207c 100644
--- a/test/CodeGen/Thumb2/thumb2-lsr.ll
+++ b/test/CodeGen/Thumb2/thumb2-lsr.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lsrs r0, r0, #13
     %tmp = lshr i32 %a, 13
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-lsr2.ll b/test/CodeGen/Thumb2/thumb2-lsr2.ll
index 87800f9..ae55735 100644
--- a/test/CodeGen/Thumb2/thumb2-lsr2.ll
+++ b/test/CodeGen/Thumb2/thumb2-lsr2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: lsrs r0, r1
     %tmp = lshr i32 %a, %b
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-mla.ll b/test/CodeGen/Thumb2/thumb2-mla.ll
index 594d974..709fa13 100644
--- a/test/CodeGen/Thumb2/thumb2-mla.ll
+++ b/test/CodeGen/Thumb2/thumb2-mla.ll
@@ -6,9 +6,9 @@ define i32 @f1(i32 %a, i32 %b, i32 %c) {
     %tmp2 = add i32 %c, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	mla	r0, r0, r1, r2
-; NO_MULOPS: f1:
+; NO_MULOPS-LABEL: f1:
 ; NO_MULOPS: muls r0, r1, r0
 ; NO_MULOPS-NEXT: add r0, r2
 
@@ -17,8 +17,8 @@ define i32 @f2(i32 %a, i32 %b, i32 %c) {
     %tmp2 = add i32 %tmp1, %c
     ret i32 %tmp2
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	mla	r0, r0, r1, r2
-; NO_MULOPS: f2:
+; NO_MULOPS-LABEL: f2:
 ; NO_MULOPS: muls r0, r1, r0
 ; NO_MULOPS-NEXT: add r0, r2
diff --git a/test/CodeGen/Thumb2/thumb2-mls.ll b/test/CodeGen/Thumb2/thumb2-mls.ll
index 58f9add..86e147b 100644
--- a/test/CodeGen/Thumb2/thumb2-mls.ll
+++ b/test/CodeGen/Thumb2/thumb2-mls.ll
@@ -5,7 +5,7 @@ define i32 @f1(i32 %a, i32 %b, i32 %c) {
     %tmp2 = sub i32 %c, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	mls	r0, r0, r1, r2
 
 ; sub doesn't commute, so no mls for this one
@@ -14,6 +14,6 @@ define i32 @f2(i32 %a, i32 %b, i32 %c) {
     %tmp2 = sub i32 %tmp1, %c
     ret i32 %tmp2
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	muls	r0, r1, r0
 
diff --git a/test/CodeGen/Thumb2/thumb2-mov.ll b/test/CodeGen/Thumb2/thumb2-mov.ll
index adb6dde..148bafe 100644
--- a/test/CodeGen/Thumb2/thumb2-mov.ll
+++ b/test/CodeGen/Thumb2/thumb2-mov.ll
@@ -4,14 +4,14 @@
 
 ; var 2.1 - 0x00ab00ab
 define i32 @t2_const_var2_1_ok_1(i32 %lhs) {
-;CHECK: t2_const_var2_1_ok_1:
+;CHECK-LABEL: t2_const_var2_1_ok_1:
 ;CHECK: add.w   r0, r0, #11206827
     %ret = add i32 %lhs, 11206827 ; 0x00ab00ab
     ret i32 %ret
 }
 
 define i32 @t2_const_var2_1_ok_2(i32 %lhs) {
-;CHECK: t2_const_var2_1_ok_2:
+;CHECK-LABEL: t2_const_var2_1_ok_2:
 ;CHECK: add.w   r0, r0, #11206656
 ;CHECK: adds    r0, #187
     %ret = add i32 %lhs, 11206843 ; 0x00ab00bb
@@ -19,7 +19,7 @@ define i32 @t2_const_var2_1_ok_2(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_1_ok_3(i32 %lhs) {
-;CHECK: t2_const_var2_1_ok_3:
+;CHECK-LABEL: t2_const_var2_1_ok_3:
 ;CHECK: add.w   r0, r0, #11206827
 ;CHECK: add.w   r0, r0, #16777216
     %ret = add i32 %lhs, 27984043 ; 0x01ab00ab
@@ -27,7 +27,7 @@ define i32 @t2_const_var2_1_ok_3(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_1_ok_4(i32 %lhs) {
-;CHECK: t2_const_var2_1_ok_4:
+;CHECK-LABEL: t2_const_var2_1_ok_4:
 ;CHECK: add.w   r0, r0, #16777472
 ;CHECK: add.w   r0, r0, #11206827
     %ret = add i32 %lhs, 27984299 ; 0x01ab01ab
@@ -35,7 +35,7 @@ define i32 @t2_const_var2_1_ok_4(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
-;CHECK: t2_const_var2_1_fail_1:
+;CHECK-LABEL: t2_const_var2_1_fail_1:
 ;CHECK: movw    r1, #43777
 ;CHECK: movt    r1, #427
 ;CHECK: add     r0, r1
@@ -45,14 +45,14 @@ define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
 
 ; var 2.2 - 0xab00ab00
 define i32 @t2_const_var2_2_ok_1(i32 %lhs) {
-;CHECK: t2_const_var2_2_ok_1:
+;CHECK-LABEL: t2_const_var2_2_ok_1:
 ;CHECK: add.w   r0, r0, #-1426019584
     %ret = add i32 %lhs, 2868947712 ; 0xab00ab00
     ret i32 %ret
 }
 
 define i32 @t2_const_var2_2_ok_2(i32 %lhs) {
-;CHECK: t2_const_var2_2_ok_2:
+;CHECK-LABEL: t2_const_var2_2_ok_2:
 ;CHECK: add.w   r0, r0, #2868903936
 ;CHECK: add.w   r0, r0, #47616
     %ret = add i32 %lhs, 2868951552 ; 0xab00ba00
@@ -60,7 +60,7 @@ define i32 @t2_const_var2_2_ok_2(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_2_ok_3(i32 %lhs) {
-;CHECK: t2_const_var2_2_ok_3:
+;CHECK-LABEL: t2_const_var2_2_ok_3:
 ;CHECK: add.w   r0, r0, #2868947712
 ;CHECK: adds    r0, #16
     %ret = add i32 %lhs, 2868947728 ; 0xab00ab10
@@ -68,7 +68,7 @@ define i32 @t2_const_var2_2_ok_3(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_2_ok_4(i32 %lhs) {
-;CHECK: t2_const_var2_2_ok_4:
+;CHECK-LABEL: t2_const_var2_2_ok_4:
 ;CHECK: add.w   r0, r0, #2868947712
 ;CHECK: add.w   r0, r0, #1048592
     %ret = add i32 %lhs, 2869996304 ; 0xab10ab10
@@ -76,7 +76,7 @@ define i32 @t2_const_var2_2_ok_4(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
-;CHECK: t2_const_var2_2_fail_1:
+;CHECK-LABEL: t2_const_var2_2_fail_1:
 ;CHECK: movw    r1, #43792
 ;CHECK: movt    r1, #4267
 ;CHECK: add     r0, r1
@@ -86,14 +86,14 @@ define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
 
 ; var 2.3 - 0xabababab
 define i32 @t2_const_var2_3_ok_1(i32 %lhs) {
-;CHECK: t2_const_var2_3_ok_1:
+;CHECK-LABEL: t2_const_var2_3_ok_1:
 ;CHECK: add.w   r0, r0, #-1414812757
     %ret = add i32 %lhs, 2880154539 ; 0xabababab
     ret i32 %ret
 }
 
 define i32 @t2_const_var2_3_fail_1(i32 %lhs) {
-;CHECK: t2_const_var2_3_fail_1:
+;CHECK-LABEL: t2_const_var2_3_fail_1:
 ;CHECK: movw    r1, #43962
 ;CHECK: movt    r1, #43947
 ;CHECK: add     r0, r1
@@ -102,7 +102,7 @@ define i32 @t2_const_var2_3_fail_1(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_3_fail_2(i32 %lhs) {
-;CHECK: t2_const_var2_3_fail_2:
+;CHECK-LABEL: t2_const_var2_3_fail_2:
 ;CHECK: movw    r1, #47787
 ;CHECK: movt    r1, #43947
 ;CHECK: add     r0, r1
@@ -111,7 +111,7 @@ define i32 @t2_const_var2_3_fail_2(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_3_fail_3(i32 %lhs) {
-;CHECK: t2_const_var2_3_fail_3:
+;CHECK-LABEL: t2_const_var2_3_fail_3:
 ;CHECK: movw    r1, #43947
 ;CHECK: movt    r1, #43962
 ;CHECK: add     r0, r1
@@ -120,7 +120,7 @@ define i32 @t2_const_var2_3_fail_3(i32 %lhs) {
 }
 
 define i32 @t2_const_var2_3_fail_4(i32 %lhs) {
-;CHECK: t2_const_var2_3_fail_4:
+;CHECK-LABEL: t2_const_var2_3_fail_4:
 ;CHECK: movw    r1, #43947
 ;CHECK: movt    r1, #47787
 ;CHECK: add     r0, r1
@@ -130,21 +130,21 @@ define i32 @t2_const_var2_3_fail_4(i32 %lhs) {
 
 ; var 3 - 0x0F000000
 define i32 @t2_const_var3_1_ok_1(i32 %lhs) {
-;CHECK: t2_const_var3_1_ok_1:
+;CHECK-LABEL: t2_const_var3_1_ok_1:
 ;CHECK: add.w   r0, r0, #251658240
     %ret = add i32 %lhs, 251658240 ; 0x0F000000
     ret i32 %ret
 }
 
 define i32 @t2_const_var3_2_ok_1(i32 %lhs) {
-;CHECK: t2_const_var3_2_ok_1:
+;CHECK-LABEL: t2_const_var3_2_ok_1:
 ;CHECK: add.w   r0, r0, #3948544
     %ret = add i32 %lhs, 3948544 ; 0b00000000001111000100000000000000
     ret i32 %ret
 }
 
 define i32 @t2_const_var3_2_ok_2(i32 %lhs) {
-;CHECK: t2_const_var3_2_ok_2:
+;CHECK-LABEL: t2_const_var3_2_ok_2:
 ;CHECK: add.w   r0, r0, #2097152
 ;CHECK: add.w   r0, r0, #1843200
     %ret = add i32 %lhs, 3940352 ; 0b00000000001111000010000000000000
@@ -152,21 +152,21 @@ define i32 @t2_const_var3_2_ok_2(i32 %lhs) {
 }
 
 define i32 @t2_const_var3_3_ok_1(i32 %lhs) {
-;CHECK: t2_const_var3_3_ok_1:
+;CHECK-LABEL: t2_const_var3_3_ok_1:
 ;CHECK: add.w   r0, r0, #258
     %ret = add i32 %lhs, 258 ; 0b00000000000000000000000100000010
     ret i32 %ret
 }
 
 define i32 @t2_const_var3_4_ok_1(i32 %lhs) {
-;CHECK: t2_const_var3_4_ok_1:
+;CHECK-LABEL: t2_const_var3_4_ok_1:
 ;CHECK: add.w   r0, r0, #-268435456
     %ret = add i32 %lhs, 4026531840 ; 0xF0000000
     ret i32 %ret
 }
 
 define i32 @t2MOVTi16_ok_1(i32 %a) {
-; CHECK: t2MOVTi16_ok_1:
+; CHECK-LABEL: t2MOVTi16_ok_1:
 ; CHECK: movt r0, #1234
     %1 = and i32 %a, 65535
     %2 = shl i32 1234, 16
@@ -176,7 +176,7 @@ define i32 @t2MOVTi16_ok_1(i32 %a) {
 }
 
 define i32 @t2MOVTi16_test_1(i32 %a) {
-; CHECK: t2MOVTi16_test_1:
+; CHECK-LABEL: t2MOVTi16_test_1:
 ; CHECK: movt r0, #1234
     %1 = shl i32  255,   8
     %2 = shl i32 1234,   8
@@ -189,7 +189,7 @@ define i32 @t2MOVTi16_test_1(i32 %a) {
 }
 
 define i32 @t2MOVTi16_test_2(i32 %a) {
-; CHECK: t2MOVTi16_test_2:
+; CHECK-LABEL: t2MOVTi16_test_2:
 ; CHECK: movt r0, #1234
     %1 = shl i32  255,   8
     %2 = shl i32 1234,   8
@@ -203,7 +203,7 @@ define i32 @t2MOVTi16_test_2(i32 %a) {
 }
 
 define i32 @t2MOVTi16_test_3(i32 %a) {
-; CHECK: t2MOVTi16_test_3:
+; CHECK-LABEL: t2MOVTi16_test_3:
 ; CHECK: movt r0, #1234
     %1 = shl i32  255,   8
     %2 = shl i32 1234,   8
@@ -220,7 +220,7 @@ define i32 @t2MOVTi16_test_3(i32 %a) {
 
 ; 171 = 0x000000ab
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: movs r0, #171
     %tmp = add i32 0, 171
     ret i32 %tmp
@@ -228,7 +228,7 @@ define i32 @f1(i32 %a) {
 
 ; 1179666 = 0x00120012
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mov.w r0, #1179666
     %tmp = add i32 0, 1179666
     ret i32 %tmp
@@ -236,7 +236,7 @@ define i32 @f2(i32 %a) {
 
 ; 872428544 = 0x34003400
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov.w r0, #872428544
     %tmp = add i32 0, 872428544
     ret i32 %tmp
@@ -244,7 +244,7 @@ define i32 @f3(i32 %a) {
 
 ; 1448498774 = 0x56565656
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: mov.w r0, #1448498774
     %tmp = add i32 0, 1448498774
     ret i32 %tmp
@@ -252,14 +252,14 @@ define i32 @f4(i32 %a) {
 
 ; 66846720 = 0x03fc0000
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mov.w r0, #66846720
     %tmp = add i32 0, 66846720
     ret i32 %tmp
 }
 
 define i32 @f6(i32 %a) {
-;CHECK: f6
+;CHECK-LABEL: f6:
 ;CHECK: movw    r0, #65535
     %tmp = add i32 0, 65535
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-mul.ll b/test/CodeGen/Thumb2/thumb2-mul.ll
index a8134e6..a989989 100644
--- a/test/CodeGen/Thumb2/thumb2-mul.ll
+++ b/test/CodeGen/Thumb2/thumb2-mul.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b, i32 %c) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: muls r0, r1, r0
     %tmp = mul i32 %a, %b
     ret i32 %tmp
@@ -12,7 +12,7 @@ define i32 @f1(i32 %a, i32 %b, i32 %c) {
 
 define %struct.CMPoint* @t1(i32 %i, i32 %j, i32 %n, %struct.CMPoint* %thePoints) nounwind readnone ssp {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: mla     r0, r2, r0, r1
 ; CHECK: add.w   r0, r0, r0, lsl #3
 ; CHECK: add.w   r0, r3, r0, lsl #2
diff --git a/test/CodeGen/Thumb2/thumb2-mvn.ll b/test/CodeGen/Thumb2/thumb2-mvn.ll
index a8c8f83..a5592f6 100644
--- a/test/CodeGen/Thumb2/thumb2-mvn.ll
+++ b/test/CodeGen/Thumb2/thumb2-mvn.ll
@@ -2,7 +2,7 @@
 
 ; 0x000000bb = 187
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvn r0, #187
     %tmp = xor i32 4294967295, 187
     ret i32 %tmp
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
 
 ; 0x00aa00aa = 11141290
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvn r0, #11141290
     %tmp = xor i32 4294967295, 11141290 
     ret i32 %tmp
@@ -18,7 +18,7 @@ define i32 @f2(i32 %a) {
 
 ; 0xcc00cc00 = 3422604288
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mvn r0, #-872363008
     %tmp = xor i32 4294967295, 3422604288
     ret i32 %tmp
@@ -26,7 +26,7 @@ define i32 @f3(i32 %a) {
 
 ; 0x00110000 = 1114112
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvn r0, #1114112
     %tmp = xor i32 4294967295, 1114112
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-mvn2.ll b/test/CodeGen/Thumb2/thumb2-mvn2.ll
index 375d0aa..bce54a3 100644
--- a/test/CodeGen/Thumb2/thumb2-mvn2.ll
+++ b/test/CodeGen/Thumb2/thumb2-mvn2.ll
@@ -1,21 +1,21 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: mvns r0, r0
     %tmp = xor i32 4294967295, %a
     ret i32 %tmp
 }
 
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: mvns r0, r0
     %tmp = xor i32 %a, 4294967295
     ret i32 %tmp
 }
 
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: mvn.w r0, r0, lsl #5
     %tmp = shl i32 %a, 5
     %tmp1 = xor i32 %tmp, 4294967295
@@ -23,7 +23,7 @@ define i32 @f5(i32 %a) {
 }
 
 define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: mvn.w r0, r0, lsr #6
     %tmp = lshr i32 %a, 6
     %tmp1 = xor i32 %tmp, 4294967295
@@ -31,7 +31,7 @@ define i32 @f6(i32 %a) {
 }
 
 define i32 @f7(i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: mvn.w r0, r0, asr #7
     %tmp = ashr i32 %a, 7
     %tmp1 = xor i32 %tmp, 4294967295
@@ -39,7 +39,7 @@ define i32 @f7(i32 %a) {
 }
 
 define i32 @f8(i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: mvn.w r0, r0, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/thumb2-neg.ll b/test/CodeGen/Thumb2/thumb2-neg.ll
index 6bf11ec..40e8098 100644
--- a/test/CodeGen/Thumb2/thumb2-neg.ll
+++ b/test/CodeGen/Thumb2/thumb2-neg.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: rsbs r0, r0, #0
     %tmp = sub i32 0, %a
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-orn.ll b/test/CodeGen/Thumb2/thumb2-orn.ll
index 97a3fd7..5bbe653 100644
--- a/test/CodeGen/Thumb2/thumb2-orn.ll
+++ b/test/CodeGen/Thumb2/thumb2-orn.ll
@@ -6,7 +6,7 @@ define i32 @f1(i32 %a, i32 %b) {
     %tmp1 = or i32 %a, %tmp
     ret i32 %tmp1
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	orn	r0, r0, r1
 
 define i32 @f2(i32 %a, i32 %b) {
@@ -14,7 +14,7 @@ define i32 @f2(i32 %a, i32 %b) {
     %tmp1 = or i32 %tmp, %a
     ret i32 %tmp1
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	orn	r0, r0, r1
 
 define i32 @f3(i32 %a, i32 %b) {
@@ -22,7 +22,7 @@ define i32 @f3(i32 %a, i32 %b) {
     %tmp1 = or i32 %a, %tmp
     ret i32 %tmp1
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	orn	r0, r0, r1
 
 define i32 @f4(i32 %a, i32 %b) {
@@ -30,7 +30,7 @@ define i32 @f4(i32 %a, i32 %b) {
     %tmp1 = or i32 %tmp, %a
     ret i32 %tmp1
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: 	orn	r0, r0, r1
 
 define i32 @f5(i32 %a, i32 %b) {
@@ -39,7 +39,7 @@ define i32 @f5(i32 %a, i32 %b) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: 	orn	r0, r0, r1, lsl #5
 
 define i32 @f6(i32 %a, i32 %b) {
@@ -48,7 +48,7 @@ define i32 @f6(i32 %a, i32 %b) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: 	orn	r0, r0, r1, lsr #6
 
 define i32 @f7(i32 %a, i32 %b) {
@@ -57,7 +57,7 @@ define i32 @f7(i32 %a, i32 %b) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: 	orn	r0, r0, r1, asr #7
 
 define i32 @f8(i32 %a, i32 %b) {
@@ -68,5 +68,5 @@ define i32 @f8(i32 %a, i32 %b) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: 	orn	r0, r0, r0, ror #8
diff --git a/test/CodeGen/Thumb2/thumb2-orn2.ll b/test/CodeGen/Thumb2/thumb2-orn2.ll
index 34ab3a5..eff3ae3 100644
--- a/test/CodeGen/Thumb2/thumb2-orn2.ll
+++ b/test/CodeGen/Thumb2/thumb2-orn2.ll
@@ -7,7 +7,7 @@ define i32 @f1(i32 %a) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	orn	r0, r0, #187
 
 ; 0x00aa00aa = 11141290
@@ -16,7 +16,7 @@ define i32 @f2(i32 %a) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	orn	r0, r0, #11141290
 
 ; 0xcc00cc00 = 3422604288
@@ -25,7 +25,7 @@ define i32 @f3(i32 %a) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	orn	r0, r0, #-872363008
 
 ; 0x00110000 = 1114112
@@ -34,5 +34,5 @@ define i32 @f5(i32 %a) {
     %tmp2 = or i32 %a, %tmp1
     ret i32 %tmp2
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: 	orn	r0, r0, #1114112
diff --git a/test/CodeGen/Thumb2/thumb2-orr.ll b/test/CodeGen/Thumb2/thumb2-orr.ll
index 89ab7b1..13ed862 100644
--- a/test/CodeGen/Thumb2/thumb2-orr.ll
+++ b/test/CodeGen/Thumb2/thumb2-orr.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: orrs r0, r1
     %tmp2 = or i32 %a, %b
     ret i32 %tmp2
 }
 
 define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: orr.w r0, r0, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp2 = or i32 %a, %tmp
@@ -16,7 +16,7 @@ define i32 @f5(i32 %a, i32 %b) {
 }
 
 define i32 @f6(i32 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: orr.w r0, r0, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp2 = or i32 %a, %tmp
@@ -24,7 +24,7 @@ define i32 @f6(i32 %a, i32 %b) {
 }
 
 define i32 @f7(i32 %a, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: orr.w r0, r0, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp2 = or i32 %a, %tmp
@@ -32,7 +32,7 @@ define i32 @f7(i32 %a, i32 %b) {
 }
 
 define i32 @f8(i32 %a, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: orr.w r0, r0, r0, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/thumb2-orr2.ll b/test/CodeGen/Thumb2/thumb2-orr2.ll
index 8f7a3c2..837bb1c 100644
--- a/test/CodeGen/Thumb2/thumb2-orr2.ll
+++ b/test/CodeGen/Thumb2/thumb2-orr2.ll
@@ -6,7 +6,7 @@ define i32 @f1(i32 %a) {
     %tmp2 = or i32 %a, 187
     ret i32 %tmp2
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	orr	r0, r0, #187
 
 ; 0x00aa00aa = 11141290
@@ -14,7 +14,7 @@ define i32 @f2(i32 %a) {
     %tmp2 = or i32 %a, 11141290 
     ret i32 %tmp2
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	orr	r0, r0, #11141290
 
 ; 0xcc00cc00 = 3422604288
@@ -22,7 +22,7 @@ define i32 @f3(i32 %a) {
     %tmp2 = or i32 %a, 3422604288
     ret i32 %tmp2
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	orr	r0, r0, #-872363008
 
 ; 0x44444444 = 1145324612
@@ -30,7 +30,7 @@ define i32 @f4(i32 %a) {
     %tmp2 = or i32 %a, 1145324612
     ret i32 %tmp2
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: 	orr	r0, r0, #1145324612
 
 ; 0x00110000 = 1114112
@@ -38,5 +38,5 @@ define i32 @f5(i32 %a) {
     %tmp2 = or i32 %a, 1114112
     ret i32 %tmp2
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: 	orr	r0, r0, #1114112
diff --git a/test/CodeGen/Thumb2/thumb2-pack.ll b/test/CodeGen/Thumb2/thumb2-pack.ll
index 2e8bb1d..1052dd2 100644
--- a/test/CodeGen/Thumb2/thumb2-pack.ll
+++ b/test/CodeGen/Thumb2/thumb2-pack.ll
@@ -88,10 +88,33 @@ define i32 @test7(i32 %X, i32 %Y) {
 }
 
 ; CHECK: test8
-; CHECK: pkhtb   r0, r0, r1, asr #22
+; CHECK-NOT: pkhtb   r0, r0, r1, asr #22
+;   pkhtb does an arithmetic shift, not a logical shift. Make sure we don't
+;   use it for problematic cases when whether sign bits would be shifted in
+;   would matter.
 define i32 @test8(i32 %X, i32 %Y) {
 	%tmp1 = and i32 %X, -65536
 	%tmp3 = lshr i32 %Y, 22
 	%tmp57 = or i32 %tmp3, %tmp1
 	ret i32 %tmp57
 }
+
+; CHECK-LABEL: test9:
+; CHECK: pkhtb r0, r0, r1, asr #16
+define i32 @test9(i32 %src1, i32 %src2) {
+entry:
+    %tmp = and i32 %src1, -65536
+    %tmp2 = lshr i32 %src2, 16
+    %tmp3 = or i32 %tmp, %tmp2
+    ret i32 %tmp3
+}
+
+; CHECK: test10
+; CHECK: pkhtb   r0, r0, r1, asr #22
+define i32 @test10(i32 %X, i32 %Y) {
+	%tmp1 = and i32 %X, -65536
+	%tmp3 = ashr i32 %Y, 22
+	%tmp57 = or i32 %tmp3, %tmp1
+	ret i32 %tmp57
+}
+
diff --git a/test/CodeGen/Thumb2/thumb2-rev.ll b/test/CodeGen/Thumb2/thumb2-rev.ll
index b469bbd..67cd623 100644
--- a/test/CodeGen/Thumb2/thumb2-rev.ll
+++ b/test/CodeGen/Thumb2/thumb2-rev.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7,+t2xtpk | FileCheck %s
 
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: rev r0, r0
     %tmp = tail call i32 @llvm.bswap.i32(i32 %a)
     ret i32 %tmp
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
 declare i32 @llvm.bswap.i32(i32) nounwind readnone
 
 define i32 @f2(i32 %X) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: revsh r0, r0
         %tmp1 = lshr i32 %X, 8
         %tmp1.upgrd.1 = trunc i32 %tmp1 to i16
diff --git a/test/CodeGen/Thumb2/thumb2-ror.ll b/test/CodeGen/Thumb2/thumb2-ror.ll
index 5ad92cd..2a218ea 100644
--- a/test/CodeGen/Thumb2/thumb2-ror.ll
+++ b/test/CodeGen/Thumb2/thumb2-ror.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 ; RUN: llc < %s -march=thumb | FileCheck %s -check-prefix=THUMB1
 
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	ror.w	r0, r0, #22
 define i32 @f1(i32 %a) {
     %l8 = shl i32 %a, 10
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
     ret i32 %tmp
 }
 
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NOT: and
 ; CHECK: ror
 ; THUMB1: f2
diff --git a/test/CodeGen/Thumb2/thumb2-rsb.ll b/test/CodeGen/Thumb2/thumb2-rsb.ll
index 15185be..150a25f 100644
--- a/test/CodeGen/Thumb2/thumb2-rsb.ll
+++ b/test/CodeGen/Thumb2/thumb2-rsb.ll
@@ -5,7 +5,7 @@ define i32 @f1(i32 %a, i32 %b) {
     %tmp1 = sub i32 %tmp, %a
     ret i32 %tmp1
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	rsb	r0, r0, r1, lsl #5
 
 define i32 @f2(i32 %a, i32 %b) {
@@ -13,7 +13,7 @@ define i32 @f2(i32 %a, i32 %b) {
     %tmp1 = sub i32 %tmp, %a
     ret i32 %tmp1
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	rsb	r0, r0, r1, lsr #6
 
 define i32 @f3(i32 %a, i32 %b) {
@@ -21,7 +21,7 @@ define i32 @f3(i32 %a, i32 %b) {
     %tmp1 = sub i32 %tmp, %a
     ret i32 %tmp1
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	rsb	r0, r0, r1, asr #7
 
 define i32 @f4(i32 %a, i32 %b) {
@@ -31,5 +31,5 @@ define i32 @f4(i32 %a, i32 %b) {
     %tmp1 = sub i32 %tmp, %a
     ret i32 %tmp1
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: 	rsb	r0, r0, r0, ror #8
diff --git a/test/CodeGen/Thumb2/thumb2-rsb2.ll b/test/CodeGen/Thumb2/thumb2-rsb2.ll
index 61fb619..15aa8af 100644
--- a/test/CodeGen/Thumb2/thumb2-rsb2.ll
+++ b/test/CodeGen/Thumb2/thumb2-rsb2.ll
@@ -5,7 +5,7 @@ define i32 @f1(i32 %a) {
     %tmp = sub i32 171, %a
     ret i32 %tmp
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	rsb.w	r0, r0, #171
 
 ; 1179666 = 0x00120012
@@ -13,7 +13,7 @@ define i32 @f2(i32 %a) {
     %tmp = sub i32 1179666, %a
     ret i32 %tmp
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	rsb.w	r0, r0, #1179666
 
 ; 872428544 = 0x34003400
@@ -21,7 +21,7 @@ define i32 @f3(i32 %a) {
     %tmp = sub i32 872428544, %a
     ret i32 %tmp
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	rsb.w	r0, r0, #872428544
 
 ; 1448498774 = 0x56565656
@@ -29,7 +29,7 @@ define i32 @f4(i32 %a) {
     %tmp = sub i32 1448498774, %a
     ret i32 %tmp
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: 	rsb.w	r0, r0, #1448498774
 
 ; 66846720 = 0x03fc0000
@@ -37,5 +37,5 @@ define i32 @f5(i32 %a) {
     %tmp = sub i32 66846720, %a
     ret i32 %tmp
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: 	rsb.w	r0, r0, #66846720
diff --git a/test/CodeGen/Thumb2/thumb2-sbc.ll b/test/CodeGen/Thumb2/thumb2-sbc.ll
index 492e5f0..0c37984 100644
--- a/test/CodeGen/Thumb2/thumb2-sbc.ll
+++ b/test/CodeGen/Thumb2/thumb2-sbc.ll
@@ -54,7 +54,7 @@ define i64 @f6(i64 %a) {
 
 ; Example from numerics code that manually computes wider-than-64 values.
 ;
-; CHECK: livecarry:
+; CHECK-LABEL: livecarry:
 ; CHECK: adds
 ; CHECK: adc
 define i64 @livecarry(i64 %carry, i32 %digit) nounwind {
diff --git a/test/CodeGen/Thumb2/thumb2-select.ll b/test/CodeGen/Thumb2/thumb2-select.ll
index 2dcf8aa..0feaf95 100644
--- a/test/CodeGen/Thumb2/thumb2-select.ll
+++ b/test/CodeGen/Thumb2/thumb2-select.ll
@@ -2,7 +2,7 @@
 
 define i32 @f1(i32 %a.s) {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: it eq
 ; CHECK: moveq
 
@@ -13,7 +13,7 @@ entry:
 
 define i32 @f2(i32 %a.s) {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: it gt
 ; CHECK: movgt
     %tmp = icmp sgt i32 %a.s, 4
@@ -23,7 +23,7 @@ entry:
 
 define i32 @f3(i32 %a.s, i32 %b.s) {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: it lt
 ; CHECK: movlt
     %tmp = icmp slt i32 %a.s, %b.s
@@ -33,7 +33,7 @@ entry:
 
 define i32 @f4(i32 %a.s, i32 %b.s) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: it le
 ; CHECK: movle
 
@@ -44,7 +44,7 @@ entry:
 
 define i32 @f5(i32 %a.u, i32 %b.u) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: it ls
 ; CHECK: movls
     %tmp = icmp ule i32 %a.u, %b.u
@@ -54,7 +54,7 @@ entry:
 
 define i32 @f6(i32 %a.u, i32 %b.u) {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: it hi
 ; CHECK: movhi
     %tmp = icmp ugt i32 %a.u, %b.u
@@ -64,7 +64,7 @@ entry:
 
 define i32 @f7(i32 %a, i32 %b, i32 %c) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: it hi
 ; CHECK: lsrhi.w
     %tmp1 = icmp ugt i32 %a, %b
@@ -75,7 +75,7 @@ entry:
 
 define i32 @f8(i32 %a, i32 %b, i32 %c) {
 entry:
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: it lo
 ; CHECK: lsllo.w
     %tmp1 = icmp ult i32 %a, %b
@@ -86,7 +86,7 @@ entry:
 
 define i32 @f9(i32 %a, i32 %b, i32 %c) {
 entry:
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: it ge
 ; CHECK: rorge.w
     %tmp1 = icmp sge i32 %a, %b
diff --git a/test/CodeGen/Thumb2/thumb2-spill-q.ll b/test/CodeGen/Thumb2/thumb2-spill-q.ll
index 5bff268..52c1063 100644
--- a/test/CodeGen/Thumb2/thumb2-spill-q.ll
+++ b/test/CodeGen/Thumb2/thumb2-spill-q.ll
@@ -10,7 +10,7 @@
 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
 
 define void @aaa(%quuz* %this, i8* %block) {
-; CHECK: aaa:
+; CHECK-LABEL: aaa:
 ; CHECK: bic r4, r4, #15
 ; CHECK: vst1.64 {{.*}}[{{.*}}:128]
 ; CHECK: vld1.64 {{.*}}[{{.*}}:128]
diff --git a/test/CodeGen/Thumb2/thumb2-str.ll b/test/CodeGen/Thumb2/thumb2-str.ll
index 11bb936..fb5fa16 100644
--- a/test/CodeGen/Thumb2/thumb2-str.ll
+++ b/test/CodeGen/Thumb2/thumb2-str.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32* %v) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: str r0, [r1]
         store i32 %a, i32* %v
         ret i32 %a
 }
 
 define i32 @f2(i32 %a, i32* %v) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: str.w r0, [r1, #4092]
         %tmp2 = getelementptr i32* %v, i32 1023
         store i32 %a, i32* %tmp2
@@ -16,7 +16,7 @@ define i32 @f2(i32 %a, i32* %v) {
 }
 
 define i32 @f2a(i32 %a, i32* %v) {
-; CHECK: f2a:
+; CHECK-LABEL: f2a:
 ; CHECK: str r0, [r1, #-128]
         %tmp2 = getelementptr i32* %v, i32 -32
         store i32 %a, i32* %tmp2
@@ -24,7 +24,7 @@ define i32 @f2a(i32 %a, i32* %v) {
 }
 
 define i32 @f3(i32 %a, i32* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov.w r2, #4096
 ; CHECK: str r0, [r1, r2]
         %tmp2 = getelementptr i32* %v, i32 1024
@@ -34,7 +34,7 @@ define i32 @f3(i32 %a, i32* %v) {
 
 define i32 @f4(i32 %a, i32 %base) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: str r0, [r1, #-128]
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i32*
@@ -44,7 +44,7 @@ entry:
 
 define i32 @f5(i32 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: str r0, [r1, r2]
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i32*
@@ -54,7 +54,7 @@ entry:
 
 define i32 @f6(i32 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: str.w r0, [r1, r2, lsl #2]
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
@@ -65,7 +65,7 @@ entry:
 
 define i32 @f7(i32 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lsrs r2, r2, #2
 ; CHECK: str r0, [r1, r2]
         %tmp1 = lshr i32 %offset, 2
diff --git a/test/CodeGen/Thumb2/thumb2-str_post.ll b/test/CodeGen/Thumb2/thumb2-str_post.ll
index bbfb447..2133d28 100644
--- a/test/CodeGen/Thumb2/thumb2-str_post.ll
+++ b/test/CodeGen/Thumb2/thumb2-str_post.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i16 @test1(i32* %X, i16* %A) {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: strh {{.*}}[{{.*}}], #-4
         %Y = load i32* %X               ; <i32> [#uses=1]
         %tmp1 = trunc i32 %Y to i16             ; <i16> [#uses=1]
@@ -12,7 +12,7 @@ define i16 @test1(i32* %X, i16* %A) {
 }
 
 define i32 @test2(i32* %X, i32* %A) {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: str {{.*}}[{{.*}}],
         %Y = load i32* %X               ; <i32> [#uses=1]
         store i32 %Y, i32* %A
diff --git a/test/CodeGen/Thumb2/thumb2-strb.ll b/test/CodeGen/Thumb2/thumb2-strb.ll
index 7978e7f..cc39b7d 100644
--- a/test/CodeGen/Thumb2/thumb2-strb.ll
+++ b/test/CodeGen/Thumb2/thumb2-strb.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i8 @f1(i8 %a, i8* %v) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: strb r0, [r1]
         store i8 %a, i8* %v
         ret i8 %a
 }
 
 define i8 @f2(i8 %a, i8* %v) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: strb.w r0, [r1, #4092]
         %tmp2 = getelementptr i8* %v, i32 4092
         store i8 %a, i8* %tmp2
@@ -16,7 +16,7 @@ define i8 @f2(i8 %a, i8* %v) {
 }
 
 define i8 @f2a(i8 %a, i8* %v) {
-; CHECK: f2a:
+; CHECK-LABEL: f2a:
 ; CHECK: strb r0, [r1, #-128]
         %tmp2 = getelementptr i8* %v, i32 -128
         store i8 %a, i8* %tmp2
@@ -24,7 +24,7 @@ define i8 @f2a(i8 %a, i8* %v) {
 }
 
 define i8 @f3(i8 %a, i8* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov.w r2, #4096
 ; CHECK: strb r0, [r1, r2]
         %tmp2 = getelementptr i8* %v, i32 4096
@@ -34,7 +34,7 @@ define i8 @f3(i8 %a, i8* %v) {
 
 define i8 @f4(i8 %a, i32 %base) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: strb r0, [r1, #-128]
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i8*
@@ -44,7 +44,7 @@ entry:
 
 define i8 @f5(i8 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: strb r0, [r1, r2]
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i8*
@@ -54,7 +54,7 @@ entry:
 
 define i8 @f6(i8 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: strb.w r0, [r1, r2, lsl #2]
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
@@ -65,7 +65,7 @@ entry:
 
 define i8 @f7(i8 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lsrs r2, r2, #2
 ; CHECK: strb r0, [r1, r2]
         %tmp1 = lshr i32 %offset, 2
diff --git a/test/CodeGen/Thumb2/thumb2-strh.ll b/test/CodeGen/Thumb2/thumb2-strh.ll
index 97110a72..d686938 100644
--- a/test/CodeGen/Thumb2/thumb2-strh.ll
+++ b/test/CodeGen/Thumb2/thumb2-strh.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i16 @f1(i16 %a, i16* %v) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: strh r0, [r1]
         store i16 %a, i16* %v
         ret i16 %a
 }
 
 define i16 @f2(i16 %a, i16* %v) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: strh.w r0, [r1, #4092]
         %tmp2 = getelementptr i16* %v, i32 2046
         store i16 %a, i16* %tmp2
@@ -16,7 +16,7 @@ define i16 @f2(i16 %a, i16* %v) {
 }
 
 define i16 @f2a(i16 %a, i16* %v) {
-; CHECK: f2a:
+; CHECK-LABEL: f2a:
 ; CHECK: strh r0, [r1, #-128]
         %tmp2 = getelementptr i16* %v, i32 -64
         store i16 %a, i16* %tmp2
@@ -24,7 +24,7 @@ define i16 @f2a(i16 %a, i16* %v) {
 }
 
 define i16 @f3(i16 %a, i16* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: mov.w r2, #4096
 ; CHECK: strh r0, [r1, r2]
         %tmp2 = getelementptr i16* %v, i32 2048
@@ -34,7 +34,7 @@ define i16 @f3(i16 %a, i16* %v) {
 
 define i16 @f4(i16 %a, i32 %base) {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: strh r0, [r1, #-128]
         %tmp1 = sub i32 %base, 128
         %tmp2 = inttoptr i32 %tmp1 to i16*
@@ -44,7 +44,7 @@ entry:
 
 define i16 @f5(i16 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: strh r0, [r1, r2]
         %tmp1 = add i32 %base, %offset
         %tmp2 = inttoptr i32 %tmp1 to i16*
@@ -54,7 +54,7 @@ entry:
 
 define i16 @f6(i16 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: strh.w r0, [r1, r2, lsl #2]
         %tmp1 = shl i32 %offset, 2
         %tmp2 = add i32 %base, %tmp1
@@ -65,7 +65,7 @@ entry:
 
 define i16 @f7(i16 %a, i32 %base, i32 %offset) {
 entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: lsrs r2, r2, #2
 ; CHECK: strh r0, [r1, r2]
         %tmp1 = lshr i32 %offset, 2
diff --git a/test/CodeGen/Thumb2/thumb2-sub.ll b/test/CodeGen/Thumb2/thumb2-sub.ll
index 95335a2..f83dfe2 100644
--- a/test/CodeGen/Thumb2/thumb2-sub.ll
+++ b/test/CodeGen/Thumb2/thumb2-sub.ll
@@ -2,7 +2,7 @@
 
 ; 171 = 0x000000ab
 define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: subs r0, #171
     %tmp = sub i32 %a, 171
     ret i32 %tmp
@@ -10,7 +10,7 @@ define i32 @f1(i32 %a) {
 
 ; 1179666 = 0x00120012
 define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sub.w r0, r0, #1179666
     %tmp = sub i32 %a, 1179666
     ret i32 %tmp
@@ -18,7 +18,7 @@ define i32 @f2(i32 %a) {
 
 ; 872428544 = 0x34003400
 define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sub.w r0, r0, #872428544
     %tmp = sub i32 %a, 872428544
     ret i32 %tmp
@@ -26,7 +26,7 @@ define i32 @f3(i32 %a) {
 
 ; 1448498774 = 0x56565656
 define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sub.w r0, r0, #1448498774
     %tmp = sub i32 %a, 1448498774
     ret i32 %tmp
@@ -34,7 +34,7 @@ define i32 @f4(i32 %a) {
 
 ; 510 = 0x000001fe
 define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sub.w r0, r0, #510
     %tmp = sub i32 %a, 510
     ret i32 %tmp
@@ -42,7 +42,7 @@ define i32 @f5(i32 %a) {
 
 ; Don't change this to an add.
 define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: subs r0, #1
     %tmp = sub i32 %a, 1
     ret i32 %tmp
diff --git a/test/CodeGen/Thumb2/thumb2-sub2.ll b/test/CodeGen/Thumb2/thumb2-sub2.ll
index bb99cbd..47eb1e1 100644
--- a/test/CodeGen/Thumb2/thumb2-sub2.ll
+++ b/test/CodeGen/Thumb2/thumb2-sub2.ll
@@ -4,5 +4,5 @@ define i32 @f1(i32 %a) {
     %tmp = sub i32 %a, 4095
     ret i32 %tmp
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: 	subw	r0, r0, #4095
diff --git a/test/CodeGen/Thumb2/thumb2-sub4.ll b/test/CodeGen/Thumb2/thumb2-sub4.ll
index a040d17..ff1441a 100644
--- a/test/CodeGen/Thumb2/thumb2-sub4.ll
+++ b/test/CodeGen/Thumb2/thumb2-sub4.ll
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: subs r0, r0, r1
     %tmp = sub i32 %a, %b
     ret i32 %tmp
 }
 
 define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: sub.w r0, r0, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp1 = sub i32 %a, %tmp
@@ -16,7 +16,7 @@ define i32 @f2(i32 %a, i32 %b) {
 }
 
 define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: sub.w r0, r0, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp1 = sub i32 %a, %tmp
@@ -24,7 +24,7 @@ define i32 @f3(i32 %a, i32 %b) {
 }
 
 define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: sub.w r0, r0, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp1 = sub i32 %a, %tmp
@@ -32,7 +32,7 @@ define i32 @f4(i32 %a, i32 %b) {
 }
 
 define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: sub.w r0, r0, r0, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/thumb2-sub5.ll b/test/CodeGen/Thumb2/thumb2-sub5.ll
index 6edd789..5941dd6 100644
--- a/test/CodeGen/Thumb2/thumb2-sub5.ll
+++ b/test/CodeGen/Thumb2/thumb2-sub5.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 -mattr=+32bit | FileCheck %s
 
 define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: subs.w r0, r0, r2
 ; To test dead_carry, +32bit prevents sbc conveting to 16-bit sbcs
 ; CHECK: sbc.w  r1, r1, r3
diff --git a/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll b/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll
index ab888e6..792ebef 100644
--- a/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll
+++ b/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll
@@ -1,28 +1,28 @@
 ; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s
 
 define i32 @test1(i16 zeroext %z) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: sxth
   %r = sext i16 %z to i32
   ret i32 %r
 }
 
 define i32 @test2(i8 zeroext %z) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: sxtb
   %r = sext i8 %z to i32
   ret i32 %r
 }
 
 define i32 @test3(i16 signext %z) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: uxth
   %r = zext i16 %z to i32
   ret i32 %r
 }
 
 define i32 @test4(i8 signext %z) nounwind {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: uxtb
   %r = zext i8 %z to i32
   ret i32 %r
diff --git a/test/CodeGen/Thumb2/thumb2-tbb.ll b/test/CodeGen/Thumb2/thumb2-tbb.ll
index a9d71d6..d57638b 100644
--- a/test/CodeGen/Thumb2/thumb2-tbb.ll
+++ b/test/CodeGen/Thumb2/thumb2-tbb.ll
@@ -3,7 +3,7 @@
 
 define void @bar(i32 %n.u) {
 entry:
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: tbb
 ; CHECK: .data_region jt8
 ; CHECK: .end_data_region
diff --git a/test/CodeGen/Thumb2/thumb2-tbh.ll b/test/CodeGen/Thumb2/thumb2-tbh.ll
index cd9c8e1..bf1c7c6 100644
--- a/test/CodeGen/Thumb2/thumb2-tbh.ll
+++ b/test/CodeGen/Thumb2/thumb2-tbh.ll
@@ -15,7 +15,7 @@ declare void @Z_fatal(i8*) noreturn nounwind
 declare noalias i8* @calloc(i32, i32) nounwind
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK: tbb
 entry:
 	br label %bb42.i
diff --git a/test/CodeGen/Thumb2/thumb2-teq.ll b/test/CodeGen/Thumb2/thumb2-teq.ll
index d453f46..5acda35 100644
--- a/test/CodeGen/Thumb2/thumb2-teq.ll
+++ b/test/CodeGen/Thumb2/thumb2-teq.ll
@@ -9,7 +9,7 @@ define i1 @f2(i32 %a) {
     %tmp1 = icmp eq i32 0, %tmp
     ret i1 %tmp1
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	teq.w	{{.*}}, #187
 
 ; 0x00aa00aa = 11141290
@@ -18,7 +18,7 @@ define i1 @f3(i32 %a) {
     %tmp1 = icmp eq i32 %tmp, 0
     ret i1 %tmp1
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	teq.w	{{.*}}, #11141290
 
 ; 0xcc00cc00 = 3422604288
@@ -27,7 +27,7 @@ define i1 @f6(i32 %a) {
     %tmp1 = icmp eq i32 0, %tmp
     ret i1 %tmp1
 }
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: 	teq.w	{{.*}}, #-872363008
 
 ; 0xdddddddd = 3722304989
@@ -36,7 +36,7 @@ define i1 @f7(i32 %a) {
     %tmp1 = icmp eq i32 %tmp, 0
     ret i1 %tmp1
 }
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: 	teq.w	{{.*}}, #-572662307
 
 ; 0xdddddddd = 3722304989
@@ -52,6 +52,6 @@ define i1 @f10(i32 %a) {
     %tmp1 = icmp eq i32 0, %tmp
     ret i1 %tmp1
 }
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: 	teq.w	{{.*}}, #1114112
 
diff --git a/test/CodeGen/Thumb2/thumb2-tst.ll b/test/CodeGen/Thumb2/thumb2-tst.ll
index 67fe82e..31eafea 100644
--- a/test/CodeGen/Thumb2/thumb2-tst.ll
+++ b/test/CodeGen/Thumb2/thumb2-tst.ll
@@ -9,7 +9,7 @@ define i1 @f2(i32 %a) {
     %tmp1 = icmp eq i32 0, %tmp
     ret i1 %tmp1
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: 	tst.w	{{.*}}, #187
 
 ; 0x00aa00aa = 11141290
@@ -18,7 +18,7 @@ define i1 @f3(i32 %a) {
     %tmp1 = icmp eq i32 %tmp, 0
     ret i1 %tmp1
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: 	tst.w	{{.*}}, #11141290
 
 ; 0xcc00cc00 = 3422604288
@@ -27,7 +27,7 @@ define i1 @f6(i32 %a) {
     %tmp1 = icmp eq i32 0, %tmp
     ret i1 %tmp1
 }
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: 	tst.w	{{.*}}, #-872363008
 
 ; 0xdddddddd = 3722304989
@@ -36,7 +36,7 @@ define i1 @f7(i32 %a) {
     %tmp1 = icmp eq i32 %tmp, 0
     ret i1 %tmp1
 }
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: 	tst.w	{{.*}}, #-572662307
 
 ; 0x00110000 = 1114112
@@ -45,5 +45,5 @@ define i1 @f10(i32 %a) {
     %tmp1 = icmp eq i32 0, %tmp
     ret i1 %tmp1
 }
-; CHECK: f10:
+; CHECK-LABEL: f10:
 ; CHECK: 	tst.w	{{.*}}, #1114112
diff --git a/test/CodeGen/Thumb2/thumb2-tst2.ll b/test/CodeGen/Thumb2/thumb2-tst2.ll
index e3fe792..f71e91d 100644
--- a/test/CodeGen/Thumb2/thumb2-tst2.ll
+++ b/test/CodeGen/Thumb2/thumb2-tst2.ll
@@ -4,7 +4,7 @@
 ; tst as 'mov.w r0, #0'.
 
 define i1 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: tst {{.*}}, r1
     %tmp = and i32 %a, %b
     %tmp1 = icmp eq i32 %tmp, 0
@@ -12,7 +12,7 @@ define i1 @f2(i32 %a, i32 %b) {
 }
 
 define i1 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: tst {{.*}}, r1
     %tmp = and i32 %a, %b
     %tmp1 = icmp eq i32 0, %tmp
@@ -20,7 +20,7 @@ define i1 @f4(i32 %a, i32 %b) {
 }
 
 define i1 @f6(i32 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
 ; CHECK: tst.w {{.*}}, r1, lsl #5
     %tmp = shl i32 %b, 5
     %tmp1 = and i32 %a, %tmp
@@ -29,7 +29,7 @@ define i1 @f6(i32 %a, i32 %b) {
 }
 
 define i1 @f7(i32 %a, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
 ; CHECK: tst.w {{.*}}, r1, lsr #6
     %tmp = lshr i32 %b, 6
     %tmp1 = and i32 %a, %tmp
@@ -38,7 +38,7 @@ define i1 @f7(i32 %a, i32 %b) {
 }
 
 define i1 @f8(i32 %a, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
 ; CHECK: tst.w {{.*}}, r1, asr #7
     %tmp = ashr i32 %b, 7
     %tmp1 = and i32 %a, %tmp
@@ -47,7 +47,7 @@ define i1 @f8(i32 %a, i32 %b) {
 }
 
 define i1 @f9(i32 %a, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
 ; CHECK: tst.w {{.*}}, {{.*}}, ror #8
     %l8 = shl i32 %a, 24
     %r8 = lshr i32 %a, 8
diff --git a/test/CodeGen/Thumb2/tls2.ll b/test/CodeGen/Thumb2/tls2.ll
index b8a0657..6cb019f 100644
--- a/test/CodeGen/Thumb2/tls2.ll
+++ b/test/CodeGen/Thumb2/tls2.ll
@@ -5,12 +5,12 @@
 
 define i32 @f() {
 entry:
-; CHECK-NOT-PIC: f:
+; CHECK-NOT-PIC-LABEL: f:
 ; CHECK-NOT-PIC: add r0, pc
 ; CHECK-NOT-PIC: ldr r1, [r0]
 ; CHECK-NOT-PIC: i(gottpoff)
 
-; CHECK-PIC: f:
+; CHECK-PIC-LABEL: f:
 ; CHECK-PIC: bl __tls_get_addr(PLT)
 	%tmp1 = load i32* @i		; <i32> [#uses=1]
 	ret i32 %tmp1
@@ -18,12 +18,12 @@ entry:
 
 define i32* @g() {
 entry:
-; CHECK-NOT-PIC: g:
+; CHECK-NOT-PIC-LABEL: g:
 ; CHECK-NOT-PIC: add r0, pc
 ; CHECK-NOT-PIC: ldr r1, [r0]
 ; CHECK-NOT-PIC: i(gottpoff)
 
-; CHECK-PIC: g:
+; CHECK-PIC-LABEL: g:
 ; CHECK-PIC: bl __tls_get_addr(PLT)
 	ret i32* @i
 }
diff --git a/test/CodeGen/X86/2006-05-11-InstrSched.ll b/test/CodeGen/X86/2006-05-11-InstrSched.ll
index 6912351..3d09466 100644
--- a/test/CodeGen/X86/2006-05-11-InstrSched.ll
+++ b/test/CodeGen/X86/2006-05-11-InstrSched.ll
@@ -1,5 +1,5 @@
 ; REQUIRES: asserts
-; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mcpu=penryn -mattr=+sse2 -stats -realign-stack=0 2>&1 | \
+; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mcpu=penryn -mattr=+sse2 -stats 2>&1 | \
 ; RUN:     grep "asm-printer" | grep 35
 
 target datalayout = "e-p:32:32"
diff --git a/test/CodeGen/X86/2006-11-12-CSRetCC.ll b/test/CodeGen/X86/2006-11-12-CSRetCC.ll
index a58c9b1..d7af1c3 100644
--- a/test/CodeGen/X86/2006-11-12-CSRetCC.ll
+++ b/test/CodeGen/X86/2006-11-12-CSRetCC.ll
@@ -4,7 +4,7 @@ target triple = "i686-pc-linux-gnu"
 @str = internal constant [9 x i8] c"%f+%f*i\0A\00"              ; <[9 x i8]*> [#uses=1]
 
 define i32 @main() {
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK-NOT: ret
 ; CHECK: subl $4, %{{.*}}
 ; CHECK: ret
diff --git a/test/CodeGen/X86/2007-02-04-OrAddrMode.ll b/test/CodeGen/X86/2007-02-04-OrAddrMode.ll
index b0eb1c5..cea4d9d 100644
--- a/test/CodeGen/X86/2007-02-04-OrAddrMode.ll
+++ b/test/CodeGen/X86/2007-02-04-OrAddrMode.ll
@@ -2,7 +2,7 @@
 
 ;; This example can't fold the or into an LEA.
 define i32 @test(float ** %tmp2, i32 %tmp12) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: ret
 ; CHECK: orl $1, %{{.*}}
 ; CHECK: ret
@@ -18,7 +18,7 @@ define i32 @test(float ** %tmp2, i32 %tmp12) nounwind {
 
 ;; This can!
 define i32 @test2(i32 %a, i32 %b) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK-NOT: ret
 ; CHECK: leal 3(,%{{.*}},8)
 ; CHECK: ret
diff --git a/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll b/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll
index b48ce84..cbc1bc4 100644
--- a/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll
+++ b/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=x86 | FileCheck %s
 
 define i32 @test(i1 %X) {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: ret
 ; CHECK: movl $1, %eax
 ; CHECK: ret
diff --git a/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll b/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
index e2cd750..3e1786b 100644
--- a/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
+++ b/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:32:32"
 target triple = "i686-apple-darwin9"
 
 define void @test() {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: ret
 ; CHECK: psrlw $8, %xmm0
 ; CHECK: ret
diff --git a/test/CodeGen/X86/2007-05-07-InvokeSRet.ll b/test/CodeGen/X86/2007-05-07-InvokeSRet.ll
deleted file mode 100644
index c3d7e8a..0000000
--- a/test/CodeGen/X86/2007-05-07-InvokeSRet.ll
+++ /dev/null
@@ -1,19 +0,0 @@
-; RUN: llc < %s -mtriple=i686-pc-linux-gnu -disable-fp-elim | not grep "addl .12, %esp"
-; PR1398
-
-	%struct.S = type { i32, i32 }
-
-declare void @invokee(%struct.S* sret )
-
-define void @invoker(%struct.S* %name.0.0) {
-entry:
-	invoke void @invokee( %struct.S* sret %name.0.0   )
-			to label %return unwind label %return
-
-return:		; preds = %entry, %entry
-        %exn = landingpad {i8*, i32} personality i32 (...)* @__gxx_personality_v0
-                 cleanup
-	ret void
-}
-
-declare i32 @__gxx_personality_v0(...)
diff --git a/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll b/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
index f7ffb93..88057c8 100644
--- a/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
+++ b/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll
@@ -7,7 +7,7 @@ entry:
 	%tmp2 = call x86_fp80 @llvm.sqrt.f80( x86_fp80 %x )
 	ret x86_fp80 %tmp2
         
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: fldt 4(%esp)
 ; CHECK-NEXT: fsqrt
 ; CHECK-NEXT: ret
@@ -19,7 +19,7 @@ define x86_fp80 @bar(x86_fp80 %x) nounwind {
 entry:
 	%tmp2 = call x86_fp80 @llvm.powi.f80( x86_fp80 %x, i32 3 )
 	ret x86_fp80 %tmp2
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: fldt 4(%esp)
 ; CHECK-NEXT: fld	%st(0)
 ; CHECK-NEXT: fmul	%st(1)
diff --git a/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll b/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
index 8091bd1..d3a47ae 100644
--- a/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
+++ b/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll
@@ -7,8 +7,10 @@ entry:
 cond_next127:		; preds = %cond_next391, %entry
 	%v.1 = phi i32 [ undef, %entry ], [ %tmp411, %cond_next391 ]		; <i32> [#uses=1]
 	%tmp149 = mul i32 0, %v.1		; <i32> [#uses=0]
-	%tmp254 = and i32 0, 15		; <i32> [#uses=1]
-	%tmp256 = and i32 0, 15		; <i32> [#uses=2]
+	%tmpss = load i32* %ss, align 4		; <i32> [#uses=1]
+	%tmpbp = load i32* %bp, align 4		; <i32> [#uses=2]
+	%tmp254 = and i32 %tmpss, 15		; <i32> [#uses=1]
+	%tmp256 = and i32 %tmpbp, 15		; <i32> [#uses=2]
 	br label %cond_next391
 
 cond_next391:		; preds = %cond_next127
diff --git a/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll b/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll
index 39af931..9b9b781 100644
--- a/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll
+++ b/test/CodeGen/X86/2008-01-08-SchedulerCrash.ll
@@ -19,7 +19,7 @@ bb917:		; preds = %entry
 	ret i32 0
 
 bb951:		; preds = %bb986, %entry
-	%tmp955 = sdiv i32 0, 2		; <i32> [#uses=3]
+	%tmp955 = sdiv i32 %offset, 2		; <i32> [#uses=3]
 	%tmp961 = getelementptr %struct.indexentry* null, i32 %tmp955, i32 0		; <i32*> [#uses=1]
 	br i1 %cond, label %bb986, label %bb967
 
diff --git a/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll b/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll
deleted file mode 100644
index b772d77..0000000
--- a/test/CodeGen/X86/2008-02-08-LoadFoldingBug.ll
+++ /dev/null
@@ -1,99 +0,0 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 | grep andpd | not grep esp
-
-declare double @llvm.sqrt.f64(double) nounwind readnone 
-
-declare fastcc void @ApplyGivens(double**, double, double, i32, i32, i32, i32) nounwind 
-
-declare double @fabs(double)
-
-define void @main_bb114_2E_outer_2E_i_bb3_2E_i27(double** %tmp12.sub.i.i, [51 x double*]* %tmp12.i.i.i, i32 %i.0.reg2mem.0.ph.i, i32 %tmp11688.i, i32 %tmp19.i, i32 %tmp24.i, [51 x double*]* %tmp12.i.i) {
-newFuncRoot:
-	br label %bb3.i27
-
-bb111.i77.bb121.i_crit_edge.exitStub:		; preds = %bb111.i77
-	ret void
-
-bb3.i27:		; preds = %bb111.i77.bb3.i27_crit_edge, %newFuncRoot
-	%indvar94.i = phi i32 [ 0, %newFuncRoot ], [ %tmp113.i76, %bb111.i77.bb3.i27_crit_edge ]		; <i32> [#uses=6]
-	%tmp6.i20 = getelementptr [51 x double*]* %tmp12.i.i, i32 0, i32 %indvar94.i		; <double**> [#uses=1]
-	%tmp7.i21 = load double** %tmp6.i20, align 4		; <double*> [#uses=2]
-	%tmp10.i = add i32 %indvar94.i, %i.0.reg2mem.0.ph.i		; <i32> [#uses=5]
-	%tmp11.i22 = getelementptr double* %tmp7.i21, i32 %tmp10.i		; <double*> [#uses=1]
-	%tmp12.i23 = load double* %tmp11.i22, align 8		; <double> [#uses=4]
-	%tmp20.i24 = add i32 %tmp19.i, %indvar94.i		; <i32> [#uses=3]
-	%tmp21.i = getelementptr double* %tmp7.i21, i32 %tmp20.i24		; <double*> [#uses=1]
-	%tmp22.i25 = load double* %tmp21.i, align 8		; <double> [#uses=3]
-	%tmp1.i.i26 = fcmp oeq double %tmp12.i23, 0.000000e+00		; <i1> [#uses=1]
-	br i1 %tmp1.i.i26, label %bb3.i27.Givens.exit.i49_crit_edge, label %bb5.i.i31
-
-bb5.i.i31:		; preds = %bb3.i27
-	%tmp7.i.i28 = call double @fabs( double %tmp12.i23 ) nounwind 		; <double> [#uses=1]
-	%tmp9.i.i29 = call double @fabs( double %tmp22.i25 ) nounwind 		; <double> [#uses=1]
-	%tmp10.i.i30 = fcmp ogt double %tmp7.i.i28, %tmp9.i.i29		; <i1> [#uses=1]
-	br i1 %tmp10.i.i30, label %bb13.i.i37, label %bb30.i.i43
-
-bb13.i.i37:		; preds = %bb5.i.i31
-	%tmp15.i.i32 = fsub double -0.000000e+00, %tmp22.i25		; <double> [#uses=1]
-	%tmp17.i.i33 = fdiv double %tmp15.i.i32, %tmp12.i23		; <double> [#uses=3]
-	%tmp20.i4.i = fmul double %tmp17.i.i33, %tmp17.i.i33		; <double> [#uses=1]
-	%tmp21.i.i34 = fadd double %tmp20.i4.i, 1.000000e+00		; <double> [#uses=1]
-	%tmp22.i.i35 = call double @llvm.sqrt.f64( double %tmp21.i.i34 ) nounwind 		; <double> [#uses=1]
-	%tmp23.i5.i = fdiv double 1.000000e+00, %tmp22.i.i35		; <double> [#uses=2]
-	%tmp28.i.i36 = fmul double %tmp23.i5.i, %tmp17.i.i33		; <double> [#uses=1]
-	br label %Givens.exit.i49
-
-bb30.i.i43:		; preds = %bb5.i.i31
-	%tmp32.i.i38 = fsub double -0.000000e+00, %tmp12.i23		; <double> [#uses=1]
-	%tmp34.i.i39 = fdiv double %tmp32.i.i38, %tmp22.i25		; <double> [#uses=3]
-	%tmp37.i6.i = fmul double %tmp34.i.i39, %tmp34.i.i39		; <double> [#uses=1]
-	%tmp38.i.i40 = fadd double %tmp37.i6.i, 1.000000e+00		; <double> [#uses=1]
-	%tmp39.i7.i = call double @llvm.sqrt.f64( double %tmp38.i.i40 ) nounwind 		; <double> [#uses=1]
-	%tmp40.i.i41 = fdiv double 1.000000e+00, %tmp39.i7.i		; <double> [#uses=2]
-	%tmp45.i.i42 = fmul double %tmp40.i.i41, %tmp34.i.i39		; <double> [#uses=1]
-	br label %Givens.exit.i49
-
-Givens.exit.i49:		; preds = %bb3.i27.Givens.exit.i49_crit_edge, %bb30.i.i43, %bb13.i.i37
-	%s.0.i44 = phi double [ %tmp45.i.i42, %bb30.i.i43 ], [ %tmp23.i5.i, %bb13.i.i37 ], [ 0.000000e+00, %bb3.i27.Givens.exit.i49_crit_edge ]		; <double> [#uses=2]
-	%c.0.i45 = phi double [ %tmp40.i.i41, %bb30.i.i43 ], [ %tmp28.i.i36, %bb13.i.i37 ], [ 1.000000e+00, %bb3.i27.Givens.exit.i49_crit_edge ]		; <double> [#uses=2]
-	%tmp26.i46 = add i32 %tmp24.i, %indvar94.i		; <i32> [#uses=2]
-	%tmp27.i47 = icmp slt i32 %tmp26.i46, 51		; <i1> [#uses=1]
-	%min.i48 = select i1 %tmp27.i47, i32 %tmp26.i46, i32 50		; <i32> [#uses=1]
-	call fastcc void @ApplyGivens( double** %tmp12.sub.i.i, double %s.0.i44, double %c.0.i45, i32 %tmp20.i24, i32 %tmp10.i, i32 %indvar94.i, i32 %min.i48 ) nounwind 
-	br label %codeRepl
-
-codeRepl:		; preds = %Givens.exit.i49
-	call void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb_2E_i48_2E_i( i32 %tmp10.i, i32 %tmp20.i24, double %s.0.i44, double %c.0.i45, [51 x double*]* %tmp12.i.i.i )
-	br label %ApplyRGivens.exit49.i
-
-ApplyRGivens.exit49.i:		; preds = %codeRepl
-	%tmp10986.i = icmp sgt i32 %tmp11688.i, %tmp10.i		; <i1> [#uses=1]
-	br i1 %tmp10986.i, label %ApplyRGivens.exit49.i.bb52.i57_crit_edge, label %ApplyRGivens.exit49.i.bb111.i77_crit_edge
-
-codeRepl1:		; preds = %ApplyRGivens.exit49.i.bb52.i57_crit_edge
-	call void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb52_2E_i57( i32 %tmp10.i, double** %tmp12.sub.i.i, [51 x double*]* %tmp12.i.i.i, i32 %i.0.reg2mem.0.ph.i, i32 %tmp11688.i, i32 %tmp19.i, i32 %tmp24.i, [51 x double*]* %tmp12.i.i )
-	br label %bb105.i.bb111.i77_crit_edge
-
-bb111.i77:		; preds = %bb105.i.bb111.i77_crit_edge, %ApplyRGivens.exit49.i.bb111.i77_crit_edge
-	%tmp113.i76 = add i32 %indvar94.i, 1		; <i32> [#uses=2]
-	%tmp118.i = icmp sgt i32 %tmp11688.i, %tmp113.i76		; <i1> [#uses=1]
-	br i1 %tmp118.i, label %bb111.i77.bb3.i27_crit_edge, label %bb111.i77.bb121.i_crit_edge.exitStub
-
-bb3.i27.Givens.exit.i49_crit_edge:		; preds = %bb3.i27
-	br label %Givens.exit.i49
-
-ApplyRGivens.exit49.i.bb52.i57_crit_edge:		; preds = %ApplyRGivens.exit49.i
-	br label %codeRepl1
-
-ApplyRGivens.exit49.i.bb111.i77_crit_edge:		; preds = %ApplyRGivens.exit49.i
-	br label %bb111.i77
-
-bb105.i.bb111.i77_crit_edge:		; preds = %codeRepl1
-	br label %bb111.i77
-
-bb111.i77.bb3.i27_crit_edge:		; preds = %bb111.i77
-	br label %bb3.i27
-}
-
-declare void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb_2E_i48_2E_i(i32, i32, double, double, [51 x double*]*)
-
-declare void @main_bb114_2E_outer_2E_i_bb3_2E_i27_bb52_2E_i57(i32, double**, [51 x double*]*, i32, i32, i32, i32, [51 x double*]*)
diff --git a/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll b/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll
index 6e9a629..d4805b4 100644
--- a/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll
+++ b/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 target triple = "i386-apple-darwin8"
 
 define void @test() nounwind  {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: ret
 ; CHECK: 1 $2 3
 ; CHECK: ret
diff --git a/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll b/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll
index fc38135..da56ce7 100644
--- a/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll
+++ b/test/CodeGen/X86/2008-05-22-FoldUnalignedLoad.ll
@@ -8,7 +8,7 @@ entry:
         ret void
 }
 
-; CHECK: a:
+; CHECK-LABEL: a:
 ; CHECK: movups
 ; CHECK: movups
 ; CHECK-NOT: movups
diff --git a/test/CodeGen/X86/2008-07-19-movups-spills.ll b/test/CodeGen/X86/2008-07-19-movups-spills.ll
index 368af6d..cd86ee1 100644
--- a/test/CodeGen/X86/2008-07-19-movups-spills.ll
+++ b/test/CodeGen/X86/2008-07-19-movups-spills.ll
@@ -1,5 +1,4 @@
-; RUN: llc < %s -mtriple=i686-pc-linux -realign-stack=1 -mattr=sse2 | grep movups | count 33
-; RUN: llc < %s -mtriple=i686-pc-linux -realign-stack=0 -mattr=sse2 | grep movups | count 33
+; RUN: llc < %s -mtriple=i686-pc-linux -mattr=sse2 | FileCheck %s
 ; PR2539
 ; PR8969 - make 32-bit linux have a 16-byte aligned stack
 ; Verify that movups is still generated with an aligned stack for the globals
@@ -40,7 +39,42 @@ external global <4 x float>, align 1		; <<4 x float>*>:31 [#uses=1]
 
 declare void @abort()
 
-define void @""() {
+define void @test1() {
+; CHECK: test1
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK-NOT: movups
 	load <4 x float>* @0, align 1		; <<4 x float>>:1 [#uses=2]
 	load <4 x float>* @1, align 1		; <<4 x float>>:2 [#uses=3]
 	load <4 x float>* @2, align 1		; <<4 x float>>:3 [#uses=4]
@@ -637,3 +671,636 @@ define void @""() {
 	store <4 x float> %593, <4 x float>* @0, align 1
 	ret void
 }
+
+define void @test2() "no-realign-stack" {
+; CHECK: test2
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK: movups
+; CHECK-NOT: movups
+	load <4 x float>* @0, align 1
+	load <4 x float>* @1, align 1
+	load <4 x float>* @2, align 1
+	load <4 x float>* @3, align 1
+	load <4 x float>* @4, align 1
+	load <4 x float>* @5, align 1
+	load <4 x float>* @6, align 1
+	load <4 x float>* @7, align 1
+	load <4 x float>* @8, align 1
+	load <4 x float>* @9, align 1
+	load <4 x float>* @10, align 1
+	load <4 x float>* @11, align 1
+	load <4 x float>* @12, align 1
+	load <4 x float>* @13, align 1
+	load <4 x float>* @14, align 1
+	load <4 x float>* @15, align 1
+	load <4 x float>* @16, align 1
+	load <4 x float>* @17, align 1
+	load <4 x float>* @18, align 1
+	load <4 x float>* @19, align 1
+	load <4 x float>* @20, align 1
+	load <4 x float>* @21, align 1
+	load <4 x float>* @22, align 1
+	load <4 x float>* @23, align 1
+	load <4 x float>* @24, align 1
+	load <4 x float>* @25, align 1
+	load <4 x float>* @26, align 1
+	load <4 x float>* @27, align 1
+	load <4 x float>* @28, align 1
+	load <4 x float>* @29, align 1
+	load <4 x float>* @30, align 1
+	load <4 x float>* @31, align 1
+	fmul <4 x float> %1, %1
+	fmul <4 x float> %33, %2
+	fmul <4 x float> %34, %3
+	fmul <4 x float> %35, %4
+	fmul <4 x float> %36, %5
+	fmul <4 x float> %37, %6
+	fmul <4 x float> %38, %7
+	fmul <4 x float> %39, %8
+	fmul <4 x float> %40, %9
+	fmul <4 x float> %41, %10
+	fmul <4 x float> %42, %11		; <<4 x float>>:43 [#uses=1]
+	fmul <4 x float> %43, %12		; <<4 x float>>:44 [#uses=1]
+	fmul <4 x float> %44, %13		; <<4 x float>>:45 [#uses=1]
+	fmul <4 x float> %45, %14		; <<4 x float>>:46 [#uses=1]
+	fmul <4 x float> %46, %15		; <<4 x float>>:47 [#uses=1]
+	fmul <4 x float> %47, %16		; <<4 x float>>:48 [#uses=1]
+	fmul <4 x float> %48, %17		; <<4 x float>>:49 [#uses=1]
+	fmul <4 x float> %49, %18		; <<4 x float>>:50 [#uses=1]
+	fmul <4 x float> %50, %19		; <<4 x float>>:51 [#uses=1]
+	fmul <4 x float> %51, %20		; <<4 x float>>:52 [#uses=1]
+	fmul <4 x float> %52, %21		; <<4 x float>>:53 [#uses=1]
+	fmul <4 x float> %53, %22		; <<4 x float>>:54 [#uses=1]
+	fmul <4 x float> %54, %23		; <<4 x float>>:55 [#uses=1]
+	fmul <4 x float> %55, %24		; <<4 x float>>:56 [#uses=1]
+	fmul <4 x float> %56, %25		; <<4 x float>>:57 [#uses=1]
+	fmul <4 x float> %57, %26		; <<4 x float>>:58 [#uses=1]
+	fmul <4 x float> %58, %27		; <<4 x float>>:59 [#uses=1]
+	fmul <4 x float> %59, %28		; <<4 x float>>:60 [#uses=1]
+	fmul <4 x float> %60, %29		; <<4 x float>>:61 [#uses=1]
+	fmul <4 x float> %61, %30		; <<4 x float>>:62 [#uses=1]
+	fmul <4 x float> %62, %31		; <<4 x float>>:63 [#uses=1]
+	fmul <4 x float> %63, %32		; <<4 x float>>:64 [#uses=3]
+	fmul <4 x float> %2, %2		; <<4 x float>>:65 [#uses=1]
+	fmul <4 x float> %65, %3		; <<4 x float>>:66 [#uses=1]
+	fmul <4 x float> %66, %4		; <<4 x float>>:67 [#uses=1]
+	fmul <4 x float> %67, %5		; <<4 x float>>:68 [#uses=1]
+	fmul <4 x float> %68, %6		; <<4 x float>>:69 [#uses=1]
+	fmul <4 x float> %69, %7		; <<4 x float>>:70 [#uses=1]
+	fmul <4 x float> %70, %8		; <<4 x float>>:71 [#uses=1]
+	fmul <4 x float> %71, %9		; <<4 x float>>:72 [#uses=1]
+	fmul <4 x float> %72, %10		; <<4 x float>>:73 [#uses=1]
+	fmul <4 x float> %73, %11		; <<4 x float>>:74 [#uses=1]
+	fmul <4 x float> %74, %12		; <<4 x float>>:75 [#uses=1]
+	fmul <4 x float> %75, %13		; <<4 x float>>:76 [#uses=1]
+	fmul <4 x float> %76, %14		; <<4 x float>>:77 [#uses=1]
+	fmul <4 x float> %77, %15		; <<4 x float>>:78 [#uses=1]
+	fmul <4 x float> %78, %16		; <<4 x float>>:79 [#uses=1]
+	fmul <4 x float> %79, %17		; <<4 x float>>:80 [#uses=1]
+	fmul <4 x float> %80, %18		; <<4 x float>>:81 [#uses=1]
+	fmul <4 x float> %81, %19		; <<4 x float>>:82 [#uses=1]
+	fmul <4 x float> %82, %20		; <<4 x float>>:83 [#uses=1]
+	fmul <4 x float> %83, %21		; <<4 x float>>:84 [#uses=1]
+	fmul <4 x float> %84, %22		; <<4 x float>>:85 [#uses=1]
+	fmul <4 x float> %85, %23		; <<4 x float>>:86 [#uses=1]
+	fmul <4 x float> %86, %24		; <<4 x float>>:87 [#uses=1]
+	fmul <4 x float> %87, %25		; <<4 x float>>:88 [#uses=1]
+	fmul <4 x float> %88, %26		; <<4 x float>>:89 [#uses=1]
+	fmul <4 x float> %89, %27		; <<4 x float>>:90 [#uses=1]
+	fmul <4 x float> %90, %28		; <<4 x float>>:91 [#uses=1]
+	fmul <4 x float> %91, %29		; <<4 x float>>:92 [#uses=1]
+	fmul <4 x float> %92, %30		; <<4 x float>>:93 [#uses=1]
+	fmul <4 x float> %93, %31		; <<4 x float>>:94 [#uses=1]
+	fmul <4 x float> %94, %32		; <<4 x float>>:95 [#uses=1]
+	fmul <4 x float> %3, %3		; <<4 x float>>:96 [#uses=1]
+	fmul <4 x float> %96, %4		; <<4 x float>>:97 [#uses=1]
+	fmul <4 x float> %97, %5		; <<4 x float>>:98 [#uses=1]
+	fmul <4 x float> %98, %6		; <<4 x float>>:99 [#uses=1]
+	fmul <4 x float> %99, %7		; <<4 x float>>:100 [#uses=1]
+	fmul <4 x float> %100, %8		; <<4 x float>>:101 [#uses=1]
+	fmul <4 x float> %101, %9		; <<4 x float>>:102 [#uses=1]
+	fmul <4 x float> %102, %10		; <<4 x float>>:103 [#uses=1]
+	fmul <4 x float> %103, %11		; <<4 x float>>:104 [#uses=1]
+	fmul <4 x float> %104, %12		; <<4 x float>>:105 [#uses=1]
+	fmul <4 x float> %105, %13		; <<4 x float>>:106 [#uses=1]
+	fmul <4 x float> %106, %14		; <<4 x float>>:107 [#uses=1]
+	fmul <4 x float> %107, %15		; <<4 x float>>:108 [#uses=1]
+	fmul <4 x float> %108, %16		; <<4 x float>>:109 [#uses=1]
+	fmul <4 x float> %109, %17		; <<4 x float>>:110 [#uses=1]
+	fmul <4 x float> %110, %18		; <<4 x float>>:111 [#uses=1]
+	fmul <4 x float> %111, %19		; <<4 x float>>:112 [#uses=1]
+	fmul <4 x float> %112, %20		; <<4 x float>>:113 [#uses=1]
+	fmul <4 x float> %113, %21		; <<4 x float>>:114 [#uses=1]
+	fmul <4 x float> %114, %22		; <<4 x float>>:115 [#uses=1]
+	fmul <4 x float> %115, %23		; <<4 x float>>:116 [#uses=1]
+	fmul <4 x float> %116, %24		; <<4 x float>>:117 [#uses=1]
+	fmul <4 x float> %117, %25		; <<4 x float>>:118 [#uses=1]
+	fmul <4 x float> %118, %26		; <<4 x float>>:119 [#uses=1]
+	fmul <4 x float> %119, %27		; <<4 x float>>:120 [#uses=1]
+	fmul <4 x float> %120, %28		; <<4 x float>>:121 [#uses=1]
+	fmul <4 x float> %121, %29		; <<4 x float>>:122 [#uses=1]
+	fmul <4 x float> %122, %30		; <<4 x float>>:123 [#uses=1]
+	fmul <4 x float> %123, %31		; <<4 x float>>:124 [#uses=1]
+	fmul <4 x float> %124, %32		; <<4 x float>>:125 [#uses=1]
+	fmul <4 x float> %4, %4		; <<4 x float>>:126 [#uses=1]
+	fmul <4 x float> %126, %5		; <<4 x float>>:127 [#uses=1]
+	fmul <4 x float> %127, %6		; <<4 x float>>:128 [#uses=1]
+	fmul <4 x float> %128, %7		; <<4 x float>>:129 [#uses=1]
+	fmul <4 x float> %129, %8		; <<4 x float>>:130 [#uses=1]
+	fmul <4 x float> %130, %9		; <<4 x float>>:131 [#uses=1]
+	fmul <4 x float> %131, %10		; <<4 x float>>:132 [#uses=1]
+	fmul <4 x float> %132, %11		; <<4 x float>>:133 [#uses=1]
+	fmul <4 x float> %133, %12		; <<4 x float>>:134 [#uses=1]
+	fmul <4 x float> %134, %13		; <<4 x float>>:135 [#uses=1]
+	fmul <4 x float> %135, %14		; <<4 x float>>:136 [#uses=1]
+	fmul <4 x float> %136, %15		; <<4 x float>>:137 [#uses=1]
+	fmul <4 x float> %137, %16		; <<4 x float>>:138 [#uses=1]
+	fmul <4 x float> %138, %17		; <<4 x float>>:139 [#uses=1]
+	fmul <4 x float> %139, %18		; <<4 x float>>:140 [#uses=1]
+	fmul <4 x float> %140, %19		; <<4 x float>>:141 [#uses=1]
+	fmul <4 x float> %141, %20		; <<4 x float>>:142 [#uses=1]
+	fmul <4 x float> %142, %21		; <<4 x float>>:143 [#uses=1]
+	fmul <4 x float> %143, %22		; <<4 x float>>:144 [#uses=1]
+	fmul <4 x float> %144, %23		; <<4 x float>>:145 [#uses=1]
+	fmul <4 x float> %145, %24		; <<4 x float>>:146 [#uses=1]
+	fmul <4 x float> %146, %25		; <<4 x float>>:147 [#uses=1]
+	fmul <4 x float> %147, %26		; <<4 x float>>:148 [#uses=1]
+	fmul <4 x float> %148, %27		; <<4 x float>>:149 [#uses=1]
+	fmul <4 x float> %149, %28		; <<4 x float>>:150 [#uses=1]
+	fmul <4 x float> %150, %29		; <<4 x float>>:151 [#uses=1]
+	fmul <4 x float> %151, %30		; <<4 x float>>:152 [#uses=1]
+	fmul <4 x float> %152, %31		; <<4 x float>>:153 [#uses=1]
+	fmul <4 x float> %153, %32		; <<4 x float>>:154 [#uses=1]
+	fmul <4 x float> %5, %5		; <<4 x float>>:155 [#uses=1]
+	fmul <4 x float> %155, %6		; <<4 x float>>:156 [#uses=1]
+	fmul <4 x float> %156, %7		; <<4 x float>>:157 [#uses=1]
+	fmul <4 x float> %157, %8		; <<4 x float>>:158 [#uses=1]
+	fmul <4 x float> %158, %9		; <<4 x float>>:159 [#uses=1]
+	fmul <4 x float> %159, %10		; <<4 x float>>:160 [#uses=1]
+	fmul <4 x float> %160, %11		; <<4 x float>>:161 [#uses=1]
+	fmul <4 x float> %161, %12		; <<4 x float>>:162 [#uses=1]
+	fmul <4 x float> %162, %13		; <<4 x float>>:163 [#uses=1]
+	fmul <4 x float> %163, %14		; <<4 x float>>:164 [#uses=1]
+	fmul <4 x float> %164, %15		; <<4 x float>>:165 [#uses=1]
+	fmul <4 x float> %165, %16		; <<4 x float>>:166 [#uses=1]
+	fmul <4 x float> %166, %17		; <<4 x float>>:167 [#uses=1]
+	fmul <4 x float> %167, %18		; <<4 x float>>:168 [#uses=1]
+	fmul <4 x float> %168, %19		; <<4 x float>>:169 [#uses=1]
+	fmul <4 x float> %169, %20		; <<4 x float>>:170 [#uses=1]
+	fmul <4 x float> %170, %21		; <<4 x float>>:171 [#uses=1]
+	fmul <4 x float> %171, %22		; <<4 x float>>:172 [#uses=1]
+	fmul <4 x float> %172, %23		; <<4 x float>>:173 [#uses=1]
+	fmul <4 x float> %173, %24		; <<4 x float>>:174 [#uses=1]
+	fmul <4 x float> %174, %25		; <<4 x float>>:175 [#uses=1]
+	fmul <4 x float> %175, %26		; <<4 x float>>:176 [#uses=1]
+	fmul <4 x float> %176, %27		; <<4 x float>>:177 [#uses=1]
+	fmul <4 x float> %177, %28		; <<4 x float>>:178 [#uses=1]
+	fmul <4 x float> %178, %29		; <<4 x float>>:179 [#uses=1]
+	fmul <4 x float> %179, %30		; <<4 x float>>:180 [#uses=1]
+	fmul <4 x float> %180, %31		; <<4 x float>>:181 [#uses=1]
+	fmul <4 x float> %181, %32		; <<4 x float>>:182 [#uses=1]
+	fmul <4 x float> %6, %6		; <<4 x float>>:183 [#uses=1]
+	fmul <4 x float> %183, %7		; <<4 x float>>:184 [#uses=1]
+	fmul <4 x float> %184, %8		; <<4 x float>>:185 [#uses=1]
+	fmul <4 x float> %185, %9		; <<4 x float>>:186 [#uses=1]
+	fmul <4 x float> %186, %10		; <<4 x float>>:187 [#uses=1]
+	fmul <4 x float> %187, %11		; <<4 x float>>:188 [#uses=1]
+	fmul <4 x float> %188, %12		; <<4 x float>>:189 [#uses=1]
+	fmul <4 x float> %189, %13		; <<4 x float>>:190 [#uses=1]
+	fmul <4 x float> %190, %14		; <<4 x float>>:191 [#uses=1]
+	fmul <4 x float> %191, %15		; <<4 x float>>:192 [#uses=1]
+	fmul <4 x float> %192, %16		; <<4 x float>>:193 [#uses=1]
+	fmul <4 x float> %193, %17		; <<4 x float>>:194 [#uses=1]
+	fmul <4 x float> %194, %18		; <<4 x float>>:195 [#uses=1]
+	fmul <4 x float> %195, %19		; <<4 x float>>:196 [#uses=1]
+	fmul <4 x float> %196, %20		; <<4 x float>>:197 [#uses=1]
+	fmul <4 x float> %197, %21		; <<4 x float>>:198 [#uses=1]
+	fmul <4 x float> %198, %22		; <<4 x float>>:199 [#uses=1]
+	fmul <4 x float> %199, %23		; <<4 x float>>:200 [#uses=1]
+	fmul <4 x float> %200, %24		; <<4 x float>>:201 [#uses=1]
+	fmul <4 x float> %201, %25		; <<4 x float>>:202 [#uses=1]
+	fmul <4 x float> %202, %26		; <<4 x float>>:203 [#uses=1]
+	fmul <4 x float> %203, %27		; <<4 x float>>:204 [#uses=1]
+	fmul <4 x float> %204, %28		; <<4 x float>>:205 [#uses=1]
+	fmul <4 x float> %205, %29		; <<4 x float>>:206 [#uses=1]
+	fmul <4 x float> %206, %30		; <<4 x float>>:207 [#uses=1]
+	fmul <4 x float> %207, %31		; <<4 x float>>:208 [#uses=1]
+	fmul <4 x float> %208, %32		; <<4 x float>>:209 [#uses=1]
+	fmul <4 x float> %7, %7		; <<4 x float>>:210 [#uses=1]
+	fmul <4 x float> %210, %8		; <<4 x float>>:211 [#uses=1]
+	fmul <4 x float> %211, %9		; <<4 x float>>:212 [#uses=1]
+	fmul <4 x float> %212, %10		; <<4 x float>>:213 [#uses=1]
+	fmul <4 x float> %213, %11		; <<4 x float>>:214 [#uses=1]
+	fmul <4 x float> %214, %12		; <<4 x float>>:215 [#uses=1]
+	fmul <4 x float> %215, %13		; <<4 x float>>:216 [#uses=1]
+	fmul <4 x float> %216, %14		; <<4 x float>>:217 [#uses=1]
+	fmul <4 x float> %217, %15		; <<4 x float>>:218 [#uses=1]
+	fmul <4 x float> %218, %16		; <<4 x float>>:219 [#uses=1]
+	fmul <4 x float> %219, %17		; <<4 x float>>:220 [#uses=1]
+	fmul <4 x float> %220, %18		; <<4 x float>>:221 [#uses=1]
+	fmul <4 x float> %221, %19		; <<4 x float>>:222 [#uses=1]
+	fmul <4 x float> %222, %20		; <<4 x float>>:223 [#uses=1]
+	fmul <4 x float> %223, %21		; <<4 x float>>:224 [#uses=1]
+	fmul <4 x float> %224, %22		; <<4 x float>>:225 [#uses=1]
+	fmul <4 x float> %225, %23		; <<4 x float>>:226 [#uses=1]
+	fmul <4 x float> %226, %24		; <<4 x float>>:227 [#uses=1]
+	fmul <4 x float> %227, %25		; <<4 x float>>:228 [#uses=1]
+	fmul <4 x float> %228, %26		; <<4 x float>>:229 [#uses=1]
+	fmul <4 x float> %229, %27		; <<4 x float>>:230 [#uses=1]
+	fmul <4 x float> %230, %28		; <<4 x float>>:231 [#uses=1]
+	fmul <4 x float> %231, %29		; <<4 x float>>:232 [#uses=1]
+	fmul <4 x float> %232, %30		; <<4 x float>>:233 [#uses=1]
+	fmul <4 x float> %233, %31		; <<4 x float>>:234 [#uses=1]
+	fmul <4 x float> %234, %32		; <<4 x float>>:235 [#uses=1]
+	fmul <4 x float> %8, %8		; <<4 x float>>:236 [#uses=1]
+	fmul <4 x float> %236, %9		; <<4 x float>>:237 [#uses=1]
+	fmul <4 x float> %237, %10		; <<4 x float>>:238 [#uses=1]
+	fmul <4 x float> %238, %11		; <<4 x float>>:239 [#uses=1]
+	fmul <4 x float> %239, %12		; <<4 x float>>:240 [#uses=1]
+	fmul <4 x float> %240, %13		; <<4 x float>>:241 [#uses=1]
+	fmul <4 x float> %241, %14		; <<4 x float>>:242 [#uses=1]
+	fmul <4 x float> %242, %15		; <<4 x float>>:243 [#uses=1]
+	fmul <4 x float> %243, %16		; <<4 x float>>:244 [#uses=1]
+	fmul <4 x float> %244, %17		; <<4 x float>>:245 [#uses=1]
+	fmul <4 x float> %245, %18		; <<4 x float>>:246 [#uses=1]
+	fmul <4 x float> %246, %19		; <<4 x float>>:247 [#uses=1]
+	fmul <4 x float> %247, %20		; <<4 x float>>:248 [#uses=1]
+	fmul <4 x float> %248, %21		; <<4 x float>>:249 [#uses=1]
+	fmul <4 x float> %249, %22		; <<4 x float>>:250 [#uses=1]
+	fmul <4 x float> %250, %23		; <<4 x float>>:251 [#uses=1]
+	fmul <4 x float> %251, %24		; <<4 x float>>:252 [#uses=1]
+	fmul <4 x float> %252, %25		; <<4 x float>>:253 [#uses=1]
+	fmul <4 x float> %253, %26		; <<4 x float>>:254 [#uses=1]
+	fmul <4 x float> %254, %27		; <<4 x float>>:255 [#uses=1]
+	fmul <4 x float> %255, %28		; <<4 x float>>:256 [#uses=1]
+	fmul <4 x float> %256, %29		; <<4 x float>>:257 [#uses=1]
+	fmul <4 x float> %257, %30		; <<4 x float>>:258 [#uses=1]
+	fmul <4 x float> %258, %31		; <<4 x float>>:259 [#uses=1]
+	fmul <4 x float> %259, %32		; <<4 x float>>:260 [#uses=1]
+	fmul <4 x float> %9, %9		; <<4 x float>>:261 [#uses=1]
+	fmul <4 x float> %261, %10		; <<4 x float>>:262 [#uses=1]
+	fmul <4 x float> %262, %11		; <<4 x float>>:263 [#uses=1]
+	fmul <4 x float> %263, %12		; <<4 x float>>:264 [#uses=1]
+	fmul <4 x float> %264, %13		; <<4 x float>>:265 [#uses=1]
+	fmul <4 x float> %265, %14		; <<4 x float>>:266 [#uses=1]
+	fmul <4 x float> %266, %15		; <<4 x float>>:267 [#uses=1]
+	fmul <4 x float> %267, %16		; <<4 x float>>:268 [#uses=1]
+	fmul <4 x float> %268, %17		; <<4 x float>>:269 [#uses=1]
+	fmul <4 x float> %269, %18		; <<4 x float>>:270 [#uses=1]
+	fmul <4 x float> %270, %19		; <<4 x float>>:271 [#uses=1]
+	fmul <4 x float> %271, %20		; <<4 x float>>:272 [#uses=1]
+	fmul <4 x float> %272, %21		; <<4 x float>>:273 [#uses=1]
+	fmul <4 x float> %273, %22		; <<4 x float>>:274 [#uses=1]
+	fmul <4 x float> %274, %23		; <<4 x float>>:275 [#uses=1]
+	fmul <4 x float> %275, %24		; <<4 x float>>:276 [#uses=1]
+	fmul <4 x float> %276, %25		; <<4 x float>>:277 [#uses=1]
+	fmul <4 x float> %277, %26		; <<4 x float>>:278 [#uses=1]
+	fmul <4 x float> %278, %27		; <<4 x float>>:279 [#uses=1]
+	fmul <4 x float> %279, %28		; <<4 x float>>:280 [#uses=1]
+	fmul <4 x float> %280, %29		; <<4 x float>>:281 [#uses=1]
+	fmul <4 x float> %281, %30		; <<4 x float>>:282 [#uses=1]
+	fmul <4 x float> %282, %31		; <<4 x float>>:283 [#uses=1]
+	fmul <4 x float> %283, %32		; <<4 x float>>:284 [#uses=1]
+	fmul <4 x float> %10, %10		; <<4 x float>>:285 [#uses=1]
+	fmul <4 x float> %285, %11		; <<4 x float>>:286 [#uses=1]
+	fmul <4 x float> %286, %12		; <<4 x float>>:287 [#uses=1]
+	fmul <4 x float> %287, %13		; <<4 x float>>:288 [#uses=1]
+	fmul <4 x float> %288, %14		; <<4 x float>>:289 [#uses=1]
+	fmul <4 x float> %289, %15		; <<4 x float>>:290 [#uses=1]
+	fmul <4 x float> %290, %16		; <<4 x float>>:291 [#uses=1]
+	fmul <4 x float> %291, %17		; <<4 x float>>:292 [#uses=1]
+	fmul <4 x float> %292, %18		; <<4 x float>>:293 [#uses=1]
+	fmul <4 x float> %293, %19		; <<4 x float>>:294 [#uses=1]
+	fmul <4 x float> %294, %20		; <<4 x float>>:295 [#uses=1]
+	fmul <4 x float> %295, %21		; <<4 x float>>:296 [#uses=1]
+	fmul <4 x float> %296, %22		; <<4 x float>>:297 [#uses=1]
+	fmul <4 x float> %297, %23		; <<4 x float>>:298 [#uses=1]
+	fmul <4 x float> %298, %24		; <<4 x float>>:299 [#uses=1]
+	fmul <4 x float> %299, %25		; <<4 x float>>:300 [#uses=1]
+	fmul <4 x float> %300, %26		; <<4 x float>>:301 [#uses=1]
+	fmul <4 x float> %301, %27		; <<4 x float>>:302 [#uses=1]
+	fmul <4 x float> %302, %28		; <<4 x float>>:303 [#uses=1]
+	fmul <4 x float> %303, %29		; <<4 x float>>:304 [#uses=1]
+	fmul <4 x float> %304, %30		; <<4 x float>>:305 [#uses=1]
+	fmul <4 x float> %305, %31		; <<4 x float>>:306 [#uses=1]
+	fmul <4 x float> %306, %32		; <<4 x float>>:307 [#uses=1]
+	fmul <4 x float> %11, %11		; <<4 x float>>:308 [#uses=1]
+	fmul <4 x float> %308, %12		; <<4 x float>>:309 [#uses=1]
+	fmul <4 x float> %309, %13		; <<4 x float>>:310 [#uses=1]
+	fmul <4 x float> %310, %14		; <<4 x float>>:311 [#uses=1]
+	fmul <4 x float> %311, %15		; <<4 x float>>:312 [#uses=1]
+	fmul <4 x float> %312, %16		; <<4 x float>>:313 [#uses=1]
+	fmul <4 x float> %313, %17		; <<4 x float>>:314 [#uses=1]
+	fmul <4 x float> %314, %18		; <<4 x float>>:315 [#uses=1]
+	fmul <4 x float> %315, %19		; <<4 x float>>:316 [#uses=1]
+	fmul <4 x float> %316, %20		; <<4 x float>>:317 [#uses=1]
+	fmul <4 x float> %317, %21		; <<4 x float>>:318 [#uses=1]
+	fmul <4 x float> %318, %22		; <<4 x float>>:319 [#uses=1]
+	fmul <4 x float> %319, %23		; <<4 x float>>:320 [#uses=1]
+	fmul <4 x float> %320, %24		; <<4 x float>>:321 [#uses=1]
+	fmul <4 x float> %321, %25		; <<4 x float>>:322 [#uses=1]
+	fmul <4 x float> %322, %26		; <<4 x float>>:323 [#uses=1]
+	fmul <4 x float> %323, %27		; <<4 x float>>:324 [#uses=1]
+	fmul <4 x float> %324, %28		; <<4 x float>>:325 [#uses=1]
+	fmul <4 x float> %325, %29		; <<4 x float>>:326 [#uses=1]
+	fmul <4 x float> %326, %30		; <<4 x float>>:327 [#uses=1]
+	fmul <4 x float> %327, %31		; <<4 x float>>:328 [#uses=1]
+	fmul <4 x float> %328, %32		; <<4 x float>>:329 [#uses=1]
+	fmul <4 x float> %12, %12		; <<4 x float>>:330 [#uses=1]
+	fmul <4 x float> %330, %13		; <<4 x float>>:331 [#uses=1]
+	fmul <4 x float> %331, %14		; <<4 x float>>:332 [#uses=1]
+	fmul <4 x float> %332, %15		; <<4 x float>>:333 [#uses=1]
+	fmul <4 x float> %333, %16		; <<4 x float>>:334 [#uses=1]
+	fmul <4 x float> %334, %17		; <<4 x float>>:335 [#uses=1]
+	fmul <4 x float> %335, %18		; <<4 x float>>:336 [#uses=1]
+	fmul <4 x float> %336, %19		; <<4 x float>>:337 [#uses=1]
+	fmul <4 x float> %337, %20		; <<4 x float>>:338 [#uses=1]
+	fmul <4 x float> %338, %21		; <<4 x float>>:339 [#uses=1]
+	fmul <4 x float> %339, %22		; <<4 x float>>:340 [#uses=1]
+	fmul <4 x float> %340, %23		; <<4 x float>>:341 [#uses=1]
+	fmul <4 x float> %341, %24		; <<4 x float>>:342 [#uses=1]
+	fmul <4 x float> %342, %25		; <<4 x float>>:343 [#uses=1]
+	fmul <4 x float> %343, %26		; <<4 x float>>:344 [#uses=1]
+	fmul <4 x float> %344, %27		; <<4 x float>>:345 [#uses=1]
+	fmul <4 x float> %345, %28		; <<4 x float>>:346 [#uses=1]
+	fmul <4 x float> %346, %29		; <<4 x float>>:347 [#uses=1]
+	fmul <4 x float> %347, %30		; <<4 x float>>:348 [#uses=1]
+	fmul <4 x float> %348, %31		; <<4 x float>>:349 [#uses=1]
+	fmul <4 x float> %349, %32		; <<4 x float>>:350 [#uses=1]
+	fmul <4 x float> %13, %13		; <<4 x float>>:351 [#uses=1]
+	fmul <4 x float> %351, %14		; <<4 x float>>:352 [#uses=1]
+	fmul <4 x float> %352, %15		; <<4 x float>>:353 [#uses=1]
+	fmul <4 x float> %353, %16		; <<4 x float>>:354 [#uses=1]
+	fmul <4 x float> %354, %17		; <<4 x float>>:355 [#uses=1]
+	fmul <4 x float> %355, %18		; <<4 x float>>:356 [#uses=1]
+	fmul <4 x float> %356, %19		; <<4 x float>>:357 [#uses=1]
+	fmul <4 x float> %357, %20		; <<4 x float>>:358 [#uses=1]
+	fmul <4 x float> %358, %21		; <<4 x float>>:359 [#uses=1]
+	fmul <4 x float> %359, %22		; <<4 x float>>:360 [#uses=1]
+	fmul <4 x float> %360, %23		; <<4 x float>>:361 [#uses=1]
+	fmul <4 x float> %361, %24		; <<4 x float>>:362 [#uses=1]
+	fmul <4 x float> %362, %25		; <<4 x float>>:363 [#uses=1]
+	fmul <4 x float> %363, %26		; <<4 x float>>:364 [#uses=1]
+	fmul <4 x float> %364, %27		; <<4 x float>>:365 [#uses=1]
+	fmul <4 x float> %365, %28		; <<4 x float>>:366 [#uses=1]
+	fmul <4 x float> %366, %29		; <<4 x float>>:367 [#uses=1]
+	fmul <4 x float> %367, %30		; <<4 x float>>:368 [#uses=1]
+	fmul <4 x float> %368, %31		; <<4 x float>>:369 [#uses=1]
+	fmul <4 x float> %369, %32		; <<4 x float>>:370 [#uses=1]
+	fmul <4 x float> %14, %14		; <<4 x float>>:371 [#uses=1]
+	fmul <4 x float> %371, %15		; <<4 x float>>:372 [#uses=1]
+	fmul <4 x float> %372, %16		; <<4 x float>>:373 [#uses=1]
+	fmul <4 x float> %373, %17		; <<4 x float>>:374 [#uses=1]
+	fmul <4 x float> %374, %18		; <<4 x float>>:375 [#uses=1]
+	fmul <4 x float> %375, %19		; <<4 x float>>:376 [#uses=1]
+	fmul <4 x float> %376, %20		; <<4 x float>>:377 [#uses=1]
+	fmul <4 x float> %377, %21		; <<4 x float>>:378 [#uses=1]
+	fmul <4 x float> %378, %22		; <<4 x float>>:379 [#uses=1]
+	fmul <4 x float> %379, %23		; <<4 x float>>:380 [#uses=1]
+	fmul <4 x float> %380, %24		; <<4 x float>>:381 [#uses=1]
+	fmul <4 x float> %381, %25		; <<4 x float>>:382 [#uses=1]
+	fmul <4 x float> %382, %26		; <<4 x float>>:383 [#uses=1]
+	fmul <4 x float> %383, %27		; <<4 x float>>:384 [#uses=1]
+	fmul <4 x float> %384, %28		; <<4 x float>>:385 [#uses=1]
+	fmul <4 x float> %385, %29		; <<4 x float>>:386 [#uses=1]
+	fmul <4 x float> %386, %30		; <<4 x float>>:387 [#uses=1]
+	fmul <4 x float> %387, %31		; <<4 x float>>:388 [#uses=1]
+	fmul <4 x float> %388, %32		; <<4 x float>>:389 [#uses=1]
+	fmul <4 x float> %15, %15		; <<4 x float>>:390 [#uses=1]
+	fmul <4 x float> %390, %16		; <<4 x float>>:391 [#uses=1]
+	fmul <4 x float> %391, %17		; <<4 x float>>:392 [#uses=1]
+	fmul <4 x float> %392, %18		; <<4 x float>>:393 [#uses=1]
+	fmul <4 x float> %393, %19		; <<4 x float>>:394 [#uses=1]
+	fmul <4 x float> %394, %20		; <<4 x float>>:395 [#uses=1]
+	fmul <4 x float> %395, %21		; <<4 x float>>:396 [#uses=1]
+	fmul <4 x float> %396, %22		; <<4 x float>>:397 [#uses=1]
+	fmul <4 x float> %397, %23		; <<4 x float>>:398 [#uses=1]
+	fmul <4 x float> %398, %24		; <<4 x float>>:399 [#uses=1]
+	fmul <4 x float> %399, %25		; <<4 x float>>:400 [#uses=1]
+	fmul <4 x float> %400, %26		; <<4 x float>>:401 [#uses=1]
+	fmul <4 x float> %401, %27		; <<4 x float>>:402 [#uses=1]
+	fmul <4 x float> %402, %28		; <<4 x float>>:403 [#uses=1]
+	fmul <4 x float> %403, %29		; <<4 x float>>:404 [#uses=1]
+	fmul <4 x float> %404, %30		; <<4 x float>>:405 [#uses=1]
+	fmul <4 x float> %405, %31		; <<4 x float>>:406 [#uses=1]
+	fmul <4 x float> %406, %32		; <<4 x float>>:407 [#uses=1]
+	fmul <4 x float> %16, %16		; <<4 x float>>:408 [#uses=1]
+	fmul <4 x float> %408, %17		; <<4 x float>>:409 [#uses=1]
+	fmul <4 x float> %409, %18		; <<4 x float>>:410 [#uses=1]
+	fmul <4 x float> %410, %19		; <<4 x float>>:411 [#uses=1]
+	fmul <4 x float> %411, %20		; <<4 x float>>:412 [#uses=1]
+	fmul <4 x float> %412, %21		; <<4 x float>>:413 [#uses=1]
+	fmul <4 x float> %413, %22		; <<4 x float>>:414 [#uses=1]
+	fmul <4 x float> %414, %23		; <<4 x float>>:415 [#uses=1]
+	fmul <4 x float> %415, %24		; <<4 x float>>:416 [#uses=1]
+	fmul <4 x float> %416, %25		; <<4 x float>>:417 [#uses=1]
+	fmul <4 x float> %417, %26		; <<4 x float>>:418 [#uses=1]
+	fmul <4 x float> %418, %27		; <<4 x float>>:419 [#uses=1]
+	fmul <4 x float> %419, %28		; <<4 x float>>:420 [#uses=1]
+	fmul <4 x float> %420, %29		; <<4 x float>>:421 [#uses=1]
+	fmul <4 x float> %421, %30		; <<4 x float>>:422 [#uses=1]
+	fmul <4 x float> %422, %31		; <<4 x float>>:423 [#uses=1]
+	fmul <4 x float> %423, %32		; <<4 x float>>:424 [#uses=1]
+	fmul <4 x float> %17, %17		; <<4 x float>>:425 [#uses=1]
+	fmul <4 x float> %425, %18		; <<4 x float>>:426 [#uses=1]
+	fmul <4 x float> %426, %19		; <<4 x float>>:427 [#uses=1]
+	fmul <4 x float> %427, %20		; <<4 x float>>:428 [#uses=1]
+	fmul <4 x float> %428, %21		; <<4 x float>>:429 [#uses=1]
+	fmul <4 x float> %429, %22		; <<4 x float>>:430 [#uses=1]
+	fmul <4 x float> %430, %23		; <<4 x float>>:431 [#uses=1]
+	fmul <4 x float> %431, %24		; <<4 x float>>:432 [#uses=1]
+	fmul <4 x float> %432, %25		; <<4 x float>>:433 [#uses=1]
+	fmul <4 x float> %433, %26		; <<4 x float>>:434 [#uses=1]
+	fmul <4 x float> %434, %27		; <<4 x float>>:435 [#uses=1]
+	fmul <4 x float> %435, %28		; <<4 x float>>:436 [#uses=1]
+	fmul <4 x float> %436, %29		; <<4 x float>>:437 [#uses=1]
+	fmul <4 x float> %437, %30		; <<4 x float>>:438 [#uses=1]
+	fmul <4 x float> %438, %31		; <<4 x float>>:439 [#uses=1]
+	fmul <4 x float> %439, %32		; <<4 x float>>:440 [#uses=1]
+	fmul <4 x float> %18, %18		; <<4 x float>>:441 [#uses=1]
+	fmul <4 x float> %441, %19		; <<4 x float>>:442 [#uses=1]
+	fmul <4 x float> %442, %20		; <<4 x float>>:443 [#uses=1]
+	fmul <4 x float> %443, %21		; <<4 x float>>:444 [#uses=1]
+	fmul <4 x float> %444, %22		; <<4 x float>>:445 [#uses=1]
+	fmul <4 x float> %445, %23		; <<4 x float>>:446 [#uses=1]
+	fmul <4 x float> %446, %24		; <<4 x float>>:447 [#uses=1]
+	fmul <4 x float> %447, %25		; <<4 x float>>:448 [#uses=1]
+	fmul <4 x float> %448, %26		; <<4 x float>>:449 [#uses=1]
+	fmul <4 x float> %449, %27		; <<4 x float>>:450 [#uses=1]
+	fmul <4 x float> %450, %28		; <<4 x float>>:451 [#uses=1]
+	fmul <4 x float> %451, %29		; <<4 x float>>:452 [#uses=1]
+	fmul <4 x float> %452, %30		; <<4 x float>>:453 [#uses=1]
+	fmul <4 x float> %453, %31		; <<4 x float>>:454 [#uses=1]
+	fmul <4 x float> %454, %32		; <<4 x float>>:455 [#uses=1]
+	fmul <4 x float> %19, %19		; <<4 x float>>:456 [#uses=1]
+	fmul <4 x float> %456, %20		; <<4 x float>>:457 [#uses=1]
+	fmul <4 x float> %457, %21		; <<4 x float>>:458 [#uses=1]
+	fmul <4 x float> %458, %22		; <<4 x float>>:459 [#uses=1]
+	fmul <4 x float> %459, %23		; <<4 x float>>:460 [#uses=1]
+	fmul <4 x float> %460, %24		; <<4 x float>>:461 [#uses=1]
+	fmul <4 x float> %461, %25		; <<4 x float>>:462 [#uses=1]
+	fmul <4 x float> %462, %26		; <<4 x float>>:463 [#uses=1]
+	fmul <4 x float> %463, %27		; <<4 x float>>:464 [#uses=1]
+	fmul <4 x float> %464, %28		; <<4 x float>>:465 [#uses=1]
+	fmul <4 x float> %465, %29		; <<4 x float>>:466 [#uses=1]
+	fmul <4 x float> %466, %30		; <<4 x float>>:467 [#uses=1]
+	fmul <4 x float> %467, %31		; <<4 x float>>:468 [#uses=1]
+	fmul <4 x float> %468, %32		; <<4 x float>>:469 [#uses=1]
+	fmul <4 x float> %20, %20		; <<4 x float>>:470 [#uses=1]
+	fmul <4 x float> %470, %21		; <<4 x float>>:471 [#uses=1]
+	fmul <4 x float> %471, %22		; <<4 x float>>:472 [#uses=1]
+	fmul <4 x float> %472, %23		; <<4 x float>>:473 [#uses=1]
+	fmul <4 x float> %473, %24		; <<4 x float>>:474 [#uses=1]
+	fmul <4 x float> %474, %25		; <<4 x float>>:475 [#uses=1]
+	fmul <4 x float> %475, %26		; <<4 x float>>:476 [#uses=1]
+	fmul <4 x float> %476, %27		; <<4 x float>>:477 [#uses=1]
+	fmul <4 x float> %477, %28		; <<4 x float>>:478 [#uses=1]
+	fmul <4 x float> %478, %29		; <<4 x float>>:479 [#uses=1]
+	fmul <4 x float> %479, %30		; <<4 x float>>:480 [#uses=1]
+	fmul <4 x float> %480, %31		; <<4 x float>>:481 [#uses=1]
+	fmul <4 x float> %481, %32		; <<4 x float>>:482 [#uses=1]
+	fmul <4 x float> %21, %21		; <<4 x float>>:483 [#uses=1]
+	fmul <4 x float> %483, %22		; <<4 x float>>:484 [#uses=1]
+	fmul <4 x float> %484, %23		; <<4 x float>>:485 [#uses=1]
+	fmul <4 x float> %485, %24		; <<4 x float>>:486 [#uses=1]
+	fmul <4 x float> %486, %25		; <<4 x float>>:487 [#uses=1]
+	fmul <4 x float> %487, %26		; <<4 x float>>:488 [#uses=1]
+	fmul <4 x float> %488, %27		; <<4 x float>>:489 [#uses=1]
+	fmul <4 x float> %489, %28		; <<4 x float>>:490 [#uses=1]
+	fmul <4 x float> %490, %29		; <<4 x float>>:491 [#uses=1]
+	fmul <4 x float> %491, %30		; <<4 x float>>:492 [#uses=1]
+	fmul <4 x float> %492, %31		; <<4 x float>>:493 [#uses=1]
+	fmul <4 x float> %493, %32		; <<4 x float>>:494 [#uses=1]
+	fmul <4 x float> %22, %22		; <<4 x float>>:495 [#uses=1]
+	fmul <4 x float> %495, %23		; <<4 x float>>:496 [#uses=1]
+	fmul <4 x float> %496, %24		; <<4 x float>>:497 [#uses=1]
+	fmul <4 x float> %497, %25		; <<4 x float>>:498 [#uses=1]
+	fmul <4 x float> %498, %26		; <<4 x float>>:499 [#uses=1]
+	fmul <4 x float> %499, %27		; <<4 x float>>:500 [#uses=1]
+	fmul <4 x float> %500, %28		; <<4 x float>>:501 [#uses=1]
+	fmul <4 x float> %501, %29		; <<4 x float>>:502 [#uses=1]
+	fmul <4 x float> %502, %30		; <<4 x float>>:503 [#uses=1]
+	fmul <4 x float> %503, %31		; <<4 x float>>:504 [#uses=1]
+	fmul <4 x float> %504, %32		; <<4 x float>>:505 [#uses=1]
+	fmul <4 x float> %23, %23		; <<4 x float>>:506 [#uses=1]
+	fmul <4 x float> %506, %24		; <<4 x float>>:507 [#uses=1]
+	fmul <4 x float> %507, %25		; <<4 x float>>:508 [#uses=1]
+	fmul <4 x float> %508, %26		; <<4 x float>>:509 [#uses=1]
+	fmul <4 x float> %509, %27		; <<4 x float>>:510 [#uses=1]
+	fmul <4 x float> %510, %28		; <<4 x float>>:511 [#uses=1]
+	fmul <4 x float> %511, %29		; <<4 x float>>:512 [#uses=1]
+	fmul <4 x float> %512, %30		; <<4 x float>>:513 [#uses=1]
+	fmul <4 x float> %513, %31		; <<4 x float>>:514 [#uses=1]
+	fmul <4 x float> %514, %32		; <<4 x float>>:515 [#uses=1]
+	fmul <4 x float> %24, %24		; <<4 x float>>:516 [#uses=1]
+	fmul <4 x float> %516, %25		; <<4 x float>>:517 [#uses=1]
+	fmul <4 x float> %517, %26		; <<4 x float>>:518 [#uses=1]
+	fmul <4 x float> %518, %27		; <<4 x float>>:519 [#uses=1]
+	fmul <4 x float> %519, %28		; <<4 x float>>:520 [#uses=1]
+	fmul <4 x float> %520, %29		; <<4 x float>>:521 [#uses=1]
+	fmul <4 x float> %521, %30		; <<4 x float>>:522 [#uses=1]
+	fmul <4 x float> %522, %31		; <<4 x float>>:523 [#uses=1]
+	fmul <4 x float> %523, %32		; <<4 x float>>:524 [#uses=1]
+	fmul <4 x float> %25, %25		; <<4 x float>>:525 [#uses=1]
+	fmul <4 x float> %525, %26		; <<4 x float>>:526 [#uses=1]
+	fmul <4 x float> %526, %27		; <<4 x float>>:527 [#uses=1]
+	fmul <4 x float> %527, %28		; <<4 x float>>:528 [#uses=1]
+	fmul <4 x float> %528, %29		; <<4 x float>>:529 [#uses=1]
+	fmul <4 x float> %529, %30		; <<4 x float>>:530 [#uses=1]
+	fmul <4 x float> %530, %31		; <<4 x float>>:531 [#uses=1]
+	fmul <4 x float> %531, %32		; <<4 x float>>:532 [#uses=1]
+	fmul <4 x float> %26, %26		; <<4 x float>>:533 [#uses=1]
+	fmul <4 x float> %533, %27		; <<4 x float>>:534 [#uses=1]
+	fmul <4 x float> %534, %28		; <<4 x float>>:535 [#uses=1]
+	fmul <4 x float> %535, %29		; <<4 x float>>:536 [#uses=1]
+	fmul <4 x float> %536, %30		; <<4 x float>>:537 [#uses=1]
+	fmul <4 x float> %537, %31		; <<4 x float>>:538 [#uses=1]
+	fmul <4 x float> %538, %32		; <<4 x float>>:539 [#uses=1]
+	fmul <4 x float> %27, %27		; <<4 x float>>:540 [#uses=1]
+	fmul <4 x float> %540, %28		; <<4 x float>>:541 [#uses=1]
+	fmul <4 x float> %541, %29		; <<4 x float>>:542 [#uses=1]
+	fmul <4 x float> %542, %30		; <<4 x float>>:543 [#uses=1]
+	fmul <4 x float> %543, %31		; <<4 x float>>:544 [#uses=1]
+	fmul <4 x float> %544, %32		; <<4 x float>>:545 [#uses=1]
+	fmul <4 x float> %28, %28		; <<4 x float>>:546 [#uses=1]
+	fmul <4 x float> %546, %29		; <<4 x float>>:547 [#uses=1]
+	fmul <4 x float> %547, %30		; <<4 x float>>:548 [#uses=1]
+	fmul <4 x float> %548, %31		; <<4 x float>>:549 [#uses=1]
+	fmul <4 x float> %549, %32		; <<4 x float>>:550 [#uses=1]
+	fmul <4 x float> %29, %29		; <<4 x float>>:551 [#uses=1]
+	fmul <4 x float> %551, %30		; <<4 x float>>:552 [#uses=1]
+	fmul <4 x float> %552, %31		; <<4 x float>>:553 [#uses=1]
+	fmul <4 x float> %553, %32		; <<4 x float>>:554 [#uses=1]
+	fmul <4 x float> %30, %30		; <<4 x float>>:555 [#uses=1]
+	fmul <4 x float> %555, %31		; <<4 x float>>:556 [#uses=1]
+	fmul <4 x float> %556, %32		; <<4 x float>>:557 [#uses=1]
+	fmul <4 x float> %31, %31		; <<4 x float>>:558 [#uses=1]
+	fmul <4 x float> %558, %32		; <<4 x float>>:559 [#uses=1]
+	fmul <4 x float> %32, %32		; <<4 x float>>:560 [#uses=1]
+	fadd <4 x float> %64, %64		; <<4 x float>>:561 [#uses=1]
+	fadd <4 x float> %561, %64		; <<4 x float>>:562 [#uses=1]
+	fadd <4 x float> %562, %95		; <<4 x float>>:563 [#uses=1]
+	fadd <4 x float> %563, %125		; <<4 x float>>:564 [#uses=1]
+	fadd <4 x float> %564, %154		; <<4 x float>>:565 [#uses=1]
+	fadd <4 x float> %565, %182		; <<4 x float>>:566 [#uses=1]
+	fadd <4 x float> %566, %209		; <<4 x float>>:567 [#uses=1]
+	fadd <4 x float> %567, %235		; <<4 x float>>:568 [#uses=1]
+	fadd <4 x float> %568, %260		; <<4 x float>>:569 [#uses=1]
+	fadd <4 x float> %569, %284		; <<4 x float>>:570 [#uses=1]
+	fadd <4 x float> %570, %307		; <<4 x float>>:571 [#uses=1]
+	fadd <4 x float> %571, %329		; <<4 x float>>:572 [#uses=1]
+	fadd <4 x float> %572, %350		; <<4 x float>>:573 [#uses=1]
+	fadd <4 x float> %573, %370		; <<4 x float>>:574 [#uses=1]
+	fadd <4 x float> %574, %389		; <<4 x float>>:575 [#uses=1]
+	fadd <4 x float> %575, %407		; <<4 x float>>:576 [#uses=1]
+	fadd <4 x float> %576, %424		; <<4 x float>>:577 [#uses=1]
+	fadd <4 x float> %577, %440		; <<4 x float>>:578 [#uses=1]
+	fadd <4 x float> %578, %455		; <<4 x float>>:579 [#uses=1]
+	fadd <4 x float> %579, %469		; <<4 x float>>:580 [#uses=1]
+	fadd <4 x float> %580, %482		; <<4 x float>>:581 [#uses=1]
+	fadd <4 x float> %581, %494		; <<4 x float>>:582 [#uses=1]
+	fadd <4 x float> %582, %505		; <<4 x float>>:583 [#uses=1]
+	fadd <4 x float> %583, %515		; <<4 x float>>:584 [#uses=1]
+	fadd <4 x float> %584, %524		; <<4 x float>>:585 [#uses=1]
+	fadd <4 x float> %585, %532		; <<4 x float>>:586 [#uses=1]
+	fadd <4 x float> %586, %539		; <<4 x float>>:587 [#uses=1]
+	fadd <4 x float> %587, %545		; <<4 x float>>:588 [#uses=1]
+	fadd <4 x float> %588, %550		; <<4 x float>>:589 [#uses=1]
+	fadd <4 x float> %589, %554		; <<4 x float>>:590 [#uses=1]
+	fadd <4 x float> %590, %557		; <<4 x float>>:591 [#uses=1]
+	fadd <4 x float> %591, %559		; <<4 x float>>:592 [#uses=1]
+	fadd <4 x float> %592, %560		; <<4 x float>>:593 [#uses=1]
+	store <4 x float> %593, <4 x float>* @0, align 1
+	ret void
+}
diff --git a/test/CodeGen/X86/2008-08-19-SubAndFetch.ll b/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
index 360ec73..9324d5d 100644
--- a/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
+++ b/test/CodeGen/X86/2008-08-19-SubAndFetch.ll
@@ -4,7 +4,7 @@
 
 define i32 @main() nounwind {
 entry:
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK: lock
 ; CHECK: decq
 	atomicrmw sub i64* @var, i64 1 monotonic
diff --git a/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll b/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll
index c63c890..7cf9cb0 100644
--- a/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll
+++ b/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll
@@ -1,5 +1,5 @@
 ; Check that eh_return & unwind_init were properly lowered
-; RUN: llc < %s -verify-machineinstrs | FileCheck %s
+; RUN: llc -mcpu=corei7 < %s -verify-machineinstrs | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "i386-pc-linux"
diff --git a/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll b/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll
index 890fd0f..ecd8663 100644
--- a/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll
+++ b/test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll
@@ -67,19 +67,22 @@ declare i64 @strlen(i8*) nounwind readonly
 declare void @llvm.stackrestore(i8*) nounwind
 
 !0 = metadata !{i32 459009, metadata !1, metadata !"s1", metadata !2, i32 2, metadata !6} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 458798, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
-!2 = metadata !{i32 458769, i32 0, i32 1, metadata !"vla.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 458773, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!1 = metadata !{i32 458798, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", i32 2, metadata !3, i1 false, i1 true,
+                i32 0, i32 0, null, i32 0, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 458769, metadata !17, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !18, metadata !18, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 458773, null, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5, metadata !6}
-!5 = metadata !{i32 458788, metadata !2, metadata !"char", metadata !2, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 458767, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_pointer_type ]
+!5 = metadata !{i32 458788, null, metadata !2, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 458767, null, metadata !2, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_pointer_type ]
 !7 = metadata !{i32 2, i32 0, metadata !1, null}
 !8 = metadata !{i32 459008, metadata !1, metadata !"str.0", metadata !2, i32 3, metadata !9} ; [ DW_TAG_auto_variable ]
-!9 = metadata !{i32 458767, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !10} ; [ DW_TAG_pointer_type ]
-!10 = metadata !{i32 458753, metadata !2, metadata !"", metadata !2, i32 0, i64 8, i64 8, i64 0, i32 0, metadata !5, metadata !11, i32 0, null} ; [ DW_TAG_array_type ]
+!9 = metadata !{i32 458767, null, metadata !2, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 64, metadata !10} ; [ DW_TAG_pointer_type ]
+!10 = metadata !{i32 458753, null, metadata !2, metadata !"", i32 0, i64 8, i64 8, i64 0, i32 0, metadata !5, metadata !11, i32 0, null} ; [ DW_TAG_array_type ]
 !11 = metadata !{metadata !12}
 !12 = metadata !{i32 458785, i64 0, i64 1}        ; [ DW_TAG_subrange_type ]
 !13 = metadata !{i32 3, i32 0, metadata !14, null}
-!14 = metadata !{i32 458763, metadata !1, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!14 = metadata !{i32 458763, metadata !17, metadata !1, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !15 = metadata !{i32 4, i32 0, metadata !14, null}
 !16 = metadata !{i32 5, i32 0, metadata !14, null}
+!17 = metadata !{metadata !"vla.c", metadata !"/tmp/"}
+!18 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll b/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll
index d64c966..7549651 100644
--- a/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll
+++ b/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll
@@ -5,7 +5,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 target triple = "i386-apple-darwin9.6"
 
 define void @f() nounwind {
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK-NOT: ret
 ; CHECK: foo $-81920
 ; CHECK-NOT: ret
diff --git a/test/CodeGen/X86/2009-03-23-MultiUseSched.ll b/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
index 351a172..bbc1d34 100644
--- a/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
+++ b/test/CodeGen/X86/2009-03-23-MultiUseSched.ll
@@ -1,5 +1,5 @@
 ; REQUIRES: asserts
-; RUN: llc < %s -mtriple=x86_64-linux -relocation-model=static -o /dev/null -stats -info-output-file - > %t
+; RUN: llc < %s -mtriple=x86_64-linux -mcpu=corei7 -relocation-model=static -o /dev/null -stats -info-output-file - > %t
 ; RUN: not grep spill %t
 ; RUN: not grep "%rsp" %t
 ; RUN: not grep "%rbp" %t
diff --git a/test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll b/test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll
index 3cd5416..7c87598 100644
--- a/test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll
+++ b/test/CodeGen/X86/2009-05-23-dagcombine-shifts.ll
@@ -9,7 +9,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define i64 @foo(i64 %b) nounwind readnone {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: shlq $56, %rdi
 ; CHECK: sarq $48, %rdi
 ; CHECK: leaq 1(%rdi), %rax
diff --git a/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll b/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll
index 80b8835..0268d81 100644
--- a/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll
+++ b/test/CodeGen/X86/2009-09-21-NoSpillLoopCount.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=i386-apple-darwin10.0 -relocation-model=pic | FileCheck %s
 
 define void @dot(i16* nocapture %A, i32 %As, i16* nocapture %B, i32 %Bs, i16* nocapture %C, i32 %N) nounwind ssp {
-; CHECK: dot:
+; CHECK-LABEL: dot:
 ; CHECK: decl %
 ; CHECK-NEXT: jne
 entry:
diff --git a/test/CodeGen/X86/2009-10-16-Scope.ll b/test/CodeGen/X86/2009-10-16-Scope.ll
index e41038d..ae2e9ac 100644
--- a/test/CodeGen/X86/2009-10-16-Scope.ll
+++ b/test/CodeGen/X86/2009-10-16-Scope.ll
@@ -23,10 +23,13 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 declare i32 @foo(i32) ssp
 
 !0 = metadata !{i32 5, i32 2, metadata !1, null}
-!1 = metadata !{i32 458763, metadata !2, i32 1, i32 1}; [DW_TAG_lexical_block ]
-!2 = metadata !{i32 458798, i32 0, metadata !3, metadata !"bar", metadata !"bar", metadata !"bar", metadata !3, i32 4, null, i1 false, i1 true}; [DW_TAG_subprogram ]
-!3 = metadata !{i32 458769, i32 0, i32 12, metadata !"genmodes.i", metadata !"/Users/yash/Downloads", metadata !"clang 1.1", i1 true, i1 false, metadata !"", i32 0}; [DW_TAG_compile_unit ]
+!1 = metadata !{i32 458763, null, metadata !2, i32 1, i32 1, i32 0}; [DW_TAG_lexical_block ]
+!2 = metadata !{i32 458798, i32 0, metadata !3, metadata !"bar", metadata !"bar", metadata !"bar", i32 4, null, i1 false, i1 true,
+               i32 0, i32 0, null, i32 0, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!3 = metadata !{i32 458769, metadata !8, i32 12, metadata !"clang 1.1", i1 true, metadata !"", i32 0, null, metadata !9, null, null, null, metadata !""}; [DW_TAG_compile_unit ]
 !4 = metadata !{i32 459008, metadata !5, metadata !"count_", metadata !3, i32 5, metadata !6}; [ DW_TAG_auto_variable ]
-!5 = metadata !{i32 458763, metadata !1, i32 1, i32 1}; [DW_TAG_lexical_block ]
-!6 = metadata !{i32 458788, metadata !3, metadata !"int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}; [DW_TAG_base_type ]
+!5 = metadata !{i32 458763, null, metadata !1, i32 1, i32 1, i32 0}; [DW_TAG_lexical_block ]
+!6 = metadata !{i32 458788, null, metadata !3, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}; [DW_TAG_base_type ]
 !7 = metadata !{i32 6, i32 1, metadata !2, null}
+!8 = metadata !{metadata !"genmodes.i", metadata !"/Users/yash/Downloads"}
+!9 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/2009-11-16-MachineLICM.ll b/test/CodeGen/X86/2009-11-16-MachineLICM.ll
index 2ac688f..fedb2a5 100644
--- a/test/CodeGen/X86/2009-11-16-MachineLICM.ll
+++ b/test/CodeGen/X86/2009-11-16-MachineLICM.ll
@@ -5,7 +5,7 @@
 
 define void @foo(i32 %n, float* nocapture %x) nounwind ssp {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
   %0 = icmp sgt i32 %n, 0                         ; <i1> [#uses=1]
   br i1 %0, label %bb.nph, label %return
 
diff --git a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll
index c2d9d84..08a99e3 100644
--- a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll
+++ b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll
@@ -5,7 +5,7 @@
 
 define void @t(i32 %count) ssp nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movups L_str+12(%rip), %xmm0
 ; CHECK: movups L_str(%rip), %xmm1
   %tmp0 = alloca [60 x i8], align 1
diff --git a/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll b/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
index 0700323..b166447 100644
--- a/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
+++ b/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll
@@ -3,7 +3,7 @@
 
 define void @t() nounwind ssp {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movl %ecx, %eax
 ; CHECK: %eax = foo (%eax, %ecx)
   %b = alloca i32                                 ; <i32*> [#uses=2]
@@ -21,7 +21,7 @@ return:                                           ; preds = %entry
 
 define void @t2() nounwind ssp {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: movl
 ; CHECK: [[D2:%e.x]] = foo
 ; CHECK: ([[D2]],
diff --git a/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll b/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll
index 823e0ca..65b70a7 100644
--- a/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll
+++ b/test/CodeGen/X86/2009-12-11-TLSNoRedZone.ll
@@ -18,7 +18,7 @@ target triple = "x86_64-unknown-linux-gnu"
 @_dm_offset_addr_mask = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=0]
 
 define void @leaf() nounwind {
-; CHECK: leaf:
+; CHECK-LABEL: leaf:
 ; CHECK-NOT: -8(%rsp)
 ; CHECK: leaq link_ptr@TLSGD
 ; CHECK: callq __tls_get_addr@PLT
diff --git a/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll b/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
index 3d058bc..f9bf310 100644
--- a/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
+++ b/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll
@@ -6,7 +6,7 @@
 
 define void @t(i64* nocapture %p) nounwind ssp {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movl ([[REG:%[a-z]+]]), %eax
 ; CHECK: movl 4([[REG]]), %edx
 ; CHECK: LBB0_1:
diff --git a/test/CodeGen/X86/2010-01-18-DbgValue.ll b/test/CodeGen/X86/2010-01-18-DbgValue.ll
index 7dba332..c54f030 100644
--- a/test/CodeGen/X86/2010-01-18-DbgValue.ll
+++ b/test/CodeGen/X86/2010-01-18-DbgValue.ll
@@ -31,9 +31,9 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!3}
 
 !0 = metadata !{i32 786689, metadata !1, metadata !"my_r0", metadata !2, i32 11, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, double (%struct.Rect*)* @foo, null, null, null, i32 11} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786478, metadata !19, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, double (%struct.Rect*)* @foo, null, null, null, i32 11} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !19} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !18, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786449, metadata !19, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !20, metadata !20, metadata !18, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !4 = metadata !{i32 786453, metadata !19, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{metadata !6, metadata !7}
 !6 = metadata !{i32 786468, metadata !19, metadata !2, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
@@ -47,6 +47,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 !14 = metadata !{i32 786445, metadata !19, metadata !7, metadata !"P2", i32 8, i64 128, i64 64, i64 128, i32 0, metadata !10} ; [ DW_TAG_member ]
 !15 = metadata !{i32 11, i32 0, metadata !1, null}
 !16 = metadata !{i32 12, i32 0, metadata !17, null}
-!17 = metadata !{i32 786443, metadata !1, i32 11, i32 0} ; [ DW_TAG_lexical_block ]
+!17 = metadata !{i32 786443, metadata !19, metadata !1, i32 11, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !18 = metadata !{metadata !1}
 !19 = metadata !{metadata !"b2.c", metadata !"/tmp/"}
+!20 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/2010-02-01-DbgValueCrash.ll b/test/CodeGen/X86/2010-02-01-DbgValueCrash.ll
index 2113263..71c7b65 100644
--- a/test/CodeGen/X86/2010-02-01-DbgValueCrash.ll
+++ b/test/CodeGen/X86/2010-02-01-DbgValueCrash.ll
@@ -16,18 +16,20 @@ entry:
 declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone
 
-!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ]
-!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ]
+!0 = metadata !{i32 458769, metadata !15, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !16, metadata !16, null, null, null, i32 0} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 458790, metadata !15, metadata !0, metadata !"", i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ]
+!2 = metadata !{i32 458771, metadata !15, metadata !0, metadata !"C", i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ]
 !3 = metadata !{metadata !4, metadata !6, metadata !7}
-!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ]
-!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ]
-!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ]
+!4 = metadata !{i32 458765, metadata !15, metadata !2, metadata !"x", i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ]
+!5 = metadata !{i32 458788, metadata !15, metadata !0, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 458765, metadata !15, metadata !2, metadata !"y", i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ]
+!7 = metadata !{i32 458765, metadata !15, metadata !2, metadata !"z", i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ]
 !8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ]
-!9 = metadata !{i32 458763, metadata !10}        ; [ DW_TAG_lexical_block ]
-!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ]
-!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!9 = metadata !{i32 458763, null, metadata !10, i32 0, i32 0, i32 0}        ; [ DW_TAG_lexical_block ]
+!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i32 0, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!11 = metadata !{i32 458773, metadata !15, metadata !0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !12 = metadata !{metadata !13}
-!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!13 = metadata !{i32 458788, metadata !15, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest}
+!15 = metadata !{metadata !"sm.c", metadata !""}
+!16 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/2010-02-23-DAGCombineBug.ll b/test/CodeGen/X86/2010-02-23-DAGCombineBug.ll
index 6a58e9e..a8c87fa 100644
--- a/test/CodeGen/X86/2010-02-23-DAGCombineBug.ll
+++ b/test/CodeGen/X86/2010-02-23-DAGCombineBug.ll
@@ -2,7 +2,7 @@
 
 define i32* @t() nounwind optsize ssp {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: testl %eax, %eax
 ; CHECK: js
   %cmp = icmp slt i32 undef, 0                    ; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/2010-04-08-CoalescerBug.ll b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll
index 9a5958e..5e86ecf 100644
--- a/test/CodeGen/X86/2010-04-08-CoalescerBug.ll
+++ b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll
@@ -11,7 +11,7 @@
 
 define void @t(%struct.F* %this) nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: addq $12, %rsi
   %BitValueArray = alloca [32 x i32], align 4
   %tmp2 = getelementptr inbounds %struct.F* %this, i64 0, i32 0
diff --git a/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll b/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll
index 7650a5c..00ac71a 100644
--- a/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll
+++ b/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll
@@ -201,9 +201,9 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !llvm.dbg.cu = !{!3}
 
 !0 = metadata !{i32 786689, metadata !1, metadata !"a", metadata !2, i32 1921, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"__divsc3", metadata !"__divsc3", metadata !"__divsc3", metadata !2, i32 1922, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, %0 (float, float, float, float)* @__divsc3, null, null, metadata !43, i32 1922} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786478, metadata !45, metadata !2, metadata !"__divsc3", metadata !"__divsc3", metadata !"__divsc3", i32 1922, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, %0 (float, float, float, float)* @__divsc3, null, null, metadata !43, i32 1922} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !45} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !44, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786449, metadata !45, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !47, metadata !47, metadata !44, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
 !4 = metadata !{i32 786453, metadata !45, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{metadata !6, metadata !9, metadata !9, metadata !9, metadata !9}
 !6 = metadata !{i32 786454, metadata !46, metadata !7, metadata !"SCtype", i32 170, i64 0, i64 0, i64 0, i32 0, metadata !8} ; [ DW_TAG_typedef ]
@@ -215,7 +215,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !12 = metadata !{i32 786689, metadata !1, metadata !"c", metadata !2, i32 1921, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ]
 !13 = metadata !{i32 786689, metadata !1, metadata !"d", metadata !2, i32 1921, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ]
 !14 = metadata !{i32 786688, metadata !15, metadata !"denom", metadata !2, i32 1923, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ]
-!15 = metadata !{i32 786443, metadata !2, metadata !1, i32 1922, i32 0} ; [ DW_TAG_lexical_block ]
+!15 = metadata !{i32 786443, metadata !45, metadata !1, i32 1922, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !16 = metadata !{i32 786688, metadata !15, metadata !"ratio", metadata !2, i32 1923, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ]
 !17 = metadata !{i32 786688, metadata !15, metadata !"x", metadata !2, i32 1923, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ]
 !18 = metadata !{i32 786688, metadata !15, metadata !"y", metadata !2, i32 1923, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ]
@@ -247,3 +247,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !44 = metadata !{metadata !1}
 !45 = metadata !{metadata !"libgcc2.c", metadata !"/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc"}
 !46 = metadata !{metadata !"libgcc2.h", metadata !"/Users/yash/clean/LG.D/gcc/../../llvmgcc/gcc"}
+!47 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll
index 6510ff1..4b1dfb3 100644
--- a/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll
+++ b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll
@@ -23,31 +23,31 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786484, i32 0, metadata !1, metadata !"ret", metadata !"ret", metadata !"", metadata !1, i32 7, metadata !3, i1 false, i1 true, null} ; [ DW_TAG_variable ]
+!0 = metadata !{i32 786484, i32 0, metadata !1, metadata !"ret", metadata !"ret", metadata !"", metadata !1, i32 7, metadata !3, i1 false, i1 true, null, null} ; [ DW_TAG_variable ]
 !1 = metadata !{i32 786473, metadata !36} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, metadata !36, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !32, metadata !31,  metadata !31, metadata !""} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!2 = metadata !{i32 786449, metadata !36, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !37, metadata !37, metadata !32, metadata !31,  metadata !31, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786468, metadata !36, metadata !1, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !4 = metadata !{i32 786689, metadata !5, metadata !"x", metadata !1, i32 12, metadata !3, i32 0, null} ; [ DW_TAG_arg_variable ]
-!5 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 13, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, void (i32)* @foo, null, null, metadata !33, i32 13} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!5 = metadata !{i32 786478, metadata !36, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", i32 13, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, void (i32)* @foo, null, null, metadata !33, i32 13} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 786453, metadata !36, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !7 = metadata !{null, metadata !3}
 !8 = metadata !{i32 786689, metadata !9, metadata !"myvar", metadata !1, i32 17, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ]
-!9 = metadata !{i32 786478, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", metadata !1, i32 17, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i8* (%struct.a*)* @bar, null, null, metadata !34, i32 17} ; [ DW_TAG_subprogram ]
-!10 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!9 = metadata !{i32 786478, metadata !36, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", i32 17, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i8* (%struct.a*)* @bar, null, null, metadata !34, i32 17} ; [ DW_TAG_subprogram ]
+!10 = metadata !{i32 786453, metadata !36, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !11 = metadata !{metadata !12, metadata !13}
-!12 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
-!13 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ]
-!14 = metadata !{i32 786451, metadata !1, metadata !"a", metadata !1, i32 2, i64 128, i64 64, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_structure_type ]
+!12 = metadata !{i32 786447, metadata !36, metadata !1, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
+!13 = metadata !{i32 786447, metadata !36, metadata !1, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ]
+!14 = metadata !{i32 786451, metadata !36, metadata !1, metadata !"a", i32 2, i64 128, i64 64, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_structure_type ]
 !15 = metadata !{metadata !16, metadata !17}
-!16 = metadata !{i32 786445, metadata !14, metadata !"c", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !3} ; [ DW_TAG_member ]
-!17 = metadata !{i32 786445, metadata !14, metadata !"d", metadata !1, i32 4, i64 64, i64 64, i64 64, i32 0, metadata !13} ; [ DW_TAG_member ]
+!16 = metadata !{i32 786445, metadata !36, metadata !14, metadata !"c", i32 3, i64 32, i64 32, i64 0, i32 0, metadata !3} ; [ DW_TAG_member ]
+!17 = metadata !{i32 786445, metadata !36, metadata !14, metadata !"d", i32 4, i64 64, i64 64, i64 64, i32 0, metadata !13} ; [ DW_TAG_member ]
 !18 = metadata !{i32 786689, metadata !19, metadata !"argc", metadata !1, i32 22, metadata !3, i32 0, null} ; [ DW_TAG_arg_variable ]
-!19 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 22, metadata !20, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, null, null, null, metadata !35, i32 22} ; [ DW_TAG_subprogram ]
-!20 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !21, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!19 = metadata !{i32 786478, metadata !36, metadata !1, metadata !"main", metadata !"main", metadata !"main", i32 22, metadata !20, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, null, null, null, metadata !35, i32 22} ; [ DW_TAG_subprogram ]
+!20 = metadata !{i32 786453, metadata !36, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !21, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !21 = metadata !{metadata !3, metadata !3, metadata !22}
-!22 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ]
-!23 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !24} ; [ DW_TAG_pointer_type ]
-!24 = metadata !{i32 786468, metadata !1, metadata !"char", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!22 = metadata !{i32 786447, metadata !36, metadata !1, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ]
+!23 = metadata !{i32 786447, metadata !36, metadata !1, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !24} ; [ DW_TAG_pointer_type ]
+!24 = metadata !{i32 786468, metadata !36, metadata !1, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !25 = metadata !{i32 786689, metadata !19, metadata !"argv", metadata !1, i32 22, metadata !22, i32 0, null} ; [ DW_TAG_arg_variable ]
 !26 = metadata !{i32 786688, metadata !27, metadata !"e", metadata !1, i32 23, metadata !14, i32 0, null} ; [ DW_TAG_auto_variable ]
 !27 = metadata !{i32 786443, metadata !36, metadata !19, i32 22, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
@@ -60,6 +60,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !34 = metadata !{metadata !8}
 !35 = metadata !{metadata !18, metadata !25, metadata !26}
 !36 = metadata !{metadata !"foo.c", metadata !"/tmp/"}
+!37 = metadata !{i32 0}
 
 ; The variable bar:myvar changes registers after the first movq.
 ; It is cobbered by popq %rbx
diff --git a/test/CodeGen/X86/2010-05-28-Crash.ll b/test/CodeGen/X86/2010-05-28-Crash.ll
index ee00dba..d5c0ead 100644
--- a/test/CodeGen/X86/2010-05-28-Crash.ll
+++ b/test/CodeGen/X86/2010-05-28-Crash.ll
@@ -1,5 +1,5 @@
-; RUN: llc  -mtriple=x86_64-apple-darwin < %s | FileCheck %s
-; RUN: llc  -mtriple=x86_64-apple-darwin -regalloc=basic < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-apple-darwin -regalloc=basic < %s | FileCheck %s
 ; Test to check separate label for inlined function argument.
 
 define i32 @foo(i32 %y) nounwind optsize ssp {
@@ -25,25 +25,26 @@ entry:
 !llvm.dbg.cu = !{!3}
 
 !0 = metadata !{i32 786689, metadata !1, metadata !"y", metadata !2, i32 2, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 2, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32)* @foo, null, null, metadata !15, i32 2} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786478, metadata !18, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", i32 2, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32)* @foo, null, null, metadata !15, i32 2} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !18} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !17, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
-!4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!3 = metadata !{i32 786449, metadata !18, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !19, metadata !19, metadata !17, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
+!4 = metadata !{i32 786453, metadata !18, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{metadata !6, metadata !6}
-!6 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786468, metadata !18, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !7 = metadata !{i32 786689, metadata !8, metadata !"x", metadata !2, i32 6, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ]
-!8 = metadata !{i32 786478, metadata !2, metadata !"bar", metadata !"bar", metadata !"bar", metadata !2, i32 6, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32)* @bar, null, null, metadata !16, i32 6} ; [ DW_TAG_subprogram ]
+!8 = metadata !{i32 786478, metadata !18, metadata !2, metadata !"bar", metadata !"bar", metadata !"bar", i32 6, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32)* @bar, null, null, metadata !16, i32 6} ; [ DW_TAG_subprogram ]
 !9 = metadata !{i32 3, i32 0, metadata !10, null}
-!10 = metadata !{i32 786443, metadata !2, metadata !1, i32 2, i32 0} ; [ DW_TAG_lexical_block ]
+!10 = metadata !{i32 786443, metadata !18, metadata !1, i32 2, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !11 = metadata !{i32 1}
 !12 = metadata !{i32 3, i32 0, metadata !10, metadata !13}
 !13 = metadata !{i32 7, i32 0, metadata !14, null}
-!14 = metadata !{i32 786443, metadata !2, metadata !8, i32 6, i32 0} ; [ DW_TAG_lexical_block ]
+!14 = metadata !{i32 786443, metadata !18, metadata !8, i32 6, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !15 = metadata !{metadata !0}
 !16 = metadata !{metadata !7}
 !17 = metadata !{metadata !1, metadata !8}
 !18 = metadata !{metadata !"f.c", metadata !"/tmp"}
+!19 = metadata !{i32 0}
 
 ;CHECK: DEBUG_VALUE: bar:x <- E
 ;CHECK: Ltmp
-;CHECK:	DEBUG_VALUE: foo:y <- 1+0
+;CHECK:	DEBUG_VALUE: foo:y <- 1{{$}}
diff --git a/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll b/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll
index b764b0b..1571a58 100644
--- a/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll
+++ b/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll
@@ -8,7 +8,7 @@ target triple = "x86_64-apple-darwin10.2"
 @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (%struct.foo*, i32)* @_ZN3foo3bazEi to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
 
 define i32 @_ZN3foo3bazEi(%struct.foo* nocapture %this, i32 %x) nounwind readnone optsize noinline ssp align 2 {
-;CHECK: DEBUG_VALUE: baz:this <- RDI+0
+;CHECK: DEBUG_VALUE: baz:this <- RDI{{$}}
 entry:
   tail call void @llvm.dbg.value(metadata !{%struct.foo* %this}, i64 0, metadata !15)
   tail call void @llvm.dbg.value(metadata !{i32 %x}, i64 0, metadata !16)
@@ -19,37 +19,40 @@ entry:
 
 declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
+!llvm.dbg.cu = !{!4}
 !llvm.dbg.lv = !{!0, !14, !15, !16, !17, !24, !25, !28}
 
 !0 = metadata !{i32 786689, metadata !1, metadata !"this", metadata !3, i32 11, metadata !12, i32 0, null} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 786478, metadata !3, metadata !2, metadata !"bar", metadata !"bar", metadata !"_ZN3foo3barEi", i32 11, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, i32 (%struct.foo*, i32)* @_ZN3foo3bazEi, null, null, null, i32 11} ; [ DW_TAG_subprogram ]
-!2 = metadata !{i32 786451, metadata !3, metadata !"foo", metadata !3, i32 3, i64 32, i64 32, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_structure_type ]
+!1 = metadata !{i32 786478, metadata !31, metadata !2, metadata !"bar", metadata !"bar", metadata !"_ZN3foo3barEi", i32 11, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, i32 (%struct.foo*, i32)* @_ZN3foo3bazEi, null, null, null, i32 11} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 786451, metadata !31, metadata !3, metadata !"foo", i32 3, i64 32, i64 32, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_structure_type ]
 !3 = metadata !{i32 786473, metadata !31} ; [ DW_TAG_file_type ]
-!4 = metadata !{i32 786449, i32 0, i32 4, metadata !"foo.cp", metadata !"/tmp/", metadata !"4.2.1 LLVM build", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
+!4 = metadata !{i32 786449, metadata !31, i32 4, metadata !"4.2.1 LLVM build", i1 true, metadata !"", i32 0, metadata !32, metadata !32, metadata !33, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !5 = metadata !{metadata !6, metadata !1, metadata !8}
-!6 = metadata !{i32 786445, metadata !2, metadata !"y", metadata !3, i32 8, i64 32, i64 32, i64 0, i32 0, metadata !7} ; [ DW_TAG_member ]
-!7 = metadata !{i32 786468, metadata !3, metadata !"int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!8 = metadata !{i32 786478, metadata !3, metadata !2, metadata !"baz", metadata !"baz", metadata !"_ZN3foo3bazEi", i32 15, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, i32 (%struct.foo*, i32)* @_ZN3foo3bazEi, null, null, null, i32 15} ; [ DW_TAG_subprogram ]
-!9 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !10, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!6 = metadata !{i32 786445, metadata !31, metadata !2, metadata !"y", i32 8, i64 32, i64 32, i64 0, i32 0, metadata !7} ; [ DW_TAG_member ]
+!7 = metadata !{i32 786468, metadata !31, metadata !3, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!8 = metadata !{i32 786478, metadata !31, metadata !2, metadata !"baz", metadata !"baz", metadata !"_ZN3foo3bazEi", i32 15, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, i32 (%struct.foo*, i32)* @_ZN3foo3bazEi, null, null, null, i32 15} ; [ DW_TAG_subprogram ]
+!9 = metadata !{i32 786453, metadata !31, metadata !3, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !10, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !10 = metadata !{metadata !7, metadata !11, metadata !7}
-!11 = metadata !{i32 786447, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !2} ; [ DW_TAG_pointer_type ]
-!12 = metadata !{i32 786470, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !13} ; [ DW_TAG_const_type ]
-!13 = metadata !{i32 786447, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_pointer_type ]
+!11 = metadata !{i32 786447, metadata !31, metadata !3, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 64, metadata !2} ; [ DW_TAG_pointer_type ]
+!12 = metadata !{i32 786470, metadata !31, metadata !3, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 64, metadata !13} ; [ DW_TAG_const_type ]
+!13 = metadata !{i32 786447, metadata !31, metadata !3, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_pointer_type ]
 !14 = metadata !{i32 786689, metadata !1, metadata !"x", metadata !3, i32 11, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ]
 !15 = metadata !{i32 786689, metadata !8, metadata !"this", metadata !3, i32 15, metadata !12, i32 0, null} ; [ DW_TAG_arg_variable ]
 !16 = metadata !{i32 786689, metadata !8, metadata !"x", metadata !3, i32 15, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ]
 !17 = metadata !{i32 786689, metadata !18, metadata !"argc", metadata !3, i32 19, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ]
-!18 = metadata !{i32 786478, metadata !3, metadata !3, metadata !"main", metadata !"main", metadata !"main", i32 19, metadata !19, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, null, null, null, null, i32 19} ; [ DW_TAG_subprogram ]
-!19 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !20, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!18 = metadata !{i32 786478, metadata !31, metadata !3, metadata !"main", metadata !"main", metadata !"main", i32 19, metadata !19, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, null, null, null, null, i32 19} ; [ DW_TAG_subprogram ]
+!19 = metadata !{i32 786453, metadata !31, metadata !3, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !20, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !20 = metadata !{metadata !7, metadata !7, metadata !21}
-!21 = metadata !{i32 786447, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !22} ; [ DW_TAG_pointer_type ]
-!22 = metadata !{i32 786447, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ]
-!23 = metadata !{i32 786468, metadata !3, metadata !"char", metadata !3, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!21 = metadata !{i32 786447, metadata !31, metadata !3, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !22} ; [ DW_TAG_pointer_type ]
+!22 = metadata !{i32 786447, metadata !31, metadata !3, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ]
+!23 = metadata !{i32 786468, metadata !31, metadata !3, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !24 = metadata !{i32 786689, metadata !18, metadata !"argv", metadata !3, i32 19, metadata !21, i32 0, null} ; [ DW_TAG_arg_variable ]
 !25 = metadata !{i32 786688, metadata !26, metadata !"a", metadata !3, i32 20, metadata !2, i32 0, null} ; [ DW_TAG_auto_variable ]
-!26 = metadata !{i32 786443, metadata !27, i32 19, i32 0} ; [ DW_TAG_lexical_block ]
-!27 = metadata !{i32 786443, metadata !18, i32 19, i32 0} ; [ DW_TAG_lexical_block ]
+!26 = metadata !{i32 786443, metadata !31, metadata !27, i32 19, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!27 = metadata !{i32 786443, metadata !31, metadata !18, i32 19, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !28 = metadata !{i32 786688, metadata !26, metadata !"b", metadata !3, i32 21, metadata !7, i32 0, null} ; [ DW_TAG_auto_variable ]
 !29 = metadata !{i32 16, i32 0, metadata !30, null}
-!30 = metadata !{i32 786443, metadata !8, i32 15, i32 0} ; [ DW_TAG_lexical_block ]
+!30 = metadata !{i32 786443, metadata !31, metadata !8, i32 15, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !31 = metadata !{metadata !"foo.cp", metadata !"/tmp/"}
+!32 = metadata !{i32 0}
+!33 = metadata !{metadata !1, metadata !8, metadata !18}
diff --git a/test/CodeGen/X86/2010-07-06-DbgCrash.ll b/test/CodeGen/X86/2010-07-06-DbgCrash.ll
index 208e93e..e91cd76 100644
--- a/test/CodeGen/X86/2010-07-06-DbgCrash.ll
+++ b/test/CodeGen/X86/2010-07-06-DbgCrash.ll
@@ -3,21 +3,24 @@
 @.str = private constant [4 x i8] c"one\00", align 1 ; <[4 x i8]*> [#uses=1]
 @.str1 = private constant [4 x i8] c"two\00", align 1 ; <[5 x i8]*> [#uses=1]
 @C.9.2167 = internal constant [2 x i8*] [i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8]* @.str1, i64 0, i64 0)]
-!38 = metadata !{i32 524329, metadata !"pbmsrch.c", metadata !"/Users/grawp/LLVM/test-suite/MultiSource/Benchmarks/MiBench/office-stringsearch", metadata !39} ; [ DW_TAG_file_type ]
-!39 = metadata !{i32 524305, i32 0, i32 1, metadata !"pbmsrch.c", metadata !"/Users/grawp/LLVM/test-suite/MultiSource/Benchmarks/MiBench/office-stringsearch", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!46 = metadata !{i32 524303, metadata !38, metadata !"", metadata !38, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !47} ; [ DW_TAG_pointer_type ]!97 = metadata !{i32 524334, i32 0, metadata !38, metadata !"main", metadata !"main", metadata !"main", metadata !38, i32 73, metadata !98, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]!101 = metadata !{[2 x i8*]* @C.9.2167}
-!47 = metadata !{i32 524324, metadata !38, metadata !"char", metadata !38, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
-!97 = metadata !{i32 524334, i32 0, metadata !38, metadata !"main", metadata !"main", metadata !"main", metadata !38, i32 73, metadata !98, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]
-!98 = metadata !{i32 524309, metadata !38, metadata !"", metadata !38, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !99, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!38 = metadata !{i32 524329, metadata !109} ; [ DW_TAG_file_type ]
+!39 = metadata !{i32 524305, metadata !109, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)", i1 true, metadata !"", i32 0, metadata !108, metadata !108, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!46 = metadata !{i32 524303, metadata !109, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !47} ; [ DW_TAG_pointer_type ]
+!47 = metadata !{i32 524324, metadata !109, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!97 = metadata !{i32 524334, i32 0, metadata !39, metadata !"main", metadata !"main", metadata !"main", i32 73, metadata !98, i1 false, i1 true,
+                i32 0, i32 0, null, i32 0, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!98 = metadata !{i32 524309, metadata !109, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !99, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !99 = metadata !{metadata !100}
-!100 = metadata !{i32 524324, metadata !38, metadata !"int", metadata !38, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!100 = metadata !{i32 524324, metadata !109, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !101 = metadata !{[2 x i8*]* @C.9.2167}
-!102 = metadata !{i32 524544, metadata !103, metadata !"find_strings", metadata !38, i32 75, metadata !104} ; [ DW_TAG_auto_variable ]
-!103 = metadata !{i32 524299, metadata !97, i32 73, i32 0} ; [ DW_TAG_lexical_block ]
-!104 = metadata !{i32 524289, metadata !38, metadata !"", metadata !38, i32 0, i64 85312, i64 64, i64 0, i32 0, metadata !46, metadata !105, i32 0, null} ; [ DW_TAG_array_type ]
+!102 = metadata !{i32 524544, metadata !103, metadata !"find_strings", metadata !38, i32 75, metadata !104, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
+!103 = metadata !{i32 524299, null, metadata !97, i32 73, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!104 = metadata !{i32 524289, metadata !109, null, metadata !"", i32 0, i64 85312, i64 64, i64 0, i32 0, metadata !46, metadata !105, i32 0, null} ; [ DW_TAG_array_type ]
 !105 = metadata !{metadata !106}
 !106 = metadata !{i32 524321, i64 0, i64 1333}    ; [ DW_TAG_subrange_type ]
 !107 = metadata !{i32 73, i32 0, metadata !103, null}
+!108 = metadata !{i32 0}
+!109 = metadata !{metadata !"pbmsrch.c", metadata !"/Users/grawp/LLVM/test-suite/MultiSource/Benchmarks/MiBench/office-stringsearch"}
 
 define i32 @main() nounwind ssp {
 bb.nph:
diff --git a/test/CodeGen/X86/2010-07-29-SetccSimplify.ll b/test/CodeGen/X86/2010-07-29-SetccSimplify.ll
index 96016cf..47e511f 100644
--- a/test/CodeGen/X86/2010-07-29-SetccSimplify.ll
+++ b/test/CodeGen/X86/2010-07-29-SetccSimplify.ll
@@ -9,6 +9,6 @@ entry:
   ret i32 %3
 }
 
-; CHECK: extend2bit_v2:
+; CHECK-LABEL: extend2bit_v2:
 ; CHECK: xorl	%eax, %eax
 ; CHECK-NEXT: ret
diff --git a/test/CodeGen/X86/2010-08-04-StackVariable.ll b/test/CodeGen/X86/2010-08-04-StackVariable.ll
index 91711bb..c6e1654 100644
--- a/test/CodeGen/X86/2010-08-04-StackVariable.ll
+++ b/test/CodeGen/X86/2010-08-04-StackVariable.ll
@@ -77,49 +77,51 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !llvm.dbg.cu = !{!3}
 !46 = metadata !{metadata !0, metadata !9, metadata !16, metadata !17, metadata !20}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", metadata !2, i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 11} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 786451, metadata !2, metadata !"SVal", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ]
-!2 = metadata !{i32 786473, metadata !"small.cc", metadata !"/Users/manav/R8248330", metadata !3} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786449, i32 4, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !46, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786478, metadata !47, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 11} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786451, metadata !47, metadata !2, metadata !"SVal", i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ]
+!2 = metadata !{i32 786473, metadata !47} ; [ DW_TAG_file_type ]
+!3 = metadata !{i32 786449, metadata !47, i32 4, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !48, metadata !48, metadata !46, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
 !4 = metadata !{metadata !5, metadata !7, metadata !0, metadata !9}
-!5 = metadata !{i32 786445, metadata !1, metadata !"Data", metadata !2, i32 7, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ]
-!6 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
-!7 = metadata !{i32 786445, metadata !1, metadata !"Kind", metadata !2, i32 8, i64 32, i64 32, i64 64, i32 0, metadata !8} ; [ DW_TAG_member ]
-!8 = metadata !{i32 786468, metadata !2, metadata !"unsigned int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
-!9 = metadata !{i32 786478, metadata !1, metadata !"~SVal", metadata !"~SVal", metadata !"", metadata !2, i32 12, metadata !10, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 12} ; [ DW_TAG_subprogram ]
-!10 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!5 = metadata !{i32 786445, metadata !47, metadata !1, metadata !"Data", i32 7, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ]
+!6 = metadata !{i32 786447, metadata !47, metadata !2, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
+!7 = metadata !{i32 786445, metadata !47, metadata !1, metadata !"Kind", i32 8, i64 32, i64 32, i64 64, i32 0, metadata !8} ; [ DW_TAG_member ]
+!8 = metadata !{i32 786468, metadata !47, metadata !2, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 786478, metadata !47, metadata !1, metadata !"~SVal", metadata !"~SVal", metadata !"", i32 12, metadata !10, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 12} ; [ DW_TAG_subprogram ]
+!10 = metadata !{i32 786453, metadata !47, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !11 = metadata !{null, metadata !12, metadata !13}
-!12 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ]
-!13 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!14 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!12 = metadata !{i32 786447, metadata !47, metadata !2, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ]
+!13 = metadata !{i32 786468, metadata !47, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!14 = metadata !{i32 786453, metadata !47, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !15 = metadata !{null, metadata !12}
-!16 = metadata !{i32 786478, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"_ZN4SValC1Ev", metadata !2, i32 11, metadata !14, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void (%struct.SVal*)* @_ZN4SValC1Ev, null, null, null, i32 11} ; [ DW_TAG_subprogram ]
-!17 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3fooi4SVal", metadata !2, i32 16, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal, null, null, null, i32 16} ; [ DW_TAG_subprogram ]
-!18 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !19, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!16 = metadata !{i32 786478, metadata !47, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"_ZN4SValC1Ev", i32 11, metadata !14, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void (%struct.SVal*)* @_ZN4SValC1Ev, null, null, null, i32 11} ; [ DW_TAG_subprogram ]
+!17 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3fooi4SVal", i32 16, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal, null, null, null, i32 16} ; [ DW_TAG_subprogram ]
+!18 = metadata !{i32 786453, metadata !47, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !19, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !19 = metadata !{metadata !13, metadata !13, metadata !1}
-!20 = metadata !{i32 786478, metadata !2, metadata !"main", metadata !"main", metadata !"main", metadata !2, i32 23, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main, null, null, null, i32 23} ; [ DW_TAG_subprogram ]
-!21 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!20 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"main", metadata !"main", metadata !"main", i32 23, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main, null, null, null, i32 23} ; [ DW_TAG_subprogram ]
+!21 = metadata !{i32 786453, metadata !47, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !22 = metadata !{metadata !13}
 !23 = metadata !{i32 786689, metadata !17, metadata !"i", metadata !2, i32 16, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ]
 !24 = metadata !{i32 16, i32 0, metadata !17, null}
 !25 = metadata !{i32 786689, metadata !17, metadata !"location", metadata !2, i32 16, metadata !26, i32 0, null} ; [ DW_TAG_arg_variable ]
-!26 = metadata !{i32 786448, metadata !2, metadata !"SVal", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_reference_type ]
+!26 = metadata !{i32 786448, metadata !47, metadata !2, metadata !"SVal", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_reference_type ]
 !27 = metadata !{i32 17, i32 0, metadata !28, null}
-!28 = metadata !{i32 786443, metadata !2, metadata !17, i32 16, i32 0, i32 2} ; [ DW_TAG_lexical_block ]
+!28 = metadata !{i32 786443, metadata !47, metadata !17, i32 16, i32 0, i32 2} ; [ DW_TAG_lexical_block ]
 !29 = metadata !{i32 18, i32 0, metadata !28, null}
 !30 = metadata !{i32 20, i32 0, metadata !28, null}
 !31 = metadata !{i32 786689, metadata !16, metadata !"this", metadata !2, i32 11, metadata !32, i32 0, null} ; [ DW_TAG_arg_variable ]
-!32 = metadata !{i32 786470, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !33} ; [ DW_TAG_const_type ]
-!33 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_pointer_type ]
+!32 = metadata !{i32 786470, metadata !47, metadata !2, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 64, metadata !33} ; [ DW_TAG_const_type ]
+!33 = metadata !{i32 786447, metadata !47, metadata !2, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !1} ; [ DW_TAG_pointer_type ]
 !34 = metadata !{i32 11, i32 0, metadata !16, null}
 !35 = metadata !{i32 11, i32 0, metadata !36, null}
-!36 = metadata !{i32 786443, metadata !2, metadata !37, i32 11, i32 0, i32 1} ; [ DW_TAG_lexical_block ]
-!37 = metadata !{i32 786443, metadata !2, metadata !16, i32 11, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!36 = metadata !{i32 786443, metadata !47, metadata !37, i32 11, i32 0, i32 1} ; [ DW_TAG_lexical_block ]
+!37 = metadata !{i32 786443, metadata !47, metadata !16, i32 11, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !38 = metadata !{i32 786688, metadata !39, metadata !"v", metadata !2, i32 24, metadata !1, i32 0, null} ; [ DW_TAG_auto_variable ]
-!39 = metadata !{i32 786443, metadata !2, metadata !40, i32 23, i32 0, i32 4} ; [ DW_TAG_lexical_block ]
-!40 = metadata !{i32 786443, metadata !2, metadata !20, i32 23, i32 0, i32 3} ; [ DW_TAG_lexical_block ]
+!39 = metadata !{i32 786443, metadata !47, metadata !40, i32 23, i32 0, i32 4} ; [ DW_TAG_lexical_block ]
+!40 = metadata !{i32 786443, metadata !47, metadata !20, i32 23, i32 0, i32 3} ; [ DW_TAG_lexical_block ]
 !41 = metadata !{i32 24, i32 0, metadata !39, null}
 !42 = metadata !{i32 25, i32 0, metadata !39, null}
 !43 = metadata !{i32 26, i32 0, metadata !39, null}
 !44 = metadata !{i32 786688, metadata !39, metadata !"k", metadata !2, i32 26, metadata !13, i32 0, null} ; [ DW_TAG_auto_variable ]
 !45 = metadata !{i32 27, i32 0, metadata !39, null}
+!47 = metadata !{metadata !"small.cc", metadata !"/Users/manav/R8248330"}
+!48 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/2010-09-16-EmptyFilename.ll b/test/CodeGen/X86/2010-09-16-EmptyFilename.ll
index de0d216..831fe66 100644
--- a/test/CodeGen/X86/2010-09-16-EmptyFilename.ll
+++ b/test/CodeGen/X86/2010-09-16-EmptyFilename.ll
@@ -14,19 +14,20 @@ entry:
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 53, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @foo} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !14, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", i32 53, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !14} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, metadata !15, i32 12, metadata !"clang version 2.9 (trunk 114084)", i1 false, metadata !"", i32 0, null, null, metadata !13, null, metadata !""} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null, null, metadata !13, null} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 786449, metadata !15, i32 12, metadata !"clang version 2.9 (trunk 114084)", i1 false, metadata !"", i32 0, metadata !16, metadata !16, metadata !13, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !14, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null, null, metadata !13, null} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 786478, metadata !7, metadata !"bar", metadata !"bar", metadata !"bar", metadata !7, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @bar} ; [ DW_TAG_subprogram ]
+!5 = metadata !{i32 786468, metadata !14, metadata !1, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786478, metadata !15, metadata !7, metadata !"bar", metadata !"bar", metadata !"bar", i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @bar, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !7 = metadata !{i32 786473, metadata !15} ; [ DW_TAG_file_type ]
 !8 = metadata !{i32 53, i32 13, metadata !9, null}
-!9 = metadata !{i32 786443, metadata !0, i32 53, i32 11, metadata !1, i32 0} ; [ DW_TAG_lexical_block ]
+!9 = metadata !{i32 786443, metadata !14, metadata !0, i32 53, i32 11, i32 0} ; [ DW_TAG_lexical_block ]
 !10 = metadata !{i32 4, i32 13, metadata !11, null}
-!11 = metadata !{i32 786443, metadata !12, i32 4, i32 13, metadata !7, i32 2} ; [ DW_TAG_lexical_block ]
-!12 = metadata !{i32 786443, metadata !6, i32 4, i32 11, metadata !7, i32 1} ; [ DW_TAG_lexical_block ]
+!11 = metadata !{i32 786443, metadata !15, metadata !12, i32 4, i32 13, i32 2} ; [ DW_TAG_lexical_block ]
+!12 = metadata !{i32 786443, metadata !15, metadata !6, i32 4, i32 11, i32 1} ; [ DW_TAG_lexical_block ]
 !13 = metadata !{metadata !0, metadata !6}
 !14 = metadata !{metadata !"", metadata !"/private/tmp"}
 !15 = metadata !{metadata !"bug.c", metadata !"/private/tmp"}
+!16 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/2010-11-02-DbgParameter.ll b/test/CodeGen/X86/2010-11-02-DbgParameter.ll
index 8719f73..e118e80 100644
--- a/test/CodeGen/X86/2010-11-02-DbgParameter.ll
+++ b/test/CodeGen/X86/2010-11-02-DbgParameter.ll
@@ -17,21 +17,22 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (%struct.bar*)* @foo, null, null, metadata !16, i32 3} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !17, metadata !1, metadata !"foo", metadata !"foo", metadata !"", i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (%struct.bar*)* @foo, null, null, metadata !16, i32 3} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !17} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 2.9 (trunk 117922)", i1 true, metadata !"", i32 0, null, null, metadata !15, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 786449, metadata !17, i32 12, metadata !"clang version 2.9 (trunk 117922)", i1 true, metadata !"", i32 0, metadata !18, metadata !18, metadata !15, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !17, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 786468, metadata !17, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !6 = metadata !{i32 786689, metadata !0, metadata !"i", metadata !1, i32 3, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ]
-!7 = metadata !{i32 786447, metadata !1, metadata !"", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ]
-!8 = metadata !{i32 786451, metadata !1, metadata !"bar", metadata !1, i32 2, i64 64, i64 32, i64 0, i32 0, null, metadata !9, i32 0, null} ; [ DW_TAG_structure_type ]
+!7 = metadata !{i32 786447, metadata !17, metadata !1, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ]
+!8 = metadata !{i32 786451, metadata !17, metadata !1, metadata !"bar", i32 2, i64 64, i64 32, i64 0, i32 0, null, metadata !9, i32 0, null} ; [ DW_TAG_structure_type ]
 !9 = metadata !{metadata !10, metadata !11}
-!10 = metadata !{i32 786445, metadata !1, metadata !"x", metadata !1, i32 2, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ]
-!11 = metadata !{i32 786445, metadata !1, metadata !"y", metadata !1, i32 2, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ]
+!10 = metadata !{i32 786445, metadata !17,  metadata !1, metadata !"x", i32 2, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ]
+!11 = metadata !{i32 786445, metadata !17, metadata !1, metadata !"y", i32 2, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ]
 !12 = metadata !{i32 3, i32 47, metadata !0, null}
 !13 = metadata !{i32 4, i32 2, metadata !14, null}
-!14 = metadata !{i32 786443, metadata !0, i32 3, i32 50, metadata !1, i32 0} ; [ DW_TAG_lexical_block ]
+!14 = metadata !{i32 786443, metadata !17, metadata !0, i32 3, i32 50, i32 0} ; [ DW_TAG_lexical_block ]
 !15 = metadata !{metadata !0}
 !16 = metadata !{metadata !6}
 !17 = metadata !{metadata !"one.c", metadata !"/private/tmp"}
+!18 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/2010-12-02-MC-Set.ll b/test/CodeGen/X86/2010-12-02-MC-Set.ll
index 4d8d974..1a4c586 100644
--- a/test/CodeGen/X86/2010-12-02-MC-Set.ll
+++ b/test/CodeGen/X86/2010-12-02-MC-Set.ll
@@ -9,13 +9,15 @@ entry:
 !llvm.dbg.cu = !{!2}
 !7 = metadata !{metadata !0}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 786473, metadata !"e.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 2.9 (trunk 120563)", i1 false, metadata !"", i32 0, null, null, metadata !7, null, metadata !""} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 786478, metadata !9, metadata !1, metadata !"foo", metadata !"foo", metadata !"", i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786473, metadata !9} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 786449, metadata !9, i32 12, metadata !"clang version 2.9 (trunk 120563)", i1 false, metadata !"", i32 0, metadata !8, metadata !8, metadata !7, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !9, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{null}
 !5 = metadata !{i32 5, i32 1, metadata !6, null}
-!6 = metadata !{i32 786443, metadata !0, i32 3, i32 16, metadata !1, i32 0} ; [ DW_TAG_lexical_block ]
+!6 = metadata !{i32 786443, metadata !9, metadata !0, i32 3, i32 16, i32 0} ; [ DW_TAG_lexical_block ]
+!8 = metadata !{i32 0}
+!9 = metadata !{metadata !"e.c", metadata !"/private/tmp"}
 
 ; CHECK: .subsections_via_symbols
 ; CHECK-NEXT: __debug_line
diff --git a/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll b/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll
index 14fb3e4..3e0fbca 100644
--- a/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll
+++ b/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll
@@ -71,29 +71,29 @@ declare i32 @puts(i8* nocapture) nounwind
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"gcd", metadata !"gcd", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i64 (i64, i64)* @gcd, null, null, metadata !29, i32 0} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !31, metadata !1, metadata !"gcd", metadata !"gcd", metadata !"", i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i64 (i64, i64)* @gcd, null, null, metadata !29, i32 0} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !31} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, metadata !31, i32 12, metadata !"clang version 2.9 (trunk 124117)", i1 true, metadata !"", i32 0, null, null, metadata !28, null,  null, null} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 786449, metadata !31, i32 12, metadata !"clang version 2.9 (trunk 124117)", i1 true, metadata !"", i32 0, metadata !32, metadata !32, metadata !28, null,  null, null} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !31, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
 !5 = metadata !{i32 786468, null, metadata !2, metadata !"long int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 25, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @main, null, null, metadata !30, i32 0} ; [ DW_TAG_subprogram ]
-!7 = metadata !{i32 786453, metadata !1, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!6 = metadata !{i32 786478, metadata !31, metadata !1, metadata !"main", metadata !"main", metadata !"", i32 25, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @main, null, null, metadata !30, i32 0} ; [ DW_TAG_subprogram ]
+!7 = metadata !{i32 786453, metadata !31, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{metadata !9}
 !9 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !10 = metadata !{i32 786689, metadata !0, metadata !"a", metadata !1, i32 5, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !11 = metadata !{i32 786689, metadata !0, metadata !"b", metadata !1, i32 5, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !12 = metadata !{i32 786688, metadata !13, metadata !"c", metadata !1, i32 6, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!13 = metadata !{i32 786443, metadata !1, metadata !0, i32 5, i32 52, i32 0} ; [ DW_TAG_lexical_block ]
+!13 = metadata !{i32 786443, metadata !31, metadata !0, i32 5, i32 52, i32 0} ; [ DW_TAG_lexical_block ]
 !14 = metadata !{i32 786688, metadata !15, metadata !"m", metadata !1, i32 26, metadata !16, i32 0, null} ; [ DW_TAG_auto_variable ]
-!15 = metadata !{i32 786443, metadata !1, metadata !6, i32 25, i32 12, i32 2} ; [ DW_TAG_lexical_block ]
+!15 = metadata !{i32 786443, metadata !31, metadata !6, i32 25, i32 12, i32 2} ; [ DW_TAG_lexical_block ]
 !16 = metadata !{i32 786468, null, metadata !2, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
 !17 = metadata !{i32 786688, metadata !15, metadata !"z_s", metadata !1, i32 27, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ]
 !18 = metadata !{i32 5, i32 41, metadata !0, null}
 !19 = metadata !{i32 5, i32 49, metadata !0, null}
 !20 = metadata !{i32 7, i32 5, metadata !13, null}
 !21 = metadata !{i32 8, i32 9, metadata !22, null}
-!22 = metadata !{i32 786443, metadata !1, metadata !13, i32 7, i32 14, i32 1} ; [ DW_TAG_lexical_block ]
+!22 = metadata !{i32 786443, metadata !31, metadata !13, i32 7, i32 14, i32 1} ; [ DW_TAG_lexical_block ]
 !23 = metadata !{i32 9, i32 9, metadata !22, null}
 !24 = metadata !{i32 26, i32 38, metadata !15, null}
 !25 = metadata !{i32 27, i32 38, metadata !15, null}
@@ -103,3 +103,4 @@ declare i32 @puts(i8* nocapture) nounwind
 !29 = metadata !{metadata !10, metadata !11, metadata !12}
 !30 = metadata !{metadata !14, metadata !17}
 !31 = metadata !{metadata !"rem_small.c", metadata !"/private/tmp"}
+!32 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/2011-04-19-sclr-bb.ll b/test/CodeGen/X86/2011-04-19-sclr-bb.ll
index 771e4b3..b77cc40 100644
--- a/test/CodeGen/X86/2011-04-19-sclr-bb.ll
+++ b/test/CodeGen/X86/2011-04-19-sclr-bb.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s
 
 ; Make sure that values of illegal types are not scalarized between basic blocks.
-;CHECK: test
+;CHECK-LABEL: test:
 ;CHECK-NOT: pinsrw
 ;CHECK-NOT: pextrb
 ;CHECK: ret
diff --git a/test/CodeGen/X86/2011-05-09-loaduse.ll b/test/CodeGen/X86/2011-05-09-loaduse.ll
index 8673d74..adcea5c 100644
--- a/test/CodeGen/X86/2011-05-09-loaduse.ll
+++ b/test/CodeGen/X86/2011-05-09-loaduse.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
 
-;CHECK: test
+;CHECK-LABEL: test:
 ;CHECK-not: pshufd
 ;CHECK: ret
 define float @test(<4 x float>* %A) nounwind {
diff --git a/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll b/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll
index 7632034..aea53b3 100644
--- a/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll
+++ b/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll
@@ -16,5 +16,5 @@ entry:
   %tmp10 = sext i8 %tmp9 to i32
   ret i32 %tmp10
 }
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: movsbl	-2147483647
diff --git a/test/CodeGen/X86/2011-10-18-FastISel-VectorParams.ll b/test/CodeGen/X86/2011-10-18-FastISel-VectorParams.ll
index 8c09d97..e7d1e19 100644
--- a/test/CodeGen/X86/2011-10-18-FastISel-VectorParams.ll
+++ b/test/CodeGen/X86/2011-10-18-FastISel-VectorParams.ll
@@ -20,7 +20,7 @@ entry:
   %2 = load <4 x float>* %p3, align 16
   %3 = load <4 x float>* %p4, align 16
   %4 = load <4 x float>* %p5, align 16
-; CHECK:      movaps {{%xmm[0-7]}}, (%esp)
+; CHECK:      movups {{%xmm[0-7]}}, (%esp)
 ; CHECK-NEXT: calll _dovectortest 
   call void @dovectortest(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3, <4 x float> %4)
   ret void
diff --git a/test/CodeGen/X86/2011-10-27-tstore.ll b/test/CodeGen/X86/2011-10-27-tstore.ll
index 6e83f67..6dea92b 100644
--- a/test/CodeGen/X86/2011-10-27-tstore.ll
+++ b/test/CodeGen/X86/2011-10-27-tstore.ll
@@ -2,7 +2,7 @@
 
 target triple = "x86_64-unknown-linux-gnu"
 
-;CHECK: ltstore
+;CHECK-LABEL: ltstore:
 ;CHECK: movq
 ;CHECK: movq
 ;CHECK: ret
diff --git a/test/CodeGen/X86/2011-10-30-padd.ll b/test/CodeGen/X86/2011-10-30-padd.ll
index 180ca15..1b8c12b 100644
--- a/test/CodeGen/X86/2011-10-30-padd.ll
+++ b/test/CodeGen/X86/2011-10-30-padd.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s
 
-;CHECK: addXX_test
+;CHECK-LABEL: addXX_test:
 ;CHECK: padd
 ;CHECK: ret
 
@@ -10,7 +10,7 @@ define <16 x i8> @addXX_test(<16 x i8> %a) {
       ret <16 x i8> %b
 }
 
-;CHECK: instcombine_test
+;CHECK-LABEL: instcombine_test:
 ;CHECK: padd
 ;CHECK: ret
 define <16 x i8> @instcombine_test(<16 x i8> %a) {
diff --git a/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll b/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll
index fcaabdd..df9823a 100644
--- a/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll
+++ b/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll
@@ -2,7 +2,7 @@
 ; PR11494
 
 define void @test(<4 x i32>* nocapture %p) nounwind {
-  ; CHECK: test:
+  ; CHECK-LABEL: test:
   ; CHECK: vpxor %xmm0, %xmm0, %xmm0
   ; CHECK-NEXT: vpmaxsd {{.*}}, %xmm0, %xmm0
   ; CHECK-NEXT: vmovdqu	%xmm0, (%rdi)
diff --git a/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll b/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll
index 39c213f..7515e80 100644
--- a/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll
+++ b/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll
@@ -5,7 +5,7 @@
 ; the chains correctly.
 ; PR10747
 
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: pextrd $2, %xmm
 define <4 x i32> @test(<4 x i32>* %p) {
   %v = load <4 x i32>* %p
diff --git a/test/CodeGen/X86/2011-20-21-zext-ui2fp.ll b/test/CodeGen/X86/2011-20-21-zext-ui2fp.ll
index 75efcf5..78cdfcf 100644
--- a/test/CodeGen/X86/2011-20-21-zext-ui2fp.ll
+++ b/test/CodeGen/X86/2011-20-21-zext-ui2fp.ll
@@ -5,7 +5,7 @@ target triple = "x86_64-unknown-linux-gnu"
 ; 0x1 means that we only look at the first bit.
 
 ;CHECK: 0x1
-;CHECK: ui_to_fp_conv
+;CHECK-LABEL: ui_to_fp_conv:
 ;CHECK: ret
 define void @ui_to_fp_conv(<8 x float> * nocapture %aFOO, <8 x float>* nocapture %RET) nounwind {
 allocas:
diff --git a/test/CodeGen/X86/2012-01-11-split-cv.ll b/test/CodeGen/X86/2012-01-11-split-cv.ll
index 7e91498..69d4b93 100644
--- a/test/CodeGen/X86/2012-01-11-split-cv.ll
+++ b/test/CodeGen/X86/2012-01-11-split-cv.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86 -mcpu=corei7-avx -mattr=+avx -mtriple=i686-pc-win32 | FileCheck %s
 
-;CHECK: add18i16
+;CHECK-LABEL: add18i16:
 define void @add18i16(<18 x i16>* nocapture sret %ret, <18 x i16>* %bp) nounwind {
 ;CHECK: vmovaps
   %b = load <18 x i16>* %bp, align 16
diff --git a/test/CodeGen/X86/2012-01-18-vbitcast.ll b/test/CodeGen/X86/2012-01-18-vbitcast.ll
index 3ce7db6..9eb59e4 100644
--- a/test/CodeGen/X86/2012-01-18-vbitcast.ll
+++ b/test/CodeGen/X86/2012-01-18-vbitcast.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-pc-win32 | FileCheck %s
 
-;CHECK: vcast
+;CHECK-LABEL: vcast:
 define <2 x i32> @vcast(<2 x float> %a, <2 x float> %b) {
 ;CHECK: pmovzxdq
 ;CHECK: pmovzxdq
diff --git a/test/CodeGen/X86/2012-02-20-MachineCPBug.ll b/test/CodeGen/X86/2012-02-20-MachineCPBug.ll
deleted file mode 100644
index 477b4de..0000000
--- a/test/CodeGen/X86/2012-02-20-MachineCPBug.ll
+++ /dev/null
@@ -1,78 +0,0 @@
-; RUN: llc < %s -mtriple=i386-apple-macosx -mcpu=core2 -mattr=+sse | FileCheck %s
-; PR11940: Do not optimize away movb %al, %ch
-
-%struct.APInt = type { i64* }
-
-declare noalias i8* @calloc(i32, i32) nounwind
-
-define void @bug(%struct.APInt* noalias nocapture sret %agg.result, %struct.APInt* nocapture %this, i32 %rotateAmt) nounwind align 2 {
-entry:
-; CHECK: bug:
-  %call = tail call i8* @calloc(i32 1, i32 32)
-  %call.i = tail call i8* @calloc(i32 1, i32 32) nounwind
-  %0 = bitcast i8* %call.i to i64*
-  %rem.i = and i32 %rotateAmt, 63
-  %div.i = lshr i32 %rotateAmt, 6
-  %cmp.i = icmp eq i32 %rem.i, 0
-  br i1 %cmp.i, label %for.cond.preheader.i, label %if.end.i
-
-for.cond.preheader.i:                             ; preds = %entry
-  %sub.i = sub i32 4, %div.i
-  %cmp23.i = icmp eq i32 %div.i, 4
-  br i1 %cmp23.i, label %for.body9.lr.ph.i, label %for.body.lr.ph.i
-
-for.body.lr.ph.i:                                 ; preds = %for.cond.preheader.i
-  %pVal.i = getelementptr inbounds %struct.APInt* %this, i32 0, i32 0
-  %.pre5.i = load i64** %pVal.i, align 4
-  br label %for.body.i
-
-for.body.i:                                       ; preds = %for.body.i, %for.body.lr.ph.i
-  %i.04.i = phi i32 [ 0, %for.body.lr.ph.i ], [ %inc.i, %for.body.i ]
-  %add.i = add i32 %i.04.i, %div.i
-  %arrayidx.i = getelementptr inbounds i64* %.pre5.i, i32 %add.i
-  %1 = load i64* %arrayidx.i, align 4
-  %arrayidx3.i = getelementptr inbounds i64* %0, i32 %i.04.i
-  store i64 %1, i64* %arrayidx3.i, align 4
-  %inc.i = add i32 %i.04.i, 1
-  %cmp2.i = icmp ult i32 %inc.i, %sub.i
-  br i1 %cmp2.i, label %for.body.i, label %if.end.i
-
-if.end.i:                                         ; preds = %for.body.i, %entry
-  %cmp81.i = icmp eq i32 %div.i, 3
-  br i1 %cmp81.i, label %_ZNK5APInt4lshrEj.exit, label %for.body9.lr.ph.i
-
-for.body9.lr.ph.i:                                ; preds = %if.end.i, %for.cond.preheader.i
-  %sub58.i = sub i32 3, %div.i
-  %pVal11.i = getelementptr inbounds %struct.APInt* %this, i32 0, i32 0
-  %sh_prom.i = zext i32 %rem.i to i64
-  %sub17.i = sub i32 64, %rem.i
-  %sh_prom18.i = zext i32 %sub17.i to i64
-  %.pre.i = load i64** %pVal11.i, align 4
-  br label %for.body9.i
-
-for.body9.i:                                      ; preds = %for.body9.i, %for.body9.lr.ph.i
-; CHECK: %for.body9.i
-; CHECK: movb
-; CHECK: shrdl
-  %i6.02.i = phi i32 [ 0, %for.body9.lr.ph.i ], [ %inc21.i, %for.body9.i ]
-  %add10.i = add i32 %i6.02.i, %div.i
-  %arrayidx12.i = getelementptr inbounds i64* %.pre.i, i32 %add10.i
-  %2 = load i64* %arrayidx12.i, align 4
-  %shr.i = lshr i64 %2, %sh_prom.i
-  %add14.i = add i32 %add10.i, 1
-  %arrayidx16.i = getelementptr inbounds i64* %.pre.i, i32 %add14.i
-  %3 = load i64* %arrayidx16.i, align 4
-  %shl.i = shl i64 %3, %sh_prom18.i
-  %or.i = or i64 %shl.i, %shr.i
-  %arrayidx19.i = getelementptr inbounds i64* %0, i32 %i6.02.i
-  store i64 %or.i, i64* %arrayidx19.i, align 4
-  %inc21.i = add i32 %i6.02.i, 1
-  %cmp8.i = icmp ult i32 %inc21.i, %sub58.i
-  br i1 %cmp8.i, label %for.body9.i, label %_ZNK5APInt4lshrEj.exit
-
-_ZNK5APInt4lshrEj.exit:                           ; preds = %for.body9.i, %if.end.i
-  %call.i1 = tail call i8* @calloc(i32 1, i32 32) nounwind
-  %4 = getelementptr inbounds %struct.APInt* %agg.result, i32 0, i32 0
-  store i64* %0, i64** %4, align 4
-  ret void
-}
diff --git a/test/CodeGen/X86/2012-04-26-sdglue.ll b/test/CodeGen/X86/2012-04-26-sdglue.ll
index 0465952..186fafb 100644
--- a/test/CodeGen/X86/2012-04-26-sdglue.ll
+++ b/test/CodeGen/X86/2012-04-26-sdglue.ll
@@ -4,7 +4,7 @@
 
 ; It's hard to test for the ISEL condition because CodeGen optimizes
 ; away the bugpointed code. Just ensure the basics are still there.
-;CHECK: func:
+;CHECK-LABEL: func:
 ;CHECK: vxorps
 ;CHECK: vinsertf128
 ;CHECK: vpshufd
diff --git a/test/CodeGen/X86/2012-05-17-TwoAddressBug.ll b/test/CodeGen/X86/2012-05-17-TwoAddressBug.ll
index 171c3f1..881fa37 100644
--- a/test/CodeGen/X86/2012-05-17-TwoAddressBug.ll
+++ b/test/CodeGen/X86/2012-05-17-TwoAddressBug.ll
@@ -6,7 +6,7 @@
 ; rdar://11472010
 define i32 @t(i32 %mask) nounwind readnone ssp {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK-NOT: mov
   %sub = add i32 %mask, -65535
   %shr = lshr i32 %sub, 23
diff --git a/test/CodeGen/X86/2012-07-10-extload64.ll b/test/CodeGen/X86/2012-07-10-extload64.ll
index 4abdded..7233027 100644
--- a/test/CodeGen/X86/2012-07-10-extload64.ll
+++ b/test/CodeGen/X86/2012-07-10-extload64.ll
@@ -13,7 +13,7 @@ entry:
 }
 
 ; Make sure that we store a 64bit value, even on 32bit systems.
-;CHECK: store_64
+;CHECK-LABEL: store_64:
 define void @store_64(<2 x i32>* %ptr) {
 BB:
   store <2 x i32> zeroinitializer, <2 x i32>* %ptr
@@ -22,7 +22,7 @@ BB:
 ;CHECK: ret
 }
 
-;CHECK: load_64
+;CHECK-LABEL: load_64:
 define <2 x i32> @load_64(<2 x i32>* %ptr) {
 BB:
   %t = load <2 x i32>* %ptr
diff --git a/test/CodeGen/X86/2012-07-15-broadcastfold.ll b/test/CodeGen/X86/2012-07-15-broadcastfold.ll
index 2c7dfc8..1c39c74 100644
--- a/test/CodeGen/X86/2012-07-15-broadcastfold.ll
+++ b/test/CodeGen/X86/2012-07-15-broadcastfold.ll
@@ -2,7 +2,7 @@
 
 declare x86_fastcallcc i64 @barrier()
 
-;CHECK: bcast_fold
+;CHECK-LABEL: bcast_fold:
 ;CHECK: vmov{{[au]}}ps %xmm{{[0-9]+}}, [[SPILLED:[^\)]+\)]]
 ;CHECK: barrier
 ;CHECK: vbroadcastss [[SPILLED]], %ymm0
diff --git a/test/CodeGen/X86/2012-08-07-CmpISelBug.ll b/test/CodeGen/X86/2012-08-07-CmpISelBug.ll
index 000b853..eba970e 100644
--- a/test/CodeGen/X86/2012-08-07-CmpISelBug.ll
+++ b/test/CodeGen/X86/2012-08-07-CmpISelBug.ll
@@ -6,7 +6,7 @@
 
 define void @foo(i8 %arg4, i32 %arg5, i32* %arg14) nounwind {
 bb:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NOT: testl
 ; CHECK: testb
   %tmp48 = zext i8 %arg4 to i32
diff --git a/test/CodeGen/X86/2012-08-16-setcc.ll b/test/CodeGen/X86/2012-08-16-setcc.ll
index ed51156..c03b923 100644
--- a/test/CodeGen/X86/2012-08-16-setcc.ll
+++ b/test/CodeGen/X86/2012-08-16-setcc.ll
@@ -2,7 +2,7 @@
 
 ; rdar://12081007
 
-; CHECK: and_1:
+; CHECK-LABEL: and_1:
 ; CHECK: andb
 ; CHECK-NEXT: cmovnel
 ; CHECK: ret
@@ -13,7 +13,7 @@ define i32 @and_1(i8 zeroext %a, i8 zeroext %b, i32 %x) {
   ret i32 %3
 }
 
-; CHECK: and_2:
+; CHECK-LABEL: and_2:
 ; CHECK: andb
 ; CHECK-NEXT: setne
 ; CHECK: ret
@@ -23,7 +23,7 @@ define zeroext i1 @and_2(i8 zeroext %a, i8 zeroext %b) {
   ret i1 %2
 }
 
-; CHECK: xor_1:
+; CHECK-LABEL: xor_1:
 ; CHECK: xorb
 ; CHECK-NEXT: cmovnel
 ; CHECK: ret
@@ -34,7 +34,7 @@ define i32 @xor_1(i8 zeroext %a, i8 zeroext %b, i32 %x) {
   ret i32 %3
 }
 
-; CHECK: xor_2:
+; CHECK-LABEL: xor_2:
 ; CHECK: xorb
 ; CHECK-NEXT: setne
 ; CHECK: ret
diff --git a/test/CodeGen/X86/2012-08-17-legalizer-crash.ll b/test/CodeGen/X86/2012-08-17-legalizer-crash.ll
index cb9fa2e..971e56d 100644
--- a/test/CodeGen/X86/2012-08-17-legalizer-crash.ll
+++ b/test/CodeGen/X86/2012-08-17-legalizer-crash.ll
@@ -25,7 +25,7 @@ if.then:                                          ; preds = %entry
 if.end:                                           ; preds = %if.then, %entry
   ret void
 
-; CHECK: fn1:
+; CHECK-LABEL: fn1:
 ; CHECK: shrq $32, [[REG:%.*]]
 ; CHECK: je
 }
diff --git a/test/CodeGen/X86/2012-1-10-buildvector.ll b/test/CodeGen/X86/2012-1-10-buildvector.ll
index ff6be36..a5f64c5 100644
--- a/test/CodeGen/X86/2012-1-10-buildvector.ll
+++ b/test/CodeGen/X86/2012-1-10-buildvector.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"
 target triple = "i686-pc-win32"
 
-;CHECK: bad_cast
+;CHECK-LABEL: bad_cast:
 define void @bad_cast() {
 entry:
   %vext.i = shufflevector <2 x i64> undef, <2 x i64> undef, <3 x i32> <i32 0, i32 1, i32 undef>
@@ -14,7 +14,7 @@ entry:
 }
 
 
-;CHECK: bad_insert
+;CHECK-LABEL: bad_insert:
 define void @bad_insert(i32 %t) {
 entry:
 ;CHECK: vpinsrd
diff --git a/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll b/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll
index 9164eb9..503aab4 100644
--- a/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll
+++ b/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll
@@ -37,7 +37,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"MultiSource/Benchmarks/Olden/bh/newbh.c", metadata !"MultiSource/Benchmarks/Olden/bh", metadata !"clang version 3.3 (trunk 168918) (llvm/trunk 168920)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3} ; [ DW_TAG_compile_unit ] [MultiSource/Benchmarks/Olden/bh/newbh.c] [DW_LANG_C99]
+!0 = metadata !{i32 786449, metadata !11, i32 12, metadata !"clang version 3.3 (trunk 168918) (llvm/trunk 168920)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !2, metadata !3, null, metadata !""} ; [ DW_TAG_compile_unit ] [MultiSource/Benchmarks/Olden/bh/newbh.c] [DW_LANG_C99]
 !1 = metadata !{metadata !2}
 !2 = metadata !{i32 0}
 !3 = metadata !{null}
diff --git a/test/CodeGen/X86/2012-11-30-misched-dbg.ll b/test/CodeGen/X86/2012-11-30-misched-dbg.ll
index a0fbbb2..21e105d 100644
--- a/test/CodeGen/X86/2012-11-30-misched-dbg.ll
+++ b/test/CodeGen/X86/2012-11-30-misched-dbg.ll
@@ -64,7 +64,7 @@ declare i32 @__sprintf_chk(i8*, i32, i64, i8*, ...)
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c", metadata !"MultiSource/Benchmarks/MiBench/consumer-typeset", metadata !"clang version 3.3 (trunk 168918) (llvm/trunk 168920)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ] [MultiSource/Benchmarks/MiBench/consumer-typeset/MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] [DW_LANG_C99]
+!0 = metadata !{i32 786449, metadata !19, i32 12, metadata !"clang version 3.3 (trunk 168918) (llvm/trunk 168920)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, null, metadata !""} ; [ DW_TAG_compile_unit ] [MultiSource/Benchmarks/MiBench/consumer-typeset/MultiSource/Benchmarks/MiBench/consumer-typeset/z19.c] [DW_LANG_C99]
 !1 = metadata !{metadata !2}
 !2 = metadata !{i32 0}
 !3 = metadata !{}
@@ -129,7 +129,7 @@ declare void @_Znwm()
 
 !llvm.dbg.cu = !{!30}
 
-!30 = metadata !{i32 786449, i32 0, i32 4, metadata !"SingleSource/Benchmarks/Shootout-C++/hash.cpp", metadata !"SingleSource/Benchmarks/Shootout-C++", metadata !"clang version 3.3 (trunk 169129) (llvm/trunk 169135)", i1 true, i1 true, metadata !"", i32 0, null, null, null, null} ; [ DW_TAG_compile_unit ] [SingleSource/Benchmarks/Shootout-C++/hash.cpp] [DW_LANG_C_plus_plus]
+!30 = metadata !{i32 786449, metadata !34, i32 4, metadata !"clang version 3.3 (trunk 169129) (llvm/trunk 169135)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ] [SingleSource/Benchmarks/Shootout-C++/hash.cpp] [DW_LANG_C_plus_plus]
 !31 = metadata !{i32 786688, null, metadata !"X", null, i32 29, metadata !32, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [X] [line 29]
 !32 = metadata !{i32 786454, metadata !34, null, metadata !"HM", i32 28, i64 0, i64 0, i64 0, i32 0, null} ; [ DW_TAG_typedef ] [HM] [line 28, size 0, align 0, offset 0] [from ]
 !33 = metadata !{i32 786473, metadata !34} ; [ DW_TAG_file_type ]
diff --git a/test/CodeGen/X86/2012-11-30-regpres-dbg.ll b/test/CodeGen/X86/2012-11-30-regpres-dbg.ll
index df93c56..dcbe109 100644
--- a/test/CodeGen/X86/2012-11-30-regpres-dbg.ll
+++ b/test/CodeGen/X86/2012-11-30-regpres-dbg.ll
@@ -35,10 +35,10 @@ invoke.cont44:                                    ; preds = %if.end
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp", metadata !"MultiSource/Benchmarks/Bullet", metadata !"clang version 3.3 (trunk 168984) (llvm/trunk 168983)", i1 true, i1 true, metadata !"", i32 0, metadata !1, null, null, null} ; [ DW_TAG_compile_unit ] [MultiSource/Benchmarks/Bullet/MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp] [DW_LANG_C_plus_plus]
-!1 = metadata !{metadata !2}
-!2 = metadata !{null, null}
+!0 = metadata !{i32 786449, metadata !6, i32 4, metadata !"clang version 3.3 (trunk 168984) (llvm/trunk 168983)", i1 true, metadata !"", i32 0, metadata !2, metadata !7, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ] [MultiSource/Benchmarks/Bullet/MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp] [DW_LANG_C_plus_plus]
+!2 = metadata !{null}
 !3 = metadata !{i32 786688, null, metadata !"callback", null, i32 214, metadata !4, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [callback] [line 214]
 !4 = metadata !{i32 786451, metadata !6, null, metadata !"btCompoundLeafCallback", i32 90, i64 512, i64 64, i32 0, i32 0, null, null, i32 0, null, null} ; [ DW_TAG_structure_type ] [btCompoundLeafCallback] [line 90, size 512, align 64, offset 0] [from ]
 !5 = metadata !{i32 786473, metadata !6} ; [ DW_TAG_file_type ]
 !6 = metadata !{metadata !"MultiSource/Benchmarks/Bullet/btCompoundCollisionAlgorithm.cpp", metadata !"MultiSource/Benchmarks/Bullet"}
+!7 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/3addr-16bit.ll b/test/CodeGen/X86/3addr-16bit.ll
index c51247a..77c3c16 100644
--- a/test/CodeGen/X86/3addr-16bit.ll
+++ b/test/CodeGen/X86/3addr-16bit.ll
@@ -5,12 +5,12 @@
 
 define zeroext i16 @t1(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
-; 32BIT:     t1:
+; 32BIT-LABEL:     t1:
 ; 32BIT:     movw 20(%esp), %ax
 ; 32BIT-NOT: movw %ax, %cx
 ; 32BIT:     leal 1(%eax), %ecx
 
-; 64BIT:     t1:
+; 64BIT-LABEL:     t1:
 ; 64BIT-NOT: movw %si, %ax
 ; 64BIT:     leal 1(%rsi), %eax
   %0 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
@@ -27,12 +27,12 @@ bb1:                                              ; preds = %entry
 
 define zeroext i16 @t2(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
-; 32BIT:     t2:
+; 32BIT-LABEL:     t2:
 ; 32BIT:     movw 20(%esp), %ax
 ; 32BIT-NOT: movw %ax, %cx
 ; 32BIT:     leal -1(%eax), %ecx
 
-; 64BIT:     t2:
+; 64BIT-LABEL:     t2:
 ; 64BIT-NOT: movw %si, %ax
 ; 64BIT:     leal -1(%rsi), %eax
   %0 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
@@ -51,12 +51,12 @@ declare void @foo(i16 zeroext)
 
 define zeroext i16 @t3(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
-; 32BIT:     t3:
+; 32BIT-LABEL:     t3:
 ; 32BIT:     movw 20(%esp), %ax
 ; 32BIT-NOT: movw %ax, %cx
 ; 32BIT:     leal 2(%eax), %ecx
 
-; 64BIT:     t3:
+; 64BIT-LABEL:     t3:
 ; 64BIT-NOT: movw %si, %ax
 ; 64BIT:     leal 2(%rsi), %eax
   %0 = add i16 %k, 2                              ; <i16> [#uses=3]
@@ -73,13 +73,13 @@ bb1:                                              ; preds = %entry
 
 define zeroext i16 @t4(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
 entry:
-; 32BIT:     t4:
+; 32BIT-LABEL:     t4:
 ; 32BIT:     movw 16(%esp), %ax
 ; 32BIT:     movw 20(%esp), %cx
 ; 32BIT-NOT: movw %cx, %dx
 ; 32BIT:     leal (%ecx,%eax), %edx
 
-; 64BIT:     t4:
+; 64BIT-LABEL:     t4:
 ; 64BIT-NOT: movw %si, %ax
 ; 64BIT:     leal (%rsi,%rdi), %eax
   %0 = add i16 %k, %c                             ; <i16> [#uses=3]
diff --git a/test/CodeGen/X86/3addr-or.ll b/test/CodeGen/X86/3addr-or.ll
index 912bdc2..76fabbf 100644
--- a/test/CodeGen/X86/3addr-or.ll
+++ b/test/CodeGen/X86/3addr-or.ll
@@ -3,7 +3,7 @@
 
 define i32 @test1(i32 %x) nounwind readnone ssp {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: leal 3(%rdi), %eax
   %0 = shl i32 %x, 5                              ; <i32> [#uses=1]
   %1 = or i32 %0, 3                               ; <i32> [#uses=1]
@@ -11,7 +11,7 @@ entry:
 }
 
 define i64 @test2(i8 %A, i8 %B) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: shrq $4
 ; CHECK-NOT: movq
 ; CHECK-NOT: orq
@@ -31,7 +31,7 @@ define i64 @test2(i8 %A, i8 %B) nounwind {
 define void @test3(i32 %x, i32* %P) nounwind readnone ssp {
 entry:
 ; No reason to emit an add here, should be an or.
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: orl $3, %edi
   %0 = shl i32 %x, 5
   %1 = or i32 %0, 3
@@ -45,7 +45,7 @@ entry:
   %and2 = and i32 %b, 16
   %or = or i32 %and2, %and
   ret i32 %or
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: leal	(%rsi,%rdi), %eax
 }
 
@@ -56,6 +56,6 @@ entry:
   %or = or i32 %and2, %and
   store i32 %or, i32* %P, align 4
   ret void
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: orl
 }
diff --git a/test/CodeGen/X86/MachineSink-DbgValue.ll b/test/CodeGen/X86/MachineSink-DbgValue.ll
index 13a6444..df9580c 100644
--- a/test/CodeGen/X86/MachineSink-DbgValue.ll
+++ b/test/CodeGen/X86/MachineSink-DbgValue.ll
@@ -27,16 +27,16 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, metadata !20, i32 12, metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, metadata !"", i32 0, null, null, metadata !18, null,  null, null} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i32*)* @foo, null, null, metadata !19, i32 0} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786449, metadata !20, i32 12, metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, metadata !"", i32 0, metadata !21, metadata !21, metadata !18, null,  null, null} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 786478, metadata !20, metadata !2, metadata !"foo", metadata !"foo", metadata !"", i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i32*)* @foo, null, null, metadata !19, i32 0} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !20} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!3 = metadata !{i32 786453, metadata !20, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 786468, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !6 = metadata !{i32 786689, metadata !1, metadata !"i", metadata !2, i32 16777218, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !7 = metadata !{i32 786689, metadata !1, metadata !"c", metadata !2, i32 33554434, metadata !8, i32 0, null} ; [ DW_TAG_arg_variable ]
-!8 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ]
-!9 = metadata !{i32 786468, metadata !0, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!8 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ]
+!9 = metadata !{i32 786468, null, metadata !0, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !10 = metadata !{i32 786688, metadata !11, metadata !"a", metadata !2, i32 3, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ]
 !11 = metadata !{i32 786443, metadata !20, metadata !1, i32 2, i32 25, i32 0} ; [ DW_TAG_lexical_block ]
 !12 = metadata !{i32 2, i32 13, metadata !1, null}
@@ -48,3 +48,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !18 = metadata !{metadata !1}
 !19 = metadata !{metadata !6, metadata !7, metadata !10}
 !20 = metadata !{metadata !"a.c", metadata !"/private/tmp"}
+!21 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/MergeConsecutiveStores.ll b/test/CodeGen/X86/MergeConsecutiveStores.ll
index bb227a0..0ef3aa5 100644
--- a/test/CodeGen/X86/MergeConsecutiveStores.ll
+++ b/test/CodeGen/X86/MergeConsecutiveStores.ll
@@ -147,7 +147,7 @@ define void @merge_nonconst_store(i32 %count, i8 %zz, %struct.A* nocapture %p) n
 }
 
 
-;CHECK: merge_loads_i16
+;CHECK-LABEL: merge_loads_i16:
 ; load:
 ;CHECK: movw
 ; store:
@@ -181,7 +181,7 @@ define void @merge_loads_i16(i32 %count, %struct.A* noalias nocapture %q, %struc
 }
 
 ; The loads and the stores are interleved. Can't merge them.
-;CHECK: no_merge_loads
+;CHECK-LABEL: no_merge_loads:
 ;CHECK: movb
 ;CHECK: movb
 ;CHECK: movb
@@ -215,7 +215,7 @@ a4:                                       ; preds = %4, %.lr.ph
 }
 
 
-;CHECK: merge_loads_integer
+;CHECK-LABEL: merge_loads_integer:
 ; load:
 ;CHECK: movq
 ; store:
@@ -249,7 +249,7 @@ define void @merge_loads_integer(i32 %count, %struct.B* noalias nocapture %q, %s
 }
 
 
-;CHECK: merge_loads_vector
+;CHECK-LABEL: merge_loads_vector:
 ; load:
 ;CHECK: movups
 ; store:
@@ -290,7 +290,7 @@ block4:                                       ; preds = %4, %.lr.ph
   ret void
 }
 
-;CHECK: merge_loads_no_align
+;CHECK-LABEL: merge_loads_no_align:
 ; load:
 ;CHECK: movl
 ;CHECK: movl
diff --git a/test/CodeGen/X86/StackColoring-dbg.ll b/test/CodeGen/X86/StackColoring-dbg.ll
index 5982544..8b67a44 100644
--- a/test/CodeGen/X86/StackColoring-dbg.ll
+++ b/test/CodeGen/X86/StackColoring-dbg.ll
@@ -25,6 +25,6 @@ declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
 
 declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind
 
-!16 = metadata !{i32 786468, null, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6}
+!16 = metadata !{i32 786468, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6}
 !2 = metadata !{i32 0}
-!22 = metadata !{i32 786688, metadata !2, metadata !"x", metadata !2, i32 16, metadata !16, i32 0, i32 0}
+!22 = metadata !{i32 786688, null, metadata !"x", metadata !2, i32 16, metadata !16, i32 0, i32 0}
diff --git a/test/CodeGen/X86/StackColoring.ll b/test/CodeGen/X86/StackColoring.ll
index 6c0f00d..f1d9296 100644
--- a/test/CodeGen/X86/StackColoring.ll
+++ b/test/CodeGen/X86/StackColoring.ll
@@ -82,8 +82,8 @@ bb2:
 bb3:
   ret i32 0
 }
-;YESCOLOR: subq  $208, %rsp
-;NOCOLOR: subq  $400, %rsp
+;YESCOLOR: subq  $200, %rsp
+;NOCOLOR: subq  $408, %rsp
 
 
 
@@ -297,8 +297,8 @@ bb3:
 }
 
 
-;YESCOLOR: multi_region_bb
-;NOCOLOR: multi_region_bb
+;YESCOLOR-LABEL: multi_region_bb:
+;NOCOLOR-LABEL: multi_region_bb:
 define void @multi_region_bb() nounwind ssp {
 entry:
   %A.i1 = alloca [100 x i32], align 4
@@ -353,9 +353,9 @@ bb3:
 
 ; Regression test for PR15707.  %buf1 and %buf2 should not be merged
 ; in this test case.
-;YESCOLOR: myCall_pr15707
+;YESCOLOR-LABEL: myCall_pr15707:
 ;YESCOLOR: subq $200008, %rsp
-;NOCOLOR: myCall_pr15707
+;NOCOLOR-LABEL: myCall_pr15707:
 ;NOCOLOR: subq $200008, %rsp
 define void @myCall_pr15707() {
   %buf1 = alloca i8, i32 100000, align 16
@@ -374,8 +374,8 @@ define void @myCall_pr15707() {
 
 ; Check that we don't assert and crash even when there are allocas
 ; outside the declared lifetime regions.
-;YESCOLOR: bad_range
-;NOCOLOR:  bad_range
+;YESCOLOR-LABEL: bad_range:
+;NOCOLOR-LABEL:  bad_range:
 define void @bad_range() nounwind ssp {
 entry:
   %A.i1 = alloca [100 x i32], align 4
@@ -400,8 +400,8 @@ block2:
 
 ; Check that we don't assert and crash even when there are usages
 ; of allocas which do not read or write outside the declared lifetime regions.
-;YESCOLOR: shady_range
-;NOCOLOR:  shady_range
+;YESCOLOR-LABEL: shady_range:
+;NOCOLOR-LABEL:  shady_range:
 
 %struct.Klass = type { i32, i32 }
 
@@ -429,4 +429,3 @@ declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
 declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind
 
 declare i32 @foo(i32, i8*)
-
diff --git a/test/CodeGen/X86/WidenArith.ll b/test/CodeGen/X86/WidenArith.ll
index 0383bd6..f87b382 100644
--- a/test/CodeGen/X86/WidenArith.ll
+++ b/test/CodeGen/X86/WidenArith.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s
 
-;CHECK: test
+;CHECK-LABEL: test:
 ;CHECK: vaddps
 ;CHECK: vmulps
 ;CHECK: vsubps
diff --git a/test/CodeGen/X86/abi-isel.ll b/test/CodeGen/X86/abi-isel.ll
index 955fc62..3b84231 100644
--- a/test/CodeGen/X86/abi-isel.ll
+++ b/test/CodeGen/X86/abi-isel.ll
@@ -37,22 +37,22 @@ entry:
 	store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 0), align 4
 	ret void
 
-; LINUX-64-STATIC: foo00:
+; LINUX-64-STATIC-LABEL: foo00:
 ; LINUX-64-STATIC: movl	src(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl	[[EAX]], dst
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo00:
+; LINUX-32-STATIC-LABEL: foo00:
 ; LINUX-32-STATIC: 	movl	src, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dst
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo00:
+; LINUX-32-PIC-LABEL: foo00:
 ; LINUX-32-PIC: 	movl	src, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dst
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo00:
+; LINUX-64-PIC-LABEL: foo00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r..]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e..]]
 ; LINUX-64-PIC-NEXT: 	movq	dst@GOTPCREL(%rip), [[RCX:%r..]]
@@ -109,22 +109,22 @@ entry:
 	store i32 %0, i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 0), align 4
 	ret void
 
-; LINUX-64-STATIC: fxo00:
+; LINUX-64-STATIC-LABEL: fxo00:
 ; LINUX-64-STATIC: movl	xsrc(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl	[[EAX]], xdst
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: fxo00:
+; LINUX-32-STATIC-LABEL: fxo00:
 ; LINUX-32-STATIC: 	movl	xsrc, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], xdst
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: fxo00:
+; LINUX-32-PIC-LABEL: fxo00:
 ; LINUX-32-PIC: 	movl	xsrc, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], xdst
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: fxo00:
+; LINUX-64-PIC-LABEL: fxo00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	xdst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -179,19 +179,19 @@ define void @foo01() nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @dst, i32 0, i32 0), i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: foo01:
+; LINUX-64-STATIC-LABEL: foo01:
 ; LINUX-64-STATIC: movq	$dst, ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo01:
+; LINUX-32-STATIC-LABEL: foo01:
 ; LINUX-32-STATIC: 	movl	$dst, ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo01:
+; LINUX-32-PIC-LABEL: foo01:
 ; LINUX-32-PIC: 	movl	$dst, ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo01:
+; LINUX-64-PIC-LABEL: foo01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
@@ -239,19 +239,19 @@ define void @fxo01() nounwind {
 entry:
 	store i32* getelementptr ([32 x i32]* @xdst, i32 0, i32 0), i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: fxo01:
+; LINUX-64-STATIC-LABEL: fxo01:
 ; LINUX-64-STATIC: movq	$xdst, ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: fxo01:
+; LINUX-32-STATIC-LABEL: fxo01:
 ; LINUX-32-STATIC: 	movl	$xdst, ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: fxo01:
+; LINUX-32-PIC-LABEL: fxo01:
 ; LINUX-32-PIC: 	movl	$xdst, ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: fxo01:
+; LINUX-64-PIC-LABEL: fxo01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
@@ -301,25 +301,25 @@ entry:
 	%1 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 0), align 4
 	store i32 %1, i32* %0, align 4
 	ret void
-; LINUX-64-STATIC: foo02:
+; LINUX-64-STATIC-LABEL: foo02:
 ; LINUX-64-STATIC: movl    src(%rip), %
 ; LINUX-64-STATIC: movq    ptr(%rip), %
 ; LINUX-64-STATIC: movl
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo02:
+; LINUX-32-STATIC-LABEL: foo02:
 ; LINUX-32-STATIC: 	movl	src, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo02:
+; LINUX-32-PIC-LABEL: foo02:
 ; LINUX-32-PIC: 	movl	src, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo02:
+; LINUX-64-PIC-LABEL: foo02:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -382,26 +382,26 @@ entry:
 	%0 = load i32** @ptr, align 8
 	%1 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 0), align 4
 	store i32 %1, i32* %0, align 4
-; LINUX-64-STATIC: fxo02:
+; LINUX-64-STATIC-LABEL: fxo02:
 ; LINUX-64-STATIC: movl    xsrc(%rip), %
 ; LINUX-64-STATIC: movq    ptr(%rip), %
 ; LINUX-64-STATIC: movl
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: fxo02:
+; LINUX-32-STATIC-LABEL: fxo02:
 ; LINUX-32-STATIC: 	movl	xsrc, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 	ret void
 
-; LINUX-32-PIC: fxo02:
+; LINUX-32-PIC-LABEL: fxo02:
 ; LINUX-32-PIC: 	movl	xsrc, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: fxo02:
+; LINUX-64-PIC-LABEL: fxo02:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -464,22 +464,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 0), align 32
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 0), align 32
 	ret void
-; LINUX-64-STATIC: foo03:
+; LINUX-64-STATIC-LABEL: foo03:
 ; LINUX-64-STATIC: movl    dsrc(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ddst
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo03:
+; LINUX-32-STATIC-LABEL: foo03:
 ; LINUX-32-STATIC: 	movl	dsrc, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ddst
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo03:
+; LINUX-32-PIC-LABEL: foo03:
 ; LINUX-32-PIC: 	movl	dsrc, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ddst
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo03:
+; LINUX-64-PIC-LABEL: foo03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ddst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -524,19 +524,19 @@ define void @foo04() nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @ddst, i32 0, i32 0), i32** @dptr, align 8
 	ret void
-; LINUX-64-STATIC: foo04:
+; LINUX-64-STATIC-LABEL: foo04:
 ; LINUX-64-STATIC: movq    $ddst, dptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo04:
+; LINUX-32-STATIC-LABEL: foo04:
 ; LINUX-32-STATIC: 	movl	$ddst, dptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo04:
+; LINUX-32-PIC-LABEL: foo04:
 ; LINUX-32-PIC: 	movl	$ddst, dptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo04:
+; LINUX-64-PIC-LABEL: foo04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
@@ -580,25 +580,25 @@ entry:
 	%1 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 0), align 32
 	store i32 %1, i32* %0, align 4
 	ret void
-; LINUX-64-STATIC: foo05:
+; LINUX-64-STATIC-LABEL: foo05:
 ; LINUX-64-STATIC: movl    dsrc(%rip), %
 ; LINUX-64-STATIC: movq    dptr(%rip), %
 ; LINUX-64-STATIC: movl
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo05:
+; LINUX-32-STATIC-LABEL: foo05:
 ; LINUX-32-STATIC: 	movl	dsrc, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo05:
+; LINUX-32-PIC-LABEL: foo05:
 ; LINUX-32-PIC: 	movl	dsrc, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo05:
+; LINUX-64-PIC-LABEL: foo05:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -651,22 +651,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 0), align 4
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 0), align 4
 	ret void
-; LINUX-64-STATIC: foo06:
+; LINUX-64-STATIC-LABEL: foo06:
 ; LINUX-64-STATIC: movl    lsrc(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ldst(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo06:
+; LINUX-32-STATIC-LABEL: foo06:
 ; LINUX-32-STATIC: 	movl	lsrc, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ldst
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo06:
+; LINUX-32-PIC-LABEL: foo06:
 ; LINUX-32-PIC: 	movl	lsrc, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ldst
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo06:
+; LINUX-64-PIC-LABEL: foo06:
 ; LINUX-64-PIC: 	movl	lsrc(%rip), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ldst(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
@@ -709,19 +709,19 @@ define void @foo07() nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @ldst, i32 0, i32 0), i32** @lptr, align 8
 	ret void
-; LINUX-64-STATIC: foo07:
+; LINUX-64-STATIC-LABEL: foo07:
 ; LINUX-64-STATIC: movq    $ldst, lptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo07:
+; LINUX-32-STATIC-LABEL: foo07:
 ; LINUX-32-STATIC: 	movl	$ldst, lptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo07:
+; LINUX-32-PIC-LABEL: foo07:
 ; LINUX-32-PIC: 	movl	$ldst, lptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo07:
+; LINUX-64-PIC-LABEL: foo07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
@@ -764,25 +764,25 @@ entry:
 	%1 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 0), align 4
 	store i32 %1, i32* %0, align 4
 	ret void
-; LINUX-64-STATIC: foo08:
+; LINUX-64-STATIC-LABEL: foo08:
 ; LINUX-64-STATIC: movl    lsrc(%rip), %
 ; LINUX-64-STATIC: movq    lptr(%rip), %
 ; LINUX-64-STATIC: movl
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: foo08:
+; LINUX-32-STATIC-LABEL: foo08:
 ; LINUX-32-STATIC: 	movl	lsrc, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: foo08:
+; LINUX-32-PIC-LABEL: foo08:
 ; LINUX-32-PIC: 	movl	lsrc, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: foo08:
+; LINUX-64-PIC-LABEL: foo08:
 ; LINUX-64-PIC: 	movl	lsrc(%rip), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]])
@@ -833,22 +833,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 16), align 4
 	store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16), align 4
 	ret void
-; LINUX-64-STATIC: qux00:
+; LINUX-64-STATIC-LABEL: qux00:
 ; LINUX-64-STATIC: movl    src+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], dst+64(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux00:
+; LINUX-32-STATIC-LABEL: qux00:
 ; LINUX-32-STATIC: 	movl	src+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dst+64
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qux00:
+; LINUX-32-PIC-LABEL: qux00:
 ; LINUX-32-PIC: 	movl	src+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dst+64
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux00:
+; LINUX-64-PIC-LABEL: qux00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -904,22 +904,22 @@ entry:
 	%0 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 16), align 4
 	store i32 %0, i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16), align 4
 	ret void
-; LINUX-64-STATIC: qxx00:
+; LINUX-64-STATIC-LABEL: qxx00:
 ; LINUX-64-STATIC: movl    xsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], xdst+64(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qxx00:
+; LINUX-32-STATIC-LABEL: qxx00:
 ; LINUX-32-STATIC: 	movl	xsrc+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], xdst+64
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qxx00:
+; LINUX-32-PIC-LABEL: qxx00:
 ; LINUX-32-PIC: 	movl	xsrc+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], xdst+64
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qxx00:
+; LINUX-64-PIC-LABEL: qxx00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	xdst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -974,19 +974,19 @@ define void @qux01() nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16), i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: qux01:
+; LINUX-64-STATIC-LABEL: qux01:
 ; LINUX-64-STATIC: movq    $dst+64, ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux01:
+; LINUX-32-STATIC-LABEL: qux01:
 ; LINUX-32-STATIC: 	movl	$dst+64, ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qux01:
+; LINUX-32-PIC-LABEL: qux01:
 ; LINUX-32-PIC: 	movl	$dst+64, ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux01:
+; LINUX-64-PIC-LABEL: qux01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	addq	$64, [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1040,19 +1040,19 @@ define void @qxx01() nounwind {
 entry:
 	store i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16), i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: qxx01:
+; LINUX-64-STATIC-LABEL: qxx01:
 ; LINUX-64-STATIC: movq    $xdst+64, ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qxx01:
+; LINUX-32-STATIC-LABEL: qxx01:
 ; LINUX-32-STATIC: 	movl	$xdst+64, ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qxx01:
+; LINUX-32-PIC-LABEL: qxx01:
 ; LINUX-32-PIC: 	movl	$xdst+64, ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qxx01:
+; LINUX-64-PIC-LABEL: qxx01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	addq	$64, [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1108,26 +1108,26 @@ entry:
 	%1 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 16), align 4
 	%2 = getelementptr i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
-; LINUX-64-STATIC: qux02:
+; LINUX-64-STATIC-LABEL: qux02:
 ; LINUX-64-STATIC: movl    src+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]])
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux02:
+; LINUX-32-STATIC-LABEL: qux02:
 ; LINUX-32-STATIC: 	movl	src+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 	ret void
 
-; LINUX-32-PIC: qux02:
+; LINUX-32-PIC-LABEL: qux02:
 ; LINUX-32-PIC: 	movl	src+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux02:
+; LINUX-64-PIC-LABEL: qux02:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1191,26 +1191,26 @@ entry:
 	%1 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 16), align 4
 	%2 = getelementptr i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
-; LINUX-64-STATIC: qxx02:
+; LINUX-64-STATIC-LABEL: qxx02:
 ; LINUX-64-STATIC: movl    xsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]])
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qxx02:
+; LINUX-32-STATIC-LABEL: qxx02:
 ; LINUX-32-STATIC: 	movl	xsrc+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 	ret void
 
-; LINUX-32-PIC: qxx02:
+; LINUX-32-PIC-LABEL: qxx02:
 ; LINUX-32-PIC: 	movl	xsrc+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qxx02:
+; LINUX-64-PIC-LABEL: qxx02:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1273,22 +1273,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 16), align 32
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16), align 32
 	ret void
-; LINUX-64-STATIC: qux03:
+; LINUX-64-STATIC-LABEL: qux03:
 ; LINUX-64-STATIC: movl    dsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ddst+64(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux03:
+; LINUX-32-STATIC-LABEL: qux03:
 ; LINUX-32-STATIC: 	movl	dsrc+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ddst+64
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qux03:
+; LINUX-32-PIC-LABEL: qux03:
 ; LINUX-32-PIC: 	movl	dsrc+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ddst+64
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux03:
+; LINUX-64-PIC-LABEL: qux03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ddst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1333,19 +1333,19 @@ define void @qux04() nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16), i32** @dptr, align 8
 	ret void
-; LINUX-64-STATIC: qux04:
+; LINUX-64-STATIC-LABEL: qux04:
 ; LINUX-64-STATIC: movq    $ddst+64, dptr(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux04:
+; LINUX-32-STATIC-LABEL: qux04:
 ; LINUX-32-STATIC: 	movl	$ddst+64, dptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qux04:
+; LINUX-32-PIC-LABEL: qux04:
 ; LINUX-32-PIC: 	movl	$ddst+64, dptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux04:
+; LINUX-64-PIC-LABEL: qux04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	addq	$64, [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1390,26 +1390,26 @@ entry:
 	%1 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 16), align 32
 	%2 = getelementptr i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
-; LINUX-64-STATIC: qux05:
+; LINUX-64-STATIC-LABEL: qux05:
 ; LINUX-64-STATIC: movl    dsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    dptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]])
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux05:
+; LINUX-32-STATIC-LABEL: qux05:
 ; LINUX-32-STATIC: 	movl	dsrc+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 	ret void
 
-; LINUX-32-PIC: qux05:
+; LINUX-32-PIC-LABEL: qux05:
 ; LINUX-32-PIC: 	movl	dsrc+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux05:
+; LINUX-64-PIC-LABEL: qux05:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1462,22 +1462,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 16), align 4
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16), align 4
 	ret void
-; LINUX-64-STATIC: qux06:
+; LINUX-64-STATIC-LABEL: qux06:
 ; LINUX-64-STATIC: movl    lsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ldst+64
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux06:
+; LINUX-32-STATIC-LABEL: qux06:
 ; LINUX-32-STATIC: 	movl	lsrc+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ldst+64
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qux06:
+; LINUX-32-PIC-LABEL: qux06:
 ; LINUX-32-PIC: 	movl	lsrc+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ldst+64
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux06:
+; LINUX-64-PIC-LABEL: qux06:
 ; LINUX-64-PIC: 	movl	lsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ldst+64(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
@@ -1520,19 +1520,19 @@ define void @qux07() nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16), i32** @lptr, align 8
 	ret void
-; LINUX-64-STATIC: qux07:
+; LINUX-64-STATIC-LABEL: qux07:
 ; LINUX-64-STATIC: movq    $ldst+64, lptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux07:
+; LINUX-32-STATIC-LABEL: qux07:
 ; LINUX-32-STATIC: 	movl	$ldst+64, lptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: qux07:
+; LINUX-32-PIC-LABEL: qux07:
 ; LINUX-32-PIC: 	movl	$ldst+64, lptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux07:
+; LINUX-64-PIC-LABEL: qux07:
 ; LINUX-64-PIC: 	leaq	ldst+64(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
@@ -1575,26 +1575,26 @@ entry:
 	%1 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 16), align 4
 	%2 = getelementptr i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
-; LINUX-64-STATIC: qux08:
+; LINUX-64-STATIC-LABEL: qux08:
 ; LINUX-64-STATIC: movl    lsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]])
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: qux08:
+; LINUX-32-STATIC-LABEL: qux08:
 ; LINUX-32-STATIC: 	movl	lsrc+64, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 	ret void
 
-; LINUX-32-PIC: qux08:
+; LINUX-32-PIC-LABEL: qux08:
 ; LINUX-32-PIC: 	movl	lsrc+64, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: qux08:
+; LINUX-64-PIC-LABEL: qux08:
 ; LINUX-64-PIC: 	movl	lsrc+64(%rip), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
@@ -1647,24 +1647,24 @@ entry:
 	%2 = getelementptr [131072 x i32]* @dst, i64 0, i64 %i
 	store i32 %1, i32* %2, align 4
 	ret void
-; LINUX-64-STATIC: ind00:
+; LINUX-64-STATIC-LABEL: ind00:
 ; LINUX-64-STATIC: movl    src(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], dst(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind00:
+; LINUX-32-STATIC-LABEL: ind00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	src(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], dst(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind00:
+; LINUX-32-PIC-LABEL: ind00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	src(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], dst(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind00:
+; LINUX-64-PIC-LABEL: ind00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1725,24 +1725,24 @@ entry:
 	%2 = getelementptr [32 x i32]* @xdst, i64 0, i64 %i
 	store i32 %1, i32* %2, align 4
 	ret void
-; LINUX-64-STATIC: ixd00:
+; LINUX-64-STATIC-LABEL: ixd00:
 ; LINUX-64-STATIC: movl    xsrc(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], xdst(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ixd00:
+; LINUX-32-STATIC-LABEL: ixd00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	xsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], xdst(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ixd00:
+; LINUX-32-PIC-LABEL: ixd00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	xsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], xdst(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ixd00:
+; LINUX-64-PIC-LABEL: ixd00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	xdst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -1801,24 +1801,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %i
 	store i32* %0, i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: ind01:
+; LINUX-64-STATIC-LABEL: ind01:
 ; LINUX-64-STATIC: leaq    dst(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind01:
+; LINUX-32-STATIC-LABEL: ind01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	dst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind01:
+; LINUX-32-PIC-LABEL: ind01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	dst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind01:
+; LINUX-64-PIC-LABEL: ind01:
 ; LINUX-64-PIC: 	shlq	$2, %rdi
 ; LINUX-64-PIC-NEXT: 	addq	dst@GOTPCREL(%rip), %rdi
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RAX:%r.x]]
@@ -1877,24 +1877,24 @@ entry:
 	%0 = getelementptr [32 x i32]* @xdst, i64 0, i64 %i
 	store i32* %0, i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: ixd01:
+; LINUX-64-STATIC-LABEL: ixd01:
 ; LINUX-64-STATIC: leaq    xdst(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ixd01:
+; LINUX-32-STATIC-LABEL: ixd01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	xdst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ixd01:
+; LINUX-32-PIC-LABEL: ixd01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	xdst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ixd01:
+; LINUX-64-PIC-LABEL: ixd01:
 ; LINUX-64-PIC: 	shlq	$2, %rdi
 ; LINUX-64-PIC-NEXT: 	addq	xdst@GOTPCREL(%rip), %rdi
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RAX:%r.x]]
@@ -1956,27 +1956,27 @@ entry:
 	%3 = getelementptr i32* %0, i64 %i
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: ind02:
+; LINUX-64-STATIC-LABEL: ind02:
 ; LINUX-64-STATIC: movl    src(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind02:
+; LINUX-32-STATIC-LABEL: ind02:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	src(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind02:
+; LINUX-32-PIC-LABEL: ind02:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	src(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind02:
+; LINUX-64-PIC-LABEL: ind02:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2045,27 +2045,27 @@ entry:
 	%3 = getelementptr i32* %0, i64 %i
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: ixd02:
+; LINUX-64-STATIC-LABEL: ixd02:
 ; LINUX-64-STATIC: movl    xsrc(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ixd02:
+; LINUX-32-STATIC-LABEL: ixd02:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	xsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ixd02:
+; LINUX-32-PIC-LABEL: ixd02:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	xsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ixd02:
+; LINUX-64-PIC-LABEL: ixd02:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2133,24 +2133,24 @@ entry:
 	%2 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %i
 	store i32 %1, i32* %2, align 4
 	ret void
-; LINUX-64-STATIC: ind03:
+; LINUX-64-STATIC-LABEL: ind03:
 ; LINUX-64-STATIC: movl    dsrc(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ddst(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind03:
+; LINUX-32-STATIC-LABEL: ind03:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ddst(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind03:
+; LINUX-32-PIC-LABEL: ind03:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ddst(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind03:
+; LINUX-64-PIC-LABEL: ind03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ddst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2205,24 +2205,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %i
 	store i32* %0, i32** @dptr, align 8
 	ret void
-; LINUX-64-STATIC: ind04:
+; LINUX-64-STATIC-LABEL: ind04:
 ; LINUX-64-STATIC: leaq    ddst(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], dptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind04:
+; LINUX-32-STATIC-LABEL: ind04:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ddst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind04:
+; LINUX-32-PIC-LABEL: ind04:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ddst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind04:
+; LINUX-64-PIC-LABEL: ind04:
 ; LINUX-64-PIC: 	shlq	$2, %rdi
 ; LINUX-64-PIC-NEXT: 	addq	ddst@GOTPCREL(%rip), %rdi
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RAX:%r.x]]
@@ -2277,27 +2277,27 @@ entry:
 	%3 = getelementptr i32* %0, i64 %i
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: ind05:
+; LINUX-64-STATIC-LABEL: ind05:
 ; LINUX-64-STATIC: movl    dsrc(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    dptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind05:
+; LINUX-32-STATIC-LABEL: ind05:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind05:
+; LINUX-32-PIC-LABEL: ind05:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind05:
+; LINUX-64-PIC-LABEL: ind05:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2358,24 +2358,24 @@ entry:
 	%2 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %i
 	store i32 %1, i32* %2, align 4
 	ret void
-; LINUX-64-STATIC: ind06:
+; LINUX-64-STATIC-LABEL: ind06:
 ; LINUX-64-STATIC: movl    lsrc(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ldst(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind06:
+; LINUX-32-STATIC-LABEL: ind06:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ldst(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind06:
+; LINUX-32-PIC-LABEL: ind06:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ldst(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind06:
+; LINUX-64-PIC-LABEL: ind06:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	ldst(%rip), [[RCX:%r.x]]
@@ -2430,24 +2430,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %i
 	store i32* %0, i32** @lptr, align 8
 	ret void
-; LINUX-64-STATIC: ind07:
+; LINUX-64-STATIC-LABEL: ind07:
 ; LINUX-64-STATIC: leaq    ldst(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], lptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind07:
+; LINUX-32-STATIC-LABEL: ind07:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ldst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind07:
+; LINUX-32-PIC-LABEL: ind07:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ldst(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind07:
+; LINUX-64-PIC-LABEL: ind07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
@@ -2501,27 +2501,27 @@ entry:
 	%3 = getelementptr i32* %0, i64 %i
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: ind08:
+; LINUX-64-STATIC-LABEL: ind08:
 ; LINUX-64-STATIC: movl    lsrc(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ind08:
+; LINUX-32-STATIC-LABEL: ind08:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ind08:
+; LINUX-32-PIC-LABEL: ind08:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lsrc(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ind08:
+; LINUX-64-PIC-LABEL: ind08:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
@@ -2582,24 +2582,24 @@ entry:
 	%3 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: off00:
+; LINUX-64-STATIC-LABEL: off00:
 ; LINUX-64-STATIC: movl    src+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], dst+64(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off00:
+; LINUX-32-STATIC-LABEL: off00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	src+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], dst+64(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off00:
+; LINUX-32-PIC-LABEL: off00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	src+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], dst+64(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off00:
+; LINUX-64-PIC-LABEL: off00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2661,24 +2661,24 @@ entry:
 	%3 = getelementptr [32 x i32]* @xdst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: oxf00:
+; LINUX-64-STATIC-LABEL: oxf00:
 ; LINUX-64-STATIC: movl    xsrc+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], xdst+64(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: oxf00:
+; LINUX-32-STATIC-LABEL: oxf00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], xdst+64(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: oxf00:
+; LINUX-32-PIC-LABEL: oxf00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], xdst+64(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: oxf00:
+; LINUX-64-PIC-LABEL: oxf00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	xdst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2738,24 +2738,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %.sum
 	store i32* %0, i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: off01:
+; LINUX-64-STATIC-LABEL: off01:
 ; LINUX-64-STATIC: leaq    dst+64(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off01:
+; LINUX-32-STATIC-LABEL: off01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	dst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off01:
+; LINUX-32-PIC-LABEL: off01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	dst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off01:
+; LINUX-64-PIC-LABEL: off01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2815,24 +2815,24 @@ entry:
 	%0 = getelementptr [32 x i32]* @xdst, i64 0, i64 %.sum
 	store i32* %0, i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: oxf01:
+; LINUX-64-STATIC-LABEL: oxf01:
 ; LINUX-64-STATIC: leaq    xdst+64(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], ptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: oxf01:
+; LINUX-32-STATIC-LABEL: oxf01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	xdst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: oxf01:
+; LINUX-32-PIC-LABEL: oxf01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	xdst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: oxf01:
+; LINUX-64-PIC-LABEL: oxf01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2895,27 +2895,27 @@ entry:
 	%4 = getelementptr i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
-; LINUX-64-STATIC: off02:
+; LINUX-64-STATIC-LABEL: off02:
 ; LINUX-64-STATIC: movl    src+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off02:
+; LINUX-32-STATIC-LABEL: off02:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	src+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off02:
+; LINUX-32-PIC-LABEL: off02:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	src+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off02:
+; LINUX-64-PIC-LABEL: off02:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -2985,27 +2985,27 @@ entry:
 	%4 = getelementptr i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
-; LINUX-64-STATIC: oxf02:
+; LINUX-64-STATIC-LABEL: oxf02:
 ; LINUX-64-STATIC: movl    xsrc+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: oxf02:
+; LINUX-32-STATIC-LABEL: oxf02:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: oxf02:
+; LINUX-32-PIC-LABEL: oxf02:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: oxf02:
+; LINUX-64-PIC-LABEL: oxf02:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3074,24 +3074,24 @@ entry:
 	%3 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: off03:
+; LINUX-64-STATIC-LABEL: off03:
 ; LINUX-64-STATIC: movl    dsrc+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ddst+64(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off03:
+; LINUX-32-STATIC-LABEL: off03:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ddst+64(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off03:
+; LINUX-32-PIC-LABEL: off03:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ddst+64(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off03:
+; LINUX-64-PIC-LABEL: off03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ddst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3147,24 +3147,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %.sum
 	store i32* %0, i32** @dptr, align 8
 	ret void
-; LINUX-64-STATIC: off04:
+; LINUX-64-STATIC-LABEL: off04:
 ; LINUX-64-STATIC: leaq    ddst+64(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], dptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off04:
+; LINUX-32-STATIC-LABEL: off04:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ddst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off04:
+; LINUX-32-PIC-LABEL: off04:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ddst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off04:
+; LINUX-64-PIC-LABEL: off04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3220,27 +3220,27 @@ entry:
 	%4 = getelementptr i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
-; LINUX-64-STATIC: off05:
+; LINUX-64-STATIC-LABEL: off05:
 ; LINUX-64-STATIC: movl    dsrc+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    dptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off05:
+; LINUX-32-STATIC-LABEL: off05:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off05:
+; LINUX-32-PIC-LABEL: off05:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off05:
+; LINUX-64-PIC-LABEL: off05:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3302,24 +3302,24 @@ entry:
 	%3 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: off06:
+; LINUX-64-STATIC-LABEL: off06:
 ; LINUX-64-STATIC: movl    lsrc+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ldst+64(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off06:
+; LINUX-32-STATIC-LABEL: off06:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ldst+64(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off06:
+; LINUX-32-PIC-LABEL: off06:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ldst+64(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off06:
+; LINUX-64-PIC-LABEL: off06:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	ldst(%rip), [[RCX:%r.x]]
@@ -3375,24 +3375,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %.sum
 	store i32* %0, i32** @lptr, align 8
 	ret void
-; LINUX-64-STATIC: off07:
+; LINUX-64-STATIC-LABEL: off07:
 ; LINUX-64-STATIC: leaq    ldst+64(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], lptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off07:
+; LINUX-32-STATIC-LABEL: off07:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ldst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off07:
+; LINUX-32-PIC-LABEL: off07:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ldst+64(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off07:
+; LINUX-64-PIC-LABEL: off07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
@@ -3447,27 +3447,27 @@ entry:
 	%4 = getelementptr i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
-; LINUX-64-STATIC: off08:
+; LINUX-64-STATIC-LABEL: off08:
 ; LINUX-64-STATIC: movl    lsrc+64(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: off08:
+; LINUX-32-STATIC-LABEL: off08:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: off08:
+; LINUX-32-PIC-LABEL: off08:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: off08:
+; LINUX-64-PIC-LABEL: off08:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
@@ -3525,22 +3525,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 65536), align 4
 	store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536), align 4
 	ret void
-; LINUX-64-STATIC: moo00:
+; LINUX-64-STATIC-LABEL: moo00:
 ; LINUX-64-STATIC: movl    src+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], dst+262144(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo00:
+; LINUX-32-STATIC-LABEL: moo00:
 ; LINUX-32-STATIC: 	movl	src+262144, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dst+262144
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo00:
+; LINUX-32-PIC-LABEL: moo00:
 ; LINUX-32-PIC: 	movl	src+262144, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dst+262144
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo00:
+; LINUX-64-PIC-LABEL: moo00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3595,19 +3595,19 @@ define void @moo01(i64 %i) nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536), i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: moo01:
+; LINUX-64-STATIC-LABEL: moo01:
 ; LINUX-64-STATIC: movq    $dst+262144, ptr(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo01:
+; LINUX-32-STATIC-LABEL: moo01:
 ; LINUX-32-STATIC: 	movl	$dst+262144, ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo01:
+; LINUX-32-PIC-LABEL: moo01:
 ; LINUX-32-PIC: 	movl	$dst+262144, ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo01:
+; LINUX-64-PIC-LABEL: moo01:
 ; LINUX-64-PIC: 	movl	$262144, [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	addq	dst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3664,25 +3664,25 @@ entry:
 	%2 = getelementptr i32* %0, i64 65536
 	store i32 %1, i32* %2, align 4
 	ret void
-; LINUX-64-STATIC: moo02:
+; LINUX-64-STATIC-LABEL: moo02:
 ; LINUX-64-STATIC: movl    src+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]])
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo02:
+; LINUX-32-STATIC-LABEL: moo02:
 ; LINUX-32-STATIC: 	movl	src+262144, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo02:
+; LINUX-32-PIC-LABEL: moo02:
 ; LINUX-32-PIC: 	movl	src+262144, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo02:
+; LINUX-64-PIC-LABEL: moo02:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3745,22 +3745,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 65536), align 32
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536), align 32
 	ret void
-; LINUX-64-STATIC: moo03:
+; LINUX-64-STATIC-LABEL: moo03:
 ; LINUX-64-STATIC: movl    dsrc+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ddst+262144(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo03:
+; LINUX-32-STATIC-LABEL: moo03:
 ; LINUX-32-STATIC: 	movl	dsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ddst+262144
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo03:
+; LINUX-32-PIC-LABEL: moo03:
 ; LINUX-32-PIC: 	movl	dsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ddst+262144
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo03:
+; LINUX-64-PIC-LABEL: moo03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ddst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3805,19 +3805,19 @@ define void @moo04(i64 %i) nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536), i32** @dptr, align 8
 	ret void
-; LINUX-64-STATIC: moo04:
+; LINUX-64-STATIC-LABEL: moo04:
 ; LINUX-64-STATIC: movq    $ddst+262144, dptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo04:
+; LINUX-32-STATIC-LABEL: moo04:
 ; LINUX-32-STATIC: 	movl	$ddst+262144, dptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo04:
+; LINUX-32-PIC-LABEL: moo04:
 ; LINUX-32-PIC: 	movl	$ddst+262144, dptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo04:
+; LINUX-64-PIC-LABEL: moo04:
 ; LINUX-64-PIC: 	movl	$262144, [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	addq	ddst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3863,25 +3863,25 @@ entry:
 	%2 = getelementptr i32* %0, i64 65536
 	store i32 %1, i32* %2, align 4
 	ret void
-; LINUX-64-STATIC: moo05:
+; LINUX-64-STATIC-LABEL: moo05:
 ; LINUX-64-STATIC: movl    dsrc+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    dptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]])
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo05:
+; LINUX-32-STATIC-LABEL: moo05:
 ; LINUX-32-STATIC: 	movl	dsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo05:
+; LINUX-32-PIC-LABEL: moo05:
 ; LINUX-32-PIC: 	movl	dsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo05:
+; LINUX-64-PIC-LABEL: moo05:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -3934,22 +3934,22 @@ entry:
 	%0 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 65536), align 4
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536), align 4
 	ret void
-; LINUX-64-STATIC: moo06:
+; LINUX-64-STATIC-LABEL: moo06:
 ; LINUX-64-STATIC: movl    lsrc+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ldst+262144(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo06:
+; LINUX-32-STATIC-LABEL: moo06:
 ; LINUX-32-STATIC: 	movl	lsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ldst+262144
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo06:
+; LINUX-32-PIC-LABEL: moo06:
 ; LINUX-32-PIC: 	movl	lsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ldst+262144
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo06:
+; LINUX-64-PIC-LABEL: moo06:
 ; LINUX-64-PIC: 	movl	lsrc+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ldst+262144(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
@@ -3992,19 +3992,19 @@ define void @moo07(i64 %i) nounwind {
 entry:
 	store i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536), i32** @lptr, align 8
 	ret void
-; LINUX-64-STATIC: moo07:
+; LINUX-64-STATIC-LABEL: moo07:
 ; LINUX-64-STATIC: movq    $ldst+262144, lptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo07:
+; LINUX-32-STATIC-LABEL: moo07:
 ; LINUX-32-STATIC: 	movl	$ldst+262144, lptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo07:
+; LINUX-32-PIC-LABEL: moo07:
 ; LINUX-32-PIC: 	movl	$ldst+262144, lptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo07:
+; LINUX-64-PIC-LABEL: moo07:
 ; LINUX-64-PIC: 	leaq	ldst+262144(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
@@ -4048,25 +4048,25 @@ entry:
 	%2 = getelementptr i32* %0, i64 65536
 	store i32 %1, i32* %2, align 4
 	ret void
-; LINUX-64-STATIC: moo08:
+; LINUX-64-STATIC-LABEL: moo08:
 ; LINUX-64-STATIC: movl    lsrc+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]])
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: moo08:
+; LINUX-32-STATIC-LABEL: moo08:
 ; LINUX-32-STATIC: 	movl	lsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: moo08:
+; LINUX-32-PIC-LABEL: moo08:
 ; LINUX-32-PIC: 	movl	lsrc+262144, [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: moo08:
+; LINUX-64-PIC-LABEL: moo08:
 ; LINUX-64-PIC: 	movl	lsrc+262144(%rip), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
@@ -4120,24 +4120,24 @@ entry:
 	%3 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: big00:
+; LINUX-64-STATIC-LABEL: big00:
 ; LINUX-64-STATIC: movl    src+262144(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], dst+262144(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big00:
+; LINUX-32-STATIC-LABEL: big00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	src+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], dst+262144(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big00:
+; LINUX-32-PIC-LABEL: big00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	src+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], dst+262144(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big00:
+; LINUX-64-PIC-LABEL: big00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -4197,24 +4197,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %.sum
 	store i32* %0, i32** @ptr, align 8
 	ret void
-; LINUX-64-STATIC: big01:
+; LINUX-64-STATIC-LABEL: big01:
 ; LINUX-64-STATIC: leaq    dst+262144(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], ptr(%rip)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big01:
+; LINUX-32-STATIC-LABEL: big01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	dst+262144(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big01:
+; LINUX-32-PIC-LABEL: big01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	dst+262144(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big01:
+; LINUX-64-PIC-LABEL: big01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -4277,27 +4277,27 @@ entry:
 	%4 = getelementptr i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
-; LINUX-64-STATIC: big02:
+; LINUX-64-STATIC-LABEL: big02:
 ; LINUX-64-STATIC: movl    src+262144(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big02:
+; LINUX-32-STATIC-LABEL: big02:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	src+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big02:
+; LINUX-32-PIC-LABEL: big02:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	src+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big02:
+; LINUX-64-PIC-LABEL: big02:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -4366,24 +4366,24 @@ entry:
 	%3 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: big03:
+; LINUX-64-STATIC-LABEL: big03:
 ; LINUX-64-STATIC: movl    dsrc+262144(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ddst+262144(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big03:
+; LINUX-32-STATIC-LABEL: big03:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ddst+262144(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big03:
+; LINUX-32-PIC-LABEL: big03:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ddst+262144(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big03:
+; LINUX-64-PIC-LABEL: big03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ddst@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -4439,24 +4439,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %.sum
 	store i32* %0, i32** @dptr, align 8
 	ret void
-; LINUX-64-STATIC: big04:
+; LINUX-64-STATIC-LABEL: big04:
 ; LINUX-64-STATIC: leaq    ddst+262144(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], dptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big04:
+; LINUX-32-STATIC-LABEL: big04:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ddst+262144(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big04:
+; LINUX-32-PIC-LABEL: big04:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ddst+262144(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big04:
+; LINUX-64-PIC-LABEL: big04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -4512,27 +4512,27 @@ entry:
 	%4 = getelementptr i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
-; LINUX-64-STATIC: big05:
+; LINUX-64-STATIC-LABEL: big05:
 ; LINUX-64-STATIC: movl    dsrc+262144(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    dptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big05:
+; LINUX-32-STATIC-LABEL: big05:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big05:
+; LINUX-32-PIC-LABEL: big05:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big05:
+; LINUX-64-PIC-LABEL: big05:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
@@ -4594,24 +4594,24 @@ entry:
 	%3 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
 	store i32 %2, i32* %3, align 4
 	ret void
-; LINUX-64-STATIC: big06:
+; LINUX-64-STATIC-LABEL: big06:
 ; LINUX-64-STATIC: movl    lsrc+262144(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], ldst+262144(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big06:
+; LINUX-32-STATIC-LABEL: big06:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ldst+262144(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big06:
+; LINUX-32-PIC-LABEL: big06:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ldst+262144(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big06:
+; LINUX-64-PIC-LABEL: big06:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	ldst(%rip), [[RCX:%r.x]]
@@ -4667,24 +4667,24 @@ entry:
 	%0 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %.sum
 	store i32* %0, i32** @lptr, align 8
 	ret void
-; LINUX-64-STATIC: big07:
+; LINUX-64-STATIC-LABEL: big07:
 ; LINUX-64-STATIC: leaq    ldst+262144(,%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-STATIC: movq    [[RAX]], lptr
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big07:
+; LINUX-32-STATIC-LABEL: big07:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ldst+262144(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big07:
+; LINUX-32-PIC-LABEL: big07:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ldst+262144(,[[EAX]],4), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big07:
+; LINUX-64-PIC-LABEL: big07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
@@ -4739,27 +4739,27 @@ entry:
 	%4 = getelementptr i32* %0, i64 %1
 	store i32 %3, i32* %4, align 4
 	ret void
-; LINUX-64-STATIC: big08:
+; LINUX-64-STATIC-LABEL: big08:
 ; LINUX-64-STATIC: movl    lsrc+262144(,%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-STATIC: movq    lptr(%rip), [[RCX:%r.x]]
 ; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: big08:
+; LINUX-32-STATIC-LABEL: big08:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: big08:
+; LINUX-32-PIC-LABEL: big08:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: big08:
+; LINUX-64-PIC-LABEL: big08:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
 ; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
@@ -4815,19 +4815,19 @@ entry:
 define i8* @bar00() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @src to i8*)
-; LINUX-64-STATIC: bar00:
+; LINUX-64-STATIC-LABEL: bar00:
 ; LINUX-64-STATIC: movl    $src, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar00:
+; LINUX-32-STATIC-LABEL: bar00:
 ; LINUX-32-STATIC: 	movl	$src, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar00:
+; LINUX-32-PIC-LABEL: bar00:
 ; LINUX-32-PIC: 	movl	$src, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar00:
+; LINUX-64-PIC-LABEL: bar00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -4862,19 +4862,19 @@ entry:
 define i8* @bxr00() nounwind {
 entry:
 	ret i8* bitcast ([32 x i32]* @xsrc to i8*)
-; LINUX-64-STATIC: bxr00:
+; LINUX-64-STATIC-LABEL: bxr00:
 ; LINUX-64-STATIC: movl    $xsrc, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bxr00:
+; LINUX-32-STATIC-LABEL: bxr00:
 ; LINUX-32-STATIC: 	movl	$xsrc, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bxr00:
+; LINUX-32-PIC-LABEL: bxr00:
 ; LINUX-32-PIC: 	movl	$xsrc, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bxr00:
+; LINUX-64-PIC-LABEL: bxr00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -4909,19 +4909,19 @@ entry:
 define i8* @bar01() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @dst to i8*)
-; LINUX-64-STATIC: bar01:
+; LINUX-64-STATIC-LABEL: bar01:
 ; LINUX-64-STATIC: movl    $dst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar01:
+; LINUX-32-STATIC-LABEL: bar01:
 ; LINUX-32-STATIC: 	movl	$dst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar01:
+; LINUX-32-PIC-LABEL: bar01:
 ; LINUX-32-PIC: 	movl	$dst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar01:
+; LINUX-64-PIC-LABEL: bar01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -4956,19 +4956,19 @@ entry:
 define i8* @bxr01() nounwind {
 entry:
 	ret i8* bitcast ([32 x i32]* @xdst to i8*)
-; LINUX-64-STATIC: bxr01:
+; LINUX-64-STATIC-LABEL: bxr01:
 ; LINUX-64-STATIC: movl    $xdst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bxr01:
+; LINUX-32-STATIC-LABEL: bxr01:
 ; LINUX-32-STATIC: 	movl	$xdst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bxr01:
+; LINUX-32-PIC-LABEL: bxr01:
 ; LINUX-32-PIC: 	movl	$xdst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bxr01:
+; LINUX-64-PIC-LABEL: bxr01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5003,19 +5003,19 @@ entry:
 define i8* @bar02() nounwind {
 entry:
 	ret i8* bitcast (i32** @ptr to i8*)
-; LINUX-64-STATIC: bar02:
+; LINUX-64-STATIC-LABEL: bar02:
 ; LINUX-64-STATIC: movl    $ptr, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar02:
+; LINUX-32-STATIC-LABEL: bar02:
 ; LINUX-32-STATIC: 	movl	$ptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar02:
+; LINUX-32-PIC-LABEL: bar02:
 ; LINUX-32-PIC: 	movl	$ptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar02:
+; LINUX-64-PIC-LABEL: bar02:
 ; LINUX-64-PIC: 	movq	ptr@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5050,19 +5050,19 @@ entry:
 define i8* @bar03() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @dsrc to i8*)
-; LINUX-64-STATIC: bar03:
+; LINUX-64-STATIC-LABEL: bar03:
 ; LINUX-64-STATIC: movl    $dsrc, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar03:
+; LINUX-32-STATIC-LABEL: bar03:
 ; LINUX-32-STATIC: 	movl	$dsrc, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar03:
+; LINUX-32-PIC-LABEL: bar03:
 ; LINUX-32-PIC: 	movl	$dsrc, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar03:
+; LINUX-64-PIC-LABEL: bar03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5097,19 +5097,19 @@ entry:
 define i8* @bar04() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @ddst to i8*)
-; LINUX-64-STATIC: bar04:
+; LINUX-64-STATIC-LABEL: bar04:
 ; LINUX-64-STATIC: movl    $ddst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar04:
+; LINUX-32-STATIC-LABEL: bar04:
 ; LINUX-32-STATIC: 	movl	$ddst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar04:
+; LINUX-32-PIC-LABEL: bar04:
 ; LINUX-32-PIC: 	movl	$ddst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar04:
+; LINUX-64-PIC-LABEL: bar04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5144,19 +5144,19 @@ entry:
 define i8* @bar05() nounwind {
 entry:
 	ret i8* bitcast (i32** @dptr to i8*)
-; LINUX-64-STATIC: bar05:
+; LINUX-64-STATIC-LABEL: bar05:
 ; LINUX-64-STATIC: movl    $dptr, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar05:
+; LINUX-32-STATIC-LABEL: bar05:
 ; LINUX-32-STATIC: 	movl	$dptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar05:
+; LINUX-32-PIC-LABEL: bar05:
 ; LINUX-32-PIC: 	movl	$dptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar05:
+; LINUX-64-PIC-LABEL: bar05:
 ; LINUX-64-PIC: 	movq	dptr@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5191,19 +5191,19 @@ entry:
 define i8* @bar06() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @lsrc to i8*)
-; LINUX-64-STATIC: bar06:
+; LINUX-64-STATIC-LABEL: bar06:
 ; LINUX-64-STATIC: movl    $lsrc, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar06:
+; LINUX-32-STATIC-LABEL: bar06:
 ; LINUX-32-STATIC: 	movl	$lsrc, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar06:
+; LINUX-32-PIC-LABEL: bar06:
 ; LINUX-32-PIC: 	movl	$lsrc, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar06:
+; LINUX-64-PIC-LABEL: bar06:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5238,19 +5238,19 @@ entry:
 define i8* @bar07() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @ldst to i8*)
-; LINUX-64-STATIC: bar07:
+; LINUX-64-STATIC-LABEL: bar07:
 ; LINUX-64-STATIC: movl    $ldst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar07:
+; LINUX-32-STATIC-LABEL: bar07:
 ; LINUX-32-STATIC: 	movl	$ldst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar07:
+; LINUX-32-PIC-LABEL: bar07:
 ; LINUX-32-PIC: 	movl	$ldst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar07:
+; LINUX-64-PIC-LABEL: bar07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5285,19 +5285,19 @@ entry:
 define i8* @bar08() nounwind {
 entry:
 	ret i8* bitcast (i32** @lptr to i8*)
-; LINUX-64-STATIC: bar08:
+; LINUX-64-STATIC-LABEL: bar08:
 ; LINUX-64-STATIC: movl    $lptr, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bar08:
+; LINUX-32-STATIC-LABEL: bar08:
 ; LINUX-32-STATIC: 	movl	$lptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bar08:
+; LINUX-32-PIC-LABEL: bar08:
 ; LINUX-32-PIC: 	movl	$lptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bar08:
+; LINUX-64-PIC-LABEL: bar08:
 ; LINUX-64-PIC: 	leaq	lptr(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5332,19 +5332,19 @@ entry:
 define i8* @har00() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @src to i8*)
-; LINUX-64-STATIC: har00:
+; LINUX-64-STATIC-LABEL: har00:
 ; LINUX-64-STATIC: movl    $src, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har00:
+; LINUX-32-STATIC-LABEL: har00:
 ; LINUX-32-STATIC: 	movl	$src, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har00:
+; LINUX-32-PIC-LABEL: har00:
 ; LINUX-32-PIC: 	movl	$src, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har00:
+; LINUX-64-PIC-LABEL: har00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5379,19 +5379,19 @@ entry:
 define i8* @hxr00() nounwind {
 entry:
 	ret i8* bitcast ([32 x i32]* @xsrc to i8*)
-; LINUX-64-STATIC: hxr00:
+; LINUX-64-STATIC-LABEL: hxr00:
 ; LINUX-64-STATIC: movl    $xsrc, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: hxr00:
+; LINUX-32-STATIC-LABEL: hxr00:
 ; LINUX-32-STATIC: 	movl	$xsrc, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: hxr00:
+; LINUX-32-PIC-LABEL: hxr00:
 ; LINUX-32-PIC: 	movl	$xsrc, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: hxr00:
+; LINUX-64-PIC-LABEL: hxr00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5426,19 +5426,19 @@ entry:
 define i8* @har01() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @dst to i8*)
-; LINUX-64-STATIC: har01:
+; LINUX-64-STATIC-LABEL: har01:
 ; LINUX-64-STATIC: movl    $dst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har01:
+; LINUX-32-STATIC-LABEL: har01:
 ; LINUX-32-STATIC: 	movl	$dst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har01:
+; LINUX-32-PIC-LABEL: har01:
 ; LINUX-32-PIC: 	movl	$dst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har01:
+; LINUX-64-PIC-LABEL: har01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5473,19 +5473,19 @@ entry:
 define i8* @hxr01() nounwind {
 entry:
 	ret i8* bitcast ([32 x i32]* @xdst to i8*)
-; LINUX-64-STATIC: hxr01:
+; LINUX-64-STATIC-LABEL: hxr01:
 ; LINUX-64-STATIC: movl    $xdst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: hxr01:
+; LINUX-32-STATIC-LABEL: hxr01:
 ; LINUX-32-STATIC: 	movl	$xdst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: hxr01:
+; LINUX-32-PIC-LABEL: hxr01:
 ; LINUX-32-PIC: 	movl	$xdst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: hxr01:
+; LINUX-64-PIC-LABEL: hxr01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5522,19 +5522,19 @@ entry:
 	%0 = load i32** @ptr, align 8
 	%1 = bitcast i32* %0 to i8*
 	ret i8* %1
-; LINUX-64-STATIC: har02:
+; LINUX-64-STATIC-LABEL: har02:
 ; LINUX-64-STATIC: movq    ptr(%rip), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har02:
+; LINUX-32-STATIC-LABEL: har02:
 ; LINUX-32-STATIC: 	movl	ptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har02:
+; LINUX-32-PIC-LABEL: har02:
 ; LINUX-32-PIC: 	movl	ptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har02:
+; LINUX-64-PIC-LABEL: har02:
 ; LINUX-64-PIC: 	movq	ptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -5575,19 +5575,19 @@ entry:
 define i8* @har03() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @dsrc to i8*)
-; LINUX-64-STATIC: har03:
+; LINUX-64-STATIC-LABEL: har03:
 ; LINUX-64-STATIC: movl    $dsrc, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har03:
+; LINUX-32-STATIC-LABEL: har03:
 ; LINUX-32-STATIC: 	movl	$dsrc, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har03:
+; LINUX-32-PIC-LABEL: har03:
 ; LINUX-32-PIC: 	movl	$dsrc, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har03:
+; LINUX-64-PIC-LABEL: har03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5622,19 +5622,19 @@ entry:
 define i8* @har04() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @ddst to i8*)
-; LINUX-64-STATIC: har04:
+; LINUX-64-STATIC-LABEL: har04:
 ; LINUX-64-STATIC: movl    $ddst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har04:
+; LINUX-32-STATIC-LABEL: har04:
 ; LINUX-32-STATIC: 	movl	$ddst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har04:
+; LINUX-32-PIC-LABEL: har04:
 ; LINUX-32-PIC: 	movl	$ddst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har04:
+; LINUX-64-PIC-LABEL: har04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5671,19 +5671,19 @@ entry:
 	%0 = load i32** @dptr, align 8
 	%1 = bitcast i32* %0 to i8*
 	ret i8* %1
-; LINUX-64-STATIC: har05:
+; LINUX-64-STATIC-LABEL: har05:
 ; LINUX-64-STATIC: movq    dptr(%rip), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har05:
+; LINUX-32-STATIC-LABEL: har05:
 ; LINUX-32-STATIC: 	movl	dptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har05:
+; LINUX-32-PIC-LABEL: har05:
 ; LINUX-32-PIC: 	movl	dptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har05:
+; LINUX-64-PIC-LABEL: har05:
 ; LINUX-64-PIC: 	movq	dptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -5719,19 +5719,19 @@ entry:
 define i8* @har06() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @lsrc to i8*)
-; LINUX-64-STATIC: har06:
+; LINUX-64-STATIC-LABEL: har06:
 ; LINUX-64-STATIC: movl    $lsrc, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har06:
+; LINUX-32-STATIC-LABEL: har06:
 ; LINUX-32-STATIC: 	movl	$lsrc, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har06:
+; LINUX-32-PIC-LABEL: har06:
 ; LINUX-32-PIC: 	movl	$lsrc, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har06:
+; LINUX-64-PIC-LABEL: har06:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5766,19 +5766,19 @@ entry:
 define i8* @har07() nounwind {
 entry:
 	ret i8* bitcast ([131072 x i32]* @ldst to i8*)
-; LINUX-64-STATIC: har07:
+; LINUX-64-STATIC-LABEL: har07:
 ; LINUX-64-STATIC: movl    $ldst, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har07:
+; LINUX-32-STATIC-LABEL: har07:
 ; LINUX-32-STATIC: 	movl	$ldst, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har07:
+; LINUX-32-PIC-LABEL: har07:
 ; LINUX-32-PIC: 	movl	$ldst, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har07:
+; LINUX-64-PIC-LABEL: har07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5815,19 +5815,19 @@ entry:
 	%0 = load i32** @lptr, align 8
 	%1 = bitcast i32* %0 to i8*
 	ret i8* %1
-; LINUX-64-STATIC: har08:
+; LINUX-64-STATIC-LABEL: har08:
 ; LINUX-64-STATIC: movq    lptr(%rip), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: har08:
+; LINUX-32-STATIC-LABEL: har08:
 ; LINUX-32-STATIC: 	movl	lptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: har08:
+; LINUX-32-PIC-LABEL: har08:
 ; LINUX-32-PIC: 	movl	lptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: har08:
+; LINUX-64-PIC-LABEL: har08:
 ; LINUX-64-PIC: 	movq	lptr(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -5862,19 +5862,19 @@ entry:
 define i8* @bat00() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @src, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat00:
+; LINUX-64-STATIC-LABEL: bat00:
 ; LINUX-64-STATIC: movl    $src+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat00:
+; LINUX-32-STATIC-LABEL: bat00:
 ; LINUX-32-STATIC: 	movl	$src+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat00:
+; LINUX-32-PIC-LABEL: bat00:
 ; LINUX-32-PIC: 	movl	$src+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat00:
+; LINUX-64-PIC-LABEL: bat00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -5915,19 +5915,19 @@ entry:
 define i8* @bxt00() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bxt00:
+; LINUX-64-STATIC-LABEL: bxt00:
 ; LINUX-64-STATIC: movl    $xsrc+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bxt00:
+; LINUX-32-STATIC-LABEL: bxt00:
 ; LINUX-32-STATIC: 	movl	$xsrc+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bxt00:
+; LINUX-32-PIC-LABEL: bxt00:
 ; LINUX-32-PIC: 	movl	$xsrc+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bxt00:
+; LINUX-64-PIC-LABEL: bxt00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -5968,19 +5968,19 @@ entry:
 define i8* @bat01() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat01:
+; LINUX-64-STATIC-LABEL: bat01:
 ; LINUX-64-STATIC: movl    $dst+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat01:
+; LINUX-32-STATIC-LABEL: bat01:
 ; LINUX-32-STATIC: 	movl	$dst+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat01:
+; LINUX-32-PIC-LABEL: bat01:
 ; LINUX-32-PIC: 	movl	$dst+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat01:
+; LINUX-64-PIC-LABEL: bat01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6021,19 +6021,19 @@ entry:
 define i8* @bxt01() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bxt01:
+; LINUX-64-STATIC-LABEL: bxt01:
 ; LINUX-64-STATIC: movl    $xdst+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bxt01:
+; LINUX-32-STATIC-LABEL: bxt01:
 ; LINUX-32-STATIC: 	movl	$xdst+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bxt01:
+; LINUX-32-PIC-LABEL: bxt01:
 ; LINUX-32-PIC: 	movl	$xdst+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bxt01:
+; LINUX-64-PIC-LABEL: bxt01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6077,22 +6077,22 @@ entry:
 	%1 = getelementptr i32* %0, i64 16
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: bat02:
+; LINUX-64-STATIC-LABEL: bat02:
 ; LINUX-64-STATIC: movq    ptr(%rip), %rax
 ; LINUX-64-STATIC: addq    $64, %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat02:
+; LINUX-32-STATIC-LABEL: bat02:
 ; LINUX-32-STATIC: 	movl	ptr, %eax
 ; LINUX-32-STATIC-NEXT: 	addl	$64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat02:
+; LINUX-32-PIC-LABEL: bat02:
 ; LINUX-32-PIC: 	movl	ptr, %eax
 ; LINUX-32-PIC-NEXT: 	addl	$64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat02:
+; LINUX-64-PIC-LABEL: bat02:
 ; LINUX-64-PIC: 	movq	ptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
@@ -6140,19 +6140,19 @@ entry:
 define i8* @bat03() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat03:
+; LINUX-64-STATIC-LABEL: bat03:
 ; LINUX-64-STATIC: movl    $dsrc+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat03:
+; LINUX-32-STATIC-LABEL: bat03:
 ; LINUX-32-STATIC: 	movl	$dsrc+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat03:
+; LINUX-32-PIC-LABEL: bat03:
 ; LINUX-32-PIC: 	movl	$dsrc+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat03:
+; LINUX-64-PIC-LABEL: bat03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6188,19 +6188,19 @@ entry:
 define i8* @bat04() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat04:
+; LINUX-64-STATIC-LABEL: bat04:
 ; LINUX-64-STATIC: movl    $ddst+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat04:
+; LINUX-32-STATIC-LABEL: bat04:
 ; LINUX-32-STATIC: 	movl	$ddst+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat04:
+; LINUX-32-PIC-LABEL: bat04:
 ; LINUX-32-PIC: 	movl	$ddst+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat04:
+; LINUX-64-PIC-LABEL: bat04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6239,22 +6239,22 @@ entry:
 	%1 = getelementptr i32* %0, i64 16
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: bat05:
+; LINUX-64-STATIC-LABEL: bat05:
 ; LINUX-64-STATIC: movq    dptr(%rip), %rax
 ; LINUX-64-STATIC: addq    $64, %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat05:
+; LINUX-32-STATIC-LABEL: bat05:
 ; LINUX-32-STATIC: 	movl	dptr, %eax
 ; LINUX-32-STATIC-NEXT: 	addl	$64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat05:
+; LINUX-32-PIC-LABEL: bat05:
 ; LINUX-32-PIC: 	movl	dptr, %eax
 ; LINUX-32-PIC-NEXT: 	addl	$64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat05:
+; LINUX-64-PIC-LABEL: bat05:
 ; LINUX-64-PIC: 	movq	dptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
@@ -6297,19 +6297,19 @@ entry:
 define i8* @bat06() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat06:
+; LINUX-64-STATIC-LABEL: bat06:
 ; LINUX-64-STATIC: movl    $lsrc+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat06:
+; LINUX-32-STATIC-LABEL: bat06:
 ; LINUX-32-STATIC: 	movl	$lsrc+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat06:
+; LINUX-32-PIC-LABEL: bat06:
 ; LINUX-32-PIC: 	movl	$lsrc+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat06:
+; LINUX-64-PIC-LABEL: bat06:
 ; LINUX-64-PIC: 	leaq	lsrc+64(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -6344,19 +6344,19 @@ entry:
 define i8* @bat07() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat07:
+; LINUX-64-STATIC-LABEL: bat07:
 ; LINUX-64-STATIC: movl    $ldst+64, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat07:
+; LINUX-32-STATIC-LABEL: bat07:
 ; LINUX-32-STATIC: 	movl	$ldst+64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat07:
+; LINUX-32-PIC-LABEL: bat07:
 ; LINUX-32-PIC: 	movl	$ldst+64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat07:
+; LINUX-64-PIC-LABEL: bat07:
 ; LINUX-64-PIC: 	leaq	ldst+64(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -6394,22 +6394,22 @@ entry:
 	%1 = getelementptr i32* %0, i64 16
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: bat08:
+; LINUX-64-STATIC-LABEL: bat08:
 ; LINUX-64-STATIC: movq    lptr(%rip), %rax
 ; LINUX-64-STATIC: addq    $64, %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bat08:
+; LINUX-32-STATIC-LABEL: bat08:
 ; LINUX-32-STATIC: 	movl	lptr, %eax
 ; LINUX-32-STATIC-NEXT: 	addl	$64, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bat08:
+; LINUX-32-PIC-LABEL: bat08:
 ; LINUX-32-PIC: 	movl	lptr, %eax
 ; LINUX-32-PIC-NEXT: 	addl	$64, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bat08:
+; LINUX-64-PIC-LABEL: bat08:
 ; LINUX-64-PIC: 	movq	lptr(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6451,19 +6451,19 @@ entry:
 define i8* @bam00() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @src, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam00:
+; LINUX-64-STATIC-LABEL: bam00:
 ; LINUX-64-STATIC: movl    $src+262144, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam00:
+; LINUX-32-STATIC-LABEL: bam00:
 ; LINUX-32-STATIC: 	movl	$src+262144, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam00:
+; LINUX-32-PIC-LABEL: bam00:
 ; LINUX-32-PIC: 	movl	$src+262144, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam00:
+; LINUX-64-PIC-LABEL: bam00:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	addq	src@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6504,19 +6504,19 @@ entry:
 define i8* @bam01() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam01:
+; LINUX-64-STATIC-LABEL: bam01:
 ; LINUX-64-STATIC: movl    $dst+262144, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam01:
+; LINUX-32-STATIC-LABEL: bam01:
 ; LINUX-32-STATIC: 	movl	$dst+262144, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam01:
+; LINUX-32-PIC-LABEL: bam01:
 ; LINUX-32-PIC: 	movl	$dst+262144, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam01:
+; LINUX-64-PIC-LABEL: bam01:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	addq	dst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6557,19 +6557,19 @@ entry:
 define i8* @bxm01() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bxm01:
+; LINUX-64-STATIC-LABEL: bxm01:
 ; LINUX-64-STATIC: movl    $xdst+262144, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bxm01:
+; LINUX-32-STATIC-LABEL: bxm01:
 ; LINUX-32-STATIC: 	movl	$xdst+262144, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bxm01:
+; LINUX-32-PIC-LABEL: bxm01:
 ; LINUX-32-PIC: 	movl	$xdst+262144, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bxm01:
+; LINUX-64-PIC-LABEL: bxm01:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	addq	xdst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6613,22 +6613,22 @@ entry:
 	%1 = getelementptr i32* %0, i64 65536
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: bam02:
+; LINUX-64-STATIC-LABEL: bam02:
 ; LINUX-64-STATIC: movl    $262144, %eax
 ; LINUX-64-STATIC: addq    ptr(%rip), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam02:
+; LINUX-32-STATIC-LABEL: bam02:
 ; LINUX-32-STATIC: 	movl	$262144, %eax
 ; LINUX-32-STATIC-NEXT: 	addl	ptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam02:
+; LINUX-32-PIC-LABEL: bam02:
 ; LINUX-32-PIC: 	movl	$262144, %eax
 ; LINUX-32-PIC-NEXT: 	addl	ptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam02:
+; LINUX-64-PIC-LABEL: bam02:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	movq	ptr@GOTPCREL(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	addq	([[RCX]]), %rax
@@ -6676,19 +6676,19 @@ entry:
 define i8* @bam03() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam03:
+; LINUX-64-STATIC-LABEL: bam03:
 ; LINUX-64-STATIC: movl    $dsrc+262144, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam03:
+; LINUX-32-STATIC-LABEL: bam03:
 ; LINUX-32-STATIC: 	movl	$dsrc+262144, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam03:
+; LINUX-32-PIC-LABEL: bam03:
 ; LINUX-32-PIC: 	movl	$dsrc+262144, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam03:
+; LINUX-64-PIC-LABEL: bam03:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	addq	dsrc@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6724,19 +6724,19 @@ entry:
 define i8* @bam04() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam04:
+; LINUX-64-STATIC-LABEL: bam04:
 ; LINUX-64-STATIC: movl    $ddst+262144, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam04:
+; LINUX-32-STATIC-LABEL: bam04:
 ; LINUX-32-STATIC: 	movl	$ddst+262144, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam04:
+; LINUX-32-PIC-LABEL: bam04:
 ; LINUX-32-PIC: 	movl	$ddst+262144, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam04:
+; LINUX-64-PIC-LABEL: bam04:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	addq	ddst@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6775,22 +6775,22 @@ entry:
 	%1 = getelementptr i32* %0, i64 65536
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: bam05:
+; LINUX-64-STATIC-LABEL: bam05:
 ; LINUX-64-STATIC: movl    $262144, %eax
 ; LINUX-64-STATIC: addq    dptr(%rip), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam05:
+; LINUX-32-STATIC-LABEL: bam05:
 ; LINUX-32-STATIC: 	movl	$262144, %eax
 ; LINUX-32-STATIC-NEXT: 	addl	dptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam05:
+; LINUX-32-PIC-LABEL: bam05:
 ; LINUX-32-PIC: 	movl	$262144, %eax
 ; LINUX-32-PIC-NEXT: 	addl	dptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam05:
+; LINUX-64-PIC-LABEL: bam05:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	movq	dptr@GOTPCREL(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	addq	([[RCX]]), %rax
@@ -6833,19 +6833,19 @@ entry:
 define i8* @bam06() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam06:
+; LINUX-64-STATIC-LABEL: bam06:
 ; LINUX-64-STATIC: movl    $lsrc+262144, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam06:
+; LINUX-32-STATIC-LABEL: bam06:
 ; LINUX-32-STATIC: 	movl	$lsrc+262144, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam06:
+; LINUX-32-PIC-LABEL: bam06:
 ; LINUX-32-PIC: 	movl	$lsrc+262144, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam06:
+; LINUX-64-PIC-LABEL: bam06:
 ; LINUX-64-PIC: 	leaq	lsrc+262144(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -6880,19 +6880,19 @@ entry:
 define i8* @bam07() nounwind {
 entry:
 	ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam07:
+; LINUX-64-STATIC-LABEL: bam07:
 ; LINUX-64-STATIC: movl    $ldst+262144, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam07:
+; LINUX-32-STATIC-LABEL: bam07:
 ; LINUX-32-STATIC: 	movl	$ldst+262144, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam07:
+; LINUX-32-PIC-LABEL: bam07:
 ; LINUX-32-PIC: 	movl	$ldst+262144, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam07:
+; LINUX-64-PIC-LABEL: bam07:
 ; LINUX-64-PIC: 	leaq	ldst+262144(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -6930,22 +6930,22 @@ entry:
 	%1 = getelementptr i32* %0, i64 65536
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: bam08:
+; LINUX-64-STATIC-LABEL: bam08:
 ; LINUX-64-STATIC: movl    $262144, %eax
 ; LINUX-64-STATIC: addq    lptr(%rip), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: bam08:
+; LINUX-32-STATIC-LABEL: bam08:
 ; LINUX-32-STATIC: 	movl	$262144, %eax
 ; LINUX-32-STATIC-NEXT: 	addl	lptr, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: bam08:
+; LINUX-32-PIC-LABEL: bam08:
 ; LINUX-32-PIC: 	movl	$262144, %eax
 ; LINUX-32-PIC-NEXT: 	addl	lptr, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: bam08:
+; LINUX-64-PIC-LABEL: bam08:
 ; LINUX-64-PIC: 	movl	$262144, %eax
 ; LINUX-64-PIC-NEXT: 	addq	lptr(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -6990,21 +6990,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @src, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cat00:
+; LINUX-64-STATIC-LABEL: cat00:
 ; LINUX-64-STATIC: leaq    src+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat00:
+; LINUX-32-STATIC-LABEL: cat00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	src+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat00:
+; LINUX-32-PIC-LABEL: cat00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	src+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat00:
+; LINUX-64-PIC-LABEL: cat00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7051,21 +7051,21 @@ entry:
 	%1 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cxt00:
+; LINUX-64-STATIC-LABEL: cxt00:
 ; LINUX-64-STATIC: leaq    xsrc+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cxt00:
+; LINUX-32-STATIC-LABEL: cxt00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	xsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cxt00:
+; LINUX-32-PIC-LABEL: cxt00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	xsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cxt00:
+; LINUX-64-PIC-LABEL: cxt00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7112,21 +7112,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cat01:
+; LINUX-64-STATIC-LABEL: cat01:
 ; LINUX-64-STATIC: leaq    dst+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat01:
+; LINUX-32-STATIC-LABEL: cat01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	dst+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat01:
+; LINUX-32-PIC-LABEL: cat01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	dst+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat01:
+; LINUX-64-PIC-LABEL: cat01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7173,21 +7173,21 @@ entry:
 	%1 = getelementptr [32 x i32]* @xdst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cxt01:
+; LINUX-64-STATIC-LABEL: cxt01:
 ; LINUX-64-STATIC: leaq    xdst+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cxt01:
+; LINUX-32-STATIC-LABEL: cxt01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	xdst+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cxt01:
+; LINUX-32-PIC-LABEL: cxt01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	xdst+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cxt01:
+; LINUX-64-PIC-LABEL: cxt01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7235,24 +7235,24 @@ entry:
 	%2 = getelementptr i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
-; LINUX-64-STATIC: cat02:
+; LINUX-64-STATIC-LABEL: cat02:
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-STATIC: leaq    64([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat02:
+; LINUX-32-STATIC-LABEL: cat02:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat02:
+; LINUX-32-PIC-LABEL: cat02:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat02:
+; LINUX-64-PIC-LABEL: cat02:
 ; LINUX-64-PIC: 	movq	ptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
@@ -7306,21 +7306,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cat03:
+; LINUX-64-STATIC-LABEL: cat03:
 ; LINUX-64-STATIC: leaq    dsrc+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat03:
+; LINUX-32-STATIC-LABEL: cat03:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	dsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat03:
+; LINUX-32-PIC-LABEL: cat03:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	dsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat03:
+; LINUX-64-PIC-LABEL: cat03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7365,21 +7365,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cat04:
+; LINUX-64-STATIC-LABEL: cat04:
 ; LINUX-64-STATIC: leaq    ddst+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat04:
+; LINUX-32-STATIC-LABEL: cat04:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ddst+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat04:
+; LINUX-32-PIC-LABEL: cat04:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ddst+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat04:
+; LINUX-64-PIC-LABEL: cat04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7425,24 +7425,24 @@ entry:
 	%2 = getelementptr i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
-; LINUX-64-STATIC: cat05:
+; LINUX-64-STATIC-LABEL: cat05:
 ; LINUX-64-STATIC: movq    dptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-STATIC: leaq    64([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat05:
+; LINUX-32-STATIC-LABEL: cat05:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat05:
+; LINUX-32-PIC-LABEL: cat05:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat05:
+; LINUX-64-PIC-LABEL: cat05:
 ; LINUX-64-PIC: 	movq	dptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
@@ -7491,21 +7491,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cat06:
+; LINUX-64-STATIC-LABEL: cat06:
 ; LINUX-64-STATIC: leaq    lsrc+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat06:
+; LINUX-32-STATIC-LABEL: cat06:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	lsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat06:
+; LINUX-32-PIC-LABEL: cat06:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	lsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat06:
+; LINUX-64-PIC-LABEL: cat06:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7550,21 +7550,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cat07:
+; LINUX-64-STATIC-LABEL: cat07:
 ; LINUX-64-STATIC: leaq    ldst+64(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat07:
+; LINUX-32-STATIC-LABEL: cat07:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ldst+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat07:
+; LINUX-32-PIC-LABEL: cat07:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ldst+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat07:
+; LINUX-64-PIC-LABEL: cat07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7610,24 +7610,24 @@ entry:
 	%2 = getelementptr i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
-; LINUX-64-STATIC: cat08:
+; LINUX-64-STATIC-LABEL: cat08:
 ; LINUX-64-STATIC: movq    lptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-STATIC: leaq    64([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cat08:
+; LINUX-32-STATIC-LABEL: cat08:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cat08:
+; LINUX-32-PIC-LABEL: cat08:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cat08:
+; LINUX-64-PIC-LABEL: cat08:
 ; LINUX-64-PIC: 	movq	lptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7675,21 +7675,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @src, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cam00:
+; LINUX-64-STATIC-LABEL: cam00:
 ; LINUX-64-STATIC: leaq    src+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam00:
+; LINUX-32-STATIC-LABEL: cam00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	src+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam00:
+; LINUX-32-PIC-LABEL: cam00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	src+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam00:
+; LINUX-64-PIC-LABEL: cam00:
 ; LINUX-64-PIC: 	movq	src@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7736,21 +7736,21 @@ entry:
 	%1 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cxm00:
+; LINUX-64-STATIC-LABEL: cxm00:
 ; LINUX-64-STATIC: leaq    xsrc+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cxm00:
+; LINUX-32-STATIC-LABEL: cxm00:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	xsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cxm00:
+; LINUX-32-PIC-LABEL: cxm00:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	xsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cxm00:
+; LINUX-64-PIC-LABEL: cxm00:
 ; LINUX-64-PIC: 	movq	xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7797,21 +7797,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cam01:
+; LINUX-64-STATIC-LABEL: cam01:
 ; LINUX-64-STATIC: leaq    dst+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam01:
+; LINUX-32-STATIC-LABEL: cam01:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	dst+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam01:
+; LINUX-32-PIC-LABEL: cam01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	dst+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam01:
+; LINUX-64-PIC-LABEL: cam01:
 ; LINUX-64-PIC: 	movq	dst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7858,21 +7858,21 @@ entry:
 	%1 = getelementptr [32 x i32]* @xdst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cxm01:
+; LINUX-64-STATIC-LABEL: cxm01:
 ; LINUX-64-STATIC: leaq    xdst+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cxm01:
+; LINUX-32-STATIC-LABEL: cxm01:
 ; LINUX-32-STATIC: 	movl	4(%esp), %eax
 ; LINUX-32-STATIC-NEXT: 	leal	xdst+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cxm01:
+; LINUX-32-PIC-LABEL: cxm01:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	xdst+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cxm01:
+; LINUX-64-PIC-LABEL: cxm01:
 ; LINUX-64-PIC: 	movq	xdst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -7920,24 +7920,24 @@ entry:
 	%2 = getelementptr i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
-; LINUX-64-STATIC: cam02:
+; LINUX-64-STATIC-LABEL: cam02:
 ; LINUX-64-STATIC: movq    ptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-STATIC: leaq    262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam02:
+; LINUX-32-STATIC-LABEL: cam02:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam02:
+; LINUX-32-PIC-LABEL: cam02:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam02:
+; LINUX-64-PIC-LABEL: cam02:
 ; LINUX-64-PIC: 	movq	ptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
@@ -7991,21 +7991,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cam03:
+; LINUX-64-STATIC-LABEL: cam03:
 ; LINUX-64-STATIC: leaq    dsrc+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam03:
+; LINUX-32-STATIC-LABEL: cam03:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	dsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam03:
+; LINUX-32-PIC-LABEL: cam03:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	dsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam03:
+; LINUX-64-PIC-LABEL: cam03:
 ; LINUX-64-PIC: 	movq	dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -8050,21 +8050,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cam04:
+; LINUX-64-STATIC-LABEL: cam04:
 ; LINUX-64-STATIC: leaq    ddst+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam04:
+; LINUX-32-STATIC-LABEL: cam04:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ddst+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam04:
+; LINUX-32-PIC-LABEL: cam04:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ddst+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam04:
+; LINUX-64-PIC-LABEL: cam04:
 ; LINUX-64-PIC: 	movq	ddst@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -8110,24 +8110,24 @@ entry:
 	%2 = getelementptr i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
-; LINUX-64-STATIC: cam05:
+; LINUX-64-STATIC-LABEL: cam05:
 ; LINUX-64-STATIC: movq    dptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-STATIC: leaq    262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam05:
+; LINUX-32-STATIC-LABEL: cam05:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam05:
+; LINUX-32-PIC-LABEL: cam05:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam05:
+; LINUX-64-PIC-LABEL: cam05:
 ; LINUX-64-PIC: 	movq	dptr@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
@@ -8176,21 +8176,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cam06:
+; LINUX-64-STATIC-LABEL: cam06:
 ; LINUX-64-STATIC: leaq    lsrc+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam06:
+; LINUX-32-STATIC-LABEL: cam06:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	lsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam06:
+; LINUX-32-PIC-LABEL: cam06:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	lsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam06:
+; LINUX-64-PIC-LABEL: cam06:
 ; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -8235,21 +8235,21 @@ entry:
 	%1 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
 	%2 = bitcast i32* %1 to i8*
 	ret i8* %2
-; LINUX-64-STATIC: cam07:
+; LINUX-64-STATIC-LABEL: cam07:
 ; LINUX-64-STATIC: leaq    ldst+262144(,%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam07:
+; LINUX-32-STATIC-LABEL: cam07:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	ldst+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam07:
+; LINUX-32-PIC-LABEL: cam07:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	ldst+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam07:
+; LINUX-64-PIC-LABEL: cam07:
 ; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -8295,24 +8295,24 @@ entry:
 	%2 = getelementptr i32* %0, i64 %1
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
-; LINUX-64-STATIC: cam08:
+; LINUX-64-STATIC-LABEL: cam08:
 ; LINUX-64-STATIC: movq    lptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-STATIC: leaq    262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: cam08:
+; LINUX-32-STATIC-LABEL: cam08:
 ; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-STATIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: cam08:
+; LINUX-32-PIC-LABEL: cam08:
 ; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
 ; LINUX-32-PIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: cam08:
+; LINUX-64-PIC-LABEL: cam08:
 ; LINUX-64-PIC: 	movq	lptr(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
@@ -8364,7 +8364,7 @@ entry:
 	call void @x() nounwind
 	call void @x() nounwind
 	ret void
-; LINUX-64-STATIC: lcallee:
+; LINUX-64-STATIC-LABEL: lcallee:
 ; LINUX-64-STATIC: callq   x
 ; LINUX-64-STATIC: callq   x
 ; LINUX-64-STATIC: callq   x
@@ -8374,7 +8374,7 @@ entry:
 ; LINUX-64-STATIC: callq   x
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: lcallee:
+; LINUX-32-STATIC-LABEL: lcallee:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	x
 ; LINUX-32-STATIC-NEXT: 	calll	x
@@ -8386,7 +8386,7 @@ entry:
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: lcallee:
+; LINUX-32-PIC-LABEL: lcallee:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	x
 ; LINUX-32-PIC-NEXT: 	calll	x
@@ -8399,7 +8399,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: lcallee:
+; LINUX-64-PIC-LABEL: lcallee:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	x@PLT
 ; LINUX-64-PIC-NEXT: 	callq	x@PLT
@@ -8496,7 +8496,7 @@ entry:
 	call void @y() nounwind
 	call void @y() nounwind
 	ret void
-; LINUX-64-STATIC: dcallee:
+; LINUX-64-STATIC-LABEL: dcallee:
 ; LINUX-64-STATIC: callq   y
 ; LINUX-64-STATIC: callq   y
 ; LINUX-64-STATIC: callq   y
@@ -8506,7 +8506,7 @@ entry:
 ; LINUX-64-STATIC: callq   y
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: dcallee:
+; LINUX-32-STATIC-LABEL: dcallee:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	y
 ; LINUX-32-STATIC-NEXT: 	calll	y
@@ -8518,7 +8518,7 @@ entry:
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: dcallee:
+; LINUX-32-PIC-LABEL: dcallee:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	y
 ; LINUX-32-PIC-NEXT: 	calll	y
@@ -8531,7 +8531,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: dcallee:
+; LINUX-64-PIC-LABEL: dcallee:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	y@PLT
 ; LINUX-64-PIC-NEXT: 	callq	y@PLT
@@ -8621,19 +8621,19 @@ declare void @y()
 define void ()* @address() nounwind {
 entry:
 	ret void ()* @callee
-; LINUX-64-STATIC: address:
+; LINUX-64-STATIC-LABEL: address:
 ; LINUX-64-STATIC: movl    $callee, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: address:
+; LINUX-32-STATIC-LABEL: address:
 ; LINUX-32-STATIC: 	movl	$callee, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: address:
+; LINUX-32-PIC-LABEL: address:
 ; LINUX-32-PIC: 	movl	$callee, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: address:
+; LINUX-64-PIC-LABEL: address:
 ; LINUX-64-PIC: 	movq	callee@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -8670,19 +8670,19 @@ declare void @callee()
 define void ()* @laddress() nounwind {
 entry:
 	ret void ()* @lcallee
-; LINUX-64-STATIC: laddress:
+; LINUX-64-STATIC-LABEL: laddress:
 ; LINUX-64-STATIC: movl    $lcallee, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: laddress:
+; LINUX-32-STATIC-LABEL: laddress:
 ; LINUX-32-STATIC: 	movl	$lcallee, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: laddress:
+; LINUX-32-PIC-LABEL: laddress:
 ; LINUX-32-PIC: 	movl	$lcallee, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: laddress:
+; LINUX-64-PIC-LABEL: laddress:
 ; LINUX-64-PIC: 	movq	lcallee@GOTPCREL(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -8717,19 +8717,19 @@ entry:
 define void ()* @daddress() nounwind {
 entry:
 	ret void ()* @dcallee
-; LINUX-64-STATIC: daddress:
+; LINUX-64-STATIC-LABEL: daddress:
 ; LINUX-64-STATIC: movl    $dcallee, %eax
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: daddress:
+; LINUX-32-STATIC-LABEL: daddress:
 ; LINUX-32-STATIC: 	movl	$dcallee, %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: daddress:
+; LINUX-32-PIC-LABEL: daddress:
 ; LINUX-32-PIC: 	movl	$dcallee, %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: daddress:
+; LINUX-64-PIC-LABEL: daddress:
 ; LINUX-64-PIC: 	leaq	dcallee(%rip), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -8766,19 +8766,19 @@ entry:
 	call void @callee() nounwind
 	call void @callee() nounwind
 	ret void
-; LINUX-64-STATIC: caller:
+; LINUX-64-STATIC-LABEL: caller:
 ; LINUX-64-STATIC: callq   callee
 ; LINUX-64-STATIC: callq   callee
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: caller:
+; LINUX-32-STATIC-LABEL: caller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	callee
 ; LINUX-32-STATIC-NEXT: 	calll	callee
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: caller:
+; LINUX-32-PIC-LABEL: caller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	callee
 ; LINUX-32-PIC-NEXT: 	calll	callee
@@ -8786,7 +8786,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: caller:
+; LINUX-64-PIC-LABEL: caller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	callee@PLT
 ; LINUX-64-PIC-NEXT: 	callq	callee@PLT
@@ -8841,19 +8841,19 @@ entry:
 	call void @dcallee() nounwind
 	call void @dcallee() nounwind
 	ret void
-; LINUX-64-STATIC: dcaller:
+; LINUX-64-STATIC-LABEL: dcaller:
 ; LINUX-64-STATIC: callq   dcallee
 ; LINUX-64-STATIC: callq   dcallee
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: dcaller:
+; LINUX-32-STATIC-LABEL: dcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	dcallee
 ; LINUX-32-STATIC-NEXT: 	calll	dcallee
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: dcaller:
+; LINUX-32-PIC-LABEL: dcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	dcallee
 ; LINUX-32-PIC-NEXT: 	calll	dcallee
@@ -8861,7 +8861,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: dcaller:
+; LINUX-64-PIC-LABEL: dcaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	dcallee
 ; LINUX-64-PIC-NEXT: 	callq	dcallee
@@ -8916,19 +8916,19 @@ entry:
 	call void @lcallee() nounwind
 	call void @lcallee() nounwind
 	ret void
-; LINUX-64-STATIC: lcaller:
+; LINUX-64-STATIC-LABEL: lcaller:
 ; LINUX-64-STATIC: callq   lcallee
 ; LINUX-64-STATIC: callq   lcallee
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: lcaller:
+; LINUX-32-STATIC-LABEL: lcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	lcallee
 ; LINUX-32-STATIC-NEXT: 	calll	lcallee
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: lcaller:
+; LINUX-32-PIC-LABEL: lcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	lcallee
 ; LINUX-32-PIC-NEXT: 	calll	lcallee
@@ -8936,7 +8936,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: lcaller:
+; LINUX-64-PIC-LABEL: lcaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	lcallee@PLT
 ; LINUX-64-PIC-NEXT: 	callq	lcallee@PLT
@@ -8990,24 +8990,24 @@ define void @tailcaller() nounwind {
 entry:
 	call void @callee() nounwind
 	ret void
-; LINUX-64-STATIC: tailcaller:
+; LINUX-64-STATIC-LABEL: tailcaller:
 ; LINUX-64-STATIC: callq   callee
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: tailcaller:
+; LINUX-32-STATIC-LABEL: tailcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	callee
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: tailcaller:
+; LINUX-32-PIC-LABEL: tailcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	callee
 ; LINUX-32-PIC-NEXT: 	addl
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: tailcaller:
+; LINUX-64-PIC-LABEL: tailcaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	callee@PLT
 ; LINUX-64-PIC-NEXT: 	popq
@@ -9054,24 +9054,24 @@ define void @dtailcaller() nounwind {
 entry:
 	call void @dcallee() nounwind
 	ret void
-; LINUX-64-STATIC: dtailcaller:
+; LINUX-64-STATIC-LABEL: dtailcaller:
 ; LINUX-64-STATIC: callq   dcallee
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: dtailcaller:
+; LINUX-32-STATIC-LABEL: dtailcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	dcallee
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: dtailcaller:
+; LINUX-32-PIC-LABEL: dtailcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	dcallee
 ; LINUX-32-PIC-NEXT: 	addl
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: dtailcaller:
+; LINUX-64-PIC-LABEL: dtailcaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	dcallee
 ; LINUX-64-PIC-NEXT: 	popq
@@ -9118,24 +9118,24 @@ define void @ltailcaller() nounwind {
 entry:
 	call void @lcallee() nounwind
 	ret void
-; LINUX-64-STATIC: ltailcaller:
+; LINUX-64-STATIC-LABEL: ltailcaller:
 ; LINUX-64-STATIC: callq   lcallee
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ltailcaller:
+; LINUX-32-STATIC-LABEL: ltailcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	lcallee
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ltailcaller:
+; LINUX-32-PIC-LABEL: ltailcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	lcallee
 ; LINUX-32-PIC-NEXT: 	addl
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ltailcaller:
+; LINUX-64-PIC-LABEL: ltailcaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	lcallee@PLT
 ; LINUX-64-PIC-NEXT: 	popq
@@ -9185,19 +9185,19 @@ entry:
 	%1 = load void ()** @ifunc, align 8
 	call void %1() nounwind
 	ret void
-; LINUX-64-STATIC: icaller:
+; LINUX-64-STATIC-LABEL: icaller:
 ; LINUX-64-STATIC: callq   *ifunc
 ; LINUX-64-STATIC: callq   *ifunc
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: icaller:
+; LINUX-32-STATIC-LABEL: icaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	*ifunc
 ; LINUX-32-STATIC-NEXT: 	calll	*ifunc
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: icaller:
+; LINUX-32-PIC-LABEL: icaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	*ifunc
 ; LINUX-32-PIC-NEXT: 	calll	*ifunc
@@ -9205,7 +9205,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: icaller:
+; LINUX-64-PIC-LABEL: icaller:
 ; LINUX-64-PIC: 	pushq	[[RBX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ifunc@GOTPCREL(%rip), [[RBX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	callq	*([[RBX]])
@@ -9275,19 +9275,19 @@ entry:
 	%1 = load void ()** @difunc, align 8
 	call void %1() nounwind
 	ret void
-; LINUX-64-STATIC: dicaller:
+; LINUX-64-STATIC-LABEL: dicaller:
 ; LINUX-64-STATIC: callq   *difunc
 ; LINUX-64-STATIC: callq   *difunc
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: dicaller:
+; LINUX-32-STATIC-LABEL: dicaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	*difunc
 ; LINUX-32-STATIC-NEXT: 	calll	*difunc
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: dicaller:
+; LINUX-32-PIC-LABEL: dicaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	*difunc
 ; LINUX-32-PIC-NEXT: 	calll	*difunc
@@ -9295,7 +9295,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: dicaller:
+; LINUX-64-PIC-LABEL: dicaller:
 ; LINUX-64-PIC: 	pushq	[[RBX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	difunc@GOTPCREL(%rip), [[RBX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	callq	*([[RBX]])
@@ -9358,19 +9358,19 @@ entry:
 	%1 = load void ()** @lifunc, align 8
 	call void %1() nounwind
 	ret void
-; LINUX-64-STATIC: licaller:
+; LINUX-64-STATIC-LABEL: licaller:
 ; LINUX-64-STATIC: callq   *lifunc
 ; LINUX-64-STATIC: callq   *lifunc
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: licaller:
+; LINUX-32-STATIC-LABEL: licaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	*lifunc
 ; LINUX-32-STATIC-NEXT: 	calll	*lifunc
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: licaller:
+; LINUX-32-PIC-LABEL: licaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	*lifunc
 ; LINUX-32-PIC-NEXT: 	calll	*lifunc
@@ -9378,7 +9378,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: licaller:
+; LINUX-64-PIC-LABEL: licaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	*lifunc(%rip)
 ; LINUX-64-PIC-NEXT: 	callq	*lifunc(%rip)
@@ -9440,19 +9440,19 @@ entry:
 	%1 = load void ()** @ifunc, align 8
 	call void %1() nounwind
 	ret void
-; LINUX-64-STATIC: itailcaller:
+; LINUX-64-STATIC-LABEL: itailcaller:
 ; LINUX-64-STATIC: callq   *ifunc
 ; LINUX-64-STATIC: callq   *ifunc
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: itailcaller:
+; LINUX-32-STATIC-LABEL: itailcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	*ifunc
 ; LINUX-32-STATIC-NEXT: 	calll	*ifunc
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: itailcaller:
+; LINUX-32-PIC-LABEL: itailcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	*ifunc
 ; LINUX-32-PIC-NEXT: 	calll	*ifunc
@@ -9460,7 +9460,7 @@ entry:
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: itailcaller:
+; LINUX-64-PIC-LABEL: itailcaller:
 ; LINUX-64-PIC: 	pushq	[[RBX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movq	ifunc@GOTPCREL(%rip), [[RBX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	callq	*([[RBX]])
@@ -9528,24 +9528,24 @@ entry:
 	%0 = load void ()** @difunc, align 8
 	call void %0() nounwind
 	ret void
-; LINUX-64-STATIC: ditailcaller:
+; LINUX-64-STATIC-LABEL: ditailcaller:
 ; LINUX-64-STATIC: callq   *difunc
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: ditailcaller:
+; LINUX-32-STATIC-LABEL: ditailcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	*difunc
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: ditailcaller:
+; LINUX-32-PIC-LABEL: ditailcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	*difunc
 ; LINUX-32-PIC-NEXT: 	addl
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: ditailcaller:
+; LINUX-64-PIC-LABEL: ditailcaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	movq	difunc@GOTPCREL(%rip), [[RAX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	callq	*([[RAX]])
@@ -9596,24 +9596,24 @@ entry:
 	%0 = load void ()** @lifunc, align 8
 	call void %0() nounwind
 	ret void
-; LINUX-64-STATIC: litailcaller:
+; LINUX-64-STATIC-LABEL: litailcaller:
 ; LINUX-64-STATIC: callq   *lifunc
 ; LINUX-64-STATIC: ret
 
-; LINUX-32-STATIC: litailcaller:
+; LINUX-32-STATIC-LABEL: litailcaller:
 ; LINUX-32-STATIC: 	subl
 ; LINUX-32-STATIC-NEXT: 	calll	*lifunc
 ; LINUX-32-STATIC-NEXT: 	addl
 ; LINUX-32-STATIC-NEXT: 	ret
 
-; LINUX-32-PIC: litailcaller:
+; LINUX-32-PIC-LABEL: litailcaller:
 ; LINUX-32-PIC: 	subl
 ; LINUX-32-PIC-NEXT: 	calll	*lifunc
 ; LINUX-32-PIC-NEXT: 	addl
 
 ; LINUX-32-PIC-NEXT: 	ret
 
-; LINUX-64-PIC: litailcaller:
+; LINUX-64-PIC-LABEL: litailcaller:
 ; LINUX-64-PIC: 	pushq
 ; LINUX-64-PIC-NEXT: 	callq	*lifunc(%rip)
 ; LINUX-64-PIC-NEXT: 	popq
diff --git a/test/CodeGen/X86/add-of-carry.ll b/test/CodeGen/X86/add-of-carry.ll
index 4e30f2b..1513fcb 100644
--- a/test/CodeGen/X86/add-of-carry.ll
+++ b/test/CodeGen/X86/add-of-carry.ll
@@ -3,7 +3,7 @@
 
 define i32 @test1(i32 %sum, i32 %x) nounwind readnone ssp {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: cmpl %ecx, %eax
 ; CHECK-NOT: addl
 ; CHECK: adcl $0, %eax
@@ -15,7 +15,7 @@ entry:
 }
 
 ; Instcombine transforms test1 into test2:
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movl
 ; CHECK-NEXT: addl
 ; CHECK-NEXT: adcl $0
@@ -37,7 +37,7 @@ entry:
   %dec = sext i1 %cmp to i32
   %dec.res = add nsw i32 %dec, %res
   ret i32 %dec.res
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: cmpl
 ; CHECK: sbbl
 ; CHECK: ret
diff --git a/test/CodeGen/X86/add.ll b/test/CodeGen/X86/add.ll
index 5fe08ed..f36577b 100644
--- a/test/CodeGen/X86/add.ll
+++ b/test/CodeGen/X86/add.ll
@@ -39,11 +39,11 @@ normal:
 overflow:
   ret i1 false
   
-; X32: test4:
+; X32-LABEL: test4:
 ; X32: addl
 ; X32-NEXT: jo
 
-; X64:        test4:
+; X64-LABEL:        test4:
 ; X64:          addl	%e[[A1:si|dx]], %e[[A0:di|cx]]
 ; X64-NEXT:	jo
 }
@@ -62,11 +62,11 @@ normal:
 carry:
   ret i1 false
 
-; X32: test5:
+; X32-LABEL: test5:
 ; X32: addl
 ; X32-NEXT: jb
 
-; X64:        test5:
+; X64-LABEL:        test5:
 ; X64:          addl	%e[[A1]], %e[[A0]]
 ; X64-NEXT:	jb
 }
@@ -81,13 +81,13 @@ define i64 @test6(i64 %A, i32 %B) nounwind {
         %tmp5 = add i64 %tmp3, %A               ; <i64> [#uses=1]
         ret i64 %tmp5
 
-; X32: test6:
+; X32-LABEL: test6:
 ; X32:	    movl 12(%esp), %edx
 ; X32-NEXT: addl 8(%esp), %edx
 ; X32-NEXT: movl 4(%esp), %eax
 ; X32-NEXT: ret
         
-; X64: test6:
+; X64-LABEL: test6:
 ; X64:	shlq	$32, %r[[A1]]
 ; X64:	leaq	(%r[[A1]],%r[[A0]]), %rax
 ; X64:	ret
@@ -98,7 +98,7 @@ define {i32, i1} @test7(i32 %v1, i32 %v2) nounwind {
    ret {i32, i1} %t
 }
 
-; X64: test7:
+; X64-LABEL: test7:
 ; X64: addl %e[[A1]], %e
 ; X64-NEXT: setb %dl
 ; X64: ret
@@ -117,7 +117,7 @@ entry:
     ret {i64, i1} %final1
 }
 
-; X64: test8:
+; X64-LABEL: test8:
 ; X64: addq
 ; X64-NEXT: setb
 ; X64: ret
@@ -127,7 +127,7 @@ define i32 @test9(i32 %x, i32 %y) nounwind readnone {
   %sub = sext i1 %cmp to i32
   %cond = add i32 %sub, %y
   ret i32 %cond
-; X64: test9:
+; X64-LABEL: test9:
 ; X64: cmpl $10
 ; X64: sete
 ; X64: subl
@@ -140,11 +140,11 @@ entry:
   %obit = extractvalue {i32, i1} %t, 1
   ret i1 %obit
 
-; X32: test10:
+; X32-LABEL: test10:
 ; X32: incl
 ; X32-NEXT: seto
 
-; X64: test10:
+; X64-LABEL: test10:
 ; X64: incl
 ; X64-NEXT: seto
 }
diff --git a/test/CodeGen/X86/alloca-align-rounding-32.ll b/test/CodeGen/X86/alloca-align-rounding-32.ll
index a45284e..2b5a205 100644
--- a/test/CodeGen/X86/alloca-align-rounding-32.ll
+++ b/test/CodeGen/X86/alloca-align-rounding-32.ll
@@ -16,5 +16,5 @@ define void @foo2(i32 %h) {
   ret void
 ; CHECK: foo2
 ; CHECK: andl $-32, %esp
-; CHECK: andl $-32, %eax
+; CHECK: andl $-32, %e{{..}}
 }
diff --git a/test/CodeGen/X86/and-su.ll b/test/CodeGen/X86/and-su.ll
index 38db88a..70c2461 100644
--- a/test/CodeGen/X86/and-su.ll
+++ b/test/CodeGen/X86/and-su.ll
@@ -3,7 +3,7 @@
 ; Don't duplicate the load.
 
 define fastcc i32 @foo(i32* %p) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: andl $10, %eax
 ; CHECK: je
 	%t0 = load i32* %p
@@ -18,7 +18,7 @@ bb76:
 
 define fastcc double @bar(i32 %hash, double %x, double %y) nounwind {
 entry:
-; CHECK: bar:
+; CHECK-LABEL: bar:
   %0 = and i32 %hash, 15
   %1 = icmp ult i32 %0, 8
   br i1 %1, label %bb11, label %bb10
diff --git a/test/CodeGen/X86/apm.ll b/test/CodeGen/X86/apm.ll
index aaedf18..4ba1e21 100644
--- a/test/CodeGen/X86/apm.ll
+++ b/test/CodeGen/X86/apm.ll
@@ -2,11 +2,11 @@
 ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse3 | FileCheck %s -check-prefix=WIN64
 ; PR8573
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: leaq    (%rdi), %rax
 ; CHECK-NEXT: movl    %esi, %ecx
 ; CHECK-NEXT: monitor
-; WIN64: foo:
+; WIN64-LABEL: foo:
 ; WIN64:      leaq    (%rcx), %rax
 ; WIN64-NEXT: movl    %edx, %ecx
 ; WIN64-NEXT: movl    %r8d, %edx
@@ -19,11 +19,11 @@ entry:
 
 declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind
 
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: movl    %edi, %ecx
 ; CHECK-NEXT: movl    %esi, %eax
 ; CHECK-NEXT: mwait
-; WIN64: bar:
+; WIN64-LABEL: bar:
 ; WIN64:      movl    %edx, %eax
 ; WIN64-NEXT: mwait
 define void @bar(i32 %E, i32 %H) nounwind {
diff --git a/test/CodeGen/X86/asm-global-imm.ll b/test/CodeGen/X86/asm-global-imm.ll
index 6c569d6..ebf585a 100644
--- a/test/CodeGen/X86/asm-global-imm.ll
+++ b/test/CodeGen/X86/asm-global-imm.ll
@@ -7,7 +7,7 @@ target triple = "i686-apple-darwin9.0.0d2"
 @str = external global [12 x i8]		; <[12 x i8]*> [#uses=1]
 
 define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NOT: ret
 ; CHECK: test1 $_GV
 ; CHECK-NOT: ret
diff --git a/test/CodeGen/X86/asm-modifier-P.ll b/test/CodeGen/X86/asm-modifier-P.ll
index 6139da8..0aa5555 100644
--- a/test/CodeGen/X86/asm-modifier-P.ll
+++ b/test/CodeGen/X86/asm-modifier-P.ll
@@ -21,20 +21,20 @@ define void @test1() nounwind {
 entry:
 ; P suffix removes (rip) in -static 64-bit mode.
 
-; CHECK-PIC-64: test1:
+; CHECK-PIC-64-LABEL: test1:
 ; CHECK-PIC-64: movq	G@GOTPCREL(%rip), %rax
 ; CHECK-PIC-64: frob (%rax) x
 ; CHECK-PIC-64: frob (%rax) x
 
-; CHECK-STATIC-64: test1:
+; CHECK-STATIC-64-LABEL: test1:
 ; CHECK-STATIC-64: frob G(%rip) x
 ; CHECK-STATIC-64: frob G x
 
-; CHECK-PIC-32: test1:
+; CHECK-PIC-32-LABEL: test1:
 ; CHECK-PIC-32: frob G x
 ; CHECK-PIC-32: frob G x
 
-; CHECK-STATIC-32: test1:
+; CHECK-STATIC-32-LABEL: test1:
 ; CHECK-STATIC-32: frob G x
 ; CHECK-STATIC-32: frob G x
 
@@ -45,25 +45,25 @@ entry:
 
 define void @test3() nounwind {
 entry:
-; CHECK-STATIC-64: test3:
+; CHECK-STATIC-64-LABEL: test3:
 ; CHECK-STATIC-64: call bar
 ; CHECK-STATIC-64: call test3
 ; CHECK-STATIC-64: call $bar
 ; CHECK-STATIC-64: call $test3
 
-; CHECK-STATIC-32: test3:
+; CHECK-STATIC-32-LABEL: test3:
 ; CHECK-STATIC-32: call bar
 ; CHECK-STATIC-32: call test3
 ; CHECK-STATIC-32: call $bar
 ; CHECK-STATIC-32: call $test3
 
-; CHECK-PIC-64: test3:
+; CHECK-PIC-64-LABEL: test3:
 ; CHECK-PIC-64: call bar@PLT
 ; CHECK-PIC-64: call test3@PLT
 ; CHECK-PIC-64: call $bar
 ; CHECK-PIC-64: call $test3
 
-; CHECK-PIC-32: test3:
+; CHECK-PIC-32-LABEL: test3:
 ; CHECK-PIC-32: call bar@PLT
 ; CHECK-PIC-32: call test3@PLT
 ; CHECK-PIC-32: call $bar
diff --git a/test/CodeGen/X86/asm-modifier.ll b/test/CodeGen/X86/asm-modifier.ll
index 44f972e..47b185a 100644
--- a/test/CodeGen/X86/asm-modifier.ll
+++ b/test/CodeGen/X86/asm-modifier.ll
@@ -5,7 +5,7 @@ target triple = "i386-apple-darwin9.6"
 
 define i32 @test1() nounwind {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: movw	%gs:6, %ax
   %asmtmp.i = tail call i16 asm "movw\09%gs:${1:a}, ${0:w}", "=r,ir,~{dirflag},~{fpsr},~{flags}"(i32 6) nounwind ; <i16> [#uses=1]
   %0 = zext i16 %asmtmp.i to i32                  ; <i32> [#uses=1]
@@ -14,7 +14,7 @@ entry:
 
 define zeroext i16 @test2(i32 %address) nounwind {
 entry:
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movw	%gs:(%eax), %ax
   %asmtmp = tail call i16 asm "movw\09%gs:${1:a}, ${0:w}", "=r,ir,~{dirflag},~{fpsr},~{flags}"(i32 %address) nounwind ; <i16> [#uses=1]
   ret i16 %asmtmp
@@ -25,7 +25,7 @@ entry:
 
 define void @test3() nounwind {
 entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: movl _n, %eax
   call void asm sideeffect "movl ${0:a}, %eax", "ir,~{dirflag},~{fpsr},~{flags},~{eax}"(i32* @n) nounwind
   ret void
@@ -33,7 +33,7 @@ entry:
 
 define void @test4() nounwind {
 entry:
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: movl	L_y$non_lazy_ptr, %ecx
 ; CHECK: movl (%ecx), %eax
   call void asm sideeffect "movl ${0:a}, %eax", "ir,~{dirflag},~{fpsr},~{flags},~{eax}"(i32* @y) nounwind
diff --git a/test/CodeGen/X86/atom-bypass-slow-division-64.ll b/test/CodeGen/X86/atom-bypass-slow-division-64.ll
index a3bbea3..d1b52a4 100644
--- a/test/CodeGen/X86/atom-bypass-slow-division-64.ll
+++ b/test/CodeGen/X86/atom-bypass-slow-division-64.ll
@@ -3,9 +3,10 @@
 ; Additional tests for 64-bit divide bypass
 
 define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind {
-; CHECK: Test_get_quotient:
-; CHECK: orq %rsi, %rcx
-; CHECK-NEXT: testq $-65536, %rcx
+; CHECK-LABEL: Test_get_quotient:
+; CHECK: movq %rdi, %rax
+; CHECK: orq %rsi, %rax
+; CHECK-NEXT: testq $-65536, %rax
 ; CHECK-NEXT: je
 ; CHECK: idivq
 ; CHECK: ret
@@ -16,9 +17,10 @@ define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind {
 }
 
 define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
-; CHECK: Test_get_remainder:
-; CHECK: orq %rsi, %rcx
-; CHECK-NEXT: testq $-65536, %rcx
+; CHECK-LABEL: Test_get_remainder:
+; CHECK: movq %rdi, %rax
+; CHECK: orq %rsi, %rax
+; CHECK-NEXT: testq $-65536, %rax
 ; CHECK-NEXT: je
 ; CHECK: idivq
 ; CHECK: ret
@@ -29,9 +31,10 @@ define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
 }
 
 define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind {
-; CHECK: Test_get_quotient_and_remainder:
-; CHECK: orq %rsi, %rcx
-; CHECK-NEXT: testq $-65536, %rcx
+; CHECK-LABEL: Test_get_quotient_and_remainder:
+; CHECK: movq %rdi, %rax
+; CHECK: orq %rsi, %rax
+; CHECK-NEXT: testq $-65536, %rax
 ; CHECK-NEXT: je
 ; CHECK: idivq
 ; CHECK: divw
diff --git a/test/CodeGen/X86/atom-bypass-slow-division.ll b/test/CodeGen/X86/atom-bypass-slow-division.ll
index 4612940..79001e5 100644
--- a/test/CodeGen/X86/atom-bypass-slow-division.ll
+++ b/test/CodeGen/X86/atom-bypass-slow-division.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s
 
 define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind {
-; CHECK: Test_get_quotient:
+; CHECK-LABEL: Test_get_quotient:
 ; CHECK: orl %ecx, %edx
 ; CHECK-NEXT: testl $-256, %edx
 ; CHECK-NEXT: je
@@ -14,7 +14,7 @@ define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind {
 }
 
 define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind {
-; CHECK: Test_get_remainder:
+; CHECK-LABEL: Test_get_remainder:
 ; CHECK: orl %ecx, %edx
 ; CHECK-NEXT: testl $-256, %edx
 ; CHECK-NEXT: je
@@ -27,7 +27,7 @@ define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind {
 }
 
 define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind {
-; CHECK: Test_get_quotient_and_remainder:
+; CHECK-LABEL: Test_get_quotient_and_remainder:
 ; CHECK: orl %ecx, %edx
 ; CHECK-NEXT: testl $-256, %edx
 ; CHECK-NEXT: je
@@ -44,7 +44,7 @@ define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind {
 }
 
 define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind {
-; CHECK: Test_use_div_and_idiv:
+; CHECK-LABEL: Test_use_div_and_idiv:
 ; CHECK: idivl
 ; CHECK: divb
 ; CHECK: divl
@@ -58,14 +58,14 @@ define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind {
 }
 
 define i32 @Test_use_div_imm_imm() nounwind {
-; CHECK: Test_use_div_imm_imm:
+; CHECK-LABEL: Test_use_div_imm_imm:
 ; CHECK: movl $64
   %resultdiv = sdiv i32 256, 4
   ret i32 %resultdiv
 }
 
 define i32 @Test_use_div_reg_imm(i32 %a) nounwind {
-; CHECK: Test_use_div_reg_imm:
+; CHECK-LABEL: Test_use_div_reg_imm:
 ; CHECK-NOT: test
 ; CHECK-NOT: idiv
 ; CHECK-NOT: divb
@@ -74,7 +74,7 @@ define i32 @Test_use_div_reg_imm(i32 %a) nounwind {
 }
 
 define i32 @Test_use_rem_reg_imm(i32 %a) nounwind {
-; CHECK: Test_use_rem_reg_imm:
+; CHECK-LABEL: Test_use_rem_reg_imm:
 ; CHECK-NOT: test
 ; CHECK-NOT: idiv
 ; CHECK-NOT: divb
@@ -83,7 +83,7 @@ define i32 @Test_use_rem_reg_imm(i32 %a) nounwind {
 }
 
 define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind {
-; CHECK: Test_use_divrem_reg_imm:
+; CHECK-LABEL: Test_use_divrem_reg_imm:
 ; CHECK-NOT: test
 ; CHECK-NOT: idiv
 ; CHECK-NOT: divb
@@ -94,7 +94,7 @@ define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind {
 }
 
 define i32 @Test_use_div_imm_reg(i32 %a) nounwind {
-; CHECK: Test_use_div_imm_reg:
+; CHECK-LABEL: Test_use_div_imm_reg:
 ; CHECK: test
 ; CHECK: idiv
 ; CHECK: divb
@@ -103,7 +103,7 @@ define i32 @Test_use_div_imm_reg(i32 %a) nounwind {
 }
 
 define i32 @Test_use_rem_imm_reg(i32 %a) nounwind {
-; CHECK: Test_use_rem_imm_reg:
+; CHECK-LABEL: Test_use_rem_imm_reg:
 ; CHECK: test
 ; CHECK: idiv
 ; CHECK: divb
diff --git a/test/CodeGen/X86/atom-call-reg-indirect.ll b/test/CodeGen/X86/atom-call-reg-indirect.ll
index 6327811..933b98b 100644
--- a/test/CodeGen/X86/atom-call-reg-indirect.ll
+++ b/test/CodeGen/X86/atom-call-reg-indirect.ll
@@ -8,7 +8,7 @@
 %class.A = type { i32 (...)** }
 
 define i32 @test1() #0 {
-  ;ATOM: test1
+  ;ATOM-LABEL: test1:
 entry:
   %call = tail call %class.A* @_Z3facv()
   %0 = bitcast %class.A* %call to void (%class.A*)***
@@ -30,7 +30,7 @@ declare %class.A* @_Z3facv() #1
 @p = external global void (i32)**
 
 define i32 @test2() #0 {
-  ;ATOM: test2
+  ;ATOM-LABEL: test2:
 entry:
   %0 = load void (i32)*** @p, align 8
   %1 = load void (i32)** %0, align 8
diff --git a/test/CodeGen/X86/atom-lea-sp.ll b/test/CodeGen/X86/atom-lea-sp.ll
index 19482e1..1df1974 100644
--- a/test/CodeGen/X86/atom-lea-sp.ll
+++ b/test/CodeGen/X86/atom-lea-sp.ll
@@ -5,13 +5,13 @@ declare void @use_arr(i8*)
 declare void @many_params(i32, i32, i32, i32, i32, i32)
 
 define void @test1() nounwind {
-; ATOM: test1:
+; ATOM-LABEL: test1:
 ; ATOM: leal -1052(%esp), %esp
 ; ATOM-NOT: sub
 ; ATOM: call
 ; ATOM: leal 1052(%esp), %esp
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: subl
 ; CHECK: call
 ; CHECK-NOT: lea
@@ -22,23 +22,23 @@ define void @test1() nounwind {
 }
 
 define void @test2() nounwind {
-; ATOM: test2:
+; ATOM-LABEL: test2:
 ; ATOM: leal -28(%esp), %esp
 ; ATOM: call
 ; ATOM: leal 28(%esp), %esp
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK-NOT: lea
   call void @many_params(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
   ret void
 }
 
 define void @test3() nounwind {
-; ATOM: test3:
+; ATOM-LABEL: test3:
 ; ATOM: leal -8(%esp), %esp
 ; ATOM: leal 8(%esp), %esp
 
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK-NOT: lea
   %x = alloca i32, align 4
   %y = alloca i32, align 4
diff --git a/test/CodeGen/X86/atomic-minmax-i6432.ll b/test/CodeGen/X86/atomic-minmax-i6432.ll
index 62f784f..1cfbc49 100644
--- a/test/CodeGen/X86/atomic-minmax-i6432.ll
+++ b/test/CodeGen/X86/atomic-minmax-i6432.ll
@@ -97,7 +97,7 @@ define void @atomic_maxmin_i6432() {
 @id = internal global i64 0, align 8
 
 define void @tf_bug(i8* %ptr) nounwind {
-; PIC: tf_bug:
+; PIC-LABEL: tf_bug:
 ; PIC: movl _id-L1$pb(
 ; PIC: movl (_id-L1$pb)+4(
   %tmp1 = atomicrmw add i64* @id, i64 1 seq_cst
diff --git a/test/CodeGen/X86/atomic-or.ll b/test/CodeGen/X86/atomic-or.ll
index d759beb..1687e07 100644
--- a/test/CodeGen/X86/atomic-or.ll
+++ b/test/CodeGen/X86/atomic-or.ll
@@ -7,7 +7,7 @@ entry:
   %p.addr = alloca i64*, align 8
   store i64* %p, i64** %p.addr, align 8
   %tmp = load i64** %p.addr, align 8
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: movl    $2147483648, %eax
 ; CHECK: lock
 ; CHECK-NEXT: orq %r{{.*}}, (%r{{.*}})
@@ -20,7 +20,7 @@ entry:
   %p.addr = alloca i64*, align 8
   store i64* %p, i64** %p.addr, align 8
   %tmp = load i64** %p.addr, align 8
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: lock
 ; CHECK-NEXT: orq $2147483644, (%r{{.*}})
   %0 = atomicrmw or i64* %tmp, i64 2147483644 seq_cst
diff --git a/test/CodeGen/X86/atomic_add.ll b/test/CodeGen/X86/atomic_add.ll
index 6b3a6b2..bdd25e6 100644
--- a/test/CodeGen/X86/atomic_add.ll
+++ b/test/CodeGen/X86/atomic_add.ll
@@ -4,7 +4,7 @@
 
 define void @sub1(i32* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: sub1:
+; CHECK-LABEL: sub1:
 ; CHECK: subl
   %0 = atomicrmw sub i32* %p, i32 %v monotonic
   ret void
@@ -12,7 +12,7 @@ entry:
 
 define void @inc4(i64* nocapture %p) nounwind ssp {
 entry:
-; CHECK: inc4:
+; CHECK-LABEL: inc4:
 ; CHECK: incq
   %0 = atomicrmw add i64* %p, i64 1 monotonic
   ret void
@@ -20,7 +20,7 @@ entry:
 
 define void @add8(i64* nocapture %p) nounwind ssp {
 entry:
-; CHECK: add8:
+; CHECK-LABEL: add8:
 ; CHECK: addq $2
   %0 = atomicrmw add i64* %p, i64 2 monotonic
   ret void
@@ -28,7 +28,7 @@ entry:
 
 define void @add4(i64* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: add4:
+; CHECK-LABEL: add4:
 ; CHECK: addq
   %0 = sext i32 %v to i64		; <i64> [#uses=1]
   %1 = atomicrmw add i64* %p, i64 %0 monotonic
@@ -37,7 +37,7 @@ entry:
 
 define void @inc3(i8* nocapture %p) nounwind ssp {
 entry:
-; CHECK: inc3:
+; CHECK-LABEL: inc3:
 ; CHECK: incb
   %0 = atomicrmw add i8* %p, i8 1 monotonic
   ret void
@@ -45,7 +45,7 @@ entry:
 
 define void @add7(i8* nocapture %p) nounwind ssp {
 entry:
-; CHECK: add7:
+; CHECK-LABEL: add7:
 ; CHECK: addb $2
   %0 = atomicrmw add i8* %p, i8 2 monotonic
   ret void
@@ -53,7 +53,7 @@ entry:
 
 define void @add3(i8* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: add3:
+; CHECK-LABEL: add3:
 ; CHECK: addb
   %0 = trunc i32 %v to i8		; <i8> [#uses=1]
   %1 = atomicrmw add i8* %p, i8 %0 monotonic
@@ -62,7 +62,7 @@ entry:
 
 define void @inc2(i16* nocapture %p) nounwind ssp {
 entry:
-; CHECK: inc2:
+; CHECK-LABEL: inc2:
 ; CHECK: incw
   %0 = atomicrmw add i16* %p, i16 1 monotonic
   ret void
@@ -70,7 +70,7 @@ entry:
 
 define void @add6(i16* nocapture %p) nounwind ssp {
 entry:
-; CHECK: add6:
+; CHECK-LABEL: add6:
 ; CHECK: addw $2
   %0 = atomicrmw add i16* %p, i16 2 monotonic
   ret void
@@ -78,7 +78,7 @@ entry:
 
 define void @add2(i16* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: add2:
+; CHECK-LABEL: add2:
 ; CHECK: addw
 	%0 = trunc i32 %v to i16		; <i16> [#uses=1]
   %1 = atomicrmw add i16* %p, i16 %0 monotonic
@@ -87,7 +87,7 @@ entry:
 
 define void @inc1(i32* nocapture %p) nounwind ssp {
 entry:
-; CHECK: inc1:
+; CHECK-LABEL: inc1:
 ; CHECK: incl
   %0 = atomicrmw add i32* %p, i32 1 monotonic
   ret void
@@ -95,7 +95,7 @@ entry:
 
 define void @add5(i32* nocapture %p) nounwind ssp {
 entry:
-; CHECK: add5:
+; CHECK-LABEL: add5:
 ; CHECK: addl $2
   %0 = atomicrmw add i32* %p, i32 2 monotonic
   ret void
@@ -103,7 +103,7 @@ entry:
 
 define void @add1(i32* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: add1:
+; CHECK-LABEL: add1:
 ; CHECK: addl
   %0 = atomicrmw add i32* %p, i32 %v monotonic
   ret void
@@ -111,7 +111,7 @@ entry:
 
 define void @dec4(i64* nocapture %p) nounwind ssp {
 entry:
-; CHECK: dec4:
+; CHECK-LABEL: dec4:
 ; CHECK: decq
   %0 = atomicrmw sub i64* %p, i64 1 monotonic
   ret void
@@ -119,7 +119,7 @@ entry:
 
 define void @sub8(i64* nocapture %p) nounwind ssp {
 entry:
-; CHECK: sub8:
+; CHECK-LABEL: sub8:
 ; CHECK: subq $2
   %0 = atomicrmw sub i64* %p, i64 2 monotonic
   ret void
@@ -127,7 +127,7 @@ entry:
 
 define void @sub4(i64* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: sub4:
+; CHECK-LABEL: sub4:
 ; CHECK: subq
 	%0 = sext i32 %v to i64		; <i64> [#uses=1]
   %1 = atomicrmw sub i64* %p, i64 %0 monotonic
@@ -136,7 +136,7 @@ entry:
 
 define void @dec3(i8* nocapture %p) nounwind ssp {
 entry:
-; CHECK: dec3:
+; CHECK-LABEL: dec3:
 ; CHECK: decb
   %0 = atomicrmw sub i8* %p, i8 1 monotonic
   ret void
@@ -144,7 +144,7 @@ entry:
 
 define void @sub7(i8* nocapture %p) nounwind ssp {
 entry:
-; CHECK: sub7:
+; CHECK-LABEL: sub7:
 ; CHECK: subb $2
   %0 = atomicrmw sub i8* %p, i8 2 monotonic
   ret void
@@ -152,7 +152,7 @@ entry:
 
 define void @sub3(i8* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: sub3:
+; CHECK-LABEL: sub3:
 ; CHECK: subb
 	%0 = trunc i32 %v to i8		; <i8> [#uses=1]
   %1 = atomicrmw sub i8* %p, i8 %0 monotonic
@@ -161,7 +161,7 @@ entry:
 
 define void @dec2(i16* nocapture %p) nounwind ssp {
 entry:
-; CHECK: dec2:
+; CHECK-LABEL: dec2:
 ; CHECK: decw
   %0 = atomicrmw sub i16* %p, i16 1 monotonic
   ret void
@@ -169,7 +169,7 @@ entry:
 
 define void @sub6(i16* nocapture %p) nounwind ssp {
 entry:
-; CHECK: sub6:
+; CHECK-LABEL: sub6:
 ; CHECK: subw $2
   %0 = atomicrmw sub i16* %p, i16 2 monotonic
   ret void
@@ -177,7 +177,7 @@ entry:
 
 define void @sub2(i16* nocapture %p, i32 %v) nounwind ssp {
 entry:
-; CHECK: sub2:
+; CHECK-LABEL: sub2:
 ; CHECK-NOT: negl
 ; CHECK: subw
 	%0 = trunc i32 %v to i16		; <i16> [#uses=1]
@@ -187,7 +187,7 @@ entry:
 
 define void @dec1(i32* nocapture %p) nounwind ssp {
 entry:
-; CHECK: dec1:
+; CHECK-LABEL: dec1:
 ; CHECK: decl
   %0 = atomicrmw sub i32* %p, i32 1 monotonic
   ret void
@@ -195,7 +195,7 @@ entry:
 
 define void @sub5(i32* nocapture %p) nounwind ssp {
 entry:
-; CHECK: sub5:
+; CHECK-LABEL: sub5:
 ; CHECK: subl $2
   %0 = atomicrmw sub i32* %p, i32 2 monotonic
   ret void
diff --git a/test/CodeGen/X86/avx-blend.ll b/test/CodeGen/X86/avx-blend.ll
index 188efe2..a98e076 100644
--- a/test/CodeGen/X86/avx-blend.ll
+++ b/test/CodeGen/X86/avx-blend.ll
@@ -2,7 +2,7 @@
 
 ; AVX128 tests:
 
-;CHECK: vsel_float
+;CHECK-LABEL: vsel_float:
 ;CHECK: vblendvps
 ;CHECK: ret
 define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
@@ -11,7 +11,7 @@ define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
 }
 
 
-;CHECK: vsel_i32
+;CHECK-LABEL: vsel_i32:
 ;CHECK: vblendvps
 ;CHECK: ret
 define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
@@ -20,7 +20,7 @@ define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
 }
 
 
-;CHECK: vsel_double
+;CHECK-LABEL: vsel_double:
 ;CHECK: vblendvpd
 ;CHECK: ret
 define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
@@ -29,7 +29,7 @@ define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
 }
 
 
-;CHECK: vsel_i64
+;CHECK-LABEL: vsel_i64:
 ;CHECK: vblendvpd
 ;CHECK: ret
 define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
@@ -38,7 +38,7 @@ define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
 }
 
 
-;CHECK: vsel_i8
+;CHECK-LABEL: vsel_i8:
 ;CHECK: vpblendvb
 ;CHECK: ret
 define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
@@ -50,7 +50,7 @@ define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
 ; AVX256 tests:
 
 
-;CHECK: vsel_float
+;CHECK-LABEL: vsel_float8:
 ;CHECK: vblendvps
 ;CHECK: ret
 define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
@@ -58,7 +58,7 @@ define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
   ret <8 x float> %vsel
 }
 
-;CHECK: vsel_i32
+;CHECK-LABEL: vsel_i328:
 ;CHECK: vblendvps
 ;CHECK: ret
 define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
@@ -66,7 +66,7 @@ define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
   ret <8 x i32> %vsel
 }
 
-;CHECK: vsel_double
+;CHECK-LABEL: vsel_double8:
 ;CHECK: vblendvpd
 ;CHECK: ret
 define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
@@ -74,7 +74,7 @@ define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
   ret <8 x double> %vsel
 }
 
-;CHECK: vsel_i64
+;CHECK-LABEL: vsel_i648:
 ;CHECK: vblendvpd
 ;CHECK: ret
 define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
@@ -83,8 +83,8 @@ define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
 }
 
 ;; TEST blend + compares
-; CHECK: A
-define <2 x double> @A(<2 x double> %x, <2 x double> %y) {
+; CHECK: testa
+define <2 x double> @testa(<2 x double> %x, <2 x double> %y) {
   ; CHECK: vcmplepd
   ; CHECK: vblendvpd
   %max_is_x = fcmp oge <2 x double> %x, %y
@@ -92,8 +92,8 @@ define <2 x double> @A(<2 x double> %x, <2 x double> %y) {
   ret <2 x double> %max
 }
 
-; CHECK: B
-define <2 x double> @B(<2 x double> %x, <2 x double> %y) {
+; CHECK: testb
+define <2 x double> @testb(<2 x double> %x, <2 x double> %y) {
   ; CHECK: vcmpnlepd
   ; CHECK: vblendvpd
   %min_is_x = fcmp ult <2 x double> %x, %y
diff --git a/test/CodeGen/X86/avx-brcond.ll b/test/CodeGen/X86/avx-brcond.ll
index d52ae52..4313a15 100644
--- a/test/CodeGen/X86/avx-brcond.ll
+++ b/test/CodeGen/X86/avx-brcond.ll
@@ -5,7 +5,7 @@ declare i32 @llvm.x86.avx.ptestc.256(<4 x i64> %p1, <4 x i64> %p2) nounwind
 
 define <4 x float> @test1(<4 x i64> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: vptest
 ; CHECK-NEXT:	jne
 ; CHECK: ret
@@ -29,7 +29,7 @@ return:
 
 define <4 x float> @test3(<4 x i64> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: vptest
 ; CHECK-NEXT:	jne
 ; CHECK: ret
@@ -53,7 +53,7 @@ return:
 
 define <4 x float> @test4(<4 x i64> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: vptest
 ; CHECK-NEXT:	jae
 ; CHECK: ret
@@ -77,7 +77,7 @@ return:
 
 define <4 x float> @test6(<4 x i64> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: vptest
 ; CHECK-NEXT:	jae
 ; CHECK: ret
@@ -101,7 +101,7 @@ return:
 
 define <4 x float> @test7(<4 x i64> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: vptest
 ; CHECK-NEXT:	jne
 ; CHECK: ret
@@ -125,7 +125,7 @@ return:
 
 define <4 x float> @test8(<4 x i64> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: vptest
 ; CHECK-NEXT:	je
 ; CHECK: ret
diff --git a/test/CodeGen/X86/avx-fp2int.ll b/test/CodeGen/X86/avx-fp2int.ll
index a3aadde..8beaac6 100644
--- a/test/CodeGen/X86/avx-fp2int.ll
+++ b/test/CodeGen/X86/avx-fp2int.ll
@@ -2,10 +2,10 @@
 
 ;; Check that FP_TO_SINT and FP_TO_UINT generate convert with truncate
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: vcvttpd2dqy
 ; CHECK: ret
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: vcvttpd2dqy
 ; CHECK: ret
 
diff --git a/test/CodeGen/X86/avx-minmax.ll b/test/CodeGen/X86/avx-minmax.ll
index eff9251..c94962b 100644
--- a/test/CodeGen/X86/avx-minmax.ll
+++ b/test/CodeGen/X86/avx-minmax.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+avx -asm-verbose=false -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=UNSAFE %s
 
-; UNSAFE: maxpd:
+; UNSAFE-LABEL: maxpd:
 ; UNSAFE: vmaxpd {{.+}}, %xmm
 define <2 x double> @maxpd(<2 x double> %x, <2 x double> %y) {
   %max_is_x = fcmp oge <2 x double> %x, %y
@@ -8,7 +8,7 @@ define <2 x double> @maxpd(<2 x double> %x, <2 x double> %y) {
   ret <2 x double> %max
 }
 
-; UNSAFE: minpd:
+; UNSAFE-LABEL: minpd:
 ; UNSAFE: vminpd {{.+}}, %xmm
 define <2 x double> @minpd(<2 x double> %x, <2 x double> %y) {
   %min_is_x = fcmp ole <2 x double> %x, %y
@@ -16,7 +16,7 @@ define <2 x double> @minpd(<2 x double> %x, <2 x double> %y) {
   ret <2 x double> %min
 }
 
-; UNSAFE: maxps:
+; UNSAFE-LABEL: maxps:
 ; UNSAFE: vmaxps {{.+}}, %xmm
 define <4 x float> @maxps(<4 x float> %x, <4 x float> %y) {
   %max_is_x = fcmp oge <4 x float> %x, %y
@@ -24,7 +24,7 @@ define <4 x float> @maxps(<4 x float> %x, <4 x float> %y) {
   ret <4 x float> %max
 }
 
-; UNSAFE: minps:
+; UNSAFE-LABEL: minps:
 ; UNSAFE: vminps {{.+}}, %xmm
 define <4 x float> @minps(<4 x float> %x, <4 x float> %y) {
   %min_is_x = fcmp ole <4 x float> %x, %y
@@ -32,7 +32,7 @@ define <4 x float> @minps(<4 x float> %x, <4 x float> %y) {
   ret <4 x float> %min
 }
 
-; UNSAFE: vmaxpd:
+; UNSAFE-LABEL: vmaxpd:
 ; UNSAFE: vmaxpd {{.+}}, %ymm
 define <4 x double> @vmaxpd(<4 x double> %x, <4 x double> %y) {
   %max_is_x = fcmp oge <4 x double> %x, %y
@@ -40,7 +40,7 @@ define <4 x double> @vmaxpd(<4 x double> %x, <4 x double> %y) {
   ret <4 x double> %max
 }
 
-; UNSAFE: vminpd:
+; UNSAFE-LABEL: vminpd:
 ; UNSAFE: vminpd {{.+}}, %ymm
 define <4 x double> @vminpd(<4 x double> %x, <4 x double> %y) {
   %min_is_x = fcmp ole <4 x double> %x, %y
@@ -48,7 +48,7 @@ define <4 x double> @vminpd(<4 x double> %x, <4 x double> %y) {
   ret <4 x double> %min
 }
 
-; UNSAFE: vmaxps:
+; UNSAFE-LABEL: vmaxps:
 ; UNSAFE: vmaxps {{.+}}, %ymm
 define <8 x float> @vmaxps(<8 x float> %x, <8 x float> %y) {
   %max_is_x = fcmp oge <8 x float> %x, %y
@@ -56,7 +56,7 @@ define <8 x float> @vmaxps(<8 x float> %x, <8 x float> %y) {
   ret <8 x float> %max
 }
 
-; UNSAFE: vminps:
+; UNSAFE-LABEL: vminps:
 ; UNSAFE: vminps {{.+}}, %ymm
 define <8 x float> @vminps(<8 x float> %x, <8 x float> %y) {
   %min_is_x = fcmp ole <8 x float> %x, %y
diff --git a/test/CodeGen/X86/avx-shift.ll b/test/CodeGen/X86/avx-shift.ll
index 01eb736..d79dfcc 100644
--- a/test/CodeGen/X86/avx-shift.ll
+++ b/test/CodeGen/X86/avx-shift.ll
@@ -103,9 +103,10 @@ define <32 x i8> @vshift12(<32 x i8> %a) nounwind readnone {
 
 ;;; Support variable shifts
 ; CHECK: _vshift08
-; CHECK: vextractf128 $1
 ; CHECK: vpslld $23
+; CHECK: vextractf128 $1
 ; CHECK: vpslld $23
+; CHECK: ret
 define <8 x i32> @vshift08(<8 x i32> %a) nounwind {
   %bitop = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %a
   ret <8 x i32> %bitop
diff --git a/test/CodeGen/X86/avx-shuffle-x86_32.ll b/test/CodeGen/X86/avx-shuffle-x86_32.ll
index e203c4e..78b4888 100644
--- a/test/CodeGen/X86/avx-shuffle-x86_32.ll
+++ b/test/CodeGen/X86/avx-shuffle-x86_32.ll
@@ -3,6 +3,6 @@
 define <4 x i64> @test1(<4 x i64> %a) nounwind {
  %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
  ret <4 x i64>%b
- ; CHECK: test1:
+ ; CHECK-LABEL: test1:
  ; CHECK-NOT: vinsertf128
  }
diff --git a/test/CodeGen/X86/avx-shuffle.ll b/test/CodeGen/X86/avx-shuffle.ll
index 73faa1f..a625601 100644
--- a/test/CodeGen/X86/avx-shuffle.ll
+++ b/test/CodeGen/X86/avx-shuffle.ll
@@ -4,14 +4,14 @@
 define <4 x float> @test1(<4 x float> %a) nounwind {
   %b = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 undef, i32 undef>
   ret <4 x float> %b
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: vshufps
 ; CHECK: vpshufd
 }
 
 ; rdar://10538417
 define <3 x i64> @test2(<2 x i64> %v) nounwind readnone {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: vinsertf128
   %1 = shufflevector <2 x i64> %v, <2 x i64> %v, <3 x i32> <i32 0, i32 1, i32 undef>
   %2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> <i32 3, i32 4, i32 2>
@@ -22,7 +22,7 @@ define <3 x i64> @test2(<2 x i64> %v) nounwind readnone {
 define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind {
   %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 undef>
   ret <4 x i64> %c
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: vperm2f128
 ; CHECK: ret
 }
@@ -30,7 +30,7 @@ define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind {
 define <8 x float> @test4(float %a) nounwind {
   %b = insertelement <8 x float> zeroinitializer, float %a, i32 0
   ret <8 x float> %b
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: vinsertf128
 }
 
@@ -220,7 +220,7 @@ define <16 x i16> @narrow(<16 x i16> %a) nounwind alwaysinline {
   ret <16 x i16> %t
 }
 
-;CHECK: test17
+;CHECK-LABEL: test17:
 ;CHECK-NOT: vinsertf128
 ;CHECK: ret
 define   <8 x float> @test17(<4 x float> %y) {
diff --git a/test/CodeGen/X86/avx-varargs-x86_64.ll b/test/CodeGen/X86/avx-varargs-x86_64.ll
index b0932bd..f73174d 100644
--- a/test/CodeGen/X86/avx-varargs-x86_64.ll
+++ b/test/CodeGen/X86/avx-varargs-x86_64.ll
@@ -5,7 +5,7 @@
 @x = common global <8 x float> zeroinitializer, align 32
 declare i32 @f(i32, ...)
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: vmovaps	%ymm0, (%rsp)
 define void @test1() nounwind uwtable ssp {
 entry:
diff --git a/test/CodeGen/X86/avx-vextractf128.ll b/test/CodeGen/X86/avx-vextractf128.ll
index ad8365b..fa49f94 100644
--- a/test/CodeGen/X86/avx-vextractf128.ll
+++ b/test/CodeGen/X86/avx-vextractf128.ll
@@ -114,7 +114,7 @@ define void @t9(i64* %p) {
  store i64 0, i64* %s
  ret void
 
-; CHECK: t9:
+; CHECK-LABEL: t9:
 ; CHECK: vxorps	%xmm
 ; CHECK-NOT: vextractf
 ; CHECK: vmovups
diff --git a/test/CodeGen/X86/avx-zext.ll b/test/CodeGen/X86/avx-zext.ll
index 582537e..e2b6c55 100644
--- a/test/CodeGen/X86/avx-zext.ll
+++ b/test/CodeGen/X86/avx-zext.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
 
 define <8 x i32> @zext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
-;CHECK: zext_8i16_to_8i32
+;CHECK-LABEL: zext_8i16_to_8i32:
 ;CHECK: vpunpckhwd
 ;CHECK: ret
 
@@ -10,7 +10,7 @@ define <8 x i32> @zext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp
 }
 
 define <4 x i64> @zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
-;CHECK: zext_4i32_to_4i64
+;CHECK-LABEL: zext_4i32_to_4i64:
 ;CHECK: vpunpckhdq
 ;CHECK: ret
 
@@ -19,7 +19,7 @@ define <4 x i64> @zext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp
 }
 
 define <8 x i32> @zext_8i8_to_8i32(<8 x i8> %z) {
-;CHECK: zext_8i8_to_8i32
+;CHECK-LABEL: zext_8i8_to_8i32:
 ;CHECK: vpunpckhwd
 ;CHECK: vpmovzxwd
 ;CHECK: vinsertf128
diff --git a/test/CodeGen/X86/avx2-arith.ll b/test/CodeGen/X86/avx2-arith.ll
index 09f9538..997fa19 100644
--- a/test/CodeGen/X86/avx2-arith.ll
+++ b/test/CodeGen/X86/avx2-arith.ll
@@ -1,65 +1,66 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
 
 ; CHECK: vpaddq %ymm
-define <4 x i64> @vpaddq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
+define <4 x i64> @test_vpaddq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
   %x = add <4 x i64> %i, %j
   ret <4 x i64> %x
 }
 
 ; CHECK: vpaddd %ymm
-define <8 x i32> @vpaddd(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
+define <8 x i32> @test_vpaddd(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
   %x = add <8 x i32> %i, %j
   ret <8 x i32> %x
 }
 
 ; CHECK: vpaddw %ymm
-define <16 x i16> @vpaddw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
+define <16 x i16> @test_vpaddw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
   %x = add <16 x i16> %i, %j
   ret <16 x i16> %x
 }
 
 ; CHECK: vpaddb %ymm
-define <32 x i8> @vpaddb(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
+define <32 x i8> @test_vpaddb(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
   %x = add <32 x i8> %i, %j
   ret <32 x i8> %x
 }
 
 ; CHECK: vpsubq %ymm
-define <4 x i64> @vpsubq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
+define <4 x i64> @test_vpsubq(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
   %x = sub <4 x i64> %i, %j
   ret <4 x i64> %x
 }
 
 ; CHECK: vpsubd %ymm
-define <8 x i32> @vpsubd(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
+define <8 x i32> @test_vpsubd(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
   %x = sub <8 x i32> %i, %j
   ret <8 x i32> %x
 }
 
 ; CHECK: vpsubw %ymm
-define <16 x i16> @vpsubw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
+define <16 x i16> @test_vpsubw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
   %x = sub <16 x i16> %i, %j
   ret <16 x i16> %x
 }
 
 ; CHECK: vpsubb %ymm
-define <32 x i8> @vpsubb(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
+define <32 x i8> @test_vpsubb(<32 x i8> %i, <32 x i8> %j) nounwind readnone {
   %x = sub <32 x i8> %i, %j
   ret <32 x i8> %x
 }
 
 ; CHECK: vpmulld %ymm
-define <8 x i32> @vpmulld(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
+define <8 x i32> @test_vpmulld(<8 x i32> %i, <8 x i32> %j) nounwind readnone {
   %x = mul <8 x i32> %i, %j
   ret <8 x i32> %x
 }
 
 ; CHECK: vpmullw %ymm
-define <16 x i16> @vpmullw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
+define <16 x i16> @test_vpmullw(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
   %x = mul <16 x i16> %i, %j
   ret <16 x i16> %x
 }
 
+; CHECK: mul-v4i64
 ; CHECK: vpmuludq %ymm
 ; CHECK-NEXT: vpsrlq $32, %ymm
 ; CHECK-NEXT: vpmuludq %ymm
@@ -74,3 +75,76 @@ define <4 x i64> @mul-v4i64(<4 x i64> %i, <4 x i64> %j) nounwind readnone {
   ret <4 x i64> %x
 }
 
+; CHECK: mul_const1
+; CHECK: vpaddd
+; CHECK: ret
+define <8 x i32> @mul_const1(<8 x i32> %x) {
+  %y = mul <8 x i32> %x, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
+  ret <8 x i32> %y
+}
+
+; CHECK: mul_const2
+; CHECK: vpsllq  $2
+; CHECK: ret
+define <4 x i64> @mul_const2(<4 x i64> %x) {
+  %y = mul <4 x i64> %x, <i64 4, i64 4, i64 4, i64 4>
+  ret <4 x i64> %y
+}
+
+; CHECK: mul_const3
+; CHECK: vpsllw  $3
+; CHECK: ret
+define <16 x i16> @mul_const3(<16 x i16> %x) {
+  %y = mul <16 x i16> %x, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+  ret <16 x i16> %y
+}
+
+; CHECK: mul_const4
+; CHECK: vpxor
+; CHECK: vpsubq
+; CHECK: ret
+define <4 x i64> @mul_const4(<4 x i64> %x) {
+  %y = mul <4 x i64> %x, <i64 -1, i64 -1, i64 -1, i64 -1>
+  ret <4 x i64> %y
+}
+
+; CHECK: mul_const5
+; CHECK: vxorps
+; CHECK-NEXT: ret
+define <8 x i32> @mul_const5(<8 x i32> %x) {
+  %y = mul <8 x i32> %x, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+  ret <8 x i32> %y
+}
+
+; CHECK: mul_const6
+; CHECK: vpmulld
+; CHECK: ret
+define <8 x i32> @mul_const6(<8 x i32> %x) {
+  %y = mul <8 x i32> %x, <i32 0, i32 0, i32 0, i32 2, i32 0, i32 2, i32 0, i32 0>
+  ret <8 x i32> %y
+}
+
+; CHECK: mul_const7
+; CHECK: vpaddq
+; CHECK: vpaddq
+; CHECK: ret
+define <8 x i64> @mul_const7(<8 x i64> %x) {
+  %y = mul <8 x i64> %x, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
+  ret <8 x i64> %y
+}
+
+; CHECK: mul_const8
+; CHECK: vpsllw  $3
+; CHECK: ret
+define <8 x i16> @mul_const8(<8 x i16> %x) {
+  %y = mul <8 x i16> %x, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+  ret <8 x i16> %y
+}
+
+; CHECK: mul_const9
+; CHECK: vpmulld
+; CHECK: ret
+define <8 x i32> @mul_const9(<8 x i32> %x) {
+  %y = mul <8 x i32> %x, <i32 2, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+  ret <8 x i32> %y
+}
diff --git a/test/CodeGen/X86/avx2-logic.ll b/test/CodeGen/X86/avx2-logic.ll
index a5bb1a8..3d4fcec 100644
--- a/test/CodeGen/X86/avx2-logic.ll
+++ b/test/CodeGen/X86/avx2-logic.ll
@@ -55,7 +55,7 @@ define <32 x i8> @vpblendvb(<32 x i1> %cond, <32 x i8> %x, <32 x i8> %y) {
 
 define <8 x i32> @signd(<8 x i32> %a, <8 x i32> %b) nounwind {
 entry:
-; CHECK: signd:
+; CHECK-LABEL: signd:
 ; CHECK: psignd
 ; CHECK-NOT: sub
 ; CHECK: ret
@@ -70,7 +70,7 @@ entry:
 
 define <8 x i32> @blendvb(<8 x i32> %b, <8 x i32> %a, <8 x i32> %c) nounwind {
 entry:
-; CHECK: blendvb:
+; CHECK-LABEL: blendvb:
 ; CHECK: pblendvb
 ; CHECK: ret
   %b.lobit = ashr <8 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
diff --git a/test/CodeGen/X86/avx2-palignr.ll b/test/CodeGen/X86/avx2-palignr.ll
index 53b9da3..176e02c 100644
--- a/test/CodeGen/X86/avx2-palignr.ll
+++ b/test/CodeGen/X86/avx2-palignr.ll
@@ -1,56 +1,56 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
 
 define <8 x i32> @test1(<8 x i32> %A, <8 x i32> %B) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: vpalignr $4
   %C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 7, i32 12>
   ret <8 x i32> %C
 }
 
 define <8 x i32> @test2(<8 x i32> %A, <8 x i32> %B) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: vpalignr $4
   %C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 undef, i32 12>
   ret <8 x i32> %C
 }
 
 define <8 x i32> @test3(<8 x i32> %A, <8 x i32> %B) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: vpalignr $4
   %C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 1, i32 undef, i32 3, i32 8, i32 5, i32 6, i32 7, i32 12>
   ret <8 x i32> %C
 }
 ;
 define <8 x i32> @test4(<8 x i32> %A, <8 x i32> %B) nounwind {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: vpalignr $8
   %C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 10, i32 11, i32 undef, i32 1, i32 14, i32 15, i32 4, i32 5>
   ret <8 x i32> %C
 }
 
 define <16 x i16> @test5(<16 x i16> %A, <16 x i16> %B) nounwind {
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: vpalignr $6
   %C = shufflevector <16 x i16> %A, <16 x i16> %B, <16 x i32> <i32 3, i32 4, i32 undef, i32 6, i32 7, i32 16, i32 17, i32 18, i32 11, i32 12, i32 13, i32 undef, i32 15, i32 24, i32 25, i32 26>
   ret <16 x i16> %C
 }
 
 define <16 x i16> @test6(<16 x i16> %A, <16 x i16> %B) nounwind {
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: vpalignr $6
   %C = shufflevector <16 x i16> %A, <16 x i16> %B, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 11, i32 12, i32 13, i32 undef, i32 15, i32 24, i32 25, i32 26>
   ret <16 x i16> %C
 }
 
 define <16 x i16> @test7(<16 x i16> %A, <16 x i16> %B) nounwind {
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: vpalignr $6
   %C = shufflevector <16 x i16> %A, <16 x i16> %B, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   ret <16 x i16> %C
 }
 
 define <32 x i8> @test8(<32 x i8> %A, <32 x i8> %B) nounwind {
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: palignr $5
   %C = shufflevector <32 x i8> %A, <32 x i8> %B, <32 x i32> <i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52>
   ret <32 x i8> %C
diff --git a/test/CodeGen/X86/avx2-phaddsub.ll b/test/CodeGen/X86/avx2-phaddsub.ll
index 4eac71d..3f9c95c 100644
--- a/test/CodeGen/X86/avx2-phaddsub.ll
+++ b/test/CodeGen/X86/avx2-phaddsub.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+avx2 | FileCheck %s
 
-; CHECK: phaddw1:
+; CHECK-LABEL: phaddw1:
 ; CHECK: vphaddw
 define <16 x i16> @phaddw1(<16 x i16> %x, <16 x i16> %y) {
   %a = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
@@ -9,7 +9,7 @@ define <16 x i16> @phaddw1(<16 x i16> %x, <16 x i16> %y) {
   ret <16 x i16> %r
 }
 
-; CHECK: phaddw2:
+; CHECK-LABEL: phaddw2:
 ; CHECK: vphaddw
 define <16 x i16> @phaddw2(<16 x i16> %x, <16 x i16> %y) {
   %a = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
@@ -18,7 +18,7 @@ define <16 x i16> @phaddw2(<16 x i16> %x, <16 x i16> %y) {
   ret <16 x i16> %r
 }
 
-; CHECK: phaddd1:
+; CHECK-LABEL: phaddd1:
 ; CHECK: vphaddd
 define <8 x i32> @phaddd1(<8 x i32> %x, <8 x i32> %y) {
   %a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
@@ -27,7 +27,7 @@ define <8 x i32> @phaddd1(<8 x i32> %x, <8 x i32> %y) {
   ret <8 x i32> %r
 }
 
-; CHECK: phaddd2:
+; CHECK-LABEL: phaddd2:
 ; CHECK: vphaddd
 define <8 x i32> @phaddd2(<8 x i32> %x, <8 x i32> %y) {
   %a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 1, i32 2, i32 9, i32 10, i32 5, i32 6, i32 13, i32 14>
@@ -36,7 +36,7 @@ define <8 x i32> @phaddd2(<8 x i32> %x, <8 x i32> %y) {
   ret <8 x i32> %r
 }
 
-; CHECK: phaddd3:
+; CHECK-LABEL: phaddd3:
 ; CHECK: vphaddd
 define <8 x i32> @phaddd3(<8 x i32> %x) {
   %a = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
@@ -45,7 +45,7 @@ define <8 x i32> @phaddd3(<8 x i32> %x) {
   ret <8 x i32> %r
 }
 
-; CHECK: phsubw1:
+; CHECK-LABEL: phsubw1:
 ; CHECK: vphsubw
 define <16 x i16> @phsubw1(<16 x i16> %x, <16 x i16> %y) {
   %a = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
@@ -54,7 +54,7 @@ define <16 x i16> @phsubw1(<16 x i16> %x, <16 x i16> %y) {
   ret <16 x i16> %r
 }
 
-; CHECK: phsubd1:
+; CHECK-LABEL: phsubd1:
 ; CHECK: vphsubd
 define <8 x i32> @phsubd1(<8 x i32> %x, <8 x i32> %y) {
   %a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
@@ -63,7 +63,7 @@ define <8 x i32> @phsubd1(<8 x i32> %x, <8 x i32> %y) {
   ret <8 x i32> %r
 }
 
-; CHECK: phsubd2:
+; CHECK-LABEL: phsubd2:
 ; CHECK: vphsubd
 define <8 x i32> @phsubd2(<8 x i32> %x, <8 x i32> %y) {
   %a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 undef, i32 8, i32 undef, i32 4, i32 6, i32 12, i32 14>
diff --git a/test/CodeGen/X86/avx2-shift.ll b/test/CodeGen/X86/avx2-shift.ll
index 1f192a0..7fdbaaa 100644
--- a/test/CodeGen/X86/avx2-shift.ll
+++ b/test/CodeGen/X86/avx2-shift.ll
@@ -212,7 +212,7 @@ define <4 x i64> @variable_srl3_load(<4 x i64> %x, <4 x i64>* %y) {
 define <32 x i8> @shl9(<32 x i8> %A) nounwind {
   %B = shl <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ret <32 x i8> %B
-; CHECK: shl9:
+; CHECK-LABEL: shl9:
 ; CHECK: vpsllw $3
 ; CHECK: vpand
 ; CHECK: ret
@@ -221,7 +221,7 @@ define <32 x i8> @shl9(<32 x i8> %A) nounwind {
 define <32 x i8> @shr9(<32 x i8> %A) nounwind {
   %B = lshr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ret <32 x i8> %B
-; CHECK: shr9:
+; CHECK-LABEL: shr9:
 ; CHECK: vpsrlw $3
 ; CHECK: vpand
 ; CHECK: ret
@@ -230,7 +230,7 @@ define <32 x i8> @shr9(<32 x i8> %A) nounwind {
 define <32 x i8> @sra_v32i8_7(<32 x i8> %A) nounwind {
   %B = ashr <32 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
   ret <32 x i8> %B
-; CHECK: sra_v32i8_7:
+; CHECK-LABEL: sra_v32i8_7:
 ; CHECK: vpxor
 ; CHECK: vpcmpgtb
 ; CHECK: ret
@@ -239,7 +239,7 @@ define <32 x i8> @sra_v32i8_7(<32 x i8> %A) nounwind {
 define <32 x i8> @sra_v32i8(<32 x i8> %A) nounwind {
   %B = ashr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ret <32 x i8> %B
-; CHECK: sra_v32i8:
+; CHECK-LABEL: sra_v32i8:
 ; CHECK: vpsrlw $3
 ; CHECK: vpand
 ; CHECK: vpxor
diff --git a/test/CodeGen/X86/avx2-shuffle.ll b/test/CodeGen/X86/avx2-shuffle.ll
index cf319cb..0e6dd29 100644
--- a/test/CodeGen/X86/avx2-shuffle.ll
+++ b/test/CodeGen/X86/avx2-shuffle.ll
@@ -54,10 +54,10 @@ define <8 x float> @blend_test3(<8 x float> %a, <8 x float> %b) nounwind alwaysi
 
 ; CHECK: blend_test4
 ; CHECK: vblendpd
-; CHECK: ret

-define <4 x i64> @blend_test4(<4 x i64> %a, <4 x i64> %b) nounwind alwaysinline {

-  %t = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 3>

-  ret <4 x i64> %t

+; CHECK: ret
+define <4 x i64> @blend_test4(<4 x i64> %a, <4 x i64> %b) nounwind alwaysinline {
+  %t = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
+  ret <4 x i64> %t
 }
 
 ; CHECK: vpshufhw $27, %ymm
diff --git a/test/CodeGen/X86/avx2-vbroadcast.ll b/test/CodeGen/X86/avx2-vbroadcast.ll
index b804233..5610416 100644
--- a/test/CodeGen/X86/avx2-vbroadcast.ll
+++ b/test/CodeGen/X86/avx2-vbroadcast.ll
@@ -259,7 +259,7 @@ define <4 x double> @_inreg3(double %scalar) nounwind uwtable readnone ssp {
   ret <4 x double> %wide
 }
 
-;CHECK: _inreg8xfloat
+;CHECK-LABEL: _inreg8xfloat:
 ;CHECK: vbroadcastss
 ;CHECK: ret
 define   <8 x float> @_inreg8xfloat(<8 x float> %a) {
@@ -267,7 +267,7 @@ define   <8 x float> @_inreg8xfloat(<8 x float> %a) {
   ret <8 x float> %b
 }
 
-;CHECK: _inreg4xfloat
+;CHECK-LABEL: _inreg4xfloat:
 ;CHECK: vbroadcastss
 ;CHECK: ret
 define   <4 x float> @_inreg4xfloat(<4 x float> %a) {
@@ -275,7 +275,7 @@ define   <4 x float> @_inreg4xfloat(<4 x float> %a) {
   ret <4 x float> %b
 }
 
-;CHECK: _inreg16xi16
+;CHECK-LABEL: _inreg16xi16:
 ;CHECK: vpbroadcastw
 ;CHECK: ret
 define   <16 x i16> @_inreg16xi16(<16 x i16> %a) {
@@ -283,7 +283,7 @@ define   <16 x i16> @_inreg16xi16(<16 x i16> %a) {
   ret <16 x i16> %b
 }
 
-;CHECK: _inreg8xi16
+;CHECK-LABEL: _inreg8xi16:
 ;CHECK: vpbroadcastw
 ;CHECK: ret
 define   <8 x i16> @_inreg8xi16(<8 x i16> %a) {
@@ -292,7 +292,7 @@ define   <8 x i16> @_inreg8xi16(<8 x i16> %a) {
 }
 
 
-;CHECK: _inreg4xi64
+;CHECK-LABEL: _inreg4xi64:
 ;CHECK: vpbroadcastq
 ;CHECK: ret
 define   <4 x i64> @_inreg4xi64(<4 x i64> %a) {
@@ -300,7 +300,7 @@ define   <4 x i64> @_inreg4xi64(<4 x i64> %a) {
   ret <4 x i64> %b
 }
 
-;CHECK: _inreg2xi64
+;CHECK-LABEL: _inreg2xi64:
 ;CHECK: vpbroadcastq
 ;CHECK: ret
 define   <2 x i64> @_inreg2xi64(<2 x i64> %a) {
@@ -308,7 +308,7 @@ define   <2 x i64> @_inreg2xi64(<2 x i64> %a) {
   ret <2 x i64> %b
 }
 
-;CHECK: _inreg4xdouble
+;CHECK-LABEL: _inreg4xdouble:
 ;CHECK: vbroadcastsd
 ;CHECK: ret
 define   <4 x double> @_inreg4xdouble(<4 x double> %a) {
@@ -316,7 +316,7 @@ define   <4 x double> @_inreg4xdouble(<4 x double> %a) {
   ret <4 x double> %b
 }
 
-;CHECK: _inreg2xdouble
+;CHECK-LABEL: _inreg2xdouble:
 ;CHECK: vpbroadcastq
 ;CHECK: ret
 define   <2 x double> @_inreg2xdouble(<2 x double> %a) {
@@ -324,7 +324,7 @@ define   <2 x double> @_inreg2xdouble(<2 x double> %a) {
   ret <2 x double> %b
 }
 
-;CHECK: _inreg8xi32
+;CHECK-LABEL: _inreg8xi32:
 ;CHECK: vpbroadcastd
 ;CHECK: ret
 define   <8 x i32> @_inreg8xi32(<8 x i32> %a) {
@@ -332,7 +332,7 @@ define   <8 x i32> @_inreg8xi32(<8 x i32> %a) {
   ret <8 x i32> %b
 }
 
-;CHECK: _inreg4xi32
+;CHECK-LABEL: _inreg4xi32:
 ;CHECK: vpbroadcastd
 ;CHECK: ret
 define   <4 x i32> @_inreg4xi32(<4 x i32> %a) {
@@ -340,7 +340,7 @@ define   <4 x i32> @_inreg4xi32(<4 x i32> %a) {
   ret <4 x i32> %b
 }
 
-;CHECK: _inreg32xi8
+;CHECK-LABEL: _inreg32xi8:
 ;CHECK: vpbroadcastb
 ;CHECK: ret
 define   <32 x i8> @_inreg32xi8(<32 x i8> %a) {
@@ -348,7 +348,7 @@ define   <32 x i8> @_inreg32xi8(<32 x i8> %a) {
   ret <32 x i8> %b
 }
 
-;CHECK: _inreg16xi8
+;CHECK-LABEL: _inreg16xi8:
 ;CHECK: vpbroadcastb
 ;CHECK: ret
 define   <16 x i8> @_inreg16xi8(<16 x i8> %a) {
diff --git a/test/CodeGen/X86/avx2-vector-shifts.ll b/test/CodeGen/X86/avx2-vector-shifts.ll
new file mode 100644
index 0000000..a978d93
--- /dev/null
+++ b/test/CodeGen/X86/avx2-vector-shifts.ll
@@ -0,0 +1,247 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
+
+; AVX2 Logical Shift Left
+
+define <16 x i16> @test_sllw_1(<16 x i16> %InVec) {
+entry:
+  %shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+  ret <16 x i16> %shl
+}
+
+; CHECK-LABEL: test_sllw_1:
+; CHECK: vpsllw  $0, %ymm0, %ymm0
+; CHECK: ret
+
+define <16 x i16> @test_sllw_2(<16 x i16> %InVec) {
+entry:
+  %shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <16 x i16> %shl
+}
+
+; CHECK-LABEL: test_sllw_2:
+; CHECK: vpaddw  %ymm0, %ymm0, %ymm0
+; CHECK: ret
+
+define <16 x i16> @test_sllw_3(<16 x i16> %InVec) {
+entry:
+  %shl = shl <16 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
+  ret <16 x i16> %shl
+}
+
+; CHECK-LABEL: test_sllw_3:
+; CHECK: vxorps  %ymm0, %ymm0, %ymm0
+; CHECK: ret
+
+define <8 x i32> @test_slld_1(<8 x i32> %InVec) {
+entry:
+  %shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+  ret <8 x i32> %shl
+}
+
+; CHECK-LABEL: test_slld_1:
+; CHECK: vpslld  $0, %ymm0, %ymm0
+; CHECK: ret
+
+define <8 x i32> @test_slld_2(<8 x i32> %InVec) {
+entry:
+  %shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+  ret <8 x i32> %shl
+}
+
+; CHECK-LABEL: test_slld_2:
+; CHECK: vpaddd  %ymm0, %ymm0, %ymm0
+; CHECK: ret
+
+define <8 x i32> @test_slld_3(<8 x i32> %InVec) {
+entry:
+  %shl = shl <8 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
+  ret <8 x i32> %shl
+}
+
+; CHECK-LABEL: test_slld_3:
+; CHECK: vxorps  %ymm0, %ymm0, %ymm0
+; CHECK: ret
+
+define <4 x i64> @test_sllq_1(<4 x i64> %InVec) {
+entry:
+  %shl = shl <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
+  ret <4 x i64> %shl
+}
+
+; CHECK-LABEL: test_sllq_1:
+; CHECK: vpsllq  $0, %ymm0, %ymm0
+; CHECK: ret
+
+define <4 x i64> @test_sllq_2(<4 x i64> %InVec) {
+entry:
+  %shl = shl <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
+  ret <4 x i64> %shl
+}
+
+; CHECK-LABEL: test_sllq_2:
+; CHECK: vpaddq  %ymm0, %ymm0, %ymm0
+; CHECK: ret
+
+define <4 x i64> @test_sllq_3(<4 x i64> %InVec) {
+entry:
+  %shl = shl <4 x i64> %InVec, <i64 64, i64 64, i64 64, i64 64>
+  ret <4 x i64> %shl
+}
+
+; CHECK-LABEL: test_sllq_3:
+; CHECK: vxorps  %ymm0, %ymm0, %ymm0
+; CHECK: ret
+
+; AVX2 Arithmetic Shift
+
+define <16 x i16> @test_sraw_1(<16 x i16> %InVec) {
+entry:
+  %shl = ashr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+  ret <16 x i16> %shl
+}
+
+; CHECK-LABEL: test_sraw_1:
+; CHECK: vpsraw  $0, %ymm0, %ymm0
+; CHECK: ret
+
+define <16 x i16> @test_sraw_2(<16 x i16> %InVec) {
+entry:
+  %shl = ashr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <16 x i16> %shl
+}
+
+; CHECK-LABEL: test_sraw_2:
+; CHECK: vpsraw  $1, %ymm0, %ymm0
+; CHECK: ret
+
+define <16 x i16> @test_sraw_3(<16 x i16> %InVec) {
+entry:
+  %shl = ashr <16 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
+  ret <16 x i16> %shl
+}
+
+; CHECK-LABEL: test_sraw_3:
+; CHECK: vpsraw  $16, %ymm0, %ymm0
+; CHECK: ret
+
+define <8 x i32> @test_srad_1(<8 x i32> %InVec) {
+entry:
+  %shl = ashr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+  ret <8 x i32> %shl
+}
+
+; CHECK-LABEL: test_srad_1:
+; CHECK: vpsrad  $0, %ymm0, %ymm0
+; CHECK: ret
+
+define <8 x i32> @test_srad_2(<8 x i32> %InVec) {
+entry:
+  %shl = ashr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+  ret <8 x i32> %shl
+}
+
+; CHECK-LABEL: test_srad_2:
+; CHECK: vpsrad  $1, %ymm0, %ymm0
+; CHECK: ret
+
+define <8 x i32> @test_srad_3(<8 x i32> %InVec) {
+entry:
+  %shl = ashr <8 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
+  ret <8 x i32> %shl
+}
+
+; CHECK-LABEL: test_srad_3:
+; CHECK: vpsrad  $32, %ymm0, %ymm0
+; CHECK: ret
+
+; SSE Logical Shift Right
+
+define <16 x i16> @test_srlw_1(<16 x i16> %InVec) {
+entry:
+  %shl = lshr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+  ret <16 x i16> %shl
+}
+
+; CHECK-LABEL: test_srlw_1:
+; CHECK: vpsrlw  $0, %ymm0, %ymm0
+; CHECK: ret
+
+define <16 x i16> @test_srlw_2(<16 x i16> %InVec) {
+entry:
+  %shl = lshr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <16 x i16> %shl
+}
+
+; CHECK-LABEL: test_srlw_2:
+; CHECK: vpsrlw  $1, %ymm0, %ymm0
+; CHECK: ret
+
+define <16 x i16> @test_srlw_3(<16 x i16> %InVec) {
+entry:
+  %shl = lshr <16 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
+  ret <16 x i16> %shl
+}
+
+; CHECK-LABEL: test_srlw_3:
+; CHECK: vxorps  %ymm0, %ymm0, %ymm0
+; CHECK: ret
+
+define <8 x i32> @test_srld_1(<8 x i32> %InVec) {
+entry:
+  %shl = lshr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+  ret <8 x i32> %shl
+}
+
+; CHECK-LABEL: test_srld_1:
+; CHECK: vpsrld  $0, %ymm0, %ymm0
+; CHECK: ret
+
+define <8 x i32> @test_srld_2(<8 x i32> %InVec) {
+entry:
+  %shl = lshr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+  ret <8 x i32> %shl
+}
+
+; CHECK-LABEL: test_srld_2:
+; CHECK: vpsrld  $1, %ymm0, %ymm0
+; CHECK: ret
+
+define <8 x i32> @test_srld_3(<8 x i32> %InVec) {
+entry:
+  %shl = lshr <8 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
+  ret <8 x i32> %shl
+}
+
+; CHECK-LABEL: test_srld_3:
+; CHECK: vxorps  %ymm0, %ymm0, %ymm0
+; CHECK: ret
+
+define <4 x i64> @test_srlq_1(<4 x i64> %InVec) {
+entry:
+  %shl = lshr <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
+  ret <4 x i64> %shl
+}
+
+; CHECK-LABEL: test_srlq_1:
+; CHECK: vpsrlq  $0, %ymm0, %ymm0
+; CHECK: ret
+
+define <4 x i64> @test_srlq_2(<4 x i64> %InVec) {
+entry:
+  %shl = lshr <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
+  ret <4 x i64> %shl
+}
+
+; CHECK-LABEL: test_srlq_2:
+; CHECK: vpsrlq  $1, %ymm0, %ymm0
+; CHECK: ret
+
+define <4 x i64> @test_srlq_3(<4 x i64> %InVec) {
+entry:
+  %shl = lshr <4 x i64> %InVec, <i64 64, i64 64, i64 64, i64 64>
+  ret <4 x i64> %shl
+}
+
+; CHECK-LABEL: test_srlq_3:
+; CHECK: vxorps  %ymm0, %ymm0, %ymm0
+; CHECK: ret
diff --git a/test/CodeGen/X86/avx512-insert-extract.ll b/test/CodeGen/X86/avx512-insert-extract.ll
new file mode 100644
index 0000000..189bdd7
--- /dev/null
+++ b/test/CodeGen/X86/avx512-insert-extract.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
+
+;CHECK: test1
+;CHECK: vinsertps
+;CHECK: vinsertf32x4
+;CHECK: ret
+define <16 x float> @test1(<16 x float> %x, float* %br, float %y) nounwind {
+  %rrr = load float* %br
+  %rrr2 = insertelement <16 x float> %x, float %rrr, i32 1
+  %rrr3 = insertelement <16 x float> %rrr2, float %y, i32 14
+  ret <16 x float> %rrr3
+}
+
+;CHECK: test2
+;CHECK: vinsertf32x4
+;CHECK: vextractf32x4
+;CHECK: vinsertf32x4
+;CHECK: ret
+define <8 x double> @test2(<8 x double> %x, double* %br, double %y) nounwind {
+  %rrr = load double* %br
+  %rrr2 = insertelement <8 x double> %x, double %rrr, i32 1
+  %rrr3 = insertelement <8 x double> %rrr2, double %y, i32 6
+  ret <8 x double> %rrr3
+}
+
+;CHECK: test3
+;CHECK: vextractf32x4
+;CHECK: vinsertf32x4
+;CHECK: ret
+define <16 x float> @test3(<16 x float> %x) nounwind {
+  %eee = extractelement <16 x float> %x, i32 4
+  %rrr2 = insertelement <16 x float> %x, float %eee, i32 1
+  ret <16 x float> %rrr2
+}
+
+;CHECK: test4
+;CHECK: vextracti32x4
+;CHECK: vinserti32x4
+;CHECK: ret
+define <8 x i64> @test4(<8 x i64> %x) nounwind {
+  %eee = extractelement <8 x i64> %x, i32 4
+  %rrr2 = insertelement <8 x i64> %x, i64 %eee, i32 1
+  ret <8 x i64> %rrr2
+}
+
+;CHECK: test5
+;CHECK: vextractpsz
+;CHECK: ret
+define i32 @test5(<4 x float> %x) nounwind {
+  %ef = extractelement <4 x float> %x, i32 3
+  %ei = bitcast float %ef to i32
+  ret i32 %ei
+}
+
+;CHECK: test6
+;CHECK: vextractpsz {{.*}}, (%rdi)
+;CHECK: ret
+define void @test6(<4 x float> %x, float* %out) nounwind {
+  %ef = extractelement <4 x float> %x, i32 3
+  store float %ef, float* %out, align 4
+  ret void
+}
+
diff --git a/test/CodeGen/X86/avx512-mask-op.ll b/test/CodeGen/X86/avx512-mask-op.ll
new file mode 100644
index 0000000..eec8873
--- /dev/null
+++ b/test/CodeGen/X86/avx512-mask-op.ll
@@ -0,0 +1,58 @@
+; RUN: llc < %s -march=x86-64 -mcpu=knl | FileCheck %s
+
+define i16 @mask16(i16 %x) {
+  %m0 = bitcast i16 %x to <16 x i1>
+  %m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
+  %ret = bitcast <16 x i1> %m1 to i16
+  ret i16 %ret
+; CHECK: mask16
+; CHECK: knotw
+; CHECK: ret
+}
+
+define i8 @mask8(i8 %x) {
+  %m0 = bitcast i8 %x to <8 x i1>
+  %m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
+  %ret = bitcast <8 x i1> %m1 to i8
+  ret i8 %ret
+; CHECK: mask8
+; CHECK: knotw
+; CHECK: ret
+}
+
+define i16 @mand16(i16 %x, i16 %y) {
+  %ma = bitcast i16 %x to <16 x i1>
+  %mb = bitcast i16 %y to <16 x i1>
+  %mc = and <16 x i1> %ma, %mb
+  %md = xor <16 x i1> %ma, %mb
+  %me = or <16 x i1> %mc, %md
+  %ret = bitcast <16 x i1> %me to i16
+; CHECK: kxorw
+; CHECK: kandw
+; CHECK: korw
+  ret i16 %ret
+}
+
+; CHECK: unpckbw_test
+; CHECK: kunpckbw
+; CHECK:ret
+declare <16 x i1> @llvm.x86.kunpck.v16i1(<8 x i1>, <8 x i1>) nounwind readnone
+
+define i16 @unpckbw_test(i8 %x, i8 %y) {
+  %m0 = bitcast i8 %x to <8 x i1>
+  %m1 = bitcast i8 %y to <8 x i1>
+  %k = tail call <16 x i1> @llvm.x86.kunpck.v16i1(<8 x i1> %m0, <8 x i1> %m1)
+  %r = bitcast <16 x i1> %k to i16
+  ret i16 %r
+}
+
+; CHECK: shuf_test1
+; CHECK: kshiftrw        $8
+; CHECK:ret
+define i8 @shuf_test1(i16 %v) nounwind {
+   %v1 = bitcast i16 %v to <16 x i1>
+   %mask = shufflevector <16 x i1> %v1, <16 x i1> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+   %mask1 = bitcast <8 x i1> %mask to i8
+   ret i8 %mask1
+}
+
diff --git a/test/CodeGen/X86/avx512-vbroadcast.ll b/test/CodeGen/X86/avx512-vbroadcast.ll
new file mode 100644
index 0000000..4f07f94
--- /dev/null
+++ b/test/CodeGen/X86/avx512-vbroadcast.ll
@@ -0,0 +1,37 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
+
+;CHECK: _inreg16xi32
+;CHECK: vpbroadcastd {{.*}}, %zmm
+;CHECK: ret
+define   <16 x i32> @_inreg16xi32(i32 %a) {
+  %b = insertelement <16 x i32> undef, i32 %a, i32 0
+  %c = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer
+  ret <16 x i32> %c
+}
+
+;CHECK: _inreg8xi64
+;CHECK: vpbroadcastq {{.*}}, %zmm
+;CHECK: ret
+define   <8 x i64> @_inreg8xi64(i64 %a) {
+  %b = insertelement <8 x i64> undef, i64 %a, i32 0
+  %c = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
+  ret <8 x i64> %c
+}
+
+;CHECK: _inreg16xfloat
+;CHECK: vbroadcastssz {{.*}}, %zmm
+;CHECK: ret
+define   <16 x float> @_inreg16xfloat(float %a) {
+  %b = insertelement <16 x float> undef, float %a, i32 0
+  %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer
+  ret <16 x float> %c
+}
+
+;CHECK: _inreg8xdouble
+;CHECK: vbroadcastsdz {{.*}}, %zmm
+;CHECK: ret
+define   <8 x double> @_inreg8xdouble(double %a) {
+  %b = insertelement <8 x double> undef, double %a, i32 0
+  %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer
+  ret <8 x double> %c
+}
diff --git a/test/CodeGen/X86/blend-msb.ll b/test/CodeGen/X86/blend-msb.ll
index e565da7..fa775bd 100644
--- a/test/CodeGen/X86/blend-msb.ll
+++ b/test/CodeGen/X86/blend-msb.ll
@@ -4,7 +4,7 @@
 ; In this test we check that sign-extend of the mask bit is performed by
 ; shifting the needed bit to the MSB, and not using shl+sra.
 
-;CHECK: vsel_float
+;CHECK-LABEL: vsel_float:
 ;CHECK: movl $-2147483648
 ;CHECK-NEXT: movd
 ;CHECK-NEXT: blendvps
@@ -14,7 +14,7 @@ define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
   ret <4 x float> %vsel
 }
 
-;CHECK: vsel_4xi8
+;CHECK-LABEL: vsel_4xi8:
 ;CHECK: movl $-2147483648
 ;CHECK-NEXT: movd
 ;CHECK-NEXT: blendvps
@@ -28,7 +28,7 @@ define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
 ; We do not have native support for v8i16 blends and we have to use the
 ; blendvb instruction or a sequence of NAND/OR/AND. Make sure that we do not r
 ; reduce the mask in this case.
-;CHECK: vsel_8xi16
+;CHECK-LABEL: vsel_8xi16:
 ;CHECK: psllw
 ;CHECK: psraw
 ;CHECK: pblendvb
diff --git a/test/CodeGen/X86/block-placement.ll b/test/CodeGen/X86/block-placement.ll
index be627e0..d3e05d6 100644
--- a/test/CodeGen/X86/block-placement.ll
+++ b/test/CodeGen/X86/block-placement.ll
@@ -1,11 +1,11 @@
-; RUN: llc -mtriple=i686-linux < %s | FileCheck %s
+; RUN: llc -mtriple=i686-linux -pre-RA-sched=source < %s | FileCheck %s
 
 declare void @error(i32 %i, i32 %a, i32 %b)
 
 define i32 @test_ifchains(i32 %i, i32* %a, i32 %b) {
 ; Test a chain of ifs, where the block guarded by the if is error handling code
 ; that is not expected to run.
-; CHECK: test_ifchains:
+; CHECK-LABEL: test_ifchains:
 ; CHECK: %entry
 ; CHECK-NOT: .align
 ; CHECK: %else1
@@ -79,7 +79,7 @@ exit:
 
 define i32 @test_loop_cold_blocks(i32 %i, i32* %a) {
 ; Check that we sink cold loop blocks after the hot loop body.
-; CHECK: test_loop_cold_blocks:
+; CHECK-LABEL: test_loop_cold_blocks:
 ; CHECK: %entry
 ; CHECK-NOT: .align
 ; CHECK: %unlikely1
@@ -128,7 +128,7 @@ exit:
 
 define i32 @test_loop_early_exits(i32 %i, i32* %a) {
 ; Check that we sink early exit blocks out of loop bodies.
-; CHECK: test_loop_early_exits:
+; CHECK-LABEL: test_loop_early_exits:
 ; CHECK: %entry
 ; CHECK: %body1
 ; CHECK: %body2
@@ -180,7 +180,7 @@ exit:
 define i32 @test_loop_rotate(i32 %i, i32* %a) {
 ; Check that we rotate conditional exits from the loop to the bottom of the
 ; loop, eliminating unconditional branches to the top.
-; CHECK: test_loop_rotate:
+; CHECK-LABEL: test_loop_rotate:
 ; CHECK: %entry
 ; CHECK: %body1
 ; CHECK: %body0
@@ -210,7 +210,7 @@ exit:
 define i32 @test_no_loop_rotate(i32 %i, i32* %a) {
 ; Check that we don't try to rotate a loop which is already laid out with
 ; fallthrough opportunities into the top and out of the bottom.
-; CHECK: test_no_loop_rotate:
+; CHECK-LABEL: test_no_loop_rotate:
 ; CHECK: %entry
 ; CHECK: %body0
 ; CHECK: %body1
@@ -278,7 +278,7 @@ exit:
 define i32 @test_loop_align(i32 %i, i32* %a) {
 ; Check that we provide basic loop body alignment with the block placement
 ; pass.
-; CHECK: test_loop_align:
+; CHECK-LABEL: test_loop_align:
 ; CHECK: %entry
 ; CHECK: .align [[ALIGN:[0-9]+]],
 ; CHECK-NEXT: %body
@@ -303,7 +303,7 @@ exit:
 
 define i32 @test_nested_loop_align(i32 %i, i32* %a, i32* %b) {
 ; Check that we provide nested loop body alignment.
-; CHECK: test_nested_loop_align:
+; CHECK-LABEL: test_nested_loop_align:
 ; CHECK: %entry
 ; CHECK: .align [[ALIGN]],
 ; CHECK-NEXT: %loop.body.1
@@ -997,7 +997,7 @@ define void @benchmark_heapsort(i32 %n, double* nocapture %ra) {
 ; CHECK: %while.body
 ; CHECK: %land.lhs.true
 ; CHECK: %if.then19
-; CHECK: %if.then19
+; CHECK: %if.end20
 ; CHECK: %if.then8
 ; CHECK: ret
 
@@ -1096,7 +1096,7 @@ define i32 @test_cold_calls(i32* %a) {
 ; Test that edges to blocks post-dominated by cold calls are
 ; marked as not expected to be taken.  They should be laid out
 ; at the bottom.
-; CHECK: test_cold_calls:
+; CHECK-LABEL: test_cold_calls:
 ; CHECK: %entry
 ; CHECK: %else
 ; CHECK: %exit
diff --git a/test/CodeGen/X86/bmi.ll b/test/CodeGen/X86/bmi.ll
index b89e648..4eda888 100644
--- a/test/CodeGen/X86/bmi.ll
+++ b/test/CodeGen/X86/bmi.ll
@@ -8,21 +8,21 @@ declare i64 @llvm.cttz.i64(i64, i1) nounwind readnone
 define i8 @t1(i8 %x) nounwind  {
   %tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 false )
   ret i8 %tmp
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: tzcntl
 }
 
 define i16 @t2(i16 %x) nounwind  {
   %tmp = tail call i16 @llvm.cttz.i16( i16 %x, i1 false )
   ret i16 %tmp
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: tzcntw
 }
 
 define i32 @t3(i32 %x) nounwind  {
   %tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 false )
   ret i32 %tmp
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: tzcntl
 }
 
@@ -30,42 +30,42 @@ define i32 @tzcnt32_load(i32* %x) nounwind  {
   %x1 = load i32* %x
   %tmp = tail call i32 @llvm.cttz.i32(i32 %x1, i1 false )
   ret i32 %tmp
-; CHECK: tzcnt32_load:
+; CHECK-LABEL: tzcnt32_load:
 ; CHECK: tzcntl ({{.*}})
 }
 
 define i64 @t4(i64 %x) nounwind  {
   %tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 false )
   ret i64 %tmp
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: tzcntq
 }
 
 define i8 @t5(i8 %x) nounwind  {
   %tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 true )
   ret i8 %tmp
-; CHECK: t5:
+; CHECK-LABEL: t5:
 ; CHECK: tzcntl
 }
 
 define i16 @t6(i16 %x) nounwind  {
   %tmp = tail call i16 @llvm.cttz.i16( i16 %x, i1 true )
   ret i16 %tmp
-; CHECK: t6:
+; CHECK-LABEL: t6:
 ; CHECK: tzcntw
 }
 
 define i32 @t7(i32 %x) nounwind  {
   %tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 true )
   ret i32 %tmp
-; CHECK: t7:
+; CHECK-LABEL: t7:
 ; CHECK: tzcntl
 }
 
 define i64 @t8(i64 %x) nounwind  {
   %tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 true )
   ret i64 %tmp
-; CHECK: t8:
+; CHECK-LABEL: t8:
 ; CHECK: tzcntq
 }
 
@@ -73,7 +73,7 @@ define i32 @andn32(i32 %x, i32 %y) nounwind readnone {
   %tmp1 = xor i32 %x, -1
   %tmp2 = and i32 %y, %tmp1
   ret i32 %tmp2
-; CHECK: andn32:
+; CHECK-LABEL: andn32:
 ; CHECK: andnl
 }
 
@@ -82,7 +82,7 @@ define i32 @andn32_load(i32 %x, i32* %y) nounwind readnone {
   %tmp1 = xor i32 %x, -1
   %tmp2 = and i32 %y1, %tmp1
   ret i32 %tmp2
-; CHECK: andn32_load:
+; CHECK-LABEL: andn32_load:
 ; CHECK: andnl ({{.*}})
 }
 
@@ -90,14 +90,14 @@ define i64 @andn64(i64 %x, i64 %y) nounwind readnone {
   %tmp1 = xor i64 %x, -1
   %tmp2 = and i64 %tmp1, %y
   ret i64 %tmp2
-; CHECK: andn64:
+; CHECK-LABEL: andn64:
 ; CHECK: andnq
 }
 
 define i32 @bextr32(i32 %x, i32 %y) nounwind readnone {
   %tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x, i32 %y)
   ret i32 %tmp
-; CHECK: bextr32:
+; CHECK-LABEL: bextr32:
 ; CHECK: bextrl
 }
 
@@ -105,7 +105,7 @@ define i32 @bextr32_load(i32* %x, i32 %y) nounwind readnone {
   %x1 = load i32* %x
   %tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x1, i32 %y)
   ret i32 %tmp
-; CHECK: bextr32_load:
+; CHECK-LABEL: bextr32_load:
 ; CHECK: bextrl {{.*}}, ({{.*}}), {{.*}}
 }
 
@@ -114,7 +114,7 @@ declare i32 @llvm.x86.bmi.bextr.32(i32, i32) nounwind readnone
 define i64 @bextr64(i64 %x, i64 %y) nounwind readnone {
   %tmp = tail call i64 @llvm.x86.bmi.bextr.64(i64 %x, i64 %y)
   ret i64 %tmp
-; CHECK: bextr64:
+; CHECK-LABEL: bextr64:
 ; CHECK: bextrq
 }
 
@@ -123,7 +123,7 @@ declare i64 @llvm.x86.bmi.bextr.64(i64, i64) nounwind readnone
 define i32 @bzhi32(i32 %x, i32 %y) nounwind readnone {
   %tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x, i32 %y)
   ret i32 %tmp
-; CHECK: bzhi32:
+; CHECK-LABEL: bzhi32:
 ; CHECK: bzhil
 }
 
@@ -131,7 +131,7 @@ define i32 @bzhi32_load(i32* %x, i32 %y) nounwind readnone {
   %x1 = load i32* %x
   %tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x1, i32 %y)
   ret i32 %tmp
-; CHECK: bzhi32_load:
+; CHECK-LABEL: bzhi32_load:
 ; CHECK: bzhil {{.*}}, ({{.*}}), {{.*}}
 }
 
@@ -140,7 +140,7 @@ declare i32 @llvm.x86.bmi.bzhi.32(i32, i32) nounwind readnone
 define i64 @bzhi64(i64 %x, i64 %y) nounwind readnone {
   %tmp = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %x, i64 %y)
   ret i64 %tmp
-; CHECK: bzhi64:
+; CHECK-LABEL: bzhi64:
 ; CHECK: bzhiq
 }
 
@@ -150,7 +150,7 @@ define i32 @blsi32(i32 %x) nounwind readnone {
   %tmp = sub i32 0, %x
   %tmp2 = and i32 %x, %tmp
   ret i32 %tmp2
-; CHECK: blsi32:
+; CHECK-LABEL: blsi32:
 ; CHECK: blsil
 }
 
@@ -159,7 +159,7 @@ define i32 @blsi32_load(i32* %x) nounwind readnone {
   %tmp = sub i32 0, %x1
   %tmp2 = and i32 %x1, %tmp
   ret i32 %tmp2
-; CHECK: blsi32_load:
+; CHECK-LABEL: blsi32_load:
 ; CHECK: blsil ({{.*}})
 }
 
@@ -167,7 +167,7 @@ define i64 @blsi64(i64 %x) nounwind readnone {
   %tmp = sub i64 0, %x
   %tmp2 = and i64 %tmp, %x
   ret i64 %tmp2
-; CHECK: blsi64:
+; CHECK-LABEL: blsi64:
 ; CHECK: blsiq
 }
 
@@ -175,7 +175,7 @@ define i32 @blsmsk32(i32 %x) nounwind readnone {
   %tmp = sub i32 %x, 1
   %tmp2 = xor i32 %x, %tmp
   ret i32 %tmp2
-; CHECK: blsmsk32:
+; CHECK-LABEL: blsmsk32:
 ; CHECK: blsmskl
 }
 
@@ -184,7 +184,7 @@ define i32 @blsmsk32_load(i32* %x) nounwind readnone {
   %tmp = sub i32 %x1, 1
   %tmp2 = xor i32 %x1, %tmp
   ret i32 %tmp2
-; CHECK: blsmsk32_load:
+; CHECK-LABEL: blsmsk32_load:
 ; CHECK: blsmskl ({{.*}})
 }
 
@@ -192,7 +192,7 @@ define i64 @blsmsk64(i64 %x) nounwind readnone {
   %tmp = sub i64 %x, 1
   %tmp2 = xor i64 %tmp, %x
   ret i64 %tmp2
-; CHECK: blsmsk64:
+; CHECK-LABEL: blsmsk64:
 ; CHECK: blsmskq
 }
 
@@ -200,7 +200,7 @@ define i32 @blsr32(i32 %x) nounwind readnone {
   %tmp = sub i32 %x, 1
   %tmp2 = and i32 %x, %tmp
   ret i32 %tmp2
-; CHECK: blsr32:
+; CHECK-LABEL: blsr32:
 ; CHECK: blsrl
 }
 
@@ -209,7 +209,7 @@ define i32 @blsr32_load(i32* %x) nounwind readnone {
   %tmp = sub i32 %x1, 1
   %tmp2 = and i32 %x1, %tmp
   ret i32 %tmp2
-; CHECK: blsr32_load:
+; CHECK-LABEL: blsr32_load:
 ; CHECK: blsrl ({{.*}})
 }
 
@@ -217,14 +217,14 @@ define i64 @blsr64(i64 %x) nounwind readnone {
   %tmp = sub i64 %x, 1
   %tmp2 = and i64 %tmp, %x
   ret i64 %tmp2
-; CHECK: blsr64:
+; CHECK-LABEL: blsr64:
 ; CHECK: blsrq
 }
 
 define i32 @pdep32(i32 %x, i32 %y) nounwind readnone {
   %tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y)
   ret i32 %tmp
-; CHECK: pdep32:
+; CHECK-LABEL: pdep32:
 ; CHECK: pdepl
 }
 
@@ -232,7 +232,7 @@ define i32 @pdep32_load(i32 %x, i32* %y) nounwind readnone {
   %y1 = load i32* %y
   %tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y1)
   ret i32 %tmp
-; CHECK: pdep32_load:
+; CHECK-LABEL: pdep32_load:
 ; CHECK: pdepl ({{.*}})
 }
 
@@ -241,7 +241,7 @@ declare i32 @llvm.x86.bmi.pdep.32(i32, i32) nounwind readnone
 define i64 @pdep64(i64 %x, i64 %y) nounwind readnone {
   %tmp = tail call i64 @llvm.x86.bmi.pdep.64(i64 %x, i64 %y)
   ret i64 %tmp
-; CHECK: pdep64:
+; CHECK-LABEL: pdep64:
 ; CHECK: pdepq
 }
 
@@ -250,7 +250,7 @@ declare i64 @llvm.x86.bmi.pdep.64(i64, i64) nounwind readnone
 define i32 @pext32(i32 %x, i32 %y) nounwind readnone {
   %tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y)
   ret i32 %tmp
-; CHECK: pext32:
+; CHECK-LABEL: pext32:
 ; CHECK: pextl
 }
 
@@ -258,7 +258,7 @@ define i32 @pext32_load(i32 %x, i32* %y) nounwind readnone {
   %y1 = load i32* %y
   %tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y1)
   ret i32 %tmp
-; CHECK: pext32_load:
+; CHECK-LABEL: pext32_load:
 ; CHECK: pextl ({{.*}})
 }
 
@@ -267,7 +267,7 @@ declare i32 @llvm.x86.bmi.pext.32(i32, i32) nounwind readnone
 define i64 @pext64(i64 %x, i64 %y) nounwind readnone {
   %tmp = tail call i64 @llvm.x86.bmi.pext.64(i64 %x, i64 %y)
   ret i64 %tmp
-; CHECK: pext64:
+; CHECK-LABEL: pext64:
 ; CHECK: pextq
 }
 
diff --git a/test/CodeGen/X86/brcond.ll b/test/CodeGen/X86/brcond.ll
index bc4032b..3ebe1a1 100644
--- a/test/CodeGen/X86/brcond.ll
+++ b/test/CodeGen/X86/brcond.ll
@@ -4,7 +4,7 @@
 
 define i32 @test1(i32 %a, i32 %b) nounwind ssp {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: xorb
 ; CHECK-NOT: andb
 ; CHECK-NOT: shrb
@@ -44,7 +44,7 @@ bb1:                                              ; preds = %entry
 
 return:                                           ; preds = %entry
   ret i32 192
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK:	movl	4(%esp), %eax
 ; CHECK-NEXT:	orl	8(%esp), %eax
 ; CHECK-NEXT:	jne	LBB1_2
@@ -63,7 +63,7 @@ bb1:                                              ; preds = %entry
 
 return:                                           ; preds = %entry
   ret i32 192
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK:	movl	4(%esp), %eax
 ; CHECK-NEXT:	orl	8(%esp), %eax
 ; CHECK-NEXT:	je	LBB2_2
@@ -113,7 +113,7 @@ declare i32 @llvm.x86.sse41.ptestc(<4 x float> %p1, <4 x float> %p2) nounwind
 
 define <4 x float> @test5(<4 x float> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: ptest
 ; CHECK-NEXT:	jne
 ; CHECK: ret
@@ -137,7 +137,7 @@ return:
 
 define <4 x float> @test7(<4 x float> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: ptest
 ; CHECK-NEXT:	jne
 ; CHECK: ret
@@ -161,7 +161,7 @@ return:
 
 define <4 x float> @test8(<4 x float> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: ptest
 ; CHECK-NEXT:	jae
 ; CHECK: ret
@@ -185,7 +185,7 @@ return:
 
 define <4 x float> @test10(<4 x float> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: ptest
 ; CHECK-NEXT:	jae
 ; CHECK: ret
@@ -209,7 +209,7 @@ return:
 
 define <4 x float> @test11(<4 x float> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK: ptest
 ; CHECK-NEXT:	jne
 ; CHECK: ret
@@ -233,7 +233,7 @@ return:
 
 define <4 x float> @test12(<4 x float> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK: ptest
 ; CHECK-NEXT:	je
 ; CHECK: ret
diff --git a/test/CodeGen/X86/break-sse-dep.ll b/test/CodeGen/X86/break-sse-dep.ll
index 4d80189..8124d6f 100644
--- a/test/CodeGen/X86/break-sse-dep.ll
+++ b/test/CodeGen/X86/break-sse-dep.ll
@@ -3,7 +3,7 @@
 
 define double @t1(float* nocapture %x) nounwind readonly ssp {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: movss ([[A0:%rdi|%rcx]]), %xmm0
 ; CHECK: cvtss2sd %xmm0, %xmm0
 
@@ -14,7 +14,7 @@ entry:
 
 define float @t2(double* nocapture %x) nounwind readonly ssp optsize {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: cvtsd2ss ([[A0]]), %xmm0
   %0 = load double* %x, align 8
   %1 = fptrunc double %0 to float
@@ -23,7 +23,7 @@ entry:
 
 define float @squirtf(float* %x) nounwind {
 entry:
-; CHECK: squirtf:
+; CHECK-LABEL: squirtf:
 ; CHECK: movss ([[A0]]), %xmm0
 ; CHECK: sqrtss %xmm0, %xmm0
   %z = load float* %x
@@ -33,7 +33,7 @@ entry:
 
 define double @squirt(double* %x) nounwind {
 entry:
-; CHECK: squirt:
+; CHECK-LABEL: squirt:
 ; CHECK: sqrtsd ([[A0]]), %xmm0
   %z = load double* %x
   %t = call double @llvm.sqrt.f64(double %z)
@@ -42,7 +42,7 @@ entry:
 
 define float @squirtf_size(float* %x) nounwind optsize {
 entry:
-; CHECK: squirtf_size:
+; CHECK-LABEL: squirtf_size:
 ; CHECK: sqrtss ([[A0]]), %xmm0
   %z = load float* %x
   %t = call float @llvm.sqrt.f32(float %z)
@@ -51,7 +51,7 @@ entry:
 
 define double @squirt_size(double* %x) nounwind optsize {
 entry:
-; CHECK: squirt_size:
+; CHECK-LABEL: squirt_size:
 ; CHECK: sqrtsd ([[A0]]), %xmm0
   %z = load double* %x
   %t = call double @llvm.sqrt.f64(double %z)
diff --git a/test/CodeGen/X86/bswap-inline-asm.ll b/test/CodeGen/X86/bswap-inline-asm.ll
index d69bfa6..f8f154c 100644
--- a/test/CodeGen/X86/bswap-inline-asm.ll
+++ b/test/CodeGen/X86/bswap-inline-asm.ll
@@ -3,84 +3,84 @@
 
 ; CHK-NOT: InlineAsm
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: bswapq
 define i64 @foo(i64 %x) nounwind {
 	%asmtmp = tail call i64 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
 	ret i64 %asmtmp
 }
 
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: bswapq
 define i64 @bar(i64 %x) nounwind {
 	%asmtmp = tail call i64 asm "bswapq ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
 	ret i64 %asmtmp
 }
 
-; CHECK: pen:
+; CHECK-LABEL: pen:
 ; CHECK: bswapl
 define i32 @pen(i32 %x) nounwind {
 	%asmtmp = tail call i32 asm "bswapl ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind
 	ret i32 %asmtmp
 }
 
-; CHECK: s16:
+; CHECK-LABEL: s16:
 ; CHECK: rolw    $8,
 define zeroext i16 @s16(i16 zeroext %x) nounwind {
   %asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind
   ret i16 %asmtmp
 }
 
-; CHECK: t16:
+; CHECK-LABEL: t16:
 ; CHECK: rolw    $8,
 define zeroext i16 @t16(i16 zeroext %x) nounwind {
   %asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind
   ret i16 %asmtmp
 }
 
-; CHECK: u16:
+; CHECK-LABEL: u16:
 ; CHECK: rolw    $8,
 define zeroext i16 @u16(i16 zeroext %x) nounwind {
   %asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind
   ret i16 %asmtmp
 }
 
-; CHECK: v16:
+; CHECK-LABEL: v16:
 ; CHECK: rolw    $8,
 define zeroext i16 @v16(i16 zeroext %x) nounwind {
   %asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind
   ret i16 %asmtmp
 }
 
-; CHECK: s32:
+; CHECK-LABEL: s32:
 ; CHECK: bswapl
 define i32 @s32(i32 %x) nounwind {
   %asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind
   ret i32 %asmtmp
 }
 
-; CHECK: t32:
+; CHECK-LABEL: t32:
 ; CHECK: bswapl
 define i32 @t32(i32 %x) nounwind {
   %asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{flags},~{fpsr}"(i32 %x) nounwind
   ret i32 %asmtmp
 }
 
-; CHECK: u32:
+; CHECK-LABEL: u32:
 ; CHECK: bswapl
 define i32 @u32(i32 %x) nounwind {
   %asmtmp = tail call i32 asm "rorw $$8, ${0:w};rorl $$16, $0;rorw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{flags},~{fpsr}"(i32 %x) nounwind
   ret i32 %asmtmp
 }
 
-; CHECK: s64:
+; CHECK-LABEL: s64:
 ; CHECK: bswapq
 define i64 @s64(i64 %x) nounwind {
   %asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
   ret i64 %asmtmp
 }
 
-; CHECK: t64:
+; CHECK-LABEL: t64:
 ; CHECK: bswapq
 define i64 @t64(i64 %x) nounwind {
   %asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{fpsr},~{dirflag},~{flags}"(i64 %x) nounwind
diff --git a/test/CodeGen/X86/bswap.ll b/test/CodeGen/X86/bswap.ll
index d2d6f90..9e46592 100644
--- a/test/CodeGen/X86/bswap.ll
+++ b/test/CodeGen/X86/bswap.ll
@@ -9,21 +9,21 @@ declare i32 @llvm.bswap.i32(i32)
 declare i64 @llvm.bswap.i64(i64)
 
 define i16 @W(i16 %A) {
-; CHECK: W:
+; CHECK-LABEL: W:
 ; CHECK: rolw $8, %ax
         %Z = call i16 @llvm.bswap.i16( i16 %A )         ; <i16> [#uses=1]
         ret i16 %Z
 }
 
 define i32 @X(i32 %A) {
-; CHECK: X:
+; CHECK-LABEL: X:
 ; CHECK: bswapl %eax
         %Z = call i32 @llvm.bswap.i32( i32 %A )         ; <i32> [#uses=1]
         ret i32 %Z
 }
 
 define i64 @Y(i64 %A) {
-; CHECK: Y:
+; CHECK-LABEL: Y:
 ; CHECK: bswapl %eax
 ; CHECK: bswapl %edx
         %Z = call i64 @llvm.bswap.i64( i64 %A )         ; <i64> [#uses=1]
diff --git a/test/CodeGen/X86/btq.ll b/test/CodeGen/X86/btq.ll
index 9c137a7..add6576 100644
--- a/test/CodeGen/X86/btq.ll
+++ b/test/CodeGen/X86/btq.ll
@@ -7,7 +7,7 @@ define void @test1(i64 %foo) nounwind {
   %tobool = icmp eq i64 %and, 0
   br i1 %tobool, label %if.end, label %if.then
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: btq $32
 
 if.then:
@@ -23,7 +23,7 @@ define void @test2(i64 %foo) nounwind {
   %tobool = icmp eq i64 %and, 0
   br i1 %tobool, label %if.end, label %if.then
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: testl $-2147483648
 
 if.then:
diff --git a/test/CodeGen/X86/byval7.ll b/test/CodeGen/X86/byval7.ll
index 98a26e4..8a96e41 100644
--- a/test/CodeGen/X86/byval7.ll
+++ b/test/CodeGen/X86/byval7.ll
@@ -6,7 +6,7 @@
 
 define i32 @main() nounwind  {
 entry:
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK: movl $1, (%esp)
 ; CHECK: leal 16(%esp), %edi
 ; CHECK: leal 160(%esp), %esi
diff --git a/test/CodeGen/X86/call-push.ll b/test/CodeGen/X86/call-push.ll
index e69f8c1..ccb98fe 100644
--- a/test/CodeGen/X86/call-push.ll
+++ b/test/CodeGen/X86/call-push.ll
@@ -4,7 +4,7 @@
         %struct.range_t = type { float, float, i32, i32, i32, [0 x i8] }
 
 define i32 @decode_byte(%struct.decode_t* %decode) nounwind {
-; CHECK: decode_byte:
+; CHECK-LABEL: decode_byte:
 ; CHECK: pushl
 ; CHECK: popl
 ; CHECK: jmp
diff --git a/test/CodeGen/X86/chain_order.ll b/test/CodeGen/X86/chain_order.ll
index 056fd27..8c1c864 100644
--- a/test/CodeGen/X86/chain_order.ll
+++ b/test/CodeGen/X86/chain_order.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mcpu=corei7-avx -mtriple=x86_64-linux | FileCheck %s
 
-;CHECK: cftx020
+;CHECK-LABEL: cftx020:
 ;CHECK: vmovsd  (%rdi), %xmm{{.*}}
 ;CHECK: vmovsd  16(%rdi), %xmm{{.*}}
 ;CHECK: vmovhpd  8(%rdi), %xmm{{.*}}
diff --git a/test/CodeGen/X86/change-compare-stride-1.ll b/test/CodeGen/X86/change-compare-stride-1.ll
index 1c5c113..b45b404 100644
--- a/test/CodeGen/X86/change-compare-stride-1.ll
+++ b/test/CodeGen/X86/change-compare-stride-1.ll
@@ -8,7 +8,7 @@
 ; XFAIL: *
 
 define void @borf(i8* nocapture %in, i8* nocapture %out) nounwind {
-; CHECK: borf:
+; CHECK-LABEL: borf:
 ; CHECK-NOT: inc
 ; CHECK-NOT: leal 1(
 ; CHECK-NOT: leal -1(
diff --git a/test/CodeGen/X86/change-compare-stride-trickiness-0.ll b/test/CodeGen/X86/change-compare-stride-trickiness-0.ll
index 1f7f6ec..be9e709 100644
--- a/test/CodeGen/X86/change-compare-stride-trickiness-0.ll
+++ b/test/CodeGen/X86/change-compare-stride-trickiness-0.ll
@@ -5,7 +5,7 @@ target triple = "x86_64-apple-darwin9"
 ; The comparison happens before the relevant use, but it can still be rewritten
 ; to compare with zero.
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: align
 ; CHECK: incl  %eax
 ; CHECK-NEXT: decl  %ecx
diff --git a/test/CodeGen/X86/change-compare-stride-trickiness-1.ll b/test/CodeGen/X86/change-compare-stride-trickiness-1.ll
index a3933e2..63733ab 100644
--- a/test/CodeGen/X86/change-compare-stride-trickiness-1.ll
+++ b/test/CodeGen/X86/change-compare-stride-trickiness-1.ll
@@ -7,7 +7,7 @@
 ; could be made simpler.
 
 define void @foo() nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NOT: ret
 ; CHECK: cmpl $10
 ; CHECK: ret
diff --git a/test/CodeGen/X86/clz.ll b/test/CodeGen/X86/clz.ll
index 763079f..6a6f525 100644
--- a/test/CodeGen/X86/clz.ll
+++ b/test/CodeGen/X86/clz.ll
@@ -12,7 +12,7 @@ declare i64 @llvm.ctlz.i64(i64, i1)
 define i8 @cttz_i8(i8 %x)  {
   %tmp = call i8 @llvm.cttz.i8( i8 %x, i1 true )
   ret i8 %tmp
-; CHECK: cttz_i8:
+; CHECK-LABEL: cttz_i8:
 ; CHECK: bsfl
 ; CHECK-NOT: cmov
 ; CHECK: ret
@@ -21,7 +21,7 @@ define i8 @cttz_i8(i8 %x)  {
 define i16 @cttz_i16(i16 %x)  {
   %tmp = call i16 @llvm.cttz.i16( i16 %x, i1 true )
   ret i16 %tmp
-; CHECK: cttz_i16:
+; CHECK-LABEL: cttz_i16:
 ; CHECK: bsfw
 ; CHECK-NOT: cmov
 ; CHECK: ret
@@ -30,7 +30,7 @@ define i16 @cttz_i16(i16 %x)  {
 define i32 @cttz_i32(i32 %x)  {
   %tmp = call i32 @llvm.cttz.i32( i32 %x, i1 true )
   ret i32 %tmp
-; CHECK: cttz_i32:
+; CHECK-LABEL: cttz_i32:
 ; CHECK: bsfl
 ; CHECK-NOT: cmov
 ; CHECK: ret
@@ -39,7 +39,7 @@ define i32 @cttz_i32(i32 %x)  {
 define i64 @cttz_i64(i64 %x)  {
   %tmp = call i64 @llvm.cttz.i64( i64 %x, i1 true )
   ret i64 %tmp
-; CHECK: cttz_i64:
+; CHECK-LABEL: cttz_i64:
 ; CHECK: bsfq
 ; CHECK-NOT: cmov
 ; CHECK: ret
@@ -49,7 +49,7 @@ define i8 @ctlz_i8(i8 %x) {
 entry:
   %tmp2 = call i8 @llvm.ctlz.i8( i8 %x, i1 true )
   ret i8 %tmp2
-; CHECK: ctlz_i8:
+; CHECK-LABEL: ctlz_i8:
 ; CHECK: bsrl
 ; CHECK-NOT: cmov
 ; CHECK: xorl $7,
@@ -60,7 +60,7 @@ define i16 @ctlz_i16(i16 %x) {
 entry:
   %tmp2 = call i16 @llvm.ctlz.i16( i16 %x, i1 true )
   ret i16 %tmp2
-; CHECK: ctlz_i16:
+; CHECK-LABEL: ctlz_i16:
 ; CHECK: bsrw
 ; CHECK-NOT: cmov
 ; CHECK: xorl $15,
@@ -70,7 +70,7 @@ entry:
 define i32 @ctlz_i32(i32 %x) {
   %tmp = call i32 @llvm.ctlz.i32( i32 %x, i1 true )
   ret i32 %tmp
-; CHECK: ctlz_i32:
+; CHECK-LABEL: ctlz_i32:
 ; CHECK: bsrl
 ; CHECK-NOT: cmov
 ; CHECK: xorl $31,
@@ -80,7 +80,7 @@ define i32 @ctlz_i32(i32 %x) {
 define i64 @ctlz_i64(i64 %x) {
   %tmp = call i64 @llvm.ctlz.i64( i64 %x, i1 true )
   ret i64 %tmp
-; CHECK: ctlz_i64:
+; CHECK-LABEL: ctlz_i64:
 ; CHECK: bsrq
 ; CHECK-NOT: cmov
 ; CHECK: xorq $63,
@@ -90,7 +90,7 @@ define i64 @ctlz_i64(i64 %x) {
 define i32 @ctlz_i32_cmov(i32 %n) {
 entry:
 ; Generate a cmov to handle zero inputs when necessary.
-; CHECK: ctlz_i32_cmov:
+; CHECK-LABEL: ctlz_i32_cmov:
 ; CHECK: bsrl
 ; CHECK: cmov
 ; CHECK: xorl $31,
@@ -104,7 +104,7 @@ entry:
 ; Don't generate the cmovne when the source is known non-zero (and bsr would
 ; not set ZF).
 ; rdar://9490949
-; CHECK: ctlz_i32_fold_cmov:
+; CHECK-LABEL: ctlz_i32_fold_cmov:
 ; CHECK: bsrl
 ; CHECK-NOT: cmov
 ; CHECK: xorl $31,
@@ -118,7 +118,7 @@ define i32 @ctlz_bsr(i32 %n) {
 entry:
 ; Don't generate any xors when a 'ctlz' intrinsic is actually used to compute
 ; the most significant bit, which is what 'bsr' does natively.
-; CHECK: ctlz_bsr:
+; CHECK-LABEL: ctlz_bsr:
 ; CHECK: bsrl
 ; CHECK-NOT: xorl
 ; CHECK: ret
@@ -131,7 +131,7 @@ define i32 @ctlz_bsr_cmov(i32 %n) {
 entry:
 ; Same as ctlz_bsr, but ensure this happens even when there is a potential
 ; zero.
-; CHECK: ctlz_bsr_cmov:
+; CHECK-LABEL: ctlz_bsr_cmov:
 ; CHECK: bsrl
 ; CHECK-NOT: xorl
 ; CHECK: ret
diff --git a/test/CodeGen/X86/cmov-fp.ll b/test/CodeGen/X86/cmov-fp.ll
index ca91f9e..768af94 100644
--- a/test/CodeGen/X86/cmov-fp.ll
+++ b/test/CodeGen/X86/cmov-fp.ll
@@ -9,16 +9,16 @@ define double @test1(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test1:
+; SSE-LABEL: test1:
 ; SSE: movsd
 
-; NOSSE2: test1:
+; NOSSE2-LABEL: test1:
 ; NOSSE2: fcmovnbe
 
-; NOSSE1: test1:
+; NOSSE1-LABEL: test1:
 ; NOSSE1: fcmovnbe
 
-; NOCMOV: test1:
+; NOCMOV-LABEL: test1:
 ; NOCMOV: fstp
 
 }
@@ -28,16 +28,16 @@ define double @test2(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test2:
+; SSE-LABEL: test2:
 ; SSE: movsd
 
-; NOSSE2: test2:
+; NOSSE2-LABEL: test2:
 ; NOSSE2: fcmovnb
 
-; NOSSE1: test2:
+; NOSSE1-LABEL: test2:
 ; NOSSE1: fcmovnb
 
-; NOCMOV: test2:
+; NOCMOV-LABEL: test2:
 ; NOCMOV: fstp
 }
 
@@ -46,16 +46,16 @@ define double @test3(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test3:
+; SSE-LABEL: test3:
 ; SSE: movsd
 
-; NOSSE2: test3:
+; NOSSE2-LABEL: test3:
 ; NOSSE2: fcmovb
 
-; NOSSE1: test3:
+; NOSSE1-LABEL: test3:
 ; NOSSE1: fcmovb
 
-; NOCMOV: test3:
+; NOCMOV-LABEL: test3:
 ; NOCMOV: fstp
 }
 
@@ -64,16 +64,16 @@ define double @test4(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test4:
+; SSE-LABEL: test4:
 ; SSE: movsd
 
-; NOSSE2: test4:
+; NOSSE2-LABEL: test4:
 ; NOSSE2: fcmovbe
 
-; NOSSE1: test4:
+; NOSSE1-LABEL: test4:
 ; NOSSE1: fcmovbe
 
-; NOCMOV: test4:
+; NOCMOV-LABEL: test4:
 ; NOCMOV: fstp
 }
 
@@ -82,16 +82,16 @@ define double @test5(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test5:
+; SSE-LABEL: test5:
 ; SSE: movsd
 
-; NOSSE2: test5:
+; NOSSE2-LABEL: test5:
 ; NOSSE2: fstp
 
-; NOSSE1: test5:
+; NOSSE1-LABEL: test5:
 ; NOSSE1: fstp
 
-; NOCMOV: test5:
+; NOCMOV-LABEL: test5:
 ; NOCMOV: fstp
 }
 
@@ -100,16 +100,16 @@ define double @test6(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test6:
+; SSE-LABEL: test6:
 ; SSE: movsd
 
-; NOSSE2: test6:
+; NOSSE2-LABEL: test6:
 ; NOSSE2: fstp
 
-; NOSSE1: test6:
+; NOSSE1-LABEL: test6:
 ; NOSSE1: fstp
 
-; NOCMOV: test6:
+; NOCMOV-LABEL: test6:
 ; NOCMOV: fstp
 }
 
@@ -118,16 +118,16 @@ define double @test7(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test7:
+; SSE-LABEL: test7:
 ; SSE: movsd
 
-; NOSSE2: test7:
+; NOSSE2-LABEL: test7:
 ; NOSSE2: fstp
 
-; NOSSE1: test7:
+; NOSSE1-LABEL: test7:
 ; NOSSE1: fstp
 
-; NOCMOV: test7:
+; NOCMOV-LABEL: test7:
 ; NOCMOV: fstp
 }
 
@@ -136,16 +136,16 @@ define double @test8(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test8:
+; SSE-LABEL: test8:
 ; SSE: movsd
 
-; NOSSE2: test8:
+; NOSSE2-LABEL: test8:
 ; NOSSE2: fstp
 
-; NOSSE1: test8:
+; NOSSE1-LABEL: test8:
 ; NOSSE1: fstp
 
-; NOCMOV: test8:
+; NOCMOV-LABEL: test8:
 ; NOCMOV: fstp
 }
 
@@ -154,16 +154,16 @@ define float @test9(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test9:
+; SSE-LABEL: test9:
 ; SSE: movss
 
-; NOSSE2: test9:
+; NOSSE2-LABEL: test9:
 ; NOSSE2: movss
 
-; NOSSE1: test9:
+; NOSSE1-LABEL: test9:
 ; NOSSE1: fcmovnbe
 
-; NOCMOV: test9:
+; NOCMOV-LABEL: test9:
 ; NOCMOV: fstp
 }
 
@@ -172,16 +172,16 @@ define float @test10(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test10:
+; SSE-LABEL: test10:
 ; SSE: movss
 
-; NOSSE2: test10:
+; NOSSE2-LABEL: test10:
 ; NOSSE2: movss
 
-; NOSSE1: test10:
+; NOSSE1-LABEL: test10:
 ; NOSSE1: fcmovnb
 
-; NOCMOV: test10:
+; NOCMOV-LABEL: test10:
 ; NOCMOV: fstp
 }
 
@@ -190,16 +190,16 @@ define float @test11(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test11:
+; SSE-LABEL: test11:
 ; SSE: movss
 
-; NOSSE2: test11:
+; NOSSE2-LABEL: test11:
 ; NOSSE2: movss
 
-; NOSSE1: test11:
+; NOSSE1-LABEL: test11:
 ; NOSSE1: fcmovb
 
-; NOCMOV: test11:
+; NOCMOV-LABEL: test11:
 ; NOCMOV: fstp
 }
 
@@ -208,16 +208,16 @@ define float @test12(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test12:
+; SSE-LABEL: test12:
 ; SSE: movss
 
-; NOSSE2: test12:
+; NOSSE2-LABEL: test12:
 ; NOSSE2: movss
 
-; NOSSE1: test12:
+; NOSSE1-LABEL: test12:
 ; NOSSE1: fcmovbe
 
-; NOCMOV: test12:
+; NOCMOV-LABEL: test12:
 ; NOCMOV: fstp
 }
 
@@ -226,16 +226,16 @@ define float @test13(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test13:
+; SSE-LABEL: test13:
 ; SSE: movss
 
-; NOSSE2: test13:
+; NOSSE2-LABEL: test13:
 ; NOSSE2: movss
 
-; NOSSE1: test13:
+; NOSSE1-LABEL: test13:
 ; NOSSE1: fstp
 
-; NOCMOV: test13:
+; NOCMOV-LABEL: test13:
 ; NOCMOV: fstp
 }
 
@@ -244,16 +244,16 @@ define float @test14(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test14:
+; SSE-LABEL: test14:
 ; SSE: movss
 
-; NOSSE2: test14:
+; NOSSE2-LABEL: test14:
 ; NOSSE2: movss
 
-; NOSSE1: test14:
+; NOSSE1-LABEL: test14:
 ; NOSSE1: fstp
 
-; NOCMOV: test14:
+; NOCMOV-LABEL: test14:
 ; NOCMOV: fstp
 }
 
@@ -262,16 +262,16 @@ define float @test15(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test15:
+; SSE-LABEL: test15:
 ; SSE: movss
 
-; NOSSE2: test15:
+; NOSSE2-LABEL: test15:
 ; NOSSE2: movss
 
-; NOSSE1: test15:
+; NOSSE1-LABEL: test15:
 ; NOSSE1: fstp
 
-; NOCMOV: test15:
+; NOCMOV-LABEL: test15:
 ; NOCMOV: fstp
 }
 
@@ -280,16 +280,16 @@ define float @test16(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test16:
+; SSE-LABEL: test16:
 ; SSE: movss
 
-; NOSSE2: test16:
+; NOSSE2-LABEL: test16:
 ; NOSSE2: movss
 
-; NOSSE1: test16:
+; NOSSE1-LABEL: test16:
 ; NOSSE1: fstp
 
-; NOCMOV: test16:
+; NOCMOV-LABEL: test16:
 ; NOCMOV: fstp
 }
 
@@ -298,16 +298,16 @@ define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 
-; SSE: test17:
+; SSE-LABEL: test17:
 ; SSE: fcmovnbe
 
-; NOSSE2: test17:
+; NOSSE2-LABEL: test17:
 ; NOSSE2: fcmovnbe
 
-; NOSSE1: test17:
+; NOSSE1-LABEL: test17:
 ; NOSSE1: fcmovnbe
 
-; NOCMOV: test17:
+; NOCMOV-LABEL: test17:
 ; NOCMOV: fstp
 }
 
@@ -316,16 +316,16 @@ define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 
-; SSE: test18:
+; SSE-LABEL: test18:
 ; SSE: fcmovnb
 
-; NOSSE2: test18:
+; NOSSE2-LABEL: test18:
 ; NOSSE2: fcmovnb
 
-; NOSSE1: test18:
+; NOSSE1-LABEL: test18:
 ; NOSSE1: fcmovnb
 
-; NOCMOV: test18:
+; NOCMOV-LABEL: test18:
 ; NOCMOV: fstp
 }
 
@@ -334,16 +334,16 @@ define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 
-; SSE: test19:
+; SSE-LABEL: test19:
 ; SSE: fcmovb
 
-; NOSSE2: test19:
+; NOSSE2-LABEL: test19:
 ; NOSSE2: fcmovb
 
-; NOSSE1: test19:
+; NOSSE1-LABEL: test19:
 ; NOSSE1: fcmovb
 
-; NOCMOV: test19:
+; NOCMOV-LABEL: test19:
 ; NOCMOV: fstp
 }
 
@@ -352,16 +352,16 @@ define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 
-; SSE: test20:
+; SSE-LABEL: test20:
 ; SSE: fcmovbe
 
-; NOSSE2: test20:
+; NOSSE2-LABEL: test20:
 ; NOSSE2: fcmovbe
 
-; NOSSE1: test20:
+; NOSSE1-LABEL: test20:
 ; NOSSE1: fcmovbe
 
-; NOCMOV: test20:
+; NOCMOV-LABEL: test20:
 ; NOCMOV: fstp
 }
 
@@ -371,19 +371,19 @@ define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   ret x86_fp80 %sel
 
 ; We don't emit a branch for fp80, why?
-; SSE: test21:
+; SSE-LABEL: test21:
 ; SSE: testb
 ; SSE: fcmovne
 
-; NOSSE2: test21:
+; NOSSE2-LABEL: test21:
 ; NOSSE2: testb
 ; NOSSE2: fcmovne
 
-; NOSSE1: test21:
+; NOSSE1-LABEL: test21:
 ; NOSSE1: testb
 ; NOSSE1: fcmovne
 
-; NOCMOV: test21:
+; NOCMOV-LABEL: test21:
 ; NOCMOV: fstp
 }
 
@@ -392,19 +392,19 @@ define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 
-; SSE: test22:
+; SSE-LABEL: test22:
 ; SSE: testb
 ; SSE: fcmovne
 
-; NOSSE2: test22:
+; NOSSE2-LABEL: test22:
 ; NOSSE2: testb
 ; NOSSE2: fcmovne
 
-; NOSSE1: test22:
+; NOSSE1-LABEL: test22:
 ; NOSSE1: testb
 ; NOSSE1: fcmovne
 
-; NOCMOV: test22:
+; NOCMOV-LABEL: test22:
 ; NOCMOV: fstp
 }
 
@@ -413,19 +413,19 @@ define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 
-; SSE: test23:
+; SSE-LABEL: test23:
 ; SSE: testb
 ; SSE: fcmovne
 
-; NOSSE2: test23:
+; NOSSE2-LABEL: test23:
 ; NOSSE2: testb
 ; NOSSE2: fcmovne
 
-; NOSSE1: test23:
+; NOSSE1-LABEL: test23:
 ; NOSSE1: testb
 ; NOSSE1: fcmovne
 
-; NOCMOV: test23:
+; NOCMOV-LABEL: test23:
 ; NOCMOV: fstp
 }
 
@@ -434,18 +434,18 @@ define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 
-; SSE: test24:
+; SSE-LABEL: test24:
 ; SSE: testb
 ; SSE: fcmovne
 
-; NOSSE2: test24:
+; NOSSE2-LABEL: test24:
 ; NOSSE2: testb
 ; NOSSE2: fcmovne
 
-; NOSSE1: test24:
+; NOSSE1-LABEL: test24:
 ; NOSSE1: testb
 ; NOSSE1: fcmovne
 
-; NOCMOV: test24:
+; NOCMOV-LABEL: test24:
 ; NOCMOV: fstp
 }
diff --git a/test/CodeGen/X86/cmov-into-branch.ll b/test/CodeGen/X86/cmov-into-branch.ll
index 780746a..cad8dd3 100644
--- a/test/CodeGen/X86/cmov-into-branch.ll
+++ b/test/CodeGen/X86/cmov-into-branch.ll
@@ -6,7 +6,7 @@ define i32 @test1(double %a, double* nocapture %b, i32 %x, i32 %y)  {
   %cmp = fcmp olt double %load, %a
   %cond = select i1 %cmp, i32 %x, i32 %y
   ret i32 %cond
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: ucomisd
 ; CHECK-NOT: cmov
 ; CHECK: j
@@ -18,7 +18,7 @@ define i32 @test2(double %a, double %b, i32 %x, i32 %y)  {
   %cmp = fcmp ogt double %a, %b
   %cond = select i1 %cmp, i32 %x, i32 %y
   ret i32 %cond
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: ucomisd
 ; CHECK: cmov
 }
@@ -29,7 +29,7 @@ define i32 @test3(i32 %a, i32* nocapture %b, i32 %x)  {
   %cmp = icmp ult i32 %load, %a
   %cond = select i1 %cmp, i32 %a, i32 %x
   ret i32 %cond
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: cmpl
 ; CHECK-NOT: cmov
 ; CHECK: j
@@ -43,7 +43,7 @@ define i32 @test4(i32 %a, i32* nocapture %b, i32 %x, i32 %y)  {
   %cond = select i1 %cmp, i32 %x, i32 %y
   %add = add i32 %cond, %load
   ret i32 %add
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: cmpl
 ; CHECK: cmov
 }
@@ -56,7 +56,7 @@ define i32 @test5(i32 %a, i32* nocapture %b, i32 %x, i32 %y) {
   %cond = select i1 %cmp1, i32 %a, i32 %y
   %cond5 = select i1 %cmp, i32 %cond, i32 %x
   ret i32 %cond5
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: cmpl
 ; CHECK: cmov
 ; CHECK: cmov
diff --git a/test/CodeGen/X86/cmov.ll b/test/CodeGen/X86/cmov.ll
index ed25c82..92c0445 100644
--- a/test/CodeGen/X86/cmov.ll
+++ b/test/CodeGen/X86/cmov.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 define i32 @test1(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: movl	$12, %eax
 ; CHECK-NEXT: btl
 ; CHECK-NEXT: cmovael	(%rcx), %eax
@@ -18,7 +18,7 @@ entry:
 }
 define i32 @test2(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
 entry:
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movl	$12, %eax
 ; CHECK-NEXT: btl
 ; CHECK-NEXT: cmovbl	(%rcx), %eax
@@ -40,7 +40,7 @@ entry:
 declare void @bar(i64) nounwind
 
 define void @test3(i64 %a, i64 %b, i1 %p) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK:      cmovnel %edi, %esi
 ; CHECK-NEXT: movl    %esi, %edi
 
@@ -87,7 +87,7 @@ bb.i.i.i:                                         ; preds = %entry
   %4 = load volatile i8* @g_100, align 1          ; <i8> [#uses=0]
   br label %func_4.exit.i
 
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: g_100
 ; CHECK: testb
 ; CHECK-NOT: xor
@@ -119,7 +119,7 @@ declare i32 @printf(i8* nocapture, ...) nounwind
 ; rdar://6668608
 define i32 @test5(i32* nocapture %P) nounwind readonly {
 entry:
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: 	setg	%al
 ; CHECK:	movzbl	%al, %eax
 ; CHECK:	orl	$-2, %eax
@@ -133,7 +133,7 @@ entry:
 
 define i32 @test6(i32* nocapture %P) nounwind readonly {
 entry:
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: 	setl	%al
 ; CHECK:	movzbl	%al, %eax
 ; CHECK:	leal	4(%rax,%rax,8), %eax
@@ -148,7 +148,7 @@ entry:
 ; Don't try to use a 16-bit conditional move to do an 8-bit select,
 ; because it isn't worth it. Just use a branch instead.
 define i8 @test7(i1 inreg %c, i8 inreg %a, i8 inreg %b) nounwind {
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK:     testb	$1, %dil
 ; CHECK-NEXT:     jne	LBB
 
diff --git a/test/CodeGen/X86/cmp.ll b/test/CodeGen/X86/cmp.ll
index 5f5ba21..551d9bc 100644
--- a/test/CodeGen/X86/cmp.ll
+++ b/test/CodeGen/X86/cmp.ll
@@ -10,7 +10,7 @@ cond_true:		; preds = %0
 
 ReturnBlock:		; preds = %0
 	ret i32 0
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: cmpl	$0, (%rsi)
 }
 
@@ -25,7 +25,7 @@ cond_true:		; preds = %0
 
 ReturnBlock:		; preds = %0
 	ret i32 0
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movl	(%rsi), %eax
 ; CHECK: shll	$3, %eax
 ; CHECK: testl	%eax, %eax
@@ -35,7 +35,7 @@ define i64 @test3(i64 %x) nounwind {
   %t = icmp eq i64 %x, 0
   %r = zext i1 %t to i64
   ret i64 %r
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: 	testq	%rdi, %rdi
 ; CHECK: 	sete	%al
 ; CHECK: 	movzbl	%al, %eax
@@ -46,7 +46,7 @@ define i64 @test4(i64 %x) nounwind {
   %t = icmp slt i64 %x, 1
   %r = zext i1 %t to i64
   ret i64 %r
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: 	testq	%rdi, %rdi
 ; CHECK: 	setle	%al
 ; CHECK: 	movzbl	%al, %eax
@@ -67,7 +67,7 @@ define i32 @test5(double %A) nounwind  {
 
  bb12:; preds = %entry
  ret i32 32
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: ucomisd	LCPI4_0(%rip), %xmm0
 ; CHECK: ucomisd	LCPI4_1(%rip), %xmm0
 }
@@ -85,7 +85,7 @@ T:
   
 F:
   ret i32 0
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: cmpq	$0, -8(%rsp)
 ; CHECK: encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
 }
@@ -93,7 +93,7 @@ F:
 ; rdar://11866926
 define i32 @test7(i64 %res) nounwind {
 entry:
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK-NOT: movabsq
 ; CHECK: shrq $32, %rdi
 ; CHECK: sete
@@ -104,7 +104,7 @@ entry:
 
 define i32 @test8(i64 %res) nounwind {
 entry:
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK-NOT: movabsq
 ; CHECK: shrq $32, %rdi
 ; CHECK: cmpq $3, %rdi
@@ -115,7 +115,7 @@ entry:
 
 define i32 @test9(i64 %res) nounwind {
 entry:
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK-NOT: movabsq
 ; CHECK: shrq $33, %rdi
 ; CHECK: sete
@@ -126,7 +126,7 @@ entry:
 
 define i32 @test10(i64 %res) nounwind {
 entry:
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK-NOT: movabsq
 ; CHECK: shrq $32, %rdi
 ; CHECK: setne
@@ -138,7 +138,7 @@ entry:
 ; rdar://9758774
 define i32 @test11(i64 %l) nounwind {
 entry:
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK-NOT: movabsq
 ; CHECK-NOT: andq
 ; CHECK: shrq $47, %rdi
@@ -150,7 +150,7 @@ entry:
 }
 
 define i32 @test12() uwtable ssp {
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK: testb
   %1 = call zeroext i1 @test12b()
   br i1 %1, label %2, label %3
diff --git a/test/CodeGen/X86/coalescer-commute1.ll b/test/CodeGen/X86/coalescer-commute1.ll
index d9e0778..cbcb890 100644
--- a/test/CodeGen/X86/coalescer-commute1.ll
+++ b/test/CodeGen/X86/coalescer-commute1.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps
+; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx -mattr=+sse2 | not grep movaps
 ; PR1877
 
 @NNTOT = weak global i32 0		; <i32*> [#uses=1]
diff --git a/test/CodeGen/X86/code_placement_align_all.ll b/test/CodeGen/X86/code_placement_align_all.ll
index 1e5e8f7..53df906 100644
--- a/test/CodeGen/X86/code_placement_align_all.ll
+++ b/test/CodeGen/X86/code_placement_align_all.ll
@@ -1,6 +1,6 @@
 ; RUN: llc  -mcpu=corei7 -mtriple=x86_64-linux -align-all-blocks=16 < %s | FileCheck %s
 
-;CHECK: foo
+;CHECK-LABEL: foo:
 ;CHECK: .align  65536, 0x90
 ;CHECK: .align  65536, 0x90
 ;CHECK: .align  65536, 0x90
diff --git a/test/CodeGen/X86/codegen-prepare.ll b/test/CodeGen/X86/codegen-prepare.ll
index e8ee070..316accf 100644
--- a/test/CodeGen/X86/codegen-prepare.ll
+++ b/test/CodeGen/X86/codegen-prepare.ll
@@ -38,7 +38,7 @@ if.end:                                           ; preds = %if.then, %if.else,
   ret void
 }
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: movss 12([[THIS:%[a-zA-Z0-9]+]]), [[REGISTER:%[a-zA-Z0-9]+]]
 ; CHECK-NEXT: movss [[REGISTER]], 60([[THIS]])
 
diff --git a/test/CodeGen/X86/codemodel.ll b/test/CodeGen/X86/codemodel.ll
index b6ca1ce..3aebc13 100644
--- a/test/CodeGen/X86/codemodel.ll
+++ b/test/CodeGen/X86/codemodel.ll
@@ -7,9 +7,9 @@ target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @foo() nounwind readonly {
 entry:
-; CHECK-SMALL:  foo:
+; CHECK-SMALL-LABEL:  foo:
 ; CHECK-SMALL:   movl data(%rip), %eax
-; CHECK-KERNEL: foo:
+; CHECK-KERNEL-LABEL: foo:
 ; CHECK-KERNEL:  movl data, %eax
 	%0 = load i32* getelementptr ([0 x i32]* @data, i64 0, i64 0), align 4		; <i32> [#uses=1]
 	ret i32 %0
@@ -17,9 +17,9 @@ entry:
 
 define i32 @foo2() nounwind readonly {
 entry:
-; CHECK-SMALL:  foo2:
+; CHECK-SMALL-LABEL:  foo2:
 ; CHECK-SMALL:   movl data+40(%rip), %eax
-; CHECK-KERNEL: foo2:
+; CHECK-KERNEL-LABEL: foo2:
 ; CHECK-KERNEL:  movl data+40, %eax
 	%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 10), align 4		; <i32> [#uses=1]
 	ret i32 %0
@@ -27,9 +27,9 @@ entry:
 
 define i32 @foo3() nounwind readonly {
 entry:
-; CHECK-SMALL:  foo3:
+; CHECK-SMALL-LABEL:  foo3:
 ; CHECK-SMALL:   movl data-40(%rip), %eax
-; CHECK-KERNEL: foo3:
+; CHECK-KERNEL-LABEL: foo3:
 ; CHECK-KERNEL:  movq $-40, %rax
 	%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 -10), align 4		; <i32> [#uses=1]
 	ret i32 %0
@@ -38,10 +38,10 @@ entry:
 define i32 @foo4() nounwind readonly {
 entry:
 ; FIXME: We really can use movabsl here!
-; CHECK-SMALL:  foo4:
+; CHECK-SMALL-LABEL:  foo4:
 ; CHECK-SMALL:   movl $16777216, %eax
 ; CHECK-SMALL:   movl data(%rax), %eax
-; CHECK-KERNEL: foo4:
+; CHECK-KERNEL-LABEL: foo4:
 ; CHECK-KERNEL:  movl data+16777216, %eax
 	%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 4194304), align 4		; <i32> [#uses=1]
 	ret i32 %0
@@ -49,18 +49,18 @@ entry:
 
 define i32 @foo1() nounwind readonly {
 entry:
-; CHECK-SMALL:  foo1:
+; CHECK-SMALL-LABEL:  foo1:
 ; CHECK-SMALL:   movl data+16777212(%rip), %eax
-; CHECK-KERNEL: foo1:
+; CHECK-KERNEL-LABEL: foo1:
 ; CHECK-KERNEL:  movl data+16777212, %eax
         %0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 4194303), align 4            ; <i32> [#uses=1]
         ret i32 %0
 }
 define i32 @foo5() nounwind readonly {
 entry:
-; CHECK-SMALL:  foo5:
+; CHECK-SMALL-LABEL:  foo5:
 ; CHECK-SMALL:   movl data-16777216(%rip), %eax
-; CHECK-KERNEL: foo5:
+; CHECK-KERNEL-LABEL: foo5:
 ; CHECK-KERNEL:  movq $-16777216, %rax
 	%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 -4194304), align 4		; <i32> [#uses=1]
 	ret i32 %0
diff --git a/test/CodeGen/X86/commute-two-addr.ll b/test/CodeGen/X86/commute-two-addr.ll
index ef44a3d..eb44e08 100644
--- a/test/CodeGen/X86/commute-two-addr.ll
+++ b/test/CodeGen/X86/commute-two-addr.ll
@@ -2,8 +2,8 @@
 ; insertion of register-register copies.
 
 ; Make sure there are only 3 mov's for each testcase
-; RUN: llc < %s -mtriple=i686-pc-linux-gnu   | FileCheck %s -check-prefix=LINUX
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s -check-prefix=DARWIN
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu   -mcpu=corei7 | FileCheck %s -check-prefix=LINUX
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s -check-prefix=DARWIN
 
 
 @G = external global i32                ; <i32*> [#uses=2]
@@ -11,7 +11,7 @@
 declare void @ext(i32)
 
 define i32 @t1(i32 %X, i32 %Y) nounwind {
-; LINUX: t1:
+; LINUX-LABEL: t1:
 ; LINUX: movl 4(%esp), %eax
 ; LINUX: movl 8(%esp), %ecx
 ; LINUX: addl %eax, %ecx
@@ -22,7 +22,7 @@ define i32 @t1(i32 %X, i32 %Y) nounwind {
 }
 
 define i32 @t2(i32 %X, i32 %Y) nounwind {
-; LINUX: t2:
+; LINUX-LABEL: t2:
 ; LINUX: movl 4(%esp), %eax
 ; LINUX: movl 8(%esp), %ecx
 ; LINUX: xorl %eax, %ecx
@@ -37,7 +37,7 @@ define i32 @t2(i32 %X, i32 %Y) nounwind {
 
 define %0 @t3(i32 %lb, i8 zeroext %has_lb, i8 zeroext %lb_inclusive, i32 %ub, i8 zeroext %has_ub, i8 zeroext %ub_inclusive) nounwind {
 entry:
-; DARWIN: t3:
+; DARWIN-LABEL: t3:
 ; DARWIN: shll $16
 ; DARWIN: shlq $32, %rcx
 ; DARWIN-NOT: leaq
diff --git a/test/CodeGen/X86/compare-inf.ll b/test/CodeGen/X86/compare-inf.ll
index 9aa44a3..5eb0135 100644
--- a/test/CodeGen/X86/compare-inf.ll
+++ b/test/CodeGen/X86/compare-inf.ll
@@ -3,74 +3,124 @@
 ; Convert oeq and une to ole/oge/ule/uge when comparing with infinity
 ; and negative infinity, because those are more efficient on x86.
 
-; CHECK: oeq_inff:
+declare void @f() nounwind
+
+; CHECK-LABEL: oeq_inff:
 ; CHECK: ucomiss
 ; CHECK: jb
-define float @oeq_inff(float %x, float %y) nounwind readonly {
+define void @oeq_inff(float %x) nounwind {
   %t0 = fcmp oeq float %x, 0x7FF0000000000000
-  %t1 = select i1 %t0, float 1.0, float %y
-  ret float %t1
+  br i1 %t0, label %true, label %false
+
+true:
+  call void @f() nounwind
+  br label %false
+
+false:
+  ret void
 }
 
-; CHECK: oeq_inf:
+; CHECK-LABEL: oeq_inf:
 ; CHECK: ucomisd
 ; CHECK: jb
-define double @oeq_inf(double %x, double %y) nounwind readonly {
+define void @oeq_inf(double %x) nounwind {
   %t0 = fcmp oeq double %x, 0x7FF0000000000000
-  %t1 = select i1 %t0, double 1.0, double %y
-  ret double %t1
+  br i1 %t0, label %true, label %false
+
+true:
+  call void @f() nounwind
+  br label %false
+
+false:
+  ret void
 }
 
-; CHECK: une_inff:
+; CHECK-LABEL: une_inff:
 ; CHECK: ucomiss
 ; CHECK: jae
-define float @une_inff(float %x, float %y) nounwind readonly {
+define void @une_inff(float %x) nounwind {
   %t0 = fcmp une float %x, 0x7FF0000000000000
-  %t1 = select i1 %t0, float 1.0, float %y
-  ret float %t1
+  br i1 %t0, label %true, label %false
+
+true:
+  call void @f() nounwind
+  br label %false
+
+false:
+  ret void
 }
 
-; CHECK: une_inf:
+; CHECK-LABEL: une_inf:
 ; CHECK: ucomisd
 ; CHECK: jae
-define double @une_inf(double %x, double %y) nounwind readonly {
+define void @une_inf(double %x) nounwind {
   %t0 = fcmp une double %x, 0x7FF0000000000000
-  %t1 = select i1 %t0, double 1.0, double %y
-  ret double %t1
+  br i1 %t0, label %true, label %false
+
+true:
+  call void @f() nounwind
+  br label %false
+
+false:
+  ret void
 }
 
-; CHECK: oeq_neg_inff:
+; CHECK-LABEL: oeq_neg_inff:
 ; CHECK: ucomiss
 ; CHECK: jb
-define float @oeq_neg_inff(float %x, float %y) nounwind readonly {
+define void @oeq_neg_inff(float %x) nounwind {
   %t0 = fcmp oeq float %x, 0xFFF0000000000000
-  %t1 = select i1 %t0, float 1.0, float %y
-  ret float %t1
+  br i1 %t0, label %true, label %false
+
+true:
+  call void @f() nounwind
+  br label %false
+
+false:
+  ret void
 }
 
-; CHECK: oeq_neg_inf:
+; CHECK-LABEL: oeq_neg_inf:
 ; CHECK: ucomisd
 ; CHECK: jb
-define double @oeq_neg_inf(double %x, double %y) nounwind readonly {
+define void @oeq_neg_inf(double %x) nounwind {
   %t0 = fcmp oeq double %x, 0xFFF0000000000000
-  %t1 = select i1 %t0, double 1.0, double %y
-  ret double %t1
+  br i1 %t0, label %true, label %false
+
+true:
+  call void @f() nounwind
+  br label %false
+
+false:
+  ret void
 }
 
-; CHECK: une_neg_inff:
+; CHECK-LABEL: une_neg_inff:
 ; CHECK: ucomiss
 ; CHECK: jae
-define float @une_neg_inff(float %x, float %y) nounwind readonly {
+define void @une_neg_inff(float %x) nounwind {
   %t0 = fcmp une float %x, 0xFFF0000000000000
-  %t1 = select i1 %t0, float 1.0, float %y
-  ret float %t1
+  br i1 %t0, label %true, label %false
+
+true:
+  call void @f() nounwind
+  br label %false
+
+false:
+  ret void
 }
 
-; CHECK: une_neg_inf:
+; CHECK-LABEL: une_neg_inf:
 ; CHECK: ucomisd
 ; CHECK: jae
-define double @une_neg_inf(double %x, double %y) nounwind readonly {
+define void @une_neg_inf(double %x) nounwind {
   %t0 = fcmp une double %x, 0xFFF0000000000000
-  %t1 = select i1 %t0, double 1.0, double %y
-  ret double %t1
+  br i1 %t0, label %true, label %false
+
+true:
+  call void @f() nounwind
+  br label %false
+
+false:
+  ret void
 }
diff --git a/test/CodeGen/X86/compiler_used.ll b/test/CodeGen/X86/compiler_used.ll
index d38ce91..af5c86c 100644
--- a/test/CodeGen/X86/compiler_used.ll
+++ b/test/CodeGen/X86/compiler_used.ll
@@ -5,7 +5,7 @@
 @Z = internal global i8 4
 
 @llvm.used = appending global [1 x i8*] [ i8* @Z ], section "llvm.metadata"
-@llvm.compiler_used = appending global [2 x i8*] [ i8* @X, i8* bitcast (i32* @Y to i8*)], section "llvm.metadata"
+@llvm.compiler.used = appending global [2 x i8*] [ i8* @X, i8* bitcast (i32* @Y to i8*)], section "llvm.metadata"
 
 ; CHECK-NOT: .no_dead_strip
 ; CHECK: .no_dead_strip	_Z
diff --git a/test/CodeGen/X86/conditional-indecrement.ll b/test/CodeGen/X86/conditional-indecrement.ll
index a3a0c39..c3e7118 100644
--- a/test/CodeGen/X86/conditional-indecrement.ll
+++ b/test/CodeGen/X86/conditional-indecrement.ll
@@ -5,7 +5,7 @@ define i32 @test1(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %not.cmp to i32
   %retval.0 = add i32 %inc, %b
   ret i32 %retval.0
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: cmpl $1
 ; CHECK: sbbl $-1
 ; CHECK: ret
@@ -16,7 +16,7 @@ define i32 @test2(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %cmp to i32
   %retval.0 = add i32 %inc, %b
   ret i32 %retval.0
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: cmpl $1
 ; CHECK: adcl $0
 ; CHECK: ret
@@ -27,7 +27,7 @@ define i32 @test3(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %cmp to i32
   %retval.0 = add i32 %inc, %b
   ret i32 %retval.0
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: cmpl $1
 ; CHECK: adcl $0
 ; CHECK: ret
@@ -38,7 +38,7 @@ define i32 @test4(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %not.cmp to i32
   %retval.0 = add i32 %inc, %b
   ret i32 %retval.0
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: cmpl $1
 ; CHECK: sbbl $-1
 ; CHECK: ret
@@ -49,7 +49,7 @@ define i32 @test5(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %not.cmp to i32
   %retval.0 = sub i32 %b, %inc
   ret i32 %retval.0
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: cmpl $1
 ; CHECK: adcl $-1
 ; CHECK: ret
@@ -60,7 +60,7 @@ define i32 @test6(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %cmp to i32
   %retval.0 = sub i32 %b, %inc
   ret i32 %retval.0
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: cmpl $1
 ; CHECK: sbbl $0
 ; CHECK: ret
@@ -71,7 +71,7 @@ define i32 @test7(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %cmp to i32
   %retval.0 = sub i32 %b, %inc
   ret i32 %retval.0
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: cmpl $1
 ; CHECK: sbbl $0
 ; CHECK: ret
@@ -82,7 +82,7 @@ define i32 @test8(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %not.cmp to i32
   %retval.0 = sub i32 %b, %inc
   ret i32 %retval.0
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: cmpl $1
 ; CHECK: adcl $-1
 ; CHECK: ret
diff --git a/test/CodeGen/X86/crash-nosse.ll b/test/CodeGen/X86/crash-nosse.ll
index 1cec25b..7a15a47 100644
--- a/test/CodeGen/X86/crash-nosse.ll
+++ b/test/CodeGen/X86/crash-nosse.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mattr=-sse2,-sse41 -verify-machineinstrs
+; RUN: llc < %s -mcpu=corei7 -mattr=-sse2,-sse41 -verify-machineinstrs
 target triple = "x86_64-unknown-linux-gnu"
 
 ; PR10503
diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll
index 852b642..b0a0e24 100644
--- a/test/CodeGen/X86/crash.ll
+++ b/test/CodeGen/X86/crash.ll
@@ -1,5 +1,6 @@
-; RUN: llc -march=x86 < %s -verify-machineinstrs
-; RUN: llc -march=x86-64 < %s -verify-machineinstrs
+; REQUIRES: asserts
+; RUN: llc -march=x86 < %s -verify-machineinstrs -precompute-phys-liveness
+; RUN: llc -march=x86-64 < %s -verify-machineinstrs -precompute-phys-liveness
 
 ; PR6497
 
@@ -107,8 +108,8 @@ do.body92:                                        ; preds = %if.then66
   ret void
 }
 
-!0 = metadata !{i32 633550}                       
-!1 = metadata !{i32 634261}                       
+!0 = metadata !{i32 633550}
+!1 = metadata !{i32 634261}
 
 
 ; Crash during XOR optimization.
diff --git a/test/CodeGen/X86/critical-edge-split-2.ll b/test/CodeGen/X86/critical-edge-split-2.ll
index 70301cd..44205d6 100644
--- a/test/CodeGen/X86/critical-edge-split-2.ll
+++ b/test/CodeGen/X86/critical-edge-split-2.ll
@@ -22,7 +22,7 @@ cond.end.i:                                       ; preds = %entry
   ret i16 %call1
 }
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: testb %dil, %dil
 ; CHECK: jne LBB0_2
 ; CHECK: divl
diff --git a/test/CodeGen/X86/ctpop-combine.ll b/test/CodeGen/X86/ctpop-combine.ll
index 0a3dfca..786f7f9 100644
--- a/test/CodeGen/X86/ctpop-combine.ll
+++ b/test/CodeGen/X86/ctpop-combine.ll
@@ -8,7 +8,7 @@ define i32 @test1(i64 %x) nounwind readnone {
   %cmp = icmp ugt i32 %cast, 1
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: leaq -1([[A0:%rdi|%rcx]])
 ; CHECK-NEXT: testq
 ; CHECK-NEXT: setne
@@ -21,7 +21,7 @@ define i32 @test2(i64 %x) nounwind readnone {
   %cmp = icmp ult i64 %count, 2
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: leaq -1([[A0]])
 ; CHECK-NEXT: testq
 ; CHECK-NEXT: sete
@@ -34,7 +34,7 @@ define i32 @test3(i64 %x) nounwind readnone {
   %cmp = icmp ult i6 %cast, 2
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: cmpb $2
 ; CHECK: ret
 }
diff --git a/test/CodeGen/X86/dag-rauw-cse.ll b/test/CodeGen/X86/dag-rauw-cse.ll
index eca8c86..12a2e62 100644
--- a/test/CodeGen/X86/dag-rauw-cse.ll
+++ b/test/CodeGen/X86/dag-rauw-cse.ll
@@ -2,7 +2,7 @@
 ; PR3018
 
 define i32 @test(i32 %A) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: ret
 ; CHECK: orl $1
 ; CHECK: ret
diff --git a/test/CodeGen/X86/dagcombine-buildvector.ll b/test/CodeGen/X86/dagcombine-buildvector.ll
index dae91d5..cf631c3 100644
--- a/test/CodeGen/X86/dagcombine-buildvector.ll
+++ b/test/CodeGen/X86/dagcombine-buildvector.ll
@@ -3,7 +3,7 @@
 ; Shows a dag combine bug that will generate an illegal build vector
 ; with v2i64 build_vector i32, i32.
 
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: unpcklpd
 ; CHECK: movapd
 define void @test(<2 x double>* %dst, <4 x double> %src) nounwind {
@@ -13,7 +13,7 @@ entry:
         ret void
 }
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movdqa
 define void @test2(<4 x i16>* %src, <4 x i32>* %dest) nounwind {
 entry:
diff --git a/test/CodeGen/X86/dbg-at-specficiation.ll b/test/CodeGen/X86/dbg-at-specficiation.ll
index 48b8202..a6eebcb 100644
--- a/test/CodeGen/X86/dbg-at-specficiation.ll
+++ b/test/CodeGen/X86/dbg-at-specficiation.ll
@@ -7,14 +7,13 @@
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"x.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 140253)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{metadata !2}
+!0 = metadata !{i32 720913, metadata !11, i32 12, metadata !"clang version 3.0 (trunk 140253)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !2, metadata !3, null, i32 0} ; [ DW_TAG_compile_unit ]
 !2 = metadata !{i32 0}
-!3 = metadata !{metadata !4}
-!4 = metadata !{metadata !5}
-!5 = metadata !{i32 720948, i32 0, null, metadata !"a", metadata !"a", metadata !"", metadata !6, i32 1, metadata !7, i32 0, i32 1, [10 x i32]* @a} ; [ DW_TAG_variable ]
-!6 = metadata !{i32 720937, metadata !"x.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
+!3 = metadata !{metadata !5}
+!5 = metadata !{i32 720948, i32 0, null, metadata !"a", metadata !"a", metadata !"", metadata !6, i32 1, metadata !7, i32 0, i32 1, [10 x i32]* @a, null} ; [ DW_TAG_variable ]
+!6 = metadata !{i32 720937, metadata !11} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 720897, null, metadata !"", null, i32 0, i64 320, i64 32, i32 0, i32 0, metadata !8, metadata !9, i32 0, i32 0} ; [ DW_TAG_array_type ]
-!8 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!8 = metadata !{i32 720932, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !9 = metadata !{metadata !10}
 !10 = metadata !{i32 720929, i64 0, i64 10}        ; [ DW_TAG_subrange_type ]
+!11 = metadata !{metadata !"x.c", metadata !"/private/tmp"}
diff --git a/test/CodeGen/X86/dbg-byval-parameter.ll b/test/CodeGen/X86/dbg-byval-parameter.ll
index 719a526..ef9e03c 100644
--- a/test/CodeGen/X86/dbg-byval-parameter.ll
+++ b/test/CodeGen/X86/dbg-byval-parameter.ll
@@ -1,4 +1,4 @@
-; RUN: llc  -march=x86 -asm-verbose < %s | grep DW_TAG_formal_parameter
+; RUN: llc -march=x86 -asm-verbose < %s | grep DW_TAG_formal_parameter
 
 
 %struct.Pt = type { double, double }
@@ -28,9 +28,9 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!3}
 
 !0 = metadata !{i32 786689, metadata !1, metadata !"my_r0", metadata !2, i32 11, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, double (%struct.Rect*)* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786478, metadata !19, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, double (%struct.Rect*)* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !19} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !18, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786449, metadata !19, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !20, metadata !20, metadata !18, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
 !4 = metadata !{i32 786453, metadata !19, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{metadata !6, metadata !7}
 !6 = metadata !{i32 786468, metadata !19, metadata !2, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
@@ -44,6 +44,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 !14 = metadata !{i32 786445, metadata !19, metadata !7, metadata !"P2", i32 8, i64 128, i64 64, i64 128, i32 0, metadata !10} ; [ DW_TAG_member ]
 !15 = metadata !{i32 11, i32 0, metadata !1, null}
 !16 = metadata !{i32 12, i32 0, metadata !17, null}
-!17 = metadata !{i32 786443, metadata !2, metadata !1, i32 11, i32 0} ; [ DW_TAG_lexical_block ]
+!17 = metadata !{i32 786443, metadata !19, metadata !1, i32 11, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !18 = metadata !{metadata !1}
 !19 = metadata !{metadata !"b2.c", metadata !"/tmp/"}
+!20 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/dbg-const-int.ll b/test/CodeGen/X86/dbg-const-int.ll
index f72729c..fc4ff6d 100644
--- a/test/CodeGen/X86/dbg-const-int.ll
+++ b/test/CodeGen/X86/dbg-const-int.ll
@@ -14,17 +14,18 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 12, metadata !2, metadata !"clang version 3.0 (trunk 132191)", i1 true, metadata !"", i32 0, null, null, metadata !11, null,  null, null} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @foo, null, null, metadata !12, i32 0} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786449, metadata !13, i32 12, metadata !"clang version 3.0 (trunk 132191)", i1 true, metadata !"", i32 0, metadata !14, metadata !14, metadata !11, null,  null, null} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 786478, metadata !13, metadata !2, metadata !"foo", metadata !"foo", metadata !"", i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @foo, null, null, metadata !12, i32 0} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !13} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!3 = metadata !{i32 786453, metadata !13, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 786468, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !6 = metadata !{i32 786688, metadata !7, metadata !"i", metadata !2, i32 2, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!7 = metadata !{i32 786443, metadata !2, metadata !1, i32 1, i32 11, i32 0} ; [ DW_TAG_lexical_block ]
+!7 = metadata !{i32 786443, metadata !13, metadata !1, i32 1, i32 11, i32 0} ; [ DW_TAG_lexical_block ]
 !8 = metadata !{i32 42}
 !9 = metadata !{i32 2, i32 12, metadata !7, null}
 !10 = metadata !{i32 3, i32 2, metadata !7, null}
 !11 = metadata !{metadata !1}
 !12 = metadata !{metadata !6}
 !13 = metadata !{metadata !"a.c", metadata !"/private/tmp"}
+!14 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/dbg-const.ll b/test/CodeGen/X86/dbg-const.ll
index 2ac359d..b37eb0a 100644
--- a/test/CodeGen/X86/dbg-const.ll
+++ b/test/CodeGen/X86/dbg-const.ll
@@ -30,14 +30,14 @@ declare i32 @bar() nounwind readnone
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"foobar", metadata !"foobar", metadata !"foobar", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @foobar, null, null, metadata !14, i32 0} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !15, metadata !1, metadata !"foobar", metadata !"foobar", metadata !"foobar", i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @foobar, null, null, metadata !14, i32 0} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !15} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 2.9 (trunk 114183)", i1 true, metadata !"", i32 0, null, null, metadata !13, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null}
+!2 = metadata !{i32 786449, metadata !15, i32 12, metadata !"clang version 2.9 (trunk 114183)", i1 true, metadata !"", i32 0, metadata !16, metadata !16, metadata !13, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !15, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null}
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}
+!5 = metadata !{i32 786468, metadata !15, metadata !1, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}
 !6 = metadata !{i32 786688, metadata !7, metadata !"j", metadata !1, i32 15, metadata !5, i32 0, null}
-!7 = metadata !{i32 786443, metadata !1, metadata !0, i32 12, i32 52, i32 0} ; [ DW_TAG_lexical_block ]
+!7 = metadata !{i32 786443, metadata !15, metadata !0, i32 12, i32 52, i32 0} ; [ DW_TAG_lexical_block ]
 !8 = metadata !{i32 42}
 !9 = metadata !{i32 15, i32 12, metadata !7, null}
 !10 = metadata !{i32 23, i32 3, metadata !7, null}
@@ -46,3 +46,4 @@ declare i32 @bar() nounwind readnone
 !13 = metadata !{metadata !0}
 !14 = metadata !{metadata !6}
 !15 = metadata !{metadata !"mu.c", metadata !"/private/tmp"}
+!16 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/dbg-declare-arg.ll b/test/CodeGen/X86/dbg-declare-arg.ll
index f7e0c91..55b4238 100644
--- a/test/CodeGen/X86/dbg-declare-arg.ll
+++ b/test/CodeGen/X86/dbg-declare-arg.ll
@@ -71,41 +71,41 @@ entry:
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !"", i32 0, metadata !1, metadata !"~A", metadata !"~A", metadata !3, i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 589826, metadata !2, metadata !"A", metadata !3, i32 2, i64 128, i64 32, i32 0, i32 0, null, metadata !4, i32 0, null, null} ; [ DW_TAG_class_type ]
-!2 = metadata !{i32 786449, i32 4, metadata !3, metadata !"clang version 3.0 (trunk 130127)", i1 false, metadata !"", i32 0, null, null, metadata !50, null, null} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786478, metadata !51, metadata !1, metadata !"~A", metadata !"~A", metadata !"", i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 589826, metadata !51, metadata !2, metadata !"A", i32 2, i64 128, i64 32, i32 0, i32 0, null, metadata !4, i32 0, null, null} ; [ DW_TAG_class_type ]
+!2 = metadata !{i32 786449, metadata !51, i32 4, metadata !"clang version 3.0 (trunk 130127)", i1 false, metadata !"", i32 0, metadata !24, metadata !24, metadata !50, null, null, null} ; [ DW_TAG_compile_unit ]
 !3 = metadata !{i32 786473, metadata !51} ; [ DW_TAG_file_type ]
 !4 = metadata !{metadata !5, metadata !7, metadata !8, metadata !9, metadata !0, metadata !10, metadata !14}
-!5 = metadata !{i32 786445, metadata !3, metadata !"x", metadata !3, i32 2, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ]
-!6 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!7 = metadata !{i32 786445, metadata !3, metadata !"y", metadata !3, i32 2, i64 32, i64 32, i64 32, i32 0, metadata !6} ; [ DW_TAG_member ]
-!8 = metadata !{i32 786445, metadata !3, metadata !"z", metadata !3, i32 2, i64 32, i64 32, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ]
-!9 = metadata !{i32 786445, metadata !3, metadata !"o", metadata !3, i32 2, i64 32, i64 32, i64 96, i32 0, metadata !6} ; [ DW_TAG_member ]
-!10 = metadata !{i32 786478, metadata !"", i32 0, metadata !1, metadata !"A", metadata !"A", metadata !3, i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null} ; [ DW_TAG_subprogram ]
-!11 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!5 = metadata !{i32 786445, metadata !51, metadata !3, metadata !"x", i32 2, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ]
+!6 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!7 = metadata !{i32 786445, metadata !51, metadata !3, metadata !"y", i32 2, i64 32, i64 32, i64 32, i32 0, metadata !6} ; [ DW_TAG_member ]
+!8 = metadata !{i32 786445, metadata !51, metadata !3, metadata !"z", i32 2, i64 32, i64 32, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ]
+!9 = metadata !{i32 786445, metadata !51, metadata !3, metadata !"o", i32 2, i64 32, i64 32, i64 96, i32 0, metadata !6} ; [ DW_TAG_member ]
+!10 = metadata !{i32 786478, metadata !51, metadata !1, metadata !"A", metadata !"A", metadata !"", i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!11 = metadata !{i32 786453, metadata !51, metadata !3, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !12 = metadata !{null, metadata !13}
 !13 = metadata !{i32 786447, metadata !2, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ]
-!14 = metadata !{i32 786478, metadata !"", i32 0, metadata !1, metadata !"A", metadata !"A", metadata !3, i32 2, metadata !15, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null} ; [ DW_TAG_subprogram ]
-!15 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !16, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!14 = metadata !{i32 786478, metadata !51, metadata !1, metadata !"A", metadata !"A", metadata !"", i32 2, metadata !15, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!15 = metadata !{i32 786453, metadata !51, metadata !3, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !16, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !16 = metadata !{null, metadata !13, metadata !17}
-!17 = metadata !{i32 589840, metadata !2, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !18} ; [ DW_TAG_reference_type ]
+!17 = metadata !{i32 589840, null, metadata !2, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !18} ; [ DW_TAG_reference_type ]
 !18 = metadata !{i32 786470, metadata !2, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !1} ; [ DW_TAG_const_type ]
-!19 = metadata !{i32 786478, metadata !"_Z3fooi", i32 0, metadata !3, metadata !"foo", metadata !"foo", metadata !3, i32 4, metadata !20, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*, i32)* @_Z3fooi, null, null} ; [ DW_TAG_subprogram ]
-!20 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !21, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!19 = metadata !{i32 786478, metadata !51, metadata !3, metadata !"foo", metadata !"foo", metadata !"_Z3fooi", i32 4, metadata !20, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*, i32)* @_Z3fooi, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!20 = metadata !{i32 786453, metadata !51, metadata !3, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !21, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !21 = metadata !{metadata !1}
-!22 = metadata !{i32 786478, metadata !"_ZN1AD1Ev", i32 0, metadata !3, metadata !"~A", metadata !"~A", metadata !3, i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD1Ev, null, null} ; [ DW_TAG_subprogram ]
-!23 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !24, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!22 = metadata !{i32 786478, metadata !51, metadata !3, metadata !"~A", metadata !"~A", metadata !"_ZN1AD1Ev", i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD1Ev, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!23 = metadata !{i32 786453, metadata !51, metadata !3, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !24, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !24 = metadata !{null}
-!25 = metadata !{i32 786478, metadata !"_ZN1AD2Ev", i32 0, metadata !3, metadata !"~A", metadata !"~A", metadata !3, i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD2Ev, null, null} ; [ DW_TAG_subprogram ]
+!25 = metadata !{i32 786478, metadata !51, metadata !3, metadata !"~A", metadata !"~A", metadata !"_ZN1AD2Ev", i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD2Ev, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !26 = metadata !{i32 786689, metadata !19, metadata !"i", metadata !3, i32 16777220, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ]
 !27 = metadata !{i32 4, i32 11, metadata !19, null}
 !28 = metadata !{i32 786688, metadata !29, metadata !"j", metadata !3, i32 5, metadata !6, i32 0, null} ; [ DW_TAG_auto_variable ]
-!29 = metadata !{i32 786443, metadata !19, i32 4, i32 14, metadata !3, i32 0} ; [ DW_TAG_lexical_block ]
+!29 = metadata !{i32 786443, metadata !51, metadata !19, i32 4, i32 14, i32 0} ; [ DW_TAG_lexical_block ]
 !30 = metadata !{i32 5, i32 7, metadata !29, null}
 !31 = metadata !{i32 5, i32 12, metadata !29, null}
 !32 = metadata !{i32 6, i32 3, metadata !29, null}
 !33 = metadata !{i32 7, i32 5, metadata !34, null}
-!34 = metadata !{i32 786443, metadata !29, i32 6, i32 16, metadata !3, i32 1} ; [ DW_TAG_lexical_block ]
+!34 = metadata !{i32 786443, metadata !51, metadata !29, i32 6, i32 16, i32 1} ; [ DW_TAG_lexical_block ]
 !35 = metadata !{i32 8, i32 3, metadata !34, null}
 !36 = metadata !{i32 9, i32 9, metadata !29, null}
 !37 = metadata !{i32 786688, metadata !29, metadata !"my_a", metadata !3, i32 9, metadata !38, i32 0, null} ; [ DW_TAG_auto_variable ]
@@ -120,6 +120,6 @@ entry:
 !46 = metadata !{i32 786689, metadata !25, metadata !"this", metadata !3, i32 16777218, metadata !13, i32 64, null} ; [ DW_TAG_arg_variable ]
 !47 = metadata !{i32 2, i32 47, metadata !25, null}
 !48 = metadata !{i32 2, i32 54, metadata !49, null}
-!49 = metadata !{i32 786443, metadata !25, i32 2, i32 52, metadata !3, i32 2} ; [ DW_TAG_lexical_block ]
+!49 = metadata !{i32 786443, metadata !51, metadata !25, i32 2, i32 52, i32 2} ; [ DW_TAG_lexical_block ]
 !50 = metadata !{metadata !0, metadata !10, metadata !14, metadata !19, metadata !22, metadata !25}
 !51 = metadata !{metadata !"a.cc", metadata !"/private/tmp"}
diff --git a/test/CodeGen/X86/dbg-declare.ll b/test/CodeGen/X86/dbg-declare.ll
index 6ac397a..d74e270 100644
--- a/test/CodeGen/X86/dbg-declare.ll
+++ b/test/CodeGen/X86/dbg-declare.ll
@@ -29,14 +29,14 @@ declare void @llvm.stackrestore(i8*) nounwind
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.1 (trunk 153698)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !26, i32 12, metadata !"clang version 3.1 (trunk 153698)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, metadata !6, metadata !"foo", metadata !"foo", metadata !"", metadata !6, i32 6, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32*)* @foo, null, null, metadata !12} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 786473, metadata !"20020104-2.c", metadata !"/Volumes/Sandbox/llvm", null} ; [ DW_TAG_file_type ]
+!5 = metadata !{i32 786478, metadata !26, metadata !0, metadata !"foo", metadata !"foo", metadata !"", i32 6, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32*)* @foo, null, null, metadata !12, i32 0} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 786473, metadata !26} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{metadata !9, metadata !10}
-!9 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !10 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ]
 !11 = metadata !{i32 786470, null, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !9} ; [ DW_TAG_const_type ]
 !12 = metadata !{metadata !13}
@@ -44,12 +44,13 @@ declare void @llvm.stackrestore(i8*) nounwind
 !14 = metadata !{i32 786689, metadata !5, metadata !"x", metadata !6, i32 16777221, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
 !15 = metadata !{i32 5, i32 21, metadata !5, null}
 !16 = metadata !{i32 7, i32 13, metadata !17, null}
-!17 = metadata !{i32 786443, metadata !5, i32 6, i32 1, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
+!17 = metadata !{i32 786443, metadata !26, metadata !5, i32 6, i32 1, i32 0} ; [ DW_TAG_lexical_block ]
 !18 = metadata !{i32 786688, metadata !17, metadata !"a", metadata !6, i32 7, metadata !19, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
 !19 = metadata !{i32 786433, null, metadata !"", null, i32 0, i64 0, i64 8, i32 0, i32 0, metadata !20, metadata !21, i32 0, i32 0} ; [ DW_TAG_array_type ]
-!20 = metadata !{i32 786468, null, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!20 = metadata !{i32 786468, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !21 = metadata !{metadata !22}
 !22 = metadata !{i32 786465, i64 0, i64 -1}        ; [ DW_TAG_subrange_type ]
 !23 = metadata !{i32 7, i32 8, metadata !17, null}
 !24 = metadata !{i32 9, i32 1, metadata !17, null}
 !25 = metadata !{i32 8, i32 3, metadata !17, null}
+!26 = metadata !{metadata !"20020104-2.c", metadata !"/Volumes/Sandbox/llvm"}
diff --git a/test/CodeGen/X86/dbg-file-name.ll b/test/CodeGen/X86/dbg-file-name.ll
index 1bd3d77..797b4b5 100644
--- a/test/CodeGen/X86/dbg-file-name.ll
+++ b/test/CodeGen/X86/dbg-file-name.ll
@@ -12,10 +12,11 @@ define i32 @main() nounwind {
 !llvm.dbg.cu = !{!2}
 
 !1 = metadata !{i32 786473, metadata !10} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, metadata !10, i32 1, metadata !"LLVM build 00", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !9, null} ; [ DW_TAG_compile_unit ]
-!5 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 786478, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 9, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
-!7 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 786449, metadata !10, i32 1, metadata !"LLVM build 00", i1 true, metadata !"", i32 0, metadata !11, metadata !11, metadata !9, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!5 = metadata !{i32 786468, metadata !10, metadata !1, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786478, metadata !10, metadata !1, metadata !"main", metadata !"main", metadata !"main", i32 9, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!7 = metadata !{i32 786453, metadata !10, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{metadata !5}
 !9 = metadata !{metadata !6}
 !10 = metadata !{metadata !"simple.c", metadata !"/Users/manav/one/two"}
+!11 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/dbg-i128-const.ll b/test/CodeGen/X86/dbg-i128-const.ll
index cc612b2..f413909 100644
--- a/test/CodeGen/X86/dbg-i128-const.ll
+++ b/test/CodeGen/X86/dbg-i128-const.ll
@@ -16,10 +16,10 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !0 = metadata !{i128 42 }
 !1 = metadata !{i32 786688, metadata !2, metadata !"MAX", metadata !4, i32 29, metadata !8, i32 0, null} ; [ DW_TAG_auto_variable ]
-!2 = metadata !{i32 786443, metadata !4, metadata !3, i32 26, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
-!3 = metadata !{i32 786478, metadata !4, metadata !"__foo", metadata !"__foo", metadata !"__foo", metadata !4, i32 26, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i128 (i128, i128)* @__foo, null, null, null, i32 26} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 786443, metadata !13, metadata !3, i32 26, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!3 = metadata !{i32 786478, metadata !13, metadata !4, metadata !"__foo", metadata !"__foo", metadata !"__foo", i32 26, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 0, i128 (i128, i128)* @__foo, null, null, null, i32 26} ; [ DW_TAG_subprogram ]
 !4 = metadata !{i32 786473, metadata !13} ; [ DW_TAG_file_type ]
-!5 = metadata !{i32 786449, i32 1, metadata !4, metadata !"clang", i1 true, metadata !"", i32 0, null, null, metadata !12, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
+!5 = metadata !{i32 786449, metadata !13, i32 1, metadata !"clang", i1 true, metadata !"", i32 0, metadata !15, metadata !15, metadata !12, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
 !6 = metadata !{i32 786453, metadata !13, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !7 = metadata !{metadata !8, metadata !8, metadata !8}
 !8 = metadata !{i32 786454, metadata !14, metadata !4, metadata !"ti_int", i32 78, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_typedef ]
@@ -29,3 +29,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !12 = metadata !{metadata !3}
 !13 = metadata !{metadata !"foo.c", metadata !"/tmp"}
 !14 = metadata !{metadata !"myint.h", metadata !"/tmp"}
+!15 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/dbg-large-unsigned-const.ll b/test/CodeGen/X86/dbg-large-unsigned-const.ll
index c381cd7..c5cbf06 100644
--- a/test/CodeGen/X86/dbg-large-unsigned-const.ll
+++ b/test/CodeGen/X86/dbg-large-unsigned-const.ll
@@ -30,29 +30,31 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !30 = metadata !{metadata !7, metadata !11}
 !31 = metadata !{metadata !12}
 
-!0 = metadata !{i32 786449, i32 4, metadata !2, metadata !"clang version 3.0 (trunk 135593)", i1 true, metadata !"", i32 0, null, null, metadata !29, null, metadata !""} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{i32 786478, metadata !"_Z3iseRKxS0_", i32 0, metadata !2, metadata !"ise", metadata !"ise", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i1 (i64*, i64*)* @_Z3iseRKxS0_, null, null, metadata !30, i32 2} ; [ DW_TAG_subprogram ]
-!2 = metadata !{i32 786473, metadata !"lli.cc", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 786449, metadata !32, i32 4, metadata !"clang version 3.0 (trunk 135593)", i1 true, metadata !"", i32 0, metadata !33, metadata !33, metadata !29, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 786478, metadata !32, null, metadata !"ise", metadata !"ise", metadata !"_Z3iseRKxS0_", i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i1 (i64*, i64*)* @_Z3iseRKxS0_, null, null, metadata !30, i32 2} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 786473, metadata !32} ; [ DW_TAG_file_type ]
+!3 = metadata !{i32 786453, metadata !32, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !0, metadata !"bool", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 786478, metadata !"_Z2fnx", i32 0, metadata !2, metadata !"fn", metadata !"fn", metadata !2, i32 6, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i1 (i64)* @_Z2fnx, null, null, metadata !31, i32 6} ; [ DW_TAG_subprogram ]
+!5 = metadata !{i32 786468, null, metadata !0, metadata !"bool", i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786478, metadata !32, null, metadata !"fn", metadata !"fn", metadata !"_Z2fnx", i32 6, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i1 (i64)* @_Z2fnx, null, null, metadata !31, i32 6} ; [ DW_TAG_subprogram ]
 !7 = metadata !{i32 786689, metadata !1, metadata !"LHS", metadata !2, i32 16777218, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
 !8 = metadata !{i32 786448, metadata !0, null, null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !9} ; [ DW_TAG_reference_type ]
 !9 = metadata !{i32 786470, metadata !0, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_const_type ]
-!10 = metadata !{i32 786468, metadata !0, metadata !"long long int", null, i32 0, i64 64, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!10 = metadata !{i32 786468, null, metadata !0, metadata !"long long int", i32 0, i64 64, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !11 = metadata !{i32 786689, metadata !1, metadata !"RHS", metadata !2, i32 33554434, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
 !12 = metadata !{i32 786689, metadata !6, metadata !"a", metadata !2, i32 16777222, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
 !13 = metadata !{i32 2, i32 27, metadata !1, null}
 !14 = metadata !{i32 2, i32 49, metadata !1, null}
 !15 = metadata !{i32 3, i32 3, metadata !16, null}
-!16 = metadata !{i32 786443, metadata !2, metadata !1, i32 2, i32 54, i32 0} ; [ DW_TAG_lexical_block ]
+!16 = metadata !{i32 786443, metadata !32, metadata !1, i32 2, i32 54, i32 0} ; [ DW_TAG_lexical_block ]
 !20 = metadata !{i32 6, i32 19, metadata !6, null}
 !21 = metadata !{i32 786689, metadata !1, metadata !"LHS", metadata !2, i32 16777218, metadata !8, i32 0, metadata !22} ; [ DW_TAG_arg_variable ]
 !22 = metadata !{i32 7, i32 10, metadata !23, null}
-!23 = metadata !{i32 786443, metadata !2, metadata !6, i32 6, i32 22, i32 1} ; [ DW_TAG_lexical_block ]
+!23 = metadata !{i32 786443, metadata !32, metadata !6, i32 6, i32 22, i32 1} ; [ DW_TAG_lexical_block ]
 !24 = metadata !{i32 2, i32 27, metadata !1, metadata !22}
 !25 = metadata !{i64 9223372036854775807}         
 !26 = metadata !{i32 786689, metadata !1, metadata !"RHS", metadata !2, i32 33554434, metadata !8, i32 0, metadata !22} ; [ DW_TAG_arg_variable ]
 !27 = metadata !{i32 2, i32 49, metadata !1, metadata !22}
 !28 = metadata !{i32 3, i32 3, metadata !16, metadata !22}
+!32 = metadata !{metadata !"lli.cc", metadata !"/private/tmp"}
+!33 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/dbg-merge-loc-entry.ll b/test/CodeGen/X86/dbg-merge-loc-entry.ll
index 30d0305..ccf4808 100644
--- a/test/CodeGen/X86/dbg-merge-loc-entry.ll
+++ b/test/CodeGen/X86/dbg-merge-loc-entry.ll
@@ -1,18 +1,12 @@
-; RUN: llc < %s | FileCheck %s
-; RUN: llc < %s -regalloc=basic | FileCheck %s
+; RUN: llc < %s -o %t -filetype=obj
+; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s
+; RUN: llc < %s -o %t -filetype=obj -regalloc=basic
+; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s
+
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin8"
 
-;CHECK: Ldebug_loc0:
-;CHECK-NEXT:	.quad	Lfunc_begin0
-;CHECK-NEXT:	.quad	L
-;CHECK-NEXT: Lset{{.*}} = Ltmp{{.*}}-Ltmp{{.*}}          ## Loc expr size
-;CHECK-NEXT:    .short  Lset
-;CHECK-NEXT: Ltmp
-;CHECK-NEXT:	.byte	85                      ## DW_OP_reg5
-;CHECK-NEXT: Ltmp
-;CHECK-NEXT:	.quad	0
-;CHECK-NEXT:	.quad	0
+;CHECK: DW_AT_location{{.*}}(<0x01> 55 )
 
 %0 = type { i64, i1 }
 
@@ -45,16 +39,16 @@ declare %0 @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"__udivmodti4", metadata !"__udivmodti4", metadata !"", metadata !1, i32 879, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, null, i32 879} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !29, metadata !1, metadata !"__udivmodti4", metadata !"__udivmodti4", metadata !"", i32 879, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, null, i32 879} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !29} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !28, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
+!2 = metadata !{i32 786449, metadata !29, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !31, metadata !31, metadata !28, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
 !3 = metadata !{i32 786453, metadata !29, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5, metadata !5, metadata !5, metadata !8}
 !5 = metadata !{i32 786454, metadata !30, metadata !6, metadata !"UTItype", i32 166, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ]
 !6 = metadata !{i32 786473, metadata !30} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786468, metadata !29, metadata !1, metadata !"", i32 0, i64 128, i64 128, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
 !8 = metadata !{i32 786447, metadata !29, metadata !1, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_pointer_type ]
-!9 = metadata !{i32 786478, metadata !1, metadata !"__divti3", metadata !"__divti3", metadata !"__divti3", metadata !1, i32 1094, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i128 (i128, i128)* @__divti3, null, null, null, i32 1094} ; [ DW_TAG_subprogram ]
+!9 = metadata !{i32 786478, metadata !29, metadata !1, metadata !"__divti3", metadata !"__divti3", metadata !"__divti3", i32 1094, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i128 (i128, i128)* @__divti3, null, null, null, i32 1094} ; [ DW_TAG_subprogram ]
 !10 = metadata !{i32 786453, metadata !29, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !11 = metadata !{metadata !12, metadata !12, metadata !12}
 !12 = metadata !{i32 786454, metadata !30, metadata !6, metadata !"TItype", i32 160, i64 0, i64 0, i64 0, i32 0, metadata !13} ; [ DW_TAG_typedef ]
@@ -63,16 +57,17 @@ declare %0 @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
 !15 = metadata !{i32 1093, i32 0, metadata !9, null}
 !16 = metadata !{i64 0}
 !17 = metadata !{i32 786688, metadata !18, metadata !"c", metadata !1, i32 1095, metadata !19, i32 0, null} ; [ DW_TAG_auto_variable ]
-!18 = metadata !{i32 786443, metadata !1, metadata !9, i32 1094, i32 0, i32 13} ; [ DW_TAG_lexical_block ]
+!18 = metadata !{i32 786443, metadata !29, metadata !9, i32 1094, i32 0, i32 13} ; [ DW_TAG_lexical_block ]
 !19 = metadata !{i32 786454, metadata !30, metadata !6, metadata !"word_type", i32 424, i64 0, i64 0, i64 0, i32 0, metadata !20} ; [ DW_TAG_typedef ]
 !20 = metadata !{i32 786468, metadata !29, metadata !1, metadata !"long int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !21 = metadata !{i32 1095, i32 0, metadata !18, null}
 !22 = metadata !{i32 1103, i32 0, metadata !18, null}
 !23 = metadata !{i32 1104, i32 0, metadata !18, null}
 !24 = metadata !{i32 1003, i32 0, metadata !25, metadata !26}
-!25 = metadata !{i32 786443, metadata !1, metadata !0, i32 879, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!25 = metadata !{i32 786443, metadata !29, metadata !0, i32 879, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !26 = metadata !{i32 1107, i32 0, metadata !18, null}
 !27 = metadata !{i32 1111, i32 0, metadata !18, null}
 !28 = metadata !{metadata !0, metadata !9}
 !29 = metadata !{metadata !"foobar.c", metadata !"/tmp"}
 !30 = metadata !{metadata !"foobar.h", metadata !"/tmp"}
+!31 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/dbg-prolog-end.ll b/test/CodeGen/X86/dbg-prolog-end.ll
index d1774cc..c8d8499 100644
--- a/test/CodeGen/X86/dbg-prolog-end.ll
+++ b/test/CodeGen/X86/dbg-prolog-end.ll
@@ -35,21 +35,23 @@ entry:
 !llvm.dbg.cu = !{!0}
 !18 = metadata !{metadata !1, metadata !6}
 
-!0 = metadata !{i32 786449, i32 12, metadata !2, metadata !"clang version 3.0 (trunk 131100)", i1 false, metadata !"", i32 0, null, null, metadata !18, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32)* @foo, null, null, null, i32 1} ; [ DW_TAG_subprogram ]
-!2 = metadata !{i32 786473, metadata !"/tmp/a.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 786449, metadata !19, i32 12, metadata !"clang version 3.0 (trunk 131100)", i1 false, metadata !"", i32 0, metadata !20, metadata !20, metadata !18, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 786478, metadata !19, metadata !2, metadata !"foo", metadata !"foo", metadata !"", i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32)* @foo, null, null, null, i32 1} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 786473, metadata !19} ; [ DW_TAG_file_type ]
+!3 = metadata !{i32 786453, metadata !19, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 786478, metadata !2, metadata !"main", metadata !"main", metadata !"", metadata !2, i32 7, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @main, null, null, null, i32 7} ; [ DW_TAG_subprogram ]
+!5 = metadata !{i32 786468, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786478, metadata !19, metadata !2, metadata !"main", metadata !"main", metadata !"", i32 7, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @main, null, null, null, i32 7} ; [ DW_TAG_subprogram ]
 !7 = metadata !{i32 786689, metadata !1, metadata !"i", metadata !2, i32 16777217, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !8 = metadata !{i32 1, i32 13, metadata !1, null}
 !9 = metadata !{i32 786688, metadata !10, metadata !"j", metadata !2, i32 2, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!10 = metadata !{i32 786443, metadata !2, metadata !1, i32 1, i32 16, i32 0} ; [ DW_TAG_lexical_block ]
+!10 = metadata !{i32 786443, metadata !19, metadata !1, i32 1, i32 16, i32 0} ; [ DW_TAG_lexical_block ]
 !11 = metadata !{i32 2, i32 6, metadata !10, null}
 !12 = metadata !{i32 2, i32 11, metadata !10, null}
 !13 = metadata !{i32 3, i32 2, metadata !10, null}
 !14 = metadata !{i32 4, i32 2, metadata !10, null}
 !15 = metadata !{i32 5, i32 2, metadata !10, null}
 !16 = metadata !{i32 8, i32 2, metadata !17, null}
-!17 = metadata !{i32 786443, metadata !2, metadata !6, i32 7, i32 12, i32 1} ; [ DW_TAG_lexical_block ]
+!17 = metadata !{i32 786443, metadata !19, metadata !6, i32 7, i32 12, i32 1} ; [ DW_TAG_lexical_block ]
+!19 = metadata !{metadata !"/tmp/a.c", metadata !"/private/tmp"}
+!20 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/dbg-subrange.ll b/test/CodeGen/X86/dbg-subrange.ll
index b08d68a..ffb5f2d 100644
--- a/test/CodeGen/X86/dbg-subrange.ll
+++ b/test/CodeGen/X86/dbg-subrange.ll
@@ -14,11 +14,11 @@ entry:
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.1 (trunk 144833)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !11,  metadata !11, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !21, i32 12, metadata !"clang version 3.1 (trunk 144833)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !11,  metadata !11, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 720942, metadata !6, metadata !"bar", metadata !"bar", metadata !"", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void ()* @bar, null, null, metadata !9} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 720937, metadata !"small.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
+!5 = metadata !{i32 720942, metadata !21, metadata !6, metadata !"bar", metadata !"bar", metadata !"", i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void ()* @bar, null, null, metadata !9, i32 0} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 720937, metadata !21} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{null}
 !9 = metadata !{metadata !10}
@@ -26,9 +26,10 @@ entry:
 !11 = metadata !{metadata !13}
 !13 = metadata !{i32 720948, i32 0, null, metadata !"s", metadata !"s", metadata !"", metadata !6, i32 2, metadata !14, i32 0, i32 1, [4294967296 x i8]* @s, null} ; [ DW_TAG_variable ]
 !14 = metadata !{i32 720897, null, metadata !"", null, i32 0, i64 34359738368, i64 8, i32 0, i32 0, metadata !15, metadata !16, i32 0, i32 0} ; [ DW_TAG_array_type ]
-!15 = metadata !{i32 720932, null, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!15 = metadata !{i32 720932, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !16 = metadata !{metadata !17}
 !17 = metadata !{i32 720929, i64 0, i64 4294967296} ; [ DW_TAG_subrange_type ]
 !18 = metadata !{i32 5, i32 3, metadata !19, null}
-!19 = metadata !{i32 786443, metadata !5, i32 4, i32 1, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
+!19 = metadata !{i32 786443, metadata !21, metadata !5, i32 4, i32 1, i32 0} ; [ DW_TAG_lexical_block ]
 !20 = metadata !{i32 6, i32 1, metadata !19, null}
+!21 = metadata !{metadata !"small.c", metadata !"/private/tmp"}
diff --git a/test/CodeGen/X86/dbg-value-dag-combine.ll b/test/CodeGen/X86/dbg-value-dag-combine.ll
index c63235e..e281493 100644
--- a/test/CodeGen/X86/dbg-value-dag-combine.ll
+++ b/test/CodeGen/X86/dbg-value-dag-combine.ll
@@ -16,7 +16,7 @@ entry:
   call void @llvm.dbg.value(metadata !12, i64 0, metadata !13), !dbg !14
   %tmp2 = load i32 addrspace(1)* %ip, align 4, !dbg !15
   %tmp3 = add i32 0, %tmp2, !dbg !15
-; CHECK:  ##DEBUG_VALUE: idx <- EAX+0
+; CHECK:  ##DEBUG_VALUE: idx <- EAX{{$}}
   call void @llvm.dbg.value(metadata !{i32 %tmp3}, i64 0, metadata !13), !dbg
 !15
   %arrayidx = getelementptr i32 addrspace(1)* %ip, i32 %1, !dbg !16
@@ -25,17 +25,17 @@ entry:
 }
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"__OpenCL_test_kernel", metadata !"__OpenCL_test_kernel", metadata !"__OpenCL_test_kernel", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !19, metadata !1, metadata !"__OpenCL_test_kernel", metadata !"__OpenCL_test_kernel", metadata !"__OpenCL_test_kernel", i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !19} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"clc", i1 false, metadata !"", i32 0, null, null, metadata !18, null,  null, null} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 786449, metadata !19, i32 1, metadata !"clc", i1 false, metadata !"", i32 0, metadata !12, metadata !12, metadata !18, null,  null, null} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !19, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{null, metadata !5}
-!5 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_pointer_type ]
-!6 = metadata !{i32 786468, metadata !2, metadata !"unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_pointer_type ]
+!6 = metadata !{i32 786468, null, metadata !2, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
 !7 = metadata !{i32 786689, metadata !0, metadata !"ip", metadata !1, i32 1, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !8 = metadata !{i32 1, i32 42, metadata !0, null}
 !9 = metadata !{i32 786688, metadata !10, metadata !"gid", metadata !1, i32 3, metadata !6, i32 0, null} ; [ DW_TAG_auto_variable ]
-!10 = metadata !{i32 786443, metadata !0, i32 2, i32 1, metadata !1, i32 0} ; [ DW_TAG_lexical_block ]
+!10 = metadata !{i32 786443, metadata !19, metadata !0, i32 2, i32 1, i32 0} ; [ DW_TAG_lexical_block ]
 !11 = metadata !{i32 3, i32 41, metadata !10, null}
 !12 = metadata !{i32 0}
 !13 = metadata !{i32 786688, metadata !10, metadata !"idx", metadata !1, i32 4, metadata !6, i32 0, null} ; [ DW_TAG_auto_variable ]
diff --git a/test/CodeGen/X86/dbg-value-isel.ll b/test/CodeGen/X86/dbg-value-isel.ll
index acc360e..0013385 100644
--- a/test/CodeGen/X86/dbg-value-isel.ll
+++ b/test/CodeGen/X86/dbg-value-isel.ll
@@ -80,9 +80,9 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !20, metadata !1, metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !20} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, metadata !20, i32 1, metadata !"clc", i1 false, metadata !"", i32 0, null, null, metadata !19, null,  null, null} ; [ DW_TAG_compile_unit ]
+!2 = metadata !{i32 786449, metadata !20, i32 1, metadata !"clc", i1 false, metadata !"", i32 0, metadata !21, metadata !21, metadata !19, null,  null, null} ; [ DW_TAG_compile_unit ]
 !3 = metadata !{i32 786453, metadata !20, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{null, metadata !5}
 !5 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_pointer_type ]
@@ -101,3 +101,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !18 = metadata !{i32 10, i32 1, metadata !0, null}
 !19 = metadata !{metadata !0}
 !20 = metadata !{metadata !"OCLlLwTXZ.cl", metadata !"/tmp"}
+!21 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/dbg-value-location.ll b/test/CodeGen/X86/dbg-value-location.ll
index a6c3e13..f896e58 100644
--- a/test/CodeGen/X86/dbg-value-location.ll
+++ b/test/CodeGen/X86/dbg-value-location.ll
@@ -47,28 +47,29 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"foo", metadata !"foo", metadata !"", i32 19510, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i64, i8*, i32)* @foo, null, null, null, i32 19510} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !26, metadata !1, metadata !"foo", metadata !"foo", metadata !"", i32 19510, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i64, i8*, i32)* @foo, null, null, null, i32 19510} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !26} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, metadata !27, i32 12, metadata !"clang version 2.9 (trunk 124753)", i1 true, metadata !"", i32 0, null, null, metadata !24, null,  null, null} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 786449, metadata !27, i32 12, metadata !"clang version 2.9 (trunk 124753)", i1 true, metadata !"", i32 0, metadata !28, metadata !28, metadata !24, null,  null, null} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !26, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"bar3", metadata !"bar3", metadata !"", i32 14827, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @bar3} ; [ DW_TAG_subprogram ]
-!7 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"bar2", metadata !"bar2", metadata !"", i32 15397, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @bar2} ; [ DW_TAG_subprogram ]
-!8 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"bar", metadata !"bar", metadata !"", i32 12382, metadata !9, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i32*)* @bar} ; [ DW_TAG_subprogram ]
-!9 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !10, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!5 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786478, metadata !26, metadata !1, metadata !"bar3", metadata !"bar3", metadata !"", i32 14827, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @bar3, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!7 = metadata !{i32 786478, metadata !26, metadata !1, metadata !"bar2", metadata !"bar2", metadata !"", i32 15397, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @bar2, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!8 = metadata !{i32 786478, metadata !26, metadata !1, metadata !"bar", metadata !"bar", metadata !"", i32 12382, metadata !9, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i32*)* @bar, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!9 = metadata !{i32 786453, metadata !26, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !10, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !10 = metadata !{metadata !11}
-!11 = metadata !{i32 786468, metadata !2, metadata !"unsigned char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ]
+!11 = metadata !{i32 786468, null, metadata !2, metadata !"unsigned char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ]
 !12 = metadata !{i32 786689, metadata !0, metadata !"var", metadata !1, i32 19509, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !13 = metadata !{i32 19509, i32 20, metadata !0, null}
 !14 = metadata !{i32 18091, i32 2, metadata !15, metadata !17}
-!15 = metadata !{i32 786443, metadata !1, metadata !16, i32 18086, i32 1, i32 748} ; [ DW_TAG_lexical_block ]
-!16 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"foo_bar", metadata !"foo_bar", metadata !"", i32 18086, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null} ; [ DW_TAG_subprogram ]
+!15 = metadata !{i32 786443, metadata !26, metadata !16, i32 18086, i32 1, i32 748} ; [ DW_TAG_lexical_block ]
+!16 = metadata !{i32 786478, metadata !26, metadata !1, metadata !"foo_bar", metadata !"foo_bar", metadata !"", i32 18086, metadata !3, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !17 = metadata !{i32 19514, i32 2, metadata !18, null}
-!18 = metadata !{i32 786443, metadata !1, metadata !0, i32 19510, i32 1, i32 99} ; [ DW_TAG_lexical_block ]
+!18 = metadata !{i32 786443, metadata !26, metadata !0, i32 19510, i32 1, i32 99} ; [ DW_TAG_lexical_block ]
 !22 = metadata !{i32 18094, i32 2, metadata !15, metadata !17}
 !23 = metadata !{i32 19524, i32 1, metadata !18, null}
 !24 = metadata !{metadata !0, metadata !6, metadata !7, metadata !8}
 !25 = metadata !{i32 786473, metadata !27} ; [ DW_TAG_file_type ]
 !26 = metadata !{metadata !"/tmp/f.c", metadata !"/tmp"}
 !27 = metadata !{metadata !"f.i", metadata !"/tmp"}
+!28 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/dbg-value-terminator.ll b/test/CodeGen/X86/dbg-value-terminator.ll
index ed0b212..e8d70de 100644
--- a/test/CodeGen/X86/dbg-value-terminator.ll
+++ b/test/CodeGen/X86/dbg-value-terminator.ll
@@ -5,8 +5,8 @@
 ; verify-machineinstrs should ensure that DEBUG_VALUEs go before the
 ; terminator.
 ;
-; CHECK: test:
-; CHECK: ##DEBUG_VALUE: :i
+; CHECK-LABEL: test:
+; CHECK: ##DEBUG_VALUE: i
 %a = type { i32, i32 }
 
 define hidden fastcc %a* @test() #1 {
@@ -112,19 +112,20 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, metadata !20, i32 12, metadata !"Apple clang version", i1 true, metadata !"", i32 0, null, null, metadata !18, null,  null, null} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, %a* ()* @test, null, null, metadata !19, i32 0} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786449, metadata !20, i32 12, metadata !"Apple clang version", i1 true, metadata !"", i32 0, metadata !21, metadata !21, metadata !18, null,  null, null} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 786478, metadata !20, metadata !2, metadata !"foo", metadata !"", metadata !"", i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, %a* ()* @test, null, null, metadata !19, i32 0} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !20} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!3 = metadata !{i32 786453, metadata !20, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 786468, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !6 = metadata !{i32 786689, metadata !1, metadata !"i", metadata !2, i32 16777218, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !7 = metadata !{i32 786689, metadata !1, metadata !"c", metadata !2, i32 33554434, metadata !8, i32 0, null} ; [ DW_TAG_arg_variable ]
-!8 = metadata !{i32 786447, metadata !0, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ]
-!9 = metadata !{i32 786468, metadata !0, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!8 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ]
+!9 = metadata !{i32 786468, null, metadata !0, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !10 = metadata !{i32 786688, metadata !11, metadata !"a", metadata !2, i32 3, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ]
 !11 = metadata !{i32 786443, metadata !20, metadata !1, i32 2, i32 25, i32 0} ; [ DW_TAG_lexical_block ]
 !12 = metadata !{i32 2, i32 13, metadata !1, null}
 !18 = metadata !{metadata !1}
 !19 = metadata !{metadata !6, metadata !7, metadata !10}
 !20 = metadata !{metadata !"a.c", metadata !"/private/tmp"}
+!21 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/divide-by-constant.ll b/test/CodeGen/X86/divide-by-constant.ll
index 9669d97..98ae1d5 100644
--- a/test/CodeGen/X86/divide-by-constant.ll
+++ b/test/CodeGen/X86/divide-by-constant.ll
@@ -6,7 +6,7 @@ define zeroext i16 @test1(i16 zeroext %x) nounwind {
 entry:
 	%div = udiv i16 %x, 33
 	ret i16 %div
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: imull	$63551, %eax, %eax
 ; CHECK-NEXT: shrl	$21, %eax
 ; CHECK-NEXT: ret
@@ -17,7 +17,7 @@ entry:
   %div = udiv i16 %c, 3
   ret i16 %div
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: imull	$43691, %eax, %eax
 ; CHECK-NEXT: shrl	$17, %eax
 ; CHECK-NEXT: ret
@@ -28,7 +28,7 @@ entry:
   %div = udiv i8 %c, 3
   ret i8 %div
 
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: movzbl  8(%esp), %eax
 ; CHECK-NEXT: imull	$171, %eax, %eax
 ; CHECK-NEXT: shrl	$9, %eax
@@ -39,14 +39,14 @@ define signext i16 @test4(i16 signext %x) nounwind {
 entry:
 	%div = sdiv i16 %x, 33		; <i32> [#uses=1]
 	ret i16 %div
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: imull	$1986, %eax, %
 }
 
 define i32 @test5(i32 %A) nounwind {
         %tmp1 = udiv i32 %A, 1577682821         ; <i32> [#uses=1]
         ret i32 %tmp1
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: movl	$365384439, %eax
 ; CHECK: mull	4(%esp)
 }
@@ -55,7 +55,7 @@ define signext i16 @test6(i16 signext %x) nounwind {
 entry:
   %div = sdiv i16 %x, 10
   ret i16 %div
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: imull $26215, %eax, %ecx
 ; CHECK: sarl $18, %ecx
 ; CHECK: shrl $15, %eax
@@ -64,7 +64,7 @@ entry:
 define i32 @test7(i32 %x) nounwind {
   %div = udiv i32 %x, 28
   ret i32 %div
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: shrl $2
 ; CHECK: movl $613566757
 ; CHECK: mull
@@ -76,7 +76,7 @@ define i32 @test7(i32 %x) nounwind {
 define i8 @test8(i8 %x) nounwind {
   %div = udiv i8 %x, 78
   ret i8 %div
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: shrb %
 ; CHECK: imull $211
 ; CHECK: shrl $13
@@ -86,7 +86,7 @@ define i8 @test8(i8 %x) nounwind {
 define i8 @test9(i8 %x) nounwind {
   %div = udiv i8 %x, 116
   ret i8 %div
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: shrb $2
 ; CHECK: imull $71
 ; CHECK: shrl $11
diff --git a/test/CodeGen/X86/dwarf-comp-dir.ll b/test/CodeGen/X86/dwarf-comp-dir.ll
index 3bc2957..b746dec 100644
--- a/test/CodeGen/X86/dwarf-comp-dir.ll
+++ b/test/CodeGen/X86/dwarf-comp-dir.ll
@@ -6,8 +6,7 @@ target triple = "x86_64-unknown-linux-gnu"
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 720913, metadata !4, i32 12, metadata !"clang version 3.1 (trunk 143523)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !1} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{metadata !2}
+!0 = metadata !{i32 720913, metadata !4, i32 12, metadata !"clang version 3.1 (trunk 143523)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !2, metadata !2, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !2 = metadata !{i32 0}
 !3 = metadata !{i32 786473, metadata !4} ; [ DW_TAG_file_type ]
 !4 = metadata !{metadata !"empty.c", metadata !"/home/nlewycky"}
diff --git a/test/CodeGen/X86/extended-fma-contraction.ll b/test/CodeGen/X86/extended-fma-contraction.ll
new file mode 100644
index 0000000..858eabc
--- /dev/null
+++ b/test/CodeGen/X86/extended-fma-contraction.ll
@@ -0,0 +1,22 @@
+; RUN: llc -march=x86 -mcpu=bdver2 -mattr=-fma -mtriple=x86_64-apple-darwin < %s | FileCheck %s
+; RUN: llc -march=x86 -mcpu=bdver2 -mattr=-fma,-fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA
+
+; CHECK-LABEL: fmafunc
+define <3 x float> @fmafunc(<3 x float> %a, <3 x float> %b, <3 x float> %c) {
+
+; CHECK-NOT: vmulps
+; CHECK-NOT: vaddps
+; CHECK: vfmaddps
+; CHECK-NOT: vmulps
+; CHECK-NOT: vaddps
+
+; CHECK-NOFMA-NOT: calll
+; CHECK-NOFMA: vmulps
+; CHECK-NOFMA: vaddps
+; CHECK-NOFMA-NOT: calll
+
+  %ret = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %a, <3 x float> %b, <3 x float> %c)
+  ret <3 x float> %ret
+}
+
+declare <3 x float> @llvm.fmuladd.v3f32(<3 x float>, <3 x float>, <3 x float>) nounwind readnone
diff --git a/test/CodeGen/X86/extractelement-load.ll b/test/CodeGen/X86/extractelement-load.ll
index 06d739c..cadc0fb 100644
--- a/test/CodeGen/X86/extractelement-load.ll
+++ b/test/CodeGen/X86/extractelement-load.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | FileCheck %s
 
 define i32 @t(<2 x i64>* %val) nounwind  {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK-NOT: movd
 ; CHECK: movl 8(
 ; CHECK-NEXT: ret
@@ -15,7 +15,7 @@ define i32 @t(<2 x i64>* %val) nounwind  {
 ; Case where extractelement of load ends up as undef.
 ; (Making sure this doesn't crash.)
 define i32 @t2(<8 x i32>* %xp) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: ret
   %x = load <8 x i32>* %xp
   %Shuff68 = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32
diff --git a/test/CodeGen/X86/fabs.ll b/test/CodeGen/X86/fabs.ll
index af1867f..e330ee7 100644
--- a/test/CodeGen/X86/fabs.ll
+++ b/test/CodeGen/X86/fabs.ll
@@ -7,9 +7,9 @@ declare float @fabsf(float)
 
 declare x86_fp80 @fabsl(x86_fp80)
 
-; CHECK:  test1:
-; UNSAFE: test1:
-; NOOPT:  test1:
+; CHECK-LABEL:  test1:
+; UNSAFE-LABEL: test1:
+; NOOPT-LABEL:  test1:
 define float @test1(float %X) {
         %Y = call float @fabsf(float %X) readnone
         ret float %Y
@@ -21,9 +21,9 @@ define float @test1(float %X) {
 ; UNSAFE-NOT: fabs
 ; NOOPT-NOT:  fabsf
 
-; CHECK:  test2:
-; UNSAFE: test2:
-; NOOPT:  test2:
+; CHECK-LABEL:  test2:
+; UNSAFE-LABEL: test2:
+; NOOPT-LABEL:  test2:
 define double @test2(double %X) {
         %Y = fcmp oge double %X, -0.0
         %Z = fsub double -0.0, %X
@@ -38,9 +38,9 @@ define double @test2(double %X) {
 
 ; UNSAFE-NOT: fabs
 
-; CHECK:  test3:
-; UNSAFE: test3:
-; NOOPT:  test3:
+; CHECK-LABEL:  test3:
+; UNSAFE-LABEL: test3:
+; NOOPT-LABEL:  test3:
 define x86_fp80 @test3(x86_fp80 %X) {
         %Y = call x86_fp80 @fabsl(x86_fp80 %X) readnone
         ret x86_fp80 %Y
diff --git a/test/CodeGen/X86/fast-cc-merge-stack-adj.ll b/test/CodeGen/X86/fast-cc-merge-stack-adj.ll
index 5121ed1..d9cfaa4 100644
--- a/test/CodeGen/X86/fast-cc-merge-stack-adj.ll
+++ b/test/CodeGen/X86/fast-cc-merge-stack-adj.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -mcpu=generic -march=x86 -x86-asm-syntax=intel | FileCheck %s
-; CHECK: add ESP, 8
+; CHECK: add esp, 8
 
 target triple = "i686-pc-linux-gnu"
 
diff --git a/test/CodeGen/X86/fast-cc-pass-in-regs.ll b/test/CodeGen/X86/fast-cc-pass-in-regs.ll
index b60b68b..ac898e6 100644
--- a/test/CodeGen/X86/fast-cc-pass-in-regs.ll
+++ b/test/CodeGen/X86/fast-cc-pass-in-regs.ll
@@ -5,25 +5,25 @@ declare x86_fastcallcc i64 @callee(i64 inreg)
 
 define i64 @caller() {
         %X = call x86_fastcallcc  i64 @callee( i64 4294967299 )          ; <i64> [#uses=1]
-; CHECK: mov{{.*}}EDX, 1
+; CHECK: mov{{.*}}edx, 1
         ret i64 %X
 }
 
 define x86_fastcallcc i64 @caller2(i64 inreg %X) {
         ret i64 %X
-; CHECK: mov{{.*}}EAX, ECX
+; CHECK: mov{{.*}}eax, ecx
 }
 
 declare x86_thiscallcc i64 @callee2(i32)
 
 define i64 @caller3() {
         %X = call x86_thiscallcc i64 @callee2( i32 3 )
-; CHECK: mov{{.*}}ECX, 3
+; CHECK: mov{{.*}}ecx, 3
         ret i64 %X
 }
 
 define x86_thiscallcc i32 @caller4(i32 %X) {
         ret i32 %X
-; CHECK: mov{{.*}}EAX, ECX
+; CHECK: mov{{.*}}eax, ecx
 }
 
diff --git a/test/CodeGen/X86/fast-isel-call.ll b/test/CodeGen/X86/fast-isel-call.ll
index 3159741..42d2b8b 100644
--- a/test/CodeGen/X86/fast-isel-call.ll
+++ b/test/CodeGen/X86/fast-isel-call.ll
@@ -10,7 +10,7 @@ BB1:
 	ret i32 1
 BB2:
 	ret i32 0
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: calll
 ; CHECK-NEXT: testb	$1
 }
@@ -21,7 +21,7 @@ declare void @foo2(%struct.s* byval)
 define void @test2(%struct.s* %d) nounwind {
   call void @foo2(%struct.s* byval %d )
   ret void
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movl	(%eax)
 ; CHECK: movl {{.*}}, (%esp)
 ; CHECK: movl	4(%eax)
@@ -35,7 +35,7 @@ declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
 define void @test3(i8* %a) {
   call void @llvm.memset.p0i8.i32(i8* %a, i8 0, i32 100, i32 1, i1 false)
   ret void
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK:   movl	{{.*}}, (%esp)
 ; CHECK:   movl	$0, 4(%esp)
 ; CHECK:   movl	$100, 8(%esp)
@@ -47,7 +47,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32,
 define void @test4(i8* %a, i8* %b) {
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a, i8* %b, i32 100, i32 1, i1 false)
   ret void
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK:   movl	{{.*}}, (%esp)
 ; CHECK:   movl	{{.*}}, 4(%esp)
 ; CHECK:   movl	$100, 8(%esp)
diff --git a/test/CodeGen/X86/fast-isel-divrem-x86-64.ll b/test/CodeGen/X86/fast-isel-divrem-x86-64.ll
index f2afaa0..0fd0561 100644
--- a/test/CodeGen/X86/fast-isel-divrem-x86-64.ll
+++ b/test/CodeGen/X86/fast-isel-divrem-x86-64.ll
@@ -6,7 +6,7 @@ entry:
   ret i64 %result
 }
 
-; CHECK: test_sdiv64:
+; CHECK-LABEL: test_sdiv64:
 ; CHECK: cqto
 ; CHECK: idivq
 
@@ -16,7 +16,7 @@ entry:
   ret i64 %result
 }
 
-; CHECK: test_srem64:
+; CHECK-LABEL: test_srem64:
 ; CHECK: cqto
 ; CHECK: idivq
 
@@ -26,7 +26,7 @@ entry:
   ret i64 %result
 }
 
-; CHECK: test_udiv64:
+; CHECK-LABEL: test_udiv64:
 ; CHECK: xorl
 ; CHECK: divq
 
@@ -36,6 +36,6 @@ entry:
   ret i64 %result
 }
 
-; CHECK: test_urem64:
+; CHECK-LABEL: test_urem64:
 ; CHECK: xorl
 ; CHECK: divq
diff --git a/test/CodeGen/X86/fast-isel-divrem.ll b/test/CodeGen/X86/fast-isel-divrem.ll
index 1a309a1..5828bec 100644
--- a/test/CodeGen/X86/fast-isel-divrem.ll
+++ b/test/CodeGen/X86/fast-isel-divrem.ll
@@ -7,7 +7,7 @@ entry:
   ret i8 %result
 }
 
-; CHECK: test_sdiv8:
+; CHECK-LABEL: test_sdiv8:
 ; CHECK: movsbw
 ; CHECK: idivb
 
@@ -17,7 +17,7 @@ entry:
   ret i8 %result
 }
 
-; CHECK: test_srem8:
+; CHECK-LABEL: test_srem8:
 ; CHECK: movsbw
 ; CHECK: idivb
 
@@ -27,7 +27,7 @@ entry:
   ret i8 %result
 }
 
-; CHECK: test_udiv8:
+; CHECK-LABEL: test_udiv8:
 ; CHECK: movzbw
 ; CHECK: divb
 
@@ -37,7 +37,7 @@ entry:
   ret i8 %result
 }
 
-; CHECK: test_urem8:
+; CHECK-LABEL: test_urem8:
 ; CHECK: movzbw
 ; CHECK: divb
 
@@ -47,7 +47,7 @@ entry:
   ret i16 %result
 }
 
-; CHECK: test_sdiv16:
+; CHECK-LABEL: test_sdiv16:
 ; CHECK: cwtd
 ; CHECK: idivw
 
@@ -57,7 +57,7 @@ entry:
   ret i16 %result
 }
 
-; CHECK: test_srem16:
+; CHECK-LABEL: test_srem16:
 ; CHECK: cwtd
 ; CHECK: idivw
 
@@ -67,7 +67,7 @@ entry:
   ret i16 %result
 }
 
-; CHECK: test_udiv16:
+; CHECK-LABEL: test_udiv16:
 ; CHECK: xorl
 ; CHECK: divw
 
@@ -77,7 +77,7 @@ entry:
   ret i16 %result
 }
 
-; CHECK: test_urem16:
+; CHECK-LABEL: test_urem16:
 ; CHECK: xorl
 ; CHECK: divw
 
@@ -87,7 +87,7 @@ entry:
   ret i32 %result
 }
 
-; CHECK: test_sdiv32:
+; CHECK-LABEL: test_sdiv32:
 ; CHECK: cltd
 ; CHECK: idivl
 
@@ -97,7 +97,7 @@ entry:
   ret i32 %result
 }
 
-; CHECK: test_srem32:
+; CHECK-LABEL: test_srem32:
 ; CHECK: cltd
 ; CHECK: idivl
 
@@ -107,7 +107,7 @@ entry:
   ret i32 %result
 }
 
-; CHECK: test_udiv32:
+; CHECK-LABEL: test_udiv32:
 ; CHECK: xorl
 ; CHECK: divl
 
@@ -117,6 +117,6 @@ entry:
   ret i32 %result
 }
 
-; CHECK: test_urem32:
+; CHECK-LABEL: test_urem32:
 ; CHECK: xorl
 ; CHECK: divl
diff --git a/test/CodeGen/X86/fast-isel-extract.ll b/test/CodeGen/X86/fast-isel-extract.ll
index f63396e..3a4b2a6 100644
--- a/test/CodeGen/X86/fast-isel-extract.ll
+++ b/test/CodeGen/X86/fast-isel-extract.ll
@@ -10,7 +10,7 @@ define void @test1(i64*) nounwind ssp {
   %4 = add i64 %3, 10
   store i64 %4, i64* %0
   ret void
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: callq _f
 ; CHECK-NEXT: addq	$10, %rax
 }
@@ -21,7 +21,7 @@ define void @test2(i64*) nounwind ssp {
   %4 = add i64 %3, 10
   store i64 %4, i64* %0
   ret void
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: callq _f
 ; CHECK-NEXT: addq	$10, %rdx
 }
diff --git a/test/CodeGen/X86/fast-isel-fneg.ll b/test/CodeGen/X86/fast-isel-fneg.ll
index 67fdad2..8b38587 100644
--- a/test/CodeGen/X86/fast-isel-fneg.ll
+++ b/test/CodeGen/X86/fast-isel-fneg.ll
@@ -5,14 +5,14 @@
 ; SSE2: xor
 ; SSE2-NOT: xor
 
-; CHECK: doo:
+; CHECK-LABEL: doo:
 ; CHECK: xor
 define double @doo(double %x) nounwind {
   %y = fsub double -0.0, %x
   ret double %y
 }
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: xor
 define float @foo(float %x) nounwind {
   %y = fsub float -0.0, %x
diff --git a/test/CodeGen/X86/fast-isel-gep.ll b/test/CodeGen/X86/fast-isel-gep.ll
index f0375f8..4e47c74 100644
--- a/test/CodeGen/X86/fast-isel-gep.ll
+++ b/test/CodeGen/X86/fast-isel-gep.ll
@@ -9,11 +9,11 @@ define i32 @test1(i32 %t3, i32* %t1) nounwind {
        %t9 = getelementptr i32* %t1, i32 %t3           ; <i32*> [#uses=1]
        %t15 = load i32* %t9            ; <i32> [#uses=1]
        ret i32 %t15
-; X32: test1:
+; X32-LABEL: test1:
 ; X32:  	movl	(%eax,%ecx,4), %eax
 ; X32:  	ret
 
-; X64: test1:
+; X64-LABEL: test1:
 ; X64:  	movslq	%e[[A0:di|cx]], %rax
 ; X64:  	movl	(%r[[A1:si|dx]],%rax,4), %eax
 ; X64:  	ret
@@ -23,11 +23,11 @@ define i32 @test2(i64 %t3, i32* %t1) nounwind {
        %t9 = getelementptr i32* %t1, i64 %t3           ; <i32*> [#uses=1]
        %t15 = load i32* %t9            ; <i32> [#uses=1]
        ret i32 %t15
-; X32: test2:
+; X32-LABEL: test2:
 ; X32:  	movl	(%edx,%ecx,4), %e
 ; X32:  	ret
 
-; X64: test2:
+; X64-LABEL: test2:
 ; X64:  	movl	(%r[[A1]],%r[[A0]],4), %eax
 ; X64:  	ret
 }
@@ -42,12 +42,12 @@ entry:
   ret i8 %B
   
   
-; X32: test3:
+; X32-LABEL: test3:
 ; X32:  	movl	4(%esp), %eax
 ; X32:  	movb	-2(%eax), %al
 ; X32:  	ret
 
-; X64: test3:
+; X64-LABEL: test3:
 ; X64:  	movb	-2(%r[[A0]]), %al
 ; X64:  	ret
 
@@ -66,9 +66,9 @@ entry:
   %tmp2 = load double* %arrayidx                  ; <double> [#uses=1]
   ret double %tmp2
 
-; X32: test4:
+; X32-LABEL: test4:
 ; X32: 128(%e{{.*}},%e{{.*}},8)
-; X64: test4:
+; X64-LABEL: test4:
 ; X64: 128(%r{{.*}},%r{{.*}},8)
 }
 
@@ -80,7 +80,7 @@ define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind {
   %v10 = load i64* %v9
   %v11 = add i64 %B, %v10
   ret i64 %v11
-; X64: test5:
+; X64-LABEL: test5:
 ; X64: movslq	%e[[A1]], %rax
 ; X64-NEXT: (%r[[A0]],%rax),
 ; X64: ret
@@ -113,7 +113,7 @@ declare i8* @_ZNK18G__FastAllocString4dataEv() nounwind
 ; PR10605 / rdar://9930964 - Don't fold loads incorrectly.  The load should
 ; happen before the store.  
 define i32 @test7({i32,i32,i32}* %tmp1, i32 %tmp71, i32 %tmp63) nounwind  {
-; X64: test7:
+; X64-LABEL: test7:
 ; X64:    movl	8({{%rdi|%rcx}}), %eax
 ; X64:     movl	$4, 8({{%rdi|%rcx}})
 
diff --git a/test/CodeGen/X86/fast-isel-i1.ll b/test/CodeGen/X86/fast-isel-i1.ll
index bea18a1..9c042d3 100644
--- a/test/CodeGen/X86/fast-isel-i1.ll
+++ b/test/CodeGen/X86/fast-isel-i1.ll
@@ -4,7 +4,7 @@
 declare i32 @test1a(i32)
 
 define i32 @test1(i32 %x) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: andb $1, %
 	%y = add i32 %x, -3
 	%t = call i32 @test1a(i32 %y)
@@ -23,7 +23,7 @@ exit:		; preds = %next
 
 define void @test2(i8* %a) nounwind {
 entry:
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movb {{.*}} %al
 ; CHECK-NEXT: xorb $1, %al
 ; CHECK-NEXT: testb $1
diff --git a/test/CodeGen/X86/fast-isel-mem.ll b/test/CodeGen/X86/fast-isel-mem.ll
index 52b1e85..7fcef03 100644
--- a/test/CodeGen/X86/fast-isel-mem.ll
+++ b/test/CodeGen/X86/fast-isel-mem.ll
@@ -12,7 +12,7 @@ entry:
         store i32 %2, i32* @src
 	ret i32 %2
 ; This should fold one of the loads into the add.
-; CHECK: loadgv:
+; CHECK-LABEL: loadgv:
 ; CHECK: 	movl	L_src$non_lazy_ptr, %ecx
 ; CHECK: 	movl	(%ecx), %eax
 ; CHECK: 	addl	(%ecx), %eax
diff --git a/test/CodeGen/X86/fast-isel-ret-ext.ll b/test/CodeGen/X86/fast-isel-ret-ext.ll
index fd768cb..0370d99 100644
--- a/test/CodeGen/X86/fast-isel-ret-ext.ll
+++ b/test/CodeGen/X86/fast-isel-ret-ext.ll
@@ -4,35 +4,35 @@
 define zeroext i8 @test1(i32 %y) nounwind {
   %conv = trunc i32 %y to i8
   ret i8 %conv
-  ; CHECK: test1:
+  ; CHECK-LABEL: test1:
   ; CHECK: movzbl {{.*}}, %eax
 }
 
 define signext i8 @test2(i32 %y) nounwind {
   %conv = trunc i32 %y to i8
   ret i8 %conv
-  ; CHECK: test2:
+  ; CHECK-LABEL: test2:
   ; CHECK: movsbl {{.*}}, %eax
 }
 
 define zeroext i16 @test3(i32 %y) nounwind {
   %conv = trunc i32 %y to i16
   ret i16 %conv
-  ; CHECK: test3:
+  ; CHECK-LABEL: test3:
   ; CHECK: movzwl {{.*}}, %eax
 }
 
 define signext i16 @test4(i32 %y) nounwind {
   %conv = trunc i32 %y to i16
   ret i16 %conv
-  ; CHECK: test4:
-  ; CHECK: movswl {{.*}}, %eax
+  ; CHECK-LABEL: test4:
+  ; CHECK: {{(movswl.%.x, %eax|cwtl)}}
 }
 
 define zeroext i1 @test5(i32 %y) nounwind {
   %conv = trunc i32 %y to i1
   ret i1 %conv
-  ; CHECK: test5:
+  ; CHECK-LABEL: test5:
   ; CHECK: andb $1
   ; CHECK: movzbl {{.*}}, %eax
 }
diff --git a/test/CodeGen/X86/fast-isel-store.ll b/test/CodeGen/X86/fast-isel-store.ll
new file mode 100644
index 0000000..3d2a46c
--- /dev/null
+++ b/test/CodeGen/X86/fast-isel-store.ll
@@ -0,0 +1,64 @@
+; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort -mattr=+sse2 < %s | FileCheck %s
+; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort -mattr=+sse2 < %s | FileCheck %s
+
+define i32 @test_store_32(i32* nocapture %addr, i32 %value) {
+entry:
+  store i32 %value, i32* %addr, align 1
+  ret i32 %value
+}
+
+; CHECK: ret
+
+define i16 @test_store_16(i16* nocapture %addr, i16 %value) {
+entry:
+  store i16 %value, i16* %addr, align 1
+  ret i16 %value
+}
+
+; CHECK: ret
+
+define <4 x i32> @test_store_4xi32(<4 x i32>* nocapture %addr, <4 x i32> %value, <4 x i32> %value2) {
+; CHECK: movdqu
+; CHECK: ret
+  %foo = add <4 x i32> %value, %value2 ; to force integer type on store
+  store <4 x i32> %foo, <4 x i32>* %addr, align 1
+  ret <4 x i32> %foo
+}
+
+define <4 x i32> @test_store_4xi32_aligned(<4 x i32>* nocapture %addr, <4 x i32> %value, <4 x i32> %value2) {
+; CHECK: movdqa
+; CHECK: ret
+  %foo = add <4 x i32> %value, %value2 ; to force integer type on store
+  store <4 x i32> %foo, <4 x i32>* %addr, align 16
+  ret <4 x i32> %foo
+}
+
+define <4 x float> @test_store_4xf32(<4 x float>* nocapture %addr, <4 x float> %value) {
+; CHECK: movups
+; CHECK: ret
+  store <4 x float> %value, <4 x float>* %addr, align 1
+  ret <4 x float> %value
+}
+
+define <4 x float> @test_store_4xf32_aligned(<4 x float>* nocapture %addr, <4 x float> %value) {
+; CHECK: movaps
+; CHECK: ret
+  store <4 x float> %value, <4 x float>* %addr, align 16
+  ret <4 x float> %value
+}
+
+define <2 x double> @test_store_2xf64(<2 x double>* nocapture %addr, <2 x double> %value, <2 x double> %value2) {
+; CHECK: movupd
+; CHECK: ret
+  %foo = fadd <2 x double> %value, %value2 ; to force dobule type on store
+  store <2 x double> %foo, <2 x double>* %addr, align 1
+  ret <2 x double> %foo
+}
+
+define <2 x double> @test_store_2xf64_aligned(<2 x double>* nocapture %addr, <2 x double> %value, <2 x double> %value2) {
+; CHECK: movapd
+; CHECK: ret
+  %foo = fadd <2 x double> %value, %value2 ; to force dobule type on store
+  store <2 x double> %foo, <2 x double>* %addr, align 16
+  ret <2 x double> %foo
+}
diff --git a/test/CodeGen/X86/fast-isel-tls.ll b/test/CodeGen/X86/fast-isel-tls.ll
index 0963c52..f71abd2 100644
--- a/test/CodeGen/X86/fast-isel-tls.ll
+++ b/test/CodeGen/X86/fast-isel-tls.ll
@@ -9,7 +9,7 @@ entry:
           ret i32 %s
 }
 
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: leal	v@TLSGD
 ; CHECK: __tls_get_addr
 
@@ -21,6 +21,6 @@ entry:
           ret i32 %s
 }
 
-; CHECK: f_alias:
+; CHECK-LABEL: f_alias:
 ; CHECK: leal	v@TLSGD
 ; CHECK: __tls_get_addr
diff --git a/test/CodeGen/X86/fast-isel-unaligned-store.ll b/test/CodeGen/X86/fast-isel-unaligned-store.ll
deleted file mode 100644
index 7ce7f67..0000000
--- a/test/CodeGen/X86/fast-isel-unaligned-store.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s
-; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s
-
-define i32 @test_store_32(i32* nocapture %addr, i32 %value) {
-entry:
-  store i32 %value, i32* %addr, align 1
-  ret i32 %value
-}
-
-; CHECK: ret
-
-define i16 @test_store_16(i16* nocapture %addr, i16 %value) {
-entry:
-  store i16 %value, i16* %addr, align 1
-  ret i16 %value
-}
-
-; CHECK: ret
diff --git a/test/CodeGen/X86/fast-isel-x86-64.ll b/test/CodeGen/X86/fast-isel-x86-64.ll
index ad1520e..f7d2750 100644
--- a/test/CodeGen/X86/fast-isel-x86-64.ll
+++ b/test/CodeGen/X86/fast-isel-x86-64.ll
@@ -11,7 +11,7 @@ define i32 @test1(i32 %i) nounwind ssp {
   ret i32 %and
 }
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: andl	$8, 
 
 
@@ -29,7 +29,7 @@ if.then:                                          ; preds = %entry
 
 if.end:                                           ; preds = %if.then, %entry
   ret void
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movq	%rdi, -8(%rsp)
 ; CHECK: cmpq	$42, -8(%rsp)
 }
@@ -41,7 +41,7 @@ if.end:                                           ; preds = %if.then, %entry
 define i64 @test3() nounwind {
   %A = ptrtoint i32* @G to i64
   ret i64 %A
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: movq _G@GOTPCREL(%rip), %rax
 ; CHECK-NEXT: ret
 }
@@ -57,7 +57,7 @@ define i32 @test4(i64 %idxprom9) nounwind {
   %conv = zext i8 %tmp11 to i32
   ret i32 %conv
 
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: movq	_rtx_length@GOTPCREL(%rip), %rax
 ; CHECK-NEXT: movzbl	(%rax,%rdi), %eax
 ; CHECK-NEXT: ret
@@ -70,7 +70,7 @@ define void @test5(i32 %x, i32* %p) nounwind {
   store i32 %y, i32* %p
   ret void
 
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: movl	$50000, %ecx
 ; CHECK: sarl	%cl, %edi
 ; CHECK: ret
@@ -82,7 +82,7 @@ entry:
   %mul = mul nsw i64 %x, 8
   ret i64 %mul
 
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: shlq	$3, %rdi
 }
 
@@ -90,7 +90,7 @@ define i32 @test7(i32 %x) nounwind ssp {
 entry:
   %mul = mul nsw i32 %x, 8
   ret i32 %mul
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: shll	$3, %edi
 }
 
@@ -101,7 +101,7 @@ entry:
   %add = add nsw i64 %x, 7
   ret i64 %add
 
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: addq	$7, %rdi
 }
 
@@ -109,7 +109,7 @@ define i64 @test9(i64 %x) nounwind ssp {
 entry:
   %add = mul nsw i64 %x, 7
   ret i64 %add
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: imulq	$7, %rdi, %rax
 }
 
@@ -117,14 +117,14 @@ entry:
 define i32 @test10(i32 %X) nounwind {
   %Y = udiv i32 %X, 8
   ret i32 %Y
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: shrl	$3, 
 }
 
 define i32 @test11(i32 %X) nounwind {
   %Y = sdiv exact i32 %X, 8
   ret i32 %Y
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK: sarl	$3, 
 }
 
@@ -141,7 +141,7 @@ if.then:                                          ; preds = %entry
 
 if.end:                                           ; preds = %if.then, %entry
   ret void
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK: testb	$1,
 ; CHECK-NEXT: je L
 ; CHECK-NEXT: movl $0, %edi
@@ -153,7 +153,7 @@ declare void @test13f(i1 %X)
 define void @test13() nounwind {
   call void @test13f(i1 0)
   ret void
-; CHECK: test13:
+; CHECK-LABEL: test13:
 ; CHECK: movl $0, %edi
 ; CHECK-NEXT: callq
 }
@@ -166,7 +166,7 @@ entry:
   %tobool = trunc i8 %tmp to i1
   call void @test13f(i1 zeroext %tobool) noredzone
   ret void
-; CHECK: test14:
+; CHECK-LABEL: test14:
 ; CHECK: andb	$1, 
 ; CHECK: callq
 }
@@ -177,7 +177,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1)
 define void @test15(i8* %a, i8* %b) nounwind {
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 4, i32 4, i1 false)
   ret void
-; CHECK: test15:
+; CHECK-LABEL: test15:
 ; CHECK-NEXT: movl	(%rsi), %eax
 ; CHECK-NEXT: movl	%eax, (%rdi)
 ; CHECK-NEXT: ret
@@ -186,7 +186,7 @@ define void @test15(i8* %a, i8* %b) nounwind {
 ; Handling for varargs calls
 declare void @test16callee(...) nounwind
 define void @test16() nounwind {
-; CHECK: test16:
+; CHECK-LABEL: test16:
 ; CHECK: movl $1, %edi
 ; CHECK: movb $0, %al
 ; CHECK: callq _test16callee
@@ -224,7 +224,7 @@ if.then:                                          ; preds = %entry
 
 if.else:                                          ; preds = %entry
   ret i32 2
-; CHECK: test17:
+; CHECK-LABEL: test17:
 ; CHECK: movl	(%rdi), %eax
 ; CHECK: callq _foo
 ; CHECK: cmpl	$5, %eax
@@ -235,7 +235,7 @@ if.else:                                          ; preds = %entry
 define void @test18(float* %p1) {
   store float 0.0, float* %p1
   ret void
-; CHECK: test18:
+; CHECK-LABEL: test18:
 ; CHECK: xorps
 }
 
@@ -243,7 +243,7 @@ define void @test18(float* %p1) {
 define void @test19(double* %p1) {
   store double 0.0, double* %p1
   ret void
-; CHECK: test19:
+; CHECK-LABEL: test19:
 ; CHECK: xorps
 }
 
@@ -254,7 +254,7 @@ entry:
   %tmp = alloca %struct.a, align 8
   call void @test20sret(%struct.a* sret %tmp)
   ret void
-; CHECK: test20:
+; CHECK-LABEL: test20:
 ; CHECK: leaq (%rsp), %rdi
 ; CHECK: callq _test20sret
 }
@@ -264,7 +264,7 @@ declare void @test20sret(%struct.a* sret)
 define void @test21(double* %p1) {
   store double -0.0, double* %p1
   ret void
-; CHECK: test21:
+; CHECK-LABEL: test21:
 ; CHECK-NOT: xor
 ; CHECK: movsd	LCPI
 }
@@ -279,7 +279,7 @@ entry:
   call void @foo22(i32 2)
   call void @foo22(i32 3)
   ret void
-; CHECK: test22:
+; CHECK-LABEL: test22:
 ; CHECK: movl	$0, %edi
 ; CHECK: callq	_foo22
 ; CHECK: movl	$1, %edi
@@ -297,7 +297,7 @@ define void @test23(i8* noalias sret %result) {
   %a = alloca i8
   %b = call i8* @foo23()
   ret void
-; CHECK: test23:
+; CHECK-LABEL: test23:
 ; CHECK: call
 ; CHECK: movq  %rdi, %rax
 ; CHECK: ret
diff --git a/test/CodeGen/X86/fast-isel-x86.ll b/test/CodeGen/X86/fast-isel-x86.ll
index 4caa3a0..ba86e88 100644
--- a/test/CodeGen/X86/fast-isel-x86.ll
+++ b/test/CodeGen/X86/fast-isel-x86.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -fast-isel -O0 -mcpu=generic -mtriple=i386-apple-darwin10 -relocation-model=pic < %s | FileCheck %s
 
 ; This should use flds to set the return value.
-; CHECK: test0:
+; CHECK-LABEL: test0:
 ; CHECK: flds
 ; CHECK: ret
 @G = external global float
@@ -11,7 +11,7 @@ define float @test0() nounwind {
 }
 
 ; This should pop 4 bytes on return.
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: ret $4
 define void @test1({i32, i32, i32, i32}* sret %p) nounwind {
   store {i32, i32, i32, i32} zeroinitializer, {i32, i32, i32, i32}* %p
@@ -19,7 +19,7 @@ define void @test1({i32, i32, i32, i32}* sret %p) nounwind {
 }
 
 ; Properly initialize the pic base.
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK-NOT: HHH
 ; CHECK: call{{.*}}L2$pb
 ; CHECK-NEXT: L2$pb:
@@ -39,7 +39,7 @@ entry:
   %tmp = alloca %struct.a, align 8
   call void @test3sret(%struct.a* sret %tmp)
   ret void
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: subl $44
 ; CHECK: leal 16(%esp)
 ; CHECK: calll _test3sret
@@ -53,7 +53,7 @@ entry:
   %tmp = alloca %struct.a, align 8
   call fastcc void @test4fastccsret(%struct.a* sret %tmp)
   ret void
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: subl $28
 ; CHECK: leal (%esp), %ecx
 ; CHECK: calll _test4fastccsret
diff --git a/test/CodeGen/X86/floor-soft-float.ll b/test/CodeGen/X86/floor-soft-float.ll
new file mode 100644
index 0000000..8e7ee09
--- /dev/null
+++ b/test/CodeGen/X86/floor-soft-float.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx -soft-float=0 | FileCheck %s --check-prefix=CHECK-HARD-FLOAT
+; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx -soft-float=1 | FileCheck %s --check-prefix=CHECK-SOFT-FLOAT
+
+target triple = "x86_64-unknown-linux-gnu"
+
+declare float @llvm.floor.f32(float)
+
+; CHECK-SOFT-FLOAT: callq floorf
+; CHECK-HARD-FLOAT: roundss $1, %xmm0, %xmm0
+define float @myfloor(float %a) {
+  %val = tail call float @llvm.floor.f32(float %a)
+  ret float %val
+}
diff --git a/test/CodeGen/X86/fma_patterns.ll b/test/CodeGen/X86/fma_patterns.ll
index 6d98d59..cfb598d 100644
--- a/test/CodeGen/X86/fma_patterns.ll
+++ b/test/CodeGen/X86/fma_patterns.ll
@@ -182,11 +182,11 @@ define float @test_x86_fnmsub_ss(float %a0, float %a1, float %a2) {
   ret float %res
 }
 
-; CHECK: test_x86_fmadd_ps
+; CHECK: test_x86_fmadd_ps_load
 ; CHECK: vmovaps         (%rdi), %xmm2
 ; CHECK: vfmadd213ps     %xmm1, %xmm0, %xmm2
 ; CHECK: ret
-; CHECK_FMA4: test_x86_fmadd_ps
+; CHECK_FMA4: test_x86_fmadd_ps_load
 ; CHECK_FMA4: vfmaddps     %xmm1, (%rdi), %xmm0, %xmm0
 ; CHECK_FMA4: ret
 define <4 x float> @test_x86_fmadd_ps_load(<4 x float>* %a0, <4 x float> %a1, <4 x float> %a2) {
@@ -196,11 +196,11 @@ define <4 x float> @test_x86_fmadd_ps_load(<4 x float>* %a0, <4 x float> %a1, <4
   ret <4 x float> %res
 }
 
-; CHECK: test_x86_fmsub_ps
+; CHECK: test_x86_fmsub_ps_load
 ; CHECK: vmovaps         (%rdi), %xmm2
 ; CHECK: fmsub213ps     %xmm1, %xmm0, %xmm2
 ; CHECK: ret
-; CHECK_FMA4: test_x86_fmsub_ps
+; CHECK_FMA4: test_x86_fmsub_ps_load
 ; CHECK_FMA4: vfmsubps     %xmm1, (%rdi), %xmm0, %xmm0
 ; CHECK_FMA4: ret
 define <4 x float> @test_x86_fmsub_ps_load(<4 x float>* %a0, <4 x float> %a1, <4 x float> %a2) {
diff --git a/test/CodeGen/X86/fma_patterns_wide.ll b/test/CodeGen/X86/fma_patterns_wide.ll
new file mode 100644
index 0000000..04db2d7
--- /dev/null
+++ b/test/CodeGen/X86/fma_patterns_wide.ll
@@ -0,0 +1,84 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=avx2,+fma -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -mattr=-fma4 -fp-contract=fast | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 -fp-contract=fast | FileCheck %s --check-prefix=CHECK_FMA4
+
+; CHECK-LABEL: test_x86_fmadd_ps_y_wide
+; CHECK: vfmadd213ps
+; CHECK: vfmadd213ps
+; CHECK: ret
+; CHECK_FMA4-LABEL: test_x86_fmadd_ps_y_wide
+; CHECK_FMA4: vfmaddps
+; CHECK_FMA4: vfmaddps
+; CHECK_FMA4: ret
+define <16 x float> @test_x86_fmadd_ps_y_wide(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
+  %x = fmul <16 x float> %a0, %a1
+  %res = fadd <16 x float> %x, %a2
+  ret <16 x float> %res
+}
+
+; CHECK-LABEL: test_x86_fmsub_ps_y_wide
+; CHECK: vfmsub213ps
+; CHECK: vfmsub213ps
+; CHECK: ret
+; CHECK_FMA4-LABEL: test_x86_fmsub_ps_y_wide
+; CHECK_FMA4: vfmsubps
+; CHECK_FMA4: vfmsubps
+; CHECK_FMA4: ret
+define <16 x float> @test_x86_fmsub_ps_y_wide(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
+  %x = fmul <16 x float> %a0, %a1
+  %res = fsub <16 x float> %x, %a2
+  ret <16 x float> %res
+}
+
+; CHECK-LABEL: test_x86_fnmadd_ps_y_wide
+; CHECK: vfnmadd213ps
+; CHECK: vfnmadd213ps
+; CHECK: ret
+; CHECK_FMA4-LABEL: test_x86_fnmadd_ps_y_wide
+; CHECK_FMA4: vfnmaddps
+; CHECK_FMA4: vfnmaddps
+; CHECK_FMA4: ret
+define <16 x float> @test_x86_fnmadd_ps_y_wide(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
+  %x = fmul <16 x float> %a0, %a1
+  %res = fsub <16 x float> %a2, %x
+  ret <16 x float> %res
+}
+
+; CHECK-LABEL: test_x86_fnmsub_ps_y_wide
+; CHECK: vfnmsub213ps
+; CHECK: vfnmsub213ps
+; CHECK: ret
+define <16 x float> @test_x86_fnmsub_ps_y_wide(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
+  %x = fmul <16 x float> %a0, %a1
+  %y = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %x
+  %res = fsub <16 x float> %y, %a2
+  ret <16 x float> %res
+}
+
+; CHECK-LABEL: test_x86_fmadd_pd_y_wide
+; CHECK: vfmadd213pd
+; CHECK: vfmadd213pd
+; CHECK: ret
+; CHECK_FMA4-LABEL: test_x86_fmadd_pd_y_wide
+; CHECK_FMA4: vfmaddpd
+; CHECK_FMA4: vfmaddpd
+; CHECK_FMA4: ret
+define <8 x double> @test_x86_fmadd_pd_y_wide(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
+  %x = fmul <8 x double> %a0, %a1
+  %res = fadd <8 x double> %x, %a2
+  ret <8 x double> %res
+}
+
+; CHECK-LABEL: test_x86_fmsub_pd_y_wide
+; CHECK: vfmsub213pd
+; CHECK: vfmsub213pd
+; CHECK: ret
+; CHECK_FMA4-LABEL: test_x86_fmsub_pd_y_wide
+; CHECK_FMA4: vfmsubpd
+; CHECK_FMA4: vfmsubpd
+; CHECK_FMA4: ret
+define <8 x double> @test_x86_fmsub_pd_y_wide(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
+  %x = fmul <8 x double> %a0, %a1
+  %res = fsub <8 x double> %x, %a2
+  ret <8 x double> %res
+}
diff --git a/test/CodeGen/X86/fold-add.ll b/test/CodeGen/X86/fold-add.ll
index 63e7d36..0b27387 100644
--- a/test/CodeGen/X86/fold-add.ll
+++ b/test/CodeGen/X86/fold-add.ll
@@ -7,7 +7,7 @@ target triple = "x86_64-apple-darwin9.6"
 @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32)* @longest_match to i8*)]		; <[1 x i8*]*> [#uses=0]
 
 define fastcc i32 @longest_match(i32 %cur_match) nounwind {
-; CHECK: longest_match:
+; CHECK-LABEL: longest_match:
 ; CHECK-NOT: ret
 ; CHECK: cmpb $0, (%r{{.*}},%r{{.*}})
 ; CHECK: ret
diff --git a/test/CodeGen/X86/fold-and-shift.ll b/test/CodeGen/X86/fold-and-shift.ll
index 93baa0e..a5eb8b5 100644
--- a/test/CodeGen/X86/fold-and-shift.ll
+++ b/test/CodeGen/X86/fold-and-shift.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86 | FileCheck %s
 
 define i32 @t1(i8* %X, i32 %i) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK-NOT: and
 ; CHECK: movzbl
 ; CHECK: movl (%{{...}},%{{...}},4),
@@ -17,7 +17,7 @@ entry:
 }
 
 define i32 @t2(i16* %X, i32 %i) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK-NOT: and
 ; CHECK: movzwl
 ; CHECK: movl (%{{...}},%{{...}},4),
@@ -39,7 +39,7 @@ define i32 @t3(i16* %i.ptr, i32* %arr) {
 ; To make matters worse, because of the two-phase zext of %i and their reuse in
 ; the function, the DAG can get confusing trying to re-use both of them and
 ; prevent easy analysis of the mask in order to match this.
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK-NOT: and
 ; CHECK: shrl
 ; CHECK: addl (%{{...}},%{{...}},4),
@@ -58,7 +58,7 @@ entry:
 define i32 @t4(i16* %i.ptr, i32* %arr) {
 ; A version of @t3 that has more zero extends and more re-use of intermediate
 ; values. This exercise slightly different bits of canonicalization.
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK-NOT: and
 ; CHECK: shrl
 ; CHECK: addl (%{{...}},%{{...}},4),
diff --git a/test/CodeGen/X86/fold-load-vec.ll b/test/CodeGen/X86/fold-load-vec.ll
index c1756d5..47100be 100644
--- a/test/CodeGen/X86/fold-load-vec.ll
+++ b/test/CodeGen/X86/fold-load-vec.ll
@@ -5,8 +5,8 @@
 ; loads from m32.
 define void @sample_test(<4 x float>* %source, <2 x float>* %dest) nounwind {
 ; CHECK: sample_test
-; CHECK: movss
-; CHECK: pshufd
+; CHECK: movaps
+; CHECK: insertps
 entry:
   %source.addr = alloca <4 x float>*, align 8
   %dest.addr = alloca <2 x float>*, align 8
diff --git a/test/CodeGen/X86/fold-load.ll b/test/CodeGen/X86/fold-load.ll
index d836665..495acd9 100644
--- a/test/CodeGen/X86/fold-load.ll
+++ b/test/CodeGen/X86/fold-load.ll
@@ -39,7 +39,7 @@ L:
   store i16 %A, i16* %Q
   ret i32 %D
   
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: 	movl	4(%esp), %eax
 ; CHECK-NEXT:	movzwl	(%eax), %ecx
 
@@ -48,7 +48,7 @@ L:
 ; rdar://10554090
 ; xor in exit block will be CSE'ed and load will be folded to xor in entry.
 define i1 @test3(i32* %P, i32* %Q) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: movl 8(%esp), %eax
 ; CHECK: xorl (%eax),
 ; CHECK: j
diff --git a/test/CodeGen/X86/fold-pcmpeqd-1.ll b/test/CodeGen/X86/fold-pcmpeqd-1.ll
index d850630..663e2af 100644
--- a/test/CodeGen/X86/fold-pcmpeqd-1.ll
+++ b/test/CodeGen/X86/fold-pcmpeqd-1.ll
@@ -2,14 +2,14 @@
 
 define <2 x double> @foo() nounwind {
   ret <2 x double> bitcast (<2 x i64><i64 -1, i64 -1> to <2 x double>)
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: pcmpeqd %xmm0, %xmm0
 ; CHECK-NOT: %xmm
 ; CHECK: ret
 }
 define <2 x double> @bar() nounwind {
   ret <2 x double> bitcast (<2 x i64><i64 0, i64 0> to <2 x double>)
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: xorps %xmm0, %xmm0
 ; CHECK-NOT: %xmm
 ; CHECK: ret
diff --git a/test/CodeGen/X86/fold-pcmpeqd-2.ll b/test/CodeGen/X86/fold-pcmpeqd-2.ll
index 2bde76e..0a3afb7 100644
--- a/test/CodeGen/X86/fold-pcmpeqd-2.ll
+++ b/test/CodeGen/X86/fold-pcmpeqd-2.ll
@@ -11,7 +11,7 @@
 ; CHECK: .space 16,255
 
 ; No pcmpeqd instructions, everybody uses the constant pool.
-; CHECK: program_1:
+; CHECK-LABEL: program_1:
 ; CHECK-NOT: pcmpeqd
 
 	%struct.__ImageExecInfo = type <{ <4 x i32>, <4 x float>, <2 x i64>, i8*, i8*, i8*, i32, i32, i32, i32, i32 }>
diff --git a/test/CodeGen/X86/force-align-stack-alloca.ll b/test/CodeGen/X86/force-align-stack-alloca.ll
index 2ada194..95defc8 100644
--- a/test/CodeGen/X86/force-align-stack-alloca.ll
+++ b/test/CodeGen/X86/force-align-stack-alloca.ll
@@ -16,7 +16,7 @@ entry:
 }
 
 define i64 @g(i32 %i) nounwind {
-; CHECK: g:
+; CHECK-LABEL: g:
 ; CHECK:      pushl  %ebp
 ; CHECK-NEXT: movl   %esp, %ebp
 ; CHECK-NEXT: pushl
diff --git a/test/CodeGen/X86/fp-elim-and-no-fp-elim.ll b/test/CodeGen/X86/fp-elim-and-no-fp-elim.ll
index 3468a45..c3b2dfb 100644
--- a/test/CodeGen/X86/fp-elim-and-no-fp-elim.ll
+++ b/test/CodeGen/X86/fp-elim-and-no-fp-elim.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple x86_64-apple-darwin | FileCheck %s
 
 define void @bar(i32 %argc) #0 {
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: pushq %rbp
 entry:
   %conv = sitofp i32 %argc to double
@@ -14,7 +14,7 @@ entry:
 }
 
 define void @qux(i32 %argc) #1 {
-; CHECK: qux:
+; CHECK-LABEL: qux:
 ; CHECK-NOT: pushq %rbp
 entry:
   %conv = sitofp i32 %argc to double
diff --git a/test/CodeGen/X86/fp-elim.ll b/test/CodeGen/X86/fp-elim.ll
index 60892a2..583388c 100644
--- a/test/CodeGen/X86/fp-elim.ll
+++ b/test/CodeGen/X86/fp-elim.ll
@@ -1,42 +1,60 @@
 ; RUN: llc < %s -march=x86 -asm-verbose=false                           | FileCheck %s -check-prefix=FP-ELIM
 ; RUN: llc < %s -march=x86 -asm-verbose=false -disable-fp-elim          | FileCheck %s -check-prefix=NO-ELIM
-; RUN: llc < %s -march=x86 -asm-verbose=false -disable-non-leaf-fp-elim | FileCheck %s -check-prefix=NON-LEAF
 
 ; Implement -momit-leaf-frame-pointer
 ; rdar://7886181
 
-define i32 @t1() nounwind readnone {
+define i32 @t1() "no-frame-pointer-elim-non-leaf"="false" nounwind readnone {
 entry:
-; FP-ELIM:      t1:
-; FP-ELIM-NEXT: movl
-; FP-ELIM-NEXT: ret
-
-; NO-ELIM:      t1:
-; NO-ELIM-NEXT: pushl %ebp
-; NO-ELIM:      popl %ebp
-; NO-ELIM-NEXT: ret
-
-; NON-LEAF:      t1:
-; NON-LEAF-NEXT: movl
-; NON-LEAF-NEXT: ret
+; FP-ELIM-LABEL:  t1:
+; FP-ELIM-NEXT:     movl
+; FP-ELIM-NEXT:     ret
+
+; NO-ELIM-LABEL:  t1:
+; NO-ELIM-NEXT:     pushl %ebp
+; NO-ELIM:          popl %ebp
+; NO-ELIM-NEXT:     ret
   ret i32 10
 }
 
-define void @t2() nounwind {
+define void @t2() "no-frame-pointer-elim-non-leaf"="false" nounwind {
 entry:
-; FP-ELIM:     t2:
-; FP-ELIM-NOT: pushl %ebp
-; FP-ELIM:     ret
-
-; NO-ELIM:      t2:
-; NO-ELIM-NEXT: pushl %ebp
-; NO-ELIM:      popl %ebp
-; NO-ELIM-NEXT: ret
-
-; NON-LEAF:      t2:
-; NON-LEAF-NEXT: pushl %ebp
-; NON-LEAF:      popl %ebp
-; NON-LEAF-NEXT: ret
+; FP-ELIM-LABEL:  t2:
+; FP-ELIM-NOT:      pushl %ebp
+; FP-ELIM:          ret
+
+; NO-ELIM-LABEL:  t2:
+; NO-ELIM-NEXT:     pushl %ebp
+; NO-ELIM:          popl %ebp
+; NO-ELIM-NEXT:     ret
+  tail call void @foo(i32 0) nounwind
+  ret void
+}
+
+define i32 @t3() "no-frame-pointer-elim-non-leaf"="true" nounwind readnone {
+entry:
+; FP-ELIM-LABEL:  t3:
+; FP-ELIM-NEXT:     movl
+; FP-ELIM-NEXT:     ret
+
+; NO-ELIM-LABEL:  t3:
+; NO-ELIM-NEXT:     pushl %ebp
+; NO-ELIM:          popl %ebp
+; NO-ELIM-NEXT:     ret
+  ret i32 10
+}
+
+define void @t4() "no-frame-pointer-elim-non-leaf"="true" nounwind {
+entry:
+; FP-ELIM-LABEL:  t4:
+; FP-ELIM-NEXT:     pushl %ebp
+; FP-ELIM:          popl %ebp
+; FP-ELIM-NEXT:     ret
+
+; NO-ELIM-LABEL:  t4:
+; NO-ELIM-NEXT:     pushl %ebp
+; NO-ELIM:          popl %ebp
+; NO-ELIM-NEXT:     ret
   tail call void @foo(i32 0) nounwind
   ret void
 }
diff --git a/test/CodeGen/X86/fp-fast.ll b/test/CodeGen/X86/fp-fast.ll
index 2875048..07baca8 100644
--- a/test/CodeGen/X86/fp-fast.ll
+++ b/test/CodeGen/X86/fp-fast.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=x86-64 -mattr=+avx,-fma4 -mtriple=x86_64-apple-darwin -enable-unsafe-fp-math < %s | FileCheck %s
 
-; CHECK: test1
+; CHECK-LABEL: test1
 define float @test1(float %a) {
 ; CHECK-NOT: addss
 ; CHECK: mulss
@@ -11,7 +11,7 @@ define float @test1(float %a) {
   ret float %r
 }
 
-; CHECK: test2
+; CHECK-LABEL: test2
 define float @test2(float %a) {
 ; CHECK-NOT: addss
 ; CHECK: mulss
@@ -23,9 +23,45 @@ define float @test2(float %a) {
   ret float %r
 }
 
-; CHECK: test3
+; CHECK-LABEL: test3
 define float @test3(float %a) {
 ; CHECK-NOT: addss
+; CHECK: mulss
+; CHECK-NOT: addss
+; CHECK: ret
+  %t1 = fmul float %a, 4.0
+  %t2 = fadd float %a, %a
+  %r = fadd float %t1, %t2
+  ret float %r
+}
+
+; CHECK-LABEL: test4
+define float @test4(float %a) {
+; CHECK-NOT: addss
+; CHECK: mulss
+; CHECK-NOT: addss
+; CHECK: ret
+  %t1 = fadd float %a, %a
+  %t2 = fmul float 4.0, %a
+  %r = fadd float %t1, %t2
+  ret float %r
+}
+
+; CHECK-LABEL: test5
+define float @test5(float %a) {
+; CHECK-NOT: addss
+; CHECK: mulss
+; CHECK-NOT: addss
+; CHECK: ret
+  %t1 = fadd float %a, %a
+  %t2 = fmul float %a, 4.0
+  %r = fadd float %t1, %t2
+  ret float %r
+}
+
+; CHECK-LABEL: test6
+define float @test6(float %a) {
+; CHECK-NOT: addss
 ; CHECK: xorps
 ; CHECK-NOT: addss
 ; CHECK: ret
@@ -35,8 +71,20 @@ define float @test3(float %a) {
   ret float %r
 }
 
-; CHECK: test4
-define float @test4(float %a) {
+; CHECK-LABEL: test7
+define float @test7(float %a) {
+; CHECK-NOT: addss
+; CHECK: xorps
+; CHECK-NOT: addss
+; CHECK: ret
+  %t1 = fmul float %a, 2.0
+  %t2 = fadd float %a, %a
+  %r = fsub float %t1, %t2
+  ret float %r
+}
+
+; CHECK-LABEL: test8
+define float @test8(float %a) {
 ; CHECK-NOT: fma
 ; CHECK-NOT: mul
 ; CHECK-NOT: add
@@ -46,8 +94,29 @@ define float @test4(float %a) {
   ret float %t2
 }
 
-; CHECK: test5
-define float @test5(float %a) {
+; CHECK-LABEL: test9
+define float @test9(float %a) {
+; CHECK-NOT: fma
+; CHECK-NOT: mul
+; CHECK-NOT: add
+; CHECK: ret
+  %t1 = fmul float 0.0, %a
+  %t2 = fadd float %t1, %a
+  ret float %t2
+}
+
+; CHECK-LABEL: test10
+define float @test10(float %a) {
+; CHECK-NOT: add
+; CHECK: vxorps
+; CHECK: ret
+  %t1 = fsub float -0.0, %a
+  %t2 = fadd float %a, %t1
+  ret float %t2
+}
+
+; CHECK-LABEL: test11
+define float @test11(float %a) {
 ; CHECK-NOT: add
 ; CHECK: vxorps
 ; CHECK: ret
diff --git a/test/CodeGen/X86/fp-select-cmp-and.ll b/test/CodeGen/X86/fp-select-cmp-and.ll
new file mode 100644
index 0000000..cc76b43
--- /dev/null
+++ b/test/CodeGen/X86/fp-select-cmp-and.ll
@@ -0,0 +1,185 @@
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=nehalem | FileCheck %s
+
+define double @test1(double %a, double %b, double %eps) {
+  %cmp = fcmp olt double %a, %eps
+  %cond = select i1 %cmp, double %b, double 0.000000e+00
+  ret double %cond
+
+; CHECK-LABEL: @test1
+; CHECK:	cmpltsd	%xmm2, %xmm0
+; CHECK-NEXT:	andpd	%xmm1, %xmm0
+}
+
+define double @test2(double %a, double %b, double %eps) {
+  %cmp = fcmp ole double %a, %eps
+  %cond = select i1 %cmp, double %b, double 0.000000e+00
+  ret double %cond
+
+; CHECK-LABEL: @test2
+; CHECK:	cmplesd	%xmm2, %xmm0
+; CHECK-NEXT:	andpd	%xmm1, %xmm0
+}
+
+define double @test3(double %a, double %b, double %eps) {
+  %cmp = fcmp ogt double %a, %eps
+  %cond = select i1 %cmp, double %b, double 0.000000e+00
+  ret double %cond
+
+; CHECK-LABEL: @test3
+; CHECK:	cmpltsd	%xmm0, %xmm2
+; CHECK-NEXT:	andpd	%xmm1, %xmm2
+}
+
+define double @test4(double %a, double %b, double %eps) {
+  %cmp = fcmp oge double %a, %eps
+  %cond = select i1 %cmp, double %b, double 0.000000e+00
+  ret double %cond
+
+; CHECK-LABEL: @test4
+; CHECK:	cmplesd	%xmm0, %xmm2
+; CHECK-NEXT:	andpd	%xmm1, %xmm2
+}
+
+define double @test5(double %a, double %b, double %eps) {
+  %cmp = fcmp olt double %a, %eps
+  %cond = select i1 %cmp, double 0.000000e+00, double %b
+  ret double %cond
+
+; CHECK-LABEL: @test5
+; CHECK:	cmpltsd	%xmm2, %xmm0
+; CHECK-NEXT:	andnpd	%xmm1, %xmm0
+}
+
+define double @test6(double %a, double %b, double %eps) {
+  %cmp = fcmp ole double %a, %eps
+  %cond = select i1 %cmp, double 0.000000e+00, double %b
+  ret double %cond
+
+; CHECK-LABEL: @test6
+; CHECK:	cmplesd	%xmm2, %xmm0
+; CHECK-NEXT:	andnpd	%xmm1, %xmm0
+}
+
+define double @test7(double %a, double %b, double %eps) {
+  %cmp = fcmp ogt double %a, %eps
+  %cond = select i1 %cmp, double 0.000000e+00, double %b
+  ret double %cond
+
+; CHECK-LABEL: @test7
+; CHECK:	cmpltsd	%xmm0, %xmm2
+; CHECK-NEXT:	andnpd	%xmm1, %xmm2
+}
+
+define double @test8(double %a, double %b, double %eps) {
+  %cmp = fcmp oge double %a, %eps
+  %cond = select i1 %cmp, double 0.000000e+00, double %b
+  ret double %cond
+
+; CHECK-LABEL: @test8
+; CHECK:	cmplesd	%xmm0, %xmm2
+; CHECK-NEXT:	andnpd	%xmm1, %xmm2
+}
+
+define float @test9(float %a, float %b, float %eps) {
+  %cmp = fcmp olt float %a, %eps
+  %cond = select i1 %cmp, float %b, float 0.000000e+00
+  ret float %cond
+
+; CHECK-LABEL: @test9
+; CHECK:	cmpltss	%xmm2, %xmm0
+; CHECK-NEXT:	andps	%xmm1, %xmm0
+}
+
+define float @test10(float %a, float %b, float %eps) {
+  %cmp = fcmp ole float %a, %eps
+  %cond = select i1 %cmp, float %b, float 0.000000e+00
+  ret float %cond
+
+; CHECK-LABEL: @test10
+; CHECK:	cmpless	%xmm2, %xmm0
+; CHECK-NEXT:	andps	%xmm1, %xmm0
+}
+
+define float @test11(float %a, float %b, float %eps) {
+  %cmp = fcmp ogt float %a, %eps
+  %cond = select i1 %cmp, float %b, float 0.000000e+00
+  ret float %cond
+
+; CHECK-LABEL: @test11
+; CHECK:	cmpltss	%xmm0, %xmm2
+; CHECK-NEXT:	andps	%xmm1, %xmm2
+}
+
+define float @test12(float %a, float %b, float %eps) {
+  %cmp = fcmp oge float %a, %eps
+  %cond = select i1 %cmp, float %b, float 0.000000e+00
+  ret float %cond
+
+; CHECK-LABEL: @test12
+; CHECK:	cmpless	%xmm0, %xmm2
+; CHECK-NEXT:	andps	%xmm1, %xmm2
+}
+
+define float @test13(float %a, float %b, float %eps) {
+  %cmp = fcmp olt float %a, %eps
+  %cond = select i1 %cmp, float 0.000000e+00, float %b
+  ret float %cond
+
+; CHECK-LABEL: @test13
+; CHECK:	cmpltss	%xmm2, %xmm0
+; CHECK-NEXT:	andnps	%xmm1, %xmm0
+}
+
+define float @test14(float %a, float %b, float %eps) {
+  %cmp = fcmp ole float %a, %eps
+  %cond = select i1 %cmp, float 0.000000e+00, float %b
+  ret float %cond
+
+; CHECK-LABEL: @test14
+; CHECK:	cmpless	%xmm2, %xmm0
+; CHECK-NEXT:	andnps	%xmm1, %xmm0
+}
+
+define float @test15(float %a, float %b, float %eps) {
+  %cmp = fcmp ogt float %a, %eps
+  %cond = select i1 %cmp, float 0.000000e+00, float %b
+  ret float %cond
+
+; CHECK-LABEL: @test15
+; CHECK:	cmpltss	%xmm0, %xmm2
+; CHECK-NEXT:	andnps	%xmm1, %xmm2
+}
+
+define float @test16(float %a, float %b, float %eps) {
+  %cmp = fcmp oge float %a, %eps
+  %cond = select i1 %cmp, float 0.000000e+00, float %b
+  ret float %cond
+
+; CHECK-LABEL: @test16
+; CHECK:	cmpless	%xmm0, %xmm2
+; CHECK-NEXT:	andnps	%xmm1, %xmm2
+}
+
+define float @test17(float %a, float %b, float %c, float %eps) {
+  %cmp = fcmp oge float %a, %eps
+  %cond = select i1 %cmp, float %c, float %b
+  ret float %cond
+
+; CHECK-LABEL: @test17
+; CHECK: cmpless	%xmm0, %xmm3
+; CHECK-NEXT: andps	%xmm3, %xmm2
+; CHECK-NEXT: andnps	%xmm1, %xmm3
+; CHECK-NEXT: orps	%xmm2, %xmm3
+}
+
+define double @test18(double %a, double %b, double %c, double %eps) {
+  %cmp = fcmp oge double %a, %eps
+  %cond = select i1 %cmp, double %c, double %b
+  ret double %cond
+
+; CHECK-LABEL: @test18
+; CHECK: cmplesd	%xmm0, %xmm3
+; CHECK-NEXT: andpd	%xmm3, %xmm2
+; CHECK-NEXT: andnpd	%xmm1, %xmm3
+; CHECK-NEXT: orpd	%xmm2, %xmm3
+}
diff --git a/test/CodeGen/X86/fp_constant_op.ll b/test/CodeGen/X86/fp_constant_op.ll
index b3ec538..9a1337a 100644
--- a/test/CodeGen/X86/fp_constant_op.ll
+++ b/test/CodeGen/X86/fp_constant_op.ll
@@ -6,41 +6,41 @@ define double @foo_add(double %P) {
 	%tmp.1 = fadd double %P, 1.230000e+02		; <double> [#uses=1]
 	ret double %tmp.1
 }
-; CHECK: foo_add:
-; CHECK: fadd DWORD PTR
+; CHECK-LABEL: foo_add:
+; CHECK: fadd dword ptr
 
 define double @foo_mul(double %P) {
 	%tmp.1 = fmul double %P, 1.230000e+02		; <double> [#uses=1]
 	ret double %tmp.1
 }
-; CHECK: foo_mul:
-; CHECK: fmul DWORD PTR
+; CHECK-LABEL: foo_mul:
+; CHECK: fmul dword ptr
 
 define double @foo_sub(double %P) {
 	%tmp.1 = fsub double %P, 1.230000e+02		; <double> [#uses=1]
 	ret double %tmp.1
 }
-; CHECK: foo_sub:
-; CHECK: fadd DWORD PTR
+; CHECK-LABEL: foo_sub:
+; CHECK: fadd dword ptr
 
 define double @foo_subr(double %P) {
 	%tmp.1 = fsub double 1.230000e+02, %P		; <double> [#uses=1]
 	ret double %tmp.1
 }
-; CHECK: foo_subr:
-; CHECK: fsub QWORD PTR
+; CHECK-LABEL: foo_subr:
+; CHECK: fsub qword ptr
 
 define double @foo_div(double %P) {
 	%tmp.1 = fdiv double %P, 1.230000e+02		; <double> [#uses=1]
 	ret double %tmp.1
 }
-; CHECK: foo_div:
-; CHECK: fdiv DWORD PTR
+; CHECK-LABEL: foo_div:
+; CHECK: fdiv dword ptr
 
 define double @foo_divr(double %P) {
 	%tmp.1 = fdiv double 1.230000e+02, %P		; <double> [#uses=1]
 	ret double %tmp.1
 }
-; CHECK: foo_divr:
-; CHECK: fdiv QWORD PTR
+; CHECK-LABEL: foo_divr:
+; CHECK: fdiv qword ptr
 
diff --git a/test/CodeGen/X86/h-registers-0.ll b/test/CodeGen/X86/h-registers-0.ll
index cdc75af..71b3b43 100644
--- a/test/CodeGen/X86/h-registers-0.ll
+++ b/test/CodeGen/X86/h-registers-0.ll
@@ -6,17 +6,17 @@
 ; of h registers yet, due to x86 encoding complications.
 
 define void @bar64(i64 inreg %x, i8* inreg %p) nounwind {
-; X86-64: bar64:
+; X86-64-LABEL: bar64:
 ; X86-64: shrq $8, %rdi
 ; X86-64: incb %dil
 
 ; See FIXME: on regclass GR8.
 ; It could be optimally transformed like; incb %ch; movb %ch, (%rdx)
-; WIN64:  bar64:
+; WIN64-LABEL:  bar64:
 ; WIN64:  shrq $8, %rcx
 ; WIN64:  incb %cl
 
-; X86-32: bar64:
+; X86-32-LABEL: bar64:
 ; X86-32: incb %ah
   %t0 = lshr i64 %x, 8
   %t1 = trunc i64 %t0 to i8
@@ -26,15 +26,15 @@ define void @bar64(i64 inreg %x, i8* inreg %p) nounwind {
 }
 
 define void @bar32(i32 inreg %x, i8* inreg %p) nounwind {
-; X86-64: bar32:
+; X86-64-LABEL: bar32:
 ; X86-64: shrl $8, %edi
 ; X86-64: incb %dil
 
-; WIN64:  bar32:
+; WIN64-LABEL:  bar32:
 ; WIN64:  shrl $8, %ecx
 ; WIN64:  incb %cl
 
-; X86-32: bar32:
+; X86-32-LABEL: bar32:
 ; X86-32: incb %ah
   %t0 = lshr i32 %x, 8
   %t1 = trunc i32 %t0 to i8
@@ -44,15 +44,15 @@ define void @bar32(i32 inreg %x, i8* inreg %p) nounwind {
 }
 
 define void @bar16(i16 inreg %x, i8* inreg %p) nounwind {
-; X86-64: bar16:
+; X86-64-LABEL: bar16:
 ; X86-64: shrl $8, %edi
 ; X86-64: incb %dil
 
-; WIN64:  bar16:
+; WIN64-LABEL:  bar16:
 ; WIN64:  shrl $8, %ecx
 ; WIN64:  incb %cl
 
-; X86-32: bar16:
+; X86-32-LABEL: bar16:
 ; X86-32: incb %ah
   %t0 = lshr i16 %x, 8
   %t1 = trunc i16 %t0 to i8
@@ -62,14 +62,14 @@ define void @bar16(i16 inreg %x, i8* inreg %p) nounwind {
 }
 
 define i64 @qux64(i64 inreg %x) nounwind {
-; X86-64: qux64:
+; X86-64-LABEL: qux64:
 ; X86-64: movq %rdi, %rax
 ; X86-64: movzbl %ah, %eax
 
-; WIN64:  qux64:
+; WIN64-LABEL:  qux64:
 ; WIN64:  movzbl %ch, %eax
 
-; X86-32: qux64:
+; X86-32-LABEL: qux64:
 ; X86-32: movzbl %ah, %eax
   %t0 = lshr i64 %x, 8
   %t1 = and i64 %t0, 255
@@ -77,14 +77,14 @@ define i64 @qux64(i64 inreg %x) nounwind {
 }
 
 define i32 @qux32(i32 inreg %x) nounwind {
-; X86-64: qux32:
+; X86-64-LABEL: qux32:
 ; X86-64: movl %edi, %eax
 ; X86-64: movzbl %ah, %eax
 
-; WIN64:  qux32:
+; WIN64-LABEL:  qux32:
 ; WIN64:  movzbl %ch, %eax
 
-; X86-32: qux32:
+; X86-32-LABEL: qux32:
 ; X86-32: movzbl %ah, %eax
   %t0 = lshr i32 %x, 8
   %t1 = and i32 %t0, 255
@@ -92,14 +92,14 @@ define i32 @qux32(i32 inreg %x) nounwind {
 }
 
 define i16 @qux16(i16 inreg %x) nounwind {
-; X86-64: qux16:
+; X86-64-LABEL: qux16:
 ; X86-64: movl %edi, %eax
 ; X86-64: movzbl %ah, %eax
 
-; WIN64:  qux16:
+; WIN64-LABEL:  qux16:
 ; WIN64:  movzbl %ch, %eax
 
-; X86-32: qux16:
+; X86-32-LABEL: qux16:
 ; X86-32: movzbl %ah, %eax
   %t0 = lshr i16 %x, 8
   ret i16 %t0
diff --git a/test/CodeGen/X86/h-registers-2.ll b/test/CodeGen/X86/h-registers-2.ll
index 488444c..91acb7d 100644
--- a/test/CodeGen/X86/h-registers-2.ll
+++ b/test/CodeGen/X86/h-registers-2.ll
@@ -4,7 +4,7 @@
 ; non-address use(s).
 
 define i32 @foo(i8* %x, i32 %y) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NOT: ret
 ; CHECK: movzbl %{{[abcd]h}},
 ; CHECK-NOT: ret
diff --git a/test/CodeGen/X86/haddsub.ll b/test/CodeGen/X86/haddsub.ll
index 5f1f4fd..9feb5f6 100644
--- a/test/CodeGen/X86/haddsub.ll
+++ b/test/CodeGen/X86/haddsub.ll
@@ -1,10 +1,10 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+sse3,-avx | FileCheck %s -check-prefix=SSE3
 ; RUN: llc < %s -march=x86-64 -mattr=-sse3,+avx | FileCheck %s -check-prefix=AVX
 
-; SSE3: haddpd1:
+; SSE3-LABEL: haddpd1:
 ; SSE3-NOT: vhaddpd
 ; SSE3: haddpd
-; AVX: haddpd1:
+; AVX-LABEL: haddpd1:
 ; AVX: vhaddpd
 define <2 x double> @haddpd1(<2 x double> %x, <2 x double> %y) {
   %a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
@@ -13,10 +13,10 @@ define <2 x double> @haddpd1(<2 x double> %x, <2 x double> %y) {
   ret <2 x double> %r
 }
 
-; SSE3: haddpd2:
+; SSE3-LABEL: haddpd2:
 ; SSE3-NOT: vhaddpd
 ; SSE3: haddpd
-; AVX: haddpd2:
+; AVX-LABEL: haddpd2:
 ; AVX: vhaddpd
 define <2 x double> @haddpd2(<2 x double> %x, <2 x double> %y) {
   %a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 2>
@@ -25,10 +25,10 @@ define <2 x double> @haddpd2(<2 x double> %x, <2 x double> %y) {
   ret <2 x double> %r
 }
 
-; SSE3: haddpd3:
+; SSE3-LABEL: haddpd3:
 ; SSE3-NOT: vhaddpd
 ; SSE3: haddpd
-; AVX: haddpd3:
+; AVX-LABEL: haddpd3:
 ; AVX: vhaddpd
 define <2 x double> @haddpd3(<2 x double> %x) {
   %a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
@@ -37,10 +37,10 @@ define <2 x double> @haddpd3(<2 x double> %x) {
   ret <2 x double> %r
 }
 
-; SSE3: haddps1:
+; SSE3-LABEL: haddps1:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
-; AVX: haddps1:
+; AVX-LABEL: haddps1:
 ; AVX: vhaddps
 define <4 x float> @haddps1(<4 x float> %x, <4 x float> %y) {
   %a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -49,10 +49,10 @@ define <4 x float> @haddps1(<4 x float> %x, <4 x float> %y) {
   ret <4 x float> %r
 }
 
-; SSE3: haddps2:
+; SSE3-LABEL: haddps2:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
-; AVX: haddps2:
+; AVX-LABEL: haddps2:
 ; AVX: vhaddps
 define <4 x float> @haddps2(<4 x float> %x, <4 x float> %y) {
   %a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 2, i32 5, i32 6>
@@ -61,10 +61,10 @@ define <4 x float> @haddps2(<4 x float> %x, <4 x float> %y) {
   ret <4 x float> %r
 }
 
-; SSE3: haddps3:
+; SSE3-LABEL: haddps3:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
-; AVX: haddps3:
+; AVX-LABEL: haddps3:
 ; AVX: vhaddps
 define <4 x float> @haddps3(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
@@ -73,10 +73,10 @@ define <4 x float> @haddps3(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: haddps4:
+; SSE3-LABEL: haddps4:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
-; AVX: haddps4:
+; AVX-LABEL: haddps4:
 ; AVX: vhaddps
 define <4 x float> @haddps4(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
@@ -85,10 +85,10 @@ define <4 x float> @haddps4(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: haddps5:
+; SSE3-LABEL: haddps5:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
-; AVX: haddps5:
+; AVX-LABEL: haddps5:
 ; AVX: vhaddps
 define <4 x float> @haddps5(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 3, i32 undef, i32 undef>
@@ -97,10 +97,10 @@ define <4 x float> @haddps5(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: haddps6:
+; SSE3-LABEL: haddps6:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
-; AVX: haddps6:
+; AVX-LABEL: haddps6:
 ; AVX: vhaddps
 define <4 x float> @haddps6(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
@@ -109,10 +109,10 @@ define <4 x float> @haddps6(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: haddps7:
+; SSE3-LABEL: haddps7:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
-; AVX: haddps7:
+; AVX-LABEL: haddps7:
 ; AVX: vhaddps
 define <4 x float> @haddps7(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 undef>
@@ -121,10 +121,10 @@ define <4 x float> @haddps7(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: hsubpd1:
+; SSE3-LABEL: hsubpd1:
 ; SSE3-NOT: vhsubpd
 ; SSE3: hsubpd
-; AVX: hsubpd1:
+; AVX-LABEL: hsubpd1:
 ; AVX: vhsubpd
 define <2 x double> @hsubpd1(<2 x double> %x, <2 x double> %y) {
   %a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
@@ -133,10 +133,10 @@ define <2 x double> @hsubpd1(<2 x double> %x, <2 x double> %y) {
   ret <2 x double> %r
 }
 
-; SSE3: hsubpd2:
+; SSE3-LABEL: hsubpd2:
 ; SSE3-NOT: vhsubpd
 ; SSE3: hsubpd
-; AVX: hsubpd2:
+; AVX-LABEL: hsubpd2:
 ; AVX: vhsubpd
 define <2 x double> @hsubpd2(<2 x double> %x) {
   %a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
@@ -145,10 +145,10 @@ define <2 x double> @hsubpd2(<2 x double> %x) {
   ret <2 x double> %r
 }
 
-; SSE3: hsubps1:
+; SSE3-LABEL: hsubps1:
 ; SSE3-NOT: vhsubps
 ; SSE3: hsubps
-; AVX: hsubps1:
+; AVX-LABEL: hsubps1:
 ; AVX: vhsubps
 define <4 x float> @hsubps1(<4 x float> %x, <4 x float> %y) {
   %a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -157,10 +157,10 @@ define <4 x float> @hsubps1(<4 x float> %x, <4 x float> %y) {
   ret <4 x float> %r
 }
 
-; SSE3: hsubps2:
+; SSE3-LABEL: hsubps2:
 ; SSE3-NOT: vhsubps
 ; SSE3: hsubps
-; AVX: hsubps2:
+; AVX-LABEL: hsubps2:
 ; AVX: vhsubps
 define <4 x float> @hsubps2(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
@@ -169,10 +169,10 @@ define <4 x float> @hsubps2(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: hsubps3:
+; SSE3-LABEL: hsubps3:
 ; SSE3-NOT: vhsubps
 ; SSE3: hsubps
-; AVX: hsubps3:
+; AVX-LABEL: hsubps3:
 ; AVX: vhsubps
 define <4 x float> @hsubps3(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
@@ -181,10 +181,10 @@ define <4 x float> @hsubps3(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: hsubps4:
+; SSE3-LABEL: hsubps4:
 ; SSE3-NOT: vhsubps
 ; SSE3: hsubps
-; AVX: hsubps4:
+; AVX-LABEL: hsubps4:
 ; AVX: vhsubps
 define <4 x float> @hsubps4(<4 x float> %x) {
   %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
@@ -193,11 +193,11 @@ define <4 x float> @hsubps4(<4 x float> %x) {
   ret <4 x float> %r
 }
 
-; SSE3: vhaddps1:
+; SSE3-LABEL: vhaddps1:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
 ; SSE3: haddps
-; AVX: vhaddps1:
+; AVX-LABEL: vhaddps1:
 ; AVX: vhaddps
 define <8 x float> @vhaddps1(<8 x float> %x, <8 x float> %y) {
   %a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
@@ -206,11 +206,11 @@ define <8 x float> @vhaddps1(<8 x float> %x, <8 x float> %y) {
   ret <8 x float> %r
 }
 
-; SSE3: vhaddps2:
+; SSE3-LABEL: vhaddps2:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
 ; SSE3: haddps
-; AVX: vhaddps2:
+; AVX-LABEL: vhaddps2:
 ; AVX: vhaddps
 define <8 x float> @vhaddps2(<8 x float> %x, <8 x float> %y) {
   %a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 1, i32 2, i32 9, i32 10, i32 5, i32 6, i32 13, i32 14>
@@ -219,11 +219,11 @@ define <8 x float> @vhaddps2(<8 x float> %x, <8 x float> %y) {
   ret <8 x float> %r
 }
 
-; SSE3: vhaddps3:
+; SSE3-LABEL: vhaddps3:
 ; SSE3-NOT: vhaddps
 ; SSE3: haddps
 ; SSE3: haddps
-; AVX: vhaddps3:
+; AVX-LABEL: vhaddps3:
 ; AVX: vhaddps
 define <8 x float> @vhaddps3(<8 x float> %x) {
   %a = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
@@ -232,11 +232,11 @@ define <8 x float> @vhaddps3(<8 x float> %x) {
   ret <8 x float> %r
 }
 
-; SSE3: vhsubps1:
+; SSE3-LABEL: vhsubps1:
 ; SSE3-NOT: vhsubps
 ; SSE3: hsubps
 ; SSE3: hsubps
-; AVX: vhsubps1:
+; AVX-LABEL: vhsubps1:
 ; AVX: vhsubps
 define <8 x float> @vhsubps1(<8 x float> %x, <8 x float> %y) {
   %a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
@@ -245,11 +245,11 @@ define <8 x float> @vhsubps1(<8 x float> %x, <8 x float> %y) {
   ret <8 x float> %r
 }
 
-; SSE3: vhsubps3:
+; SSE3-LABEL: vhsubps3:
 ; SSE3-NOT: vhsubps
 ; SSE3: hsubps
 ; SSE3: hsubps
-; AVX: vhsubps3:
+; AVX-LABEL: vhsubps3:
 ; AVX: vhsubps
 define <8 x float> @vhsubps3(<8 x float> %x) {
   %a = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
@@ -258,11 +258,11 @@ define <8 x float> @vhsubps3(<8 x float> %x) {
   ret <8 x float> %r
 }
 
-; SSE3: vhaddpd1:
+; SSE3-LABEL: vhaddpd1:
 ; SSE3-NOT: vhaddpd
 ; SSE3: haddpd
 ; SSE3: haddpd
-; AVX: vhaddpd1:
+; AVX-LABEL: vhaddpd1:
 ; AVX: vhaddpd
 define <4 x double> @vhaddpd1(<4 x double> %x, <4 x double> %y) {
   %a = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
@@ -271,11 +271,11 @@ define <4 x double> @vhaddpd1(<4 x double> %x, <4 x double> %y) {
   ret <4 x double> %r
 }
 
-; SSE3: vhsubpd1:
+; SSE3-LABEL: vhsubpd1:
 ; SSE3-NOT: vhsubpd
 ; SSE3: hsubpd
 ; SSE3: hsubpd
-; AVX: vhsubpd1:
+; AVX-LABEL: vhsubpd1:
 ; AVX: vhsubpd
 define <4 x double> @vhsubpd1(<4 x double> %x, <4 x double> %y) {
   %a = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
diff --git a/test/CodeGen/X86/hidden-vis-4.ll b/test/CodeGen/X86/hidden-vis-4.ll
index a8aede5..25a87b9 100644
--- a/test/CodeGen/X86/hidden-vis-4.ll
+++ b/test/CodeGen/X86/hidden-vis-4.ll
@@ -4,7 +4,7 @@
 
 define i32 @t() nounwind readonly {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movl _x, %eax
 ; CHECK: .comm _x,4
 	%0 = load i32* @x, align 4		; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/hidden-vis.ll b/test/CodeGen/X86/hidden-vis.ll
index fcb74fc..a072cb0 100644
--- a/test/CodeGen/X86/hidden-vis.ll
+++ b/test/CodeGen/X86/hidden-vis.ll
@@ -9,12 +9,12 @@
 
 define weak hidden void @t1() nounwind {
 ; LINUX: .hidden t1
-; LINUX: t1:
+; LINUX-LABEL: t1:
 
 ; DARWIN: .private_extern _t1
-; DARWIN: t1:
+; DARWIN-LABEL: t1:
 
-; WINDOWS: t1:
+; WINDOWS-LABEL: t1:
 ; WINDOWS-NOT: hidden
   ret void
 }
diff --git a/test/CodeGen/X86/hipe-prologue.ll b/test/CodeGen/X86/hipe-prologue.ll
index ff3c5c8..2f16423 100644
--- a/test/CodeGen/X86/hipe-prologue.ll
+++ b/test/CodeGen/X86/hipe-prologue.ll
@@ -9,10 +9,10 @@
 declare void @dummy_use(i32*, i32)
 
 define {i32, i32} @test_basic(i32 %hp, i32 %p) {
-  ; X32-Linux:       test_basic:
+  ; X32-Linux-LABEL:       test_basic:
   ; X32-Linux-NOT:   calll inc_stack_0
 
-  ; X64-Linux:       test_basic:
+  ; X64-Linux-LABEL:       test_basic:
   ; X64-Linux-NOT:   callq inc_stack_0
 
   %mem = alloca i32, i32 10
@@ -23,7 +23,7 @@ define {i32, i32} @test_basic(i32 %hp, i32 %p) {
 }
 
 define cc 11 {i32, i32} @test_basic_hipecc(i32 %hp, i32 %p) {
-  ; X32-Linux:       test_basic_hipecc:
+  ; X32-Linux-LABEL:       test_basic_hipecc:
   ; X32-Linux:       leal -156(%esp), %ebx
   ; X32-Linux-NEXT:  cmpl 76(%ebp), %ebx
   ; X32-Linux-NEXT:  jb .LBB1_1
@@ -33,7 +33,7 @@ define cc 11 {i32, i32} @test_basic_hipecc(i32 %hp, i32 %p) {
   ; X32-Linux:       .LBB1_1:
   ; X32-Linux-NEXT:  calll inc_stack_0
 
-  ; X64-Linux:       test_basic_hipecc:
+  ; X64-Linux-LABEL:       test_basic_hipecc:
   ; X64-Linux:       leaq -232(%rsp), %r14
   ; X64-Linux-NEXT:  cmpq 144(%rbp), %r14
   ; X64-Linux-NEXT:  jb .LBB1_1
@@ -51,10 +51,10 @@ define cc 11 {i32, i32} @test_basic_hipecc(i32 %hp, i32 %p) {
 }
 
 define cc 11 {i32,i32,i32} @test_nocall_hipecc(i32 %hp,i32 %p,i32 %x,i32 %y) {
-  ; X32-Linux:       test_nocall_hipecc:
+  ; X32-Linux-LABEL:       test_nocall_hipecc:
   ; X32-Linux-NOT:   calll inc_stack_0
 
-  ; X64-Linux:       test_nocall_hipecc:
+  ; X64-Linux-LABEL:       test_nocall_hipecc:
   ; X64-Linux-NOT:   callq inc_stack_0
 
   %1 = add i32 %x, %y
diff --git a/test/CodeGen/X86/hoist-common.ll b/test/CodeGen/X86/hoist-common.ll
index cdfdea3..6b26876 100644
--- a/test/CodeGen/X86/hoist-common.ll
+++ b/test/CodeGen/X86/hoist-common.ll
@@ -7,7 +7,7 @@
 
 define zeroext i1 @t(i32 %c) nounwind ssp {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: xorl %eax, %eax
 ; CHECK: test
 ; CHECK: je
diff --git a/test/CodeGen/X86/i128-mul.ll b/test/CodeGen/X86/i128-mul.ll
index e9d30d6..c0b85df 100644
--- a/test/CodeGen/X86/i128-mul.ll
+++ b/test/CodeGen/X86/i128-mul.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64
+; RUN: llc < %s -march=x86-64 | FileCheck %s
 ; PR1198
 
 define i64 @foo(i64 %x, i64 %y) {
@@ -10,3 +10,37 @@ define i64 @foo(i64 %x, i64 %y) {
         %tmp4 = trunc i128 %tmp3 to i64
         ret i64 %tmp4
 }
+
+; <rdar://problem/14096009> superfluous multiply by high part of
+; zero-extended value.
+; CHECK: @mul1
+; CHECK-NOT: imulq
+; CHECK: mulq
+; CHECK-NOT: imulq
+define i64 @mul1(i64 %n, i64* nocapture %z, i64* nocapture %x, i64 %y) {
+entry:
+  %conv = zext i64 %y to i128
+  %cmp11 = icmp eq i64 %n, 0
+  br i1 %cmp11, label %for.end, label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %carry.013 = phi i64 [ %conv6, %for.body ], [ 0, %entry ]
+  %i.012 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds i64* %x, i64 %i.012
+  %0 = load i64* %arrayidx, align 8
+  %conv2 = zext i64 %0 to i128
+  %mul = mul i128 %conv2, %conv
+  %conv3 = zext i64 %carry.013 to i128
+  %add = add i128 %mul, %conv3
+  %conv4 = trunc i128 %add to i64
+  %arrayidx5 = getelementptr inbounds i64* %z, i64 %i.012
+  store i64 %conv4, i64* %arrayidx5, align 8
+  %shr = lshr i128 %add, 64
+  %conv6 = trunc i128 %shr to i64
+  %inc = add i64 %i.012, 1
+  %exitcond = icmp eq i64 %inc, %n
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret i64 0
+}
diff --git a/test/CodeGen/X86/i128-sdiv.ll b/test/CodeGen/X86/i128-sdiv.ll
index ab5cdda..89cd495 100644
--- a/test/CodeGen/X86/i128-sdiv.ll
+++ b/test/CodeGen/X86/i128-sdiv.ll
@@ -3,21 +3,21 @@
 ; trigger correctly.
 
 define i128 @test1(i128 %x) {
-  ; CHECK: test1:
+  ; CHECK-LABEL: test1:
   ; CHECK-NOT: call
   %tmp = sdiv i128 %x, 73786976294838206464
   ret i128 %tmp
 }
 
 define i128 @test2(i128 %x) {
-  ; CHECK: test2:
+  ; CHECK-LABEL: test2:
   ; CHECK-NOT: call
   %tmp = sdiv i128 %x, -73786976294838206464
   ret i128 %tmp
 }
 
 define i128 @test3(i128 %x) {
-  ; CHECK: test3:
+  ; CHECK-LABEL: test3:
   ; CHECK: call
   %tmp = sdiv i128 %x, -73786976294838206467
   ret i128 %tmp
diff --git a/test/CodeGen/X86/iabs.ll b/test/CodeGen/X86/iabs.ll
index 9196cce..f47bd7b 100644
--- a/test/CodeGen/X86/iabs.ll
+++ b/test/CodeGen/X86/iabs.ll
@@ -7,7 +7,7 @@
 ;;       ret
 ; rdar://10695237
 define i32 @test(i32 %a) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: mov
 ; CHECK-NEXT: neg
 ; CHECK-NEXT: cmov
diff --git a/test/CodeGen/X86/inline-asm-R-constraint.ll b/test/CodeGen/X86/inline-asm-R-constraint.ll
index 66c27ac..d17e04d 100644
--- a/test/CodeGen/X86/inline-asm-R-constraint.ll
+++ b/test/CodeGen/X86/inline-asm-R-constraint.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-apple-darwin10.0"
 
 define void @udiv8(i8* %quotient, i16 zeroext %a, i8 zeroext %b, i8 zeroext %c, i8* %remainder) nounwind ssp {
 entry:
-; CHECK: udiv8:
+; CHECK-LABEL: udiv8:
 ; CHECK-NOT: movb %ah, (%r8)
   %a_addr = alloca i16, align 2                   ; <i16*> [#uses=2]
   %b_addr = alloca i8, align 1                    ; <i8*> [#uses=2]
diff --git a/test/CodeGen/X86/inline-asm-fpstack.ll b/test/CodeGen/X86/inline-asm-fpstack.ll
index 2249618..e83c065 100644
--- a/test/CodeGen/X86/inline-asm-fpstack.ll
+++ b/test/CodeGen/X86/inline-asm-fpstack.ll
@@ -147,7 +147,7 @@ declare x86_fp80 @ceil(x86_fp80)
 ; PR4484
 ; test1 leaves a value on the stack that is needed after the asm.
 ; CHECK: testPR4484
-; CHECK: test1
+; CHECK: calll _test1
 ; CHECK-NOT: fstp
 ; Load %a from stack after ceil
 ; CHECK: fldt
diff --git a/test/CodeGen/X86/inreg.ll b/test/CodeGen/X86/inreg.ll
index 6653cfb..e4610e3 100644
--- a/test/CodeGen/X86/inreg.ll
+++ b/test/CodeGen/X86/inreg.ll
@@ -8,7 +8,7 @@ entry:
   %tmp = alloca %struct.s1, align 4
   call void @f(%struct.s1* inreg sret %tmp, i32 inreg 41, i32 inreg 42, i32 43)
   ret void
-  ; DAG: g1:
+  ; DAG-LABEL: g1:
   ; DAG: subl $[[AMT:.*]], %esp
   ; DAG-NEXT: $43, (%esp)
   ; DAG-NEXT: leal    16(%esp), %eax
@@ -18,7 +18,7 @@ entry:
   ; DAG-NEXT: addl $[[AMT]], %esp
   ; DAG-NEXT: ret
 
-  ; FAST: g1:
+  ; FAST-LABEL: g1:
   ; FAST: subl $[[AMT:.*]], %esp
   ; FAST-NEXT: leal    8(%esp), %eax
   ; FAST-NEXT: movl    $41, %edx
diff --git a/test/CodeGen/X86/ins_subreg_coalesce-1.ll b/test/CodeGen/X86/ins_subreg_coalesce-1.ll
index 8367436..bec98a2 100644
--- a/test/CodeGen/X86/ins_subreg_coalesce-1.ll
+++ b/test/CodeGen/X86/ins_subreg_coalesce-1.ll
@@ -2,7 +2,7 @@
 
 define fastcc i32 @t() nounwind  {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movzwl 0, %eax
 ; CHECK: orl $2, %eax
 ; CHECK: movw %ax, 0
diff --git a/test/CodeGen/X86/isel-sink.ll b/test/CodeGen/X86/isel-sink.ll
index d275533..458f19d 100644
--- a/test/CodeGen/X86/isel-sink.ll
+++ b/test/CodeGen/X86/isel-sink.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86 | FileCheck %s
 
 define i32 @test(i32* %X, i32 %B) {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: ret
 ; CHECK-NOT: lea
 ; CHECK: mov{{.}} $4, ({{.*}},{{.*}},4)
diff --git a/test/CodeGen/X86/jump_sign.ll b/test/CodeGen/X86/jump_sign.ll
index 0e34222..d417453 100644
--- a/test/CodeGen/X86/jump_sign.ll
+++ b/test/CodeGen/X86/jump_sign.ll
@@ -1,8 +1,8 @@
 ; RUN: llc < %s -march=x86 -mcpu=pentiumpro -verify-machineinstrs | FileCheck %s
 
-define i32 @f(i32 %X) {
+define i32 @func_f(i32 %X) {
 entry:
-; CHECK: f:
+; CHECK-LABEL: func_f:
 ; CHECK: jns
 	%tmp1 = add i32 %X, 1		; <i32> [#uses=1]
 	%tmp = icmp slt i32 %tmp1, 0		; <i1> [#uses=1]
@@ -23,9 +23,9 @@ declare i32 @baz(...)
 
 ; rdar://10633221
 ; rdar://11355268
-define i32 @g(i32 %a, i32 %b) nounwind {
+define i32 @func_g(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: g:
+; CHECK-LABEL: func_g:
 ; CHECK-NOT: test
 ; CHECK: cmovs
   %sub = sub nsw i32 %a, %b
@@ -35,9 +35,9 @@ entry:
 }
 
 ; rdar://10734411
-define i32 @h(i32 %a, i32 %b) nounwind {
+define i32 @func_h(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: h:
+; CHECK-LABEL: func_h:
 ; CHECK-NOT: cmp
 ; CHECK: cmov
 ; CHECK-NOT: movl
@@ -47,9 +47,9 @@ entry:
   %cond = select i1 %cmp, i32 %sub, i32 0
   ret i32 %cond
 }
-define i32 @i(i32 %a, i32 %b) nounwind {
+define i32 @func_i(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: i:
+; CHECK-LABEL: func_i:
 ; CHECK-NOT: cmp
 ; CHECK: cmov
 ; CHECK-NOT: movl
@@ -59,9 +59,9 @@ entry:
   %cond = select i1 %cmp, i32 %sub, i32 0
   ret i32 %cond
 }
-define i32 @j(i32 %a, i32 %b) nounwind {
+define i32 @func_j(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: j:
+; CHECK-LABEL: func_j:
 ; CHECK-NOT: cmp
 ; CHECK: cmov
 ; CHECK-NOT: movl
@@ -71,9 +71,9 @@ entry:
   %cond = select i1 %cmp, i32 %sub, i32 0
   ret i32 %cond
 }
-define i32 @k(i32 %a, i32 %b) nounwind {
+define i32 @func_k(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: k:
+; CHECK-LABEL: func_k:
 ; CHECK-NOT: cmp
 ; CHECK: cmov
 ; CHECK-NOT: movl
@@ -84,18 +84,18 @@ entry:
   ret i32 %cond
 }
 ; redundant cmp instruction
-define i32 @l(i32 %a, i32 %b) nounwind {
+define i32 @func_l(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: l:
+; CHECK-LABEL: func_l:
 ; CHECK-NOT: cmp
   %cmp = icmp slt i32 %b, %a
   %sub = sub nsw i32 %a, %b
   %cond = select i1 %cmp, i32 %sub, i32 %a
   ret i32 %cond
 }
-define i32 @m(i32 %a, i32 %b) nounwind {
+define i32 @func_m(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: m:
+; CHECK-LABEL: func_m:
 ; CHECK-NOT: cmp
   %cmp = icmp sgt i32 %a, %b
   %sub = sub nsw i32 %a, %b
@@ -104,9 +104,9 @@ entry:
 }
 ; If EFLAGS is live-out, we can't remove cmp if there exists
 ; a swapped sub.
-define i32 @l2(i32 %a, i32 %b) nounwind {
+define i32 @func_l2(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: l2:
+; CHECK-LABEL: func_l2:
 ; CHECK: cmp
   %cmp = icmp eq i32 %b, %a
   %sub = sub nsw i32 %a, %b
@@ -120,9 +120,9 @@ if.then:
 if.else:
   ret i32 %sub
 }
-define i32 @l3(i32 %a, i32 %b) nounwind {
+define i32 @func_l3(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: l3:
+; CHECK-LABEL: func_l3:
 ; CHECK: sub
 ; CHECK-NOT: cmp
 ; CHECK: jge
@@ -139,9 +139,9 @@ if.else:
 }
 ; rdar://11830760
 ; When Movr0 is between sub and cmp, we need to move "Movr0" before sub.
-define i32 @l4(i32 %a, i32 %b) nounwind {
+define i32 @func_l4(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: l4:
+; CHECK-LABEL: func_l4:
 ; CHECK: xor
 ; CHECK: sub
 ; CHECK-NOT: cmp
@@ -151,9 +151,9 @@ entry:
   ret i32 %.sub
 }
 ; rdar://11540023
-define i32 @n(i32 %x, i32 %y) nounwind {
+define i32 @func_n(i32 %x, i32 %y) nounwind {
 entry:
-; CHECK: n:
+; CHECK-LABEL: func_n:
 ; CHECK-NOT: sub
 ; CHECK: cmp
   %sub = sub nsw i32 %x, %y
@@ -162,7 +162,7 @@ entry:
   ret i32 %y.x
 }
 ; PR://13046
-define void @o() nounwind uwtable {
+define void @func_o() nounwind uwtable {
 entry:
   %0 = load i16* undef, align 2
   br i1 undef, label %if.then.i, label %if.end.i
@@ -177,7 +177,7 @@ sw.bb:                                            ; preds = %if.end.i
   br i1 undef, label %if.then44, label %if.end29
 
 if.end29:                                         ; preds = %sw.bb
-; CHECK: o:
+; CHECK-LABEL: func_o:
 ; CHECK: cmp
   %1 = urem i16 %0, 10
   %cmp25 = icmp eq i16 %1, 0
@@ -204,9 +204,9 @@ if.else.i104:                                     ; preds = %if.then44
   ret void
 }
 ; rdar://11855129
-define i32 @p(i32 %a, i32 %b) nounwind {
+define i32 @func_p(i32 %a, i32 %b) nounwind {
 entry:
-; CHECK: p:
+; CHECK-LABEL: func_p:
 ; CHECK-NOT: test
 ; CHECK: cmovs
   %add = add nsw i32 %b, %a
@@ -217,8 +217,8 @@ entry:
 ; PR13475
 ; If we have sub a, b and cmp b, a and the result of cmp is used
 ; by sbb, we should not optimize cmp away.
-define i32 @q(i32 %j.4, i32 %w, i32 %el) {
-; CHECK: q:
+define i32 @func_q(i32 %j.4, i32 %w, i32 %el) {
+; CHECK-LABEL: func_q:
 ; CHECK: cmp
 ; CHECK-NEXT: sbb
   %tmp532 = add i32 %j.4, %w
@@ -230,9 +230,9 @@ define i32 @q(i32 %j.4, i32 %w, i32 %el) {
   ret i32 %j.5
 }
 ; rdar://11873276
-define i8* @r(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
+define i8* @func_r(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
 entry:
-; CHECK: r:
+; CHECK-LABEL: func_r:
 ; CHECK: sub
 ; CHECK-NOT: cmp
 ; CHECK: j
@@ -254,9 +254,9 @@ return:
 }
 
 ; Test optimizations of dec/inc.
-define i32 @dec(i32 %a) nounwind {
+define i32 @func_dec(i32 %a) nounwind {
 entry:
-; CHECK: dec:
+; CHECK-LABEL: func_dec:
 ; CHECK: decl
 ; CHECK-NOT: test
 ; CHECK: cmovsl
@@ -266,9 +266,9 @@ entry:
   ret i32 %cond
 }
 
-define i32 @inc(i32 %a) nounwind {
+define i32 @func_inc(i32 %a) nounwind {
 entry:
-; CHECK: inc:
+; CHECK-LABEL: func_inc:
 ; CHECK: incl
 ; CHECK-NOT: test
 ; CHECK: cmovsl
@@ -281,9 +281,9 @@ entry:
 ; PR13966
 @b = common global i32 0, align 4
 @a = common global i32 0, align 4
-define i32 @test1(i32 %p1) nounwind uwtable {
+define i32 @func_test1(i32 %p1) nounwind uwtable {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: func_test1:
 ; CHECK: testb
 ; CHECK: j
 ; CHECK: ret
diff --git a/test/CodeGen/X86/lea-2.ll b/test/CodeGen/X86/lea-2.ll
index 2112809..82cefb7 100644
--- a/test/CodeGen/X86/lea-2.ll
+++ b/test/CodeGen/X86/lea-2.ll
@@ -7,7 +7,7 @@ define i32 @test1(i32 %A, i32 %B) {
 ; The above computation of %tmp4 should match a single lea, without using
 ; actual add instructions.
 ; CHECK-NOT: add
-; CHECK: lea {{[A-Z]+}}, DWORD PTR [{{[A-Z]+}} + 4*{{[A-Z]+}} - 5]
+; CHECK: lea {{[a-z]+}}, dword ptr [{{[a-z]+}} + 4*{{[a-z]+}} - 5]
 
   ret i32 %tmp4
 }
diff --git a/test/CodeGen/X86/lea.ll b/test/CodeGen/X86/lea.ll
index 87f0b0b..affd6bf 100644
--- a/test/CodeGen/X86/lea.ll
+++ b/test/CodeGen/X86/lea.ll
@@ -5,7 +5,7 @@ define i32 @test1(i32 %x) nounwind {
         %tmp1 = shl i32 %x, 3
         %tmp2 = add i32 %tmp1, 7
         ret i32 %tmp2
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK:    leal 7(,%r[[A0:di|cx]],8), %eax
 }
 
@@ -27,7 +27,7 @@ bb.nph:
 
 bb2:
 	ret i32 %x_offs
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movl %e[[A0]], %eax
 ; CHECK: addl $-5, %eax
 ; CHECK:	andl	$-4, %eax
diff --git a/test/CodeGen/X86/leaf-fp-elim.ll b/test/CodeGen/X86/leaf-fp-elim.ll
index 607dc72..7eebf8d 100644
--- a/test/CodeGen/X86/leaf-fp-elim.ll
+++ b/test/CodeGen/X86/leaf-fp-elim.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -disable-non-leaf-fp-elim -relocation-model=pic -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -relocation-model=pic -mtriple=x86_64-apple-darwin | FileCheck %s
 ; <rdar://problem/8170192>
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin11.0"
@@ -6,7 +6,7 @@ target triple = "x86_64-apple-darwin11.0"
 @msg = internal global i8* null                   ; <i8**> [#uses=1]
 @.str = private constant [2 x i8] c"x\00", align 1 ; <[2 x i8]*> [#uses=1]
 
-define void @test(i8* %p) nounwind optsize ssp {
+define void @test(i8* %p) "no-frame-pointer-elim-non-leaf"="true" nounwind optsize ssp {
 
 ; No stack frame, please.
 ; CHECK:     _test
diff --git a/test/CodeGen/X86/legalize-shift-64.ll b/test/CodeGen/X86/legalize-shift-64.ll
index 71ef2d3..7736468 100644
--- a/test/CodeGen/X86/legalize-shift-64.ll
+++ b/test/CodeGen/X86/legalize-shift-64.ll
@@ -1,12 +1,11 @@
-; RUN: llc -mcpu=generic -march=x86 < %s | FileCheck %s
-
+; RUN: llc -mcpu=generic -mtriple=i686-unknown-unknown < %s | FileCheck %s
 define i64 @test1(i32 %xx, i32 %test) nounwind {
   %conv = zext i32 %xx to i64
   %and = and i32 %test, 7
   %sh_prom = zext i32 %and to i64
   %shl = shl i64 %conv, %sh_prom
   ret i64 %shl
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: shll	%cl, %eax
 ; CHECK: shrl	%edx
 ; CHECK: xorb	$31
@@ -18,7 +17,7 @@ define i64 @test2(i64 %xx, i32 %test) nounwind {
   %sh_prom = zext i32 %and to i64
   %shl = shl i64 %xx, %sh_prom
   ret i64 %shl
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: shll	%cl, %esi
 ; CHECK: shrl	%edx
 ; CHECK: xorb	$31
@@ -32,7 +31,7 @@ define i64 @test3(i64 %xx, i32 %test) nounwind {
   %sh_prom = zext i32 %and to i64
   %shr = lshr i64 %xx, %sh_prom
   ret i64 %shr
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: shrl	%cl, %esi
 ; CHECK: leal	(%edx,%edx), %eax
 ; CHECK: xorb	$31, %cl
@@ -46,7 +45,7 @@ define i64 @test4(i64 %xx, i32 %test) nounwind {
   %sh_prom = zext i32 %and to i64
   %shr = ashr i64 %xx, %sh_prom
   ret i64 %shr
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: shrl	%cl, %esi
 ; CHECK: leal	(%edx,%edx), %eax
 ; CHECK: xorb	$31, %cl
diff --git a/test/CodeGen/X86/lock-inst-encoding.ll b/test/CodeGen/X86/lock-inst-encoding.ll
index 9765fae..5ce771f 100644
--- a/test/CodeGen/X86/lock-inst-encoding.ll
+++ b/test/CodeGen/X86/lock-inst-encoding.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10.0.0"
 
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: addq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x01,0x37]
 ; CHECK: ret
 define void @f1(i64* %a, i64 %b) nounwind {
@@ -11,7 +11,7 @@ define void @f1(i64* %a, i64 %b) nounwind {
   ret void
 }
 
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: subq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x29,0x37]
 ; CHECK: ret
 define void @f2(i64* %a, i64 %b) nounwind {
@@ -19,7 +19,7 @@ define void @f2(i64* %a, i64 %b) nounwind {
   ret void
 }
 
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: andq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x21,0x37]
 ; CHECK: ret
 define void @f3(i64* %a, i64 %b) nounwind {
@@ -27,7 +27,7 @@ define void @f3(i64* %a, i64 %b) nounwind {
   ret void
 }
 
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: orq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x09,0x37]
 ; CHECK: ret
 define void @f4(i64* %a, i64 %b) nounwind {
@@ -35,7 +35,7 @@ define void @f4(i64* %a, i64 %b) nounwind {
   ret void
 }
 
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: xorq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x31,0x37]
 ; CHECK: ret
 define void @f5(i64* %a, i64 %b) nounwind {
diff --git a/test/CodeGen/X86/longlong-deadload.ll b/test/CodeGen/X86/longlong-deadload.ll
index db91961e0..73e1012 100644
--- a/test/CodeGen/X86/longlong-deadload.ll
+++ b/test/CodeGen/X86/longlong-deadload.ll
@@ -2,7 +2,7 @@
 ; This should not load or store the top part of *P.
 
 define void @test(i64* %P) nounwind  {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: movl 4(%esp), %[[REGISTER:.*]]
 ; CHECK-NOT: 4(%[[REGISTER]])
 ; CHECK: ret
diff --git a/test/CodeGen/X86/loop-blocks.ll b/test/CodeGen/X86/loop-blocks.ll
index 4bd162b..a81ceb9 100644
--- a/test/CodeGen/X86/loop-blocks.ll
+++ b/test/CodeGen/X86/loop-blocks.ll
@@ -6,7 +6,7 @@
 ; CodeGen should insert a branch into the middle of the loop in
 ; order to avoid a branch within the loop.
 
-; CHECK: simple:
+; CHECK-LABEL: simple:
 ;      CHECK:   jmp   .LBB0_1
 ; CHECK-NEXT:   align
 ; CHECK-NEXT: .LBB0_2:
@@ -36,7 +36,7 @@ done:
 ; CodeGen should move block_a to the top of the loop so that it
 ; falls through into the loop, avoiding a branch within the loop.
 
-; CHECK: slightly_more_involved:
+; CHECK-LABEL: slightly_more_involved:
 ;      CHECK:   jmp .LBB1_1
 ; CHECK-NEXT:   align
 ; CHECK-NEXT: .LBB1_4:
@@ -72,7 +72,7 @@ exit:
 ; fallthrough edges which should be preserved.
 ; "callq block_a_merge_func" is tail duped.
 
-; CHECK: yet_more_involved:
+; CHECK-LABEL: yet_more_involved:
 ;      CHECK:   jmp .LBB2_1
 ; CHECK-NEXT:   align
 ; CHECK-NEXT: .LBB2_5:
@@ -132,7 +132,7 @@ exit:
 ; conveniently fit anywhere so that they are at least contiguous with the
 ; loop.
 
-; CHECK: cfg_islands:
+; CHECK-LABEL: cfg_islands:
 ;      CHECK:   jmp     .LBB3_1
 ; CHECK-NEXT:   align
 ; CHECK-NEXT: .LBB3_7:
diff --git a/test/CodeGen/X86/lsr-loop-exit-cond.ll b/test/CodeGen/X86/lsr-loop-exit-cond.ll
index 8a81f70..c7a3186 100644
--- a/test/CodeGen/X86/lsr-loop-exit-cond.ll
+++ b/test/CodeGen/X86/lsr-loop-exit-cond.ll
@@ -1,13 +1,13 @@
 ; RUN: llc -mtriple=x86_64-darwin -mcpu=generic < %s | FileCheck %s
 ; RUN: llc -mtriple=x86_64-darwin -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s
 
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: decq
 ; CHECK-NEXT: movl (%r9,%rax,4), %eax
 ; CHECK-NEXT: jne
 
-; ATOM: t:
-; ATOM: movl (%r9,%rax,4), %eax
+; ATOM-LABEL: t:
+; ATOM: movl (%r9,%r{{.+}},4), %eax
 ; ATOM-NEXT: decq
 ; ATOM-NEXT: jne
 
@@ -148,14 +148,14 @@ bb2:		; preds = %bb
 ; is equal to the stride.
 ; It must not fold (cmp (add iv, 1), 1) --> (cmp iv, 0).
 
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: %for.body
 ; CHECK: incl [[IV:%e..]]
 ; CHECK: cmpl $1, [[IV]]
 ; CHECK: jne
 ; CHECK: ret
 
-; ATOM: f:
+; ATOM-LABEL: f:
 ; ATOM: %for.body
 ; ATOM: incl [[IV:%e..]]
 ; ATOM: cmpl $1, [[IV]]
@@ -190,4 +190,3 @@ for.end:                                          ; preds = %for.body, %entry
   %bi.0.lcssa = phi i32 [ 0, %entry ], [ %i.addr.0.bi.0, %for.body ]
   ret i32 %bi.0.lcssa
 }
-
diff --git a/test/CodeGen/X86/lsr-reuse.ll b/test/CodeGen/X86/lsr-reuse.ll
index 1311a73..40c041a 100644
--- a/test/CodeGen/X86/lsr-reuse.ll
+++ b/test/CodeGen/X86/lsr-reuse.ll
@@ -8,7 +8,7 @@ target triple = "x86_64-unknown-unknown"
 ; Instruction selection should use the FLAGS value from the dec for
 ; the branch. Scheduling should push the adds upwards.
 
-; CHECK: full_me_0:
+; CHECK-LABEL: full_me_0:
 ; CHECK: movsd   (%rsi), %xmm0
 ; CHECK: mulsd   (%rdx), %xmm0
 ; CHECK: movsd   %xmm0, (%rdi)
@@ -50,7 +50,7 @@ return:
 ; would be better on x86-64, since the start value would be 0 instead of
 ; 2048.
 
-; CHECK: mostly_full_me_0:
+; CHECK-LABEL: mostly_full_me_0:
 ; CHECK: movsd   -2048(%rsi), %xmm0
 ; CHECK: mulsd   -2048(%rdx), %xmm0
 ; CHECK: movsd   %xmm0, -2048(%rdi)
@@ -96,7 +96,7 @@ return:
 ; A minor variation on mostly_full_me_0.
 ; Prefer to start the indvar at 0.
 
-; CHECK: mostly_full_me_1:
+; CHECK-LABEL: mostly_full_me_1:
 ; CHECK: movsd   (%rsi), %xmm0
 ; CHECK: mulsd   (%rdx), %xmm0
 ; CHECK: movsd   %xmm0, (%rdi)
@@ -141,7 +141,7 @@ return:
 
 ; A slightly less minor variation on mostly_full_me_0.
 
-; CHECK: mostly_full_me_2:
+; CHECK-LABEL: mostly_full_me_2:
 ; CHECK: movsd   (%rsi), %xmm0
 ; CHECK: mulsd   (%rdx), %xmm0
 ; CHECK: movsd   %xmm0, (%rdi)
@@ -190,7 +190,7 @@ return:
 ; cases away, but it's useful here to verify that LSR's register pressure
 ; heuristics are working as expected.
 
-; CHECK: count_me_0:
+; CHECK-LABEL: count_me_0:
 ; CHECK: movsd   (%rsi,%rax,8), %xmm0
 ; CHECK: mulsd   (%rdx,%rax,8), %xmm0
 ; CHECK: movsd   %xmm0, (%rdi,%rax,8)
@@ -225,7 +225,7 @@ return:
 ; would not reduce register pressure.
 ; (though it would reduce register pressure inside the loop...)
 
-; CHECK: count_me_1:
+; CHECK-LABEL: count_me_1:
 ; CHECK: movsd   (%rsi,%rax,8), %xmm0
 ; CHECK: mulsd   (%rdx,%rax,8), %xmm0
 ; CHECK: movsd   %xmm0, (%rdi,%rax,8)
@@ -259,7 +259,7 @@ return:
 ; Full strength reduction doesn't save any registers here because the
 ; loop tripcount is a constant.
 
-; CHECK: count_me_2:
+; CHECK-LABEL: count_me_2:
 ; CHECK: movl    $10, %eax
 ; CHECK: align
 ; CHECK: BB6_1:
@@ -305,7 +305,7 @@ return:
 
 ; This should be fully strength-reduced to reduce register pressure.
 
-; CHECK: full_me_1:
+; CHECK-LABEL: full_me_1:
 ; CHECK: align
 ; CHECK: BB7_1:
 ; CHECK: movsd   (%rdi), %xmm0
@@ -353,7 +353,7 @@ return:
 ; This is a variation on full_me_0 in which the 0,+,1 induction variable
 ; has a non-address use, pinning that value in a register.
 
-; CHECK: count_me_3:
+; CHECK-LABEL: count_me_3:
 ; CHECK: call
 ; CHECK: movsd   (%r{{[^,]*}},%r{{[^,]*}},8), %xmm0
 ; CHECK: mulsd   (%r{{[^,]*}},%r{{[^,]*}},8), %xmm0
@@ -390,7 +390,7 @@ return:
 ; LSR should use only one indvar for the inner loop.
 ; rdar://7657764
 
-; CHECK: asd:
+; CHECK-LABEL: asd:
 ; CHECK: BB9_4:
 ; CHECK-NEXT: addl  (%r{{[^,]*}},%rdi,4), %e
 ; CHECK-NEXT: incq  %rdi
@@ -447,7 +447,7 @@ bb5:                                              ; preds = %bb3, %entry
 ; we don't want to leave extra induction variables around, or use an
 ; lea to compute an exit condition inside the loop:
 
-; CHECK: test:
+; CHECK-LABEL: test:
 
 ; CHECK:      BB10_4:
 ; CHECK-NEXT:   movaps  %xmm{{.*}}, %xmm{{.*}}
diff --git a/test/CodeGen/X86/lzcnt.ll b/test/CodeGen/X86/lzcnt.ll
index 2faa24a..ff83f85 100644
--- a/test/CodeGen/X86/lzcnt.ll
+++ b/test/CodeGen/X86/lzcnt.ll
@@ -8,55 +8,55 @@ declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
 define i8 @t1(i8 %x) nounwind  {
 	%tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 false )
 	ret i8 %tmp
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: lzcntl
 }
 
 define i16 @t2(i16 %x) nounwind  {
 	%tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 false )
 	ret i16 %tmp
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: lzcntw
 }
 
 define i32 @t3(i32 %x) nounwind  {
 	%tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 false )
 	ret i32 %tmp
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: lzcntl
 }
 
 define i64 @t4(i64 %x) nounwind  {
 	%tmp = tail call i64 @llvm.ctlz.i64( i64 %x, i1 false )
 	ret i64 %tmp
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: lzcntq
 }
 
 define i8 @t5(i8 %x) nounwind  {
 	%tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 true )
 	ret i8 %tmp
-; CHECK: t5:
+; CHECK-LABEL: t5:
 ; CHECK: lzcntl
 }
 
 define i16 @t6(i16 %x) nounwind  {
 	%tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 true )
 	ret i16 %tmp
-; CHECK: t6:
+; CHECK-LABEL: t6:
 ; CHECK: lzcntw
 }
 
 define i32 @t7(i32 %x) nounwind  {
 	%tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 true )
 	ret i32 %tmp
-; CHECK: t7:
+; CHECK-LABEL: t7:
 ; CHECK: lzcntl
 }
 
 define i64 @t8(i64 %x) nounwind  {
 	%tmp = tail call i64 @llvm.ctlz.i64( i64 %x, i1 true )
 	ret i64 %tmp
-; CHECK: t8:
+; CHECK-LABEL: t8:
 ; CHECK: lzcntq
 }
diff --git a/test/CodeGen/X86/machine-cp.ll b/test/CodeGen/X86/machine-cp.ll
index 8e97b99..f04e111 100644
--- a/test/CodeGen/X86/machine-cp.ll
+++ b/test/CodeGen/X86/machine-cp.ll
@@ -4,7 +4,7 @@
 ; rdar://10640363
 define i32 @t1(i32 %a, i32 %b) nounwind  {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: je [[LABEL:.*BB.*]]
   %cmp1 = icmp eq i32 %b, 0
   br i1 %cmp1, label %while.end, label %while.body
@@ -29,7 +29,7 @@ while.end:                                        ; preds = %while.body, %entry
 ; rdar://10428165
 define <8 x i16> @t2(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK-NOT: movdqa
   %tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef >
   ret <8 x i16> %tmp8
diff --git a/test/CodeGen/X86/machine-cse.ll b/test/CodeGen/X86/machine-cse.ll
index b42d82e..409147b 100644
--- a/test/CodeGen/X86/machine-cse.ll
+++ b/test/CodeGen/X86/machine-cse.ll
@@ -8,7 +8,7 @@
 
 define fastcc i8* @t(i32 %base) nounwind {
 entry:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: leaq (%rax,%rax,4)
   %0 = zext i32 %base to i64
   %1 = getelementptr inbounds %struct.s2* null, i64 %0
@@ -43,7 +43,7 @@ declare fastcc i8* @foo(%struct.s2*) nounwind
 declare void @printf(...) nounwind
 
 define void @commute(i32 %test_case, i32 %scale) nounwind ssp {
-; CHECK: commute:
+; CHECK-LABEL: commute:
 entry:
   switch i32 %test_case, label %sw.bb307 [
     i32 1, label %sw.bb
@@ -83,7 +83,7 @@ sw.bb307:                                         ; preds = %sw.bb, %entry
 ; rdar://10660865
 define i32 @cross_mbb_phys_cse(i32 %a, i32 %b) nounwind ssp {
 entry:
-; CHECK: cross_mbb_phys_cse:
+; CHECK-LABEL: cross_mbb_phys_cse:
 ; CHECK: cmpl
 ; CHECK: ja
   %cmp = icmp ugt i32 %a, %b
@@ -153,7 +153,7 @@ a:
 b:
   ret i32 0
 
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: t2_global@GOTPCREL(%rip)
 ; CHECK-NOT: t2_global@GOTPCREL(%rip)
 }
diff --git a/test/CodeGen/X86/mcinst-lowering.ll b/test/CodeGen/X86/mcinst-lowering.ll
index 1ef5a97..a82cfc4 100644
--- a/test/CodeGen/X86/mcinst-lowering.ll
+++ b/test/CodeGen/X86/mcinst-lowering.ll
@@ -24,3 +24,21 @@ if.end:                                           ; preds = %entry
 return:                                           ; preds = %entry
   ret i32 0
 }
+
+define i32 @f1() nounwind {
+  %ax = tail call i16 asm sideeffect "", "={ax},~{dirflag},~{fpsr},~{flags}"()
+  %conv = sext i16 %ax to i32
+  ret i32 %conv
+
+; CHECK-LABEL: f1:
+; CHECK: cwtl ## encoding: [0x98]
+}
+
+define i64 @f2() nounwind {
+  %eax = tail call i32 asm sideeffect "", "={ax},~{dirflag},~{fpsr},~{flags}"()
+  %conv = sext i32 %eax to i64
+  ret i64 %conv
+
+; CHECK-LABEL: f2:
+; CHECK: cltq ## encoding: [0x48,0x98]
+}
diff --git a/test/CodeGen/X86/memcmp.ll b/test/CodeGen/X86/memcmp.ll
index 723d1d8..cb0797d 100644
--- a/test/CodeGen/X86/memcmp.ll
+++ b/test/CodeGen/X86/memcmp.ll
@@ -21,10 +21,10 @@ bb:                                               ; preds = %entry
 
 return:                                           ; preds = %entry
   ret void
-; CHECK: memcmp2:
+; CHECK-LABEL: memcmp2:
 ; CHECK: movw    ([[A0:%rdi|%rcx]]), %ax
 ; CHECK: cmpw    ([[A1:%rsi|%rdx]]), %ax
-; NOBUILTIN: memcmp2:
+; NOBUILTIN-LABEL: memcmp2:
 ; NOBUILTIN: callq
 }
 
@@ -40,7 +40,7 @@ bb:                                               ; preds = %entry
 
 return:                                           ; preds = %entry
   ret void
-; CHECK: memcmp2a:
+; CHECK-LABEL: memcmp2a:
 ; CHECK: cmpw    $28527, ([[A0]])
 }
 
@@ -57,7 +57,7 @@ bb:                                               ; preds = %entry
 
 return:                                           ; preds = %entry
   ret void
-; CHECK: memcmp4:
+; CHECK-LABEL: memcmp4:
 ; CHECK: movl    ([[A0]]), %eax
 ; CHECK: cmpl    ([[A1]]), %eax
 }
@@ -74,7 +74,7 @@ bb:                                               ; preds = %entry
 
 return:                                           ; preds = %entry
   ret void
-; CHECK: memcmp4a:
+; CHECK-LABEL: memcmp4a:
 ; CHECK: cmpl $1869573999, ([[A0]])
 }
 
@@ -90,7 +90,7 @@ bb:                                               ; preds = %entry
 
 return:                                           ; preds = %entry
   ret void
-; CHECK: memcmp8:
+; CHECK-LABEL: memcmp8:
 ; CHECK: movq    ([[A0]]), %rax
 ; CHECK: cmpq    ([[A1]]), %rax
 }
@@ -107,7 +107,7 @@ bb:                                               ; preds = %entry
 
 return:                                           ; preds = %entry
   ret void
-; CHECK: memcmp8a:
+; CHECK-LABEL: memcmp8a:
 ; CHECK: movabsq $8029759185026510694, %rax
 ; CHECK: cmpq	%rax, ([[A0]])
 }
diff --git a/test/CodeGen/X86/memcpy-2.ll b/test/CodeGen/X86/memcpy-2.ll
index 630c0ed..c17cc7f 100644
--- a/test/CodeGen/X86/memcpy-2.ll
+++ b/test/CodeGen/X86/memcpy-2.ll
@@ -9,28 +9,28 @@
 
 define void @t1(i32 %argc, i8** %argv) nounwind  {
 entry:
-; SSE2-Darwin: t1:
+; SSE2-Darwin-LABEL: t1:
 ; SSE2-Darwin: movsd _.str+16, %xmm0
 ; SSE2-Darwin: movsd %xmm0, 16(%esp)
 ; SSE2-Darwin: movaps _.str, %xmm0
 ; SSE2-Darwin: movaps %xmm0
 ; SSE2-Darwin: movb $0, 24(%esp)
 
-; SSE2-Mingw32: t1:
+; SSE2-Mingw32-LABEL: t1:
 ; SSE2-Mingw32: movsd _.str+16, %xmm0
 ; SSE2-Mingw32: movsd %xmm0, 16(%esp)
 ; SSE2-Mingw32: movaps _.str, %xmm0
 ; SSE2-Mingw32: movups %xmm0
 ; SSE2-Mingw32: movb $0, 24(%esp)
 
-; SSE1: t1:
+; SSE1-LABEL: t1:
 ; SSE1: movaps _.str, %xmm0
 ; SSE1: movaps %xmm0
 ; SSE1: movb $0, 24(%esp)
 ; SSE1: movl $0, 20(%esp)
 ; SSE1: movl $0, 16(%esp)
 
-; NOSSE: t1:
+; NOSSE-LABEL: t1:
 ; NOSSE: movb $0
 ; NOSSE: movl $0
 ; NOSSE: movl $0
@@ -39,7 +39,7 @@ entry:
 ; NOSSE: movl $101
 ; NOSSE: movl $1734438249
 
-; X86-64: t1:
+; X86-64-LABEL: t1:
 ; X86-64: movaps _.str(%rip), %xmm0
 ; X86-64: movaps %xmm0
 ; X86-64: movb $0
@@ -55,19 +55,19 @@ entry:
 
 define void @t2(%struct.s0* nocapture %a, %struct.s0* nocapture %b) nounwind ssp {
 entry:
-; SSE2-Darwin: t2:
+; SSE2-Darwin-LABEL: t2:
 ; SSE2-Darwin: movaps (%eax), %xmm0
 ; SSE2-Darwin: movaps %xmm0, (%eax)
 
-; SSE2-Mingw32: t2:
+; SSE2-Mingw32-LABEL: t2:
 ; SSE2-Mingw32: movaps (%eax), %xmm0
 ; SSE2-Mingw32: movaps %xmm0, (%eax)
 
-; SSE1: t2:
+; SSE1-LABEL: t2:
 ; SSE1: movaps (%eax), %xmm0
 ; SSE1: movaps %xmm0, (%eax)
 
-; NOSSE: t2:
+; NOSSE-LABEL: t2:
 ; NOSSE: movl
 ; NOSSE: movl
 ; NOSSE: movl
@@ -79,7 +79,7 @@ entry:
 ; NOSSE: movl
 ; NOSSE: movl
 
-; X86-64: t2:
+; X86-64-LABEL: t2:
 ; X86-64: movaps (%rsi), %xmm0
 ; X86-64: movaps %xmm0, (%rdi)
   %tmp2 = bitcast %struct.s0* %a to i8*           ; <i8*> [#uses=1]
@@ -90,19 +90,19 @@ entry:
 
 define void @t3(%struct.s0* nocapture %a, %struct.s0* nocapture %b) nounwind ssp {
 entry:
-; SSE2-Darwin: t3:
+; SSE2-Darwin-LABEL: t3:
 ; SSE2-Darwin: movsd (%eax), %xmm0
 ; SSE2-Darwin: movsd 8(%eax), %xmm1
 ; SSE2-Darwin: movsd %xmm1, 8(%eax)
 ; SSE2-Darwin: movsd %xmm0, (%eax)
 
-; SSE2-Mingw32: t3:
+; SSE2-Mingw32-LABEL: t3:
 ; SSE2-Mingw32: movsd (%eax), %xmm0
 ; SSE2-Mingw32: movsd 8(%eax), %xmm1
 ; SSE2-Mingw32: movsd %xmm1, 8(%eax)
 ; SSE2-Mingw32: movsd %xmm0, (%eax)
 
-; SSE1: t3:
+; SSE1-LABEL: t3:
 ; SSE1: movl
 ; SSE1: movl
 ; SSE1: movl
@@ -114,7 +114,7 @@ entry:
 ; SSE1: movl
 ; SSE1: movl
 
-; NOSSE: t3:
+; NOSSE-LABEL: t3:
 ; NOSSE: movl
 ; NOSSE: movl
 ; NOSSE: movl
@@ -126,7 +126,7 @@ entry:
 ; NOSSE: movl
 ; NOSSE: movl
 
-; X86-64: t3:
+; X86-64-LABEL: t3:
 ; X86-64: movq (%rsi), %rax
 ; X86-64: movq 8(%rsi), %rcx
 ; X86-64: movq %rcx, 8(%rdi)
@@ -139,7 +139,7 @@ entry:
 
 define void @t4() nounwind {
 entry:
-; SSE2-Darwin: t4:
+; SSE2-Darwin-LABEL: t4:
 ; SSE2-Darwin: movw $120
 ; SSE2-Darwin: movl $2021161080
 ; SSE2-Darwin: movl $2021161080
@@ -149,7 +149,7 @@ entry:
 ; SSE2-Darwin: movl $2021161080
 ; SSE2-Darwin: movl $2021161080
 
-; SSE2-Mingw32: t4:
+; SSE2-Mingw32-LABEL: t4:
 ; SSE2-Mingw32: movw $120
 ; SSE2-Mingw32: movl $2021161080
 ; SSE2-Mingw32: movl $2021161080
@@ -159,7 +159,7 @@ entry:
 ; SSE2-Mingw32: movl $2021161080
 ; SSE2-Mingw32: movl $2021161080
 
-; SSE1: t4:
+; SSE1-LABEL: t4:
 ; SSE1: movw $120
 ; SSE1: movl $2021161080
 ; SSE1: movl $2021161080
@@ -169,7 +169,7 @@ entry:
 ; SSE1: movl $2021161080
 ; SSE1: movl $2021161080
 
-; NOSSE: t4:
+; NOSSE-LABEL: t4:
 ; NOSSE: movw $120
 ; NOSSE: movl $2021161080
 ; NOSSE: movl $2021161080
@@ -179,7 +179,7 @@ entry:
 ; NOSSE: movl $2021161080
 ; NOSSE: movl $2021161080
 
-; X86-64: t4:
+; X86-64-LABEL: t4:
 ; X86-64: movabsq $8680820740569200760, %rax
 ; X86-64: movq %rax
 ; X86-64: movq %rax
diff --git a/test/CodeGen/X86/memcpy.ll b/test/CodeGen/X86/memcpy.ll
index 3372a4a..88b6cfd 100644
--- a/test/CodeGen/X86/memcpy.ll
+++ b/test/CodeGen/X86/memcpy.ll
@@ -10,7 +10,7 @@ entry:
 	tail call void @llvm.memcpy.p0i8.p0i8.i64( i8* %a, i8* %b, i64 %n, i32 1, i1 0 )
 	ret i8* %a
         
-; LINUX: test1:
+; LINUX-LABEL: test1:
 ; LINUX: memcpy
 }
 
@@ -22,7 +22,7 @@ entry:
 	tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp25, i64 %n, i32 8, i1 0 )
 	ret i8* %tmp14
         
-; LINUX: test2:
+; LINUX-LABEL: test2:
 ; LINUX: memcpy
 }
 
@@ -36,10 +36,10 @@ define void @test3(i8* nocapture %A, i8* nocapture %B) nounwind optsize noredzon
 entry:
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %A, i8* %B, i64 64, i32 1, i1 false)
   ret void
-; LINUX: test3:
+; LINUX-LABEL: test3:
 ; LINUX: memcpy
 
-; DARWIN: test3:
+; DARWIN-LABEL: test3:
 ; DARWIN-NOT: memcpy
 ; DARWIN: movq
 ; DARWIN: movq
@@ -64,7 +64,7 @@ define void @test4(i8* nocapture %A, i8* nocapture %B) nounwind noredzone {
 entry:
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %A, i8* %B, i64 64, i32 1, i1 false)
   ret void
-; LINUX: test4:
+; LINUX-LABEL: test4:
 ; LINUX: movq
 ; LINUX: movq
 ; LINUX: movq
@@ -87,7 +87,7 @@ entry:
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([30 x i8]* @.str, i64 0, i64 0), i64 16, i32 1, i1 false)
   ret void
 
-; DARWIN: test5:
+; DARWIN-LABEL: test5:
 ; DARWIN: movabsq	$7016996765293437281
 ; DARWIN: movabsq	$7016996765293437184
 }
diff --git a/test/CodeGen/X86/memset-2.ll b/test/CodeGen/X86/memset-2.ll
index b2bd72b..d0a3c7a 100644
--- a/test/CodeGen/X86/memset-2.ll
+++ b/test/CodeGen/X86/memset-2.ll
@@ -4,7 +4,7 @@ declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind
 
 define fastcc void @t1() nounwind {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: calll _memset
   call void @llvm.memset.p0i8.i32(i8* null, i8 0, i32 188, i32 1, i1 false)
   unreachable
@@ -12,7 +12,7 @@ entry:
 
 define fastcc void @t2(i8 signext %c) nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: calll _memset
   call void @llvm.memset.p0i8.i32(i8* undef, i8 %c, i32 76, i32 1, i1 false)
   unreachable
@@ -24,7 +24,7 @@ define void @t3(i8* nocapture %s, i8 %a) nounwind {
 entry:
   tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 8, i32 1, i1 false)
   ret void
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: imull $16843009
 }
 
@@ -32,7 +32,7 @@ define void @t4(i8* nocapture %s, i8 %a) nounwind {
 entry:
   tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 15, i32 1, i1 false)
   ret void
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: imull $16843009
 ; CHECK-NOT: imul
 ; CHECK: ret
diff --git a/test/CodeGen/X86/memset-sse-stack-realignment.ll b/test/CodeGen/X86/memset-sse-stack-realignment.ll
index df9de5d..d77a7ed 100644
--- a/test/CodeGen/X86/memset-sse-stack-realignment.ll
+++ b/test/CodeGen/X86/memset-sse-stack-realignment.ll
@@ -14,26 +14,26 @@ define void @test1(i32 %t) nounwind {
   call void @dummy(i8* %x)
   ret void
 
-; NOSSE: test1:
+; NOSSE-LABEL: test1:
 ; NOSSE-NOT: and
 ; NOSSE: movl $0
 
-; SSE1: test1:
+; SSE1-LABEL: test1:
 ; SSE1: andl $-16
 ; SSE1: movl %esp, %esi
 ; SSE1: movaps
 
-; SSE2: test1:
+; SSE2-LABEL: test1:
 ; SSE2: andl $-16
 ; SSE2: movl %esp, %esi
 ; SSE2: movaps
 
-; AVX1: test1:
+; AVX1-LABEL: test1:
 ; AVX1: andl $-32
 ; AVX1: movl %esp, %esi
 ; AVX1: vmovaps %ymm
 
-; AVX2: test1:
+; AVX2-LABEL: test1:
 ; AVX2: andl $-32
 ; AVX2: movl %esp, %esi
 ; AVX2: vmovaps %ymm
@@ -47,26 +47,26 @@ define void @test2(i32 %t) nounwind {
   call void @dummy(i8* %x)
   ret void
 
-; NOSSE: test2:
+; NOSSE-LABEL: test2:
 ; NOSSE-NOT: and
 ; NOSSE: movl $0
 
-; SSE1: test2:
+; SSE1-LABEL: test2:
 ; SSE1: andl $-16
 ; SSE1: movl %esp, %esi
 ; SSE1: movaps
 
-; SSE2: test2:
+; SSE2-LABEL: test2:
 ; SSE2: andl $-16
 ; SSE2: movl %esp, %esi
 ; SSE2: movaps
 
-; AVX1: test2:
+; AVX1-LABEL: test2:
 ; AVX1: andl $-16
 ; AVX1: movl %esp, %esi
 ; AVX1: vmovaps %xmm
 
-; AVX2: test2:
+; AVX2-LABEL: test2:
 ; AVX2: andl $-16
 ; AVX2: movl %esp, %esi
 ; AVX2: vmovaps %xmm
diff --git a/test/CodeGen/X86/misched-balance.ll b/test/CodeGen/X86/misched-balance.ll
index 2184d9e..5f6c501 100644
--- a/test/CodeGen/X86/misched-balance.ll
+++ b/test/CodeGen/X86/misched-balance.ll
@@ -1,5 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched \
-; RUN:          -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-machineinstrs | FileCheck %s
 ;
 ; Verify that misched resource/latency balancy heuristics are sane.
 
@@ -228,3 +227,51 @@ for.body:
 end:
   ret void
 }
+
+; A mildly interesting little block extracted from a cipher.  The
+; balanced heuristics are interesting here because we have resource,
+; latency, and register limits all at once. For now, simply check that
+; we don't use any callee-saves.
+; CHECK: @encpc1
+; CHECK: %entry
+; CHECK-NOT: push
+; CHECK-NOT: pop
+; CHECK: ret
+@a = external global i32, align 4
+@b = external global i32, align 4
+@c = external global i32, align 4
+@d = external global i32, align 4
+define i32 @encpc1() nounwind {
+entry:
+  %l1 = load i32* @a, align 16
+  %conv = shl i32 %l1, 8
+  %s5 = lshr i32 %l1, 8
+  %add = or i32 %conv, %s5
+  store i32 %add, i32* @b
+  %l6 = load i32* @a
+  %l7 = load i32* @c
+  %add.i = add i32 %l7, %l6
+  %idxprom.i = zext i32 %l7 to i64
+  %arrayidx.i = getelementptr inbounds i32* @d, i64 %idxprom.i
+  %l8 = load i32* %arrayidx.i
+  store i32 346, i32* @c
+  store i32 20021, i32* @d
+  %l9 = load i32* @a
+  store i32 %l8, i32* @a
+  store i32 %l9, i32* @b
+  store i32 %add.i, i32* @c
+  store i32 %l9, i32* @d
+  %cmp.i = icmp eq i32 %add.i, 0
+  %s10 = lshr i32 %l1, 16
+  %s12 = lshr i32 %l1, 24
+  %s14 = lshr i32 %l1, 30
+  br i1 %cmp.i, label %if, label %return
+if:
+  %sa = add i32 %s5, %s10
+  %sb = add i32 %sa, %s12
+  %sc = add i32 %sb, %s14
+  br label %return
+return:
+  %result = phi i32 [0, %entry], [%sc, %if]
+  ret i32 %result
+}
diff --git a/test/CodeGen/X86/misched-fusion.ll b/test/CodeGen/X86/misched-fusion.ll
new file mode 100644
index 0000000..859d92d
--- /dev/null
+++ b/test/CodeGen/X86/misched-fusion.ll
@@ -0,0 +1,108 @@
+; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx -disable-lsr -pre-RA-sched=source -enable-misched -verify-machineinstrs | FileCheck %s
+
+; Verify that TEST+JE are scheduled together.
+; CHECK: test_je
+; CHECK: %loop
+; CHECK: test
+; CHECK-NEXT: je
+define void @test_je() {
+entry:
+  br label %loop
+
+loop:
+  %var = phi i32* [ null, %entry ], [ %next.load, %loop1 ], [ %var, %loop2 ]
+  %next.ptr = phi i32** [ null, %entry ], [ %next.ptr, %loop1 ], [ %gep, %loop2 ]
+  br label %loop1
+
+loop1:
+  %cond = icmp eq i32* %var, null
+  %next.load = load i32** %next.ptr
+  br i1 %cond, label %loop, label %loop2
+
+loop2:                                           ; preds = %loop1
+  %gep = getelementptr inbounds i32** %next.ptr, i32 1
+  store i32* %next.load, i32** undef
+  br label %loop
+}
+
+; Verify that DEC+JE are scheduled together.
+; CHECK: dec_je
+; CHECK: %loop1
+; CHECK: dec
+; CHECK-NEXT: je
+define void @dec_je() {
+entry:
+  br label %loop
+
+loop:
+  %var = phi i32 [ 0, %entry ], [ %next.var, %loop1 ], [ %var2, %loop2 ]
+  %next.ptr = phi i32** [ null, %entry ], [ %next.ptr, %loop1 ], [ %gep, %loop2 ]
+  br label %loop1
+
+loop1:
+  %var2 = sub i32 %var, 1
+  %cond = icmp eq i32 %var2, 0
+  %next.load = load i32** %next.ptr
+  %next.var = load i32* %next.load
+  br i1 %cond, label %loop, label %loop2
+
+loop2:
+  %gep = getelementptr inbounds i32** %next.ptr, i32 1
+  store i32* %next.load, i32** undef
+  br label %loop
+}
+
+; DEC+JS should *not* be scheduled together.
+; CHECK: dec_js
+; CHECK: %loop1
+; CHECK: dec
+; CHECK: mov
+; CHECK: js
+define void @dec_js() {
+entry:
+  br label %loop2a
+
+loop2a:                                           ; preds = %loop1, %body, %entry
+  %var = phi i32 [ 0, %entry ], [ %next.var, %loop1 ], [ %var2, %loop2b ]
+  %next.ptr = phi i32** [ null, %entry ], [ %next.ptr, %loop1 ], [ %gep, %loop2b ]
+  br label %loop1
+
+loop1:                                            ; preds = %loop2a, %loop2b
+  %var2 = sub i32 %var, 1
+  %cond = icmp slt i32 %var2, 0
+  %next.load = load i32** %next.ptr
+  %next.var = load i32* %next.load
+  br i1 %cond, label %loop2a, label %loop2b
+
+loop2b:                                           ; preds = %loop1
+  %gep = getelementptr inbounds i32** %next.ptr, i32 1
+  store i32* %next.load, i32** undef
+  br label %loop2a
+}
+
+; Verify that CMP+JB are scheduled together.
+; CHECK: cmp_jb
+; CHECK: %loop1
+; CHECK: cmp
+; CHECK-NEXT: jb
+define void @cmp_jb(i32 %n) {
+entry:
+  br label %loop2a
+
+loop2a:                                           ; preds = %loop1, %body, %entry
+  %var = phi i32 [ 0, %entry ], [ %next.var, %loop1 ], [ %var2, %loop2b ]
+  %next.ptr = phi i32** [ null, %entry ], [ %next.ptr, %loop1 ], [ %gep, %loop2b ]
+  br label %loop1
+
+loop1:                                            ; preds = %loop2a, %loop2b
+  %var2 = sub i32 %var, 1
+  %cond = icmp ult i32 %var2, %n
+  %next.load = load i32** %next.ptr
+  %next.var = load i32* %next.load
+  br i1 %cond, label %loop2a, label %loop2b
+
+loop2b:                                           ; preds = %loop1
+  %gep = getelementptr inbounds i32** %next.ptr, i32 1
+  store i32* %next.load, i32** undef
+  br label %loop2a
+}
diff --git a/test/CodeGen/X86/misched-matmul.ll b/test/CodeGen/X86/misched-matmul.ll
index 15e8a0a..6b67607 100644
--- a/test/CodeGen/X86/misched-matmul.ll
+++ b/test/CodeGen/X86/misched-matmul.ll
@@ -7,7 +7,7 @@
 ; flag to disable it for this test case.
 ;
 ; CHECK: @wrap_mul4
-; CHECK: 30 regalloc - Number of spills inserted
+; CHECK: 22 regalloc - Number of spills inserted
 
 define void @wrap_mul4(double* nocapture %Out, [4 x double]* nocapture %A, [4 x double]* nocapture %B) #0 {
 entry:
diff --git a/test/CodeGen/X86/mmx-arg-passing.ll b/test/CodeGen/X86/mmx-arg-passing.ll
index b348512..3a0fb95 100644
--- a/test/CodeGen/X86/mmx-arg-passing.ll
+++ b/test/CodeGen/X86/mmx-arg-passing.ll
@@ -1,8 +1,5 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | grep mm0 | count 1
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | grep esp | count 2
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep xmm0
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | grep rdi
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | not grep movups
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+mmx | FileCheck %s -check-prefix=X86-32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | FileCheck %s -check-prefix=X86-64
 ;
 ; On Darwin x86-32, v8i8, v4i16, v2i32 values are passed in MM[0-2].
 ; On Darwin x86-32, v1i64 values are passed in memory.  In this example, they
@@ -15,6 +12,13 @@
 define void @t1(x86_mmx %v1) nounwind  {
 	store x86_mmx %v1, x86_mmx* @u1, align 8
 	ret void
+
+; X86-32-LABEL: t1:
+; X86-32: movq %mm0
+
+; X86-64-LABEL: t1:
+; X86-64: movdq2q %xmm0
+; X86-64: movq %mm0
 }
 
 @u2 = external global x86_mmx
@@ -23,5 +27,12 @@ define void @t2(<1 x i64> %v1) nounwind  {
         %tmp = bitcast <1 x i64> %v1 to x86_mmx
 	store x86_mmx %tmp, x86_mmx* @u2, align 8
 	ret void
+
+; X86-32-LABEL: t2:
+; X86-32: movl 4(%esp)
+; X86-32: movl 8(%esp)
+
+; X86-64-LABEL: t2:
+; X86-64: movq %rdi
 }
 
diff --git a/test/CodeGen/X86/mmx-builtins.ll b/test/CodeGen/X86/mmx-builtins.ll
index a8d33f4..f5b3f76 100644
--- a/test/CodeGen/X86/mmx-builtins.ll
+++ b/test/CodeGen/X86/mmx-builtins.ll
@@ -1337,3 +1337,11 @@ entry:
   %7 = extractelement <1 x i64> %6, i32 0
   ret i64 %7
 }
+
+define <4 x float> @test89(<4 x float> %a, x86_mmx %b) nounwind {
+; CHECK: cvtpi2ps
+  %c = tail call <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float> %a, x86_mmx %b)
+  ret <4 x float> %c
+}
+
+declare <4 x float> @llvm.x86.sse.cvtpi2ps(<4 x float>, x86_mmx) nounwind readnone
diff --git a/test/CodeGen/X86/mmx-shift.ll b/test/CodeGen/X86/mmx-shift.ll
index bafc754..c7c6e75 100644
--- a/test/CodeGen/X86/mmx-shift.ll
+++ b/test/CodeGen/X86/mmx-shift.ll
@@ -1,7 +1,5 @@
-; RUN: llc < %s -march=x86 -mattr=+mmx | grep psllq | grep 32
-; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep psllq | grep 32
-; RUN: llc < %s -march=x86 -mattr=+mmx | grep psrad
-; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep psrlw
+; RUN: llc < %s -march=x86 -mattr=+mmx | FileCheck %s
+; RUN: llc < %s -march=x86-64 -mattr=+mmx | FileCheck %s
 
 define i64 @t1(<1 x i64> %mm1) nounwind  {
 entry:
@@ -9,6 +7,9 @@ entry:
 	%tmp6 = tail call x86_mmx @llvm.x86.mmx.pslli.q( x86_mmx %tmp, i32 32 )		; <x86_mmx> [#uses=1]
         %retval1112 = bitcast x86_mmx %tmp6 to i64
 	ret i64 %retval1112
+
+; CHECK-LABEL: t1:
+; CHECK: psllq $32
 }
 
 declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32) nounwind readnone 
@@ -18,6 +19,9 @@ entry:
 	%tmp7 = tail call x86_mmx @llvm.x86.mmx.psra.d( x86_mmx %mm1, x86_mmx %mm2 ) nounwind readnone 		; <x86_mmx> [#uses=1]
         %retval1112 = bitcast x86_mmx %tmp7 to i64
 	ret i64 %retval1112
+
+; CHECK-LABEL: t2:
+; CHECK: psrad
 }
 
 declare x86_mmx @llvm.x86.mmx.psra.d(x86_mmx, x86_mmx) nounwind readnone 
@@ -27,6 +31,9 @@ entry:
 	%tmp8 = tail call x86_mmx @llvm.x86.mmx.psrli.w( x86_mmx %mm1, i32 %bits ) nounwind readnone 		; <x86_mmx> [#uses=1]
         %retval1314 = bitcast x86_mmx %tmp8 to i64
 	ret i64 %retval1314
+
+; CHECK-LABEL: t3:
+; CHECK: psrlw
 }
 
 declare x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx, i32) nounwind readnone 
diff --git a/test/CodeGen/X86/movbe.ll b/test/CodeGen/X86/movbe.ll
index 3d3d8cf..aa58c10 100644
--- a/test/CodeGen/X86/movbe.ll
+++ b/test/CodeGen/X86/movbe.ll
@@ -7,7 +7,7 @@ define void @test1(i32* nocapture %x, i32 %y) nounwind {
   %bswap = call i32 @llvm.bswap.i32(i32 %y)
   store i32 %bswap, i32* %x, align 4
   ret void
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: movbel	%esi, (%rdi)
 }
 
@@ -15,7 +15,7 @@ define i32 @test2(i32* %x) nounwind {
   %load = load i32* %x, align 4
   %bswap = call i32 @llvm.bswap.i32(i32 %load)
   ret i32 %bswap
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movbel	(%rdi), %eax
 }
 
@@ -23,7 +23,7 @@ define void @test3(i64* %x, i64 %y) nounwind {
   %bswap = call i64 @llvm.bswap.i64(i64 %y)
   store i64 %bswap, i64* %x, align 8
   ret void
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: movbeq	%rsi, (%rdi)
 }
 
@@ -31,6 +31,6 @@ define i64 @test4(i64* %x) nounwind {
   %load = load i64* %x, align 8
   %bswap = call i64 @llvm.bswap.i64(i64 %load)
   ret i64 %bswap
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: movbeq	(%rdi), %rax
 }
diff --git a/test/CodeGen/X86/movgs.ll b/test/CodeGen/X86/movgs.ll
index bb42734..d3930fa 100644
--- a/test/CodeGen/X86/movgs.ll
+++ b/test/CodeGen/X86/movgs.ll
@@ -8,12 +8,12 @@ entry:
 	%tmp1 = load i32* %tmp		; <i32> [#uses=1]
 	ret i32 %tmp1
 }
-; X32: test1:
+; X32-LABEL: test1:
 ; X32: 	movl	%gs:196, %eax
 ; X32: 	movl	(%eax), %eax
 ; X32: 	ret
 
-; X64: test1:
+; X64-LABEL: test1:
 ; X64: 	movq	%gs:320, %rax
 ; X64: 	movl	(%rax), %eax
 ; X64: 	ret
@@ -26,11 +26,11 @@ entry:
 }
 
 ; rdar://8453210
-; X32: test2:
+; X32-LABEL: test2:
 ; X32: movl	{{.*}}(%esp), %eax
 ; X32: calll	*%gs:(%eax)
 
-; X64: test2:
+; X64-LABEL: test2:
 ; X64: callq	*%gs:([[A0:%rdi|%rcx]])
 
 
@@ -45,12 +45,12 @@ entry:
   %3 = bitcast <4 x i32> %2 to <2 x i64>
   ret <2 x i64> %3
   
-; X32: pmovsxwd_1:
+; X32-LABEL: pmovsxwd_1:
 ; X32: 	movl	4(%esp), %eax
 ; X32: 	pmovsxwd	%gs:(%eax), %xmm0
 ; X32: 	ret
 
-; X64: pmovsxwd_1:
+; X64-LABEL: pmovsxwd_1:
 ; X64:	pmovsxwd	%gs:([[A0]]), %xmm0
 ; X64:	ret
 }
@@ -66,7 +66,7 @@ entry:
 	%tmp4 = add i32 %tmp1, %tmp3
 	ret i32 %tmp4
 }
-; X32: test_no_cse:
+; X32-LABEL: test_no_cse:
 ; X32: 	movl	%gs:196
 ; X32: 	movl	%fs:196
 ; X32: 	ret
diff --git a/test/CodeGen/X86/movmsk.ll b/test/CodeGen/X86/movmsk.ll
index 928ad03..2520662 100644
--- a/test/CodeGen/X86/movmsk.ll
+++ b/test/CodeGen/X86/movmsk.ll
@@ -83,7 +83,7 @@ define void @float_call_signbit(double %n) {
 entry:
 ; FIXME: This should also use movmskps; we don't form the FGETSIGN node
 ; in this case, though.
-; CHECK: float_call_signbit:
+; CHECK-LABEL: float_call_signbit:
 ; CHECK: movd %xmm0, %rdi
 ; FIXME
   %t0 = bitcast double %n to i64
@@ -99,7 +99,7 @@ declare void @float_call_signbit_callee(i1 zeroext)
 
 define i32 @t1(<4 x float> %x, i32* nocapture %indexTable) nounwind uwtable readonly ssp {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: movmskps
 ; CHECK-NOT: movslq
   %0 = tail call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %x) nounwind
@@ -111,7 +111,7 @@ entry:
 
 define i32 @t2(<4 x float> %x, i32* nocapture %indexTable) nounwind uwtable readonly ssp {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: movmskpd
 ; CHECK-NOT: movslq
   %0 = bitcast <4 x float> %x to <2 x double>
diff --git a/test/CodeGen/X86/ms-inline-asm.ll b/test/CodeGen/X86/ms-inline-asm.ll
index 5048a93..5e7ba37 100644
--- a/test/CodeGen/X86/ms-inline-asm.ll
+++ b/test/CodeGen/X86/ms-inline-asm.ll
@@ -75,7 +75,7 @@ define void @t19() nounwind {
 entry:
   call void asm sideeffect inteldialect "call $0", "r,~{dirflag},~{fpsr},~{flags}"(void ()* @t19_helper) nounwind
   ret void
-; CHECK: t19:
+; CHECK-LABEL: t19:
 ; CHECK: movl %esp, %ebp
 ; CHECK: movl ${{_?}}t19_helper, %eax
 ; CHECK: {{## InlineAsm Start|#APP}}
@@ -94,7 +94,7 @@ entry:
   call void asm sideeffect inteldialect "mov dword ptr $0, edi", "=*m,~{dirflag},~{fpsr},~{flags}"(i32** %res) nounwind
   %0 = load i32** %res, align 4
   ret i32* %0
-; CHECK: t30:
+; CHECK-LABEL: t30:
 ; CHECK: movl %esp, %ebp
 ; CHECK: {{## InlineAsm Start|#APP}}
 ; CHECK: .intel_syntax
diff --git a/test/CodeGen/X86/narrow-shl-cst.ll b/test/CodeGen/X86/narrow-shl-cst.ll
index a404f34..40b9760 100644
--- a/test/CodeGen/X86/narrow-shl-cst.ll
+++ b/test/CodeGen/X86/narrow-shl-cst.ll
@@ -5,7 +5,7 @@ define i32 @test1(i32 %x) nounwind {
   %and = shl i32 %x, 10
   %shl = and i32 %and, 31744
   ret i32 %shl
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: andl $31
 ; CHECK: shll $10
 }
@@ -14,7 +14,7 @@ define i32 @test2(i32 %x) nounwind {
   %or = shl i32 %x, 10
   %shl = or i32 %or, 31744
   ret i32 %shl
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: orl $31
 ; CHECK: shll $10
 }
@@ -23,7 +23,7 @@ define i32 @test3(i32 %x) nounwind {
   %xor = shl i32 %x, 10
   %shl = xor i32 %xor, 31744
   ret i32 %shl
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: xorl $31
 ; CHECK: shll $10
 }
@@ -32,7 +32,7 @@ define i64 @test4(i64 %x) nounwind {
   %and = shl i64 %x, 40
   %shl = and i64 %and, 264982302294016
   ret i64 %shl
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: andq $241
 ; CHECK: shlq $40
 }
@@ -41,7 +41,7 @@ define i64 @test5(i64 %x) nounwind {
   %and = shl i64 %x, 40
   %shl = and i64 %and, 34084860461056
   ret i64 %shl
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: andq $31
 ; CHECK: shlq $40
 }
@@ -50,7 +50,7 @@ define i64 @test6(i64 %x) nounwind {
   %and = shl i64 %x, 32
   %shl = and i64 %and, -281474976710656
   ret i64 %shl
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: andq $-65536
 ; CHECK: shlq $32
 }
@@ -59,7 +59,7 @@ define i64 @test7(i64 %x) nounwind {
   %or = shl i64 %x, 40
   %shl = or i64 %or, 264982302294016
   ret i64 %shl
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: orq $241
 ; CHECK: shlq $40
 }
@@ -68,7 +68,7 @@ define i64 @test8(i64 %x) nounwind {
   %or = shl i64 %x, 40
   %shl = or i64 %or, 34084860461056
   ret i64 %shl
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: orq $31
 ; CHECK: shlq $40
 }
@@ -77,7 +77,7 @@ define i64 @test9(i64 %x) nounwind {
   %xor = shl i64 %x, 40
   %shl = xor i64 %xor, 264982302294016
   ret i64 %shl
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: orq $241
 ; CHECK: shlq $40
 }
@@ -86,7 +86,7 @@ define i64 @test10(i64 %x) nounwind {
   %xor = shl i64 %x, 40
   %shl = xor i64 %xor, 34084860461056
   ret i64 %shl
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: xorq $31
 ; CHECK: shlq $40
 }
@@ -95,7 +95,7 @@ define i64 @test11(i64 %x) nounwind {
   %xor = shl i64 %x, 33
   %shl = xor i64 %xor, -562949953421312
   ret i64 %shl
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK: xorq $-65536
 ; CHECK: shlq $33
 }
diff --git a/test/CodeGen/X86/narrow-shl-load.ll b/test/CodeGen/X86/narrow-shl-load.ll
index 7822453..30387925 100644
--- a/test/CodeGen/X86/narrow-shl-load.ll
+++ b/test/CodeGen/X86/narrow-shl-load.ll
@@ -33,7 +33,7 @@ while.end:                                        ; preds = %while.cond
 
 ; DAGCombiner shouldn't fold the sdiv (ashr) away.
 ; rdar://8636812
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK:   sarl
 
 define i32 @test2() nounwind {
diff --git a/test/CodeGen/X86/narrow_op-1.ll b/test/CodeGen/X86/narrow_op-1.ll
index 18f1108..89ae3f1 100644
--- a/test/CodeGen/X86/narrow_op-1.ll
+++ b/test/CodeGen/X86/narrow_op-1.ll
@@ -1,7 +1,4 @@
-; RUN: llc < %s -march=x86-64 | grep orb | count 1
-; RUN: llc < %s -march=x86-64 | grep orb | grep 1
-; RUN: llc < %s -march=x86-64 | grep orl | count 1
-; RUN: llc < %s -march=x86-64 | grep orl | grep 16842752
+; RUN: llc < %s -march=x86-64 | FileCheck %s
 
 	%struct.bf = type { i64, i16, i16, i32 }
 @bfi = common global %struct.bf zeroinitializer, align 16
@@ -12,6 +9,10 @@ entry:
 	%1 = or i32 %0, 65536
 	store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
 	ret void
+
+; CHECK-LABEL: t1:
+; CHECK: orb $1
+; CHECK-NEXT: ret
 }
 
 define void @t2() nounwind optsize ssp {
@@ -20,4 +21,8 @@ entry:
 	%1 = or i32 %0, 16842752
 	store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
 	ret void
+
+; CHECK-LABEL: t2:
+; CHECK: orl $16842752
+; CHECK-NEXT: ret
 }
diff --git a/test/CodeGen/X86/neg_cmp.ll b/test/CodeGen/X86/neg_cmp.ll
index 866514e..7905072 100644
--- a/test/CodeGen/X86/neg_cmp.ll
+++ b/test/CodeGen/X86/neg_cmp.ll
@@ -4,7 +4,7 @@
 ; PR12545
 define void @f(i32 %x, i32 %y) nounwind uwtable ssp {
 entry:
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK-NOT: neg
 ; CHECK: add
   %sub = sub i32 0, %y
diff --git a/test/CodeGen/X86/no-cmov.ll b/test/CodeGen/X86/no-cmov.ll
index 62d73b0..e13edf2 100644
--- a/test/CodeGen/X86/no-cmov.ll
+++ b/test/CodeGen/X86/no-cmov.ll
@@ -6,6 +6,6 @@ define i32 @test1(i32 %g, i32* %j) {
   %retval.0 = select i1 %tobool, i32 1, i32 %cmp
   ret i32 %retval.0
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: cmov
 }
diff --git a/test/CodeGen/X86/non-lazy-bind.ll b/test/CodeGen/X86/non-lazy-bind.ll
index f729658..546a136 100644
--- a/test/CodeGen/X86/non-lazy-bind.ll
+++ b/test/CodeGen/X86/non-lazy-bind.ll
@@ -3,7 +3,7 @@
 declare void @lazy() nonlazybind
 declare void @not()
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK:  callq _not
 ; CHECK:  callq *_lazy@GOTPCREL(%rip)
 define void @foo() nounwind {
@@ -12,14 +12,14 @@ define void @foo() nounwind {
   ret void
 }
 
-; CHECK: tail_call_regular:
+; CHECK-LABEL: tail_call_regular:
 ; CHECK:   jmp _not
 define void @tail_call_regular() nounwind {
   tail call void @not()
   ret void
 }
 
-; CHECK: tail_call_eager:
+; CHECK-LABEL: tail_call_eager:
 ; CHECK:   jmpq *_lazy@GOTPCREL(%rip)
 define void @tail_call_eager() nounwind {
   tail call void @lazy()
diff --git a/test/CodeGen/X86/nonconst-static-ev.ll b/test/CodeGen/X86/nonconst-static-ev.ll
new file mode 100644
index 0000000..f852cae
--- /dev/null
+++ b/test/CodeGen/X86/nonconst-static-ev.ll
@@ -0,0 +1,9 @@
+; RUN: not llc -march=x86 -mtriple=x86_64-linux-gnu < %s 2> %t
+; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+; REQUIRES: shell
+
+@0 = global i8 extractvalue ([1 x i8] select (i1 ptrtoint (i32* @1 to i1), [1 x i8] [ i8 1 ], [1 x i8] [ i8 2 ]), 0)
+@1 = external global i32
+
+; CHECK-ERRORS: Unsupported expression in static initializer: extractvalue
+
diff --git a/test/CodeGen/X86/nonconst-static-iv.ll b/test/CodeGen/X86/nonconst-static-iv.ll
new file mode 100644
index 0000000..8fad39b
--- /dev/null
+++ b/test/CodeGen/X86/nonconst-static-iv.ll
@@ -0,0 +1,9 @@
+; RUN: not llc -march=x86 -mtriple=x86_64-linux-gnu < %s 2> %t
+; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+; REQUIRES: shell
+
+@0 = global i8 insertvalue( { i8 } select (i1 ptrtoint (i32* @1 to i1), { i8 } { i8 1 }, { i8 } { i8 2 }), i8 0, 0)
+@1 = external global i32
+
+; CHECK-ERRORS: Unsupported expression in static initializer: insertvalue
+
diff --git a/test/CodeGen/X86/nosse-error1.ll b/test/CodeGen/X86/nosse-error1.ll
index cddff3f..291379e 100644
--- a/test/CodeGen/X86/nosse-error1.ll
+++ b/test/CodeGen/X86/nosse-error1.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mattr=-sse 2>&1 | FileCheck --check-prefix NOSSE %s
+; RUN: not  llc < %s -march=x86-64 -mattr=-sse 2>&1 | FileCheck --check-prefix NOSSE %s
 ; RUN: llc < %s -march=x86-64 | FileCheck %s
 
 ; NOSSE: {{SSE register return with SSE disabled}}
diff --git a/test/CodeGen/X86/nosse-error2.ll b/test/CodeGen/X86/nosse-error2.ll
index fc9ba01..a7cee2d 100644
--- a/test/CodeGen/X86/nosse-error2.ll
+++ b/test/CodeGen/X86/nosse-error2.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mcpu=i686 -mattr=-sse 2>&1 | FileCheck --check-prefix NOSSE %s
+; RUN: not llc < %s -march=x86 -mcpu=i686 -mattr=-sse 2>&1 | FileCheck --check-prefix NOSSE %s
 ; RUN: llc < %s -march=x86 -mcpu=i686 -mattr=+sse | FileCheck %s
 
 ; NOSSE: {{SSE register return with SSE disabled}}
diff --git a/test/CodeGen/X86/optimize-max-3.ll b/test/CodeGen/X86/optimize-max-3.ll
index d092916..1b65373 100644
--- a/test/CodeGen/X86/optimize-max-3.ll
+++ b/test/CodeGen/X86/optimize-max-3.ll
@@ -3,7 +3,7 @@
 
 ; LSR's OptimizeMax should eliminate the select (max).
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NOT: cmov
 ; CHECK: jle
 
@@ -37,7 +37,7 @@ for.end:                                          ; preds = %for.body, %entry
 ; OptimizeMax should handle this case.
 ; PR7454
 
-;      CHECK: _Z18GenerateStatusPagei:
+;      CHECK-LABEL: _Z18GenerateStatusPagei:
 
 ;      CHECK:         jle
 ;  CHECK-NOT:         cmov
diff --git a/test/CodeGen/X86/or-address.ll b/test/CodeGen/X86/or-address.ll
index f866e41..6bea864 100644
--- a/test/CodeGen/X86/or-address.ll
+++ b/test/CodeGen/X86/or-address.ll
@@ -46,7 +46,7 @@ return:                                           ; preds = %bb
   ret void
 }
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: 	movl	%{{.*}},   (%[[RDI:...]],%[[RCX:...]],4)
 ; CHECK:	movl	%{{.*}},  8(%[[RDI]],%[[RCX]],4)
 ; CHECK:	movl	%{{.*}},  4(%[[RDI]],%[[RCX]],4)
diff --git a/test/CodeGen/X86/palignr-2.ll b/test/CodeGen/X86/palignr-2.ll
index 116d4c7..4df9a22 100644
--- a/test/CodeGen/X86/palignr-2.ll
+++ b/test/CodeGen/X86/palignr-2.ll
@@ -7,7 +7,7 @@
 
 define void @t1(<2 x i64> %a, <2 x i64> %b) nounwind ssp {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; palignr $3, %xmm1, %xmm0
   %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i8 24) nounwind readnone
   store <2 x i64> %0, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16
@@ -18,7 +18,7 @@ declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwin
 
 define void @t2() nounwind ssp {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; palignr $4, _b, %xmm0
   %0 = load <2 x i64>* bitcast ([4 x i32]* @b to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1]
   %1 = load <2 x i64>* bitcast ([4 x i32]* @a to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1]
diff --git a/test/CodeGen/X86/palignr.ll b/test/CodeGen/X86/palignr.ll
index 6875fb3..c76cbbe 100644
--- a/test/CodeGen/X86/palignr.ll
+++ b/test/CodeGen/X86/palignr.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck --check-prefix=YONAH %s
 
 define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: pshufd
 ; CHECK-YONAH: pshufd
   %C = shufflevector <4 x i32> %A, <4 x i32> undef, <4 x i32> < i32 1, i32 2, i32 3, i32 0 >
@@ -10,7 +10,7 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
 }
 
 define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: palignr
 ; CHECK-YONAH: shufps
   %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 3, i32 4 >
@@ -18,42 +18,42 @@ define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
 }
 
 define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: palignr
   %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 undef, i32 4 >
 	ret <4 x i32> %C
 }
 
 define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: palignr
   %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 >
 	ret <4 x i32> %C
 }
 
 define <4 x float> @test5(<4 x float> %A, <4 x float> %B) nounwind {
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: palignr
   %C = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 >
 	ret <4 x float> %C
 }
 
 define <8 x i16> @test6(<8 x i16> %A, <8 x i16> %B) nounwind {
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: palignr
   %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 3, i32 4, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10 >
 	ret <8 x i16> %C
 }
 
 define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) nounwind {
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: palignr
   %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 undef, i32 6, i32 undef, i32 8, i32 9, i32 10, i32 11, i32 12 >
 	ret <8 x i16> %C
 }
 
 define <16 x i8> @test8(<16 x i8> %A, <16 x i8> %B) nounwind {
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: palignr
   %C = shufflevector <16 x i8> %A, <16 x i8> %B, <16 x i32> < i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20 >
 	ret <16 x i8> %C
@@ -64,7 +64,7 @@ define <16 x i8> @test8(<16 x i8> %A, <16 x i8> %B) nounwind {
 ; incorrectly.  In particular, one of the operands of the palignr node
 ; was an UNDEF.)
 define <8 x i16> @test9(<8 x i16> %A, <8 x i16> %B) nounwind {
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK-NOT: palignr
 ; CHECK: pshufb
   %C = shufflevector <8 x i16> %B, <8 x i16> %A, <8 x i32> < i32 undef, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0 >
diff --git a/test/CodeGen/X86/pass-three.ll b/test/CodeGen/X86/pass-three.ll
index 23005c7..39ff69a 100644
--- a/test/CodeGen/X86/pass-three.ll
+++ b/test/CodeGen/X86/pass-three.ll
@@ -11,6 +11,6 @@ entry:
   ret { i8*, i64, i64* } %2
 }
 
-; CHECK: copy_3:
+; CHECK-LABEL: copy_3:
 ; CHECK-NOT: (%rdi)
 ; CHECK: ret
diff --git a/test/CodeGen/X86/peep-setb.ll b/test/CodeGen/X86/peep-setb.ll
index 0bab789..adae8ac 100644
--- a/test/CodeGen/X86/peep-setb.ll
+++ b/test/CodeGen/X86/peep-setb.ll
@@ -5,7 +5,7 @@ define i8 @test1(i8 %a, i8 %b) nounwind {
   %cond = zext i1 %cmp to i8
   %add = add i8 %cond, %b
   ret i8 %add
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: adcb $0
 }
 
@@ -14,7 +14,7 @@ define i32 @test2(i32 %a, i32 %b) nounwind {
   %cond = zext i1 %cmp to i32
   %add = add i32 %cond, %b
   ret i32 %add
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: adcl $0
 }
 
@@ -23,7 +23,7 @@ define i64 @test3(i64 %a, i64 %b) nounwind {
   %conv = zext i1 %cmp to i64
   %add = add i64 %conv, %b
   ret i64 %add
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: adcq $0
 }
 
@@ -32,7 +32,7 @@ define i8 @test4(i8 %a, i8 %b) nounwind {
   %cond = zext i1 %cmp to i8
   %sub = sub i8 %b, %cond
   ret i8 %sub
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: sbbb $0
 }
 
@@ -41,7 +41,7 @@ define i32 @test5(i32 %a, i32 %b) nounwind {
   %cond = zext i1 %cmp to i32
   %sub = sub i32 %b, %cond
   ret i32 %sub
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: sbbl $0
 }
 
@@ -50,7 +50,7 @@ define i64 @test6(i64 %a, i64 %b) nounwind {
   %conv = zext i1 %cmp to i64
   %sub = sub i64 %b, %conv
   ret i64 %sub
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: sbbq $0
 }
 
@@ -59,7 +59,7 @@ define i8 @test7(i8 %a, i8 %b) nounwind {
   %cond = sext i1 %cmp to i8
   %sub = sub i8 %b, %cond
   ret i8 %sub
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: adcb $0
 }
 
@@ -68,7 +68,7 @@ define i32 @test8(i32 %a, i32 %b) nounwind {
   %cond = sext i1 %cmp to i32
   %sub = sub i32 %b, %cond
   ret i32 %sub
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: adcl $0
 }
 
@@ -77,6 +77,6 @@ define i64 @test9(i64 %a, i64 %b) nounwind {
   %conv = sext i1 %cmp to i64
   %sub = sub i64 %b, %conv
   ret i64 %sub
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: adcq $0
 }
diff --git a/test/CodeGen/X86/peep-test-3.ll b/test/CodeGen/X86/peep-test-3.ll
index a379980..b3d4f58 100644
--- a/test/CodeGen/X86/peep-test-3.ll
+++ b/test/CodeGen/X86/peep-test-3.ll
@@ -3,7 +3,7 @@
 
 ; LLVM should omit the testl and use the flags result from the orl.
 
-; CHECK: or:
+; CHECK-LABEL: or:
 define void @or(float* %A, i32 %IA, i32 %N) nounwind {
 entry:
   %0 = ptrtoint float* %A to i32                  ; <i32> [#uses=1]
@@ -22,7 +22,7 @@ bb:                                               ; preds = %entry
 return:                                           ; preds = %entry
   ret void
 }
-; CHECK: xor:
+; CHECK-LABEL: xor:
 define void @xor(float* %A, i32 %IA, i32 %N) nounwind {
 entry:
   %0 = ptrtoint float* %A to i32                  ; <i32> [#uses=1]
@@ -41,7 +41,7 @@ bb:                                               ; preds = %entry
 return:                                           ; preds = %entry
   ret void
 }
-; CHECK: and:
+; CHECK-LABEL: and:
 define void @and(float* %A, i32 %IA, i32 %N, i8* %p) nounwind {
 entry:
   store i8 0, i8* %p
@@ -67,7 +67,7 @@ return:                                           ; preds = %entry
 
 ; Just like @and, but without the trunc+store. This should use a testb
 ; instead of an andl.
-; CHECK: test:
+; CHECK-LABEL: test:
 define void @test(float* %A, i32 %IA, i32 %N, i8* %p) nounwind {
 entry:
   store i8 0, i8* %p
diff --git a/test/CodeGen/X86/peep-test-4.ll b/test/CodeGen/X86/peep-test-4.ll
index a1eea00..884ee7c 100644
--- a/test/CodeGen/X86/peep-test-4.ll
+++ b/test/CodeGen/X86/peep-test-4.ll
@@ -2,7 +2,7 @@
 declare void @foo(i32)
 declare void @foo64(i64)
 
-; CHECK: neg:
+; CHECK-LABEL: neg:
 ; CHECK: negl %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -20,7 +20,7 @@ return:
   ret void
 }
 
-; CHECK: sar:
+; CHECK-LABEL: sar:
 ; CHECK: sarl %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -38,7 +38,7 @@ return:
   ret void
 }
 
-; CHECK: shr:
+; CHECK-LABEL: shr:
 ; CHECK: shrl %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -56,7 +56,7 @@ return:
   ret void
 }
 
-; CHECK: shri:
+; CHECK-LABEL: shri:
 ; CHECK: shrl $3, %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -74,7 +74,7 @@ return:
   ret void
 }
 
-; CHECK: shl:
+; CHECK-LABEL: shl:
 ; CHECK: addl %edi, %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -92,7 +92,7 @@ return:
   ret void
 }
 
-; CHECK: shli:
+; CHECK-LABEL: shli:
 ; CHECK: shll $4, %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -110,7 +110,7 @@ return:
   ret void
 }
 
-; CHECK: adc:
+; CHECK-LABEL: adc:
 ; CHECK: movabsq $-9223372036854775808, %rax
 ; CHECK-NEXT: addq  %rdi, %rax
 ; CHECK-NEXT: adcq  $0, %rsi
@@ -122,7 +122,7 @@ define zeroext i1 @adc(i128 %x) nounwind {
   ret i1 %cmp
 }
 
-; CHECK: sbb:
+; CHECK-LABEL: sbb:
 ; CHECK: cmpq  %rdx, %rdi
 ; CHECK-NEXT: sbbq  %rcx, %rsi
 ; CHECK-NEXT: setns %al
@@ -133,7 +133,7 @@ define zeroext i1 @sbb(i128 %x, i128 %y) nounwind {
   ret i1 %cmp
 }
 
-; CHECK: andn:
+; CHECK-LABEL: andn:
 ; CHECK: andnl   %esi, %edi, %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -152,7 +152,7 @@ return:
   ret void
 }
 
-; CHECK: bextr:
+; CHECK-LABEL: bextr:
 ; CHECK: bextrl   %esi, %edi, %edi
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
@@ -171,7 +171,7 @@ return:
   ret void
 }
 
-; CHECK: popcnt:
+; CHECK-LABEL: popcnt:
 ; CHECK: popcntl
 ; CHECK-NEXT: je
 ; CHECK: jmp foo
diff --git a/test/CodeGen/X86/phaddsub.ll b/test/CodeGen/X86/phaddsub.ll
index 62d85f7..17e7e1d 100644
--- a/test/CodeGen/X86/phaddsub.ll
+++ b/test/CodeGen/X86/phaddsub.ll
@@ -1,10 +1,10 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+ssse3,-avx | FileCheck %s -check-prefix=SSSE3
 ; RUN: llc < %s -march=x86-64 -mattr=-ssse3,+avx | FileCheck %s -check-prefix=AVX
 
-; SSSE3: phaddw1:
+; SSSE3-LABEL: phaddw1:
 ; SSSE3-NOT: vphaddw
 ; SSSE3: phaddw
-; AVX: phaddw1:
+; AVX-LABEL: phaddw1:
 ; AVX: vphaddw
 define <8 x i16> @phaddw1(<8 x i16> %x, <8 x i16> %y) {
   %a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
@@ -13,10 +13,10 @@ define <8 x i16> @phaddw1(<8 x i16> %x, <8 x i16> %y) {
   ret <8 x i16> %r
 }
 
-; SSSE3: phaddw2:
+; SSSE3-LABEL: phaddw2:
 ; SSSE3-NOT: vphaddw
 ; SSSE3: phaddw
-; AVX: phaddw2:
+; AVX-LABEL: phaddw2:
 ; AVX: vphaddw
 define <8 x i16> @phaddw2(<8 x i16> %x, <8 x i16> %y) {
   %a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 2, i32 5, i32 6, i32 9, i32 10, i32 13, i32 14>
@@ -25,10 +25,10 @@ define <8 x i16> @phaddw2(<8 x i16> %x, <8 x i16> %y) {
   ret <8 x i16> %r
 }
 
-; SSSE3: phaddd1:
+; SSSE3-LABEL: phaddd1:
 ; SSSE3-NOT: vphaddd
 ; SSSE3: phaddd
-; AVX: phaddd1:
+; AVX-LABEL: phaddd1:
 ; AVX: vphaddd
 define <4 x i32> @phaddd1(<4 x i32> %x, <4 x i32> %y) {
   %a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -37,10 +37,10 @@ define <4 x i32> @phaddd1(<4 x i32> %x, <4 x i32> %y) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phaddd2:
+; SSSE3-LABEL: phaddd2:
 ; SSSE3-NOT: vphaddd
 ; SSSE3: phaddd
-; AVX: phaddd2:
+; AVX-LABEL: phaddd2:
 ; AVX: vphaddd
 define <4 x i32> @phaddd2(<4 x i32> %x, <4 x i32> %y) {
   %a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 2, i32 5, i32 6>
@@ -49,10 +49,10 @@ define <4 x i32> @phaddd2(<4 x i32> %x, <4 x i32> %y) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phaddd3:
+; SSSE3-LABEL: phaddd3:
 ; SSSE3-NOT: vphaddd
 ; SSSE3: phaddd
-; AVX: phaddd3:
+; AVX-LABEL: phaddd3:
 ; AVX: vphaddd
 define <4 x i32> @phaddd3(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
@@ -61,10 +61,10 @@ define <4 x i32> @phaddd3(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phaddd4:
+; SSSE3-LABEL: phaddd4:
 ; SSSE3-NOT: vphaddd
 ; SSSE3: phaddd
-; AVX: phaddd4:
+; AVX-LABEL: phaddd4:
 ; AVX: vphaddd
 define <4 x i32> @phaddd4(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
@@ -73,10 +73,10 @@ define <4 x i32> @phaddd4(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phaddd5:
+; SSSE3-LABEL: phaddd5:
 ; SSSE3-NOT: vphaddd
 ; SSSE3: phaddd
-; AVX: phaddd5:
+; AVX-LABEL: phaddd5:
 ; AVX: vphaddd
 define <4 x i32> @phaddd5(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 undef, i32 undef>
@@ -85,10 +85,10 @@ define <4 x i32> @phaddd5(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phaddd6:
+; SSSE3-LABEL: phaddd6:
 ; SSSE3-NOT: vphaddd
 ; SSSE3: phaddd
-; AVX: phaddd6:
+; AVX-LABEL: phaddd6:
 ; AVX: vphaddd
 define <4 x i32> @phaddd6(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
@@ -97,10 +97,10 @@ define <4 x i32> @phaddd6(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phaddd7:
+; SSSE3-LABEL: phaddd7:
 ; SSSE3-NOT: vphaddd
 ; SSSE3: phaddd
-; AVX: phaddd7:
+; AVX-LABEL: phaddd7:
 ; AVX: vphaddd
 define <4 x i32> @phaddd7(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 undef>
@@ -109,10 +109,10 @@ define <4 x i32> @phaddd7(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phsubw1:
+; SSSE3-LABEL: phsubw1:
 ; SSSE3-NOT: vphsubw
 ; SSSE3: phsubw
-; AVX: phsubw1:
+; AVX-LABEL: phsubw1:
 ; AVX: vphsubw
 define <8 x i16> @phsubw1(<8 x i16> %x, <8 x i16> %y) {
   %a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
@@ -121,10 +121,10 @@ define <8 x i16> @phsubw1(<8 x i16> %x, <8 x i16> %y) {
   ret <8 x i16> %r
 }
 
-; SSSE3: phsubd1:
+; SSSE3-LABEL: phsubd1:
 ; SSSE3-NOT: vphsubd
 ; SSSE3: phsubd
-; AVX: phsubd1:
+; AVX-LABEL: phsubd1:
 ; AVX: vphsubd
 define <4 x i32> @phsubd1(<4 x i32> %x, <4 x i32> %y) {
   %a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
@@ -133,10 +133,10 @@ define <4 x i32> @phsubd1(<4 x i32> %x, <4 x i32> %y) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phsubd2:
+; SSSE3-LABEL: phsubd2:
 ; SSSE3-NOT: vphsubd
 ; SSSE3: phsubd
-; AVX: phsubd2:
+; AVX-LABEL: phsubd2:
 ; AVX: vphsubd
 define <4 x i32> @phsubd2(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
@@ -145,10 +145,10 @@ define <4 x i32> @phsubd2(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phsubd3:
+; SSSE3-LABEL: phsubd3:
 ; SSSE3-NOT: vphsubd
 ; SSSE3: phsubd
-; AVX: phsubd3:
+; AVX-LABEL: phsubd3:
 ; AVX: vphsubd
 define <4 x i32> @phsubd3(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
@@ -157,10 +157,10 @@ define <4 x i32> @phsubd3(<4 x i32> %x) {
   ret <4 x i32> %r
 }
 
-; SSSE3: phsubd4:
+; SSSE3-LABEL: phsubd4:
 ; SSSE3-NOT: vphsubd
 ; SSSE3: phsubd
-; AVX: phsubd4:
+; AVX-LABEL: phsubd4:
 ; AVX: vphsubd
 define <4 x i32> @phsubd4(<4 x i32> %x) {
   %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
diff --git a/test/CodeGen/X86/phys_subreg_coalesce-3.ll b/test/CodeGen/X86/phys_subreg_coalesce-3.ll
index 2a20e7a..6eb97c3 100644
--- a/test/CodeGen/X86/phys_subreg_coalesce-3.ll
+++ b/test/CodeGen/X86/phys_subreg_coalesce-3.ll
@@ -7,7 +7,7 @@
 ; 336L		%vreg15<def> = SAR32rCL %vreg15, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg15
 
 define void @foo(i32* nocapture %quadrant, i32* nocapture %ptr, i32 %bbSize, i32 %bbStart, i32 %shifts) nounwind ssp {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 entry:
   %j.03 = add i32 %bbSize, -1                     ; <i32> [#uses=2]
   %0 = icmp sgt i32 %j.03, -1                     ; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/pic.ll b/test/CodeGen/X86/pic.ll
index fc06309..7bb127e 100644
--- a/test/CodeGen/X86/pic.ll
+++ b/test/CodeGen/X86/pic.ll
@@ -11,7 +11,7 @@ entry:
     store i32 %tmp.s, i32* @dst
     ret void
     
-; LINUX:    test0:
+; LINUX-LABEL:    test0:
 ; LINUX:	calll	.L0$pb
 ; LINUX-NEXT: .L0$pb:
 ; LINUX-NEXT:	popl
@@ -33,7 +33,7 @@ entry:
     store i32 %tmp.s, i32* @dst2
     ret void
     
-; LINUX: test1:
+; LINUX-LABEL: test1:
 ; LINUX:	calll	.L1$pb
 ; LINUX-NEXT: .L1$pb:
 ; LINUX-NEXT:	popl
@@ -51,7 +51,7 @@ define void @test2() nounwind {
 entry:
     %ptr = call i8* @malloc(i32 40)
     ret void
-; LINUX: test2:
+; LINUX-LABEL: test2:
 ; LINUX: 	pushl	%ebx
 ; LINUX-NEXT: 	subl	$8, %esp
 ; LINUX-NEXT: 	calll	.L2$pb
@@ -74,7 +74,7 @@ entry:
     %tmp1 = load void(...)** @pfoo
     call void(...)* %tmp1()
     ret void
-; LINUX: test3:
+; LINUX-LABEL: test3:
 ; LINUX: 	calll	.L3$pb
 ; LINUX-NEXT: .L3$pb:
 ; LINUX: 	popl
@@ -90,7 +90,7 @@ define void @test4() nounwind {
 entry:
     call void(...)* @foo()
     ret void
-; LINUX: test4:
+; LINUX-LABEL: test4:
 ; LINUX: calll	.L4$pb
 ; LINUX: popl	%ebx
 ; LINUX: addl	$_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L4$pb), %ebx
@@ -111,7 +111,7 @@ entry:
     store i32 %tmp.s, i32* @dst6
     ret void
     
-; LINUX: test5:
+; LINUX-LABEL: test5:
 ; LINUX: 	calll	.L5$pb
 ; LINUX-NEXT: .L5$pb:
 ; LINUX-NEXT: 	popl	%eax
@@ -133,7 +133,7 @@ entry:
 
 ; LINUX: .LCPI6_0:
 
-; LINUX: test6:
+; LINUX-LABEL: test6:
 ; LINUX:    calll .L6$pb
 ; LINUX: .L6$pb:
 ; LINUX:    addl	$_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L6$pb), 
@@ -185,7 +185,7 @@ bb12:
     tail call void(...)* @foo6()
     ret void
     
-; LINUX: test7:
+; LINUX-LABEL: test7:
 ; LINUX:   calll	.L7$pb
 ; LINUX: .L7$pb:
 ; LINUX:   addl	$_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L7$pb),
diff --git a/test/CodeGen/X86/pmovext.ll b/test/CodeGen/X86/pmovext.ll
index 16e9c28..b85b4c3 100644
--- a/test/CodeGen/X86/pmovext.ll
+++ b/test/CodeGen/X86/pmovext.ll
@@ -2,7 +2,7 @@
 
 ; rdar://11897677
 
-;CHECK: intrin_pmov
+;CHECK-LABEL: intrin_pmov:
 ;CHECK: pmovzxbw  (%{{.*}}), %xmm0
 ;CHECK-NEXT: movdqu
 ;CHECK-NEXT: ret
diff --git a/test/CodeGen/X86/pmovsx-inreg.ll b/test/CodeGen/X86/pmovsx-inreg.ll
index d8c27f2..d30d7d0 100644
--- a/test/CodeGen/X86/pmovsx-inreg.ll
+++ b/test/CodeGen/X86/pmovsx-inreg.ll
@@ -12,13 +12,13 @@ define void @test1(<2 x i8>* %in, <2 x i64>* %out) nounwind {
   store <2 x i64> %sext, <2 x i64>* %out, align 8
   ret void
 
-; SSE41: test1:
+; SSE41-LABEL: test1:
 ; SSE41: pmovsxbq
 
-; AVX1: test1:
+; AVX1-LABEL: test1:
 ; AVX1: vpmovsxbq
 
-; AVX2: test1:
+; AVX2-LABEL: test1:
 ; AVX2: vpmovsxbq
 }
 
@@ -29,7 +29,7 @@ define void @test2(<4 x i8>* %in, <4 x i64>* %out) nounwind {
   store <4 x i64> %sext, <4 x i64>* %out, align 8
   ret void
 
-; AVX2: test2:
+; AVX2-LABEL: test2:
 ; AVX2: vpmovsxbq
 }
 
@@ -40,13 +40,13 @@ define void @test3(<4 x i8>* %in, <4 x i32>* %out) nounwind {
   store <4 x i32> %sext, <4 x i32>* %out, align 8
   ret void
 
-; SSE41: test3:
+; SSE41-LABEL: test3:
 ; SSE41: pmovsxbd
 
-; AVX1: test3:
+; AVX1-LABEL: test3:
 ; AVX1: vpmovsxbd
 
-; AVX2: test3:
+; AVX2-LABEL: test3:
 ; AVX2: vpmovsxbd
 }
 
@@ -57,7 +57,7 @@ define void @test4(<8 x i8>* %in, <8 x i32>* %out) nounwind {
   store <8 x i32> %sext, <8 x i32>* %out, align 8
   ret void
 
-; AVX2: test4:
+; AVX2-LABEL: test4:
 ; AVX2: vpmovsxbd
 }
 
@@ -68,13 +68,13 @@ define void @test5(<8 x i8>* %in, <8 x i16>* %out) nounwind {
   store <8 x i16> %sext, <8 x i16>* %out, align 8
   ret void
 
-; SSE41: test5:
+; SSE41-LABEL: test5:
 ; SSE41: pmovsxbw
 
-; AVX1: test5:
+; AVX1-LABEL: test5:
 ; AVX1: vpmovsxbw
 
-; AVX2: test5:
+; AVX2-LABEL: test5:
 ; AVX2: vpmovsxbw
 }
 
@@ -85,7 +85,7 @@ define void @test6(<16 x i8>* %in, <16 x i16>* %out) nounwind {
   store <16 x i16> %sext, <16 x i16>* %out, align 8
   ret void
 
-; AVX2: test6:
+; AVX2-LABEL: test6:
 ; FIXME: v16i8 -> v16i16 is scalarized.
 ; AVX2-NOT: pmovsx
 }
@@ -98,13 +98,13 @@ define void @test7(<2 x i16>* %in, <2 x i64>* %out) nounwind {
   ret void
 
 
-; SSE41: test7:
+; SSE41-LABEL: test7:
 ; SSE41: pmovsxwq
 
-; AVX1: test7:
+; AVX1-LABEL: test7:
 ; AVX1: vpmovsxwq
 
-; AVX2: test7:
+; AVX2-LABEL: test7:
 ; AVX2: vpmovsxwq
 }
 
@@ -115,7 +115,7 @@ define void @test8(<4 x i16>* %in, <4 x i64>* %out) nounwind {
   store <4 x i64> %sext, <4 x i64>* %out, align 8
   ret void
 
-; AVX2: test8:
+; AVX2-LABEL: test8:
 ; AVX2: vpmovsxwq
 }
 
@@ -126,13 +126,13 @@ define void @test9(<4 x i16>* %in, <4 x i32>* %out) nounwind {
   store <4 x i32> %sext, <4 x i32>* %out, align 8
   ret void
 
-; SSE41: test9:
+; SSE41-LABEL: test9:
 ; SSE41: pmovsxwd
 
-; AVX1: test9:
+; AVX1-LABEL: test9:
 ; AVX1: vpmovsxwd
 
-; AVX2: test9:
+; AVX2-LABEL: test9:
 ; AVX2: vpmovsxwd
 }
 
@@ -143,7 +143,7 @@ define void @test10(<8 x i16>* %in, <8 x i32>* %out) nounwind {
   store <8 x i32> %sext, <8 x i32>* %out, align 8
   ret void
 
-; AVX2: test10:
+; AVX2-LABEL: test10:
 ; AVX2: vpmovsxwd
 }
 
@@ -154,13 +154,13 @@ define void @test11(<2 x i32>* %in, <2 x i64>* %out) nounwind {
   store <2 x i64> %sext, <2 x i64>* %out, align 8
   ret void
 
-; SSE41: test11:
+; SSE41-LABEL: test11:
 ; SSE41: pmovsxdq
 
-; AVX1: test11:
+; AVX1-LABEL: test11:
 ; AVX1: vpmovsxdq
 
-; AVX2: test11:
+; AVX2-LABEL: test11:
 ; AVX2: vpmovsxdq
 }
 
@@ -171,6 +171,6 @@ define void @test12(<4 x i32>* %in, <4 x i64>* %out) nounwind {
   store <4 x i64> %sext, <4 x i64>* %out, align 8
   ret void
 
-; AVX2: test12:
+; AVX2-LABEL: test12:
 ; AVX2: vpmovsxdq
 }
diff --git a/test/CodeGen/X86/pmulld.ll b/test/CodeGen/X86/pmulld.ll
index be527ae..4103eab 100644
--- a/test/CodeGen/X86/pmulld.ll
+++ b/test/CodeGen/X86/pmulld.ll
@@ -2,10 +2,10 @@
 ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse41 -asm-verbose=0 | FileCheck %s -check-prefix=WIN64
 
 define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NEXT: pmulld
 
-; WIN64: test1:
+; WIN64-LABEL: test1:
 ; WIN64-NEXT: movdqa  (%rcx), %xmm0
 ; WIN64-NEXT: pmulld  (%rdx), %xmm0
   %C = mul <4 x i32> %A, %B
@@ -13,10 +13,10 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
 }
 
 define <4 x i32> @test1a(<4 x i32> %A, <4 x i32> *%Bp) nounwind {
-; CHECK: test1a:
+; CHECK-LABEL: test1a:
 ; CHECK-NEXT: pmulld
 
-; WIN64: test1a:
+; WIN64-LABEL: test1a:
 ; WIN64-NEXT: movdqa  (%rcx), %xmm0
 ; WIN64-NEXT: pmulld  (%rdx), %xmm0
 
diff --git a/test/CodeGen/X86/popcnt.ll b/test/CodeGen/X86/popcnt.ll
index 430214c..e9350de 100644
--- a/test/CodeGen/X86/popcnt.ll
+++ b/test/CodeGen/X86/popcnt.ll
@@ -3,7 +3,7 @@
 define i8 @cnt8(i8 %x) nounwind readnone {
   %cnt = tail call i8 @llvm.ctpop.i8(i8 %x)
   ret i8 %cnt
-; CHECK: cnt8:
+; CHECK-LABEL: cnt8:
 ; CHECK: popcntw
 ; CHECK: ret
 }
@@ -11,7 +11,7 @@ define i8 @cnt8(i8 %x) nounwind readnone {
 define i16 @cnt16(i16 %x) nounwind readnone {
   %cnt = tail call i16 @llvm.ctpop.i16(i16 %x)
   ret i16 %cnt
-; CHECK: cnt16:
+; CHECK-LABEL: cnt16:
 ; CHECK: popcntw
 ; CHECK: ret
 }
@@ -19,7 +19,7 @@ define i16 @cnt16(i16 %x) nounwind readnone {
 define i32 @cnt32(i32 %x) nounwind readnone {
   %cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
   ret i32 %cnt
-; CHECK: cnt32:
+; CHECK-LABEL: cnt32:
 ; CHECK: popcntl
 ; CHECK: ret
 }
@@ -27,7 +27,7 @@ define i32 @cnt32(i32 %x) nounwind readnone {
 define i64 @cnt64(i64 %x) nounwind readnone {
   %cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
   ret i64 %cnt
-; CHECK: cnt64:
+; CHECK-LABEL: cnt64:
 ; CHECK: popcntq
 ; CHECK: ret
 }
diff --git a/test/CodeGen/X86/postra-licm.ll b/test/CodeGen/X86/postra-licm.ll
index 01d6cbe..946b836 100644
--- a/test/CodeGen/X86/postra-licm.ll
+++ b/test/CodeGen/X86/postra-licm.ll
@@ -16,7 +16,7 @@
 @.str24 = external constant [4 x i8], align 1     ; <[4 x i8]*> [#uses=1]
 
 define i32 @t1(i32 %c, i8** nocapture %v) nounwind ssp {
-; X86-32: t1:
+; X86-32-LABEL: t1:
 entry:
   br i1 undef, label %bb, label %bb3
 
@@ -146,7 +146,7 @@ declare i32 @strcmp(i8* nocapture, i8* nocapture) nounwind readonly
 @map_4_to_16 = external constant [16 x i16], align 32 ; <[16 x i16]*> [#uses=2]
 
 define void @t2(i8* nocapture %bufp, i8* nocapture %data, i32 %dsize) nounwind ssp {
-; X86-64: t2:
+; X86-64-LABEL: t2:
 entry:
   br i1 undef, label %return, label %bb.nph
 
diff --git a/test/CodeGen/X86/pr12360.ll b/test/CodeGen/X86/pr12360.ll
index f29e50e..8b30596 100644
--- a/test/CodeGen/X86/pr12360.ll
+++ b/test/CodeGen/X86/pr12360.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
 
 define zeroext i1 @f1(i8* %x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: movb	(%rdi), %al
 ; CHECK-NEXT: ret
 
@@ -12,7 +12,7 @@ entry:
 }
 
 define zeroext i1 @f2(i8* %x) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: movb	(%rdi), %al
 ; CHECK-NEXT: ret
 
@@ -27,7 +27,7 @@ entry:
 
 ; check that we don't build a "trunc" from i1 to i1, which would assert.
 define zeroext i1 @f3(i1 %x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
 
 entry:
   %tobool = icmp ne i1 %x, 0
@@ -36,7 +36,7 @@ entry:
 
 ; check that we don't build a trunc when other bits are needed
 define zeroext i1 @f4(i32 %x) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: and
 
 entry:
diff --git a/test/CodeGen/X86/pr13209.ll b/test/CodeGen/X86/pr13209.ll
index 1c93163..8e5eca2 100644
--- a/test/CodeGen/X86/pr13209.ll
+++ b/test/CodeGen/X86/pr13209.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s
 
-; CHECK: pr13209:
+; CHECK-LABEL: pr13209:
 ; CHECK-NOT: mov
 ; CHECK: .size pr13209
 
diff --git a/test/CodeGen/X86/pr16031.ll b/test/CodeGen/X86/pr16031.ll
index 4721173..ab0b5ef 100644
--- a/test/CodeGen/X86/pr16031.ll
+++ b/test/CodeGen/X86/pr16031.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=corei7-avx | FileCheck %s
 
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK: pushl %esi
 ; CHECK-NEXT: movl  $-12, %eax
 ; CHECK-NEXT: movl  $-1, %edx
diff --git a/test/CodeGen/X86/pr16360.ll b/test/CodeGen/X86/pr16360.ll
new file mode 100644
index 0000000..1f73a4d
--- /dev/null
+++ b/test/CodeGen/X86/pr16360.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mcpu=pentium4 -mtriple=i686-pc-linux | FileCheck %s
+
+define i64 @foo(i32 %sum) {
+entry:
+  %conv = sext i32 %sum to i64
+  %shr = lshr i64 %conv, 2
+  %or = or i64 4611686018360279040, %shr
+  ret i64 %or
+}
+
+; CHECK: foo
+; CHECK: shrl $2
+; CHECK: orl $-67108864
+; CHECK-NOT: movl $-1
+; CHECK: movl $1073741823
+; CHECK: ret
diff --git a/test/CodeGen/X86/pr2182.ll b/test/CodeGen/X86/pr2182.ll
index 02a3605..94429b2 100644
--- a/test/CodeGen/X86/pr2182.ll
+++ b/test/CodeGen/X86/pr2182.ll
@@ -7,7 +7,7 @@ target triple = "i386-apple-darwin8"
 @x = weak global i32 0          ; <i32*> [#uses=8]
 
 define void @loop_2() nounwind  {
-; CHECK: loop_2:
+; CHECK-LABEL: loop_2:
 ; CHECK-NOT: ret
 ; CHECK: addl $3, (%{{.*}})
 ; CHECK-NEXT: addl $3, (%{{.*}})
diff --git a/test/CodeGen/X86/pr3216.ll b/test/CodeGen/X86/pr3216.ll
index 63676d9..a4a4821 100644
--- a/test/CodeGen/X86/pr3216.ll
+++ b/test/CodeGen/X86/pr3216.ll
@@ -3,7 +3,7 @@
 @foo = global i8 127
 
 define i32 @main() nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK-NOT: ret
 ; CHECK: sar{{.}} $5
 ; CHECK: ret
diff --git a/test/CodeGen/X86/pr3457.ll b/test/CodeGen/X86/pr3457.ll
index f7af927..7264bcd 100644
--- a/test/CodeGen/X86/pr3457.ll
+++ b/test/CodeGen/X86/pr3457.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin | not grep fstpt
+; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=corei7 | not grep fstpt
 ; PR3457
 ; rdar://6548010
 
diff --git a/test/CodeGen/X86/private.ll b/test/CodeGen/X86/private.ll
index 484afc9..c02d193 100644
--- a/test/CodeGen/X86/private.ll
+++ b/test/CodeGen/X86/private.ll
@@ -1,18 +1,22 @@
 ; Test to make sure that the 'private' is used correctly.
 ;
-; RUN: llc < %s -mtriple=x86_64-pc-linux | grep .Lfoo:
-; RUN: llc < %s -mtriple=x86_64-pc-linux | grep call.*\.Lfoo
-; RUN: llc < %s -mtriple=x86_64-pc-linux | grep .Lbaz:
-; RUN: llc < %s -mtriple=x86_64-pc-linux | grep movl.*\.Lbaz
+; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s
 
 define private void @foo() {
         ret void
-}
 
-@baz = private global i32 4
+; CHECK: .Lfoo:
+}
 
 define i32 @bar() {
         call void @foo()
 	%1 = load i32* @baz, align 4
         ret i32 %1
+
+; CHECK-LABEL: bar:
+; CHECK: callq .Lfoo
+; CHECK: movl	.Lbaz(%rip)
 }
+
+@baz = private global i32 4
+; CHECK: .Lbaz:
diff --git a/test/CodeGen/X86/promote-i16.ll b/test/CodeGen/X86/promote-i16.ll
index 3c91d74..963bc1c 100644
--- a/test/CodeGen/X86/promote-i16.ll
+++ b/test/CodeGen/X86/promote-i16.ll
@@ -2,7 +2,7 @@
 
 define signext i16 @foo(i16 signext %x) nounwind {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NOT: movzwl
 ; CHECK: movswl 4(%esp), %eax
 ; CHECK: xorl $21998, %eax
@@ -12,7 +12,7 @@ entry:
 
 define signext i16 @bar(i16 signext %x) nounwind {
 entry:
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK-NOT: movzwl
 ; CHECK: movswl 4(%esp), %eax
 ; CHECK: xorl $-10770, %eax
diff --git a/test/CodeGen/X86/rd-mod-wr-eflags.ll b/test/CodeGen/X86/rd-mod-wr-eflags.ll
index 0bf601b..5089bd7 100644
--- a/test/CodeGen/X86/rd-mod-wr-eflags.ll
+++ b/test/CodeGen/X86/rd-mod-wr-eflags.ll
@@ -179,7 +179,7 @@ return:
 
 define void @test3() nounwind ssp {
 entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: decq 16(%rax)
   %0 = load i64** @foo, align 8
   %arrayidx = getelementptr inbounds i64* %0, i64 2
diff --git a/test/CodeGen/X86/rdrand.ll b/test/CodeGen/X86/rdrand.ll
index 98f4077..1b16a2d 100644
--- a/test/CodeGen/X86/rdrand.ll
+++ b/test/CodeGen/X86/rdrand.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mcpu=core-avx-i -mattr=+rdrand | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i -mattr=+rdrand | FileCheck %s
 declare {i16, i32} @llvm.x86.rdrand.16()
 declare {i32, i32} @llvm.x86.rdrand.32()
 declare {i64, i32} @llvm.x86.rdrand.64()
@@ -9,7 +9,7 @@ define i32 @_rdrand16_step(i16* %random_val) {
   store i16 %randval, i16* %random_val
   %isvalid = extractvalue {i16, i32} %call, 1
   ret i32 %isvalid
-; CHECK: _rdrand16_step:
+; CHECK-LABEL: _rdrand16_step:
 ; CHECK: rdrandw	%ax
 ; CHECK: movw	%ax, (%r[[A0:di|cx]])
 ; CHECK: movzwl	%ax, %ecx
@@ -24,7 +24,7 @@ define i32 @_rdrand32_step(i32* %random_val) {
   store i32 %randval, i32* %random_val
   %isvalid = extractvalue {i32, i32} %call, 1
   ret i32 %isvalid
-; CHECK: _rdrand32_step:
+; CHECK-LABEL: _rdrand32_step:
 ; CHECK: rdrandl	%e[[T0:[a-z]+]]
 ; CHECK: movl	%e[[T0]], (%r[[A0]])
 ; CHECK: movl	$1, %eax
@@ -38,7 +38,7 @@ define i32 @_rdrand64_step(i64* %random_val) {
   store i64 %randval, i64* %random_val
   %isvalid = extractvalue {i64, i32} %call, 1
   ret i32 %isvalid
-; CHECK: _rdrand64_step:
+; CHECK-LABEL: _rdrand64_step:
 ; CHECK: rdrandq	%r[[T1:[a-z]+]]
 ; CHECK: movq	%r[[T1]], (%r[[A0]])
 ; CHECK: movl	$1, %eax
@@ -54,7 +54,7 @@ define i32 @CSE() nounwind {
  %v2 = extractvalue { i32, i32 } %rand2, 0
  %add = add i32 %v2, %v1
  ret i32 %add
-; CHECK: CSE:
+; CHECK-LABEL: CSE:
 ; CHECK: rdrandl
 ; CHECK: rdrandl
 }
@@ -78,7 +78,7 @@ while.body:                                       ; preds = %entry, %while.body
 
 while.end:                                        ; preds = %while.body, %entry
   ret void
-; CHECK: loop:
+; CHECK-LABEL: loop:
 ; CHECK-NOT: rdrandl
 ; CHECK: This Inner Loop Header: Depth=1
 ; CHECK: rdrandl
diff --git a/test/CodeGen/X86/rdseed.ll b/test/CodeGen/X86/rdseed.ll
index 35de7eb..edc5069 100644
--- a/test/CodeGen/X86/rdseed.ll
+++ b/test/CodeGen/X86/rdseed.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 -mcpu=core-avx-i -mattr=+rdseed | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i -mattr=+rdseed | FileCheck %s
 
 declare {i16, i32} @llvm.x86.rdseed.16()
 declare {i32, i32} @llvm.x86.rdseed.32()
@@ -10,7 +10,7 @@ define i32 @_rdseed16_step(i16* %random_val) {
   store i16 %randval, i16* %random_val
   %isvalid = extractvalue {i16, i32} %call, 1
   ret i32 %isvalid
-; CHECK: _rdseed16_step:
+; CHECK-LABEL: _rdseed16_step:
 ; CHECK: rdseedw	%ax
 ; CHECK: movw	%ax, (%r[[A0:di|cx]])
 ; CHECK: movzwl	%ax, %ecx
@@ -25,7 +25,7 @@ define i32 @_rdseed32_step(i32* %random_val) {
   store i32 %randval, i32* %random_val
   %isvalid = extractvalue {i32, i32} %call, 1
   ret i32 %isvalid
-; CHECK: _rdseed32_step:
+; CHECK-LABEL: _rdseed32_step:
 ; CHECK: rdseedl	%e[[T0:[a-z]+]]
 ; CHECK: movl	%e[[T0]], (%r[[A0]])
 ; CHECK: movl	$1, %eax
@@ -39,7 +39,7 @@ define i32 @_rdseed64_step(i64* %random_val) {
   store i64 %randval, i64* %random_val
   %isvalid = extractvalue {i64, i32} %call, 1
   ret i32 %isvalid
-; CHECK: _rdseed64_step:
+; CHECK-LABEL: _rdseed64_step:
 ; CHECK: rdseedq	%r[[T1:[a-z]+]]
 ; CHECK: movq	%r[[T1]], (%r[[A0]])
 ; CHECK: movl	$1, %eax
diff --git a/test/CodeGen/X86/red-zone.ll b/test/CodeGen/X86/red-zone.ll
index d99a7a4..cce71f5 100644
--- a/test/CodeGen/X86/red-zone.ll
+++ b/test/CodeGen/X86/red-zone.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s
 
 ; First without noredzone.
-; CHECK: f0:
+; CHECK-LABEL: f0:
 ; CHECK: -4(%rsp)
 ; CHECK: -4(%rsp)
 ; CHECK: ret
@@ -12,7 +12,7 @@ entry:
 }
 
 ; Then with noredzone.
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: subq $4, %rsp
 ; CHECK: (%rsp)
 ; CHECK: (%rsp)
diff --git a/test/CodeGen/X86/red-zone2.ll b/test/CodeGen/X86/red-zone2.ll
index 3e9c790..c7e855b 100644
--- a/test/CodeGen/X86/red-zone2.ll
+++ b/test/CodeGen/X86/red-zone2.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s
-; CHECK: f0:
+; CHECK-LABEL: f0:
 ; CHECK: subq
 ; CHECK: addq
 
diff --git a/test/CodeGen/X86/remat-mov-0.ll b/test/CodeGen/X86/remat-mov-0.ll
index f89cd33..9e8d8f6 100644
--- a/test/CodeGen/X86/remat-mov-0.ll
+++ b/test/CodeGen/X86/remat-mov-0.ll
@@ -5,7 +5,7 @@
 
 declare void @foo(i64 %p)
 
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: xorl %e[[A0:di|cx]], %e
 ; CHECK: xorl %e[[A0]], %e[[A0]]
 define void @bar() nounwind {
@@ -14,7 +14,7 @@ define void @bar() nounwind {
   ret void
 }
 
-; CHECK: bat:
+; CHECK-LABEL: bat:
 ; CHECK: movq $-1, %r[[A0]]
 ; CHECK: movq $-1, %r[[A0]]
 define void @bat() nounwind {
@@ -23,7 +23,7 @@ define void @bat() nounwind {
   ret void
 }
 
-; CHECK: bau:
+; CHECK-LABEL: bau:
 ; CHECK: movl $1, %e[[A0]]
 ; CHECK: movl $1, %e[[A0]]
 define void @bau() nounwind {
diff --git a/test/CodeGen/X86/remat-phys-dead.ll b/test/CodeGen/X86/remat-phys-dead.ll
new file mode 100644
index 0000000..4d7ee62
--- /dev/null
+++ b/test/CodeGen/X86/remat-phys-dead.ll
@@ -0,0 +1,23 @@
+; REQUIRES: asserts
+; RUN: llc -mtriple=x86_64-apple-darwin -debug -o /dev/null < %s 2>&1 | FileCheck %s
+
+; We need to make sure that rematerialization into a physical register marks the
+; super- or sub-register as dead after this rematerialization since only the
+; original register is actually used later. Largely irrelevant for a trivial
+; example like this, since EAX is never used again, but easy to test.
+
+define i8 @test_remat() {
+  ret i8 0
+; CHECK: REGISTER COALESCING
+; CHECK: Remat: %EAX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %AL<imp-def>
+}
+
+; On the other hand, if it's already the correct width, we really shouldn't be
+; marking the definition register as dead.
+
+define i32 @test_remat32() {
+  ret i32 0
+; CHECK: REGISTER COALESCING
+; CHECK: Remat: %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
+}
+
diff --git a/test/CodeGen/X86/ret-mmx.ll b/test/CodeGen/X86/ret-mmx.ll
index 778e472..091fd53 100644
--- a/test/CodeGen/X86/ret-mmx.ll
+++ b/test/CodeGen/X86/ret-mmx.ll
@@ -8,7 +8,7 @@ entry:
 	%call = call <1 x i64> @return_v1di()		; <<1 x i64>> [#uses=0]
 	store <1 x i64> %call, <1 x i64>* @g_v1di
         ret void
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: callq
 ; CHECK-NEXT: movq	_g_v1di
 ; CHECK-NEXT: movq	%rax,
@@ -18,21 +18,21 @@ declare <1 x i64> @return_v1di()
 
 define <1 x i64> @t2() nounwind {
 	ret <1 x i64> <i64 1>
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: movl	$1
 ; CHECK-NEXT: ret
 }
 
 define <2 x i32> @t3() nounwind {
 	ret <2 x i32> <i32 1, i32 0>
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: movl $1
 ; CHECK: movd {{.*}}, %xmm0
 }
 
 define double @t4() nounwind {
 	ret double bitcast (<2 x i32> <i32 1, i32 0> to double)
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: movl $1
 ; CHECK: movd {{.*}}, %xmm0
 }
diff --git a/test/CodeGen/X86/returned-trunc-tail-calls.ll b/test/CodeGen/X86/returned-trunc-tail-calls.ll
new file mode 100644
index 0000000..10bd3b6
--- /dev/null
+++ b/test/CodeGen/X86/returned-trunc-tail-calls.ll
@@ -0,0 +1,97 @@
+; RUN: llc < %s -mtriple=x86_64-pc-win32 | FileCheck %s
+
+declare i32 @ret32(i32 returned)
+declare i64 @ret64(i64 returned)
+
+define i64 @test1(i64 %val) {
+; CHECK-LABEL: test1:
+; CHECK-NOT: jmp
+; CHECK: callq
+  %in = trunc i64 %val to i32
+  tail call i32 @ret32(i32 returned %in)
+  ret i64 %val
+}
+
+define i32 @test2(i64 %val) {
+; CHECK-LABEL: test2:
+; CHECK: jmp
+; CHECK-NOT: callq
+  %in = trunc i64 %val to i32
+  tail call i64 @ret64(i64 returned %val)
+  ret i32 %in
+}
+
+define i32 @test3(i64 %in) {
+; CHECK-LABEL: test3:
+; CHECK: jmp
+; CHECK-NOT: callq
+  %small = trunc i64 %in to i32
+  tail call i32 @ret32(i32 returned %small)
+  ret i32 %small
+}
+
+declare {i32, i8} @take_i32_i8({i32, i8} returned)
+define { i8, i8 } @test_nocommon_value({i32, i32} %in) {
+; CHECK-LABEL: test_nocommon_value
+; CHECK: jmp
+
+  %first = extractvalue {i32, i32} %in, 0
+  %first.trunc = trunc i32 %first to i8
+
+  %second = extractvalue {i32, i32} %in, 1
+  %second.trunc = trunc i32 %second to i8
+
+  %tmp = insertvalue {i32, i8} undef, i32 %first, 0
+  %callval = insertvalue {i32, i8} %tmp, i8 %second.trunc, 1
+  tail call {i32, i8} @take_i32_i8({i32, i8} returned %callval)
+
+  %restmp = insertvalue {i8, i8} undef, i8 %first.trunc, 0
+  %res = insertvalue {i8, i8} %restmp, i8 %second.trunc, 1
+  ret {i8, i8} %res
+}
+
+declare {i32, {i32, i32}} @give_i32_i32_i32()
+define {{i32, i32}, i32} @test_structs_different_shape() {
+; CHECK-LABEL: test_structs_different_shape
+; CHECK: jmp
+  %val = tail call {i32, {i32, i32}} @give_i32_i32_i32()
+
+  %first = extractvalue {i32, {i32, i32}} %val, 0
+  %second = extractvalue {i32, {i32, i32}} %val, 1, 0
+  %third = extractvalue {i32, {i32, i32}} %val, 1, 1
+
+  %restmp = insertvalue {{i32, i32}, i32} undef, i32 %first, 0, 0
+  %reseventmper = insertvalue {{i32, i32}, i32} %restmp, i32 %second, 0, 1
+  %res = insertvalue {{i32, i32}, i32} %reseventmper, i32 %third, 1
+
+  ret {{i32, i32}, i32} %res
+}
+
+define i64 @test_undef_asymmetry() {
+; CHECK: test_undef_asymmetry
+; CHECK-NOT: jmp
+  tail call i64 @ret64(i64 returned undef)
+  ret i64 2
+}
+
+define {{}, {{}, i32, {}}, [1 x i32]} @evil_empty_aggregates() {
+; CHECK-LABEL: evil_empty_aggregates
+; CHECK: jmp
+  %agg = tail call {i32, {i32, i32}} @give_i32_i32_i32()
+
+  %first = extractvalue {i32, {i32, i32}} %agg, 0
+  %second = extractvalue {i32, {i32, i32}} %agg, 1, 0
+
+  %restmp = insertvalue {{}, {{}, i32, {}}, [1 x i32]} undef, i32 %first, 1, 1
+  %res = insertvalue {{}, {{}, i32, {}}, [1 x i32]} %restmp, i32 %second, 2, 0
+  ret {{}, {{}, i32, {}}, [1 x i32]} %res
+}
+
+define i32 @structure_is_unimportant() {
+; CHECK-LABEL: structure_is_unimportant
+; CHECK: jmp
+  %val = tail call {i32, {i32, i32}} @give_i32_i32_i32()
+
+  %res = extractvalue {i32, {i32, i32}} %val, 0
+  ret i32 %res
+}
diff --git a/test/CodeGen/X86/reverse_branches.ll b/test/CodeGen/X86/reverse_branches.ll
index 9772125..ee6333e 100644
--- a/test/CodeGen/X86/reverse_branches.ll
+++ b/test/CodeGen/X86/reverse_branches.ll
@@ -7,7 +7,7 @@
 ; Make sure at end of do.cond.i, we jump to do.body.i first to have a tighter
 ; inner loop.
 define i32 @test_branches_order() uwtable ssp {
-; CHECK: test_branches_order:
+; CHECK-LABEL: test_branches_order:
 ; CHECK: [[L0:LBB0_[0-9]+]]: ## %do.body.i
 ; CHECK: je
 ; CHECK: %do.cond.i
diff --git a/test/CodeGen/X86/rodata-relocs.ll b/test/CodeGen/X86/rodata-relocs.ll
index 9291200..9228ea1 100644
--- a/test/CodeGen/X86/rodata-relocs.ll
+++ b/test/CodeGen/X86/rodata-relocs.ll
@@ -1,13 +1,9 @@
-; RUN: llc < %s -relocation-model=static | grep rodata | count 3
-; RUN: llc < %s -relocation-model=static | grep -F "rodata.cst" | count 2
-; RUN: llc < %s -relocation-model=pic | grep rodata | count 2
-; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel.ro" | count 2
-; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel.ro.local" | count 1
-; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel" | count 4
-; RUN: llc < %s -relocation-model=pic | grep -F ".data.rel.local" | count 1
+; RUN: llc < %s -relocation-model=static | FileCheck %s -check-prefix=STATIC
+; RUN: llc < %s -relocation-model=pic | FileCheck %s -check-prefix=PIC
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-unknown-linux-gnu"
+
 @a = internal unnamed_addr constant [2 x i32] [i32 1, i32 2]
 @a1 = unnamed_addr constant [2 x i32] [i32 1, i32 2]
 @e = internal  unnamed_addr constant [2 x [2 x i32]] [[2 x i32] [i32 1, i32 2], [2 x i32] [i32 3, i32 4]], align 16
@@ -21,3 +17,30 @@ target triple = "x86_64-unknown-linux-gnu"
 @p3 = internal global i8* bitcast([2 x i32]* @a to i8*)
 @t3 = internal global i8* bitcast([2 x [2 x i32]]* @e to i8*)
 
+; STATIC: .section .rodata.cst8,"aM",@progbits,8
+; STATIC: a:
+; STATIC: a1:
+; STATIC: .section .rodata.cst16,"aM",@progbits,16
+; STATIC: e:
+; STATIC: e1:
+; STATIC: .section .rodata,"a",@progbits
+; STATIC: p:
+
+; PIC: .section .rodata.cst8,"aM",@progbits,8
+; PIC: a:
+; PIC: a1:
+; PIC: .section .rodata.cst16,"aM",@progbits,16
+; PIC: e:
+; PIC: e1:
+; PIC: .section .data.rel.ro.local,"aw",@progbits
+; PIC: p:
+; PIC: t:
+; PIC: .section .data.rel.ro,"aw",@progbits
+; PIC: p1:
+; PIC: t1:
+; PIC: .section .data.rel,"aw",@progbits
+; PIC: p2:
+; PIC: t2:
+; PIC: .section .data.rel.local,"aw",@progbits
+; PIC: p3:
+; PIC: t3:
diff --git a/test/CodeGen/X86/rot16.ll b/test/CodeGen/X86/rot16.ll
index de23dcb..0293f4e 100644
--- a/test/CodeGen/X86/rot16.ll
+++ b/test/CodeGen/X86/rot16.ll
@@ -2,7 +2,7 @@
 
 define i16 @foo(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: rolw %cl
 	%0 = shl i16 %x, %z
 	%1 = sub i16 16, %z
@@ -13,7 +13,7 @@ entry:
 
 define i16 @bar(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: shldw %cl
 	%0 = shl i16 %y, %z
 	%1 = sub i16 16, %z
@@ -24,7 +24,7 @@ entry:
 
 define i16 @un(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: un:
+; CHECK-LABEL: un:
 ; CHECK: rorw %cl
 	%0 = lshr i16 %x, %z
 	%1 = sub i16 16, %z
@@ -35,7 +35,7 @@ entry:
 
 define i16 @bu(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: bu:
+; CHECK-LABEL: bu:
 ; CHECK: shrdw
 	%0 = lshr i16 %y, %z
 	%1 = sub i16 16, %z
@@ -46,7 +46,7 @@ entry:
 
 define i16 @xfoo(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: xfoo:
+; CHECK-LABEL: xfoo:
 ; CHECK: rolw $5
 	%0 = lshr i16 %x, 11
 	%1 = shl i16 %x, 5
@@ -56,7 +56,7 @@ entry:
 
 define i16 @xbar(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: xbar:
+; CHECK-LABEL: xbar:
 ; CHECK: shldw $5
 	%0 = shl i16 %y, 5
 	%1 = lshr i16 %x, 11
@@ -66,7 +66,7 @@ entry:
 
 define i16 @xun(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: xun:
+; CHECK-LABEL: xun:
 ; CHECK: rolw $11
 	%0 = lshr i16 %x, 5
 	%1 = shl i16 %x, 11
@@ -76,7 +76,7 @@ entry:
 
 define i16 @xbu(i16 %x, i16 %y, i16 %z) nounwind readnone {
 entry:
-; CHECK: xbu:
+; CHECK-LABEL: xbu:
 ; CHECK: shldw $11
 	%0 = lshr i16 %y, 5
 	%1 = shl i16 %x, 11
diff --git a/test/CodeGen/X86/rot32.ll b/test/CodeGen/X86/rot32.ll
index e95a734..7bdd606 100644
--- a/test/CodeGen/X86/rot32.ll
+++ b/test/CodeGen/X86/rot32.ll
@@ -3,7 +3,7 @@
 
 define i32 @foo(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: roll %cl
 	%0 = shl i32 %x, %z
 	%1 = sub i32 32, %z
@@ -14,7 +14,7 @@ entry:
 
 define i32 @bar(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: shldl %cl
 	%0 = shl i32 %y, %z
 	%1 = sub i32 32, %z
@@ -25,7 +25,7 @@ entry:
 
 define i32 @un(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: un:
+; CHECK-LABEL: un:
 ; CHECK: rorl %cl
 	%0 = lshr i32 %x, %z
 	%1 = sub i32 32, %z
@@ -36,7 +36,7 @@ entry:
 
 define i32 @bu(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: bu:
+; CHECK-LABEL: bu:
 ; CHECK: shrdl %cl
 	%0 = lshr i32 %y, %z
 	%1 = sub i32 32, %z
@@ -47,9 +47,9 @@ entry:
 
 define i32 @xfoo(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: xfoo:
+; CHECK-LABEL: xfoo:
 ; CHECK: roll $7
-; BMI2: xfoo:
+; BMI2-LABEL: xfoo:
 ; BMI2: rorxl $25
 	%0 = lshr i32 %x, 25
 	%1 = shl i32 %x, 7
@@ -59,7 +59,7 @@ entry:
 
 define i32 @xfoop(i32* %p) nounwind readnone {
 entry:
-; BMI2: xfoop:
+; BMI2-LABEL: xfoop:
 ; BMI2: rorxl $25, ({{.+}}), %{{.+}}
 	%x = load i32* %p
 	%a = lshr i32 %x, 25
@@ -70,7 +70,7 @@ entry:
 
 define i32 @xbar(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: xbar:
+; CHECK-LABEL: xbar:
 ; CHECK: shldl $7
 	%0 = shl i32 %y, 7
 	%1 = lshr i32 %x, 25
@@ -80,9 +80,9 @@ entry:
 
 define i32 @xun(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: xun:
+; CHECK-LABEL: xun:
 ; CHECK: roll $25
-; BMI2: xun:
+; BMI2-LABEL: xun:
 ; BMI2: rorxl $7
 	%0 = lshr i32 %x, 7
 	%1 = shl i32 %x, 25
@@ -92,7 +92,7 @@ entry:
 
 define i32 @xunp(i32* %p) nounwind readnone {
 entry:
-; BMI2: xunp:
+; BMI2-LABEL: xunp:
 ; BMI2: rorxl $7, ({{.+}}), %{{.+}}
 	%x = load i32* %p
 	%a = lshr i32 %x, 7
@@ -103,7 +103,7 @@ entry:
 
 define i32 @xbu(i32 %x, i32 %y, i32 %z) nounwind readnone {
 entry:
-; CHECK: xbu:
+; CHECK-LABEL: xbu:
 ; CHECK: shldl
 	%0 = lshr i32 %y, 7
 	%1 = shl i32 %x, 25
diff --git a/test/CodeGen/X86/rot64.ll b/test/CodeGen/X86/rot64.ll
index 7fa982d..e19a35d 100644
--- a/test/CodeGen/X86/rot64.ll
+++ b/test/CodeGen/X86/rot64.ll
@@ -43,7 +43,7 @@ entry:
 
 define i64 @xfoo(i64 %x, i64 %y, i64 %z) nounwind readnone {
 entry:
-; BMI2: xfoo:
+; BMI2-LABEL: xfoo:
 ; BMI2: rorxq $57
 	%0 = lshr i64 %x, 57
 	%1 = shl i64 %x, 7
@@ -53,7 +53,7 @@ entry:
 
 define i64 @xfoop(i64* %p) nounwind readnone {
 entry:
-; BMI2: xfoop:
+; BMI2-LABEL: xfoop:
 ; BMI2: rorxq $57, ({{.+}}), %{{.+}}
 	%x = load i64* %p
 	%a = lshr i64 %x, 57
@@ -72,7 +72,7 @@ entry:
 
 define i64 @xun(i64 %x, i64 %y, i64 %z) nounwind readnone {
 entry:
-; BMI2: xun:
+; BMI2-LABEL: xun:
 ; BMI2: rorxq $7
 	%0 = lshr i64 %x, 7
 	%1 = shl i64 %x, 57
@@ -82,7 +82,7 @@ entry:
 
 define i64 @xunp(i64* %p) nounwind readnone {
 entry:
-; BMI2: xunp:
+; BMI2-LABEL: xunp:
 ; BMI2: rorxq $7, ({{.+}}), %{{.+}}
 	%x = load i64* %p
 	%a = lshr i64 %x, 7
diff --git a/test/CodeGen/X86/rounding-ops.ll b/test/CodeGen/X86/rounding-ops.ll
index 51fcf64..ace31cf 100644
--- a/test/CodeGen/X86/rounding-ops.ll
+++ b/test/CodeGen/X86/rounding-ops.ll
@@ -5,10 +5,10 @@ define float @test1(float %x) nounwind  {
   %call = tail call float @floorf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-SSE: test1:
+; CHECK-SSE-LABEL: test1:
 ; CHECK-SSE: roundss $1
 
-; CHECK-AVX: test1:
+; CHECK-AVX-LABEL: test1:
 ; CHECK-AVX: vroundss $1
 }
 
@@ -18,10 +18,10 @@ define double @test2(double %x) nounwind  {
   %call = tail call double @floor(double %x) nounwind readnone
   ret double %call
 
-; CHECK-SSE: test2:
+; CHECK-SSE-LABEL: test2:
 ; CHECK-SSE: roundsd $1
 
-; CHECK-AVX: test2:
+; CHECK-AVX-LABEL: test2:
 ; CHECK-AVX: vroundsd $1
 }
 
@@ -31,10 +31,10 @@ define float @test3(float %x) nounwind  {
   %call = tail call float @nearbyintf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-SSE: test3:
+; CHECK-SSE-LABEL: test3:
 ; CHECK-SSE: roundss $12
 
-; CHECK-AVX: test3:
+; CHECK-AVX-LABEL: test3:
 ; CHECK-AVX: vroundss $12
 }
 
@@ -44,10 +44,10 @@ define double @test4(double %x) nounwind  {
   %call = tail call double @nearbyint(double %x) nounwind readnone
   ret double %call
 
-; CHECK-SSE: test4:
+; CHECK-SSE-LABEL: test4:
 ; CHECK-SSE: roundsd $12
 
-; CHECK-AVX: test4:
+; CHECK-AVX-LABEL: test4:
 ; CHECK-AVX: vroundsd $12
 }
 
@@ -57,10 +57,10 @@ define float @test5(float %x) nounwind  {
   %call = tail call float @ceilf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-SSE: test5:
+; CHECK-SSE-LABEL: test5:
 ; CHECK-SSE: roundss $2
 
-; CHECK-AVX: test5:
+; CHECK-AVX-LABEL: test5:
 ; CHECK-AVX: vroundss $2
 }
 
@@ -70,10 +70,10 @@ define double @test6(double %x) nounwind  {
   %call = tail call double @ceil(double %x) nounwind readnone
   ret double %call
 
-; CHECK-SSE: test6:
+; CHECK-SSE-LABEL: test6:
 ; CHECK-SSE: roundsd $2
 
-; CHECK-AVX: test6:
+; CHECK-AVX-LABEL: test6:
 ; CHECK-AVX: vroundsd $2
 }
 
@@ -83,10 +83,10 @@ define float @test7(float %x) nounwind  {
   %call = tail call float @rintf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-SSE: test7:
+; CHECK-SSE-LABEL: test7:
 ; CHECK-SSE: roundss $4
 
-; CHECK-AVX: test7:
+; CHECK-AVX-LABEL: test7:
 ; CHECK-AVX: vroundss $4
 }
 
@@ -96,10 +96,10 @@ define double @test8(double %x) nounwind  {
   %call = tail call double @rint(double %x) nounwind readnone
   ret double %call
 
-; CHECK-SSE: test8:
+; CHECK-SSE-LABEL: test8:
 ; CHECK-SSE: roundsd $4
 
-; CHECK-AVX: test8:
+; CHECK-AVX-LABEL: test8:
 ; CHECK-AVX: vroundsd $4
 }
 
@@ -109,10 +109,10 @@ define float @test9(float %x) nounwind  {
   %call = tail call float @truncf(float %x) nounwind readnone
   ret float %call
 
-; CHECK-SSE: test9:
+; CHECK-SSE-LABEL: test9:
 ; CHECK-SSE: roundss $3
 
-; CHECK-AVX: test9:
+; CHECK-AVX-LABEL: test9:
 ; CHECK-AVX: vroundss $3
 }
 
@@ -122,10 +122,10 @@ define double @test10(double %x) nounwind  {
   %call = tail call double @trunc(double %x) nounwind readnone
   ret double %call
 
-; CHECK-SSE: test10:
+; CHECK-SSE-LABEL: test10:
 ; CHECK-SSE: roundsd $3
 
-; CHECK-AVX: test10:
+; CHECK-AVX-LABEL: test10:
 ; CHECK-AVX: vroundsd $3
 }
 
diff --git a/test/CodeGen/X86/sandybridge-loads.ll b/test/CodeGen/X86/sandybridge-loads.ll
index 5a23cf1..b8c364e 100644
--- a/test/CodeGen/X86/sandybridge-loads.ll
+++ b/test/CodeGen/X86/sandybridge-loads.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -o - < %s | FileCheck %s
 
-;CHECK: wideloads
+;CHECK-LABEL: wideloads:
 ;CHECK: vmovaps
 ;CHECK: vinsertf128
 ;CHECK: vmovaps
diff --git a/test/CodeGen/X86/sdiv-exact.ll b/test/CodeGen/X86/sdiv-exact.ll
index 48bb883..4f8d3f0 100644
--- a/test/CodeGen/X86/sdiv-exact.ll
+++ b/test/CodeGen/X86/sdiv-exact.ll
@@ -3,7 +3,7 @@
 define i32 @test1(i32 %x) {
   %div = sdiv exact i32 %x, 25
   ret i32 %div
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: imull	$-1030792151, 4(%esp)
 ; CHECK-NEXT: ret
 }
@@ -11,7 +11,7 @@ define i32 @test1(i32 %x) {
 define i32 @test2(i32 %x) {
   %div = sdiv exact i32 %x, 24
   ret i32 %div
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: sarl	$3
 ; CHECK-NEXT: imull	$-1431655765
 ; CHECK-NEXT: ret
diff --git a/test/CodeGen/X86/segmented-stacks-dynamic.ll b/test/CodeGen/X86/segmented-stacks-dynamic.ll
index d68b00b..c2aa617 100644
--- a/test/CodeGen/X86/segmented-stacks-dynamic.ll
+++ b/test/CodeGen/X86/segmented-stacks-dynamic.ll
@@ -20,7 +20,7 @@ false:
         %retvalue = call i32 @test_basic(i32 %newlen)
         ret i32 %retvalue
 
-; X32:      test_basic:
+; X32-LABEL:      test_basic:
 
 ; X32:      cmpl %gs:48, %esp
 ; X32-NEXT: ja      .LBB0_2
@@ -41,7 +41,7 @@ false:
 ; X32-NEXT: calll __morestack_allocate_stack_space
 ; X32-NEXT: addl $16, %esp
 
-; X64:      test_basic:
+; X64-LABEL:      test_basic:
 
 ; X64:      cmpq %fs:112, %rsp
 ; X64-NEXT: ja      .LBB0_2
diff --git a/test/CodeGen/X86/segmented-stacks.ll b/test/CodeGen/X86/segmented-stacks.ll
index 5407b87..08a98ef 100644
--- a/test/CodeGen/X86/segmented-stacks.ll
+++ b/test/CodeGen/X86/segmented-stacks.ll
@@ -32,7 +32,7 @@ define void @test_basic() {
         call void @dummy_use (i32* %mem, i32 10)
 	ret void
 
-; X32-Linux:       test_basic:
+; X32-Linux-LABEL:       test_basic:
 
 ; X32-Linux:       cmpl %gs:48, %esp
 ; X32-Linux-NEXT:  ja      .LBB0_2
@@ -42,7 +42,7 @@ define void @test_basic() {
 ; X32-Linux-NEXT:  calll __morestack
 ; X32-Linux-NEXT:  ret
 
-; X64-Linux:       test_basic:
+; X64-Linux-LABEL:       test_basic:
 
 ; X64-Linux:       cmpq %fs:112, %rsp
 ; X64-Linux-NEXT:  ja      .LBB0_2
@@ -52,7 +52,7 @@ define void @test_basic() {
 ; X64-Linux-NEXT:  callq __morestack
 ; X64-Linux-NEXT:  ret
 
-; X32-Darwin:      test_basic:
+; X32-Darwin-LABEL:      test_basic:
 
 ; X32-Darwin:      movl $432, %ecx
 ; X32-Darwin-NEXT: cmpl %gs:(%ecx), %esp
@@ -63,7 +63,7 @@ define void @test_basic() {
 ; X32-Darwin-NEXT: calll ___morestack
 ; X32-Darwin-NEXT: ret
 
-; X64-Darwin:      test_basic:
+; X64-Darwin-LABEL:      test_basic:
 
 ; X64-Darwin:      cmpq %gs:816, %rsp
 ; X64-Darwin-NEXT: ja      LBB0_2
@@ -73,7 +73,7 @@ define void @test_basic() {
 ; X64-Darwin-NEXT: callq ___morestack
 ; X64-Darwin-NEXT: ret
 
-; X32-MinGW:       test_basic:
+; X32-MinGW-LABEL:       test_basic:
 
 ; X32-MinGW:       cmpl %fs:20, %esp
 ; X32-MinGW-NEXT:  ja      LBB0_2
@@ -83,7 +83,7 @@ define void @test_basic() {
 ; X32-MinGW-NEXT:  calll ___morestack
 ; X32-MinGW-NEXT:  ret
 
-; X64-FreeBSD:       test_basic:
+; X64-FreeBSD-LABEL:       test_basic:
 
 ; X64-FreeBSD:       cmpq %fs:24, %rsp
 ; X64-FreeBSD-NEXT:  ja      .LBB0_2
@@ -224,7 +224,7 @@ define fastcc void @test_fastcc() {
         call void @dummy_use (i32* %mem, i32 10)
         ret void
 
-; X32-Linux:       test_fastcc:
+; X32-Linux-LABEL:       test_fastcc:
 
 ; X32-Linux:       cmpl %gs:48, %esp
 ; X32-Linux-NEXT:  ja      .LBB3_2
@@ -234,7 +234,7 @@ define fastcc void @test_fastcc() {
 ; X32-Linux-NEXT:  calll __morestack
 ; X32-Linux-NEXT:  ret
 
-; X64-Linux:       test_fastcc:
+; X64-Linux-LABEL:       test_fastcc:
 
 ; X64-Linux:       cmpq %fs:112, %rsp
 ; X64-Linux-NEXT:  ja      .LBB3_2
@@ -244,7 +244,7 @@ define fastcc void @test_fastcc() {
 ; X64-Linux-NEXT:  callq __morestack
 ; X64-Linux-NEXT:  ret
 
-; X32-Darwin:      test_fastcc:
+; X32-Darwin-LABEL:      test_fastcc:
 
 ; X32-Darwin:      movl $432, %eax
 ; X32-Darwin-NEXT: cmpl %gs:(%eax), %esp
@@ -255,7 +255,7 @@ define fastcc void @test_fastcc() {
 ; X32-Darwin-NEXT: calll ___morestack
 ; X32-Darwin-NEXT: ret
 
-; X64-Darwin:      test_fastcc:
+; X64-Darwin-LABEL:      test_fastcc:
 
 ; X64-Darwin:      cmpq %gs:816, %rsp
 ; X64-Darwin-NEXT: ja      LBB3_2
@@ -265,7 +265,7 @@ define fastcc void @test_fastcc() {
 ; X64-Darwin-NEXT: callq ___morestack
 ; X64-Darwin-NEXT: ret
 
-; X32-MinGW:       test_fastcc:
+; X32-MinGW-LABEL:       test_fastcc:
 
 ; X32-MinGW:       cmpl %fs:20, %esp
 ; X32-MinGW-NEXT:  ja      LBB3_2
@@ -275,7 +275,7 @@ define fastcc void @test_fastcc() {
 ; X32-MinGW-NEXT:  calll ___morestack
 ; X32-MinGW-NEXT:  ret
 
-; X64-FreeBSD:       test_fastcc:
+; X64-FreeBSD-LABEL:       test_fastcc:
 
 ; X64-FreeBSD:       cmpq %fs:24, %rsp
 ; X64-FreeBSD-NEXT:  ja      .LBB3_2
@@ -292,7 +292,7 @@ define fastcc void @test_fastcc_large() {
         call void @dummy_use (i32* %mem, i32 0)
         ret void
 
-; X32-Linux:       test_fastcc_large:
+; X32-Linux-LABEL:       test_fastcc_large:
 
 ; X32-Linux:       leal -40012(%esp), %eax
 ; X32-Linux-NEXT:  cmpl %gs:48, %eax
@@ -303,7 +303,7 @@ define fastcc void @test_fastcc_large() {
 ; X32-Linux-NEXT:  calll __morestack
 ; X32-Linux-NEXT:  ret
 
-; X64-Linux:       test_fastcc_large:
+; X64-Linux-LABEL:       test_fastcc_large:
 
 ; X64-Linux:       leaq -40008(%rsp), %r11
 ; X64-Linux-NEXT:  cmpq %fs:112, %r11
@@ -314,7 +314,7 @@ define fastcc void @test_fastcc_large() {
 ; X64-Linux-NEXT:  callq __morestack
 ; X64-Linux-NEXT:  ret
 
-; X32-Darwin:      test_fastcc_large:
+; X32-Darwin-LABEL:      test_fastcc_large:
 
 ; X32-Darwin:      leal -40012(%esp), %eax
 ; X32-Darwin-NEXT: movl $432, %ecx
@@ -326,7 +326,7 @@ define fastcc void @test_fastcc_large() {
 ; X32-Darwin-NEXT: calll ___morestack
 ; X32-Darwin-NEXT: ret
 
-; X64-Darwin:      test_fastcc_large:
+; X64-Darwin-LABEL:      test_fastcc_large:
 
 ; X64-Darwin:      leaq -40008(%rsp), %r11
 ; X64-Darwin-NEXT: cmpq %gs:816, %r11
@@ -337,7 +337,7 @@ define fastcc void @test_fastcc_large() {
 ; X64-Darwin-NEXT: callq ___morestack
 ; X64-Darwin-NEXT: ret
 
-; X32-MinGW:       test_fastcc_large:
+; X32-MinGW-LABEL:       test_fastcc_large:
 
 ; X32-MinGW:       leal -40008(%esp), %eax
 ; X32-MinGW-NEXT:  cmpl %fs:20, %eax
@@ -348,7 +348,7 @@ define fastcc void @test_fastcc_large() {
 ; X32-MinGW-NEXT:  calll ___morestack
 ; X32-MinGW-NEXT:  ret
 
-; X64-FreeBSD:       test_fastcc_large:
+; X64-FreeBSD-LABEL:       test_fastcc_large:
 
 ; X64-FreeBSD:       leaq -40008(%rsp), %r11
 ; X64-FreeBSD-NEXT:  cmpq %fs:24, %r11
@@ -368,7 +368,7 @@ define fastcc void @test_fastcc_large_with_ecx_arg(i32 %a) {
 
 ; This is testing that the Mac implementation preserves ecx
 
-; X32-Darwin:      test_fastcc_large_with_ecx_arg:
+; X32-Darwin-LABEL:      test_fastcc_large_with_ecx_arg:
 
 ; X32-Darwin:      leal -40012(%esp), %eax
 ; X32-Darwin-NEXT: pushl %ecx
diff --git a/test/CodeGen/X86/select.ll b/test/CodeGen/X86/select.ll
index 09ca07b..5fe2b70 100644
--- a/test/CodeGen/X86/select.ll
+++ b/test/CodeGen/X86/select.ll
@@ -10,11 +10,11 @@ define i32 @test1(%0* %p, %0* %q, i1 %r) nounwind {
   %t4 = select i1 %r, %0 %t0, %0 %t1
   %t5 = extractvalue %0 %t4, 1
   ret i32 %t5
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: cmovneq %rdi, %rsi
 ; CHECK: movl (%rsi), %eax
 
-; ATOM: test1:
+; ATOM-LABEL: test1:
 ; ATOM: cmovneq %rdi, %rsi
 ; ATOM: movl (%rsi), %eax
 }
@@ -33,11 +33,11 @@ bb90:		; preds = %bb84, %bb72
 	unreachable
 bb91:		; preds = %bb84
 	ret i32 0
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movnew
 ; CHECK: movswl
 
-; ATOM: test2:
+; ATOM-LABEL: test2:
 ; ATOM: movnew
 ; ATOM: movswl
 }
@@ -51,10 +51,10 @@ entry:
 	%0 = icmp eq i32 %x, 0		; <i1> [#uses=1]
 	%iftmp.0.0 = select i1 %0, float 4.200000e+01, float 2.300000e+01		; <float> [#uses=1]
 	ret float %iftmp.0.0
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: movss	{{.*}},4), %xmm0
 
-; ATOM: test3:
+; ATOM-LABEL: test3:
 ; ATOM: movss  {{.*}},4), %xmm0
 }
 
@@ -65,10 +65,10 @@ entry:
 	%1 = getelementptr i8* %P, i32 %iftmp.0.0		; <i8*> [#uses=1]
 	%2 = load i8* %1, align 1		; <i8> [#uses=1]
 	ret i8 %2
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: movsbl	({{.*}},4), %eax
 
-; ATOM: test4:
+; ATOM-LABEL: test4:
 ; ATOM: movsbl ({{.*}},4), %eax
 }
 
@@ -76,9 +76,9 @@ define void @test5(i1 %c, <2 x i16> %a, <2 x i16> %b, <2 x i16>* %p) nounwind {
   %x = select i1 %c, <2 x i16> %a, <2 x i16> %b
   store <2 x i16> %x, <2 x i16>* %p
   ret void
-; CHECK: test5:
+; CHECK-LABEL: test5:
 
-; ATOM: test5:
+; ATOM-LABEL: test5:
 }
 
 define void @test6(i32 %C, <4 x float>* %A, <4 x float>* %B) nounwind {
@@ -91,13 +91,13 @@ define void @test6(i32 %C, <4 x float>* %A, <4 x float>* %B) nounwind {
         ret void
 ; Verify that the fmul gets sunk into the one part of the diamond where it is
 ; needed.
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: je
 ; CHECK: ret
 ; CHECK: mulps
 ; CHECK: ret
 
-; ATOM: test6:
+; ATOM-LABEL: test6:
 ; ATOM: je
 ; ATOM: ret
 ; ATOM: mulps
@@ -109,11 +109,11 @@ define x86_fp80 @test7(i32 %tmp8) nounwind {
         %tmp9 = icmp sgt i32 %tmp8, -1          ; <i1> [#uses=1]
         %retval = select i1 %tmp9, x86_fp80 0xK4005B400000000000000, x86_fp80 0xK40078700000000000000
         ret x86_fp80 %retval
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: leaq
 ; CHECK: fldt (%r{{.}}x,%r{{.}}x)
 
-; ATOM: test7:
+; ATOM-LABEL: test7:
 ; ATOM: leaq
 ; ATOM: fldt (%r{{.}}x,%r{{.}}x)
 }
@@ -125,9 +125,9 @@ define void @test8(i1 %c, <6 x i32>* %dst.addr, <6 x i32> %src1,<6 x i32> %src2)
 	store <6 x i32> %val, <6 x i32>* %dst.addr
 	ret void
 
-; CHECK: test8:
+; CHECK-LABEL: test8:
 
-; ATOM: test8:
+; ATOM-LABEL: test8:
 }
 
 
@@ -137,13 +137,13 @@ define i64 @test9(i64 %x, i64 %y) nounwind readnone ssp noredzone {
   %cmp = icmp ne i64 %x, 0
   %cond = select i1 %cmp, i64 %y, i64 -1
   ret i64 %cond
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: cmpq	$1, %rdi
 ; CHECK: sbbq	%rax, %rax
 ; CHECK: orq	%rsi, %rax
 ; CHECK: ret
 
-; ATOM: test9:
+; ATOM-LABEL: test9:
 ; ATOM: cmpq   $1, %rdi
 ; ATOM: sbbq   %rax, %rax
 ; ATOM: orq    %rsi, %rax
@@ -155,13 +155,13 @@ define i64 @test9a(i64 %x, i64 %y) nounwind readnone ssp noredzone {
   %cmp = icmp eq i64 %x, 0
   %cond = select i1 %cmp, i64 -1, i64 %y
   ret i64 %cond
-; CHECK: test9a:
+; CHECK-LABEL: test9a:
 ; CHECK: cmpq	$1, %rdi
 ; CHECK: sbbq	%rax, %rax
 ; CHECK: orq	%rsi, %rax
 ; CHECK: ret
 
-; ATOM: test9a:
+; ATOM-LABEL: test9a:
 ; ATOM: cmpq   $1, %rdi
 ; ATOM: sbbq   %rax, %rax
 ; ATOM: orq    %rsi, %rax
@@ -173,13 +173,13 @@ define i64 @test9b(i64 %x, i64 %y) nounwind readnone ssp noredzone {
   %A = sext i1 %cmp to i64
   %cond = or i64 %y, %A
   ret i64 %cond
-; CHECK: test9b:
+; CHECK-LABEL: test9b:
 ; CHECK: cmpq	$1, %rdi
 ; CHECK: sbbq	%rax, %rax
 ; CHECK: orq	%rsi, %rax
 ; CHECK: ret
 
-; ATOM: test9b:
+; ATOM-LABEL: test9b:
 ; ATOM: cmpq   $1, %rdi
 ; ATOM: sbbq   %rax, %rax
 ; ATOM: orq    %rsi, %rax
@@ -191,13 +191,13 @@ define i64 @test10(i64 %x, i64 %y) nounwind readnone ssp noredzone {
   %cmp = icmp eq i64 %x, 0
   %cond = select i1 %cmp, i64 -1, i64 1
   ret i64 %cond
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: cmpq	$1, %rdi
 ; CHECK: sbbq	%rax, %rax
 ; CHECK: orq	$1, %rax
 ; CHECK: ret
 
-; ATOM: test10:
+; ATOM-LABEL: test10:
 ; ATOM: cmpq   $1, %rdi
 ; ATOM: sbbq   %rax, %rax
 ; ATOM: orq    $1, %rax
@@ -210,14 +210,14 @@ define i64 @test11(i64 %x, i64 %y) nounwind readnone ssp noredzone {
   %cmp = icmp eq i64 %x, 0
   %cond = select i1 %cmp, i64 %y, i64 -1
   ret i64 %cond
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK: cmpq	$1, %rdi
 ; CHECK: sbbq	%rax, %rax
 ; CHECK: notq %rax
 ; CHECK: orq	%rsi, %rax
 ; CHECK: ret
 
-; ATOM: test11:
+; ATOM-LABEL: test11:
 ; ATOM: cmpq   $1, %rdi
 ; ATOM: sbbq   %rax, %rax
 ; ATOM: notq %rax
@@ -229,14 +229,14 @@ define i64 @test11a(i64 %x, i64 %y) nounwind readnone ssp noredzone {
   %cmp = icmp ne i64 %x, 0
   %cond = select i1 %cmp, i64 -1, i64 %y
   ret i64 %cond
-; CHECK: test11a:
+; CHECK-LABEL: test11a:
 ; CHECK: cmpq	$1, %rdi
 ; CHECK: sbbq	%rax, %rax
 ; CHECK: notq %rax
 ; CHECK: orq	%rsi, %rax
 ; CHECK: ret
 
-; ATOM: test11a:
+; ATOM-LABEL: test11a:
 ; ATOM: cmpq   $1, %rdi
 ; ATOM: sbbq   %rax, %rax
 ; ATOM: notq %rax
@@ -255,13 +255,13 @@ entry:
   %D = select i1 %B, i64 -1, i64 %C
   %call = tail call noalias i8* @_Znam(i64 %D) nounwind noredzone
   ret i8* %call
-; CHECK: test12:
-; CHECK: movq $-1, %rdi
+; CHECK-LABEL: test12:
+; CHECK: movq $-1, %[[R:r..]]
 ; CHECK: mulq
-; CHECK: cmovnoq	%rax, %rdi
+; CHECK: cmovnoq	%rax, %[[R]]
 ; CHECK: jmp	__Znam
 
-; ATOM: test12:
+; ATOM-LABEL: test12:
 ; ATOM: mulq
 ; ATOM: movq $-1, %rdi
 ; ATOM: cmovnoq        %rax, %rdi
@@ -274,12 +274,12 @@ define i32 @test13(i32 %a, i32 %b) nounwind {
   %c = icmp ult i32 %a, %b
   %d = sext i1 %c to i32
   ret i32 %d
-; CHECK: test13:
+; CHECK-LABEL: test13:
 ; CHECK: cmpl
 ; CHECK-NEXT: sbbl
 ; CHECK-NEXT: ret
 
-; ATOM: test13:
+; ATOM-LABEL: test13:
 ; ATOM: cmpl
 ; ATOM-NEXT: sbbl
 ; ATOM: ret
@@ -289,13 +289,13 @@ define i32 @test14(i32 %a, i32 %b) nounwind {
   %c = icmp uge i32 %a, %b
   %d = sext i1 %c to i32
   ret i32 %d
-; CHECK: test14:
+; CHECK-LABEL: test14:
 ; CHECK: cmpl
 ; CHECK-NEXT: sbbl
 ; CHECK-NEXT: notl
 ; CHECK-NEXT: ret
 
-; ATOM: test14:
+; ATOM-LABEL: test14:
 ; ATOM: cmpl
 ; ATOM-NEXT: sbbl
 ; ATOM-NEXT: notl
@@ -308,11 +308,11 @@ entry:
   %cmp = icmp ne i32 %x, 0
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK: test15:
+; CHECK-LABEL: test15:
 ; CHECK: negl
 ; CHECK: sbbl
 
-; ATOM: test15:
+; ATOM-LABEL: test15:
 ; ATOM: negl
 ; ATOM: sbbl
 }
@@ -322,11 +322,11 @@ entry:
   %cmp = icmp ne i64 %x, 0
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
-; CHECK: test16:
+; CHECK-LABEL: test16:
 ; CHECK: negq
 ; CHECK: sbbq
 
-; ATOM: test16:
+; ATOM-LABEL: test16:
 ; ATOM: negq
 ; ATOM: sbbq
 }
@@ -336,11 +336,11 @@ entry:
   %cmp = icmp ne i16 %x, 0
   %sub = sext i1 %cmp to i16
   ret i16 %sub
-; CHECK: test17:
+; CHECK-LABEL: test17:
 ; CHECK: negw
 ; CHECK: sbbw
 
-; ATOM: test17:
+; ATOM-LABEL: test17:
 ; ATOM: negw
 ; ATOM: sbbw
 }
@@ -349,11 +349,11 @@ define i8 @test18(i32 %x, i8 zeroext %a, i8 zeroext %b) nounwind {
   %cmp = icmp slt i32 %x, 15
   %sel = select i1 %cmp, i8 %a, i8 %b
   ret i8 %sel
-; CHECK: test18:
+; CHECK-LABEL: test18:
 ; CHECK: cmpl $15, %edi
 ; CHECK: cmovgel %edx
 
-; ATOM: test18:
+; ATOM-LABEL: test18:
 ; ATOM: cmpl $15, %edi
 ; ATOM: cmovgel %edx
 }
diff --git a/test/CodeGen/X86/select_const.ll b/test/CodeGen/X86/select_const.ll
index 5b2409d..a6c2377 100644
--- a/test/CodeGen/X86/select_const.ll
+++ b/test/CodeGen/X86/select_const.ll
@@ -7,7 +7,7 @@ entry:
   %retval.0 = select i1 %cmp, i64 2, i64 %add
   ret i64 %retval.0
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: leaq 1(%rdi), %rax
 ; CHECK: cmpq $2, %rdi
 ; CHECK: cmoveq %rdi, %rax
diff --git a/test/CodeGen/X86/setcc.ll b/test/CodeGen/X86/setcc.ll
index c37e15d..2454af9 100644
--- a/test/CodeGen/X86/setcc.ll
+++ b/test/CodeGen/X86/setcc.ll
@@ -6,7 +6,7 @@
 
 define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: seta %al
 ; CHECK: movzbl %al, %eax
 ; CHECK: shll $5, %eax
@@ -17,7 +17,7 @@ entry:
 
 define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: sbbl %eax, %eax
 ; CHECK: andl $32, %eax
   %0 = icmp ult i16 %x, 26                        ; <i1> [#uses=1]
@@ -27,7 +27,7 @@ entry:
 
 define i64 @t3(i64 %x) nounwind readnone ssp {
 entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: sbbq %rax, %rax
 ; CHECK: andq $64, %rax
   %0 = icmp ult i64 %x, 18                        ; <i1> [#uses=1]
diff --git a/test/CodeGen/X86/sext-i1.ll b/test/CodeGen/X86/sext-i1.ll
index 574769b..64de0ae 100644
--- a/test/CodeGen/X86/sext-i1.ll
+++ b/test/CodeGen/X86/sext-i1.ll
@@ -5,11 +5,11 @@
 
 define i32 @t1(i32 %x) nounwind readnone ssp {
 entry:
-; 32: t1:
+; 32-LABEL: t1:
 ; 32: cmpl $1
 ; 32: sbbl
 
-; 64: t1:
+; 64-LABEL: t1:
 ; 64: cmpl $1
 ; 64: sbbl
   %0 = icmp eq i32 %x, 0
@@ -19,11 +19,11 @@ entry:
 
 define i32 @t2(i32 %x) nounwind readnone ssp {
 entry:
-; 32: t2:
+; 32-LABEL: t2:
 ; 32: cmpl $1
 ; 32: sbbl
 
-; 64: t2:
+; 64-LABEL: t2:
 ; 64: cmpl $1
 ; 64: sbbl
   %0 = icmp eq i32 %x, 0
@@ -36,13 +36,13 @@ entry:
 
 define i32 @t3() nounwind readonly {
 entry:
-; 32: t3:
+; 32-LABEL: t3:
 ; 32: cmpl $1
 ; 32: sbbl
 ; 32: cmpl
 ; 32: xorl
 
-; 64: t3:
+; 64-LABEL: t3:
 ; 64: cmpl $1
 ; 64: sbbq
 ; 64: cmpq
diff --git a/test/CodeGen/X86/sext-load.ll b/test/CodeGen/X86/sext-load.ll
index 58c9322..2753e87 100644
--- a/test/CodeGen/X86/sext-load.ll
+++ b/test/CodeGen/X86/sext-load.ll
@@ -3,7 +3,7 @@
 ; When doing sign extension, use the sext-load lowering to take advantage of
 ; x86's sign extension during loads.
 ;
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK:      movsbl {{.*}}, %eax
 ; CHECK-NEXT: ret
 define i32 @test1(i32 %X) nounwind  {
@@ -16,7 +16,7 @@ entry:
 ; When using a sextload representation, ensure that the sign extension is
 ; preserved even when removing shifted-out low bits.
 ;
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK:      movswl {{.*}}, %eax
 ; CHECK-NEXT: ret
 define i32 @test2({i16, [6 x i8]}* %this) {
diff --git a/test/CodeGen/X86/sext-subreg.ll b/test/CodeGen/X86/sext-subreg.ll
index a128af9..e0c8ff9 100644
--- a/test/CodeGen/X86/sext-subreg.ll
+++ b/test/CodeGen/X86/sext-subreg.ll
@@ -2,7 +2,7 @@
 ; rdar://7529457
 
 define i64 @t(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: movslq %e{{.*}}, %rax
 ; CHECK: movq %rax
 ; CHECK: movl %eax
diff --git a/test/CodeGen/X86/shift-and.ll b/test/CodeGen/X86/shift-and.ll
index 1de9151..d487368 100644
--- a/test/CodeGen/X86/shift-and.ll
+++ b/test/CodeGen/X86/shift-and.ll
@@ -2,11 +2,11 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s --check-prefix=X64
 
 define i32 @t1(i32 %t, i32 %val) nounwind {
-; X32: t1:
+; X32-LABEL: t1:
 ; X32-NOT: andl
 ; X32: shll
 
-; X64: t1:
+; X64-LABEL: t1:
 ; X64-NOT: andl
 ; X64: shll
        %shamt = and i32 %t, 31
@@ -15,11 +15,11 @@ define i32 @t1(i32 %t, i32 %val) nounwind {
 }
 
 define i32 @t2(i32 %t, i32 %val) nounwind {
-; X32: t2:
+; X32-LABEL: t2:
 ; X32-NOT: andl
 ; X32: shll
 
-; X64: t2:
+; X64-LABEL: t2:
 ; X64-NOT: andl
 ; X64: shll
        %shamt = and i32 %t, 63
@@ -30,11 +30,11 @@ define i32 @t2(i32 %t, i32 %val) nounwind {
 @X = internal global i16 0
 
 define void @t3(i16 %t) nounwind {
-; X32: t3:
+; X32-LABEL: t3:
 ; X32-NOT: andl
 ; X32: sarw
 
-; X64: t3:
+; X64-LABEL: t3:
 ; X64-NOT: andl
 ; X64: sarw
        %shamt = and i16 %t, 31
@@ -45,7 +45,7 @@ define void @t3(i16 %t) nounwind {
 }
 
 define i64 @t4(i64 %t, i64 %val) nounwind {
-; X64: t4:
+; X64-LABEL: t4:
 ; X64-NOT: and
 ; X64: shrq
        %shamt = and i64 %t, 63
@@ -54,7 +54,7 @@ define i64 @t4(i64 %t, i64 %val) nounwind {
 }
 
 define i64 @t5(i64 %t, i64 %val) nounwind {
-; X64: t5:
+; X64-LABEL: t5:
 ; X64-NOT: and
 ; X64: shrq
        %shamt = and i64 %t, 191
@@ -66,7 +66,7 @@ define i64 @t5(i64 %t, i64 %val) nounwind {
 ; rdar://11866926
 define i64 @t6(i64 %key, i64* nocapture %val) nounwind {
 entry:
-; X64: t6:
+; X64-LABEL: t6:
 ; X64-NOT: movabsq
 ; X64: decq
 ; X64: andq
diff --git a/test/CodeGen/X86/shift-bmi2.ll b/test/CodeGen/X86/shift-bmi2.ll
index d1f321f..0116789 100644
--- a/test/CodeGen/X86/shift-bmi2.ll
+++ b/test/CodeGen/X86/shift-bmi2.ll
@@ -83,7 +83,7 @@ define i64 @shl64pi(i64* %p) nounwind uwtable readnone {
 entry:
   %x = load i64* %p
   %shl = shl i64 %x, 7
-; BMI264: shl64p
+; BMI264: shl64pi
 ; BMI264-NOT: shlxq
 ; BMI264: ret
   ret i64 %shl
@@ -108,7 +108,7 @@ entry:
 ; BMI2: lshr32p
 ; BMI2: shrxl %{{.+}}, ({{.+}}), %{{.+}}
 ; BMI2: ret
-; BMI264: lshr32
+; BMI264: lshr32p
 ; BMI264: shrxl %{{.+}}, ({{.+}}), %{{.+}}
 ; BMI264: ret
   ret i32 %shl
@@ -152,7 +152,7 @@ entry:
 ; BMI2: ashr32p
 ; BMI2: sarxl %{{.+}}, ({{.+}}), %{{.+}}
 ; BMI2: ret
-; BMI264: ashr32
+; BMI264: ashr32p
 ; BMI264: sarxl %{{.+}}, ({{.+}}), %{{.+}}
 ; BMI264: ret
   ret i32 %shl
diff --git a/test/CodeGen/X86/shift-coalesce.ll b/test/CodeGen/X86/shift-coalesce.ll
index 4f27e97..5241042 100644
--- a/test/CodeGen/X86/shift-coalesce.ll
+++ b/test/CodeGen/X86/shift-coalesce.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
-; RUN:   grep "shld.*CL"
+; RUN:   grep "shld.*cl"
 ; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | \
-; RUN:   not grep "mov CL, BL"
+; RUN:   not grep "mov cl, bl"
 
 ; PR687
 
diff --git a/test/CodeGen/X86/shift-codegen.ll b/test/CodeGen/X86/shift-codegen.ll
index 7d961e8..88b8610 100644
--- a/test/CodeGen/X86/shift-codegen.ll
+++ b/test/CodeGen/X86/shift-codegen.ll
@@ -8,7 +8,7 @@ target triple = "i686-apple-darwin8"
 
 
 define void @fn1() {
-; CHECK: fn1:
+; CHECK-LABEL: fn1:
 ; CHECK-NOT: ret
 ; CHECK-NOT: lea
 ; CHECK: shll $3
@@ -24,7 +24,7 @@ define void @fn1() {
 }
 
 define i32 @fn2(i32 %X, i32 %Y) {
-; CHECK: fn2:
+; CHECK-LABEL: fn2:
 ; CHECK-NOT: ret
 ; CHECK-NOT: lea
 ; CHECK: shll $3
diff --git a/test/CodeGen/X86/shift-combine.ll b/test/CodeGen/X86/shift-combine.ll
index 51f8303..113dedb 100644
--- a/test/CodeGen/X86/shift-combine.ll
+++ b/test/CodeGen/X86/shift-combine.ll
@@ -3,7 +3,7 @@
 @array = weak global [4 x i32] zeroinitializer
 
 define i32 @test_lshr_and(i32 %x) {
-; CHECK: test_lshr_and:
+; CHECK-LABEL: test_lshr_and:
 ; CHECK-NOT: shrl
 ; CHECK: andl $12,
 ; CHECK: movl {{.*}}array{{.*}},
diff --git a/test/CodeGen/X86/shift-folding.ll b/test/CodeGen/X86/shift-folding.ll
index c518cdd..ea9002c 100644
--- a/test/CodeGen/X86/shift-folding.ll
+++ b/test/CodeGen/X86/shift-folding.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86 -verify-coalescing | FileCheck %s
 
 define i32* @test1(i32* %P, i32 %X) {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: shrl
 ; CHECK-NOT: shll
 ; CHECK: ret
@@ -14,7 +14,7 @@ entry:
 }
 
 define i32* @test2(i32* %P, i32 %X) {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: shll $4
 ; CHECK-NOT: shll
 ; CHECK: ret
@@ -27,7 +27,7 @@ entry:
 }
 
 define i32* @test3(i32* %P, i32 %X) {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK-NOT: shrl
 ; CHECK-NOT: shll
 ; CHECK: ret
@@ -39,7 +39,7 @@ entry:
 }
 
 define fastcc i32 @test4(i32* %d) {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK-NOT: shrl
 ; CHECK: ret
 
@@ -52,7 +52,7 @@ entry:
 define i64 @test5(i16 %i, i32* %arr) {
 ; Ensure that we don't fold away shifts which have multiple uses, as they are
 ; just re-introduced for the second use.
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK-NOT: shrl
 ; CHECK: shrl $11
 ; CHECK-NOT: shrl
diff --git a/test/CodeGen/X86/shl-anyext.ll b/test/CodeGen/X86/shl-anyext.ll
index 10d489b..0a5d047 100644
--- a/test/CodeGen/X86/shl-anyext.ll
+++ b/test/CodeGen/X86/shl-anyext.ll
@@ -17,7 +17,7 @@ if.end523:                                        ; preds = %if.end453
   ret void
 }
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 
 declare void @bar(i64)
 
diff --git a/test/CodeGen/X86/shl_elim.ll b/test/CodeGen/X86/shl_elim.ll
index 83e1eb5..4762b13 100644
--- a/test/CodeGen/X86/shl_elim.ll
+++ b/test/CodeGen/X86/shl_elim.ll
@@ -1,6 +1,4 @@
-; RUN: llc < %s -march=x86 | grep "movl	8(.esp), %eax"
-; RUN: llc < %s -march=x86 | grep "shrl	.eax"
-; RUN: llc < %s -march=x86 | grep "movswl	.ax, .eax"
+; RUN: llc < %s -march=x86 | FileCheck %s
 
 define i32 @test1(i64 %a) nounwind {
         %tmp29 = lshr i64 %a, 24                ; <i64> [#uses=1]
@@ -9,5 +7,10 @@ define i32 @test1(i64 %a) nounwind {
         %tmp45 = trunc i32 %tmp410 to i16               ; <i16> [#uses=1]
         %tmp456 = sext i16 %tmp45 to i32                ; <i32> [#uses=1]
         ret i32 %tmp456
+
+; CHECK-LABEL: test1:
+; CHECK: movl 8(%esp), %eax
+; CHECK: shrl %eax
+; CHECK: cwtl
 }
 
diff --git a/test/CodeGen/X86/shrink-compare.ll b/test/CodeGen/X86/shrink-compare.ll
index 83793f0..bb89201 100644
--- a/test/CodeGen/X86/shrink-compare.ll
+++ b/test/CodeGen/X86/shrink-compare.ll
@@ -15,7 +15,7 @@ if.then:
 
 if.end:
   ret void
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: cmpb $47, (%{{rdi|rcx}})
 }
 
@@ -31,7 +31,7 @@ if.then:
 
 if.end:
   ret void
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: cmpb $47, %{{dil|cl}}
 }
 
@@ -47,7 +47,7 @@ if.then:
 
 if.end:
   ret void
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: cmpb $-1, %{{dil|cl}}
 }
 
@@ -66,3 +66,26 @@ lor.end:                                          ; preds = %lor.rhs, %entry
   %p = phi i1 [ true, %entry ], [ %tobool1, %lor.rhs ]
   ret i1 %p
 }
+
+@x = global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 1 }, align 4
+
+; PR16551
+define void @test5(i32 %X) nounwind {
+entry:
+  %bf.load = load i56* bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @x to i56*), align 4
+  %bf.lshr = lshr i56 %bf.load, 32
+  %bf.cast = trunc i56 %bf.lshr to i32
+  %cmp = icmp ne i32 %bf.cast, 1
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  tail call void @bar() nounwind
+  br label %if.end
+
+if.end:
+  ret void
+
+; CHECK-LABEL: test5:
+; CHECK-NOT: cmpl $1,{{.*}}x+4
+; CHECK: ret
+}
diff --git a/test/CodeGen/X86/sibcall-2.ll b/test/CodeGen/X86/sibcall-2.ll
index f8a7465..1b9d2db 100644
--- a/test/CodeGen/X86/sibcall-2.ll
+++ b/test/CodeGen/X86/sibcall-2.ll
@@ -5,10 +5,10 @@
 
 define void @t1(i8* nocapture %value) nounwind {
 entry:
-; 32: t1:
+; 32-LABEL: t1:
 ; 32: jmpl *4(%esp)
 
-; 64: t1:
+; 64-LABEL: t1:
 ; 64: jmpq *%rdi
   %0 = bitcast i8* %value to void ()*
   tail call void %0() nounwind
@@ -17,10 +17,10 @@ entry:
 
 define void @t2(i32 %a, i8* nocapture %value) nounwind {
 entry:
-; 32: t2:
+; 32-LABEL: t2:
 ; 32: jmpl *8(%esp)
 
-; 64: t2:
+; 64-LABEL: t2:
 ; 64: jmpq *%rsi
   %0 = bitcast i8* %value to void ()*
   tail call void %0() nounwind
@@ -29,10 +29,10 @@ entry:
 
 define void @t3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i8* nocapture %value) nounwind {
 entry:
-; 32: t3:
+; 32-LABEL: t3:
 ; 32: jmpl *28(%esp)
 
-; 64: t3:
+; 64-LABEL: t3:
 ; 64: jmpq *8(%rsp)
   %0 = bitcast i8* %value to void ()*
   tail call void %0() nounwind
@@ -41,10 +41,10 @@ entry:
 
 define void @t4(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i8* nocapture %value) nounwind {
 entry:
-; 32: t4:
+; 32-LABEL: t4:
 ; 32: jmpl *32(%esp)
 
-; 64: t4:
+; 64-LABEL: t4:
 ; 64: jmpq *16(%rsp)
   %0 = bitcast i8* %value to void ()*
   tail call void %0() nounwind
diff --git a/test/CodeGen/X86/sibcall-3.ll b/test/CodeGen/X86/sibcall-3.ll
index f97abe0..9fcb460 100644
--- a/test/CodeGen/X86/sibcall-3.ll
+++ b/test/CodeGen/X86/sibcall-3.ll
@@ -2,14 +2,14 @@
 ; PR7193
 
 define void @t1(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: calll 0
   tail call void null(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind
   ret void
 }
 
 define void @t2(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: jmpl
   tail call void null(i8* inreg %dst, i8* inreg %src) nounwind
   ret void
diff --git a/test/CodeGen/X86/sibcall-4.ll b/test/CodeGen/X86/sibcall-4.ll
index 1499e66..980b0f7 100644
--- a/test/CodeGen/X86/sibcall-4.ll
+++ b/test/CodeGen/X86/sibcall-4.ll
@@ -3,7 +3,7 @@
 
 define cc10 void @t(i32* %Base_Arg, i32* %Sp_Arg, i32* %Hp_Arg, i32 %R1_Arg) nounwind {
 cm1:
-; CHECK: t:
+; CHECK-LABEL: t:
 ; CHECK: jmpl *%eax
   %nm3 = getelementptr i32* %Sp_Arg, i32 1
   %nm9 = load i32* %Sp_Arg
diff --git a/test/CodeGen/X86/sibcall-5.ll b/test/CodeGen/X86/sibcall-5.ll
index 937817e..c479030 100644
--- a/test/CodeGen/X86/sibcall-5.ll
+++ b/test/CodeGen/X86/sibcall-5.ll
@@ -7,20 +7,20 @@
 
 define double @foo(double %a) nounwind readonly ssp {
 entry:
-; X32: foo:
+; X32-LABEL: foo:
 ; X32: jmp _sin$stub
 
-; X64: foo:
+; X64-LABEL: foo:
 ; X64: jmp _sin
   %0 = tail call double @sin(double %a) nounwind readonly
   ret double %0
 }
 
 define float @bar(float %a) nounwind readonly ssp {
-; X32: bar:
+; X32-LABEL: bar:
 ; X32: jmp _sinf$stub
 
-; X64: bar:
+; X64-LABEL: bar:
 ; X64: jmp _sinf
 entry:
   %0 = tail call float @sinf(float %a) nounwind readonly
diff --git a/test/CodeGen/X86/sibcall-6.ll b/test/CodeGen/X86/sibcall-6.ll
index 2cdc3c4..c9dff6b 100644
--- a/test/CodeGen/X86/sibcall-6.ll
+++ b/test/CodeGen/X86/sibcall-6.ll
@@ -6,7 +6,7 @@ target triple = "i386-unknown-linux-gnu"
 
 declare void @callee1(i32 inreg, i32 inreg, i32 inreg)
 define void @test1(i32 %a, i32 %b) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: calll callee1@PLT
   tail call void @callee1(i32 inreg 0, i32 inreg 0, i32 inreg 0) nounwind
   ret void
diff --git a/test/CodeGen/X86/sibcall.ll b/test/CodeGen/X86/sibcall.ll
index de98cb4..7b774f6 100644
--- a/test/CodeGen/X86/sibcall.ll
+++ b/test/CodeGen/X86/sibcall.ll
@@ -3,10 +3,10 @@
 
 define void @t1(i32 %x) nounwind ssp {
 entry:
-; 32: t1:
+; 32-LABEL: t1:
 ; 32: jmp {{_?}}foo
 
-; 64: t1:
+; 64-LABEL: t1:
 ; 64: jmp {{_?}}foo
   tail call void @foo() nounwind
   ret void
@@ -16,10 +16,10 @@ declare void @foo()
 
 define void @t2() nounwind ssp {
 entry:
-; 32: t2:
+; 32-LABEL: t2:
 ; 32: jmp {{_?}}foo2
 
-; 64: t2:
+; 64-LABEL: t2:
 ; 64: jmp {{_?}}foo2
   %0 = tail call i32 @foo2() nounwind
   ret void
@@ -29,10 +29,10 @@ declare i32 @foo2()
 
 define void @t3() nounwind ssp {
 entry:
-; 32: t3:
+; 32-LABEL: t3:
 ; 32: jmp {{_?}}foo3
 
-; 64: t3:
+; 64-LABEL: t3:
 ; 64: jmp {{_?}}foo3
   %0 = tail call i32 @foo3() nounwind
   ret void
@@ -42,11 +42,11 @@ declare i32 @foo3()
 
 define void @t4(void (i32)* nocapture %x) nounwind ssp {
 entry:
-; 32: t4:
+; 32-LABEL: t4:
 ; 32: calll *
 ; FIXME: gcc can generate a tailcall for this. But it's tricky.
 
-; 64: t4:
+; 64-LABEL: t4:
 ; 64-NOT: call
 ; 64: jmpq *
   tail call void %x(i32 0) nounwind
@@ -55,11 +55,11 @@ entry:
 
 define void @t5(void ()* nocapture %x) nounwind ssp {
 entry:
-; 32: t5:
+; 32-LABEL: t5:
 ; 32-NOT: call
 ; 32: jmpl *4(%esp)
 
-; 64: t5:
+; 64-LABEL: t5:
 ; 64-NOT: call
 ; 64: jmpq *%rdi
   tail call void %x() nounwind
@@ -68,11 +68,11 @@ entry:
 
 define i32 @t6(i32 %x) nounwind ssp {
 entry:
-; 32: t6:
+; 32-LABEL: t6:
 ; 32: calll {{_?}}t6
 ; 32: jmp {{_?}}bar
 
-; 64: t6:
+; 64-LABEL: t6:
 ; 64: jmp {{_?}}t6
 ; 64: jmp {{_?}}bar
   %0 = icmp slt i32 %x, 10
@@ -92,10 +92,10 @@ declare i32 @bar(i32)
 
 define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind ssp {
 entry:
-; 32: t7:
+; 32-LABEL: t7:
 ; 32: jmp {{_?}}bar2
 
-; 64: t7:
+; 64-LABEL: t7:
 ; 64: jmp {{_?}}bar2
   %0 = tail call i32 @bar2(i32 %a, i32 %b, i32 %c) nounwind
   ret i32 %0
@@ -105,10 +105,10 @@ declare i32 @bar2(i32, i32, i32)
 
 define signext i16 @t8() nounwind ssp {
 entry:
-; 32: t8:
+; 32-LABEL: t8:
 ; 32: calll {{_?}}bar3
 
-; 64: t8:
+; 64-LABEL: t8:
 ; 64: callq {{_?}}bar3
   %0 = tail call signext i16 @bar3() nounwind      ; <i16> [#uses=1]
   ret i16 %0
@@ -118,10 +118,10 @@ declare signext i16 @bar3()
 
 define signext i16 @t9(i32 (i32)* nocapture %x) nounwind ssp {
 entry:
-; 32: t9:
+; 32-LABEL: t9:
 ; 32: calll *
 
-; 64: t9:
+; 64-LABEL: t9:
 ; 64: callq *
   %0 = bitcast i32 (i32)* %x to i16 (i32)*
   %1 = tail call signext i16 %0(i32 0) nounwind
@@ -130,10 +130,10 @@ entry:
 
 define void @t10() nounwind ssp {
 entry:
-; 32: t10:
+; 32-LABEL: t10:
 ; 32: calll
 
-; 64: t10:
+; 64-LABEL: t10:
 ; 64: callq
   %0 = tail call i32 @foo4() noreturn nounwind
   unreachable
@@ -145,14 +145,14 @@ define i32 @t11(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind ssp {
 ; In 32-bit mode, it's emitting a bunch of dead loads that are not being
 ; eliminated currently.
 
-; 32: t11:
+; 32-LABEL: t11:
 ; 32-NOT: subl ${{[0-9]+}}, %esp
 ; 32: je
 ; 32-NOT: movl
 ; 32-NOT: addl ${{[0-9]+}}, %esp
 ; 32: jmp {{_?}}foo5
 
-; 64: t11:
+; 64-LABEL: t11:
 ; 64-NOT: subq ${{[0-9]+}}, %esp
 ; 64-NOT: addq ${{[0-9]+}}, %esp
 ; 64: jmp {{_?}}foo5
@@ -173,12 +173,12 @@ declare i32 @foo5(i32, i32, i32, i32, i32)
 %struct.t = type { i32, i32, i32, i32, i32 }
 
 define i32 @t12(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind ssp {
-; 32: t12:
+; 32-LABEL: t12:
 ; 32-NOT: subl ${{[0-9]+}}, %esp
 ; 32-NOT: addl ${{[0-9]+}}, %esp
 ; 32: jmp {{_?}}foo6
 
-; 64: t12:
+; 64-LABEL: t12:
 ; 64-NOT: subq ${{[0-9]+}}, %esp
 ; 64-NOT: addq ${{[0-9]+}}, %esp
 ; 64: jmp {{_?}}foo6
@@ -201,12 +201,12 @@ declare i32 @foo6(i32, i32, %struct.t* byval align 4)
 %struct.cp = type { float, float, float, float, float }
 
 define %struct.ns* @t13(%struct.cp* %yy) nounwind ssp {
-; 32: t13:
+; 32-LABEL: t13:
 ; 32-NOT: jmp
 ; 32: calll
 ; 32: ret
 
-; 64: t13:
+; 64-LABEL: t13:
 ; 64-NOT: jmp
 ; 64: callq
 ; 64: ret
@@ -226,7 +226,7 @@ declare fastcc %struct.ns* @foo7(%struct.cp* byval align 4, i8 signext) nounwind
 
 define void @t14(%struct.__block_literal_2* nocapture %.block_descriptor) nounwind ssp {
 entry:
-; 64: t14:
+; 64-LABEL: t14:
 ; 64: movq 32(%rdi)
 ; 64-NOT: movq 16(%rdi)
 ; 64: jmpq *16({{%rdi|%rax}})
@@ -245,11 +245,11 @@ entry:
 %struct.foo = type { [4 x i32] }
 
 define void @t15(%struct.foo* noalias sret %agg.result) nounwind  {
-; 32: t15:
+; 32-LABEL: t15:
 ; 32: calll {{_?}}f
 ; 32: ret $4
 
-; 64: t15:
+; 64-LABEL: t15:
 ; 64: callq {{_?}}f
 ; 64: ret
   tail call fastcc void @f(%struct.foo* noalias sret %agg.result) nounwind
@@ -260,11 +260,11 @@ declare void @f(%struct.foo* noalias sret) nounwind
 
 define void @t16() nounwind ssp {
 entry:
-; 32: t16:
+; 32-LABEL: t16:
 ; 32: calll {{_?}}bar4
 ; 32: fstp
 
-; 64: t16:
+; 64-LABEL: t16:
 ; 64: jmp {{_?}}bar4
   %0 = tail call double @bar4() nounwind
   ret void
@@ -275,10 +275,10 @@ declare double @bar4()
 ; rdar://6283267
 define void @t17() nounwind ssp {
 entry:
-; 32: t17:
+; 32-LABEL: t17:
 ; 32: jmp {{_?}}bar5
 
-; 64: t17:
+; 64-LABEL: t17:
 ; 64: xorl %eax, %eax
 ; 64: jmp {{_?}}bar5
   tail call void (...)* @bar5() nounwind
@@ -290,11 +290,11 @@ declare void @bar5(...)
 ; rdar://7774847
 define void @t18() nounwind ssp {
 entry:
-; 32: t18:
+; 32-LABEL: t18:
 ; 32: calll {{_?}}bar6
 ; 32: fstp %st(0)
 
-; 64: t18:
+; 64-LABEL: t18:
 ; 64: xorl %eax, %eax
 ; 64: jmp {{_?}}bar6
   %0 = tail call double (...)* @bar6() nounwind
@@ -305,7 +305,7 @@ declare double @bar6(...)
 
 define void @t19() alignstack(32) nounwind {
 entry:
-; CHECK: t19:
+; CHECK-LABEL: t19:
 ; CHECK: andl $-32
 ; CHECK: calll {{_?}}foo
   tail call void @foo() nounwind
@@ -318,11 +318,11 @@ entry:
 
 define double @t20(double %x) nounwind {
 entry:
-; 32: t20:
+; 32-LABEL: t20:
 ; 32: calll {{_?}}foo20
 ; 32: fldl (%esp)
 
-; 64: t20:
+; 64-LABEL: t20:
 ; 64: jmp {{_?}}foo20
   %0 = tail call fastcc double @foo20(double %x) nounwind
   ret double %0
diff --git a/test/CodeGen/X86/simple-zext.ll b/test/CodeGen/X86/simple-zext.ll
new file mode 100644
index 0000000..ccd8292
--- /dev/null
+++ b/test/CodeGen/X86/simple-zext.ll
@@ -0,0 +1,16 @@
+; RUN: llc -mtriple=x86_64-apple-darwin < %s| FileCheck %s
+
+; A bug in DAGCombiner prevented it forming a zextload in this simple case
+; because it counted both the chain user and the real user against the
+; profitability total.
+
+define void @load_zext(i32* nocapture %p){
+entry:
+  %0 = load i32* %p, align 4
+  %and = and i32 %0, 255
+  tail call void @use(i32 %and)
+  ret void
+; CHECK: movzbl ({{%r[a-z]+}}), {{%e[a-z]+}}
+}
+
+declare void @use(i32)
diff --git a/test/CodeGen/X86/sincos-opt.ll b/test/CodeGen/X86/sincos-opt.ll
index f800c58..2dc8816 100644
--- a/test/CodeGen/X86/sincos-opt.ll
+++ b/test/CodeGen/X86/sincos-opt.ll
@@ -8,12 +8,12 @@
 
 define float @test1(float %x) nounwind {
 entry:
-; GNU_SINCOS: test1:
+; GNU_SINCOS-LABEL: test1:
 ; GNU_SINCOS: callq sincosf
 ; GNU_SINCOS: movss 4(%rsp), %xmm0
 ; GNU_SINCOS: addss (%rsp), %xmm0
 
-; OSX_SINCOS: test1:
+; OSX_SINCOS-LABEL: test1:
 ; OSX_SINCOS: callq ___sincosf_stret
 ; OSX_SINCOS: pshufd $1, %xmm0, %xmm1
 ; OSX_SINCOS: addss %xmm0, %xmm1
@@ -29,12 +29,12 @@ entry:
 
 define double @test2(double %x) nounwind {
 entry:
-; GNU_SINCOS: test2:
+; GNU_SINCOS-LABEL: test2:
 ; GNU_SINCOS: callq sincos
 ; GNU_SINCOS: movsd 16(%rsp), %xmm0
 ; GNU_SINCOS: addsd 8(%rsp), %xmm0
 
-; OSX_SINCOS: test2:
+; OSX_SINCOS-LABEL: test2:
 ; OSX_SINCOS: callq ___sincos_stret
 ; OSX_SINCOS: addsd %xmm1, %xmm0
 
@@ -49,7 +49,7 @@ entry:
 
 define x86_fp80 @test3(x86_fp80 %x) nounwind {
 entry:
-; GNU_SINCOS: test3:
+; GNU_SINCOS-LABEL: test3:
 ; GNU_SINCOS: callq sinl
 ; GNU_SINCOS: callq cosl
 ; GNU_SINCOS: ret
diff --git a/test/CodeGen/X86/sincos.ll b/test/CodeGen/X86/sincos.ll
index 734f48a..8f0e6f1 100644
--- a/test/CodeGen/X86/sincos.ll
+++ b/test/CodeGen/X86/sincos.ll
@@ -9,7 +9,7 @@ declare double @sin(double) readonly
 
 declare x86_fp80 @sinl(x86_fp80) readonly
 
-; SIN: test1:
+; SIN-LABEL: test1:
 define float @test1(float %X) {
         %Y = call float @sinf(float %X) readonly
         ret float %Y
@@ -21,7 +21,7 @@ define float @test1(float %X) {
 ; SAFE: test1
 ; SAFE-NOT: fsin
 
-; SIN: test2:
+; SIN-LABEL: test2:
 define double @test2(double %X) {
         %Y = call double @sin(double %X) readonly
         ret double %Y
@@ -33,7 +33,7 @@ define double @test2(double %X) {
 ; SAFE: test2
 ; SAFE-NOT: fsin
 
-; SIN: test3:
+; SIN-LABEL: test3:
 define x86_fp80 @test3(x86_fp80 %X) {
         %Y = call x86_fp80 @sinl(x86_fp80 %X) readonly
         ret x86_fp80 %Y
@@ -49,8 +49,8 @@ declare double @cos(double) readonly
 declare x86_fp80 @cosl(x86_fp80) readonly
 
 
-; SIN: test4:
-; COS: test3:
+; SIN-LABEL: test4:
+; COS-LABEL: test3:
 define float @test4(float %X) {
         %Y = call float @cosf(float %X) readonly
         ret float %Y
diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll
index 2aca5b8..0741635 100644
--- a/test/CodeGen/X86/sink-hoist.ll
+++ b/test/CodeGen/X86/sink-hoist.ll
@@ -5,7 +5,7 @@
 ; evaluated, however with MachineSink we can sink the other side so
 ; that it's conditionally evaluated.
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NEXT: testb $1, %dil
 ; CHECK-NEXT: jne
 ; CHECK-NEXT: divsd
@@ -24,7 +24,7 @@ define double @foo(double %x, double %y, i1 %c) nounwind {
 ; the conditional branch.
 ; rdar://8454886
 
-; CHECK: split:
+; CHECK-LABEL: split:
 ; CHECK-NEXT: testb $1, %dil
 ; CHECK-NEXT: jne
 ; CHECK-NEXT: movaps
@@ -40,7 +40,7 @@ define double @split(double %x, double %y, i1 %c) nounwind {
 
 ; Hoist floating-point constant-pool loads out of loops.
 
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: movsd
 ; CHECK: align
 define void @bar(double* nocapture %p, i64 %n) nounwind {
@@ -87,7 +87,7 @@ return:
 
 ; Codegen should hoist and CSE these constants.
 
-; CHECK: vv:
+; CHECK-LABEL: vv:
 ; CHECK: LCPI3_0(%rip), %xmm0
 ; CHECK: LCPI3_1(%rip), %xmm1
 ; CHECK: LCPI3_2(%rip), %xmm2
@@ -151,7 +151,7 @@ declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone
 ; CodeGen should use the correct register class when extracting
 ; a load from a zero-extending load for hoisting.
 
-; CHECK: default_get_pch_validity:
+; CHECK-LABEL: default_get_pch_validity:
 ; CHECK: movl cl_options_count(%rip), %ecx
 
 @cl_options_count = external constant i32         ; <i32*> [#uses=2]
diff --git a/test/CodeGen/X86/smul-with-overflow.ll b/test/CodeGen/X86/smul-with-overflow.ll
index 2d0b2f7..cefbda6 100644
--- a/test/CodeGen/X86/smul-with-overflow.ll
+++ b/test/CodeGen/X86/smul-with-overflow.ll
@@ -17,7 +17,7 @@ normal:
 overflow:
   %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: imull
 ; CHECK-NEXT: jno
 }
@@ -36,7 +36,7 @@ overflow:
 normal:
   %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
   ret i1 true
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: imull
 ; CHECK-NEXT: jno
 }
@@ -50,7 +50,7 @@ entry:
 	%tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 2)
 	%tmp2 = extractvalue { i32, i1 } %tmp1, 0
 	ret i32 %tmp2
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: addl
 ; CHECK-NEXT: addl
 ; CHECK-NEXT: ret
@@ -62,7 +62,7 @@ entry:
 	%tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 4)
 	%tmp2 = extractvalue { i32, i1 } %tmp1, 0
 	ret i32 %tmp2
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: addl
 ; CHECK: mull
 ; CHECK-NEXT: ret
@@ -78,6 +78,6 @@ entry:
   ret i1 %overflow
 ; Was returning false, should return true (not constant folded yet though).
 ; PR13991
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK-NOT: xorb
 }
diff --git a/test/CodeGen/X86/splat-scalar-load.ll b/test/CodeGen/X86/splat-scalar-load.ll
index 980f18c..4d59b9c 100644
--- a/test/CodeGen/X86/splat-scalar-load.ll
+++ b/test/CodeGen/X86/splat-scalar-load.ll
@@ -3,7 +3,7 @@
 
 define <2 x i64> @t2() nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: pshufd	$85, (%esp), %xmm0
   %array = alloca [8 x float], align 4
   %arrayidx = getelementptr inbounds [8 x float]* %array, i32 0, i32 1
diff --git a/test/CodeGen/X86/sse-align-12.ll b/test/CodeGen/X86/sse-align-12.ll
index 71a42f4..2351fd6 100644
--- a/test/CodeGen/X86/sse-align-12.ll
+++ b/test/CodeGen/X86/sse-align-12.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86-64 -mcpu=nehalem | FileCheck %s
 
-; CHECK: a:
+; CHECK-LABEL: a:
 ; CHECK: movdqu
 ; CHECK: pshufd
 define <4 x float> @a(<4 x float>* %y) nounwind {
@@ -16,7 +16,7 @@ define <4 x float> @a(<4 x float>* %y) nounwind {
   ret <4 x float> %s
 }
 
-; CHECK: b:
+; CHECK-LABEL: b:
 ; CHECK: movups
 ; CHECK: unpckhps
 define <4 x float> @b(<4 x float>* %y, <4 x float> %z) nounwind {
@@ -32,7 +32,7 @@ define <4 x float> @b(<4 x float>* %y, <4 x float> %z) nounwind {
   ret <4 x float> %s
 }
 
-; CHECK: c:
+; CHECK-LABEL: c:
 ; CHECK: movupd
 ; CHECK: shufpd
 define <2 x double> @c(<2 x double>* %y) nounwind {
@@ -44,7 +44,7 @@ define <2 x double> @c(<2 x double>* %y) nounwind {
   ret <2 x double> %r
 }
 
-; CHECK: d:
+; CHECK-LABEL: d:
 ; CHECK: movupd
 ; CHECK: unpckhpd
 define <2 x double> @d(<2 x double>* %y, <2 x double> %z) nounwind {
diff --git a/test/CodeGen/X86/sse-align-2.ll b/test/CodeGen/X86/sse-align-2.ll
index 22cd772..98e75b5 100644
--- a/test/CodeGen/X86/sse-align-2.ll
+++ b/test/CodeGen/X86/sse-align-2.ll
@@ -6,7 +6,7 @@ define <4 x float> @foo(<4 x float>* %p, <4 x float> %x) nounwind {
   ret <4 x float> %z
 }
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: movups
 ; CHECK: ret
 
@@ -16,6 +16,6 @@ define <2 x double> @bar(<2 x double>* %p, <2 x double> %x) nounwind {
   ret <2 x double> %z
 }
 
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: movupd
 ; CHECK: ret
diff --git a/test/CodeGen/X86/sse-commute.ll b/test/CodeGen/X86/sse-commute.ll
index 336bf06..1800a6e 100644
--- a/test/CodeGen/X86/sse-commute.ll
+++ b/test/CodeGen/X86/sse-commute.ll
@@ -3,7 +3,7 @@
 ; Commute the comparison to avoid a move.
 ; PR7500.
 
-; CHECK: a:
+; CHECK-LABEL: a:
 ; CHECK-NOT: mov
 ; CHECK:     pcmpeqd
 define <2 x double> @a(<2 x double>, <2 x double>) nounwind readnone {
diff --git a/test/CodeGen/X86/sse-minmax.ll b/test/CodeGen/X86/sse-minmax.ll
index 0ba0215..5122c44 100644
--- a/test/CodeGen/X86/sse-minmax.ll
+++ b/test/CodeGen/X86/sse-minmax.ll
@@ -12,13 +12,13 @@
 ;  _y: use -0.0 instead of %y
 ; _inverse : swap the arms of the select.
 
-; CHECK:      ogt:
+; CHECK-LABEL:      ogt:
 ; CHECK-NEXT: maxsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ogt:
+; UNSAFE-LABEL:      ogt:
 ; UNSAFE-NEXT: maxsd %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ogt:
+; FINITE-LABEL:      ogt:
 ; FINITE-NEXT: maxsd %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @ogt(double %x, double %y) nounwind {
@@ -27,13 +27,13 @@ define double @ogt(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      olt:
+; CHECK-LABEL:      olt:
 ; CHECK-NEXT: minsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      olt:
+; UNSAFE-LABEL:      olt:
 ; UNSAFE-NEXT: minsd %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      olt:
+; FINITE-LABEL:      olt:
 ; FINITE-NEXT: minsd %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @olt(double %x, double %y) nounwind {
@@ -42,14 +42,14 @@ define double @olt(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ogt_inverse:
+; CHECK-LABEL:      ogt_inverse:
 ; CHECK-NEXT: minsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ogt_inverse:
+; UNSAFE-LABEL:      ogt_inverse:
 ; UNSAFE-NEXT: minsd  %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ogt_inverse:
+; FINITE-LABEL:      ogt_inverse:
 ; FINITE-NEXT: minsd  %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -59,14 +59,14 @@ define double @ogt_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      olt_inverse:
+; CHECK-LABEL:      olt_inverse:
 ; CHECK-NEXT: maxsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      olt_inverse:
+; UNSAFE-LABEL:      olt_inverse:
 ; UNSAFE-NEXT: maxsd  %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      olt_inverse:
+; FINITE-LABEL:      olt_inverse:
 ; FINITE-NEXT: maxsd  %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -76,12 +76,12 @@ define double @olt_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      oge:
-; CHECK-NEXT: ucomisd %xmm1, %xmm0
-; UNSAFE:      oge:
+; CHECK-LABEL:      oge:
+; CHECK: cmplesd %xmm0
+; UNSAFE-LABEL:      oge:
 ; UNSAFE-NEXT: maxsd	%xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      oge:
+; FINITE-LABEL:      oge:
 ; FINITE-NEXT: maxsd	%xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @oge(double %x, double %y) nounwind {
@@ -90,11 +90,11 @@ define double @oge(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ole:
-; CHECK-NEXT: ucomisd %xmm0, %xmm1
-; UNSAFE:      ole:
+; CHECK-LABEL:      ole:
+; CHECK: cmplesd %xmm1
+; UNSAFE-LABEL:      ole:
 ; UNSAFE-NEXT: minsd %xmm1, %xmm0
-; FINITE:      ole:
+; FINITE-LABEL:      ole:
 ; FINITE-NEXT: minsd %xmm1, %xmm0
 define double @ole(double %x, double %y) nounwind {
   %c = fcmp ole double %x, %y
@@ -102,12 +102,12 @@ define double @ole(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      oge_inverse:
-; CHECK-NEXT: ucomisd %xmm1, %xmm0
-; UNSAFE:      oge_inverse:
+; CHECK-LABEL:      oge_inverse:
+; CHECK: cmplesd %xmm0
+; UNSAFE-LABEL:      oge_inverse:
 ; UNSAFE-NEXT: minsd %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      oge_inverse:
+; FINITE-LABEL:      oge_inverse:
 ; FINITE-NEXT: minsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -117,12 +117,12 @@ define double @oge_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ole_inverse:
-; CHECK-NEXT: ucomisd %xmm0, %xmm1
-; UNSAFE:      ole_inverse:
+; CHECK-LABEL:      ole_inverse:
+; CHECK: cmplesd %xmm1
+; UNSAFE-LABEL:      ole_inverse:
 ; UNSAFE-NEXT: maxsd %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ole_inverse:
+; FINITE-LABEL:      ole_inverse:
 ; FINITE-NEXT: maxsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -132,16 +132,16 @@ define double @ole_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ogt_x:
+; CHECK-LABEL:      ogt_x:
 ; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; CHECK-NEXT: maxsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ogt_x:
+; UNSAFE-LABEL:      ogt_x:
 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ogt_x:
+; FINITE-LABEL:      ogt_x:
 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; FINITE-NEXT: maxsd %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -151,16 +151,16 @@ define double @ogt_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      olt_x:
+; CHECK-LABEL:      olt_x:
 ; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; CHECK-NEXT: minsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      olt_x:
+; UNSAFE-LABEL:      olt_x:
 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      olt_x:
+; FINITE-LABEL:      olt_x:
 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; FINITE-NEXT: minsd %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -170,17 +170,17 @@ define double @olt_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ogt_inverse_x:
+; CHECK-LABEL:      ogt_inverse_x:
 ; CHECK-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; CHECK-NEXT: minsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ogt_inverse_x:
+; UNSAFE-LABEL:      ogt_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd  %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ogt_inverse_x:
+; FINITE-LABEL:      ogt_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; FINITE-NEXT: minsd  %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -191,17 +191,17 @@ define double @ogt_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      olt_inverse_x:
+; CHECK-LABEL:      olt_inverse_x:
 ; CHECK-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; CHECK-NEXT: maxsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      olt_inverse_x:
+; UNSAFE-LABEL:      olt_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd  %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      olt_inverse_x:
+; FINITE-LABEL:      olt_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; FINITE-NEXT: maxsd  %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -212,14 +212,15 @@ define double @olt_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      oge_x:
-; CHECK:      ucomisd %xmm1, %xmm0
-; UNSAFE:      oge_x:
+; CHECK-LABEL:      oge_x:
+; CHECK:      cmplesd %xmm
+; CHECK-NEXT: andpd
+; UNSAFE-LABEL:      oge_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd   %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      oge_x:
+; FINITE-LABEL:      oge_x:
 ; FINITE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; FINITE-NEXT: maxsd   %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -229,14 +230,15 @@ define double @oge_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ole_x:
-; CHECK:      ucomisd %xmm0, %xmm1
-; UNSAFE:      ole_x:
+; CHECK-LABEL:      ole_x:
+; CHECK:      cmplesd %xmm
+; CHECK-NEXT: andpd
+; UNSAFE-LABEL:      ole_x:
 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ole_x:
+; FINITE-LABEL:      ole_x:
 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; FINITE-NEXT: minsd %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -246,14 +248,15 @@ define double @ole_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      oge_inverse_x:
-; CHECK:      ucomisd %xmm
-; UNSAFE:      oge_inverse_x:
+; CHECK-LABEL:      oge_inverse_x:
+; CHECK:      cmplesd %xmm
+; CHECK-NEXT: andnpd
+; UNSAFE-LABEL:      oge_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd   %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      oge_inverse_x:
+; FINITE-LABEL:      oge_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; FINITE-NEXT: minsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -264,14 +267,14 @@ define double @oge_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ole_inverse_x:
-; CHECK:      ucomisd %xmm
-; UNSAFE:      ole_inverse_x:
+; CHECK-LABEL:      ole_inverse_x:
+; CHECK:      cmplesd %xmm
+; UNSAFE-LABEL:      ole_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd   %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ole_inverse_x:
+; FINITE-LABEL:      ole_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; FINITE-NEXT: maxsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -282,12 +285,12 @@ define double @ole_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ugt:
-; CHECK:      ucomisd %xmm0, %xmm1
-; UNSAFE:      ugt:
+; CHECK-LABEL:      ugt:
+; CHECK:      cmpnlesd %xmm1
+; UNSAFE-LABEL:      ugt:
 ; UNSAFE-NEXT: maxsd   %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ugt:
+; FINITE-LABEL:      ugt:
 ; FINITE-NEXT: maxsd   %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @ugt(double %x, double %y) nounwind {
@@ -296,12 +299,12 @@ define double @ugt(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ult:
-; CHECK:      ucomisd %xmm1, %xmm0
-; UNSAFE:      ult:
+; CHECK-LABEL:      ult:
+; CHECK:      cmpnlesd %xmm0
+; UNSAFE-LABEL:      ult:
 ; UNSAFE-NEXT: minsd   %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ult:
+; FINITE-LABEL:      ult:
 ; FINITE-NEXT: minsd   %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @ult(double %x, double %y) nounwind {
@@ -310,12 +313,12 @@ define double @ult(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ugt_inverse:
-; CHECK:      ucomisd %xmm0, %xmm1
-; UNSAFE:      ugt_inverse:
+; CHECK-LABEL:      ugt_inverse:
+; CHECK:      cmpnlesd %xmm1
+; UNSAFE-LABEL:      ugt_inverse:
 ; UNSAFE-NEXT: minsd   %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ugt_inverse:
+; FINITE-LABEL:      ugt_inverse:
 ; FINITE-NEXT: minsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -325,12 +328,12 @@ define double @ugt_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ult_inverse:
-; CHECK:      ucomisd %xmm1, %xmm0
-; UNSAFE:      ult_inverse:
+; CHECK-LABEL:      ult_inverse:
+; CHECK:      cmpnlesd %xmm0
+; UNSAFE-LABEL:      ult_inverse:
 ; UNSAFE-NEXT: maxsd   %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ult_inverse:
+; FINITE-LABEL:      ult_inverse:
 ; FINITE-NEXT: maxsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -340,14 +343,14 @@ define double @ult_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      uge:
+; CHECK-LABEL:      uge:
 ; CHECK-NEXT: maxsd   %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      uge:
+; UNSAFE-LABEL:      uge:
 ; UNSAFE-NEXT: maxsd   %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      uge:
+; FINITE-LABEL:      uge:
 ; FINITE-NEXT: maxsd   %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @uge(double %x, double %y) nounwind {
@@ -356,14 +359,14 @@ define double @uge(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ule:
+; CHECK-LABEL:      ule:
 ; CHECK-NEXT: minsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ule:
+; UNSAFE-LABEL:      ule:
 ; UNSAFE-NEXT: minsd   %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ule:
+; FINITE-LABEL:      ule:
 ; FINITE-NEXT: minsd   %xmm1, %xmm0
 ; FINITE-NEXT: ret
 define double @ule(double %x, double %y) nounwind {
@@ -372,13 +375,13 @@ define double @ule(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      uge_inverse:
+; CHECK-LABEL:      uge_inverse:
 ; CHECK-NEXT: minsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      uge_inverse:
+; UNSAFE-LABEL:      uge_inverse:
 ; UNSAFE-NEXT: minsd %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      uge_inverse:
+; FINITE-LABEL:      uge_inverse:
 ; FINITE-NEXT: minsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -388,13 +391,13 @@ define double @uge_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ule_inverse:
+; CHECK-LABEL:      ule_inverse:
 ; CHECK-NEXT: maxsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ule_inverse:
+; UNSAFE-LABEL:      ule_inverse:
 ; UNSAFE-NEXT: maxsd %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ule_inverse:
+; FINITE-LABEL:      ule_inverse:
 ; FINITE-NEXT: maxsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -404,14 +407,15 @@ define double @ule_inverse(double %x, double %y) nounwind {
   ret double %d
 }
 
-; CHECK:      ugt_x:
-; CHECK:      ucomisd %xmm0, %xmm1
-; UNSAFE:      ugt_x:
+; CHECK-LABEL:      ugt_x:
+; CHECK:      cmpnlesd %xmm
+; CHECK-NEXT: andpd
+; UNSAFE-LABEL:      ugt_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd   %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ugt_x:
+; FINITE-LABEL:      ugt_x:
 ; FINITE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; FINITE-NEXT: maxsd   %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -421,14 +425,15 @@ define double @ugt_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ult_x:
-; CHECK:      ucomisd %xmm1, %xmm0
-; UNSAFE:      ult_x:
+; CHECK-LABEL:      ult_x:
+; CHECK:      cmpnlesd %xmm
+; CHECK-NEXT: andpd
+; UNSAFE-LABEL:      ult_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd   %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ult_x:
+; FINITE-LABEL:      ult_x:
 ; FINITE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; FINITE-NEXT: minsd   %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -438,14 +443,15 @@ define double @ult_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ugt_inverse_x:
-; CHECK:      ucomisd %xmm
-; UNSAFE:      ugt_inverse_x:
+; CHECK-LABEL:      ugt_inverse_x:
+; CHECK:      cmpnlesd %xmm
+; CHECK-NEXT: andnpd
+; UNSAFE-LABEL:      ugt_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd   %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ugt_inverse_x:
+; FINITE-LABEL:      ugt_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; FINITE-NEXT: minsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -456,14 +462,15 @@ define double @ugt_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ult_inverse_x:
-; CHECK:      ucomisd %xmm
-; UNSAFE:      ult_inverse_x:
+; CHECK-LABEL:      ult_inverse_x:
+; CHECK:      cmpnlesd %xmm
+; CHECK-NEXT: andnpd
+; UNSAFE-LABEL:      ult_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd   %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ult_inverse_x:
+; FINITE-LABEL:      ult_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}}   %xmm1, %xmm1
 ; FINITE-NEXT: maxsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -474,17 +481,17 @@ define double @ult_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      uge_x:
+; CHECK-LABEL:      uge_x:
 ; CHECK-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; CHECK-NEXT: maxsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      uge_x:
+; UNSAFE-LABEL:      uge_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd  %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      uge_x:
+; FINITE-LABEL:      uge_x:
 ; FINITE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; FINITE-NEXT: maxsd  %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -494,17 +501,17 @@ define double @uge_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ule_x:
+; CHECK-LABEL:      ule_x:
 ; CHECK-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; CHECK-NEXT: minsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ule_x:
+; UNSAFE-LABEL:      ule_x:
 ; UNSAFE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd  %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ule_x:
+; FINITE-LABEL:      ule_x:
 ; FINITE-NEXT: xorp{{[sd]}}  %xmm1, %xmm1
 ; FINITE-NEXT: minsd  %xmm1, %xmm0
 ; FINITE-NEXT: ret
@@ -514,16 +521,16 @@ define double @ule_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      uge_inverse_x:
+; CHECK-LABEL:      uge_inverse_x:
 ; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; CHECK-NEXT: minsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      uge_inverse_x:
+; UNSAFE-LABEL:      uge_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; UNSAFE-NEXT: minsd %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      uge_inverse_x:
+; FINITE-LABEL:      uge_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; FINITE-NEXT: minsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -534,16 +541,16 @@ define double @uge_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ule_inverse_x:
+; CHECK-LABEL:      ule_inverse_x:
 ; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; CHECK-NEXT: maxsd %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ule_inverse_x:
+; UNSAFE-LABEL:      ule_inverse_x:
 ; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; UNSAFE-NEXT: maxsd %xmm0, %xmm1
 ; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ule_inverse_x:
+; FINITE-LABEL:      ule_inverse_x:
 ; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
 ; FINITE-NEXT: maxsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -554,13 +561,13 @@ define double @ule_inverse_x(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ogt_y:
+; CHECK-LABEL:      ogt_y:
 ; CHECK-NEXT: maxsd {{[^,]*}}, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ogt_y:
+; UNSAFE-LABEL:      ogt_y:
 ; UNSAFE-NEXT: maxsd {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ogt_y:
+; FINITE-LABEL:      ogt_y:
 ; FINITE-NEXT: maxsd {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @ogt_y(double %x) nounwind {
@@ -569,13 +576,13 @@ define double @ogt_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      olt_y:
+; CHECK-LABEL:      olt_y:
 ; CHECK-NEXT: minsd {{[^,]*}}, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      olt_y:
+; UNSAFE-LABEL:      olt_y:
 ; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      olt_y:
+; FINITE-LABEL:      olt_y:
 ; FINITE-NEXT: minsd {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @olt_y(double %x) nounwind {
@@ -584,15 +591,15 @@ define double @olt_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ogt_inverse_y:
+; CHECK-LABEL:      ogt_inverse_y:
 ; CHECK-NEXT: movsd  {{[^,]*}}, %xmm1
 ; CHECK-NEXT: minsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ogt_inverse_y:
+; UNSAFE-LABEL:      ogt_inverse_y:
 ; UNSAFE-NEXT: minsd  {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ogt_inverse_y:
+; FINITE-LABEL:      ogt_inverse_y:
 ; FINITE-NEXT: movsd  {{[^,]*}}, %xmm1
 ; FINITE-NEXT: minsd  %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -603,15 +610,15 @@ define double @ogt_inverse_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      olt_inverse_y:
+; CHECK-LABEL:      olt_inverse_y:
 ; CHECK-NEXT: movsd  {{[^,]*}}, %xmm1
 ; CHECK-NEXT: maxsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      olt_inverse_y:
+; UNSAFE-LABEL:      olt_inverse_y:
 ; UNSAFE-NEXT: maxsd  {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      olt_inverse_y:
+; FINITE-LABEL:      olt_inverse_y:
 ; FINITE-NEXT: movsd  {{[^,]*}}, %xmm1
 ; FINITE-NEXT: maxsd  %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -622,12 +629,12 @@ define double @olt_inverse_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      oge_y:
-; CHECK:      ucomisd %xmm1, %xmm0
-; UNSAFE:      oge_y:
+; CHECK-LABEL:      oge_y:
+; CHECK:      cmplesd %xmm0
+; UNSAFE-LABEL:      oge_y:
 ; UNSAFE-NEXT: maxsd   {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      oge_y:
+; FINITE-LABEL:      oge_y:
 ; FINITE-NEXT: maxsd   {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @oge_y(double %x) nounwind {
@@ -636,12 +643,12 @@ define double @oge_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ole_y:
-; CHECK:      ucomisd %xmm0, %xmm1
-; UNSAFE:      ole_y:
+; CHECK-LABEL:      ole_y:
+; CHECK:      cmplesd %xmm
+; UNSAFE-LABEL:      ole_y:
 ; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ole_y:
+; FINITE-LABEL:      ole_y:
 ; FINITE-NEXT: minsd {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @ole_y(double %x) nounwind {
@@ -650,12 +657,12 @@ define double @ole_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      oge_inverse_y:
-; CHECK:      ucomisd %xmm
-; UNSAFE:      oge_inverse_y:
+; CHECK-LABEL:      oge_inverse_y:
+; CHECK:      cmplesd %xmm0
+; UNSAFE-LABEL:      oge_inverse_y:
 ; UNSAFE-NEXT: minsd   {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      oge_inverse_y:
+; FINITE-LABEL:      oge_inverse_y:
 ; FINITE-NEXT: movsd   {{[^,]*}}, %xmm1
 ; FINITE-NEXT: minsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -666,12 +673,12 @@ define double @oge_inverse_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ole_inverse_y:
-; CHECK:      ucomisd %xmm
-; UNSAFE:      ole_inverse_y:
+; CHECK-LABEL:      ole_inverse_y:
+; CHECK:      cmplesd %xmm
+; UNSAFE-LABEL:      ole_inverse_y:
 ; UNSAFE-NEXT: maxsd   {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ole_inverse_y:
+; FINITE-LABEL:      ole_inverse_y:
 ; FINITE-NEXT: movsd   {{[^,]*}}, %xmm1
 ; FINITE-NEXT: maxsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -682,12 +689,12 @@ define double @ole_inverse_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ugt_y:
-; CHECK:      ucomisd %xmm0, %xmm1
-; UNSAFE:      ugt_y:
+; CHECK-LABEL:      ugt_y:
+; CHECK:      cmpnlesd %xmm
+; UNSAFE-LABEL:      ugt_y:
 ; UNSAFE-NEXT: maxsd   {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ugt_y:
+; FINITE-LABEL:      ugt_y:
 ; FINITE-NEXT: maxsd   {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @ugt_y(double %x) nounwind {
@@ -696,12 +703,12 @@ define double @ugt_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ult_y:
-; CHECK:      ucomisd %xmm1, %xmm0
-; UNSAFE:      ult_y:
+; CHECK-LABEL:      ult_y:
+; CHECK:      cmpnlesd %xmm0
+; UNSAFE-LABEL:      ult_y:
 ; UNSAFE-NEXT: minsd   {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ult_y:
+; FINITE-LABEL:      ult_y:
 ; FINITE-NEXT: minsd   {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @ult_y(double %x) nounwind {
@@ -710,12 +717,12 @@ define double @ult_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ugt_inverse_y:
-; CHECK:      ucomisd %xmm
-; UNSAFE:      ugt_inverse_y:
+; CHECK-LABEL:      ugt_inverse_y:
+; CHECK:      cmpnlesd %xmm
+; UNSAFE-LABEL:      ugt_inverse_y:
 ; UNSAFE-NEXT: minsd   {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ugt_inverse_y:
+; FINITE-LABEL:      ugt_inverse_y:
 ; FINITE-NEXT: movsd   {{[^,]*}}, %xmm1
 ; FINITE-NEXT: minsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -726,12 +733,12 @@ define double @ugt_inverse_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ult_inverse_y:
-; CHECK:      ucomisd %xmm
-; UNSAFE:      ult_inverse_y:
+; CHECK-LABEL:      ult_inverse_y:
+; CHECK:      cmpnlesd %xmm
+; UNSAFE-LABEL:      ult_inverse_y:
 ; UNSAFE-NEXT: maxsd   {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ult_inverse_y:
+; FINITE-LABEL:      ult_inverse_y:
 ; FINITE-NEXT: movsd   {{[^,]*}}, %xmm1
 ; FINITE-NEXT: maxsd   %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}}  %xmm1, %xmm0
@@ -742,15 +749,15 @@ define double @ult_inverse_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      uge_y:
+; CHECK-LABEL:      uge_y:
 ; CHECK-NEXT: movsd  {{[^,]*}}, %xmm1
 ; CHECK-NEXT: maxsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      uge_y:
+; UNSAFE-LABEL:      uge_y:
 ; UNSAFE-NEXT: maxsd  {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      uge_y:
+; FINITE-LABEL:      uge_y:
 ; FINITE-NEXT: maxsd  {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @uge_y(double %x) nounwind {
@@ -759,15 +766,15 @@ define double @uge_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ule_y:
+; CHECK-LABEL:      ule_y:
 ; CHECK-NEXT: movsd  {{[^,]*}}, %xmm1
 ; CHECK-NEXT: minsd  %xmm0, %xmm1
 ; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ule_y:
+; UNSAFE-LABEL:      ule_y:
 ; UNSAFE-NEXT: minsd  {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ule_y:
+; FINITE-LABEL:      ule_y:
 ; FINITE-NEXT: minsd  {{[^,]*}}, %xmm0
 ; FINITE-NEXT: ret
 define double @ule_y(double %x) nounwind {
@@ -776,13 +783,13 @@ define double @ule_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      uge_inverse_y:
+; CHECK-LABEL:      uge_inverse_y:
 ; CHECK-NEXT: minsd {{[^,]*}}, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      uge_inverse_y:
+; UNSAFE-LABEL:      uge_inverse_y:
 ; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      uge_inverse_y:
+; FINITE-LABEL:      uge_inverse_y:
 ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
 ; FINITE-NEXT: minsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -793,13 +800,13 @@ define double @uge_inverse_y(double %x) nounwind {
   ret double %d
 }
 
-; CHECK:      ule_inverse_y:
+; CHECK-LABEL:      ule_inverse_y:
 ; CHECK-NEXT: maxsd {{[^,]*}}, %xmm0
 ; CHECK-NEXT: ret
-; UNSAFE:      ule_inverse_y:
+; UNSAFE-LABEL:      ule_inverse_y:
 ; UNSAFE-NEXT: maxsd {{[^,]*}}, %xmm0
 ; UNSAFE-NEXT: ret
-; FINITE:      ule_inverse_y:
+; FINITE-LABEL:      ule_inverse_y:
 ; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
 ; FINITE-NEXT: maxsd %xmm0, %xmm1
 ; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
@@ -811,11 +818,11 @@ define double @ule_inverse_y(double %x) nounwind {
 }
 ; Test a few more misc. cases.
 
-; CHECK: clampTo3k_a:
+; CHECK-LABEL: clampTo3k_a:
 ; CHECK: minsd
-; UNSAFE: clampTo3k_a:
+; UNSAFE-LABEL: clampTo3k_a:
 ; UNSAFE: minsd
-; FINITE: clampTo3k_a:
+; FINITE-LABEL: clampTo3k_a:
 ; FINITE: minsd
 define double @clampTo3k_a(double %x) nounwind readnone {
 entry:
@@ -824,11 +831,11 @@ entry:
   ret double %x_addr.0
 }
 
-; CHECK: clampTo3k_b:
+; CHECK-LABEL: clampTo3k_b:
 ; CHECK: minsd
-; UNSAFE: clampTo3k_b:
+; UNSAFE-LABEL: clampTo3k_b:
 ; UNSAFE: minsd
-; FINITE: clampTo3k_b:
+; FINITE-LABEL: clampTo3k_b:
 ; FINITE: minsd
 define double @clampTo3k_b(double %x) nounwind readnone {
 entry:
@@ -837,11 +844,11 @@ entry:
   ret double %x_addr.0
 }
 
-; CHECK: clampTo3k_c:
+; CHECK-LABEL: clampTo3k_c:
 ; CHECK: maxsd
-; UNSAFE: clampTo3k_c:
+; UNSAFE-LABEL: clampTo3k_c:
 ; UNSAFE: maxsd
-; FINITE: clampTo3k_c:
+; FINITE-LABEL: clampTo3k_c:
 ; FINITE: maxsd
 define double @clampTo3k_c(double %x) nounwind readnone {
 entry:
@@ -850,11 +857,11 @@ entry:
   ret double %x_addr.0
 }
 
-; CHECK: clampTo3k_d:
+; CHECK-LABEL: clampTo3k_d:
 ; CHECK: maxsd
-; UNSAFE: clampTo3k_d:
+; UNSAFE-LABEL: clampTo3k_d:
 ; UNSAFE: maxsd
-; FINITE: clampTo3k_d:
+; FINITE-LABEL: clampTo3k_d:
 ; FINITE: maxsd
 define double @clampTo3k_d(double %x) nounwind readnone {
 entry:
@@ -863,11 +870,11 @@ entry:
   ret double %x_addr.0
 }
 
-; CHECK: clampTo3k_e:
+; CHECK-LABEL: clampTo3k_e:
 ; CHECK: maxsd
-; UNSAFE: clampTo3k_e:
+; UNSAFE-LABEL: clampTo3k_e:
 ; UNSAFE: maxsd
-; FINITE: clampTo3k_e:
+; FINITE-LABEL: clampTo3k_e:
 ; FINITE: maxsd
 define double @clampTo3k_e(double %x) nounwind readnone {
 entry:
@@ -876,11 +883,11 @@ entry:
   ret double %x_addr.0
 }
 
-; CHECK: clampTo3k_f:
+; CHECK-LABEL: clampTo3k_f:
 ; CHECK: maxsd
-; UNSAFE: clampTo3k_f:
+; UNSAFE-LABEL: clampTo3k_f:
 ; UNSAFE: maxsd
-; FINITE: clampTo3k_f:
+; FINITE-LABEL: clampTo3k_f:
 ; FINITE: maxsd
 define double @clampTo3k_f(double %x) nounwind readnone {
 entry:
@@ -889,11 +896,11 @@ entry:
   ret double %x_addr.0
 }
 
-; CHECK: clampTo3k_g:
+; CHECK-LABEL: clampTo3k_g:
 ; CHECK: minsd
-; UNSAFE: clampTo3k_g:
+; UNSAFE-LABEL: clampTo3k_g:
 ; UNSAFE: minsd
-; FINITE: clampTo3k_g:
+; FINITE-LABEL: clampTo3k_g:
 ; FINITE: minsd
 define double @clampTo3k_g(double %x) nounwind readnone {
 entry:
@@ -902,11 +909,11 @@ entry:
   ret double %x_addr.0
 }
 
-; CHECK: clampTo3k_h:
+; CHECK-LABEL: clampTo3k_h:
 ; CHECK: minsd
-; UNSAFE: clampTo3k_h:
+; UNSAFE-LABEL: clampTo3k_h:
 ; UNSAFE: minsd
-; FINITE: clampTo3k_h:
+; FINITE-LABEL: clampTo3k_h:
 ; FINITE: minsd
 define double @clampTo3k_h(double %x) nounwind readnone {
 entry:
@@ -915,33 +922,33 @@ entry:
   ret double %x_addr.0
 }
 
-; UNSAFE: maxpd:
+; UNSAFE-LABEL: test_maxpd:
 ; UNSAFE: maxpd
-define <2 x double> @maxpd(<2 x double> %x, <2 x double> %y) {
+define <2 x double> @test_maxpd(<2 x double> %x, <2 x double> %y) {
   %max_is_x = fcmp oge <2 x double> %x, %y
   %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
   ret <2 x double> %max
 }
 
-; UNSAFE: minpd:
+; UNSAFE-LABEL: test_minpd:
 ; UNSAFE: minpd
-define <2 x double> @minpd(<2 x double> %x, <2 x double> %y) {
+define <2 x double> @test_minpd(<2 x double> %x, <2 x double> %y) {
   %min_is_x = fcmp ole <2 x double> %x, %y
   %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
   ret <2 x double> %min
 }
 
-; UNSAFE: maxps:
+; UNSAFE-LABEL: test_maxps:
 ; UNSAFE: maxps
-define <4 x float> @maxps(<4 x float> %x, <4 x float> %y) {
+define <4 x float> @test_maxps(<4 x float> %x, <4 x float> %y) {
   %max_is_x = fcmp oge <4 x float> %x, %y
   %max = select <4 x i1> %max_is_x, <4 x float> %x, <4 x float> %y
   ret <4 x float> %max
 }
 
-; UNSAFE: minps:
+; UNSAFE-LABEL: test_minps:
 ; UNSAFE: minps
-define <4 x float> @minps(<4 x float> %x, <4 x float> %y) {
+define <4 x float> @test_minps(<4 x float> %x, <4 x float> %y) {
   %min_is_x = fcmp ole <4 x float> %x, %y
   %min = select <4 x i1> %min_is_x, <4 x float> %x, <4 x float> %y
   ret <4 x float> %min
diff --git a/test/CodeGen/X86/sse1.ll b/test/CodeGen/X86/sse1.ll
index 9b2e05b..47c6429 100644
--- a/test/CodeGen/X86/sse1.ll
+++ b/test/CodeGen/X86/sse1.ll
@@ -33,7 +33,7 @@ entry:
   %tmp11 = insertelement <2 x float> undef, float %add.r, i32 0
   %tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1
   ret <2 x float> %tmp9
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK-NOT: shufps	$16
 ; CHECK: shufps	$1, 
 ; CHECK-NOT: shufps	$16
diff --git a/test/CodeGen/X86/sse2-mul.ll b/test/CodeGen/X86/sse2-mul.ll
index 0466d60..e066368 100644
--- a/test/CodeGen/X86/sse2-mul.ll
+++ b/test/CodeGen/X86/sse2-mul.ll
@@ -3,7 +3,7 @@
 define <4 x i32> @test1(<4 x i32> %x, <4 x i32> %y) {
   %m = mul <4 x i32> %x, %y
   ret <4 x i32> %m
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: pshufd $49
 ; CHECK: pmuludq
 ; CHECK: pshufd $49
diff --git a/test/CodeGen/X86/sse2-vector-shifts.ll b/test/CodeGen/X86/sse2-vector-shifts.ll
new file mode 100644
index 0000000..e2d6125
--- /dev/null
+++ b/test/CodeGen/X86/sse2-vector-shifts.ll
@@ -0,0 +1,247 @@
+; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse2 -mcpu=corei7 | FileCheck %s
+
+; SSE2 Logical Shift Left
+
+define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
+entry:
+  %shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+  ret <8 x i16> %shl
+}
+
+; CHECK-LABEL: test_sllw_1:
+; CHECK: psllw   $0, %xmm0
+; CHECK-NEXT: ret
+
+define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
+entry:
+  %shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %shl
+}
+
+; CHECK-LABEL: test_sllw_2:
+; CHECK: paddw   %xmm0, %xmm0
+; CHECK-NEXT: ret
+
+define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
+entry:
+  %shl = shl <8 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
+  ret <8 x i16> %shl
+}
+
+; CHECK-LABEL: test_sllw_3:
+; CHECK: xorps   %xmm0, %xmm0
+; CHECK-NEXT: ret
+
+define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
+entry:
+  %shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
+  ret <4 x i32> %shl
+}
+
+; CHECK-LABEL: test_slld_1:
+; CHECK: pslld   $0, %xmm0
+; CHECK-NEXT: ret
+
+define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
+entry:
+  %shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %shl
+}
+
+; CHECK-LABEL: test_slld_2:
+; CHECK: paddd   %xmm0, %xmm0
+; CHECK-NEXT: ret
+
+define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
+entry:
+  %shl = shl <4 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32>
+  ret <4 x i32> %shl
+}
+
+; CHECK-LABEL: test_slld_3:
+; CHECK: xorps   %xmm0, %xmm0
+; CHECK-NEXT: ret
+
+define <2 x i64> @test_sllq_1(<2 x i64> %InVec) {
+entry:
+  %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
+  ret <2 x i64> %shl
+}
+
+; CHECK-LABEL: test_sllq_1:
+; CHECK: psllq   $0, %xmm0
+; CHECK-NEXT: ret
+
+define <2 x i64> @test_sllq_2(<2 x i64> %InVec) {
+entry:
+  %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
+  ret <2 x i64> %shl
+}
+
+; CHECK-LABEL: test_sllq_2:
+; CHECK: paddq   %xmm0, %xmm0
+; CHECK-NEXT: ret
+
+define <2 x i64> @test_sllq_3(<2 x i64> %InVec) {
+entry:
+  %shl = shl <2 x i64> %InVec, <i64 64, i64 64>
+  ret <2 x i64> %shl
+}
+
+; CHECK-LABEL: test_sllq_3:
+; CHECK: xorps   %xmm0, %xmm0
+; CHECK-NEXT: ret
+
+; SSE2 Arithmetic Shift
+
+define <8 x i16> @test_sraw_1(<8 x i16> %InVec) {
+entry:
+  %shl = ashr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+  ret <8 x i16> %shl
+}
+
+; CHECK-LABEL: test_sraw_1:
+; CHECK: psraw   $0, %xmm0
+; CHECK-NEXT: ret
+
+define <8 x i16> @test_sraw_2(<8 x i16> %InVec) {
+entry:
+  %shl = ashr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %shl
+}
+
+; CHECK-LABEL: test_sraw_2:
+; CHECK: psraw   $1, %xmm0
+; CHECK-NEXT: ret
+
+define <8 x i16> @test_sraw_3(<8 x i16> %InVec) {
+entry:
+  %shl = ashr <8 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
+  ret <8 x i16> %shl
+}
+
+; CHECK-LABEL: test_sraw_3:
+; CHECK: psraw   $16, %xmm0
+; CHECK-NEXT: ret
+
+define <4 x i32> @test_srad_1(<4 x i32> %InVec) {
+entry:
+  %shl = ashr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
+  ret <4 x i32> %shl
+}
+
+; CHECK-LABEL: test_srad_1:
+; CHECK: psrad   $0, %xmm0
+; CHECK-NEXT: ret
+
+define <4 x i32> @test_srad_2(<4 x i32> %InVec) {
+entry:
+  %shl = ashr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %shl
+}
+
+; CHECK-LABEL: test_srad_2:
+; CHECK: psrad   $1, %xmm0
+; CHECK-NEXT: ret
+
+define <4 x i32> @test_srad_3(<4 x i32> %InVec) {
+entry:
+  %shl = ashr <4 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32>
+  ret <4 x i32> %shl
+}
+
+; CHECK-LABEL: test_srad_3:
+; CHECK: psrad   $32, %xmm0
+; CHECK-NEXT: ret
+
+; SSE Logical Shift Right
+
+define <8 x i16> @test_srlw_1(<8 x i16> %InVec) {
+entry:
+  %shl = lshr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+  ret <8 x i16> %shl
+}
+
+; CHECK-LABEL: test_srlw_1:
+; CHECK: psrlw   $0, %xmm0
+; CHECK-NEXT: ret
+
+define <8 x i16> @test_srlw_2(<8 x i16> %InVec) {
+entry:
+  %shl = lshr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+  ret <8 x i16> %shl
+}
+
+; CHECK-LABEL: test_srlw_2:
+; CHECK: psrlw   $1, %xmm0
+; CHECK-NEXT: ret
+
+define <8 x i16> @test_srlw_3(<8 x i16> %InVec) {
+entry:
+  %shl = lshr <8 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
+  ret <8 x i16> %shl
+}
+
+; CHECK-LABEL: test_srlw_3:
+; CHECK: xorps   %xmm0, %xmm0
+; CHECK-NEXT: ret
+
+define <4 x i32> @test_srld_1(<4 x i32> %InVec) {
+entry:
+  %shl = lshr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
+  ret <4 x i32> %shl
+}
+
+; CHECK-LABEL: test_srld_1:
+; CHECK: psrld   $0, %xmm0
+; CHECK-NEXT: ret
+
+define <4 x i32> @test_srld_2(<4 x i32> %InVec) {
+entry:
+  %shl = lshr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %shl
+}
+
+; CHECK-LABEL: test_srld_2:
+; CHECK: psrld   $1, %xmm0
+; CHECK-NEXT: ret
+
+define <4 x i32> @test_srld_3(<4 x i32> %InVec) {
+entry:
+  %shl = lshr <4 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32>
+  ret <4 x i32> %shl
+}
+
+; CHECK-LABEL: test_srld_3:
+; CHECK: xorps   %xmm0, %xmm0
+; CHECK-NEXT: ret
+
+define <2 x i64> @test_srlq_1(<2 x i64> %InVec) {
+entry:
+  %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
+  ret <2 x i64> %shl
+}
+
+; CHECK-LABEL: test_srlq_1:
+; CHECK: psrlq   $0, %xmm0
+; CHECK-NEXT: ret
+
+define <2 x i64> @test_srlq_2(<2 x i64> %InVec) {
+entry:
+  %shl = lshr <2 x i64> %InVec, <i64 1, i64 1>
+  ret <2 x i64> %shl
+}
+
+; CHECK-LABEL: test_srlq_2:
+; CHECK: psrlq   $1, %xmm0
+; CHECK-NEXT: ret
+
+define <2 x i64> @test_srlq_3(<2 x i64> %InVec) {
+entry:
+  %shl = lshr <2 x i64> %InVec, <i64 64, i64 64>
+  ret <2 x i64> %shl
+}
+
+; CHECK-LABEL: test_srlq_3:
+; CHECK: xorps   %xmm0, %xmm0
+; CHECK-NEXT: ret
diff --git a/test/CodeGen/X86/sse2.ll b/test/CodeGen/X86/sse2.ll
index 36a0fd9..217139a 100644
--- a/test/CodeGen/X86/sse2.ll
+++ b/test/CodeGen/X86/sse2.ll
@@ -8,7 +8,7 @@ define void @test1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind  {
 	store <2 x double> %tmp9, <2 x double>* %r, align 16
 	ret void
         
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: 	movl	8(%esp), %eax
 ; CHECK-NEXT: 	movapd	(%eax), %xmm0
 ; CHECK-NEXT: 	movlpd	12(%esp), %xmm0
@@ -24,7 +24,7 @@ define void @test2(<2 x double>* %r, <2 x double>* %A, double %B) nounwind  {
 	store <2 x double> %tmp9, <2 x double>* %r, align 16
 	ret void
         
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: 	movl	8(%esp), %eax
 ; CHECK-NEXT: 	movapd	(%eax), %xmm0
 ; CHECK-NEXT: 	movhpd	12(%esp), %xmm0
@@ -60,7 +60,7 @@ define void @test4(<4 x float> %X, <4 x float>* %res) nounwind {
 }
 
 define <4 x i32> @test5(i8** %ptr) nounwind {
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: pxor
 ; CHECK: punpcklbw
 ; CHECK: punpcklwd
@@ -86,7 +86,7 @@ define void @test6(<4 x float>* %res, <4 x float>* %A) nounwind {
         store <4 x float> %tmp2, <4 x float>* %res
         ret void
         
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: 	movaps	(%eax), %xmm0
 ; CHECK:	movaps	%xmm0, (%eax)
 }
@@ -97,7 +97,7 @@ define void @test7() nounwind {
         store <4 x float> %2, <4 x float>* null
         ret void
         
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK:	xorps	%xmm0, %xmm0
 ; CHECK:	movaps	%xmm0, 0
 }
@@ -115,7 +115,7 @@ define <2 x i64> @test8() nounwind {
 	%tmp15 = insertelement <4 x i32> %tmp14, i32 %tmp7, i32 3		; <<4 x i32>> [#uses=1]
 	%tmp16 = bitcast <4 x i32> %tmp15 to <2 x i64>		; <<2 x i64>> [#uses=1]
 	ret <2 x i64> %tmp16
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: movups	(%eax), %xmm0
 }
 
@@ -125,7 +125,7 @@ define <4 x float> @test9(i32 %dummy, float %a, float %b, float %c, float %d) no
 	%tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2		; <<4 x float>> [#uses=1]
 	%tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3		; <<4 x float>> [#uses=1]
 	ret <4 x float> %tmp13
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: movups	8(%esp), %xmm0
 }
 
@@ -135,7 +135,7 @@ define <4 x float> @test10(float %a, float %b, float %c, float %d) nounwind {
 	%tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2		; <<4 x float>> [#uses=1]
 	%tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3		; <<4 x float>> [#uses=1]
 	ret <4 x float> %tmp13
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: movaps	4(%esp), %xmm0
 }
 
@@ -143,7 +143,7 @@ define <2 x double> @test11(double %a, double %b) nounwind {
 	%tmp = insertelement <2 x double> undef, double %a, i32 0		; <<2 x double>> [#uses=1]
 	%tmp7 = insertelement <2 x double> %tmp, double %b, i32 1		; <<2 x double>> [#uses=1]
 	ret <2 x double> %tmp7
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK: movaps	4(%esp), %xmm0
 }
 
@@ -154,7 +154,7 @@ define void @test12() nounwind {
         %tmp4 = fadd <4 x float> %tmp2, %tmp3            ; <<4 x float>> [#uses=1]
         store <4 x float> %tmp4, <4 x float>* null
         ret void
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK: movhlps
 ; CHECK: shufps
 }
@@ -177,7 +177,7 @@ define <4 x float> @test14(<4 x float>* %x, <4 x float>* %y) nounwind {
         %tmp21 = fsub <4 x float> %tmp5, %tmp            ; <<4 x float>> [#uses=1]
         %tmp27 = shufflevector <4 x float> %tmp9, <4 x float> %tmp21, <4 x i32> < i32 0, i32 1, i32 4, i32 5 >                ; <<4 x float>> [#uses=1]
         ret <4 x float> %tmp27
-; CHECK: test14:
+; CHECK-LABEL: test14:
 ; CHECK: 	subps	[[X1:%xmm[0-9]+]], [[X2:%xmm[0-9]+]]
 ; CHECK: 	addps	[[X1]], [[X0:%xmm[0-9]+]]
 ; CHECK: 	movlhps	[[X2]], [[X0]]
@@ -189,12 +189,12 @@ entry:
         %tmp3 = load <4 x float>* %x            ; <<4 x float>> [#uses=1]
         %tmp4 = shufflevector <4 x float> %tmp3, <4 x float> %tmp, <4 x i32> < i32 2, i32 3, i32 6, i32 7 >           ; <<4 x float>> [#uses=1]
         ret <4 x float> %tmp4
-; CHECK: test15:
+; CHECK-LABEL: test15:
 ; CHECK: 	movhlps	%xmm1, %xmm0
 }
 
 ; PR8900
-; CHECK: test16:
+; CHECK-LABEL: test16:
 ; CHECK: unpcklpd
 ; CHECK: ret
 
diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll
index 48638b3..6d5b192 100644
--- a/test/CodeGen/X86/sse3.ll
+++ b/test/CodeGen/X86/sse3.ll
@@ -14,8 +14,8 @@ entry:
                 <8 x i32> < i32 8, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef  >
 	store <8 x i16> %tmp6, <8 x i16>* %dest
 	ret void
-        
-; X64: t0:
+
+; X64-LABEL: t0:
 ; X64:	movdqa	(%rsi), %xmm0
 ; X64:	pslldq	$2, %xmm0
 ; X64:	movdqa	%xmm0, (%rdi)
@@ -27,8 +27,8 @@ define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 	%tmp2 = load <8 x i16>* %B
 	%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
 	ret <8 x i16> %tmp3
-        
-; X64: t1:
+
+; X64-LABEL: t1:
 ; X64: 	movdqa	(%rdi), %xmm0
 ; X64: 	pinsrw	$0, (%rsi), %xmm0
 ; X64: 	ret
@@ -37,7 +37,7 @@ define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) nounwind {
 	%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 9, i32 1, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7 >
 	ret <8 x i16> %tmp
-; X64: t2:
+; X64-LABEL: t2:
 ; X64:	pextrw	$1, %xmm1, %eax
 ; X64:	pinsrw	$0, %eax, %xmm0
 ; X64:	pinsrw	$3, %eax, %xmm0
@@ -47,7 +47,7 @@ define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) nounwind {
 define <8 x i16> @t3(<8 x i16> %A, <8 x i16> %B) nounwind {
 	%tmp = shufflevector <8 x i16> %A, <8 x i16> %A, <8 x i32> < i32 8, i32 3, i32 2, i32 13, i32 7, i32 6, i32 5, i32 4 >
 	ret <8 x i16> %tmp
-; X64: t3:
+; X64-LABEL: t3:
 ; X64: 	pextrw	$5, %xmm0, %eax
 ; X64: 	pshuflw	$44, %xmm0, %xmm0
 ; X64: 	pshufhw	$27, %xmm0, %xmm0
@@ -58,12 +58,12 @@ define <8 x i16> @t3(<8 x i16> %A, <8 x i16> %B) nounwind {
 define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind {
 	%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 7, i32 2, i32 3, i32 1, i32 5, i32 6, i32 5 >
 	ret <8 x i16> %tmp
-; X64: t4:
+; X64-LABEL: t4:
 ; X64: 	pextrw	$7, [[XMM0:%xmm[0-9]+]], %eax
 ; X64: 	pshufhw	$100, [[XMM0]], [[XMM1:%xmm[0-9]+]]
 ; X64: 	pinsrw	$1, %eax, [[XMM1]]
 ; X64: 	pextrw	$1, [[XMM0]], %eax
-; X64: 	pinsrw	$4, %eax, %xmm0
+; X64: 	pinsrw	$4, %eax, %xmm{{[0-9]}}
 ; X64: 	ret
 }
 
@@ -127,13 +127,13 @@ define void @t9(<4 x float>* %r, <2 x i32>* %A) nounwind {
 	%tmp.upgrd.3 = bitcast <2 x i32>* %A to double*
 	%tmp.upgrd.4 = load double* %tmp.upgrd.3
 	%tmp.upgrd.5 = insertelement <2 x double> undef, double %tmp.upgrd.4, i32 0
-	%tmp5 = insertelement <2 x double> %tmp.upgrd.5, double undef, i32 1	
-	%tmp6 = bitcast <2 x double> %tmp5 to <4 x float>	
-	%tmp.upgrd.6 = extractelement <4 x float> %tmp, i32 0	
-	%tmp7 = extractelement <4 x float> %tmp, i32 1		
-	%tmp8 = extractelement <4 x float> %tmp6, i32 0		
-	%tmp9 = extractelement <4 x float> %tmp6, i32 1		
-	%tmp10 = insertelement <4 x float> undef, float %tmp.upgrd.6, i32 0	
+	%tmp5 = insertelement <2 x double> %tmp.upgrd.5, double undef, i32 1
+	%tmp6 = bitcast <2 x double> %tmp5 to <4 x float>
+	%tmp.upgrd.6 = extractelement <4 x float> %tmp, i32 0
+	%tmp7 = extractelement <4 x float> %tmp, i32 1
+	%tmp8 = extractelement <4 x float> %tmp6, i32 0
+	%tmp9 = extractelement <4 x float> %tmp6, i32 1
+	%tmp10 = insertelement <4 x float> undef, float %tmp.upgrd.6, i32 0
 	%tmp11 = insertelement <4 x float> %tmp10, float %tmp7, i32 1
 	%tmp12 = insertelement <4 x float> %tmp11, float %tmp8, i32 2
 	%tmp13 = insertelement <4 x float> %tmp12, float %tmp9, i32 3
@@ -155,21 +155,21 @@ define void @t9(<4 x float>* %r, <2 x i32>* %A) nounwind {
 @g2 = external constant <4 x i16>
 
 define internal void @t10() nounwind {
-        load <4 x i32>* @g1, align 16 
+        load <4 x i32>* @g1, align 16
         bitcast <4 x i32> %1 to <8 x i16>
         shufflevector <8 x i16> %2, <8 x i16> undef, <8 x i32> < i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef >
-        bitcast <8 x i16> %3 to <2 x i64>  
-        extractelement <2 x i64> %4, i32 0 
-        bitcast i64 %5 to <4 x i16>        
+        bitcast <8 x i16> %3 to <2 x i64>
+        extractelement <2 x i64> %4, i32 0
+        bitcast i64 %5 to <4 x i16>
         store <4 x i16> %6, <4 x i16>* @g2, align 8
         ret void
 ; X64: 	t10:
-; X64: 		pextrw	$4, [[X0:%xmm[0-9]+]], %ecx
-; X64: 		pextrw	$6, [[X0]], %eax
+; X64: 		pextrw	$4, [[X0:%xmm[0-9]+]], %e{{..}}
+; X64: 		pextrw	$6, [[X0]], %e{{..}}
 ; X64: 		movlhps [[X0]], [[X0]]
 ; X64: 		pshuflw	$8, [[X0]], [[X0]]
-; X64: 		pinsrw	$2, %ecx, [[X0]]
-; X64: 		pinsrw	$3, %eax, [[X0]]
+; X64: 		pinsrw	$2, %e{{..}}, [[X0]]
+; X64: 		pinsrw	$3, %e{{..}}, [[X0]]
 }
 
 
@@ -179,7 +179,7 @@ entry:
 	%tmp7 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 1, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
 	ret <8 x i16> %tmp7
 
-; X64: t11:
+; X64-LABEL: t11:
 ; X64:	movd	%xmm1, %eax
 ; X64:	movlhps	%xmm0, %xmm0
 ; X64:	pshuflw	$1, %xmm0, %xmm0
@@ -193,7 +193,7 @@ entry:
 	%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 0, i32 1, i32 undef, i32 undef, i32 3, i32 11, i32 undef , i32 undef >
 	ret <8 x i16> %tmp9
 
-; X64: t12:
+; X64-LABEL: t12:
 ; X64: 	pextrw	$3, %xmm1, %eax
 ; X64: 	movlhps	%xmm0, %xmm0
 ; X64: 	pshufhw	$3, %xmm0, %xmm0
@@ -206,7 +206,7 @@ define <8 x i16> @t13(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 entry:
 	%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 11, i32 3, i32 undef , i32 undef >
 	ret <8 x i16> %tmp9
-; X64: t13:
+; X64-LABEL: t13:
 ; X64: 	punpcklqdq	%xmm0, %xmm1
 ; X64: 	pextrw	$3, %xmm1, %eax
 ; X64: 	pshufd	$52, %xmm1, %xmm0
@@ -219,7 +219,7 @@ define <8 x i16> @t14(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 entry:
 	%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 2, i32 undef , i32 undef >
 	ret <8 x i16> %tmp9
-; X64: t14:
+; X64-LABEL: t14:
 ; X64: 	punpcklqdq	%xmm0, %xmm1
 ; X64: 	pshufhw	$8, %xmm1, %xmm0
 ; X64: 	ret
@@ -259,7 +259,7 @@ entry:
 ; rdar://8520311
 define <4 x i32> @t17() nounwind {
 entry:
-; X64: t17:
+; X64-LABEL: t17:
 ; X64:          movddup (%rax), %xmm0
   %tmp1 = load <4 x float>* undef, align 16
   %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
diff --git a/test/CodeGen/X86/sse41-blend.ll b/test/CodeGen/X86/sse41-blend.ll
index a2a0deb..bd92d22 100644
--- a/test/CodeGen/X86/sse41-blend.ll
+++ b/test/CodeGen/X86/sse41-blend.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -mattr=+sse41 | FileCheck %s
 
-;CHECK: vsel_float
+;CHECK-LABEL: vsel_float:
 ;CHECK: blendvps
 ;CHECK: ret
 define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
@@ -9,7 +9,7 @@ define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
 }
 
 
-;CHECK: vsel_4xi8
+;CHECK-LABEL: vsel_4xi8:
 ;CHECK: blendvps
 ;CHECK: ret
 define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
@@ -17,7 +17,7 @@ define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
   ret <4 x i8> %vsel
 }
 
-;CHECK: vsel_4xi16
+;CHECK-LABEL: vsel_4xi16:
 ;CHECK: blendvps
 ;CHECK: ret
 define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) {
@@ -26,7 +26,7 @@ define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) {
 }
 
 
-;CHECK: vsel_i32
+;CHECK-LABEL: vsel_i32:
 ;CHECK: blendvps
 ;CHECK: ret
 define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
@@ -35,7 +35,7 @@ define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
 }
 
 
-;CHECK: vsel_double
+;CHECK-LABEL: vsel_double:
 ;CHECK: blendvpd
 ;CHECK: ret
 define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) {
@@ -44,7 +44,7 @@ define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) {
 }
 
 
-;CHECK: vsel_i64
+;CHECK-LABEL: vsel_i64:
 ;CHECK: blendvpd
 ;CHECK: ret
 define <4 x i64> @vsel_i64(<4 x i64> %v1, <4 x i64> %v2) {
@@ -53,7 +53,7 @@ define <4 x i64> @vsel_i64(<4 x i64> %v1, <4 x i64> %v2) {
 }
 
 
-;CHECK: vsel_i8
+;CHECK-LABEL: vsel_i8:
 ;CHECK: pblendvb
 ;CHECK: ret
 define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
diff --git a/test/CodeGen/X86/sse41.ll b/test/CodeGen/X86/sse41.ll
index c6f9f0c..87b64e5 100644
--- a/test/CodeGen/X86/sse41.ll
+++ b/test/CodeGen/X86/sse41.ll
@@ -6,20 +6,20 @@
 define <4 x i32> @pinsrd_1(i32 %s, <4 x i32> %tmp) nounwind {
         %tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 1
         ret <4 x i32> %tmp1
-; X32: pinsrd_1:
+; X32-LABEL: pinsrd_1:
 ; X32:    pinsrd $1, 4(%esp), %xmm0
 
-; X64: pinsrd_1:
+; X64-LABEL: pinsrd_1:
 ; X64:    pinsrd $1, %edi, %xmm0
 }
 
 define <16 x i8> @pinsrb_1(i8 %s, <16 x i8> %tmp) nounwind {
         %tmp1 = insertelement <16 x i8> %tmp, i8 %s, i32 1
         ret <16 x i8> %tmp1
-; X32: pinsrb_1:
+; X32-LABEL: pinsrb_1:
 ; X32:    pinsrb $1, 4(%esp), %xmm0
 
-; X64: pinsrb_1:
+; X64-LABEL: pinsrb_1:
 ; X64:    pinsrb $1, %edi, %xmm0
 }
 
@@ -237,12 +237,12 @@ entry:
   %tmp11 = insertelement <2 x float> undef, float %add.r, i32 0
   %tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1
   ret <2 x float> %tmp9
-; X32: buildvector:
+; X32-LABEL: buildvector:
 ; X32-NOT: insertps $0
 ; X32: insertps $16
 ; X32-NOT: insertps $0
 ; X32: ret
-; X64: buildvector:
+; X64-LABEL: buildvector:
 ; X64-NOT: insertps $0
 ; X64: insertps $16
 ; X64-NOT: insertps $0
diff --git a/test/CodeGen/X86/sse4a.ll b/test/CodeGen/X86/sse4a.ll
index 076e213..165d476 100644
--- a/test/CodeGen/X86/sse4a.ll
+++ b/test/CodeGen/X86/sse4a.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4a | FileCheck %s
 
 define void @test1(i8* %p, <4 x float> %a) nounwind optsize ssp {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: movntss
   tail call void @llvm.x86.sse4a.movnt.ss(i8* %p, <4 x float> %a) nounwind
   ret void
@@ -10,7 +10,7 @@ define void @test1(i8* %p, <4 x float> %a) nounwind optsize ssp {
 declare void @llvm.x86.sse4a.movnt.ss(i8*, <4 x float>)
 
 define void @test2(i8* %p, <2 x double> %a) nounwind optsize ssp {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movntsd
   tail call void @llvm.x86.sse4a.movnt.sd(i8* %p, <2 x double> %a) nounwind
   ret void
@@ -19,7 +19,7 @@ define void @test2(i8* %p, <2 x double> %a) nounwind optsize ssp {
 declare void @llvm.x86.sse4a.movnt.sd(i8*, <2 x double>)
 
 define <2 x i64> @test3(<2 x i64> %x) nounwind uwtable ssp {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: extrq
   %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2)
   ret <2 x i64> %1
@@ -28,7 +28,7 @@ define <2 x i64> @test3(<2 x i64> %x) nounwind uwtable ssp {
 declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind
 
 define <2 x i64> @test4(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: extrq
   %1 = bitcast <2 x i64> %y to <16 x i8>
   %2 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %1) nounwind
@@ -38,7 +38,7 @@ define <2 x i64> @test4(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
 declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind
 
 define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: insertq
   %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 5, i8 6)
   ret <2 x i64> %1
@@ -47,7 +47,7 @@ define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
 declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind
 
 define <2 x i64> @test6(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: insertq
   %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
   ret <2 x i64> %1
diff --git a/test/CodeGen/X86/sse_partial_update.ll b/test/CodeGen/X86/sse_partial_update.ll
index 655f758..2c16a55 100644
--- a/test/CodeGen/X86/sse_partial_update.ll
+++ b/test/CodeGen/X86/sse_partial_update.ll
@@ -8,7 +8,7 @@
 ; destination of rsqrtss are the same.
 define void @t1(<4 x float> %a) nounwind uwtable ssp {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: rsqrtss %xmm0, %xmm0
   %0 = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %a) nounwind
   %a.addr.0.extract = extractelement <4 x float> %0, i32 0
@@ -23,7 +23,7 @@ declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone
 
 define void @t2(<4 x float> %a) nounwind uwtable ssp {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: rcpss %xmm0, %xmm0
   %0 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %a) nounwind
   %a.addr.0.extract = extractelement <4 x float> %0, i32 0
diff --git a/test/CodeGen/X86/stack-align-memcpy.ll b/test/CodeGen/X86/stack-align-memcpy.ll
index 74945e5..87bb85f 100644
--- a/test/CodeGen/X86/stack-align-memcpy.ll
+++ b/test/CodeGen/X86/stack-align-memcpy.ll
@@ -9,7 +9,7 @@ define void @test1(%struct.foo* nocapture %x, i32 %y) nounwind {
   call void @bar(i8* %dynalloc, %struct.foo* align 4 byval %x)
   ret void
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: andl $-16, %esp
 ; CHECK: movl %esp, %esi
 ; CHECK-NOT: rep;movsl
diff --git a/test/CodeGen/X86/stack-align.ll b/test/CodeGen/X86/stack-align.ll
index 0ddb237..eafb7c2 100644
--- a/test/CodeGen/X86/stack-align.ll
+++ b/test/CodeGen/X86/stack-align.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -relocation-model=static -realign-stack=1 -mcpu=yonah | FileCheck %s
+; RUN: llc < %s -relocation-model=static -mcpu=yonah | FileCheck %s
 
 ; The double argument is at 4(esp) which is 16-byte aligned, allowing us to
 ; fold the load into the andpd.
@@ -45,7 +45,7 @@ entry:
   %0 = ptrtoint [2048 x i8]* %buffer to i32
   %and = and i32 %0, -16
   ret i32 %and
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK-NOT: and
 ; CHECK: ret
 }
diff --git a/test/CodeGen/X86/stack-protector.ll b/test/CodeGen/X86/stack-protector.ll
index 6191ce6..a4dbbb9 100644
--- a/test/CodeGen/X86/stack-protector.ll
+++ b/test/CodeGen/X86/stack-protector.ll
@@ -24,19 +24,19 @@
 ; Requires no protector.
 define void @test1a(i8* %a) nounwind uwtable {
 entry:
-; LINUX-I386: test1a:
+; LINUX-I386-LABEL: test1a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test1a:
+; LINUX-X64-LABEL: test1a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test1a:
+; LINUX-KERNEL-X64-LABEL: test1a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test1a:
+; DARWIN-X64-LABEL: test1a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -55,23 +55,23 @@ entry:
 ; Requires protector.
 define void @test1b(i8* %a) nounwind uwtable ssp {
 entry:
-; LINUX-I386: test1b:
+; LINUX-I386-LABEL: test1b:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test1b:
+; LINUX-X64-LABEL: test1b:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test1b:
+; LINUX-KERNEL-X64-LABEL: test1b:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test1b:
+; DARWIN-X64-LABEL: test1b:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
 
-; OPENBSD-AMD64: test1b:
+; OPENBSD-AMD64-LABEL: test1b:
 ; OPENBSD-AMD64: movq __guard_local(%rip)
 ; OPENBSD-AMD64: callq __stack_smash_handler
   %a.addr = alloca i8*, align 8
@@ -90,19 +90,19 @@ entry:
 ; Requires protector.
 define void @test1c(i8* %a) nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test1c:
+; LINUX-I386-LABEL: test1c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test1c:
+; LINUX-X64-LABEL: test1c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test1c:
+; LINUX-KERNEL-X64-LABEL: test1c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test1c:
+; DARWIN-X64-LABEL: test1c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -121,19 +121,19 @@ entry:
 ; Requires protector.
 define void @test1d(i8* %a) nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test1d:
+; LINUX-I386-LABEL: test1d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test1d:
+; LINUX-X64-LABEL: test1d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test1d:
+; LINUX-KERNEL-X64-LABEL: test1d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test1d:
+; DARWIN-X64-LABEL: test1d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -152,19 +152,19 @@ entry:
 ; Requires no protector.
 define void @test2a(i8* %a) nounwind uwtable {
 entry:
-; LINUX-I386: test2a:
+; LINUX-I386-LABEL: test2a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test2a:
+; LINUX-X64-LABEL: test2a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test2a:
+; LINUX-KERNEL-X64-LABEL: test2a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test2a:
+; DARWIN-X64-LABEL: test2a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -185,19 +185,19 @@ entry:
 ; Requires protector.
 define void @test2b(i8* %a) nounwind uwtable ssp {
 entry:
-; LINUX-I386: test2b:
+; LINUX-I386-LABEL: test2b:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test2b:
+; LINUX-X64-LABEL: test2b:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test2b:
+; LINUX-KERNEL-X64-LABEL: test2b:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test2b:
+; DARWIN-X64-LABEL: test2b:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -218,19 +218,19 @@ entry:
 ; Requires protector.
 define void @test2c(i8* %a) nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test2c:
+; LINUX-I386-LABEL: test2c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test2c:
+; LINUX-X64-LABEL: test2c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test2c:
+; LINUX-KERNEL-X64-LABEL: test2c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test2c:
+; DARWIN-X64-LABEL: test2c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -251,19 +251,19 @@ entry:
 ; Requires protector.
 define void @test2d(i8* %a) nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test2d:
+; LINUX-I386-LABEL: test2d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test2d:
+; LINUX-X64-LABEL: test2d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test2d:
+; LINUX-KERNEL-X64-LABEL: test2d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test2d:
+; DARWIN-X64-LABEL: test2d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -284,19 +284,19 @@ entry:
 ; Requires no protector.
 define void @test3a(i8* %a) nounwind uwtable {
 entry:
-; LINUX-I386: test3a:
+; LINUX-I386-LABEL: test3a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test3a:
+; LINUX-X64-LABEL: test3a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test3a:
+; LINUX-KERNEL-X64-LABEL: test3a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test3a:
+; DARWIN-X64-LABEL: test3a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -315,19 +315,19 @@ entry:
 ; Requires no protector.
 define void @test3b(i8* %a) nounwind uwtable ssp {
 entry:
-; LINUX-I386: test3b:
+; LINUX-I386-LABEL: test3b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test3b:
+; LINUX-X64-LABEL: test3b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test3b:
+; LINUX-KERNEL-X64-LABEL: test3b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test3b:
+; DARWIN-X64-LABEL: test3b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -346,19 +346,19 @@ entry:
 ; Requires protector.
 define void @test3c(i8* %a) nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test3c:
+; LINUX-I386-LABEL: test3c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test3c:
+; LINUX-X64-LABEL: test3c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test3c:
+; LINUX-KERNEL-X64-LABEL: test3c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test3c:
+; DARWIN-X64-LABEL: test3c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -377,19 +377,19 @@ entry:
 ; Requires protector.
 define void @test3d(i8* %a) nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test3d:
+; LINUX-I386-LABEL: test3d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test3d:
+; LINUX-X64-LABEL: test3d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test3d:
+; LINUX-KERNEL-X64-LABEL: test3d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test3d:
+; DARWIN-X64-LABEL: test3d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -408,19 +408,19 @@ entry:
 ; Requires no protector.
 define void @test4a(i8* %a) nounwind uwtable {
 entry:
-; LINUX-I386: test4a:
+; LINUX-I386-LABEL: test4a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test4a:
+; LINUX-X64-LABEL: test4a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test4a:
+; LINUX-KERNEL-X64-LABEL: test4a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test4a:
+; DARWIN-X64-LABEL: test4a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -441,19 +441,19 @@ entry:
 ; Requires no protector.
 define void @test4b(i8* %a) nounwind uwtable ssp {
 entry:
-; LINUX-I386: test4b:
+; LINUX-I386-LABEL: test4b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test4b:
+; LINUX-X64-LABEL: test4b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test4b:
+; LINUX-KERNEL-X64-LABEL: test4b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test4b:
+; DARWIN-X64-LABEL: test4b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -474,19 +474,19 @@ entry:
 ; Requires protector.
 define void @test4c(i8* %a) nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test4c:
+; LINUX-I386-LABEL: test4c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test4c:
+; LINUX-X64-LABEL: test4c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test4c:
+; LINUX-KERNEL-X64-LABEL: test4c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test4c:
+; DARWIN-X64-LABEL: test4c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -507,19 +507,19 @@ entry:
 ; Requires protector.
 define void @test4d(i8* %a) nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test4d:
+; LINUX-I386-LABEL: test4d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test4d:
+; LINUX-X64-LABEL: test4d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test4d:
+; LINUX-KERNEL-X64-LABEL: test4d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test4d:
+; DARWIN-X64-LABEL: test4d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -540,19 +540,19 @@ entry:
 ; Requires no protector.
 define void @test5a(i8* %a) nounwind uwtable {
 entry:
-; LINUX-I386: test5a:
+; LINUX-I386-LABEL: test5a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test5a:
+; LINUX-X64-LABEL: test5a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test5a:
+; LINUX-KERNEL-X64-LABEL: test5a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test5a:
+; DARWIN-X64-LABEL: test5a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -567,19 +567,19 @@ entry:
 ; Requires no protector.
 define void @test5b(i8* %a) nounwind uwtable ssp {
 entry:
-; LINUX-I386: test5b:
+; LINUX-I386-LABEL: test5b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test5b:
+; LINUX-X64-LABEL: test5b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test5b:
+; LINUX-KERNEL-X64-LABEL: test5b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test5b:
+; DARWIN-X64-LABEL: test5b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -594,19 +594,19 @@ entry:
 ; Requires no protector.
 define void @test5c(i8* %a) nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test5c:
+; LINUX-I386-LABEL: test5c:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test5c:
+; LINUX-X64-LABEL: test5c:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test5c:
+; LINUX-KERNEL-X64-LABEL: test5c:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test5c:
+; DARWIN-X64-LABEL: test5c:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a.addr = alloca i8*, align 8
@@ -621,19 +621,19 @@ entry:
 ; Requires protector.
 define void @test5d(i8* %a) nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test5d:
+; LINUX-I386-LABEL: test5d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test5d:
+; LINUX-X64-LABEL: test5d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test5d:
+; LINUX-KERNEL-X64-LABEL: test5d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test5d:
+; DARWIN-X64-LABEL: test5d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a.addr = alloca i8*, align 8
@@ -648,19 +648,19 @@ entry:
 ; Requires no protector.
 define void @test6a() nounwind uwtable {
 entry:
-; LINUX-I386: test6a:
+; LINUX-I386-LABEL: test6a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test6a:
+; LINUX-X64-LABEL: test6a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test6a:
+; LINUX-KERNEL-X64-LABEL: test6a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test6a:
+; DARWIN-X64-LABEL: test6a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %retval = alloca i32, align 4
@@ -679,19 +679,19 @@ entry:
 ; Requires no protector.
 define void @test6b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test6b:
+; LINUX-I386-LABEL: test6b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test6b:
+; LINUX-X64-LABEL: test6b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test6b:
+; LINUX-KERNEL-X64-LABEL: test6b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test6b:
+; DARWIN-X64-LABEL: test6b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %retval = alloca i32, align 4
@@ -710,19 +710,19 @@ entry:
 ; Requires protector.
 define void @test6c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test6c:
+; LINUX-I386-LABEL: test6c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test6c:
+; LINUX-X64-LABEL: test6c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test6c:
+; LINUX-KERNEL-X64-LABEL: test6c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test6c:
+; DARWIN-X64-LABEL: test6c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %retval = alloca i32, align 4
@@ -741,19 +741,19 @@ entry:
 ; Requires protector.
 define void @test6d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test6d:
+; LINUX-I386-LABEL: test6d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test6d:
+; LINUX-X64-LABEL: test6d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test6d:
+; LINUX-KERNEL-X64-LABEL: test6d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test6d:
+; DARWIN-X64-LABEL: test6d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %retval = alloca i32, align 4
@@ -772,19 +772,19 @@ entry:
 ; Requires no protector.
 define void @test7a() nounwind uwtable readnone {
 entry:
-; LINUX-I386: test7a:
+; LINUX-I386-LABEL: test7a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test7a:
+; LINUX-X64-LABEL: test7a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test7a:
+; LINUX-KERNEL-X64-LABEL: test7a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test7a:
+; DARWIN-X64-LABEL: test7a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -798,19 +798,19 @@ entry:
 ; Requires no protector.
 define void @test7b() nounwind uwtable readnone ssp {
 entry:
-; LINUX-I386: test7b:
+; LINUX-I386-LABEL: test7b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test7b:
+; LINUX-X64-LABEL: test7b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test7b:
+; LINUX-KERNEL-X64-LABEL: test7b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test7b:
+; DARWIN-X64-LABEL: test7b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -824,19 +824,19 @@ entry:
 ; Requires protector.
 define void @test7c() nounwind uwtable readnone sspstrong {
 entry:
-; LINUX-I386: test7c:
+; LINUX-I386-LABEL: test7c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test7c:
+; LINUX-X64-LABEL: test7c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test7c:
+; LINUX-KERNEL-X64-LABEL: test7c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test7c:
+; DARWIN-X64-LABEL: test7c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -850,19 +850,19 @@ entry:
 ; Requires protector.
 define void @test7d() nounwind uwtable readnone sspreq {
 entry:
-; LINUX-I386: test7d:
+; LINUX-I386-LABEL: test7d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test7d:
+; LINUX-X64-LABEL: test7d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test7d:
+; LINUX-KERNEL-X64-LABEL: test7d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test7d:
+; DARWIN-X64-LABEL: test7d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -876,19 +876,19 @@ entry:
 ; Requires no protector.
 define void @test8a() nounwind uwtable {
 entry:
-; LINUX-I386: test8a:
+; LINUX-I386-LABEL: test8a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test8a:
+; LINUX-X64-LABEL: test8a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test8a:
+; LINUX-KERNEL-X64-LABEL: test8a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test8a:
+; DARWIN-X64-LABEL: test8a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %b = alloca i32, align 4
@@ -901,19 +901,19 @@ entry:
 ; Requires no protector.
 define void @test8b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test8b:
+; LINUX-I386-LABEL: test8b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test8b:
+; LINUX-X64-LABEL: test8b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test8b:
+; LINUX-KERNEL-X64-LABEL: test8b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test8b:
+; DARWIN-X64-LABEL: test8b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %b = alloca i32, align 4
@@ -926,19 +926,19 @@ entry:
 ; Requires protector.
 define void @test8c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test8c:
+; LINUX-I386-LABEL: test8c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test8c:
+; LINUX-X64-LABEL: test8c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test8c:
+; LINUX-KERNEL-X64-LABEL: test8c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test8c:
+; DARWIN-X64-LABEL: test8c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %b = alloca i32, align 4
@@ -951,19 +951,19 @@ entry:
 ; Requires protector.
 define void @test8d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test8d:
+; LINUX-I386-LABEL: test8d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test8d:
+; LINUX-X64-LABEL: test8d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test8d:
+; LINUX-KERNEL-X64-LABEL: test8d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test8d:
+; DARWIN-X64-LABEL: test8d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %b = alloca i32, align 4
@@ -976,19 +976,19 @@ entry:
 ; Requires no protector.
 define void @test9a() nounwind uwtable {
 entry:
-; LINUX-I386: test9a:
+; LINUX-I386-LABEL: test9a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test9a:
+; LINUX-X64-LABEL: test9a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test9a:
+; LINUX-KERNEL-X64-LABEL: test9a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test9a:
+; DARWIN-X64-LABEL: test9a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %x = alloca double, align 8
@@ -1005,19 +1005,19 @@ entry:
 ; Requires no protector.
 define void @test9b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test9b:
+; LINUX-I386-LABEL: test9b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test9b:
+; LINUX-X64-LABEL: test9b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test9b:
+; LINUX-KERNEL-X64-LABEL: test9b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test9b:
+; DARWIN-X64-LABEL: test9b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %x = alloca double, align 8
@@ -1034,19 +1034,19 @@ entry:
 ; Requires protector.
 define void @test9c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test9c:
+; LINUX-I386-LABEL: test9c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test9c:
+; LINUX-X64-LABEL: test9c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test9c:
+; LINUX-KERNEL-X64-LABEL: test9c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test9c:
+; DARWIN-X64-LABEL: test9c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %x = alloca double, align 8
@@ -1063,19 +1063,19 @@ entry:
 ; Requires protector.
 define void @test9d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test9d:
+; LINUX-I386-LABEL: test9d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test9d:
+; LINUX-X64-LABEL: test9d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test9d:
+; LINUX-KERNEL-X64-LABEL: test9d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test9d:
+; DARWIN-X64-LABEL: test9d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %x = alloca double, align 8
@@ -1092,19 +1092,19 @@ entry:
 ; Requires no protector.
 define void @test10a() nounwind uwtable {
 entry:
-; LINUX-I386: test10a:
+; LINUX-I386-LABEL: test10a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test10a:
+; LINUX-X64-LABEL: test10a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test10a:
+; LINUX-KERNEL-X64-LABEL: test10a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test10a:
+; DARWIN-X64-LABEL: test10a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %x = alloca double, align 8
@@ -1136,19 +1136,19 @@ if.end4:                                          ; preds = %if.else, %if.then3,
 ; Requires no protector.
 define void @test10b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test10b:
+; LINUX-I386-LABEL: test10b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test10b:
+; LINUX-X64-LABEL: test10b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test10b:
+; LINUX-KERNEL-X64-LABEL: test10b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test10b:
+; DARWIN-X64-LABEL: test10b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %x = alloca double, align 8
@@ -1180,19 +1180,19 @@ if.end4:                                          ; preds = %if.else, %if.then3,
 ; Requires protector.
 define void @test10c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test10c:
+; LINUX-I386-LABEL: test10c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test10c:
+; LINUX-X64-LABEL: test10c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test10c:
+; LINUX-KERNEL-X64-LABEL: test10c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test10c:
+; DARWIN-X64-LABEL: test10c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %x = alloca double, align 8
@@ -1224,19 +1224,19 @@ if.end4:                                          ; preds = %if.else, %if.then3,
 ; Requires protector.
 define void @test10d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test10d:
+; LINUX-I386-LABEL: test10d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test10d:
+; LINUX-X64-LABEL: test10d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test10d:
+; LINUX-KERNEL-X64-LABEL: test10d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test10d:
+; DARWIN-X64-LABEL: test10d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %x = alloca double, align 8
@@ -1268,19 +1268,19 @@ if.end4:                                          ; preds = %if.else, %if.then3,
 ; Requires no protector.
 define void @test11a() nounwind uwtable {
 entry:
-; LINUX-I386: test11a:
+; LINUX-I386-LABEL: test11a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test11a:
+; LINUX-X64-LABEL: test11a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test11a:
+; LINUX-KERNEL-X64-LABEL: test11a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test11a:
+; DARWIN-X64-LABEL: test11a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -1297,19 +1297,19 @@ entry:
 ; Requires no protector.
 define void @test11b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test11b:
+; LINUX-I386-LABEL: test11b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test11b:
+; LINUX-X64-LABEL: test11b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test11b:
+; LINUX-KERNEL-X64-LABEL: test11b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test11b:
+; DARWIN-X64-LABEL: test11b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -1326,19 +1326,19 @@ entry:
 ; Requires protector.
 define void @test11c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test11c:
+; LINUX-I386-LABEL: test11c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test11c:
+; LINUX-X64-LABEL: test11c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test11c:
+; LINUX-KERNEL-X64-LABEL: test11c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test11c:
+; DARWIN-X64-LABEL: test11c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -1355,19 +1355,19 @@ entry:
 ; Requires protector.
 define void @test11d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test11d:
+; LINUX-I386-LABEL: test11d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test11d:
+; LINUX-X64-LABEL: test11d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test11d:
+; LINUX-KERNEL-X64-LABEL: test11d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test11d:
+; DARWIN-X64-LABEL: test11d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -1384,19 +1384,19 @@ entry:
 ; Requires no protector.
 define void @test12a() nounwind uwtable {
 entry:
-; LINUX-I386: test12a:
+; LINUX-I386-LABEL: test12a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test12a:
+; LINUX-X64-LABEL: test12a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test12a:
+; LINUX-KERNEL-X64-LABEL: test12a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test12a:
+; DARWIN-X64-LABEL: test12a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -1412,19 +1412,19 @@ entry:
 ; Requires no protector.
 define void @test12b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test12b:
+; LINUX-I386-LABEL: test12b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test12b:
+; LINUX-X64-LABEL: test12b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test12b:
+; LINUX-KERNEL-X64-LABEL: test12b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test12b:
+; DARWIN-X64-LABEL: test12b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -1440,19 +1440,19 @@ entry:
 ; Requires protector.
 define void @test12c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test12c:
+; LINUX-I386-LABEL: test12c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test12c:
+; LINUX-X64-LABEL: test12c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test12c:
+; LINUX-KERNEL-X64-LABEL: test12c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test12c:
+; DARWIN-X64-LABEL: test12c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -1468,19 +1468,19 @@ entry:
 ; Requires protector.
 define void @test12d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test12d:
+; LINUX-I386-LABEL: test12d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test12d:
+; LINUX-X64-LABEL: test12d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test12d:
+; LINUX-KERNEL-X64-LABEL: test12d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test12d:
+; DARWIN-X64-LABEL: test12d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -1496,19 +1496,19 @@ entry:
 ; Requires no protector.
 define void @test13a() nounwind uwtable {
 entry:
-; LINUX-I386: test13a:
+; LINUX-I386-LABEL: test13a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test13a:
+; LINUX-X64-LABEL: test13a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test13a:
+; LINUX-KERNEL-X64-LABEL: test13a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test13a:
+; DARWIN-X64-LABEL: test13a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -1522,19 +1522,19 @@ entry:
 ; Requires no protector.
 define void @test13b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test13b:
+; LINUX-I386-LABEL: test13b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test13b:
+; LINUX-X64-LABEL: test13b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test13b:
+; LINUX-KERNEL-X64-LABEL: test13b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test13b:
+; DARWIN-X64-LABEL: test13b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -1548,19 +1548,19 @@ entry:
 ; Requires protector.
 define void @test13c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test13c:
+; LINUX-I386-LABEL: test13c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test13c:
+; LINUX-X64-LABEL: test13c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test13c:
+; LINUX-KERNEL-X64-LABEL: test13c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test13c:
+; DARWIN-X64-LABEL: test13c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -1574,19 +1574,19 @@ entry:
 ; Requires protector.
 define void @test13d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test13d:
+; LINUX-I386-LABEL: test13d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test13d:
+; LINUX-X64-LABEL: test13d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test13d:
+; LINUX-KERNEL-X64-LABEL: test13d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test13d:
+; DARWIN-X64-LABEL: test13d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -1600,19 +1600,19 @@ entry:
 ; Requires no protector.
 define void @test14a() nounwind uwtable {
 entry:
-; LINUX-I386: test14a:
+; LINUX-I386-LABEL: test14a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test14a:
+; LINUX-X64-LABEL: test14a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test14a:
+; LINUX-KERNEL-X64-LABEL: test14a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test14a:
+; DARWIN-X64-LABEL: test14a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -1626,19 +1626,19 @@ entry:
 ; Requires no protector.
 define void @test14b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test14b:
+; LINUX-I386-LABEL: test14b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test14b:
+; LINUX-X64-LABEL: test14b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test14b:
+; LINUX-KERNEL-X64-LABEL: test14b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test14b:
+; DARWIN-X64-LABEL: test14b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -1652,19 +1652,19 @@ entry:
 ; Requires protector.
 define void @test14c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test14c:
+; LINUX-I386-LABEL: test14c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test14c:
+; LINUX-X64-LABEL: test14c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test14c:
+; LINUX-KERNEL-X64-LABEL: test14c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test14c:
+; DARWIN-X64-LABEL: test14c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -1678,19 +1678,19 @@ entry:
 ; Requires protector.
 define void @test14d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test14d:
+; LINUX-I386-LABEL: test14d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test14d:
+; LINUX-X64-LABEL: test14d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test14d:
+; LINUX-KERNEL-X64-LABEL: test14d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test14d:
+; DARWIN-X64-LABEL: test14d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -1705,19 +1705,19 @@ entry:
 ; Requires no protector.
 define void @test15a() nounwind uwtable {
 entry:
-; LINUX-I386: test15a:
+; LINUX-I386-LABEL: test15a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test15a:
+; LINUX-X64-LABEL: test15a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test15a:
+; LINUX-KERNEL-X64-LABEL: test15a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test15a:
+; DARWIN-X64-LABEL: test15a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -1736,19 +1736,19 @@ entry:
 ; Requires no protector.
 define void @test15b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test15b:
+; LINUX-I386-LABEL: test15b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test15b:
+; LINUX-X64-LABEL: test15b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test15b:
+; LINUX-KERNEL-X64-LABEL: test15b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test15b:
+; DARWIN-X64-LABEL: test15b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -1767,19 +1767,19 @@ entry:
 ; Requires protector.
 define void @test15c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test15c:
+; LINUX-I386-LABEL: test15c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test15c:
+; LINUX-X64-LABEL: test15c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test15c:
+; LINUX-KERNEL-X64-LABEL: test15c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test15c:
+; DARWIN-X64-LABEL: test15c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -1798,19 +1798,19 @@ entry:
 ; Requires protector.
 define void @test15d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test15d:
+; LINUX-I386-LABEL: test15d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test15d:
+; LINUX-X64-LABEL: test15d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test15d:
+; LINUX-KERNEL-X64-LABEL: test15d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test15d:
+; DARWIN-X64-LABEL: test15d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -1829,19 +1829,19 @@ entry:
 ; Requires no protector.
 define void @test16a() nounwind uwtable {
 entry:
-; LINUX-I386: test16a:
+; LINUX-I386-LABEL: test16a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test16a:
+; LINUX-X64-LABEL: test16a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test16a:
+; LINUX-KERNEL-X64-LABEL: test16a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test16a:
+; DARWIN-X64-LABEL: test16a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -1857,19 +1857,19 @@ entry:
 ; Requires no protector.
 define void @test16b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test16b:
+; LINUX-I386-LABEL: test16b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test16b:
+; LINUX-X64-LABEL: test16b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test16b:
+; LINUX-KERNEL-X64-LABEL: test16b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test16b:
+; DARWIN-X64-LABEL: test16b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -1885,19 +1885,19 @@ entry:
 ; Requires protector.
 define void @test16c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test16c:
+; LINUX-I386-LABEL: test16c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test16c:
+; LINUX-X64-LABEL: test16c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test16c:
+; LINUX-KERNEL-X64-LABEL: test16c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test16c:
+; DARWIN-X64-LABEL: test16c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -1913,19 +1913,19 @@ entry:
 ; Requires protector.
 define void @test16d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test16d:
+; LINUX-I386-LABEL: test16d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test16d:
+; LINUX-X64-LABEL: test16d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test16d:
+; LINUX-KERNEL-X64-LABEL: test16d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test16d:
+; DARWIN-X64-LABEL: test16d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -1940,19 +1940,19 @@ entry:
 ; Requires no protector.
 define void @test17a() nounwind uwtable {
 entry:
-; LINUX-I386: test17a:
+; LINUX-I386-LABEL: test17a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test17a:
+; LINUX-X64-LABEL: test17a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test17a:
+; LINUX-KERNEL-X64-LABEL: test17a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test17a:
+; DARWIN-X64-LABEL: test17a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.vec, align 16
@@ -1967,19 +1967,19 @@ entry:
 ; Requires no protector.
 define void @test17b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test17b:
+; LINUX-I386-LABEL: test17b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test17b:
+; LINUX-X64-LABEL: test17b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test17b:
+; LINUX-KERNEL-X64-LABEL: test17b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test17b:
+; DARWIN-X64-LABEL: test17b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.vec, align 16
@@ -1994,19 +1994,19 @@ entry:
 ; Requires protector.
 define void @test17c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test17c:
+; LINUX-I386-LABEL: test17c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test17c:
+; LINUX-X64-LABEL: test17c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test17c:
+; LINUX-KERNEL-X64-LABEL: test17c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test17c:
+; DARWIN-X64-LABEL: test17c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.vec, align 16
@@ -2021,19 +2021,19 @@ entry:
 ; Requires protector.
 define void @test17d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test17d:
+; LINUX-I386-LABEL: test17d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test17d:
+; LINUX-X64-LABEL: test17d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test17d:
+; LINUX-KERNEL-X64-LABEL: test17d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test17d:
+; DARWIN-X64-LABEL: test17d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.vec, align 16
@@ -2048,19 +2048,19 @@ entry:
 ; Requires no protector.
 define i32 @test18a() uwtable {
 entry:
-; LINUX-I386: test18a:
+; LINUX-I386-LABEL: test18a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test18a:
+; LINUX-X64-LABEL: test18a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test18a:
+; LINUX-KERNEL-X64-LABEL: test18a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test18a:
+; DARWIN-X64-LABEL: test18a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -2084,19 +2084,19 @@ lpad:
 ; Requires no protector.
 define i32 @test18b() uwtable ssp {
 entry:
-; LINUX-I386: test18b:
+; LINUX-I386-LABEL: test18b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test18b:
+; LINUX-X64-LABEL: test18b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test18b:
+; LINUX-KERNEL-X64-LABEL: test18b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test18b:
+; DARWIN-X64-LABEL: test18b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32, align 4
@@ -2120,19 +2120,19 @@ lpad:
 ; Requires protector.
 define i32 @test18c() uwtable sspstrong {
 entry:
-; LINUX-I386: test18c:
+; LINUX-I386-LABEL: test18c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test18c:
+; LINUX-X64-LABEL: test18c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test18c:
+; LINUX-KERNEL-X64-LABEL: test18c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test18c:
+; DARWIN-X64-LABEL: test18c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -2156,19 +2156,19 @@ lpad:
 ; Requires protector.
 define i32 @test18d() uwtable sspreq {
 entry:
-; LINUX-I386: test18d:
+; LINUX-I386-LABEL: test18d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test18d:
+; LINUX-X64-LABEL: test18d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test18d:
+; LINUX-KERNEL-X64-LABEL: test18d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test18d:
+; DARWIN-X64-LABEL: test18d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32, align 4
@@ -2193,19 +2193,19 @@ lpad:
 ; Requires no protector.
 define i32 @test19a() uwtable {
 entry:
-; LINUX-I386: test19a:
+; LINUX-I386-LABEL: test19a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test19a:
+; LINUX-X64-LABEL: test19a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test19a:
+; LINUX-KERNEL-X64-LABEL: test19a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test19a:
+; DARWIN-X64-LABEL: test19a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -2232,19 +2232,19 @@ lpad:
 ; Requires no protector.
 define i32 @test19b() uwtable ssp {
 entry:
-; LINUX-I386: test19b:
+; LINUX-I386-LABEL: test19b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test19b:
+; LINUX-X64-LABEL: test19b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test19b:
+; LINUX-KERNEL-X64-LABEL: test19b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test19b:
+; DARWIN-X64-LABEL: test19b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.pair, align 4
@@ -2271,19 +2271,19 @@ lpad:
 ; Requires protector.
 define i32 @test19c() uwtable sspstrong {
 entry:
-; LINUX-I386: test19c:
+; LINUX-I386-LABEL: test19c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test19c:
+; LINUX-X64-LABEL: test19c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test19c:
+; LINUX-KERNEL-X64-LABEL: test19c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test19c:
+; DARWIN-X64-LABEL: test19c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -2310,19 +2310,19 @@ lpad:
 ; Requires protector.
 define i32 @test19d() uwtable sspreq {
 entry:
-; LINUX-I386: test19d:
+; LINUX-I386-LABEL: test19d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test19d:
+; LINUX-X64-LABEL: test19d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test19d:
+; LINUX-KERNEL-X64-LABEL: test19d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test19d:
+; DARWIN-X64-LABEL: test19d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %c = alloca %struct.pair, align 4
@@ -2348,19 +2348,19 @@ lpad:
 ; Requires no protector.
 define void @test20a() nounwind uwtable {
 entry:
-; LINUX-I386: test20a:
+; LINUX-I386-LABEL: test20a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test20a:
+; LINUX-X64-LABEL: test20a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test20a:
+; LINUX-KERNEL-X64-LABEL: test20a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test20a:
+; DARWIN-X64-LABEL: test20a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32*, align 8
@@ -2378,19 +2378,19 @@ entry:
 ; Requires no protector.
 define void @test20b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test20b:
+; LINUX-I386-LABEL: test20b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test20b:
+; LINUX-X64-LABEL: test20b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test20b:
+; LINUX-KERNEL-X64-LABEL: test20b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test20b:
+; DARWIN-X64-LABEL: test20b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32*, align 8
@@ -2408,19 +2408,19 @@ entry:
 ; Requires protector.
 define void @test20c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test20c:
+; LINUX-I386-LABEL: test20c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test20c:
+; LINUX-X64-LABEL: test20c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test20c:
+; LINUX-KERNEL-X64-LABEL: test20c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test20c:
+; DARWIN-X64-LABEL: test20c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32*, align 8
@@ -2438,19 +2438,19 @@ entry:
 ; Requires protector.
 define void @test20d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test20d:
+; LINUX-I386-LABEL: test20d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test20d:
+; LINUX-X64-LABEL: test20d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test20d:
+; LINUX-KERNEL-X64-LABEL: test20d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test20d:
+; DARWIN-X64-LABEL: test20d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32*, align 8
@@ -2468,19 +2468,19 @@ entry:
 ; Requires no protector.
 define void @test21a() nounwind uwtable {
 entry:
-; LINUX-I386: test21a:
+; LINUX-I386-LABEL: test21a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test21a:
+; LINUX-X64-LABEL: test21a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test21a:
+; LINUX-KERNEL-X64-LABEL: test21a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test21a:
+; DARWIN-X64-LABEL: test21a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32*, align 8
@@ -2499,19 +2499,19 @@ entry:
 ; Requires no protector.
 define void @test21b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test21b:
+; LINUX-I386-LABEL: test21b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test21b:
+; LINUX-X64-LABEL: test21b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test21b:
+; LINUX-KERNEL-X64-LABEL: test21b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test21b:
+; DARWIN-X64-LABEL: test21b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca i32*, align 8
@@ -2530,19 +2530,19 @@ entry:
 ; Requires protector.
 define void @test21c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test21c:
+; LINUX-I386-LABEL: test21c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test21c:
+; LINUX-X64-LABEL: test21c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test21c:
+; LINUX-KERNEL-X64-LABEL: test21c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test21c:
+; DARWIN-X64-LABEL: test21c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32*, align 8
@@ -2561,19 +2561,19 @@ entry:
 ; Requires protector.
 define void @test21d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test21d:
+; LINUX-I386-LABEL: test21d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test21d:
+; LINUX-X64-LABEL: test21d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test21d:
+; LINUX-KERNEL-X64-LABEL: test21d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test21d:
+; DARWIN-X64-LABEL: test21d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca i32*, align 8
@@ -2592,19 +2592,19 @@ entry:
 ; Requires no protector.
 define signext i8 @test22a() nounwind uwtable {
 entry:
-; LINUX-I386: test22a:
+; LINUX-I386-LABEL: test22a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test22a:
+; LINUX-X64-LABEL: test22a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test22a:
+; LINUX-KERNEL-X64-LABEL: test22a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test22a:
+; DARWIN-X64-LABEL: test22a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca %class.A, align 1
@@ -2619,19 +2619,19 @@ entry:
 ; Requires no protector.
 define signext i8 @test22b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test22b:
+; LINUX-I386-LABEL: test22b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test22b:
+; LINUX-X64-LABEL: test22b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test22b:
+; LINUX-KERNEL-X64-LABEL: test22b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test22b:
+; DARWIN-X64-LABEL: test22b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca %class.A, align 1
@@ -2646,19 +2646,19 @@ entry:
 ; Requires protector.
 define signext i8 @test22c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test22c:
+; LINUX-I386-LABEL: test22c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test22c:
+; LINUX-X64-LABEL: test22c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test22c:
+; LINUX-KERNEL-X64-LABEL: test22c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test22c:
+; DARWIN-X64-LABEL: test22c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca %class.A, align 1
@@ -2673,19 +2673,19 @@ entry:
 ; Requires protector.
 define signext i8 @test22d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test22d:
+; LINUX-I386-LABEL: test22d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test22d:
+; LINUX-X64-LABEL: test22d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test22d:
+; LINUX-KERNEL-X64-LABEL: test22d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test22d:
+; DARWIN-X64-LABEL: test22d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca %class.A, align 1
@@ -2700,19 +2700,19 @@ entry:
 ; Requires no protector.
 define signext i8 @test23a() nounwind uwtable {
 entry:
-; LINUX-I386: test23a:
+; LINUX-I386-LABEL: test23a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test23a:
+; LINUX-X64-LABEL: test23a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test23a:
+; LINUX-KERNEL-X64-LABEL: test23a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test23a:
+; DARWIN-X64-LABEL: test23a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %x = alloca %struct.deep, align 1
@@ -2731,19 +2731,19 @@ entry:
 ; Requires no protector.
 define signext i8 @test23b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test23b:
+; LINUX-I386-LABEL: test23b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test23b:
+; LINUX-X64-LABEL: test23b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test23b:
+; LINUX-KERNEL-X64-LABEL: test23b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test23b:
+; DARWIN-X64-LABEL: test23b:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %x = alloca %struct.deep, align 1
@@ -2762,19 +2762,19 @@ entry:
 ; Requires protector.
 define signext i8 @test23c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test23c:
+; LINUX-I386-LABEL: test23c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test23c:
+; LINUX-X64-LABEL: test23c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test23c:
+; LINUX-KERNEL-X64-LABEL: test23c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test23c:
+; DARWIN-X64-LABEL: test23c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %x = alloca %struct.deep, align 1
@@ -2793,19 +2793,19 @@ entry:
 ; Requires protector.
 define signext i8 @test23d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test23d:
+; LINUX-I386-LABEL: test23d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test23d:
+; LINUX-X64-LABEL: test23d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test23d:
+; LINUX-KERNEL-X64-LABEL: test23d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test23d:
+; DARWIN-X64-LABEL: test23d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %x = alloca %struct.deep, align 1
@@ -2824,19 +2824,19 @@ entry:
 ; Requires no protector.
 define void @test24a(i32 %n) nounwind uwtable {
 entry:
-; LINUX-I386: test24a:
+; LINUX-I386-LABEL: test24a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test24a:
+; LINUX-X64-LABEL: test24a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test24a:
+; LINUX-KERNEL-X64-LABEL: test24a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test24a:
+; DARWIN-X64-LABEL: test24a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %n.addr = alloca i32, align 4
@@ -2855,19 +2855,19 @@ entry:
 ; Requires protector.
 define void @test24b(i32 %n) nounwind uwtable ssp {
 entry:
-; LINUX-I386: test24b:
+; LINUX-I386-LABEL: test24b:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test24b:
+; LINUX-X64-LABEL: test24b:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test24b:
+; LINUX-KERNEL-X64-LABEL: test24b:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test24b:
+; DARWIN-X64-LABEL: test24b:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %n.addr = alloca i32, align 4
@@ -2886,19 +2886,19 @@ entry:
 ; Requires protector.
 define void @test24c(i32 %n) nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test24c:
+; LINUX-I386-LABEL: test24c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test24c:
+; LINUX-X64-LABEL: test24c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test24c:
+; LINUX-KERNEL-X64-LABEL: test24c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test24c:
+; DARWIN-X64-LABEL: test24c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %n.addr = alloca i32, align 4
@@ -2917,19 +2917,19 @@ entry:
 ; Requires protector.
 define void @test24d(i32 %n) nounwind uwtable sspreq  {
 entry:
-; LINUX-I386: test24d:
+; LINUX-I386-LABEL: test24d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test24d:
+; LINUX-X64-LABEL: test24d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test24d:
+; LINUX-KERNEL-X64-LABEL: test24d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test24d:
+; DARWIN-X64-LABEL: test24d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %n.addr = alloca i32, align 4
@@ -2948,19 +2948,19 @@ entry:
 ; Requires no protector.
 define i32 @test25a() nounwind uwtable {
 entry:
-; LINUX-I386: test25a:
+; LINUX-I386-LABEL: test25a:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test25a:
+; LINUX-X64-LABEL: test25a:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test25a:
+; LINUX-KERNEL-X64-LABEL: test25a:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test25a:
+; DARWIN-X64-LABEL: test25a:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %a = alloca [4 x i32], align 16
@@ -2974,19 +2974,19 @@ entry:
 ; Requires no protector, except for Darwin which _does_ require a protector.
 define i32 @test25b() nounwind uwtable ssp {
 entry:
-; LINUX-I386: test25b:
+; LINUX-I386-LABEL: test25b:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test25b:
+; LINUX-X64-LABEL: test25b:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test25b:
+; LINUX-KERNEL-X64-LABEL: test25b:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test25b:
+; DARWIN-X64-LABEL: test25b:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca [4 x i32], align 16
@@ -3000,19 +3000,19 @@ entry:
 ; Requires protector.
 define i32 @test25c() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test25c:
+; LINUX-I386-LABEL: test25c:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test25c:
+; LINUX-X64-LABEL: test25c:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test25c:
+; LINUX-KERNEL-X64-LABEL: test25c:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test25c:
+; DARWIN-X64-LABEL: test25c:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca [4 x i32], align 16
@@ -3026,19 +3026,19 @@ entry:
 ; Requires protector.
 define i32 @test25d() nounwind uwtable sspreq {
 entry:
-; LINUX-I386: test25d:
+; LINUX-I386-LABEL: test25d:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test25d:
+; LINUX-X64-LABEL: test25d:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test25d:
+; LINUX-KERNEL-X64-LABEL: test25d:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test25d:
+; DARWIN-X64-LABEL: test25d:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %a = alloca [4 x i32], align 16
@@ -3054,19 +3054,19 @@ entry:
 ; Requires no protector.
 define void @test26() nounwind uwtable sspstrong {
 entry:
-; LINUX-I386: test26:
+; LINUX-I386-LABEL: test26:
 ; LINUX-I386-NOT: calll __stack_chk_fail
 ; LINUX-I386: .cfi_endproc
 
-; LINUX-X64: test26:
+; LINUX-X64-LABEL: test26:
 ; LINUX-X64-NOT: callq __stack_chk_fail
 ; LINUX-X64: .cfi_endproc
 
-; LINUX-KERNEL-X64: test26:
+; LINUX-KERNEL-X64-LABEL: test26:
 ; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
 ; LINUX-KERNEL-X64: .cfi_endproc
 
-; DARWIN-X64: test26:
+; DARWIN-X64-LABEL: test26:
 ; DARWIN-X64-NOT: callq ___stack_chk_fail
 ; DARWIN-X64: .cfi_endproc
   %c = alloca %struct.nest, align 4
@@ -3085,19 +3085,19 @@ entry:
 ; Requires protector.
 define i32 @test27(i32 %arg) nounwind uwtable sspstrong {
 bb:
-; LINUX-I386: test27:
+; LINUX-I386-LABEL: test27:
 ; LINUX-I386: mov{{l|q}} %gs:
 ; LINUX-I386: calll __stack_chk_fail
 
-; LINUX-X64: test27:
+; LINUX-X64-LABEL: test27:
 ; LINUX-X64: mov{{l|q}} %fs:
 ; LINUX-X64: callq __stack_chk_fail
 
-; LINUX-KERNEL-X64: test27:
+; LINUX-KERNEL-X64-LABEL: test27:
 ; LINUX-KERNEL-X64: mov{{l|q}} %gs:
 ; LINUX-KERNEL-X64: callq __stack_chk_fail
 
-; DARWIN-X64: test27:
+; DARWIN-X64-LABEL: test27:
 ; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
 ; DARWIN-X64: callq ___stack_chk_fail
   %tmp = alloca %struct.small*, align 8
diff --git a/test/CodeGen/X86/stdcall-notailcall.ll b/test/CodeGen/X86/stdcall-notailcall.ll
index 8e33c30..8f522cd 100644
--- a/test/CodeGen/X86/stdcall-notailcall.ll
+++ b/test/CodeGen/X86/stdcall-notailcall.ll
@@ -2,7 +2,7 @@
 
 %struct.I = type { i32 (...)** }
 define x86_stdcallcc void @bar(%struct.I* nocapture %this) ssp align 2 {
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK-NOT: jmp
 ; CHECK: ret $4
 entry:
diff --git a/test/CodeGen/X86/store-narrow.ll b/test/CodeGen/X86/store-narrow.ll
index 0dd228e..fab266f 100644
--- a/test/CodeGen/X86/store-narrow.ll
+++ b/test/CodeGen/X86/store-narrow.ll
@@ -13,10 +13,10 @@ entry:
   store i32 %D, i32* %a0, align 4
   ret void
   
-; X64: test1:
+; X64-LABEL: test1:
 ; X64: movb	%sil, (%rdi)
 
-; X32: test1:
+; X32-LABEL: test1:
 ; X32: movb	8(%esp), %al
 ; X32: movb	%al, (%{{.*}})
 }
@@ -30,10 +30,10 @@ entry:
   %D = or i32 %B, %CS
   store i32 %D, i32* %a0, align 4
   ret void
-; X64: test2:
+; X64-LABEL: test2:
 ; X64: movb	%sil, 1(%rdi)
 
-; X32: test2:
+; X32-LABEL: test2:
 ; X32: movb	8(%esp), %al
 ; X32: movb	%al, 1(%{{.*}})
 }
@@ -46,10 +46,10 @@ entry:
   %D = or i32 %B, %C
   store i32 %D, i32* %a0, align 4
   ret void
-; X64: test3:
+; X64-LABEL: test3:
 ; X64: movw	%si, (%rdi)
 
-; X32: test3:
+; X32-LABEL: test3:
 ; X32: movw	8(%esp), %ax
 ; X32: movw	%ax, (%{{.*}})
 }
@@ -63,10 +63,10 @@ entry:
   %D = or i32 %B, %CS
   store i32 %D, i32* %a0, align 4
   ret void
-; X64: test4:
+; X64-LABEL: test4:
 ; X64: movw	%si, 2(%rdi)
 
-; X32: test4:
+; X32-LABEL: test4:
 ; X32: movl	8(%esp), %eax
 ; X32: movw	%ax, 2(%{{.*}})
 }
@@ -80,10 +80,10 @@ entry:
   %D = or i64 %B, %CS
   store i64 %D, i64* %a0, align 4
   ret void
-; X64: test5:
+; X64-LABEL: test5:
 ; X64: movw	%si, 2(%rdi)
 
-; X32: test5:
+; X32-LABEL: test5:
 ; X32: movzwl	8(%esp), %eax
 ; X32: movw	%ax, 2(%{{.*}})
 }
@@ -97,11 +97,11 @@ entry:
   %D = or i64 %B, %CS
   store i64 %D, i64* %a0, align 4
   ret void
-; X64: test6:
+; X64-LABEL: test6:
 ; X64: movb	%sil, 5(%rdi)
 
 
-; X32: test6:
+; X32-LABEL: test6:
 ; X32: movb	8(%esp), %al
 ; X32: movb	%al, 5(%{{.*}})
 }
@@ -116,11 +116,11 @@ entry:
   %D = or i64 %B, %CS
   store i64 %D, i64* %a0, align 4
   ret i32 %OtherLoad
-; X64: test7:
+; X64-LABEL: test7:
 ; X64: movb	%sil, 5(%rdi)
 
 
-; X32: test7:
+; X32-LABEL: test7:
 ; X32: movb	8(%esp), %cl
 ; X32: movb	%cl, 5(%{{.*}})
 }
@@ -129,7 +129,7 @@ entry:
 
 @g_16 = internal global i32 -1
 
-; X64: test8:
+; X64-LABEL: test8:
 ; X64-NEXT: movl _g_16(%rip), %eax
 ; X64-NEXT: movl $0, _g_16(%rip)
 ; X64-NEXT: orl  $1, %eax
@@ -143,7 +143,7 @@ define void @test8() nounwind {
   ret void
 }
 
-; X64: test9:
+; X64-LABEL: test9:
 ; X64-NEXT: orb $1, _g_16(%rip)
 ; X64-NEXT: ret
 define void @test9() nounwind {
@@ -154,7 +154,7 @@ define void @test9() nounwind {
 }
 
 ; rdar://8494845 + PR8244
-; X64: test10:
+; X64-LABEL: test10:
 ; X64-NEXT: movsbl	(%rdi), %eax
 ; X64-NEXT: shrl	$8, %eax
 ; X64-NEXT: ret
diff --git a/test/CodeGen/X86/store_op_load_fold.ll b/test/CodeGen/X86/store_op_load_fold.ll
index 070cccd..bbeb744 100644
--- a/test/CodeGen/X86/store_op_load_fold.ll
+++ b/test/CodeGen/X86/store_op_load_fold.ll
@@ -5,7 +5,7 @@
 @X = internal global i16 0              ; <i16*> [#uses=2]
 
 define void @foo() nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK-NOT: mov
 ; CHECK: add
 ; CHECK-NEXT: ret
@@ -19,7 +19,7 @@ define void @foo() nounwind {
 %struct.S2 = type { i64, i16, [2 x i8], i8, [3 x i8], [7 x i8], i8, [8 x i8] }
 @s2 = external global %struct.S2, align 16
 define void @test2() nounwind uwtable ssp {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: mov
 ; CHECK-NEXT: and
 ; CHECK-NEXT: ret
diff --git a/test/CodeGen/X86/store_op_load_fold2.ll b/test/CodeGen/X86/store_op_load_fold2.ll
index 6e4fe90..705fdcd 100644
--- a/test/CodeGen/X86/store_op_load_fold2.ll
+++ b/test/CodeGen/X86/store_op_load_fold2.ll
@@ -17,10 +17,10 @@ cond_true2732.preheader:                ; preds = %entry
         store i64 %tmp2676.us.us, i64* %tmp2666
         ret i32 0
 
-; INTEL: 	and	{{E..}}, DWORD PTR [360]
-; INTEL:	and	DWORD PTR [356], {{E..}}
-; FIXME:	mov	DWORD PTR [360], {{E..}}
-; The above line comes out as 'mov 360, EAX', but when the register is ECX it works?
+; INTEL: 	and	{{e..}}, dword ptr [360]
+; INTEL:	and	dword ptr [356], {{e..}}
+; FIXME:	mov	dword ptr [360], {{e..}}
+; The above line comes out as 'mov 360, eax', but when the register is ecx it works?
 
 ; ATT: 	andl	360, %{{e..}}
 ; ATT:	andl	%{{e..}}, 356
diff --git a/test/CodeGen/X86/sub-with-overflow.ll b/test/CodeGen/X86/sub-with-overflow.ll
index db8313c..baaee35 100644
--- a/test/CodeGen/X86/sub-with-overflow.ll
+++ b/test/CodeGen/X86/sub-with-overflow.ll
@@ -18,7 +18,7 @@ overflow:
   %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
 
-; CHECK: func1:
+; CHECK-LABEL: func1:
 ; CHECK: subl 20(%esp)
 ; CHECK-NEXT: jno
 }
@@ -38,7 +38,7 @@ carry:
   %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
 
-; CHECK: func2:
+; CHECK-LABEL: func2:
 ; CHECK: subl 20(%esp)
 ; CHECK-NEXT: jae
 }
@@ -53,7 +53,7 @@ entry:
   %obit = extractvalue {i32, i1} %t, 1
   ret i1 %obit
 
-; CHECK: func3:
+; CHECK-LABEL: func3:
 ; CHECK: decl
 ; CHECK-NEXT: seto
 }
diff --git a/test/CodeGen/X86/sub.ll b/test/CodeGen/X86/sub.ll
index ee5ea1d..3cf79a3 100644
--- a/test/CodeGen/X86/sub.ll
+++ b/test/CodeGen/X86/sub.ll
@@ -4,7 +4,7 @@ define i32 @test1(i32 %x) {
   %xor = xor i32 %x, 31
   %sub = sub i32 32, %xor
   ret i32 %sub
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK:      xorl $-32
 ; CHECK-NEXT: addl $33
 ; CHECK-NEXT: ret
diff --git a/test/CodeGen/X86/switch-bt.ll b/test/CodeGen/X86/switch-bt.ll
index 58a5c03..a80002b 100644
--- a/test/CodeGen/X86/switch-bt.ll
+++ b/test/CodeGen/X86/switch-bt.ll
@@ -53,7 +53,7 @@ declare void @foo(i32)
 ; Don't zero extend the test operands to pointer type if it can be avoided.
 ; rdar://8781238
 define void @test2(i32 %x) nounwind ssp {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: cmpl $6
 ; CHECK: ja
 
@@ -81,7 +81,7 @@ if.end:                                           ; preds = %entry
 declare void @bar()
 
 define void @test3(i32 %x) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: cmpl $5
 ; CHECK: ja
 ; CHECK: cmpl $4
diff --git a/test/CodeGen/X86/switch-order-weight.ll b/test/CodeGen/X86/switch-order-weight.ll
index 0fdd56d..207e0b3 100644
--- a/test/CodeGen/X86/switch-order-weight.ll
+++ b/test/CodeGen/X86/switch-order-weight.ll
@@ -10,7 +10,7 @@ entry:
     i32 20, label %if.then5
   ]
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: unr
 ; CHECK: cmpl $10
 ; CHECK: bar
diff --git a/test/CodeGen/X86/tail-call-got.ll b/test/CodeGen/X86/tail-call-got.ll
index 1d7eb2e..84d561d 100644
--- a/test/CodeGen/X86/tail-call-got.ll
+++ b/test/CodeGen/X86/tail-call-got.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 target triple = "i386-unknown-freebsd9.0"
 
 define double @test1(double %x) nounwind readnone {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: movl foo@GOT
 ; CHECK-NEXT: jmpl
   %1 = tail call double @foo(double %x) nounwind readnone
@@ -14,7 +14,7 @@ define double @test1(double %x) nounwind readnone {
 declare double @foo(double) readnone
 
 define double @test2(double %x) nounwind readnone {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movl sin@GOT
 ; CHECK-NEXT: jmpl
   %1 = tail call double @sin(double %x) nounwind readnone
diff --git a/test/CodeGen/X86/tail-call-legality.ll b/test/CodeGen/X86/tail-call-legality.ll
new file mode 100644
index 0000000..1196104
--- /dev/null
+++ b/test/CodeGen/X86/tail-call-legality.ll
@@ -0,0 +1,32 @@
+; RUN: llc -march=x86 -o - < %s | FileCheck %s
+
+; This used to be classified as a tail call because of a mismatch in the
+; arguments seen by Analysis.cpp and ISelLowering. As seen by ISelLowering, they
+; both return {i32, i32, i32} (since i64 is illegal) which is fine for a tail
+; call.
+
+; As seen by Analysis.cpp: i64 -> i32 is a valid trunc, second i32 passes
+; straight through and the third is undef, also OK for a tail call.
+
+; Analysis.cpp was wrong.
+
+; FIXME: in principle we *could* support some tail calls involving truncations
+; of illegal types: a single "trunc i64 %whatever to i32" is probably valid
+; because of how the extra registers are laid out.
+
+declare {i64, i32} @test()
+
+define {i32, i32, i32} @test_pair_notail(i64 %in) {
+; CHECK-LABEL: test_pair_notail
+; CHECK-NOT: jmp
+
+  %whole = tail call {i64, i32} @test()
+  %first = extractvalue {i64, i32} %whole, 0
+  %first.trunc = trunc i64 %first to i32
+
+  %second = extractvalue {i64, i32} %whole, 1
+
+  %tmp = insertvalue {i32, i32, i32} undef, i32 %first.trunc, 0
+  %res = insertvalue {i32, i32, i32} %tmp, i32 %second, 1
+  ret {i32, i32, i32} %res
+}
diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll
index 75a728c..73d93ff 100644
--- a/test/CodeGen/X86/tail-opts.ll
+++ b/test/CodeGen/X86/tail-opts.ll
@@ -13,7 +13,7 @@ declare i1 @qux()
 ; BranchFolding should tail-merge the stores since they all precede
 ; direct branches to the same place.
 
-; CHECK: tail_merge_me:
+; CHECK-LABEL: tail_merge_me:
 ; CHECK-NOT:  GHJK
 ; CHECK:      movl $0, GHJK(%rip)
 ; CHECK-NEXT: movl $1, HABC(%rip)
@@ -60,7 +60,7 @@ declare i8* @choose(i8*, i8*)
 ; BranchFolding should tail-duplicate the indirect jump to avoid
 ; redundant branching.
 
-; CHECK: tail_duplicate_me:
+; CHECK-LABEL: tail_duplicate_me:
 ; CHECK:      movl $0, GHJK(%rip)
 ; CHECK-NEXT: jmpq *%r
 ; CHECK:      movl $0, GHJK(%rip)
@@ -107,7 +107,7 @@ altret:
 ; BranchFolding shouldn't try to merge the tails of two blocks
 ; with only a branch in common, regardless of the fallthrough situation.
 
-; CHECK: dont_merge_oddly:
+; CHECK-LABEL: dont_merge_oddly:
 ; CHECK-NOT:   ret
 ; CHECK:        ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
 ; CHECK-NEXT:   jbe .LBB2_3
@@ -153,7 +153,7 @@ bb30:
 ; Do any-size tail-merging when two candidate blocks will both require
 ; an unconditional jump to complete a two-way conditional branch.
 
-; CHECK: c_expand_expr_stmt:
+; CHECK-LABEL: c_expand_expr_stmt:
 ;
 ; This test only works when register allocation happens to use %rax for both
 ; load addresses.
@@ -275,7 +275,7 @@ declare fastcc %union.tree_node* @default_conversion(%union.tree_node*) nounwind
 ; instructions are involved. This function should have only
 ; one ret instruction.
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK:        callq func
 ; CHECK-NEXT: .LBB4_2:
 ; CHECK-NEXT:   popq
@@ -298,7 +298,7 @@ declare void @func()
 
 ; one - One instruction may be tail-duplicated even with optsize.
 
-; CHECK: one:
+; CHECK-LABEL: one:
 ; CHECK: movl $0, XYZ(%rip)
 ; CHECK: movl $0, XYZ(%rip)
 
@@ -335,7 +335,7 @@ return:
 ; tail instead of one. This is too much to be merged, given
 ; the optsize attribute.
 
-; CHECK: two:
+; CHECK-LABEL: two:
 ; CHECK-NOT: XYZ
 ; CHECK: ret
 ; CHECK: movl $0, XYZ(%rip)
@@ -374,7 +374,7 @@ return:
 ; two_nosize - Same as two, but without the optsize attribute.
 ; Now two instructions are enough to be tail-duplicated.
 
-; CHECK: two_nosize:
+; CHECK-LABEL: two_nosize:
 ; CHECK: movl $0, XYZ(%rip)
 ; CHECK: movl $1, XYZ(%rip)
 ; CHECK: movl $0, XYZ(%rip)
@@ -412,7 +412,7 @@ return:
 ; Tail-merging should merge the two ret instructions since one side
 ; can fall-through into the ret and the other side has to branch anyway.
 
-; CHECK: TESTE:
+; CHECK-LABEL: TESTE:
 ; CHECK: ret
 ; CHECK-NOT: ret
 ; CHECK: size TESTE
diff --git a/test/CodeGen/X86/tailcall-64.ll b/test/CodeGen/X86/tailcall-64.ll
index 60fe776..deab1dc 100644
--- a/test/CodeGen/X86/tailcall-64.ll
+++ b/test/CodeGen/X86/tailcall-64.ll
@@ -6,7 +6,7 @@ define i64 @test_trivial() {
  %A = tail call i64 @testi()
  ret i64 %A
 }
-; CHECK: test_trivial:
+; CHECK-LABEL: test_trivial:
 ; CHECK: jmp	_testi                  ## TAILCALL
 
 
@@ -15,7 +15,7 @@ define i64 @test_noop_bitcast() {
  %B = bitcast i64 %A to i64
  ret i64 %B
 }
-; CHECK: test_noop_bitcast:
+; CHECK-LABEL: test_noop_bitcast:
 ; CHECK: jmp	_testi                  ## TAILCALL
 
 
@@ -26,7 +26,7 @@ define i8* @test_inttoptr() {
   ret i8* %B
 }
 
-; CHECK: test_inttoptr:
+; CHECK-LABEL: test_inttoptr:
 ; CHECK: jmp	_testi                  ## TAILCALL
 
 
@@ -37,7 +37,7 @@ define <4 x i32> @test_vectorbitcast() {
   %B = bitcast <4 x float> %A to <4 x i32>
   ret <4 x i32> %B
 }
-; CHECK: test_vectorbitcast:
+; CHECK-LABEL: test_vectorbitcast:
 ; CHECK: jmp	_testv                  ## TAILCALL
 
 
@@ -47,7 +47,7 @@ define {i64, i64} @test_pair_trivial() {
   %A = tail call { i64, i64} @testp()
   ret { i64, i64} %A
 }
-; CHECK: test_pair_trivial:
+; CHECK-LABEL: test_pair_trivial:
 ; CHECK: jmp	_testp                  ## TAILCALL
 
 define {i64, i64} @test_pair_notail() {
@@ -58,7 +58,7 @@ define {i64, i64} @test_pair_notail() {
 
   ret { i64, i64} %c
 }
-; CHECK: test_pair_notail:
+; CHECK-LABEL: test_pair_notail:
 ; CHECK-NOT: jmp	_testi
 
 define {i64, i64} @test_pair_extract_trivial() {
@@ -72,7 +72,7 @@ define {i64, i64} @test_pair_extract_trivial() {
   ret { i64, i64} %c
 }
 
-; CHECK: test_pair_extract_trivial:
+; CHECK-LABEL: test_pair_extract_trivial:
 ; CHECK: jmp	_testp                  ## TAILCALL
 
 define {i64, i64} @test_pair_extract_notail() {
@@ -86,7 +86,7 @@ define {i64, i64} @test_pair_extract_notail() {
   ret { i64, i64} %c
 }
 
-; CHECK: test_pair_extract_notail:
+; CHECK-LABEL: test_pair_extract_notail:
 ; CHECK-NOT: jmp	_testp
 
 define {i8*, i64} @test_pair_extract_conv() {
@@ -102,7 +102,7 @@ define {i8*, i64} @test_pair_extract_conv() {
   ret { i8*, i64} %c
 }
 
-; CHECK: test_pair_extract_conv:
+; CHECK-LABEL: test_pair_extract_conv:
 ; CHECK: jmp	_testp                  ## TAILCALL
 
 define {i64, i64} @test_pair_extract_multiple() {
@@ -122,7 +122,7 @@ define {i64, i64} @test_pair_extract_multiple() {
   ret { i64, i64} %e
 }
 
-; CHECK: test_pair_extract_multiple:
+; CHECK-LABEL: test_pair_extract_multiple:
 ; CHECK: jmp	_testp                  ## TAILCALL
 
 define {i64, i64} @test_pair_extract_undef() {
@@ -134,7 +134,7 @@ define {i64, i64} @test_pair_extract_undef() {
   ret { i64, i64} %b
 }
 
-; CHECK: test_pair_extract_undef:
+; CHECK-LABEL: test_pair_extract_undef:
 ; CHECK: jmp	_testp                  ## TAILCALL
 
 declare { i64, { i32, i32 } } @testn()
@@ -154,7 +154,7 @@ define {i64, {i32, i32}} @test_nest() {
   ret { i64, { i32, i32}} %c
 }
 
-; CHECK: test_nest:
+; CHECK-LABEL: test_nest:
 ; CHECK: jmp	_testn                  ## TAILCALL
 
 %struct.A = type { i32 }
@@ -169,7 +169,7 @@ entry:
   ret %struct.A* %x
 }
 
-; CHECK: test_upcast:
+; CHECK-LABEL: test_upcast:
 ; CHECK: jmp	_testu                  ## TAILCALL
 
 ; PR13006
@@ -206,7 +206,7 @@ entry:
 ;   return funcs[n](0, 0, 0, 0, 0, 0);
 ; }
 ;
-; CHECK: rdar12282281
+; CHECK-LABEL: rdar12282281
 ; CHECK: jmpq *%r11 # TAILCALL
 @funcs = external constant [0 x i32 (i8*, ...)*]
 
@@ -221,7 +221,7 @@ entry:
 
 define x86_fp80 @fp80_call(x86_fp80 %x) nounwind  {
 entry:
-; CHECK: fp80_call:
+; CHECK-LABEL: fp80_call:
 ; CHECK: jmp _fp80_callee
   %call = tail call x86_fp80 @fp80_callee(x86_fp80 %x) nounwind
   ret x86_fp80 %call
@@ -232,7 +232,7 @@ declare x86_fp80 @fp80_callee(x86_fp80)
 ; rdar://12229511
 define x86_fp80 @trunc_fp80(x86_fp80 %x) nounwind  {
 entry:
-; CHECK: trunc_fp80
+; CHECK-LABEL: trunc_fp80
 ; CHECK: callq _trunc
 ; CHECK-NOT: jmp _trunc
 ; CHECK: ret
diff --git a/test/CodeGen/X86/tailcall-calleesave.ll b/test/CodeGen/X86/tailcall-calleesave.ll
new file mode 100644
index 0000000..c748bce
--- /dev/null
+++ b/test/CodeGen/X86/tailcall-calleesave.ll
@@ -0,0 +1,19 @@
+; RUN: llc -march=x86 -tailcallopt -mcpu=core < %s | FileCheck %s
+
+target triple = "i686-apple-darwin"
+
+declare fastcc void @foo(i32, i32, i32, i32, i32, i32)
+declare i32* @bar(i32*)
+
+define fastcc void @hoge(i32 %b) nounwind {
+; Do not overwrite pushed callee-save registers
+; CHECK: pushl
+; CHECK: subl $[[SIZE:[0-9]+]], %esp
+; CHECK-NOT: [[SIZE]](%esp)
+  %a = alloca i32
+  store i32 0, i32* %a
+  %d = tail call i32* @bar(i32* %a) nounwind
+  store i32 %b, i32* %d
+  tail call fastcc void @foo(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6) nounwind
+  ret void
+}
diff --git a/test/CodeGen/X86/tailcall-cgp-dup.ll b/test/CodeGen/X86/tailcall-cgp-dup.ll
index a80b90f..a51bc88 100644
--- a/test/CodeGen/X86/tailcall-cgp-dup.ll
+++ b/test/CodeGen/X86/tailcall-cgp-dup.ll
@@ -4,7 +4,7 @@
 ; rdar://9147433
 
 define i32 @foo(i32 %x) nounwind ssp {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 entry:
   switch i32 %x, label %return [
     i32 1, label %sw.bb
@@ -69,7 +69,7 @@ declare i8* @bar(i8*) uwtable optsize noinline ssp
 
 define hidden %0* @thingWithValue(i8* %self) uwtable ssp {
 entry:
-; CHECK: thingWithValue:
+; CHECK-LABEL: thingWithValue:
 ; CHECK: jmp _bar
   br i1 undef, label %if.then.i, label %if.else.i
 
diff --git a/test/CodeGen/X86/tailcall-disable.ll b/test/CodeGen/X86/tailcall-disable.ll
index b628f5e..1fd2d72 100644
--- a/test/CodeGen/X86/tailcall-disable.ll
+++ b/test/CodeGen/X86/tailcall-disable.ll
@@ -15,12 +15,12 @@ entry:
   ret i32 %call
 }
 
-; CALL: test1:
+; CALL-LABEL: test1:
 ; CALL-NOT: ret
 ; CALL: callq helper
 ; CALL: ret
 
-; JMP: test1:
+; JMP-LABEL: test1:
 ; JMP-NOT: ret
 ; JMP: jmp helper # TAILCALL
 
@@ -30,11 +30,11 @@ entry:
   ret i32 %call
 }
 
-; CALL: test2:
+; CALL-LABEL: test2:
 ; CALL-NOT: ret
 ; CALL: callq test2
 ; CALL: ret
 
-; JMP: test2:
+; JMP-LABEL: test2:
 ; JMP-NOT: ret
 ; JMP: jmp test2 # TAILCALL
diff --git a/test/CodeGen/X86/tailcallbyval64.ll b/test/CodeGen/X86/tailcallbyval64.ll
index 7621602..75a6d87 100644
--- a/test/CodeGen/X86/tailcallbyval64.ll
+++ b/test/CodeGen/X86/tailcallbyval64.ll
@@ -3,7 +3,7 @@
 ; FIXME: Win64 does not support byval.
 
 ; Expect the entry point.
-; CHECK: tailcaller:
+; CHECK-LABEL: tailcaller:
 
 ; Expect 2 rep;movs because of tail call byval lowering.
 ; CHECK: rep;
diff --git a/test/CodeGen/X86/tailcallfp2.ll b/test/CodeGen/X86/tailcallfp2.ll
index 04c4e95..9ef0d27 100644
--- a/test/CodeGen/X86/tailcallfp2.ll
+++ b/test/CodeGen/X86/tailcallfp2.ll
@@ -3,7 +3,7 @@
 declare i32 @putchar(i32)
 
 define fastcc i32 @checktail(i32 %x, i32* %f, i32 %g) nounwind {
-; CHECK: checktail:
+; CHECK-LABEL: checktail:
         %tmp1 = icmp sgt i32 %x, 0
         br i1 %tmp1, label %if-then, label %if-else
 
diff --git a/test/CodeGen/X86/test-shrink.ll b/test/CodeGen/X86/test-shrink.ll
index 5bc28ec..c9b76c8 100644
--- a/test/CodeGen/X86/test-shrink.ll
+++ b/test/CodeGen/X86/test-shrink.ll
@@ -2,10 +2,10 @@
 ; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s --check-prefix=CHECK-64
 ; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32
 
-; CHECK-64: g64xh:
+; CHECK-64-LABEL: g64xh:
 ; CHECK-64:   testb $8, {{%ah|%ch}}
 ; CHECK-64:   ret
-; CHECK-32: g64xh:
+; CHECK-32-LABEL: g64xh:
 ; CHECK-32:   testb $8, %ah
 ; CHECK-32:   ret
 define void @g64xh(i64 inreg %x) nounwind {
@@ -19,10 +19,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g64xl:
+; CHECK-64-LABEL: g64xl:
 ; CHECK-64:   testb $8, [[A0L:%dil|%cl]]
 ; CHECK-64:   ret
-; CHECK-32: g64xl:
+; CHECK-32-LABEL: g64xl:
 ; CHECK-32:   testb $8, %al
 ; CHECK-32:   ret
 define void @g64xl(i64 inreg %x) nounwind {
@@ -36,10 +36,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g32xh:
+; CHECK-64-LABEL: g32xh:
 ; CHECK-64:   testb $8, {{%ah|%ch}}
 ; CHECK-64:   ret
-; CHECK-32: g32xh:
+; CHECK-32-LABEL: g32xh:
 ; CHECK-32:   testb $8, %ah
 ; CHECK-32:   ret
 define void @g32xh(i32 inreg %x) nounwind {
@@ -53,10 +53,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g32xl:
+; CHECK-64-LABEL: g32xl:
 ; CHECK-64:   testb $8, [[A0L]]
 ; CHECK-64:   ret
-; CHECK-32: g32xl:
+; CHECK-32-LABEL: g32xl:
 ; CHECK-32:   testb $8, %al
 ; CHECK-32:   ret
 define void @g32xl(i32 inreg %x) nounwind {
@@ -70,10 +70,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g16xh:
+; CHECK-64-LABEL: g16xh:
 ; CHECK-64:   testb $8, {{%ah|%ch}}
 ; CHECK-64:   ret
-; CHECK-32: g16xh:
+; CHECK-32-LABEL: g16xh:
 ; CHECK-32:   testb $8, %ah
 ; CHECK-32:   ret
 define void @g16xh(i16 inreg %x) nounwind {
@@ -87,10 +87,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g16xl:
+; CHECK-64-LABEL: g16xl:
 ; CHECK-64:   testb $8, [[A0L]]
 ; CHECK-64:   ret
-; CHECK-32: g16xl:
+; CHECK-32-LABEL: g16xl:
 ; CHECK-32:   testb $8, %al
 ; CHECK-32:   ret
 define void @g16xl(i16 inreg %x) nounwind {
@@ -104,10 +104,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g64x16:
+; CHECK-64-LABEL: g64x16:
 ; CHECK-64:   testw $-32640, %[[A0W:di|cx]]
 ; CHECK-64:   ret
-; CHECK-32: g64x16:
+; CHECK-32-LABEL: g64x16:
 ; CHECK-32:   testw $-32640, %ax
 ; CHECK-32:   ret
 define void @g64x16(i64 inreg %x) nounwind {
@@ -121,10 +121,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g32x16:
+; CHECK-64-LABEL: g32x16:
 ; CHECK-64:   testw $-32640, %[[A0W]]
 ; CHECK-64:   ret
-; CHECK-32: g32x16:
+; CHECK-32-LABEL: g32x16:
 ; CHECK-32:   testw $-32640, %ax
 ; CHECK-32:   ret
 define void @g32x16(i32 inreg %x) nounwind {
@@ -138,10 +138,10 @@ yes:
 no:
   ret void
 }
-; CHECK-64: g64x32:
+; CHECK-64-LABEL: g64x32:
 ; CHECK-64:   testl $268468352, %e[[A0W]]
 ; CHECK-64:   ret
-; CHECK-32: g64x32:
+; CHECK-32-LABEL: g64x32:
 ; CHECK-32:   testl $268468352, %eax
 ; CHECK-32:   ret
 define void @g64x32(i64 inreg %x) nounwind {
diff --git a/test/CodeGen/X86/testl-commute.ll b/test/CodeGen/X86/testl-commute.ll
index 0e6f636..bf6debf 100644
--- a/test/CodeGen/X86/testl-commute.ll
+++ b/test/CodeGen/X86/testl-commute.ll
@@ -7,7 +7,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-apple-darwin7"
 
 define i32 @test(i32* %P, i32* %G) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: ret
 ; CHECK: testl (%{{.*}}), %{{.*}}
 ; CHECK: ret
@@ -28,7 +28,7 @@ bb1:		; preds = %entry
 }
 
 define i32 @test2(i32* %P, i32* %G) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK-NOT: ret
 ; CHECK: testl (%{{.*}}), %{{.*}}
 ; CHECK: ret
@@ -49,7 +49,7 @@ bb1:		; preds = %entry
 }
 
 define i32 @test3(i32* %P, i32* %G) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK-NOT: ret
 ; CHECK: testl (%{{.*}}), %{{.*}}
 ; CHECK: ret
diff --git a/test/CodeGen/X86/this-return-64.ll b/test/CodeGen/X86/this-return-64.ll
index 2b26a89..4e6be71 100644
--- a/test/CodeGen/X86/this-return-64.ll
+++ b/test/CodeGen/X86/this-return-64.ll
@@ -14,7 +14,7 @@ declare %struct.B* @B_ctor_nothisret(%struct.B*, i32)
 
 define %struct.C* @C_ctor(%struct.C* %this, i32 %y) {
 entry:
-; CHECK: C_ctor:
+; CHECK-LABEL: C_ctor:
 ; CHECK: jmp     B_ctor                  # TAILCALL
   %0 = getelementptr inbounds %struct.C* %this, i64 0, i32 0
   %call = tail call %struct.B* @B_ctor(%struct.B* %0, i32 %y)
@@ -23,7 +23,7 @@ entry:
 
 define %struct.C* @C_ctor_nothisret(%struct.C* %this, i32 %y) {
 entry:
-; CHECK: C_ctor_nothisret:
+; CHECK-LABEL: C_ctor_nothisret:
 ; CHECK-NOT: jmp     B_ctor_nothisret
   %0 = getelementptr inbounds %struct.C* %this, i64 0, i32 0
   %call = tail call %struct.B* @B_ctor_nothisret(%struct.B* %0, i32 %y)
@@ -32,7 +32,7 @@ entry:
 
 define %struct.D* @D_ctor(%struct.D* %this, i32 %y) {
 entry:
-; CHECK: D_ctor:
+; CHECK-LABEL: D_ctor:
 ; CHECK: movq    %rcx, [[SAVETHIS:%r[0-9a-z]+]]
 ; CHECK: callq   A_ctor
 ; CHECK: movq    [[SAVETHIS]], %rcx
@@ -48,7 +48,7 @@ entry:
 
 define %struct.D* @D_ctor_nothisret(%struct.D* %this, i32 %y) {
 entry:
-; CHECK: D_ctor_nothisret:
+; CHECK-LABEL: D_ctor_nothisret:
 ; CHECK: movq    %rcx, [[SAVETHIS:%r[0-9a-z]+]]
 ; CHECK: callq   A_ctor_nothisret
 ; CHECK: movq    [[SAVETHIS]], %rcx
@@ -64,7 +64,7 @@ entry:
 
 define %struct.E* @E_ctor(%struct.E* %this, i32 %x) {
 entry:
-; CHECK: E_ctor:
+; CHECK-LABEL: E_ctor:
 ; CHECK: movq    %rcx, [[SAVETHIS:%r[0-9a-z]+]]
 ; CHECK: callq   B_ctor
 ; CHECK: movq    [[SAVETHIS]], %rcx
@@ -77,7 +77,7 @@ entry:
 
 define %struct.E* @E_ctor_nothisret(%struct.E* %this, i32 %x) {
 entry:
-; CHECK: E_ctor_nothisret:
+; CHECK-LABEL: E_ctor_nothisret:
 ; CHECK: movq    %rcx, [[SAVETHIS:%r[0-9a-z]+]]
 ; CHECK: callq   B_ctor_nothisret
 ; CHECK: movq    [[SAVETHIS]], %rcx
diff --git a/test/CodeGen/X86/tls-local-dynamic.ll b/test/CodeGen/X86/tls-local-dynamic.ll
index c5fd16b..4841e52 100644
--- a/test/CodeGen/X86/tls-local-dynamic.ll
+++ b/test/CodeGen/X86/tls-local-dynamic.ll
@@ -10,7 +10,7 @@ entry:
   ret i32* @x
 ; FIXME: This function uses a single thread-local variable,
 ; so we might want to fall back to general-dynamic here.
-; CHECK:       get_x:
+; CHECK-LABEL:       get_x:
 ; CHECK:       leaq x@TLSLD(%rip), %rdi
 ; CHECK-NEXT:  callq __tls_get_addr@PLT
 ; CHECK:       x@DTPOFF
@@ -26,7 +26,7 @@ entry:
   %cmp = icmp eq i32 %i, 1
   br i1 %cmp, label %return, label %if.else
 ; This bb does not access TLS, so should not call __tls_get_addr.
-; CHECK:       f:
+; CHECK-LABEL:       f:
 ; CHECK-NOT:   __tls_get_addr
 ; CHECK:       je
 
diff --git a/test/CodeGen/X86/tls-models.ll b/test/CodeGen/X86/tls-models.ll
index 7c527e2..8e3e958 100644
--- a/test/CodeGen/X86/tls-models.ll
+++ b/test/CodeGen/X86/tls-models.ll
@@ -25,15 +25,15 @@ entry:
   ret i32* @external_gd
 
   ; Non-PIC code can use initial-exec, PIC code has to use general dynamic.
-  ; X64:     f1:
+  ; X64-LABEL:     f1:
   ; X64:     external_gd@GOTTPOFF
-  ; X32:     f1:
+  ; X32-LABEL:     f1:
   ; X32:     external_gd@INDNTPOFF
-  ; X64_PIC: f1:
+  ; X64_PIC-LABEL: f1:
   ; X64_PIC: external_gd@TLSGD
-  ; X32_PIC: f1:
+  ; X32_PIC-LABEL: f1:
   ; X32_PIC: external_gd@TLSGD
-  ; DARWIN:  f1:
+  ; DARWIN-LABEL:  f1:
   ; DARWIN:  _external_gd@TLVP
 }
 
@@ -42,15 +42,15 @@ entry:
   ret i32* @internal_gd
 
   ; Non-PIC code can use local exec, PIC code can use local dynamic.
-  ; X64:     f2:
+  ; X64-LABEL:     f2:
   ; X64:     internal_gd@TPOFF
-  ; X32:     f2:
+  ; X32-LABEL:     f2:
   ; X32:     internal_gd@NTPOFF
-  ; X64_PIC: f2:
+  ; X64_PIC-LABEL: f2:
   ; X64_PIC: internal_gd@TLSLD
-  ; X32_PIC: f2:
+  ; X32_PIC-LABEL: f2:
   ; X32_PIC: internal_gd@TLSLDM
-  ; DARWIN:  f2:
+  ; DARWIN-LABEL:  f2:
   ; DARWIN:  _internal_gd@TLVP
 }
 
@@ -62,15 +62,15 @@ entry:
   ret i32* @external_ld
 
   ; Non-PIC code can use initial exec, PIC code use local dynamic as specified.
-  ; X64:     f3:
+  ; X64-LABEL:     f3:
   ; X64:     external_ld@GOTTPOFF
-  ; X32:     f3:
+  ; X32-LABEL:     f3:
   ; X32:     external_ld@INDNTPOFF
-  ; X64_PIC: f3:
+  ; X64_PIC-LABEL: f3:
   ; X64_PIC: external_ld@TLSLD
-  ; X32_PIC: f3:
+  ; X32_PIC-LABEL: f3:
   ; X32_PIC: external_ld@TLSLDM
-  ; DARWIN:  f3:
+  ; DARWIN-LABEL:  f3:
   ; DARWIN:  _external_ld@TLVP
 }
 
@@ -79,15 +79,15 @@ entry:
   ret i32* @internal_ld
 
   ; Non-PIC code can use local exec, PIC code can use local dynamic.
-  ; X64:     f4:
+  ; X64-LABEL:     f4:
   ; X64:     internal_ld@TPOFF
-  ; X32:     f4:
+  ; X32-LABEL:     f4:
   ; X32:     internal_ld@NTPOFF
-  ; X64_PIC: f4:
+  ; X64_PIC-LABEL: f4:
   ; X64_PIC: internal_ld@TLSLD
-  ; X32_PIC: f4:
+  ; X32_PIC-LABEL: f4:
   ; X32_PIC: internal_ld@TLSLDM
-  ; DARWIN:  f4:
+  ; DARWIN-LABEL:  f4:
   ; DARWIN:  _internal_ld@TLVP
 }
 
@@ -99,15 +99,15 @@ entry:
   ret i32* @external_ie
 
   ; Non-PIC and PIC code will use initial exec as specified.
-  ; X64:     f5:
+  ; X64-LABEL:     f5:
   ; X64:     external_ie@GOTTPOFF
-  ; X32:     f5:
+  ; X32-LABEL:     f5:
   ; X32:     external_ie@INDNTPOFF
-  ; X64_PIC: f5:
+  ; X64_PIC-LABEL: f5:
   ; X64_PIC: external_ie@GOTTPOFF
-  ; X32_PIC: f5:
+  ; X32_PIC-LABEL: f5:
   ; X32_PIC: external_ie@GOTNTPOFF
-  ; DARWIN:  f5:
+  ; DARWIN-LABEL:  f5:
   ; DARWIN:  _external_ie@TLVP
 }
 
@@ -116,15 +116,15 @@ entry:
   ret i32* @internal_ie
 
   ; Non-PIC code can use local exec, PIC code use initial exec as specified.
-  ; X64:     f6:
+  ; X64-LABEL:     f6:
   ; X64:     internal_ie@TPOFF
-  ; X32:     f6:
+  ; X32-LABEL:     f6:
   ; X32:     internal_ie@NTPOFF
-  ; X64_PIC: f6:
+  ; X64_PIC-LABEL: f6:
   ; X64_PIC: internal_ie@GOTTPOFF
-  ; X32_PIC: f6:
+  ; X32_PIC-LABEL: f6:
   ; X32_PIC: internal_ie@GOTNTPOFF
-  ; DARWIN:  f6:
+  ; DARWIN-LABEL:  f6:
   ; DARWIN:  _internal_ie@TLVP
 }
 
@@ -136,15 +136,15 @@ entry:
   ret i32* @external_le
 
   ; Non-PIC and PIC code will use local exec as specified.
-  ; X64:     f7:
+  ; X64-LABEL:     f7:
   ; X64:     external_le@TPOFF
-  ; X32:     f7:
+  ; X32-LABEL:     f7:
   ; X32:     external_le@NTPOFF
-  ; X64_PIC: f7:
+  ; X64_PIC-LABEL: f7:
   ; X64_PIC: external_le@TPOFF
-  ; X32_PIC: f7:
+  ; X32_PIC-LABEL: f7:
   ; X32_PIC: external_le@NTPOFF
-  ; DARWIN:  f7:
+  ; DARWIN-LABEL:  f7:
   ; DARWIN:  _external_le@TLVP
 }
 
@@ -153,14 +153,14 @@ entry:
   ret i32* @internal_le
 
   ; Non-PIC and PIC code will use local exec as specified.
-  ; X64:     f8:
+  ; X64-LABEL:     f8:
   ; X64:     internal_le@TPOFF
-  ; X32:     f8:
+  ; X32-LABEL:     f8:
   ; X32:     internal_le@NTPOFF
-  ; X64_PIC: f8:
+  ; X64_PIC-LABEL: f8:
   ; X64_PIC: internal_le@TPOFF
-  ; X32_PIC: f8:
+  ; X32_PIC-LABEL: f8:
   ; X32_PIC: internal_le@NTPOFF
-  ; DARWIN:  f8:
+  ; DARWIN-LABEL:  f8:
   ; DARWIN:  _internal_le@TLVP
 }
diff --git a/test/CodeGen/X86/tls-pic.ll b/test/CodeGen/X86/tls-pic.ll
index b823f0a..0c79da6 100644
--- a/test/CodeGen/X86/tls-pic.ll
+++ b/test/CodeGen/X86/tls-pic.ll
@@ -11,11 +11,11 @@ entry:
 	ret i32 %tmp1
 }
 
-; X32: f1:
+; X32-LABEL: f1:
 ; X32:   leal i@TLSGD(,%ebx), %eax
 ; X32:   calll ___tls_get_addr@PLT
 
-; X64: f1:
+; X64-LABEL: f1:
 ; X64:   leaq i@TLSGD(%rip), %rdi
 ; X64:   callq __tls_get_addr@PLT
 
@@ -27,11 +27,11 @@ entry:
 	ret i32* @i
 }
 
-; X32: f2:
+; X32-LABEL: f2:
 ; X32:   leal i@TLSGD(,%ebx), %eax
 ; X32:   calll ___tls_get_addr@PLT
 
-; X64: f2:
+; X64-LABEL: f2:
 ; X64:   leaq i@TLSGD(%rip), %rdi
 ; X64:   callq __tls_get_addr@PLT
 
@@ -43,11 +43,11 @@ entry:
 	ret i32 %tmp1
 }
 
-; X32: f3:
+; X32-LABEL: f3:
 ; X32:   leal	i@TLSGD(,%ebx), %eax
 ; X32:   calll ___tls_get_addr@PLT
 
-; X64: f3:
+; X64-LABEL: f3:
 ; X64:   leaq i@TLSGD(%rip), %rdi
 ; X64:   callq __tls_get_addr@PLT
 
@@ -57,11 +57,11 @@ entry:
 	ret i32* @i
 }
 
-; X32: f4:
+; X32-LABEL: f4:
 ; X32:   leal	i@TLSGD(,%ebx), %eax
 ; X32:   calll ___tls_get_addr@PLT
 
-; X64: f4:
+; X64-LABEL: f4:
 ; X64:   leaq i@TLSGD(%rip), %rdi
 ; X64:   callq __tls_get_addr@PLT
 
@@ -74,13 +74,13 @@ entry:
 	ret i32 %add
 }
 
-; X32:    f5:
+; X32-LABEL:    f5:
 ; X32:      leal {{[jk]}}@TLSLDM(%ebx)
 ; X32: calll ___tls_get_addr@PLT
 ; X32: movl {{[jk]}}@DTPOFF(%e
 ; X32: addl {{[jk]}}@DTPOFF(%e
 
-; X64:    f5:
+; X64-LABEL:    f5:
 ; X64:      leaq {{[jk]}}@TLSLD(%rip), %rdi
 ; X64: callq	__tls_get_addr@PLT
 ; X64: movl {{[jk]}}@DTPOFF(%r
diff --git a/test/CodeGen/X86/tls-pie.ll b/test/CodeGen/X86/tls-pie.ll
index 3fca9f5..d1e09c2 100644
--- a/test/CodeGen/X86/tls-pie.ll
+++ b/test/CodeGen/X86/tls-pie.ll
@@ -7,10 +7,10 @@
 @i2 = external thread_local global i32
 
 define i32 @f1() {
-; X32: f1:
+; X32-LABEL: f1:
 ; X32:      movl %gs:i@NTPOFF, %eax
 ; X32-NEXT: ret
-; X64: f1:
+; X64-LABEL: f1:
 ; X64:      movl %fs:i@TPOFF, %eax
 ; X64-NEXT: ret
 
@@ -20,11 +20,11 @@ entry:
 }
 
 define i32* @f2() {
-; X32: f2:
+; X32-LABEL: f2:
 ; X32:      movl %gs:0, %eax
 ; X32-NEXT: leal i@NTPOFF(%eax), %eax
 ; X32-NEXT: ret
-; X64: f2:
+; X64-LABEL: f2:
 ; X64:      movq %fs:0, %rax
 ; X64-NEXT: leaq i@TPOFF(%rax), %rax
 ; X64-NEXT: ret
@@ -34,7 +34,7 @@ entry:
 }
 
 define i32 @f3() {
-; X32: f3:
+; X32-LABEL: f3:
 ; X32:      calll .L{{[0-9]+}}$pb
 ; X32-NEXT: .L{{[0-9]+}}$pb:
 ; X32-NEXT: popl %eax
@@ -43,7 +43,7 @@ define i32 @f3() {
 ; X32-NEXT: movl i2@GOTNTPOFF(%eax), %eax
 ; X32-NEXT: movl %gs:(%eax), %eax
 ; X32-NEXT: ret
-; X64: f3:
+; X64-LABEL: f3:
 ; X64:      movq i2@GOTTPOFF(%rip), %rax
 ; X64-NEXT: movl %fs:(%rax), %eax
 ; X64-NEXT: ret
@@ -54,7 +54,7 @@ entry:
 }
 
 define i32* @f4() {
-; X32: f4:
+; X32-LABEL: f4:
 ; X32:      calll .L{{[0-9]+}}$pb
 ; X32-NEXT: .L{{[0-9]+}}$pb:
 ; X32-NEXT: popl %ecx
@@ -63,7 +63,7 @@ define i32* @f4() {
 ; X32-NEXT: movl %gs:0, %eax
 ; X32-NEXT: addl i2@GOTNTPOFF(%ecx), %eax
 ; X32-NEXT: ret
-; X64: f4:
+; X64-LABEL: f4:
 ; X64:      movq %fs:0, %rax
 ; X64-NEXT: addq i2@GOTTPOFF(%rip), %rax
 ; X64-NEXT: ret
diff --git a/test/CodeGen/X86/tls.ll b/test/CodeGen/X86/tls.ll
index 8cdecd8..24284e5 100644
--- a/test/CodeGen/X86/tls.ll
+++ b/test/CodeGen/X86/tls.ll
@@ -12,19 +12,19 @@
 @b1 = thread_local global i8 0
 
 define i32 @f1() {
-; X32_LINUX: f1:
+; X32_LINUX-LABEL: f1:
 ; X32_LINUX:      movl %gs:i1@NTPOFF, %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f1:
+; X64_LINUX-LABEL: f1:
 ; X64_LINUX:      movl %fs:i1@TPOFF, %eax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f1:
+; X32_WIN-LABEL: f1:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: movl _i1@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f1:
+; X64_WIN-LABEL: f1:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -37,21 +37,21 @@ entry:
 }
 
 define i32* @f2() {
-; X32_LINUX: f2:
+; X32_LINUX-LABEL: f2:
 ; X32_LINUX:      movl %gs:0, %eax
 ; X32_LINUX-NEXT: leal i1@NTPOFF(%eax), %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f2:
+; X64_LINUX-LABEL: f2:
 ; X64_LINUX:      movq %fs:0, %rax
 ; X64_LINUX-NEXT: leaq i1@TPOFF(%rax), %rax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f2:
+; X32_WIN-LABEL: f2:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: leal _i1@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f2:
+; X64_WIN-LABEL: f2:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -63,21 +63,21 @@ entry:
 }
 
 define i32 @f3() nounwind {
-; X32_LINUX: f3:
+; X32_LINUX-LABEL: f3:
 ; X32_LINUX:      movl i2@INDNTPOFF, %eax
 ; X32_LINUX-NEXT: movl %gs:(%eax), %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f3:
+; X64_LINUX-LABEL: f3:
 ; X64_LINUX:      movq i2@GOTTPOFF(%rip), %rax
 ; X64_LINUX-NEXT: movl %fs:(%rax), %eax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f3:
+; X32_WIN-LABEL: f3:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: movl _i2@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f3:
+; X64_WIN-LABEL: f3:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -90,21 +90,21 @@ entry:
 }
 
 define i32* @f4() {
-; X32_LINUX: f4:
+; X32_LINUX-LABEL: f4:
 ; X32_LINUX:      movl %gs:0, %eax
 ; X32_LINUX-NEXT: addl i2@INDNTPOFF, %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f4:
+; X64_LINUX-LABEL: f4:
 ; X64_LINUX:      movq %fs:0, %rax
 ; X64_LINUX-NEXT: addq i2@GOTTPOFF(%rip), %rax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f4:
+; X32_WIN-LABEL: f4:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: leal _i2@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f4:
+; X64_WIN-LABEL: f4:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -116,19 +116,19 @@ entry:
 }
 
 define i32 @f5() nounwind {
-; X32_LINUX: f5:
+; X32_LINUX-LABEL: f5:
 ; X32_LINUX:      movl %gs:i3@NTPOFF, %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f5:
+; X64_LINUX-LABEL: f5:
 ; X64_LINUX:      movl %fs:i3@TPOFF, %eax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f5:
+; X32_WIN-LABEL: f5:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: movl _i3@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f5:
+; X64_WIN-LABEL: f5:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -141,21 +141,21 @@ entry:
 }
 
 define i32* @f6() {
-; X32_LINUX: f6:
+; X32_LINUX-LABEL: f6:
 ; X32_LINUX:      movl %gs:0, %eax
 ; X32_LINUX-NEXT: leal i3@NTPOFF(%eax), %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f6:
+; X64_LINUX-LABEL: f6:
 ; X64_LINUX:      movq %fs:0, %rax
 ; X64_LINUX-NEXT: leaq i3@TPOFF(%rax), %rax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f6:
+; X32_WIN-LABEL: f6:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: leal _i3@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f6:
+; X64_WIN-LABEL: f6:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -167,10 +167,10 @@ entry:
 }
 
 define i32 @f7() {
-; X32_LINUX: f7:
+; X32_LINUX-LABEL: f7:
 ; X32_LINUX:      movl %gs:i4@NTPOFF, %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f7:
+; X64_LINUX-LABEL: f7:
 ; X64_LINUX:      movl %fs:i4@TPOFF, %eax
 ; X64_LINUX-NEXT: ret
 
@@ -180,11 +180,11 @@ entry:
 }
 
 define i32* @f8() {
-; X32_LINUX: f8:
+; X32_LINUX-LABEL: f8:
 ; X32_LINUX:      movl %gs:0, %eax
 ; X32_LINUX-NEXT: leal i4@NTPOFF(%eax), %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f8:
+; X64_LINUX-LABEL: f8:
 ; X64_LINUX:      movq %fs:0, %rax
 ; X64_LINUX-NEXT: leaq i4@TPOFF(%rax), %rax
 ; X64_LINUX-NEXT: ret
@@ -194,10 +194,10 @@ entry:
 }
 
 define i32 @f9() {
-; X32_LINUX: f9:
+; X32_LINUX-LABEL: f9:
 ; X32_LINUX:      movl %gs:i5@NTPOFF, %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f9:
+; X64_LINUX-LABEL: f9:
 ; X64_LINUX:      movl %fs:i5@TPOFF, %eax
 ; X64_LINUX-NEXT: ret
 
@@ -207,11 +207,11 @@ entry:
 }
 
 define i32* @f10() {
-; X32_LINUX: f10:
+; X32_LINUX-LABEL: f10:
 ; X32_LINUX:      movl %gs:0, %eax
 ; X32_LINUX-NEXT: leal i5@NTPOFF(%eax), %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f10:
+; X64_LINUX-LABEL: f10:
 ; X64_LINUX:      movq %fs:0, %rax
 ; X64_LINUX-NEXT: leaq i5@TPOFF(%rax), %rax
 ; X64_LINUX-NEXT: ret
@@ -221,23 +221,23 @@ entry:
 }
 
 define i16 @f11() {
-; X32_LINUX: f11:
+; X32_LINUX-LABEL: f11:
 ; X32_LINUX:      movzwl %gs:s1@NTPOFF, %eax
 ; Why is this kill line here, but no where else?
 ; X32_LINUX-NEXT: # kill
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f11:
+; X64_LINUX-LABEL: f11:
 ; X64_LINUX:      movzwl %fs:s1@TPOFF, %eax
 ; X64_LINUX-NEXT: # kill
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f11:
+; X32_WIN-LABEL: f11:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: movzwl _s1@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: # kill
 ; X32_WIN-NEXT: ret
-; X64_WIN: f11:
+; X64_WIN-LABEL: f11:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -251,19 +251,19 @@ entry:
 }
 
 define i32 @f12() {
-; X32_LINUX: f12:
+; X32_LINUX-LABEL: f12:
 ; X32_LINUX:      movswl %gs:s1@NTPOFF, %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f12:
+; X64_LINUX-LABEL: f12:
 ; X64_LINUX:      movswl %fs:s1@TPOFF, %eax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f12:
+; X32_WIN-LABEL: f12:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: movswl _s1@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f12:
+; X64_WIN-LABEL: f12:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -277,19 +277,19 @@ entry:
 }
 
 define i8 @f13() {
-; X32_LINUX: f13:
+; X32_LINUX-LABEL: f13:
 ; X32_LINUX:      movb %gs:b1@NTPOFF, %al
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f13:
+; X64_LINUX-LABEL: f13:
 ; X64_LINUX:      movb %fs:b1@TPOFF, %al
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f13:
+; X32_WIN-LABEL: f13:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: movb _b1@SECREL32(%eax), %al
 ; X32_WIN-NEXT: ret
-; X64_WIN: f13:
+; X64_WIN-LABEL: f13:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@@ -302,19 +302,19 @@ entry:
 }
 
 define i32 @f14() {
-; X32_LINUX: f14:
+; X32_LINUX-LABEL: f14:
 ; X32_LINUX:      movsbl %gs:b1@NTPOFF, %eax
 ; X32_LINUX-NEXT: ret
-; X64_LINUX: f14:
+; X64_LINUX-LABEL: f14:
 ; X64_LINUX:      movsbl %fs:b1@TPOFF, %eax
 ; X64_LINUX-NEXT: ret
-; X32_WIN: f14:
+; X32_WIN-LABEL: f14:
 ; X32_WIN:      movl __tls_index, %eax
 ; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
 ; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
 ; X32_WIN-NEXT: movsbl _b1@SECREL32(%eax), %eax
 ; X32_WIN-NEXT: ret
-; X64_WIN: f14:
+; X64_WIN-LABEL: f14:
 ; X64_WIN:      movl _tls_index(%rip), %eax
 ; X64_WIN-NEXT: movq %gs:88, %rcx
 ; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
diff --git a/test/CodeGen/X86/tlv-1.ll b/test/CodeGen/X86/tlv-1.ll
index 92dac30..66e2f81 100644
--- a/test/CodeGen/X86/tlv-1.ll
+++ b/test/CodeGen/X86/tlv-1.ll
@@ -5,7 +5,7 @@
 @c = external thread_local global %struct.A, align 4
 
 define void @main() nounwind ssp {
-; CHECK: main:
+; CHECK-LABEL: main:
 entry:
   call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds (%struct.A* @c, i32 0, i32 0, i32 0), i8 0, i64 60, i32 1, i1 false)
   unreachable  
@@ -18,7 +18,7 @@ entry:
 ; rdar://10291355
 define i32 @test() nounwind readonly ssp {
 entry:
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: movq _a@TLVP(%rip),
 ; CHECK: callq *
 ; CHECK: movl (%rax), [[REGISTER:%[a-z]+]]
diff --git a/test/CodeGen/X86/trap.ll b/test/CodeGen/X86/trap.ll
index 3f44be0..149c667 100644
--- a/test/CodeGen/X86/trap.ll
+++ b/test/CodeGen/X86/trap.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
 
-; CHECK: test0:
+; CHECK-LABEL: test0:
 ; CHECK: ud2
 define i32 @test0() noreturn nounwind  {
 entry:
@@ -8,7 +8,7 @@ entry:
 	unreachable
 }
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: int3
 define i32 @test1() noreturn nounwind  {
 entry:
diff --git a/test/CodeGen/X86/trunc-ext-ld-st.ll b/test/CodeGen/X86/trunc-ext-ld-st.ll
index 1d22a18..408bdc8 100644
--- a/test/CodeGen/X86/trunc-ext-ld-st.ll
+++ b/test/CodeGen/X86/trunc-ext-ld-st.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mattr=+sse41 | FileCheck %s
 
-;CHECK: load_2_i8
+;CHECK-LABEL: load_2_i8:
 ; A single 16-bit load
 ;CHECK: pmovzxbq
 ;CHECK: paddq
@@ -16,7 +16,7 @@ define void @load_2_i8(<2 x i8>* %A)  {
    ret void
 } 
 
-;CHECK: load_2_i16
+;CHECK-LABEL: load_2_i16:
 ; Read 32-bits
 ;CHECK: pmovzxwq
 ;CHECK: paddq
@@ -30,7 +30,7 @@ define void @load_2_i16(<2 x i16>* %A)  {
    ret void
 } 
 
-;CHECK: load_2_i32
+;CHECK-LABEL: load_2_i32:
 ;CHECK: pmovzxdq
 ;CHECK: paddq
 ;CHECK: pshufd
@@ -42,7 +42,7 @@ define void @load_2_i32(<2 x i32>* %A)  {
    ret void
 } 
 
-;CHECK: load_4_i8
+;CHECK-LABEL: load_4_i8:
 ;CHECK: pmovzxbd
 ;CHECK: paddd
 ;CHECK: pshufb
@@ -54,7 +54,7 @@ define void @load_4_i8(<4 x i8>* %A)  {
    ret void
 } 
 
-;CHECK: load_4_i16
+;CHECK-LABEL: load_4_i16:
 ;CHECK: pmovzxwd
 ;CHECK: paddd
 ;CHECK: pshufb
@@ -66,7 +66,7 @@ define void @load_4_i16(<4 x i16>* %A)  {
    ret void
 } 
 
-;CHECK: load_8_i8
+;CHECK-LABEL: load_8_i8:
 ;CHECK: pmovzxbw
 ;CHECK: paddw
 ;CHECK: pshufb
diff --git a/test/CodeGen/X86/trunc-to-bool.ll b/test/CodeGen/X86/trunc-to-bool.ll
index 92b6859..3711cf1 100644
--- a/test/CodeGen/X86/trunc-to-bool.ll
+++ b/test/CodeGen/X86/trunc-to-bool.ll
@@ -7,7 +7,7 @@ define zeroext i1 @test1(i32 %X)  nounwind {
     %Y = trunc i32 %X to i1
     ret i1 %Y
 }
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: andl $1, %eax
 
 define i1 @test2(i32 %val, i32 %mask) nounwind {
@@ -21,7 +21,7 @@ ret_true:
 ret_false:
     ret i1 false
 }
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: btl %eax
 
 define i32 @test3(i8* %ptr) nounwind {
@@ -33,7 +33,7 @@ cond_true:
 cond_false:
     ret i32 42
 }
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: testb $1, (%eax)
 
 define i32 @test4(i8* %ptr) nounwind {
@@ -44,7 +44,7 @@ cond_true:
 cond_false:
     ret i32 42
 }
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: testb $1, 4(%esp)
 
 define i32 @test5(double %d) nounwind {
@@ -55,5 +55,5 @@ cond_true:
 cond_false:
     ret i32 42
 }
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: testb $1
diff --git a/test/CodeGen/X86/twoaddr-lea.ll b/test/CodeGen/X86/twoaddr-lea.ll
index 9d58019..b5ca027 100644
--- a/test/CodeGen/X86/twoaddr-lea.ll
+++ b/test/CodeGen/X86/twoaddr-lea.ll
@@ -10,7 +10,7 @@
 @G = external global i32
 
 define i32 @test1(i32 %X) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: mov
 ; CHECK: leal 1(%rdi)
         %Z = add i32 %X, 1
@@ -23,7 +23,7 @@ define i32 @test1(i32 %X) nounwind {
 ; commutted (which would require inserting a copy).
 define i32 @test2(i32 inreg %a, i32 inreg %b, i32 %c, i32 %d) nounwind {
 entry:
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: leal
 ; CHECK-NOT: leal
 ; CHECK-NOT: mov
@@ -38,7 +38,7 @@ entry:
 ; rdar://9002648
 define i64 @test3(i64 %x) nounwind readnone ssp {
 entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: leaq (%rdi,%rdi), %rax
 ; CHECK-NOT: addq
 ; CHECK-NEXT: ret
diff --git a/test/CodeGen/X86/umul-with-overflow.ll b/test/CodeGen/X86/umul-with-overflow.ll
index e5858de..ba5a790 100644
--- a/test/CodeGen/X86/umul-with-overflow.ll
+++ b/test/CodeGen/X86/umul-with-overflow.ll
@@ -6,7 +6,7 @@ define zeroext i1 @a(i32 %x)  nounwind {
   %obil = extractvalue {i32, i1} %res, 1
   ret i1 %obil
   
-; CHECK: a:
+; CHECK-LABEL: a:
 ; CHECK: mull
 ; CHECK: seto %al
 ; CHECK: movzbl	%al, %eax
@@ -19,7 +19,7 @@ entry:
 	%tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 2)
 	%tmp2 = extractvalue { i32, i1 } %tmp1, 0
 	ret i32 %tmp2
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: addl
 ; CHECK-NEXT: addl
 ; CHECK-NEXT: ret
@@ -31,7 +31,7 @@ entry:
 	%tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 4)
 	%tmp2 = extractvalue { i32, i1 } %tmp1, 0
 	ret i32 %tmp2
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: addl
 ; CHECK: mull
 ; CHECK-NEXT: ret
diff --git a/test/CodeGen/X86/unknown-location.ll b/test/CodeGen/X86/unknown-location.ll
index e02e3b5..2422de9 100644
--- a/test/CodeGen/X86/unknown-location.ll
+++ b/test/CodeGen/X86/unknown-location.ll
@@ -21,13 +21,14 @@ entry:
 !llvm.dbg.cu = !{!3}
 
 !0 = metadata !{i32 786689, metadata !1, metadata !"x", metadata !2, i32 1, metadata !6} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 1, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, i32, i32, i32)* @foo, null, null, null, i32 1} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786478, metadata !10, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", i32 1, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, i32, i32, i32)* @foo, null, null, null, i32 1} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !10} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786449, metadata !10, i32 12, metadata !"producer", i1 false, metadata !"", i32 0, null, null, metadata !9, null, metadata !""} ; [ DW_TAG_compile_unit ]
-!4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!3 = metadata !{i32 786449, metadata !10, i32 12, metadata !"producer", i1 false, metadata !"", i32 0, metadata !11, metadata !11, metadata !9, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!4 = metadata !{i32 786453, metadata !10, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{metadata !6}
-!6 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!7 = metadata !{i32 786443, metadata !1, i32 1, i32 30} ; [ DW_TAG_lexical_block ]
+!6 = metadata !{i32 786468, metadata !10, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!7 = metadata !{i32 786443, metadata !2, metadata !1, i32 1, i32 30, i32 0} ; [ DW_TAG_lexical_block ]
 !8 = metadata !{i32 4, i32 3, metadata !7, null}
 !9 = metadata !{metadata !1}
 !10 = metadata !{metadata !"test.c", metadata !"/dir"}
+!11 = metadata !{i32 0}
diff --git a/test/CodeGen/X86/unwind-init.ll b/test/CodeGen/X86/unwind-init.ll
new file mode 100644
index 0000000..d0915e2
--- /dev/null
+++ b/test/CodeGen/X86/unwind-init.ll
@@ -0,0 +1,36 @@
+; RUN: llc -mtriple=x86_64-unknown-linux < %s | FileCheck -check-prefix X8664 %s
+; RUN: llc -mtriple=i686-unknown-linux < %s | FileCheck -check-prefix X8632 %s
+; Check that all callee-saved registers are saved and restored in functions
+; that call __builtin_unwind_init(). This is its undocumented behavior in gcc,
+; and it is used in compiling libgcc_eh.
+; See also PR8541
+
+declare void @llvm.eh.unwind.init()
+
+define void @calls_unwind_init() {
+  call void @llvm.eh.unwind.init()
+  ret void
+}
+
+; X8664-LABEL: calls_unwind_init:
+; X8664: pushq %rbp
+; X8664: pushq %r15
+; X8664: pushq %r14
+; X8664: pushq %r13
+; X8664: pushq %r12
+; X8664: pushq %rbx
+; X8664: popq %rbx
+; X8664: popq %r12
+; X8664: popq %r13
+; X8664: popq %r14
+; X8664: popq %r15
+
+; X8632-LABEL: calls_unwind_init:
+; X8632: pushl %ebp
+; X8632: pushl %ebx
+; X8632: pushl %edi
+; X8632: pushl %esi
+; X8632: popl %esi
+; X8632: popl %edi
+; X8632: popl %ebx
+; X8632: popl %ebp
diff --git a/test/CodeGen/X86/use-add-flags.ll b/test/CodeGen/X86/use-add-flags.ll
index a0448ec..fd57f5c 100644
--- a/test/CodeGen/X86/use-add-flags.ll
+++ b/test/CodeGen/X86/use-add-flags.ll
@@ -6,7 +6,7 @@
 
 ; Use the flags on the add.
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ;     CHECK: addl
 ; CHECK-NOT: test
 ;     CHECK: cmovnsl
@@ -25,7 +25,7 @@ declare void @foo(i32)
 ; Don't use the flags result of the and here, since the and has no
 ; other use. A simple test is better.
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: testb   $16, {{%dil|%cl}}
 
 define void @test2(i32 %x) nounwind {
@@ -41,7 +41,7 @@ false:
 
 ; Do use the flags result of the and here, since the and has another use.
 
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ;      CHECK: andl    $16, %e
 ; CHECK-NEXT: jne
 
diff --git a/test/CodeGen/X86/v2f32.ll b/test/CodeGen/X86/v2f32.ll
index ba54833..f2bebf5 100644
--- a/test/CodeGen/X86/v2f32.ll
+++ b/test/CodeGen/X86/v2f32.ll
@@ -10,20 +10,20 @@ define void @test1(<2 x float> %Q, float *%P2) nounwind {
 
   store float %c, float* %P2
   ret void
-; X64: test1:
+; X64-LABEL: test1:
 ; X64-NEXT: pshufd	$1, %xmm0, %xmm1
 ; X64-NEXT: addss	%xmm0, %xmm1
 ; X64-NEXT: movss	%xmm1, (%rdi)
 ; X64-NEXT: ret
 
-; W64: test1:
+; W64-LABEL: test1:
 ; W64-NEXT: movdqa  (%rcx), %xmm0
 ; W64-NEXT: pshufd  $1, %xmm0, %xmm1
 ; W64-NEXT: addss   %xmm0, %xmm1
 ; W64-NEXT: movss   %xmm1, (%rdx)
 ; W64-NEXT: ret
 
-; X32: test1:
+; X32-LABEL: test1:
 ; X32-NEXT: pshufd	$1, %xmm0, %xmm1
 ; X32-NEXT: addss	%xmm0, %xmm1
 ; X32-NEXT: movl	4(%esp), %eax
@@ -36,16 +36,16 @@ define <2 x float> @test2(<2 x float> %Q, <2 x float> %R, <2 x float> *%P) nounw
   %Z = fadd <2 x float> %Q, %R
   ret <2 x float> %Z
   
-; X64: test2:
+; X64-LABEL: test2:
 ; X64-NEXT: addps	%xmm1, %xmm0
 ; X64-NEXT: ret
 
-; W64: test2:
+; W64-LABEL: test2:
 ; W64-NEXT: movaps  (%rcx), %xmm0
 ; W64-NEXT: addps   (%rdx), %xmm0
 ; W64-NEXT: ret
 
-; X32: test2:
+; X32-LABEL: test2:
 ; X32:      addps	%xmm1, %xmm0
 }
 
@@ -54,16 +54,16 @@ define <2 x float> @test3(<4 x float> %A) nounwind {
 	%B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
 	%C = fadd <2 x float> %B, %B
 	ret <2 x float> %C
-; X64: test3:
+; X64-LABEL: test3:
 ; X64-NEXT: addps	%xmm0, %xmm0
 ; X64-NEXT: ret
 
-; W64: test3:
+; W64-LABEL: test3:
 ; W64-NEXT: movaps  (%rcx), %xmm0
 ; W64-NEXT: addps   %xmm0, %xmm0
 ; W64-NEXT: ret
 
-; X32: test3:
+; X32-LABEL: test3:
 ; X32-NEXT: addps	%xmm0, %xmm0
 ; X32-NEXT: ret
 }
@@ -71,16 +71,16 @@ define <2 x float> @test3(<4 x float> %A) nounwind {
 define <2 x float> @test4(<2 x float> %A) nounwind {
 	%C = fadd <2 x float> %A, %A
 	ret <2 x float> %C
-; X64: test4:
+; X64-LABEL: test4:
 ; X64-NEXT: addps	%xmm0, %xmm0
 ; X64-NEXT: ret
 
-; W64: test4:
+; W64-LABEL: test4:
 ; W64-NEXT: movaps  (%rcx), %xmm0
 ; W64-NEXT: addps   %xmm0, %xmm0
 ; W64-NEXT: ret
 
-; X32: test4:
+; X32-LABEL: test4:
 ; X32-NEXT: addps	%xmm0, %xmm0
 ; X32-NEXT: ret
 }
@@ -95,18 +95,18 @@ BB:
 	%E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 	ret <4 x float> %E
         
-; X64: test5:
+; X64-LABEL: test5:
 ; X64-NEXT: addps	%xmm0, %xmm0
 ; X64-NEXT: addps	%xmm0, %xmm0
 ; X64-NEXT: ret
 
-; W64: test5:
+; W64-LABEL: test5:
 ; W64-NEXT: movaps  (%rcx), %xmm0
 ; W64-NEXT: addps   %xmm0, %xmm0
 ; W64-NEXT: addps   %xmm0, %xmm0
 ; W64-NEXT: ret
 
-; X32: test5:
+; X32-LABEL: test5:
 ; X32-NEXT: addps	%xmm0, %xmm0
 ; X32-NEXT: addps	%xmm0, %xmm0
 ; X32-NEXT: ret
diff --git a/test/CodeGen/X86/v8i1-masks.ll b/test/CodeGen/X86/v8i1-masks.ll
index 8cbfb5d..5da6e96 100644
--- a/test/CodeGen/X86/v8i1-masks.ll
+++ b/test/CodeGen/X86/v8i1-masks.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -o - < %s | FileCheck %s
 
-;CHECK: and_masks
+;CHECK-LABEL: and_masks:
 ;CHECK: vmovaps
 ;CHECK: vcmpltp
 ;CHECK: vcmpltp
diff --git a/test/CodeGen/X86/vec-sign.ll b/test/CodeGen/X86/vec-sign.ll
index 31b9c2e..b3d85fd 100644
--- a/test/CodeGen/X86/vec-sign.ll
+++ b/test/CodeGen/X86/vec-sign.ll
@@ -2,7 +2,7 @@
 
 define <4 x i32> @signd(<4 x i32> %a, <4 x i32> %b) nounwind {
 entry:
-; CHECK: signd:
+; CHECK-LABEL: signd:
 ; CHECK: psignd
 ; CHECK-NOT: sub
 ; CHECK: ret
@@ -17,7 +17,7 @@ entry:
 
 define <4 x i32> @blendvb(<4 x i32> %b, <4 x i32> %a, <4 x i32> %c) nounwind {
 entry:
-; CHECK: blendvb:
+; CHECK-LABEL: blendvb:
 ; CHECK: pblendvb
 ; CHECK: ret
   %b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
diff --git a/test/CodeGen/X86/vec_cast2.ll b/test/CodeGen/X86/vec_cast2.ll
index 08eb16f..5f6e7a8 100644
--- a/test/CodeGen/X86/vec_cast2.ll
+++ b/test/CodeGen/X86/vec_cast2.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=corei7-avx -mattr=+avx | FileCheck %s
 
-;CHECK: foo1_8
+;CHECK-LABEL: foo1_8:
 ;CHECK: vcvtdq2ps
 ;CHECK: ret
 define <8 x float> @foo1_8(<8 x i8> %src) {
@@ -8,7 +8,7 @@ define <8 x float> @foo1_8(<8 x i8> %src) {
   ret <8 x float> %res
 }
 
-;CHECK: foo1_4
+;CHECK-LABEL: foo1_4:
 ;CHECK: vcvtdq2ps
 ;CHECK: ret
 define <4 x float> @foo1_4(<4 x i8> %src) {
@@ -16,7 +16,7 @@ define <4 x float> @foo1_4(<4 x i8> %src) {
   ret <4 x float> %res
 }
 
-;CHECK: foo2_8
+;CHECK-LABEL: foo2_8:
 ;CHECK: vcvtdq2ps
 ;CHECK: ret
 define <8 x float> @foo2_8(<8 x i8> %src) {
@@ -24,7 +24,7 @@ define <8 x float> @foo2_8(<8 x i8> %src) {
   ret <8 x float> %res
 }
 
-;CHECK: foo2_4
+;CHECK-LABEL: foo2_4:
 ;CHECK: vcvtdq2ps
 ;CHECK: ret
 define <4 x float> @foo2_4(<4 x i8> %src) {
@@ -32,14 +32,14 @@ define <4 x float> @foo2_4(<4 x i8> %src) {
   ret <4 x float> %res
 }
 
-;CHECK: foo3_8
+;CHECK-LABEL: foo3_8:
 ;CHECK: vcvttps2dq
 ;CHECK: ret
 define <8 x i8> @foo3_8(<8 x float> %src) {
   %res = fptosi <8 x float> %src to <8 x i8>
   ret <8 x i8> %res
 }
-;CHECK: foo3_4
+;CHECK-LABEL: foo3_4:
 ;CHECK: vcvttps2dq
 ;CHECK: ret
 define <4 x i8> @foo3_4(<4 x float> %src) {
diff --git a/test/CodeGen/X86/vec_compare-sse4.ll b/test/CodeGen/X86/vec_compare-sse4.ll
index b4a4a4c..a08d9f5 100644
--- a/test/CodeGen/X86/vec_compare-sse4.ll
+++ b/test/CodeGen/X86/vec_compare-sse4.ll
@@ -3,13 +3,13 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s -check-prefix=SSE42
 
 define <2 x i64> @test1(<2 x i64> %A, <2 x i64> %B) nounwind {
-; SSE42: test1:
+; SSE42-LABEL: test1:
 ; SSE42: pcmpgtq
 ; SSE42: ret
-; SSE41: test1:
+; SSE41-LABEL: test1:
 ; SSE41-NOT: pcmpgtq
 ; SSE41: ret
-; SSE2: test1:
+; SSE2-LABEL: test1:
 ; SSE2-NOT: pcmpgtq
 ; SSE2: ret
 
@@ -19,13 +19,13 @@ define <2 x i64> @test1(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test2(<2 x i64> %A, <2 x i64> %B) nounwind {
-; SSE42: test2:
+; SSE42-LABEL: test2:
 ; SSE42: pcmpeqq
 ; SSE42: ret
-; SSE41: test2:
+; SSE41-LABEL: test2:
 ; SSE41: pcmpeqq
 ; SSE41: ret
-; SSE2: test2:
+; SSE2-LABEL: test2:
 ; SSE2-NOT: pcmpeqq
 ; SSE2: ret
 
diff --git a/test/CodeGen/X86/vec_compare.ll b/test/CodeGen/X86/vec_compare.ll
index fd5c234..365fe92 100644
--- a/test/CodeGen/X86/vec_compare.ll
+++ b/test/CodeGen/X86/vec_compare.ll
@@ -2,7 +2,7 @@
 
 
 define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: pcmpgtd
 ; CHECK: ret
 
@@ -12,7 +12,7 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
 }
 
 define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: pcmp
 ; CHECK: pcmp
 ; CHECK: pxor
@@ -23,7 +23,7 @@ define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
 }
 
 define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: pcmpgtd
 ; CHECK: movdqa
 ; CHECK: ret
@@ -33,7 +33,7 @@ define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind {
 }
 
 define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: movdqa
 ; CHECK: pcmpgtd
 ; CHECK: ret
@@ -43,7 +43,7 @@ define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind {
 }
 
 define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: pcmpeqd
 ; CHECK: pshufd $-79
 ; CHECK: pand
@@ -54,7 +54,7 @@ define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: pcmpeqd
 ; CHECK: pshufd $-79
 ; CHECK: pand
@@ -72,7 +72,7 @@ define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind {
 ; CHECK-NEXT: .long	0
 ; CHECK-NEXT: .long	2147483648
 ; CHECK-NEXT: .long	0
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]]
 ; CHECK: pxor [[CONSTREG]]
 ; CHECK: pxor [[CONSTREG]]
@@ -90,7 +90,7 @@ define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm0
@@ -107,7 +107,7 @@ define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm0
@@ -126,7 +126,7 @@ define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test10(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm1
@@ -150,7 +150,7 @@ define <2 x i64> @test11(<2 x i64> %A, <2 x i64> %B) nounwind {
 ; CHECK-NEXT: .long	2147483648
 ; CHECK-NEXT: .long	2147483648
 ; CHECK-NEXT: .long	2147483648
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]]
 ; CHECK: pxor [[CONSTREG]]
 ; CHECK: pxor [[CONSTREG]]
@@ -168,7 +168,7 @@ define <2 x i64> @test11(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test12(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm0
@@ -185,7 +185,7 @@ define <2 x i64> @test12(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test13(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test13:
+; CHECK-LABEL: test13:
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm0
@@ -204,7 +204,7 @@ define <2 x i64> @test13(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test14(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test14:
+; CHECK-LABEL: test14:
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm1
diff --git a/test/CodeGen/X86/vec_insert-2.ll b/test/CodeGen/X86/vec_insert-2.ll
index dee91fd..bfac1ba 100644
--- a/test/CodeGen/X86/vec_insert-2.ll
+++ b/test/CodeGen/X86/vec_insert-2.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | FileCheck --check-prefix=X64 %s
 
 define <4 x float> @t1(float %s, <4 x float> %tmp) nounwind {
-; X32: t1:
+; X32-LABEL: t1:
 ; X32: shufps $36
 ; X32: ret
 
@@ -11,7 +11,7 @@ define <4 x float> @t1(float %s, <4 x float> %tmp) nounwind {
 }
 
 define <4 x i32> @t2(i32 %s, <4 x i32> %tmp) nounwind {
-; X32: t2:
+; X32-LABEL: t2:
 ; X32: shufps $36
 ; X32: ret
 
@@ -20,11 +20,11 @@ define <4 x i32> @t2(i32 %s, <4 x i32> %tmp) nounwind {
 }
 
 define <2 x double> @t3(double %s, <2 x double> %tmp) nounwind {
-; X32: t3:
+; X32-LABEL: t3:
 ; X32: movhpd
 ; X32: ret
 
-; X64: t3:
+; X64-LABEL: t3:
 ; X64: unpcklpd
 ; X64: ret
 
@@ -33,7 +33,7 @@ define <2 x double> @t3(double %s, <2 x double> %tmp) nounwind {
 }
 
 define <8 x i16> @t4(i16 %s, <8 x i16> %tmp) nounwind {
-; X32: t4:
+; X32-LABEL: t4:
 ; X32: pinsrw
 ; X32: ret
 
diff --git a/test/CodeGen/X86/vec_insert-5.ll b/test/CodeGen/X86/vec_insert-5.ll
index bd4a06d..5cb9f69 100644
--- a/test/CodeGen/X86/vec_insert-5.ll
+++ b/test/CodeGen/X86/vec_insert-5.ll
@@ -9,7 +9,7 @@ define void  @t1(i32 %a, x86_mmx* %P) nounwind {
        store x86_mmx %tmp23, x86_mmx* %P
        ret void
 
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK-NOT: %mm
 ; CHECK: shll $12
 ; CHECK-NOT: %mm
@@ -20,7 +20,7 @@ define <4 x float> @t2(<4 x float>* %P) nounwind {
         %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 4, i32 4, i32 4, i32 0 >
         ret <4 x float> %tmp2
 
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: pslldq $12
 }
 
@@ -29,7 +29,7 @@ define <4 x float> @t3(<4 x float>* %P) nounwind {
         %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 2, i32 3, i32 4, i32 4 >
         ret <4 x float> %tmp2
 
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: psrldq $8
 }
 
@@ -38,7 +38,7 @@ define <4 x float> @t4(<4 x float>* %P) nounwind {
         %tmp2 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp1, <4 x i32> < i32 7, i32 0, i32 0, i32 0 >
         ret <4 x float> %tmp2
 
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: psrldq $12
 }
 
@@ -46,7 +46,7 @@ define <16 x i8> @t5(<16 x i8> %x) nounwind {
         %s = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 17>
         ret <16 x i8> %s
 
-; CHECK: t5:
+; CHECK-LABEL: t5:
 ; CHECK: psrldq $1
 }
 
@@ -54,7 +54,7 @@ define <16 x i8> @t6(<16 x i8> %x) nounwind {
         %s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
         ret <16 x i8> %s
 
-; CHECK: t6:
+; CHECK-LABEL: t6:
 ; CHECK: palignr $1
 }
 
@@ -62,6 +62,6 @@ define <16 x i8> @t7(<16 x i8> %x) nounwind {
         %s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2>
         ret <16 x i8> %s
 
-; CHECK: t7:
+; CHECK-LABEL: t7:
 ; CHECK: pslldq $13
 }
diff --git a/test/CodeGen/X86/vec_sdiv_to_shift.ll b/test/CodeGen/X86/vec_sdiv_to_shift.ll
index 349868a..56855d3 100644
--- a/test/CodeGen/X86/vec_sdiv_to_shift.ll
+++ b/test/CodeGen/X86/vec_sdiv_to_shift.ll
@@ -70,3 +70,11 @@ entry:
   %a0 = sdiv <16 x i16> %var, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
   ret <16 x i16> %a0
 }
+
+; CHECK: sdiv_non_splat
+; CHECK: idivl
+; CHECK: ret
+define <4 x i32> @sdiv_non_splat(<4 x i32> %x) {
+  %y = sdiv <4 x i32> %x, <i32 2, i32 0, i32 0, i32 0>
+  ret <4 x i32> %y
+}
diff --git a/test/CodeGen/X86/vec_setcc.ll b/test/CodeGen/X86/vec_setcc.ll
new file mode 100644
index 0000000..bcfd4d3
--- /dev/null
+++ b/test/CodeGen/X86/vec_setcc.ll
@@ -0,0 +1,126 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse2 | FileCheck %s -check-prefix=SSE2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse41 | FileCheck %s -check-prefix=SSE41
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx | FileCheck %s -check-prefix=AVX
+
+define <16 x i8> @v16i8_icmp_uge(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable {
+  %1 = icmp uge <16 x i8> %a, %b
+  %2 = sext <16 x i1> %1 to <16 x i8>
+  ret <16 x i8> %2
+; SSE2-LABEL: v16i8_icmp_uge:
+; SSE2: pmaxub  %xmm0, %xmm1
+; SSE2: pcmpeqb %xmm1, %xmm0
+
+; SSE41-LABEL: v16i8_icmp_uge:
+; SSE41: pmaxub  %xmm0, %xmm1
+; SSE41: pcmpeqb %xmm1, %xmm0
+
+; AVX-LABEL: v16i8_icmp_uge:
+; AVX: vpmaxub  %xmm1, %xmm0, %xmm1
+; AVX: vpcmpeqb %xmm1, %xmm0, %xmm0
+}
+
+define <16 x i8> @v16i8_icmp_ule(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable {
+  %1 = icmp ule <16 x i8> %a, %b
+  %2 = sext <16 x i1> %1 to <16 x i8>
+  ret <16 x i8> %2
+; SSE2-LABEL: v16i8_icmp_ule:
+; SSE2: pminub  %xmm0, %xmm1
+; SSE2: pcmpeqb %xmm1, %xmm0
+
+; SSE41-LABEL: v16i8_icmp_ule:
+; SSE41: pminub  %xmm0, %xmm1
+; SSE41: pcmpeqb %xmm1, %xmm0
+
+; AVX-LABEL: v16i8_icmp_ule:
+; AVX: vpminub  %xmm1, %xmm0, %xmm1
+; AVX: vpcmpeqb %xmm1, %xmm0, %xmm0
+}
+
+
+define <8 x i16> @v8i16_icmp_uge(<8 x i16> %a, <8 x i16> %b) nounwind readnone ssp uwtable {
+  %1 = icmp uge <8 x i16> %a, %b
+  %2 = sext <8 x i1> %1 to <8 x i16>
+  ret <8 x i16> %2
+; SSE2-LABEL: v8i16_icmp_uge:
+; SSE2: movdqa  {{.*}}(%rip), %xmm2
+; SEE2: pxor    %xmm2, %xmm0
+; SSE2: pxor    %xmm1, %xmm2
+; SSE2: pcmpgtw %xmm0, %xmm2
+; SSE2: pcmpeqd %xmm0, %xmm0
+; SSE2: pxor    %xmm2, %xmm0
+
+; SSE41-LABEL: v8i16_icmp_uge:
+; SSE41: pmaxuw  %xmm0, %xmm1
+; SSE41: pcmpeqw %xmm1, %xmm0
+
+; AVX-LABEL: v8i16_icmp_uge:
+; AVX: vpmaxuw  %xmm1, %xmm0, %xmm1
+; AVX: vpcmpeqw %xmm1, %xmm0, %xmm0
+}
+
+define <8 x i16> @v8i16_icmp_ule(<8 x i16> %a, <8 x i16> %b) nounwind readnone ssp uwtable {
+  %1 = icmp ule <8 x i16> %a, %b
+  %2 = sext <8 x i1> %1 to <8 x i16>
+  ret <8 x i16> %2
+; SSE2-LABEL: v8i16_icmp_ule:
+; SSE2: movdqa  {{.*}}(%rip), %xmm2
+; SSE2: pxor    %xmm2, %xmm1
+; SSE2: pxor    %xmm2, %xmm0
+; SSE2: pcmpgtw %xmm1, %xmm0
+; SSE2: pcmpeqd %xmm1, %xmm1
+; SSE2: pxor    %xmm0, %xmm1
+; SSE2: movdqa  %xmm1, %xmm0
+
+; SSE41-LABEL: v8i16_icmp_ule:
+; SSE41: pminuw  %xmm0, %xmm1
+; SSE41: pcmpeqw %xmm1, %xmm0
+
+; AVX-LABEL: v8i16_icmp_ule:
+; AVX: vpminuw  %xmm1, %xmm0, %xmm1
+; AVX: vpcmpeqw %xmm1, %xmm0, %xmm0
+}
+
+
+define <4 x i32> @v4i32_icmp_uge(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp uwtable {
+  %1 = icmp uge <4 x i32> %a, %b
+  %2 = sext <4 x i1> %1 to <4 x i32>
+  ret <4 x i32> %2
+; SSE2-LABEL: v4i32_icmp_uge:
+; SSE2: movdqa  {{.*}}(%rip), %xmm2
+; SSE2: pxor    %xmm2, %xmm0
+; SSE2: pxor    %xmm1, %xmm2
+; SSE2: pcmpgtd %xmm0, %xmm2
+; SSE2: pcmpeqd %xmm0, %xmm0
+; SSE2: pxor    %xmm2, %xmm0
+
+; SSE41-LABEL: v4i32_icmp_uge:
+; SSE41: pmaxud  %xmm0, %xmm1
+; SSE41: pcmpeqd %xmm1, %xmm0
+
+; AVX-LABEL: v4i32_icmp_uge:
+; AVX: vpmaxud  %xmm1, %xmm0, %xmm1
+; AVX: vpcmpeqd %xmm1, %xmm0, %xmm0
+}
+
+define <4 x i32> @v4i32_icmp_ule(<4 x i32> %a, <4 x i32> %b) nounwind readnone ssp uwtable {
+  %1 = icmp ule <4 x i32> %a, %b
+  %2 = sext <4 x i1> %1 to <4 x i32>
+  ret <4 x i32> %2
+; SSE2-LABEL: v4i32_icmp_ule:
+; SSE2: movdqa  {{.*}}(%rip), %xmm2
+; SSE2: pxor    %xmm2, %xmm1
+; SSE2: pxor    %xmm2, %xmm0
+; SSE2: pcmpgtd %xmm1, %xmm0
+; SSE2: pcmpeqd %xmm1, %xmm1
+; SSE2: pxor    %xmm0, %xmm1
+; SSE2: movdqa  %xmm1, %xmm0
+
+; SSE41-LABEL: v4i32_icmp_ule:
+; SSE41: pminud  %xmm0, %xmm1
+; SSE41: pcmpeqd %xmm1, %xmm0
+
+; AVX-LABEL: v4i32_icmp_ule:
+; AVX: pminud  %xmm1, %xmm0, %xmm1
+; AVX: pcmpeqd %xmm1, %xmm0, %xmm0
+}
+
diff --git a/test/CodeGen/X86/vec_shuffle-14.ll b/test/CodeGen/X86/vec_shuffle-14.ll
index f0cfc44..95e9a18 100644
--- a/test/CodeGen/X86/vec_shuffle-14.ll
+++ b/test/CodeGen/X86/vec_shuffle-14.ll
@@ -1,14 +1,17 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2
-; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 1
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd | count 2
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq | count 3
-; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep xor
+; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=X86-32
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | FileCheck %s -check-prefix=X86-64
 
 define <4 x i32> @t1(i32 %a) nounwind  {
 entry:
         %tmp = insertelement <4 x i32> undef, i32 %a, i32 0
 	%tmp6 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp, <4 x i32> < i32 4, i32 1, i32 2, i32 3 >		; <<4 x i32>> [#uses=1]
 	ret <4 x i32> %tmp6
+
+; X86-32-LABEL: t1:
+; X86-32: movd	4(%esp), %xmm0
+
+; X86-64-LABEL: t1:
+; X86-64: movd	%e{{..}}, %xmm0
 }
 
 define <2 x i64> @t2(i64 %a) nounwind  {
@@ -16,6 +19,12 @@ entry:
         %tmp = insertelement <2 x i64> undef, i64 %a, i32 0
 	%tmp6 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %tmp, <2 x i32> < i32 2, i32 1 >		; <<4 x i32>> [#uses=1]
 	ret <2 x i64> %tmp6
+
+; X86-32-LABEL: t2:
+; X86-32: movq	4(%esp), %xmm0
+
+; X86-64-LABEL: t2:
+; X86-64: movd	%r{{..}}, %xmm0
 }
 
 define <2 x i64> @t3(<2 x i64>* %a) nounwind  {
@@ -25,6 +34,13 @@ entry:
 	%tmp7 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp6, <4 x i32> < i32 4, i32 5, i32 2, i32 3 >		; <<4 x i32>> [#uses=1]
 	%tmp8 = bitcast <4 x i32> %tmp7 to <2 x i64>		; <<2 x i64>> [#uses=1]
 	ret <2 x i64> %tmp8
+
+; X86-32-LABEL: t3:
+; X86-32: movl	4(%esp)
+; X86-32: movq
+
+; X86-64-LABEL: t3:
+; X86-64: movq	({{.*}}), %xmm0
 }
 
 define <2 x i64> @t4(<2 x i64> %a) nounwind  {
@@ -33,10 +49,22 @@ entry:
 	%tmp6 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp5, <4 x i32> < i32 4, i32 5, i32 2, i32 3 >		; <<4 x i32>> [#uses=1]
 	%tmp7 = bitcast <4 x i32> %tmp6 to <2 x i64>		; <<2 x i64>> [#uses=1]
 	ret <2 x i64> %tmp7
+
+; X86-32-LABEL: t4:
+; X86-32: movq %xmm0, %xmm0
+
+; X86-64-LABEL: t4:
+; X86-64: movq {{.*}}, %xmm0
 }
 
 define <2 x i64> @t5(<2 x i64> %a) nounwind  {
 entry:
 	%tmp6 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %a, <2 x i32> < i32 2, i32 1 >		; <<4 x i32>> [#uses=1]
 	ret <2 x i64> %tmp6
+
+; X86-32-LABEL: t5:
+; X86-32: movq %xmm0, %xmm0
+
+; X86-64-LABEL: t5:
+; X86-64: movq {{.*}}, %xmm0
 }
diff --git a/test/CodeGen/X86/vec_shuffle-16.ll b/test/CodeGen/X86/vec_shuffle-16.ll
index 09d4c1a..9aeb942 100644
--- a/test/CodeGen/X86/vec_shuffle-16.ll
+++ b/test/CodeGen/X86/vec_shuffle-16.ll
@@ -1,8 +1,8 @@
 ; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=+sse,-sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse
 ; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=+sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse2
 
-; sse:  t1:
-; sse2: t1:
+; sse-LABEL:  t1:
+; sse2-LABEL: t1:
 define <4 x float> @t1(<4 x float> %a, <4 x float> %b) nounwind  {
 ; sse: shufps
 ; sse2: pshufd
@@ -11,8 +11,8 @@ define <4 x float> @t1(<4 x float> %a, <4 x float> %b) nounwind  {
         ret <4 x float> %tmp1
 }
 
-; sse:  t2:
-; sse2: t2:
+; sse-LABEL:  t2:
+; sse2-LABEL: t2:
 define <4 x float> @t2(<4 x float> %A, <4 x float> %B) nounwind {
 ; sse: shufps
 ; sse2: pshufd
@@ -21,8 +21,8 @@ define <4 x float> @t2(<4 x float> %A, <4 x float> %B) nounwind {
 	ret <4 x float> %tmp
 }
 
-; sse:  t3:
-; sse2: t3:
+; sse-LABEL:  t3:
+; sse2-LABEL: t3:
 define <4 x float> @t3(<4 x float> %A, <4 x float> %B) nounwind {
 ; sse: shufps
 ; sse2: pshufd
@@ -31,8 +31,8 @@ define <4 x float> @t3(<4 x float> %A, <4 x float> %B) nounwind {
 	ret <4 x float> %tmp
 }
 
-; sse:  t4:
-; sse2: t4:
+; sse-LABEL:  t4:
+; sse2-LABEL: t4:
 define <4 x float> @t4(<4 x float> %A, <4 x float> %B) nounwind {
 
 ; sse: shufps
diff --git a/test/CodeGen/X86/vec_shuffle-39.ll b/test/CodeGen/X86/vec_shuffle-39.ll
index ee8d2d5..1560454 100644
--- a/test/CodeGen/X86/vec_shuffle-39.ll
+++ b/test/CodeGen/X86/vec_shuffle-39.ll
@@ -3,7 +3,7 @@
 
 define <4 x float> @t1(<4 x float> %a, <1 x i64>* nocapture %p) nounwind {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: movlps (%rdi), %xmm0
 ; CHECK: ret
   %p.val = load <1 x i64>* %p, align 1
@@ -15,7 +15,7 @@ entry:
 
 define <4 x float> @t1a(<4 x float> %a, <1 x i64>* nocapture %p) nounwind {
 entry:
-; CHECK: t1a:
+; CHECK-LABEL: t1a:
 ; CHECK: movlps (%rdi), %xmm0
 ; CHECK: ret
   %0 = bitcast <1 x i64>* %p to double*
@@ -28,7 +28,7 @@ entry:
 
 define void @t2(<1 x i64>* nocapture %p, <4 x float> %a) nounwind {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: movlps %xmm0, (%rdi)
 ; CHECK: ret
   %cast.i = bitcast <4 x float> %a to <2 x i64>
@@ -40,7 +40,7 @@ entry:
 
 define void @t2a(<1 x i64>* nocapture %p, <4 x float> %a) nounwind {
 entry:
-; CHECK: t2a:
+; CHECK-LABEL: t2a:
 ; CHECK: movlps %xmm0, (%rdi)
 ; CHECK: ret
   %0 = bitcast <1 x i64>* %p to double*
@@ -53,7 +53,7 @@ entry:
 ; rdar://10436044
 define <2 x double> @t3() nounwind readonly {
 bb:
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK: punpcklqdq %xmm1, %xmm0
 ; CHECK: movq (%rax), %xmm1
 ; CHECK: movsd %xmm1, %xmm0
@@ -71,7 +71,7 @@ bb:
 ; rdar://10450317
 define <2 x i64> @t4() nounwind readonly {
 bb:
-; CHECK: t4:
+; CHECK-LABEL: t4:
 ; CHECK: punpcklqdq %xmm0, %xmm1
 ; CHECK: movq (%rax), %xmm0
 ; CHECK: movsd %xmm1, %xmm0
diff --git a/test/CodeGen/X86/vec_splat-2.ll b/test/CodeGen/X86/vec_splat-2.ll
index 5c668b7..9d82f97 100644
--- a/test/CodeGen/X86/vec_splat-2.ll
+++ b/test/CodeGen/X86/vec_splat-2.ll
@@ -24,7 +24,7 @@ define void @test(<2 x i64>* %P, i8 %x) nounwind {
 	store <2 x i64> %tmp73.upgrd.1, <2 x i64>* %P
 	ret void
 
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: pshufd
 ; CHECK: punpcklbw
 ; CHECK: punpcklbw
diff --git a/test/CodeGen/X86/vec_splat-3.ll b/test/CodeGen/X86/vec_splat-3.ll
index cf0ecf4..60e3005 100644
--- a/test/CodeGen/X86/vec_splat-3.ll
+++ b/test/CodeGen/X86/vec_splat-3.ll
@@ -5,7 +5,7 @@ define <8 x i16> @shuf_8i16_0(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 0, i32 undef, i32 undef, i32 0, i32 undef, i32 undef, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_0:
+; CHECK-LABEL: shuf_8i16_0:
 ; CHECK: pshuflw $0
 }
 
@@ -13,7 +13,7 @@ define <8 x i16> @shuf_8i16_1(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_1:
+; CHECK-LABEL: shuf_8i16_1:
 ; CHECK: pshuflw $5
 }
 
@@ -21,7 +21,7 @@ define <8 x i16> @shuf_8i16_2(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_2:
+; CHECK-LABEL: shuf_8i16_2:
 ; CHECK: punpcklwd
 ; CHECK-NEXT: pshufd $-86
 }
@@ -30,7 +30,7 @@ define <8 x i16> @shuf_8i16_3(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 3, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_3:
+; CHECK-LABEL: shuf_8i16_3:
 ; CHECK: pshuflw $15
 }
 
@@ -38,7 +38,7 @@ define <8 x i16> @shuf_8i16_4(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 4, i32 undef, i32 undef, i32 undef, i32 4, i32 undef, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_4:
+; CHECK-LABEL: shuf_8i16_4:
 ; CHECK: movhlps
 }
 
@@ -46,7 +46,7 @@ define <8 x i16> @shuf_8i16_5(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 5, i32 undef, i32 undef, i32 5, i32 undef, i32 undef, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_5:
+; CHECK-LABEL: shuf_8i16_5:
 ; CHECK: punpckhwd
 ; CHECK-NEXT: pshufd $85
 }
@@ -55,7 +55,7 @@ define <8 x i16> @shuf_8i16_6(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 6, i32 6, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_6:
+; CHECK-LABEL: shuf_8i16_6:
 ; CHECK: punpckhwd
 ; CHECK-NEXT: pshufd $-86
 }
@@ -64,7 +64,7 @@ define <8 x i16> @shuf_8i16_7(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
 	%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 7, i32 undef, i32 undef, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
 	ret <8 x i16> %tmp6
 
-; CHECK: shuf_8i16_7:
+; CHECK-LABEL: shuf_8i16_7:
 ; CHECK: punpckhwd
 ; CHECK-NEXT: pshufd $-1
 }
@@ -74,7 +74,7 @@ define <16 x i8> @shuf_16i8_8(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 0, i32 undef, i32 undef, i32 0, i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_8:
+; CHECK-LABEL: shuf_16i8_8:
 ; CHECK: punpcklbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $0
@@ -84,7 +84,7 @@ define <16 x i8> @shuf_16i8_9(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef >
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_9:
+; CHECK-LABEL: shuf_16i8_9:
 ; CHECK: punpcklbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $85
@@ -94,7 +94,7 @@ define <16 x i8> @shuf_16i8_10(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_10:
+; CHECK-LABEL: shuf_16i8_10:
 ; CHECK: punpcklbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $-86
@@ -104,7 +104,7 @@ define <16 x i8> @shuf_16i8_11(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 3, i32 undef, i32 undef, i32 3, i32 undef, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_11:
+; CHECK-LABEL: shuf_16i8_11:
 ; CHECK: punpcklbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $-1
@@ -115,7 +115,7 @@ define <16 x i8> @shuf_16i8_12(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 4, i32 undef, i32 undef, i32 undef, i32 4, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef >
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_12:
+; CHECK-LABEL: shuf_16i8_12:
 ; CHECK: pshufd $5
 }
 
@@ -123,7 +123,7 @@ define <16 x i8> @shuf_16i8_13(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 5, i32 undef, i32 undef, i32 5, i32 undef, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_13:
+; CHECK-LABEL: shuf_16i8_13:
 ; CHECK: punpcklbw
 ; CHECK-NEXT: punpckhbw
 ; CHECK-NEXT: pshufd $85
@@ -133,7 +133,7 @@ define <16 x i8> @shuf_16i8_14(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 6, i32 undef, i32 undef, i32 6, i32 undef, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_14:
+; CHECK-LABEL: shuf_16i8_14:
 ; CHECK: punpcklbw
 ; CHECK-NEXT: punpckhbw
 ; CHECK-NEXT: pshufd $-86
@@ -143,7 +143,7 @@ define <16 x i8> @shuf_16i8_15(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 7, i32 undef, i32 undef, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef >
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_15:
+; CHECK-LABEL: shuf_16i8_15:
 ; CHECK: punpcklbw
 ; CHECK-NEXT: punpckhbw
 ; CHECK-NEXT: pshufd $-1
@@ -153,7 +153,7 @@ define <16 x i8> @shuf_16i8_16(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 8, i32 undef, i32 undef, i32 8, i32 undef, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_16:
+; CHECK-LABEL: shuf_16i8_16:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $0
@@ -163,7 +163,7 @@ define <16 x i8> @shuf_16i8_17(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 9, i32 undef, i32 undef, i32 9, i32 undef, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_17:
+; CHECK-LABEL: shuf_16i8_17:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $85
@@ -173,7 +173,7 @@ define <16 x i8> @shuf_16i8_18(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 10, i32 undef, i32 undef, i32 10, i32 undef, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_18:
+; CHECK-LABEL: shuf_16i8_18:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $-86
@@ -183,7 +183,7 @@ define <16 x i8> @shuf_16i8_19(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 11, i32 undef, i32 undef, i32 11, i32 undef, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_19:
+; CHECK-LABEL: shuf_16i8_19:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpcklbw
 ; CHECK-NEXT: pshufd $-1
@@ -193,7 +193,7 @@ define <16 x i8> @shuf_16i8_20(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 12, i32 undef, i32 undef, i32 12, i32 undef, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_20:
+; CHECK-LABEL: shuf_16i8_20:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpckhbw
 ; CHECK-NEXT: pshufd $0
@@ -203,7 +203,7 @@ define <16 x i8> @shuf_16i8_21(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 13, i32 undef, i32 undef, i32 13, i32 undef, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_21:
+; CHECK-LABEL: shuf_16i8_21:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpckhbw
 ; CHECK-NEXT: pshufd $85
@@ -213,7 +213,7 @@ define <16 x i8> @shuf_16i8_22(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 14, i32 undef, i32 undef, i32 14, i32 undef, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_22:
+; CHECK-LABEL: shuf_16i8_22:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpckhbw
 ; CHECK-NEXT: pshufd $-86
@@ -223,7 +223,7 @@ define <16 x i8> @shuf_16i8_23(<16 x i8> %T0, <16 x i8> %T1) nounwind readnone {
 	%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 15, i32 undef, i32 undef, i32 15, i32 undef, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
 	ret <16 x i8> %tmp6
 
-; CHECK: shuf_16i8_23:
+; CHECK-LABEL: shuf_16i8_23:
 ; CHECK: punpckhbw
 ; CHECK-NEXT: punpckhbw
 ; CHECK-NEXT: pshufd $-1
diff --git a/test/CodeGen/X86/vec_splat.ll b/test/CodeGen/X86/vec_splat.ll
index deedee8..543c96e 100644
--- a/test/CodeGen/X86/vec_splat.ll
+++ b/test/CodeGen/X86/vec_splat.ll
@@ -11,10 +11,10 @@ define void @test_v4sf(<4 x float>* %P, <4 x float>* %Q, float %X) nounwind {
 	store <4 x float> %tmp10, <4 x float>* %P
 	ret void
 
-; SSE2: test_v4sf:
+; SSE2-LABEL: test_v4sf:
 ; SSE2: pshufd $0
 
-; SSE3: test_v4sf:
+; SSE3-LABEL: test_v4sf:
 ; SSE3: pshufd $0
 }
 
@@ -26,9 +26,9 @@ define void @test_v2sd(<2 x double>* %P, <2 x double>* %Q, double %X) nounwind {
 	store <2 x double> %tmp6, <2 x double>* %P
 	ret void
 
-; SSE2: test_v2sd:
+; SSE2-LABEL: test_v2sd:
 ; SSE2: shufpd $0
 
-; SSE3: test_v2sd:
+; SSE3-LABEL: test_v2sd:
 ; SSE3: movddup
 }
diff --git a/test/CodeGen/X86/vec_ss_load_fold.ll b/test/CodeGen/X86/vec_ss_load_fold.ll
index c294df5..2eb911f 100644
--- a/test/CodeGen/X86/vec_ss_load_fold.ll
+++ b/test/CodeGen/X86/vec_ss_load_fold.ll
@@ -15,7 +15,7 @@ define i16 @test1(float %f) nounwind {
 	%tmp.upgrd.1 = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 )		; <i32> [#uses=1]
 	%tmp69 = trunc i32 %tmp.upgrd.1 to i16		; <i16> [#uses=1]
 	ret i16 %tmp69
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: subss	LCPI0_
 ; CHECK: mulss	LCPI0_
 ; CHECK: minss	LCPI0_
@@ -30,7 +30,7 @@ define i16 @test2(float %f) nounwind {
 	%tmp = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 )		; <i32> [#uses=1]
 	%tmp69 = trunc i32 %tmp to i16		; <i16> [#uses=1]
 	ret i16 %tmp69
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: addss	LCPI1_
 ; CHECK: mulss	LCPI1_
 ; CHECK: minss	LCPI1_
@@ -55,7 +55,7 @@ define <4 x float> @test3(<4 x float> %A, float *%b, i32 %C) nounwind {
   %B = insertelement <4 x float> undef, float %a, i32 0
   %X = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %A, <4 x float> %B, i32 4)
   ret <4 x float> %X
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: roundss	$4, (%eax), %xmm0
 }
 
@@ -65,7 +65,7 @@ define <4 x float> @test4(<4 x float> %A, float *%b, i32 %C) nounwind {
   %q = call <4 x float> @f()
   %X = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %q, <4 x float> %B, i32 4)
   ret <4 x float> %X
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: movss	(%eax), %xmm
 ; CHECK: call
 ; CHECK: roundss $4, %xmm{{.*}}, %xmm0
@@ -77,7 +77,7 @@ entry:
   %0 = tail call <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double> <double
 4.569870e+02, double 1.233210e+02>, i32 128) nounwind readnone
   ret <2 x double> %0
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: mov
 ; CHECK: mov
 ; CHECK: cvtsi2sd
diff --git a/test/CodeGen/X86/vec_uint_to_fp.ll b/test/CodeGen/X86/vec_uint_to_fp.ll
index fe7fa2f..ee20f1f 100644
--- a/test/CodeGen/X86/vec_uint_to_fp.ll
+++ b/test/CodeGen/X86/vec_uint_to_fp.ll
@@ -2,7 +2,7 @@
 
 ; Test that we are not lowering uinttofp to scalars
 define <4 x float> @test1(<4 x i32> %A) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: cvtsd2ss
 ; CHECK: ret
   %C = uitofp <4 x i32> %A to <4 x float>
diff --git a/test/CodeGen/X86/vector-gep.ll b/test/CodeGen/X86/vector-gep.ll
index ec93ce0..b87d844 100644
--- a/test/CodeGen/X86/vector-gep.ll
+++ b/test/CodeGen/X86/vector-gep.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86 -mcpu=corei7-avx | FileCheck %s
 ; RUN: opt -instsimplify -disable-output < %s
 
-;CHECK: AGEP0:
+;CHECK-LABEL: AGEP0:
 define <4 x i32*> @AGEP0(i32* %ptr) nounwind {
 entry:
   %vecinit.i = insertelement <4 x i32*> undef, i32* %ptr, i32 0
@@ -16,7 +16,7 @@ entry:
 ;CHECK: ret
 }
 
-;CHECK: AGEP1:
+;CHECK-LABEL: AGEP1:
 define i32 @AGEP1(<4 x i32*> %param) nounwind {
 entry:
 ;CHECK: padd
@@ -27,7 +27,7 @@ entry:
 ;CHECK: ret
 }
 
-;CHECK: AGEP2:
+;CHECK-LABEL: AGEP2:
 define i32 @AGEP2(<4 x i32*> %param, <4 x i32> %off) nounwind {
 entry:
 ;CHECK: pslld $2
@@ -39,7 +39,7 @@ entry:
 ;CHECK: ret
 }
 
-;CHECK: AGEP3:
+;CHECK-LABEL: AGEP3:
 define <4 x i32*> @AGEP3(<4 x i32*> %param, <4 x i32> %off) nounwind {
 entry:
 ;CHECK: pslld $2
@@ -51,7 +51,7 @@ entry:
 ;CHECK: ret
 }
 
-;CHECK: AGEP4:
+;CHECK-LABEL: AGEP4:
 define <4 x i16*> @AGEP4(<4 x i16*> %param, <4 x i32> %off) nounwind {
 entry:
 ; Multiply offset by two (add it to itself).
@@ -63,7 +63,7 @@ entry:
 ;CHECK: ret
 }
 
-;CHECK: AGEP5:
+;CHECK-LABEL: AGEP5:
 define <4 x i8*> @AGEP5(<4 x i8*> %param, <4 x i8> %off) nounwind {
 entry:
 ;CHECK: paddd
@@ -74,7 +74,7 @@ entry:
 
 
 ; The size of each element is 1 byte. No need to multiply by element size.
-;CHECK: AGEP6:
+;CHECK-LABEL: AGEP6:
 define <4 x i8*> @AGEP6(<4 x i8*> %param, <4 x i32> %off) nounwind {
 entry:
 ;CHECK-NOT: pslld
diff --git a/test/CodeGen/X86/viabs.ll b/test/CodeGen/X86/viabs.ll
index f748a14..0be00da 100644
--- a/test/CodeGen/X86/viabs.ll
+++ b/test/CodeGen/X86/viabs.ll
@@ -3,18 +3,18 @@
 ; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s -check-prefix=AVX2
 
 define <4 x i32> @test1(<4 x i32> %a) nounwind {
-; SSE2: test1:
+; SSE2-LABEL: test1:
 ; SSE2: movdqa
 ; SSE2: psrad $31
 ; SSE2-NEXT: padd
 ; SSE2-NEXT: pxor
 ; SSE2-NEXT: ret
 
-; SSSE3: test1:
+; SSSE3-LABEL: test1:
 ; SSSE3: pabsd
 ; SSSE3-NEXT: ret
 
-; AVX2: test1:
+; AVX2-LABEL: test1:
 ; AVX2: vpabsd
 ; AVX2-NEXT: ret
         %tmp1neg = sub <4 x i32> zeroinitializer, %a
@@ -24,18 +24,18 @@ define <4 x i32> @test1(<4 x i32> %a) nounwind {
 }
 
 define <4 x i32> @test2(<4 x i32> %a) nounwind {
-; SSE2: test2:
+; SSE2-LABEL: test2:
 ; SSE2: movdqa
 ; SSE2: psrad $31
 ; SSE2-NEXT: padd
 ; SSE2-NEXT: pxor
 ; SSE2-NEXT: ret
 
-; SSSE3: test2:
+; SSSE3-LABEL: test2:
 ; SSSE3: pabsd
 ; SSSE3-NEXT: ret
 
-; AVX2: test2:
+; AVX2-LABEL: test2:
 ; AVX2: vpabsd
 ; AVX2-NEXT: ret
         %tmp1neg = sub <4 x i32> zeroinitializer, %a
@@ -45,18 +45,18 @@ define <4 x i32> @test2(<4 x i32> %a) nounwind {
 }
 
 define <8 x i16> @test3(<8 x i16> %a) nounwind {
-; SSE2: test3:
+; SSE2-LABEL: test3:
 ; SSE2: movdqa
 ; SSE2: psraw $15
 ; SSE2-NEXT: padd
 ; SSE2-NEXT: pxor
 ; SSE2-NEXT: ret
 
-; SSSE3: test3:
+; SSSE3-LABEL: test3:
 ; SSSE3: pabsw
 ; SSSE3-NEXT: ret
 
-; AVX2: test3:
+; AVX2-LABEL: test3:
 ; AVX2: vpabsw
 ; AVX2-NEXT: ret
         %tmp1neg = sub <8 x i16> zeroinitializer, %a
@@ -66,18 +66,18 @@ define <8 x i16> @test3(<8 x i16> %a) nounwind {
 }
 
 define <16 x i8> @test4(<16 x i8> %a) nounwind {
-; SSE2: test4:
+; SSE2-LABEL: test4:
 ; SSE2: pxor
 ; SSE2: pcmpgtb
 ; SSE2-NEXT: padd
 ; SSE2-NEXT: pxor
 ; SSE2-NEXT: ret
 
-; SSSE3: test4:
+; SSSE3-LABEL: test4:
 ; SSSE3: pabsb
 ; SSSE3-NEXT: ret
 
-; AVX2: test4:
+; AVX2-LABEL: test4:
 ; AVX2: vpabsb
 ; AVX2-NEXT: ret
         %tmp1neg = sub <16 x i8> zeroinitializer, %a
@@ -87,18 +87,18 @@ define <16 x i8> @test4(<16 x i8> %a) nounwind {
 }
 
 define <4 x i32> @test5(<4 x i32> %a) nounwind {
-; SSE2: test5:
+; SSE2-LABEL: test5:
 ; SSE2: movdqa
 ; SSE2: psrad $31
 ; SSE2-NEXT: padd
 ; SSE2-NEXT: pxor
 ; SSE2-NEXT: ret
 
-; SSSE3: test5:
+; SSSE3-LABEL: test5:
 ; SSSE3: pabsd
 ; SSSE3-NEXT: ret
 
-; AVX2: test5:
+; AVX2-LABEL: test5:
 ; AVX2: vpabsd
 ; AVX2-NEXT: ret
         %tmp1neg = sub <4 x i32> zeroinitializer, %a
@@ -108,12 +108,12 @@ define <4 x i32> @test5(<4 x i32> %a) nounwind {
 }
 
 define <8 x i32> @test6(<8 x i32> %a) nounwind {
-; SSSE3: test6:
+; SSSE3-LABEL: test6:
 ; SSSE3: pabsd
 ; SSSE3: pabsd
 ; SSSE3-NEXT: ret
 
-; AVX2: test6:
+; AVX2-LABEL: test6:
 ; AVX2: vpabsd {{.*}}%ymm
 ; AVX2-NEXT: ret
         %tmp1neg = sub <8 x i32> zeroinitializer, %a
@@ -123,12 +123,12 @@ define <8 x i32> @test6(<8 x i32> %a) nounwind {
 }
 
 define <8 x i32> @test7(<8 x i32> %a) nounwind {
-; SSSE3: test7:
+; SSSE3-LABEL: test7:
 ; SSSE3: pabsd
 ; SSSE3: pabsd
 ; SSSE3-NEXT: ret
 
-; AVX2: test7:
+; AVX2-LABEL: test7:
 ; AVX2: vpabsd {{.*}}%ymm
 ; AVX2-NEXT: ret
         %tmp1neg = sub <8 x i32> zeroinitializer, %a
@@ -138,12 +138,12 @@ define <8 x i32> @test7(<8 x i32> %a) nounwind {
 }
 
 define <16 x i16> @test8(<16 x i16> %a) nounwind {
-; SSSE3: test8:
+; SSSE3-LABEL: test8:
 ; SSSE3: pabsw
 ; SSSE3: pabsw
 ; SSSE3-NEXT: ret
 
-; AVX2: test8:
+; AVX2-LABEL: test8:
 ; AVX2: vpabsw {{.*}}%ymm
 ; AVX2-NEXT: ret
         %tmp1neg = sub <16 x i16> zeroinitializer, %a
@@ -153,12 +153,12 @@ define <16 x i16> @test8(<16 x i16> %a) nounwind {
 }
 
 define <32 x i8> @test9(<32 x i8> %a) nounwind {
-; SSSE3: test9:
+; SSSE3-LABEL: test9:
 ; SSSE3: pabsb
 ; SSSE3: pabsb
 ; SSSE3-NEXT: ret
 
-; AVX2: test9:
+; AVX2-LABEL: test9:
 ; AVX2: vpabsb {{.*}}%ymm
 ; AVX2-NEXT: ret
         %tmp1neg = sub <32 x i8> zeroinitializer, %a
@@ -168,12 +168,12 @@ define <32 x i8> @test9(<32 x i8> %a) nounwind {
 }
 
 define <8 x i32> @test10(<8 x i32> %a) nounwind {
-; SSSE3: test10:
+; SSSE3-LABEL: test10:
 ; SSSE3: pabsd
 ; SSSE3: pabsd
 ; SSSE3-NEXT: ret
 
-; AVX2: test10:
+; AVX2-LABEL: test10:
 ; AVX2: vpabsd {{.*}}%ymm
 ; AVX2-NEXT: ret
         %tmp1neg = sub <8 x i32> zeroinitializer, %a
diff --git a/test/CodeGen/X86/vselect-minmax.ll b/test/CodeGen/X86/vselect-minmax.ll
index cf654b6..25189f2 100644
--- a/test/CodeGen/X86/vselect-minmax.ll
+++ b/test/CodeGen/X86/vselect-minmax.ll
@@ -25,13 +25,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test1:
+; SSE4-LABEL: test1:
 ; SSE4: pminsb
 
-; AVX1: test1:
+; AVX1-LABEL: test1:
 ; AVX1: vpminsb
 
-; AVX2: test1:
+; AVX2-LABEL: test1:
 ; AVX2: vpminsb
 }
 
@@ -57,13 +57,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test2:
+; SSE4-LABEL: test2:
 ; SSE4: pminsb
 
-; AVX1: test2:
+; AVX1-LABEL: test2:
 ; AVX1: vpminsb
 
-; AVX2: test2:
+; AVX2-LABEL: test2:
 ; AVX2: vpminsb
 }
 
@@ -89,13 +89,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test3:
+; SSE4-LABEL: test3:
 ; SSE4: pmaxsb
 
-; AVX1: test3:
+; AVX1-LABEL: test3:
 ; AVX1: vpmaxsb
 
-; AVX2: test3:
+; AVX2-LABEL: test3:
 ; AVX2: vpmaxsb
 }
 
@@ -121,13 +121,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test4:
+; SSE4-LABEL: test4:
 ; SSE4: pmaxsb
 
-; AVX1: test4:
+; AVX1-LABEL: test4:
 ; AVX1: vpmaxsb
 
-; AVX2: test4:
+; AVX2-LABEL: test4:
 ; AVX2: vpmaxsb
 }
 
@@ -153,13 +153,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test5:
+; SSE2-LABEL: test5:
 ; SSE2: pminub
 
-; AVX1: test5:
+; AVX1-LABEL: test5:
 ; AVX1: vpminub
 
-; AVX2: test5:
+; AVX2-LABEL: test5:
 ; AVX2: vpminub
 }
 
@@ -185,13 +185,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test6:
+; SSE2-LABEL: test6:
 ; SSE2: pminub
 
-; AVX1: test6:
+; AVX1-LABEL: test6:
 ; AVX1: vpminub
 
-; AVX2: test6:
+; AVX2-LABEL: test6:
 ; AVX2: vpminub
 }
 
@@ -217,13 +217,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test7:
+; SSE2-LABEL: test7:
 ; SSE2: pmaxub
 
-; AVX1: test7:
+; AVX1-LABEL: test7:
 ; AVX1: vpmaxub
 
-; AVX2: test7:
+; AVX2-LABEL: test7:
 ; AVX2: vpmaxub
 }
 
@@ -249,13 +249,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test8:
+; SSE2-LABEL: test8:
 ; SSE2: pmaxub
 
-; AVX1: test8:
+; AVX1-LABEL: test8:
 ; AVX1: vpmaxub
 
-; AVX2: test8:
+; AVX2-LABEL: test8:
 ; AVX2: vpmaxub
 }
 
@@ -281,13 +281,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test9:
+; SSE2-LABEL: test9:
 ; SSE2: pminsw
 
-; AVX1: test9:
+; AVX1-LABEL: test9:
 ; AVX1: vpminsw
 
-; AVX2: test9:
+; AVX2-LABEL: test9:
 ; AVX2: vpminsw
 }
 
@@ -313,13 +313,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test10:
+; SSE2-LABEL: test10:
 ; SSE2: pminsw
 
-; AVX1: test10:
+; AVX1-LABEL: test10:
 ; AVX1: vpminsw
 
-; AVX2: test10:
+; AVX2-LABEL: test10:
 ; AVX2: vpminsw
 }
 
@@ -345,13 +345,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test11:
+; SSE2-LABEL: test11:
 ; SSE2: pmaxsw
 
-; AVX1: test11:
+; AVX1-LABEL: test11:
 ; AVX1: vpmaxsw
 
-; AVX2: test11:
+; AVX2-LABEL: test11:
 ; AVX2: vpmaxsw
 }
 
@@ -377,13 +377,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test12:
+; SSE2-LABEL: test12:
 ; SSE2: pmaxsw
 
-; AVX1: test12:
+; AVX1-LABEL: test12:
 ; AVX1: vpmaxsw
 
-; AVX2: test12:
+; AVX2-LABEL: test12:
 ; AVX2: vpmaxsw
 }
 
@@ -409,13 +409,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test13:
+; SSE4-LABEL: test13:
 ; SSE4: pminuw
 
-; AVX1: test13:
+; AVX1-LABEL: test13:
 ; AVX1: vpminuw
 
-; AVX2: test13:
+; AVX2-LABEL: test13:
 ; AVX2: vpminuw
 }
 
@@ -441,13 +441,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test14:
+; SSE4-LABEL: test14:
 ; SSE4: pminuw
 
-; AVX1: test14:
+; AVX1-LABEL: test14:
 ; AVX1: vpminuw
 
-; AVX2: test14:
+; AVX2-LABEL: test14:
 ; AVX2: vpminuw
 }
 
@@ -473,13 +473,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test15:
+; SSE4-LABEL: test15:
 ; SSE4: pmaxuw
 
-; AVX1: test15:
+; AVX1-LABEL: test15:
 ; AVX1: vpmaxuw
 
-; AVX2: test15:
+; AVX2-LABEL: test15:
 ; AVX2: vpmaxuw
 }
 
@@ -505,13 +505,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test16:
+; SSE4-LABEL: test16:
 ; SSE4: pmaxuw
 
-; AVX1: test16:
+; AVX1-LABEL: test16:
 ; AVX1: vpmaxuw
 
-; AVX2: test16:
+; AVX2-LABEL: test16:
 ; AVX2: vpmaxuw
 }
 
@@ -537,13 +537,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test17:
+; SSE4-LABEL: test17:
 ; SSE4: pminsd
 
-; AVX1: test17:
+; AVX1-LABEL: test17:
 ; AVX1: vpminsd
 
-; AVX2: test17:
+; AVX2-LABEL: test17:
 ; AVX2: vpminsd
 }
 
@@ -569,13 +569,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test18:
+; SSE4-LABEL: test18:
 ; SSE4: pminsd
 
-; AVX1: test18:
+; AVX1-LABEL: test18:
 ; AVX1: vpminsd
 
-; AVX2: test18:
+; AVX2-LABEL: test18:
 ; AVX2: vpminsd
 }
 
@@ -601,13 +601,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test19:
+; SSE4-LABEL: test19:
 ; SSE4: pmaxsd
 
-; AVX1: test19:
+; AVX1-LABEL: test19:
 ; AVX1: vpmaxsd
 
-; AVX2: test19:
+; AVX2-LABEL: test19:
 ; AVX2: vpmaxsd
 }
 
@@ -633,13 +633,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test20:
+; SSE4-LABEL: test20:
 ; SSE4: pmaxsd
 
-; AVX1: test20:
+; AVX1-LABEL: test20:
 ; AVX1: vpmaxsd
 
-; AVX2: test20:
+; AVX2-LABEL: test20:
 ; AVX2: vpmaxsd
 }
 
@@ -665,13 +665,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test21:
+; SSE4-LABEL: test21:
 ; SSE4: pminud
 
-; AVX1: test21:
+; AVX1-LABEL: test21:
 ; AVX1: vpminud
 
-; AVX2: test21:
+; AVX2-LABEL: test21:
 ; AVX2: vpminud
 }
 
@@ -697,13 +697,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test22:
+; SSE4-LABEL: test22:
 ; SSE4: pminud
 
-; AVX1: test22:
+; AVX1-LABEL: test22:
 ; AVX1: vpminud
 
-; AVX2: test22:
+; AVX2-LABEL: test22:
 ; AVX2: vpminud
 }
 
@@ -729,13 +729,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test23:
+; SSE4-LABEL: test23:
 ; SSE4: pmaxud
 
-; AVX1: test23:
+; AVX1-LABEL: test23:
 ; AVX1: vpmaxud
 
-; AVX2: test23:
+; AVX2-LABEL: test23:
 ; AVX2: vpmaxud
 }
 
@@ -761,13 +761,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test24:
+; SSE4-LABEL: test24:
 ; SSE4: pmaxud
 
-; AVX1: test24:
+; AVX1-LABEL: test24:
 ; AVX1: vpmaxud
 
-; AVX2: test24:
+; AVX2-LABEL: test24:
 ; AVX2: vpmaxud
 }
 
@@ -793,7 +793,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test25:
+; AVX2-LABEL: test25:
 ; AVX2: vpminsb
 }
 
@@ -819,7 +819,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test26:
+; AVX2-LABEL: test26:
 ; AVX2: vpminsb
 }
 
@@ -845,7 +845,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test27:
+; AVX2-LABEL: test27:
 ; AVX2: vpmaxsb
 }
 
@@ -871,7 +871,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test28:
+; AVX2-LABEL: test28:
 ; AVX2: vpmaxsb
 }
 
@@ -897,7 +897,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test29:
+; AVX2-LABEL: test29:
 ; AVX2: vpminub
 }
 
@@ -923,7 +923,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test30:
+; AVX2-LABEL: test30:
 ; AVX2: vpminub
 }
 
@@ -949,7 +949,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test31:
+; AVX2-LABEL: test31:
 ; AVX2: vpmaxub
 }
 
@@ -975,7 +975,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test32:
+; AVX2-LABEL: test32:
 ; AVX2: vpmaxub
 }
 
@@ -1001,7 +1001,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test33:
+; AVX2-LABEL: test33:
 ; AVX2: vpminsw
 }
 
@@ -1027,7 +1027,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test34:
+; AVX2-LABEL: test34:
 ; AVX2: vpminsw
 }
 
@@ -1053,7 +1053,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test35:
+; AVX2-LABEL: test35:
 ; AVX2: vpmaxsw
 }
 
@@ -1079,7 +1079,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test36:
+; AVX2-LABEL: test36:
 ; AVX2: vpmaxsw
 }
 
@@ -1105,7 +1105,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test37:
+; AVX2-LABEL: test37:
 ; AVX2: vpminuw
 }
 
@@ -1131,7 +1131,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test38:
+; AVX2-LABEL: test38:
 ; AVX2: vpminuw
 }
 
@@ -1157,7 +1157,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test39:
+; AVX2-LABEL: test39:
 ; AVX2: vpmaxuw
 }
 
@@ -1183,7 +1183,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test40:
+; AVX2-LABEL: test40:
 ; AVX2: vpmaxuw
 }
 
@@ -1209,7 +1209,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test41:
+; AVX2-LABEL: test41:
 ; AVX2: vpminsd
 }
 
@@ -1235,7 +1235,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test42:
+; AVX2-LABEL: test42:
 ; AVX2: vpminsd
 }
 
@@ -1261,7 +1261,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test43:
+; AVX2-LABEL: test43:
 ; AVX2: vpmaxsd
 }
 
@@ -1287,7 +1287,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test44:
+; AVX2-LABEL: test44:
 ; AVX2: vpmaxsd
 }
 
@@ -1313,7 +1313,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test45:
+; AVX2-LABEL: test45:
 ; AVX2: vpminud
 }
 
@@ -1339,7 +1339,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test46:
+; AVX2-LABEL: test46:
 ; AVX2: vpminud
 }
 
@@ -1365,7 +1365,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test47:
+; AVX2-LABEL: test47:
 ; AVX2: vpmaxud
 }
 
@@ -1391,7 +1391,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test48:
+; AVX2-LABEL: test48:
 ; AVX2: vpmaxud
 }
 
@@ -1417,13 +1417,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test49:
+; SSE4-LABEL: test49:
 ; SSE4: pmaxsb
 
-; AVX1: test49:
+; AVX1-LABEL: test49:
 ; AVX1: vpmaxsb
 
-; AVX2: test49:
+; AVX2-LABEL: test49:
 ; AVX2: vpmaxsb
 }
 
@@ -1449,13 +1449,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test50:
+; SSE4-LABEL: test50:
 ; SSE4: pmaxsb
 
-; AVX1: test50:
+; AVX1-LABEL: test50:
 ; AVX1: vpmaxsb
 
-; AVX2: test50:
+; AVX2-LABEL: test50:
 ; AVX2: vpmaxsb
 }
 
@@ -1481,13 +1481,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test51:
+; SSE4-LABEL: test51:
 ; SSE4: pminsb
 
-; AVX1: test51:
+; AVX1-LABEL: test51:
 ; AVX1: vpminsb
 
-; AVX2: test51:
+; AVX2-LABEL: test51:
 ; AVX2: vpminsb
 }
 
@@ -1513,13 +1513,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test52:
+; SSE4-LABEL: test52:
 ; SSE4: pminsb
 
-; AVX1: test52:
+; AVX1-LABEL: test52:
 ; AVX1: vpminsb
 
-; AVX2: test52:
+; AVX2-LABEL: test52:
 ; AVX2: vpminsb
 }
 
@@ -1545,13 +1545,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test53:
+; SSE2-LABEL: test53:
 ; SSE2: pmaxub
 
-; AVX1: test53:
+; AVX1-LABEL: test53:
 ; AVX1: vpmaxub
 
-; AVX2: test53:
+; AVX2-LABEL: test53:
 ; AVX2: vpmaxub
 }
 
@@ -1577,13 +1577,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test54:
+; SSE2-LABEL: test54:
 ; SSE2: pmaxub
 
-; AVX1: test54:
+; AVX1-LABEL: test54:
 ; AVX1: vpmaxub
 
-; AVX2: test54:
+; AVX2-LABEL: test54:
 ; AVX2: vpmaxub
 }
 
@@ -1609,13 +1609,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test55:
+; SSE2-LABEL: test55:
 ; SSE2: pminub
 
-; AVX1: test55:
+; AVX1-LABEL: test55:
 ; AVX1: vpminub
 
-; AVX2: test55:
+; AVX2-LABEL: test55:
 ; AVX2: vpminub
 }
 
@@ -1641,13 +1641,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test56:
+; SSE2-LABEL: test56:
 ; SSE2: pminub
 
-; AVX1: test56:
+; AVX1-LABEL: test56:
 ; AVX1: vpminub
 
-; AVX2: test56:
+; AVX2-LABEL: test56:
 ; AVX2: vpminub
 }
 
@@ -1673,13 +1673,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test57:
+; SSE2-LABEL: test57:
 ; SSE2: pmaxsw
 
-; AVX1: test57:
+; AVX1-LABEL: test57:
 ; AVX1: vpmaxsw
 
-; AVX2: test57:
+; AVX2-LABEL: test57:
 ; AVX2: vpmaxsw
 }
 
@@ -1705,13 +1705,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test58:
+; SSE2-LABEL: test58:
 ; SSE2: pmaxsw
 
-; AVX1: test58:
+; AVX1-LABEL: test58:
 ; AVX1: vpmaxsw
 
-; AVX2: test58:
+; AVX2-LABEL: test58:
 ; AVX2: vpmaxsw
 }
 
@@ -1737,13 +1737,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test59:
+; SSE2-LABEL: test59:
 ; SSE2: pminsw
 
-; AVX1: test59:
+; AVX1-LABEL: test59:
 ; AVX1: vpminsw
 
-; AVX2: test59:
+; AVX2-LABEL: test59:
 ; AVX2: vpminsw
 }
 
@@ -1769,13 +1769,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test60:
+; SSE2-LABEL: test60:
 ; SSE2: pminsw
 
-; AVX1: test60:
+; AVX1-LABEL: test60:
 ; AVX1: vpminsw
 
-; AVX2: test60:
+; AVX2-LABEL: test60:
 ; AVX2: vpminsw
 }
 
@@ -1801,13 +1801,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test61:
+; SSE4-LABEL: test61:
 ; SSE4: pmaxuw
 
-; AVX1: test61:
+; AVX1-LABEL: test61:
 ; AVX1: vpmaxuw
 
-; AVX2: test61:
+; AVX2-LABEL: test61:
 ; AVX2: vpmaxuw
 }
 
@@ -1833,13 +1833,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test62:
+; SSE4-LABEL: test62:
 ; SSE4: pmaxuw
 
-; AVX1: test62:
+; AVX1-LABEL: test62:
 ; AVX1: vpmaxuw
 
-; AVX2: test62:
+; AVX2-LABEL: test62:
 ; AVX2: vpmaxuw
 }
 
@@ -1865,13 +1865,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test63:
+; SSE4-LABEL: test63:
 ; SSE4: pminuw
 
-; AVX1: test63:
+; AVX1-LABEL: test63:
 ; AVX1: vpminuw
 
-; AVX2: test63:
+; AVX2-LABEL: test63:
 ; AVX2: vpminuw
 }
 
@@ -1897,13 +1897,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test64:
+; SSE4-LABEL: test64:
 ; SSE4: pminuw
 
-; AVX1: test64:
+; AVX1-LABEL: test64:
 ; AVX1: vpminuw
 
-; AVX2: test64:
+; AVX2-LABEL: test64:
 ; AVX2: vpminuw
 }
 
@@ -1929,13 +1929,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test65:
+; SSE4-LABEL: test65:
 ; SSE4: pmaxsd
 
-; AVX1: test65:
+; AVX1-LABEL: test65:
 ; AVX1: vpmaxsd
 
-; AVX2: test65:
+; AVX2-LABEL: test65:
 ; AVX2: vpmaxsd
 }
 
@@ -1961,13 +1961,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test66:
+; SSE4-LABEL: test66:
 ; SSE4: pmaxsd
 
-; AVX1: test66:
+; AVX1-LABEL: test66:
 ; AVX1: vpmaxsd
 
-; AVX2: test66:
+; AVX2-LABEL: test66:
 ; AVX2: vpmaxsd
 }
 
@@ -1993,13 +1993,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test67:
+; SSE4-LABEL: test67:
 ; SSE4: pminsd
 
-; AVX1: test67:
+; AVX1-LABEL: test67:
 ; AVX1: vpminsd
 
-; AVX2: test67:
+; AVX2-LABEL: test67:
 ; AVX2: vpminsd
 }
 
@@ -2025,13 +2025,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test68:
+; SSE4-LABEL: test68:
 ; SSE4: pminsd
 
-; AVX1: test68:
+; AVX1-LABEL: test68:
 ; AVX1: vpminsd
 
-; AVX2: test68:
+; AVX2-LABEL: test68:
 ; AVX2: vpminsd
 }
 
@@ -2057,13 +2057,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test69:
+; SSE4-LABEL: test69:
 ; SSE4: pmaxud
 
-; AVX1: test69:
+; AVX1-LABEL: test69:
 ; AVX1: vpmaxud
 
-; AVX2: test69:
+; AVX2-LABEL: test69:
 ; AVX2: vpmaxud
 }
 
@@ -2089,13 +2089,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test70:
+; SSE4-LABEL: test70:
 ; SSE4: pmaxud
 
-; AVX1: test70:
+; AVX1-LABEL: test70:
 ; AVX1: vpmaxud
 
-; AVX2: test70:
+; AVX2-LABEL: test70:
 ; AVX2: vpmaxud
 }
 
@@ -2121,13 +2121,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test71:
+; SSE4-LABEL: test71:
 ; SSE4: pminud
 
-; AVX1: test71:
+; AVX1-LABEL: test71:
 ; AVX1: vpminud
 
-; AVX2: test71:
+; AVX2-LABEL: test71:
 ; AVX2: vpminud
 }
 
@@ -2153,13 +2153,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test72:
+; SSE4-LABEL: test72:
 ; SSE4: pminud
 
-; AVX1: test72:
+; AVX1-LABEL: test72:
 ; AVX1: vpminud
 
-; AVX2: test72:
+; AVX2-LABEL: test72:
 ; AVX2: vpminud
 }
 
@@ -2185,7 +2185,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test73:
+; AVX2-LABEL: test73:
 ; AVX2: vpmaxsb
 }
 
@@ -2211,7 +2211,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test74:
+; AVX2-LABEL: test74:
 ; AVX2: vpmaxsb
 }
 
@@ -2237,7 +2237,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test75:
+; AVX2-LABEL: test75:
 ; AVX2: vpminsb
 }
 
@@ -2263,7 +2263,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test76:
+; AVX2-LABEL: test76:
 ; AVX2: vpminsb
 }
 
@@ -2289,7 +2289,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test77:
+; AVX2-LABEL: test77:
 ; AVX2: vpmaxub
 }
 
@@ -2315,7 +2315,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test78:
+; AVX2-LABEL: test78:
 ; AVX2: vpmaxub
 }
 
@@ -2341,7 +2341,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test79:
+; AVX2-LABEL: test79:
 ; AVX2: vpminub
 }
 
@@ -2367,7 +2367,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test80:
+; AVX2-LABEL: test80:
 ; AVX2: vpminub
 }
 
@@ -2393,7 +2393,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test81:
+; AVX2-LABEL: test81:
 ; AVX2: vpmaxsw
 }
 
@@ -2419,7 +2419,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test82:
+; AVX2-LABEL: test82:
 ; AVX2: vpmaxsw
 }
 
@@ -2445,7 +2445,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test83:
+; AVX2-LABEL: test83:
 ; AVX2: vpminsw
 }
 
@@ -2471,7 +2471,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test84:
+; AVX2-LABEL: test84:
 ; AVX2: vpminsw
 }
 
@@ -2497,7 +2497,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test85:
+; AVX2-LABEL: test85:
 ; AVX2: vpmaxuw
 }
 
@@ -2523,7 +2523,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test86:
+; AVX2-LABEL: test86:
 ; AVX2: vpmaxuw
 }
 
@@ -2549,7 +2549,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test87:
+; AVX2-LABEL: test87:
 ; AVX2: vpminuw
 }
 
@@ -2575,7 +2575,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test88:
+; AVX2-LABEL: test88:
 ; AVX2: vpminuw
 }
 
@@ -2601,7 +2601,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test89:
+; AVX2-LABEL: test89:
 ; AVX2: vpmaxsd
 }
 
@@ -2627,7 +2627,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test90:
+; AVX2-LABEL: test90:
 ; AVX2: vpmaxsd
 }
 
@@ -2653,7 +2653,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test91:
+; AVX2-LABEL: test91:
 ; AVX2: vpminsd
 }
 
@@ -2679,7 +2679,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test92:
+; AVX2-LABEL: test92:
 ; AVX2: vpminsd
 }
 
@@ -2705,7 +2705,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test93:
+; AVX2-LABEL: test93:
 ; AVX2: vpmaxud
 }
 
@@ -2731,7 +2731,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test94:
+; AVX2-LABEL: test94:
 ; AVX2: vpmaxud
 }
 
@@ -2757,7 +2757,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test95:
+; AVX2-LABEL: test95:
 ; AVX2: vpminud
 }
 
@@ -2783,6 +2783,6 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test96:
+; AVX2-LABEL: test96:
 ; AVX2: vpminud
 }
diff --git a/test/CodeGen/X86/vshift-1.ll b/test/CodeGen/X86/vshift-1.ll
index e775750..b8a6767 100644
--- a/test/CodeGen/X86/vshift-1.ll
+++ b/test/CodeGen/X86/vshift-1.ll
@@ -5,7 +5,7 @@
 
 define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
 entry:
-; CHECK: shift1a:
+; CHECK-LABEL: shift1a:
 ; CHECK: psllq
   %shl = shl <2 x i64> %val, < i64 32, i64 32 >
   store <2 x i64> %shl, <2 x i64>* %dst
@@ -14,7 +14,7 @@ entry:
 
 define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
 entry:
-; CHECK: shift1b:
+; CHECK-LABEL: shift1b:
 ; CHECK: movd
 ; CHECK: psllq
   %0 = insertelement <2 x i64> undef, i64 %amt, i32 0
@@ -27,7 +27,7 @@ entry:
 
 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
 entry:
-; CHECK: shift2a:
+; CHECK-LABEL: shift2a:
 ; CHECK: pslld
   %shl = shl <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
   store <4 x i32> %shl, <4 x i32>* %dst
@@ -36,7 +36,7 @@ entry:
 
 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
 entry:
-; CHECK: shift2b:
+; CHECK-LABEL: shift2b:
 ; CHECK: movd
 ; CHECK: pslld
   %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
@@ -50,7 +50,7 @@ entry:
 
 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
 entry:
-; CHECK: shift3a:
+; CHECK-LABEL: shift3a:
 ; CHECK: psllw
   %shl = shl <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
   store <8 x i16> %shl, <8 x i16>* %dst
@@ -60,18 +60,18 @@ entry:
 ; Make sure the shift amount is properly zero extended.
 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
 entry:
-; CHECK: shift3b:
+; CHECK-LABEL: shift3b:
 ; CHECK: movzwl
 ; CHECK: movd
 ; CHECK-NEXT: psllw
   %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
   %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
-  %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
-  %3 = insertelement <8 x i16> %0, i16 %amt, i32 3
-  %4 = insertelement <8 x i16> %0, i16 %amt, i32 4
-  %5 = insertelement <8 x i16> %0, i16 %amt, i32 5
-  %6 = insertelement <8 x i16> %0, i16 %amt, i32 6
-  %7 = insertelement <8 x i16> %0, i16 %amt, i32 7
+  %2 = insertelement <8 x i16> %1, i16 %amt, i32 2
+  %3 = insertelement <8 x i16> %2, i16 %amt, i32 3
+  %4 = insertelement <8 x i16> %3, i16 %amt, i32 4
+  %5 = insertelement <8 x i16> %4, i16 %amt, i32 5
+  %6 = insertelement <8 x i16> %5, i16 %amt, i32 6
+  %7 = insertelement <8 x i16> %6, i16 %amt, i32 7
   %shl = shl <8 x i16> %val, %7
   store <8 x i16> %shl, <8 x i16>* %dst
   ret void
diff --git a/test/CodeGen/X86/vshift-2.ll b/test/CodeGen/X86/vshift-2.ll
index 9496893..156649a 100644
--- a/test/CodeGen/X86/vshift-2.ll
+++ b/test/CodeGen/X86/vshift-2.ll
@@ -5,7 +5,7 @@
 
 define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
 entry:
-; CHECK: shift1a:
+; CHECK-LABEL: shift1a:
 ; CHECK: psrlq
   %lshr = lshr <2 x i64> %val, < i64 32, i64 32 >
   store <2 x i64> %lshr, <2 x i64>* %dst
@@ -14,7 +14,7 @@ entry:
 
 define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
 entry:
-; CHECK: shift1b:
+; CHECK-LABEL: shift1b:
 ; CHECK: movd
 ; CHECK: psrlq
   %0 = insertelement <2 x i64> undef, i64 %amt, i32 0
@@ -26,7 +26,7 @@ entry:
 
 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
 entry:
-; CHECK: shift2a:
+; CHECK-LABEL: shift2a:
 ; CHECK: psrld
   %lshr = lshr <4 x i32> %val, < i32 17, i32 17, i32 17, i32 17 >
   store <4 x i32> %lshr, <4 x i32>* %dst
@@ -35,7 +35,7 @@ entry:
 
 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
 entry:
-; CHECK: shift2b:
+; CHECK-LABEL: shift2b:
 ; CHECK: movd
 ; CHECK: psrld
   %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
@@ -50,7 +50,7 @@ entry:
 
 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
 entry:
-; CHECK: shift3a:
+; CHECK-LABEL: shift3a:
 ; CHECK: psrlw
   %lshr = lshr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
   store <8 x i16> %lshr, <8 x i16>* %dst
@@ -60,18 +60,18 @@ entry:
 ; properly zero extend the shift amount
 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
 entry:
-; CHECK: shift3b:
+; CHECK-LABEL: shift3b:
 ; CHECK: movzwl
 ; CHECK: movd
 ; CHECK: psrlw
   %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
   %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
-  %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
-  %3 = insertelement <8 x i16> %0, i16 %amt, i32 3
-  %4 = insertelement <8 x i16> %0, i16 %amt, i32 4
-  %5 = insertelement <8 x i16> %0, i16 %amt, i32 5
-  %6 = insertelement <8 x i16> %0, i16 %amt, i32 6
-  %7 = insertelement <8 x i16> %0, i16 %amt, i32 7
+  %2 = insertelement <8 x i16> %1, i16 %amt, i32 2
+  %3 = insertelement <8 x i16> %2, i16 %amt, i32 3
+  %4 = insertelement <8 x i16> %3, i16 %amt, i32 4
+  %5 = insertelement <8 x i16> %4, i16 %amt, i32 5
+  %6 = insertelement <8 x i16> %5, i16 %amt, i32 6
+  %7 = insertelement <8 x i16> %6, i16 %amt, i32 7
   %lshr = lshr <8 x i16> %val, %7
   store <8 x i16> %lshr, <8 x i16>* %dst
   ret void
diff --git a/test/CodeGen/X86/vshift-3.ll b/test/CodeGen/X86/vshift-3.ll
index b2b48b9..0bdb32f 100644
--- a/test/CodeGen/X86/vshift-3.ll
+++ b/test/CodeGen/X86/vshift-3.ll
@@ -8,7 +8,7 @@
 ; shift1a can't use a packed shift
 define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
 entry:
-; CHECK: shift1a:
+; CHECK-LABEL: shift1a:
 ; CHECK: sarl
   %ashr = ashr <2 x i64> %val, < i64 32, i64 32 >
   store <2 x i64> %ashr, <2 x i64>* %dst
@@ -17,7 +17,7 @@ entry:
 
 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
 entry:
-; CHECK: shift2a:
+; CHECK-LABEL: shift2a:
 ; CHECK: psrad	$5
   %ashr = ashr <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
   store <4 x i32> %ashr, <4 x i32>* %dst
@@ -26,7 +26,7 @@ entry:
 
 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
 entry:
-; CHECK: shift2b:
+; CHECK-LABEL: shift2b:
 ; CHECK: movd
 ; CHECK: psrad
   %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
@@ -40,7 +40,7 @@ entry:
 
 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
 entry:
-; CHECK: shift3a:
+; CHECK-LABEL: shift3a:
 ; CHECK: psraw	$5
   %ashr = ashr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
   store <8 x i16> %ashr, <8 x i16>* %dst
@@ -49,18 +49,18 @@ entry:
 
 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
 entry:
-; CHECK: shift3b:
+; CHECK-LABEL: shift3b:
 ; CHECK: movzwl
 ; CHECK: movd
 ; CHECK: psraw
   %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
   %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
-  %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
-  %3 = insertelement <8 x i16> %0, i16 %amt, i32 3
-  %4 = insertelement <8 x i16> %0, i16 %amt, i32 4
-  %5 = insertelement <8 x i16> %0, i16 %amt, i32 5
-  %6 = insertelement <8 x i16> %0, i16 %amt, i32 6
-  %7 = insertelement <8 x i16> %0, i16 %amt, i32 7
+  %2 = insertelement <8 x i16> %1, i16 %amt, i32 2
+  %3 = insertelement <8 x i16> %2, i16 %amt, i32 3
+  %4 = insertelement <8 x i16> %3, i16 %amt, i32 4
+  %5 = insertelement <8 x i16> %4, i16 %amt, i32 5
+  %6 = insertelement <8 x i16> %5, i16 %amt, i32 6
+  %7 = insertelement <8 x i16> %6, i16 %amt, i32 7
   %ashr = ashr <8 x i16> %val, %7
   store <8 x i16> %ashr, <8 x i16>* %dst
   ret void
diff --git a/test/CodeGen/X86/vshift-4.ll b/test/CodeGen/X86/vshift-4.ll
index 8e24fda..4363cd9 100644
--- a/test/CodeGen/X86/vshift-4.ll
+++ b/test/CodeGen/X86/vshift-4.ll
@@ -5,7 +5,7 @@
 
 define void @shift1a(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
 entry:
-; CHECK: shift1a:
+; CHECK-LABEL: shift1a:
 ; CHECK: psllq
   %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
   %shl = shl <2 x i64> %val, %shamt
@@ -16,7 +16,7 @@ entry:
 ; shift1b can't use a packed shift
 define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
 entry:
-; CHECK: shift1b:
+; CHECK-LABEL: shift1b:
 ; CHECK: shll
   %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1>
   %shl = shl <2 x i64> %val, %shamt
@@ -26,7 +26,7 @@ entry:
 
 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
 entry:
-; CHECK: shift2a:
+; CHECK-LABEL: shift2a:
 ; CHECK: pslld
   %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %shl = shl <4 x i32> %val, %shamt
@@ -36,7 +36,7 @@ entry:
 
 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
 entry:
-; CHECK: shift2b:
+; CHECK-LABEL: shift2b:
 ; CHECK: pslld
   %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1>
   %shl = shl <4 x i32> %val, %shamt
@@ -46,7 +46,7 @@ entry:
 
 define void @shift2c(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
 entry:
-; CHECK: shift2c:
+; CHECK-LABEL: shift2c:
 ; CHECK: pslld
   %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
   %shl = shl <4 x i32> %val, %shamt
@@ -56,7 +56,7 @@ entry:
 
 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
 entry:
-; CHECK: shift3a:
+; CHECK-LABEL: shift3a:
 ; CHECK: movzwl
 ; CHECK: psllw
   %shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
@@ -67,17 +67,17 @@ entry:
 
 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
 entry:
-; CHECK: shift3b:
+; CHECK-LABEL: shift3b:
 ; CHECK: movzwl
 ; CHECK: psllw
   %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
   %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
-  %2 = insertelement <8 x i16> %0, i16 %amt, i32 2
-  %3 = insertelement <8 x i16> %0, i16 %amt, i32 3
-  %4 = insertelement <8 x i16> %0, i16 %amt, i32 4
-  %5 = insertelement <8 x i16> %0, i16 %amt, i32 5
-  %6 = insertelement <8 x i16> %0, i16 %amt, i32 6
-  %7 = insertelement <8 x i16> %0, i16 %amt, i32 7
+  %2 = insertelement <8 x i16> %1, i16 %amt, i32 2
+  %3 = insertelement <8 x i16> %2, i16 %amt, i32 3
+  %4 = insertelement <8 x i16> %3, i16 %amt, i32 4
+  %5 = insertelement <8 x i16> %4, i16 %amt, i32 5
+  %6 = insertelement <8 x i16> %5, i16 %amt, i32 6
+  %7 = insertelement <8 x i16> %6, i16 %amt, i32 7
   %shl = shl <8 x i16> %val, %7
   store <8 x i16> %shl, <8 x i16>* %dst
   ret void
diff --git a/test/CodeGen/X86/vshift-5.ll b/test/CodeGen/X86/vshift-5.ll
index f6c311d..562e520 100644
--- a/test/CodeGen/X86/vshift-5.ll
+++ b/test/CodeGen/X86/vshift-5.ll
@@ -4,7 +4,7 @@
 
 define void @shift5a(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
 entry:
-; CHECK: shift5a:
+; CHECK-LABEL: shift5a:
 ; CHECK: movd
 ; CHECK: pslld
   %amt = load i32* %pamt 
@@ -18,7 +18,7 @@ entry:
 
 define void @shift5b(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
 entry:
-; CHECK: shift5b:
+; CHECK-LABEL: shift5b:
 ; CHECK: movd
 ; CHECK: psrad
   %amt = load i32* %pamt 
@@ -32,7 +32,7 @@ entry:
 
 define void @shift5c(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
 entry:
-; CHECK: shift5c:
+; CHECK-LABEL: shift5c:
 ; CHECK: movd
 ; CHECK: pslld
   %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
@@ -45,7 +45,7 @@ entry:
 
 define void @shift5d(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
 entry:
-; CHECK: shift5d:
+; CHECK-LABEL: shift5d:
 ; CHECK: movd
 ; CHECK: psrad
   %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
diff --git a/test/CodeGen/X86/wide-fma-contraction.ll b/test/CodeGen/X86/wide-fma-contraction.ll
index d93f33b..f51f917 100644
--- a/test/CodeGen/X86/wide-fma-contraction.ll
+++ b/test/CodeGen/X86/wide-fma-contraction.ll
@@ -1,7 +1,10 @@
-; RUN: llc -march=x86 -mattr=+fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s
+; RUN: llc -march=x86 -mcpu=bdver2 -mattr=-fma -mtriple=x86_64-apple-darwin < %s | FileCheck %s
+; RUN: llc -march=x86 -mcpu=bdver2 -mattr=-fma,-fma4 -mtriple=x86_64-apple-darwin < %s | FileCheck %s --check-prefix=CHECK-NOFMA
 
-; CHECK: fmafunc
+; CHECK-LABEL: fmafunc
+; CHECK-NOFMA-LABEL: fmafunc
 define <16 x float> @fmafunc(<16 x float> %a, <16 x float> %b, <16 x float> %c) {
+
 ; CHECK-NOT: vmulps
 ; CHECK-NOT: vaddps
 ; CHECK: vfmaddps
@@ -10,11 +13,17 @@ define <16 x float> @fmafunc(<16 x float> %a, <16 x float> %b, <16 x float> %c)
 ; CHECK: vfmaddps
 ; CHECK-NOT: vmulps
 ; CHECK-NOT: vaddps
+
+; CHECK-NOFMA-NOT: calll
+; CHECK-NOFMA: vmulps
+; CHECK-NOFMA: vaddps
+; CHECK-NOFMA-NOT: calll
+; CHECK-NOFMA: vmulps
+; CHECK-NOFMA: vaddps
+; CHECK-NOFMA-NOT: calll
+
   %ret = tail call <16 x float> @llvm.fmuladd.v16f32(<16 x float> %a, <16 x float> %b, <16 x float> %c)
   ret <16 x float> %ret
 }
 
 declare <16 x float> @llvm.fmuladd.v16f32(<16 x float>, <16 x float>, <16 x float>) nounwind readnone
-
-
-
diff --git a/test/CodeGen/X86/widen_arith-4.ll b/test/CodeGen/X86/widen_arith-4.ll
index 5931d63..63c8d0e 100644
--- a/test/CodeGen/X86/widen_arith-4.ll
+++ b/test/CodeGen/X86/widen_arith-4.ll
@@ -33,7 +33,7 @@ forbody:		; preds = %forcond
 	%arrayidx6 = getelementptr <5 x i16>* %tmp5, i32 %tmp4		; <<5 x i16>*> [#uses=1]
 	%tmp7 = load <5 x i16>* %arrayidx6		; <<5 x i16>> [#uses=1]
 	%sub = sub <5 x i16> %tmp7, < i16 271, i16 271, i16 271, i16 271, i16 271 >		; <<5 x i16>> [#uses=1]
-	%mul = mul <5 x i16> %sub, < i16 2, i16 2, i16 2, i16 2, i16 2 >		; <<5 x i16>> [#uses=1]
+	%mul = mul <5 x i16> %sub, < i16 2, i16 4, i16 2, i16 2, i16 2 >		; <<5 x i16>> [#uses=1]
 	store <5 x i16> %mul, <5 x i16>* %arrayidx
 	br label %forinc
 
diff --git a/test/CodeGen/X86/widen_arith-5.ll b/test/CodeGen/X86/widen_arith-5.ll
index 7f2eff0..41df0e4 100644
--- a/test/CodeGen/X86/widen_arith-5.ll
+++ b/test/CodeGen/X86/widen_arith-5.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+sse42  | FileCheck %s
 ; CHECK: movdqa
-; CHECK: pmulld
+; CHECK: pslld $2
 ; CHECK: psubd
 
 ; widen a v3i32 to v4i32 to do a vector multiple and a subtraction
diff --git a/test/CodeGen/X86/widen_conv-2.ll b/test/CodeGen/X86/widen_conv-2.ll
index 969cb51..db8fa93 100644
--- a/test/CodeGen/X86/widen_conv-2.ll
+++ b/test/CodeGen/X86/widen_conv-2.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
-; CHECK: movswl
-; CHECK: movswl
+; CHECK: cwtl
+; CHECK: cwtl
 
 ; sign extension v2i32 to v2i16
 
diff --git a/test/CodeGen/X86/widen_extract-1.ll b/test/CodeGen/X86/widen_extract-1.ll
index 8672742..c4fe43a 100644
--- a/test/CodeGen/X86/widen_extract-1.ll
+++ b/test/CodeGen/X86/widen_extract-1.ll
@@ -3,7 +3,7 @@
 
 define void @convert(<2 x double>* %dst.addr, <3 x double> %src)  {
 entry:
-; CHECK: convert:
+; CHECK-LABEL: convert:
 ; CHECK: unpcklpd {{%xmm[0-7]}}, {{%xmm[0-7]}}
 ; CHECK-NEXT: movapd
   %val = shufflevector <3 x double> %src, <3 x double> undef, <2 x i32> < i32 0, i32 1>
diff --git a/test/CodeGen/X86/widen_load-2.ll b/test/CodeGen/X86/widen_load-2.ll
index 224898c..f0f94e4 100644
--- a/test/CodeGen/X86/widen_load-2.ll
+++ b/test/CodeGen/X86/widen_load-2.ll
@@ -73,7 +73,6 @@ define void @add12i32(%i32vec12*  sret %ret, %i32vec12* %ap, %i32vec12* %bp)  {
 ; CHECK: add3i16
 %i16vec3 = type <3 x i16>
 define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind {
-; CHECK: add3i16
 ; CHECK: addl
 ; CHECK: addl
 ; CHECK: addl
@@ -88,7 +87,6 @@ define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp
 ; CHECK: add4i16
 %i16vec4 = type <4 x i16>
 define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp) nounwind {
-; CHECK: add4i16
 ; CHECK: paddd
 ; CHECK: movq
 	%a = load %i16vec4* %ap, align 16
@@ -148,7 +146,7 @@ define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) no
 	ret void
 }
 
-; CHECK: add31i8:
+; CHECK-LABEL: add31i8:
 %i8vec31 = type <31 x i8>
 define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind {
 ; CHECK: movdqa
diff --git a/test/CodeGen/X86/widen_shuffle-1.ll b/test/CodeGen/X86/widen_shuffle-1.ll
index 7bebb27..c7d2044 100644
--- a/test/CodeGen/X86/widen_shuffle-1.ll
+++ b/test/CodeGen/X86/widen_shuffle-1.ll
@@ -3,7 +3,7 @@
 ; widening shuffle v3float and then a add
 define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
 entry:
-; CHECK: shuf:
+; CHECK-LABEL: shuf:
 ; CHECK: extractps
 ; CHECK: extractps
 	%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2>
@@ -17,7 +17,7 @@ entry:
 ; widening shuffle v3float with a different mask and then a add
 define void @shuf2(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
 entry:
-; CHECK: shuf2:
+; CHECK-LABEL: shuf2:
 ; CHECK: extractps
 ; CHECK: extractps
 	%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 4, i32 2>
@@ -32,7 +32,7 @@ entry:
 ; opA with opB, the DAG will produce new operations with opA.
 define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) nounwind {
 entry:
-; CHECK: shuf3:
+; CHECK-LABEL: shuf3:
 ; CHECK: shufps
   %shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
   %tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> 
@@ -52,7 +52,7 @@ entry:
 
 ; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS
 define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone {
-; CHECK: shuf4:
+; CHECK-LABEL: shuf4:
 ; CHECK-NOT: punpckldq
   %vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i8> %vshuf
@@ -61,7 +61,7 @@ define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone {
 
 ; PR11389: another CONCAT_VECTORS case
 define void @shuf5(<8 x i8>* %p) nounwind {
-; CHECK: shuf5:
+; CHECK-LABEL: shuf5:
   %v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   store <8 x i8> %v, <8 x i8>* %p, align 8
   ret void
diff --git a/test/CodeGen/X86/win64_alloca_dynalloca.ll b/test/CodeGen/X86/win64_alloca_dynalloca.ll
index cc11e4c..275ebf9 100644
--- a/test/CodeGen/X86/win64_alloca_dynalloca.ll
+++ b/test/CodeGen/X86/win64_alloca_dynalloca.ll
@@ -19,7 +19,7 @@ entry:
 ; W64: movq  %rsp, %rbp
 ; W64:       $4096, %rax
 ; W64: callq __chkstk
-; W64: subq  $4096, %rsp
+; W64: subq  %rax, %rsp
 
 ; Freestanding
 ; EFI: movq  %rsp, %rbp
diff --git a/test/CodeGen/X86/win64_params.ll b/test/CodeGen/X86/win64_params.ll
index f9d4bf9..9718c86 100644
--- a/test/CodeGen/X86/win64_params.ll
+++ b/test/CodeGen/X86/win64_params.ll
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mtriple=x86_64-pc-win32 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s -check-prefix=LINUX
 
 ; Verify that the 5th and 6th parameters are coming from the correct location
 ; on the stack.
@@ -6,6 +7,30 @@ define i32 @f6(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6) nounwind re
 entry:
 ; CHECK: movl    48(%rsp), %eax
 ; CHECK: addl    40(%rsp), %eax
+; LINUX: addl    %r9d, %r8d
+; LINUX: movl    %r8d, %eax
+  %add = add nsw i32 %p6, %p5
+  ret i32 %add
+}
+
+define x86_64_win64cc i32 @f7(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6) nounwind readnone optsize {
+entry:
+; CHECK: movl    48(%rsp), %eax
+; CHECK: addl    40(%rsp), %eax
+; LINUX: movl    48(%rsp), %eax
+; LINUX: addl    40(%rsp), %eax
+  %add = add nsw i32 %p6, %p5
+  ret i32 %add
+}
+
+; Verify that even though we're compiling for Windows, parameters behave as
+; on other platforms here (note the x86_64_sysvcc calling convention).
+define x86_64_sysvcc i32 @f8(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6) nounwind readnone optsize {
+entry:
+; CHECK: addl    %r9d, %r8d
+; CHECK: movl    %r8d, %eax
+; LINUX: addl    %r9d, %r8d
+; LINUX: movl    %r8d, %eax
   %add = add nsw i32 %p6, %p5
   ret i32 %add
 }
diff --git a/test/CodeGen/X86/win64_vararg.ll b/test/CodeGen/X86/win64_vararg.ll
index 52bc509..1a51b2a 100644
--- a/test/CodeGen/X86/win64_vararg.ll
+++ b/test/CodeGen/X86/win64_vararg.ll
@@ -18,8 +18,9 @@ entry:
 }
 
 declare void @llvm.va_start(i8*) nounwind
+declare void @llvm.va_copy(i8*, i8*) nounwind
 
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: pushq
 ; CHECK: leaq 56(%rsp),
 define i8* @f5(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, ...) nounwind {
@@ -30,7 +31,7 @@ entry:
   ret i8* %ap1
 }
 
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: pushq
 ; CHECK: leaq 48(%rsp),
 define i8* @f4(i64 %a0, i64 %a1, i64 %a2, i64 %a3, ...) nounwind {
@@ -41,7 +42,7 @@ entry:
   ret i8* %ap1
 }
 
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: pushq
 ; CHECK: leaq 40(%rsp),
 define i8* @f3(i64 %a0, i64 %a1, i64 %a2, ...) nounwind {
@@ -51,3 +52,62 @@ entry:
   call void @llvm.va_start(i8* %ap1)
   ret i8* %ap1
 }
+
+; WinX86_64 uses char* for va_list. Verify that the correct amount of bytes
+; are copied using va_copy.
+
+; CHECK-LABEL: copy1:
+; CHECK: subq $16
+; CHECK: leaq 32(%rsp), [[REG_copy1:%[a-z]+]]
+; CHECK: movq [[REG_copy1]], 8(%rsp)
+; CHECK: movq [[REG_copy1]], (%rsp)
+; CHECK: addq $16
+; CHECK: ret
+define void @copy1(i64 %a0, ...) nounwind {
+entry:
+  %ap = alloca i8*, align 8
+  %cp = alloca i8*, align 8
+  %ap1 = bitcast i8** %ap to i8*
+  %cp1 = bitcast i8** %cp to i8*
+  call void @llvm.va_start(i8* %ap1)
+  call void @llvm.va_copy(i8* %cp1, i8* %ap1)
+  ret void
+}
+
+; CHECK-LABEL: copy4:
+; CHECK: subq $16
+; CHECK: leaq 56(%rsp), [[REG_copy4:%[a-z]+]]
+; CHECK: movq [[REG_copy4]], 8(%rsp)
+; CHECK: movq [[REG_copy4]], (%rsp)
+; CHECK: addq $16
+; CHECK: ret
+define void @copy4(i64 %a0, i64 %a1, i64 %a2, i64 %a3, ...) nounwind {
+entry:
+  %ap = alloca i8*, align 8
+  %cp = alloca i8*, align 8
+  %ap1 = bitcast i8** %ap to i8*
+  %cp1 = bitcast i8** %cp to i8*
+  call void @llvm.va_start(i8* %ap1)
+  call void @llvm.va_copy(i8* %cp1, i8* %ap1)
+  ret void
+}
+
+; CHECK-LABEL: arg4:
+; CHECK: pushq
+; va_start:
+; CHECK: leaq 48(%rsp), [[REG_arg4_1:%[a-z]+]]
+; CHECK: movq [[REG_arg4_1]], (%rsp)
+; va_arg:
+; CHECK: leaq 52(%rsp), [[REG_arg4_2:%[a-z]+]]
+; CHECK: movq [[REG_arg4_2]], (%rsp)
+; CHECK: movl 48(%rsp), %eax
+; CHECK: popq
+; CHECK: ret
+define i32 @arg4(i64 %a0, i64 %a1, i64 %a2, i64 %a3, ...) nounwind {
+entry:
+  %ap = alloca i8*, align 8
+  %ap1 = bitcast i8** %ap to i8*
+  call void @llvm.va_start(i8* %ap1)
+  %tmp = va_arg i8** %ap, i32
+  ret i32 %tmp
+}
diff --git a/test/CodeGen/X86/win_chkstk.ll b/test/CodeGen/X86/win_chkstk.ll
index e4e4483..3f522ea 100644
--- a/test/CodeGen/X86/win_chkstk.ll
+++ b/test/CodeGen/X86/win_chkstk.ll
@@ -45,3 +45,16 @@ entry:
   %array128 = alloca [128 x i8], align 16         ; <[128 x i8]*> [#uses=0]
   ret i32 0
 }
+
+; Make sure we don't call __chkstk or __alloca on non-Windows even if the
+; caller has the Win64 calling convention.
+define x86_64_win64cc i32 @main4k_win64() nounwind {
+entry:
+; WIN_X32:    calll __chkstk
+; WIN_X64:    callq __chkstk
+; MINGW_X32:  calll __alloca
+; MINGW_X64:  callq ___chkstk
+; LINUX-NOT:  call __chkstk
+  %array4096 = alloca [4096 x i8], align 16       ; <[4096 x i8]*> [#uses=0]
+  ret i32 0
+}
diff --git a/test/CodeGen/X86/x86-64-and-mask.ll b/test/CodeGen/X86/x86-64-and-mask.ll
index 07ccb23..bc6c612 100644
--- a/test/CodeGen/X86/x86-64-and-mask.ll
+++ b/test/CodeGen/X86/x86-64-and-mask.ll
@@ -1,10 +1,10 @@
-; RUN: llc < %s | FileCheck %s
+; RUN: llc -mcpu=corei7 < %s | FileCheck %s
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-apple-darwin8"
 
 ; This should be a single mov, not a load of immediate + andq.
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: movl %edi, %eax
 
 define i64 @test(i64 %x) nounwind {
@@ -14,7 +14,7 @@ entry:
 }
 
 ; This copy can't be coalesced away because it needs the implicit zero-extend.
-; CHECK: bbb:
+; CHECK-LABEL: bbb:
 ; CHECK: movl %edi, %edi
 
 define void @bbb(i64 %x) nounwind {
@@ -26,7 +26,7 @@ define void @bbb(i64 %x) nounwind {
 ; This should use a 32-bit and with implicit zero-extension, not a 64-bit and
 ; with a separate mov to materialize the mask.
 ; rdar://7527390
-; CHECK: ccc:
+; CHECK-LABEL: ccc:
 ; CHECK: andl $-1048593, %edi
 
 declare void @foo(i64 %x) nounwind
@@ -38,9 +38,9 @@ define void @ccc(i64 %x) nounwind {
 }
 
 ; This requires a mov and a 64-bit and.
-; CHECK: ddd:
+; CHECK-LABEL: ddd:
 ; CHECK: movabsq $4294967296, %r
-; CHECK: andq %rax, %rdi
+; CHECK: andq %r{{..}}, %r{{..}}
 
 define void @ddd(i64 %x) nounwind {
   %t = and i64 %x, 4294967296
diff --git a/test/CodeGen/X86/x86-64-psub.ll b/test/CodeGen/X86/x86-64-psub.ll
index 7869a80..be09a4f 100644
--- a/test/CodeGen/X86/x86-64-psub.ll
+++ b/test/CodeGen/X86/x86-64-psub.ll
@@ -26,7 +26,7 @@ entry:
   ret i64 %retval.0.extract.i15
 }
 
-; CHECK: test_psubb:
+; CHECK-LABEL: test_psubb:
 ; CHECK:   callq getFirstParam
 ; CHECK:   callq getSecondParam
 ; CHECK:   movd %rax, [[PARAM2:%[a-z0-9]+]]
@@ -53,7 +53,7 @@ entry:
   ret i64 %retval.0.extract.i15
 }
 
-; CHECK: test_psubw:
+; CHECK-LABEL: test_psubw:
 ; CHECK:   callq getFirstParam
 ; CHECK:   callq getSecondParam
 ; CHECK:   movd %rax, [[PARAM2:%[a-z0-9]+]]
@@ -81,7 +81,7 @@ entry:
   ret i64 %retval.0.extract.i15
 }
 
-; CHECK: test_psubd:
+; CHECK-LABEL: test_psubd:
 ; CHECK:   callq getFirstParam
 ; CHECK:   callq getSecondParam
 ; CHECK:   movd %rax, [[PARAM2:%[a-z0-9]+]]
@@ -108,7 +108,7 @@ entry:
   ret i64 %retval.0.extract.i15
 }
 
-; CHECK: test_psubsb:
+; CHECK-LABEL: test_psubsb:
 ; CHECK:   callq getFirstParam
 ; CHECK:   callq getSecondParam
 ; CHECK:   movd %rax, [[PARAM2:%[a-z0-9]+]]
@@ -135,7 +135,7 @@ entry:
   ret i64 %retval.0.extract.i15
 }
 
-; CHECK: test_psubswv:
+; CHECK-LABEL: test_psubswv:
 ; CHECK:   callq getFirstParam
 ; CHECK:   callq getSecondParam
 ; CHECK:   movd %rax, [[PARAM2:%[a-z0-9]+]]
@@ -162,7 +162,7 @@ entry:
   ret i64 %retval.0.extract.i15
 }
 
-; CHECK: test_psubusbv:
+; CHECK-LABEL: test_psubusbv:
 ; CHECK:   callq getFirstParam
 ; CHECK:   callq getSecondParam
 ; CHECK:   movd %rax, [[PARAM2:%[a-z0-9]+]]
@@ -189,7 +189,7 @@ entry:
   ret i64 %retval.0.extract.i15
 }
 
-; CHECK: test_psubuswv:
+; CHECK-LABEL: test_psubuswv:
 ; CHECK:   callq getFirstParam
 ; CHECK:   callq getSecondParam
 ; CHECK:   movd %rax, [[PARAM2:%[a-z0-9]+]]
diff --git a/test/CodeGen/X86/x86-64-sret-return.ll b/test/CodeGen/X86/x86-64-sret-return.ll
index bc8a543..2d00114 100644
--- a/test/CodeGen/X86/x86-64-sret-return.ll
+++ b/test/CodeGen/X86/x86-64-sret-return.ll
@@ -4,11 +4,11 @@
 
 %struct.foo = type { [4 x i64] }
 
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: movq %rdi, %rax
 
 ; For the x32 ABI, pointers are 32-bit so 32-bit instructions will be used
-; X32ABI: bar:
+; X32ABI-LABEL: bar:
 ; X32ABI: movl %edi, %eax
 
 define void @bar(%struct.foo* noalias sret  %agg.result, %struct.foo* %d) nounwind  {
@@ -60,11 +60,11 @@ return:		; preds = %entry
 	ret void
 }
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: movq %rdi, %rax
 
 ; For the x32 ABI, pointers are 32-bit so 32-bit instructions will be used
-; X32ABI: foo:
+; X32ABI-LABEL: foo:
 ; X32ABI: movl %edi, %eax
 
 define void @foo({ i64 }* noalias nocapture sret %agg.result) nounwind {
diff --git a/test/CodeGen/X86/x86-shifts.ll b/test/CodeGen/X86/x86-shifts.ll
index 20bccab..af57e5c 100644
--- a/test/CodeGen/X86/x86-shifts.ll
+++ b/test/CodeGen/X86/x86-shifts.ll
@@ -156,7 +156,7 @@ entry:
 define <16 x i8> @shl9(<16 x i8> %A) nounwind {
   %B = shl <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ret <16 x i8> %B
-; CHECK: shl9:
+; CHECK-LABEL: shl9:
 ; CHECK: psllw $3
 ; CHECK: pand
 ; CHECK: ret
@@ -165,7 +165,7 @@ define <16 x i8> @shl9(<16 x i8> %A) nounwind {
 define <16 x i8> @shr9(<16 x i8> %A) nounwind {
   %B = lshr <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ret <16 x i8> %B
-; CHECK: shr9:
+; CHECK-LABEL: shr9:
 ; CHECK: psrlw $3
 ; CHECK: pand
 ; CHECK: ret
@@ -174,7 +174,7 @@ define <16 x i8> @shr9(<16 x i8> %A) nounwind {
 define <16 x i8> @sra_v16i8_7(<16 x i8> %A) nounwind {
   %B = ashr <16 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
   ret <16 x i8> %B
-; CHECK: sra_v16i8_7:
+; CHECK-LABEL: sra_v16i8_7:
 ; CHECK: pxor
 ; CHECK: pcmpgtb
 ; CHECK: ret
@@ -183,7 +183,7 @@ define <16 x i8> @sra_v16i8_7(<16 x i8> %A) nounwind {
 define <16 x i8> @sra_v16i8(<16 x i8> %A) nounwind {
   %B = ashr <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
   ret <16 x i8> %B
-; CHECK: sra_v16i8:
+; CHECK-LABEL: sra_v16i8:
 ; CHECK: psrlw $3
 ; CHECK: pand
 ; CHECK: pxor
diff --git a/test/CodeGen/X86/xmulo.ll b/test/CodeGen/X86/xmulo.ll
index 486dafe..71efac4 100644
--- a/test/CodeGen/X86/xmulo.ll
+++ b/test/CodeGen/X86/xmulo.ll
@@ -8,7 +8,7 @@ declare i32 @printf(i8*, ...)
 @.str = private unnamed_addr constant [10 x i8] c"%llx, %d\0A\00", align 1
 
 define i32 @t1() nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK:  movl $0, 12(%esp)
 ; CHECK:  movl $0, 8(%esp)
 ; CHECK:  movl $72, 4(%esp)
@@ -22,7 +22,7 @@ define i32 @t1() nounwind {
 }
 
 define i32 @t2() nounwind {
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK:  movl $0, 12(%esp)
 ; CHECK:  movl $0, 8(%esp)
 ; CHECK:  movl $0, 4(%esp)
@@ -36,7 +36,7 @@ define i32 @t2() nounwind {
 }
 
 define i32 @t3() nounwind {
-; CHECK: t3:
+; CHECK-LABEL: t3:
 ; CHECK:  movl $1, 12(%esp)
 ; CHECK:  movl $-1, 8(%esp)
 ; CHECK:  movl $-9, 4(%esp)
diff --git a/test/CodeGen/X86/xor-icmp.ll b/test/CodeGen/X86/xor-icmp.ll
index fd1b006..dd1fcca 100644
--- a/test/CodeGen/X86/xor-icmp.ll
+++ b/test/CodeGen/X86/xor-icmp.ll
@@ -4,14 +4,14 @@
 
 define i32 @t(i32 %a, i32 %b) nounwind ssp {
 entry:
-; X32:     t:
+; X32-LABEL:     t:
 ; X32:     xorb
 ; X32-NOT: andb
 ; X32-NOT: shrb
 ; X32:     testb $64
 ; X32:     je
 
-; X64:     t:
+; X64-LABEL:     t:
 ; X64-NOT: setne
 ; X64:     xorl
 ; X64:     testb $64
@@ -37,7 +37,7 @@ declare i32 @foo(...)
 declare i32 @bar(...)
 
 define i32 @t2(i32 %x, i32 %y) nounwind ssp {
-; X32: t2:
+; X32-LABEL: t2:
 ; X32: cmpl
 ; X32: sete
 ; X32: cmpl
@@ -45,7 +45,7 @@ define i32 @t2(i32 %x, i32 %y) nounwind ssp {
 ; X32-NOT: xor
 ; X32: je
 
-; X64: t2:
+; X64-LABEL: t2:
 ; X64: testl
 ; X64: sete
 ; X64: testl
diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll
index 574bb78..b56ce0f 100644
--- a/test/CodeGen/X86/xor.ll
+++ b/test/CodeGen/X86/xor.ll
@@ -7,7 +7,7 @@ define <4 x i32> @test1() nounwind {
 	%tmp = xor <4 x i32> undef, undef
 	ret <4 x i32> %tmp
         
-; X32: test1:
+; X32-LABEL: test1:
 ; X32:	xorps	%xmm0, %xmm0
 ; X32:	ret
 }
@@ -16,7 +16,7 @@ define <4 x i32> @test1() nounwind {
 define i32 @test2() nounwind{
 	%tmp = xor i32 undef, undef
 	ret i32 %tmp
-; X32: test2:
+; X32-LABEL: test2:
 ; X32:	xorl	%eax, %eax
 ; X32:	ret
 }
@@ -28,13 +28,13 @@ entry:
         %tmp4 = lshr i32 %tmp3, 1
         ret i32 %tmp4
         
-; X64: test3:
+; X64-LABEL: test3:
 ; X64:	notl
 ; X64:	andl
 ; X64:	shrl
 ; X64:	ret
 
-; X32: test3:
+; X32-LABEL: test3:
 ; X32: 	movl	8(%esp), %eax
 ; X32: 	notl	%eax
 ; X32: 	andl	4(%esp), %eax
@@ -57,10 +57,10 @@ bb:
 bb12:
 	ret i32 %tmp3
         
-; X64: test4:
+; X64-LABEL: test4:
 ; X64:    notl	[[REG:%[a-z]+]]
 ; X64:    andl	{{.*}}[[REG]]
-; X32: test4:
+; X32-LABEL: test4:
 ; X32:    notl	[[REG:%[a-z]+]]
 ; X32:    andl	{{.*}}[[REG]]
 }
@@ -79,10 +79,10 @@ bb:
 	br i1 %tmp10, label %bb12, label %bb
 bb12:
 	ret i16 %tmp3
-; X64: test5:
+; X64-LABEL: test5:
 ; X64:    notl	[[REG:%[a-z]+]]
 ; X64:    andl	{{.*}}[[REG]]
-; X32: test5:
+; X32-LABEL: test5:
 ; X32:    notl	[[REG:%[a-z]+]]
 ; X32:    andl	{{.*}}[[REG]]
 }
@@ -101,10 +101,10 @@ bb:
 	br i1 %tmp10, label %bb12, label %bb
 bb12:
 	ret i8 %tmp3
-; X64: test6:
+; X64-LABEL: test6:
 ; X64:    notb	[[REG:%[a-z]+]]
 ; X64:    andb	{{.*}}[[REG]]
-; X32: test6:
+; X32-LABEL: test6:
 ; X32:    notb	[[REG:%[a-z]+]]
 ; X32:    andb	{{.*}}[[REG]]
 }
@@ -123,10 +123,10 @@ bb:
 	br i1 %tmp10, label %bb12, label %bb
 bb12:
 	ret i32 %tmp3
-; X64: test7:
+; X64-LABEL: test7:
 ; X64:    xorl	$2147483646, [[REG:%[a-z]+]]
 ; X64:    andl	{{.*}}[[REG]]
-; X32: test7:
+; X32-LABEL: test7:
 ; X32:    xorl	$2147483646, [[REG:%[a-z]+]]
 ; X32:    andl	{{.*}}[[REG]]
 }
@@ -137,9 +137,9 @@ entry:
   %t1 = sub i32 0, %a
   %t2 = add i32 %t1, -1
   ret i32 %t2
-; X64: test8:
+; X64-LABEL: test8:
 ; X64:   notl {{%eax|%edi|%ecx}}
-; X32: test8:
+; X32-LABEL: test8:
 ; X32:   notl %eax
 }
 
@@ -147,10 +147,10 @@ define i32 @test9(i32 %a) nounwind {
   %1 = and i32 %a, 4096
   %2 = xor i32 %1, 4096
   ret i32 %2
-; X64: test9:
+; X64-LABEL: test9:
 ; X64:    notl	[[REG:%[a-z]+]]
 ; X64:    andl	{{.*}}[[REG:%[a-z]+]]
-; X32: test9:
+; X32-LABEL: test9:
 ; X32:    notl	[[REG:%[a-z]+]]
 ; X32:    andl	{{.*}}[[REG:%[a-z]+]]
 }
@@ -160,8 +160,8 @@ define <4 x i32> @test10(<4 x i32> %a) nounwind {
   %1 = and <4 x i32> %a, <i32 4096, i32 4096, i32 4096, i32 4096>
   %2 = xor <4 x i32> %1, <i32 4096, i32 4096, i32 4096, i32 4096>
   ret <4 x i32> %2
-; X64: test10:
+; X64-LABEL: test10:
 ; X64:    andnps
-; X32: test10:
+; X32-LABEL: test10:
 ; X32:    andnps
 }
diff --git a/test/CodeGen/X86/zero-remat.ll b/test/CodeGen/X86/zero-remat.ll
index 5d25a2d..e3c3c5e 100644
--- a/test/CodeGen/X86/zero-remat.ll
+++ b/test/CodeGen/X86/zero-remat.ll
@@ -11,12 +11,12 @@ define double @foo() nounwind {
   call void @bar(double 0.0)
   ret double 0.0
 
-;CHECK-32: foo:
+;CHECK-32-LABEL: foo:
 ;CHECK-32: call
 ;CHECK-32: fldz
 ;CHECK-32: ret
 
-;CHECK-64: foo:
+;CHECK-64-LABEL: foo:
 ;CHECK-64: xorps
 ;CHECK-64: call
 ;CHECK-64: xorps
@@ -28,12 +28,12 @@ define float @foof() nounwind {
   call void @barf(float 0.0)
   ret float 0.0
 
-;CHECK-32: foof:
+;CHECK-32-LABEL: foof:
 ;CHECK-32: call
 ;CHECK-32: fldz
 ;CHECK-32: ret
 
-;CHECK-64: foof:
+;CHECK-64-LABEL: foof:
 ;CHECK-64: xorps
 ;CHECK-64: call
 ;CHECK-64: xorps
diff --git a/test/CodeGen/X86/zext-extract_subreg.ll b/test/CodeGen/X86/zext-extract_subreg.ll
index 7fa0574..43e79c7 100644
--- a/test/CodeGen/X86/zext-extract_subreg.ll
+++ b/test/CodeGen/X86/zext-extract_subreg.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
 
 define void @t() nounwind ssp {
-; CHECK: t:
+; CHECK-LABEL: t:
 entry:
   br i1 undef, label %return, label %if.end.i
 
diff --git a/test/CodeGen/X86/zext-sext.ll b/test/CodeGen/X86/zext-sext.ll
index 0ab302a..25dabbe 100644
--- a/test/CodeGen/X86/zext-sext.ll
+++ b/test/CodeGen/X86/zext-sext.ll
@@ -35,7 +35,7 @@ entry:
 
 ; CHECK:      addl	$2138875574, %e[[REGISTER_zext:[a-z0-9]+]]
 ; CHECK-NEXT: cmpl	$-8608074, %e[[REGISTER_zext]]
-; CHECK-NEXT: movslq	%e[[REGISTER_zext]], [[REGISTER_tmp:%r[a-z0-9]+]]
+; CHECK:      movslq	%e[[REGISTER_zext]], [[REGISTER_tmp:%r[a-z0-9]+]]
 ; CHECK:      movq	[[REGISTER_tmp]], [[REGISTER_sext:%r[a-z0-9]+]]
 ; CHECK-NOT:  [[REGISTER_zext]]
 ; CHECK:      subq	%r[[REGISTER_zext]], [[REGISTER_sext]]
diff --git a/test/CodeGen/X86/zext-shl.ll b/test/CodeGen/X86/zext-shl.ll
index 928848e..ac3ecc8 100644
--- a/test/CodeGen/X86/zext-shl.ll
+++ b/test/CodeGen/X86/zext-shl.ll
@@ -2,7 +2,7 @@
 
 define i32 @t1(i8 zeroext %x) nounwind readnone ssp {
 entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
 ; CHECK: shll
 ; CHECK-NOT: movzwl
 ; CHECK: ret
@@ -14,7 +14,7 @@ entry:
 
 define i32 @t2(i8 zeroext %x) nounwind readnone ssp {
 entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
 ; CHECK: shrl
 ; CHECK-NOT: movzwl
 ; CHECK: ret
diff --git a/test/CodeGen/X86/zext-trunc.ll b/test/CodeGen/X86/zext-trunc.ll
index b9ffbe8..32afd6b 100644
--- a/test/CodeGen/X86/zext-trunc.ll
+++ b/test/CodeGen/X86/zext-trunc.ll
@@ -2,7 +2,7 @@
 ; rdar://7570931
 
 define i64 @foo(i64 %a, i64 %b) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: leal
 ; CHECK-NOT: movl
 ; CHECK: ret
diff --git a/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll b/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll
index 84e21e4..2a04963 100644
--- a/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll
+++ b/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll
@@ -13,7 +13,7 @@ allocas:
   call void @llvm.stackrestore(i8* %0)
   ret void
 }
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: ldaw [[REGISTER:r[0-9]+]], {{r[0-9]+}}[-r1]
 ; CHECK: set sp, [[REGISTER]]
 ; CHECK: extsp 1
diff --git a/test/CodeGen/XCore/2011-08-01-VarargsBug.ll b/test/CodeGen/XCore/2011-08-01-VarargsBug.ll
deleted file mode 100644
index 2076057..0000000
--- a/test/CodeGen/XCore/2011-08-01-VarargsBug.ll
+++ /dev/null
@@ -1,17 +0,0 @@
-; RUN: llc < %s -march=xcore | FileCheck %s
-define void @_Z1fz(...) {
-entry:
-; CHECK: _Z1fz:
-; CHECK: extsp 3
-; CHECK: stw r[[REG:[0-3]{1,1}]]
-; CHECK: , sp{{\[}}[[REG]]{{\]}}
-; CHECK: stw r[[REG:[0-3]{1,1}]]
-; CHECK: , sp{{\[}}[[REG]]{{\]}}
-; CHECK: stw r[[REG:[0-3]{1,1}]]
-; CHECK: , sp{{\[}}[[REG]]{{\]}}
-; CHECK: stw r[[REG:[0-3]{1,1}]]
-; CHECK: , sp{{\[}}[[REG]]{{\]}}
-; CHECK: ldaw sp, sp[3]
-; CHECK: retsp 0
-  ret void
-}
diff --git a/test/CodeGen/XCore/addsub64.ll b/test/CodeGen/XCore/addsub64.ll
index d062480..89271ce 100644
--- a/test/CodeGen/XCore/addsub64.ll
+++ b/test/CodeGen/XCore/addsub64.ll
@@ -27,7 +27,7 @@ entry:
 	%3 = add i64 %2, %a
 	ret i64 %3
 }
-; CHECK: maccu:
+; CHECK-LABEL: maccu:
 ; CHECK: maccu r1, r0, r3, r2
 ; CHECK-NEXT: retsp 0
 
@@ -39,7 +39,7 @@ entry:
 	%3 = add i64 %2, %a
 	ret i64 %3
 }
-; CHECK: maccs:
+; CHECK-LABEL: maccs:
 ; CHECK: maccs r1, r0, r3, r2
 ; CHECK-NEXT: retsp 0
 
@@ -54,6 +54,6 @@ entry:
 	%6 = add i64 %5, %3
 	ret i64 %6
 }
-; CHECK: lmul:
+; CHECK-LABEL: lmul:
 ; CHECK: lmul r1, r0, r1, r0, r2, r3
 ; CHECK-NEXT: retsp 0
diff --git a/test/CodeGen/XCore/aliases.ll b/test/CodeGen/XCore/aliases.ll
index d83b246..d4da63c 100644
--- a/test/CodeGen/XCore/aliases.ll
+++ b/test/CodeGen/XCore/aliases.ll
@@ -7,7 +7,7 @@ declare void @a_val() nounwind
 @b = alias i32* @b_val
 @c = alias i32* @c_val
 
-; CHECK: a_addr:
+; CHECK-LABEL: a_addr:
 ; CHECK: ldap r11, a
 ; CHECK: retsp
 define void ()* @a_addr() nounwind {
@@ -15,7 +15,7 @@ entry:
   ret void ()* @a
 }
 
-; CHECK: b_addr:
+; CHECK-LABEL: b_addr:
 ; CHECK: ldaw r11, cp[b]
 ; CHECK: retsp
 define i32 *@b_addr() nounwind {
@@ -23,7 +23,7 @@ entry:
   ret i32* @b
 }
 
-; CHECK: c_addr:
+; CHECK-LABEL: c_addr:
 ; CHECK: ldaw r0, dp[c]
 ; CHECK: retsp
 define i32 *@c_addr() nounwind {
diff --git a/test/CodeGen/XCore/ashr.ll b/test/CodeGen/XCore/ashr.ll
index 03b6b1f..2752f52 100644
--- a/test/CodeGen/XCore/ashr.ll
+++ b/test/CodeGen/XCore/ashr.ll
@@ -3,21 +3,21 @@ define i32 @ashr(i32 %a, i32 %b) {
 	%1 = ashr i32 %a, %b
 	ret i32 %1
 }
-; CHECK: ashr:
+; CHECK-LABEL: ashr:
 ; CHECK-NEXT: ashr r0, r0, r1
 
 define i32 @ashri1(i32 %a) {
 	%1 = ashr i32 %a, 24
 	ret i32 %1
 }
-; CHECK: ashri1:
+; CHECK-LABEL: ashri1:
 ; CHECK-NEXT: ashr r0, r0, 24
 
 define i32 @ashri2(i32 %a) {
 	%1 = ashr i32 %a, 31
 	ret i32 %1
 }
-; CHECK: ashri2:
+; CHECK-LABEL: ashri2:
 ; CHECK-NEXT: ashr r0, r0, 32
 
 define i32 @f1(i32 %a) {
@@ -28,7 +28,7 @@ less:
 not_less:
 	ret i32 17
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK-NEXT: ashr r0, r0, 32
 ; CHECK-NEXT: bt r0
 
@@ -40,7 +40,7 @@ greater:
 not_greater:
 	ret i32 17
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK-NEXT: ashr r0, r0, 32
 ; CHECK-NEXT: bt r0
 
@@ -49,7 +49,7 @@ define i32 @f3(i32 %a) {
 	%2 = select i1 %1, i32 10, i32 17
 	ret i32 %2
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK-NEXT: ashr r0, r0, 32
 ; CHECK-NEXT: bt r0
 ; CHECK-NEXT: ldc r0, 17
@@ -60,7 +60,7 @@ define i32 @f4(i32 %a) {
 	%2 = select i1 %1, i32 10, i32 17
 	ret i32 %2
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK-NEXT: ashr r0, r0, 32
 ; CHECK-NEXT: bt r0
 ; CHECK-NEXT: ldc r0, 10
@@ -71,6 +71,6 @@ define i32 @f5(i32 %a) {
 	%2 = zext i1 %1 to i32
 	ret i32 %2
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK-NEXT: ashr r0, r0, 32
 ; CHECK-NEXT: eq r0, r0, 0
diff --git a/test/CodeGen/XCore/bigstructret.ll b/test/CodeGen/XCore/bigstructret.ll
index 56af930..877c571 100644
--- a/test/CodeGen/XCore/bigstructret.ll
+++ b/test/CodeGen/XCore/bigstructret.ll
@@ -12,7 +12,7 @@ entry:
   %3 = insertvalue %0 %2, i32 24601, 3
   ret %0 %3
 }
-; CHECK: ReturnBigStruct:
+; CHECK-LABEL: ReturnBigStruct:
 ; CHECK: ldc r0, 12
 ; CHECK: ldc r1, 24
 ; CHECK: ldc r2, 48
@@ -29,7 +29,7 @@ entry:
   %4 = insertvalue %1 %3, i32 4321, 4
   ret %1 %4
 }
-; CHECK: ReturnBigStruct2:
+; CHECK-LABEL: ReturnBigStruct2:
 ; CHECK: ldc r1, 4321
 ; CHECK: stw r1, r0[4]
 ; CHECK: ldc r1, 24601
diff --git a/test/CodeGen/XCore/byVal.ll b/test/CodeGen/XCore/byVal.ll
new file mode 100644
index 0000000..a5d25d2
--- /dev/null
+++ b/test/CodeGen/XCore/byVal.ll
@@ -0,0 +1,58 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+
+; CHECK-LABEL: f0Test
+; CHECK: entsp 1
+; CHECK: bl f0
+; CHECK: retsp 1
+%struct.st0 = type { [0 x i32] }
+declare void @f0(%struct.st0*) nounwind
+define void @f0Test(%struct.st0* byval %s0) nounwind {
+entry:
+  call void @f0(%struct.st0* %s0) nounwind
+  ret void
+}
+
+; CHECK-LABEL: f1Test
+; CHECK: entsp 13
+; CHECK: stw r4, sp[12]
+; CHECK: stw r5, sp[11]
+; CHECK: mov r4, r0
+; CHECK: ldaw r5, sp[1]
+; CHECK: ldc r2, 40
+; CHECK: mov r0, r5
+; CHECK: bl memcpy
+; CHECK: mov r0, r5
+; CHECK: bl f1
+; CHECK: mov r0, r4
+; CHECK: ldw r5, sp[11]
+; CHECK: ldw r4, sp[12]
+; CHECK: retsp 13
+%struct.st1 = type { [10 x i32] }
+declare void @f1(%struct.st1*) nounwind
+define i32 @f1Test(i32 %i, %struct.st1* byval %s1) nounwind {
+entry:
+  call void @f1(%struct.st1* %s1) nounwind
+  ret i32 %i
+}
+
+; CHECK-LABEL: f2Test
+; CHECK: extsp 4
+; CHECK: stw lr, sp[1]
+; CHECK: stw r2, sp[3]
+; CHECK: stw r3, sp[4]
+; CHECK: ldw r0, r0[0]
+; CHECK: stw r0, sp[2]
+; CHECK: ldaw r2, sp[2]
+; CHECK: mov r0, r1
+; CHECK: mov r1, r2
+; CHECK: bl f2
+; CHECK: ldw lr, sp[1]
+; CHECK: ldaw sp, sp[4]
+; CHECK: retsp 0
+%struct.st2 = type { i32 }
+declare void @f2(i32, %struct.st2*) nounwind
+define void @f2Test(%struct.st2* byval %s2, i32 %i, ...) nounwind {
+entry:
+  call void @f2(i32 %i, %struct.st2* %s2)
+  ret void
+}
diff --git a/test/CodeGen/XCore/constants.ll b/test/CodeGen/XCore/constants.ll
index cad1a21..c289bf9 100644
--- a/test/CodeGen/XCore/constants.ll
+++ b/test/CodeGen/XCore/constants.ll
@@ -3,9 +3,17 @@
 ; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4
 ; CHECK: .LCPI0_0:
 ; CHECK: .long 12345678
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: ldw r0, cp[.LCPI0_0]
 define i32 @f() {
 entry:
 	ret i32 12345678
 }
+
+define i32 @g() {
+entry:
+; CHECK-LABEL: g:
+; CHECK: mkmsk r0, 1
+; CHECK: retsp 0
+  ret i32 1;
+}
diff --git a/test/CodeGen/XCore/epilogue_prologue.ll b/test/CodeGen/XCore/epilogue_prologue.ll
index 49a4cc7..185565f 100644
--- a/test/CodeGen/XCore/epilogue_prologue.ll
+++ b/test/CodeGen/XCore/epilogue_prologue.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=xcore | FileCheck %s
 
-; CHECK: f1
+; CHECK-LABEL: f1
 ; CHECK: stw lr, sp[0]
 ; CHECK: ldw lr, sp[0]
 ; CHECK-NEXT: retsp 0
@@ -9,3 +9,18 @@ entry:
   tail call void asm sideeffect "", "~{lr}"() nounwind
   ret void
 }
+
+; CHECK-LABEL: f3
+; CHECK: entsp 2
+; CHECK: stw [[REG:r[4-9]+]], sp[1]
+; CHECK: mov [[REG]], r0
+; CHECK: bl f2
+; CHECK: mov r0, [[REG]]
+; CHECK: ldw [[REG]], sp[1]
+; CHECK: retsp 2
+declare void @f2()
+define i32 @f3(i32 %i) nounwind {
+entry:
+  call void @f2()
+  ret i32 %i
+}
diff --git a/test/CodeGen/XCore/events.ll b/test/CodeGen/XCore/events.ll
index 30a6ec3..672669b 100644
--- a/test/CodeGen/XCore/events.ll
+++ b/test/CodeGen/XCore/events.ll
@@ -6,7 +6,7 @@ declare i8* @llvm.xcore.checkevent(i8*)
 declare void @llvm.xcore.clre()
 
 define i32 @f(i8 addrspace(1)* %r) nounwind {
-; CHECK: f:
+; CHECK-LABEL: f:
 entry:
 ; CHECK: clre
   call void @llvm.xcore.clre()
@@ -25,7 +25,7 @@ ret:
 }
 
 define i32 @g(i8 addrspace(1)* %r) nounwind {
-; CHECK: g:
+; CHECK-LABEL: g:
 entry:
 ; CHECK: clre
   call void @llvm.xcore.clre()
diff --git a/test/CodeGen/XCore/float-intrinsics.ll b/test/CodeGen/XCore/float-intrinsics.ll
index 69a40f3..5882036 100644
--- a/test/CodeGen/XCore/float-intrinsics.ll
+++ b/test/CodeGen/XCore/float-intrinsics.ll
@@ -11,7 +11,7 @@ declare double @llvm.sin.f64(double)
 declare double @llvm.sqrt.f64(double)
 
 define double @cos(double %F) {
-; CHECK: cos:
+; CHECK-LABEL: cos:
 ; CHECK: bl cos
         %result = call double @llvm.cos.f64(double %F)
 	ret double %result
@@ -19,7 +19,7 @@ define double @cos(double %F) {
 
 declare float @llvm.cos.f32(float)
 
-; CHECK: cosf:
+; CHECK-LABEL: cosf:
 ; CHECK: bl cosf
 define float @cosf(float %F) {
         %result = call float @llvm.cos.f32(float %F)
@@ -27,7 +27,7 @@ define float @cosf(float %F) {
 }
 
 define double @exp(double %F) {
-; CHECK: exp:
+; CHECK-LABEL: exp:
 ; CHECK: bl exp
         %result = call double @llvm.exp.f64(double %F)
 	ret double %result
@@ -36,14 +36,14 @@ define double @exp(double %F) {
 declare float @llvm.exp.f32(float)
 
 define float @expf(float %F) {
-; CHECK: expf:
+; CHECK-LABEL: expf:
 ; CHECK: bl expf
         %result = call float @llvm.exp.f32(float %F)
 	ret float %result
 }
 
 define double @exp2(double %F) {
-; CHECK: exp2:
+; CHECK-LABEL: exp2:
 ; CHECK: bl exp2
         %result = call double @llvm.exp2.f64(double %F)
 	ret double %result
@@ -52,14 +52,14 @@ define double @exp2(double %F) {
 declare float @llvm.exp2.f32(float)
 
 define float @exp2f(float %F) {
-; CHECK: exp2f:
+; CHECK-LABEL: exp2f:
 ; CHECK: bl exp2f
         %result = call float @llvm.exp2.f32(float %F)
 	ret float %result
 }
 
 define double @log(double %F) {
-; CHECK: log:
+; CHECK-LABEL: log:
 ; CHECK: bl log
         %result = call double @llvm.log.f64(double %F)
 	ret double %result
@@ -68,14 +68,14 @@ define double @log(double %F) {
 declare float @llvm.log.f32(float)
 
 define float @logf(float %F) {
-; CHECK: logf:
+; CHECK-LABEL: logf:
 ; CHECK: bl logf
         %result = call float @llvm.log.f32(float %F)
 	ret float %result
 }
 
 define double @log10(double %F) {
-; CHECK: log10:
+; CHECK-LABEL: log10:
 ; CHECK: bl log10
         %result = call double @llvm.log10.f64(double %F)
 	ret double %result
@@ -84,14 +84,14 @@ define double @log10(double %F) {
 declare float @llvm.log10.f32(float)
 
 define float @log10f(float %F) {
-; CHECK: log10f:
+; CHECK-LABEL: log10f:
 ; CHECK: bl log10f
         %result = call float @llvm.log10.f32(float %F)
 	ret float %result
 }
 
 define double @log2(double %F) {
-; CHECK: log2:
+; CHECK-LABEL: log2:
 ; CHECK: bl log2
         %result = call double @llvm.log2.f64(double %F)
 	ret double %result
@@ -100,14 +100,14 @@ define double @log2(double %F) {
 declare float @llvm.log2.f32(float)
 
 define float @log2f(float %F) {
-; CHECK: log2f:
+; CHECK-LABEL: log2f:
 ; CHECK: bl log2f
         %result = call float @llvm.log2.f32(float %F)
 	ret float %result
 }
 
 define double @pow(double %F, double %power) {
-; CHECK: pow:
+; CHECK-LABEL: pow:
 ; CHECK: bl pow
         %result = call double @llvm.pow.f64(double %F, double %power)
 	ret double %result
@@ -116,14 +116,14 @@ define double @pow(double %F, double %power) {
 declare float @llvm.pow.f32(float, float)
 
 define float @powf(float %F, float %power) {
-; CHECK: powf:
+; CHECK-LABEL: powf:
 ; CHECK: bl powf
         %result = call float @llvm.pow.f32(float %F, float %power)
 	ret float %result
 }
 
 define double @powi(double %F, i32 %power) {
-; CHECK: powi:
+; CHECK-LABEL: powi:
 ; CHECK: bl __powidf2
         %result = call double @llvm.powi.f64(double %F, i32 %power)
 	ret double %result
@@ -132,14 +132,14 @@ define double @powi(double %F, i32 %power) {
 declare float @llvm.powi.f32(float, i32)
 
 define float @powif(float %F, i32 %power) {
-; CHECK: powif:
+; CHECK-LABEL: powif:
 ; CHECK: bl __powisf2
         %result = call float @llvm.powi.f32(float %F, i32 %power)
 	ret float %result
 }
 
 define double @sin(double %F) {
-; CHECK: sin:
+; CHECK-LABEL: sin:
 ; CHECK: bl sin
         %result = call double @llvm.sin.f64(double %F)
 	ret double %result
@@ -148,14 +148,14 @@ define double @sin(double %F) {
 declare float @llvm.sin.f32(float)
 
 define float @sinf(float %F) {
-; CHECK: sinf:
+; CHECK-LABEL: sinf:
 ; CHECK: bl sinf
         %result = call float @llvm.sin.f32(float %F)
 	ret float %result
 }
 
 define double @sqrt(double %F) {
-; CHECK: sqrt:
+; CHECK-LABEL: sqrt:
 ; CHECK: bl sqrt
         %result = call double @llvm.sqrt.f64(double %F)
 	ret double %result
@@ -164,7 +164,7 @@ define double @sqrt(double %F) {
 declare float @llvm.sqrt.f32(float)
 
 define float @sqrtf(float %F) {
-; CHECK: sqrtf:
+; CHECK-LABEL: sqrtf:
 ; CHECK: bl sqrtf
         %result = call float @llvm.sqrt.f32(float %F)
 	ret float %result
diff --git a/test/CodeGen/XCore/fneg.ll b/test/CodeGen/XCore/fneg.ll
index d442a19..67ab619 100644
--- a/test/CodeGen/XCore/fneg.ll
+++ b/test/CodeGen/XCore/fneg.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=xcore | FileCheck %s
 define i1 @test(double %F) nounwind {
 entry:
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: xor
 	%0 = fsub double -0.000000e+00, %F
 	%1 = fcmp olt double 0.000000e+00, %0
diff --git a/test/CodeGen/XCore/getid.ll b/test/CodeGen/XCore/getid.ll
index ec46071..da80e10 100644
--- a/test/CodeGen/XCore/getid.ll
+++ b/test/CodeGen/XCore/getid.ll
@@ -2,7 +2,7 @@
 declare i32 @llvm.xcore.getid()
 
 define i32 @test() {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: get r11, id
 ; CHECK-NEXT: mov r0, r11
 	%result = call i32 @llvm.xcore.getid()
diff --git a/test/CodeGen/XCore/globals.ll b/test/CodeGen/XCore/globals.ll
index 7487561..b140587 100644
--- a/test/CodeGen/XCore/globals.ll
+++ b/test/CodeGen/XCore/globals.ll
@@ -2,21 +2,21 @@
 
 define i32 *@addr_G1() {
 entry:
-; CHECK: addr_G1:
+; CHECK-LABEL: addr_G1:
 ; CHECK: ldaw r0, dp[G1]
 	ret i32* @G1
 }
 
 define i32 *@addr_G2() {
 entry:
-; CHECK: addr_G2:
+; CHECK-LABEL: addr_G2:
 ; CHECK: ldaw r0, dp[G2]
 	ret i32* @G2
 }
 
 define i32 *@addr_G3() {
 entry:
-; CHECK: addr_G3:
+; CHECK-LABEL: addr_G3:
 ; CHECK: ldaw r11, cp[G3]
 ; CHECK: mov r0, r11
 	ret i32* @G3
@@ -24,14 +24,14 @@ entry:
 
 define i32 **@addr_G4() {
 entry:
-; CHECK: addr_G4:
+; CHECK-LABEL: addr_G4:
 ; CHECK: ldaw r0, dp[G4]
 	ret i32** @G4
 }
 
 define i32 **@addr_G5() {
 entry:
-; CHECK: addr_G5:
+; CHECK-LABEL: addr_G5:
 ; CHECK: ldaw r11, cp[G5]
 ; CHECK: mov r0, r11
 	ret i32** @G5
@@ -39,14 +39,14 @@ entry:
 
 define i32 **@addr_G6() {
 entry:
-; CHECK: addr_G6:
+; CHECK-LABEL: addr_G6:
 ; CHECK: ldaw r0, dp[G6]
 	ret i32** @G6
 }
 
 define i32 **@addr_G7() {
 entry:
-; CHECK: addr_G7:
+; CHECK-LABEL: addr_G7:
 ; CHECK: ldaw r11, cp[G7]
 ; CHECK: mov r0, r11
 	ret i32** @G7
@@ -54,7 +54,7 @@ entry:
 
 define i32 *@addr_G8() {
 entry:
-; CHECK: addr_G8:
+; CHECK-LABEL: addr_G8:
 ; CHECK: ldaw r0, dp[G8]
 	ret i32* @G8
 }
@@ -90,3 +90,7 @@ entry:
 @G8 = internal global i32 9312
 ; CHECK: .section .dp.data,"awd",@progbits
 ; CHECK: G8:
+
+@array = global [10 x i16] zeroinitializer, align 2
+; CHECK: .globl  array.globound
+; CHECK: .set  array.globound,10
diff --git a/test/CodeGen/XCore/indirectbr.ll b/test/CodeGen/XCore/indirectbr.ll
index 9269002..d7758ea 100644
--- a/test/CodeGen/XCore/indirectbr.ll
+++ b/test/CodeGen/XCore/indirectbr.ll
@@ -4,7 +4,7 @@
 @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
 
 define internal i32 @foo(i32 %i) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
 entry:
   %0 = load i8** @nextaddr, align 4               ; <i8*> [#uses=2]
   %1 = icmp eq i8* %0, null                       ; <i1> [#uses=1]
diff --git a/test/CodeGen/XCore/inline-asm.ll b/test/CodeGen/XCore/inline-asm.ll
new file mode 100644
index 0000000..af3edd1
--- /dev/null
+++ b/test/CodeGen/XCore/inline-asm.ll
@@ -0,0 +1,32 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+; CHECK-LABEL: f1:
+; CHECK: foo r0
+define i32 @f1() nounwind {
+entry:
+  %asmtmp = tail call i32 asm sideeffect "foo $0", "=r"() nounwind
+  ret i32 %asmtmp
+}
+
+; CHECK-LABEL: f2:
+; CHECK: foo 5
+define void @f2() nounwind {
+entry:
+  tail call void asm sideeffect "foo $0", "i"(i32 5) nounwind
+  ret void
+}
+
+; CHECK-LABEL: f3:
+; CHECK: foo 42
+define void @f3() nounwind {
+entry:
+  tail call void asm sideeffect "foo ${0:c}", "i"(i32 42) nounwind
+  ret void
+}
+
+; CHECK-LABEL: f4:
+; CHECK: foo -99
+define void @f4() nounwind {
+entry:
+  tail call void asm sideeffect "foo ${0:n}", "i"(i32 99) nounwind
+  ret void
+}
diff --git a/test/CodeGen/XCore/ladd_lsub_combine.ll b/test/CodeGen/XCore/ladd_lsub_combine.ll
index cd89966..b75e30d 100644
--- a/test/CodeGen/XCore/ladd_lsub_combine.ll
+++ b/test/CodeGen/XCore/ladd_lsub_combine.ll
@@ -8,7 +8,7 @@ entry:
 	%2 = add i64 %1, %0		; <i64> [#uses=1]
 	ret i64 %2
 }
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldc r2, 0
 ; CHECK-NEXT: ladd r1, r0, r1, r0, r2
 ; CHECK-NEXT: retsp 0
@@ -21,7 +21,7 @@ entry:
 	%2 = sub i64 %1, %0		; <i64> [#uses=1]
 	ret i64 %2
 }
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldc r2, 0
 ; CHECK-NEXT: lsub r1, r0, r1, r0, r2
 ; CHECK-NEXT: neg r1, r1
@@ -34,7 +34,7 @@ entry:
 	%1 = add i64 %x, %0		; <i64> [#uses=1]
 	ret i64 %1
 }
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ldc r3, 0
 ; CHECK-NEXT: ladd r2, r0, r0, r2, r3
 ; CHECK-NEXT: add r1, r1, r2
@@ -47,7 +47,7 @@ entry:
 	%1 = add i64 %0, %y		; <i64> [#uses=1]
 	ret i64 %1
 }
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldc r3, 0
 ; CHECK-NEXT: ladd r1, r0, r0, r1, r3
 ; CHECK-NEXT: add r1, r2, r1
@@ -60,7 +60,7 @@ entry:
 	%1 = sub i64 %x, %0		; <i64> [#uses=1]
 	ret i64 %1
 }
-; CHECK: f5:
+; CHECK-LABEL: f5:
 ; CHECK: ldc r3, 0
 ; CHECK-NEXT: lsub r2, r0, r0, r2, r3
 ; CHECK-NEXT: sub r1, r1, r2
diff --git a/test/CodeGen/XCore/licm-ldwcp.ll b/test/CodeGen/XCore/licm-ldwcp.ll
index 794c6bb..f98c0eb 100644
--- a/test/CodeGen/XCore/licm-ldwcp.ll
+++ b/test/CodeGen/XCore/licm-ldwcp.ll
@@ -2,7 +2,7 @@
 
 ; MachineLICM should hoist the LDWCP out of the loop.
 
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK-NEXT: ldw [[REG:r[0-9]+]], cp[.LCPI0_0]
 ; CHECK-NEXT: .LBB0_1:
 ; CHECK-NEXT: stw [[REG]], r0[0]
diff --git a/test/CodeGen/XCore/load.ll b/test/CodeGen/XCore/load.ll
index faff03b..0622f1c 100644
--- a/test/CodeGen/XCore/load.ll
+++ b/test/CodeGen/XCore/load.ll
@@ -2,7 +2,7 @@
 
 define i32 @load32(i32* %p, i32 %offset) nounwind {
 entry:
-; CHECK: load32:
+; CHECK-LABEL: load32:
 ; CHECK: ldw r0, r0[r1]
 	%0 = getelementptr i32* %p, i32 %offset
 	%1 = load i32* %0, align 4
@@ -11,7 +11,7 @@ entry:
 
 define i32 @load32_imm(i32* %p) nounwind {
 entry:
-; CHECK: load32_imm:
+; CHECK-LABEL: load32_imm:
 ; CHECK: ldw r0, r0[11]
 	%0 = getelementptr i32* %p, i32 11
 	%1 = load i32* %0, align 4
@@ -20,7 +20,7 @@ entry:
 
 define i32 @load16(i16* %p, i32 %offset) nounwind {
 entry:
-; CHECK: load16:
+; CHECK-LABEL: load16:
 ; CHECK: ld16s r0, r0[r1]
 ; CHECK-NOT: sext
 	%0 = getelementptr i16* %p, i32 %offset
@@ -31,7 +31,7 @@ entry:
 
 define i32 @load8(i8* %p, i32 %offset) nounwind {
 entry:
-; CHECK: load8:
+; CHECK-LABEL: load8:
 ; CHECK: ld8u r0, r0[r1]
 ; CHECK-NOT: zext
 	%0 = getelementptr i8* %p, i32 %offset
@@ -39,3 +39,12 @@ entry:
 	%2 = zext i8 %1 to i32
 	ret i32 %2
 }
+
+@GConst = external constant i32
+define i32 @load_cp() nounwind {
+entry:
+; CHECK-LABEL: load_cp:
+; CHECK: ldw r0, cp[GConst]
+  %0 = load i32* @GConst
+  ret i32 %0
+}
diff --git a/test/CodeGen/XCore/misc-intrinsics.ll b/test/CodeGen/XCore/misc-intrinsics.ll
index 6d39d77..30d7493 100644
--- a/test/CodeGen/XCore/misc-intrinsics.ll
+++ b/test/CodeGen/XCore/misc-intrinsics.ll
@@ -10,56 +10,56 @@ declare i32 @llvm.xcore.geted()
 declare i32 @llvm.xcore.getet()
 
 define i32 @bitrev(i32 %val) {
-; CHECK: bitrev:
+; CHECK-LABEL: bitrev:
 ; CHECK: bitrev r0, r0
 	%result = call i32 @llvm.xcore.bitrev(i32 %val)
 	ret i32 %result
 }
 
 define i32 @crc32(i32 %crc, i32 %data, i32 %poly) {
-; CHECK: crc32:
+; CHECK-LABEL: crc32:
 ; CHECK: crc32 r0, r1, r2
 	%result = call i32 @llvm.xcore.crc32(i32 %crc, i32 %data, i32 %poly)
 	ret i32 %result
 }
 
 define %0 @crc8(i32 %crc, i32 %data, i32 %poly) {
-; CHECK: crc8:
+; CHECK-LABEL: crc8:
 ; CHECK: crc8 r0, r1, r1, r2
 	%result = call %0 @llvm.xcore.crc8(i32 %crc, i32 %data, i32 %poly)
 	ret %0 %result
 }
 
 define i32 @zext(i32 %a, i32 %b) {
-; CHECK: zext:
+; CHECK-LABEL: zext:
 ; CHECK: zext r0, r1
 	%result = call i32 @llvm.xcore.zext(i32 %a, i32 %b)
 	ret i32 %result
 }
 
 define i32 @zexti(i32 %a) {
-; CHECK: zexti:
+; CHECK-LABEL: zexti:
 ; CHECK: zext r0, 4
 	%result = call i32 @llvm.xcore.zext(i32 %a, i32 4)
 	ret i32 %result
 }
 
 define i32 @sext(i32 %a, i32 %b) {
-; CHECK: sext:
+; CHECK-LABEL: sext:
 ; CHECK: sext r0, r1
 	%result = call i32 @llvm.xcore.sext(i32 %a, i32 %b)
 	ret i32 %result
 }
 
 define i32 @sexti(i32 %a) {
-; CHECK: sexti:
+; CHECK-LABEL: sexti:
 ; CHECK: sext r0, 4
 	%result = call i32 @llvm.xcore.sext(i32 %a, i32 4)
 	ret i32 %result
 }
 
 define i32 @geted() {
-; CHECK: geted:
+; CHECK-LABEL: geted:
 ; CHECK: get r11, ed
 ; CHECK-NEXT: mov r0, r11
 	%result = call i32 @llvm.xcore.geted()
@@ -67,7 +67,7 @@ define i32 @geted() {
 }
 
 define i32 @getet() {
-; CHECK: getet:
+; CHECK-LABEL: getet:
 ; CHECK: get r11, et
 ; CHECK-NEXT: mov r0, r11
 	%result = call i32 @llvm.xcore.getet()
diff --git a/test/CodeGen/XCore/mkmsk.ll b/test/CodeGen/XCore/mkmsk.ll
index 377612b..bcec32d 100644
--- a/test/CodeGen/XCore/mkmsk.ll
+++ b/test/CodeGen/XCore/mkmsk.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=xcore | FileCheck %s
 
 define i32 @f(i32) nounwind {
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: mkmsk r0, r0
 ; CHECK-NEXT: retsp 0
 entry:
diff --git a/test/CodeGen/XCore/mul64.ll b/test/CodeGen/XCore/mul64.ll
index 3d373b1..cfc9855 100644
--- a/test/CodeGen/XCore/mul64.ll
+++ b/test/CodeGen/XCore/mul64.ll
@@ -7,7 +7,7 @@ entry:
 	%2 = mul i64 %1, %0
 	ret i64 %2
 }
-; CHECK: umul_lohi:
+; CHECK-LABEL: umul_lohi:
 ; CHECK: ldc [[REG:r[0-9]+]], 0
 ; CHECK-NEXT: lmul {{.*}}, [[REG]], [[REG]]
 ; CHECK-NEXT: retsp 0
@@ -19,7 +19,7 @@ entry:
 	%2 = mul i64 %1, %0
 	ret i64 %2
 }
-; CHECK: smul_lohi:
+; CHECK-LABEL: smul_lohi:
 ; CHECK: ldc
 ; CHECK-NEXT: mov
 ; CHECK-NEXT: maccs
@@ -30,7 +30,7 @@ entry:
 	%0 = mul i64 %a, %b
 	ret i64 %0
 }
-; CHECK: mul64:
+; CHECK-LABEL: mul64:
 ; CHECK: ldc
 ; CHECK-NEXT: lmul
 ; CHECK-NEXT: mul
@@ -42,7 +42,7 @@ entry:
 	%1 = mul i64 %a, %0
 	ret i64 %1
 }
-; CHECK: mul64_2:
+; CHECK-LABEL: mul64_2:
 ; CHECK: ldc
 ; CHECK-NEXT: lmul
 ; CHECK-NEXT: mul
diff --git a/test/CodeGen/XCore/offset_folding.ll b/test/CodeGen/XCore/offset_folding.ll
index 30edfe6..8085a0f 100644
--- a/test/CodeGen/XCore/offset_folding.ll
+++ b/test/CodeGen/XCore/offset_folding.ll
@@ -5,7 +5,7 @@
 
 define i32 *@f1() nounwind {
 entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
 ; CHECK: ldaw r11, cp[a+4]
 ; CHECK: mov r0, r11
 	%0 = getelementptr [0 x i32]* @a, i32 0, i32 1
@@ -14,7 +14,7 @@ entry:
 
 define i32 *@f2() nounwind {
 entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
 ; CHECK: ldaw r0, dp[b+4]
 	%0 = getelementptr [0 x i32]* @b, i32 0, i32 1
 	ret i32* %0
@@ -25,7 +25,7 @@ entry:
 
 define i32 *@f3() nounwind {
 entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
 ; CHECK: ldaw r11, cp[a]
 ; CHECK: sub r0, r11, 4
 	%0 = getelementptr [0 x i32]* @a, i32 0, i32 -1
@@ -34,7 +34,7 @@ entry:
 
 define i32 *@f4() nounwind {
 entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
 ; CHECK: ldaw [[REG:r[0-9]+]], dp[b]
 ; CHECK: sub r0, [[REG]], 4
 	%0 = getelementptr [0 x i32]* @b, i32 0, i32 -1
diff --git a/test/CodeGen/XCore/private.ll b/test/CodeGen/XCore/private.ll
index 80b7db4..474448a 100644
--- a/test/CodeGen/XCore/private.ll
+++ b/test/CodeGen/XCore/private.ll
@@ -10,7 +10,7 @@ define private void @foo() {
 @baz = private global i32 4
 
 define i32 @bar() {
-; CHECK: bar:
+; CHECK-LABEL: bar:
 ; CHECK: bl .Lfoo
 ; CHECK: ldw r0, dp[.Lbaz]
         call void @foo()
diff --git a/test/CodeGen/XCore/ps-intrinsics.ll b/test/CodeGen/XCore/ps-intrinsics.ll
index 92b26c7..02609ed 100644
--- a/test/CodeGen/XCore/ps-intrinsics.ll
+++ b/test/CodeGen/XCore/ps-intrinsics.ll
@@ -3,7 +3,7 @@ declare i32 @llvm.xcore.getps(i32)
 declare void @llvm.xcore.setps(i32, i32)
 
 define i32 @getps(i32 %reg) nounwind {
-; CHECK: getps:
+; CHECK-LABEL: getps:
 ; CHECK: get r0, ps[r0]
 	%result = call i32 @llvm.xcore.getps(i32 %reg)
 	ret i32 %result
@@ -11,7 +11,7 @@ define i32 @getps(i32 %reg) nounwind {
 
 
 define void @setps(i32 %reg, i32 %value) nounwind {
-; CHECK: setps:
+; CHECK-LABEL: setps:
 ; CHECK: set ps[r0], r1
 	call void @llvm.xcore.setps(i32 %reg, i32 %value)
 	ret void
diff --git a/test/CodeGen/XCore/resources.ll b/test/CodeGen/XCore/resources.ll
index 8f00fed..5385010 100644
--- a/test/CodeGen/XCore/resources.ll
+++ b/test/CodeGen/XCore/resources.ll
@@ -29,147 +29,147 @@ declare i32 @llvm.xcore.peek.p1i8(i8 addrspace(1)* %r)
 declare i32 @llvm.xcore.endin.p1i8(i8 addrspace(1)* %r)
 
 define i8 addrspace(1)* @getr() {
-; CHECK: getr:
+; CHECK-LABEL: getr:
 ; CHECK: getr r0, 5
 	%result = call i8 addrspace(1)* @llvm.xcore.getr.p1i8(i32 5)
 	ret i8 addrspace(1)* %result
 }
 
 define void @freer(i8 addrspace(1)* %r) {
-; CHECK: freer:
+; CHECK-LABEL: freer:
 ; CHECK: freer res[r0]
 	call void @llvm.xcore.freer.p1i8(i8 addrspace(1)* %r)
 	ret void
 }
 
 define i32 @in(i8 addrspace(1)* %r) {
-; CHECK: in:
+; CHECK-LABEL: in:
 ; CHECK: in r0, res[r0]
 	%result = call i32 @llvm.xcore.in.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
 }
 
 define i32 @int(i8 addrspace(1)* %r) {
-; CHECK: int:
+; CHECK-LABEL: int:
 ; CHECK: int r0, res[r0]
 	%result = call i32 @llvm.xcore.int.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
 }
 
 define i32 @inct(i8 addrspace(1)* %r) {
-; CHECK: inct:
+; CHECK-LABEL: inct:
 ; CHECK: inct r0, res[r0]
 	%result = call i32 @llvm.xcore.inct.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
 }
 
 define void @out(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: out:
+; CHECK-LABEL: out:
 ; CHECK: out res[r0], r1
 	call void @llvm.xcore.out.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define void @outt(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: outt:
+; CHECK-LABEL: outt:
 ; CHECK: outt res[r0], r1
 	call void @llvm.xcore.outt.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define void @outct(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: outct:
+; CHECK-LABEL: outct:
 ; CHECK: outct res[r0], r1
 	call void @llvm.xcore.outct.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define void @outcti(i8 addrspace(1)* %r) {
-; CHECK: outcti:
+; CHECK-LABEL: outcti:
 ; CHECK: outct res[r0], 11
 	call void @llvm.xcore.outct.p1i8(i8 addrspace(1)* %r, i32 11)
 	ret void
 }
 
 define void @chkct(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: chkct:
+; CHECK-LABEL: chkct:
 ; CHECK: chkct res[r0], r1
 	call void @llvm.xcore.chkct.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define void @chkcti(i8 addrspace(1)* %r) {
-; CHECK: chkcti:
+; CHECK-LABEL: chkcti:
 ; CHECK: chkct res[r0], 11
 	call void @llvm.xcore.chkct.p1i8(i8 addrspace(1)* %r, i32 11)
 	ret void
 }
 
 define void @setd(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: setd:
+; CHECK-LABEL: setd:
 ; CHECK: setd res[r0], r1
 	call void @llvm.xcore.setd.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define void @setc(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: setc:
+; CHECK-LABEL: setc:
 ; CHECK: setc res[r0], r1
 	call void @llvm.xcore.setc.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define void @setci(i8 addrspace(1)* %r) {
-; CHECK: setci:
+; CHECK-LABEL: setci:
 ; CHECK: setc res[r0], 2
 	call void @llvm.xcore.setc.p1i8(i8 addrspace(1)* %r, i32 2)
 	ret void
 }
 
 define i32 @inshr(i32 %value, i8 addrspace(1)* %r) {
-; CHECK: inshr:
+; CHECK-LABEL: inshr:
 ; CHECK: inshr r0, res[r1]
 	%result = call i32 @llvm.xcore.inshr.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret i32 %result
 }
 
 define i32 @outshr(i32 %value, i8 addrspace(1)* %r) {
-; CHECK: outshr:
+; CHECK-LABEL: outshr:
 ; CHECK: outshr res[r1], r0
 	%result = call i32 @llvm.xcore.outshr.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret i32 %result
 }
 
 define void @setpt(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: setpt:
+; CHECK-LABEL: setpt:
 ; CHECK: setpt res[r0], r1
 	call void @llvm.xcore.setpt.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define i32 @getts(i8 addrspace(1)* %r) {
-; CHECK: getts:
+; CHECK-LABEL: getts:
 ; CHECK: getts r0, res[r0]
 	%result = call i32 @llvm.xcore.getts.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
 }
 
 define void @syncr(i8 addrspace(1)* %r) {
-; CHECK: syncr:
+; CHECK-LABEL: syncr:
 ; CHECK: syncr res[r0]
 	call void @llvm.xcore.syncr.p1i8(i8 addrspace(1)* %r)
 	ret void
 }
 
 define void @settw(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: settw:
+; CHECK-LABEL: settw:
 ; CHECK: settw res[r0], r1
 	call void @llvm.xcore.settw.p1i8(i8 addrspace(1)* %r, i32 %value)
 	ret void
 }
 
 define void @setv(i8 addrspace(1)* %r, i8* %p) {
-; CHECK: setv:
+; CHECK-LABEL: setv:
 ; CHECK: mov r11, r1
 ; CHECK-NEXT: setv res[r0], r11
 	call void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* %p)
@@ -177,7 +177,7 @@ define void @setv(i8 addrspace(1)* %r, i8* %p) {
 }
 
 define void @setev(i8 addrspace(1)* %r, i8* %p) {
-; CHECK: setev:
+; CHECK-LABEL: setev:
 ; CHECK: mov r11, r1
 ; CHECK-NEXT: setev res[r0], r11
 	call void @llvm.xcore.setev.p1i8(i8 addrspace(1)* %r, i8* %p)
@@ -185,7 +185,7 @@ define void @setev(i8 addrspace(1)* %r, i8* %p) {
 }
 
 define void @eeu(i8 addrspace(1)* %r) {
-; CHECK: eeu:
+; CHECK-LABEL: eeu:
 ; CHECK: eeu res[r0]
 	call void @llvm.xcore.eeu.p1i8(i8 addrspace(1)* %r)
 	ret void
@@ -213,28 +213,28 @@ define void @setpsc(i8 addrspace(1)* %r, i32 %value) {
 }
 
 define i32 @peek(i8 addrspace(1)* %r) {
-; CHECK: peek:
+; CHECK-LABEL: peek:
 ; CHECK: peek r0, res[r0]
 	%result = call i32 @llvm.xcore.peek.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
 }
 
 define i32 @endin(i8 addrspace(1)* %r) {
-; CHECK: endin:
+; CHECK-LABEL: endin:
 ; CHECK: endin r0, res[r0]
 	%result = call i32 @llvm.xcore.endin.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
 }
 
 define i32 @testct(i8 addrspace(1)* %r) {
-; CHECK: testct:
+; CHECK-LABEL: testct:
 ; CHECK: testct r0, res[r0]
 	%result = call i32 @llvm.xcore.testct.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
 }
 
 define i32 @testwct(i8 addrspace(1)* %r) {
-; CHECK: testwct:
+; CHECK-LABEL: testwct:
 ; CHECK: testwct r0, res[r0]
 	%result = call i32 @llvm.xcore.testwct.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
diff --git a/test/CodeGen/XCore/sext.ll b/test/CodeGen/XCore/sext.ll
index 9cd4ad6..b3e66ec 100644
--- a/test/CodeGen/XCore/sext.ll
+++ b/test/CodeGen/XCore/sext.ll
@@ -4,7 +4,7 @@ define i32 @sext1(i32 %a) {
 	%2 = sext i1 %1 to i32
 	ret i32 %2
 }
-; CHECK: sext1:
+; CHECK-LABEL: sext1:
 ; CHECK: sext r0, 1
 
 define i32 @sext2(i32 %a) {
@@ -12,7 +12,7 @@ define i32 @sext2(i32 %a) {
 	%2 = sext i2 %1 to i32
 	ret i32 %2
 }
-; CHECK: sext2:
+; CHECK-LABEL: sext2:
 ; CHECK: sext r0, 2
 
 define i32 @sext8(i32 %a) {
@@ -20,7 +20,7 @@ define i32 @sext8(i32 %a) {
 	%2 = sext i8 %1 to i32
 	ret i32 %2
 }
-; CHECK: sext8:
+; CHECK-LABEL: sext8:
 ; CHECK: sext r0, 8
 
 define i32 @sext16(i32 %a) {
@@ -28,5 +28,5 @@ define i32 @sext16(i32 %a) {
 	%2 = sext i16 %1 to i32
 	ret i32 %2
 }
-; CHECK: sext16:
+; CHECK-LABEL: sext16:
 ; CHECK: sext r0, 16
diff --git a/test/CodeGen/XCore/sr-intrinsics.ll b/test/CodeGen/XCore/sr-intrinsics.ll
index e12ed03..2c4175d 100644
--- a/test/CodeGen/XCore/sr-intrinsics.ll
+++ b/test/CodeGen/XCore/sr-intrinsics.ll
@@ -3,7 +3,7 @@ declare void @llvm.xcore.setsr(i32)
 declare void @llvm.xcore.clrsr(i32)
 
 define void @setsr() nounwind {
-; CHECK: setsr:
+; CHECK-LABEL: setsr:
 ; CHECK: setsr 128
 	call void @llvm.xcore.setsr(i32 128)
 	ret void
@@ -11,7 +11,7 @@ define void @setsr() nounwind {
 
 
 define void @clrsr() nounwind {
-; CHECK: clrsr:
+; CHECK-LABEL: clrsr:
 ; CHECK: clrsr 128
 	call void @llvm.xcore.clrsr(i32 128)
 	ret void
diff --git a/test/CodeGen/XCore/store.ll b/test/CodeGen/XCore/store.ll
index 836b125..87553d8 100644
--- a/test/CodeGen/XCore/store.ll
+++ b/test/CodeGen/XCore/store.ll
@@ -2,7 +2,7 @@
 
 define void @store32(i32* %p, i32 %offset, i32 %val) nounwind {
 entry:
-; CHECK: store32:
+; CHECK-LABEL: store32:
 ; CHECK: stw r2, r0[r1]
 	%0 = getelementptr i32* %p, i32 %offset
 	store i32 %val, i32* %0, align 4
@@ -11,7 +11,7 @@ entry:
 
 define void @store32_imm(i32* %p, i32 %val) nounwind {
 entry:
-; CHECK: store32_imm:
+; CHECK-LABEL: store32_imm:
 ; CHECK: stw r1, r0[11]
 	%0 = getelementptr i32* %p, i32 11
 	store i32 %val, i32* %0, align 4
@@ -20,7 +20,7 @@ entry:
 
 define void @store16(i16* %p, i32 %offset, i16 %val) nounwind {
 entry:
-; CHECK: store16:
+; CHECK-LABEL: store16:
 ; CHECK: st16 r2, r0[r1]
 	%0 = getelementptr i16* %p, i32 %offset
 	store i16 %val, i16* %0, align 2
@@ -29,7 +29,7 @@ entry:
 
 define void @store8(i8* %p, i32 %offset, i8 %val) nounwind {
 entry:
-; CHECK: store8:
+; CHECK-LABEL: store8:
 ; CHECK: st8 r2, r0[r1]
 	%0 = getelementptr i8* %p, i32 %offset
 	store i8 %val, i8* %0, align 1
diff --git a/test/CodeGen/XCore/threads.ll b/test/CodeGen/XCore/threads.ll
index a0558e3..5840e77 100644
--- a/test/CodeGen/XCore/threads.ll
+++ b/test/CodeGen/XCore/threads.ll
@@ -10,57 +10,57 @@ declare void @llvm.xcore.initlr.p1i8(i8 addrspace(1)* %r, i8* %value)
 declare void @llvm.xcore.initcp.p1i8(i8 addrspace(1)* %r, i8* %value)
 declare void @llvm.xcore.initdp.p1i8(i8 addrspace(1)* %r, i8* %value)
 
-define i8 addrspace(1)* @getst(i8 addrspace(1)* %r) {
-; CHECK: getst:
+define i8 addrspace(1)* @test_getst(i8 addrspace(1)* %r) {
+; CHECK-LABEL: test_getst:
 ; CHECK: getst r0, res[r0]
         %result = call i8 addrspace(1)* @llvm.xcore.getst.p1i8.p1i8(i8 addrspace(1)* %r)
         ret i8 addrspace(1)* %result
 }
 
-define void @ssync() {
-; CHECK: ssync:
+define void @test_ssync() {
+; CHECK-LABEL: test_ssync:
 ; CHECK: ssync
 	call void @llvm.xcore.ssync()
 	ret void
 }
 
-define void @mjoin(i8 addrspace(1)* %r) {
-; CHECK: mjoin:
+define void @test_mjoin(i8 addrspace(1)* %r) {
+; CHECK-LABEL: test_mjoin:
 ; CHECK: mjoin res[r0]
 	call void @llvm.xcore.mjoin.p1i8(i8 addrspace(1)* %r)
 	ret void
 }
 
-define void @initsp(i8 addrspace(1)* %t, i8* %src) {
-; CHECK: initsp:
+define void @test_initsp(i8 addrspace(1)* %t, i8* %src) {
+; CHECK-LABEL: test_initsp:
 ; CHECK: init t[r0]:sp, r1
         call void @llvm.xcore.initsp.p1i8(i8 addrspace(1)* %t, i8* %src)
         ret void
 }
 
-define void @initpc(i8 addrspace(1)* %t, i8* %src) {
-; CHECK: initpc:
+define void @test_initpc(i8 addrspace(1)* %t, i8* %src) {
+; CHECK-LABEL: test_initpc:
 ; CHECK: init t[r0]:pc, r1
         call void @llvm.xcore.initpc.p1i8(i8 addrspace(1)* %t, i8* %src)
         ret void
 }
 
-define void @initlr(i8 addrspace(1)* %t, i8* %src) {
-; CHECK: initlr:
+define void @test_initlr(i8 addrspace(1)* %t, i8* %src) {
+; CHECK-LABEL: test_initlr:
 ; CHECK: init t[r0]:lr, r1
         call void @llvm.xcore.initlr.p1i8(i8 addrspace(1)* %t, i8* %src)
         ret void
 }
 
-define void @initcp(i8 addrspace(1)* %t, i8* %src) {
-; CHECK: initcp:
+define void @test_initcp(i8 addrspace(1)* %t, i8* %src) {
+; CHECK-LABEL: test_initcp:
 ; CHECK: init t[r0]:cp, r1
         call void @llvm.xcore.initcp.p1i8(i8 addrspace(1)* %t, i8* %src)
         ret void
 }
 
-define void @initdp(i8 addrspace(1)* %t, i8* %src) {
-; CHECK: initdp:
+define void @test_initdp(i8 addrspace(1)* %t, i8* %src) {
+; CHECK-LABEL: test_initdp:
 ; CHECK: init t[r0]:dp, r1
         call void @llvm.xcore.initdp.p1i8(i8 addrspace(1)* %t, i8* %src)
         ret void
diff --git a/test/CodeGen/XCore/tls.ll b/test/CodeGen/XCore/tls.ll
index ed41afa..648d611 100644
--- a/test/CodeGen/XCore/tls.ll
+++ b/test/CodeGen/XCore/tls.ll
@@ -2,7 +2,7 @@
 
 define i32 *@addr_G() {
 entry:
-; CHECK: addr_G:
+; CHECK-LABEL: addr_G:
 ; CHECK: get r11, id
 	ret i32* @G
 }
diff --git a/test/CodeGen/XCore/trampoline.ll b/test/CodeGen/XCore/trampoline.ll
index 6b42134..7ca331a 100644
--- a/test/CodeGen/XCore/trampoline.ll
+++ b/test/CodeGen/XCore/trampoline.ll
@@ -4,7 +4,7 @@
 
 define void @f() nounwind {
 entry:
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: ldap r11, g.1101
 ; CHECK: stw r11, sp[7]
   %TRAMP.23 = alloca [20 x i8], align 2
diff --git a/test/CodeGen/XCore/trap.ll b/test/CodeGen/XCore/trap.ll
index eb71cb6..ef0dfd6 100644
--- a/test/CodeGen/XCore/trap.ll
+++ b/test/CodeGen/XCore/trap.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=xcore | FileCheck %s
 define i32 @test() noreturn nounwind  {
 entry:
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: ldc
 ; CHECK: ecallf
 	tail call void @llvm.trap( )
diff --git a/test/CodeGen/XCore/unaligned_load.ll b/test/CodeGen/XCore/unaligned_load.ll
index 772a847..b8b8827 100644
--- a/test/CodeGen/XCore/unaligned_load.ll
+++ b/test/CodeGen/XCore/unaligned_load.ll
@@ -10,7 +10,7 @@ entry:
 }
 
 ; Half word aligned load.
-; CHECK: align2:
+; CHECK-LABEL: align2:
 ; CHECK: ld16s
 ; CHECK: ld16s
 ; CHECK: or
@@ -23,7 +23,7 @@ entry:
 @a = global [5 x i8] zeroinitializer, align 4
 
 ; Constant offset from word aligned base.
-; CHECK: align3:
+; CHECK-LABEL: align3:
 ; CHECK: ldw {{r[0-9]+}}, dp
 ; CHECK: ldw {{r[0-9]+}}, dp
 ; CHECK: or
diff --git a/test/CodeGen/XCore/unaligned_store.ll b/test/CodeGen/XCore/unaligned_store.ll
index 94e1852..27b4280 100644
--- a/test/CodeGen/XCore/unaligned_store.ll
+++ b/test/CodeGen/XCore/unaligned_store.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=xcore | FileCheck %s
 
 ; Byte aligned store.
-; CHECK: align1:
+; CHECK-LABEL: align1:
 ; CHECK: bl __misaligned_store
 define void @align1(i32* %p, i32 %val) nounwind {
 entry:
diff --git a/test/CodeGen/XCore/unaligned_store_combine.ll b/test/CodeGen/XCore/unaligned_store_combine.ll
index c997b78..d1f4e6c 100644
--- a/test/CodeGen/XCore/unaligned_store_combine.ll
+++ b/test/CodeGen/XCore/unaligned_store_combine.ll
@@ -4,7 +4,7 @@
 ; of size 8
 define void @f(i64* %dst, i64* %src) nounwind {
 entry:
-; CHECK: f:
+; CHECK-LABEL: f:
 ; CHECK: ldc r2, 8
 ; CHECK: bl memmove
 	%0 = load i64* %src, align 1
diff --git a/test/CodeGen/XCore/varargs.ll b/test/CodeGen/XCore/varargs.ll
new file mode 100644
index 0000000..28c2933
--- /dev/null
+++ b/test/CodeGen/XCore/varargs.ll
@@ -0,0 +1,55 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+
+define void @_Z1fz(...) {
+entry:
+; CHECK-LABEL: _Z1fz:
+; CHECK: extsp 3
+; CHECK: stw r[[REG:[0-3]{1,1}]]
+; CHECK: , sp{{\[}}[[REG]]{{\]}}
+; CHECK: stw r[[REG:[0-3]{1,1}]]
+; CHECK: , sp{{\[}}[[REG]]{{\]}}
+; CHECK: stw r[[REG:[0-3]{1,1}]]
+; CHECK: , sp{{\[}}[[REG]]{{\]}}
+; CHECK: stw r[[REG:[0-3]{1,1}]]
+; CHECK: , sp{{\[}}[[REG]]{{\]}}
+; CHECK: ldaw sp, sp[3]
+; CHECK: retsp 0
+  ret void
+}
+
+
+declare void @llvm.va_start(i8*) nounwind
+declare void @llvm.va_end(i8*) nounwind
+declare void @f(i32) nounwind
+define void @test_vararg(...) nounwind {
+entry:
+; CHECK-LABEL: test_vararg
+; CHECK: extsp 6
+; CHECK: stw lr, sp[1]
+; CHECK: stw r0, sp[3]
+; CHECK: stw r1, sp[4]
+; CHECK: stw r2, sp[5]
+; CHECK: stw r3, sp[6]
+; CHECK: ldaw r0, sp[3]
+; CHECK: stw r0, sp[2]
+  %list = alloca i8*, align 4
+  %list1 = bitcast i8** %list to i8*
+  call void @llvm.va_start(i8* %list1)
+  br label %for.cond
+
+; CHECK-LABEL: .LBB1_1
+; CHECK: ldw r0, sp[2]
+; CHECK: add r1, r0, 4
+; CHECK: stw r1, sp[2]
+; CHECK: ldw r0, r0[0]
+; CHECK: bl f
+; CHECK: bu .LBB1_1
+for.cond:
+  %0 = va_arg i8** %list, i32
+  call void @f(i32 %0)
+  br label %for.cond
+
+  call void @llvm.va_end(i8* %list1)
+  ret void
+}
+
diff --git a/test/CodeGen/XCore/zext.ll b/test/CodeGen/XCore/zext.ll
new file mode 100644
index 0000000..32abfca
--- /dev/null
+++ b/test/CodeGen/XCore/zext.ll
@@ -0,0 +1,10 @@
+; RUN: llc -march=xcore < %s | FileCheck %s
+
+define i32 @f(i1 %a) {
+entry:
+; CHECK: f
+; CHECK: zext r0, 1
+; CHECK: retsp 0
+  %b= zext i1 %a to i32
+  ret i32 %b
+}
diff --git a/test/DebugInfo/2009-11-03-InsertExtractValue.ll b/test/DebugInfo/2009-11-03-InsertExtractValue.ll
index 5bfca21..9a3e622 100644
--- a/test/DebugInfo/2009-11-03-InsertExtractValue.ll
+++ b/test/DebugInfo/2009-11-03-InsertExtractValue.ll
@@ -1,16 +1,19 @@
 ; RUN: llvm-as < %s | llvm-dis | FileCheck %s
 
-!dbg = !{!0}
-!0 = metadata !{i32 786478, metadata !1, metadata !"bar", metadata !"bar", metadata !"_ZN3foo3barEv", metadata !1, i32 3, metadata !2, i1 false, i1 false, i32 0, i32 0, null, i32 258, i1 false, null, null, i32 0, metadata !1, i32 3} ; [ DW_TAG_subprogram ]
+!llvm.dbg.sp = !{!0}
+!llvm.dbg.cu = !{!5}
+
+!0 = metadata !{i32 786478, metadata !4, metadata !1, metadata !"bar", metadata !"bar", metadata !"_ZN3foo3barEv", i32 3, metadata !2, i1 false, i1 false, i32 0, i32 0, null, i32 258, i1 false, null, null, i32 0, metadata !1, i32 3} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 41, metadata !4} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 21, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 21, metadata !4, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !3 = metadata !{null}
 !4 = metadata !{metadata !"/foo", metadata !"bar.cpp"}
+!5 = metadata !{i32 458769, metadata !4, i32 12, metadata !"", i1 true, metadata !"", i32 0, metadata !3, metadata !3, null, null, null, metadata !""}; [DW_TAG_compile_unit ]
 
 define <{i32, i32}> @f1() {
-; CHECK: !dbgx !1
+; CHECK: !dbgx ![[NUMBER:[0-9]+]]
   %r = insertvalue <{ i32, i32 }> zeroinitializer, i32 4, 1, !dbgx !1
-; CHECK: !dbgx !1
+; CHECK: !dbgx ![[NUMBER]]
   %e = extractvalue <{ i32, i32 }> %r, 0, !dbgx !1
   ret <{ i32, i32 }> %r
 }
diff --git a/test/DebugInfo/2009-11-05-DeadGlobalVariable.ll b/test/DebugInfo/2009-11-05-DeadGlobalVariable.ll
index 13bd310..1ca88ae 100644
--- a/test/DebugInfo/2009-11-05-DeadGlobalVariable.ll
+++ b/test/DebugInfo/2009-11-05-DeadGlobalVariable.ll
@@ -9,18 +9,18 @@ entry:
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 720913, i32 12, metadata !6, metadata !"clang version 3.0 (trunk 139632)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !12, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 720913, metadata !17, i32 12, metadata !"clang version 3.0 (trunk 139632)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !12, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 720942, metadata !6, metadata !"foo", metadata !"foo", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @foo, null, null, metadata !10} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 720937, metadata !"fb.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
+!5 = metadata !{i32 720942, metadata !17, metadata !6, metadata !"foo", metadata !"foo", metadata !"", i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @foo, null, null, metadata !10, i32 0} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 720937, metadata !17} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{metadata !9}
-!9 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 720932, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !10 = metadata !{metadata !11}
 !11 = metadata !{i32 720932}                      ; [ DW_TAG_base_type ]
-!12 = metadata !{metadata !13}
-!13 = metadata !{metadata !14}
-!14 = metadata !{i32 720948, i32 0, metadata !5, metadata !"bar", metadata !"bar", metadata !"", metadata !6, i32 2, metadata !9, i32 1, i32 1, null} ; [ DW_TAG_variable ]
+!12 = metadata !{metadata !14}
+!14 = metadata !{i32 720948, i32 0, metadata !5, metadata !"bar", metadata !"bar", metadata !"", metadata !6, i32 2, metadata !9, i32 1, i32 1, null, null} ; [ DW_TAG_variable ]
 !15 = metadata !{i32 3, i32 3, metadata !16, null}
-!16 = metadata !{i32 720907, metadata !5, i32 1, i32 11, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
+!16 = metadata !{i32 720907, metadata !17, metadata !5, i32 1, i32 11, i32 0} ; [ DW_TAG_lexical_block ]
+!17 = metadata !{metadata !"fb.c", metadata !"/private/tmp"}
diff --git a/test/DebugInfo/2009-11-06-NamelessGlobalVariable.ll b/test/DebugInfo/2009-11-06-NamelessGlobalVariable.ll
index 0b81a01..aec299b 100644
--- a/test/DebugInfo/2009-11-06-NamelessGlobalVariable.ll
+++ b/test/DebugInfo/2009-11-06-NamelessGlobalVariable.ll
@@ -3,11 +3,10 @@
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"g.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 139632)", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{metadata !2}
+!0 = metadata !{i32 720913, metadata !8, i32 12, metadata !"clang version 3.0 (trunk 139632)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !2, metadata !3, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !2 = metadata !{i32 0}
-!3 = metadata !{metadata !4}
-!4 = metadata !{metadata !5}
-!5 = metadata !{i32 720948, i32 0, null, metadata !"", metadata !"", metadata !"", metadata !6, i32 2, metadata !7, i32 0, i32 1, i32* @0} ; [ DW_TAG_variable ]
-!6 = metadata !{i32 720937, metadata !"g.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
-!7 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!3 = metadata !{metadata !5}
+!5 = metadata !{i32 720948, i32 0, null, metadata !"a", metadata !"a", metadata !"", metadata !6, i32 2, metadata !7, i32 0, i32 1, i32* @0, null} ; [ DW_TAG_variable ]
+!6 = metadata !{i32 720937, metadata !8} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 720932, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!8 = metadata !{metadata !"g.c", metadata !"/private/tmp"}
diff --git a/test/DebugInfo/2009-11-10-CurrentFn.ll b/test/DebugInfo/2009-11-10-CurrentFn.ll
index 83d6ac2..10f2e88 100644
--- a/test/DebugInfo/2009-11-10-CurrentFn.ll
+++ b/test/DebugInfo/2009-11-10-CurrentFn.ll
@@ -12,19 +12,18 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 720913, i32 12, metadata !6, metadata !"clang version 3.0 (trunk 139632)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 720913, metadata !17, i32 12, metadata !"clang version 3.0 (trunk 139632)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 720942, metadata !6, metadata !"bar", metadata !"bar", metadata !"", metadata !6, i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void (i32)* @bar, null, null, metadata !9} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 720937, metadata !"cf.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
+!5 = metadata !{i32 720942, metadata !17, metadata !6, metadata !"bar", metadata !"bar", metadata !"", i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void (i32)* @bar, null, null, metadata !9, metadata !""} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 720937, metadata !17} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{null}
-!9 = metadata !{metadata !10}
-!10 = metadata !{metadata !11}
-!11 = metadata !{i32 721153, metadata !5, metadata !"i", metadata !6, i32 16777219, metadata !12, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
-!12 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!9 = metadata !{metadata !11}
+!11 = metadata !{i32 721153, metadata !17, metadata !5, metadata !"i", i32 16777219, metadata !12, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
+!12 = metadata !{i32 720932, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !13 = metadata !{i32 3, i32 14, metadata !5, null}
 !14 = metadata !{i32 4, i32 3, metadata !15, null}
-!15 = metadata !{i32 720907, metadata !5, i32 3, i32 17, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
+!15 = metadata !{i32 720907, metadata !17, metadata !5, i32 3, i32 17, i32 0} ; [ DW_TAG_lexical_block ]
 !16 = metadata !{i32 5, i32 1, metadata !15, null}
-
+!17 = metadata !{metadata !"cf.c", metadata !"/private/tmp"}
diff --git a/test/DebugInfo/2010-01-05-DbgScope.ll b/test/DebugInfo/2010-01-05-DbgScope.ll
index ad4c8d7..e421c93 100644
--- a/test/DebugInfo/2010-01-05-DbgScope.ll
+++ b/test/DebugInfo/2010-01-05-DbgScope.ll
@@ -8,11 +8,16 @@ entry:
 
 }
 
+!llvm.dbg.cu = !{!3}
+
 !0 = metadata !{i32 571, i32 3, metadata !1, null}
-!1 = metadata !{i32 458763, metadata !2, i32 1, i32 1}; [DW_TAG_lexical_block ]
-!2 = metadata !{i32 458798, i32 0, metadata !3, metadata !"foo", metadata !"foo", metadata !"foo", metadata !3, i32 561, metadata !4, i1 false, i1 true}; [DW_TAG_subprogram ]
-!3 = metadata !{i32 458769, i32 0, i32 12, metadata !"hashtab.c", metadata !"/usr/src/gnu/usr.bin/cc/cc_tools/../../../../contrib/gcclibs/libiberty", metadata !"clang 1.1", i1 true, i1 false, metadata !"", i32 0}; [DW_TAG_compile_unit ]
-!4 = metadata !{i32 458773, metadata !3, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0}; [DW_TAG_subroutine_type ]
+!1 = metadata !{i32 458763, metadata !11, metadata !2, i32 1, i32 1, i32 0}; [DW_TAG_lexical_block ]
+!2 = metadata !{i32 458798, i32 0, metadata !3, metadata !"foo", metadata !"foo", metadata !"foo", i32 561, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i32 0, null, null, null, null, i32 0}; [DW_TAG_subprogram ]
+!3 = metadata !{i32 458769, metadata !11, i32 12, metadata !"clang 1.1", i1 true, metadata !"", i32 0, metadata !12, metadata !12, metadata !13, null, null, metadata !""}; [DW_TAG_compile_unit ]
+!4 = metadata !{i32 458773, null, metadata !3, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0}; [DW_TAG_subroutine_type ]
 !5 = metadata !{metadata !6}
-!6 = metadata !{i32 458788, metadata !3, metadata !"char", metadata !3, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 458788, null, metadata !3, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !10 = metadata !{i32 588, i32 1, metadata !2, null}
+!11 = metadata !{metadata !"hashtab.c", metadata !"/usr/src/gnu/usr.bin/cc/cc_tools/../../../../contrib/gcclibs/libiberty"}
+!12 = metadata !{i32 0}
+!13 = metadata !{metadata !2}
diff --git a/test/DebugInfo/2010-01-19-DbgScope.ll b/test/DebugInfo/2010-01-19-DbgScope.ll
index 7afb5a5..6aedfc8 100644
--- a/test/DebugInfo/2010-01-19-DbgScope.ll
+++ b/test/DebugInfo/2010-01-19-DbgScope.ll
@@ -14,15 +14,20 @@ bb11:                                             ; preds = %entry
   ret i32 1, !dbg !11
 }
 
+!llvm.dbg.cu = !{!3}
+
 !0 = metadata !{i32 8647, i32 0, metadata !1, null}
-!1 = metadata !{i32 458763, metadata !2}          ; [ DW_TAG_lexical_block ]
-!2 = metadata !{i32 458798, i32 0, metadata !3, metadata !"bar", metadata !"bar", metadata !"bar", metadata !3, i32 8639, metadata !4, i1 true, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ]
-!3 = metadata !{i32 458769, i32 0, i32 1, metadata !"c-parser.c", metadata !"llvmgcc", metadata !"LLVM build 00", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!4 = metadata !{i32 458773, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0} ; [ DW_TAG_subroutine_type ]
+!1 = metadata !{i32 458763, metadata !12, metadata !2, i32 0, i32 0, i32 0}          ; [ DW_TAG_lexical_block ]
+!2 = metadata !{i32 458798, null, metadata !3, metadata !"bar", metadata !"bar", metadata !"bar", i32 8639, metadata !4, i1 true, i1 true, i32 0, i32 0, null, i32 0, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!3 = metadata !{i32 458769, metadata !12, i32 1, metadata !"LLVM build 00", i1 true, metadata !"", i32 0, metadata !13, metadata !13, metadata !14, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!4 = metadata !{i32 458773, null, metadata !3, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{metadata !6}
-!6 = metadata !{i32 458788, metadata !3, metadata !"char", metadata !3, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 458788, null, metadata !3, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !7 = metadata !{i32 8648, i32 0, metadata !8, null}
-!8 = metadata !{i32 458763, metadata !9}          ; [ DW_TAG_lexical_block ]
-!9 = metadata !{i32 458763, metadata !10}         ; [ DW_TAG_lexical_block ]
-!10 = metadata !{i32 458798, i32 0, metadata !3, metadata !"bar2", metadata !"bar2", metadata !"bar2", metadata !3, i32 8639, metadata !4, i1 true, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ]
+!8 = metadata !{i32 458763, metadata !12, metadata !9, i32 0, i32 0, i32 0}          ; [ DW_TAG_lexical_block ]
+!9 = metadata !{i32 458763, metadata !12, metadata !10, i32 0, i32 0, i32 0}         ; [ DW_TAG_lexical_block ]
+!10 = metadata !{i32 458798, null, metadata !3, metadata !"bar2", metadata !"bar2", metadata !"bar2", i32 8639, metadata !4, i1 true, i1 true, i32 0, i32 0, null, i32 0, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !11 = metadata !{i32 8652, i32 0, metadata !1, null}
+!12 = metadata !{metadata !"c-parser.c", metadata !"llvmgcc"}
+!13 = metadata !{i32 0}
+!14 = metadata !{metadata !2}
diff --git a/test/DebugInfo/2010-03-12-llc-crash.ll b/test/DebugInfo/2010-03-12-llc-crash.ll
index f6de234..114c870 100644
--- a/test/DebugInfo/2010-03-12-llc-crash.ll
+++ b/test/DebugInfo/2010-03-12-llc-crash.ll
@@ -10,11 +10,13 @@ entry:
 }
 
 !0 = metadata !{i32 524545, metadata !1, metadata !"sy", metadata !2, i32 890, metadata !7} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 892, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
-!2 = metadata !{i32 524329, metadata !"qpainter.h", metadata !"QtGui", metadata !3} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 524305, i32 0, i32 4, metadata !"splineeditor.cpp", metadata !"editor", metadata !"clang 1.1", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!4 = metadata !{i32 524309, metadata !5, metadata !"", metadata !5, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ]
-!5 = metadata !{i32 524329, metadata !"splineeditor.cpp", metadata !"src", metadata !3} ; [ DW_TAG_file_type ]
+!1 = metadata !{i32 524334, metadata !8, metadata !3, metadata !"foo", metadata !"foo", metadata !"foo", i32 892, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 524329, metadata !8} ; [ DW_TAG_file_type ]
+!3 = metadata !{i32 524305, metadata !9, i32 4, metadata !"clang 1.1", i1 true, metadata !"", i32 0, metadata !10, metadata !10, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!4 = metadata !{i32 524309, metadata !9, metadata !5, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!5 = metadata !{i32 524329, metadata !9} ; [ DW_TAG_file_type ]
 !6 = metadata !{null}
-!7 = metadata !{i32 524324, metadata !5, metadata !"int", metadata !5, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-
+!7 = metadata !{i32 524324, metadata !9, metadata !5, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!8 = metadata !{metadata !"qpainter.h", metadata !"QtGui"}
+!9 = metadata !{metadata !"splineeditor.cpp", metadata !"src"}
+!10 = metadata !{i32 0}
diff --git a/test/DebugInfo/2010-03-24-MemberFn.ll b/test/DebugInfo/2010-03-24-MemberFn.ll
index 15197f4..dfdf87f 100644
--- a/test/DebugInfo/2010-03-24-MemberFn.ll
+++ b/test/DebugInfo/2010-03-24-MemberFn.ll
@@ -39,19 +39,19 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!5}
 
 !0 = metadata !{i32 786688, metadata !1, metadata !"s1", metadata !4, i32 3, metadata !9, i32 0, null} ; [ DW_TAG_auto_variable ]
-!1 = metadata !{i32 786443, metadata !2, i32 3, i32 0} ; [ DW_TAG_lexical_block ]
-!2 = metadata !{i32 786443, metadata !3, i32 3, i32 0} ; [ DW_TAG_lexical_block ]
-!3 = metadata !{i32 786478, metadata !4, metadata !4, metadata !"bar", metadata !"bar", metadata !"_Z3barv", i32 3, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 ()* @_Z3barv, null, null, null, i32 3} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786443, metadata !25, metadata !2, i32 3, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!2 = metadata !{i32 786443, metadata !25, metadata !3, i32 3, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!3 = metadata !{i32 786478, metadata !25, metadata !4, metadata !"bar", metadata !"bar", metadata !"_Z3barv", i32 3, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @_Z3barv, null, null, null, i32 3} ; [ DW_TAG_subprogram ]
 !4 = metadata !{i32 786473, metadata !25} ; [ DW_TAG_file_type ]
-!5 = metadata !{i32 786449, i32 4, metadata !4, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !24, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
+!5 = metadata !{i32 786449, metadata !25, i32 4, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !27, metadata !27, metadata !24, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
 !6 = metadata !{i32 786453, metadata !25, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !7 = metadata !{metadata !8}
 !8 = metadata !{i32 786468, metadata !25, metadata !4, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !9 = metadata !{i32 786451, metadata !26, metadata !4, metadata !"S", i32 2, i64 8, i64 8, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ]
 !10 = metadata !{i32 786473, metadata !26} ; [ DW_TAG_file_type ]
 !11 = metadata !{metadata !12}
-!12 = metadata !{i32 786478, metadata !10, metadata !9, metadata !"foo", metadata !"foo", metadata !"_ZN1S3fooEv", i32 3, metadata !13, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 (%struct.S*)* @_ZN1S3fooEv, null, null, null, i32 3} ; [ DW_TAG_subprogram ]
-!13 = metadata !{i32 786453, metadata !25, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !14, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!12 = metadata !{i32 786478, metadata !26, metadata !9, metadata !"foo", metadata !"foo", metadata !"_ZN1S3fooEv", i32 3, metadata !13, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 (%struct.S*)* @_ZN1S3fooEv, null, null, null, i32 3} ; [ DW_TAG_subprogram ]
+!13 = metadata !{i32 786453, metadata !25, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !14, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !14 = metadata !{metadata !8, metadata !15}
 !15 = metadata !{i32 786447, metadata !25, metadata !4, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 64, metadata !9} ; [ DW_TAG_pointer_type ]
 !16 = metadata !{i32 3, i32 0, metadata !1, null}
@@ -61,7 +61,8 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 !20 = metadata !{i32 786447, metadata !25, metadata !4, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ]
 !21 = metadata !{i32 3, i32 0, metadata !12, null}
 !22 = metadata !{i32 3, i32 0, metadata !23, null}
-!23 = metadata !{i32 786443, metadata !12, i32 3, i32 0} ; [ DW_TAG_lexical_block ]
+!23 = metadata !{i32 786443, metadata !26, metadata !12, i32 3, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !24 = metadata !{metadata !3, metadata !12}
 !25 = metadata !{metadata !"one.cc", metadata !"/tmp/"}
 !26 = metadata !{metadata !"one.h", metadata !"/tmp/"}
+!27 = metadata !{i32 0}
diff --git a/test/DebugInfo/2010-03-30-InvalidDbgInfoCrash.ll b/test/DebugInfo/2010-03-30-InvalidDbgInfoCrash.ll
index accdf8a..7958f49 100644
--- a/test/DebugInfo/2010-03-30-InvalidDbgInfoCrash.ll
+++ b/test/DebugInfo/2010-03-30-InvalidDbgInfoCrash.ll
@@ -8,23 +8,27 @@ entry:
 
 declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 
+!llvm.dbg.cu = !{!5}
+
 !0 = metadata !{{ [0 x i8] }** undef}
 !1 = metadata !{i32 524544, metadata !2, metadata !"x", metadata !4, i32 11, metadata !9} ; [ DW_TAG_auto_variable ]
-!2 = metadata !{i32 524299, metadata !3, i32 8, i32 0} ; [ DW_TAG_lexical_block ]
-!3 = metadata !{i32 524334, i32 0, metadata !4, metadata !"baz", metadata !"baz", metadata !"baz", metadata !4, i32 8, metadata !6, i1 true, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
-!4 = metadata !{i32 524329, metadata !"2007-12-VarArrayDebug.c", metadata !"/Users/sabre/llvm/test/FrontendC/", metadata !5} ; [ DW_TAG_file_type ]
-!5 = metadata !{i32 524305, i32 0, i32 1, metadata !"2007-12-VarArrayDebug.c", metadata !"/Users/sabre/llvm/test/FrontendC/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!6 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 524299, metadata !20, metadata !3, i32 8, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!3 = metadata !{i32 524334, metadata !20, null, metadata !"baz", metadata !"baz", metadata !"baz", i32 8, metadata !6, i1 true, i1 true, i32 0, i32 0, null, i1 false, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!4 = metadata !{i32 524329, metadata !20} ; [ DW_TAG_file_type ]
+!5 = metadata !{i32 524305, metadata !20, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !21, metadata !21, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!6 = metadata !{i32 524309, metadata !20, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !7 = metadata !{null, metadata !8}
-!8 = metadata !{i32 524324, metadata !4, metadata !"int", metadata !4, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!9 = metadata !{i32 524303, metadata !4, metadata !"", metadata !4, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ]
-!10 = metadata !{i32 524307, metadata !3, metadata !"", metadata !4, i32 11, i64 8, i64 8, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ]
+!8 = metadata !{i32 524324, metadata !20, metadata !4, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 524303, metadata !20, metadata !4, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ]
+!10 = metadata !{i32 524307, metadata !20, metadata !3, metadata !"", i32 11, i64 8, i64 8, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ]
 !11 = metadata !{metadata !12}
-!12 = metadata !{i32 524301, metadata !10, metadata !"b", metadata !4, i32 11, i64 8, i64 8, i64 0, i32 0, metadata !13} ; [ DW_TAG_member ]
-!13 = metadata !{i32 524310, metadata !3, metadata !"A", metadata !4, i32 11, i64 0, i64 0, i64 0, i32 0, metadata !14} ; [ DW_TAG_typedef ]
-!14 = metadata !{i32 524289, metadata !4, metadata !"", metadata !4, i32 0, i64 8, i64 8, i64 0, i32 0, metadata !15, metadata !16, i32 0, null} ; [ DW_TAG_array_type ]
-!15 = metadata !{i32 524324, metadata !4, metadata !"char", metadata !4, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!12 = metadata !{i32 524301, metadata !20, metadata !10, metadata !"b", i32 11, i64 8, i64 8, i64 0, i32 0, metadata !13} ; [ DW_TAG_member ]
+!13 = metadata !{i32 524310, metadata !20, metadata !3, metadata !"A", i32 11, i64 0, i64 0, i64 0, i32 0, metadata !14} ; [ DW_TAG_typedef ]
+!14 = metadata !{i32 524289, metadata !20, metadata !4, metadata !"", i32 0, i64 8, i64 8, i64 0, i32 0, metadata !15, metadata !16, i32 0, null} ; [ DW_TAG_array_type ]
+!15 = metadata !{i32 524324, metadata !20, metadata !4, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !16 = metadata !{metadata !17}
 !17 = metadata !{i32 524321, i64 0, i64 1}        ; [ DW_TAG_subrange_type ]
 !18 = metadata !{metadata !"llvm.mdnode.fwdref.19"}
 !19 = metadata !{metadata !"llvm.mdnode.fwdref.23"}
+!20 = metadata !{metadata !"2007-12-VarArrayDebug.c", metadata !"/Users/sabre/llvm/test/FrontendC/"}
+!21 = metadata !{i32 0}
diff --git a/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll b/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll
index 7f8e418..aea98fd 100644
--- a/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll
+++ b/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll
@@ -54,32 +54,32 @@ entry:
 !37 = metadata !{metadata !2, metadata !10, metadata !23}
 
 !0 = metadata !{i32 786688, metadata !1, metadata !"b", metadata !3, i32 16, metadata !8, i32 0, null} ; [ DW_TAG_auto_variable ]
-!1 = metadata !{i32 786443, metadata !2, i32 15, i32 12} ; [ DW_TAG_lexical_block ]
-!2 = metadata !{i32 786478, metadata !3, metadata !"main", metadata !"main", metadata !"main", metadata !3, i32 15, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 ()* @main, null, null, null, i32 15} ; [ DW_TAG_subprogram ]
-!3 = metadata !{i32 786473, metadata !"one.cc", metadata !"/tmp", metadata !4} ; [ DW_TAG_file_type ]
-!4 = metadata !{i32 786449, i32 4, metadata !3, metadata !"clang 1.5", i1 false, metadata !"", i32 0, null, null, metadata !37, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
-!5 = metadata !{i32 786453, metadata !3, metadata !3, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!1 = metadata !{i32 786443, metadata !38, metadata !2, i32 15, i32 12, i32 0} ; [ DW_TAG_lexical_block ]
+!2 = metadata !{i32 786478, metadata !38, metadata !3, metadata !"main", metadata !"main", metadata !"main", i32 15, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 0, i32 ()* @main, null, null, null, i32 15} ; [ DW_TAG_subprogram ]
+!3 = metadata !{i32 786473, metadata !38} ; [ DW_TAG_file_type ]
+!4 = metadata !{i32 786449, metadata !38, i32 4, metadata !"clang 1.5", i1 false, metadata !"", i32 0, metadata !39, metadata !39, metadata !37, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
+!5 = metadata !{i32 786453, metadata !38, metadata !3, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !6 = metadata !{metadata !7}
-!7 = metadata !{i32 786468, metadata !3, metadata !3, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!8 = metadata !{i32 786434, metadata !3, metadata !3, metadata !"B", i32 2, i64 8, i64 8, i64 0, i32 0, null, metadata !9, i32 0, null} ; [ DW_TAG_class_type ]
+!7 = metadata !{i32 786468, metadata !38, metadata !3, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!8 = metadata !{i32 786434, metadata !38, metadata !3, metadata !"B", i32 2, i64 8, i64 8, i64 0, i32 0, null, metadata !9, i32 0, null} ; [ DW_TAG_class_type ]
 !9 = metadata !{metadata !10}
-!10 = metadata !{i32 786478, metadata !8, metadata !"fn", metadata !"fn", metadata !"_ZN1B2fnEv", metadata !3, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 (%class.A*)* @_ZN1B2fnEv, null, null, null, i32 4} ; [ DW_TAG_subprogram ]
-!11 = metadata !{i32 786453, metadata !3, metadata !3, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!10 = metadata !{i32 786478, metadata !38, metadata !8, metadata !"fn", metadata !"fn", metadata !"_ZN1B2fnEv", i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 0, i32 (%class.A*)* @_ZN1B2fnEv, null, null, null, i32 4} ; [ DW_TAG_subprogram ]
+!11 = metadata !{i32 786453, metadata !38, metadata !3, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !12 = metadata !{metadata !7, metadata !13}
-!13 = metadata !{i32 786447, metadata !3, metadata !3, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 64, metadata !8} ; [ DW_TAG_pointer_type ]
+!13 = metadata !{i32 786447, metadata !38, metadata !3, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 64, metadata !8} ; [ DW_TAG_pointer_type ]
 !14 = metadata !{i32 16, i32 5, metadata !1, null}
 !15 = metadata !{i32 17, i32 3, metadata !1, null}
 !16 = metadata !{i32 18, i32 1, metadata !2, null}
 !17 = metadata !{i32 786689, metadata !10, metadata !"this", metadata !3, i32 4, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ]
 !18 = metadata !{i32 4, i32 7, metadata !10, null}
 !19 = metadata !{i32 786688, metadata !20, metadata !"a", metadata !3, i32 9, metadata !21, i32 0, null} ; [ DW_TAG_auto_variable ]
-!20 = metadata !{i32 786443, metadata !10, i32 4, i32 12} ; [ DW_TAG_lexical_block ]
-!21 = metadata !{i32 786434, metadata !3, metadata !10, metadata !"A", i32 5, i64 8, i64 8, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_class_type ]
+!20 = metadata !{i32 786443, metadata !38, metadata !10, i32 4, i32 12, i32 0} ; [ DW_TAG_lexical_block ]
+!21 = metadata !{i32 786434, metadata !38, metadata !10, metadata !"A", i32 5, i64 8, i64 8, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_class_type ]
 !22 = metadata !{metadata !23}
-!23 = metadata !{i32 786478, metadata !21, metadata !"foo", metadata !"foo", metadata !"_ZZN1B2fnEvEN1A3fooEv", metadata !3, i32 7, metadata !24, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 (%class.A*)* @_ZZN1B2fnEvEN1A3fooEv, null, null, null, i32 7} ; [ DW_TAG_subprogram ]
-!24 = metadata !{i32 786453, metadata !3, metadata !3, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !25, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!23 = metadata !{i32 786478, metadata !38, metadata !21, metadata !"foo", metadata !"foo", metadata !"_ZZN1B2fnEvEN1A3fooEv", i32 7, metadata !24, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 0, i32 (%class.A*)* @_ZZN1B2fnEvEN1A3fooEv, null, null, null, i32 7} ; [ DW_TAG_subprogram ]
+!24 = metadata !{i32 786453, metadata !38, metadata !3, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !25, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !25 = metadata !{metadata !7, metadata !26}
-!26 = metadata !{i32 786447, metadata !3, metadata !3, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 64, metadata !21} ; [ DW_TAG_pointer_type ]
+!26 = metadata !{i32 786447, metadata !38, metadata !3, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 64, metadata !21} ; [ DW_TAG_pointer_type ]
 !27 = metadata !{i32 9, i32 7, metadata !20, null}
 !28 = metadata !{i32 786688, metadata !20, metadata !"i", metadata !3, i32 10, metadata !7, i32 0, null} ; [ DW_TAG_auto_variable ]
 !29 = metadata !{i32 10, i32 9, metadata !20, null}
@@ -89,4 +89,6 @@ entry:
 !33 = metadata !{i32 786689, metadata !23, metadata !"this", metadata !3, i32 7, metadata !26, i32 0, null} ; [ DW_TAG_arg_variable ]
 !34 = metadata !{i32 7, i32 11, metadata !23, null}
 !35 = metadata !{i32 7, i32 19, metadata !36, null}
-!36 = metadata !{i32 786443, metadata !23, i32 7, i32 17} ; [ DW_TAG_lexical_block ]
+!36 = metadata !{i32 786443, metadata !38, metadata !23, i32 7, i32 17, i32 0} ; [ DW_TAG_lexical_block ]
+!38 = metadata !{metadata !"one.cc", metadata !"/tmp" }
+!39 = metadata !{i32 0}
diff --git a/test/DebugInfo/2010-04-19-FramePtr.ll b/test/DebugInfo/2010-04-19-FramePtr.ll
index 88eebe6..30aad38 100644
--- a/test/DebugInfo/2010-04-19-FramePtr.ll
+++ b/test/DebugInfo/2010-04-19-FramePtr.ll
@@ -1,6 +1,6 @@
-; RUN: llc -asm-verbose -O0 -o %t < %s 
+; RUN: llc -asm-verbose -O1 -o %t < %s 
 ; RUN: grep DW_AT_APPLE_omit_frame_ptr %t
-; RUN: llc -disable-fp-elim -asm-verbose -O0 -o %t < %s 
+; RUN: llc -disable-fp-elim -asm-verbose -O1 -o %t < %s 
 ; RUN: grep -v DW_AT_APPLE_omit_frame_ptr %t
 
 
@@ -23,11 +23,13 @@ return:                                           ; preds = %entry
 !9 = metadata !{metadata !1}
 
 !0 = metadata !{i32 2, i32 0, metadata !1, null}
-!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 2, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 ()* @foo, null, null, null, i32 2} ; [ DW_TAG_subprogram ]
-!2 = metadata !{i32 786473, metadata !"a.c", metadata !"/tmp", metadata !3} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !9, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
-!4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!1 = metadata !{i32 786478, metadata !10, null, metadata !"foo", metadata !"foo", metadata !"foo", i32 2, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @foo, null, null, null, i32 2} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 786473, metadata !10} ; [ DW_TAG_file_type ]
+!3 = metadata !{i32 786449, metadata !10, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !11, metadata !11, metadata !9, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
+!4 = metadata !{i32 786453, metadata !10, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{metadata !6}
-!6 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786468, metadata !10, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !7 = metadata !{i32 2, i32 0, metadata !8, null}
-!8 = metadata !{i32 786443, metadata !1, i32 2, i32 0} ; [ DW_TAG_lexical_block ]
+!8 = metadata !{i32 786443, metadata !10, metadata !1, i32 2, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!10 = metadata !{metadata !"a.c", metadata !"/tmp"}
+!11 = metadata !{i32 0}
diff --git a/test/DebugInfo/2010-05-03-DisableFramePtr.ll b/test/DebugInfo/2010-05-03-DisableFramePtr.ll
index 4061bdc..1aa2240 100644
--- a/test/DebugInfo/2010-05-03-DisableFramePtr.ll
+++ b/test/DebugInfo/2010-05-03-DisableFramePtr.ll
@@ -1,8 +1,8 @@
-; RUN: llc  -o /dev/null -disable-non-leaf-fp-elim < %s
+; RUN: llc  -o /dev/null < %s
 ; Radar 7937664
 %struct.AppleEvent = type opaque
 
-define void @DisposeDMNotificationUPP(void (%struct.AppleEvent*)* %userUPP) nounwind ssp {
+define void @DisposeDMNotificationUPP(void (%struct.AppleEvent*)* %userUPP) "no-frame-pointer-elim-non-leaf"="true" nounwind ssp {
 entry:
   %userUPP_addr = alloca void (%struct.AppleEvent*)* ; <void (%struct.AppleEvent*)**> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
@@ -16,19 +16,23 @@ return:                                           ; preds = %entry
 
 declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 
-!0 = metadata !{i32 524545, metadata !1, metadata !"userUPP", metadata !2, i32 7, metadata !6} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"DisposeDMNotificationUPP", metadata !"DisposeDMNotificationUPP", metadata !"DisposeDMNotificationUPP", metadata !2, i32 7, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
-!2 = metadata !{i32 524329, metadata !"t.c", metadata !"/Users/echeng/LLVM/radars/r7937664/", metadata !3} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"t.c", metadata !"/Users/echeng/LLVM/radars/r7937664/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!llvm.dbg.cu = !{!3}
+!0 = metadata !{i32 524545, metadata !1, metadata !"userUPP", metadata !2, i32 7, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ]
+!1 = metadata !{i32 524334, metadata !16, null, metadata !"DisposeDMNotificationUPP", metadata !"DisposeDMNotificationUPP", metadata !"DisposeDMNotificationUPP", i32 7, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 524329, metadata !16} ; [ DW_TAG_file_type ]
+!3 = metadata !{i32 524305, metadata !16, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)", i1 true, metadata !"", i32 0, metadata !17, metadata !17, metadata !18, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!4 = metadata !{i32 524309, metadata !16, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{null, metadata !6}
-!6 = metadata !{i32 524310, metadata !2, metadata !"DMNotificationUPP", metadata !2, i32 6, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ]
-!7 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ]
-!8 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !9, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!6 = metadata !{i32 524310, metadata !16, metadata !2, metadata !"DMNotificationUPP", i32 6, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ]
+!7 = metadata !{i32 524303, metadata !16, metadata !2, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ]
+!8 = metadata !{i32 524309, metadata !16, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !9, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !9 = metadata !{null, metadata !10}
-!10 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ]
-!11 = metadata !{i32 524310, metadata !2, metadata !"AppleEvent", metadata !2, i32 4, i64 0, i64 0, i64 0, i32 0, metadata !12} ; [ DW_TAG_typedef ]
-!12 = metadata !{i32 524307, metadata !2, metadata !"AEDesc", metadata !2, i32 1, i64 0, i64 0, i64 0, i32 4, null, null, i32 0, null} ; [ DW_TAG_structure_type ]
+!10 = metadata !{i32 524303, metadata !16, metadata !2, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ]
+!11 = metadata !{i32 524310, metadata !16, metadata !2, metadata !"AppleEvent", i32 4, i64 0, i64 0, i64 0, i32 0, metadata !12} ; [ DW_TAG_typedef ]
+!12 = metadata !{i32 524307, metadata !16, metadata !2, metadata !"AEDesc", i32 1, i64 0, i64 0, i64 0, i32 4, null, null, i32 0, null} ; [ DW_TAG_structure_type ]
 !13 = metadata !{i32 7, i32 0, metadata !1, null}
 !14 = metadata !{i32 8, i32 0, metadata !15, null}
-!15 = metadata !{i32 524299, metadata !1, i32 7, i32 0} ; [ DW_TAG_lexical_block ]
+!15 = metadata !{i32 524299, metadata !16, metadata !1, i32 7, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!16 = metadata !{metadata !"t.c", metadata !"/Users/echeng/LLVM/radars/r7937664/"}
+!17 = metadata !{i32 0}
+!18 = metadata !{metadata !1}
diff --git a/test/DebugInfo/2010-05-03-OriginDIE.ll b/test/DebugInfo/2010-05-03-OriginDIE.ll
index 1ade045..b4c2bc2b 100644
--- a/test/DebugInfo/2010-05-03-OriginDIE.ll
+++ b/test/DebugInfo/2010-05-03-OriginDIE.ll
@@ -48,39 +48,45 @@ declare i64 @llvm.bswap.i64(i64) nounwind readnone
 
 declare void @uuid_LtoB(i8*, i8*)
 
+!llvm.dbg.cu = !{!4}
 !0 = metadata !{i32 808, i32 0, metadata !1, null}
-!1 = metadata !{i32 524299, metadata !2, i32 807, i32 0} ; [ DW_TAG_lexical_block ]
-!2 = metadata !{i32 524334, i32 0, metadata !3, metadata !"gpt2gpm", metadata !"gpt2gpm", metadata !"gpt2gpm", metadata !3, i32 807, metadata !5, i1 true, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
-!3 = metadata !{i32 524329, metadata !"G.c", metadata !"/tmp", metadata !4} ; [ DW_TAG_file_type ]
-!4 = metadata !{i32 524305, i32 0, i32 1, metadata !"G.c", metadata !"/tmp", metadata !"llvm-gcc", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!5 = metadata !{i32 524309, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!1 = metadata !{i32 524299, metadata !39, metadata !2, i32 807, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!2 = metadata !{i32 524334, metadata !39, null, metadata !"gpt2gpm", metadata !"gpt2gpm", metadata !"gpt2gpm", i32 807, metadata !5, i1 true, i1 true, i32 0, i32 0, null, i1 false, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!3 = metadata !{i32 524329, metadata !39} ; [ DW_TAG_file_type ]
+!4 = metadata !{i32 524305, metadata !39, i32 1, metadata !"llvm-gcc", i1 true, metadata !"", i32 0, metadata !18, metadata !18, metadata !40, null, null, i32 0} ; [ DW_TAG_compile_unit ]
+!5 = metadata !{i32 524309, metadata !39, metadata !3, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !6 = metadata !{null}
 !7 = metadata !{i32 810, i32 0, metadata !1, null}
 !8 = metadata !{i32 524545, metadata !9, metadata !"data", metadata !10, i32 201, metadata !11} ; [ DW_TAG_arg_variable ]
-!9 = metadata !{i32 524334, i32 0, metadata !3, metadata !"_OSSwapInt64", metadata !"_OSSwapInt64", metadata !"_OSSwapInt64", metadata !10, i32 202, metadata !5, i1 true, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
+!9 = metadata !{i32 524334, metadata !10, null, metadata !"_OSSwapInt64", metadata !"_OSSwapInt64", metadata !"_OSSwapInt64", i32 202, metadata !5, i1 true, i1 true, i32 0, i32 0, null, i1 false, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !10 = metadata !{i32 524329, metadata !"OSByteOrder.h", metadata !"/usr/include/libkern/ppc", metadata !4} ; [ DW_TAG_file_type ]
-!11 = metadata !{i32 524310, metadata !3, metadata !"uint64_t", metadata !12, i32 59, i64 0, i64 0, i64 0, i32 0, metadata !13} ; [ DW_TAG_typedef ]
+!11 = metadata !{i32 524310, metadata !36, metadata !3, metadata !"uint64_t", i32 59, i64 0, i64 0, i64 0, i32 0, metadata !13} ; [ DW_TAG_typedef ]
 !12 = metadata !{i32 524329, metadata !"stdint.h", metadata !"/usr/4.2.1/include", metadata !4} ; [ DW_TAG_file_type ]
-!13 = metadata !{i32 524324, metadata !3, metadata !"long long unsigned int", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!13 = metadata !{i32 524324, metadata !39, metadata !3, metadata !"long long unsigned int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
 !14 = metadata !{i32 202, i32 0, metadata !9, metadata !7}
 !15 = metadata !{i32 524545, metadata !16, metadata !"base", metadata !10, i32 92, metadata !17} ; [ DW_TAG_arg_variable ]
-!16 = metadata !{i32 524334, i32 0, metadata !3, metadata !"OSReadSwapInt64", metadata !"OSReadSwapInt64", metadata !"OSReadSwapInt64", metadata !10, i32 95, metadata !5, i1 true, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
-!17 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
+!16 = metadata !{i32 524334, metadata !38, null, metadata !"OSReadSwapInt64", metadata !"OSReadSwapInt64", metadata !"OSReadSwapInt64", i32 95, metadata !5, i1 true, i1 true, i32 0, i32 0, null, i1 false, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!17 = metadata !{i32 524303, metadata !39, metadata !3, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
 !18 = metadata !{i32 0}
 !19 = metadata !{i32 524545, metadata !16, metadata !"byteOffset", metadata !10, i32 94, metadata !20} ; [ DW_TAG_arg_variable ]
-!20 = metadata !{i32 524310, metadata !3, metadata !"uintptr_t", metadata !21, i32 114, i64 0, i64 0, i64 0, i32 0, metadata !22} ; [ DW_TAG_typedef ]
+!20 = metadata !{i32 524310, metadata !37, metadata !3, metadata !"uintptr_t", i32 114, i64 0, i64 0, i64 0, i32 0, metadata !22} ; [ DW_TAG_typedef ]
 !21 = metadata !{i32 524329, metadata !"types.h", metadata !"/usr/include/ppc", metadata !4} ; [ DW_TAG_file_type ]
-!22 = metadata !{i32 524324, metadata !3, metadata !"long unsigned int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!22 = metadata !{i32 524324, metadata !39, metadata !3, metadata !"long unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
 !23 = metadata !{i32 524544, metadata !24, metadata !"u", metadata !10, i32 100, metadata !25} ; [ DW_TAG_auto_variable ]
-!24 = metadata !{i32 524299, metadata !16, i32 95, i32 0} ; [ DW_TAG_lexical_block ]
-!25 = metadata !{i32 524311, metadata !16, metadata !"", metadata !10, i32 97, i64 64, i64 64, i64 0, i32 0, null, metadata !26, i32 0, null} ; [ DW_TAG_union_type ]
+!24 = metadata !{i32 524299, metadata !38, metadata !16, i32 95, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!25 = metadata !{i32 524311, metadata !38, metadata !16, metadata !"", i32 97, i64 64, i64 64, i64 0, i32 0, null, metadata !26, i32 0, null} ; [ DW_TAG_union_type ]
 !26 = metadata !{metadata !27, metadata !28}
-!27 = metadata !{i32 524301, metadata !25, metadata !"u64", metadata !10, i32 98, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_member ]
-!28 = metadata !{i32 524301, metadata !25, metadata !"u32", metadata !10, i32 99, i64 64, i64 32, i64 0, i32 0, metadata !29} ; [ DW_TAG_member ]
-!29 = metadata !{i32 524289, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 32, i64 0, i32 0, metadata !30, metadata !32, i32 0, null} ; [ DW_TAG_array_type ]
-!30 = metadata !{i32 524310, metadata !3, metadata !"uint32_t", metadata !12, i32 55, i64 0, i64 0, i64 0, i32 0, metadata !31} ; [ DW_TAG_typedef ]
-!31 = metadata !{i32 524324, metadata !3, metadata !"unsigned int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!27 = metadata !{i32 524301, metadata !38, metadata !25, metadata !"u64", i32 98, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_member ]
+!28 = metadata !{i32 524301, metadata !38, metadata !25, metadata !"u32", i32 99, i64 64, i64 32, i64 0, i32 0, metadata !29} ; [ DW_TAG_member ]
+!29 = metadata !{i32 524289, metadata !39, metadata !3, metadata !"", i32 0, i64 64, i64 32, i64 0, i32 0, metadata !30, metadata !32, i32 0, null} ; [ DW_TAG_array_type ]
+!30 = metadata !{i32 524310, metadata !36, metadata !3, metadata !"uint32_t", i32 55, i64 0, i64 0, i64 0, i32 0, metadata !31} ; [ DW_TAG_typedef ]
+!31 = metadata !{i32 524324, metadata !39, metadata !3, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
 !32 = metadata !{metadata !33}
 !33 = metadata !{i32 524321, i64 0, i64 2}        ; [ DW_TAG_subrange_type ]
 !34 = metadata !{i32 524544, metadata !24, metadata !"addr", metadata !10, i32 96, metadata !35} ; [ DW_TAG_auto_variable ]
-!35 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ]
+!35 = metadata !{i32 524303, metadata !39, metadata !3, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ]
+!36 = metadata !{metadata !"stdint.h", metadata !"/usr/4.2.1/include"}
+!37 = metadata !{metadata !"types.h", metadata !"/usr/include/ppc"}
+!38 = metadata !{metadata !"OSByteOrder.h", metadata !"/usr/include/libkern/ppc"}
+!39 = metadata !{metadata !"G.c", metadata !"/tmp"}
+!40 = metadata !{metadata !2, metadata !9, metadata !16}
diff --git a/test/DebugInfo/2010-05-10-MultipleCU.ll b/test/DebugInfo/2010-05-10-MultipleCU.ll
index 75e4389..da0b2e8 100644
--- a/test/DebugInfo/2010-05-10-MultipleCU.ll
+++ b/test/DebugInfo/2010-05-10-MultipleCU.ll
@@ -31,18 +31,21 @@ return:
 !17 = metadata !{metadata !10}
 
 !0 = metadata !{i32 3, i32 0, metadata !1, null}
-!1 = metadata !{i32 786443, metadata !2, i32 2, i32 0} ; [ DW_TAG_lexical_block ]
-!2 = metadata !{i32 786478, metadata !3, metadata !"foo", metadata !"foo", metadata !"foo", metadata !3, i32 2, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
-!3 = metadata !{i32 786473, metadata !"a.c", metadata !"/tmp/", metadata !4} ; [ DW_TAG_file_type ]
-!4 = metadata !{i32 786449, i32 1, metadata !3, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !16, null, metadata !""} ; [ DW_TAG_compile_unit ]
-!5 = metadata !{i32 786453, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!1 = metadata !{i32 786443, metadata !18, metadata !2, i32 2, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!2 = metadata !{i32 786478, metadata !18, metadata !3, metadata !"foo", metadata !"foo", metadata !"foo", i32 2, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!3 = metadata !{i32 786473, metadata !18} ; [ DW_TAG_file_type ]
+!4 = metadata !{i32 786449, metadata !18, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !19, metadata !19, metadata !16, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!5 = metadata !{i32 786453, metadata !18, metadata !3, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !6 = metadata !{metadata !7}
-!7 = metadata !{i32 786468, metadata !3, metadata !"int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!7 = metadata !{i32 786468, metadata !18, metadata !3, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !8 = metadata !{i32 3, i32 0, metadata !9, null}
-!9 = metadata !{i32 786443, metadata !10, i32 2, i32 0} ; [ DW_TAG_lexical_block ]
-!10 = metadata !{i32 786478, metadata !11, metadata !"bar", metadata !"bar", metadata !"bar", metadata !11, i32 2, metadata !13, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @bar, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
-!11 = metadata !{i32 786473, metadata !"b.c", metadata !"/tmp/", metadata !12} ; [ DW_TAG_file_type ]
-!12 = metadata !{i32 786449, i32 1, metadata !11, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !17, null, metadata !""} ; [ DW_TAG_compile_unit ]
-!13 = metadata !{i32 786453, metadata !11, metadata !"", metadata !11, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !14, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!9 = metadata !{i32 786443, metadata !20, metadata !10, i32 2, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!10 = metadata !{i32 786478, metadata !20, metadata !11, metadata !"bar", metadata !"bar", metadata !"bar", i32 2, metadata !13, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @bar, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!11 = metadata !{i32 786473, metadata !20} ; [ DW_TAG_file_type ]
+!12 = metadata !{i32 786449, metadata !20, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !19, metadata !19, metadata !17, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!13 = metadata !{i32 786453, metadata !20, metadata !11, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !14, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !14 = metadata !{metadata !15}
-!15 = metadata !{i32 786468, metadata !11, metadata !"int", metadata !11, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!15 = metadata !{i32 786468, metadata !20, metadata !11, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!18 = metadata !{metadata !"a.c", metadata !"/tmp/"}
+!19 = metadata !{i32 0}
+!20 = metadata !{metadata !"b.c", metadata !"/tmp/"}
diff --git a/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll b/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll
index f5ebb2d..295648f 100644
--- a/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll
+++ b/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll
@@ -2,7 +2,7 @@
 ; Check struct X for dead variable xyz from inlined function foo.
 
 ; CHECK:	DW_TAG_structure_type
-; CHECK-NEXT:	DW_AT_name
+; CHECK-NEXT:	info_string
  
 
 @i = common global i32 0                          ; <i32*> [#uses=2]
@@ -23,13 +23,13 @@ entry:
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 9, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 true, null, null, null, metadata !24, i32 9} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !27, metadata !1, metadata !"foo", metadata !"foo", metadata !"", i32 9, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 true, null, null, null, metadata !24, i32 9} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !27} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !25, metadata !26,  metadata !26, metadata !""} ; [ DW_TAG_compile_unit ]
+!2 = metadata !{i32 786449, metadata !27, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !20, metadata !20, metadata !25, metadata !26,  metadata !26, metadata !""} ; [ DW_TAG_compile_unit ]
 !3 = metadata !{i32 786453, metadata !27, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5, metadata !5}
 !5 = metadata !{i32 786468, metadata !27, metadata !1, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 786478, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", metadata !1, i32 14, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @bar} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 786478, metadata !27, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", i32 14, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @bar, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !7 = metadata !{i32 786453, metadata !27, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{metadata !5}
 !9 = metadata !{i32 786689, metadata !0, metadata !"j", metadata !1, i32 9, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
@@ -39,7 +39,7 @@ entry:
 !13 = metadata !{metadata !14, metadata !15}
 !14 = metadata !{i32 786445, metadata !27, metadata !12, metadata !"a", i32 10, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ]
 !15 = metadata !{i32 786445, metadata !27, metadata !12, metadata !"b", i32 10, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ]
-!16 = metadata !{i32 786484, i32 0, metadata !1, metadata !"i", metadata !"i", metadata !"", metadata !1, i32 5, metadata !5, i1 false, i1 true, i32* @i} ; [ DW_TAG_variable ]
+!16 = metadata !{i32 786484, i32 0, metadata !1, metadata !"i", metadata !"i", metadata !"", metadata !1, i32 5, metadata !5, i1 false, i1 true, i32* @i, null} ; [ DW_TAG_variable ]
 !17 = metadata !{i32 15, i32 0, metadata !18, null}
 !18 = metadata !{i32 786443, metadata !1, metadata !6, i32 14, i32 0, i32 1} ; [ DW_TAG_lexical_block ]
 !19 = metadata !{i32 9, i32 0, metadata !0, metadata !17}
diff --git a/test/DebugInfo/2010-07-19-Crash.ll b/test/DebugInfo/2010-07-19-Crash.ll
index 87a4a89..a395efe 100644
--- a/test/DebugInfo/2010-07-19-Crash.ll
+++ b/test/DebugInfo/2010-07-19-Crash.ll
@@ -7,18 +7,22 @@ entry:
   ret i32 42, !dbg !9
 }
 
+!llvm.dbg.cu = !{!2}
 !llvm.dbg.sp = !{!0, !6, !11}
 !llvm.dbg.lv.foo = !{!7}
 
-!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @bar} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 524329, metadata !"one.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"one.c", metadata !".", metadata !"clang 2.8", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 524334, metadata !12, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @bar, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 524329, metadata !12} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 524305, metadata !12, i32 12, metadata !"clang 2.8", i1 true, metadata !"", i32 0, metadata !14, metadata !14, metadata !13, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 524309, metadata !12, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 7, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 true, null} ; [ DW_TAG_subprogram ]
-!11 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 7, metadata !3, i1 true, i1 false, i32 0, i32 0, null, i1 false, i1 true, null} ; [ DW_TAG_subprogram ]
+!5 = metadata !{i32 524324, metadata !12, metadata !1, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 524334, metadata !12, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", i32 7, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 true, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !7 = metadata !{i32 524544, metadata !8, metadata !"one", metadata !1, i32 8, metadata !5} ; [ DW_TAG_auto_variable ]
-!8 = metadata !{i32 524299, metadata !6, i32 7, i32 18} ; [ DW_TAG_lexical_block ]
+!8 = metadata !{i32 524299, metadata !12, metadata !6, i32 7, i32 18, i32 0} ; [ DW_TAG_lexical_block ]
 !9 = metadata !{i32 4, i32 3, metadata !10, null}
-!10 = metadata !{i32 524299, metadata !0, i32 3, i32 11} ; [ DW_TAG_lexical_block ]
+!10 = metadata !{i32 524299, metadata !12, metadata !0, i32 3, i32 11, i32 0} ; [ DW_TAG_lexical_block ]
+!11 = metadata !{i32 524334, metadata !12, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", i32 7, metadata !3, i1 true, i1 false, i32 0, i32 0, null, i1 false, i1 true, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!12 = metadata !{metadata !"one.c", metadata !"/private/tmp"}
+!13 = metadata !{metadata !0, metadata !6, metadata !11}
+!14 = metadata !{i32 0}
diff --git a/test/DebugInfo/2010-10-01-crash.ll b/test/DebugInfo/2010-10-01-crash.ll
index c4161b4..ddb9acc 100644
--- a/test/DebugInfo/2010-10-01-crash.ll
+++ b/test/DebugInfo/2010-10-01-crash.ll
@@ -13,10 +13,12 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
 
 
-!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"CGRectStandardize", metadata !"CGRectStandardize", metadata !"CGRectStandardize", metadata !1, i32 54, null, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void (i32*, i32*)* @CGRectStandardize} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 589865, metadata !"GSFusedSilica.m", metadata !"/Volumes/Data/Users/sabre/Desktop", metadata !2}
-!2 = metadata !{i32 589841, i32 0, i32 16, metadata !"GSFusedSilica.m", metadata !"/Volumes/Data/Users/sabre/Desktop", metadata !"clang version 2.9 (trunk 115292)", i1 true, i1 false, metadata !"", i32 1} ; [ DW_TAG_compile_unit ]
-!5 = metadata !{i32 589846, metadata !1, metadata !"CGRect", metadata !1, i32 49, i64 0, i64 0, i64 0, i32 0, null}
+!llvm.dbg.cu = !{!2}
+!0 = metadata !{i32 589870, metadata !1, i32 0, metadata !"CGRectStandardize", metadata !"CGRectStandardize", metadata !"CGRectStandardize", i32 54, null, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void (i32*, i32*)* @CGRectStandardize, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 589865, metadata !25}
+!2 = metadata !{i32 589841, metadata !25, i32 16, metadata !"clang version 2.9 (trunk 115292)", i1 true, metadata !"", i32 1, metadata !26, metadata !26, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!5 = metadata !{i32 589846, metadata !25, null, metadata !"CGRect", i32 49, i64 0, i64 0, i64 0, i32 0, null}
 !23 = metadata !{i32 590081, metadata !0, metadata !"rect", metadata !1, i32 53, metadata !5, i32 0} ; [ DW_TAG_arg_variable ]
 !24 = metadata !{i32 53, i32 33, metadata !0, null}
-
+!25 = metadata !{metadata !"GSFusedSilica.m", metadata !"/Volumes/Data/Users/sabre/Desktop"}
+!26 = metadata !{i32 0}
diff --git a/test/DebugInfo/AArch64/dwarfdump.ll b/test/DebugInfo/AArch64/dwarfdump.ll
index bcdd462..2598d5c 100644
--- a/test/DebugInfo/AArch64/dwarfdump.ll
+++ b/test/DebugInfo/AArch64/dwarfdump.ll
@@ -25,10 +25,10 @@ attributes #0 = { nounwind }
 !0 = metadata !{i32 786449, metadata !9, i32 12, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !2, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/timnor01/llvm/build/tmp.c] [DW_LANG_C99]
 !1 = metadata !{i32 0}
 !2 = metadata !{metadata !3}
-!3 = metadata !{i32 786478, metadata !4, metadata !"main", metadata !"main", metadata !"", metadata !4, i32 1, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main, null, null, metadata !1, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [main]
+!3 = metadata !{i32 786478, metadata !9, metadata !4, metadata !"main", metadata !"main", metadata !"", i32 1, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main, null, null, metadata !1, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [main]
 !4 = metadata !{i32 786473, metadata !9} ; [ DW_TAG_file_type ]
-!5 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = metadata !{i32 786453, null, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !6 = metadata !{metadata !7}
-!7 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!7 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
 !8 = metadata !{i32 2, i32 0, metadata !3, null}
 !9 = metadata !{metadata !"tmp.c", metadata !"/home/tim/llvm/build"}
diff --git a/test/DebugInfo/AArch64/variable-loc.ll b/test/DebugInfo/AArch64/variable-loc.ll
index 05a5bd0..30eabc8 100644
--- a/test/DebugInfo/AArch64/variable-loc.ll
+++ b/test/DebugInfo/AArch64/variable-loc.ll
@@ -72,20 +72,20 @@ declare i32 @printf(i8*, ...)
 !0 = metadata !{i32 786449, metadata !29, i32 12, metadata !"clang version 3.2 ", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/timnor01/a64-trunk/build/simple.c] [DW_LANG_C99]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5, metadata !11, metadata !14}
-!5 = metadata !{i32 786478, metadata !6, metadata !"populate_array", metadata !"populate_array", metadata !"", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32*, i32)* @populate_array, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ] [line 4] [def] [populate_array]
+!5 = metadata !{i32 786478, metadata !29, metadata !6, metadata !"populate_array", metadata !"populate_array", metadata !"", i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32*, i32)* @populate_array, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ] [line 4] [def] [populate_array]
 !6 = metadata !{i32 786473, metadata !29} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !8 = metadata !{null, metadata !9, metadata !10}
 !9 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
 !10 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!11 = metadata !{i32 786478, metadata !6, metadata !"sum_array", metadata !"sum_array", metadata !"", metadata !6, i32 9, metadata !12, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32*, i32)* @sum_array, null, null, metadata !1, i32 9} ; [ DW_TAG_subprogram ] [line 9] [def] [sum_array]
+!11 = metadata !{i32 786478, metadata !29, metadata !6, metadata !"sum_array", metadata !"sum_array", metadata !"", i32 9, metadata !12, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32*, i32)* @sum_array, null, null, metadata !1, i32 9} ; [ DW_TAG_subprogram ] [line 9] [def] [sum_array]
 !12 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !13, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !13 = metadata !{metadata !10, metadata !9, metadata !10}
-!14 = metadata !{i32 786478, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 18, metadata !15, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, metadata !1, i32 18} ; [ DW_TAG_subprogram ] [line 18] [def] [main]
+!14 = metadata !{i32 786478, metadata !29, metadata !6, metadata !"main", metadata !"main", metadata !"", i32 18, metadata !15, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, metadata !1, i32 18} ; [ DW_TAG_subprogram ] [line 18] [def] [main]
 !15 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !16, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !16 = metadata !{metadata !10}
 !17 = metadata !{i32 786688, metadata !18, metadata !"main_arr", metadata !6, i32 19, metadata !19, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [main_arr] [line 19]
-!18 = metadata !{i32 786443, metadata !6, metadata !14, i32 18, i32 16, i32 4} ; [ DW_TAG_lexical_block ] [/home/timnor01/a64-trunk/build/simple.c]
+!18 = metadata !{i32 786443, metadata !29, metadata !14, i32 18, i32 16, i32 4} ; [ DW_TAG_lexical_block ] [/home/timnor01/a64-trunk/build/simple.c]
 !19 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 3200, i64 32, i32 0, i32 0, metadata !10, metadata !20, i32 0, i32 0} ; [ DW_TAG_array_type ] [line 0, size 3200, align 32, offset 0] [from int]
 !20 = metadata !{i32 786465, i64 0, i64 99}       ; [ DW_TAG_subrange_type ] [0, 99]
 !22 = metadata !{i32 19, i32 7, metadata !18, null}
diff --git a/test/DebugInfo/Inputs/dwarfdump-test-loc-list-32bit.elf.cpp b/test/DebugInfo/Inputs/dwarfdump-test-loc-list-32bit.elf.cpp
new file mode 100644
index 0000000..04a0b20
--- /dev/null
+++ b/test/DebugInfo/Inputs/dwarfdump-test-loc-list-32bit.elf.cpp
@@ -0,0 +1,13 @@
+// clang -c -g -o dwarfdump-test-loc-list-32bit.elf.o -m32 dwarfdump-test-loc-list-32bit.elf.cpp
+
+namespace pr14763 {
+struct foo {
+  foo(const foo&);
+};
+
+foo func(bool b, foo f, foo g) {
+  if (b)
+    return f;
+  return g;
+}
+}
diff --git a/test/DebugInfo/Inputs/dwarfdump-test-loc-list-32bit.elf.o b/test/DebugInfo/Inputs/dwarfdump-test-loc-list-32bit.elf.o
new file mode 100644
index 0000000..25d10b9
--- /dev/null
+++ b/test/DebugInfo/Inputs/dwarfdump-test-loc-list-32bit.elf.o
diff --git a/test/DebugInfo/Inputs/macho-universal b/test/DebugInfo/Inputs/macho-universal
new file mode 100755
index 0000000..a161441
--- /dev/null
+++ b/test/DebugInfo/Inputs/macho-universal
diff --git a/test/DebugInfo/Inputs/macho-universal.cc b/test/DebugInfo/Inputs/macho-universal.cc
new file mode 100644
index 0000000..9f34fdb
--- /dev/null
+++ b/test/DebugInfo/Inputs/macho-universal.cc
@@ -0,0 +1,10 @@
+// Built with Apple LLVM version 4.2 (clang-425.0.24) (based on LLVM 3.2svn)
+// clang++ -arch x86_64 -arch i386 macho-universal.cc
+
+int inc(int x) {
+  return x + 1;
+}
+
+int main(int argc, char *argv[]) {
+  return inc(argc);
+}
diff --git a/test/MC/Disassembler/MBlaze/lit.local.cfg b/test/DebugInfo/PowerPC/lit.local.cfg
index 3955b4e..112a1c3 100644
--- a/test/MC/Disassembler/MBlaze/lit.local.cfg
+++ b/test/DebugInfo/PowerPC/lit.local.cfg
@@ -1,6 +1,5 @@
-config.suffixes = ['.txt']
+config.suffixes = ['.ll', '.s']
 
 targets = set(config.root.targets_to_build.split())
-if not 'MBlaze' in targets:
+if not 'PowerPC' in targets:
     config.unsupported = True
-
diff --git a/test/DebugInfo/PowerPC/tls-fission.ll b/test/DebugInfo/PowerPC/tls-fission.ll
new file mode 100644
index 0000000..83a2cf3
--- /dev/null
+++ b/test/DebugInfo/PowerPC/tls-fission.ll
@@ -0,0 +1,31 @@
+; RUN: llc -split-dwarf=Enable -mtriple=powerpc64-unknown-linux-gnu -O0 -filetype=asm < %s | FileCheck %s
+
+; FIXME: add relocation and DWARF expression support to llvm-dwarfdump & use
+; that here instead of raw assembly printing
+
+; CHECK: debug_info.dwo
+; 3 bytes of data in this DW_FORM_block1 representation of the location of 'tls'
+; CHECK: .byte 3{{ *}}# DW_AT_location
+; DW_OP_const_index (0xfx == 252) to refer to the debug_addr table
+; CHECK-NEXT: .byte 252
+; an index of zero into the debug_addr table
+; CHECK-NEXT: .byte 0
+; DW_OP_GNU_push_tls_address
+; CHECK-NEXT: .byte 224
+; check that the expected TLS address description is the first thing in the debug_addr section
+; CHECK: debug_addr
+; CHECK-NEXT: .quad tls@dtprel+32768
+
+@tls = thread_local global i32 0, align 4
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7}
+
+!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.4 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !2, metadata !3, metadata !2, metadata !"tls.dwo"} ; [ DW_TAG_compile_unit ] [/tmp/tls.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{metadata !"tls.cpp", metadata !"/tmp"}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786484, i32 0, null, metadata !"tls", metadata !"tls", metadata !"", metadata !5, i32 1, metadata !6, i32 0, i32 1, i32* @tls, null} ; [ DW_TAG_variable ] [tls] [line 1] [def]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [/tmp/tls.cpp]
+!6 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!7 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}
diff --git a/test/DebugInfo/PowerPC/tls.ll b/test/DebugInfo/PowerPC/tls.ll
new file mode 100644
index 0000000..ae32a90
--- /dev/null
+++ b/test/DebugInfo/PowerPC/tls.ll
@@ -0,0 +1,28 @@
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -O0 -filetype=asm < %s | FileCheck %s
+
+; FIXME: add relocation and DWARF expression support to llvm-dwarfdump & use
+; that here instead of raw assembly printing
+
+; 10 bytes of data in this DW_FORM_block1 representation of the location of 'tls'
+; CHECK: .byte  10{{ *}}# DW_AT_location
+; DW_OP_const8u
+; CHECK: .byte  14
+; The debug relocation of the address of the tls variable
+; CHECK: .quad  tls@dtprel+32768
+; DW_OP_GNU_push_tls_address
+; CHECK: .byte  224
+
+@tls = thread_local global i32 7, align 4
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7}
+
+!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.4 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !2, metadata !3, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/tls.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{metadata !"tls.cpp", metadata !"/tmp"}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786484, i32 0, null, metadata !"tls", metadata !"tls", metadata !"", metadata !5, i32 1, metadata !6, i32 0, i32 1, i32* @tls, null} ; [ DW_TAG_variable ] [tls] [line 1] [def]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [/tmp/tls.cpp]
+!6 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!7 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}
+
diff --git a/test/DebugInfo/SystemZ/variable-loc.ll b/test/DebugInfo/SystemZ/variable-loc.ll
index e6f4ff9..139fae8 100644
--- a/test/DebugInfo/SystemZ/variable-loc.ll
+++ b/test/DebugInfo/SystemZ/variable-loc.ll
@@ -8,8 +8,7 @@
 ;
 ; CHECK: main:
 ; CHECK: aghi    %r15, -568
-; CHECK: la      [[MAIN_ARR:%r[0-9]+]], 164(%r11)
-; CHECK: lgr     %r2, [[MAIN_ARR]]
+; CHECK: la      %r2, 164(%r11)
 ; CHECK: brasl   %r14, populate_array@PLT
 ;
 ; Now check that the debugging information reflects this:
@@ -59,20 +58,20 @@ declare i32 @printf(i8*, ...)
 !0 = metadata !{i32 786449, metadata !29, i32 12, metadata !"clang version 3.2 ", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/timnor01/a64-trunk/build/simple.c] [DW_LANG_C99]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5, metadata !11, metadata !14}
-!5 = metadata !{i32 786478, metadata !6, metadata !"populate_array", metadata !"populate_array", metadata !"", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32*, i32)* @populate_array, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ] [line 4] [def] [populate_array]
+!5 = metadata !{i32 786478, metadata !29, metadata !6, metadata !"populate_array", metadata !"populate_array", metadata !"", i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32*, i32)* @populate_array, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ] [line 4] [def] [populate_array]
 !6 = metadata !{i32 786473, metadata !29} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !8 = metadata !{null, metadata !9, metadata !10}
 !9 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
 !10 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!11 = metadata !{i32 786478, metadata !6, metadata !"sum_array", metadata !"sum_array", metadata !"", metadata !6, i32 9, metadata !12, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32*, i32)* @sum_array, null, null, metadata !1, i32 9} ; [ DW_TAG_subprogram ] [line 9] [def] [sum_array]
+!11 = metadata !{i32 786478, metadata !29, metadata !6, metadata !"sum_array", metadata !"sum_array", metadata !"", i32 9, metadata !12, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32*, i32)* @sum_array, null, null, metadata !1, i32 9} ; [ DW_TAG_subprogram ] [line 9] [def] [sum_array]
 !12 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !13, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !13 = metadata !{metadata !10, metadata !9, metadata !10}
-!14 = metadata !{i32 786478, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 18, metadata !15, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, metadata !1, i32 18} ; [ DW_TAG_subprogram ] [line 18] [def] [main]
+!14 = metadata !{i32 786478, metadata !29, metadata !6, metadata !"main", metadata !"main", metadata !"", i32 18, metadata !15, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, metadata !1, i32 18} ; [ DW_TAG_subprogram ] [line 18] [def] [main]
 !15 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !16, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !16 = metadata !{metadata !10}
 !17 = metadata !{i32 786688, metadata !18, metadata !"main_arr", metadata !6, i32 19, metadata !19, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [main_arr] [line 19]
-!18 = metadata !{i32 786443, metadata !6, metadata !14, i32 18, i32 16, i32 4} ; [ DW_TAG_lexical_block ] [/home/timnor01/a64-trunk/build/simple.c]
+!18 = metadata !{i32 786443, metadata !29, metadata !14, i32 18, i32 16, i32 4} ; [ DW_TAG_lexical_block ] [/home/timnor01/a64-trunk/build/simple.c]
 !19 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 3200, i64 32, i32 0, i32 0, metadata !10, metadata !20, i32 0, i32 0} ; [ DW_TAG_array_type ] [line 0, size 3200, align 32, offset 0] [from int]
 !20 = metadata !{i32 786465, i64 0, i64 99}       ; [ DW_TAG_subrange_type ] [0, 99]
 !22 = metadata !{i32 19, i32 7, metadata !18, null}
diff --git a/test/DebugInfo/X86/2010-04-13-PubType.ll b/test/DebugInfo/X86/2010-04-13-PubType.ll
index 5bebeaa..0ec7f59 100644
--- a/test/DebugInfo/X86/2010-04-13-PubType.ll
+++ b/test/DebugInfo/X86/2010-04-13-PubType.ll
@@ -31,9 +31,9 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!3}
 
 !0 = metadata !{i32 786689, metadata !1, metadata !"x", metadata !2, i32 7, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 7, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 (%struct.X*, %struct.Y*)* @foo, null, null, null, i32 7} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786478, metadata !18, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", i32 7, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 (%struct.X*, %struct.Y*)* @foo, null, null, null, i32 7} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !18} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !17, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786449, metadata !18, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !19, metadata !19, metadata !17, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
 !4 = metadata !{i32 786453, metadata !18, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{metadata !6, metadata !7, metadata !9}
 !6 = metadata !{i32 786468, metadata !18, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
@@ -46,6 +46,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 !13 = metadata !{i32 7, i32 0, metadata !1, null}
 !14 = metadata !{i32 786689, metadata !1, metadata !"y", metadata !2, i32 7, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ]
 !15 = metadata !{i32 7, i32 0, metadata !16, null}
-!16 = metadata !{i32 786443, metadata !1, i32 7, i32 0} ; [ DW_TAG_lexical_block ]
+!16 = metadata !{i32 786443, metadata !18, metadata !1, i32 7, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !17 = metadata !{metadata !1}
 !18 = metadata !{metadata !"a.c", metadata !"/tmp/"}
+!19 = metadata !{i32 0}
diff --git a/test/DebugInfo/X86/2010-08-10-DbgConstant.ll b/test/DebugInfo/X86/2010-08-10-DbgConstant.ll
index 94eba6a..51a375a 100644
--- a/test/DebugInfo/X86/2010-08-10-DbgConstant.ll
+++ b/test/DebugInfo/X86/2010-08-10-DbgConstant.ll
@@ -13,16 +13,16 @@ declare void @bar(i32)
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void ()* @foo, null, null, null, i32 3} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !12, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void ()* @foo, null, null, null, i32 3} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !12} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, metadata !12, i32 12, metadata !"clang 2.8", i1 false, metadata !"", i32 0, null, null, metadata !10, metadata !11,  metadata !11, metadata !""} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 786449, metadata !12, i32 12, metadata !"clang 2.8", i1 false, metadata !"", i32 0, metadata !4, metadata !4, metadata !10, metadata !11,  metadata !11, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !12, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{null}
 !5 = metadata !{i32 786471, i32 0, metadata !1, metadata !"ro", metadata !"ro", metadata !"ro", metadata !1, i32 1, metadata !6, i1 true, i1 true, i32 201, null} ; [ DW_TAG_constant ]
-!6 = metadata !{i32 786470, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_const_type ]
-!7 = metadata !{i32 786468, metadata !1, metadata !"unsigned int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786470, metadata !12, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_const_type ]
+!7 = metadata !{i32 786468, metadata !12, metadata !1, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
 !8 = metadata !{i32 3, i32 14, metadata !9, null}
-!9 = metadata !{i32 786443, metadata !0, i32 3, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ]
+!9 = metadata !{i32 786443, metadata !12, metadata !0, i32 3, i32 12, i32 0} ; [ DW_TAG_lexical_block ]
 !10 = metadata !{metadata !0}
 !11 = metadata !{metadata !5}
 !12 = metadata !{metadata !"/tmp/l.c", metadata !"/Volumes/Lalgate/clean/D"}
diff --git a/test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll b/test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll
index 7b8d914..1c6778c 100644
--- a/test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll
+++ b/test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll
@@ -21,7 +21,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 !0 = metadata !{i32 786449, metadata !20, i32 12, metadata !"clang version 3.0 (trunk)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !12,  metadata !12, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 720942, metadata !6, metadata !6, metadata !"f", metadata !"f", metadata !"", i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @f, null, null, metadata !10} ; [ DW_TAG_subprogram ]
+!5 = metadata !{i32 720942, metadata !6, metadata !6, metadata !"f", metadata !"f", metadata !"", i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @f, null, null, metadata !10, i32 0} ; [ DW_TAG_subprogram ]
 !6 = metadata !{i32 720937, metadata !20} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{metadata !9}
diff --git a/test/DebugInfo/X86/2011-12-16-BadStructRef.ll b/test/DebugInfo/X86/2011-12-16-BadStructRef.ll
index 5464b87..405d9f5 100644
--- a/test/DebugInfo/X86/2011-12-16-BadStructRef.ll
+++ b/test/DebugInfo/X86/2011-12-16-BadStructRef.ll
@@ -88,7 +88,7 @@ entry:
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 720913, i32 4, metadata !6, metadata !"clang version 3.1 (trunk 146596)", i1 false, metadata !"", i32 0, metadata !1, metadata !3, metadata !27, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 720913, metadata !82, i32 4, metadata !"clang version 3.1 (trunk 146596)", i1 false, metadata !"", i32 0, metadata !1, metadata !3, metadata !27, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5, metadata !9}
 !5 = metadata !{i32 720898, metadata !82, null, metadata !"bar", i32 9, i64 128, i64 64, i32 0, i32 0, null, metadata !7, i32 0, null, null} ; [ DW_TAG_class_type ]
@@ -99,7 +99,7 @@ entry:
 !10 = metadata !{metadata !11, metadata !13}
 !11 = metadata !{i32 720909, metadata !82, metadata !9, metadata !"h", i32 5, i64 32, i64 32, i64 0, i32 0, metadata !12} ; [ DW_TAG_member ]
 !12 = metadata !{i32 720932, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!13 = metadata !{i32 720942, metadata !6, metadata !9, metadata !"baz", metadata !"baz", metadata !"", i32 6, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !17} ; [ DW_TAG_subprogram ]
+!13 = metadata !{i32 720942, metadata !82, metadata !9, metadata !"baz", metadata !"baz", metadata !"", i32 6, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !17, i32 0} ; [ DW_TAG_subprogram ]
 !14 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !15, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !15 = metadata !{null, metadata !16, metadata !12}
 !16 = metadata !{i32 720911, i32 0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !9} ; [ DW_TAG_pointer_type ]
@@ -107,14 +107,14 @@ entry:
 !18 = metadata !{i32 720932}                      ; [ DW_TAG_base_type ]
 !19 = metadata !{i32 720909, metadata !82, metadata !5, metadata !"b_ref", i32 12, i64 64, i64 64, i64 64, i32 0, metadata !20} ; [ DW_TAG_member ]
 !20 = metadata !{i32 720912, null, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !9} ; [ DW_TAG_reference_type ]
-!21 = metadata !{i32 720942, metadata !6, metadata !5, metadata !"bar", metadata !"bar", metadata !"", i32 13, metadata !22, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !25} ; [ DW_TAG_subprogram ]
+!21 = metadata !{i32 720942, metadata !82, metadata !5, metadata !"bar", metadata !"bar", metadata !"", i32 13, metadata !22, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !25, i32 0} ; [ DW_TAG_subprogram ]
 !22 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !23, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !23 = metadata !{null, metadata !24, metadata !12}
 !24 = metadata !{i32 720911, i32 0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !5} ; [ DW_TAG_pointer_type ]
 !25 = metadata !{metadata !26}
 !26 = metadata !{i32 720932}                      ; [ DW_TAG_base_type ]
 !27 = metadata !{metadata !29, metadata !37, metadata !40, metadata !43, metadata !46}
-!29 = metadata !{i32 720942, metadata !6, metadata !6, metadata !"main", metadata !"main", metadata !"", i32 17, metadata !30, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32, i8**)* @main, null, null, metadata !35} ; [ DW_TAG_subprogram ]
+!29 = metadata !{i32 720942, metadata !82, metadata !6, metadata !"main", metadata !"main", metadata !"", i32 17, metadata !30, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32, i8**)* @main, null, null, metadata !35, i32 0} ; [ DW_TAG_subprogram ]
 !30 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !31, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !31 = metadata !{metadata !12, metadata !12, metadata !32}
 !32 = metadata !{i32 720911, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !33} ; [ DW_TAG_pointer_type ]
@@ -122,16 +122,16 @@ entry:
 !34 = metadata !{i32 720932, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !35 = metadata !{metadata !36}
 !36 = metadata !{i32 720932}                      ; [ DW_TAG_base_type ]
-!37 = metadata !{i32 720942, metadata !6, null, metadata !"bar", metadata !"bar", metadata !"_ZN3barC1Ei", i32 13, metadata !22, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%struct.bar*, i32)* @_ZN3barC1Ei, null, metadata !21, metadata !38} ; [ DW_TAG_subprogram ]
+!37 = metadata !{i32 720942, metadata !82, null, metadata !"bar", metadata !"bar", metadata !"_ZN3barC1Ei", i32 13, metadata !22, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%struct.bar*, i32)* @_ZN3barC1Ei, null, metadata !21, metadata !38, i32 0} ; [ DW_TAG_subprogram ]
 !38 = metadata !{metadata !39}
 !39 = metadata !{i32 720932}                      ; [ DW_TAG_base_type ]
-!40 = metadata !{i32 720942, metadata !6, null, metadata !"bar", metadata !"bar", metadata !"_ZN3barC2Ei", i32 13, metadata !22, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%struct.bar*, i32)* @_ZN3barC2Ei, null, metadata !21, metadata !41} ; [ DW_TAG_subprogram ]
+!40 = metadata !{i32 720942, metadata !82, null, metadata !"bar", metadata !"bar", metadata !"_ZN3barC2Ei", i32 13, metadata !22, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%struct.bar*, i32)* @_ZN3barC2Ei, null, metadata !21, metadata !41, i32 0} ; [ DW_TAG_subprogram ]
 !41 = metadata !{metadata !42}
 !42 = metadata !{i32 720932}                      ; [ DW_TAG_base_type ]
-!43 = metadata !{i32 720942, metadata !6, null, metadata !"baz", metadata !"baz", metadata !"_ZN3bazC1Ei", i32 6, metadata !14, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%struct.baz*, i32)* @_ZN3bazC1Ei, null, metadata !13, metadata !44} ; [ DW_TAG_subprogram ]
+!43 = metadata !{i32 720942, metadata !82, null, metadata !"baz", metadata !"baz", metadata !"_ZN3bazC1Ei", i32 6, metadata !14, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%struct.baz*, i32)* @_ZN3bazC1Ei, null, metadata !13, metadata !44, i32 0} ; [ DW_TAG_subprogram ]
 !44 = metadata !{metadata !45}
 !45 = metadata !{i32 720932}                      ; [ DW_TAG_base_type ]
-!46 = metadata !{i32 720942, metadata !6, null, metadata !"baz", metadata !"baz", metadata !"_ZN3bazC2Ei", i32 6, metadata !14, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%struct.baz*, i32)* @_ZN3bazC2Ei, null, metadata !13, metadata !47} ; [ DW_TAG_subprogram ]
+!46 = metadata !{i32 720942, metadata !82, null, metadata !"baz", metadata !"baz", metadata !"_ZN3bazC2Ei", i32 6, metadata !14, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%struct.baz*, i32)* @_ZN3bazC2Ei, null, metadata !13, metadata !47, i32 0} ; [ DW_TAG_subprogram ]
 !47 = metadata !{metadata !48}
 !48 = metadata !{i32 720932}                      ; [ DW_TAG_base_type ]
 !49 = metadata !{i32 721153, metadata !29, metadata !"argc", metadata !6, i32 16777232, metadata !12, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
@@ -139,7 +139,7 @@ entry:
 !51 = metadata !{i32 721153, metadata !29, metadata !"argv", metadata !6, i32 33554448, metadata !32, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
 !52 = metadata !{i32 16, i32 27, metadata !29, null}
 !53 = metadata !{i32 721152, metadata !54, metadata !"myBar", metadata !6, i32 18, metadata !5, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
-!54 = metadata !{i32 720907, metadata !29, i32 17, i32 1, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
+!54 = metadata !{i32 720907, metadata !82, metadata !29, i32 17, i32 1, i32 0} ; [ DW_TAG_lexical_block ]
 !55 = metadata !{i32 18, i32 9, metadata !54, null}
 !56 = metadata !{i32 18, i32 17, metadata !54, null}
 !57 = metadata !{i32 19, i32 5, metadata !54, null}
@@ -154,7 +154,7 @@ entry:
 !66 = metadata !{i32 13, i32 13, metadata !40, null}
 !67 = metadata !{i32 13, i32 33, metadata !40, null}
 !68 = metadata !{i32 13, i32 34, metadata !69, null}
-!69 = metadata !{i32 720907, metadata !40, i32 13, i32 33, metadata !6, i32 1} ; [ DW_TAG_lexical_block ]
+!69 = metadata !{i32 720907, metadata !82, metadata !40, i32 13, i32 33, i32 1} ; [ DW_TAG_lexical_block ]
 !70 = metadata !{i32 721153, metadata !43, metadata !"this", metadata !6, i32 16777222, metadata !16, i32 64, i32 0} ; [ DW_TAG_arg_variable ]
 !71 = metadata !{i32 6, i32 5, metadata !43, null}
 !72 = metadata !{i32 721153, metadata !43, metadata !"a", metadata !6, i32 33554438, metadata !12, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
@@ -166,5 +166,5 @@ entry:
 !78 = metadata !{i32 6, i32 13, metadata !46, null}
 !79 = metadata !{i32 6, i32 23, metadata !46, null}
 !80 = metadata !{i32 6, i32 24, metadata !81, null}
-!81 = metadata !{i32 720907, metadata !46, i32 6, i32 23, metadata !6, i32 2} ; [ DW_TAG_lexical_block ]
+!81 = metadata !{i32 720907, metadata !82, metadata !46, i32 6, i32 23, i32 2} ; [ DW_TAG_lexical_block ]
 !82 = metadata !{metadata !"main.cpp", metadata !"/Users/echristo/tmp/bad-struct-ref"}
diff --git a/test/DebugInfo/X86/DW_AT_byte_size.ll b/test/DebugInfo/X86/DW_AT_byte_size.ll
index dcacba1..ef55839 100644
--- a/test/DebugInfo/X86/DW_AT_byte_size.ll
+++ b/test/DebugInfo/X86/DW_AT_byte_size.ll
@@ -24,10 +24,10 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.1 (trunk 150996)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !20, i32 4, metadata !"clang version 3.1 (trunk 150996)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, metadata !6, metadata !"foo", metadata !"foo", metadata !"_Z3fooP1A", metadata !6, i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (%struct.A*)* @_Z3fooP1A, null, null, metadata !14, i32 3} ; [ DW_TAG_subprogram ]
+!5 = metadata !{i32 786478, metadata !20, metadata !6, metadata !"foo", metadata !"foo", metadata !"_Z3fooP1A", i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (%struct.A*)* @_Z3fooP1A, null, null, metadata !14, i32 3} ; [ DW_TAG_subprogram ]
 !6 = metadata !{i32 786473, metadata !20} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{metadata !9, metadata !10}
@@ -41,5 +41,5 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 !16 = metadata !{i32 786689, metadata !5, metadata !"a", metadata !6, i32 16777219, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
 !17 = metadata !{i32 3, i32 13, metadata !5, null}
 !18 = metadata !{i32 4, i32 3, metadata !19, null}
-!19 = metadata !{i32 786443, metadata !6, metadata !5, i32 3, i32 16, i32 0} ; [ DW_TAG_lexical_block ]
+!19 = metadata !{i32 786443, metadata !20, metadata !5, i32 3, i32 16, i32 0} ; [ DW_TAG_lexical_block ]
 !20 = metadata !{metadata !"foo.cpp", metadata !"/Users/echristo"}
diff --git a/test/DebugInfo/X86/DW_AT_location-reference.ll b/test/DebugInfo/X86/DW_AT_location-reference.ll
index 6f1aa41..f0f4f48 100644
--- a/test/DebugInfo/X86/DW_AT_location-reference.ll
+++ b/test/DebugInfo/X86/DW_AT_location-reference.ll
@@ -87,14 +87,14 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"f", metadata !"f", metadata !"", metadata !1, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void ()* @f, null, null, metadata !22, i32 4} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !23, metadata !1, metadata !"f", metadata !"f", metadata !"", i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void ()* @f, null, null, metadata !22, i32 4} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !23} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 3.0 (trunk)", i1 true, metadata !"", i32 0, null, null, metadata !21, null,  null, null} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 786449, metadata !23, i32 12, metadata !"clang version 3.0 (trunk)", i1 true, metadata !"", i32 0, metadata !4, metadata !4, metadata !21, null,  null, null} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !23, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{null}
 !5 = metadata !{i32 786688, metadata !6, metadata !"x", metadata !1, i32 5, metadata !7, i32 0, null} ; [ DW_TAG_auto_variable ]
-!6 = metadata !{i32 786443, metadata !1, metadata !0, i32 4, i32 14, i32 0} ; [ DW_TAG_lexical_block ]
-!7 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786443, metadata !23, metadata !0, i32 4, i32 14, i32 0} ; [ DW_TAG_lexical_block ]
+!7 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !8 = metadata !{i32 6, i32 3, metadata !6, null}
 !12 = metadata !{i32 1}
 !13 = metadata !{i32 7, i32 3, metadata !6, null}
diff --git a/test/DebugInfo/X86/aligned_stack_var.ll b/test/DebugInfo/X86/aligned_stack_var.ll
index b99de3c..5b23f64 100644
--- a/test/DebugInfo/X86/aligned_stack_var.ll
+++ b/test/DebugInfo/X86/aligned_stack_var.ll
@@ -26,15 +26,16 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.2 (trunk 155696:155697) (llvm/trunk 155696)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !14, i32 4, metadata !"clang version 3.2 (trunk 155696:155697) (llvm/trunk 155696)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, metadata !6, metadata !"run", metadata !"run", metadata !"_Z3runv", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @_Z3runv, null, null, metadata !1, i32 1} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 786473, metadata !"test.cc", metadata !"/home/samsonov/debuginfo", null} ; [ DW_TAG_file_type ]
+!5 = metadata !{i32 786478, metadata !14, metadata !6, metadata !"run", metadata !"run", metadata !"_Z3runv", i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @_Z3runv, null, null, metadata !1, i32 1} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 786473, metadata !14} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{null}
 !9 = metadata !{i32 786688, metadata !10, metadata !"x", metadata !6, i32 2, metadata !11, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
-!10 = metadata !{i32 786443, metadata !6, metadata !5, i32 1, i32 12, i32 0} ; [ DW_TAG_lexical_block ]
-!11 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!10 = metadata !{i32 786443, metadata !14, metadata !5, i32 1, i32 12, i32 0} ; [ DW_TAG_lexical_block ]
+!11 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !12 = metadata !{i32 2, i32 7, metadata !10, null}
 !13 = metadata !{i32 3, i32 1, metadata !10, null}
+!14 = metadata !{metadata !"test.cc", metadata !"/home/samsonov/debuginfo"}
diff --git a/test/DebugInfo/X86/arguments.ll b/test/DebugInfo/X86/arguments.ll
new file mode 100644
index 0000000..6f99f87
--- /dev/null
+++ b/test/DebugInfo/X86/arguments.ll
@@ -0,0 +1,71 @@
+; REQUIRES: object-emission
+
+; RUN: llc -mtriple=x86_64-unknown-unknown -O0 -filetype=obj < %s > %t
+; RUN: llvm-dwarfdump %t | FileCheck %s
+
+; IR generated from clang -g with the following source:
+; struct foo {
+;   foo(const foo&);
+;   int i;
+; };
+;
+; void func(foo f, foo g) {
+;   f.i++;
+; }
+
+; CHECK: debug_info contents
+; CHECK: DW_TAG_subprogram
+; CHECK-NEXT: DW_AT_MIPS_linkage_name{{.*}}"_Z4func3fooS_"
+; CHECK-NOT: NULL
+; CHECK: DW_TAG_formal_parameter
+; CHECK-NEXT: DW_AT_name{{.*}}"f"
+; CHECK-NOT: NULL
+; CHECK: DW_TAG_formal_parameter
+; CHECK-NEXT: DW_AT_name{{.*}}"g"
+
+%struct.foo = type { i32 }
+
+; Function Attrs: nounwind uwtable
+define void @_Z4func3fooS_(%struct.foo* %f, %struct.foo* %g) #0 {
+entry:
+  call void @llvm.dbg.declare(metadata !{%struct.foo* %f}, metadata !19), !dbg !20
+  call void @llvm.dbg.declare(metadata !{%struct.foo* %g}, metadata !21), !dbg !20
+  %i = getelementptr inbounds %struct.foo* %f, i32 0, i32 0, !dbg !22
+  %0 = load i32* %i, align 4, !dbg !22
+  %inc = add nsw i32 %0, 1, !dbg !22
+  store i32 %inc, i32* %i, align 4, !dbg !22
+  ret void, !dbg !23
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata) #1
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+
+!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.4 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/blaikie/dev/scratch/scratch.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{metadata !"scratch.cpp", metadata !"/usr/local/google/home/blaikie/dev/scratch"}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"func", metadata !"func", metadata !"_Z4func3fooS_", i32 6, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%struct.foo*, %struct.foo*)* @_Z4func3fooS_, null, null, metadata !2, i32 6} ; [ DW_TAG_subprogram ] [line 6] [def] [func]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [/usr/local/google/home/blaikie/dev/scratch/scratch.cpp]
+!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{null, metadata !8, metadata !8}
+!8 = metadata !{i32 786451, metadata !1, null, metadata !"foo", i32 1, i64 32, i64 32, i32 0, i32 0, null, metadata !9, i32 0, null, null} ; [ DW_TAG_structure_type ] [foo] [line 1, size 32, align 32, offset 0] [from ]
+!9 = metadata !{metadata !10, metadata !12}
+!10 = metadata !{i32 786445, metadata !1, metadata !8, metadata !"i", i32 3, i64 32, i64 32, i64 0, i32 0, metadata !11} ; [ DW_TAG_member ] [i] [line 3, size 32, align 32, offset 0] [from int]
+!11 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!12 = metadata !{i32 786478, metadata !1, metadata !8, metadata !"foo", metadata !"foo", metadata !"", i32 2, metadata !13, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !18, i32 2} ; [ DW_TAG_subprogram ] [line 2] [foo]
+!13 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !14, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!14 = metadata !{null, metadata !15, metadata !16}
+!15 = metadata !{i32 786447, i32 0, i32 0, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !8} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from foo]
+!16 = metadata !{i32 786448, null, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !17} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from ]
+!17 = metadata !{i32 786470, null, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, metadata !8} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from foo]
+!18 = metadata !{i32 786468}
+!19 = metadata !{i32 786689, metadata !4, metadata !"f", metadata !5, i32 16777222, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [f] [line 6]
+!20 = metadata !{i32 6, i32 0, metadata !4, null}
+!21 = metadata !{i32 786689, metadata !4, metadata !"g", metadata !5, i32 33554438, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [g] [line 6]
+!22 = metadata !{i32 7, i32 0, metadata !4, null}
+!23 = metadata !{i32 8, i32 0, metadata !4, null} ; [ DW_TAG_imported_declaration ]
diff --git a/test/DebugInfo/X86/coff_relative_names.ll b/test/DebugInfo/X86/coff_relative_names.ll
new file mode 100644
index 0000000..8e46e0b
--- /dev/null
+++ b/test/DebugInfo/X86/coff_relative_names.ll
@@ -0,0 +1,40 @@
+; RUN: llc -mtriple=i686-w64-mingw32 -filetype=asm -O0 < %s | FileCheck %s

+

+; CHECK:  	.secrel32 Linfo_string0

+; CHECK:  	.secrel32 Linfo_string1

+;

+; generated from:

+; clang -g -S -emit-llvm test.c -o test.ll

+; int main()

+; {

+; 	return 0;

+; }

+

+; ModuleID = 'test.c'

+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"

+target triple = "i686-pc-win32"

+

+; Function Attrs: nounwind

+define i32 @main() #0 {

+entry:

+  %retval = alloca i32, align 4

+  store i32 0, i32* %retval

+  ret i32 0, !dbg !10

+}

+

+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }

+

+!llvm.dbg.cu = !{!0}

+!llvm.module.flags = !{!9}

+

+!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.4 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [C:\Projects/test.c] [DW_LANG_C99]

+!1 = metadata !{metadata !"test.c", metadata !"C:\5CProjects"}

+!2 = metadata !{i32 0}

+!3 = metadata !{metadata !4}

+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"main", metadata !"main", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main, null, null, metadata !2, i32 2} ; [ DW_TAG_subprogram ] [line 1] [def] [scope 2] [main]

+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [C:\Projects/test.c]

+!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]

+!7 = metadata !{metadata !8}

+!8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]

+!9 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}

+!10 = metadata !{i32 3, i32 0, metadata !4, null}

diff --git a/test/DebugInfo/X86/dbg-value-inlined-parameter.ll b/test/DebugInfo/X86/dbg-value-inlined-parameter.ll
index da6423f..de9f672 100644
--- a/test/DebugInfo/X86/dbg-value-inlined-parameter.ll
+++ b/test/DebugInfo/X86/dbg-value-inlined-parameter.ll
@@ -3,14 +3,15 @@
 ; RUN: llc -mtriple=x86_64-apple-darwin -regalloc=basic %s -filetype=obj -o %t
 ; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s
 
-;CHECK: DW_TAG_inlined_subroutine [12]
+;CHECK: DW_TAG_inlined_subroutine
 ;CHECK-NEXT: DW_AT_abstract_origin
 ;CHECK-NEXT: DW_AT_low_pc
 ;CHECK-NEXT: DW_AT_high_pc
 ;CHECK-NEXT: DW_AT_call_file
 ;CHECK-NEXT: DW_AT_call_line
 
-;CHECK: DW_TAG_formal_parameter [9]
+;CHECK: DW_TAG_formal_parameter
+;CHECK: DW_TAG_formal_parameter
 ;CHECK-NEXT: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000055] = "sp")
 
 %struct.S1 = type { float*, i32 }
@@ -49,11 +50,11 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !0 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"foo", metadata !"foo", metadata !"", i32 8, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (%struct.S1*, i32)* @foo, null, null, metadata !41, i32 8} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !42} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, metadata !42, i32 12, metadata !"clang version 2.9 (trunk 125693)", i1 true, metadata !"", i32 0, null, null, metadata !39, metadata !40,  metadata !40, null} ; [ DW_TAG_compile_unit ]
+!2 = metadata !{i32 786449, metadata !42, i32 12, metadata !"clang version 2.9 (trunk 125693)", i1 true, metadata !"", i32 0, metadata !8, metadata !8, metadata !39, metadata !40,  metadata !40, null} ; [ DW_TAG_compile_unit ]
 !3 = metadata !{i32 786453, metadata !42, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
 !5 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"foobar", metadata !"foobar", metadata !"", i32 15, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, void ()* @foobar} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"foobar", metadata !"foobar", metadata !"", i32 15, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, void ()* @foobar, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !7 = metadata !{i32 786453, metadata !42, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{null}
 !9 = metadata !{i32 786689, metadata !0, metadata !"sp", metadata !1, i32 7, metadata !10, i32 0, metadata !32} ; [ DW_TAG_arg_variable ]
diff --git a/test/CodeGen/X86/dbg-value-range.ll b/test/DebugInfo/X86/dbg-value-range.ll
index b068bbbe..a784cc1 100644
--- a/test/CodeGen/X86/dbg-value-range.ll
+++ b/test/DebugInfo/X86/dbg-value-range.ll
@@ -19,17 +19,17 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"bar", metadata !"bar", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (%struct.a*)* @bar, null, null, metadata !21, i32 0} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !22, metadata !1, metadata !"bar", metadata !"bar", metadata !"", i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (%struct.a*)* @bar, null, null, metadata !21, i32 0} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !22} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, metadata !22, i32 12, metadata !"clang version 2.9 (trunk 122997)", i1 true, metadata !"", i32 0, null, null, metadata !20, null,  null, null} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 786449, metadata !22, i32 12, metadata !"clang version 2.9 (trunk 122997)", i1 true, metadata !"", i32 0, metadata !23, metadata !23, metadata !20, null,  null, null} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !22, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !6 = metadata !{i32 786689, metadata !0, metadata !"b", metadata !1, i32 5, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ]
-!7 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ]
-!8 = metadata !{i32 786451, metadata !2, metadata !"a", metadata !1, i32 1, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !9, i32 0, i32 0} ; [ DW_TAG_structure_type ]
+!7 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ]
+!8 = metadata !{i32 786451, metadata !22, metadata !2, metadata !"a", i32 1, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !9, i32 0, i32 0} ; [ DW_TAG_structure_type ]
 !9 = metadata !{metadata !10}
-!10 = metadata !{i32 786445, metadata !1, metadata !"c", metadata !1, i32 2, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ]
+!10 = metadata !{i32 786445, metadata !22, metadata !1, metadata !"c", i32 2, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ]
 !11 = metadata !{i32 786688, metadata !12, metadata !"x", metadata !1, i32 6, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
 !12 = metadata !{i32 786443, metadata !22, metadata !0, i32 5, i32 22, i32 0} ; [ DW_TAG_lexical_block ]
 !13 = metadata !{i32 5, i32 19, metadata !0, null}
@@ -39,8 +39,9 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !20 = metadata !{metadata !0}
 !21 = metadata !{metadata !6, metadata !11}
 !22 = metadata !{metadata !"bar.c", metadata !"/private/tmp"}
+!23 = metadata !{i32 0}
 
-; Check that variable bar:b value range is appropriately trucated in debug info.
+; Check that variable bar:b value range is appropriately truncated in debug info.
 ; The variable is in %rdi which is clobbered by 'movl %ebx, %edi'
 ; Here Ltmp7 is the end of the location range.
 
@@ -54,7 +55,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 ;CHECK-NEXT: Lset{{.*}} = Ltmp{{.*}}-Ltmp{{.*}}
 ;CHECK-NEXT:    .short  Lset
 ;CHECK-NEXT: Ltmp
-;CHECK-NEXT:	.byte	85
+;CHECK-NEXT:	.byte	85 ## DW_OP_reg
 ;CHECK-NEXT: Ltmp
 ;CHECK-NEXT:	.quad	0
 ;CHECK-NEXT:	.quad	0
diff --git a/test/DebugInfo/X86/dbg_value_direct.ll b/test/DebugInfo/X86/dbg_value_direct.ll
new file mode 100644
index 0000000..9a40d59
--- /dev/null
+++ b/test/DebugInfo/X86/dbg_value_direct.ll
@@ -0,0 +1,176 @@
+; RUN: llc -filetype=obj -O0 < %s
+; Test that we handle DBG_VALUEs in a register without crashing.
+;
+; Generated from clang with -fsanitize=address:
+; struct A {
+;   A();
+;   A(const A&);
+; };
+;
+; A func(int) {
+;   A a;
+;   return a;
+; }
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.A = type { i8 }
+
+@__asan_mapping_offset = linkonce_odr constant i64 2147450880
+@__asan_mapping_scale = linkonce_odr constant i64 3
+@llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 1, void ()* @asan.module_ctor }]
+@__asan_gen_ = private unnamed_addr constant [16 x i8] c"1 32 4 5 .addr \00", align 1
+
+; Function Attrs: sanitize_address uwtable
+define void @_Z4funci(%struct.A* noalias sret %agg.result, i32) #0 "stack-protector-buffer-size"="1" {
+entry:
+  %MyAlloca = alloca [96 x i8], align 32
+  %1 = ptrtoint [96 x i8]* %MyAlloca to i64
+  %2 = add i64 %1, 32
+  %3 = inttoptr i64 %2 to i32*
+  %4 = inttoptr i64 %1 to i64*
+  store i64 1102416563, i64* %4
+  %5 = add i64 %1, 8
+  %6 = inttoptr i64 %5 to i64*
+  store i64 ptrtoint ([16 x i8]* @__asan_gen_ to i64), i64* %6
+  %7 = add i64 %1, 16
+  %8 = inttoptr i64 %7 to i64*
+  store i64 ptrtoint (void (%struct.A*, i32)* @_Z4funci to i64), i64* %8
+  %9 = lshr i64 %1, 3
+  %10 = add i64 %9, 2147450880
+  %11 = inttoptr i64 %10 to i32*
+  store i32 -235802127, i32* %11
+  %12 = add i64 %10, 4
+  %13 = inttoptr i64 %12 to i32*
+  store i32 -185273340, i32* %13
+  %14 = add i64 %10, 8
+  %15 = inttoptr i64 %14 to i32*
+  store i32 -202116109, i32* %15
+  %16 = ptrtoint i32* %3 to i64
+  %17 = lshr i64 %16, 3
+  %18 = add i64 %17, 2147450880
+  %19 = inttoptr i64 %18 to i8*
+  %20 = load i8* %19
+  %21 = icmp ne i8 %20, 0
+  call void @llvm.dbg.declare(metadata !{i32* %3}, metadata !23)
+  br i1 %21, label %22, label %28
+
+; <label>:22                                      ; preds = %entry
+  %23 = and i64 %16, 7
+  %24 = add i64 %23, 3
+  %25 = trunc i64 %24 to i8
+  %26 = icmp sge i8 %25, %20
+  br i1 %26, label %27, label %28
+
+; <label>:27                                      ; preds = %22
+  call void @__asan_report_store4(i64 %16)
+  call void asm sideeffect "", ""()
+  unreachable
+
+; <label>:28                                      ; preds = %22, %entry
+  store i32 %0, i32* %3, align 4
+  call void @llvm.dbg.declare(metadata !{%struct.A* %agg.result}, metadata !24), !dbg !25
+  call void @_ZN1AC1Ev(%struct.A* %agg.result), !dbg !25
+  store i64 1172321806, i64* %4, !dbg !26
+  %29 = inttoptr i64 %10 to i32*, !dbg !26
+  store i32 0, i32* %29, !dbg !26
+  %30 = add i64 %10, 4, !dbg !26
+  %31 = inttoptr i64 %30 to i32*, !dbg !26
+  store i32 0, i32* %31, !dbg !26
+  %32 = add i64 %10, 8, !dbg !26
+  %33 = inttoptr i64 %32 to i32*, !dbg !26
+  store i32 0, i32* %33, !dbg !26
+  ret void, !dbg !26
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata) #1
+
+declare void @_ZN1AC1Ev(%struct.A*) #2
+
+define internal void @asan.module_ctor()  "stack-protector-buffer-size"="1" {
+  call void @__asan_init_v3()
+  %1 = load volatile i64* @__asan_mapping_offset
+  %2 = load volatile i64* @__asan_mapping_scale
+  ret void
+}
+
+declare void @__asan_init_v3()
+
+declare void @__asan_report_load1(i64)
+
+declare void @__asan_report_load2(i64)
+
+declare void @__asan_report_load4(i64)
+
+declare void @__asan_report_load8(i64)
+
+declare void @__asan_report_load16(i64)
+
+declare void @__asan_report_store1(i64)
+
+declare void @__asan_report_store2(i64)
+
+declare void @__asan_report_store4(i64)
+
+declare void @__asan_report_store8(i64)
+
+declare void @__asan_report_store16(i64)
+
+declare void @__asan_report_load_n(i64, i64)
+
+declare void @__asan_report_store_n(i64, i64)
+
+declare void @__asan_handle_no_return()
+
+declare i64 @__asan_stack_malloc(i64, i64)
+
+declare void @__asan_stack_free(i64, i64, i64)
+
+declare void @__asan_poison_stack_memory(i64, i64)
+
+declare void @__asan_unpoison_stack_memory(i64, i64)
+
+declare void @__asan_before_dynamic_init(i64)
+
+declare void @__asan_after_dynamic_init()
+
+declare void @__asan_register_globals(i64, i64)
+
+declare void @__asan_unregister_globals(i64, i64)
+
+attributes #0 = { sanitize_address uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "ssp-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "ssp-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!22}
+
+!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.4 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/crash.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{metadata !"crash.cpp", metadata !"/tmp"}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"func", metadata !"func", metadata !"_Z4funci", i32 6, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%struct.A*, i32)* @_Z4funci, null, null, metadata !2, i32 6} ; [ DW_TAG_subprogram ] [line 6] [def] [func]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [/tmp/crash.cpp]
+!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{metadata !8, metadata !21}
+!8 = metadata !{i32 786451, metadata !1, null, metadata !"A", i32 1, i64 8, i64 8, i32 0, i32 0, null, metadata !9, i32 0, null, null} ; [ DW_TAG_structure_type ] [A] [line 1, size 8, align 8, offset 0] [def] [from ]
+!9 = metadata !{metadata !10, metadata !15}
+!10 = metadata !{i32 786478, metadata !1, metadata !8, metadata !"A", metadata !"A", metadata !"", i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !14, i32 2} ; [ DW_TAG_subprogram ] [line 2] [A]
+!11 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = metadata !{null, metadata !13}
+!13 = metadata !{i32 786447, i32 0, i32 0, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !8} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from A]
+!14 = metadata !{i32 786468}
+!15 = metadata !{i32 786478, metadata !1, metadata !8, metadata !"A", metadata !"A", metadata !"", i32 3, metadata !16, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !20, i32 3} ; [ DW_TAG_subprogram ] [line 3] [A]
+!16 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !17, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!17 = metadata !{null, metadata !13, metadata !18}
+!18 = metadata !{i32 786448, null, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !19} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from ]
+!19 = metadata !{i32 786470, null, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, metadata !8} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from A]
+!20 = metadata !{i32 786468}
+!21 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!22 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}
+!23 = metadata !{i32 786689, metadata !4, metadata !"", metadata !5, i32 16777222, metadata !21, i32 0, i32 0, i64 2} ; [ DW_TAG_arg_variable ] [line 6]
+!24 = metadata !{i32 786688, metadata !4, metadata !"a", metadata !5, i32 7, metadata !8, i32 8192, i32 0} ; [ DW_TAG_auto_variable ] [a] [line 7]
+!25 = metadata !{i32 7, i32 0, metadata !4, null}
+!26 = metadata !{i32 8, i32 0, metadata !4, null} ; [ DW_TAG_imported_declaration ]
diff --git a/test/DebugInfo/X86/debug-info-block-captured-self.ll b/test/DebugInfo/X86/debug-info-block-captured-self.ll
index 7e318f6..3d36350 100644
--- a/test/DebugInfo/X86/debug-info-block-captured-self.ll
+++ b/test/DebugInfo/X86/debug-info-block-captured-self.ll
@@ -77,7 +77,7 @@ define internal void @"__24-[Main initWithContext:]_block_invoke_2"(i8* %.block_
 }
 
 !llvm.dbg.cu = !{!0}
-!0 = metadata !{i32 786449, i32 16, metadata !1, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 2, metadata !2, metadata !4, metadata !23, metadata !15,  metadata !15, metadata !""} ; [ DW_TAG_compile_unit ] [llvm/tools/clang/test/CodeGenObjC/debug-info-block-captured-self.m] [DW_LANG_ObjC]
+!0 = metadata !{i32 786449, metadata !107, i32 16, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 2, metadata !2, metadata !4, metadata !23, metadata !15,  metadata !15, metadata !""} ; [ DW_TAG_compile_unit ] [llvm/tools/clang/test/CodeGenObjC/debug-info-block-captured-self.m] [DW_LANG_ObjC]
 !1 = metadata !{i32 786473, metadata !107} ; [ DW_TAG_file_type ]
 !2 = metadata !{metadata !3}
 !3 = metadata !{i32 786436, metadata !107, null, metadata !"", i32 20, i64 32, i64 32, i32 0, i32 0, null, metadata !4, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] [line 20, size 32, align 32, offset 0] [from ]
diff --git a/test/DebugInfo/X86/debug-info-static-member.ll b/test/DebugInfo/X86/debug-info-static-member.ll
index 33485b6..02b8ae0 100644
--- a/test/DebugInfo/X86/debug-info-static-member.ll
+++ b/test/DebugInfo/X86/debug-info-static-member.ll
@@ -58,10 +58,10 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.3 (trunk 171914)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !10,  metadata !10, metadata !""} ; [ DW_TAG_compile_unit ] [/home/probinson/projects/upstream/static-member/test/debug-info-static-member.cpp] [DW_LANG_C_plus_plus]
+!0 = metadata !{i32 786449, metadata !33, i32 4, metadata !"clang version 3.3 (trunk 171914)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !10,  metadata !10, metadata !""} ; [ DW_TAG_compile_unit ] [/home/probinson/projects/upstream/static-member/test/debug-info-static-member.cpp] [DW_LANG_C_plus_plus]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 18, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, metadata !1, i32 23} ; [ DW_TAG_subprogram ] [line 18] [def] [scope 23] [main]
+!5 = metadata !{i32 786478, metadata !33, metadata !6, metadata !"main", metadata !"main", metadata !"", i32 18, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, metadata !1, i32 23} ; [ DW_TAG_subprogram ] [line 18] [def] [scope 23] [main]
 !6 = metadata !{i32 786473, metadata !33} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !8 = metadata !{metadata !9}
diff --git a/test/DebugInfo/X86/debug_frame.ll b/test/DebugInfo/X86/debug_frame.ll
index 0e93427..622e5d3 100644
--- a/test/DebugInfo/X86/debug_frame.ll
+++ b/test/DebugInfo/X86/debug_frame.ll
@@ -12,8 +12,9 @@ entry:
 !llvm.dbg.cu = !{!2}
 !5 = metadata !{metadata !0}
 
-!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"f", metadata !"f", metadata !"", metadata !1, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void ()* @f, null, null, null, i32 1} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 786473, metadata !"/home/espindola/llvm/test.c", metadata !"/home/espindola/llvm/build", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, i32 0, i32 12, metadata !"/home/espindola/llvm/test.c", metadata !"/home/espindola/llvm/build", metadata !"clang version 3.0 ()", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !5, null} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 786478, metadata !6, metadata !1, metadata !"f", metadata !"f", metadata !"", i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void ()* @f, null, null, null, i32 1} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786473, metadata !6} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 786449, metadata !6, i32 12, metadata !"clang version 3.0 ()", i1 true, metadata !"", i32 0, metadata !4, metadata !4, metadata !5, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !6, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{null}
+!6 = metadata !{metadata !"/home/espindola/llvm/test.c", metadata !"/home/espindola/llvm/build"}
diff --git a/test/DebugInfo/X86/earlydup-crash.ll b/test/DebugInfo/X86/earlydup-crash.ll
index 5bd0c7e..1e66264 100644
--- a/test/DebugInfo/X86/earlydup-crash.ll
+++ b/test/DebugInfo/X86/earlydup-crash.ll
@@ -42,44 +42,51 @@ bb33:                                             ; preds = %bb31, %bb22, %bb18,
 
 declare void @foobar(i32)
 
+!llvm.dbg.cu = !{!4}
 !0 = metadata !{i32 590080, metadata !1, metadata !"frname_len", metadata !3, i32 517, metadata !38, i32 0} ; [ DW_TAG_auto_variable ]
-!1 = metadata !{i32 589835, metadata !2, i32 515, i32 0, metadata !3, i32 19} ; [ DW_TAG_lexical_block ]
-!2 = metadata !{i32 589870, i32 0, metadata !3, metadata !"framework_construct_pathname", metadata !"framework_construct_pathname", metadata !"", metadata !3, i32 515, metadata !5, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8* (i8*, %struct.cpp_dir*)* @framework_construct_pathname} ; [ DW_TAG_subprogram ]
-!3 = metadata !{i32 589865, metadata !"darwin-c.c", metadata !"/Users/espindola/llvm/build-llvm-gcc/gcc/../../llvm-gcc-4.2/gcc/config", metadata !4} ; [ DW_TAG_file_type ]
-!4 = metadata !{i32 589841, i32 0, i32 1, metadata !"/Users/espindola/llvm/build-llvm-gcc/gcc/../../llvm-gcc-4.2/gcc/config/darwin-c.c", metadata !"/Users/espindola/llvm/build-llvm-gcc/gcc", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!5 = metadata !{i32 589845, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!1 = metadata !{i32 589835, metadata !44, metadata !2, i32 515, i32 0, i32 19} ; [ DW_TAG_lexical_block ]
+!2 = metadata !{i32 589870, metadata !44, null, metadata !"framework_construct_pathname", metadata !"framework_construct_pathname", metadata !"", i32 515, metadata !5, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8* (i8*, %struct.cpp_dir*)* @framework_construct_pathname, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!3 = metadata !{i32 589865, metadata !44}  ; [ DW_TAG_file_type ]
+!4 = metadata !{i32 589841, metadata !44, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !46, metadata !46, metadata !45, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!5 = metadata !{i32 589845, metadata !44, metadata !3, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !6 = metadata !{metadata !7, metadata !9, metadata !11}
-!7 = metadata !{i32 589839, metadata !3, metadata !"", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ]
-!8 = metadata !{i32 589860, metadata !3, metadata !"char", metadata !3, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
-!9 = metadata !{i32 589839, metadata !3, metadata !"", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ]
-!10 = metadata !{i32 589862, metadata !3, metadata !"", metadata !3, i32 0, i64 8, i64 8, i64 0, i32 0, metadata !8} ; [ DW_TAG_const_type ]
-!11 = metadata !{i32 589839, metadata !3, metadata !"", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ]
-!12 = metadata !{i32 589846, metadata !13, metadata !"cpp_dir", metadata !13, i32 45, i64 0, i64 0, i64 0, i32 0, metadata !14} ; [ DW_TAG_typedef ]
-!13 = metadata !{i32 589865, metadata !"cpplib.h", metadata !"/Users/espindola/llvm/build-llvm-gcc/gcc/../../llvm-gcc-4.2/gcc/../libcpp/include", metadata !4} ; [ DW_TAG_file_type ]
-!14 = metadata !{i32 589843, metadata !3, metadata !"cpp_dir", metadata !13, i32 43, i64 352, i64 32, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_structure_type ]
+!7 = metadata !{i32 589839, metadata !44, metadata !3, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ]
+!8 = metadata !{i32 589860, metadata !44, metadata !3, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 589839, metadata !44, metadata !3, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ]
+!10 = metadata !{i32 589862, metadata !44, metadata !3, metadata !"", i32 0, i64 8, i64 8, i64 0, i32 0, metadata !8} ; [ DW_TAG_const_type ]
+!11 = metadata !{i32 589839, metadata !44, metadata !3, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ]
+!12 = metadata !{i32 589846, metadata !41, metadata !13, metadata !"cpp_dir", i32 45, i64 0, i64 0, i64 0, i32 0, metadata !14} ; [ DW_TAG_typedef ]
+!13 = metadata !{i32 589865, metadata !41} ; [ DW_TAG_file_type ]
+!14 = metadata !{i32 589843, metadata !41, metadata !3, metadata !"cpp_dir", i32 43, i64 352, i64 32, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_structure_type ]
 !15 = metadata !{metadata !16, metadata !18, metadata !19, metadata !21, metadata !23, metadata !25, metadata !27, metadata !29, metadata !33, metadata !36}
-!16 = metadata !{i32 589837, metadata !14, metadata !"next", metadata !13, i32 572, i64 32, i64 32, i64 0, i32 0, metadata !17} ; [ DW_TAG_member ]
-!17 = metadata !{i32 589839, metadata !3, metadata !"", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ]
-!18 = metadata !{i32 589837, metadata !14, metadata !"name", metadata !13, i32 575, i64 32, i64 32, i64 32, i32 0, metadata !7} ; [ DW_TAG_member ]
-!19 = metadata !{i32 589837, metadata !14, metadata !"len", metadata !13, i32 576, i64 32, i64 32, i64 64, i32 0, metadata !20} ; [ DW_TAG_member ]
-!20 = metadata !{i32 589860, metadata !3, metadata !"unsigned int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
-!21 = metadata !{i32 589837, metadata !14, metadata !"sysp", metadata !13, i32 580, i64 8, i64 8, i64 96, i32 0, metadata !22} ; [ DW_TAG_member ]
-!22 = metadata !{i32 589860, metadata !3, metadata !"unsigned char", metadata !3, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ]
-!23 = metadata !{i32 589837, metadata !14, metadata !"name_map", metadata !13, i32 584, i64 32, i64 32, i64 128, i32 0, metadata !24} ; [ DW_TAG_member ]
-!24 = metadata !{i32 589839, metadata !3, metadata !"", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ]
-!25 = metadata !{i32 589837, metadata !14, metadata !"header_map", metadata !13, i32 590, i64 32, i64 32, i64 160, i32 0, metadata !26} ; [ DW_TAG_member ]
-!26 = metadata !{i32 589839, metadata !3, metadata !"", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
-!27 = metadata !{i32 589837, metadata !14, metadata !"construct", metadata !13, i32 597, i64 32, i64 32, i64 192, i32 0, metadata !28} ; [ DW_TAG_member ]
-!28 = metadata !{i32 589839, metadata !3, metadata !"", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_pointer_type ]
-!29 = metadata !{i32 589837, metadata !14, metadata !"ino", metadata !13, i32 601, i64 64, i64 64, i64 224, i32 0, metadata !30} ; [ DW_TAG_member ]
-!30 = metadata !{i32 589846, metadata !31, metadata !"ino_t", metadata !31, i32 141, i64 0, i64 0, i64 0, i32 0, metadata !32} ; [ DW_TAG_typedef ]
-!31 = metadata !{i32 589865, metadata !"types.h", metadata !"/usr/include/sys", metadata !4} ; [ DW_TAG_file_type ]
-!32 = metadata !{i32 589860, metadata !3, metadata !"long long unsigned int", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
-!33 = metadata !{i32 589837, metadata !14, metadata !"dev", metadata !13, i32 602, i64 32, i64 32, i64 288, i32 0, metadata !34} ; [ DW_TAG_member ]
-!34 = metadata !{i32 589846, metadata !31, metadata !"dev_t", metadata !31, i32 107, i64 0, i64 0, i64 0, i32 0, metadata !35} ; [ DW_TAG_typedef ]
-!35 = metadata !{i32 589860, metadata !3, metadata !"int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!36 = metadata !{i32 589837, metadata !14, metadata !"user_supplied_p", metadata !13, i32 605, i64 8, i64 8, i64 320, i32 0, metadata !37} ; [ DW_TAG_member ]
-!37 = metadata !{i32 589860, metadata !3, metadata !"_Bool", metadata !3, i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ]
-!38 = metadata !{i32 589846, metadata !39, metadata !"size_t", metadata !39, i32 326, i64 0, i64 0, i64 0, i32 0, metadata !40} ; [ DW_TAG_typedef ]
-!39 = metadata !{i32 589865, metadata !"stddef.h", metadata !"/Users/espindola/llvm/build-llvm-gcc/./prev-gcc/include", metadata !4} ; [ DW_TAG_file_type ]
-!40 = metadata !{i32 589860, metadata !3, metadata !"long unsigned int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!16 = metadata !{i32 589837, metadata !41, metadata !14, metadata !"next", i32 572, i64 32, i64 32, i64 0, i32 0, metadata !17} ; [ DW_TAG_member ]
+!17 = metadata !{i32 589839, metadata !44, metadata !3, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ]
+!18 = metadata !{i32 589837, metadata !41, metadata !14, metadata !"name", i32 575, i64 32, i64 32, i64 32, i32 0, metadata !7} ; [ DW_TAG_member ]
+!19 = metadata !{i32 589837, metadata !41, metadata !14, metadata !"len", i32 576, i64 32, i64 32, i64 64, i32 0, metadata !20} ; [ DW_TAG_member ]
+!20 = metadata !{i32 589860, metadata !44, metadata !3, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!21 = metadata !{i32 589837, metadata !41, metadata !14, metadata !"sysp", i32 580, i64 8, i64 8, i64 96, i32 0, metadata !22} ; [ DW_TAG_member ]
+!22 = metadata !{i32 589860, metadata !44, metadata !3, metadata !"unsigned char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ]
+!23 = metadata !{i32 589837, metadata !41, metadata !14, metadata !"name_map", i32 584, i64 32, i64 32, i64 128, i32 0, metadata !24} ; [ DW_TAG_member ]
+!24 = metadata !{i32 589839, metadata !44, metadata !3, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ]
+!25 = metadata !{i32 589837, metadata !41, metadata !14, metadata !"header_map", i32 590, i64 32, i64 32, i64 160, i32 0, metadata !26} ; [ DW_TAG_member ]
+!26 = metadata !{i32 589839, metadata !44, metadata !3, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
+!27 = metadata !{i32 589837, metadata !41, metadata !14, metadata !"construct", i32 597, i64 32, i64 32, i64 192, i32 0, metadata !28} ; [ DW_TAG_member ]
+!28 = metadata !{i32 589839, metadata !44, metadata !3, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_pointer_type ]
+!29 = metadata !{i32 589837, metadata !41, metadata !14, metadata !"ino", i32 601, i64 64, i64 64, i64 224, i32 0, metadata !30} ; [ DW_TAG_member ]
+!30 = metadata !{i32 589846, metadata !42, metadata !31, metadata !"ino_t", i32 141, i64 0, i64 0, i64 0, i32 0, metadata !32} ; [ DW_TAG_typedef ]
+!31 = metadata !{i32 589865, metadata !42} ; [ DW_TAG_file_type ]
+!32 = metadata !{i32 589860, metadata !44, metadata !3, metadata !"long long unsigned int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!33 = metadata !{i32 589837, metadata !41, metadata !14, metadata !"dev", i32 602, i64 32, i64 32, i64 288, i32 0, metadata !34} ; [ DW_TAG_member ]
+!34 = metadata !{i32 589846, metadata !42, metadata !31, metadata !"dev_t", i32 107, i64 0, i64 0, i64 0, i32 0, metadata !35} ; [ DW_TAG_typedef ]
+!35 = metadata !{i32 589860, metadata !44, metadata !3, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!36 = metadata !{i32 589837, metadata !41, metadata !14, metadata !"user_supplied_p", i32 605, i64 8, i64 8, i64 320, i32 0, metadata !37} ; [ DW_TAG_member ]
+!37 = metadata !{i32 589860, metadata !44, metadata !3, metadata !"_Bool", i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ]
+!38 = metadata !{i32 589846, metadata !43, metadata !39, metadata !"size_t", i32 326, i64 0, i64 0, i64 0, i32 0, metadata !40} ; [ DW_TAG_typedef ]
+!39 = metadata !{i32 589865, metadata !43} ; [ DW_TAG_file_type ]
+!40 = metadata !{i32 589860, metadata !44, metadata !3, metadata !"long unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!41 = metadata !{metadata !"cpplib.h", metadata !"/Users/espindola/llvm/build-llvm-gcc/gcc/../../llvm-gcc-4.2/gcc/../libcpp/include"}
+!42 = metadata !{metadata !"types.h", metadata !"/usr/include/sys"}
+!43 = metadata !{metadata !"stddef.h", metadata !"/Users/espindola/llvm/build-llvm-gcc/./prev-gcc/include"}
+!44 = metadata !{metadata !"darwin-c.c", metadata !"/Users/espindola/llvm/build-llvm-gcc/gcc/../../llvm-gcc-4.2/gcc/config"}
+!45 = metadata !{metadata !2}
+!46 = metadata !{i32 0}
diff --git a/test/DebugInfo/X86/eh_symbol.ll b/test/DebugInfo/X86/eh_symbol.ll
index a87afed..9ab95b1 100644
--- a/test/DebugInfo/X86/eh_symbol.ll
+++ b/test/DebugInfo/X86/eh_symbol.ll
@@ -8,11 +8,15 @@ entry:
   ret i32 42
 }
 
+!llvm.dbg.cu = !{!2}
 !llvm.dbg.sp = !{!0}
 
-!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"f", metadata !"f", metadata !"", metadata !1, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 ()* @f, null, null} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 589865, metadata !"/home/espindola/llvm/test.c", metadata !"/home/espindola/tmpfs/build", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/home/espindola/llvm/test.c", metadata !"/home/espindola/tmpfs/build", metadata !"clang version 3.0 ()", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 589870, metadata !6, metadata !1, metadata !"f", metadata !"f", metadata !"", i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 ()* @f, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 589865, metadata !6} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 589841, metadata !6, i32 12, metadata !"clang version 3.0 ()", i1 true, metadata !"", i32 0, metadata !7, metadata !7, metadata !8, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 589845, metadata !6, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 589860, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{metadata !"/home/espindola/llvm/test.c", metadata !"/home/espindola/tmpfs/build"}
+!7 = metadata !{i32 0}
+!8 = metadata !{metadata !0}
diff --git a/test/DebugInfo/X86/ending-run.ll b/test/DebugInfo/X86/ending-run.ll
index b0156b8..b55ccc4 100644
--- a/test/DebugInfo/X86/ending-run.ll
+++ b/test/DebugInfo/X86/ending-run.ll
@@ -31,11 +31,11 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 !0 = metadata !{i32 786449, metadata !19, i32 12, metadata !"clang version 3.1 (trunk 153921) (llvm/trunk 153916)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, metadata !19, metadata !"callee", metadata !"callee", metadata !"", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 (i32)* @callee, null, null, metadata !10, i32 7} ; [ DW_TAG_subprogram ]
+!5 = metadata !{i32 786478, metadata !19, metadata !6, metadata !"callee", metadata !"callee", metadata !"", i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 (i32)* @callee, null, null, metadata !10, i32 7} ; [ DW_TAG_subprogram ]
 !6 = metadata !{i32 786473, metadata !19} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{metadata !9, metadata !9}
-!9 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !10 = metadata !{metadata !11}
 !11 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ]
 !12 = metadata !{i32 786689, metadata !5, metadata !"x", metadata !6, i32 16777221, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
diff --git a/test/DebugInfo/X86/enum-fwd-decl.ll b/test/DebugInfo/X86/enum-fwd-decl.ll
index f4ff8b4..03f590c 100644
--- a/test/DebugInfo/X86/enum-fwd-decl.ll
+++ b/test/DebugInfo/X86/enum-fwd-decl.ll
@@ -5,12 +5,13 @@
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.2 (trunk 165274) (llvm/trunk 165272)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3,  metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/foo.cpp] [DW_LANG_C_plus_plus]
+!0 = metadata !{i32 786449, metadata !8, i32 4, metadata !"clang version 3.2 (trunk 165274) (llvm/trunk 165272)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3,  metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/foo.cpp] [DW_LANG_C_plus_plus]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
 !5 = metadata !{i32 786484, i32 0, null, metadata !"e", metadata !"e", metadata !"", metadata !6, i32 2, metadata !7, i32 0, i32 1, i16* @e, null} ; [ DW_TAG_variable ] [e] [line 2] [def]
-!6 = metadata !{i32 786473, metadata !"foo.cpp", metadata !"/tmp", null} ; [ DW_TAG_file_type ]
-!7 = metadata !{i32 786436, metadata !6, null, metadata !"E", i32 1, i64 16, i64 16, i32 0, i32 4, null, null, i32 0} ; [ DW_TAG_enumeration_type ] [E] [line 1, size 16, align 16, offset 0] [fwd] [from ]
+!6 = metadata !{i32 786473, metadata !8} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 786436, metadata !8, null, metadata !"E", i32 1, i64 16, i64 16, i32 0, i32 4, null, null, i32 0} ; [ DW_TAG_enumeration_type ] [E] [line 1, size 16, align 16, offset 0] [fwd] [from ]
+!8 = metadata !{metadata !"foo.cpp", metadata !"/tmp"}
 
 ; CHECK: DW_TAG_enumeration_type
 ; CHECK-NEXT: DW_AT_name
diff --git a/test/DebugInfo/X86/generate-odr-hash.ll b/test/DebugInfo/X86/generate-odr-hash.ll
new file mode 100644
index 0000000..956d3f6
--- /dev/null
+++ b/test/DebugInfo/X86/generate-odr-hash.ll
@@ -0,0 +1,218 @@
+; REQUIRES: object-emission
+
+; RUN: llc %s -o %t -filetype=obj -O0 -generate-odr-hash -mtriple=x86_64-unknown-linux-gnu
+; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s
+;
+; Generated from:
+; struct bar {};
+
+; struct bar b;
+
+; void foo(void) {
+;   struct baz {};
+;   baz b;
+; }
+
+; namespace echidna {
+; namespace capybara {
+; namespace mongoose {
+; class fluffy {
+;   int a;
+;   int b;
+; };
+
+; fluffy animal;
+; }
+; }
+; }
+
+; namespace {
+; struct walrus {
+;   walrus() {}
+; };
+; }
+
+; walrus w;
+
+; struct wombat {
+;   struct {
+;     int a;
+;     int b;
+;   } a_b;
+; };
+
+; wombat wom;
+
+; Check that we generate a hash for bar and the value.
+; CHECK: DW_TAG_structure_type
+; CHECK-NEXT: debug_str{{.*}}"bar"
+; CHECK: DW_AT_GNU_odr_signature [DW_FORM_data8] (0x200520c0d5b90eff)
+; CHECK: DW_TAG_namespace
+; CHECK-NEXT: debug_str{{.*}}"echidna"
+; CHECK: DW_TAG_namespace
+; CHECK-NEXT: debug_str{{.*}}"capybara"
+; CHECK: DW_TAG_namespace
+; CHECK-NEXT: debug_str{{.*}}"mongoose"
+; CHECK: DW_TAG_class_type
+; CHECK-NEXT: debug_str{{.*}}"fluffy"
+; CHECK: DW_AT_GNU_odr_signature [DW_FORM_data8]   (0x9a0124d5a0c21c52)
+
+; We emit no hash for walrus since the type is contained in an anonymous
+; namespace and won't violate any ODR-ness.
+; CHECK: DW_TAG_structure_type
+; CHECK-NEXT: debug_str{{.*}}"walrus"
+; CHECK-NEXT: DW_AT_byte_size
+; CHECK-NEXT: DW_AT_decl_file
+; CHECK-NEXT: DW_AT_decl_line
+; CHECK-NOT: DW_AT_GNU_odr_signature
+; CHECK: DW_TAG_subprogram
+
+; Check that we generate a hash for wombat and the value, but not for the
+; anonymous type contained within.
+; CHECK: DW_TAG_structure_type
+; CHECK-NEXT: debug_str{{.*}}wombat
+; CHECK: DW_AT_GNU_odr_signature [DW_FORM_data8] (0x685bcc220141e9d7)
+; CHECK: DW_TAG_structure_type
+; CHECK-NEXT: DW_AT_byte_size
+; CHECK-NEXT: DW_AT_decl_file
+; CHECK-NEXT: DW_AT_decl_line
+; CHECK: DW_TAG_member
+; CHECK-NEXT: debug_str{{.*}}"a"
+
+; Check that we don't generate a hash for baz.
+; CHECK: DW_TAG_structure_type
+; CHECK-NEXT: debug_str{{.*}}"baz"
+; CHECK-NOT: DW_AT_GNU_odr_signature
+
+%struct.bar = type { i8 }
+%"class.echidna::capybara::mongoose::fluffy" = type { i32, i32 }
+%"struct.<anonymous namespace>::walrus" = type { i8 }
+%struct.wombat = type { %struct.anon }
+%struct.anon = type { i32, i32 }
+%struct.baz = type { i8 }
+
+@b = global %struct.bar zeroinitializer, align 1
+@_ZN7echidna8capybara8mongoose6animalE = global %"class.echidna::capybara::mongoose::fluffy" zeroinitializer, align 4
+@w = internal global %"struct.<anonymous namespace>::walrus" zeroinitializer, align 1
+@wom = global %struct.wombat zeroinitializer, align 4
+@llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }]
+
+@_ZN12_GLOBAL__N_16walrusC1Ev = alias internal void (%"struct.<anonymous namespace>::walrus"*)* @_ZN12_GLOBAL__N_16walrusC2Ev
+
+; Function Attrs: nounwind uwtable
+define void @_Z3foov() #0 {
+entry:
+  %b = alloca %struct.baz, align 1
+  call void @llvm.dbg.declare(metadata !{%struct.baz* %b}, metadata !63), !dbg !71
+  ret void, !dbg !72
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata) #1
+
+define internal void @__cxx_global_var_init() section ".text.startup" {
+entry:
+  call void @_ZN12_GLOBAL__N_16walrusC1Ev(%"struct.<anonymous namespace>::walrus"* @w), !dbg !73
+  ret void, !dbg !73
+}
+
+; Function Attrs: nounwind uwtable
+define internal void @_ZN12_GLOBAL__N_16walrusC2Ev(%"struct.<anonymous namespace>::walrus"* %this) unnamed_addr #0 align 2 {
+entry:
+  %this.addr = alloca %"struct.<anonymous namespace>::walrus"*, align 8
+  store %"struct.<anonymous namespace>::walrus"* %this, %"struct.<anonymous namespace>::walrus"** %this.addr, align 8
+  call void @llvm.dbg.declare(metadata !{%"struct.<anonymous namespace>::walrus"** %this.addr}, metadata !74), !dbg !76
+  %this1 = load %"struct.<anonymous namespace>::walrus"** %this.addr
+  ret void, !dbg !76
+}
+
+define internal void @_GLOBAL__I_a() section ".text.startup" {
+entry:
+  call void @__cxx_global_var_init(), !dbg !77
+  ret void, !dbg !77
+}
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!62}
+
+!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.4 (trunk 187387) (llvm/trunk 187385)", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !20, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/bar.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{metadata !"bar.cpp", metadata !"/usr/local/google/home/echristo/tmp"}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4, metadata !8, metadata !9, metadata !18}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"foo", metadata !"foo", metadata !"_Z3foov", i32 6, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @_Z3foov, null, null, metadata !2, i32 6} ; [ DW_TAG_subprogram ] [line 6] [def] [foo]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [/usr/local/google/home/echristo/tmp/bar.cpp]
+!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{null}
+!8 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"__cxx_global_var_init", metadata !"__cxx_global_var_init", metadata !"", i32 31, metadata !6, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @__cxx_global_var_init, null, null, metadata !2, i32 31} ; [ DW_TAG_subprogram ] [line 31] [local] [def] [__cxx_global_var_init]
+!9 = metadata !{i32 786478, metadata !1, metadata !10, metadata !"walrus", metadata !"walrus", metadata !"_ZN12_GLOBAL__N_16walrusC2Ev", i32 27, metadata !11, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%"struct.<anonymous namespace>::walrus"*)* @_ZN12_GLOBAL__N_16walrusC2Ev, null, metadata !16, metadata !2, i32 27} ; [ DW_TAG_subprogram ] [line 27] [local] [def] [walrus]
+!10 = metadata !{i32 786489, metadata !1, null, metadata !"", i32 25} ; [ DW_TAG_namespace ] [line 25]
+!11 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = metadata !{null, metadata !13}
+!13 = metadata !{i32 786447, i32 0, i32 0, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !14} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from walrus]
+!14 = metadata !{i32 786451, metadata !1, metadata !10, metadata !"walrus", i32 26, i64 8, i64 8, i32 0, i32 0, null, metadata !15, i32 0, null, null} ; [ DW_TAG_structure_type ] [walrus] [line 26, size 8, align 8, offset 0] [def] [from ]
+!15 = metadata !{metadata !16}
+!16 = metadata !{i32 786478, metadata !1, metadata !14, metadata !"walrus", metadata !"walrus", metadata !"", i32 27, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !17, i32 27} ; [ DW_TAG_subprogram ] [line 27] [walrus]
+!17 = metadata !{i32 786468}
+!18 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"_GLOBAL__I_a", metadata !"_GLOBAL__I_a", metadata !"", i32 27, metadata !19, i1 true, i1 true, i32 0, i32 0, null, i32 64, i1 false, void ()* @_GLOBAL__I_a, null, null, metadata !2, i32 27} ; [ DW_TAG_subprogram ] [line 27] [local] [def] [_GLOBAL__I_a]
+!19 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!20 = metadata !{metadata !21, metadata !29, metadata !43, metadata !44}
+!21 = metadata !{i32 786484, i32 0, null, metadata !"b", metadata !"b", metadata !"", metadata !5, i32 4, metadata !22, i32 0, i32 1, %struct.bar* @b, null} ; [ DW_TAG_variable ] [b] [line 4] [def]
+!22 = metadata !{i32 786451, metadata !1, null, metadata !"bar", i32 1, i64 8, i64 8, i32 0, i32 0, null, metadata !23, i32 0, null, null} ; [ DW_TAG_structure_type ] [bar] [line 1, size 8, align 8, offset 0] [def] [from ]
+!23 = metadata !{metadata !24}
+!24 = metadata !{i32 786478, metadata !1, metadata !22, metadata !"bar", metadata !"bar", metadata !"", i32 1, metadata !25, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !28, i32 1} ; [ DW_TAG_subprogram ] [line 1] [bar]
+!25 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !26, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!26 = metadata !{null, metadata !27}
+!27 = metadata !{i32 786447, i32 0, i32 0, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !22} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from bar]
+!28 = metadata !{i32 786468}
+!29 = metadata !{i32 786484, i32 0, metadata !30, metadata !"animal", metadata !"animal", metadata !"_ZN7echidna8capybara8mongoose6animalE", metadata !5, i32 20, metadata !33, i32 0, i32 1, %"class.echidna::capybara::mongoose::fluffy"* @_ZN7echidna8capybara8mongoose6animalE, null} ; [ DW_TAG_variable ] [animal] [line 20] [def]
+!30 = metadata !{i32 786489, metadata !1, metadata !31, metadata !"mongoose", i32 14} ; [ DW_TAG_namespace ] [mongoose] [line 14]
+!31 = metadata !{i32 786489, metadata !1, metadata !32, metadata !"capybara", i32 13} ; [ DW_TAG_namespace ] [capybara] [line 13]
+!32 = metadata !{i32 786489, metadata !1, null, metadata !"echidna", i32 12} ; [ DW_TAG_namespace ] [echidna] [line 12]
+!33 = metadata !{i32 786434, metadata !1, metadata !30, metadata !"fluffy", i32 15, i64 64, i64 32, i32 0, i32 0, null, metadata !34, i32 0, null, null} ; [ DW_TAG_class_type ] [fluffy] [line 15, size 64, align 32, offset 0] [def] [from ]
+!34 = metadata !{metadata !35, metadata !37, metadata !38}
+!35 = metadata !{i32 786445, metadata !1, metadata !33, metadata !"a", i32 16, i64 32, i64 32, i64 0, i32 1, metadata !36} ; [ DW_TAG_member ] [a] [line 16, size 32, align 32, offset 0] [private] [from int]
+!36 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!37 = metadata !{i32 786445, metadata !1, metadata !33, metadata !"b", i32 17, i64 32, i64 32, i64 32, i32 1, metadata !36} ; [ DW_TAG_member ] [b] [line 17, size 32, align 32, offset 32] [private] [from int]
+!38 = metadata !{i32 786478, metadata !1, metadata !33, metadata !"fluffy", metadata !"fluffy", metadata !"", i32 15, metadata !39, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !42, i32 15} ; [ DW_TAG_subprogram ] [line 15] [fluffy]
+!39 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !40, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!40 = metadata !{null, metadata !41}
+!41 = metadata !{i32 786447, i32 0, i32 0, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !33} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from fluffy]
+!42 = metadata !{i32 786468}
+!43 = metadata !{i32 786484, i32 0, null, metadata !"w", metadata !"w", metadata !"", metadata !5, i32 31, metadata !14, i32 1, i32 1, %"struct.<anonymous namespace>::walrus"* @w, null} ; [ DW_TAG_variable ] [w] [line 31] [local] [def]
+!44 = metadata !{i32 786484, i32 0, null, metadata !"wom", metadata !"wom", metadata !"", metadata !5, i32 40, metadata !45, i32 0, i32 1, %struct.wombat* @wom, null} ; [ DW_TAG_variable ] [wom] [line 40] [def]
+!45 = metadata !{i32 786451, metadata !1, null, metadata !"wombat", i32 33, i64 64, i64 32, i32 0, i32 0, null, metadata !46, i32 0, null, null} ; [ DW_TAG_structure_type ] [wombat] [line 33, size 64, align 32, offset 0] [def] [from ]
+!46 = metadata !{metadata !47, metadata !57}
+!47 = metadata !{i32 786445, metadata !1, metadata !45, metadata !"a_b", i32 37, i64 64, i64 32, i64 0, i32 0, metadata !48} ; [ DW_TAG_member ] [a_b] [line 37, size 64, align 32, offset 0] [from ]
+!48 = metadata !{i32 786451, metadata !1, metadata !45, metadata !"", i32 34, i64 64, i64 32, i32 0, i32 0, null, metadata !49, i32 0, null, null} ; [ DW_TAG_structure_type ] [line 34, size 64, align 32, offset 0] [def] [from ]
+!49 = metadata !{metadata !50, metadata !51, metadata !52}
+!50 = metadata !{i32 786445, metadata !1, metadata !48, metadata !"a", i32 35, i64 32, i64 32, i64 0, i32 0, metadata !36} ; [ DW_TAG_member ] [a] [line 35, size 32, align 32, offset 0] [from int]
+!51 = metadata !{i32 786445, metadata !1, metadata !48, metadata !"b", i32 36, i64 32, i64 32, i64 32, i32 0, metadata !36} ; [ DW_TAG_member ] [b] [line 36, size 32, align 32, offset 32] [from int]
+!52 = metadata !{i32 786478, metadata !1, metadata !48, metadata !"", metadata !"", metadata !"", i32 34, metadata !53, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !56, i32 34} ; [ DW_TAG_subprogram ] [line 34]
+!53 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !54, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!54 = metadata !{null, metadata !55}
+!55 = metadata !{i32 786447, i32 0, i32 0, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !48} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from ]
+!56 = metadata !{i32 786468}
+!57 = metadata !{i32 786478, metadata !1, metadata !45, metadata !"wombat", metadata !"wombat", metadata !"", i32 33, metadata !58, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !61, i32 33} ; [ DW_TAG_subprogram ] [line 33] [wombat]
+!58 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !59, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!59 = metadata !{null, metadata !60}
+!60 = metadata !{i32 786447, i32 0, i32 0, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !45} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from wombat]
+!61 = metadata !{i32 786468}
+!62 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}
+!63 = metadata !{i32 786688, metadata !4, metadata !"b", metadata !5, i32 9, metadata !64, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [b] [line 9]
+!64 = metadata !{i32 786451, metadata !1, metadata !4, metadata !"baz", i32 7, i64 8, i64 8, i32 0, i32 0, null, metadata !65, i32 0, null, null} ; [ DW_TAG_structure_type ] [baz] [line 7, size 8, align 8, offset 0] [def] [from ]
+!65 = metadata !{metadata !66}
+!66 = metadata !{i32 786478, metadata !1, metadata !64, metadata !"baz", metadata !"baz", metadata !"", i32 7, metadata !67, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !70, i32 7} ; [ DW_TAG_subprogram ] [line 7] [baz]
+!67 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !68, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!68 = metadata !{null, metadata !69}
+!69 = metadata !{i32 786447, i32 0, i32 0, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !64} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from baz]
+!70 = metadata !{i32 786468}
+!71 = metadata !{i32 9, i32 0, metadata !4, null}
+!72 = metadata !{i32 10, i32 0, metadata !4, null}
+!73 = metadata !{i32 31, i32 0, metadata !8, null}
+!74 = metadata !{i32 786689, metadata !9, metadata !"this", metadata !5, i32 16777243, metadata !75, i32 1088, i32 0} ; [ DW_TAG_arg_variable ] [this] [line 27]
+!75 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from walrus]
+!76 = metadata !{i32 27, i32 0, metadata !9, null}
+!77 = metadata !{i32 27, i32 0, metadata !18, null}
diff --git a/test/DebugInfo/X86/instcombine-instrinsics.ll b/test/DebugInfo/X86/instcombine-instrinsics.ll
index 4466828..886b0eb 100644
--- a/test/DebugInfo/X86/instcombine-instrinsics.ll
+++ b/test/DebugInfo/X86/instcombine-instrinsics.ll
@@ -61,7 +61,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.3 ", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !48, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.3 ", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !48, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{metadata !"i1", metadata !""}
 !2 = metadata !{i32 0}
 !3 = metadata !{metadata !4, metadata !21, metadata !33, metadata !47}
diff --git a/test/DebugInfo/X86/linkage-name.ll b/test/DebugInfo/X86/linkage-name.ll
index c9bd2cf..1ed7b18 100644
--- a/test/DebugInfo/X86/linkage-name.ll
+++ b/test/DebugInfo/X86/linkage-name.ll
@@ -26,7 +26,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.1 (trunk 152691) (llvm/trunk 152692)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !18,  metadata !18, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !28, i32 4, metadata !"clang version 3.1 (trunk 152691) (llvm/trunk 152692)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !18,  metadata !18, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
 !5 = metadata !{i32 786478, metadata !6, null, metadata !"a", metadata !"a", metadata !"_ZN1A1aEi", i32 5, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (%class.A*, i32)* @_ZN1A1aEi, null, metadata !13, metadata !16, i32 5} ; [ DW_TAG_subprogram ]
@@ -37,7 +37,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 !10 = metadata !{i32 786447, i32 0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !11} ; [ DW_TAG_pointer_type ]
 !11 = metadata !{i32 786434, metadata !28, null, metadata !"A", i32 1, i64 8, i64 8, i32 0, i32 0, null, metadata !12, i32 0, null, null} ; [ DW_TAG_class_type ]
 !12 = metadata !{metadata !13}
-!13 = metadata !{i32 786478, metadata !6, metadata !11, metadata !"a", metadata !"a", metadata !"_ZN1A1aEi", i32 2, metadata !7, i1 false, i1 false, i32 0, i32 0, null, i32 257, i1 false, null, null, i32 0, metadata !14} ; [ DW_TAG_subprogram ]
+!13 = metadata !{i32 786478, metadata !6, metadata !11, metadata !"a", metadata !"a", metadata !"_ZN1A1aEi", i32 2, metadata !7, i1 false, i1 false, i32 0, i32 0, null, i32 257, i1 false, null, null, i32 0, metadata !14, i32 0} ; [ DW_TAG_subprogram ]
 !14 = metadata !{metadata !15}
 !15 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ]
 !16 = metadata !{metadata !17}
diff --git a/test/DebugInfo/X86/low-pc-cu.ll b/test/DebugInfo/X86/low-pc-cu.ll
index c080555..f7e1aae 100644
--- a/test/DebugInfo/X86/low-pc-cu.ll
+++ b/test/DebugInfo/X86/low-pc-cu.ll
@@ -14,17 +14,17 @@ entry:
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.1 (trunk 153454) (llvm/trunk 153471)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !15, i32 4, metadata !"clang version 3.1 (trunk 153454) (llvm/trunk 153471)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5, metadata !12}
-!5 = metadata !{i32 786478, metadata !"_Z1qv", i32 0, metadata !6, metadata !"q", metadata !"q", metadata !6, i32 5, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @_Z1qv, null, null, metadata !10} ; [ DW_TAG_subprogram ]
+!5 = metadata !{i32 786478, metadata !6, i32 0, metadata !"q", metadata !"q", metadata !"_Z1qv", i32 5, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @_Z1qv, null, null, metadata !10, i32 0} ; [ DW_TAG_subprogram ]
 !6 = metadata !{i32 786473, metadata !15} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{metadata !9}
-!9 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 786468, metadata !15, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !10 = metadata !{metadata !11}
 !11 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ]
-!12 = metadata !{i32 786478, metadata !15, metadata !6, metadata !"t", metadata !"t", metadata !"", i32 2, metadata !7, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, null, null, null, metadata !10} ; [ DW_TAG_subprogram ]
+!12 = metadata !{i32 786478, metadata !15, metadata !6, metadata !"t", metadata !"t", metadata !"", i32 2, metadata !7, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, null, null, null, metadata !10, i32 0} ; [ DW_TAG_subprogram ]
 !13 = metadata !{i32 7, i32 1, metadata !14, null}
 !14 = metadata !{i32 786443, metadata !5, i32 5, i32 1, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
 !15 = metadata !{metadata !"foo.cpp", metadata !"/Users/echristo/tmp"}
diff --git a/test/DebugInfo/X86/misched-dbg-value.ll b/test/DebugInfo/X86/misched-dbg-value.ll
index 4b78c88..9aa362f 100644
--- a/test/DebugInfo/X86/misched-dbg-value.ll
+++ b/test/DebugInfo/X86/misched-dbg-value.ll
@@ -89,7 +89,7 @@ attributes #1 = { nounwind readnone }
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 12, metadata !3, metadata !"clang version 3.3 (trunk 175015)", i1 true, metadata !"", i32 0, metadata !1, metadata !10, metadata !11, metadata !29,  metadata !29, metadata !""} ; [ DW_TAG_compile_unit ] [/Users/manmanren/test-Nov/rdar_13183203/test2/dry.c] [DW_LANG_C99]
+!0 = metadata !{i32 786449, metadata !82, i32 12, metadata !"clang version 3.3 (trunk 175015)", i1 true, metadata !"", i32 0, metadata !1, metadata !10, metadata !11, metadata !29,  metadata !29, metadata !""} ; [ DW_TAG_compile_unit ] [/Users/manmanren/test-Nov/rdar_13183203/test2/dry.c] [DW_LANG_C99]
 !1 = metadata !{metadata !2}
 !2 = metadata !{i32 786436, metadata !82, null, metadata !"", i32 128, i64 32, i64 32, i32 0, i32 0, null, metadata !4, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] [line 128, size 32, align 32, offset 0] [from ]
 !3 = metadata !{i32 786473, metadata !82} ; [ DW_TAG_file_type ]
@@ -101,7 +101,7 @@ attributes #1 = { nounwind readnone }
 !9 = metadata !{i32 786472, metadata !"Ident5", i64 10003} ; [ DW_TAG_enumerator ] [Ident5 :: 10003]
 !10 = metadata !{i32 0}
 !11 = metadata !{metadata !12}
-!12 = metadata !{i32 786478, metadata !3, metadata !"Proc8", metadata !"Proc8", metadata !"", metadata !3, i32 180, metadata !13, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, void (i32*, [51 x i32]*, i32, i32)* @Proc8, null, null, metadata !22, i32 185} ; [ DW_TAG_subprogram ] [line 180] [def] [scope 185] [Proc8]
+!12 = metadata !{i32 786478, metadata !82, metadata !3, metadata !"Proc8", metadata !"Proc8", metadata !"", i32 180, metadata !13, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, void (i32*, [51 x i32]*, i32, i32)* @Proc8, null, null, metadata !22, i32 185} ; [ DW_TAG_subprogram ] [line 180] [def] [scope 185] [Proc8]
 !13 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !14, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !14 = metadata !{null, metadata !15, metadata !17, metadata !21, metadata !21}
 !15 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !16} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
@@ -162,7 +162,7 @@ attributes #1 = { nounwind readnone }
 !73 = metadata !{i32 191, i32 0, metadata !12, null}
 !74 = metadata !{i32 192, i32 0, metadata !12, null}
 !75 = metadata !{i32 193, i32 0, metadata !76, null}
-!76 = metadata !{i32 786443, metadata !12, i32 193, i32 0, metadata !3, i32 0} ; [ DW_TAG_lexical_block ] [/Users/manmanren/test-Nov/rdar_13183203/test2/dry.c]
+!76 = metadata !{i32 786443, metadata !82, metadata !12, i32 193, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [/Users/manmanren/test-Nov/rdar_13183203/test2/dry.c]
 !77 = metadata !{i32 194, i32 0, metadata !76, null}
 !78 = metadata !{i32 195, i32 0, metadata !12, null}
 !79 = metadata !{i32 196, i32 0, metadata !12, null}
diff --git a/test/DebugInfo/X86/multiple-at-const-val.ll b/test/DebugInfo/X86/multiple-at-const-val.ll
index 7779d1e..2e02cbd 100644
--- a/test/DebugInfo/X86/multiple-at-const-val.ll
+++ b/test/DebugInfo/X86/multiple-at-const-val.ll
@@ -31,7 +31,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 4, metadata !961, metadata !"clang version 3.3 (trunk 174207)", i1 true, metadata !"", i32 0, metadata !1, metadata !955, metadata !956, metadata !1786,  metadata !1786, metadata !""} ; [ DW_TAG_compile_unit ] [/privite/tmp/student2.cpp] [DW_LANG_C_plus_plus]
+!0 = metadata !{i32 786449, metadata !1802, i32 4, metadata !"clang version 3.3 (trunk 174207)", i1 true, metadata !"", i32 0, metadata !1, metadata !955, metadata !956, metadata !1786,  metadata !1786, metadata !""} ; [ DW_TAG_compile_unit ] [/privite/tmp/student2.cpp] [DW_LANG_C_plus_plus]
 !1 = metadata !{metadata !26}
 !4 = metadata !{i32 786489, null, metadata !"std", metadata !5, i32 48} ; [ DW_TAG_namespace ]
 !5 = metadata !{i32 786473, metadata !1801} ; [ DW_TAG_file_type ]
@@ -50,10 +50,10 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !56 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !77 = metadata !{i32 786445, metadata !1801, metadata !49, metadata !"badbit", i32 331, i64 0, i64 0, i64 0, i32 4096, metadata !78, i32 1} ; [ DW_TAG_member ]
 !78 = metadata !{i32 786470, null, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, metadata !79} ; [ DW_TAG_const_type ]
-!79 = metadata !{i32 786454, metadata !49, metadata !"ostate", metadata !5, i32 327, i64 0, i64 0, i64 0, i32 0, metadata !26} ; [ DW_TAG_typedef ]
+!79 = metadata !{i32 786454, metadata !1801, metadata !49, metadata !"ostate", i32 327, i64 0, i64 0, i64 0, i32 0, metadata !26} ; [ DW_TAG_typedef ]
 !955 = metadata !{i32 0}
 !956 = metadata !{metadata !960}
-!960 = metadata !{i32 786478, i32 0, metadata !961, metadata !"main", metadata !"main", metadata !"", metadata !961, i32 73, metadata !54, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 ()* @main, null, null, metadata !955, i32 73} ; [ DW_TAG_subprogram ]
+!960 = metadata !{i32 786478, metadata !1802, null, metadata !"main", metadata !"main", metadata !"", i32 73, metadata !54, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 ()* @main, null, null, metadata !955, i32 73} ; [ DW_TAG_subprogram ]
 !961 = metadata !{i32 786473, metadata !1802} ; [ DW_TAG_file_type ]
 !1786 = metadata !{metadata !1800}
 !1800 = metadata !{i32 786484, i32 0, metadata !5, metadata !"badbit", metadata !"badbit", metadata !"badbit", metadata !5, i32 331, metadata !78, i32 1, i32 1, i32 1, metadata !77} ; [ DW_TAG_variable ]
diff --git a/test/DebugInfo/X86/op_deref.ll b/test/DebugInfo/X86/op_deref.ll
index c3580a7..864cbef 100644
--- a/test/DebugInfo/X86/op_deref.ll
+++ b/test/DebugInfo/X86/op_deref.ll
@@ -1,10 +1,16 @@
 ; RUN: llc -O0 -mtriple=x86_64-apple-darwin %s -o %t -filetype=obj
-; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s
+; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s -check-prefix=DW-CHECK
 
-; CHECK: DW_AT_name [DW_FORM_strp]  ( .debug_str[0x00000067] = "vla")
+; DW-CHECK: DW_AT_name [DW_FORM_strp]  ( .debug_str[0x00000067] = "vla")
 ; FIXME: The location here needs to be fixed, but llvm-dwarfdump doesn't handle
 ; DW_AT_location lists yet.
-; CHECK: DW_AT_location [DW_FORM_data4]                      (0x00000000)
+; DW-CHECK: DW_AT_location [DW_FORM_data4]                      (0x00000000)
+
+; Unfortunately llvm-dwarfdump can't unparse a list of DW_AT_locations
+; right now, so we check the asm output:
+; RUN: llc -O0 -mtriple=x86_64-apple-darwin %s -o - -filetype=asm | FileCheck %s -check-prefix=ASM-CHECK
+; vla should have a register-indirect address at one point.
+; ASM-CHECK: DEBUG_VALUE: vla <- [RCX+0]
 
 define void @testVLAwithSize(i32 %s) nounwind uwtable ssp {
 entry:
@@ -62,7 +68,7 @@ declare void @llvm.stackrestore(i8*) nounwind
 !0 = metadata !{i32 786449, metadata !28, i32 12, metadata !"clang version 3.2 (trunk 156005) (llvm/trunk 156000)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, metadata !6, metadata !"testVLAwithSize", metadata !"testVLAwithSize", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32)* @testVLAwithSize, null, null, metadata !1, i32 2} ; [ DW_TAG_subprogram ]
+!5 = metadata !{i32 786478, metadata !28, metadata !6, metadata !"testVLAwithSize", metadata !"testVLAwithSize", metadata !"", i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32)* @testVLAwithSize, null, null, metadata !1, i32 2} ; [ DW_TAG_subprogram ]
 !6 = metadata !{i32 786473, metadata !28} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{null, metadata !9}
@@ -70,7 +76,7 @@ declare void @llvm.stackrestore(i8*) nounwind
 !10 = metadata !{i32 786689, metadata !5, metadata !"s", metadata !6, i32 16777217, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
 !11 = metadata !{i32 1, i32 26, metadata !5, null}
 !12 = metadata !{i32 3, i32 13, metadata !13, null}
-!13 = metadata !{i32 786443, metadata !6, metadata !5, i32 2, i32 1, i32 0} ; [ DW_TAG_lexical_block ]
+!13 = metadata !{i32 786443, metadata !28, metadata !5, i32 2, i32 1, i32 0} ; [ DW_TAG_lexical_block ]
 !14 = metadata !{i32 786688, metadata !13, metadata !"vla", metadata !6, i32 3, metadata !15, i32 0, i32 0, i64 2} ; [ DW_TAG_auto_variable ]
 !15 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 0, i64 32, i32 0, i32 0, metadata !9, metadata !16, i32 0, i32 0} ; [ DW_TAG_array_type ]
 !16 = metadata !{metadata !17}
@@ -79,9 +85,9 @@ declare void @llvm.stackrestore(i8*) nounwind
 !19 = metadata !{i32 786688, metadata !13, metadata !"i", metadata !6, i32 4, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
 !20 = metadata !{i32 4, i32 7, metadata !13, null}
 !21 = metadata !{i32 5, i32 8, metadata !22, null}
-!22 = metadata !{i32 786443, metadata !6, metadata !13, i32 5, i32 3, i32 1} ; [ DW_TAG_lexical_block ]
+!22 = metadata !{i32 786443, metadata !28, metadata !13, i32 5, i32 3, i32 1} ; [ DW_TAG_lexical_block ]
 !23 = metadata !{i32 6, i32 5, metadata !24, null}
-!24 = metadata !{i32 786443, metadata !6, metadata !22, i32 5, i32 27, i32 2} ; [ DW_TAG_lexical_block ]
+!24 = metadata !{i32 786443, metadata !28, metadata !22, i32 5, i32 27, i32 2} ; [ DW_TAG_lexical_block ]
 !25 = metadata !{i32 7, i32 3, metadata !24, null}
 !26 = metadata !{i32 5, i32 22, metadata !22, null}
 !27 = metadata !{i32 8, i32 1, metadata !13, null}
diff --git a/test/DebugInfo/X86/parameters.ll b/test/DebugInfo/X86/parameters.ll
new file mode 100644
index 0000000..7846924
--- /dev/null
+++ b/test/DebugInfo/X86/parameters.ll
@@ -0,0 +1,115 @@
+; REQUIRES: object-emission
+;
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -O0 -filetype=obj < %s > %t
+; RUN: llvm-dwarfdump %t | FileCheck %s
+
+; Test case derived from compiling the following source with clang -g:
+;
+; namespace pr14763 {
+; struct foo {
+;   foo(const foo&);
+; };
+;
+; foo func(foo f) {
+;   return f; // reference 'f' for now because otherwise we hit another bug
+; }
+;
+; void sink(void*);
+;
+; void func2(bool b, foo g) {
+;   if (b)
+;     sink(&g); // reference 'f' for now because otherwise we hit another bug
+; }
+; }
+
+; CHECK: debug_info contents
+; CHECK: DW_AT_name{{.*}} = "f"
+; 0x74 is DW_OP_breg4, showing that the parameter is accessed indirectly
+; (with a zero offset) from the register parameter
+; CHECK: DW_AT_location{{.*}}(<0x0{{.}}> 74 00
+
+; CHECK: DW_AT_name{{.*}} = "g"
+; CHECK: DW_AT_location{{.*}}([[G_LOC:0x[0-9]*]])
+; CHECK: debug_loc contents
+; CHECK-NEXT: [[G_LOC]]: Beginning
+; CHECK-NEXT:               Ending
+; CHECK-NEXT: Location description: 74 00
+
+%"struct.pr14763::foo" = type { i8 }
+
+; Function Attrs: uwtable
+define void @_ZN7pr147634funcENS_3fooE(%"struct.pr14763::foo"* noalias sret %agg.result, %"struct.pr14763::foo"* %f) #0 {
+entry:
+  call void @llvm.dbg.declare(metadata !{%"struct.pr14763::foo"* %f}, metadata !22), !dbg !24
+  call void @_ZN7pr147633fooC1ERKS0_(%"struct.pr14763::foo"* %agg.result, %"struct.pr14763::foo"* %f), !dbg !25
+  ret void, !dbg !25
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata) #1
+
+declare void @_ZN7pr147633fooC1ERKS0_(%"struct.pr14763::foo"*, %"struct.pr14763::foo"*) #2
+
+; Function Attrs: uwtable
+define void @_ZN7pr147635func2EbNS_3fooE(i1 zeroext %b, %"struct.pr14763::foo"* %g) #0 {
+entry:
+  %b.addr = alloca i8, align 1
+  %frombool = zext i1 %b to i8
+  store i8 %frombool, i8* %b.addr, align 1
+  call void @llvm.dbg.declare(metadata !{i8* %b.addr}, metadata !26), !dbg !27
+  call void @llvm.dbg.declare(metadata !{%"struct.pr14763::foo"* %g}, metadata !28), !dbg !27
+  %0 = load i8* %b.addr, align 1, !dbg !29
+  %tobool = trunc i8 %0 to i1, !dbg !29
+  br i1 %tobool, label %if.then, label %if.end, !dbg !29
+
+if.then:                                          ; preds = %entry
+  %1 = bitcast %"struct.pr14763::foo"* %g to i8*, !dbg !31
+  call void @_ZN7pr147634sinkEPv(i8* %1), !dbg !31
+  br label %if.end, !dbg !31
+
+if.end:                                           ; preds = %if.then, %entry
+  ret void, !dbg !32
+}
+
+declare void @_ZN7pr147634sinkEPv(i8*) #2
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!21}
+
+!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.4 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/pass.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{metadata !"pass.cpp", metadata !"/tmp"}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4, metadata !17}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"func", metadata !"func", metadata !"_ZN7pr147634funcENS_3fooE", i32 6, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%"struct.pr14763::foo"*, %"struct.pr14763::foo"*)* @_ZN7pr147634funcENS_3fooE, null, null, metadata !2, i32 6} ; [ DW_TAG_subprogram ] [line 6] [def] [func]
+!5 = metadata !{i32 786489, metadata !1, null, metadata !"pr14763", i32 1} ; [ DW_TAG_namespace ] [pr14763] [line 1]
+!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{metadata !8, metadata !8}
+!8 = metadata !{i32 786451, metadata !1, metadata !5, metadata !"foo", i32 2, i64 8, i64 8, i32 0, i32 0, null, metadata !9, i32 0, null, null} ; [ DW_TAG_structure_type ] [foo] [line 2, size 8, align 8, offset 0] [from ]
+!9 = metadata !{metadata !10}
+!10 = metadata !{i32 786478, metadata !1, metadata !8, metadata !"foo", metadata !"foo", metadata !"", i32 3, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !16, i32 3} ; [ DW_TAG_subprogram ] [line 3] [foo]
+!11 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!12 = metadata !{null, metadata !13, metadata !14}
+!13 = metadata !{i32 786447, i32 0, i32 0, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !8} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from foo]
+!14 = metadata !{i32 786448, null, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !15} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from ]
+!15 = metadata !{i32 786470, null, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, metadata !8} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from foo]
+!16 = metadata !{i32 786468}
+!17 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"func2", metadata !"func2", metadata !"_ZN7pr147635func2EbNS_3fooE", i32 12, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i1, %"struct.pr14763::foo"*)* @_ZN7pr147635func2EbNS_3fooE, null, null, metadata !2, i32 12} ; [ DW_TAG_subprogram ] [line 12] [def] [func2]
+!18 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !19, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!19 = metadata !{null, metadata !20, metadata !8}
+!20 = metadata !{i32 786468, null, null, metadata !"bool", i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] [bool] [line 0, size 8, align 8, offset 0, enc DW_ATE_boolean]
+!21 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}
+!22 = metadata !{i32 786689, metadata !4, metadata !"f", metadata !23, i32 16777222, metadata !8, i32 8192, i32 0} ; [ DW_TAG_arg_variable ] [f] [line 6]
+!23 = metadata !{i32 786473, metadata !1}         ; [ DW_TAG_file_type ] [/tmp/pass.cpp]
+!24 = metadata !{i32 6, i32 0, metadata !4, null}
+!25 = metadata !{i32 7, i32 0, metadata !4, null}
+!26 = metadata !{i32 786689, metadata !17, metadata !"b", metadata !23, i32 16777228, metadata !20, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [b] [line 12]
+!27 = metadata !{i32 12, i32 0, metadata !17, null}
+!28 = metadata !{i32 786689, metadata !17, metadata !"g", metadata !23, i32 33554444, metadata !8, i32 8192, i32 0} ; [ DW_TAG_arg_variable ] [g] [line 12]
+!29 = metadata !{i32 13, i32 0, metadata !30, null}
+!30 = metadata !{i32 786443, metadata !1, metadata !17, i32 13, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [/tmp/pass.cpp]
+!31 = metadata !{i32 14, i32 0, metadata !30, null}
+!32 = metadata !{i32 15, i32 0, metadata !17, null}
diff --git a/test/DebugInfo/X86/pointer-type-size.ll b/test/DebugInfo/X86/pointer-type-size.ll
index b065353..a640069 100644
--- a/test/DebugInfo/X86/pointer-type-size.ll
+++ b/test/DebugInfo/X86/pointer-type-size.ll
@@ -10,7 +10,7 @@
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.1 (trunk 147882)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3,  metadata !3, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !13, i32 12, metadata !"clang version 3.1 (trunk 147882)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3,  metadata !3, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
 !5 = metadata !{i32 720948, i32 0, null, metadata !"crass", metadata !"crass", metadata !"", metadata !6, i32 1, metadata !7, i32 0, i32 1, %struct.crass* @crass, null} ; [ DW_TAG_variable ]
diff --git a/test/DebugInfo/X86/pr12831.ll b/test/DebugInfo/X86/pr12831.ll
index 295c018..0244d1e 100644
--- a/test/DebugInfo/X86/pr12831.ll
+++ b/test/DebugInfo/X86/pr12831.ll
@@ -77,46 +77,46 @@ entry:
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 4, metadata !159, metadata !"clang version 3.2 ", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !128, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !161, i32 4, metadata !"clang version 3.2 ", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !128, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5, metadata !106, metadata !107, metadata !126, metadata !127}
-!5 = metadata !{i32 786478, metadata !"_ZN17BPLFunctionWriter9writeExprEv", i32 0, null, metadata !"writeExpr", metadata !"writeExpr", metadata !6, i32 19, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%class.BPLFunctionWriter*)* @_ZN17BPLFunctionWriter9writeExprEv, null, metadata !103, metadata !1, i32 19} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 786473, metadata !"BPLFunctionWriter2.ii", metadata !"/home/peter/crashdelta", null} ; [ DW_TAG_file_type ]
+!5 = metadata !{i32 786478, metadata !6, null, metadata !"writeExpr", metadata !"writeExpr", metadata !"_ZN17BPLFunctionWriter9writeExprEv", i32 19, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%class.BPLFunctionWriter*)* @_ZN17BPLFunctionWriter9writeExprEv, null, metadata !103, metadata !1, i32 19} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 786473, metadata !160} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{null, metadata !9}
 !9 = metadata !{i32 786447, i32 0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !10} ; [ DW_TAG_pointer_type ]
-!10 = metadata !{i32 786434, null, metadata !"BPLFunctionWriter", metadata !6, i32 15, i64 64, i64 64, i32 0, i32 0, null, metadata !11, i32 0, null, null} ; [ DW_TAG_class_type ]
+!10 = metadata !{i32 786434, metadata !160, null, metadata !"BPLFunctionWriter", i32 15, i64 64, i64 64, i32 0, i32 0, null, metadata !11, i32 0, null, null} ; [ DW_TAG_class_type ]
 !11 = metadata !{metadata !12, metadata !103}
-!12 = metadata !{i32 786445, metadata !10, metadata !"MW", metadata !6, i32 16, i64 64, i64 64, i64 0, i32 1, metadata !13} ; [ DW_TAG_member ]
+!12 = metadata !{i32 786445, metadata !160, metadata !10, metadata !"MW", i32 16, i64 64, i64 64, i64 0, i32 1, metadata !13} ; [ DW_TAG_member ]
 !13 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ]
-!14 = metadata !{i32 786434, null, metadata !"BPLModuleWriter", metadata !6, i32 12, i64 8, i64 8, i32 0, i32 0, null, metadata !15, i32 0, null, null} ; [ DW_TAG_class_type ]
+!14 = metadata !{i32 786434, metadata !160, null, metadata !"BPLModuleWriter", i32 12, i64 8, i64 8, i32 0, i32 0, null, metadata !15, i32 0, null, null} ; [ DW_TAG_class_type ]
 !15 = metadata !{metadata !16}
-!16 = metadata !{i32 786478, metadata !"_ZN15BPLModuleWriter14writeIntrinsicE8functionIFvvEE", i32 0, metadata !14, metadata !"writeIntrinsic", metadata !"writeIntrinsic", metadata !6, i32 13, metadata !17, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !101, i32 13} ; [ DW_TAG_subprogram ]
+!16 = metadata !{i32 786478, metadata !6, metadata !14, metadata !"writeIntrinsic", metadata !"writeIntrinsic", metadata !"_ZN15BPLModuleWriter14writeIntrinsicE8functionIFvvEE", i32 13, metadata !17, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !101, i32 13} ; [ DW_TAG_subprogram ]
 !17 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !18, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !18 = metadata !{null, metadata !19, metadata !20}
 !19 = metadata !{i32 786447, i32 0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !14} ; [ DW_TAG_pointer_type ]
-!20 = metadata !{i32 786434, null, metadata !"function<void ()>", metadata !6, i32 6, i64 8, i64 8, i32 0, i32 0, null, metadata !21, i32 0, null, metadata !97} ; [ DW_TAG_class_type ]
+!20 = metadata !{i32 786434, metadata !160, null, metadata !"function<void ()>", i32 6, i64 8, i64 8, i32 0, i32 0, null, metadata !21, i32 0, null, metadata !97} ; [ DW_TAG_class_type ]
 !21 = metadata !{metadata !22, metadata !51, metadata !58, metadata !86, metadata !92}
-!22 = metadata !{i32 786478, metadata !"", i32 0, metadata !20, metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !6, i32 8, metadata !23, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, metadata !47, i32 0, metadata !49, i32 8} ; [ DW_TAG_subprogram ]
+!22 = metadata !{i32 786478, metadata !6, metadata !20, metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !"", i32 8, metadata !23, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, metadata !47, i32 0, metadata !49, i32 8} ; [ DW_TAG_subprogram ]
 !23 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !24, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !24 = metadata !{null, metadata !25, metadata !26}
 !25 = metadata !{i32 786447, i32 0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !20} ; [ DW_TAG_pointer_type ]
-!26 = metadata !{i32 786434, metadata !5, metadata !"", metadata !6, i32 20, i64 8, i64 8, i32 0, i32 0, null, metadata !27, i32 0, null, null} ; [ DW_TAG_class_type ]
+!26 = metadata !{i32 786434, metadata !160, metadata !5, metadata !"", i32 20, i64 8, i64 8, i32 0, i32 0, null, metadata !27, i32 0, null, null} ; [ DW_TAG_class_type ]
 !27 = metadata !{metadata !28, metadata !35, metadata !41}
-!28 = metadata !{i32 786478, metadata !"", i32 0, metadata !26, metadata !"operator()", metadata !"operator()", metadata !6, i32 20, metadata !29, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !33, i32 20} ; [ DW_TAG_subprogram ]
+!28 = metadata !{i32 786478, metadata !6, metadata !26, metadata !"operator()", metadata !"operator()", metadata !"", i32 20, metadata !29, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !33, i32 20} ; [ DW_TAG_subprogram ]
 !29 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !30, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !30 = metadata !{null, metadata !31}
 !31 = metadata !{i32 786447, i32 0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !32} ; [ DW_TAG_pointer_type ]
 !32 = metadata !{i32 786470, null, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !26} ; [ DW_TAG_const_type ]
 !33 = metadata !{metadata !34}
 !34 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ]
-!35 = metadata !{i32 786478, metadata !"", i32 0, metadata !26, metadata !"~", metadata !"~", metadata !6, i32 20, metadata !36, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !39, i32 20} ; [ DW_TAG_subprogram ]
+!35 = metadata !{i32 786478, metadata !6, metadata !26, metadata !"~", metadata !"~", metadata !"", i32 20, metadata !36, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !39, i32 20} ; [ DW_TAG_subprogram ]
 !36 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !37, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !37 = metadata !{null, metadata !38}
 !38 = metadata !{i32 786447, i32 0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !26} ; [ DW_TAG_pointer_type ]
 !39 = metadata !{metadata !40}
 !40 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ]
-!41 = metadata !{i32 786478, metadata !"", i32 0, metadata !26, metadata !"", metadata !"", metadata !6, i32 20, metadata !42, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !45, i32 20} ; [ DW_TAG_subprogram ]
+!41 = metadata !{i32 786478, metadata !6, metadata !26, metadata !"", metadata !"", metadata !"", i32 20, metadata !42, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !45, i32 20} ; [ DW_TAG_subprogram ]
 !42 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !43, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !43 = metadata !{null, metadata !38, metadata !44}
 !44 = metadata !{i32 786498, null, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !26} ; [ DW_TAG_rvalue_reference_type ]
@@ -126,32 +126,32 @@ entry:
 !48 = metadata !{i32 786479, null, metadata !"_Functor", metadata !26, null, i32 0, i32 0} ; [ DW_TAG_template_type_parameter ]
 !49 = metadata !{metadata !50}
 !50 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ]
-!51 = metadata !{i32 786478, metadata !"", i32 0, metadata !20, metadata !"function<function<void ()> >", metadata !"function<function<void ()> >", metadata !6, i32 8, metadata !52, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, metadata !54, i32 0, metadata !56, i32 8} ; [ DW_TAG_subprogram ]
+!51 = metadata !{i32 786478, metadata !6, metadata !20, metadata !"function<function<void ()> >", metadata !"function<function<void ()> >", metadata !"", i32 8, metadata !52, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, metadata !54, i32 0, metadata !56, i32 8} ; [ DW_TAG_subprogram ]
 !52 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !53, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !53 = metadata !{null, metadata !25, metadata !20}
 !54 = metadata !{metadata !55}
 !55 = metadata !{i32 786479, null, metadata !"_Functor", metadata !20, null, i32 0, i32 0} ; [ DW_TAG_template_type_parameter ]
 !56 = metadata !{metadata !57}
 !57 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ]
-!58 = metadata !{i32 786478, metadata !"", i32 0, metadata !20, metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !6, i32 8, metadata !59, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, metadata !82, i32 0, metadata !84, i32 8} ; [ DW_TAG_subprogram ]
+!58 = metadata !{i32 786478, metadata !6, metadata !20, metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !"", i32 8, metadata !59, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, metadata !82, i32 0, metadata !84, i32 8} ; [ DW_TAG_subprogram ]
 !59 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !60, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !60 = metadata !{null, metadata !25, metadata !61}
-!61 = metadata !{i32 786434, metadata !5, metadata !"", metadata !6, i32 23, i64 8, i64 8, i32 0, i32 0, null, metadata !62, i32 0, null, null} ; [ DW_TAG_class_type ]
+!61 = metadata !{i32 786434, metadata !160, metadata !5, metadata !"", i32 23, i64 8, i64 8, i32 0, i32 0, null, metadata !62, i32 0, null, null} ; [ DW_TAG_class_type ]
 !62 = metadata !{metadata !63, metadata !70, metadata !76}
-!63 = metadata !{i32 786478, metadata !"", i32 0, metadata !61, metadata !"operator()", metadata !"operator()", metadata !6, i32 23, metadata !64, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !68, i32 23} ; [ DW_TAG_subprogram ]
+!63 = metadata !{i32 786478, metadata !6, metadata !61, metadata !"operator()", metadata !"operator()", metadata !"", i32 23, metadata !64, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !68, i32 23} ; [ DW_TAG_subprogram ]
 !64 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !65, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !65 = metadata !{null, metadata !66}
 !66 = metadata !{i32 786447, i32 0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !67} ; [ DW_TAG_pointer_type ]
 !67 = metadata !{i32 786470, null, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !61} ; [ DW_TAG_const_type ]
 !68 = metadata !{metadata !69}
 !69 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ]
-!70 = metadata !{i32 786478, metadata !"", i32 0, metadata !61, metadata !"~", metadata !"~", metadata !6, i32 23, metadata !71, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !74, i32 23} ; [ DW_TAG_subprogram ]
+!70 = metadata !{i32 786478, metadata !6, metadata !61, metadata !"~", metadata !"~", metadata !"", i32 23, metadata !71, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !74, i32 23} ; [ DW_TAG_subprogram ]
 !71 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !72, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !72 = metadata !{null, metadata !73}
 !73 = metadata !{i32 786447, i32 0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !61} ; [ DW_TAG_pointer_type ]
 !74 = metadata !{metadata !75}
 !75 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ]
-!76 = metadata !{i32 786478, metadata !"", i32 0, metadata !61, metadata !"", metadata !"", metadata !6, i32 23, metadata !77, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !80, i32 23} ; [ DW_TAG_subprogram ]
+!76 = metadata !{i32 786478, metadata !6, metadata !61, metadata !"", metadata !"", metadata !"", i32 23, metadata !77, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !80, i32 23} ; [ DW_TAG_subprogram ]
 !77 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !78, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !78 = metadata !{null, metadata !73, metadata !79}
 !79 = metadata !{i32 786498, null, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !61} ; [ DW_TAG_rvalue_reference_type ]
@@ -161,13 +161,13 @@ entry:
 !83 = metadata !{i32 786479, null, metadata !"_Functor", metadata !61, null, i32 0, i32 0} ; [ DW_TAG_template_type_parameter ]
 !84 = metadata !{metadata !85}
 !85 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ]
-!86 = metadata !{i32 786478, metadata !"", i32 0, metadata !20, metadata !"function", metadata !"function", metadata !6, i32 6, metadata !87, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !90, i32 6} ; [ DW_TAG_subprogram ]
+!86 = metadata !{i32 786478, metadata !6, metadata !20, metadata !"function", metadata !"function", metadata !"", i32 6, metadata !87, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !90, i32 6} ; [ DW_TAG_subprogram ]
 !87 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !88, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !88 = metadata !{null, metadata !25, metadata !89}
 !89 = metadata !{i32 786498, null, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !20} ; [ DW_TAG_rvalue_reference_type ]
 !90 = metadata !{metadata !91}
 !91 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ]
-!92 = metadata !{i32 786478, metadata !"", i32 0, metadata !20, metadata !"~function", metadata !"~function", metadata !6, i32 6, metadata !93, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !95, i32 6} ; [ DW_TAG_subprogram ]
+!92 = metadata !{i32 786478, metadata !6, metadata !20, metadata !"~function", metadata !"~function", metadata !"", i32 6, metadata !93, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !95, i32 6} ; [ DW_TAG_subprogram ]
 !93 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !94, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !94 = metadata !{null, metadata !25}
 !95 = metadata !{metadata !96}
@@ -178,20 +178,20 @@ entry:
 !100 = metadata !{null}
 !101 = metadata !{metadata !102}
 !102 = metadata !{i32 786468}                     ; [ DW_TAG_base_type ]
-!103 = metadata !{i32 786478, metadata !"_ZN17BPLFunctionWriter9writeExprEv", i32 0, metadata !10, metadata !"writeExpr", metadata !"writeExpr", metadata !6, i32 17, metadata !7, i1 false, i1 false, i32 0, i32 0, null, i32 257, i1 false, null, null, i32 0, metadata !104, i32 17} ; [ DW_TAG_subprogram ]
+!103 = metadata !{i32 786478, metadata !6, metadata !10, metadata !"writeExpr", metadata !"writeExpr", metadata !"_ZN17BPLFunctionWriter9writeExprEv", i32 17, metadata !7, i1 false, i1 false, i32 0, i32 0, null, i32 257, i1 false, null, null, i32 0, metadata !104, i32 17} ; [ DW_TAG_subprogram ]
 !104 = metadata !{metadata !105}
 !105 = metadata !{i32 786468}                     ; [ DW_TAG_base_type ]
-!106 = metadata !{i32 786478, metadata !"_ZN8functionIFvvEEC2IZN17BPLFunctionWriter9writeExprEvE3$_1_0EET_", i32 0, null, metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !6, i32 8, metadata !59, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%class.function*)* @"_ZN8functionIFvvEEC2IZN17BPLFunctionWriter9writeExprEvE3$_1_0EET_", metadata !82, metadata !58, metadata !1, i32 8} ; [ DW_TAG_subprogram ]
-!107 = metadata !{i32 786478, metadata !"_ZN13_Base_manager21_M_not_empty_functionIZN17BPLFunctionWriter9writeExprEvE3$_1_0EEvRKT_", i32 0, null, metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !6, i32 3, metadata !108, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%class.anon.0*)* @"_ZN13_Base_manager21_M_not_empty_functionIZN17BPLFunctionWriter9writeExprEvE3$_1_0EEvRKT_", metadata !111, metadata !113, metadata !1, i32 3} ; [ DW_TAG_subprogram ]
+!106 = metadata !{i32 786478, metadata !6, null, metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !"_ZN8functionIFvvEEC2IZN17BPLFunctionWriter9writeExprEvE3$_1_0EET_", i32 8, metadata !59, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%class.function*)* @"_ZN8functionIFvvEEC2IZN17BPLFunctionWriter9writeExprEvE3$_1_0EET_", metadata !82, metadata !58, metadata !1, i32 8} ; [ DW_TAG_subprogram ]
+!107 = metadata !{i32 786478, metadata !6, null, metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !"_ZN13_Base_manager21_M_not_empty_functionIZN17BPLFunctionWriter9writeExprEvE3$_1_0EEvRKT_", i32 3, metadata !108, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%class.anon.0*)* @"_ZN13_Base_manager21_M_not_empty_functionIZN17BPLFunctionWriter9writeExprEvE3$_1_0EEvRKT_", metadata !111, metadata !113, metadata !1, i32 3} ; [ DW_TAG_subprogram ]
 !108 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !109, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !109 = metadata !{null, metadata !110}
 !110 = metadata !{i32 786448, null, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !61} ; [ DW_TAG_reference_type ]
 !111 = metadata !{metadata !112}
 !112 = metadata !{i32 786479, null, metadata !"_Tp", metadata !61, null, i32 0, i32 0} ; [ DW_TAG_template_type_parameter ]
-!113 = metadata !{i32 786478, metadata !"_ZN13_Base_manager21_M_not_empty_functionIZN17BPLFunctionWriter9writeExprEvE3$_1_0EEvRKT_", i32 0, metadata !114, metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !6, i32 3, metadata !108, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, metadata !111, i32 0, metadata !124, i32 3} ; [ DW_TAG_subprogram ]
-!114 = metadata !{i32 786434, null, metadata !"_Base_manager", metadata !6, i32 1, i64 8, i64 8, i32 0, i32 0, null, metadata !115, i32 0, null, null} ; [ DW_TAG_class_type ]
+!113 = metadata !{i32 786478, metadata !6, metadata !114, metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:23:36> >", metadata !"_ZN13_Base_manager21_M_not_empty_functionIZN17BPLFunctionWriter9writeExprEvE3$_1_0EEvRKT_", i32 3, metadata !108, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, metadata !111, i32 0, metadata !124, i32 3} ; [ DW_TAG_subprogram ]
+!114 = metadata !{i32 786434, metadata !160, null, metadata !"_Base_manager", i32 1, i64 8, i64 8, i32 0, i32 0, null, metadata !115, i32 0, null, null} ; [ DW_TAG_class_type ]
 !115 = metadata !{metadata !116, metadata !113}
-!116 = metadata !{i32 786478, metadata !"_ZN13_Base_manager21_M_not_empty_functionIZN17BPLFunctionWriter9writeExprEvE3$_0EEvRKT_", i32 0, metadata !114, metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !6, i32 3, metadata !117, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, metadata !120, i32 0, metadata !122, i32 3} ; [ DW_TAG_subprogram ]
+!116 = metadata !{i32 786478, metadata !6, metadata !114, metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !"_ZN13_Base_manager21_M_not_empty_functionIZN17BPLFunctionWriter9writeExprEvE3$_0EEvRKT_", i32 3, metadata !117, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, metadata !120, i32 0, metadata !122, i32 3} ; [ DW_TAG_subprogram ]
 !117 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !118, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !118 = metadata !{null, metadata !119}
 !119 = metadata !{i32 786448, null, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !26} ; [ DW_TAG_reference_type ]
@@ -201,12 +201,12 @@ entry:
 !123 = metadata !{i32 786468}                     ; [ DW_TAG_base_type ]
 !124 = metadata !{metadata !125}
 !125 = metadata !{i32 786468}                     ; [ DW_TAG_base_type ]
-!126 = metadata !{i32 786478, metadata !"_ZN8functionIFvvEEC2IZN17BPLFunctionWriter9writeExprEvE3$_0EET_", i32 0, null, metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !6, i32 8, metadata !23, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%class.function*)* @"_ZN8functionIFvvEEC2IZN17BPLFunctionWriter9writeExprEvE3$_0EET_", metadata !47, metadata !22, metadata !1, i32 8} ; [ DW_TAG_subprogram ]
-!127 = metadata !{i32 786478, metadata !"_ZN13_Base_manager21_M_not_empty_functionIZN17BPLFunctionWriter9writeExprEvE3$_0EEvRKT_", i32 0, null, metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !6, i32 3, metadata !117, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%class.anon*)* @"_ZN13_Base_manager21_M_not_empty_functionIZN17BPLFunctionWriter9writeExprEvE3$_0EEvRKT_", metadata !120, metadata !116, metadata !1, i32 3} ; [ DW_TAG_subprogram ]
+!126 = metadata !{i32 786478, metadata !6, null, metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !"function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !"_ZN8functionIFvvEEC2IZN17BPLFunctionWriter9writeExprEvE3$_0EET_", i32 8, metadata !23, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%class.function*)* @"_ZN8functionIFvvEEC2IZN17BPLFunctionWriter9writeExprEvE3$_0EET_", metadata !47, metadata !22, metadata !1, i32 8} ; [ DW_TAG_subprogram ]
+!127 = metadata !{i32 786478, metadata !6, null, metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !"_M_not_empty_function<BPLFunctionWriter::<lambda at BPLFunctionWriter2.ii:20:36> >", metadata !"_ZN13_Base_manager21_M_not_empty_functionIZN17BPLFunctionWriter9writeExprEvE3$_0EEvRKT_", i32 3, metadata !117, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%class.anon*)* @"_ZN13_Base_manager21_M_not_empty_functionIZN17BPLFunctionWriter9writeExprEvE3$_0EEvRKT_", metadata !120, metadata !116, metadata !1, i32 3} ; [ DW_TAG_subprogram ]
 !128 = metadata !{metadata !130}
-!130 = metadata !{i32 786484, i32 0, metadata !114, metadata !"__stored_locally", metadata !"__stored_locally", metadata !"__stored_locally", metadata !6, i32 2, metadata !131, i32 1, i32 1, i1 true} ; [ DW_TAG_variable ]
-!131 = metadata !{i32 786470, null, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !132} ; [ DW_TAG_const_type ]
-!132 = metadata !{i32 786468, null, metadata !"bool", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ]
+!130 = metadata !{i32 786484, i32 0, metadata !114, metadata !"__stored_locally", metadata !"__stored_locally", metadata !"__stored_locally", metadata !6, i32 2, metadata !131, i32 1, i32 1, i1 true, null} ; [ DW_TAG_variable ]
+!131 = metadata !{i32 786470, null, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, metadata !132} ; [ DW_TAG_const_type ]
+!132 = metadata !{i32 786468, null, null, metadata !"bool", i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ]
 !133 = metadata !{i32 786689, metadata !5, metadata !"this", metadata !6, i32 16777235, metadata !134, i32 64, i32 0} ; [ DW_TAG_arg_variable ]
 !134 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ]
 !135 = metadata !{i32 19, i32 39, metadata !5, null}
@@ -233,4 +233,6 @@ entry:
 !156 = metadata !{i32 10, i32 13, metadata !155, null}
 !157 = metadata !{i32 4, i32 5, metadata !158, null}
 !158 = metadata !{i32 786443, metadata !127, i32 3, i32 105, metadata !6, i32 4} ; [ DW_TAG_lexical_block ]
-!159 = metadata !{i32 786473, metadata !"BPLFunctionWriter.cpp", metadata !"/home/peter/crashdelta", null} ; [ DW_TAG_file_type ]
+!159 = metadata !{i32 786473, metadata !161} ; [ DW_TAG_file_type ]
+!160 = metadata !{metadata !"BPLFunctionWriter2.ii", metadata !"/home/peter/crashdelta"}
+!161 = metadata !{metadata !"BPLFunctionWriter.cpp", metadata !"/home/peter/crashdelta"}
diff --git a/test/DebugInfo/X86/pr13303.ll b/test/DebugInfo/X86/pr13303.ll
index 63ddfa7..338c576 100644
--- a/test/DebugInfo/X86/pr13303.ll
+++ b/test/DebugInfo/X86/pr13303.ll
@@ -14,13 +14,14 @@ entry:
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.2 (trunk 160143)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/probinson/PR13303.c] [DW_LANG_C99]
+!0 = metadata !{i32 786449, metadata !12, i32 12, metadata !"clang version 3.2 (trunk 160143)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/probinson/PR13303.c] [DW_LANG_C99]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main, null, null, metadata !1, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [main]
-!6 = metadata !{i32 786473, metadata !"PR13303.c", metadata !"/home/probinson", null} ; [ DW_TAG_file_type ]
-!7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = metadata !{i32 786478, metadata !12, metadata !6, metadata !"main", metadata !"main", metadata !"", i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main, null, null, metadata !1, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [main]
+!6 = metadata !{i32 786473, metadata !12} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !8 = metadata !{metadata !9}
-!9 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
 !10 = metadata !{i32 1, i32 14, metadata !11, null}
-!11 = metadata !{i32 786443, metadata !6, metadata !5, i32 1, i32 12, i32 0} ; [ DW_TAG_lexical_block ] [/home/probinson/PR13303.c]
+!11 = metadata !{i32 786443, metadata !12, metadata !5, i32 1, i32 12, i32 0} ; [ DW_TAG_lexical_block ] [/home/probinson/PR13303.c]
+!12 = metadata !{metadata !"PR13303.c", metadata !"/home/probinson"}
diff --git a/test/DebugInfo/X86/pr9951.ll b/test/DebugInfo/X86/pr9951.ll
index cb348e2..db60fb1 100644
--- a/test/DebugInfo/X86/pr9951.ll
+++ b/test/DebugInfo/X86/pr9951.ll
@@ -8,13 +8,14 @@ entry:
 !llvm.dbg.cu = !{!2}
 !6 = metadata !{metadata !0}
 
-!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"f", metadata !"f", metadata !"", metadata !1, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 ()* @f, null, null, null, i32 1} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 786473, metadata !"/home/espindola/llvm/test.c", metadata !"/home/espindola/llvm/build-rust2", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, i32 0, i32 12, metadata !"/home/espindola/llvm/test.c", metadata !"/home/espindola/llvm/build-rust2", metadata !"clang version 3.0 ()", i1 true, i1 false, metadata !"", i32 0, null, null, metadata !6, null} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 786478, metadata !7, metadata !1, metadata !"f", metadata !"f", metadata !"", i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 ()* @f, null, null, null, i32 1} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786473, metadata !7} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 786449, metadata !7, i32 12, metadata !"clang version 3.0 ()", i1 true, metadata !"", i32 0, metadata !8, metadata !8, metadata !6, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !7, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-
+!5 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!7 = metadata !{metadata !"/home/espindola/llvm/test.c", metadata !"/home/espindola/llvm/build-rust2"}
+!8 = metadata !{i32 0}
 
 ; CHECK:      _f:                                     ## @f
 ; CHECK-NEXT: Ltmp0:
diff --git a/test/DebugInfo/X86/prologue-stack.ll b/test/DebugInfo/X86/prologue-stack.ll
index 00ee7a0..57d164a 100644
--- a/test/DebugInfo/X86/prologue-stack.ll
+++ b/test/DebugInfo/X86/prologue-stack.ll
@@ -20,14 +20,15 @@ declare i32 @callme(i32)
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.2 (trunk 164980) (llvm/trunk 164979)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/bar.c] [DW_LANG_C99]
+!0 = metadata !{i32 786449, metadata !13, i32 12, metadata !"clang version 3.2 (trunk 164980) (llvm/trunk 164979)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/bar.c] [DW_LANG_C99]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, metadata !6, metadata !"isel_line_test2", metadata !"isel_line_test2", metadata !"", metadata !6, i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @isel_line_test2, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 4] [isel_line_test2]
-!6 = metadata !{i32 786473, metadata !"bar.c", metadata !"/usr/local/google/home/echristo/tmp", null} ; [ DW_TAG_file_type ]
-!7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!5 = metadata !{i32 786478, metadata !13, metadata !6, metadata !"isel_line_test2", metadata !"isel_line_test2", metadata !"", i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @isel_line_test2, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 4] [isel_line_test2]
+!6 = metadata !{i32 786473, metadata !13} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !8 = metadata !{metadata !9}
-!9 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
 !10 = metadata !{i32 5, i32 3, metadata !11, null}
-!11 = metadata !{i32 786443, metadata !6, metadata !5, i32 4, i32 1, i32 0} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/bar.c]
+!11 = metadata !{i32 786443, metadata !13, metadata !5, i32 4, i32 1, i32 0} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/bar.c]
 !12 = metadata !{i32 6, i32 3, metadata !11, null}
+!13 = metadata !{metadata !"bar.c", metadata !"/usr/local/google/home/echristo/tmp"}
diff --git a/test/DebugInfo/X86/reference-argument.ll b/test/DebugInfo/X86/reference-argument.ll
new file mode 100644
index 0000000..00846b3
--- /dev/null
+++ b/test/DebugInfo/X86/reference-argument.ll
@@ -0,0 +1,102 @@
+; RUN: llc -O0 -mtriple=x86_64-apple-darwin -filetype=asm %s -o - | FileCheck %s
+; ModuleID = 'aggregate-indirect-arg.cpp'
+; extracted from debuginfo-tests/aggregate-indirect-arg.cpp
+
+; v should not be a pointer.
+; CHECK: ##DEBUG_VALUE: foo:v <- RSI
+; rdar://problem/13658587
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.9.0"
+
+%class.SVal = type { i8*, i32 }
+%class.A = type { i8 }
+
+declare void @_Z3barR4SVal(%class.SVal* %v)
+declare void @llvm.dbg.declare(metadata, metadata) #1
+declare i32 @main()
+; Function Attrs: nounwind ssp uwtable
+define linkonce_odr void @_ZN1A3fooE4SVal(%class.A* %this, %class.SVal* %v) nounwind ssp uwtable align 2 {
+entry:
+  %this.addr = alloca %class.A*, align 8
+  store %class.A* %this, %class.A** %this.addr, align 8
+  call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !59), !dbg !61
+  call void @llvm.dbg.declare(metadata !{%class.SVal* %v}, metadata !62), !dbg !61
+  %this1 = load %class.A** %this.addr
+  call void @_Z3barR4SVal(%class.SVal* %v), !dbg !61
+  ret void, !dbg !61
+}
+declare void @_ZN4SValD1Ev(%class.SVal* %this)
+declare void @_ZN4SValD2Ev(%class.SVal* %this)
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!47}
+
+!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.4 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [aggregate-indirect-arg.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{metadata !"aggregate-indirect-arg.cpp", metadata !""}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4, metadata !29, metadata !33, metadata !34, metadata !35}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"bar", metadata !"bar", metadata !"_Z3barR4SVal", i32 19, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%class.SVal*)* @_Z3barR4SVal, null, null, metadata !2, i32 19} ; [ DW_TAG_subprogram ] [line 19] [def] [bar]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [aggregate-indirect-arg.cpp]
+!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{null, metadata !8}
+!8 = metadata !{i32 786448, null, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !9} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from SVal]
+!9 = metadata !{i32 786434, metadata !1, null, metadata !"SVal", i32 12, i64 128, i64 64, i32 0, i32 0, null, metadata !10, i32 0, null, null} ; [ DW_TAG_class_type ] [SVal] [line 12, size 128, align 64, offset 0] [def] [from ]
+!10 = metadata !{metadata !11, metadata !14, metadata !16, metadata !21, metadata !23}
+!11 = metadata !{i32 786445, metadata !1, metadata !9, metadata !"Data", i32 15, i64 64, i64 64, i64 0, i32 0, metadata !12} ; [ DW_TAG_member ] [Data] [line 15, size 64, align 64, offset 0] [from ]
+!12 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !13} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
+!13 = metadata !{i32 786470, null, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from ]
+!14 = metadata !{i32 786445, metadata !1, metadata !9, metadata !"Kind", i32 16, i64 32, i64 32, i64 64, i32 0, metadata !15} ; [ DW_TAG_member ] [Kind] [line 16, size 32, align 32, offset 64] [from unsigned int]
+!15 = metadata !{i32 786468, null, null, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] [unsigned int] [line 0, size 32, align 32, offset 0, enc DW_ATE_unsigned]
+!16 = metadata !{i32 786478, metadata !1, metadata !9, metadata !"~SVal", metadata !"~SVal", metadata !"", i32 14, metadata !17, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !20, i32 14} ; [ DW_TAG_subprogram ] [line 14] [~SVal]
+!17 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !18, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!18 = metadata !{null, metadata !19}
+!19 = metadata !{i32 786447, i32 0, i32 0, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from SVal]
+!20 = metadata !{i32 786468}
+!21 = metadata !{i32 786478, metadata !1, metadata !9, metadata !"SVal", metadata !"SVal", metadata !"", i32 12, metadata !17, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !22, i32 12} ; [ DW_TAG_subprogram ] [line 12] [SVal]
+!22 = metadata !{i32 786468}
+!23 = metadata !{i32 786478, metadata !1, metadata !9, metadata !"SVal", metadata !"SVal", metadata !"", i32 12, metadata !24, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !28, i32 12} ; [ DW_TAG_subprogram ] [line 12] [SVal]
+!24 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !25, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!25 = metadata !{null, metadata !19, metadata !26}
+!26 = metadata !{i32 786448, null, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !27} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from ]
+!27 = metadata !{i32 786470, null, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, metadata !9} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from SVal]
+!28 = metadata !{i32 786468}
+!29 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"main", metadata !"main", metadata !"", i32 25, metadata !30, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, metadata !2, i32 25} ; [ DW_TAG_subprogram ] [line 25] [def] [main]
+!30 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !31, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!31 = metadata !{metadata !32}
+!32 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!33 = metadata !{i32 786478, metadata !1, null, metadata !"~SVal", metadata !"~SVal", metadata !"_ZN4SValD1Ev", i32 14, metadata !17, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%class.SVal*)* @_ZN4SValD1Ev, null, metadata !16, metadata !2, i32 14} ; [ DW_TAG_subprogram ] [line 14] [def] [~SVal]
+!34 = metadata !{i32 786478, metadata !1, null, metadata !"~SVal", metadata !"~SVal", metadata !"_ZN4SValD2Ev", i32 14, metadata !17, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%class.SVal*)* @_ZN4SValD2Ev, null, metadata !16, metadata !2, i32 14} ; [ DW_TAG_subprogram ] [line 14] [def] [~SVal]
+!35 = metadata !{i32 786478, metadata !1, null, metadata !"foo", metadata !"foo", metadata !"_ZN1A3fooE4SVal", i32 22, metadata !36, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%class.A*, %class.SVal*)* @_ZN1A3fooE4SVal, null, metadata !41, metadata !2, i32 22} ; [ DW_TAG_subprogram ] [line 22] [def] [foo]
+!36 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !37, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!37 = metadata !{null, metadata !38, metadata !9}
+!38 = metadata !{i32 786447, i32 0, i32 0, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !39} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from A]
+!39 = metadata !{i32 786434, metadata !1, null, metadata !"A", i32 20, i64 8, i64 8, i32 0, i32 0, null, metadata !40, i32 0, null, null} ; [ DW_TAG_class_type ] [A] [line 20, size 8, align 8, offset 0] [def] [from ]
+!40 = metadata !{metadata !41, metadata !43}
+!41 = metadata !{i32 786478, metadata !1, metadata !39, metadata !"foo", metadata !"foo", metadata !"_ZN1A3fooE4SVal", i32 22, metadata !36, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null, i32 0, metadata !42, i32 22} ; [ DW_TAG_subprogram ] [line 22] [foo]
+!42 = metadata !{i32 786468}
+!43 = metadata !{i32 786478, metadata !1, metadata !39, metadata !"A", metadata !"A", metadata !"", i32 20, metadata !44, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !46, i32 20} ; [ DW_TAG_subprogram ] [line 20] [A]
+!44 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !45, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!45 = metadata !{null, metadata !38}
+!46 = metadata !{i32 786468}
+!47 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}
+!48 = metadata !{i32 786689, metadata !4, metadata !"v", metadata !5, i32 16777235, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [v] [line 19]
+!49 = metadata !{i32 19, i32 0, metadata !4, null}
+!50 = metadata !{i32 786688, metadata !29, metadata !"v", metadata !5, i32 26, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [v] [line 26]
+!51 = metadata !{i32 26, i32 0, metadata !29, null}
+!52 = metadata !{i32 27, i32 0, metadata !29, null}
+!53 = metadata !{i32 28, i32 0, metadata !29, null}
+!54 = metadata !{i32 786688, metadata !29, metadata !"a", metadata !5, i32 29, metadata !39, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [a] [line 29]
+!55 = metadata !{i32 29, i32 0, metadata !29, null}
+!56 = metadata !{i32 30, i32 0, metadata !29, null}
+!57 = metadata !{i32 31, i32 0, metadata !29, null}
+!58 = metadata !{i32 32, i32 0, metadata !29, null}
+!59 = metadata !{i32 786689, metadata !35, metadata !"this", metadata !5, i32 16777238, metadata !60, i32 1088, i32 0} ; [ DW_TAG_arg_variable ] [this] [line 22]
+!60 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !39} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from A]
+!61 = metadata !{i32 22, i32 0, metadata !35, null}
+!62 = metadata !{i32 786689, metadata !35, metadata !"v", metadata !5, i32 33554454, metadata !9, i32 8192, i32 0} ; [ DW_TAG_arg_variable ] [v] [line 22]
+!63 = metadata !{i32 786689, metadata !33, metadata !"this", metadata !5, i32 16777230, metadata !64, i32 1088, i32 0} ; [ DW_TAG_arg_variable ] [this] [line 14]
+!64 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from SVal]
+!65 = metadata !{i32 14, i32 0, metadata !33, null}
+!66 = metadata !{i32 786689, metadata !34, metadata !"this", metadata !5, i32 16777230, metadata !64, i32 1088, i32 0} ; [ DW_TAG_arg_variable ] [this] [line 14]
+!67 = metadata !{i32 14, i32 0, metadata !34, null}
diff --git a/test/DebugInfo/X86/rvalue-ref.ll b/test/DebugInfo/X86/rvalue-ref.ll
index b5aa4f6..d4f69fe 100644
--- a/test/DebugInfo/X86/rvalue-ref.ll
+++ b/test/DebugInfo/X86/rvalue-ref.ll
@@ -22,18 +22,18 @@ declare i32 @printf(i8*, ...)
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.2 (trunk 157054) (llvm/trunk 157060)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !16, i32 4, metadata !"clang version 3.2 (trunk 157054) (llvm/trunk 157060)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, metadata !6, metadata !"foo", metadata !"foo", metadata !"_Z3fooOi", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32*)* @_Z3fooOi, null, null, metadata !1, i32 5} ; [ DW_TAG_subprogram ]
+!5 = metadata !{i32 786478, metadata !16, metadata !6, metadata !"foo", metadata !"foo", metadata !"_Z3fooOi", i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32*)* @_Z3fooOi, null, null, metadata !1, i32 5} ; [ DW_TAG_subprogram ]
 !6 = metadata !{i32 786473, metadata !16} ; [ DW_TAG_file_type ]
-!7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!7 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{null, metadata !9}
 !9 = metadata !{i32 786498, null, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_rvalue_reference_type ]
-!10 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!10 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !11 = metadata !{i32 786689, metadata !5, metadata !"i", metadata !6, i32 16777220, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
 !12 = metadata !{i32 4, i32 17, metadata !5, null}
 !13 = metadata !{i32 6, i32 3, metadata !14, null}
-!14 = metadata !{i32 786443, metadata !6, metadata !5, i32 5, i32 1, i32 0} ; [ DW_TAG_lexical_block ]
+!14 = metadata !{i32 786443, metadata !16, metadata !5, i32 5, i32 1, i32 0} ; [ DW_TAG_lexical_block ]
 !15 = metadata !{i32 7, i32 1, metadata !14, null}
 !16 = metadata !{metadata !"foo.cpp", metadata !"/Users/echristo/tmp"}
diff --git a/test/DebugInfo/X86/stmt-list-multiple-compile-units.ll b/test/DebugInfo/X86/stmt-list-multiple-compile-units.ll
index 620478a..a0bed16 100644
--- a/test/DebugInfo/X86/stmt-list-multiple-compile-units.ll
+++ b/test/DebugInfo/X86/stmt-list-multiple-compile-units.ll
@@ -49,17 +49,16 @@ entry:
 
 !llvm.dbg.cu = !{!0, !10}
 !0 = metadata !{i32 786449, metadata !23, i32 12, metadata !"clang version 3.3", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{metadata !2}
-!2 = metadata !{i32 0}
+!1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, metadata !23, metadata !"test", metadata !"test", metadata !"", metadata !6, i32 2, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32)* @test, null, null, metadata !1, i32 3} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 3] [test]
+!5 = metadata !{i32 786478, metadata !23, metadata !6, metadata !"test", metadata !"test", metadata !"", i32 2, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32)* @test, null, null, metadata !1, i32 3} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 3] [test]
 !6 = metadata !{i32 786473, metadata !23} ; [ DW_TAG_file_type ]
-!7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !8 = metadata !{metadata !9, metadata !9}
-!9 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
 !10 = metadata !{i32 786449, metadata !24, i32 12, metadata !"clang version 3.3 (trunk 172862)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !11, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
 !11 = metadata !{metadata !13}
-!13 = metadata !{i32 786478, metadata !24, metadata !"fn", metadata !"fn", metadata !"", metadata !14, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32)* @fn, null, null, metadata !1, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [fn]
+!13 = metadata !{i32 786478, metadata !24, metadata !14, metadata !"fn", metadata !"fn", metadata !"", i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32)* @fn, null, null, metadata !1, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [fn]
 !14 = metadata !{i32 786473, metadata !24} ; [ DW_TAG_file_type ]
 !15 = metadata !{i32 786689, metadata !5, metadata !"a", metadata !6, i32 16777218, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [a] [line 2]
 !16 = metadata !{i32 2, i32 0, metadata !5, null}
diff --git a/test/DebugInfo/X86/stmt-list.ll b/test/DebugInfo/X86/stmt-list.ll
index 4c8521f..c3a456e 100644
--- a/test/DebugInfo/X86/stmt-list.ll
+++ b/test/DebugInfo/X86/stmt-list.ll
@@ -13,8 +13,9 @@ entry:
 !llvm.dbg.cu = !{!2}
 !5 = metadata !{metadata !0}
 
-!0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"f", metadata !"f", metadata !"", metadata !1, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void ()* @f, null, null, null, i32 1} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 786473, metadata !"test2.c", metadata !"/home/espindola/llvm", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, i32 0, i32 12, metadata !"test2.c", metadata !"/home/espindola/llvm", metadata !"clang version 3.0 ()", i1 true, i1 true, metadata !"", i32 0, null, null, metadata !5, null} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 786478, metadata !6, metadata !1, metadata !"f", metadata !"f", metadata !"", i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void ()* @f, null, null, null, i32 1} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786473, metadata !6} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 786449, metadata !6, i32 12, metadata !"clang version 3.0 ()", i1 true, metadata !"", i32 0, metadata !4, metadata !4, metadata !5, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !6, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{null}
+!6 = metadata !{metadata !"test2.c", metadata !"/home/espindola/llvm"}
diff --git a/test/DebugInfo/X86/struct-loc.ll b/test/DebugInfo/X86/struct-loc.ll
index 76cb1f7..fb990b2 100644
--- a/test/DebugInfo/X86/struct-loc.ll
+++ b/test/DebugInfo/X86/struct-loc.ll
@@ -13,7 +13,7 @@
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.1 (trunk 152837) (llvm/trunk 152845)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3,  metadata !3, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !11, i32 12, metadata !"clang version 3.1 (trunk 152837) (llvm/trunk 152845)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3,  metadata !3, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
 !5 = metadata !{i32 786484, i32 0, null, metadata !"f", metadata !"f", metadata !"", metadata !6, i32 5, metadata !7, i32 0, i32 1, %struct.foo* @f, null} ; [ DW_TAG_variable ]
diff --git a/test/DebugInfo/X86/subreg.ll b/test/DebugInfo/X86/subreg.ll
index c7f8638..9aa6e54 100644
--- a/test/DebugInfo/X86/subreg.ll
+++ b/test/DebugInfo/X86/subreg.ll
@@ -20,11 +20,12 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !9 = metadata !{metadata !1}
 
 !0 = metadata !{i32 786689, metadata !1, metadata !"zzz", metadata !2, i32 16777219, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"f", metadata !"f", metadata !"", metadata !2, i32 3, metadata !4, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i16 (i16)* @f, null, null, null, i32 3} ; [ DW_TAG_subprogram ]
-!2 = metadata !{i32 786473, metadata !"/home/espindola/llvm/test.c", metadata !"/home/espindola/tmpfs/build", metadata !3} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786449, i32 12, metadata !2, metadata !"clang version 3.0 ()", i1 false, metadata !"", i32 0, null, null, metadata !9, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
-!4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !5, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!1 = metadata !{i32 786478, metadata !10, metadata !2, metadata !"f", metadata !"f", metadata !"", i32 3, metadata !4, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i16 (i16)* @f, null, null, null, i32 3} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 786473, metadata !10} ; [ DW_TAG_file_type ]
+!3 = metadata !{i32 786449, metadata !10, i32 12, metadata !"clang version 3.0 ()", i1 false, metadata !"", i32 0, metadata !5, metadata !5, metadata !9, null,  null, metadata !""} ; [ DW_TAG_compile_unit ]
+!4 = metadata !{i32 786453, metadata !10, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !5, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{null}
-!6 = metadata !{i32 786468, metadata !3, metadata !"short", null, i32 0, i64 16, i64 16, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786468, null, metadata !3, metadata !"short", i32 0, i64 16, i64 16, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !7 = metadata !{i32 4, i32 22, metadata !8, null}
-!8 = metadata !{i32 786443, metadata !2, metadata !1, i32 3, i32 19, i32 0} ; [ DW_TAG_lexical_block ]
+!8 = metadata !{i32 786443, metadata !10, metadata !1, i32 3, i32 19, i32 0} ; [ DW_TAG_lexical_block ]
+!10 = metadata !{metadata !"/home/espindola/llvm/test.c", metadata !"/home/espindola/tmpfs/build"}
diff --git a/test/DebugInfo/X86/template.ll b/test/DebugInfo/X86/template.ll
index 817bdc9..f80dd5c 100644
--- a/test/DebugInfo/X86/template.ll
+++ b/test/DebugInfo/X86/template.ll
@@ -4,13 +4,20 @@
 ; RUN: llvm-dwarfdump %t | FileCheck %s
 
 ; IR generated with `clang++ -g -emit-llvm -S` from the following code:
-; template<int, int* x>  func() { }
-; int glbl = func<3, &glbl>();
+; template<int x, int*, template<typename> class y, int ...z>  int func() { return 3; }
+; template<typename> struct y_impl { struct nested { }; };
+; int glbl = func<3, &glbl, y_impl, 1, 2>();
+; y_impl<int>::nested n;
 
 ; CHECK: [[INT:0x[0-9a-f]*]]:{{ *}}DW_TAG_base_type
 ; CHECK-NEXT: DW_AT_name{{.*}} = "int"
 
-; CHECK: DW_AT_name{{.*}}"func<3, &glbl>"
+; CHECK: DW_TAG_structure_type
+; CHECK-NEXT: DW_AT_name{{.*}}"y_impl<int>"
+; CHECK-NOT: NULL
+; CHECK: DW_TAG_template_type_parameter
+
+; CHECK: DW_AT_name{{.*}}"func<3, &glbl, y_impl, 1, 2>"
 ; CHECK-NOT: NULL
 ; CHECK: DW_TAG_template_value_parameter
 ; CHECK-NEXT: DW_AT_type{{.*}}=> {[[INT]]}
@@ -29,56 +36,93 @@
 ; the value immediately, rather than indirecting through the address.
 
 ; CHECK-NEXT: DW_AT_location [DW_FORM_block1]{{ *}}(<0x0a> 03 00 00 00 00 00 00 00 00 9f )
+; CHECK-NOT: NULL
+
+; CHECK: DW_TAG_GNU_template_template_param
+; CHECK-NEXT: DW_AT_name{{.*}}= "y"
+; CHECK-NEXT: DW_AT_GNU_template_name{{.*}}= "y_impl"
+; CHECK-NOT: NULL
+
+; CHECK: DW_TAG_GNU_template_parameter_pack
+; CHECK-NOT: NULL
+; CHECK: DW_TAG_template_value_parameter
+; CHECK-NEXT: DW_AT_type{{.*}}=> {[[INT]]}
+; CHECK-NEXT: DW_AT_const_value  [DW_FORM_data4]{{.*}}(0x00000001)
+; CHECK-NOT: NULL
+; CHECK: DW_TAG_template_value_parameter
+; CHECK-NEXT: DW_AT_type{{.*}}=> {[[INT]]}
+; CHECK-NEXT: DW_AT_const_value  [DW_FORM_data4]{{.*}}(0x00000002)
 
 ; CHECK: [[INTPTR]]:{{ *}}DW_TAG_pointer_type
 ; CHECK-NEXT: DW_AT_type{{.*}} => {[[INT]]}
 
+%"struct.y_impl<int>::nested" = type { i8 }
+
 @glbl = global i32 0, align 4
+@n = global %"struct.y_impl<int>::nested" zeroinitializer, align 1
 @llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }]
 
 define internal void @__cxx_global_var_init() section ".text.startup" {
 entry:
-  %call = call i32 @_Z4funcILi3EXadL_Z4glblEEEiv(), !dbg !20
-  store i32 %call, i32* @glbl, align 4, !dbg !20
-  ret void, !dbg !20
+  %call = call i32 @_Z4funcILi3EXadL_Z4glblEE6y_implJLi1ELi2EEEiv(), !dbg !37
+  store i32 %call, i32* @glbl, align 4, !dbg !37
+  ret void, !dbg !37
 }
 
 ; Function Attrs: nounwind uwtable
-define linkonce_odr i32 @_Z4funcILi3EXadL_Z4glblEEEiv() #0 {
+define linkonce_odr i32 @_Z4funcILi3EXadL_Z4glblEE6y_implJLi1ELi2EEEiv() #0 {
 entry:
-  ret i32 3, !dbg !21
+  ret i32 3, !dbg !38
 }
 
 define internal void @_GLOBAL__I_a() section ".text.startup" {
 entry:
-  call void @__cxx_global_var_init(), !dbg !22
-  ret void, !dbg !22
+  call void @__cxx_global_var_init(), !dbg !39
+  ret void, !dbg !39
 }
 
-attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
 
 !llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!36}
 
-!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.4 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !18, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/blaikie/dev/scratch/templ.cpp] [DW_LANG_C_plus_plus]
-!1 = metadata !{metadata !"templ.cpp", metadata !"/usr/local/google/home/blaikie/dev/scratch"}
+!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.4 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !23, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/templ.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{metadata !"templ.cpp", metadata !"/tmp"}
 !2 = metadata !{i32 0}
-!3 = metadata !{metadata !4, metadata !8, metadata !16}
-!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"__cxx_global_var_init", metadata !"__cxx_global_var_init", metadata !"", i32 2, metadata !6, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @__cxx_global_var_init, null, null, metadata !2, i32 2} ; [ DW_TAG_subprogram ] [line 2] [local] [def] [__cxx_global_var_init]
-!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [/usr/local/google/home/blaikie/dev/scratch/templ.cpp]
+!3 = metadata !{metadata !4, metadata !8, metadata !21}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"__cxx_global_var_init", metadata !"__cxx_global_var_init", metadata !"", i32 3, metadata !6, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @__cxx_global_var_init, null, null, metadata !2, i32 3} ; [ DW_TAG_subprogram ] [line 3] [local] [def] [__cxx_global_var_init]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [/tmp/templ.cpp]
 !6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !7 = metadata !{null}
-!8 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"func<3, &glbl>", metadata !"func<3, &glbl>", metadata !"_Z4funcILi3EXadL_Z4glblEEEiv", i32 1, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @_Z4funcILi3EXadL_Z4glblEEEiv, metadata !12, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [func<3, &glbl>]
+!8 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"func<3, &glbl, y_impl, 1, 2>", metadata !"func<3, &glbl, y_impl, 1, 2>", metadata !"_Z4funcILi3EXadL_Z4glblEE6y_implJLi1ELi2EEEiv", i32 1, metadata !9, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @_Z4funcILi3EXadL_Z4glblEE6y_implJLi1ELi2EEEiv, metadata !12, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [func<3, &glbl, y_impl, 1, 2>]
 !9 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !10, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !10 = metadata !{metadata !11}
 !11 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!12 = metadata !{metadata !13, metadata !14}
+!12 = metadata !{metadata !13, metadata !14, metadata !16, metadata !17}
 !13 = metadata !{i32 786480, null, metadata !"x", metadata !11, i32 3, null, i32 0, i32 0} ; [ DW_TAG_template_value_parameter ]
 !14 = metadata !{i32 786480, null, metadata !"", metadata !15, i32* @glbl, null, i32 0, i32 0} ; [ DW_TAG_template_value_parameter ]
 !15 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
-!16 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"_GLOBAL__I_a", metadata !"_GLOBAL__I_a", metadata !"", i32 1, metadata !17, i1 true, i1 true, i32 0, i32 0, null, i32 64, i1 false, void ()* @_GLOBAL__I_a, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [local] [def] [_GLOBAL__I_a]
-!17 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!18 = metadata !{metadata !19}
-!19 = metadata !{i32 786484, i32 0, null, metadata !"glbl", metadata !"glbl", metadata !"", metadata !5, i32 2, metadata !11, i32 0, i32 1, i32* @glbl, null} ; [ DW_TAG_variable ] [glbl] [line 2] [def]
-!20 = metadata !{i32 2, i32 0, metadata !4, null}
-!21 = metadata !{i32 1, i32 0, metadata !8, null}
-!22 = metadata !{i32 1, i32 0, metadata !16, null}
+!16 = metadata !{i32 803078, null, metadata !"y", null, metadata !"y_impl", null, i32 0, i32 0} ; [ DW_TAG_GNU_template_template_param ]
+!17 = metadata !{i32 803079, null, metadata !"z", null, metadata !18, null, i32 0, i32 0} ; [ DW_TAG_GNU_template_parameter_pack ]
+!18 = metadata !{metadata !19, metadata !20}
+!19 = metadata !{i32 786480, null, metadata !"", metadata !11, i32 1, null, i32 0, i32 0} ; [ DW_TAG_template_value_parameter ]
+!20 = metadata !{i32 786480, null, metadata !"", metadata !11, i32 2, null, i32 0, i32 0} ; [ DW_TAG_template_value_parameter ]
+!21 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"_GLOBAL__I_a", metadata !"_GLOBAL__I_a", metadata !"", i32 1, metadata !22, i1 true, i1 true, i32 0, i32 0, null, i32 64, i1 false, void ()* @_GLOBAL__I_a, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [local] [def] [_GLOBAL__I_a]
+!22 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!23 = metadata !{metadata !24, metadata !25}
+!24 = metadata !{i32 786484, i32 0, null, metadata !"glbl", metadata !"glbl", metadata !"", metadata !5, i32 3, metadata !11, i32 0, i32 1, i32* @glbl, null} ; [ DW_TAG_variable ] [glbl] [line 3] [def]
+!25 = metadata !{i32 786484, i32 0, null, metadata !"n", metadata !"n", metadata !"", metadata !5, i32 4, metadata !26, i32 0, i32 1, %"struct.y_impl<int>::nested"* @n, null} ; [ DW_TAG_variable ] [n] [line 4] [def]
+!26 = metadata !{i32 786451, metadata !1, metadata !27, metadata !"nested", i32 2, i64 8, i64 8, i32 0, i32 0, null, metadata !30, i32 0, null, null} ; [ DW_TAG_structure_type ] [nested] [line 2, size 8, align 8, offset 0] [def] [from ]
+!27 = metadata !{i32 786451, metadata !1, null, metadata !"y_impl<int>", i32 2, i64 8, i64 8, i32 0, i32 0, null, null, i32 0, null, metadata !28} ; [ DW_TAG_structure_type ] [y_impl<int>] [line 2, size 8, align 8, offset 0] [def] [from ]
+!28 = metadata !{metadata !29}
+!29 = metadata !{i32 786479, null, metadata !"", metadata !11, null, i32 0, i32 0} ; [ DW_TAG_template_type_parameter ]
+!30 = metadata !{metadata !31}
+!31 = metadata !{i32 786478, metadata !1, metadata !26, metadata !"nested", metadata !"nested", metadata !"", i32 2, metadata !32, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !35, i32 2} ; [ DW_TAG_subprogram ] [line 2] [nested]
+!32 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !33, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!33 = metadata !{null, metadata !34}
+!34 = metadata !{i32 786447, i32 0, i32 0, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !26} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from nested]
+!35 = metadata !{i32 786468}
+!36 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}
+!37 = metadata !{i32 3, i32 0, metadata !4, null}
+!38 = metadata !{i32 1, i32 0, metadata !8, null}
+!39 = metadata !{i32 1, i32 0, metadata !21, null}
diff --git a/test/DebugInfo/X86/tls-fission.ll b/test/DebugInfo/X86/tls-fission.ll
new file mode 100644
index 0000000..b95ff40
--- /dev/null
+++ b/test/DebugInfo/X86/tls-fission.ll
@@ -0,0 +1,31 @@
+; RUN: llc -split-dwarf=Enable -mtriple=x86_64-linux -O0 -filetype=asm < %s | FileCheck %s
+
+; FIXME: add relocation and DWARF expression support to llvm-dwarfdump & use
+; that here instead of raw assembly printing
+
+; CHECK: debug_info.dwo
+; 3 bytes of data in this DW_FORM_block1 representation of the location of 'tls'
+; CHECK: .byte 3{{ *}}# DW_AT_location
+; DW_OP_const_index (0xfx == 252) to refer to the debug_addr table
+; CHECK-NEXT: .byte 252
+; an index of zero into the debug_addr table
+; CHECK-NEXT: .byte 0
+; DW_OP_lo_user based on GCC/GDB extension presumably (by experiment) to support TLS
+; CHECK-NEXT: .byte 224
+; check that the expected TLS address description is the first thing in the debug_addr section
+; CHECK: debug_addr
+; CHECK-NEXT: .quad	tls@DTPOFF
+
+@tls = thread_local global i32 0, align 4
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7}
+
+!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.4 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !2, metadata !3, metadata !2, metadata !"tls.dwo"} ; [ DW_TAG_compile_unit ] [/tmp/tls.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{metadata !"tls.cpp", metadata !"/tmp"}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786484, i32 0, null, metadata !"tls", metadata !"tls", metadata !"", metadata !5, i32 1, metadata !6, i32 0, i32 1, i32* @tls, null} ; [ DW_TAG_variable ] [tls] [line 1] [def]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [/tmp/tls.cpp]
+!6 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!7 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}
diff --git a/test/DebugInfo/X86/tls.ll b/test/DebugInfo/X86/tls.ll
new file mode 100644
index 0000000..e2a9af9
--- /dev/null
+++ b/test/DebugInfo/X86/tls.ll
@@ -0,0 +1,34 @@
+; RUN: llc -mtriple=x86_64-linux -O0 -filetype=asm < %s | FileCheck %s
+; RUN: llc -mtriple=i386-linux -O0 -filetype=asm < %s | FileCheck --check-prefix=CHECK-32 %s
+
+; FIXME: add relocation and DWARF expression support to llvm-dwarfdump & use
+; that here instead of raw assembly printing
+
+; 10 bytes of data in this DW_FORM_block1 representation of the location of 'tls'
+; CHECK: .byte	10{{ *}}# DW_AT_location
+; DW_OP_const8u (0x0e == 14) of adress
+; CHECK: .byte	14
+; The debug relocation of the address of the tls variable
+; CHECK: .quad	tls@DTPOFF
+; DW_OP_lo_user based on GCC/GDB extension presumably (by experiment) to support TLS
+; CHECK: .byte	224
+
+; same again, except with a 32 bit address
+; CHECK-32: .byte	6{{ *}}# DW_AT_location
+; CHECK-32: .byte	12
+; CHECK-32: .long	tls@DTPOFF
+; CHECK-32: .byte	224
+
+@tls = thread_local global i32 7, align 4
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!7}
+
+!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.4 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !2, metadata !3, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/tls.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{metadata !"tls.cpp", metadata !"/tmp"}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786484, i32 0, null, metadata !"tls", metadata !"tls", metadata !"", metadata !5, i32 1, metadata !6, i32 0, i32 1, i32* @tls, null} ; [ DW_TAG_variable ] [tls] [line 1] [def]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [/tmp/tls.cpp]
+!6 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!7 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}
diff --git a/test/DebugInfo/X86/vector.ll b/test/DebugInfo/X86/vector.ll
index 658303a..0f33032 100644
--- a/test/DebugInfo/X86/vector.ll
+++ b/test/DebugInfo/X86/vector.ll
@@ -11,7 +11,7 @@
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.3 (trunk 171825) (llvm/trunk 171822)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3,  metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/Users/echristo/foo.c] [DW_LANG_C99]
+!0 = metadata !{i32 786449, metadata !12, i32 12, metadata !"clang version 3.3 (trunk 171825) (llvm/trunk 171822)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3,  metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/Users/echristo/foo.c] [DW_LANG_C99]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
 !5 = metadata !{i32 786484, i32 0, null, metadata !"a", metadata !"a", metadata !"", metadata !6, i32 3, metadata !7, i32 0, i32 1, <4 x i32>* @a, null} ; [ DW_TAG_variable ] [a] [line 3] [def]
diff --git a/test/DebugInfo/X86/vla.ll b/test/DebugInfo/X86/vla.ll
new file mode 100644
index 0000000..81faec7
--- /dev/null
+++ b/test/DebugInfo/X86/vla.ll
@@ -0,0 +1,104 @@
+; RUN: llc -O0 -mtriple=x86_64-apple-darwin -filetype=asm %s -o - | FileCheck %s
+; Ensure that we generate a breg+0 location for the variable length array a.
+; CHECK: ##DEBUG_VALUE: vla:a <- [RDX+0]
+; rdar://problem/13658587
+;
+; generated from:
+;
+; int vla(int n) {
+;   int a[n];
+;   a[0] = 42;
+;   return a[n-1];
+; }
+;
+; int main(int argc, char** argv) {
+;    return vla(argc);
+; }
+
+; ModuleID = 'vla.c'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+; Function Attrs: nounwind ssp uwtable
+define i32 @vla(i32 %n) nounwind ssp uwtable {
+entry:
+  %n.addr = alloca i32, align 4
+  %saved_stack = alloca i8*
+  %cleanup.dest.slot = alloca i32
+  store i32 %n, i32* %n.addr, align 4
+  call void @llvm.dbg.declare(metadata !{i32* %n.addr}, metadata !15), !dbg !16
+  %0 = load i32* %n.addr, align 4, !dbg !17
+  %1 = zext i32 %0 to i64, !dbg !17
+  %2 = call i8* @llvm.stacksave(), !dbg !17
+  store i8* %2, i8** %saved_stack, !dbg !17
+  %vla = alloca i32, i64 %1, align 16, !dbg !17
+  call void @llvm.dbg.declare(metadata !{i32* %vla}, metadata !18), !dbg !17
+  %arrayidx = getelementptr inbounds i32* %vla, i64 0, !dbg !22
+  store i32 42, i32* %arrayidx, align 4, !dbg !22
+  %3 = load i32* %n.addr, align 4, !dbg !23
+  %sub = sub nsw i32 %3, 1, !dbg !23
+  %idxprom = sext i32 %sub to i64, !dbg !23
+  %arrayidx1 = getelementptr inbounds i32* %vla, i64 %idxprom, !dbg !23
+  %4 = load i32* %arrayidx1, align 4, !dbg !23
+  store i32 1, i32* %cleanup.dest.slot
+  %5 = load i8** %saved_stack, !dbg !24
+  call void @llvm.stackrestore(i8* %5), !dbg !24
+  ret i32 %4, !dbg !23
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
+
+; Function Attrs: nounwind
+declare i8* @llvm.stacksave() nounwind
+
+; Function Attrs: nounwind
+declare void @llvm.stackrestore(i8*) nounwind
+
+; Function Attrs: nounwind ssp uwtable
+define i32 @main(i32 %argc, i8** %argv) nounwind ssp uwtable {
+entry:
+  %retval = alloca i32, align 4
+  %argc.addr = alloca i32, align 4
+  %argv.addr = alloca i8**, align 8
+  store i32 0, i32* %retval
+  store i32 %argc, i32* %argc.addr, align 4
+  call void @llvm.dbg.declare(metadata !{i32* %argc.addr}, metadata !25), !dbg !26
+  store i8** %argv, i8*** %argv.addr, align 8
+  call void @llvm.dbg.declare(metadata !{i8*** %argv.addr}, metadata !27), !dbg !26
+  %0 = load i32* %argc.addr, align 4, !dbg !28
+  %call = call i32 @vla(i32 %0), !dbg !28
+  ret i32 %call, !dbg !28
+}
+
+!llvm.dbg.cu = !{!0}
+
+!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/vla.c] [DW_LANG_C99]
+!1 = metadata !{metadata !"vla.c", metadata !""}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4, metadata !9}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"vla", metadata !"vla", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32)* @vla, null, null, metadata !2, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [vla]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [/vla.c]
+!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{metadata !8, metadata !8}
+!8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"main", metadata !"main", metadata !"", i32 7, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32, i8**)* @main, null, null, metadata !2, i32 7} ; [ DW_TAG_subprogram ] [line 7] [def] [main]
+!10 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!11 = metadata !{metadata !8, metadata !8, metadata !12}
+!12 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !13} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
+!13 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char]
+!14 = metadata !{i32 786468, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
+!15 = metadata !{i32 786689, metadata !4, metadata !"n", metadata !5, i32 16777217, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [n] [line 1]
+!16 = metadata !{i32 1, i32 0, metadata !4, null}
+!17 = metadata !{i32 2, i32 0, metadata !4, null}
+!18 = metadata !{i32 786688, metadata !4, metadata !"a", metadata !5, i32 2, metadata !19, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [a] [line 2]
+!19 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 0, i64 32, i32 0, i32 0, metadata !8, metadata !20, i32 0, i32 0} ; [ DW_TAG_array_type ] [line 0, size 0, align 32, offset 0] [from int]
+!20 = metadata !{metadata !21}
+!21 = metadata !{i32 786465, i64 0, i64 -1}       ; [ DW_TAG_subrange_type ] [unbounded]
+!22 = metadata !{i32 3, i32 0, metadata !4, null}
+!23 = metadata !{i32 4, i32 0, metadata !4, null}
+!24 = metadata !{i32 5, i32 0, metadata !4, null}
+!25 = metadata !{i32 786689, metadata !9, metadata !"argc", metadata !5, i32 16777223, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [argc] [line 7]
+!26 = metadata !{i32 7, i32 0, metadata !9, null}
+!27 = metadata !{i32 786689, metadata !9, metadata !"argv", metadata !5, i32 33554439, metadata !12, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [argv] [line 7]
+!28 = metadata !{i32 8, i32 0, metadata !9, null}
diff --git a/test/DebugInfo/array.ll b/test/DebugInfo/array.ll
index 7dd57d7..f6556fc 100644
--- a/test/DebugInfo/array.ll
+++ b/test/DebugInfo/array.ll
@@ -14,15 +14,15 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!2}
 
-!0 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @main, null, null, null, i32 3} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786478, metadata !14, metadata !1, metadata !"main", metadata !"main", metadata !"", i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @main, null, null, null, i32 3} ; [ DW_TAG_subprogram ]
 !1 = metadata !{i32 786473, metadata !14} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.0 (trunk 129138)", i1 false, metadata !"", i32 0, null, null, metadata !13, null,  null, null} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!2 = metadata !{i32 786449, metadata !14, i32 12, metadata !"clang version 3.0 (trunk 129138)", i1 false, metadata !"", i32 0, metadata !15, metadata !15, metadata !13, null,  null, null} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 786453, metadata !14, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !6 = metadata !{i32 786688, metadata !7, metadata !"a", metadata !1, i32 4, metadata !8, i32 0, null} ; [ DW_TAG_auto_variable ]
-!7 = metadata !{i32 786443, metadata !1, metadata !0, i32 3, i32 12, i32 0} ; [ DW_TAG_lexical_block ]
-!8 = metadata !{i32 786433, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 32, i32 0, i32 0, metadata !5, metadata !9, i32 0, i32 0} ; [ DW_TAG_array_type ]
+!7 = metadata !{i32 786443, metadata !14, metadata !0, i32 3, i32 12, i32 0} ; [ DW_TAG_lexical_block ]
+!8 = metadata !{i32 786433, metadata !14, metadata !2, metadata !"", i32 0, i64 0, i64 32, i32 0, i32 0, metadata !5, metadata !9, i32 0, i32 0} ; [ DW_TAG_array_type ]
 !9 = metadata !{metadata !10}
 ;CHECK: DW_TAG_subrange_type
 ;CHECK-NEXT: DW_AT_type
@@ -34,3 +34,4 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 !12 = metadata !{i32 5, i32 3, metadata !7, null}
 !13 = metadata !{metadata !0}
 !14 = metadata !{metadata !"array.c", metadata !"/private/tmp"}
+!15 = metadata !{i32 0}
diff --git a/test/DebugInfo/bug_null_debuginfo.ll b/test/DebugInfo/bug_null_debuginfo.ll
index b17affe..06436f9 100644
--- a/test/DebugInfo/bug_null_debuginfo.ll
+++ b/test/DebugInfo/bug_null_debuginfo.ll
@@ -2,4 +2,5 @@
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{null, null, null}
+!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"", i1 false, metadata !"", i32 0, null, null, null,  null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{metadata !"t", metadata !""}
diff --git a/test/DebugInfo/dwarf-public-names.ll b/test/DebugInfo/dwarf-public-names.ll
index 5d33048..0733c1b 100644
--- a/test/DebugInfo/dwarf-public-names.ll
+++ b/test/DebugInfo/dwarf-public-names.ll
@@ -86,7 +86,7 @@ attributes #1 = { nounwind readnone }
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 4, metadata !4, metadata !"clang version 3.3 (http://llvm.org/git/clang.git a09cd8103a6a719cb2628cdf0c91682250a17bd2) (http://llvm.org/git/llvm.git 47d03cec0afca0c01ae42b82916d1d731716cd20)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !2, metadata !24,  metadata !24, metadata !""} ; [ DW_TAG_compile_unit ] [/usr2/kparzysz/s.hex/t/dwarf-public-names.cpp] [DW_LANG_C_plus_plus]
+!0 = metadata !{i32 786449, metadata !37, i32 4, metadata !"clang version 3.3 (http://llvm.org/git/clang.git a09cd8103a6a719cb2628cdf0c91682250a17bd2) (http://llvm.org/git/llvm.git 47d03cec0afca0c01ae42b82916d1d731716cd20)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !2, metadata !24,  metadata !24, metadata !""} ; [ DW_TAG_compile_unit ] [/usr2/kparzysz/s.hex/t/dwarf-public-names.cpp] [DW_LANG_C_plus_plus]
 !1 = metadata !{i32 0}
 !2 = metadata !{metadata !3, metadata !18, metadata !19, metadata !20}
 !3 = metadata !{i32 786478, metadata !4, null, metadata !"member_function", metadata !"member_function", metadata !"_ZN1C15member_functionEv", i32 9, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%struct.C*)* @_ZN1C15member_functionEv, null, metadata !12, metadata !1, i32 9} ; [ DW_TAG_subprogram ] [line 9] [def] [member_function]
diff --git a/test/DebugInfo/dwarfdump-debug-loc-simple.test b/test/DebugInfo/dwarfdump-debug-loc-simple.test
new file mode 100644
index 0000000..77dfa25
--- /dev/null
+++ b/test/DebugInfo/dwarfdump-debug-loc-simple.test
@@ -0,0 +1,26 @@
+RUN: llvm-dwarfdump %p/Inputs/dwarfdump-test-loc-list-32bit.elf.o | FileCheck %s
+Note: the input file was generated from Inputs/dwarfdump-test-loc-list-32bit.elf.cpp
+
+CHECK: .debug_info
+CHECK: DW_AT_name{{.*}}"f"
+CHECK: DW_AT_location{{.*}}([[F_LOC:0x[0-9a-f]*]])
+CHECK: DW_AT_name{{.*}}"g"
+CHECK: DW_AT_location{{.*}}([[G_LOC:0x[0-9a-f]*]])
+CHECK: .debug_loc contents:
+CHECK-NEXT: [[F_LOC]]: Beginning address offset: 0x0000000000000000
+CHECK-NEXT:               Ending address offset: 0x0000000000000023
+this is actually the wrong location due to PR14763, but that doesn't matter for
+the purposes of testing dwarfdump
+CHECK-NEXT:                Location description: 51
+CHECK-NEXT: {{^$}}
+CHECK-NEXT:            Beginning address offset: 0x0000000000000023
+CHECK-NEXT:               Ending address offset: 0x000000000000005d
+CHECK-NEXT:                Location description: 75 70
+CHECK-NEXT: {{^$}}
+CHECK-NEXT: [[G_LOC]]: Beginning address offset: 0x0000000000000000
+CHECK-NEXT:               Ending address offset: 0x0000000000000020
+CHECK-NEXT:               Location description: 50
+CHECK-NEXT: {{^$}}
+CHECK-NEXT:            Beginning address offset: 0x0000000000000020
+CHECK-NEXT:               Ending address offset: 0x000000000000005d
+CHECK-NEXT:                Location description: 75 74
diff --git a/test/DebugInfo/enum.ll b/test/DebugInfo/enum.ll
new file mode 100644
index 0000000..59a303e
--- /dev/null
+++ b/test/DebugInfo/enum.ll
@@ -0,0 +1,79 @@
+; REQUIRES: object-emission
+
+; RUN: llc -O0 -filetype=obj < %s > %t
+; RUN: llvm-dwarfdump %t | FileCheck %s
+
+; IR generated from the following code compiled with clang -g:
+; enum e1 { I, J = 0xffffffffU, K = 0xf000000000000000ULL } a;
+; enum e2 { X };
+; void func() {
+;   int b = X;
+; }
+
+; These values were previously being truncated to -1 and 0 respectively.
+
+; CHECK: debug_info contents
+; CHECK: DW_TAG_enumeration_type
+; CHECK-NEXT: DW_AT_name{{.*}} = "e1"
+; CHECK-NOT: NULL
+; CHECK: DW_TAG_enumerator
+; CHECK-NOT: NULL
+; CHECK: DW_TAG_enumerator
+; CHECK-NEXT: DW_AT_name{{.*}} = "J"
+; CHECK-NEXT: DW_AT_const_value [DW_FORM_sdata]     (4294967295)
+; CHECK-NOT: NULL
+; CHECK: DW_TAG_enumerator
+; CHECK-NEXT: DW_AT_name{{.*}} = "K"
+; CHECK-NEXT: DW_AT_const_value [DW_FORM_sdata]     (-1152921504606846976)
+
+; Check that we retain enums that aren't referenced by any variables, etc
+; CHECK: DW_TAG_enumeration_type
+; CHECK-NEXT: DW_AT_name{{.*}} = "e2"
+; CHECK-NOT: NULL
+; CHECK: DW_TAG_enumerator
+; CHECK-NEXT: DW_AT_name{{.*}} = "X"
+
+@a = global i64 0, align 8
+
+; Function Attrs: nounwind uwtable
+define void @_Z4funcv() #0 {
+entry:
+  %b = alloca i32, align 4
+  call void @llvm.dbg.declare(metadata !{i32* %b}, metadata !20), !dbg !22
+  store i32 0, i32* %b, align 4, !dbg !22
+  ret void, !dbg !23
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata) #1
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!19}
+
+!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.4 ", i1 false, metadata !"", i32 0, metadata !2, metadata !11, metadata !12, metadata !17, metadata !11, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/enum.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{metadata !"enum.cpp", metadata !"/tmp"}
+!2 = metadata !{metadata !3, metadata !8}
+!3 = metadata !{i32 786436, metadata !1, null, metadata !"e1", i32 1, i64 64, i64 64, i32 0, i32 0, null, metadata !4, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] [e1] [line 1, size 64, align 64, offset 0] [def] [from ]
+!4 = metadata !{metadata !5, metadata !6, metadata !7}
+!5 = metadata !{i32 786472, metadata !"I", i64 0} ; [ DW_TAG_enumerator ] [I :: 0]
+!6 = metadata !{i32 786472, metadata !"J", i64 4294967295} ; [ DW_TAG_enumerator ] [J :: 4294967295]
+!7 = metadata !{i32 786472, metadata !"K", i64 -1152921504606846976} ; [ DW_TAG_enumerator ] [K :: 17293822569102704640]
+!8 = metadata !{i32 786436, metadata !1, null, metadata !"e2", i32 2, i64 32, i64 32, i32 0, i32 0, null, metadata !9, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] [e2] [line 2, size 32, align 32, offset 0] [def] [from ]
+!9 = metadata !{metadata !10}
+!10 = metadata !{i32 786472, metadata !"X", i64 0} ; [ DW_TAG_enumerator ] [X :: 0]
+!11 = metadata !{i32 0}
+!12 = metadata !{metadata !13}
+!13 = metadata !{i32 786478, metadata !1, metadata !14, metadata !"func", metadata !"func", metadata !"_Z4funcv", i32 3, metadata !15, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @_Z4funcv, null, null, metadata !11, i32 3} ; [ DW_TAG_subprogram ] [line 3] [def] [func]
+!14 = metadata !{i32 786473, metadata !1}         ; [ DW_TAG_file_type ] [/tmp/enum.cpp]
+!15 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !16, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!16 = metadata !{null}
+!17 = metadata !{metadata !18}
+!18 = metadata !{i32 786484, i32 0, null, metadata !"a", metadata !"a", metadata !"", metadata !14, i32 1, metadata !3, i32 0, i32 1, i64* @a, null} ; [ DW_TAG_variable ] [a] [line 1] [def]
+!19 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}
+!20 = metadata !{i32 786688, metadata !13, metadata !"b", metadata !14, i32 4, metadata !21, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [b] [line 4]
+!21 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!22 = metadata !{i32 4, i32 0, metadata !13, null}
+!23 = metadata !{i32 5, i32 0, metadata !13, null}
diff --git a/test/DebugInfo/global.ll b/test/DebugInfo/global.ll
new file mode 100644
index 0000000..b438305
--- /dev/null
+++ b/test/DebugInfo/global.ll
@@ -0,0 +1,38 @@
+; REQUIRES: object-emission
+
+; RUN: llc -O0 -filetype=obj < %s > %t
+; RUN: llvm-dwarfdump %t | FileCheck %s
+
+; generated from the following source compiled to bitcode with clang -g -O1
+; static int i;
+; int main() {
+;   (void)&i;
+; }
+
+; CHECK: debug_info contents
+; CHECK: DW_TAG_variable
+
+; Function Attrs: nounwind readnone uwtable
+define i32 @main() #0 {
+entry:
+  ret i32 0, !dbg !12
+}
+
+attributes #0 = { nounwind readnone uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!11}
+
+!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.4 ", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !9, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/global.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{metadata !"global.cpp", metadata !"/tmp"}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"main", metadata !"main", metadata !"", i32 2, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 ()* @main, null, null, metadata !2, i32 2} ; [ DW_TAG_subprogram ] [line 2] [def] [main]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [/tmp/global.cpp]
+!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{metadata !8}
+!8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = metadata !{metadata !10}
+!10 = metadata !{i32 786484, i32 0, null, metadata !"i", metadata !"i", metadata !"_ZL1i", metadata !5, i32 1, metadata !8, i32 1, i32 1, null, null}
+!11 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}
+!12 = metadata !{i32 4, i32 0, metadata !4, null}
diff --git a/test/DebugInfo/inheritance.ll b/test/DebugInfo/inheritance.ll
index a689cb2..b0665b2 100644
--- a/test/DebugInfo/inheritance.ll
+++ b/test/DebugInfo/inheritance.ll
@@ -106,46 +106,49 @@ return:                                           ; preds = %bb2
 declare void @_ZdlPv(i8*) nounwind
 
 !0 = metadata !{i32 459008, metadata !1, metadata !"tst", metadata !4, i32 13, metadata !8} ; [ DW_TAG_auto_variable ]
-!1 = metadata !{i32 458763, metadata !2, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
-!2 = metadata !{i32 458763, metadata !3, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
-!3 = metadata !{i32 458798, i32 0, metadata !4, metadata !"main", metadata !"main", metadata !"main", metadata !4, i32 11, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
-!4 = metadata !{i32 458769, i32 0, i32 4, metadata !"inheritance.cpp", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 458763, metadata !44, metadata !2, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!2 = metadata !{i32 458763, metadata !44, metadata !3, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!3 = metadata !{i32 458798, i32 0, metadata !4, metadata !"main", metadata !"main", metadata !"main", i32 11, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!4 = metadata !{i32 458769, metadata !44, i32 4, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !45, metadata !45, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !5 = metadata !{i32 458773, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !6 = metadata !{metadata !7}
-!7 = metadata !{i32 458788, metadata !4, metadata !"int", metadata !4, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!8 = metadata !{i32 458771, metadata !4, metadata !"test1", metadata !4, i32 1, i64 64, i64 64, i64 0, i32 0, null, metadata !9, i32 0, metadata !8} ; [ DW_TAG_structure_type ]
+!7 = metadata !{i32 458788, null, metadata !4, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!8 = metadata !{i32 458771, metadata !44, metadata !4, metadata !"test1", i32 1, i64 64, i64 64, i64 0, i32 0, null, metadata !9, i32 0, metadata !8} ; [ DW_TAG_structure_type ]
 !9 = metadata !{metadata !10, metadata !14, metadata !18}
-!10 = metadata !{i32 458765, metadata !8, metadata !"_vptr$test1", metadata !4, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_member ]
+!10 = metadata !{i32 458765, metadata !44, metadata !8, metadata !"_vptr$test1", i32 1, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_member ]
 !11 = metadata !{i32 458767, metadata !4, metadata !"", metadata !4, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ]
-!12 = metadata !{i32 458767, metadata !4, metadata !"__vtbl_ptr_type", metadata !13, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !5} ; [ DW_TAG_pointer_type ]
-!13 = metadata !{i32 458769, i32 0, i32 4, metadata !"<built-in>", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!14 = metadata !{i32 458798, i32 0, metadata !8, metadata !"test1", metadata !"test1", metadata !"", metadata !4, i32 1, metadata !15, i1 false, i1 false, i32 0, i32 0, null, i1 true} ; [ DW_TAG_subprogram ]
+!12 = metadata !{i32 458767, null, metadata !4, metadata !"__vtbl_ptr_type", i32 0, i64 0, i64 0, i64 0, i32 0, metadata !5} ; [ DW_TAG_pointer_type ]
+!13 = metadata !{i32 458769, metadata !46, i32 4, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !45, metadata !45, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!14 = metadata !{i32 458798, i32 0, metadata !8, metadata !"test1", metadata !"test1", metadata !"", i32 1, metadata !15, i1 false, i1 false, i32 0, i32 0, null, i1 true, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !15 = metadata !{i32 458773, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !16, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !16 = metadata !{null, metadata !17}
 !17 = metadata !{i32 458767, metadata !4, metadata !"", metadata !4, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !8} ; [ DW_TAG_pointer_type ]
-!18 = metadata !{i32 458798, i32 0, metadata !8, metadata !"~test1", metadata !"~test1", metadata !"", metadata !4, i32 4, metadata !19, i1 false, i1 false, i32 1, i32 0, metadata !8, i1 false} ; [ DW_TAG_subprogram ]
+!18 = metadata !{i32 458798, i32 0, metadata !8, metadata !"~test1", metadata !"~test1", metadata !"", i32 4, metadata !19, i1 false, i1 false, i32 1, i32 0, metadata !8, i1 false, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !19 = metadata !{i32 458773, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !20, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !20 = metadata !{null, metadata !17, metadata !7}
 !21 = metadata !{i32 11, i32 0, metadata !1, null}
 !22 = metadata !{i32 13, i32 0, metadata !1, null}
 !23 = metadata !{i32 14, i32 0, metadata !1, null}
 !24 = metadata !{i32 459009, metadata !25, metadata !"this", metadata !4, i32 13, metadata !26} ; [ DW_TAG_arg_variable ]
-!25 = metadata !{i32 458798, i32 0, metadata !4, metadata !"test1", metadata !"test1", metadata !"_ZN5test1C1Ev", metadata !4, i32 1, metadata !15, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
+!25 = metadata !{i32 458798, i32 0, metadata !4, metadata !"test1", metadata !"test1", metadata !"_ZN5test1C1Ev", i32 1, metadata !15, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !26 = metadata !{i32 458790, metadata !4, metadata !"", metadata !4, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !27} ; [ DW_TAG_const_type ]
 !27 = metadata !{i32 458767, metadata !4, metadata !"", metadata !4, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ]
 !28 = metadata !{i32 1, i32 0, metadata !25, null}
 !29 = metadata !{i32 1, i32 0, metadata !30, null}
-!30 = metadata !{i32 458763, metadata !31, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
-!31 = metadata !{i32 458763, metadata !25, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!30 = metadata !{i32 458763, metadata !44, metadata !31, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!31 = metadata !{i32 458763, metadata !44, metadata !25, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !32 = metadata !{i32 459009, metadata !33, metadata !"this", metadata !4, i32 4, metadata !26} ; [ DW_TAG_arg_variable ]
-!33 = metadata !{i32 458798, i32 0, metadata !8, metadata !"~test1", metadata !"~test1", metadata !"_ZN5test1D1Ev", metadata !4, i32 4, metadata !15, i1 false, i1 true, i32 1, i32 0, metadata !8, i1 false} ; [ DW_TAG_subprogram ]
+!33 = metadata !{i32 458798, i32 0, metadata !8, metadata !"~test1", metadata !"~test1", metadata !"_ZN5test1D1Ev", i32 4, metadata !15, i1 false, i1 true, i32 1, i32 0, metadata !8, i1 false, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !34 = metadata !{i32 4, i32 0, metadata !33, null}
 !35 = metadata !{i32 5, i32 0, metadata !36, null}
-!36 = metadata !{i32 458763, metadata !33, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!36 = metadata !{i32 458763, metadata !44, metadata !33, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !37 = metadata !{i32 6, i32 0, metadata !36, null}
 !38 = metadata !{i32 459009, metadata !39, metadata !"this", metadata !4, i32 4, metadata !26} ; [ DW_TAG_arg_variable ]
-!39 = metadata !{i32 458798, i32 0, metadata !8, metadata !"~test1", metadata !"~test1", metadata !"_ZN5test1D0Ev", metadata !4, i32 4, metadata !15, i1 false, i1 true, i32 1, i32 1, metadata !8, i1 false} ; [ DW_TAG_subprogram ]
+!39 = metadata !{i32 458798, i32 0, metadata !8, metadata !"~test1", metadata !"~test1", metadata !"_ZN5test1D0Ev", i32 4, metadata !15, i1 false, i1 true, i32 1, i32 1, metadata !8, i1 false, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !40 = metadata !{i32 4, i32 0, metadata !39, null}
 !41 = metadata !{i32 5, i32 0, metadata !42, null}
-!42 = metadata !{i32 458763, metadata !39, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!42 = metadata !{i32 458763, metadata !44, metadata !39, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !43 = metadata !{i32 6, i32 0, metadata !42, null}
+!44 = metadata !{metadata !"inheritance.cpp", metadata !"/tmp/"}
+!45 = metadata !{i32 0}
+!46 = metadata !{metadata !"<built-in>", metadata !"/tmp/"}
diff --git a/test/DebugInfo/inlined-arguments.ll b/test/DebugInfo/inlined-arguments.ll
index d3ece10..50a9068 100644
--- a/test/DebugInfo/inlined-arguments.ll
+++ b/test/DebugInfo/inlined-arguments.ll
@@ -1,3 +1,5 @@
+; REQUIRES: object-emission
+
 ; RUN: llc -filetype=obj < %s > %t
 ; RUN: llvm-dwarfdump %t | FileCheck %s
 
diff --git a/test/DebugInfo/inlined-vars.ll b/test/DebugInfo/inlined-vars.ll
index 841daaa..cd98e1d 100644
--- a/test/DebugInfo/inlined-vars.ll
+++ b/test/DebugInfo/inlined-vars.ll
@@ -17,15 +17,15 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.2 (trunk 159419)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !26, i32 4, metadata !"clang version 3.2 (trunk 159419)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5, metadata !10}
-!5 = metadata !{i32 786478, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 10, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 ()* @main, null, null, metadata !1, i32 10} ; [ DW_TAG_subprogram ]
+!5 = metadata !{i32 786478, metadata !26, metadata !6, metadata !"main", metadata !"main", metadata !"", i32 10, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 ()* @main, null, null, metadata !1, i32 10} ; [ DW_TAG_subprogram ]
 !6 = metadata !{i32 786473, metadata !26} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, null, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{metadata !9}
 !9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!10 = metadata !{i32 786478, metadata !6, metadata !"f", metadata !"f", metadata !"_ZL1fi", metadata !6, i32 3, metadata !11, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !13, i32 3} ; [ DW_TAG_subprogram ]
+!10 = metadata !{i32 786478, metadata !26, metadata !6, metadata !"f", metadata !"f", metadata !"_ZL1fi", i32 3, metadata !11, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !13, i32 3} ; [ DW_TAG_subprogram ]
 !11 = metadata !{i32 786453, null, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !12 = metadata !{metadata !9, metadata !9}
 !13 = metadata !{metadata !14}
diff --git a/test/DebugInfo/llvm-symbolizer.test b/test/DebugInfo/llvm-symbolizer.test
index 9a7b365..4dc3699 100644
--- a/test/DebugInfo/llvm-symbolizer.test
+++ b/test/DebugInfo/llvm-symbolizer.test
@@ -3,11 +3,12 @@ RUN: echo "%p/Inputs/dwarfdump-test.elf-x86-64 0x400436" >> %t.input
 RUN: echo "%p/Inputs/dwarfdump-test4.elf-x86-64 0x62c" >> %t.input
 RUN: echo "%p/Inputs/dwarfdump-inl-test.elf-x86-64 0x710" >> %t.input
 RUN: echo "\"%p/Inputs/dwarfdump-test3.elf-x86-64 space\" 0x633" >> %t.input
+RUN: echo "%p/Inputs/macho-universal 0x1f84" >> %t.input
+RUN: echo "%p/Inputs/macho-universal:i386 0x1f67" >> %t.input
+RUN: echo "%p/Inputs/macho-universal:x86_64 0x100000f05" >> %t.input
 
-RUN: llvm-symbolizer --functions --inlining --demangle=false < %t.input \
-RUN:    | FileCheck %s
-
-REQUIRES: shell
+RUN: llvm-symbolizer --functions --inlining --demangle=false \
+RUN:    --default-arch=i386 < %t.input | FileCheck %s
 
 CHECK:       main
 CHECK-NEXT: /tmp/dbginfo{{[/\\]}}dwarfdump-test.cc:16
@@ -29,5 +30,16 @@ CHECK-NEXT: dwarfdump-inl-test.cc:
 CHECK:       _Z3do1v
 CHECK-NEXT: dwarfdump-test3-decl.h:7
 
+CHECK:      main
+CHECK:      _Z3inci
+CHECK:      _Z3inci
+
 RUN: echo "unexisting-file 0x1234" > %t.input2
 RUN: llvm-symbolizer < %t.input2
+
+RUN: echo "%p/Inputs/macho-universal 0x1f84" > %t.input3
+RUN: llvm-symbolizer < %t.input3 | FileCheck %s --check-prefix=UNKNOWN-ARCH
+
+UNKNOWN-ARCH-NOT: main
+UNKNOWN-ARCH: ??
+UNKNOWN-ARCH-NOT: main
diff --git a/test/DebugInfo/member-pointers.ll b/test/DebugInfo/member-pointers.ll
index 20f4e68..7d999f1 100644
--- a/test/DebugInfo/member-pointers.ll
+++ b/test/DebugInfo/member-pointers.ll
@@ -22,7 +22,7 @@
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3,  metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/home/blaikie/Development/scratch/simple.cpp] [DW_LANG_C_plus_plus]
+!0 = metadata !{i32 786449, metadata !15, i32 4, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3,  metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/home/blaikie/Development/scratch/simple.cpp] [DW_LANG_C_plus_plus]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5, metadata !10}
 !5 = metadata !{i32 786484, i32 0, null, metadata !"x", metadata !"x", metadata !"", metadata !6, i32 4, metadata !7, i32 0, i32 1, i64* @x, null} ; [ DW_TAG_variable ] [x] [line 4] [def]
diff --git a/test/DebugInfo/two-cus-from-same-file.ll b/test/DebugInfo/two-cus-from-same-file.ll
index 22cf4eb..6d8c484 100644
--- a/test/DebugInfo/two-cus-from-same-file.ll
+++ b/test/DebugInfo/two-cus-from-same-file.ll
@@ -37,30 +37,30 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !0 = metadata !{i32 786449, metadata !32, i32 12, metadata !"clang version 3.2 (trunk 156513)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, metadata !6, metadata !"foo", metadata !"foo", metadata !"", metadata !6, i32 5, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void ()* @foo, null, null, metadata !1, i32 5} ; [ DW_TAG_subprogram ]
+!5 = metadata !{i32 786478, metadata !32, metadata !6, metadata !"foo", metadata !"foo", metadata !"", i32 5, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void ()* @foo, null, null, metadata !1, i32 5} ; [ DW_TAG_subprogram ]
 !6 = metadata !{i32 786473, metadata !32} ; [ DW_TAG_file_type ]
-!7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!7 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{null}
 !9 = metadata !{i32 786449, metadata !32, i32 12, metadata !"clang version 3.2 (trunk 156513)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !10, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ]
 !10 = metadata !{metadata !12}
-!12 = metadata !{i32 786478, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 11, metadata !13, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !19, i32 11} ; [ DW_TAG_subprogram ]
-!13 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !14, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!12 = metadata !{i32 786478, metadata !32, metadata !6, metadata !"main", metadata !"main", metadata !"", i32 11, metadata !13, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !19, i32 11} ; [ DW_TAG_subprogram ]
+!13 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !14, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !14 = metadata !{metadata !15, metadata !15, metadata !16}
-!15 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!16 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !17} ; [ DW_TAG_pointer_type ]
-!17 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !18} ; [ DW_TAG_pointer_type ]
-!18 = metadata !{i32 786468, null, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!15 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!16 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !17} ; [ DW_TAG_pointer_type ]
+!17 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !18} ; [ DW_TAG_pointer_type ]
+!18 = metadata !{i32 786468, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !19 = metadata !{metadata !20}
 !20 = metadata !{metadata !21, metadata !22}
 !21 = metadata !{i32 786689, metadata !12, metadata !"argc", metadata !6, i32 16777227, metadata !15, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
 !22 = metadata !{i32 786689, metadata !12, metadata !"argv", metadata !6, i32 33554443, metadata !16, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
 !23 = metadata !{i32 6, i32 3, metadata !24, null}
-!24 = metadata !{i32 786443, metadata !5, i32 5, i32 16, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
+!24 = metadata !{i32 786443, metadata !32, metadata !5, i32 5, i32 16, i32 0} ; [ DW_TAG_lexical_block ]
 !25 = metadata !{i32 7, i32 1, metadata !24, null}
 !26 = metadata !{i32 11, i32 14, metadata !12, null}
 !27 = metadata !{i32 11, i32 26, metadata !12, null}
 !28 = metadata !{i32 12, i32 3, metadata !29, null}
-!29 = metadata !{i32 786443, metadata !12, i32 11, i32 34, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
+!29 = metadata !{i32 786443, metadata !32, metadata !12, i32 11, i32 34, i32 0} ; [ DW_TAG_lexical_block ]
 !30 = metadata !{i32 13, i32 3, metadata !29, null}
 !31 = metadata !{i32 14, i32 3, metadata !29, null}
 !32 = metadata !{metadata !"foo.c", metadata !"/tmp"}
diff --git a/test/DebugInfo/version.ll b/test/DebugInfo/version.ll
new file mode 100644
index 0000000..b36e38e
--- /dev/null
+++ b/test/DebugInfo/version.ll
@@ -0,0 +1,31 @@
+; REQUIRES: object-emission
+
+; RUN: llc -O0 -filetype=obj < %s > %t
+; RUN: llvm-dwarfdump %t | FileCheck %s
+
+; Make sure we are generating DWARF version 3 when module flag says so.
+; CHECK: Compile Unit: length = {{.*}} version = 0x0003
+
+define i32 @main() #0 {
+entry:
+  %retval = alloca i32, align 4
+  store i32 0, i32* %retval
+  ret i32 0, !dbg !10
+}
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!9}
+
+!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.4 (trunk 185475)", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{metadata !"CodeGen/dwarf-version.c", metadata !"test"}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"main", metadata !"main", metadata !"", i32 6, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, metadata !2, i32 6} ; [ DW_TAG_subprogram ] [line 6] [def] [main]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ]
+!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{metadata !8}
+!8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}
+!10 = metadata !{i32 7, i32 0, metadata !4, null}
diff --git a/test/ExecutionEngine/MCJIT/remote/test-ptr-reloc-remote.ll b/test/ExecutionEngine/MCJIT/remote/test-ptr-reloc-remote.ll
index 1a55879..bd044b6 100644
--- a/test/ExecutionEngine/MCJIT/remote/test-ptr-reloc-remote.ll
+++ b/test/ExecutionEngine/MCJIT/remote/test-ptr-reloc-remote.ll
@@ -1,5 +1,4 @@
 ; RUN: %lli_mcjit -remote-mcjit -O0 %s
-; XFAIL: mips
 
 @.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1
 @ptr = global i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), align 4
diff --git a/test/ExecutionEngine/mov64zext32.ll b/test/ExecutionEngine/mov64zext32.ll
index 482510d..f38c21a 100644
--- a/test/ExecutionEngine/mov64zext32.ll
+++ b/test/ExecutionEngine/mov64zext32.ll
@@ -15,4 +15,4 @@ good:
 
 bad:
   ret i32 1
-} 
\ No newline at end of file
+} 
diff --git a/test/ExecutionEngine/test-interp-vec-cast.ll b/test/ExecutionEngine/test-interp-vec-cast.ll
new file mode 100644
index 0000000..3f9f666
--- /dev/null
+++ b/test/ExecutionEngine/test-interp-vec-cast.ll
@@ -0,0 +1,146 @@
+; RUN: %lli -force-interpreter=true %s > /dev/null
+
+define i32 @main() {
+    zext <2 x i1> <i1 true,i1 true> to <2 x i8>
+    zext <3 x i1> <i1 true,i1 true,i1 true> to <3 x i8>
+    zext <2 x i1> <i1 true,i1 true> to <2 x i16>
+    zext <3 x i1> <i1 true,i1 true,i1 true> to <3 x i16>
+    zext <2 x i1> <i1 true,i1 true> to <2 x i32>
+    zext <3 x i1> <i1 true,i1 true,i1 true> to <3 x i32>
+    zext <2 x i1> <i1 true,i1 true> to <2 x i64>
+    zext <3 x i1> <i1 true,i1 true,i1 true> to <3 x i64>
+    zext <3 x i8> <i8 4, i8 4, i8 4> to <3 x i16>
+    zext <2 x i8> <i8 -4, i8 -4> to <2 x i16>
+    zext <3 x i8> <i8 4, i8 4, i8 4> to <3 x i32>
+    zext <2 x i8> <i8 -4, i8 -4> to <2 x i32>
+    zext <3 x i8> <i8 4, i8 4, i8 4> to <3 x i64>
+    zext <2 x i8> <i8 -4, i8 -4> to <2 x i64>
+    zext <3 x i16> <i16 4, i16 4, i16 4> to <3 x i32>
+    zext <2 x i16> <i16 -4, i16 -4> to <2 x i32>
+    zext <3 x i16> <i16 4, i16 4, i16 4> to <3 x i64>
+    zext <2 x i16> <i16 -4, i16 -4> to <2 x i64>
+    zext <3 x i32> <i32 4, i32 4, i32 4> to <3 x i64>
+    zext <2 x i32> <i32 -4, i32 -4> to <2 x i64>
+
+
+    sext <2 x i1> <i1 true,i1 true> to <2 x i8>
+    sext <3 x i1> <i1 true,i1 false,i1 true> to <3 x i8>
+    sext <2 x i1> <i1 true,i1 true> to <2 x i16>
+    sext <3 x i1> <i1 true,i1 false,i1 true> to <3 x i16>
+    sext <2 x i1> <i1 true,i1 true> to <2 x i32>
+    sext <3 x i1> <i1 true,i1 false,i1 true> to <3 x i32>
+    sext <2 x i1> <i1 true,i1 true> to <2 x i64>
+    sext <3 x i1> <i1 true,i1 false,i1 true> to <3 x i64>
+    sext <3 x i8> <i8 -4, i8 0, i8 4> to <3 x i16>
+    sext <2 x i8> <i8 -4, i8 4> to <2 x i16>
+    sext <3 x i8> <i8 -4, i8 0, i8 4> to <3 x i32>
+    sext <2 x i8> <i8 -4, i8 4> to <2 x i32>
+    sext <3 x i8> <i8 -4, i8 0, i8 4> to <3 x i64>
+    sext <2 x i8> <i8 -4, i8 4> to <2 x i64>
+    sext <3 x i16> <i16 -4, i16 0, i16 4> to <3 x i32>
+    sext <2 x i16> <i16 -4, i16 4> to <2 x i32>
+    sext <3 x i16> <i16 -4, i16 0, i16 4> to <3 x i64>
+    sext <2 x i16> <i16 -4, i16 4> to <2 x i64>
+    sext <3 x i32> <i32 -4, i32 0, i32 4> to <3 x i64>
+    sext <2 x i32> <i32 -4, i32 4> to <2 x i64>
+
+
+    uitofp <3 x i1> <i1 true,i1 false,i1 true> to <3 x float>
+    uitofp <2 x i1> <i1 true,i1 true> to <2 x double>
+    uitofp <3 x i8> <i8 -4,i8 0,i8 4> to <3 x float>
+    uitofp <2 x i8> <i8 -4,i8 4> to <2 x double>
+    uitofp <3 x i16> <i16 -4,i16 0,i16 4> to <3 x float>
+    uitofp <2 x i16> <i16 -4,i16 4> to <2 x double>
+    uitofp <3 x i32> <i32 -4,i32 0,i32 4> to <3 x float>
+    uitofp <2 x i32> <i32 -4,i32 4> to <2 x double>
+    uitofp <3 x i64> <i64 -4,i64 0,i64 4> to <3 x float>
+    uitofp <2 x i64> <i64 -4,i64 4> to <2 x double>
+
+
+    sitofp <3 x i1> <i1 true,i1 false,i1 true> to <3 x float>
+    sitofp <2 x i1> <i1 true,i1 true> to <2 x double>
+    sitofp <3 x i8> <i8 -4,i8 0,i8 4> to <3 x float>
+    sitofp <2 x i8> <i8 -4,i8 4> to <2 x double>
+    sitofp <3 x i16> <i16 -4,i16 0,i16 4> to <3 x float>
+    sitofp <2 x i16> <i16 -4,i16 4> to <2 x double>
+    sitofp <3 x i32> <i32 -4,i32 0,i32 4> to <3 x float>
+    sitofp <2 x i32> <i32 -4,i32 4> to <2 x double>
+    sitofp <3 x i64> <i64 -4,i64 0,i64 4> to <3 x float>
+    sitofp <2 x i64> <i64 -4,i64 4> to <2 x double>
+
+    trunc <2 x i16> <i16 -6, i16 6> to <2 x i8>
+    trunc <3 x i16> <i16 -6, i16 6, i16 0> to <3 x i8>
+    trunc <2 x i32> <i32 -6, i32 6> to <2 x i8>
+    trunc <3 x i32> <i32 -6, i32 6, i32 0> to <3 x i8>
+    trunc <2 x i32> <i32 -6, i32 6> to <2 x i16>
+    trunc <3 x i32> <i32 -6, i32 6, i32 0> to <3 x i16>
+    trunc <2 x i64> <i64 -6, i64 6> to <2 x i8>
+    trunc <3 x i64> <i64 -6, i64 6, i64 0> to <3 x i8>
+    trunc <2 x i64> <i64 -6, i64 6> to <2 x i16>
+    trunc <3 x i64> <i64 -6, i64 6, i64 0> to <3 x i16>
+    trunc <2 x i64> <i64 -6, i64 6> to <2 x i32>
+    trunc <3 x i64> <i64 -6, i64 6, i64 0> to <3 x i32>
+
+
+    fpext <2 x float>  < float 0.000000e+00, float 1.0> to <2 x double>
+    fpext <3 x float>  < float 0.000000e+00, float -1.0, float 1.0> to <3 x double>
+
+    fptosi <2 x double> < double 0.000000e+00, double 1.0> to <2 x i8>
+    fptosi <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i8>
+    fptosi <2 x double> < double 0.000000e+00, double 1.0> to <2 x i16>
+    fptosi <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i16>
+    fptosi <2 x double> < double 0.000000e+00, double 1.0> to <2 x i32>
+    fptosi <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i32>
+    fptosi <2 x double> < double 0.000000e+00, double 1.0> to <2 x i64>
+    fptosi <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i64>
+
+    fptoui <2 x double> < double 0.000000e+00, double 1.0> to <2 x i8>
+    fptoui <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i8>
+    fptoui <2 x double> < double 0.000000e+00, double 1.0> to <2 x i16>
+    fptoui <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i16>
+    fptoui <2 x double> < double 0.000000e+00, double 1.0> to <2 x i32>
+    fptoui <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i32>
+    fptoui <2 x double> < double 0.000000e+00, double 1.0> to <2 x i64>
+    fptoui <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x i64>
+
+    fptrunc <2 x double> < double 0.000000e+00, double 1.0> to <2 x float>
+    fptrunc <3 x double> < double 0.000000e+00, double 1.0, double -1.0> to <3 x float>
+
+    bitcast <8 x i8> <i8 0, i8 -1, i8 2, i8 -3, i8 4, i8 -5, i8 6, i8 -7> to <4 x i16>
+    bitcast <8 x i8> <i8 0, i8 -1, i8 2, i8 -3, i8 4, i8 -5, i8 6, i8 -7> to <2 x i32>
+    bitcast <8 x i8> <i8 0, i8 -1, i8 2, i8 -3, i8 4, i8 -5, i8 6, i8 -7> to i64
+    bitcast <8 x i8> <i8 0, i8 -1, i8 2, i8 -3, i8 4, i8 -5, i8 6, i8 -7> to <2 x float>
+    bitcast <8 x i8> <i8 0, i8 -1, i8 2, i8 -3, i8 4, i8 -5, i8 6, i8 -7> to double
+
+    bitcast <4 x i16> <i16 0, i16 -1, i16 2, i16 -3> to <8 x i8>
+    bitcast <4 x i16> <i16 0, i16 -1, i16 2, i16 -3> to <2 x i32>
+    bitcast <4 x i16> <i16 0, i16 -1, i16 2, i16 -3> to i64
+    bitcast <4 x i16> <i16 0, i16 -1, i16 2, i16 -3> to <2 x float>
+    bitcast <4 x i16> <i16 0, i16 -1, i16 2, i16 -3> to double
+
+    bitcast <2 x i32> <i32 1, i32 -1> to <8 x i8>
+    bitcast <2 x i32> <i32 1, i32 -1> to <4 x i16>
+    bitcast <2 x i32> <i32 1, i32 -1> to i64
+    bitcast <2 x i32> <i32 1, i32 -1> to <2 x float>
+    bitcast <2 x i32> <i32 1, i32 -1> to double
+
+    bitcast i64 1 to <8 x i8>
+    bitcast i64 1 to <4 x i16>
+    bitcast i64 1 to <2 x i32>
+    bitcast i64 1 to <2 x float>
+    bitcast i64 1 to double
+
+    bitcast <2 x float> <float 1.0, float -1.0> to <8 x i8>
+    bitcast <2 x float> <float 1.0, float -1.0> to <4 x i16>
+    bitcast <2 x float> <float 1.0, float -1.0> to i64
+    bitcast <2 x float> <float 1.0, float -1.0> to <2 x i32>
+    bitcast <2 x float> <float 1.0, float -1.0> to double
+
+    bitcast double 1.0 to <8 x i8>
+    bitcast double 1.0 to <4 x i16>
+    bitcast double 1.0 to <2 x i32>
+    bitcast double 1.0 to <2 x float>
+    bitcast double 1.0 to i64
+
+    ret i32 0
+}
diff --git a/test/ExecutionEngine/test-interp-vec-loadstore.ll b/test/ExecutionEngine/test-interp-vec-loadstore.ll
index e500711..665a135 100644
--- a/test/ExecutionEngine/test-interp-vec-loadstore.ll
+++ b/test/ExecutionEngine/test-interp-vec-loadstore.ll
@@ -1,22 +1,11 @@
 ; RUN: %lli -force-interpreter=true %s | FileCheck %s
-; XFAIL: mips
-; CHECK: 1
-; CHECK: 2
-; CHECK: 3
-; CHECK: 4
-; CHECK: 5.{{[0]+}}e+{{[0]+}}
-; CHECK: 6.{{[0]+}}e+{{[0]+}}
-; CHECK: 7.{{[0]+}}e+{{[0]+}}
-; CHECK: 8.{{[0]+}}e+{{[0]+}}
-; CHECK: 9.{{[0]+}}e+{{[0]+}}
-; CHECK: 1.{{[0]+}}e+{{[0]+}}1
-; CHECK: 1.1{{[0]+}}e+{{[0]+}}1
-; CHECK: 1.2{{[0]+}}e+{{[0]+}}1
-
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
-
-@format_i32 = internal global [4 x i8] c"%d\0A\00"
-@format_float = internal global [4 x i8] c"%e\0A\00"
+; CHECK: int test passed
+; CHECK: double test passed
+; CHECK: float test passed
+
+@msg_int = internal global [17 x i8] c"int test passed\0A\00"
+@msg_double = internal global [20 x i8] c"double test passed\0A\00"
+@msg_float = internal global [19 x i8] c"float test passed\0A\00"
 
 declare i32 @printf(i8*, ...)
 
@@ -24,62 +13,157 @@ define i32 @main() {
   %a = alloca <4 x i32>, align 16
   %b = alloca <4 x double>, align 16
   %c = alloca <4 x float>, align 16
-  
+  %pint_0 = alloca i32
+  %pint_1 = alloca i32
+  %pint_2 = alloca i32
+  %pint_3 = alloca i32
+  %pdouble_0 = alloca double
+  %pdouble_1 = alloca double
+  %pdouble_2 = alloca double
+  %pdouble_3 = alloca double
+  %pfloat_0 = alloca float
+  %pfloat_1 = alloca float
+  %pfloat_2 = alloca float
+  %pfloat_3 = alloca float
+
+  ; store constants 1,2,3,4 as vector
   store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32>* %a, align 16
+  ; store constants 1,2,3,4 as scalars
+  store i32 1, i32* %pint_0
+  store i32 2, i32* %pint_1
+  store i32 3, i32* %pint_2
+  store i32 4, i32* %pint_3
+  
+  ; load stored scalars
+  %val_int0 = load i32* %pint_0
+  %val_int1 = load i32* %pint_1
+  %val_int2 = load i32* %pint_2
+  %val_int3 = load i32* %pint_3
 
+  ; load stored vector
   %val0 = load <4 x i32> *%a, align 16
 
+  ; extract integers from the loaded vector
   %res_i32_0 = extractelement <4 x i32> %val0, i32 0
   %res_i32_1 = extractelement <4 x i32> %val0, i32 1
   %res_i32_2 = extractelement <4 x i32> %val0, i32 2
   %res_i32_3 = extractelement <4 x i32> %val0, i32 3
-  
-  %ptr0 = getelementptr [4 x i8]* @format_i32, i32 0, i32 0
-  call i32 (i8*,...)* @printf(i8* %ptr0, i32 %res_i32_0)
-  call i32 (i8*,...)* @printf(i8* %ptr0, i32 %res_i32_1)
-  call i32 (i8*,...)* @printf(i8* %ptr0, i32 %res_i32_2)
-  call i32 (i8*,...)* @printf(i8* %ptr0, i32 %res_i32_3)
 
+  ; compare extracted data with stored constants
+  %test_result_int_0 = icmp eq i32 %res_i32_0, %val_int0
+  %test_result_int_1 = icmp eq i32 %res_i32_1, %val_int1
+  %test_result_int_2 = icmp eq i32 %res_i32_2, %val_int2
+  %test_result_int_3 = icmp eq i32 %res_i32_3, %val_int3
+
+  %test_result_int_4 = icmp eq i32 %res_i32_0, %val_int3
+  %test_result_int_5 = icmp eq i32 %res_i32_1, %val_int2
+  %test_result_int_6 = icmp eq i32 %res_i32_2, %val_int1
+  %test_result_int_7 = icmp eq i32 %res_i32_3, %val_int0
+
+  ; it should be TRUE
+  %A_i = or i1 %test_result_int_0, %test_result_int_4
+  %B_i = or i1 %test_result_int_1, %test_result_int_5
+  %C_i = or i1 %test_result_int_2, %test_result_int_6
+  %D_i = or i1 %test_result_int_3, %test_result_int_7
+  %E_i = and i1 %A_i, %B_i
+  %F_i = and i1 %C_i, %D_i
+  %res_i = and i1 %E_i, %F_i
+
+  ; if TRUE print message
+  br i1 %res_i, label %Print_int, label %Double
+Print_int:
+  %ptr0 = getelementptr [17 x i8]* @msg_int, i32 0, i32 0
+  call i32 (i8*,...)* @printf(i8* %ptr0)
+  br label %Double
+Double:
   store <4 x double> <double 5.0, double 6.0, double 7.0, double 8.0>, <4 x double>* %b, align 16
+  ; store constants as scalars
+  store double 5.0, double* %pdouble_0
+  store double 6.0, double* %pdouble_1
+  store double 7.0, double* %pdouble_2
+  store double 8.0, double* %pdouble_3
 
+  ; load stored vector
   %val1 = load <4 x double> *%b, align 16
+  ; load stored scalars
+  %val_double0 = load double* %pdouble_0
+  %val_double1 = load double* %pdouble_1
+  %val_double2 = load double* %pdouble_2
+  %val_double3 = load double* %pdouble_3
 
   %res_double_0 = extractelement <4 x double> %val1, i32 0
   %res_double_1 = extractelement <4 x double> %val1, i32 1
   %res_double_2 = extractelement <4 x double> %val1, i32 2
   %res_double_3 = extractelement <4 x double> %val1, i32 3
-  
-  %ptr1 = getelementptr [4 x i8]* @format_float, i32 0, i32 0
-  call i32 (i8*,...)* @printf(i8* %ptr1, double %res_double_0)
-  call i32 (i8*,...)* @printf(i8* %ptr1, double %res_double_1)
-  call i32 (i8*,...)* @printf(i8* %ptr1, double %res_double_2)
-  call i32 (i8*,...)* @printf(i8* %ptr1, double %res_double_3)
 
+  %test_result_double_0 = fcmp oeq double %res_double_0, %val_double0
+  %test_result_double_1 = fcmp oeq double %res_double_1, %val_double1
+  %test_result_double_2 = fcmp oeq double %res_double_2, %val_double2
+  %test_result_double_3 = fcmp oeq double %res_double_3, %val_double3
+
+  %test_result_double_4 = fcmp oeq double %res_double_0, %val_double3
+  %test_result_double_5 = fcmp oeq double %res_double_1, %val_double2
+  %test_result_double_6 = fcmp oeq double %res_double_2, %val_double1
+  %test_result_double_7 = fcmp oeq double %res_double_3, %val_double0
+
+  %A_double = or i1 %test_result_double_0, %test_result_double_4
+  %B_double = or i1 %test_result_double_1, %test_result_double_5
+  %C_double = or i1 %test_result_double_2, %test_result_double_6
+  %D_double = or i1 %test_result_double_3, %test_result_double_7
+  %E_double = and i1 %A_double, %B_double
+  %F_double = and i1 %C_double, %D_double
+  %res_double = and i1 %E_double, %F_double
 
+  br i1 %res_double, label %Print_double, label %Float
+Print_double:
+  %ptr1 = getelementptr [20 x i8]* @msg_double, i32 0, i32 0
+  call i32 (i8*,...)* @printf(i8* %ptr1)
+  br label %Float
+Float:
   store <4 x float> <float 9.0, float 10.0, float 11.0, float 12.0>, <4 x float>* %c, align 16
-  
+
+  store float 9.0, float* %pfloat_0
+  store float 10.0, float* %pfloat_1
+  store float 11.0, float* %pfloat_2
+  store float 12.0, float* %pfloat_3
+
+  ; load stored vector
   %val2 = load <4 x float> *%c, align 16
-  
-  %ptr2 = getelementptr [4 x i8]* @format_float, i32 0, i32 0
+  ; load stored scalars
+  %val_float0 = load float* %pfloat_0
+  %val_float1 = load float* %pfloat_1
+  %val_float2 = load float* %pfloat_2
+  %val_float3 = load float* %pfloat_3
+
+  %res_float_0 = extractelement <4 x float> %val2, i32 0
+  %res_float_1 = extractelement <4 x float> %val2, i32 1
+  %res_float_2 = extractelement <4 x float> %val2, i32 2
+  %res_float_3 = extractelement <4 x float> %val2, i32 3
+
+  %test_result_float_0 = fcmp oeq float %res_float_0, %val_float0
+  %test_result_float_1 = fcmp oeq float %res_float_1, %val_float1
+  %test_result_float_2 = fcmp oeq float %res_float_2, %val_float2
+  %test_result_float_3 = fcmp oeq float %res_float_3, %val_float3
+
+  %test_result_float_4 = fcmp oeq float %res_float_0, %val_float3
+  %test_result_float_5 = fcmp oeq float %res_float_1, %val_float2
+  %test_result_float_6 = fcmp oeq float %res_float_2, %val_float1
+  %test_result_float_7 = fcmp oeq float %res_float_3, %val_float0
+
+  %A_float = or i1 %test_result_float_0, %test_result_float_4
+  %B_float = or i1 %test_result_float_1, %test_result_float_5
+  %C_float = or i1 %test_result_float_2, %test_result_float_6
+  %D_float = or i1 %test_result_float_3, %test_result_float_7
+  %E_float = and i1 %A_float, %B_float
+  %F_float = and i1 %C_float, %D_float
+  %res_float = and i1 %E_float, %F_float
+
+  br i1 %res_float, label %Print_float, label %Exit
+Print_float:
+  %ptr2 = getelementptr [19 x i8]* @msg_float, i32 0, i32 0
+  call i32 (i8*,...)* @printf(i8* %ptr2)
+  br label %Exit
+Exit:
 
-  ; by some reason printf doesn't print float correctly, so
-  ; floats are casted to doubles and are printed as doubles
-  
-  %res_serv_0 = extractelement <4 x float> %val2, i32 0
-  %res_float_0 = fpext float %res_serv_0 to double
-  %res_serv_1 = extractelement <4 x float> %val2, i32 1
-  %res_float_1 = fpext float %res_serv_1 to double
-  %res_serv_2 = extractelement <4 x float> %val2, i32 2
-  %res_float_2 = fpext float %res_serv_2 to double
-  %res_serv_3 = extractelement <4 x float> %val2, i32 3
-  %res_float_3 = fpext float %res_serv_3 to double
-
- 
-  call i32 (i8*,...)* @printf(i8* %ptr1, double %res_float_0)
-  call i32 (i8*,...)* @printf(i8* %ptr1, double %res_float_1)
-  call i32 (i8*,...)* @printf(i8* %ptr1, double %res_float_2)
-  call i32 (i8*,...)* @printf(i8* %ptr1, double %res_float_3)
- 
-  
   ret i32 0
 }
diff --git a/test/ExecutionEngine/test-interp-vec-shift.ll b/test/ExecutionEngine/test-interp-vec-shift.ll
new file mode 100644
index 0000000..3aa4f4e
--- /dev/null
+++ b/test/ExecutionEngine/test-interp-vec-shift.ll
@@ -0,0 +1,32 @@
+; RUN: %lli -force-interpreter=true %s > /dev/null
+
+define i32 @main() {
+    %shamt = add <2 x i8> <i8 0, i8 0>, <i8 1, i8 2>
+    %shift.upgrd.1 = zext <2 x i8> %shamt to <2 x i32>
+    %t1.s = shl <2 x i32> <i32 1, i32 2>, %shift.upgrd.1
+    %t2.s = shl <2 x i32> <i32 1, i32 2>, <i32 3, i32 4>
+    %shift.upgrd.2 = zext <2 x i8> %shamt to <2 x i32>
+    %t1 = shl <2 x i32> <i32 1, i32 2>, %shift.upgrd.2
+    %t2 = shl <2 x i32> <i32 1, i32 0>, <i32 5, i32 6>
+    %t2.s.upgrd.3 = shl <2 x i64> <i64 1, i64 2>, <i64 3, i64 4>
+    %t2.upgrd.4 = shl <2 x i64> <i64 1, i64 2>, <i64 6, i64 7>
+    %shift.upgrd.5 = zext <2 x i8> %shamt to <2 x i32>
+    %tr1.s = ashr <2 x i32> <i32 1, i32 2>, %shift.upgrd.5
+    %tr2.s = ashr <2 x i32> <i32 1, i32 2>, <i32 4, i32 5>
+    %shift.upgrd.6 = zext <2 x i8> %shamt to <2 x i32>
+    %tr1 = lshr <2 x i32> <i32 1, i32 2>, %shift.upgrd.6
+    %tr2 = lshr <2 x i32> <i32 1, i32 2>, <i32 5, i32 6>
+    %tr1.l = ashr <2 x i64> <i64 1, i64 2>, <i64 4, i64 5>
+    %shift.upgrd.7 = zext <2 x i8> %shamt to <2 x i64>
+    %tr2.l = ashr <2 x i64> <i64 1, i64 2>, %shift.upgrd.7
+    %tr3.l = shl <2 x i64> <i64 1, i64 2>, <i64 4, i64 5>
+    %shift.upgrd.8 = zext <2 x i8> %shamt to <2 x i64>
+    %tr4.l = shl <2 x i64> <i64 1, i64 2>, %shift.upgrd.8
+    %tr1.u = lshr <2 x i64> <i64 1, i64 2>, <i64 5, i64 6>
+    %shift.upgrd.9 = zext <2 x i8> %shamt to <2 x i64>
+    %tr2.u = lshr <2 x i64> <i64 1, i64 2>, %shift.upgrd.9
+    %tr3.u = shl <2 x i64> <i64 1, i64 2>, <i64 5, i64 6>
+    %shift.upgrd.10 = zext <2 x i8> %shamt to <2 x i64>
+    %tr4.u = shl <2 x i64> <i64 1, i64 2>, %shift.upgrd.10
+    ret i32 0
+}
diff --git a/test/Feature/md_on_instruction.ll b/test/Feature/md_on_instruction.ll
index da9e49e..8599601 100644
--- a/test/Feature/md_on_instruction.ll
+++ b/test/Feature/md_on_instruction.ll
@@ -17,6 +17,8 @@ declare void @llvm.dbg.func.start(metadata) nounwind readnone
 declare void @llvm.dbg.region.end(metadata) nounwind readnone
 
 !0 = metadata !{i32 458798, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 1, metadata !2, i1 false, i1 true}
-!1 = metadata !{i32 458769, i32 0, i32 12, metadata !"foo.c", metadata !"/tmp", metadata !"clang 1.0", i1 true, i1 false, metadata !"", i32 0}
-!2 = metadata !{i32 458788, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}
+!1 = metadata !{i32 458769, metadata !4, i32 12, metadata !"clang 1.0", i1 true, metadata !"", i32 0, metadata !5, metadata !5, metadata !4, null, null, metadata !""}
+!2 = metadata !{i32 458788, null, metadata !1, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}
 !3 = metadata !{i32 1, i32 13, metadata !1, metadata !1}
+!4 = metadata !{metadata !"foo.c", metadata !"/tmp"}
+!5 = metadata !{i32 0}
diff --git a/test/FileCheck/check-dag.txt b/test/FileCheck/check-dag.txt
index 6325e06..2b5a475 100644
--- a/test/FileCheck/check-dag.txt
+++ b/test/FileCheck/check-dag.txt
@@ -22,4 +22,5 @@ mul r5, r10, r11
 
 ; CHECK-DAG: add [[REG1:r[0-9]+]], r1, r2
 ; CHECK-DAG: add [[REG2:r[0-9]+]], r3, r4
+; CHECK-NOT: xor
 ; CHECK-DAG: mul r5, [[REG1]], [[REG2]]
diff --git a/test/FileCheck/check-label.txt b/test/FileCheck/check-label.txt
new file mode 100644
index 0000000..27f0bee
--- /dev/null
+++ b/test/FileCheck/check-label.txt
@@ -0,0 +1,51 @@
+; RUN: FileCheck -input-file %s %s -check-prefix=CHECKOK
+; RUN: not FileCheck -input-file %s %s -check-prefix=CHECKFAIL 2>&1 | FileCheck %s -check-prefix=CHECKERROR
+
+label0:
+a
+b
+
+label1:
+b
+c
+
+label2:
+a
+c
+
+; CHECKOK-LABEL: {{^}}label0:
+; CHECKOK: {{^}}a
+; CHECKOK: {{^}}b
+
+; CHECKOK-LABEL: {{^}}label1:
+; CHECKOK: {{^}}b
+; CHECKOK: {{^}}c
+
+; CHECKOK-LABEL: {{^}}label2:
+; CHECKOK: {{^}}a
+; CHECKOK: {{^}}c
+
+; CHECKFAIL-LABEL: {{^}}label0:
+; CHECKFAIL: {{^}}a
+; CHECKFAIL: {{^}}b
+; CHECKFAIL: {{^}}c
+
+; CHECKERROR: expected string not found in input
+; CHECKERROR-NEXT: CHECKFAIL: {{[{][{]\^[}][}]}}c
+
+; CHECKFAIL-LABEL: {{^}}label1:
+; CHECKFAIL: {{^}}a
+; CHECKFAIL: {{^}}b
+; CHECKFAIL: {{^}}c
+
+; CHECKERROR: expected string not found in input
+; CHECKERROR-NEXT: CHECKFAIL: {{[{][{]\^[}][}]}}a
+
+; CHECKFAIL-LABEL: {{^}}label2:
+; CHECKFAIL: {{^}}a
+; CHECKFAIL: {{^}}b
+; CHECKFAIL: {{^}}c
+
+; CHECKERROR: expected string not found in input
+; CHECKERROR-NEXT: CHECKFAIL: {{[{][{]\^[}][}]}}b
+
diff --git a/test/FileCheck/check-not-diaginfo.txt b/test/FileCheck/check-not-diaginfo.txt
index a4c3ca8..44a46a3 100644
--- a/test/FileCheck/check-not-diaginfo.txt
+++ b/test/FileCheck/check-not-diaginfo.txt
@@ -1,4 +1,4 @@
-; RUN: FileCheck -input-file %s %s 2>&1 | FileCheck -check-prefix DIAG %s
+; RUN: not FileCheck -input-file %s %s 2>&1 | FileCheck -check-prefix DIAG %s
 
 CHECK-NOT: test
 
diff --git a/test/Instrumentation/AddressSanitizer/basic.ll b/test/Instrumentation/AddressSanitizer/basic.ll
index fb32e70..6002b9e 100644
--- a/test/Instrumentation/AddressSanitizer/basic.ll
+++ b/test/Instrumentation/AddressSanitizer/basic.ll
@@ -89,6 +89,25 @@ entry:
 ; CHECK-NOT: = alloca
 ; CHECK: ret void
 
+; Check that asan does not touch allocas with alignment > 32.
+define void @alloca_alignment_test() sanitize_address {
+entry:
+  %x = alloca [10 x i8], align 64
+  %y = alloca [10 x i8], align 128
+  %z = alloca [10 x i8], align 256
+  call void @alloca_test_use([10 x i8]* %x)
+  call void @alloca_test_use([10 x i8]* %y)
+  call void @alloca_test_use([10 x i8]* %z)
+  ret void
+}
+
+; CHECK: define void @alloca_alignment_test()
+; CHECK: = alloca{{.*}} align 64
+; CHECK: = alloca{{.*}} align 128
+; CHECK: = alloca{{.*}} align 256
+; CHECK: ret void
+
+
 define void @LongDoubleTest(x86_fp80* nocapture %a) nounwind uwtable sanitize_address {
 entry:
     store x86_fp80 0xK3FFF8000000000000000, x86_fp80* %a, align 16
diff --git a/test/Instrumentation/AddressSanitizer/debug_info.ll b/test/Instrumentation/AddressSanitizer/debug_info.ll
index ec51cae..ec89d26 100644
--- a/test/Instrumentation/AddressSanitizer/debug_info.ll
+++ b/test/Instrumentation/AddressSanitizer/debug_info.ll
@@ -32,16 +32,14 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"a.cc", metadata !"/usr/local/google/llvm_cmake_clang/tmp/debuginfo", metadata !"clang version 3.3 (trunk 169314)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ] [/usr/local/google/llvm_cmake_clang/tmp/debuginfo/a.cc] [DW_LANG_C_plus_plus]
-!1 = metadata !{metadata !2}
-!2 = metadata !{i32 0}
-!3 = metadata !{metadata !4}
-!4 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, metadata !6, metadata !"zzz", metadata !"zzz", metadata !"_Z3zzzi", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32)* @_Z3zzzi, null, null, metadata !1, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [zzz]
+!0 = metadata !{i32 786449, metadata !16, i32 4, metadata !"clang version 3.3 (trunk 169314)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, null, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/llvm_cmake_clang/tmp/debuginfo/a.cc] [DW_LANG_C_plus_plus]
+!1 = metadata !{i32 0}
+!3 = metadata !{metadata !5}
+!5 = metadata !{i32 786478, metadata !16, metadata !6, metadata !"zzz", metadata !"zzz", metadata !"_Z3zzzi", i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32)* @_Z3zzzi, null, null, metadata !1, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [zzz]
 !6 = metadata !{i32 786473, metadata !16} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !8 = metadata !{metadata !9, metadata !9}
-!9 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
 !10 = metadata !{i32 786689, metadata !5, metadata !"p", metadata !6, i32 16777217, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [p] [line 1]
 !11 = metadata !{i32 1, i32 0, metadata !5, null}
 !12 = metadata !{i32 786688, metadata !13, metadata !"r", metadata !6, i32 2, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [r] [line 2]
@@ -55,7 +53,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 ;   CHECK-NOT: DW_TAG_auto_variable
 
 
-!13 = metadata !{i32 786443, metadata !5, i32 1, i32 0, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] [/usr/local/google/llvm_cmake_clang/tmp/debuginfo/a.cc]
+!13 = metadata !{i32 786443, metadata !16, metadata !5, i32 1, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [/usr/local/google/llvm_cmake_clang/tmp/debuginfo/a.cc]
 !14 = metadata !{i32 2, i32 0, metadata !13, null}
 !15 = metadata !{i32 3, i32 0, metadata !13, null}
 !16 = metadata !{metadata !"a.cc", metadata !"/usr/local/google/llvm_cmake_clang/tmp/debuginfo"}
diff --git a/test/Instrumentation/AddressSanitizer/do-not-instrument-internal-globals.ll b/test/Instrumentation/AddressSanitizer/do-not-instrument-internal-globals.ll
index 0928c49..d4fd93c 100644
--- a/test/Instrumentation/AddressSanitizer/do-not-instrument-internal-globals.ll
+++ b/test/Instrumentation/AddressSanitizer/do-not-instrument-internal-globals.ll
@@ -16,5 +16,5 @@ declare void @_Z3fooPi(i32*)
 ; We create one global string constant for the stack frame above.
 ; It should have unnamed_addr and align 1.
 ; Make sure we don't create any other global constants.
-; CHECK: = private unnamed_addr constant{{.*}}align 1
-; CHECK-NOT: = private unnamed_addr constant
+; CHECK: = internal unnamed_addr constant{{.*}}align 1
+; CHECK-NOT: = internal unnamed_addr constant
diff --git a/test/Instrumentation/AddressSanitizer/keep-instrumented_functions.ll b/test/Instrumentation/AddressSanitizer/keep-instrumented_functions.ll
new file mode 100644
index 0000000..ff3bbb0
--- /dev/null
+++ b/test/Instrumentation/AddressSanitizer/keep-instrumented_functions.ll
@@ -0,0 +1,23 @@
+; Test the -asan-keep-uninstrumented-functions flag: FOO should get cloned
+; RUN: opt < %s -asan -asan-keep-uninstrumented-functions -S | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+@a = global i32 0, align 4
+
+define i32 @main() sanitize_address {
+entry:
+  tail call void @FOO(i32* @a)
+  ret i32 0
+}
+
+define void @FOO(i32* nocapture %x) sanitize_address {
+entry:
+  store i32 1, i32* %x, align 4
+  ret void
+}
+
+; main should not be cloned since it is not being instrumented by asan.
+; CHECK-NOT: NOASAN_main
+; CHECK: define void @FOO{{.*}} section "ASAN"
+; CHECK: define void @NOASAN_FOO{{.*}} section "NOASAN"
diff --git a/test/Instrumentation/MemorySanitizer/msan_basic.ll b/test/Instrumentation/MemorySanitizer/msan_basic.ll
index 3a8092b..4fa0319 100644
--- a/test/Instrumentation/MemorySanitizer/msan_basic.ll
+++ b/test/Instrumentation/MemorySanitizer/msan_basic.ll
@@ -638,6 +638,41 @@ declare void @bar()
 ; CHECK: ret i32
 
 
+; Test that stack allocations are unpoisoned in functions missing
+; sanitize_memory attribute
+
+define i32 @NoSanitizeMemoryAlloca() {
+entry:
+  %p = alloca i32, align 4
+  %x = call i32 @NoSanitizeMemoryAllocaHelper(i32* %p)
+  ret i32 %x
+}
+
+declare i32 @NoSanitizeMemoryAllocaHelper(i32* %p)
+
+; CHECK: @NoSanitizeMemoryAlloca
+; CHECK: call void @llvm.memset.p0i8.i64(i8* {{.*}}, i8 0, i64 4, i32 4, i1 false)
+; CHECK: call i32 @NoSanitizeMemoryAllocaHelper(i32*
+; CHECK: ret i32
+
+
+; Test that undef is unpoisoned in functions missing
+; sanitize_memory attribute
+
+define i32 @NoSanitizeMemoryUndef() {
+entry:
+  %x = call i32 @NoSanitizeMemoryUndefHelper(i32 undef)
+  ret i32 %x
+}
+
+declare i32 @NoSanitizeMemoryUndefHelper(i32 %x)
+
+; CHECK: @NoSanitizeMemoryAlloca
+; CHECK: store i32 0, i32* {{.*}} @__msan_param_tls
+; CHECK: call i32 @NoSanitizeMemoryUndefHelper(i32 undef)
+; CHECK: ret i32
+
+
 ; Test argument shadow alignment
 
 define <2 x i64> @ArgumentShadowAlignment(i64 %a, <2 x i64> %b) sanitize_memory {
diff --git a/test/JitListener/test-common-symbols.ll b/test/JitListener/test-common-symbols.ll
index bc94bda..91891d8 100644
--- a/test/JitListener/test-common-symbols.ll
+++ b/test/JitListener/test-common-symbols.ll
@@ -77,37 +77,35 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"test-common-symbols.c", metadata !"/store/store/llvm/build", metadata !"clang version 3.1 ()", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !12} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{metadata !2}
-!2 = metadata !{i32 0}
-!3 = metadata !{metadata !4}
-!4 = metadata !{metadata !5}
-!5 = metadata !{i32 720942, i32 0, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 6, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main, null, null, metadata !10} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 720937, metadata !"test-common-symbols.c", metadata !"/store/store/llvm/build", null} ; [ DW_TAG_file_type ]
+!0 = metadata !{i32 720913, metadata !34, i32 12, metadata !"clang version 3.1 ()", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !12, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 0}
+!3 = metadata !{metadata !5}
+!5 = metadata !{i32 720942, metadata !34, metadata !6, metadata !"main", metadata !"main", metadata !"", i32 6, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main, null, null, metadata !10, i32 0} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 720937, metadata !34} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 720917, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{metadata !9}
-!9 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 720932, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !10 = metadata !{metadata !11}
 !11 = metadata !{i32 720932}                      ; [ DW_TAG_base_type ]
-!12 = metadata !{metadata !13}
-!13 = metadata !{metadata !14, metadata !15, metadata !17}
-!14 = metadata !{i32 720948, i32 0, null, metadata !"zero_int", metadata !"zero_int", metadata !"", metadata !6, i32 1, metadata !9, i32 0, i32 1, i32* @zero_int} ; [ DW_TAG_variable ]
-!15 = metadata !{i32 720948, i32 0, null, metadata !"zero_double", metadata !"zero_double", metadata !"", metadata !6, i32 2, metadata !16, i32 0, i32 1, double* @zero_double} ; [ DW_TAG_variable ]
-!16 = metadata !{i32 720932, null, metadata !"double", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
-!17 = metadata !{i32 720948, i32 0, null, metadata !"zero_arr", metadata !"zero_arr", metadata !"", metadata !6, i32 3, metadata !18, i32 0, i32 1, [10 x i32]* @zero_arr} ; [ DW_TAG_variable ]
+!12 = metadata !{metadata !14, metadata !15, metadata !17}
+!14 = metadata !{i32 720948, i32 0, null, metadata !"zero_int", metadata !"zero_int", metadata !"", metadata !6, i32 1, metadata !9, i32 0, i32 1, i32* @zero_int, null} ; [ DW_TAG_variable ]
+!15 = metadata !{i32 720948, i32 0, null, metadata !"zero_double", metadata !"zero_double", metadata !"", metadata !6, i32 2, metadata !16, i32 0, i32 1, double* @zero_double, null} ; [ DW_TAG_variable ]
+!16 = metadata !{i32 720932, null, null, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
+!17 = metadata !{i32 720948, i32 0, null, metadata !"zero_arr", metadata !"zero_arr", metadata !"", metadata !6, i32 3, metadata !18, i32 0, i32 1, [10 x i32]* @zero_arr, null} ; [ DW_TAG_variable ]
 !18 = metadata !{i32 720897, null, metadata !"", null, i32 0, i64 320, i64 32, i32 0, i32 0, metadata !9, metadata !19, i32 0, i32 0} ; [ DW_TAG_array_type ]
 !19 = metadata !{metadata !20}
 !20 = metadata !{i32 720929, i64 0, i64 10}        ; [ DW_TAG_subrange_type ]
 !21 = metadata !{i32 7, i32 5, metadata !22, null}
-!22 = metadata !{i32 720907, metadata !5, i32 6, i32 1, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
+!22 = metadata !{i32 720907, metadata !34, metadata !5, i32 6, i32 1, i32 0} ; [ DW_TAG_lexical_block ]
 !23 = metadata !{i32 9, i32 5, metadata !22, null}
 !24 = metadata !{i32 10, i32 9, metadata !22, null}
 !25 = metadata !{i32 721152, metadata !26, metadata !"i", metadata !6, i32 12, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
-!26 = metadata !{i32 720907, metadata !22, i32 12, i32 5, metadata !6, i32 1} ; [ DW_TAG_lexical_block ]
+!26 = metadata !{i32 720907, metadata !34, metadata !22, i32 12, i32 5, i32 1} ; [ DW_TAG_lexical_block ]
 !27 = metadata !{i32 12, i32 14, metadata !26, null}
 !28 = metadata !{i32 12, i32 19, metadata !26, null}
 !29 = metadata !{i32 13, i32 9, metadata !30, null}
-!30 = metadata !{i32 720907, metadata !26, i32 12, i32 34, metadata !6, i32 2} ; [ DW_TAG_lexical_block ]
+!30 = metadata !{i32 720907, metadata !34, metadata !26, i32 12, i32 34, i32 2} ; [ DW_TAG_lexical_block ]
 !31 = metadata !{i32 14, i32 5, metadata !30, null}
 !32 = metadata !{i32 12, i32 29, metadata !26, null}
 !33 = metadata !{i32 15, i32 5, metadata !22, null}
+!34 = metadata !{metadata !"test-common-symbols.c", metadata !"/store/store/llvm/build"}
diff --git a/test/JitListener/test-inline.ll b/test/JitListener/test-inline.ll
index ca5d8d6..5c16c94 100644
--- a/test/JitListener/test-inline.ll
+++ b/test/JitListener/test-inline.ll
@@ -133,30 +133,28 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"test-inline.cpp", metadata !"/home/akaylor/dev", metadata !"clang version 3.3 (ssh://akaylor@git-amr-1.devtools.intel.com:29418/ssg_llvm-clang2 gitosis@miro.kw.intel.com:clang.git 39450d0469e0d5589ad39fd0b20b5742750619a0) (ssh://akaylor@git-amr-1.devtools.intel.com:29418/ssg_llvm-llvm gitosis@miro.kw.intel.com:llvm.git 376642ed620ecae05b68c7bc81f79aeb2065abe0)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !43} ; [ DW_TAG_compile_unit ] [/home/akaylor/dev/test-inline.cpp] [DW_LANG_C_plus_plus]
-!1 = metadata !{metadata !2}
-!2 = metadata !{i32 0}
-!3 = metadata !{metadata !4}
-!4 = metadata !{metadata !5, metadata !35, metadata !40}
-!5 = metadata !{i32 786478, i32 0, metadata !6, metadata !"test_parameters", metadata !"test_parameters", metadata !"_Z15test_parametersPfPA2_dR11char_structPPitm", metadata !6, i32 32, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, double (float*, [2 x double]*, %struct.char_struct*, i32**, i16, i64)* @_Z15test_parametersPfPA2_dR11char_structPPitm, null, null, metadata !1, i32 33} ; [ DW_TAG_subprogram ] [line 32] [def] [scope 33] [test_parameters]
-!6 = metadata !{i32 786473, metadata !"test-inline.cpp", metadata !"/home/akaylor/dev", null} ; [ DW_TAG_file_type ]
+!0 = metadata !{i32 786449, metadata !77, i32 4, metadata !"clang version 3.3 (ssh://akaylor@git-amr-1.devtools.intel.com:29418/ssg_llvm-clang2 gitosis@miro.kw.intel.com:clang.git 39450d0469e0d5589ad39fd0b20b5742750619a0) (ssh://akaylor@git-amr-1.devtools.intel.com:29418/ssg_llvm-llvm gitosis@miro.kw.intel.com:llvm.git 376642ed620ecae05b68c7bc81f79aeb2065abe0)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !43, null, metadata !""} ; [ DW_TAG_compile_unit ] [/home/akaylor/dev/test-inline.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{i32 0}
+!3 = metadata !{metadata !5, metadata !35, metadata !40}
+!5 = metadata !{i32 786478, metadata !77, metadata !6, metadata !"test_parameters", metadata !"test_parameters", metadata !"_Z15test_parametersPfPA2_dR11char_structPPitm", i32 32, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, double (float*, [2 x double]*, %struct.char_struct*, i32**, i16, i64)* @_Z15test_parametersPfPA2_dR11char_structPPitm, null, null, metadata !1, i32 33} ; [ DW_TAG_subprogram ] [line 32] [def] [scope 33] [test_parameters]
+!6 = metadata !{i32 786473, metadata !77} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !8 = metadata !{metadata !9, metadata !10, metadata !12, metadata !16, metadata !29, metadata !32, metadata !33}
-!9 = metadata !{i32 786468, null, metadata !"double", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float]
+!9 = metadata !{i32 786468, null, null, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float]
 !10 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from float]
-!11 = metadata !{i32 786468, null, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] [float] [line 0, size 32, align 32, offset 0, enc DW_ATE_float]
+!11 = metadata !{i32 786468, null, null, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] [float] [line 0, size 32, align 32, offset 0, enc DW_ATE_float]
 !12 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !13} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
 !13 = metadata !{i32 786433, null, metadata !"", null, i32 0, i64 128, i64 64, i32 0, i32 0, metadata !9, metadata !14, i32 0, i32 0} ; [ DW_TAG_array_type ] [line 0, size 128, align 64, offset 0] [from double]
 !14 = metadata !{metadata !15}
 !15 = metadata !{i32 786465, i64 0, i64 2}        ; [ DW_TAG_subrange_type ] [0, 1]
 !16 = metadata !{i32 786448, null, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !17} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from char_struct]
-!17 = metadata !{i32 786451, null, metadata !"char_struct", metadata !6, i32 22, i64 24, i64 8, i32 0, i32 0, null, metadata !18, i32 0, null, null} ; [ DW_TAG_structure_type ] [char_struct] [line 22, size 24, align 8, offset 0] [from ]
+!17 = metadata !{i32 786451, metadata !77, null, metadata !"char_struct", i32 22, i64 24, i64 8, i32 0, i32 0, null, metadata !18, i32 0, null, null} ; [ DW_TAG_structure_type ] [char_struct] [line 22, size 24, align 8, offset 0] [from ]
 !18 = metadata !{metadata !19, metadata !21, metadata !23}
-!19 = metadata !{i32 786445, metadata !17, metadata !"c", metadata !6, i32 23, i64 8, i64 8, i64 0, i32 0, metadata !20} ; [ DW_TAG_member ] [c] [line 23, size 8, align 8, offset 0] [from char]
-!20 = metadata !{i32 786468, null, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
-!21 = metadata !{i32 786445, metadata !17, metadata !"c2", metadata !6, i32 24, i64 16, i64 8, i64 8, i32 0, metadata !22} ; [ DW_TAG_member ] [c2] [line 24, size 16, align 8, offset 8] [from ]
+!19 = metadata !{i32 786445, metadata !77, metadata !17, metadata !"c", i32 23, i64 8, i64 8, i64 0, i32 0, metadata !20} ; [ DW_TAG_member ] [c] [line 23, size 8, align 8, offset 0] [from char]
+!20 = metadata !{i32 786468, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
+!21 = metadata !{i32 786445, metadata !77, metadata !17, metadata !"c2", i32 24, i64 16, i64 8, i64 8, i32 0, metadata !22} ; [ DW_TAG_member ] [c2] [line 24, size 16, align 8, offset 8] [from ]
 !22 = metadata !{i32 786433, null, metadata !"", null, i32 0, i64 16, i64 8, i32 0, i32 0, metadata !20, metadata !14, i32 0, i32 0} ; [ DW_TAG_array_type ] [line 0, size 16, align 8, offset 0] [from char]
-!23 = metadata !{i32 786478, i32 0, metadata !17, metadata !"char_struct", metadata !"char_struct", metadata !"", metadata !6, i32 22, metadata !24, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !27, i32 22} ; [ DW_TAG_subprogram ] [line 22] [char_struct]
+!23 = metadata !{i32 786478, metadata !77, metadata !17, metadata !"char_struct", metadata !"char_struct", metadata !"", i32 22, metadata !24, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !27, i32 22} ; [ DW_TAG_subprogram ] [line 22] [char_struct]
 !24 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !25, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !25 = metadata !{null, metadata !26}
 !26 = metadata !{i32 786447, i32 0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !17} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char_struct]
@@ -164,21 +162,20 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
 !28 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ] [line 0, size 0, align 0, offset 0]
 !29 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !30} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
 !30 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !31} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
-!31 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!32 = metadata !{i32 786468, null, metadata !"unsigned short", null, i32 0, i64 16, i64 16, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] [unsigned short] [line 0, size 16, align 16, offset 0, enc DW_ATE_unsigned]
+!31 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!32 = metadata !{i32 786468, null, null, metadata !"unsigned short", i32 0, i64 16, i64 16, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] [unsigned short] [line 0, size 16, align 16, offset 0, enc DW_ATE_unsigned]
 !33 = metadata !{i32 786470, null, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !34} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from long unsigned int]
-!34 = metadata !{i32 786468, null, metadata !"long unsigned int", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] [long unsigned int] [line 0, size 64, align 64, offset 0, enc DW_ATE_unsigned]
-!35 = metadata !{i32 786478, i32 0, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 38, metadata !36, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32, i8**)* @main, null, null, metadata !1, i32 39} ; [ DW_TAG_subprogram ] [line 38] [def] [scope 39] [main]
+!34 = metadata !{i32 786468, null, null, metadata !"long unsigned int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] [long unsigned int] [line 0, size 64, align 64, offset 0, enc DW_ATE_unsigned]
+!35 = metadata !{i32 786478, metadata !77, metadata !6, metadata !"main", metadata !"main", metadata !"", i32 38, metadata !36, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32, i8**)* @main, null, null, metadata !1, i32 39} ; [ DW_TAG_subprogram ] [line 38] [def] [scope 39] [main]
 !36 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !37, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !37 = metadata !{metadata !31, metadata !31, metadata !38}
 !38 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !39} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
 !39 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !20} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char]
-!40 = metadata !{i32 786478, i32 0, metadata !6, metadata !"foo", metadata !"foo", metadata !"_Z3foov", metadata !6, i32 27, metadata !41, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @_Z3foov, null, null, metadata !1, i32 28} ; [ DW_TAG_subprogram ] [line 27] [def] [scope 28] [foo]
+!40 = metadata !{i32 786478, metadata !77, metadata !6, metadata !"foo", metadata !"foo", metadata !"_Z3foov", i32 27, metadata !41, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @_Z3foov, null, null, metadata !1, i32 28} ; [ DW_TAG_subprogram ] [line 27] [def] [scope 28] [foo]
 !41 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !42, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !42 = metadata !{metadata !31}
-!43 = metadata !{metadata !44}
-!44 = metadata !{metadata !45}
-!45 = metadata !{i32 786484, i32 0, null, metadata !"compound_char", metadata !"compound_char", metadata !"", metadata !6, i32 25, metadata !17, i32 0, i32 1, %struct.char_struct* @compound_char} ; [ DW_TAG_variable ] [compound_char] [line 25] [def]
+!43 = metadata !{metadata !45}
+!45 = metadata !{i32 786484, i32 0, null, metadata !"compound_char", metadata !"compound_char", metadata !"", metadata !6, i32 25, metadata !17, i32 0, i32 1, %struct.char_struct* @compound_char, null} ; [ DW_TAG_variable ] [compound_char] [line 25] [def]
 !46 = metadata !{i32 786689, metadata !5, metadata !"pf", metadata !6, i32 16777248, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [pf] [line 32]
 !47 = metadata !{i32 32, i32 0, metadata !5, null}
 !48 = metadata !{i32 786689, metadata !5, metadata !"ppd", metadata !6, i32 33554464, metadata !12, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [ppd] [line 32]
@@ -187,16 +184,16 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
 !51 = metadata !{i32 786689, metadata !5, metadata !"us", metadata !6, i32 83886112, metadata !32, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [us] [line 32]
 !52 = metadata !{i32 786689, metadata !5, metadata !"l", metadata !6, i32 100663328, metadata !33, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [l] [line 32]
 !53 = metadata !{i32 786688, metadata !54, metadata !"result", metadata !6, i32 34, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [result] [line 34]
-!54 = metadata !{i32 786443, metadata !5, i32 33, i32 0, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] [/home/akaylor/dev/test-inline.cpp]
+!54 = metadata !{i32 786443, metadata !77, metadata !5, i32 33, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [/home/akaylor/dev/test-inline.cpp]
 !55 = metadata !{i32 34, i32 0, metadata !54, null}
 !56 = metadata !{i32 35, i32 0, metadata !54, null}
 !57 = metadata !{i32 29, i32 0, metadata !58, null}
-!58 = metadata !{i32 786443, metadata !40, i32 28, i32 0, metadata !6, i32 2} ; [ DW_TAG_lexical_block ] [/home/akaylor/dev/test-inline.cpp]
+!58 = metadata !{i32 786443, metadata !77, metadata !40, i32 28, i32 0, i32 2} ; [ DW_TAG_lexical_block ] [/home/akaylor/dev/test-inline.cpp]
 !59 = metadata !{i32 786689, metadata !35, metadata !"argc", metadata !6, i32 16777254, metadata !31, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [argc] [line 38]
 !60 = metadata !{i32 38, i32 0, metadata !35, null}
 !61 = metadata !{i32 786689, metadata !35, metadata !"argv", metadata !6, i32 33554470, metadata !38, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [argv] [line 38]
 !62 = metadata !{i32 786688, metadata !63, metadata !"s", metadata !6, i32 40, metadata !17, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [s] [line 40]
-!63 = metadata !{i32 786443, metadata !35, i32 39, i32 0, metadata !6, i32 1} ; [ DW_TAG_lexical_block ] [/home/akaylor/dev/test-inline.cpp]
+!63 = metadata !{i32 786443, metadata !77, metadata !35, i32 39, i32 0, i32 1} ; [ DW_TAG_lexical_block ] [/home/akaylor/dev/test-inline.cpp]
 !64 = metadata !{i32 40, i32 0, metadata !63, null}
 !65 = metadata !{i32 786688, metadata !63, metadata !"f", metadata !6, i32 41, metadata !11, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [f] [line 41]
 !66 = metadata !{i32 41, i32 0, metadata !63, null}
@@ -210,3 +207,4 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
 !74 = metadata !{i32 786688, metadata !63, metadata !"result", metadata !6, i32 48, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [result] [line 48]
 !75 = metadata !{i32 48, i32 0, metadata !63, null}
 !76 = metadata !{i32 49, i32 0, metadata !63, null}
+!77 = metadata !{metadata !"test-inline.cpp", metadata !"/home/akaylor/dev"}
diff --git a/test/JitListener/test-parameters.ll b/test/JitListener/test-parameters.ll
index 1e2a2b3..96af18e 100644
--- a/test/JitListener/test-parameters.ll
+++ b/test/JitListener/test-parameters.ll
@@ -132,34 +132,32 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"test-parameters.cpp", metadata !"/home/akaylor/dev", metadata !"clang version 3.3 (ssh://akaylor@git-amr-1.devtools.intel.com:29418/ssg_llvm-clang2 gitosis@miro.kw.intel.com:clang.git 39450d0469e0d5589ad39fd0b20b5742750619a0) (ssh://akaylor@git-amr-1.devtools.intel.com:29418/ssg_llvm-llvm gitosis@miro.kw.intel.com:llvm.git 376642ed620ecae05b68c7bc81f79aeb2065abe0)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !43} ; [ DW_TAG_compile_unit ] [/home/akaylor/dev/test-parameters.cpp] [DW_LANG_C_plus_plus]
-!1 = metadata !{metadata !2}
-!2 = metadata !{i32 0}
-!3 = metadata !{metadata !4}
-!4 = metadata !{metadata !5, metadata !10, metadata !38}
-!5 = metadata !{i32 786478, i32 0, metadata !6, metadata !"foo", metadata !"foo", metadata !"_Z3foov", metadata !6, i32 27, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @_Z3foov, null, null, metadata !1, i32 28} ; [ DW_TAG_subprogram ] [line 27] [def] [scope 28] [foo]
-!6 = metadata !{i32 786473, metadata !"test-parameters.cpp", metadata !"/home/akaylor/dev", null} ; [ DW_TAG_file_type ]
+!0 = metadata !{i32 786449, metadata !77, i32 4, metadata !"clang version 3.3 (ssh://akaylor@git-amr-1.devtools.intel.com:29418/ssg_llvm-clang2 gitosis@miro.kw.intel.com:clang.git 39450d0469e0d5589ad39fd0b20b5742750619a0) (ssh://akaylor@git-amr-1.devtools.intel.com:29418/ssg_llvm-llvm gitosis@miro.kw.intel.com:llvm.git 376642ed620ecae05b68c7bc81f79aeb2065abe0)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !43, null, metadata !""} ; [ DW_TAG_compile_unit ] [/home/akaylor/dev/test-parameters.cpp] [DW_LANG_C_plus_plus]
+!1 = metadata !{i32 0}
+!3 = metadata !{metadata !5, metadata !10, metadata !38}
+!5 = metadata !{i32 786478, metadata !77, metadata !6, metadata !"foo", metadata !"foo", metadata !"_Z3foov", i32 27, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @_Z3foov, null, null, metadata !1, i32 28} ; [ DW_TAG_subprogram ] [line 27] [def] [scope 28] [foo]
+!6 = metadata !{i32 786473, metadata !77} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !8 = metadata !{metadata !9}
-!9 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
-!10 = metadata !{i32 786478, i32 0, metadata !6, metadata !"test_parameters", metadata !"test_parameters", metadata !"_Z15test_parametersPfPA2_dR11char_structPPitm", metadata !6, i32 32, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, double (float*, [2 x double]*, %struct.char_struct*, i32**, i16, i64)* @_Z15test_parametersPfPA2_dR11char_structPPitm, null, null, metadata !1, i32 33} ; [ DW_TAG_subprogram ] [line 32] [def] [scope 33] [test_parameters]
+!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!10 = metadata !{i32 786478, metadata !77, metadata !6, metadata !"test_parameters", metadata !"test_parameters", metadata !"_Z15test_parametersPfPA2_dR11char_structPPitm", i32 32, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, double (float*, [2 x double]*, %struct.char_struct*, i32**, i16, i64)* @_Z15test_parametersPfPA2_dR11char_structPPitm, null, null, metadata !1, i32 33} ; [ DW_TAG_subprogram ] [line 32] [def] [scope 33] [test_parameters]
 !11 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !12 = metadata !{metadata !13, metadata !14, metadata !16, metadata !20, metadata !33, metadata !35, metadata !36}
-!13 = metadata !{i32 786468, null, metadata !"double", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float]
+!13 = metadata !{i32 786468, null, null, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float]
 !14 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !15} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from float]
-!15 = metadata !{i32 786468, null, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] [float] [line 0, size 32, align 32, offset 0, enc DW_ATE_float]
+!15 = metadata !{i32 786468, null, null, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] [float] [line 0, size 32, align 32, offset 0, enc DW_ATE_float]
 !16 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !17} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
 !17 = metadata !{i32 786433, null, metadata !"", null, i32 0, i64 128, i64 64, i32 0, i32 0, metadata !13, metadata !18, i32 0, i32 0} ; [ DW_TAG_array_type ] [line 0, size 128, align 64, offset 0] [from double]
 !18 = metadata !{metadata !19}
 !19 = metadata !{i32 786465, i64 0, i64 2}        ; [ DW_TAG_subrange_type ] [0, 1]
 !20 = metadata !{i32 786448, null, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !21} ; [ DW_TAG_reference_type ] [line 0, size 0, align 0, offset 0] [from char_struct]
-!21 = metadata !{i32 786451, null, metadata !"char_struct", metadata !6, i32 22, i64 24, i64 8, i32 0, i32 0, null, metadata !22, i32 0, null, null} ; [ DW_TAG_structure_type ] [char_struct] [line 22, size 24, align 8, offset 0] [from ]
+!21 = metadata !{i32 786451, metadata !77, null, metadata !"char_struct", i32 22, i64 24, i64 8, i32 0, i32 0, null, metadata !22, i32 0, null, null} ; [ DW_TAG_structure_type ] [char_struct] [line 22, size 24, align 8, offset 0] [from ]
 !22 = metadata !{metadata !23, metadata !25, metadata !27}
-!23 = metadata !{i32 786445, metadata !21, metadata !"c", metadata !6, i32 23, i64 8, i64 8, i64 0, i32 0, metadata !24} ; [ DW_TAG_member ] [c] [line 23, size 8, align 8, offset 0] [from char]
-!24 = metadata !{i32 786468, null, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
-!25 = metadata !{i32 786445, metadata !21, metadata !"c2", metadata !6, i32 24, i64 16, i64 8, i64 8, i32 0, metadata !26} ; [ DW_TAG_member ] [c2] [line 24, size 16, align 8, offset 8] [from ]
+!23 = metadata !{i32 786445, metadata !77, metadata !21, metadata !"c", i32 23, i64 8, i64 8, i64 0, i32 0, metadata !24} ; [ DW_TAG_member ] [c] [line 23, size 8, align 8, offset 0] [from char]
+!24 = metadata !{i32 786468, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
+!25 = metadata !{i32 786445, metadata !77, metadata !21, metadata !"c2", i32 24, i64 16, i64 8, i64 8, i32 0, metadata !26} ; [ DW_TAG_member ] [c2] [line 24, size 16, align 8, offset 8] [from ]
 !26 = metadata !{i32 786433, null, metadata !"", null, i32 0, i64 16, i64 8, i32 0, i32 0, metadata !24, metadata !18, i32 0, i32 0} ; [ DW_TAG_array_type ] [line 0, size 16, align 8, offset 0] [from char]
-!27 = metadata !{i32 786478, i32 0, metadata !21, metadata !"char_struct", metadata !"char_struct", metadata !"", metadata !6, i32 22, metadata !28, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !31, i32 22} ; [ DW_TAG_subprogram ] [line 22] [char_struct]
+!27 = metadata !{i32 786478, metadata !77, metadata !21, metadata !"char_struct", metadata !"char_struct", metadata !"", i32 22, metadata !28, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null, i32 0, metadata !31, i32 22} ; [ DW_TAG_subprogram ] [line 22] [char_struct]
 !28 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !29, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !29 = metadata !{null, metadata !30}
 !30 = metadata !{i32 786447, i32 0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 1088, metadata !21} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char_struct]
@@ -167,19 +165,18 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
 !32 = metadata !{i32 786468}                      ; [ DW_TAG_base_type ] [line 0, size 0, align 0, offset 0]
 !33 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !34} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
 !34 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
-!35 = metadata !{i32 786468, null, metadata !"unsigned short", null, i32 0, i64 16, i64 16, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] [unsigned short] [line 0, size 16, align 16, offset 0, enc DW_ATE_unsigned]
+!35 = metadata !{i32 786468, null, null, metadata !"unsigned short", i32 0, i64 16, i64 16, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] [unsigned short] [line 0, size 16, align 16, offset 0, enc DW_ATE_unsigned]
 !36 = metadata !{i32 786470, null, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !37} ; [ DW_TAG_const_type ] [line 0, size 0, align 0, offset 0] [from long unsigned int]
-!37 = metadata !{i32 786468, null, metadata !"long unsigned int", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] [long unsigned int] [line 0, size 64, align 64, offset 0, enc DW_ATE_unsigned]
-!38 = metadata !{i32 786478, i32 0, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 38, metadata !39, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32, i8**)* @main, null, null, metadata !1, i32 39} ; [ DW_TAG_subprogram ] [line 38] [def] [scope 39] [main]
+!37 = metadata !{i32 786468, null, null, metadata !"long unsigned int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] [long unsigned int] [line 0, size 64, align 64, offset 0, enc DW_ATE_unsigned]
+!38 = metadata !{i32 786478, metadata !77, metadata !6, metadata !"main", metadata !"main", metadata !"", i32 38, metadata !39, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32, i8**)* @main, null, null, metadata !1, i32 39} ; [ DW_TAG_subprogram ] [line 38] [def] [scope 39] [main]
 !39 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !40, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !40 = metadata !{metadata !9, metadata !9, metadata !41}
 !41 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !42} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ]
 !42 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !24} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char]
-!43 = metadata !{metadata !44}
-!44 = metadata !{metadata !45}
-!45 = metadata !{i32 786484, i32 0, null, metadata !"compound_char", metadata !"compound_char", metadata !"", metadata !6, i32 25, metadata !21, i32 0, i32 1, %struct.char_struct* @compound_char} ; [ DW_TAG_variable ] [compound_char] [line 25] [def]
+!43 = metadata !{metadata !45}
+!45 = metadata !{i32 786484, i32 0, null, metadata !"compound_char", metadata !"compound_char", metadata !"", metadata !6, i32 25, metadata !21, i32 0, i32 1, %struct.char_struct* @compound_char, null} ; [ DW_TAG_variable ] [compound_char] [line 25] [def]
 !46 = metadata !{i32 29, i32 0, metadata !47, null}
-!47 = metadata !{i32 786443, metadata !5, i32 28, i32 0, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] [/home/akaylor/dev/test-parameters.cpp]
+!47 = metadata !{i32 786443, metadata !77, metadata !5, i32 28, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [/home/akaylor/dev/test-parameters.cpp]
 !48 = metadata !{i32 786689, metadata !10, metadata !"pf", metadata !6, i32 16777248, metadata !14, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [pf] [line 32]
 !49 = metadata !{i32 32, i32 0, metadata !10, null}
 !50 = metadata !{i32 786689, metadata !10, metadata !"ppd", metadata !6, i32 33554464, metadata !16, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [ppd] [line 32]
@@ -188,14 +185,14 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
 !53 = metadata !{i32 786689, metadata !10, metadata !"us", metadata !6, i32 83886112, metadata !35, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [us] [line 32]
 !54 = metadata !{i32 786689, metadata !10, metadata !"l", metadata !6, i32 100663328, metadata !36, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [l] [line 32]
 !55 = metadata !{i32 786688, metadata !56, metadata !"result", metadata !6, i32 34, metadata !13, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [result] [line 34]
-!56 = metadata !{i32 786443, metadata !10, i32 33, i32 0, metadata !6, i32 1} ; [ DW_TAG_lexical_block ] [/home/akaylor/dev/test-parameters.cpp]
+!56 = metadata !{i32 786443, metadata !77, metadata !10, i32 33, i32 0, i32 1} ; [ DW_TAG_lexical_block ] [/home/akaylor/dev/test-parameters.cpp]
 !57 = metadata !{i32 34, i32 0, metadata !56, null}
 !58 = metadata !{i32 35, i32 0, metadata !56, null}
 !59 = metadata !{i32 786689, metadata !38, metadata !"argc", metadata !6, i32 16777254, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [argc] [line 38]
 !60 = metadata !{i32 38, i32 0, metadata !38, null}
 !61 = metadata !{i32 786689, metadata !38, metadata !"argv", metadata !6, i32 33554470, metadata !41, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [argv] [line 38]
 !62 = metadata !{i32 786688, metadata !63, metadata !"s", metadata !6, i32 40, metadata !21, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [s] [line 40]
-!63 = metadata !{i32 786443, metadata !38, i32 39, i32 0, metadata !6, i32 2} ; [ DW_TAG_lexical_block ] [/home/akaylor/dev/test-parameters.cpp]
+!63 = metadata !{i32 786443, metadata !77, metadata !38, i32 39, i32 0, i32 2} ; [ DW_TAG_lexical_block ] [/home/akaylor/dev/test-parameters.cpp]
 !64 = metadata !{i32 40, i32 0, metadata !63, null}
 !65 = metadata !{i32 786688, metadata !63, metadata !"f", metadata !6, i32 41, metadata !15, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [f] [line 41]
 !66 = metadata !{i32 41, i32 0, metadata !63, null}
@@ -209,3 +206,4 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
 !74 = metadata !{i32 786688, metadata !63, metadata !"result", metadata !6, i32 48, metadata !13, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [result] [line 48]
 !75 = metadata !{i32 48, i32 0, metadata !63, null}
 !76 = metadata !{i32 49, i32 0, metadata !63, null}
+!77 = metadata !{metadata !"test-parameters.cpp", metadata !"/home/akaylor/dev"}
diff --git a/test/Linker/2011-08-04-DebugLoc.ll b/test/Linker/2011-08-04-DebugLoc.ll
index 699f0b5..5daf33b 100644
--- a/test/Linker/2011-08-04-DebugLoc.ll
+++ b/test/Linker/2011-08-04-DebugLoc.ll
@@ -16,11 +16,14 @@ define i32 @foo() nounwind ssp {
 !llvm.dbg.cu = !{!0}
 !llvm.dbg.sp = !{!1}
 
-!0 = metadata !{i32 589841, i32 0, i32 12, metadata !"a.c", metadata !"/private/tmp", metadata !"Apple clang version 3.0 (tags/Apple/clang-209.11) (based on LLVM 3.0svn)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @foo, null, null} ; [ DW_TAG_subprogram ]
-!2 = metadata !{i32 589865, metadata !"a.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 589841, metadata !8, i32 12, metadata !"Apple clang version 3.0 (tags/Apple/clang-209.11) (based on LLVM 3.0svn)", i1 true, metadata !"", i32 0, metadata !9, metadata !9, metadata !10, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 589870, metadata !8, metadata !2, metadata !"foo", metadata !"foo", metadata !"", i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 589865, metadata !8} ; [ DW_TAG_file_type ]
+!3 = metadata !{i32 589845, metadata !8, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 589860, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !6 = metadata !{i32 2, i32 13, metadata !7, null}
-!7 = metadata !{i32 589835, metadata !1, i32 2, i32 11, metadata !2, i32 0} ; [ DW_TAG_lexical_block ]
+!7 = metadata !{i32 589835, metadata !8, metadata !1, i32 2, i32 11, i32 0} ; [ DW_TAG_lexical_block ]
+!8 = metadata !{metadata !"a.c", metadata !"/private/tmp"}
+!9 = metadata !{i32 0}
+!10 = metadata !{metadata !1}
diff --git a/test/Linker/2011-08-04-DebugLoc2.ll b/test/Linker/2011-08-04-DebugLoc2.ll
index f30e180..3f8504f 100644
--- a/test/Linker/2011-08-04-DebugLoc2.ll
+++ b/test/Linker/2011-08-04-DebugLoc2.ll
@@ -13,11 +13,14 @@ define i32 @bar() nounwind ssp {
 !llvm.dbg.cu = !{!0}
 !llvm.dbg.sp = !{!1}
 
-!0 = metadata !{i32 589841, i32 0, i32 12, metadata !"b.c", metadata !"/private/tmp", metadata !"Apple clang version 3.0 (tags/Apple/clang-209.11) (based on LLVM 3.0svn)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"bar", metadata !"bar", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @bar, null, null} ; [ DW_TAG_subprogram ]
-!2 = metadata !{i32 589865, metadata !"b.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 589841, metadata !8, i32 12, metadata !"Apple clang version 3.0 (tags/Apple/clang-209.11) (based on LLVM 3.0svn)", i1 true, metadata !"", i32 0, metadata !9, metadata !9, metadata !10, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 589870, metadata !8, metadata !2, metadata !"bar", metadata !"bar", metadata !"", i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @bar, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 589865, metadata !8} ; [ DW_TAG_file_type ]
+!3 = metadata !{i32 589845, metadata !8, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 589860, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !6 = metadata !{i32 1, i32 13, metadata !7, null}
-!7 = metadata !{i32 589835, metadata !1, i32 1, i32 11, metadata !2, i32 0} ; [ DW_TAG_lexical_block ]
+!7 = metadata !{i32 589835, metadata !8, metadata !1, i32 1, i32 11, i32 0} ; [ DW_TAG_lexical_block ]
+!8 = metadata !{metadata !"b.c", metadata !"/private/tmp"}
+!9 = metadata !{i32 0}
+!10 = metadata !{metadata !1}
diff --git a/test/Linker/2011-08-04-Metadata.ll b/test/Linker/2011-08-04-Metadata.ll
index 952eccc..b800e5d 100644
--- a/test/Linker/2011-08-04-Metadata.ll
+++ b/test/Linker/2011-08-04-Metadata.ll
@@ -18,12 +18,14 @@ entry:
 !llvm.dbg.sp = !{!1}
 !llvm.dbg.gv = !{!5}
 
-!0 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/one.c", metadata !"/Volumes/Lalgate/Slate/D", metadata !"clang version 3.0 ()", i1 true, i1 false, metadata !"", i32 0}
-!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, void ()* @foo, null, null}
-!2 = metadata !{i32 589865, metadata !"/tmp/one.c", metadata !"/Volumes/Lalgate/Slate/D", metadata !0}
-!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0}
+!0 = metadata !{i32 589841, metadata !9, i32 12, metadata !"clang version 3.0 ()", i1 true, metadata !"", i32 0, metadata !4, metadata !4, metadata !10, null, null, metadata !""}
+!1 = metadata !{i32 589870, metadata !9, metadata !2, metadata !"foo", metadata !"foo", metadata !"", i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, void ()* @foo, null, null, null, i32 0}
+!2 = metadata !{i32 589865, metadata !9}
+!3 = metadata !{i32 589845, metadata !9, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0}
 !4 = metadata !{null}
 !5 = metadata !{i32 589876, i32 0, metadata !0, metadata !"x", metadata !"x", metadata !"", metadata !2, i32 2, metadata !6, i32 1, i32 1, i32* @x}
-!6 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}
+!6 = metadata !{i32 589860, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}
 !7 = metadata !{i32 3, i32 14, metadata !8, null}
-!8 = metadata !{i32 589835, metadata !1, i32 3, i32 12, metadata !2, i32 0}
+!8 = metadata !{i32 589835, metadata !9, metadata !1, i32 3, i32 12, i32 0}
+!9 = metadata !{metadata !"/tmp/one.c", metadata !"/Volumes/Lalgate/Slate/D"}
+!10 = metadata !{metadata !1}
diff --git a/test/Linker/2011-08-04-Metadata2.ll b/test/Linker/2011-08-04-Metadata2.ll
index fa5e7c9..311a7c6 100644
--- a/test/Linker/2011-08-04-Metadata2.ll
+++ b/test/Linker/2011-08-04-Metadata2.ll
@@ -18,12 +18,14 @@ entry:
 !llvm.dbg.sp = !{!1}
 !llvm.dbg.gv = !{!5}
 
-!0 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/two.c", metadata !"/Volumes/Lalgate/Slate/D", metadata !"clang version 3.0 ()", i1 true, i1 false, metadata !"", i32 0}
-!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"bar", metadata !"bar", metadata !"", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, void ()* @bar, null, null}
-!2 = metadata !{i32 589865, metadata !"/tmp/two.c", metadata !"/Volumes/Lalgate/Slate/D", metadata !0}
-!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0}
+!0 = metadata !{i32 589841, metadata !9, i32 12, metadata !"clang version 3.0 ()", i1 true, metadata !"", i32 0, metadata !4, metadata !4, metadata !10, null, null, metadata !""}
+!1 = metadata !{i32 589870, metadata !9, metadata !2, metadata !"bar", metadata !"bar", metadata !"", i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, void ()* @bar, null, null, null, i32 0}
+!2 = metadata !{i32 589865, metadata !9}
+!3 = metadata !{i32 589845, metadata !9, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0}
 !4 = metadata !{null}
 !5 = metadata !{i32 589876, i32 0, metadata !0, metadata !"x", metadata !"x", metadata !"", metadata !2, i32 1, metadata !6, i32 1, i32 1, i32* @x}
-!6 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}
+!6 = metadata !{i32 589860, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}
 !7 = metadata !{i32 2, i32 14, metadata !8, null}
-!8 = metadata !{i32 589835, metadata !1, i32 2, i32 12, metadata !2, i32 0}
+!8 = metadata !{i32 589835, metadata !9, metadata !1, i32 2, i32 12, i32 0}
+!9 = metadata !{metadata !"/tmp/two.c", metadata !"/Volumes/Lalgate/Slate/D"}
+!10 = metadata !{metadata !1}
diff --git a/test/Linker/2011-08-18-unique-class-type.ll b/test/Linker/2011-08-18-unique-class-type.ll
index 328e83b..b460ac3 100644
--- a/test/Linker/2011-08-18-unique-class-type.ll
+++ b/test/Linker/2011-08-18-unique-class-type.ll
@@ -19,19 +19,20 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 720913, i32 0, i32 4, metadata !"n1.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 137954)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 720913, metadata !16, i32 4, metadata !"clang version 3.0 (trunk 137954)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{metadata !2}
 !2 = metadata !{i32 0}
-!3 = metadata !{metadata !4}
-!4 = metadata !{metadata !5}
-!5 = metadata !{i32 720942, i32 0, metadata !6, metadata !"foo", metadata !"foo", metadata !"_Z3fooN2N11AE", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void ()* @_Z3fooN2N11AE, null, null} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 720937, metadata !"n1.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
-!7 = metadata !{i32 720917, metadata !6, metadata !"", metadata !6, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!3 = metadata !{metadata !5}
+!5 = metadata !{i32 720942, metadata !16, metadata !6, metadata !"foo", metadata !"foo", metadata !"_Z3fooN2N11AE", i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void ()* @_Z3fooN2N11AE, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 720937, metadata !16} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 720917, metadata !16, metadata !6, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{null}
 !9 = metadata !{i32 721153, metadata !5, metadata !"mya", metadata !6, i32 16777220, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
-!10 = metadata !{i32 720898, metadata !11, metadata !"A", metadata !12, i32 3, i64 8, i64 8, i32 0, i32 0, null, metadata !2, i32 0, null, null} ; [ DW_TAG_class_type ]
-!11 = metadata !{i32 720953, null, metadata !"N1", metadata !12, i32 2} ; [ DW_TAG_namespace ]
-!12 = metadata !{i32 720937, metadata !"./n.h", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
+!10 = metadata !{i32 720898, metadata !17, metadata !11, metadata !"A", i32 3, i64 8, i64 8, i32 0, i32 0, null, metadata !2, i32 0, null, null} ; [ DW_TAG_class_type ]
+!11 = metadata !{i32 720953, metadata !17, null, metadata !"N1", i32 2} ; [ DW_TAG_namespace ]
+!12 = metadata !{i32 720937, metadata !17} ; [ DW_TAG_file_type ]
 !13 = metadata !{i32 4, i32 12, metadata !5, null}
 !14 = metadata !{i32 4, i32 18, metadata !15, null}
-!15 = metadata !{i32 720907, metadata !5, i32 4, i32 17, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
+!15 = metadata !{i32 720907, metadata !16, metadata !5, i32 4, i32 17, i32 0} ; [ DW_TAG_lexical_block ]
+!16 = metadata !{metadata !"n1.c", metadata !"/private/tmp"}
+!17 = metadata !{metadata !"./n.h", metadata !"/private/tmp"}
diff --git a/test/Linker/2011-08-18-unique-class-type2.ll b/test/Linker/2011-08-18-unique-class-type2.ll
index 95892a4..8bd3841 100644
--- a/test/Linker/2011-08-18-unique-class-type2.ll
+++ b/test/Linker/2011-08-18-unique-class-type2.ll
@@ -17,19 +17,20 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 720913, i32 0, i32 4, metadata !"n2.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 137954)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 720913, metadata !16, i32 4, metadata !"clang version 3.0 (trunk 137954)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{metadata !2}
 !2 = metadata !{i32 0}
-!3 = metadata !{metadata !4}
-!4 = metadata !{metadata !5}
-!5 = metadata !{i32 720942, i32 0, metadata !6, metadata !"bar", metadata !"bar", metadata !"_Z3barN2N11AE", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void ()* @_Z3barN2N11AE, null, null} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 720937, metadata !"n2.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
-!7 = metadata !{i32 720917, metadata !6, metadata !"", metadata !6, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!3 = metadata !{metadata !5}
+!5 = metadata !{i32 720942, i32 0, metadata !6, metadata !"bar", metadata !"bar", metadata !"_Z3barN2N11AE", i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void ()* @_Z3barN2N11AE, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 720937, metadata !16} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 720917, metadata !16, metadata !6, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{null}
 !9 = metadata !{i32 721153, metadata !5, metadata !"youra", metadata !6, i32 16777220, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
-!10 = metadata !{i32 720898, metadata !11, metadata !"A", metadata !12, i32 3, i64 8, i64 8, i32 0, i32 0, null, metadata !2, i32 0, null, null} ; [ DW_TAG_class_type ]
-!11 = metadata !{i32 720953, null, metadata !"N1", metadata !12, i32 2} ; [ DW_TAG_namespace ]
-!12 = metadata !{i32 720937, metadata !"./n.h", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
+!10 = metadata !{i32 720898, metadata !17, metadata !11, metadata !"A", i32 3, i64 8, i64 8, i32 0, i32 0, null, metadata !2, i32 0, null, null} ; [ DW_TAG_class_type ]
+!11 = metadata !{i32 720953, metadata !17, null, metadata !"N1", i32 2} ; [ DW_TAG_namespace ]
+!12 = metadata !{i32 720937, metadata !17} ; [ DW_TAG_file_type ]
 !13 = metadata !{i32 4, i32 12, metadata !5, null}
 !14 = metadata !{i32 4, i32 20, metadata !15, null}
-!15 = metadata !{i32 720907, metadata !5, i32 4, i32 19, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
+!15 = metadata !{i32 720907, metadata !16, metadata !5, i32 4, i32 19, i32 0} ; [ DW_TAG_lexical_block ]
+!16 = metadata !{metadata !"n2.c", metadata !"/private/tmp"}
+!17 = metadata !{metadata !"./n.h", metadata !"/private/tmp"}
diff --git a/test/Linker/2011-08-18-unique-debug-type.ll b/test/Linker/2011-08-18-unique-debug-type.ll
index cc0df4d..d56968d 100644
--- a/test/Linker/2011-08-18-unique-debug-type.ll
+++ b/test/Linker/2011-08-18-unique-debug-type.ll
@@ -11,16 +11,15 @@ entry:
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"one.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 137954)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 720913, metadata !12, i32 12, metadata !"clang version 3.0 (trunk 137954)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{metadata !2}
 !2 = metadata !{i32 0}
-!3 = metadata !{metadata !4}
-!4 = metadata !{metadata !5}
-!5 = metadata !{i32 720942, i32 0, metadata !6, metadata !"foo", metadata !"foo", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @foo, null, null} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 720937, metadata !"one.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
-!7 = metadata !{i32 720917, metadata !6, metadata !"", metadata !6, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!3 = metadata !{metadata !5}
+!5 = metadata !{i32 720942, metadata !12, metadata !6, metadata !"foo", metadata !"foo", metadata !"", i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 720937, metadata !12} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 720917, metadata !12, metadata !6, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{metadata !9}
-!9 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 720932, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !10 = metadata !{i32 1, i32 13, metadata !11, null}
-!11 = metadata !{i32 720907, metadata !5, i32 1, i32 11, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
-
+!11 = metadata !{i32 720907, metadata !12, metadata !5, i32 1, i32 11, i32 0} ; [ DW_TAG_lexical_block ]
+!12 = metadata !{metadata !"one.c", metadata !"/private/tmp"}
diff --git a/test/Linker/2011-08-18-unique-debug-type2.ll b/test/Linker/2011-08-18-unique-debug-type2.ll
index 986da5b..e724a67 100644
--- a/test/Linker/2011-08-18-unique-debug-type2.ll
+++ b/test/Linker/2011-08-18-unique-debug-type2.ll
@@ -11,15 +11,15 @@ entry:
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 720913, i32 0, i32 12, metadata !"two.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 137954)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 720913, metadata !12, i32 12, metadata !"clang version 3.0 (trunk 137954)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{metadata !2}
 !2 = metadata !{i32 0}
-!3 = metadata !{metadata !4}
-!4 = metadata !{metadata !5}
-!5 = metadata !{i32 720942, i32 0, metadata !6, metadata !"bar", metadata !"bar", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @bar, null, null} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 720937, metadata !"two.c", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
-!7 = metadata !{i32 720917, metadata !6, metadata !"", metadata !6, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!3 = metadata !{metadata !5}
+!5 = metadata !{i32 720942, metadata !12, metadata !6, metadata !"bar", metadata !"bar", metadata !"", i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @bar, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 720937, metadata !12} ; [ DW_TAG_file_type ]
+!7 = metadata !{i32 720917, metadata !12, metadata !6, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{metadata !9}
-!9 = metadata !{i32 720932, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 720932, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !10 = metadata !{i32 1, i32 13, metadata !11, null}
-!11 = metadata !{i32 720907, metadata !5, i32 1, i32 11, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
+!11 = metadata !{i32 720907, metadata !12, metadata !5, i32 1, i32 11, i32 0} ; [ DW_TAG_lexical_block ]
+!12 = metadata !{metadata !"two.c", metadata !"/private/tmp"}
diff --git a/test/Linker/DbgDeclare.ll b/test/Linker/DbgDeclare.ll
index 7f64f95..7f3fbde 100644
--- a/test/Linker/DbgDeclare.ll
+++ b/test/Linker/DbgDeclare.ll
@@ -36,23 +36,23 @@ declare void @test(i32, i8**)
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"main.cpp", metadata !"/private/tmp", metadata !"clang version 3.3 (trunk 173515)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !20, i32 4, metadata !"clang version 3.3 (trunk 173515)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{metadata !2}
 !2 = metadata !{i32 0}
-!3 = metadata !{metadata !4}
-!4 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, i32 0, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32, i8**)* @main, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 786473, metadata !"main.cpp", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
+!3 = metadata !{metadata !5}
+!5 = metadata !{i32 786478, metadata !20, null, metadata !"main", metadata !"main", metadata !"", i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32, i8**)* @main, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 786473, metadata !20} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{metadata !9, metadata !9, metadata !10}
-!9 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !10 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ]
 !11 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ]
 !12 = metadata !{i32 786470, null, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !13} ; [ DW_TAG_const_type ]
-!13 = metadata !{i32 786468, null, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!13 = metadata !{i32 786468, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !14 = metadata !{i32 786689, metadata !5, metadata !"argc", metadata !6, i32 16777219, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
 !15 = metadata !{i32 3, i32 0, metadata !5, null}
 !16 = metadata !{i32 786689, metadata !5, metadata !"argv", metadata !6, i32 33554435, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
 !17 = metadata !{i32 5, i32 0, metadata !18, null}
-!18 = metadata !{i32 786443, metadata !5, i32 4, i32 0, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
+!18 = metadata !{i32 786443, metadata !20, metadata !5, i32 4, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !19 = metadata !{i32 6, i32 0, metadata !18, null}
+!20 = metadata !{metadata !"main.cpp", metadata !"/private/tmp"}
diff --git a/test/Linker/DbgDeclare2.ll b/test/Linker/DbgDeclare2.ll
index e2e56b2..fbcae30 100644
--- a/test/Linker/DbgDeclare2.ll
+++ b/test/Linker/DbgDeclare2.ll
@@ -49,28 +49,29 @@ declare i32 @puts(i8*)
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"main.cpp", metadata !"/private/tmp", metadata !"clang version 3.3 (trunk 173515)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ]
+!0 = metadata !{i32 786449, metadata !25, i32 4, metadata !"clang version 3.3 (trunk 173515)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, null, metadata !""} ; [ DW_TAG_compile_unit ]
 !1 = metadata !{metadata !2}
 !2 = metadata !{i32 0}
-!3 = metadata !{metadata !4}
-!4 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, i32 0, metadata !6, metadata !"print_args", metadata !"print_args", metadata !"test", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32, i8**)* @test, null, null, metadata !1, i32 5} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 786473, metadata !"test.cpp", metadata !"/private/tmp", null} ; [ DW_TAG_file_type ]
+!3 = metadata !{metadata !5}
+!5 = metadata !{i32 786478, metadata !26, null, metadata !"print_args", metadata !"print_args", metadata !"test", i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32, i8**)* @test, null, null, metadata !1, i32 5} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 786473, metadata !26} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{null, metadata !9, metadata !10}
-!9 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !10 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ]
 !11 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ]
 !12 = metadata !{i32 786470, null, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !13} ; [ DW_TAG_const_type ]
-!13 = metadata !{i32 786468, null, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!13 = metadata !{i32 786468, null, null, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
 !14 = metadata !{i32 786689, metadata !5, metadata !"argc", metadata !6, i32 16777220, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
 !15 = metadata !{i32 4, i32 0, metadata !5, null}
 !16 = metadata !{i32 786689, metadata !5, metadata !"argv", metadata !6, i32 33554436, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ]
 !17 = metadata !{i32 786688, metadata !18, metadata !"i", metadata !6, i32 6, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ]
-!18 = metadata !{i32 786443, metadata !19, i32 6, i32 0, metadata !6, i32 1} ; [ DW_TAG_lexical_block ]
-!19 = metadata !{i32 786443, metadata !5, i32 5, i32 0, metadata !6, i32 0} ; [ DW_TAG_lexical_block ]
+!18 = metadata !{i32 786443, metadata !26, metadata !19, i32 6, i32 0, i32 1} ; [ DW_TAG_lexical_block ]
+!19 = metadata !{i32 786443, metadata !26, metadata !5, i32 5, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !20 = metadata !{i32 6, i32 0, metadata !18, null}
 !21 = metadata !{i32 8, i32 0, metadata !22, null}
-!22 = metadata !{i32 786443, metadata !18, i32 7, i32 0, metadata !6, i32 2} ; [ DW_TAG_lexical_block ]
+!22 = metadata !{i32 786443, metadata !26, metadata !18, i32 7, i32 0, i32 2} ; [ DW_TAG_lexical_block ]
 !23 = metadata !{i32 9, i32 0, metadata !22, null}
 !24 = metadata !{i32 10, i32 0, metadata !19, null}
+!25 = metadata !{metadata !"main.cpp", metadata !"/private/tmp"}
+!26 = metadata !{metadata !"test.cpp", metadata !"/private/tmp"}
diff --git a/test/MC/AArch64/basic-a64-diagnostics.s b/test/MC/AArch64/basic-a64-diagnostics.s
index 1e9024c..2e6e0bb 100644
--- a/test/MC/AArch64/basic-a64-diagnostics.s
+++ b/test/MC/AArch64/basic-a64-diagnostics.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -triple=aarch64 < %s 2> %t
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
 
 //------------------------------------------------------------------------------
@@ -2892,13 +2892,13 @@
         movi wzr, #0x44444444
         movi w3, #0xffff
         movi x9, #0x0000ffff00000000
-// CHECK-ERROR: error: invalid instruction
+// CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR-NEXT:         movi wzr, #0x44444444
 // CHECK-ERROR-NEXT:         ^
-// CHECK-ERROR: error: invalid instruction
+// CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR-NEXT:         movi w3, #0xffff
 // CHECK-ERROR-NEXT:         ^
-// CHECK-ERROR: error: invalid instruction
+// CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR-NEXT:         movi x9, #0x0000ffff00000000
 // CHECK-ERROR-NEXT:         ^
 
diff --git a/test/MC/AArch64/basic-a64-instructions.s b/test/MC/AArch64/basic-a64-instructions.s
index ad3064e..e4f6b21 100644
--- a/test/MC/AArch64/basic-a64-instructions.s
+++ b/test/MC/AArch64/basic-a64-instructions.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple=aarch64 -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
   .globl _func
 
 // Check that the assembler can handle the documented syntax from the ARM ARM.
diff --git a/test/MC/AArch64/elf-objdump.s b/test/MC/AArch64/elf-objdump.s
index 51d444a..3b3aa65 100644
--- a/test/MC/AArch64/elf-objdump.s
+++ b/test/MC/AArch64/elf-objdump.s
@@ -1,5 +1,5 @@
 // 64 bit little endian
-// RUN: llvm-mc -filetype=obj -triple aarch64-none-linux-gnu %s -o - | llvm-objdump -d
+// RUN: llvm-mc -filetype=obj -triple aarch64-none-linux-gnu %s -o - | llvm-objdump -d -
 
 // We just want to see if llvm-objdump works at all.
 // CHECK: .text
diff --git a/test/MC/AArch64/elf-reloc-addend.s b/test/MC/AArch64/elf-reloc-addend.s
new file mode 100644
index 0000000..0e7e2ca
--- /dev/null
+++ b/test/MC/AArch64/elf-reloc-addend.s
@@ -0,0 +1,8 @@
+// RUN: llvm-mc -triple=aarch64-linux-gnu -filetype=obj -o - %s | llvm-objdump -triple=aarch64-linux-gnu -r - | FileCheck %s
+
+	add x0, x4, #:lo12:sym
+// CHECK: 0 R_AARCH64_ADD_ABS_LO12_NC sym
+	add x3, x5, #:lo12:sym+1
+// CHECK: 4 R_AARCH64_ADD_ABS_LO12_NC sym+1
+	add x3, x5, #:lo12:sym-1
+// CHECK: 8 R_AARCH64_ADD_ABS_LO12_NC sym-1
diff --git a/test/MC/AArch64/gicv3-regs-diagnostics.s b/test/MC/AArch64/gicv3-regs-diagnostics.s
index e891adb..bc005b1 100644
--- a/test/MC/AArch64/gicv3-regs-diagnostics.s
+++ b/test/MC/AArch64/gicv3-regs-diagnostics.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s
 
         // Write-only
         mrs x10, icc_eoir1_el1
diff --git a/test/MC/AArch64/neon-aba-abd.s b/test/MC/AArch64/neon-aba-abd.s
new file mode 100644
index 0000000..178eb26
--- /dev/null
+++ b/test/MC/AArch64/neon-aba-abd.s
@@ -0,0 +1,78 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+//----------------------------------------------------------------------
+// Vector Absolute Difference and Accumulate (Signed, Unsigned)
+//----------------------------------------------------------------------
+         uaba v0.8b, v1.8b, v2.8b
+         uaba v0.16b, v1.16b, v2.16b
+         uaba v0.4h, v1.4h, v2.4h
+         uaba v0.8h, v1.8h, v2.8h
+         uaba v0.2s, v1.2s, v2.2s
+         uaba v0.4s, v1.4s, v2.4s
+
+// CHECK: uaba v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x7c,0x22,0x2e]
+// CHECK: uaba v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x7c,0x22,0x6e]
+// CHECK: uaba v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x7c,0x62,0x2e]
+// CHECK: uaba v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x7c,0x62,0x6e]
+// CHECK: uaba v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x7c,0xa2,0x2e]
+// CHECK: uaba v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x7c,0xa2,0x6e]
+
+
+         saba v0.8b, v1.8b, v2.8b
+         saba v0.16b, v1.16b, v2.16b
+         saba v0.4h, v1.4h, v2.4h
+         saba v0.8h, v1.8h, v2.8h
+         saba v0.2s, v1.2s, v2.2s
+         saba v0.4s, v1.4s, v2.4s
+
+// CHECK: saba v0.8b, v1.8b, v2.8b         // encoding: [0x20,0x7c,0x22,0x0e]
+// CHECK: saba v0.16b, v1.16b, v2.16b      // encoding: [0x20,0x7c,0x22,0x4e]
+// CHECK: saba v0.4h, v1.4h, v2.4h         // encoding: [0x20,0x7c,0x62,0x0e]
+// CHECK: saba v0.8h, v1.8h, v2.8h         // encoding: [0x20,0x7c,0x62,0x4e]
+// CHECK: saba v0.2s, v1.2s, v2.2s         // encoding: [0x20,0x7c,0xa2,0x0e]
+// CHECK: saba v0.4s, v1.4s, v2.4s         // encoding: [0x20,0x7c,0xa2,0x4e]
+
+//----------------------------------------------------------------------
+// Vector Absolute Difference (Signed, Unsigned)
+//----------------------------------------------------------------------
+         uabd v0.8b, v1.8b, v2.8b
+         uabd v0.16b, v1.16b, v2.16b
+         uabd v0.4h, v1.4h, v2.4h
+         uabd v0.8h, v1.8h, v2.8h
+         uabd v0.2s, v1.2s, v2.2s
+         uabd v0.4s, v1.4s, v2.4s
+
+// CHECK: uabd v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x74,0x22,0x2e]
+// CHECK: uabd v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x74,0x22,0x6e]
+// CHECK: uabd v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x74,0x62,0x2e]
+// CHECK: uabd v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x74,0x62,0x6e]
+// CHECK: uabd v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x74,0xa2,0x2e]
+// CHECK: uabd v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x74,0xa2,0x6e]
+
+         sabd v0.8b, v1.8b, v2.8b
+         sabd v0.16b, v1.16b, v2.16b
+         sabd v0.4h, v1.4h, v2.4h
+         sabd v0.8h, v1.8h, v2.8h
+         sabd v0.2s, v1.2s, v2.2s
+         sabd v0.4s, v1.4s, v2.4s
+
+// CHECK: sabd v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x74,0x22,0x0e]
+// CHECK: sabd v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x74,0x22,0x4e]
+// CHECK: sabd v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x74,0x62,0x0e]
+// CHECK: sabd v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x74,0x62,0x4e]
+// CHECK: sabd v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x74,0xa2,0x0e]
+// CHECK: sabd v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x74,0xa2,0x4e]
+
+//----------------------------------------------------------------------
+// Vector Absolute Difference (Floating Point)
+//----------------------------------------------------------------------
+         fabd v0.2s, v1.2s, v2.2s
+         fabd v31.4s, v15.4s, v16.4s
+         fabd v7.2d, v8.2d, v25.2d
+
+// CHECK: fabd v0.2s, v1.2s, v2.2s    // encoding: [0x20,0xd4,0xa2,0x2e]
+// CHECK: fabd v31.4s, v15.4s, v16.4s // encoding: [0xff,0xd5,0xb0,0x6e]
+// CHECK: fabd v7.2d, v8.2d, v25.2d   // encoding: [0x07,0xd5,0xf9,0x6e]
+
diff --git a/test/MC/AArch64/neon-add-pairwise.s b/test/MC/AArch64/neon-add-pairwise.s
new file mode 100644
index 0000000..b586c22
--- /dev/null
+++ b/test/MC/AArch64/neon-add-pairwise.s
@@ -0,0 +1,35 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+
+//------------------------------------------------------------------------------
+// Vector  Add Pairwise (Integer)
+//------------------------------------------------------------------------------
+         addp v0.8b, v1.8b, v2.8b
+         addp v0.16b, v1.16b, v2.16b
+         addp v0.4h, v1.4h, v2.4h
+         addp v0.8h, v1.8h, v2.8h
+         addp v0.2s, v1.2s, v2.2s
+         addp v0.4s, v1.4s, v2.4s
+         addp v0.2d, v1.2d, v2.2d
+
+// CHECK: addp v0.8b, v1.8b, v2.8b        // encoding: [0x20,0xbc,0x22,0x0e]
+// CHECK: addp v0.16b, v1.16b, v2.16b     // encoding: [0x20,0xbc,0x22,0x4e]
+// CHECK: addp v0.4h, v1.4h, v2.4h        // encoding: [0x20,0xbc,0x62,0x0e]
+// CHECK: addp v0.8h, v1.8h, v2.8h        // encoding: [0x20,0xbc,0x62,0x4e]
+// CHECK: addp v0.2s, v1.2s, v2.2s        // encoding: [0x20,0xbc,0xa2,0x0e]
+// CHECK: addp v0.4s, v1.4s, v2.4s        // encoding: [0x20,0xbc,0xa2,0x4e]
+// CHECK: addp v0.2d, v1.2d, v2.2d        // encoding: [0x20,0xbc,0xe2,0x4e]
+
+//------------------------------------------------------------------------------
+// Vector Add Pairwise (Floating Point
+//------------------------------------------------------------------------------
+         faddp v0.2s, v1.2s, v2.2s
+         faddp v0.4s, v1.4s, v2.4s
+         faddp v0.2d, v1.2d, v2.2d
+
+// CHECK: faddp v0.2s, v1.2s, v2.2s       // encoding: [0x20,0xd4,0x22,0x2e]
+// CHECK: faddp v0.4s, v1.4s, v2.4s       // encoding: [0x20,0xd4,0x22,0x6e]
+// CHECK: faddp v0.2d, v1.2d, v2.2d       // encoding: [0x20,0xd4,0x62,0x6e]
+
diff --git a/test/MC/AArch64/neon-add-sub-instructions.s b/test/MC/AArch64/neon-add-sub-instructions.s
new file mode 100644
index 0000000..863798e
--- /dev/null
+++ b/test/MC/AArch64/neon-add-sub-instructions.s
@@ -0,0 +1,82 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+
+//------------------------------------------------------------------------------
+// Vector Integer Add
+//------------------------------------------------------------------------------
+         add v0.8b, v1.8b, v2.8b
+         add v0.16b, v1.16b, v2.16b
+         add v0.4h, v1.4h, v2.4h
+         add v0.8h, v1.8h, v2.8h
+         add v0.2s, v1.2s, v2.2s
+         add v0.4s, v1.4s, v2.4s
+         add v0.2d, v1.2d, v2.2d
+
+// CHECK: add v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x84,0x22,0x0e]
+// CHECK: add v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x84,0x22,0x4e]
+// CHECK: add v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x84,0x62,0x0e]
+// CHECK: add v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x84,0x62,0x4e]
+// CHECK: add v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x84,0xa2,0x0e]
+// CHECK: add v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x84,0xa2,0x4e]
+// CHECK: add v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x84,0xe2,0x4e]
+
+//------------------------------------------------------------------------------
+// Vector Integer Sub
+//------------------------------------------------------------------------------
+         sub v0.8b, v1.8b, v2.8b
+         sub v0.16b, v1.16b, v2.16b
+         sub v0.4h, v1.4h, v2.4h
+         sub v0.8h, v1.8h, v2.8h
+         sub v0.2s, v1.2s, v2.2s
+         sub v0.4s, v1.4s, v2.4s
+         sub v0.2d, v1.2d, v2.2d
+
+// CHECK: sub v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x84,0x22,0x2e]
+// CHECK: sub v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x84,0x22,0x6e]
+// CHECK: sub v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x84,0x62,0x2e]
+// CHECK: sub v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x84,0x62,0x6e]
+// CHECK: sub v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x84,0xa2,0x2e]
+// CHECK: sub v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x84,0xa2,0x6e]
+// CHECK: sub v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x84,0xe2,0x6e]
+
+//------------------------------------------------------------------------------
+// Vector Floating-Point Add
+//------------------------------------------------------------------------------
+         fadd v0.2s, v1.2s, v2.2s
+         fadd v0.4s, v1.4s, v2.4s
+         fadd v0.2d, v1.2d, v2.2d
+
+// CHECK: fadd v0.2s, v1.2s, v2.2s       // encoding: [0x20,0xd4,0x22,0x0e]
+// CHECK: fadd v0.4s, v1.4s, v2.4s       // encoding: [0x20,0xd4,0x22,0x4e]
+// CHECK: fadd v0.2d, v1.2d, v2.2d       // encoding: [0x20,0xd4,0x62,0x4e]
+
+
+//------------------------------------------------------------------------------
+// Vector Floating-Point Sub
+//------------------------------------------------------------------------------
+         fsub v0.2s, v1.2s, v2.2s
+         fsub v0.4s, v1.4s, v2.4s
+         fsub v0.2d, v1.2d, v2.2d
+
+// CHECK: fsub v0.2s, v1.2s, v2.2s       // encoding: [0x20,0xd4,0xa2,0x0e]
+// CHECK: fsub v0.4s, v1.4s, v2.4s       // encoding: [0x20,0xd4,0xa2,0x4e]
+// CHECK: fsub v0.2d, v1.2d, v2.2d       // encoding: [0x20,0xd4,0xe2,0x4e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Add
+//------------------------------------------------------------------------------
+         add d31, d0, d16
+
+// CHECK: add d31, d0, d16       // encoding: [0x1f,0x84,0xf0,0x5e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Sub
+//------------------------------------------------------------------------------
+         sub d1, d7, d8
+
+// CHECK: sub d1, d7, d8       // encoding: [0xe1,0x84,0xe8,0x7e]
+
+
+
diff --git a/test/MC/AArch64/neon-bitwise-instructions.s b/test/MC/AArch64/neon-bitwise-instructions.s
new file mode 100644
index 0000000..79d0a9b
--- /dev/null
+++ b/test/MC/AArch64/neon-bitwise-instructions.s
@@ -0,0 +1,60 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+//------------------------------------------------------------------------------
+// Vector And
+//------------------------------------------------------------------------------
+         and v0.8b, v1.8b, v2.8b
+         and v0.16b, v1.16b, v2.16b
+
+// CHECK: and v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x1c,0x22,0x0e]
+// CHECK: and v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x1c,0x22,0x4e]
+
+
+//------------------------------------------------------------------------------
+// Vector Orr
+//------------------------------------------------------------------------------
+         orr v0.8b, v1.8b, v2.8b
+         orr v0.16b, v1.16b, v2.16b
+
+// CHECK: orr v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x1c,0xa2,0x0e]
+// CHECK: orr v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x1c,0xa2,0x4e]
+
+
+//------------------------------------------------------------------------------
+// Vector Eor
+//------------------------------------------------------------------------------
+         eor v0.8b, v1.8b, v2.8b
+         eor v0.16b, v1.16b, v2.16b
+
+// CHECK: eor v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x1c,0x22,0x2e]
+// CHECK: eor v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x1c,0x22,0x6e]
+
+
+//----------------------------------------------------------------------
+// Vector Bitwise
+//----------------------------------------------------------------------
+
+         bit v0.8b, v1.8b, v2.8b
+         bit v0.16b, v1.16b, v2.16b
+         bif v0.8b, v1.8b, v2.8b
+         bif v0.16b, v1.16b, v2.16b
+         bsl v0.8b, v1.8b, v2.8b
+         bsl v0.16b, v1.16b, v2.16b
+         orn v0.8b, v1.8b, v2.8b
+         orn v0.16b, v1.16b, v2.16b
+         bic v0.8b, v1.8b, v2.8b
+         bic v0.16b, v1.16b, v2.16b
+
+// CHECK: bit v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x1c,0xa2,0x2e]
+// CHECK: bit v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x1c,0xa2,0x6e]
+// CHECK: bif v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x1c,0xe2,0x2e]
+// CHECK: bif v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x1c,0xe2,0x6e]
+// CHECK: bsl v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x1c,0x62,0x2e]
+// CHECK: bsl v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x1c,0x62,0x6e]
+// CHECK: orn v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x1c,0xe2,0x0e]
+// CHECK: orn v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x1c,0xe2,0x4e]
+// CHECK: bic v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x1c,0x62,0x0e]
+// CHECK: bic v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x1c,0x62,0x4e]
+
diff --git a/test/MC/AArch64/neon-compare-instructions.s b/test/MC/AArch64/neon-compare-instructions.s
new file mode 100644
index 0000000..e4bc202
--- /dev/null
+++ b/test/MC/AArch64/neon-compare-instructions.s
@@ -0,0 +1,405 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Equal (Integer)
+//----------------------------------------------------------------------
+
+         cmeq v0.8b, v15.8b, v17.8b
+         cmeq v1.16b, v31.16b, v8.16b
+         cmeq v15.4h, v16.4h, v17.4h
+         cmeq v5.8h, v6.8h, v7.8h
+         cmeq v29.2s, v27.2s, v28.2s
+         cmeq v9.4s, v7.4s, v8.4s
+         cmeq v3.2d, v31.2d, v21.2d
+
+// CHECK: cmeq v0.8b, v15.8b, v17.8b    // encoding: [0xe0,0x8d,0x31,0x2e]
+// CHECK: cmeq v1.16b, v31.16b, v8.16b  // encoding: [0xe1,0x8f,0x28,0x6e]
+// CHECK: cmeq v15.4h, v16.4h, v17.4h   // encoding: [0x0f,0x8e,0x71,0x2e]
+// CHECK: cmeq v5.8h, v6.8h, v7.8h      // encoding: [0xc5,0x8c,0x67,0x6e]
+// CHECK: cmeq v29.2s, v27.2s, v28.2s   // encoding: [0x7d,0x8f,0xbc,0x2e]
+// CHECK: cmeq v9.4s, v7.4s, v8.4s      // encoding: [0xe9,0x8c,0xa8,0x6e]
+// CHECK: cmeq v3.2d, v31.2d, v21.2d    // encoding: [0xe3,0x8f,0xf5,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Higher or Same (Unsigned Integer)
+// Vector Compare Mask Less or Same (Unsigned Integer)
+// CMLS is alias for CMHS with operands reversed.
+//----------------------------------------------------------------------
+
+         cmhs v0.8b, v15.8b, v17.8b
+         cmhs v1.16b, v31.16b, v8.16b
+         cmhs v15.4h, v16.4h, v17.4h
+         cmhs v5.8h, v6.8h, v7.8h
+         cmhs v29.2s, v27.2s, v28.2s
+         cmhs v9.4s, v7.4s, v8.4s
+         cmhs v3.2d, v31.2d, v21.2d
+
+         cmls v0.8b, v17.8b, v15.8b
+         cmls v1.16b, v8.16b, v31.16b
+         cmls v15.4h, v17.4h, v16.4h
+         cmls v5.8h, v7.8h, v6.8h
+         cmls v29.2s, v28.2s, v27.2s
+         cmls v9.4s, v8.4s, v7.4s
+         cmls v3.2d, v21.2d, v31.2d
+
+// CHECK: cmhs v0.8b, v15.8b, v17.8b   // encoding: [0xe0,0x3d,0x31,0x2e]
+// CHECK: cmhs v1.16b, v31.16b, v8.16b // encoding: [0xe1,0x3f,0x28,0x6e]
+// CHECK: cmhs v15.4h, v16.4h, v17.4h  // encoding: [0x0f,0x3e,0x71,0x2e]
+// CHECK: cmhs v5.8h, v6.8h, v7.8h     // encoding: [0xc5,0x3c,0x67,0x6e]
+// CHECK: cmhs v29.2s, v27.2s, v28.2s  // encoding: [0x7d,0x3f,0xbc,0x2e]
+// CHECK: cmhs v9.4s, v7.4s, v8.4s     // encoding: [0xe9,0x3c,0xa8,0x6e]
+// CHECK: cmhs v3.2d, v31.2d, v21.2d   // encoding: [0xe3,0x3f,0xf5,0x6e]
+// CHECK: cmhs v0.8b, v15.8b, v17.8b   // encoding: [0xe0,0x3d,0x31,0x2e]
+// CHECK: cmhs v1.16b, v31.16b, v8.16b // encoding: [0xe1,0x3f,0x28,0x6e]
+// CHECK: cmhs v15.4h, v16.4h, v17.4h  // encoding: [0x0f,0x3e,0x71,0x2e]
+// CHECK: cmhs v5.8h, v6.8h, v7.8h     // encoding: [0xc5,0x3c,0x67,0x6e]
+// CHECK: cmhs v29.2s, v27.2s, v28.2s  // encoding: [0x7d,0x3f,0xbc,0x2e]
+// CHECK: cmhs v9.4s, v7.4s, v8.4s     // encoding: [0xe9,0x3c,0xa8,0x6e]
+// CHECK: cmhs v3.2d, v31.2d, v21.2d   // encoding: [0xe3,0x3f,0xf5,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than or Equal (Integer)
+// Vector Compare Mask Less Than or Equal (Integer)
+// CMLE is alias for CMGE with operands reversed.
+//----------------------------------------------------------------------
+
+         cmge v0.8b, v15.8b, v17.8b
+         cmge v1.16b, v31.16b, v8.16b
+         cmge v15.4h, v16.4h, v17.4h
+         cmge v5.8h, v6.8h, v7.8h
+         cmge v29.2s, v27.2s, v28.2s
+         cmge v9.4s, v7.4s, v8.4s
+         cmge v3.2d, v31.2d, v21.2d
+
+         cmle v0.8b, v17.8b, v15.8b
+         cmle v1.16b, v8.16b, v31.16b
+         cmle v15.4h, v17.4h, v16.4h
+         cmle v5.8h, v7.8h, v6.8h
+         cmle v29.2s, v28.2s, v27.2s
+         cmle v9.4s, v8.4s, v7.4s
+         cmle v3.2d, v21.2d, v31.2d
+
+// CHECK: cmge v0.8b, v15.8b, v17.8b    // encoding: [0xe0,0x3d,0x31,0x0e]
+// CHECK: cmge v1.16b, v31.16b, v8.16b  // encoding: [0xe1,0x3f,0x28,0x4e]
+// CHECK: cmge v15.4h, v16.4h, v17.4h   // encoding: [0x0f,0x3e,0x71,0x0e]
+// CHECK: cmge v5.8h, v6.8h, v7.8h      // encoding: [0xc5,0x3c,0x67,0x4e]
+// CHECK: cmge v29.2s, v27.2s, v28.2s   // encoding: [0x7d,0x3f,0xbc,0x0e]
+// CHECK: cmge v9.4s, v7.4s, v8.4s      // encoding: [0xe9,0x3c,0xa8,0x4e]
+// CHECK: cmge v3.2d, v31.2d, v21.2d    // encoding: [0xe3,0x3f,0xf5,0x4e]
+// CHECK: cmge v0.8b, v15.8b, v17.8b    // encoding: [0xe0,0x3d,0x31,0x0e]
+// CHECK: cmge v1.16b, v31.16b, v8.16b  // encoding: [0xe1,0x3f,0x28,0x4e]
+// CHECK: cmge v15.4h, v16.4h, v17.4h   // encoding: [0x0f,0x3e,0x71,0x0e]
+// CHECK: cmge v5.8h, v6.8h, v7.8h      // encoding: [0xc5,0x3c,0x67,0x4e]
+// CHECK: cmge v29.2s, v27.2s, v28.2s   // encoding: [0x7d,0x3f,0xbc,0x0e]
+// CHECK: cmge v9.4s, v7.4s, v8.4s      // encoding: [0xe9,0x3c,0xa8,0x4e]
+// CHECK: cmge v3.2d, v31.2d, v21.2d    // encoding: [0xe3,0x3f,0xf5,0x4e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Higher (Unsigned Integer)
+// Vector Compare Mask Lower (Unsigned Integer)
+// CMLO is alias for CMHI with operands reversed.
+//----------------------------------------------------------------------
+
+         cmhi v0.8b, v15.8b, v17.8b
+         cmhi v1.16b, v31.16b, v8.16b
+         cmhi v15.4h, v16.4h, v17.4h
+         cmhi v5.8h, v6.8h, v7.8h
+         cmhi v29.2s, v27.2s, v28.2s
+         cmhi v9.4s, v7.4s, v8.4s
+         cmhi v3.2d, v31.2d, v21.2d
+
+         cmlo v0.8b, v17.8b, v15.8b
+         cmlo v1.16b, v8.16b, v31.16b
+         cmlo v15.4h, v17.4h, v16.4h
+         cmlo v5.8h, v7.8h, v6.8h
+         cmlo v29.2s, v28.2s, v27.2s
+         cmlo v9.4s, v8.4s, v7.4s
+         cmlo v3.2d, v21.2d, v31.2d
+
+// CHECK: cmhi v0.8b, v15.8b, v17.8b    // encoding: [0xe0,0x35,0x31,0x2e]
+// CHECK: cmhi v1.16b, v31.16b, v8.16b  // encoding: [0xe1,0x37,0x28,0x6e]
+// CHECK: cmhi v15.4h, v16.4h, v17.4h   // encoding: [0x0f,0x36,0x71,0x2e]
+// CHECK: cmhi v5.8h, v6.8h, v7.8h      // encoding: [0xc5,0x34,0x67,0x6e]
+// CHECK: cmhi v29.2s, v27.2s, v28.2s   // encoding: [0x7d,0x37,0xbc,0x2e]
+// CHECK: cmhi v9.4s, v7.4s, v8.4s      // encoding: [0xe9,0x34,0xa8,0x6e]
+// CHECK: cmhi v3.2d, v31.2d, v21.2d    // encoding: [0xe3,0x37,0xf5,0x6e]
+// CHECK: cmhi v0.8b, v15.8b, v17.8b    // encoding: [0xe0,0x35,0x31,0x2e]
+// CHECK: cmhi v1.16b, v31.16b, v8.16b  // encoding: [0xe1,0x37,0x28,0x6e]
+// CHECK: cmhi v15.4h, v16.4h, v17.4h   // encoding: [0x0f,0x36,0x71,0x2e]
+// CHECK: cmhi v5.8h, v6.8h, v7.8h      // encoding: [0xc5,0x34,0x67,0x6e]
+// CHECK: cmhi v29.2s, v27.2s, v28.2s   // encoding: [0x7d,0x37,0xbc,0x2e]
+// CHECK: cmhi v9.4s, v7.4s, v8.4s      // encoding: [0xe9,0x34,0xa8,0x6e]
+// CHECK: cmhi v3.2d, v31.2d, v21.2d    // encoding: [0xe3,0x37,0xf5,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than (Integer)
+// Vector Compare Mask Less Than (Integer)
+// CMLT is alias for CMGT with operands reversed.
+//----------------------------------------------------------------------
+
+         cmgt v0.8b, v15.8b, v17.8b
+         cmgt v1.16b, v31.16b, v8.16b
+         cmgt v15.4h, v16.4h, v17.4h
+         cmgt v5.8h, v6.8h, v7.8h
+         cmgt v29.2s, v27.2s, v28.2s
+         cmgt v9.4s, v7.4s, v8.4s
+         cmgt v3.2d, v31.2d, v21.2d
+
+         cmlt v0.8b, v17.8b, v15.8b
+         cmlt v1.16b, v8.16b, v31.16b
+         cmlt v15.4h, v17.4h, v16.4h
+         cmlt v5.8h, v7.8h, v6.8h
+         cmlt v29.2s, v28.2s, v27.2s
+         cmlt v9.4s, v8.4s, v7.4s
+         cmlt v3.2d, v21.2d, v31.2d
+
+// CHECK: cmgt v0.8b, v15.8b, v17.8b    // encoding: [0xe0,0x35,0x31,0x0e]
+// CHECK: cmgt v1.16b, v31.16b, v8.16b  // encoding: [0xe1,0x37,0x28,0x4e]
+// CHECK: cmgt v15.4h, v16.4h, v17.4h   // encoding: [0x0f,0x36,0x71,0x0e]
+// CHECK: cmgt v5.8h, v6.8h, v7.8h      // encoding: [0xc5,0x34,0x67,0x4e]
+// CHECK: cmgt v29.2s, v27.2s, v28.2s   // encoding: [0x7d,0x37,0xbc,0x0e]
+// CHECK: cmgt v9.4s, v7.4s, v8.4s      // encoding: [0xe9,0x34,0xa8,0x4e]
+// CHECK: cmgt v3.2d, v31.2d, v21.2d    // encoding: [0xe3,0x37,0xf5,0x4e]
+// CHECK: cmgt v0.8b, v15.8b, v17.8b    // encoding: [0xe0,0x35,0x31,0x0e]
+// CHECK: cmgt v1.16b, v31.16b, v8.16b  // encoding: [0xe1,0x37,0x28,0x4e]
+// CHECK: cmgt v15.4h, v16.4h, v17.4h   // encoding: [0x0f,0x36,0x71,0x0e]
+// CHECK: cmgt v5.8h, v6.8h, v7.8h      // encoding: [0xc5,0x34,0x67,0x4e]
+// CHECK: cmgt v29.2s, v27.2s, v28.2s   // encoding: [0x7d,0x37,0xbc,0x0e]
+// CHECK: cmgt v9.4s, v7.4s, v8.4s      // encoding: [0xe9,0x34,0xa8,0x4e]
+// CHECK: cmgt v3.2d, v31.2d, v21.2d    // encoding: [0xe3,0x37,0xf5,0x4e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Bitwise Test (Integer)
+//----------------------------------------------------------------------
+
+         cmtst v0.8b, v15.8b, v17.8b
+         cmtst v1.16b, v31.16b, v8.16b
+         cmtst v15.4h, v16.4h, v17.4h
+         cmtst v5.8h, v6.8h, v7.8h
+         cmtst v29.2s, v27.2s, v28.2s
+         cmtst v9.4s, v7.4s, v8.4s
+         cmtst v3.2d, v31.2d, v21.2d
+
+// CHECK: cmtst v0.8b, v15.8b, v17.8b    // encoding: [0xe0,0x8d,0x31,0x0e]
+// CHECK: cmtst v1.16b, v31.16b, v8.16b  // encoding: [0xe1,0x8f,0x28,0x4e]
+// CHECK: cmtst v15.4h, v16.4h, v17.4h   // encoding: [0x0f,0x8e,0x71,0x0e]
+// CHECK: cmtst v5.8h, v6.8h, v7.8h      // encoding: [0xc5,0x8c,0x67,0x4e]
+// CHECK: cmtst v29.2s, v27.2s, v28.2s   // encoding: [0x7d,0x8f,0xbc,0x0e]
+// CHECK: cmtst v9.4s, v7.4s, v8.4s      // encoding: [0xe9,0x8c,0xa8,0x4e]
+// CHECK: cmtst v3.2d, v31.2d, v21.2d    // encoding: [0xe3,0x8f,0xf5,0x4e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Equal (Floating Point)
+//----------------------------------------------------------------------
+
+         fcmeq v0.2s, v31.2s, v16.2s
+         fcmeq v4.4s, v7.4s, v15.4s
+         fcmeq v29.2d, v2.2d, v5.2d
+
+// CHECK: fcmeq v0.2s, v31.2s, v16.2s // encoding: [0xe0,0xe7,0x30,0x0e]
+// CHECK: fcmeq v4.4s, v7.4s, v15.4s  // encoding: [0xe4,0xe4,0x2f,0x4e]
+// CHECK: fcmeq v29.2d, v2.2d, v5.2d  // encoding: [0x5d,0xe4,0x65,0x4e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than Or Equal (Floating Point)
+// Vector Compare Mask Less Than Or Equal (Floating Point)
+// FCMLE is alias for FCMGE with operands reversed.
+//----------------------------------------------------------------------
+
+         fcmge v31.4s, v29.4s, v28.4s
+         fcmge v3.2s, v8.2s, v12.2s
+         fcmge v17.2d, v15.2d, v13.2d
+         fcmle v31.4s, v28.4s, v29.4s
+         fcmle v3.2s,  v12.2s, v8.2s
+         fcmle v17.2d, v13.2d, v15.2d
+
+// CHECK: fcmge v31.4s, v29.4s, v28.4s  // encoding: [0xbf,0xe7,0x3c,0x6e]
+// CHECK: fcmge v3.2s, v8.2s, v12.2s    // encoding: [0x03,0xe5,0x2c,0x2e]
+// CHECK: fcmge v17.2d, v15.2d, v13.2d  // encoding: [0xf1,0xe5,0x6d,0x6e]
+// CHECK: fcmge v31.4s, v29.4s, v28.4s  // encoding: [0xbf,0xe7,0x3c,0x6e]
+// CHECK: fcmge v3.2s,  v8.2s, v12.2s   // encoding: [0x03,0xe5,0x2c,0x2e]
+// CHECK: fcmge v17.2d, v15.2d, v13.2d  // encoding: [0xf1,0xe5,0x6d,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than (Floating Point)
+// Vector Compare Mask Less Than (Floating Point)
+// FCMLT is alias for FCMGT with operands reversed.
+//----------------------------------------------------------------------
+
+         fcmgt v0.2s, v31.2s, v16.2s
+         fcmgt v4.4s, v7.4s, v15.4s
+         fcmgt v29.2d, v2.2d, v5.2d
+         fcmlt v0.2s, v16.2s, v31.2s
+         fcmlt v4.4s, v15.4s, v7.4s
+         fcmlt v29.2d, v5.2d, v2.2d
+
+// CHECK: fcmgt v0.2s, v31.2s, v16.2s  // encoding: [0xe0,0xe7,0xb0,0x2e]
+// CHECK: fcmgt v4.4s, v7.4s, v15.4s   // encoding: [0xe4,0xe4,0xaf,0x6e]
+// CHECK: fcmgt v29.2d, v2.2d, v5.2d   // encoding: [0x5d,0xe4,0xe5,0x6e]
+// CHECK: fcmgt v0.2s, v31.2s, v16.2s  // encoding: [0xe0,0xe7,0xb0,0x2e]
+// CHECK: fcmgt v4.4s, v7.4s, v15.4s   // encoding: [0xe4,0xe4,0xaf,0x6e]
+// CHECK: fcmgt v29.2d, v2.2d, v5.2d   // encoding: [0x5d,0xe4,0xe5,0x6e]
+
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Equal to Zero (Integer)
+//----------------------------------------------------------------------
+
+         cmeq v0.8b, v15.8b, #0
+         cmeq v1.16b, v31.16b, #0
+         cmeq v15.4h, v16.4h, #0
+         cmeq v5.8h, v6.8h, #0
+         cmeq v29.2s, v27.2s, #0
+         cmeq v9.4s, v7.4s, #0
+         cmeq v3.2d, v31.2d, #0
+
+// CHECK: cmeq v0.8b, v15.8b, #0x0    // encoding: [0xe0,0x99,0x20,0x0e]
+// CHECK: cmeq v1.16b, v31.16b, #0x0  // encoding: [0xe1,0x9b,0x20,0x4e]
+// CHECK: cmeq v15.4h, v16.4h, #0x0   // encoding: [0x0f,0x9a,0x60,0x0e]
+// CHECK: cmeq v5.8h, v6.8h, #0x0     // encoding: [0xc5,0x98,0x60,0x4e]
+// CHECK: cmeq v29.2s, v27.2s, #0x0   // encoding: [0x7d,0x9b,0xa0,0x0e]
+// CHECK: cmeq v9.4s, v7.4s, #0x0     // encoding: [0xe9,0x98,0xa0,0x4e]
+// CHECK: cmeq v3.2d, v31.2d, #0x0    // encoding: [0xe3,0x9b,0xe0,0x4e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
+//----------------------------------------------------------------------
+         cmge v0.8b, v15.8b, #0
+         cmge v1.16b, v31.16b, #0
+         cmge v15.4h, v16.4h, #0
+         cmge v5.8h, v6.8h, #0
+         cmge v29.2s, v27.2s, #0
+         cmge v17.4s, v20.4s, #0
+         cmge v3.2d, v31.2d, #0
+
+// CHECK: cmge v0.8b, v15.8b, #0x0    // encoding: [0xe0,0x89,0x20,0x2e]
+// CHECK: cmge v1.16b, v31.16b, #0x0  // encoding: [0xe1,0x8b,0x20,0x6e]
+// CHECK: cmge v15.4h, v16.4h, #0x0   // encoding: [0x0f,0x8a,0x60,0x2e]
+// CHECK: cmge v5.8h, v6.8h, #0x0     // encoding: [0xc5,0x88,0x60,0x6e]
+// CHECK: cmge v29.2s, v27.2s, #0x0   // encoding: [0x7d,0x8b,0xa0,0x2e]
+// CHECK: cmge v17.4s, v20.4s, #0x0   // encoding: [0x91,0x8a,0xa0,0x6e]
+// CHECK: cmge v3.2d, v31.2d, #0x0    // encoding: [0xe3,0x8b,0xe0,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than Zero (Signed Integer)
+//----------------------------------------------------------------------
+
+         cmgt v0.8b, v15.8b, #0
+         cmgt v1.16b, v31.16b, #0
+         cmgt v15.4h, v16.4h, #0
+         cmgt v5.8h, v6.8h, #0
+         cmgt v29.2s, v27.2s, #0
+         cmgt v9.4s, v7.4s, #0
+         cmgt v3.2d, v31.2d, #0
+
+// CHECK: cmgt v0.8b, v15.8b, #0x0    // encoding: [0xe0,0x89,0x20,0x0e]
+// CHECK: cmgt v1.16b, v31.16b, #0x0  // encoding: [0xe1,0x8b,0x20,0x4e]
+// CHECK: cmgt v15.4h, v16.4h, #0x0   // encoding: [0x0f,0x8a,0x60,0x0e]
+// CHECK: cmgt v5.8h, v6.8h, #0x0     // encoding: [0xc5,0x88,0x60,0x4e]
+// CHECK: cmgt v29.2s, v27.2s, #0x0   // encoding: [0x7d,0x8b,0xa0,0x0e]
+// CHECK: cmgt v9.4s, v7.4s, #0x0     // encoding: [0xe9,0x88,0xa0,0x4e]
+// CHECK: cmgt v3.2d, v31.2d, #0x0    // encoding: [0xe3,0x8b,0xe0,0x4e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
+//----------------------------------------------------------------------
+         cmle v0.8b, v15.8b, #0
+         cmle v1.16b, v31.16b, #0
+         cmle v15.4h, v16.4h, #0
+         cmle v5.8h, v6.8h, #0
+         cmle v29.2s, v27.2s, #0
+         cmle v9.4s, v7.4s, #0
+         cmle v3.2d, v31.2d, #0
+
+// CHECK: cmle v0.8b, v15.8b, #0x0    // encoding: [0xe0,0x99,0x20,0x2e]
+// CHECK: cmle v1.16b, v31.16b, #0x0  // encoding: [0xe1,0x9b,0x20,0x6e]
+// CHECK: cmle v15.4h, v16.4h, #0x0   // encoding: [0x0f,0x9a,0x60,0x2e]
+// CHECK: cmle v5.8h, v6.8h, #0x0     // encoding: [0xc5,0x98,0x60,0x6e]
+// CHECK: cmle v29.2s, v27.2s, #0x0   // encoding: [0x7d,0x9b,0xa0,0x2e]
+// CHECK: cmle v9.4s, v7.4s, #0x0     // encoding: [0xe9,0x98,0xa0,0x6e]
+// CHECK: cmle v3.2d, v31.2d, #0x0    // encoding: [0xe3,0x9b,0xe0,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Less Than Zero (Signed Integer)
+//----------------------------------------------------------------------
+         cmlt v0.8b, v15.8b, #0
+         cmlt v1.16b, v31.16b, #0
+         cmlt v15.4h, v16.4h, #0
+         cmlt v5.8h, v6.8h, #0
+         cmlt v29.2s, v27.2s, #0
+         cmlt v9.4s, v7.4s, #0
+         cmlt v3.2d, v31.2d, #0
+
+// CHECK: cmlt v0.8b, v15.8b, #0x0    // encoding: [0xe0,0xa9,0x20,0x0e]
+// CHECK: cmlt v1.16b, v31.16b, #0x0  // encoding: [0xe1,0xab,0x20,0x4e]
+// CHECK: cmlt v15.4h, v16.4h, #0x0   // encoding: [0x0f,0xaa,0x60,0x0e]
+// CHECK: cmlt v5.8h, v6.8h, #0x0     // encoding: [0xc5,0xa8,0x60,0x4e]
+// CHECK: cmlt v29.2s, v27.2s, #0x0   // encoding: [0x7d,0xab,0xa0,0x0e]
+// CHECK: cmlt v9.4s, v7.4s, #0x0     // encoding: [0xe9,0xa8,0xa0,0x4e]
+// CHECK: cmlt v3.2d, v31.2d, #0x0    // encoding: [0xe3,0xab,0xe0,0x4e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Equal to Zero (Floating Point)
+//----------------------------------------------------------------------
+         fcmeq v0.2s, v31.2s, #0.0
+         fcmeq v4.4s, v7.4s, #0.0
+         fcmeq v29.2d, v2.2d, #0.0
+
+// CHECK: fcmeq v0.2s, v31.2s, #0.0  // encoding: [0xe0,0xdb,0xa0,0x0e]
+// CHECK: fcmeq v4.4s, v7.4s, #0.0   // encoding: [0xe4,0xd8,0xa0,0x4e]
+// CHECK: fcmeq v29.2d, v2.2d, #0.0  // encoding: [0x5d,0xd8,0xe0,0x4e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
+//----------------------------------------------------------------------
+         fcmge v31.4s, v29.4s, #0.0
+         fcmge v3.2s, v8.2s, #0.0
+         fcmge v17.2d, v15.2d, #0.0
+
+// CHECK: fcmge v31.4s, v29.4s, #0.0  // encoding: [0xbf,0xcb,0xa0,0x6e]
+// CHECK: fcmge v3.2s, v8.2s, #0.0    // encoding: [0x03,0xc9,0xa0,0x2e]
+// CHECK: fcmge v17.2d, v15.2d, #0.0   // encoding: [0xf1,0xc9,0xe0,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than Zero (Floating Point)
+//----------------------------------------------------------------------
+         fcmgt v0.2s, v31.2s, #0.0
+         fcmgt v4.4s, v7.4s, #0.0
+         fcmgt v29.2d, v2.2d, #0.0
+
+// CHECK: fcmgt v0.2s, v31.2s, #0.0   // encoding: [0xe0,0xcb,0xa0,0x0e]
+// CHECK: fcmgt v4.4s, v7.4s, #0.0    // encoding: [0xe4,0xc8,0xa0,0x4e]
+// CHECK: fcmgt v29.2d, v2.2d, #0.0   // encoding: [0x5d,0xc8,0xe0,0x4e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Less Than or Equal To Zero (Floating Point)
+//----------------------------------------------------------------------
+         fcmle v1.4s, v8.4s, #0.0
+         fcmle v3.2s, v20.2s, #0.0
+         fcmle v7.2d, v13.2d, #0.0
+
+// CHECK: fcmle v1.4s, v8.4s, #0.0   // encoding: [0x01,0xd9,0xa0,0x6e]
+// CHECK: fcmle v3.2s, v20.2s, #0.0  // encoding: [0x83,0xda,0xa0,0x2e]
+// CHECK: fcmle v7.2d, v13.2d, #0.0  // encoding: [0xa7,0xd9,0xe0,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Less Than Zero (Floating Point)
+//----------------------------------------------------------------------
+         fcmlt v16.2s, v2.2s, #0.0
+         fcmlt v15.4s, v4.4s, #0.0
+         fcmlt v5.2d, v29.2d, #0.0
+
+// CHECK: fcmlt v16.2s, v2.2s, #0.0   // encoding: [0x50,0xe8,0xa0,0x0e]
+// CHECK: fcmlt v15.4s, v4.4s, #0.0   // encoding: [0x8f,0xe8,0xa0,0x4e]
+// CHECK: fcmlt v5.2d, v29.2d, #0.0   // encoding: [0xa5,0xeb,0xe0,0x4e]
+
+
+
+
+
+
+
+
+
diff --git a/test/MC/AArch64/neon-diagnostics.s b/test/MC/AArch64/neon-diagnostics.s
new file mode 100644
index 0000000..5373889
--- /dev/null
+++ b/test/MC/AArch64/neon-diagnostics.s
@@ -0,0 +1,1207 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
+
+//------------------------------------------------------------------------------
+// Vector Integer Add/sub
+//------------------------------------------------------------------------------
+
+        // Mismatched vector types
+        add v0.16b, v1.8b, v2.8b
+        sub v0.2d, v1.2d, v2.2s
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         add v0.16b, v1.8b, v2.8b
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         sub v0.2d, v1.2d, v2.2s
+// CHECK-ERROR:                              ^
+
+//------------------------------------------------------------------------------
+// Vector Floating-Point Add/sub
+//------------------------------------------------------------------------------
+
+        // Mismatched and invalid vector types
+        fadd v0.2d, v1.2s, v2.2s
+        fsub v0.4s, v1.2s, v2.4s
+        fsub v0.8b, v1.8b, v2.8b
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         fadd v0.2d, v1.2s, v2.2s
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         fsub v0.4s, v1.2s, v2.4s
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         fsub v0.8b, v1.8b, v2.8b
+// CHECK-ERROR:                  ^
+
+//----------------------------------------------------------------------
+// Vector Integer Mul
+//----------------------------------------------------------------------
+
+        // Mismatched and invalid vector types
+        mul v0.16b, v1.8b, v2.8b
+        mul v0.2d, v1.2d, v2.2d
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         mul v0.16b, v1.8b, v2.8b
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         mul v0.2d, v1.2d, v2.2d
+// CHECK-ERROR:                ^
+
+//----------------------------------------------------------------------
+// Vector Floating-Point Mul/Div
+//----------------------------------------------------------------------
+        // Mismatched vector types
+        fmul v0.16b, v1.8b, v2.8b
+        fdiv v0.2s, v1.2d, v2.2d
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         fmul v0.16b, v1.8b, v2.8b
+// CHECK-ERROR:                         ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         fdiv v0.2s, v1.2d, v2.2d
+// CHECK-ERROR:                        ^
+
+//----------------------------------------------------------------------
+// Vector And Orr Eor Bsl Bit Bif, Orn, Bic,
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        and v0.8b, v1.16b, v2.8b
+        orr v0.4h, v1.4h, v2.4h
+        eor v0.2s, v1.2s, v2.2s
+        bsl v0.8b, v1.16b, v2.8b
+        bsl v0.2s, v1.2s, v2.2s
+        bit v0.2d, v1.2d, v2.2d
+        bif v0.4h, v1.4h, v2.4h
+        orn v0.8b, v1.16b, v2.16b
+        bic v0.2d, v1.2d, v2.2d
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         and v0.8b, v1.16b, v2.8b
+// CHECK-ERROR:                       ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         orr v0.4h, v1.4h, v2.4h
+// CHECK-ERROR:                ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         eor v0.2s, v1.2s, v2.2s
+// CHECK-ERROR:                ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         bsl v0.8b, v1.16b, v2.8b
+// CHECK-ERROR:                       ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         bsl v0.2s, v1.2s, v2.2s
+// CHECK-ERROR:                ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         bit v0.2d, v1.2d, v2.2d
+// CHECK-ERROR:                ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         bif v0.4h, v1.4h, v2.4h
+// CHECK-ERROR:                ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         orn v0.8b, v1.16b, v2.16b
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         bic v0.2d, v1.2d, v2.2d
+// CHECK-ERROR:                ^
+
+//----------------------------------------------------------------------
+// Vector Integer Multiply-accumulate and Multiply-subtract
+//----------------------------------------------------------------------
+
+        // Mismatched and invalid vector types
+        mla v0.16b, v1.8b, v2.8b
+        mls v0.2d, v1.2d, v2.2d
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         mla v0.16b, v1.8b, v2.8b
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         mls v0.2d, v1.2d, v2.2d
+// CHECK-ERROR:                ^
+
+//----------------------------------------------------------------------
+// Vector Floating-Point Multiply-accumulate and Multiply-subtract
+//----------------------------------------------------------------------
+        // Mismatched vector types
+        fmla v0.2s, v1.2d, v2.2d
+        fmls v0.16b, v1.8b, v2.8b
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         fmla v0.2s, v1.2d, v2.2d
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         fmls v0.16b, v1.8b, v2.8b
+// CHECK-ERROR:                         ^
+
+
+//----------------------------------------------------------------------
+// Vector Move Immediate Shifted
+// Vector Move Inverted Immediate Shifted
+// Vector Bitwise Bit Clear (AND NOT) - immediate
+// Vector Bitwise OR - immedidate
+//----------------------------------------------------------------------
+      // out of range immediate (0 to 0xff)
+      movi v0.2s, #-1
+      mvni v1.4s, #256
+      // out of range shift (0, 8, 16, 24 and 0, 8)
+      bic v15.4h, #1, lsl #7
+      orr v31.2s, #1, lsl #25
+      movi v5.4h, #10, lsl #16
+      // invalid vector type (2s, 4s, 4h, 8h)
+      movi v5.8b, #1, lsl #8
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:          movi v0.2s, #-1
+// CHECK-ERROR:                      ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         mvni v1.4s, #256
+// CHECK-ERROR:                     ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         bic v15.4h, #1, lsl #7
+// CHECK-ERROR:                         ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         orr v31.2s, #1, lsl #25
+// CHECK-ERROR:                         ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         movi v5.4h, #10, lsl #16
+// CHECK-ERROR:                          ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         movi v5.8b, #1, lsl #8
+// CHECK-ERROR:                         ^
+//----------------------------------------------------------------------
+// Vector Move Immediate Masked
+// Vector Move Inverted Immediate Masked
+//----------------------------------------------------------------------
+      // out of range immediate (0 to 0xff)
+      movi v0.2s, #-1, msl #8
+      mvni v7.4s, #256, msl #16
+      // out of range shift (8, 16)
+      movi v3.2s, #1, msl #0
+      mvni v17.4s, #255, msl #32
+      // invalid vector type (2s, 4s)
+      movi v5.4h, #31, msl #8
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         movi v0.2s, #-1, msl #8
+// CHECK-ERROR:                     ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         mvni v7.4s, #256, msl #16
+// CHECK-ERROR:                     ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         movi v3.2s, #1, msl #0
+// CHECK-ERROR:                         ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         mvni v17.4s, #255, msl #32
+// CHECK-ERROR:                            ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         movi v5.4h, #31, msl #8
+// CHECK-ERROR:                          ^
+
+//----------------------------------------------------------------------
+// Vector Immediate - per byte
+//----------------------------------------------------------------------
+        // out of range immediate (0 to 0xff)
+        movi v0.8b, #-1
+        movi v1.16b, #256
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         movi v0.8b, #-1
+// CHECK-ERROR:                     ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         movi v1.16b, #256
+// CHECK-ERROR:                      ^
+
+
+//----------------------------------------------------------------------
+// Vector Move Immediate - bytemask, per doubleword
+//---------------------------------------------------------------------
+        // invalid bytemask (0x00 or 0xff)
+        movi v0.2d, #0x10ff00ff00ff00ff
+
+// CHECK:ERROR: error: invalid operand for instruction
+// CHECK:ERROR:         movi v0.2d, #0x10ff00ff00ff00ff
+// CHECK:ERROR:                     ^
+
+//----------------------------------------------------------------------
+// Vector Move Immediate - bytemask, one doubleword
+//----------------------------------------------------------------------
+        // invalid bytemask (0x00 or 0xff)
+        movi v0.2d, #0xffff00ff001f00ff
+
+// CHECK:ERROR: error: invalid operand for instruction
+// CHECK:ERROR:         movi v0.2d, #0xffff00ff001f00ff
+// CHECK:ERROR:                     ^
+//----------------------------------------------------------------------
+// Vector Floating Point Move Immediate
+//----------------------------------------------------------------------
+        // invalid vector type (2s, 4s, 2d)
+         fmov v0.4h, #1.0
+
+// CHECK:ERROR: error: invalid operand for instruction
+// CHECK:ERROR:         fmov v0.4h, #1.0
+// CHECK:ERROR:              ^
+
+//----------------------------------------------------------------------
+// Vector Move -  register
+//----------------------------------------------------------------------
+      // invalid vector type (8b, 16b)
+      mov v0.2s, v31.8b
+// CHECK:ERROR: error: invalid operand for instruction
+// CHECK:ERROR:         mov v0.2s, v31.8b
+// CHECK:ERROR:                ^
+
+//----------------------------------------------------------------------
+// Vector Absolute Difference and Accumulate (Signed, Unsigned)
+//----------------------------------------------------------------------
+
+        // Mismatched and invalid vector types (2d)
+        saba v0.16b, v1.8b, v2.8b
+        uaba v0.2d, v1.2d, v2.2d
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         saba v0.16b, v1.8b, v2.8b
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         uaba v0.2d, v1.2d, v2.2d
+// CHECK-ERROR:                ^
+
+//----------------------------------------------------------------------
+// Vector Absolute Difference and Accumulate (Signed, Unsigned)
+// Vector Absolute Difference (Signed, Unsigned)
+
+        // Mismatched and invalid vector types (2d)
+        uaba v0.16b, v1.8b, v2.8b
+        saba v0.2d, v1.2d, v2.2d
+        uabd v0.4s, v1.2s, v2.2s
+        sabd v0.4h, v1.8h, v8.8h
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         uaba v0.16b, v1.8b, v2.8b
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         saba v0.2d, v1.2d, v2.2d
+// CHECK-ERROR:                ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         uabd v0.4s, v1.2s, v2.2s
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         sabd v0.4h, v1.8h, v8.8h
+// CHECK-ERROR:                        ^
+
+//----------------------------------------------------------------------
+// Vector Absolute Difference (Floating Point)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        fabd v0.2s, v1.4s, v2.2d
+        fabd v0.4h, v1.4h, v2.4h
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         fabd v0.2s, v1.4s, v2.2d
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         fabd v0.4h, v1.4h, v2.4h
+// CHECK-ERROR:                 ^
+//----------------------------------------------------------------------
+// Vector Multiply (Polynomial)
+//----------------------------------------------------------------------
+
+        // Mismatched and invalid vector types
+         pmul v0.8b, v1.8b, v2.16b
+         pmul v0.2s, v1.2s, v2.2s
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         pmul v0.8b, v1.8b, v2.16b
+// CHECK-ERROR:                               ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         pmul v0.2s, v1.2s, v2.2s
+// CHECK-ERROR:                 ^
+
+//----------------------------------------------------------------------
+// Scalar Integer Add and Sub
+//----------------------------------------------------------------------
+
+      // Mismatched registers
+         add d0, s1, d2
+         sub s1, d1, d2
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         add d0, s1, d2
+// CHECK-ERROR:                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         sub s1, d1, d2
+// CHECK-ERROR:             ^
+
+//----------------------------------------------------------------------
+// Vector Reciprocal Step (Floating Point)
+//----------------------------------------------------------------------
+
+        // Mismatched and invalid vector types
+         frecps v0.4s, v1.2d, v2.4s
+         frecps v0.8h, v1.8h, v2.8h
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        frecps v0.4s, v1.2d, v2.4s
+// CHECK-ERROR:                         ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        frecps v0.8h, v1.8h, v2.8h
+// CHECK-ERROR:                  ^
+
+//----------------------------------------------------------------------
+// Vector Reciprocal Square Root Step (Floating Point)
+//----------------------------------------------------------------------
+
+        // Mismatched and invalid vector types
+         frsqrts v0.2d, v1.2d, v2.2s
+         frsqrts v0.4h, v1.4h, v2.4h
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        frsqrts v0.2d, v1.2d, v2.2s
+// CHECK-ERROR:                                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        frsqrts v0.4h, v1.4h, v2.4h
+// CHECK-ERROR:                   ^
+
+
+//----------------------------------------------------------------------
+// Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
+//----------------------------------------------------------------------
+
+        // Mismatched and invalid vector types
+        facge v0.2d, v1.2s, v2.2d
+        facge v0.4h, v1.4h, v2.4h
+        facle v0.8h, v1.4h, v2.4h
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        facge v0.2d, v1.2s, v2.2d
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        facge v0.4h, v1.4h, v2.4h
+// CHECK-ERROR:                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        facle v0.8h, v1.4h, v2.4h
+// CHECK-ERROR:                 ^
+//----------------------------------------------------------------------
+// Vector Absolute Compare Mask Less Than (Floating Point)
+//----------------------------------------------------------------------
+
+        // Mismatched and invalid vector types
+        facgt v0.2d, v1.2d, v2.4s
+        facgt v0.8h, v1.8h, v2.8h
+        faclt v0.8b, v1.8b, v2.8b
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        facgt v0.2d, v1.2d, v2.4s
+// CHECK-ERROR:                               ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        facgt v0.8h, v1.8h, v2.8h
+// CHECK-ERROR:                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        faclt v0.8b, v1.8b, v2.8b
+// CHECK-ERROR:                 ^
+
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Equal (Integer)
+//----------------------------------------------------------------------
+
+         // Mismatched vector types
+         cmeq c0.2d, v1.2d, v2.2s
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        cmeq c0.2d, v1.2d, v2.2s
+// CHECK-ERROR:                              ^
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Higher or Same (Unsigned Integer)
+// Vector Compare Mask Less or Same (Unsigned Integer)
+// CMLS is alias for CMHS with operands reversed.
+//----------------------------------------------------------------------
+
+         // Mismatched vector types
+         cmhs c0.4h, v1.8b, v2.8b
+         cmls c0.16b, v1.16b, v2.2d
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        cmhs c0.4h, v1.8b, v2.8b
+// CHECK-ERROR:                       ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        cmls c0.16b, v1.16b, v2.2d
+// CHECK-ERROR:                                ^
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than or Equal (Integer)
+// Vector Compare Mask Less Than or Equal (Integer)
+// CMLE is alias for CMGE with operands reversed.
+//----------------------------------------------------------------------
+
+         // Mismatched vector types
+         cmge c0.8h, v1.8b, v2.8b
+         cmle c0.4h, v1.2s, v2.2s
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        cmge c0.8h, v1.8b, v2.8b
+// CHECK-ERROR:                       ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         cmle c0.4h, v1.2s, v2.2s
+// CHECK-ERROR:                        ^
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Higher (Unsigned Integer)
+// Vector Compare Mask Lower (Unsigned Integer)
+// CMLO is alias for CMHI with operands reversed.
+//----------------------------------------------------------------------
+
+         // Mismatched vector types
+         cmhi c0.4s, v1.4s, v2.16b
+         cmlo c0.8b, v1.8b, v2.2s
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        cmhi c0.4s, v1.4s, v2.16b
+// CHECK-ERROR:                              ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         cmlo c0.8b, v1.8b, v2.2s
+// CHECK-ERROR:                               ^
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than (Integer)
+// Vector Compare Mask Less Than (Integer)
+// CMLT is alias for CMGT with operands reversed.
+//----------------------------------------------------------------------
+
+         // Mismatched vector types
+         cmgt c0.8b, v1.4s, v2.16b
+         cmlt c0.8h, v1.16b, v2.4s
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         cmgt c0.8b, v1.4s, v2.16b
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         cmlt c0.8h, v1.16b, v2.4s
+// CHECK-ERROR:                        ^
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Bitwise Test (Integer)
+//----------------------------------------------------------------------
+
+         // Mismatched vector types
+         cmtst c0.16b, v1.16b, v2.4s
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         cmtst c0.16b, v1.16b, v2.4s
+// CHECK-ERROR:                                  ^
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Equal (Floating Point)
+//----------------------------------------------------------------------
+
+        // Mismatched and invalid vector types
+        fcmeq v0.2d, v1.2s, v2.2d
+        fcmeq v0.16b, v1.16b, v2.16b
+        fcmeq v0.8b, v1.4h, v2.4h
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmeq v0.2d, v1.2s, v2.2d
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmeq v0.16b, v1.16b, v2.16b
+// CHECK-ERROR:                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmeq v0.8b, v1.4h, v2.4h
+// CHECK-ERROR:                 ^
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than Or Equal (Floating Point)
+// Vector Compare Mask Less Than Or Equal (Floating Point)
+// FCMLE is alias for FCMGE with operands reversed.
+//----------------------------------------------------------------------
+
+        // Mismatched and invalid vector types
+         fcmge v31.4s, v29.2s, v28.4s
+         fcmge v3.8b, v8.2s, v12.2s
+         fcmle v17.8h, v15.2d, v13.2d
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmge v31.4s, v29.2s, v28.4s
+// CHECK-ERROR:                          ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmge v3.8b, v8.2s, v12.2s
+// CHECK-ERROR:                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmle v17.8h, v15.2d, v13.2d
+// CHECK-ERROR:                 ^
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than (Floating Point)
+// Vector Compare Mask Less Than (Floating Point)
+// FCMLT is alias for FCMGT with operands reversed.
+//----------------------------------------------------------------------
+
+        // Mismatched and invalid vector types
+         fcmgt v0.2d, v31.2s, v16.2s
+         fcmgt v4.4s, v7.4s, v15.4h
+         fcmlt v29.2d, v5.2d, v2.16b
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmgt v0.2d, v31.2s, v16.2s
+// CHECK-ERROR:                         ^
+// CHECK-ERROR: error: expected floating-point constant #0.0 or invalid register type
+// CHECK-ERROR:        fcmgt v4.4s, v7.4s, v15.4h
+// CHECK-ERROR:                                ^
+// CHECK-ERROR: error: expected floating-point constant #0.0 or invalid register type
+// CHECK-ERROR:        fcmlt v29.2d, v5.2d, v2.16b
+// CHECK-ERROR:                                ^
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Equal to Zero (Integer)
+//----------------------------------------------------------------------
+        // Mismatched vector types and invalid imm
+         // Mismatched vector types
+         cmeq c0.2d, v1.2s, #0
+         cmeq c0.2d, v1.2d, #1
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        cmeq c0.2d, v1.2s, #0
+// CHECK-ERROR:                       ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        cmeq c0.2d, v1.2d, #1
+// CHECK-ERROR:                            ^
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
+//----------------------------------------------------------------------
+        // Mismatched vector types and invalid imm
+         cmge c0.8h, v1.8b, #0
+         cmge c0.4s, v1.4s, #-1
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        cmge c0.8h, v1.8b, #0
+// CHECK-ERROR:                       ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         cmge c0.4s, v1.4s, #-1
+// CHECK-ERROR:                             ^
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than Zero (Signed Integer)
+//----------------------------------------------------------------------
+        // Mismatched vector types and invalid imm
+         cmgt c0.8b, v1.4s, #0
+         cmgt c0.8b, v1.8b, #-255
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         cmgt c0.8b, v1.4s, #0
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         cmgt c0.8b, v1.8b, #-255
+// CHECK-ERROR:                             ^
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
+//----------------------------------------------------------------------
+        // Mismatched vector types and invalid imm
+         cmle c0.4h, v1.2s, #0
+         cmle c0.16b, v1.16b, #16
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        cmle c0.4h, v1.2s, #0
+// CHECK-ERROR:                       ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         cmle c0.16b, v1.16b, #16
+// CHECK-ERROR:                               ^
+//----------------------------------------------------------------------
+// Vector Compare Mask Less Than Zero (Signed Integer)
+//----------------------------------------------------------------------
+        // Mismatched vector types and invalid imm
+         cmlt c0.8h, v1.16b, #0
+         cmlt c0.8h, v1.8h, #-15
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         cmlt c0.8h, v1.16b, #0
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         cmlt c0.8h, v1.8h, #-15
+// CHECK-ERROR:                             ^
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Equal to Zero (Floating Point)
+//----------------------------------------------------------------------
+
+        // Mismatched and invalid vector types, invalid imm
+        fcmeq v0.2d, v1.2s, #0.0
+        fcmeq v0.16b, v1.16b, #0.0
+        fcmeq v0.8b, v1.4h, #1.0
+        fcmeq v0.8b, v1.4h, #1
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmeq v0.2d, v1.2s, #0.0
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmeq v0.16b, v1.16b, #0.0
+// CHECK-ERROR:                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmeq v0.8b, v1.4h, #1.0
+// CHECK-ERROR:                             ^
+// CHECK-ERROR: error:  Expected floating-point immediate
+// CHECK-ERROR:        fcmeq v0.8b, v1.4h, #1
+// CHECK-ERROR:                             ^
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
+//----------------------------------------------------------------------
+
+        // Mismatched and invalid vector types, invalid imm
+         fcmge v31.4s, v29.2s, #0.0
+         fcmge v3.8b, v8.2s, #0.0
+         fcmle v17.8h, v15.2d, #-1.0
+         fcmle v17.8h, v15.2d, #0
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmge v31.4s, v29.2s, #0.0
+// CHECK-ERROR:                          ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmge v3.8b, v8.2s, #0.0
+// CHECK-ERROR:                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmle v17.8h, v15.2d, #-1.0
+// CHECK-ERROR:                               ^
+// CHECK-ERROR: error:  Expected floating-point immediate
+// CHECK-ERROR:        fcmle v17.8h, v15.2d, #0
+// CHECK-ERROR:                               ^
+//----------------------------------------------------------------------
+// Vector Compare Mask Greater Than Zero (Floating Point)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types, invalid imm
+         fcmgt v0.2d, v31.2s, #0.0
+         fcmgt v4.4s, v7.4h, #0.0
+         fcmlt v29.2d, v5.2d, #255.0
+         fcmlt v29.2d, v5.2d, #255
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmgt v0.2d, v31.2s, #0.0
+// CHECK-ERROR:                         ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmgt v4.4s, v7.4h, #0.0
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: expected floating-point constant #0.0 or invalid register type
+// CHECK-ERROR:        fcmlt v29.2d, v5.2d, #255.0
+// CHECK-ERROR:                              ^
+// CHECK-ERROR: error:  Expected floating-point immediate
+// CHECK-ERROR:        fcmlt v29.2d, v5.2d, #255
+// CHECK-ERROR:                              ^
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Less Than or Equal To Zero (Floating Point)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types, invalid imm
+         fcmge v31.4s, v29.2s, #0.0
+         fcmge v3.8b, v8.2s, #0.0
+         fcmle v17.2d, v15.2d, #15.0
+         fcmle v17.2d, v15.2d, #15
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmge v31.4s, v29.2s, #0.0
+// CHECK-ERROR:                          ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmge v3.8b, v8.2s, #0.0
+// CHECK-ERROR:                 ^
+// CHECK-ERROR: error: expected floating-point constant #0.0 or invalid register type
+// CHECK-ERROR:        fcmle v17.2d, v15.2d, #15.0
+// CHECK-ERROR:                               ^
+// CHECK-ERROR: error:  Expected floating-point immediate
+// CHECK-ERROR:        fcmle v17.2d, v15.2d, #15
+// CHECK-ERROR:                              ^
+
+//----------------------------------------------------------------------
+// Vector Compare Mask Less Than Zero (Floating Point)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types, invalid imm
+         fcmgt v0.2d, v31.2s, #0.0
+         fcmgt v4.4s, v7.4h, #0.0
+         fcmlt v29.2d, v5.2d, #16.0
+         fcmlt v29.2d, v5.2d, #2
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmgt v0.2d, v31.2s, #0.0
+// CHECK-ERROR:                         ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fcmgt v4.4s, v7.4h, #0.0
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: expected floating-point constant #0.0 or invalid register type
+// CHECK-ERROR:        fcmlt v29.2d, v5.2d, #16.0
+// CHECK-ERROR:                              ^
+// CHECK-ERROR: error:  Expected floating-point immediate
+// CHECK-ERROR:        fcmlt v29.2d, v5.2d, #2
+// CHECK-ERROR:                              ^
+
+/-----------------------------------------------------------------------
+// Vector Integer Halving Add (Signed)
+// Vector Integer Halving Add (Unsigned)
+// Vector Integer Halving Sub (Signed)
+// Vector Integer Halving Sub (Unsigned)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types (2d)
+        shadd v0.2d, v1.2d, v2.2d
+        uhadd v4.2s, v5.2s, v5.4h
+        shsub v11.4h, v12.8h, v13.4h
+        uhsub v31.16b, v29.8b, v28.8b
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        shadd v0.2d, v1.2d, v2.2d
+// CHECK-ERROR:                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        uhadd v4.2s, v5.2s, v5.4h
+// CHECK-ERROR:                               ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        shsub v11.4h, v12.8h, v13.4h
+// CHECK-ERROR:                          ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        uhsub v31.16b, v29.8b, v28.8b
+// CHECK-ERROR:                          ^
+
+//----------------------------------------------------------------------
+// Vector Integer Rouding Halving Add (Signed)
+// Vector Integer Rouding Halving Add (Unsigned)
+//----------------------------------------------------------------------
+
+        // Mismatched and invalid vector types (2d)
+        srhadd v0.2s, v1.2s, v2.2d
+        urhadd v0.16b, v1.16b, v2.8h
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        srhadd v0.2s, v1.2s, v2.2d
+// CHECK-ERROR:                                ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        urhadd v0.16b, v1.16b, v2.8h
+// CHECK-ERROR:                                  ^
+
+//----------------------------------------------------------------------
+// Vector Integer Saturating Add (Signed)
+// Vector Integer Saturating Add (Unsigned)
+// Vector Integer Saturating Sub (Signed)
+// Vector Integer Saturating Sub (Unsigned)
+//----------------------------------------------------------------------
+
+        // Mismatched vector types
+        sqadd v0.2s, v1.2s, v2.2d
+        uqadd v31.8h, v1.4h, v2.4h
+        sqsub v10.8h, v1.16b, v2.16b
+        uqsub v31.8b, v1.8b, v2.4s
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        sqadd v0.2s, v1.2s, v2.2d
+// CHECK-ERROR:                               ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        uqadd v31.8h, v1.4h, v2.4h
+// CHECK-ERROR:                         ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        sqsub v10.8h, v1.16b, v2.16b
+// CHECK-ERROR:                         ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        uqsub v31.8b, v1.8b, v2.4s
+// CHECK-ERROR:                                ^
+
+//----------------------------------------------------------------------
+// Scalar Integer Saturating Add (Signed)
+// Scalar Integer Saturating Add (Unsigned)
+// Scalar Integer Saturating Sub (Signed)
+// Scalar Integer Saturating Sub (Unsigned)
+//----------------------------------------------------------------------
+
+      // Mismatched registers
+         sqadd d0, s31, d2
+         uqadd s0, s1, d2
+         sqsub b0, b2, s18
+         uqsub h1, h2, d2
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        sqadd d0, s31, d2
+// CHECK-ERROR:                  ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        uqadd s0, s1, d2
+// CHECK-ERROR:                      ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        sqsub b0, b2, s18
+// CHECK-ERROR:                      ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        uqsub h1, h2, d2
+// CHECK-ERROR:                      ^
+
+
+//----------------------------------------------------------------------
+// Vector Shift Left (Signed and Unsigned Integer)
+//----------------------------------------------------------------------
+        // Mismatched vector types
+        sshl v0.4s, v15.2s, v16.2s
+        ushl v1.16b, v25.16b, v6.8h
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        sshl v0.4s, v15.2s, v16.2s
+// CHECK-ERROR:                        ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        ushl v1.16b, v25.16b, v6.8h
+// CHECK-ERROR:                                 ^
+
+//----------------------------------------------------------------------
+// Vector Saturating Shift Left (Signed and Unsigned Integer)
+//----------------------------------------------------------------------
+        // Mismatched vector types
+        sqshl v0.2s, v15.2s, v16.2d
+        uqshl v1.8b, v25.4h, v6.8h
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        sqshl v0.2s, v15.2s, v16.2d
+// CHECK-ERROR:                                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        uqshl v1.8b, v25.4h, v6.8h
+// CHECK-ERROR:                         ^
+
+//----------------------------------------------------------------------
+// Vector Rouding Shift Left (Signed and Unsigned Integer)
+//----------------------------------------------------------------------
+        // Mismatched vector types
+        srshl v0.8h, v15.8h, v16.16b
+        urshl v1.2d, v25.2d, v6.4s
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        srshl v0.8h, v15.8h, v16.16b
+// CHECK-ERROR:                                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        urshl v1.2d, v25.2d, v6.4s
+// CHECK-ERROR:                                ^
+
+//----------------------------------------------------------------------
+// Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
+//----------------------------------------------------------------------
+        // Mismatched vector types
+        sqrshl v0.2s, v15.8h, v16.16b
+        uqrshl v1.4h, v25.4h,  v6.2d
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        sqrshl v0.2s, v15.8h, v16.16b
+// CHECK-ERROR:                          ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        uqrshl v1.4h, v25.4h,  v6.2d
+// CHECK-ERROR:                                  ^
+
+//----------------------------------------------------------------------
+// Scalar Integer Shift Left (Signed, Unsigned)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        sshl d0, d1, s2
+        ushl b2, b0, b1
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        sshl d0, d1, s2
+// CHECK-ERROR:                     ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        ushl b2, b0, b1
+// CHECK-ERROR:             ^
+
+//----------------------------------------------------------------------
+// Scalar Integer Saturating Shift Left (Signed, Unsigned)
+//----------------------------------------------------------------------
+
+        // Mismatched vector types
+        sqshl b0, b1, s0
+        uqshl h0, h1, b0
+        sqshl s0, s1, h0
+        uqshl d0, d1, b0
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        sqshl b0, b1, s0
+// CHECK-ERROR:                      ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        uqshl h0, h1, b0
+// CHECK-ERROR:                      ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        sqshl s0, s1, h0
+// CHECK-ERROR:                      ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        uqshl d0, d1, b0
+// CHECK-ERROR:                      ^
+
+//----------------------------------------------------------------------
+// Scalar Integer Rouding Shift Left (Signed, Unsigned)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        srshl h0, h1, h2
+        urshl s0, s1, s2
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        srshl h0, h1, h2
+// CHECK-ERROR:              ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        urshl s0, s1, s2
+// CHECK-ERROR:              ^
+
+
+//----------------------------------------------------------------------
+// Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
+//----------------------------------------------------------------------
+
+        // Mismatched vector types
+        sqrshl b0, b1, s0
+        uqrshl h0, h1, b0
+        sqrshl s0, s1, h0
+        uqrshl d0, d1, b0
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        sqrshl b0, b1, s0
+// CHECK-ERROR:                       ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        uqrshl h0, h1, b0
+// CHECK-ERROR:                       ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        sqrshl s0, s1, h0
+// CHECK-ERROR:                       ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        uqrshl d0, d1, b0
+// CHECK-ERROR:                       ^
+
+
+//----------------------------------------------------------------------
+// Vector Maximum (Signed, Unsigned)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        smax v0.2d, v1.2d, v2.2d
+        umax v0.4h, v1.4h, v2.2s
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        smax v0.2d, v1.2d, v2.2d
+// CHECK-ERROR:                ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        umax v0.4h, v1.4h, v2.2s
+// CHECK-ERROR:                              ^
+
+//----------------------------------------------------------------------
+// Vector Minimum (Signed, Unsigned)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        smin v0.2d, v1.2d, v2.2d
+        umin v0.2s, v1.2s, v2.8b
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        smin v0.2d, v1.2d, v2.2d
+// CHECK-ERROR:                ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        umin v0.2s, v1.2s, v2.8b
+// CHECK-ERROR:                             ^
+
+
+//----------------------------------------------------------------------
+// Vector Maximum (Floating Point)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        fmax v0.2s, v1.2s, v2.4s
+        fmax v0.8b, v1.8b, v2.8b
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fmax v0.2s, v1.2s, v2.4s
+// CHECK-ERROR:                              ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fmax v0.8b, v1.8b, v2.8b
+// CHECK-ERROR:                ^
+//----------------------------------------------------------------------
+// Vector Minimum (Floating Point)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        fmin v0.4s, v1.4s, v2.2d
+        fmin v0.8h, v1.8h, v2.8h
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fmin v0.4s, v1.4s, v2.2d
+// CHECK-ERROR:                              ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fmin v0.8h, v1.8h, v2.8h
+// CHECK-ERROR:                ^
+
+//----------------------------------------------------------------------
+// Vector maxNum (Floating Point)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        fmaxnm v0.2s, v1.2s, v2.2d
+        fmaxnm v0.4h, v1.8h, v2.4h
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fmaxnm v0.2s, v1.2s, v2.2d
+// CHECK-ERROR:                                ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fmaxnm v0.4h, v1.8h, v2.4h
+// CHECK-ERROR:                  ^
+
+//----------------------------------------------------------------------
+// Vector minNum (Floating Point)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        fminnm v0.4s, v1.2s, v2.4s
+        fminnm v0.16b, v0.16b, v0.16b
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fminnm v0.4s, v1.2s, v2.4s
+// CHECK-ERROR:                         ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fminnm v0.16b, v0.16b, v0.16b
+// CHECK-ERROR:                  ^
+
+
+//----------------------------------------------------------------------
+// Vector Maximum Pairwise (Signed, Unsigned)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        smaxp v0.2d, v1.2d, v2.2d
+        umaxp v0.4h, v1.4h, v2.2s
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        smaxp v0.2d, v1.2d, v2.2d
+// CHECK-ERROR:                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        umaxp v0.4h, v1.4h, v2.2s
+// CHECK-ERROR:                               ^
+
+//----------------------------------------------------------------------
+// Vector Minimum Pairwise (Signed, Unsigned)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        sminp v0.2d, v1.2d, v2.2d
+        uminp v0.2s, v1.2s, v2.8b
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        sminp v0.2d, v1.2d, v2.2d
+// CHECK-ERROR:                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        uminp v0.2s, v1.2s, v2.8b
+// CHECK-ERROR:                               ^
+
+
+//----------------------------------------------------------------------
+// Vector Maximum Pairwise (Floating Point)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        fmaxp v0.2s, v1.2s, v2.4s
+        fmaxp v0.8b, v1.8b, v2.8b
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fmaxp v0.2s, v1.2s, v2.4s
+// CHECK-ERROR:                               ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fmaxp v0.8b, v1.8b, v2.8b
+// CHECK-ERROR:                 ^
+//----------------------------------------------------------------------
+// Vector Minimum Pairwise (Floating Point)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        fminp v0.4s, v1.4s, v2.2d
+        fminp v0.8h, v1.8h, v2.8h
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fminp v0.4s, v1.4s, v2.2d
+// CHECK-ERROR:                               ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fminp v0.8h, v1.8h, v2.8h
+// CHECK-ERROR:                 ^
+
+//----------------------------------------------------------------------
+// Vector maxNum Pairwise (Floating Point)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        fmaxnmp v0.2s, v1.2s, v2.2d
+        fmaxnmp v0.4h, v1.8h, v2.4h
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fmaxnmp v0.2s, v1.2s, v2.2d
+// CHECK-ERROR:                                 ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fmaxnmp v0.4h, v1.8h, v2.4h
+// CHECK-ERROR:                   ^
+
+//----------------------------------------------------------------------
+// Vector minNum Pairwise (Floating Point)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        fminnmp v0.4s, v1.2s, v2.4s
+        fminnmp v0.16b, v0.16b, v0.16b
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fminnmp v0.4s, v1.2s, v2.4s
+// CHECK-ERROR:                          ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:        fminnmp v0.16b, v0.16b, v0.16b
+// CHECK-ERROR:                   ^
+
+
+//----------------------------------------------------------------------
+// Vector Add Pairwise (Integer)
+//----------------------------------------------------------------------
+
+        // Mismatched vector types
+        addp v0.16b, v1.8b, v2.8b
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         addp v0.16b, v1.8b, v2.8b
+// CHECK-ERROR:                         ^
+
+//----------------------------------------------------------------------
+// Vector Add Pairwise (Floating Point)
+//----------------------------------------------------------------------
+        // Mismatched and invalid vector types
+        faddp v0.16b, v1.8b, v2.8b
+        faddp v0.2d, v1.2d, v2.8h
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         faddp v0.16b, v1.8b, v2.8b
+// CHECK-ERROR:                  ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         faddp v0.2d, v1.2d, v2.8h
+// CHECK-ERROR:                                ^
+
+
+//----------------------------------------------------------------------
+// Vector Saturating Doubling Multiply High
+//----------------------------------------------------------------------
+         // Mismatched and invalid vector types
+         sqdmulh v2.4h, v25.8h, v3.4h
+         sqdmulh v12.2d, v5.2d, v13.2d
+         sqdmulh v3.8b, v1.8b, v30.8b
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         sqdmulh v2.4h, v25.8h, v3.4h
+// CHECK-ERROR:                            ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         sqdmulh v12.2d, v5.2d, v13.2d
+// CHECK-ERROR:                     ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         sqdmulh v3.8b, v1.8b, v30.8b
+// CHECK-ERROR:                    ^
+
+//----------------------------------------------------------------------
+// Vector Saturating Rouding Doubling Multiply High
+//----------------------------------------------------------------------
+         // Mismatched and invalid vector types
+         sqrdmulh v2.2s, v25.4s, v3.4s
+         sqrdmulh v12.16b, v5.16b, v13.16b
+         sqrdmulh v3.4h, v1.4h, v30.2d
+
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         sqrdmulh v2.2s, v25.4s, v3.4s
+// CHECK-ERROR:                             ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         sqrdmulh v12.16b, v5.16b, v13.16b
+// CHECK-ERROR:                       ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         sqrdmulh v3.4h, v1.4h, v30.2d
+// CHECK-ERROR:                                    ^
+
+//----------------------------------------------------------------------
+// Vector Multiply Extended
+//----------------------------------------------------------------------
+         // Mismatched and invalid vector types
+      fmulx v21.2s, v5.2s, v13.2d
+      fmulx v1.4h, v25.4h, v3.4h
+
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         fmulx v21.2s, v5.2s, v13.2d
+// CHECK-ERROR:                                  ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:         fmulx v1.4h, v25.4h, v3.4h
+// CHECK-ERROR:                  ^
diff --git a/test/MC/AArch64/neon-facge-facgt.s b/test/MC/AArch64/neon-facge-facgt.s
new file mode 100644
index 0000000..212eda2
--- /dev/null
+++ b/test/MC/AArch64/neon-facge-facgt.s
@@ -0,0 +1,41 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+//----------------------------------------------------------------------
+// Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
+// FACLE is alias for FACGE with operands reversed
+//----------------------------------------------------------------------
+         facge v0.2s, v31.2s, v16.2s
+         facge v4.4s, v7.4s, v15.4s
+         facge v29.2d, v2.2d, v5.2d
+         facle v0.2s, v16.2s, v31.2s
+         facle v4.4s, v15.4s, v7.4s
+         facle v29.2d, v5.2d, v2.2d
+
+// CHECK: facge v0.2s, v31.2s, v16.2s // encoding: [0xe0,0xef,0x30,0x2e]
+// CHECK: facge v4.4s, v7.4s, v15.4s  // encoding: [0xe4,0xec,0x2f,0x6e]
+// CHECK: facge v29.2d, v2.2d, v5.2d  // encoding: [0x5d,0xec,0x65,0x6e]
+// CHECK: facge v0.2s, v31.2s, v16.2s // encoding: [0xe0,0xef,0x30,0x2e]
+// CHECK: facge v4.4s, v7.4s, v15.4s  // encoding: [0xe4,0xec,0x2f,0x6e]
+// CHECK: facge v29.2d, v2.2d, v5.2d  // encoding: [0x5d,0xec,0x65,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Absolute Compare Mask Less Than (Floating Point)
+// FACLT is alias for FACGT with operands reversed
+//----------------------------------------------------------------------
+         facgt v31.4s, v29.4s, v28.4s
+         facgt v3.2s, v8.2s, v12.2s
+         facgt v17.2d, v15.2d, v13.2d
+         faclt v31.4s, v28.4s, v29.4s
+         faclt v3.2s,  v12.2s, v8.2s
+         faclt v17.2d, v13.2d, v15.2d
+
+// CHECK: facgt v31.4s, v29.4s, v28.4s  // encoding: [0xbf,0xef,0xbc,0x6e]
+// CHECK: facgt v3.2s, v8.2s, v12.2s    // encoding: [0x03,0xed,0xac,0x2e]
+// CHECK: facgt v17.2d, v15.2d, v13.2d  // encoding: [0xf1,0xed,0xed,0x6e]
+// CHECK: facgt v31.4s, v29.4s, v28.4s  // encoding: [0xbf,0xef,0xbc,0x6e]
+// CHECK: facgt v3.2s, v8.2s, v12.2s    // encoding: [0x03,0xed,0xac,0x2e]
+// CHECK: facgt v17.2d, v15.2d, v13.2d  // encoding: [0xf1,0xed,0xed,0x6e]
+
+
diff --git a/test/MC/AArch64/neon-frsqrt-frecp.s b/test/MC/AArch64/neon-frsqrt-frecp.s
new file mode 100644
index 0000000..79fe5da
--- /dev/null
+++ b/test/MC/AArch64/neon-frsqrt-frecp.s
@@ -0,0 +1,27 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+//----------------------------------------------------------------------
+// Vector Reciprocal Square Root Step (Floating Point)
+//----------------------------------------------------------------------
+         frsqrts v0.2s, v31.2s, v16.2s
+         frsqrts v4.4s, v7.4s, v15.4s
+         frsqrts v29.2d, v2.2d, v5.2d
+
+// CHECK: frsqrts v0.2s, v31.2s, v16.2s // encoding: [0xe0,0xff,0xb0,0x0e]
+// CHECK: frsqrts v4.4s, v7.4s, v15.4s  // encoding: [0xe4,0xfc,0xaf,0x4e]
+// CHECK: frsqrts v29.2d, v2.2d, v5.2d  // encoding: [0x5d,0xfc,0xe5,0x4e]
+
+//----------------------------------------------------------------------
+// Vector Reciprocal Step (Floating Point)
+//----------------------------------------------------------------------
+         frecps v31.4s, v29.4s, v28.4s
+         frecps v3.2s, v8.2s, v12.2s
+         frecps v17.2d, v15.2d, v13.2d
+
+// CHECK: frecps v31.4s, v29.4s, v28.4s  // encoding: [0xbf,0xff,0x3c,0x4e]
+// CHECK: frecps v3.2s, v8.2s, v12.2s    // encoding: [0x03,0xfd,0x2c,0x0e]
+// CHECK: frecps v17.2d, v15.2d, v13.2d  // encoding: [0xf1,0xfd,0x6d,0x4e]
+
+
diff --git a/test/MC/AArch64/neon-halving-add-sub.s b/test/MC/AArch64/neon-halving-add-sub.s
new file mode 100644
index 0000000..555f1b8
--- /dev/null
+++ b/test/MC/AArch64/neon-halving-add-sub.s
@@ -0,0 +1,74 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+
+//------------------------------------------------------------------------------
+// Vector Integer Halving Add (Signed)
+//------------------------------------------------------------------------------
+         shadd v0.8b, v1.8b, v2.8b
+         shadd v0.16b, v1.16b, v2.16b
+         shadd v0.4h, v1.4h, v2.4h
+         shadd v0.8h, v1.8h, v2.8h
+         shadd v0.2s, v1.2s, v2.2s
+         shadd v0.4s, v1.4s, v2.4s
+
+// CHECK: shadd v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x04,0x22,0x0e]
+// CHECK: shadd v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x04,0x22,0x4e]
+// CHECK: shadd v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x04,0x62,0x0e]
+// CHECK: shadd v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x04,0x62,0x4e]
+// CHECK: shadd v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x04,0xa2,0x0e]
+// CHECK: shadd v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x04,0xa2,0x4e]
+
+
+//------------------------------------------------------------------------------
+// Vector Integer Halving Add (Unsigned)
+//------------------------------------------------------------------------------
+         uhadd v0.8b, v1.8b, v2.8b
+         uhadd v0.16b, v1.16b, v2.16b
+         uhadd v0.4h, v1.4h, v2.4h
+         uhadd v0.8h, v1.8h, v2.8h
+         uhadd v0.2s, v1.2s, v2.2s
+         uhadd v0.4s, v1.4s, v2.4s
+
+// CHECK: uhadd v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x04,0x22,0x2e]
+// CHECK: uhadd v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x04,0x22,0x6e]
+// CHECK: uhadd v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x04,0x62,0x2e]
+// CHECK: uhadd v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x04,0x62,0x6e]
+// CHECK: uhadd v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x04,0xa2,0x2e]
+// CHECK: uhadd v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x04,0xa2,0x6e]
+
+//------------------------------------------------------------------------------
+// Vector Integer Halving Sub (Signed)
+//------------------------------------------------------------------------------
+         shsub v0.8b, v1.8b, v2.8b
+         shsub v0.16b, v1.16b, v2.16b
+         shsub v0.4h, v1.4h, v2.4h
+         shsub v0.8h, v1.8h, v2.8h
+         shsub v0.2s, v1.2s, v2.2s
+         shsub v0.4s, v1.4s, v2.4s
+
+// CHECK: shsub v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x24,0x22,0x0e]
+// CHECK: shsub v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x24,0x22,0x4e]
+// CHECK: shsub v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x24,0x62,0x0e]
+// CHECK: shsub v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x24,0x62,0x4e]
+// CHECK: shsub v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x24,0xa2,0x0e]
+// CHECK: shsub v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x24,0xa2,0x4e]
+
+//------------------------------------------------------------------------------
+// Vector Integer Halving Sub (Unsigned)
+//------------------------------------------------------------------------------
+         uhsub v0.8b, v1.8b, v2.8b
+         uhsub v0.16b, v1.16b, v2.16b
+         uhsub v0.4h, v1.4h, v2.4h
+         uhsub v0.8h, v1.8h, v2.8h
+         uhsub v0.2s, v1.2s, v2.2s
+         uhsub v0.4s, v1.4s, v2.4s
+
+// CHECK: uhsub v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x24,0x22,0x2e]
+// CHECK: uhsub v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x24,0x22,0x6e]
+// CHECK: uhsub v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x24,0x62,0x2e]
+// CHECK: uhsub v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x24,0x62,0x6e]
+// CHECK: uhsub v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x24,0xa2,0x2e]
+// CHECK: uhsub v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x24,0xa2,0x6e]
+
diff --git a/test/MC/AArch64/neon-max-min-pairwise.s b/test/MC/AArch64/neon-max-min-pairwise.s
new file mode 100644
index 0000000..8d2dadb
--- /dev/null
+++ b/test/MC/AArch64/neon-max-min-pairwise.s
@@ -0,0 +1,110 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+//----------------------------------------------------------------------
+// Vector Maximum Pairwise (Signed and Unsigned Integer)
+//----------------------------------------------------------------------
+         smaxp v0.8b, v1.8b, v2.8b
+         smaxp v0.16b, v1.16b, v2.16b
+         smaxp v0.4h, v1.4h, v2.4h
+         smaxp v0.8h, v1.8h, v2.8h
+         smaxp v0.2s, v1.2s, v2.2s
+         smaxp v0.4s, v1.4s, v2.4s
+
+// CHECK: smaxp v0.8b, v1.8b, v2.8b        // encoding: [0x20,0xa4,0x22,0x0e]
+// CHECK: smaxp v0.16b, v1.16b, v2.16b     // encoding: [0x20,0xa4,0x22,0x4e]
+// CHECK: smaxp v0.4h, v1.4h, v2.4h        // encoding: [0x20,0xa4,0x62,0x0e]
+// CHECK: smaxp v0.8h, v1.8h, v2.8h        // encoding: [0x20,0xa4,0x62,0x4e]
+// CHECK: smaxp v0.2s, v1.2s, v2.2s        // encoding: [0x20,0xa4,0xa2,0x0e]
+// CHECK: smaxp v0.4s, v1.4s, v2.4s        // encoding: [0x20,0xa4,0xa2,0x4e]
+
+         umaxp v0.8b, v1.8b, v2.8b
+         umaxp v0.16b, v1.16b, v2.16b
+         umaxp v0.4h, v1.4h, v2.4h
+         umaxp v0.8h, v1.8h, v2.8h
+         umaxp v0.2s, v1.2s, v2.2s
+         umaxp v0.4s, v1.4s, v2.4s
+
+// CHECK: umaxp v0.8b, v1.8b, v2.8b         // encoding: [0x20,0xa4,0x22,0x2e]
+// CHECK: umaxp v0.16b, v1.16b, v2.16b      // encoding: [0x20,0xa4,0x22,0x6e]
+// CHECK: umaxp v0.4h, v1.4h, v2.4h         // encoding: [0x20,0xa4,0x62,0x2e]
+// CHECK: umaxp v0.8h, v1.8h, v2.8h         // encoding: [0x20,0xa4,0x62,0x6e]
+// CHECK: umaxp v0.2s, v1.2s, v2.2s         // encoding: [0x20,0xa4,0xa2,0x2e]
+// CHECK: umaxp v0.4s, v1.4s, v2.4s         // encoding: [0x20,0xa4,0xa2,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Minimum Pairwise (Signed and Unsigned Integer)
+//----------------------------------------------------------------------
+         sminp v0.8b, v1.8b, v2.8b
+         sminp v0.16b, v1.16b, v2.16b
+         sminp v0.4h, v1.4h, v2.4h
+         sminp v0.8h, v1.8h, v2.8h
+         sminp v0.2s, v1.2s, v2.2s
+         sminp v0.4s, v1.4s, v2.4s
+
+// CHECK: sminp v0.8b, v1.8b, v2.8b        // encoding: [0x20,0xac,0x22,0x0e]
+// CHECK: sminp v0.16b, v1.16b, v2.16b     // encoding: [0x20,0xac,0x22,0x4e]
+// CHECK: sminp v0.4h, v1.4h, v2.4h        // encoding: [0x20,0xac,0x62,0x0e]
+// CHECK: sminp v0.8h, v1.8h, v2.8h        // encoding: [0x20,0xac,0x62,0x4e]
+// CHECK: sminp v0.2s, v1.2s, v2.2s        // encoding: [0x20,0xac,0xa2,0x0e]
+// CHECK: sminp v0.4s, v1.4s, v2.4s        // encoding: [0x20,0xac,0xa2,0x4e]
+
+         uminp v0.8b, v1.8b, v2.8b
+         uminp v0.16b, v1.16b, v2.16b
+         uminp v0.4h, v1.4h, v2.4h
+         uminp v0.8h, v1.8h, v2.8h
+         uminp v0.2s, v1.2s, v2.2s
+         uminp v0.4s, v1.4s, v2.4s
+
+// CHECK: uminp v0.8b, v1.8b, v2.8b         // encoding: [0x20,0xac,0x22,0x2e]
+// CHECK: uminp v0.16b, v1.16b, v2.16b      // encoding: [0x20,0xac,0x22,0x6e]
+// CHECK: uminp v0.4h, v1.4h, v2.4h         // encoding: [0x20,0xac,0x62,0x2e]
+// CHECK: uminp v0.8h, v1.8h, v2.8h         // encoding: [0x20,0xac,0x62,0x6e]
+// CHECK: uminp v0.2s, v1.2s, v2.2s         // encoding: [0x20,0xac,0xa2,0x2e]
+// CHECK: uminp v0.4s, v1.4s, v2.4s         // encoding: [0x20,0xac,0xa2,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Maximum Pairwise (Floating Point)
+//----------------------------------------------------------------------
+         fmaxp v0.2s, v1.2s, v2.2s
+         fmaxp v31.4s, v15.4s, v16.4s
+         fmaxp v7.2d, v8.2d, v25.2d
+
+// CHECK: fmaxp v0.2s, v1.2s, v2.2s    // encoding: [0x20,0xf4,0x22,0x2e]
+// CHECK: fmaxp v31.4s, v15.4s, v16.4s // encoding: [0xff,0xf5,0x30,0x6e]
+// CHECK: fmaxp v7.2d, v8.2d, v25.2d   // encoding: [0x07,0xf5,0x79,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Minimum Pairwise (Floating Point)
+//----------------------------------------------------------------------
+         fminp v10.2s, v15.2s, v22.2s
+         fminp v3.4s, v5.4s, v6.4s
+         fminp v17.2d, v13.2d, v2.2d
+
+// CHECK: fminp v10.2s, v15.2s, v22.2s  // encoding: [0xea,0xf5,0xb6,0x2e]
+// CHECK: fminp v3.4s, v5.4s, v6.4s     // encoding: [0xa3,0xf4,0xa6,0x6e]
+// CHECK: fminp v17.2d, v13.2d, v2.2d   // encoding: [0xb1,0xf5,0xe2,0x6e]
+
+//----------------------------------------------------------------------
+// Vector maxNum Pairwise (Floating Point)
+//----------------------------------------------------------------------
+         fmaxnmp v0.2s, v1.2s, v2.2s
+         fmaxnmp v31.4s, v15.4s, v16.4s
+         fmaxnmp v7.2d, v8.2d, v25.2d
+
+// CHECK: fmaxnmp v0.2s, v1.2s, v2.2s    // encoding: [0x20,0xc4,0x22,0x2e]
+// CHECK: fmaxnmp v31.4s, v15.4s, v16.4s // encoding: [0xff,0xc5,0x30,0x6e]
+// CHECK: fmaxnmp v7.2d, v8.2d, v25.2d   // encoding: [0x07,0xc5,0x79,0x6e]
+
+//----------------------------------------------------------------------
+// Vector minNum Pairwise (Floating Point)
+//----------------------------------------------------------------------
+         fminnmp v10.2s, v15.2s, v22.2s
+         fminnmp v3.4s, v5.4s, v6.4s
+         fminnmp v17.2d, v13.2d, v2.2d
+
+// CHECK: fminnmp v10.2s, v15.2s, v22.2s  // encoding: [0xea,0xc5,0xb6,0x2e]
+// CHECK: fminnmp v3.4s, v5.4s, v6.4s     // encoding: [0xa3,0xc4,0xa6,0x6e]
+// CHECK: fminnmp v17.2d, v13.2d, v2.2d   // encoding: [0xb1,0xc5,0xe2,0x6e]
+
diff --git a/test/MC/AArch64/neon-max-min.s b/test/MC/AArch64/neon-max-min.s
new file mode 100644
index 0000000..6d1efde
--- /dev/null
+++ b/test/MC/AArch64/neon-max-min.s
@@ -0,0 +1,110 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+//----------------------------------------------------------------------
+// Vector Maximum (Signed and Unsigned Integer)
+//----------------------------------------------------------------------
+         smax v0.8b, v1.8b, v2.8b
+         smax v0.16b, v1.16b, v2.16b
+         smax v0.4h, v1.4h, v2.4h
+         smax v0.8h, v1.8h, v2.8h
+         smax v0.2s, v1.2s, v2.2s
+         smax v0.4s, v1.4s, v2.4s
+
+// CHECK: smax v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x64,0x22,0x0e]
+// CHECK: smax v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x64,0x22,0x4e]
+// CHECK: smax v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x64,0x62,0x0e]
+// CHECK: smax v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x64,0x62,0x4e]
+// CHECK: smax v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x64,0xa2,0x0e]
+// CHECK: smax v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x64,0xa2,0x4e]
+
+         umax v0.8b, v1.8b, v2.8b
+         umax v0.16b, v1.16b, v2.16b
+         umax v0.4h, v1.4h, v2.4h
+         umax v0.8h, v1.8h, v2.8h
+         umax v0.2s, v1.2s, v2.2s
+         umax v0.4s, v1.4s, v2.4s
+
+// CHECK: umax v0.8b, v1.8b, v2.8b         // encoding: [0x20,0x64,0x22,0x2e]
+// CHECK: umax v0.16b, v1.16b, v2.16b      // encoding: [0x20,0x64,0x22,0x6e]
+// CHECK: umax v0.4h, v1.4h, v2.4h         // encoding: [0x20,0x64,0x62,0x2e]
+// CHECK: umax v0.8h, v1.8h, v2.8h         // encoding: [0x20,0x64,0x62,0x6e]
+// CHECK: umax v0.2s, v1.2s, v2.2s         // encoding: [0x20,0x64,0xa2,0x2e]
+// CHECK: umax v0.4s, v1.4s, v2.4s         // encoding: [0x20,0x64,0xa2,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Minimum (Signed and Unsigned Integer)
+//----------------------------------------------------------------------
+         smin v0.8b, v1.8b, v2.8b
+         smin v0.16b, v1.16b, v2.16b
+         smin v0.4h, v1.4h, v2.4h
+         smin v0.8h, v1.8h, v2.8h
+         smin v0.2s, v1.2s, v2.2s
+         smin v0.4s, v1.4s, v2.4s
+
+// CHECK: smin v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x6c,0x22,0x0e]
+// CHECK: smin v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x6c,0x22,0x4e]
+// CHECK: smin v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x6c,0x62,0x0e]
+// CHECK: smin v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x6c,0x62,0x4e]
+// CHECK: smin v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x6c,0xa2,0x0e]
+// CHECK: smin v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x6c,0xa2,0x4e]
+
+         umin v0.8b, v1.8b, v2.8b
+         umin v0.16b, v1.16b, v2.16b
+         umin v0.4h, v1.4h, v2.4h
+         umin v0.8h, v1.8h, v2.8h
+         umin v0.2s, v1.2s, v2.2s
+         umin v0.4s, v1.4s, v2.4s
+
+// CHECK: umin v0.8b, v1.8b, v2.8b         // encoding: [0x20,0x6c,0x22,0x2e]
+// CHECK: umin v0.16b, v1.16b, v2.16b      // encoding: [0x20,0x6c,0x22,0x6e]
+// CHECK: umin v0.4h, v1.4h, v2.4h         // encoding: [0x20,0x6c,0x62,0x2e]
+// CHECK: umin v0.8h, v1.8h, v2.8h         // encoding: [0x20,0x6c,0x62,0x6e]
+// CHECK: umin v0.2s, v1.2s, v2.2s         // encoding: [0x20,0x6c,0xa2,0x2e]
+// CHECK: umin v0.4s, v1.4s, v2.4s         // encoding: [0x20,0x6c,0xa2,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Maximum (Floating Point)
+//----------------------------------------------------------------------
+         fmax v0.2s, v1.2s, v2.2s
+         fmax v31.4s, v15.4s, v16.4s
+         fmax v7.2d, v8.2d, v25.2d
+
+// CHECK: fmax v0.2s, v1.2s, v2.2s    // encoding: [0x20,0xf4,0x22,0x0e]
+// CHECK: fmax v31.4s, v15.4s, v16.4s // encoding: [0xff,0xf5,0x30,0x4e]
+// CHECK: fmax v7.2d, v8.2d, v25.2d   // encoding: [0x07,0xf5,0x79,0x4e]
+
+//----------------------------------------------------------------------
+// Vector Minimum (Floating Point)
+//----------------------------------------------------------------------
+         fmin v10.2s, v15.2s, v22.2s
+         fmin v3.4s, v5.4s, v6.4s
+         fmin v17.2d, v13.2d, v2.2d
+
+// CHECK: fmin v10.2s, v15.2s, v22.2s  // encoding: [0xea,0xf5,0xb6,0x0e]
+// CHECK: fmin v3.4s, v5.4s, v6.4s     // encoding: [0xa3,0xf4,0xa6,0x4e]
+// CHECK: fmin v17.2d, v13.2d, v2.2d   // encoding: [0xb1,0xf5,0xe2,0x4e]
+
+//----------------------------------------------------------------------
+// Vector maxNum (Floating Point)
+//----------------------------------------------------------------------
+         fmaxnm v0.2s, v1.2s, v2.2s
+         fmaxnm v31.4s, v15.4s, v16.4s
+         fmaxnm v7.2d, v8.2d, v25.2d
+
+// CHECK: fmaxnm v0.2s, v1.2s, v2.2s    // encoding: [0x20,0xc4,0x22,0x0e]
+// CHECK: fmaxnm v31.4s, v15.4s, v16.4s // encoding: [0xff,0xc5,0x30,0x4e]
+// CHECK: fmaxnm v7.2d, v8.2d, v25.2d   // encoding: [0x07,0xc5,0x79,0x4e]
+
+//----------------------------------------------------------------------
+// Vector minNum (Floating Point)
+//----------------------------------------------------------------------
+         fminnm v10.2s, v15.2s, v22.2s
+         fminnm v3.4s, v5.4s, v6.4s
+         fminnm v17.2d, v13.2d, v2.2d
+
+// CHECK: fminnm v10.2s, v15.2s, v22.2s  // encoding: [0xea,0xc5,0xb6,0x0e]
+// CHECK: fminnm v3.4s, v5.4s, v6.4s     // encoding: [0xa3,0xc4,0xa6,0x4e]
+// CHECK: fminnm v17.2d, v13.2d, v2.2d   // encoding: [0xb1,0xc5,0xe2,0x4e]
+
diff --git a/test/MC/AArch64/neon-mla-mls-instructions.s b/test/MC/AArch64/neon-mla-mls-instructions.s
new file mode 100644
index 0000000..3072e6f
--- /dev/null
+++ b/test/MC/AArch64/neon-mla-mls-instructions.s
@@ -0,0 +1,61 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+//----------------------------------------------------------------------
+// Vector Integer Multiply-accumulate
+//----------------------------------------------------------------------
+         mla v0.8b, v1.8b, v2.8b
+         mla v0.16b, v1.16b, v2.16b
+         mla v0.4h, v1.4h, v2.4h
+         mla v0.8h, v1.8h, v2.8h
+         mla v0.2s, v1.2s, v2.2s
+         mla v0.4s, v1.4s, v2.4s
+
+// CHECK: mla v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x94,0x22,0x0e]
+// CHECK: mla v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x94,0x22,0x4e]
+// CHECK: mla v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x94,0x62,0x0e]
+// CHECK: mla v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x94,0x62,0x4e]
+// CHECK: mla v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x94,0xa2,0x0e]
+// CHECK: mla v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x94,0xa2,0x4e]
+
+
+//----------------------------------------------------------------------
+// Vector Integer Multiply-subtract
+//----------------------------------------------------------------------
+         mls v0.8b, v1.8b, v2.8b
+         mls v0.16b, v1.16b, v2.16b
+         mls v0.4h, v1.4h, v2.4h
+         mls v0.8h, v1.8h, v2.8h
+         mls v0.2s, v1.2s, v2.2s
+         mls v0.4s, v1.4s, v2.4s
+
+// CHECK: mls v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x94,0x22,0x2e]
+// CHECK: mls v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x94,0x22,0x6e]
+// CHECK: mls v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x94,0x62,0x2e]
+// CHECK: mls v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x94,0x62,0x6e]
+// CHECK: mls v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x94,0xa2,0x2e]
+// CHECK: mls v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x94,0xa2,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Floating-Point Multiply-accumulate
+//----------------------------------------------------------------------
+         fmla v0.2s, v1.2s, v2.2s
+         fmla v0.4s, v1.4s, v2.4s
+         fmla v0.2d, v1.2d, v2.2d
+
+// CHECK: fmla v0.2s, v1.2s, v2.2s       // encoding: [0x20,0xcc,0x22,0x0e]
+// CHECK: fmla v0.4s, v1.4s, v2.4s       // encoding: [0x20,0xcc,0x22,0x4e]
+// CHECK: fmla v0.2d, v1.2d, v2.2d       // encoding: [0x20,0xcc,0x62,0x4e]
+
+//----------------------------------------------------------------------
+// Vector Floating-Point Multiply-subtract
+//----------------------------------------------------------------------
+         fmls v0.2s, v1.2s, v2.2s
+         fmls v0.4s, v1.4s, v2.4s
+         fmls v0.2d, v1.2d, v2.2d
+
+// CHECK: fmls v0.2s, v1.2s, v2.2s       // encoding: [0x20,0xcc,0xa2,0x0e]
+// CHECK: fmls v0.4s, v1.4s, v2.4s       // encoding: [0x20,0xcc,0xa2,0x4e]
+// CHECK: fmls v0.2d, v1.2d, v2.2d       // encoding: [0x20,0xcc,0xe2,0x4e]
+
diff --git a/test/MC/AArch64/neon-mov.s b/test/MC/AArch64/neon-mov.s
new file mode 100644
index 0000000..8331372
--- /dev/null
+++ b/test/MC/AArch64/neon-mov.s
@@ -0,0 +1,207 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+
+//----------------------------------------------------------------------
+// Vector Move Immediate Shifted
+//----------------------------------------------------------------------
+         movi v0.2s, #1
+         movi v1.2s, #0
+         movi v15.2s, #1, lsl #8
+         movi v16.2s, #1, lsl #16
+         movi v31.2s, #1, lsl #24
+         movi v0.4s, #1
+         movi v0.4s, #1, lsl #8
+         movi v0.4s, #1, lsl #16
+         movi v0.4s, #1, lsl #24
+         movi v0.4h, #1
+         movi v0.4h, #1, lsl #8
+         movi v0.8h, #1
+         movi v0.8h, #1, lsl #8
+
+// CHECK:  movi v0.2s, #0x1           // encoding: [0x20,0x04,0x00,0x0f]
+// CHECK:  movi v1.2s, #0x0           // encoding: [0x01,0x04,0x00,0x0f]
+// CHECK:  movi v15.2s, #0x1, lsl #8  // encoding: [0x2f,0x24,0x00,0x0f]
+// CHECK:  movi v16.2s, #0x1, lsl #16 // encoding: [0x30,0x44,0x00,0x0f]
+// CHECK:  movi v31.2s, #0x1, lsl #24 // encoding: [0x3f,0x64,0x00,0x0f]
+// CHECK:  movi v0.4s, #0x1           // encoding: [0x20,0x04,0x00,0x4f]
+// CHECK:  movi v0.4s, #0x1, lsl #8   // encoding: [0x20,0x24,0x00,0x4f]
+// CHECK:  movi v0.4s, #0x1, lsl #16  // encoding: [0x20,0x44,0x00,0x4f]
+// CHECK:  movi v0.4s, #0x1, lsl #24  // encoding: [0x20,0x64,0x00,0x4f]
+// CHECK:  movi v0.4h, #0x1           // encoding: [0x20,0x84,0x00,0x0f]
+// CHECK:  movi v0.4h, #0x1, lsl #8   // encoding: [0x20,0xa4,0x00,0x0f]
+// CHECK:  movi v0.8h, #0x1           // encoding: [0x20,0x84,0x00,0x4f]
+// CHECK:  movi v0.8h, #0x1, lsl #8   // encoding: [0x20,0xa4,0x00,0x4f]
+
+//----------------------------------------------------------------------
+// Vector Move Inverted Immediate Shifted
+//----------------------------------------------------------------------
+         mvni v0.2s, #1
+         mvni v1.2s, #0
+         mvni v0.2s, #1, lsl #8
+         mvni v0.2s, #1, lsl #16
+         mvni v0.2s, #1, lsl #24
+         mvni v0.4s, #1
+         mvni v15.4s, #1, lsl #8
+         mvni v16.4s, #1, lsl #16
+         mvni v31.4s, #1, lsl #24
+         mvni v0.4h, #1
+         mvni v0.4h, #1, lsl #8
+         mvni v0.8h, #1
+         mvni v0.8h, #1, lsl #8
+
+// CHECK:  mvni v0.2s, #0x1           // encoding: [0x20,0x04,0x00,0x2f]
+// CHECK:  mvni v1.2s, #0x0           // encoding: [0x01,0x04,0x00,0x2f]
+// CHECK:  mvni v0.2s, #0x1, lsl #8   // encoding: [0x20,0x24,0x00,0x2f]
+// CHECK:  mvni v0.2s, #0x1, lsl #16  // encoding: [0x20,0x44,0x00,0x2f]
+// CHECK:  mvni v0.2s, #0x1, lsl #24  // encoding: [0x20,0x64,0x00,0x2f]
+// CHECK:  mvni v0.4s, #0x1           // encoding: [0x20,0x04,0x00,0x6f]
+// CHECK:  mvni v15.4s, #0x1, lsl #8  // encoding: [0x2f,0x24,0x00,0x6f]
+// CHECK:  mvni v16.4s, #0x1, lsl #16 // encoding: [0x30,0x44,0x00,0x6f]
+// CHECK:  mvni v31.4s, #0x1, lsl #24 // encoding: [0x3f,0x64,0x00,0x6f]
+// CHECK:  mvni v0.4h, #0x1           // encoding: [0x20,0x84,0x00,0x2f]
+// CHECK:  mvni v0.4h, #0x1, lsl #8   // encoding: [0x20,0xa4,0x00,0x2f]
+// CHECK:  mvni v0.8h, #0x1           // encoding: [0x20,0x84,0x00,0x6f]
+// CHECK:  mvni v0.8h, #0x1, lsl #8   // encoding: [0x20,0xa4,0x00,0x6f]
+
+//----------------------------------------------------------------------
+// Vector Bitwise Bit Clear (AND NOT) - immediate
+//----------------------------------------------------------------------
+         bic v0.2s, #1
+         bic v1.2s, #0
+         bic v0.2s, #1, lsl #8
+         bic v0.2s, #1, lsl #16
+         bic v0.2s, #1, lsl #24
+         bic v0.4s, #1
+         bic v0.4s, #1, lsl #8
+         bic v0.4s, #1, lsl #16
+         bic v0.4s, #1, lsl #24
+         bic v15.4h, #1
+         bic v16.4h, #1, lsl #8
+         bic v0.8h, #1
+         bic v31.8h, #1, lsl #8
+
+// CHECK:  bic v0.2s, #0x1           // encoding: [0x20,0x14,0x00,0x2f]
+// CHECK:  bic v1.2s, #0x0           // encoding: [0x01,0x14,0x00,0x2f]
+// CHECK:  bic v0.2s, #0x1, lsl #8   // encoding: [0x20,0x34,0x00,0x2f]
+// CHECK:  bic v0.2s, #0x1, lsl #16  // encoding: [0x20,0x54,0x00,0x2f]
+// CHECK:  bic v0.2s, #0x1, lsl #24  // encoding: [0x20,0x74,0x00,0x2f]
+// CHECK:  bic v0.4s, #0x1           // encoding: [0x20,0x14,0x00,0x6f]
+// CHECK:  bic v0.4s, #0x1, lsl #8   // encoding: [0x20,0x34,0x00,0x6f]
+// CHECK:  bic v0.4s, #0x1, lsl #16  // encoding: [0x20,0x54,0x00,0x6f]
+// CHECK:  bic v0.4s, #0x1, lsl #24  // encoding: [0x20,0x74,0x00,0x6f]
+// CHECK:  bic v15.4h, #0x1          // encoding: [0x2f,0x94,0x00,0x2f]
+// CHECK:  bic v16.4h, #0x1, lsl #8  // encoding: [0x30,0xb4,0x00,0x2f]
+// CHECK:  bic v0.8h, #0x1           // encoding: [0x20,0x94,0x00,0x6f]
+// CHECK:  bic v31.8h, #0x1, lsl #8  // encoding: [0x3f,0xb4,0x00,0x6f]
+
+//----------------------------------------------------------------------
+// Vector Bitwise OR - immedidate
+//----------------------------------------------------------------------
+         orr v0.2s, #1
+         orr v1.2s, #0
+         orr v0.2s, #1, lsl #8
+         orr v0.2s, #1, lsl #16
+         orr v0.2s, #1, lsl #24
+         orr v0.4s, #1
+         orr v0.4s, #1, lsl #8
+         orr v0.4s, #1, lsl #16
+         orr v0.4s, #1, lsl #24
+         orr v31.4h, #1
+         orr v15.4h, #1, lsl #8
+         orr v0.8h, #1
+         orr v16.8h, #1, lsl #8
+
+// CHECK:  orr v0.2s, #0x1           // encoding: [0x20,0x14,0x00,0x0f]
+// CHECK:  orr v1.2s, #0x0           // encoding: [0x01,0x14,0x00,0x0f]
+// CHECK:  orr v0.2s, #0x1, lsl #8   // encoding: [0x20,0x34,0x00,0x0f]
+// CHECK:  orr v0.2s, #0x1, lsl #16  // encoding: [0x20,0x54,0x00,0x0f]
+// CHECK:  orr v0.2s, #0x1, lsl #24  // encoding: [0x20,0x74,0x00,0x0f]
+// CHECK:  orr v0.4s, #0x1           // encoding: [0x20,0x14,0x00,0x4f]
+// CHECK:  orr v0.4s, #0x1, lsl #8   // encoding: [0x20,0x34,0x00,0x4f]
+// CHECK:  orr v0.4s, #0x1, lsl #16  // encoding: [0x20,0x54,0x00,0x4f]
+// CHECK:  orr v0.4s, #0x1, lsl #24  // encoding: [0x20,0x74,0x00,0x4f]
+// CHECK:  orr v31.4h, #0x1          // encoding: [0x3f,0x94,0x00,0x0f]
+// CHECK:  orr v15.4h, #0x1, lsl #8  // encoding: [0x2f,0xb4,0x00,0x0f]
+// CHECK:  orr v0.8h, #0x1           // encoding: [0x20,0x94,0x00,0x4f]
+// CHECK:  orr v16.8h, #0x1, lsl #8  // encoding: [0x30,0xb4,0x00,0x4f]
+
+//----------------------------------------------------------------------
+// Vector Move Immediate Masked
+//----------------------------------------------------------------------
+         movi v0.2s, #1, msl #8
+         movi v1.2s, #1, msl #16
+         movi v0.4s, #1, msl #8
+         movi v31.4s, #1, msl #16
+
+// CHECK:  movi v0.2s, #0x1, msl #8   // encoding: [0x20,0xc4,0x00,0x0f]
+// CHECK:  movi v1.2s, #0x1, msl #16  // encoding: [0x21,0xd4,0x00,0x0f]
+// CHECK:  movi v0.4s, #0x1, msl #8   // encoding: [0x20,0xc4,0x00,0x4f]
+// CHECK:  movi v31.4s, #0x1, msl #16 // encoding: [0x3f,0xd4,0x00,0x4f]
+
+//----------------------------------------------------------------------
+// Vector Move Inverted Immediate Masked
+//----------------------------------------------------------------------
+         mvni v1.2s, #0x1, msl #8
+         mvni v0.2s, #0x1, msl #16
+         mvni v31.4s, #0x1, msl #8
+         mvni v0.4s, #0x1, msl #16
+
+// CHECK:   mvni v1.2s, #0x1, msl #8  // encoding: [0x21,0xc4,0x00,0x2f]
+// CHECK:   mvni v0.2s, #0x1, msl #16 // encoding: [0x20,0xd4,0x00,0x2f]
+// CHECK:   mvni v31.4s, #0x1, msl #8 // encoding: [0x3f,0xc4,0x00,0x6f]
+// CHECK:   mvni v0.4s, #0x1, msl #16 // encoding: [0x20,0xd4,0x00,0x6f]
+
+//----------------------------------------------------------------------
+// Vector Immediate - per byte
+//----------------------------------------------------------------------
+         movi v0.8b, #0
+         movi v31.8b, #0xff
+         movi v15.16b, #0xf
+         movi v31.16b, #0x1f
+
+// CHECK:   movi v0.8b, #0x0        // encoding: [0x00,0xe4,0x00,0x0f]
+// CHECK:   movi v31.8b, #0xff      // encoding: [0xff,0xe7,0x07,0x0f]
+// CHECK:   movi v15.16b, #0xf      // encoding: [0xef,0xe5,0x00,0x4f]
+// CHECK:   movi v31.16b, #0x1f     // encoding: [0xff,0xe7,0x00,0x4f]
+
+//----------------------------------------------------------------------
+// Vector Move Immediate - bytemask, per doubleword
+//---------------------------------------------------------------------
+         movi v0.2d, #0xff00ff00ff00ff00
+
+// CHECK: movi v0.2d, #0xff00ff00ff00ff00 // encoding: [0x40,0xe5,0x05,0x6f]
+
+//----------------------------------------------------------------------
+// Vector Move Immediate - bytemask, one doubleword
+//----------------------------------------------------------------------
+         movi d0, #0xff00ff00ff00ff00
+
+// CHECK: movi d0,  #0xff00ff00ff00ff00 // encoding: [0x40,0xe5,0x05,0x2f]
+
+//----------------------------------------------------------------------
+// Vector Floating Point Move Immediate
+//----------------------------------------------------------------------
+         fmov v1.2s, #1.0
+         fmov v15.4s, #1.0
+         fmov v31.2d, #1.0
+
+// CHECK:  fmov v1.2s, #1.00000000     // encoding: [0x01,0xf6,0x03,0x0f]
+// CHECK:  fmov v15.4s, #1.00000000    // encoding: [0x0f,0xf6,0x03,0x4f]
+// CHECK:  fmov v31.2d, #1.00000000    // encoding: [0x1f,0xf6,0x03,0x6f]
+
+
+//----------------------------------------------------------------------
+// Vector Move -  register
+//----------------------------------------------------------------------
+      mov v0.8b, v31.8b
+      mov v15.16b, v16.16b
+      orr v0.8b, v31.8b, v31.8b
+      orr v15.16b, v16.16b, v16.16b
+
+// CHECK:   mov v0.8b, v31.8b     // encoding: [0xe0,0x1f,0xbf,0x0e]
+// CHECK:   mov v15.16b, v16.16b  // encoding: [0x0f,0x1e,0xb0,0x4e]
+// CHECK:   mov v0.8b, v31.8b     // encoding: [0xe0,0x1f,0xbf,0x0e]
+// CHECK:   mov v15.16b, v16.16b  // encoding: [0x0f,0x1e,0xb0,0x4e]
+
diff --git a/test/MC/AArch64/neon-mul-div-instructions.s b/test/MC/AArch64/neon-mul-div-instructions.s
new file mode 100644
index 0000000..1fe6d2b
--- /dev/null
+++ b/test/MC/AArch64/neon-mul-div-instructions.s
@@ -0,0 +1,86 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+//----------------------------------------------------------------------
+// Vector Integer Mul
+//----------------------------------------------------------------------
+         mul v0.8b, v1.8b, v2.8b
+         mul v0.16b, v1.16b, v2.16b
+         mul v0.4h, v1.4h, v2.4h
+         mul v0.8h, v1.8h, v2.8h
+         mul v0.2s, v1.2s, v2.2s
+         mul v0.4s, v1.4s, v2.4s
+
+// CHECK: mul v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x9c,0x22,0x0e]
+// CHECK: mul v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x9c,0x22,0x4e]
+// CHECK: mul v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x9c,0x62,0x0e]
+// CHECK: mul v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x9c,0x62,0x4e]
+// CHECK: mul v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x9c,0xa2,0x0e]
+// CHECK: mul v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x9c,0xa2,0x4e]
+
+
+//----------------------------------------------------------------------
+// Vector Floating-Point Mul
+//----------------------------------------------------------------------
+         fmul v0.2s, v1.2s, v2.2s
+         fmul v0.4s, v1.4s, v2.4s
+         fmul v0.2d, v1.2d, v2.2d
+
+// CHECK: fmul v0.2s, v1.2s, v2.2s       // encoding: [0x20,0xdc,0x22,0x2e]
+// CHECK: fmul v0.4s, v1.4s, v2.4s       // encoding: [0x20,0xdc,0x22,0x6e]
+// CHECK: fmul v0.2d, v1.2d, v2.2d       // encoding: [0x20,0xdc,0x62,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Floating-Point Div
+//----------------------------------------------------------------------
+         fdiv v0.2s, v1.2s, v2.2s
+         fdiv v0.4s, v1.4s, v2.4s
+         fdiv v0.2d, v1.2d, v2.2d
+
+// CHECK: fdiv v0.2s, v1.2s, v2.2s       // encoding: [0x20,0xfc,0x22,0x2e]
+// CHECK: fdiv v0.4s, v1.4s, v2.4s       // encoding: [0x20,0xfc,0x22,0x6e]
+// CHECK: fdiv v0.2d, v1.2d, v2.2d       // encoding: [0x20,0xfc,0x62,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Multiply (Polynomial)
+//----------------------------------------------------------------------
+         pmul v17.8b, v31.8b, v16.8b
+         pmul v0.16b, v1.16b, v2.16b
+
+// CHECK: pmul v17.8b, v31.8b, v16.8b     // encoding: [0xf1,0x9f,0x30,0x2e]
+// CHECK: pmul v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x9c,0x22,0x6e]
+
+//----------------------------------------------------------------------
+// Vector Saturating Doubling Multiply High
+//----------------------------------------------------------------------
+         sqdmulh v2.4h, v25.4h, v3.4h
+         sqdmulh v12.8h, v5.8h, v13.8h
+         sqdmulh v3.2s, v1.2s, v30.2s
+
+// CHECK: sqdmulh v2.4h, v25.4h, v3.4h    // encoding: [0x22,0xb7,0x63,0x0e]
+// CHECK: sqdmulh v12.8h, v5.8h, v13.8h   // encoding: [0xac,0xb4,0x6d,0x4e]
+// CHECK: sqdmulh v3.2s, v1.2s, v30.2s    // encoding: [0x23,0xb4,0xbe,0x0e]
+
+//----------------------------------------------------------------------
+// Vector Saturating Rouding Doubling Multiply High
+//----------------------------------------------------------------------
+         sqrdmulh v2.4h, v25.4h, v3.4h
+         sqrdmulh v12.8h, v5.8h, v13.8h
+         sqrdmulh v3.2s, v1.2s, v30.2s
+
+// CHECK: sqrdmulh v2.4h, v25.4h, v3.4h    // encoding: [0x22,0xb7,0x63,0x2e]
+// CHECK: sqrdmulh v12.8h, v5.8h, v13.8h   // encoding: [0xac,0xb4,0x6d,0x6e]
+// CHECK: sqrdmulh v3.2s, v1.2s, v30.2s    // encoding: [0x23,0xb4,0xbe,0x2e]
+
+//----------------------------------------------------------------------
+// Vector Multiply Extended
+//----------------------------------------------------------------------
+      fmulx v21.2s, v5.2s, v13.2s
+      fmulx v1.4s, v25.4s, v3.4s
+      fmulx v31.2d, v22.2d, v2.2d
+
+// CHECK: fmulx v21.2s, v5.2s, v13.2s // encoding: [0xb5,0xdc,0x2d,0x0e]
+// CHECK: fmulx v1.4s, v25.4s, v3.4s // encoding: [0x21,0xdf,0x23,0x4e]
+// CHECK: fmulx v31.2d, v22.2d, v2.2d // encoding: [0xdf,0xde,0x62,0x4e]
+
diff --git a/test/MC/AArch64/neon-rounding-halving-add.s b/test/MC/AArch64/neon-rounding-halving-add.s
new file mode 100644
index 0000000..47ac212
--- /dev/null
+++ b/test/MC/AArch64/neon-rounding-halving-add.s
@@ -0,0 +1,39 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+
+//------------------------------------------------------------------------------
+// Vector Integer Rouding Halving Add (Signed)
+//------------------------------------------------------------------------------
+         srhadd v0.8b, v1.8b, v2.8b
+         srhadd v0.16b, v1.16b, v2.16b
+         srhadd v0.4h, v1.4h, v2.4h
+         srhadd v0.8h, v1.8h, v2.8h
+         srhadd v0.2s, v1.2s, v2.2s
+         srhadd v0.4s, v1.4s, v2.4s
+
+// CHECK: srhadd v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x14,0x22,0x0e]
+// CHECK: srhadd v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x14,0x22,0x4e]
+// CHECK: srhadd v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x14,0x62,0x0e]
+// CHECK: srhadd v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x14,0x62,0x4e]
+// CHECK: srhadd v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x14,0xa2,0x0e]
+// CHECK: srhadd v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x14,0xa2,0x4e]
+
+//------------------------------------------------------------------------------
+// Vector Integer Rouding Halving Add (Unsigned)
+//------------------------------------------------------------------------------
+         urhadd v0.8b, v1.8b, v2.8b
+         urhadd v0.16b, v1.16b, v2.16b
+         urhadd v0.4h, v1.4h, v2.4h
+         urhadd v0.8h, v1.8h, v2.8h
+         urhadd v0.2s, v1.2s, v2.2s
+         urhadd v0.4s, v1.4s, v2.4s
+
+// CHECK: urhadd v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x14,0x22,0x2e]
+// CHECK: urhadd v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x14,0x22,0x6e]
+// CHECK: urhadd v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x14,0x62,0x2e]
+// CHECK: urhadd v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x14,0x62,0x6e]
+// CHECK: urhadd v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x14,0xa2,0x2e]
+// CHECK: urhadd v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x14,0xa2,0x6e]
+
diff --git a/test/MC/AArch64/neon-rounding-shift.s b/test/MC/AArch64/neon-rounding-shift.s
new file mode 100644
index 0000000..f3c70d7
--- /dev/null
+++ b/test/MC/AArch64/neon-rounding-shift.s
@@ -0,0 +1,57 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+
+//------------------------------------------------------------------------------
+// Vector Integer Rounding Shift Lef (Signed)
+//------------------------------------------------------------------------------
+         srshl v0.8b, v1.8b, v2.8b
+         srshl v0.16b, v1.16b, v2.16b
+         srshl v0.4h, v1.4h, v2.4h
+         srshl v0.8h, v1.8h, v2.8h
+         srshl v0.2s, v1.2s, v2.2s
+         srshl v0.4s, v1.4s, v2.4s
+         srshl v0.2d, v1.2d, v2.2d
+
+// CHECK: srshl v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x54,0x22,0x0e]
+// CHECK: srshl v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x54,0x22,0x4e]
+// CHECK: srshl v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x54,0x62,0x0e]
+// CHECK: srshl v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x54,0x62,0x4e]
+// CHECK: srshl v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x54,0xa2,0x0e]
+// CHECK: srshl v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x54,0xa2,0x4e]
+// CHECK: srshl v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x54,0xe2,0x4e]
+
+//------------------------------------------------------------------------------
+// Vector Integer Rounding Shift Lef (Unsigned)
+//------------------------------------------------------------------------------
+         urshl v0.8b, v1.8b, v2.8b
+         urshl v0.16b, v1.16b, v2.16b
+         urshl v0.4h, v1.4h, v2.4h
+         urshl v0.8h, v1.8h, v2.8h
+         urshl v0.2s, v1.2s, v2.2s
+         urshl v0.4s, v1.4s, v2.4s
+         urshl v0.2d, v1.2d, v2.2d
+
+// CHECK: urshl v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x54,0x22,0x2e]
+// CHECK: urshl v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x54,0x22,0x6e]
+// CHECK: urshl v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x54,0x62,0x2e]
+// CHECK: urshl v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x54,0x62,0x6e]
+// CHECK: urshl v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x54,0xa2,0x2e]
+// CHECK: urshl v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x54,0xa2,0x6e]
+// CHECK: urshl v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x54,0xe2,0x6e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Rounding Shift Lef (Signed)
+//------------------------------------------------------------------------------
+         srshl d17, d31, d8
+
+// CHECK: srshl d17, d31, d8      // encoding: [0xf1,0x57,0xe8,0x5e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Rounding Shift Lef (Unsigned)
+//------------------------------------------------------------------------------
+         urshl d17, d31, d8
+
+// CHECK: urshl d17, d31, d8      // encoding: [0xf1,0x57,0xe8,0x7e]
+
diff --git a/test/MC/AArch64/neon-saturating-add-sub.s b/test/MC/AArch64/neon-saturating-add-sub.s
new file mode 100644
index 0000000..1032ae4
--- /dev/null
+++ b/test/MC/AArch64/neon-saturating-add-sub.s
@@ -0,0 +1,133 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+
+//------------------------------------------------------------------------------
+// Vector Integer Saturating Add (Signed)
+//------------------------------------------------------------------------------
+         sqadd v0.8b, v1.8b, v2.8b
+         sqadd v0.16b, v1.16b, v2.16b
+         sqadd v0.4h, v1.4h, v2.4h
+         sqadd v0.8h, v1.8h, v2.8h
+         sqadd v0.2s, v1.2s, v2.2s
+         sqadd v0.4s, v1.4s, v2.4s
+         sqadd v0.2d, v1.2d, v2.2d
+
+// CHECK: sqadd v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x0c,0x22,0x0e]
+// CHECK: sqadd v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x0c,0x22,0x4e]
+// CHECK: sqadd v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x0c,0x62,0x0e]
+// CHECK: sqadd v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x0c,0x62,0x4e]
+// CHECK: sqadd v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x0c,0xa2,0x0e]
+// CHECK: sqadd v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x0c,0xa2,0x4e]
+// CHECK: sqadd v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x0c,0xe2,0x4e]
+
+//------------------------------------------------------------------------------
+// Vector Integer Saturating Add (Unsigned)
+//------------------------------------------------------------------------------
+         uqadd v0.8b, v1.8b, v2.8b
+         uqadd v0.16b, v1.16b, v2.16b
+         uqadd v0.4h, v1.4h, v2.4h
+         uqadd v0.8h, v1.8h, v2.8h
+         uqadd v0.2s, v1.2s, v2.2s
+         uqadd v0.4s, v1.4s, v2.4s
+         uqadd v0.2d, v1.2d, v2.2d
+
+// CHECK: uqadd v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x0c,0x22,0x2e]
+// CHECK: uqadd v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x0c,0x22,0x6e]
+// CHECK: uqadd v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x0c,0x62,0x2e]
+// CHECK: uqadd v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x0c,0x62,0x6e]
+// CHECK: uqadd v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x0c,0xa2,0x2e]
+// CHECK: uqadd v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x0c,0xa2,0x6e]
+// CHECK: uqadd v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x0c,0xe2,0x6e]
+
+//------------------------------------------------------------------------------
+// Vector Integer Saturating Sub (Signed)
+//------------------------------------------------------------------------------
+         sqsub v0.8b, v1.8b, v2.8b
+         sqsub v0.16b, v1.16b, v2.16b
+         sqsub v0.4h, v1.4h, v2.4h
+         sqsub v0.8h, v1.8h, v2.8h
+         sqsub v0.2s, v1.2s, v2.2s
+         sqsub v0.4s, v1.4s, v2.4s
+         sqsub v0.2d, v1.2d, v2.2d
+
+// CHECK: sqsub v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x2c,0x22,0x0e]
+// CHECK: sqsub v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x2c,0x22,0x4e]
+// CHECK: sqsub v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x2c,0x62,0x0e]
+// CHECK: sqsub v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x2c,0x62,0x4e]
+// CHECK: sqsub v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x2c,0xa2,0x0e]
+// CHECK: sqsub v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x2c,0xa2,0x4e]
+// CHECK: sqsub v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x2c,0xe2,0x4e]
+
+//------------------------------------------------------------------------------
+// Vector Integer Saturating Sub (Unsigned)
+//------------------------------------------------------------------------------
+         uqsub v0.8b, v1.8b, v2.8b
+         uqsub v0.16b, v1.16b, v2.16b
+         uqsub v0.4h, v1.4h, v2.4h
+         uqsub v0.8h, v1.8h, v2.8h
+         uqsub v0.2s, v1.2s, v2.2s
+         uqsub v0.4s, v1.4s, v2.4s
+         uqsub v0.2d, v1.2d, v2.2d
+
+// CHECK: uqsub v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x2c,0x22,0x2e]
+// CHECK: uqsub v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x2c,0x22,0x6e]
+// CHECK: uqsub v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x2c,0x62,0x2e]
+// CHECK: uqsub v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x2c,0x62,0x6e]
+// CHECK: uqsub v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x2c,0xa2,0x2e]
+// CHECK: uqsub v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x2c,0xa2,0x6e]
+// CHECK: uqsub v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x2c,0xe2,0x6e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Saturating Add (Signed)
+//------------------------------------------------------------------------------
+         sqadd b0, b1, b2
+         sqadd h10, h11, h12
+         sqadd s20, s21, s2
+         sqadd d17, d31, d8
+
+// CHECK: sqadd b0, b1, b2        // encoding: [0x20,0x0c,0x22,0x5e]
+// CHECK: sqadd h10, h11, h12     // encoding: [0x6a,0x0d,0x6c,0x5e]
+// CHECK: sqadd s20, s21, s2      // encoding: [0xb4,0x0e,0xa2,0x5e]
+// CHECK: sqadd d17, d31, d8      // encoding: [0xf1,0x0f,0xe8,0x5e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Saturating Add (Unsigned)
+//------------------------------------------------------------------------------
+         uqadd b0, b1, b2
+         uqadd h10, h11, h12
+         uqadd s20, s21, s2
+         uqadd d17, d31, d8
+
+// CHECK: uqadd b0, b1, b2        // encoding: [0x20,0x0c,0x22,0x7e]
+// CHECK: uqadd h10, h11, h12     // encoding: [0x6a,0x0d,0x6c,0x7e]
+// CHECK: uqadd s20, s21, s2      // encoding: [0xb4,0x0e,0xa2,0x7e]
+// CHECK: uqadd d17, d31, d8      // encoding: [0xf1,0x0f,0xe8,0x7e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Saturating Sub (Signed)
+//------------------------------------------------------------------------------
+         sqsub b0, b1, b2
+         sqsub h10, h11, h12
+         sqsub s20, s21, s2
+         sqsub d17, d31, d8
+
+// CHECK: sqsub b0, b1, b2        // encoding: [0x20,0x2c,0x22,0x5e]
+// CHECK: sqsub h10, h11, h12     // encoding: [0x6a,0x2d,0x6c,0x5e]
+// CHECK: sqsub s20, s21, s2      // encoding: [0xb4,0x2e,0xa2,0x5e]
+// CHECK: sqsub d17, d31, d8      // encoding: [0xf1,0x2f,0xe8,0x5e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Saturating Sub (Unsigned)
+//------------------------------------------------------------------------------
+         uqsub b0, b1, b2
+         uqsub h10, h11, h12
+         uqsub s20, s21, s2
+         uqsub d17, d31, d8
+
+// CHECK: uqsub b0, b1, b2        // encoding: [0x20,0x2c,0x22,0x7e]
+// CHECK: uqsub h10, h11, h12     // encoding: [0x6a,0x2d,0x6c,0x7e]
+// CHECK: uqsub s20, s21, s2      // encoding: [0xb4,0x2e,0xa2,0x7e]
+// CHECK: uqsub d17, d31, d8      // encoding: [0xf1,0x2f,0xe8,0x7e]
+
diff --git a/test/MC/AArch64/neon-saturating-rounding-shift.s b/test/MC/AArch64/neon-saturating-rounding-shift.s
new file mode 100644
index 0000000..a36e689
--- /dev/null
+++ b/test/MC/AArch64/neon-saturating-rounding-shift.s
@@ -0,0 +1,70 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+
+//------------------------------------------------------------------------------
+// Vector Integer Saturating Rounding Shift Lef (Signed)
+//------------------------------------------------------------------------------
+         sqrshl v0.8b, v1.8b, v2.8b
+         sqrshl v0.16b, v1.16b, v2.16b
+         sqrshl v0.4h, v1.4h, v2.4h
+         sqrshl v0.8h, v1.8h, v2.8h
+         sqrshl v0.2s, v1.2s, v2.2s
+         sqrshl v0.4s, v1.4s, v2.4s
+         sqrshl v0.2d, v1.2d, v2.2d
+
+// CHECK: sqrshl v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x5c,0x22,0x0e]
+// CHECK: sqrshl v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x5c,0x22,0x4e]
+// CHECK: sqrshl v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x5c,0x62,0x0e]
+// CHECK: sqrshl v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x5c,0x62,0x4e]
+// CHECK: sqrshl v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x5c,0xa2,0x0e]
+// CHECK: sqrshl v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x5c,0xa2,0x4e]
+// CHECK: sqrshl v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x5c,0xe2,0x4e]
+
+//------------------------------------------------------------------------------
+// Vector Integer Saturating Rounding Shift Lef (Unsigned)
+//------------------------------------------------------------------------------
+         uqrshl v0.8b, v1.8b, v2.8b
+         uqrshl v0.16b, v1.16b, v2.16b
+         uqrshl v0.4h, v1.4h, v2.4h
+         uqrshl v0.8h, v1.8h, v2.8h
+         uqrshl v0.2s, v1.2s, v2.2s
+         uqrshl v0.4s, v1.4s, v2.4s
+         uqrshl v0.2d, v1.2d, v2.2d
+
+// CHECK: uqrshl v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x5c,0x22,0x2e]
+// CHECK: uqrshl v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x5c,0x22,0x6e]
+// CHECK: uqrshl v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x5c,0x62,0x2e]
+// CHECK: uqrshl v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x5c,0x62,0x6e]
+// CHECK: uqrshl v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x5c,0xa2,0x2e]
+// CHECK: uqrshl v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x5c,0xa2,0x6e]
+// CHECK: uqrshl v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x5c,0xe2,0x6e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Saturating Rounding Shift Lef (Signed)
+//------------------------------------------------------------------------------
+         sqrshl b0, b1, b2
+         sqrshl h10, h11, h12
+         sqrshl s20, s21, s2
+         sqrshl d17, d31, d8
+
+// CHECK: sqrshl b0, b1, b2        // encoding: [0x20,0x5c,0x22,0x5e]
+// CHECK: sqrshl h10, h11, h12     // encoding: [0x6a,0x5d,0x6c,0x5e]
+// CHECK: sqrshl s20, s21, s2      // encoding: [0xb4,0x5e,0xa2,0x5e]
+// CHECK: sqrshl d17, d31, d8      // encoding: [0xf1,0x5f,0xe8,0x5e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Saturating Rounding Shift Lef (Unsigned)
+//------------------------------------------------------------------------------
+         uqrshl b0, b1, b2
+         uqrshl h10, h11, h12
+         uqrshl s20, s21, s2
+         uqrshl d17, d31, d8
+
+// CHECK: uqrshl b0, b1, b2        // encoding: [0x20,0x5c,0x22,0x7e]
+// CHECK: uqrshl h10, h11, h12     // encoding: [0x6a,0x5d,0x6c,0x7e]
+// CHECK: uqrshl s20, s21, s2      // encoding: [0xb4,0x5e,0xa2,0x7e]
+// CHECK: uqrshl d17, d31, d8      // encoding: [0xf1,0x5f,0xe8,0x7e]
+
+
diff --git a/test/MC/AArch64/neon-saturating-shift.s b/test/MC/AArch64/neon-saturating-shift.s
new file mode 100644
index 0000000..2c8456d
--- /dev/null
+++ b/test/MC/AArch64/neon-saturating-shift.s
@@ -0,0 +1,69 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+
+//------------------------------------------------------------------------------
+// Vector Integer Saturating Shift Lef (Signed)
+//------------------------------------------------------------------------------
+         sqshl v0.8b, v1.8b, v2.8b
+         sqshl v0.16b, v1.16b, v2.16b
+         sqshl v0.4h, v1.4h, v2.4h
+         sqshl v0.8h, v1.8h, v2.8h
+         sqshl v0.2s, v1.2s, v2.2s
+         sqshl v0.4s, v1.4s, v2.4s
+         sqshl v0.2d, v1.2d, v2.2d
+
+// CHECK: sqshl v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x4c,0x22,0x0e]
+// CHECK: sqshl v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x4c,0x22,0x4e]
+// CHECK: sqshl v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x4c,0x62,0x0e]
+// CHECK: sqshl v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x4c,0x62,0x4e]
+// CHECK: sqshl v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x4c,0xa2,0x0e]
+// CHECK: sqshl v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x4c,0xa2,0x4e]
+// CHECK: sqshl v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x4c,0xe2,0x4e]
+
+//------------------------------------------------------------------------------
+// Vector Integer Saturating Shift Lef (Unsigned)
+//------------------------------------------------------------------------------
+         uqshl v0.8b, v1.8b, v2.8b
+         uqshl v0.16b, v1.16b, v2.16b
+         uqshl v0.4h, v1.4h, v2.4h
+         uqshl v0.8h, v1.8h, v2.8h
+         uqshl v0.2s, v1.2s, v2.2s
+         uqshl v0.4s, v1.4s, v2.4s
+         uqshl v0.2d, v1.2d, v2.2d
+
+// CHECK: uqshl v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x4c,0x22,0x2e]
+// CHECK: uqshl v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x4c,0x22,0x6e]
+// CHECK: uqshl v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x4c,0x62,0x2e]
+// CHECK: uqshl v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x4c,0x62,0x6e]
+// CHECK: uqshl v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x4c,0xa2,0x2e]
+// CHECK: uqshl v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x4c,0xa2,0x6e]
+// CHECK: uqshl v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x4c,0xe2,0x6e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Saturating Shift Lef (Signed)
+//------------------------------------------------------------------------------
+         sqshl b0, b1, b2
+         sqshl h10, h11, h12
+         sqshl s20, s21, s2
+         sqshl d17, d31, d8
+
+// CHECK: sqshl b0, b1, b2        // encoding: [0x20,0x4c,0x22,0x5e]
+// CHECK: sqshl h10, h11, h12     // encoding: [0x6a,0x4d,0x6c,0x5e]
+// CHECK: sqshl s20, s21, s2      // encoding: [0xb4,0x4e,0xa2,0x5e]
+// CHECK: sqshl d17, d31, d8      // encoding: [0xf1,0x4f,0xe8,0x5e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Saturating Shift Lef (Unsigned)
+//------------------------------------------------------------------------------
+         uqshl b0, b1, b2
+         uqshl h10, h11, h12
+         uqshl s20, s21, s2
+         uqshl d17, d31, d8
+
+// CHECK: uqshl b0, b1, b2        // encoding: [0x20,0x4c,0x22,0x7e]
+// CHECK: uqshl h10, h11, h12     // encoding: [0x6a,0x4d,0x6c,0x7e]
+// CHECK: uqshl s20, s21, s2      // encoding: [0xb4,0x4e,0xa2,0x7e]
+// CHECK: uqshl d17, d31, d8      // encoding: [0xf1,0x4f,0xe8,0x7e]
+
diff --git a/test/MC/AArch64/neon-shift.s b/test/MC/AArch64/neon-shift.s
new file mode 100644
index 0000000..be1799e
--- /dev/null
+++ b/test/MC/AArch64/neon-shift.s
@@ -0,0 +1,57 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
+
+// Check that the assembler can handle the documented syntax for AArch64
+
+
+//------------------------------------------------------------------------------
+// Vector Integer Shift Lef (Signed)
+//------------------------------------------------------------------------------
+         sshl v0.8b, v1.8b, v2.8b
+         sshl v0.16b, v1.16b, v2.16b
+         sshl v0.4h, v1.4h, v2.4h
+         sshl v0.8h, v1.8h, v2.8h
+         sshl v0.2s, v1.2s, v2.2s
+         sshl v0.4s, v1.4s, v2.4s
+         sshl v0.2d, v1.2d, v2.2d
+
+// CHECK: sshl v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x44,0x22,0x0e]
+// CHECK: sshl v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x44,0x22,0x4e]
+// CHECK: sshl v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x44,0x62,0x0e]
+// CHECK: sshl v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x44,0x62,0x4e]
+// CHECK: sshl v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x44,0xa2,0x0e]
+// CHECK: sshl v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x44,0xa2,0x4e]
+// CHECK: sshl v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x44,0xe2,0x4e]
+
+//------------------------------------------------------------------------------
+// Vector Integer Shift Lef (Unsigned)
+//------------------------------------------------------------------------------
+         ushl v0.8b, v1.8b, v2.8b
+         ushl v0.16b, v1.16b, v2.16b
+         ushl v0.4h, v1.4h, v2.4h
+         ushl v0.8h, v1.8h, v2.8h
+         ushl v0.2s, v1.2s, v2.2s
+         ushl v0.4s, v1.4s, v2.4s
+         ushl v0.2d, v1.2d, v2.2d
+
+// CHECK: ushl v0.8b, v1.8b, v2.8b        // encoding: [0x20,0x44,0x22,0x2e]
+// CHECK: ushl v0.16b, v1.16b, v2.16b     // encoding: [0x20,0x44,0x22,0x6e]
+// CHECK: ushl v0.4h, v1.4h, v2.4h        // encoding: [0x20,0x44,0x62,0x2e]
+// CHECK: ushl v0.8h, v1.8h, v2.8h        // encoding: [0x20,0x44,0x62,0x6e]
+// CHECK: ushl v0.2s, v1.2s, v2.2s        // encoding: [0x20,0x44,0xa2,0x2e]
+// CHECK: ushl v0.4s, v1.4s, v2.4s        // encoding: [0x20,0x44,0xa2,0x6e]
+// CHECK: ushl v0.2d, v1.2d, v2.2d        // encoding: [0x20,0x44,0xe2,0x6e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Shift Lef (Signed)
+//------------------------------------------------------------------------------
+         sshl d17, d31, d8
+
+// CHECK: sshl d17, d31, d8      // encoding: [0xf1,0x47,0xe8,0x5e]
+
+//------------------------------------------------------------------------------
+// Scalar Integer Shift Lef (Unsigned)
+//------------------------------------------------------------------------------
+         ushl d17, d31, d8
+
+// CHECK: ushl d17, d31, d8      // encoding: [0xf1,0x47,0xe8,0x7e]
+
diff --git a/test/MC/AArch64/noneon-diagnostics.s b/test/MC/AArch64/noneon-diagnostics.s
new file mode 100644
index 0000000..ea786c0
--- /dev/null
+++ b/test/MC/AArch64/noneon-diagnostics.s
@@ -0,0 +1,28 @@
+// RUN: not llvm-mc  -triple aarch64-none-linux-gnu -mattr=-neon < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
+
+        fmla v3.4s, v12.4s, v17.4s
+        fmla v1.2d, v30.2d, v20.2d
+        fmla v9.2s, v9.2s, v0.2s
+// CHECK-ERROR: error: instruction requires a CPU feature not currently enabled
+// CHECK-ERROR-NEXT:    fmla v3.4s, v12.4s, v17.4s
+// CHECK-ERROR-NEXT:    ^
+// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled
+// CHECK-ERROR-NEXT:    fmla v1.2d, v30.2d, v20.2d
+// CHECK-ERROR-NEXT:    ^
+// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled
+// CHECK-ERROR-NEXT:    fmla v9.2s, v9.2s, v0.2s
+// CHECK-ERROR-NEXT:    ^
+
+        fmls v3.4s, v12.4s, v17.4s
+        fmls v1.2d, v30.2d, v20.2d
+        fmls v9.2s, v9.2s, v0.2s
+// CHECK-ERROR: error: instruction requires a CPU feature not currently enabled
+// CHECK-ERROR-NEXT:    fmls v3.4s, v12.4s, v17.4s
+// CHECK-ERROR-NEXT:    ^
+// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled
+// CHECK-ERROR-NEXT:    fmls v1.2d, v30.2d, v20.2d
+// CHECK-ERROR-NEXT:    ^
+// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled
+// CHECK-ERROR-NEXT:    fmls v9.2s, v9.2s, v0.2s
+// CHECK-ERROR-NEXT:    ^
diff --git a/test/MC/AArch64/tls-relocs.s b/test/MC/AArch64/tls-relocs.s
index 5cbd794..f99cb41 100644
--- a/test/MC/AArch64/tls-relocs.s
+++ b/test/MC/AArch64/tls-relocs.s
@@ -30,11 +30,11 @@
         movn w8, #:dtprel_g1:var
 // CHECK: movz    x5, #:dtprel_g1:var     // encoding: [0x05'A',A,0xa0'A',0x92'A']
 // CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1
-// CHECK-NEXT: movn    x6, #:dtprel_g1:var     // encoding: [0x06'A',A,0xa0'A',0x92'A']
+// CHECK: movn    x6, #:dtprel_g1:var     // encoding: [0x06'A',A,0xa0'A',0x92'A']
 // CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1
-// CHECK-NEXT: movz    w7, #:dtprel_g1:var     // encoding: [0x07'A',A,0xa0'A',0x12'A']
+// CHECK: movz    w7, #:dtprel_g1:var     // encoding: [0x07'A',A,0xa0'A',0x12'A']
 // CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1
-// CHECK-NEXT: movn    w8, #:dtprel_g1:var     // encoding: [0x08'A',A,0xa0'A',0x12'A']
+// CHECK: movn    w8, #:dtprel_g1:var     // encoding: [0x08'A',A,0xa0'A',0x12'A']
 // CHECK-NEXT:                                 //   fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1
 
 // CHECK-ELF-NEXT:     0x10 R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]]
diff --git a/test/MC/AArch64/trace-regs-diagnostics.s b/test/MC/AArch64/trace-regs-diagnostics.s
index 82ec7c0..41331e7 100644
--- a/test/MC/AArch64/trace-regs-diagnostics.s
+++ b/test/MC/AArch64/trace-regs-diagnostics.s
@@ -1,4 +1,4 @@
-// RUN: llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s
         // Write-only
         mrs x12, trcoslar
         mrs x10, trclar
diff --git a/test/MC/ARM/arm-thumb-cpus.s b/test/MC/ARM/arm-thumb-cpus.s
index c15e807..24be989 100644
--- a/test/MC/ARM/arm-thumb-cpus.s
+++ b/test/MC/ARM/arm-thumb-cpus.s
@@ -1,9 +1,9 @@
-@ RUN: llvm-mc -show-encoding -arch=arm < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ARM-ONLY
+@ RUN: not llvm-mc -show-encoding -arch=arm < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ARM-ONLY
 @ RUN: llvm-mc -show-encoding -triple=armv4t < %s 2>&1| FileCheck %s --check-prefix=CHECK-ARM-THUMB
 @ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-a15 < %s 2>&1| FileCheck %s --check-prefix=CHECK-ARM-THUMB
-@ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-m3 < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
-@ RUN: llvm-mc -show-encoding -triple=armv7m < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
-@ RUN: llvm-mc -show-encoding -triple=armv6m < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
+@ RUN: not llvm-mc -show-encoding -arch=arm -mcpu=cortex-m3 < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
+@ RUN: not llvm-mc -show-encoding -triple=armv7m < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
+@ RUN: not llvm-mc -show-encoding -triple=armv6m < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
 
         @ Make sure correct diagnostics are given for CPUs without support for
         @ one or other of the execution states.
diff --git a/test/MC/ARM/arm-thumb-trustzone.s b/test/MC/ARM/arm-thumb-trustzone.s
index a080b3e..7755a3c 100644
--- a/test/MC/ARM/arm-thumb-trustzone.s
+++ b/test/MC/ARM/arm-thumb-trustzone.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
+@ RUN: not llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
 @ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ
 
   .syntax unified
diff --git a/test/MC/ARM/arm-trustzone.s b/test/MC/ARM/arm-trustzone.s
index 69157f6..72bac48e 100644
--- a/test/MC/ARM/arm-trustzone.s
+++ b/test/MC/ARM/arm-trustzone.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
+@ RUN: not llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ
 @ RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ
 
   .syntax unified
diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 8aec4b3..ead2ce1 100644
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -459,10 +459,14 @@ Lforward:
 @------------------------------------------------------------------------------
         cdp  p7, #1, c1, c1, c1, #4
         cdp2  p7, #1, c1, c1, c1, #4
+        cdp2   p10, #0, c6, c12, c0, #7
 
 @ CHECK: cdp  p7, #1, c1, c1, c1, #4     @ encoding: [0x81,0x17,0x11,0xee]
 @ CHECK: cdp2  p7, #1, c1, c1, c1, #4    @ encoding: [0x81,0x17,0x11,0xfe]
+@ CHECK: cdp2  p10, #0, c6, c12, c0, #7   @ encoding: [0xe0,0x6a,0x0c,0xfe]
 
+        cdpne  p7, #1, c1, c1, c1, #4
+@ CHECK: cdpne  p7, #1, c1, c1, c1, #4     @ encoding: [0x81,0x17,0x11,0x1e]
 
 @------------------------------------------------------------------------------
 @ CLREX
@@ -904,8 +908,8 @@ Lforward:
 @ CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe9]
 @ CHECK: ldmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe8]
 @ CHECK: ldmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe9]
-@ CHECK: ldm	r0, {lr, r0, r2} ^          @ encoding: [0x05,0x40,0xd0,0xe8]
-@ CHECK: ldm	sp!, {pc, r0, r1, r2, r3} ^ @ encoding: [0x0f,0x80,0xfd,0xe8]
+@ CHECK: ldm	r0, {r0, r2, lr} ^          @ encoding: [0x05,0x40,0xd0,0xe8]
+@ CHECK: ldm	sp!, {r0, r1, r2, r3, pc} ^ @ encoding: [0x0f,0x80,0xfd,0xe8]
 
 
 @------------------------------------------------------------------------------
@@ -967,6 +971,9 @@ Lforward:
 @ CHECK: mcr  p7, #1, r5, c1, c1, #4    @ encoding: [0x91,0x57,0x21,0xee]
 @ CHECK: mcr2  p7, #1, r5, c1, c1, #4   @ encoding: [0x91,0x57,0x21,0xfe]
 
+        mcrls  p7, #1, r5, c1, c1, #4
+@ CHECK: mcrls  p7, #1, r5, c1, c1, #4   @ encoding: [0x91,0x57,0x21,0x9e]
+
 @------------------------------------------------------------------------------
 @ MCRR/MCRR2
 @------------------------------------------------------------------------------
@@ -976,6 +983,8 @@ Lforward:
 @ CHECK: mcrr  p7, #15, r5, r4, c1      @ encoding: [0xf1,0x57,0x44,0xec]
 @ CHECK: mcrr2  p7, #15, r5, r4, c1     @ encoding: [0xf1,0x57,0x44,0xfc]
 
+        mcrrgt  p7, #15, r5, r4, c1
+@ CHECK: mcrrgt  p7, #15, r5, r4, c1     @ encoding: [0xf1,0x57,0x44,0xcc]
 
 @------------------------------------------------------------------------------
 @ MLA
@@ -1067,17 +1076,16 @@ Lforward:
 @------------------------------------------------------------------------------
         mrc  p14, #0, r1, c1, c2, #4
         mrc  p15, #7, apsr_nzcv, c15, c6, #6
-        mrc  p15, #7, pc, c15, c6, #6
         mrc2  p14, #0, r1, c1, c2, #4
         mrc2  p10, #7, apsr_nzcv, c15, c0, #1
-        mrc2  p10, #7, pc, c15, c0, #1
 
 @ CHECK: mrc  p14, #0, r1, c1, c2, #4             @ encoding: [0x92,0x1e,0x11,0xee]
 @ CHECK: mrc  p15, #7, apsr_nzcv, c15, c6, #6     @ encoding: [0xd6,0xff,0xff,0xee]
-@ CHECK: mrc  p15, #7, pc, c15, c6, #6            @ encoding: [0xd6,0xff,0xff,0xee]
 @ CHECK: mrc2  p14, #0, r1, c1, c2, #4            @ encoding: [0x92,0x1e,0x11,0xfe]
 @ CHECK: mrc2  p10, #7, apsr_nzcv, c15, c0, #1    @ encoding: [0x30,0xfa,0xff,0xfe]
-@ CHECK: mrc2  p10, #7, pc, c15, c0, #1           @ encoding: [0x30,0xfa,0xff,0xfe]
+
+         mrceq  p15, #7, apsr_nzcv, c15, c6, #6
+@ CHECK: mrceq  p15, #7, apsr_nzcv, c15, c6, #6   @ encoding: [0xd6,0xff,0xff,0x0e]
 
 @------------------------------------------------------------------------------
 @ MRRC/MRRC2
@@ -1088,6 +1096,8 @@ Lforward:
 @ CHECK: mrrc  p7, #1, r5, r4, c1       @ encoding: [0x11,0x57,0x54,0xec]
 @ CHECK: mrrc2  p7, #1, r5, r4, c1      @ encoding: [0x11,0x57,0x54,0xfc]
 
+        mrrclo  p7, #1, r5, r4, c1
+@ CHECK: mrrclo  p7, #1, r5, r4, c1      @ encoding: [0x11,0x57,0x54,0x3c]
 
 @------------------------------------------------------------------------------
 @ MRS
@@ -1247,9 +1257,11 @@ Lforward:
 @ NOP
 @------------------------------------------------------------------------------
         nop
+        nop.w
         nopgt
 
 @ CHECK: nop @ encoding: [0x00,0xf0,0x20,0xe3]
+@ CHECK: nop @ encoding: [0x00,0xf0,0x20,0xe3]
 @ CHECK: nopgt @ encoding: [0x00,0xf0,0x20,0xc3]
 
 
@@ -2109,15 +2121,15 @@ Lforward:
 @ CHECK: srsia	sp!, #2                 @ encoding: [0x02,0x05,0xed,0xf8]
 @ CHECK: srsib	sp!, #14                @ encoding: [0x0e,0x05,0xed,0xf9]
 
-@ CHECK: srsda	sp, #11                 @ encoding: [0x0b,0x05,0x4d,0xf8]
-@ CHECK: srsdb	sp, #10                 @ encoding: [0x0a,0x05,0x4d,0xf9]
-@ CHECK: srsia	sp, #9                  @ encoding: [0x09,0x05,0xcd,0xf8]
-@ CHECK: srsib	sp, #5                  @ encoding: [0x05,0x05,0xcd,0xf9]
+@ CHECK: srsib	sp, #11                 @ encoding: [0x0b,0x05,0xcd,0xf9]
+@ CHECK: srsia	sp, #10                 @ encoding: [0x0a,0x05,0xcd,0xf8]
+@ CHECK: srsdb	sp, #9                  @ encoding: [0x09,0x05,0x4d,0xf9]
+@ CHECK: srsda	sp, #5                  @ encoding: [0x05,0x05,0x4d,0xf8]
 
-@ CHECK: srsda	sp!, #5                 @ encoding: [0x05,0x05,0x6d,0xf8]
-@ CHECK: srsdb	sp!, #5                 @ encoding: [0x05,0x05,0x6d,0xf9]
-@ CHECK: srsia	sp!, #5                 @ encoding: [0x05,0x05,0xed,0xf8]
 @ CHECK: srsib	sp!, #5                 @ encoding: [0x05,0x05,0xed,0xf9]
+@ CHECK: srsia	sp!, #5                 @ encoding: [0x05,0x05,0xed,0xf8]
+@ CHECK: srsdb	sp!, #5                 @ encoding: [0x05,0x05,0x6d,0xf9]
+@ CHECK: srsda	sp!, #5                 @ encoding: [0x05,0x05,0x6d,0xf8]
 
 @ CHECK: srsia	sp, #5                  @ encoding: [0x05,0x05,0xcd,0xf8]
 @ CHECK: srsia	sp!, #5                 @ encoding: [0x05,0x05,0xed,0xf8]
@@ -2154,14 +2166,14 @@ Lforward:
 @ CHECK: srsdb	sp!, #19                @ encoding: [0x13,0x05,0x6d,0xf9]
 @ CHECK: srsia	sp!, #2                 @ encoding: [0x02,0x05,0xed,0xf8]
 @ CHECK: srsib	sp!, #14                @ encoding: [0x0e,0x05,0xed,0xf9]
-@ CHECK: srsda	sp, #11                 @ encoding: [0x0b,0x05,0x4d,0xf8]
-@ CHECK: srsdb	sp, #10                 @ encoding: [0x0a,0x05,0x4d,0xf9]
-@ CHECK: srsia	sp, #9                  @ encoding: [0x09,0x05,0xcd,0xf8]
-@ CHECK: srsib	sp, #5                  @ encoding: [0x05,0x05,0xcd,0xf9]
-@ CHECK: srsda	sp!, #5                 @ encoding: [0x05,0x05,0x6d,0xf8]
-@ CHECK: srsdb	sp!, #5                 @ encoding: [0x05,0x05,0x6d,0xf9]
-@ CHECK: srsia	sp!, #5                 @ encoding: [0x05,0x05,0xed,0xf8]
+@ CHECK: srsib	sp, #11                 @ encoding: [0x0b,0x05,0xcd,0xf9]
+@ CHECK: srsia	sp, #10                 @ encoding: [0x0a,0x05,0xcd,0xf8]
+@ CHECK: srsdb	sp, #9                  @ encoding: [0x09,0x05,0x4d,0xf9]
+@ CHECK: srsda	sp, #5                  @ encoding: [0x05,0x05,0x4d,0xf8]
 @ CHECK: srsib	sp!, #5                 @ encoding: [0x05,0x05,0xed,0xf9]
+@ CHECK: srsia	sp!, #5                 @ encoding: [0x05,0x05,0xed,0xf8]
+@ CHECK: srsdb	sp!, #5                 @ encoding: [0x05,0x05,0x6d,0xf9]
+@ CHECK: srsda	sp!, #5                 @ encoding: [0x05,0x05,0x6d,0xf8]
 @ CHECK: srsia	sp, #5                  @ encoding: [0x05,0x05,0xcd,0xf8]
 @ CHECK: srsia	sp!, #5                 @ encoding: [0x05,0x05,0xed,0xf8]
 
@@ -2317,7 +2329,7 @@ Lforward:
         stmdb     r0!, {r1,r5,r7,sp}
 
 @ CHECK: stm	r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8]
-@ CHECK: stm	r3, {lr, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x40,0x83,0xe8]
+@ CHECK: stm	r3, {r1, r3, r4, r5, r6, lr} @ encoding: [0x7a,0x40,0x83,0xe8]
 @ CHECK: stmib	r4, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x84,0xe9]
 @ CHECK: stmda	r5, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x05,0xe8]
 @ CHECK: stmdb	r6, {r1, r3, r4, r5, r6, r8} @ encoding: [0x7a,0x01,0x06,0xe9]
diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s
index 22e21da..b48db9a 100644
--- a/test/MC/ARM/basic-thumb-instructions.s
+++ b/test/MC/ARM/basic-thumb-instructions.s
@@ -85,11 +85,15 @@ _func:
 @ ADR
 @------------------------------------------------------------------------------
         adr r2, _baz
-        adr	r2, #3
+        adr r5, #0
+        adr r2, #4
+        adr r3, #1020
 
 @ CHECK: adr	r2, _baz                @ encoding: [A,0xa2]
             @   fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10
-@ CHECK: adr	r2, #3                  @ encoding: [0x03,0xa2]
+@ CHECK: adr	r5, #0                  @ encoding: [0x00,0xa5]
+@ CHECK: adr	r2, #4                  @ encoding: [0x01,0xa2]
+@ CHECK: adr	r3, #1020               @ encoding: [0xff,0xa3]
 
 @------------------------------------------------------------------------------
 @ ASR (immediate)
diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s
index 98eb7f2..b5d3966 100644
--- a/test/MC/ARM/basic-thumb2-instructions.s
+++ b/test/MC/ARM/basic-thumb2-instructions.s
@@ -79,6 +79,7 @@ _func:
         add r0, r0, #32
         adds r2, r2, #56
         adds r2, #56
+        add r1, r7, #0xcbcbcbcb
 
         adds.w r2, #-16
         adds.w r2, r2, #-16
@@ -101,6 +102,7 @@ _func:
 @ CHECK: add.w	r0, r0, #32             @ encoding: [0x00,0xf1,0x20,0x00]
 @ CHECK: adds	r2, #56                 @ encoding: [0x38,0x32]
 @ CHECK: adds	r2, #56                 @ encoding: [0x38,0x32]
+@ CHECK: add.w  r1, r7, #3419130827     @ encoding: [0x07,0xf1,0xcb,0x31]
 
 @ CHECK: subs.w	r2, r2, #16             @ encoding: [0xb2,0xf1,0x10,0x02]
 @ CHECK: subs.w	r2, r2, #16             @ encoding: [0xb2,0xf1,0x10,0x02]
@@ -134,12 +136,14 @@ _func:
 @------------------------------------------------------------------------------
 
         subw r11, pc, #3270
+        adr.w r2, #3
         adr.w r11, #-826
         adr.w r1, #-0x0
 
-@ CHECK: subw	r11, pc, #3270          @ encoding: [0xaf,0xf6,0xc6,0x4b]
-@ CHECK: adr.w	r11, #-826              @ encoding: [0xaf,0xf2,0x3a,0x3b]
-@ CHECK: adr.w	r1, #-0                 @ encoding: [0xaf,0xf2,0x00,0x01]
+@ CHECK: subw  r11, pc, #3270          @ encoding: [0xaf,0xf6,0xc6,0x4b]
+@ CHECK: adr.w r2, #3                  @ encoding: [0x0f,0xf2,0x03,0x02]
+@ CHECK: adr.w r11, #-826              @ encoding: [0xaf,0xf2,0x3a,0x3b]
+@ CHECK: adr.w r1, #-0                 @ encoding: [0xaf,0xf2,0x00,0x01]
 
 @------------------------------------------------------------------------------
 @ AND (immediate)
@@ -708,7 +712,7 @@ _func:
 @ CHECK: ldm.w	r4, {r5, r6}            @ encoding: [0x94,0xe8,0x60,0x00]
 @ CHECK: ldm.w	r5!, {r3, r8}           @ encoding: [0xb5,0xe8,0x08,0x01]
 @ CHECK: ldm.w	r5!, {r3, r8}           @ encoding: [0xb5,0xe8,0x08,0x01]
-@ CHECK: pop.w	{pc, r4, r5, r6, r7, r8, r9, r10, r11} @ encoding: [0xbd,0xe8,0xf0,0x8f]
+@ CHECK: pop.w	{r4, r5, r6, r7, r8, r9, r10, r11, pc} @ encoding: [0xbd,0xe8,0xf0,0x8f]
 
 
 @------------------------------------------------------------------------------
@@ -768,6 +772,23 @@ _func:
 @ CHECK: ldr.w	lr, _strcmp-4           @ encoding: [0x5f'A',0xf8'A',A,0xe0'A']
 @ CHECK: @   fixup A - offset: 0, value: _strcmp-4, kind: fixup_t2_ldst_pcrel_12
 
+        ldr r4, [pc, #1020]
+        ldr r3, [pc, #-1020]
+        ldr r6, [pc, #1024]
+        ldr r0, [pc, #-1024]
+        ldr r2, [pc, #4095]
+        ldr r1, [pc, #-4095]
+        ldr.n r8, [pc, #132]
+        ldr.w r8, [pc, #132]
+
+@ CHECK: ldr	r4, [pc, #1020]       @ encoding: [0xff,0x4c]
+@ CHECK: ldr	r3, [pc, #-1020]      @ encoding: [0x01,0x4b]
+@ CHECK: ldr.w	r6, [pc, #1024]       @ encoding: [0xdf,0xf8,0x00,0x64]
+@ CHECK: ldr.w	r0, [pc, #-1024]      @ encoding: [0x5f,0xf8,0x00,0x04]
+@ CHECK: ldr.w	r2, [pc, #4095]       @ encoding: [0xdf,0xf8,0xff,0x2f]
+@ CHECK: ldr.w	r1, [pc, #-4095]      @ encoding: [0x5f,0xf8,0xff,0x1f]
+@ CHECK: ldr	r8, [pc, #132]        @ encoding: [0x21,0x48]
+@ CHECK: ldr.w	r8, [pc, #132]        @ encoding: [0xdf,0xf8,0x84,0x80]
 
 @------------------------------------------------------------------------------
 @ LDR(register)
@@ -1326,16 +1347,19 @@ _func:
 @ MRC/MRC2
 @------------------------------------------------------------------------------
         mrc  p14, #0, r1, c1, c2, #4
-        mrc2  p14, #0, r1, c1, c2, #4
-        mrc p11, #1, r1, c2, c2
+        mrc  p15, #7, apsr_nzcv, c15, c6, #6
+        mrc  p11, #1, r1, c2, c2
         mrc2 p12, #3, r3, c3, c4
-
-@ CHECK: mrc	p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xee,0x92,0x1e]
-@ CHECK: mrc2	p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xfe,0x92,0x1e]
-@ CHECK: mrc	p11, #1, r1, c2, c2, #0 @ encoding: [0x32,0xee,0x12,0x1b]
-@ CHECK: mrc2	p12, #3, r3, c3, c4, #0 @ encoding: [0x73,0xfe,0x14,0x3c]
-
-
+        mrc2 p14, #0, r1, c1, c2, #4
+        mrc2 p10, #7, apsr_nzcv, c15, c0, #1
+ 
+@ CHECK: mrc  p14, #0, r1, c1, c2, #4            @ encoding: [0x11,0xee,0x92,0x1e]
+@ CHECK: mrc  p15, #7, apsr_nzcv, c15, c6, #6    @ encoding: [0xff,0xee,0xd6,0xff]
+@ CHECK: mrc  p11, #1, r1, c2, c2, #0            @ encoding: [0x32,0xee,0x12,0x1b]
+@ CHECK: mrc2 p12, #3, r3, c3, c4, #0            @ encoding: [0x73,0xfe,0x14,0x3c]
+@ CHECK: mrc2 p14, #0, r1, c1, c2, #4            @ encoding: [0x11,0xfe,0x92,0x1e]
+@ CHECK: mrc2 p10, #7, apsr_nzcv, c15, c0, #1    @ encoding: [0xff,0xfe,0x30,0xfa]
+ 
 @------------------------------------------------------------------------------
 @ MRRC/MRRC2
 @------------------------------------------------------------------------------
@@ -1569,6 +1593,9 @@ _func:
 @ FIXME: pld	_foo                    @ encoding: [0x9f'A',0xf8'A',A,0xf0'A']
             @   fixup A - offset: 0, value: _foo, kind: fixup_t2_ldst_pcrel_12
 
+        pld [pc,#-4095]
+@ CHECK: pld [pc, #-4095]            @ encoding: [0x1f,0xf8,0xff,0xff]
+
 
 @------------------------------------------------------------------------------
 @ PLD(register)
@@ -1595,12 +1622,16 @@ _func:
         pli [r6, #33]
         pli [r6, #257]
         pli [r7, #257]
+        pli [pc, #+4095]
+        pli [pc, #-4095]
 
 @ CHECK: pli	[r5, #-4]               @ encoding: [0x15,0xf9,0x04,0xfc]
 @ CHECK: pli	[r6, #32]               @ encoding: [0x96,0xf9,0x20,0xf0]
 @ CHECK: pli	[r6, #33]               @ encoding: [0x96,0xf9,0x21,0xf0]
 @ CHECK: pli	[r6, #257]              @ encoding: [0x96,0xf9,0x01,0xf1]
 @ CHECK: pli	[r7, #257]              @ encoding: [0x97,0xf9,0x01,0xf1]
+@ CHECK: pli    [pc, #4095]             @ encoding: [0x9f,0xf9,0xff,0xff]
+@ CHECK: pli    [pc, #-4095]            @ encoding: [0x1f,0xf9,0xff,0xff]
 
 
 @------------------------------------------------------------------------------
@@ -2349,10 +2380,10 @@ _func:
 @ CHECK: srsia	sp, #0                  @ encoding: [0x8d,0xe9,0x00,0xc0]
 @ CHECK: srsdb	sp!, #19                @ encoding: [0x2d,0xe8,0x13,0xc0]
 @ CHECK: srsia	sp!, #2                 @ encoding: [0xad,0xe9,0x02,0xc0]
-@ CHECK: srsdb	sp, #10                 @ encoding: [0x0d,0xe8,0x0a,0xc0]
-@ CHECK: srsia	sp, #9                  @ encoding: [0x8d,0xe9,0x09,0xc0]
-@ CHECK: srsdb	sp!, #5                 @ encoding: [0x2d,0xe8,0x05,0xc0]
+@ CHECK: srsia	sp, #10                 @ encoding: [0x8d,0xe9,0x0a,0xc0]
+@ CHECK: srsdb	sp, #9                  @ encoding: [0x0d,0xe8,0x09,0xc0]
 @ CHECK: srsia	sp!, #5                 @ encoding: [0xad,0xe9,0x05,0xc0]
+@ CHECK: srsdb	sp!, #5                 @ encoding: [0x2d,0xe8,0x05,0xc0]
 @ CHECK: srsia	sp, #5                  @ encoding: [0x8d,0xe9,0x05,0xc0]
 @ CHECK: srsia	sp!, #5                 @ encoding: [0xad,0xe9,0x05,0xc0]
 
@@ -2375,10 +2406,10 @@ _func:
 @ CHECK: srsia	sp, #0                  @ encoding: [0x8d,0xe9,0x00,0xc0]
 @ CHECK: srsdb	sp!, #19                @ encoding: [0x2d,0xe8,0x13,0xc0]
 @ CHECK: srsia	sp!, #2                 @ encoding: [0xad,0xe9,0x02,0xc0]
-@ CHECK: srsdb	sp, #10                 @ encoding: [0x0d,0xe8,0x0a,0xc0]
-@ CHECK: srsia	sp, #9                  @ encoding: [0x8d,0xe9,0x09,0xc0]
-@ CHECK: srsdb	sp!, #5                 @ encoding: [0x2d,0xe8,0x05,0xc0]
+@ CHECK: srsia	sp, #10                 @ encoding: [0x8d,0xe9,0x0a,0xc0]
+@ CHECK: srsdb	sp, #9                  @ encoding: [0x0d,0xe8,0x09,0xc0]
 @ CHECK: srsia	sp!, #5                 @ encoding: [0xad,0xe9,0x05,0xc0]
+@ CHECK: srsdb	sp!, #5                 @ encoding: [0x2d,0xe8,0x05,0xc0]
 @ CHECK: srsia	sp, #5                  @ encoding: [0x8d,0xe9,0x05,0xc0]
 @ CHECK: srsia	sp!, #5                 @ encoding: [0xad,0xe9,0x05,0xc0]
 
@@ -2616,6 +2647,7 @@ _func:
         strb r9, [r2], #4
         strb r3, [sp], #-4
         strb r4, [r8, #-0]!
+        strb r1, [r0], #-0
 
 @ CHECK: strb	r5, [r5, #-4]           @ encoding: [0x05,0xf8,0x04,0x5c]
 @ CHECK: strb.w	r5, [r6, #32]           @ encoding: [0x86,0xf8,0x20,0x50]
@@ -2629,6 +2661,7 @@ _func:
 @ CHECK: strb	r9, [r2], #4            @ encoding: [0x02,0xf8,0x04,0x9b]
 @ CHECK: strb	r3, [sp], #-4           @ encoding: [0x0d,0xf8,0x04,0x39]
 @ CHECK: strb	r4, [r8, #-0]!          @ encoding: [0x08,0xf8,0x00,0x4d]
+@ CHECK: strb	r1, [r0], #-0           @ encoding: [0x00,0xf8,0x00,0x19]
 
 
 @------------------------------------------------------------------------------
@@ -3513,12 +3546,31 @@ _func:
 @------------------------------------------------------------------------------
 @ Alternate syntax for LDR*(literal) encodings
 @------------------------------------------------------------------------------
+        ldrb r11, [pc, #22]
+        ldrh r11, [pc, #22]
+        ldrsb r11, [pc, #22]
+        ldrsh r11, [pc, #22]
+        ldr.w r11, [pc, #22]
+        ldrb.w r11, [pc, #22]
+        ldrh.w r11, [pc, #22]
+        ldrsb.w r11, [pc, #22]
+        ldrsh.w r11, [pc, #22]
+
+@ CHECK: ldrb.w r11, [pc, #22]        @ encoding: [0x9f,0xf8,0x16,0xb0]
+@ CHECK: ldrh.w r11, [pc, #22]        @ encoding: [0xbf,0xf8,0x16,0xb0]
+@ CHECK: ldrsb.w r11, [pc, #22]       @ encoding: [0x9f,0xf9,0x16,0xb0]
+@ CHECK: ldrsh.w r11, [pc, #22]       @ encoding: [0xbf,0xf9,0x16,0xb0]
+@ CHECK: ldr.w r11, [pc, #22]         @ encoding: [0xdf,0xf8,0x16,0xb0]
+@ CHECK: ldrb.w r11, [pc, #22]        @ encoding: [0x9f,0xf8,0x16,0xb0]
+@ CHECK: ldrh.w r11, [pc, #22]        @ encoding: [0xbf,0xf8,0x16,0xb0]
+@ CHECK: ldrsb.w r11, [pc, #22]       @ encoding: [0x9f,0xf9,0x16,0xb0]
+@ CHECK: ldrsh.w r11, [pc, #22]       @ encoding: [0xbf,0xf9,0x16,0xb0]
+
         ldr r11, [pc, #-22]
         ldrb r11, [pc, #-22]
         ldrh r11, [pc, #-22]
         ldrsb r11, [pc, #-22]
         ldrsh r11, [pc, #-22]
-
         ldr.w r11, [pc, #-22]
         ldrb.w r11, [pc, #-22]
         ldrh.w r11, [pc, #-22]
@@ -3537,5 +3589,9 @@ _func:
 @ CHECK: ldrsh.w r11, [pc, #-22]        @ encoding: [0x3f,0xf9,0x16,0xb0]
 
 @ rdar://12596361
-        ldr r1, [pc, #12]
-@ CHECK: ldr.n r1, [pc, #12]        @ encoding: [0x03,0x49]
+         ldr r1, [pc, #12]
+@ CHECK: ldr r1, [pc, #12]              @ encoding: [0x03,0x49]
+
+@ rdar://14214063
+         subs pc, lr, #4
+@ CHECK: subs pc, lr, #4                @ encoding: [0xde,0xf3,0x04,0x8f]
diff --git a/test/MC/ARM/deprecated-v8.s b/test/MC/ARM/deprecated-v8.s
new file mode 100644
index 0000000..e509a35
--- /dev/null
+++ b/test/MC/ARM/deprecated-v8.s
@@ -0,0 +1,3 @@
+@ RUN: llvm-mc -triple armv8 -show-encoding < %s 2>&1 | FileCheck %s
+setend be
+@ CHECK: warning: deprecated on armv8
diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s
index b4b7386..1aea117 100644
--- a/test/MC/ARM/diagnostics.s
+++ b/test/MC/ARM/diagnostics.s
@@ -376,3 +376,34 @@
         isb #16
 @ CHECK-ERRORS: error: immediate value out of range
 @ CHECK-ERRORS: error: immediate value out of range
+
+        nop.n
+@ CHECK-ERRORS: error: instruction with .n (narrow) qualifier not allowed in arm mode
+
+	dmbeq #5
+	dsble #15
+	isblo #7
+@ CHECK-ERRORS: error: instruction 'dmb' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'dsb' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'isb' is not predicable, but condition code specified
+
+	dmblt
+	dsbne
+	isbeq
+@ CHECK-ERRORS: error: instruction 'dmb' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'dsb' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'isb' is not predicable, but condition code specified
+
+        mcr2le  p7, #1, r5, c1, c1, #4
+        mcrr2ne p7, #15, r5, r4, c1
+        mrc2lo  p14, #0, r1, c1, c2, #4
+        mrrc2lo  p7, #1, r5, r4, c1
+        cdp2hi   p10, #0, c6, c12, c0, #7
+@ CHECK-ERRORS: error: instruction 'mcr2' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'mcrr2' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'mrc2' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'mrrc2' is not predicable, but condition code specified
+@ CHECK-ERRORS: error: instruction 'cdp2' is not predicable, but condition code specified
+
+        bkpteq #7
+@ CHECK-ERRORS: error: instruction 'bkpt' is not predicable, but condition code specified
diff --git a/test/MC/ARM/eh-compact-pr1.s b/test/MC/ARM/eh-compact-pr1.s
index 41971d0..17d32f8 100644
--- a/test/MC/ARM/eh-compact-pr1.s
+++ b/test/MC/ARM/eh-compact-pr1.s
@@ -46,7 +46,7 @@ func1:
 @ 0xB0   = finish
 @-------------------------------------------------------------------------------
 @ CHECK:     SectionData (
-@ CHECK:       0000: 419B0181 B0B08384                    |A.......|
+@ CHECK:       0000: 419B0181 B0B08384 00000000           |A...........|
 @ CHECK:     )
 @ CHECK:   }
 
diff --git a/test/MC/ARM/eh-directive-cantunwind-diagnostics.s b/test/MC/ARM/eh-directive-cantunwind-diagnostics.s
index 5a6a46c..640cc30 100644
--- a/test/MC/ARM/eh-directive-cantunwind-diagnostics.s
+++ b/test/MC/ARM/eh-directive-cantunwind-diagnostics.s
@@ -8,99 +8,99 @@
 @ the conflicts.
 
 
-	.syntax unified
-	.text
+        .syntax unified
+        .text
 
 @-------------------------------------------------------------------------------
 @ TEST1: cantunwind + personality
 @-------------------------------------------------------------------------------
-	.globl	func1
-	.align	2
-	.type	func1,%function
-	.fnstart
+        .globl  func1
+        .align  2
+        .type   func1,%function
+        .fnstart
 func1:
-	.cantunwind
-	.personality	__gxx_personality_v0
+        .cantunwind
+        .personality    __gxx_personality_v0
 @ CHECK: error: .personality can't be used with .cantunwind directive
-@ CEHCK:        .personality __gxx_personality_v0
+@ CHECK:        .personality __gxx_personality_v0
 @ CHECK:        ^
 @ CHECK: error: .cantunwind was specified here
 @ CHECK:        .cantunwind
 @ CHECK:        ^
-	.fnend
+        .fnend
 
 
 
 @-------------------------------------------------------------------------------
 @ TEST2: cantunwind + handlerdata
 @-------------------------------------------------------------------------------
-	.globl	func2
-	.align	2
-	.type	func2,%function
-	.fnstart
+        .globl  func2
+        .align  2
+        .type   func2,%function
+        .fnstart
 func2:
-	.cantunwind
-	.handlerdata
+        .cantunwind
+        .handlerdata
 @ CHECK: error: .handlerdata can't be used with .cantunwind directive
-@ CEHCK:        .handlerdata
+@ CHECK:        .handlerdata
 @ CHECK:        ^
 @ CHECK: error: .cantunwind was specified here
 @ CHECK:        .cantunwind
 @ CHECK:        ^
-	.fnend
+        .fnend
 
 
 
 @-------------------------------------------------------------------------------
 @ TEST3: personality + cantunwind
 @-------------------------------------------------------------------------------
-	.globl	func3
-	.align	2
-	.type	func3,%function
-	.fnstart
+        .globl  func3
+        .align  2
+        .type   func3,%function
+        .fnstart
 func3:
-	.personality	__gxx_personality_v0
-	.cantunwind
+        .personality    __gxx_personality_v0
+        .cantunwind
 @ CHECK: error: .cantunwind can't be used with .personality directive
-@ CEHCK:        .cantunwind
+@ CHECK:        .cantunwind
 @ CHECK:        ^
 @ CHECK: error: .personality was specified here
 @ CHECK:        .personality __gxx_personality_v0
 @ CHECK:        ^
-	.fnend
+        .fnend
 
 
 
 @-------------------------------------------------------------------------------
 @ TEST4: handlerdata + cantunwind
 @-------------------------------------------------------------------------------
-	.globl	func4
-	.align	2
-	.type	func4,%function
-	.fnstart
+        .globl  func4
+        .align  2
+        .type   func4,%function
+        .fnstart
 func4:
-	.handlerdata
-	.cantunwind
+        .handlerdata
+        .cantunwind
 @ CHECK: error: .cantunwind can't be used with .handlerdata directive
-@ CEHCK:        .cantunwind
+@ CHECK:        .cantunwind
 @ CHECK:        ^
 @ CHECK: error: .handlerdata was specified here
 @ CHECK:        .handlerdata
 @ CHECK:        ^
-	.fnend
+        .fnend
 
 
 
 @-------------------------------------------------------------------------------
 @ TEST5: cantunwind + fnstart
 @-------------------------------------------------------------------------------
-	.globl	func5
-	.align	2
-	.type	func5,%function
-	.cantunwind
+        .globl  func5
+        .align  2
+        .type   func5,%function
+        .cantunwind
 @ CHECK: error: .fnstart must precede .cantunwind directive
 @ CHECK:        .cantunwind
 @ CHECK:        ^
-	.fnstart
+        .fnstart
 func5:
-	.fnend
+        .fnend
diff --git a/test/MC/ARM/eh-directive-fnend-diagnostics.s b/test/MC/ARM/eh-directive-fnend-diagnostics.s
index a5e4d3b..99161ee 100644
--- a/test/MC/ARM/eh-directive-fnend-diagnostics.s
+++ b/test/MC/ARM/eh-directive-fnend-diagnostics.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi \
+@ RUN: not llvm-mc %s -triple=armv7-unknown-linux-gnueabi \
 @ RUN:   -filetype=obj -o /dev/null 2>&1 | FileCheck %s
 
 @ Check the diagnostics for mismatched .fnend directive
diff --git a/test/MC/ARM/eh-directive-fnstart-diagnostics.s b/test/MC/ARM/eh-directive-fnstart-diagnostics.s
index 29bcb0d..75ddd9f 100644
--- a/test/MC/ARM/eh-directive-fnstart-diagnostics.s
+++ b/test/MC/ARM/eh-directive-fnstart-diagnostics.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi \
+@ RUN: not llvm-mc %s -triple=armv7-unknown-linux-gnueabi \
 @ RUN:   -filetype=obj -o /dev/null 2>&1 | FileCheck %s
 
 @ Check the diagnostics for the mismatched .fnstart directives.
diff --git a/test/MC/ARM/invalid-hint-arm.s b/test/MC/ARM/invalid-hint-arm.s
index e0cd97a..3608e95 100644
--- a/test/MC/ARM/invalid-hint-arm.s
+++ b/test/MC/ARM/invalid-hint-arm.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 < %s 2>&1 | FileCheck %s
+@ RUN: not llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 < %s 2>&1 | FileCheck %s
 
 hint #5
 hint #100
diff --git a/test/MC/ARM/invalid-hint-thumb.s b/test/MC/ARM/invalid-hint-thumb.s
index fd0a761..bde987c 100644
--- a/test/MC/ARM/invalid-hint-thumb.s
+++ b/test/MC/ARM/invalid-hint-thumb.s
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 < %s 2>&1 | FileCheck %s
+@ RUN: not llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 < %s 2>&1 | FileCheck %s
 
 hint #5
 hint.w #5
diff --git a/test/MC/ARM/invalid-v8fp.s b/test/MC/ARM/invalid-v8fp.s
new file mode 100644
index 0000000..4dff188
--- /dev/null
+++ b/test/MC/ARM/invalid-v8fp.s
@@ -0,0 +1,10 @@
+@ RUN: not llvm-mc -triple armv7 -show-encoding < %s | FileCheck %s
+
+@ VCVT{B,T}
+
+  vcvtt.f64.f16 d3, s1
+@ CHECK-NOT: vcvtt.f64.f16 d3, s1      @ encoding: [0xe0,0x3b,0xb2,0xee]
+  vcvtt.f16.f64 s5, d12
+@ CHECK-NOT: vcvtt.f16.f64 s5, d12     @ encoding: [0xcc,0x2b,0xf3,0xee]
+
+
diff --git a/test/MC/ARM/neon-mov-encoding.s b/test/MC/ARM/neon-mov-encoding.s
index 6f26a13..ba66d7e 100644
--- a/test/MC/ARM/neon-mov-encoding.s
+++ b/test/MC/ARM/neon-mov-encoding.s
@@ -128,3 +128,42 @@
 @ CHECK: vmov.8	d18[1], r1              @ encoding: [0xb0,0x1b,0x42,0xee]
 @ CHECK: vmov.16	d18[1], r1      @ encoding: [0xf0,0x1b,0x02,0xee]
 @ CHECK: vmov.32	d18[1], r1      @ encoding: [0x90,0x1b,0x22,0xee]
+
+
+        vmvn.8 d1, d2
+        vmvn.16 d1, d2
+        vmvn.32 d1, d2
+        vmvn.64 d1, d2
+        vmvn.i8 d1, d2
+        vmvn.i16 d1, d2
+        vmvn.i32 d1, d2
+        vmvn.i64 d1, d2
+        vmvn.s8 d1, d2
+        vmvn.s16 d1, d2
+        vmvn.s32 d1, d2
+        vmvn.s64 d1, d2
+        vmvn.u8 d1, d2
+        vmvn.u16 d1, d2
+        vmvn.u32 d1, d2
+        vmvn.u64 d1, d2
+        vmvn.f32 d1, d2
+        vmvn.f64 d1, d2
+
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
+@ CHECK: vmvn	d1, d2                  @ encoding: [0x82,0x15,0xb0,0xf3]
diff --git a/test/MC/ARM/neon-v8.s b/test/MC/ARM/neon-v8.s
new file mode 100644
index 0000000..429c8e3
--- /dev/null
+++ b/test/MC/ARM/neon-v8.s
@@ -0,0 +1,83 @@
+@ RUN: llvm-mc -triple armv8 -mattr=+neon -show-encoding < %s | FileCheck %s
+
+vmaxnm.f32 d4, d5, d1
+@ CHECK: vmaxnm.f32 d4, d5, d1 @ encoding: [0x11,0x4f,0x05,0xf3]
+vmaxnm.f32 q2, q4, q6
+@ CHECK: vmaxnm.f32 q2, q4, q6 @ encoding: [0x5c,0x4f,0x08,0xf3]
+vminnm.f32 d5, d4, d30
+@ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x3e,0x5f,0x24,0xf3]
+vminnm.f32 q0, q13, q2
+@ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0xd4,0x0f,0x2a,0xf3]
+
+vcvta.s32.f32	d4, d6
+@ CHECK: vcvta.s32.f32	d4, d6 @ encoding: [0x06,0x40,0xbb,0xf3]
+vcvta.u32.f32	d12, d10
+@ CHECK: vcvta.u32.f32	d12, d10 @ encoding: [0x8a,0xc0,0xbb,0xf3]
+vcvta.s32.f32	q4, q6
+@ CHECK: vcvta.s32.f32	q4, q6 @ encoding: [0x4c,0x80,0xbb,0xf3]
+vcvta.u32.f32	q4, q10
+@ CHECK: vcvta.u32.f32	q4, q10 @ encoding: [0xe4,0x80,0xbb,0xf3]
+
+vcvtm.s32.f32	d1, d30
+@ CHECK: vcvtm.s32.f32	d1, d30 @ encoding: [0x2e,0x13,0xbb,0xf3]
+vcvtm.u32.f32	d12, d10
+@ CHECK: vcvtm.u32.f32	d12, d10 @ encoding: [0x8a,0xc3,0xbb,0xf3]
+vcvtm.s32.f32	q1, q10
+@ CHECK: vcvtm.s32.f32	q1, q10 @ encoding: [0x64,0x23,0xbb,0xf3]
+vcvtm.u32.f32	q13, q1
+@ CHECK: vcvtm.u32.f32	q13, q1 @ encoding: [0xc2,0xa3,0xfb,0xf3]
+
+vcvtn.s32.f32	d15, d17
+@ CHECK: vcvtn.s32.f32	d15, d17 @ encoding: [0x21,0xf1,0xbb,0xf3]
+vcvtn.u32.f32	d5, d3
+@ CHECK: vcvtn.u32.f32	d5, d3 @ encoding: [0x83,0x51,0xbb,0xf3]
+vcvtn.s32.f32	q3, q8
+@ CHECK: vcvtn.s32.f32	q3, q8 @ encoding: [0x60,0x61,0xbb,0xf3]
+vcvtn.u32.f32	q5, q3
+@ CHECK: vcvtn.u32.f32	q5, q3 @ encoding: [0xc6,0xa1,0xbb,0xf3]
+
+vcvtp.s32.f32	d11, d21
+@ CHECK: vcvtp.s32.f32	d11, d21 @ encoding: [0x25,0xb2,0xbb,0xf3]
+vcvtp.u32.f32	d14, d23
+@ CHECK: vcvtp.u32.f32	d14, d23 @ encoding: [0xa7,0xe2,0xbb,0xf3]
+vcvtp.s32.f32	q4, q15
+@ CHECK: vcvtp.s32.f32	q4, q15 @ encoding: [0x6e,0x82,0xbb,0xf3]
+vcvtp.u32.f32	q9, q8
+@ CHECK: vcvtp.u32.f32	q9, q8 @ encoding: [0xe0,0x22,0xfb,0xf3]
+
+vrintn.f32 d3, d0
+@ CHECK: vrintn.f32 d3, d0 @ encoding: [0x00,0x34,0xba,0xf3]
+vrintn.f32 q1, q4
+@ CHECK: vrintn.f32 q1, q4 @ encoding: [0x48,0x24,0xba,0xf3]
+vrintx.f32 d5, d12
+@ CHECK: vrintx.f32 d5, d12 @ encoding: [0x8c,0x54,0xba,0xf3]
+vrintx.f32 q0, q3
+@ CHECK: vrintx.f32 q0, q3 @ encoding: [0xc6,0x04,0xba,0xf3]
+vrinta.f32 d3, d0
+@ CHECK: vrinta.f32 d3, d0 @ encoding: [0x00,0x35,0xba,0xf3]
+vrinta.f32 q8, q2
+@ CHECK: vrinta.f32 q8, q2 @ encoding: [0x44,0x05,0xfa,0xf3]
+vrintz.f32 d12, d18
+@ CHECK: vrintz.f32 d12, d18 @ encoding: [0xa2,0xc5,0xba,0xf3]
+vrintz.f32 q9, q4
+@ CHECK: vrintz.f32 q9, q4 @ encoding: [0xc8,0x25,0xfa,0xf3]
+vrintm.f32 d3, d0
+@ CHECK: vrintm.f32 d3, d0 @ encoding: [0x80,0x36,0xba,0xf3]
+vrintm.f32 q1, q4
+@ CHECK: vrintm.f32 q1, q4 @ encoding: [0xc8,0x26,0xba,0xf3]
+vrintp.f32 d3, d0
+@ CHECK: vrintp.f32 d3, d0 @ encoding: [0x80,0x37,0xba,0xf3]
+vrintp.f32 q1, q4
+@ CHECK: vrintp.f32 q1, q4 @ encoding: [0xc8,0x27,0xba,0xf3]
+
+@ test the aliases of vrint
+vrintn.f32.f32 d3, d0
+@ CHECK: vrintn.f32 d3, d0 @ encoding: [0x00,0x34,0xba,0xf3]
+vrintx.f32.f32 q0, q3
+@ CHECK: vrintx.f32 q0, q3 @ encoding: [0xc6,0x04,0xba,0xf3]
+vrinta.f32.f32 d3, d0
+@ CHECK: vrinta.f32 d3, d0 @ encoding: [0x00,0x35,0xba,0xf3]
+vrintz.f32.f32 q9, q4
+@ CHECK: vrintz.f32 q9, q4 @ encoding: [0xc8,0x25,0xfa,0xf3]
+vrintp.f32.f32 q1, q4
+@ CHECK: vrintp.f32 q1, q4 @ encoding: [0xc8,0x27,0xba,0xf3]
diff --git a/test/MC/ARM/neon-vst-encoding.s b/test/MC/ARM/neon-vst-encoding.s
index ef9f037..3c7e34e 100644
--- a/test/MC/ARM/neon-vst-encoding.s
+++ b/test/MC/ARM/neon-vst-encoding.s
@@ -282,4 +282,4 @@
         vst2.16	{d16, d17}, [r0, :128]
 
 @ CHECK: vst2.8	{d16, d17}, [r0:64]   @ encoding: [0x1f,0x08,0x40,0xf4]
-@ CHECK: vst2.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x08,0x40,0xf4]
\ No newline at end of file
+@ CHECK: vst2.16 {d16, d17}, [r0:128] @ encoding: [0x6f,0x08,0x40,0xf4]
diff --git a/test/MC/ARM/thumb-diagnostics.s b/test/MC/ARM/thumb-diagnostics.s
index 6f822d1..a194ab4 100644
--- a/test/MC/ARM/thumb-diagnostics.s
+++ b/test/MC/ARM/thumb-diagnostics.s
@@ -156,3 +156,8 @@ error: invalid operand for instruction
 @ CHECK-ERRORS: yield
 @ CHECK-ERRORS: ^
 
+@------------------------------------------------------------------------------
+@ PLDW required mp-extensions
+@------------------------------------------------------------------------------
+        pldw [r0, #4]
+@ CHECK-ERRORS: error: instruction requires: mp-extensions
diff --git a/test/MC/ARM/thumb-neon-v8.s b/test/MC/ARM/thumb-neon-v8.s
new file mode 100644
index 0000000..5b32781
--- /dev/null
+++ b/test/MC/ARM/thumb-neon-v8.s
@@ -0,0 +1,83 @@
+@ RUN: llvm-mc -triple thumbv8 -mattr=+neon -show-encoding < %s | FileCheck %s
+
+vmaxnm.f32 d4, d5, d1
+@ CHECK: vmaxnm.f32 d4, d5, d1 @ encoding: [0x05,0xff,0x11,0x4f]
+vmaxnm.f32 q2, q4, q6
+@ CHECK: vmaxnm.f32 q2, q4, q6 @ encoding: [0x08,0xff,0x5c,0x4f]
+vminnm.f32 d5, d4, d30
+@ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x24,0xff,0x3e,0x5f]
+vminnm.f32 q0, q13, q2
+@ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0x2a,0xff,0xd4,0x0f]
+
+vcvta.s32.f32	d4, d6
+@ CHECK: vcvta.s32.f32	d4, d6 @ encoding: [0xbb,0xff,0x06,0x40]
+vcvta.u32.f32	d12, d10
+@ CHECK: vcvta.u32.f32	d12, d10 @ encoding: [0xbb,0xff,0x8a,0xc0]
+vcvta.s32.f32	q4, q6
+@ CHECK: vcvta.s32.f32	q4, q6 @ encoding: [0xbb,0xff,0x4c,0x80]
+vcvta.u32.f32	q4, q10
+@ CHECK: vcvta.u32.f32	q4, q10 @ encoding: [0xbb,0xff,0xe4,0x80]
+
+vcvtm.s32.f32	d1, d30
+@ CHECK: vcvtm.s32.f32	d1, d30 @ encoding: [0xbb,0xff,0x2e,0x13]
+vcvtm.u32.f32	d12, d10
+@ CHECK: vcvtm.u32.f32	d12, d10 @ encoding: [0xbb,0xff,0x8a,0xc3]
+vcvtm.s32.f32	q1, q10
+@ CHECK: vcvtm.s32.f32	q1, q10 @ encoding: [0xbb,0xff,0x64,0x23]
+vcvtm.u32.f32	q13, q1
+@ CHECK: vcvtm.u32.f32	q13, q1 @ encoding: [0xfb,0xff,0xc2,0xa3]
+
+vcvtn.s32.f32	d15, d17
+@ CHECK: vcvtn.s32.f32	d15, d17 @ encoding: [0xbb,0xff,0x21,0xf1]
+vcvtn.u32.f32	d5, d3
+@ CHECK: vcvtn.u32.f32	d5, d3 @ encoding: [0xbb,0xff,0x83,0x51]
+vcvtn.s32.f32	q3, q8
+@ CHECK: vcvtn.s32.f32	q3, q8 @ encoding: [0xbb,0xff,0x60,0x61]
+vcvtn.u32.f32	q5, q3
+@ CHECK: vcvtn.u32.f32	q5, q3 @ encoding: [0xbb,0xff,0xc6,0xa1]
+
+vcvtp.s32.f32	d11, d21
+@ CHECK: vcvtp.s32.f32	d11, d21 @ encoding: [0xbb,0xff,0x25,0xb2]
+vcvtp.u32.f32	d14, d23
+@ CHECK: vcvtp.u32.f32	d14, d23 @ encoding: [0xbb,0xff,0xa7,0xe2]
+vcvtp.s32.f32	q4, q15
+@ CHECK: vcvtp.s32.f32	q4, q15 @ encoding: [0xbb,0xff,0x6e,0x82]
+vcvtp.u32.f32	q9, q8
+@ CHECK: vcvtp.u32.f32	q9, q8 @ encoding: [0xfb,0xff,0xe0,0x22]
+
+vrintn.f32 d3, d0
+@ CHECK: vrintn.f32 d3, d0 @ encoding: [0xba,0xff,0x00,0x34]
+vrintn.f32 q1, q4
+@ CHECK: vrintn.f32 q1, q4 @ encoding: [0xba,0xff,0x48,0x24]
+vrintx.f32 d5, d12
+@ CHECK: vrintx.f32 d5, d12 @ encoding: [0xba,0xff,0x8c,0x54]
+vrintx.f32 q0, q3
+@ CHECK: vrintx.f32 q0, q3 @ encoding: [0xba,0xff,0xc6,0x04]
+vrinta.f32 d3, d0
+@ CHECK: vrinta.f32 d3, d0 @ encoding: [0xba,0xff,0x00,0x35]
+vrinta.f32 q8, q2
+@ CHECK: vrinta.f32 q8, q2 @ encoding: [0xfa,0xff,0x44,0x05]
+vrintz.f32 d12, d18
+@ CHECK: vrintz.f32 d12, d18 @ encoding: [0xba,0xff,0xa2,0xc5]
+vrintz.f32 q9, q4
+@ CHECK: vrintz.f32 q9, q4 @ encoding: [0xfa,0xff,0xc8,0x25]
+vrintm.f32 d3, d0
+@ CHECK: vrintm.f32 d3, d0 @ encoding: [0xba,0xff,0x80,0x36]
+vrintm.f32 q1, q4
+@ CHECK: vrintm.f32 q1, q4 @ encoding: [0xba,0xff,0xc8,0x26]
+vrintp.f32 d3, d0
+@ CHECK: vrintp.f32 d3, d0 @ encoding: [0xba,0xff,0x80,0x37]
+vrintp.f32 q1, q4
+@ CHECK: vrintp.f32 q1, q4 @ encoding: [0xba,0xff,0xc8,0x27]
+
+@ test the aliases of vrint
+vrintn.f32.f32 d3, d0
+@ CHECK: vrintn.f32 d3, d0 @ encoding: [0xba,0xff,0x00,0x34]
+vrintx.f32.f32 q0, q3
+@ CHECK: vrintx.f32 q0, q3 @ encoding: [0xba,0xff,0xc6,0x04]
+vrinta.f32.f32 d3, d0
+@ CHECK: vrinta.f32 d3, d0 @ encoding: [0xba,0xff,0x00,0x35]
+vrintz.f32.f32 q9, q4
+@ CHECK: vrintz.f32 q9, q4 @ encoding: [0xfa,0xff,0xc8,0x25]
+vrintp.f32.f32 q1, q4
+@ CHECK: vrintp.f32 q1, q4 @ encoding: [0xba,0xff,0xc8,0x27]
diff --git a/test/MC/ARM/thumb-nop.s b/test/MC/ARM/thumb-nop.s
index 0b580ea..66f61a6 100644
--- a/test/MC/ARM/thumb-nop.s
+++ b/test/MC/ARM/thumb-nop.s
@@ -5,5 +5,5 @@
 
         nop
 
-@ CHECK-V6: nop                            @ encoding: [0xc0,0x46]
+@ CHECK-V6: mov r8, r8                     @ encoding: [0xc0,0x46]
 @ CHECK-V7: nop                            @ encoding: [0x00,0xbf]
diff --git a/test/MC/ARM/thumb-only-conditionals.s b/test/MC/ARM/thumb-only-conditionals.s
new file mode 100644
index 0000000..6d13ce5
--- /dev/null
+++ b/test/MC/ARM/thumb-only-conditionals.s
@@ -0,0 +1,54 @@
+@ RUN: llvm-mc -triple=thumbv7-apple-ios -o - %s | FileCheck %s
+
+        itte eq
+        dmbeq #11
+        dsbeq #7
+        isbne #15
+@ CHECK: itte eq
+@ CHECK-NEXT: dmbeq ish
+@ CHECK-NEXT: dsbeq nsh
+@ CHECK-NEXT: isbne sy
+
+        itet le
+        dmble
+        dsbgt
+        isble
+@ CHECK: itet le
+@ CHECK-NEXT: dmble sy
+@ CHECK-NEXT: dsbgt sy
+@ CHECK-NEXT: isble sy
+
+        itt gt
+        cdpgt  p7, #1, c1, c1, c1, #4
+        cdp2gt  p7, #1, c1, c1, c1, #4
+@ CHECK: itt gt
+@ CHECK-NEXT: cdpgt  p7, #1, c1, c1, c1, #4
+@ CHECK-NEXT: cdp2gt  p7, #1, c1, c1, c1, #4
+
+        itt ne
+        mcrne p0, #0, r0, c0, c0, #0
+        mcr2ne p0, #0, r0, c0, c0, #0
+@ CHECK: itt ne
+@ CHECK-NEXT: mcrne p0, #0, r0, c0, c0, #0
+@ CHECK-NEXT: mcr2ne p0, #0, r0, c0, c0, #0
+
+        ite le
+        mcrrle  p7, #15, r5, r4, c1
+        mcrr2gt  p7, #15, r5, r4, c1
+@ CHECK: ite le
+@ CHECK-NEXT: mcrrle  p7, #15, r5, r4, c1
+@ CHECK-NEXT: mcrr2gt  p7, #15, r5, r4, c1
+
+        ite eq
+        mrceq p11, #1, r1, c2, c2
+        mrc2ne p12, #3, r3, c3, c4
+@ CHECK: ite eq
+@ CHECK-NEXT: mrceq p11, #1, r1, c2, c2
+@ CHECK-NEXT: mrc2ne p12, #3, r3, c3, c4
+
+        itt lo
+        mrrclo  p7, #1, r5, r4, c1
+        mrrc2lo  p7, #1, r5, r4, c1
+@ CHECK: itt lo
+@ CHECK-NEXT: mrrclo  p7, #1, r5, r4, c1
+@ CHECK-NEXT: mrrc2lo  p7, #1, r5, r4, c1
diff --git a/test/MC/ARM/thumb-v8fp.s b/test/MC/ARM/thumb-v8fp.s
new file mode 100644
index 0000000..50cd005
--- /dev/null
+++ b/test/MC/ARM/thumb-v8fp.s
@@ -0,0 +1,130 @@
+@ RUN: llvm-mc -triple thumbv8 -mattr=+v8fp -show-encoding < %s | FileCheck %s
+
+@ VCVT{B,T}
+
+  vcvtt.f64.f16 d3, s1
+@ CHECK: vcvtt.f64.f16 d3, s1      @ encoding: [0xb2,0xee,0xe0,0x3b]
+  vcvtt.f16.f64 s5, d12
+@ CHECK: vcvtt.f16.f64 s5, d12     @ encoding: [0xf3,0xee,0xcc,0x2b]
+
+  vcvtb.f64.f16 d3, s1
+@ CHECK: vcvtb.f64.f16 d3, s1     @ encoding: [0xb2,0xee,0x60,0x3b]
+  vcvtb.f16.f64 s4, d1
+@ CHECK: vcvtb.f16.f64 s4, d1     @ encoding: [0xb3,0xee,0x41,0x2b]
+
+  it ge
+  vcvttge.f64.f16 d3, s1
+@ CHECK: vcvttge.f64.f16 d3, s1      @ encoding: [0xb2,0xee,0xe0,0x3b]
+  it gt
+  vcvttgt.f16.f64 s5, d12
+@ CHECK: vcvttgt.f16.f64 s5, d12     @ encoding: [0xf3,0xee,0xcc,0x2b]
+  it eq
+  vcvtbeq.f64.f16 d3, s1
+@ CHECK: vcvtbeq.f64.f16 d3, s1     @ encoding: [0xb2,0xee,0x60,0x3b]
+  it lt
+  vcvtblt.f16.f64 s4, d1
+@ CHECK: vcvtblt.f16.f64 s4, d1     @ encoding: [0xb3,0xee,0x41,0x2b]
+
+
+@ VCVT{A,N,P,M}
+
+  vcvta.s32.f32 s2, s3
+@ CHECK: vcvta.s32.f32 s2, s3     @ encoding: [0xbc,0xfe,0xe1,0x1a]
+  vcvta.s32.f64 s2, d3
+@ CHECK: vcvta.s32.f64 s2, d3     @ encoding: [0xbc,0xfe,0xc3,0x1b]
+  vcvtn.s32.f32 s6, s23
+@ CHECK: vcvtn.s32.f32 s6, s23     @ encoding: [0xbd,0xfe,0xeb,0x3a]
+  vcvtn.s32.f64 s6, d23
+@ CHECK: vcvtn.s32.f64 s6, d23     @ encoding: [0xbd,0xfe,0xe7,0x3b]
+  vcvtp.s32.f32 s0, s4
+@ CHECK: vcvtp.s32.f32 s0, s4     @ encoding: [0xbe,0xfe,0xc2,0x0a]
+  vcvtp.s32.f64 s0, d4
+@ CHECK: vcvtp.s32.f64 s0, d4     @ encoding: [0xbe,0xfe,0xc4,0x0b]
+  vcvtm.s32.f32 s17, s8
+@ CHECK: vcvtm.s32.f32 s17, s8     @ encoding: [0xff,0xfe,0xc4,0x8a]
+  vcvtm.s32.f64 s17, d8
+@ CHECK: vcvtm.s32.f64 s17, d8     @ encoding: [0xff,0xfe,0xc8,0x8b]
+
+  vcvta.u32.f32 s2, s3
+@ CHECK: vcvta.u32.f32 s2, s3     @ encoding: [0xbc,0xfe,0x61,0x1a]
+  vcvta.u32.f64 s2, d3
+@ CHECK: vcvta.u32.f64 s2, d3     @ encoding: [0xbc,0xfe,0x43,0x1b]
+  vcvtn.u32.f32 s6, s23
+@ CHECK: vcvtn.u32.f32 s6, s23     @ encoding: [0xbd,0xfe,0x6b,0x3a]
+  vcvtn.u32.f64 s6, d23
+@ CHECK: vcvtn.u32.f64 s6, d23     @ encoding: [0xbd,0xfe,0x67,0x3b]
+  vcvtp.u32.f32 s0, s4
+@ CHECK: vcvtp.u32.f32 s0, s4     @ encoding: [0xbe,0xfe,0x42,0x0a]
+  vcvtp.u32.f64 s0, d4
+@ CHECK: vcvtp.u32.f64 s0, d4     @ encoding: [0xbe,0xfe,0x44,0x0b]
+  vcvtm.u32.f32 s17, s8
+@ CHECK: vcvtm.u32.f32 s17, s8     @ encoding: [0xff,0xfe,0x44,0x8a]
+  vcvtm.u32.f64 s17, d8
+@ CHECK: vcvtm.u32.f64 s17, d8     @ encoding: [0xff,0xfe,0x48,0x8b]
+
+
+@ VSEL
+  vselge.f32 s4, s1, s23
+@ CHECK: vselge.f32 s4, s1, s23    @ encoding: [0x20,0xfe,0xab,0x2a]
+  vselge.f64 d30, d31, d23
+@ CHECK: vselge.f64 d30, d31, d23  @ encoding: [0x6f,0xfe,0xa7,0xeb]
+  vselgt.f32 s0, s1, s0
+@ CHECK: vselgt.f32 s0, s1, s0    @ encoding: [0x30,0xfe,0x80,0x0a]
+  vselgt.f64 d5, d10, d20
+@ CHECK: vselgt.f64 d5, d10, d20  @ encoding: [0x3a,0xfe,0x24,0x5b]
+  vseleq.f32 s30, s28, s23
+@ CHECK: vseleq.f32 s30, s28, s23 @ encoding: [0x0e,0xfe,0x2b,0xfa]
+  vseleq.f64 d2, d4, d8
+@ CHECK: vseleq.f64 d2, d4, d8    @ encoding: [0x04,0xfe,0x08,0x2b]
+  vselvs.f32 s21, s16, s14
+@ CHECK: vselvs.f32 s21, s16, s14 @ encoding: [0x58,0xfe,0x07,0xaa]
+  vselvs.f64 d0, d1, d31
+@ CHECK: vselvs.f64 d0, d1, d31   @ encoding: [0x11,0xfe,0x2f,0x0b]
+
+
+@ VMAXNM / VMINNM
+  vmaxnm.f32 s5, s12, s0
+@ CHECK: vmaxnm.f32 s5, s12, s0    @ encoding: [0xc6,0xfe,0x00,0x2a]
+  vmaxnm.f64 d5, d22, d30
+@ CHECK: vmaxnm.f64 d5, d22, d30   @ encoding: [0x86,0xfe,0xae,0x5b]
+  vminnm.f32 s0, s0, s12
+@ CHECK: vminnm.f32 s0, s0, s12    @ encoding: [0x80,0xfe,0x46,0x0a]
+  vminnm.f64 d4, d6, d9
+@ CHECK: vminnm.f64 d4, d6, d9     @ encoding: [0x86,0xfe,0x49,0x4b]
+
+@ VRINT{Z,R,X}
+  it ge
+  vrintzge.f64 d3, d12
+@ CHECK: vrintzge.f64 d3, d12   @ encoding: [0xb6,0xee,0xcc,0x3b]
+  vrintz.f32 s3, s24
+@ CHECK: vrintz.f32 s3, s24     @ encoding: [0xf6,0xee,0xcc,0x1a]
+  it lt
+  vrintrlt.f64 d5, d0
+@ CHECK: vrintrlt.f64 d5, d0    @ encoding: [0xb6,0xee,0x40,0x5b]
+  vrintr.f32 s0, s9
+@ CHECK: vrintr.f32 s0, s9      @ encoding: [0xb6,0xee,0x64,0x0a]
+  it eq
+  vrintxeq.f64 d28, d30
+@ CHECK: vrintxeq.f64 d28, d30  @ encoding: [0xf7,0xee,0x6e,0xcb]
+  it vs
+  vrintxvs.f32 s10, s14
+@ CHECK: vrintxvs.f32 s10, s14  @ encoding: [0xb7,0xee,0x47,0x5a]
+
+@ VRINT{A,N,P,M}
+
+  vrinta.f64 d3, d4
+@ CHECK: vrinta.f64 d3, d4     @ encoding: [0xb8,0xfe,0x44,0x3b]
+  vrinta.f32 s12, s1
+@ CHECK: vrinta.f32 s12, s1    @ encoding: [0xb8,0xfe,0x60,0x6a]
+  vrintn.f64 d3, d4
+@ CHECK: vrintn.f64 d3, d4     @ encoding: [0xb9,0xfe,0x44,0x3b]
+  vrintn.f32 s12, s1
+@ CHECK: vrintn.f32 s12, s1    @ encoding: [0xb9,0xfe,0x60,0x6a]
+  vrintp.f64 d3, d4
+@ CHECK: vrintp.f64 d3, d4     @ encoding: [0xba,0xfe,0x44,0x3b]
+  vrintp.f32 s12, s1
+@ CHECK: vrintp.f32 s12, s1    @ encoding: [0xba,0xfe,0x60,0x6a]
+  vrintm.f64 d3, d4
+@ CHECK: vrintm.f64 d3, d4     @ encoding: [0xbb,0xfe,0x44,0x3b]
+  vrintm.f32 s12, s1
+@ CHECK: vrintm.f32 s12, s1    @ encoding: [0xbb,0xfe,0x60,0x6a]
diff --git a/test/MC/ARM/thumb.s b/test/MC/ARM/thumb.s
index 2223bdc..9a72541 100644
--- a/test/MC/ARM/thumb.s
+++ b/test/MC/ARM/thumb.s
@@ -42,7 +42,7 @@
 @ CHECK: bkpt  #2                       @ encoding: [0x02,0xbe]
 
         nop
-@ CHECK: nop @ encoding: [0xc0,0x46]
+@ CHECK: mov r8, r8 @ encoding: [0xc0,0x46]
 
         cpsie aif
 @ CHECK: cpsie aif                      @ encoding: [0x67,0xb6]
diff --git a/test/MC/ARM/thumb2-diagnostics.s b/test/MC/ARM/thumb2-diagnostics.s
index b7fe44d..e1c0058 100644
--- a/test/MC/ARM/thumb2-diagnostics.s
+++ b/test/MC/ARM/thumb2-diagnostics.s
@@ -47,3 +47,7 @@
         isb  #16
 @ CHECK-ERRORS: error: immediate value out of range
 @ CHECK-ERRORS: error: immediate value out of range
+
+        itt eq
+        bkpteq #1
+@ CHECK-ERRORS: error: instruction 'bkpt' is not predicable, but condition code specified
diff --git a/test/MC/ARM/thumb2-pldw.s b/test/MC/ARM/thumb2-pldw.s
new file mode 100644
index 0000000..f0eeaf9
--- /dev/null
+++ b/test/MC/ARM/thumb2-pldw.s
@@ -0,0 +1,7 @@
+@ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -mattr=+mp -show-encoding < %s | FileCheck %s
+
+@------------------------------------------------------------------------------
+@ PLD(literal)
+@------------------------------------------------------------------------------
+         pldw   [r0, #257]
+@ CHECK: pldw   [r0, #257]              @ encoding: [0xb0,0xf8,0x01,0xf1]
diff --git a/test/MC/ARM/v8fp.s b/test/MC/ARM/v8fp.s
new file mode 100644
index 0000000..b12d7e2
--- /dev/null
+++ b/test/MC/ARM/v8fp.s
@@ -0,0 +1,124 @@
+@ RUN: llvm-mc -triple armv8 -mattr=+v8fp -show-encoding < %s | FileCheck %s
+
+@ VCVT{B,T}
+
+  vcvtt.f64.f16 d3, s1
+@ CHECK: vcvtt.f64.f16 d3, s1      @ encoding: [0xe0,0x3b,0xb2,0xee]
+  vcvtt.f16.f64 s5, d12
+@ CHECK: vcvtt.f16.f64 s5, d12     @ encoding: [0xcc,0x2b,0xf3,0xee]
+
+  vcvtb.f64.f16 d3, s1
+@ CHECK: vcvtb.f64.f16 d3, s1     @ encoding: [0x60,0x3b,0xb2,0xee]
+  vcvtb.f16.f64 s4, d1
+@ CHECK: vcvtb.f16.f64 s4, d1     @ encoding: [0x41,0x2b,0xb3,0xee]
+
+  vcvttge.f64.f16 d3, s1
+@ CHECK: vcvttge.f64.f16 d3, s1      @ encoding: [0xe0,0x3b,0xb2,0xae]
+  vcvttgt.f16.f64 s5, d12
+@ CHECK: vcvttgt.f16.f64 s5, d12     @ encoding: [0xcc,0x2b,0xf3,0xce]
+
+  vcvtbeq.f64.f16 d3, s1
+@ CHECK: vcvtbeq.f64.f16 d3, s1     @ encoding: [0x60,0x3b,0xb2,0x0e]
+  vcvtblt.f16.f64 s4, d1
+@ CHECK: vcvtblt.f16.f64 s4, d1     @ encoding: [0x41,0x2b,0xb3,0xbe]
+
+
+@ VCVT{A,N,P,M}
+
+  vcvta.s32.f32 s2, s3
+@ CHECK: vcvta.s32.f32 s2, s3     @ encoding: [0xe1,0x1a,0xbc,0xfe]
+  vcvta.s32.f64 s2, d3
+@ CHECK: vcvta.s32.f64 s2, d3     @ encoding: [0xc3,0x1b,0xbc,0xfe]
+  vcvtn.s32.f32 s6, s23
+@ CHECK: vcvtn.s32.f32 s6, s23     @ encoding: [0xeb,0x3a,0xbd,0xfe]
+  vcvtn.s32.f64 s6, d23
+@ CHECK: vcvtn.s32.f64 s6, d23     @ encoding: [0xe7,0x3b,0xbd,0xfe]
+  vcvtp.s32.f32 s0, s4
+@ CHECK: vcvtp.s32.f32 s0, s4     @ encoding: [0xc2,0x0a,0xbe,0xfe]
+  vcvtp.s32.f64 s0, d4
+@ CHECK: vcvtp.s32.f64 s0, d4     @ encoding: [0xc4,0x0b,0xbe,0xfe]
+  vcvtm.s32.f32 s17, s8
+@ CHECK: vcvtm.s32.f32 s17, s8     @ encoding: [0xc4,0x8a,0xff,0xfe]
+  vcvtm.s32.f64 s17, d8
+@ CHECK: vcvtm.s32.f64 s17, d8     @ encoding: [0xc8,0x8b,0xff,0xfe]
+
+  vcvta.u32.f32 s2, s3
+@ CHECK: vcvta.u32.f32 s2, s3     @ encoding: [0x61,0x1a,0xbc,0xfe]
+  vcvta.u32.f64 s2, d3
+@ CHECK: vcvta.u32.f64 s2, d3     @ encoding: [0x43,0x1b,0xbc,0xfe]
+  vcvtn.u32.f32 s6, s23
+@ CHECK: vcvtn.u32.f32 s6, s23     @ encoding: [0x6b,0x3a,0xbd,0xfe]
+  vcvtn.u32.f64 s6, d23
+@ CHECK: vcvtn.u32.f64 s6, d23     @ encoding: [0x67,0x3b,0xbd,0xfe]
+  vcvtp.u32.f32 s0, s4
+@ CHECK: vcvtp.u32.f32 s0, s4     @ encoding: [0x42,0x0a,0xbe,0xfe]
+  vcvtp.u32.f64 s0, d4
+@ CHECK: vcvtp.u32.f64 s0, d4     @ encoding: [0x44,0x0b,0xbe,0xfe]
+  vcvtm.u32.f32 s17, s8
+@ CHECK: vcvtm.u32.f32 s17, s8     @ encoding: [0x44,0x8a,0xff,0xfe]
+  vcvtm.u32.f64 s17, d8
+@ CHECK: vcvtm.u32.f64 s17, d8     @ encoding: [0x48,0x8b,0xff,0xfe]
+
+
+@ VSEL
+  vselge.f32 s4, s1, s23
+@ CHECK: vselge.f32 s4, s1, s23    @ encoding: [0xab,0x2a,0x20,0xfe]
+  vselge.f64 d30, d31, d23
+@ CHECK: vselge.f64 d30, d31, d23  @ encoding: [0xa7,0xeb,0x6f,0xfe]
+  vselgt.f32 s0, s1, s0
+@ CHECK: vselgt.f32 s0, s1, s0    @ encoding: [0x80,0x0a,0x30,0xfe]
+  vselgt.f64 d5, d10, d20
+@ CHECK: vselgt.f64 d5, d10, d20  @ encoding: [0x24,0x5b,0x3a,0xfe]
+  vseleq.f32 s30, s28, s23
+@ CHECK: vseleq.f32 s30, s28, s23 @ encoding: [0x2b,0xfa,0x0e,0xfe]
+  vseleq.f64 d2, d4, d8
+@ CHECK: vseleq.f64 d2, d4, d8    @ encoding: [0x08,0x2b,0x04,0xfe]
+  vselvs.f32 s21, s16, s14
+@ CHECK: vselvs.f32 s21, s16, s14 @ encoding: [0x07,0xaa,0x58,0xfe]
+  vselvs.f64 d0, d1, d31
+@ CHECK: vselvs.f64 d0, d1, d31   @ encoding: [0x2f,0x0b,0x11,0xfe]
+
+
+@ VMAXNM / VMINNM
+  vmaxnm.f32 s5, s12, s0
+@ CHECK: vmaxnm.f32 s5, s12, s0    @ encoding: [0x00,0x2a,0xc6,0xfe]
+  vmaxnm.f64 d5, d22, d30
+@ CHECK: vmaxnm.f64 d5, d22, d30   @ encoding: [0xae,0x5b,0x86,0xfe]
+  vminnm.f32 s0, s0, s12
+@ CHECK: vminnm.f32 s0, s0, s12    @ encoding: [0x46,0x0a,0x80,0xfe]
+  vminnm.f64 d4, d6, d9
+@ CHECK: vminnm.f64 d4, d6, d9     @ encoding: [0x49,0x4b,0x86,0xfe]
+
+@ VRINT{Z,R,X}
+
+  vrintzge.f64 d3, d12
+@ CHECK: vrintzge.f64 d3, d12   @ encoding: [0xcc,0x3b,0xb6,0xae]
+  vrintz.f32 s3, s24
+@ CHECK: vrintz.f32 s3, s24     @ encoding: [0xcc,0x1a,0xf6,0xee]
+  vrintrlt.f64 d5, d0
+@ CHECK: vrintrlt.f64 d5, d0    @ encoding: [0x40,0x5b,0xb6,0xbe]
+  vrintr.f32 s0, s9
+@ CHECK: vrintr.f32 s0, s9      @ encoding: [0x64,0x0a,0xb6,0xee]
+  vrintxeq.f64 d28, d30
+@ CHECK: vrintxeq.f64 d28, d30  @ encoding: [0x6e,0xcb,0xf7,0x0e]
+  vrintxvs.f32 s10, s14
+@ CHECK: vrintxvs.f32 s10, s14  @ encoding: [0x47,0x5a,0xb7,0x6e]
+
+@ VRINT{A,N,P,M}
+
+  vrinta.f64 d3, d4
+@ CHECK: vrinta.f64 d3, d4     @ encoding: [0x44,0x3b,0xb8,0xfe]
+  vrinta.f32 s12, s1
+@ CHECK: vrinta.f32 s12, s1    @ encoding: [0x60,0x6a,0xb8,0xfe]
+  vrintn.f64 d3, d4
+@ CHECK: vrintn.f64 d3, d4     @ encoding: [0x44,0x3b,0xb9,0xfe]
+  vrintn.f32 s12, s1
+@ CHECK: vrintn.f32 s12, s1    @ encoding: [0x60,0x6a,0xb9,0xfe]
+  vrintp.f64 d3, d4
+@ CHECK: vrintp.f64 d3, d4     @ encoding: [0x44,0x3b,0xba,0xfe]
+  vrintp.f32 s12, s1
+@ CHECK: vrintp.f32 s12, s1    @ encoding: [0x60,0x6a,0xba,0xfe]
+  vrintm.f64 d3, d4
+@ CHECK: vrintm.f64 d3, d4     @ encoding: [0x44,0x3b,0xbb,0xfe]
+  vrintm.f32 s12, s1
+@ CHECK: vrintm.f32 s12, s1    @ encoding: [0x60,0x6a,0xbb,0xfe]
diff --git a/test/MC/AsmParser/align_invalid.s b/test/MC/AsmParser/align_invalid.s
index 0d06d94..7ffbed4 100644
--- a/test/MC/AsmParser/align_invalid.s
+++ b/test/MC/AsmParser/align_invalid.s
@@ -1,5 +1,5 @@
-# RUN: llvm-mc -triple i386-linux-gnu < %s 2>&1 | FileCheck %s -check-prefix=ELF
-# RUN: llvm-mc -triple i386-apple-darwin < %s 2>&1 | FileCheck %s -check-prefix=DARWIN
+# RUN: not llvm-mc -triple i386-linux-gnu < %s 2>&1 | FileCheck %s -check-prefix=ELF
+# RUN: not llvm-mc -triple i386-apple-darwin < %s 2>&1 | FileCheck %s -check-prefix=DARWIN
 
 .align 3
 # ELF: error: alignment must be a power of 2
diff --git a/test/MC/AsmParser/directive_align.s b/test/MC/AsmParser/directive_align.s
index 15eb430..7ce2855 100644
--- a/test/MC/AsmParser/directive_align.s
+++ b/test/MC/AsmParser/directive_align.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple i386-apple-darwin9 %s | FileCheck %s
+# RUN: not llvm-mc -triple i386-apple-darwin9 %s | FileCheck %s
 
 # CHECK: TEST0:
 # CHECK: .align 1
diff --git a/test/MC/AsmParser/macros-darwin.s b/test/MC/AsmParser/macros-darwin.s
index 31b9edb..95965d3 100644
--- a/test/MC/AsmParser/macros-darwin.s
+++ b/test/MC/AsmParser/macros-darwin.s
@@ -1,4 +1,4 @@
-// RUN: not llvm-mc -triple i386-apple-darwin10 %s 2> %t.err | FileCheck %s
+// RUN: llvm-mc -triple i386-apple-darwin10 %s | FileCheck %s
 
 .macro test1
 .globl "$0 $1 $2 $$3 $n"
diff --git a/test/MC/AsmParser/secure_log_unique.s b/test/MC/AsmParser/secure_log_unique.s
new file mode 100644
index 0000000..8145981
--- /dev/null
+++ b/test/MC/AsmParser/secure_log_unique.s
@@ -0,0 +1,9 @@
+// RUN: rm -f %t
+// RUN: env AS_SECURE_LOG_FILE=%t llvm-mc -triple x86_64-apple-darwin %s
+// RUN: env AS_SECURE_LOG_FILE=%t llvm-mc -triple x86_64-apple-darwin %s
+// RUN: FileCheck --input-file=%t %s
+.secure_log_unique "foobar"
+
+// CHECK: "foobar"
+// CHECK-NEXT: "foobar"
+
diff --git a/test/MC/COFF/alias.s b/test/MC/COFF/alias.s
new file mode 100644
index 0000000..f6f6d46
--- /dev/null
+++ b/test/MC/COFF/alias.s
@@ -0,0 +1,106 @@
+// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s -o - | llvm-readobj -t -r | FileCheck %s
+
+local1:
+external_aliased_to_local = local1
+
+        .globl  global_aliased_to_external
+global_aliased_to_external = external1
+
+        .globl  global_aliased_to_local
+local2:
+global_aliased_to_local = local2
+
+        .weak   weak_aliased_to_external
+weak_aliased_to_external = external2
+
+// Generate relocs against the above aliases.
+        .long external_aliased_to_local
+        .long global_aliased_to_external
+        .long global_aliased_to_local
+        .long weak_aliased_to_external
+
+// CHECK:      Relocations [
+// CHECK:        0x0 IMAGE_REL_I386_DIR32 local1
+// CHECK:        0x4 IMAGE_REL_I386_DIR32 external1
+// CHECK:        0x8 IMAGE_REL_I386_DIR32 local2
+// CHECK:        0xC IMAGE_REL_I386_DIR32 external2
+// CHECK:      ]
+// CHECK:      Symbols [
+// CHECK-NEXT:   Symbol {
+// CHECK-NEXT:     Name: .text
+// CHECK-NEXT:     Value: 0
+// CHECK-NEXT:     Section: .text (1)
+// CHECK-NEXT:     BaseType: Null (0x0)
+// CHECK-NEXT:     ComplexType: Null (0x0)
+// CHECK-NEXT:     StorageClass: Static (0x3)
+// CHECK-NEXT:     AuxSymbolCount: 1
+// CHECK:        }
+// CHECK:        Symbol {
+// CHECK-NEXT:     Name: local1
+// CHECK-NEXT:     Value: 0
+// CHECK-NEXT:     Section: .text (1)
+// CHECK-NEXT:     BaseType: Null (0x0)
+// CHECK-NEXT:     ComplexType: Null (0x0)
+// CHECK-NEXT:     StorageClass: Static (0x3)
+// CHECK-NEXT:     AuxSymbolCount: 0
+// CHECK-NEXT:   }
+// CHECK-NEXT:   Symbol {
+// CHECK-NEXT:     Name: global_aliased_to_external
+// CHECK-NEXT:     Value: 0
+// CHECK-NEXT:     Section:  (0)
+// CHECK-NEXT:     BaseType: Null (0x0)
+// CHECK-NEXT:     ComplexType: Null (0x0)
+// CHECK-NEXT:     StorageClass: External (0x2)
+// CHECK-NEXT:     AuxSymbolCount: 0
+// CHECK-NEXT:   }
+// CHECK-NEXT:   Symbol {
+// CHECK-NEXT:     Name: external1
+// CHECK-NEXT:     Value: 0
+// CHECK-NEXT:     Section:  (0)
+// CHECK-NEXT:     BaseType: Null (0x0)
+// CHECK-NEXT:     ComplexType: Null (0x0)
+// CHECK-NEXT:     StorageClass: External (0x2)
+// CHECK-NEXT:     AuxSymbolCount: 0
+// CHECK-NEXT:   }
+// CHECK-NEXT:   Symbol {
+// CHECK-NEXT:     Name: global_aliased_to_local
+// CHECK-NEXT:     Value: 0
+// CHECK-NEXT:     Section: .text (1)
+// CHECK-NEXT:     BaseType: Null (0x0)
+// CHECK-NEXT:     ComplexType: Null (0x0)
+// CHECK-NEXT:     StorageClass: Static (0x3)
+// CHECK-NEXT:     AuxSymbolCount: 0
+// CHECK-NEXT:   }
+// CHECK-NEXT:   Symbol {
+// CHECK-NEXT:     Name: local2
+// CHECK-NEXT:     Value: 0
+// CHECK-NEXT:     Section: .text (1)
+// CHECK-NEXT:     BaseType: Null (0x0)
+// CHECK-NEXT:     ComplexType: Null (0x0)
+// CHECK-NEXT:     StorageClass: Static (0x3)
+// CHECK-NEXT:     AuxSymbolCount: 0
+// CHECK-NEXT:   }
+// CHECK-NEXT:   Symbol {
+// CHECK-NEXT:     Name: weak_aliased_to_external
+// CHECK-NEXT:     Value: 0
+// CHECK-NEXT:     Section:  (0)
+// CHECK-NEXT:     BaseType: Null (0x0)
+// CHECK-NEXT:     ComplexType: Null (0x0)
+// CHECK-NEXT:     StorageClass: WeakExternal (0x69)
+// CHECK-NEXT:     AuxSymbolCount: 1
+// CHECK-NEXT:     AuxWeakExternal {
+// CHECK-NEXT:       Linked: external2 (9)
+// CHECK-NEXT:       Search: Library (0x2)
+// CHECK-NEXT:       Unused: (00 00 00 00 00 00 00 00 00 00)
+// CHECK-NEXT:     }
+// CHECK-NEXT:   }
+// CHECK-NEXT:   Symbol {
+// CHECK-NEXT:     Name: external2
+// CHECK-NEXT:     Value: 0
+// CHECK-NEXT:     Section:  (0)
+// CHECK-NEXT:     BaseType: Null (0x0)
+// CHECK-NEXT:     ComplexType: Null (0x0)
+// CHECK-NEXT:     StorageClass: External (0x2)
+// CHECK-NEXT:     AuxSymbolCount: 0
+// CHECK-NEXT:   }
+// CHECK-NEXT: ]
diff --git a/test/MC/COFF/linkonce-invalid.s b/test/MC/COFF/linkonce-invalid.s
new file mode 100644
index 0000000..90ce4a7
--- /dev/null
+++ b/test/MC/COFF/linkonce-invalid.s
@@ -0,0 +1,40 @@
+// Test invalid use of the .linkonce directive.
+//
+// RUN: not llvm-mc -triple i386-pc-win32 -filetype=obj %s 2>&1 | FileCheck %s
+
+.section non_comdat
+
+.section comdat
+.linkonce discard
+
+.section assoc
+.linkonce associative comdat
+
+
+.section invalid
+
+// CHECK: error: unrecognized COMDAT type 'unknown'
+.linkonce unknown
+
+// CHECK: error: unexpected token in directive
+.linkonce discard foo
+
+// CHECK: error: expected associated section name
+.linkonce associative
+
+// CHECK: error: cannot associate unknown section 'unknown'
+.linkonce associative unknown
+
+// CHECK: error: cannot associate a section with itself
+.linkonce associative invalid
+
+// CHECK: error: associated section must be a COMDAT section
+.linkonce associative non_comdat
+
+// CHECK: error: associated section cannot be itself associative
+.linkonce associative assoc
+
+// CHECK: error: section 'multi' is already linkonce
+.section multi
+.linkonce discard
+.linkonce same_size
diff --git a/test/MC/COFF/linkonce.s b/test/MC/COFF/linkonce.s
new file mode 100644
index 0000000..e7b7f47
--- /dev/null
+++ b/test/MC/COFF/linkonce.s
@@ -0,0 +1,179 @@
+// Test section manipulation via .linkonce directive.
+//
+// RUN: llvm-mc -triple i386-pc-win32 -filetype=obj %s | llvm-readobj -s -t | FileCheck %s
+// RUN: llvm-mc -triple x86_64-pc-win32 -filetype=obj %s | llvm-readobj -s -t | FileCheck %s
+
+.section s1
+.linkonce
+.long 1
+
+.section s2
+.linkonce one_only
+.long 1
+
+.section s3
+.linkonce discard
+.long 1
+
+.section s4
+.linkonce same_size
+.long 1
+
+.section s5
+.linkonce same_contents
+.long 1
+
+.section s6
+.linkonce associative s1
+.long 1
+
+.section s7
+.linkonce largest
+.long 1
+
+.section s8
+.linkonce newest
+.long 1
+
+.section .foo$bar
+.linkonce discard
+.long 1
+
+// Check that valid '.section' names can be associated.
+.section multi
+.linkonce associative .foo$bar
+.long 1
+
+
+// CHECK: Sections [
+// CHECK:   Section {
+// CHECK:     Name: s1
+// CHECK:     Characteristics [
+// CHECK:       IMAGE_SCN_LNK_COMDAT
+// CHECK:     ]
+// CHECK:   }
+// CHECK:   Section {
+// CHECK:     Name: s2
+// CHECK:     Characteristics [
+// CHECK:       IMAGE_SCN_LNK_COMDAT
+// CHECK:     ]
+// CHECK:   }
+// CHECK:   Section {
+// CHECK:     Name: s3
+// CHECK:     Characteristics [
+// CHECK:       IMAGE_SCN_LNK_COMDAT
+// CHECK:     ]
+// CHECK:   }
+// CHECK:   Section {
+// CHECK:     Name: s4
+// CHECK:     Characteristics [
+// CHECK:       IMAGE_SCN_LNK_COMDAT
+// CHECK:     ]
+// CHECK:   }
+// CHECK:   Section {
+// CHECK:     Name: s5
+// CHECK:     Characteristics [
+// CHECK:       IMAGE_SCN_LNK_COMDAT
+// CHECK:     ]
+// CHECK:   }
+// CHECK:   Section {
+// CHECK:     Name: s6
+// CHECK:     Characteristics [
+// CHECK:       IMAGE_SCN_LNK_COMDAT
+// CHECK:     ]
+// CHECK:   }
+// CHECK:   Section {
+// CHECK:     Name: s7
+// CHECK:     Characteristics [
+// CHECK:       IMAGE_SCN_LNK_COMDAT
+// CHECK:     ]
+// CHECK:   }
+// CHECK:   Section {
+// CHECK:     Name: s8
+// CHECK:     Characteristics [
+// CHECK:       IMAGE_SCN_LNK_COMDAT
+// CHECK:     ]
+// CHECK:   }
+// CHECK:   Section {
+// CHECK:     Name: multi
+// CHECK:     Characteristics [
+// CHECK:       IMAGE_SCN_LNK_COMDAT
+// CHECK:     ]
+// CHECK:   }
+// CHECK: ]
+// CHECK: Symbols [
+// CHECK:   Symbol {
+// CHECK:     Name: s1
+// CHECK:     Section: s1 (1)
+// CHECK:     AuxSectionDef {
+// CHECK:       Number: 1
+// CHECK:       Selection: Any (0x2)
+// CHECK:     }
+// CHECK:   }
+// CHECK:   Symbol {
+// CHECK:     Name: s2
+// CHECK:     Section: s2 (2)
+// CHECK:     AuxSectionDef {
+// CHECK:       Number: 2
+// CHECK:       Selection: NoDuplicates (0x1)
+// CHECK:     }
+// CHECK:   }
+// CHECK:   Symbol {
+// CHECK:     Name: s3
+// CHECK:     Section: s3 (3)
+// CHECK:     AuxSectionDef {
+// CHECK:       Number: 3
+// CHECK:       Selection: Any (0x2)
+// CHECK:     }
+// CHECK:   }
+// CHECK:   Symbol {
+// CHECK:     Name: s4
+// CHECK:     Section: s4 (4)
+// CHECK:     AuxSectionDef {
+// CHECK:       Number: 4
+// CHECK:       Selection: SameSize (0x3)
+// CHECK:     }
+// CHECK:   }
+// CHECK:   Symbol {
+// CHECK:     Name: s5
+// CHECK:     Section: s5 (5)
+// CHECK:     AuxSectionDef {
+// CHECK:       Number: 5
+// CHECK:       Selection: ExactMatch (0x4)
+// CHECK:     }
+// CHECK:   }
+// CHECK:   Symbol {
+// CHECK:     Name: s6
+// CHECK:     Section: s6 (6)
+// CHECK:     AuxSectionDef {
+// CHECK:       Number: 1
+// CHECK:       Selection: Associative (0x5)
+// CHECK:       AssocSection: s1
+// CHECK:     }
+// CHECK:   }
+// CHECK:   Symbol {
+// CHECK:     Name: s7
+// CHECK:     Section: s7 (7)
+// CHECK:     AuxSectionDef {
+// CHECK:       Number: 7
+// CHECK:       Selection: Largest (0x6)
+// CHECK:     }
+// CHECK:   }
+// CHECK:   Symbol {
+// CHECK:     Name: s8
+// CHECK:     Section: s8 (8)
+// CHECK:     AuxSectionDef {
+// CHECK:       Number: 8
+// CHECK:       Selection: Newest (0x7)
+// CHECK:     }
+// CHECK:   }
+// CHECK:   Symbol {
+// CHECK:     Name: multi
+// CHECK:     Value: 0
+// CHECK:     Section: multi (10)
+// CHECK:     AuxSectionDef {
+// CHECK:       Number: 9
+// CHECK:       Selection: Associative (0x5)
+// CHECK:       AssocSection: .foo$bar
+// CHECK:     }
+// CHECK:   }
diff --git a/test/MC/COFF/section-invalid-flags.s b/test/MC/COFF/section-invalid-flags.s
new file mode 100644
index 0000000..17b1550
--- /dev/null
+++ b/test/MC/COFF/section-invalid-flags.s
@@ -0,0 +1,8 @@
+// RUN: not llvm-mc -triple i386-pc-win32 -filetype=obj %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple x86_64-pc-win32 -filetype=obj %s 2>&1 | FileCheck %s
+
+// CHECK: error: conflicting section flags 'b' and 'd'
+.section s_db,"db"; .long 1
+
+// CHECK: error: conflicting section flags 'b' and 'd'
+.section s_bd,"bd"; .long 1
diff --git a/test/MC/COFF/section-name-encoding.s b/test/MC/COFF/section-name-encoding.s
new file mode 100644
index 0000000..0f531f3
--- /dev/null
+++ b/test/MC/COFF/section-name-encoding.s
@@ -0,0 +1,62 @@
+// Check that COFF section names are properly encoded.
+//
+// Encodings for different lengths:
+//   [0, 8]:               raw name
+//   (8, 999999]:          base 10 string table index (/9999999)
+//
+// RUN: llvm-mc -triple x86_64-pc-win32 -filetype=obj %s | llvm-readobj -s | FileCheck %s
+
+// Raw encoding
+
+// CHECK:   Section {
+// CHECK:     Number: 1
+// CHECK:     Name: s (73 00 00 00 00 00 00 00)
+// CHECK:   }
+// CHECK:   Section {
+// CHECK:     Number: 2
+// CHECK:     Name: s1234567 (73 31 32 33 34 35 36 37)
+// CHECK:   }
+.section s;        .long 1
+.section s1234567; .long 1
+
+
+// Base 10 encoding
+
+// /4
+// CHECK:   Section {
+// CHECK:     Number: 3
+// CHECK:     Name: s12345678 (2F 34 00 00 00 00 00 00)
+// CHECK:   }
+.section s12345678; .long 1
+
+
+// Generate padding sections to increase the string table size to at least
+// 1,000,000 bytes.
+.macro pad_sections2 pad
+  // 10x \pad
+  .section p0\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad; .long 1
+  .section p1\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad; .long 1
+  .section p2\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad; .long 1
+  .section p3\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad; .long 1
+  .section p4\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad; .long 1
+.endm
+
+.macro pad_sections pad
+  // 20x \pad
+  pad_sections2 \pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad\pad
+.endm
+
+// 1000x 'a'
+pad_sections aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
+
+
+// /1000029 == 4 + 10 + (5 * (2 + (20 * 10 * 1000) + 1))
+//             v   |     |    v    ~~~~~~~~~~~~~~    v
+//    table size   v     v   "p0"        pad         NUL seperator
+//     "s12345678\0"     # of pad sections
+//
+// CHECK:   Section {
+// CHECK:     Number: 9
+// CHECK:     Name: seven_digit (2F 31 30 30 30 30 32 39)
+// CHECK:   }
+.section seven_digit; .long 1
diff --git a/test/MC/COFF/section.s b/test/MC/COFF/section.s
new file mode 100644
index 0000000..d7547e6
--- /dev/null
+++ b/test/MC/COFF/section.s
@@ -0,0 +1,170 @@
+// RUN: llvm-mc -triple i386-pc-win32 -filetype=obj %s | llvm-readobj -s | FileCheck %s
+// RUN: llvm-mc -triple x86_64-pc-win32 -filetype=obj %s | llvm-readobj -s | FileCheck %s
+
+.section .foo$bar; .long 1
+.section .foo@bar; .long 1
+.section ABCDEFGHIJKLMNOPQRSTUVWXYZ; .long 1
+.section abcdefghijklmnopqrstuvwxyz; .long 1
+.section _0123456789; .long 1
+
+// CHECK: Sections [
+// CHECK:   Section {
+// CHECK:     Name: .foo$bar
+// CHECK:   }
+// CHECK:   Section {
+// CHECK:     Name: .foo@bar
+// CHECK:   }
+// CHECK:   Section {
+// CHECK:     Name: ABCDEFGHIJKLMNOPQRSTUVWXYZ
+// CHECK:   }
+// CHECK:   Section {
+// CHECK:     Name: abcdefghijklmnopqrstuvwxyz
+// CHECK:   }
+// CHECK:   Section {
+// CHECK:     Name: _0123456789
+// CHECK:   }
+
+// Test that the defaults are used
+.section s      ; .long 1
+.section s_, "" ; .long 1
+.section s_a,"a"; .long 1
+.section s_b,"b"; .long 1
+.section s_d,"d"; .long 1
+.section s_n,"n"; .long 1
+.section s_r,"r"; .long 1
+.section s_s,"s"; .long 1
+.section s_w,"w"; .long 1
+.section s_x,"x"; .long 1
+.section s_y,"y"; .long 1
+
+// CHECK:        Section {
+// CHECK:          Name: s
+// CHECK:          Characteristics [
+// CHECK-NEXT:       IMAGE_SCN_ALIGN_1BYTES
+// CHECK-NEXT:       IMAGE_SCN_CNT_INITIALIZED_DATA
+// CHECK-NEXT:       IMAGE_SCN_MEM_READ
+// CHECK-NEXT:       IMAGE_SCN_MEM_WRITE
+// CHECK-NEXT:     ]
+// CHECK:        }
+// CHECK:        Section {
+// CHECK:          Name: s_
+// CHECK:          Characteristics [
+// CHECK-NEXT:       IMAGE_SCN_ALIGN_1BYTES
+// CHECK-NEXT:       IMAGE_SCN_CNT_INITIALIZED_DATA
+// CHECK-NEXT:       IMAGE_SCN_MEM_READ
+// CHECK-NEXT:       IMAGE_SCN_MEM_WRITE
+// CHECK-NEXT:     ]
+// CHECK:        }
+// CHECK:        Section {
+// CHECK:          Name: s_a
+// CHECK:          Characteristics [
+// CHECK-NEXT:       IMAGE_SCN_ALIGN_1BYTES
+// CHECK-NEXT:       IMAGE_SCN_CNT_INITIALIZED_DATA
+// CHECK-NEXT:       IMAGE_SCN_MEM_READ
+// CHECK-NEXT:       IMAGE_SCN_MEM_WRITE
+// CHECK-NEXT:     ]
+// CHECK:        }
+// CHECK:        Section {
+// CHECK:          Name: s_b
+// CHECK:          Characteristics [
+// CHECK-NEXT:       IMAGE_SCN_ALIGN_1BYTES
+// CHECK-NEXT:       IMAGE_SCN_CNT_UNINITIALIZED_DATA
+// CHECK-NEXT:       IMAGE_SCN_MEM_READ
+// CHECK-NEXT:       IMAGE_SCN_MEM_WRITE
+// CHECK-NEXT:     ]
+// CHECK:        }
+// CHECK:        Section {
+// CHECK:          Name: s_d
+// CHECK:          Characteristics [
+// CHECK-NEXT:       IMAGE_SCN_ALIGN_1BYTES
+// CHECK-NEXT:       IMAGE_SCN_CNT_INITIALIZED_DATA
+// CHECK-NEXT:       IMAGE_SCN_MEM_READ
+// CHECK-NEXT:       IMAGE_SCN_MEM_WRITE
+// CHECK-NEXT:     ]
+// CHECK:        }
+// CHECK:        Section {
+// CHECK:          Name: s_n
+// CHECK:          Characteristics [
+// CHECK-NEXT:       IMAGE_SCN_ALIGN_1BYTES
+// CHECK-NEXT:       IMAGE_SCN_LNK_REMOVE
+// CHECK-NEXT:       IMAGE_SCN_MEM_READ
+// CHECK-NEXT:       IMAGE_SCN_MEM_WRITE
+// CHECK-NEXT:     ]
+// CHECK:        }
+// CHECK:        Section {
+// CHECK:          Name: s_r
+// CHECK:          Characteristics [
+// CHECK-NEXT:       IMAGE_SCN_ALIGN_1BYTES
+// CHECK-NEXT:       IMAGE_SCN_CNT_INITIALIZED_DATA
+// CHECK-NEXT:       IMAGE_SCN_MEM_READ
+// CHECK-NEXT:     ]
+// CHECK:        }
+// CHECK:        Section {
+// CHECK:          Name: s_s
+// CHECK:          Characteristics [
+// CHECK-NEXT:       IMAGE_SCN_ALIGN_1BYTES
+// CHECK-NEXT:       IMAGE_SCN_CNT_INITIALIZED_DATA
+// CHECK-NEXT:       IMAGE_SCN_MEM_READ
+// CHECK-NEXT:       IMAGE_SCN_MEM_SHARED
+// CHECK-NEXT:       IMAGE_SCN_MEM_WRITE
+// CHECK-NEXT:     ]
+// CHECK:        }
+// CHECK:        Section {
+// CHECK:          Name: s_w
+// CHECK:          Characteristics [
+// CHECK-NEXT:       IMAGE_SCN_ALIGN_1BYTES
+// CHECK-NEXT:       IMAGE_SCN_CNT_INITIALIZED_DATA
+// CHECK-NEXT:       IMAGE_SCN_MEM_READ
+// CHECK-NEXT:       IMAGE_SCN_MEM_WRITE
+// CHECK-NEXT:     ]
+// CHECK:        }
+// CHECK:        Section {
+// CHECK:          Name: s_x
+// CHECK:          Characteristics [
+// CHECK-NEXT:       IMAGE_SCN_ALIGN_1BYTES
+// CHECK-NEXT:       IMAGE_SCN_CNT_CODE
+// CHECK-NEXT:       IMAGE_SCN_MEM_EXECUTE
+// CHECK-NEXT:       IMAGE_SCN_MEM_READ
+// CHECK-NEXT:     ]
+// CHECK:        }
+// CHECK:        Section {
+// CHECK:          Name: s_y
+// CHECK:          Characteristics [
+// CHECK-NEXT:       IMAGE_SCN_ALIGN_1BYTES
+// CHECK-NEXT:     ]
+// CHECK:        }
+
+// w makes read-only to readable
+.section s_rw,"rw"; .long 1
+// CHECK:        Section {
+// CHECK:          Name: s_rw
+// CHECK:          Characteristics [
+// CHECK-NEXT:       IMAGE_SCN_ALIGN_1BYTES
+// CHECK-NEXT:       IMAGE_SCN_CNT_INITIALIZED_DATA
+// CHECK-NEXT:       IMAGE_SCN_MEM_READ
+// CHECK-NEXT:       IMAGE_SCN_MEM_WRITE
+// CHECK-NEXT:     ]
+// CHECK:        }
+
+// r cancels w
+.section s_wr,"wr"; .long 1
+// CHECK:        Section {
+// CHECK:          Name: s_wr
+// CHECK:          Characteristics [
+// CHECK-NEXT:       IMAGE_SCN_ALIGN_1BYTES
+// CHECK-NEXT:       IMAGE_SCN_CNT_INITIALIZED_DATA
+// CHECK-NEXT:       IMAGE_SCN_MEM_READ
+// CHECK-NEXT:     ]
+// CHECK:        }
+
+// y cancels both
+.section s_rwy,"rwy"; .long 1
+// CHECK:        Section {
+// CHECK:          Name: s_rwy
+// CHECK:          Characteristics [
+// CHECK-NEXT:       IMAGE_SCN_ALIGN_1BYTES
+// CHECK-NEXT:       IMAGE_SCN_CNT_INITIALIZED_DATA
+// CHECK-NEXT:     ]
+// CHECK:        }
+
+// CHECK:      ]
diff --git a/test/MC/COFF/seh-section.s b/test/MC/COFF/seh-section.s
index 7f05cc3..026c0d7 100644
--- a/test/MC/COFF/seh-section.s
+++ b/test/MC/COFF/seh-section.s
@@ -1,7 +1,6 @@
 // This test ensures that, if the section containing a function has a suffix
 // (e.g. .text$foo), its unwind info section also has a suffix (.xdata$foo).
 // RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | llvm-readobj -s -sd | FileCheck %s
-// XFAIL: *
 
 // CHECK:      Name: .xdata$foo
 // CHECK-NEXT: VirtualSize
@@ -16,7 +15,6 @@
 // CHECK-NEXT:   IMAGE_SCN_ALIGN_4BYTES
 // CHECK-NEXT:   IMAGE_SCN_CNT_INITIALIZED_DATA
 // CHECK-NEXT:   IMAGE_SCN_MEM_READ
-// CHECK-NEXT:   IMAGE_SCN_MEM_WRITE
 // CHECK-NEXT: ]
 // CHECK-NEXT: SectionData (
 // CHECK-NEXT:   0000: 01050200 05500402
diff --git a/test/MC/COFF/weak-symbol-section-specification.ll b/test/MC/COFF/weak-symbol-section-specification.ll
deleted file mode 100644
index 4772c92..0000000
--- a/test/MC/COFF/weak-symbol-section-specification.ll
+++ /dev/null
@@ -1,25 +0,0 @@
-; The purpose of this test is to verify that weak linkage type is not ignored by backend,
-; if section was specialized.
-
-; RUN: llc -filetype=obj -mtriple i686-pc-win32 %s -o - | llvm-readobj -s -sd | FileCheck %s
-
-@a = weak unnamed_addr constant { i32, i32, i32 } { i32 0, i32 0, i32 0}, section ".data"
-
-; CHECK:           Name:                      .data$a
-; CHECK-NEXT:      VirtualSize:               0
-; CHECK-NEXT:      VirtualAddress:            0
-; CHECK-NEXT:      RawDataSize:               {{[0-9]+}}
-; CHECK-NEXT:      PointerToRawData:          0x{{[0-9A-F]+}}
-; CHECK-NEXT:      PointerToRelocations:      0x0
-; CHECK-NEXT:      PointerToLineNumbers:      0x0
-; CHECK-NEXT:      RelocationCount:           0
-; CHECK-NEXT:      LineNumberCount:           0
-; CHECK-NEXT:      Characteristics [ (0x40401040)
-; CHECK-NEXT:        IMAGE_SCN_ALIGN_8BYTES
-; CHECK-NEXT:        IMAGE_SCN_CNT_INITIALIZED_DATA
-; CHECK-NEXT:        IMAGE_SCN_LNK_COMDAT
-; CHECK-NEXT:        IMAGE_SCN_MEM_READ
-; CHECK-NEXT:      ]
-; CHECK-NEXT:      SectionData (
-; CHECK-NEXT:        0000: 00000000 00000000 00000000
-; CHECK-NEXT:      )
diff --git a/test/MC/COFF/weak-symbol.ll b/test/MC/COFF/weak-symbol.ll
new file mode 100644
index 0000000..7f2e87c
--- /dev/null
+++ b/test/MC/COFF/weak-symbol.ll
@@ -0,0 +1,44 @@
+; Test that weak functions and globals are placed into selectany COMDAT

+; sections with the mangled name as suffix. Ensure that the weak linkage

+; type is not ignored by the backend if the section was specialized.

+;

+; RUN: llc -mtriple=i686-pc-win32 %s     -o - | FileCheck %s --check-prefix=X86

+; RUN: llc -mtriple=i686-pc-mingw32 %s   -o - | FileCheck %s --check-prefix=X86

+; RUN: llc -mtriple=x86_64-pc-win32 %s   -o - | FileCheck %s --check-prefix=X64

+; RUN: llc -mtriple=x86_64-pc-mingw32 %s -o - | FileCheck %s --check-prefix=X64

+

+; Mangled function

+; X86: .section .text$_Z3foo

+; X86: .linkonce discard

+; X86: .globl __Z3foo

+;

+; X64: .section .text$_Z3foo

+; X64: .linkonce discard

+; X64: .globl _Z3foo

+define weak void @_Z3foo() {

+  ret void

+}

+

+; Unmangled function

+; X86: .section .sect$f

+; X86: .linkonce discard

+; X86: .globl _f

+;

+; X64: .section .sect$f

+; X64: .linkonce discard

+; X64: .globl f

+define weak void @f() section ".sect" {

+  ret void

+}

+

+; Weak global

+; X86: .section .data$a

+; X86: .linkonce discard

+; X86: .globl _a

+; X86: .zero 12

+;

+; X64: .section .data$a

+; X64: .linkonce discard

+; X64: .globl a

+; X64: .zero 12

+@a = weak unnamed_addr constant { i32, i32, i32 } { i32 0, i32 0, i32 0}, section ".data"

diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt
new file mode 100644
index 0000000..40d1f4c
--- /dev/null
+++ b/test/MC/Disassembler/AArch64/neon-instructions.txt
@@ -0,0 +1,673 @@
+# RUN: llvm-mc  -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s | FileCheck %s
+
+#------------------------------------------------------------------------------
+# Vector Integer Add/Sub
+#------------------------------------------------------------------------------
+# CHECK: add v31.8b, v31.8b, v31.8b
+# CHECK: sub v0.2d, v0.2d, v0.2d
+0xff 0x87 0x3f 0x0e
+0x00 0x84 0xe0 0x6e
+
+#------------------------------------------------------------------------------
+# Vector Floating-Point Add/Sub
+#------------------------------------------------------------------------------
+
+# CHECK: fadd v0.4s, v0.4s, v0.4s
+# CHECK: fsub v31.2s, v31.2s, v31.2s
+0x00 0xd4 0x20 0x4e
+0xff 0xd7 0xbf 0x0e
+
+#------------------------------------------------------------------------------
+# Vector Integer Mul
+#------------------------------------------------------------------------------
+# CHECK: mul v0.8b, v1.8b, v2.8b
+0x20 0x9c 0x22 0x0e
+
+#------------------------------------------------------------------------------
+# Vector Floating-Point Mul/Div
+#------------------------------------------------------------------------------
+# CHECK: fmul v0.2s, v1.2s, v2.2s
+# CHECK: fdiv v31.2s, v31.2s, v31.2s
+0x20 0xdc 0x22 0x2e
+0xff 0xff 0x3f 0x2e
+
+#----------------------------------------------------------------------
+# Vector Polynomial Multiply
+#----------------------------------------------------------------------
+# CHECK: pmul v0.8b, v15.8b, v16.8b
+# CHECK: pmul v31.16b, v7.16b, v8.16b
+0xe0 0x9d 0x30 0x2e
+0xff 0x9c 0x28 0x6e
+
+#------------------------------------------------------------------------------
+# Vector And, Orr, Eor, Orn, Bic
+#------------------------------------------------------------------------------
+# CHECK: and v2.8b, v2.8b, v2.8b
+# CHECK: orr v31.16b, v31.16b, v30.16b
+# CHECK: eor v0.16b, v1.16b, v2.16b
+# CHECK: orn v9.16b, v10.16b, v11.16b
+# CHECK: bic v31.8b, v30.8b, v29.8b
+0x42 0x1c 0x22 0x0e
+0xff 0x1f 0xbe 0x4e
+0x20 0x1c 0x22 0x6e
+0x49 0x1d 0xeb 0x4e
+0xdf 0x1f 0x7d 0x0e
+
+#------------------------------------------------------------------------------
+# Vector Bsl, Bit, Bif
+#------------------------------------------------------------------------------
+# CHECK: bsl v0.8b, v1.8b, v2.8b
+# CHECK: bit v31.16b, v31.16b, v31.16b
+# CHECK: bif v0.16b, v1.16b, v2.16b
+0x20 0x1c 0x62 0x2e
+0xff 0x1f 0xbf 0x6e
+0x20 0x1c 0xe2 0x6e
+
+
+#------------------------------------------------------------------------------
+# Vector Integer Multiply-accumulate and Multiply-subtract
+#------------------------------------------------------------------------------
+# CHECK: mla v0.8b, v1.8b, v2.8b
+# CHECK: mls v31.4h, v31.4h, v31.4h
+0x20 0x94 0x22 0x0e
+0xff 0x97 0x7f 0x2e
+
+#------------------------------------------------------------------------------
+# Vector Floating-Point Multiply-accumulate and Multiply-subtract
+#------------------------------------------------------------------------------
+# CHECK: fmla v0.2s, v1.2s, v2.2s
+# CHECK: fmls v31.2s, v31.2s, v31.2s
+0x20 0xcc 0x22 0x0e
+0xff 0xcf 0xbf 0x0e
+
+#------------------------------------------------------------------------------
+# Vector Move Immediate Shifted
+# Vector Move Inverted Immediate Shifted
+# Vector Bitwise Bit Clear (AND NOT) - immediate
+# Vector Bitwise OR - immedidate
+#------------------------------------------------------------------------------
+# CHECK: movi v31.4s, #0xff, lsl #24
+# CHECK: mvni v0.2s, #0x0
+# CHECK: bic v15.4h, #0xf, lsl #8
+# CHECK: orr v16.8h, #0x1f
+0xff 0x67 0x07 0x4f
+0x00 0x04 0x00 0x2f
+0xef 0xb5 0x00 0x2f
+0xf0 0x97 0x00 0x4f
+
+#------------------------------------------------------------------------------
+# Vector Move Immediate Masked
+# Vector Move Inverted Immediate Masked
+#------------------------------------------------------------------------------
+# CHECK: movi v8.2s, #0x8, msl #8
+# CHECK: mvni v16.4s, #0x10, msl #16
+0x08 0xc5 0x00 0x0f
+0x10 0xd6 0x00 0x6f
+
+#------------------------------------------------------------------------------
+# Vector Immediate - per byte
+# Vector Move Immediate - bytemask, per doubleword
+# Vector Move Immediate - bytemask, one doubleword
+#------------------------------------------------------------------------------
+# CHECK: movi v16.8b, #0xff
+# CHECK: movi v31.16b, #0x1f
+# CHECK: movi d15, #0xff00ff00ff00ff
+# CHECK: movi v31.2d, #0xff0000ff0000ffff
+0xf0 0xe7 0x07 0x0f
+0xff 0xe7 0x00 0x4f
+0xaf 0xe6 0x02 0x2f
+0x7f 0xe6 0x04 0x6f
+
+#------------------------------------------------------------------------------
+# Vector Floating Point Move Immediate
+#------------------------------------------------------------------------------
+# CHECK: fmov v0.2s, #13.0
+# CHECK: fmov v15.4s, #1.0
+# CHECK: fmov v31.2d, #-1.25
+0x40 0xf5 0x01 0x0f
+0x0f 0xf6 0x03 0x4f
+0x9f 0xf6 0x07 0x6f
+
+#------------------------------------------------------------------------------
+# Vector Move - register
+#------------------------------------------------------------------------------
+# CHECK: mov v1.16b, v15.16b
+# CHECK: mov v25.8b, v4.8b
+0xe1 0x1d 0xaf 0x4e
+0x99 0x1c 0xa4 0x0e
+
+#----------------------------------------------------------------------
+# Vector Absolute Difference and Accumulate (Signed, Unsigned)
+# Vector Absolute Difference (Signed, Unsigned)
+# Vector Absolute Difference (Floating Point)
+#----------------------------------------------------------------------
+
+# CHECK: uaba v0.8b, v1.8b, v2.8b
+# CHECK: saba v31.16b, v30.16b, v29.16b
+# CHECK: uabd v15.4h, v16.4h, v17.4h
+# CHECK: sabd v5.4h, v4.4h, v6.4h
+# CHECK: fabd v1.4s, v31.4s, v16.4s
+0x20 0x7c 0x22 0x2e
+0xdf 0x7f 0x3d 0x4e
+0x0f 0x76 0x71 0x2e
+0x85 0x74 0x66 0x0e
+0xe1 0xd7 0xb0 0x6e
+
+#----------------------------------------------------------------------
+# Scalar Integer Add
+# Scalar Integer Sub
+#----------------------------------------------------------------------
+
+# CHECK: add d17, d31, d29
+# CHECK: sub d15, d5, d16
+0xf1 0x87 0xfd 0x5e
+0xaf 0x84 0xf0 0x7e
+
+#----------------------------------------------------------------------
+# Vector Reciprocal Square Root Step (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: frsqrts v31.2d, v15.2d, v8.2d
+0xff 0xfd 0xe8 0x4e
+
+#----------------------------------------------------------------------
+# Vector Reciprocal Step (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: frecps  v5.4s, v7.4s, v16.4s
+0xe5 0xfc 0x30 0x4e
+
+#----------------------------------------------------------------------
+# Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: facge v0.4s, v31.4s, v16.4s
+0xe0 0xef 0x30 0x6e
+
+#----------------------------------------------------------------------
+# Vector Absolute Compare Mask Less Than (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: facgt v31.2d, v29.2d, v28.2d
+0xbf 0xef 0xfc 0x6e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Equal (Integer)
+#----------------------------------------------------------------------
+# CHECK: cmeq v5.16b, v15.16b, v31.16b
+0xe5 0x8d 0x3f 0x6e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Higher or Same (Unsigned Integer)
+#----------------------------------------------------------------------
+# CHECK: cmhs v1.8b, v16.8b, v30.8b
+0x01 0x3e 0x3e 0x2e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Greater Than or Equal (Integer)
+#----------------------------------------------------------------------
+# CHECK: cmge v20.4h, v11.4h, v23.4h
+0x74 0x3d 0x77 0x0e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Higher (Unsigned Integer)
+# CHECK: cmhi v13.8h, v3.8h, v27.8h
+0x6d 0x34 0x7b 0x6e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Greater Than (Integer)
+#----------------------------------------------------------------------
+# CHECK: cmgt v9.4s, v4.4s, v28.4s
+0x89 0x34 0xbc 0x4e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Bitwise Test (Integer)
+#----------------------------------------------------------------------
+# CHECK: cmtst v21.2s, v19.2s, v18.2s
+0x75 0x8e 0xb2 0x0e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Equal (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fcmeq v0.2s, v15.2s, v16.2s
+0xe0 0xe5 0x30 0x0e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Greater Than Or Equal (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fcmge v31.4s, v7.4s, v29.4s
+0xff 0xe4 0x3d 0x6e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Greater Than (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fcmgt v17.4s, v8.4s, v25.4s
+0x11 0xe5 0xb9 0x6e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Equal to Zero (Integer)
+#----------------------------------------------------------------------
+# CHECK: cmeq v31.16b, v15.16b, #0x0
+0xff 0x99 0x20 0x4e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
+#----------------------------------------------------------------------
+# CHECK: cmge v3.8b, v15.8b, #0x0
+0xe3 0x89 0x20 0x2e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Greater Than Zero (Signed Integer)
+#----------------------------------------------------------------------
+# CHECK: cmgt v22.2s, v9.2s, #0x0
+0x36 0x89 0xa0 0x0e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
+#----------------------------------------------------------------------
+# CHECK: cmle v5.2d, v14.2d, #0x0
+0xc5 0x99 0xe0 0x6e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Less Than Zero (Signed Integer)
+#----------------------------------------------------------------------
+# CHECK: cmlt v13.8h, v11.8h, #0x0
+0x6d 0xa9 0x60 0x4e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Equal to Zero (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fcmeq v15.2s, v21.2s, #0.0
+0xaf 0xda 0xa0 0x0e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fcmge v14.2d, v13.2d, #0.0
+0xae 0xc9 0xe0 0x6e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Greater Than Zero (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fcmgt v9.4s, v23.4s, #0.0
+0xe9 0xca 0xa0 0x4e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Less Than or Equal To Zero (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fcmle v11.2d, v6.2d, #0.0
+0xcb 0xd8 0xe0 0x6e
+
+#----------------------------------------------------------------------
+# Vector Compare Mask Less Than Zero (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fcmlt v12.4s, v25.4s, #0.0
+0x2c 0xeb 0xa0 0x4e
+
+
+#------------------------------------------------------------------------------
+# Vector Integer Halving Add (Signed)
+# Vector Integer Halving Add (Unsigned)
+# Vector Integer Halving Sub (Signed)
+# Vector Integer Halving Sub (Unsigned)
+#------------------------------------------------------------------------------
+# CHECK: shadd v0.8b, v31.8b, v29.8b
+# CHECK: uhadd v15.16b, v16.16b, v17.16b
+# CHECK: shsub v0.4h, v1.4h, v2.4h
+# CHECK: uhadd v5.8h, v7.8h, v8.8h
+# CHECK: shsub v9.2s, v11.2s, v21.2s
+# CHECK: uhsub v22.4s, v30.4s, v19.4s
+0xe0 0x07 0x3d 0x0e
+0x0f 0x06 0x31 0x6e
+0x20 0x24 0x62 0x0e
+0xe5 0x04 0x68 0x6e
+0x69 0x25 0xb5 0x0e
+0xd6 0x27 0xb3 0x6e
+
+#------------------------------------------------------------------------------
+# Vector Integer Rouding Halving Add (Signed)
+# Vector Integer Rouding Halving Add (Unsigned)
+#------------------------------------------------------------------------------
+# CHECK: srhadd v3.8b, v5.8b, v7.8b
+# CHECK: urhadd v7.16b, v17.16b, v27.16b
+# CHECK: srhadd v10.4h, v11.4h, v13.4h
+# CHECK: urhadd v1.8h, v2.8h, v3.8h
+# CHECK: srhadd v4.2s, v5.2s, v6.2s
+# CHECK: urhadd v7.4s, v7.4s, v7.4s
+0xa3 0x14 0x27 0x0e
+0x27 0x16 0x3b 0x6e
+0x6a 0x15 0x6d 0x0e
+0x41 0x14 0x63 0x6e
+0xa4 0x14 0xa6 0x0e
+0xe7 0x14 0xa7 0x6e
+
+#------------------------------------------------------------------------------
+# Vector Integer Saturating Add (Signed)
+# Vector Integer Saturating Add (Unsigned)
+# Vector Integer Saturating Sub (Signed)
+# Vector Integer Saturating Sub (Unsigned)
+#------------------------------------------------------------------------------
+# CHECK: sqsub v0.8b, v1.8b, v2.8b
+# CHECK: sqadd v0.16b, v1.16b, v2.16b
+# CHECK: uqsub v0.4h, v1.4h, v2.4h
+# CHECK: uqadd v0.8h, v1.8h, v2.8h
+# CHECK: sqadd v0.2s, v1.2s, v2.2s
+# CHECK: sqsub v0.4s, v1.4s, v2.4s
+# CHECK: sqsub v0.2d, v1.2d, v2.2d
+0x20 0x2c 0x22 0x0e
+0x20 0x0c 0x22 0x4e
+0x20 0x2c 0x62 0x2e
+0x20 0x0c 0x62 0x6e
+0x20 0x0c 0xa2 0x0e
+0x20 0x2c 0xa2 0x4e
+0x20 0x2c 0xe2 0x4e
+
+#------------------------------------------------------------------------------
+# Scalar Integer Saturating Add (Signed)
+# Scalar Integer Saturating Add (Unsigned)
+# Scalar Integer Saturating Sub (Signed)
+# Scalar Integer Saturating Add (Unsigned)
+#------------------------------------------------------------------------------
+# CHECK: sqadd b20, b11, b15
+# CHECK: uqadd h0, h1, h5
+# CHECK: sqsub s20, s10, s7
+# CHECK: uqsub d16, d16, d16
+0x74 0x0d 0x2f 0x5e
+0x20 0x0c 0x65 0x7e
+0x54 0x2d 0xa7 0x5e
+0x10 0x2e 0xf0 0x7e
+
+
+#----------------------------------------------------------------------
+# Vector Shift Left (Signed and Unsigned Integer)
+#----------------------------------------------------------------------
+# CHECK: sshl v10.8b, v15.8b, v22.8b
+# CHECK: ushl v10.16b, v5.16b, v2.16b
+# CHECK: sshl v10.4h, v15.4h, v22.4h
+# CHECK: ushl v10.8h, v5.8h, v2.8h
+# CHECK: sshl v10.2s, v15.2s, v22.2s
+# CHECK: ushl v10.4s, v5.4s, v2.4s
+# CHECK: sshl v0.2d, v1.2d, v2.2d
+0xea 0x45 0x36 0x0e
+0xaa 0x44 0x22 0x6e
+0xea 0x45 0x76 0x0e
+0xaa 0x44 0x62 0x6e
+0xea 0x45 0xb6 0x0e
+0xaa 0x44 0xa2 0x6e
+0x20 0x44 0xe2 0x4e
+
+#----------------------------------------------------------------------
+# Vector Saturating Shift Left (Signed and Unsigned Integer)
+#----------------------------------------------------------------------
+# CHECK: sqshl v1.8b, v15.8b, v22.8b
+# CHECK: uqshl v2.16b, v14.16b, v23.16b
+# CHECK: sqshl v3.4h, v13.4h, v24.4h
+# CHECK: uqshl v4.8h, v12.8h, v25.8h
+# CHECK: sqshl v5.2s, v11.2s, v26.2s
+# CHECK: uqshl v6.4s, v10.4s, v27.4s
+# CHECK: uqshl v0.2d, v1.2d, v2.2d
+0xe1 0x4d 0x36 0x0e
+0xc2 0x4d 0x37 0x6e
+0xa3 0x4d 0x78 0x0e
+0x84 0x4d 0x79 0x6e
+0x65 0x4d 0xba 0x0e
+0x46 0x4d 0xbb 0x6e
+0x20 0x4c 0xe2 0x6e
+
+#----------------------------------------------------------------------
+# Vector Rouding Shift Left (Signed and Unsigned Integer)
+#----------------------------------------------------------------------
+# CHECK: srshl v10.8b, v5.8b, v22.8b
+# CHECK: urshl v10.16b, v5.16b, v2.16b
+# CHECK: srshl v1.4h, v5.4h, v31.4h
+# CHECK: urshl v1.8h, v5.8h, v2.8h
+# CHECK: srshl v10.2s, v15.2s, v2.2s
+# CHECK: urshl v1.4s, v5.4s, v2.4s
+# CHECK: urshl v0.2d, v1.2d, v2.2d
+0xaa 0x54 0x36 0x0e
+0xaa 0x54 0x22 0x6e
+0xa1 0x54 0x7f 0x0e
+0xa1 0x54 0x62 0x6e
+0xea 0x55 0xa2 0x0e
+0xa1 0x54 0xa2 0x6e
+0x20 0x54 0xe2 0x6e
+
+#----------------------------------------------------------------------
+# Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
+#----------------------------------------------------------------------
+# CHECK: sqrshl v1.8b, v15.8b, v22.8b
+# CHECK: uqrshl v2.16b, v14.16b, v23.16b
+# CHECK: sqrshl v3.4h, v13.4h, v24.4h
+# CHECK: uqrshl v4.8h, v12.8h, v25.8h
+# CHECK: sqrshl v5.2s, v11.2s, v26.2s
+# CHECK: uqrshl v6.4s, v10.4s, v27.4s
+# CHECK: uqrshl v6.4s, v10.4s, v27.4s
+0xe1 0x5d 0x36 0x0e
+0xc2 0x5d 0x37 0x6e
+0xa3 0x5d 0x78 0x0e
+0x84 0x5d 0x79 0x6e
+0x65 0x5d 0xba 0x0e
+0x46 0x5d 0xbb 0x6e
+0x46 0x5d 0xbb 0x6e
+
+#----------------------------------------------------------------------
+# Scalar Integer Shift Left (Signed, Unsigned)
+#----------------------------------------------------------------------
+# CHECK: sshl d31, d31, d31
+# CHECK: ushl d0, d0, d0
+0xff 0x47 0xff 0x5e
+0x00 0x44 0xe0 0x7e
+
+#----------------------------------------------------------------------
+# Scalar Integer Saturating Shift Left (Signed, Unsigned)
+#----------------------------------------------------------------------
+# CHECK: sqshl d31, d31, d31
+# CHECK: uqshl s23, s20, s16
+# CHECK: sqshl h3, h4, h15
+# CHECK: uqshl b11, b20, b30
+0xff 0x4f 0xff 0x5e
+0x97 0x4e 0xb0 0x7e
+0x83 0x4c 0x6f 0x5e
+0x8b 0x4e 0x3e 0x7e
+
+#----------------------------------------------------------------------
+# Scalar Integer Rouding Shift Left (Signed, Unsigned)
+#----------------------------------------------------------------------
+# CHECK: srshl d16, d16, d16
+# CHECK: urshl d8, d7, d4
+0x10 0x56 0xf0 0x5e
+0xe8 0x54 0xe4 0x7e
+
+#----------------------------------------------------------------------
+# Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
+#----------------------------------------------------------------------
+# CHECK: sqrshl d31, d31, d31
+# CHECK: uqrshl s23, s20, s16
+# CHECK: sqrshl h3, h4, h15
+# CHECK: uqrshl b11, b20, b30
+0xff 0x5f 0xff 0x5e
+0x97 0x5e 0xb0 0x7e
+0x83 0x5c 0x6f 0x5e
+0x8b 0x5e 0x3e 0x7e
+
+#----------------------------------------------------------------------
+# Vector Maximum (Signed and Unsigned Integer)
+#----------------------------------------------------------------------
+# CHECK: smax v1.8b, v15.8b, v22.8b
+# CHECK: umax v2.16b, v14.16b, v23.16b
+# CHECK: smax v3.4h, v13.4h, v24.4h
+# CHECK: umax v4.8h, v12.8h, v25.8h
+# CHECK: smax v5.2s, v11.2s, v26.2s
+# CHECK: umax v6.4s, v10.4s, v27.4s
+0xe1 0x65 0x36 0x0e
+0xc2 0x65 0x37 0x6e
+0xa3 0x65 0x78 0x0e
+0x84 0x65 0x79 0x6e
+0x65 0x65 0xba 0x0e
+0x46 0x65 0xbb 0x6e
+
+#----------------------------------------------------------------------
+# Vector Minimum (Signed and Unsigned Integer)
+#----------------------------------------------------------------------
+# CHECK: umin v1.8b, v15.8b, v22.8b
+# CHECK: smin v2.16b, v14.16b, v23.16b
+# CHECK: umin v3.4h, v13.4h, v24.4h
+# CHECK: smin v4.8h, v12.8h, v25.8h
+# CHECK: umin v5.2s, v11.2s, v26.2s
+# CHECK: smin v6.4s, v10.4s, v27.4s
+0xe1 0x6d 0x36 0x2e
+0xc2 0x6d 0x37 0x4e
+0xa3 0x6d 0x78 0x2e
+0x84 0x6d 0x79 0x4e
+0x65 0x6d 0xba 0x2e
+0x46 0x6d 0xbb 0x4e
+
+#----------------------------------------------------------------------
+# Vector Maximum (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fmax v29.2s, v28.2s, v25.2s
+# CHECK: fmax v9.4s, v8.4s, v5.4s
+# CHECK: fmax v11.2d, v10.2d, v7.2d
+0x9d 0xf7 0x39 0x0e
+0x09 0xf5 0x25 0x4e
+0x4b 0xf5 0x67 0x4e
+
+#----------------------------------------------------------------------
+# Vector Minimum (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fmin v29.2s, v28.2s, v25.2s
+# CHECK: fmin v9.4s, v8.4s, v5.4s
+# CHECK: fmin v11.2d, v10.2d, v7.2d
+0x9d 0xf7 0xb9 0x0e
+0x09 0xf5 0xa5 0x4e
+0x4b 0xf5 0xe7 0x4e
+
+#----------------------------------------------------------------------
+# Vector maxNum (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fmaxnm v9.2s, v8.2s, v5.2s
+# CHECK: fmaxnm v9.4s, v8.4s, v5.4s
+# CHECK: fmaxnm v11.2d, v10.2d, v7.2d
+0x09 0xc5 0x25 0x0e
+0x09 0xc5 0x25 0x4e
+0x4b 0xc5 0x67 0x4e
+
+#----------------------------------------------------------------------
+# Vector minNum (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fminnm v2.2s, v8.2s, v25.2s
+# CHECK: fminnm v9.4s, v8.4s, v5.4s
+# CHECK: fminnm v11.2d, v10.2d, v7.2d
+0x02 0xc5 0xb9 0x0e
+0x09 0xc5 0xa5 0x4e
+0x4b 0xc5 0xe7 0x4e
+
+
+#----------------------------------------------------------------------
+# Vector Maximum Pairwise (Signed and Unsigned Integer)
+#----------------------------------------------------------------------
+# CHECK: smaxp v1.8b, v15.8b, v22.8b
+# CHECK: umaxp v2.16b, v14.16b, v23.16b
+# CHECK: smaxp v3.4h, v13.4h, v24.4h
+# CHECK: umaxp v4.8h, v12.8h, v25.8h
+# CHECK: smaxp v5.2s, v11.2s, v26.2s
+# CHECK: umaxp v6.4s, v10.4s, v27.4s
+0xe1 0xa5 0x36 0x0e
+0xc2 0xa5 0x37 0x6e
+0xa3 0xa5 0x78 0x0e
+0x84 0xa5 0x79 0x6e
+0x65 0xa5 0xba 0x0e
+0x46 0xa5 0xbb 0x6e
+
+#----------------------------------------------------------------------
+# Vector Minimum Pairwise (Signed and Unsigned Integer)
+#----------------------------------------------------------------------
+# CHECK: uminp v1.8b, v15.8b, v22.8b
+# CHECK: sminp v2.16b, v14.16b, v23.16b
+# CHECK: uminp v3.4h, v13.4h, v24.4h
+# CHECK: sminp v4.8h, v12.8h, v25.8h
+# CHECK: uminp v5.2s, v11.2s, v26.2s
+# CHECK: sminp v6.4s, v10.4s, v27.4s
+0xe1 0xad 0x36 0x2e
+0xc2 0xad 0x37 0x4e
+0xa3 0xad 0x78 0x2e
+0x84 0xad 0x79 0x4e
+0x65 0xad 0xba 0x2e
+0x46 0xad 0xbb 0x4e
+
+#----------------------------------------------------------------------
+# Vector Maximum Pairwise (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fmaxp v29.2s, v28.2s, v25.2s
+# CHECK: fmaxp v9.4s, v8.4s, v5.4s
+# CHECK: fmaxp v11.2d, v10.2d, v7.2d
+0x9d 0xf7 0x39 0x2e
+0x09 0xf5 0x25 0x6e
+0x4b 0xf5 0x67 0x6e
+
+#----------------------------------------------------------------------
+# Vector Minimum Pairwise (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fminp v29.2s, v28.2s, v25.2s
+# CHECK: fminp v9.4s, v8.4s, v5.4s
+# CHECK: fminp v11.2d, v10.2d, v7.2d
+0x9d 0xf7 0xb9 0x2e
+0x09 0xf5 0xa5 0x6e
+0x4b 0xf5 0xe7 0x6e
+
+#----------------------------------------------------------------------
+# Vector maxNum Pairwise (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fmaxnmp v9.2s, v8.2s, v5.2s
+# CHECK: fmaxnmp v9.4s, v8.4s, v5.4s
+# CHECK: fmaxnmp v11.2d, v10.2d, v7.2d
+0x09 0xc5 0x25 0x2e
+0x09 0xc5 0x25 0x6e
+0x4b 0xc5 0x67 0x6e
+
+#----------------------------------------------------------------------
+# Vector minNum Pairwise (Floating Point)
+#----------------------------------------------------------------------
+# CHECK: fminnmp v2.2s, v8.2s, v25.2s
+# CHECK: fminnmp v9.4s, v8.4s, v5.4s
+# CHECK: fminnmp v11.2d, v10.2d, v7.2d
+0x02 0xc5 0xb9 0x2e
+0x09 0xc5 0xa5 0x6e
+0x4b 0xc5 0xe7 0x6e
+
+#------------------------------------------------------------------------------
+# Vector Add Pairwise (Integer)
+#------------------------------------------------------------------------------
+# CHECK: addp v31.8b, v31.8b, v31.8b
+# CHECK: addp v0.2d, v0.2d, v0.2d
+0xff 0xbf 0x3f 0x0e
+0x00 0xbc 0xe0 0x4e
+
+#------------------------------------------------------------------------------
+# Vector Add Pairwise (Floating Point)
+#------------------------------------------------------------------------------
+# CHECK: faddp v0.4s, v0.4s, v0.4s
+# CHECK: faddp v31.2s, v31.2s, v31.2s
+0x00 0xd4 0x20 0x6e
+0xff 0xd7 0x3f 0x2e
+
+
+#------------------------------------------------------------------------------
+# Vector Saturating Doubling Multiply High
+# Vector Saturating Rouding Doubling Multiply High
+#------------------------------------------------------------------------------
+# CHECK: sqdmulh v31.2s, v31.2s, v31.2s
+# CHECK: sqdmulh v5.4s, v7.4s, v9.4s
+# CHECK: sqrdmulh v31.4h, v3.4h, v13.4h
+# CHECK: sqrdmulh v0.8h, v10.8h, v20.8h
+0xff 0xb7 0xbf 0x0e
+0xe5 0xb4 0xa9 0x4e
+0x7f 0xb4 0x6d 0x2e
+0x40 0xb5 0x74 0x6e
+
+#------------------------------------------------------------------------------
+# Vector Multiply Extended
+#------------------------------------------------------------------------------
+# CHECK: fmulx v1.2s, v22.2s, v2.2s
+# CHECK: fmulx v21.4s, v15.4s, v3.4s
+# CHECK: fmulx v11.2d, v5.2d, v23.2d
+0xc1 0xde 0x22 0x0e
+0xf5 0xdd 0x23 0x4e
+0xab 0xdc 0x77 0x4e
+
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt
index 98daaa7..acc2d9f 100644
--- a/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/test/MC/Disassembler/ARM/arm-tests.txt
@@ -362,7 +362,3 @@
 
 # CHECK: ldmgt	sp!, {r9}
 0x00 0x02 0xbd 0xc8
-
-# CHECK: cdp2	p10, #0, c6, c12, c0, #7
-0xe0 0x6a 0x0c 0xfe
-
diff --git a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt
deleted file mode 100644
index f7acce9..0000000
--- a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# if d == 15 then UNPREDICTABLE;
-0x16 0xf0 0xcf 0xe7
diff --git a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt
deleted file mode 100644
index 356c376..0000000
--- a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# if cond = '1110' then UNDEFINED
-0x6f 0xde
diff --git a/test/MC/Disassembler/ARM/invalid-CPS-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS-arm.txt
deleted file mode 100644
index e447eb6..0000000
--- a/test/MC/Disassembler/ARM/invalid-CPS-arm.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-# CPS: various encodings that are ambiguous with other instructions
-
-# RUN: echo "0x9f 0xff 0x4e 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0x80 0x80 0x2c 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0xce 0x3f 0x28 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0x80 0x00 0x20 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0xa0 0x00 0x00 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
diff --git a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
deleted file mode 100644
index bc8b7e1..0000000
--- a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# invalid imod value (0b01)
-0xc0 0x67 0x4 0xf1
diff --git a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
deleted file mode 100644
index 842a52b..0000000
--- a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding"
-
-# invalid (imod, M, iflags) combination
-0x93 0x00 0x02 0xf1
diff --git a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt b/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt
deleted file mode 100644
index 8396156..0000000
--- a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=1908 Name=t2DMB Format=ARM_FORMAT_THUMBFRM(25)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 0: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST.
-# Reject invalid encodings.
-#
-# See also A8.6.42 DSB
-# All other encodings of option are reserved. It is IMPLEMENTATION DEFINED whether options
-# other than SY are implemented. All unsupported and reserved options must execute as a full
-# system DSB operation, but software must not rely on this behavior.
-0xbf 0xf3 0x51 0x8f
diff --git a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt b/test/MC/Disassembler/ARM/invalid-DSB-arm.txt
deleted file mode 100644
index 2c6e6a7..0000000
--- a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=102 Name=DSB Format=ARM_FORMAT_MISCFRM(26)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 1: 0: 1| 0: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 0: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST.
-# Reject invalid encodings.
-#
-# See also A8.6.42 DSB
-# All other encodings of option are reserved. It is IMPLEMENTATION DEFINED whether options
-# other than SY are implemented. All unsupported and reserved options must execute as a full
-# system DSB operation, but software must not rely on this behavior.
-0x40 0xf0 0x7f 0xf5
diff --git a/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt b/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt
deleted file mode 100644
index 4297c016..0000000
--- a/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding"
-
-# CBZ / CBNZ not allowed in IT block.
-
-0xdb 0xbf 0x42 0xbb
diff --git a/test/MC/Disassembler/ARM/invalid-IT-thumb.txt b/test/MC/Disassembler/ARM/invalid-IT-thumb.txt
deleted file mode 100644
index 1a8ff48..0000000
--- a/test/MC/Disassembler/ARM/invalid-IT-thumb.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown 2>&1 | grep "potentially undefined instruction encoding"
-
-0xff 0xbf 0x6b 0x80 0x00 0x75
diff --git a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt b/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt
deleted file mode 100644
index 6cff09e..0000000
--- a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=0 Name=PHI Format=(42)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined.
-0x92 0xb4 0x1f 0xdc
-
diff --git a/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt
deleted file mode 100644
index 7d8c492..0000000
--- a/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding"
-
-# Writeback is not allowed is Rn is in the target register list.
-
-0xb4 0xe8 0x34 0x04
diff --git a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt
deleted file mode 100644
index 68d22de..0000000
--- a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding"
-
-# Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# if wback && (n == 15 || n == t) then UNPREDICTABLE
-0x05 0x70 0xd7 0xe6
diff --git a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt
deleted file mode 100644
index 4df5309..0000000
--- a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
-# -------------------------------------------------------------------------------------------------
-# 
-# A8.6.66 LDRD (immediate)
-# if Rn = '1111' then SEE LDRD (literal)
-# A8.6.67 LDRD (literal)
-# Inst{21} = 0
-0xff 0xe9 0x0 0xeb
diff --git a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt
deleted file mode 100644
index ecab5a5..0000000
--- a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# LDR_PRE/POST has encoding Inst{4} = 0.
-0xde 0x69 0x18 0x46
diff --git a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt
deleted file mode 100644
index 30cb727..0000000
--- a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding"
-
-# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# if m == 15 then UNPREDICTABLE
-0x8f 0x60 0xb7 0xe7
diff --git a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt
deleted file mode 100644
index 7b7286a..0000000
--- a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# LDR (register) has encoding Inst{4} = 0.
-0xba 0xae 0x9f 0x57
diff --git a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt b/test/MC/Disassembler/ARM/invalid-MCR-arm.txt
deleted file mode 100644
index bb4b06c..0000000
--- a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C
-0x1b 0x1b 0xa0 0x2e
diff --git a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt
deleted file mode 100644
index 528563a..0000000
--- a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# if d == 15 then UNPREDICTABLE
-0x00 0xf0 0x41 0xe3
diff --git a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt
deleted file mode 100644
index 41ec53f..0000000
--- a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=0 Name=PHI Format=(42)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0|
-# -------------------------------------------------------------------------------------------------
-# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
-# The instruction is UNPREDICTABLE, and is not a valid intruction.
-#
-# See also
-# A8.6.97 MOV (register)
-0x2 0xd0 0xbc 0xf1
diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt
deleted file mode 100644
index e5f2a5e..0000000
--- a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1|
-# -------------------------------------------------------------------------------------------------
-# A8.6.89 LSL (register): Inst{7-4} = 0b0001
-0x93 0x42 0xa0 0xd1
diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt
deleted file mode 100644
index 3f4c1e5..0000000
--- a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=0 Name=PHI Format=(42)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0|
-# -------------------------------------------------------------------------------------------------
-# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
-# The instruction is UNPREDICTABLE, and is not a valid intruction.
-#
-# See also
-# A8.6.88 LSL (immediate)
-# A8.6.98 MOV (shifted register), and
-# I.1 Instruction encoding diagrams and pseudocode
-0x2 0xd1 0xbc 0xf1
-
-
diff --git a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt
deleted file mode 100644
index c20ce54..0000000
--- a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
-0x00 0x1a 0x50 0xfc
diff --git a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt
deleted file mode 100644
index 901667a..0000000
--- a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)
-# The hints instructions have more specific encodings, so if mask == 0,
-# we should reject this as an invalid instruction.
-0xa7 0xf1 0x20 0x3
diff --git a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt
deleted file mode 100644
index 499aa86..0000000
--- a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10)
-# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction
-# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction
-0x32 0xb1 0x99 0xf8
diff --git a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt
deleted file mode 100644
index 7bc97d5..0000000
--- a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# if d == 15 || n == 15 then UNPREDICTABLE;
-0x5f 0x54 0xa7 0xe7
diff --git a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt b/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt
deleted file mode 100644
index fe4f43a..0000000
--- a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.167
-# if d == 15 || n == 15 | m == 15 then UNPREDICTABLE
-0x1b 0x68 0xf 0x97
diff --git a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt
deleted file mode 100644
index bf9aac4..0000000
--- a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-# Opcode=0 Name=PHI Format=(42)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1|
-# -------------------------------------------------------------------------------------------------
-# Unknown format
-#
-# B6.1.10 SRS
-# Inst{19-8} = 0xd05
-# Inst{7-5} = 0b000
-# RUN: echo "0x83 0x1c 0xc5 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# RUN: echo "0x00 0x00 0x20 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0xff 0xff 0xaf 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-# RUN: echo "0x13 0x00 0xa0 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
diff --git a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt
deleted file mode 100644
index 3d5235d..0000000
--- a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# if BitCount(registers) < 1 then UNPREDICTABLE
-0x00 0xc7
diff --git a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt b/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt
deleted file mode 100644
index f67f38e..0000000
--- a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.223 SXTB
-# if d == 15 || m == 15 then UNPREDICTABLE;
-0x75 0xf4 0xaf 0xe6
diff --git a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt b/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt
deleted file mode 100644
index f57c48f..0000000
--- a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.244 UMAAL
-# if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
-0x98 0xbf 0x4f 0xf0
diff --git a/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt b/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt
deleted file mode 100644
index 113507c..0000000
--- a/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# A8.8.307: VCVT (between floating-point and fixed-point, AdvSIMD)
-# imm6=0b0xxxxx -> UNDEFINED
-
-# RUN: echo "0x1e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s
-
-# RUN: echo "0x3e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
diff --git a/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt b/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt
deleted file mode 100644
index b76485e..0000000
--- a/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=armv7 2>&1 | grep "invalid instruction encoding"
-
-# invalid imm4 value (0b1xxx)
-# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED;
-0x8f 0xf9 0xf7 0xf2
diff --git a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
deleted file mode 100644
index 00b8526..0000000
--- a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
-
-# Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1|
-# -------------------------------------------------------------------------------------------------
-# 
-# 'a' == 1 and data_size == 8 is invalid
-0x3d 0x3c 0xa0 0xf4
-# CHECK: invalid instruction encoding
diff --git a/test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt
deleted file mode 100644
index 9bb0995..0000000
--- a/test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
-
-0xa0 0xf9 0x10 0x08
-# CHECK: invalid instruction encoding
diff --git a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt
deleted file mode 100644
index 58def05..0000000
--- a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.315 VLD3 (single 3-element structure to all lanes)
-# The a bit must be encoded as 0.
-0xa2 0xf9 0x92 0x2e
diff --git a/test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt
deleted file mode 100644
index 84c98bf..0000000
--- a/test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
-
-0xa0 0xf9 0xc0 0x0f
-# CHECK: invalid instruction encoding
diff --git a/test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt
deleted file mode 100644
index 9024b09..0000000
--- a/test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
-
-0xa0 0xf9 0x30 0x0b
-# CHECK: invalid instruction encoding
diff --git a/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt
deleted file mode 100644
index 54fcadb..0000000
--- a/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# core registers out of range
-0xa5 0xba 0x72 0xed
diff --git a/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt b/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt
deleted file mode 100644
index e363110..0000000
--- a/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt
+++ /dev/null
@@ -1,62 +0,0 @@
-# VST1 multi-element, type == 0b0111, align == 0b10 -> undefined
-# RUN: echo "0xaf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST1 multi-element, type == 0b0111, align == 0b11 -> undefined
-# RUN: echo "0xbf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST1 multi-element, type == 0b1010, align == 0b11 -> undefined
-# RUN: echo "0xbf 0x8a 0x03 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST1 multi-element, type == 0b0110, align == 0b10 -> undefined
-# RUN: echo "0xaf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST1 multi-element, type == 0b0110, align == 0b11 -> undefined
-# RUN: echo "0xbf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
-# RUN: echo "0x4f 0xa8 0x07 0xf7" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
-# RUN: echo "0x4f 0xa9 0x07 0xf7" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST3 multi-element, size = 0b11 -> undefined
-# RUN: echo "0xbf 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST3 multi-element, align = 0b10 -> undefined
-# RUN: echo "0x6f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST3 multi-element, align = 0b11 -> undefined
-# RUN: echo "0x7f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VST4 multi-element, size = 0b11 -> undefined
-# RUN: echo "0xcf 0x50 0x03 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD1 multi-element, type=0b1010 align=0b11
-# RUN: echo "0x24 0xf9 0xbf 0x8a" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD1 multi-element type=0b0111 align=0b1x
-# RUN: echo "0x24 0xf9 0xbf 0x87" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD1 multi-element type=0b0010 align=0b1x
-# RUN: echo "0x24 0xf9 0xbf 0x86" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD2 multi-element size=0b11
-# RUN: echo "0x60 0xf9 0xcf 0x08" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD2 multi-element type=0b1111 align=0b11
-# RUN: echo "0x60 0xf9 0xbf 0x08" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD2 multi-element type=0b1001 align=0b11
-# RUN: echo "0x60 0xf9 0xbf 0x09" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD3 multi-element size=0b11
-# RUN: echo "0x60 0xf9 0x7f 0x04" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD3 multi-element align=0b1x
-# RUN: echo "0x60 0xf9 0xcf 0x04" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# VLD4 multi-element size=0b11
-# RUN: echo "0x60 0xf9 0xcd 0x11" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
-
diff --git a/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt b/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt
deleted file mode 100644
index 9d6cd5c..0000000
--- a/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-# VMOV cmode=0b1111 op=1
-# RUN: echo "0x70 0xef 0xc7 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# VMOV cmode=0b1111 op=1
-# RUN: echo "0x30 0x0f 0x80 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
diff --git a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
deleted file mode 100644
index e8e5d6f..0000000
--- a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
-
-# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# Qm -> bit[0] == 0, otherwise UNDEFINED
-0xdb 0xe0 0x40 0xf2
-# CHECK: invalid instruction encoding
diff --git a/test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt
deleted file mode 100644
index 9462812..0000000
--- a/test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
-
-0x80 0xf9 0x10 0x08
-# CHECK: invalid instruction encoding
diff --git a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt
deleted file mode 100644
index 99da8ce..0000000
--- a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.391 VST1 (multiple single elements)
-# This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128]
-# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list>
-# contains two or four registers.  rdar://11220250
-0x00 0xf9 0x2f 0x06
diff --git a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt
deleted file mode 100644
index 497822a..0000000
--- a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-# Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.393 VST2 (multiple 2-element structures)
-# type == '1001' and align == '11' ==> UNDEFINED
-# RUN: echo "0xb3 0x09 0x03 0xf4" | llvm-mc --disassemble -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
-
-# size == '11' ==> UNDEFINED
-# RUN: echo "0xc3 0x08 0x03 0xf4" | llvm-mc --disassemble -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
-
-# type == '1000' and align == '11' ==> UNDEFINED
-# RUN: echo "0xb3 0x08 0x03 0xf4" | llvm-mc --disassemble -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s
-
-# CHECK: invalid instruction encoding
-
diff --git a/test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt
deleted file mode 100644
index f6e71bc..0000000
--- a/test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s
-
-0x80 0xf9 0x30 0x0b
-# CHECK: invalid instruction encoding
diff --git a/test/MC/Disassembler/ARM/invalid-armv7.txt b/test/MC/Disassembler/ARM/invalid-armv7.txt
new file mode 100644
index 0000000..be79326
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-armv7.txt
@@ -0,0 +1,510 @@
+# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple armv7 2>&1 | FileCheck %s
+
+# This file is checking ARMv7 encodings which are globally invalid, usually due
+# to the constraints of the instructions not being met. For example invalid
+# combinations of registers.
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for bfi
+#------------------------------------------------------------------------------
+
+# Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# if d == 15 then UNPREDICTABLE;
+[0x16 0xf0 0xcf 0xe7]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x16 0xf0 0xcf 0xe7]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for cdp2
+#------------------------------------------------------------------------------
+
+[0xe0 0x6a 0x0c 0xfe]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xe0 0x6a 0x0c 0xfe]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for cps*
+#------------------------------------------------------------------------------
+
+# invalid imod value (0b01)
+[0xc0 0x67 0x4 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xc0 0x67 0x4 0xf1]
+
+# invalid (imod, M, iflags) combination
+[0x93 0x00 0x02 0xf1]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x93 0x00 0x02 0xf1]
+
+# CPS: various encodings that are ambiguous with other instructions
+[0x9f 0xff 0x4e 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x9f 0xff 0x4e 0xf1]
+
+[0x80 0x80 0x2c 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x80 0x80 0x2c 0xf1]
+
+[0xce 0x3f 0x28 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xce 0x3f 0x28 0xf1]
+
+[0x80 0x00 0x20 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x80 0x00 0x20 0xf1]
+
+[0xa0 0x00 0x00 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xa0 0x00 0x00 0xf1]
+
+
+#------------------------------------------------------------------------------
+# Undefined encoding space for hint instructions
+#------------------------------------------------------------------------------
+
+[0x05 0xf0 0x20 0xe3]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x05 0xf0 0x20 0xe3]
+
+[0x41 0xf0 0x20 0xe3]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x41 0xf0 0x20 0xe3]
+
+# FIXME: is it "dbg #14" or not????
+[0xfe 0xf0 0x20 0xe3]
+# CHCK: invalid instruction encoding
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for ldc
+#------------------------------------------------------------------------------
+
+# Opcode=0 Name=PHI Format=(42)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined.
+
+[0x92 0xb4 0x1f 0xdc]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x92 0xb4 0x1f 0xdc]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for ldm
+#------------------------------------------------------------------------------
+
+# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction
+# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction
+
+[0x32 0xb1 0x99 0xf8]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x32 0xb1 0x99 0xf8]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for ldr
+#------------------------------------------------------------------------------
+
+# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# if m == 15 then UNPREDICTABLE
+
+[0x8f 0x60 0xb7 0xe7]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x8f 0x60 0xb7 0xe7]
+
+# LDR (register) has encoding Inst{4} = 0.
+[0xba 0xae 0x9f 0x57]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xba 0xae 0x9f 0x57]
+
+# LDR_PRE/POST has encoding Inst{4} = 0.
+[0xde 0x69 0x18 0x46]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xde 0x69 0x18 0x46]
+
+# Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# if wback && (n == 15 || n == t) then UNPREDICTABLE
+[0x05 0x70 0xd7 0xe6]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x05 0x70 0xd7 0xe6]
+
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for mcr
+#------------------------------------------------------------------------------
+
+# Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C
+
+[0x1b 0x1b 0xa0 0x2e]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x1b 0x1b 0xa0 0x2e]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for mov/lsl
+#------------------------------------------------------------------------------
+
+# Opcode=0 Name=PHI Format=(42)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0|
+# -------------------------------------------------------------------------------------------------
+# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
+# The instruction is UNPREDICTABLE, and is not a valid intruction.
+#
+# See also
+# A8.6.88 LSL (immediate)
+# A8.6.98 MOV (shifted register), and
+# I.1 Instruction encoding diagrams and pseudocode
+
+[0x2 0xd1 0xbc 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x2 0xd1 0xbc 0xf1]
+
+
+# Opcode=0 Name=PHI Format=(42)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0|
+# -------------------------------------------------------------------------------------------------
+# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
+# The instruction is UNPREDICTABLE, and is not a valid intruction.
+#
+# See also
+# A8.6.97 MOV (register)
+
+[0x2 0xd0 0xbc 0xf1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x2 0xd0 0xbc 0xf1]
+
+# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+# A8.6.89 LSL (register): Inst{7-4} = 0b0001
+[0x93 0x42 0xa0 0xd1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x93 0x42 0xa0 0xd1]
+
+# Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# if d == 15 then UNPREDICTABLE
+[0x00 0xf0 0x41 0xe3]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x00 0xf0 0x41 0xe3]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for mrrc2
+#------------------------------------------------------------------------------
+
+[0x00 0x1a 0x50 0xfc]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x00 0x1a 0x50 0xfc]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for msr (imm)
+#------------------------------------------------------------------------------
+
+# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)
+# The hints instructions have more specific encodings, so if mask == 0,
+# we should reject this as an invalid instruction.
+
+[0xa7 0xf1 0x20 0x3]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xa7 0xf1 0x20 0x3]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for sbfx
+#------------------------------------------------------------------------------
+
+# Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# if d == 15 || n == 15 then UNPREDICTABLE;
+
+[0x5f 0x54 0xa7 0xe7]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x5f 0x54 0xa7 0xe7]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for smlad
+#------------------------------------------------------------------------------
+
+# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.167
+# if d == 15 || n == 15 | m == 15 then UNPREDICTABLE
+
+[0x1b 0x68 0xf 0x97]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x1b 0x68 0xf 0x97]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for srs
+#------------------------------------------------------------------------------
+
+# Opcode=0 Name=PHI Format=(42)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+# Unknown format
+#
+# B6.1.10 SRS
+# Inst{19-8} = 0xd05
+# Inst{7-5} = 0b000
+
+[0x83 0x1c 0xc5 0xf8]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x83 0x1c 0xc5 0xf8]
+
+[0x00 0x00 0x20 0xf8]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x00 0x00 0x20 0xf8]
+
+[0xff 0xff 0xaf 0xf8]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xff 0xff 0xaf 0xf8]
+
+[0x13 0x00 0xa0 0xf8]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x13 0x00 0xa0 0xf8]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for sxtb
+#------------------------------------------------------------------------------
+
+# Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.223 SXTB
+# if d == 15 || m == 15 then UNPREDICTABLE;
+
+[0x75 0xf4 0xaf 0xe6]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x75 0xf4 0xaf 0xe6]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON umaal
+#------------------------------------------------------------------------------
+
+# Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.244 UMAAL
+# if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
+[0x98 0xbf 0x4f 0xf0]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x98 0xbf 0x4f 0xf0]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vcvt (float <-> fixed)
+#------------------------------------------------------------------------------
+
+# imm6=0b0xxxxx -> UNDEFINED
+[0x1e 0xcf 0x92 0xf3]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x1e 0xcf 0x92 0xf3]
+
+[0x3e 0xcf 0x92 0xf3]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x3e 0xcf 0x92 0xf3]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vext
+#------------------------------------------------------------------------------
+
+# invalid imm4 value (0b1xxx)
+# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED;
+[0x8f 0xf9 0xf7 0xf2]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x8f 0xf9 0xf7 0xf2]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vldmsdb
+#------------------------------------------------------------------------------
+
+# core registers out of range
+[0xa5 0xba 0x72 0xed]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xa5 0xba 0x72 0xed]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vmov
+#------------------------------------------------------------------------------
+
+# VMOV cmode=0b1111 op=1 is UNDEFINED
+[0x70 0xef 0xc7 0xf3]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x70 0xef 0xc7 0xf3]
+
+#  VMOV cmode=0b1111 op=1 is UNDEFINED
+[0x30 0x0f 0x80 0xf3]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x30 0x0f 0x80 0xf3]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vqadd
+#------------------------------------------------------------------------------
+
+# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# Qm -> bit[0] == 0, otherwise UNDEFINED
+[0xdb 0xe0 0x40 0xf2]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xdb 0xe0 0x40 0xf2]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vld/vst
+#------------------------------------------------------------------------------
+
+# A8.6.393 VST2 (multiple 2-element structures)
+[0xb3 0x09 0x03 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xb3 0x09 0x03 0xf4]
+
+# size == '11' ==> UNDEFINED
+[0xc3 0x08 0x03 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xc3 0x08 0x03 0xf4]
+
+# type == '1000' and align == '11' ==> UNDEFINED
+[0xb3 0x08 0x03 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xb3 0x08 0x03 0xf4]
+
+# VST1 multi-element, type == 0b0111, align == 0b10 -> undefined
+[0xaf 0xb7 0x07 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xaf 0xb7 0x07 0xf4]
+
+# VST1 multi-element, type == 0b0111, align == 0b11 -> undefined
+[0xbf 0xb7 0x07 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xbf 0xb7 0x07 0xf4]
+
+# VST1 multi-element, type == 0b1010, align == 0b11 -> undefined
+[0xbf 0x8a 0x03 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xbf 0x8a 0x03 0xf4]
+
+# VST1 multi-element, type == 0b0110, align == 0b10 -> undefined
+[0xaf 0xb6 0x07 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xaf 0xb6 0x07 0xf4]
+
+# VST1 multi-element, type == 0b0110, align == 0b11 -> undefined
+[0xbf 0xb6 0x07 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xbf 0xb6 0x07 0xf4]
+
+# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
+[0x4f 0xa8 0x07 0xf7]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x4f 0xa8 0x07 0xf7]
+
+# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
+[0x4f 0xa9 0x07 0xf7]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x4f 0xa9 0x07 0xf7]
+
+# VST3 multi-element, size = 0b11 -> undefined
+[0xbf 0xa4 0x0b 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xbf 0xa4 0x0b 0xf4]
+
+# VST3 multi-element, align = 0b10 -> undefined
+[0x6f 0xa4 0x0b 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x6f 0xa4 0x0b 0xf4]
+
+# VST3 multi-element, align = 0b11 -> undefined
+[0x7f 0xa4 0x0b 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x7f 0xa4 0x0b 0xf4]
+
+# VST4 multi-element, size = 0b11 -> undefined
+[0xcf 0x50 0x03 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xcf 0x50 0x03 0xf4]
+
+
+# Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1|
+# -------------------------------------------------------------------------------------------------
+# 
+# 'a' == 1 and data_size == 8 is invalid
+[0x3d 0x3c 0xa0 0xf4]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x3d 0x3c 0xa0 0xf4]
diff --git a/test/MC/Disassembler/ARM/invalid-because-armv7.txt b/test/MC/Disassembler/ARM/invalid-because-armv7.txt
new file mode 100644
index 0000000..4bf4833
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-because-armv7.txt
@@ -0,0 +1,20 @@
+# RUN: not llvm-mc -disassemble -triple armv7 -show-encoding < %s 2>&1 | FileCheck %s
+
+# This file is checking encodings that are valid on some triples, but not on the
+# ARMv7 triple, probably because the relevant instruction is v8, though there
+# could be other reasons.
+
+# Would be vcvtt.f64.f16 d3, s1
+[0xe0 0x3b 0xb2 0xee]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xe0 0x3b 0xb2 0xee]
+
+# Would be vcvtb.f16.f64 s4, d1
+[0x41 0x2b 0xb3 0xee]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x41 0x2b 0xb3 0xee]
+
+# Would be vcvtblt.f16.f64 s4, d1
+[0x41 0x2b 0xb3 0xbe]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x41 0x2b 0xb3 0xbe]
diff --git a/test/MC/Disassembler/ARM/invalid-hint-arm.txt b/test/MC/Disassembler/ARM/invalid-hint-arm.txt
deleted file mode 100644
index 7da96d8..0000000
--- a/test/MC/Disassembler/ARM/invalid-hint-arm.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s 2>&1 | FileCheck %s
-
-#------------------------------------------------------------------------------
-# Undefined encoding space for hint instructions
-#------------------------------------------------------------------------------
-
-0x05 0xf0 0x20 0xe3
-# CHECK: invalid instruction encoding
-0x41 0xf0 0x20 0xe3
-# CHECK: invalid instruction encoding
-0xfe 0xf0 0x20 0xe3
-# CHECK: invalid instruction encoding
-
diff --git a/test/MC/Disassembler/ARM/invalid-hint-thumb.txt b/test/MC/Disassembler/ARM/invalid-hint-thumb.txt
deleted file mode 100644
index 1e41336..0000000
--- a/test/MC/Disassembler/ARM/invalid-hint-thumb.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# RUN: llvm-mc -triple=thumbv7 -disassemble -show-encoding < %s 2>&1 | FileCheck %s
-
-#------------------------------------------------------------------------------
-# Undefined encoding space for hint instructions
-#------------------------------------------------------------------------------
-
-0xaf 0xf3 0x05 0x80
-# CHECK: invalid instruction encoding
diff --git a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt
deleted file mode 100644
index c9f1cf1..0000000
--- a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# A8.6.16 B
-# if cond<3:1> == '111' then SEE "Related Encodings"
-0xaf 0xf7 0x44 0x8b
diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt
deleted file mode 100644
index eb415f7..0000000
--- a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# The unpriviledged Load/Store cannot have SP or PC as Rt.
-0x10 0xf8 0x3 0xfe
diff --git a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt
deleted file mode 100644
index 6c13560..0000000
--- a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-# XFAIL: *
-
-# Opcode=1934 Name=t2LDREXD Format=ARM_FORMAT_THUMBFRM(25)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 1| 0: 0: 1: 0| 1: 0: 0: 0| 1: 0: 0: 0| 0: 1: 1: 1| 1: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-# 
-# if t == t2 then UNPREDICTABLE
-0xd2 0xe8 0x7f 0x88
diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt
deleted file mode 100644
index 7f84e08..0000000
--- a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# if Rt = '1111' then SEE "Unallocated memory hints"
-0xb3 0xf9 0xdf 0xf8
diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt
deleted file mode 100644
index e44cf95..0000000
--- a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints"
-0x35 0xf9 0x00 0xfc
diff --git a/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt
deleted file mode 100644
index 8c0d48b..0000000
--- a/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# SP and PC are not allowed in the register list on STM instructions in Thumb2.
-
-0x2d 0xe9 0xf7 0xb6
diff --git a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt
deleted file mode 100644
index 64ba368..0000000
--- a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-# XFAIL: *
-
-# Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 0| 0: 1: 0: 0| 0: 1: 0: 0| 0: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 0|
-# -------------------------------------------------------------------------------------------------
-# 
-# if wback && (n == t || n == t2) then UNPREDICTABLE
-0xe4 0xe9 0x02 0x46
diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
deleted file mode 100644
index 243c11d..0000000
--- a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-# XFAIL: *
-
-# Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 1: 0|
-# -------------------------------------------------------------------------------------------------
-# 
-# if d == n || d == t then UNPREDICTABLE
-0xc2 0xe8 0x42 0x8f
diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt
deleted file mode 100644
index 7a7c4a5..0000000
--- a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 0: 1: 1: 1| 1: 0: 0: 0| 0: 1: 1: 1| 1: 0: 0: 0|
-# -------------------------------------------------------------------------------------------------
-#
-# if d == n || d == t || d == t2 then UNPREDICTABLE
-mc-input.txt:1:1: warning: invalid instruction encoding
diff --git a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt
deleted file mode 100644
index 2ad3e7d..0000000
--- a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding"
-
-# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25)
-#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
-# -------------------------------------------------------------------------------------------------
-# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1|
-# -------------------------------------------------------------------------------------------------
-#
-# if Rn == '1111' then UNDEFINED
-0x4f 0xf8 0xff 0xeb
diff --git a/test/MC/Disassembler/ARM/invalid-thumbv7-xfail.txt b/test/MC/Disassembler/ARM/invalid-thumbv7-xfail.txt
new file mode 100644
index 0000000..ca5dd65
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-thumbv7-xfail.txt
@@ -0,0 +1,38 @@
+# RUN: llvm-mc -disassemble -triple thumbv7 2>&1 | FileCheck %s
+# XFAIL: *
+
+#------------------------------------------------------------------------------
+# Undefined encodings for ldrexd/strexd
+#------------------------------------------------------------------------------
+
+# FIXME: "ldrexd r8, r8, [r2]"
+# Rt == Rt2 is UNPREDICTABLE
+
+[0xd2 0xe8 0x7f 0x88]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xd2 0xe8 0x7f 0x88]
+
+# Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 1: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# if d == n || d == t then UNPREDICTABLE
+
+[0xc2 0xe8 0x42 0x8f]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xc2 0xe8 0x42 0x8f]
+
+# Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 0: 1: 1: 1| 1: 0: 0: 0| 0: 1: 1: 1| 1: 0: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# if d == n || d == t || d == t2 then UNPREDICTABLE
+
+# FIXME: should be unpredictable since it's "strexd r8, r7, r8, [r2]"
+[0xc2 0xe8 0x78 0x78]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xc2 0xe8 0x78 0x78]
diff --git a/test/MC/Disassembler/ARM/invalid-thumbv7.txt b/test/MC/Disassembler/ARM/invalid-thumbv7.txt
new file mode 100644
index 0000000..f465b3c
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-thumbv7.txt
@@ -0,0 +1,404 @@
+# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s
+
+# This file is checking Thumbv7 encodings which are globally invalid, usually due
+# to the constraints of the instructions not being met. For example invalid
+# combinations of registers.
+
+#------------------------------------------------------------------------------
+# Undefined encoding for b.cc
+#------------------------------------------------------------------------------
+
+# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.16 B
+# if cond<3:1> == '111' then SEE "Related Encodings"
+
+[0xaf 0xf7 0x44 0x8b]
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0xaf 0xf7 0x44 0x8b]
+
+# Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# if cond = '1110' then UNDEFINED
+[0x6f 0xde]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x6f 0xde]
+
+
+#------------------------------------------------------------------------------
+# Undefined encoding space for hint instructions
+#------------------------------------------------------------------------------
+
+[0xaf 0xf3 0x05 0x80]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xaf 0xf3 0x05 0x80]
+
+
+#------------------------------------------------------------------------------
+# Undefined encoding for it
+#------------------------------------------------------------------------------
+
+[0xff 0xbf 0x6b 0x80 0x00 0x75]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xff 0xbf 0x6b 0x80 0x00 0x75]
+
+# mask = 0
+[0x50 0xbf 0x00 0x00]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x50 0xbf 0x00 0x00]
+
+# Two warnings from this block since there are two instructions in there
+[0xdb 0xbf 0x42 0xbb]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb]
+
+#------------------------------------------------------------------------------
+# Undefined encoding for ldm
+#------------------------------------------------------------------------------
+
+# Writeback is not allowed is Rn is in the target register list.
+[0xb4 0xe8 0x34 0x04]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0xb4 0xe8 0x34 0x04]
+
+
+#------------------------------------------------------------------------------
+# Undefined encoding for ldrd
+#------------------------------------------------------------------------------
+
+# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.66 LDRD (immediate)
+# if Rn = '1111' then SEE LDRD (literal)
+# A8.6.67 LDRD (literal)
+# Inst{21} = 0
+
+[0xff 0xe9 0x0 0xeb]
+# CHECK: potentially undefined
+# CHECK-NEXT: [0xff 0xe9 0x0 0xeb]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for ldrbt
+#------------------------------------------------------------------------------
+
+# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# The unpriviledged Load/Store cannot have SP or PC as Rt.
+[0x10 0xf8 0x3 0xfe]
+# CHECK: potentially undefined instruction encoding
+# CHECK-NEXT: [0x10 0xf8 0x3 0xfe]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for ldrsh
+#------------------------------------------------------------------------------
+
+# invalid LDRSHs Rt=PC
+[0x30 0xf9 0x00 0xf0]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x30 0xf9 0x00 0xf0]
+
+# invalid LDRSHi8 Rt=PC
+[0x30 0xf9 0x00 0xfc]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x30 0xf9 0x00 0xfc]
+
+# invalid LDRSHi12 Rt=PC
+[0xb0 0xf9 0x00 0xf0]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xb0 0xf9 0x00 0xf0]
+
+# Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints"
+[0x35 0xf9 0x00 0xfc]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x35 0xf9 0x00 0xfc]
+
+# Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# if Rt = '1111' then SEE "Unallocated memory hints"
+[0xb3 0xf9 0xdf 0xf8]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xb3 0xf9 0xdf 0xf8]
+
+
+#------------------------------------------------------------------------------
+# Undefined encoding for push
+#------------------------------------------------------------------------------
+
+# SP and PC are not allowed in the register list on STM instructions in Thumb2.
+[0x2d 0xe9 0xf7 0xb6]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x2d 0xe9 0xf7 0xb6]
+
+
+#------------------------------------------------------------------------------
+# Undefined encoding for stmia
+#------------------------------------------------------------------------------
+
+# Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# if BitCount(registers) < 1 then UNPREDICTABLE
+[0x00 0xc7]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x00 0xc7]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for str
+#------------------------------------------------------------------------------
+
+# invalid STRi12   Rn=PC
+[0xcf 0xf8 0x00 0x00]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xcf 0xf8 0x00 0x00]
+
+# invalid STRi8    Rn=PC
+[0x4f 0xf8 0x00 0x0c]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x4f 0xf8 0x00 0x0c]
+
+# invalid STRs     Rn=PC
+[0x4f 0xf8 0x00 0x00]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x4f 0xf8 0x00 0x00]
+
+# invalid STRBi12  Rn=PC
+[0x0f 0xf8 0x00 0x00]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x0f 0xf8 0x00 0x00]
+
+# invalid STRBi8   Rn=PC
+[0x0f 0xf8 0x00 0x0c]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x0f 0xf8 0x00 0x0c]
+
+# invalid STRBs    Rn=PC
+[0x0f 0xf8 0x00 0x00]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x0f 0xf8 0x00 0x00]
+
+# invalid STRHi12  Rn=PC
+[0xaf 0xf8 0x00 0x00]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xaf 0xf8 0x00 0x00]
+
+# invalid STRHi8   Rn=PC
+[0x2f 0xf8 0x00 0x0c]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x2f 0xf8 0x00 0x0c]
+
+# invalid STRHs    Rn=PC
+[0x2f 0xf8 0x00 0x00]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x2f 0xf8 0x00 0x00]
+
+# invalid STRBT    Rn=PC
+[0x0f 0xf8 0x00 0x0e]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x0f 0xf8 0x00 0x0e]
+
+# invalid STRHT    Rn=PC
+[0x2f 0xf8 0x00 0x0e]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x2f 0xf8 0x00 0x0e]
+
+# invalid STRT     Rn=PC
+[0x4f 0xf8 0x00 0x0e]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x4f 0xf8 0x00 0x0e]
+
+# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# if Rn == '1111' then UNDEFINED
+
+[0x4f 0xf8 0xff 0xeb]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x4f 0xf8 0xff 0xeb]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for strd
+#------------------------------------------------------------------------------
+
+# Rt == Rn is UNPREDICTABLE
+[0xe4 0xe9 0x02 0x46]
+# CHECK: warning: potentially undefined instruction encoding
+# CHECK-NEXT: [0xe4 0xe9 0x02 0x46]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON/VFP instructions with invalid predicate bits
+#------------------------------------------------------------------------------
+
+# VABS
+[0x40 0xde 0x00 0x0a]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x40 0xde 0x00 0x0a]
+
+
+# VMLA
+[0xf0 0xde 0xe0 0x0b]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xf0 0xde 0xe0 0x0b]
+
+# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110)
+
+# VMOV
+[0x00 0xde 0x10 0x0b]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x00 0xde 0x10 0x0b]
+
+# VDUP
+[0xff 0xde 0xf0 0xfb]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xff 0xde 0xf0 0xfb]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vld instructions
+#------------------------------------------------------------------------------
+
+# size = '00' and index_align == '0001' so UNDEFINED
+[0xa0 0xf9 0x10 0x08]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xa0 0xf9 0x10 0x08]
+
+
+# vld3
+
+# Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.315 VLD3 (single 3-element structure to all lanes)
+# The a bit must be encoded as 0.
+
+[0xa2 0xf9 0x92 0x2e]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xa2 0xf9 0x92 0x2e]
+
+
+# Some vld4 ones
+# size == '11' and a == '0' so UNDEFINED
+[0xa0 0xf9 0xc0 0x0f]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xa0 0xf9 0xc0 0x0f]
+
+[0xa0 0xf9 0x30 0x0b]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xa0 0xf9 0x30 0x0b]
+
+
+# VLD1 multi-element, type=0b1010 align=0b11
+[0x24 0xf9 0xbf 0x8a]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x24 0xf9 0xbf 0x8a]
+
+# VLD1 multi-element type=0b0111 align=0b1x
+[0x24 0xf9 0xbf 0x87]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x24 0xf9 0xbf 0x87]
+
+# VLD1 multi-element type=0b0010 align=0b1x
+[0x24 0xf9 0xbf 0x86]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x24 0xf9 0xbf 0x86]
+
+# VLD2 multi-element size=0b11
+[0x60 0xf9 0xcf 0x08]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x60 0xf9 0xcf 0x08]
+
+# VLD2 multi-element type=0b1111 align=0b11
+[0x60 0xf9 0xbf 0x08]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x60 0xf9 0xbf 0x08]
+
+# VLD2 multi-element type=0b1001 align=0b11
+[0x60 0xf9 0xbf 0x09]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x60 0xf9 0xbf 0x09]
+
+# VLD3 multi-element size=0b11
+[0x60 0xf9 0x7f 0x04]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x60 0xf9 0x7f 0x04]
+
+# VLD3 multi-element align=0b1x
+[0x60 0xf9 0xcf 0x04]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x60 0xf9 0xcf 0x04]
+
+# VLD4 multi-element size=0b11
+[0x60 0xf9 0xcd 0x11]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x60 0xf9 0xcd 0x11]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vst1
+#------------------------------------------------------------------------------
+
+# size == '10' and index_align == '0001' so UNDEFINED
+[0x80 0xf9 0x10 0x08]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x80 0xf9 0x10 0x08]
+
+# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.391 VST1 (multiple single elements)
+# This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128]
+# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list>
+# contains two or four registers.  rdar://11220250
+[0x00 0xf9 0x2f 0x06]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x00 0xf9 0x2f 0x06]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for NEON vst4
+#------------------------------------------------------------------------------
+
+[0x80 0xf9 0x30 0x0b]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x80 0xf9 0x30 0x0b]
diff --git a/test/MC/Disassembler/ARM/neon-v8.txt b/test/MC/Disassembler/ARM/neon-v8.txt
new file mode 100644
index 0000000..8c6e689
--- /dev/null
+++ b/test/MC/Disassembler/ARM/neon-v8.txt
@@ -0,0 +1,71 @@
+# RUN: llvm-mc -triple armv8-unknown-unknown -mattr=+neon -disassemble < %s | FileCheck %s
+
+0x11 0x4f 0x05 0xf3
+# CHECK: vmaxnm.f32 d4, d5, d1
+0x5c 0x4f 0x08 0xf3
+# CHECK: vmaxnm.f32 q2, q4, q6
+0x3e 0x5f 0x24 0xf3
+# CHECK: vminnm.f32 d5, d4, d30
+0xd4 0x0f 0x2a 0xf3
+# CHECK: vminnm.f32 q0, q13, q2
+
+0x06 0x40 0xbb 0xf3
+# CHECK: vcvta.s32.f32	d4, d6
+0x8a 0xc0 0xbb 0xf3
+# CHECK: vcvta.u32.f32	d12, d10
+0x4c 0x80 0xbb 0xf3
+# CHECK: vcvta.s32.f32	q4, q6
+0xe4 0x80 0xbb 0xf3
+# CHECK: vcvta.u32.f32	q4, q10
+
+0x2e 0x13 0xbb 0xf3
+# CHECK: vcvtm.s32.f32	d1, d30
+0x8a 0xc3 0xbb 0xf3
+# CHECK: vcvtm.u32.f32	d12, d10
+0x64 0x23 0xbb 0xf3
+# CHECK: vcvtm.s32.f32	q1, q10
+0xc2 0xa3 0xfb 0xf3
+# CHECK: vcvtm.u32.f32	q13, q1
+
+0x21 0xf1 0xbb 0xf3
+# CHECK: vcvtn.s32.f32	d15, d17
+0x83 0x51 0xbb 0xf3
+# CHECK: vcvtn.u32.f32	d5, d3
+0x60 0x61 0xbb 0xf3
+# CHECK: vcvtn.s32.f32	q3, q8
+0xc6 0xa1 0xbb 0xf3
+# CHECK: vcvtn.u32.f32	q5, q3
+
+0x25 0xb2 0xbb 0xf3
+# CHECK: vcvtp.s32.f32	d11, d21
+0xa7 0xe2 0xbb 0xf3
+# CHECK: vcvtp.u32.f32	d14, d23
+0x6e 0x82 0xbb 0xf3
+# CHECK: vcvtp.s32.f32	q4, q15
+0xe0 0x22 0xfb 0xf3
+# CHECK: vcvtp.u32.f32	q9, q8
+
+0x00 0x34 0xba 0xf3
+# CHECK: vrintn.f32 d3, d0
+0x48 0x24 0xba 0xf3
+# CHECK: vrintn.f32 q1, q4
+0x8c 0x54 0xba 0xf3
+# CHECK: vrintx.f32 d5, d12
+0xc6 0x04 0xba 0xf3
+# CHECK: vrintx.f32 q0, q3
+0x00 0x35 0xba 0xf3
+# CHECK: vrinta.f32 d3, d0
+0x44 0x05 0xfa 0xf3
+# CHECK: vrinta.f32 q8, q2
+0xa2 0xc5 0xba 0xf3
+# CHECK: vrintz.f32 d12, d18
+0xc8 0x25 0xfa 0xf3
+# CHECK: vrintz.f32 q9, q4
+0x80 0x36 0xba 0xf3
+# CHECK: vrintm.f32 d3, d0
+0xc8 0x26 0xba 0xf3
+# CHECK: vrintm.f32 q1, q4
+0x80 0x37 0xba 0xf3
+# CHECK: vrintp.f32 d3, d0
+0xc8 0x27 0xba 0xf3
+# CHECK: vrintp.f32 q1, q4
diff --git a/test/MC/Disassembler/ARM/thumb-neon-v8.txt b/test/MC/Disassembler/ARM/thumb-neon-v8.txt
new file mode 100644
index 0000000..27c09ea
--- /dev/null
+++ b/test/MC/Disassembler/ARM/thumb-neon-v8.txt
@@ -0,0 +1,71 @@
+# RUN: llvm-mc -triple thumbv8-unknown-unknown -mattr=+neon -disassemble < %s | FileCheck %s
+
+0x5 0xff 0x11 0x4f
+# CHECK: vmaxnm.f32 d4, d5, d1
+0x08 0xff 0x5c 0x4f
+# CHECK: vmaxnm.f32 q2, q4, q6
+0x24 0xff 0x3e 0x5f
+# CHECK: vminnm.f32 d5, d4, d30
+0x2a 0xff 0xd4 0x0f
+# CHECK: vminnm.f32 q0, q13, q2
+
+0xbb 0xff 0x06 0x40
+# CHECK: vcvta.s32.f32	d4, d6
+0xbb 0xff 0x8a 0xc0
+# CHECK: vcvta.u32.f32	d12, d10
+0xbb 0xff 0x4c 0x80
+# CHECK: vcvta.s32.f32	q4, q6
+0xbb 0xff 0xe4 0x80
+# CHECK: vcvta.u32.f32	q4, q10
+
+0xbb 0xff 0x2e 0x13
+# CHECK: vcvtm.s32.f32	d1, d30
+0xbb 0xff 0x8a 0xc3
+# CHECK: vcvtm.u32.f32	d12, d10
+0xbb 0xff 0x64 0x23
+# CHECK: vcvtm.s32.f32	q1, q10
+0xfb 0xff 0xc2 0xa3
+# CHECK: vcvtm.u32.f32	q13, q1
+
+0xbb 0xff 0x21 0xf1
+# CHECK: vcvtn.s32.f32	d15, d17
+0xbb 0xff 0x83 0x51
+# CHECK: vcvtn.u32.f32	d5, d3
+0xbb 0xff 0x60 0x61
+# CHECK: vcvtn.s32.f32	q3, q8
+0xbb 0xff 0xc6 0xa1
+# CHECK: vcvtn.u32.f32	q5, q3
+
+0xbb 0xff 0x25 0xb2
+# CHECK: vcvtp.s32.f32	d11, d21
+0xbb 0xff 0xa7 0xe2
+# CHECK: vcvtp.u32.f32	d14, d23
+0xbb 0xff 0x6e 0x82
+# CHECK: vcvtp.s32.f32	q4, q15
+0xfb 0xff 0xe0 0x22
+# CHECK: vcvtp.u32.f32	q9, q8
+
+0xba 0xff 0x00 0x34
+# CHECK: vrintn.f32 d3, d0
+0xba 0xff 0x48 0x24
+# CHECK: vrintn.f32 q1, q4
+0xba 0xff 0x8c 0x54
+# CHECK: vrintx.f32 d5, d12
+0xba 0xff 0xc6 0x04
+# CHECK: vrintx.f32 q0, q3
+0xba 0xff 0x00 0x35
+# CHECK: vrinta.f32 d3, d0
+0xfa 0xff 0x44 0x05
+# CHECK: vrinta.f32 q8, q2
+0xba 0xff 0xa2 0xc5
+# CHECK: vrintz.f32 d12, d18
+0xfa 0xff 0xc8 0x25
+# CHECK: vrintz.f32 q9, q4
+0xba 0xff 0x80 0x36
+# CHECK: vrintm.f32 d3, d0
+0xba 0xff 0xc8 0x26
+# CHECK: vrintm.f32 q1, q4
+0xba 0xff 0x80 0x37
+# CHECK: vrintp.f32 d3, d0
+0xba 0xff 0xc8 0x27
+# CHECK: vrintp.f32 q1, q4
diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt
index 757ce6e..84dd075 100644
--- a/test/MC/Disassembler/ARM/thumb-tests.txt
+++ b/test/MC/Disassembler/ARM/thumb-tests.txt
@@ -221,6 +221,9 @@
 # CHECK:	stc2	p12, c15, [r9], {137}
 0x89 0xfc 0x89 0xfc
 
+# CHECK:	stc2	p0, c0, [r0, #0]!
+0xa0 0xfd 0x00 0x00
+
 # CHECK:	vmov	r1, r0, d11
 0x50 0xec 0x1b 0x1b
 
diff --git a/test/MC/Disassembler/ARM/thumb-v8fp.txt b/test/MC/Disassembler/ARM/thumb-v8fp.txt
new file mode 100644
index 0000000..3457192
--- /dev/null
+++ b/test/MC/Disassembler/ARM/thumb-v8fp.txt
@@ -0,0 +1,163 @@
+# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+v8fp -show-encoding < %s | FileCheck %s
+
+0xb2 0xee 0xe0 0x3b
+# CHECK: vcvtt.f64.f16 d3, s1
+
+0xf3 0xee 0xcc 0x2b
+# CHECK: vcvtt.f16.f64 s5, d12
+
+0xb2 0xee 0x60 0x3b
+# CHECK: vcvtb.f64.f16 d3, s1
+
+0xb3 0xee 0x41 0x2b
+# CHECK: vcvtb.f16.f64 s4, d1
+
+0xa8 0xbf # IT block
+0xb2 0xee 0xe0 0x3b
+# CHECK: vcvttge.f64.f16 d3, s1
+
+0xc8 0xbf # IT block
+0xf3 0xee 0xcc 0x2b
+# CHECK: vcvttgt.f16.f64 s5, d12
+
+0x08 0xbf # IT block
+0xb2 0xee 0x60 0x3b
+# CHECK: vcvtbeq.f64.f16 d3, s1
+
+0xb8 0xbf # IT block
+0xb3 0xee 0x41 0x2b
+# CHECK: vcvtblt.f16.f64 s4, d1
+
+
+0xbc 0xfe 0xe1 0x1a
+# CHECK: vcvta.s32.f32 s2, s3
+
+0xbc 0xfe 0xc3 0x1b
+# CHECK: vcvta.s32.f64 s2, d3
+
+0xbd 0xfe 0xeb 0x3a
+# CHECK: vcvtn.s32.f32 s6, s23
+
+0xbd 0xfe 0xe7 0x3b
+# CHECK: vcvtn.s32.f64 s6, d23
+
+0xbe 0xfe 0xc2 0x0a
+# CHECK: vcvtp.s32.f32 s0, s4
+
+0xbe 0xfe 0xc4 0x0b
+# CHECK: vcvtp.s32.f64 s0, d4
+
+0xff 0xfe 0xc4 0x8a
+# CHECK: vcvtm.s32.f32 s17, s8
+
+0xff 0xfe 0xc8 0x8b
+# CHECK: vcvtm.s32.f64 s17, d8
+
+0xbc 0xfe 0x61 0x1a
+# CHECK: vcvta.u32.f32 s2, s3
+
+0xbc 0xfe 0x43 0x1b
+# CHECK: vcvta.u32.f64 s2, d3
+
+0xbd 0xfe 0x6b 0x3a
+# CHECK: vcvtn.u32.f32 s6, s23
+
+0xbd 0xfe 0x67 0x3b
+# CHECK: vcvtn.u32.f64 s6, d23
+
+0xbe 0xfe 0x42 0x0a
+# CHECK: vcvtp.u32.f32 s0, s4
+
+0xbe 0xfe 0x44 0x0b
+# CHECK: vcvtp.u32.f64 s0, d4
+
+0xff 0xfe 0x44 0x8a
+# CHECK: vcvtm.u32.f32 s17, s8
+
+0xff 0xfe 0x48 0x8b
+# CHECK: vcvtm.u32.f64 s17, d8
+
+
+0x20 0xfe 0xab 0x2a
+# CHECK: vselge.f32 s4, s1, s23
+
+0x6f 0xfe 0xa7 0xeb
+# CHECK: vselge.f64 d30, d31, d23
+
+0x30 0xfe 0x80 0x0a
+# CHECK: vselgt.f32 s0, s1, s0
+
+0x3a 0xfe 0x24 0x5b
+# CHECK: vselgt.f64 d5, d10, d20
+
+0x0e 0xfe 0x2b 0xfa
+# CHECK: vseleq.f32 s30, s28, s23
+
+0x04 0xfe 0x08 0x2b
+# CHECK: vseleq.f64 d2, d4, d8
+
+0x58 0xfe 0x07 0xaa
+# CHECK: vselvs.f32 s21, s16, s14
+
+0x11 0xfe 0x2f 0x0b
+# CHECK: vselvs.f64 d0, d1, d31
+
+
+0xc6 0xfe 0x00 0x2a
+# CHECK: vmaxnm.f32 s5, s12, s0
+
+0x86 0xfe 0xae 0x5b
+# CHECK: vmaxnm.f64 d5, d22, d30
+
+0x80 0xfe 0x46 0x0a
+# CHECK: vminnm.f32 s0, s0, s12
+
+0x86 0xfe 0x49 0x4b
+# CHECK: vminnm.f64 d4, d6, d9
+
+
+0xa8 0xbf # IT block
+0xb6 0xee 0xcc 0x3b
+# CHECK: vrintzge.f64 d3, d12
+
+0xf6 0xee 0xcc 0x1a
+# CHECK: vrintz.f32 s3, s24
+
+0xb8 0xbf # IT block
+0xb6 0xee 0x40 0x5b
+# CHECK: vrintrlt.f64 d5, d0
+
+0xb6 0xee 0x64 0x0a
+# CHECK: vrintr.f32 s0, s9
+
+0x08 0xbf # IT block
+0xf7 0xee 0x6e 0xcb
+# CHECK: vrintxeq.f64 d28, d30
+
+0x68 0xbf # IT block
+0xb7 0xee 0x47 0x5a
+# CHECK: vrintxvs.f32 s10, s14
+
+0xb8 0xfe 0x44 0x3b
+# CHECK: vrinta.f64 d3, d4
+
+0xb8 0xfe 0x60 0x6a
+# CHECK: vrinta.f32 s12, s1
+
+0xb9 0xfe 0x44 0x3b
+# CHECK: vrintn.f64 d3, d4
+
+0xb9 0xfe 0x60 0x6a
+# CHECK: vrintn.f32 s12, s1
+
+0xba 0xfe 0x44 0x3b
+# CHECK: vrintp.f64 d3, d4
+
+0xba 0xfe 0x60 0x6a
+# CHECK: vrintp.f32 s12, s1
+
+0xbb 0xfe 0x44 0x3b
+# CHECK: vrintm.f64 d3, d4
+
+0xbb 0xfe 0x60 0x6a
+# CHECK: vrintm.f32 s12, s1
diff --git a/test/MC/Disassembler/ARM/thumb1.txt b/test/MC/Disassembler/ARM/thumb1.txt
index de9596a..a129abb 100644
--- a/test/MC/Disassembler/ARM/thumb1.txt
+++ b/test/MC/Disassembler/ARM/thumb1.txt
@@ -54,8 +54,12 @@
 #------------------------------------------------------------------------------
 # ADR
 #------------------------------------------------------------------------------
-# CHECK: adr	r2, #3
+# CHECK: adr    r5, #0
+# CHECK: adr    r2, #12
+# CHECK: adr    r3, #1020
+0x00 0xa5
 0x03 0xa2
+0xff 0xa3
 
 #------------------------------------------------------------------------------
 # ASR (immediate)
@@ -279,9 +283,11 @@
 #------------------------------------------------------------------------------
 # CHECK: mov r3, r4
 # CHECK: movs r1, r3
+# CHECK: mov r8, r8
 
 0x23 0x46
 0x19 0x00
+0xc0 0x46
 
 
 #------------------------------------------------------------------------------
@@ -310,14 +316,6 @@
 
 
 #------------------------------------------------------------------------------
-# NOP
-#------------------------------------------------------------------------------
-# CHECK: nop
-
-0xc0 0x46
-
-
-#------------------------------------------------------------------------------
 # ORR
 #------------------------------------------------------------------------------
 # CHECK: orrs  r3, r4
diff --git a/test/MC/Disassembler/ARM/thumb2.txt b/test/MC/Disassembler/ARM/thumb2.txt
index fc237ab..9fc166f 100644
--- a/test/MC/Disassembler/ARM/thumb2.txt
+++ b/test/MC/Disassembler/ARM/thumb2.txt
@@ -170,8 +170,10 @@
 0x13 0xf5 0xce 0xa9
 
 # CHECK: b.w   #208962
+# CHECK: b.w   #-16777216
 
 0x33 0xf0 0x21 0xb8 # rdar://12585795
+0x00 0xf4 0x00 0x90
 
 #------------------------------------------------------------------------------
 # BFC
@@ -551,6 +553,17 @@
 
 
 #------------------------------------------------------------------------------
+# LDR(literal)
+#------------------------------------------------------------------------------
+# CHECK: ldr.w r4, [pc, #-0]
+# CHECK: ldr.w r2, [pc, #-40]
+# CHECK: ldr.w r1, [pc, #1024]
+0x5f 0xf8 0x00 0x40
+0x5f 0xf8 0x28 0x20
+0xdf 0xf8 0x00 0x14
+
+
+#------------------------------------------------------------------------------
 # LDR(register)
 #------------------------------------------------------------------------------
 # CHECK: ldr.w r1, [r8, r1]
@@ -563,6 +576,7 @@
 # CHECK: ldr r2, [r4, #255]!
 # CHECK: ldr r8, [sp, #4]!
 # CHECK: ldr lr, [sp, #-4]!
+# CHECK: ldr lr, [sp, #0]!
 # CHECK: ldr r2, [r4], #255
 # CHECK: ldr r8, [sp], #4
 # CHECK: ldr lr, [sp], #-4
@@ -577,6 +591,7 @@
 0x54 0xf8 0xff 0x2f
 0x5d 0xf8 0x04 0x8f
 0x5d 0xf8 0x04 0xed
+0x5d 0xf8 0x00 0xef
 0x54 0xf8 0xff 0x2b
 0x5d 0xf8 0x04 0x8b
 0x5d 0xf8 0x04 0xe9
@@ -610,6 +625,7 @@
 # CHECK: ldrb r5, [r8, #255]!
 # CHECK: ldrb r2, [r5, #4]!
 # CHECK: ldrb r1, [r4, #-4]!
+# CHECK: ldrb r1, [r4, #0]!
 # CHECK: ldrb lr, [r3], #255
 # CHECK: ldrb r9, [r2], #4
 # CHECK: ldrb r3, [sp], #-4
@@ -623,12 +639,24 @@
 0x18 0xf8 0xff 0x5f
 0x15 0xf8 0x04 0x2f
 0x14 0xf8 0x04 0x1d
+0x14 0xf8 0x00 0x1f
 0x13 0xf8 0xff 0xeb
 0x12 0xf8 0x04 0x9b
 0x1d 0xf8 0x04 0x39
 
 
 #------------------------------------------------------------------------------
+# LDRB(literal)
+#------------------------------------------------------------------------------
+# CHECK: ldrb.w r6, [pc, #-0]
+# CHECK: ldrb.w r10, [pc, #227]
+# CHECK: ldrb.w r5, [pc, #0]
+0x1f 0xf8 0x00 0x60
+0x9f 0xf8 0xe3 0xa0
+0x9f 0xf8 0x00 0x50
+
+
+#------------------------------------------------------------------------------
 # LDRBT
 #------------------------------------------------------------------------------
 # CHECK: ldrbt r1, [r2]
@@ -653,7 +681,9 @@
 # CHECK: ldrd r8, r1, [r3]
 # CHECK: ldrd r0, r1, [r2], #-0
 # CHECK: ldrd r0, r1, [r2, #-0]!
+# CHECK: ldrd r0, r1, [r2, #0]!
 # CHECK: ldrd r0, r1, [r2, #-0]
+# CHECK: ldrd r1, r1, [r0], #0
 
 0xd6 0xe9 0x06 0x35
 0xf6 0xe9 0x06 0x35
@@ -663,7 +693,9 @@
 0xd3 0xe9 0x00 0x81
 0x72 0xe8 0x00 0x01
 0x72 0xe9 0x00 0x01
+0xf2 0xe9 0x00 0x01
 0x52 0xe9 0x00 0x01
+0xf0 0xe8 0x00 0x11
 
 
 #------------------------------------------------------------------------------
@@ -697,14 +729,12 @@
 # CHECK: ldrh.w r5, [r6, #33]
 # CHECK: ldrh.w r5, [r6, #257]
 # CHECK: ldrh.w lr, [r7, #257]
-# CHECK: ldrh.w r0, [pc, #-21]
 
 0x35 0xf8 0x04 0x5c
 0x35 0x8c
 0xb6 0xf8 0x21 0x50
 0xb6 0xf8 0x01 0x51
 0xb7 0xf8 0x01 0xe1
-0x3f 0xf8 0x15 0x00
 
 
 #------------------------------------------------------------------------------
@@ -719,6 +749,7 @@
 # CHECK: ldrh r5, [r8, #255]!
 # CHECK: ldrh r2, [r5, #4]!
 # CHECK: ldrh r1, [r4, #-4]!
+# CHECK: ldrh r1, [r4, #0]!
 # CHECK: ldrh lr, [r3], #255
 # CHECK: ldrh r9, [r2], #4
 # CHECK: ldrh r3, [sp], #-4
@@ -732,12 +763,24 @@
 0x38 0xf8 0xff 0x5f
 0x35 0xf8 0x04 0x2f
 0x34 0xf8 0x04 0x1d
+0x34 0xf8 0x00 0x1f
 0x33 0xf8 0xff 0xeb
 0x32 0xf8 0x04 0x9b
 0x3d 0xf8 0x04 0x39
 
 
 #------------------------------------------------------------------------------
+# LDRH(literal)
+#------------------------------------------------------------------------------
+# CHECK: ldrh.w r7, [pc, #-0]
+# CHECK: ldrh.w r5, [pc, #121]
+# CHECK: ldrh.w r4, [pc, #0]
+0x3f 0xf8 0x00 0x70
+0xbf 0xf8 0x79 0x50
+0xbf 0xf8 0x00 0x40
+
+
+#------------------------------------------------------------------------------
 # LDRSB(immediate)
 #------------------------------------------------------------------------------
 # CHECK: ldrsb r5, [r5, #-4]
@@ -765,6 +808,7 @@
 # CHECK: ldrsb r5, [r8, #255]!
 # CHECK: ldrsb r2, [r5, #4]!
 # CHECK: ldrsb r1, [r4, #-4]!
+# CHECK: ldrsb r1, [r4, #0]!
 # CHECK: ldrsb lr, [r3], #255
 # CHECK: ldrsb r9, [r2], #4
 # CHECK: ldrsb r3, [sp], #-4
@@ -778,12 +822,24 @@
 0x18 0xf9 0xff 0x5f
 0x15 0xf9 0x04 0x2f
 0x14 0xf9 0x04 0x1d
+0x14 0xf9 0x00 0x1f
 0x13 0xf9 0xff 0xeb
 0x12 0xf9 0x04 0x9b
 0x1d 0xf9 0x04 0x39
 
 
 #------------------------------------------------------------------------------
+# LDRSB(literal)
+#------------------------------------------------------------------------------
+# CHECK: ldrsb.w r0, [pc, #-0]
+# CHECK: ldrsb.w r12, [pc, #80]
+# CHECK: ldrsb.w r3, [pc, #0]
+0x1f 0xf9 0x00 0x00
+0x9f 0xf9 0x50 0xc0
+0x9f 0xf9 0x00 0x30
+
+
+#------------------------------------------------------------------------------
 # LDRSBT
 #------------------------------------------------------------------------------
 # CHECK: ldrsbt r1, [r2]
@@ -826,6 +882,7 @@
 # CHECK: ldrsh r5, [r8, #255]!
 # CHECK: ldrsh r2, [r5, #4]!
 # CHECK: ldrsh r1, [r4, #-4]!
+# CHECK: ldrsh r1, [r4, #0]!
 # CHECK: ldrsh lr, [r3], #255
 # CHECK: ldrsh r9, [r2], #4
 # CHECK: ldrsh r3, [sp], #-4
@@ -839,12 +896,24 @@
 0x38 0xf9 0xff 0x5f
 0x35 0xf9 0x04 0x2f
 0x34 0xf9 0x04 0x1d
+0x34 0xf9 0x00 0x1f
 0x33 0xf9 0xff 0xeb
 0x32 0xf9 0x04 0x9b
 0x3d 0xf9 0x04 0x39
 
 
 #------------------------------------------------------------------------------
+# LDRSH(literal)
+#------------------------------------------------------------------------------
+# CHECK: ldrsh.w r0, [pc, #-0]
+# CHECK: ldrsh.w r10, [pc, #-231]
+# CHECK: ldrsh.w r6, [pc, #0]
+0x3f 0xf9 0x00 0x00
+0x3f 0xf9 0xe7 0xa0
+0xbf 0xf9 0x00 0x60
+
+
+#------------------------------------------------------------------------------
 # LDRSHT
 #------------------------------------------------------------------------------
 # CHECK: ldrsht r1, [r2]
@@ -1237,6 +1306,17 @@
 0x1d 0xf8 0x02 0xf0
 
 #------------------------------------------------------------------------------
+# PLD(literal)
+#------------------------------------------------------------------------------
+# CHECK: pld [pc, #-0]
+# CHECK: pld [pc, #455]
+# CHECK: pld [pc, #0]
+
+0x1f 0xf8 0x00 0xf0
+0x9f 0xf8 0xc7 0xf1
+0x9f 0xf8 0x00 0xf0
+
+#------------------------------------------------------------------------------
 # PLI(immediate)
 #------------------------------------------------------------------------------
 # CHECK: pli [r5, #-4]
@@ -1268,6 +1348,17 @@
 0x1d 0xf9 0x12 0xf0
 0x1d 0xf9 0x02 0xf0
 
+#------------------------------------------------------------------------------
+# PLI(literal)
+#------------------------------------------------------------------------------
+# CHECK: pli [pc, #-0]
+# CHECK: pli [pc, #-328]
+# CHECK: pli [pc, #0]
+
+0x1f 0xf9 0x00 0xf0
+0x1f 0xf9 0x48 0xf1
+0x9f 0xf9 0x00 0xf0
+
 
 #------------------------------------------------------------------------------
 # QADD/QADD16/QADD8
@@ -1837,16 +1928,20 @@
 #------------------------------------------------------------------------------
 # STRD (immediate)
 #------------------------------------------------------------------------------
+# CHECK: strd r1, r1, [r0], #0
 # CHECK: strd r6, r3, [r5], #-8
 # CHECK: strd r8, r5, [r5], #-0
 # CHECK: strd r7, r4, [r5], #-4
 # CHECK: strd r0, r1, [r2, #-0]!
+# CHECK: strd r0, r1, [r2, #0]!
 # CHECK: strd r0, r1, [r2, #-0]
 
+0xe0 0xe8 0x00 0x11
 0x65 0xe8 0x02 0x63
 0x65 0xe8 0x00 0x85
 0x65 0xe8 0x01 0x74
 0x62 0xe9 0x00 0x01
+0xe2 0xe9 0x00 0x01
 0x42 0xe9 0x00 0x01
 
 #------------------------------------------------------------------------------
@@ -1878,6 +1973,7 @@
 # CHECK: strh r5, [r8, #255]!
 # CHECK: strh r2, [r5, #4]!
 # CHECK: strh r1, [r4, #-4]!
+# CHECK: strh r1, [r4, #0]!
 # CHECK: strh lr, [r3], #255
 # CHECK: strh r9, [r2], #4
 # CHECK: strh r3, [sp], #-4
@@ -1890,6 +1986,7 @@
 0x28 0xf8 0xff 0x5f
 0x25 0xf8 0x04 0x2f
 0x24 0xf8 0x04 0x1d
+0x24 0xf8 0x00 0x1f
 0x23 0xf8 0xff 0xeb
 0x22 0xf8 0x04 0x9b
 0x2d 0xf8 0x04 0x39
@@ -1954,6 +2051,7 @@
 # CHECK: sub.w r12, r6, #256
 # CHECK: subw r12, r6, #256
 # CHECK: subs.w r1, r2, #496
+# CHECK: subs pc, lr, #4
 
 0x0a 0xbf
 0x11 0x1f
@@ -1965,6 +2063,7 @@
 0xa6 0xf5 0x80 0x7c
 0xa6 0xf2 0x00 0x1c
 0xb2 0xf5 0xf8 0x71
+0xde 0xf3 0x04 0x8f
 
 
 #------------------------------------------------------------------------------
diff --git a/test/MC/Disassembler/ARM/v8fp.txt b/test/MC/Disassembler/ARM/v8fp.txt
new file mode 100644
index 0000000..a6e88b6
--- /dev/null
+++ b/test/MC/Disassembler/ARM/v8fp.txt
@@ -0,0 +1,155 @@
+# RUN: llvm-mc -disassemble -triple armv8 -mattr=+v8fp -show-encoding < %s | FileCheck %s
+
+0xe0 0x3b 0xb2 0xee
+# CHECK: vcvtt.f64.f16 d3, s1
+
+0xcc 0x2b 0xf3 0xee
+# CHECK: vcvtt.f16.f64 s5, d12
+
+0x60 0x3b 0xb2 0xee
+# CHECK: vcvtb.f64.f16 d3, s1
+
+0x41 0x2b 0xb3 0xee
+# CHECK: vcvtb.f16.f64 s4, d1
+
+0xe0 0x3b 0xb2 0xae
+# CHECK: vcvttge.f64.f16 d3, s1
+
+0xcc 0x2b 0xf3 0xce
+# CHECK: vcvttgt.f16.f64 s5, d12
+
+0x60 0x3b 0xb2 0x0e
+# CHECK: vcvtbeq.f64.f16 d3, s1
+
+0x41 0x2b 0xb3 0xbe
+# CHECK: vcvtblt.f16.f64 s4, d1
+
+
+0xe1 0x1a 0xbc 0xfe
+# CHECK: vcvta.s32.f32 s2, s3
+
+0xc3 0x1b 0xbc 0xfe
+# CHECK: vcvta.s32.f64 s2, d3
+
+0xeb 0x3a 0xbd 0xfe
+# CHECK: vcvtn.s32.f32 s6, s23
+
+0xe7 0x3b 0xbd 0xfe
+# CHECK: vcvtn.s32.f64 s6, d23
+
+0xc2 0x0a 0xbe 0xfe
+# CHECK: vcvtp.s32.f32 s0, s4
+
+0xc4 0x0b 0xbe 0xfe
+# CHECK: vcvtp.s32.f64 s0, d4
+
+0xc4 0x8a 0xff 0xfe
+# CHECK: vcvtm.s32.f32 s17, s8
+
+0xc8 0x8b 0xff 0xfe
+# CHECK: vcvtm.s32.f64 s17, d8
+
+0x61 0x1a 0xbc 0xfe
+# CHECK: vcvta.u32.f32 s2, s3
+
+0x43 0x1b 0xbc 0xfe
+# CHECK: vcvta.u32.f64 s2, d3
+
+0x6b 0x3a 0xbd 0xfe
+# CHECK: vcvtn.u32.f32 s6, s23
+
+0x67 0x3b 0xbd 0xfe
+# CHECK: vcvtn.u32.f64 s6, d23
+
+0x42 0x0a 0xbe 0xfe
+# CHECK: vcvtp.u32.f32 s0, s4
+
+0x44 0x0b 0xbe 0xfe
+# CHECK: vcvtp.u32.f64 s0, d4
+
+0x44 0x8a 0xff 0xfe
+# CHECK: vcvtm.u32.f32 s17, s8
+
+0x48 0x8b 0xff 0xfe
+# CHECK: vcvtm.u32.f64 s17, d8
+
+
+0xab 0x2a 0x20 0xfe
+# CHECK: vselge.f32 s4, s1, s23
+
+0xa7 0xeb 0x6f 0xfe
+# CHECK: vselge.f64 d30, d31, d23
+
+0x80 0x0a 0x30 0xfe
+# CHECK: vselgt.f32 s0, s1, s0
+
+0x24 0x5b 0x3a 0xfe
+# CHECK: vselgt.f64 d5, d10, d20
+
+0x2b 0xfa 0x0e 0xfe
+# CHECK: vseleq.f32 s30, s28, s23
+
+0x08 0x2b 0x04 0xfe
+# CHECK: vseleq.f64 d2, d4, d8
+
+0x07 0xaa 0x58 0xfe
+# CHECK: vselvs.f32 s21, s16, s14
+
+0x2f 0x0b 0x11 0xfe
+# CHECK: vselvs.f64 d0, d1, d31
+
+
+0x00 0x2a 0xc6 0xfe
+# CHECK: vmaxnm.f32 s5, s12, s0
+
+0xae 0x5b 0x86 0xfe
+# CHECK: vmaxnm.f64 d5, d22, d30
+
+0x46 0x0a 0x80 0xfe
+# CHECK: vminnm.f32 s0, s0, s12
+
+0x49 0x4b 0x86 0xfe
+# CHECK: vminnm.f64 d4, d6, d9
+
+
+0xcc 0x3b 0xb6 0xae
+# CHECK: vrintzge.f64 d3, d12
+
+0xcc 0x1a 0xf6 0xee
+# CHECK: vrintz.f32 s3, s24
+
+0x40 0x5b 0xb6 0xbe
+# CHECK: vrintrlt.f64 d5, d0
+
+0x64 0x0a 0xb6 0xee
+# CHECK: vrintr.f32 s0, s9
+
+0x6e 0xcb 0xf7 0x0e
+# CHECK: vrintxeq.f64 d28, d30
+
+0x47 0x5a 0xb7 0x6e
+# CHECK: vrintxvs.f32 s10, s14
+
+0x44 0x3b 0xb8 0xfe
+# CHECK: vrinta.f64 d3, d4
+
+0x60 0x6a 0xb8 0xfe
+# CHECK: vrinta.f32 s12, s1
+
+0x44 0x3b 0xb9 0xfe
+# CHECK: vrintn.f64 d3, d4
+
+0x60 0x6a 0xb9 0xfe
+# CHECK: vrintn.f32 s12, s1
+
+0x44 0x3b 0xba 0xfe
+# CHECK: vrintp.f64 d3, d4
+
+0x60 0x6a 0xba 0xfe
+# CHECK: vrintp.f32 s12, s1
+
+0x44 0x3b 0xbb 0xfe
+# CHECK: vrintm.f64 d3, d4
+
+0x60 0x6a 0xbb 0xfe
+# CHECK: vrintm.f32 s12, s1
diff --git a/test/MC/Disassembler/MBlaze/mblaze_branch.txt b/test/MC/Disassembler/MBlaze/mblaze_branch.txt
deleted file mode 100644
index 5f40517..0000000
--- a/test/MC/Disassembler/MBlaze/mblaze_branch.txt
+++ /dev/null
@@ -1,119 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s
-
-################################################################################
-# Branch instructions
-################################################################################
-
-# CHECK:    beq     r2, r3
-0x9c 0x02 0x18 0x00
-
-# CHECK:    bge     r2, r3
-0x9c 0xa2 0x18 0x00
-
-# CHECK:    bgt     r2, r3
-0x9c 0x82 0x18 0x00
-
-# CHECK:    ble     r2, r3
-0x9c 0x62 0x18 0x00
-
-# CHECK:    blt     r2, r3
-0x9c 0x42 0x18 0x00
-
-# CHECK:    bne     r2, r3
-0x9c 0x22 0x18 0x00
-
-# CHECK:    beqd    r2, r3
-0x9e 0x02 0x18 0x00
-
-# CHECK:    bged    r2, r3
-0x9e 0xa2 0x18 0x00
-
-# CHECK:    bgtd    r2, r3
-0x9e 0x82 0x18 0x00
-
-# CHECK:    bled    r2, r3
-0x9e 0x62 0x18 0x00
-
-# CHECK:    bltd    r2, r3
-0x9e 0x42 0x18 0x00
-
-# CHECK:    bned    r2, r3
-0x9e 0x22 0x18 0x00
-
-# CHECK:    br      r3
-0x98 0x00 0x18 0x00
-
-# CHECK:    bra     r3
-0x98 0x08 0x18 0x00
-
-# CHECK:    brd     r3
-0x98 0x10 0x18 0x00
-
-# CHECK:    brad    r3
-0x98 0x18 0x18 0x00
-
-# CHECK:    brld    r15, r3
-0x99 0xf4 0x18 0x00
-
-# CHECK:    brald   r15, r3
-0x99 0xfc 0x18 0x00
-
-# CHECK:    brk     r15, r3
-0x99 0xec 0x18 0x00
-
-# CHECK:    beqi    r2, 0
-0xbc 0x02 0x00 0x00
-
-# CHECK:    bgei    r2, 0
-0xbc 0xa2 0x00 0x00
-
-# CHECK:    bgti    r2, 0
-0xbc 0x82 0x00 0x00
-
- # CHECK:   blei    r2, 0
-0xbc 0x62 0x00 0x00
-
-# CHECK:    blti    r2, 0
-0xbc 0x42 0x00 0x00
-
-# CHECK:    bnei    r2, 0
-0xbc 0x22 0x00 0x00
-
-# CHECK:    beqid   r2, 0
-0xbe 0x02 0x00 0x00
-
-# CHECK:    bgeid   r2, 0
-0xbe 0xa2 0x00 0x00
-
-# CHECK:    bgtid   r2, 0
-0xbe 0x82 0x00 0x00
-
-# CHECK:    bleid   r2, 0
-0xbe 0x62 0x00 0x00
-
-# CHECK:    bltid   r2, 0
-0xbe 0x42 0x00 0x00
-
-# CHECK:    bneid   r2, 0
-0xbe 0x22 0x00 0x00
-
-# CHECK:    bri     0
-0xb8 0x00 0x00 0x00
-
-# CHECK:    brai    0
-0xb8 0x08 0x00 0x00
-
-# CHECK:    brid    0
-0xb8 0x10 0x00 0x00
-
-# CHECK:    braid   0
-0xb8 0x18 0x00 0x00
-
-# CHECK:    brlid   r15, 0
-0xb9 0xf4 0x00 0x00
-
-# CHECK:    bralid  r15, 0
-0xb9 0xfc 0x00 0x00
-
-# CHECK:    brki    r15, 0
-0xb9 0xec 0x00 0x00
diff --git a/test/MC/Disassembler/MBlaze/mblaze_fpu.txt b/test/MC/Disassembler/MBlaze/mblaze_fpu.txt
deleted file mode 100644
index 0fb7abc..0000000
--- a/test/MC/Disassembler/MBlaze/mblaze_fpu.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s
-
-################################################################################
-# FPU instructions
-################################################################################
-
-# CHECK:    fadd         r0, r1, r2
-0x58 0x01 0x10 0x00
-
-# CHECK:    frsub        r0, r1, r2
-0x58 0x01 0x10 0x80
-
-# CHECK:    fmul         r0, r1, r2
-0x58 0x01 0x11 0x00
-
-# CHECK:    fdiv         r0, r1, r2
-0x58 0x01 0x11 0x80
-
-# CHECK:    fsqrt        r0, r1
-0x58 0x01 0x03 0x80
-
-# CHECK:    fint         r0, r1
-0x58 0x01 0x03 0x00
-
-# CHECK:    flt          r0, r1
-0x58 0x01 0x02 0x80
-
-# CHECK:    fcmp.un     r0, r1, r2
-0x58 0x01 0x12 0x00
-
-# CHECK:    fcmp.lt     r0, r1, r2
-0x58 0x01 0x12 0x10
-
-# CHECK:    fcmp.eq     r0, r1, r2
-0x58 0x01 0x12 0x20
-
-# CHECK:    fcmp.le     r0, r1, r2
-0x58 0x01 0x12 0x30
-
-# CHECK:    fcmp.gt     r0, r1, r2
-0x58 0x01 0x12 0x40
-
-# CHECK:    fcmp.ne     r0, r1, r2
-0x58 0x01 0x12 0x50
-
-# CHECK:    fcmp.ge     r0, r1, r2
-0x58 0x01 0x12 0x60
diff --git a/test/MC/Disassembler/MBlaze/mblaze_fsl.txt b/test/MC/Disassembler/MBlaze/mblaze_fsl.txt
deleted file mode 100644
index a12b3b4..0000000
--- a/test/MC/Disassembler/MBlaze/mblaze_fsl.txt
+++ /dev/null
@@ -1,338 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s
-
-################################################################################
-# FSL instructions
-################################################################################
-
-# CHECK:    get         r0, rfsl0
-0x6c 0x00 0x00 0x00
-
-# CHECK:    nget        r0, rfsl0
-0x6c 0x00 0x40 0x00
-
-# CHECK:    cget        r0, rfsl0
-0x6c 0x00 0x20 0x00
-
-# CHECK:    ncget       r0, rfsl0
-0x6c 0x00 0x60 0x00
-
-# CHECK:    tget        r0, rfsl0
-0x6c 0x00 0x10 0x00
-
-# CHECK:    tnget       r0, rfsl0
-0x6c 0x00 0x50 0x00
-
-# CHECK:    tcget       r0, rfsl0
-0x6c 0x00 0x30 0x00
-
-# CHECK:    tncget      r0, rfsl0
-0x6c 0x00 0x70 0x00
-
-# CHECK:    aget        r0, rfsl0
-0x6c 0x00 0x08 0x00
-
-# CHECK:    naget       r0, rfsl0
-0x6c 0x00 0x48 0x00
-
-# CHECK:    caget       r0, rfsl0
-0x6c 0x00 0x28 0x00
-
-# CHECK:    ncaget      r0, rfsl0
-0x6c 0x00 0x68 0x00
-
-# CHECK:    taget       r0, rfsl0
-0x6c 0x00 0x18 0x00
-
-# CHECK:    tnaget      r0, rfsl0
-0x6c 0x00 0x58 0x00
-
-# CHECK:    tcaget      r0, rfsl0
-0x6c 0x00 0x38 0x00
-
-# CHECK:    tncaget     r0, rfsl0
-0x6c 0x00 0x78 0x00
-
-# CHECK:    eget        r0, rfsl0
-0x6c 0x00 0x04 0x00
-
-# CHECK:    neget       r0, rfsl0
-0x6c 0x00 0x44 0x00
-
-# CHECK:    ecget       r0, rfsl0
-0x6c 0x00 0x24 0x00
-
-# CHECK:    necget      r0, rfsl0
-0x6c 0x00 0x64 0x00
-
-# CHECK:    teget       r0, rfsl0
-0x6c 0x00 0x14 0x00
-
-# CHECK:    tneget      r0, rfsl0
-0x6c 0x00 0x54 0x00
-
-# CHECK:    tecget      r0, rfsl0
-0x6c 0x00 0x34 0x00
-
-# CHECK:    tnecget     r0, rfsl0
-0x6c 0x00 0x74 0x00
-
-# CHECK:    eaget       r0, rfsl0
-0x6c 0x00 0x0c 0x00
-
-# CHECK:    neaget      r0, rfsl0
-0x6c 0x00 0x4c 0x00
-
-# CHECK:    ecaget      r0, rfsl0
-0x6c 0x00 0x2c 0x00
-
-# CHECK:    necaget     r0, rfsl0
-0x6c 0x00 0x6c 0x00
-
-# CHECK:    teaget      r0, rfsl0
-0x6c 0x00 0x1c 0x00
-
-# CHECK:    tneaget     r0, rfsl0
-0x6c 0x00 0x5c 0x00
-
-# CHECK:    tecaget     r0, rfsl0
-0x6c 0x00 0x3c 0x00
-
-# CHECK:    tnecaget    r0, rfsl0
-0x6c 0x00 0x7c 0x00
-
-# CHECK:    getd        r0, r1
-0x4c 0x00 0x08 0x00
-
-# CHECK:    ngetd       r0, r1
-0x4c 0x00 0x0a 0x00
-
-# CHECK:    cgetd       r0, r1
-0x4c 0x00 0x09 0x00
-
-# CHECK:    ncgetd      r0, r1
-0x4c 0x00 0x0b 0x00
-
-# CHECK:    tgetd       r0, r1
-0x4c 0x00 0x08 0x80
-
-# CHECK:    tngetd      r0, r1
-0x4c 0x00 0x0a 0x80
-
-# CHECK:    tcgetd      r0, r1
-0x4c 0x00 0x09 0x80
-
-# CHECK:    tncgetd     r0, r1
-0x4c 0x00 0x0b 0x80
-
-# CHECK:    agetd       r0, r1
-0x4c 0x00 0x08 0x40
-
-# CHECK:    nagetd      r0, r1
-0x4c 0x00 0x0a 0x40
-
-# CHECK:    cagetd     r0, r1
-0x4c 0x00 0x09 0x40
-
-# CHECK:    ncagetd     r0, r1
-0x4c 0x00 0x0b 0x40
-
-# CHECK:    tagetd      r0, r1
-0x4c 0x00 0x08 0xc0
-
-# CHECK:    tnagetd     r0, r1
-0x4c 0x00 0x0a 0xc0
-
-# CHECK:    tcagetd     r0, r1
-0x4c 0x00 0x09 0xc0
-
-# CHECK:    tncagetd    r0, r1
-0x4c 0x00 0x0b 0xc0
-
-# CHECK:    egetd       r0, r1
-0x4c 0x00 0x08 0x20
-
-# CHECK:    negetd      r0, r1
-0x4c 0x00 0x0a 0x20
-
-# CHECK:    ecgetd      r0, r1
-0x4c 0x00 0x09 0x20
-
-# CHECK:    necgetd     r0, r1
-0x4c 0x00 0x0b 0x20
-
-# CHECK:    tegetd      r0, r1
-0x4c 0x00 0x08 0xa0
-
-# CHECK:    tnegetd     r0, r1
-0x4c 0x00 0x0a 0xa0
-
-# CHECK:    tecgetd     r0, r1
-0x4c 0x00 0x09 0xa0
-
-# CHECK:    tnecgetd    r0, r1
-0x4c 0x00 0x0b 0xa0
-
-# CHECK:    eagetd      r0, r1
-0x4c 0x00 0x08 0x60
-
-# CHECK:    neagetd     r0, r1
-0x4c 0x00 0x0a 0x60
-
-# CHECK:    ecagetd     r0, r1
-0x4c 0x00 0x09 0x60
-
-# CHECK:    necagetd    r0, r1
-0x4c 0x00 0x0b 0x60
-
-# CHECK:    teagetd     r0, r1
-0x4c 0x00 0x08 0xe0
-
-# CHECK:    tneagetd    r0, r1
-0x4c 0x00 0x0a 0xe0
-
-# CHECK:    tecagetd    r0, r1
-0x4c 0x00 0x09 0xe0
-
-# CHECK:    tnecagetd   r0, r1
-0x4c 0x00 0x0b 0xe0
-
-# CHECK:    put         r0, rfsl0
-0x6c 0x00 0x80 0x00
-
-# CHECK:    aput        r0, rfsl0
-0x6c 0x00 0x88 0x00
-
-# CHECK:    cput        r0, rfsl0
-0x6c 0x00 0xa0 0x00
-
-# CHECK:    caput       r0, rfsl0
-0x6c 0x00 0xa8 0x00
-
-# CHECK:    nput        r0, rfsl0
-0x6c 0x00 0xc0 0x00
-
-# CHECK:    naput       r0, rfsl0
-0x6c 0x00 0xc8 0x00
-
-# CHECK:    ncput       r0, rfsl0
-0x6c 0x00 0xe0 0x00
-
-# CHECK:    ncaput      r0, rfsl0
-0x6c 0x00 0xe8 0x00
-
-# CHECK:    tput        rfsl0
-0x6c 0x00 0x90 0x00
-
-# CHECK:    taput       rfsl0
-0x6c 0x00 0x98 0x00
-
-# CHECK:    tcput       rfsl0
-0x6c 0x00 0xb0 0x00
-
-# CHECK:    tcaput      rfsl0
-0x6c 0x00 0xb8 0x00
-
-# CHECK:    tnput       rfsl0
-0x6c 0x00 0xd0 0x00
-
-# CHECK:    tnaput      rfsl0
-0x6c 0x00 0xd8 0x00
-
-# CHECK:    tncput      rfsl0
-0x6c 0x00 0xf0 0x00
-
-# CHECK:    tncaput     rfsl0
-0x6c 0x00 0xf8 0x00
-
-# CHECK:    putd        r0, r1
-0x4c 0x00 0x0c 0x00
-
-# CHECK:    aputd       r0, r1
-0x4c 0x00 0x0c 0x40
-
-# CHECK:    cputd       r0, r1
-0x4c 0x00 0x0d 0x00
-
-# CHECK:    caputd      r0, r1
-0x4c 0x00 0x0d 0x40
-
-# CHECK:    nputd       r0, r1
-0x4c 0x00 0x0e 0x00
-
-# CHECK:    naputd      r0, r1
-0x4c 0x00 0x0e 0x40
-
-# CHECK:    ncputd      r0, r1
-0x4c 0x00 0x0f 0x00
-
-# CHECK:    ncaputd     r0, r1
-0x4c 0x00 0x0f 0x40
-
-# CHECK:    tputd       r1
-0x4c 0x00 0x0c 0x80
-
-# CHECK:    taputd      r1
-0x4c 0x00 0x0c 0xc0
-
-# CHECK:    tcputd      r1
-0x4c 0x00 0x0d 0x80
-
-# CHECK:    tcaputd     r1
-0x4c 0x00 0x0d 0xc0
-
-# CHECK:    tnputd      r1
-0x4c 0x00 0x0e 0x80
-
-# CHECK:    tnaputd     r1
-0x4c 0x00 0x0e 0xc0
-
-# CHECK:    tncputd     r1
-0x4c 0x00 0x0f 0x80
-
-# CHECK:    tncaputd    r1
-0x4c 0x00 0x0f 0xc0
-
-# CHECK:    get     r0, rfsl1
-0x6c 0x00 0x00 0x01
-
-# CHECK:    get     r0, rfsl2
-0x6c 0x00 0x00 0x02
-
-# CHECK:    get     r0, rfsl3
-0x6c 0x00 0x00 0x03
-
-# CHECK:    get     r0, rfsl4
-0x6c 0x00 0x00 0x04
-
-# CHECK:    get     r0, rfsl5
-0x6c 0x00 0x00 0x05
-
-# CHECK:    get     r0, rfsl6
-0x6c 0x00 0x00 0x06
-
-# CHECK:    get     r0, rfsl7
-0x6c 0x00 0x00 0x07
-
-# CHECK:    get     r0, rfsl8
-0x6c 0x00 0x00 0x08
-
-# CHECK:    get     r0, rfsl9
-0x6c 0x00 0x00 0x09
-
-# CHECK:    get     r0, rfsl10
-0x6c 0x00 0x00 0x0a
-
-# CHECK:    get     r0, rfsl11
-0x6c 0x00 0x00 0x0b
-
-# CHECK:    get     r0, rfsl12
-0x6c 0x00 0x00 0x0c
-
-# CHECK:    get     r0, rfsl13
-0x6c 0x00 0x00 0x0d
-
-# CHECK:    get     r0, rfsl14
-0x6c 0x00 0x00 0x0e
-
-# CHECK:    get     r0, rfsl15
-0x6c 0x00 0x00 0x0f
diff --git a/test/MC/Disassembler/MBlaze/mblaze_imm.txt b/test/MC/Disassembler/MBlaze/mblaze_imm.txt
deleted file mode 100644
index 3833ea8..0000000
--- a/test/MC/Disassembler/MBlaze/mblaze_imm.txt
+++ /dev/null
@@ -1,121 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s
-
-################################################################################
-# IMM instruction processing
-################################################################################
-
-# CHECK:    addi    r0, r0, 0
-0x20 0x00 0x00 0x00
-
-# CHECK:    addi    r0, r0, 1
-0x20 0x00 0x00 0x01
-
-# CHECK:    addi    r0, r0, 2
-0x20 0x00 0x00 0x02
-
-# CHECK:    addi    r0, r0, 4
-0x20 0x00 0x00 0x04
-
-# CHECK:    addi    r0, r0, 8
-0x20 0x00 0x00 0x08
-
-# CHECK:    addi    r0, r0, 16
-0x20 0x00 0x00 0x10
-
-# CHECK:    addi    r0, r0, 32
-0x20 0x00 0x00 0x20
-
-# CHECK:    addi    r0, r0, 64
-0x20 0x00 0x00 0x40
-
-# CHECK:    addi    r0, r0, 128
-0x20 0x00 0x00 0x80
-
-# CHECK:    addi    r0, r0, 256
-0x20 0x00 0x01 0x00
-
-# CHECK:    addi    r0, r0, 512
-0x20 0x00 0x02 0x00
-
-# CHECK:    addi    r0, r0, 1024
-0x20 0x00 0x04 0x00
-
-# CHECK:    addi    r0, r0, 2048
-0x20 0x00 0x08 0x00
-
-# CHECK:    addi    r0, r0, 4096
-0x20 0x00 0x10 0x00
-
-# CHECK:    addi    r0, r0, 8192
-0x20 0x00 0x20 0x00
-
-# CHECK:    addi    r0, r0, 16384
-0x20 0x00 0x40 0x00
-
-# CHECK:    imm     0
-# CHECK:    addi    r0, r0, -32768
-0xb0 0x00 0x00 0x00 0x20 0x00 0x80 0x00
-
-# CHECK:    imm     1
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x00 0x01 0x20 0x00 0x00 0x00
-
-# CHECK:    imm     2
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x00 0x02 0x20 0x00 0x00 0x00
-
-# CHECK:    imm     4
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x00 0x04 0x20 0x00 0x00 0x00
-
-# CHECK:    imm     8
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x00 0x08 0x20 0x00 0x00 0x00
-
-# CHECK:    imm     16
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x00 0x10 0x20 0x00 0x00 0x00
-
-# CHECK:    imm     32
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x00 0x20 0x20 0x00 0x00 0x00
-
-# CHECK:    imm     64
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x00 0x40 0x20 0x00 0x00 0x00
-
-# CHECK:    imm     128
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x00 0x80 0x20 0x00 0x00 0x00
-
-# CHECK:    imm     256
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x01 0x00 0x20 0x00 0x00 0x00
-
-# CHECK:    imm     512
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x02 0x00 0x20 0x00 0x00 0x00
-
-# CHECK:    imm     1024
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x04 0x00 0x20 0x00 0x00 0x00
-
-# CHECK:    imm     2048
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x08 0x00 0x20 0x00 0x00 0x00
-
-# CHECK:    imm     4096
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x10 0x00 0x20 0x00 0x00 0x00
-
-# CHECK:    imm     8192
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x20 0x00 0x20 0x00 0x00 0x00
-
-# CHECK:    imm     16384
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x40 0x00 0x20 0x00 0x00 0x00
-
-# CHECK:    imm     -32768
-# CHECK:    addi    r0, r0, 0
-0xb0 0x00 0x80 0x00 0x20 0x00 0x00 0x00
diff --git a/test/MC/Disassembler/MBlaze/mblaze_mbar.txt b/test/MC/Disassembler/MBlaze/mblaze_mbar.txt
deleted file mode 100644
index 6beba86..0000000
--- a/test/MC/Disassembler/MBlaze/mblaze_mbar.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s
-
-################################################################################
-# Memory Barrier instructions
-################################################################################
-
-# CHECK:    mbar        0
-0xB8 0x02 0x00 0x04
-
-# CHECK:    mbar        1
-0xB8 0x22 0x00 0x04
-
-# CHECK:    mbar        2
-0xB8 0x42 0x00 0x04
diff --git a/test/MC/Disassembler/MBlaze/mblaze_memory.txt b/test/MC/Disassembler/MBlaze/mblaze_memory.txt
deleted file mode 100644
index 584d61c..0000000
--- a/test/MC/Disassembler/MBlaze/mblaze_memory.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s
-
-################################################################################
-# Memory instructions
-################################################################################
-
-# CHECK:    lbu     r1, r2, r3
-0xc0 0x22 0x18 0x00
-
-# CHECK:    lbur    r1, r2, r3
-0xc0 0x22 0x1a 0x00
-
-# CHECK:    lbui    r1, r2, 28
-0xe0 0x22 0x00 0x1c
-
-# CHECK:    lhu     r1, r2, r3
-0xc4 0x22 0x18 0x00
-
-# CHECK:    lhur    r1, r2, r3
-0xc4 0x22 0x1a 0x00
-
-# CHECK:    lhui    r1, r2, 28
-0xe4 0x22 0x00 0x1c
-
-# CHECK:    lw      r1, r2, r3
-0xc8 0x22 0x18 0x00
-
-# CHECK:    lwr    r1, r2, r3
-0xc8 0x22 0x1a 0x00
-
-# CHECK:    lwi     r1, r2, 28
-0xe8 0x22 0x00 0x1c
-
-# CHECK:    lwx      r1, r2, r3
-0xc8 0x22 0x1c 0x00
-
-# CHECK:    sb      r1, r2, r3
-0xd0 0x22 0x18 0x00
-
-# CHECK:    sbr     r1, r2, r3
-0xd0 0x22 0x1a 0x00
-
-# CHECK:    sbi     r1, r2, 28
-0xf0 0x22 0x00 0x1c
-
-# CHECK:    sh      r1, r2, r3
-0xd4 0x22 0x18 0x00
-
-# CHECK:    shr     r1, r2, r3
-0xd4 0x22 0x1a 0x00
-
-# CHECK:    shi     r1, r2, 28
-0xf4 0x22 0x00 0x1c
-
-# CHECK:    sw      r1, r2, r3
-0xd8 0x22 0x18 0x00
-
-# CHECK:    swr    r1, r2, r3
-0xd8 0x22 0x1a 0x00
-
-# CHECK:    swi     r1, r2, 28
-0xf8 0x22 0x00 0x1c
-
-# CHECK:    swx      r1, r2, r3
-0xd8 0x22 0x1c 0x00
diff --git a/test/MC/Disassembler/MBlaze/mblaze_operands.txt b/test/MC/Disassembler/MBlaze/mblaze_operands.txt
deleted file mode 100644
index f0304b1..0000000
--- a/test/MC/Disassembler/MBlaze/mblaze_operands.txt
+++ /dev/null
@@ -1,197 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s
-
-################################################################################
-# Operands disassembly
-################################################################################
-
-# CHECK:    add     r0, r0, r0
-0x00 0x00 0x00 0x00
-
-# CHECK:    add     r1, r1, r1
-0x00 0x21 0x08 0x00
-
-# CHECK:    add     r2, r2, r2
-0x00 0x42 0x10 0x00
-
-# CHECK:    add     r3, r3, r3
-0x00 0x63 0x18 0x00
-
-# CHECK:    add     r4, r4, r4
-0x00 0x84 0x20 0x00
-
-# CHECK:    add     r5, r5, r5
-0x00 0xa5 0x28 0x00
-
-# CHECK:    add     r6, r6, r6
-0x00 0xc6 0x30 0x00
-
-# CHECK:    add     r7, r7, r7
-0x00 0xe7 0x38 0x00
-
-# CHECK:    add     r8, r8, r8
-0x01 0x08 0x40 0x00
-
-# CHECK:    add     r9, r9, r9
-0x01 0x29 0x48 0x00
-
-# CHECK:    add     r10, r10, r10
-0x01 0x4a 0x50 0x00
-
-# CHECK:    add     r11, r11, r11
-0x01 0x6b 0x58 0x00
-
-# CHECK:    add     r12, r12, r12
-0x01 0x8c 0x60 0x00
-
-# CHECK:    add     r13, r13, r13
-0x01 0xad 0x68 0x00
-
-# CHECK:    add     r14, r14, r14
-0x01 0xce 0x70 0x00
-
-# CHECK:    add     r15, r15, r15
-0x01 0xef 0x78 0x00
-
-# CHECK:    add     r16, r16, r16
-0x02 0x10 0x80 0x00
-
-# CHECK:    add     r17, r17, r17
-0x02 0x31 0x88 0x00
-
-# CHECK:    add     r18, r18, r18
-0x02 0x52 0x90 0x00
-
-# CHECK:    add     r19, r19, r19
-0x02 0x73 0x98 0x00
-
-# CHECK:    add     r20, r20, r20
-0x02 0x94 0xa0 0x00
-
-# CHECK:    add     r21, r21, r21
-0x02 0xb5 0xa8 0x00
-
-# CHECK:    add     r22, r22, r22
-0x02 0xd6 0xb0 0x00
-
-# CHECK:    add     r23, r23, r23
-0x02 0xf7 0xb8 0x00
-
-# CHECK:    add     r24, r24, r24
-0x03 0x18 0xc0 0x00
-
-# CHECK:    add     r25, r25, r25
-0x03 0x39 0xc8 0x00
-
-# CHECK:    add     r26, r26, r26
-0x03 0x5a 0xd0 0x00
-
-# CHECK:    add     r27, r27, r27
-0x03 0x7b 0xd8 0x00
-
-# CHECK:    add     r28, r28, r28
-0x03 0x9c 0xe0 0x00
-
-# CHECK:    add     r29, r29, r29
-0x03 0xbd 0xe8 0x00
-
-# CHECK:    add     r30, r30, r30
-0x03 0xde 0xf0 0x00
-
-# CHECK:    add     r31, r31, r31
-0x03 0xff 0xf8 0x00
-
-# CHECK:    addi    r0, r0, 0
-0x20 0x00 0x00 0x00
-
-# CHECK:    addi    r0, r0, 1
-0x20 0x00 0x00 0x01
-
-# CHECK:    addi    r0, r0, 2
-0x20 0x00 0x00 0x02
-
-# CHECK:    addi    r0, r0, 4
-0x20 0x00 0x00 0x04
-
-# CHECK:    addi    r0, r0, 8
-0x20 0x00 0x00 0x08
-
-# CHECK:    addi    r0, r0, 16
-0x20 0x00 0x00 0x10
-
-# CHECK:    addi    r0, r0, 32
-0x20 0x00 0x00 0x20
-
-# CHECK:    addi    r0, r0, 64
-0x20 0x00 0x00 0x40
-
-# CHECK:    addi    r0, r0, 128
-0x20 0x00 0x00 0x80
-
-# CHECK:    addi    r0, r0, 256
-0x20 0x00 0x01 0x00
-
-# CHECK:    addi    r0, r0, 512
-0x20 0x00 0x02 0x00
-
-# CHECK:    addi    r0, r0, 1024
-0x20 0x00 0x04 0x00
-
-# CHECK:    addi    r0, r0, 2048
-0x20 0x00 0x08 0x00
-
-# CHECK:    addi    r0, r0, 4096
-0x20 0x00 0x10 0x00
-
-# CHECK:    addi    r0, r0, 8192
-0x20 0x00 0x20 0x00
-
-# CHECK:    addi    r0, r0, 16384
-0x20 0x00 0x40 0x00
-
-# CHECK:    addi    r0, r0, -1
-0x20 0x00 0xff 0xff
-
-# CHECK:    addi    r0, r0, -2
-0x20 0x00 0xff 0xfe
-
-# CHECK:    addi    r0, r0, -4
-0x20 0x00 0xff 0xfc
-
-# CHECK:    addi    r0, r0, -8
-0x20 0x00 0xff 0xf8
-
-# CHECK:    addi    r0, r0, -16
-0x20 0x00 0xff 0xf0
-
-# CHECK:    addi    r0, r0, -32
-0x20 0x00 0xff 0xe0
-
-# CHECK:    addi    r0, r0, -64
-0x20 0x00 0xff 0xc0
-
-# CHECK:    addi    r0, r0, -128
-0x20 0x00 0xff 0x80
-
-# CHECK:    addi    r0, r0, -256
-0x20 0x00 0xff 0x00
-
-# CHECK:    addi    r0, r0, -512
-0x20 0x00 0xfe 0x00
-
-# CHECK:    addi    r0, r0, -1024
-0x20 0x00 0xfc 0x00
-
-# CHECK:    addi    r0, r0, -2048
-0x20 0x00 0xf8 0x00
-
-# CHECK:    addi    r0, r0, -4096
-0x20 0x00 0xf0 0x00
-
-# CHECK:    addi    r0, r0, -8192
-0x20 0x00 0xe0 0x00
-
-# CHECK:    addi    r0, r0, -16384
-0x20 0x00 0xc0 0x00
-
-# CHECK:    addi    r0, r0, -32768
-0x20 0x00 0x80 0x00
diff --git a/test/MC/Disassembler/MBlaze/mblaze_pattern.txt b/test/MC/Disassembler/MBlaze/mblaze_pattern.txt
deleted file mode 100644
index cb19ee0..0000000
--- a/test/MC/Disassembler/MBlaze/mblaze_pattern.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s
-
-################################################################################
-# Pattern instructions
-################################################################################
-
-# CHECK:    pcmpbf      r0, r1, r2
-0x80 0x01 0x14 0x00
-
-# CHECK:    pcmpne      r0, r1, r2
-0x8c 0x01 0x14 0x00
-
-# CHECK:    pcmpeq      r0, r1, r2
-0x88 0x01 0x14 0x00
-
-# CHECK:    clz         r0, r1
-0x90 0x01 0x00 0xE0
diff --git a/test/MC/Disassembler/MBlaze/mblaze_shift.txt b/test/MC/Disassembler/MBlaze/mblaze_shift.txt
deleted file mode 100644
index 2783ffc..0000000
--- a/test/MC/Disassembler/MBlaze/mblaze_shift.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s
-
-################################################################################
-# Shift instructions
-################################################################################
-
-# CHECK:    bsrl    r1, r2, r3
-0x44 0x22 0x18 0x00
-
-# CHECK:    bsra    r1, r2, r3
-0x44 0x22 0x1a 0x00
-
-# CHECK:    bsll    r1, r2, r3
-0x44 0x22 0x1c 0x00
-
-# CHECK:    bsrli   r1, r2, 0
-0x64 0x22 0x00 0x00
-
-# CHECK:    bsrai   r1, r2, 0
-0x64 0x22 0x02 0x00
-
-# CHECK:    bslli   r1, r2, 0
-0x64 0x22 0x04 0x00
-
-# CHECK:    sra     r1, r2
-0x90 0x22 0x00 0x01
-
-# CHECK:    srl     r1, r2
-0x90 0x22 0x00 0x41
diff --git a/test/MC/Disassembler/MBlaze/mblaze_special.txt b/test/MC/Disassembler/MBlaze/mblaze_special.txt
deleted file mode 100644
index a808cc9..0000000
--- a/test/MC/Disassembler/MBlaze/mblaze_special.txt
+++ /dev/null
@@ -1,105 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s
-
-################################################################################
-# Special instructions
-################################################################################
-
-# CHECK:    mfs         r0, rpc
-0x94 0x00 0x80 0x00
-
-# CHECK:    msrclr      r0, 0
-0x94 0x11 0x00 0x00
-
-# CHECK:    msrset      r0, 0
-0x94 0x10 0x00 0x00
-
-# CHECK:    mts         rpc, r0
-0x94 0x00 0xc0 0x00
-
-# CHECK:    wdc         r0, r1
-0x90 0x00 0x08 0x64
-
-# CHECK:    wdc.clear   r0, r1
-0x90 0x00 0x08 0x66
-
-# CHECK:    wdc.flush   r0, r1
-0x90 0x00 0x08 0x74
-
-# CHECK:    wic         r0, r1
-0x90 0x00 0x08 0x68
-
-################################################################################
-# Special registers
-################################################################################
-
-# CHECK:    mfs         r1, rpc
-0x94 0x20 0x80 0x00
-
-# CHECK:    mfs         r1, rmsr
-0x94 0x20 0x80 0x01
-
-# CHECK:    mfs         r1, rear
-0x94 0x20 0x80 0x03
-
-# CHECK:    mfs         r1, resr
-0x94 0x20 0x80 0x05
-
-# CHECK:    mfs         r1, rfsr
-0x94 0x20 0x80 0x07
-
-# CHECK:    mfs         r1, rbtr
-0x94 0x20 0x80 0x0b
-
-# CHECK:    mfs         r1, redr
-0x94 0x20 0x80 0x0d
-
-# CHECK:    mfs         r1, rpid
-0x94 0x20 0x90 0x00
-
-# CHECK:    mfs         r1, rzpr
-0x94 0x20 0x90 0x01
-
-# CHECK:    mfs         r1, rtlbx
-0x94 0x20 0x90 0x02
-
-# CHECK:    mfs         r1, rtlbhi
-0x94 0x20 0x90 0x04
-
-# CHECK:    mfs         r1, rtlblo
-0x94 0x20 0x90 0x03
-
-# CHECK:    mfs         r1, rpvr0
-0x94 0x20 0xa0 0x00
-
-# CHECK:    mfs         r1, rpvr1
-0x94 0x20 0xa0 0x01
-
-# CHECK:    mfs         r1, rpvr2
-0x94 0x20 0xa0 0x02
-
-# CHECK:    mfs         r1, rpvr3
-0x94 0x20 0xa0 0x03
-
-# CHECK:    mfs         r1, rpvr4
-0x94 0x20 0xa0 0x04
-
-# CHECK:    mfs         r1, rpvr5
-0x94 0x20 0xa0 0x05
-
-# CHECK:    mfs         r1, rpvr6
-0x94 0x20 0xa0 0x06
-
-# CHECK:    mfs         r1, rpvr7
-0x94 0x20 0xa0 0x07
-
-# CHECK:    mfs         r1, rpvr8
-0x94 0x20 0xa0 0x08
-
-# CHECK:    mfs         r1, rpvr9
-0x94 0x20 0xa0 0x09
-
-# CHECK:    mfs         r1, rpvr10
-0x94 0x20 0xa0 0x0a
-
-# CHECK:    mfs         r1, rpvr11
-0x94 0x20 0xa0 0x0b
diff --git a/test/MC/Disassembler/MBlaze/mblaze_typea.txt b/test/MC/Disassembler/MBlaze/mblaze_typea.txt
deleted file mode 100644
index ce99950..0000000
--- a/test/MC/Disassembler/MBlaze/mblaze_typea.txt
+++ /dev/null
@@ -1,74 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s
-
-################################################################################
-# TYPE A instructions
-################################################################################
-
-# CHECK:    add     r1, r2, r3
-0x00 0x22 0x18 0x00
-
-# CHECK:    addc    r1, r2, r3
-0x08 0x22 0x18 0x00
-
-# CHECK:    addk    r1, r2, r3
-0x10 0x22 0x18 0x00
-
-# CHECK:    addkc   r1, r2, r3
-0x18 0x22 0x18 0x00
-
-# CHECK:    and     r1, r2, r3
-0x84 0x22 0x18 0x00
-
-# CHECK:    andn    r1, r2, r3
-0x8c 0x22 0x18 0x00
-
-# CHECK:    cmp     r1, r2, r3
-0x14 0x22 0x18 0x01
-
-# CHECK:    cmpu    r1, r2, r3
-0x14 0x22 0x18 0x03
-
-# CHECK:    idiv    r1, r2, r3
-0x48 0x22 0x18 0x00
-
-# CHECK:    idivu   r1, r2, r3
-0x48 0x22 0x18 0x02
-
-# CHECK:    mul    r1, r2, r3
-0x40 0x22 0x18 0x00
-
-# CHECK:    mulh   r1, r2, r3
-0x40 0x22 0x18 0x01
-
-# CHECK:    mulhu  r1, r2, r3
-0x40 0x22 0x18 0x03
-
-# CHECK:    mulhsu r1, r2, r3
-0x40 0x22 0x18 0x02
-
-# CHECK:    or      r1, r2, r3
-0x80 0x22 0x18 0x00
-
-# CHECK:    rsub    r1, r2, r3
-0x04 0x22 0x18 0x00
-
-# CHECK:    rsubc   r1, r2, r3
-0x0c 0x22 0x18 0x00
-
-# CHECK:    rsubk   r1, r2, r3
-0x14 0x22 0x18 0x00
-
-# CHECK:    rsubkc  r1, r2, r3
-0x1c 0x22 0x18 0x00
-
-# CHECK:    sext16  r1, r2
-0x90 0x22 0x00 0x61
-
-# CHECK:    sext8   r1, r2
-0x90 0x22 0x00 0x60
-
-# CHECK:    xor     r1, r2, r3
-0x88 0x22 0x18 0x00
-
-# CHECK:    or      r0, r0, r0
-0x80 0x00 0x00 0x00
diff --git a/test/MC/Disassembler/MBlaze/mblaze_typeb.txt b/test/MC/Disassembler/MBlaze/mblaze_typeb.txt
deleted file mode 100644
index 99782ac..0000000
--- a/test/MC/Disassembler/MBlaze/mblaze_typeb.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s
-
-################################################################################
-# TYPE B instructions
-################################################################################
-
-# CHECK:    addi    r1, r2, 15
-0x20 0x22 0x00 0x0f
-
-# CHECK:    addic   r1, r2, 15
-0x28 0x22 0x00 0x0f
-
-# CHECK:    addik   r1, r2, 15
-0x30 0x22 0x00 0x0f
-
-# CHECK:    addikc  r1, r2, 15
-0x38 0x22 0x00 0x0f
-
-# CHECK:    andi    r1, r2, 15
-0xa4 0x22 0x00 0x0f
-
-# CHECK:    andni   r1, r2, 15
-0xac 0x22 0x00 0x0f
-
-# CHECK:    muli    r1, r2, 15
-0x60 0x22 0x00 0x0f
-
-# CHECK:    ori     r1, r2, 15
-0xa0 0x22 0x00 0x0f
-
-# CHECK:    rsubi   r1, r2, 15
-0x24 0x22 0x00 0x0f
-
-# CHECK:    rsubic  r1, r2, 15
-0x2c 0x22 0x00 0x0f
-
-# CHECK:    rsubik  r1, r2, 15
-0x34 0x22 0x00 0x0f
-
-# CHECK:    rsubikc r1, r2, 15
-0x3c 0x22 0x00 0x0f
-
-# CHECK:    rtbd r15, 15
-0xb6 0x4f 0x00 0x0f
-
-# CHECK:    rted r15, 15
-0xb6 0x8f 0x00 0x0f
-
-# CHECK:    rtid r15, 15
-0xb6 0x2f 0x00 0x0f
-
-# CHECK:    rtsd r15, 15
-0xb6 0x0f 0x00 0x0f
-
-# CHECK:    xori r1, r2, 15
-0xa8 0x22 0x00 0x0f
diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt
index ef8bf71..6d02925 100644
--- a/test/MC/Disassembler/Mips/mips32.txt
+++ b/test/MC/Disassembler/Mips/mips32.txt
@@ -35,9 +35,15 @@
 # CHECK: bc1f 1332
 0x45 0x00 0x01 0x4c
 
+# CHECK: bc1f $fcc7, 1332
+0x45 0x1c 0x01 0x4c
+
 # CHECK: bc1t 1332
 0x45 0x01 0x01 0x4c
 
+# CHECK: bc1t $fcc7, 1332
+0x45 0x1d 0x01 0x4c
+
 # CHECK: beq $9, $6, 1332
 0x11 0x26 0x01 0x4c
 
@@ -260,6 +266,24 @@
 # CHECK: mov.s $f6, $f7
 0x46 0x00 0x39 0x86
 
+# CHECK: movf $3, $2, $fcc7
+0x00,0x5c,0x18,0x01
+
+# CHECK: movf.d $f4, $f2, $fcc7
+0x46,0x3c,0x11,0x11
+
+# CHECK: movf.s $f4, $f2, $fcc7
+0x46,0x1c,0x11,0x11
+
+# CHECK: movt $3, $2, $fcc7
+0x00,0x5d,0x18,0x01
+
+# CHECK: movt.d $f4, $f2, $fcc7
+0x46,0x3d,0x11,0x11
+
+# CHECK: movt.s $f4, $f2, $fcc7
+0x46,0x1d,0x11,0x11
+
 # CHECK: msub   $6,  $7
 0x70 0xc7 0x00 0x04
 
diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt
index a0885a4..61e6fc8 100644
--- a/test/MC/Disassembler/Mips/mips32_le.txt
+++ b/test/MC/Disassembler/Mips/mips32_le.txt
@@ -35,9 +35,15 @@
 # CHECK: bc1f 1332
 0x4c 0x01 0x00 0x45
 
+# CHECK: bc1f $fcc7, 1332
+0x4c 0x01 0x1c 0x45
+
 # CHECK: bc1t 1332
 0x4c 0x01 0x01 0x45
 
+# CHECK: bc1t $fcc7, 1332
+0x4c 0x01 0x1d 0x45
+
 # CHECK: beq $9, $6, 1332
 0x4c 0x01 0x26 0x11
 
@@ -260,6 +266,30 @@
 # CHECK: mov.s $f6, $f7
 0x86 0x39 0x00 0x46
 
+# CHECK: move $7, $8
+0x21,0x38,0x00,0x01
+
+# CHECK: move $3, $2
+0x25,0x18,0x40,0x00
+
+# CHECK: movf $3, $2, $fcc7
+0x01,0x18,0x5c,0x00
+
+# CHECK: movf.d $f4, $f2, $fcc7
+0x11,0x11,0x3c,0x46
+
+# CHECK: movf.s $f4, $f2, $fcc7
+0x11,0x11,0x1c,0x46
+
+# CHECK: movt $3, $2, $fcc7
+0x01,0x18,0x5d,0x00
+
+# CHECK: movt.d $f4, $f2, $fcc7
+0x11,0x11,0x3d,0x46
+
+# CHECK: movt.s $f4, $f2, $fcc7
+0x11,0x11,0x1d,0x46
+
 # CHECK: msub   $6,  $7
 0x04 0x00 0xc7 0x70
 
diff --git a/test/MC/Disassembler/Mips/mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2.txt
index 991eaa6..48b6ad4 100644
--- a/test/MC/Disassembler/Mips/mips32r2.txt
+++ b/test/MC/Disassembler/Mips/mips32r2.txt
@@ -35,9 +35,15 @@
 # CHECK: bc1f 1332
 0x45 0x00 0x01 0x4c
 
+# CHECK: bc1f $fcc7, 1332
+0x45 0x1c 0x01 0x4c
+
 # CHECK: bc1t 1332
 0x45 0x01 0x01 0x4c
 
+# CHECK: bc1t $fcc7, 1332
+0x45 0x1d 0x01 0x4c
+
 # CHECK: beq $9, $6, 1332
 0x11 0x26 0x01 0x4c
 
diff --git a/test/MC/Disassembler/Mips/mips32r2_le.txt b/test/MC/Disassembler/Mips/mips32r2_le.txt
index 10c2938..c62c695 100644
--- a/test/MC/Disassembler/Mips/mips32r2_le.txt
+++ b/test/MC/Disassembler/Mips/mips32r2_le.txt
@@ -35,9 +35,15 @@
 # CHECK: bc1f 1332
 0x4c 0x01 0x00 0x45
 
+# CHECK: bc1f $fcc7, 1332
+0x4c 0x01 0x1c 0x45
+
 # CHECK: bc1t 1332
 0x4c 0x01 0x01 0x45
 
+# CHECK: bc1t $fcc7, 1332
+0x4c 0x01 0x1d 0x45
+
 # CHECK: beq $9, $6, 1332
 0x4c 0x01 0x26 0x11
 
diff --git a/test/MC/Disassembler/SystemZ/insns-pcrel.txt b/test/MC/Disassembler/SystemZ/insns-pcrel.txt
index f9e7774..c565b6e 100644
--- a/test/MC/Disassembler/SystemZ/insns-pcrel.txt
+++ b/test/MC/Disassembler/SystemZ/insns-pcrel.txt
@@ -1298,3 +1298,35 @@
 # 0x0000075a:
 # CHECK: cij %r0, 0, 15, 0x75a
 0xec 0x0f 0x00 0x00 0x00 0x7e
+
+# 0x00000760:
+# CHECK: brct %r0, 0x760
+0xa7 0x06 0x00 0x00
+
+# 0x00000764:
+# CHECK: brct %r1, 0x762
+0xa7 0x16 0xff 0xff
+
+# 0x00000768:
+# CHECK: brct %r9, 0xffffffffffff0768
+0xa7 0x96 0x80 0x00
+
+# 0x0000076c:
+# CHECK: brct %r15, 0x1076a
+0xa7 0xf6 0x7f 0xff
+
+# 0x00000770:
+# CHECK: brctg %r0, 0x770
+0xa7 0x07 0x00 0x00
+
+# 0x00000774:
+# CHECK: brctg %r1, 0x772
+0xa7 0x17 0xff 0xff
+
+# 0x00000778:
+# CHECK: brctg %r9, 0xffffffffffff0778
+0xa7 0x97 0x80 0x00
+
+# 0x0000077c:
+# CHECK: brctg %r15, 0x1077a
+0xa7 0xf7 0x7f 0xff
diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt
index 56236f7..51860cc 100644
--- a/test/MC/Disassembler/SystemZ/insns.txt
+++ b/test/MC/Disassembler/SystemZ/insns.txt
@@ -1,5 +1,5 @@
 # Test instructions that don't have PC-relative operands.
-# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
 
 # CHECK: adbr %f0, %f0
 0xb3 0x1a 0x00 0x00
@@ -163,6 +163,21 @@
 # CHECK: aghi %r15, 0
 0xa7 0xfb 0x00 0x00
 
+# CHECK: aghik %r0, %r1, -32768
+0xec 0x01 0x80 0x00 0x00 0xd9
+
+# CHECK: aghik %r2, %r3, -1
+0xec 0x23 0xff 0xff 0x00 0xd9
+
+# CHECK: aghik %r4, %r5, 0
+0xec 0x45 0x00 0x00 0x00 0xd9
+
+# CHECK: aghik %r6, %r7, 1
+0xec 0x67 0x00 0x01 0x00 0xd9
+
+# CHECK: aghik %r8, %r15, 32767
+0xec 0x8f 0x7f 0xff 0x00 0xd9
+
 # CHECK: agr %r0, %r0
 0xb9 0x08 0x00 0x00
 
@@ -175,6 +190,12 @@
 # CHECK: agr %r7, %r8
 0xb9 0x08 0x00 0x78
 
+# CHECK: agrk %r0, %r0, %r0
+0xb9 0xe8 0x00 0x00
+
+# CHECK: agrk %r2, %r3, %r4
+0xb9 0xe8 0x40 0x23
+
 # CHECK: agsi -524288, 0
 0xeb 0x00 0x00 0x00 0x80 0x7a
 
@@ -262,6 +283,21 @@
 # CHECK: ahi %r15, 0
 0xa7 0xfa 0x00 0x00
 
+# CHECK: ahik %r0, %r1, -32768
+0xec 0x01 0x80 0x00 0x00 0xd8
+
+# CHECK: ahik %r2, %r3, -1
+0xec 0x23 0xff 0xff 0x00 0xd8
+
+# CHECK: ahik %r4, %r5, 0
+0xec 0x45 0x00 0x00 0x00 0xd8
+
+# CHECK: ahik %r6, %r7, 1
+0xec 0x67 0x00 0x01 0x00 0xd8
+
+# CHECK: ahik %r8, %r15, 32767
+0xec 0x8f 0x7f 0xff 0x00 0xd8
+
 # CHECK: ah %r0, 0
 0x4a 0x00 0x00 0x00
 
@@ -469,6 +505,12 @@
 # CHECK: algr %r7, %r8
 0xb9 0x0a 0x00 0x78
 
+# CHECK: algrk %r0, %r0, %r0
+0xb9 0xea 0x00 0x00
+
+# CHECK: algrk %r2, %r3, %r4
+0xb9 0xea 0x40 0x23
+
 # CHECK: alg %r0, -524288
 0xe3 0x00 0x00 0x00 0x80 0x0a
 
@@ -499,6 +541,36 @@
 # CHECK: alg %r15, 0
 0xe3 0xf0 0x00 0x00 0x00 0x0a
 
+# CHECK: alghsik %r0, %r1, -32768
+0xec 0x01 0x80 0x00 0x00 0xdb
+
+# CHECK: alghsik %r2, %r3, -1
+0xec 0x23 0xff 0xff 0x00 0xdb
+
+# CHECK: alghsik %r4, %r5, 0
+0xec 0x45 0x00 0x00 0x00 0xdb
+
+# CHECK: alghsik %r6, %r7, 1
+0xec 0x67 0x00 0x01 0x00 0xdb
+
+# CHECK: alghsik %r8, %r15, 32767
+0xec 0x8f 0x7f 0xff 0x00 0xdb
+
+# CHECK: alhsik %r0, %r1, -32768
+0xec 0x01 0x80 0x00 0x00 0xda
+
+# CHECK: alhsik %r2, %r3, -1
+0xec 0x23 0xff 0xff 0x00 0xda
+
+# CHECK: alhsik %r4, %r5, 0
+0xec 0x45 0x00 0x00 0x00 0xda
+
+# CHECK: alhsik %r6, %r7, 1
+0xec 0x67 0x00 0x01 0x00 0xda
+
+# CHECK: alhsik %r8, %r15, 32767
+0xec 0x8f 0x7f 0xff 0x00 0xda
+
 # CHECK: alr %r0, %r0
 0x1e 0x00
 
@@ -511,6 +583,12 @@
 # CHECK: alr %r7, %r8
 0x1e 0x78
 
+# CHECK: alrk %r0, %r0, %r0
+0xb9 0xfa 0x00 0x00
+
+# CHECK: alrk %r2, %r3, %r4
+0xb9 0xfa 0x40 0x23
+
 # CHECK: al %r0, 0
 0x5e 0x00 0x00 0x00
 
@@ -574,6 +652,12 @@
 # CHECK: ar %r7, %r8
 0x1a 0x78
 
+# CHECK: ark %r0, %r0, %r0
+0xb9 0xf8 0x00 0x00
+
+# CHECK: ark %r2, %r3, %r4
+0xb9 0xf8 0x40 0x23
+
 # CHECK: asi -524288, 0
 0xeb 0x00 0x00 0x00 0x80 0x6a
 
@@ -3178,6 +3262,198 @@
 # CHECK: lnxbr %f13, %f9
 0xb3 0x41 0x00 0xd9
 
+# CHECK: loc %r7, 6399(%r8), 0
+0xeb 0x70 0x88 0xff 0x01 0xf2
+
+# CHECK: loco %r7, 6399(%r8)
+0xeb 0x71 0x88 0xff 0x01 0xf2
+
+# CHECK: loch %r7, 6399(%r8)
+0xeb 0x72 0x88 0xff 0x01 0xf2
+
+# CHECK: locnle %r7, 6399(%r8)
+0xeb 0x73 0x88 0xff 0x01 0xf2
+
+# CHECK: locl %r7, 6399(%r8)
+0xeb 0x74 0x88 0xff 0x01 0xf2
+
+# CHECK: locnhe %r7, 6399(%r8)
+0xeb 0x75 0x88 0xff 0x01 0xf2
+
+# CHECK: loclh %r7, 6399(%r8)
+0xeb 0x76 0x88 0xff 0x01 0xf2
+
+# CHECK: locne %r7, 6399(%r8)
+0xeb 0x77 0x88 0xff 0x01 0xf2
+
+# CHECK: loce %r7, 6399(%r8)
+0xeb 0x78 0x88 0xff 0x01 0xf2
+
+# CHECK: locnlh %r7, 6399(%r8)
+0xeb 0x79 0x88 0xff 0x01 0xf2
+
+# CHECK: loche %r7, 6399(%r8)
+0xeb 0x7a 0x88 0xff 0x01 0xf2
+
+# CHECK: locnl %r7, 6399(%r8)
+0xeb 0x7b 0x88 0xff 0x01 0xf2
+
+# CHECK: locle %r7, 6399(%r8)
+0xeb 0x7c 0x88 0xff 0x01 0xf2
+
+# CHECK: locnh %r7, 6399(%r8)
+0xeb 0x7d 0x88 0xff 0x01 0xf2
+
+# CHECK: locno %r7, 6399(%r8)
+0xeb 0x7e 0x88 0xff 0x01 0xf2
+
+# CHECK: loc %r7, 6399(%r8), 15
+0xeb 0x7f 0x88 0xff 0x01 0xf2
+
+# CHECK: locg %r7, 6399(%r8), 0
+0xeb 0x70 0x88 0xff 0x01 0xe2
+
+# CHECK: locgo %r7, 6399(%r8)
+0xeb 0x71 0x88 0xff 0x01 0xe2
+
+# CHECK: locgh %r7, 6399(%r8)
+0xeb 0x72 0x88 0xff 0x01 0xe2
+
+# CHECK: locgnle %r7, 6399(%r8)
+0xeb 0x73 0x88 0xff 0x01 0xe2
+
+# CHECK: locgl %r7, 6399(%r8)
+0xeb 0x74 0x88 0xff 0x01 0xe2
+
+# CHECK: locgnhe %r7, 6399(%r8)
+0xeb 0x75 0x88 0xff 0x01 0xe2
+
+# CHECK: locglh %r7, 6399(%r8)
+0xeb 0x76 0x88 0xff 0x01 0xe2
+
+# CHECK: locgne %r7, 6399(%r8)
+0xeb 0x77 0x88 0xff 0x01 0xe2
+
+# CHECK: locge %r7, 6399(%r8)
+0xeb 0x78 0x88 0xff 0x01 0xe2
+
+# CHECK: locgnlh %r7, 6399(%r8)
+0xeb 0x79 0x88 0xff 0x01 0xe2
+
+# CHECK: locghe %r7, 6399(%r8)
+0xeb 0x7a 0x88 0xff 0x01 0xe2
+
+# CHECK: locgnl %r7, 6399(%r8)
+0xeb 0x7b 0x88 0xff 0x01 0xe2
+
+# CHECK: locgle %r7, 6399(%r8)
+0xeb 0x7c 0x88 0xff 0x01 0xe2
+
+# CHECK: locgnh %r7, 6399(%r8)
+0xeb 0x7d 0x88 0xff 0x01 0xe2
+
+# CHECK: locgno %r7, 6399(%r8)
+0xeb 0x7e 0x88 0xff 0x01 0xe2
+
+# CHECK: locg %r7, 6399(%r8), 15
+0xeb 0x7f 0x88 0xff 0x01 0xe2
+
+# CHECK: locr %r11, %r3, 0
+0xb9 0xf2 0x00 0xb3
+
+# CHECK: locro %r11, %r3
+0xb9 0xf2 0x10 0xb3
+
+# CHECK: locrh %r11, %r3
+0xb9 0xf2 0x20 0xb3
+
+# CHECK: locrnle %r11, %r3
+0xb9 0xf2 0x30 0xb3
+
+# CHECK: locrl %r11, %r3
+0xb9 0xf2 0x40 0xb3
+
+# CHECK: locrnhe %r11, %r3
+0xb9 0xf2 0x50 0xb3
+
+# CHECK: locrlh %r11, %r3
+0xb9 0xf2 0x60 0xb3
+
+# CHECK: locrne %r11, %r3
+0xb9 0xf2 0x70 0xb3
+
+# CHECK: locre %r11, %r3
+0xb9 0xf2 0x80 0xb3
+
+# CHECK: locrnlh %r11, %r3
+0xb9 0xf2 0x90 0xb3
+
+# CHECK: locrhe %r11, %r3
+0xb9 0xf2 0xa0 0xb3
+
+# CHECK: locrnl %r11, %r3
+0xb9 0xf2 0xb0 0xb3
+
+# CHECK: locrle %r11, %r3
+0xb9 0xf2 0xc0 0xb3
+
+# CHECK: locrnh %r11, %r3
+0xb9 0xf2 0xd0 0xb3
+
+# CHECK: locrno %r11, %r3
+0xb9 0xf2 0xe0 0xb3
+
+# CHECK: locr %r11, %r3, 15
+0xb9 0xf2 0xf0 0xb3
+
+# CHECK: locgr %r11, %r3, 0
+0xb9 0xe2 0x00 0xb3
+
+# CHECK: locgro %r11, %r3
+0xb9 0xe2 0x10 0xb3
+
+# CHECK: locgrh %r11, %r3
+0xb9 0xe2 0x20 0xb3
+
+# CHECK: locgrnle %r11, %r3
+0xb9 0xe2 0x30 0xb3
+
+# CHECK: locgrl %r11, %r3
+0xb9 0xe2 0x40 0xb3
+
+# CHECK: locgrnhe %r11, %r3
+0xb9 0xe2 0x50 0xb3
+
+# CHECK: locgrlh %r11, %r3
+0xb9 0xe2 0x60 0xb3
+
+# CHECK: locgrne %r11, %r3
+0xb9 0xe2 0x70 0xb3
+
+# CHECK: locgre %r11, %r3
+0xb9 0xe2 0x80 0xb3
+
+# CHECK: locgrnlh %r11, %r3
+0xb9 0xe2 0x90 0xb3
+
+# CHECK: locgrhe %r11, %r3
+0xb9 0xe2 0xa0 0xb3
+
+# CHECK: locgrnl %r11, %r3
+0xb9 0xe2 0xb0 0xb3
+
+# CHECK: locgrle %r11, %r3
+0xb9 0xe2 0xc0 0xb3
+
+# CHECK: locgrnh %r11, %r3
+0xb9 0xe2 0xd0 0xb3
+
+# CHECK: locgrno %r11, %r3
+0xb9 0xe2 0xe0 0xb3
+
+# CHECK: locgr %r11, %r3, 15
+0xb9 0xe2 0xf0 0xb3
+
 # CHECK: lpdbr %f0, %f9
 0xb3 0x10 0x00 0x09
 
@@ -3337,6 +3613,168 @@
 # CHECK: l %r15, 0
 0x58 0xf0 0x00 0x00
 
+# CHECK: lt %r0, -524288
+0xe3 0x00 0x00 0x00 0x80 0x12
+
+# CHECK: lt %r0, -1
+0xe3 0x00 0x0f 0xff 0xff 0x12
+
+# CHECK: lt %r0, 0
+0xe3 0x00 0x00 0x00 0x00 0x12
+
+# CHECK: lt %r0, 1
+0xe3 0x00 0x00 0x01 0x00 0x12
+
+# CHECK: lt %r0, 524287
+0xe3 0x00 0x0f 0xff 0x7f 0x12
+
+# CHECK: lt %r0, 0(%r1)
+0xe3 0x00 0x10 0x00 0x00 0x12
+
+# CHECK: lt %r0, 0(%r15)
+0xe3 0x00 0xf0 0x00 0x00 0x12
+
+# CHECK: lt %r0, 524287(%r1,%r15)
+0xe3 0x01 0xff 0xff 0x7f 0x12
+
+# CHECK: lt %r0, 524287(%r15,%r1)
+0xe3 0x0f 0x1f 0xff 0x7f 0x12
+
+# CHECK: lt %r15, 0
+0xe3 0xf0 0x00 0x00 0x00 0x12
+
+# CHECK: ltdbr %f0, %f9
+0xb3 0x12 0x00 0x09
+
+# CHECK: ltdbr %f0, %f15
+0xb3 0x12 0x00 0x0f
+
+# CHECK: ltdbr %f15, %f0
+0xb3 0x12 0x00 0xf0
+
+# CHECK: ltdbr %f15, %f9
+0xb3 0x12 0x00 0xf9
+
+# CHECK: ltebr %f0, %f9
+0xb3 0x02 0x00 0x09
+
+# CHECK: ltebr %f0, %f15
+0xb3 0x02 0x00 0x0f
+
+# CHECK: ltebr %f15, %f0
+0xb3 0x02 0x00 0xf0
+
+# CHECK: ltebr %f15, %f9
+0xb3 0x02 0x00 0xf9
+
+# CHECK: ltg %r0, -524288
+0xe3 0x00 0x00 0x00 0x80 0x02
+
+# CHECK: ltg %r0, -1
+0xe3 0x00 0x0f 0xff 0xff 0x02
+
+# CHECK: ltg %r0, 0
+0xe3 0x00 0x00 0x00 0x00 0x02
+
+# CHECK: ltg %r0, 1
+0xe3 0x00 0x00 0x01 0x00 0x02
+
+# CHECK: ltg %r0, 524287
+0xe3 0x00 0x0f 0xff 0x7f 0x02
+
+# CHECK: ltg %r0, 0(%r1)
+0xe3 0x00 0x10 0x00 0x00 0x02
+
+# CHECK: ltg %r0, 0(%r15)
+0xe3 0x00 0xf0 0x00 0x00 0x02
+
+# CHECK: ltg %r0, 524287(%r1,%r15)
+0xe3 0x01 0xff 0xff 0x7f 0x02
+
+# CHECK: ltg %r0, 524287(%r15,%r1)
+0xe3 0x0f 0x1f 0xff 0x7f 0x02
+
+# CHECK: ltg %r15, 0
+0xe3 0xf0 0x00 0x00 0x00 0x02
+
+# CHECK: ltgf %r0, -524288
+0xe3 0x00 0x00 0x00 0x80 0x32
+
+# CHECK: ltgf %r0, -1
+0xe3 0x00 0x0f 0xff 0xff 0x32
+
+# CHECK: ltgf %r0, 0
+0xe3 0x00 0x00 0x00 0x00 0x32
+
+# CHECK: ltgf %r0, 1
+0xe3 0x00 0x00 0x01 0x00 0x32
+
+# CHECK: ltgf %r0, 524287
+0xe3 0x00 0x0f 0xff 0x7f 0x32
+
+# CHECK: ltgf %r0, 0(%r1)
+0xe3 0x00 0x10 0x00 0x00 0x32
+
+# CHECK: ltgf %r0, 0(%r15)
+0xe3 0x00 0xf0 0x00 0x00 0x32
+
+# CHECK: ltgf %r0, 524287(%r1,%r15)
+0xe3 0x01 0xff 0xff 0x7f 0x32
+
+# CHECK: ltgf %r0, 524287(%r15,%r1)
+0xe3 0x0f 0x1f 0xff 0x7f 0x32
+
+# CHECK: ltgf %r15, 0
+0xe3 0xf0 0x00 0x00 0x00 0x32
+
+# CHECK: ltgfr %r0, %r9
+0xb9 0x12 0x00 0x09
+
+# CHECK: ltgfr %r0, %r15
+0xb9 0x12 0x00 0x0f
+
+# CHECK: ltgfr %r15, %r0
+0xb9 0x12 0x00 0xf0
+
+# CHECK: ltgfr %r15, %r9
+0xb9 0x12 0x00 0xf9
+
+# CHECK: ltgr %r0, %r9
+0xb9 0x02 0x00 0x09
+
+# CHECK: ltgr %r0, %r15
+0xb9 0x02 0x00 0x0f
+
+# CHECK: ltgr %r15, %r0
+0xb9 0x02 0x00 0xf0
+
+# CHECK: ltgr %r15, %r9
+0xb9 0x02 0x00 0xf9
+
+# CHECK: ltr %r0, %r9
+0x12 0x09
+
+# CHECK: ltr %r0, %r15
+0x12 0x0f
+
+# CHECK: ltr %r15, %r0
+0x12 0xf0
+
+# CHECK: ltr %r15, %r9
+0x12 0xf9
+
+# CHECK: ltxbr %f0, %f9
+0xb3 0x42 0x00 0x09
+
+# CHECK: ltxbr %f0, %f13
+0xb3 0x42 0x00 0x0d
+
+# CHECK: ltxbr %f13, %f0
+0xb3 0x42 0x00 0xd0
+
+# CHECK: ltxbr %f13, %f9
+0xb3 0x42 0x00 0xd9
+
 # CHECK: lxr %f0, %f8
 0xb3 0x65 0x00 0x08
 
@@ -4207,6 +4645,12 @@
 # CHECK: ng %r0, -524288
 0xe3 0x00 0x00 0x00 0x80 0x80
 
+# CHECK: ngrk %r0, %r0, %r0
+0xb9 0xe4 0x00 0x00
+
+# CHECK: ngrk %r2, %r3, %r4
+0xb9 0xe4 0x40 0x23
+
 # CHECK: ng %r0, -1
 0xe3 0x00 0x0f 0xff 0xff 0x80
 
@@ -4363,6 +4807,12 @@
 # CHECK: nr %r7, %r8
 0x14 0x78
 
+# CHECK: nrk %r0, %r0, %r0
+0xb9 0xf4 0x00 0x00
+
+# CHECK: nrk %r2, %r3, %r4
+0xb9 0xf4 0x40 0x23
+
 # CHECK: n %r0, 0
 0x54 0x00 0x00 0x00
 
@@ -4426,6 +4876,12 @@
 # CHECK: ogr %r7, %r8
 0xb9 0x81 0x00 0x78
 
+# CHECK: ogrk %r0, %r0, %r0
+0xb9 0xe6 0x00 0x00
+
+# CHECK: ogrk %r2, %r3, %r4
+0xb9 0xe6 0x40 0x23
+
 # CHECK: og %r0, -524288
 0xe3 0x00 0x00 0x00 0x80 0x81
 
@@ -4585,6 +5041,12 @@
 # CHECK: or %r7, %r8
 0x16 0x78
 
+# CHECK: ork %r0, %r0, %r0
+0xb9 0xf6 0x00 0x00
+
+# CHECK: ork %r2, %r3, %r4
+0xb9 0xf6 0x40 0x23
+
 # CHECK: o %r0, 0
 0x56 0x00 0x00 0x00
 
@@ -4642,11 +5104,11 @@
 # CHECK: risbg %r0, %r0, 0, 0, 63
 0xec 0x00 0x00 0x00 0x3f 0x55
 
-# CHECK: risbg %r0, %r0, 0, 63, 0
-0xec 0x00 0x00 0x3f 0x00 0x55
+# CHECK: risbg %r0, %r0, 0, 255, 0
+0xec 0x00 0x00 0xff 0x00 0x55
 
-# CHECK: risbg %r0, %r0, 63, 0, 0
-0xec 0x00 0x3f 0x00 0x00 0x55
+# CHECK: risbg %r0, %r0, 255, 0, 0
+0xec 0x00 0xff 0x00 0x00 0x55
 
 # CHECK: risbg %r0, %r15, 0, 0, 0
 0xec 0x0f 0x00 0x00 0x00 0x55
@@ -4657,6 +5119,111 @@
 # CHECK: risbg %r4, %r5, 6, 7, 8
 0xec 0x45 0x06 0x07 0x08 0x55
 
+# CHECK: risbhg %r0, %r0, 0, 0, 0
+0xec 0x00 0x00 0x00 0x00 0x5d
+
+# CHECK: risbhg %r0, %r0, 0, 0, 63
+0xec 0x00 0x00 0x00 0x3f 0x5d
+
+# CHECK: risbhg %r0, %r0, 0, 255, 0
+0xec 0x00 0x00 0xff 0x00 0x5d
+
+# CHECK: risbhg %r0, %r0, 255, 0, 0
+0xec 0x00 0xff 0x00 0x00 0x5d
+
+# CHECK: risbhg %r0, %r15, 0, 0, 0
+0xec 0x0f 0x00 0x00 0x00 0x5d
+
+# CHECK: risbhg %r15, %r0, 0, 0, 0
+0xec 0xf0 0x00 0x00 0x00 0x5d
+
+# CHECK: risbhg %r4, %r5, 6, 7, 8
+0xec 0x45 0x06 0x07 0x08 0x5d
+
+# CHECK: risblg %r0, %r0, 0, 0, 0
+0xec 0x00 0x00 0x00 0x00 0x51
+
+# CHECK: risblg %r0, %r0, 0, 0, 63
+0xec 0x00 0x00 0x00 0x3f 0x51
+
+# CHECK: risblg %r0, %r0, 0, 255, 0
+0xec 0x00 0x00 0xff 0x00 0x51
+
+# CHECK: risblg %r0, %r0, 255, 0, 0
+0xec 0x00 0xff 0x00 0x00 0x51
+
+# CHECK: risblg %r0, %r15, 0, 0, 0
+0xec 0x0f 0x00 0x00 0x00 0x51
+
+# CHECK: risblg %r15, %r0, 0, 0, 0
+0xec 0xf0 0x00 0x00 0x00 0x51
+
+# CHECK: risblg %r4, %r5, 6, 7, 8
+0xec 0x45 0x06 0x07 0x08 0x51
+
+# CHECK: rnsbg %r0, %r0, 0, 0, 0
+0xec 0x00 0x00 0x00 0x00 0x54
+
+# CHECK: rnsbg %r0, %r0, 0, 0, 63
+0xec 0x00 0x00 0x00 0x3f 0x54
+
+# CHECK: rnsbg %r0, %r0, 0, 255, 0
+0xec 0x00 0x00 0xff 0x00 0x54
+
+# CHECK: rnsbg %r0, %r0, 255, 0, 0
+0xec 0x00 0xff 0x00 0x00 0x54
+
+# CHECK: rnsbg %r0, %r15, 0, 0, 0
+0xec 0x0f 0x00 0x00 0x00 0x54
+
+# CHECK: rnsbg %r15, %r0, 0, 0, 0
+0xec 0xf0 0x00 0x00 0x00 0x54
+
+# CHECK: rnsbg %r4, %r5, 6, 7, 8
+0xec 0x45 0x06 0x07 0x08 0x54
+
+# CHECK: rosbg %r0, %r0, 0, 0, 0
+0xec 0x00 0x00 0x00 0x00 0x56
+
+# CHECK: rosbg %r0, %r0, 0, 0, 63
+0xec 0x00 0x00 0x00 0x3f 0x56
+
+# CHECK: rosbg %r0, %r0, 0, 255, 0
+0xec 0x00 0x00 0xff 0x00 0x56
+
+# CHECK: rosbg %r0, %r0, 255, 0, 0
+0xec 0x00 0xff 0x00 0x00 0x56
+
+# CHECK: rosbg %r0, %r15, 0, 0, 0
+0xec 0x0f 0x00 0x00 0x00 0x56
+
+# CHECK: rosbg %r15, %r0, 0, 0, 0
+0xec 0xf0 0x00 0x00 0x00 0x56
+
+# CHECK: rosbg %r4, %r5, 6, 7, 8
+0xec 0x45 0x06 0x07 0x08 0x56
+
+# CHECK: rxsbg %r0, %r0, 0, 0, 0
+0xec 0x00 0x00 0x00 0x00 0x57
+
+# CHECK: rxsbg %r0, %r0, 0, 0, 63
+0xec 0x00 0x00 0x00 0x3f 0x57
+
+# CHECK: rxsbg %r0, %r0, 0, 255, 0
+0xec 0x00 0x00 0xff 0x00 0x57
+
+# CHECK: rxsbg %r0, %r0, 255, 0, 0
+0xec 0x00 0xff 0x00 0x00 0x57
+
+# CHECK: rxsbg %r0, %r15, 0, 0, 0
+0xec 0x0f 0x00 0x00 0x00 0x57
+
+# CHECK: rxsbg %r15, %r0, 0, 0, 0
+0xec 0xf0 0x00 0x00 0x00 0x57
+
+# CHECK: rxsbg %r4, %r5, 6, 7, 8
+0xec 0x45 0x06 0x07 0x08 0x57
+
 # CHECK: rllg %r0, %r0, 0
 0xeb 0x00 0x00 0x00 0x00 0x1c
 
@@ -4849,6 +5416,12 @@
 # CHECK: sgr %r7, %r8
 0xb9 0x09 0x00 0x78
 
+# CHECK: sgrk %r0, %r0, %r0
+0xb9 0xe9 0x00 0x00
+
+# CHECK: sgrk %r2, %r3, %r4
+0xb9 0xe9 0x40 0x23
+
 # CHECK: sg %r0, -524288
 0xe3 0x00 0x00 0x00 0x80 0x09
 
@@ -5086,6 +5659,12 @@
 # CHECK: slgr %r7, %r8
 0xb9 0x0b 0x00 0x78
 
+# CHECK: slgrk %r0, %r0, %r0
+0xb9 0xeb 0x00 0x00
+
+# CHECK: slgrk %r2, %r3, %r4
+0xb9 0xeb 0x40 0x23
+
 # CHECK: slg %r0, -524288
 0xe3 0x00 0x00 0x00 0x80 0x0b
 
@@ -5152,6 +5731,42 @@
 # CHECK: sllg %r0, %r0, 524287(%r15)
 0xeb 0x00 0xff 0xff 0x7f 0x0d
 
+# CHECK: sllk %r0, %r0, 0
+0xeb 0x00 0x00 0x00 0x00 0xdf
+
+# CHECK: sllk %r15, %r1, 0
+0xeb 0xf1 0x00 0x00 0x00 0xdf
+
+# CHECK: sllk %r1, %r15, 0
+0xeb 0x1f 0x00 0x00 0x00 0xdf
+
+# CHECK: sllk %r15, %r15, 0
+0xeb 0xff 0x00 0x00 0x00 0xdf
+
+# CHECK: sllk %r0, %r0, -524288
+0xeb 0x00 0x00 0x00 0x80 0xdf
+
+# CHECK: sllk %r0, %r0, -1
+0xeb 0x00 0x0f 0xff 0xff 0xdf
+
+# CHECK: sllk %r0, %r0, 1
+0xeb 0x00 0x00 0x01 0x00 0xdf
+
+# CHECK: sllk %r0, %r0, 524287
+0xeb 0x00 0x0f 0xff 0x7f 0xdf
+
+# CHECK: sllk %r0, %r0, 0(%r1)
+0xeb 0x00 0x10 0x00 0x00 0xdf
+
+# CHECK: sllk %r0, %r0, 0(%r15)
+0xeb 0x00 0xf0 0x00 0x00 0xdf
+
+# CHECK: sllk %r0, %r0, 524287(%r1)
+0xeb 0x00 0x1f 0xff 0x7f 0xdf
+
+# CHECK: sllk %r0, %r0, 524287(%r15)
+0xeb 0x00 0xff 0xff 0x7f 0xdf
+
 # CHECK: sll %r0, 0
 0x89 0x00 0x00 0x00
 
@@ -5188,6 +5803,12 @@
 # CHECK: slr %r7, %r8
 0x1f 0x78
 
+# CHECK: slrk %r0, %r0, %r0
+0xb9 0xfb 0x00 0x00
+
+# CHECK: slrk %r2, %r3, %r4
+0xb9 0xfb 0x40 0x23
+
 # CHECK: sl %r0, 0
 0x5f 0x00 0x00 0x00
 
@@ -5353,6 +5974,42 @@
 # CHECK: srag %r0, %r0, 524287(%r15)
 0xeb 0x00 0xff 0xff 0x7f 0x0a
 
+# CHECK: srak %r0, %r0, 0
+0xeb 0x00 0x00 0x00 0x00 0xdc
+
+# CHECK: srak %r15, %r1, 0
+0xeb 0xf1 0x00 0x00 0x00 0xdc
+
+# CHECK: srak %r1, %r15, 0
+0xeb 0x1f 0x00 0x00 0x00 0xdc
+
+# CHECK: srak %r15, %r15, 0
+0xeb 0xff 0x00 0x00 0x00 0xdc
+
+# CHECK: srak %r0, %r0, -524288
+0xeb 0x00 0x00 0x00 0x80 0xdc
+
+# CHECK: srak %r0, %r0, -1
+0xeb 0x00 0x0f 0xff 0xff 0xdc
+
+# CHECK: srak %r0, %r0, 1
+0xeb 0x00 0x00 0x01 0x00 0xdc
+
+# CHECK: srak %r0, %r0, 524287
+0xeb 0x00 0x0f 0xff 0x7f 0xdc
+
+# CHECK: srak %r0, %r0, 0(%r1)
+0xeb 0x00 0x10 0x00 0x00 0xdc
+
+# CHECK: srak %r0, %r0, 0(%r15)
+0xeb 0x00 0xf0 0x00 0x00 0xdc
+
+# CHECK: srak %r0, %r0, 524287(%r1)
+0xeb 0x00 0x1f 0xff 0x7f 0xdc
+
+# CHECK: srak %r0, %r0, 524287(%r15)
+0xeb 0x00 0xff 0xff 0x7f 0xdc
+
 # CHECK: sra %r0, 0
 0x8a 0x00 0x00 0x00
 
@@ -5413,6 +6070,42 @@
 # CHECK: srlg %r0, %r0, 524287(%r15)
 0xeb 0x00 0xff 0xff 0x7f 0x0c
 
+# CHECK: srlk %r0, %r0, 0
+0xeb 0x00 0x00 0x00 0x00 0xde
+
+# CHECK: srlk %r15, %r1, 0
+0xeb 0xf1 0x00 0x00 0x00 0xde
+
+# CHECK: srlk %r1, %r15, 0
+0xeb 0x1f 0x00 0x00 0x00 0xde
+
+# CHECK: srlk %r15, %r15, 0
+0xeb 0xff 0x00 0x00 0x00 0xde
+
+# CHECK: srlk %r0, %r0, -524288
+0xeb 0x00 0x00 0x00 0x80 0xde
+
+# CHECK: srlk %r0, %r0, -1
+0xeb 0x00 0x0f 0xff 0xff 0xde
+
+# CHECK: srlk %r0, %r0, 1
+0xeb 0x00 0x00 0x01 0x00 0xde
+
+# CHECK: srlk %r0, %r0, 524287
+0xeb 0x00 0x0f 0xff 0x7f 0xde
+
+# CHECK: srlk %r0, %r0, 0(%r1)
+0xeb 0x00 0x10 0x00 0x00 0xde
+
+# CHECK: srlk %r0, %r0, 0(%r15)
+0xeb 0x00 0xf0 0x00 0x00 0xde
+
+# CHECK: srlk %r0, %r0, 524287(%r1)
+0xeb 0x00 0x1f 0xff 0x7f 0xde
+
+# CHECK: srlk %r0, %r0, 524287(%r15)
+0xeb 0x00 0xff 0xff 0x7f 0xde
+
 # CHECK: srl %r0, 0
 0x88 0x00 0x00 0x00
 
@@ -5449,6 +6142,12 @@
 # CHECK: sr %r7, %r8
 0x1b 0x78
 
+# CHECK: srk %r0, %r0, %r0
+0xb9 0xf9 0x00 0x00
+
+# CHECK: srk %r2, %r3, %r4
+0xb9 0xf9 0x40 0x23
+
 # CHECK: stc %r0, 0
 0x42 0x00 0x00 0x00
 
@@ -5803,6 +6502,102 @@
 # CHECK: st %r15, 0
 0x50 0xf0 0x00 0x00
 
+# CHECK: stoc %r1, 2(%r3), 0
+0xeb 0x10 0x30 0x02 0x00 0xf3
+
+# CHECK: stoco %r1, 2(%r3)
+0xeb 0x11 0x30 0x02 0x00 0xf3
+
+# CHECK: stoch %r1, 2(%r3)
+0xeb 0x12 0x30 0x02 0x00 0xf3
+
+# CHECK: stocnle %r1, 2(%r3)
+0xeb 0x13 0x30 0x02 0x00 0xf3
+
+# CHECK: stocl %r1, 2(%r3)
+0xeb 0x14 0x30 0x02 0x00 0xf3
+
+# CHECK: stocnhe %r1, 2(%r3)
+0xeb 0x15 0x30 0x02 0x00 0xf3
+
+# CHECK: stoclh %r1, 2(%r3)
+0xeb 0x16 0x30 0x02 0x00 0xf3
+
+# CHECK: stocne %r1, 2(%r3)
+0xeb 0x17 0x30 0x02 0x00 0xf3
+
+# CHECK: stoce %r1, 2(%r3)
+0xeb 0x18 0x30 0x02 0x00 0xf3
+
+# CHECK: stocnlh %r1, 2(%r3)
+0xeb 0x19 0x30 0x02 0x00 0xf3
+
+# CHECK: stoche %r1, 2(%r3)
+0xeb 0x1a 0x30 0x02 0x00 0xf3
+
+# CHECK: stocnl %r1, 2(%r3)
+0xeb 0x1b 0x30 0x02 0x00 0xf3
+
+# CHECK: stocle %r1, 2(%r3)
+0xeb 0x1c 0x30 0x02 0x00 0xf3
+
+# CHECK: stocnh %r1, 2(%r3)
+0xeb 0x1d 0x30 0x02 0x00 0xf3
+
+# CHECK: stocno %r1, 2(%r3)
+0xeb 0x1e 0x30 0x02 0x00 0xf3
+
+# CHECK: stoc %r1, 2(%r3), 15
+0xeb 0x1f 0x30 0x02 0x00 0xf3
+
+# CHECK: stocg %r1, 2(%r3), 0
+0xeb 0x10 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgo %r1, 2(%r3)
+0xeb 0x11 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgh %r1, 2(%r3)
+0xeb 0x12 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgnle %r1, 2(%r3)
+0xeb 0x13 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgl %r1, 2(%r3)
+0xeb 0x14 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgnhe %r1, 2(%r3)
+0xeb 0x15 0x30 0x02 0x00 0xe3
+
+# CHECK: stocglh %r1, 2(%r3)
+0xeb 0x16 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgne %r1, 2(%r3)
+0xeb 0x17 0x30 0x02 0x00 0xe3
+
+# CHECK: stocge %r1, 2(%r3)
+0xeb 0x18 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgnlh %r1, 2(%r3)
+0xeb 0x19 0x30 0x02 0x00 0xe3
+
+# CHECK: stocghe %r1, 2(%r3)
+0xeb 0x1a 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgnl %r1, 2(%r3)
+0xeb 0x1b 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgle %r1, 2(%r3)
+0xeb 0x1c 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgnh %r1, 2(%r3)
+0xeb 0x1d 0x30 0x02 0x00 0xe3
+
+# CHECK: stocgno %r1, 2(%r3)
+0xeb 0x1e 0x30 0x02 0x00 0xe3
+
+# CHECK: stocg %r1, 2(%r3), 15
+0xeb 0x1f 0x30 0x02 0x00 0xe3
+
 # CHECK: s %r0, 0
 0x5b 0x00 0x00 0x00
 
@@ -5908,6 +6703,12 @@
 # CHECK: xgr %r7, %r8
 0xb9 0x82 0x00 0x78
 
+# CHECK: xgrk %r0, %r0, %r0
+0xb9 0xe7 0x00 0x00
+
+# CHECK: xgrk %r2, %r3, %r4
+0xb9 0xe7 0x40 0x23
+
 # CHECK: xg %r0, -524288
 0xe3 0x00 0x00 0x00 0x80 0x82
 
@@ -6019,6 +6820,12 @@
 # CHECK: xr %r7, %r8
 0x17 0x78
 
+# CHECK: xrk %r0, %r0, %r0
+0xb9 0xf7 0x00 0x00
+
+# CHECK: xrk %r2, %r3, %r4
+0xb9 0xf7 0x40 0x23
+
 # CHECK: x %r0, 0
 0x57 0x00 0x00 0x00
 
diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt
index 57e602f..6c0c239 100644
--- a/test/MC/Disassembler/X86/intel-syntax.txt
+++ b/test/MC/Disassembler/X86/intel-syntax.txt
@@ -12,70 +12,70 @@
 # CHECK: movsq
 0x48 0xa5
 
-# CHECK: pop FS
+# CHECK: pop fs
 0x0f 0xa1
 
-# CHECK: pop GS
+# CHECK: pop gs
 0x0f 0xa9
 
-# CHECK: in AL, DX
+# CHECK: in al, dx
 0xec
 
 # CHECK: nop
 0x90
 
-# CHECK: xchg EAX, R8D
+# CHECK: xchg eax, r8d
 0x41 0x90
 
-# CHECK: xchg RAX, R8
+# CHECK: xchg rax, r8
 0x49 0x90
 
-# CHECK: add AL, 0
+# CHECK: add al, 0
 0x04 0x00
 
-# CHECK: add AX, 0
+# CHECK: add ax, 0
 0x66 0x05 0x00 0x00
 
-# CHECK: add EAX, 0
+# CHECK: add eax, 0
 0x05 0x00 0x00 0x00 0x00
 
-# CHECK: add RAX, 0
+# CHECK: add rax, 0
 0x48 0x05 0x00 0x00 0x00 0x00
 
-# CHECK: adc AL, 0
+# CHECK: adc al, 0
 0x14 0x00
 
-# CHECK: adc AX, 0
+# CHECK: adc ax, 0
 0x66 0x15 0x00 0x00
 
-# CHECK: adc EAX, 0
+# CHECK: adc eax, 0
 0x15 0x00 0x00 0x00 0x00
 
-# CHECK: adc RAX, 0
+# CHECK: adc rax, 0
 0x48 0x15 0x00 0x00 0x00 0x00
 
-# CHECK: cmp AL, 0
+# CHECK: cmp al, 0
 0x3c 0x00
 
-# CHECK: cmp AX, 0
+# CHECK: cmp ax, 0
 0x66 0x3d 0x00 0x00
 
-# CHECK: cmp EAX, 0
+# CHECK: cmp eax, 0
 0x3d 0x00 0x00 0x00 0x00
 
-# CHECK: cmp RAX, 0
+# CHECK: cmp rax, 0
 0x48 0x3d 0x00 0x00 0x00 0x00
 
-# CHECK: test AL, 0
+# CHECK: test al, 0
 0xa8 0x00
 
-# CHECK: test AX, 0
+# CHECK: test ax, 0
 0x66 0xa9 0x00 0x00
 
-# CHECK: test EAX, 0
+# CHECK: test eax, 0
 0xa9 0x00 0x00 0x00 0x00
 
-# CHECK: test RAX, 0
+# CHECK: test rax, 0
 0x48 0xa9 0x00 0x00 0x00 0x00
 
 # CHECK: sysret
@@ -105,17 +105,17 @@
 # CHECK: retf
 0x66 0xcb
 
-# CHECK: vpgatherqq YMM2, QWORD PTR [RDI + 2*YMM1], YMM0
+# CHECK: vpgatherqq ymm2, qword ptr [rdi + 2*ymm1], ymm0
 0xc4 0xe2 0xfd 0x91 0x14 0x4f
 
-# CHECK: vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8
+# CHECK: vpgatherdd xmm10, dword ptr [r15 + 2*xmm9], xmm8
 0xc4 0x02 0x39 0x90 0x14 0x4f
 
-# CHECK: xsave64 OPAQUE PTR [RAX]
+# CHECK: xsave64 opaque ptr [rax]
 0x48 0x0f 0xae 0x20
 
-# CHECK: xrstor64 OPAQUE PTR [RAX]
+# CHECK: xrstor64 opaque ptr [rax]
 0x48 0x0f 0xae 0x28
 
-# CHECK: xsaveopt64 OPAQUE PTR [RAX]
+# CHECK: xsaveopt64 opaque ptr [rax]
 0x48 0x0f 0xae 0x30
diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt
index 9827a18..940b1f7 100644
--- a/test/MC/Disassembler/X86/simple-tests.txt
+++ b/test/MC/Disassembler/X86/simple-tests.txt
@@ -756,7 +756,7 @@
 
 # rdar://13493622 lldb doesn't print the x86 rep/repne prefix when disassembling
 # CHECK: repne
-# CHECK-NEXT: movsd
+# CHECK-NEXT: movsl
 0xf2 0xa5
 # CHECK: repne
 # CHECK-NEXT: movsq
@@ -764,7 +764,35 @@
 # CHECK: repne
 # CHECK-NEXT: movb  $0, (%rax)
 0xf2 0xc6 0x0 0x0
-# CHECK: rep
+
+# rdar://11019859 Support 2013 Haswell RTM instructions and HLE prefixes
+# CHECK: xrelease
 # CHECK-NEXT: lock
 # CHECK-NEXT: incl   (%rax)
 0xf3 0xf0 0xff 0x00
+
+# CHECK: xrelease
+# CHECK-NEXT: xchgl %ebx, %eax
+0xf3 0x93
+# CHECK: xrelease
+# CHECK-NEXT: xchgl %ebx, (%rax)
+0xf3 0x87 0x18
+# CHECK: xrelease
+# CHECK-NEXT: movb %al, (%rbx)
+0xf3 0x88 0x03
+# CHECK: xrelease
+# CHECK-NEXT: movl %eax, (%rbx)
+0xf3 0x89 0x03
+# CHECK: xrelease
+# CHECK-NEXT: movb $1, (%rbx)
+0xf3 0xc6 0x03 0x01
+# CHECK: xrelease
+# CHECK-NEXT: movl $1, (%rbx)
+0xf3 0xc7 0x03 0x01 0x00 0x00 0x00
+
+# CHECK: xacquire
+# CHECK-NEXT: xchgl %ebx, %eax
+0xf2 0x93
+# CHECK: xacquire
+# CHECK-NEXT: xchgl %ebx, (%rax)
+0xf2 0x87 0x18
diff --git a/test/MC/Disassembler/X86/x86-64.txt b/test/MC/Disassembler/X86/x86-64.txt
index c285af7..bf1fa21 100644
--- a/test/MC/Disassembler/X86/x86-64.txt
+++ b/test/MC/Disassembler/X86/x86-64.txt
@@ -127,3 +127,33 @@
 
 # CHECK: stac
 0x0f 0x01 0xcb
+
+# CHECK: movabsb -6066930261531658096, %al
+0xa0 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
+
+# CHECK: movabsb -6066930261531658096, %al
+0x48 0xa0 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
+
+# CHECK: movabsw -6066930261531658096, %ax
+0x66 0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
+
+# CHECK: movabsl -6066930261531658096, %eax
+0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
+
+# CHECK: movabsq -6066930261531658096, %rax
+0x48 0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
+
+# CHECK: movabsb %al, -6066930261531658096
+0xa2 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
+
+# CHECK: movabsb %al, -6066930261531658096
+0x48 0xa2 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
+
+# CHECK: movabsw %ax, -6066930261531658096
+0x66 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
+
+# CHECK: movabsl %eax, -6066930261531658096
+0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
+
+# CHECK: movabsq %rax, -6066930261531658096
+0x48 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
diff --git a/test/MC/ELF/bss-large.ll b/test/MC/ELF/bss-large.ll
new file mode 100644
index 0000000..e2a7a23
--- /dev/null
+++ b/test/MC/ELF/bss-large.ll
@@ -0,0 +1,13 @@
+; RUN: llc -filetype=obj %s -o %t
+
+; PR16338 - ICE when compiling very large two-dimensional array
+; Check if a huge object can be put into bss section
+; C++ code is:
+;   int a[60666][60666];
+
+; ModuleID = 'test.c'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+@a0 = addrspace(1) global [4 x [4 x i32]] zeroinitializer, align 16
+@a = global [60666 x [60666 x i32]] zeroinitializer, align 16
diff --git a/test/MC/ELF/comdat-reloc.s b/test/MC/ELF/comdat-reloc.s
new file mode 100644
index 0000000..d893a7b
--- /dev/null
+++ b/test/MC/ELF/comdat-reloc.s
@@ -0,0 +1,29 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck %s
+
+  .text
+  .globl  hello
+  .type  hello,@function
+hello:
+  call  world
+  ret
+
+  .section  .text.world,"axG",@progbits,world,comdat
+  .type  world,@function
+world:
+  call  doctor
+  ret
+
+// CHECK:  Name: .group
+// CHECK-NOT: SectionData
+// CHECK: SectionData
+// CHECK-NEXT: 0000: 01000000 06000000 07000000
+
+// CHECK: Index: 6
+// CHECK-NEXT: Name: .text.world
+// CHECK-NOT: Section {
+// CHECK: SHF_GROUP
+
+// CHECK: Index: 7
+// CHECK-NEXT: Name: .rela.text.world
+// CHECK-NOT: Section {
+// CHECK: SHF_GROUP
diff --git a/test/MC/ELF/comdat.s b/test/MC/ELF/comdat.s
index f9469df..6dbe583 100644
--- a/test/MC/ELF/comdat.s
+++ b/test/MC/ELF/comdat.s
@@ -39,7 +39,7 @@
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Address: 0x0
 // CHECK-NEXT:     Offset: 0x54
-// CHECK-NEXT:     Size: 8
+// CHECK-NEXT:     Size: 12
 // CHECK-NEXT:     Link: 13
 // CHECK-NEXT:     Info: 13
 // CHECK-NEXT:     AddressAlignment: 4
diff --git a/test/MC/ELF/debug-line2.s b/test/MC/ELF/debug-line2.s
new file mode 100644
index 0000000..71b0b16
--- /dev/null
+++ b/test/MC/ELF/debug-line2.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck %s
+
+// Test that two subsequent .loc directives generate two
+// distinct line table entries.
+
+// CHECK:        Section {
+// CHECK:          Name: .debug_line
+// CHECK-NEXT:     Type: SHT_PROGBITS
+// CHECK-NEXT:     Flags [
+// CHECK-NEXT:     ]
+// CHECK-NEXT:     Address: 0x0
+// CHECK-NEXT:     Offset:
+// CHECK-NEXT:     Size: 56
+// CHECK-NEXT:     Link: 0
+// CHECK-NEXT:     Info: 0
+// CHECK-NEXT:     AddressAlignment: 1
+// CHECK-NEXT:     EntrySize: 0
+// CHECK-NEXT:     SectionData (
+// CHECK-NEXT:       0000: 34000000 02001C00 00000101 FB0E0D00
+// CHECK-NEXT:       0010: 01010101 00000001 00000100 666F6F2E
+// CHECK-NEXT:       0020: 63000000 00000009 02000000 00000000
+// CHECK-NEXT:       0030: 00011302 01000101
+// CHECK-NEXT:     )
+// CHECK-NEXT:   }
+
+	.section	.debug_line,"",@progbits
+	.text
+
+	.file 1 "foo.c"
+	.loc 1 1 0
+	.loc 1 2 0
+	nop
diff --git a/test/MC/ELF/relocation.s b/test/MC/ELF/relocation.s
index 18d43da..d2c4f2e 100644
--- a/test/MC/ELF/relocation.s
+++ b/test/MC/ELF/relocation.s
@@ -18,7 +18,7 @@ bar:
         movq	foo(%rip), %rdx
         leaq    foo-bar(%r14),%r14
         addq	$bar,%rax         # R_X86_64_32S
-
+	.quad	foo@DTPOFF
 
 // CHECK:        Section {
 // CHECK:          Name: .rela.text
@@ -38,6 +38,7 @@ bar:
 // CHECK-NEXT:       0x55 R_X86_64_PC32     foo 0xFFFFFFFFFFFFFFFC
 // CHECK-NEXT:       0x5C R_X86_64_PC32     foo 0x5C
 // CHECK-NEXT:       0x63 R_X86_64_32S      .text 0x0
+// CHECK-NEXT:       0x67 R_X86_64_DTPOFF64 foo 0x0
 // CHECK-NEXT:     ]
 // CHECK-NEXT:   }
 
diff --git a/test/MC/MBlaze/lit.local.cfg b/test/MC/MBlaze/lit.local.cfg
deleted file mode 100644
index b0e1d85..0000000
--- a/test/MC/MBlaze/lit.local.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-config.suffixes = ['.ll', '.c', '.cpp', '.s']
-
-targets = set(config.root.targets_to_build.split())
-if not 'MBlaze' in targets:
-    config.unsupported = True
-
diff --git a/test/MC/MBlaze/mblaze_branch.s b/test/MC/MBlaze/mblaze_branch.s
deleted file mode 100644
index 2ec4319..0000000
--- a/test/MC/MBlaze/mblaze_branch.s
+++ /dev/null
@@ -1,197 +0,0 @@
-# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
-
-# Test to make sure that all of the TYPE-A instructions supported by
-# the Microblaze can be parsed by the assembly parser.
-
-# TYPE A:   OPCODE RD    RA    RB    FLAGS
-# BINARY:   000000 00000 00000 00000 00000000000
-
-# CHECK:    beq
-# BINARY:   100111 00000 00010 00011 00000000000
-# CHECK:    encoding: [0x9c,0x02,0x18,0x00]
-            beq     r2, r3
-
-# CHECK:    bge
-# BINARY:   100111 00101 00010 00011 00000000000
-# CHECK:    encoding: [0x9c,0xa2,0x18,0x00]
-            bge     r2, r3
-
-# CHECK:    bgt
-# BINARY:   100111 00100 00010 00011 00000000000
-# CHECK:    encoding: [0x9c,0x82,0x18,0x00]
-            bgt     r2, r3
-
-# CHECK:    ble
-# BINARY:   100111 00011 00010 00011 00000000000
-# CHECK:    encoding: [0x9c,0x62,0x18,0x00]
-            ble     r2, r3
-
-# CHECK:    blt
-# BINARY:   100111 00010 00010 00011 00000000000
-# CHECK:    encoding: [0x9c,0x42,0x18,0x00]
-            blt     r2, r3
-
-# CHECK:    bne
-# BINARY:   100111 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x9c,0x22,0x18,0x00]
-            bne     r2, r3
-
-# CHECK:    beqd
-# BINARY:   100111 10000 00010 00011 00000000000
-# CHECK:    encoding: [0x9e,0x02,0x18,0x00]
-            beqd    r2, r3
-
-# CHECK:    bged
-# BINARY:   100111 10101 00010 00011 00000000000
-# CHECK:    encoding: [0x9e,0xa2,0x18,0x00]
-            bged    r2, r3
-
-# CHECK:    bgtd
-# BINARY:   100111 10100 00010 00011 00000000000
-# CHECK:    encoding: [0x9e,0x82,0x18,0x00]
-            bgtd    r2, r3
-
-# CHECK:    bled
-# BINARY:   100111 10011 00010 00011 00000000000
-# CHECK:    encoding: [0x9e,0x62,0x18,0x00]
-            bled    r2, r3
-
-# CHECK:    bltd
-# BINARY:   100111 10010 00010 00011 00000000000
-# CHECK:    encoding: [0x9e,0x42,0x18,0x00]
-            bltd    r2, r3
-
-# CHECK:    bned
-# BINARY:   100111 10001 00010 00011 00000000000
-# CHECK:    encoding: [0x9e,0x22,0x18,0x00]
-            bned    r2, r3
-
-# CHECK:    br
-# BINARY:   100110 00000 00000 00011 00000000000
-# CHECK:    encoding: [0x98,0x00,0x18,0x00]
-            br      r3
-
-# CHECK:    bra
-# BINARY:   100110 00000 01000 00011 00000000000
-# CHECK:    encoding: [0x98,0x08,0x18,0x00]
-            bra     r3
-
-# CHECK:    brd
-# BINARY:   100110 00000 10000 00011 00000000000
-# CHECK:    encoding: [0x98,0x10,0x18,0x00]
-            brd     r3
-
-# CHECK:    brad
-# BINARY:   100110 00000 11000 00011 00000000000
-# CHECK:    encoding: [0x98,0x18,0x18,0x00]
-            brad    r3
-
-# CHECK:    brld
-# BINARY:   100110 01111 10100 00011 00000000000
-# CHECK:    encoding: [0x99,0xf4,0x18,0x00]
-            brld    r15, r3
-
-# CHECK:    brald
-# BINARY:   100110 01111 11100 00011 00000000000
-# CHECK:    encoding: [0x99,0xfc,0x18,0x00]
-            brald   r15, r3
-
-# CHECK:    brk
-# BINARY:   100110 01111 01100 00011 00000000000
-# CHECK:    encoding: [0x99,0xec,0x18,0x00]
-            brk     r15, r3
-
-# CHECK:    beqi
-# BINARY:   101111 00000 00010 0000000000000000
-# CHECK:    encoding: [0xbc,0x02,0x00,0x00]
-            beqi    r2, 0
-
-# CHECK:    bgei
-# BINARY:   101111 00101 00010 0000000000000000
-# CHECK:    encoding: [0xbc,0xa2,0x00,0x00]
-            bgei    r2, 0
-
-# CHECK:    bgti
-# BINARY:   101111 00100 00010 0000000000000000
-# CHECK:    encoding: [0xbc,0x82,0x00,0x00]
-            bgti    r2, 0
-
-# CHECK:    blei
-# BINARY:   101111 00011 00010 0000000000000000
-# CHECK:    encoding: [0xbc,0x62,0x00,0x00]
-            blei    r2, 0
-
-# CHECK:    blti
-# BINARY:   101111 00010 00010 0000000000000000
-# CHECK:    encoding: [0xbc,0x42,0x00,0x00]
-            blti    r2, 0
-
-# CHECK:    bnei
-# BINARY:   101111 00001 00010 0000000000000000
-# CHECK:    encoding: [0xbc,0x22,0x00,0x00]
-            bnei    r2, 0
-
-# CHECK:    beqid
-# BINARY:   101111 10000 00010 0000000000000000
-# CHECK:    encoding: [0xbe,0x02,0x00,0x00]
-            beqid   r2, 0
-
-# CHECK:    bgeid
-# BINARY:   101111 10101 00010 0000000000000000
-# CHECK:    encoding: [0xbe,0xa2,0x00,0x00]
-            bgeid   r2, 0
-
-# CHECK:    bgtid
-# BINARY:   101111 10100 00010 0000000000000000
-# CHECK:    encoding: [0xbe,0x82,0x00,0x00]
-            bgtid   r2, 0
-
-# CHECK:    bleid
-# BINARY:   101111 10011 00010 0000000000000000
-# CHECK:    encoding: [0xbe,0x62,0x00,0x00]
-            bleid   r2, 0
-
-# CHECK:    bltid
-# BINARY:   101111 10010 00010 0000000000000000
-# CHECK:    encoding: [0xbe,0x42,0x00,0x00]
-            bltid   r2, 0
-
-# CHECK:    bneid
-# BINARY:   101111 10001 00010 0000000000000000
-# CHECK:    encoding: [0xbe,0x22,0x00,0x00]
-            bneid   r2, 0
-
-# CHECK:    bri
-# BINARY:   101110 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb8,0x00,0x00,0x00]
-            bri     0
-
-# CHECK:    brai
-# BINARY:   101110 00000 01000 0000000000000000
-# CHECK:    encoding: [0xb8,0x08,0x00,0x00]
-            brai    0
-
-# CHECK:    brid
-# BINARY:   101110 00000 10000 0000000000000000
-# CHECK:    encoding: [0xb8,0x10,0x00,0x00]
-            brid    0
-
-# CHECK:    braid
-# BINARY:   101110 00000 11000 0000000000000000
-# CHECK:    encoding: [0xb8,0x18,0x00,0x00]
-            braid   0
-
-# CHECK:    brlid
-# BINARY:   101110 01111 10100 0000000000000000
-# CHECK:    encoding: [0xb9,0xf4,0x00,0x00]
-            brlid   r15, 0
-
-# CHECK:    bralid
-# BINARY:   101110 01111 11100 0000000000000000
-# CHECK:    encoding: [0xb9,0xfc,0x00,0x00]
-            bralid  r15, 0
-
-# CHECK:    brki
-# BINARY:   101110 01111 01100 0000000000000000
-# CHECK:    encoding: [0xb9,0xec,0x00,0x00]
-            brki    r15, 0
diff --git a/test/MC/MBlaze/mblaze_fpu.s b/test/MC/MBlaze/mblaze_fpu.s
deleted file mode 100644
index a3b6838..0000000
--- a/test/MC/MBlaze/mblaze_fpu.s
+++ /dev/null
@@ -1,77 +0,0 @@
-# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
-
-# Test to ensure that all FPU instructions can be parsed by the
-# assembly parser correctly.
-
-# TYPE A:   OPCODE RD    RA    RB    FLAGS
-# BINARY:   011011 00000 00000 00000 00000000000
-
-# CHECK:    fadd
-# BINARY:   010110 00000 00001 00010 00000000000
-# CHECK:    encoding: [0x58,0x01,0x10,0x00]
-            fadd         r0, r1, r2
-
-# CHECK:    frsub
-# BINARY:   010110 00000 00001 00010 00010000000
-# CHECK:    encoding: [0x58,0x01,0x10,0x80]
-            frsub        r0, r1, r2
-
-# CHECK:    fmul
-# BINARY:   010110 00000 00001 00010 00100000000
-# CHECK:    encoding: [0x58,0x01,0x11,0x00]
-            fmul         r0, r1, r2
-
-# CHECK:    fdiv
-# BINARY:   010110 00000 00001 00010 00110000000
-# CHECK:    encoding: [0x58,0x01,0x11,0x80]
-            fdiv         r0, r1, r2
-
-# CHECK:    fsqrt
-# BINARY:   010110 00000 00001 00000 01110000000
-# CHECK:    encoding: [0x58,0x01,0x03,0x80]
-            fsqrt        r0, r1
-
-# CHECK:    fint
-# BINARY:   010110 00000 00001 00000 01100000000
-# CHECK:    encoding: [0x58,0x01,0x03,0x00]
-            fint         r0, r1
-
-# CHECK:    flt
-# BINARY:   010110 00000 00001 00000 01010000000
-# CHECK:    encoding: [0x58,0x01,0x02,0x80]
-            flt          r0, r1
-
-# CHECK:    fcmp.un
-# BINARY:   010110 00000 00001 00010 01000000000
-# CHECK:    encoding: [0x58,0x01,0x12,0x00]
-            fcmp.un     r0, r1, r2
-
-# CHECK:    fcmp.lt
-# BINARY:   010110 00000 00001 00010 01000010000
-# CHECK:    encoding: [0x58,0x01,0x12,0x10]
-            fcmp.lt     r0, r1, r2
-
-# CHECK:    fcmp.eq
-# BINARY:   010110 00000 00001 00010 01000100000
-# CHECK:    encoding: [0x58,0x01,0x12,0x20]
-            fcmp.eq     r0, r1, r2
-
-# CHECK:    fcmp.le
-# BINARY:   010110 00000 00001 00010 01000110000
-# CHECK:    encoding: [0x58,0x01,0x12,0x30]
-            fcmp.le     r0, r1, r2
-
-# CHECK:    fcmp.gt
-# BINARY:   010110 00000 00001 00010 01001000000
-# CHECK:    encoding: [0x58,0x01,0x12,0x40]
-            fcmp.gt     r0, r1, r2
-
-# CHECK:    fcmp.ne
-# BINARY:   010110 00000 00001 00010 01001010000
-# CHECK:    encoding: [0x58,0x01,0x12,0x50]
-            fcmp.ne     r0, r1, r2
-
-# CHECK:    fcmp.ge
-# BINARY:   010110 00000 00001 00010 01001100000
-# CHECK:    encoding: [0x58,0x01,0x12,0x60]
-            fcmp.ge     r0, r1, r2
diff --git a/test/MC/MBlaze/mblaze_fsl.s b/test/MC/MBlaze/mblaze_fsl.s
deleted file mode 100644
index d0a42b3..0000000
--- a/test/MC/MBlaze/mblaze_fsl.s
+++ /dev/null
@@ -1,568 +0,0 @@
-# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
-
-# Test to ensure that all FSL immediate operands and FSL instructions
-# can be parsed by the assembly parser correctly.
-
-# TYPE F:   OPCODE RD           NCTAE        FSL
-# BINARY:   011011 00000 000000 00000 000000 0000
-
-# TYPE FD:  OPCODE RD          RB      NCTAE
-# BINARY:   011011 00000 00000 00000 0 00000 00000
-
-# TYPE FP:  OPCODE       RA      NCTA         FSL
-#           000000 00000 00000 1 0000 0000000 0000
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x00,0x00]
-            get         r0, rfsl0
-
-# CHECK:    nget
-# BINARY:   011011 00000 000000 10000 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x40,0x00]
-            nget        r0, rfsl0
-
-# CHECK:    cget
-# BINARY:   011011 00000 000000 01000 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x20,0x00]
-            cget        r0, rfsl0
-
-# CHECK:    ncget
-# BINARY:   011011 00000 000000 11000 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x60,0x00]
-            ncget       r0, rfsl0
-
-# CHECK:    tget
-# BINARY:   011011 00000 000000 00100 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x10,0x00]
-            tget        r0, rfsl0
-
-# CHECK:    tnget
-# BINARY:   011011 00000 000000 10100 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x50,0x00]
-            tnget       r0, rfsl0
-
-# CHECK:    tcget
-# BINARY:   011011 00000 000000 01100 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x30,0x00]
-            tcget       r0, rfsl0
-
-# CHECK:    tncget
-# BINARY:   011011 00000 000000 11100 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x70,0x00]
-            tncget      r0, rfsl0
-
-# CHECK:    aget
-# BINARY:   011011 00000 000000 00010 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x08,0x00]
-            aget        r0, rfsl0
-
-# CHECK:    naget
-# BINARY:   011011 00000 000000 10010 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x48,0x00]
-            naget       r0, rfsl0
-
-# CHECK:    caget
-# BINARY:   011011 00000 000000 01010 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x28,0x00]
-            caget       r0, rfsl0
-
-# CHECK:    ncaget
-# BINARY:   011011 00000 000000 11010 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x68,0x00]
-            ncaget      r0, rfsl0
-
-# CHECK:    taget
-# BINARY:   011011 00000 000000 00110 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x18,0x00]
-            taget       r0, rfsl0
-
-# CHECK:    tnaget
-# BINARY:   011011 00000 000000 10110 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x58,0x00]
-            tnaget      r0, rfsl0
-
-# CHECK:    tcaget
-# BINARY:   011011 00000 000000 01110 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x38,0x00]
-            tcaget      r0, rfsl0
-
-# CHECK:    tncaget
-# BINARY:   011011 00000 000000 11110 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x78,0x00]
-            tncaget     r0, rfsl0
-
-# CHECK:    eget
-# BINARY:   011011 00000 000000 00001 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x04,0x00]
-            eget        r0, rfsl0
-
-# CHECK:    neget
-# BINARY:   011011 00000 000000 10001 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x44,0x00]
-            neget       r0, rfsl0
-
-# CHECK:    ecget
-# BINARY:   011011 00000 000000 01001 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x24,0x00]
-            ecget       r0, rfsl0
-
-# CHECK:    necget
-# BINARY:   011011 00000 000000 11001 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x64,0x00]
-            necget      r0, rfsl0
-
-# CHECK:    teget
-# BINARY:   011011 00000 000000 00101 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x14,0x00]
-            teget       r0, rfsl0
-
-# CHECK:    tneget
-# BINARY:   011011 00000 000000 10101 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x54,0x00]
-            tneget      r0, rfsl0
-
-# CHECK:    tecget
-# BINARY:   011011 00000 000000 01101 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x34,0x00]
-            tecget      r0, rfsl0
-
-# CHECK:    tnecget
-# BINARY:   011011 00000 000000 11101 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x74,0x00]
-            tnecget     r0, rfsl0
-
-# CHECK:    eaget
-# BINARY:   011011 00000 000000 00011 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x0c,0x00]
-            eaget       r0, rfsl0
-
-# CHECK:    neaget
-# BINARY:   011011 00000 000000 10011 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x4c,0x00]
-            neaget      r0, rfsl0
-
-# CHECK:    ecaget
-# BINARY:   011011 00000 000000 01011 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x2c,0x00]
-            ecaget      r0, rfsl0
-
-# CHECK:    necaget
-# BINARY:   011011 00000 000000 11011 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x6c,0x00]
-            necaget     r0, rfsl0
-
-# CHECK:    teaget
-# BINARY:   011011 00000 000000 00111 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x1c,0x00]
-            teaget      r0, rfsl0
-
-# CHECK:    tneaget
-# BINARY:   011011 00000 000000 10111 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x5c,0x00]
-            tneaget     r0, rfsl0
-
-# CHECK:    tecaget
-# BINARY:   011011 00000 000000 01111 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x3c,0x00]
-            tecaget     r0, rfsl0
-
-# CHECK:    tnecaget
-# BINARY:   011011 00000 000000 11111 000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x7c,0x00]
-            tnecaget    r0, rfsl0
-
-# CHECK:    getd
-# BINARY:   010011 00000 00000 00001 0 00000 00000
-# CHECK:    encoding: [0x4c,0x00,0x08,0x00]
-            getd        r0, r1
-
-# CHECK:    ngetd
-# BINARY:   010011 00000 00000 00001 0 10000 00000
-# CHECK:    encoding: [0x4c,0x00,0x0a,0x00]
-            ngetd       r0, r1
-
-# CHECK:    cgetd
-# BINARY:   010011 00000 00000 00001 0 01000 00000
-# CHECK:    encoding: [0x4c,0x00,0x09,0x00]
-            cgetd       r0, r1
-
-# CHECK:    ncgetd
-# BINARY:   010011 00000 00000 00001 0 11000 00000
-# CHECK:    encoding: [0x4c,0x00,0x0b,0x00]
-            ncgetd      r0, r1
-
-# CHECK:    tgetd
-# BINARY:   010011 00000 00000 00001 0 00100 00000
-# CHECK:    encoding: [0x4c,0x00,0x08,0x80]
-            tgetd       r0, r1
-
-# CHECK:    tngetd
-# BINARY:   010011 00000 00000 00001 0 10100 00000
-# CHECK:    encoding: [0x4c,0x00,0x0a,0x80]
-            tngetd      r0, r1
-
-# CHECK:    tcgetd
-# BINARY:   010011 00000 00000 00001 0 01100 00000
-# CHECK:    encoding: [0x4c,0x00,0x09,0x80]
-            tcgetd      r0, r1
-
-# CHECK:    tncgetd
-# BINARY:   010011 00000 00000 00001 0 11100 00000
-# CHECK:    encoding: [0x4c,0x00,0x0b,0x80]
-            tncgetd     r0, r1
-
-# CHECK:    agetd
-# BINARY:   010011 00000 00000 00001 0 00010 00000
-# CHECK:    encoding: [0x4c,0x00,0x08,0x40]
-            agetd       r0, r1
-
-# CHECK:    nagetd
-# BINARY:   010011 00000 00000 00001 0 10010 00000
-# CHECK:    encoding: [0x4c,0x00,0x0a,0x40]
-            nagetd      r0, r1
-
-# CHECK:    cagetd
-# BINARY:   010011 00000 00000 00001 0 01010 00000
-# CHECK:    encoding: [0x4c,0x00,0x09,0x40]
-            cagetd     r0, r1
-
-# CHECK:    ncagetd
-# BINARY:   010011 00000 00000 00001 0 11010 00000
-# CHECK:    encoding: [0x4c,0x00,0x0b,0x40]
-            ncagetd     r0, r1
-
-# CHECK:    tagetd
-# BINARY:   010011 00000 00000 00001 0 00110 00000
-# CHECK:    encoding: [0x4c,0x00,0x08,0xc0]
-            tagetd      r0, r1
-
-# CHECK:    tnagetd
-# BINARY:   010011 00000 00000 00001 0 10110 00000
-# CHECK:    encoding: [0x4c,0x00,0x0a,0xc0]
-            tnagetd     r0, r1
-
-# CHECK:    tcagetd
-# BINARY:   010011 00000 00000 00001 0 01110 00000
-# CHECK:    encoding: [0x4c,0x00,0x09,0xc0]
-            tcagetd     r0, r1
-
-# CHECK:    tncagetd
-# BINARY:   010011 00000 00000 00001 0 11110 00000
-# CHECK:    encoding: [0x4c,0x00,0x0b,0xc0]
-            tncagetd    r0, r1
-
-# CHECK:    egetd
-# BINARY:   010011 00000 00000 00001 0 00001 00000
-# CHECK:    encoding: [0x4c,0x00,0x08,0x20]
-            egetd       r0, r1
-
-# CHECK:    negetd
-# BINARY:   010011 00000 00000 00001 0 10001 00000
-# CHECK:    encoding: [0x4c,0x00,0x0a,0x20]
-            negetd      r0, r1
-
-# CHECK:    ecgetd
-# BINARY:   010011 00000 00000 00001 0 01001 00000
-# CHECK:    encoding: [0x4c,0x00,0x09,0x20]
-            ecgetd      r0, r1
-
-# CHECK:    necgetd
-# BINARY:   010011 00000 00000 00001 0 11001 00000
-# CHECK:    encoding: [0x4c,0x00,0x0b,0x20]
-            necgetd     r0, r1
-
-# CHECK:    tegetd
-# BINARY:   010011 00000 00000 00001 0 00101 00000
-# CHECK:    encoding: [0x4c,0x00,0x08,0xa0]
-            tegetd      r0, r1
-
-# CHECK:    tnegetd
-# BINARY:   010011 00000 00000 00001 0 10101 00000
-# CHECK:    encoding: [0x4c,0x00,0x0a,0xa0]
-            tnegetd     r0, r1
-
-# CHECK:    tecgetd
-# BINARY:   010011 00000 00000 00001 0 01101 00000
-# CHECK:    encoding: [0x4c,0x00,0x09,0xa0]
-            tecgetd     r0, r1
-
-# CHECK:    tnecgetd
-# BINARY:   010011 00000 00000 00001 0 11101 00000
-# CHECK:    encoding: [0x4c,0x00,0x0b,0xa0]
-            tnecgetd    r0, r1
-
-# CHECK:    eagetd
-# BINARY:   010011 00000 00000 00001 0 00011 00000
-# CHECK:    encoding: [0x4c,0x00,0x08,0x60]
-            eagetd      r0, r1
-
-# CHECK:    neagetd
-# BINARY:   010011 00000 00000 00001 0 10011 00000
-# CHECK:    encoding: [0x4c,0x00,0x0a,0x60]
-            neagetd     r0, r1
-
-# CHECK:    ecagetd
-# BINARY:   010011 00000 00000 00001 0 01011 00000
-# CHECK:    encoding: [0x4c,0x00,0x09,0x60]
-            ecagetd     r0, r1
-
-# CHECK:    necagetd
-# BINARY:   010011 00000 00000 00001 0 11011 00000
-# CHECK:    encoding: [0x4c,0x00,0x0b,0x60]
-            necagetd    r0, r1
-
-# CHECK:    teagetd
-# BINARY:   010011 00000 00000 00001 0 00111 00000
-# CHECK:    encoding: [0x4c,0x00,0x08,0xe0]
-            teagetd     r0, r1
-
-# CHECK:    tneagetd
-# BINARY:   010011 00000 00000 00001 0 10111 00000
-# CHECK:    encoding: [0x4c,0x00,0x0a,0xe0]
-            tneagetd    r0, r1
-
-# CHECK:    tecagetd
-# BINARY:   010011 00000 00000 00001 0 01111 00000
-# CHECK:    encoding: [0x4c,0x00,0x09,0xe0]
-            tecagetd    r0, r1
-
-# CHECK:    tnecagetd
-# BINARY:   010011 00000 00000 00001 0 11111 00000
-# CHECK:    encoding: [0x4c,0x00,0x0b,0xe0]
-            tnecagetd   r0, r1
-
-# CHECK:    put
-# BINARY:   011011 00000 00000 1 0000 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x80,0x00]
-            put         r0, rfsl0
-
-# CHECK:    aput
-# BINARY:   011011 00000 00000 1 0001 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x88,0x00]
-            aput        r0, rfsl0
-
-# CHECK:    cput
-# BINARY:   011011 00000 00000 1 0100 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0xa0,0x00]
-            cput        r0, rfsl0
-
-# CHECK:    caput
-# BINARY:   011011 00000 00000 1 0101 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0xa8,0x00]
-            caput       r0, rfsl0
-
-# CHECK:    nput
-# BINARY:   011011 00000 00000 1 1000 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0xc0,0x00]
-            nput        r0, rfsl0
-
-# CHECK:    naput
-# BINARY:   011011 00000 00000 1 1001 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0xc8,0x00]
-            naput       r0, rfsl0
-
-# CHECK:    ncput
-# BINARY:   011011 00000 00000 1 1100 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0xe0,0x00]
-            ncput       r0, rfsl0
-
-# CHECK:    ncaput
-# BINARY:   011011 00000 00000 1 1101 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0xe8,0x00]
-            ncaput      r0, rfsl0
-
-# CHECK:    tput
-# BINARY:   011011 00000 00000 1 0010 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x90,0x00]
-            tput        rfsl0
-
-# CHECK:    taput
-# BINARY:   011011 00000 00000 1 0011 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0x98,0x00]
-            taput       rfsl0
-
-# CHECK:    tcput
-# BINARY:   011011 00000 00000 1 0110 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0xb0,0x00]
-            tcput       rfsl0
-
-# CHECK:    tcaput
-# BINARY:   011011 00000 00000 1 0111 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0xb8,0x00]
-            tcaput      rfsl0
-
-# CHECK:    tnput
-# BINARY:   011011 00000 00000 1 1010 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0xd0,0x00]
-            tnput       rfsl0
-
-# CHECK:    tnaput
-# BINARY:   011011 00000 00000 1 1011 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0xd8,0x00]
-            tnaput      rfsl0
-
-# CHECK:    tncput
-# BINARY:   011011 00000 00000 1 1110 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0xf0,0x00]
-            tncput      rfsl0
-
-# CHECK:    tncaput
-# BINARY:   011011 00000 00000 1 1111 0000000 0000
-# CHECK:    encoding: [0x6c,0x00,0xf8,0x00]
-            tncaput     rfsl0
-
-# CHECK:    putd
-# BINARY:   010011 00000 00000 00001 1 0000 000000
-# CHECK:    encoding: [0x4c,0x00,0x0c,0x00]
-            putd        r0, r1
-
-# CHECK:    aputd
-# BINARY:   010011 00000 00000 00001 1 0001 000000
-# CHECK:    encoding: [0x4c,0x00,0x0c,0x40]
-            aputd       r0, r1
-
-# CHECK:    cputd
-# BINARY:   010011 00000 00000 00001 1 0100 000000
-# CHECK:    encoding: [0x4c,0x00,0x0d,0x00]
-            cputd       r0, r1
-
-# CHECK:    caputd
-# BINARY:   010011 00000 00000 00001 1 0101 000000
-# CHECK:    encoding: [0x4c,0x00,0x0d,0x40]
-            caputd      r0, r1
-
-# CHECK:    nputd
-# BINARY:   010011 00000 00000 00001 1 1000 000000
-# CHECK:    encoding: [0x4c,0x00,0x0e,0x00]
-            nputd       r0, r1
-
-# CHECK:    naputd
-# BINARY:   010011 00000 00000 00001 1 1001 000000
-# CHECK:    encoding: [0x4c,0x00,0x0e,0x40]
-            naputd      r0, r1
-
-# CHECK:    ncputd
-# BINARY:   010011 00000 00000 00001 1 1100 000000
-# CHECK:    encoding: [0x4c,0x00,0x0f,0x00]
-            ncputd      r0, r1
-
-# CHECK:    ncaputd
-# BINARY:   010011 00000 00000 00001 1 1101 000000
-# CHECK:    encoding: [0x4c,0x00,0x0f,0x40]
-            ncaputd     r0, r1
-
-# CHECK:    tputd
-# BINARY:   010011 00000 00000 00001 1 0010 000000
-# CHECK:    encoding: [0x4c,0x00,0x0c,0x80]
-            tputd       r1
-
-# CHECK:    taputd
-# BINARY:   010011 00000 00000 00001 1 0011 000000
-# CHECK:    encoding: [0x4c,0x00,0x0c,0xc0]
-            taputd      r1
-
-# CHECK:    tcputd
-# BINARY:   010011 00000 00000 00001 1 0110 000000
-# CHECK:    encoding: [0x4c,0x00,0x0d,0x80]
-            tcputd      r1
-
-# CHECK:    tcaputd
-# BINARY:   010011 00000 00000 00001 1 0111 000000
-# CHECK:    encoding: [0x4c,0x00,0x0d,0xc0]
-            tcaputd     r1
-
-# CHECK:    tnputd
-# BINARY:   010011 00000 00000 00001 1 1010 000000
-# CHECK:    encoding: [0x4c,0x00,0x0e,0x80]
-            tnputd      r1
-
-# CHECK:    tnaputd
-# BINARY:   010011 00000 00000 00001 1 1011 000000
-# CHECK:    encoding: [0x4c,0x00,0x0e,0xc0]
-            tnaputd     r1
-
-# CHECK:    tncputd
-# BINARY:   010011 00000 00000 00001 1 1110 000000
-# CHECK:    encoding: [0x4c,0x00,0x0f,0x80]
-            tncputd     r1
-
-# CHECK:    tncaputd
-# BINARY:   010011 00000 00000 00001 1 1111 000000
-# CHECK:    encoding: [0x4c,0x00,0x0f,0xc0]
-            tncaputd    r1
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 0001
-# CHECK:    encoding: [0x6c,0x00,0x00,0x01]
-            get     r0, rfsl1
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 0010
-# CHECK:    encoding: [0x6c,0x00,0x00,0x02]
-            get     r0, rfsl2
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 0011
-# CHECK:    encoding: [0x6c,0x00,0x00,0x03]
-            get     r0, rfsl3
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 0100
-# CHECK:    encoding: [0x6c,0x00,0x00,0x04]
-            get     r0, rfsl4
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 0101
-# CHECK:    encoding: [0x6c,0x00,0x00,0x05]
-            get     r0, rfsl5
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 0110
-# CHECK:    encoding: [0x6c,0x00,0x00,0x06]
-            get     r0, rfsl6
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 0111
-# CHECK:    encoding: [0x6c,0x00,0x00,0x07]
-            get     r0, rfsl7
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 1000
-# CHECK:    encoding: [0x6c,0x00,0x00,0x08]
-            get     r0, rfsl8
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 1001
-# CHECK:    encoding: [0x6c,0x00,0x00,0x09]
-            get     r0, rfsl9
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 1010
-# CHECK:    encoding: [0x6c,0x00,0x00,0x0a]
-            get     r0, rfsl10
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 1011
-# CHECK:    encoding: [0x6c,0x00,0x00,0x0b]
-            get     r0, rfsl11
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 1100
-# CHECK:    encoding: [0x6c,0x00,0x00,0x0c]
-            get     r0, rfsl12
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 1101
-# CHECK:    encoding: [0x6c,0x00,0x00,0x0d]
-            get     r0, rfsl13
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 1110
-# CHECK:    encoding: [0x6c,0x00,0x00,0x0e]
-            get     r0, rfsl14
-
-# CHECK:    get
-# BINARY:   011011 00000 000000 00000 000000 1111
-# CHECK:    encoding: [0x6c,0x00,0x00,0x0f]
-            get     r0, rfsl15
diff --git a/test/MC/MBlaze/mblaze_imm.s b/test/MC/MBlaze/mblaze_imm.s
deleted file mode 100644
index 08b8a0f..0000000
--- a/test/MC/MBlaze/mblaze_imm.s
+++ /dev/null
@@ -1,194 +0,0 @@
-# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
-
-# In the microblaze instruction set, any TYPE-B instruction with a
-# signed immediate value requiring more than 16-bits must be prefixed
-# with an IMM instruction that contains the high 16-bits. The higher
-# 16-bits are then combined with the lower 16-bits in the original
-# instruction to form a 32-bit immediate value.
-#
-# The generation of IMM instructions is handled automatically by the
-# code emitter. Test to ensure that IMM instructions are generated
-# when they are suppose to and are not generated when they are not
-# needed.
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x00000000
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000000000001
-# CHECK:    encoding: [0x20,0x00,0x00,0x01]
-            addi    r0, r0, 0x00000001
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000000000010
-# CHECK:    encoding: [0x20,0x00,0x00,0x02]
-            addi    r0, r0, 0x00000002
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000000000100
-# CHECK:    encoding: [0x20,0x00,0x00,0x04]
-            addi    r0, r0, 0x00000004
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000000001000
-# CHECK:    encoding: [0x20,0x00,0x00,0x08]
-            addi    r0, r0, 0x00000008
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000000010000
-# CHECK:    encoding: [0x20,0x00,0x00,0x10]
-            addi    r0, r0, 0x00000010
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000000100000
-# CHECK:    encoding: [0x20,0x00,0x00,0x20]
-            addi    r0, r0, 0x00000020
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000001000000
-# CHECK:    encoding: [0x20,0x00,0x00,0x40]
-            addi    r0, r0, 0x00000040
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000010000000
-# CHECK:    encoding: [0x20,0x00,0x00,0x80]
-            addi    r0, r0, 0x00000080
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000100000000
-# CHECK:    encoding: [0x20,0x00,0x01,0x00]
-            addi    r0, r0, 0x00000100
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000001000000000
-# CHECK:    encoding: [0x20,0x00,0x02,0x00]
-            addi    r0, r0, 0x00000200
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000010000000000
-# CHECK:    encoding: [0x20,0x00,0x04,0x00]
-            addi    r0, r0, 0x00000400
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000100000000000
-# CHECK:    encoding: [0x20,0x00,0x08,0x00]
-            addi    r0, r0, 0x00000800
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0001000000000000
-# CHECK:    encoding: [0x20,0x00,0x10,0x00]
-            addi    r0, r0, 0x00001000
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0010000000000000
-# CHECK:    encoding: [0x20,0x00,0x20,0x00]
-            addi    r0, r0, 0x00002000
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0100000000000000
-# CHECK:    encoding: [0x20,0x00,0x40,0x00]
-            addi    r0, r0, 0x00004000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0000000000000000
-# BINARY:   001000 00000 00000 1000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x00,0x00,0x20,0x00,0x80,0x00]
-            addi    r0, r0, 0x00008000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0000000000000001
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x00,0x01,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x00010000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0000000000000010
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x00,0x02,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x00020000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0000000000000100
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x00,0x04,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x00040000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0000000000001000
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x00,0x08,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x00080000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0000000000010000
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x00,0x10,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x00100000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0000000000100000
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x00,0x20,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x00200000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0000000001000000
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x00,0x40,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x00400000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0000000010000000
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x00,0x80,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x00800000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0000000100000000
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x01,0x00,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x01000000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0000001000000000
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x02,0x00,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x02000000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0000010000000000
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x04,0x00,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x04000000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0000100000000000
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x08,0x00,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x08000000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0001000000000000
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x10,0x00,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x10000000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0010000000000000
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x20,0x00,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x20000000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 0100000000000000
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x40,0x00,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x40000000
-
-# CHECK:    addi
-# BINARY:   101100 00000 00000 1000000000000000
-#           001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0xb0,0x00,0x80,0x00,0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0x80000000
diff --git a/test/MC/MBlaze/mblaze_memory.s b/test/MC/MBlaze/mblaze_memory.s
deleted file mode 100644
index fe74475..0000000
--- a/test/MC/MBlaze/mblaze_memory.s
+++ /dev/null
@@ -1,107 +0,0 @@
-# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
-
-# Test to make sure that all of the TYPE-A instructions supported by
-# the Microblaze can be parsed by the assembly parser.
-
-# TYPE A:   OPCODE RD    RA    RB    FLAGS
-# BINARY:   000000 00000 00000 00000 00000000000
-
-# CHECK:    lbu
-# BINARY:   110000 00001 00010 00011 00000000000
-# CHECK:    encoding: [0xc0,0x22,0x18,0x00]
-            lbu     r1, r2, r3
-
-# CHECK:    lbur
-# BINARY:   110000 00001 00010 00011 01000000000
-# CHECK:    encoding: [0xc0,0x22,0x1a,0x00]
-            lbur    r1, r2, r3
-
-# CHECK:    lbui
-# BINARY:   111000 00001 00010 0000000000011100
-# CHECK:    encoding: [0xe0,0x22,0x00,0x1c]
-            lbui    r1, r2, 28
-
-# CHECK:    lhu
-# BINARY:   110001 00001 00010 00011 00000000000
-# CHECK:    encoding: [0xc4,0x22,0x18,0x00]
-            lhu     r1, r2, r3
-
-# CHECK:    lhur
-# BINARY:   110001 00001 00010 00011 01000000000
-# CHECK:    encoding: [0xc4,0x22,0x1a,0x00]
-            lhur    r1, r2, r3
-
-# CHECK:    lhui
-# BINARY:   111001 00001 00010 0000000000011100
-# CHECK:    encoding: [0xe4,0x22,0x00,0x1c]
-            lhui    r1, r2, 28
-
-# CHECK:    lw
-# BINARY:   110010 00001 00010 00011 00000000000
-# CHECK:    encoding: [0xc8,0x22,0x18,0x00]
-            lw      r1, r2, r3
-
-# CHECK:    lwr
-# BINARY:   110010 00001 00010 00011 01000000000
-# CHECK:    encoding: [0xc8,0x22,0x1a,0x00]
-            lwr    r1, r2, r3
-
-# CHECK:    lwi
-# BINARY:   111010 00001 00010 0000000000011100
-# CHECK:    encoding: [0xe8,0x22,0x00,0x1c]
-            lwi     r1, r2, 28
-
-# CHECK:    lwx
-# BINARY:   110010 00001 00010 00011 10000000000
-# CHECK:    encoding: [0xc8,0x22,0x1c,0x00]
-            lwx      r1, r2, r3
-
-# CHECK:    sb
-# BINARY:   110100 00001 00010 00011 00000000000
-# CHECK:    encoding: [0xd0,0x22,0x18,0x00]
-            sb      r1, r2, r3
-
-# CHECK:    sbr
-# BINARY:   110100 00001 00010 00011 01000000000
-# CHECK:    encoding: [0xd0,0x22,0x1a,0x00]
-            sbr     r1, r2, r3
-
-# CHECK:    sbi
-# BINARY:   111100 00001 00010 0000000000011100
-# CHECK:    encoding: [0xf0,0x22,0x00,0x1c]
-            sbi     r1, r2, 28
-
-# CHECK:    sh
-# BINARY:   110101 00001 00010 00011 00000000000
-# CHECK:    encoding: [0xd4,0x22,0x18,0x00]
-            sh      r1, r2, r3
-
-# CHECK:    shr
-# BINARY:   110101 00001 00010 00011 01000000000
-# CHECK:    encoding: [0xd4,0x22,0x1a,0x00]
-            shr     r1, r2, r3
-
-# CHECK:    shi
-# BINARY:   111101 00001 00010 0000000000011100
-# CHECK:    encoding: [0xf4,0x22,0x00,0x1c]
-            shi     r1, r2, 28
-
-# CHECK:    sw
-# BINARY:   110110 00001 00010 00011 00000000000
-# CHECK:    encoding: [0xd8,0x22,0x18,0x00]
-            sw      r1, r2, r3
-
-# CHECK:    swr
-# BINARY:   110110 00001 00010 00011 01000000000
-# CHECK:    encoding: [0xd8,0x22,0x1a,0x00]
-            swr    r1, r2, r3
-
-# CHECK:    swi
-# BINARY:   111110 00001 00010 0000000000011100
-# CHECK:    encoding: [0xf8,0x22,0x00,0x1c]
-            swi     r1, r2, 28
-
-# CHECK:    swx
-# BINARY:   110110 00001 00010 00011 10000000000
-# CHECK:    encoding: [0xd8,0x22,0x1c,0x00]
-            swx      r1, r2, r3
diff --git a/test/MC/MBlaze/mblaze_operands.s b/test/MC/MBlaze/mblaze_operands.s
deleted file mode 100644
index d5f1d80..0000000
--- a/test/MC/MBlaze/mblaze_operands.s
+++ /dev/null
@@ -1,328 +0,0 @@
-# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
-
-# Test to ensure that all register and immediate operands can be parsed by
-# the assembly parser correctly. Testing the parsing of FSL immediate
-# values is done in a different test.
-
-# TYPE A:   OPCODE RD    RA    RB    FLAGS
-# BINARY:   000000 00000 00000 00000 00000000000
-
-# CHECK:    add
-# BINARY:   000000 00000 00000 00000 00000000000
-# CHECK:    encoding: [0x00,0x00,0x00,0x00]
-            add     r0, r0, r0
-
-# CHECK:    add
-# BINARY:   000000 00001 00001 00001 00000000000
-# CHECK:    encoding: [0x00,0x21,0x08,0x00]
-            add     r1, r1, r1
-
-# CHECK:    add
-# BINARY:   000000 00010 00010 00010 00000000000
-# CHECK:    encoding: [0x00,0x42,0x10,0x00]
-            add     r2, r2, r2
-
-# CHECK:    add
-# BINARY:   000000 00011 00011 00011 00000000000
-# CHECK:    encoding: [0x00,0x63,0x18,0x00]
-            add     r3, r3, r3
-
-# CHECK:    add
-# BINARY:   000000 00100 00100 00100 00000000000
-# CHECK:    encoding: [0x00,0x84,0x20,0x00]
-            add     r4, r4, r4
-
-# CHECK:    add
-# BINARY:   000000 00101 00101 00101 00000000000
-# CHECK:    encoding: [0x00,0xa5,0x28,0x00]
-            add     r5, r5, r5
-
-# CHECK:    add
-# BINARY:   000000 00110 00110 00110 00000000000
-# CHECK:    encoding: [0x00,0xc6,0x30,0x00]
-            add     r6, r6, r6
-
-# CHECK:    add
-# BINARY:   000000 00111 00111 00111 00000000000
-# CHECK:    encoding: [0x00,0xe7,0x38,0x00]
-            add     r7, r7, r7
-
-# CHECK:    add
-# BINARY:   000000 01000 01000 01000 00000000000
-# CHECK:    encoding: [0x01,0x08,0x40,0x00]
-            add     r8, r8, r8
-
-# CHECK:    add
-# BINARY:   000000 01001 01001 01001 00000000000
-# CHECK:    encoding: [0x01,0x29,0x48,0x00]
-            add     r9, r9, r9
-
-# CHECK:    add
-# BINARY:   000000 01010 01010 01010 00000000000
-# CHECK:    encoding: [0x01,0x4a,0x50,0x00]
-            add     r10, r10, r10
-
-# CHECK:    add
-# BINARY:   000000 01011 01011 01011 00000000000
-# CHECK:    encoding: [0x01,0x6b,0x58,0x00]
-            add     r11, r11, r11
-
-# CHECK:    add
-# BINARY:   000000 01100 01100 01100 00000000000
-# CHECK:    encoding: [0x01,0x8c,0x60,0x00]
-            add     r12, r12, r12
-
-# CHECK:    add
-# BINARY:   000000 01101 01101 01101 00000000000
-# CHECK:    encoding: [0x01,0xad,0x68,0x00]
-            add     r13, r13, r13
-
-# CHECK:    add
-# BINARY:   000000 01110 01110 01110 00000000000
-# CHECK:    encoding: [0x01,0xce,0x70,0x00]
-            add     r14, r14, r14
-
-# CHECK:    add
-# BINARY:   000000 01111 01111 01111 00000000000
-# CHECK:    encoding: [0x01,0xef,0x78,0x00]
-            add     r15, r15, r15
-
-# CHECK:    add
-# BINARY:   000000 10000 10000 10000 00000000000
-# CHECK:    encoding: [0x02,0x10,0x80,0x00]
-            add     r16, r16, r16
-
-# CHECK:    add
-# BINARY:   000000 10001 10001 10001 00000000000
-# CHECK:    encoding: [0x02,0x31,0x88,0x00]
-            add     r17, r17, r17
-
-# CHECK:    add
-# BINARY:   000000 10010 10010 10010 00000000000
-# CHECK:    encoding: [0x02,0x52,0x90,0x00]
-            add     r18, r18, r18
-
-# CHECK:    add
-# BINARY:   000000 10011 10011 10011 00000000000
-# CHECK:    encoding: [0x02,0x73,0x98,0x00]
-            add     r19, r19, r19
-
-# CHECK:    add
-# BINARY:   000000 10100 10100 10100 00000000000
-# CHECK:    encoding: [0x02,0x94,0xa0,0x00]
-            add     r20, r20, r20
-
-# CHECK:    add
-# BINARY:   000000 10101 10101 10101 00000000000
-# CHECK:    encoding: [0x02,0xb5,0xa8,0x00]
-            add     r21, r21, r21
-
-# CHECK:    add
-# BINARY:   000000 10110 10110 10110 00000000000
-# CHECK:    encoding: [0x02,0xd6,0xb0,0x00]
-            add     r22, r22, r22
-
-# CHECK:    add
-# BINARY:   000000 10111 10111 10111 00000000000
-# CHECK:    encoding: [0x02,0xf7,0xb8,0x00]
-            add     r23, r23, r23
-
-# CHECK:    add
-# BINARY:   000000 11000 11000 11000 00000000000
-# CHECK:    encoding: [0x03,0x18,0xc0,0x00]
-            add     r24, r24, r24
-
-# CHECK:    add
-# BINARY:   000000 11001 11001 11001 00000000000
-# CHECK:    encoding: [0x03,0x39,0xc8,0x00]
-            add     r25, r25, r25
-
-# CHECK:    add
-# BINARY:   000000 11010 11010 11010 00000000000
-# CHECK:    encoding: [0x03,0x5a,0xd0,0x00]
-            add     r26, r26, r26
-
-# CHECK:    add
-# BINARY:   000000 11011 11011 11011 00000000000
-# CHECK:    encoding: [0x03,0x7b,0xd8,0x00]
-            add     r27, r27, r27
-
-# CHECK:    add
-# BINARY:   000000 11100 11100 11100 00000000000
-# CHECK:    encoding: [0x03,0x9c,0xe0,0x00]
-            add     r28, r28, r28
-
-# CHECK:    add
-# BINARY:   000000 11101 11101 11101 00000000000
-# CHECK:    encoding: [0x03,0xbd,0xe8,0x00]
-            add     r29, r29, r29
-
-# CHECK:    add
-# BINARY:   000000 11110 11110 11110 00000000000
-# CHECK:    encoding: [0x03,0xde,0xf0,0x00]
-            add     r30, r30, r30
-
-# CHECK:    add
-# BINARY:   000000 11111 11111 11111 00000000000
-# CHECK:    encoding: [0x03,0xff,0xf8,0x00]
-            add     r31, r31, r31
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000000000000
-# CHECK:    encoding: [0x20,0x00,0x00,0x00]
-            addi    r0, r0, 0
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000000000001
-# CHECK:    encoding: [0x20,0x00,0x00,0x01]
-            addi    r0, r0, 1
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000000000010
-# CHECK:    encoding: [0x20,0x00,0x00,0x02]
-            addi    r0, r0, 2
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000000000100
-# CHECK:    encoding: [0x20,0x00,0x00,0x04]
-            addi    r0, r0, 4
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000000001000
-# CHECK:    encoding: [0x20,0x00,0x00,0x08]
-            addi    r0, r0, 8
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000000010000
-# CHECK:    encoding: [0x20,0x00,0x00,0x10]
-            addi    r0, r0, 16
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000000100000
-# CHECK:    encoding: [0x20,0x00,0x00,0x20]
-            addi    r0, r0, 32
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000001000000
-# CHECK:    encoding: [0x20,0x00,0x00,0x40]
-            addi    r0, r0, 64
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000010000000
-# CHECK:    encoding: [0x20,0x00,0x00,0x80]
-            addi    r0, r0, 128
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000000100000000
-# CHECK:    encoding: [0x20,0x00,0x01,0x00]
-            addi    r0, r0, 256
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000001000000000
-# CHECK:    encoding: [0x20,0x00,0x02,0x00]
-            addi    r0, r0, 512
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000010000000000
-# CHECK:    encoding: [0x20,0x00,0x04,0x00]
-            addi    r0, r0, 1024
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0000100000000000
-# CHECK:    encoding: [0x20,0x00,0x08,0x00]
-            addi    r0, r0, 2048
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0001000000000000
-# CHECK:    encoding: [0x20,0x00,0x10,0x00]
-            addi    r0, r0, 4096
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0010000000000000
-# CHECK:    encoding: [0x20,0x00,0x20,0x00]
-            addi    r0, r0, 8192
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 0100000000000000
-# CHECK:    encoding: [0x20,0x00,0x40,0x00]
-            addi    r0, r0, 16384
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1111111111111111
-# CHECK:    encoding: [0x20,0x00,0xff,0xff]
-            addi    r0, r0, -1
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1111111111111110
-# CHECK:    encoding: [0x20,0x00,0xff,0xfe]
-            addi    r0, r0, -2
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1111111111111100
-# CHECK:    encoding: [0x20,0x00,0xff,0xfc]
-            addi    r0, r0, -4
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1111111111111000
-# CHECK:    encoding: [0x20,0x00,0xff,0xf8]
-            addi    r0, r0, -8
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1111111111110000
-# CHECK:    encoding: [0x20,0x00,0xff,0xf0]
-            addi    r0, r0, -16
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1111111111100000
-# CHECK:    encoding: [0x20,0x00,0xff,0xe0]
-            addi    r0, r0, -32
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1111111111000000
-# CHECK:    encoding: [0x20,0x00,0xff,0xc0]
-            addi    r0, r0, -64
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1111111110000000
-# CHECK:    encoding: [0x20,0x00,0xff,0x80]
-            addi    r0, r0, -128
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1111111100000000
-# CHECK:    encoding: [0x20,0x00,0xff,0x00]
-            addi    r0, r0, -256
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1111111000000000
-# CHECK:    encoding: [0x20,0x00,0xfe,0x00]
-            addi    r0, r0, -512
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1111110000000000
-# CHECK:    encoding: [0x20,0x00,0xfc,0x00]
-            addi    r0, r0, -1024
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1111100000000000
-# CHECK:    encoding: [0x20,0x00,0xf8,0x00]
-            addi    r0, r0, -2048
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1111000000000000
-# CHECK:    encoding: [0x20,0x00,0xf0,0x00]
-            addi    r0, r0, -4096
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1110000000000000
-# CHECK:    encoding: [0x20,0x00,0xe0,0x00]
-            addi    r0, r0, -8192
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1100000000000000
-# CHECK:    encoding: [0x20,0x00,0xc0,0x00]
-            addi    r0, r0, -16384
-
-# CHECK:    addi
-# BINARY:   001000 00000 00000 1000000000000000
-# CHECK:    encoding: [0x20,0x00,0x80,0x00]
-            addi    r0, r0, -32768
diff --git a/test/MC/MBlaze/mblaze_pattern.s b/test/MC/MBlaze/mblaze_pattern.s
deleted file mode 100644
index 6bbc234..0000000
--- a/test/MC/MBlaze/mblaze_pattern.s
+++ /dev/null
@@ -1,22 +0,0 @@
-# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
-
-# Test to ensure that all FPU instructions can be parsed by the
-# assembly parser correctly.
-
-# TYPE A:   OPCODE RD    RA    RB    FLAGS
-# BINARY:   011011 00000 00000 00000 00000000000
-
-# CHECK:    pcmpbf
-# BINARY:   100000 00000 00001 00010 10000000000
-# CHECK:    encoding: [0x80,0x01,0x14,0x00]
-            pcmpbf      r0, r1, r2
-
-# CHECK:    pcmpne
-# BINARY:   100011 00000 00001 00010 10000000000
-# CHECK:    encoding: [0x8c,0x01,0x14,0x00]
-            pcmpne      r0, r1, r2
-
-# CHECK:    pcmpeq
-# BINARY:   100010 00000 00001 00010 10000000000
-# CHECK:    encoding: [0x88,0x01,0x14,0x00]
-            pcmpeq      r0, r1, r2
diff --git a/test/MC/MBlaze/mblaze_shift.s b/test/MC/MBlaze/mblaze_shift.s
deleted file mode 100644
index a25502b..0000000
--- a/test/MC/MBlaze/mblaze_shift.s
+++ /dev/null
@@ -1,47 +0,0 @@
-# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
-
-# Test to make sure that all of the TYPE-A instructions supported by
-# the Microblaze can be parsed by the assembly parser.
-
-# TYPE A:   OPCODE RD    RA    RB    FLAGS
-# BINARY:   000000 00000 00000 00000 00000000000
-
-# CHECK:    bsrl
-# BINARY:   010001 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x44,0x22,0x18,0x00]
-            bsrl    r1, r2, r3
-
-# CHECK:    bsra
-# BINARY:   010001 00001 00010 00011 01000000000
-# CHECK:    encoding: [0x44,0x22,0x1a,0x00]
-            bsra    r1, r2, r3
-
-# CHECK:    bsll
-# BINARY:   010001 00001 00010 00011 10000000000
-# CHECK:    encoding: [0x44,0x22,0x1c,0x00]
-            bsll    r1, r2, r3
-
-# CHECK:    bsrli
-# BINARY:   011001 00001 00010 0000000000000000
-# CHECK:    encoding: [0x64,0x22,0x00,0x00]
-            bsrli   r1, r2, 0
-
-# CHECK:    bsrai
-# BINARY:   011001 00001 00010 0000001000000000
-# CHECK:    encoding: [0x64,0x22,0x02,0x00]
-            bsrai   r1, r2, 0
-
-# CHECK:    bslli
-# BINARY:   011001 00001 00010 0000010000000000
-# CHECK:    encoding: [0x64,0x22,0x04,0x00]
-            bslli   r1, r2, 0
-
-# CHECK:    sra
-# BINARY:   100100 00001 00010 00000 00000000001
-# CHECK:    encoding: [0x90,0x22,0x00,0x01]
-            sra     r1, r2
-
-# CHECK:    srl
-# BINARY:   100100 00001 00010 00000 00001000001
-# CHECK:    encoding: [0x90,0x22,0x00,0x41]
-            srl     r1, r2
diff --git a/test/MC/MBlaze/mblaze_special.s b/test/MC/MBlaze/mblaze_special.s
deleted file mode 100644
index c55ec27..0000000
--- a/test/MC/MBlaze/mblaze_special.s
+++ /dev/null
@@ -1,167 +0,0 @@
-# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
-
-# Test to ensure that all special instructions and special registers can be
-# parsed by the assembly parser correctly.
-
-# TYPE A:   OPCODE RD    RA    RB    FLAGS
-# BINARY:   011011 00000 00000 00000 00000000000
-
-# CHECK:    mfs
-# BINARY:   100101 00000 00000 10000 00000000000
-# CHECK:    encoding: [0x94,0x00,0x80,0x00]
-            mfs         r0, rpc
-
-# CHECK:    msrclr
-# BINARY:   100101 00000 100010 000000000000000
-# CHECK:    encoding: [0x94,0x11,0x00,0x00]
-            msrclr      r0, 0x0
-
-# CHECK:    msrset
-# BINARY:   100101 00000 100000 000000000000000
-# CHECK:    encoding: [0x94,0x10,0x00,0x00]
-            msrset      r0, 0x0
-
-# CHECK:    mts
-# BINARY:   100101 00000 00000 11 00000000000000
-# CHECK:    encoding: [0x94,0x00,0xc0,0x00]
-            mts         rpc, r0
-
-# CHECK:    wdc
-# BINARY:   100100 00000 00000 00001 00001100100
-# CHECK:    encoding: [0x90,0x00,0x08,0x64]
-            wdc         r0, r1
-
-# CHECK:    wdc.clear
-# BINARY:   100100 00000 00000 00001 00001100110
-# CHECK:    encoding: [0x90,0x00,0x08,0x66]
-            wdc.clear   r0, r1
-
-# CHECK:    wdc.flush
-# BINARY:   100100 00000 00000 00001 00001110100
-# CHECK:    encoding: [0x90,0x00,0x08,0x74]
-            wdc.flush   r0, r1
-
-# CHECK:    wic
-# BINARY:   100100 00000 00000 00001 00001101000
-# CHECK:    encoding: [0x90,0x00,0x08,0x68]
-            wic         r0, r1
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10000 00000000000
-# CHECK:    encoding: [0x94,0x20,0x80,0x00]
-            mfs         r1, rpc
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10000 00000000001
-# CHECK:    encoding: [0x94,0x20,0x80,0x01]
-            mfs         r1, rmsr
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10000 00000000011
-# CHECK:    encoding: [0x94,0x20,0x80,0x03]
-            mfs         r1, rear
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10000 00000000101
-# CHECK:    encoding: [0x94,0x20,0x80,0x05]
-            mfs         r1, resr
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10000 00000000111
-# CHECK:    encoding: [0x94,0x20,0x80,0x07]
-            mfs         r1, rfsr
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10000 00000001011
-# CHECK:    encoding: [0x94,0x20,0x80,0x0b]
-            mfs         r1, rbtr
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10000 00000001101
-# CHECK:    encoding: [0x94,0x20,0x80,0x0d]
-            mfs         r1, redr
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10010 00000000000
-# CHECK:    encoding: [0x94,0x20,0x90,0x00]
-            mfs         r1, rpid
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10010 00000000001
-# CHECK:    encoding: [0x94,0x20,0x90,0x01]
-            mfs         r1, rzpr
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10010 00000000010
-# CHECK:    encoding: [0x94,0x20,0x90,0x02]
-            mfs         r1, rtlbx
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10010 00000000100
-# CHECK:    encoding: [0x94,0x20,0x90,0x04]
-            mfs         r1, rtlbhi
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10010 00000000011
-# CHECK:    encoding: [0x94,0x20,0x90,0x03]
-            mfs         r1, rtlblo
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10100 00000000000
-# CHECK:    encoding: [0x94,0x20,0xa0,0x00]
-            mfs         r1, rpvr0
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10100 00000000001
-# CHECK:    encoding: [0x94,0x20,0xa0,0x01]
-            mfs         r1, rpvr1
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10100 00000000010
-# CHECK:    encoding: [0x94,0x20,0xa0,0x02]
-            mfs         r1, rpvr2
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10100 00000000011
-# CHECK:    encoding: [0x94,0x20,0xa0,0x03]
-            mfs         r1, rpvr3
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10100 00000000100
-# CHECK:    encoding: [0x94,0x20,0xa0,0x04]
-            mfs         r1, rpvr4
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10100 00000000101
-# CHECK:    encoding: [0x94,0x20,0xa0,0x05]
-            mfs         r1, rpvr5
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10100 00000000110
-# CHECK:    encoding: [0x94,0x20,0xa0,0x06]
-            mfs         r1, rpvr6
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10100 00000000111
-# CHECK:    encoding: [0x94,0x20,0xa0,0x07]
-            mfs         r1, rpvr7
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10100 00000001000
-# CHECK:    encoding: [0x94,0x20,0xa0,0x08]
-            mfs         r1, rpvr8
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10100 00000001001
-# CHECK:    encoding: [0x94,0x20,0xa0,0x09]
-            mfs         r1, rpvr9
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10100 00000001010
-# CHECK:    encoding: [0x94,0x20,0xa0,0x0a]
-            mfs         r1, rpvr10
-
-# CHECK:    mfs
-# BINARY:   100101 00001 00000 10100 00000001011
-# CHECK:    encoding: [0x94,0x20,0xa0,0x0b]
-            mfs         r1, rpvr11
diff --git a/test/MC/MBlaze/mblaze_typea.s b/test/MC/MBlaze/mblaze_typea.s
deleted file mode 100644
index a0735e4..0000000
--- a/test/MC/MBlaze/mblaze_typea.s
+++ /dev/null
@@ -1,122 +0,0 @@
-# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
-
-# Test to make sure that all of the TYPE-A instructions supported by
-# the Microblaze can be parsed by the assembly parser.
-
-# TYPE A:   OPCODE RD    RA    RB    FLAGS
-# BINARY:   000000 00000 00000 00000 00000000000
-
-# CHECK:    add
-# BINARY:   000000 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x00,0x22,0x18,0x00]
-            add     r1, r2, r3
-
-# CHECK:    addc
-# BINARY:   000010 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x08,0x22,0x18,0x00]
-            addc    r1, r2, r3
-
-# CHECK:    addk
-# BINARY:   000100 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x10,0x22,0x18,0x00]
-            addk    r1, r2, r3
-
-# CHECK:    addkc
-# BINARY:   000110 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x18,0x22,0x18,0x00]
-            addkc   r1, r2, r3
-
-# CHECK:    and
-# BINARY:   100001 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x84,0x22,0x18,0x00]
-            and     r1, r2, r3
-
-# CHECK:    andn
-# BINARY:   100011 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x8c,0x22,0x18,0x00]
-            andn    r1, r2, r3
-
-# CHECK:    cmp
-# BINARY:   000101 00001 00010 00011 00000000001
-# CHECK:    encoding: [0x14,0x22,0x18,0x01]
-            cmp     r1, r2, r3
-
-# CHECK:    cmpu
-# BINARY:   000101 00001 00010 00011 00000000011
-# CHECK:    encoding: [0x14,0x22,0x18,0x03]
-            cmpu    r1, r2, r3
-
-# CHECK:    idiv
-# BINARY:   010010 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x48,0x22,0x18,0x00]
-            idiv    r1, r2, r3
-
-# CHECK:    idivu
-# BINARY:   010010 00001 00010 00011 00000000010
-# CHECK:    encoding: [0x48,0x22,0x18,0x02]
-            idivu   r1, r2, r3
-
-# CHECK:    mul
-# BINARY:   010000 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x40,0x22,0x18,0x00]
-            mul    r1, r2, r3
-
-# CHECK:    mulh
-# BINARY:   010000 00001 00010 00011 00000000001
-# CHECK:    encoding: [0x40,0x22,0x18,0x01]
-            mulh   r1, r2, r3
-
-# CHECK:    mulhu
-# BINARY:   010000 00001 00010 00011 00000000011
-# CHECK:    encoding: [0x40,0x22,0x18,0x03]
-            mulhu  r1, r2, r3
-
-# CHECK:    mulhsu
-# BINARY:   010000 00001 00010 00011 00000000010
-# CHECK:    encoding: [0x40,0x22,0x18,0x02]
-            mulhsu r1, r2, r3
-
-# CHECK:    or
-# BINARY:   100000 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x80,0x22,0x18,0x00]
-            or      r1, r2, r3
-
-# CHECK:    rsub
-# BINARY:   000001 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x04,0x22,0x18,0x00]
-            rsub    r1, r2, r3
-
-# CHECK:    rsubc
-# BINARY:   000011 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x0c,0x22,0x18,0x00]
-            rsubc   r1, r2, r3
-
-# CHECK:    rsubk
-# BINARY:   000101 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x14,0x22,0x18,0x00]
-            rsubk   r1, r2, r3
-
-# CHECK:    rsubkc
-# BINARY:   000111 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x1c,0x22,0x18,0x00]
-            rsubkc  r1, r2, r3
-
-# CHECK:    sext16
-# BINARY:   100100 00001 00010 00000 00001100001
-# CHECK:    encoding: [0x90,0x22,0x00,0x61]
-            sext16  r1, r2
-
-# CHECK:    sext8
-# BINARY:   100100 00001 00010 00000 00001100000
-# CHECK:    encoding: [0x90,0x22,0x00,0x60]
-            sext8   r1, r2
-
-# CHECK:    xor
-# BINARY:   100010 00001 00010 00011 00000000000
-# CHECK:    encoding: [0x88,0x22,0x18,0x00]
-            xor     r1, r2, r3
-
-# CHECK:    nop
-# BINARY:   100000 00000 00000 00000 00000000000
-# CHECK:    encoding: [0x80,0x00,0x00,0x00]
-        nop
diff --git a/test/MC/MBlaze/mblaze_typeb.s b/test/MC/MBlaze/mblaze_typeb.s
deleted file mode 100644
index ac4f1e2..0000000
--- a/test/MC/MBlaze/mblaze_typeb.s
+++ /dev/null
@@ -1,92 +0,0 @@
-# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
-
-# Test to make sure that all of the TYPE-B instructions supported by
-# the Microblaze can be parsed by the assembly parser.
-
-# TYPE B:   OPCODE RD    RA    IMMEDIATE
-#           000000 00000 00000 0000000000000000
-
-# CHECK:    addi
-# BINARY:   001000 00001 00010 0000000000001111
-# CHECK:    encoding: [0x20,0x22,0x00,0x0f]
-            addi    r1, r2, 0x000F
-
-# CHECK:    addic
-# BINARY:   001010 00001 00010 0000000000001111
-# CHECK:    encoding: [0x28,0x22,0x00,0x0f]
-            addic   r1, r2, 0x000F
-
-# CHECK:    addik
-# BINARY:   001100 00001 00010 0000000000001111
-# CHECK:    encoding: [0x30,0x22,0x00,0x0f]
-            addik   r1, r2, 0x000F
-
-# CHECK:    addikc
-# BINARY:   001110 00001 00010 0000000000001111
-# CHECK:    encoding: [0x38,0x22,0x00,0x0f]
-            addikc  r1, r2, 0x000F
-
-# CHECK:    andi
-# BINARY:   101001 00001 00010 0000000000001111
-# CHECK:    encoding: [0xa4,0x22,0x00,0x0f]
-            andi    r1, r2, 0x000F
-
-# CHECK:    andni
-# BINARY:   101011 00001 00010 0000000000001111
-# CHECK:    encoding: [0xac,0x22,0x00,0x0f]
-            andni   r1, r2, 0x000F
-
-# CHECK:    muli
-# BINARY:   011000 00001 00010 0000000000001111
-# CHECK:    encoding: [0x60,0x22,0x00,0x0f]
-            muli    r1, r2, 0x000F
-
-# CHECK:    ori
-# BINARY:   101000 00001 00010 0000000000001111
-# CHECK:    encoding: [0xa0,0x22,0x00,0x0f]
-            ori     r1, r2, 0x000F
-
-# CHECK:    rsubi
-# BINARY:   001001 00001 00010 0000000000001111
-# CHECK:    encoding: [0x24,0x22,0x00,0x0f]
-            rsubi   r1, r2, 0x000F
-
-# CHECK:    rsubic
-# BINARY:   001011 00001 00010 0000000000001111
-# CHECK:    encoding: [0x2c,0x22,0x00,0x0f]
-            rsubic  r1, r2, 0x000F
-
-# CHECK:    rsubik
-# BINARY:   001101 00001 00010 0000000000001111
-# CHECK:    encoding: [0x34,0x22,0x00,0x0f]
-            rsubik  r1, r2, 0x000F
-
-# CHECK:    rsubikc
-# BINARY:   001111 00001 00010 0000000000001111
-# CHECK:    encoding: [0x3c,0x22,0x00,0x0f]
-            rsubikc r1, r2, 0x000F
-
-# CHECK:    rtbd
-# BINARY:   101101 10010 01111 0000000000001111
-# CHECK:    encoding: [0xb6,0x4f,0x00,0x0f]
-            rtbd r15, 0x000F
-
-# CHECK:    rted
-# BINARY:   101101 10001 01111 0000000000001111
-# CHECK:    encoding: [0xb6,0x8f,0x00,0x0f]
-            rted r15, 0x000F
-
-# CHECK:    rtid
-# BINARY:   101101 10001 01111 0000000000001111
-# CHECK:    encoding: [0xb6,0x2f,0x00,0x0f]
-            rtid r15, 0x000F
-
-# CHECK:    rtsd
-# BINARY:   101101 10000 01111 0000000000001111
-# CHECK:    encoding: [0xb6,0x0f,0x00,0x0f]
-            rtsd r15, 0x000F
-
-# CHECK:    xori
-# BINARY:   101010 00001 00010 0000000000001111
-# CHECK:    encoding: [0xa8,0x22,0x00,0x0f]
-            xori r1, r2, 0x000F
diff --git a/test/MC/MachO/tlv-bss.ll b/test/MC/MachO/tlv-bss.ll
new file mode 100644
index 0000000..af620f9
--- /dev/null
+++ b/test/MC/MachO/tlv-bss.ll
@@ -0,0 +1,33 @@
+; RUN: llc -O0 -mtriple=x86_64-apple-darwin12 -filetype=obj -o - %s | macho-dump | FileCheck %s
+; Test that we emit weak_odr thread_locals correctly into the thread_bss section
+; PR15972
+
+; CHECK: __thread_bss
+; CHECK: 'size', 8
+; CHECK: 'alignment', 3
+; CHECK: __thread_vars
+
+; Generated from this C++ source
+; template<class T>
+; struct Tls {
+;   static __thread void* val;
+; };
+
+; template<class T> __thread void* Tls<T>::val;
+
+; void* f(int x) {
+;         return Tls<long>::val;
+; }
+
+@_ZN3TlsIlE3valE = weak_odr thread_local global i8* null, align 8
+
+; Function Attrs: nounwind ssp uwtable
+define i8* @_Z1fi(i32 %x) #0 {
+entry:
+  %x.addr = alloca i32, align 4
+  store i32 %x, i32* %x.addr, align 4
+  %0 = load i8** @_ZN3TlsIlE3valE, align 8
+  ret i8* %0
+}
+
+attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/MC/Mips/abicalls.ll b/test/MC/Mips/abicalls.ll
new file mode 100644
index 0000000..7b98b02
--- /dev/null
+++ b/test/MC/Mips/abicalls.ll
@@ -0,0 +1,15 @@
+; 
+; When the assembler is ready a .s file for it will
+; be created.
+
+; Note that EF_MIPS_CPIC is set by -mabicalls which is the default on Linux
+; TODO need to support -mno-abicalls
+
+; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-STATIC %s
+; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 %s -o - | FileCheck -check-prefix=CHECK-PIC %s
+; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips64 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-PIC %s
+
+; CHECK-STATIC: .abicalls
+; CHECK-STATIC-NEXT: pic0
+; CHECK-PIC: .abicalls
+; CHECK-PIC-NOT: pic0
diff --git a/test/MC/Mips/elf_eflags.ll b/test/MC/Mips/elf_eflags.ll
index 6d16a42..91217bc 100644
--- a/test/MC/Mips/elf_eflags.ll
+++ b/test/MC/Mips/elf_eflags.ll
@@ -6,13 +6,16 @@
 
 ; EF_MIPS_NOREORDER (0x00000001) is always on by default currently
 ; EF_MIPS_PIC (0x00000002)
-; EF_MIPS_CPIC (0x00000004) - not tested yet
+; EF_MIPS_CPIC (0x00000004) - See note below
 ; EF_MIPS_ABI2 (0x00000020) - n32 not tested yet
 ; EF_MIPS_ARCH_32 (0x50000000)
 ; EF_MIPS_ARCH_64 (0x60000000)
 ; EF_MIPS_ARCH_32R2 (0x70000000)
 ; EF_MIPS_ARCH_64R2 (0x80000000)
 
+; Note that EF_MIPS_CPIC is set by -mabicalls which is the default on Linux
+; TODO need to support -mno-abicalls
+
 ; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=static %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-BE32 %s
 ; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32 %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-BE32_PIC %s
 ; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32r2 -relocation-model=static %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-BE32R2 %s
@@ -28,37 +31,37 @@
 ; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+mips16 -relocation-model=pic %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-LE32R2-MIPS16 %s
  
 ; 32(R1) bit with NO_REORDER and static
-; CHECK-BE32: Flags [ (0x50001001)
+; CHECK-BE32: Flags [ (0x50001005)
 ;
 ; 32(R1) bit with NO_REORDER and PIC
-; CHECK-BE32_PIC: Flags [ (0x50001003)
+; CHECK-BE32_PIC: Flags [ (0x50001007)
 ;
 ; 32R2 bit with NO_REORDER and static
-; CHECK-BE32R2: Flags [ (0x70001001)
+; CHECK-BE32R2: Flags [ (0x70001005)
 ;
 ; 32R2 bit with NO_REORDER and PIC
-; CHECK-BE32R2_PIC: Flags [ (0x70001003)
+; CHECK-BE32R2_PIC: Flags [ (0x70001007)
 ;
 ; 32R2 bit MICROMIPS with NO_REORDER and static
-; CHECK-BE32R2-MICROMIPS: Flags [ (0x72001001)
+; CHECK-BE32R2-MICROMIPS: Flags [ (0x72001005)
 ;
 ; 32R2 bit MICROMIPS with NO_REORDER and PIC
-;CHECK-BE32R2-MICROMIPS_PIC: Flags [ (0x72001003)
+;CHECK-BE32R2-MICROMIPS_PIC: Flags [ (0x72001007)
 ;
 ; 64(R1) bit with NO_REORDER and static
-; CHECK-BE64: Flags [ (0x60000001)
+; CHECK-BE64: Flags [ (0x60000005)
 ;
 ; 64(R1) bit with NO_REORDER and PIC
-; CHECK-BE64_PIC: Flags [ (0x60000003)
+; CHECK-BE64_PIC: Flags [ (0x60000007)
 ;
 ; 64R2 bit with NO_REORDER and static
-; CHECK-BE64R2: Flags [ (0x80000001)
+; CHECK-BE64R2: Flags [ (0x80000005)
 ;
 ; 64R2 bit with NO_REORDER and PIC
-; CHECK-BE64R2_PIC: Flags [ (0x80000003)
+; CHECK-BE64R2_PIC: Flags [ (0x80000007)
 ;
 ; 32R2 bit MIPS16 with PIC
-; CHECK-LE32R2-MIPS16: Flags [ (0x74001002)
+; CHECK-LE32R2-MIPS16: Flags [ (0x74001006)
  
 define i32 @main() nounwind {
 entry:
diff --git a/test/MC/Mips/mips-control-instructions.s b/test/MC/Mips/mips-control-instructions.s
new file mode 100644
index 0000000..ee70940
--- /dev/null
+++ b/test/MC/Mips/mips-control-instructions.s
@@ -0,0 +1,28 @@
+# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips32r2 | \
+# RUN: FileCheck -check-prefix=CHECK32  %s
+# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips64r2 | \
+# RUN: FileCheck -check-prefix=CHECK64  %s
+
+# CHECK32:    break                      # encoding: [0x00,0x00,0x00,0x0d]
+# CHECK32:    break   7, 0               # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK32:    break   7, 5               # encoding: [0x00,0x07,0x01,0x4d]
+# CHECK32:    syscall                    # encoding: [0x00,0x00,0x00,0x0c]
+# CHECK32:    syscall 13396              # encoding: [0x00,0x0d,0x15,0x0c]
+# CHECK32:    eret                       # encoding: [0x42,0x00,0x00,0x18]
+# CHECK32:    deret                      # encoding: [0x42,0x00,0x00,0x1f]
+
+# CHECK64:    break                      # encoding: [0x00,0x00,0x00,0x0d]
+# CHECK64:    break   7, 0               # encoding: [0x00,0x07,0x00,0x0d]
+# CHECK64:    break   7, 5               # encoding: [0x00,0x07,0x01,0x4d]
+# CHECK64:    syscall                    # encoding: [0x00,0x00,0x00,0x0c]
+# CHECK64:    syscall 13396              # encoding: [0x00,0x0d,0x15,0x0c]
+# CHECK64:    eret                       # encoding: [0x42,0x00,0x00,0x18]
+# CHECK64:    deret                      # encoding: [0x42,0x00,0x00,0x1f]
+
+    break
+    break 7
+    break 7,5
+    syscall
+    syscall 0x3454
+    eret
+    deret
diff --git a/test/MC/Mips/mips-dsp-instructions.s b/test/MC/Mips/mips-dsp-instructions.s
new file mode 100644
index 0000000..4de88ce
--- /dev/null
+++ b/test/MC/Mips/mips-dsp-instructions.s
@@ -0,0 +1,44 @@
+# RUN: llvm-mc -show-encoding -triple=mips-unknown-unknown -mattr=dspr2 %s | FileCheck %s
+#
+# CHECK:   .text
+# CHECK:   precrq.qb.ph      $16, $17, $18   # encoding: [0x7e,0x32,0x83,0x11]
+# CHECK:   precrq.ph.w       $17, $18, $19   # encoding: [0x7e,0x53,0x8d,0x11]
+# CHECK:   precrq_rs.ph.w    $18, $19, $20   # encoding: [0x7e,0x74,0x95,0x51]
+# CHECK:   precrqu_s.qb.ph   $19, $20, $21   # encoding: [0x7e,0x95,0x9b,0xd1]
+# CHECK:   preceq.w.phl      $20, $21        # encoding: [0x7c,0x15,0xa3,0x12]
+# CHECK:   preceq.w.phr      $21, $22        # encoding: [0x7c,0x16,0xab,0x52]
+# CHECK:   precequ.ph.qbl    $22, $23        # encoding: [0x7c,0x17,0xb1,0x12]
+# CHECK:   precequ.ph.qbr    $23, $24        # encoding: [0x7c,0x18,0xb9,0x52]
+# CHECK:   precequ.ph.qbla   $24, $25        # encoding: [0x7c,0x19,0xc1,0x92]
+# CHECK:   precequ.ph.qbra   $25, $26        # encoding: [0x7c,0x1a,0xc9,0xd2]
+# CHECK:   preceu.ph.qbl     $26, $27        # encoding: [0x7c,0x1b,0xd7,0x12]
+# CHECK:   preceu.ph.qbr     $27, $gp        # encoding: [0x7c,0x1c,0xdf,0x52]
+# CHECK:   preceu.ph.qbla    $gp, $sp        # encoding: [0x7c,0x1d,0xe7,0x92]
+# CHECK:   preceu.ph.qbra    $sp, $fp        # encoding: [0x7c,0x1e,0xef,0xd2]
+
+# CHECK:   precr.qb.ph       $23, $24, $25   # encoding: [0x7f,0x19,0xbb,0x51]
+# CHECK:   precr_sra.ph.w    $24, $25, 0     # encoding: [0x7f,0x38,0x07,0x91]
+# CHECK:   precr_sra.ph.w    $24, $25, 31    # encoding: [0x7f,0x38,0xff,0x91]
+# CHECK:   precr_sra_r.ph.w  $25, $26, 0     # encoding: [0x7f,0x59,0x07,0xd1]
+# CHECK:   precr_sra_r.ph.w  $25, $26, 31    # encoding: [0x7f,0x59,0xff,0xd1]
+
+  precrq.qb.ph    $16,$17,$18
+  precrq.ph.w     $17,$18,$19
+  precrq_rs.ph.w  $18,$19,$20
+  precrqu_s.qb.ph $19,$20,$21
+  preceq.w.phl    $20,$21
+  preceq.w.phr    $21,$22
+  precequ.ph.qbl  $22,$23
+  precequ.ph.qbr  $23,$24
+  precequ.ph.qbla $24,$25
+  precequ.ph.qbra $25,$26
+  preceu.ph.qbl   $26,$27
+  preceu.ph.qbr   $27,$28
+  preceu.ph.qbla  $28,$29
+  preceu.ph.qbra  $29,$30
+
+  precr.qb.ph     $23,$24,$25
+  precr_sra.ph.w  $24,$25,0
+  precr_sra.ph.w  $24,$25,31
+  precr_sra_r.ph.w  $25,$26,0
+  precr_sra_r.ph.w  $25,$26,31
diff --git a/test/MC/Mips/mips-fpu-instructions.s b/test/MC/Mips/mips-fpu-instructions.s
index e515872..dc52676 100644
--- a/test/MC/Mips/mips-fpu-instructions.s
+++ b/test/MC/Mips/mips-fpu-instructions.s
@@ -138,7 +138,8 @@
 # FP move instructions
 #------------------------------------------------------------------------------
 
-# CHECK:  cfc1    $6, $fcc0            # encoding: [0x00,0x00,0x46,0x44]
+# CHECK:  cfc1    $6, $0               # encoding: [0x00,0x00,0x46,0x44]
+# CHECK:  ctc1    $10, $31             # encoding: [0x00,0xf8,0xca,0x44]
 # CHECK:  mfc1    $6, $f7              # encoding: [0x00,0x38,0x06,0x44]
 # CHECK:  mfhi    $5                   # encoding: [0x10,0x28,0x00,0x00]
 # CHECK:  mflo    $5                   # encoding: [0x12,0x28,0x00,0x00]
@@ -158,8 +159,14 @@
 # CHECK:  mtc2    $9, $4, 5               # encoding: [0x05,0x20,0x89,0x48]
 # CHECK:  movf    $2, $1, $fcc0           # encoding: [0x01,0x10,0x20,0x00]
 # CHECK:  movt    $2, $1, $fcc0           # encoding: [0x01,0x10,0x21,0x00]
+# CHECK:  movt    $4, $5, $fcc4           # encoding: [0x01,0x20,0xb1,0x00]
+# CHECK:  movf.d  $f4, $f6, $fcc2         # encoding: [0x11,0x31,0x28,0x46]
+# CHECK:  movf.s  $f4, $f6, $fcc5         # encoding: [0x11,0x31,0x14,0x46]
+# CHECK:  luxc1   $f0, $6($5)             # encoding: [0x05,0x00,0xa6,0x4c]
+# CHECK:  suxc1   $f4, $24($5)            # encoding: [0x0d,0x20,0xb8,0x4c]
 
    cfc1    $a2,$0
+   ctc1    $10,$31
    mfc1    $a2,$f7
    mfhi    $a1
    mflo    $a1
@@ -179,3 +186,8 @@
    mtc2    $9, $4, 5
    movf    $2, $1, $fcc0
    movt    $2, $1, $fcc0
+   movt    $4, $5, $fcc4
+   movf.d  $f4, $f6, $fcc2
+   movf.s  $f4, $f6, $fcc5
+   luxc1 $f0, $a2($a1)
+   suxc1 $f4, $t8($a1)
\ No newline at end of file
diff --git a/test/MC/Mips/mips-jump-instructions.s b/test/MC/Mips/mips-jump-instructions.s
index bfc052c..989826a 100644
--- a/test/MC/Mips/mips-jump-instructions.s
+++ b/test/MC/Mips/mips-jump-instructions.s
@@ -1,6 +1,6 @@
 # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | \
 # RUN: FileCheck -check-prefix=CHECK32  %s
-# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64r2 | \
+# RUN: llvm-mc %s -triple=mips64el-unknown-linux -show-encoding -mcpu=mips64r2 | \
 # RUN: FileCheck -check-prefix=CHECK64  %s
 
 # Check that the assembler can handle the documented syntax
@@ -28,9 +28,9 @@
 # CHECK32:   nop                    # encoding: [0x00,0x00,0x00,0x00]
 # CHECK32:   bal  1332              # encoding: [0x4d,0x01,0x11,0x04]
 # CHECK32:   nop                    # encoding: [0x00,0x00,0x00,0x00]
-# CHECK32:   bne  $11, $zero, 1332  # encoding: [0x4d,0x01,0x60,0x15]
+# CHECK32:   bnez $11, 1332         # encoding: [0x4d,0x01,0x60,0x15]
 # CHECK32:   nop                    # encoding: [0x00,0x00,0x00,0x00]
-# CHECK32:   beq  $11, $zero, 1332  # encoding: [0x4d,0x01,0x60,0x11]
+# CHECK32:   beqz $11, 1332         # encoding: [0x4d,0x01,0x60,0x11]
 # CHECK32:   nop                    # encoding: [0x00,0x00,0x00,0x00]
 
 # CHECK64:   b 1332                 # encoding: [0x4d,0x01,0x00,0x10]
@@ -53,9 +53,9 @@
 # CHECK64:   nop                    # encoding: [0x00,0x00,0x00,0x00]
 # CHECK64:   bal     1332           # encoding: [0x4d,0x01,0x11,0x04]
 # CHECK64:   nop                    # encoding: [0x00,0x00,0x00,0x00]
-# CHECK64:   bne  $11, $zero, 1332  # encoding: [0x4d,0x01,0x60,0x15]
+# CHECK64:   bnez $11, 1332         # encoding: [0x4d,0x01,0x60,0x15]
 # CHECK64:   nop                    # encoding: [0x00,0x00,0x00,0x00]
-# CHECK64:   beq  $11, $zero, 1332  # encoding: [0x4d,0x01,0x60,0x11]
+# CHECK64:   beqz $11, 1332         # encoding: [0x4d,0x01,0x60,0x11]
 # CHECK64:   nop                    # encoding: [0x00,0x00,0x00,0x00]
 
 .set noreorder
diff --git a/test/MC/Mips/mips_directives.s b/test/MC/Mips/mips_directives.s
index 24bef61..bbb2616 100644
--- a/test/MC/Mips/mips_directives.s
+++ b/test/MC/Mips/mips_directives.s
@@ -38,7 +38,8 @@ $JTI0_0:
     .set STORE_MASK,$t7
     .set FPU_MASK,$f7
     .set r3,$3
-#CHECK:    abs.s   $f6, $f7           # encoding: [0x46,0x00,0x39,0x85]
-#CHECK:    and     $3, $15, $15       # encoding: [0x01,0xef,0x18,0x24]
-    abs.s  $f6,FPU_MASK
+    .set f6,$f6
+# CHECK:    abs.s   $f6, $f7           # encoding: [0x46,0x00,0x39,0x85]
+# CHECK:    and     $3, $15, $15       # encoding: [0x01,0xef,0x18,0x24]
+    abs.s  f6,FPU_MASK
     and    r3,$t7,STORE_MASK
diff --git a/test/MC/PowerPC/ppc-llong.s b/test/MC/PowerPC/ppc-llong.s
new file mode 100644
index 0000000..0838e42
--- /dev/null
+++ b/test/MC/PowerPC/ppc-llong.s
@@ -0,0 +1,28 @@
+
+# RUN: llvm-mc -triple powerpc-unknown-unknown -filetype=obj %s | \
+# RUN: llvm-readobj -s -sd | FileCheck %s
+# RUN: llvm-mc -triple powerpc64-unknown-unknown -filetype=obj %s | \
+# RUN: llvm-readobj -s -sd | FileCheck %s
+
+.data
+.llong 0
+
+# CHECK:        Section {
+# CHECK:          Name: .data
+# CHECK-NEXT:     Type: SHT_PROGBITS
+# CHECK-NEXT:     Flags [
+# CHECK-NEXT:       SHF_ALLOC
+# CHECK-NEXT:       SHF_WRITE
+# CHECK-NEXT:     ]
+# CHECK-NEXT:     Address: 0x0
+# CHECK-NEXT:     Offset:
+# CHECK-NEXT:     Size: 8
+# CHECK-NEXT:     Link: 0
+# CHECK-NEXT:     Info: 0
+# CHECK-NEXT:     AddressAlignment: 4
+# CHECK-NEXT:     EntrySize: 0
+# CHECK-NEXT:     SectionData (
+# CHECK-NEXT:       0000: 00000000 00000000
+# CHECK-NEXT:     )
+# CHECK-NEXT:   }
+
diff --git a/test/MC/PowerPC/ppc-machine.s b/test/MC/PowerPC/ppc-machine.s
new file mode 100644
index 0000000..b8a7e3f
--- /dev/null
+++ b/test/MC/PowerPC/ppc-machine.s
@@ -0,0 +1,14 @@
+# RUN: llvm-mc -triple powerpc-unknown-unknown %s
+# RUN: llvm-mc -triple powerpc64-unknown-unknown %s
+
+# For now, the only thing we check is that the .machine directive
+# is accepted without syntax error.
+
+	.machine push
+	.machine any
+	.machine pop
+
+	.machine "push"
+	.machine "any"
+	.machine "pop"
+
diff --git a/test/MC/PowerPC/ppc-nop.s b/test/MC/PowerPC/ppc-nop.s
new file mode 100644
index 0000000..567943c
--- /dev/null
+++ b/test/MC/PowerPC/ppc-nop.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -filetype=obj -triple=powerpc-unknown-linux-gnu %s | llvm-readobj -s -sd - | FileCheck %s
+# RUN: llvm-mc -filetype=obj -triple=powerpc64-unknown-linux-gnu %s | llvm-readobj -s -sd - | FileCheck %s
+
+blr
+.p2align 3
+blr
+
+# CHECK:  0000: 4E800020 60000000 4E800020
+
diff --git a/test/MC/PowerPC/ppc-word.s b/test/MC/PowerPC/ppc-word.s
new file mode 100644
index 0000000..773fa14
--- /dev/null
+++ b/test/MC/PowerPC/ppc-word.s
@@ -0,0 +1,28 @@
+
+# RUN: llvm-mc -triple powerpc-unknown-unknown -filetype=obj %s | \
+# RUN: llvm-readobj -s -sd | FileCheck %s
+# RUN: llvm-mc -triple powerpc64-unknown-unknown -filetype=obj %s | \
+# RUN: llvm-readobj -s -sd | FileCheck %s
+
+.data
+.word 0
+
+# CHECK:        Section {
+# CHECK:          Name: .data
+# CHECK-NEXT:     Type: SHT_PROGBITS
+# CHECK-NEXT:     Flags [
+# CHECK-NEXT:       SHF_ALLOC
+# CHECK-NEXT:       SHF_WRITE
+# CHECK-NEXT:     ]
+# CHECK-NEXT:     Address: 0x0
+# CHECK-NEXT:     Offset:
+# CHECK-NEXT:     Size: 2
+# CHECK-NEXT:     Link: 0
+# CHECK-NEXT:     Info: 0
+# CHECK-NEXT:     AddressAlignment: 4
+# CHECK-NEXT:     EntrySize: 0
+# CHECK-NEXT:     SectionData (
+# CHECK-NEXT:       0000: 0000
+# CHECK-NEXT:     )
+# CHECK-NEXT:   }
+
diff --git a/test/MC/PowerPC/ppc64-encoding-bookII.s b/test/MC/PowerPC/ppc64-encoding-bookII.s
index e74c971..9e68a4b 100644
--- a/test/MC/PowerPC/ppc64-encoding-bookII.s
+++ b/test/MC/PowerPC/ppc64-encoding-bookII.s
@@ -3,11 +3,15 @@
 
 # Cache management instruction
 
-# FIXME: icbi 2, 3
-# FIXME: icbt 1, 2, 3
+# CHECK: icbi 2, 3                       # encoding: [0x7c,0x02,0x1f,0xac]
+         icbi 2, 3
 
 # FIXME: dcbt 2, 3, 10
+# CHECK: dcbt 2, 3                       # encoding: [0x7c,0x02,0x1a,0x2c]
+         dcbt 2, 3
 # FIXME: dcbtst 2, 3, 10
+# CHECK: dcbtst 2, 3                     # encoding: [0x7c,0x02,0x19,0xec]
+         dcbtst 2, 3
 # CHECK: dcbz 2, 3                       # encoding: [0x7c,0x02,0x1f,0xec]
          dcbz 2, 3
 # CHECK: dcbst 2, 3                      # encoding: [0x7c,0x02,0x18,0x6c]
@@ -16,7 +20,8 @@
 
 # Synchronization instructions
 
-# FIXME: isync
+# CHECK: isync                           # encoding: [0x4c,0x00,0x01,0x2c]
+         isync
 
 # FIXME: lbarx 2, 3, 4, 1
 # FIXME: lharx 2, 3, 4, 1
@@ -30,9 +35,12 @@
 # CHECK: stdcx. 2, 3, 4                  # encoding: [0x7c,0x43,0x21,0xad]
          stdcx. 2, 3, 4
 
-# FIXME: sync 2
-# FIXME: eieio
-# FIXME: wait 2
+# CHECK: sync 2                          # encoding: [0x7c,0x40,0x04,0xac]
+         sync 2
+# CHECK: eieio                           # encoding: [0x7c,0x00,0x06,0xac]
+         eieio
+# CHECK: wait 2                          # encoding: [0x7c,0x40,0x00,0x7c]
+         wait 2
 
 # Extended mnemonics
 
@@ -47,12 +55,28 @@
 # CHECK: ldarx 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0xa8]
          ldarx 2, 3, 4
 
-# CHECK: sync                            # encoding: [0x7c,0x00,0x04,0xac]
+# CHECK: sync 0                          # encoding: [0x7c,0x00,0x04,0xac]
          sync
-# FIXME: lwsync
-# FIXME: ptesync
+# CHECK: sync 0                          # encoding: [0x7c,0x00,0x04,0xac]
+         msync
+# CHECK: sync 1                          # encoding: [0x7c,0x20,0x04,0xac]
+         lwsync
+# CHECK: sync 2                          # encoding: [0x7c,0x40,0x04,0xac]
+         ptesync
 
-# FIXME: wait
-# FIXME: waitrsv
-# FIXME: waitimpl
+# CHECK: wait 0                          # encoding: [0x7c,0x00,0x00,0x7c]
+         wait
+# CHECK: wait 1                          # encoding: [0x7c,0x20,0x00,0x7c]
+         waitrsv
+# CHECK: wait 2                          # encoding: [0x7c,0x40,0x00,0x7c]
+         waitimpl
+
+# Time base instructions
+
+# CHECK: mftb 2, 123                     # encoding: [0x7c,0x5b,0x1a,0xe6]
+         mftb 2, 123
+# CHECK: mftb 2, 268                     # encoding: [0x7c,0x4c,0x42,0xe6]
+         mftb 2
+# CHECK: mftb 2, 269                     # encoding: [0x7c,0x4d,0x42,0xe6]
+         mftbu 2
 
diff --git a/test/MC/PowerPC/ppc64-encoding-ext.s b/test/MC/PowerPC/ppc64-encoding-ext.s
index cac76ba..a9c313a 100644
--- a/test/MC/PowerPC/ppc64-encoding-ext.s
+++ b/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -1,7 +1,105 @@
 
 # RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s
 
-# FIXME: Condition register bit symbols
+# Condition register bit symbols
+
+# CHECK: beqlr 0                         # encoding: [0x4d,0x82,0x00,0x20]
+         beqlr cr0
+# CHECK: beqlr 1                         # encoding: [0x4d,0x86,0x00,0x20]
+         beqlr cr1
+# CHECK: beqlr 2                         # encoding: [0x4d,0x8a,0x00,0x20]
+         beqlr cr2
+# CHECK: beqlr 3                         # encoding: [0x4d,0x8e,0x00,0x20]
+         beqlr cr3
+# CHECK: beqlr 4                         # encoding: [0x4d,0x92,0x00,0x20]
+         beqlr cr4
+# CHECK: beqlr 5                         # encoding: [0x4d,0x96,0x00,0x20]
+         beqlr cr5
+# CHECK: beqlr 6                         # encoding: [0x4d,0x9a,0x00,0x20]
+         beqlr cr6
+# CHECK: beqlr 7                         # encoding: [0x4d,0x9e,0x00,0x20]
+         beqlr cr7
+
+# CHECK: bclr 12, 0, 0                   # encoding: [0x4d,0x80,0x00,0x20]
+         btlr 4*cr0+lt
+# CHECK: bclr 12, 1, 0                   # encoding: [0x4d,0x81,0x00,0x20]
+         btlr 4*cr0+gt
+# CHECK: bclr 12, 2, 0                   # encoding: [0x4d,0x82,0x00,0x20]
+         btlr 4*cr0+eq
+# CHECK: bclr 12, 3, 0                   # encoding: [0x4d,0x83,0x00,0x20]
+         btlr 4*cr0+so
+# CHECK: bclr 12, 3, 0                   # encoding: [0x4d,0x83,0x00,0x20]
+         btlr 4*cr0+un
+# CHECK: bclr 12, 4, 0                   # encoding: [0x4d,0x84,0x00,0x20]
+         btlr 4*cr1+lt
+# CHECK: bclr 12, 5, 0                   # encoding: [0x4d,0x85,0x00,0x20]
+         btlr 4*cr1+gt
+# CHECK: bclr 12, 6, 0                   # encoding: [0x4d,0x86,0x00,0x20]
+         btlr 4*cr1+eq
+# CHECK: bclr 12, 7, 0                   # encoding: [0x4d,0x87,0x00,0x20]
+         btlr 4*cr1+so
+# CHECK: bclr 12, 7, 0                   # encoding: [0x4d,0x87,0x00,0x20]
+         btlr 4*cr1+un
+# CHECK: bclr 12, 8, 0                   # encoding: [0x4d,0x88,0x00,0x20]
+         btlr 4*cr2+lt
+# CHECK: bclr 12, 9, 0                   # encoding: [0x4d,0x89,0x00,0x20]
+         btlr 4*cr2+gt
+# CHECK: bclr 12, 10, 0                  # encoding: [0x4d,0x8a,0x00,0x20]
+         btlr 4*cr2+eq
+# CHECK: bclr 12, 11, 0                  # encoding: [0x4d,0x8b,0x00,0x20]
+         btlr 4*cr2+so
+# CHECK: bclr 12, 11, 0                  # encoding: [0x4d,0x8b,0x00,0x20]
+         btlr 4*cr2+un
+# CHECK: bclr 12, 12, 0                  # encoding: [0x4d,0x8c,0x00,0x20]
+         btlr 4*cr3+lt
+# CHECK: bclr 12, 13, 0                  # encoding: [0x4d,0x8d,0x00,0x20]
+         btlr 4*cr3+gt
+# CHECK: bclr 12, 14, 0                  # encoding: [0x4d,0x8e,0x00,0x20]
+         btlr 4*cr3+eq
+# CHECK: bclr 12, 15, 0                  # encoding: [0x4d,0x8f,0x00,0x20]
+         btlr 4*cr3+so
+# CHECK: bclr 12, 15, 0                  # encoding: [0x4d,0x8f,0x00,0x20]
+         btlr 4*cr3+un
+# CHECK: bclr 12, 16, 0                  # encoding: [0x4d,0x90,0x00,0x20]
+         btlr 4*cr4+lt
+# CHECK: bclr 12, 17, 0                  # encoding: [0x4d,0x91,0x00,0x20]
+         btlr 4*cr4+gt
+# CHECK: bclr 12, 18, 0                  # encoding: [0x4d,0x92,0x00,0x20]
+         btlr 4*cr4+eq
+# CHECK: bclr 12, 19, 0                  # encoding: [0x4d,0x93,0x00,0x20]
+         btlr 4*cr4+so
+# CHECK: bclr 12, 19, 0                  # encoding: [0x4d,0x93,0x00,0x20]
+         btlr 4*cr4+un
+# CHECK: bclr 12, 20, 0                  # encoding: [0x4d,0x94,0x00,0x20]
+         btlr 4*cr5+lt
+# CHECK: bclr 12, 21, 0                  # encoding: [0x4d,0x95,0x00,0x20]
+         btlr 4*cr5+gt
+# CHECK: bclr 12, 22, 0                  # encoding: [0x4d,0x96,0x00,0x20]
+         btlr 4*cr5+eq
+# CHECK: bclr 12, 23, 0                  # encoding: [0x4d,0x97,0x00,0x20]
+         btlr 4*cr5+so
+# CHECK: bclr 12, 23, 0                  # encoding: [0x4d,0x97,0x00,0x20]
+         btlr 4*cr5+un
+# CHECK: bclr 12, 24, 0                  # encoding: [0x4d,0x98,0x00,0x20]
+         btlr 4*cr6+lt
+# CHECK: bclr 12, 25, 0                  # encoding: [0x4d,0x99,0x00,0x20]
+         btlr 4*cr6+gt
+# CHECK: bclr 12, 26, 0                  # encoding: [0x4d,0x9a,0x00,0x20]
+         btlr 4*cr6+eq
+# CHECK: bclr 12, 27, 0                  # encoding: [0x4d,0x9b,0x00,0x20]
+         btlr 4*cr6+so
+# CHECK: bclr 12, 27, 0                  # encoding: [0x4d,0x9b,0x00,0x20]
+         btlr 4*cr6+un
+# CHECK: bclr 12, 28, 0                  # encoding: [0x4d,0x9c,0x00,0x20]
+         btlr 4*cr7+lt
+# CHECK: bclr 12, 29, 0                  # encoding: [0x4d,0x9d,0x00,0x20]
+         btlr 4*cr7+gt
+# CHECK: bclr 12, 30, 0                  # encoding: [0x4d,0x9e,0x00,0x20]
+         btlr 4*cr7+eq
+# CHECK: bclr 12, 31, 0                  # encoding: [0x4d,0x9f,0x00,0x20]
+         btlr 4*cr7+so
+# CHECK: bclr 12, 31, 0                  # encoding: [0x4d,0x9f,0x00,0x20]
+         btlr 4*cr7+un
 
 # Branch mnemonics
 
@@ -9,113 +107,306 @@
          blr
 # CHECK: bctr                            # encoding: [0x4e,0x80,0x04,0x20]
          bctr
-# FIXME: blrl
+# CHECK: blrl                            # encoding: [0x4e,0x80,0x00,0x21]
+         blrl
 # CHECK: bctrl                           # encoding: [0x4e,0x80,0x04,0x21]
          bctrl
 
-# FIXME: bt 2, target
-# FIXME: bt target
-# FIXME: bta 2, target
-# FIXME: bta target
-# FIXME: btlr 2
-# FIXME: btlr
-# FIXME: btctr 2
-# FIXME: btctr
-# FIXME: btl 2, target
-# FIXME: btl target
-# FIXME: btla 2, target
-# FIXME: btla target
-# FIXME: btlrl 2
-# FIXME: btlrl
-# FIXME: btctrl 2
-# FIXME: btctrl
-
-# FIXME: bf 2, target
-# FIXME: bf target
-# FIXME: bfa 2, target
-# FIXME: bfa target
-# FIXME: bflr 2
-# FIXME: bflr
-# FIXME: bfctr 2
-# FIXME: bfctr
-# FIXME: bfl 2, target
-# FIXME: bfl target
-# FIXME: bfla 2, target
-# FIXME: bfla target
-# FIXME: bflrl 2
-# FIXME: bflrl
-# FIXME: bfctrl 2
-# FIXME: bfctrl
+# CHECK: bc 12, 2, target                # encoding: [0x41,0x82,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bt 2, target
+# CHECK: bca 12, 2, target               # encoding: [0x41,0x82,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bta 2, target
+# CHECK: bclr 12, 2, 0                   # encoding: [0x4d,0x82,0x00,0x20]
+         btlr 2
+# CHECK: bcctr 12, 2, 0                  # encoding: [0x4d,0x82,0x04,0x20]
+         btctr 2
+# CHECK: bcl 12, 2, target               # encoding: [0x41,0x82,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         btl 2, target
+# CHECK: bcla 12, 2, target              # encoding: [0x41,0x82,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         btla 2, target
+# CHECK: bclrl 12, 2, 0                  # encoding: [0x4d,0x82,0x00,0x21]
+         btlrl 2
+# CHECK: bcctrl 12, 2, 0                 # encoding: [0x4d,0x82,0x04,0x21]
+         btctrl 2
+
+# CHECK: bc 15, 2, target                # encoding: [0x41,0xe2,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bt+ 2, target
+# CHECK: bca 15, 2, target               # encoding: [0x41,0xe2,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bta+ 2, target
+# CHECK: bclr 15, 2, 0                   # encoding: [0x4d,0xe2,0x00,0x20]
+         btlr+ 2
+# CHECK: bcctr 15, 2, 0                  # encoding: [0x4d,0xe2,0x04,0x20]
+         btctr+ 2
+# CHECK: bcl 15, 2, target               # encoding: [0x41,0xe2,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         btl+ 2, target
+# CHECK: bcla 15, 2, target              # encoding: [0x41,0xe2,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         btla+ 2, target
+# CHECK: bclrl 15, 2, 0                  # encoding: [0x4d,0xe2,0x00,0x21]
+         btlrl+ 2
+# CHECK: bcctrl 15, 2, 0                 # encoding: [0x4d,0xe2,0x04,0x21]
+         btctrl+ 2
+
+# CHECK: bc 14, 2, target                # encoding: [0x41,0xc2,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bt- 2, target
+# CHECK: bca 14, 2, target               # encoding: [0x41,0xc2,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bta- 2, target
+# CHECK: bclr 14, 2, 0                   # encoding: [0x4d,0xc2,0x00,0x20]
+         btlr- 2
+# CHECK: bcctr 14, 2, 0                  # encoding: [0x4d,0xc2,0x04,0x20]
+         btctr- 2
+# CHECK: bcl 14, 2, target               # encoding: [0x41,0xc2,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         btl- 2, target
+# CHECK: bcla 14, 2, target              # encoding: [0x41,0xc2,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         btla- 2, target
+# CHECK: bclrl 14, 2, 0                  # encoding: [0x4d,0xc2,0x00,0x21]
+         btlrl- 2
+# CHECK: bcctrl 14, 2, 0                 # encoding: [0x4d,0xc2,0x04,0x21]
+         btctrl- 2
+
+# CHECK: bc 4, 2, target                 # encoding: [0x40,0x82,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bf 2, target
+# CHECK: bca 4, 2, target                # encoding: [0x40,0x82,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bfa 2, target
+# CHECK: bclr 4, 2, 0                    # encoding: [0x4c,0x82,0x00,0x20]
+         bflr 2
+# CHECK: bcctr 4, 2, 0                   # encoding: [0x4c,0x82,0x04,0x20]
+         bfctr 2
+# CHECK: bcl 4, 2, target                # encoding: [0x40,0x82,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bfl 2, target
+# CHECK: bcla 4, 2, target               # encoding: [0x40,0x82,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bfla 2, target
+# CHECK: bclrl 4, 2, 0                   # encoding: [0x4c,0x82,0x00,0x21]
+         bflrl 2
+# CHECK: bcctrl 4, 2, 0                  # encoding: [0x4c,0x82,0x04,0x21]
+         bfctrl 2
+
+# CHECK: bc 7, 2, target                 # encoding: [0x40,0xe2,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bf+ 2, target
+# CHECK: bca 7, 2, target                # encoding: [0x40,0xe2,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bfa+ 2, target
+# CHECK: bclr 7, 2, 0                    # encoding: [0x4c,0xe2,0x00,0x20]
+         bflr+ 2
+# CHECK: bcctr 7, 2, 0                   # encoding: [0x4c,0xe2,0x04,0x20]
+         bfctr+ 2
+# CHECK: bcl 7, 2, target                # encoding: [0x40,0xe2,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bfl+ 2, target
+# CHECK: bcla 7, 2, target               # encoding: [0x40,0xe2,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bfla+ 2, target
+# CHECK: bclrl 7, 2, 0                   # encoding: [0x4c,0xe2,0x00,0x21]
+         bflrl+ 2
+# CHECK: bcctrl 7, 2, 0                  # encoding: [0x4c,0xe2,0x04,0x21]
+         bfctrl+ 2
+
+# CHECK: bc 6, 2, target                 # encoding: [0x40,0xc2,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bf- 2, target
+# CHECK: bca 6, 2, target                # encoding: [0x40,0xc2,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bfa- 2, target
+# CHECK: bclr 6, 2, 0                    # encoding: [0x4c,0xc2,0x00,0x20]
+         bflr- 2
+# CHECK: bcctr 6, 2, 0                   # encoding: [0x4c,0xc2,0x04,0x20]
+         bfctr- 2
+# CHECK: bcl 6, 2, target                # encoding: [0x40,0xc2,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bfl- 2, target
+# CHECK: bcla 6, 2, target               # encoding: [0x40,0xc2,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bfla- 2, target
+# CHECK: bclrl 6, 2, 0                   # encoding: [0x4c,0xc2,0x00,0x21]
+         bflrl- 2
+# CHECK: bcctrl 6, 2, 0                  # encoding: [0x4c,0xc2,0x04,0x21]
+         bfctrl- 2
 
 # CHECK: bdnz target                     # encoding: [0x42,0x00,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bdnz target
-# FIXME: bdnza target
+# CHECK: bdnza target                    # encoding: [0x42,0x00,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdnza target
 # CHECK: bdnzlr                          # encoding: [0x4e,0x00,0x00,0x20]
          bdnzlr
-# FIXME: bdnzl target
-# FIXME: bdnzla target
-# FIXME: bdnzlrl
-
-# FIXME: bdnzt 2, target
-# FIXME: bdnzt target
-# FIXME: bdnzta 2, target
-# FIXME: bdnzta target
-# FIXME: bdnztlr 2
-# FIXME: bdnztlr
-# FIXME: bdnztl 2, target
-# FIXME: bdnztl target
-# FIXME: bdnztla 2, target
-# FIXME: bdnztla target
-# FIXME: bdnztlrl 2
-# FIXME: bdnztlrl
-# FIXME: bdnzf 2, target
-# FIXME: bdnzf target
-# FIXME: bdnzfa 2, target
-# FIXME: bdnzfa target
-# FIXME: bdnzflr 2
-# FIXME: bdnzflr
-# FIXME: bdnzfl 2, target
-# FIXME: bdnzfl target
-# FIXME: bdnzfla 2, target
-# FIXME: bdnzfla target
-# FIXME: bdnzflrl 2
-# FIXME: bdnzflrl
+# CHECK: bdnzl target                    # encoding: [0x42,0x00,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdnzl target
+# CHECK: bdnzla target                   # encoding: [0x42,0x00,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdnzla target
+# CHECK: bdnzlrl                         # encoding: [0x4e,0x00,0x00,0x21]
+         bdnzlrl
+
+# CHECK: bdnz+ target                    # encoding: [0x43,0x20,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdnz+ target
+# CHECK: bdnza+ target                   # encoding: [0x43,0x20,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdnza+ target
+# CHECK: bdnzlr+                         # encoding: [0x4f,0x20,0x00,0x20]
+         bdnzlr+
+# CHECK: bdnzl+ target                   # encoding: [0x43,0x20,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdnzl+ target
+# CHECK: bdnzla+ target                  # encoding: [0x43,0x20,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdnzla+ target
+# CHECK: bdnzlrl+                        # encoding: [0x4f,0x20,0x00,0x21]
+         bdnzlrl+
+
+# CHECK: bdnz- target                    # encoding: [0x43,0x00,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdnz- target
+# CHECK: bdnza- target                   # encoding: [0x43,0x00,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdnza- target
+# CHECK: bdnzlr-                         # encoding: [0x4f,0x00,0x00,0x20]
+         bdnzlr-
+# CHECK: bdnzl- target                   # encoding: [0x43,0x00,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdnzl- target
+# CHECK: bdnzla- target                  # encoding: [0x43,0x00,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdnzla- target
+# CHECK: bdnzlrl-                        # encoding: [0x4f,0x00,0x00,0x21]
+         bdnzlrl-
+
+# CHECK: bc 8, 2, target                 # encoding: [0x41,0x02,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdnzt 2, target
+# CHECK: bca 8, 2, target                # encoding: [0x41,0x02,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdnzta 2, target
+# CHECK: bclr 8, 2, 0                    # encoding: [0x4d,0x02,0x00,0x20]
+         bdnztlr 2
+# CHECK: bcl 8, 2, target                # encoding: [0x41,0x02,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdnztl 2, target
+# CHECK: bcla 8, 2, target               # encoding: [0x41,0x02,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdnztla 2, target
+# CHECK: bclrl 8, 2, 0                   # encoding: [0x4d,0x02,0x00,0x21]
+         bdnztlrl 2
+
+# CHECK: bc 0, 2, target                 # encoding: [0x40,0x02,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdnzf 2, target
+# CHECK: bca 0, 2, target                # encoding: [0x40,0x02,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdnzfa 2, target
+# CHECK: bclr 0, 2, 0                    # encoding: [0x4c,0x02,0x00,0x20]
+         bdnzflr 2
+# CHECK: bcl 0, 2, target                # encoding: [0x40,0x02,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdnzfl 2, target
+# CHECK: bcla 0, 2, target               # encoding: [0x40,0x02,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdnzfla 2, target
+# CHECK: bclrl 0, 2, 0                   # encoding: [0x4c,0x02,0x00,0x21]
+         bdnzflrl 2
 
 # CHECK: bdz target                      # encoding: [0x42,0x40,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bdz target
-# FIXME: bdza target
+# CHECK: bdza target                     # encoding: [0x42,0x40,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdza target
 # CHECK: bdzlr                           # encoding: [0x4e,0x40,0x00,0x20]
          bdzlr
-# FIXME: bdzl target
-# FIXME: bdzla target
-# FIXME: bdzlrl
-
-# FIXME: bdzt 2, target
-# FIXME: bdzt target
-# FIXME: bdzta 2, target
-# FIXME: bdzta target
-# FIXME: bdztlr 2
-# FIXME: bdztlr
-# FIXME: bdztl 2, target
-# FIXME: bdztl target
-# FIXME: bdztla 2, target
-# FIXME: bdztla target
-# FIXME: bdztlrl 2
-# FIXME: bdztlrl
-# FIXME: bdzf 2, target
-# FIXME: bdzf target
-# FIXME: bdzfa 2, target
-# FIXME: bdzfa target
-# FIXME: bdzflr 2
-# FIXME: bdzflr
-# FIXME: bdzfl 2, target
-# FIXME: bdzfl target
-# FIXME: bdzfla 2, target
-# FIXME: bdzfla target
-# FIXME: bdzflrl 2
-# FIXME: bdzflrl
+# CHECK: bdzl target                     # encoding: [0x42,0x40,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdzl target
+# CHECK: bdzla target                    # encoding: [0x42,0x40,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdzla target
+# CHECK: bdzlrl                          # encoding: [0x4e,0x40,0x00,0x21]
+         bdzlrl
+
+# CHECK: bdz+ target                     # encoding: [0x43,0x60,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdz+ target
+# CHECK: bdza+ target                    # encoding: [0x43,0x60,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdza+ target
+# CHECK: bdzlr+                          # encoding: [0x4f,0x60,0x00,0x20]
+         bdzlr+
+# CHECK: bdzl+ target                    # encoding: [0x43,0x60,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdzl+ target
+# CHECK: bdzla+ target                   # encoding: [0x43,0x60,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdzla+ target
+# CHECK: bdzlrl+                         # encoding: [0x4f,0x60,0x00,0x21]
+         bdzlrl+
+
+# CHECK: bdz- target                     # encoding: [0x43,0x40,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdz- target
+# CHECK: bdza- target                    # encoding: [0x43,0x40,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdza- target
+# CHECK: bdzlr-                          # encoding: [0x4f,0x40,0x00,0x20]
+         bdzlr-
+# CHECK: bdzl- target                    # encoding: [0x43,0x40,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdzl- target
+# CHECK: bdzla- target                   # encoding: [0x43,0x40,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdzla- target
+# CHECK: bdzlrl-                         # encoding: [0x4f,0x40,0x00,0x21]
+         bdzlrl-
+
+# CHECK: bc 10, 2, target                # encoding: [0x41,0x42,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdzt 2, target
+# CHECK: bca 10, 2, target               # encoding: [0x41,0x42,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdzta 2, target
+# CHECK: bclr 10, 2, 0                   # encoding: [0x4d,0x42,0x00,0x20]
+         bdztlr 2
+# CHECK: bcl 10, 2, target               # encoding: [0x41,0x42,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdztl 2, target
+# CHECK: bcla 10, 2, target              # encoding: [0x41,0x42,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdztla 2, target
+# CHECK: bclrl 10, 2, 0                  # encoding: [0x4d,0x42,0x00,0x21]
+         bdztlrl 2
+
+# CHECK: bc 2, 2, target                 # encoding: [0x40,0x42,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdzf 2, target
+# CHECK: bca 2, 2, target                # encoding: [0x40,0x42,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdzfa 2, target
+# CHECK: bclr 2, 2, 0                    # encoding: [0x4c,0x42,0x00,0x20]
+         bdzflr 2
+# CHECK: bcl 2, 2, target                # encoding: [0x40,0x42,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bdzfl 2, target
+# CHECK: bcla 2, 2, target               # encoding: [0x40,0x42,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bdzfla 2, target
+# CHECK: bclrl 2, 2, 0                   # encoding: [0x4c,0x42,0x00,0x21]
+         bdzflrl 2
 
 # CHECK: blt 2, target                   # encoding: [0x41,0x88,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
@@ -123,8 +414,12 @@
 # CHECK: blt 0, target                   # encoding: [0x41,0x80,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          blt target
-# FIXME: blta 2, target
-# FIXME: blta target
+# CHECK: blta 2, target                  # encoding: [0x41,0x88,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blta 2, target
+# CHECK: blta 0, target                  # encoding: [0x41,0x80,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blta target
 # CHECK: bltlr 2                         # encoding: [0x4d,0x88,0x00,0x20]
          bltlr 2
 # CHECK: bltlr 0                         # encoding: [0x4d,0x80,0x00,0x20]
@@ -133,25 +428,121 @@
          bltctr 2
 # CHECK: bltctr 0                        # encoding: [0x4d,0x80,0x04,0x20]
          bltctr
-# FIXME: bltl 2, target
-# FIXME: bltl target
-# FIXME: bltla 2, target
-# FIXME: bltla target
-# FIXME: bltlrl 2
-# FIXME: bltlrl
+# CHECK: bltl 2, target                  # encoding: [0x41,0x88,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bltl 2, target
+# CHECK: bltl 0, target                  # encoding: [0x41,0x80,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bltl target
+# CHECK: bltla 2, target                 # encoding: [0x41,0x88,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bltla 2, target
+# CHECK: bltla 0, target                 # encoding: [0x41,0x80,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bltla target
+# CHECK: bltlrl 2                        # encoding: [0x4d,0x88,0x00,0x21]
+         bltlrl 2
+# CHECK: bltlrl 0                        # encoding: [0x4d,0x80,0x00,0x21]
+         bltlrl
 # CHECK: bltctrl 2                       # encoding: [0x4d,0x88,0x04,0x21]
          bltctrl 2
 # CHECK: bltctrl 0                       # encoding: [0x4d,0x80,0x04,0x21]
          bltctrl
 
+# CHECK: blt+ 2, target                  # encoding: [0x41,0xe8,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         blt+ 2, target
+# CHECK: blt+ 0, target                  # encoding: [0x41,0xe0,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         blt+ target
+# CHECK: blta+ 2, target                 # encoding: [0x41,0xe8,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blta+ 2, target
+# CHECK: blta+ 0, target                 # encoding: [0x41,0xe0,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blta+ target
+# CHECK: bltlr+ 2                        # encoding: [0x4d,0xe8,0x00,0x20]
+         bltlr+ 2
+# CHECK: bltlr+ 0                        # encoding: [0x4d,0xe0,0x00,0x20]
+         bltlr+
+# CHECK: bltctr+ 2                       # encoding: [0x4d,0xe8,0x04,0x20]
+         bltctr+ 2
+# CHECK: bltctr+ 0                       # encoding: [0x4d,0xe0,0x04,0x20]
+         bltctr+
+# CHECK: bltl+ 2, target                 # encoding: [0x41,0xe8,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bltl+ 2, target
+# CHECK: bltl+ 0, target                 # encoding: [0x41,0xe0,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bltl+ target
+# CHECK: bltla+ 2, target                # encoding: [0x41,0xe8,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bltla+ 2, target
+# CHECK: bltla+ 0, target                # encoding: [0x41,0xe0,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bltla+ target
+# CHECK: bltlrl+ 2                       # encoding: [0x4d,0xe8,0x00,0x21]
+         bltlrl+ 2
+# CHECK: bltlrl+ 0                       # encoding: [0x4d,0xe0,0x00,0x21]
+         bltlrl+
+# CHECK: bltctrl+ 2                      # encoding: [0x4d,0xe8,0x04,0x21]
+         bltctrl+ 2
+# CHECK: bltctrl+ 0                      # encoding: [0x4d,0xe0,0x04,0x21]
+         bltctrl+
+
+# CHECK: blt- 2, target                  # encoding: [0x41,0xc8,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         blt- 2, target
+# CHECK: blt- 0, target                  # encoding: [0x41,0xc0,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         blt- target
+# CHECK: blta- 2, target                 # encoding: [0x41,0xc8,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blta- 2, target
+# CHECK: blta- 0, target                 # encoding: [0x41,0xc0,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blta- target
+# CHECK: bltlr- 2                        # encoding: [0x4d,0xc8,0x00,0x20]
+         bltlr- 2
+# CHECK: bltlr- 0                        # encoding: [0x4d,0xc0,0x00,0x20]
+         bltlr-
+# CHECK: bltctr- 2                       # encoding: [0x4d,0xc8,0x04,0x20]
+         bltctr- 2
+# CHECK: bltctr- 0                       # encoding: [0x4d,0xc0,0x04,0x20]
+         bltctr-
+# CHECK: bltl- 2, target                 # encoding: [0x41,0xc8,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bltl- 2, target
+# CHECK: bltl- 0, target                 # encoding: [0x41,0xc0,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bltl- target
+# CHECK: bltla- 2, target                # encoding: [0x41,0xc8,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bltla- 2, target
+# CHECK: bltla- 0, target                # encoding: [0x41,0xc0,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bltla- target
+# CHECK: bltlrl- 2                       # encoding: [0x4d,0xc8,0x00,0x21]
+         bltlrl- 2
+# CHECK: bltlrl- 0                       # encoding: [0x4d,0xc0,0x00,0x21]
+         bltlrl-
+# CHECK: bltctrl- 2                      # encoding: [0x4d,0xc8,0x04,0x21]
+         bltctrl- 2
+# CHECK: bltctrl- 0                      # encoding: [0x4d,0xc0,0x04,0x21]
+         bltctrl-
+
 # CHECK: ble 2, target                   # encoding: [0x40,0x89,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          ble 2, target
 # CHECK: ble 0, target                   # encoding: [0x40,0x81,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          ble target
-# FIXME: blea 2, target
-# FIXME: blea target
+# CHECK: blea 2, target                  # encoding: [0x40,0x89,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blea 2, target
+# CHECK: blea 0, target                  # encoding: [0x40,0x81,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blea target
 # CHECK: blelr 2                         # encoding: [0x4c,0x89,0x00,0x20]
          blelr 2
 # CHECK: blelr 0                         # encoding: [0x4c,0x81,0x00,0x20]
@@ -160,25 +551,121 @@
          blectr 2
 # CHECK: blectr 0                        # encoding: [0x4c,0x81,0x04,0x20]
          blectr
-# FIXME: blel 2, target
-# FIXME: blel target
-# FIXME: blela 2, target
-# FIXME: blela target
-# FIXME: blelrl 2
-# FIXME: blelrl
+# CHECK: blel 2, target                  # encoding: [0x40,0x89,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         blel 2, target
+# CHECK: blel 0, target                  # encoding: [0x40,0x81,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         blel target
+# CHECK: blela 2, target                 # encoding: [0x40,0x89,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blela 2, target
+# CHECK: blela 0, target                 # encoding: [0x40,0x81,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blela target
+# CHECK: blelrl 2                        # encoding: [0x4c,0x89,0x00,0x21]
+         blelrl 2
+# CHECK: blelrl 0                        # encoding: [0x4c,0x81,0x00,0x21]
+         blelrl
 # CHECK: blectrl 2                       # encoding: [0x4c,0x89,0x04,0x21]
          blectrl 2
 # CHECK: blectrl 0                       # encoding: [0x4c,0x81,0x04,0x21]
          blectrl
 
+# CHECK: ble+ 2, target                  # encoding: [0x40,0xe9,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         ble+ 2, target
+# CHECK: ble+ 0, target                  # encoding: [0x40,0xe1,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         ble+ target
+# CHECK: blea+ 2, target                 # encoding: [0x40,0xe9,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blea+ 2, target
+# CHECK: blea+ 0, target                 # encoding: [0x40,0xe1,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blea+ target
+# CHECK: blelr+ 2                        # encoding: [0x4c,0xe9,0x00,0x20]
+         blelr+ 2
+# CHECK: blelr+ 0                        # encoding: [0x4c,0xe1,0x00,0x20]
+         blelr+
+# CHECK: blectr+ 2                       # encoding: [0x4c,0xe9,0x04,0x20]
+         blectr+ 2
+# CHECK: blectr+ 0                       # encoding: [0x4c,0xe1,0x04,0x20]
+         blectr+
+# CHECK: blel+ 2, target                 # encoding: [0x40,0xe9,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         blel+ 2, target
+# CHECK: blel+ 0, target                 # encoding: [0x40,0xe1,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         blel+ target
+# CHECK: blela+ 2, target                # encoding: [0x40,0xe9,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blela+ 2, target
+# CHECK: blela+ 0, target                # encoding: [0x40,0xe1,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blela+ target
+# CHECK: blelrl+ 2                       # encoding: [0x4c,0xe9,0x00,0x21]
+         blelrl+ 2
+# CHECK: blelrl+ 0                       # encoding: [0x4c,0xe1,0x00,0x21]
+         blelrl+
+# CHECK: blectrl+ 2                      # encoding: [0x4c,0xe9,0x04,0x21]
+         blectrl+ 2
+# CHECK: blectrl+ 0                      # encoding: [0x4c,0xe1,0x04,0x21]
+         blectrl+
+
+# CHECK: ble- 2, target                  # encoding: [0x40,0xc9,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         ble- 2, target
+# CHECK: ble- 0, target                  # encoding: [0x40,0xc1,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         ble- target
+# CHECK: blea- 2, target                 # encoding: [0x40,0xc9,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blea- 2, target
+# CHECK: blea- 0, target                 # encoding: [0x40,0xc1,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blea- target
+# CHECK: blelr- 2                        # encoding: [0x4c,0xc9,0x00,0x20]
+         blelr- 2
+# CHECK: blelr- 0                        # encoding: [0x4c,0xc1,0x00,0x20]
+         blelr-
+# CHECK: blectr- 2                       # encoding: [0x4c,0xc9,0x04,0x20]
+         blectr- 2
+# CHECK: blectr- 0                       # encoding: [0x4c,0xc1,0x04,0x20]
+         blectr-
+# CHECK: blel- 2, target                 # encoding: [0x40,0xc9,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         blel- 2, target
+# CHECK: blel- 0, target                 # encoding: [0x40,0xc1,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         blel- target
+# CHECK: blela- 2, target                # encoding: [0x40,0xc9,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blela- 2, target
+# CHECK: blela- 0, target                # encoding: [0x40,0xc1,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         blela- target
+# CHECK: blelrl- 2                       # encoding: [0x4c,0xc9,0x00,0x21]
+         blelrl- 2
+# CHECK: blelrl- 0                       # encoding: [0x4c,0xc1,0x00,0x21]
+         blelrl-
+# CHECK: blectrl- 2                      # encoding: [0x4c,0xc9,0x04,0x21]
+         blectrl- 2
+# CHECK: blectrl- 0                      # encoding: [0x4c,0xc1,0x04,0x21]
+         blectrl-
+
 # CHECK: beq 2, target                   # encoding: [0x41,0x8a,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          beq 2, target
 # CHECK: beq 0, target                   # encoding: [0x41,0x82,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          beq target
-# FIXME: beqa 2, target
-# FIXME: beqa target
+# CHECK: beqa 2, target                  # encoding: [0x41,0x8a,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         beqa 2, target
+# CHECK: beqa 0, target                  # encoding: [0x41,0x82,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         beqa target
 # CHECK: beqlr 2                         # encoding: [0x4d,0x8a,0x00,0x20]
          beqlr 2
 # CHECK: beqlr 0                         # encoding: [0x4d,0x82,0x00,0x20]
@@ -187,25 +674,121 @@
          beqctr 2
 # CHECK: beqctr 0                        # encoding: [0x4d,0x82,0x04,0x20]
          beqctr
-# FIXME: beql 2, target
-# FIXME: beql target
-# FIXME: beqla 2, target
-# FIXME: beqla target
-# FIXME: beqlrl 2
-# FIXME: beqlrl
+# CHECK: beql 2, target                  # encoding: [0x41,0x8a,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         beql 2, target
+# CHECK: beql 0, target                  # encoding: [0x41,0x82,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         beql target
+# CHECK: beqla 2, target                 # encoding: [0x41,0x8a,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         beqla 2, target
+# CHECK: beqla 0, target                 # encoding: [0x41,0x82,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         beqla target
+# CHECK: beqlrl 2                        # encoding: [0x4d,0x8a,0x00,0x21]
+         beqlrl 2
+# CHECK: beqlrl 0                        # encoding: [0x4d,0x82,0x00,0x21]
+         beqlrl
 # CHECK: beqctrl 2                       # encoding: [0x4d,0x8a,0x04,0x21]
          beqctrl 2
 # CHECK: beqctrl 0                       # encoding: [0x4d,0x82,0x04,0x21]
          beqctrl
 
+# CHECK: beq+ 2, target                  # encoding: [0x41,0xea,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         beq+ 2, target
+# CHECK: beq+ 0, target                  # encoding: [0x41,0xe2,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         beq+ target
+# CHECK: beqa+ 2, target                 # encoding: [0x41,0xea,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         beqa+ 2, target
+# CHECK: beqa+ 0, target                 # encoding: [0x41,0xe2,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         beqa+ target
+# CHECK: beqlr+ 2                        # encoding: [0x4d,0xea,0x00,0x20]
+         beqlr+ 2
+# CHECK: beqlr+ 0                        # encoding: [0x4d,0xe2,0x00,0x20]
+         beqlr+
+# CHECK: beqctr+ 2                       # encoding: [0x4d,0xea,0x04,0x20]
+         beqctr+ 2
+# CHECK: beqctr+ 0                       # encoding: [0x4d,0xe2,0x04,0x20]
+         beqctr+
+# CHECK: beql+ 2, target                 # encoding: [0x41,0xea,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         beql+ 2, target
+# CHECK: beql+ 0, target                 # encoding: [0x41,0xe2,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         beql+ target
+# CHECK: beqla+ 2, target                # encoding: [0x41,0xea,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         beqla+ 2, target
+# CHECK: beqla+ 0, target                # encoding: [0x41,0xe2,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         beqla+ target
+# CHECK: beqlrl+ 2                       # encoding: [0x4d,0xea,0x00,0x21]
+         beqlrl+ 2
+# CHECK: beqlrl+ 0                       # encoding: [0x4d,0xe2,0x00,0x21]
+         beqlrl+
+# CHECK: beqctrl+ 2                      # encoding: [0x4d,0xea,0x04,0x21]
+         beqctrl+ 2
+# CHECK: beqctrl+ 0                      # encoding: [0x4d,0xe2,0x04,0x21]
+         beqctrl+
+
+# CHECK: beq- 2, target                  # encoding: [0x41,0xca,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         beq- 2, target
+# CHECK: beq- 0, target                  # encoding: [0x41,0xc2,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         beq- target
+# CHECK: beqa- 2, target                 # encoding: [0x41,0xca,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         beqa- 2, target
+# CHECK: beqa- 0, target                 # encoding: [0x41,0xc2,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         beqa- target
+# CHECK: beqlr- 2                        # encoding: [0x4d,0xca,0x00,0x20]
+         beqlr- 2
+# CHECK: beqlr- 0                        # encoding: [0x4d,0xc2,0x00,0x20]
+         beqlr-
+# CHECK: beqctr- 2                       # encoding: [0x4d,0xca,0x04,0x20]
+         beqctr- 2
+# CHECK: beqctr- 0                       # encoding: [0x4d,0xc2,0x04,0x20]
+         beqctr-
+# CHECK: beql- 2, target                 # encoding: [0x41,0xca,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         beql- 2, target
+# CHECK: beql- 0, target                 # encoding: [0x41,0xc2,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         beql- target
+# CHECK: beqla- 2, target                # encoding: [0x41,0xca,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         beqla- 2, target
+# CHECK: beqla- 0, target                # encoding: [0x41,0xc2,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         beqla- target
+# CHECK: beqlrl- 2                       # encoding: [0x4d,0xca,0x00,0x21]
+         beqlrl- 2
+# CHECK: beqlrl- 0                       # encoding: [0x4d,0xc2,0x00,0x21]
+         beqlrl-
+# CHECK: beqctrl- 2                      # encoding: [0x4d,0xca,0x04,0x21]
+         beqctrl- 2
+# CHECK: beqctrl- 0                      # encoding: [0x4d,0xc2,0x04,0x21]
+         beqctrl-
+
 # CHECK: bge 2, target                   # encoding: [0x40,0x88,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bge 2, target
 # CHECK: bge 0, target                   # encoding: [0x40,0x80,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bge target
-# FIXME: bgea 2, target
-# FIXME: bgea target
+# CHECK: bgea 2, target                  # encoding: [0x40,0x88,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgea 2, target
+# CHECK: bgea 0, target                  # encoding: [0x40,0x80,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgea target
 # CHECK: bgelr 2                         # encoding: [0x4c,0x88,0x00,0x20]
          bgelr 2
 # CHECK: bgelr 0                         # encoding: [0x4c,0x80,0x00,0x20]
@@ -214,25 +797,121 @@
          bgectr 2
 # CHECK: bgectr 0                        # encoding: [0x4c,0x80,0x04,0x20]
          bgectr
-# FIXME: bgel 2, target
-# FIXME: bgel target
-# FIXME: bgela 2, target
-# FIXME: bgela target
-# FIXME: bgelrl 2
-# FIXME: bgelrl
+# CHECK: bgel 2, target                  # encoding: [0x40,0x88,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgel 2, target
+# CHECK: bgel 0, target                  # encoding: [0x40,0x80,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgel target
+# CHECK: bgela 2, target                 # encoding: [0x40,0x88,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgela 2, target
+# CHECK: bgela 0, target                 # encoding: [0x40,0x80,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgela target
+# CHECK: bgelrl 2                        # encoding: [0x4c,0x88,0x00,0x21]
+         bgelrl 2
+# CHECK: bgelrl 0                        # encoding: [0x4c,0x80,0x00,0x21]
+         bgelrl
 # CHECK: bgectrl 2                       # encoding: [0x4c,0x88,0x04,0x21]
          bgectrl 2
 # CHECK: bgectrl 0                       # encoding: [0x4c,0x80,0x04,0x21]
          bgectrl
 
+# CHECK: bge+ 2, target                   # encoding: [0x40,0xe8,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bge+ 2, target
+# CHECK: bge+ 0, target                   # encoding: [0x40,0xe0,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bge+ target
+# CHECK: bgea+ 2, target                  # encoding: [0x40,0xe8,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgea+ 2, target
+# CHECK: bgea+ 0, target                  # encoding: [0x40,0xe0,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgea+ target
+# CHECK: bgelr+ 2                         # encoding: [0x4c,0xe8,0x00,0x20]
+         bgelr+ 2
+# CHECK: bgelr+ 0                         # encoding: [0x4c,0xe0,0x00,0x20]
+         bgelr+
+# CHECK: bgectr+ 2                        # encoding: [0x4c,0xe8,0x04,0x20]
+         bgectr+ 2
+# CHECK: bgectr+ 0                        # encoding: [0x4c,0xe0,0x04,0x20]
+         bgectr+
+# CHECK: bgel+ 2, target                  # encoding: [0x40,0xe8,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgel+ 2, target
+# CHECK: bgel+ 0, target                  # encoding: [0x40,0xe0,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgel+ target
+# CHECK: bgela+ 2, target                 # encoding: [0x40,0xe8,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgela+ 2, target
+# CHECK: bgela+ 0, target                 # encoding: [0x40,0xe0,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgela+ target
+# CHECK: bgelrl+ 2                        # encoding: [0x4c,0xe8,0x00,0x21]
+         bgelrl+ 2
+# CHECK: bgelrl+ 0                        # encoding: [0x4c,0xe0,0x00,0x21]
+         bgelrl+
+# CHECK: bgectrl+ 2                       # encoding: [0x4c,0xe8,0x04,0x21]
+         bgectrl+ 2
+# CHECK: bgectrl+ 0                       # encoding: [0x4c,0xe0,0x04,0x21]
+         bgectrl+
+
+# CHECK: bge- 2, target                   # encoding: [0x40,0xc8,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bge- 2, target
+# CHECK: bge- 0, target                   # encoding: [0x40,0xc0,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bge- target
+# CHECK: bgea- 2, target                  # encoding: [0x40,0xc8,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgea- 2, target
+# CHECK: bgea- 0, target                  # encoding: [0x40,0xc0,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgea- target
+# CHECK: bgelr- 2                         # encoding: [0x4c,0xc8,0x00,0x20]
+         bgelr- 2
+# CHECK: bgelr- 0                         # encoding: [0x4c,0xc0,0x00,0x20]
+         bgelr-
+# CHECK: bgectr- 2                        # encoding: [0x4c,0xc8,0x04,0x20]
+         bgectr- 2
+# CHECK: bgectr- 0                        # encoding: [0x4c,0xc0,0x04,0x20]
+         bgectr-
+# CHECK: bgel- 2, target                  # encoding: [0x40,0xc8,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgel- 2, target
+# CHECK: bgel- 0, target                  # encoding: [0x40,0xc0,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgel- target
+# CHECK: bgela- 2, target                 # encoding: [0x40,0xc8,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgela- 2, target
+# CHECK: bgela- 0, target                 # encoding: [0x40,0xc0,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgela- target
+# CHECK: bgelrl- 2                        # encoding: [0x4c,0xc8,0x00,0x21]
+         bgelrl- 2
+# CHECK: bgelrl- 0                        # encoding: [0x4c,0xc0,0x00,0x21]
+         bgelrl-
+# CHECK: bgectrl- 2                       # encoding: [0x4c,0xc8,0x04,0x21]
+         bgectrl- 2
+# CHECK: bgectrl- 0                       # encoding: [0x4c,0xc0,0x04,0x21]
+         bgectrl-
+
 # CHECK: bgt 2, target                   # encoding: [0x41,0x89,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bgt 2, target
 # CHECK: bgt 0, target                   # encoding: [0x41,0x81,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bgt target
-# FIXME: bgta 2, target
-# FIXME: bgta target
+# CHECK: bgta 2, target                  # encoding: [0x41,0x89,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgta 2, target
+# CHECK: bgta 0, target                  # encoding: [0x41,0x81,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgta target
 # CHECK: bgtlr 2                         # encoding: [0x4d,0x89,0x00,0x20]
          bgtlr 2
 # CHECK: bgtlr 0                         # encoding: [0x4d,0x81,0x00,0x20]
@@ -241,25 +920,121 @@
          bgtctr 2
 # CHECK: bgtctr 0                        # encoding: [0x4d,0x81,0x04,0x20]
          bgtctr
-# FIXME: bgtl 2, target
-# FIXME: bgtl target
-# FIXME: bgtla 2, target
-# FIXME: bgtla target
-# FIXME: bgtlrl 2
-# FIXME: bgtlrl
+# CHECK: bgtl 2, target                  # encoding: [0x41,0x89,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgtl 2, target
+# CHECK: bgtl 0, target                  # encoding: [0x41,0x81,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgtl target
+# CHECK: bgtla 2, target                 # encoding: [0x41,0x89,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgtla 2, target
+# CHECK: bgtla 0, target                 # encoding: [0x41,0x81,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgtla target
+# CHECK: bgtlrl 2                        # encoding: [0x4d,0x89,0x00,0x21]
+         bgtlrl 2
+# CHECK: bgtlrl 0                        # encoding: [0x4d,0x81,0x00,0x21]
+         bgtlrl
 # CHECK: bgtctrl 2                       # encoding: [0x4d,0x89,0x04,0x21]
          bgtctrl 2
 # CHECK: bgtctrl 0                       # encoding: [0x4d,0x81,0x04,0x21]
          bgtctrl
 
+# CHECK: bgt+ 2, target                  # encoding: [0x41,0xe9,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgt+ 2, target
+# CHECK: bgt+ 0, target                  # encoding: [0x41,0xe1,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgt+ target
+# CHECK: bgta+ 2, target                 # encoding: [0x41,0xe9,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgta+ 2, target
+# CHECK: bgta+ 0, target                 # encoding: [0x41,0xe1,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgta+ target
+# CHECK: bgtlr+ 2                        # encoding: [0x4d,0xe9,0x00,0x20]
+         bgtlr+ 2
+# CHECK: bgtlr+ 0                        # encoding: [0x4d,0xe1,0x00,0x20]
+         bgtlr+
+# CHECK: bgtctr+ 2                       # encoding: [0x4d,0xe9,0x04,0x20]
+         bgtctr+ 2
+# CHECK: bgtctr+ 0                       # encoding: [0x4d,0xe1,0x04,0x20]
+         bgtctr+
+# CHECK: bgtl+ 2, target                 # encoding: [0x41,0xe9,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgtl+ 2, target
+# CHECK: bgtl+ 0, target                 # encoding: [0x41,0xe1,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgtl+ target
+# CHECK: bgtla+ 2, target                # encoding: [0x41,0xe9,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgtla+ 2, target
+# CHECK: bgtla+ 0, target                # encoding: [0x41,0xe1,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgtla+ target
+# CHECK: bgtlrl+ 2                       # encoding: [0x4d,0xe9,0x00,0x21]
+         bgtlrl+ 2
+# CHECK: bgtlrl+ 0                       # encoding: [0x4d,0xe1,0x00,0x21]
+         bgtlrl+
+# CHECK: bgtctrl+ 2                      # encoding: [0x4d,0xe9,0x04,0x21]
+         bgtctrl+ 2
+# CHECK: bgtctrl+ 0                      # encoding: [0x4d,0xe1,0x04,0x21]
+         bgtctrl+
+
+# CHECK: bgt- 2, target                  # encoding: [0x41,0xc9,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgt- 2, target
+# CHECK: bgt- 0, target                  # encoding: [0x41,0xc1,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgt- target
+# CHECK: bgta- 2, target                 # encoding: [0x41,0xc9,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgta- 2, target
+# CHECK: bgta- 0, target                 # encoding: [0x41,0xc1,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgta- target
+# CHECK: bgtlr- 2                        # encoding: [0x4d,0xc9,0x00,0x20]
+         bgtlr- 2
+# CHECK: bgtlr- 0                        # encoding: [0x4d,0xc1,0x00,0x20]
+         bgtlr-
+# CHECK: bgtctr- 2                       # encoding: [0x4d,0xc9,0x04,0x20]
+         bgtctr- 2
+# CHECK: bgtctr- 0                       # encoding: [0x4d,0xc1,0x04,0x20]
+         bgtctr-
+# CHECK: bgtl- 2, target                 # encoding: [0x41,0xc9,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgtl- 2, target
+# CHECK: bgtl- 0, target                 # encoding: [0x41,0xc1,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bgtl- target
+# CHECK: bgtla- 2, target                # encoding: [0x41,0xc9,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgtla- 2, target
+# CHECK: bgtla- 0, target                # encoding: [0x41,0xc1,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bgtla- target
+# CHECK: bgtlrl- 2                       # encoding: [0x4d,0xc9,0x00,0x21]
+         bgtlrl- 2
+# CHECK: bgtlrl- 0                       # encoding: [0x4d,0xc1,0x00,0x21]
+         bgtlrl-
+# CHECK: bgtctrl- 2                      # encoding: [0x4d,0xc9,0x04,0x21]
+         bgtctrl- 2
+# CHECK: bgtctrl- 0                      # encoding: [0x4d,0xc1,0x04,0x21]
+         bgtctrl-
+
 # CHECK: bge 2, target                   # encoding: [0x40,0x88,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bnl 2, target
 # CHECK: bge 0, target                   # encoding: [0x40,0x80,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bnl target
-# FIXME: bnla 2, target
-# FIXME: bnla target
+# CHECK: bgea 2, target                  # encoding: [0x40,0x88,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnla 2, target
+# CHECK: bgea 0, target                  # encoding: [0x40,0x80,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnla target
 # CHECK: bgelr 2                         # encoding: [0x4c,0x88,0x00,0x20]
          bnllr 2
 # CHECK: bgelr 0                         # encoding: [0x4c,0x80,0x00,0x20]
@@ -268,25 +1043,121 @@
          bnlctr 2
 # CHECK: bgectr 0                        # encoding: [0x4c,0x80,0x04,0x20]
          bnlctr
-# FIXME: bnll 2, target
-# FIXME: bnll target
-# FIXME: bnlla 2, target
-# FIXME: bnlla target
-# FIXME: bnllrl 2
-# FIXME: bnllrl
+# CHECK: bgel 2, target                  # encoding: [0x40,0x88,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnll 2, target
+# CHECK: bgel 0, target                  # encoding: [0x40,0x80,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnll target
+# CHECK: bgela 2, target                  # encoding: [0x40,0x88,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnlla 2, target
+# CHECK: bgela 0, target                  # encoding: [0x40,0x80,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnlla target
+# CHECK: bgelrl 2                        # encoding: [0x4c,0x88,0x00,0x21]
+         bnllrl 2
+# CHECK: bgelrl 0                        # encoding: [0x4c,0x80,0x00,0x21]
+         bnllrl
 # CHECK: bgectrl 2                       # encoding: [0x4c,0x88,0x04,0x21]
          bnlctrl 2
 # CHECK: bgectrl 0                       # encoding: [0x4c,0x80,0x04,0x21]
          bnlctrl
 
+# CHECK: bge+ 2, target                  # encoding: [0x40,0xe8,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnl+ 2, target
+# CHECK: bge+ 0, target                  # encoding: [0x40,0xe0,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnl+ target
+# CHECK: bgea+ 2, target                 # encoding: [0x40,0xe8,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnla+ 2, target
+# CHECK: bgea+ 0, target                 # encoding: [0x40,0xe0,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnla+ target
+# CHECK: bgelr+ 2                        # encoding: [0x4c,0xe8,0x00,0x20]
+         bnllr+ 2
+# CHECK: bgelr+ 0                        # encoding: [0x4c,0xe0,0x00,0x20]
+         bnllr+
+# CHECK: bgectr+ 2                       # encoding: [0x4c,0xe8,0x04,0x20]
+         bnlctr+ 2
+# CHECK: bgectr+ 0                       # encoding: [0x4c,0xe0,0x04,0x20]
+         bnlctr+
+# CHECK: bgel+ 2, target                 # encoding: [0x40,0xe8,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnll+ 2, target
+# CHECK: bgel+ 0, target                 # encoding: [0x40,0xe0,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnll+ target
+# CHECK: bgela+ 2, target                # encoding: [0x40,0xe8,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnlla+ 2, target
+# CHECK: bgela+ 0, target                # encoding: [0x40,0xe0,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnlla+ target
+# CHECK: bgelrl+ 2                       # encoding: [0x4c,0xe8,0x00,0x21]
+         bnllrl+ 2
+# CHECK: bgelrl+ 0                       # encoding: [0x4c,0xe0,0x00,0x21]
+         bnllrl+
+# CHECK: bgectrl+ 2                      # encoding: [0x4c,0xe8,0x04,0x21]
+         bnlctrl+ 2
+# CHECK: bgectrl+ 0                      # encoding: [0x4c,0xe0,0x04,0x21]
+         bnlctrl+
+
+# CHECK: bge- 2, target                  # encoding: [0x40,0xc8,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnl- 2, target
+# CHECK: bge- 0, target                  # encoding: [0x40,0xc0,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnl- target
+# CHECK: bgea- 2, target                 # encoding: [0x40,0xc8,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnla- 2, target
+# CHECK: bgea- 0, target                 # encoding: [0x40,0xc0,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnla- target
+# CHECK: bgelr- 2                        # encoding: [0x4c,0xc8,0x00,0x20]
+         bnllr- 2
+# CHECK: bgelr- 0                        # encoding: [0x4c,0xc0,0x00,0x20]
+         bnllr-
+# CHECK: bgectr- 2                       # encoding: [0x4c,0xc8,0x04,0x20]
+         bnlctr- 2
+# CHECK: bgectr- 0                       # encoding: [0x4c,0xc0,0x04,0x20]
+         bnlctr-
+# CHECK: bgel- 2, target                 # encoding: [0x40,0xc8,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnll- 2, target
+# CHECK: bgel- 0, target                 # encoding: [0x40,0xc0,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnll- target
+# CHECK: bgela- 2, target                # encoding: [0x40,0xc8,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnlla- 2, target
+# CHECK: bgela- 0, target                # encoding: [0x40,0xc0,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnlla- target
+# CHECK: bgelrl- 2                       # encoding: [0x4c,0xc8,0x00,0x21]
+         bnllrl- 2
+# CHECK: bgelrl- 0                       # encoding: [0x4c,0xc0,0x00,0x21]
+         bnllrl-
+# CHECK: bgectrl- 2                      # encoding: [0x4c,0xc8,0x04,0x21]
+         bnlctrl- 2
+# CHECK: bgectrl- 0                      # encoding: [0x4c,0xc0,0x04,0x21]
+         bnlctrl-
+
 # CHECK: bne 2, target                   # encoding: [0x40,0x8a,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bne 2, target
 # CHECK: bne 0, target                   # encoding: [0x40,0x82,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bne target
-# FIXME: bnea 2, target
-# FIXME: bnea target
+# CHECK: bnea 2, target                  # encoding: [0x40,0x8a,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnea 2, target
+# CHECK: bnea 0, target                  # encoding: [0x40,0x82,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnea target
 # CHECK: bnelr 2                         # encoding: [0x4c,0x8a,0x00,0x20]
          bnelr 2
 # CHECK: bnelr 0                         # encoding: [0x4c,0x82,0x00,0x20]
@@ -295,25 +1166,121 @@
          bnectr 2
 # CHECK: bnectr 0                        # encoding: [0x4c,0x82,0x04,0x20]
          bnectr
-# FIXME: bnel 2, target
-# FIXME: bnel target
-# FIXME: bnela 2, target
-# FIXME: bnela target
-# FIXME: bnelrl 2
-# FIXME: bnelrl
+# CHECK: bnel 2, target                  # encoding: [0x40,0x8a,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnel 2, target
+# CHECK: bnel 0, target                  # encoding: [0x40,0x82,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnel target
+# CHECK: bnela 2, target                 # encoding: [0x40,0x8a,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnela 2, target
+# CHECK: bnela 0, target                 # encoding: [0x40,0x82,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnela target
+# CHECK: bnelrl 2                        # encoding: [0x4c,0x8a,0x00,0x21]
+         bnelrl 2
+# CHECK: bnelrl 0                        # encoding: [0x4c,0x82,0x00,0x21]
+         bnelrl
 # CHECK: bnectrl 2                       # encoding: [0x4c,0x8a,0x04,0x21]
          bnectrl 2
 # CHECK: bnectrl 0                       # encoding: [0x4c,0x82,0x04,0x21]
          bnectrl
 
+# CHECK: bne+ 2, target                  # encoding: [0x40,0xea,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bne+ 2, target
+# CHECK: bne+ 0, target                  # encoding: [0x40,0xe2,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bne+ target
+# CHECK: bnea+ 2, target                 # encoding: [0x40,0xea,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnea+ 2, target
+# CHECK: bnea+ 0, target                 # encoding: [0x40,0xe2,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnea+ target
+# CHECK: bnelr+ 2                        # encoding: [0x4c,0xea,0x00,0x20]
+         bnelr+ 2
+# CHECK: bnelr+ 0                        # encoding: [0x4c,0xe2,0x00,0x20]
+         bnelr+
+# CHECK: bnectr+ 2                       # encoding: [0x4c,0xea,0x04,0x20]
+         bnectr+ 2
+# CHECK: bnectr+ 0                       # encoding: [0x4c,0xe2,0x04,0x20]
+         bnectr+
+# CHECK: bnel+ 2, target                 # encoding: [0x40,0xea,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnel+ 2, target
+# CHECK: bnel+ 0, target                 # encoding: [0x40,0xe2,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnel+ target
+# CHECK: bnela+ 2, target                # encoding: [0x40,0xea,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnela+ 2, target
+# CHECK: bnela+ 0, target                # encoding: [0x40,0xe2,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnela+ target
+# CHECK: bnelrl+ 2                       # encoding: [0x4c,0xea,0x00,0x21]
+         bnelrl+ 2
+# CHECK: bnelrl+ 0                       # encoding: [0x4c,0xe2,0x00,0x21]
+         bnelrl+
+# CHECK: bnectrl+ 2                      # encoding: [0x4c,0xea,0x04,0x21]
+         bnectrl+ 2
+# CHECK: bnectrl+ 0                      # encoding: [0x4c,0xe2,0x04,0x21]
+         bnectrl+
+
+# CHECK: bne- 2, target                  # encoding: [0x40,0xca,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bne- 2, target
+# CHECK: bne- 0, target                  # encoding: [0x40,0xc2,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bne- target
+# CHECK: bnea- 2, target                 # encoding: [0x40,0xca,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnea- 2, target
+# CHECK: bnea- 0, target                 # encoding: [0x40,0xc2,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnea- target
+# CHECK: bnelr- 2                        # encoding: [0x4c,0xca,0x00,0x20]
+         bnelr- 2
+# CHECK: bnelr- 0                        # encoding: [0x4c,0xc2,0x00,0x20]
+         bnelr-
+# CHECK: bnectr- 2                       # encoding: [0x4c,0xca,0x04,0x20]
+         bnectr- 2
+# CHECK: bnectr- 0                       # encoding: [0x4c,0xc2,0x04,0x20]
+         bnectr-
+# CHECK: bnel- 2, target                 # encoding: [0x40,0xca,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnel- 2, target
+# CHECK: bnel- 0, target                 # encoding: [0x40,0xc2,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnel- target
+# CHECK: bnela- 2, target                # encoding: [0x40,0xca,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnela- 2, target
+# CHECK: bnela- 0, target                # encoding: [0x40,0xc2,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnela- target
+# CHECK: bnelrl- 2                       # encoding: [0x4c,0xca,0x00,0x21]
+         bnelrl- 2
+# CHECK: bnelrl- 0                       # encoding: [0x4c,0xc2,0x00,0x21]
+         bnelrl-
+# CHECK: bnectrl- 2                      # encoding: [0x4c,0xca,0x04,0x21]
+         bnectrl- 2
+# CHECK: bnectrl- 0                      # encoding: [0x4c,0xc2,0x04,0x21]
+         bnectrl-
+
 # CHECK: ble 2, target                   # encoding: [0x40,0x89,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bng 2, target
 # CHECK: ble 0, target                   # encoding: [0x40,0x81,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bng target
-# FIXME: bnga 2, target
-# FIXME: bnga target
+# CHECK: blea 2, target                  # encoding: [0x40,0x89,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnga 2, target
+# CHECK: blea 0, target                  # encoding: [0x40,0x81,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnga target
 # CHECK: blelr 2                         # encoding: [0x4c,0x89,0x00,0x20]
          bnglr 2
 # CHECK: blelr 0                         # encoding: [0x4c,0x81,0x00,0x20]
@@ -322,25 +1289,121 @@
          bngctr 2
 # CHECK: blectr 0                        # encoding: [0x4c,0x81,0x04,0x20]
          bngctr
-# FIXME: bngl 2, target
-# FIXME: bngl target
-# FIXME: bngla 2, target
-# FIXME: bngla target
-# FIXME: bnglrl 2
-# FIXME: bnglrl
+# CHECK: blel 2, target                  # encoding: [0x40,0x89,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bngl 2, target
+# CHECK: blel 0, target                  # encoding: [0x40,0x81,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bngl target
+# CHECK: blela 2, target                 # encoding: [0x40,0x89,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bngla 2, target
+# CHECK: blela 0, target                 # encoding: [0x40,0x81,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bngla target
+# CHECK: blelrl 2                        # encoding: [0x4c,0x89,0x00,0x21]
+         bnglrl 2
+# CHECK: blelrl 0                        # encoding: [0x4c,0x81,0x00,0x21]
+         bnglrl
 # CHECK: blectrl 2                       # encoding: [0x4c,0x89,0x04,0x21]
          bngctrl 2
 # CHECK: blectrl 0                       # encoding: [0x4c,0x81,0x04,0x21]
          bngctrl
 
+# CHECK: ble+ 2, target                   # encoding: [0x40,0xe9,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bng+ 2, target
+# CHECK: ble+ 0, target                   # encoding: [0x40,0xe1,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bng+ target
+# CHECK: blea+ 2, target                  # encoding: [0x40,0xe9,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnga+ 2, target
+# CHECK: blea+ 0, target                  # encoding: [0x40,0xe1,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnga+ target
+# CHECK: blelr+ 2                         # encoding: [0x4c,0xe9,0x00,0x20]
+         bnglr+ 2
+# CHECK: blelr+ 0                         # encoding: [0x4c,0xe1,0x00,0x20]
+         bnglr+
+# CHECK: blectr+ 2                        # encoding: [0x4c,0xe9,0x04,0x20]
+         bngctr+ 2
+# CHECK: blectr+ 0                        # encoding: [0x4c,0xe1,0x04,0x20]
+         bngctr+
+# CHECK: blel+ 2, target                  # encoding: [0x40,0xe9,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bngl+ 2, target
+# CHECK: blel+ 0, target                  # encoding: [0x40,0xe1,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bngl+ target
+# CHECK: blela+ 2, target                 # encoding: [0x40,0xe9,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bngla+ 2, target
+# CHECK: blela+ 0, target                 # encoding: [0x40,0xe1,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bngla+ target
+# CHECK: blelrl+ 2                        # encoding: [0x4c,0xe9,0x00,0x21]
+         bnglrl+ 2
+# CHECK: blelrl+ 0                        # encoding: [0x4c,0xe1,0x00,0x21]
+         bnglrl+
+# CHECK: blectrl+ 2                       # encoding: [0x4c,0xe9,0x04,0x21]
+         bngctrl+ 2
+# CHECK: blectrl+ 0                       # encoding: [0x4c,0xe1,0x04,0x21]
+         bngctrl+
+
+# CHECK: ble- 2, target                   # encoding: [0x40,0xc9,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bng- 2, target
+# CHECK: ble- 0, target                   # encoding: [0x40,0xc1,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bng- target
+# CHECK: blea- 2, target                  # encoding: [0x40,0xc9,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnga- 2, target
+# CHECK: blea- 0, target                  # encoding: [0x40,0xc1,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnga- target
+# CHECK: blelr- 2                         # encoding: [0x4c,0xc9,0x00,0x20]
+         bnglr- 2
+# CHECK: blelr- 0                         # encoding: [0x4c,0xc1,0x00,0x20]
+         bnglr-
+# CHECK: blectr- 2                        # encoding: [0x4c,0xc9,0x04,0x20]
+         bngctr- 2
+# CHECK: blectr- 0                        # encoding: [0x4c,0xc1,0x04,0x20]
+         bngctr-
+# CHECK: blel- 2, target                  # encoding: [0x40,0xc9,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bngl- 2, target
+# CHECK: blel- 0, target                  # encoding: [0x40,0xc1,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bngl- target
+# CHECK: blela- 2, target                 # encoding: [0x40,0xc9,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bngla- 2, target
+# CHECK: blela- 0, target                 # encoding: [0x40,0xc1,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bngla- target
+# CHECK: blelrl- 2                        # encoding: [0x4c,0xc9,0x00,0x21]
+         bnglrl- 2
+# CHECK: blelrl- 0                        # encoding: [0x4c,0xc1,0x00,0x21]
+         bnglrl-
+# CHECK: blectrl- 2                       # encoding: [0x4c,0xc9,0x04,0x21]
+         bngctrl- 2
+# CHECK: blectrl- 0                       # encoding: [0x4c,0xc1,0x04,0x21]
+         bngctrl-
+
 # CHECK: bun 2, target                   # encoding: [0x41,0x8b,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bso 2, target
 # CHECK: bun 0, target                   # encoding: [0x41,0x83,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bso target
-# FIXME: bsoa 2, target
-# FIXME: bsoa target
+# CHECK: buna 2, target                  # encoding: [0x41,0x8b,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bsoa 2, target
+# CHECK: buna 0, target                  # encoding: [0x41,0x83,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bsoa target
 # CHECK: bunlr 2                         # encoding: [0x4d,0x8b,0x00,0x20]
          bsolr 2
 # CHECK: bunlr 0                         # encoding: [0x4d,0x83,0x00,0x20]
@@ -349,25 +1412,121 @@
          bsoctr 2
 # CHECK: bunctr 0                        # encoding: [0x4d,0x83,0x04,0x20]
          bsoctr
-# FIXME: bsol 2, target
-# FIXME: bsol target
-# FIXME: bsola 2, target
-# FIXME: bsola target
-# FIXME: bsolrl 2
-# FIXME: bsolrl
+# CHECK: bunl 2, target                  # encoding: [0x41,0x8b,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bsol 2, target
+# CHECK: bunl 0, target                  # encoding: [0x41,0x83,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bsol target
+# CHECK: bunla 2, target                 # encoding: [0x41,0x8b,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bsola 2, target
+# CHECK: bunla 0, target                 # encoding: [0x41,0x83,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bsola target
+# CHECK: bunlrl 2                        # encoding: [0x4d,0x8b,0x00,0x21]
+         bsolrl 2
+# CHECK: bunlrl 0                        # encoding: [0x4d,0x83,0x00,0x21]
+         bsolrl
 # CHECK: bunctrl 2                       # encoding: [0x4d,0x8b,0x04,0x21]
          bsoctrl 2
 # CHECK: bunctrl 0                       # encoding: [0x4d,0x83,0x04,0x21]
          bsoctrl
 
+# CHECK: bun+ 2, target                  # encoding: [0x41,0xeb,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bso+ 2, target
+# CHECK: bun+ 0, target                  # encoding: [0x41,0xe3,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bso+ target
+# CHECK: buna+ 2, target                 # encoding: [0x41,0xeb,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bsoa+ 2, target
+# CHECK: buna+ 0, target                 # encoding: [0x41,0xe3,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bsoa+ target
+# CHECK: bunlr+ 2                        # encoding: [0x4d,0xeb,0x00,0x20]
+         bsolr+ 2
+# CHECK: bunlr+ 0                        # encoding: [0x4d,0xe3,0x00,0x20]
+         bsolr+
+# CHECK: bunctr+ 2                       # encoding: [0x4d,0xeb,0x04,0x20]
+         bsoctr+ 2
+# CHECK: bunctr+ 0                       # encoding: [0x4d,0xe3,0x04,0x20]
+         bsoctr+
+# CHECK: bunl+ 2, target                 # encoding: [0x41,0xeb,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bsol+ 2, target
+# CHECK: bunl+ 0, target                 # encoding: [0x41,0xe3,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bsol+ target
+# CHECK: bunla+ 2, target                # encoding: [0x41,0xeb,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bsola+ 2, target
+# CHECK: bunla+ 0, target                # encoding: [0x41,0xe3,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bsola+ target
+# CHECK: bunlrl+ 2                       # encoding: [0x4d,0xeb,0x00,0x21]
+         bsolrl+ 2
+# CHECK: bunlrl+ 0                       # encoding: [0x4d,0xe3,0x00,0x21]
+         bsolrl+
+# CHECK: bunctrl+ 2                      # encoding: [0x4d,0xeb,0x04,0x21]
+         bsoctrl+ 2
+# CHECK: bunctrl+ 0                      # encoding: [0x4d,0xe3,0x04,0x21]
+         bsoctrl+
+
+# CHECK: bun- 2, target                  # encoding: [0x41,0xcb,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bso- 2, target
+# CHECK: bun- 0, target                  # encoding: [0x41,0xc3,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bso- target
+# CHECK: buna- 2, target                 # encoding: [0x41,0xcb,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bsoa- 2, target
+# CHECK: buna- 0, target                 # encoding: [0x41,0xc3,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bsoa- target
+# CHECK: bunlr- 2                        # encoding: [0x4d,0xcb,0x00,0x20]
+         bsolr- 2
+# CHECK: bunlr- 0                        # encoding: [0x4d,0xc3,0x00,0x20]
+         bsolr-
+# CHECK: bunctr- 2                       # encoding: [0x4d,0xcb,0x04,0x20]
+         bsoctr- 2
+# CHECK: bunctr- 0                       # encoding: [0x4d,0xc3,0x04,0x20]
+         bsoctr-
+# CHECK: bunl- 2, target                 # encoding: [0x41,0xcb,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bsol- 2, target
+# CHECK: bunl- 0, target                 # encoding: [0x41,0xc3,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bsol- target
+# CHECK: bunla- 2, target                # encoding: [0x41,0xcb,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bsola- 2, target
+# CHECK: bunla- 0, target                # encoding: [0x41,0xc3,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bsola- target
+# CHECK: bunlrl- 2                       # encoding: [0x4d,0xcb,0x00,0x21]
+         bsolrl- 2
+# CHECK: bunlrl- 0                       # encoding: [0x4d,0xc3,0x00,0x21]
+         bsolrl-
+# CHECK: bunctrl- 2                      # encoding: [0x4d,0xcb,0x04,0x21]
+         bsoctrl- 2
+# CHECK: bunctrl- 0                      # encoding: [0x4d,0xc3,0x04,0x21]
+         bsoctrl-
+
 # CHECK: bnu 2, target                   # encoding: [0x40,0x8b,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bns 2, target
 # CHECK: bnu 0, target                   # encoding: [0x40,0x83,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bns target
-# FIXME: bnsa 2, target
-# FIXME: bnsa target
+# CHECK: bnua 2, target                  # encoding: [0x40,0x8b,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnsa 2, target
+# CHECK: bnua 0, target                  # encoding: [0x40,0x83,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnsa target
 # CHECK: bnulr 2                         # encoding: [0x4c,0x8b,0x00,0x20]
          bnslr 2
 # CHECK: bnulr 0                         # encoding: [0x4c,0x83,0x00,0x20]
@@ -376,25 +1535,121 @@
          bnsctr 2
 # CHECK: bnuctr 0                        # encoding: [0x4c,0x83,0x04,0x20]
          bnsctr
-# FIXME: bnsl 2, target
-# FIXME: bnsl target
-# FIXME: bnsla 2, target
-# FIXME: bnsla target
-# FIXME: bnslrl 2
-# FIXME: bnslrl
+# CHECK: bnul 2, target                  # encoding: [0x40,0x8b,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnsl 2, target
+# CHECK: bnul 0, target                  # encoding: [0x40,0x83,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnsl target
+# CHECK: bnula 2, target                 # encoding: [0x40,0x8b,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnsla 2, target
+# CHECK: bnula 0, target                 # encoding: [0x40,0x83,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnsla target
+# CHECK: bnulrl 2                        # encoding: [0x4c,0x8b,0x00,0x21]
+         bnslrl 2
+# CHECK: bnulrl 0                        # encoding: [0x4c,0x83,0x00,0x21]
+         bnslrl
 # CHECK: bnuctrl 2                       # encoding: [0x4c,0x8b,0x04,0x21]
          bnsctrl 2
 # CHECK: bnuctrl 0                       # encoding: [0x4c,0x83,0x04,0x21]
          bnsctrl
 
+# CHECK: bnu+ 2, target                  # encoding: [0x40,0xeb,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bns+ 2, target
+# CHECK: bnu+ 0, target                  # encoding: [0x40,0xe3,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bns+ target
+# CHECK: bnua+ 2, target                 # encoding: [0x40,0xeb,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnsa+ 2, target
+# CHECK: bnua+ 0, target                 # encoding: [0x40,0xe3,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnsa+ target
+# CHECK: bnulr+ 2                        # encoding: [0x4c,0xeb,0x00,0x20]
+         bnslr+ 2
+# CHECK: bnulr+ 0                        # encoding: [0x4c,0xe3,0x00,0x20]
+         bnslr+
+# CHECK: bnuctr+ 2                       # encoding: [0x4c,0xeb,0x04,0x20]
+         bnsctr+ 2
+# CHECK: bnuctr+ 0                       # encoding: [0x4c,0xe3,0x04,0x20]
+         bnsctr+
+# CHECK: bnul+ 2, target                 # encoding: [0x40,0xeb,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnsl+ 2, target
+# CHECK: bnul+ 0, target                 # encoding: [0x40,0xe3,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnsl+ target
+# CHECK: bnula+ 2, target                # encoding: [0x40,0xeb,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnsla+ 2, target
+# CHECK: bnula+ 0, target                # encoding: [0x40,0xe3,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnsla+ target
+# CHECK: bnulrl+ 2                       # encoding: [0x4c,0xeb,0x00,0x21]
+         bnslrl+ 2
+# CHECK: bnulrl+ 0                       # encoding: [0x4c,0xe3,0x00,0x21]
+         bnslrl+
+# CHECK: bnuctrl+ 2                      # encoding: [0x4c,0xeb,0x04,0x21]
+         bnsctrl+ 2
+# CHECK: bnuctrl+ 0                      # encoding: [0x4c,0xe3,0x04,0x21]
+         bnsctrl+
+
+# CHECK: bnu- 2, target                  # encoding: [0x40,0xcb,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bns- 2, target
+# CHECK: bnu- 0, target                  # encoding: [0x40,0xc3,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bns- target
+# CHECK: bnua- 2, target                 # encoding: [0x40,0xcb,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnsa- 2, target
+# CHECK: bnua- 0, target                 # encoding: [0x40,0xc3,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnsa- target
+# CHECK: bnulr- 2                        # encoding: [0x4c,0xcb,0x00,0x20]
+         bnslr- 2
+# CHECK: bnulr- 0                        # encoding: [0x4c,0xc3,0x00,0x20]
+         bnslr-
+# CHECK: bnuctr- 2                       # encoding: [0x4c,0xcb,0x04,0x20]
+         bnsctr- 2
+# CHECK: bnuctr- 0                       # encoding: [0x4c,0xc3,0x04,0x20]
+         bnsctr-
+# CHECK: bnul- 2, target                 # encoding: [0x40,0xcb,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnsl- 2, target
+# CHECK: bnul- 0, target                 # encoding: [0x40,0xc3,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnsl- target
+# CHECK: bnula- 2, target                # encoding: [0x40,0xcb,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnsla- 2, target
+# CHECK: bnula- 0, target                # encoding: [0x40,0xc3,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnsla- target
+# CHECK: bnulrl- 2                       # encoding: [0x4c,0xcb,0x00,0x21]
+         bnslrl- 2
+# CHECK: bnulrl- 0                       # encoding: [0x4c,0xc3,0x00,0x21]
+         bnslrl-
+# CHECK: bnuctrl- 2                      # encoding: [0x4c,0xcb,0x04,0x21]
+         bnsctrl- 2
+# CHECK: bnuctrl- 0                      # encoding: [0x4c,0xc3,0x04,0x21]
+         bnsctrl-
+
 # CHECK: bun 2, target                   # encoding: [0x41,0x8b,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bun 2, target
 # CHECK: bun 0, target                   # encoding: [0x41,0x83,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bun target
-# FIXME: buna 2, target
-# FIXME: buna target
+# CHECK: buna 2, target                  # encoding: [0x41,0x8b,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         buna 2, target
+# CHECK: buna 0, target                  # encoding: [0x41,0x83,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         buna target
 # CHECK: bunlr 2                         # encoding: [0x4d,0x8b,0x00,0x20]
          bunlr 2
 # CHECK: bunlr 0                         # encoding: [0x4d,0x83,0x00,0x20]
@@ -403,25 +1658,121 @@
          bunctr 2
 # CHECK: bunctr 0                        # encoding: [0x4d,0x83,0x04,0x20]
          bunctr
-# FIXME: bunl 2, target
-# FIXME: bunl target
-# FIXME: bunla 2, target
-# FIXME: bunla target
-# FIXME: bunlrl 2
-# FIXME: bunlrl
+# CHECK: bunl 2, target                  # encoding: [0x41,0x8b,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bunl 2, target
+# CHECK: bunl 0, target                  # encoding: [0x41,0x83,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bunl target
+# CHECK: bunla 2, target                 # encoding: [0x41,0x8b,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bunla 2, target
+# CHECK: bunla 0, target                 # encoding: [0x41,0x83,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bunla target
+# CHECK: bunlrl 2                        # encoding: [0x4d,0x8b,0x00,0x21]
+         bunlrl 2
+# CHECK: bunlrl 0                        # encoding: [0x4d,0x83,0x00,0x21]
+         bunlrl
 # CHECK: bunctrl 2                       # encoding: [0x4d,0x8b,0x04,0x21]
          bunctrl 2
 # CHECK: bunctrl 0                       # encoding: [0x4d,0x83,0x04,0x21]
          bunctrl
 
+# CHECK: bun+ 2, target                  # encoding: [0x41,0xeb,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bun+ 2, target
+# CHECK: bun+ 0, target                  # encoding: [0x41,0xe3,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bun+ target
+# CHECK: buna+ 2, target                 # encoding: [0x41,0xeb,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         buna+ 2, target
+# CHECK: buna+ 0, target                 # encoding: [0x41,0xe3,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         buna+ target
+# CHECK: bunlr+ 2                        # encoding: [0x4d,0xeb,0x00,0x20]
+         bunlr+ 2
+# CHECK: bunlr+ 0                        # encoding: [0x4d,0xe3,0x00,0x20]
+         bunlr+
+# CHECK: bunctr+ 2                       # encoding: [0x4d,0xeb,0x04,0x20]
+         bunctr+ 2
+# CHECK: bunctr+ 0                       # encoding: [0x4d,0xe3,0x04,0x20]
+         bunctr+
+# CHECK: bunl+ 2, target                 # encoding: [0x41,0xeb,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bunl+ 2, target
+# CHECK: bunl+ 0, target                 # encoding: [0x41,0xe3,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bunl+ target
+# CHECK: bunla+ 2, target                # encoding: [0x41,0xeb,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bunla+ 2, target
+# CHECK: bunla+ 0, target                # encoding: [0x41,0xe3,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bunla+ target
+# CHECK: bunlrl+ 2                       # encoding: [0x4d,0xeb,0x00,0x21]
+         bunlrl+ 2
+# CHECK: bunlrl+ 0                       # encoding: [0x4d,0xe3,0x00,0x21]
+         bunlrl+
+# CHECK: bunctrl+ 2                      # encoding: [0x4d,0xeb,0x04,0x21]
+         bunctrl+ 2
+# CHECK: bunctrl+ 0                      # encoding: [0x4d,0xe3,0x04,0x21]
+         bunctrl+
+
+# CHECK: bun- 2, target                  # encoding: [0x41,0xcb,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bun- 2, target
+# CHECK: bun- 0, target                  # encoding: [0x41,0xc3,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bun- target
+# CHECK: buna- 2, target                 # encoding: [0x41,0xcb,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         buna- 2, target
+# CHECK: buna- 0, target                 # encoding: [0x41,0xc3,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         buna- target
+# CHECK: bunlr- 2                        # encoding: [0x4d,0xcb,0x00,0x20]
+         bunlr- 2
+# CHECK: bunlr- 0                        # encoding: [0x4d,0xc3,0x00,0x20]
+         bunlr-
+# CHECK: bunctr- 2                       # encoding: [0x4d,0xcb,0x04,0x20]
+         bunctr- 2
+# CHECK: bunctr- 0                       # encoding: [0x4d,0xc3,0x04,0x20]
+         bunctr-
+# CHECK: bunl- 2, target                 # encoding: [0x41,0xcb,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bunl- 2, target
+# CHECK: bunl- 0, target                 # encoding: [0x41,0xc3,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bunl- target
+# CHECK: bunla- 2, target                # encoding: [0x41,0xcb,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bunla- 2, target
+# CHECK: bunla- 0, target                # encoding: [0x41,0xc3,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bunla- target
+# CHECK: bunlrl- 2                       # encoding: [0x4d,0xcb,0x00,0x21]
+         bunlrl- 2
+# CHECK: bunlrl- 0                       # encoding: [0x4d,0xc3,0x00,0x21]
+         bunlrl-
+# CHECK: bunctrl- 2                      # encoding: [0x4d,0xcb,0x04,0x21]
+         bunctrl- 2
+# CHECK: bunctrl- 0                      # encoding: [0x4d,0xc3,0x04,0x21]
+         bunctrl-
+
 # CHECK: bnu 2, target                   # encoding: [0x40,0x8b,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bnu 2, target
 # CHECK: bnu 0, target                   # encoding: [0x40,0x83,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
          bnu target
-# FIXME: bnua 2, target
-# FIXME: bnua target
+# CHECK: bnua 2, target                  # encoding: [0x40,0x8b,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnua 2, target
+# CHECK: bnua 0, target                  # encoding: [0x40,0x83,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnua target
 # CHECK: bnulr 2                         # encoding: [0x4c,0x8b,0x00,0x20]
          bnulr 2
 # CHECK: bnulr 0                         # encoding: [0x4c,0x83,0x00,0x20]
@@ -430,78 +1781,418 @@
          bnuctr 2
 # CHECK: bnuctr 0                        # encoding: [0x4c,0x83,0x04,0x20]
          bnuctr
-# FIXME: bnul 2, target
-# FIXME: bnul target
-# FIXME: bnula 2, target
-# FIXME: bnula target
-# FIXME: bnulrl 2
-# FIXME: bnulrl
+# CHECK: bnul 2, target                  # encoding: [0x40,0x8b,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnul 2, target
+# CHECK: bnul 0, target                  # encoding: [0x40,0x83,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnul target
+# CHECK: bnula 2, target                 # encoding: [0x40,0x8b,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnula 2, target
+# CHECK: bnula 0, target                 # encoding: [0x40,0x83,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnula target
+# CHECK: bnulrl 2                        # encoding: [0x4c,0x8b,0x00,0x21]
+         bnulrl 2
+# CHECK: bnulrl 0                        # encoding: [0x4c,0x83,0x00,0x21]
+         bnulrl
 # CHECK: bnuctrl 2                       # encoding: [0x4c,0x8b,0x04,0x21]
          bnuctrl 2
 # CHECK: bnuctrl 0                       # encoding: [0x4c,0x83,0x04,0x21]
          bnuctrl
 
-# FIXME: Condition register logical mnemonics
+# CHECK: bnu+ 2, target                  # encoding: [0x40,0xeb,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnu+ 2, target
+# CHECK: bnu+ 0, target                  # encoding: [0x40,0xe3,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnu+ target
+# CHECK: bnua+ 2, target                 # encoding: [0x40,0xeb,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnua+ 2, target
+# CHECK: bnua+ 0, target                 # encoding: [0x40,0xe3,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnua+ target
+# CHECK: bnulr+ 2                        # encoding: [0x4c,0xeb,0x00,0x20]
+         bnulr+ 2
+# CHECK: bnulr+ 0                        # encoding: [0x4c,0xe3,0x00,0x20]
+         bnulr+
+# CHECK: bnuctr+ 2                       # encoding: [0x4c,0xeb,0x04,0x20]
+         bnuctr+ 2
+# CHECK: bnuctr+ 0                       # encoding: [0x4c,0xe3,0x04,0x20]
+         bnuctr+
+# CHECK: bnul+ 2, target                 # encoding: [0x40,0xeb,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnul+ 2, target
+# CHECK: bnul+ 0, target                 # encoding: [0x40,0xe3,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnul+ target
+# CHECK: bnula+ 2, target                # encoding: [0x40,0xeb,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnula+ 2, target
+# CHECK: bnula+ 0, target                # encoding: [0x40,0xe3,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnula+ target
+# CHECK: bnulrl+ 2                       # encoding: [0x4c,0xeb,0x00,0x21]
+         bnulrl+ 2
+# CHECK: bnulrl+ 0                       # encoding: [0x4c,0xe3,0x00,0x21]
+         bnulrl+
+# CHECK: bnuctrl+ 2                      # encoding: [0x4c,0xeb,0x04,0x21]
+         bnuctrl+ 2
+# CHECK: bnuctrl+ 0                      # encoding: [0x4c,0xe3,0x04,0x21]
+         bnuctrl+
+
+# CHECK: bnu- 2, target                  # encoding: [0x40,0xcb,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnu- 2, target
+# CHECK: bnu- 0, target                  # encoding: [0x40,0xc3,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnu- target
+# CHECK: bnua- 2, target                 # encoding: [0x40,0xcb,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnua- 2, target
+# CHECK: bnua- 0, target                 # encoding: [0x40,0xc3,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnua- target
+# CHECK: bnulr- 2                        # encoding: [0x4c,0xcb,0x00,0x20]
+         bnulr- 2
+# CHECK: bnulr- 0                        # encoding: [0x4c,0xc3,0x00,0x20]
+         bnulr-
+# CHECK: bnuctr- 2                       # encoding: [0x4c,0xcb,0x04,0x20]
+         bnuctr- 2
+# CHECK: bnuctr- 0                       # encoding: [0x4c,0xc3,0x04,0x20]
+         bnuctr-
+# CHECK: bnul- 2, target                 # encoding: [0x40,0xcb,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnul- 2, target
+# CHECK: bnul- 0, target                 # encoding: [0x40,0xc3,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bnul- target
+# CHECK: bnula- 2, target                # encoding: [0x40,0xcb,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnula- 2, target
+# CHECK: bnula- 0, target                # encoding: [0x40,0xc3,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bnula- target
+# CHECK: bnulrl- 2                       # encoding: [0x4c,0xcb,0x00,0x21]
+         bnulrl- 2
+# CHECK: bnulrl- 0                       # encoding: [0x4c,0xc3,0x00,0x21]
+         bnulrl-
+# CHECK: bnuctrl- 2                      # encoding: [0x4c,0xcb,0x04,0x21]
+         bnuctrl- 2
+# CHECK: bnuctrl- 0                      # encoding: [0x4c,0xc3,0x04,0x21]
+         bnuctrl-
+
+# Condition register logical mnemonics
+
+# CHECK: creqv 2, 2, 2                   # encoding: [0x4c,0x42,0x12,0x42]
+         crset 2
+# CHECK: crxor 2, 2, 2                   # encoding: [0x4c,0x42,0x11,0x82]
+         crclr 2
+# CHECK: cror 2, 3, 3                    # encoding: [0x4c,0x43,0x1b,0x82]
+         crmove 2, 3
+# CHECK: crnor 2, 3, 3                   # encoding: [0x4c,0x43,0x18,0x42]
+         crnot 2, 3
 
-# FIXME: Subtract mnemonics
+# Subtract mnemonics
+
+# CHECK: addi 2, 3, -128                 # encoding: [0x38,0x43,0xff,0x80]
+         subi 2, 3, 128
+# CHECK: addis 2, 3, -128                # encoding: [0x3c,0x43,0xff,0x80]
+         subis 2, 3, 128
+# CHECK: addic 2, 3, -128                # encoding: [0x30,0x43,0xff,0x80]
+         subic 2, 3, 128
+# CHECK: addic. 2, 3, -128               # encoding: [0x34,0x43,0xff,0x80]
+         subic. 2, 3, 128
+
+# CHECK: subf 2, 4, 3                    # encoding: [0x7c,0x44,0x18,0x50]
+         sub 2, 3, 4
+# CHECK: subf. 2, 4, 3                   # encoding: [0x7c,0x44,0x18,0x51]
+         sub. 2, 3, 4
+# CHECK: subfc 2, 4, 3                   # encoding: [0x7c,0x44,0x18,0x10]
+         subc 2, 3, 4
+# CHECK: subfc. 2, 4, 3                  # encoding: [0x7c,0x44,0x18,0x11]
+         subc. 2, 3, 4
 
 # Compare mnemonics
 
 # CHECK: cmpdi 2, 3, 128                 # encoding: [0x2d,0x23,0x00,0x80]
          cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128                 # encoding: [0x2c,0x23,0x00,0x80]
+         cmpdi 3, 128
 # CHECK: cmpd 2, 3, 4                    # encoding: [0x7d,0x23,0x20,0x00]
          cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4                    # encoding: [0x7c,0x23,0x20,0x00]
+         cmpd 3, 4
 # CHECK: cmpldi 2, 3, 128                # encoding: [0x29,0x23,0x00,0x80]
          cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128                # encoding: [0x28,0x23,0x00,0x80]
+         cmpldi 3, 128
 # CHECK: cmpld 2, 3, 4                   # encoding: [0x7d,0x23,0x20,0x40]
          cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4                   # encoding: [0x7c,0x23,0x20,0x40]
+         cmpld 3, 4
 
 # CHECK: cmpwi 2, 3, 128                 # encoding: [0x2d,0x03,0x00,0x80]
          cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128                 # encoding: [0x2c,0x03,0x00,0x80]
+         cmpwi 3, 128
 # CHECK: cmpw 2, 3, 4                    # encoding: [0x7d,0x03,0x20,0x00]
          cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4                    # encoding: [0x7c,0x03,0x20,0x00]
+         cmpw 3, 4
 # CHECK: cmplwi 2, 3, 128                # encoding: [0x29,0x03,0x00,0x80]
          cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128                # encoding: [0x28,0x03,0x00,0x80]
+         cmplwi 3, 128
 # CHECK: cmplw 2, 3, 4                   # encoding: [0x7d,0x03,0x20,0x40]
          cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4                   # encoding: [0x7c,0x03,0x20,0x40]
+         cmplw 3, 4
+
+# Trap mnemonics
+
+# CHECK: twi 16, 3, 4                    # encoding: [0x0e,0x03,0x00,0x04]
+         twlti 3, 4
+# CHECK: tw 16, 3, 4                     # encoding: [0x7e,0x03,0x20,0x08]
+         twlt 3, 4
+# CHECK: tdi 16, 3, 4                    # encoding: [0x0a,0x03,0x00,0x04]
+         tdlti 3, 4
+# CHECK: td 16, 3, 4                     # encoding: [0x7e,0x03,0x20,0x88]
+         tdlt 3, 4
+
+# CHECK: twi 20, 3, 4                    # encoding: [0x0e,0x83,0x00,0x04]
+         twlei 3, 4
+# CHECK: tw 20, 3, 4                     # encoding: [0x7e,0x83,0x20,0x08]
+         twle 3, 4
+# CHECK: tdi 20, 3, 4                    # encoding: [0x0a,0x83,0x00,0x04]
+         tdlei 3, 4
+# CHECK: td 20, 3, 4                     # encoding: [0x7e,0x83,0x20,0x88]
+         tdle 3, 4
+
+# CHECK: twi 4, 3, 4                     # encoding: [0x0c,0x83,0x00,0x04]
+         tweqi 3, 4
+# CHECK: tw 4, 3, 4                      # encoding: [0x7c,0x83,0x20,0x08]
+         tweq 3, 4
+# CHECK: tdi 4, 3, 4                     # encoding: [0x08,0x83,0x00,0x04]
+         tdeqi 3, 4
+# CHECK: td 4, 3, 4                      # encoding: [0x7c,0x83,0x20,0x88]
+         tdeq 3, 4
 
-# FIXME: Trap mnemonics
+# CHECK: twi 12, 3, 4                    # encoding: [0x0d,0x83,0x00,0x04]
+         twgei 3, 4
+# CHECK: tw 12, 3, 4                     # encoding: [0x7d,0x83,0x20,0x08]
+         twge 3, 4
+# CHECK: tdi 12, 3, 4                    # encoding: [0x09,0x83,0x00,0x04]
+         tdgei 3, 4
+# CHECK: td 12, 3, 4                     # encoding: [0x7d,0x83,0x20,0x88]
+         tdge 3, 4
+
+# CHECK: twi 8, 3, 4                     # encoding: [0x0d,0x03,0x00,0x04]
+         twgti 3, 4
+# CHECK: tw 8, 3, 4                      # encoding: [0x7d,0x03,0x20,0x08]
+         twgt 3, 4
+# CHECK: tdi 8, 3, 4                     # encoding: [0x09,0x03,0x00,0x04]
+         tdgti 3, 4
+# CHECK: td 8, 3, 4                      # encoding: [0x7d,0x03,0x20,0x88]
+         tdgt 3, 4
+
+# CHECK: twi 12, 3, 4                    # encoding: [0x0d,0x83,0x00,0x04]
+         twnli 3, 4
+# CHECK: tw 12, 3, 4                     # encoding: [0x7d,0x83,0x20,0x08]
+         twnl 3, 4
+# CHECK: tdi 12, 3, 4                    # encoding: [0x09,0x83,0x00,0x04]
+         tdnli 3, 4
+# CHECK: td 12, 3, 4                     # encoding: [0x7d,0x83,0x20,0x88]
+         tdnl 3, 4
+
+# CHECK: twi 24, 3, 4                    # encoding: [0x0f,0x03,0x00,0x04]
+         twnei 3, 4
+# CHECK: tw 24, 3, 4                     # encoding: [0x7f,0x03,0x20,0x08]
+         twne 3, 4
+# CHECK: tdi 24, 3, 4                    # encoding: [0x0b,0x03,0x00,0x04]
+         tdnei 3, 4
+# CHECK: td 24, 3, 4                     # encoding: [0x7f,0x03,0x20,0x88]
+         tdne 3, 4
+
+# CHECK: twi 20, 3, 4                    # encoding: [0x0e,0x83,0x00,0x04]
+         twngi 3, 4
+# CHECK: tw 20, 3, 4                     # encoding: [0x7e,0x83,0x20,0x08]
+         twng 3, 4
+# CHECK: tdi 20, 3, 4                    # encoding: [0x0a,0x83,0x00,0x04]
+         tdngi 3, 4
+# CHECK: td 20, 3, 4                     # encoding: [0x7e,0x83,0x20,0x88]
+         tdng 3, 4
+
+# CHECK: twi 2, 3, 4                     # encoding: [0x0c,0x43,0x00,0x04]
+         twllti 3, 4
+# CHECK: tw 2, 3, 4                      # encoding: [0x7c,0x43,0x20,0x08]
+         twllt 3, 4
+# CHECK: tdi 2, 3, 4                     # encoding: [0x08,0x43,0x00,0x04]
+         tdllti 3, 4
+# CHECK: td 2, 3, 4                      # encoding: [0x7c,0x43,0x20,0x88]
+         tdllt 3, 4
+
+# CHECK: twi 6, 3, 4                     # encoding: [0x0c,0xc3,0x00,0x04]
+         twllei 3, 4
+# CHECK: tw 6, 3, 4                      # encoding: [0x7c,0xc3,0x20,0x08]
+         twlle 3, 4
+# CHECK: tdi 6, 3, 4                     # encoding: [0x08,0xc3,0x00,0x04]
+         tdllei 3, 4
+# CHECK: td 6, 3, 4                      # encoding: [0x7c,0xc3,0x20,0x88]
+         tdlle 3, 4
+
+# CHECK: twi 5, 3, 4                     # encoding: [0x0c,0xa3,0x00,0x04]
+         twlgei 3, 4
+# CHECK: tw 5, 3, 4                      # encoding: [0x7c,0xa3,0x20,0x08]
+         twlge 3, 4
+# CHECK: tdi 5, 3, 4                     # encoding: [0x08,0xa3,0x00,0x04]
+         tdlgei 3, 4
+# CHECK: td 5, 3, 4                      # encoding: [0x7c,0xa3,0x20,0x88]
+         tdlge 3, 4
+
+# CHECK: twi 1, 3, 4                     # encoding: [0x0c,0x23,0x00,0x04]
+         twlgti 3, 4
+# CHECK: tw 1, 3, 4                      # encoding: [0x7c,0x23,0x20,0x08]
+         twlgt 3, 4
+# CHECK: tdi 1, 3, 4                     # encoding: [0x08,0x23,0x00,0x04]
+         tdlgti 3, 4
+# CHECK: td 1, 3, 4                      # encoding: [0x7c,0x23,0x20,0x88]
+         tdlgt 3, 4
+
+# CHECK: twi 5, 3, 4                     # encoding: [0x0c,0xa3,0x00,0x04]
+         twlnli 3, 4
+# CHECK: tw 5, 3, 4                      # encoding: [0x7c,0xa3,0x20,0x08]
+         twlnl 3, 4
+# CHECK: tdi 5, 3, 4                     # encoding: [0x08,0xa3,0x00,0x04]
+         tdlnli 3, 4
+# CHECK: td 5, 3, 4                      # encoding: [0x7c,0xa3,0x20,0x88]
+         tdlnl 3, 4
+
+# CHECK: twi 6, 3, 4                     # encoding: [0x0c,0xc3,0x00,0x04]
+         twlngi 3, 4
+# CHECK: tw 6, 3, 4                      # encoding: [0x7c,0xc3,0x20,0x08]
+         twlng 3, 4
+# CHECK: tdi 6, 3, 4                     # encoding: [0x08,0xc3,0x00,0x04]
+         tdlngi 3, 4
+# CHECK: td 6, 3, 4                      # encoding: [0x7c,0xc3,0x20,0x88]
+         tdlng 3, 4
+
+# CHECK: twi 31, 3, 4                    # encoding: [0x0f,0xe3,0x00,0x04]
+         twui 3, 4
+# CHECK: tw 31, 3, 4                     # encoding: [0x7f,0xe3,0x20,0x08]
+         twu 3, 4
+# CHECK: tdi 31, 3, 4                    # encoding: [0x0b,0xe3,0x00,0x04]
+         tdui 3, 4
+# CHECK: td 31, 3, 4                     # encoding: [0x7f,0xe3,0x20,0x88]
+         tdu 3, 4
+
+# CHECK: trap                            # encoding: [0x7f,0xe0,0x00,0x08]
+         trap
 
 # Rotate and shift mnemonics
 
-# FIXME: extldi 2, 3, 4, 5
-# FIXME: extrdi 2, 3, 4, 5
-# FIXME: insrdi 2, 3, 4, 5
-# FIXME: rotldi 2, 3, 4
-# FIXME: rotrdi 2, 3, 4
-# FIXME: rotld 2, 3, 4
+# CHECK: rldicr 2, 3, 5, 3               # encoding: [0x78,0x62,0x28,0xc4]
+         extldi 2, 3, 4, 5
+# CHECK: rldicr. 2, 3, 5, 3              # encoding: [0x78,0x62,0x28,0xc5]
+         extldi. 2, 3, 4, 5
+# CHECK: rldicl 2, 3, 9, 60              # encoding: [0x78,0x62,0x4f,0x20]
+         extrdi 2, 3, 4, 5
+# CHECK: rldicl. 2, 3, 9, 60             # encoding: [0x78,0x62,0x4f,0x21]
+         extrdi. 2, 3, 4, 5
+# CHECK: rldimi 2, 3, 55, 5              # encoding: [0x78,0x62,0xb9,0x4e]
+         insrdi 2, 3, 4, 5
+# CHECK: rldimi. 2, 3, 55, 5             # encoding: [0x78,0x62,0xb9,0x4f]
+         insrdi. 2, 3, 4, 5
+# CHECK: rldicl 2, 3, 4, 0               # encoding: [0x78,0x62,0x20,0x00]
+         rotldi 2, 3, 4
+# CHECK: rldicl. 2, 3, 4, 0              # encoding: [0x78,0x62,0x20,0x01]
+         rotldi. 2, 3, 4
+# CHECK: rldicl 2, 3, 60, 0              # encoding: [0x78,0x62,0xe0,0x02]
+         rotrdi 2, 3, 4
+# CHECK: rldicl. 2, 3, 60, 0             # encoding: [0x78,0x62,0xe0,0x03]
+         rotrdi. 2, 3, 4
+# CHECK: rldcl 2, 3, 4, 0                # encoding: [0x78,0x62,0x20,0x10]
+         rotld 2, 3, 4
+# CHECK: rldcl. 2, 3, 4, 0               # encoding: [0x78,0x62,0x20,0x11]
+         rotld. 2, 3, 4
 # CHECK: sldi 2, 3, 4                    # encoding: [0x78,0x62,0x26,0xe4]
          sldi 2, 3, 4
+# CHECK: rldicr. 2, 3, 4, 59             # encoding: [0x78,0x62,0x26,0xe5]
+         sldi. 2, 3, 4
 # CHECK: rldicl 2, 3, 60, 4              # encoding: [0x78,0x62,0xe1,0x02]
          srdi 2, 3, 4
-# FIXME: clrldi 2, 3, 4
-# FIXME: clrrdi 2, 3, 4
-# FIXME: clrlsldi 2, 3, 4, 5
-
-# FIXME: extlwi 2, 3, 4, 5
-# FIXME: extrwi 2, 3, 4, 5
-# FIXME: inslwi 2, 3, 4, 5
-# FIXME: insrwi 2, 3, 4, 5
-# FIXME: rotlwi 2, 3, 4
-# FIXME: rotrwi 2, 3, 4
-# FIXME: rotlw 2, 3, 4
+# CHECK: rldicl. 2, 3, 60, 4             # encoding: [0x78,0x62,0xe1,0x03]
+         srdi. 2, 3, 4
+# CHECK: rldicl 2, 3, 0, 4               # encoding: [0x78,0x62,0x01,0x00]
+         clrldi 2, 3, 4
+# CHECK: rldicl. 2, 3, 0, 4              # encoding: [0x78,0x62,0x01,0x01]
+         clrldi. 2, 3, 4
+# CHECK: rldicr 2, 3, 0, 59              # encoding: [0x78,0x62,0x06,0xe4]
+         clrrdi 2, 3, 4
+# CHECK: rldicr. 2, 3, 0, 59             # encoding: [0x78,0x62,0x06,0xe5]
+         clrrdi. 2, 3, 4
+# CHECK: rldic 2, 3, 4, 1                # encoding: [0x78,0x62,0x20,0x48]
+         clrlsldi 2, 3, 5, 4
+# CHECK: rldic. 2, 3, 4, 1               # encoding: [0x78,0x62,0x20,0x49]
+         clrlsldi. 2, 3, 5, 4
+
+# CHECK: rlwinm 2, 3, 5, 0, 3            # encoding: [0x54,0x62,0x28,0x06]
+         extlwi 2, 3, 4, 5
+# CHECK: rlwinm. 2, 3, 5, 0, 3           # encoding: [0x54,0x62,0x28,0x07]
+         extlwi. 2, 3, 4, 5
+# CHECK: rlwinm 2, 3, 9, 28, 31          # encoding: [0x54,0x62,0x4f,0x3e]
+         extrwi 2, 3, 4, 5
+# CHECK: rlwinm. 2, 3, 9, 28, 31         # encoding: [0x54,0x62,0x4f,0x3f]
+         extrwi. 2, 3, 4, 5
+# CHECK: rlwimi 2, 3, 27, 5, 8           # encoding: [0x50,0x62,0xd9,0x50]
+         inslwi 2, 3, 4, 5
+# CHECK: rlwimi. 2, 3, 27, 5, 8          # encoding: [0x50,0x62,0xd9,0x51]
+         inslwi. 2, 3, 4, 5
+# CHECK: rlwimi 2, 3, 23, 5, 8           # encoding: [0x50,0x62,0xb9,0x50]
+         insrwi 2, 3, 4, 5
+# CHECK: rlwimi. 2, 3, 23, 5, 8          # encoding: [0x50,0x62,0xb9,0x51]
+         insrwi. 2, 3, 4, 5
+# CHECK: rlwinm 2, 3, 4, 0, 31           # encoding: [0x54,0x62,0x20,0x3e]
+         rotlwi 2, 3, 4
+# CHECK: rlwinm. 2, 3, 4, 0, 31          # encoding: [0x54,0x62,0x20,0x3f]
+         rotlwi. 2, 3, 4
+# CHECK: rlwinm 2, 3, 28, 0, 31          # encoding: [0x54,0x62,0xe0,0x3e]
+         rotrwi 2, 3, 4
+# CHECK: rlwinm. 2, 3, 28, 0, 31         # encoding: [0x54,0x62,0xe0,0x3f]
+         rotrwi. 2, 3, 4
+# CHECK: rlwnm 2, 3, 4, 0, 31            # encoding: [0x5c,0x62,0x20,0x3e]
+         rotlw 2, 3, 4
+# CHECK: rlwnm. 2, 3, 4, 0, 31           # encoding: [0x5c,0x62,0x20,0x3f]
+         rotlw. 2, 3, 4
 # CHECK: slwi 2, 3, 4                    # encoding: [0x54,0x62,0x20,0x36]
          slwi 2, 3, 4
+# CHECK: rlwinm. 2, 3, 4, 0, 27          # encoding: [0x54,0x62,0x20,0x37]
+         slwi. 2, 3, 4
 # CHECK: srwi 2, 3, 4                    # encoding: [0x54,0x62,0xe1,0x3e]
          srwi 2, 3, 4
-# FIXME: clrlwi 2, 3, 4
-# FIXME: clrrwi 2, 3, 4
-# FIXME: clrlslwi 2, 3, 4, 5
+# CHECK: rlwinm. 2, 3, 28, 4, 31         # encoding: [0x54,0x62,0xe1,0x3f]
+         srwi. 2, 3, 4
+# CHECK: rlwinm 2, 3, 0, 4, 31           # encoding: [0x54,0x62,0x01,0x3e]
+         clrlwi 2, 3, 4
+# CHECK: rlwinm. 2, 3, 0, 4, 31          # encoding: [0x54,0x62,0x01,0x3f]
+         clrlwi. 2, 3, 4
+# CHECK: rlwinm 2, 3, 0, 0, 27           # encoding: [0x54,0x62,0x00,0x36]
+         clrrwi 2, 3, 4
+# CHECK: rlwinm. 2, 3, 0, 0, 27          # encoding: [0x54,0x62,0x00,0x37]
+         clrrwi. 2, 3, 4
+# CHECK: rlwinm 2, 3, 4, 1, 27           # encoding: [0x54,0x62,0x20,0x76]
+         clrlslwi 2, 3, 5, 4
+# CHECK: rlwinm. 2, 3, 4, 1, 27          # encoding: [0x54,0x62,0x20,0x77]
+         clrlslwi. 2, 3, 5, 4
 
 # Move to/from special purpose register mnemonics
 
-# FIXME: mtxer 2
-# FIXME: mfxer 2
+# CHECK: mtspr 1, 2                      # encoding: [0x7c,0x41,0x03,0xa6]
+         mtxer 2
+# CHECK: mfspr 2, 1                      # encoding: [0x7c,0x41,0x02,0xa6]
+         mfxer 2
 # CHECK: mtlr 2                          # encoding: [0x7c,0x48,0x03,0xa6]
          mtlr 2
 # CHECK: mflr 2                          # encoding: [0x7c,0x48,0x02,0xa6]
@@ -515,13 +2206,22 @@
 
 # CHECK: nop                             # encoding: [0x60,0x00,0x00,0x00]
          nop
-# FIXME: xnop
+# CHECK: xori 0, 0, 0                    # encoding: [0x68,0x00,0x00,0x00]
+         xnop
 # CHECK: li 2, 128                       # encoding: [0x38,0x40,0x00,0x80]
          li 2, 128
 # CHECK: lis 2, 128                      # encoding: [0x3c,0x40,0x00,0x80]
          lis 2, 128
-# FIXME: la 2, 128(4)
+# CHECK: la 2, 128(4)
+         la 2, 128(4)
 # CHECK: mr 2, 3                         # encoding: [0x7c,0x62,0x1b,0x78]
          mr 2, 3
-# FIXME: not 2, 3
+# CHECK: or. 2, 3, 3                     # encoding: [0x7c,0x62,0x1b,0x79]
+         mr. 2, 3
+# CHECK: nor 2, 3, 3                     # encoding: [0x7c,0x62,0x18,0xf8]
+         not 2, 3
+# CHECK: nor. 2, 3, 3                    # encoding: [0x7c,0x62,0x18,0xf9]
+         not. 2, 3
+# CHECK: mtcrf 255, 2                    # encoding: [0x7c,0x4f,0xf1,0x20]
+         mtcr 2
 
diff --git a/test/MC/PowerPC/ppc64-encoding.s b/test/MC/PowerPC/ppc64-encoding.s
index d11ad4f..d82d86f 100644
--- a/test/MC/PowerPC/ppc64-encoding.s
+++ b/test/MC/PowerPC/ppc64-encoding.s
@@ -8,34 +8,64 @@
 # CHECK: b target                        # encoding: [0b010010AA,A,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_br24
          b target
-# FIXME: ba target
+# CHECK: ba target                       # encoding: [0b010010AA,A,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs
+         ba target
 # CHECK: bl target                       # encoding: [0b010010AA,A,A,0bAAAAAA01]
 # CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_br24
          bl target
-# FIXME: bla target
-
-# FIXME: bc 4, 10, target
-# FIXME: bca 4, 10, target
-# FIXME: bcl 4, 10, target
-# FIXME: bcla 4, 10, target
-
-# FIXME: bclr 4, 10, 3
-# FIXME: bclrl 4, 10, 3
-# FIXME: bcctr 4, 10, 3
-# FIXME: bcctrl 4, 10, 3
+# CHECK: bla target                      # encoding: [0b010010AA,A,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs
+         bla target
+
+# CHECK: bc 4, 10, target                # encoding: [0x40,0x8a,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bc 4, 10, target
+# CHECK: bca 4, 10, target               # encoding: [0x40,0x8a,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bca 4, 10, target
+# CHECK: bcl 4, 10, target               # encoding: [0x40,0x8a,A,0bAAAAAA01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+         bcl 4, 10, target
+# CHECK: bcla 4, 10, target              # encoding: [0x40,0x8a,A,0bAAAAAA11]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+         bcla 4, 10, target
+
+# CHECK: bclr 4, 10, 3                   # encoding: [0x4c,0x8a,0x18,0x20]
+         bclr 4, 10, 3
+# CHECK: bclr 4, 10, 0                   # encoding: [0x4c,0x8a,0x00,0x20]
+         bclr 4, 10
+# CHECK: bclrl 4, 10, 3                  # encoding: [0x4c,0x8a,0x18,0x21]
+         bclrl 4, 10, 3
+# CHECK: bclrl 4, 10, 0                  # encoding: [0x4c,0x8a,0x00,0x21]
+         bclrl 4, 10
+# CHECK: bcctr 4, 10, 3                  # encoding: [0x4c,0x8a,0x1c,0x20]
+         bcctr 4, 10, 3
+# CHECK: bcctr 4, 10, 0                  # encoding: [0x4c,0x8a,0x04,0x20]
+         bcctr 4, 10
+# CHECK: bcctrl 4, 10, 3                 # encoding: [0x4c,0x8a,0x1c,0x21]
+         bcctrl 4, 10, 3
+# CHECK: bcctrl 4, 10, 0                 # encoding: [0x4c,0x8a,0x04,0x21]
+         bcctrl 4, 10
 
 # Condition register instructions
 
-# FIXME: crand 2, 3, 4
-# FIXME: crnand 2, 3, 4
+# CHECK: crand 2, 3, 4                   # encoding: [0x4c,0x43,0x22,0x02]
+         crand 2, 3, 4
+# CHECK: crnand 2, 3, 4                  # encoding: [0x4c,0x43,0x21,0xc2]
+         crnand 2, 3, 4
 # CHECK: cror 2, 3, 4                    # encoding: [0x4c,0x43,0x23,0x82]
          cror 2, 3, 4
-# FIXME: crxor 2, 3, 4
-# FIXME: crnor 2, 3, 4
+# CHECK: crxor 2, 3, 4                   # encoding: [0x4c,0x43,0x21,0x82]
+         crxor 2, 3, 4
+# CHECK: crnor 2, 3, 4                   # encoding: [0x4c,0x43,0x20,0x42]
+         crnor 2, 3, 4
 # CHECK: creqv 2, 3, 4                   # encoding: [0x4c,0x43,0x22,0x42]
          creqv 2, 3, 4
-# FIXME: crandc 2, 3, 4
-# FIXME: crorc 2, 3, 4
+# CHECK: crandc 2, 3, 4                  # encoding: [0x4c,0x43,0x21,0x02]
+         crandc 2, 3, 4
+# CHECK: crorc 2, 3, 4                   # encoding: [0x4c,0x43,0x23,0x42]
+         crorc 2, 3, 4
 # CHECK: mcrf 2, 3                       # encoding: [0x4d,0x0c,0x00,0x00]
          mcrf 2, 3
 
@@ -147,7 +177,12 @@
 # CHECK: stdbrx 2, 3, 4                  # encoding: [0x7c,0x43,0x25,0x28]
          stdbrx 2, 3, 4
 
-# FIXME: Fixed-point load and store multiple instructions
+# Fixed-point load and store multiple instructions
+
+# CHECK: lmw 2, 128(1)                   # encoding: [0xb8,0x41,0x00,0x80]
+         lmw 2, 128(1)
+# CHECK: stmw 2, 128(1)                  # encoding: [0xbc,0x41,0x00,0x80]
+         stmw 2, 128(1)
 
 # FIXME: Fixed-point move assist instructions
 
@@ -309,9 +344,36 @@
 # FIXME: divdeuo 2, 3, 4
 # FIXME: divdeuo. 2, 3, 4
 
-# FIXME: Fixed-point compare instructions
-
-# FIXME: Fixed-point trap instructions
+# Fixed-point compare instructions
+
+# CHECK: cmpdi 2, 3, 128                 # encoding: [0x2d,0x23,0x00,0x80]
+         cmpi 2, 1, 3, 128
+# CHECK: cmpd 2, 3, 4                    # encoding: [0x7d,0x23,0x20,0x00]
+         cmp 2, 1, 3, 4
+# CHECK: cmpldi 2, 3, 128                # encoding: [0x29,0x23,0x00,0x80]
+         cmpli 2, 1, 3, 128
+# CHECK: cmpld 2, 3, 4                   # encoding: [0x7d,0x23,0x20,0x40]
+         cmpl 2, 1, 3, 4
+
+# CHECK: cmpwi 2, 3, 128                 # encoding: [0x2d,0x03,0x00,0x80]
+         cmpi 2, 0, 3, 128
+# CHECK: cmpw 2, 3, 4                    # encoding: [0x7d,0x03,0x20,0x00]
+         cmp 2, 0, 3, 4
+# CHECK: cmplwi 2, 3, 128                # encoding: [0x29,0x03,0x00,0x80]
+         cmpli 2, 0, 3, 128
+# CHECK: cmplw 2, 3, 4                   # encoding: [0x7d,0x03,0x20,0x40]
+         cmpl 2, 0, 3, 4
+
+# Fixed-point trap instructions
+
+# CHECK: twi 2, 3, 4                     # encoding: [0x0c,0x43,0x00,0x04]
+         twi 2, 3, 4
+# CHECK: tw 2, 3, 4                      # encoding: [0x7c,0x43,0x20,0x08]
+         tw 2, 3, 4
+# CHECK: tdi 2, 3, 4                     # encoding: [0x08,0x43,0x00,0x04]
+         tdi 2, 3, 4
+# CHECK: td 2, 3, 4                      # encoding: [0x7c,0x43,0x20,0x88]
+         td 2, 3, 4
 
 # Fixed-point select
 
@@ -420,14 +482,18 @@
          rldicr 2, 3, 4, 5
 # CHECK: rldicr. 2, 3, 4, 5              # encoding: [0x78,0x62,0x21,0x45]
          rldicr. 2, 3, 4, 5
-# FIXME: rldic 2, 3, 4, 5
-# FIXME: rldic. 2, 3, 4, 5
+# CHECK: rldic 2, 3, 4, 5                # encoding: [0x78,0x62,0x21,0x48]
+         rldic 2, 3, 4, 5
+# CHECK: rldic. 2, 3, 4, 5               # encoding: [0x78,0x62,0x21,0x49]
+         rldic. 2, 3, 4, 5
 # CHECK: rldcl 2, 3, 4, 5                # encoding: [0x78,0x62,0x21,0x50]
          rldcl 2, 3, 4, 5
 # CHECK: rldcl. 2, 3, 4, 5               # encoding: [0x78,0x62,0x21,0x51]
          rldcl. 2, 3, 4, 5
-# FIXME: rldcr 2, 3, 4, 5
-# FIXME: rldcr. 2, 3, 4, 5
+# CHECK: rldcr 2, 3, 4, 5                # encoding: [0x78,0x62,0x21,0x52]
+         rldcr 2, 3, 4, 5
+# CHECK: rldcr. 2, 3, 4, 5               # encoding: [0x78,0x62,0x21,0x53]
+         rldcr. 2, 3, 4, 5
 # CHECK: rldimi 2, 3, 4, 5               # encoding: [0x78,0x62,0x21,0x4c]
          rldimi 2, 3, 4, 5
 # CHECK: rldimi. 2, 3, 4, 5              # encoding: [0x78,0x62,0x21,0x4d]
@@ -470,14 +536,16 @@
 
 # Move to/from system register instructions
 
-# FIXME: mtspr 256, 2
-# FIXME: mfspr 2, 256
-# CHECK: mtcrf 16, 2                     # encoding: [0x7c,0x41,0x01,0x20]
-         mtcrf 16, 2
+# CHECK: mtspr 600, 2                    # encoding: [0x7c,0x58,0x93,0xa6]
+         mtspr 600, 2
+# CHECK: mfspr 2, 600                    # encoding: [0x7c,0x58,0x92,0xa6]
+         mfspr 2, 600
+# CHECK: mtcrf 123, 2                    # encoding: [0x7c,0x47,0xb1,0x20]
+         mtcrf 123, 2
 # CHECK: mfcr 2                          # encoding: [0x7c,0x40,0x00,0x26]
          mfcr 2
-# FIXME: mtocrf 16, 2
+# CHECK: mtocrf 16, 2                    # encoding: [0x7c,0x51,0x01,0x20]
+         mtocrf 16, 2
 # CHECK: mfocrf 16, 8                    # encoding: [0x7e,0x10,0x80,0x26]
          mfocrf 16, 8
-# FIXME: mcrxr 2
 
diff --git a/test/MC/PowerPC/ppc64-errors.s b/test/MC/PowerPC/ppc64-errors.s
index 1da5753..bc8c95c 100644
--- a/test/MC/PowerPC/ppc64-errors.s
+++ b/test/MC/PowerPC/ppc64-errors.s
@@ -12,6 +12,16 @@
 # CHECK-NEXT: add %r32, %r32, %r32
               add %r32, %r32, %r32
 
+# TLS register operands
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: add 3, symbol@tls, 4
+              add 3, symbol@tls, 4
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: subf 3, 4, symbol@tls
+              subf 3, 4, symbol@tls
+
 # Signed 16-bit immediate operands
 
 # CHECK: error: invalid operand for instruction
@@ -32,6 +42,14 @@
 # CHECK-NEXT: ori 1, 2, 65536
               ori 1, 2, 65536
 
+# Signed 16-bit immediate operands (extended range for addis)
+
+# CHECK: error: invalid operand for instruction
+         addis 1, 0, -65537
+
+# CHECK: error: invalid operand for instruction
+         addis 1, 0, 65536
+
 # D-Form memory operands
 
 # CHECK: error: invalid register number
diff --git a/test/MC/PowerPC/ppc64-fixup-apply.s b/test/MC/PowerPC/ppc64-fixup-apply.s
index fb75703..ba141e4 100644
--- a/test/MC/PowerPC/ppc64-fixup-apply.s
+++ b/test/MC/PowerPC/ppc64-fixup-apply.s
@@ -12,10 +12,43 @@ addis 1, 1, target
 
 .set target, 0x1234
 
+addi 1, 1, target2@l
+addis 1, 1, target2@ha
+
+.set target2, 0x12345678
+
+addi 1, 1, target3-target4@l
+addis 1, 1, target3-target4@ha
+
+.set target3, 0x23455678
+.set target4, 0x12341234
+
+addi 1, 1, target5+0x8000@l
+addis 1, 1, target5+0x8000@ha
+
+.set target5, 0x10000001
+
+1:
+addi 1, 1, 2f-1b@l
+addis 1, 1, 1b-2f@ha
+2:
+
+addi 1, 1, target6@h
+addis 1, 1, target6@h
+
+.set target6, 0x4321fedc
+
+addi 1, 1, target7@higher
+addis 1, 1, target7@highest
+addi 1, 1, target7@highera
+addis 1, 1, target7@highesta
+
+.set target7, 0x1234ffffffff8000
+
 .data
 
 .quad v1
-.word v2
+.long v2
 .short v3
 .byte v4
 
@@ -33,13 +66,16 @@ addis 1, 1, target
 # CHECK-NEXT:    ]
 # CHECK-NEXT:    Address: 0x0
 # CHECK-NEXT:    Offset:
-# CHECK-NEXT:    Size: 8
+# CHECK-NEXT:    Size: 64
 # CHECK-NEXT:    Link: 0
 # CHECK-NEXT:    Info: 0
 # CHECK-NEXT:    AddressAlignment: 4
 # CHECK-NEXT:    EntrySize: 0
 # CHECK-NEXT:    SectionData (
-# CHECK-NEXT:      0000: 38211234 3C211234
+# CHECK-NEXT:      0000: 38211234 3C211234 38215678 3C211234
+# CHECK-NEXT:      0010: 38214444 3C211111 38218001 3C211001
+# CHECK-NEXT:      0020: 38210008 3C210000 38214321 3C214321
+# CHECK-NEXT:      0030: 3821FFFF 3C211234 38210000 3C211235
 # CHECK-NEXT:    )
 # CHECK-NEXT:  }
 
diff --git a/test/MC/PowerPC/ppc64-fixup-explicit.s b/test/MC/PowerPC/ppc64-fixup-explicit.s
new file mode 100644
index 0000000..217e057
--- /dev/null
+++ b/test/MC/PowerPC/ppc64-fixup-explicit.s
@@ -0,0 +1,46 @@
+
+# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s
+
+# RUN: llvm-mc -triple powerpc64-unknown-unknown -filetype=obj %s | \
+# RUN: llvm-readobj -r | FileCheck %s -check-prefix=REL
+
+# GOT references must result in explicit relocations
+# even if the target symbol is local.
+
+target:
+
+# CHECK: addi 4, 3, target@GOT           # encoding: [0x38,0x83,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@GOT, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16 target 0x0
+         addi 4, 3, target@got  
+
+# CHECK: ld 1, target@GOT(2)             # encoding: [0xe8,0x22,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@GOT, kind: fixup_ppc_half16ds
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_DS target 0x0
+         ld 1, target@got(2)
+
+# CHECK: addis 3, 2, target@got@ha       # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@ha, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_HA target 0x0
+         addis 3, 2, target@got@ha
+
+# CHECK: addi 4, 3, target@got@l         # encoding: [0x38,0x83,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO target 0x0
+         addi 4, 3, target@got@l
+
+# CHECK: addis 3, 2, target@got@h        # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@h, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_HI target 0x0
+         addis 3, 2, target@got@h
+
+# CHECK: lwz 1, target@got@l(3)          # encoding: [0x80,0x23,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO target 0x0
+         lwz 1, target@got@l(3)
+
+# CHECK: ld 1, target@got@l(3)           # encoding: [0xe8,0x23,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16ds
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO_DS target 0x0
+         ld 1, target@got@l(3)
+
diff --git a/test/MC/PowerPC/ppc64-fixups.s b/test/MC/PowerPC/ppc64-fixups.s
index 38937c8..56f99d8 100644
--- a/test/MC/PowerPC/ppc64-fixups.s
+++ b/test/MC/PowerPC/ppc64-fixups.s
@@ -4,8 +4,26 @@
 # RUN: llvm-mc -triple powerpc64-unknown-unknown -filetype=obj %s | \
 # RUN: llvm-readobj -r | FileCheck %s -check-prefix=REL
 
+# CHECK: b target                        # encoding: [0b010010AA,A,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_br24
+# CHECK-REL:                             0x{{[0-9A-F]*[048C]}} R_PPC64_REL24 target 0x0
+         b target
+
+# CHECK: ba target                       # encoding: [0b010010AA,A,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs
+# CHECK-REL:                             0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR24 target 0x0
+         ba target
+
+# CHECK: beq 0, target                   # encoding: [0x41,0x82,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
+# CHECK-REL:                             0x{{[0-9A-F]*[048C]}} R_PPC64_REL14 target 0x0
+         beq target
+
+# CHECK: beqa 0, target                  # encoding: [0x41,0x82,A,0bAAAAAA10]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs
+# CHECK-REL:                             0x{{[0-9A-F]*[048C]}} R_PPC64_ADDR14 target 0x0
+         beqa target
 
-# FIXME: .TOC.@tocbase
 
 # CHECK: li 3, target@l                  # encoding: [0x38,0x60,A,A]
 # CHECK-NEXT:                            #   fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16
@@ -37,26 +55,87 @@
 # CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
          lis 3, target@l
 
-# CHECK: li 3, target                    # encoding: [0x38,0x60,A,A]
-# CHECK-NEXT:                            #   fixup A - offset: 2, value: target, kind: fixup_ppc_half16
-# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16 target 0x0
-         li 3, target
+# CHECK: li 3, target@h                  # encoding: [0x38,0x60,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@h, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HI target 0x0
+         li 3, target@h
 
-# CHECK: lis 3, target                   # encoding: [0x3c,0x60,A,A]
-# CHECK-NEXT:                            #   fixup A - offset: 2, value: target, kind: fixup_ppc_half16
-# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16 target 0x0
-         lis 3, target
+# CHECK: lis 3, target@h                  # encoding: [0x3c,0x60,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@h, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HI target 0x0
+         lis 3, target@h
+
+# CHECK: li 3, target@higher             # encoding: [0x38,0x60,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@higher, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHER target 0x0
+         li 3, target@higher
+
+# CHECK: lis 3, target@highest           # encoding: [0x3c,0x60,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@highest, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHEST target 0x0
+         lis 3, target@highest
+
+# CHECK: li 3, target@highera            # encoding: [0x38,0x60,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@highera, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHERA target 0x0
+         li 3, target@highera
+
+# CHECK: lis 3, target@highesta          # encoding: [0x3c,0x60,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@highesta, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHESTA target 0x0
+         lis 3, target@highesta
 
 # CHECK: lwz 1, target@l(3)              # encoding: [0x80,0x23,A,A]
 # CHECK-NEXT:                            #   fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16
 # CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
          lwz 1, target@l(3)
 
+# CHECK: lwz 1, target(3)                # encoding: [0x80,0x23,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16 target 0x0
+         lwz 1, target(3)
+
 # CHECK: ld 1, target@l(3)               # encoding: [0xe8,0x23,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16ds
 # CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO_DS target 0x0
          ld 1, target@l(3)
 
+# CHECK: ld 1, target(3)                 # encoding: [0xe8,0x23,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target, kind: fixup_ppc_half16ds
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_DS target 0x0
+         ld 1, target(3)
+
+base:
+# CHECK: lwz 1, target-base(3)           # encoding: [0x80,0x23,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target-base, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16 target 0x2
+         lwz 1, target-base(3)
+
+# CHECK: li 3, target-base@h             # encoding: [0x38,0x60,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target-base@h, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_HI target 0x6
+         li 3, target-base@h
+
+# CHECK: li 3, target-base@l             # encoding: [0x38,0x60,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target-base@l, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_LO target 0xA
+         li 3, target-base@l
+
+# CHECK: li 3, target-base@ha            # encoding: [0x38,0x60,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target-base@ha, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_REL16_HA target 0xE
+         li 3, target-base@ha
+
+# CHECK: ori 3, 3, target@l              # encoding: [0x60,0x63,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
+         ori 3, 3, target@l
+
+# CHECK: oris 3, 3, target@h             # encoding: [0x64,0x63,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@h, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HI target 0x0
+         oris 3, 3, target@h
+
 # CHECK: ld 1, target@toc(2)             # encoding: [0xe8,0x22,A,0bAAAAAA00]
 # CHECK-NEXT:                            #   fixup A - offset: 2, value: target@toc, kind: fixup_ppc_half16ds
 # CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0
@@ -72,6 +151,11 @@
 # CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
          addi 4, 3, target@toc@l
 
+# CHECK: addis 3, 2, target@toc@h        # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@toc@h, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_HI target 0x0
+         addis 3, 2, target@toc@h
+
 # CHECK: lwz 1, target@toc@l(3)          # encoding: [0x80,0x23,A,A]
 # CHECK-NEXT:                            #   fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16
 # CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
@@ -82,7 +166,40 @@
 # CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO_DS target 0x0
          ld 1, target@toc@l(3)
 
-# FIXME: @tls
+# CHECK: addi 4, 3, target@GOT           # encoding: [0x38,0x83,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@GOT, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16 target 0x0
+         addi 4, 3, target@got  
+
+# CHECK: ld 1, target@GOT(2)             # encoding: [0xe8,0x22,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@GOT, kind: fixup_ppc_half16ds
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_DS target 0x0
+         ld 1, target@got(2)
+
+# CHECK: addis 3, 2, target@got@ha       # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@ha, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_HA target 0x0
+         addis 3, 2, target@got@ha
+
+# CHECK: addi 4, 3, target@got@l         # encoding: [0x38,0x83,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO target 0x0
+         addi 4, 3, target@got@l
+
+# CHECK: addis 3, 2, target@got@h        # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@h, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_HI target 0x0
+         addis 3, 2, target@got@h
+
+# CHECK: lwz 1, target@got@l(3)          # encoding: [0x80,0x23,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO target 0x0
+         lwz 1, target@got@l(3)
+
+# CHECK: ld 1, target@got@l(3)           # encoding: [0xe8,0x23,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@l, kind: fixup_ppc_half16ds
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT16_LO_DS target 0x0
+         ld 1, target@got@l(3)
 
 
 # CHECK: addis 3, 2, target@tprel@ha     # encoding: [0x3c,0x62,A,A]
@@ -95,6 +212,46 @@
 # CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO target 0x0
          addi 3, 3, target@tprel@l
 
+# CHECK: addi 3, 3, target@tprel         # encoding: [0x38,0x63,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@tprel, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16 target 0x0
+         addi 3, 3, target@tprel
+
+# CHECK: addi 3, 3, target@tprel@h       # encoding: [0x38,0x63,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@tprel@h, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HI target 0x0
+         addi 3, 3, target@tprel@h
+
+# CHECK: addi 3, 3, target@tprel@higher  # encoding: [0x38,0x63,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@tprel@higher, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHER target 0x0
+         addi 3, 3, target@tprel@higher
+
+# CHECK: addis 3, 2, target@tprel@highest # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@tprel@highest, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHEST target 0x0
+         addis 3, 2, target@tprel@highest
+
+# CHECK: addi 3, 3, target@tprel@highera  # encoding: [0x38,0x63,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@tprel@highera, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHERA target 0x0
+         addi 3, 3, target@tprel@highera
+
+# CHECK: addis 3, 2, target@tprel@highesta # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@tprel@highesta, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHESTA target 0x0
+         addis 3, 2, target@tprel@highesta
+
+# CHECK: ld 1, target@tprel@l(3)         # encoding: [0xe8,0x23,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@tprel@l, kind: fixup_ppc_half16ds
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO_DS target 0x0
+         ld 1, target@tprel@l(3)
+
+# CHECK: ld 1, target@tprel(3)           # encoding: [0xe8,0x23,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@tprel, kind: fixup_ppc_half16ds
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_DS target 0x0
+         ld 1, target@tprel(3)
+
 # CHECK: addis 3, 2, target@dtprel@ha    # encoding: [0x3c,0x62,A,A]
 # CHECK-NEXT:                            #   fixup A - offset: 2, value: target@dtprel@ha, kind: fixup_ppc_half16
 # CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HA target 0x0
@@ -105,6 +262,46 @@
 # CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO target 0x0
          addi 3, 3, target@dtprel@l
 
+# CHECK: addi 3, 3, target@dtprel         # encoding: [0x38,0x63,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@dtprel, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16 target 0x0
+         addi 3, 3, target@dtprel
+
+# CHECK: addi 3, 3, target@dtprel@h       # encoding: [0x38,0x63,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@dtprel@h, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HI target 0x0
+         addi 3, 3, target@dtprel@h
+
+# CHECK: addi 3, 3, target@dtprel@higher  # encoding: [0x38,0x63,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@dtprel@higher, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHER target 0x0
+         addi 3, 3, target@dtprel@higher
+
+# CHECK: addis 3, 2, target@dtprel@highest # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@dtprel@highest, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHEST target 0x0
+         addis 3, 2, target@dtprel@highest
+
+# CHECK: addi 3, 3, target@dtprel@highera  # encoding: [0x38,0x63,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@dtprel@highera, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHERA target 0x0
+         addi 3, 3, target@dtprel@highera
+
+# CHECK: addis 3, 2, target@dtprel@highesta # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@dtprel@highesta, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHESTA target 0x0
+         addis 3, 2, target@dtprel@highesta
+
+# CHECK: ld 1, target@dtprel@l(3)        # encoding: [0xe8,0x23,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@dtprel@l, kind: fixup_ppc_half16ds
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO_DS target 0x0
+         ld 1, target@dtprel@l(3)
+
+# CHECK: ld 1, target@dtprel(3)          # encoding: [0xe8,0x23,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@dtprel, kind: fixup_ppc_half16ds
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_DS target 0x0
+         ld 1, target@dtprel(3)
+
 
 # CHECK: addis 3, 2, target@got@tprel@ha # encoding: [0x3c,0x62,A,A]
 # CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@tprel@ha, kind: fixup_ppc_half16
@@ -116,6 +313,55 @@
 # CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0
          ld 1, target@got@tprel@l(3)
 
+# CHECK: addis 3, 2, target@got@tprel@h  # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@tprel@h, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HI target 0x0
+         addis 3, 2, target@got@tprel@h
+
+# CHECK: addis 3, 2, target@got@tprel@l  # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@tprel@l, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0
+         addis 3, 2, target@got@tprel@l
+
+# CHECK: addis 3, 2, target@got@tprel    # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@tprel, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_DS target 0x0
+         addis 3, 2, target@got@tprel
+
+# CHECK: ld 1, target@got@tprel(3)       # encoding: [0xe8,0x23,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@tprel, kind: fixup_ppc_half16ds
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_DS target 0x0
+         ld 1, target@got@tprel(3)
+
+# CHECK: addis 3, 2, target@got@dtprel@ha # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@dtprel@ha, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_HA target 0x0
+         addis 3, 2, target@got@dtprel@ha
+
+# CHECK: ld 1, target@got@dtprel@l(3)    # encoding: [0xe8,0x23,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@dtprel@l, kind: fixup_ppc_half16ds
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_LO_DS target 0x0
+         ld 1, target@got@dtprel@l(3)
+
+# CHECK: addis 3, 2, target@got@dtprel@h # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@dtprel@h, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_HI target 0x0
+         addis 3, 2, target@got@dtprel@h
+
+# CHECK: addis 3, 2, target@got@dtprel@l # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@dtprel@l, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_LO_DS target 0x0
+         addis 3, 2, target@got@dtprel@l
+
+# CHECK: addis 3, 2, target@got@dtprel   # encoding: [0x3c,0x62,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@dtprel, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_DS target 0x0
+         addis 3, 2, target@got@dtprel
+
+# CHECK: ld 1, target@got@dtprel(3)      # encoding: [0xe8,0x23,A,0bAAAAAA00]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@dtprel, kind: fixup_ppc_half16ds
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_DS target 0x0
+         ld 1, target@got@dtprel(3)
 
 # CHECK: addis 3, 2, target@got@tlsgd@ha # encoding: [0x3c,0x62,A,A]
 # CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@tlsgd@ha, kind: fixup_ppc_half16
@@ -127,6 +373,16 @@
 # CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_LO target 0x0
          addi 3, 3, target@got@tlsgd@l
 
+# CHECK: addi 3, 3, target@got@tlsgd@h   # encoding: [0x38,0x63,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@tlsgd@h, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_HI target 0x0
+         addi 3, 3, target@got@tlsgd@h
+
+# CHECK: addi 3, 3, target@got@tlsgd     # encoding: [0x38,0x63,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@tlsgd, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16 target 0x0
+         addi 3, 3, target@got@tlsgd
+
 
 # CHECK: addis 3, 2, target@got@tlsld@ha # encoding: [0x3c,0x62,A,A]
 # CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@tlsld@ha, kind: fixup_ppc_half16
@@ -138,3 +394,51 @@
 # CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_LO target 0x0
          addi 3, 3, target@got@tlsld@l
 
+# CHECK: addi 3, 3, target@got@tlsld@h   # encoding: [0x38,0x63,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@tlsld@h, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_HI target 0x0
+         addi 3, 3, target@got@tlsld@h
+
+# CHECK: addi 3, 3, target@got@tlsld     # encoding: [0x38,0x63,A,A]
+# CHECK-NEXT:                            #   fixup A - offset: 2, value: target@got@tlsld, kind: fixup_ppc_half16
+# CHECK-REL:                             0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16 target 0x0
+         addi 3, 3, target@got@tlsld
+
+# CHECK: bl __tls_get_addr(target@tlsgd) # encoding: [0b010010BB,B,B,0bBBBBBB01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target@tlsgd, kind: fixup_ppc_nofixup
+# CHECK-NEXT:                            #   fixup B - offset: 0, value: __tls_get_addr, kind: fixup_ppc_br24
+# CHECK-REL:                             0x{{[0-9A-F]*[048C]}} R_PPC64_TLSGD target 0x0
+# CHECK-REL-NEXT:                        0x{{[0-9A-F]*[048C]}} R_PPC64_REL24 __tls_get_addr 0x0
+         bl __tls_get_addr(target@tlsgd)
+
+# CHECK: bl __tls_get_addr(target@tlsld) # encoding: [0b010010BB,B,B,0bBBBBBB01]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target@tlsld, kind: fixup_ppc_nofixup
+# CHECK-NEXT:                            #   fixup B - offset: 0, value: __tls_get_addr, kind: fixup_ppc_br24
+# CHECK-REL:                             0x{{[0-9A-F]*[048C]}} R_PPC64_TLSLD target 0x0
+# CHECK-REL-NEXT:                        0x{{[0-9A-F]*[048C]}} R_PPC64_REL24 __tls_get_addr 0x0
+         bl __tls_get_addr(target@tlsld)
+
+# CHECK: add 3, 4, target@tls            # encoding: [0x7c,0x64,0x6a,0x14]
+# CHECK-NEXT:                            #   fixup A - offset: 0, value: target@tls, kind: fixup_ppc_nofixup
+# CHECK-REL:                             0x{{[0-9A-F]*[048C]}} R_PPC64_TLS target 0x0
+         add 3, 4, target@tls
+
+
+# Data relocs
+# llvm-mc does not show any "encoding" string for data, so we just check the relocs
+
+# CHECK-REL: .rela.data
+	.data
+
+# CHECK-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_TOC - 0x0
+	.quad .TOC.@tocbase
+
+# CHECK-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_DTPMOD64 target 0x0
+	.quad target@dtpmod
+
+# CHECK-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_TPREL64 target 0x0
+	.quad target@tprel
+
+# CHECK-REL: 0x{{[0-9A-F]*[08]}} R_PPC64_DTPREL64 target 0x0
+	.quad target@dtprel
+
diff --git a/test/MC/PowerPC/ppc64-operands.s b/test/MC/PowerPC/ppc64-operands.s
index de5fcb0..cb96fd4 100644
--- a/test/MC/PowerPC/ppc64-operands.s
+++ b/test/MC/PowerPC/ppc64-operands.s
@@ -40,6 +40,14 @@
 # CHECK: ori 1, 2, 65535                 # encoding: [0x60,0x41,0xff,0xff]
          ori 1, 2, 65535
 
+# Signed 16-bit immediate operands (extended range for addis)
+
+# CHECK: addis 1, 0, 0                   # encoding: [0x3c,0x20,0x00,0x00]
+         addis 1, 0, -65536
+
+# CHECK: addis 1, 0, -1                  # encoding: [0x3c,0x20,0xff,0xff]
+         addis 1, 0, 65535
+
 # D-Form memory operands
 
 # CHECK: lwz 1, 0(0)                     # encoding: [0x80,0x20,0x00,0x00]
@@ -85,3 +93,18 @@
 # CHECK: ld 1, -4(2)                     # encoding: [0xe8,0x22,0xff,0xfc]
          ld 1, -4(2)
 
+
+# Immediate branch operands
+
+# CHECK: b .+1024                        # encoding: [0x48,0x00,0x04,0x00]
+         b 1024
+
+# CHECK: ba 1024                         # encoding: [0x48,0x00,0x04,0x02]
+         ba 1024
+
+# CHECK: beq 0, .+1024                   # encoding: [0x41,0x82,0x04,0x00]
+         beq 1024
+
+# CHECK: beqa 0, 1024                    # encoding: [0x41,0x82,0x04,0x02]
+         beqa 1024
+
diff --git a/test/MC/PowerPC/ppc64-regs.s b/test/MC/PowerPC/ppc64-regs.s
new file mode 100644
index 0000000..02b1fc5
--- /dev/null
+++ b/test/MC/PowerPC/ppc64-regs.s
@@ -0,0 +1,235 @@
+# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s
+
+#CHECK: .cfi_startproc
+#CHECK: .cfi_offset r0, 0
+#CHECK: .cfi_offset r1, 8
+#CHECK: .cfi_offset r2, 16
+#CHECK: .cfi_offset r3, 24
+#CHECK: .cfi_offset r4, 32
+#CHECK: .cfi_offset r5, 40
+#CHECK: .cfi_offset r6, 48
+#CHECK: .cfi_offset r7, 56
+#CHECK: .cfi_offset r8, 64
+#CHECK: .cfi_offset r9, 72
+#CHECK: .cfi_offset r10, 80
+#CHECK: .cfi_offset r11, 88
+#CHECK: .cfi_offset r12, 96
+#CHECK: .cfi_offset r13, 104
+#CHECK: .cfi_offset r14, 112
+#CHECK: .cfi_offset r15, 120
+#CHECK: .cfi_offset r16, 128
+#CHECK: .cfi_offset r17, 136
+#CHECK: .cfi_offset r18, 144
+#CHECK: .cfi_offset r19, 152
+#CHECK: .cfi_offset r20, 160
+#CHECK: .cfi_offset r21, 168
+#CHECK: .cfi_offset r22, 176
+#CHECK: .cfi_offset r22, 184
+#CHECK: .cfi_offset r23, 192
+#CHECK: .cfi_offset r24, 200
+#CHECK: .cfi_offset r25, 208
+#CHECK: .cfi_offset r26, 216
+#CHECK: .cfi_offset r27, 224
+#CHECK: .cfi_offset r28, 232
+#CHECK: .cfi_offset r29, 240
+#CHECK: .cfi_offset r30, 248
+#CHECK: .cfi_offset r31, 256
+
+#CHECK: .cfi_offset f0, 300
+#CHECK: .cfi_offset f1, 308
+#CHECK: .cfi_offset f2, 316
+#CHECK: .cfi_offset f3, 324
+#CHECK: .cfi_offset f4, 332
+#CHECK: .cfi_offset f5, 340
+#CHECK: .cfi_offset f6, 348
+#CHECK: .cfi_offset f7, 356
+#CHECK: .cfi_offset f8, 364
+#CHECK: .cfi_offset f9, 372
+#CHECK: .cfi_offset f10, 380
+#CHECK: .cfi_offset f11, 388
+#CHECK: .cfi_offset f12, 396
+#CHECK: .cfi_offset f13, 404
+#CHECK: .cfi_offset f14, 412
+#CHECK: .cfi_offset f15, 420
+#CHECK: .cfi_offset f16, 428
+#CHECK: .cfi_offset f17, 436
+#CHECK: .cfi_offset f18, 444
+#CHECK: .cfi_offset f19, 452
+#CHECK: .cfi_offset f20, 460
+#CHECK: .cfi_offset f21, 468
+#CHECK: .cfi_offset f22, 476
+#CHECK: .cfi_offset f22, 484
+#CHECK: .cfi_offset f23, 492
+#CHECK: .cfi_offset f24, 500
+#CHECK: .cfi_offset f25, 508
+#CHECK: .cfi_offset f26, 516
+#CHECK: .cfi_offset f27, 524
+#CHECK: .cfi_offset f28, 532
+#CHECK: .cfi_offset f29, 540
+#CHECK: .cfi_offset f30, 548
+#CHECK: .cfi_offset f31, 556
+
+#CHECK: .cfi_offset lr, 600
+#CHECK: .cfi_offset ctr, 608
+#CHECK: .cfi_offset vrsave, 616
+
+#CHECK: .cfi_offset cr0, 620
+#CHECK: .cfi_offset cr1, 621
+#CHECK: .cfi_offset cr2, 622
+#CHECK: .cfi_offset cr3, 623
+#CHECK: .cfi_offset cr4, 624
+#CHECK: .cfi_offset cr5, 625
+#CHECK: .cfi_offset cr6, 626
+#CHECK: .cfi_offset cr7, 627
+
+#CHECK: .cfi_offset v0, 700
+#CHECK: .cfi_offset v1, 716
+#CHECK: .cfi_offset v2, 732
+#CHECK: .cfi_offset v3, 748
+#CHECK: .cfi_offset v4, 764
+#CHECK: .cfi_offset v5, 780
+#CHECK: .cfi_offset v6, 796
+#CHECK: .cfi_offset v7, 812
+#CHECK: .cfi_offset v8, 828
+#CHECK: .cfi_offset v9, 844
+#CHECK: .cfi_offset v10, 860
+#CHECK: .cfi_offset v11, 876
+#CHECK: .cfi_offset v12, 892
+#CHECK: .cfi_offset v13, 908
+#CHECK: .cfi_offset v14, 924
+#CHECK: .cfi_offset v15, 940
+#CHECK: .cfi_offset v16, 956
+#CHECK: .cfi_offset v17, 972
+#CHECK: .cfi_offset v18, 988
+#CHECK: .cfi_offset v19, 1004
+#CHECK: .cfi_offset v20, 1020
+#CHECK: .cfi_offset v21, 1036
+#CHECK: .cfi_offset v22, 1052
+#CHECK: .cfi_offset v22, 1068
+#CHECK: .cfi_offset v23, 1084
+#CHECK: .cfi_offset v24, 1100
+#CHECK: .cfi_offset v25, 1116
+#CHECK: .cfi_offset v26, 1132
+#CHECK: .cfi_offset v27, 1148
+#CHECK: .cfi_offset v28, 1164
+#CHECK: .cfi_offset v29, 1180
+#CHECK: .cfi_offset v30, 1196
+#CHECK: .cfi_offset v31, 1212
+#CHECK: .cfi_endproc
+
+	.cfi_startproc
+	.cfi_offset r0,0
+	.cfi_offset r1,8
+	.cfi_offset r2,16
+	.cfi_offset r3,24
+	.cfi_offset r4,32
+	.cfi_offset r5,40
+	.cfi_offset r6,48
+	.cfi_offset r7,56
+	.cfi_offset r8,64
+	.cfi_offset r9,72
+	.cfi_offset r10,80
+	.cfi_offset r11,88
+	.cfi_offset r12,96
+	.cfi_offset r13,104
+	.cfi_offset r14,112
+	.cfi_offset r15,120
+	.cfi_offset r16,128
+	.cfi_offset r17,136
+	.cfi_offset r18,144
+	.cfi_offset r19,152
+	.cfi_offset r20,160
+	.cfi_offset r21,168
+	.cfi_offset r22,176
+	.cfi_offset r22,184
+	.cfi_offset r23,192
+	.cfi_offset r24,200
+	.cfi_offset r25,208
+	.cfi_offset r26,216
+	.cfi_offset r27,224
+	.cfi_offset r28,232
+	.cfi_offset r29,240
+	.cfi_offset r30,248
+	.cfi_offset r31,256
+
+	.cfi_offset f0,300
+	.cfi_offset f1,308
+	.cfi_offset f2,316
+	.cfi_offset f3,324
+	.cfi_offset f4,332
+	.cfi_offset f5,340
+	.cfi_offset f6,348
+	.cfi_offset f7,356
+	.cfi_offset f8,364
+	.cfi_offset f9,372
+	.cfi_offset f10,380
+	.cfi_offset f11,388
+	.cfi_offset f12,396
+	.cfi_offset f13,404
+	.cfi_offset f14,412
+	.cfi_offset f15,420
+	.cfi_offset f16,428
+	.cfi_offset f17,436
+	.cfi_offset f18,444
+	.cfi_offset f19,452
+	.cfi_offset f20,460
+	.cfi_offset f21,468
+	.cfi_offset f22,476
+	.cfi_offset f22,484
+	.cfi_offset f23,492
+	.cfi_offset f24,500
+	.cfi_offset f25,508
+	.cfi_offset f26,516
+	.cfi_offset f27,524
+	.cfi_offset f28,532
+	.cfi_offset f29,540
+	.cfi_offset f30,548
+	.cfi_offset f31,556
+
+	.cfi_offset lr,600
+	.cfi_offset ctr,608
+	.cfi_offset vrsave,616
+	.cfi_offset cr0,620
+	.cfi_offset cr1,621
+	.cfi_offset cr2,622
+	.cfi_offset cr3,623
+	.cfi_offset cr4,624
+	.cfi_offset cr5,625
+	.cfi_offset cr6,626
+	.cfi_offset cr7,627
+
+	.cfi_offset v0,700
+	.cfi_offset v1,716
+	.cfi_offset v2,732
+	.cfi_offset v3,748
+	.cfi_offset v4,764
+	.cfi_offset v5,780
+	.cfi_offset v6,796
+	.cfi_offset v7,812
+	.cfi_offset v8,828
+	.cfi_offset v9,844
+	.cfi_offset v10,860
+	.cfi_offset v11,876
+	.cfi_offset v12,892
+	.cfi_offset v13,908
+	.cfi_offset v14,924
+	.cfi_offset v15,940
+	.cfi_offset v16,956
+	.cfi_offset v17,972
+	.cfi_offset v18,988
+	.cfi_offset v19,1004
+	.cfi_offset v20,1020
+	.cfi_offset v21,1036
+	.cfi_offset v22,1052
+	.cfi_offset v22,1068
+	.cfi_offset v23,1084
+	.cfi_offset v24,1100
+	.cfi_offset v25,1116
+	.cfi_offset v26,1132
+	.cfi_offset v27,1148
+	.cfi_offset v28,1164
+	.cfi_offset v29,1180
+	.cfi_offset v30,1196
+	.cfi_offset v31,1212
+
+	.cfi_endproc
diff --git a/test/MC/SystemZ/insn-bad-z196.s b/test/MC/SystemZ/insn-bad-z196.s
new file mode 100644
index 0000000..ec90c89
--- /dev/null
+++ b/test/MC/SystemZ/insn-bad-z196.s
@@ -0,0 +1,191 @@
+# For z196 only.
+# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=z196 < %s 2> %t
+# RUN: FileCheck < %t %s
+
+#CHECK: error: invalid operand
+#CHECK: aghik	%r0, %r1, -32769
+#CHECK: error: invalid operand
+#CHECK: aghik	%r0, %r1, 32768
+#CHECK: error: invalid operand
+#CHECK: aghik	%r0, %r1, foo
+
+	aghik	%r0, %r1, -32769
+	aghik	%r0, %r1, 32768
+	aghik	%r0, %r1, foo
+
+#CHECK: error: invalid operand
+#CHECK: ahik	%r0, %r1, -32769
+#CHECK: error: invalid operand
+#CHECK: ahik	%r0, %r1, 32768
+#CHECK: error: invalid operand
+#CHECK: ahik	%r0, %r1, foo
+
+	ahik	%r0, %r1, -32769
+	ahik	%r0, %r1, 32768
+	ahik	%r0, %r1, foo
+
+#CHECK: error: invalid operand
+#CHECK: loc	%r0,0,-1
+#CHECK: error: invalid operand
+#CHECK: loc	%r0,0,16
+#CHECK: error: invalid operand
+#CHECK: loc	%r0,-524289,1
+#CHECK: error: invalid operand
+#CHECK: loc	%r0,524288,1
+#CHECK: error: invalid use of indexed addressing
+#CHECK: loc	%r0,0(%r1,%r2),1
+
+	loc	%r0,0,-1
+	loc	%r0,0,16
+	loc	%r0,-524289,1
+	loc	%r0,524288,1
+	loc	%r0,0(%r1,%r2),1
+
+#CHECK: error: invalid operand
+#CHECK: locg	%r0,0,-1
+#CHECK: error: invalid operand
+#CHECK: locg	%r0,0,16
+#CHECK: error: invalid operand
+#CHECK: locg	%r0,-524289,1
+#CHECK: error: invalid operand
+#CHECK: locg	%r0,524288,1
+#CHECK: error: invalid use of indexed addressing
+#CHECK: locg	%r0,0(%r1,%r2),1
+
+	locg	%r0,0,-1
+	locg	%r0,0,16
+	locg	%r0,-524289,1
+	locg	%r0,524288,1
+	locg	%r0,0(%r1,%r2),1
+
+#CHECK: error: invalid operand
+#CHECK: locgr	%r0,%r0,-1
+#CHECK: error: invalid operand
+#CHECK: locgr	%r0,%r0,16
+
+	locgr	%r0,%r0,-1
+	locgr	%r0,%r0,16
+
+#CHECK: error: invalid operand
+#CHECK: locr	%r0,%r0,-1
+#CHECK: error: invalid operand
+#CHECK: locr	%r0,%r0,16
+
+	locr	%r0,%r0,-1
+	locr	%r0,%r0,16
+
+#CHECK: error: invalid operand
+#CHECK: risbhg	%r0,%r0,0,0,-1
+#CHECK: error: invalid operand
+#CHECK: risbhg	%r0,%r0,0,0,64
+#CHECK: error: invalid operand
+#CHECK: risbhg	%r0,%r0,0,-1,0
+#CHECK: error: invalid operand
+#CHECK: risbhg	%r0,%r0,0,256,0
+#CHECK: error: invalid operand
+#CHECK: risbhg	%r0,%r0,-1,0,0
+#CHECK: error: invalid operand
+#CHECK: risbhg	%r0,%r0,256,0,0
+
+	risbhg	%r0,%r0,0,0,-1
+	risbhg	%r0,%r0,0,0,64
+	risbhg	%r0,%r0,0,-1,0
+	risbhg	%r0,%r0,0,256,0
+	risbhg	%r0,%r0,-1,0,0
+	risbhg	%r0,%r0,256,0,0
+
+#CHECK: error: invalid operand
+#CHECK: risblg	%r0,%r0,0,0,-1
+#CHECK: error: invalid operand
+#CHECK: risblg	%r0,%r0,0,0,64
+#CHECK: error: invalid operand
+#CHECK: risblg	%r0,%r0,0,-1,0
+#CHECK: error: invalid operand
+#CHECK: risblg	%r0,%r0,0,256,0
+#CHECK: error: invalid operand
+#CHECK: risblg	%r0,%r0,-1,0,0
+#CHECK: error: invalid operand
+#CHECK: risblg	%r0,%r0,256,0,0
+
+	risblg	%r0,%r0,0,0,-1
+	risblg	%r0,%r0,0,0,64
+	risblg	%r0,%r0,0,-1,0
+	risblg	%r0,%r0,0,256,0
+	risblg	%r0,%r0,-1,0,0
+	risblg	%r0,%r0,256,0,0
+
+#CHECK: error: invalid operand
+#CHECK: sllk	%r0,%r0,-524289
+#CHECK: error: invalid operand
+#CHECK: sllk	%r0,%r0,524288
+#CHECK: error: %r0 used in an address
+#CHECK: sllk	%r0,%r0,0(%r0)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: sllk	%r0,%r0,0(%r1,%r2)
+
+	sllk	%r0,%r0,-524289
+	sllk	%r0,%r0,524288
+	sllk	%r0,%r0,0(%r0)
+	sllk	%r0,%r0,0(%r1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: srak	%r0,%r0,-524289
+#CHECK: error: invalid operand
+#CHECK: srak	%r0,%r0,524288
+#CHECK: error: %r0 used in an address
+#CHECK: srak	%r0,%r0,0(%r0)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: srak	%r0,%r0,0(%r1,%r2)
+
+	srak	%r0,%r0,-524289
+	srak	%r0,%r0,524288
+	srak	%r0,%r0,0(%r0)
+	srak	%r0,%r0,0(%r1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: srlk	%r0,%r0,-524289
+#CHECK: error: invalid operand
+#CHECK: srlk	%r0,%r0,524288
+#CHECK: error: %r0 used in an address
+#CHECK: srlk	%r0,%r0,0(%r0)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: srlk	%r0,%r0,0(%r1,%r2)
+
+	srlk	%r0,%r0,-524289
+	srlk	%r0,%r0,524288
+	srlk	%r0,%r0,0(%r0)
+	srlk	%r0,%r0,0(%r1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: stoc	%r0,0,-1
+#CHECK: error: invalid operand
+#CHECK: stoc	%r0,0,16
+#CHECK: error: invalid operand
+#CHECK: stoc	%r0,-524289,1
+#CHECK: error: invalid operand
+#CHECK: stoc	%r0,524288,1
+#CHECK: error: invalid use of indexed addressing
+#CHECK: stoc	%r0,0(%r1,%r2),1
+
+	stoc	%r0,0,-1
+	stoc	%r0,0,16
+	stoc	%r0,-524289,1
+	stoc	%r0,524288,1
+	stoc	%r0,0(%r1,%r2),1
+
+#CHECK: error: invalid operand
+#CHECK: stocg	%r0,0,-1
+#CHECK: error: invalid operand
+#CHECK: stocg	%r0,0,16
+#CHECK: error: invalid operand
+#CHECK: stocg	%r0,-524289,1
+#CHECK: error: invalid operand
+#CHECK: stocg	%r0,524288,1
+#CHECK: error: invalid use of indexed addressing
+#CHECK: stocg	%r0,0(%r1,%r2),1
+
+	stocg	%r0,0,-1
+	stocg	%r0,0,16
+	stocg	%r0,-524289,1
+	stocg	%r0,524288,1
+	stocg	%r0,0(%r1,%r2),1
diff --git a/test/MC/SystemZ/insn-bad.s b/test/MC/SystemZ/insn-bad.s
index 8dbe718..b730637 100644
--- a/test/MC/SystemZ/insn-bad.s
+++ b/test/MC/SystemZ/insn-bad.s
@@ -1,4 +1,5 @@
-# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t
+# For z10 only.
+# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=z10 < %s 2> %t
 # RUN: FileCheck < %t %s
 
 #CHECK: error: invalid operand
@@ -68,6 +69,16 @@
 	aghi	%r0, 32768
 	aghi	%r0, foo
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: aghik	%r1, %r2, 3
+
+	aghik	%r1, %r2, 3
+
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: agrk	%r2,%r3,%r4
+
+	agrk	%r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: agsi	-524289, 0
 #CHECK: error: invalid operand
@@ -104,6 +115,11 @@
 	ahi	%r0, 32768
 	ahi	%r0, foo
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: ahik	%r1, %r2, 3
+
+	ahik	%r1, %r2, 3
+
 #CHECK: error: invalid operand
 #CHECK: ahy	%r0, -524289
 #CHECK: error: invalid operand
@@ -144,6 +160,16 @@
 	alfi	%r0, -1
 	alfi	%r0, (1 << 32)
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: alghsik	%r1, %r2, 3
+
+	alghsik	%r1, %r2, 3
+
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: alhsik	%r1, %r2, 3
+
+	alhsik	%r1, %r2, 3
+
 #CHECK: error: invalid operand
 #CHECK: alg	%r0, -524289
 #CHECK: error: invalid operand
@@ -168,6 +194,16 @@
 	algfi	%r0, -1
 	algfi	%r0, (1 << 32)
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: algrk	%r2,%r3,%r4
+
+	algrk	%r2,%r3,%r4
+
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: alrk	%r2,%r3,%r4
+
+	alrk	%r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: aly	%r0, -524289
 #CHECK: error: invalid operand
@@ -176,6 +212,11 @@
 	aly	%r0, -524289
 	aly	%r0, 524288
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: ark	%r2,%r3,%r4
+
+	ark	%r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: asi	-524289, 0
 #CHECK: error: invalid operand
@@ -288,6 +329,34 @@
 	brcl	-1, bar
 	brcl	16, bar
 
+#CHECK: error: offset out of range
+#CHECK: brct	%r0, -0x100002
+#CHECK: error: offset out of range
+#CHECK: brct	%r0, -1
+#CHECK: error: offset out of range
+#CHECK: brct	%r0, 1
+#CHECK: error: offset out of range
+#CHECK: brct	%r0, 0x10000
+
+	brct	%r0, -0x100002
+	brct	%r0, -1
+	brct	%r0, 1
+	brct	%r0, 0x10000
+
+#CHECK: error: offset out of range
+#CHECK: brctg	%r0, -0x100002
+#CHECK: error: offset out of range
+#CHECK: brctg	%r0, -1
+#CHECK: error: offset out of range
+#CHECK: brctg	%r0, 1
+#CHECK: error: offset out of range
+#CHECK: brctg	%r0, 0x10000
+
+	brctg	%r0, -0x100002
+	brctg	%r0, -1
+	brctg	%r0, 1
+	brctg	%r0, 0x10000
+
 #CHECK: error: invalid operand
 #CHECK: c	%r0, -1
 #CHECK: error: invalid operand
@@ -1551,6 +1620,38 @@
 	lrvg	%r0, -524289
 	lrvg	%r0, 524288
 
+#CHECK: error: invalid operand
+#CHECK: lt	%r0, -524289
+#CHECK: error: invalid operand
+#CHECK: lt	%r0, 524288
+
+	lt	%r0, -524289
+	lt	%r0, 524288
+
+#CHECK: error: invalid operand
+#CHECK: ltg	%r0, -524289
+#CHECK: error: invalid operand
+#CHECK: ltg	%r0, 524288
+
+	ltg	%r0, -524289
+	ltg	%r0, 524288
+
+#CHECK: error: invalid operand
+#CHECK: ltgf	%r0, -524289
+#CHECK: error: invalid operand
+#CHECK: ltgf	%r0, 524288
+
+	ltgf	%r0, -524289
+	ltgf	%r0, 524288
+
+#CHECK: error: invalid register pair
+#CHECK: ltxbr	%f0, %f14
+#CHECK: error: invalid register pair
+#CHECK: ltxbr	%f14, %f0
+
+	ltxbr	%f0, %f14
+	ltxbr	%f14, %f0
+
 #CHECK: error: invalid register pair
 #CHECK: lxr	%f0, %f2
 #CHECK: error: invalid register pair
@@ -1730,6 +1831,50 @@
 	msy	%r0, -524289
 	msy	%r0, 524288
 
+#CHECK: error: missing length in address
+#CHECK: mvc	0, 0
+#CHECK: error: missing length in address
+#CHECK: mvc	0(%r1), 0(%r1)
+#CHECK: error: invalid use of length addressing
+#CHECK: mvc	0(1,%r1), 0(2,%r1)
+#CHECK: error: invalid operand
+#CHECK: mvc	0(0,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: mvc	0(257,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: mvc	-1(1,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: mvc	4096(1,%r1), 0(%r1)
+#CHECK: error: invalid operand
+#CHECK: mvc	0(1,%r1), -1(%r1)
+#CHECK: error: invalid operand
+#CHECK: mvc	0(1,%r1), 4096(%r1)
+#CHECK: error: %r0 used in an address
+#CHECK: mvc	0(1,%r0), 0(%r1)
+#CHECK: error: %r0 used in an address
+#CHECK: mvc	0(1,%r1), 0(%r0)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: mvc	0(%r1,%r2), 0(%r1)
+#CHECK: error: invalid use of indexed addressing
+#CHECK: mvc	0(1,%r2), 0(%r1,%r2)
+#CHECK: error: unknown token in expression
+#CHECK: mvc	0(-), 0
+
+	mvc	0, 0
+	mvc	0(%r1), 0(%r1)
+	mvc	0(1,%r1), 0(2,%r1)
+	mvc	0(0,%r1), 0(%r1)
+	mvc	0(257,%r1), 0(%r1)
+	mvc	-1(1,%r1), 0(%r1)
+	mvc	4096(1,%r1), 0(%r1)
+	mvc	0(1,%r1), -1(%r1)
+	mvc	0(1,%r1), 4096(%r1)
+	mvc	0(1,%r0), 0(%r1)
+	mvc	0(1,%r1), 0(%r0)
+	mvc	0(%r1,%r2), 0(%r1)
+	mvc	0(1,%r2), 0(%r1,%r2)
+	mvc	0(-), 0
+
 #CHECK: error: invalid operand
 #CHECK: mvghi	-1, 0
 #CHECK: error: invalid operand
@@ -1855,6 +2000,11 @@
 	ng	%r0, -524289
 	ng	%r0, 524288
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: ngrk	%r2,%r3,%r4
+
+	ngrk	%r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: ni	-1, 0
 #CHECK: error: invalid operand
@@ -1937,6 +2087,11 @@
 	niy	0, -1
 	niy	0, 256
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: nrk	%r2,%r3,%r4
+
+	nrk	%r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: ny	%r0, -524289
 #CHECK: error: invalid operand
@@ -1961,6 +2116,11 @@
 	og	%r0, -524289
 	og	%r0, 524288
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: ogrk	%r2,%r3,%r4
+
+	ogrk	%r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: oi	-1, 0
 #CHECK: error: invalid operand
@@ -2043,6 +2203,11 @@
 	oiy	0, -1
 	oiy	0, 256
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: ork	%r2,%r3,%r4
+
+	ork	%r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: oy	%r0, -524289
 #CHECK: error: invalid operand
@@ -2058,18 +2223,88 @@
 #CHECK: error: invalid operand
 #CHECK: risbg	%r0,%r0,0,-1,0
 #CHECK: error: invalid operand
-#CHECK: risbg	%r0,%r0,0,64,0
+#CHECK: risbg	%r0,%r0,0,256,0
 #CHECK: error: invalid operand
 #CHECK: risbg	%r0,%r0,-1,0,0
 #CHECK: error: invalid operand
-#CHECK: risbg	%r0,%r0,64,0,0
+#CHECK: risbg	%r0,%r0,256,0,0
 
 	risbg	%r0,%r0,0,0,-1
 	risbg	%r0,%r0,0,0,64
 	risbg	%r0,%r0,0,-1,0
-	risbg	%r0,%r0,0,64,0
+	risbg	%r0,%r0,0,256,0
 	risbg	%r0,%r0,-1,0,0
-	risbg	%r0,%r0,64,0,0
+	risbg	%r0,%r0,256,0,0
+
+#CHECK: error: {{(instruction requires: high-word)?}}
+#CHECK: risbhg	%r1, %r2, 0, 0, 0
+
+	risbhg	%r1, %r2, 0, 0, 0
+
+#CHECK: error: {{(instruction requires: high-word)?}}
+#CHECK: risblg	%r1, %r2, 0, 0, 0
+
+	risblg	%r1, %r2, 0, 0, 0
+
+#CHECK: error: invalid operand
+#CHECK: rnsbg	%r0,%r0,0,0,-1
+#CHECK: error: invalid operand
+#CHECK: rnsbg	%r0,%r0,0,0,64
+#CHECK: error: invalid operand
+#CHECK: rnsbg	%r0,%r0,0,-1,0
+#CHECK: error: invalid operand
+#CHECK: rnsbg	%r0,%r0,0,256,0
+#CHECK: error: invalid operand
+#CHECK: rnsbg	%r0,%r0,-1,0,0
+#CHECK: error: invalid operand
+#CHECK: rnsbg	%r0,%r0,256,0,0
+
+	rnsbg	%r0,%r0,0,0,-1
+	rnsbg	%r0,%r0,0,0,64
+	rnsbg	%r0,%r0,0,-1,0
+	rnsbg	%r0,%r0,0,256,0
+	rnsbg	%r0,%r0,-1,0,0
+	rnsbg	%r0,%r0,256,0,0
+
+#CHECK: error: invalid operand
+#CHECK: rosbg	%r0,%r0,0,0,-1
+#CHECK: error: invalid operand
+#CHECK: rosbg	%r0,%r0,0,0,64
+#CHECK: error: invalid operand
+#CHECK: rosbg	%r0,%r0,0,-1,0
+#CHECK: error: invalid operand
+#CHECK: rosbg	%r0,%r0,0,256,0
+#CHECK: error: invalid operand
+#CHECK: rosbg	%r0,%r0,-1,0,0
+#CHECK: error: invalid operand
+#CHECK: rosbg	%r0,%r0,256,0,0
+
+	rosbg	%r0,%r0,0,0,-1
+	rosbg	%r0,%r0,0,0,64
+	rosbg	%r0,%r0,0,-1,0
+	rosbg	%r0,%r0,0,256,0
+	rosbg	%r0,%r0,-1,0,0
+	rosbg	%r0,%r0,256,0,0
+
+#CHECK: error: invalid operand
+#CHECK: rxsbg	%r0,%r0,0,0,-1
+#CHECK: error: invalid operand
+#CHECK: rxsbg	%r0,%r0,0,0,64
+#CHECK: error: invalid operand
+#CHECK: rxsbg	%r0,%r0,0,-1,0
+#CHECK: error: invalid operand
+#CHECK: rxsbg	%r0,%r0,0,256,0
+#CHECK: error: invalid operand
+#CHECK: rxsbg	%r0,%r0,-1,0,0
+#CHECK: error: invalid operand
+#CHECK: rxsbg	%r0,%r0,256,0,0
+
+	rxsbg	%r0,%r0,0,0,-1
+	rxsbg	%r0,%r0,0,0,64
+	rxsbg	%r0,%r0,0,-1,0
+	rxsbg	%r0,%r0,0,256,0
+	rxsbg	%r0,%r0,-1,0,0
+	rxsbg	%r0,%r0,256,0,0
 
 #CHECK: error: invalid operand
 #CHECK: rll	%r0,%r0,-524289
@@ -2139,6 +2374,11 @@
 	sgf	%r0, -524289
 	sgf	%r0, 524288
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: sgrk	%r2,%r3,%r4
+
+	sgrk	%r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: sh	%r0, -1
 #CHECK: error: invalid operand
@@ -2211,6 +2451,11 @@
 	slgfi	%r0, -1
 	slgfi	%r0, (1 << 32)
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: slgrk	%r2,%r3,%r4
+
+	slgrk	%r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: sll	%r0,-1
 #CHECK: error: invalid operand
@@ -2239,6 +2484,16 @@
 	sllg	%r0,%r0,0(%r0)
 	sllg	%r0,%r0,0(%r1,%r2)
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: sllk	%r2,%r3,4(%r5)
+
+	sllk	%r2,%r3,4(%r5)
+
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: slrk	%r2,%r3,%r4
+
+	slrk	%r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: sly	%r0, -524289
 #CHECK: error: invalid operand
@@ -2299,6 +2554,16 @@
 	srag	%r0,%r0,0(%r0)
 	srag	%r0,%r0,0(%r1,%r2)
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: srak	%r2,%r3,4(%r5)
+
+	srak	%r2,%r3,4(%r5)
+
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: srk	%r2,%r3,%r4
+
+	srk	%r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: srl	%r0,-1
 #CHECK: error: invalid operand
@@ -2327,6 +2592,11 @@
 	srlg	%r0,%r0,0(%r0)
 	srlg	%r0,%r0,0(%r1,%r2)
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: srlk	%r2,%r3,4(%r5)
+
+	srlk	%r2,%r3,4(%r5)
+
 #CHECK: error: invalid operand
 #CHECK: st	%r0, -1
 #CHECK: error: invalid operand
@@ -2516,6 +2786,11 @@
 	xg	%r0, -524289
 	xg	%r0, 524288
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: xgrk	%r2,%r3,%r4
+
+	xgrk	%r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: xi	-1, 0
 #CHECK: error: invalid operand
@@ -2566,6 +2841,11 @@
 	xiy	0, -1
 	xiy	0, 256
 
+#CHECK: error: {{(instruction requires: distinct-ops)?}}
+#CHECK: xrk	%r2,%r3,%r4
+
+	xrk	%r2,%r3,%r4
+
 #CHECK: error: invalid operand
 #CHECK: xy	%r0, -524289
 #CHECK: error: invalid operand
diff --git a/test/MC/SystemZ/insn-good-z196.s b/test/MC/SystemZ/insn-good-z196.s
new file mode 100644
index 0000000..5f7c277
--- /dev/null
+++ b/test/MC/SystemZ/insn-good-z196.s
@@ -0,0 +1,616 @@
+# For z196 and above.
+# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z196 -show-encoding %s | FileCheck %s
+
+#CHECK: aghik	%r0, %r0, -32768        # encoding: [0xec,0x00,0x80,0x00,0x00,0xd9]
+#CHECK: aghik	%r0, %r0, -1            # encoding: [0xec,0x00,0xff,0xff,0x00,0xd9]
+#CHECK: aghik	%r0, %r0, 0             # encoding: [0xec,0x00,0x00,0x00,0x00,0xd9]
+#CHECK: aghik	%r0, %r0, 1             # encoding: [0xec,0x00,0x00,0x01,0x00,0xd9]
+#CHECK: aghik	%r0, %r0, 32767         # encoding: [0xec,0x00,0x7f,0xff,0x00,0xd9]
+#CHECK: aghik	%r0, %r15, 0            # encoding: [0xec,0x0f,0x00,0x00,0x00,0xd9]
+#CHECK: aghik	%r15, %r0, 0            # encoding: [0xec,0xf0,0x00,0x00,0x00,0xd9]
+#CHECK: aghik	%r7, %r8, -16           # encoding: [0xec,0x78,0xff,0xf0,0x00,0xd9]
+
+	aghik	%r0, %r0, -32768
+	aghik	%r0, %r0, -1
+	aghik	%r0, %r0, 0
+	aghik	%r0, %r0, 1
+	aghik	%r0, %r0, 32767
+	aghik	%r0, %r15, 0
+	aghik	%r15, %r0, 0
+	aghik	%r7, %r8, -16
+
+#CHECK: agrk	%r0, %r0, %r0           # encoding: [0xb9,0xe8,0x00,0x00]
+#CHECK: agrk	%r0, %r0, %r15          # encoding: [0xb9,0xe8,0xf0,0x00]
+#CHECK: agrk	%r0, %r15, %r0          # encoding: [0xb9,0xe8,0x00,0x0f]
+#CHECK: agrk	%r15, %r0, %r0          # encoding: [0xb9,0xe8,0x00,0xf0]
+#CHECK: agrk	%r7, %r8, %r9           # encoding: [0xb9,0xe8,0x90,0x78]
+
+	agrk	%r0,%r0,%r0
+	agrk	%r0,%r0,%r15
+	agrk	%r0,%r15,%r0
+	agrk	%r15,%r0,%r0
+	agrk	%r7,%r8,%r9
+
+#CHECK: ahik	%r0, %r0, -32768        # encoding: [0xec,0x00,0x80,0x00,0x00,0xd8]
+#CHECK: ahik	%r0, %r0, -1            # encoding: [0xec,0x00,0xff,0xff,0x00,0xd8]
+#CHECK: ahik	%r0, %r0, 0             # encoding: [0xec,0x00,0x00,0x00,0x00,0xd8]
+#CHECK: ahik	%r0, %r0, 1             # encoding: [0xec,0x00,0x00,0x01,0x00,0xd8]
+#CHECK: ahik	%r0, %r0, 32767         # encoding: [0xec,0x00,0x7f,0xff,0x00,0xd8]
+#CHECK: ahik	%r0, %r15, 0            # encoding: [0xec,0x0f,0x00,0x00,0x00,0xd8]
+#CHECK: ahik	%r15, %r0, 0            # encoding: [0xec,0xf0,0x00,0x00,0x00,0xd8]
+#CHECK: ahik	%r7, %r8, -16           # encoding: [0xec,0x78,0xff,0xf0,0x00,0xd8]
+
+	ahik	%r0, %r0, -32768
+	ahik	%r0, %r0, -1
+	ahik	%r0, %r0, 0
+	ahik	%r0, %r0, 1
+	ahik	%r0, %r0, 32767
+	ahik	%r0, %r15, 0
+	ahik	%r15, %r0, 0
+	ahik	%r7, %r8, -16
+
+#CHECK: alghsik	%r0, %r0, -32768        # encoding: [0xec,0x00,0x80,0x00,0x00,0xdb]
+#CHECK: alghsik	%r0, %r0, -1            # encoding: [0xec,0x00,0xff,0xff,0x00,0xdb]
+#CHECK: alghsik	%r0, %r0, 0             # encoding: [0xec,0x00,0x00,0x00,0x00,0xdb]
+#CHECK: alghsik	%r0, %r0, 1             # encoding: [0xec,0x00,0x00,0x01,0x00,0xdb]
+#CHECK: alghsik	%r0, %r0, 32767         # encoding: [0xec,0x00,0x7f,0xff,0x00,0xdb]
+#CHECK: alghsik	%r0, %r15, 0            # encoding: [0xec,0x0f,0x00,0x00,0x00,0xdb]
+#CHECK: alghsik	%r15, %r0, 0            # encoding: [0xec,0xf0,0x00,0x00,0x00,0xdb]
+#CHECK: alghsik	%r7, %r8, -16           # encoding: [0xec,0x78,0xff,0xf0,0x00,0xdb]
+
+	alghsik	%r0, %r0, -32768
+	alghsik	%r0, %r0, -1
+	alghsik	%r0, %r0, 0
+	alghsik	%r0, %r0, 1
+	alghsik	%r0, %r0, 32767
+	alghsik	%r0, %r15, 0
+	alghsik	%r15, %r0, 0
+	alghsik	%r7, %r8, -16
+
+#CHECK: algrk	%r0, %r0, %r0           # encoding: [0xb9,0xea,0x00,0x00]
+#CHECK: algrk	%r0, %r0, %r15          # encoding: [0xb9,0xea,0xf0,0x00]
+#CHECK: algrk	%r0, %r15, %r0          # encoding: [0xb9,0xea,0x00,0x0f]
+#CHECK: algrk	%r15, %r0, %r0          # encoding: [0xb9,0xea,0x00,0xf0]
+#CHECK: algrk	%r7, %r8, %r9           # encoding: [0xb9,0xea,0x90,0x78]
+
+	algrk	%r0,%r0,%r0
+	algrk	%r0,%r0,%r15
+	algrk	%r0,%r15,%r0
+	algrk	%r15,%r0,%r0
+	algrk	%r7,%r8,%r9
+
+#CHECK: alhsik	%r0, %r0, -32768        # encoding: [0xec,0x00,0x80,0x00,0x00,0xda]
+#CHECK: alhsik	%r0, %r0, -1            # encoding: [0xec,0x00,0xff,0xff,0x00,0xda]
+#CHECK: alhsik	%r0, %r0, 0             # encoding: [0xec,0x00,0x00,0x00,0x00,0xda]
+#CHECK: alhsik	%r0, %r0, 1             # encoding: [0xec,0x00,0x00,0x01,0x00,0xda]
+#CHECK: alhsik	%r0, %r0, 32767         # encoding: [0xec,0x00,0x7f,0xff,0x00,0xda]
+#CHECK: alhsik	%r0, %r15, 0            # encoding: [0xec,0x0f,0x00,0x00,0x00,0xda]
+#CHECK: alhsik	%r15, %r0, 0            # encoding: [0xec,0xf0,0x00,0x00,0x00,0xda]
+#CHECK: alhsik	%r7, %r8, -16           # encoding: [0xec,0x78,0xff,0xf0,0x00,0xda]
+
+	alhsik	%r0, %r0, -32768
+	alhsik	%r0, %r0, -1
+	alhsik	%r0, %r0, 0
+	alhsik	%r0, %r0, 1
+	alhsik	%r0, %r0, 32767
+	alhsik	%r0, %r15, 0
+	alhsik	%r15, %r0, 0
+	alhsik	%r7, %r8, -16
+
+#CHECK: alrk	%r0, %r0, %r0           # encoding: [0xb9,0xfa,0x00,0x00]
+#CHECK: alrk	%r0, %r0, %r15          # encoding: [0xb9,0xfa,0xf0,0x00]
+#CHECK: alrk	%r0, %r15, %r0          # encoding: [0xb9,0xfa,0x00,0x0f]
+#CHECK: alrk	%r15, %r0, %r0          # encoding: [0xb9,0xfa,0x00,0xf0]
+#CHECK: alrk	%r7, %r8, %r9           # encoding: [0xb9,0xfa,0x90,0x78]
+
+	alrk	%r0,%r0,%r0
+	alrk	%r0,%r0,%r15
+	alrk	%r0,%r15,%r0
+	alrk	%r15,%r0,%r0
+	alrk	%r7,%r8,%r9
+
+#CHECK: ark	%r0, %r0, %r0           # encoding: [0xb9,0xf8,0x00,0x00]
+#CHECK: ark	%r0, %r0, %r15          # encoding: [0xb9,0xf8,0xf0,0x00]
+#CHECK: ark	%r0, %r15, %r0          # encoding: [0xb9,0xf8,0x00,0x0f]
+#CHECK: ark	%r15, %r0, %r0          # encoding: [0xb9,0xf8,0x00,0xf0]
+#CHECK: ark	%r7, %r8, %r9           # encoding: [0xb9,0xf8,0x90,0x78]
+
+	ark	%r0,%r0,%r0
+	ark	%r0,%r0,%r15
+	ark	%r0,%r15,%r0
+	ark	%r15,%r0,%r0
+	ark	%r7,%r8,%r9
+
+#CHECK: loc	%r0, 0, 0               # encoding: [0xeb,0x00,0x00,0x00,0x00,0xf2]
+#CHECK: loc	%r0, 0, 15              # encoding: [0xeb,0x0f,0x00,0x00,0x00,0xf2]
+#CHECK: loc	%r0, -524288, 0         # encoding: [0xeb,0x00,0x00,0x00,0x80,0xf2]
+#CHECK: loc	%r0, 524287, 0          # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xf2]
+#CHECK: loc	%r0, 0(%r1), 0          # encoding: [0xeb,0x00,0x10,0x00,0x00,0xf2]
+#CHECK: loc	%r0, 0(%r15), 0         # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xf2]
+#CHECK: loc	%r15, 0, 0              # encoding: [0xeb,0xf0,0x00,0x00,0x00,0xf2]
+#CHECK: loc	%r1, 4095(%r2), 3       # encoding: [0xeb,0x13,0x2f,0xff,0x00,0xf2]
+
+	loc	%r0,0,0
+	loc	%r0,0,15
+	loc	%r0,-524288,0
+	loc	%r0,524287,0
+	loc	%r0,0(%r1),0
+	loc	%r0,0(%r15),0
+	loc	%r15,0,0
+	loc	%r1,4095(%r2),3
+
+#CHECK: loco   %r1, 2(%r3)              # encoding: [0xeb,0x11,0x30,0x02,0x00,0xf2]
+#CHECK: loch   %r1, 2(%r3)              # encoding: [0xeb,0x12,0x30,0x02,0x00,0xf2]
+#CHECK: locnle %r1, 2(%r3)              # encoding: [0xeb,0x13,0x30,0x02,0x00,0xf2]
+#CHECK: locl   %r1, 2(%r3)              # encoding: [0xeb,0x14,0x30,0x02,0x00,0xf2]
+#CHECK: locnhe %r1, 2(%r3)              # encoding: [0xeb,0x15,0x30,0x02,0x00,0xf2]
+#CHECK: loclh  %r1, 2(%r3)              # encoding: [0xeb,0x16,0x30,0x02,0x00,0xf2]
+#CHECK: locne  %r1, 2(%r3)              # encoding: [0xeb,0x17,0x30,0x02,0x00,0xf2]
+#CHECK: loce   %r1, 2(%r3)              # encoding: [0xeb,0x18,0x30,0x02,0x00,0xf2]
+#CHECK: locnlh %r1, 2(%r3)              # encoding: [0xeb,0x19,0x30,0x02,0x00,0xf2]
+#CHECK: loche  %r1, 2(%r3)              # encoding: [0xeb,0x1a,0x30,0x02,0x00,0xf2]
+#CHECK: locnl  %r1, 2(%r3)              # encoding: [0xeb,0x1b,0x30,0x02,0x00,0xf2]
+#CHECK: locle  %r1, 2(%r3)              # encoding: [0xeb,0x1c,0x30,0x02,0x00,0xf2]
+#CHECK: locnh  %r1, 2(%r3)              # encoding: [0xeb,0x1d,0x30,0x02,0x00,0xf2]
+#CHECK: locno  %r1, 2(%r3)              # encoding: [0xeb,0x1e,0x30,0x02,0x00,0xf2]
+
+	loco   %r1,2(%r3)
+	loch   %r1,2(%r3)
+	locnle %r1,2(%r3)
+	locl   %r1,2(%r3)
+	locnhe %r1,2(%r3)
+	loclh  %r1,2(%r3)
+	locne  %r1,2(%r3)
+	loce   %r1,2(%r3)
+	locnlh %r1,2(%r3)
+	loche  %r1,2(%r3)
+	locnl  %r1,2(%r3)
+	locle  %r1,2(%r3)
+	locnh  %r1,2(%r3)
+	locno  %r1,2(%r3)
+
+#CHECK: locg	%r0, 0, 0               # encoding: [0xeb,0x00,0x00,0x00,0x00,0xe2]
+#CHECK: locg	%r0, 0, 15              # encoding: [0xeb,0x0f,0x00,0x00,0x00,0xe2]
+#CHECK: locg	%r0, -524288, 0         # encoding: [0xeb,0x00,0x00,0x00,0x80,0xe2]
+#CHECK: locg	%r0, 524287, 0          # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xe2]
+#CHECK: locg	%r0, 0(%r1), 0          # encoding: [0xeb,0x00,0x10,0x00,0x00,0xe2]
+#CHECK: locg	%r0, 0(%r15), 0         # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xe2]
+#CHECK: locg	%r15, 0, 0              # encoding: [0xeb,0xf0,0x00,0x00,0x00,0xe2]
+#CHECK: locg	%r1, 4095(%r2), 3       # encoding: [0xeb,0x13,0x2f,0xff,0x00,0xe2]
+
+	locg	%r0,0,0
+	locg	%r0,0,15
+	locg	%r0,-524288,0
+	locg	%r0,524287,0
+	locg	%r0,0(%r1),0
+	locg	%r0,0(%r15),0
+	locg	%r15,0,0
+	locg	%r1,4095(%r2),3
+
+#CHECK: locgo   %r1, 2(%r3)             # encoding: [0xeb,0x11,0x30,0x02,0x00,0xe2]
+#CHECK: locgh   %r1, 2(%r3)             # encoding: [0xeb,0x12,0x30,0x02,0x00,0xe2]
+#CHECK: locgnle %r1, 2(%r3)             # encoding: [0xeb,0x13,0x30,0x02,0x00,0xe2]
+#CHECK: locgl   %r1, 2(%r3)             # encoding: [0xeb,0x14,0x30,0x02,0x00,0xe2]
+#CHECK: locgnhe %r1, 2(%r3)             # encoding: [0xeb,0x15,0x30,0x02,0x00,0xe2]
+#CHECK: locglh  %r1, 2(%r3)             # encoding: [0xeb,0x16,0x30,0x02,0x00,0xe2]
+#CHECK: locgne  %r1, 2(%r3)             # encoding: [0xeb,0x17,0x30,0x02,0x00,0xe2]
+#CHECK: locge   %r1, 2(%r3)             # encoding: [0xeb,0x18,0x30,0x02,0x00,0xe2]
+#CHECK: locgnlh %r1, 2(%r3)             # encoding: [0xeb,0x19,0x30,0x02,0x00,0xe2]
+#CHECK: locghe  %r1, 2(%r3)             # encoding: [0xeb,0x1a,0x30,0x02,0x00,0xe2]
+#CHECK: locgnl  %r1, 2(%r3)             # encoding: [0xeb,0x1b,0x30,0x02,0x00,0xe2]
+#CHECK: locgle  %r1, 2(%r3)             # encoding: [0xeb,0x1c,0x30,0x02,0x00,0xe2]
+#CHECK: locgnh  %r1, 2(%r3)             # encoding: [0xeb,0x1d,0x30,0x02,0x00,0xe2]
+#CHECK: locgno  %r1, 2(%r3)             # encoding: [0xeb,0x1e,0x30,0x02,0x00,0xe2]
+
+	locgo   %r1,2(%r3)
+	locgh   %r1,2(%r3)
+	locgnle %r1,2(%r3)
+	locgl   %r1,2(%r3)
+	locgnhe %r1,2(%r3)
+	locglh  %r1,2(%r3)
+	locgne  %r1,2(%r3)
+	locge   %r1,2(%r3)
+	locgnlh %r1,2(%r3)
+	locghe  %r1,2(%r3)
+	locgnl  %r1,2(%r3)
+	locgle  %r1,2(%r3)
+	locgnh  %r1,2(%r3)
+	locgno  %r1,2(%r3)
+
+#CHECK: locgr	%r1, %r2, 0             # encoding: [0xb9,0xe2,0x00,0x12]
+#CHECK: locgr	%r1, %r2, 15            # encoding: [0xb9,0xe2,0xf0,0x12]
+
+	locgr	%r1,%r2,0
+	locgr	%r1,%r2,15
+
+#CHECK: locgro   %r1, %r3               # encoding: [0xb9,0xe2,0x10,0x13]
+#CHECK: locgrh   %r1, %r3               # encoding: [0xb9,0xe2,0x20,0x13]
+#CHECK: locgrnle %r1, %r3               # encoding: [0xb9,0xe2,0x30,0x13]
+#CHECK: locgrl   %r1, %r3               # encoding: [0xb9,0xe2,0x40,0x13]
+#CHECK: locgrnhe %r1, %r3               # encoding: [0xb9,0xe2,0x50,0x13]
+#CHECK: locgrlh  %r1, %r3               # encoding: [0xb9,0xe2,0x60,0x13]
+#CHECK: locgrne  %r1, %r3               # encoding: [0xb9,0xe2,0x70,0x13]
+#CHECK: locgre   %r1, %r3               # encoding: [0xb9,0xe2,0x80,0x13]
+#CHECK: locgrnlh %r1, %r3               # encoding: [0xb9,0xe2,0x90,0x13]
+#CHECK: locgrhe  %r1, %r3               # encoding: [0xb9,0xe2,0xa0,0x13]
+#CHECK: locgrnl  %r1, %r3               # encoding: [0xb9,0xe2,0xb0,0x13]
+#CHECK: locgrle  %r1, %r3               # encoding: [0xb9,0xe2,0xc0,0x13]
+#CHECK: locgrnh  %r1, %r3               # encoding: [0xb9,0xe2,0xd0,0x13]
+#CHECK: locgrno  %r1, %r3               # encoding: [0xb9,0xe2,0xe0,0x13]
+
+	locgro   %r1,%r3
+	locgrh   %r1,%r3
+	locgrnle %r1,%r3
+	locgrl   %r1,%r3
+	locgrnhe %r1,%r3
+	locgrlh  %r1,%r3
+	locgrne  %r1,%r3
+	locgre   %r1,%r3
+	locgrnlh %r1,%r3
+	locgrhe  %r1,%r3
+	locgrnl  %r1,%r3
+	locgrle  %r1,%r3
+	locgrnh  %r1,%r3
+	locgrno  %r1,%r3
+
+#CHECK: locr	%r1, %r2, 0             # encoding: [0xb9,0xf2,0x00,0x12]
+#CHECK: locr	%r1, %r2, 15            # encoding: [0xb9,0xf2,0xf0,0x12]
+
+	locr	%r1,%r2,0
+	locr	%r1,%r2,15
+
+#CHECK: locro   %r1, %r3                # encoding: [0xb9,0xf2,0x10,0x13]
+#CHECK: locrh   %r1, %r3                # encoding: [0xb9,0xf2,0x20,0x13]
+#CHECK: locrnle %r1, %r3                # encoding: [0xb9,0xf2,0x30,0x13]
+#CHECK: locrl   %r1, %r3                # encoding: [0xb9,0xf2,0x40,0x13]
+#CHECK: locrnhe %r1, %r3                # encoding: [0xb9,0xf2,0x50,0x13]
+#CHECK: locrlh  %r1, %r3                # encoding: [0xb9,0xf2,0x60,0x13]
+#CHECK: locrne  %r1, %r3                # encoding: [0xb9,0xf2,0x70,0x13]
+#CHECK: locre   %r1, %r3                # encoding: [0xb9,0xf2,0x80,0x13]
+#CHECK: locrnlh %r1, %r3                # encoding: [0xb9,0xf2,0x90,0x13]
+#CHECK: locrhe  %r1, %r3                # encoding: [0xb9,0xf2,0xa0,0x13]
+#CHECK: locrnl  %r1, %r3                # encoding: [0xb9,0xf2,0xb0,0x13]
+#CHECK: locrle  %r1, %r3                # encoding: [0xb9,0xf2,0xc0,0x13]
+#CHECK: locrnh  %r1, %r3                # encoding: [0xb9,0xf2,0xd0,0x13]
+#CHECK: locrno  %r1, %r3                # encoding: [0xb9,0xf2,0xe0,0x13]
+
+	locro   %r1,%r3
+	locrh   %r1,%r3
+	locrnle %r1,%r3
+	locrl   %r1,%r3
+	locrnhe %r1,%r3
+	locrlh  %r1,%r3
+	locrne  %r1,%r3
+	locre   %r1,%r3
+	locrnlh %r1,%r3
+	locrhe  %r1,%r3
+	locrnl  %r1,%r3
+	locrle  %r1,%r3
+	locrnh  %r1,%r3
+	locrno  %r1,%r3
+
+#CHECK: ngrk	%r0, %r0, %r0           # encoding: [0xb9,0xe4,0x00,0x00]
+#CHECK: ngrk	%r0, %r0, %r15          # encoding: [0xb9,0xe4,0xf0,0x00]
+#CHECK: ngrk	%r0, %r15, %r0          # encoding: [0xb9,0xe4,0x00,0x0f]
+#CHECK: ngrk	%r15, %r0, %r0          # encoding: [0xb9,0xe4,0x00,0xf0]
+#CHECK: ngrk	%r7, %r8, %r9           # encoding: [0xb9,0xe4,0x90,0x78]
+
+	ngrk	%r0,%r0,%r0
+	ngrk	%r0,%r0,%r15
+	ngrk	%r0,%r15,%r0
+	ngrk	%r15,%r0,%r0
+	ngrk	%r7,%r8,%r9
+
+#CHECK: nrk	%r0, %r0, %r0           # encoding: [0xb9,0xf4,0x00,0x00]
+#CHECK: nrk	%r0, %r0, %r15          # encoding: [0xb9,0xf4,0xf0,0x00]
+#CHECK: nrk	%r0, %r15, %r0          # encoding: [0xb9,0xf4,0x00,0x0f]
+#CHECK: nrk	%r15, %r0, %r0          # encoding: [0xb9,0xf4,0x00,0xf0]
+#CHECK: nrk	%r7, %r8, %r9           # encoding: [0xb9,0xf4,0x90,0x78]
+
+	nrk	%r0,%r0,%r0
+	nrk	%r0,%r0,%r15
+	nrk	%r0,%r15,%r0
+	nrk	%r15,%r0,%r0
+	nrk	%r7,%r8,%r9
+
+#CHECK: ogrk	%r0, %r0, %r0           # encoding: [0xb9,0xe6,0x00,0x00]
+#CHECK: ogrk	%r0, %r0, %r15          # encoding: [0xb9,0xe6,0xf0,0x00]
+#CHECK: ogrk	%r0, %r15, %r0          # encoding: [0xb9,0xe6,0x00,0x0f]
+#CHECK: ogrk	%r15, %r0, %r0          # encoding: [0xb9,0xe6,0x00,0xf0]
+#CHECK: ogrk	%r7, %r8, %r9           # encoding: [0xb9,0xe6,0x90,0x78]
+
+	ogrk	%r0,%r0,%r0
+	ogrk	%r0,%r0,%r15
+	ogrk	%r0,%r15,%r0
+	ogrk	%r15,%r0,%r0
+	ogrk	%r7,%r8,%r9
+
+#CHECK: ork	%r0, %r0, %r0           # encoding: [0xb9,0xf6,0x00,0x00]
+#CHECK: ork	%r0, %r0, %r15          # encoding: [0xb9,0xf6,0xf0,0x00]
+#CHECK: ork	%r0, %r15, %r0          # encoding: [0xb9,0xf6,0x00,0x0f]
+#CHECK: ork	%r15, %r0, %r0          # encoding: [0xb9,0xf6,0x00,0xf0]
+#CHECK: ork	%r7, %r8, %r9           # encoding: [0xb9,0xf6,0x90,0x78]
+
+	ork	%r0,%r0,%r0
+	ork	%r0,%r0,%r15
+	ork	%r0,%r15,%r0
+	ork	%r15,%r0,%r0
+	ork	%r7,%r8,%r9
+
+#CHECK: risbhg	%r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x5d]
+#CHECK: risbhg	%r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x5d]
+#CHECK: risbhg	%r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x5d]
+#CHECK: risbhg	%r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x5d]
+#CHECK: risbhg	%r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x5d]
+#CHECK: risbhg	%r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x5d]
+#CHECK: risbhg	%r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x5d]
+
+	risbhg	%r0,%r0,0,0,0
+	risbhg	%r0,%r0,0,0,63
+	risbhg	%r0,%r0,0,255,0
+	risbhg	%r0,%r0,255,0,0
+	risbhg	%r0,%r15,0,0,0
+	risbhg	%r15,%r0,0,0,0
+	risbhg	%r4,%r5,6,7,8
+
+#CHECK: risblg	%r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x51]
+#CHECK: risblg	%r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x51]
+#CHECK: risblg	%r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x51]
+#CHECK: risblg	%r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x51]
+#CHECK: risblg	%r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x51]
+#CHECK: risblg	%r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x51]
+#CHECK: risblg	%r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x51]
+
+	risblg	%r0,%r0,0,0,0
+	risblg	%r0,%r0,0,0,63
+	risblg	%r0,%r0,0,255,0
+	risblg	%r0,%r0,255,0,0
+	risblg	%r0,%r15,0,0,0
+	risblg	%r15,%r0,0,0,0
+	risblg	%r4,%r5,6,7,8
+
+#CHECK: sgrk	%r0, %r0, %r0           # encoding: [0xb9,0xe9,0x00,0x00]
+#CHECK: sgrk	%r0, %r0, %r15          # encoding: [0xb9,0xe9,0xf0,0x00]
+#CHECK: sgrk	%r0, %r15, %r0          # encoding: [0xb9,0xe9,0x00,0x0f]
+#CHECK: sgrk	%r15, %r0, %r0          # encoding: [0xb9,0xe9,0x00,0xf0]
+#CHECK: sgrk	%r7, %r8, %r9           # encoding: [0xb9,0xe9,0x90,0x78]
+
+	sgrk	%r0,%r0,%r0
+	sgrk	%r0,%r0,%r15
+	sgrk	%r0,%r15,%r0
+	sgrk	%r15,%r0,%r0
+	sgrk	%r7,%r8,%r9
+
+#CHECK: slgrk	%r0, %r0, %r0           # encoding: [0xb9,0xeb,0x00,0x00]
+#CHECK: slgrk	%r0, %r0, %r15          # encoding: [0xb9,0xeb,0xf0,0x00]
+#CHECK: slgrk	%r0, %r15, %r0          # encoding: [0xb9,0xeb,0x00,0x0f]
+#CHECK: slgrk	%r15, %r0, %r0          # encoding: [0xb9,0xeb,0x00,0xf0]
+#CHECK: slgrk	%r7, %r8, %r9           # encoding: [0xb9,0xeb,0x90,0x78]
+
+	slgrk	%r0,%r0,%r0
+	slgrk	%r0,%r0,%r15
+	slgrk	%r0,%r15,%r0
+	slgrk	%r15,%r0,%r0
+	slgrk	%r7,%r8,%r9
+
+#CHECK: slrk	%r0, %r0, %r0           # encoding: [0xb9,0xfb,0x00,0x00]
+#CHECK: slrk	%r0, %r0, %r15          # encoding: [0xb9,0xfb,0xf0,0x00]
+#CHECK: slrk	%r0, %r15, %r0          # encoding: [0xb9,0xfb,0x00,0x0f]
+#CHECK: slrk	%r15, %r0, %r0          # encoding: [0xb9,0xfb,0x00,0xf0]
+#CHECK: slrk	%r7, %r8, %r9           # encoding: [0xb9,0xfb,0x90,0x78]
+
+	slrk	%r0,%r0,%r0
+	slrk	%r0,%r0,%r15
+	slrk	%r0,%r15,%r0
+	slrk	%r15,%r0,%r0
+	slrk	%r7,%r8,%r9
+
+#CHECK: sllk	%r0, %r0, 0             # encoding: [0xeb,0x00,0x00,0x00,0x00,0xdf]
+#CHECK: sllk	%r15, %r1, 0            # encoding: [0xeb,0xf1,0x00,0x00,0x00,0xdf]
+#CHECK: sllk	%r1, %r15, 0            # encoding: [0xeb,0x1f,0x00,0x00,0x00,0xdf]
+#CHECK: sllk	%r15, %r15, 0           # encoding: [0xeb,0xff,0x00,0x00,0x00,0xdf]
+#CHECK: sllk	%r0, %r0, -524288       # encoding: [0xeb,0x00,0x00,0x00,0x80,0xdf]
+#CHECK: sllk	%r0, %r0, -1            # encoding: [0xeb,0x00,0x0f,0xff,0xff,0xdf]
+#CHECK: sllk	%r0, %r0, 1             # encoding: [0xeb,0x00,0x00,0x01,0x00,0xdf]
+#CHECK: sllk	%r0, %r0, 524287        # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xdf]
+#CHECK: sllk	%r0, %r0, 0(%r1)        # encoding: [0xeb,0x00,0x10,0x00,0x00,0xdf]
+#CHECK: sllk	%r0, %r0, 0(%r15)       # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xdf]
+#CHECK: sllk	%r0, %r0, 524287(%r1)   # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0xdf]
+#CHECK: sllk	%r0, %r0, 524287(%r15)  # encoding: [0xeb,0x00,0xff,0xff,0x7f,0xdf]
+
+	sllk	%r0,%r0,0
+	sllk	%r15,%r1,0
+	sllk	%r1,%r15,0
+	sllk	%r15,%r15,0
+	sllk	%r0,%r0,-524288
+	sllk	%r0,%r0,-1
+	sllk	%r0,%r0,1
+	sllk	%r0,%r0,524287
+	sllk	%r0,%r0,0(%r1)
+	sllk	%r0,%r0,0(%r15)
+	sllk	%r0,%r0,524287(%r1)
+	sllk	%r0,%r0,524287(%r15)
+
+#CHECK: srak	%r0, %r0, 0             # encoding: [0xeb,0x00,0x00,0x00,0x00,0xdc]
+#CHECK: srak	%r15, %r1, 0            # encoding: [0xeb,0xf1,0x00,0x00,0x00,0xdc]
+#CHECK: srak	%r1, %r15, 0            # encoding: [0xeb,0x1f,0x00,0x00,0x00,0xdc]
+#CHECK: srak	%r15, %r15, 0           # encoding: [0xeb,0xff,0x00,0x00,0x00,0xdc]
+#CHECK: srak	%r0, %r0, -524288       # encoding: [0xeb,0x00,0x00,0x00,0x80,0xdc]
+#CHECK: srak	%r0, %r0, -1            # encoding: [0xeb,0x00,0x0f,0xff,0xff,0xdc]
+#CHECK: srak	%r0, %r0, 1             # encoding: [0xeb,0x00,0x00,0x01,0x00,0xdc]
+#CHECK: srak	%r0, %r0, 524287        # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xdc]
+#CHECK: srak	%r0, %r0, 0(%r1)        # encoding: [0xeb,0x00,0x10,0x00,0x00,0xdc]
+#CHECK: srak	%r0, %r0, 0(%r15)       # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xdc]
+#CHECK: srak	%r0, %r0, 524287(%r1)   # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0xdc]
+#CHECK: srak	%r0, %r0, 524287(%r15)  # encoding: [0xeb,0x00,0xff,0xff,0x7f,0xdc]
+
+	srak	%r0,%r0,0
+	srak	%r15,%r1,0
+	srak	%r1,%r15,0
+	srak	%r15,%r15,0
+	srak	%r0,%r0,-524288
+	srak	%r0,%r0,-1
+	srak	%r0,%r0,1
+	srak	%r0,%r0,524287
+	srak	%r0,%r0,0(%r1)
+	srak	%r0,%r0,0(%r15)
+	srak	%r0,%r0,524287(%r1)
+	srak	%r0,%r0,524287(%r15)
+
+#CHECK: srk	%r0, %r0, %r0           # encoding: [0xb9,0xf9,0x00,0x00]
+#CHECK: srk	%r0, %r0, %r15          # encoding: [0xb9,0xf9,0xf0,0x00]
+#CHECK: srk	%r0, %r15, %r0          # encoding: [0xb9,0xf9,0x00,0x0f]
+#CHECK: srk	%r15, %r0, %r0          # encoding: [0xb9,0xf9,0x00,0xf0]
+#CHECK: srk	%r7, %r8, %r9           # encoding: [0xb9,0xf9,0x90,0x78]
+
+	srk	%r0,%r0,%r0
+	srk	%r0,%r0,%r15
+	srk	%r0,%r15,%r0
+	srk	%r15,%r0,%r0
+	srk	%r7,%r8,%r9
+
+#CHECK: srlk	%r0, %r0, 0             # encoding: [0xeb,0x00,0x00,0x00,0x00,0xde]
+#CHECK: srlk	%r15, %r1, 0            # encoding: [0xeb,0xf1,0x00,0x00,0x00,0xde]
+#CHECK: srlk	%r1, %r15, 0            # encoding: [0xeb,0x1f,0x00,0x00,0x00,0xde]
+#CHECK: srlk	%r15, %r15, 0           # encoding: [0xeb,0xff,0x00,0x00,0x00,0xde]
+#CHECK: srlk	%r0, %r0, -524288       # encoding: [0xeb,0x00,0x00,0x00,0x80,0xde]
+#CHECK: srlk	%r0, %r0, -1            # encoding: [0xeb,0x00,0x0f,0xff,0xff,0xde]
+#CHECK: srlk	%r0, %r0, 1             # encoding: [0xeb,0x00,0x00,0x01,0x00,0xde]
+#CHECK: srlk	%r0, %r0, 524287        # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xde]
+#CHECK: srlk	%r0, %r0, 0(%r1)        # encoding: [0xeb,0x00,0x10,0x00,0x00,0xde]
+#CHECK: srlk	%r0, %r0, 0(%r15)       # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xde]
+#CHECK: srlk	%r0, %r0, 524287(%r1)   # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0xde]
+#CHECK: srlk	%r0, %r0, 524287(%r15)  # encoding: [0xeb,0x00,0xff,0xff,0x7f,0xde]
+
+	srlk	%r0,%r0,0
+	srlk	%r15,%r1,0
+	srlk	%r1,%r15,0
+	srlk	%r15,%r15,0
+	srlk	%r0,%r0,-524288
+	srlk	%r0,%r0,-1
+	srlk	%r0,%r0,1
+	srlk	%r0,%r0,524287
+	srlk	%r0,%r0,0(%r1)
+	srlk	%r0,%r0,0(%r15)
+	srlk	%r0,%r0,524287(%r1)
+	srlk	%r0,%r0,524287(%r15)
+
+#CHECK: stoc	%r0, 0, 0               # encoding: [0xeb,0x00,0x00,0x00,0x00,0xf3]
+#CHECK: stoc	%r0, 0, 15              # encoding: [0xeb,0x0f,0x00,0x00,0x00,0xf3]
+#CHECK: stoc	%r0, -524288, 0         # encoding: [0xeb,0x00,0x00,0x00,0x80,0xf3]
+#CHECK: stoc	%r0, 524287, 0          # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xf3]
+#CHECK: stoc	%r0, 0(%r1), 0          # encoding: [0xeb,0x00,0x10,0x00,0x00,0xf3]
+#CHECK: stoc	%r0, 0(%r15), 0         # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xf3]
+#CHECK: stoc	%r15, 0, 0              # encoding: [0xeb,0xf0,0x00,0x00,0x00,0xf3]
+#CHECK: stoc	%r1, 4095(%r2), 3       # encoding: [0xeb,0x13,0x2f,0xff,0x00,0xf3]
+
+	stoc	%r0,0,0
+	stoc	%r0,0,15
+	stoc	%r0,-524288,0
+	stoc	%r0,524287,0
+	stoc	%r0,0(%r1),0
+	stoc	%r0,0(%r15),0
+	stoc	%r15,0,0
+	stoc	%r1,4095(%r2),3
+
+#CHECK: stoco   %r1, 2(%r3)             # encoding: [0xeb,0x11,0x30,0x02,0x00,0xf3]
+#CHECK: stoch   %r1, 2(%r3)             # encoding: [0xeb,0x12,0x30,0x02,0x00,0xf3]
+#CHECK: stocnle %r1, 2(%r3)             # encoding: [0xeb,0x13,0x30,0x02,0x00,0xf3]
+#CHECK: stocl   %r1, 2(%r3)             # encoding: [0xeb,0x14,0x30,0x02,0x00,0xf3]
+#CHECK: stocnhe %r1, 2(%r3)             # encoding: [0xeb,0x15,0x30,0x02,0x00,0xf3]
+#CHECK: stoclh  %r1, 2(%r3)             # encoding: [0xeb,0x16,0x30,0x02,0x00,0xf3]
+#CHECK: stocne  %r1, 2(%r3)             # encoding: [0xeb,0x17,0x30,0x02,0x00,0xf3]
+#CHECK: stoce   %r1, 2(%r3)             # encoding: [0xeb,0x18,0x30,0x02,0x00,0xf3]
+#CHECK: stocnlh %r1, 2(%r3)             # encoding: [0xeb,0x19,0x30,0x02,0x00,0xf3]
+#CHECK: stoche  %r1, 2(%r3)             # encoding: [0xeb,0x1a,0x30,0x02,0x00,0xf3]
+#CHECK: stocnl  %r1, 2(%r3)             # encoding: [0xeb,0x1b,0x30,0x02,0x00,0xf3]
+#CHECK: stocle  %r1, 2(%r3)             # encoding: [0xeb,0x1c,0x30,0x02,0x00,0xf3]
+#CHECK: stocnh  %r1, 2(%r3)             # encoding: [0xeb,0x1d,0x30,0x02,0x00,0xf3]
+#CHECK: stocno  %r1, 2(%r3)             # encoding: [0xeb,0x1e,0x30,0x02,0x00,0xf3]
+
+	stoco   %r1,2(%r3)
+	stoch   %r1,2(%r3)
+	stocnle %r1,2(%r3)
+	stocl   %r1,2(%r3)
+	stocnhe %r1,2(%r3)
+	stoclh  %r1,2(%r3)
+	stocne  %r1,2(%r3)
+	stoce   %r1,2(%r3)
+	stocnlh %r1,2(%r3)
+	stoche  %r1,2(%r3)
+	stocnl  %r1,2(%r3)
+	stocle  %r1,2(%r3)
+	stocnh  %r1,2(%r3)
+	stocno  %r1,2(%r3)
+
+#CHECK: stocg	%r0, 0, 0               # encoding: [0xeb,0x00,0x00,0x00,0x00,0xe3]
+#CHECK: stocg	%r0, 0, 15              # encoding: [0xeb,0x0f,0x00,0x00,0x00,0xe3]
+#CHECK: stocg	%r0, -524288, 0         # encoding: [0xeb,0x00,0x00,0x00,0x80,0xe3]
+#CHECK: stocg	%r0, 524287, 0          # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0xe3]
+#CHECK: stocg	%r0, 0(%r1), 0          # encoding: [0xeb,0x00,0x10,0x00,0x00,0xe3]
+#CHECK: stocg	%r0, 0(%r15), 0         # encoding: [0xeb,0x00,0xf0,0x00,0x00,0xe3]
+#CHECK: stocg	%r15, 0, 0              # encoding: [0xeb,0xf0,0x00,0x00,0x00,0xe3]
+#CHECK: stocg	%r1, 4095(%r2), 3       # encoding: [0xeb,0x13,0x2f,0xff,0x00,0xe3]
+
+	stocg	%r0,0,0
+	stocg	%r0,0,15
+	stocg	%r0,-524288,0
+	stocg	%r0,524287,0
+	stocg	%r0,0(%r1),0
+	stocg	%r0,0(%r15),0
+	stocg	%r15,0,0
+	stocg	%r1,4095(%r2),3
+
+#CHECK: stocgo   %r1, 2(%r3)            # encoding: [0xeb,0x11,0x30,0x02,0x00,0xe3]
+#CHECK: stocgh   %r1, 2(%r3)            # encoding: [0xeb,0x12,0x30,0x02,0x00,0xe3]
+#CHECK: stocgnle %r1, 2(%r3)            # encoding: [0xeb,0x13,0x30,0x02,0x00,0xe3]
+#CHECK: stocgl   %r1, 2(%r3)            # encoding: [0xeb,0x14,0x30,0x02,0x00,0xe3]
+#CHECK: stocgnhe %r1, 2(%r3)            # encoding: [0xeb,0x15,0x30,0x02,0x00,0xe3]
+#CHECK: stocglh  %r1, 2(%r3)            # encoding: [0xeb,0x16,0x30,0x02,0x00,0xe3]
+#CHECK: stocgne  %r1, 2(%r3)            # encoding: [0xeb,0x17,0x30,0x02,0x00,0xe3]
+#CHECK: stocge   %r1, 2(%r3)            # encoding: [0xeb,0x18,0x30,0x02,0x00,0xe3]
+#CHECK: stocgnlh %r1, 2(%r3)            # encoding: [0xeb,0x19,0x30,0x02,0x00,0xe3]
+#CHECK: stocghe  %r1, 2(%r3)            # encoding: [0xeb,0x1a,0x30,0x02,0x00,0xe3]
+#CHECK: stocgnl  %r1, 2(%r3)            # encoding: [0xeb,0x1b,0x30,0x02,0x00,0xe3]
+#CHECK: stocgle  %r1, 2(%r3)            # encoding: [0xeb,0x1c,0x30,0x02,0x00,0xe3]
+#CHECK: stocgnh  %r1, 2(%r3)            # encoding: [0xeb,0x1d,0x30,0x02,0x00,0xe3]
+#CHECK: stocgno  %r1, 2(%r3)            # encoding: [0xeb,0x1e,0x30,0x02,0x00,0xe3]
+
+	stocgo   %r1,2(%r3)
+	stocgh   %r1,2(%r3)
+	stocgnle %r1,2(%r3)
+	stocgl   %r1,2(%r3)
+	stocgnhe %r1,2(%r3)
+	stocglh  %r1,2(%r3)
+	stocgne  %r1,2(%r3)
+	stocge   %r1,2(%r3)
+	stocgnlh %r1,2(%r3)
+	stocghe  %r1,2(%r3)
+	stocgnl  %r1,2(%r3)
+	stocgle  %r1,2(%r3)
+	stocgnh  %r1,2(%r3)
+	stocgno  %r1,2(%r3)
+
+#CHECK: xgrk	%r0, %r0, %r0           # encoding: [0xb9,0xe7,0x00,0x00]
+#CHECK: xgrk	%r0, %r0, %r15          # encoding: [0xb9,0xe7,0xf0,0x00]
+#CHECK: xgrk	%r0, %r15, %r0          # encoding: [0xb9,0xe7,0x00,0x0f]
+#CHECK: xgrk	%r15, %r0, %r0          # encoding: [0xb9,0xe7,0x00,0xf0]
+#CHECK: xgrk	%r7, %r8, %r9           # encoding: [0xb9,0xe7,0x90,0x78]
+
+	xgrk	%r0,%r0,%r0
+	xgrk	%r0,%r0,%r15
+	xgrk	%r0,%r15,%r0
+	xgrk	%r15,%r0,%r0
+	xgrk	%r7,%r8,%r9
+
+#CHECK: xrk	%r0, %r0, %r0           # encoding: [0xb9,0xf7,0x00,0x00]
+#CHECK: xrk	%r0, %r0, %r15          # encoding: [0xb9,0xf7,0xf0,0x00]
+#CHECK: xrk	%r0, %r15, %r0          # encoding: [0xb9,0xf7,0x00,0x0f]
+#CHECK: xrk	%r15, %r0, %r0          # encoding: [0xb9,0xf7,0x00,0xf0]
+#CHECK: xrk	%r7, %r8, %r9           # encoding: [0xb9,0xf7,0x90,0x78]
+
+	xrk	%r0,%r0,%r0
+	xrk	%r0,%r0,%r15
+	xrk	%r0,%r15,%r0
+	xrk	%r15,%r0,%r0
+	xrk	%r7,%r8,%r9
diff --git a/test/MC/SystemZ/insn-good.s b/test/MC/SystemZ/insn-good.s
index 17af858..c997271 100644
--- a/test/MC/SystemZ/insn-good.s
+++ b/test/MC/SystemZ/insn-good.s
@@ -1,3 +1,4 @@
+# For z10 and above.
 # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s
 
 #CHECK: a	%r0, 0                  # encoding: [0x5a,0x00,0x00,0x00]
@@ -1121,6 +1122,38 @@
 #CHECK:  fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL
 	jg	bar@PLT
 
+#CHECK: brct	%r0, .[[LAB:L.*]]-65536	# encoding: [0xa7,0x06,A,A]
+#CHECK:  fixup A - offset: 2, value: (.[[LAB]]-65536)+2, kind: FK_390_PC16DBL
+	brct	%r0, -0x10000
+#CHECK: brct	%r0, .[[LAB:L.*]]-2	# encoding: [0xa7,0x06,A,A]
+#CHECK:  fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC16DBL
+	brct	%r0, -2
+#CHECK: brct	%r0, .[[LAB:L.*]]	# encoding: [0xa7,0x06,A,A]
+#CHECK:  fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC16DBL
+	brct	%r0, 0
+#CHECK: brct	%r0, .[[LAB:L.*]]+65534	# encoding: [0xa7,0x06,A,A]
+#CHECK:  fixup A - offset: 2, value: (.[[LAB]]+65534)+2, kind: FK_390_PC16DBL
+	brct	%r0, 0xfffe
+#CHECK: brct	%r15, .[[LAB:L.*]]	# encoding: [0xa7,0xf6,A,A]
+#CHECK:  fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC16DBL
+	brct	%r15, 0
+
+#CHECK: brctg	%r0, .[[LAB:L.*]]-65536	# encoding: [0xa7,0x07,A,A]
+#CHECK:  fixup A - offset: 2, value: (.[[LAB]]-65536)+2, kind: FK_390_PC16DBL
+	brctg	%r0, -0x10000
+#CHECK: brctg	%r0, .[[LAB:L.*]]-2	# encoding: [0xa7,0x07,A,A]
+#CHECK:  fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC16DBL
+	brctg	%r0, -2
+#CHECK: brctg	%r0, .[[LAB:L.*]]	# encoding: [0xa7,0x07,A,A]
+#CHECK:  fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC16DBL
+	brctg	%r0, 0
+#CHECK: brctg	%r0, .[[LAB:L.*]]+65534	# encoding: [0xa7,0x07,A,A]
+#CHECK:  fixup A - offset: 2, value: (.[[LAB]]+65534)+2, kind: FK_390_PC16DBL
+	brctg	%r0, 0xfffe
+#CHECK: brctg	%r15, .[[LAB:L.*]]	# encoding: [0xa7,0xf7,A,A]
+#CHECK:  fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC16DBL
+	brctg	%r15, 0
+
 #CHECK: c	%r0, 0                  # encoding: [0x59,0x00,0x00,0x00]
 #CHECK: c	%r0, 4095               # encoding: [0x59,0x00,0x0f,0xff]
 #CHECK: c	%r0, 0(%r1)             # encoding: [0x59,0x00,0x10,0x00]
@@ -4805,6 +4838,132 @@
 	lrvr	%r7,%r8
 	lrvr	%r15,%r15
 
+#CHECK: lt	%r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x12]
+#CHECK: lt	%r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x12]
+#CHECK: lt	%r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x12]
+#CHECK: lt	%r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x12]
+#CHECK: lt	%r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x12]
+#CHECK: lt	%r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x12]
+#CHECK: lt	%r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x12]
+#CHECK: lt	%r0, 524287(%r1,%r15)   # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x12]
+#CHECK: lt	%r0, 524287(%r15,%r1)   # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x12]
+#CHECK: lt	%r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x12]
+
+	lt	%r0, -524288
+	lt	%r0, -1
+	lt	%r0, 0
+	lt	%r0, 1
+	lt	%r0, 524287
+	lt	%r0, 0(%r1)
+	lt	%r0, 0(%r15)
+	lt	%r0, 524287(%r1,%r15)
+	lt	%r0, 524287(%r15,%r1)
+	lt	%r15, 0
+
+#CHECK: ltg	%r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x02]
+#CHECK: ltg	%r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x02]
+#CHECK: ltg	%r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x02]
+#CHECK: ltg	%r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x02]
+#CHECK: ltg	%r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x02]
+#CHECK: ltg	%r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x02]
+#CHECK: ltg	%r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x02]
+#CHECK: ltg	%r0, 524287(%r1,%r15)   # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x02]
+#CHECK: ltg	%r0, 524287(%r15,%r1)   # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x02]
+#CHECK: ltg	%r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x02]
+
+	ltg	%r0, -524288
+	ltg	%r0, -1
+	ltg	%r0, 0
+	ltg	%r0, 1
+	ltg	%r0, 524287
+	ltg	%r0, 0(%r1)
+	ltg	%r0, 0(%r15)
+	ltg	%r0, 524287(%r1,%r15)
+	ltg	%r0, 524287(%r15,%r1)
+	ltg	%r15, 0
+
+#CHECK: ltgf	%r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x32]
+#CHECK: ltgf	%r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x32]
+#CHECK: ltgf	%r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x32]
+#CHECK: ltgf	%r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x32]
+#CHECK: ltgf	%r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x32]
+#CHECK: ltgf	%r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x32]
+#CHECK: ltgf	%r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x32]
+#CHECK: ltgf	%r0, 524287(%r1,%r15)   # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x32]
+#CHECK: ltgf	%r0, 524287(%r15,%r1)   # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x32]
+#CHECK: ltgf	%r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x32]
+
+	ltgf	%r0, -524288
+	ltgf	%r0, -1
+	ltgf	%r0, 0
+	ltgf	%r0, 1
+	ltgf	%r0, 524287
+	ltgf	%r0, 0(%r1)
+	ltgf	%r0, 0(%r15)
+	ltgf	%r0, 524287(%r1,%r15)
+	ltgf	%r0, 524287(%r15,%r1)
+	ltgf	%r15, 0
+
+#CHECK: ltdbr	%f0, %f9                # encoding: [0xb3,0x12,0x00,0x09]
+#CHECK: ltdbr	%f0, %f15               # encoding: [0xb3,0x12,0x00,0x0f]
+#CHECK: ltdbr	%f15, %f0               # encoding: [0xb3,0x12,0x00,0xf0]
+#CHECK: ltdbr	%f15, %f9               # encoding: [0xb3,0x12,0x00,0xf9]
+
+	ltdbr	%f0,%f9
+	ltdbr	%f0,%f15
+	ltdbr	%f15,%f0
+	ltdbr	%f15,%f9
+
+#CHECK: ltebr	%f0, %f9                # encoding: [0xb3,0x02,0x00,0x09]
+#CHECK: ltebr	%f0, %f15               # encoding: [0xb3,0x02,0x00,0x0f]
+#CHECK: ltebr	%f15, %f0               # encoding: [0xb3,0x02,0x00,0xf0]
+#CHECK: ltebr	%f15, %f9               # encoding: [0xb3,0x02,0x00,0xf9]
+
+	ltebr	%f0,%f9
+	ltebr	%f0,%f15
+	ltebr	%f15,%f0
+	ltebr	%f15,%f9
+
+#CHECK: ltgfr	%r0, %r9                # encoding: [0xb9,0x12,0x00,0x09]
+#CHECK: ltgfr	%r0, %r15               # encoding: [0xb9,0x12,0x00,0x0f]
+#CHECK: ltgfr	%r15, %r0               # encoding: [0xb9,0x12,0x00,0xf0]
+#CHECK: ltgfr	%r15, %r9               # encoding: [0xb9,0x12,0x00,0xf9]
+
+	ltgfr	%r0,%r9
+	ltgfr	%r0,%r15
+	ltgfr	%r15,%r0
+	ltgfr	%r15,%r9
+
+#CHECK: ltgr	%r0, %r9                # encoding: [0xb9,0x02,0x00,0x09]
+#CHECK: ltgr	%r0, %r15               # encoding: [0xb9,0x02,0x00,0x0f]
+#CHECK: ltgr	%r15, %r0               # encoding: [0xb9,0x02,0x00,0xf0]
+#CHECK: ltgr	%r15, %r9               # encoding: [0xb9,0x02,0x00,0xf9]
+
+	ltgr	%r0,%r9
+	ltgr	%r0,%r15
+	ltgr	%r15,%r0
+	ltgr	%r15,%r9
+
+#CHECK: ltr	%r0, %r9                # encoding: [0x12,0x09]
+#CHECK: ltr	%r0, %r15               # encoding: [0x12,0x0f]
+#CHECK: ltr	%r15, %r0               # encoding: [0x12,0xf0]
+#CHECK: ltr	%r15, %r9               # encoding: [0x12,0xf9]
+
+	ltr	%r0,%r9
+	ltr	%r0,%r15
+	ltr	%r15,%r0
+	ltr	%r15,%r9
+
+#CHECK: ltxbr	%f0, %f9                # encoding: [0xb3,0x42,0x00,0x09]
+#CHECK: ltxbr	%f0, %f13               # encoding: [0xb3,0x42,0x00,0x0d]
+#CHECK: ltxbr	%f13, %f0               # encoding: [0xb3,0x42,0x00,0xd0]
+#CHECK: ltxbr	%f13, %f9               # encoding: [0xb3,0x42,0x00,0xd9]
+
+	ltxbr	%f0,%f9
+	ltxbr	%f0,%f13
+	ltxbr	%f13,%f0
+	ltxbr	%f13,%f9
+
 #CHECK: lxr	%f0, %f8                # encoding: [0xb3,0x65,0x00,0x08]
 #CHECK: lxr	%f0, %f13               # encoding: [0xb3,0x65,0x00,0x0d]
 #CHECK: lxr	%f13, %f0               # encoding: [0xb3,0x65,0x00,0xd0]
@@ -5313,6 +5472,32 @@
 	msy	%r0, 524287(%r15,%r1)
 	msy	%r15, 0
 
+#CHECK: mvc	0(1), 0                 # encoding: [0xd2,0x00,0x00,0x00,0x00,0x00]
+#CHECK: mvc	0(1), 0(%r1)            # encoding: [0xd2,0x00,0x00,0x00,0x10,0x00]
+#CHECK: mvc	0(1), 0(%r15)           # encoding: [0xd2,0x00,0x00,0x00,0xf0,0x00]
+#CHECK: mvc	0(1), 4095              # encoding: [0xd2,0x00,0x00,0x00,0x0f,0xff]
+#CHECK: mvc	0(1), 4095(%r1)         # encoding: [0xd2,0x00,0x00,0x00,0x1f,0xff]
+#CHECK: mvc	0(1), 4095(%r15)        # encoding: [0xd2,0x00,0x00,0x00,0xff,0xff]
+#CHECK: mvc	0(1,%r1), 0             # encoding: [0xd2,0x00,0x10,0x00,0x00,0x00]
+#CHECK: mvc	0(1,%r15), 0            # encoding: [0xd2,0x00,0xf0,0x00,0x00,0x00]
+#CHECK: mvc	4095(1,%r1), 0          # encoding: [0xd2,0x00,0x1f,0xff,0x00,0x00]
+#CHECK: mvc	4095(1,%r15), 0         # encoding: [0xd2,0x00,0xff,0xff,0x00,0x00]
+#CHECK: mvc	0(256,%r1), 0           # encoding: [0xd2,0xff,0x10,0x00,0x00,0x00]
+#CHECK: mvc	0(256,%r15), 0          # encoding: [0xd2,0xff,0xf0,0x00,0x00,0x00]
+
+	mvc	0(1), 0
+	mvc	0(1), 0(%r1)
+	mvc	0(1), 0(%r15)
+	mvc	0(1), 4095
+	mvc	0(1), 4095(%r1)
+	mvc	0(1), 4095(%r15)
+	mvc	0(1,%r1), 0
+	mvc	0(1,%r15), 0
+	mvc	4095(1,%r1), 0
+	mvc	4095(1,%r15), 0
+	mvc	0(256,%r1), 0
+	mvc	0(256,%r15), 0
+
 #CHECK: mvghi	0, 0                    # encoding: [0xe5,0x48,0x00,0x00,0x00,0x00]
 #CHECK: mvghi	4095, 0                 # encoding: [0xe5,0x48,0x0f,0xff,0x00,0x00]
 #CHECK: mvghi	0, -32768               # encoding: [0xe5,0x48,0x00,0x00,0x80,0x00]
@@ -5809,20 +5994,68 @@
 
 #CHECK: risbg	%r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x55]
 #CHECK: risbg	%r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x55]
-#CHECK: risbg	%r0, %r0, 0, 63, 0      # encoding: [0xec,0x00,0x00,0x3f,0x00,0x55]
-#CHECK: risbg	%r0, %r0, 63, 0, 0      # encoding: [0xec,0x00,0x3f,0x00,0x00,0x55]
+#CHECK: risbg	%r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x55]
+#CHECK: risbg	%r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x55]
 #CHECK: risbg	%r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x55]
 #CHECK: risbg	%r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x55]
 #CHECK: risbg	%r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x55]
 
 	risbg	%r0,%r0,0,0,0
 	risbg	%r0,%r0,0,0,63
-	risbg	%r0,%r0,0,63,0
-	risbg	%r0,%r0,63,0,0
+	risbg	%r0,%r0,0,255,0
+	risbg	%r0,%r0,255,0,0
 	risbg	%r0,%r15,0,0,0
 	risbg	%r15,%r0,0,0,0
 	risbg	%r4,%r5,6,7,8
 
+#CHECK: rnsbg	%r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x54]
+#CHECK: rnsbg	%r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x54]
+#CHECK: rnsbg	%r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x54]
+#CHECK: rnsbg	%r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x54]
+#CHECK: rnsbg	%r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x54]
+#CHECK: rnsbg	%r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x54]
+#CHECK: rnsbg	%r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x54]
+
+	rnsbg	%r0,%r0,0,0,0
+	rnsbg	%r0,%r0,0,0,63
+	rnsbg	%r0,%r0,0,255,0
+	rnsbg	%r0,%r0,255,0,0
+	rnsbg	%r0,%r15,0,0,0
+	rnsbg	%r15,%r0,0,0,0
+	rnsbg	%r4,%r5,6,7,8
+
+#CHECK: rosbg	%r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x56]
+#CHECK: rosbg	%r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x56]
+#CHECK: rosbg	%r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x56]
+#CHECK: rosbg	%r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x56]
+#CHECK: rosbg	%r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x56]
+#CHECK: rosbg	%r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x56]
+#CHECK: rosbg	%r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x56]
+
+	rosbg	%r0,%r0,0,0,0
+	rosbg	%r0,%r0,0,0,63
+	rosbg	%r0,%r0,0,255,0
+	rosbg	%r0,%r0,255,0,0
+	rosbg	%r0,%r15,0,0,0
+	rosbg	%r15,%r0,0,0,0
+	rosbg	%r4,%r5,6,7,8
+
+#CHECK: rxsbg	%r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x57]
+#CHECK: rxsbg	%r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x57]
+#CHECK: rxsbg	%r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x57]
+#CHECK: rxsbg	%r0, %r0, 255, 0, 0     # encoding: [0xec,0x00,0xff,0x00,0x00,0x57]
+#CHECK: rxsbg	%r0, %r15, 0, 0, 0      # encoding: [0xec,0x0f,0x00,0x00,0x00,0x57]
+#CHECK: rxsbg	%r15, %r0, 0, 0, 0      # encoding: [0xec,0xf0,0x00,0x00,0x00,0x57]
+#CHECK: rxsbg	%r4, %r5, 6, 7, 8       # encoding: [0xec,0x45,0x06,0x07,0x08,0x57]
+
+	rxsbg	%r0,%r0,0,0,0
+	rxsbg	%r0,%r0,0,0,63
+	rxsbg	%r0,%r0,0,255,0
+	rxsbg	%r0,%r0,255,0,0
+	rxsbg	%r0,%r15,0,0,0
+	rxsbg	%r15,%r0,0,0,0
+	rxsbg	%r4,%r5,6,7,8
+
 #CHECK: rll	%r0, %r0, 0             # encoding: [0xeb,0x00,0x00,0x00,0x00,0x1d]
 #CHECK: rll	%r15, %r1, 0            # encoding: [0xeb,0xf1,0x00,0x00,0x00,0x1d]
 #CHECK: rll	%r1, %r15, 0            # encoding: [0xeb,0x1f,0x00,0x00,0x00,0x1d]
diff --git a/test/MC/SystemZ/tokens.s b/test/MC/SystemZ/tokens.s
index 07b29d8..2719752 100644
--- a/test/MC/SystemZ/tokens.s
+++ b/test/MC/SystemZ/tokens.s
@@ -3,10 +3,16 @@
 
 #CHECK: error: invalid instruction
 #CHECK: foo	100, 200
-#CHECK: error: register expected
+#CHECK: error: unknown token in expression
 #CHECK: foo	100(, 200
+#CHECK: error: invalid instruction
+#CHECK: foo	100(200), 300
 #CHECK: error: register expected
-#CHECK: foo	100(0), 200
+#CHECK: foo	100(200,), 300
+#CHECK: error: %r0 used in an address
+#CHECK: foo	100(200,%r0), 300
+#CHECK: error: invalid instruction
+#CHECK: foo	100(200,%r1), 300
 #CHECK: error: invalid operand
 #CHECK: foo	100(%a0), 200
 #CHECK: error: %r0 used in an address
@@ -48,7 +54,10 @@
 
 	foo	100, 200
 	foo	100(, 200
-	foo	100(0), 200
+	foo	100(200), 300
+	foo	100(200,), 300
+	foo	100(200,%r0), 300
+	foo	100(200,%r1), 300
 	foo	100(%a0), 200
 	foo	100(%r0), 200
 	foo	100(%r1,%a0), 200
diff --git a/test/MC/X86/AlignedBundling/align-mode-argument-error.s b/test/MC/X86/AlignedBundling/align-mode-argument-error.s
index b4ce0a9..37c74c8 100644
--- a/test/MC/X86/AlignedBundling/align-mode-argument-error.s
+++ b/test/MC/X86/AlignedBundling/align-mode-argument-error.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
+# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
 
 # Missing .bundle_align_mode argument
 # CHECK: error: unknown token
diff --git a/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s b/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s
index 722bf7b..a9a78a7 100644
--- a/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s
+++ b/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
+# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
 
 # CHECK: ERROR: Fragment can't be larger than a bundle size
 
diff --git a/test/MC/X86/AlignedBundling/bundle-lock-option-error.s b/test/MC/X86/AlignedBundling/bundle-lock-option-error.s
index 82c5d7c..b0b595f 100644
--- a/test/MC/X86/AlignedBundling/bundle-lock-option-error.s
+++ b/test/MC/X86/AlignedBundling/bundle-lock-option-error.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
+# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
 
 # Missing .bundle_align_mode argument
 # CHECK: error: invalid option
diff --git a/test/MC/X86/AlignedBundling/lock-without-bundle-mode-error.s b/test/MC/X86/AlignedBundling/lock-without-bundle-mode-error.s
index d45a9b4..2f71654 100644
--- a/test/MC/X86/AlignedBundling/lock-without-bundle-mode-error.s
+++ b/test/MC/X86/AlignedBundling/lock-without-bundle-mode-error.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
+# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
 
 # .bundle_lock can't come without a .bundle_align_mode before it
 
diff --git a/test/MC/X86/AlignedBundling/switch-section-locked-error.s b/test/MC/X86/AlignedBundling/switch-section-locked-error.s
index af41e19..a5812fd 100644
--- a/test/MC/X86/AlignedBundling/switch-section-locked-error.s
+++ b/test/MC/X86/AlignedBundling/switch-section-locked-error.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
+# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
 
 # This test invokes .bundle_lock and then switches to a different section
 # w/o the appropriate unlock.
diff --git a/test/MC/X86/AlignedBundling/unlock-without-lock-error.s b/test/MC/X86/AlignedBundling/unlock-without-lock-error.s
index 699511d..a73f19e 100644
--- a/test/MC/X86/AlignedBundling/unlock-without-lock-error.s
+++ b/test/MC/X86/AlignedBundling/unlock-without-lock-error.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
+# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s
 
 # .bundle_unlock can't come without a .bundle_lock before it
 
diff --git a/test/MC/X86/avx512-encodings.s b/test/MC/X86/avx512-encodings.s
new file mode 100644
index 0000000..26a77c1
--- /dev/null
+++ b/test/MC/X86/avx512-encodings.s
@@ -0,0 +1,21 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK: vinserti32x4
+// CHECK: encoding: [0x62,0xa3,0x55,0x48,0x38,0xcd,0x01]
+vinserti32x4  $1, %xmm21, %zmm5, %zmm17
+
+// CHECK: vinserti32x4
+// CHECK: encoding: [0x62,0xe3,0x1d,0x40,0x38,0x4f,0x10,0x01]
+vinserti32x4  $1, 256(%rdi), %zmm28, %zmm17
+
+// CHECK: vextracti32x4
+// CHECK: encoding: [0x62,0x33,0x7d,0x48,0x39,0xc9,0x01]
+vextracti32x4  $1, %zmm9, %xmm17
+
+// CHECK: vextracti64x4
+// CHECK: encoding: [0x62,0x33,0xfd,0x48,0x3b,0xc9,0x01]
+vextracti64x4  $1, %zmm9, %ymm17
+
+// CHECK: vextracti64x4
+// CHECK: encoding: [0x62,0x73,0xfd,0x48,0x3b,0x4f,0x10,0x01]
+vextracti64x4  $1, %zmm9, 512(%rdi)
diff --git a/test/MC/X86/intel-syntax.s b/test/MC/X86/intel-syntax.s
index fa1ba5b..ff86e8d 100644
--- a/test/MC/X86/intel-syntax.s
+++ b/test/MC/X86/intel-syntax.s
@@ -325,3 +325,254 @@ _main:
 // CHECK: outb %al, $4
     out 4, al
     ret
+
+// CHECK: cmovbl %ebx, %eax
+    cmovc eax, ebx
+// CHECK: cmovel %ebx, %eax
+    cmovz eax, ebx
+// CHECK: cmovbel %ebx, %eax
+    cmovna eax, ebx
+// CHECK: cmovael %ebx, %eax
+    cmovnb eax, ebx
+// CHECK: cmovael %ebx, %eax
+    cmovnc eax, ebx
+// CHECK: cmovlel %ebx, %eax
+    cmovng eax, ebx
+// CHECK: cmovgel %ebx, %eax
+    cmovnl eax, ebx
+// CHECK: cmovnel %ebx, %eax
+    cmovnz eax, ebx
+// CHECK: cmovpl %ebx, %eax
+    cmovpe eax, ebx
+// CHECK: cmovnpl %ebx, %eax
+    cmovpo eax, ebx
+// CHECK: cmovbl %ebx, %eax
+    cmovnae eax, ebx
+// CHECK: cmoval %ebx, %eax
+    cmovnbe eax, ebx
+// CHECK: cmovll %ebx, %eax
+    cmovnge eax, ebx
+// CHECK: cmovgl %ebx, %eax
+    cmovnle eax, ebx
+
+// CHECK: shldw	%cl, %bx, %dx
+// CHECK: shldw	%cl, %bx, %dx
+// CHECK: shldw	$1, %bx, %dx
+// CHECK: shldw	%cl, %bx, (%rax)
+// CHECK: shldw	%cl, %bx, (%rax)
+// CHECK: shrdw	%cl, %bx, %dx
+// CHECK: shrdw	%cl, %bx, %dx
+// CHECK: shrdw	$1, %bx, %dx
+// CHECK: shrdw	%cl, %bx, (%rax)
+// CHECK: shrdw	%cl, %bx, (%rax)
+
+shld  DX, BX
+shld  DX, BX, CL
+shld  DX, BX, 1
+shld  [RAX], BX
+shld  [RAX], BX, CL
+shrd  DX, BX
+shrd  DX, BX, CL
+shrd  DX, BX, 1
+shrd  [RAX], BX
+shrd  [RAX], BX, CL
+
+// CHECK: btl $1, (%eax)
+// CHECK: btsl $1, (%eax)
+// CHECK: btrl $1, (%eax)
+// CHECK: btcl $1, (%eax)
+    bt DWORD PTR [EAX], 1
+    bt DWORD PTR [EAX], 1
+    bts DWORD PTR [EAX], 1
+    btr DWORD PTR [EAX], 1
+    btc DWORD PTR [EAX], 1
+
+//CHECK: divb	%bl
+//CHECK: divw	%bx
+//CHECK: divl	%ecx
+//CHECK: divl	3735928559(%ebx,%ecx,8)
+//CHECK: divl	69
+//CHECK: divl	32493
+//CHECK: divl	3133065982
+//CHECK: divl	305419896
+//CHECK: idivb	%bl
+//CHECK: idivw	%bx
+//CHECK: idivl	%ecx
+//CHECK: idivl	3735928559(%ebx,%ecx,8)
+//CHECK: idivl	69
+//CHECK: idivl	32493
+//CHECK: idivl	3133065982
+//CHECK: idivl	305419896
+    div AL, BL
+    div AX, BX
+    div EAX, ECX
+    div EAX, [ECX*8+EBX+0xdeadbeef]
+    div EAX, [0x45]
+    div EAX, [0x7eed]
+    div EAX, [0xbabecafe]
+    div EAX, [0x12345678]
+    idiv AL, BL
+    idiv AX, BX
+    idiv EAX, ECX
+    idiv EAX, [ECX*8+EBX+0xdeadbeef]
+    idiv EAX, [0x45]
+    idiv EAX, [0x7eed]
+    idiv EAX, [0xbabecafe]
+    idiv EAX, [0x12345678]
+
+
+// CHECK: inb %dx, %al
+// CHECK: inw %dx, %ax
+// CHECK: inl %dx, %eax
+// CHECK: outb %al, %dx
+// CHECK: outw %ax, %dx
+// CHECK: outl %eax, %dx
+    inb DX
+    inw DX
+    inl DX
+    outb DX
+    outw DX
+    outl DX
+
+// CHECK: xchgq %rcx, %rax
+// CHECK: xchgq %rcx, %rax
+// CHECK: xchgl %ecx, %eax
+// CHECK: xchgl %ecx, %eax
+// CHECK: xchgw %cx, %ax
+// CHECK: xchgw %cx, %ax
+xchg RAX, RCX
+xchg RCX, RAX
+xchg EAX, ECX
+xchg ECX, EAX
+xchg AX, CX
+xchg CX, AX
+
+// CHECK: xchgq %rax, (%ecx)
+// CHECK: xchgq %rax, (%ecx)
+// CHECK: xchgl %eax, (%ecx)
+// CHECK: xchgl %eax, (%ecx)
+// CHECK: xchgw %ax, (%ecx)
+// CHECK: xchgw %ax, (%ecx)
+xchg RAX, [ECX]
+xchg [ECX], RAX
+xchg EAX, [ECX]
+xchg [ECX], EAX
+xchg AX, [ECX]
+xchg [ECX], AX
+
+// CHECK: testq (%ecx), %rax
+// CHECK: testq (%ecx), %rax
+// CHECK: testl (%ecx), %eax
+// CHECK: testl (%ecx), %eax
+// CHECK: testw (%ecx), %ax
+// CHECK: testw (%ecx), %ax
+// CHECK: testb (%ecx), %al
+// CHECK: testb (%ecx), %al
+test RAX, [ECX]
+test [ECX], RAX
+test EAX, [ECX]
+test [ECX], EAX
+test AX, [ECX]
+test [ECX], AX
+test AL, [ECX]
+test [ECX], AL
+
+// CHECK: fnstsw %ax
+// CHECK: fnstsw %ax
+// CHECK: fnstsw %ax
+// CHECK: fnstsw %ax
+fnstsw
+fnstsw AX
+fnstsw EAX
+fnstsw AL
+
+// CHECK: faddp %st(1)
+// CHECK: fmulp %st(1)
+// CHECK: fsubrp %st(1)
+// CHECK: fsubp %st(1)
+// CHECK: fdivrp %st(1)
+// CHECK: fdivp %st(1)
+faddp ST(1), ST(0)
+fmulp ST(1), ST(0)
+fsubp ST(1), ST(0)
+fsubrp ST(1), ST(0)
+fdivp ST(1), ST(0)
+fdivrp ST(1), ST(0)
+
+// CHECK: faddp %st(1)
+// CHECK: fmulp %st(1)
+// CHECK: fsubrp %st(1)
+// CHECK: fsubp %st(1)
+// CHECK: fdivrp %st(1)
+// CHECK: fdivp %st(1)
+faddp ST(0), ST(1)
+fmulp ST(0), ST(1)
+fsubp ST(0), ST(1)
+fsubrp ST(0), ST(1)
+fdivp ST(0), ST(1)
+fdivrp ST(0), ST(1)
+
+// CHECK: faddp %st(1)
+// CHECK: fmulp %st(1)
+// CHECK: fsubrp %st(1)
+// CHECK: fsubp %st(1)
+// CHECK: fdivrp %st(1)
+// CHECK: fdivp %st(1)
+faddp ST(1)
+fmulp ST(1)
+fsubp ST(1)
+fsubrp ST(1)
+fdivp ST(1)
+fdivrp ST(1)
+
+// CHECK: faddp %st(1)
+// CHECK: fmulp %st(1)
+// CHECK: fsubrp %st(1)
+// CHECK: fsubp %st(1)
+// CHECK: fdivrp %st(1)
+// CHECK: fdivp %st(1)
+faddp
+fmulp
+fsubp
+fsubrp
+fdivp
+fdivrp
+
+// CHECK: fadd %st(1)
+// CHECK: fmul %st(1)
+// CHECK: fsub %st(1)
+// CHECK: fsubr %st(1)
+// CHECK: fdiv %st(1)
+// CHECK: fdivr %st(1)
+fadd ST(0), ST(1)
+fmul ST(0), ST(1)
+fsub ST(0), ST(1)
+fsubr ST(0), ST(1)
+fdiv ST(0), ST(1)
+fdivr ST(0), ST(1)
+
+// CHECK: fadd %st(0), %st(1)
+// CHECK: fmul %st(0), %st(1)
+// CHECK: fsubr %st(0), %st(1)
+// CHECK: fsub %st(0), %st(1)
+// CHECK: fdivr %st(0), %st(1)
+// CHECK: fdiv %st(0), %st(1)
+fadd ST(1), ST(0)
+fmul ST(1), ST(0)
+fsub ST(1), ST(0)
+fsubr ST(1), ST(0)
+fdiv ST(1), ST(0)
+fdivr ST(1), ST(0)
+
+// CHECK: fadd %st(1)
+// CHECK: fmul %st(1)
+// CHECK: fsub %st(1)
+// CHECK: fsubr %st(1)
+// CHECK: fdiv %st(1)
+// CHECK: fdivr %st(1)
+fadd ST(1)
+fmul ST(1)
+fsub ST(1)
+fsubr ST(1)
+fdiv ST(1)
+fdivr ST(1)
diff --git a/test/MC/X86/x86-32-coverage.s b/test/MC/X86/x86-32-coverage.s
index c348915..732874b 100644
--- a/test/MC/X86/x86-32-coverage.s
+++ b/test/MC/X86/x86-32-coverage.s
@@ -3948,7 +3948,7 @@
 // CHECK:  encoding: [0xd9,0xca]
         	fxch	%st(2)
 
-// CHECK: fcom
+// CHECK: fcom	%st(1)
 // CHECK:  encoding: [0xd8,0xd1]
         	fcom
 
@@ -3972,7 +3972,7 @@
 // CHECK:  encoding: [0xda,0x15,0x78,0x56,0x34,0x12]
         	ficoml	0x12345678
 
-// CHECK: fcomp
+// CHECK: fcomp	%st(1)
 // CHECK:  encoding: [0xd8,0xd9]
         	fcomp
 
@@ -19660,3 +19660,37 @@ blendvps %xmm0, %xmm2, %xmm1
 blendvps (%eax), %xmm1
 // CHECK: blendvps (%eax), %xmm1
 blendvps %xmm0, (%eax), %xmm1
+
+
+// CHECK: btl $4, (%eax)
+// CHECK: btw $4, (%eax)
+// CHECK: btl $4, (%eax)
+// CHECK: btq $4, (%eax)
+// CHECK: btsl $4, (%eax)
+// CHECK: btsw $4, (%eax)
+// CHECK: btsl $4, (%eax)
+// CHECK: btsq $4, (%eax)
+// CHECK: btrl $4, (%eax)
+// CHECK: btrw $4, (%eax)
+// CHECK: btrl $4, (%eax)
+// CHECK: btrq $4, (%eax)
+// CHECK: btcl $4, (%eax)
+// CHECK: btcw $4, (%eax)
+// CHECK: btcl $4, (%eax)
+// CHECK: btcq $4, (%eax)
+bt $4, (%eax)
+btw $4, (%eax)
+btl $4, (%eax)
+btq $4, (%eax)
+bts $4, (%eax)
+btsw $4, (%eax)
+btsl $4, (%eax)
+btsq $4, (%eax)
+btr $4, (%eax)
+btrw $4, (%eax)
+btrl $4, (%eax)
+btrq $4, (%eax)
+btc $4, (%eax)
+btcw $4, (%eax)
+btcl $4, (%eax)
+btcq $4, (%eax)
diff --git a/test/MC/X86/x86-32.s b/test/MC/X86/x86-32.s
index 57a0037..99136bd 100644
--- a/test/MC/X86/x86-32.s
+++ b/test/MC/X86/x86-32.s
@@ -894,9 +894,9 @@ pshufw $90, %mm4, %mm0
 	movsw	%ds:(%esi), %es:(%edi)
 	movsw	(%esi), %es:(%edi)
 
-// CHECK: movsd # encoding: [0xa5]
-// CHECK: movsd
-// CHECK: movsd
+// CHECK: movsl # encoding: [0xa5]
+// CHECK: movsl
+// CHECK: movsl
 	movsl
 	movsl	%ds:(%esi), %es:(%edi)
 	movsl	(%esi), %es:(%edi)
diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s
index 521a077..c0eac5e 100644
--- a/test/MC/X86/x86-64.s
+++ b/test/MC/X86/x86-64.s
@@ -115,12 +115,12 @@
 // rdar://8470918
 smovb // CHECK: movsb
 smovw // CHECK: movsw
-smovl // CHECK: movsd
+smovl // CHECK: movsl
 smovq // CHECK: movsq
 
 // rdar://8456361
 // CHECK: rep
-// CHECK: movsd
+// CHECK: movsl
         rep movsd
 
 // CHECK: rep
@@ -241,10 +241,10 @@ cmovnzq %rbx, %rax
 
 // rdar://8407928
 // CHECK: inb	$127, %al
-// CHECK: inw	%dx
+// CHECK: inw	%dx, %ax
 // CHECK: outb	%al, $127
-// CHECK: outw	%dx
-// CHECK: inl	%dx
+// CHECK: outw	%ax, %dx
+// CHECK: inl	%dx, %eax
 inb	$0x7f
 inw	%dx
 outb	$0x7f
@@ -253,12 +253,12 @@ inl	%dx
 
 
 // PR8114
-// CHECK: outb	%dx
-// CHECK: outb	%dx
-// CHECK: outw	%dx
-// CHECK: outw	%dx
-// CHECK: outl	%dx
-// CHECK: outl	%dx
+// CHECK: outb	%al, %dx
+// CHECK: outb	%al, %dx
+// CHECK: outw	%ax, %dx
+// CHECK: outw	%ax, %dx
+// CHECK: outl	%eax, %dx
+// CHECK: outl	%eax, %dx
 
 out	%al, (%dx)
 outb	%al, (%dx)
@@ -267,12 +267,12 @@ outw	%ax, (%dx)
 out	%eax, (%dx)
 outl	%eax, (%dx)
 
-// CHECK: inb	%dx
-// CHECK: inb	%dx
-// CHECK: inw	%dx
-// CHECK: inw	%dx
-// CHECK: inl	%dx
-// CHECK: inl	%dx
+// CHECK: inb	%dx, %al
+// CHECK: inb	%dx, %al
+// CHECK: inw	%dx, %ax
+// CHECK: inw	%dx, %ax
+// CHECK: inl	%dx, %eax
+// CHECK: inl	%dx, %eax
 
 in	(%dx), %al
 inb	(%dx), %al
@@ -283,16 +283,16 @@ inl	(%dx), %eax
 
 // rdar://8431422
 
-// CHECK: fxch
-// CHECK: fucom
-// CHECK: fucomp
-// CHECK: faddp
+// CHECK: fxch %st(1)
+// CHECK: fucom %st(1)
+// CHECK: fucomp %st(1)
+// CHECK: faddp %st(1)
 // CHECK: faddp	%st(0)
-// CHECK: fsubp
-// CHECK: fsubrp
-// CHECK: fmulp
-// CHECK: fdivp
-// CHECK: fdivrp
+// CHECK: fsubp %st(1)
+// CHECK: fsubrp %st(1)
+// CHECK: fmulp %st(1)
+// CHECK: fdivp %st(1)
+// CHECK: fdivrp %st(1)
 
 fxch
 fucom
@@ -305,9 +305,9 @@ fmulp
 fdivp
 fdivrp
 
-// CHECK: fcomi
+// CHECK: fcomi %st(1)
 // CHECK: fcomi	%st(2)
-// CHECK: fucomi
+// CHECK: fucomi %st(1)
 // CHECK: fucomi %st(2)
 // CHECK: fucomi %st(2)
 
@@ -317,10 +317,10 @@ fucomi
 fucomi	%st(2)
 fucomi	%st(2), %st
 
-// CHECK: fnstsw
-// CHECK: fnstsw
-// CHECK: fnstsw
-// CHECK: fnstsw
+// CHECK: fnstsw %ax
+// CHECK: fnstsw %ax
+// CHECK: fnstsw %ax
+// CHECK: fnstsw %ax
 
 fnstsw
 fnstsw %ax
@@ -627,7 +627,7 @@ movsq
 // CHECK:   encoding: [0x48,0xa5]
 
 movsl
-// CHECK: movsd
+// CHECK: movsl
 // CHECK:   encoding: [0xa5]
 
 stosq
@@ -672,6 +672,38 @@ movl	0, %eax   // CHECK: movl 0, %eax # encoding: [0x8b,0x04,0x25,0x00,0x00,0x00
 // CHECK: encoding: [0x48,0xc7,0xc0,0x0a,0x00,0x00,0x00]
         movq $10, %rax
 
+// CHECK: movabsb -6066930261531658096, %al
+// CHECK: encoding: [0xa0,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
+        movabsb 0xabcdef1234567890,%al
+
+// CHECK: movabsw -6066930261531658096, %ax
+// CHECK: encoding: [0x66,0xa1,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
+        movabsw 0xabcdef1234567890,%ax
+
+// CHECK: movabsl -6066930261531658096, %eax
+// CHECK: encoding: [0xa1,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
+        movabsl 0xabcdef1234567890,%eax
+
+// CHECK: movabsq -6066930261531658096, %rax
+// CHECK: encoding: [0x48,0xa1,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
+        movabsq 0xabcdef1234567890, %rax
+
+// CHECK: movabsb %al, -6066930261531658096
+// CHECK: encoding: [0xa2,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
+        movabsb %al,0xabcdef1234567890
+
+// CHECK: movabsw %ax, -6066930261531658096
+// CHECK: encoding: [0x66,0xa3,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
+        movabsw %ax,0xabcdef1234567890
+
+// CHECK: movabsl %eax, -6066930261531658096
+// CHECK: encoding: [0xa3,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
+        movabsl %eax,0xabcdef1234567890
+
+// CHECK: movabsq %rax, -6066930261531658096
+// CHECK: encoding: [0x48,0xa3,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
+        movabsq %rax,0xabcdef1234567890
+
 // rdar://8014869
 //
 // CHECK: ret
@@ -813,7 +845,7 @@ lock/incl 1(%rsp)
 rep movsl
 // CHECK: rep
 // CHECK: encoding: [0xf3]
-// CHECK: movsd
+// CHECK: movsl
 // CHECK: encoding: [0xa5]
 
 
@@ -958,6 +990,22 @@ mov %gs, (%rsi)  // CHECK: movl	%gs, (%rsi) # encoding: [0x8c,0x2e]
 
 
 // rdar://8431864
+//CHECK: divb	%bl
+//CHECK: divw	%bx
+//CHECK: divl	%ecx
+//CHECK: divl	3735928559(%ebx,%ecx,8)
+//CHECK: divl	69
+//CHECK: divl	32493
+//CHECK: divl	3133065982
+//CHECK: divl	305419896
+//CHECK: idivb	%bl
+//CHECK: idivw	%bx
+//CHECK: idivl	%ecx
+//CHECK: idivl	3735928559(%ebx,%ecx,8)
+//CHECK: idivl	69
+//CHECK: idivl	32493
+//CHECK: idivl	3133065982
+//CHECK: idivl	305419896
 	div	%bl,%al
 	div	%bx,%ax
 	div	%ecx,%eax
@@ -1051,14 +1099,14 @@ xsetbv // CHECK: xsetbv # encoding: [0x0f,0x01,0xd1]
 	movsw	%ds:(%rsi), %es:(%rdi)
 	movsw	(%rsi), %es:(%rdi)
 
-// CHECK: movsd # encoding: [0xa5]
-// CHECK: movsd
-// CHECK: movsd
+// CHECK: movsl # encoding: [0xa5]
+// CHECK: movsl
+// CHECK: movsl
 	movsl
 	movsl	%ds:(%rsi), %es:(%rdi)
 	movsl	(%rsi), %es:(%rdi)
 // rdar://10883092
-// CHECK: movsd
+// CHECK: movsl
 	movsl	(%rsi), (%rdi)
 
 // CHECK: movsq # encoding: [0x48,0xa5]
@@ -1236,3 +1284,94 @@ clac
 // CHECK: stac
 // CHECK: encoding: [0x0f,0x01,0xcb]
 stac
+
+// CHECK: faddp %st(1)
+// CHECK: fmulp %st(1)
+// CHECK: fsubp %st(1)
+// CHECK: fsubrp %st(1)
+// CHECK: fdivp %st(1)
+// CHECK: fdivrp %st(1)
+faddp %st(0), %st(1)
+fmulp %st(0), %st(1)
+fsubp %st(0), %st(1)
+fsubrp %st(0), %st(1)
+fdivp %st(0), %st(1)
+fdivrp %st(0), %st(1)
+
+// CHECK: faddp %st(1)
+// CHECK: fmulp %st(1)
+// CHECK: fsubp %st(1)
+// CHECK: fsubrp %st(1)
+// CHECK: fdivp %st(1)
+// CHECK: fdivrp %st(1)
+faddp %st(1), %st(0)
+fmulp %st(1), %st(0)
+fsubp %st(1), %st(0)
+fsubrp %st(1), %st(0)
+fdivp %st(1), %st(0)
+fdivrp %st(1), %st(0)
+
+// CHECK: faddp %st(1)
+// CHECK: fmulp %st(1)
+// CHECK: fsubp %st(1)
+// CHECK: fsubrp %st(1)
+// CHECK: fdivp %st(1)
+// CHECK: fdivrp %st(1)
+faddp %st(1)
+fmulp %st(1)
+fsubp %st(1)
+fsubrp %st(1)
+fdivp %st(1)
+fdivrp %st(1)
+
+// CHECK: faddp %st(1)
+// CHECK: fmulp %st(1)
+// CHECK: fsubp %st(1)
+// CHECK: fsubrp %st(1)
+// CHECK: fdivp %st(1)
+// CHECK: fdivrp %st(1)
+faddp
+fmulp
+fsubp
+fsubrp
+fdivp
+fdivrp
+
+// CHECK: fadd %st(1)
+// CHECK: fmul %st(1)
+// CHECK: fsub %st(1)
+// CHECK: fsubr %st(1)
+// CHECK: fdiv %st(1)
+// CHECK: fdivr %st(1)
+fadd %st(1), %st(0)
+fmul %st(1), %st(0)
+fsub %st(1), %st(0)
+fsubr %st(1), %st(0)
+fdiv %st(1), %st(0)
+fdivr %st(1), %st(0)
+
+// CHECK: fadd %st(0), %st(1)
+// CHECK: fmul %st(0), %st(1)
+// CHECK: fsub %st(0), %st(1)
+// CHECK: fsubr %st(0), %st(1)
+// CHECK: fdiv %st(0), %st(1)
+// CHECK: fdivr %st(0), %st(1)
+fadd %st(0), %st(1)
+fmul %st(0), %st(1)
+fsub %st(0), %st(1)
+fsubr %st(0), %st(1)
+fdiv %st(0), %st(1)
+fdivr %st(0), %st(1)
+
+// CHECK: fadd %st(1)
+// CHECK: fmul %st(1)
+// CHECK: fsub %st(1)
+// CHECK: fsubr %st(1)
+// CHECK: fdiv %st(1)
+// CHECK: fdivr %st(1)
+fadd %st(1)
+fmul %st(1)
+fsub %st(1)
+fsubr %st(1)
+fdiv %st(1)
+fdivr %st(1)
diff --git a/test/MC/X86/x86_64-hle-encoding.s b/test/MC/X86/x86_64-hle-encoding.s
new file mode 100644
index 0000000..aaaca7d
--- /dev/null
+++ b/test/MC/X86/x86_64-hle-encoding.s
@@ -0,0 +1,9 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK: xacquire
+// CHECK: [0xf2]
+    xacquire
+
+// CHECK: xrelease
+// CHECK: [0xf3]
+    xrelease
diff --git a/test/Makefile.tests b/test/Makefile.tests
index c60c90c..b2e5300 100644
--- a/test/Makefile.tests
+++ b/test/Makefile.tests
@@ -47,18 +47,6 @@ clean::
 	$(RM) -f a.out core
 	$(RM) -rf Output/
 
-# Compile from X.c to Output/X.ll
-Output/%.ll: %.c $(LCC1) Output/.dir $(INCLUDES)
-	-$(LLVMCC) $(CPPFLAGS) $(LCCFLAGS) -S $< -o $@
-
-# Compile from X.cpp to Output/X.ll
-Output/%.ll: %.cpp $(LCC1XX) Output/.dir $(INCLUDES)
-	-$(LLVMCXX) $(CPPFLAGS) $(LCXXFLAGS) -S $< -o $@
-
-# Compile from X.cc to Output/X.ll
-Output/%.ll: %.cc $(LCC1XX) Output/.dir $(INCLUDES)
-	-$(LLVMCXX) $(CPPFLAGS) $(LCXXFLAGS) -S $< -o $@
-
 # LLVM Assemble from Output/X.ll to Output/X.bc.  Output/X.ll must have come
 # from GCC output, so use GCCAS.
 #
diff --git a/test/Archive/GNU.a b/test/Object/Inputs/GNU.a
index 4c09881..4c09881 100644
--- a/test/Archive/GNU.a
+++ b/test/Object/Inputs/GNU.a
diff --git a/test/Archive/IsNAN.o b/test/Object/Inputs/IsNAN.o
index 7b3a12a..7b3a12a 100644
--- a/test/Archive/IsNAN.o
+++ b/test/Object/Inputs/IsNAN.o
diff --git a/test/Archive/MacOSX.a b/test/Object/Inputs/MacOSX.a
index 8ba1e6d..8ba1e6d 100644
--- a/test/Archive/MacOSX.a
+++ b/test/Object/Inputs/MacOSX.a
diff --git a/test/Archive/SVR4.a b/test/Object/Inputs/SVR4.a
index 3947813..3947813 100644
--- a/test/Archive/SVR4.a
+++ b/test/Object/Inputs/SVR4.a
diff --git a/test/Object/Inputs/archive-test.a-corrupt-symbol-table b/test/Object/Inputs/archive-test.a-corrupt-symbol-table
new file mode 100644
index 0000000..34e5ed7
--- /dev/null
+++ b/test/Object/Inputs/archive-test.a-corrupt-symbol-table
diff --git a/test/Object/Inputs/archive-test.a-empty b/test/Object/Inputs/archive-test.a-empty
new file mode 100644
index 0000000..8b277f0
--- /dev/null
+++ b/test/Object/Inputs/archive-test.a-empty
@@ -0,0 +1 @@
+!<arch>
diff --git a/test/Object/Inputs/archive-test.a-gnu-minimal b/test/Object/Inputs/archive-test.a-gnu-minimal
new file mode 100644
index 0000000..a243273
--- /dev/null
+++ b/test/Object/Inputs/archive-test.a-gnu-minimal
@@ -0,0 +1,2 @@
+!<arch>
+test/           1372964340  1000  1000  100664  0         `
diff --git a/test/Object/Inputs/archive-test.a-gnu-no-symtab b/test/Object/Inputs/archive-test.a-gnu-no-symtab
new file mode 100644
index 0000000..0a5b237
--- /dev/null
+++ b/test/Object/Inputs/archive-test.a-gnu-no-symtab
@@ -0,0 +1,5 @@
+!<arch>
+//                                              24        `
+a-very-long-file-name/
+
+/0              1372864788  1000  1000  100664  0         `
diff --git a/test/Archive/evenlen b/test/Object/Inputs/evenlen
index 59ee8d5..59ee8d5 100644
--- a/test/Archive/evenlen
+++ b/test/Object/Inputs/evenlen
diff --git a/test/Object/Inputs/macho-universal.x86_64.i386 b/test/Object/Inputs/macho-universal.x86_64.i386
new file mode 100755
index 0000000..36d5fc2
--- /dev/null
+++ b/test/Object/Inputs/macho-universal.x86_64.i386
diff --git a/test/Archive/oddlen b/test/Object/Inputs/oddlen
index 8cf5bd1..8cf5bd1 100644
--- a/test/Archive/oddlen
+++ b/test/Object/Inputs/oddlen
diff --git a/test/Object/Inputs/trivial-object-test2.elf-x86-64 b/test/Object/Inputs/trivial-object-test2.elf-x86-64
new file mode 100644
index 0000000..9124518
--- /dev/null
+++ b/test/Object/Inputs/trivial-object-test2.elf-x86-64
diff --git a/test/Archive/very_long_bytecode_file_name.bc b/test/Object/Inputs/very_long_bytecode_file_name.bc
index f7fce24..f7fce24 100644
--- a/test/Archive/very_long_bytecode_file_name.bc
+++ b/test/Object/Inputs/very_long_bytecode_file_name.bc
diff --git a/test/Archive/xpg4.a b/test/Object/Inputs/xpg4.a
index b2bdb51..b2bdb51 100644
--- a/test/Archive/xpg4.a
+++ b/test/Object/Inputs/xpg4.a
diff --git a/test/Object/ar-create.test b/test/Object/ar-create.test
new file mode 100644
index 0000000..95d994e
--- /dev/null
+++ b/test/Object/ar-create.test
@@ -0,0 +1,17 @@
+Test which operations create an archive and which don't.
+
+RUN: touch %t
+RUN: rm -f %t.foo.a
+RUN: not llvm-ar p %t.foo.a %t 2>&1 | FileCheck %s
+RUN: not llvm-ar d %t.foo.a %t 2>&1 | FileCheck %s
+RUN: not llvm-ar m %t.foo.a %t 2>&1 | FileCheck %s
+RUN: not llvm-ar t %t.foo.a %t 2>&1 | FileCheck %s
+RUN: not llvm-ar x %t.foo.a %t 2>&1 | FileCheck %s
+
+RUN: llvm-ar q %t.foo.a %t 2>&1 | FileCheck --check-prefix=CREATE %s
+RUN: rm -f %t.foo.a
+RUN: llvm-ar r %t.foo.a %t 2>&1 | FileCheck --check-prefix=CREATE %s
+RUN: rm -f %t.foo.a
+
+CHECK: llvm-ar{{(.exe|.EXE)?}}: error loading '{{[^']+}}.foo.a':
+CREATE: creating {{.*}}.foo.a
diff --git a/test/Object/archive-delete.test b/test/Object/archive-delete.test
new file mode 100644
index 0000000..552b0e7
--- /dev/null
+++ b/test/Object/archive-delete.test
@@ -0,0 +1,30 @@
+Test the 'd' operation in llvm-ar
+
+REQUIRES: shell
+
+RUN: cd %T
+
+RUN: rm -f %t.a
+RUN: cp %p/Inputs/GNU.a %t.a
+RUN: llvm-ar d %t.a very_long_bytecode_file_name.bc
+RUN: llvm-ar t %t.a | FileCheck %s
+
+RUN: rm -f %t.a
+RUN: cp %p/Inputs/MacOSX.a %t.a
+RUN: llvm-ar d %t.a very_long_bytecode_file_name.bc
+RUN: llvm-ar t %t.a | FileCheck %s
+
+RUN: rm -f %t.a
+RUN: cp %p/Inputs/SVR4.a %t.a
+RUN: llvm-ar d %t.a very_long_bytecode_file_name.bc
+RUN: llvm-ar t %t.a | FileCheck %s
+
+RUN: rm -f %t.a
+RUN: cp %p/Inputs/xpg4.a %t.a
+RUN: llvm-ar d %t.a very_long_bytecode_file_name.bc
+RUN: llvm-ar t %t.a | FileCheck %s
+
+
+CHECK: evenlen
+CHECK-NEXT: oddlen
+CHECK-NEXT: IsNAN.o
diff --git a/test/Object/archive-error-tmp.txt b/test/Object/archive-error-tmp.txt
new file mode 100644
index 0000000..0618986
--- /dev/null
+++ b/test/Object/archive-error-tmp.txt
@@ -0,0 +1,9 @@
+REQUIRES: shell
+
+Test that no temporary file is left behind on error.
+
+RUN: rm -rf %t
+RUN: mkdir %t
+RUN: not llvm-ar rc %t/foo.a .
+RUN: rmdir %t
+
diff --git a/test/Object/archive-extract-dir.test b/test/Object/archive-extract-dir.test
new file mode 100644
index 0000000..c718f90
--- /dev/null
+++ b/test/Object/archive-extract-dir.test
@@ -0,0 +1,13 @@
+REQUIRES: shell
+
+RUN: mkdir -p %t
+RUN: cd %t
+RUN: rm -rf foo
+RUN: echo foo > foo
+RUN: rm -f test.a
+RUN: llvm-ar rc          test.a foo
+RUN: rm foo
+RUN: mkdir foo
+RUN: not llvm-ar x test.a foo 2>&1 | FileCheck %s
+
+CHECK: foo: Is a directory
diff --git a/test/Object/archive-format.test b/test/Object/archive-format.test
new file mode 100644
index 0000000..20ac1a0
--- /dev/null
+++ b/test/Object/archive-format.test
@@ -0,0 +1,22 @@
+Test the exact archive format. In particular, test which file names use the
+string table or not.
+
+REQUIRES: shell
+
+RUN: mkdir -p %t
+RUN: cd %t
+
+RUN: echo bar > 0123456789abcde
+RUN: echo zed > 0123456789abcdef
+
+RUN: rm -f test.a
+RUN: llvm-ar rc test.a 0123456789abcde 0123456789abcdef
+RUN: cat test.a | FileCheck -strict-whitespace %s
+
+CHECK:      !<arch>
+CHECK-NEXT: //                                              18        `
+CHECK-NEXT: 0123456789abcdef/
+CHECK-NEXT: 0123456789abcde/{{................................}}4         `
+CHECK-NEXT: bar
+CHECK-NEXT: /0              {{................................}}4         `
+CHECK-NEXT: zed
diff --git a/test/Object/archive-move.test b/test/Object/archive-move.test
new file mode 100644
index 0000000..0378e91
--- /dev/null
+++ b/test/Object/archive-move.test
@@ -0,0 +1,50 @@
+Test the 'm' operation in llvm-ar
+
+REQUIRES: shell
+
+RUN: cd %T
+
+RUN: rm -f %t.a
+RUN: cp %p/Inputs/GNU.a %t.a
+RUN: llvm-ar m %t.a very_long_bytecode_file_name.bc
+RUN: llvm-ar t %t.a | FileCheck %s
+
+RUN: rm -f %t.a
+RUN: cp %p/Inputs/MacOSX.a %t.a
+RUN: llvm-ar m %t.a very_long_bytecode_file_name.bc
+RUN: llvm-ar t %t.a | FileCheck %s
+
+RUN: rm -f %t.a
+RUN: cp %p/Inputs/SVR4.a %t.a
+RUN: llvm-ar m %t.a very_long_bytecode_file_name.bc
+RUN: llvm-ar t %t.a | FileCheck %s
+
+RUN: rm -f %t.a
+RUN: cp %p/Inputs/xpg4.a %t.a
+RUN: llvm-ar m %t.a very_long_bytecode_file_name.bc
+RUN: llvm-ar t %t.a | FileCheck %s
+
+CHECK: evenlen
+CHECK-NEXT: oddlen
+CHECK-NEXT: IsNAN.o
+CHECK-NEXT: very_long_bytecode_file_name.bc
+
+RUN: rm -f %t.a
+RUN: cp %p/Inputs/GNU.a %t.a
+RUN: llvm-ar mb evenlen %t.a very_long_bytecode_file_name.bc
+RUN: llvm-ar t %t.a | FileCheck --check-prefix=BEFORE %s
+
+BEFORE: very_long_bytecode_file_name.bc
+BEFORE-NEXT: evenlen
+BEFORE-NEXT: oddlen
+BEFORE-NEXT: IsNAN.o
+
+RUN: rm -f %t.a
+RUN: cp %p/Inputs/GNU.a %t.a
+RUN: llvm-ar ma evenlen %t.a very_long_bytecode_file_name.bc
+RUN: llvm-ar t %t.a | FileCheck --check-prefix=AFTER %s
+
+AFTER: evenlen
+AFTER-NEXT: very_long_bytecode_file_name.bc
+AFTER-NEXT: oddlen
+AFTER-NEXT: IsNAN.o
diff --git a/test/Object/archive-replace-pos.test b/test/Object/archive-replace-pos.test
new file mode 100644
index 0000000..0acead6
--- /dev/null
+++ b/test/Object/archive-replace-pos.test
@@ -0,0 +1,30 @@
+Test adding a member to a particular position
+
+RUN: touch %t.foo
+RUN: touch %t.bar
+RUN: rm -f %t.a
+RUN: llvm-ar rc %t.a %t.foo %t.bar
+RUN: touch %t.zed
+RUN: llvm-ar rca %t.foo %t.a %t.zed
+RUN: llvm-ar t %t.a | FileCheck %s
+
+CHECK: .foo
+CHECK-NEXT: .zed
+CHECK-NEXT: .bar
+
+RUN: rm -f %t.a
+RUN: llvm-ar rc %t.a %t.zed %t.foo %t.bar
+RUN: llvm-ar t %t.a | FileCheck --check-prefix=CHECK2 %s
+
+CHECK2: .zed
+CHECK2-NEXT: .foo
+CHECK2-NEXT: .bar
+
+RUN: llvm-ar rca %t.foo %t.a %t.zed
+RUN: llvm-ar t %t.a | FileCheck --check-prefix=CHECK3 %s
+CHECK3: .foo
+CHECK3-NEXT: .zed
+CHECK3-NEXT: .bar
+
+RUN: llvm-ar rc %t.a %t.zed
+RUN: llvm-ar t %t.a | FileCheck --check-prefix=CHECK3 %s
diff --git a/test/Object/archive-symtab.test b/test/Object/archive-symtab.test
new file mode 100644
index 0000000..0d2504d
--- /dev/null
+++ b/test/Object/archive-symtab.test
@@ -0,0 +1,50 @@
+RUN: rm -f %t.a
+RUN: llvm-ar rcs %t.a %p/Inputs/trivial-object-test.elf-x86-64 %p/Inputs/trivial-object-test2.elf-x86-64
+RUN: llvm-nm -s %t.a | FileCheck %s
+
+CHECK: Archive map
+CHECK-NEXT: main in trivial-object-test.elf-x86-64
+CHECK-NEXT: foo in trivial-object-test2.elf-x86-64
+CHECK-NEXT: main in trivial-object-test2.elf-x86-64
+CHECK-NOT: bar
+
+CHECK: trivial-object-test.elf-x86-64:
+CHECK-NEXT:         U SomeOtherFunction
+CHECK-NEXT: 00000000 T main
+CHECK-NEXT:         U puts
+CHECK-NEXT: trivial-object-test2.elf-x86-64:
+CHECK-NEXT: 00000000 t bar
+CHECK-NEXT: 00000006 T foo
+CHECK-NEXT: 00000016 T main
+
+RUN: rm -f %t.a
+RUN: llvm-ar rcS %t.a %p/Inputs/trivial-object-test.elf-x86-64 %p/Inputs/trivial-object-test2.elf-x86-64
+RUN: llvm-nm -s %t.a | FileCheck %s --check-prefix=NOMAP
+
+NOMAP-NOT: Archive map
+
+RUN: llvm-ar s %t.a
+RUN: llvm-nm -s %t.a | FileCheck %s
+
+check that the archive does have a corrupt symbol table.
+RUN: rm -f %t.a
+RUN: cp %p/Inputs/archive-test.a-corrupt-symbol-table %t.a
+RUN: llvm-nm -s %t.a | FileCheck %s --check-prefix=CORRUPT
+
+CORRUPT: Archive map
+CORRUPT-NEXT: mbin in trivial-object-test.elf-x86-64
+CORRUPT-NEXT: foo in trivial-object-test2.elf-x86-64
+CORRUPT-NEXT: main in trivial-object-test2.elf-x86-64
+
+CORRUPT: trivial-object-test.elf-x86-64:
+CORRUPT-NEXT:         U SomeOtherFunction
+CORRUPT-NEXT: 00000000 T main
+CORRUPT-NEXT:         U puts
+CORRUPT-NEXT: trivial-object-test2.elf-x86-64:
+CORRUPT-NEXT: 00000000 t bar
+CORRUPT-NEXT: 00000006 T foo
+CORRUPT-NEXT: 00000016 T main
+
+check that the we *don't* update the symbol table.
+RUN: llvm-ar s %t.a
+RUN: llvm-nm -s %t.a | FileCheck %s --check-prefix=CORRUPT
diff --git a/test/Object/archive-toc.test b/test/Object/archive-toc.test
new file mode 100644
index 0000000..0a5e72b
--- /dev/null
+++ b/test/Object/archive-toc.test
@@ -0,0 +1,28 @@
+Test reading an archive created by gnu ar
+RUN: env TZ=GMT llvm-ar tv %p/Inputs/GNU.a | FileCheck %s --check-prefix=GNU -strict-whitespace
+
+GNU:      rw-r--r-- 500/500      8 Nov 19 02:57 2004 evenlen
+GNU-NEXT: rw-r--r-- 500/500      7 Nov 19 02:57 2004 oddlen
+GNU-NEXT: rwxr-xr-x 500/500   1465 Nov 19 03:01 2004 very_long_bytecode_file_name.bc
+GNU-NEXT: rw-r--r-- 500/500   2280 Nov 19 03:04 2004 IsNAN.o
+
+
+Test reading an archive createdy by Mac OS X ar
+RUN: env TZ=GMT llvm-ar tv %p/Inputs/MacOSX.a | FileCheck %s --check-prefix=OSX -strict-whitespace
+
+OSX-NOT: __.SYMDEF
+OSX:      rw-r--r-- 501/501      8 Nov 19 02:57 2004 evenlen
+OSX-NEXT: rw-r--r-- 501/501      8 Nov 19 02:57 2004 oddlen
+OSX-NEXT: rw-r--r-- 502/502   1465 Feb  4 06:59 2010 very_long_bytecode_file_name.bc
+OSX-NEXT: rw-r--r-- 501/501   2280 Nov 19 04:32 2004 IsNAN.o
+
+Test reading an archive created on Solaris by /usr/ccs/bin/ar
+RUN: env TZ=GMT llvm-ar tv %p/Inputs/SVR4.a | FileCheck %s -strict-whitespace
+
+Test reading an archive created on Solaris by /usr/xpg4/bin/ar
+RUN: env TZ=GMT llvm-ar tv %p/Inputs/xpg4.a | FileCheck %s -strict-whitespace
+
+CHECK:      rw-r--r-- 1002/102      8 Nov 19 03:24 2004 evenlen
+CHECK-NEXT: rw-r--r-- 1002/102      7 Nov 19 03:24 2004 oddlen
+CHECK-NEXT: rwxr-xr-x 1002/102   1465 Nov 19 03:24 2004 very_long_bytecode_file_name.bc
+CHECK-NEXT: rw-r--r-- 1002/102   2280 Nov 19 03:24 2004 IsNAN.o
diff --git a/test/Object/archive-update.test b/test/Object/archive-update.test
new file mode 100644
index 0000000..20286d2
--- /dev/null
+++ b/test/Object/archive-update.test
@@ -0,0 +1,37 @@
+Test the 'u' option of llvm-ar
+
+REQUIRES: shell
+
+RUN: cd %T
+RUN: rm -f %t.a
+
+Create a file named evenlen that is newer than the evenlen on the source dir.
+RUN: mkdir -p %t.older
+RUN: echo older > %t.older/evenlen
+
+Either the shell supports the 'touch' command with a flag to manually set the
+mtime or we sleep for over a second so that the mtime is definitely observable.
+RUN: touch -m -t 200001010000 %t.older/evenlen || sleep 1.1
+
+RUN: mkdir -p %t.newer
+RUN: echo newer > %t.newer/evenlen
+RUN: touch %t.newer/evenlen
+
+Create an achive with the newest file
+RUN: llvm-ar r %t.a %t.newer/evenlen
+RUN: llvm-ar p %t.a | FileCheck --check-prefix=NEWER %s
+
+Check that without the 'u' option the member is replaced with an older file.
+RUN: llvm-ar r %t.a %t.older/evenlen
+RUN: llvm-ar p %t.a | FileCheck --check-prefix=OLDER %s
+
+Check that with the 'u' option the member is replaced with a newer file.
+RUN: llvm-ar ru %t.a %t.newer/evenlen
+RUN: llvm-ar p %t.a | FileCheck --check-prefix=NEWER %s
+
+Check that with the 'u' option the member is not replaced with an older file.
+RUN: llvm-ar ru %t.a %t.older/evenlen
+RUN: llvm-ar p %t.a | FileCheck --check-prefix=NEWER %s
+
+NEWER: newer
+OLDER: older
diff --git a/test/Archive/check_binary_output.ll b/test/Object/check_binary_output.ll
index 60ab5ca..567f18e 100644
--- a/test/Archive/check_binary_output.ll
+++ b/test/Object/check_binary_output.ll
@@ -1,4 +1,4 @@
 ; This is not an assembly file, this is just to run the test.
 ; The test verifies that llvm-ar produces a binary output.
 
-;RUN: llvm-ar p %p/GNU.a very_long_bytecode_file_name.bc | cmp -s %p/very_long_bytecode_file_name.bc -
+;RUN: llvm-ar p %p/Inputs/GNU.a very_long_bytecode_file_name.bc | cmp -s %p/Inputs/very_long_bytecode_file_name.bc -
diff --git a/test/Object/directory.ll b/test/Object/directory.ll
new file mode 100644
index 0000000..bf8ff32
--- /dev/null
+++ b/test/Object/directory.ll
@@ -0,0 +1,16 @@
+;RUN: rm -f %T/test.a
+;RUN: not llvm-ar r %T/test.a . 2>&1 | FileCheck %s
+;CHECK: .: Is a directory
+
+; Opening a directory works on cygwin and freebsd.
+;XFAIL: freebsd, cygwin
+
+;RUN: rm -f %T/test.a
+;RUN: touch %T/a-very-long-file-name
+;RUN: llvm-ar r %T/test.a %s %T/a-very-long-file-name
+;RUN: llvm-ar r %T/test.a %T/a-very-long-file-name
+;RUN: llvm-ar t %T/test.a | FileCheck -check-prefix=MEMBERS %s
+;MEMBERS-NOT: /
+;MEMBERS: directory.ll
+;MEMBERS: a-very-long-file-name
+;MEMBERS-NOT: a-very-long-file-name
diff --git a/test/Object/extract.ll b/test/Object/extract.ll
new file mode 100644
index 0000000..4e519ae
--- /dev/null
+++ b/test/Object/extract.ll
@@ -0,0 +1,46 @@
+; This isn't really an assembly file, its just here to run the test.
+
+; This test just makes sure that llvm-ar can extract bytecode members
+; from various style archives.
+
+; REQUIRES: shell
+
+; RUN: cd %T
+
+; RUN: rm -f very_long_bytecode_file_name.bc
+; RUN: llvm-ar p %p/Inputs/GNU.a very_long_bytecode_file_name.bc | \
+; RUN:   cmp -s %p/Inputs/very_long_bytecode_file_name.bc -
+; RUN: llvm-ar x %p/Inputs/GNU.a very_long_bytecode_file_name.bc
+; RUN: cmp -s %p/Inputs/very_long_bytecode_file_name.bc \
+; RUN:        very_long_bytecode_file_name.bc
+
+; RUN: rm -f very_long_bytecode_file_name.bc
+; RUN: llvm-ar p %p/Inputs/MacOSX.a very_long_bytecode_file_name.bc | \
+; RUN:   cmp -s %p/Inputs/very_long_bytecode_file_name.bc -
+; RUN: llvm-ar x %p/Inputs/MacOSX.a very_long_bytecode_file_name.bc
+; RUN: cmp -s %p/Inputs/very_long_bytecode_file_name.bc \
+; RUN:        very_long_bytecode_file_name.bc
+
+; RUN: rm -f very_long_bytecode_file_name.bc
+; RUN: llvm-ar p %p/Inputs/SVR4.a very_long_bytecode_file_name.bc | \
+; RUN:   cmp -s %p/Inputs/very_long_bytecode_file_name.bc -
+; RUN: llvm-ar x %p/Inputs/SVR4.a very_long_bytecode_file_name.bc
+; RUN: cmp -s %p/Inputs/very_long_bytecode_file_name.bc \
+; RUN:        very_long_bytecode_file_name.bc
+
+; RUN: rm -f very_long_bytecode_file_name.bc
+; RUN: llvm-ar p %p/Inputs/xpg4.a very_long_bytecode_file_name.bc |\
+; RUN:   cmp -s %p/Inputs/very_long_bytecode_file_name.bc -
+; RUN: llvm-ar x %p/Inputs/xpg4.a very_long_bytecode_file_name.bc
+; RUN: cmp -s %p/Inputs/very_long_bytecode_file_name.bc \
+; RUN:        very_long_bytecode_file_name.bc
+
+
+; Test that the 'o' option is working by extracting a file, putting it in o
+; new archive and checking that date.
+; RUN: rm -f very_long_bytecode_file_name.bc
+; RUN: llvm-ar xo %p/Inputs/GNU.a very_long_bytecode_file_name.bc
+; RUN: llvm-ar rc %t.a very_long_bytecode_file_name.bc
+; RUN: env TZ=GMT llvm-ar tv %t.a | FileCheck %s
+
+CHECK: 1465 Nov 19 03:01 2004 very_long_bytecode_file_name.bc
diff --git a/test/Object/lit.local.cfg b/test/Object/lit.local.cfg
index b2439b2..d74d039 100644
--- a/test/Object/lit.local.cfg
+++ b/test/Object/lit.local.cfg
@@ -1 +1 @@
-config.suffixes = ['.test', '.ll']
+config.suffixes = ['.test', '.ll', '.yaml']
diff --git a/test/Object/nm-archive.test b/test/Object/nm-archive.test
index 2d96b73..0d43cc7 100644
--- a/test/Object/nm-archive.test
+++ b/test/Object/nm-archive.test
@@ -1,9 +1,5 @@
 RUN: llvm-nm %p/Inputs/archive-test.a-coff-i386 \
 RUN:         | FileCheck %s -check-prefix COFF
-RUN: llvm-as %p/Inputs/trivial.ll -o=%t1
-RUN: llvm-ar rcs %t2 %t1
-RUN: llvm-nm %t2 | FileCheck %s -check-prefix BITCODE
-
 
 COFF: trivial-object-test.coff-i386:
 COFF-NEXT: 00000000 d .data
@@ -13,6 +9,27 @@ COFF-NEXT:          U _SomeOtherFunction
 COFF-NEXT: 00000000 T _main
 COFF-NEXT:          U _puts
 
+
+RUN: llvm-as %p/Inputs/trivial.ll -o=%t1
+RUN: rm -f %t2
+RUN: llvm-ar rcs %t2 %t1
+RUN: llvm-nm %t2 | FileCheck %s -check-prefix BITCODE
+
 BITCODE:          U SomeOtherFunction
 BITCODE-NEXT:          T main
 BITCODE-NEXT:          U puts
+
+
+Test we don't error with an archive with no symtab.
+RUN: llvm-nm %p/Inputs/archive-test.a-gnu-no-symtab
+
+
+Or in an archive with no symtab or string table.
+RUN: llvm-nm %p/Inputs/archive-test.a-gnu-minimal
+
+
+And don't crash when asked to print a non existing symtab.
+RUN: llvm-nm -s %p/Inputs/archive-test.a-gnu-minimal
+
+Don't reject an empty archive.
+RUN: llvm-nm %p/Inputs/archive-test.a-empty
diff --git a/test/Object/nm-error.test b/test/Object/nm-error.test
new file mode 100644
index 0000000..146b887
--- /dev/null
+++ b/test/Object/nm-error.test
@@ -0,0 +1,17 @@
+Test that llvm-nm returns an error because of the unknown file type, but
+keeps processing subsequent files.
+
+Note: We use a temporary file since the tests don't run with pipefail.
+
+RUN: touch %t
+RUN: not llvm-nm %p/Inputs/trivial-object-test.elf-i386 %t \
+RUN:             %p/Inputs/trivial-object-test.elf-i386 > %t.log
+RUN: FileCheck %s < %t.log
+
+CHECK:          U SomeOtherFunction
+CHECK: 00000000 T main
+CHECK:          U puts
+
+CHECK:          U SomeOtherFunction
+CHECK: 00000000 T main
+CHECK:          U puts
diff --git a/test/Object/nm-trivial-object.test b/test/Object/nm-trivial-object.test
index 5c3cc31..d517745 100644
--- a/test/Object/nm-trivial-object.test
+++ b/test/Object/nm-trivial-object.test
@@ -18,6 +18,7 @@ COFF:          U {{_?}}SomeOtherFunction
 COFF: 00000000 T {{_?}}main
 COFF:          U {{_?}}puts
 
+ELF-NOT:      U
 ELF:          U SomeOtherFunction
 ELF: 00000000 T main
 ELF:          U puts
diff --git a/test/Object/nm-universal-binary.test b/test/Object/nm-universal-binary.test
new file mode 100644
index 0000000..8febfdf
--- /dev/null
+++ b/test/Object/nm-universal-binary.test
@@ -0,0 +1,6 @@
+RUN: llvm-nm %p/Inputs/macho-universal.x86_64.i386 | FileCheck %s
+
+CHECK: macho-universal.x86_64.i386:x86_64
+CHECK: main
+CHECK: macho-universal.x86_64.i386:i386
+CHECK: main
diff --git a/test/Object/yaml2obj-elf-file-headers.yaml b/test/Object/yaml2obj-elf-file-headers.yaml
new file mode 100644
index 0000000..2851701
--- /dev/null
+++ b/test/Object/yaml2obj-elf-file-headers.yaml
@@ -0,0 +1,11 @@
+# RUN: yaml2obj -format=elf %s | llvm-readobj -file-headers - | FileCheck %s
+!ELF
+FileHeader:
+  Class: ELFCLASS64
+  Data: ELFDATA2LSB
+  OSABI: ELFOSABI_GNU
+  Type: ET_REL
+  Machine: EM_X86_64
+
+# CHECK: OS/ABI: GNU/Linux
+# CHECK: Type: Relocatable
diff --git a/test/Object/yaml2obj-elf-section-basic.yaml b/test/Object/yaml2obj-elf-section-basic.yaml
new file mode 100644
index 0000000..34be11d
--- /dev/null
+++ b/test/Object/yaml2obj-elf-section-basic.yaml
@@ -0,0 +1,35 @@
+# RUN: yaml2obj -format=elf %s | llvm-readobj -sections -section-data - | FileCheck %s
+!ELF
+FileHeader:
+  Class: ELFCLASS64
+  Data: ELFDATA2LSB
+  Type: ET_REL
+  Machine: EM_X86_64
+Sections:
+  - Name: .text
+    Type: SHT_PROGBITS
+    Flags: [ SHF_ALLOC, SHF_EXECINSTR ]
+    Address: 0xCAFEBABE
+    Link: .text # Doesn't make sense for SHT_PROGBITS, but good enough for test.
+    Content: EBFE
+    AddressAlign: 2
+
+# CHECK:        Section {
+# CHECK:          Index: 0
+# CHECK:          Type: SHT_NULL (0x0)
+#
+# CHECK:        Section {
+# CHECK:          Name: .text
+# CHECK:          Type: SHT_PROGBITS (0x1)
+# CHECK-NEXT:     Flags [ (0x6)
+# CHECK-NEXT:       SHF_ALLOC (0x2)
+# CHECK-NEXT:       SHF_EXECINSTR (0x4)
+# CHECK-NEXT:     ]
+# CHECK-NEXT:     Address: 0xCAFEBABE
+# CHECK:          Size: 2
+# Check that Link != 0.
+# CHECK:          Link: {{[1-9][0-9]*}}
+# CHECK:          AddressAlignment: 2
+# CHECK:          SectionData (
+# CHECK-NEXT:       0000: EBFE
+# CHECK-NEXT:     )
diff --git a/test/Object/yaml2obj-elf-symbol-LocalGlobalWeak.yaml b/test/Object/yaml2obj-elf-symbol-LocalGlobalWeak.yaml
new file mode 100644
index 0000000..3c4e830
--- /dev/null
+++ b/test/Object/yaml2obj-elf-symbol-LocalGlobalWeak.yaml
@@ -0,0 +1,37 @@
+# RUN: yaml2obj -format=elf %s | llvm-readobj -symbols - | FileCheck %s
+!ELF
+FileHeader:
+  Class: ELFCLASS64
+  Data: ELFDATA2LSB
+  Type: ET_REL
+  Machine: EM_X86_64
+Sections:
+  - Name: .data
+    Type: SHT_PROGBITS
+    Flags: [ SHF_ALLOC, SHF_WRITE ]
+    Content: "DEADBEEF"
+Symbols:
+  Local:
+    - Name: local_symbol
+      Type: STT_OBJECT
+      Section: .data
+  Global:
+    - Name: global_symbol
+      Type: STT_OBJECT
+      Section: .data
+  Weak:
+    - Name: weak_symbol
+      Type: STT_OBJECT
+      Section: .data
+
+# CHECK: Symbol {
+# CHECK:   Name:  (0)
+# CHECK: Symbol {
+# CHECK:   Name: local_symbol
+# CHECK:   Binding: Local
+# CHECK: Symbol {
+# CHECK:   Name: global_symbol
+# CHECK:   Binding: Global
+# CHECK: Symbol {
+# CHECK:   Name: weak_symbol
+# CHECK:   Binding: Weak
diff --git a/test/Object/yaml2obj-elf-symbol-basic.yaml b/test/Object/yaml2obj-elf-symbol-basic.yaml
new file mode 100644
index 0000000..3fb9b17
--- /dev/null
+++ b/test/Object/yaml2obj-elf-symbol-basic.yaml
@@ -0,0 +1,40 @@
+# RUN: yaml2obj -format=elf %s | llvm-readobj -symbols - | FileCheck %s
+!ELF
+FileHeader:
+  Class: ELFCLASS64
+  Data: ELFDATA2LSB
+  Type: ET_REL
+  Machine: EM_X86_64
+Sections:
+  - Name: .text
+    Type: SHT_PROGBITS
+    Flags: [ SHF_ALLOC, SHF_EXECINSTR ]
+    Content: "90EBFE" # x86 machine code
+                      #   NOP ; To make main's `Value` non-zero (for testing).
+                      # main:
+                      #   JMP -2 ; (infloop)
+                      # This YAML file is a valid relocatable object that,
+                      # when linked and run on x86_64, will go into an
+                      # infloop.
+Symbols:
+  Global:
+    - Name: main
+      Type: STT_FUNC
+      Section: .text
+      Value: 0x1
+      Size: 2
+    - Name: undefined_symbol
+
+# CHECK:      Symbols [
+# CHECK-NEXT:   Symbol {
+# CHECK-NEXT:     Name:  (0)
+# CHECK:        Symbol {
+# CHECK-NEXT:     Name: main
+# CHECK-NEXT:     Value: 0x1
+# CHECK-NEXT:     Size: 2
+# CHECK:          Binding: Global
+# CHECK-NEXT:     Type: Function
+# CHECK:          Section: .text
+# CHECK:        Symbol {
+# CHECK:          Name: undefined_symbol
+# CHECK:          Section:  (0x0)
diff --git a/test/Other/Inputs/TestProg/TestProg b/test/Other/Inputs/TestProg/TestProg
new file mode 100755
index 0000000..1c4efba
--- /dev/null
+++ b/test/Other/Inputs/TestProg/TestProg
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+false
diff --git a/test/Other/Inputs/llvm-cov.gcda b/test/Other/Inputs/llvm_cov.gcda
index 9ae2286..9ae2286 100644
--- a/test/Other/Inputs/llvm-cov.gcda
+++ b/test/Other/Inputs/llvm_cov.gcda
diff --git a/test/Other/Inputs/llvm-cov.gcno b/test/Other/Inputs/llvm_cov.gcno
index 25e2023..25e2023 100644
--- a/test/Other/Inputs/llvm-cov.gcno
+++ b/test/Other/Inputs/llvm_cov.gcno
diff --git a/test/Other/ResponseFile.ll b/test/Other/ResponseFile.ll
index b8b3d0a..914e548 100644
--- a/test/Other/ResponseFile.ll
+++ b/test/Other/ResponseFile.ll
@@ -1,5 +1,9 @@
-; RUN: echo %s > %t.list
-; RUN: llvm-as @%t.list -o %t.bc
+; Test that we can recurse, at least a little bit.  The -time-passes flag here
+; is a hack to make sure that neither echo nor the shell expands the response
+; file for us.  Tokenization with quotes is tested in unittests.
+; RUN: echo %s > %t.list1
+; RUN: echo "-time-passes @%t.list1" > %t.list2
+; RUN: llvm-as @%t.list2 -o %t.bc
 ; RUN: llvm-nm %t.bc 2>&1 | FileCheck %s
 
 ; CHECK: T foobar
diff --git a/test/Other/can-execute.txt b/test/Other/can-execute.txt
new file mode 100644
index 0000000..fd6961f
--- /dev/null
+++ b/test/Other/can-execute.txt
@@ -0,0 +1,20 @@
+REQUIRES: can-execute
+
+This tests that we abstract two peculiarities of unix in can_execute:
+
+* Directories are executable, but we don't want to try to execute them.
+* For shell scripts, we also need to be able to read them.
+
+The PATH is constructed such that 'not' will first find a directory named
+TestProg, then a file with executable bit but not readable and finally a
+shell script which always returns false, which is what it actually tries to
+execute.
+
+If we want, it is probably OK to change the semantics of can_execute and this
+test, but for now this test serves as a reminder to audit all the callers if
+we do that.
+
+RUN: cp -f %S/Inputs/TestProg/TestProg %T/TestProg
+RUN: chmod 111 %T/TestProg
+RUN: export PATH=%S/Inputs:%T:%S/Inputs/TestProg:$PATH
+RUN: not TestProg
diff --git a/test/Other/lit.local.cfg b/test/Other/lit.local.cfg
index 2693077..67c7ec7 100644
--- a/test/Other/lit.local.cfg
+++ b/test/Other/lit.local.cfg
@@ -1 +1 @@
-config.suffixes = ['.ll', '.c', '.cpp', '.txt']
+config.suffixes = ['.ll', '.c', '.cpp', '.txt', '.test']
diff --git a/test/Other/llvm-cov.test b/test/Other/llvm-cov.test
index c0aa203..2ac4e9e 100644
--- a/test/Other/llvm-cov.test
+++ b/test/Other/llvm-cov.test
@@ -1,3 +1,4 @@
 PR11760
-RUN: llvm-cov -gcda=%S/Inputs/llvm-cov.gcda -gcno=%S/Inputs/llvm-cov.gcno
-
+RUN: llvm-cov -gcda=%S/Inputs/llvm_cov.gcda -gcno=%S/Inputs/llvm_cov.gcno
+REQUIRES: asserts
+XFAIL: *
diff --git a/test/Other/pipefail.txt b/test/Other/pipefail.txt
new file mode 100644
index 0000000..241080a
--- /dev/null
+++ b/test/Other/pipefail.txt
@@ -0,0 +1,2 @@
+REQUIRES: shell
+RUN: ((false | true) && echo true || echo false) | grep false
diff --git a/test/Other/umask.ll b/test/Other/umask.ll
new file mode 100644
index 0000000..af9710e
--- /dev/null
+++ b/test/Other/umask.ll
@@ -0,0 +1,14 @@
+; REQUIRES: shell
+; XFAIL: mingw32
+
+; RUN: umask 000
+; RUN: rm -f %t.000
+; RUN: llvm-as %s -o %t.000
+; RUN: ls -l %t.000 | FileCheck --check-prefix=CHECK000 %s
+; CHECK000: rw-rw-rw
+
+; RUN: umask 002
+; RUN: rm -f %t.002
+; RUN: llvm-as %s -o %t.002
+; RUN: ls -l %t.002 | FileCheck --check-prefix=CHECK002 %s
+; CHECK002: rw-rw-r-
diff --git a/test/TableGen/intrinsic-order.td b/test/TableGen/intrinsic-order.td
new file mode 100644
index 0000000..5eadf60
--- /dev/null
+++ b/test/TableGen/intrinsic-order.td
@@ -0,0 +1,35 @@
+// RUN: llvm-tblgen -gen-intrinsic %s | FileCheck %s
+
+class IntrinsicProperty;
+
+class ValueType<int size, int value> {
+  string Namespace = "MVT";
+  int Size = size;
+  int Value = value;
+}
+
+class LLVMType<ValueType vt> {
+  ValueType VT = vt;
+}
+
+class Intrinsic<string name, list<LLVMType> param_types = []> {
+  string LLVMName = name;
+  bit isTarget = 0;
+  string TargetPrefix = "";
+  list<LLVMType> RetTypes = [];
+  list<LLVMType> ParamTypes = param_types;
+  list<IntrinsicProperty> Properties = [];
+}
+
+def iAny : ValueType<0, 254>;
+def llvm_anyint_ty : LLVMType<iAny>;
+
+
+// Make sure an intrinsic name that is a prefix of another is checked after the
+// other.
+
+// CHECK: if (NameR.startswith("oo.bar.")) return Intrinsic::foo_bar;
+// CHECK: if (NameR.startswith("oo.")) return Intrinsic::foo;
+
+def int_foo : Intrinsic<"llvm.foo", [llvm_anyint_ty]>;
+def int_foo_bar : Intrinsic<"llvm.foo.bar", [llvm_anyint_ty]>;
diff --git a/test/Transforms/BBVectorize/X86/cmp-types.ll b/test/Transforms/BBVectorize/X86/cmp-types.ll
index a4fcbb6..fc1da1b 100644
--- a/test/Transforms/BBVectorize/X86/cmp-types.ll
+++ b/test/Transforms/BBVectorize/X86/cmp-types.ll
@@ -11,6 +11,6 @@ entry:
   %tobool21 = icmp ne %"struct.btSoftBody"* %n2, null
   %cond22 = zext i1 %tobool21 to i32
   ret void
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 }
 
diff --git a/test/Transforms/BBVectorize/X86/loop1.ll b/test/Transforms/BBVectorize/X86/loop1.ll
index bbf565d..4018084 100644
--- a/test/Transforms/BBVectorize/X86/loop1.ll
+++ b/test/Transforms/BBVectorize/X86/loop1.ll
@@ -7,8 +7,8 @@ target triple = "x86_64-unknown-linux-gnu"
 define void @test1(double* noalias %out, double* noalias %in1, double* noalias %in2) nounwind uwtable {
 entry:
   br label %for.body
-; CHECK: @test1
-; CHECK-UNRL: @test1
+; CHECK-LABEL: @test1(
+; CHECK-UNRL-LABEL: @test1(
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
diff --git a/test/Transforms/BBVectorize/X86/sh-rec.ll b/test/Transforms/BBVectorize/X86/sh-rec.ll
index 1e0492c..ad75fc9 100644
--- a/test/Transforms/BBVectorize/X86/sh-rec.ll
+++ b/test/Transforms/BBVectorize/X86/sh-rec.ll
@@ -46,7 +46,7 @@ if.end10:                                         ; preds = %entry
 
 return:                                           ; preds = %entry
   ret void
-; CHECK: @ptoa
+; CHECK-LABEL: @ptoa(
 }
 
 declare noalias i8* @malloc() nounwind
diff --git a/test/Transforms/BBVectorize/X86/sh-rec2.ll b/test/Transforms/BBVectorize/X86/sh-rec2.ll
index ef22399..d65ac1c 100644
--- a/test/Transforms/BBVectorize/X86/sh-rec2.ll
+++ b/test/Transforms/BBVectorize/X86/sh-rec2.ll
@@ -77,7 +77,7 @@ entry:
   %and390 = shl i8 %conv3898, 6
   store i8 %and390, i8* %incdec.ptr387, align 1
   unreachable
-; CHECK: @gsm_encode
+; CHECK-LABEL: @gsm_encode(
 }
 
 declare void @Gsm_Coder(%struct.gsm_state.2.8.14.15.16.17.19.22.23.25.26.28.29.31.32.33.35.36.37.38.40.41.42.44.45.47.48.50.52.53.54.56.57.58.59.60.61.62.63.66.73.83.84.89.90.91.92.93.94.95.96.99.100.101.102.103.104.106.107.114.116.121.122.129.130.135.136.137.138.139.140.141.142.143.144.147.148.149.158.159.160.161.164.165.166.167.168.169.172.179.181.182.183.188.195.200.201.202.203.204.205.208.209.210.212.213.214.215.222.223.225.226.230.231.232.233.234.235.236.237.238.239.240.241.242.243.244.352*, i16*, i16*, i16*, i16*, i16*, i16*, i16*)
diff --git a/test/Transforms/BBVectorize/X86/sh-rec3.ll b/test/Transforms/BBVectorize/X86/sh-rec3.ll
index fd2cc8b..ad880ed 100644
--- a/test/Transforms/BBVectorize/X86/sh-rec3.ll
+++ b/test/Transforms/BBVectorize/X86/sh-rec3.ll
@@ -162,7 +162,7 @@ entry:
   %conv365 = trunc i32 %or364 to i8
   store i8 %conv365, i8* %incdec.ptr350, align 1
   unreachable
-; CHECK: @gsm_encode
+; CHECK-LABEL: @gsm_encode(
 }
 
 declare void @Gsm_Coder(%struct.gsm_state.2.8.39.44.45.55.56.57.58.59.62.63.64.65.74.75.76.77.80.87.92.93.94.95.96.97.110.111.112.113.114.128.130.135.136.137.138.139.140.141.142.143.144.145.148.149.150.151.152.169.170.177.178.179.184.185.186.187.188.201.208.209.219.220.221.223.224.225.230.231.232.233.235.236.237.238.245.246.248.249.272.274.279.280.281.282.283.286.293.298.299.314.315.316.317.318.319.320.321.322.323.324.325.326.327.328.329.330.331.332.333.334.335.336.337.338.339.340.341.342.343.344.345.346.347.348.349.350.351.352.353.565*, i16*, i16*, i16*, i16*, i16*, i16*, i16*)
diff --git a/test/Transforms/BBVectorize/X86/sh-types.ll b/test/Transforms/BBVectorize/X86/sh-types.ll
index 0bcb714..fbff2fb 100644
--- a/test/Transforms/BBVectorize/X86/sh-types.ll
+++ b/test/Transforms/BBVectorize/X86/sh-types.ll
@@ -18,7 +18,7 @@ define <4 x float> @test7(<4 x float> %A1, <4 x float> %B1, double %C1, double %
 
         %R = fmul <4 x float> %Y1, %Y2
         ret <4 x float> %R
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NOT: <8 x float>
 ; CHECK: ret <4 x float>
 }
diff --git a/test/Transforms/BBVectorize/X86/simple-int.ll b/test/Transforms/BBVectorize/X86/simple-int.ll
index f5dbe46..7842ec8 100644
--- a/test/Transforms/BBVectorize/X86/simple-int.ll
+++ b/test/Transforms/BBVectorize/X86/simple-int.ll
@@ -16,7 +16,7 @@ define double @test1(double %A1, double %A2, double %B1, double %B2, double %C1,
 	%Z2 = fadd double %Y2, %B2
 	%R  = fmul double %Z1, %Z2
 	ret double %R
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret double %R
 }
 
@@ -30,7 +30,7 @@ define double @test1a(double %A1, double %A2, double %B1, double %B2, double %C1
 	%Z2 = fadd double %Y2, %B2
 	%R  = fmul double %Z1, %Z2
 	ret double %R
-; CHECK: @test1a
+; CHECK-LABEL: @test1a(
 ; CHECK: ret double %R
 }
 
@@ -44,7 +44,7 @@ define double @test2(double %A1, double %A2, double %B1, double %B2) {
 	%Z2 = fadd double %Y2, %B2
 	%R  = fmul double %Z1, %Z2
 	ret double %R
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: ret double %R
 }
 
@@ -58,7 +58,7 @@ define double @test3(double %A1, double %A2, double %B1, double %B2, i32 %P) {
 	%Z2 = fadd double %Y2, %B2
 	%R  = fmul double %Z1, %Z2
 	ret double %R
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: ret double %R
 }
 
@@ -73,7 +73,7 @@ define double @test4(double %A1, double %A2, double %B1, double %B2, i32 %P) {
 	%Z2 = fadd double %Y2, %B2
 	%R  = fmul double %Z1, %Z2
 	ret double %R
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: ret double %R
 }
 
diff --git a/test/Transforms/BBVectorize/X86/simple-ldstr.ll b/test/Transforms/BBVectorize/X86/simple-ldstr.ll
index 0124399..1abbc34 100644
--- a/test/Transforms/BBVectorize/X86/simple-ldstr.ll
+++ b/test/Transforms/BBVectorize/X86/simple-ldstr.ll
@@ -16,7 +16,7 @@ entry:
   %arrayidx5 = getelementptr inbounds double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   ret void
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %i0.v.i0 = bitcast double* %a to <2 x double>*
 ; CHECK: %i1.v.i0 = bitcast double* %b to <2 x double>*
 ; CHECK: %i0 = load <2 x double>* %i0.v.i0, align 8
diff --git a/test/Transforms/BBVectorize/X86/simple.ll b/test/Transforms/BBVectorize/X86/simple.ll
index 8abfa5f..a11e309 100644
--- a/test/Transforms/BBVectorize/X86/simple.ll
+++ b/test/Transforms/BBVectorize/X86/simple.ll
@@ -11,7 +11,7 @@ define double @test1(double %A1, double %A2, double %B1, double %B2) {
 	%Z2 = fadd double %Y2, %B2
 	%R  = fmul double %Z1, %Z2
 	ret double %R
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: fsub <2 x double>
 ; CHECK: fmul <2 x double>
 ; CHECK: fadd <2 x double>
@@ -38,7 +38,7 @@ define double @test1a(double %A1, double %A2, double %B1, double %B2) {
 	%S2 = fadd double %W2, %Q2
 	%R  = fmul double %S1, %S2
 	ret double %R
-; CHECK: @test1a
+; CHECK-LABEL: @test1a(
 ; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0
 ; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1
 ; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0
@@ -66,7 +66,7 @@ define double @test2(double %A1, double %A2, double %B1, double %B2) {
 	%Z2 = fadd double %Y1, %B2
 	%R  = fmul double %Z1, %Z2
 	ret double %R
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: insertelement
 ; CHECK: insertelement
 ; CHECK: insertelement
@@ -88,7 +88,7 @@ define double @test4(double %A1, double %A2, double %B1, double %B2) {
 	%W2 = fadd double %Y1, %Z2
 	%R  = fmul double %Z1, %Z2
 	ret double %R
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: insertelement
 ; CHECK: insertelement
 ; CHECK: insertelement
@@ -113,7 +113,7 @@ define <8 x i8> @test6(<8 x i8> %A1, <8 x i8> %A2, <8 x i8> %B1, <8 x i8> %B2) {
         %Q2 = shufflevector <8 x i8> %Z2, <8 x i8> %Z2, <8 x i32> <i32 6, i32 7, i32 0, i32 1, i32 2, i32 4, i32 4, i32 1>
 	%R  = mul <8 x i8> %Q1, %Q2
 	ret <8 x i8> %R
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NOT: sub <16 x i8>
 ; CHECK: ret <8 x i8>
 }
diff --git a/test/Transforms/BBVectorize/X86/vs-cast.ll b/test/Transforms/BBVectorize/X86/vs-cast.ll
index be3efca..0c666b1 100644
--- a/test/Transforms/BBVectorize/X86/vs-cast.ll
+++ b/test/Transforms/BBVectorize/X86/vs-cast.ll
@@ -7,6 +7,6 @@ entry:
   %0 = bitcast <2 x i64> undef to i128
   %1 = bitcast <2 x i64> undef to i128
   ret void
-; CHECK: @main
+; CHECK-LABEL: @main(
 }
 
diff --git a/test/Transforms/BBVectorize/cycle.ll b/test/Transforms/BBVectorize/cycle.ll
index bdcb30d..6bfa625 100644
--- a/test/Transforms/BBVectorize/cycle.ll
+++ b/test/Transforms/BBVectorize/cycle.ll
@@ -105,7 +105,7 @@ go:
   br i1 %or.cond, label %done, label %go
 done:
   ret void
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: go:
 ; CHECK: %conv.v.i0.1 = insertelement <2 x i32> undef, i32 %n.0, i32 0
 ; FIXME: When tree pruning is deterministic, include the entire output.
diff --git a/test/Transforms/BBVectorize/ld1.ll b/test/Transforms/BBVectorize/ld1.ll
index ea5cb5d..9c79eef 100644
--- a/test/Transforms/BBVectorize/ld1.ll
+++ b/test/Transforms/BBVectorize/ld1.ll
@@ -22,7 +22,7 @@ entry:
   %add15 = fadd double %mul13, %i5
   %mul16 = fmul double %add11, %add15
   ret double %mul16
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %i0.v.i0 = bitcast double* %a to <2 x double>*
 ; CHECK: %i1.v.i0 = bitcast double* %b to <2 x double>*
 ; CHECK: %i2.v.i0 = bitcast double* %c to <2 x double>*
diff --git a/test/Transforms/BBVectorize/loop1.ll b/test/Transforms/BBVectorize/loop1.ll
index e592edb..ed7be15 100644
--- a/test/Transforms/BBVectorize/loop1.ll
+++ b/test/Transforms/BBVectorize/loop1.ll
@@ -7,8 +7,8 @@ target triple = "x86_64-unknown-linux-gnu"
 define void @test1(double* noalias %out, double* noalias %in1, double* noalias %in2) nounwind uwtable {
 entry:
   br label %for.body
-; CHECK: @test1
-; CHECK-UNRL: @test1
+; CHECK-LABEL: @test1(
+; CHECK-UNRL-LABEL: @test1(
 
 for.body:                                         ; preds = %for.body, %entry
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
diff --git a/test/Transforms/BBVectorize/mem-op-depth.ll b/test/Transforms/BBVectorize/mem-op-depth.ll
index 84f16bd..c31d452 100644
--- a/test/Transforms/BBVectorize/mem-op-depth.ll
+++ b/test/Transforms/BBVectorize/mem-op-depth.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-unknown-linux-gnu"
 @B = common global [1024 x float] zeroinitializer, align 16
 
 define i32 @test1() nounwind {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
   %V1 = load float* getelementptr inbounds ([1024 x float]* @A, i64 0, i64 0), align 16
   %V2 = load float* getelementptr inbounds ([1024 x float]* @A, i64 0, i64 1), align 4
   %V3= load float* getelementptr inbounds ([1024 x float]* @A, i64 0, i64 2), align 8
diff --git a/test/Transforms/BBVectorize/metadata.ll b/test/Transforms/BBVectorize/metadata.ll
index 1e3aaa1..ac7297d 100644
--- a/test/Transforms/BBVectorize/metadata.ll
+++ b/test/Transforms/BBVectorize/metadata.ll
@@ -16,7 +16,7 @@ entry:
   %arrayidx5 = getelementptr inbounds double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   ret void
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: !fpmath
 ; CHECK: ret void
 }
@@ -36,7 +36,7 @@ entry:
   %arrayidx5 = getelementptr inbounds i64* %c, i64 1
   store i64 %mul5, i64* %arrayidx5, align 8
   ret void
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NOT: !range
 ; CHECK: ret void
 }
diff --git a/test/Transforms/BBVectorize/no-ldstr-conn.ll b/test/Transforms/BBVectorize/no-ldstr-conn.ll
index ada2a71..bcc5ce7 100644
--- a/test/Transforms/BBVectorize/no-ldstr-conn.ll
+++ b/test/Transforms/BBVectorize/no-ldstr-conn.ll
@@ -17,7 +17,7 @@ entry:
   store i64 %v3a, i64* %a3, align 8
   %r = add i64 %v2, %v3
   ret i64 %r
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NOT: getelementptr <2 x i64*>
 }
 
diff --git a/test/Transforms/BBVectorize/req-depth.ll b/test/Transforms/BBVectorize/req-depth.ll
index e012005..2675354 100644
--- a/test/Transforms/BBVectorize/req-depth.ll
+++ b/test/Transforms/BBVectorize/req-depth.ll
@@ -9,8 +9,8 @@ define double @test1(double %A1, double %A2, double %B1, double %B2) {
 	%Y2 = fmul double %X2, %A2
 	%R  = fmul double %Y1, %Y2
 	ret double %R
-; CHECK-RD3: @test1
-; CHECK-RD2: @test1
+; CHECK-RD3-LABEL: @test1(
+; CHECK-RD2-LABEL: @test1(
 ; CHECK-RD3-NOT: <2 x double>
 ; CHECK-RD2: <2 x double>
 }
diff --git a/test/Transforms/BBVectorize/search-limit.ll b/test/Transforms/BBVectorize/search-limit.ll
index a694e45..be38d34 100644
--- a/test/Transforms/BBVectorize/search-limit.ll
+++ b/test/Transforms/BBVectorize/search-limit.ll
@@ -3,8 +3,8 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; RUN: opt < %s -bb-vectorize -bb-vectorize-req-chain-depth=3 -bb-vectorize-search-limit=4 -bb-vectorize-ignore-target-info -instcombine -gvn -S | FileCheck %s -check-prefix=CHECK-SL4
 
 define double @test1(double %A1, double %A2, double %B1, double %B2) {
-; CHECK: @test1
-; CHECK-SL4: @test1
+; CHECK-LABEL: @test1(
+; CHECK-SL4-LABEL: @test1(
 ; CHECK-SL4-NOT: <2 x double>
 ; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0
 ; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1
diff --git a/test/Transforms/BBVectorize/simple-int.ll b/test/Transforms/BBVectorize/simple-int.ll
index e4d5152..e33ac61 100644
--- a/test/Transforms/BBVectorize/simple-int.ll
+++ b/test/Transforms/BBVectorize/simple-int.ll
@@ -16,7 +16,7 @@ define double @test1(double %A1, double %A2, double %B1, double %B2, double %C1,
 	%Z2 = fadd double %Y2, %B2
 	%R  = fmul double %Z1, %Z2
 	ret double %R
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0
 ; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1
 ; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0
@@ -42,7 +42,7 @@ define double @test1a(double %A1, double %A2, double %B1, double %B2, double %C1
 	%Z2 = fadd double %Y2, %B2
 	%R  = fmul double %Z1, %Z2
 	ret double %R
-; CHECK: @test1a
+; CHECK-LABEL: @test1a(
 ; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0
 ; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1
 ; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0
@@ -68,7 +68,7 @@ define double @test2(double %A1, double %A2, double %B1, double %B2) {
 	%Z2 = fadd double %Y2, %B2
 	%R  = fmul double %Z1, %Z2
 	ret double %R
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0
 ; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1
 ; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0
@@ -93,7 +93,7 @@ define double @test3(double %A1, double %A2, double %B1, double %B2, i32 %P) {
 	%Z2 = fadd double %Y2, %B2
 	%R  = fmul double %Z1, %Z2
 	ret double %R
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0
 ; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1
 ; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0
@@ -119,7 +119,7 @@ define double @test4(double %A1, double %A2, double %B1, double %B2, i32 %P) {
 	%Z2 = fadd double %Y2, %B2
 	%R  = fmul double %Z1, %Z2
 	ret double %R
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NOT: <2 x double>
 ; CHECK: ret double %R
 }
diff --git a/test/Transforms/BBVectorize/simple-ldstr-ptrs.ll b/test/Transforms/BBVectorize/simple-ldstr-ptrs.ll
index d46f769..4d2298c 100644
--- a/test/Transforms/BBVectorize/simple-ldstr-ptrs.ll
+++ b/test/Transforms/BBVectorize/simple-ldstr-ptrs.ll
@@ -27,7 +27,7 @@ entry:
   %arrayidx5 = getelementptr inbounds i64* %c, i64 1
   store i64 %mul5, i64* %arrayidx5, align 8
   ret double %r
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %i0.v.i0 = bitcast i64* %a to <2 x i64>*
 ; CHECK: %i1.v.i0 = bitcast i64* %b to <2 x i64>*
 ; CHECK: %i0 = load <2 x i64>* %i0.v.i0, align 8
@@ -43,7 +43,7 @@ entry:
 ; CHECK: %0 = bitcast i64* %c to <2 x i64>*
 ; CHECK: store <2 x i64> %mul, <2 x i64>* %0, align 8
 ; CHECK: ret double %r
-; CHECK-AO: @test1
+; CHECK-AO-LABEL: @test1(
 ; CHECK-AO-NOT: load <2 x
 }
 
@@ -64,7 +64,7 @@ entry:
   %arrayidx5 = getelementptr inbounds i64** %c, i64 1
   store i64* %ptr3, i64** %arrayidx5, align 8
   ret void
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: %i0.v.i0 = bitcast i64** %a to <2 x i64*>*
 ; CHECK: %i1 = load i64** %b, align 8
 ; CHECK: %i0 = load <2 x i64*>* %i0.v.i0, align 8
@@ -78,7 +78,7 @@ entry:
 ; CHECK: %0 = bitcast i64** %c to <2 x i64*>*
 ; CHECK: store <2 x i64*> %ptr0, <2 x i64*>* %0, align 8
 ; CHECK: ret void
-; CHECK-AO: @test2
+; CHECK-AO-LABEL: @test2(
 ; CHECK-AO-NOT: <2 x
 }
 
@@ -108,7 +108,7 @@ entry:
   %arrayidx5 = getelementptr inbounds <2 x i64*>* %c, i64 1
   store <2 x i64*> %rtr3, <2 x i64*>* %arrayidx5, align 8
   ret void
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: %i0.v.i0 = bitcast <2 x i64*>* %a to <4 x i64*>*
 ; CHECK: %i1 = load <2 x i64*>* %b, align 8
 ; CHECK: %i0 = load <4 x i64*>* %i0.v.i0, align 8
@@ -128,7 +128,7 @@ entry:
 ; CHECK: %1 = shufflevector <2 x i64*> %rtr0, <2 x i64*> %rtr3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
 ; CHECK: store <4 x i64*> %1, <4 x i64*>* %0, align 8
 ; CHECK: ret void
-; CHECK-AO: @test3
+; CHECK-AO-LABEL: @test3(
 ; CHECK-AO-NOT: <4 x
 }
 
diff --git a/test/Transforms/BBVectorize/simple-ldstr.ll b/test/Transforms/BBVectorize/simple-ldstr.ll
index 8e51d29..558f8b3 100644
--- a/test/Transforms/BBVectorize/simple-ldstr.ll
+++ b/test/Transforms/BBVectorize/simple-ldstr.ll
@@ -17,7 +17,7 @@ entry:
   %arrayidx5 = getelementptr inbounds double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   ret void
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %i0.v.i0 = bitcast double* %a to <2 x double>*
 ; CHECK: %i1.v.i0 = bitcast double* %b to <2 x double>*
 ; CHECK: %i0 = load <2 x double>* %i0.v.i0, align 8
@@ -26,7 +26,7 @@ entry:
 ; CHECK: %0 = bitcast double* %c to <2 x double>*
 ; CHECK: store <2 x double> %mul, <2 x double>* %0, align 8
 ; CHECK: ret void
-; CHECK-AO: @test1
+; CHECK-AO-LABEL: @test1(
 ; CHECK-AO-NOT: <2 x double>
 }
 
@@ -49,7 +49,7 @@ entry:
   %arrayidx5 = getelementptr inbounds double* %c, i64 1
   store double %mul5, double* %arrayidx5, align 8
   ret void
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: %i0f.v.i0 = bitcast float* %a to <2 x float>*
 ; CHECK: %i1f.v.i0 = bitcast float* %b to <2 x float>*
 ; CHECK: %i0f = load <2 x float>* %i0f.v.i0, align 4
@@ -60,7 +60,7 @@ entry:
 ; CHECK: %0 = bitcast double* %c to <2 x double>*
 ; CHECK: store <2 x double> %mul, <2 x double>* %0, align 8
 ; CHECK: ret void
-; CHECK-AO: @test2
+; CHECK-AO-LABEL: @test2(
 ; CHECK-AO-NOT: <2 x double>
 }
 
@@ -81,7 +81,7 @@ entry:
   %arrayidx5 = getelementptr inbounds float* %c, i64 1
   store float %mul5f, float* %arrayidx5, align 4
   ret void
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: %i0.v.i0 = bitcast double* %a to <2 x double>*
 ; CHECK: %i1.v.i0 = bitcast double* %b to <2 x double>*
 ; CHECK: %i0 = load <2 x double>* %i0.v.i0, align 8
@@ -91,7 +91,7 @@ entry:
 ; CHECK: %0 = bitcast float* %c to <2 x float>*
 ; CHECK: store <2 x float> %mulf, <2 x float>* %0, align 8
 ; CHECK: ret void
-; CHECK-AO: @test3
+; CHECK-AO-LABEL: @test3(
 ; CHECK-AO: %i0 = load double* %a, align 8
 ; CHECK-AO: %i1 = load double* %b, align 8
 ; CHECK-AO: %arrayidx3 = getelementptr inbounds double* %a, i64 1
@@ -134,9 +134,9 @@ if.then:
 
 if.end:
   ret void
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NOT: <2 x double>
-; CHECK-AO: @test4
+; CHECK-AO-LABEL: @test4(
 ; CHECK-AO-NOT: <2 x double>
 }
 
@@ -155,7 +155,7 @@ entry:
   store double %mul5, double* %arrayidx5, align 8
   store double %mul, double* %c, align 4
   ret void
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: %i0.v.i0 = bitcast double* %a to <2 x double>*
 ; CHECK: %i1.v.i0 = bitcast double* %b to <2 x double>*
 ; CHECK: %i0 = load <2 x double>* %i0.v.i0, align 8
@@ -164,7 +164,7 @@ entry:
 ; CHECK: %0 = bitcast double* %c to <2 x double>*
 ; CHECK: store <2 x double> %mul, <2 x double>* %0, align 4
 ; CHECK: ret void
-; CHECK-AO: @test5
+; CHECK-AO-LABEL: @test5(
 ; CHECK-AO-NOT: <2 x double>
 }
 
diff --git a/test/Transforms/BBVectorize/simple-sel.ll b/test/Transforms/BBVectorize/simple-sel.ll
index 8caccfd..269b07f 100644
--- a/test/Transforms/BBVectorize/simple-sel.ll
+++ b/test/Transforms/BBVectorize/simple-sel.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 ; Basic depth-3 chain with select
 define double @test1(double %A1, double %A2, double %B1, double %B2, i1 %C1, i1 %C2) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0
 ; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1
 ; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0
@@ -30,8 +30,8 @@ define double @test1(double %A1, double %A2, double %B1, double %B2, i1 %C1, i1
 
 ; Basic depth-3 chain with select (and vect. compare)
 define double @test2(double %A1, double %A2, double %B1, double %B2) {
-; CHECK: @test2
-; CHECK-NB: @test2
+; CHECK-LABEL: @test2(
+; CHECK-NB-LABEL: @test2(
 ; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0
 ; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1
 ; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0
diff --git a/test/Transforms/BBVectorize/simple-tst.ll b/test/Transforms/BBVectorize/simple-tst.ll
index 42146c6..6a88e1b 100644
--- a/test/Transforms/BBVectorize/simple-tst.ll
+++ b/test/Transforms/BBVectorize/simple-tst.ll
@@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-linux"
 
 ; Basic depth-3 chain (target-specific type should not vectorize)
 define ppc_fp128 @test7(ppc_fp128 %A1, ppc_fp128 %A2, ppc_fp128 %B1, ppc_fp128 %B2) {
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NOT: <2 x ppc_fp128>
 	%X1 = fsub ppc_fp128 %A1, %B1
 	%X2 = fsub ppc_fp128 %A2, %B2
diff --git a/test/Transforms/BBVectorize/simple.ll b/test/Transforms/BBVectorize/simple.ll
index a447908..0fe33f1 100644
--- a/test/Transforms/BBVectorize/simple.ll
+++ b/test/Transforms/BBVectorize/simple.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 ; Basic depth-3 chain
 define double @test1(double %A1, double %A2, double %B1, double %B2) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0
 ; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1
 ; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0
@@ -27,7 +27,7 @@ define double @test1(double %A1, double %A2, double %B1, double %B2) {
 
 ; Basic depth-3 chain (last pair permuted)
 define double @test2(double %A1, double %A2, double %B1, double %B2) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0
 ; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1
 ; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0
@@ -53,7 +53,7 @@ define double @test2(double %A1, double %A2, double %B1, double %B2) {
 
 ; Basic depth-3 chain (last pair first splat)
 define double @test3(double %A1, double %A2, double %B1, double %B2) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0
 ; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1
 ; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0
@@ -78,7 +78,7 @@ define double @test3(double %A1, double %A2, double %B1, double %B2) {
 
 ; Basic depth-3 chain (last pair second splat)
 define double @test4(double %A1, double %A2, double %B1, double %B2) {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0
 ; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1
 ; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0
@@ -103,7 +103,7 @@ define double @test4(double %A1, double %A2, double %B1, double %B2) {
 
 ; Basic depth-3 chain
 define <2 x float> @test5(<2 x float> %A1, <2 x float> %A2, <2 x float> %B1, <2 x float> %B2) {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: %X1.v.i1 = shufflevector <2 x float> %B1, <2 x float> %B2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
 ; CHECK: %X1.v.i0 = shufflevector <2 x float> %A1, <2 x float> %A2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
 	%X1 = fsub <2 x float> %A1, %B1
@@ -125,7 +125,7 @@ define <2 x float> @test5(<2 x float> %A1, <2 x float> %A2, <2 x float> %B1, <2
 
 ; Basic chain with shuffles
 define <8 x i8> @test6(<8 x i8> %A1, <8 x i8> %A2, <8 x i8> %B1, <8 x i8> %B2) {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: %X1.v.i1 = shufflevector <8 x i8> %B1, <8 x i8> %B2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
 ; CHECK: %X1.v.i0 = shufflevector <8 x i8> %A1, <8 x i8> %A2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
 	%X1 = sub <8 x i8> %A1, %B1
@@ -151,7 +151,7 @@ define <8 x i8> @test6(<8 x i8> %A1, <8 x i8> %A2, <8 x i8> %B1, <8 x i8> %B2) {
 
 ; Basic depth-3 chain (flipped order)
 define double @test7(double %A1, double %A2, double %B1, double %B2) {
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0
 ; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1
 ; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0
@@ -175,7 +175,7 @@ define double @test7(double %A1, double %A2, double %B1, double %B2) {
 
 ; Basic depth-3 chain (subclass data)
 define i64 @test8(i64 %A1, i64 %A2, i64 %B1, i64 %B2) {
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: %X1.v.i1.1 = insertelement <2 x i64> undef, i64 %B1, i32 0
 ; CHECK: %X1.v.i1.2 = insertelement <2 x i64> %X1.v.i1.1, i64 %B2, i32 1
 ; CHECK: %X1.v.i0.1 = insertelement <2 x i64> undef, i64 %A1, i32 0
diff --git a/test/Transforms/BBVectorize/simple3.ll b/test/Transforms/BBVectorize/simple3.ll
index 78bcc9f..6edf7f0 100644
--- a/test/Transforms/BBVectorize/simple3.ll
+++ b/test/Transforms/BBVectorize/simple3.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 ; Basic depth-3 chain
 define double @test1(double %A1, double %A2, double %A3, double %B1, double %B2, double %B3) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %X1.v.i1.11 = insertelement <3 x double> undef, double %B1, i32 0
 ; CHECK: %X1.v.i1.22 = insertelement <3 x double> %X1.v.i1.11, double %B2, i32 1
 ; CHECK: %X1.v.i1 = insertelement <3 x double> %X1.v.i1.22, double %B3, i32 2
diff --git a/test/Transforms/CodeGenPrepare/basic.ll b/test/Transforms/CodeGenPrepare/basic.ll
index d617e43..495d910 100644
--- a/test/Transforms/CodeGenPrepare/basic.ll
+++ b/test/Transforms/CodeGenPrepare/basic.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10.0.0"
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; objectsize should fold to a constant, which causes the branch to fold to an
 ; uncond branch. Next, we fold the control flow alltogether.
 ; rdar://8785296
diff --git a/test/Transforms/ConstProp/basictest.ll b/test/Transforms/ConstProp/basictest.ll
index 09e6e7d..afe6ef9 100644
--- a/test/Transforms/ConstProp/basictest.ll
+++ b/test/Transforms/ConstProp/basictest.ll
@@ -16,7 +16,7 @@ BB2:
         br label %BB3
 
 BB3:     
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %Ret = phi i32 [ 0, %BB1 ], [ 1, %BB2 ]
         %Ret = phi i32 [ %Val, %BB1 ], [ 1, %BB2 ] 
         ret i32 %Ret
@@ -31,12 +31,12 @@ entry:
 bb:
   ret i1 %V
   
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: ret i1 true
 }
 
 define i1 @TNAN() {
-; CHECK: @TNAN
+; CHECK-LABEL: @TNAN(
 ; CHECK: ret i1 true
   %A = fcmp uno double 0x7FF8000000000000, 1.000000e+00
   %B = fcmp uno double 1.230000e+02, 1.000000e+00
@@ -47,7 +47,7 @@ define i1 @TNAN() {
 define i128 @vector_to_int_cast() {
   %A = bitcast <4 x i32> <i32 1073741824, i32 1073741824, i32 1073741824, i32 1073741824> to i128
   ret i128 %A
-; CHECK: @vector_to_int_cast
+; CHECK-LABEL: @vector_to_int_cast(
 ; CHECK: ret i128 85070591750041656499021422275829170176
 }
-  
\ No newline at end of file
+  
diff --git a/test/Transforms/ConstProp/bitcast.ll b/test/Transforms/ConstProp/bitcast.ll
index 53239c7..5e1581d 100644
--- a/test/Transforms/ConstProp/bitcast.ll
+++ b/test/Transforms/ConstProp/bitcast.ll
@@ -4,7 +4,7 @@
 define <1 x i64> @test1() {
   %A = bitcast i64 63 to <1 x i64>
   ret <1 x i64> %A
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret <1 x i64> <i64 63>
 }
 
diff --git a/test/Transforms/ConstProp/bswap.ll b/test/Transforms/ConstProp/bswap.ll
index a68fdcd..f601deb 100644
--- a/test/Transforms/ConstProp/bswap.ll
+++ b/test/Transforms/ConstProp/bswap.ll
@@ -10,28 +10,28 @@ declare i64 @llvm.bswap.i64(i64)
 
 declare i80 @llvm.bswap.i80(i80)
 
-; CHECK: define i16 @W
+; CHECK-LABEL: define i16 @W(
 define i16 @W() {
         ; CHECK: ret i16 256
         %Z = call i16 @llvm.bswap.i16( i16 1 )          ; <i16> [#uses=1]
         ret i16 %Z
 }
 
-; CHECK: define i32 @X
+; CHECK-LABEL: define i32 @X(
 define i32 @X() {
         ; CHECK: ret i32 16777216
         %Z = call i32 @llvm.bswap.i32( i32 1 )          ; <i32> [#uses=1]
         ret i32 %Z
 }
 
-; CHECK: define i64 @Y
+; CHECK-LABEL: define i64 @Y(
 define i64 @Y() {
         ; CHECK: ret i64 72057594037927936
         %Z = call i64 @llvm.bswap.i64( i64 1 )          ; <i64> [#uses=1]
         ret i64 %Z
 }
 
-; CHECK: define i80 @Z
+; CHECK-LABEL: define i80 @Z(
 define i80 @Z() {
         ; CHECK: ret i80 -450681596205739728166896
         ;                0xA0908070605040302010
diff --git a/test/Transforms/ConstProp/calls.ll b/test/Transforms/ConstProp/calls.ll
index 7a405a5..7541418 100644
--- a/test/Transforms/ConstProp/calls.ll
+++ b/test/Transforms/ConstProp/calls.ll
@@ -11,7 +11,7 @@ declare double @sqrt(double)
 declare double @exp2(double)
 
 define double @T() {
-; CHECK: @T
+; CHECK-LABEL: @T(
 ; CHECK-NOT: call
 ; CHECK: ret
   %A = call double @cos(double 0.000000e+00)
@@ -29,7 +29,7 @@ define double @T() {
 }
 
 define i1 @test_sse_cvt() nounwind readnone {
-; CHECK: @test_sse_cvt
+; CHECK-LABEL: @test_sse_cvt(
 ; CHECK-NOT: call
 ; CHECK: ret i1 true
 entry:
@@ -63,7 +63,7 @@ declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone
 
 define double @test_intrinsic_pow() nounwind uwtable ssp {
 entry:
-; CHECK: @test_intrinsic_pow
+; CHECK-LABEL: @test_intrinsic_pow(
 ; CHECK-NOT: call
   %0 = call double @llvm.pow.f64(double 1.500000e+00, double 3.000000e+00)
   ret double %0
@@ -72,7 +72,7 @@ declare double @llvm.pow.f64(double, double) nounwind readonly
 
 ; Shouldn't fold because of -fno-builtin
 define double @sin_() nounwind uwtable ssp {
-; FNOBUILTIN: @sin_
+; FNOBUILTIN-LABEL: @sin_(
 ; FNOBUILTIN: %1 = call double @sin(double 3.000000e+00)
   %1 = call double @sin(double 3.000000e+00)
   ret double %1
@@ -80,7 +80,7 @@ define double @sin_() nounwind uwtable ssp {
 
 ; Shouldn't fold because of -fno-builtin
 define double @sqrt_() nounwind uwtable ssp {
-; FNOBUILTIN: @sqrt_
+; FNOBUILTIN-LABEL: @sqrt_(
 ; FNOBUILTIN: %1 = call double @sqrt(double 3.000000e+00)
   %1 = call double @sqrt(double 3.000000e+00)
   ret double %1
@@ -88,7 +88,7 @@ define double @sqrt_() nounwind uwtable ssp {
 
 ; Shouldn't fold because of -fno-builtin
 define float @sqrtf_() nounwind uwtable ssp {
-; FNOBUILTIN: @sqrtf_
+; FNOBUILTIN-LABEL: @sqrtf_(
 ; FNOBUILTIN: %1 = call float @sqrtf(float 3.000000e+00)
   %1 = call float @sqrtf(float 3.000000e+00)
   ret float %1
@@ -97,7 +97,7 @@ declare float @sqrtf(float)
 
 ; Shouldn't fold because of -fno-builtin
 define float @sinf_() nounwind uwtable ssp {
-; FNOBUILTIN: @sinf_
+; FNOBUILTIN-LABEL: @sinf_(
 ; FNOBUILTIN: %1 = call float @sinf(float 3.000000e+00)
   %1 = call float @sinf(float 3.000000e+00)
   ret float %1
@@ -106,7 +106,7 @@ declare float @sinf(float)
 
 ; Shouldn't fold because of -fno-builtin
 define double @tan_() nounwind uwtable ssp {
-; FNOBUILTIN: @tan_
+; FNOBUILTIN-LABEL: @tan_(
 ; FNOBUILTIN: %1 = call double @tan(double 3.000000e+00)
   %1 = call double @tan(double 3.000000e+00)
   ret double %1
@@ -114,7 +114,7 @@ define double @tan_() nounwind uwtable ssp {
 
 ; Shouldn't fold because of -fno-builtin
 define double @tanh_() nounwind uwtable ssp {
-; FNOBUILTIN: @tanh_
+; FNOBUILTIN-LABEL: @tanh_(
 ; FNOBUILTIN: %1 = call double @tanh(double 3.000000e+00)
   %1 = call double @tanh(double 3.000000e+00)
   ret double %1
@@ -123,7 +123,7 @@ declare double @tanh(double)
 
 ; Shouldn't fold because of -fno-builtin
 define double @pow_() nounwind uwtable ssp {
-; FNOBUILTIN: @pow_
+; FNOBUILTIN-LABEL: @pow_(
 ; FNOBUILTIN: %1 = call double @pow(double 3.000000e+00, double 3.000000e+00)
   %1 = call double @pow(double 3.000000e+00, double 3.000000e+00)
   ret double %1
@@ -132,7 +132,7 @@ declare double @pow(double, double)
 
 ; Shouldn't fold because of -fno-builtin
 define double @fmod_() nounwind uwtable ssp {
-; FNOBUILTIN: @fmod_
+; FNOBUILTIN-LABEL: @fmod_(
 ; FNOBUILTIN: %1 = call double @fmod(double 3.000000e+00, double 3.000000e+00)
   %1 = call double @fmod(double 3.000000e+00, double 3.000000e+00)
   ret double %1
@@ -141,7 +141,7 @@ declare double @fmod(double, double)
 
 ; Shouldn't fold because of -fno-builtin
 define double @atan2_() nounwind uwtable ssp {
-; FNOBUILTIN: @atan2_
+; FNOBUILTIN-LABEL: @atan2_(
 ; FNOBUILTIN: %1 = call double @atan2(double 3.000000e+00, double 3.000000e+00)
   %1 = call double @atan2(double 3.000000e+00, double 3.000000e+00)
   ret double %1
diff --git a/test/Transforms/ConstProp/extractvalue.ll b/test/Transforms/ConstProp/extractvalue.ll
index f947b22..72d6cb7 100644
--- a/test/Transforms/ConstProp/extractvalue.ll
+++ b/test/Transforms/ConstProp/extractvalue.ll
@@ -5,21 +5,21 @@
 define i32 @test1() {
   %A = extractvalue %struct { i32 2, [4 x i8] c"foo\00" }, 0
   ret i32 %A
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret i32 2
 }
 
 define i8 @test2() {
   %A = extractvalue %struct { i32 2, [4 x i8] c"foo\00" }, 1, 2
   ret i8 %A
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: ret i8 111
 }
 
 define i32 @test3() {
   %A = extractvalue [3 x %struct] [ %struct { i32 0, [4 x i8] c"aaaa" }, %struct { i32 1, [4 x i8] c"bbbb" }, %struct { i32 2, [4 x i8] c"cccc" } ], 1, 0
   ret i32 %A
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: ret i32 1
 }
 
diff --git a/test/Transforms/ConstProp/insertvalue.ll b/test/Transforms/ConstProp/insertvalue.ll
index a4b7bb1..0d288b3 100644
--- a/test/Transforms/ConstProp/insertvalue.ll
+++ b/test/Transforms/ConstProp/insertvalue.ll
@@ -5,21 +5,21 @@
 define %struct @test1() {
   %A = insertvalue %struct { i32 2, [4 x i8] c"foo\00" }, i32 1, 0
   ret %struct %A
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret %struct { i32 1, [4 x i8] c"foo\00" }
 }
 
 define %struct @test2() {
   %A = insertvalue %struct { i32 2, [4 x i8] c"foo\00" }, i8 1, 1, 2
   ret %struct %A
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: ret %struct { i32 2, [4 x i8] c"fo\01\00" }
 }
 
 define [3 x %struct] @test3() {
   %A = insertvalue [3 x %struct] [ %struct { i32 0, [4 x i8] c"aaaa" }, %struct { i32 1, [4 x i8] c"bbbb" }, %struct { i32 2, [4 x i8] c"cccc" } ], i32 -1, 1, 0
   ret [3 x %struct] %A
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK:ret [3 x %struct] [%struct { i32 0, [4 x i8] c"aaaa" }, %struct { i32 -1, [4 x i8] c"bbbb" }, %struct { i32 2, [4 x i8] c"cccc" }]
 }
 
diff --git a/test/Transforms/ConstProp/loads.ll b/test/Transforms/ConstProp/loads.ll
index 6794288..795dc07 100644
--- a/test/Transforms/ConstProp/loads.ll
+++ b/test/Transforms/ConstProp/loads.ll
@@ -13,11 +13,11 @@ define i32 @test1() {
   ret i32 %r
 
 ; 0xDEADBEEF
-; LE: @test1
+; LE-LABEL: @test1(
 ; LE: ret i32 -559038737
 
 ; 0xDEADBEEF
-; BE: @test1
+; BE-LABEL: @test1(
 ; BE: ret i32 -559038737
 }
 
@@ -28,11 +28,11 @@ define i16 @test2() {
   ret i16 %r
 
 ; 0xBEEF
-; LE: @test2
+; LE-LABEL: @test2(
 ; LE: ret i16 -16657
 
 ; 0xDEAD
-; BE: @test2
+; BE-LABEL: @test2(
 ; BE: ret i16 -8531
 }
 
@@ -42,11 +42,11 @@ define i16 @test3() {
   ret i16 %r
 
 ; 0xDEAD
-; LE: @test3
+; LE-LABEL: @test3(
 ; LE: ret i16 -8531
 
 ; 0xBEEF
-; BE: @test3
+; BE-LABEL: @test3(
 ; BE: ret i16 -16657
 }
 
@@ -56,11 +56,11 @@ define i16 @test4() {
   ret i16 %r
 
 ; 0x00BA
-; LE: @test4
+; LE-LABEL: @test4(
 ; LE: ret i16 186
 
 ; 0xBA00
-; BE: @test4
+; BE-LABEL: @test4(
 ; BE: ret i16 -17920
 }
 
@@ -70,11 +70,11 @@ define i64 @test6() {
   ret i64 %r
 
 ; 0x3FF_0000000000000
-; LE: @test6
+; LE-LABEL: @test6(
 ; LE: ret i64 4607182418800017408
 
 ; 0x3FF_0000000000000
-; BE: @test6
+; BE-LABEL: @test6(
 ; BE: ret i64 4607182418800017408
 }
 
@@ -84,11 +84,11 @@ define i16 @test7() {
   ret i16 %r
 
 ; 0x0000
-; LE: @test7
+; LE-LABEL: @test7(
 ; LE: ret i16 0
 
 ; 0x3FF0
-; BE: @test7
+; BE-LABEL: @test7(
 ; BE: ret i16 16368
 }
 
@@ -97,10 +97,10 @@ define double @test8() {
   %r = load double* bitcast({{i32,i8},i32}* @g1 to double*)
   ret double %r
 
-; LE: @test8
+; LE-LABEL: @test8(
 ; LE: ret double 0xBADEADBEEF
 
-; BE: @test8
+; BE-LABEL: @test8(
 ; BE: ret double 0xDEADBEEFBA000000
 }
 
@@ -111,11 +111,11 @@ define i128 @test9() {
   ret i128 %r
 
 ; 0x00000000_06B1BFF8_00000000_0000007B
-; LE: @test9
+; LE-LABEL: @test9(
 ; LE: ret i128 2071796475790618158476296315
 
 ; 0x00000000_0000007B_00000000_06B1BFF8
-; BE: @test9
+; BE-LABEL: @test9(
 ; BE: ret i128 2268949521066387161080
 }
 
@@ -124,10 +124,10 @@ define <2 x i64> @test10() {
   %r = load <2 x i64>* bitcast({i64, i64}* @g3 to <2 x i64>*)
   ret <2 x i64> %r
 
-; LE: @test10
+; LE-LABEL: @test10(
 ; LE: ret <2 x i64> <i64 123, i64 112312312>
 
-; BE: @test10
+; BE-LABEL: @test10(
 ; BE: ret <2 x i64> <i64 123, i64 112312312>
 }
 
@@ -142,11 +142,11 @@ entry:
   ret i16 %a
 
 ; 0x08A1
-; LE: @test11
+; LE-LABEL: @test11(
 ; LE: ret i16 2209
 
 ; 0xA108
-; BE: @test11
+; BE-LABEL: @test11(
 ; BE: ret i16 -24312
 }
 
@@ -159,11 +159,11 @@ define i16 @test12() {
   ret i16 %a
 
 ; 0x0062
-; LE: @test12
+; LE-LABEL: @test12(
 ; LE: ret i16 98
 
 ; 0x6200
-; BE: @test12
+; BE-LABEL: @test12(
 ; BE: ret i16 25088
 }
 
@@ -174,10 +174,10 @@ define i1 @test13() {
   %A = load i1* bitcast (i8* @g5 to i1*)
   ret i1 %A
 
-; LE: @test13
+; LE-LABEL: @test13(
 ; LE: ret i1 false
 
-; BE: @test13
+; BE-LABEL: @test13(
 ; BE: ret i1 false
 }
 
@@ -187,10 +187,10 @@ entry:
   %tmp = load i64* bitcast ([2 x i8*]* @g6 to i64*)
   ret i64 %tmp
 
-; LE: @test14
+; LE-LABEL: @test14(
 ; LE: ret i64 1
 
-; BE: @test14
+; BE-LABEL: @test14(
 ; BE: ret i64 1
 }
 
@@ -199,9 +199,9 @@ entry:
   %tmp = load i64* bitcast (i8** getelementptr inbounds ([2 x i8*]* @g6, i32 0, i64 1) to i64*)
   ret i64 %tmp
 
-; LE: @test15
+; LE-LABEL: @test15(
 ; LE: ret i64 2
 
-; BE: @test15
+; BE-LABEL: @test15(
 ; BE: ret i64 2
 }
diff --git a/test/Transforms/ConstProp/overflow-ops.ll b/test/Transforms/ConstProp/overflow-ops.ll
index 849bf9e..1ae3e56 100644
--- a/test/Transforms/ConstProp/overflow-ops.ll
+++ b/test/Transforms/ConstProp/overflow-ops.ll
@@ -18,7 +18,7 @@ entry:
   %t = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 42, i8 100)
   ret {i8, i1} %t
 
-; CHECK: @uadd_1
+; CHECK-LABEL: @uadd_1(
 ; CHECK: ret { i8, i1 } { i8 -114, i1 false }
 }
 
@@ -27,7 +27,7 @@ entry:
   %t = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 142, i8 120)
   ret {i8, i1} %t
 
-; CHECK: @uadd_2
+; CHECK-LABEL: @uadd_2(
 ; CHECK: ret { i8, i1 } { i8 6, i1 true }
 }
 
@@ -40,7 +40,7 @@ entry:
   %t = call {i8, i1} @llvm.usub.with.overflow.i8(i8 4, i8 2)
   ret {i8, i1} %t
 
-; CHECK: @usub_1
+; CHECK-LABEL: @usub_1(
 ; CHECK: ret { i8, i1 } { i8 2, i1 false }
 }
 
@@ -49,7 +49,7 @@ entry:
   %t = call {i8, i1} @llvm.usub.with.overflow.i8(i8 4, i8 6)
   ret {i8, i1} %t
 
-; CHECK: @usub_2
+; CHECK-LABEL: @usub_2(
 ; CHECK: ret { i8, i1 } { i8 -2, i1 true }
 }
 
@@ -62,7 +62,7 @@ entry:
   %t = call {i8, i1} @llvm.umul.with.overflow.i8(i8 100, i8 3)
   ret {i8, i1} %t
 
-; CHECK: @umul_1
+; CHECK-LABEL: @umul_1(
 ; CHECK: ret { i8, i1 } { i8 44, i1 true }
 }
 
@@ -71,7 +71,7 @@ entry:
   %t = call {i8, i1} @llvm.umul.with.overflow.i8(i8 100, i8 2)
   ret {i8, i1} %t
 
-; CHECK: @umul_2
+; CHECK-LABEL: @umul_2(
 ; CHECK: ret { i8, i1 } { i8 -56, i1 false }
 }
 
@@ -84,7 +84,7 @@ entry:
   %t = call {i8, i1} @llvm.sadd.with.overflow.i8(i8 42, i8 2)
   ret {i8, i1} %t
 
-; CHECK: @sadd_1
+; CHECK-LABEL: @sadd_1(
 ; CHECK: ret { i8, i1 } { i8 44, i1 false }
 }
 
@@ -93,7 +93,7 @@ entry:
   %t = call {i8, i1} @llvm.sadd.with.overflow.i8(i8 120, i8 10)
   ret {i8, i1} %t
 
-; CHECK: @sadd_2
+; CHECK-LABEL: @sadd_2(
 ; CHECK: ret { i8, i1 } { i8 -126, i1 true }
 }
 
@@ -102,7 +102,7 @@ entry:
   %t = call {i8, i1} @llvm.sadd.with.overflow.i8(i8 -120, i8 10)
   ret {i8, i1} %t
 
-; CHECK: @sadd_3
+; CHECK-LABEL: @sadd_3(
 ; CHECK: ret { i8, i1 } { i8 -110, i1 false }
 }
 
@@ -111,7 +111,7 @@ entry:
   %t = call {i8, i1} @llvm.sadd.with.overflow.i8(i8 -120, i8 -10)
   ret {i8, i1} %t
 
-; CHECK: @sadd_4
+; CHECK-LABEL: @sadd_4(
 ; CHECK: ret { i8, i1 } { i8 126, i1 true }
 }
 
@@ -120,7 +120,7 @@ entry:
   %t = call {i8, i1} @llvm.sadd.with.overflow.i8(i8 2, i8 -10)
   ret {i8, i1} %t
 
-; CHECK: @sadd_5
+; CHECK-LABEL: @sadd_5(
 ; CHECK: ret { i8, i1 } { i8 -8, i1 false }
 }
 
@@ -134,7 +134,7 @@ entry:
   %t = call {i8, i1} @llvm.ssub.with.overflow.i8(i8 4, i8 2)
   ret {i8, i1} %t
 
-; CHECK: @ssub_1
+; CHECK-LABEL: @ssub_1(
 ; CHECK: ret { i8, i1 } { i8 2, i1 false }
 }
 
@@ -143,7 +143,7 @@ entry:
   %t = call {i8, i1} @llvm.ssub.with.overflow.i8(i8 4, i8 6)
   ret {i8, i1} %t
 
-; CHECK: @ssub_2
+; CHECK-LABEL: @ssub_2(
 ; CHECK: ret { i8, i1 } { i8 -2, i1 false }
 }
 
@@ -152,7 +152,7 @@ entry:
   %t = call {i8, i1} @llvm.ssub.with.overflow.i8(i8 -10, i8 120)
   ret {i8, i1} %t
 
-; CHECK: @ssub_3
+; CHECK-LABEL: @ssub_3(
 ; CHECK: ret { i8, i1 } { i8 126, i1 true }
 }
 
@@ -161,7 +161,7 @@ entry:
   %t = call {i8, i1} @llvm.ssub.with.overflow.i8(i8 -10, i8 10)
   ret {i8, i1} %t
 
-; CHECK: @ssub_3b
+; CHECK-LABEL: @ssub_3b(
 ; CHECK: ret { i8, i1 } { i8 -20, i1 false }
 }
 
@@ -170,7 +170,7 @@ entry:
   %t = call {i8, i1} @llvm.ssub.with.overflow.i8(i8 120, i8 -10)
   ret {i8, i1} %t
 
-; CHECK: @ssub_4
+; CHECK-LABEL: @ssub_4(
 ; CHECK: ret { i8, i1 } { i8 -126, i1 true }
 }
 
@@ -179,7 +179,7 @@ entry:
   %t = call {i8, i1} @llvm.ssub.with.overflow.i8(i8 20, i8 -10)
   ret {i8, i1} %t
 
-; CHECK: @ssub_4b
+; CHECK-LABEL: @ssub_4b(
 ; CHECK: ret { i8, i1 } { i8 30, i1 false }
 }
 
@@ -188,7 +188,7 @@ entry:
   %t = call {i8, i1} @llvm.ssub.with.overflow.i8(i8 -20, i8 -10)
   ret {i8, i1} %t
 
-; CHECK: @ssub_5
+; CHECK-LABEL: @ssub_5(
 ; CHECK: ret { i8, i1 } { i8 -10, i1 false }
 }
 
@@ -202,6 +202,6 @@ entry:
   %t = call {i8, i1} @llvm.smul.with.overflow.i8(i8 -20, i8 -10)
   ret {i8, i1} %t
 
-; CHECK: @smul_1
+; CHECK-LABEL: @smul_1(
 ; CHECK: ret { i8, i1 } { i8 -56, i1 true }
 }
diff --git a/test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll b/test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll
index fef5b85..0754f86 100644
--- a/test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll
+++ b/test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll
@@ -1,6 +1,6 @@
 ; RUN: opt -S < %s -correlated-propagation | FileCheck %s
 
-; CHECK: @test
+; CHECK-LABEL: @test(
 define i16 @test(i32 %a, i1 %b) {
 entry:
   %c = icmp eq i32 %a, 0
@@ -22,4 +22,4 @@ merge:
   %h = select i1 %f, i16 1, i16 0 
 ; CHECK: ret i16 %h
   ret i16 %h
-}
\ No newline at end of file
+}
diff --git a/test/Transforms/CorrelatedValuePropagation/basic.ll b/test/Transforms/CorrelatedValuePropagation/basic.ll
index 39c437c..9a22647 100644
--- a/test/Transforms/CorrelatedValuePropagation/basic.ll
+++ b/test/Transforms/CorrelatedValuePropagation/basic.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -correlated-propagation -S | FileCheck %s
 ; PR2581
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 define i32 @test1(i1 %C) nounwind  {
         br i1 %C, label %exit, label %body
 
@@ -18,7 +18,7 @@ exit:           ; preds = %0
 
 ; PR4420
 declare i1 @ext()
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 define i1 @test2() {
 entry:
         %cond = tail call i1 @ext()             ; <i1> [#uses=2]
@@ -42,7 +42,7 @@ bb3:            ; preds = %bb1
 
 ; PR4855
 @gv = internal constant i8 7
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 define i8 @test3(i8* %a) nounwind {
 entry:
         %cond = icmp eq i8* %a, @gv
@@ -58,7 +58,7 @@ bb2:            ; preds = %entry
 }
 
 ; PR1757
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 define i32 @test4(i32) {
 EntryBlock:
 ; CHECK: icmp sgt i32 %0, 2  
@@ -83,7 +83,7 @@ LessThanOrEqualToTwo:
 
 declare i32* @f(i32*)
 define void @test5(i32* %x, i32* %y) {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 entry:
   %pre = icmp eq i32* %x, null
   br i1 %pre, label %return, label %loop
@@ -102,7 +102,7 @@ return:
 }
 
 define i32 @switch1(i32 %s) {
-; CHECK: @switch1
+; CHECK-LABEL: @switch1(
 entry:
   %cmp = icmp slt i32 %s, 0
   br i1 %cmp, label %negative, label %out
@@ -134,7 +134,7 @@ next:
 }
 
 define i32 @switch2(i32 %s) {
-; CHECK: @switch2
+; CHECK-LABEL: @switch2(
 entry:
   %cmp = icmp sgt i32 %s, 0
   br i1 %cmp, label %positive, label %out
@@ -157,7 +157,7 @@ next:
 }
 
 define i32 @switch3(i32 %s) {
-; CHECK: @switch3
+; CHECK-LABEL: @switch3(
 entry:
   %cmp = icmp sgt i32 %s, 0
   br i1 %cmp, label %positive, label %out
@@ -180,7 +180,7 @@ next:
 }
 
 define void @switch4(i32 %s) {
-; CHECK: @switch4
+; CHECK-LABEL: @switch4(
 entry:
   %cmp = icmp eq i32 %s, 0
   br i1 %cmp, label %zero, label %out
diff --git a/test/Transforms/CorrelatedValuePropagation/range.ll b/test/Transforms/CorrelatedValuePropagation/range.ll
index 6750546..e40c639 100644
--- a/test/Transforms/CorrelatedValuePropagation/range.ll
+++ b/test/Transforms/CorrelatedValuePropagation/range.ll
@@ -17,7 +17,7 @@ else:
 end:
   ret i32 2
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: then:
 ; CHECK-NEXT: br i1 false, label %end, label %else
 }
@@ -37,12 +37,12 @@ else:
 end:
   ret i32 2
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: then:
 ; CHECK-NEXT: br i1 false, label %end, label %else
 }
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 define i32 @test3(i32 %c) nounwind {
   %cmp = icmp slt i32 %c, 2
   br i1 %cmp, label %if.then, label %if.end
@@ -71,7 +71,7 @@ if.end8:
   ret i32 4
 }
 
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 define i32 @test4(i32 %c) nounwind {
   switch i32 %c, label %sw.default [
     i32 1, label %sw.bb
@@ -99,7 +99,7 @@ return:
   ret i32 %retval.0
 }
 
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 define i1 @test5(i32 %c) nounwind {
   %cmp = icmp slt i32 %c, 5
   br i1 %cmp, label %if.then, label %if.end
@@ -121,7 +121,7 @@ if.end8:
   ret i1 %cmp2
 }
 
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 define i1 @test6(i32 %c) nounwind {
   %cmp = icmp ule i32 %c, 7
   br i1 %cmp, label %if.then, label %if.end
@@ -143,7 +143,7 @@ sw.bb:
   ret i1 %cmp2
 }
 
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 define i1 @test7(i32 %c) nounwind {
 entry:
  switch i32 %c, label %sw.default [
diff --git a/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll b/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll
index f5d2588..4cb742d 100644
--- a/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll
+++ b/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll
@@ -8,7 +8,7 @@ entry:
   call void @llvm.dbg.value(metadata !{i32 %len}, i64 0, metadata !10)
   call void @llvm.dbg.value(metadata !{i32 %hash}, i64 0, metadata !11)
   call void @llvm.dbg.value(metadata !{i32 %flags}, i64 0, metadata !12)
-; CHECK:  call fastcc i8* @add_name_internal(i8* %name, i32 %hash) [[NUW:#[0-9]+]], !dbg !13
+; CHECK:  call fastcc i8* @add_name_internal(i8* %name, i32 %hash) [[NUW:#[0-9]+]], !dbg !{{[0-9]+}}
   %0 = call fastcc i8* @add_name_internal(i8* %name, i32 %len, i32 %hash, i8 zeroext 0, i32 %flags) nounwind, !dbg !13 ; <i8*> [#uses=1]
   ret i8* %0, !dbg !13
 }
@@ -43,31 +43,34 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 ; CHECK: attributes #2 = { noinline nounwind ssp }
 ; CHECK: attributes [[NUW]] = { nounwind }
 
+!llvm.dbg.cu = !{!3}
 !0 = metadata !{i32 524545, metadata !1, metadata !"name", metadata !2, i32 8, metadata !6} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"vfs_addname", metadata !"vfs_addname", metadata !"vfs_addname", metadata !2, i32 12, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
-!2 = metadata !{i32 524329, metadata !"tail.c", metadata !"/Users/echeng/LLVM/radars/r7927803/", metadata !3} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"tail.c", metadata !"/Users/echeng/LLVM/radars/r7927803/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!1 = metadata !{i32 524334, metadata !28, metadata !2, metadata !"vfs_addname", metadata !"vfs_addname", metadata !"vfs_addname", i32 12, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!2 = metadata !{i32 524329, metadata !28} ; [ DW_TAG_file_type ]
+!3 = metadata !{i32 524305, metadata !28, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)", i1 true, metadata !"", i32 0, metadata !29, metadata !29, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!4 = metadata !{i32 524309, metadata !28, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{metadata !6, metadata !6, metadata !9, metadata !9, metadata !9}
-!6 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ]
-!7 = metadata !{i32 524326, metadata !2, metadata !"", metadata !2, i32 0, i64 8, i64 8, i64 0, i32 0, metadata !8} ; [ DW_TAG_const_type ]
-!8 = metadata !{i32 524324, metadata !2, metadata !"char", metadata !2, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
-!9 = metadata !{i32 524324, metadata !2, metadata !"unsigned int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 524303, metadata !28, metadata !2, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ]
+!7 = metadata !{i32 524326, metadata !28, metadata !2, metadata !"", i32 0, i64 8, i64 8, i64 0, i32 0, metadata !8} ; [ DW_TAG_const_type ]
+!8 = metadata !{i32 524324, metadata !28, metadata !2, metadata !"char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 524324, metadata !28, metadata !2, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
 !10 = metadata !{i32 524545, metadata !1, metadata !"len", metadata !2, i32 9, metadata !9} ; [ DW_TAG_arg_variable ]
 !11 = metadata !{i32 524545, metadata !1, metadata !"hash", metadata !2, i32 10, metadata !9} ; [ DW_TAG_arg_variable ]
 !12 = metadata !{i32 524545, metadata !1, metadata !"flags", metadata !2, i32 11, metadata !9} ; [ DW_TAG_arg_variable ]
 !13 = metadata !{i32 13, i32 0, metadata !14, null}
-!14 = metadata !{i32 524299, metadata !1, i32 12, i32 0} ; [ DW_TAG_lexical_block ]
+!14 = metadata !{i32 524299, metadata !28, metadata !1, i32 12, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !15 = metadata !{i32 524545, metadata !16, metadata !"name", metadata !2, i32 17, metadata !6} ; [ DW_TAG_arg_variable ]
-!16 = metadata !{i32 524334, i32 0, metadata !2, metadata !"add_name_internal", metadata !"add_name_internal", metadata !"add_name_internal", metadata !2, i32 22, metadata !17, i1 true, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
-!17 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !18, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!16 = metadata !{i32 524334, metadata !28, metadata !2, metadata !"add_name_internal", metadata !"add_name_internal", metadata !"add_name_internal", i32 22, metadata !17, i1 true, i1 true, i32 0, i32 0, null, i1 false, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!17 = metadata !{i32 524309, metadata !28, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !18, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !18 = metadata !{metadata !6, metadata !6, metadata !9, metadata !9, metadata !19, metadata !9}
-!19 = metadata !{i32 524324, metadata !2, metadata !"unsigned char", metadata !2, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ]
+!19 = metadata !{i32 524324, metadata !28, metadata !2, metadata !"unsigned char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ]
 !20 = metadata !{i32 524545, metadata !16, metadata !"len", metadata !2, i32 18, metadata !9} ; [ DW_TAG_arg_variable ]
 !21 = metadata !{i32 524545, metadata !16, metadata !"hash", metadata !2, i32 19, metadata !9} ; [ DW_TAG_arg_variable ]
 !22 = metadata !{i32 524545, metadata !16, metadata !"extra", metadata !2, i32 20, metadata !19} ; [ DW_TAG_arg_variable ]
 !23 = metadata !{i32 524545, metadata !16, metadata !"flags", metadata !2, i32 21, metadata !9} ; [ DW_TAG_arg_variable ]
 !24 = metadata !{i32 23, i32 0, metadata !25, null}
-!25 = metadata !{i32 524299, metadata !16, i32 22, i32 0} ; [ DW_TAG_lexical_block ]
+!25 = metadata !{i32 524299, metadata !28, metadata !16, i32 22, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !26 = metadata !{i32 24, i32 0, metadata !25, null}
 !27 = metadata !{i32 26, i32 0, metadata !25, null}
+!28 = metadata !{metadata !"tail.c", metadata !"/Users/echeng/LLVM/radars/r7927803/"}
+!29 = metadata !{i32 0}
diff --git a/test/Transforms/DeadArgElim/2013-05-17-VarargsAndBlockAddress.ll b/test/Transforms/DeadArgElim/2013-05-17-VarargsAndBlockAddress.ll
new file mode 100644
index 0000000..2321603
--- /dev/null
+++ b/test/Transforms/DeadArgElim/2013-05-17-VarargsAndBlockAddress.ll
@@ -0,0 +1,25 @@
+; RUN: opt %s -deadargelim -S | FileCheck %s
+
+
+@block_addr = global i8* blockaddress(@varargs_func, %l1)
+; CHECK: @block_addr = global i8* blockaddress(@varargs_func, %l1)
+
+
+; This function is referenced by a "blockaddress" constant but it is
+; not address-taken, so the pass should be able to remove its unused
+; varargs.
+
+define internal i32 @varargs_func(i8* %addr, ...) {
+  indirectbr i8* %addr, [ label %l1, label %l2 ]
+l1:
+  ret i32 1
+l2:
+  ret i32 2
+}
+; CHECK: define internal i32 @varargs_func(i8* %addr) {
+
+define i32 @caller(i8* %addr) {
+  %r = call i32 (i8*, ...)* @varargs_func(i8* %addr)
+  ret i32 %r
+}
+; CHECK: %r = call i32 @varargs_func(i8* %addr)
diff --git a/test/Transforms/DeadArgElim/dbginfo.ll b/test/Transforms/DeadArgElim/dbginfo.ll
index d53c19c..21de114 100644
--- a/test/Transforms/DeadArgElim/dbginfo.ll
+++ b/test/Transforms/DeadArgElim/dbginfo.ll
@@ -36,28 +36,28 @@ entry:
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.2 (trunk 165305)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/samsonov/tmp/clang-di/test.cc] [DW_LANG_C_plus_plus]
+!0 = metadata !{i32 786449, metadata !20, i32 4, metadata !"clang version 3.2 (trunk 165305)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1,  metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/samsonov/tmp/clang-di/test.cc] [DW_LANG_C_plus_plus]
 !1 = metadata !{i32 0}
 !3 = metadata !{metadata !5, metadata !8, metadata !9}
-!5 = metadata !{i32 786478, metadata !6, metadata !"run", metadata !"run", metadata !"", metadata !6, i32 8, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @_Z3runv, null, null, metadata !1, i32 8} ; [ DW_TAG_subprogram ] [line 8] [def] [run]
+!5 = metadata !{i32 786478, metadata !20, metadata !6, metadata !"run", metadata !"run", metadata !"", i32 8, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @_Z3runv, null, null, metadata !1, i32 8} ; [ DW_TAG_subprogram ] [line 8] [def] [run]
 !6 = metadata !{i32 786473, metadata !20} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !1, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
-!8 = metadata !{i32 786478, metadata !6, metadata !"dead_vararg", metadata !"dead_vararg", metadata !"", metadata !6, i32 5, metadata !7, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (...)* @_ZN12_GLOBAL__N_111dead_varargEz, null, null, metadata !1, i32 5} ; [ DW_TAG_subprogram ] [line 5] [local] [def] [dead_vararg]
+!8 = metadata !{i32 786478, metadata !20, metadata !6, metadata !"dead_vararg", metadata !"dead_vararg", metadata !"", i32 5, metadata !7, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (...)* @_ZN12_GLOBAL__N_111dead_varargEz, null, null, metadata !1, i32 5} ; [ DW_TAG_subprogram ] [line 5] [local] [def] [dead_vararg]
 
 ; CHECK: metadata !"dead_vararg"{{.*}}void ()* @_ZN12_GLOBAL__N_111dead_varargEz
 
-!9 = metadata !{i32 786478, metadata !6, metadata !"dead_arg", metadata !"dead_arg", metadata !"", metadata !6, i32 4, metadata !7, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i8*)* @_ZN12_GLOBAL__N_18dead_argEPv, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ] [line 4] [local] [def] [dead_arg]
+!9 = metadata !{i32 786478, metadata !20, metadata !6, metadata !"dead_arg", metadata !"dead_arg", metadata !"", i32 4, metadata !7, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i8*)* @_ZN12_GLOBAL__N_18dead_argEPv, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ] [line 4] [local] [def] [dead_arg]
 
 ; CHECK: metadata !"dead_arg"{{.*}}void ()* @_ZN12_GLOBAL__N_18dead_argEPv
 
 !10 = metadata !{i32 8, i32 14, metadata !11, null}
-!11 = metadata !{i32 786443, metadata !5, i32 8, i32 12, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] [/home/samsonov/tmp/clang-di/test.cc]
+!11 = metadata !{i32 786443, metadata !20, metadata !5, i32 8, i32 12, i32 0} ; [ DW_TAG_lexical_block ] [/home/samsonov/tmp/clang-di/test.cc]
 !12 = metadata !{i32 8, i32 27, metadata !11, null}
 !13 = metadata !{i32 8, i32 42, metadata !11, null}
 !14 = metadata !{i32 4, i32 28, metadata !15, null}
-!15 = metadata !{i32 786443, metadata !9, i32 4, i32 26, metadata !6, i32 2} ; [ DW_TAG_lexical_block ] [/home/samsonov/tmp/clang-di/test.cc]
+!15 = metadata !{i32 786443, metadata !20, metadata !9, i32 4, i32 26, i32 2} ; [ DW_TAG_lexical_block ] [/home/samsonov/tmp/clang-di/test.cc]
 !16 = metadata !{i32 4, i32 33, metadata !15, null}
 !17 = metadata !{i32 5, i32 25, metadata !18, null}
-!18 = metadata !{i32 786443, metadata !8, i32 5, i32 23, metadata !6, i32 1} ; [ DW_TAG_lexical_block ] [/home/samsonov/tmp/clang-di/test.cc]
+!18 = metadata !{i32 786443, metadata !20, metadata !8, i32 5, i32 23, i32 1} ; [ DW_TAG_lexical_block ] [/home/samsonov/tmp/clang-di/test.cc]
 !19 = metadata !{i32 5, i32 30, metadata !18, null}
 !20 = metadata !{metadata !"test.cc", metadata !"/home/samsonov/tmp/clang-di"}
diff --git a/test/Transforms/DeadArgElim/deadexternal.ll b/test/Transforms/DeadArgElim/deadexternal.ll
index cca5872..acbcf75 100644
--- a/test/Transforms/DeadArgElim/deadexternal.ll
+++ b/test/Transforms/DeadArgElim/deadexternal.ll
@@ -7,7 +7,7 @@ define void @test(i32) {
 define void @foo() {
   call void @test(i32 0)
   ret void
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK: i32 undef
 }
 
diff --git a/test/Transforms/DeadArgElim/keepalive.ll b/test/Transforms/DeadArgElim/keepalive.ll
index e41110c..82e01f2 100644
--- a/test/Transforms/DeadArgElim/keepalive.ll
+++ b/test/Transforms/DeadArgElim/keepalive.ll
@@ -13,7 +13,7 @@ define internal zeroext i32 @test1(i32 %DEADARG1) nounwind {
 }
 
 ; This checks if the struct doesn't get non-packed
-; CHECK: define internal <{ i32, i32 }> @test2
+; CHECK-LABEL: define internal <{ i32, i32 }> @test2(
 define internal <{ i32, i32 }> @test2(i32 %DEADARG1) {
         ret <{ i32, i32 }> <{ i32 1, i32 2 }>
 }
diff --git a/test/Transforms/DeadArgElim/returned.ll b/test/Transforms/DeadArgElim/returned.ll
new file mode 100644
index 0000000..cbee026
--- /dev/null
+++ b/test/Transforms/DeadArgElim/returned.ll
@@ -0,0 +1,55 @@
+; RUN: opt < %s -deadargelim -S | FileCheck %s
+
+%Ty = type { i32, i32 }
+
+; sanity check that the argument and return value are both dead
+; CHECK-LABEL: define internal void @test1()
+
+define internal %Ty* @test1(%Ty* %this) {
+  ret %Ty* %this
+}
+
+; do not keep alive the return value of a function with a dead 'returned' argument
+; CHECK-LABEL: define internal void @test2()
+
+define internal %Ty* @test2(%Ty* returned %this) {
+  ret %Ty* %this
+}
+
+; dummy to keep 'this' alive
+@dummy = global %Ty* null 
+
+; sanity check that return value is dead
+; CHECK-LABEL: define internal void @test3(%Ty* %this)
+
+define internal %Ty* @test3(%Ty* %this) {
+  store volatile %Ty* %this, %Ty** @dummy
+  ret %Ty* %this
+}
+
+; keep alive return value of a function if the 'returned' argument is live
+; CHECK-LABEL: define internal %Ty* @test4(%Ty* returned %this)
+
+define internal %Ty* @test4(%Ty* returned %this) {
+  store volatile %Ty* %this, %Ty** @dummy
+  ret %Ty* %this
+}
+
+; don't do this if 'returned' is on the call site...
+; CHECK-LABEL: define internal void @test5(%Ty* %this)
+
+define internal %Ty* @test5(%Ty* %this) {
+  store volatile %Ty* %this, %Ty** @dummy
+  ret %Ty* %this
+}
+
+define %Ty* @caller(%Ty* %this) {
+  %1 = call %Ty* @test1(%Ty* %this)
+  %2 = call %Ty* @test2(%Ty* %this)
+  %3 = call %Ty* @test3(%Ty* %this)
+  %4 = call %Ty* @test4(%Ty* %this)
+; ...instead, drop 'returned' form the call site
+; CHECK: call void @test5(%Ty* %this)
+  %5 = call %Ty* @test5(%Ty* returned %this)
+  ret %Ty* %this
+}
diff --git a/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll b/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll
index d114e51..95253f6 100644
--- a/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll
+++ b/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll
@@ -5,7 +5,7 @@ target triple = "x86_64-apple-darwin"
 
 %"class.std::auto_ptr" = type { i32* }
 
-; CHECK: @_Z3foov
+; CHECK-LABEL: @_Z3foov(
 define void @_Z3foov(%"class.std::auto_ptr"* noalias nocapture sret %agg.result) uwtable ssp {
 _ZNSt8auto_ptrIiED1Ev.exit:
   %temp.lvalue = alloca %"class.std::auto_ptr", align 8
diff --git a/test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll b/test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll
index ed53eb5..968d608 100644
--- a/test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll
+++ b/test/Transforms/DeadStoreElimination/OverwriteStoreEnd.ll
@@ -8,7 +8,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 @glob2 = global %struct.vec2plusi zeroinitializer, align 16
 
 define void @write24to28(i32* nocapture %p) nounwind uwtable ssp {
-; CHECK: @write24to28
+; CHECK-LABEL: @write24to28(
 entry:
   %arrayidx0 = getelementptr inbounds i32* %p, i64 1
   %p3 = bitcast i32* %arrayidx0 to i8*
@@ -20,7 +20,7 @@ entry:
 }
 
 define void @write28to32(i32* nocapture %p) nounwind uwtable ssp {
-; CHECK: @write28to32
+; CHECK-LABEL: @write28to32(
 entry:
   %p3 = bitcast i32* %p to i8*
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %p3, i8 0, i64 28, i32 4, i1 false)
@@ -31,7 +31,7 @@ entry:
 }
 
 define void @dontwrite28to32memset(i32* nocapture %p) nounwind uwtable ssp {
-; CHECK: @dontwrite28to32memset
+; CHECK-LABEL: @dontwrite28to32memset(
 entry:
   %p3 = bitcast i32* %p to i8*
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %p3, i8 0, i64 32, i32 16, i1 false)
@@ -42,7 +42,7 @@ entry:
 }
 
 define void @write32to36(%struct.vec2plusi* nocapture %p) nounwind uwtable ssp {
-; CHECK: @write32to36
+; CHECK-LABEL: @write32to36(
 entry:
   %0 = bitcast %struct.vec2plusi* %p to i8*
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.vec2plusi* @glob2 to i8*), i64 32, i32 16, i1 false)
@@ -53,7 +53,7 @@ entry:
 }
 
 define void @write16to32(%struct.vec2* nocapture %p) nounwind uwtable ssp {
-; CHECK: @write16to32
+; CHECK-LABEL: @write16to32(
 entry:
   %0 = bitcast %struct.vec2* %p to i8*
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.vec2* @glob1 to i8*), i64 16, i32 16, i1 false)
@@ -64,7 +64,7 @@ entry:
 }
 
 define void @dontwrite28to32memcpy(%struct.vec2* nocapture %p) nounwind uwtable ssp {
-; CHECK: @dontwrite28to32memcpy
+; CHECK-LABEL: @dontwrite28to32memcpy(
 entry:
   %0 = bitcast %struct.vec2* %p to i8*
 ; CHECK: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.vec2* @glob1 to i8*), i64 32, i32 16, i1 false)
@@ -80,7 +80,7 @@ declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
 %struct.trapframe = type { i64, i64, i64 }
 
 ; bugzilla 11455 - make sure negative GEP's don't break this optimisation
-; CHECK: @cpu_lwp_fork
+; CHECK-LABEL: @cpu_lwp_fork(
 define void @cpu_lwp_fork(%struct.trapframe* %md_regs, i64 %pcb_rsp0) nounwind uwtable noinline ssp {
 entry:
   %0 = inttoptr i64 %pcb_rsp0 to %struct.trapframe*
diff --git a/test/Transforms/DeadStoreElimination/PartialStore.ll b/test/Transforms/DeadStoreElimination/PartialStore.ll
index 7ac1e08..4799ef3 100644
--- a/test/Transforms/DeadStoreElimination/PartialStore.ll
+++ b/test/Transforms/DeadStoreElimination/PartialStore.ll
@@ -8,13 +8,13 @@ define void @test1(i32 *%V) {
         store i8 0, i8* %V2
         store i32 1234567, i32* %V
         ret void
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: store i32 1234567
 }
 
 ; Note that we could do better by merging the two stores into one.
 define void @test2(i32* %P) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
   store i32 0, i32* %P
 ; CHECK: store i32
   %Q = bitcast i32* %P to i16*
@@ -25,7 +25,7 @@ define void @test2(i32* %P) {
 
 
 define i32 @test3(double %__x) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: store double
   %__u = alloca { [3 x i32] }
   %tmp.1 = bitcast { [3 x i32] }* %__u to double*
@@ -39,7 +39,7 @@ define i32 @test3(double %__x) {
 
 ; PR6043
 define void @test4(i8* %P) {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: bitcast
 ; CHECK-NEXT: store double
 
@@ -64,7 +64,7 @@ define void @test5(i32 %i) nounwind ssp {
   
   call void @test5a(i32* %A)
   ret void
-; CHECK: @test5(
+; CHECK-LABEL: @test5(
 ; CHECK-NEXT: alloca
 ; CHECK-NEXT: store i32 20
 ; CHECK-NEXT: call void @test5a
diff --git a/test/Transforms/DeadStoreElimination/const-pointers.ll b/test/Transforms/DeadStoreElimination/const-pointers.ll
index 15976f9..c90d824 100644
--- a/test/Transforms/DeadStoreElimination/const-pointers.ll
+++ b/test/Transforms/DeadStoreElimination/const-pointers.ll
@@ -11,7 +11,7 @@ define void @test1(%t* noalias %pp) {
   %x = load i32* inttoptr (i32 12345 to i32*)
   store i32 %x, i32* %p
   ret void
-; CHECK: define void @test1
+; CHECK-LABEL: define void @test1(
 ; CHECK: store
 ; CHECK-NOT: store
 ; CHECK: ret void
@@ -21,7 +21,7 @@ define void @test3() {
   store i32 1, i32* @g; <-- This is dead.
   store i32 42, i32* @g
   ret void
-; CHECK: define void @test3
+; CHECK-LABEL: define void @test3(
 ; CHECK: store
 ; CHECK-NOT: store
 ; CHECK: ret void
@@ -32,7 +32,7 @@ define void @test4(i32* %p) {
   %x = load i32* @g; <-- %p and @g could alias
   store i32 %x, i32* %p
   ret void
-; CHECK: define void @test4
+; CHECK-LABEL: define void @test4(
 ; CHECK: store
 ; CHECK: store
 ; CHECK: ret void
diff --git a/test/Transforms/DeadStoreElimination/free.ll b/test/Transforms/DeadStoreElimination/free.ll
index a5fbdc7..1d273d6 100644
--- a/test/Transforms/DeadStoreElimination/free.ll
+++ b/test/Transforms/DeadStoreElimination/free.ll
@@ -5,7 +5,7 @@ target datalayout = "e-p:64:64:64"
 declare void @free(i8* nocapture)
 declare noalias i8* @malloc(i64)
 
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK-NEXT: bitcast
 ; CHECK-NEXT: @free
 ; CHECK-NEXT: ret void
@@ -17,7 +17,7 @@ define void @test(i32* %Q, i32* %P) {
         ret void
 }
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: bitcast
 ; CHECK-NEXT: @free
 ; CHECK-NEXT: ret void
@@ -29,7 +29,7 @@ define void @test2({i32, i32}* %P) {
 	ret void
 }
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NOT: store
 ; CHECK: ret void
 define void @test3() {
@@ -42,7 +42,7 @@ define void @test3() {
 }
 
 ; PR11240
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NOT: store
 ; CHECK: ret void
 define void @test4(i1 %x) nounwind {
@@ -59,7 +59,7 @@ skipinit1:
   ret void
 }
 
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 define void @test5() {
   br label %bb
 
diff --git a/test/Transforms/DeadStoreElimination/libcalls.ll b/test/Transforms/DeadStoreElimination/libcalls.ll
index 4639c0b..6539694 100644
--- a/test/Transforms/DeadStoreElimination/libcalls.ll
+++ b/test/Transforms/DeadStoreElimination/libcalls.ll
@@ -2,7 +2,7 @@
 
 declare i8* @strcpy(i8* %dest, i8* %src) nounwind
 define void @test1(i8* %src) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
   %B = alloca [16 x i8]
   %dest = getelementptr inbounds [16 x i8]* %B, i64 0, i64 0
 ; CHECK-NOT: @strcpy
@@ -13,7 +13,7 @@ define void @test1(i8* %src) {
 
 declare i8* @strncpy(i8* %dest, i8* %src, i32 %n) nounwind
 define void @test2(i8* %src) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
   %B = alloca [16 x i8]
   %dest = getelementptr inbounds [16 x i8]* %B, i64 0, i64 0
 ; CHECK-NOT: @strncpy
@@ -24,7 +24,7 @@ define void @test2(i8* %src) {
 
 declare i8* @strcat(i8* %dest, i8* %src) nounwind
 define void @test3(i8* %src) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
   %B = alloca [16 x i8]
   %dest = getelementptr inbounds [16 x i8]* %B, i64 0, i64 0
 ; CHECK-NOT: @strcat
@@ -35,7 +35,7 @@ define void @test3(i8* %src) {
 
 declare i8* @strncat(i8* %dest, i8* %src, i32 %n) nounwind
 define void @test4(i8* %src) {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
   %B = alloca [16 x i8]
   %dest = getelementptr inbounds [16 x i8]* %B, i64 0, i64 0
 ; CHECK-NOT: @strncat
@@ -45,7 +45,7 @@ define void @test4(i8* %src) {
 }
 
 define void @test5(i8* nocapture %src) {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
   %dest = alloca [100 x i8], align 16
   %arraydecay = getelementptr inbounds [100 x i8]* %dest, i64 0, i64 0
   %call = call i8* @strcpy(i8* %arraydecay, i8* %src)
@@ -57,7 +57,7 @@ define void @test5(i8* nocapture %src) {
 
 declare void @user(i8* %p)
 define void @test6(i8* %src) {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
   %B = alloca [16 x i8]
   %dest = getelementptr inbounds [16 x i8]* %B, i64 0, i64 0
 ; CHECK: @strcpy
diff --git a/test/Transforms/DeadStoreElimination/lifetime.ll b/test/Transforms/DeadStoreElimination/lifetime.ll
index 6785653..7fe7fbf 100644
--- a/test/Transforms/DeadStoreElimination/lifetime.ll
+++ b/test/Transforms/DeadStoreElimination/lifetime.ll
@@ -7,7 +7,7 @@ declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind
 declare void @llvm.memset.p0i8.i8(i8* nocapture, i8, i8, i32, i1) nounwind
 
 define void @test1() {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
   %A = alloca i8
 
   store i8 0, i8* %A  ;; Written to by memset
diff --git a/test/Transforms/DeadStoreElimination/memintrinsics.ll b/test/Transforms/DeadStoreElimination/memintrinsics.ll
index d5c5365..5bbb8e0 100644
--- a/test/Transforms/DeadStoreElimination/memintrinsics.ll
+++ b/test/Transforms/DeadStoreElimination/memintrinsics.ll
@@ -5,7 +5,7 @@ declare void @llvm.memmove.p0i8.p0i8.i8(i8* nocapture, i8* nocapture, i8, i32, i
 declare void @llvm.memset.p0i8.i8(i8* nocapture, i8, i8, i32, i1) nounwind
 
 define void @test1() {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
   %A = alloca i8
   %B = alloca i8
 
@@ -19,7 +19,7 @@ define void @test1() {
 }
 
 define void @test2() {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
   %A = alloca i8
   %B = alloca i8
 
@@ -33,7 +33,7 @@ define void @test2() {
 }
 
 define void @test3() {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
   %A = alloca i8
   %B = alloca i8
 
diff --git a/test/Transforms/DeadStoreElimination/no-targetdata.ll b/test/Transforms/DeadStoreElimination/no-targetdata.ll
index 4022d76..c0c7c58 100644
--- a/test/Transforms/DeadStoreElimination/no-targetdata.ll
+++ b/test/Transforms/DeadStoreElimination/no-targetdata.ll
@@ -7,7 +7,7 @@ define void @test1(i32* noalias %p) {
        call void @test1f()
        store i32 2, i32 *%p
        ret void
-; CHECK: define void @test1
+; CHECK-LABEL: define void @test1(
 ; CHECK-NOT: store
 ; CHECK-NEXT: call void
 ; CHECK-NEXT: store i32 2
diff --git a/test/Transforms/DeadStoreElimination/simple.ll b/test/Transforms/DeadStoreElimination/simple.ll
index e0eb90a..ec98466 100644
--- a/test/Transforms/DeadStoreElimination/simple.ll
+++ b/test/Transforms/DeadStoreElimination/simple.ll
@@ -10,7 +10,7 @@ define void @test1(i32* %Q, i32* %P) {
         store i32 %DEAD, i32* %P
         store i32 0, i32* %P
         ret void
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: store i32 0, i32* %P
 ; CHECK-NEXT: ret void
 }
@@ -21,7 +21,7 @@ define void @test2(i32 *%p, i32 *%q) {
   store i32 20, i32* %q, align 4
   store i32 30, i32* %p, align 4
   ret void
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: store i32 20
 }
 
@@ -30,7 +30,7 @@ define void @test2(i32 *%p, i32 *%q) {
 @g = global i32 1
 
 define i32 @test3(i32* %g_addr) nounwind {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: load i32* %g_addr
   %g_value = load i32* %g_addr, align 4
   store i32 -1, i32* @g, align 4
@@ -44,7 +44,7 @@ define void @test4(i32* %Q) {
         %a = load i32* %Q
         store volatile i32 %a, i32* %Q
         ret void
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: load i32
 ; CHECK-NEXT: store volatile
 ; CHECK-NEXT: ret void
@@ -54,7 +54,7 @@ define void @test5(i32* %Q) {
         %a = load volatile i32* %Q
         store i32 %a, i32* %Q
         ret void
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NEXT: load volatile
 ; CHECK-NEXT: ret void
 }
@@ -66,7 +66,7 @@ define void @test6(i32 *%p, i8 *%q) {
   call void @llvm.memset.p0i8.i64(i8* %q, i8 42, i64 900, i32 1, i1 false)
   store i32 30, i32* %p, align 4
   ret void
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: call void @llvm.memset
 }
 
@@ -77,7 +77,7 @@ define void @test7(i32 *%p, i8 *%q, i8* noalias %r) {
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %q, i8* %r, i64 900, i32 1, i1 false)
   store i32 30, i32* %p, align 4
   ret void
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NEXT: call void @llvm.memcpy
 }
 
@@ -90,7 +90,7 @@ define i32 @test8() {
         %X = load i32* %V
         ret i32 %X
         
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: store i32 1234567
 }
 
@@ -101,7 +101,7 @@ define void @test9(%struct.x* byval  %a) nounwind  {
 	%tmp2 = getelementptr %struct.x* %a, i32 0, i32 0
 	store i32 1, i32* %tmp2, align 4
 	ret void
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NEXT: ret void
 }
 
@@ -111,7 +111,7 @@ define double @test10(i8* %X) {
         store i8* %X, i8** %X_addr
         %tmp.0 = va_arg i8** %X_addr, double
         ret double %tmp.0
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK: store
 }
 
@@ -119,7 +119,7 @@ define double @test10(i8* %X) {
 ; DSE should delete the dead trampoline.
 declare void @test11f()
 define void @test11() {
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 	%storage = alloca [10 x i8], align 16		; <[10 x i8]*> [#uses=1]
 ; CHECK-NOT: alloca
 	%cast = getelementptr [10 x i8]* %storage, i32 0, i32 0		; <i8*> [#uses=1]
@@ -140,7 +140,7 @@ define void @test12({ i32, i32 }* %x) nounwind  {
 	store i32 %tmp5, i32* %tmp4, align 4
 	store i32 %tmp17, i32* %tmp7, align 4
 	ret void
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK-NOT: tmp5
 ; CHECK: ret void
 }
@@ -173,7 +173,7 @@ define void @test14(i32* %Q) {
         store i32 %DEAD, i32* %P
         ret void
 
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK-NEXT: ret void
 }
 
@@ -185,7 +185,7 @@ define void @test15(i8* %P, i8* %Q) nounwind ssp {
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %P, i8* %Q, i64 12, i32 1, i1 false)
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %P, i8* %Q, i64 12, i32 1, i1 false)
   ret void
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 ; CHECK-NEXT: call void @llvm.memcpy
 ; CHECK-NEXT: ret
 }
@@ -195,7 +195,7 @@ define void @test16(i8* %P, i8* %Q) nounwind ssp {
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %P, i8* %Q, i64 8, i32 1, i1 false)
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %P, i8* %Q, i64 12, i32 1, i1 false)
   ret void
-; CHECK: @test16
+; CHECK-LABEL: @test16(
 ; CHECK-NEXT: call void @llvm.memcpy
 ; CHECK-NEXT: ret
 }
@@ -205,7 +205,7 @@ define void @test17(i8* %P, i8* noalias %Q) nounwind ssp {
   tail call void @llvm.memset.p0i8.i64(i8* %P, i8 42, i64 8, i32 1, i1 false)
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %P, i8* %Q, i64 12, i32 1, i1 false)
   ret void
-; CHECK: @test17
+; CHECK-LABEL: @test17(
 ; CHECK-NEXT: call void @llvm.memcpy
 ; CHECK-NEXT: ret
 }
@@ -215,7 +215,7 @@ define void @test17v(i8* %P, i8* %Q) nounwind ssp {
   tail call void @llvm.memset.p0i8.i64(i8* %P, i8 42, i64 8, i32 1, i1 true)
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %P, i8* %Q, i64 12, i32 1, i1 false)
   ret void
-; CHECK: @test17v
+; CHECK-LABEL: @test17v(
 ; CHECK-NEXT: call void @llvm.memset
 ; CHECK-NEXT: call void @llvm.memcpy
 ; CHECK-NEXT: ret
@@ -229,7 +229,7 @@ define void @test18(i8* %P, i8* %Q, i8* %R) nounwind ssp {
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %P, i8* %Q, i64 12, i32 1, i1 false)
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %P, i8* %R, i64 12, i32 1, i1 false)
   ret void
-; CHECK: @test18
+; CHECK-LABEL: @test18(
 ; CHECK-NEXT: call void @llvm.memcpy
 ; CHECK-NEXT: call void @llvm.memcpy
 ; CHECK-NEXT: ret
@@ -246,7 +246,7 @@ bb:
   call void @test19f({i32}* byval align 4 %arg5)
   ret void
 
-; CHECK: @test19(
+; CHECK-LABEL: @test19(
 ; CHECK: store i32 912
 ; CHECK: call void @test19f
 }
@@ -256,10 +256,10 @@ define void @test20() {
   store i8 0, i8* %m
   ret void
 }
-; CHECK: @test20
+; CHECK-LABEL: @test20(
 ; CHECK-NEXT: ret void
 
-; CHECK: @test21
+; CHECK-LABEL: @test21(
 define void @test21() {
   %m = call i8* @calloc(i32 9, i32 7)
   store i8 0, i8* %m
@@ -267,7 +267,7 @@ define void @test21() {
   ret void
 }
 
-; CHECK: @test22(
+; CHECK-LABEL: @test22(
 define void @test22(i1 %i, i32 %k, i32 %m) nounwind {
   %k.addr = alloca i32
   %m.addr = alloca i32
@@ -278,7 +278,7 @@ define void @test22(i1 %i, i32 %k, i32 %m) nounwind {
 }
 
 ; PR13547
-; CHECK: @test23
+; CHECK-LABEL: @test23(
 ; CHECK: store i8 97
 ; CHECK: store i8 0
 declare noalias i8* @strdup(i8* nocapture) nounwind
@@ -293,7 +293,7 @@ define noalias i8* @test23() nounwind uwtable ssp {
 }
 
 ; Make sure same sized store to later element is deleted
-; CHECK: @test24
+; CHECK-LABEL: @test24(
 ; CHECK-NOT: store i32 0
 ; CHECK-NOT: store i32 0
 ; CHECK: store i32 %b
@@ -312,7 +312,7 @@ define void @test24([2 x i32]* %a, i32 %b, i32 %c) nounwind {
 }
 
 ; Check another case like PR13547 where strdup is not like malloc.
-; CHECK: @test25
+; CHECK-LABEL: @test25(
 ; CHECK: load i8
 ; CHECK: store i8 0
 ; CHECK: store i8 %tmp
diff --git a/test/Transforms/DebugIR/crash.ll b/test/Transforms/DebugIR/crash.ll
new file mode 100644
index 0000000..f4a88d7
--- /dev/null
+++ b/test/Transforms/DebugIR/crash.ll
@@ -0,0 +1,42 @@
+; ModuleID = 'crash.c'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnu"
+
+@.str = private unnamed_addr constant [18 x i8] c"Hello, segfault!\0A\00", align 1
+@.str1 = private unnamed_addr constant [14 x i8] c"Now crash %d\0A\00", align 1
+
+; Function Attrs: nounwind uwtable
+define i32 @main(i32 %argc, i8** %argv) #0 {
+  %1 = alloca i32, align 4                                        ;CHECK: !dbg
+  %2 = alloca i32, align 4                                        ;CHECK-NEXT: !dbg
+  %3 = alloca i8**, align 8                                       ;CHECK-NEXT: !dbg
+  %null_ptr = alloca i32*, align 8                                ;CHECK-NEXT: !dbg
+  store i32 0, i32* %1                                            ;CHECK-NEXT: !dbg
+  store i32 %argc, i32* %2, align 4                               ;CHECK-NEXT: !dbg
+  store i8** %argv, i8*** %3, align 8                             ;CHECK-NEXT: !dbg
+  store i32* null, i32** %null_ptr, align 8                       ;CHECK-NEXT: !dbg
+  %4 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([18 x i8]* @.str, i32 0, i32 0)) ;CHECK-NEXT: !dbg
+  %5 = load i32** %null_ptr, align 8                              ;CHECK-NEXT: !dbg
+  %6 = load i32* %5, align 4                                      ;CHECK-NEXT: !dbg
+  %7 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([14 x i8]* @.str1, i32 0, i32 0), i32 %6) ;CHECK-NEXT: !dbg
+  %8 = load i32* %2, align 4                                      ;CHECK-NEXT: !dbg
+  ret i32 %8                                                      ;CHECK-NEXT: !dbg
+}
+
+declare i32 @printf(i8*, ...) #1
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+; CHECK: = metadata !{i32 14,
+; CHECK-NEXT: = metadata !{i32 15,
+; CHECK-NEXT: = metadata !{i32 16,
+; CHECK-NEXT: = metadata !{i32 17,
+; CHECK-NEXT: = metadata !{i32 18,
+; CHECK-NEXT: = metadata !{i32 19,
+; CHECK-NEXT: = metadata !{i32 20,
+; CHECK-NEXT: = metadata !{i32 21,
+; CHECK-NEXT: = metadata !{i32 22,
+; CHECK-NEXT: = metadata !{i32 23,
+
+; RUN: opt %s -debug-ir -S | FileCheck %s
diff --git a/test/Transforms/DebugIR/exception.ll b/test/Transforms/DebugIR/exception.ll
new file mode 100644
index 0000000..2436d38
--- /dev/null
+++ b/test/Transforms/DebugIR/exception.ll
@@ -0,0 +1,127 @@
+; ModuleID = 'exception.cpp'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnu"
+
+@_ZTIi = external constant i8*
+
+; Function Attrs: uwtable
+define i32 @main(i32 %argc, i8** %argv) #0 {
+  %1 = alloca i32, align 4                        ; CHECK: !dbg
+  %2 = alloca i32, align 4                        ; CHECK-NEXT: !dbg
+  %3 = alloca i8**, align 8                       ; CHECK-NEXT: !dbg
+  %4 = alloca i8*                                 ; CHECK-NEXT: !dbg
+  %5 = alloca i32                                 ; CHECK-NEXT: !dbg
+  %e = alloca i32, align 4                        ; CHECK-NEXT: !dbg
+  %6 = alloca i32                                 ; CHECK-NEXT: !dbg
+  store i32 0, i32* %1                            ; CHECK-NEXT: !dbg
+  store i32 %argc, i32* %2, align 4               ; CHECK-NEXT: !dbg
+  store i8** %argv, i8*** %3, align 8             ; CHECK-NEXT: !dbg
+  %7 = call i8* @__cxa_allocate_exception(i64 4) #2 ; CHECK-NEXT: !dbg
+  %8 = bitcast i8* %7 to i32*                     ; CHECK-NEXT: !dbg
+  %9 = load i32* %2, align 4                      ; CHECK-NEXT: !dbg
+  store i32 %9, i32* %8                           ; CHECK-NEXT: !dbg
+  invoke void @__cxa_throw(i8* %7, i8* bitcast (i8** @_ZTIi to i8*), i8* null) #3
+          to label %31 unwind label %10           ; CHECK: !dbg
+
+; <label>:10                                      ; preds = %0
+  %11 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          catch i8* bitcast (i8** @_ZTIi to i8*)  ; CHECK: !dbg
+  %12 = extractvalue { i8*, i32 } %11, 0          ; CHECK-NEXT: !dbg
+  store i8* %12, i8** %4                          ; CHECK-NEXT: !dbg
+  %13 = extractvalue { i8*, i32 } %11, 1          ; CHECK-NEXT: !dbg
+  store i32 %13, i32* %5                          ; CHECK-NEXT: !dbg
+  br label %14                                    ; CHECK-NEXT: !dbg
+
+; <label>:14                                      ; preds = %10
+  %15 = load i32* %5                              ; CHECK: !dbg
+  %16 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) #2   ; CHECK-NEXT: !dbg
+  %17 = icmp eq i32 %15, %16                      ; CHECK-NEXT: !dbg
+  br i1 %17, label %18, label %26                 ; CHECK-NEXT: !dbg
+
+; <label>:18                                      ; preds = %14
+  %19 = load i8** %4                              ; CHECK: !dbg
+  %20 = call i8* @__cxa_begin_catch(i8* %19) #2   ; CHECK-NEXT: !dbg
+  %21 = bitcast i8* %20 to i32*                   ; CHECK-NEXT: !dbg
+  %22 = load i32* %21, align 4                    ; CHECK-NEXT: !dbg
+  store i32 %22, i32* %e, align 4                 ; CHECK-NEXT: !dbg
+  %23 = load i32* %e, align 4                     ; CHECK-NEXT: !dbg
+  store i32 %23, i32* %1                          ; CHECK-NEXT: !dbg
+  store i32 1, i32* %6                            ; CHECK-NEXT: !dbg
+  call void @__cxa_end_catch() #2                 ; CHECK-NEXT: !dbg
+  br label %24                                    ; CHECK-NEXT: !dbg
+
+; <label>:24                                      ; preds = %18
+  %25 = load i32* %1                              ; CHECK: !dbg
+  ret i32 %25                                     ; CHECK-NEXT: !dbg
+
+; <label>:26                                      ; preds = %14
+  %27 = load i8** %4                              ; CHECK: !dbg
+  %28 = load i32* %5                              ; CHECK-NEXT: !dbg
+  %29 = insertvalue { i8*, i32 } undef, i8* %27, 0 ; CHECK-NEXT: !dbg
+  %30 = insertvalue { i8*, i32 } %29, i32 %28, 1   ; CHECK-NEXT: !dbg
+  resume { i8*, i32 } %30                         ; CHECK-NEXT: !dbg
+
+; <label>:31                                      ; preds = %0
+  unreachable                                     ; CHECK: !dbg
+}
+
+declare i8* @__cxa_allocate_exception(i64)
+
+declare void @__cxa_throw(i8*, i8*, i8*)
+
+declare i32 @__gxx_personality_v0(...)
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.eh.typeid.for(i8*) #1
+
+declare i8* @__cxa_begin_catch(i8*)
+
+declare void @__cxa_end_catch()
+
+attributes #0 = { uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind }
+attributes #3 = { noreturn }
+; CHECK: = metadata !{i32 16,
+; CHECK-NEXT: = metadata !{i32 17,
+; CHECK-NEXT: = metadata !{i32 18,
+; CHECK-NEXT: = metadata !{i32 19,
+; CHECK-NEXT: = metadata !{i32 20,
+; CHECK-NEXT: = metadata !{i32 21,
+; CHECK-NEXT: = metadata !{i32 22,
+; CHECK-NEXT: = metadata !{i32 24,
+
+; CHECK-NEXT: = metadata !{i32 28,
+; CHECK-NEXT: = metadata !{i32 29,
+; CHECK-NEXT: = metadata !{i32 30,
+; CHECK-NEXT: = metadata !{i32 31,
+; CHECK-NEXT: = metadata !{i32 32,
+; CHECK-NEXT: = metadata !{i32 33,
+
+; CHECK-NEXT: = metadata !{i32 36,
+; CHECK-NEXT: = metadata !{i32 37,
+; CHECK-NEXT: = metadata !{i32 38,
+; CHECK-NEXT: = metadata !{i32 39,
+
+; CHECK-NEXT: = metadata !{i32 42,
+; CHECK-NEXT: = metadata !{i32 43,
+; CHECK-NEXT: = metadata !{i32 44,
+; CHECK-NEXT: = metadata !{i32 45,
+; CHECK-NEXT: = metadata !{i32 46,
+; CHECK-NEXT: = metadata !{i32 47,
+; CHECK-NEXT: = metadata !{i32 48,
+; CHECK-NEXT: = metadata !{i32 49,
+; CHECK-NEXT: = metadata !{i32 50,
+; CHECK-NEXT: = metadata !{i32 51,
+
+; CHECK-NEXT: = metadata !{i32 54,
+; CHECK-NEXT: = metadata !{i32 55,
+
+; CHECK-NEXT: = metadata !{i32 58,
+; CHECK-NEXT: = metadata !{i32 59,
+; CHECK-NEXT: = metadata !{i32 60,
+; CHECK-NEXT: = metadata !{i32 61,
+; CHECK-NEXT: = metadata !{i32 62,
+; CHECK-NEXT: = metadata !{i32 65,
+
+; RUN: opt %s -debug-ir -S | FileCheck %s
diff --git a/test/Transforms/DebugIR/function.ll b/test/Transforms/DebugIR/function.ll
new file mode 100644
index 0000000..dba073d
--- /dev/null
+++ b/test/Transforms/DebugIR/function.ll
@@ -0,0 +1,51 @@
+; ModuleID = 'function.c'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnu"
+
+; Function Attrs: nounwind uwtable
+define void @blah(i32* %i) #0 {
+  %1 = alloca i32*, align 8                   ; CHECK: !dbg
+  store i32* %i, i32** %1, align 8            ; CHECK-NEXT: !dbg
+  %2 = load i32** %1, align 8                 ; CHECK-NEXT: !dbg
+  %3 = load i32* %2, align 4                  ; CHECK-NEXT: !dbg
+  %4 = add nsw i32 %3, 1                      ; CHECK-NEXT: !dbg
+  store i32 %4, i32* %2, align 4              ; CHECK-NEXT: !dbg
+  ret void                                    ; CHECK-NEXT: !dbg
+}
+
+; Function Attrs: nounwind uwtable
+define i32 @main(i32 %argc, i8** %argv) #0 {
+  %1 = alloca i32, align 4                    ; CHECK: !dbg
+  %2 = alloca i32, align 4                    ; CHECK-NEXT: !dbg
+  %3 = alloca i8**, align 8                   ; CHECK-NEXT: !dbg
+  %i = alloca i32, align 4                    ; CHECK-NEXT: !dbg
+  store i32 0, i32* %1                        ; CHECK-NEXT: !dbg
+  store i32 %argc, i32* %2, align 4           ; CHECK-NEXT: !dbg
+  store i8** %argv, i8*** %3, align 8         ; CHECK-NEXT: !dbg
+  store i32 7, i32* %i, align 4               ; CHECK-NEXT: !dbg
+  call void @blah(i32* %i)                    ; CHECK-NEXT: !dbg
+  %4 = load i32* %i, align 4                  ; CHECK-NEXT: !dbg
+  ret i32 %4                                  ; CHECK-NEXT: !dbg
+}
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+; CHECK: = metadata !{i32 8,
+; CHECK-NEXT: = metadata !{i32 9,
+; CHECK-NEXT: = metadata !{i32 10,
+; CHECK-NEXT: = metadata !{i32 11,
+; CHECK-NEXT: = metadata !{i32 12,
+; CHECK-NEXT: = metadata !{i32 13,
+
+; CHECK-NEXT: = metadata !{i32 18,
+; CHECK-NEXT: = metadata !{i32 19,
+; CHECK-NEXT: = metadata !{i32 20,
+; CHECK-NEXT: = metadata !{i32 21,
+; CHECK-NEXT: = metadata !{i32 22,
+; CHECK-NEXT: = metadata !{i32 23,
+; CHECK-NEXT: = metadata !{i32 24,
+; CHECK-NEXT: = metadata !{i32 25,
+; CHECK-NEXT: = metadata !{i32 26,
+; CHECK-NEXT: = metadata !{i32 27,
+; CHECK-NEXT: = metadata !{i32 28,
+
+; RUN: opt %s -debug-ir -S | FileCheck %s
diff --git a/test/Transforms/DebugIR/lit.local.cfg b/test/Transforms/DebugIR/lit.local.cfg
new file mode 100644
index 0000000..c6106e4
--- /dev/null
+++ b/test/Transforms/DebugIR/lit.local.cfg
@@ -0,0 +1 @@
+config.suffixes = ['.ll']
diff --git a/test/Transforms/DebugIR/simple.ll b/test/Transforms/DebugIR/simple.ll
new file mode 100644
index 0000000..3b18895
--- /dev/null
+++ b/test/Transforms/DebugIR/simple.ll
@@ -0,0 +1,25 @@
+; ModuleID = 'simple.c'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnu"
+
+; Function Attrs: nounwind uwtable
+define i32 @main(i32 %argc, i8** %argv) #0 {
+  %1 = alloca i32, align 4                  ; CHECK: !dbg
+  %2 = alloca i32, align 4                  ; CHECK-NEXT: !dbg
+  %3 = alloca i8**, align 8                 ; CHECK-NEXT: !dbg
+  store i32 0, i32* %1                      ; CHECK-NEXT: !dbg
+  store i32 %argc, i32* %2, align 4         ; CHECK-NEXT: !dbg
+  store i8** %argv, i8*** %3, align 8       ; CHECK-NEXT: !dbg
+  %4 = load i32* %2, align 4                ; CHECK-NEXT: !dbg
+  ret i32 %4                                ; CHECK-NEXT: !dbg
+}
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+; CHECK: = metadata !{i32 10,
+; CHECK-NEXT: = metadata !{i32 11,
+; CHECK-NEXT: = metadata !{i32 12,
+; CHECK-NEXT: = metadata !{i32 13,
+; CHECK-NEXT: = metadata !{i32 14,
+
+; RUN: opt %s -debug-ir -S | FileCheck %s
diff --git a/test/Transforms/DebugIR/struct.ll b/test/Transforms/DebugIR/struct.ll
new file mode 100644
index 0000000..8db3dbe
--- /dev/null
+++ b/test/Transforms/DebugIR/struct.ll
@@ -0,0 +1,24 @@
+; ModuleID = 'struct.cpp'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnu"
+
+%struct.blah = type { i32, float, i8 }
+
+; Function Attrs: nounwind uwtable
+define i32 @main() #0 {
+  %1 = alloca i32, align 4                                    ; CHECK: !dbg
+  %b = alloca %struct.blah, align 4                           ; CHECK-NEXT: !dbg
+  store i32 0, i32* %1                                        ; CHECK-NEXT: !dbg
+  %2 = getelementptr inbounds %struct.blah* %b, i32 0, i32 0  ; CHECK-NEXT: !dbg
+  %3 = load i32* %2, align 4                                  ; CHECK-NEXT: !dbg
+  ret i32 %3                                                  ; CHECK-NEXT: !dbg
+}
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+; CHECK: = metadata !{i32 11,
+; CHECK-NEXT: = metadata !{i32 12,
+; CHECK-NEXT: = metadata !{i32 13,
+; CHECK-NEXT: = metadata !{i32 14,
+
+; RUN: opt %s -debug-ir -S | FileCheck %s
diff --git a/test/Transforms/DebugIR/vector.ll b/test/Transforms/DebugIR/vector.ll
new file mode 100644
index 0000000..50d99ac
--- /dev/null
+++ b/test/Transforms/DebugIR/vector.ll
@@ -0,0 +1,93 @@
+; ModuleID = 'vector.cpp'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-pc-linux-gnu"
+
+; Function Attrs: noinline nounwind uwtable
+define <4 x float> @_Z3fooDv2_fS_(double %a.coerce, double %b.coerce) #0 {
+  %1 = alloca <2 x float>, align 8                    ; CHECK: !dbg
+  %2 = alloca <2 x float>, align 8                    ; CHECK-NEXT: !dbg
+  %3 = alloca <2 x float>, align 8                    ; CHECK-NEXT: !dbg
+  %4 = alloca <2 x float>, align 8                    ; CHECK-NEXT: !dbg
+  %c = alloca <4 x float>, align 16                   ; CHECK-NEXT: !dbg
+  %5 = bitcast <2 x float>* %1 to double*             ; CHECK-NEXT: !dbg
+  store double %a.coerce, double* %5, align 1         ; CHECK-NEXT: !dbg
+  %a = load <2 x float>* %1, align 8                  ; CHECK-NEXT: !dbg
+  store <2 x float> %a, <2 x float>* %2, align 8      ; CHECK-NEXT: !dbg
+  %6 = bitcast <2 x float>* %3 to double*             ; CHECK-NEXT: !dbg
+  store double %b.coerce, double* %6, align 1         ; CHECK-NEXT: !dbg
+  %b = load <2 x float>* %3, align 8                  ; CHECK-NEXT: !dbg
+  store <2 x float> %b, <2 x float>* %4, align 8      ; CHECK-NEXT: !dbg
+  %7 = load <2 x float>* %2, align 8                  ; CHECK-NEXT: !dbg
+  %8 = load <4 x float>* %c, align 16                 ; CHECK-NEXT: !dbg
+  %9 = shufflevector <2 x float> %7, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>   ; CHECK-NEXT: !dbg
+  %10 = shufflevector <4 x float> %8, <4 x float> %9, <4 x i32> <i32 4, i32 1, i32 5, i32 3>             ; CHECK-NEXT: !dbg
+  store <4 x float> %10, <4 x float>* %c, align 16    ; CHECK-NEXT: !dbg
+  %11 = load <2 x float>* %4, align 8                 ; CHECK-NEXT: !dbg
+  %12 = load <4 x float>* %c, align 16                ; CHECK-NEXT: !dbg
+  %13 = shufflevector <2 x float> %11, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ; CHECK-NEXT: !dbg
+  %14 = shufflevector <4 x float> %12, <4 x float> %13, <4 x i32> <i32 0, i32 4, i32 2, i32 5>           ; CHECK-NEXT: !dbg
+  store <4 x float> %14, <4 x float>* %c, align 16    ; CHECK-NEXT: !dbg
+  %15 = load <4 x float>* %c, align 16                ; CHECK-NEXT: !dbg
+  ret <4 x float> %15                                 ; CHECK-NEXT: !dbg
+}
+
+; Function Attrs: nounwind uwtable
+define i32 @main() #1 {
+  %1 = alloca i32, align 4                            ; CHECK: !dbg
+  %a = alloca <2 x float>, align 8                    ; CHECK-NEXT: !dbg
+  %b = alloca <2 x float>, align 8                    ; CHECK-NEXT: !dbg
+  %x = alloca <4 x float>, align 16                   ; CHECK-NEXT: !dbg
+  %2 = alloca <2 x float>, align 8                    ; CHECK-NEXT: !dbg
+  %3 = alloca <2 x float>, align 8                    ; CHECK-NEXT: !dbg
+  store i32 0, i32* %1                                ; CHECK-NEXT: !dbg
+  store <2 x float> <float 1.000000e+00, float 2.000000e+00>, <2 x float>* %a, align 8                   ; CHECK-NEXT: !dbg
+  store <2 x float> <float 1.000000e+00, float 2.000000e+00>, <2 x float>* %b, align 8                   ; CHECK-NEXT: !dbg
+  %4 = load <2 x float>* %a, align 8                  ; CHECK-NEXT: !dbg
+  %5 = load <2 x float>* %b, align 8                  ; CHECK-NEXT: !dbg
+  store <2 x float> %4, <2 x float>* %2, align 8      ; CHECK-NEXT: !dbg
+  %6 = bitcast <2 x float>* %2 to double*             ; CHECK-NEXT: !dbg
+  %7 = load double* %6, align 1                       ; CHECK-NEXT: !dbg
+  store <2 x float> %5, <2 x float>* %3, align 8      ; CHECK-NEXT: !dbg
+  %8 = bitcast <2 x float>* %3 to double*             ; CHECK-NEXT: !dbg
+  %9 = load double* %8, align 1                       ; CHECK-NEXT: !dbg
+  %10 = call <4 x float> @_Z3fooDv2_fS_(double %7, double %9)                                            ; CHECK-NEXT: !dbg
+  store <4 x float> %10, <4 x float>* %x, align 16    ; CHECK-NEXT: !dbg
+  %11 = load <4 x float>* %x, align 16                ; CHECK-NEXT: !dbg
+  %12 = extractelement <4 x float> %11, i32 0         ; CHECK-NEXT: !dbg
+  %13 = load <4 x float>* %x, align 16                ; CHECK-NEXT: !dbg
+  %14 = extractelement <4 x float> %13, i32 1         ; CHECK-NEXT: !dbg
+  %15 = fadd float %12, %14                           ; CHECK-NEXT: !dbg
+  %16 = load <4 x float>* %x, align 16                ; CHECK-NEXT: !dbg
+  %17 = extractelement <4 x float> %16, i32 2         ; CHECK-NEXT: !dbg
+  %18 = fadd float %15, %17                           ; CHECK-NEXT: !dbg
+  %19 = load <4 x float>* %x, align 16                ; CHECK-NEXT: !dbg
+  %20 = extractelement <4 x float> %19, i32 3         ; CHECK-NEXT: !dbg
+  %21 = fadd float %18, %20                           ; CHECK-NEXT: !dbg
+  %22 = fptosi float %21 to i32                       ; CHECK-NEXT: !dbg
+  ret i32 %22                                         ; CHECK-NEXT: !dbg
+}
+
+attributes #0 = { noinline nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+; CHECK: = metadata !{i32 13,
+; CHECK-NEXT: = metadata !{i32 14,
+; CHECK-NEXT: = metadata !{i32 15,
+; CHECK-NEXT: = metadata !{i32 16,
+; CHECK-NEXT: = metadata !{i32 17,
+; CHECK-NEXT: = metadata !{i32 18,
+; CHECK-NEXT: = metadata !{i32 19,
+; CHECK-NEXT: = metadata !{i32 20,
+; CHECK-NEXT: = metadata !{i32 21,
+; CHECK-NEXT: = metadata !{i32 22,
+; CHECK-NEXT: = metadata !{i32 23,
+; CHECK-NEXT: = metadata !{i32 24,
+; CHECK-NEXT: = metadata !{i32 25,
+; CHECK-NEXT: = metadata !{i32 26,
+; CHECK-NEXT: = metadata !{i32 27,
+; CHECK-NEXT: = metadata !{i32 28,
+; CHECK-NEXT: = metadata !{i32 29,
+; CHECK-NEXT: = metadata !{i32 30,
+; CHECK-NEXT: = metadata !{i32 31,
+
+; RUN: opt %s -debug-ir -S | FileCheck %s
diff --git a/test/Transforms/EarlyCSE/basic.ll b/test/Transforms/EarlyCSE/basic.ll
index 32c302c..80704df 100644
--- a/test/Transforms/EarlyCSE/basic.ll
+++ b/test/Transforms/EarlyCSE/basic.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -S -early-cse | FileCheck %s
 
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 define void @test1(i8 %V, i32 *%P) {
   %A = bitcast i64 42 to double  ;; dead
   %B = add i32 4, 19             ;; constant folds
@@ -33,7 +33,7 @@ define void @test1(i8 %V, i32 *%P) {
 
 
 ;; Simple load value numbering.
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 define i32 @test2(i32 *%P) {
   %V1 = load i32* %P
   %V2 = load i32* %P
@@ -43,7 +43,7 @@ define i32 @test2(i32 *%P) {
 }
 
 ;; Cross block load value numbering.
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 define i32 @test3(i32 *%P, i1 %Cond) {
   %V1 = load i32* %P
   br i1 %Cond, label %T, label %F
@@ -59,7 +59,7 @@ F:
 }
 
 ;; Cross block load value numbering stops when stores happen.
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 define i32 @test4(i32 *%P, i1 %Cond) {
   %V1 = load i32* %P
   br i1 %Cond, label %T, label %F
@@ -79,7 +79,7 @@ F:
 declare i32 @func(i32 *%P) readonly
 
 ;; Simple call CSE'ing.
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 define i32 @test5(i32 *%P) {
   %V1 = call i32 @func(i32* %P)
   %V2 = call i32 @func(i32* %P)
@@ -89,7 +89,7 @@ define i32 @test5(i32 *%P) {
 }
 
 ;; Trivial Store->load forwarding
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 define i32 @test6(i32 *%P) {
   store i32 42, i32* %P
   %V1 = load i32* %P
@@ -98,7 +98,7 @@ define i32 @test6(i32 *%P) {
 }
 
 ;; Trivial dead store elimination.
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 define void @test7(i32 *%P) {
   store i32 42, i32* %P
   store i32 45, i32* %P
@@ -108,7 +108,7 @@ define void @test7(i32 *%P) {
 }
 
 ;; Readnone functions aren't invalidated by stores.
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 define i32 @test8(i32 *%P) {
   %V1 = call i32 @func(i32* %P) readnone
   store i32 4, i32* %P
diff --git a/test/Transforms/EarlyCSE/commute.ll b/test/Transforms/EarlyCSE/commute.ll
index 8cf04d1..985fe04 100644
--- a/test/Transforms/EarlyCSE/commute.ll
+++ b/test/Transforms/EarlyCSE/commute.ll
@@ -1,6 +1,6 @@
 ; RUN: opt < %s -S -early-cse | FileCheck %s
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 define void @test1(float %A, float %B, float* %PA, float* %PB) {
   ; CHECK-NEXT: fadd
   ; CHECK-NEXT: store
@@ -13,7 +13,7 @@ define void @test1(float %A, float %B, float* %PA, float* %PB) {
   ret void
 }
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 define void @test2(float %A, float %B, i1* %PA, i1* %PB) {
   ; CHECK-NEXT: fcmp
   ; CHECK-NEXT: store
@@ -26,7 +26,7 @@ define void @test2(float %A, float %B, i1* %PA, i1* %PB) {
   ret void
 }
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 define void @test3(float %A, float %B, i1* %PA, i1* %PB) {
   ; CHECK-NEXT: fcmp
   ; CHECK-NEXT: store
@@ -39,7 +39,7 @@ define void @test3(float %A, float %B, i1* %PA, i1* %PB) {
   ret void
 }
 
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 define void @test4(i32 %A, i32 %B, i1* %PA, i1* %PB) {
   ; CHECK-NEXT: icmp
   ; CHECK-NEXT: store
@@ -52,7 +52,7 @@ define void @test4(i32 %A, i32 %B, i1* %PA, i1* %PB) {
   ret void
 }
 
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 define void @test5(i32 %A, i32 %B, i1* %PA, i1* %PB) {
   ; CHECK-NEXT: icmp
   ; CHECK-NEXT: store
diff --git a/test/Transforms/EarlyCSE/instsimplify-dom.ll b/test/Transforms/EarlyCSE/instsimplify-dom.ll
index 36dffec..ebdd7f9 100644
--- a/test/Transforms/EarlyCSE/instsimplify-dom.ll
+++ b/test/Transforms/EarlyCSE/instsimplify-dom.ll
@@ -16,4 +16,4 @@ xxx:
   br label %lbl_1215
 }
 
-; CHECK: define i32 @fn
+; CHECK-LABEL: define i32 @fn(
diff --git a/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll b/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll
index f38c03ac..0cf1cb7 100644
--- a/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll
+++ b/test/Transforms/FunctionAttrs/2009-01-02-LocalStores.ll
@@ -1,14 +1,23 @@
-; RUN: opt < %s -functionattrs -S | not grep "nocapture *%%q"
-; RUN: opt < %s -functionattrs -S | grep "nocapture *%%p"
+; RUN: opt < %s -functionattrs -S | FileCheck %s
 
+; CHECK: define i32* @a(i32** nocapture readonly %p)
 define i32* @a(i32** %p) {
 	%tmp = load i32** %p
 	ret i32* %tmp
 }
 
+; CHECK: define i32* @b(i32* %q)
 define i32* @b(i32 *%q) {
 	%mem = alloca i32*
 	store i32* %q, i32** %mem
 	%tmp = call i32* @a(i32** %mem)
 	ret i32* %tmp
 }
+
+; CHECK: define i32* @c(i32* readnone %r)
+@g = global i32 0
+define i32* @c(i32 *%r) {
+	%a = icmp eq i32* %r, null
+	store i32 1, i32* @g
+	ret i32* %r
+}
diff --git a/test/Transforms/FunctionAttrs/2009-01-04-Annotate.ll b/test/Transforms/FunctionAttrs/2009-01-04-Annotate.ll
index d414b73..fa06cc7 100644
--- a/test/Transforms/FunctionAttrs/2009-01-04-Annotate.ll
+++ b/test/Transforms/FunctionAttrs/2009-01-04-Annotate.ll
@@ -1,6 +1,6 @@
 ; RUN: opt < %s -functionattrs -S | FileCheck %s
 
-; CHECK: declare noalias i8* @fopen(i8* nocapture, i8* nocapture) #0
+; CHECK: declare noalias i8* @fopen(i8* nocapture readonly, i8* nocapture readonly) #0
 declare i8* @fopen(i8*, i8*)
 
 ; CHECK: declare i8 @strlen(i8* nocapture) #1
diff --git a/test/Transforms/FunctionAttrs/annotate-1.ll b/test/Transforms/FunctionAttrs/annotate-1.ll
index ae77380..adb7bce 100644
--- a/test/Transforms/FunctionAttrs/annotate-1.ll
+++ b/test/Transforms/FunctionAttrs/annotate-1.ll
@@ -1,7 +1,8 @@
 ; RUN: opt < %s -functionattrs -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -functionattrs -S | FileCheck -check-prefix=POSIX %s
 
 declare i8* @fopen(i8*, i8*)
-; CHECK: declare noalias i8* @fopen(i8* nocapture, i8* nocapture) [[G0:#[0-9]]] 
+; CHECK: declare noalias i8* @fopen(i8* nocapture readonly, i8* nocapture readonly) [[G0:#[0-9]]] 
 
 declare i8 @strlen(i8*)
 ; CHECK: declare i8 @strlen(i8* nocapture) [[G1:#[0-9]]]
@@ -14,5 +15,9 @@ declare i32* @realloc(i32*, i32)
 declare i32 @strcpy(...)
 ; CHECK: declare i32 @strcpy(...)
 
+declare i32 @gettimeofday(i8*, i8*)
+; CHECK-POSIX: declare i32 @gettimeofday(i8* nocapture, i8* nocapture) [[G0:#[0-9]+]]
+
 ; CHECK: attributes [[G0]] = { nounwind }
 ; CHECK: attributes [[G1]] = { nounwind readonly }
+; CHECK-POSIX: attributes [[G0]] = { nounwind }
diff --git a/test/Transforms/FunctionAttrs/atomic.ll b/test/Transforms/FunctionAttrs/atomic.ll
index 027ee0f..d5a8db7 100644
--- a/test/Transforms/FunctionAttrs/atomic.ll
+++ b/test/Transforms/FunctionAttrs/atomic.ll
@@ -13,7 +13,7 @@ entry:
 
 ; A function with an Acquire load is not readonly.
 define i32 @test2(i32* %x) uwtable ssp {
-; CHECK: define i32 @test2(i32* nocapture %x) #1 {
+; CHECK: define i32 @test2(i32* nocapture readonly %x) #1 {
 entry:
   %r = load atomic i32* %x seq_cst, align 4
   ret i32 %r
diff --git a/test/Transforms/FunctionAttrs/nocapture.ll b/test/Transforms/FunctionAttrs/nocapture.ll
index 3027acd..110bd03 100644
--- a/test/Transforms/FunctionAttrs/nocapture.ll
+++ b/test/Transforms/FunctionAttrs/nocapture.ll
@@ -1,12 +1,13 @@
 ; RUN: opt < %s -functionattrs -S | FileCheck %s
 @g = global i32* null		; <i32**> [#uses=1]
 
-; CHECK: define i32* @c1(i32* %q)
+; CHECK: define i32* @c1(i32* readnone %q)
 define i32* @c1(i32* %q) {
 	ret i32* %q
 }
 
 ; CHECK: define void @c2(i32* %q)
+; It would also be acceptable to mark %q as readnone. Update @c3 too.
 define void @c2(i32* %q) {
 	store i32* %q, i32** @g
 	ret void
@@ -45,7 +46,7 @@ define i1 @c5(i32* %q, i32 %bitno) {
 
 declare void @throw_if_bit_set(i8*, i8) readonly
 
-; CHECK: define i1 @c6(i8* %q, i8 %bit)
+; CHECK: define i1 @c6(i8* readonly %q, i8 %bit)
 define i1 @c6(i8* %q, i8 %bit) {
 	invoke void @throw_if_bit_set(i8* %q, i8 %bit)
 		to label %ret0 unwind label %ret1
@@ -67,7 +68,7 @@ define i1* @lookup_bit(i32* %q, i32 %bitno) readnone nounwind {
 	ret i1* %lookup
 }
 
-; CHECK: define i1 @c7(i32* %q, i32 %bitno)
+; CHECK: define i1 @c7(i32* readnone %q, i32 %bitno)
 define i1 @c7(i32* %q, i32 %bitno) {
 	%ptr = call i1* @lookup_bit(i32* %q, i32 %bitno)
 	%val = load i1* %ptr
@@ -103,7 +104,7 @@ define void @nc3(void ()* %p) {
 }
 
 declare void @external(i8*) readonly nounwind
-; CHECK: define void @nc4(i8* nocapture %p)
+; CHECK: define void @nc4(i8* nocapture readonly %p)
 define void @nc4(i8* %p) {
 	call void @external(i8* %p)
 	ret void
@@ -116,28 +117,29 @@ define void @nc5(void (i8*)* %f, i8* %p) {
 	ret void
 }
 
-; CHECK: define void @test1_1(i8* nocapture %x1_1, i8* %y1_1)
+; CHECK: define void @test1_1(i8* nocapture readnone %x1_1, i8* %y1_1)
+; It would be acceptable to add readnone to %y1_1 and %y1_2.
 define void @test1_1(i8* %x1_1, i8* %y1_1) {
   call i8* @test1_2(i8* %x1_1, i8* %y1_1)
   store i32* null, i32** @g
   ret void
 }
 
-; CHECK: define i8* @test1_2(i8* nocapture %x1_2, i8* %y1_2)
+; CHECK: define i8* @test1_2(i8* nocapture readnone %x1_2, i8* %y1_2)
 define i8* @test1_2(i8* %x1_2, i8* %y1_2) {
   call void @test1_1(i8* %x1_2, i8* %y1_2)
   store i32* null, i32** @g
   ret i8* %y1_2
 }
 
-; CHECK: define void @test2(i8* nocapture %x2)
+; CHECK: define void @test2(i8* nocapture readnone %x2)
 define void @test2(i8* %x2) {
   call void @test2(i8* %x2)
   store i32* null, i32** @g
   ret void
 }
 
-; CHECK: define void @test3(i8* nocapture %x3, i8* nocapture %y3, i8* nocapture %z3)
+; CHECK: define void @test3(i8* nocapture readnone %x3, i8* nocapture readnone %y3, i8* nocapture readnone %z3)
 define void @test3(i8* %x3, i8* %y3, i8* %z3) {
   call void @test3(i8* %z3, i8* %y3, i8* %x3)
   store i32* null, i32** @g
@@ -151,7 +153,7 @@ define void @test4_1(i8* %x4_1) {
   ret void
 }
 
-; CHECK: define i8* @test4_2(i8* nocapture %x4_2, i8* %y4_2, i8* nocapture %z4_2)
+; CHECK: define i8* @test4_2(i8* nocapture readnone %x4_2, i8* readnone %y4_2, i8* nocapture readnone %z4_2)
 define i8* @test4_2(i8* %x4_2, i8* %y4_2, i8* %z4_2) {
   call void @test4_1(i8* null)
   store i32* null, i32** @g
diff --git a/test/Transforms/FunctionAttrs/noreturn.ll b/test/Transforms/FunctionAttrs/noreturn.ll
index 470ebcb..990bea9 100644
--- a/test/Transforms/FunctionAttrs/noreturn.ll
+++ b/test/Transforms/FunctionAttrs/noreturn.ll
@@ -7,7 +7,7 @@ entry:
 while.body:
   br label %while.body
 }
-;CHECK: @main
+;CHECK-LABEL: @main(
 ;CHECK: endless_loop
 ;CHECK: ret
 define i32 @main() noreturn nounwind ssp uwtable {
diff --git a/test/Transforms/FunctionAttrs/readattrs.ll b/test/Transforms/FunctionAttrs/readattrs.ll
new file mode 100644
index 0000000..0842f56
--- /dev/null
+++ b/test/Transforms/FunctionAttrs/readattrs.ll
@@ -0,0 +1,47 @@
+; RUN: opt < %s -functionattrs -S | FileCheck %s
+@x = global i32 0
+
+declare void @test1_1(i8* %x1_1, i8* readonly %y1_1, ...)
+
+; CHECK: define void @test1_2(i8* %x1_2, i8* readonly %y1_2, i8* %z1_2)
+define void @test1_2(i8* %x1_2, i8* %y1_2, i8* %z1_2) {
+  call void (i8*, i8*, ...)* @test1_1(i8* %x1_2, i8* %y1_2, i8* %z1_2)
+  store i32 0, i32* @x
+  ret void
+}
+
+; CHECK: define i8* @test2(i8* readnone %p)
+define i8* @test2(i8* %p) {
+  store i32 0, i32* @x
+  ret i8* %p
+}
+
+; CHECK: define i1 @test3(i8* readnone %p, i8* readnone %q)
+define i1 @test3(i8* %p, i8* %q) {
+  %A = icmp ult i8* %p, %q
+  ret i1 %A
+}
+
+declare void @test4_1(i8* nocapture) readonly
+
+; CHECK: define void @test4_2(i8* nocapture readonly %p)
+define void @test4_2(i8* %p) {
+  call void @test4_1(i8* %p)
+  ret void
+}
+
+; CHECK: define void @test5(i8** nocapture %p, i8* %q)
+; Missed optz'n: we could make %q readnone, but don't break test6!
+define void @test5(i8** %p, i8* %q) {
+  store i8* %q, i8** %p
+  ret void
+}
+
+declare void @test6_1()
+; CHECK: define void @test6_2(i8** nocapture %p, i8* %q)
+; This is not a missed optz'n.
+define void @test6_2(i8** %p, i8* %q) {
+  store i8* %q, i8** %p
+  call void @test6_1()
+  ret void
+}
diff --git a/test/Transforms/GCOVProfiling/linkagename.ll b/test/Transforms/GCOVProfiling/linkagename.ll
index 7ce4d86..9453e1e 100644
--- a/test/Transforms/GCOVProfiling/linkagename.ll
+++ b/test/Transforms/GCOVProfiling/linkagename.ll
@@ -14,7 +14,7 @@ entry:
 !llvm.dbg.cu = !{!0}
 !llvm.gcov = !{!9}
 
-!0 = metadata !{i32 786449, i32 4, metadata !1, metadata !"clang version 3.3 (trunk 177323)", i1 false, metadata !"", i32 0, metadata !3, metadata !3, metadata !4, metadata !3,  metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/home/nlewycky/hello.cc] [DW_LANG_C_plus_plus]
+!0 = metadata !{i32 786449, metadata !2, i32 4, metadata !"clang version 3.3 (trunk 177323)", i1 false, metadata !"", i32 0, metadata !3, metadata !3, metadata !4, metadata !3,  metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/home/nlewycky/hello.cc] [DW_LANG_C_plus_plus]
 !1 = metadata !{i32 786473, metadata !2}          ; [ DW_TAG_file_type ] [/home/nlewycky/hello.cc]
 !2 = metadata !{metadata !"hello.cc", metadata !"/home/nlewycky"}
 !3 = metadata !{i32 0}
diff --git a/test/Transforms/GCOVProfiling/version.ll b/test/Transforms/GCOVProfiling/version.ll
index d6d0f33..a90290f 100644
--- a/test/Transforms/GCOVProfiling/version.ll
+++ b/test/Transforms/GCOVProfiling/version.ll
@@ -17,13 +17,14 @@ define void @test() {
 !llvm.gcov = !{!9}
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{metadata !"./version", metadata !1}
-!1 = metadata !{i32 786449, i32 0, i32 4, metadata !2, metadata !"clang version 3.3 (trunk 176994)", i1 false, metadata !"", i32 0, metadata !3, metadata !3, metadata !4, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [./version] [DW_LANG_C_plus_plus]
-!2 = metadata !{i32 786473, metadata !"version", metadata !"/usr/local/google/home/nlewycky"} ; [ DW_TAG_file_type ]
+!0 = metadata !{i32 786449, metadata !11, i32 4, metadata !"clang version 3.3 (trunk 176994)", i1 false, metadata !"", i32 0, metadata !3, metadata !3, metadata !4, metadata !3, null, metadata !""} ; [ DW_TAG_compile_unit ] [./version] [DW_LANG_C_plus_plus]
+!2 = metadata !{i32 786473, metadata !11} ; [ DW_TAG_file_type ]
 !3 = metadata !{i32 0}
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786478, i32 0, metadata !6, metadata !"test", metadata !"test", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @test, null, null, metadata !3, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [test]
-!6 = metadata !{i32 786473, metadata !"<stdin>", metadata !"."} ; [ DW_TAG_file_type ]
+!5 = metadata !{i32 786478, metadata !10, metadata !6, metadata !"test", metadata !"test", metadata !"", i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @test, null, null, metadata !3, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [test]
+!6 = metadata !{i32 786473, metadata !10} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !3, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !8 = metadata !{i32 1, i32 0, metadata !5, null}
 ;; !9 is added through the echo line at the top.
+!10 = metadata !{metadata !"<stdin>", metadata !"."}
+!11 = metadata !{metadata !"version", metadata !"/usr/local/google/home/nlewycky"}
diff --git a/test/Transforms/GVN/2010-11-13-Simplify.ll b/test/Transforms/GVN/2010-11-13-Simplify.ll
index 07585a2..9d0becc 100644
--- a/test/Transforms/GVN/2010-11-13-Simplify.ll
+++ b/test/Transforms/GVN/2010-11-13-Simplify.ll
@@ -3,7 +3,7 @@
 declare i32 @foo(i32) readnone
 
 define i1 @bar() {
-; CHECK: @bar
+; CHECK-LABEL: @bar(
   %a = call i32 @foo (i32 0) readnone
   %b = call i32 @foo (i32 0) readnone
   %c = and i32 %a, %b
diff --git a/test/Transforms/GVN/2011-06-01-NonLocalMemdepMiscompile.ll b/test/Transforms/GVN/2011-06-01-NonLocalMemdepMiscompile.ll
index f24e956..4613bc4 100644
--- a/test/Transforms/GVN/2011-06-01-NonLocalMemdepMiscompile.ll
+++ b/test/Transforms/GVN/2011-06-01-NonLocalMemdepMiscompile.ll
@@ -7,7 +7,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-apple-macosx10.7.0"
 
 define i1 @rb_intern() nounwind ssp {
-; CHECK: @rb_intern
+; CHECK-LABEL: @rb_intern(
 
 bb:
   %tmp = alloca i8*, align 8
diff --git a/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll b/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll
index 18178e4..ce60ffe 100644
--- a/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll
+++ b/test/Transforms/GVN/2011-07-07-MatchIntrinsicExtract.ll
@@ -11,7 +11,7 @@ entry:
   ret i64 %add1
 }
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NOT: add1
 ; CHECK: ret
 
@@ -23,7 +23,7 @@ entry:
   ret i64 %sub1
 }
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NOT: sub1
 ; CHECK: ret
 
@@ -35,7 +35,7 @@ entry:
   ret i64 %mul1
 }
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NOT: mul1
 ; CHECK: ret
 
@@ -47,7 +47,7 @@ entry:
   ret i64 %add1
 }
 
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NOT: add1
 ; CHECK: ret
 
@@ -59,7 +59,7 @@ entry:
   ret i64 %sub1
 }
 
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NOT: sub1
 ; CHECK: ret
 
@@ -71,7 +71,7 @@ entry:
   ret i64 %mul1
 }
 
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NOT: mul1
 ; CHECK: ret
 
diff --git a/test/Transforms/GVN/commute.ll b/test/Transforms/GVN/commute.ll
index cf4fb7f..cdd6ecf 100644
--- a/test/Transforms/GVN/commute.ll
+++ b/test/Transforms/GVN/commute.ll
@@ -3,7 +3,7 @@
 declare void @use(i32, i32)
 
 define void @foo(i32 %x, i32 %y) {
-  ; CHECK: @foo
+  ; CHECK-LABEL: @foo(
   %add1 = add i32 %x, %y
   %add2 = add i32 %y, %x
   call void @use(i32 %add1, i32 %add2)
@@ -14,7 +14,7 @@ define void @foo(i32 %x, i32 %y) {
 declare void @vse(i1, i1)
 
 define void @bar(i32 %x, i32 %y) {
-  ; CHECK: @bar
+  ; CHECK-LABEL: @bar(
   %cmp1 = icmp ult i32 %x, %y
   %cmp2 = icmp ugt i32 %y, %x
   call void @vse(i1 %cmp1, i1 %cmp2)
diff --git a/test/Transforms/GVN/condprop.ll b/test/Transforms/GVN/condprop.ll
index 9c28955..708e4b2 100644
--- a/test/Transforms/GVN/condprop.ll
+++ b/test/Transforms/GVN/condprop.ll
@@ -2,7 +2,7 @@
 
 @a = external global i32		; <i32*> [#uses=7]
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 define i32 @test1() nounwind {
 entry:
 	%0 = load i32* @a, align 4
@@ -57,7 +57,7 @@ return:		; preds = %bb8
 declare void @foo(i1)
 declare void @bar(i32)
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 define void @test3(i32 %x, i32 %y) {
   %xz = icmp eq i32 %x, 0
   %yz = icmp eq i32 %y, 0
@@ -79,7 +79,7 @@ nope:
   ret void
 }
 
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 define void @test4(i1 %b, i32 %x) {
   br i1 %b, label %sw, label %case3
 sw:
@@ -112,7 +112,7 @@ case3:
   ret void
 }
 
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 define i1 @test5(i32 %x, i32 %y) {
   %cmp = icmp eq i32 %x, %y
   br i1 %cmp, label %same, label %different
@@ -128,7 +128,7 @@ different:
   ret i1 %cmp3
 }
 
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 define i1 @test6(i32 %x, i32 %y) {
   %cmp2 = icmp ne i32 %x, %y
   %cmp = icmp eq i32 %x, %y
@@ -144,7 +144,7 @@ different:
   ret i1 %cmp3
 }
 
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 define i1 @test7(i32 %x, i32 %y) {
   %cmp = icmp sgt i32 %x, %y
   br i1 %cmp, label %same, label %different
@@ -160,7 +160,7 @@ different:
   ret i1 %cmp3
 }
 
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 define i1 @test8(i32 %x, i32 %y) {
   %cmp2 = icmp sle i32 %x, %y
   %cmp = icmp sgt i32 %x, %y
@@ -177,7 +177,7 @@ different:
 }
 
 ; PR1768
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 define i32 @test9(i32 %i, i32 %j) {
   %cmp = icmp eq i32 %i, %j
   br i1 %cmp, label %cond_true, label %ret
@@ -193,7 +193,7 @@ ret:
 }
 
 ; PR1768
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 define i32 @test10(i32 %j, i32 %i) {
   %cmp = icmp eq i32 %i, %j
   br i1 %cmp, label %cond_true, label %ret
@@ -210,7 +210,7 @@ ret:
 
 declare i32 @yogibar()
 
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 define i32 @test11(i32 %x) {
   %v0 = call i32 @yogibar()
   %v1 = call i32 @yogibar()
@@ -233,7 +233,7 @@ next2:
   ret i32 0
 }
 
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 define i32 @test12(i32 %x) {
   %cmp = icmp eq i32 %x, 0
   br i1 %cmp, label %cond_true, label %cond_false
diff --git a/test/Transforms/GVN/edge.ll b/test/Transforms/GVN/edge.ll
index 3a102b6..646e10c 100644
--- a/test/Transforms/GVN/edge.ll
+++ b/test/Transforms/GVN/edge.ll
@@ -1,7 +1,7 @@
 ; RUN: opt -gvn -S < %s | FileCheck %s
 
 define i32 @f1(i32 %x) {
-  ; CHECK: define i32 @f1(
+  ; CHECK-LABEL: define i32 @f1(
 bb0:
   %cmp = icmp eq i32 %x, 0
   br i1 %cmp, label %bb2, label %bb1
@@ -16,7 +16,7 @@ bb2:
 }
 
 define i32 @f2(i32 %x) {
-  ; CHECK: define i32 @f2(
+  ; CHECK-LABEL: define i32 @f2(
 bb0:
   %cmp = icmp ne i32 %x, 0
   br i1 %cmp, label %bb1, label %bb2
@@ -31,7 +31,7 @@ bb2:
 }
 
 define i32 @f3(i32 %x) {
-  ; CHECK: define i32 @f3(
+  ; CHECK-LABEL: define i32 @f3(
 bb0:
   switch i32 %x, label %bb1 [ i32 0, label %bb2]
 bb1:
@@ -46,7 +46,7 @@ bb2:
 
 declare void @g(i1)
 define void @f4(i8 * %x)  {
-; CHECK: define void @f4(
+; CHECK-LABEL: define void @f4(
 bb0:
   %y = icmp eq i8* null, %x
   br i1 %y, label %bb2, label %bb1
diff --git a/test/Transforms/GVN/load-pre-align.ll b/test/Transforms/GVN/load-pre-align.ll
index d8ad59f..4816af2 100644
--- a/test/Transforms/GVN/load-pre-align.ll
+++ b/test/Transforms/GVN/load-pre-align.ll
@@ -5,7 +5,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-
 @p = external global i32
 
 define i32 @test(i32 %n) nounwind {
-; CHECK: @test
+; CHECK-LABEL: @test(
 entry:
   br label %for.cond
 
diff --git a/test/Transforms/GVN/malloc-load-removal.ll b/test/Transforms/GVN/malloc-load-removal.ll
index 66b6929..e93a62a 100644
--- a/test/Transforms/GVN/malloc-load-removal.ll
+++ b/test/Transforms/GVN/malloc-load-removal.ll
@@ -21,11 +21,11 @@ if.then:                                          ; preds = %entry
 if.end:                                           ; preds = %if.then, %entry
   ret i8* %call
 
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK-NOT: load
 ; CHECK-NOT: icmp
 
-; CHECK_NO_LIBCALLS: @test
+; CHECK_NO_LIBCALLS-LABEL: @test(
 ; CHECK_NO_LIBCALLS: load
 ; CHECK_NO_LIBCALLS: icmp
 }
diff --git a/test/Transforms/GVN/non-local-offset.ll b/test/Transforms/GVN/non-local-offset.ll
index 8eaa999..0b9edcb 100644
--- a/test/Transforms/GVN/non-local-offset.ll
+++ b/test/Transforms/GVN/non-local-offset.ll
@@ -5,7 +5,7 @@ target datalayout = "e-p:64:64:64"
 ; GVN should ignore the store to p[1] to see that the load from p[0] is
 ; fully redundant.
 
-; CHECK: @yes
+; CHECK-LABEL: @yes(
 ; CHECK: if.then:
 ; CHECK-NEXT: store i32 0, i32* %q
 ; CHECK-NEXT: ret void
@@ -30,7 +30,7 @@ if.else:
 ; fully redundant. However, the second load is larger, so it's not a simple
 ; redundancy.
 
-; CHECK: @watch_out_for_size_change
+; CHECK-LABEL: @watch_out_for_size_change(
 ; CHECK: if.then:
 ; CHECK-NEXT: store i32 0, i32* %q
 ; CHECK-NEXT: ret void
diff --git a/test/Transforms/GVN/phi-translate.ll b/test/Transforms/GVN/phi-translate.ll
index fa91d29..50d6178 100644
--- a/test/Transforms/GVN/phi-translate.ll
+++ b/test/Transforms/GVN/phi-translate.ll
@@ -2,7 +2,7 @@
 
 target datalayout = "e-p:64:64:64"
 
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK: entry.end_crit_edge:
 ; CHECK:   %n.pre = load i32* %q.phi.trans.insert
 ; CHECK: then:
diff --git a/test/Transforms/GVN/pr14166.ll b/test/Transforms/GVN/pr14166.ll
index 9f47e46..4d68205 100644
--- a/test/Transforms/GVN/pr14166.ll
+++ b/test/Transforms/GVN/pr14166.ll
@@ -10,7 +10,7 @@ define <2 x i32> @test1() {
   store <2 x i8*> %v3, <2 x i8*>* %v4
   %v5 = load <2 x i32>* %v1
   ret <2 x i32> %v5
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %v1 = alloca <2 x i32>
 ; CHECK: call void @anything(<2 x i32>* %v1)
 ; CHECK: %v2 = load <2 x i32>* %v1
diff --git a/test/Transforms/GVN/pre-load.ll b/test/Transforms/GVN/pre-load.ll
index bf4add4..9842886 100644
--- a/test/Transforms/GVN/pre-load.ll
+++ b/test/Transforms/GVN/pre-load.ll
@@ -2,7 +2,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 
 define i32 @test1(i32* %p, i1 %C) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 block1:
 	br i1 %C, label %block2, label %block3
 
@@ -25,7 +25,7 @@ block4:
 
 ; This is a simple phi translation case.
 define i32 @test2(i32* %p, i32* %q, i1 %C) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 block1:
 	br i1 %C, label %block2, label %block3
 
@@ -50,7 +50,7 @@ block4:
 
 ; This is a PRE case that requires phi translation through a GEP.
 define i32 @test3(i32* %p, i32* %q, i32** %Hack, i1 %C) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 block1:
   %B = getelementptr i32* %q, i32 1
   store i32* %B, i32** %Hack
@@ -80,7 +80,7 @@ block4:
 ;; Here the loaded address is available, but the computation is in 'block3'
 ;; which does not dominate 'block2'.
 define i32 @test4(i32* %p, i32* %q, i32** %Hack, i1 %C) {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 block1:
 	br i1 %C, label %block2, label %block3
 
@@ -116,7 +116,7 @@ block4:
 ;}
 
 define void @test5(i32 %N, double* nocapture %G) nounwind ssp {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 entry:
   %0 = add i32 %N, -1           
   %1 = icmp sgt i32 %0, 0       
@@ -159,7 +159,7 @@ return:
 ;}
 
 define void @test6(i32 %N, double* nocapture %G) nounwind ssp {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 entry:
   %0 = add i32 %N, -1           
   %1 = icmp sgt i32 %0, 0       
@@ -242,7 +242,7 @@ return:
 ;; Here the loaded address isn't available in 'block2' at all, requiring a new
 ;; GEP to be inserted into it.
 define i32 @test8(i32* %p, i32* %q, i32** %Hack, i1 %C) {
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 block1:
 	br i1 %C, label %block2, label %block3
 
@@ -365,7 +365,7 @@ return:
 
 ; Test critical edge splitting.
 define i32 @test11(i32* %p, i1 %C, i32 %N) {
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 block1:
         br i1 %C, label %block2, label %block3
 
diff --git a/test/Transforms/GVN/preserve-tbaa.ll b/test/Transforms/GVN/preserve-tbaa.ll
index a936755..e52772b 100644
--- a/test/Transforms/GVN/preserve-tbaa.ll
+++ b/test/Transforms/GVN/preserve-tbaa.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64"
 
 ; GVN should preserve the TBAA tag on loads when doing PRE.
 
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK: %tmp33.pre = load i16* %P, align 2, !tbaa !0
 ; CHECK: br label %for.body
 define void @test(i16 *%P, i16* %Q) nounwind {
diff --git a/test/Transforms/GVN/readattrs.ll b/test/Transforms/GVN/readattrs.ll
new file mode 100644
index 0000000..ba624a7
--- /dev/null
+++ b/test/Transforms/GVN/readattrs.ll
@@ -0,0 +1,17 @@
+; RUN: opt -gvn -S -o - < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+declare void @use(i8* readonly nocapture)
+
+define i8 @test() {
+  %a = alloca i8
+  store i8 1, i8* %a
+  call void @use(i8* %a)
+  %b = load i8* %a
+  ret i8 %b
+; CHECK-LABEL: define i8 @test(
+; CHECK: call void @use(i8* %a)
+; CHECK-NEXT: ret i8 1
+}
diff --git a/test/Transforms/GVN/rle-phi-translate.ll b/test/Transforms/GVN/rle-phi-translate.ll
index 6731f43..1ce7e0b 100644
--- a/test/Transforms/GVN/rle-phi-translate.ll
+++ b/test/Transforms/GVN/rle-phi-translate.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 target triple = "i386-apple-darwin7"
 
 define i32 @test1(i32* %b, i32* %c) nounwind {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 entry:
 	%g = alloca i32
 	%t1 = icmp eq i32* %b, null
@@ -36,7 +36,7 @@ bb2:		; preds = %bb1, %bb
 }
 
 define i8 @test2(i1 %cond, i32* %b, i32* %c) nounwind {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 entry:
   br i1 %cond, label %bb, label %bb1
 
@@ -61,7 +61,7 @@ bb2:
 }
 
 define i32 @test3(i1 %cond, i32* %b, i32* %c) nounwind {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 entry:
   br i1 %cond, label %bb, label %bb1
 
@@ -88,7 +88,7 @@ bb2:
 
 ; PR5313
 define i32 @test4(i1 %cond, i32* %b, i32* %c) nounwind {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 entry:
   br i1 %cond, label %bb, label %bb1
 
@@ -121,7 +121,7 @@ bb2:
 ;
 ; Should compile into one load in the loop.
 define void @test5(i32 %N, double* nocapture %G) nounwind ssp {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 bb.nph:
   br label %for.body
 
diff --git a/test/Transforms/GVN/rle.ll b/test/Transforms/GVN/rle.ll
index f470ed8..8787dd5 100644
--- a/test/Transforms/GVN/rle.ll
+++ b/test/Transforms/GVN/rle.ll
@@ -7,7 +7,7 @@ define i32 @test0(i32 %V, i32* %P) {
 
   %A = load i32* %P
   ret i32 %A
-; CHECK: @test0
+; CHECK-LABEL: @test0(
 ; CHECK: ret i32 %V
 }
 
@@ -47,7 +47,7 @@ define float @coerce_mustalias1(i32 %V, i32* %P) {
 
   %A = load float* %P2
   ret float %A
-; CHECK: @coerce_mustalias1
+; CHECK-LABEL: @coerce_mustalias1(
 ; CHECK-NOT: load
 ; CHECK: ret float 
 }
@@ -60,7 +60,7 @@ define float @coerce_mustalias2(i32* %V, i32** %P) {
 
   %A = load float* %P2
   ret float %A
-; CHECK: @coerce_mustalias2
+; CHECK-LABEL: @coerce_mustalias2(
 ; CHECK-NOT: load
 ; CHECK: ret float 
 }
@@ -73,7 +73,7 @@ define i32* @coerce_mustalias3(float %V, float* %P) {
 
   %A = load i32** %P2
   ret i32* %A
-; CHECK: @coerce_mustalias3
+; CHECK-LABEL: @coerce_mustalias3(
 ; CHECK-NOT: load
 ; CHECK: ret i32* 
 }
@@ -92,7 +92,7 @@ F:
   %X = bitcast i32 %A to float
   ret float %X
 
-; CHECK: @coerce_mustalias4
+; CHECK-LABEL: @coerce_mustalias4(
 ; CHECK: %A = load i32* %P
 ; CHECK-NOT: load
 ; CHECK: ret float
@@ -107,7 +107,7 @@ define i8 @coerce_mustalias5(i32 %V, i32* %P) {
 
   %A = load i8* %P2
   ret i8 %A
-; CHECK: @coerce_mustalias5
+; CHECK-LABEL: @coerce_mustalias5(
 ; CHECK-NOT: load
 ; CHECK: ret i8
 }
@@ -120,7 +120,7 @@ define float @coerce_mustalias6(i64 %V, i64* %P) {
 
   %A = load float* %P2
   ret float %A
-; CHECK: @coerce_mustalias6
+; CHECK-LABEL: @coerce_mustalias6(
 ; CHECK-NOT: load
 ; CHECK: ret float
 }
@@ -133,7 +133,7 @@ define i8* @coerce_mustalias7(i64 %V, i64* %P) {
 
   %A = load i8** %P2
   ret i8* %A
-; CHECK: @coerce_mustalias7
+; CHECK-LABEL: @coerce_mustalias7(
 ; CHECK-NOT: load
 ; CHECK: ret i8*
 }
@@ -146,7 +146,7 @@ entry:
   %arrayidx = getelementptr inbounds i16* %A, i64 42
   %tmp2 = load i16* %arrayidx
   ret i16 %tmp2
-; CHECK: @memset_to_i16_local
+; CHECK-LABEL: @memset_to_i16_local(
 ; CHECK-NOT: load
 ; CHECK: ret i16 257
 }
@@ -159,7 +159,7 @@ entry:
   %arrayidx = getelementptr inbounds float* %A, i64 42 ; <float*> [#uses=1]
   %tmp2 = load float* %arrayidx                   ; <float> [#uses=1]
   ret float %tmp2
-; CHECK: @memset_to_float_local
+; CHECK-LABEL: @memset_to_float_local(
 ; CHECK-NOT: load
 ; CHECK: zext
 ; CHECK-NEXT: shl
@@ -187,7 +187,7 @@ Cont:
   %A = load i16* %P2
   ret i16 %A
 
-; CHECK: @memset_to_i16_nonlocal0
+; CHECK-LABEL: @memset_to_i16_nonlocal0(
 ; CHECK: Cont:
 ; CHECK-NEXT:   %A = phi i16 [ 514, %F ], [ 257, %T ]
 ; CHECK-NOT: load
@@ -204,7 +204,7 @@ entry:
   %arrayidx = getelementptr inbounds float* %A, i64 1 ; <float*> [#uses=1]
   %tmp2 = load float* %arrayidx                   ; <float> [#uses=1]
   ret float %tmp2
-; CHECK: @memcpy_to_float_local
+; CHECK-LABEL: @memcpy_to_float_local(
 ; CHECK-NOT: load
 ; CHECK: ret float 1.400000e+01
 }
@@ -228,7 +228,7 @@ Cont:
   %A = load i8* %P3
   ret i8 %A
 
-; CHECK: @coerce_mustalias_nonlocal0
+; CHECK-LABEL: @coerce_mustalias_nonlocal0(
 ; CHECK: Cont:
 ; CHECK:   %A = phi i8 [
 ; CHECK-NOT: load
@@ -254,7 +254,7 @@ Cont:
   %A = load i8* %P3
   ret i8 %A
 
-; CHECK: @coerce_mustalias_nonlocal1
+; CHECK-LABEL: @coerce_mustalias_nonlocal1(
 ; CHECK: Cont:
 ; CHECK:   %A = phi i8 [
 ; CHECK-NOT: load
@@ -277,7 +277,7 @@ Cont:
   %A = load i8* %P3
   ret i8 %A
 
-; CHECK: @coerce_mustalias_pre0
+; CHECK-LABEL: @coerce_mustalias_pre0(
 ; CHECK: F:
 ; CHECK:   load i8* %P3
 ; CHECK: Cont:
@@ -301,7 +301,7 @@ define i8 @coerce_offset0(i32 %V, i32* %P) {
 
   %A = load i8* %P3
   ret i8 %A
-; CHECK: @coerce_offset0
+; CHECK-LABEL: @coerce_offset0(
 ; CHECK-NOT: load
 ; CHECK: ret i8
 }
@@ -324,7 +324,7 @@ Cont:
   %A = load i8* %P4
   ret i8 %A
 
-; CHECK: @coerce_offset_nonlocal0
+; CHECK-LABEL: @coerce_offset_nonlocal0(
 ; CHECK: Cont:
 ; CHECK:   %A = phi i8 [
 ; CHECK-NOT: load
@@ -348,7 +348,7 @@ Cont:
   %A = load i8* %P4
   ret i8 %A
 
-; CHECK: @coerce_offset_pre0
+; CHECK-LABEL: @coerce_offset_pre0(
 ; CHECK: F:
 ; CHECK:   load i8* %P4
 ; CHECK: Cont:
@@ -378,7 +378,7 @@ block4:
   %d = load i32* %c
   ret i32 %d
   
-; CHECK: @chained_load
+; CHECK-LABEL: @chained_load(
 ; CHECK: %z = load i32** %p
 ; CHECK-NOT: load
 ; CHECK: %d = load i32* %z
@@ -390,7 +390,7 @@ declare i1 @cond() readonly
 declare i1 @cond2() readonly
 
 define i32 @phi_trans2() {
-; CHECK: @phi_trans2
+; CHECK-LABEL: @phi_trans2(
 entry:
   %P = alloca i32, i32 400
   br label %F1
@@ -428,7 +428,7 @@ TY:
 }
 
 define i32 @phi_trans3(i32* %p) {
-; CHECK: @phi_trans3
+; CHECK-LABEL: @phi_trans3(
 block1:
   br i1 true, label %block2, label %block3
 
@@ -469,7 +469,7 @@ exit:
 }
 
 define i8 @phi_trans4(i8* %p) {
-; CHECK: @phi_trans4
+; CHECK-LABEL: @phi_trans4(
 entry:
   %X3 = getelementptr i8* %p, i32 192
   store i8 192, i8* %X3
@@ -499,7 +499,7 @@ out:
 }
 
 define i8 @phi_trans5(i8* %p) {
-; CHECK: @phi_trans5
+; CHECK-LABEL: @phi_trans5(
 entry:
   
   %X4 = getelementptr i8* %p, i32 2
@@ -542,7 +542,7 @@ entry:
   %arraydecay = getelementptr inbounds [256 x i32]* %x, i32 0, i32 0 ; <i32*>
   %tmp1 = load i32* %arraydecay                   ; <i32> [#uses=1]
   ret i32 %tmp1
-; CHECK: @memset_to_load
+; CHECK-LABEL: @memset_to_load(
 ; CHECK: ret i32 0
 }
 
@@ -561,7 +561,7 @@ entry:
   %add = add nsw i32 %tmp2, %conv
   ret i32 %add
 
-; TEMPORARILYDISABLED: @load_load_partial_alias
+; TEMPORARILYDISABLED-LABEL: @load_load_partial_alias(
 ; TEMPORARILYDISABLED: load i32*
 ; TEMPORARILYDISABLED-NOT: load
 ; TEMPORARILYDISABLED: lshr i32 {{.*}}, 8
@@ -588,7 +588,7 @@ land.lhs.true:                                    ; preds = %entry
 
 if.end:
   ret i32 52
-; TEMPORARILY_DISABLED: @load_load_partial_alias_cross_block
+; TEMPORARILY_DISABLED-LABEL: @load_load_partial_alias_cross_block(
 ; TEMPORARILY_DISABLED: land.lhs.true:
 ; TEMPORARILY_DISABLED-NOT: load i8
 ; TEMPORARILY_DISABLED: ret i32 %conv6
@@ -611,7 +611,7 @@ entry:
   %conv2 = zext i8 %tmp1 to i32
   %add = add nsw i32 %conv, %conv2
   ret i32 %add
-; CHECK: @test_widening1
+; CHECK-LABEL: @test_widening1(
 ; CHECK-NOT: load
 ; CHECK: load i16*
 ; CHECK-NOT: load
@@ -635,7 +635,7 @@ entry:
   %add3 = add nsw i32 %add2, %conv3
 
   ret i32 %add3
-; CHECK: @test_widening2
+; CHECK-LABEL: @test_widening2(
 ; CHECK-NOT: load
 ; CHECK: load i32*
 ; CHECK-NOT: load
diff --git a/test/Transforms/GlobalOpt/2009-02-15-ResolveAlias.ll b/test/Transforms/GlobalOpt/2009-02-15-ResolveAlias.ll
index a5be2b1..b98faca 100644
--- a/test/Transforms/GlobalOpt/2009-02-15-ResolveAlias.ll
+++ b/test/Transforms/GlobalOpt/2009-02-15-ResolveAlias.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -globalopt -S | FileCheck %s
 
 define internal void @f() {
-; CHECK-NOT: @f
+; CHECK-NOT: @f(
 ; CHECK: define void @a
 	ret void
 }
diff --git a/test/Transforms/GlobalOpt/2009-03-05-dbg.ll b/test/Transforms/GlobalOpt/2009-03-05-dbg.ll
index e71aed9..e08320b 100644
--- a/test/Transforms/GlobalOpt/2009-03-05-dbg.ll
+++ b/test/Transforms/GlobalOpt/2009-03-05-dbg.ll
@@ -56,22 +56,24 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !llvm.dbg.gv = !{!0}
 
 !0 = metadata !{i32 458804, i32 0, metadata !1, metadata !"Stop", metadata !"Stop", metadata !"", metadata !1, i32 2, metadata !2, i1 true, i1 true, i32* @Stop} ; [ DW_TAG_variable ]
-!1 = metadata !{i32 458769, i32 0, i32 1, metadata !"g.c", metadata !"/tmp", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!2 = metadata !{i32 458788, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!1 = metadata !{i32 458769, metadata !20, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !21, metadata !21, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!2 = metadata !{i32 458788, null, metadata !1, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !3 = metadata !{i32 459009, metadata !4, metadata !"i", metadata !1, i32 4, metadata !2} ; [ DW_TAG_arg_variable ]
-!4 = metadata !{i32 458798, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 4, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
+!4 = metadata !{i32 458798, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", i32 4, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i32 0, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !5 = metadata !{i32 458773, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !6 = metadata !{metadata !2, metadata !2}
 !7 = metadata !{i32 5, i32 0, metadata !8, null}
-!8 = metadata !{i32 458763, metadata !4, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!8 = metadata !{i32 458763, metadata !20, metadata !4, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !9 = metadata !{i32 6, i32 0, metadata !8, null}
 !10 = metadata !{i32 7, i32 0, metadata !8, null}
 !11 = metadata !{i32 9, i32 0, metadata !8, null}
 !12 = metadata !{i32 11, i32 0, metadata !8, null}
 !13 = metadata !{i32 14, i32 0, metadata !14, null}
-!14 = metadata !{i32 458763, metadata !15, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
-!15 = metadata !{i32 458798, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", metadata !1, i32 13, metadata !16, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
+!14 = metadata !{i32 458763, metadata !20, metadata !15, i32 0, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!15 = metadata !{i32 458798, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", i32 13, metadata !16, i1 false, i1 true, i32 0, i32 0, null, i32 0, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !16 = metadata !{i32 458773, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !17, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !17 = metadata !{metadata !2}
 !18 = metadata !{i32 15, i32 0, metadata !14, null}
 !19 = metadata !{i32 16, i32 0, metadata !14, null}
+!20 = metadata !{metadata !"g.c", metadata !"/tmp"}
+!21 = metadata !{i32 0}
diff --git a/test/Transforms/GlobalOpt/2012-05-11-blockaddress.ll b/test/Transforms/GlobalOpt/2012-05-11-blockaddress.ll
index 0c58c1a..24213af 100644
--- a/test/Transforms/GlobalOpt/2012-05-11-blockaddress.ll
+++ b/test/Transforms/GlobalOpt/2012-05-11-blockaddress.ll
@@ -2,7 +2,7 @@
 ; Check that the mere presence of a blockaddress doesn't prevent -globalopt
 ; from promoting @f to fastcc.
 
-; CHECK: define{{.*}}fastcc{{.*}}@f
+; CHECK-LABEL: define{{.*}}fastcc{{.*}}@f(
 define internal i8* @f() {
   ret i8* blockaddress(@f, %L1)
 L1:
diff --git a/test/Transforms/GlobalOpt/alias-used.ll b/test/Transforms/GlobalOpt/alias-used.ll
index 758e469..05ac7f9 100644
--- a/test/Transforms/GlobalOpt/alias-used.ll
+++ b/test/Transforms/GlobalOpt/alias-used.ll
@@ -9,8 +9,8 @@
 @llvm.used = appending global [3 x i8*] [i8* bitcast (void ()* @fa to i8*), i8* bitcast (void ()* @f to i8*), i8* @ca], section "llvm.metadata"
 ; CHECK-DAG: @llvm.used = appending global [3 x i8*] [i8* bitcast (void ()* @fa to i8*), i8* bitcast (void ()* @f to i8*), i8* @ca], section "llvm.metadata"
 
-@llvm.compiler_used = appending global [4 x i8*] [i8* bitcast (void ()* @fa3 to i8*), i8* bitcast (void ()* @fa to i8*), i8* @ia, i8* @i], section "llvm.metadata"
-; CHECK-DAG: @llvm.compiler_used = appending global [2 x i8*] [i8* bitcast (void ()* @fa3 to i8*), i8* @ia], section "llvm.metadata"
+@llvm.compiler.used = appending global [4 x i8*] [i8* bitcast (void ()* @fa3 to i8*), i8* bitcast (void ()* @fa to i8*), i8* @ia, i8* @i], section "llvm.metadata"
+; CHECK-DAG: @llvm.compiler.used = appending global [2 x i8*] [i8* bitcast (void ()* @fa3 to i8*), i8* @ia], section "llvm.metadata"
 
 @sameAsUsed = global [3 x i8*] [i8* bitcast (void ()* @fa to i8*), i8* bitcast (void ()* @f to i8*), i8* @ca]
 ; CHECK-DAG: @sameAsUsed = global [3 x i8*] [i8* bitcast (void ()* @f to i8*), i8* bitcast (void ()* @f to i8*), i8* @c]
diff --git a/test/Transforms/GlobalOpt/blockaddress.ll b/test/Transforms/GlobalOpt/blockaddress.ll
index 13da762..f7f8308 100644
--- a/test/Transforms/GlobalOpt/blockaddress.ll
+++ b/test/Transforms/GlobalOpt/blockaddress.ll
@@ -3,7 +3,7 @@
 @x = internal global i8* zeroinitializer
 
 define void @f() {
-; CHECK: @f
+; CHECK-LABEL: @f(
 
 ; Check that we don't hit an assert in Constant::IsThreadDependent()
 ; when storing this blockaddress into a global.
@@ -13,7 +13,7 @@ define void @f() {
 }
 
 define void @g() {
-; CHECK: @g
+; CHECK-LABEL: @g(
 
 here:
   ret void
diff --git a/test/Transforms/GlobalOpt/cleanup-pointer-root-users.ll b/test/Transforms/GlobalOpt/cleanup-pointer-root-users.ll
index a472f10..b6dfdea 100644
--- a/test/Transforms/GlobalOpt/cleanup-pointer-root-users.ll
+++ b/test/Transforms/GlobalOpt/cleanup-pointer-root-users.ll
@@ -3,7 +3,7 @@
 @glbl = internal global i8* null
 
 define void @test1a() {
-; CHECK: @test1a
+; CHECK-LABEL: @test1a(
 ; CHECK-NOT: store
 ; CHECK-NEXT: ret void
   store i8* null, i8** @glbl
@@ -11,7 +11,7 @@ define void @test1a() {
 }
 
 define void @test1b(i8* %p) {
-; CHECK: @test1b
+; CHECK-LABEL: @test1b(
 ; CHECK-NEXT: store
 ; CHECK-NEXT: ret void
   store i8* %p, i8** @glbl
@@ -19,7 +19,7 @@ define void @test1b(i8* %p) {
 }
 
 define void @test2() {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: alloca i8
   %txt = alloca i8
   call void @foo2(i8* %txt)
@@ -31,7 +31,7 @@ declare i8* @strdup(i8*)
 declare void @foo2(i8*)
 
 define void @test3() uwtable {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NOT: bb1:
 ; CHECK-NOT: bb2:
 ; CHECK: invoke
diff --git a/test/Transforms/GlobalOpt/compiler-used.ll b/test/Transforms/GlobalOpt/compiler-used.ll
new file mode 100644
index 0000000..a710d27
--- /dev/null
+++ b/test/Transforms/GlobalOpt/compiler-used.ll
@@ -0,0 +1,16 @@
+; RUN: opt < %s -globalopt -S | FileCheck %s
+
+; Test that when all members of llvm.compiler.used are found to be redundant
+; we delete it instead of crashing.
+
+define void @foo() {
+  ret void
+}
+
+@llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @foo to i8*)], section "llvm.metadata"
+
+@llvm.compiler.used = appending global [1 x i8*] [i8* bitcast (void ()* @foo to i8*)], section "llvm.metadata"
+
+; CHECK-NOT: @llvm.compiler.used
+; CHECK: @llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @foo to i8*)], section "llvm.metadata"
+; CHECK-NOT: @llvm.compiler.used
diff --git a/test/Transforms/GlobalOpt/ctor-list-opt-constexpr.ll b/test/Transforms/GlobalOpt/ctor-list-opt-constexpr.ll
index c907610..dd86f01 100644
--- a/test/Transforms/GlobalOpt/ctor-list-opt-constexpr.ll
+++ b/test/Transforms/GlobalOpt/ctor-list-opt-constexpr.ll
@@ -20,7 +20,7 @@ entry:
   store i32* inttoptr (i64 sdiv (i64 ptrtoint (i32* @G to i64), i64 ptrtoint (i32* @H to i64)) to i32*), i32** %tmp, align 8
   ret void
 }
-; CHECK: @init1
+; CHECK-LABEL: @init1(
 ; CHECK: store i32*
 
 ; PR11705 - ptrtoint isn't safe in general in global initializers.
@@ -30,5 +30,5 @@ entry:
   store i128 ptrtoint (i32* @G to i128), i128* %tmp, align 16
   ret void
 }
-; CHECK: @init2
+; CHECK-LABEL: @init2(
 ; CHECK: store i128
diff --git a/test/Transforms/GlobalOpt/deadglobal.ll b/test/Transforms/GlobalOpt/deadglobal.ll
index cad5a91..9563a23 100644
--- a/test/Transforms/GlobalOpt/deadglobal.ll
+++ b/test/Transforms/GlobalOpt/deadglobal.ll
@@ -16,7 +16,7 @@ define void @foo1() {
 @G2 = linkonce_odr constant i32 42
 
 define void @foo2() {
-; CHECK: define void @foo2
+; CHECK-LABEL: define void @foo2(
 ; CHECK-NEXT: store
         store i32 1, i32* @G2
         ret void
diff --git a/test/Transforms/GlobalOpt/integer-bool.ll b/test/Transforms/GlobalOpt/integer-bool.ll
index 5185806..abf5fdd 100644
--- a/test/Transforms/GlobalOpt/integer-bool.ll
+++ b/test/Transforms/GlobalOpt/integer-bool.ll
@@ -19,7 +19,7 @@ define void @set2() {
 }
 
 define i1 @get() {
-; CHECK: @get
+; CHECK-LABEL: @get(
   %A = load i32 addrspace(1) * @G
   %C = icmp slt i32 %A, 2
   ret i1 %C
diff --git a/test/Transforms/GlobalOpt/invariant-nodatalayout.ll b/test/Transforms/GlobalOpt/invariant-nodatalayout.ll
new file mode 100644
index 0000000..a2abd52
--- /dev/null
+++ b/test/Transforms/GlobalOpt/invariant-nodatalayout.ll
@@ -0,0 +1,17 @@
+; RUN: opt -globalopt -S -o - < %s | FileCheck %s
+; The check here is that it doesn't crash.
+
+declare {}* @llvm.invariant.start(i64 %size, i8* nocapture %ptr)
+
+@object1 = global { i32, i32 } zeroinitializer
+; CHECK: @object1 = global { i32, i32 } zeroinitializer
+
+define void @ctor1() {
+  %ptr = bitcast {i32, i32}* @object1 to i8*
+  call {}* @llvm.invariant.start(i64 4, i8* %ptr)
+  ret void
+}
+
+@llvm.global_ctors = appending constant
+  [1 x { i32, void ()* }]
+  [ { i32, void ()* } { i32 65535, void ()* @ctor1 } ]
diff --git a/test/Transforms/GlobalOpt/load-store-global.ll b/test/Transforms/GlobalOpt/load-store-global.ll
index 25a5337..ad7326d 100644
--- a/test/Transforms/GlobalOpt/load-store-global.ll
+++ b/test/Transforms/GlobalOpt/load-store-global.ll
@@ -7,14 +7,14 @@ define void @foo() {
         %V = load i32* @G               ; <i32> [#uses=1]
         store i32 %V, i32* @G
         ret void
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK-NEXT: ret void
 }
 
 define i32 @bar() {
         %X = load i32* @G               ; <i32> [#uses=1]
         ret i32 %X
-; CHECK: @bar
+; CHECK-LABEL: @bar(
 ; CHECK-NEXT: ret i32 17
 }
 
@@ -31,7 +31,7 @@ define void @qux() nounwind {
   store i64* inttoptr (i64 1 to i64*), i64** @a, align 8
   %l = load i64** @a, align 8
   ret void
-; CHECK: @qux
+; CHECK-LABEL: @qux(
 ; CHECK-NOT: store
 ; CHECK-NOT: load
 }
diff --git a/test/Transforms/GlobalOpt/metadata.ll b/test/Transforms/GlobalOpt/metadata.ll
index 730e2b0..ecf3f94 100644
--- a/test/Transforms/GlobalOpt/metadata.ll
+++ b/test/Transforms/GlobalOpt/metadata.ll
@@ -6,7 +6,7 @@
 @G = internal global i8** null
 
 define i32 @main(i32 %argc, i8** %argv) {
-; CHECK: @main
+; CHECK-LABEL: @main(
 ; CHECK: %G = alloca
   store i8** %argv, i8*** @G
   ret i32 0
diff --git a/test/Transforms/GlobalOpt/tls.ll b/test/Transforms/GlobalOpt/tls.ll
index 7a410e5..59ae23a 100644
--- a/test/Transforms/GlobalOpt/tls.ll
+++ b/test/Transforms/GlobalOpt/tls.ll
@@ -29,7 +29,7 @@ entry:
   %1 = load i32* %0, align 4
   ret i32 %1
 
-; CHECK: @f
+; CHECK-LABEL: @f(
 ; Make sure that the load from @ip hasn't been removed.
 ; CHECK: load i32** @ip
 ; CHECK: ret
@@ -46,7 +46,7 @@ entry:
   tail call void @signal() nounwind
   ret void
 
-; CHECK: @g
+; CHECK-LABEL: @g(
 ; Make sure that the store to @ip hasn't been removed.
 ; CHECK: store {{.*}} @ip
 ; CHECK: ret
diff --git a/test/Transforms/GlobalOpt/zeroinitializer-gep-load.ll b/test/Transforms/GlobalOpt/zeroinitializer-gep-load.ll
index d613601..d978723 100644
--- a/test/Transforms/GlobalOpt/zeroinitializer-gep-load.ll
+++ b/test/Transforms/GlobalOpt/zeroinitializer-gep-load.ll
@@ -6,6 +6,6 @@ define i32 @test1(i64 %idx) nounwind {
   %arrayidx = getelementptr inbounds [10 x i32]* @zero, i64 0, i64 %idx
   %l = load i32* %arrayidx
   ret i32 %l
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret i32 0
 }
diff --git a/test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll b/test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll
index 76c90e0..a8020e6 100644
--- a/test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll
+++ b/test/Transforms/IndVarSimplify/2011-10-27-lftrnull.ll
@@ -4,7 +4,7 @@
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
 target triple = "thumbv7-apple-darwin"
 
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK: if.end.i126:
 ; CHECK: %exitcond = icmp ne i8* %incdec.ptr.i, getelementptr (i8* null, i32 undef)
 define void @test() nounwind {
diff --git a/test/Transforms/IndVarSimplify/2011-11-01-lftrptr.ll b/test/Transforms/IndVarSimplify/2011-11-01-lftrptr.ll
index c0c508f..8247886 100644
--- a/test/Transforms/IndVarSimplify/2011-11-01-lftrptr.ll
+++ b/test/Transforms/IndVarSimplify/2011-11-01-lftrptr.ll
@@ -9,7 +9,7 @@
 ; SCEV. Since it's an i8*, it has unit stride so we never adjust the
 ; SCEV expression in a way that would convert it to an integer type.
 
-; CHECK: @testnullptrptr
+; CHECK-LABEL: @testnullptrptr(
 ; CHECK: loop:
 ; CHECK: icmp ne
 define i8 @testnullptrptr(i8* %buf, i8* %end) nounwind {
@@ -34,7 +34,7 @@ exit:
   ret i8 %snext
 }
 
-; CHECK: @testptrptr
+; CHECK-LABEL: @testptrptr(
 ; CHECK: loop:
 ; CHECK: icmp ne
 define i8 @testptrptr(i8* %buf, i8* %end) nounwind {
@@ -59,7 +59,7 @@ exit:
   ret i8 %snext
 }
 
-; CHECK: @testnullptrint
+; CHECK-LABEL: @testnullptrint(
 ; CHECK: loop:
 ; CHECK: icmp ne
 define i8 @testnullptrint(i8* %buf, i8* %end) nounwind {
@@ -89,7 +89,7 @@ exit:
   ret i8 %snext
 }
 
-; CHECK: @testptrint
+; CHECK-LABEL: @testptrint(
 ; CHECK: loop:
 ; CHECK: icmp ne
 define i8 @testptrint(i8* %buf, i8* %end) nounwind {
diff --git a/test/Transforms/IndVarSimplify/2011-11-17-selfphi.ll b/test/Transforms/IndVarSimplify/2011-11-17-selfphi.ll
index ccf2595..8f0cb80 100644
--- a/test/Transforms/IndVarSimplify/2011-11-17-selfphi.ll
+++ b/test/Transforms/IndVarSimplify/2011-11-17-selfphi.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -indvars -S | FileCheck %s
 ; PR11350: Check that SimplifyIndvar handles a cycle of useless self-phis.
 
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK-NOT: lcssa = phi
 define void @test() nounwind {
 entry:
diff --git a/test/Transforms/IndVarSimplify/2012-07-17-lftr-undef.ll b/test/Transforms/IndVarSimplify/2012-07-17-lftr-undef.ll
index 7c5f818..643d3cb 100644
--- a/test/Transforms/IndVarSimplify/2012-07-17-lftr-undef.ll
+++ b/test/Transforms/IndVarSimplify/2012-07-17-lftr-undef.ll
@@ -2,7 +2,7 @@
 ; PR13371: indvars pass incorrectly substitutes 'undef' values
 ;
 ; LFTR should not user %undef as the loop counter.
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK-NOT: icmp{{.*}}undef
 @.str3 = private constant [6 x i8] c"%lld\0A\00", align 1
 declare i32 @printf(i8* noalias nocapture, ...) nounwind
diff --git a/test/Transforms/IndVarSimplify/2012-10-19-congruent-constant.ll b/test/Transforms/IndVarSimplify/2012-10-19-congruent-constant.ll
index 5c47866..5f6ff36 100644
--- a/test/Transforms/IndVarSimplify/2012-10-19-congruent-constant.ll
+++ b/test/Transforms/IndVarSimplify/2012-10-19-congruent-constant.ll
@@ -19,7 +19,7 @@ for.body:                                         ; preds = %for.body, %entry
 for.end:                                          ; preds = %for.body
   ret void
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NOT: phi i1
 ; CHECK: call void @aux(i1 false, i1 false)
 }
diff --git a/test/Transforms/IndVarSimplify/dont-recompute.ll b/test/Transforms/IndVarSimplify/dont-recompute.ll
index d37b0e2..e5ced0f 100644
--- a/test/Transforms/IndVarSimplify/dont-recompute.ll
+++ b/test/Transforms/IndVarSimplify/dont-recompute.ll
@@ -21,7 +21,7 @@
 
 declare void @func(i32)
 
-; CHECK: @test
+; CHECK-LABEL: @test(
 define void @test(i32 %m) nounwind uwtable {
 entry:
   br label %for.body
@@ -45,7 +45,7 @@ for.end:                                          ; preds = %for.body
   ret void
 }
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 define i32 @test2(i32 %m) nounwind uwtable {
 entry:
   br label %for.body
diff --git a/test/Transforms/IndVarSimplify/eliminate-comparison.ll b/test/Transforms/IndVarSimplify/eliminate-comparison.ll
index 5dca712..b48403e 100644
--- a/test/Transforms/IndVarSimplify/eliminate-comparison.ll
+++ b/test/Transforms/IndVarSimplify/eliminate-comparison.ll
@@ -7,7 +7,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; Indvars should be able to simplify simple comparisons involving
 ; induction variables.
 
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK: %cond = and i1 %tobool.not, true
 
 define void @foo(i64 %n, i32* nocapture %p) nounwind {
@@ -42,7 +42,7 @@ return:
 
 ; Don't eliminate an icmp that's contributing to the loop exit test though.
 
-; CHECK: @_ZNK4llvm5APInt3ultERKS0_
+; CHECK-LABEL: @_ZNK4llvm5APInt3ultERKS0_(
 ; CHECK: %tmp99 = icmp sgt i32 %i, -1
 
 define i32 @_ZNK4llvm5APInt3ultERKS0_(i32 %tmp2.i1, i64** %tmp65, i64** %tmp73, i64** %tmp82, i64** %tmp90) {
@@ -85,7 +85,7 @@ bb20.loopexit:
 
 ; Indvars should eliminate the icmp here.
 
-; CHECK: @func_10
+; CHECK-LABEL: @func_10(
 ; CHECK-NOT: icmp
 ; CHECK: ret void
 
@@ -110,7 +110,7 @@ return:
 ; PR14432
 ; Indvars should not turn the second loop into an infinite one.
 
-; CHECK: @func_11
+; CHECK-LABEL: @func_11(
 ; CHECK: %tmp5 = icmp slt i32 %__key6.0, 10
 ; CHECK-NOT: br i1 true, label %noassert68, label %unrolledend
 
@@ -162,7 +162,7 @@ unrolledend:                                      ; preds = %forcond38
 declare void @llvm.trap() noreturn nounwind
 
 ; In this case the second loop only has a single iteration, fold the header away
-; CHECK: @func_12
+; CHECK-LABEL: @func_12(
 ; CHECK: %tmp5 = icmp slt i32 %__key6.0, 10
 ; CHECK: br i1 true, label %noassert68, label %unrolledend
 define i32 @func_12() nounwind uwtable {
diff --git a/test/Transforms/IndVarSimplify/eliminate-rem.ll b/test/Transforms/IndVarSimplify/eliminate-rem.ll
index f756389..64fe710 100644
--- a/test/Transforms/IndVarSimplify/eliminate-rem.ll
+++ b/test/Transforms/IndVarSimplify/eliminate-rem.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 
 ; Indvars should be able to eliminate this srem.
-; CHECK: @simple
+; CHECK-LABEL: @simple(
 ; CHECK-NOT: rem
 ; CHECK: ret
 
@@ -32,7 +32,7 @@ bb12:                                             ; preds = %bb11, %bb
 }
 
 ; Indvars should be able to eliminate the (i+1)%n.
-; CHECK: @f
+; CHECK-LABEL: @f(
 ; CHECK-NOT: rem
 ; CHECK: rem
 ; CHECK-NOT: rem
diff --git a/test/Transforms/IndVarSimplify/floating-point-iv.ll b/test/Transforms/IndVarSimplify/floating-point-iv.ll
index 266eebd..c5bf386 100644
--- a/test/Transforms/IndVarSimplify/floating-point-iv.ll
+++ b/test/Transforms/IndVarSimplify/floating-point-iv.ll
@@ -12,7 +12,7 @@ bb:		; preds = %bb, %entry
 
 return:		; preds = %bb
 	ret void
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: icmp
 }
 
@@ -31,7 +31,7 @@ bb:		; preds = %bb, %entry
 
 return:		; preds = %bb
 	ret void
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: icmp
 }
 
@@ -49,7 +49,7 @@ bb:		; preds = %bb, %entry
 
 return:
 	ret void
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: fcmp
 }
 
@@ -66,7 +66,7 @@ bb:		; preds = %bb, %entry
 
 return:
 	ret void
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NOT: cmp
 ; CHECK: br i1 false
 }
@@ -86,7 +86,7 @@ define void @test5() nounwind {
 exit:
   ret void
 
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: icmp slt i32 {{.*}}, 0
 ; CHECK-NEXT: br i1
 }
diff --git a/test/Transforms/IndVarSimplify/iv-fold.ll b/test/Transforms/IndVarSimplify/iv-fold.ll
index e0b05cd..41a1f5f 100644
--- a/test/Transforms/IndVarSimplify/iv-fold.ll
+++ b/test/Transforms/IndVarSimplify/iv-fold.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 ; Indvars should be able to fold IV increments into shr when low bits are zero.
 ;
-; CHECK: @foldIncShr
+; CHECK-LABEL: @foldIncShr(
 ; CHECK: shr.1 = lshr i32 %0, 5
 define i32 @foldIncShr(i32* %bitmap, i32 %bit_addr, i32 %nbits) nounwind {
 entry:
@@ -31,7 +31,7 @@ while.end:
 ; Invdars should not fold an increment into shr unless 2^shiftBits is
 ; a multiple of the recurrence step.
 ;
-; CHECK: @noFoldIncShr
+; CHECK-LABEL: @noFoldIncShr(
 ; CHECK: shr.1 = lshr i32 %inc.1, 5
 define i32 @noFoldIncShr(i32* %bitmap, i32 %bit_addr, i32 %nbits) nounwind {
 entry:
diff --git a/test/Transforms/IndVarSimplify/lftr-extend-const.ll b/test/Transforms/IndVarSimplify/lftr-extend-const.ll
new file mode 100644
index 0000000..2fac4a7
--- /dev/null
+++ b/test/Transforms/IndVarSimplify/lftr-extend-const.ll
@@ -0,0 +1,44 @@
+;RUN: opt -S %s -indvars | FileCheck %s
+
+; CHECK-LABEL-LABEL: @foo(
+; CHECK-NOT: %lftr.wideiv = trunc i32 %indvars.iv.next to i16
+; CHECK: %exitcond = icmp ne i32 %indvars.iv.next, 512
+define void @foo() #0 {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %i.01 = phi i16 [ 0, %entry ], [ %inc, %for.body ]
+  %conv2 = sext i16 %i.01 to i32
+  call void @bar(i32 %conv2) #1
+  %inc = add i16 %i.01, 1
+  %cmp = icmp slt i16 %inc, 512
+  br i1 %cmp, label %for.body, label %for.end
+
+for.end:                                          ; preds = %for.body
+  ret void
+}
+
+; Check that post-incrementing the backedge taken count does not overflow.
+; CHECK-LABEL-LABEL: @postinc(
+; CHECK: icmp eq i32 %indvars.iv.next, 256
+define i32 @postinc() #0 {
+entry:
+  br label %do.body
+
+do.body:                                          ; preds = %do.body, %entry
+  %first.0 = phi i8 [ 0, %entry ], [ %inc, %do.body ]
+  %conv = zext i8 %first.0 to i32
+  call void  @bar(i32 %conv) #1
+  %inc = add i8 %first.0, 1
+  %cmp = icmp eq i8 %first.0, -1
+  br i1 %cmp, label %do.end, label %do.body
+
+do.end:                                           ; preds = %do.body
+  ret i32 0
+}
+
+declare void @bar(i32)
+
+attributes #0 = { nounwind uwtable }
+attributes #1 = { nounwind }
diff --git a/test/Transforms/IndVarSimplify/lftr-reuse.ll b/test/Transforms/IndVarSimplify/lftr-reuse.ll
index 7fb36e5..fe3df5c 100644
--- a/test/Transforms/IndVarSimplify/lftr-reuse.ll
+++ b/test/Transforms/IndVarSimplify/lftr-reuse.ll
@@ -165,7 +165,7 @@ entry:
   %lim = add i32 %x, %n
   %cmp.ph = icmp ult i32 %x, %lim
   br i1 %cmp.ph, label %loop, label %exit
-; CHECK: @geplftr
+; CHECK-LABEL: @geplftr(
 ; CHECK: loop:
 ; CHECK: phi i8*
 ; DISABLE-NOT: phi      // This check is currently disabled
@@ -190,7 +190,7 @@ exit:
 define void @nevertaken() nounwind uwtable ssp {
 entry:
   br label %loop
-; CHECK: @nevertaken
+; CHECK-LABEL: @nevertaken(
 ; CHECK: loop:
 ; CHECK-NOT: phi
 ; CHECK-NOT: add
diff --git a/test/Transforms/IndVarSimplify/tripcount_compute.ll b/test/Transforms/IndVarSimplify/tripcount_compute.ll
index 8835b96..626a29b 100644
--- a/test/Transforms/IndVarSimplify/tripcount_compute.ll
+++ b/test/Transforms/IndVarSimplify/tripcount_compute.ll
@@ -5,7 +5,7 @@
 ; the exit value of the loop will be for some value, allowing us to substitute
 ; it directly into users outside of the loop, making the loop dead.
 
-; CHECK: @linear_setne
+; CHECK-LABEL: @linear_setne(
 ; CHECK: ret i32 100
 
 define i32 @linear_setne() {
@@ -22,7 +22,7 @@ loopexit:		; preds = %loop
 	ret i32 %i
 }
 
-; CHECK: @linear_setne_2
+; CHECK-LABEL: @linear_setne_2(
 ; CHECK: ret i32 100
 
 define i32 @linear_setne_2() {
@@ -39,7 +39,7 @@ loopexit:		; preds = %loop
 	ret i32 %i
 }
 
-; CHECK: @linear_setne_overflow
+; CHECK-LABEL: @linear_setne_overflow(
 ; CHECK: ret i32 0
 
 define i32 @linear_setne_overflow() {
@@ -56,7 +56,7 @@ loopexit:		; preds = %loop
 	ret i32 %i
 }
 
-; CHECK: @linear_setlt
+; CHECK-LABEL: @linear_setlt(
 ; CHECK: ret i32 100
 
 define i32 @linear_setlt() {
@@ -73,7 +73,7 @@ loopexit:		; preds = %loop
 	ret i32 %i
 }
 
-; CHECK: @quadratic_setlt
+; CHECK-LABEL: @quadratic_setlt(
 ; CHECK: ret i32 34
 
 define i32 @quadratic_setlt() {
@@ -91,7 +91,7 @@ loopexit:		; preds = %loop
 	ret i32 %i
 }
 
-; CHECK: @chained
+; CHECK-LABEL: @chained(
 ; CHECK: ret i32 200
 
 define i32 @chained() {
@@ -117,7 +117,7 @@ loopexit2:		; preds = %loop2
 	ret i32 %j
 }
 
-; CHECK: @chained4
+; CHECK-LABEL: @chained4(
 ; CHECK: ret i32 400
 
 define i32 @chained4() {
diff --git a/test/Transforms/IndVarSimplify/udiv-invariant-but-traps.ll b/test/Transforms/IndVarSimplify/udiv-invariant-but-traps.ll
index b2d2629..ef38f5d 100644
--- a/test/Transforms/IndVarSimplify/udiv-invariant-but-traps.ll
+++ b/test/Transforms/IndVarSimplify/udiv-invariant-but-traps.ll
@@ -27,6 +27,6 @@ bb14:
   ret i32 0
 }
 
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK: bb8:
 ; CHECK: udiv
diff --git a/test/Transforms/IndVarSimplify/udiv.ll b/test/Transforms/IndVarSimplify/udiv.ll
index 8260093..aee455d 100644
--- a/test/Transforms/IndVarSimplify/udiv.ll
+++ b/test/Transforms/IndVarSimplify/udiv.ll
@@ -8,7 +8,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; Indvars shouldn't emit a udiv here, because there's no udiv in the
 ; original code. This comes from SingleSource/Benchmarks/Shootout/sieve.c.
 
-; CHECK: @main
+; CHECK-LABEL: @main(
 ; CHECK-NOT: div
 
 define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
@@ -130,7 +130,7 @@ declare i32 @printf(i8* nocapture, ...) nounwind
 ; IndVars shouldn't be afraid to emit a udiv here, since there's a udiv in
 ; the original code.
 
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK: for.body.preheader:
 ; CHECK-NEXT: udiv
 
diff --git a/test/Transforms/IndVarSimplify/ult-sub-to-eq.ll b/test/Transforms/IndVarSimplify/ult-sub-to-eq.ll
index c58a3af..a421003 100644
--- a/test/Transforms/IndVarSimplify/ult-sub-to-eq.ll
+++ b/test/Transforms/IndVarSimplify/ult-sub-to-eq.ll
@@ -26,7 +26,7 @@ for.body:                                         ; preds = %entry, %for.body
 for.end:                                          ; preds = %for.body, %entry
   ret void
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 
 ; First check that we move the sub into the preheader, it doesn't have to be
 ; executed if %cmp4 == false
diff --git a/test/Transforms/IndVarSimplify/widen-nsw.ll b/test/Transforms/IndVarSimplify/widen-nsw.ll
new file mode 100644
index 0000000..56c3c0d
--- /dev/null
+++ b/test/Transforms/IndVarSimplify/widen-nsw.ll
@@ -0,0 +1,29 @@
+; RUN: opt < %s -indvars -S | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx"
+
+; CHECK-LABEL: @test1
+; CHECK: %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+define i32 @test1(i32* %a) #0 {
+entry:
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.body, %entry
+  %sum.0 = phi i32 [ 0, %entry ], [ %add, %for.body ]
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %cmp = icmp slt i32 %i.0, 1000
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.cond
+  %idxprom = sext i32 %i.0 to i64
+  %arrayidx = getelementptr inbounds i32* %a, i64 %idxprom
+  %0 = load i32* %arrayidx, align 4
+  %add = add nsw i32 %sum.0, %0
+  %inc = add nsw i32 %i.0, 1
+  br label %for.cond
+
+for.end:                                          ; preds = %for.cond
+  ret i32 %sum.0
+}
+
+attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/Transforms/Inline/2010-05-31-ByvalTailcall.ll b/test/Transforms/Inline/2010-05-31-ByvalTailcall.ll
index 1ce74e6..b37b9f2 100644
--- a/test/Transforms/Inline/2010-05-31-ByvalTailcall.ll
+++ b/test/Transforms/Inline/2010-05-31-ByvalTailcall.ll
@@ -17,7 +17,7 @@ define void @bar(i32* byval %x) {
 }
 
 define void @foo(i32* %x) {
-; CHECK: define void @foo
+; CHECK-LABEL: define void @foo(
 ; CHECK: store i32 %1, i32* %x
   call void @bar(i32* byval %x)
   ret void
diff --git a/test/Transforms/Inline/alloca-bonus.ll b/test/Transforms/Inline/alloca-bonus.ll
index d04d54e..3c5052b 100644
--- a/test/Transforms/Inline/alloca-bonus.ll
+++ b/test/Transforms/Inline/alloca-bonus.ll
@@ -7,7 +7,7 @@ declare void @llvm.lifetime.start(i64 %size, i8* nocapture %ptr)
 @glbl = external global i32
 
 define void @outer1() {
-; CHECK: @outer1
+; CHECK-LABEL: @outer1(
 ; CHECK-NOT: call void @inner1
   %ptr = alloca i32
   call void @inner1(i32* %ptr)
@@ -26,7 +26,7 @@ define void @inner1(i32 *%ptr) {
 }
 
 define void @outer2() {
-; CHECK: @outer2
+; CHECK-LABEL: @outer2(
 ; CHECK: call void @inner2
   %ptr = alloca i32
   call void @inner2(i32* %ptr)
@@ -46,7 +46,7 @@ define void @inner2(i32 *%ptr) {
 }
 
 define void @outer3() {
-; CHECK: @outer3
+; CHECK-LABEL: @outer3(
 ; CHECK-NOT: call void @inner3
   %ptr = alloca i32
   call void @inner3(i32* %ptr, i1 undef)
@@ -85,7 +85,7 @@ bb.false:
 }
 
 define void @outer4(i32 %A) {
-; CHECK: @outer4
+; CHECK-LABEL: @outer4(
 ; CHECK-NOT: call void @inner4
   %ptr = alloca i32
   call void @inner4(i32* %ptr, i32 %A)
@@ -126,7 +126,7 @@ bb.false:
 }
 
 define void @outer5() {
-; CHECK: @outer5
+; CHECK-LABEL: @outer5(
 ; CHECK-NOT: call void @inner5
   %ptr = alloca i32
   call void @inner5(i1 false, i32* %ptr)
diff --git a/test/Transforms/Inline/alloca-merge-align-nodl.ll b/test/Transforms/Inline/alloca-merge-align-nodl.ll
new file mode 100644
index 0000000..203f52b
--- /dev/null
+++ b/test/Transforms/Inline/alloca-merge-align-nodl.ll
@@ -0,0 +1,93 @@
+; RUN: opt < %s -inline -S | FileCheck %s
+; This variant of the test has no data layout information.
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.s = type { i32, i32 }
+
+define void @foo(%struct.s* byval nocapture readonly %a) {
+entry:
+  %x = alloca [2 x i32], align 4
+  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
+  %0 = load i32* %a1, align 4, !tbaa !0
+  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
+  store i32 %0, i32* %arrayidx, align 4, !tbaa !0
+  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
+  %1 = load i32* %b, align 4, !tbaa !0
+  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
+  store i32 %1, i32* %arrayidx2, align 4, !tbaa !0
+  call void @bar(i32* %arrayidx) #2
+  ret void
+}
+
+define void @foo0(%struct.s* byval nocapture readonly %a) {
+entry:
+  %x = alloca [2 x i32]
+  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
+  %0 = load i32* %a1, align 4, !tbaa !0
+  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
+  store i32 %0, i32* %arrayidx, align 4, !tbaa !0
+  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
+  %1 = load i32* %b, align 4, !tbaa !0
+  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
+  store i32 %1, i32* %arrayidx2, align 4, !tbaa !0
+  call void @bar(i32* %arrayidx) #2
+  ret void
+}
+
+declare void @bar(i32*) #1
+
+define void @goo(%struct.s* byval nocapture readonly %a) {
+entry:
+  %x = alloca [2 x i32], align 32
+  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
+  %0 = load i32* %a1, align 4, !tbaa !0
+  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
+  store i32 %0, i32* %arrayidx, align 32, !tbaa !0
+  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
+  %1 = load i32* %b, align 4, !tbaa !0
+  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
+  store i32 %1, i32* %arrayidx2, align 4, !tbaa !0
+  call void @bar(i32* %arrayidx) #2
+  ret void
+}
+
+; CHECK-LABEL: @main
+; CHECK: alloca [2 x i32], align 32
+; CHECK-NOT: alloca [2 x i32]
+; CHECK: ret i32 0
+
+define signext i32 @main() {
+entry:
+  %a = alloca i64, align 8
+  %tmpcast = bitcast i64* %a to %struct.s*
+  store i64 0, i64* %a, align 8
+  %a1 = bitcast i64* %a to i32*
+  store i32 1, i32* %a1, align 8, !tbaa !0
+  call void @foo(%struct.s* byval %tmpcast)
+  store i32 2, i32* %a1, align 8, !tbaa !0
+  call void @goo(%struct.s* byval %tmpcast)
+  ret i32 0
+}
+
+; CHECK-LABEL: @test0
+; CHECK: alloca [2 x i32], align 32
+; CHECK: alloca [2 x i32]
+; CHECK: ret i32 0
+
+define signext i32 @test0() {
+entry:
+  %a = alloca i64, align 8
+  %tmpcast = bitcast i64* %a to %struct.s*
+  store i64 0, i64* %a, align 8
+  %a1 = bitcast i64* %a to i32*
+  store i32 1, i32* %a1, align 8, !tbaa !0
+  call void @foo0(%struct.s* byval %tmpcast)
+  store i32 2, i32* %a1, align 8, !tbaa !0
+  call void @goo(%struct.s* byval %tmpcast)
+  ret i32 0
+}
+
+!0 = metadata !{metadata !"int", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA"}
+
diff --git a/test/Transforms/Inline/alloca-merge-align.ll b/test/Transforms/Inline/alloca-merge-align.ll
new file mode 100644
index 0000000..d789c79
--- /dev/null
+++ b/test/Transforms/Inline/alloca-merge-align.ll
@@ -0,0 +1,127 @@
+; RUN: opt < %s -inline -S | FileCheck %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.s = type { i32, i32 }
+
+define void @foo(%struct.s* byval nocapture readonly %a) {
+entry:
+  %x = alloca [2 x i32], align 4
+  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
+  %0 = load i32* %a1, align 4, !tbaa !0
+  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
+  store i32 %0, i32* %arrayidx, align 4, !tbaa !0
+  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
+  %1 = load i32* %b, align 4, !tbaa !0
+  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
+  store i32 %1, i32* %arrayidx2, align 4, !tbaa !0
+  call void @bar(i32* %arrayidx) #2
+  ret void
+}
+
+define void @foo0(%struct.s* byval nocapture readonly %a) {
+entry:
+  %x = alloca [2 x i32]
+  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
+  %0 = load i32* %a1, align 4, !tbaa !0
+  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
+  store i32 %0, i32* %arrayidx, align 4, !tbaa !0
+  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
+  %1 = load i32* %b, align 4, !tbaa !0
+  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
+  store i32 %1, i32* %arrayidx2, align 4, !tbaa !0
+  call void @bar(i32* %arrayidx) #2
+  ret void
+}
+
+define void @foo1(%struct.s* byval nocapture readonly %a) {
+entry:
+  %x = alloca [2 x i32], align 1
+  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
+  %0 = load i32* %a1, align 4, !tbaa !0
+  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
+  store i32 %0, i32* %arrayidx, align 4, !tbaa !0
+  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
+  %1 = load i32* %b, align 4, !tbaa !0
+  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
+  store i32 %1, i32* %arrayidx2, align 4, !tbaa !0
+  call void @bar(i32* %arrayidx) #2
+  ret void
+}
+
+declare void @bar(i32*) #1
+
+define void @goo(%struct.s* byval nocapture readonly %a) {
+entry:
+  %x = alloca [2 x i32], align 32
+  %a1 = getelementptr inbounds %struct.s* %a, i64 0, i32 0
+  %0 = load i32* %a1, align 4, !tbaa !0
+  %arrayidx = getelementptr inbounds [2 x i32]* %x, i64 0, i64 0
+  store i32 %0, i32* %arrayidx, align 32, !tbaa !0
+  %b = getelementptr inbounds %struct.s* %a, i64 0, i32 1
+  %1 = load i32* %b, align 4, !tbaa !0
+  %arrayidx2 = getelementptr inbounds [2 x i32]* %x, i64 0, i64 1
+  store i32 %1, i32* %arrayidx2, align 4, !tbaa !0
+  call void @bar(i32* %arrayidx) #2
+  ret void
+}
+
+; CHECK-LABEL: @main
+; CHECK: alloca [2 x i32], align 32
+; CHECK-NOT: alloca [2 x i32]
+; CHECK: ret i32 0
+
+define signext i32 @main() {
+entry:
+  %a = alloca i64, align 8
+  %tmpcast = bitcast i64* %a to %struct.s*
+  store i64 0, i64* %a, align 8
+  %a1 = bitcast i64* %a to i32*
+  store i32 1, i32* %a1, align 8, !tbaa !0
+  call void @foo(%struct.s* byval %tmpcast)
+  store i32 2, i32* %a1, align 8, !tbaa !0
+  call void @goo(%struct.s* byval %tmpcast)
+  ret i32 0
+}
+
+; CHECK-LABEL: @test0
+; CHECK: alloca [2 x i32], align 32
+; CHECK-NOT: alloca [2 x i32]
+; CHECK: ret i32 0
+
+define signext i32 @test0() {
+entry:
+  %a = alloca i64, align 8
+  %tmpcast = bitcast i64* %a to %struct.s*
+  store i64 0, i64* %a, align 8
+  %a1 = bitcast i64* %a to i32*
+  store i32 1, i32* %a1, align 8, !tbaa !0
+  call void @foo0(%struct.s* byval %tmpcast)
+  store i32 2, i32* %a1, align 8, !tbaa !0
+  call void @goo(%struct.s* byval %tmpcast)
+  ret i32 0
+}
+
+; CHECK-LABEL: @test1
+; CHECK: {{alloca \[2 x i32\]$}}
+; CHECK-NOT: alloca [2 x i32]
+; CHECK: ret i32 0
+
+define signext i32 @test1() {
+entry:
+  %a = alloca i64, align 8
+  %tmpcast = bitcast i64* %a to %struct.s*
+  store i64 0, i64* %a, align 8
+  %a1 = bitcast i64* %a to i32*
+  store i32 1, i32* %a1, align 8, !tbaa !0
+  call void @foo0(%struct.s* byval %tmpcast)
+  store i32 2, i32* %a1, align 8, !tbaa !0
+  call void @foo1(%struct.s* byval %tmpcast)
+  ret i32 0
+}
+
+!0 = metadata !{metadata !"int", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA"}
+
diff --git a/test/Transforms/Inline/always-inline.ll b/test/Transforms/Inline/always-inline.ll
index c918bc9..a8703b8 100644
--- a/test/Transforms/Inline/always-inline.ll
+++ b/test/Transforms/Inline/always-inline.ll
@@ -8,7 +8,7 @@ define i32 @inner1() alwaysinline {
   ret i32 1
 }
 define i32 @outer1() {
-; CHECK: @outer1
+; CHECK-LABEL: @outer1(
 ; CHECK-NOT: call
 ; CHECK: ret
 
@@ -17,7 +17,7 @@ define i32 @outer1() {
 }
 
 ; The always inliner can't DCE internal functions. PR2945
-; CHECK: @pr2945
+; CHECK-LABEL: @pr2945(
 define internal i32 @pr2945() nounwind {
   ret i32 0
 }
@@ -31,7 +31,7 @@ define void @outer2(i32 %N) {
 ; a function with a dynamic alloca into one without a dynamic alloca.
 ; rdar://6655932
 ;
-; CHECK: @outer2
+; CHECK-LABEL: @outer2(
 ; CHECK-NOT: call void @inner2
 ; CHECK-NOT: call void @inner2
 ; CHECK: ret void
@@ -51,7 +51,7 @@ entry:
 }
 define i32 @outer3() {
 entry:
-; CHECK: @outer3
+; CHECK-LABEL: @outer3(
 ; CHECK-NOT: call i32 @a
 ; CHECK: ret
 
@@ -69,7 +69,7 @@ entry:
 
 define i32 @outer4() {
 entry:
-; CHECK: @outer4
+; CHECK-LABEL: @outer4(
 ; CHECK: call i32 @b()
 ; CHECK: ret
 
@@ -89,7 +89,7 @@ two:
   ret i32 44
 }
 define i32 @outer5(i32 %x) {
-; CHECK: @outer5
+; CHECK-LABEL: @outer5(
 ; CHECK: call i32 @inner5
 ; CHECK: ret
 
@@ -113,7 +113,7 @@ return:
   ret void
 }
 define void @outer6() {
-; CHECK: @outer6
+; CHECK-LABEL: @outer6(
 ; CHECK: call void @inner6(i32 42)
 ; CHECK: ret
 
diff --git a/test/Transforms/Inline/basictest.ll b/test/Transforms/Inline/basictest.ll
index 39e25cb..085694f 100644
--- a/test/Transforms/Inline/basictest.ll
+++ b/test/Transforms/Inline/basictest.ll
@@ -9,7 +9,7 @@ define i32 @test1(i32 %W) {
         %X = call i32 @test1f(i32 7)
         %Y = add i32 %X, %W
         ret i32 %Y
-; CHECK: @test1(
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: %Y = add i32 7, %W
 ; CHECK-NEXT: ret i32 %Y
 }
@@ -20,7 +20,7 @@ define i32 @test1(i32 %W) {
 
 %T = type { i32, i32 }
 
-; CHECK-NOT: @test2f
+; CHECK-NOT: @test2f(
 define internal %T* @test2f(i1 %cond, %T* %P) {
   br i1 %cond, label %T, label %F
   
@@ -41,7 +41,7 @@ define i32 @test2(i1 %cond) {
   %D = load i32* %C
   ret i32 %D
   
-; CHECK: @test2(
+; CHECK-LABEL: @test2(
 ; CHECK-NOT: = alloca
 ; CHECK: ret i32
 }
@@ -75,7 +75,7 @@ define i32 @test3() {
 ;
 ; The call to @h *can* be inlined.
 
-; CHECK: @test
+; CHECK-LABEL: @test(
 define i32 @test() {
 ; CHECK: call i32 @f()
   %a = call i32 @f()
diff --git a/test/Transforms/Inline/devirtualize-2.ll b/test/Transforms/Inline/devirtualize-2.ll
index 02ff767..b7eb1be 100644
--- a/test/Transforms/Inline/devirtualize-2.ll
+++ b/test/Transforms/Inline/devirtualize-2.ll
@@ -40,5 +40,5 @@ define i32 @test2(i8* %this) ssp align 2 {
   ret i32 %X
 }
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: ret i32 41
diff --git a/test/Transforms/Inline/devirtualize.ll b/test/Transforms/Inline/devirtualize.ll
index d46154e..8948294 100644
--- a/test/Transforms/Inline/devirtualize.ll
+++ b/test/Transforms/Inline/devirtualize.ll
@@ -14,7 +14,7 @@ entry:
   %X = add i32 %call, 4
   ret i32 %X
   
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: store
 ; CHECK-NEXT: store
diff --git a/test/Transforms/Inline/dynamic_alloca_test.ll b/test/Transforms/Inline/dynamic_alloca_test.ll
index 15a5c66..1c17c7c 100644
--- a/test/Transforms/Inline/dynamic_alloca_test.ll
+++ b/test/Transforms/Inline/dynamic_alloca_test.ll
@@ -19,7 +19,7 @@ define internal void @callee(i32 %N) {
 }
 
 define void @foo(i32 %N) {
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK: alloca i32, i32 %{{.*}}
 ; CHECK: call i8* @llvm.stacksave()
 ; CHECK: alloca i32, i32 %{{.*}}
diff --git a/test/Transforms/Inline/gvn-inline-iteration.ll b/test/Transforms/Inline/gvn-inline-iteration.ll
index 526ed79..7916a13 100644
--- a/test/Transforms/Inline/gvn-inline-iteration.ll
+++ b/test/Transforms/Inline/gvn-inline-iteration.ll
@@ -12,9 +12,9 @@ entry:
   %call = tail call i32 %tmp3() nounwind          ; <i32> [#uses=1]
   ret i32 %call
 }
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK: ret i32 7
-; CHECK: @bar
+; CHECK-LABEL: @bar(
 ; CHECK: ret i32 7
 
 define internal i32 @bar() nounwind readnone ssp {
diff --git a/test/Transforms/Inline/inline-byval-bonus.ll b/test/Transforms/Inline/inline-byval-bonus.ll
index f3ed819..052a5f1 100644
--- a/test/Transforms/Inline/inline-byval-bonus.ll
+++ b/test/Transforms/Inline/inline-byval-bonus.ll
@@ -21,7 +21,7 @@ define i32 @caller(%struct.sphere* %i) {
   %call = call i32 @ray_sphere(%struct.sphere* %i, %struct.ray* byval align 8 %shadow_ray, %struct.spoint* null)
   ret i32 %call
 
-; CHECK: @caller
+; CHECK-LABEL: @caller(
 ; CHECK-NOT: call i32 @ray_sphere
 ; CHECK: ret i32
 }
diff --git a/test/Transforms/Inline/inline_cleanup.ll b/test/Transforms/Inline/inline_cleanup.ll
index 3898aa7..4361c2e 100644
--- a/test/Transforms/Inline/inline_cleanup.ll
+++ b/test/Transforms/Inline/inline_cleanup.ll
@@ -52,7 +52,7 @@ UnifiedReturnBlock:		; preds = %cond_next13
 declare void @ext(i32*)
 
 define void @test() {
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK-NOT: ret
 ;
 ; FIXME: This should be a CHECK-NOT, but currently we have a bug that causes us
@@ -128,7 +128,7 @@ end4:
 define void @outer2(i32 %z, i1 %b) {
 ; Ensure that after inlining, none of the blocks with a call to @f actually
 ; make it through inlining.
-; CHECK: define void @outer2
+; CHECK-LABEL: define void @outer2(
 ; CHECK-NOT: call
 ; CHECK: ret void
 
@@ -164,7 +164,7 @@ define void @PR12470_outer() {
 ; This previously crashed during inliner cleanup and folding inner return
 ; instructions. Check that we don't crash and we produce a function with a single
 ; return instruction due to merging the returns of the inlined function.
-; CHECK: define void @PR12470_outer
+; CHECK-LABEL: define void @PR12470_outer(
 ; CHECK-NOT: call
 ; CHECK: ret void
 ; CHECK-NOT: ret void
@@ -202,7 +202,7 @@ for.cond12.for.inc26_crit_edge.2:
 }
 
 define void @crasher_outer() {
-; CHECK: @crasher_outer
+; CHECK-LABEL: @crasher_outer(
 ; CHECK-NOT: call
 ; CHECK: ret void
 ; CHECK-NOT: ret
diff --git a/test/Transforms/Inline/inline_constprop.ll b/test/Transforms/Inline/inline_constprop.ll
index 77bc378..b59a270 100644
--- a/test/Transforms/Inline/inline_constprop.ll
+++ b/test/Transforms/Inline/inline_constprop.ll
@@ -6,7 +6,7 @@ define internal i32 @callee1(i32 %A, i32 %B) {
 }
 
 define i32 @caller1() {
-; CHECK: define i32 @caller1
+; CHECK-LABEL: define i32 @caller1(
 ; CHECK-NEXT: ret i32 3
 
   %X = call i32 @callee1( i32 10, i32 3 )
@@ -21,7 +21,7 @@ define i32 @caller2() {
 ; inline and be cheap. We should eventually do that and lower the threshold here
 ; to 1.
 ;
-; CHECK: @caller2
+; CHECK-LABEL: @caller2(
 ; CHECK-NOT: call void @callee2
 ; CHECK: ret
 
@@ -61,7 +61,7 @@ define i32 @caller3() {
 ; it doesn't count toward the inline cost when constant-prop proves those paths
 ; dead.
 ;
-; CHECK: @caller3
+; CHECK-LABEL: @caller3(
 ; CHECK-NOT: call
 ; CHECK: ret i32 6
 
@@ -119,7 +119,7 @@ define i8 @caller4(i8 %z) {
 ; as they are used heavily in standard library code and generic C++ code where
 ; the arguments are oftent constant but complete generality is required.
 ;
-; CHECK: @caller4
+; CHECK-LABEL: @caller4(
 ; CHECK-NOT: call
 ; CHECK: ret i8 -1
 
@@ -153,7 +153,7 @@ define i64 @caller5(i64 %y) {
 ; Check that we can round trip constants through various kinds of casts etc w/o
 ; losing track of the constant prop in the inline cost analysis.
 ;
-; CHECK: @caller5
+; CHECK-LABEL: @caller5(
 ; CHECK-NOT: call
 ; CHECK: ret i64 -1
 
@@ -187,6 +187,37 @@ bb.false:
   ret i64 %y8
 }
 
+define float @caller6() {
+; Check that we can constant-prop through fcmp instructions
+;
+; CHECK-LABEL: @caller6(
+; CHECK-NOT: call
+; CHECK: ret
+  %x = call float @callee6(float 42.0)
+  ret float %x
+}
+
+define float @callee6(float %x) {
+  %icmp = fcmp ugt float %x, 42.0
+  br i1 %icmp, label %bb.true, label %bb.false
+
+bb.true:
+  ; This block musn't be counted in the inline cost.
+  %x1 = fadd float %x, 1.0
+  %x2 = fadd float %x1, 1.0
+  %x3 = fadd float %x2, 1.0
+  %x4 = fadd float %x3, 1.0
+  %x5 = fadd float %x4, 1.0
+  %x6 = fadd float %x5, 1.0
+  %x7 = fadd float %x6, 1.0
+  %x8 = fadd float %x7, 1.0
+  ret float %x8
+
+bb.false:
+  ret float %x
+}
+
+
 
 define i32 @PR13412.main() {
 ; This is a somewhat complicated three layer subprogram that was reported to
diff --git a/test/Transforms/Inline/inline_minisize.ll b/test/Transforms/Inline/inline_minisize.ll
index 3dddbcf..b9aad60 100644
--- a/test/Transforms/Inline/inline_minisize.ll
+++ b/test/Transforms/Inline/inline_minisize.ll
@@ -200,7 +200,7 @@ for.end21:                                        ; preds = %for.cond14
 
 define i32 @fct3(i32 %c) nounwind uwtable ssp {
 entry:
-  ;CHECK: @fct3
+  ;CHECK-LABEL: @fct3(
   ;CHECK: call i32 @fct1
   ; The inline keyword gives a sufficient benefits to inline fct2
   ;CHECK-NOT: call i32 @fct2
@@ -216,7 +216,7 @@ entry:
 
 define i32 @fct4(i32 %c) minsize nounwind uwtable ssp {
 entry:
-  ;CHECK: @fct4
+  ;CHECK-LABEL: @fct4(
   ;CHECK: call i32 @fct1
   ; With Oz (minsize attribute), the benefit of inlining fct2
   ; is the same as fct1, thus no inlining for fct2
diff --git a/test/Transforms/Inline/inline_returns_twice.ll b/test/Transforms/Inline/inline_returns_twice.ll
index ab2e954..f316c91 100644
--- a/test/Transforms/Inline/inline_returns_twice.ll
+++ b/test/Transforms/Inline/inline_returns_twice.ll
@@ -15,7 +15,7 @@ entry:
 
 define i32 @g() {
 entry:
-; CHECK: define i32 @g
+; CHECK-LABEL: define i32 @g(
 ; CHECK: call i32 @f()
 ; CHECK-NOT: call i32 @a()
   %call = call i32 @f()
@@ -32,7 +32,7 @@ entry:
 
 define i32 @i() {
 entry:
-; CHECK: define i32 @i
+; CHECK-LABEL: define i32 @i(
 ; CHECK: call i32 @b()
 ; CHECK-NOT: call i32 @h()
   %call = call i32 @h() returns_twice
diff --git a/test/Transforms/Inline/lifetime-no-datalayout.ll b/test/Transforms/Inline/lifetime-no-datalayout.ll
index f4ffef3..5abb77f 100644
--- a/test/Transforms/Inline/lifetime-no-datalayout.ll
+++ b/test/Transforms/Inline/lifetime-no-datalayout.ll
@@ -10,7 +10,7 @@ define void @helper() {
 
 ; Size in llvm.lifetime.X should be -1 (unknown).
 define void @test() {
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK-NOT: lifetime
 ; CHECK: llvm.lifetime.start(i64 -1
 ; CHECK-NOT: lifetime
diff --git a/test/Transforms/Inline/lifetime.ll b/test/Transforms/Inline/lifetime.ll
index fc73385..12c433b 100644
--- a/test/Transforms/Inline/lifetime.ll
+++ b/test/Transforms/Inline/lifetime.ll
@@ -14,7 +14,7 @@ define void @helper_both_markers() {
 }
 
 define void @test_both_markers() {
-; CHECK: @test_both_markers
+; CHECK-LABEL: @test_both_markers(
 ; CHECK: llvm.lifetime.start(i64 2
 ; CHECK-NEXT: llvm.lifetime.end(i64 2
   call void @helper_both_markers()
@@ -38,7 +38,7 @@ define void @helper_no_markers() {
 ;; We can't use CHECK-NEXT because there's an extra call void @use in between.
 ;; Instead, we use CHECK-NOT to verify that there are no other lifetime calls.
 define void @test_no_marker() {
-; CHECK: @test_no_marker
+; CHECK-LABEL: @test_no_marker(
 ; CHECK-NOT: lifetime
 ; CHECK: llvm.lifetime.start(i64 1
 ; CHECK-NOT: lifetime
@@ -64,7 +64,7 @@ define void @helper_two_casts() {
 }
 
 define void @test_two_casts() {
-; CHECK: @test_two_casts
+; CHECK-LABEL: @test_two_casts(
 ; CHECK-NOT: lifetime
 ; CHECK: llvm.lifetime.start(i64 4
 ; CHECK-NOT: lifetime
@@ -88,7 +88,7 @@ define void @helper_arrays_alloca() {
 }
 
 define void @test_arrays_alloca() {
-; CHECK: @test_arrays_alloca
+; CHECK-LABEL: @test_arrays_alloca(
 ; CHECK-NOT: lifetime
 ; CHECK: llvm.lifetime.start(i64 40,
 ; CHECK-NOT: lifetime
diff --git a/test/Transforms/Inline/nested-inline.ll b/test/Transforms/Inline/nested-inline.ll
index 1292667..9d08ac0 100644
--- a/test/Transforms/Inline/nested-inline.ll
+++ b/test/Transforms/Inline/nested-inline.ll
@@ -6,7 +6,7 @@
 
 define fastcc void @foo(i32 %X) {
 entry:
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 	%ALL = alloca i32, align 4		; <i32*> [#uses=1]
 	%tmp1 = and i32 %X, 1		; <i32> [#uses=1]
 	%tmp1.upgrd.1 = icmp eq i32 %tmp1, 0		; <i1> [#uses=1]
@@ -47,7 +47,7 @@ UnifiedReturnBlock:		; preds = %cond_next13
 	ret void
 }
 
-; CHECK-NOT: @bar
+; CHECK-NOT: @bar(
 define internal fastcc void @bar(i32 %X) {
 entry:
 	%ALL = alloca i32, align 4		; <i32*> [#uses=1]
@@ -101,7 +101,7 @@ declare void @ext(i32*)
 define void @test(i32 %X) {
 entry:
 ; CHECK: test
-; CHECK-NOT: @bar
+; CHECK-NOT: @bar(
 	tail call fastcc void @bar( i32 %X )
 	tail call fastcc void @bar( i32 %X )
 	tail call fastcc void @bar2( i32 %X )
diff --git a/test/Transforms/Inline/noinline-recursive-fn.ll b/test/Transforms/Inline/noinline-recursive-fn.ll
index 5520093..2e581a7 100644
--- a/test/Transforms/Inline/noinline-recursive-fn.ll
+++ b/test/Transforms/Inline/noinline-recursive-fn.ll
@@ -25,7 +25,7 @@ return:                                           ; preds = %entry
 }
 
 
-;; CHECK: @bonk
+;; CHECK-LABEL: @bonk(
 ;; CHECK: call void @foo(i32 42)
 define void @bonk() nounwind ssp {
 entry:
@@ -62,7 +62,7 @@ return:                                           ; preds = %entry
 }
 
 
-; CHECK: @top_level
+; CHECK-LABEL: @top_level(
 ; CHECK: call void @f2(i32 122
 ; Here we inline one instance of the cycle, but we don't want to completely
 ; unroll it.
@@ -100,7 +100,7 @@ one.else:
 }
 
 define i32 @fib_caller() {
-; CHECK: @fib_caller
+; CHECK-LABEL: @fib_caller(
 ; CHECK-NOT: call
 ; CHECK: ret
   %f1 = call i32 @fib(i32 0)
diff --git a/test/Transforms/Inline/ptr-diff.ll b/test/Transforms/Inline/ptr-diff.ll
index 60fc3e2..01b42da 100644
--- a/test/Transforms/Inline/ptr-diff.ll
+++ b/test/Transforms/Inline/ptr-diff.ll
@@ -3,7 +3,7 @@
 target datalayout = "p:32:32"
 
 define i32 @outer1() {
-; CHECK: @outer1
+; CHECK-LABEL: @outer1(
 ; CHECK-NOT: call
 ; CHECK: ret i32
 
@@ -32,7 +32,7 @@ else:
 define i32 @outer2(i32* %ptr) {
 ; Test that an inbounds GEP disables this -- it isn't safe in general as
 ; wrapping changes the behavior of lessthan and greaterthan comparisions.
-; CHECK: @outer2
+; CHECK-LABEL: @outer2(
 ; CHECK: call i32 @inner2
 ; CHECK: ret i32
 
diff --git a/test/Transforms/Inline/recursive.ll b/test/Transforms/Inline/recursive.ll
index fe1c041..b9b14d1 100644
--- a/test/Transforms/Inline/recursive.ll
+++ b/test/Transforms/Inline/recursive.ll
@@ -6,7 +6,7 @@ target triple = "i386-apple-darwin10.0"
 ; rdar://10853263
 
 ; Make sure that the callee is still here.
-; CHECK: define i32 @callee
+; CHECK-LABEL: define i32 @callee(
 define i32 @callee(i32 %param) {
  %yyy = alloca [100000 x i8]
  %r = bitcast [100000 x i8]* %yyy to i8*
@@ -14,7 +14,7 @@ define i32 @callee(i32 %param) {
  ret i32 4
 }
 
-; CHECK: define i32 @caller
+; CHECK-LABEL: define i32 @caller(
 ; CHECK-NEXT: entry:
 ; CHECK-NOT: alloca
 ; CHECK: ret
diff --git a/test/Transforms/InstCombine/2007-01-27-AndICmp.ll b/test/Transforms/InstCombine/2007-01-27-AndICmp.ll
index 4d1b982..6298a07 100644
--- a/test/Transforms/InstCombine/2007-01-27-AndICmp.ll
+++ b/test/Transforms/InstCombine/2007-01-27-AndICmp.ll
@@ -1,8 +1,8 @@
 ; RUN: opt < %s -instcombine -S | grep "ugt.*, 1"
 
 define i1 @test(i32 %tmp1030) {
-	%tmp1037 = icmp ne i32 %tmp1030, 40		; <i1> [#uses=1]
-	%tmp1039 = icmp ne i32 %tmp1030, 41		; <i1> [#uses=1]
+	%tmp1037 = icmp ne i32 %tmp1030, 39		; <i1> [#uses=1]
+	%tmp1039 = icmp ne i32 %tmp1030, 40		; <i1> [#uses=1]
 	%tmp1042 = and i1 %tmp1037, %tmp1039		; <i1> [#uses=1]
 	ret i1 %tmp1042
 }
diff --git a/test/Transforms/InstCombine/2008-01-06-BitCastAttributes.ll b/test/Transforms/InstCombine/2008-01-06-BitCastAttributes.ll
index 23b6067..22c0782 100644
--- a/test/Transforms/InstCombine/2008-01-06-BitCastAttributes.ll
+++ b/test/Transforms/InstCombine/2008-01-06-BitCastAttributes.ll
@@ -1,23 +1,30 @@
 ; Ignore stderr, we expect warnings there
-; RUN: opt < %s -instcombine 2> /dev/null -S | not grep bitcast
+; RUN: opt < %s -instcombine 2> /dev/null -S | FileCheck %s
+
+; CHECK-NOT: bitcast
 
 define void @a() {
-	ret void
+  ret void
 }
 
 define signext i32 @b(i32* inreg  %x)   {
-	ret i32 0
+  ret i32 0
 }
 
 define void @c(...) {
-	ret void
+  ret void
 }
 
 define void @g(i32* %y) {
-	call void bitcast (void ()* @a to void (i32*)*)( i32* noalias  %y )
-	call <2 x i32> bitcast (i32 (i32*)* @b to <2 x i32> (i32*)*)( i32* inreg  null )		; <<2 x i32>>:1 [#uses=0]
+; CHECK-LABEL: @g(
+; CHECK: call i64 bitcast (i32 (i32*)* @b to i64 (i32)*)(i32 0)
 	%x = call i64 bitcast (i32 (i32*)* @b to i64 (i32)*)( i32 0 )		; <i64> [#uses=0]
-	call void bitcast (void (...)* @c to void (i32)*)( i32 0 )
-	call void bitcast (void (...)* @c to void (i32)*)( i32 zeroext  0 )
-	ret void
+
+; The rest should not have bitcasts remaining
+; CHECK-NOT: bitcast
+  call void bitcast (void ()* @a to void (i32*)*)( i32* noalias  %y )
+  call <2 x i32> bitcast (i32 (i32*)* @b to <2 x i32> (i32*)*)( i32* inreg  null )		; <<2 x i32>>:1 [#uses=0]
+  call void bitcast (void (...)* @c to void (i32)*)( i32 0 )
+  call void bitcast (void (...)* @c to void (i32)*)( i32 zeroext  0 )
+  ret void
 }
diff --git a/test/Transforms/InstCombine/2008-01-06-VoidCast.ll b/test/Transforms/InstCombine/2008-01-06-VoidCast.ll
index 407ff4d..5dcaa38 100644
--- a/test/Transforms/InstCombine/2008-01-06-VoidCast.ll
+++ b/test/Transforms/InstCombine/2008-01-06-VoidCast.ll
@@ -1,10 +1,12 @@
-; RUN: opt < %s -instcombine -S | not grep bitcast
+; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define void @f(i16 %y) {
-	ret void
+  ret void
 }
 
 define i32 @g(i32 %y) {
-	%x = call i32 bitcast (void (i16)* @f to i32 (i32)*)( i32 %y )		; <i32> [#uses=1]
-	ret i32 %x
+; CHECK-LABEL: @g(
+; CHECK: call i32 bitcast
+  %x = call i32 bitcast (void (i16)* @f to i32 (i32)*)( i32 %y )		; <i32> [#uses=1]
+  ret i32 %x
 }
diff --git a/test/Transforms/InstCombine/2008-11-20-DivMulRem.ll b/test/Transforms/InstCombine/2008-11-20-DivMulRem.ll
index 43af190..0c0e55a 100644
--- a/test/Transforms/InstCombine/2008-11-20-DivMulRem.ll
+++ b/test/Transforms/InstCombine/2008-11-20-DivMulRem.ll
@@ -2,7 +2,7 @@
 ; PR3103
 
 define i8 @test1(i8 %x, i8 %y) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
   %A = udiv i8 %x, %y
 ; CHECK-NEXT: urem
   %B = mul i8 %A, %y
@@ -12,7 +12,7 @@ define i8 @test1(i8 %x, i8 %y) {
 }
 
 define i8 @test2(i8 %x, i8 %y) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
   %A = sdiv i8 %x, %y
 ; CHECK-NEXT: srem
   %B = mul i8 %A, %y
@@ -22,7 +22,7 @@ define i8 @test2(i8 %x, i8 %y) {
 }
 
 define i8 @test3(i8 %x, i8 %y) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
   %A = udiv i8 %x, %y
 ; CHECK-NEXT: urem
   %B = mul i8 %A, %y
@@ -33,7 +33,7 @@ define i8 @test3(i8 %x, i8 %y) {
 }
 
 define i8 @test4(i8 %x) {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
   %A = udiv i8 %x, 3
 ; CHECK-NEXT: urem
   %B = mul i8 %A, -3
@@ -45,7 +45,7 @@ define i8 @test4(i8 %x) {
 }
 
 define i32 @test5(i32 %x, i32 %y) {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; (((X / Y) * Y) / Y) -> X / Y
   %div = sdiv i32 %x, %y
 ; CHECK-NEXT: sdiv
@@ -56,7 +56,7 @@ define i32 @test5(i32 %x, i32 %y) {
 }
 
 define i32 @test6(i32 %x, i32 %y) {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; (((X / Y) * Y) / Y) -> X / Y
   %div = udiv i32 %x, %y
 ; CHECK-NEXT: udiv
diff --git a/test/Transforms/InstCombine/2010-03-03-ExtElim.ll b/test/Transforms/InstCombine/2010-03-03-ExtElim.ll
index bb3159e..b1384ec 100644
--- a/test/Transforms/InstCombine/2010-03-03-ExtElim.ll
+++ b/test/Transforms/InstCombine/2010-03-03-ExtElim.ll
@@ -1,5 +1,4 @@
 ; RUN: opt -instcombine -S < %s | FileCheck %s
-; PR6486
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
 target triple = "i386-unknown-linux-gnu"
@@ -7,8 +6,8 @@ target triple = "i386-unknown-linux-gnu"
 @g_92 = common global [2 x i32*] zeroinitializer, align 4 ; <[2 x i32*]*> [#uses=1]
 @g_177 = constant i32** bitcast (i8* getelementptr (i8* bitcast ([2 x i32*]* @g_92 to i8*), i64 4) to i32**), align 4 ; <i32***> [#uses=1]
 
-define i1 @test() nounwind {
-; CHECK: @test
+define i1 @PR6486() nounwind {
+; CHECK-LABEL: @PR6486(
   %tmp = load i32*** @g_177                       ; <i32**> [#uses=1]
   %cmp = icmp ne i32** null, %tmp                 ; <i1> [#uses=1]
   %conv = zext i1 %cmp to i32                     ; <i32> [#uses=1]
@@ -16,3 +15,18 @@ define i1 @test() nounwind {
   ret i1 %cmp1
 ; CHECK: ret i1 true
 }
+
+@d = common global i32 0, align 4
+@a = common global [1 x i32] zeroinitializer, align 4
+
+define i1 @PR16462_1() nounwind {
+; CHECK-LABEL: @PR16462_1(
+  ret i1 icmp sgt (i32 sext (i16 trunc (i32 select (i1 icmp eq (i32* getelementptr inbounds ([1 x i32]* @a, i32 0, i32 0), i32* @d), i32 0, i32 1) to i16) to i32), i32 65535)
+; CHECK: ret i1 icmp sgt (i32 sext (i16 trunc (i32 select (i1 icmp eq (i32* getelementptr inbounds ([1 x i32]* @a, i32 0, i32 0), i32* @d), i32 0, i32 1) to i16) to i32), i32 65535)
+}
+
+define i1 @PR16462_2() nounwind {
+; CHECK-LABEL: @PR16462_2(
+  ret i1 icmp sgt (i32 sext (i16 trunc (i32 select (i1 icmp eq (i32* getelementptr inbounds ([1 x i32]* @a, i32 0, i32 0), i32* @d), i32 0, i32 1) to i16) to i32), i32 42)
+; CHECK: ret i1 icmp sgt (i16 trunc (i32 select (i1 icmp eq (i32* getelementptr inbounds ([1 x i32]* @a, i32 0, i32 0), i32* @d), i32 0, i32 1) to i16), i16 42)
+}
diff --git a/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll b/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll
index 8001621..1549c0d 100644
--- a/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll
+++ b/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll
@@ -1,7 +1,7 @@
 ; RUN: opt -instcombine -S < %s | FileCheck %s
 
 ; <rdar://problem/8606771>
-; CHECK: @main
+; CHECK-LABEL: @main(
 define i32 @main(i32 %argc) nounwind ssp {
 entry:
   %tmp3151 = trunc i32 %argc to i8
@@ -23,7 +23,7 @@ entry:
 }
 
 ; rdar://8739316
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 define i8 @foo(i8 %arg, i8 %arg1) nounwind {
 bb:
   %tmp = shl i8 %arg, 7
diff --git a/test/Transforms/InstCombine/2010-11-21-SizeZeroTypeGEP.ll b/test/Transforms/InstCombine/2010-11-21-SizeZeroTypeGEP.ll
index 720365c..80983ef 100644
--- a/test/Transforms/InstCombine/2010-11-21-SizeZeroTypeGEP.ll
+++ b/test/Transforms/InstCombine/2010-11-21-SizeZeroTypeGEP.ll
@@ -3,14 +3,14 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 
 define {}* @foo({}* %x, i32 %n) {
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK-NOT: getelementptr
   %p = getelementptr {}* %x, i32 %n
   ret {}* %p
 }
 
 define i8* @bar(i64 %n, {{}, [0 x {[0 x i8]}]}* %p) {
-; CHECK: @bar
+; CHECK-LABEL: @bar(
   %g = getelementptr {{}, [0 x {[0 x i8]}]}* %p, i64 %n, i32 1, i64 %n, i32 0, i64 %n
 ; CHECK: %p, i64 0, i32 1, i64 0, i32 0, i64 %n
   ret i8* %g
diff --git a/test/Transforms/InstCombine/2010-11-23-Distributed.ll b/test/Transforms/InstCombine/2010-11-23-Distributed.ll
index 4f8e8dc..20bfed8 100644
--- a/test/Transforms/InstCombine/2010-11-23-Distributed.ll
+++ b/test/Transforms/InstCombine/2010-11-23-Distributed.ll
@@ -1,6 +1,6 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 define i32 @foo(i32 %x, i32 %y) {
-; CHECK: @foo
+; CHECK-LABEL: @foo(
   %add = add nsw i32 %y, %x
   %mul = mul nsw i32 %add, %y
   %square = mul nsw i32 %y, %y
@@ -11,7 +11,7 @@ define i32 @foo(i32 %x, i32 %y) {
 }
 
 define i1 @bar(i64 %x, i64 %y) {
-; CHECK: @bar
+; CHECK-LABEL: @bar(
   %a = and i64 %y, %x
 ; CHECK: and
 ; CHECK-NOT: and
diff --git a/test/Transforms/InstCombine/2011-06-13-nsw-alloca.ll b/test/Transforms/InstCombine/2011-06-13-nsw-alloca.ll
index fedb46d..a75a465 100644
--- a/test/Transforms/InstCombine/2011-06-13-nsw-alloca.ll
+++ b/test/Transforms/InstCombine/2011-06-13-nsw-alloca.ll
@@ -2,7 +2,7 @@
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
 target triple = "i386-apple-darwin10.0.0"
 
-; CHECK: define void @fu1
+; CHECK-LABEL: define void @fu1(
 define void @fu1(i32 %parm) nounwind ssp {
   %1 = alloca i32, align 4
 ; CHECK: alloca double*
@@ -33,7 +33,7 @@ define void @fu1(i32 %parm) nounwind ssp {
 
 declare void @bar(double*)
 
-; CHECK: define void @fu2
+; CHECK-LABEL: define void @fu2(
 define void @fu2(i32 %parm) nounwind ssp {
   %1 = alloca i32, align 4
   %ptr = alloca double*, align 4
diff --git a/test/Transforms/InstCombine/2012-03-10-InstCombine.ll b/test/Transforms/InstCombine/2012-03-10-InstCombine.ll
index 58ccf12..d1860bc 100644
--- a/test/Transforms/InstCombine/2012-03-10-InstCombine.ll
+++ b/test/Transforms/InstCombine/2012-03-10-InstCombine.ll
@@ -2,7 +2,7 @@
 
 ; Derived from gcc.c-torture/execute/frame-address.c
 
-; CHECK:     @func
+; CHECK-LABEL:     @func(
 ; CHECK:     return:
 ; CHECK-NOT: ret i32 0
 ; CHECK:     ret i32 %retval
diff --git a/test/Transforms/InstCombine/2012-04-24-vselect.ll b/test/Transforms/InstCombine/2012-04-24-vselect.ll
index 8d2de2b..211d401 100644
--- a/test/Transforms/InstCombine/2012-04-24-vselect.ll
+++ b/test/Transforms/InstCombine/2012-04-24-vselect.ll
@@ -1,6 +1,6 @@
 ; RUN: opt -instcombine -S < %s | FileCheck %s
 
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK: <i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
 
 define <8 x i32> @foo() nounwind {
diff --git a/test/Transforms/InstCombine/2012-05-28-select-hang.ll b/test/Transforms/InstCombine/2012-05-28-select-hang.ll
index c580bac..db1dbd5 100644
--- a/test/Transforms/InstCombine/2012-05-28-select-hang.ll
+++ b/test/Transforms/InstCombine/2012-05-28-select-hang.ll
@@ -34,6 +34,6 @@ land.end:                                         ; preds = %land.rhs, %entry
   store i8 %conv9, i8* @a, align 1
   ret void
 
-; CHECK: @func
+; CHECK-LABEL: @func(
 ; CHECK-NOT: select
 }
diff --git a/test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll b/test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll
index 4efaf8c..0374bd5 100644
--- a/test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll
+++ b/test/Transforms/InstCombine/2012-08-28-udiv_ashl.ll
@@ -5,7 +5,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
-; CHECK: @udiv400
+; CHECK-LABEL: @udiv400(
 ; CHECK: udiv i32 %x, 400
 ; CHECK: ret
 define i32 @udiv400(i32 %x) {
@@ -16,7 +16,7 @@ entry:
 }
 
 
-; CHECK: @udiv400_no
+; CHECK-LABEL: @udiv400_no(
 ; CHECK: ashr
 ; CHECK: div
 ; CHECK: ret
@@ -27,7 +27,7 @@ entry:
   ret i32 %div1
 }
 
-; CHECK: @sdiv400_yes
+; CHECK-LABEL: @sdiv400_yes(
 ; CHECK: udiv i32 %x, 400
 ; CHECK: ret
 define i32 @sdiv400_yes(i32 %x) {
@@ -41,7 +41,7 @@ entry:
 }
 
 
-; CHECK: @udiv_i80
+; CHECK-LABEL: @udiv_i80(
 ; CHECK: udiv i80 %x, 400
 ; CHECK: ret
 define i80 @udiv_i80(i80 %x) {
diff --git a/test/Transforms/InstCombine/2012-09-17-ZeroSizedAlloca.ll b/test/Transforms/InstCombine/2012-09-17-ZeroSizedAlloca.ll
index ba025e9..7015725 100644
--- a/test/Transforms/InstCombine/2012-09-17-ZeroSizedAlloca.ll
+++ b/test/Transforms/InstCombine/2012-09-17-ZeroSizedAlloca.ll
@@ -9,7 +9,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
-; CHECK: @f
+; CHECK-LABEL: @f(
 ; CHECK-NEXT: alloca [0 x i8], align 1024
 ; CHECK-NOT: alloca
 ; CHECK: ret void
diff --git a/test/Transforms/InstCombine/2012-09-24-MemcpyFromGlobalCrash.ll b/test/Transforms/InstCombine/2012-09-24-MemcpyFromGlobalCrash.ll
index 4cd60b4..35b6285 100644
--- a/test/Transforms/InstCombine/2012-09-24-MemcpyFromGlobalCrash.ll
+++ b/test/Transforms/InstCombine/2012-09-24-MemcpyFromGlobalCrash.ll
@@ -8,7 +8,7 @@ declare void @bar(i8*)
 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
 
 define void @test() {
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK: llvm.memcpy
 ; CHECK: ret void
   %A = alloca [100 x i8]
diff --git a/test/Transforms/InstCombine/2012-3-15-or-xor-constant.ll b/test/Transforms/InstCombine/2012-3-15-or-xor-constant.ll
index c1602da..466629c 100644
--- a/test/Transforms/InstCombine/2012-3-15-or-xor-constant.ll
+++ b/test/Transforms/InstCombine/2012-3-15-or-xor-constant.ll
@@ -9,4 +9,4 @@ entry:
   %or4 = or i32 or (i32 zext (i1 icmp eq (i32* @g, i32* null) to i32), i32 1), %xor
   ret i32 %or4
 }
-; CHECK: define i32 @function
+; CHECK-LABEL: define i32 @function(
diff --git a/test/Transforms/InstCombine/2013-03-05-Combine-BitcastTy-Into-Alloca.ll b/test/Transforms/InstCombine/2013-03-05-Combine-BitcastTy-Into-Alloca.ll
index b20c3a0..789e317 100644
--- a/test/Transforms/InstCombine/2013-03-05-Combine-BitcastTy-Into-Alloca.ll
+++ b/test/Transforms/InstCombine/2013-03-05-Combine-BitcastTy-Into-Alloca.ll
@@ -10,7 +10,7 @@ target triple = "x86_64-apple-macosx10.9.0"
 ; allocation of an i96 because of the bitcast to create %2. That's not valid,
 ; as the other 32 bits of the structure still feed into the return value
 define { i64, i64 } @function(i32 %x, i32 %y, i32 %z) nounwind {
-; CHECK: @function
+; CHECK-LABEL: @function(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: %retval = alloca %struct._my_struct, align 8
 ; CHECK-NOT: bitcast i96* %retval to %struct._my_struct*
diff --git a/test/Transforms/InstCombine/ExtractCast.ll b/test/Transforms/InstCombine/ExtractCast.ll
index 5ebbefd..9a8872f 100644
--- a/test/Transforms/InstCombine/ExtractCast.ll
+++ b/test/Transforms/InstCombine/ExtractCast.ll
@@ -1,6 +1,6 @@
 ; RUN: opt < %s -instcombine -S -o - | FileCheck %s
 
-; CHECK: @a
+; CHECK-LABEL: @a(
 define i32 @a(<4 x i64> %I) {
 entry:
 ; CHECK-NOT: trunc <4 x i64>
@@ -13,7 +13,7 @@ entry:
 }
 
 
-; CHECK: @b
+; CHECK-LABEL: @b(
 define i32 @b(<4 x float> %I) {
 entry:
 ; CHECK-NOT: fptosi <4 x float>
diff --git a/test/Transforms/InstCombine/LandingPadClauses.ll b/test/Transforms/InstCombine/LandingPadClauses.ll
index de3b2d3..10af4bc 100644
--- a/test/Transforms/InstCombine/LandingPadClauses.ll
+++ b/test/Transforms/InstCombine/LandingPadClauses.ll
@@ -11,7 +11,7 @@ declare i32 @__objc_personality_v0(i32, i64, i8*, i8*)
 declare void @bar()
 
 define void @foo_generic() {
-; CHECK: @foo_generic
+; CHECK-LABEL: @foo_generic(
   invoke void @bar()
     to label %cont.a unwind label %lpad.a
 cont.a:
@@ -131,7 +131,7 @@ lpad.i:
 }
 
 define void @foo_cxx() {
-; CHECK: @foo_cxx
+; CHECK-LABEL: @foo_cxx(
   invoke void @bar()
     to label %cont.a unwind label %lpad.a
 cont.a:
@@ -182,7 +182,7 @@ lpad.d:
 }
 
 define void @foo_objc() {
-; CHECK: @foo_objc
+; CHECK-LABEL: @foo_objc(
   invoke void @bar()
     to label %cont.a unwind label %lpad.a
 cont.a:
diff --git a/test/Transforms/InstCombine/abs-1.ll b/test/Transforms/InstCombine/abs-1.ll
index 807f238..2c223ed 100644
--- a/test/Transforms/InstCombine/abs-1.ll
+++ b/test/Transforms/InstCombine/abs-1.ll
@@ -11,7 +11,7 @@ declare i64 @llabs(i64)
 ; Check abs(x) -> x >s -1 ? x : -x.
 
 define i32 @test_simplify1(i32 %x) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %ret = call i32 @abs(i32 %x)
 ; CHECK-NEXT: [[ISPOS:%[a-z0-9]+]] = icmp sgt i32 %x, -1
 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub i32 0, %x
@@ -21,7 +21,7 @@ define i32 @test_simplify1(i32 %x) {
 }
 
 define i64 @test_simplify2(i64 %x) {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %ret = call i64 @labs(i64 %x)
 ; CHECK-NEXT: [[ISPOS:%[a-z0-9]+]] = icmp sgt i64 %x, -1
 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub i64 0, %x
@@ -31,7 +31,7 @@ define i64 @test_simplify2(i64 %x) {
 }
 
 define i64 @test_simplify3(i64 %x) {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %ret = call i64 @llabs(i64 %x)
 ; CHECK-NEXT: [[ISPOS:%[a-z0-9]+]] = icmp sgt i64 %x, -1
 ; CHECK-NEXT: [[NEG:%[a-z0-9]+]] = sub i64 0, %x
diff --git a/test/Transforms/InstCombine/add2.ll b/test/Transforms/InstCombine/add2.ll
index c5109c5..0964bc0 100644
--- a/test/Transforms/InstCombine/add2.ll
+++ b/test/Transforms/InstCombine/add2.ll
@@ -6,7 +6,7 @@ define i64 @test1(i64 %A, i32 %B) {
         %tmp5 = add i64 %tmp3, %A
         %tmp6 = and i64 %tmp5, 123
         ret i64 %tmp6
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: and i64 %A, 123
 ; CHECK-NEXT: ret i64
 }
@@ -16,7 +16,7 @@ define i32 @test2(i32 %A) {
   %C = and i32 %A, 32
   %F = add i32 %B, %C
   ret i32 %F
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: and i32 %A, 39
 ; CHECK-NEXT: ret i32
 }
@@ -26,7 +26,7 @@ define i32 @test3(i32 %A) {
   %C = lshr i32 %A, 30
   %F = add i32 %B, %C
   ret i32 %F
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: and
 ; CHECK-NEXT: lshr
 ; CHECK-NEXT: or i32 %B, %C
@@ -36,7 +36,7 @@ define i32 @test3(i32 %A) {
 define i32 @test4(i32 %A) {
   %B = add nuw i32 %A, %A
   ret i32 %B
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: %B = shl nuw i32 %A, 1
 ; CHECK-NEXT: ret i32 %B
 }
diff --git a/test/Transforms/InstCombine/add4.ll b/test/Transforms/InstCombine/add4.ll
index 1047e16..208c7f0 100644
--- a/test/Transforms/InstCombine/add4.ll
+++ b/test/Transforms/InstCombine/add4.ll
@@ -1,22 +1,39 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
-;; Target triple for gep raising case below.
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
-target triple = "i686-apple-darwin8"
-
 define float @test1(float %A, float %B, i1 %C) {
 EntryBlock:
+  ;; A*(1 - uitofp i1 C) -> select C, 0, A
+  %cf = uitofp i1 %C to float
+  %mc = fsub float 1.000000e+00, %cf
+  %p1 = fmul fast float %A, %mc
+  ret float %p1
+; CHECK-LABEL: @test1(
+; CHECK: select i1 %C, float -0.000000e+00, float %A
+}
+
+define float @test2(float %A, float %B, i1 %C) {
+EntryBlock:
+  ;; B*(uitofp i1 C) -> select C, B, 0
+  %cf = uitofp i1 %C to float
+  %p2 = fmul fast float %B, %cf
+  ret float %p2
+; CHECK-LABEL: @test2(
+; CHECK: select i1 %C, float %B, float -0.000000e+00
+}
+
+define float @test3(float %A, float %B, i1 %C) {
+EntryBlock:
   ;;  select C, 0, B + select C, A, 0 -> select C, A, B
   %cf = uitofp i1 %C to float
   %s1 = select i1 %C, float 0.000000e+00, float %B
   %s2 = select i1 %C, float %A, float 0.000000e+00
   %sum = fadd fast float %s1, %s2
   ret float %sum
-; CHECK: @test1
+; CHECK-LABEL: @test3(
 ; CHECK: select i1 %C, float %A, float %B
 }
 
-define float @test2(float %A, float %B, i1 %C) {
+define float @test4(float %A, float %B, i1 %C) {
 EntryBlock:
   ;;  B*(uitofp i1 C) + A*(1 - uitofp i1 C) -> select C, A, B
   %cf = uitofp i1 %C to float
@@ -25,11 +42,11 @@ EntryBlock:
   %p2 = fmul fast float %B, %cf
   %s1 = fadd fast float %p2, %p1
   ret float %s1
-; CHECK: @test2
+; CHECK-LABEL: @test4(
 ; CHECK: select i1 %C, float %B, float %A
 }
 
-define float @test3(float %A, float %B, i1 %C) {
+define float @test5(float %A, float %B, i1 %C) {
 EntryBlock:
   ;; A*(1 - uitofp i1 C) + B*(uitofp i1 C) -> select C, A, B
   %cf = uitofp i1 %C to float
@@ -38,7 +55,25 @@ EntryBlock:
   %p2 = fmul fast float %B, %cf
   %s1 = fadd fast float %p1, %p2
   ret float %s1
-; CHECK: @test3
+; CHECK-LABEL: @test5(
 ; CHECK: select i1 %C, float %B, float %A
 }
 
+; PR15952
+define float @test6(float %A, float %B, i32 %C) {
+  %cf = uitofp i32 %C to float
+  %mc = fsub float 1.000000e+00, %cf
+  %p1 = fmul fast float %A, %mc
+  ret float %p1
+; CHECK-LABEL: @test6(
+; CHECK: uitofp
+}
+
+define float @test7(float %A, float %B, i32 %C) {
+  %cf = uitofp i32 %C to float
+  %p2 = fmul fast float %B, %cf
+  ret float %p2
+; CHECK-LABEL: @test7(
+; CHECK: uitofp
+}
+
diff --git a/test/Transforms/InstCombine/align-addr.ll b/test/Transforms/InstCombine/align-addr.ll
index 4ea1bd9..e33ee9f 100644
--- a/test/Transforms/InstCombine/align-addr.ll
+++ b/test/Transforms/InstCombine/align-addr.ll
@@ -4,7 +4,7 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1
 ; Instcombine should be able to prove vector alignment in the
 ; presence of a few mild address computation tricks.
 
-; CHECK: @test0(
+; CHECK-LABEL: @test0(
 ; CHECK: align 16
 
 define void @test0(i8* %b, i64 %n, i64 %u, i64 %y) nounwind  {
@@ -35,7 +35,7 @@ return:
 ; When we see a unaligned load from an insufficiently aligned global or
 ; alloca, increase the alignment of the load, turning it into an aligned load.
 
-; CHECK: @test1(
+; CHECK-LABEL: @test1(
 ; CHECK: tmp = load
 ; CHECK: GLOBAL{{.*}}align 16
 
@@ -49,7 +49,7 @@ entry:
 
 ; When a load or store lacks an explicit alignment, add one.
 
-; CHECK: @test2(
+; CHECK-LABEL: @test2(
 ; CHECK: load double* %p, align 8
 ; CHECK: store double %n, double* %p, align 8
 
@@ -67,7 +67,7 @@ declare void @use(i8*)
 
 define void @test3(%struct.s* sret %a4) {
 ; Check that the alignment is bumped up the alignment of the sret type.
-; CHECK: @test3
+; CHECK-LABEL: @test3(
   %a4.cast = bitcast %struct.s* %a4 to i8*
   call void @llvm.memset.p0i8.i64(i8* %a4.cast, i8 0, i64 16, i32 1, i1 false)
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %a4.cast, i8 0, i64 16, i32 4, i1 false)
diff --git a/test/Transforms/InstCombine/align-external.ll b/test/Transforms/InstCombine/align-external.ll
index c3ef2db..66ff9c1 100644
--- a/test/Transforms/InstCombine/align-external.ll
+++ b/test/Transforms/InstCombine/align-external.ll
@@ -22,7 +22,7 @@ define i64 @foo(i64 %a) {
 }
 
 define i32 @bar() {
-; CHECK: @bar
+; CHECK-LABEL: @bar(
   %r = load i32* @B, align 1
 ; CHECK: align 1
   ret i32 %r
diff --git a/test/Transforms/InstCombine/alloca.ll b/test/Transforms/InstCombine/alloca.ll
index 68a671c..9a80ad9 100644
--- a/test/Transforms/InstCombine/alloca.ll
+++ b/test/Transforms/InstCombine/alloca.ll
@@ -8,7 +8,7 @@ declare void @use(...)
 @int = global i32 zeroinitializer
 
 ; Zero byte allocas should be merged if they can't be deleted.
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK: alloca
 ; CHECK-NOT: alloca
 define void @test() {
@@ -25,7 +25,7 @@ define void @test() {
 }
 
 ; Zero byte allocas should be deleted.
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NOT: alloca
 define void @test2() {
         %A = alloca i32         ; <i32*> [#uses=1]
@@ -34,7 +34,7 @@ define void @test2() {
 }
 
 ; Zero byte allocas should be deleted.
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NOT: alloca
 define void @test3() {
         %A = alloca { i32 }             ; <{ i32 }*> [#uses=1]
@@ -43,7 +43,7 @@ define void @test3() {
         ret void
 }
 
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: = zext i32 %n to i64
 ; CHECK: %A = alloca i32, i64 %
 define i32* @test4(i32 %n) {
@@ -54,7 +54,7 @@ define i32* @test4(i32 %n) {
 ; Allocas which are only used by GEPs, bitcasts, and stores (transitively)
 ; should be deleted.
 define void @test5() {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NOT: alloca
 ; CHECK-NOT: store
 ; CHECK: ret
@@ -80,7 +80,7 @@ declare void @f(i32* %p)
 
 ; Check that we don't delete allocas in some erroneous cases.
 define void @test6() {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NOT: ret
 ; CHECK: alloca
 ; CHECK-NEXT: alloca
diff --git a/test/Transforms/InstCombine/and-xor-or.ll b/test/Transforms/InstCombine/and-xor-or.ll
index 7ff810b..ec36d13 100644
--- a/test/Transforms/InstCombine/and-xor-or.ll
+++ b/test/Transforms/InstCombine/and-xor-or.ll
@@ -7,7 +7,7 @@ define i64 @or(i64 %x, i64 %y) nounwind uwtable readnone ssp {
   %2 = xor i64 %y, %x
   %3 = add i64 %1, %2
   ret i64 %3
-; CHECK: @or
+; CHECK-LABEL: @or(
 ; CHECK: or i64
 ; CHECK-NEXT: ret
 }
@@ -18,7 +18,7 @@ define i64 @or2(i64 %x, i64 %y) nounwind uwtable readnone ssp {
   %2 = xor i64 %y, %x
   %3 = or i64 %1, %2
   ret i64 %3
-; CHECK: @or2
+; CHECK-LABEL: @or2(
 ; CHECK: or i64
 ; CHECK-NEXT: ret
 }
diff --git a/test/Transforms/InstCombine/and.ll b/test/Transforms/InstCombine/and.ll
index 8492df9..3d36bfb 100644
--- a/test/Transforms/InstCombine/and.ll
+++ b/test/Transforms/InstCombine/and.ll
@@ -186,9 +186,9 @@ define i1 @test25(i32 %A) {
 }
 
 define i1 @test26(i32 %A) {
-        %B = icmp ne i32 %A, 50         ; <i1> [#uses=1]
-        %C = icmp ne i32 %A, 51         ; <i1> [#uses=1]
-        ;; (A-50) > 1
+        %B = icmp ne i32 %A, 49         ; <i1> [#uses=1]
+        %C = icmp ne i32 %A, 50         ; <i1> [#uses=1]
+        ;; (A-49) > 1
         %D = and i1 %B, %C              ; <i1> [#uses=1]
         ret i1 %D
 }
diff --git a/test/Transforms/InstCombine/and2.ll b/test/Transforms/InstCombine/and2.ll
index 531aedb..504391a 100644
--- a/test/Transforms/InstCombine/and2.ll
+++ b/test/Transforms/InstCombine/and2.ll
@@ -13,7 +13,7 @@ define i1 @test2(i1 %X, i1 %Y) {
   %a = and i1 %X, %Y
   %b = and i1 %a, %X
   ret i1 %b
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: and i1 %X, %Y
 ; CHECK-NEXT: ret
 }
@@ -22,7 +22,7 @@ define i32 @test3(i32 %X, i32 %Y) {
   %a = and i32 %X, %Y
   %b = and i32 %Y, %a
   ret i32 %b
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: and i32 %X, %Y
 ; CHECK-NEXT: ret
 }
@@ -32,7 +32,7 @@ define i1 @test4(i32 %X) {
   %b = icmp slt i32 %X, 0
   %c = and i1 %a, %b
   ret i1 %c
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: ret i1 false
 }
 
diff --git a/test/Transforms/InstCombine/apint-call-cast-target.ll b/test/Transforms/InstCombine/apint-call-cast-target.ll
index fe336de..4e98f9b 100644
--- a/test/Transforms/InstCombine/apint-call-cast-target.ll
+++ b/test/Transforms/InstCombine/apint-call-cast-target.ll
@@ -1,16 +1,19 @@
-; RUN: opt < %s -instcombine -S | grep call | not grep bitcast
+; RUN: opt < %s -instcombine -S | FileCheck %s
 
 target datalayout = "e-p:32:32"
 target triple = "i686-pc-linux-gnu"
 
-
 define i32 @main() {
+; CHECK-LABEL: @main(
+; CHECK: call i32 bitcast
 entry:
 	%tmp = call i32 bitcast (i7* (i999*)* @ctime to i32 (i99*)*)( i99* null )
 	ret i32 %tmp
 }
 
 define i7* @ctime(i999*) {
+; CHECK-LABEL: @ctime(
+; CHECK: call i7* bitcast
 entry:
 	%tmp = call i7* bitcast (i32 ()* @main to i7* ()*)( )
 	ret i7* %tmp
diff --git a/test/Transforms/InstCombine/apint-shift-simplify.ll b/test/Transforms/InstCombine/apint-shift-simplify.ll
index 14e895a..63703ba 100644
--- a/test/Transforms/InstCombine/apint-shift-simplify.ll
+++ b/test/Transforms/InstCombine/apint-shift-simplify.ll
@@ -5,7 +5,7 @@ define i41 @test0(i41 %A, i41 %B, i41 %C) {
 	%Y = shl i41 %B, %C
 	%Z = and i41 %X, %Y
 	ret i41 %Z
-; CHECK: @test0
+; CHECK-LABEL: @test0(
 ; CHECK-NEXT: and i41 %A, %B
 ; CHECK-NEXT: shl i41
 ; CHECK-NEXT: ret
@@ -16,7 +16,7 @@ define i57 @test1(i57 %A, i57 %B, i57 %C) {
 	%Y = lshr i57 %B, %C
 	%Z = or i57 %X, %Y
 	ret i57 %Z
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: or i57 %A, %B
 ; CHECK-NEXT: lshr i57
 ; CHECK-NEXT: ret
@@ -27,7 +27,7 @@ define i49 @test2(i49 %A, i49 %B, i49 %C) {
 	%Y = ashr i49 %B, %C
 	%Z = xor i49 %X, %Y
 	ret i49 %Z
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: xor i49 %A, %B
 ; CHECK-NEXT: ashr i49
 ; CHECK-NEXT: ret
diff --git a/test/Transforms/InstCombine/apint-shift.ll b/test/Transforms/InstCombine/apint-shift.ll
index 73f630e..f5764c2 100644
--- a/test/Transforms/InstCombine/apint-shift.ll
+++ b/test/Transforms/InstCombine/apint-shift.ll
@@ -2,14 +2,14 @@
 ; even with arbitrary precision integers.
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NOT: sh
 define i47 @test1(i47 %A) {
 	%B = shl i47 %A, 0		; <i47> [#uses=1]
 	ret i47 %B
 }
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NOT: sh
 define i41 @test2(i7 %X) {
 	%A = zext i7 %X to i41		; <i41> [#uses=1]
@@ -17,14 +17,14 @@ define i41 @test2(i7 %X) {
 	ret i41 %B
 }
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NOT: sh
 define i41 @test3(i41 %A) {
 	%B = ashr i41 %A, 0		; <i41> [#uses=1]
 	ret i41 %B
 }
 
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NOT: sh
 define i39 @test4(i7 %X) {
 	%A = zext i7 %X to i39		; <i39> [#uses=1]
@@ -32,21 +32,21 @@ define i39 @test4(i7 %X) {
 	ret i39 %B
 }
 
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NOT: sh
 define i55 @test5(i55 %A) {
 	%B = lshr i55 %A, 55		; <i55> [#uses=1]
 	ret i55 %B
 }
 
-; CHECK: @test5a
+; CHECK-LABEL: @test5a(
 ; CHECK-NOT: sh
 define i32 @test5a(i32 %A) {
 	%B = shl i32 %A, 32		; <i32> [#uses=1]
 	ret i32 %B
 }
 
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: mul i55 %A, 6
 define i55 @test6(i55 %A) {
 	%B = shl i55 %A, 1		; <i55> [#uses=1]
@@ -54,7 +54,7 @@ define i55 @test6(i55 %A) {
 	ret i55 %C
 }
 
-; CHECK: @test6a
+; CHECK-LABEL: @test6a(
 ; CHECK: mul i55 %A, 6
 define i55 @test6a(i55 %A) {
 	%B = mul i55 %A, 3		; <i55> [#uses=1]
@@ -62,7 +62,7 @@ define i55 @test6a(i55 %A) {
 	ret i55 %C
 }
 
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NOT: sh
 define i29 @test7(i8 %X) {
 	%A = zext i8 %X to i29		; <i29> [#uses=1]
@@ -70,7 +70,7 @@ define i29 @test7(i8 %X) {
 	ret i29 %B
 }
 
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK-NOT: sh
 define i7 @test8(i7 %A) {
 	%B = shl i7 %A, 4		; <i7> [#uses=1]
@@ -78,7 +78,7 @@ define i7 @test8(i7 %A) {
 	ret i7 %C
 }
 
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NOT: sh
 define i17 @test9(i17 %A) {
 	%B = shl i17 %A, 16		; <i17> [#uses=1]
@@ -86,7 +86,7 @@ define i17 @test9(i17 %A) {
 	ret i17 %C
 }
 
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK-NOT: sh
 define i19 @test10(i19 %A) {
 	%B = lshr i19 %A, 18		; <i19> [#uses=1]
@@ -94,7 +94,7 @@ define i19 @test10(i19 %A) {
 	ret i19 %C
 }
 
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; Don't hide the shl from scalar evolution. DAGCombine will get it.
 ; CHECK: shl
 define i23 @test11(i23 %A) {
@@ -104,7 +104,7 @@ define i23 @test11(i23 %A) {
 	ret i23 %C
 }
 
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK-NOT: sh
 define i47 @test12(i47 %A) {
 	%B = ashr i47 %A, 8		; <i47> [#uses=1]
@@ -112,7 +112,7 @@ define i47 @test12(i47 %A) {
 	ret i47 %C
 }
 
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; Don't hide the shl from scalar evolution. DAGCombine will get it.
 ; CHECK: shl
 define i18 @test13(i18 %A) {
@@ -122,7 +122,7 @@ define i18 @test13(i18 %A) {
 	ret i18 %C
 }
 
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK-NOT: sh
 define i35 @test14(i35 %A) {
 	%B = lshr i35 %A, 4		; <i35> [#uses=1]
@@ -131,7 +131,7 @@ define i35 @test14(i35 %A) {
 	ret i35 %D
 }
 
-; CHECK: @test14a
+; CHECK-LABEL: @test14a(
 ; CHECK-NOT: sh
 define i79 @test14a(i79 %A) {
 	%B = shl i79 %A, 4		; <i79> [#uses=1]
@@ -140,7 +140,7 @@ define i79 @test14a(i79 %A) {
 	ret i79 %D
 }
 
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 ; CHECK-NOT: sh
 define i45 @test15(i1 %C) {
 	%A = select i1 %C, i45 3, i45 1	; <i45> [#uses=1]
@@ -148,7 +148,7 @@ define i45 @test15(i1 %C) {
 	ret i45 %V
 }
 
-; CHECK: @test15a
+; CHECK-LABEL: @test15a(
 ; CHECK-NOT: sh
 define i53 @test15a(i1 %X) {
 	%A = select i1 %X, i8 3, i8 1	; <i8> [#uses=1]
@@ -157,7 +157,7 @@ define i53 @test15a(i1 %X) {
 	ret i53 %V
 }
 
-; CHECK: @test16
+; CHECK-LABEL: @test16(
 ; CHECK-NOT: sh
 define i1 @test16(i84 %X) {
 	%tmp.3 = ashr i84 %X, 4		; <i84> [#uses=1]
@@ -166,7 +166,7 @@ define i1 @test16(i84 %X) {
 	ret i1 %tmp.7
 }
 
-; CHECK: @test17
+; CHECK-LABEL: @test17(
 ; CHECK-NOT: sh
 define i1 @test17(i106 %A) {
 	%B = lshr i106 %A, 3		; <i106> [#uses=1]
@@ -174,7 +174,7 @@ define i1 @test17(i106 %A) {
 	ret i1 %C
 }
 
-; CHECK: @test18
+; CHECK-LABEL: @test18(
 ; CHECK-NOT: sh
 define i1 @test18(i11 %A) {
 	%B = lshr i11 %A, 10		; <i11> [#uses=1]
@@ -182,7 +182,7 @@ define i1 @test18(i11 %A) {
 	ret i1 %C
 }
 
-; CHECK: @test19
+; CHECK-LABEL: @test19(
 ; CHECK-NOT: sh
 define i1 @test19(i37 %A) {
 	%B = ashr i37 %A, 2		; <i37> [#uses=1]
@@ -190,7 +190,7 @@ define i1 @test19(i37 %A) {
 	ret i1 %C
 }
 
-; CHECK: @test19a
+; CHECK-LABEL: @test19a(
 ; CHECK-NOT: sh
 define i1 @test19a(i39 %A) {
 	%B = ashr i39 %A, 2		; <i39> [#uses=1]
@@ -198,7 +198,7 @@ define i1 @test19a(i39 %A) {
 	ret i1 %C
 }
 
-; CHECK: @test20
+; CHECK-LABEL: @test20(
 ; CHECK-NOT: sh
 define i1 @test20(i13 %A) {
 	%B = ashr i13 %A, 12		; <i13> [#uses=1]
@@ -206,7 +206,7 @@ define i1 @test20(i13 %A) {
 	ret i1 %C
 }
 
-; CHECK: @test21
+; CHECK-LABEL: @test21(
 ; CHECK-NOT: sh
 define i1 @test21(i12 %A) {
 	%B = shl i12 %A, 6		; <i12> [#uses=1]
@@ -214,7 +214,7 @@ define i1 @test21(i12 %A) {
 	ret i1 %C
 }
 
-; CHECK: @test22
+; CHECK-LABEL: @test22(
 ; CHECK-NOT: sh
 define i1 @test22(i14 %A) {
 	%B = shl i14 %A, 7		; <i14> [#uses=1]
@@ -222,7 +222,7 @@ define i1 @test22(i14 %A) {
 	ret i1 %C
 }
 
-; CHECK: @test23
+; CHECK-LABEL: @test23(
 ; CHECK-NOT: sh
 define i11 @test23(i44 %A) {
 	%B = shl i44 %A, 33		; <i44> [#uses=1]
@@ -231,7 +231,7 @@ define i11 @test23(i44 %A) {
 	ret i11 %D
 }
 
-; CHECK: @test25
+; CHECK-LABEL: @test25(
 ; CHECK-NOT: sh
 define i37 @test25(i37 %tmp.2, i37 %AA) {
 	%x = lshr i37 %AA, 17		; <i37> [#uses=1]
@@ -241,7 +241,7 @@ define i37 @test25(i37 %tmp.2, i37 %AA) {
 	ret i37 %tmp.6
 }
 
-; CHECK: @test26
+; CHECK-LABEL: @test26(
 ; CHECK-NOT: sh
 define i40 @test26(i40 %A) {
 	%B = lshr i40 %A, 1		; <i40> [#uses=1]
diff --git a/test/Transforms/InstCombine/apint-shl-trunc.ll b/test/Transforms/InstCombine/apint-shl-trunc.ll
index f2dc7d5..b4450d4 100644
--- a/test/Transforms/InstCombine/apint-shl-trunc.ll
+++ b/test/Transforms/InstCombine/apint-shl-trunc.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i1 @test0(i39 %X, i39 %A) {
-; CHECK: @test0
+; CHECK-LABEL: @test0(
 ; CHECK: %[[V1:.*]] = shl i39 1, %A
 ; CHECK: %[[V2:.*]] = and i39 %[[V1]], %X
 ; CHECK: %[[V3:.*]] = icmp ne i39 %[[V2]], 0
@@ -13,7 +13,7 @@ define i1 @test0(i39 %X, i39 %A) {
 }
 
 define i1 @test1(i799 %X, i799 %A) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %[[V1:.*]] = shl i799 1, %A
 ; CHECK: %[[V2:.*]] = and i799 %[[V1]], %X
 ; CHECK: %[[V3:.*]] = icmp ne i799 %[[V2]], 0
diff --git a/test/Transforms/InstCombine/atomic.ll b/test/Transforms/InstCombine/atomic.ll
index 097cf5e..ccee874 100644
--- a/test/Transforms/InstCombine/atomic.ll
+++ b/test/Transforms/InstCombine/atomic.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-apple-macosx10.7.0"
 ; Check transforms involving atomic operations
 
 define i32* @test1(i8** %p) {
-; CHECK: define i32* @test1
+; CHECK-LABEL: define i32* @test1(
 ; CHECK: load atomic i8** %p monotonic, align 8
   %c = bitcast i8** %p to i32**
   %r = load atomic i32** %c monotonic, align 8
@@ -14,7 +14,7 @@ define i32* @test1(i8** %p) {
 }
 
 define i32 @test2(i32* %p) {
-; CHECK: define i32 @test2
+; CHECK-LABEL: define i32 @test2(
 ; CHECK: %x = load atomic i32* %p seq_cst, align 4
 ; CHECK: shl i32 %x, 1
   %x = load atomic i32* %p seq_cst, align 4
diff --git a/test/Transforms/InstCombine/badmalloc.ll b/test/Transforms/InstCombine/badmalloc.ll
index 3abe28a..2074d26 100644
--- a/test/Transforms/InstCombine/badmalloc.ll
+++ b/test/Transforms/InstCombine/badmalloc.ll
@@ -15,11 +15,11 @@ define i1 @test1() {
   call void @free(i8* %A)
   ret i1 %B
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret i1 false
 }
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 define noalias i8* @test2() nounwind {
 entry:
 ; CHECK: @malloc
diff --git a/test/Transforms/InstCombine/bitcast-alias-function.ll b/test/Transforms/InstCombine/bitcast-alias-function.ll
new file mode 100644
index 0000000..a6b56f9
--- /dev/null
+++ b/test/Transforms/InstCombine/bitcast-alias-function.ll
@@ -0,0 +1,229 @@
+; RUN: opt -S -instcombine -o - %s | FileCheck %s
+target datalayout = "e-p:32:32:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v64:64:64-v128:128:128-a0:0:64"
+
+
+
+; Cases that should be bitcast
+
+; Test cast between scalars with same bit sizes
+@alias_i32_to_f32 = alias bitcast (i32 (i32)* @func_i32 to float (float)*)
+
+; Test cast between vectors with same number of elements and bit sizes
+@alias_v2i32_to_v2f32 = alias bitcast (<2 x i32> (<2 x i32>)* @func_v2i32 to <2 x float> (<2 x float>)*)
+
+; Test cast from vector to scalar with same number of bits
+@alias_v2f32_to_i64 = alias bitcast (i64 (i64)* @func_i64 to <2 x float> (<2 x float>)*)
+
+; Test cast from scalar to vector with same number of bits
+@alias_i64_to_v2f32 = alias bitcast (<2 x float> (<2 x float>)* @func_v2f32 to i64 (i64)*)
+
+; Test cast between vectors of pointers
+@alias_v2i32p_to_v2i64p = alias bitcast (<2 x i32*> (<2 x i32*>)* @func_v2i32p to <2 x i64*> (<2 x i64*>)*)
+
+
+; Cases that should be invalid and unchanged
+
+; Test cast between scalars with different bit sizes
+@alias_i64_to_f32 = alias bitcast (i64 (i64)* @func_i64 to float (float)*)
+
+; Test cast between vectors with different bit sizes but the
+; same number of elements
+@alias_v2i64_to_v2f32 = alias bitcast (<2 x i64> (<2 x i64>)* @func_v2i64 to <2 x float> (<2 x float>)*)
+
+; Test cast between vectors with same number of bits and different
+; numbers of elements
+@alias_v2i32_to_v4f32 = alias bitcast (<2 x i32> (<2 x i32>)* @func_v2i32 to <4 x float> (<4 x float>)*)
+
+; Test cast between scalar and vector with different number of bits
+@alias_i64_to_v4f32 = alias bitcast (<4 x float> (<4 x float>)* @func_v4f32 to i64 (i64)*)
+
+; Test cast between vector and scalar with different number of bits
+@alias_v4f32_to_i64 = alias bitcast (i64 (i64)* @func_i64 to <4 x float> (<4 x float>)*)
+
+; Test cast from scalar to vector of pointers with same number of bits
+; We don't know the pointer size at this point, so this can't be done
+@alias_i64_to_v2i32p = alias bitcast (<2 x i32*> (<2 x i32*>)* @func_v2i32p to i64 (i64)*)
+
+; Test cast between vector of pointers and scalar with different number of bits
+@alias_v4i32p_to_i64 = alias bitcast (i64 (i64)* @func_i64 to <4 x i32*> (<4 x i32*>)*)
+
+
+
+define internal <2 x i32> @func_v2i32(<2 x i32> %v) noinline nounwind {
+entry:
+  ret <2 x i32> %v
+}
+
+define internal <2 x float> @func_v2f32(<2 x float> %v) noinline nounwind {
+entry:
+  ret <2 x float> %v
+}
+
+define internal <4 x float> @func_v4f32(<4 x float> %v) noinline nounwind {
+entry:
+  ret <4 x float> %v
+}
+
+define internal i32 @func_i32(i32 %v) noinline nounwind {
+entry:
+  ret i32 %v
+}
+
+define internal i64 @func_i64(i64 %v) noinline nounwind {
+entry:
+  ret i64 %v
+}
+
+define internal <2 x i64> @func_v2i64(<2 x i64> %v) noinline nounwind {
+entry:
+  ret <2 x i64> %v
+}
+
+define internal <2 x i32*> @func_v2i32p(<2 x i32*> %v) noinline nounwind {
+entry:
+  ret <2 x i32*> %v
+}
+
+; Valid cases, only bitcast for argument / return type and call underlying function
+
+; Sizes match, should only bitcast
+define void @bitcast_alias_scalar(float* noalias %source, float* noalias %dest) nounwind {
+entry:
+; CHECK-LABEL: @bitcast_alias_scalar
+; CHECK: bitcast float %tmp to i32
+; CHECK-NOT: fptoui
+; CHECK-NOT: uitofp
+; CHECK: bitcast i32 %call to float
+  %tmp = load float* %source, align 8
+  %call = call float @alias_i32_to_f32(float %tmp) nounwind
+  store float %call, float* %dest, align 8
+  ret void
+}
+
+; Sizes match, should only bitcast
+define void @bitcast_alias_vector(<2 x float>* noalias %source, <2 x float>* noalias %dest) nounwind {
+entry:
+; CHECK-LABEL: @bitcast_alias_vector
+; CHECK: bitcast <2 x float> %tmp to <2 x i32>
+; CHECK-NOT: fptoui
+; CHECK-NOT: uitofp
+; CHECK: bitcast <2 x i32> %call to <2 x float>
+  %tmp = load <2 x float>* %source, align 8
+  %call = call <2 x float> @alias_v2i32_to_v2f32(<2 x float> %tmp) nounwind
+  store <2 x float> %call, <2 x float>* %dest, align 8
+  ret void
+}
+
+; Sizes match, should only bitcast
+define void @bitcast_alias_vector_scalar_same_size(<2 x float>* noalias %source, <2 x float>* noalias %dest) nounwind {
+entry:
+; CHECK-LABEL: @bitcast_alias_vector_scalar_same_size
+; CHECK: bitcast <2 x float> %tmp to i64
+; CHECK: %call = call i64 @func_i64
+; CHECK: bitcast i64 %call to <2 x float>
+  %tmp = load <2 x float>* %source, align 8
+  %call = call <2 x float> @alias_v2f32_to_i64(<2 x float> %tmp) nounwind
+  store <2 x float> %call, <2 x float>* %dest, align 8
+  ret void
+}
+
+define void @bitcast_alias_scalar_vector_same_size(i64* noalias %source, i64* noalias %dest) nounwind {
+entry:
+; CHECK-LABEL: @bitcast_alias_scalar_vector_same_size
+; CHECK: bitcast i64 %tmp to <2 x float>
+; CHECK: call <2 x float> @func_v2f32
+; CHECK: bitcast <2 x float> %call to i64
+  %tmp = load i64* %source, align 8
+  %call = call i64 @alias_i64_to_v2f32(i64 %tmp) nounwind
+  store i64 %call, i64* %dest, align 8
+  ret void
+}
+
+define void @bitcast_alias_vector_ptrs_same_size(<2 x i64*>* noalias %source, <2 x i64*>* noalias %dest) nounwind {
+entry:
+; CHECK-LABEL: @bitcast_alias_vector_ptrs_same_size
+; CHECK: bitcast <2 x i64*> %tmp to <2 x i32*>
+; CHECK: call <2 x i32*> @func_v2i32p
+; CHECK: bitcast <2 x i32*> %call to <2 x i64*>
+  %tmp = load <2 x i64*>* %source, align 8
+  %call = call <2 x i64*> @alias_v2i32p_to_v2i64p(<2 x i64*> %tmp) nounwind
+  store <2 x i64*> %call, <2 x i64*>* %dest, align 8
+  ret void
+}
+
+; Invalid cases:
+
+define void @bitcast_alias_mismatch_scalar_size(float* noalias %source, float* noalias %dest) nounwind {
+entry:
+; CHECK-LABEL: @bitcast_alias_mismatch_scalar_size
+; CHECK-NOT: fptoui
+; CHECK: @alias_i64_to_f32
+; CHECK-NOT: uitofp
+  %tmp = load float* %source, align 8
+  %call = call float @alias_i64_to_f32(float %tmp) nounwind
+  store float %call, float* %dest, align 8
+  ret void
+}
+
+define void @bitcast_alias_mismatch_vector_element_and_bit_size(<2 x float>* noalias %source, <2 x float>* noalias %dest) nounwind {
+entry:
+; CHECK-LABEL: @bitcast_alias_mismatch_vector_element_and_bit_size
+; CHECK-NOT: fptoui <2 x float> %tmp to <2 x i64>
+; CHECK: @alias_v2i64_to_v2f32
+; CHECK-NOT: uitofp <2 x i64> %call to <2 x float>
+  %tmp = load <2 x float>* %source, align 8
+  %call = call <2 x float> @alias_v2i64_to_v2f32(<2 x float> %tmp) nounwind
+  store <2 x float> %call, <2 x float>* %dest, align 8
+  ret void
+}
+
+define void @bitcast_alias_vector_mismatched_number_elements(<4 x float>* noalias %source, <4 x float>* noalias %dest) nounwind {
+entry:
+; CHECK-LABEL: @bitcast_alias_vector_mismatched_number_elements
+; CHECK:  %call = call <4 x float> @alias_v2i32_to_v4f32
+  %tmp = load <4 x float>* %source, align 8
+  %call = call <4 x float> @alias_v2i32_to_v4f32(<4 x float> %tmp) nounwind
+  store <4 x float> %call, <4 x float>* %dest, align 8
+  ret void
+}
+
+define void @bitcast_alias_vector_scalar_mismatched_bit_size(<4 x float>* noalias %source, <4 x float>* noalias %dest) nounwind {
+entry:
+; CHECK-LABEL: @bitcast_alias_vector_scalar_mismatched_bit_size
+; CHECK:  %call = call <4 x float> @alias_v4f32_to_i64
+  %tmp = load <4 x float>* %source, align 8
+  %call = call <4 x float> @alias_v4f32_to_i64(<4 x float> %tmp) nounwind
+  store <4 x float> %call, <4 x float>* %dest, align 8
+  ret void
+}
+
+define void @bitcast_alias_vector_ptrs_scalar_mismatched_bit_size(<4 x i32*>* noalias %source, <4 x i32*>* noalias %dest) nounwind {
+entry:
+; CHECK-LABEL: @bitcast_alias_vector_ptrs_scalar_mismatched_bit_size
+; CHECK: @alias_v4i32p_to_i64
+  %tmp = load <4 x i32*>* %source, align 8
+  %call = call <4 x i32*> @alias_v4i32p_to_i64(<4 x i32*> %tmp) nounwind
+  store <4 x i32*> %call, <4 x i32*>* %dest, align 8
+  ret void
+}
+
+define void @bitcast_alias_scalar_vector_ptrs_same_size(i64* noalias %source, i64* noalias %dest) nounwind {
+entry:
+; CHECK-LABEL: @bitcast_alias_scalar_vector_ptrs_same_size
+; CHECK: @alias_i64_to_v2i32p
+  %tmp = load i64* %source, align 8
+  %call = call i64 @alias_i64_to_v2i32p(i64 %tmp) nounwind
+  store i64 %call, i64* %dest, align 8
+  ret void
+}
+
+define void @bitcast_alias_scalar_vector_mismatched_bit_size(i64* noalias %source, i64* noalias %dest) nounwind {
+entry:
+; CHECK-LABEL: @bitcast_alias_scalar_vector_mismatched_bit_size
+; CHECK: call i64 @alias_i64_to_v4f32
+  %tmp = load i64* %source, align 8
+  %call = call i64 @alias_i64_to_v4f32(i64 %tmp) nounwind
+  store i64 %call, i64* %dest, align 8
+  ret void
+}
+
diff --git a/test/Transforms/InstCombine/bitcast-bigendian.ll b/test/Transforms/InstCombine/bitcast-bigendian.ll
index 4ded581..28b0e9a 100644
--- a/test/Transforms/InstCombine/bitcast-bigendian.ll
+++ b/test/Transforms/InstCombine/bitcast-bigendian.ll
@@ -18,7 +18,7 @@ define float @test2(<2 x float> %A, <2 x i32> %B) {
   %add = fadd float %tmp24, %tmp4
   ret float %add
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  %tmp24 = extractelement <2 x float> %A, i32 1
 ; CHECK-NEXT:  bitcast <2 x i32> %B to <2 x float>
 ; CHECK-NEXT:  %tmp4 = extractelement <2 x float> {{.*}}, i32 1
@@ -40,7 +40,7 @@ define float @test3(<2 x float> %A, <2 x i64> %B) {
   %add = fadd float %tmp24, %tmp4
   ret float %add
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT:  %tmp24 = extractelement <2 x float> %A, i32 0
 ; CHECK-NEXT:  bitcast <2 x i64> %B to <4 x float>
 ; CHECK-NEXT:  %tmp4 = extractelement <4 x float> {{.*}}, i32 1
diff --git a/test/Transforms/InstCombine/bitcast-vec-uniform.ll b/test/Transforms/InstCombine/bitcast-vec-uniform.ll
index 5975f1e..bfb7719 100644
--- a/test/Transforms/InstCombine/bitcast-vec-uniform.ll
+++ b/test/Transforms/InstCombine/bitcast-vec-uniform.ll
@@ -1,6 +1,6 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
-; CHECK: @a
+; CHECK-LABEL: @a(
 ; CHECK-NOT: bitcast
 ; CHECK: ret
 define <4 x i32> @a(<1 x i64> %y) {
@@ -8,7 +8,7 @@ define <4 x i32> @a(<1 x i64> %y) {
   ret <4 x i32> %c
 }
 
-; CHECK: @b
+; CHECK-LABEL: @b(
 ; CHECK-NOT: bitcast
 ; CHECK: ret
 
@@ -17,7 +17,7 @@ define <4 x i32> @b(<1 x i64> %y) {
   ret <4 x i32> %c
 }
 
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK-NOT: bitcast
 ; CHECK: ret
 
@@ -28,7 +28,7 @@ define <2 x float> @foo() {
 }
 
 
-; CHECK: @foo2
+; CHECK-LABEL: @foo2(
 ; CHECK-NOT: bitcast
 ; CHECK: ret
 define <2 x double> @foo2() {
@@ -36,7 +36,7 @@ define <2 x double> @foo2() {
   ret <2 x double> %cast
 }
 
-; CHECK: @foo3
+; CHECK-LABEL: @foo3(
 ; CHECK-NOT: bitcast
 ; CHECK: ret
 define <1 x float> @foo3() {
@@ -44,7 +44,7 @@ define <1 x float> @foo3() {
   ret <1 x float> %cast
 }
 
-; CHECK: @foo4
+; CHECK-LABEL: @foo4(
 ; CHECK-NOT: bitcast
 ; CHECK: ret
 define float @foo4() {
@@ -52,7 +52,7 @@ define float @foo4() {
   ret float %cast
 }
 
-; CHECK: @foo5
+; CHECK-LABEL: @foo5(
 ; CHECK-NOT: bitcast
 ; CHECK: ret
 define double @foo5() {
@@ -61,7 +61,7 @@ define double @foo5() {
 }
 
 
-; CHECK: @foo6
+; CHECK-LABEL: @foo6(
 ; CHECK-NOT: bitcast
 ; CHECK: ret
 define <2 x double> @foo6() {
diff --git a/test/Transforms/InstCombine/bitcast-vector-fold.ll b/test/Transforms/InstCombine/bitcast-vector-fold.ll
index 8fd7f35..04c2861 100644
--- a/test/Transforms/InstCombine/bitcast-vector-fold.ll
+++ b/test/Transforms/InstCombine/bitcast-vector-fold.ll
@@ -35,4 +35,4 @@ define <4 x i32> @test6() {
 define i32 @test7() {
        %tmp3 = bitcast <2 x half> <half 0xH1100, half 0xH0011> to i32
        ret i32 %tmp3
-}
\ No newline at end of file
+}
diff --git a/test/Transforms/InstCombine/bitcast.ll b/test/Transforms/InstCombine/bitcast.ll
index 1e61132..4ef8790 100644
--- a/test/Transforms/InstCombine/bitcast.ll
+++ b/test/Transforms/InstCombine/bitcast.ll
@@ -12,7 +12,7 @@ define i32 @test1(i64 %a) {
         %t4 = extractelement <2 x i32> %t3, i32 0
         ret i32 %t4
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret i32 0
 }
 
@@ -31,7 +31,7 @@ define float @test2(<2 x float> %A, <2 x i32> %B) {
   %add = fadd float %tmp24, %tmp4
   ret float %add
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  %tmp24 = extractelement <2 x float> %A, i32 0
 ; CHECK-NEXT:  bitcast <2 x i32> %B to <2 x float>
 ; CHECK-NEXT:  %tmp4 = extractelement <2 x float> {{.*}}, i32 0
@@ -56,7 +56,7 @@ define float @test3(<2 x float> %A, <2 x i64> %B) {
   %add = fadd float %tmp24, %tmp4
   ret float %add
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT:  %tmp24 = extractelement <2 x float> %A, i32 1
 ; CHECK-NEXT:  bitcast <2 x i64> %B to <4 x float>
 ; CHECK-NEXT:  %tmp4 = extractelement <4 x float> {{.*}}, i32 2
@@ -72,7 +72,7 @@ define <2 x i32> @test4(i32 %A, i32 %B){
   %ins35 = or i64 %tmp33, %tmp38
   %tmp43 = bitcast i64 %ins35 to <2 x i32>
   ret <2 x i32> %tmp43
-  ; CHECK: @test4
+  ; CHECK-LABEL: @test4(
   ; CHECK-NEXT: insertelement <2 x i32> undef, i32 %A, i32 0
   ; CHECK-NEXT: insertelement <2 x i32> {{.*}}, i32 %B, i32 1
   ; CHECK-NEXT: ret <2 x i32>
@@ -89,7 +89,7 @@ define <2 x float> @test5(float %A, float %B) {
   %ins35 = or i64 %tmp33, %tmp38
   %tmp43 = bitcast i64 %ins35 to <2 x float>
   ret <2 x float> %tmp43
-  ; CHECK: @test5
+  ; CHECK-LABEL: @test5(
   ; CHECK-NEXT: insertelement <2 x float> undef, float %A, i32 0
   ; CHECK-NEXT: insertelement <2 x float> {{.*}}, float %B, i32 1
   ; CHECK-NEXT: ret <2 x float>
@@ -102,7 +102,7 @@ define <2 x float> @test6(float %A){
   %mask20 = or i64 %tmp25, 1109917696             ; <i64> [#uses=1]
   %tmp35 = bitcast i64 %mask20 to <2 x float>     ; <<2 x float>> [#uses=1]
   ret <2 x float> %tmp35
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: insertelement <2 x float> <float 4.200000e+01, float undef>, float %A, i32 1
 ; CHECK: ret
 }
@@ -110,7 +110,7 @@ define <2 x float> @test6(float %A){
 define i64 @ISPC0(i64 %in) {
   %out = and i64 %in, xor (i64 bitcast (<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1> to i64), i64 -1)
   ret i64 %out
-; CHECK: @ISPC0
+; CHECK-LABEL: @ISPC0(
 ; CHECK: ret i64 0
 }
 
@@ -118,14 +118,14 @@ define i64 @ISPC0(i64 %in) {
 define i64 @Vec2(i64 %in) {
   %out = and i64 %in, xor (i64 bitcast (<4 x i16> <i16 0, i16 0, i16 0, i16 0> to i64), i64 0)
   ret i64 %out
-; CHECK: @Vec2
+; CHECK-LABEL: @Vec2(
 ; CHECK: ret i64 0
 }
 
 define i64 @All11(i64 %in) {
   %out = and i64 %in, xor (i64 bitcast (<2 x float> bitcast (i64 -1 to <2 x float>) to i64), i64 -1)
   ret i64 %out
-; CHECK: @All11
+; CHECK-LABEL: @All11(
 ; CHECK: ret i64 0
 }
 
@@ -133,7 +133,7 @@ define i64 @All11(i64 %in) {
 define i32 @All111(i32 %in) {
   %out = and i32 %in, xor (i32 bitcast (<1 x float> bitcast (i32 -1 to <1 x float>) to i32), i32 -1)
   ret i32 %out
-; CHECK: @All111
+; CHECK-LABEL: @All111(
 ; CHECK: ret i32 0
 }
 
@@ -141,6 +141,6 @@ define <2 x i16> @BitcastInsert(i32 %a) {
   %v = insertelement <1 x i32> undef, i32 %a, i32 0
   %r = bitcast <1 x i32> %v to <2 x i16>
   ret <2 x i16> %r
-; CHECK: @BitcastInsert
+; CHECK-LABEL: @BitcastInsert(
 ; CHECK: bitcast i32 %a to <2 x i16>
 }
diff --git a/test/Transforms/InstCombine/call-cast-target.ll b/test/Transforms/InstCombine/call-cast-target.ll
index 7addc8a..315c516 100644
--- a/test/Transforms/InstCombine/call-cast-target.ll
+++ b/test/Transforms/InstCombine/call-cast-target.ll
@@ -1,13 +1,14 @@
-; RUN: opt < %s -instcombine -S | \
-; RUN:   grep call | not grep bitcast
+; RUN: opt < %s -instcombine -S | FileCheck %s
 
 target datalayout = "e-p:32:32"
 target triple = "i686-pc-linux-gnu"
 
 define i32 @main() {
+; CHECK-LABEL: @main
+; CHECK: call i32 bitcast
 entry:
-        %tmp = call i32 bitcast (i8* (i32*)* @ctime to i32 (i32*)*)( i32* null )          ; <i32> [#uses=1]
-        ret i32 %tmp
+  %tmp = call i32 bitcast (i8* (i32*)* @ctime to i32 (i32*)*)( i32* null )          ; <i32> [#uses=1]
+  ret i32 %tmp
 }
 
 declare i8* @ctime(i32*)
diff --git a/test/Transforms/InstCombine/call.ll b/test/Transforms/InstCombine/call.ll
index 96ec420..55833fb 100644
--- a/test/Transforms/InstCombine/call.ll
+++ b/test/Transforms/InstCombine/call.ll
@@ -7,92 +7,94 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1
 declare void @test1a(i8*)
 
 define void @test1(i32* %A) {
-        call void bitcast (void (i8*)* @test1a to void (i32*)*)( i32* %A )
-        ret void
+; CHECK-LABEL: @test1(
 ; CHECK: %1 = bitcast i32* %A to i8*
 ; CHECK: call void @test1a(i8* %1)
 ; CHECK: ret void
+  call void bitcast (void (i8*)* @test1a to void (i32*)*)( i32* %A )
+  ret void
 }
 
-; More complex case, translate argument because of resolution.  This is safe 
+; More complex case, translate argument because of resolution.  This is safe
 ; because we have the body of the function
 define void @test2a(i8 %A) {
-        ret void
+; CHECK-LABEL: @test2a(
 ; CHECK: ret void
+  ret void
 }
 
 define i32 @test2(i32 %A) {
-        call void bitcast (void (i8)* @test2a to void (i32)*)( i32 %A )
-        ret i32 %A
-; CHECK: %1 = trunc i32 %A to i8
-; CHECK: call void @test2a(i8 %1)
+; CHECK-LABEL: @test2(
+; CHECK: call void bitcast
 ; CHECK: ret i32 %A
+  call void bitcast (void (i8)* @test2a to void (i32)*)( i32 %A )
+  ret i32 %A
 }
 
 
-; Resolving this should insert a cast from sbyte to int, following the C 
+; Resolving this should insert a cast from sbyte to int, following the C
 ; promotion rules.
 define void @test3a(i8, ...) {unreachable }
 
 define void @test3(i8 %A, i8 %B) {
-        call void bitcast (void (i8, ...)* @test3a to void (i8, i8)*)( i8 %A, i8 %B 
-)
-        ret void
+; CHECK-LABEL: @test3(
 ; CHECK: %1 = zext i8 %B to i32
 ; CHECK: call void (i8, ...)* @test3a(i8 %A, i32 %1)
 ; CHECK: ret void
+  call void bitcast (void (i8, ...)* @test3a to void (i8, i8)*)( i8 %A, i8 %B)
+  ret void
 }
 
-
 ; test conversion of return value...
 define i8 @test4a() {
-        ret i8 0
+; CHECK-LABEL: @test4a(
 ; CHECK: ret i8 0
+  ret i8 0
 }
 
 define i32 @test4() {
-        %X = call i32 bitcast (i8 ()* @test4a to i32 ()*)( )            ; <i32> [#uses=1]
-        ret i32 %X
-; CHECK: %X = call i8 @test4a()
-; CHECK: %1 = zext i8 %X to i32
-; CHECK: ret i32 %1
+; CHECK-LABEL: @test4(
+; CHECK: call i32 bitcast
+  %X = call i32 bitcast (i8 ()* @test4a to i32 ()*)( )            ; <i32> [#uses=1]
+  ret i32 %X
 }
 
-
-; test conversion of return value... no value conversion occurs so we can do 
+; test conversion of return value... no value conversion occurs so we can do
 ; this with just a prototype...
 declare i32 @test5a()
 
 define i32 @test5() {
-        %X = call i32 @test5a( )                ; <i32> [#uses=1]
-        ret i32 %X
+; CHECK-LABEL: @test5(
 ; CHECK: %X = call i32 @test5a()
 ; CHECK: ret i32 %X
+  %X = call i32 @test5a( )                ; <i32> [#uses=1]
+  ret i32 %X
 }
 
-
 ; test addition of new arguments...
 declare i32 @test6a(i32)
 
 define i32 @test6() {
-        %X = call i32 bitcast (i32 (i32)* @test6a to i32 ()*)( )
-        ret i32 %X
+; CHECK-LABEL: @test6(
 ; CHECK: %X = call i32 @test6a(i32 0)
 ; CHECK: ret i32 %X
+  %X = call i32 bitcast (i32 (i32)* @test6a to i32 ()*)( )
+  ret i32 %X
 }
 
-
 ; test removal of arguments, only can happen with a function body
 define void @test7a() {
-        ret void
+; CHECK-LABEL: @test7a(
 ; CHECK: ret void
+  ret void
 }
 
 define void @test7() {
-        call void bitcast (void ()* @test7a to void (i32)*)( i32 5 )
-        ret void
+; CHECK-LABEL: @test7(
 ; CHECK: call void @test7a()
 ; CHECK: ret void
+  call void bitcast (void ()* @test7a to void (i32)*)( i32 5 )
+  ret void
 }
 
 
@@ -100,6 +102,11 @@ define void @test7() {
 declare void @test8a()
 
 define i8* @test8() {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT: invoke void @test8a()
+; Don't turn this into "unreachable": the callee and caller don't agree in
+; calling conv, but the implementation of test8a may actually end up using the
+; right calling conv.
   invoke void @test8a()
           to label %invoke.cont unwind label %try.handler
 
@@ -114,23 +121,17 @@ try.handler:                                      ; preds = %entry
 
 declare i32 @__gxx_personality_v0(...)
 
-; Don't turn this into "unreachable": the callee and caller don't agree in
-; calling conv, but the implementation of test8a may actually end up using the
-; right calling conv.
-; CHECK: @test8() {
-; CHECK-NEXT: invoke void @test8a()
-
-
 
-; Don't turn this into a direct call, because test9x is just a prototype and 
+; Don't turn this into a direct call, because test9x is just a prototype and
 ; doing so will make it varargs.
 ; rdar://9038601
 declare i8* @test9x(i8*, i8*, ...) noredzone
 define i8* @test9(i8* %arg, i8* %tmp3) nounwind ssp noredzone {
+; CHECK-LABEL: @test9
 entry:
   %call = call i8* bitcast (i8* (i8*, i8*, ...)* @test9x to i8* (i8*, i8*)*)(i8* %arg, i8* %tmp3) noredzone
   ret i8* %call
-; CHECK: @test9(
+; CHECK-LABEL: @test9(
 ; CHECK: call i8* bitcast
 }
 
diff --git a/test/Transforms/InstCombine/canonicalize_branch.ll b/test/Transforms/InstCombine/canonicalize_branch.ll
index 869546d..b62b143 100644
--- a/test/Transforms/InstCombine/canonicalize_branch.ll
+++ b/test/Transforms/InstCombine/canonicalize_branch.ll
@@ -5,7 +5,7 @@ define i32 @test0(i32 %X, i32 %Y) {
         %C = icmp eq i32 %X, %Y
         br i1 %C, label %T, label %F, !prof !0
 
-; CHECK: @test0
+; CHECK-LABEL: @test0(
 ; CHECK: %C = icmp eq i32 %X, %Y
 ; CHECK: br i1 %C, label %T, label %F
 
@@ -19,7 +19,7 @@ define i32 @test1(i32 %X, i32 %Y) {
         %C = icmp ne i32 %X, %Y
         br i1 %C, label %T, label %F, !prof !1
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %C = icmp eq i32 %X, %Y
 ; CHECK: br i1 %C, label %F, label %T
 
@@ -33,7 +33,7 @@ define i32 @test2(i32 %X, i32 %Y) {
         %C = icmp ule i32 %X, %Y
         br i1 %C, label %T, label %F, !prof !2
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: %C = icmp ugt i32 %X, %Y
 ; CHECK: br i1 %C, label %F, label %T
 
@@ -47,7 +47,7 @@ define i32 @test3(i32 %X, i32 %Y) {
         %C = icmp uge i32 %X, %Y
         br i1 %C, label %T, label %F, !prof !3
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: %C = icmp ult i32 %X, %Y
 ; CHECK: br i1 %C, label %F, label %T
 
diff --git a/test/Transforms/InstCombine/cast.ll b/test/Transforms/InstCombine/cast.ll
index ff2c0a9..52ea7b9 100644
--- a/test/Transforms/InstCombine/cast.ll
+++ b/test/Transforms/InstCombine/cast.ll
@@ -326,7 +326,7 @@ define i16 @test39(i16 %a) {
         %tmp.upgrd.32 = or i32 %tmp21, %tmp5
         %tmp.upgrd.3 = trunc i32 %tmp.upgrd.32 to i16
         ret i16 %tmp.upgrd.3
-; CHECK: @test39
+; CHECK-LABEL: @test39(
 ; CHECK: %tmp.upgrd.32 = call i16 @llvm.bswap.i16(i16 %a)
 ; CHECK: ret i16 %tmp.upgrd.32
 }
@@ -338,7 +338,7 @@ define i16 @test40(i16 %a) {
         %tmp.upgrd.32 = or i32 %tmp21, %tmp5
         %tmp.upgrd.3 = trunc i32 %tmp.upgrd.32 to i16
         ret i16 %tmp.upgrd.3
-; CHECK: @test40
+; CHECK-LABEL: @test40(
 ; CHECK: %tmp21 = lshr i16 %a, 9
 ; CHECK: %tmp5 = shl i16 %a, 8
 ; CHECK: %tmp.upgrd.32 = or i16 %tmp21, %tmp5
@@ -350,7 +350,7 @@ define i32* @test41(i32* %tmp1) {
         %tmp64 = bitcast i32* %tmp1 to { i32 }*
         %tmp65 = getelementptr { i32 }* %tmp64, i32 0, i32 0
         ret i32* %tmp65
-; CHECK: @test41
+; CHECK-LABEL: @test41(
 ; CHECK: ret i32* %tmp1
 }
 
@@ -358,7 +358,7 @@ define i32 @test42(i32 %X) {
         %Y = trunc i32 %X to i8         ; <i8> [#uses=1]
         %Z = zext i8 %Y to i32          ; <i32> [#uses=1]
         ret i32 %Z
-; CHECK: @test42
+; CHECK-LABEL: @test42(
 ; CHECK: %Z = and i32 %X, 255
 }
 
@@ -368,7 +368,7 @@ define zeroext i64 @test43(i8 zeroext %on_off) nounwind readonly {
 	%B = add i32 %A, -1
 	%C = sext i32 %B to i64
 	ret i64 %C  ;; Should be (add (zext i8 -> i64), -1)
-; CHECK: @test43
+; CHECK-LABEL: @test43(
 ; CHECK-NEXT: %A = zext i8 %on_off to i64
 ; CHECK-NEXT: %B = add i64 %A, -1
 ; CHECK-NEXT: ret i64 %B
@@ -379,7 +379,7 @@ define i64 @test44(i8 %T) {
  %B = or i16 %A, 1234
  %C = zext i16 %B to i64
  ret i64 %C
-; CHECK: @test44
+; CHECK-LABEL: @test44(
 ; CHECK-NEXT: %A = zext i8 %T to i64
 ; CHECK-NEXT: %B = or i64 %A, 1234
 ; CHECK-NEXT: ret i64 %B
@@ -391,7 +391,7 @@ define i64 @test45(i8 %A, i64 %Q) {
  %C = or i32 %B, %D
  %E = zext i32 %C to i64 
  ret i64 %E
-; CHECK: @test45
+; CHECK-LABEL: @test45(
 ; CHECK-NEXT: %B = sext i8 %A to i64
 ; CHECK-NEXT: %C = or i64 %B, %Q
 ; CHECK-NEXT: %E = and i64 %C, 4294967295
@@ -405,7 +405,7 @@ define i64 @test46(i64 %A) {
  %D = shl i32 %C, 8
  %E = zext i32 %D to i64 
  ret i64 %E
-; CHECK: @test46
+; CHECK-LABEL: @test46(
 ; CHECK-NEXT: %C = shl i64 %A, 8
 ; CHECK-NEXT: %D = and i64 %C, 10752
 ; CHECK-NEXT: ret i64 %D
@@ -416,7 +416,7 @@ define i64 @test47(i8 %A) {
  %C = or i32 %B, 42
  %E = zext i32 %C to i64 
  ret i64 %E
-; CHECK: @test47
+; CHECK-LABEL: @test47(
 ; CHECK-NEXT:   %B = sext i8 %A to i64
 ; CHECK-NEXT: %C = and i64 %B, 4294967253
 ; CHECK-NEXT:  %E = or i64 %C, 42
@@ -430,7 +430,7 @@ define i64 @test48(i8 %A, i8 %a) {
   %D = or i32 %C, %b
   %E = zext i32 %D to i64
   ret i64 %E
-; CHECK: @test48
+; CHECK-LABEL: @test48(
 ; CHECK-NEXT: %b = zext i8 %a to i64
 ; CHECK-NEXT: %B = zext i8 %A to i64
 ; CHECK-NEXT: %C = shl nuw nsw i64 %B, 8
@@ -443,7 +443,7 @@ define i64 @test49(i64 %A) {
  %C = or i32 %B, 1
  %D = sext i32 %C to i64 
  ret i64 %D
-; CHECK: @test49
+; CHECK-LABEL: @test49(
 ; CHECK-NEXT: %C = shl i64 %A, 32
 ; CHECK-NEXT: ashr exact i64 %C, 32
 ; CHECK-NEXT: %D = or i64 {{.*}}, 1
@@ -456,7 +456,7 @@ define i64 @test50(i64 %A) {
   %D = add i32 %B, -1
   %E = sext i32 %D to i64
   ret i64 %E
-; CHECK: @test50
+; CHECK-LABEL: @test50(
 ; lshr+shl will be handled by DAGCombine.
 ; CHECK-NEXT: lshr i64 %A, 2
 ; CHECK-NEXT: shl i64 %a, 32
@@ -472,7 +472,7 @@ define i64 @test51(i64 %A, i1 %cond) {
   %E = select i1 %cond, i32 %C, i32 %D
   %F = sext i32 %E to i64
   ret i64 %F
-; CHECK: @test51
+; CHECK-LABEL: @test51(
 ; CHECK-NEXT: %C = and i64 %A, 4294967294
 ; CHECK-NEXT: %D = or i64 %A, 1
 ; CHECK-NEXT: %E = select i1 %cond, i64 %C, i64 %D
@@ -487,7 +487,7 @@ define i32 @test52(i64 %A) {
   %D = and i16 %C, -25350
   %E = zext i16 %D to i32
   ret i32 %E
-; CHECK: @test52
+; CHECK-LABEL: @test52(
 ; CHECK-NEXT: %B = trunc i64 %A to i32
 ; CHECK-NEXT: %C = and i32 %B, 7224
 ; CHECK-NEXT: %D = or i32 %C, 32962
@@ -500,7 +500,7 @@ define i64 @test53(i32 %A) {
   %D = and i16 %C, -25350
   %E = zext i16 %D to i64
   ret i64 %E
-; CHECK: @test53
+; CHECK-LABEL: @test53(
 ; CHECK-NEXT: %B = zext i32 %A to i64
 ; CHECK-NEXT: %C = and i64 %B, 7224
 ; CHECK-NEXT: %D = or i64 %C, 32962
@@ -513,7 +513,7 @@ define i32 @test54(i64 %A) {
   %D = and i16 %C, -25350
   %E = sext i16 %D to i32
   ret i32 %E
-; CHECK: @test54
+; CHECK-LABEL: @test54(
 ; CHECK-NEXT: %B = trunc i64 %A to i32
 ; CHECK-NEXT: %C = and i32 %B, 7224
 ; CHECK-NEXT: %D = or i32 %C, -32574
@@ -526,7 +526,7 @@ define i64 @test55(i32 %A) {
   %D = and i16 %C, -25350
   %E = sext i16 %D to i64
   ret i64 %E
-; CHECK: @test55
+; CHECK-LABEL: @test55(
 ; CHECK-NEXT: %B = zext i32 %A to i64
 ; CHECK-NEXT: %C = and i64 %B, 7224
 ; CHECK-NEXT: %D = or i64 %C, -32574
@@ -538,7 +538,7 @@ define i64 @test56(i16 %A) nounwind {
   %tmp354 = lshr i32 %tmp353, 5
   %tmp355 = zext i32 %tmp354 to i64
   ret i64 %tmp355
-; CHECK: @test56
+; CHECK-LABEL: @test56(
 ; CHECK-NEXT: %tmp353 = sext i16 %A to i64
 ; CHECK-NEXT: %tmp354 = lshr i64 %tmp353, 5
 ; CHECK-NEXT: %tmp355 = and i64 %tmp354, 134217727
@@ -550,7 +550,7 @@ define i64 @test57(i64 %A) nounwind {
  %C = lshr i32 %B, 8
  %E = zext i32 %C to i64
  ret i64 %E
-; CHECK: @test57
+; CHECK-LABEL: @test57(
 ; CHECK-NEXT: %C = lshr i64 %A, 8 
 ; CHECK-NEXT: %E = and i64 %C, 16777215
 ; CHECK-NEXT: ret i64 %E
@@ -563,7 +563,7 @@ define i64 @test58(i64 %A) nounwind {
  %E = zext i32 %D to i64
  ret i64 %E
  
-; CHECK: @test58
+; CHECK-LABEL: @test58(
 ; CHECK-NEXT:   %C = lshr i64 %A, 8
 ; CHECK-NEXT:   %D = and i64 %C, 16777087
 ; CHECK-NEXT:   %E = or i64 %D, 128
@@ -579,7 +579,7 @@ define i64 @test59(i8 %A, i8 %B) nounwind {
   %H = or i32 %G, %E
   %I = zext i32 %H to i64
   ret i64 %I
-; CHECK: @test59
+; CHECK-LABEL: @test59(
 ; CHECK-NEXT:   %C = zext i8 %A to i64
 ; CHECK-NOT: i32
 ; CHECK:   %F = zext i8 %B to i64
@@ -593,7 +593,7 @@ define <3 x i32> @test60(<4 x i32> %call4) nounwind {
   %tmp10 = bitcast i96 %tmp9 to <3 x i32>
   ret <3 x i32> %tmp10
   
-; CHECK: @test60
+; CHECK-LABEL: @test60(
 ; CHECK-NEXT: shufflevector
 ; CHECK-NEXT: ret
 }
@@ -603,7 +603,7 @@ define <4 x i32> @test61(<3 x i32> %call4) nounwind {
   %tmp9 = zext i96 %tmp11 to i128
   %tmp10 = bitcast i128 %tmp9 to <4 x i32>
   ret <4 x i32> %tmp10
-; CHECK: @test61
+; CHECK-LABEL: @test61(
 ; CHECK-NEXT: shufflevector
 ; CHECK-NEXT: ret
 }
@@ -613,7 +613,7 @@ define <4 x i32> @test62(<3 x float> %call4) nounwind {
   %tmp9 = zext i96 %tmp11 to i128
   %tmp10 = bitcast i128 %tmp9 to <4 x i32>
   ret <4 x i32> %tmp10
-; CHECK: @test62
+; CHECK-LABEL: @test62(
 ; CHECK-NEXT: bitcast
 ; CHECK-NEXT: shufflevector
 ; CHECK-NEXT: ret
@@ -625,7 +625,7 @@ entry:
   %a = bitcast i64 %tmp8 to <2 x i32>           
   %vcvt.i = uitofp <2 x i32> %a to <2 x float>  
   ret <2 x float> %vcvt.i
-; CHECK: @test63
+; CHECK-LABEL: @test63(
 ; CHECK: bitcast
 ; CHECK: uitofp
 }
@@ -634,7 +634,7 @@ define <4 x float> @test64(<4 x float> %c) nounwind {
   %t0 = bitcast <4 x float> %c to <4 x i32>
   %t1 = bitcast <4 x i32> %t0 to <4 x float>
   ret <4 x float> %t1
-; CHECK: @test64
+; CHECK-LABEL: @test64(
 ; CHECK-NEXT: ret <4 x float> %c
 }
 
@@ -642,7 +642,7 @@ define <4 x float> @test65(<4 x float> %c) nounwind {
   %t0 = bitcast <4 x float> %c to <2 x double>
   %t1 = bitcast <2 x double> %t0 to <4 x float>
   ret <4 x float> %t1
-; CHECK: @test65
+; CHECK-LABEL: @test65(
 ; CHECK-NEXT: ret <4 x float> %c
 }
 
@@ -650,13 +650,13 @@ define <2 x float> @test66(<2 x float> %c) nounwind {
   %t0 = bitcast <2 x float> %c to double
   %t1 = bitcast double %t0 to <2 x float>
   ret <2 x float> %t1
-; CHECK: @test66
+; CHECK-LABEL: @test66(
 ; CHECK-NEXT: ret <2 x float> %c
 }
 
 define float @test2c() {
   ret float extractelement (<2 x float> bitcast (double bitcast (<2 x float> <float -1.000000e+00, float -1.000000e+00> to double) to <2 x float>), i32 0)
-; CHECK: @test2c
+; CHECK-LABEL: @test2c(
 ; CHECK-NOT: extractelement
 }
 
@@ -665,7 +665,7 @@ define i64 @test_mmx(<2 x i32> %c) nounwind {
   %B = bitcast x86_mmx %A to <2 x i32>
   %C = bitcast <2 x i32> %B to i64
   ret i64 %C
-; CHECK: @test_mmx
+; CHECK-LABEL: @test_mmx(
 ; CHECK-NOT: x86_mmx
 }
 
@@ -674,7 +674,7 @@ define i64 @test_mmx_const(<2 x i32> %c) nounwind {
   %B = bitcast x86_mmx %A to <2 x i32>
   %C = bitcast <2 x i32> %B to i64
   ret i64 %C
-; CHECK: @test_mmx_const
+; CHECK-LABEL: @test_mmx_const(
 ; CHECK-NOT: x86_mmx
 }
 
@@ -689,14 +689,14 @@ define i1 @test67(i1 %a, i32 %b) {
   %trunc = trunc i32 %conv.i.i to i8
   %tobool.i = icmp eq i8 %trunc, 0
   ret i1 %tobool.i
-; CHECK: @test67
+; CHECK-LABEL: @test67(
 ; CHECK: ret i1 false
 }
 
 %s = type { i32, i32, i32 }
 
 define %s @test68(%s *%p, i64 %i) {
-; CHECK: @test68
+; CHECK-LABEL: @test68(
   %o = mul i64 %i, 12
   %q = bitcast %s* %p to i8*
   %pp = getelementptr inbounds i8* %q, i64 %o
@@ -709,7 +709,7 @@ define %s @test68(%s *%p, i64 %i) {
 }
 
 define double @test69(double *%p, i64 %i) {
-; CHECK: @test69
+; CHECK-LABEL: @test69(
   %o = shl nsw i64 %i, 3
   %q = bitcast double* %p to i8*
   %pp = getelementptr inbounds i8* %q, i64 %o
@@ -722,7 +722,7 @@ define double @test69(double *%p, i64 %i) {
 }
 
 define %s @test70(%s *%p, i64 %i) {
-; CHECK: @test70
+; CHECK-LABEL: @test70(
   %o = mul nsw i64 %i, 36
 ; CHECK-NEXT: mul nsw i64 %i, 3
   %q = bitcast %s* %p to i8*
@@ -736,7 +736,7 @@ define %s @test70(%s *%p, i64 %i) {
 }
 
 define double @test71(double *%p, i64 %i) {
-; CHECK: @test71
+; CHECK-LABEL: @test71(
   %o = shl i64 %i, 5
 ; CHECK-NEXT: shl i64 %i, 2
   %q = bitcast double* %p to i8*
@@ -750,7 +750,7 @@ define double @test71(double *%p, i64 %i) {
 }
 
 define double @test72(double *%p, i32 %i) {
-; CHECK: @test72
+; CHECK-LABEL: @test72(
   %so = mul nsw i32 %i, 8
   %o = sext i32 %so to i64
 ; CHECK-NEXT: sext i32 %i to i64
@@ -765,7 +765,7 @@ define double @test72(double *%p, i32 %i) {
 }
 
 define double @test73(double *%p, i128 %i) {
-; CHECK: @test73
+; CHECK-LABEL: @test73(
   %lo = mul nsw i128 %i, 8
   %o = trunc i128 %lo to i64
 ; CHECK-NEXT: trunc i128 %i to i64
@@ -780,7 +780,7 @@ define double @test73(double *%p, i128 %i) {
 }
 
 define double @test74(double *%p, i64 %i) {
-; CHECK: @test74
+; CHECK-LABEL: @test74(
   %q = bitcast double* %p to i64*
   %pp = getelementptr inbounds i64* %q, i64 %i
 ; CHECK-NEXT: getelementptr inbounds double*
@@ -792,7 +792,7 @@ define double @test74(double *%p, i64 %i) {
 }
 
 define i32* @test75(i32* %p, i32 %x) {
-; CHECK: @test75
+; CHECK-LABEL: @test75(
   %y = shl i32 %x, 3
 ; CHECK-NEXT: shl i32 %x, 3
   %z = sext i32 %y to i64
@@ -804,7 +804,7 @@ define i32* @test75(i32* %p, i32 %x) {
 }
 
 define %s @test76(%s *%p, i64 %i, i64 %j) {
-; CHECK: @test76
+; CHECK-LABEL: @test76(
   %o = mul i64 %i, 12
   %o2 = mul nsw i64 %o, %j
 ; CHECK-NEXT: %o2 = mul i64 %i, %j
@@ -819,7 +819,7 @@ define %s @test76(%s *%p, i64 %i, i64 %j) {
 }
 
 define %s @test77(%s *%p, i64 %i, i64 %j) {
-; CHECK: @test77
+; CHECK-LABEL: @test77(
   %o = mul nsw i64 %i, 36
   %o2 = mul nsw i64 %o, %j
 ; CHECK-NEXT: %o = mul nsw i64 %i, 3
@@ -835,7 +835,7 @@ define %s @test77(%s *%p, i64 %i, i64 %j) {
 }
 
 define %s @test78(%s *%p, i64 %i, i64 %j, i32 %k, i32 %l, i128 %m, i128 %n) {
-; CHECK: @test78
+; CHECK-LABEL: @test78(
   %a = mul nsw i32 %k, 36
 ; CHECK-NEXT: mul nsw i32 %k, 3
   %b = mul nsw i32 %a, %l
@@ -863,7 +863,7 @@ define %s @test78(%s *%p, i64 %i, i64 %j, i32 %k, i32 %l, i128 %m, i128 %n) {
 }
 
 define %s @test79(%s *%p, i64 %i, i32 %j) {
-; CHECK: @test79
+; CHECK-LABEL: @test79(
   %a = mul nsw i64 %i, 36
 ; CHECK: mul nsw i64 %i, 36
   %b = trunc i64 %a to i32
@@ -877,7 +877,7 @@ define %s @test79(%s *%p, i64 %i, i32 %j) {
 }
 
 define double @test80([100 x double]* %p, i32 %i) {
-; CHECK: @test80
+; CHECK-LABEL: @test80(
   %tmp = mul nsw i32 %i, 8
 ; CHECK-NEXT: sext i32 %i to i64
   %q = bitcast [100 x double]* %p to i8*
@@ -906,7 +906,7 @@ define i64 @test82(i64 %A) nounwind {
   %E = zext i32 %D to i64
   ret i64 %E
 
-; CHECK: @test82
+; CHECK-LABEL: @test82(
 ; CHECK-NEXT:   [[REG:%[0-9]*]] = shl i64 %A, 1
 ; CHECK-NEXT:   %E = and i64 [[REG]], 4294966784
 ; CHECK-NEXT:   ret i64 %E
@@ -921,7 +921,7 @@ define i64 @test83(i16 %a, i64 %k) {
   %sh_prom1 = zext i32 %shl to i64
   ret i64 %sh_prom1
 
-; CHECK: @test83
+; CHECK-LABEL: @test83(
 ; CHECK: %sub = add nsw i64 %k, 4294967295
 ; CHECK: %sh_prom = trunc i64 %sub to i32
 ; CHECK: %shl = shl i32 %conv, %sh_prom
diff --git a/test/Transforms/InstCombine/cast_ptr.ll b/test/Transforms/InstCombine/cast_ptr.ll
index 09910fb..7910ea3 100644
--- a/test/Transforms/InstCombine/cast_ptr.ll
+++ b/test/Transforms/InstCombine/cast_ptr.ll
@@ -6,7 +6,7 @@ target datalayout = "p:32:32"
 ; This shouldn't convert to getelementptr because the relationship
 ; between the arithmetic and the layout of allocated memory is
 ; entirely unknown.
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ptrtoint
 ; CHECK: add
 ; CHECK: inttoptr
@@ -18,7 +18,7 @@ define i8* @test1(i8* %t) {
 }
 
 ; These casts should be folded away.
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: icmp eq i8* %a, %b
 define i1 @test2(i8* %a, i8* %b) {
         %tmpa = ptrtoint i8* %a to i32          ; <i32> [#uses=1]
@@ -28,7 +28,7 @@ define i1 @test2(i8* %a, i8* %b) {
 }
 
 ; These casts should also be folded away.
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: icmp eq i8* %a, @global
 @global = global i8 0
 define i1 @test3(i8* %a) {
@@ -41,7 +41,7 @@ define i1 @test4(i32 %A) {
   %B = inttoptr i32 %A to i8*
   %C = icmp eq i8* %B, null
   ret i1 %C
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: %C = icmp eq i32 %A, 0
 ; CHECK-NEXT: ret i1 %C 
 }
@@ -60,7 +60,7 @@ define %unop* @test5(%op* %O) {
         %tmp = load %unop* (%op*)** bitcast ([1 x %op* (%op*)*]* @Array to %unop* (%op*)**); <%unop* (%op*)*> [#uses=1]
         %tmp.2 = call %unop* %tmp( %op* %O )            ; <%unop*> [#uses=1]
         ret %unop* %tmp.2
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: call %op* @foo(%op* %O)
 }
 
@@ -74,6 +74,6 @@ entry:
   %arrayidx223 = bitcast i8 addrspace(1)* %source to i8*
   %tmp4 = load i8* %arrayidx223
   ret i8 %tmp4
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: load i8* %arrayidx223
 } 
diff --git a/test/Transforms/InstCombine/compare-signs.ll b/test/Transforms/InstCombine/compare-signs.ll
index 72db66e..cdf95ab 100644
--- a/test/Transforms/InstCombine/compare-signs.ll
+++ b/test/Transforms/InstCombine/compare-signs.ll
@@ -22,7 +22,7 @@
 ;}
 
 define i32 @test3(i32 %a, i32 %b) nounwind readnone {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 entry:
 ; CHECK: xor i32 %a, %b
 ; CHECK: lshr i32 %0, 31
@@ -40,7 +40,7 @@ entry:
 ; Variation on @test3: checking the 2nd bit in a situation where the 5th bit
 ; is one, not zero.
 define i32 @test3i(i32 %a, i32 %b) nounwind readnone {
-; CHECK: @test3i
+; CHECK-LABEL: @test3i(
 entry:
 ; CHECK: xor i32 %a, %b
 ; CHECK: lshr i32 %0, 31
diff --git a/test/Transforms/InstCombine/constant-fold-gep.ll b/test/Transforms/InstCombine/constant-fold-gep.ll
index e5b16ea..9f82e66 100644
--- a/test/Transforms/InstCombine/constant-fold-gep.ll
+++ b/test/Transforms/InstCombine/constant-fold-gep.ll
@@ -56,7 +56,7 @@ define void @frob() {
 
 
 ; PR8883 - Constant fold exotic gep subtract
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 @X = global [1000 x i8] zeroinitializer, align 16
 
 define i64 @test2() {
diff --git a/test/Transforms/InstCombine/cos-1.ll b/test/Transforms/InstCombine/cos-1.ll
index b92e448..c2e9a0d 100644
--- a/test/Transforms/InstCombine/cos-1.ll
+++ b/test/Transforms/InstCombine/cos-1.ll
@@ -10,7 +10,7 @@ declare double @cos(double)
 ; Check cos(-x) -> cos(x);
 
 define double @test_simplify1(double %d) {
-; NO-FLOAT-SHRINK: @test_simplify1
+; NO-FLOAT-SHRINK-LABEL: @test_simplify1(
   %neg = fsub double -0.000000e+00, %d
   %cos = call double @cos(double %neg)
 ; NO-FLOAT-SHRINK: call double @cos(double %d)
@@ -18,7 +18,7 @@ define double @test_simplify1(double %d) {
 }
 
 define float @test_simplify2(float %f) {
-; DO-FLOAT-SHRINK: @test_simplify2
+; DO-FLOAT-SHRINK-LABEL: @test_simplify2(
   %conv1 = fpext float %f to double
   %neg = fsub double -0.000000e+00, %conv1
   %cos = call double @cos(double %neg)
@@ -28,7 +28,7 @@ define float @test_simplify2(float %f) {
 }
 
 define float @test_simplify3(float %f) {
-; NO-FLOAT-SHRINK: @test_simplify3
+; NO-FLOAT-SHRINK-LABEL: @test_simplify3(
   %conv1 = fpext float %f to double
   %neg = fsub double -0.000000e+00, %conv1
   %cos = call double @cos(double %neg)
diff --git a/test/Transforms/InstCombine/cos-2.ll b/test/Transforms/InstCombine/cos-2.ll
index 2f2dfaf..c9a9c7c 100644
--- a/test/Transforms/InstCombine/cos-2.ll
+++ b/test/Transforms/InstCombine/cos-2.ll
@@ -9,7 +9,7 @@ declare float @cos(double)
 ; Check that cos functions with the wrong prototype aren't simplified.
 
 define float @test_no_simplify1(double %d) {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %neg = fsub double -0.000000e+00, %d
   %cos = call float @cos(double %neg)
 ; CHECK: call float @cos(double %neg)
diff --git a/test/Transforms/InstCombine/debug-line.ll b/test/Transforms/InstCombine/debug-line.ll
index 084efdc..a76c353 100644
--- a/test/Transforms/InstCombine/debug-line.ll
+++ b/test/Transforms/InstCombine/debug-line.ll
@@ -11,14 +11,16 @@ define void @foo() nounwind ssp {
 
 declare i32 @printf(i8*, ...)
 
+!llvm.dbg.cu = !{!2}
 !llvm.dbg.sp = !{!0}
 
-!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void ()* @foo} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 589865, metadata !"m.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"m.c", metadata !"/private/tmp", metadata !"clang", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 589870, metadata !8, metadata !1, metadata !"foo", metadata !"foo", metadata !"", i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void ()* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 589865, metadata !8} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 589841, metadata !8, i32 12, metadata !"clang", i1 true, metadata !"", i32 0, metadata !4, metadata !4, metadata !9, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 589845, metadata !8, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{null}
 !5 = metadata !{i32 5, i32 2, metadata !6, null}
-!6 = metadata !{i32 589835, metadata !0, i32 4, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ]
+!6 = metadata !{i32 589835, metadata !8, metadata !0, i32 4, i32 12, i32 0} ; [ DW_TAG_lexical_block ]
 !7 = metadata !{i32 6, i32 1, metadata !6, null}
-
+!8 = metadata !{metadata !"m.c", metadata !"/private/tmp"}
+!9 = metadata !{metadata !0}
diff --git a/test/Transforms/InstCombine/debuginfo.ll b/test/Transforms/InstCombine/debuginfo.ll
index a9e3de3..2f080bf 100644
--- a/test/Transforms/InstCombine/debuginfo.ll
+++ b/test/Transforms/InstCombine/debuginfo.ll
@@ -31,26 +31,27 @@ entry:
 !llvm.dbg.cu = !{!3}
 
 !0 = metadata !{i32 786689, metadata !1, metadata !"__dest", metadata !2, i32 16777294, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"foobar", metadata !"foobar", metadata !"", metadata !2, i32 79, metadata !4, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i8* (i8*, i32, i64)* @foobar, null, null, metadata !25, i32 79} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786478, metadata !27, metadata !2, metadata !"foobar", metadata !"foobar", metadata !"", i32 79, metadata !4, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i8* (i8*, i32, i64)* @foobar, null, null, metadata !25, i32 79} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !27} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786449, i32 0, i32 12, metadata !26, metadata !"clang version 3.0 (trunk 127710)", i1 true, metadata !"", i32 0, null, null, metadata !24, null, null} ; [ DW_TAG_compile_unit ]
-!4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !5, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!3 = metadata !{i32 786449, metadata !28, i32 12, metadata !"clang version 3.0 (trunk 127710)", i1 true, metadata !"", i32 0, metadata !29, metadata !29, metadata !24, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!4 = metadata !{i32 786453, metadata !27, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !5, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{metadata !6}
-!6 = metadata !{i32 786447, metadata !3, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
+!6 = metadata !{i32 786447, null, metadata !3, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
 !7 = metadata !{i32 786689, metadata !1, metadata !"__val", metadata !2, i32 33554510, metadata !8, i32 0, null} ; [ DW_TAG_arg_variable ]
-!8 = metadata !{i32 786468, metadata !3, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!8 = metadata !{i32 786468, null, metadata !3, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !9 = metadata !{i32 786689, metadata !1, metadata !"__len", metadata !2, i32 50331726, metadata !10, i32 0, null} ; [ DW_TAG_arg_variable ]
-!10 = metadata !{i32 589846, metadata !3, metadata !"size_t", metadata !2, i32 80, i64 0, i64 0, i64 0, i32 0, metadata !11} ; [ DW_TAG_typedef ]
-!11 = metadata !{i32 589846, metadata !3, metadata !"__darwin_size_t", metadata !2, i32 90, i64 0, i64 0, i64 0, i32 0, metadata !12} ; [ DW_TAG_typedef ]
-!12 = metadata !{i32 786468, metadata !3, metadata !"long unsigned int", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!10 = metadata !{i32 589846, metadata !27, metadata !3, metadata !"size_t", i32 80, i64 0, i64 0, i64 0, i32 0, metadata !11} ; [ DW_TAG_typedef ]
+!11 = metadata !{i32 589846, metadata !27, metadata !3, metadata !"__darwin_size_t", i32 90, i64 0, i64 0, i64 0, i32 0, metadata !12} ; [ DW_TAG_typedef ]
+!12 = metadata !{i32 786468, null, metadata !3, metadata !"long unsigned int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
 !16 = metadata !{i32 78, i32 28, metadata !1, null}
 !18 = metadata !{i32 78, i32 40, metadata !1, null}
 !20 = metadata !{i32 78, i32 54, metadata !1, null}
 !21 = metadata !{i32 80, i32 3, metadata !22, null}
-!22 = metadata !{i32 786443, metadata !23, i32 80, i32 3, metadata !2, i32 7} ; [ DW_TAG_lexical_block ]
-!23 = metadata !{i32 786443, metadata !1, i32 79, i32 1, metadata !2, i32 6} ; [ DW_TAG_lexical_block ]
+!22 = metadata !{i32 786443, metadata !27, metadata !23, i32 80, i32 3, i32 7} ; [ DW_TAG_lexical_block ]
+!23 = metadata !{i32 786443, metadata !27, metadata !1, i32 79, i32 1, i32 6} ; [ DW_TAG_lexical_block ]
 !24 = metadata !{metadata !1}
 !25 = metadata !{metadata !0, metadata !7, metadata !9}
 !26 = metadata !{i32 786473, metadata !28} ; [ DW_TAG_file_type ]
 !27 = metadata !{metadata !"string.h", metadata !"Game"}
 !28 = metadata !{metadata !"bits.c", metadata !"Game"}
+!29 = metadata !{i32 0}
diff --git a/test/Transforms/InstCombine/disable-simplify-libcalls.ll b/test/Transforms/InstCombine/disable-simplify-libcalls.ll
index c2c2936..6652788 100644
--- a/test/Transforms/InstCombine/disable-simplify-libcalls.ll
+++ b/test/Transforms/InstCombine/disable-simplify-libcalls.ll
@@ -51,42 +51,42 @@ declare i32 @printf(i8*)
 declare i32 @sprintf(i8*, i8*)
 
 define double @t1(double %x) {
-; CHECK: @t1
+; CHECK-LABEL: @t1(
   %ret = call double @ceil(double %x)
   ret double %ret
 ; CHECK: call double @ceil
 }
 
 define double @t2(double %x, double %y) {
-; CHECK: @t2
+; CHECK-LABEL: @t2(
   %ret = call double @copysign(double %x, double %y)
   ret double %ret
 ; CHECK: call double @copysign
 }
 
 define double @t3(double %x) {
-; CHECK: @t3
+; CHECK-LABEL: @t3(
   %call = call double @cos(double %x)
   ret double %call
 ; CHECK: call double @cos
 }
 
 define double @t4(double %x) {
-; CHECK: @t4
+; CHECK-LABEL: @t4(
   %ret = call double @fabs(double %x)
   ret double %ret
 ; CHECK: call double @fabs
 }
 
 define double @t5(double %x) {
-; CHECK: @t5
+; CHECK-LABEL: @t5(
   %ret = call double @floor(double %x)
   ret double %ret
 ; CHECK: call double @floor
 }
 
 define i8* @t6(i8* %x) {
-; CHECK: @t6
+; CHECK-LABEL: @t6(
   %empty = getelementptr [1 x i8]* @empty, i32 0, i32 0
   %ret = call i8* @strcat(i8* %x, i8* %empty)
   ret i8* %ret
@@ -94,7 +94,7 @@ define i8* @t6(i8* %x) {
 }
 
 define i8* @t7(i8* %x) {
-; CHECK: @t7
+; CHECK-LABEL: @t7(
   %empty = getelementptr [1 x i8]* @empty, i32 0, i32 0
   %ret = call i8* @strncat(i8* %x, i8* %empty, i32 1)
   ret i8* %ret
@@ -102,7 +102,7 @@ define i8* @t7(i8* %x) {
 }
 
 define i8* @t8() {
-; CHECK: @t8
+; CHECK-LABEL: @t8(
   %x = getelementptr inbounds [13 x i8]* @.str1, i32 0, i32 0
   %ret = call i8* @strchr(i8* %x, i32 119)
   ret i8* %ret
@@ -110,7 +110,7 @@ define i8* @t8() {
 }
 
 define i8* @t9() {
-; CHECK: @t9
+; CHECK-LABEL: @t9(
   %x = getelementptr inbounds [13 x i8]* @.str1, i32 0, i32 0
   %ret = call i8* @strrchr(i8* %x, i32 119)
   ret i8* %ret
@@ -118,7 +118,7 @@ define i8* @t9() {
 }
 
 define i32 @t10() {
-; CHECK: @t10
+; CHECK-LABEL: @t10(
   %x = getelementptr inbounds [4 x i8]* @.str2, i32 0, i32 0
   %y = getelementptr inbounds [4 x i8]* @.str3, i32 0, i32 0
   %ret = call i32 @strcmp(i8* %x, i8* %y)
@@ -127,7 +127,7 @@ define i32 @t10() {
 }
 
 define i32 @t11() {
-; CHECK: @t11
+; CHECK-LABEL: @t11(
   %x = getelementptr inbounds [4 x i8]* @.str2, i32 0, i32 0
   %y = getelementptr inbounds [4 x i8]* @.str3, i32 0, i32 0
   %ret = call i32 @strncmp(i8* %x, i8* %y, i64 3)
@@ -136,7 +136,7 @@ define i32 @t11() {
 }
 
 define i8* @t12(i8* %x) {
-; CHECK: @t12
+; CHECK-LABEL: @t12(
   %y = getelementptr inbounds [4 x i8]* @.str2, i32 0, i32 0
   %ret = call i8* @strcpy(i8* %x, i8* %y)
   ret i8* %ret
@@ -144,7 +144,7 @@ define i8* @t12(i8* %x) {
 }
 
 define i8* @t13(i8* %x) {
-; CHECK: @t13
+; CHECK-LABEL: @t13(
   %y = getelementptr inbounds [4 x i8]* @.str2, i32 0, i32 0
   %ret = call i8* @stpcpy(i8* %x, i8* %y)
   ret i8* %ret
@@ -152,7 +152,7 @@ define i8* @t13(i8* %x) {
 }
 
 define i8* @t14(i8* %x) {
-; CHECK: @t14
+; CHECK-LABEL: @t14(
   %y = getelementptr inbounds [4 x i8]* @.str2, i32 0, i32 0
   %ret = call i8* @strncpy(i8* %x, i8* %y, i64 3)
   ret i8* %ret
@@ -160,7 +160,7 @@ define i8* @t14(i8* %x) {
 }
 
 define i64 @t15() {
-; CHECK: @t15
+; CHECK-LABEL: @t15(
   %x = getelementptr inbounds [4 x i8]* @.str2, i32 0, i32 0
   %ret = call i64 @strlen(i8* %x)
   ret i64 %ret
@@ -168,7 +168,7 @@ define i64 @t15() {
 }
 
 define i8* @t16(i8* %x) {
-; CHECK: @t16
+; CHECK-LABEL: @t16(
   %y = getelementptr inbounds [1 x i8]* @.str, i32 0, i32 0
   %ret = call i8* @strpbrk(i8* %x, i8* %y)
   ret i8* %ret
@@ -176,7 +176,7 @@ define i8* @t16(i8* %x) {
 }
 
 define i64 @t17(i8* %x) {
-; CHECK: @t17
+; CHECK-LABEL: @t17(
   %y = getelementptr inbounds [1 x i8]* @.str, i32 0, i32 0
   %ret = call i64 @strspn(i8* %x, i8* %y)
   ret i64 %ret
@@ -184,7 +184,7 @@ define i64 @t17(i8* %x) {
 }
 
 define double @t18(i8** %y) {
-; CHECK: @t18
+; CHECK-LABEL: @t18(
   %x = getelementptr inbounds [6 x i8]* @.str4, i64 0, i64 0
   %ret = call double @strtod(i8* %x, i8** %y)
   ret double %ret
@@ -192,7 +192,7 @@ define double @t18(i8** %y) {
 }
 
 define float @t19(i8** %y) {
-; CHECK: @t19
+; CHECK-LABEL: @t19(
   %x = getelementptr inbounds [6 x i8]* @.str4, i64 0, i64 0
   %ret = call float @strtof(i8* %x, i8** %y)
   ret float %ret
@@ -200,7 +200,7 @@ define float @t19(i8** %y) {
 }
 
 define x86_fp80 @t20(i8** %y) {
-; CHECK: @t20
+; CHECK-LABEL: @t20(
   %x = getelementptr inbounds [6 x i8]* @.str4, i64 0, i64 0
   %ret = call x86_fp80 @strtold(i8* %x, i8** %y)
   ret x86_fp80 %ret
@@ -208,7 +208,7 @@ define x86_fp80 @t20(i8** %y) {
 }
 
 define i64 @t21(i8** %y) {
-; CHECK: @t21
+; CHECK-LABEL: @t21(
   %x = getelementptr inbounds [5 x i8]* @.str5, i64 0, i64 0
   %ret = call i64 @strtol(i8* %x, i8** %y, i32 10)
   ret i64 %ret
@@ -216,7 +216,7 @@ define i64 @t21(i8** %y) {
 }
 
 define i64 @t22(i8** %y) {
-; CHECK: @t22
+; CHECK-LABEL: @t22(
   %x = getelementptr inbounds [5 x i8]* @.str5, i64 0, i64 0
   %ret = call i64 @strtoll(i8* %x, i8** %y, i32 10)
   ret i64 %ret
@@ -224,7 +224,7 @@ define i64 @t22(i8** %y) {
 }
 
 define i64 @t23(i8** %y) {
-; CHECK: @t23
+; CHECK-LABEL: @t23(
   %x = getelementptr inbounds [5 x i8]* @.str5, i64 0, i64 0
   %ret = call i64 @strtoul(i8* %x, i8** %y, i32 10)
   ret i64 %ret
@@ -232,7 +232,7 @@ define i64 @t23(i8** %y) {
 }
 
 define i64 @t24(i8** %y) {
-; CHECK: @t24
+; CHECK-LABEL: @t24(
   %x = getelementptr inbounds [5 x i8]* @.str5, i64 0, i64 0
   %ret = call i64 @strtoull(i8* %x, i8** %y, i32 10)
   ret i64 %ret
@@ -240,7 +240,7 @@ define i64 @t24(i8** %y) {
 }
 
 define i64 @t25(i8* %y) {
-; CHECK: @t25
+; CHECK-LABEL: @t25(
   %x = getelementptr [1 x i8]* @empty, i32 0, i32 0
   %ret = call i64 @strcspn(i8* %x, i8* %y)
   ret i64 %ret
@@ -248,35 +248,35 @@ define i64 @t25(i8* %y) {
 }
 
 define i32 @t26(i32 %y) {
-; CHECK: @t26
+; CHECK-LABEL: @t26(
   %ret = call i32 @abs(i32 %y)
   ret i32 %ret
 ; CHECK: call i32 @abs
 }
 
 define i32 @t27(i32 %y) {
-; CHECK: @t27
+; CHECK-LABEL: @t27(
   %ret = call i32 @ffs(i32 %y)
   ret i32 %ret
 ; CHECK: call i32 @ffs
 }
 
 define i32 @t28(i64 %y) {
-; CHECK: @t28
+; CHECK-LABEL: @t28(
   %ret = call i32 @ffsl(i64 %y)
   ret i32 %ret
 ; CHECK: call i32 @ffsl
 }
 
 define i32 @t29(i64 %y) {
-; CHECK: @t29
+; CHECK-LABEL: @t29(
   %ret = call i32 @ffsll(i64 %y)
   ret i32 %ret
 ; CHECK: call i32 @ffsll
 }
 
 define void @t30() {
-; CHECK: @t30
+; CHECK-LABEL: @t30(
   %x = getelementptr inbounds [13 x i8]* @.str1, i32 0, i32 0
   call i32 @fprintf(i8* null, i8* %x)
   ret void
@@ -284,42 +284,42 @@ define void @t30() {
 }
 
 define i32 @t31(i32 %y) {
-; CHECK: @t31
+; CHECK-LABEL: @t31(
   %ret = call i32 @isascii(i32 %y)
   ret i32 %ret
 ; CHECK: call i32 @isascii
 }
 
 define i32 @t32(i32 %y) {
-; CHECK: @t32
+; CHECK-LABEL: @t32(
   %ret = call i32 @isdigit(i32 %y)
   ret i32 %ret
 ; CHECK: call i32 @isdigit
 }
 
 define i32 @t33(i32 %y) {
-; CHECK: @t33
+; CHECK-LABEL: @t33(
   %ret = call i32 @toascii(i32 %y)
   ret i32 %ret
 ; CHECK: call i32 @toascii
 }
 
 define i64 @t34(i64 %y) {
-; CHECK: @t34
+; CHECK-LABEL: @t34(
   %ret = call i64 @labs(i64 %y)
   ret i64 %ret
 ; CHECK: call i64 @labs
 }
 
 define i64 @t35(i64 %y) {
-; CHECK: @t35
+; CHECK-LABEL: @t35(
   %ret = call i64 @llabs(i64 %y)
   ret i64 %ret
 ; CHECK: call i64 @llabs
 }
 
 define void @t36() {
-; CHECK: @t36
+; CHECK-LABEL: @t36(
   %x = getelementptr inbounds [1 x i8]* @empty, i32 0, i32 0
   call i32 @printf(i8* %x)
   ret void
@@ -327,7 +327,7 @@ define void @t36() {
 }
 
 define void @t37(i8* %x) {
-; CHECK: @t37
+; CHECK-LABEL: @t37(
   %y = getelementptr inbounds [13 x i8]* @.str1, i32 0, i32 0
   call i32 @sprintf(i8* %x, i8* %y)
   ret void
diff --git a/test/Transforms/InstCombine/div-shift-crash.ll b/test/Transforms/InstCombine/div-shift-crash.ll
new file mode 100644
index 0000000..a619724
--- /dev/null
+++ b/test/Transforms/InstCombine/div-shift-crash.ll
@@ -0,0 +1,101 @@
+; RUN: opt -instcombine < %s
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.S0.0.1.2.3.4.13.22.31.44.48.53.54.55.56.58.59.60.66.68.70.74.77.106.107.108.109.110.113.117.118.128.129 = type <{ i64 }>
+
+; Function Attrs: nounwind
+define void @main() #0 {
+entry:
+  %l_819.i.i = alloca %struct.S0.0.1.2.3.4.13.22.31.44.48.53.54.55.56.58.59.60.66.68.70.74.77.106.107.108.109.110.113.117.118.128.129, align 8
+  br i1 undef, label %land.lhs.true, label %for.cond.i
+
+land.lhs.true:                                    ; preds = %entry
+  br label %for.cond.i
+
+for.cond.i:                                       ; preds = %land.lhs.true, %entry
+  %0 = getelementptr inbounds %struct.S0.0.1.2.3.4.13.22.31.44.48.53.54.55.56.58.59.60.66.68.70.74.77.106.107.108.109.110.113.117.118.128.129* %l_819.i.i, i64 0, i32 0
+  br label %for.cond.i6.i.i
+
+for.cond.i6.i.i:                                  ; preds = %for.body.i8.i.i, %for.cond.i
+  br i1 undef, label %for.body.i8.i.i, label %lbl_707.i.i.i
+
+for.body.i8.i.i:                                  ; preds = %for.cond.i6.i.i
+  br label %for.cond.i6.i.i
+
+lbl_707.i.i.i:                                    ; preds = %for.cond.i6.i.i
+  br i1 undef, label %lor.rhs.i.i.i, label %lor.end.i.i.i
+
+lor.rhs.i.i.i:                                    ; preds = %lbl_707.i.i.i
+  br label %lor.end.i.i.i
+
+lor.end.i.i.i:                                    ; preds = %lor.rhs.i.i.i, %lbl_707.i.i.i
+  br label %for.cond1.i.i.i.i
+
+for.cond1.i.i.i.i:                                ; preds = %for.body4.i.i.i.i, %lor.end.i.i.i
+  br i1 undef, label %for.body4.i.i.i.i, label %func_39.exit.i.i
+
+for.body4.i.i.i.i:                                ; preds = %for.cond1.i.i.i.i
+  br label %for.cond1.i.i.i.i
+
+func_39.exit.i.i:                                 ; preds = %for.cond1.i.i.i.i
+  %l_8191.sroa.0.0.copyload.i.i = load i64* %0, align 1
+  br label %for.cond1.i.i.i
+
+for.cond1.i.i.i:                                  ; preds = %safe_div_func_uint32_t_u_u.exit.i.i.i, %func_39.exit.i.i
+  br i1 undef, label %for.cond7.i.i.i, label %func_11.exit.i
+
+for.cond7.i.i.i:                                  ; preds = %for.end30.i.i.i, %for.cond1.i.i.i
+  %storemerge.i.i.i = phi i32 [ %sub.i.i.i, %for.end30.i.i.i ], [ 4, %for.cond1.i.i.i ]
+  br i1 undef, label %for.cond22.i.i.i, label %for.end32.i.i.i
+
+for.cond22.i.i.i:                                 ; preds = %for.body25.i.i.i, %for.cond7.i.i.i
+  br i1 undef, label %for.body25.i.i.i, label %for.end30.i.i.i
+
+for.body25.i.i.i:                                 ; preds = %for.cond22.i.i.i
+  br label %for.cond22.i.i.i
+
+for.end30.i.i.i:                                  ; preds = %for.cond22.i.i.i
+  %sub.i.i.i = add nsw i32 0, -1
+  br label %for.cond7.i.i.i
+
+for.end32.i.i.i:                                  ; preds = %for.cond7.i.i.i
+  %conv33.i.i.i = trunc i64 %l_8191.sroa.0.0.copyload.i.i to i32
+  %xor.i.i.i.i = xor i32 %storemerge.i.i.i, -701565022
+  %sub.i.i.i.i = sub nsw i32 0, %storemerge.i.i.i
+  %xor3.i.i.i.i = xor i32 %sub.i.i.i.i, %storemerge.i.i.i
+  %and4.i.i.i.i = and i32 %xor.i.i.i.i, %xor3.i.i.i.i
+  %cmp.i.i.i.i = icmp slt i32 %and4.i.i.i.i, 0
+  %sub5.i.i.i.i = sub nsw i32 -701565022, %storemerge.i.i.i
+  %.sub5.i.i.i.i = select i1 %cmp.i.i.i.i, i32 -701565022, i32 %sub5.i.i.i.i
+  br i1 undef, label %safe_div_func_uint32_t_u_u.exit.i.i.i, label %cond.false.i.i.i.i
+
+cond.false.i.i.i.i:                               ; preds = %for.end32.i.i.i
+  %div.i.i.i.i = udiv i32 %conv33.i.i.i, %.sub5.i.i.i.i
+  br label %safe_div_func_uint32_t_u_u.exit.i.i.i
+
+safe_div_func_uint32_t_u_u.exit.i.i.i:            ; preds = %cond.false.i.i.i.i, %for.end32.i.i.i
+  %cond.i.i.i.i = phi i32 [ %div.i.i.i.i, %cond.false.i.i.i.i ], [ %conv33.i.i.i, %for.end32.i.i.i ]
+  %cmp35.i.i.i = icmp ne i32 %cond.i.i.i.i, -7
+  br label %for.cond1.i.i.i
+
+func_11.exit.i:                                   ; preds = %for.cond1.i.i.i
+  br i1 undef, label %for.body, label %for.end
+
+for.body:                                         ; preds = %func_11.exit.i
+  unreachable
+
+for.end:                                          ; preds = %func_11.exit.i
+  br label %for.cond15
+
+for.cond15:                                       ; preds = %for.cond19, %for.end
+  br i1 undef, label %for.cond19, label %for.end45
+
+for.cond19:                                       ; preds = %for.cond15
+  br label %for.cond15
+
+for.end45:                                        ; preds = %for.cond15
+  unreachable
+}
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/Transforms/InstCombine/div-shift.ll b/test/Transforms/InstCombine/div-shift.ll
index e0372eb..3350f19 100644
--- a/test/Transforms/InstCombine/div-shift.ll
+++ b/test/Transforms/InstCombine/div-shift.ll
@@ -35,3 +35,41 @@ define i64 @t3(i64 %x, i32 %y) nounwind  {
   %3 = udiv i64 %x, %2
   ret i64 %3
 }
+
+define i32 @t4(i32 %x, i32 %y) nounwind {
+; CHECK: t4
+; CHECK-NOT: udiv
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 %y, 5
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP]], i32 5, i32 %y
+; CHECK-NEXT: [[SHR:%.*]] = lshr i32 %x, [[SEL]]
+; CHECK-NEXT: ret i32 [[SHR]]
+  %1 = shl i32 1, %y
+  %2 = icmp ult i32 %1, 32
+  %3 = select i1 %2, i32 32, i32 %1
+  %4 = udiv i32 %x, %3
+  ret i32 %4
+}
+
+define i32 @t5(i1 %x, i1 %y, i32 %V) nounwind {
+; CHECK: t5
+; CHECK-NOT: udiv
+; CHECK-NEXT: [[SEL1:%.*]] = select i1 %x, i32 5, i32 6
+; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 %V, [[SEL1]]
+; CHECK-NEXT: [[SEL2:%.*]] = select i1 %y, i32 [[LSHR]], i32 0
+; CHECK-NEXT: ret i32 [[SEL2]]
+  %1 = shl i32 1, %V
+  %2 = select i1 %x, i32 32, i32 64
+  %3 = select i1 %y, i32 %2, i32 %1
+  %4 = udiv i32 %V, %3
+  ret i32 %4
+}
+
+define i32 @t6(i32 %x, i32 %z) nounwind{
+; CHECK: t6
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 %x, 0
+; CHECK-NOT: udiv i32 %z, %x
+  %x_is_zero = icmp eq i32 %x, 0
+  %divisor = select i1 %x_is_zero, i32 1, i32 %x
+  %y = udiv i32 %z, %divisor
+  ret i32 %y
+}
diff --git a/test/Transforms/InstCombine/div.ll b/test/Transforms/InstCombine/div.ll
index 8a0897b..f67fd1c 100644
--- a/test/Transforms/InstCombine/div.ll
+++ b/test/Transforms/InstCombine/div.ll
@@ -5,7 +5,7 @@
 define i32 @test1(i32 %A) {
         %B = sdiv i32 %A, 1             ; <i32> [#uses=1]
         ret i32 %B
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: ret i32 %A
 }
 
@@ -13,7 +13,7 @@ define i32 @test2(i32 %A) {
         ; => Shift
         %B = udiv i32 %A, 8             ; <i32> [#uses=1]
         ret i32 %B
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: lshr i32 %A, 3
 }
 
@@ -21,7 +21,7 @@ define i32 @test3(i32 %A) {
         ; => 0, don't need to keep traps
         %B = sdiv i32 0, %A             ; <i32> [#uses=1]
         ret i32 %B
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: ret i32 0
 }
 
@@ -29,7 +29,7 @@ define i32 @test4(i32 %A) {
         ; 0-A
         %B = sdiv i32 %A, -1            ; <i32> [#uses=1]
         ret i32 %B
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: sub i32 0, %A
 }
 
@@ -37,7 +37,7 @@ define i32 @test5(i32 %A) {
         %B = udiv i32 %A, -16           ; <i32> [#uses=1]
         %C = udiv i32 %B, -4            ; <i32> [#uses=1]
         ret i32 %C
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NEXT: ret i32 0
 }
 
@@ -46,7 +46,7 @@ define i1 @test6(i32 %A) {
         ; A < 123
         %C = icmp eq i32 %B, 0          ; <i1> [#uses=1]
         ret i1 %C
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: icmp ult i32 %A, 123
 }
 
@@ -55,7 +55,7 @@ define i1 @test7(i32 %A) {
         ; A >= 20 && A < 30
         %C = icmp eq i32 %B, 2          ; <i1> [#uses=1]
         ret i1 %C
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NEXT: add i32 %A, -20
 ; CHECK-NEXT: icmp ult i32
 }
@@ -65,7 +65,7 @@ define i1 @test8(i8 %A) {
         ; A >= 246
         %C = icmp eq i8 %B, 2           ; <i1> [#uses=1]
         ret i1 %C
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK-NEXT: icmp ugt i8 %A, -11
 }
 
@@ -74,7 +74,7 @@ define i1 @test9(i8 %A) {
         ; A < 246
         %C = icmp ne i8 %B, 2           ; <i1> [#uses=1]
         ret i1 %C
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NEXT: icmp ult i8 %A, -10
 }
 
@@ -82,7 +82,7 @@ define i32 @test10(i32 %X, i1 %C) {
         %V = select i1 %C, i32 64, i32 8                ; <i32> [#uses=1]
         %R = udiv i32 %X, %V            ; <i32> [#uses=1]
         ret i32 %R
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK-NEXT: select i1 %C, i32 6, i32 3
 ; CHECK-NEXT: lshr i32 %X
 }
@@ -91,7 +91,7 @@ define i32 @test11(i32 %X, i1 %C) {
         %A = select i1 %C, i32 1024, i32 32             ; <i32> [#uses=1]
         %B = udiv i32 %X, %A            ; <i32> [#uses=1]
         ret i32 %B
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK-NEXT: select i1 %C, i32 10, i32 5
 ; CHECK-NEXT: lshr i32 %X
 }
@@ -100,14 +100,14 @@ define i32 @test11(i32 %X, i1 %C) {
 define i32 @test12(i32 %x) nounwind  {
 	%tmp3 = udiv i32 %x, %x		; 1
 	ret i32 %tmp3
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK-NEXT: ret i32 1
 }
 
 define i32 @test13(i32 %x) nounwind  {
 	%tmp3 = sdiv i32 %x, %x		; 1
 	ret i32 %tmp3
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK-NEXT: ret i32 1
 }
 
@@ -115,7 +115,7 @@ define i32 @test14(i8 %x) nounwind {
 	%zext = zext i8 %x to i32
 	%div = udiv i32 %zext, 257	; 0
 	ret i32 %div
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK-NEXT: ret i32 0
 }
 
@@ -125,7 +125,7 @@ define i32 @test15(i32 %a, i32 %b) nounwind {
   %div = lshr i32 %shl, 2
   %div2 = udiv i32 %a, %div
   ret i32 %div2
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 ; CHECK-NEXT: add i32 %b, -2
 ; CHECK-NEXT: lshr i32 %a, 
 ; CHECK-NEXT: ret i32
diff --git a/test/Transforms/InstCombine/exact.ll b/test/Transforms/InstCombine/exact.ll
index 88ca88c..868d60a 100644
--- a/test/Transforms/InstCombine/exact.ll
+++ b/test/Transforms/InstCombine/exact.ll
@@ -1,20 +1,20 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
-; CHECK: @sdiv1
+; CHECK-LABEL: @sdiv1(
 ; CHECK: sdiv i32 %x, 8
 define i32 @sdiv1(i32 %x) {
   %y = sdiv i32 %x, 8
   ret i32 %y
 }
 
-; CHECK: @sdiv2
+; CHECK-LABEL: @sdiv2(
 ; CHECK: ashr exact i32 %x, 3
 define i32 @sdiv2(i32 %x) {
   %y = sdiv exact i32 %x, 8
   ret i32 %y
 }
 
-; CHECK: @sdiv3
+; CHECK-LABEL: @sdiv3(
 ; CHECK: %y = srem i32 %x, 3
 ; CHECK: %z = sub i32 %x, %y
 ; CHECK: ret i32 %z
@@ -24,7 +24,7 @@ define i32 @sdiv3(i32 %x) {
   ret i32 %z
 }
 
-; CHECK: @sdiv4
+; CHECK-LABEL: @sdiv4(
 ; CHECK: ret i32 %x
 define i32 @sdiv4(i32 %x) {
   %y = sdiv exact i32 %x, 3
@@ -42,7 +42,7 @@ define i32 @sdiv5(i32 %x) {
   ret i32 %z
 }
 
-; CHECK: @sdiv6
+; CHECK-LABEL: @sdiv6(
 ; CHECK: %z = sub i32 0, %x
 ; CHECK: ret i32 %z
 define i32 @sdiv6(i32 %x) {
@@ -51,7 +51,7 @@ define i32 @sdiv6(i32 %x) {
   ret i32 %z
 }
 
-; CHECK: @udiv1
+; CHECK-LABEL: @udiv1(
 ; CHECK: ret i32 %x
 define i32 @udiv1(i32 %x, i32 %w) {
   %y = udiv exact i32 %x, %w
@@ -59,7 +59,7 @@ define i32 @udiv1(i32 %x, i32 %w) {
   ret i32 %z
 }
 
-; CHECK: @udiv2
+; CHECK-LABEL: @udiv2(
 ; CHECK: %z = lshr exact i32 %x, %w
 ; CHECK: ret i32 %z
 define i32 @udiv2(i32 %x, i32 %w) {
@@ -68,7 +68,7 @@ define i32 @udiv2(i32 %x, i32 %w) {
   ret i32 %z
 }
 
-; CHECK: @ashr1
+; CHECK-LABEL: @ashr1(
 ; CHECK: %B = ashr exact i64 %A, 2
 ; CHECK: ret i64 %B
 define i64 @ashr1(i64 %X) nounwind {
@@ -78,7 +78,7 @@ define i64 @ashr1(i64 %X) nounwind {
 }
 
 ; PR9120
-; CHECK: @ashr_icmp1
+; CHECK-LABEL: @ashr_icmp1(
 ; CHECK: %B = icmp eq i64 %X, 0
 ; CHECK: ret i1 %B
 define i1 @ashr_icmp1(i64 %X) nounwind {
@@ -87,7 +87,7 @@ define i1 @ashr_icmp1(i64 %X) nounwind {
   ret i1 %B
 }
 
-; CHECK: @ashr_icmp2
+; CHECK-LABEL: @ashr_icmp2(
 ; CHECK: %Z = icmp slt i64 %X, 16
 ; CHECK: ret i1 %Z
 define i1 @ashr_icmp2(i64 %X) nounwind {
@@ -98,7 +98,7 @@ define i1 @ashr_icmp2(i64 %X) nounwind {
 
 ; PR9998
 ; Make sure we don't transform the ashr here into an sdiv
-; CHECK: @pr9998
+; CHECK-LABEL: @pr9998(
 ; CHECK:      [[BIT:%[A-Za-z0-9.]+]] = and i32 %V, 1
 ; CHECK-NEXT: [[CMP:%[A-Za-z0-9.]+]] = icmp ne i32 [[BIT]], 0
 ; CHECK-NEXT: ret i1 [[CMP]]
@@ -113,7 +113,7 @@ entry:
 
 
 
-; CHECK: @udiv_icmp1
+; CHECK-LABEL: @udiv_icmp1(
 ; CHECK: icmp ne i64 %X, 0
 define i1 @udiv_icmp1(i64 %X) nounwind {
   %A = udiv exact i64 %X, 5   ; X/5
@@ -121,7 +121,7 @@ define i1 @udiv_icmp1(i64 %X) nounwind {
   ret i1 %B
 }
 
-; CHECK: @sdiv_icmp1
+; CHECK-LABEL: @sdiv_icmp1(
 ; CHECK: icmp eq i64 %X, 0
 define i1 @sdiv_icmp1(i64 %X) nounwind {
   %A = sdiv exact i64 %X, 5   ; X/5 == 0 --> x == 0
@@ -129,7 +129,7 @@ define i1 @sdiv_icmp1(i64 %X) nounwind {
   ret i1 %B
 }
 
-; CHECK: @sdiv_icmp2
+; CHECK-LABEL: @sdiv_icmp2(
 ; CHECK: icmp eq i64 %X, 5
 define i1 @sdiv_icmp2(i64 %X) nounwind {
   %A = sdiv exact i64 %X, 5   ; X/5 == 1 --> x == 5
@@ -137,7 +137,7 @@ define i1 @sdiv_icmp2(i64 %X) nounwind {
   ret i1 %B
 }
 
-; CHECK: @sdiv_icmp3
+; CHECK-LABEL: @sdiv_icmp3(
 ; CHECK: icmp eq i64 %X, -5
 define i1 @sdiv_icmp3(i64 %X) nounwind {
   %A = sdiv exact i64 %X, 5   ; X/5 == -1 --> x == -5
@@ -145,7 +145,7 @@ define i1 @sdiv_icmp3(i64 %X) nounwind {
   ret i1 %B
 }
 
-; CHECK: @sdiv_icmp4
+; CHECK-LABEL: @sdiv_icmp4(
 ; CHECK: icmp eq i64 %X, 0
 define i1 @sdiv_icmp4(i64 %X) nounwind {
   %A = sdiv exact i64 %X, -5   ; X/-5 == 0 --> x == 0
@@ -153,7 +153,7 @@ define i1 @sdiv_icmp4(i64 %X) nounwind {
   ret i1 %B
 }
 
-; CHECK: @sdiv_icmp5
+; CHECK-LABEL: @sdiv_icmp5(
 ; CHECK: icmp eq i64 %X, -5
 define i1 @sdiv_icmp5(i64 %X) nounwind {
   %A = sdiv exact i64 %X, -5   ; X/-5 == 1 --> x == -5
@@ -161,7 +161,7 @@ define i1 @sdiv_icmp5(i64 %X) nounwind {
   ret i1 %B
 }
 
-; CHECK: @sdiv_icmp6
+; CHECK-LABEL: @sdiv_icmp6(
 ; CHECK: icmp eq i64 %X, 5
 define i1 @sdiv_icmp6(i64 %X) nounwind {
   %A = sdiv exact i64 %X, -5   ; X/-5 == 1 --> x == 5
diff --git a/test/Transforms/InstCombine/exp2-1.ll b/test/Transforms/InstCombine/exp2-1.ll
index 1b0ad50..99fb9ec 100644
--- a/test/Transforms/InstCombine/exp2-1.ll
+++ b/test/Transforms/InstCombine/exp2-1.ll
@@ -10,7 +10,7 @@ declare float @exp2f(float)
 ; Check exp2(sitofp(x)) -> ldexp(1.0, sext(x)).
 
 define double @test_simplify1(i32 %x) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %conv = sitofp i32 %x to double
   %ret = call double @exp2(double %conv)
 ; CHECK: call double @ldexp
@@ -18,7 +18,7 @@ define double @test_simplify1(i32 %x) {
 }
 
 define double @test_simplify2(i16 signext %x) {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %conv = sitofp i16 %x to double
   %ret = call double @exp2(double %conv)
 ; CHECK: call double @ldexp
@@ -26,7 +26,7 @@ define double @test_simplify2(i16 signext %x) {
 }
 
 define double @test_simplify3(i8 signext %x) {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %conv = sitofp i8 %x to double
   %ret = call double @exp2(double %conv)
 ; CHECK: call double @ldexp
@@ -34,7 +34,7 @@ define double @test_simplify3(i8 signext %x) {
 }
 
 define float @test_simplify4(i32 %x) {
-; CHECK: @test_simplify4
+; CHECK-LABEL: @test_simplify4(
   %conv = sitofp i32 %x to float
   %ret = call float @exp2f(float %conv)
 ; CHECK: call float @ldexpf
@@ -44,7 +44,7 @@ define float @test_simplify4(i32 %x) {
 ; Check exp2(uitofp(x)) -> ldexp(1.0, zext(x)).
 
 define double @test_no_simplify1(i32 %x) {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %conv = uitofp i32 %x to double
   %ret = call double @exp2(double %conv)
 ; CHECK: call double @exp2
@@ -52,7 +52,7 @@ define double @test_no_simplify1(i32 %x) {
 }
 
 define double @test_simplify6(i16 zeroext %x) {
-; CHECK: @test_simplify6
+; CHECK-LABEL: @test_simplify6(
   %conv = uitofp i16 %x to double
   %ret = call double @exp2(double %conv)
 ; CHECK: call double @ldexp
@@ -60,7 +60,7 @@ define double @test_simplify6(i16 zeroext %x) {
 }
 
 define double @test_simplify7(i8 zeroext %x) {
-; CHECK: @test_simplify7
+; CHECK-LABEL: @test_simplify7(
   %conv = uitofp i8 %x to double
   %ret = call double @exp2(double %conv)
 ; CHECK: call double @ldexp
@@ -68,7 +68,7 @@ define double @test_simplify7(i8 zeroext %x) {
 }
 
 define float @test_simplify8(i8 zeroext %x) {
-; CHECK: @test_simplify8
+; CHECK-LABEL: @test_simplify8(
   %conv = uitofp i8 %x to float
   %ret = call float @exp2f(float %conv)
 ; CHECK: call float @ldexpf
diff --git a/test/Transforms/InstCombine/exp2-2.ll b/test/Transforms/InstCombine/exp2-2.ll
index bed0637..19368dc 100644
--- a/test/Transforms/InstCombine/exp2-2.ll
+++ b/test/Transforms/InstCombine/exp2-2.ll
@@ -9,7 +9,7 @@ declare float @exp2(double)
 ; Check that exp2 functions with the wrong prototype aren't simplified.
 
 define float @test_no_simplify1(i32 %x) {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %conv = sitofp i32 %x to double
   %ret = call float @exp2(double %conv)
 ; CHECK: call float @exp2(double %conv)
diff --git a/test/Transforms/InstCombine/extractvalue.ll b/test/Transforms/InstCombine/extractvalue.ll
index 5e4c677..04c7ffa 100644
--- a/test/Transforms/InstCombine/extractvalue.ll
+++ b/test/Transforms/InstCombine/extractvalue.ll
@@ -3,7 +3,7 @@
 declare void @bar({i32, i32} %a)
 declare i32 @baz(i32 %a)
 
-; CHECK: define i32 @foo
+; CHECK-LABEL: define i32 @foo(
 ; CHECK-NOT: extractvalue
 define i32 @foo(i32 %a, i32 %b) {
 ; Instcombine should fold various combinations of insertvalue and extractvalue
@@ -39,7 +39,7 @@ define i32 @foo(i32 %a, i32 %b) {
         ret i32 %v5
 }
 
-; CHECK: define i32 @extract2gep
+; CHECK-LABEL: define i32 @extract2gep(
 ; CHECK-NEXT: [[GEP:%[a-z0-9]+]] = getelementptr inbounds {{.*}}* %pair, i32 0, i32 1
 ; CHECK-NEXT: [[LOAD:%[A-Za-z0-9]+]] = load i32* [[GEP]]
 ; CHECK-NEXT: store
@@ -67,7 +67,7 @@ end:
         ret i32 %E
 }
 
-; CHECK: define i32 @doubleextract2gep
+; CHECK-LABEL: define i32 @doubleextract2gep(
 ; CHECK-NEXT: [[GEP:%[a-z0-9]+]] = getelementptr inbounds {{.*}}* %arg, i32 0, i32 1, i32 1
 ; CHECK-NEXT: [[LOAD:%[A-Za-z0-9]+]] = load i32* [[GEP]]
 ; CHECK-NEXT: ret i32 [[LOAD]]
diff --git a/test/Transforms/InstCombine/fast-math.ll b/test/Transforms/InstCombine/fast-math.ll
index edcbcc7..a9a7015 100644
--- a/test/Transforms/InstCombine/fast-math.ll
+++ b/test/Transforms/InstCombine/fast-math.ll
@@ -6,14 +6,14 @@ define float @fold(float %a) {
   %mul = fmul fast float %a, 0x3FF3333340000000
   %mul1 = fmul fast float %mul, 0x4002666660000000
   ret float %mul1
-; CHECK: @fold
+; CHECK-LABEL: @fold(
 ; CHECK: fmul fast float %a, 0x4006147AE0000000
 }
 
 ; Same testing-case as the one used in fold() except that the operators have
 ; fixed FP mode.
 define float @notfold(float %a) {
-; CHECK: @notfold
+; CHECK-LABEL: @notfold(
 ; CHECK: %mul = fmul fast float %a, 0x3FF3333340000000
   %mul = fmul fast float %a, 0x3FF3333340000000
   %mul1 = fmul float %mul, 0x4002666660000000
@@ -21,7 +21,7 @@ define float @notfold(float %a) {
 }
 
 define float @fold2(float %a) {
-; CHECK: @fold2
+; CHECK-LABEL: @fold2(
 ; CHECK: fmul fast float %a, 0x4006147AE0000000
   %mul = fmul float %a, 0x3FF3333340000000
   %mul1 = fmul fast float %mul, 0x4002666660000000
@@ -33,7 +33,7 @@ define double @fold3(double %f1) {
   %t1 = fmul fast double 2.000000e+00, %f1
   %t2 = fadd fast double %f1, %t1
   ret double %t2
-; CHECK: @fold3
+; CHECK-LABEL: @fold3(
 ; CHECK: fmul fast double %f1, 3.000000e+00
 }
 
@@ -43,7 +43,7 @@ define float @fold4(float %f1, float %f2) {
   %sub1 = fsub float 5.000000e+00, %f2
   %add = fadd fast float %sub, %sub1
   ret float %add
-; CHECK: @fold4
+; CHECK-LABEL: @fold4(
 ; CHECK: %1 = fadd fast float %f1, %f2
 ; CHECK: fsub fast float 9.000000e+00, %1
 }
@@ -53,7 +53,7 @@ define float @fold5(float %f1, float %f2) {
   %add = fadd float %f1, 4.000000e+00
   %add1 = fadd fast float %add, 5.000000e+00
   ret float %add1
-; CHECK: @fold5
+; CHECK-LABEL: @fold5(
 ; CHECK: fadd fast float %f1, 9.000000e+00
 }
 
@@ -62,7 +62,7 @@ define float @fold6(float %f1) {
   %t1 = fadd fast float %f1, %f1
   %t2 = fadd fast float %f1, %t1
   ret float %t2
-; CHECK: @fold6
+; CHECK-LABEL: @fold6(
 ; CHECK: fmul fast float %f1, 3.000000e+00
 }
 
@@ -72,7 +72,7 @@ define float @fold7(float %f1) {
   %t2 = fadd fast float %f1, %f1
   %t3 = fadd fast float %t1, %t2
   ret float %t3
-; CHECK: @fold7
+; CHECK-LABEL: @fold7(
 ; CHECK: fmul fast float %f1, 7.000000e+00
 }
 
@@ -92,7 +92,7 @@ define float @fold9(float %f1, float %f2) {
   %t3 = fsub fast float %f1, %t1
   ret float %t3
 
-; CHECK: @fold9
+; CHECK-LABEL: @fold9(
 ; CHECK: fsub fast float 0.000000e+00, %f2
 }
 
@@ -106,7 +106,7 @@ define float @fold10(float %f1, float %f2) {
   %t2 = fsub fast float %f2, 3.000000e+00
   %t3 = fadd fast float %t1, %t2
   ret float %t3
-; CHECK: @fold10
+; CHECK-LABEL: @fold10(
 ; CHECK: %t3 = fadd fast float %t2, -1.000000e+00
 ; CHECK: ret float %t3
 }
@@ -117,7 +117,7 @@ define float @fail1(float %f1, float %f2) {
   %add = fadd fast float %conv3, %conv3
   %add2 = fadd fast float %add, %conv3
   ret float %add2
-; CHECK: @fail1
+; CHECK-LABEL: @fail1(
 ; CHECK: ret
 }
 
@@ -126,7 +126,7 @@ define double @fail2(double %f1, double %f2) {
   %t2 = fadd fast double %f1, %f2
   %t3 = fsub fast double %t1, %t2
   ret double %t3
-; CHECK: @fail2
+; CHECK-LABEL: @fail2(
 ; CHECK: ret
 }
 
@@ -152,7 +152,7 @@ define float @fmul_distribute1(float %f1) {
   %t2 = fadd float %t1, 2.0e+3
   %t3 = fmul fast float %t2, 5.0e+3
   ret float %t3
-; CHECK: @fmul_distribute1
+; CHECK-LABEL: @fmul_distribute1(
 ; CHECK: %1 = fmul fast float %f1, 3.000000e+07
 ; CHECK: %t3 = fadd fast float %1, 1.000000e+07
 }
@@ -165,7 +165,7 @@ define double @fmul_distribute2(double %f1, double %f2) {
   %t3 = fmul fast double %t2, 0x10000000000000
   ret double %t3
 
-; CHECK: @fmul_distribute2
+; CHECK-LABEL: @fmul_distribute2(
 ; CHECK: %1 = fdiv fast double %f1, 0x7FE8000000000000
 ; CHECK: fadd fast double %1, 0x69000000000000
 }
@@ -178,7 +178,7 @@ define double @fmul_distribute3(double %f1) {
   %t3 = fmul fast double %t2, 0x10000000000000
   ret double %t3
 
-; CHECK: @fmul_distribute3
+; CHECK-LABEL: @fmul_distribute3(
 ; CHECK: fmul fast double %t2, 0x10000000000000
 }
 
@@ -188,7 +188,7 @@ define float @fmul_distribute4(float %f1) {
   %t2 = fsub float 2.0e+3, %t1
   %t3 = fmul fast float %t2, 5.0e+3
   ret float %t3
-; CHECK: @fmul_distribute4
+; CHECK-LABEL: @fmul_distribute4(
 ; CHECK: %1 = fmul fast float %f1, 3.000000e+07
 ; CHECK: %t3 = fsub fast float 1.000000e+07, %1
 }
@@ -198,7 +198,7 @@ define float @fmul2(float %f1) {
   %t1 = fdiv float 2.0e+3, %f1
   %t3 = fmul fast float %t1, 6.0e+3
   ret float %t3
-; CHECK: @fmul2
+; CHECK-LABEL: @fmul2(
 ; CHECK: fdiv fast float 1.200000e+07, %f1
 }
 
@@ -207,7 +207,7 @@ define float @fmul3(float %f1, float %f2) {
   %t1 = fdiv float %f1, 2.0e+3
   %t3 = fmul fast float %t1, 6.0e+3
   ret float %t3
-; CHECK: @fmul3
+; CHECK-LABEL: @fmul3(
 ; CHECK: fmul fast float %f1, 3.000000e+00
 }
 
@@ -218,7 +218,7 @@ define float @fmul4(float %f1, float %f2) {
   %t1 = fdiv float %f1, 2.0e+3
   %t3 = fmul fast float %t1, 0x3810000000000000
   ret float %t3
-; CHECK: @fmul4
+; CHECK-LABEL: @fmul4(
 ; CHECK: fmul fast float %t1, 0x3810000000000000
 }
 
@@ -229,7 +229,7 @@ define float @fmul5(float %f1, float %f2) {
   %t1 = fdiv float %f1, 3.0e+0
   %t3 = fmul fast float %t1, 0x3810000000000000
   ret float %t3
-; CHECK: @fmul5
+; CHECK-LABEL: @fmul5(
 ; CHECK: fdiv fast float %f1, 0x47E8000000000000
 }
 
@@ -238,7 +238,7 @@ define float @fmul6(float %f1, float %f2) {
   %mul = fmul float %f1, %f2
   %mul1 = fmul fast float %mul, %f1
   ret float %mul1
-; CHECK: @fmul6
+; CHECK-LABEL: @fmul6(
 ; CHECK: fmul fast float %f1, %f1
 }
 
@@ -248,7 +248,7 @@ define float @fmul7(float %f1, float %f2) {
   %mul1 = fmul fast float %mul, %f1
   %add = fadd float %mul1, %mul
   ret float %add
-; CHECK: @fmul7
+; CHECK-LABEL: @fmul7(
 ; CHECK: fmul fast float %mul, %f1
 }
 
@@ -262,7 +262,7 @@ define float @fneg1(float %f1, float %f2) {
   %sub1 = fsub nsz float 0.000000e+00, %f2
   %mul = fmul float %sub, %sub1
   ret float %mul
-; CHECK: @fneg1
+; CHECK-LABEL: @fneg1(
 ; CHECK: fmul float %f1, %f2
 }
 
@@ -280,7 +280,7 @@ define float @fdiv1(float %x) {
 ; 0x3FF3333340000000 = 1.2f
 ; 0x4002666660000000 = 2.3f
 ; 0x3FD7303B60000000 = 0.36231884057971014492
-; CHECK: @fdiv1
+; CHECK-LABEL: @fdiv1(
 ; CHECK: fmul fast float %x, 0x3FD7303B60000000
 }
 
@@ -293,7 +293,7 @@ define float @fdiv2(float %x) {
 ; 0x3FF3333340000000 = 1.2f
 ; 0x4002666660000000 = 2.3f
 ; 0x3FE0B21660000000 = 0.52173918485641479492
-; CHECK: @fdiv2
+; CHECK-LABEL: @fdiv2(
 ; CHECK: fmul fast float %x, 0x3FE0B21660000000
 }
 
@@ -303,7 +303,7 @@ define float @fdiv3(float %x) {
   %div = fdiv float %x, 0x47EFFFFFE0000000
   %div1 = fdiv fast float %div, 0x4002666660000000
   ret float %div1
-; CHECK: @fdiv3
+; CHECK-LABEL: @fdiv3(
 ; CHECK: fdiv float %x, 0x47EFFFFFE0000000
 }
 
@@ -312,7 +312,7 @@ define float @fdiv4(float %x) {
   %mul = fmul float %x, 0x47EFFFFFE0000000
   %div = fdiv float %mul, 0x3FC99999A0000000
   ret float %div
-; CHECK: @fdiv4
+; CHECK-LABEL: @fdiv4(
 ; CHECK: fmul float %x, 0x47EFFFFFE0000000
 }
 
@@ -321,7 +321,7 @@ define float @fdiv5(float %f1, float %f2, float %f3) {
   %t1 = fdiv float %f1, %f2
   %t2 = fdiv fast float %t1, %f3
   ret float %t2
-; CHECK: @fdiv5
+; CHECK-LABEL: @fdiv5(
 ; CHECK: fmul float %f2, %f3
 }
 
@@ -330,7 +330,7 @@ define float @fdiv6(float %f1, float %f2, float %f3) {
   %t1 = fdiv float %f1, %f2
   %t2 = fdiv fast float %f3, %t1
   ret float %t2
-; CHECK: @fdiv6
+; CHECK-LABEL: @fdiv6(
 ; CHECK: fmul float %f3, %f2
 }
 
@@ -339,7 +339,7 @@ define float @fdiv7(float %x) {
   %t1 = fmul float %x, 3.0e0
   %t2 = fdiv fast float 15.0e0, %t1
   ret float %t2
-; CHECK: @fdiv7
+; CHECK-LABEL: @fdiv7(
 ; CHECK: fdiv fast float 5.000000e+00, %x
 }
 
@@ -348,7 +348,7 @@ define float @fdiv8(float %x) {
   %t1 = fdiv float %x, 3.0e0
   %t2 = fdiv fast float 15.0e0, %t1
   ret float %t2
-; CHECK: @fdiv8
+; CHECK-LABEL: @fdiv8(
 ; CHECK: fdiv fast float 4.500000e+01, %x
 }
 
@@ -357,7 +357,7 @@ define float @fdiv9(float %x) {
   %t1 = fdiv float 3.0e0, %x
   %t2 = fdiv fast float 15.0e0, %t1
   ret float %t2
-; CHECK: @fdiv9
+; CHECK-LABEL: @fdiv9(
 ; CHECK: fmul fast float %x, 5.000000e+00
 }
 
@@ -372,7 +372,7 @@ define float @fact_mul1(float %x, float %y, float %z) {
   %t2 = fmul fast float %y, %z
   %t3 = fadd fast float %t1, %t2
   ret float %t3
-; CHECK: @fact_mul1
+; CHECK-LABEL: @fact_mul1(
 ; CHECK: fmul fast float %1, %z
 }
 
@@ -382,7 +382,7 @@ define float @fact_mul2(float %x, float %y, float %z) {
   %t2 = fmul fast float %y, %z
   %t3 = fsub fast float %t1, %t2
   ret float %t3
-; CHECK: @fact_mul2
+; CHECK-LABEL: @fact_mul2(
 ; CHECK: fmul fast float %1, %z
 }
 
@@ -392,7 +392,7 @@ define float @fact_mul3(float %x, float %y, float %z) {
   %t1 = fmul fast float %z, %x
   %t3 = fsub fast float %t1, %t2
   ret float %t3
-; CHECK: @fact_mul3
+; CHECK-LABEL: @fact_mul3(
 ; CHECK: fmul fast float %1, %z
 }
 
@@ -402,7 +402,7 @@ define float @fact_mul4(float %x, float %y, float %z) {
   %t2 = fmul fast float %z, %y
   %t3 = fsub fast float %t1, %t2
   ret float %t3
-; CHECK: @fact_mul4
+; CHECK-LABEL: @fact_mul4(
 ; CHECK: fmul fast float %1, %z
 }
 
diff --git a/test/Transforms/InstCombine/fcmp.ll b/test/Transforms/InstCombine/fcmp.ll
index 376fa07..afc6782 100644
--- a/test/Transforms/InstCombine/fcmp.ll
+++ b/test/Transforms/InstCombine/fcmp.ll
@@ -5,7 +5,7 @@ define i1 @test1(float %x, float %y) nounwind {
   %ext2 = fpext float %y to double
   %cmp = fcmp ogt double %ext1, %ext2
   ret i1 %cmp
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: fcmp ogt float %x, %y
 }
 
@@ -13,7 +13,7 @@ define i1 @test2(float %a) nounwind {
   %ext = fpext float %a to double
   %cmp = fcmp ogt double %ext, 1.000000e+00
   ret i1 %cmp
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: fcmp ogt float %a, 1.0
 }
 
@@ -21,7 +21,7 @@ define i1 @test3(float %a) nounwind {
   %ext = fpext float %a to double
   %cmp = fcmp ogt double %ext, 0x3FF0000000000001 ; more precision than float.
   ret i1 %cmp
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: fpext float %a to double
 }
 
@@ -29,7 +29,7 @@ define i1 @test4(float %a) nounwind {
   %ext = fpext float %a to double
   %cmp = fcmp ogt double %ext, 0x36A0000000000000 ; denormal in float.
   ret i1 %cmp
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: fpext float %a to double
 }
 
@@ -37,7 +37,7 @@ define i1 @test5(float %a) nounwind {
   %neg = fsub float -0.000000e+00, %a
   %cmp = fcmp ogt float %neg, 1.000000e+00
   ret i1 %cmp
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NEXT: fcmp olt float %a, -1.0
 }
 
@@ -46,7 +46,7 @@ define i1 @test6(float %x, float %y) nounwind {
   %neg2 = fsub float -0.000000e+00, %y
   %cmp = fcmp olt float %neg1, %neg2
   ret i1 %cmp
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: fcmp ogt float %x, %y
 }
 
@@ -54,7 +54,7 @@ define i1 @test7(float %x) nounwind readnone ssp noredzone {
   %ext = fpext float %x to ppc_fp128
   %cmp = fcmp ogt ppc_fp128 %ext, 0xM00000000000000000000000000000000
   ret i1 %cmp
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NEXT: fcmp ogt float %x, 0.000000e+00
 }
 
@@ -65,7 +65,7 @@ define float @test8(float %x) nounwind readnone optsize ssp {
   %conv2 = sitofp i32 %conv1 to float
   ret float %conv2
 ; Float comparison to zero shouldn't cast to double.
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK-NEXT: fcmp olt float %x, 0.000000e+00
 }
 
@@ -76,7 +76,7 @@ define i32 @test9(double %a) nounwind {
   %cmp = fcmp olt double %call, 0.000000e+00
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NOT: fabs
 ; CHECK: ret i32 0
 }
@@ -86,7 +86,7 @@ define i32 @test10(double %a) nounwind {
   %cmp = fcmp ole double %call, 0.000000e+00
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK-NOT: fabs
 ; CHECK: fcmp oeq double %a, 0.000000e+00
 }
@@ -96,7 +96,7 @@ define i32 @test11(double %a) nounwind {
   %cmp = fcmp ogt double %call, 0.000000e+00
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK-NOT: fabs
 ; CHECK: fcmp one double %a, 0.000000e+00
 }
@@ -106,7 +106,7 @@ define i32 @test12(double %a) nounwind {
   %cmp = fcmp oge double %call, 0.000000e+00
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK-NOT: fabs
 ; CHECK: fcmp ord double %a, 0.000000e+00
 }
@@ -116,7 +116,7 @@ define i32 @test13(double %a) nounwind {
   %cmp = fcmp une double %call, 0.000000e+00
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK-NOT: fabs
 ; CHECK: fcmp une double %a, 0.000000e+00
 }
@@ -126,7 +126,7 @@ define i32 @test14(double %a) nounwind {
   %cmp = fcmp oeq double %call, 0.000000e+00
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK-NOT: fabs
 ; CHECK: fcmp oeq double %a, 0.000000e+00
 }
@@ -136,7 +136,7 @@ define i32 @test15(double %a) nounwind {
   %cmp = fcmp one double %call, 0.000000e+00
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 ; CHECK-NOT: fabs
 ; CHECK: fcmp one double %a, 0.000000e+00
 }
@@ -146,7 +146,7 @@ define i32 @test16(double %a) nounwind {
   %cmp = fcmp ueq double %call, 0.000000e+00
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK: @test16
+; CHECK-LABEL: @test16(
 ; CHECK-NOT: fabs
 ; CHECK: fcmp ueq double %a, 0.000000e+00
 }
diff --git a/test/Transforms/InstCombine/fdiv.ll b/test/Transforms/InstCombine/fdiv.ll
index a2cce01..1edbc5e 100644
--- a/test/Transforms/InstCombine/fdiv.ll
+++ b/test/Transforms/InstCombine/fdiv.ll
@@ -4,7 +4,7 @@ define float @test1(float %x) nounwind readnone ssp {
   %div = fdiv float %x, 0x3810000000000000
   ret float %div
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: fmul float %x, 0x47D0000000000000
 }
 
@@ -12,7 +12,7 @@ define float @test2(float %x) nounwind readnone ssp {
   %div = fdiv float %x, 0x47E0000000000000
   ret float %div
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: fdiv float %x, 0x47E0000000000000
 }
 
@@ -20,6 +20,6 @@ define float @test3(float %x) nounwind readnone ssp {
   %div = fdiv float %x, 0x36A0000000000000
   ret float %div
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: fdiv float %x, 0x36A0000000000000
 }
diff --git a/test/Transforms/InstCombine/ffs-1.ll b/test/Transforms/InstCombine/ffs-1.ll
index 0510df3..8f0b38f 100644
--- a/test/Transforms/InstCombine/ffs-1.ll
+++ b/test/Transforms/InstCombine/ffs-1.ll
@@ -12,21 +12,21 @@ declare i32 @ffsll(i64)
 ; Check ffs(0) -> 0.
 
 define i32 @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %ret = call i32 @ffs(i32 0)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 0
 }
 
 define i32 @test_simplify2() {
-; CHECK-LINUX: @test_simplify2
+; CHECK-LINUX-LABEL: @test_simplify2(
   %ret = call i32 @ffsl(i32 0)
   ret i32 %ret
 ; CHECK-LINUX-NEXT: ret i32 0
 }
 
 define i32 @test_simplify3() {
-; CHECK-LINUX: @test_simplify3
+; CHECK-LINUX-LABEL: @test_simplify3(
   %ret = call i32 @ffsll(i64 0)
   ret i32 %ret
 ; CHECK-LINUX-NEXT: ret i32 0
@@ -35,63 +35,63 @@ define i32 @test_simplify3() {
 ; Check ffs(c) -> cttz(c) + 1, where 'c' is a constant.
 
 define i32 @test_simplify4() {
-; CHECK: @test_simplify4
+; CHECK-LABEL: @test_simplify4(
   %ret = call i32 @ffs(i32 1)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 1
 }
 
 define i32 @test_simplify5() {
-; CHECK: @test_simplify5
+; CHECK-LABEL: @test_simplify5(
   %ret = call i32 @ffs(i32 2048)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 12
 }
 
 define i32 @test_simplify6() {
-; CHECK: @test_simplify6
+; CHECK-LABEL: @test_simplify6(
   %ret = call i32 @ffs(i32 65536)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 17
 }
 
 define i32 @test_simplify7() {
-; CHECK-LINUX: @test_simplify7
+; CHECK-LINUX-LABEL: @test_simplify7(
   %ret = call i32 @ffsl(i32 65536)
   ret i32 %ret
 ; CHECK-LINUX-NEXT: ret i32 17
 }
 
 define i32 @test_simplify8() {
-; CHECK-LINUX: @test_simplify8
+; CHECK-LINUX-LABEL: @test_simplify8(
   %ret = call i32 @ffsll(i64 1024)
   ret i32 %ret
 ; CHECK-LINUX-NEXT: ret i32 11
 }
 
 define i32 @test_simplify9() {
-; CHECK-LINUX: @test_simplify9
+; CHECK-LINUX-LABEL: @test_simplify9(
   %ret = call i32 @ffsll(i64 65536)
   ret i32 %ret
 ; CHECK-LINUX-NEXT: ret i32 17
 }
 
 define i32 @test_simplify10() {
-; CHECK-LINUX: @test_simplify10
+; CHECK-LINUX-LABEL: @test_simplify10(
   %ret = call i32 @ffsll(i64 17179869184)
   ret i32 %ret
 ; CHECK-LINUX-NEXT: ret i32 35
 }
 
 define i32 @test_simplify11() {
-; CHECK-LINUX: @test_simplify11
+; CHECK-LINUX-LABEL: @test_simplify11(
   %ret = call i32 @ffsll(i64 281474976710656)
   ret i32 %ret
 ; CHECK-LINUX-NEXT: ret i32 49
 }
 
 define i32 @test_simplify12() {
-; CHECK-LINUX: @test_simplify12
+; CHECK-LINUX-LABEL: @test_simplify12(
   %ret = call i32 @ffsll(i64 1152921504606846976)
   ret i32 %ret
 ; CHECK-LINUX-NEXT: ret i32 61
@@ -100,7 +100,7 @@ define i32 @test_simplify12() {
 ; Check ffs(x) -> x != 0 ? (i32)llvm.cttz(x) + 1 : 0.
 
 define i32 @test_simplify13(i32 %x) {
-; CHECK: @test_simplify13
+; CHECK-LABEL: @test_simplify13(
   %ret = call i32 @ffs(i32 %x)
 ; CHECK-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 false)
 ; CHECK-NEXT: [[INC:%[a-z0-9]+]] = add i32 [[CTTZ]], 1
@@ -111,7 +111,7 @@ define i32 @test_simplify13(i32 %x) {
 }
 
 define i32 @test_simplify14(i32 %x) {
-; CHECK-LINUX: @test_simplify14
+; CHECK-LINUX-LABEL: @test_simplify14(
   %ret = call i32 @ffsl(i32 %x)
 ; CHECK-LINUX-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 false)
 ; CHECK-LINUX-NEXT: [[INC:%[a-z0-9]+]] = add i32 [[CTTZ]], 1
@@ -122,7 +122,7 @@ define i32 @test_simplify14(i32 %x) {
 }
 
 define i32 @test_simplify15(i64 %x) {
-; CHECK-LINUX: @test_simplify15
+; CHECK-LINUX-LABEL: @test_simplify15(
   %ret = call i32 @ffsll(i64 %x)
 ; CHECK-LINUX-NEXT: [[CTTZ:%[a-z0-9]+]] = call i64 @llvm.cttz.i64(i64 %x, i1 false)
 ; CHECK-LINUX-NEXT: [[INC:%[a-z0-9]+]] = add i64 [[CTTZ]], 1
diff --git a/test/Transforms/InstCombine/float-shrink-compare.ll b/test/Transforms/InstCombine/float-shrink-compare.ll
index 0b93e84..26f77a7 100644
--- a/test/Transforms/InstCombine/float-shrink-compare.ll
+++ b/test/Transforms/InstCombine/float-shrink-compare.ll
@@ -9,7 +9,7 @@ define i32 @test1(float %x, float %y) nounwind uwtable {
   %4 = fcmp oeq double %2, %3
   %5 = zext i1 %4 to i32
   ret i32 %5
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: %ceilf = call float @ceilf(float %x)
 ; CHECK-NEXT: fcmp oeq float %ceilf, %y
 }
@@ -21,7 +21,7 @@ define i32 @test2(float %x, float %y) nounwind uwtable {
   %4 = fcmp oeq double %2, %3
   %5 = zext i1 %4 to i32
   ret i32 %5
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: %fabsf = call float @fabsf(float %x)
 ; CHECK-NEXT: fcmp oeq float %fabsf, %y
 }
@@ -33,7 +33,7 @@ define i32 @test3(float %x, float %y) nounwind uwtable {
   %4 = fcmp oeq double %2, %3
   %5 = zext i1 %4 to i32
   ret i32 %5
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: %floorf = call float @floorf(float %x)
 ; CHECK-NEXT: fcmp oeq float %floorf, %y
 }
@@ -45,7 +45,7 @@ define i32 @test4(float %x, float %y) nounwind uwtable {
   %4 = fcmp oeq double %2, %3
   %5 = zext i1 %4 to i32
   ret i32 %5
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: %nearbyintf = call float @nearbyintf(float %x)
 ; CHECK-NEXT: fcmp oeq float %nearbyintf, %y
 }
@@ -57,7 +57,7 @@ define i32 @test5(float %x, float %y) nounwind uwtable {
   %4 = fcmp oeq double %2, %3
   %5 = zext i1 %4 to i32
   ret i32 %5
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NEXT: %rintf = call float @rintf(float %x)
 ; CHECK-NEXT: fcmp oeq float %rintf, %y
 }
@@ -69,7 +69,7 @@ define i32 @test6(float %x, float %y) nounwind uwtable {
   %4 = fcmp oeq double %2, %3
   %5 = zext i1 %4 to i32
   ret i32 %5
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: %roundf = call float @roundf(float %x)
 ; CHECK-NEXT: fcmp oeq float %roundf, %y
 }
@@ -81,7 +81,7 @@ define i32 @test7(float %x, float %y) nounwind uwtable {
   %4 = fcmp oeq double %2, %3
   %5 = zext i1 %4 to i32
   ret i32 %5
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NEXT: %truncf = call float @truncf(float %x)
 ; CHECK-NEXT: fcmp oeq float %truncf, %y
 }
@@ -93,7 +93,7 @@ define i32 @test8(float %x, float %y) nounwind uwtable {
   %4 = fcmp oeq double %1, %3
   %5 = zext i1 %4 to i32
   ret i32 %5
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK-NEXT: %ceilf = call float @ceilf(float %x)
 ; CHECK-NEXT: fcmp oeq float %ceilf, %y
 }
@@ -105,7 +105,7 @@ define i32 @test9(float %x, float %y) nounwind uwtable {
   %4 = fcmp oeq double %1, %3
   %5 = zext i1 %4 to i32
   ret i32 %5
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NEXT: %fabsf = call float @fabsf(float %x)
 ; CHECK-NEXT: fcmp oeq float %fabsf, %y
 }
@@ -117,7 +117,7 @@ define i32 @test10(float %x, float %y) nounwind uwtable {
   %4 = fcmp oeq double %1, %3
   %5 = zext i1 %4 to i32
   ret i32 %5
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK-NEXT: %floorf = call float @floorf(float %x)
 ; CHECK-NEXT: fcmp oeq float %floorf, %y
 }
@@ -129,7 +129,7 @@ define i32 @test11(float %x, float %y) nounwind uwtable {
   %4 = fcmp oeq double %1, %3
   %5 = zext i1 %4 to i32
   ret i32 %5
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK-NEXT: %nearbyintf = call float @nearbyintf(float %x)
 ; CHECK-NEXT: fcmp oeq float %nearbyintf, %y
 }
@@ -141,7 +141,7 @@ define i32 @test12(float %x, float %y) nounwind uwtable {
   %4 = fcmp oeq double %1, %3
   %5 = zext i1 %4 to i32
   ret i32 %5
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK-NEXT: %rintf = call float @rintf(float %x)
 ; CHECK-NEXT: fcmp oeq float %rintf, %y
 }
@@ -153,7 +153,7 @@ define i32 @test13(float %x, float %y) nounwind uwtable {
   %4 = fcmp oeq double %1, %3
   %5 = zext i1 %4 to i32
   ret i32 %5
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK-NEXT: %roundf = call float @roundf(float %x)
 ; CHECK-NEXT: fcmp oeq float %roundf, %y
 }
@@ -165,7 +165,7 @@ define i32 @test14(float %x, float %y) nounwind uwtable {
   %4 = fcmp oeq double %1, %3
   %5 = zext i1 %4 to i32
   ret i32 %5
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK-NEXT: %truncf = call float @truncf(float %x)
 ; CHECK-NEXT: fcmp oeq float %truncf, %y
 }
diff --git a/test/Transforms/InstCombine/fmul.ll b/test/Transforms/InstCombine/fmul.ll
index 3671b4c..cf57bed 100644
--- a/test/Transforms/InstCombine/fmul.ll
+++ b/test/Transforms/InstCombine/fmul.ll
@@ -6,7 +6,7 @@ define float @test1(float %x) {
   %mul = fmul float %sub, 2.0e+1
   ret float %mul
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: fmul float %x, -2.000000e+01
 }
 
@@ -16,7 +16,7 @@ define float @test2(float %x) {
   %mul = fmul float %sub, 2.0e+1
   ret float %mul
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: fmul float %x, -2.000000e+01
 }
 
@@ -26,7 +26,7 @@ define float @test3(float %x, float %y) {
   %sub2 = fsub float -0.000000e+00, %y
   %mul = fmul float %sub1, %sub2
   ret float %mul
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: fmul float %x, %y
 }
 
@@ -36,7 +36,7 @@ define float @test4(float %x, float %y) {
   %sub2 = fsub nsz float 0.000000e+00, %y
   %mul = fmul float %sub1, %sub2
   ret float %mul
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: fmul float %x, %y
 }
 
@@ -45,7 +45,7 @@ define float @test5(float %x, float %y) {
   %sub1 = fsub float -0.000000e+00, %x
   %mul = fmul float %sub1, %y
   ret float %mul
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: %1 = fmul float %x, %y
 ; CHECK: %mul = fsub float -0.000000e+00, %1
 }
@@ -55,7 +55,7 @@ define float @test6(float %x, float %y) {
   %sub1 = fsub nsz float 0.000000e+00, %x
   %mul = fmul float %sub1, %y
   ret float %mul
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: %1 = fmul float %x, %y
 ; CHECK: %mul = fsub float -0.000000e+00, %1
 }
@@ -67,6 +67,6 @@ define float @test7(float %x, float %y) {
   %mul = fmul float %sub1, %y
   %mul2 = fmul float %mul, %sub1
   ret float %mul2
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: fsub float -0.000000e+00, %x
 }
diff --git a/test/Transforms/InstCombine/fneg-ext.ll b/test/Transforms/InstCombine/fneg-ext.ll
new file mode 100644
index 0000000..922d26a
--- /dev/null
+++ b/test/Transforms/InstCombine/fneg-ext.ll
@@ -0,0 +1,23 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+; CHECK: test1
+define double @test1(float %a, double %b) nounwind readnone ssp uwtable {
+; CHECK-NOT: fsub
+; CHECK: fpext
+; CHECK: fadd
+  %1 = fsub float -0.000000e+00, %a
+  %2 = fpext float %1 to double
+  %3 = fsub double %b, %2
+  ret double %3
+}
+
+; CHECK: test2
+define double @test2(float %a, double %b) nounwind readnone ssp uwtable {
+; CHECK-NOT: fsub
+; CHECK: fpext
+; CHECK: fadd fast
+  %1 = fsub float -0.000000e+00, %a
+  %2 = fpext float %1 to double
+  %3 = fsub fast double %b, %2
+  ret double %3
+}
diff --git a/test/Transforms/InstCombine/fold-bin-operand.ll b/test/Transforms/InstCombine/fold-bin-operand.ll
index a8bad0d..d330326 100644
--- a/test/Transforms/InstCombine/fold-bin-operand.ll
+++ b/test/Transforms/InstCombine/fold-bin-operand.ll
@@ -2,14 +2,14 @@
 target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128"
 
 define i1 @f(i1 %x) {
-; CHECK: @f
+; CHECK-LABEL: @f(
 ; CHECK: ret i1 false
 	%b = and i1 %x, icmp eq (i8* inttoptr (i32 1 to i8*), i8* inttoptr (i32 2 to i8*))
 	ret i1 %b
 }
 
 define i32 @g(i32 %x) {
-; CHECK: @g
+; CHECK-LABEL: @g(
 ; CHECK: ret i32 %x
 	%b = add i32 %x, zext (i1 icmp eq (i8* inttoptr (i32 1000000 to i8*), i8* inttoptr (i32 2000000 to i8*)) to i32)
 	ret i32 %b
diff --git a/test/Transforms/InstCombine/fold-calls.ll b/test/Transforms/InstCombine/fold-calls.ll
index 504f874..1a9a9fd 100644
--- a/test/Transforms/InstCombine/fold-calls.ll
+++ b/test/Transforms/InstCombine/fold-calls.ll
@@ -1,7 +1,7 @@
 ; RUN: opt -instcombine -S < %s | FileCheck %s
 
 ; This shouldn't fold, because sin(inf) is invalid.
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK:   %t = call double @sin(double 0x7FF0000000000000)
 define double @foo() {
   %t = call double @sin(double 0x7FF0000000000000)
@@ -9,7 +9,7 @@ define double @foo() {
 }
 
 ; This should fold.
-; CHECK: @bar
+; CHECK-LABEL: @bar(
 ; CHECK:   ret double 0.0
 define double @bar() {
   %t = call double @sin(double 0.0)
diff --git a/test/Transforms/InstCombine/fold-fops-into-selects.ll b/test/Transforms/InstCombine/fold-fops-into-selects.ll
new file mode 100644
index 0000000..07aebb1
--- /dev/null
+++ b/test/Transforms/InstCombine/fold-fops-into-selects.ll
@@ -0,0 +1,71 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define float @test1(i1 %A) {
+EntryBlock:
+  %cf = select i1 %A, float 1.000000e+00, float 0.000000e+00
+  %op = fsub float 1.000000e+00, %cf
+  ret float %op
+; CHECK-LABEL: @test1(
+; CHECK: select i1 %A, float 0.000000e+00, float 1.000000e+00
+}
+
+define float @test2(i1 %A, float %B) {
+EntryBlock:
+  %cf = select i1 %A, float 1.000000e+00, float %B
+  %op = fadd float 2.000000e+00, %cf
+  ret float %op
+; CHECK-LABEL: @test2(
+; CHECK: [[OP:%.*]] = fadd float %B, 2.000000e+00
+; CHECK: select i1 %A, float 3.000000e+00, float [[OP]]
+}
+
+define float @test3(i1 %A, float %B) {
+EntryBlock:
+  %cf = select i1 %A, float 1.000000e+00, float %B
+  %op = fsub float 2.000000e+00, %cf
+  ret float %op
+; CHECK-LABEL: @test3(
+; CHECK: [[OP:%.*]] = fsub float 2.000000e+00, %B
+; CHECK: select i1 %A, float 1.000000e+00, float [[OP]]
+}
+
+define float @test4(i1 %A, float %B) {
+EntryBlock:
+  %cf = select i1 %A, float 1.000000e+00, float %B
+  %op = fmul float 2.000000e+00, %cf
+  ret float %op
+; CHECK-LABEL: @test4(
+; CHECK: [[OP:%.*]] = fmul float %B, 2.000000e+00
+; CHECK: select i1 %A, float 2.000000e+00, float [[OP]]
+}
+
+define float @test5(i1 %A, float %B) {
+EntryBlock:
+  %cf = select i1 %A, float 1.000000e+00, float %B
+  %op = fdiv float 2.000000e+00, %cf
+  ret float %op
+; CHECK-LABEL: @test5(
+; CHECK: [[OP:%.*]] = fdiv float 2.000000e+00, %B
+; CHECK: select i1 %A, float 2.000000e+00, float [[OP]]
+}
+
+define float @test6(i1 %A, float %B) {
+EntryBlock:
+  %cf = select i1 %A, float 1.000000e+00, float %B
+  %op = fdiv float %cf, 2.000000e+00
+  ret float %op
+; CHECK-LABEL: @test6(
+; CHECK: [[OP:%.*]] = fmul float %B, 5.000000e-01
+; CHECK: select i1 %A, float 5.000000e-01, float [[OP]]
+}
+
+define float @test7(i1 %A, float %B) {
+EntryBlock:
+  %cf = select i1 %A, float 1.000000e+00, float %B
+  %op = fdiv float %cf, 3.000000e+00
+  ret float %op
+; CHECK-LABEL: @test7(
+; CHECK: [[OP:%.*]] = fdiv float %B, 3.000000e+00
+; CHECK: select i1 %A, float 0x3FD5555560000000, float [[OP]]
+}
+
diff --git a/test/Transforms/InstCombine/fprintf-1.ll b/test/Transforms/InstCombine/fprintf-1.ll
index e1dc191..1b7c104 100644
--- a/test/Transforms/InstCombine/fprintf-1.ll
+++ b/test/Transforms/InstCombine/fprintf-1.ll
@@ -18,7 +18,7 @@ declare i32 @fprintf(%FILE*, i8*, ...)
 ; Check fprintf(fp, "foo") -> fwrite("foo", 3, 1, fp).
 
 define void @test_simplify1(%FILE* %fp) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %fmt = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
   call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt)
 ; CHECK-NEXT: call i32 @fwrite(i8* getelementptr inbounds ([13 x i8]* @hello_world, i32 0, i32 0), i32 12, i32 1, %FILE* %fp)
@@ -29,7 +29,7 @@ define void @test_simplify1(%FILE* %fp) {
 ; Check fprintf(fp, "%c", chr) -> fputc(chr, fp).
 
 define void @test_simplify2(%FILE* %fp) {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %fmt = getelementptr [3 x i8]* @percent_c, i32 0, i32 0
   call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt, i8 104)
 ; CHECK-NEXT: call i32 @fputc(i32 104, %FILE* %fp)
@@ -41,7 +41,7 @@ define void @test_simplify2(%FILE* %fp) {
 ; NOTE: The fputs simplifier simplifies this further to fwrite.
 
 define void @test_simplify3(%FILE* %fp) {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %fmt = getelementptr [3 x i8]* @percent_s, i32 0, i32 0
   %str = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
   call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt, i8* %str)
@@ -53,7 +53,7 @@ define void @test_simplify3(%FILE* %fp) {
 ; Check fprintf(fp, fmt, ...) -> fiprintf(fp, fmt, ...) if no floating point.
 
 define void @test_simplify4(%FILE* %fp) {
-; CHECK-IPRINTF: @test_simplify4
+; CHECK-IPRINTF-LABEL: @test_simplify4(
   %fmt = getelementptr [3 x i8]* @percent_d, i32 0, i32 0
   call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt, i32 187)
 ; CHECK-NEXT-IPRINTF: call i32 (%FILE*, i8*, ...)* @fiprintf(%FILE* %fp, i8* getelementptr inbounds ([3 x i8]* @percent_d, i32 0, i32 0), i32 187)
@@ -62,7 +62,7 @@ define void @test_simplify4(%FILE* %fp) {
 }
 
 define void @test_no_simplify1(%FILE* %fp) {
-; CHECK-IPRINTF: @test_no_simplify1
+; CHECK-IPRINTF-LABEL: @test_no_simplify1(
   %fmt = getelementptr [3 x i8]* @percent_f, i32 0, i32 0
   call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt, double 1.87)
 ; CHECK-NEXT-IPRINTF: call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* getelementptr inbounds ([3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00)
@@ -71,7 +71,7 @@ define void @test_no_simplify1(%FILE* %fp) {
 }
 
 define void @test_no_simplify2(%FILE* %fp, double %d) {
-; CHECK: @test_no_simplify2
+; CHECK-LABEL: @test_no_simplify2(
   %fmt = getelementptr [3 x i8]* @percent_f, i32 0, i32 0
   call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt, double %d)
 ; CHECK-NEXT: call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* getelementptr inbounds ([3 x i8]* @percent_f, i32 0, i32 0), double %d)
@@ -80,7 +80,7 @@ define void @test_no_simplify2(%FILE* %fp, double %d) {
 }
 
 define i32 @test_no_simplify3(%FILE* %fp) {
-; CHECK: @test_no_simplify3
+; CHECK-LABEL: @test_no_simplify3(
   %fmt = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
   %1 = call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt)
 ; CHECK-NEXT: call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* getelementptr inbounds ([13 x i8]* @hello_world, i32 0, i32 0))
diff --git a/test/Transforms/InstCombine/fputs-1.ll b/test/Transforms/InstCombine/fputs-1.ll
index c7c5bec..473610e 100644
--- a/test/Transforms/InstCombine/fputs-1.ll
+++ b/test/Transforms/InstCombine/fputs-1.ll
@@ -15,7 +15,7 @@ declare i32 @fputs(i8*, %FILE*)
 ; Check fputs(str, fp) --> fwrite(str, 1, strlen(s), fp).
 
 define void @test_simplify1(%FILE* %fp) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %str = getelementptr [1 x i8]* @empty, i32 0, i32 0
   call i32 @fputs(i8* %str, %FILE* %fp)
   ret void
@@ -25,7 +25,7 @@ define void @test_simplify1(%FILE* %fp) {
 ; NOTE: The fwrite simplifier simplifies this further to fputc.
 
 define void @test_simplify2(%FILE* %fp) {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %str = getelementptr [2 x i8]* @A, i32 0, i32 0
   call i32 @fputs(i8* %str, %FILE* %fp)
 ; CHECK-NEXT: call i32 @fputc(i32 65, %FILE* %fp)
@@ -34,7 +34,7 @@ define void @test_simplify2(%FILE* %fp) {
 }
 
 define void @test_simplify3(%FILE* %fp) {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %str = getelementptr [7 x i8]* @hello, i32 0, i32 0
   call i32 @fputs(i8* %str, %FILE* %fp)
 ; CHECK-NEXT: call i32 @fwrite(i8* getelementptr inbounds ([7 x i8]* @hello, i32 0, i32 0), i32 6, i32 1, %FILE* %fp)
diff --git a/test/Transforms/InstCombine/fwrite-1.ll b/test/Transforms/InstCombine/fwrite-1.ll
index 528cdec..6f9a8e4 100644
--- a/test/Transforms/InstCombine/fwrite-1.ll
+++ b/test/Transforms/InstCombine/fwrite-1.ll
@@ -14,7 +14,7 @@ declare i64 @fwrite(i8*, i64, i64, %FILE *)
 ; Check fwrite(S, 1, 1, fp) -> fputc(S[0], fp).
 
 define void @test_simplify1(%FILE* %fp) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %str = getelementptr inbounds [1 x i8]* @str, i64 0, i64 0
   call i64 @fwrite(i8* %str, i64 1, i64 1, %FILE* %fp)
 ; CHECK-NEXT: call i32 @fputc(i32 0, %FILE* %fp)
@@ -23,7 +23,7 @@ define void @test_simplify1(%FILE* %fp) {
 }
 
 define void @test_simplify2(%FILE* %fp) {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %str = getelementptr inbounds [0 x i8]* @empty, i64 0, i64 0
   call i64 @fwrite(i8* %str, i64 1, i64 0, %FILE* %fp)
   ret void
@@ -31,7 +31,7 @@ define void @test_simplify2(%FILE* %fp) {
 }
 
 define void @test_simplify3(%FILE* %fp) {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %str = getelementptr inbounds [0 x i8]* @empty, i64 0, i64 0
   call i64 @fwrite(i8* %str, i64 0, i64 1, %FILE* %fp)
   ret void
@@ -39,7 +39,7 @@ define void @test_simplify3(%FILE* %fp) {
 }
 
 define i64 @test_no_simplify1(%FILE* %fp) {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %str = getelementptr inbounds [1 x i8]* @str, i64 0, i64 0
   %ret = call i64 @fwrite(i8* %str, i64 1, i64 1, %FILE* %fp)
 ; CHECK-NEXT: call i64 @fwrite
@@ -48,7 +48,7 @@ define i64 @test_no_simplify1(%FILE* %fp) {
 }
 
 define void @test_no_simplify2(%FILE* %fp, i64 %size) {
-; CHECK: @test_no_simplify2
+; CHECK-LABEL: @test_no_simplify2(
   %str = getelementptr inbounds [1 x i8]* @str, i64 0, i64 0
   call i64 @fwrite(i8* %str, i64 %size, i64 1, %FILE* %fp)
 ; CHECK-NEXT: call i64 @fwrite
diff --git a/test/Transforms/InstCombine/getelementptr.ll b/test/Transforms/InstCombine/getelementptr.ll
index bb07736..90f144a 100644
--- a/test/Transforms/InstCombine/getelementptr.ll
+++ b/test/Transforms/InstCombine/getelementptr.ll
@@ -13,7 +13,7 @@ target datalayout = "e-p:64:64"
 define i32* @test1(i32* %I) {
         %A = getelementptr i32* %I, i64 0 
         ret i32* %A
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret i32* %I
 }
 
@@ -21,7 +21,7 @@ define i32* @test1(i32* %I) {
 define i32* @test2(i32* %I) {
         %A = getelementptr i32* %I
         ret i32* %A
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: ret i32* %I
 }
 
@@ -30,7 +30,7 @@ define i32* @test3(i32* %I) {
         %A = getelementptr i32* %I, i64 17
         %B = getelementptr i32* %A, i64 4
         ret i32* %B
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: getelementptr i32* %I, i64 21
 }
 
@@ -39,7 +39,7 @@ define i32* @test4({ i32 }* %I) {
         %A = getelementptr { i32 }* %I, i64 1 
         %B = getelementptr { i32 }* %A, i64 0, i32 0
         ret i32* %B
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: getelementptr { i32 }* %I, i64 1, i32 0
 }
 
@@ -48,7 +48,7 @@ define void @test5(i8 %B) {
         %A = getelementptr [10 x i8]* @Global, i64 0, i64 4 
         store i8 %B, i8* %A
         ret void
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: store i8 %B, i8* getelementptr inbounds ([10 x i8]* @Global, i64 0, i64 4)
 }
 
@@ -57,7 +57,7 @@ define i32* @test7(i32* %I, i64 %C, i64 %D) {
         %A = getelementptr i32* %I, i64 %C 
         %B = getelementptr i32* %A, i64 %D 
         ret i32* %B
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: %A.sum = add i64 %C, %D
 ; CHECK: getelementptr i32* %I, i64 %A.sum
 }
@@ -67,7 +67,7 @@ define i8* @test8([10 x i32]* %X) {
         %A = getelementptr [10 x i32]* %X, i64 0, i64 0 
         %B = bitcast i32* %A to i8*     
         ret i8* %B
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: bitcast [10 x i32]* %X to i8*
 }
 
@@ -75,7 +75,7 @@ define i32 @test9() {
         %A = getelementptr { i32, double }* null, i32 0, i32 1
         %B = ptrtoint double* %A to i32        
         ret i32 %B
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK: ret i32 8
 }
 
@@ -85,7 +85,7 @@ define i1 @test10({ i32, i32 }* %x, { i32, i32 }* %y) {
         ;; seteq x, y
         %tmp.4 = icmp eq i32* %tmp.1, %tmp.3       
         ret i1 %tmp.4
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK: icmp eq { i32, i32 }* %x, %y
 }
 
@@ -93,7 +93,7 @@ define i1 @test11({ i32, i32 }* %X) {
         %P = getelementptr { i32, i32 }* %X, i32 0, i32 0 
         %Q = icmp eq i32* %P, null             
         ret i1 %Q
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK: icmp eq { i32, i32 }* %X, null
 }
 
@@ -111,7 +111,7 @@ entry:
   %g5 = getelementptr %struct.A* %new_a, i32 0, i32 1	
   %a_a = load i32* %g5, align 4	
   ret i32 %a_a
-; CHECK:      @test12
+; CHECK-LABEL:      @test12(
 ; CHECK:      getelementptr %struct.A* %a, i64 0, i32 1
 ; CHECK-NEXT: store i32 10, i32* %g3
 ; CHECK-NEXT: ret i32 10
@@ -125,7 +125,7 @@ define i1 @test13(i64 %X, %S* %P) {
         %B = getelementptr inbounds %S* %P, i32 0, i32 0
 	%C = icmp eq i32* %A, %B
 	ret i1 %C
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK:    %C = icmp eq i64 %X, -1
 }
 
@@ -135,7 +135,7 @@ define i8* @test14(i32 %Idx) {
         %idx = zext i32 %Idx to i64
         %tmp = getelementptr i8* getelementptr ([3 x i8]* @G, i32 0, i32 0), i64 %idx
         ret i8* %tmp
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK: getelementptr [3 x i8]* @G, i64 0, i64 %idx
 }
 
@@ -145,7 +145,7 @@ define i8* @test14(i32 %Idx) {
 define i32 *@test15(i64 %X) {
         %A = getelementptr i32* getelementptr ([40 x i32]* @Array, i64 0, i64 0), i64 %X
         ret i32* %A
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 ; CHECK: getelementptr [40 x i32]* @Array, i64 0, i64 %X
 }
 
@@ -153,7 +153,7 @@ define i32 *@test15(i64 %X) {
 define i32* @test16(i32* %X, i32 %Idx) {
         %R = getelementptr i32* %X, i32 %Idx       
         ret i32* %R
-; CHECK: @test16
+; CHECK-LABEL: @test16(
 ; CHECK: sext i32 %Idx to i64
 }
 
@@ -163,7 +163,7 @@ define i1 @test17(i16* %P, i32 %I, i32 %J) {
         %Y = getelementptr inbounds i16* %P, i32 %J
         %C = icmp ult i16* %X, %Y
         ret i1 %C
-; CHECK: @test17
+; CHECK-LABEL: @test17(
 ; CHECK: %C = icmp slt i32 %I, %J 
 }
 
@@ -171,7 +171,7 @@ define i1 @test18(i16* %P, i32 %I) {
         %X = getelementptr inbounds i16* %P, i32 %I
         %C = icmp ult i16* %X, %P
         ret i1 %C
-; CHECK: @test18
+; CHECK-LABEL: @test18(
 ; CHECK: %C = icmp slt i32 %I, 0
 }
 
@@ -181,7 +181,7 @@ define i32 @test19(i32* %P, i32 %A, i32 %B) {
         %tmp.10 = icmp eq i32* %tmp.4, %tmp.9
         %tmp.11 = zext i1 %tmp.10 to i32
         ret i32 %tmp.11
-; CHECK: @test19
+; CHECK-LABEL: @test19(
 ; CHECK: icmp eq i32 %A, %B
 }
 
@@ -190,7 +190,7 @@ define i32 @test20(i32* %P, i32 %A, i32 %B) {
         %tmp.6 = icmp eq i32* %tmp.4, %P
         %tmp.7 = zext i1 %tmp.6 to i32
         ret i32 %tmp.7
-; CHECK: @test20
+; CHECK-LABEL: @test20(
 ; CHECK: icmp eq i32 %A, 0
 }
 
@@ -201,7 +201,7 @@ define i32 @test21() {
         %pbobel = getelementptr %intstruct* %pbob2, i64 0, i32 0
         %rval = load i32* %pbobel
         ret i32 %rval
-; CHECK: @test21
+; CHECK-LABEL: @test21(
 ; CHECK: getelementptr %intstruct* %pbob1, i64 0, i32 0
 }
 
@@ -213,7 +213,7 @@ define i1 @test22() {
         %C = icmp ult i32* getelementptr (i32* @A, i64 1), 
                            getelementptr (i32* @B, i64 2) 
         ret i1 %C
-; CHECK: @test22
+; CHECK-LABEL: @test22(
 ; CHECK: icmp ult (i32* getelementptr inbounds (i32* @A, i64 1), i32* getelementptr (i32* @B, i64 2))
 }
 
@@ -224,7 +224,7 @@ define i1 @test23() {
         %A = getelementptr %X* null, i64 0, i32 0, i64 0                ; <i32*> [#uses=1]
         %B = icmp ne i32* %A, null              ; <i1> [#uses=1]
         ret i1 %B
-; CHECK: @test23
+; CHECK-LABEL: @test23(
 ; CHECK: ret i1 false
 }
 
@@ -239,7 +239,7 @@ entry:
         %tmp27.i = sext i32 %sext to i64                ; <i64> [#uses=1]
         tail call void @foo25( i32 0, i64 %tmp27.i )
         unreachable
-; CHECK: @test25
+; CHECK-LABEL: @test25(
 }
 
 declare void @foo25(i32, i64)
@@ -251,7 +251,7 @@ define i1 @test26(i8* %arr) {
         %Y = getelementptr i8* %arr, i32 1
         %test = icmp uge i8* %X, %Y
         ret i1 %test
-; CHECK: @test26
+; CHECK-LABEL: @test26(
 ; CHECK: ret i1 true
 }
 
@@ -275,7 +275,7 @@ entry:
         "=r,ir,*m,i,0,~{dirflag},~{fpsr},~{flags}"( i32 %tmp351,
          %struct.__large_struct* null, i32 -14, i32 0 )
 	unreachable
-; CHECK: @test27
+; CHECK-LABEL: @test27(
 }
 
 ; PR1978
@@ -303,7 +303,7 @@ bb10:
 
 bb17:	
 	ret i32 0
-; CHECK: @test28
+; CHECK-LABEL: @test28(
 ; CHECK: icmp eq i32 %indvar, 0
 }
 
@@ -332,7 +332,7 @@ if.then216:
 
 if.end363:
 	ret i32 0
-; CHECK: @test29
+; CHECK-LABEL: @test29(
 }
 
 
@@ -345,7 +345,7 @@ entry:
 	%2 = getelementptr [0 x i32]* %1, i32 0, i32 %m
 	%3 = load i32* %2, align 4
 	ret i32 %3
-; CHECK: @test30
+; CHECK-LABEL: @test30(
 ; CHECK: getelementptr i32
 }
 
@@ -358,7 +358,7 @@ define i1 @test31(i32* %A) {
         %C = getelementptr i32* %A, i64 1
         %V = icmp eq i32* %B, %C 
         ret i1 %V
-; CHECK: @test31
+; CHECK-LABEL: @test31(
 ; CHECK: ret i1 true
 }
 
@@ -375,7 +375,7 @@ define i8* @test32(i8* %v) {
 	%F = getelementptr [4 x i8*]* %A, i32 0, i32 2	
 	%G = load i8** %F
 	ret i8* %G
-; CHECK: @test32
+; CHECK-LABEL: @test32(
 ; CHECK: %D = getelementptr [4 x i8*]* %A, i64 0, i64 1
 ; CHECK: %F = getelementptr [4 x i8*]* %A, i64 0, i64 2
 }
@@ -388,7 +388,7 @@ define i32 *@test33(%struct.Key *%A) {
 	%B = bitcast %struct.Key* %A to %struct.anon*
         %C = getelementptr %struct.anon* %B, i32 0, i32 2 
 	ret i32 *%C
-; CHECK: @test33
+; CHECK-LABEL: @test33(
 ; CHECK: getelementptr %struct.Key* %A, i64 0, i32 0, i32 1
 }
 
@@ -404,7 +404,7 @@ entry:
       	store i64 %V, i64* %mrv_gep
 	%C = load i8** %B, align 8
 	ret i8* %C
-; CHECK: @test34
+; CHECK-LABEL: @test34(
 ; CHECK: %V.c = inttoptr i64 %V to i8*
 ; CHECK: ret i8* %V.c
 }
@@ -423,7 +423,7 @@ define i32 @test35() nounwind {
   call i32 (i8*, ...)* @printf(i8* getelementptr ([17 x i8]* @"\01LC8", i32 0, i32 0),
              i8* getelementptr (%t1* bitcast (%t0* @s to %t1*), i32 0, i32 1, i32 0)) nounwind
   ret i32 0
-; CHECK: @test35
+; CHECK-LABEL: @test35(
 ; CHECK: call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @"\01LC8", i64 0, i64 0), i8* getelementptr inbounds (%t0* @s, i64 0, i32 1, i64 0)) [[NUW:#[0-9]+]]
 }
 
@@ -434,14 +434,14 @@ define i32 @test35() nounwind {
 
 define i8* @test36() nounwind {
   ret i8* getelementptr ([11 x i8]* @array, i32 0, i64 -1)
-; CHECK: @test36
+; CHECK-LABEL: @test36(
 ; CHECK: ret i8* getelementptr ([11 x i8]* @array, i64 1676976733973595601, i64 4)
 }
 
 ; Instcombine shouldn't assume that gep(A,0,1) != gep(A,1,0).
 @A37 = external constant [1 x i8]
 define i1 @test37() nounwind {
-; CHECK: @test37
+; CHECK-LABEL: @test37(
 ; CHECK: ret i1 true
   %t = icmp eq i8* getelementptr ([1 x i8]* @A37, i64 0, i64 1),
                    getelementptr ([1 x i8]* @A37, i64 1, i64 0)
@@ -452,7 +452,7 @@ define i1 @test37() nounwind {
 define i32* @test38(i32* %I, i32 %n) {
         %A = getelementptr i32* %I, i32 %n
         ret i32* %A
-; CHECK: @test38
+; CHECK-LABEL: @test38(
 ; CHECK: = sext i32 %n to i64
 ; CHECK: %A = getelementptr i32* %I, i64 %
 }
@@ -469,7 +469,7 @@ entry:
   call void @pr10322_f3(i8** %tmp2) nounwind
   ret void
 
-; CHECK: @pr10322_f1
+; CHECK-LABEL: @pr10322_f1(
 ; CHECK: %tmp2 = getelementptr inbounds %pr10322_t* %arrayidx8, i64 0, i32 0
 }
 
@@ -485,7 +485,7 @@ define void @three_gep_f(%three_gep_t2* %x) {
   %gep3 = getelementptr %three_gep_t* %gep2, i64 0, i32 0
   call void @three_gep_g(i32* %gep3)
 
-; CHECK: @three_gep_f
+; CHECK-LABEL: @three_gep_f(
 ; CHECK: %gep3 = getelementptr %three_gep_t2* %gep1, i64 0, i32 0, i32 0
   ret void
 }
@@ -504,9 +504,19 @@ define void @test39(%struct.ham* %arg, i8 %arg1) nounwind {
   store i8 %arg1, i8* %tmp4, align 8
   ret void
 
-; CHECK: @test39
+; CHECK-LABEL: @test39(
 ; CHECK: getelementptr inbounds %struct.ham* %arg, i64 0, i32 2
 ; CHECK: getelementptr inbounds i8* %tmp3, i64 -8
 }
 
+define i1 @pr16483([1 x i8]* %a, [1 x i8]* %b) {
+  %c = getelementptr [1 x i8]* %a, i32 0, i32 0
+  %d = getelementptr [1 x i8]* %b, i32 0, i32 0
+  %cmp = icmp ult i8* %c, %d
+  ret i1 %cmp
+
+; CHECK-LABEL: @pr16483(
+; CHECK-NEXT: icmp ult  [1 x i8]* %a, %b
+}
+
 ; CHECK: attributes [[NUW]] = { nounwind }
diff --git a/test/Transforms/InstCombine/icmp.ll b/test/Transforms/InstCombine/icmp.ll
index 5248a89..dfeac67 100644
--- a/test/Transforms/InstCombine/icmp.ll
+++ b/test/Transforms/InstCombine/icmp.ll
@@ -8,7 +8,7 @@ entry:
         icmp slt i32 %X, 0              ; <i1>:0 [#uses=1]
         zext i1 %0 to i32               ; <i32>:1 [#uses=1]
         ret i32 %1
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: lshr i32 %X, 31
 ; CHECK-NEXT: ret i32
 }
@@ -18,7 +18,7 @@ entry:
         icmp ult i32 %X, -2147483648            ; <i1>:0 [#uses=1]
         zext i1 %0 to i32               ; <i32>:1 [#uses=1]
         ret i32 %1
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: lshr i32 %X, 31
 ; CHECK-NEXT: xor i32
 ; CHECK-NEXT: ret i32
@@ -29,7 +29,7 @@ entry:
         icmp slt i32 %X, 0              ; <i1>:0 [#uses=1]
         sext i1 %0 to i32               ; <i32>:1 [#uses=1]
         ret i32 %1
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: ashr i32 %X, 31
 ; CHECK-NEXT: ret i32
 }
@@ -39,7 +39,7 @@ entry:
         icmp ult i32 %X, -2147483648            ; <i1>:0 [#uses=1]
         sext i1 %0 to i32               ; <i32>:1 [#uses=1]
         ret i32 %1
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: ashr i32 %X, 31
 ; CHECK-NEXT: xor i32
 ; CHECK-NEXT: ret i32
@@ -50,7 +50,7 @@ define <2 x i1> @test5(<2 x i64> %x) {
 entry:
   %V = icmp eq <2 x i64> %x, undef
   ret <2 x i1> %V
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: ret <2 x i1> <i1 true, i1 true>
 }
 
@@ -60,7 +60,7 @@ define i32 @test6(i32 %a, i32 %b) {
         %e = sub i32 0, %d
         %f = and i32 %e, %b
         ret i32 %f
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: ashr i32 %a, 31
 ; CHECK-NEXT: %f = and i32 %e, %b
 ; CHECK-NEXT: ret i32 %f
@@ -72,7 +72,7 @@ entry:
   %a = add i32 %x, -1
   %b = icmp ult i32 %a, %x
   ret i1 %b
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: %b = icmp ne i32 %x, 0
 ; CHECK: ret i1 %b
 }
@@ -82,7 +82,7 @@ entry:
   %a = add i32 %x, -1 
   %b = icmp eq i32 %a, %x
   ret i1 %b
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: ret i1 false
 }
 
@@ -91,7 +91,7 @@ entry:
   %a = add i32 %x, -2
   %b = icmp ugt i32 %x, %a 
   ret i1 %b
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK: icmp ugt i32 %x, 1
 ; CHECK: ret i1 %b
 }
@@ -102,7 +102,7 @@ entry:
   %b = icmp slt i32 %a, %x 
   ret i1 %b
   
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK: %b = icmp ne i32 %x, -2147483648
 ; CHECK: ret i1 %b
 }
@@ -111,7 +111,7 @@ define i1 @test11(i32 %x) {
   %a = add nsw i32 %x, 8
   %b = icmp slt i32 %x, %a
   ret i1 %b
-; CHECK: @test11  
+; CHECK-LABEL: @test11(
 ; CHECK: ret i1 true
 }
 
@@ -120,7 +120,7 @@ define i1 @test12(i1 %A) {
   %S = select i1 %A, i64 -4294967295, i64 8589934591
   %B = icmp ne i64 bitcast (<2 x i32> <i32 1, i32 -1> to i64), %S
   ret i1 %B
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK-NEXT: = xor i1 %A, true
 ; CHECK-NEXT: ret i1
 }
@@ -130,7 +130,7 @@ define i1 @test13(i8 %X) nounwind readnone {
 entry:
         %cmp = icmp slt i8 undef, %X
         ret i1 %cmp
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK: ret i1 false
 }
 
@@ -138,7 +138,7 @@ define i1 @test14(i8 %X) nounwind readnone {
 entry:
         %cmp = icmp slt i8 undef, -128
         ret i1 %cmp
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK: ret i1 false
 }
 
@@ -146,7 +146,7 @@ define i1 @test15() nounwind readnone {
 entry:
         %cmp = icmp eq i8 undef, -128
         ret i1 %cmp
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 ; CHECK: ret i1 undef
 }
 
@@ -154,7 +154,7 @@ define i1 @test16() nounwind readnone {
 entry:
         %cmp = icmp ne i8 undef, -128
         ret i1 %cmp
-; CHECK: @test16
+; CHECK-LABEL: @test16(
 ; CHECK: ret i1 undef
 }
 
@@ -163,7 +163,7 @@ define i1 @test17(i32 %x) nounwind {
   %and = and i32 %shl, 8
   %cmp = icmp eq i32 %and, 0
   ret i1 %cmp
-; CHECK: @test17
+; CHECK-LABEL: @test17(
 ; CHECK-NEXT: %cmp = icmp ne i32 %x, 3
 }
 
@@ -173,7 +173,7 @@ define i1 @test18(i32 %x) nounwind {
   %and = and i32 %sh, 1
   %cmp = icmp eq i32 %and, 0
   ret i1 %cmp
-; CHECK: @test18
+; CHECK-LABEL: @test18(
 ; CHECK-NEXT: %cmp = icmp ne i32 %x, 3
 }
 
@@ -182,7 +182,7 @@ define i1 @test19(i32 %x) nounwind {
   %and = and i32 %shl, 8
   %cmp = icmp eq i32 %and, 8
   ret i1 %cmp
-; CHECK: @test19
+; CHECK-LABEL: @test19(
 ; CHECK-NEXT: %cmp = icmp eq i32 %x, 3
 }
 
@@ -191,12 +191,12 @@ define i1 @test20(i32 %x) nounwind {
   %and = and i32 %shl, 8
   %cmp = icmp ne i32 %and, 0
   ret i1 %cmp
-; CHECK: @test20
+; CHECK-LABEL: @test20(
 ; CHECK-NEXT: %cmp = icmp eq i32 %x, 3
 }
 
 define i1 @test21(i8 %x, i8 %y) {
-; CHECK: @test21
+; CHECK-LABEL: @test21(
 ; CHECK-NOT: or i8
 ; CHECK: icmp ugt
   %A = or i8 %x, 1
@@ -205,7 +205,7 @@ define i1 @test21(i8 %x, i8 %y) {
 }
 
 define i1 @test22(i8 %x, i8 %y) {
-; CHECK: @test22
+; CHECK-LABEL: @test22(
 ; CHECK-NOT: or i8
 ; CHECK: icmp ult
   %A = or i8 %x, 1
@@ -214,7 +214,7 @@ define i1 @test22(i8 %x, i8 %y) {
 }
 
 ; PR2740
-; CHECK: @test23
+; CHECK-LABEL: @test23(
 ; CHECK: icmp sgt i32 %x, 1328634634
 define i1 @test23(i32 %x) nounwind {
 	%i3 = sdiv i32 %x, -1328634635
@@ -225,7 +225,7 @@ define i1 @test23(i32 %x) nounwind {
 @X = global [1000 x i32] zeroinitializer
 
 ; PR8882
-; CHECK: @test24
+; CHECK-LABEL: @test24(
 ; CHECK:    %cmp = icmp eq i64 %i, 1000
 ; CHECK:   ret i1 %cmp
 define i1 @test24(i64 %i) {
@@ -234,7 +234,7 @@ define i1 @test24(i64 %i) {
   ret i1 %cmp
 }
 
-; CHECK: @test25
+; CHECK-LABEL: @test25(
 ; X + Z > Y + Z -> X > Y if there is no overflow.
 ; CHECK: %c = icmp sgt i32 %x, %y
 ; CHECK: ret i1 %c
@@ -245,7 +245,7 @@ define i1 @test25(i32 %x, i32 %y, i32 %z) {
   ret i1 %c
 }
 
-; CHECK: @test26
+; CHECK-LABEL: @test26(
 ; X + Z > Y + Z -> X > Y if there is no overflow.
 ; CHECK: %c = icmp ugt i32 %x, %y
 ; CHECK: ret i1 %c
@@ -256,7 +256,7 @@ define i1 @test26(i32 %x, i32 %y, i32 %z) {
   ret i1 %c
 }
 
-; CHECK: @test27
+; CHECK-LABEL: @test27(
 ; X - Z > Y - Z -> X > Y if there is no overflow.
 ; CHECK: %c = icmp sgt i32 %x, %y
 ; CHECK: ret i1 %c
@@ -267,7 +267,7 @@ define i1 @test27(i32 %x, i32 %y, i32 %z) {
   ret i1 %c
 }
 
-; CHECK: @test28
+; CHECK-LABEL: @test28(
 ; X - Z > Y - Z -> X > Y if there is no overflow.
 ; CHECK: %c = icmp ugt i32 %x, %y
 ; CHECK: ret i1 %c
@@ -278,7 +278,7 @@ define i1 @test28(i32 %x, i32 %y, i32 %z) {
   ret i1 %c
 }
 
-; CHECK: @test29
+; CHECK-LABEL: @test29(
 ; X + Y > X -> Y > 0 if there is no overflow.
 ; CHECK: %c = icmp sgt i32 %y, 0
 ; CHECK: ret i1 %c
@@ -288,7 +288,7 @@ define i1 @test29(i32 %x, i32 %y) {
   ret i1 %c
 }
 
-; CHECK: @test30
+; CHECK-LABEL: @test30(
 ; X + Y > X -> Y > 0 if there is no overflow.
 ; CHECK: %c = icmp ne i32 %y, 0
 ; CHECK: ret i1 %c
@@ -298,7 +298,7 @@ define i1 @test30(i32 %x, i32 %y) {
   ret i1 %c
 }
 
-; CHECK: @test31
+; CHECK-LABEL: @test31(
 ; X > X + Y -> 0 > Y if there is no overflow.
 ; CHECK: %c = icmp slt i32 %y, 0
 ; CHECK: ret i1 %c
@@ -308,7 +308,7 @@ define i1 @test31(i32 %x, i32 %y) {
   ret i1 %c
 }
 
-; CHECK: @test32
+; CHECK-LABEL: @test32(
 ; X > X + Y -> 0 > Y if there is no overflow.
 ; CHECK: ret i1 false
 define i1 @test32(i32 %x, i32 %y) {
@@ -317,7 +317,7 @@ define i1 @test32(i32 %x, i32 %y) {
   ret i1 %c
 }
 
-; CHECK: @test33
+; CHECK-LABEL: @test33(
 ; X - Y > X -> 0 > Y if there is no overflow.
 ; CHECK: %c = icmp slt i32 %y, 0
 ; CHECK: ret i1 %c
@@ -327,7 +327,7 @@ define i1 @test33(i32 %x, i32 %y) {
   ret i1 %c
 }
 
-; CHECK: @test34
+; CHECK-LABEL: @test34(
 ; X - Y > X -> 0 > Y if there is no overflow.
 ; CHECK: ret i1 false
 define i1 @test34(i32 %x, i32 %y) {
@@ -336,7 +336,7 @@ define i1 @test34(i32 %x, i32 %y) {
   ret i1 %c
 }
 
-; CHECK: @test35
+; CHECK-LABEL: @test35(
 ; X > X - Y -> Y > 0 if there is no overflow.
 ; CHECK: %c = icmp sgt i32 %y, 0
 ; CHECK: ret i1 %c
@@ -346,7 +346,7 @@ define i1 @test35(i32 %x, i32 %y) {
   ret i1 %c
 }
 
-; CHECK: @test36
+; CHECK-LABEL: @test36(
 ; X > X - Y -> Y > 0 if there is no overflow.
 ; CHECK: %c = icmp ne i32 %y, 0
 ; CHECK: ret i1 %c
@@ -356,7 +356,7 @@ define i1 @test36(i32 %x, i32 %y) {
   ret i1 %c
 }
 
-; CHECK: @test37
+; CHECK-LABEL: @test37(
 ; X - Y > X - Z -> Z > Y if there is no overflow.
 ; CHECK: %c = icmp sgt i32 %z, %y
 ; CHECK: ret i1 %c
@@ -367,7 +367,7 @@ define i1 @test37(i32 %x, i32 %y, i32 %z) {
   ret i1 %c
 }
 
-; CHECK: @test38
+; CHECK-LABEL: @test38(
 ; X - Y > X - Z -> Z > Y if there is no overflow.
 ; CHECK: %c = icmp ugt i32 %z, %y
 ; CHECK: ret i1 %c
@@ -379,7 +379,7 @@ define i1 @test38(i32 %x, i32 %y, i32 %z) {
 }
 
 ; PR9343 #1
-; CHECK: @test39
+; CHECK-LABEL: @test39(
 ; CHECK: %B = icmp eq i32 %X, 0
 define i1 @test39(i32 %X, i32 %Y) {
   %A = ashr exact i32 %X, %Y
@@ -387,7 +387,7 @@ define i1 @test39(i32 %X, i32 %Y) {
   ret i1 %B
 }
 
-; CHECK: @test40
+; CHECK-LABEL: @test40(
 ; CHECK: %B = icmp ne i32 %X, 0
 define i1 @test40(i32 %X, i32 %Y) {
   %A = lshr exact i32 %X, %Y
@@ -396,7 +396,7 @@ define i1 @test40(i32 %X, i32 %Y) {
 }
 
 ; PR9343 #3
-; CHECK: @test41
+; CHECK-LABEL: @test41(
 ; CHECK: ret i1 true
 define i1 @test41(i32 %X, i32 %Y) {
   %A = urem i32 %X, %Y
@@ -404,7 +404,7 @@ define i1 @test41(i32 %X, i32 %Y) {
   ret i1 %B
 }
 
-; CHECK: @test42
+; CHECK-LABEL: @test42(
 ; CHECK: %B = icmp sgt i32 %Y, -1
 define i1 @test42(i32 %X, i32 %Y) {
   %A = srem i32 %X, %Y
@@ -412,7 +412,7 @@ define i1 @test42(i32 %X, i32 %Y) {
   ret i1 %B
 }
 
-; CHECK: @test43
+; CHECK-LABEL: @test43(
 ; CHECK: %B = icmp slt i32 %Y, 0
 define i1 @test43(i32 %X, i32 %Y) {
   %A = srem i32 %X, %Y
@@ -420,7 +420,7 @@ define i1 @test43(i32 %X, i32 %Y) {
   ret i1 %B
 }
 
-; CHECK: @test44
+; CHECK-LABEL: @test44(
 ; CHECK: %B = icmp sgt i32 %Y, -1
 define i1 @test44(i32 %X, i32 %Y) {
   %A = srem i32 %X, %Y
@@ -428,7 +428,7 @@ define i1 @test44(i32 %X, i32 %Y) {
   ret i1 %B
 }
 
-; CHECK: @test45
+; CHECK-LABEL: @test45(
 ; CHECK: %B = icmp slt i32 %Y, 0
 define i1 @test45(i32 %X, i32 %Y) {
   %A = srem i32 %X, %Y
@@ -437,7 +437,7 @@ define i1 @test45(i32 %X, i32 %Y) {
 }
 
 ; PR9343 #4
-; CHECK: @test46
+; CHECK-LABEL: @test46(
 ; CHECK: %C = icmp ult i32 %X, %Y
 define i1 @test46(i32 %X, i32 %Y, i32 %Z) {
   %A = ashr exact i32 %X, %Z
@@ -447,7 +447,7 @@ define i1 @test46(i32 %X, i32 %Y, i32 %Z) {
 }
 
 ; PR9343 #5
-; CHECK: @test47
+; CHECK-LABEL: @test47(
 ; CHECK: %C = icmp ugt i32 %X, %Y
 define i1 @test47(i32 %X, i32 %Y, i32 %Z) {
   %A = ashr exact i32 %X, %Z
@@ -457,7 +457,7 @@ define i1 @test47(i32 %X, i32 %Y, i32 %Z) {
 }
 
 ; PR9343 #8
-; CHECK: @test48
+; CHECK-LABEL: @test48(
 ; CHECK: %C = icmp eq i32 %X, %Y
 define i1 @test48(i32 %X, i32 %Y, i32 %Z) {
   %A = sdiv exact i32 %X, %Z
@@ -467,7 +467,7 @@ define i1 @test48(i32 %X, i32 %Y, i32 %Z) {
 }
 
 ; PR8469
-; CHECK: @test49
+; CHECK-LABEL: @test49(
 ; CHECK: ret <2 x i1> <i1 true, i1 true>
 define <2 x i1> @test49(<2 x i32> %tmp3) {
 entry:
@@ -477,7 +477,7 @@ entry:
 }
 
 ; PR9343 #7
-; CHECK: @test50
+; CHECK-LABEL: @test50(
 ; CHECK: ret i1 true
 define i1 @test50(i16 %X, i32 %Y) {
   %A = zext i16 %X to i32
@@ -486,7 +486,7 @@ define i1 @test50(i16 %X, i32 %Y) {
   ret i1 %C
 }
 
-; CHECK: @test51
+; CHECK-LABEL: @test51(
 ; CHECK: ret i1 %C
 define i1 @test51(i32 %X, i32 %Y) {
   %A = and i32 %X, 2147483648
@@ -495,7 +495,7 @@ define i1 @test51(i32 %X, i32 %Y) {
   ret i1 %C
 }
 
-; CHECK: @test52
+; CHECK-LABEL: @test52(
 ; CHECK-NEXT: and i32 %x1, 16711935
 ; CHECK-NEXT: icmp eq i32 {{.*}}, 4980863
 ; CHECK-NEXT: ret i1
@@ -511,7 +511,7 @@ define i1 @test52(i32 %x1) nounwind {
 }
 
 ; PR9838
-; CHECK: @test53
+; CHECK-LABEL: @test53(
 ; CHECK-NEXT: ashr exact
 ; CHECK-NEXT: ashr
 ; CHECK-NEXT: icmp
@@ -522,7 +522,7 @@ define i1 @test53(i32 %a, i32 %b) nounwind {
  ret i1 %z
 }
 
-; CHECK: @test54
+; CHECK-LABEL: @test54(
 ; CHECK-NEXT: %and = and i8 %a, -64
 ; CHECK-NEXT: icmp eq i8 %and, -128
 define i1 @test54(i8 %a) nounwind {
@@ -532,7 +532,7 @@ define i1 @test54(i8 %a) nounwind {
   ret i1 %ret
 }
 
-; CHECK: @test55
+; CHECK-LABEL: @test55(
 ; CHECK-NEXT: icmp eq i32 %a, -123
 define i1 @test55(i32 %a) {
   %sub = sub i32 0, %a
@@ -540,7 +540,7 @@ define i1 @test55(i32 %a) {
   ret i1 %cmp
 }
 
-; CHECK: @test56
+; CHECK-LABEL: @test56(
 ; CHECK-NEXT: icmp eq i32 %a, -113
 define i1 @test56(i32 %a) {
   %sub = sub i32 10, %a
@@ -550,7 +550,7 @@ define i1 @test56(i32 %a) {
 
 ; PR10267 Don't make icmps more expensive when no other inst is subsumed.
 declare void @foo(i32)
-; CHECK: @test57
+; CHECK-LABEL: @test57(
 ; CHECK: %and = and i32 %a, -2
 ; CHECK: %cmp = icmp ne i32 %and, 0
 define i1 @test57(i32 %a) {
@@ -561,7 +561,7 @@ define i1 @test57(i32 %a) {
 }
 
 ; rdar://problem/10482509
-; CHECK: @cmpabs1
+; CHECK-LABEL: @cmpabs1(
 ; CHECK-NEXT: icmp ne
 define zeroext i1 @cmpabs1(i64 %val) {
   %sub = sub nsw i64 0, %val
@@ -571,7 +571,7 @@ define zeroext i1 @cmpabs1(i64 %val) {
   ret i1 %tobool
 }
 
-; CHECK: @cmpabs2
+; CHECK-LABEL: @cmpabs2(
 ; CHECK-NEXT: icmp ne
 define zeroext i1 @cmpabs2(i64 %val) {
   %sub = sub nsw i64 0, %val
@@ -581,7 +581,7 @@ define zeroext i1 @cmpabs2(i64 %val) {
   ret i1 %tobool
 }
 
-; CHECK: @test58
+; CHECK-LABEL: @test58(
 ; CHECK-NEXT: call i32 @test58_d(i64 36029346783166592)
 define void @test58() nounwind {
   %cast = bitcast <1 x i64> <i64 36029346783166592> to i64
@@ -599,7 +599,7 @@ define i1 @test59(i8* %foo) {
   %use = ptrtoint i8* %cast1 to i64
   %call = call i32 @test58_d(i64 %use) nounwind
   ret i1 %cmp
-; CHECK: @test59
+; CHECK-LABEL: @test59(
 ; CHECK: ret i1 true
 }
 
@@ -610,7 +610,7 @@ define i1 @test60(i8* %foo, i64 %i, i64 %j) {
   %cast1 = bitcast i32* %gep1 to i8*
   %cmp = icmp ult i8* %cast1, %gep2
   ret i1 %cmp
-; CHECK: @test60
+; CHECK-LABEL: @test60(
 ; CHECK-NEXT: %gep1.idx = shl nuw i64 %i, 2
 ; CHECK-NEXT: icmp slt i64 %gep1.idx, %j
 ; CHECK-NEXT: ret i1
@@ -624,7 +624,7 @@ define i1 @test61(i8* %foo, i64 %i, i64 %j) {
   %cmp = icmp ult i8* %cast1, %gep2
   ret i1 %cmp
 ; Don't transform non-inbounds GEPs.
-; CHECK: @test61
+; CHECK-LABEL: @test61(
 ; CHECK: icmp ult i8* %cast1, %gep2
 ; CHECK-NEXT: ret i1
 }
@@ -634,7 +634,7 @@ define i1 @test62(i8* %a) {
   %arrayidx2 = getelementptr inbounds i8* %a, i64 10
   %cmp = icmp slt i8* %arrayidx1, %arrayidx2
   ret i1 %cmp
-; CHECK: @test62
+; CHECK-LABEL: @test62(
 ; CHECK-NEXT: ret i1 true
 }
 
@@ -643,7 +643,7 @@ define i1 @test63(i8 %a, i32 %b) nounwind {
   %t = and i32 %b, 255
   %c = icmp eq i32 %z, %t
   ret i1 %c
-; CHECK: @test63
+; CHECK-LABEL: @test63(
 ; CHECK-NEXT: %1 = trunc i32 %b to i8
 ; CHECK-NEXT: %c = icmp eq i8 %1, %a
 ; CHECK-NEXT: ret i1 %c
@@ -654,7 +654,7 @@ define i1 @test64(i8 %a, i32 %b) nounwind {
   %z = zext i8 %a to i32
   %c = icmp eq i32 %t, %z
   ret i1 %c
-; CHECK: @test64
+; CHECK-LABEL: @test64(
 ; CHECK-NEXT: %1 = trunc i32 %b to i8
 ; CHECK-NEXT: %c = icmp eq i8 %1, %a
 ; CHECK-NEXT: ret i1 %c
@@ -664,7 +664,7 @@ define i1 @test65(i64 %A, i64 %B) {
   %s1 = add i64 %A, %B
   %s2 = add i64 %A, %B
   %cmp = icmp eq i64 %s1, %s2
-; CHECK: @test65
+; CHECK-LABEL: @test65(
 ; CHECK-NEXT: ret i1 true
   ret i1 %cmp
 }
@@ -673,12 +673,12 @@ define i1 @test66(i64 %A, i64 %B) {
   %s1 = add i64 %A, %B
   %s2 = add i64 %B, %A
   %cmp = icmp eq i64 %s1, %s2
-; CHECK: @test66
+; CHECK-LABEL: @test66(
 ; CHECK-NEXT: ret i1 true
   ret i1 %cmp
 }
 
-; CHECK: @test67
+; CHECK-LABEL: @test67(
 ; CHECK: %and = and i32 %x, 96
 ; CHECK: %cmp = icmp ne i32 %and, 0
 define i1 @test67(i32 %x) nounwind uwtable {
@@ -687,7 +687,7 @@ define i1 @test67(i32 %x) nounwind uwtable {
   ret i1 %cmp
 }
 
-; CHECK: @test68
+; CHECK-LABEL: @test68(
 ; CHECK: %cmp = icmp ugt i32 %and, 30
 define i1 @test68(i32 %x) nounwind uwtable {
   %and = and i32 %x, 127
@@ -696,7 +696,7 @@ define i1 @test68(i32 %x) nounwind uwtable {
 }
 
 ; PR14708
-; CHECK: @test69
+; CHECK-LABEL: @test69(
 ; CHECK: %1 = and i32 %c, -33
 ; CHECK: %2 = icmp eq i32 %1, 65
 ; CHECK: ret i1 %2
@@ -708,7 +708,7 @@ define i1 @test69(i32 %c) nounwind uwtable {
 }
 
 ; PR15940
-; CHECK: @test70
+; CHECK-LABEL: @test70(
 ; CHECK-NEXT: %A = srem i32 5, %X
 ; CHECK-NEXT: %C = icmp ne i32 %A, 2
 ; CHECK-NEXT: ret i1 %C
@@ -719,7 +719,7 @@ define i1 @test70(i32 %X) {
   ret i1 %C
 }
 
-; CHECK: @icmp_sext16trunc
+; CHECK-LABEL: @icmp_sext16trunc(
 ; CHECK-NEXT: %1 = trunc i32 %x to i16
 ; CHECK-NEXT: %cmp = icmp slt i16 %1, 36
 define i1 @icmp_sext16trunc(i32 %x) {
@@ -729,7 +729,7 @@ define i1 @icmp_sext16trunc(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_sext8trunc
+; CHECK-LABEL: @icmp_sext8trunc(
 ; CHECK-NEXT: %1 = trunc i32 %x to i8
 ; CHECK-NEXT: %cmp = icmp slt i8 %1, 36
 define i1 @icmp_sext8trunc(i32 %x) {
@@ -739,7 +739,7 @@ define i1 @icmp_sext8trunc(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_shl16
+; CHECK-LABEL: @icmp_shl16(
 ; CHECK-NEXT: %1 = trunc i32 %x to i16
 ; CHECK-NEXT: %cmp = icmp slt i16 %1, 36
 define i1 @icmp_shl16(i32 %x) {
@@ -748,7 +748,7 @@ define i1 @icmp_shl16(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_shl24
+; CHECK-LABEL: @icmp_shl24(
 ; CHECK-NEXT: %1 = trunc i32 %x to i8
 ; CHECK-NEXT: %cmp = icmp slt i8 %1, 36
 define i1 @icmp_shl24(i32 %x) {
@@ -759,7 +759,7 @@ define i1 @icmp_shl24(i32 %x) {
 
 ; If the (shl x, C) preserved the sign and this is a sign test,
 ; compare the LHS operand instead
-; CHECK: @icmp_shl_nsw_sgt
+; CHECK-LABEL: @icmp_shl_nsw_sgt(
 ; CHECK-NEXT: icmp sgt i32 %x, 0
 define i1 @icmp_shl_nsw_sgt(i32 %x) {
   %shl = shl nsw i32 %x, 21
@@ -767,7 +767,7 @@ define i1 @icmp_shl_nsw_sgt(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_shl_nsw_sge0
+; CHECK-LABEL: @icmp_shl_nsw_sge0(
 ; CHECK-NEXT: icmp sgt i32 %x, -1
 define i1 @icmp_shl_nsw_sge0(i32 %x) {
   %shl = shl nsw i32 %x, 21
@@ -775,7 +775,7 @@ define i1 @icmp_shl_nsw_sge0(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_shl_nsw_sge1
+; CHECK-LABEL: @icmp_shl_nsw_sge1(
 ; CHECK-NEXT: icmp sgt i32 %x, 0
 define i1 @icmp_shl_nsw_sge1(i32 %x) {
   %shl = shl nsw i32 %x, 21
@@ -784,7 +784,7 @@ define i1 @icmp_shl_nsw_sge1(i32 %x) {
 }
 
 ; Checks for icmp (eq|ne) (shl x, C), 0
-; CHECK: @icmp_shl_nsw_eq
+; CHECK-LABEL: @icmp_shl_nsw_eq(
 ; CHECK-NEXT: icmp eq i32 %x, 0
 define i1 @icmp_shl_nsw_eq(i32 %x) {
   %mul = shl nsw i32 %x, 5
@@ -792,7 +792,7 @@ define i1 @icmp_shl_nsw_eq(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_shl_eq
+; CHECK-LABEL: @icmp_shl_eq(
 ; CHECK-NOT: icmp eq i32 %mul, 0
 define i1 @icmp_shl_eq(i32 %x) {
   %mul = shl i32 %x, 5
@@ -800,7 +800,7 @@ define i1 @icmp_shl_eq(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_shl_nsw_ne
+; CHECK-LABEL: @icmp_shl_nsw_ne(
 ; CHECK-NEXT: icmp ne i32 %x, 0
 define i1 @icmp_shl_nsw_ne(i32 %x) {
   %mul = shl nsw i32 %x, 7
@@ -808,7 +808,7 @@ define i1 @icmp_shl_nsw_ne(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_shl_ne
+; CHECK-LABEL: @icmp_shl_ne(
 ; CHECK-NOT: icmp ne i32 %x, 0
 define i1 @icmp_shl_ne(i32 %x) {
   %mul = shl i32 %x, 7
@@ -818,7 +818,7 @@ define i1 @icmp_shl_ne(i32 %x) {
 
 ; If the (mul x, C) preserved the sign and this is sign test,
 ; compare the LHS operand instead
-; CHECK: @icmp_mul_nsw
+; CHECK-LABEL: @icmp_mul_nsw(
 ; CHECK-NEXT: icmp sgt i32 %x, 0
 define i1 @icmp_mul_nsw(i32 %x) {
   %mul = mul nsw i32 %x, 12
@@ -826,7 +826,7 @@ define i1 @icmp_mul_nsw(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_mul_nsw1
+; CHECK-LABEL: @icmp_mul_nsw1(
 ; CHECK-NEXT: icmp slt i32 %x, 0
 define i1 @icmp_mul_nsw1(i32 %x) {
   %mul = mul nsw i32 %x, 12
@@ -834,7 +834,7 @@ define i1 @icmp_mul_nsw1(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_mul_nsw_neg
+; CHECK-LABEL: @icmp_mul_nsw_neg(
 ; CHECK-NEXT: icmp slt i32 %x, 1
 define i1 @icmp_mul_nsw_neg(i32 %x) {
   %mul = mul nsw i32 %x, -12
@@ -842,7 +842,7 @@ define i1 @icmp_mul_nsw_neg(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_mul_nsw_neg1
+; CHECK-LABEL: @icmp_mul_nsw_neg1(
 ; CHECK-NEXT: icmp slt i32 %x, 0
 define i1 @icmp_mul_nsw_neg1(i32 %x) {
   %mul = mul nsw i32 %x, -12
@@ -850,7 +850,7 @@ define i1 @icmp_mul_nsw_neg1(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_mul_nsw_0
+; CHECK-LABEL: @icmp_mul_nsw_0(
 ; CHECK-NOT: icmp sgt i32 %x, 0
 define i1 @icmp_mul_nsw_0(i32 %x) {
   %mul = mul nsw i32 %x, 0
@@ -858,7 +858,7 @@ define i1 @icmp_mul_nsw_0(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_mul
+; CHECK-LABEL: @icmp_mul(
 ; CHECK-NEXT: %mul = mul i32 %x, -12
 define i1 @icmp_mul(i32 %x) {
   %mul = mul i32 %x, -12
@@ -867,7 +867,7 @@ define i1 @icmp_mul(i32 %x) {
 }
 
 ; Checks for icmp (eq|ne) (mul x, C), 0
-; CHECK: @icmp_mul_neq0
+; CHECK-LABEL: @icmp_mul_neq0(
 ; CHECK-NEXT: icmp ne i32 %x, 0
 define i1 @icmp_mul_neq0(i32 %x) {
   %mul = mul nsw i32 %x, -12
@@ -875,7 +875,7 @@ define i1 @icmp_mul_neq0(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_mul_eq0
+; CHECK-LABEL: @icmp_mul_eq0(
 ; CHECK-NEXT: icmp eq i32 %x, 0
 define i1 @icmp_mul_eq0(i32 %x) {
   %mul = mul nsw i32 %x, 12
@@ -883,7 +883,7 @@ define i1 @icmp_mul_eq0(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_mul0_eq0
+; CHECK-LABEL: @icmp_mul0_eq0(
 ; CHECK-NEXT: ret i1 true
 define i1 @icmp_mul0_eq0(i32 %x) {
   %mul = mul i32 %x, 0
@@ -891,7 +891,7 @@ define i1 @icmp_mul0_eq0(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_mul0_ne0
+; CHECK-LABEL: @icmp_mul0_ne0(
 ; CHECK-NEXT: ret i1 false
 define i1 @icmp_mul0_ne0(i32 %x) {
   %mul = mul i32 %x, 0
@@ -899,7 +899,7 @@ define i1 @icmp_mul0_ne0(i32 %x) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_sub1_sge
+; CHECK-LABEL: @icmp_sub1_sge(
 ; CHECK-NEXT: icmp sgt i32 %x, %y
 define i1 @icmp_sub1_sge(i32 %x, i32 %y) {
   %sub = add nsw i32 %x, -1
@@ -907,7 +907,7 @@ define i1 @icmp_sub1_sge(i32 %x, i32 %y) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_add1_sgt
+; CHECK-LABEL: @icmp_add1_sgt(
 ; CHECK-NEXT: icmp sge i32 %x, %y
 define i1 @icmp_add1_sgt(i32 %x, i32 %y) {
   %add = add nsw i32 %x, 1
@@ -915,7 +915,7 @@ define i1 @icmp_add1_sgt(i32 %x, i32 %y) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_sub1_slt
+; CHECK-LABEL: @icmp_sub1_slt(
 ; CHECK-NEXT: icmp sle i32 %x, %y
 define i1 @icmp_sub1_slt(i32 %x, i32 %y) {
   %sub = add nsw i32 %x, -1
@@ -923,7 +923,7 @@ define i1 @icmp_sub1_slt(i32 %x, i32 %y) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_add1_sle
+; CHECK-LABEL: @icmp_add1_sle(
 ; CHECK-NEXT: icmp slt i32 %x, %y
 define i1 @icmp_add1_sle(i32 %x, i32 %y) {
   %add = add nsw i32 %x, 1
@@ -931,7 +931,7 @@ define i1 @icmp_add1_sle(i32 %x, i32 %y) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_add20_sge_add57
+; CHECK-LABEL: @icmp_add20_sge_add57(
 ; CHECK-NEXT: [[ADD:%[a-z0-9]+]] = add nsw i32 %y, 37
 ; CHECK-NEXT: icmp sle i32 [[ADD]], %x
 define i1 @icmp_add20_sge_add57(i32 %x, i32 %y) {
@@ -941,7 +941,7 @@ define i1 @icmp_add20_sge_add57(i32 %x, i32 %y) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_sub57_sge_sub20
+; CHECK-LABEL: @icmp_sub57_sge_sub20(
 ; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = add nsw i32 %x, -37
 ; CHECK-NEXT: icmp sge i32 [[SUB]], %y
 define i1 @icmp_sub57_sge_sub20(i32 %x, i32 %y) {
@@ -951,7 +951,7 @@ define i1 @icmp_sub57_sge_sub20(i32 %x, i32 %y) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_and_shl_neg_ne_0
+; CHECK-LABEL: @icmp_and_shl_neg_ne_0(
 ; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 1, %B
 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], %A
 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 [[AND]], 0
@@ -964,7 +964,7 @@ define i1 @icmp_and_shl_neg_ne_0(i32 %A, i32 %B) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_and_shl_neg_eq_0
+; CHECK-LABEL: @icmp_and_shl_neg_eq_0(
 ; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 1, %B
 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], %A
 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 [[AND]], 0
@@ -977,7 +977,7 @@ define i1 @icmp_and_shl_neg_eq_0(i32 %A, i32 %B) {
   ret i1 %cmp
 }
 
-; CHECK: @icmp_add_and_shr_ne_0
+; CHECK-LABEL: @icmp_add_and_shr_ne_0(
 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %X, 240
 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 [[AND]], 224
 ; CHECK-NEXT: ret i1 [[CMP]]
@@ -990,7 +990,7 @@ define i1 @icmp_add_and_shr_ne_0(i32 %X) {
 }
 
 ; PR16244
-; CHECK: define i1 @test71
+; CHECK-LABEL: define i1 @test71(
 ; CHECK-NEXT: ret i1 false
 define i1 @test71(i8* %x) {
   %a = getelementptr i8* %x, i64 8
@@ -998,3 +998,204 @@ define i1 @test71(i8* %x) {
   %c = icmp ugt i8* %a, %b
   ret i1 %c
 }
+
+; CHECK-LABEL: @icmp_shl_1_V_ult_32(
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ult i32 %V, 5
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_shl_1_V_ult_32(i32 %V) {
+  %shl = shl i32 1, %V
+  %cmp = icmp ult i32 %shl, 32
+  ret i1 %cmp
+}
+
+; CHECK-LABEL: @icmp_shl_1_V_eq_32(
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 %V, 5
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_shl_1_V_eq_32(i32 %V) {
+  %shl = shl i32 1, %V
+  %cmp = icmp eq i32 %shl, 32
+  ret i1 %cmp
+}
+
+; CHECK-LABEL: @icmp_shl_1_V_eq_31(
+; CHECK-NEXT: ret i1 false
+define i1 @icmp_shl_1_V_eq_31(i32 %V) {
+  %shl = shl i32 1, %V
+  %cmp = icmp eq i32 %shl, 31
+  ret i1 %cmp
+}
+
+; CHECK-LABEL: @icmp_shl_1_V_ne_31(
+; CHECK-NEXT: ret i1 true
+define i1 @icmp_shl_1_V_ne_31(i32 %V) {
+  %shl = shl i32 1, %V
+  %cmp = icmp ne i32 %shl, 31
+  ret i1 %cmp
+}
+
+; CHECK-LABEL: @icmp_shl_1_V_ult_30(
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ult i32 %V, 5
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_shl_1_V_ult_30(i32 %V) {
+  %shl = shl i32 1, %V
+  %cmp = icmp ult i32 %shl, 30
+  ret i1 %cmp
+}
+
+; CHECK-LABEL: @icmp_shl_1_V_ugt_30(
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ugt i32 %V, 4
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_shl_1_V_ugt_30(i32 %V) {
+  %shl = shl i32 1, %V
+  %cmp = icmp ugt i32 %shl, 30
+  ret i1 %cmp
+}
+
+; CHECK-LABEL: @icmp_shl_1_V_ule_30(
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ult i32 %V, 5
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_shl_1_V_ule_30(i32 %V) {
+  %shl = shl i32 1, %V
+  %cmp = icmp ule i32 %shl, 30
+  ret i1 %cmp
+}
+
+; CHECK-LABEL: @icmp_shl_1_V_uge_30(
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ugt i32 %V, 4
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_shl_1_V_uge_30(i32 %V) {
+  %shl = shl i32 1, %V
+  %cmp = icmp uge i32 %shl, 30
+  ret i1 %cmp
+}
+
+; CHECK-LABEL: @icmp_shl_1_V_uge_2147483648(
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 %V, 31
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_shl_1_V_uge_2147483648(i32 %V) {
+  %shl = shl i32 1, %V
+  %cmp = icmp uge i32 %shl, 2147483648
+  ret i1 %cmp
+}
+
+; CHECK-LABEL: @icmp_shl_1_V_ugt_2147483648(
+; CHECK-NEXT: ret i1 false
+define i1 @icmp_shl_1_V_ugt_2147483648(i32 %V) {
+  %shl = shl i32 1, %V
+  %cmp = icmp ugt i32 %shl, 2147483648
+  ret i1 %cmp
+}
+
+; CHECK-LABEL: @icmp_shl_1_V_ule_2147483648(
+; CHECK-NEXT: ret i1 true
+define i1 @icmp_shl_1_V_ule_2147483648(i32 %V) {
+  %shl = shl i32 1, %V
+  %cmp = icmp ule i32 %shl, 2147483648
+  ret i1 %cmp
+}
+
+; CHECK-LABEL: @icmp_shl_1_V_ult_2147483648(
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 %V, 31
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_shl_1_V_ult_2147483648(i32 %V) {
+  %shl = shl i32 1, %V
+  %cmp = icmp ult i32 %shl, 2147483648
+  ret i1 %cmp
+}
+
+; CHECK-LABEL: @or_icmp_eq_B_0_icmp_ult_A_B(
+; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = add i64 %b, -1
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp uge i64 [[SUB]], %a
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @or_icmp_eq_B_0_icmp_ult_A_B(i64 %a, i64 %b) {
+  %1 = icmp eq i64 %b, 0
+  %2 = icmp ult i64 %a, %b
+  %3 = or i1 %1, %2
+  ret i1 %3
+}
+
+; CHECK-LABEL: @icmp_add_ult_2(
+; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %X, -2
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 [[AND]], 14
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_add_ult_2(i32 %X) {
+  %add = add i32 %X, -14
+  %cmp = icmp ult i32 %add, 2
+  ret i1 %cmp
+}
+
+; CHECK: @icmp_add_X_-14_ult_2
+; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %X, -2
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 [[AND]], 14
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_add_X_-14_ult_2(i32 %X) {
+  %add = add i32 %X, -14
+  %cmp = icmp ult i32 %add, 2
+  ret i1 %cmp
+}
+
+; CHECK-LABEL: @icmp_sub_3_X_ult_2(
+; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 %X, 1
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 [[OR]], 3
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_sub_3_X_ult_2(i32 %X) {
+  %add = sub i32 3, %X
+  %cmp = icmp ult i32 %add, 2
+  ret i1 %cmp
+}
+
+; CHECK: @icmp_add_X_-14_uge_2
+; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %X, -2
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 [[AND]], 14
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_add_X_-14_uge_2(i32 %X) {
+  %add = add i32 %X, -14
+  %cmp = icmp uge i32 %add, 2
+  ret i1 %cmp
+}
+
+; CHECK-LABEL: @icmp_sub_3_X_uge_2(
+; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 %X, 1
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 [[OR]], 3
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_sub_3_X_uge_2(i32 %X) {
+  %add = sub i32 3, %X
+  %cmp = icmp uge i32 %add, 2
+  ret i1 %cmp
+}
+
+; CHECK: @icmp_and_X_-16_eq-16
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ugt i32 %X, -17
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_and_X_-16_eq-16(i32 %X) {
+  %and = and i32 %X, -16
+  %cmp = icmp eq i32 %and, -16
+  ret i1 %cmp
+}
+
+; CHECK: @icmp_and_X_-16_ne-16
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ult i32 %X, -16
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_and_X_-16_ne-16(i32 %X) {
+  %and = and i32 %X, -16
+  %cmp = icmp ne i32 %and, -16
+  ret i1 %cmp
+}
+
+; CHECK: @icmp_sub_-1_X_ult_4
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ugt i32 %X, -5
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_sub_-1_X_ult_4(i32 %X) {
+  %sub = sub i32 -1, %X
+  %cmp = icmp ult i32 %sub, 4
+  ret i1 %cmp
+}
+
+; CHECK: @icmp_sub_-1_X_uge_4
+; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ult i32 %X, -4
+; CHECK-NEXT: ret i1 [[CMP]]
+define i1 @icmp_sub_-1_X_uge_4(i32 %X) {
+  %sub = sub i32 -1, %X
+  %cmp = icmp uge i32 %sub, 4
+  ret i1 %cmp
+}
diff --git a/test/Transforms/InstCombine/idioms.ll b/test/Transforms/InstCombine/idioms.ll
index 1a21166..5848544 100644
--- a/test/Transforms/InstCombine/idioms.ll
+++ b/test/Transforms/InstCombine/idioms.ll
@@ -25,7 +25,7 @@ bb3:
 bb4:
         %f = phi i32 [ %not2, %bb2 ], [ %e, %bb3 ]
 	ret i32 %f
-; CHECK: @test_asr
+; CHECK-LABEL: @test_asr(
 ; CHECK: bb4:
 ; CHECK: %f = ashr i32 %a, %b
 ; CHECK: ret i32 %f
diff --git a/test/Transforms/InstCombine/intrinsics.ll b/test/Transforms/InstCombine/intrinsics.ll
index f334b3b..91c4470 100644
--- a/test/Transforms/InstCombine/intrinsics.ll
+++ b/test/Transforms/InstCombine/intrinsics.ll
@@ -14,7 +14,7 @@ define i8 @uaddtest1(i8 %A, i8 %B) {
   %x = call %overflow.result @llvm.uadd.with.overflow.i8(i8 %A, i8 %B)
   %y = extractvalue %overflow.result %x, 0
   ret i8 %y
-; CHECK: @uaddtest1
+; CHECK-LABEL: @uaddtest1(
 ; CHECK-NEXT: %y = add i8 %A, %B
 ; CHECK-NEXT: ret i8 %y
 }
@@ -27,7 +27,7 @@ define i8 @uaddtest2(i8 %A, i8 %B, i1* %overflowPtr) {
   %z = extractvalue %overflow.result %x, 1
   store i1 %z, i1* %overflowPtr
   ret i8 %y
-; CHECK: @uaddtest2
+; CHECK-LABEL: @uaddtest2(
 ; CHECK-NEXT: %and.A = and i8 %A, 127
 ; CHECK-NEXT: %and.B = and i8 %B, 127
 ; CHECK-NEXT: %x = add nuw i8 %and.A, %and.B
@@ -43,7 +43,7 @@ define i8 @uaddtest3(i8 %A, i8 %B, i1* %overflowPtr) {
   %z = extractvalue %overflow.result %x, 1
   store i1 %z, i1* %overflowPtr
   ret i8 %y
-; CHECK: @uaddtest3
+; CHECK-LABEL: @uaddtest3(
 ; CHECK-NEXT: %or.A = or i8 %A, -128
 ; CHECK-NEXT: %or.B = or i8 %B, -128
 ; CHECK-NEXT: %x = add i8 %or.A, %or.B
@@ -57,7 +57,7 @@ define i8 @uaddtest4(i8 %A, i1* %overflowPtr) {
   %z = extractvalue %overflow.result %x, 1
   store i1 %z, i1* %overflowPtr
   ret i8 %y
-; CHECK: @uaddtest4
+; CHECK-LABEL: @uaddtest4(
 ; CHECK-NEXT: ret i8 undef
 }
 
@@ -67,7 +67,7 @@ define i8 @uaddtest5(i8 %A, i1* %overflowPtr) {
   %z = extractvalue %overflow.result %x, 1
   store i1 %z, i1* %overflowPtr
   ret i8 %y
-; CHECK: @uaddtest5
+; CHECK-LABEL: @uaddtest5(
 ; CHECK: ret i8 %A
 }
 
@@ -75,7 +75,7 @@ define i1 @uaddtest6(i8 %A, i8 %B) {
   %x = call %overflow.result @llvm.uadd.with.overflow.i8(i8 %A, i8 -4)
   %z = extractvalue %overflow.result %x, 1
   ret i1 %z
-; CHECK: @uaddtest6
+; CHECK-LABEL: @uaddtest6(
 ; CHECK-NEXT: %z = icmp ugt i8 %A, 3
 ; CHECK-NEXT: ret i1 %z
 }
@@ -84,7 +84,7 @@ define i8 @uaddtest7(i8 %A, i8 %B) {
   %x = call %overflow.result @llvm.uadd.with.overflow.i8(i8 %A, i8 %B)
   %z = extractvalue %overflow.result %x, 0
   ret i8 %z
-; CHECK: @uaddtest7
+; CHECK-LABEL: @uaddtest7(
 ; CHECK-NEXT: %z = add i8 %A, %B
 ; CHECK-NEXT: ret i8 %z
 }
@@ -96,7 +96,7 @@ define i8 @umultest1(i8 %A, i1* %overflowPtr) {
   %z = extractvalue %overflow.result %x, 1
   store i1 %z, i1* %overflowPtr
   ret i8 %y
-; CHECK: @umultest1
+; CHECK-LABEL: @umultest1(
 ; CHECK-NEXT: store i1 false, i1* %overflowPtr
 ; CHECK-NEXT: ret i8 0
 }
@@ -107,7 +107,7 @@ define i8 @umultest2(i8 %A, i1* %overflowPtr) {
   %z = extractvalue %overflow.result %x, 1
   store i1 %z, i1* %overflowPtr
   ret i8 %y
-; CHECK: @umultest2
+; CHECK-LABEL: @umultest2(
 ; CHECK-NEXT: store i1 false, i1* %overflowPtr
 ; CHECK-NEXT: ret i8 %A
 }
@@ -122,7 +122,7 @@ define i32 @umultest3(i32 %n) nounwind {
   %res = extractvalue %ov.result.32 %mul, 0
   %ret = select i1 %ov, i32 -1, i32 %res
   ret i32 %ret
-; CHECK: @umultest3
+; CHECK-LABEL: @umultest3(
 ; CHECK-NEXT: shr
 ; CHECK-NEXT: mul nuw
 ; CHECK-NEXT: ret
@@ -135,7 +135,7 @@ define i32 @umultest4(i32 %n) nounwind {
   %res = extractvalue %ov.result.32 %mul, 0
   %ret = select i1 %ov, i32 -1, i32 %res
   ret i32 %ret
-; CHECK: @umultest4
+; CHECK-LABEL: @umultest4(
 ; CHECK: umul.with.overflow
 }
 
@@ -150,7 +150,7 @@ entry:
   %C = tail call double @llvm.powi.f64(double %V, i32 1) nounwind
   store volatile double %C, double* %P
   ret void
-; CHECK: @powi
+; CHECK-LABEL: @powi(
 ; CHECK: %A = fdiv double 1.0{{.*}}, %V
 ; CHECK: store volatile double %A, 
 ; CHECK: store volatile double 1.0 
@@ -163,7 +163,7 @@ entry:
   %and = and i32 %or, -8
   %count = tail call i32 @llvm.cttz.i32(i32 %and, i1 true) nounwind readnone
   ret i32 %count
-; CHECK: @cttz
+; CHECK-LABEL: @cttz(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: ret i32 3
 }
@@ -174,7 +174,7 @@ entry:
   %and = and i8 %or, 63
   %count = tail call i8 @llvm.ctlz.i8(i8 %and, i1 true) nounwind readnone
   ret i8 %count
-; CHECK: @ctlz
+; CHECK-LABEL: @ctlz(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: ret i8 2
 }
@@ -206,7 +206,7 @@ define i32 @cttz_simplify1a(i32 %x) nounwind readnone ssp {
   %shr3 = lshr i32 %tmp1, 5
   ret i32 %shr3
 
-; CHECK: @cttz_simplify1a
+; CHECK-LABEL: @cttz_simplify1a(
 ; CHECK: icmp eq i32 %x, 0
 ; CHECK-NEXT: zext i1
 ; CHECK-NEXT: ret i32
@@ -217,7 +217,7 @@ define i32 @cttz_simplify1b(i32 %x) nounwind readnone ssp {
   %shr3 = lshr i32 %tmp1, 5
   ret i32 %shr3
 
-; CHECK: @cttz_simplify1b
+; CHECK-LABEL: @cttz_simplify1b(
 ; CHECK-NEXT: ret i32 0
 }
 
@@ -225,7 +225,7 @@ define i32 @ctlz_undef(i32 %Value) nounwind {
   %ctlz = call i32 @llvm.ctlz.i32(i32 0, i1 true)
   ret i32 %ctlz
 
-; CHECK: @ctlz_undef
+; CHECK-LABEL: @ctlz_undef(
 ; CHECK-NEXT: ret i32 undef
 }
 
@@ -233,7 +233,7 @@ define i32 @cttz_undef(i32 %Value) nounwind {
   %cttz = call i32 @llvm.cttz.i32(i32 0, i1 true)
   ret i32 %cttz
 
-; CHECK: @cttz_undef
+; CHECK-LABEL: @cttz_undef(
 ; CHECK-NEXT: ret i32 undef
 }
 
@@ -243,7 +243,7 @@ define i32 @ctlz_select(i32 %Value) nounwind {
   %s = select i1 %tobool, i32 %ctlz, i32 32
   ret i32 %s
 
-; CHECK: @ctlz_select
+; CHECK-LABEL: @ctlz_select(
 ; CHECK: select i1 %tobool, i32 %ctlz, i32 32
 }
 
@@ -253,6 +253,6 @@ define i32 @cttz_select(i32 %Value) nounwind {
   %s = select i1 %tobool, i32 %cttz, i32 32
   ret i32 %s
 
-; CHECK: @cttz_select
+; CHECK-LABEL: @cttz_select(
 ; CHECK: select i1 %tobool, i32 %cttz, i32 32
 }
diff --git a/test/Transforms/InstCombine/invoke.ll b/test/Transforms/InstCombine/invoke.ll
index 04eaf86..c4b58de 100644
--- a/test/Transforms/InstCombine/invoke.ll
+++ b/test/Transforms/InstCombine/invoke.ll
@@ -7,7 +7,7 @@ declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readonly
 declare i8* @_Znwm(i64)
 
 
-; CHECK: @f1
+; CHECK-LABEL: @f1(
 define i64 @f1() nounwind uwtable ssp {
 entry:
 ; CHECK: nvoke noalias i8* undef()
@@ -27,7 +27,7 @@ lpad:
   unreachable
 }
 
-; CHECK: @f2
+; CHECK-LABEL: @f2(
 define i64 @f2() nounwind uwtable ssp {
 entry:
 ; CHECK: nvoke noalias i8* null()
@@ -47,7 +47,7 @@ lpad:
   unreachable
 }
 
-; CHECK: @f3
+; CHECK-LABEL: @f3(
 define void @f3() nounwind uwtable ssp {
 ; CHECK: invoke void @llvm.donothing()
   %call = invoke noalias i8* @_Znwm(i64 13)
diff --git a/test/Transforms/InstCombine/isascii-1.ll b/test/Transforms/InstCombine/isascii-1.ll
index 2a413d8..88f5ad6 100644
--- a/test/Transforms/InstCombine/isascii-1.ll
+++ b/test/Transforms/InstCombine/isascii-1.ll
@@ -9,21 +9,21 @@ declare i32 @isascii(i32)
 ; Check isascii(c) -> c <u 128.
 
 define i32 @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %ret = call i32 @isascii(i32 127)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 1
 }
 
 define i32 @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %ret = call i32 @isascii(i32 128)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 0
 }
 
 define i32 @test_simplify3(i32 %x) {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %ret = call i32 @isascii(i32 %x)
 ; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ult i32 %x, 128
 ; CHECK-NEXT: [[ZEXT:%[a-z0-9]+]] = zext i1 [[CMP]] to i32
diff --git a/test/Transforms/InstCombine/isdigit-1.ll b/test/Transforms/InstCombine/isdigit-1.ll
index f291296..6791307 100644
--- a/test/Transforms/InstCombine/isdigit-1.ll
+++ b/test/Transforms/InstCombine/isdigit-1.ll
@@ -9,35 +9,35 @@ declare i32 @isdigit(i32)
 ; Check isdigit(c) -> (c - '0') <u 10;
 
 define i32 @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %ret = call i32 @isdigit(i32 47)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 0
 }
 
 define i32 @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %ret = call i32 @isdigit(i32 48)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 1
 }
 
 define i32 @test_simplify3() {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %ret = call i32 @isdigit(i32 57)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 1
 }
 
 define i32 @test_simplify4() {
-; CHECK: @test_simplify4
+; CHECK-LABEL: @test_simplify4(
   %ret = call i32 @isdigit(i32 58)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 0
 }
 
 define i32 @test_simplify5(i32 %x) {
-; CHECK: @test_simplify5
+; CHECK-LABEL: @test_simplify5(
 
   %ret = call i32 @isdigit(i32 %x)
 ; CHECK-NEXT: [[ADD:%[a-z0-9]+]] = add i32 %x, -48
diff --git a/test/Transforms/InstCombine/load-cmp.ll b/test/Transforms/InstCombine/load-cmp.ll
index 869215c..95dc48c 100644
--- a/test/Transforms/InstCombine/load-cmp.ll
+++ b/test/Transforms/InstCombine/load-cmp.ll
@@ -10,7 +10,7 @@ define i1 @test1(i32 %X) {
   %Q = load i16* %P
   %R = icmp eq i16 %Q, 0
   ret i1 %R
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: %R = icmp eq i32 %X, 9
 ; CHECK-NEXT: ret i1 %R
 }
@@ -20,7 +20,7 @@ define i1 @test2(i32 %X) {
   %Q = load i16* %P
   %R = icmp slt i16 %Q, 85
   ret i1 %R
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: %R = icmp ne i32 %X, 4
 ; CHECK-NEXT: ret i1 %R
 }
@@ -30,7 +30,7 @@ define i1 @test3(i32 %X) {
   %Q = load double* %P
   %R = fcmp oeq double %Q, 1.0
   ret i1 %R
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: %R = icmp eq i32 %X, 1
 ; CHECK-NEXT: ret i1 %R
 }
@@ -40,7 +40,7 @@ define i1 @test4(i32 %X) {
   %Q = load i16* %P
   %R = icmp sle i16 %Q, 73
   ret i1 %R
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: lshr i32 933, %X
 ; CHECK-NEXT: and i32 {{.*}}, 1
 ; CHECK-NEXT: %R = icmp ne i32 {{.*}}, 0
@@ -52,7 +52,7 @@ define i1 @test4_i16(i16 %X) {
   %Q = load i16* %P
   %R = icmp sle i16 %Q, 73
   ret i1 %R
-; CHECK: @test4_i16
+; CHECK-LABEL: @test4_i16(
 ; CHECK-NEXT: lshr i16 933, %X
 ; CHECK-NEXT: and i16 {{.*}}, 1
 ; CHECK-NEXT: %R = icmp ne i16 {{.*}}, 0
@@ -64,7 +64,7 @@ define i1 @test5(i32 %X) {
   %Q = load i16* %P
   %R = icmp eq i16 %Q, 69
   ret i1 %R
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NEXT: icmp eq i32 %X, 2
 ; CHECK-NEXT: icmp eq i32 %X, 7
 ; CHECK-NEXT: %R = or i1
@@ -76,7 +76,7 @@ define i1 @test6(i32 %X) {
   %Q = load double* %P
   %R = fcmp ogt double %Q, 0.0
   ret i1 %R
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: add i32 %X, -1
 ; CHECK-NEXT: %R = icmp ult i32 {{.*}}, 3
 ; CHECK-NEXT: ret i1 %R
@@ -87,7 +87,7 @@ define i1 @test7(i32 %X) {
   %Q = load double* %P
   %R = fcmp olt double %Q, 0.0
   ret i1 %R
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NEXT: add i32 %X, -1
 ; CHECK-NEXT: %R = icmp ugt i32 {{.*}}, 2
 ; CHECK-NEXT: ret i1 %R
@@ -99,7 +99,7 @@ define i1 @test8(i32 %X) {
   %R = and i16 %Q, 3
   %S = icmp eq i16 %R, 0
   ret i1 %S
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK-NEXT: and i32 %X, -2
 ; CHECK-NEXT: icmp eq i32 {{.*}}, 8
 ; CHECK-NEXT: ret i1
@@ -117,7 +117,7 @@ define i1 @test9(i32 %X) {
   %Q = load i32* %P
   %R = icmp eq i32 %Q, 1
   ret i1 %R
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NEXT: add i32 %X, -1
 ; CHECK-NEXT: icmp ult i32 {{.*}}, 2
 ; CHECK-NEXT: ret i1
diff --git a/test/Transforms/InstCombine/load-select.ll b/test/Transforms/InstCombine/load-select.ll
index f3d83dc..e8cbad3 100644
--- a/test/Transforms/InstCombine/load-select.ll
+++ b/test/Transforms/InstCombine/load-select.ll
@@ -5,7 +5,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-
 @a = constant [2 x i32] [i32 3, i32 6]            ; <[2 x i32]*> [#uses=2]
 
 define i32 @b(i32 %y) nounwind readonly {
-; CHECK: @b
+; CHECK-LABEL: @b(
 ; CHECK-NOT: load
 ; CHECK: ret i32
 entry:
diff --git a/test/Transforms/InstCombine/load3.ll b/test/Transforms/InstCombine/load3.ll
index db74426..f79ef9a 100644
--- a/test/Transforms/InstCombine/load3.ll
+++ b/test/Transforms/InstCombine/load3.ll
@@ -11,7 +11,7 @@ define i32 @test1(i32* %p) {
   %x = load i32* %t1
   %a = sub i32 %y, %x
   ret i32 %a
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret i32 0
 }
 
@@ -22,7 +22,7 @@ define float @test2() {
   %tmp = load float* bitcast ([4 x i8]* @.str to float*), align 1
   ret float %tmp
   
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: ret float 0x3806965600000000
 }
 
@@ -41,6 +41,6 @@ define void @test3() nounwind {
   store i32 %l, i32* getelementptr ([36 x i32]* @rslts32, i32 29826161, i32 28), align 4
   ret void
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: store i32 1, i32* getelementptr inbounds ([36 x i32]* @rslts32, i32 0, i32 0)
 }
diff --git a/test/Transforms/InstCombine/malloc-free-delete.ll b/test/Transforms/InstCombine/malloc-free-delete.ll
index cd12b29..2085206 100644
--- a/test/Transforms/InstCombine/malloc-free-delete.ll
+++ b/test/Transforms/InstCombine/malloc-free-delete.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 ; PR1201
 define i32 @main(i32 %argc, i8** %argv) {
-; CHECK: @main
+; CHECK-LABEL: @main(
     %c_19 = alloca i8*
     %malloc_206 = tail call i8* @malloc(i32 mul (i32 ptrtoint (i8* getelementptr (i8* null, i32 1) to i32), i32 10))
     store i8* %malloc_206, i8** %c_19
@@ -16,7 +16,7 @@ declare noalias i8* @malloc(i32)
 declare void @free(i8*)
 
 define i1 @foo() {
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK-NEXT: ret i1 false
   %m = call i8* @malloc(i32 1)
   %z = icmp eq i8* %m, null
@@ -32,7 +32,7 @@ declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32,
 declare void @llvm.memset.p0i8.i32(i8*, i8, i32, i32, i1) nounwind
 
 define void @test3(i8* %src) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: ret void
   %a = call noalias i8* @malloc(i32 10)
   call void @llvm.lifetime.start(i64 10, i8* %a)
@@ -49,7 +49,7 @@ define void @test3(i8* %src) {
 
 ;; This used to crash.
 define void @test4() {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: ret void
   %A = call i8* @malloc(i32 16000)
   %B = bitcast i8* %A to double*
@@ -58,7 +58,7 @@ define void @test4() {
   ret void
 }
 
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 define void @test5(i8* %ptr, i8** %esc) {
 ; CHECK-NEXT: call i8* @malloc
 ; CHECK-NEXT: call i8* @malloc
@@ -98,7 +98,7 @@ define void @test5(i8* %ptr, i8** %esc) {
 ;; Using simplifycfg will remove the empty basic block and the branch operation
 ;; Then, performing a dead elimination will remove the comparison.
 ;; This is what happens with -O1 and upper.
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 define void @test6(i8* %foo) minsize {
 ; CHECK:  %tobool = icmp eq i8* %foo, null
 ;; Call to free moved
@@ -120,3 +120,27 @@ if.then:                                          ; preds = %entry
 if.end:                                           ; preds = %entry, %if.then
   ret void
 }
+
+declare i8* @_ZnwmRKSt9nothrow_t(i64, i8*) nobuiltin
+declare void @_ZdlPvRKSt9nothrow_t(i8*, i8*) nobuiltin
+declare i32 @__gxx_personality_v0(...)
+declare void @_ZN1AC2Ev(i8* %this)
+
+; CHECK-LABEL: @test7(
+define void @test7() {
+entry:
+  %nt = alloca i8
+  ; CHECK-NOT: call {{.*}}@_ZnwmRKSt9nothrow_t(
+  %call.i = tail call i8* @_ZnwmRKSt9nothrow_t(i64 1, i8* %nt) builtin nounwind
+  invoke void @_ZN1AC2Ev(i8* undef)
+          to label %.noexc.i unwind label %lpad.i
+
+.noexc.i:                                         ; preds = %entry
+  unreachable
+
+lpad.i:                                           ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) cleanup
+  ; CHECK-NOT: call {{.*}}@_ZdlPvRKSt9nothrow_t(
+  call void @_ZdlPvRKSt9nothrow_t(i8* %call.i, i8* %nt) builtin nounwind
+  resume { i8*, i32 } %0
+}
diff --git a/test/Transforms/InstCombine/memcmp-1.ll b/test/Transforms/InstCombine/memcmp-1.ll
index c97b201..65349c6 100644
--- a/test/Transforms/InstCombine/memcmp-1.ll
+++ b/test/Transforms/InstCombine/memcmp-1.ll
@@ -13,7 +13,7 @@ declare i32 @memcmp(i8*, i8*, i32)
 ; Check memcmp(mem, mem, size) -> 0.
 
 define i32 @test_simplify1(i8* %mem, i32 %size) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %ret = call i32 @memcmp(i8* %mem, i8* %mem, i32 %size)
   ret i32 %ret
 ; CHECK: ret i32 0
@@ -22,7 +22,7 @@ define i32 @test_simplify1(i8* %mem, i32 %size) {
 ; Check memcmp(mem1, mem2, 0) -> 0.
 
 define i32 @test_simplify2(i8* %mem1, i8* %mem2) {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %ret = call i32 @memcmp(i8* %mem1, i8* %mem2, i32 0)
   ret i32 %ret
 ; CHECK: ret i32 0
@@ -31,7 +31,7 @@ define i32 @test_simplify2(i8* %mem1, i8* %mem2) {
 ;; Check memcmp(mem1, mem2, 1) -> *(unsigned char*)mem1 - *(unsigned char*)mem2.
 
 define i32 @test_simplify3(i8* %mem1, i8* %mem2) {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %ret = call i32 @memcmp(i8* %mem1, i8* %mem2, i32 1)
 ; CHECK: [[LOAD1:%[a-z]+]] = load i8* %mem1, align 1
 ; CHECK: [[ZEXT1:%[a-z]+]] = zext i8 [[LOAD1]] to i32
@@ -45,7 +45,7 @@ define i32 @test_simplify3(i8* %mem1, i8* %mem2) {
 ; Check memcmp(mem1, mem2, size) -> cnst, where all arguments are constants.
 
 define i32 @test_simplify4() {
-; CHECK: @test_simplify4
+; CHECK-LABEL: @test_simplify4(
   %mem1 = getelementptr [4 x i8]* @hel, i32 0, i32 0
   %mem2 = getelementptr [8 x i8]* @hello_u, i32 0, i32 0
   %ret = call i32 @memcmp(i8* %mem1, i8* %mem2, i32 3)
@@ -54,7 +54,7 @@ define i32 @test_simplify4() {
 }
 
 define i32 @test_simplify5() {
-; CHECK: @test_simplify5
+; CHECK-LABEL: @test_simplify5(
   %mem1 = getelementptr [4 x i8]* @hel, i32 0, i32 0
   %mem2 = getelementptr [4 x i8]* @foo, i32 0, i32 0
   %ret = call i32 @memcmp(i8* %mem1, i8* %mem2, i32 3)
@@ -63,7 +63,7 @@ define i32 @test_simplify5() {
 }
 
 define i32 @test_simplify6() {
-; CHECK: @test_simplify6
+; CHECK-LABEL: @test_simplify6(
   %mem1 = getelementptr [4 x i8]* @foo, i32 0, i32 0
   %mem2 = getelementptr [4 x i8]* @hel, i32 0, i32 0
   %ret = call i32 @memcmp(i8* %mem1, i8* %mem2, i32 3)
diff --git a/test/Transforms/InstCombine/memcmp-2.ll b/test/Transforms/InstCombine/memcmp-2.ll
index 3796117..bed62eb 100644
--- a/test/Transforms/InstCombine/memcmp-2.ll
+++ b/test/Transforms/InstCombine/memcmp-2.ll
@@ -9,7 +9,7 @@ declare i32* @memcmp(i8*, i8*, i32)
 ; Check that memcmp functions with the wrong prototype aren't simplified.
 
 define i32* @test_no_simplify1(i8* %mem, i32 %size) {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %ret = call i32* @memcmp(i8* %mem, i8* %mem, i32 %size)
 ; CHECK-NEXT: call i32* @memcmp
   ret i32* %ret
diff --git a/test/Transforms/InstCombine/memcpy-1.ll b/test/Transforms/InstCombine/memcpy-1.ll
index 65b79ad..9efbcc8 100644
--- a/test/Transforms/InstCombine/memcpy-1.ll
+++ b/test/Transforms/InstCombine/memcpy-1.ll
@@ -9,7 +9,7 @@ declare i8* @memcpy(i8*, i8*, i32)
 ; Check memcpy(mem1, mem2, size) -> llvm.memcpy(mem1, mem2, size, 1).
 
 define i8* @test_simplify1(i8* %mem1, i8* %mem2, i32 %size) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %ret = call i8* @memcpy(i8* %mem1, i8* %mem2, i32 %size)
 ; CHECK: call void @llvm.memcpy
   ret i8* %ret
diff --git a/test/Transforms/InstCombine/memcpy-2.ll b/test/Transforms/InstCombine/memcpy-2.ll
index 4a8a020..a31854c 100644
--- a/test/Transforms/InstCombine/memcpy-2.ll
+++ b/test/Transforms/InstCombine/memcpy-2.ll
@@ -9,7 +9,7 @@ declare i8 @memcpy(i8*, i8*, i32)
 ; Check that memcpy functions with the wrong prototype aren't simplified.
 
 define i8 @test_no_simplify1(i8* %mem1, i8* %mem2, i32 %size) {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %ret = call i8 @memcpy(i8* %mem1, i8* %mem2, i32 %size)
 ; CHECK: call i8 @memcpy
   ret i8 %ret
diff --git a/test/Transforms/InstCombine/memcpy-from-global.ll b/test/Transforms/InstCombine/memcpy-from-global.ll
index 557b160..58793ab 100644
--- a/test/Transforms/InstCombine/memcpy-from-global.ll
+++ b/test/Transforms/InstCombine/memcpy-from-global.ll
@@ -8,7 +8,7 @@ entry:
 	%lookupTable1 = bitcast [128 x float]* %lookupTable to i8*		; <i8*> [#uses=1]
 	call void @llvm.memcpy.p0i8.p0i8.i64(i8* %lookupTable1, i8* bitcast ([128 x float]* @C.0.1248 to i8*), i64 512, i32 16, i1 false)
         
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NOT: alloca
 ; CHECK-NOT: call{{.*}}@llvm.memcpy
         
@@ -50,7 +50,7 @@ define void @test2() {
   %a = bitcast %T* %A to i8*
   %b = bitcast %T* %B to i8*
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 
 ; %A alloca is deleted
 ; CHECK-NEXT: alloca [124 x i8]
@@ -73,7 +73,7 @@ define void @test3() {
   %a = bitcast %T* %A to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%T* @G to i8*), i64 124, i32 4, i1 false)
   call void @bar(i8* %a) readonly
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: call void @bar(i8* getelementptr inbounds (%T* @G, i64 0, i32 0))
   ret void
 }
@@ -83,7 +83,7 @@ define void @test4() {
   %a = bitcast %T* %A to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%T* @G to i8*), i64 124, i32 4, i1 false)
   call void @baz(i8* byval %a) 
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: call void @baz(i8* byval getelementptr inbounds (%T* @G, i64 0, i32 0))
   ret void
 }
@@ -95,7 +95,7 @@ define void @test5() {
   call void @llvm.lifetime.start(i64 -1, i8* %a)
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%T* @G to i8*), i64 124, i32 4, i1 false)
   call void @baz(i8* byval %a) 
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NEXT: call void @baz(i8* byval getelementptr inbounds (%T* @G, i64 0, i32 0))
   ret void
 }
@@ -109,7 +109,7 @@ define void @test6() {
   %a = bitcast %U* %A to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast ([2 x %U]* @H to i8*), i64 20, i32 16, i1 false)
   call void @bar(i8* %a) readonly
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: call void @bar(i8* bitcast ([2 x %U]* @H to i8*))
   ret void
 }
@@ -119,7 +119,7 @@ define void @test7() {
   %a = bitcast %U* %A to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%U* getelementptr ([2 x %U]* @H, i64 0, i32 0) to i8*), i64 20, i32 4, i1 false)
   call void @bar(i8* %a) readonly
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NEXT: call void @bar(i8* bitcast ([2 x %U]* @H to i8*))
   ret void
 }
@@ -129,7 +129,7 @@ define void @test8() {
   %a = bitcast %U* %A to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%U* getelementptr ([2 x %U]* @H, i64 0, i32 1) to i8*), i64 20, i32 4, i1 false)
   call void @bar(i8* %a) readonly
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: llvm.memcpy
 ; CHECK: bar
   ret void
@@ -140,7 +140,7 @@ define void @test9() {
   %a = bitcast %U* %A to i8*
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%U* getelementptr ([2 x %U]* @H, i64 0, i32 1) to i8*), i64 20, i32 4, i1 false)
   call void @bar(i8* %a) readonly
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NEXT: call void @bar(i8* bitcast (%U* getelementptr inbounds ([2 x %U]* @H, i64 0, i64 1) to i8*))
   ret void
 }
diff --git a/test/Transforms/InstCombine/memcpy.ll b/test/Transforms/InstCombine/memcpy.ll
index 3a68ff9..f66e14c 100644
--- a/test/Transforms/InstCombine/memcpy.ll
+++ b/test/Transforms/InstCombine/memcpy.ll
@@ -6,7 +6,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
 define void @test1(i8* %a) {
         tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a, i8* %a, i32 100, i32 1, i1 false)
         ret void
-; CHECK: define void @test1
+; CHECK-LABEL: define void @test1(
 ; CHECK-NEXT: ret void
 }
 
@@ -15,13 +15,13 @@ define void @test1(i8* %a) {
 define void @test2(i8* %a) {
         tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a, i8* %a, i32 100, i32 1, i1 true)
         ret void
-; CHECK: define void @test2
+; CHECK-LABEL: define void @test2(
 ; CHECK-NEXT: call void @llvm.memcpy
 }
 
 define void @test3(i8* %d, i8* %s) {
         tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %d, i8* %s, i64 17179869184, i32 4, i1 false)
         ret void
-; CHECK: define void @test3
+; CHECK-LABEL: define void @test3(
 ; CHECK-NEXT: call void @llvm.memcpy
 }
diff --git a/test/Transforms/InstCombine/memcpy_chk-1.ll b/test/Transforms/InstCombine/memcpy_chk-1.ll
index 7c7d918..9216ae7 100644
--- a/test/Transforms/InstCombine/memcpy_chk-1.ll
+++ b/test/Transforms/InstCombine/memcpy_chk-1.ll
@@ -16,7 +16,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; Check cases where dstlen >= len.
 
 define void @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %dst = bitcast %struct.T1* @t1 to i8*
   %src = bitcast %struct.T2* @t2 to i8*
 
@@ -26,7 +26,7 @@ define void @test_simplify1() {
 }
 
 define void @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %dst = bitcast %struct.T1* @t1 to i8*
   %src = bitcast %struct.T3* @t3 to i8*
 
@@ -38,7 +38,7 @@ define void @test_simplify2() {
 ; Check cases where dstlen < len.
 
 define void @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %dst = bitcast %struct.T3* @t3 to i8*
   %src = bitcast %struct.T1* @t1 to i8*
 
@@ -48,7 +48,7 @@ define void @test_no_simplify1() {
 }
 
 define void @test_no_simplify2() {
-; CHECK: @test_no_simplify2
+; CHECK-LABEL: @test_no_simplify2(
   %dst = bitcast %struct.T1* @t1 to i8*
   %src = bitcast %struct.T2* @t2 to i8*
 
diff --git a/test/Transforms/InstCombine/memcpy_chk-2.ll b/test/Transforms/InstCombine/memcpy_chk-2.ll
index aa43029..320b54f 100644
--- a/test/Transforms/InstCombine/memcpy_chk-2.ll
+++ b/test/Transforms/InstCombine/memcpy_chk-2.ll
@@ -12,7 +12,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 @t2 = common global %struct.T2 zeroinitializer
 
 define void @test_no_simplify() {
-; CHECK: @test_no_simplify
+; CHECK-LABEL: @test_no_simplify(
   %dst = bitcast %struct.T1* @t1 to i8*
   %src = bitcast %struct.T2* @t2 to i8*
 
diff --git a/test/Transforms/InstCombine/memmove-1.ll b/test/Transforms/InstCombine/memmove-1.ll
index 53f2f11..0445a60 100644
--- a/test/Transforms/InstCombine/memmove-1.ll
+++ b/test/Transforms/InstCombine/memmove-1.ll
@@ -9,7 +9,7 @@ declare i8* @memmove(i8*, i8*, i32)
 ; Check memmove(mem1, mem2, size) -> llvm.memmove(mem1, mem2, size, 1).
 
 define i8* @test_simplify1(i8* %mem1, i8* %mem2, i32 %size) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %ret = call i8* @memmove(i8* %mem1, i8* %mem2, i32 %size)
 ; CHECK: call void @llvm.memmove
   ret i8* %ret
diff --git a/test/Transforms/InstCombine/memmove-2.ll b/test/Transforms/InstCombine/memmove-2.ll
index 23887bc..b20e96b 100644
--- a/test/Transforms/InstCombine/memmove-2.ll
+++ b/test/Transforms/InstCombine/memmove-2.ll
@@ -9,7 +9,7 @@ declare i8 @memmove(i8*, i8*, i32)
 ; Check that memmove functions with the wrong prototype aren't simplified.
 
 define i8 @test_no_simplify1(i8* %mem1, i8* %mem2, i32 %size) {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %ret = call i8 @memmove(i8* %mem1, i8* %mem2, i32 %size)
 ; CHECK: call i8 @memmove
   ret i8 %ret
diff --git a/test/Transforms/InstCombine/memmove_chk-1.ll b/test/Transforms/InstCombine/memmove_chk-1.ll
index f9ff9a1..6d93bbb 100644
--- a/test/Transforms/InstCombine/memmove_chk-1.ll
+++ b/test/Transforms/InstCombine/memmove_chk-1.ll
@@ -16,7 +16,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; Check cases where dstlen >= len.
 
 define void @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %dst = bitcast %struct.T1* @t1 to i8*
   %src = bitcast %struct.T2* @t2 to i8*
 
@@ -26,7 +26,7 @@ define void @test_simplify1() {
 }
 
 define void @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %dst = bitcast %struct.T1* @t1 to i8*
   %src = bitcast %struct.T3* @t3 to i8*
 
@@ -38,7 +38,7 @@ define void @test_simplify2() {
 ; Check cases where dstlen < len.
 
 define void @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %dst = bitcast %struct.T3* @t3 to i8*
   %src = bitcast %struct.T1* @t1 to i8*
 
@@ -48,7 +48,7 @@ define void @test_no_simplify1() {
 }
 
 define void @test_no_simplify2() {
-; CHECK: @test_no_simplify2
+; CHECK-LABEL: @test_no_simplify2(
   %dst = bitcast %struct.T1* @t1 to i8*
   %src = bitcast %struct.T2* @t2 to i8*
 
diff --git a/test/Transforms/InstCombine/memmove_chk-2.ll b/test/Transforms/InstCombine/memmove_chk-2.ll
index f0a915f..adadf90 100644
--- a/test/Transforms/InstCombine/memmove_chk-2.ll
+++ b/test/Transforms/InstCombine/memmove_chk-2.ll
@@ -12,7 +12,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 @t2 = common global %struct.T2 zeroinitializer
 
 define void @test_no_simplify() {
-; CHECK: @test_no_simplify
+; CHECK-LABEL: @test_no_simplify(
   %dst = bitcast %struct.T1* @t1 to i8*
   %src = bitcast %struct.T2* @t2 to i8*
 
diff --git a/test/Transforms/InstCombine/memset-1.ll b/test/Transforms/InstCombine/memset-1.ll
index 48b433e..991567d 100644
--- a/test/Transforms/InstCombine/memset-1.ll
+++ b/test/Transforms/InstCombine/memset-1.ll
@@ -9,7 +9,7 @@ declare i8* @memset(i8*, i32, i32)
 ; Check memset(mem1, val, size) -> llvm.memset(mem1, val, size, 1).
 
 define i8* @test_simplify1(i8* %mem, i32 %val, i32 %size) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %ret = call i8* @memset(i8* %mem, i32 %val, i32 %size)
 ; CHECK: call void @llvm.memset
   ret i8* %ret
diff --git a/test/Transforms/InstCombine/memset-2.ll b/test/Transforms/InstCombine/memset-2.ll
index 8a90333..5e446cb 100644
--- a/test/Transforms/InstCombine/memset-2.ll
+++ b/test/Transforms/InstCombine/memset-2.ll
@@ -9,7 +9,7 @@ declare i8 @memset(i8*, i32, i32)
 ; Check that memset functions with the wrong prototype aren't simplified.
 
 define i8 @test_no_simplify1(i8* %mem, i32 %val, i32 %size) {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %ret = call i8 @memset(i8* %mem, i32 %val, i32 %size)
 ; CHECK: call i8 @memset
   ret i8 %ret
diff --git a/test/Transforms/InstCombine/memset_chk-1.ll b/test/Transforms/InstCombine/memset_chk-1.ll
index be4c1cf..47cc7db 100644
--- a/test/Transforms/InstCombine/memset_chk-1.ll
+++ b/test/Transforms/InstCombine/memset_chk-1.ll
@@ -12,7 +12,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; Check cases where dstlen >= len.
 
 define void @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %dst = bitcast %struct.T* @t to i8*
 
 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64
@@ -21,7 +21,7 @@ define void @test_simplify1() {
 }
 
 define void @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %dst = bitcast %struct.T* @t to i8*
 
 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64
@@ -30,7 +30,7 @@ define void @test_simplify2() {
 }
 
 define void @test_simplify3() {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %dst = bitcast %struct.T* @t to i8*
 
 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64
@@ -41,7 +41,7 @@ define void @test_simplify3() {
 ; Check cases where dstlen < len.
 
 define void @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %dst = bitcast %struct.T* @t to i8*
 
 ; CHECK-NEXT: call i8* @__memset_chk
@@ -50,7 +50,7 @@ define void @test_no_simplify1() {
 }
 
 define void @test_no_simplify2() {
-; CHECK: @test_no_simplify2
+; CHECK-LABEL: @test_no_simplify2(
   %dst = bitcast %struct.T* @t to i8*
 
 ; CHECK-NEXT: call i8* @__memset_chk
diff --git a/test/Transforms/InstCombine/memset_chk-2.ll b/test/Transforms/InstCombine/memset_chk-2.ll
index 60fbf16..bb4f772 100644
--- a/test/Transforms/InstCombine/memset_chk-2.ll
+++ b/test/Transforms/InstCombine/memset_chk-2.ll
@@ -9,7 +9,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 @t = common global %struct.T zeroinitializer
 
 define void @test_no_simplify() {
-; CHECK: @test_no_simplify
+; CHECK-LABEL: @test_no_simplify(
   %dst = bitcast %struct.T* @t to i8*
 
 ; CHECK-NEXT: call i8* @__memset_chk
diff --git a/test/Transforms/InstCombine/merge-icmp.ll b/test/Transforms/InstCombine/merge-icmp.ll
index 00020b1..b021fe04 100644
--- a/test/Transforms/InstCombine/merge-icmp.ll
+++ b/test/Transforms/InstCombine/merge-icmp.ll
@@ -8,7 +8,7 @@ define i1 @test1(i16* %x) {
   %cmp2 = icmp eq i16 %and, 17664
   %or = and i1 %cmp1, %cmp2
   ret i1 %or
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: load i16
 ; CHECK-NEXT: icmp eq i16 %load, 17791
 ; CHECK-NEXT: ret i1
@@ -22,7 +22,7 @@ define i1 @test2(i16* %x) {
   %cmp2 = icmp eq i8 %trunc, 69
   %or = and i1 %cmp1, %cmp2
   ret i1 %or
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: load i16
 ; CHECK-NEXT: icmp eq i16 %load, 32581
 ; CHECK-NEXT: ret i1
diff --git a/test/Transforms/InstCombine/mul.ll b/test/Transforms/InstCombine/mul.ll
index 16213b8..94fc118 100644
--- a/test/Transforms/InstCombine/mul.ll
+++ b/test/Transforms/InstCombine/mul.ll
@@ -2,14 +2,14 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i32 @test1(i32 %A) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
         %B = mul i32 %A, 1              ; <i32> [#uses=1]
         ret i32 %B
 ; CHECK: ret i32 %A
 }
 
 define i32 @test2(i32 %A) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
         ; Should convert to an add instruction
         %B = mul i32 %A, 2              ; <i32> [#uses=1]
         ret i32 %B
@@ -17,7 +17,7 @@ define i32 @test2(i32 %A) {
 }
 
 define i32 @test3(i32 %A) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
         ; This should disappear entirely
         %B = mul i32 %A, 0              ; <i32> [#uses=1]
         ret i32 %B
@@ -25,7 +25,7 @@ define i32 @test3(i32 %A) {
 }
 
 define double @test4(double %A) {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
         ; This is safe for FP
         %B = fmul double 1.000000e+00, %A                ; <double> [#uses=1]
         ret double %B
@@ -33,14 +33,14 @@ define double @test4(double %A) {
 }
 
 define i32 @test5(i32 %A) {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
         %B = mul i32 %A, 8              ; <i32> [#uses=1]
         ret i32 %B
 ; CHECK: shl i32 %A, 3
 }
 
 define i8 @test6(i8 %A) {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
         %B = mul i8 %A, 8               ; <i8> [#uses=1]
         %C = mul i8 %B, 8               ; <i8> [#uses=1]
         ret i8 %C
@@ -48,28 +48,28 @@ define i8 @test6(i8 %A) {
 }
 
 define i32 @test7(i32 %i) {
-; CHECK: @test7
+; CHECK-LABEL: @test7(
         %tmp = mul i32 %i, -1           ; <i32> [#uses=1]
         ret i32 %tmp
 ; CHECK: sub i32 0, %i
 }
 
 define i64 @test8(i64 %i) {
-; CHECK: @test8
+; CHECK-LABEL: @test8(
         %j = mul i64 %i, -1             ; <i64> [#uses=1]
         ret i64 %j
 ; CHECK: sub i64 0, %i
 }
 
 define i32 @test9(i32 %i) {
-; CHECK: @test9
+; CHECK-LABEL: @test9(
         %j = mul i32 %i, -1             ; <i32> [#uses=1]
         ret i32 %j
 ; CHECK: sub i32 0, %i
 }
 
 define i32 @test10(i32 %a, i32 %b) {
-; CHECK: @test10
+; CHECK-LABEL: @test10(
         %c = icmp slt i32 %a, 0         ; <i1> [#uses=1]
         %d = zext i1 %c to i32          ; <i32> [#uses=1]
        ; e = b & (a >> 31)
@@ -81,7 +81,7 @@ define i32 @test10(i32 %a, i32 %b) {
 }
 
 define i32 @test11(i32 %a, i32 %b) {
-; CHECK: @test11
+; CHECK-LABEL: @test11(
         %c = icmp sle i32 %a, -1                ; <i1> [#uses=1]
         %d = zext i1 %c to i32          ; <i32> [#uses=1]
         ; e = b & (a >> 31)
@@ -93,7 +93,7 @@ define i32 @test11(i32 %a, i32 %b) {
 }
 
 define i32 @test12(i32 %a, i32 %b) {
-; CHECK: @test12
+; CHECK-LABEL: @test12(
         %c = icmp ugt i32 %a, 2147483647                ; <i1> [#uses=1]
         %d = zext i1 %c to i32          ; <i32> [#uses=1]
         %e = mul i32 %d, %b             ; <i32> [#uses=1]
@@ -106,7 +106,7 @@ define i32 @test12(i32 %a, i32 %b) {
 
 ; PR2642
 define internal void @test13(<4 x float>*) {
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 	load <4 x float>* %0, align 1
 	fmul <4 x float> %2, < float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 >
 	store <4 x float> %3, <4 x float>* %0, align 1
@@ -115,7 +115,7 @@ define internal void @test13(<4 x float>*) {
 }
 
 define <16 x i8> @test14(<16 x i8> %a) {
-; CHECK: @test14
+; CHECK-LABEL: @test14(
         %b = mul <16 x i8> %a, zeroinitializer
         ret <16 x i8> %b
 ; CHECK-NEXT: ret <16 x i8> zeroinitializer
@@ -123,7 +123,7 @@ define <16 x i8> @test14(<16 x i8> %a) {
 
 ; rdar://7293527
 define i32 @test15(i32 %A, i32 %B) {
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 entry:
   %shl = shl i32 1, %B
   %m = mul i32 %shl, %A
@@ -133,7 +133,7 @@ entry:
 
 ; X * Y (when Y is 0 or 1) --> x & (0-Y)
 define i32 @test16(i32 %b, i1 %c) {
-; CHECK: @test16
+; CHECK-LABEL: @test16(
         %d = zext i1 %c to i32          ; <i32> [#uses=1]
         ; e = b & (a >> 31)
         %e = mul i32 %d, %b             ; <i32> [#uses=1]
@@ -144,7 +144,7 @@ define i32 @test16(i32 %b, i1 %c) {
 
 ; X * Y (when Y is 0 or 1) --> x & (0-Y)
 define i32 @test17(i32 %a, i32 %b) {
-; CHECK: @test17
+; CHECK-LABEL: @test17(
   %a.lobit = lshr i32 %a, 31
   %e = mul i32 %a.lobit, %b
   ret i32 %e
@@ -154,7 +154,7 @@ define i32 @test17(i32 %a, i32 %b) {
 }
 
 define i32 @test18(i32 %A, i32 %B) {
-; CHECK: @test18
+; CHECK-LABEL: @test18(
   %C = and i32 %A, 1
   %D = and i32 %B, 1
 
@@ -168,7 +168,7 @@ declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32)
 declare void @use(i1)
 
 define i32 @test19(i32 %A, i32 %B) {
-; CHECK: @test19
+; CHECK-LABEL: @test19(
   %C = and i32 %A, 1
   %D = and i32 %B, 1
 
diff --git a/test/Transforms/InstCombine/no-negzero.ll b/test/Transforms/InstCombine/no-negzero.ll
index f295130..4ed2836 100644
--- a/test/Transforms/InstCombine/no-negzero.ll
+++ b/test/Transforms/InstCombine/no-negzero.ll
@@ -4,7 +4,7 @@
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin9.8"
 
-; CHECK: @mysqrt
+; CHECK-LABEL: @mysqrt(
 ; CHECK-NOT: fadd
 ; CHECK: ret
 define double @mysqrt(double %x) nounwind {
diff --git a/test/Transforms/InstCombine/nsw.ll b/test/Transforms/InstCombine/nsw.ll
index 0140c2f..0bed767 100644
--- a/test/Transforms/InstCombine/nsw.ll
+++ b/test/Transforms/InstCombine/nsw.ll
@@ -1,6 +1,6 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
-; CHECK: @sub1
+; CHECK-LABEL: @sub1(
 ; CHECK: %y = sub i32 0, %x
 ; CHECK: %z = sdiv i32 %y, 337
 ; CHECK: ret i32 %z
@@ -10,7 +10,7 @@ define i32 @sub1(i32 %x) {
   ret i32 %z
 }
 
-; CHECK: @sub2
+; CHECK-LABEL: @sub2(
 ; CHECK: %z = sdiv i32 %x, -337
 ; CHECK: ret i32 %z
 define i32 @sub2(i32 %x) {
@@ -19,7 +19,7 @@ define i32 @sub2(i32 %x) {
   ret i32 %z
 }
 
-; CHECK: @shl_icmp
+; CHECK-LABEL: @shl_icmp(
 ; CHECK: %B = icmp eq i64 %X, 0
 ; CHECK: ret i1 %B
 define i1 @shl_icmp(i64 %X) nounwind {
@@ -28,7 +28,7 @@ define i1 @shl_icmp(i64 %X) nounwind {
   ret i1 %B
 }
 
-; CHECK: @shl1
+; CHECK-LABEL: @shl1(
 ; CHECK: %B = shl nuw nsw i64 %A, 8
 ; CHECK: ret i64 %B
 define i64 @shl1(i64 %X, i64* %P) nounwind {
@@ -38,7 +38,7 @@ define i64 @shl1(i64 %X, i64* %P) nounwind {
   ret i64 %B
 }
 
-; CHECK: @preserve1
+; CHECK-LABEL: @preserve1(
 ; CHECK: add nsw i32 %x, 5
 define i32 @preserve1(i32 %x) nounwind {
   %add = add nsw i32 %x, 2
@@ -46,7 +46,7 @@ define i32 @preserve1(i32 %x) nounwind {
   ret i32 %add3
 }
 
-; CHECK: @nopreserve1
+; CHECK-LABEL: @nopreserve1(
 ; CHECK: add i8 %x, -126
 define i8 @nopreserve1(i8 %x) nounwind {
   %add = add nsw i8 %x, 127
@@ -54,7 +54,7 @@ define i8 @nopreserve1(i8 %x) nounwind {
   ret i8 %add3
 }
 
-; CHECK: @nopreserve2
+; CHECK-LABEL: @nopreserve2(
 ; CHECK: add i8 %x, 3
 define i8 @nopreserve2(i8 %x) nounwind {
   %add = add i8 %x, 1
@@ -62,7 +62,7 @@ define i8 @nopreserve2(i8 %x) nounwind {
   ret i8 %add3
 }
 
-; CHECK: @nopreserve3
+; CHECK-LABEL: @nopreserve3(
 ; CHECK: add i8 %A, %B
 ; CHECK: add i8
 define i8 @nopreserve3(i8 %A, i8 %B) nounwind {
@@ -72,7 +72,7 @@ define i8 @nopreserve3(i8 %A, i8 %B) nounwind {
   ret i8 %add
 }
 
-; CHECK: @nopreserve4
+; CHECK-LABEL: @nopreserve4(
 ; CHECK: add i8 %A, %B
 ; CHECK: add i8
 define i8 @nopreserve4(i8 %A, i8 %B) nounwind {
diff --git a/test/Transforms/InstCombine/objsize-64.ll b/test/Transforms/InstCombine/objsize-64.ll
index 530e123..5046724 100644
--- a/test/Transforms/InstCombine/objsize-64.ll
+++ b/test/Transforms/InstCombine/objsize-64.ll
@@ -7,7 +7,7 @@ declare i32 @__gxx_personality_v0(...)
 declare void @__cxa_call_unexpected(i8*)
 declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readonly
 
-; CHECK: @f1
+; CHECK-LABEL: @f1(
 define i64 @f1(i8 **%esc) {
   %call = call i8* @malloc(i32 4)
   store i8* %call, i8** %esc
@@ -17,7 +17,7 @@ define i64 @f1(i8 **%esc) {
 }
 
 
-; CHECK: @f2
+; CHECK-LABEL: @f2(
 define i64 @f2(i8** %esc) nounwind uwtable ssp {
 entry:
 ; CHECK: invoke noalias i8* @_Znwm(i64 13)
diff --git a/test/Transforms/InstCombine/objsize.ll b/test/Transforms/InstCombine/objsize.ll
index 122c650..b5351e9 100644
--- a/test/Transforms/InstCombine/objsize.ll
+++ b/test/Transforms/InstCombine/objsize.ll
@@ -7,14 +7,14 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 @.str = private constant [8 x i8] c"abcdefg\00"   ; <[8 x i8]*>
 
 define i32 @foo() nounwind {
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK-NEXT: ret i32 60
   %1 = call i32 @llvm.objectsize.i32(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i1 false)
   ret i32 %1
 }
 
 define i8* @bar() nounwind {
-; CHECK: @bar
+; CHECK-LABEL: @bar(
 entry:
   %retval = alloca i8*
   %0 = call i32 @llvm.objectsize.i32(i8* getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0), i1 false)
@@ -32,7 +32,7 @@ cond.false:
 }
 
 define i32 @f() nounwind {
-; CHECK: @f
+; CHECK-LABEL: @f(
 ; CHECK-NEXT: ret i32 0
   %1 = call i32 @llvm.objectsize.i32(i8* getelementptr ([60 x i8]* @a, i32 1, i32 0), i1 false)
   ret i32 %1
@@ -41,7 +41,7 @@ define i32 @f() nounwind {
 @window = external global [0 x i8]
 
 define i1 @baz() nounwind {
-; CHECK: @baz
+; CHECK-LABEL: @baz(
 ; CHECK-NEXT: objectsize
   %1 = tail call i32 @llvm.objectsize.i32(i8* getelementptr inbounds ([0 x i8]* @window, i32 0, i32 0), i1 false)
   %2 = icmp eq i32 %1, -1
@@ -49,7 +49,7 @@ define i1 @baz() nounwind {
 }
 
 define void @test1(i8* %q, i32 %x) nounwind noinline {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: objectsize.i32
 entry:
   %0 = call i32 @llvm.objectsize.i32(i8* getelementptr inbounds ([0 x i8]* @window, i32 0, i32 10), i1 false) ; <i64> [#uses=1]
@@ -66,7 +66,7 @@ entry:
 @.str5 = private constant [9 x i32] [i32 97, i32 98, i32 99, i32 100, i32 0, i32
  101, i32 102, i32 103, i32 0], align 4
 define i32 @test2() nounwind {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: ret i32 34
   %1 = call i32 @llvm.objectsize.i32(i8* getelementptr (i8* bitcast ([9 x i32]* @.str5 to i8*), i32 2), i1 false)
   ret i32 %1
@@ -82,7 +82,7 @@ declare i32 @llvm.objectsize.i32(i8*, i1) nounwind readonly
 declare i8* @__inline_memcpy_chk(i8*, i8*, i32) nounwind inlinehint
 
 define void @test3() nounwind {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 entry:
   br i1 undef, label %bb11, label %bb12
 
@@ -107,7 +107,7 @@ bb12:
 %struct.data = type { [100 x i32], [100 x i32], [1024 x i8] }
 
 define i32 @test4(i8** %esc) nounwind ssp {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 entry:
   %0 = alloca %struct.data, align 8
   %1 = bitcast %struct.data* %0 to i8*
@@ -123,7 +123,7 @@ entry:
 @s = external global i8*
 
 define i8* @test5(i32 %n) nounwind ssp {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 entry:
   %0 = tail call noalias i8* @malloc(i32 20) nounwind
   %1 = tail call i32 @llvm.objectsize.i32(i8* %0, i1 false)
@@ -135,7 +135,7 @@ entry:
 }
 
 define void @test6(i32 %n) nounwind ssp {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 entry:
   %0 = tail call noalias i8* @malloc(i32 20) nounwind
   %1 = tail call i32 @llvm.objectsize.i32(i8* %0, i1 false)
@@ -151,7 +151,7 @@ declare i8* @__memset_chk(i8*, i32, i32, i32) nounwind
 declare noalias i8* @malloc(i32) nounwind
 
 define i32 @test7(i8** %esc) {
-; CHECK: @test7
+; CHECK-LABEL: @test7(
   %alloc = call noalias i8* @malloc(i32 48) nounwind
   store i8* %alloc, i8** %esc
   %gep = getelementptr inbounds i8* %alloc, i32 16
@@ -163,7 +163,7 @@ define i32 @test7(i8** %esc) {
 declare noalias i8* @calloc(i32, i32) nounwind
 
 define i32 @test8(i8** %esc) {
-; CHECK: @test8
+; CHECK-LABEL: @test8(
   %alloc = call noalias i8* @calloc(i32 5, i32 7) nounwind
   store i8* %alloc, i8** %esc
   %gep = getelementptr inbounds i8* %alloc, i32 5
@@ -175,7 +175,7 @@ define i32 @test8(i8** %esc) {
 declare noalias i8* @strdup(i8* nocapture) nounwind
 declare noalias i8* @strndup(i8* nocapture, i32) nounwind
 
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 define i32 @test9(i8** %esc) {
   %call = tail call i8* @strdup(i8* getelementptr inbounds ([8 x i8]* @.str, i64 0, i64 0)) nounwind
   store i8* %call, i8** %esc, align 8
@@ -184,7 +184,7 @@ define i32 @test9(i8** %esc) {
   ret i32 %1
 }
 
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 define i32 @test10(i8** %esc) {
   %call = tail call i8* @strndup(i8* getelementptr inbounds ([8 x i8]* @.str, i64 0, i64 0), i32 3) nounwind
   store i8* %call, i8** %esc, align 8
@@ -193,7 +193,7 @@ define i32 @test10(i8** %esc) {
   ret i32 %1
 }
 
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 define i32 @test11(i8** %esc) {
   %call = tail call i8* @strndup(i8* getelementptr inbounds ([8 x i8]* @.str, i64 0, i64 0), i32 7) nounwind
   store i8* %call, i8** %esc, align 8
@@ -202,7 +202,7 @@ define i32 @test11(i8** %esc) {
   ret i32 %1
 }
 
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 define i32 @test12(i8** %esc) {
   %call = tail call i8* @strndup(i8* getelementptr inbounds ([8 x i8]* @.str, i64 0, i64 0), i32 8) nounwind
   store i8* %call, i8** %esc, align 8
@@ -211,7 +211,7 @@ define i32 @test12(i8** %esc) {
   ret i32 %1
 }
 
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 define i32 @test13(i8** %esc) {
   %call = tail call i8* @strndup(i8* getelementptr inbounds ([8 x i8]* @.str, i64 0, i64 0), i32 57) nounwind
   store i8* %call, i8** %esc, align 8
@@ -220,7 +220,7 @@ define i32 @test13(i8** %esc) {
   ret i32 %1
 }
 
-; CHECK: @PR13390
+; CHECK-LABEL: @PR13390(
 define i32 @PR13390(i1 %bool, i8* %a) {
 entry:
   %cond = or i1 %bool, true
@@ -239,7 +239,7 @@ return:
   ret i32 42
 }
 
-; CHECK: @PR13621
+; CHECK-LABEL: @PR13621(
 define i32 @PR13621(i1 %bool) nounwind {
 entry:
   %cond = or i1 %bool, true
@@ -259,7 +259,7 @@ return:
 
 @globalalias = alias internal [60 x i8]* @a
 
-; CHECK: @test18
+; CHECK-LABEL: @test18(
 ; CHECK-NEXT: ret i32 60
 define i32 @test18() {
   %bc = bitcast [60 x i8]* @globalalias to i8*
@@ -269,7 +269,7 @@ define i32 @test18() {
 
 @globalalias2 = alias weak [60 x i8]* @a
 
-; CHECK: @test19
+; CHECK-LABEL: @test19(
 ; CHECK: llvm.objectsize
 define i32 @test19() {
   %bc = bitcast [60 x i8]* @globalalias2 to i8*
diff --git a/test/Transforms/InstCombine/or-fcmp.ll b/test/Transforms/InstCombine/or-fcmp.ll
index 09a3c99..29963f6 100644
--- a/test/Transforms/InstCombine/or-fcmp.ll
+++ b/test/Transforms/InstCombine/or-fcmp.ll
@@ -1,6 +1,6 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
-; CHECK: @t1
+; CHECK-LABEL: @t1(
 define zeroext i8 @t1(float %x, float %y) nounwind {
        %a = fcmp ueq float %x, %y             ; <i1> [#uses=1]
        %b = fcmp uno float %x, %y               ; <i1> [#uses=1]
@@ -11,7 +11,7 @@ define zeroext i8 @t1(float %x, float %y) nounwind {
        ret i8 %retval
 }
 
-; CHECK: @t2
+; CHECK-LABEL: @t2(
 define zeroext i8 @t2(float %x, float %y) nounwind {
        %a = fcmp olt float %x, %y             ; <i1> [#uses=1]
        %b = fcmp oeq float %x, %y               ; <i1> [#uses=1]
@@ -23,7 +23,7 @@ define zeroext i8 @t2(float %x, float %y) nounwind {
        ret i8 %retval
 }
 
-; CHECK: @t3
+; CHECK-LABEL: @t3(
 define zeroext i8 @t3(float %x, float %y) nounwind {
        %a = fcmp ult float %x, %y             ; <i1> [#uses=1]
        %b = fcmp uge float %x, %y               ; <i1> [#uses=1]
@@ -33,7 +33,7 @@ define zeroext i8 @t3(float %x, float %y) nounwind {
        ret i8 %retval
 }
 
-; CHECK: @t4
+; CHECK-LABEL: @t4(
 define zeroext i8 @t4(float %x, float %y) nounwind {
        %a = fcmp ult float %x, %y             ; <i1> [#uses=1]
        %b = fcmp ugt float %x, %y               ; <i1> [#uses=1]
@@ -45,7 +45,7 @@ define zeroext i8 @t4(float %x, float %y) nounwind {
        ret i8 %retval
 }
 
-; CHECK: @t5
+; CHECK-LABEL: @t5(
 define zeroext i8 @t5(float %x, float %y) nounwind {
        %a = fcmp olt float %x, %y             ; <i1> [#uses=1]
        %b = fcmp oge float %x, %y               ; <i1> [#uses=1]
diff --git a/test/Transforms/InstCombine/or-xor.ll b/test/Transforms/InstCombine/or-xor.ll
index f496dd4..cec36f1 100644
--- a/test/Transforms/InstCombine/or-xor.ll
+++ b/test/Transforms/InstCombine/or-xor.ll
@@ -5,7 +5,7 @@ define i32 @test1(i32 %x, i32 %y) nounwind {
   %not = xor i32 %or, -1
   %z = or i32 %x, %not
   ret i32 %z
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: %y.not = xor i32 %y, -1
 ; CHECK-NEXT: %z = or i32 %y.not, %x
 ; CHECK-NEXT: ret i32 %z
@@ -16,7 +16,7 @@ define i32 @test2(i32 %x, i32 %y) nounwind {
   %not = xor i32 %or, -1
   %z = or i32 %y, %not
   ret i32 %z
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: %x.not = xor i32 %x, -1
 ; CHECK-NEXT: %z = or i32 %x.not, %y
 ; CHECK-NEXT: ret i32 %z
@@ -27,7 +27,7 @@ define i32 @test3(i32 %x, i32 %y) nounwind {
   %not = xor i32 %xor, -1
   %z = or i32 %x, %not
   ret i32 %z
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: %y.not = xor i32 %y, -1
 ; CHECK-NEXT: %z = or i32 %y.not, %x
 ; CHECK-NEXT: ret i32 %z
@@ -38,7 +38,7 @@ define i32 @test4(i32 %x, i32 %y) nounwind {
   %not = xor i32 %xor, -1
   %z = or i32 %y, %not
   ret i32 %z
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: %x.not = xor i32 %x, -1
 ; CHECK-NEXT: %z = or i32 %x.not, %y
 ; CHECK-NEXT: ret i32 %z
@@ -49,7 +49,7 @@ define i32 @test5(i32 %x, i32 %y) nounwind {
   %not = xor i32 %and, -1
   %z = or i32 %x, %not
   ret i32 %z
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NEXT: ret i32 -1
 }
 
@@ -58,7 +58,7 @@ define i32 @test6(i32 %x, i32 %y) nounwind {
   %not = xor i32 %and, -1
   %z = or i32 %y, %not
   ret i32 %z
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: ret i32 -1
 }
 
@@ -66,7 +66,7 @@ define i32 @test7(i32 %x, i32 %y) nounwind {
   %xor = xor i32 %x, %y
   %z = or i32 %y, %xor
   ret i32 %z
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NEXT: %z = or i32 %x, %y
 ; CHECK-NEXT: ret i32 %z
 }
@@ -76,7 +76,7 @@ define i32 @test8(i32 %x, i32 %y) nounwind {
   %xor = xor i32 %x, %not
   %z = or i32 %y, %xor
   ret i32 %z
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK-NEXT: %x.not = xor i32 %x, -1
 ; CHECK-NEXT: %z = or i32 %x.not, %y
 ; CHECK-NEXT: ret i32 %z
@@ -87,7 +87,7 @@ define i32 @test9(i32 %x, i32 %y) nounwind {
   %xor = xor i32 %not, %y
   %z = or i32 %x, %xor
   ret i32 %z
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NEXT: %y.not = xor i32 %y, -1
 ; CHECK-NEXT: %z = or i32 %y.not, %x
 ; CHECK-NEXT: ret i32 %z
diff --git a/test/Transforms/InstCombine/or.ll b/test/Transforms/InstCombine/or.ll
index 7226bd9..1cd897e 100644
--- a/test/Transforms/InstCombine/or.ll
+++ b/test/Transforms/InstCombine/or.ll
@@ -6,49 +6,49 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 define i32 @test1(i32 %A) {
         %B = or i32 %A, 0
         ret i32 %B
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret i32 %A
 }
 
 define i32 @test2(i32 %A) {
         %B = or i32 %A, -1 
         ret i32 %B
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: ret i32 -1
 }
 
 define i8 @test2a(i8 %A) {
         %B = or i8 %A, -1  
         ret i8 %B
-; CHECK: @test2a
+; CHECK-LABEL: @test2a(
 ; CHECK: ret i8 -1
 }
 
 define i1 @test3(i1 %A) {
         %B = or i1 %A, false
         ret i1 %B
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: ret i1 %A
 }
 
 define i1 @test4(i1 %A) {
         %B = or i1 %A, true 
         ret i1 %B
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: ret i1 true
 }
 
 define i1 @test5(i1 %A) {
         %B = or i1 %A, %A   
         ret i1 %B
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: ret i1 %A
 }
 
 define i32 @test6(i32 %A) {
         %B = or i32 %A, %A  
         ret i32 %B
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: ret i32 %A
 }
 
@@ -57,7 +57,7 @@ define i32 @test7(i32 %A) {
         %NotA = xor i32 -1, %A
         %B = or i32 %A, %NotA
         ret i32 %B
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: ret i32 -1
 }
 
@@ -65,7 +65,7 @@ define i8 @test8(i8 %A) {
         %B = or i8 %A, -2
         %C = or i8 %B, 1
         ret i8 %C
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: ret i8 -1
 }
 
@@ -75,7 +75,7 @@ define i8 @test9(i8 %A, i8 %B) {
         %D = or i8 %B, -2
         %E = or i8 %C, %D
         ret i8 %E
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK: ret i8 -1
 }
 
@@ -85,7 +85,7 @@ define i8 @test10(i8 %A) {
         ; (X & C1) | C2 --> (X | C2) & (C1|C2)
         %D = or i8 %C, -2
         ret i8 %D
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK: ret i8 -2
 }
 
@@ -96,7 +96,7 @@ define i8 @test11(i8 %A) {
         %D = or i8 %C, 1
         %E = xor i8 %D, 12
         ret i8 %E
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK: ret i8 -1
 }
 
@@ -105,7 +105,7 @@ define i32 @test12(i32 %A) {
         %B = or i32 %A, 4
         %C = and i32 %B, 8
         ret i32 %C
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK: %C = and i32 %A, 8
 ; CHECK: ret i32 %C
 }
@@ -115,7 +115,7 @@ define i32 @test13(i32 %A) {
         ; Always equal to 8
         %C = and i32 %B, 8
         ret i32 %C
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK: ret i32 8
 }
 
@@ -125,7 +125,7 @@ define i1 @test14(i32 %A, i32 %B) {
         ; (A < B) | (A > B) === A != B
         %D = or i1 %C1, %C2
         ret i1 %D
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK: icmp ne i32 %A, %B
 ; CHECK: ret i1
 }
@@ -136,7 +136,7 @@ define i1 @test15(i32 %A, i32 %B) {
         ; (A < B) | (A == B) === A <= B
         %D = or i1 %C1, %C2
         ret i1 %D
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 ; CHECK:  icmp ule i32 %A, %B
 ; CHECK: ret i1
 }
@@ -148,7 +148,7 @@ define i32 @test16(i32 %A) {
         ; %D = and int %B, -1 == %B
         %D = or i32 %B, %C
         ret i32 %D
-; CHECK: @test16
+; CHECK-LABEL: @test16(
 ; CHECK: ret i32 %A
 }
 
@@ -158,7 +158,7 @@ define i32 @test17(i32 %A) {
         ; %D = and int %B, 5
         %D = or i32 %B, %C
         ret i32 %D
-; CHECK: @test17
+; CHECK-LABEL: @test17(
 ; CHECK: %D = and i32 %A, 5
 ; CHECK: ret i32 %D
 }
@@ -169,7 +169,7 @@ define i1 @test18(i32 %A) {
         ;; (A-50) >u 50
         %D = or i1 %B, %C
         ret i1 %D
-; CHECK: @test18
+; CHECK-LABEL: @test18(
 ; CHECK: add i32
 ; CHECK:  icmp ugt 
 ; CHECK: ret i1 
@@ -181,7 +181,7 @@ define i1 @test19(i32 %A) {
         ;; (A&-2) == 50
         %D = or i1 %B, %C
         ret i1 %D
-; CHECK: @test19
+; CHECK-LABEL: @test19(
 ; CHECK: and i32
 ; CHECK: icmp eq 
 ; CHECK: ret i1
@@ -191,7 +191,7 @@ define i32 @test20(i32 %x) {
         %y = and i32 %x, 123
         %z = or i32 %y, %x
         ret i32 %z
-; CHECK: @test20
+; CHECK-LABEL: @test20(
 ; CHECK: ret i32 %x
 }
 
@@ -202,7 +202,7 @@ define i32 @test21(i32 %tmp.1) {
         ;; add tmp.1, 2
         %tmp.6 = or i32 %tmp.5, %tmp.3
         ret i32 %tmp.6
-; CHECK: @test21
+; CHECK-LABEL: @test21(
 ; CHECK:   add i32 %{{[^,]*}}, 2
 ; CHECK:   ret i32 
 }
@@ -212,7 +212,7 @@ define i32 @test22(i32 %B) {
         %ELIM7 = and i32 %B, -2
         %ELIM5 = or i32 %ELIM41, %ELIM7
         ret i32 %ELIM5
-; CHECK: @test22
+; CHECK-LABEL: @test22(
 ; CHECK: ret i32 %B
 }
 
@@ -222,7 +222,7 @@ define i16 @test23(i16 %A) {
         %C = or i16 %B, -32768
         %D = xor i16 %C, 8193
         ret i16 %D
-; CHECK: @test23
+; CHECK-LABEL: @test23(
 ; CHECK:   %B = lshr i16 %A, 1
 ; CHECK:   %D = xor i16 %B, -24575
 ; CHECK:   ret i16 %D
@@ -235,7 +235,7 @@ define i1 @test24(double %X, double %Y) {
         %bothcond = or i1 %tmp13, %tmp9         ; <i1> [#uses=1]
         ret i1 %bothcond
         
-; CHECK: @test24
+; CHECK-LABEL: @test24(
 ; CHECK:    = fcmp uno double %Y, %X
 ; CHECK:   ret i1 
 }
@@ -248,7 +248,7 @@ define i1 @test25(i32 %A, i32 %B) {
   %F = xor i1 %E, -1
   ret i1 %F
 
-; CHECK: @test25
+; CHECK-LABEL: @test25(
 ; CHECK: icmp ne i32 %A, 0
 ; CHECK-NEXT: icmp ne i32 %B, 57
 ; CHECK-NEXT:  %F = and i1 
@@ -262,7 +262,7 @@ define i1 @test26(i32 %A, i32 %B) {
         ; (A == 0) & (A == 0)   -->   (A|B) == 0
         %D = and i1 %C1, %C2
         ret i1 %D
-; CHECK: @test26
+; CHECK-LABEL: @test26(
 ; CHECK: or i32 %A, %B
 ; CHECK: icmp eq i32 {{.*}}, 0
 ; CHECK: ret i1 
@@ -274,7 +274,7 @@ define i1 @test27(i32* %A, i32* %B) {
   %D = or i32 %C1, %C2
   %E = icmp eq i32 %D, 0
   ret i1 %E
-; CHECK: @test27
+; CHECK-LABEL: @test27(
 ; CHECK: icmp eq i32* %A, null
 ; CHECK: icmp eq i32* %B, null
 ; CHECK: and i1
@@ -288,7 +288,7 @@ define i1 @test28(i32 %A, i32 %B) {
         ; (A != 0) | (A != 0)   -->   (A|B) != 0
         %D = or i1 %C1, %C2
         ret i1 %D
-; CHECK: @test28
+; CHECK-LABEL: @test28(
 ; CHECK: or i32 %A, %B
 ; CHECK: icmp ne i32 {{.*}}, 0
 ; CHECK: ret i1 
@@ -300,7 +300,7 @@ define i1 @test29(i32* %A, i32* %B) {
   %D = or i32 %C1, %C2
   %E = icmp ne i32 %D, 0
   ret i1 %E
-; CHECK: @test29
+; CHECK-LABEL: @test29(
 ; CHECK: icmp ne i32* %A, null
 ; CHECK: icmp ne i32* %B, null
 ; CHECK: or i1
@@ -315,7 +315,7 @@ entry:
   %D = and i32 %B, 40186
   %E = or i32 %D, %C
   ret i32 %E
-; CHECK: @test30
+; CHECK-LABEL: @test30(
 ; CHECK: %D = and i32 %A, -58312
 ; CHECK: %E = or i32 %D, 32962
 ; CHECK: ret i32 %E
@@ -331,7 +331,7 @@ define i64 @test31(i64 %A) nounwind readnone ssp noredzone {
 
   %F = or i64 %D, %E
   ret i64 %F
-; CHECK: @test31
+; CHECK-LABEL: @test31(
 ; CHECK-NEXT: %E = and i64 %A, 4294908984
 ; CHECK-NEXT: %F = or i64 %E, 32962
 ; CHECK-NEXT: ret i64 %F
@@ -345,7 +345,7 @@ define <4 x i32> @test32(<4 x i1> %and.i1352, <4 x i32> %vecinit6.i176, <4 x i32
   %or.i = or <4 x i32> %and.i, %and.i129          ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %or.i
 ; codegen is mature enough to handle vector selects.
-; CHECK: @test32
+; CHECK-LABEL: @test32(
 ; CHECK: select <4 x i1> %and.i1352, <4 x i32> %vecinit6.i176, <4 x i32> %vecinit6.i191
 }
 
@@ -353,7 +353,7 @@ define i1 @test33(i1 %X, i1 %Y) {
   %a = or i1 %X, %Y
   %b = or i1 %a, %X
   ret i1 %b
-; CHECK: @test33
+; CHECK-LABEL: @test33(
 ; CHECK-NEXT: or i1 %X, %Y
 ; CHECK-NEXT: ret
 }
@@ -362,7 +362,7 @@ define i32 @test34(i32 %X, i32 %Y) {
   %a = or i32 %X, %Y
   %b = or i32 %Y, %a
   ret i32 %b
-; CHECK: @test34
+; CHECK-LABEL: @test34(
 ; CHECK-NEXT: or i32 %X, %Y
 ; CHECK-NEXT: ret
 }
@@ -371,7 +371,7 @@ define i32 @test35(i32 %a, i32 %b) {
   %1 = or i32 %a, 1135
   %2 = or i32 %1, %b
   ret i32 %2
-  ; CHECK: @test35
+  ; CHECK-LABEL: @test35(
   ; CHECK-NEXT: or i32 %a, %b
   ; CHECK-NEXT: or i32 %1, 1135
 }
@@ -383,14 +383,14 @@ define i1 @test36(i32 %x) {
   %cmp3 = icmp eq i32 %x, 25
   %ret2 = or i1 %ret1, %cmp3
   ret i1 %ret2
-; CHECK: @test36
+; CHECK-LABEL: @test36(
 ; CHECK-NEXT: %x.off = add i32 %x, -23
 ; CHECK-NEXT: icmp ult i32 %x.off, 3
 ; CHECK-NEXT: ret i1
 }
 
 define i32 @test37(i32* %xp, i32 %y) {
-; CHECK: @test37
+; CHECK-LABEL: @test37(
 ; CHECK: select i1 %tobool, i32 -1, i32 %x
   %tobool = icmp ne i32 %y, 0
   %sext = sext i1 %tobool to i32
@@ -400,7 +400,7 @@ define i32 @test37(i32* %xp, i32 %y) {
 }
 
 define i32 @test38(i32* %xp, i32 %y) {
-; CHECK: @test38
+; CHECK-LABEL: @test38(
 ; CHECK: select i1 %tobool, i32 -1, i32 %x
   %tobool = icmp ne i32 %y, 0
   %sext = sext i1 %tobool to i32
diff --git a/test/Transforms/InstCombine/osx-names.ll b/test/Transforms/InstCombine/osx-names.ll
index 7b83526..926caad 100644
--- a/test/Transforms/InstCombine/osx-names.ll
+++ b/test/Transforms/InstCombine/osx-names.ll
@@ -14,14 +14,14 @@ target triple = "i386-apple-macosx10.7.2"
 @.str2 = private unnamed_addr constant [3 x i8] c"%s\00", align 1
 
 define void @test1(%struct.__sFILE* %stream) nounwind {
-; CHECK: define void @test1
+; CHECK-LABEL: define void @test1(
 ; CHECK: call i32 @"fwrite$UNIX2003"
   %call = tail call i32 (%struct.__sFILE*, i8*, ...)* @fprintf(%struct.__sFILE* %stream, i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0)) nounwind
   ret void
 }
 
 define void @test2(%struct.__sFILE* %stream, i8* %str) nounwind ssp {
-; CHECK: define void @test2
+; CHECK-LABEL: define void @test2(
 ; CHECK: call i32 @"fputs$UNIX2003"
   %call = tail call i32 (%struct.__sFILE*, i8*, ...)* @fprintf(%struct.__sFILE* %stream, i8* getelementptr inbounds ([3 x i8]* @.str2, i32 0, i32 0), i8* %str) nounwind
   ret void
diff --git a/test/Transforms/InstCombine/overflow.ll b/test/Transforms/InstCombine/overflow.ll
index 81ceef8..3eddc80 100644
--- a/test/Transforms/InstCombine/overflow.ll
+++ b/test/Transforms/InstCombine/overflow.ll
@@ -3,7 +3,7 @@
 
 declare void @throwAnExceptionOrWhatever()
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 define i32 @test1(i32 %a, i32 %b) nounwind ssp {
 entry:
 ; CHECK-NOT: sext
@@ -26,7 +26,7 @@ if.end:
   ret i32 %conv9
 }
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; This form should not be promoted for two reasons: 1) it is unprofitable to
 ; promote it since the add.off instruction has another use, and 2) it is unsafe
 ; because the add-with-off makes the high bits of the original add live.
@@ -76,7 +76,7 @@ if.end:
 ; CHECK: ret i64
 }
 
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; Should be able to form an i8 sadd computed in an i32.
 define zeroext i8 @test4(i8 signext %a, i8 signext %b) nounwind ssp {
 entry:
@@ -97,7 +97,7 @@ if.end:                                           ; preds = %entry
 ; CHECK: ret i8
 }
 
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: llvm.uadd.with.overflow
 ; CHECK: ret i64
 define i64 @test5(i64 %a, i64 %b) nounwind ssp {
@@ -108,7 +108,7 @@ entry:
   ret i64 %Q
 }
 
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: llvm.uadd.with.overflow
 ; CHECK: ret i64
 define i64 @test6(i64 %a, i64 %b) nounwind ssp {
@@ -119,7 +119,7 @@ entry:
   ret i64 %Q
 }
 
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: llvm.uadd.with.overflow
 ; CHECK: ret i64
 define i64 @test7(i64 %a, i64 %b) nounwind ssp {
@@ -130,7 +130,7 @@ entry:
   ret i64 %Q
 }
 
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; PR11438
 ; This is @test1, but the operands are not sign-extended.  Make sure
 ; we don't transform this case.
diff --git a/test/Transforms/InstCombine/phi.ll b/test/Transforms/InstCombine/phi.ll
index 1c307d4..6e31465 100644
--- a/test/Transforms/InstCombine/phi.ll
+++ b/test/Transforms/InstCombine/phi.ll
@@ -15,7 +15,7 @@ BB1:
 
 BB2:
         ret i32 %A
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: BB1:
 ; CHECK-NEXT: ret i32 %A
 }
@@ -31,7 +31,7 @@ BB2:
         ; Combine away PHI nodes with same values
         %B = phi i32 [ %A, %BB0 ], [ %A, %BB1 ]         
         ret i32 %B
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: BB2:
 ; CHECK-NEXT: ret i32 %A
 }
@@ -47,7 +47,7 @@ Loop:
 
 Exit:
         ret i32 %B
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: Exit:
 ; CHECK-NEXT: ret i32 %A
 }
@@ -64,7 +64,7 @@ Loop:           ; preds = %L2, %Loop
 
 L2:             ; preds = %Loop
         br label %Loop
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: Loop:
 ; CHECK-NEXT: br i1 %b
 }
@@ -80,7 +80,7 @@ Loop:           ; preds = %Loop, %BB0
 
 Exit:           ; preds = %Loop
         ret i32 %B
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: Loop:
 ; CHECK-NEXT: br i1 %b
 ; CHECK: Exit:
@@ -100,7 +100,7 @@ BB2:
         ;; Suck casts into phi
         %B = phi i32 [ %X, %BB0 ], [ %Y, %BB1 ]         
         ret i32 %B
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: BB2:
 ; CHECK: zext i16 %A to i32
 ; CHECK-NEXT: ret i32
@@ -118,7 +118,7 @@ Loop:           ; preds = %Loop, %BB0
 
 Exit:           ; preds = %Loop
         ret i32 0
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: Loop:
 ; CHECK-NEXT: br i1 %b
 }
@@ -136,7 +136,7 @@ BB2:
         ;; Suck GEPs into phi
         %B = phi i32* [ %X, %BB0 ], [ %Y, %BB1 ]
         ret i32* %B
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK-NOT: phi
 ; CHECK: BB2:
 ; CHECK-NEXT: %B = getelementptr { i32, i32 }* %A 
@@ -159,7 +159,7 @@ bb1:
 bb2:
   %E = phi i32 [ %C, %bb ], [ %D, %bb1 ]
   ret i32 %E
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK:       bb2:
 ; CHECK-NEXT:        phi i32* [ %B, %bb ], [ %A, %bb1 ]
 ; CHECK-NEXT:   %E = load i32* %{{[^,]*}}, align 1
@@ -183,7 +183,7 @@ bb1:
 bb2:
   %E = phi i32 [ %C, %bb ], [ %D, %bb1 ]
   ret i32 %E
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK:       bb2:
 ; CHECK-NEXT:        phi i32* [ %B, %bb ], [ %A, %bb1 ]
 ; CHECK-NEXT:   %E = load i32* %{{[^,]*}}, align 16
@@ -219,7 +219,7 @@ end:
   store i32 10, i32* %g
   %z = call i1 @test11a()
   ret i1 %z
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK-NOT: phi i32
 ; CHECK: ret i1 %z
 }
@@ -245,7 +245,7 @@ end:
 
   %tmp2 = add i64 %tmp32, %tmp30
   ret i64 %tmp2
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK-NOT: zext
 ; CHECK: end:
 ; CHECK-NEXT: phi i64 [ 0, %entry ], [ %Val, %two ]
@@ -276,7 +276,7 @@ end:
   
   call void @test13f(double %tmp31, i32 %tmp32)
   ret void
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK-NOT: zext
 ; CHECK: end:
 ; CHECK-NEXT: phi double [ 0.000000e+00, %entry ], [ %Vald, %two ]
@@ -296,7 +296,7 @@ Loop:
 
 Exit:           ; preds = %Loop
         ret i640 %C
-; CHECK: @test14a
+; CHECK-LABEL: @test14a(
 ; CHECK: Loop:
 ; CHECK-NEXT: phi i320
 }
@@ -313,7 +313,7 @@ Loop:
 
 Exit:           ; preds = %Loop
         ret i160 %C
-; CHECK: @test14b
+; CHECK-LABEL: @test14b(
 ; CHECK: Loop:
 ; CHECK-NEXT: phi i160
 }
@@ -321,7 +321,7 @@ Exit:           ; preds = %Loop
 declare i64 @test15a(i64)
 
 define i64 @test15b(i64 %A, i1 %b) {
-; CHECK: @test15b
+; CHECK-LABEL: @test15b(
 entry:
   %i0 = zext i64 %A to i128
   %i1 = shl i128 %i0, 64
@@ -405,7 +405,7 @@ if.else:                                          ; preds = %entry
 
 ; PR4413
 declare i32 @ext()
-; CHECK: @test17
+; CHECK-LABEL: @test17(
 define i32 @test17(i1 %a) {
 entry:
     br i1 %a, label %bb1, label %bb2
@@ -435,7 +435,7 @@ ret:
   %ptr = phi i32* [ %zero, %true ] , [ %one, %false ]
   %isnull = icmp eq i32* %ptr, null
   ret i1 %isnull
-; CHECK: @test18
+; CHECK-LABEL: @test18(
 ; CHECK: ret i1 false
 }
 
@@ -449,7 +449,7 @@ ret:
   %p = phi double [ %x, %true ], [ 0x7FF0000000000000, %false ]; RHS = +infty
   %cmp = fcmp ule double %x, %p
   ret i1 %cmp
-; CHECK: @test19
+; CHECK-LABEL: @test19(
 ; CHECK: ret i1 true
 }
 
@@ -466,7 +466,7 @@ ret:
   %p = phi i32* [ %a, %true ], [ %b, %false ]
   %r = icmp eq i32* %p, %c
   ret i1 %r
-; CHECK: @test20
+; CHECK-LABEL: @test20(
 ; CHECK: ret i1 false
 }
 
@@ -485,12 +485,12 @@ loop:
   br i1 %c2, label %ret, label %loop
 ret:
   ret i1 %r
-; CHECK: @test21
+; CHECK-LABEL: @test21(
 ; CHECK: ret i1 false
 }
 
 define void @test22() {
-; CHECK: @test22
+; CHECK-LABEL: @test22(
 entry:
   br label %loop
 loop:
@@ -518,7 +518,7 @@ Loop:           ; preds = %Loop, %BB0
 Exit:           ; preds = %Loop
         %E = add i32 %B, 19
         ret i32 %E
-; CHECK: @test23
+; CHECK-LABEL: @test23(
 ; CHECK: %phitmp = add i32 %A, 19
 ; CHECK: Loop:
 ; CHECK-NEXT: %B = phi i32 [ %phitmp, %BB0 ], [ 61, %Loop ]
@@ -538,7 +538,7 @@ BB1:
 BB2:
         %C = phi i32 [ %X, %BB0 ], [ %Y, %BB1 ]
         ret i32 %C
-; CHECK: @test24
+; CHECK-LABEL: @test24(
 ; CHECK-NOT: phi
 ; CHECK: BB2:
 ; CHECK-NEXT: %C = add nuw i32 %A, 1
@@ -573,7 +573,7 @@ end:
   store i32 10, i32* %g
   %z = call i1 @test25a()
   ret i1 %z
-; CHECK: @test25
+; CHECK-LABEL: @test25(
 ; CHECK-NOT: phi i32
 ; CHECK: ret i1 %z
 }
@@ -616,12 +616,12 @@ end:
   store i32 10, i32* %g
   %z = call i1 @test26a()
   ret i1 %z
-; CHECK: @test26
+; CHECK-LABEL: @test26(
 ; CHECK-NOT: phi i32
 ; CHECK: ret i1 %z
 }
 
-; CHECK: @test27(
+; CHECK-LABEL: @test27(
 ; CHECK: ret i32 undef
 define i32 @test27(i1 %b) {
 entry:
diff --git a/test/Transforms/InstCombine/pow-1.ll b/test/Transforms/InstCombine/pow-1.ll
index 8a311f0..0fdafeb 100644
--- a/test/Transforms/InstCombine/pow-1.ll
+++ b/test/Transforms/InstCombine/pow-1.ll
@@ -12,14 +12,14 @@ declare double @pow(double, double) nounwind readonly
 ; Check pow(1.0, x) -> 1.0.
 
 define float @test_simplify1(float %x) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %retval = call float @powf(float 1.0, float %x)
   ret float %retval
 ; CHECK-NEXT: ret float 1.000000e+00
 }
 
 define double @test_simplify2(double %x) {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %retval = call double @pow(double 1.0, double %x)
   ret double %retval
 ; CHECK-NEXT: ret double 1.000000e+00
@@ -28,7 +28,7 @@ define double @test_simplify2(double %x) {
 ; Check pow(2.0, x) -> exp2(x).
 
 define float @test_simplify3(float %x) {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %retval = call float @powf(float 2.0, float %x)
 ; CHECK-NEXT: [[EXP2F:%[a-z0-9]+]] = call float @exp2f(float %x) [[NUW_RO:#[0-9]+]]
   ret float %retval
@@ -36,7 +36,7 @@ define float @test_simplify3(float %x) {
 }
 
 define double @test_simplify4(double %x) {
-; CHECK: @test_simplify4
+; CHECK-LABEL: @test_simplify4(
   %retval = call double @pow(double 2.0, double %x)
 ; CHECK-NEXT: [[EXP2:%[a-z0-9]+]] = call double @exp2(double %x) [[NUW_RO]]
   ret double %retval
@@ -46,14 +46,14 @@ define double @test_simplify4(double %x) {
 ; Check pow(x, 0.0) -> 1.0.
 
 define float @test_simplify5(float %x) {
-; CHECK: @test_simplify5
+; CHECK-LABEL: @test_simplify5(
   %retval = call float @powf(float %x, float 0.0)
   ret float %retval
 ; CHECK-NEXT: ret float 1.000000e+00
 }
 
 define double @test_simplify6(double %x) {
-; CHECK: @test_simplify6
+; CHECK-LABEL: @test_simplify6(
   %retval = call double @pow(double %x, double 0.0)
   ret double %retval
 ; CHECK-NEXT: ret double 1.000000e+00
@@ -62,7 +62,7 @@ define double @test_simplify6(double %x) {
 ; Check pow(x, 0.5) -> fabs(sqrt(x)), where x != -infinity.
 
 define float @test_simplify7(float %x) {
-; CHECK: @test_simplify7
+; CHECK-LABEL: @test_simplify7(
   %retval = call float @powf(float %x, float 0.5)
 ; CHECK-NEXT: [[SQRTF:%[a-z0-9]+]] = call float @sqrtf(float %x) [[NUW_RO]]
 ; CHECK-NEXT: [[FABSF:%[a-z0-9]+]] = call float @fabsf(float [[SQRTF]]) [[NUW_RO]]
@@ -73,7 +73,7 @@ define float @test_simplify7(float %x) {
 }
 
 define double @test_simplify8(double %x) {
-; CHECK: @test_simplify8
+; CHECK-LABEL: @test_simplify8(
   %retval = call double @pow(double %x, double 0.5)
 ; CHECK-NEXT: [[SQRT:%[a-z0-9]+]] = call double @sqrt(double %x) [[NUW_RO]]
 ; CHECK-NEXT: [[FABS:%[a-z0-9]+]] = call double @fabs(double [[SQRT]]) [[NUW_RO]]
@@ -86,14 +86,14 @@ define double @test_simplify8(double %x) {
 ; Check pow(-infinity, 0.5) -> +infinity.
 
 define float @test_simplify9(float %x) {
-; CHECK: @test_simplify9
+; CHECK-LABEL: @test_simplify9(
   %retval = call float @powf(float 0xFFF0000000000000, float 0.5)
   ret float %retval
 ; CHECK-NEXT: ret float 0x7FF0000000000000
 }
 
 define double @test_simplify10(double %x) {
-; CHECK: @test_simplify10
+; CHECK-LABEL: @test_simplify10(
   %retval = call double @pow(double 0xFFF0000000000000, double 0.5)
   ret double %retval
 ; CHECK-NEXT: ret double 0x7FF0000000000000
@@ -102,14 +102,14 @@ define double @test_simplify10(double %x) {
 ; Check pow(x, 1.0) -> x.
 
 define float @test_simplify11(float %x) {
-; CHECK: @test_simplify11
+; CHECK-LABEL: @test_simplify11(
   %retval = call float @powf(float %x, float 1.0)
   ret float %retval
 ; CHECK-NEXT: ret float %x
 }
 
 define double @test_simplify12(double %x) {
-; CHECK: @test_simplify12
+; CHECK-LABEL: @test_simplify12(
   %retval = call double @pow(double %x, double 1.0)
   ret double %retval
 ; CHECK-NEXT: ret double %x
@@ -118,7 +118,7 @@ define double @test_simplify12(double %x) {
 ; Check pow(x, 2.0) -> x*x.
 
 define float @test_simplify13(float %x) {
-; CHECK: @test_simplify13
+; CHECK-LABEL: @test_simplify13(
   %retval = call float @powf(float %x, float 2.0)
 ; CHECK-NEXT: [[SQUARE:%[a-z0-9]+]] = fmul float %x, %x
   ret float %retval
@@ -126,7 +126,7 @@ define float @test_simplify13(float %x) {
 }
 
 define double @test_simplify14(double %x) {
-; CHECK: @test_simplify14
+; CHECK-LABEL: @test_simplify14(
   %retval = call double @pow(double %x, double 2.0)
 ; CHECK-NEXT: [[SQUARE:%[a-z0-9]+]] = fmul double %x, %x
   ret double %retval
@@ -136,7 +136,7 @@ define double @test_simplify14(double %x) {
 ; Check pow(x, -1.0) -> 1.0/x.
 
 define float @test_simplify15(float %x) {
-; CHECK: @test_simplify15
+; CHECK-LABEL: @test_simplify15(
   %retval = call float @powf(float %x, float -1.0)
 ; CHECK-NEXT: [[RECIPROCAL:%[a-z0-9]+]] = fdiv float 1.000000e+00, %x
   ret float %retval
@@ -144,7 +144,7 @@ define float @test_simplify15(float %x) {
 }
 
 define double @test_simplify16(double %x) {
-; CHECK: @test_simplify16
+; CHECK-LABEL: @test_simplify16(
   %retval = call double @pow(double %x, double -1.0)
 ; CHECK-NEXT: [[RECIPROCAL:%[a-z0-9]+]] = fdiv double 1.000000e+00, %x
   ret double %retval
diff --git a/test/Transforms/InstCombine/pow-2.ll b/test/Transforms/InstCombine/pow-2.ll
index af64cda..d1ffde7 100644
--- a/test/Transforms/InstCombine/pow-2.ll
+++ b/test/Transforms/InstCombine/pow-2.ll
@@ -7,7 +7,7 @@ declare float @pow(double, double)
 ; Check that pow functions with the wrong prototype aren't simplified.
 
 define float @test_no_simplify1(double %x) {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %retval = call float @pow(double 1.0, double %x)
 ; CHECK-NEXT: call float @pow(double 1.000000e+00, double %x)
   ret float %retval
diff --git a/test/Transforms/InstCombine/pr8547.ll b/test/Transforms/InstCombine/pr8547.ll
index 485f4d9..7e9cbe1 100644
--- a/test/Transforms/InstCombine/pr8547.ll
+++ b/test/Transforms/InstCombine/pr8547.ll
@@ -23,4 +23,4 @@ for.cond:                                         ; preds = %for.cond, %codeRepl
 codeRepl2:                                        ; preds = %for.cond
   %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i64 0, i64 0), i32 %conv2) nounwind
   ret i32 0
-}
\ No newline at end of file
+}
diff --git a/test/Transforms/InstCombine/printf-1.ll b/test/Transforms/InstCombine/printf-1.ll
index 3a910ea..59d0f16 100644
--- a/test/Transforms/InstCombine/printf-1.ll
+++ b/test/Transforms/InstCombine/printf-1.ll
@@ -20,7 +20,7 @@ declare i32 @printf(i8*, ...)
 ; Check printf("") -> noop.
 
 define void @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %fmt = getelementptr [1 x i8]* @empty, i32 0, i32 0
   call i32 (i8*, ...)* @printf(i8* %fmt)
   ret void
@@ -30,7 +30,7 @@ define void @test_simplify1() {
 ; Check printf("x") -> putchar('x'), even for '%'.
 
 define void @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %fmt = getelementptr [2 x i8]* @h, i32 0, i32 0
   call i32 (i8*, ...)* @printf(i8* %fmt)
 ; CHECK-NEXT: call i32 @putchar(i32 104)
@@ -39,7 +39,7 @@ define void @test_simplify2() {
 }
 
 define void @test_simplify3() {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %fmt = getelementptr [2 x i8]* @percent, i32 0, i32 0
   call i32 (i8*, ...)* @printf(i8* %fmt)
 ; CHECK-NEXT: call i32 @putchar(i32 37)
@@ -50,7 +50,7 @@ define void @test_simplify3() {
 ; Check printf("foo\n") -> puts("foo").
 
 define void @test_simplify4() {
-; CHECK: @test_simplify4
+; CHECK-LABEL: @test_simplify4(
   %fmt = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
   call i32 (i8*, ...)* @printf(i8* %fmt)
 ; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([12 x i8]* [[STR]], i32 0, i32 0))
@@ -61,7 +61,7 @@ define void @test_simplify4() {
 ; Check printf("%c", chr) -> putchar(chr).
 
 define void @test_simplify5() {
-; CHECK: @test_simplify5
+; CHECK-LABEL: @test_simplify5(
   %fmt = getelementptr [3 x i8]* @percent_c, i32 0, i32 0
   call i32 (i8*, ...)* @printf(i8* %fmt, i8 104)
 ; CHECK-NEXT: call i32 @putchar(i32 104)
@@ -72,7 +72,7 @@ define void @test_simplify5() {
 ; Check printf("%s\n", str) -> puts(str).
 
 define void @test_simplify6() {
-; CHECK: @test_simplify6
+; CHECK-LABEL: @test_simplify6(
   %fmt = getelementptr [4 x i8]* @percent_s, i32 0, i32 0
   %str = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
   call i32 (i8*, ...)* @printf(i8* %fmt, i8* %str)
@@ -84,7 +84,7 @@ define void @test_simplify6() {
 ; Check printf(format, ...) -> iprintf(format, ...) if no floating point.
 
 define void @test_simplify7() {
-; CHECK-IPRINTF: @test_simplify7
+; CHECK-IPRINTF-LABEL: @test_simplify7(
   %fmt = getelementptr [3 x i8]* @percent_d, i32 0, i32 0
   call i32 (i8*, ...)* @printf(i8* %fmt, i32 187)
 ; CHECK-NEXT-IPRINTF: call i32 (i8*, ...)* @iprintf(i8* getelementptr inbounds ([3 x i8]* @percent_d, i32 0, i32 0), i32 187)
@@ -93,7 +93,7 @@ define void @test_simplify7() {
 }
 
 define void @test_no_simplify1() {
-; CHECK-IPRINTF: @test_no_simplify1
+; CHECK-IPRINTF-LABEL: @test_no_simplify1(
   %fmt = getelementptr [3 x i8]* @percent_f, i32 0, i32 0
   call i32 (i8*, ...)* @printf(i8* %fmt, double 1.87)
 ; CHECK-NEXT-IPRINTF: call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00)
@@ -102,7 +102,7 @@ define void @test_no_simplify1() {
 }
 
 define void @test_no_simplify2(i8* %fmt, double %d) {
-; CHECK: @test_no_simplify2
+; CHECK-LABEL: @test_no_simplify2(
   call i32 (i8*, ...)* @printf(i8* %fmt, double %d)
 ; CHECK-NEXT: call i32 (i8*, ...)* @printf(i8* %fmt, double %d)
   ret void
@@ -110,7 +110,7 @@ define void @test_no_simplify2(i8* %fmt, double %d) {
 }
 
 define i32 @test_no_simplify3() {
-; CHECK: @test_no_simplify3
+; CHECK-LABEL: @test_no_simplify3(
   %fmt = getelementptr [2 x i8]* @h, i32 0, i32 0
   %ret = call i32 (i8*, ...)* @printf(i8* %fmt)
 ; CHECK-NEXT: call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([2 x i8]* @h, i32 0, i32 0))
diff --git a/test/Transforms/InstCombine/printf-2.ll b/test/Transforms/InstCombine/printf-2.ll
index 466ee1c..7e018eb 100644
--- a/test/Transforms/InstCombine/printf-2.ll
+++ b/test/Transforms/InstCombine/printf-2.ll
@@ -13,7 +13,7 @@ declare void @printf(i8*, ...)
 ; Check simplification of printf with void return type.
 
 define void @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %fmt = getelementptr [2 x i8]* @h, i32 0, i32 0
   call void (i8*, ...)* @printf(i8* %fmt)
 ; CHECK-NEXT: call i32 @putchar(i32 104)
@@ -22,7 +22,7 @@ define void @test_simplify1() {
 }
 
 define void @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %fmt = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
   call void (i8*, ...)* @printf(i8* %fmt)
 ; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([12 x i8]* @str, i32 0, i32 0))
@@ -31,7 +31,7 @@ define void @test_simplify2() {
 }
 
 define void @test_simplify6() {
-; CHECK: @test_simplify6
+; CHECK-LABEL: @test_simplify6(
   %fmt = getelementptr [4 x i8]* @percent_s, i32 0, i32 0
   %str = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
   call void (i8*, ...)* @printf(i8* %fmt, i8* %str)
diff --git a/test/Transforms/InstCombine/ptr-int-cast.ll b/test/Transforms/InstCombine/ptr-int-cast.ll
index 7a6ecff..826c004 100644
--- a/test/Transforms/InstCombine/ptr-int-cast.ll
+++ b/test/Transforms/InstCombine/ptr-int-cast.ll
@@ -28,7 +28,7 @@ define i64 @f0(i32 %a0) nounwind {
 }
 
 define <4 x i32> @test4(<4 x i8*> %arg) nounwind {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: ptrtoint <4 x i8*> %arg to <4 x i64>
 ; CHECK: trunc <4 x i64> %1 to <4 x i32>
   %p1 = ptrtoint <4 x i8*> %arg to <4 x i32>
@@ -36,7 +36,7 @@ define <4 x i32> @test4(<4 x i8*> %arg) nounwind {
 }
 
 define <4 x i128> @test5(<4 x i8*> %arg) nounwind {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: ptrtoint <4 x i8*> %arg to <4 x i64>
 ; CHECK: zext <4 x i64> %1 to <4 x i128>
   %p1 = ptrtoint <4 x i8*> %arg to <4 x i128>
@@ -44,7 +44,7 @@ define <4 x i128> @test5(<4 x i8*> %arg) nounwind {
 }
 
 define <4 x i8*> @test6(<4 x i32> %arg) nounwind {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: zext <4 x i32> %arg to <4 x i64>
 ; CHECK: inttoptr <4 x i64> %1 to <4 x i8*>
   %p1 = inttoptr <4 x i32> %arg to <4 x i8*>
@@ -52,7 +52,7 @@ define <4 x i8*> @test6(<4 x i32> %arg) nounwind {
 }
 
 define <4 x i8*> @test7(<4 x i128> %arg) nounwind {
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: trunc <4 x i128> %arg to <4 x i64>
 ; CHECK: inttoptr <4 x i64> %1 to <4 x i8*>
   %p1 = inttoptr <4 x i128> %arg to <4 x i8*>
diff --git a/test/Transforms/InstCombine/puts-1.ll b/test/Transforms/InstCombine/puts-1.ll
index ef4e1bb..bd7557e 100644
--- a/test/Transforms/InstCombine/puts-1.ll
+++ b/test/Transforms/InstCombine/puts-1.ll
@@ -11,7 +11,7 @@ declare i32 @puts(i8*)
 ; Check puts("") -> putchar('\n').
 
 define void @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %str = getelementptr [1 x i8]* @empty, i32 0, i32 0
   call i32 @puts(i8* %str)
 ; CHECK-NEXT: call i32 @putchar(i32 10)
@@ -22,7 +22,7 @@ define void @test_simplify1() {
 ; Don't simplify if the return value is used.
 
 define i32 @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %str = getelementptr [1 x i8]* @empty, i32 0, i32 0
   %ret = call i32 @puts(i8* %str)
 ; CHECK-NEXT: call i32 @puts(i8* getelementptr inbounds ([1 x i8]* @empty, i32 0, i32 0))
diff --git a/test/Transforms/InstCombine/rem.ll b/test/Transforms/InstCombine/rem.ll
index 808d51e..22fd90b 100644
--- a/test/Transforms/InstCombine/rem.ll
+++ b/test/Transforms/InstCombine/rem.ll
@@ -4,21 +4,21 @@
 ; END.
 
 define i32 @test1(i32 %A) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: ret i32 0
 	%B = srem i32 %A, 1	; ISA constant 0
 	ret i32 %B
 }
 
 define i32 @test2(i32 %A) {	; 0 % X = 0, we don't need to preserve traps
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: ret i32 0
 	%B = srem i32 0, %A
 	ret i32 %B
 }
 
 define i32 @test3(i32 %A) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 7
 ; CHECK-NEXT: ret i32 [[AND]]
 	%B = urem i32 %A, 8
@@ -26,7 +26,7 @@ define i32 @test3(i32 %A) {
 }
 
 define i1 @test3a(i32 %A) {
-; CHECK: @test3a
+; CHECK-LABEL: @test3a(
 ; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 7
 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0
 ; CHECK-NEXT: ret i1 [[CMP]]
@@ -36,7 +36,7 @@ define i1 @test3a(i32 %A) {
 }
 
 define i32 @test4(i32 %X, i1 %C) {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: [[SEL:%.*]] = select i1 %C, i32 0, i32 7
 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SEL]], %X
 	%V = select i1 %C, i32 1, i32 8
@@ -45,7 +45,7 @@ define i32 @test4(i32 %X, i1 %C) {
 }
 
 define i32 @test5(i32 %X, i8 %B) {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 %B to i32
 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 32, [[ZEXT]]
 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], -1
@@ -58,14 +58,14 @@ define i32 @test5(i32 %X, i8 %B) {
 }
 
 define i32 @test6(i32 %A) {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: ret i32 undef
 	%B = srem i32 %A, 0	;; undef
 	ret i32 %B
 }
 
 define i32 @test7(i32 %A) {
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NEXT: ret i32 0
 	%B = mul i32 %A, 8
 	%C = srem i32 %B, 4
@@ -73,7 +73,7 @@ define i32 @test7(i32 %A) {
 }
 
 define i32 @test8(i32 %A) {
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK-NEXT: ret i32 0
 	%B = shl i32 %A, 4
 	%C = srem i32 %B, 8
@@ -81,7 +81,7 @@ define i32 @test8(i32 %A) {
 }
 
 define i32 @test9(i32 %A) {
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NEXT: ret i32 0
 	%B = mul i32 %A, 64
 	%C = urem i32 %B, 32
@@ -89,7 +89,7 @@ define i32 @test9(i32 %A) {
 }
 
 define i32 @test10(i8 %c) {
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK-NEXT: ret i32 0
 	%tmp.1 = zext i8 %c to i32
 	%tmp.2 = mul i32 %tmp.1, 4
@@ -100,7 +100,7 @@ define i32 @test10(i8 %c) {
 }
 
 define i32 @test11(i32 %i) {
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK-NEXT: ret i32 0
 	%tmp.1 = and i32 %i, -2
 	%tmp.3 = mul i32 %tmp.1, 2
@@ -109,7 +109,7 @@ define i32 @test11(i32 %i) {
 }
 
 define i32 @test12(i32 %i) {
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK-NEXT: ret i32 0
 	%tmp.1 = and i32 %i, -4
 	%tmp.5 = srem i32 %tmp.1, 2
@@ -117,14 +117,14 @@ define i32 @test12(i32 %i) {
 }
 
 define i32 @test13(i32 %i) {
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK-NEXT: ret i32 0
 	%x = srem i32 %i, %i
 	ret i32 %x
 }
 
 define i64 @test14(i64 %x, i32 %y) {
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, %y
 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[SHL]] to i64
 ; CHECK-NEXT: [[ADD:%.*]] = add i64 [[ZEXT]], -1
@@ -137,7 +137,7 @@ define i64 @test14(i64 %x, i32 %y) {
 }
 
 define i64 @test15(i32 %x, i32 %y) {
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, %y
 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], -1
 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], %x
@@ -151,7 +151,7 @@ define i64 @test15(i32 %x, i32 %y) {
 }
 
 define i32 @test16(i32 %x, i32 %y) {
-; CHECK: @test16
+; CHECK-LABEL: @test16(
 ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 %y, 11
 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], 4
 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[AND]], 3
@@ -163,3 +163,44 @@ define i32 @test16(i32 %x, i32 %y) {
 	%rem = urem i32 %x, %add
 	ret i32 %rem
 }
+
+define i32 @test17(i32 %X) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT: icmp ne i32 %X, 1
+; CHECK-NEXT: zext i1
+; CHECK-NEXT: ret
+  %A = urem i32 1, %X
+  ret i32 %A
+}
+
+define i32 @test18(i16 %x, i32 %y) {
+; CHECK: @test18
+; CHECK-NEXT: [[AND:%.*]] = and i16 %x, 4
+; CHECK-NEXT: [[EXT:%.*]] = zext i16 [[AND]] to i32
+; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw i32 [[EXT]], 3
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[SHL]], 63
+; CHECK-NEXT: [[REM:%.*]] = and i32 [[XOR]], %y
+; CHECK-NEXT: ret i32 [[REM]]
+	%1 = and i16 %x, 4
+	%2 = icmp ne i16 %1, 0
+	%3 = select i1 %2, i32 32, i32 64
+	%4 = urem i32 %y, %3
+	ret i32 %4
+}
+
+define i32 @test19(i32 %x, i32 %y) {
+; CHECK: @test19
+; CHECK-NEXT: [[SHL1:%.*]] = shl i32 1, %x
+; CHECK-NEXT: [[SHL2:%.*]] = shl i32 1, %y
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL1]], [[SHL2]]
+; CHECK-NEXT: [[ADD:%.*]] = add i32 [[AND]], [[SHL1]]
+; CHECK-NEXT: [[SUB:%.*]] = add i32 [[ADD]], -1
+; CHECK-NEXT: [[REM:%.*]] = and i32 [[SUB]], %y
+; CHECK-NEXT: ret i32 [[REM]]
+	%A = shl i32 1, %x
+	%B = shl i32 1, %y
+	%C = and i32 %A, %B
+	%D = add i32 %C, %A
+	%E = urem i32 %y, %D
+	ret i32 %E
+}
diff --git a/test/Transforms/InstCombine/select-crash.ll b/test/Transforms/InstCombine/select-crash.ll
index 946ea2b..77446cd 100644
--- a/test/Transforms/InstCombine/select-crash.ll
+++ b/test/Transforms/InstCombine/select-crash.ll
@@ -21,7 +21,7 @@ entry:
 
 ; PR10180: same crash, but with vectors
 define <4 x float> @foo(i1 %b, <4 x float> %x, <4 x float> %y, <4 x float> %z) {
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK: fsub <4 x float>
 ; CHECK: select
 ; CHECK: fadd <4 x float>
@@ -31,7 +31,7 @@ define <4 x float> @foo(i1 %b, <4 x float> %x, <4 x float> %y, <4 x float> %z) {
   ret <4 x float> %sel
 }
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 define i32 @test3(i1 %bool, i32 %a) {
 entry:
   %cond = or i1 %bool, true
diff --git a/test/Transforms/InstCombine/select.ll b/test/Transforms/InstCombine/select.ll
index c72a6f7..c7809f7 100644
--- a/test/Transforms/InstCombine/select.ll
+++ b/test/Transforms/InstCombine/select.ll
@@ -6,14 +6,14 @@
 define i32 @test1(i32 %A, i32 %B) {
         %C = select i1 false, i32 %A, i32 %B            
         ret i32 %C
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret i32 %B
 }
 
 define i32 @test2(i32 %A, i32 %B) {
         %C = select i1 true, i32 %A, i32 %B             
         ret i32 %C
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: ret i32 %A
 }
 
@@ -22,7 +22,7 @@ define i32 @test3(i1 %C, i32 %I) {
         ; V = I
         %V = select i1 %C, i32 %I, i32 %I               
         ret i32 %V
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: ret i32 %I
 }
 
@@ -30,7 +30,7 @@ define i1 @test4(i1 %C) {
         ; V = C
         %V = select i1 %C, i1 true, i1 false            
         ret i1 %V
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: ret i1 %C
 }
 
@@ -38,7 +38,7 @@ define i1 @test5(i1 %C) {
         ; V = !C
         %V = select i1 %C, i1 false, i1 true            
         ret i1 %V
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: xor i1 %C, true
 ; CHECK: ret i1
 }
@@ -47,7 +47,7 @@ define i32 @test6(i1 %C) {
         ; V = cast C to int
         %V = select i1 %C, i32 1, i32 0         
         ret i32 %V
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: %V = zext i1 %C to i32
 ; CHECK: ret i32 %V
 }
@@ -56,7 +56,7 @@ define i1 @test7(i1 %C, i1 %X) {
         ; R = or C, X       
         %R = select i1 %C, i1 true, i1 %X               
         ret i1 %R
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: %R = or i1 %C, %X
 ; CHECK: ret i1 %R
 }
@@ -65,7 +65,7 @@ define i1 @test8(i1 %C, i1 %X) {
         ; R = and C, X
         %R = select i1 %C, i1 %X, i1 false              
         ret i1 %R
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: %R = and i1 %C, %X
 ; CHECK: ret i1 %R
 }
@@ -74,7 +74,7 @@ define i1 @test9(i1 %C, i1 %X) {
         ; R = and !C, X
         %R = select i1 %C, i1 false, i1 %X              
         ret i1 %R
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK: xor i1 %C, true
 ; CHECK: %R = and i1
 ; CHECK: ret i1 %R
@@ -84,7 +84,7 @@ define i1 @test10(i1 %C, i1 %X) {
         ; R = or !C, X
         %R = select i1 %C, i1 %X, i1 true               
         ret i1 %R
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK: xor i1 %C, true
 ; CHECK: %R = or i1
 ; CHECK: ret i1 %R
@@ -94,7 +94,7 @@ define i32 @test11(i32 %a) {
         %C = icmp eq i32 %a, 0          
         %R = select i1 %C, i32 0, i32 1         
         ret i32 %R
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK: icmp ne i32 %a, 0
 ; CHECK: %R = zext i1
 ; CHECK: ret i32 %R
@@ -104,7 +104,7 @@ define i32 @test12(i1 %cond, i32 %a) {
         %b = or i32 %a, 1               
         %c = select i1 %cond, i32 %b, i32 %a            
         ret i32 %c
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK: %b = zext i1 %cond to i32
 ; CHECK: %c = or i32 %b, %a
 ; CHECK: ret i32 %c
@@ -114,7 +114,7 @@ define i32 @test12a(i1 %cond, i32 %a) {
         %b = ashr i32 %a, 1             
         %c = select i1 %cond, i32 %b, i32 %a            
         ret i32 %c
-; CHECK: @test12a
+; CHECK-LABEL: @test12a(
 ; CHECK: %b = zext i1 %cond to i32
 ; CHECK: %c = ashr i32 %a, %b
 ; CHECK: ret i32 %c
@@ -124,7 +124,7 @@ define i32 @test12b(i1 %cond, i32 %a) {
         %b = ashr i32 %a, 1             
         %c = select i1 %cond, i32 %a, i32 %b            
         ret i32 %c
-; CHECK: @test12b
+; CHECK-LABEL: @test12b(
 ; CHECK: zext i1 %cond to i32
 ; CHECK: %b = xor i32
 ; CHECK: %c = ashr i32 %a, %b
@@ -135,7 +135,7 @@ define i32 @test13(i32 %a, i32 %b) {
         %C = icmp eq i32 %a, %b         
         %V = select i1 %C, i32 %a, i32 %b               
         ret i32 %V
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK: ret i32 %b
 }
 
@@ -143,7 +143,7 @@ define i32 @test13a(i32 %a, i32 %b) {
         %C = icmp ne i32 %a, %b         
         %V = select i1 %C, i32 %a, i32 %b               
         ret i32 %V
-; CHECK: @test13a
+; CHECK-LABEL: @test13a(
 ; CHECK: ret i32 %a
 }
 
@@ -151,7 +151,7 @@ define i32 @test13b(i32 %a, i32 %b) {
         %C = icmp eq i32 %a, %b         
         %V = select i1 %C, i32 %b, i32 %a               
         ret i32 %V
-; CHECK: @test13b
+; CHECK-LABEL: @test13b(
 ; CHECK: ret i32 %a
 }
 
@@ -160,7 +160,7 @@ define i1 @test14a(i1 %C, i32 %X) {
         ; (X < 1) | !C
         %R = icmp slt i32 %V, 1         
         ret i1 %R
-; CHECK: @test14a
+; CHECK-LABEL: @test14a(
 ; CHECK: icmp slt i32 %X, 1
 ; CHECK: xor i1 %C, true
 ; CHECK: or i1
@@ -172,7 +172,7 @@ define i1 @test14b(i1 %C, i32 %X) {
         ; (X < 1) | C
         %R = icmp slt i32 %V, 1         
         ret i1 %R
-; CHECK: @test14b
+; CHECK-LABEL: @test14b(
 ; CHECK: icmp slt i32 %X, 1
 ; CHECK: or i1
 ; CHECK: ret i1 %R
@@ -184,7 +184,7 @@ define i32 @test15a(i32 %X) {
         %t2 = icmp eq i32 %t1, 0                
         %t3 = select i1 %t2, i32 0, i32 16              
         ret i32 %t3
-; CHECK: @test15a
+; CHECK-LABEL: @test15a(
 ; CHECK: %t1 = and i32 %X, 16
 ; CHECK: ret i32 %t1
 }
@@ -195,7 +195,7 @@ define i32 @test15b(i32 %X) {
         %t2 = icmp eq i32 %t1, 0                
         %t3 = select i1 %t2, i32 32, i32 0              
         ret i32 %t3
-; CHECK: @test15b
+; CHECK-LABEL: @test15b(
 ; CHECK: %t1 = and i32 %X, 32
 ; CHECK: xor i32 %t1, 32
 ; CHECK: ret i32
@@ -207,7 +207,7 @@ define i32 @test15c(i32 %X) {
         %t2 = icmp eq i32 %t1, 16               
         %t3 = select i1 %t2, i32 16, i32 0              
         ret i32 %t3
-; CHECK: @test15c
+; CHECK-LABEL: @test15c(
 ; CHECK: %t1 = and i32 %X, 16
 ; CHECK: ret i32 %t1
 }
@@ -218,7 +218,7 @@ define i32 @test15d(i32 %X) {
         %t2 = icmp ne i32 %t1, 0                
         %t3 = select i1 %t2, i32 16, i32 0              
         ret i32 %t3
-; CHECK: @test15d
+; CHECK-LABEL: @test15d(
 ; CHECK: %t1 = and i32 %X, 16
 ; CHECK: ret i32 %t1
 }
@@ -229,7 +229,7 @@ define i32 @test15e(i32 %X) {
         %t2 = icmp ne i32 %t1, 0
         %t3 = select i1 %t2, i32 256, i32 0
         ret i32 %t3
-; CHECK: @test15e
+; CHECK-LABEL: @test15e(
 ; CHECK: %t1 = shl i32 %X, 1
 ; CHECK: and i32 %t1, 256
 ; CHECK: ret i32
@@ -241,7 +241,7 @@ define i32 @test15f(i32 %X) {
         %t2 = icmp ne i32 %t1, 0
         %t3 = select i1 %t2, i32 0, i32 256
         ret i32 %t3
-; CHECK: @test15f
+; CHECK-LABEL: @test15f(
 ; CHECK: %t1 = shl i32 %X, 1
 ; CHECK: and i32 %t1, 256
 ; CHECK: xor i32 %{{.*}}, 256
@@ -254,7 +254,7 @@ define i32 @test15g(i32 %X) {
         %t2 = icmp ne i32 %t1, 0
         %t3 = select i1 %t2, i32 -1, i32 -9
         ret i32 %t3
-; CHECK: @test15g
+; CHECK-LABEL: @test15g(
 ; CHECK-NEXT: %1 = or i32 %X, -9
 ; CHECK-NEXT: ret i32 %1
 }
@@ -265,7 +265,7 @@ define i32 @test15h(i32 %X) {
         %t2 = icmp ne i32 %t1, 0
         %t3 = select i1 %t2, i32 -9, i32 -1
         ret i32 %t3
-; CHECK: @test15h
+; CHECK-LABEL: @test15h(
 ; CHECK-NEXT: %1 = or i32 %X, -9
 ; CHECK-NEXT: %2 = xor i32 %1, 8
 ; CHECK-NEXT: ret i32 %2
@@ -277,7 +277,7 @@ define i32 @test15i(i32 %X) {
         %t2 = icmp ne i32 %t1, 0
         %t3 = select i1 %t2, i32 577, i32 1089
         ret i32 %t3
-; CHECK: @test15i
+; CHECK-LABEL: @test15i(
 ; CHECK-NEXT: %t1 = shl i32 %X, 8
 ; CHECK-NEXT: %1 = and i32 %t1, 512
 ; CHECK-NEXT: %2 = xor i32 %1, 512
@@ -291,7 +291,7 @@ define i32 @test15j(i32 %X) {
         %t2 = icmp ne i32 %t1, 0
         %t3 = select i1 %t2, i32 1089, i32 577
         ret i32 %t3
-; CHECK: @test15j
+; CHECK-LABEL: @test15j(
 ; CHECK-NEXT: %t1 = shl i32 %X, 8
 ; CHECK-NEXT: %1 = and i32 %t1, 512
 ; CHECK-NEXT: %2 = add i32 %1, 577
@@ -302,7 +302,7 @@ define i32 @test16(i1 %C, i32* %P) {
         %P2 = select i1 %C, i32* %P, i32* null          
         %V = load i32* %P2              
         ret i32 %V
-; CHECK: @test16
+; CHECK-LABEL: @test16(
 ; CHECK-NEXT: %V = load i32* %P
 ; CHECK: ret i32 %V
 }
@@ -311,7 +311,7 @@ define i1 @test17(i32* %X, i1 %C) {
         %R = select i1 %C, i32* %X, i32* null           
         %RV = icmp eq i32* %R, null             
         ret i1 %RV
-; CHECK: @test17
+; CHECK-LABEL: @test17(
 ; CHECK: icmp eq i32* %X, null
 ; CHECK: xor i1 %C, true
 ; CHECK: %RV = or i1
@@ -322,7 +322,7 @@ define i32 @test18(i32 %X, i32 %Y, i1 %C) {
         %R = select i1 %C, i32 %X, i32 0                
         %V = sdiv i32 %Y, %R            
         ret i32 %V
-; CHECK: @test18
+; CHECK-LABEL: @test18(
 ; CHECK: %V = sdiv i32 %Y, %X
 ; CHECK: ret i32 %V
 }
@@ -331,7 +331,7 @@ define i32 @test19(i32 %x) {
         %tmp = icmp ugt i32 %x, 2147483647              
         %retval = select i1 %tmp, i32 -1, i32 0         
         ret i32 %retval
-; CHECK: @test19
+; CHECK-LABEL: @test19(
 ; CHECK-NEXT: ashr i32 %x, 31
 ; CHECK-NEXT: ret i32 
 }
@@ -340,7 +340,7 @@ define i32 @test20(i32 %x) {
         %tmp = icmp slt i32 %x, 0               
         %retval = select i1 %tmp, i32 -1, i32 0         
         ret i32 %retval
-; CHECK: @test20
+; CHECK-LABEL: @test20(
 ; CHECK-NEXT: ashr i32 %x, 31
 ; CHECK-NEXT: ret i32 
 }
@@ -349,7 +349,7 @@ define i64 @test21(i32 %x) {
         %tmp = icmp slt i32 %x, 0               
         %retval = select i1 %tmp, i64 -1, i64 0         
         ret i64 %retval
-; CHECK: @test21
+; CHECK-LABEL: @test21(
 ; CHECK-NEXT: ashr i32 %x, 31
 ; CHECK-NEXT: sext i32 
 ; CHECK-NEXT: ret i64
@@ -359,7 +359,7 @@ define i16 @test22(i32 %x) {
         %tmp = icmp slt i32 %x, 0               
         %retval = select i1 %tmp, i16 -1, i16 0         
         ret i16 %retval
-; CHECK: @test22
+; CHECK-LABEL: @test22(
 ; CHECK-NEXT: ashr i32 %x, 31
 ; CHECK-NEXT: trunc i32 
 ; CHECK-NEXT: ret i16
@@ -368,7 +368,7 @@ define i16 @test22(i32 %x) {
 define i1 @test23(i1 %a, i1 %b) {
         %c = select i1 %a, i1 %b, i1 %a         
         ret i1 %c
-; CHECK: @test23
+; CHECK-LABEL: @test23(
 ; CHECK-NEXT: %c = and i1 %a, %b
 ; CHECK-NEXT: ret i1 %c
 }
@@ -376,7 +376,7 @@ define i1 @test23(i1 %a, i1 %b) {
 define i1 @test24(i1 %a, i1 %b) {
         %c = select i1 %a, i1 %a, i1 %b         
         ret i1 %c
-; CHECK: @test24
+; CHECK-LABEL: @test24(
 ; CHECK-NEXT: %c = or i1 %a, %b
 ; CHECK-NEXT: ret i1 %c
 }
@@ -390,7 +390,7 @@ ret:
   %a = phi i1 [true, %jump], [false, %entry]
   %b = select i1 %a, i32 10, i32 20
   ret i32 %b
-; CHECK: @test25
+; CHECK-LABEL: @test25(
 ; CHECK: %a = phi i32 [ 10, %jump ], [ 20, %entry ]
 ; CHECK-NEXT: ret i32 %a
 }
@@ -405,7 +405,7 @@ ret:
   %a = phi i1 [true, %jump], [%c, %entry]
   %b = select i1 %a, i32 10, i32 20
   ret i32 %b
-; CHECK: @test26
+; CHECK-LABEL: @test26(
 ; CHECK: %a = phi i32 [ 10, %jump ], [ 20, %entry ]
 ; CHECK-NEXT: ret i32 %a
 }
@@ -419,7 +419,7 @@ ret:
   %a = phi i1 [true, %jump], [false, %entry]
   %b = select i1 %a, i32 %A, i32 %B
   ret i32 %b
-; CHECK: @test27
+; CHECK-LABEL: @test27(
 ; CHECK: %a = phi i32 [ %A, %jump ], [ %B, %entry ]
 ; CHECK-NEXT: ret i32 %a
 }
@@ -434,7 +434,7 @@ ret:
   %a = phi i1 [true, %jump], [false, %entry]
   %b = select i1 %a, i32 %A, i32 %c
   ret i32 %b
-; CHECK: @test28
+; CHECK-LABEL: @test28(
 ; CHECK: %a = phi i32 [ %A, %jump ], [ %B, %entry ]
 ; CHECK-NEXT: ret i32 %a
 }
@@ -452,7 +452,7 @@ ret:
 next:
   %b = select i1 %a, i32 %A, i32 %c
   ret i32 %b
-; CHECK: @test29
+; CHECK-LABEL: @test29(
 ; CHECK: %a = phi i32 [ %A, %jump ], [ %B, %entry ]
 ; CHECK: ret i32 %a
 }
@@ -466,7 +466,7 @@ define i32 @test30(i32 %x, i32 %y) {
   %cmp5 = icmp sgt i32 %cond, %x
   %retval = select i1 %cmp5, i32 %cond, i32 %x
   ret i32 %retval
-; CHECK: @test30
+; CHECK-LABEL: @test30(
 ; CHECK: ret i32 %cond
 }
 
@@ -477,7 +477,7 @@ define i32 @test31(i32 %x, i32 %y) {
   %cmp5 = icmp ugt i32 %cond, %x
   %retval = select i1 %cmp5, i32 %cond, i32 %x
   ret i32 %retval
-; CHECK: @test31
+; CHECK-LABEL: @test31(
 ; CHECK: ret i32 %cond
 }
 
@@ -488,7 +488,7 @@ define i32 @test32(i32 %x, i32 %y) {
   %cmp5 = icmp sgt i32 %cond, %x
   %retval = select i1 %cmp5, i32 %x, i32 %cond
   ret i32 %retval
-; CHECK: @test32
+; CHECK-LABEL: @test32(
 ; CHECK: ret i32 %cond
 }
 
@@ -499,7 +499,7 @@ define i32 @test33(i32 %x, i32 %y) {
   %cmp5 = icmp sgt i32 %cond, %x
   %retval = select i1 %cmp5, i32 %cond, i32 %x
   ret i32 %retval
-; CHECK: @test33
+; CHECK-LABEL: @test33(
 ; CHECK: ret i32 %x
 }
 
@@ -510,7 +510,7 @@ define i32 @test34(i32 %x, i32 %y) {
   %cmp5 = icmp sgt i32 %cond, %x
   %retval = select i1 %cmp5, i32 %x, i32 %cond
   ret i32 %retval
-; CHECK: @test34
+; CHECK-LABEL: @test34(
 ; CHECK: ret i32 %x
 }
 
@@ -518,7 +518,7 @@ define i32 @test35(i32 %x) {
   %cmp = icmp sge i32 %x, 0
   %cond = select i1 %cmp, i32 60, i32 100
   ret i32 %cond
-; CHECK: @test35
+; CHECK-LABEL: @test35(
 ; CHECK: ashr i32 %x, 31
 ; CHECK: and i32 {{.*}}, 40
 ; CHECK: add i32 {{.*}}, 60
@@ -529,7 +529,7 @@ define i32 @test36(i32 %x) {
   %cmp = icmp slt i32 %x, 0
   %cond = select i1 %cmp, i32 60, i32 100
   ret i32 %cond
-; CHECK: @test36
+; CHECK-LABEL: @test36(
 ; CHECK: ashr i32 %x, 31
 ; CHECK: and i32 {{.*}}, -40
 ; CHECK: add i32 {{.*}}, 100
@@ -540,7 +540,7 @@ define i32 @test37(i32 %x) {
   %cmp = icmp sgt i32 %x, -1
   %cond = select i1 %cmp, i32 1, i32 -1
   ret i32 %cond
-; CHECK: @test37
+; CHECK-LABEL: @test37(
 ; CHECK: ashr i32 %x, 31
 ; CHECK: or i32 {{.*}}, 1
 ; CHECK: ret
@@ -552,7 +552,7 @@ define i1 @test38(i1 %cond) {
   %ptr = select i1 %cond, i32* %zero, i32* %one
   %isnull = icmp eq i32* %ptr, null
   ret i1 %isnull
-; CHECK: @test38
+; CHECK-LABEL: @test38(
 ; CHECK: ret i1 false
 }
 
@@ -560,7 +560,7 @@ define i1 @test39(i1 %cond, double %x) {
   %s = select i1 %cond, double %x, double 0x7FF0000000000000 ; RHS = +infty
   %cmp = fcmp ule double %x, %s
   ret i1 %cmp
-; CHECK: @test39
+; CHECK-LABEL: @test39(
 ; CHECK: ret i1 true
 }
 
@@ -571,7 +571,7 @@ define i1 @test40(i1 %cond) {
   %s = select i1 %cond, i32* %a, i32* %b
   %r = icmp eq i32* %s, %c
   ret i1 %r
-; CHECK: @test40
+; CHECK-LABEL: @test40(
 ; CHECK: ret i1 false
 }
 
@@ -580,7 +580,7 @@ define i32 @test41(i1 %cond, i32 %x, i32 %y) {
   %s = select i1 %cond, i32 %y, i32 %z
   %r = and i32 %x, %s
   ret i32 %r
-; CHECK: @test41
+; CHECK-LABEL: @test41(
 ; CHECK-NEXT: and i32 %x, %y
 ; CHECK-NEXT: ret i32
 }
@@ -590,7 +590,7 @@ define i32 @test42(i32 %x, i32 %y) {
   %cond = icmp eq i32 %x, 0
   %c = select i1 %cond, i32 %b, i32 %y
   ret i32 %c
-; CHECK: @test42
+; CHECK-LABEL: @test42(
 ; CHECK-NEXT: %cond = icmp eq i32 %x, 0
 ; CHECK-NEXT: %b = sext i1 %cond to i32
 ; CHECK-NEXT: %c = add i32 %b, %y
@@ -602,7 +602,7 @@ define i64 @test43(i32 %a) nounwind {
 	%is_a_nonnegative = icmp sgt i32 %a, -1
 	%max = select i1 %is_a_nonnegative, i64 %a_ext, i64 0
 	ret i64 %max
-; CHECK: @test43
+; CHECK-LABEL: @test43(
 ; CHECK-NEXT: %a_ext = sext i32 %a to i64
 ; CHECK-NEXT: %is_a_nonnegative = icmp slt i64 %a_ext, 0
 ; CHECK-NEXT: %max = select i1 %is_a_nonnegative, i64 0, i64 %a_ext
@@ -614,7 +614,7 @@ define i64 @test44(i32 %a) nounwind {
 	%is_a_nonpositive = icmp slt i32 %a, 1
 	%min = select i1 %is_a_nonpositive, i64 %a_ext, i64 0
 	ret i64 %min
-; CHECK: @test44
+; CHECK-LABEL: @test44(
 ; CHECK-NEXT: %a_ext = sext i32 %a to i64
 ; CHECK-NEXT: %is_a_nonpositive = icmp sgt i64 %a_ext, 0
 ; CHECK-NEXT: %min = select i1 %is_a_nonpositive, i64 0, i64 %a_ext
@@ -625,7 +625,7 @@ define i64 @test45(i32 %a) nounwind {
 	%is_a_nonnegative = icmp ugt i32 %a, 2
 	%max = select i1 %is_a_nonnegative, i64 %a_ext, i64 3
 	ret i64 %max
-; CHECK: @test45
+; CHECK-LABEL: @test45(
 ; CHECK-NEXT: %a_ext = zext i32 %a to i64
 ; CHECK-NEXT: %is_a_nonnegative = icmp ult i64 %a_ext, 3
 ; CHECK-NEXT: %max = select i1 %is_a_nonnegative, i64 3, i64 %a_ext
@@ -637,7 +637,7 @@ define i64 @test46(i32 %a) nounwind {
 	%is_a_nonpositive = icmp ult i32 %a, 3
 	%min = select i1 %is_a_nonpositive, i64 %a_ext, i64 2
 	ret i64 %min
-; CHECK: @test46
+; CHECK-LABEL: @test46(
 ; CHECK-NEXT: %a_ext = zext i32 %a to i64
 ; CHECK-NEXT: %is_a_nonpositive = icmp ugt i64 %a_ext, 2
 ; CHECK-NEXT: %min = select i1 %is_a_nonpositive, i64 2, i64 %a_ext
@@ -648,7 +648,7 @@ define i64 @test47(i32 %a) nounwind {
 	%is_a_nonnegative = icmp ugt i32 %a, 2
 	%max = select i1 %is_a_nonnegative, i64 %a_ext, i64 3
 	ret i64 %max
-; CHECK: @test47
+; CHECK-LABEL: @test47(
 ; CHECK-NEXT: %a_ext = sext i32 %a to i64
 ; CHECK-NEXT: %is_a_nonnegative = icmp ult i64 %a_ext, 3
 ; CHECK-NEXT: %max = select i1 %is_a_nonnegative, i64 3, i64 %a_ext
@@ -660,7 +660,7 @@ define i64 @test48(i32 %a) nounwind {
 	%is_a_nonpositive = icmp ult i32 %a, 3
 	%min = select i1 %is_a_nonpositive, i64 %a_ext, i64 2
 	ret i64 %min
-; CHECK: @test48
+; CHECK-LABEL: @test48(
 ; CHECK-NEXT: %a_ext = sext i32 %a to i64
 ; CHECK-NEXT: %is_a_nonpositive = icmp ugt i64 %a_ext, 2
 ; CHECK-NEXT: %min = select i1 %is_a_nonpositive, i64 2, i64 %a_ext
@@ -672,7 +672,7 @@ define i64 @test49(i32 %a) nounwind {
 	%is_a_nonpositive = icmp ult i32 %a, 3
 	%min = select i1 %is_a_nonpositive, i64 2, i64 %a_ext
 	ret i64 %min
-; CHECK: @test49
+; CHECK-LABEL: @test49(
 ; CHECK-NEXT: %a_ext = sext i32 %a to i64
 ; CHECK-NEXT: %is_a_nonpositive = icmp ugt i64 %a_ext, 2
 ; CHECK-NEXT: %min = select i1 %is_a_nonpositive, i64 %a_ext, i64 2
@@ -683,7 +683,7 @@ define i64 @test50(i32 %a) nounwind {
 	%a_ext = sext i32 %a to i64
 	%min = select i1 %is_a_nonpositive, i64 2, i64 %a_ext
 	ret i64 %min
-; CHECK: @test50
+; CHECK-LABEL: @test50(
 ; CHECK-NEXT: %a_ext = sext i32 %a to i64
 ; CHECK-NEXT: %is_a_nonpositive = icmp ugt i64 %a_ext, 2
 ; CHECK-NEXT: %min = select i1 %is_a_nonpositive, i64 %a_ext, i64 2
@@ -695,7 +695,7 @@ define i64 @test50(i32 %a) nounwind {
 ; This select instruction can't be eliminated because trying to do so would
 ; change the number of vector elements. This used to assert.
 define i48 @test51(<3 x i1> %icmp, <3 x i16> %tmp) {
-; CHECK: @test51
+; CHECK-LABEL: @test51(
   %select = select <3 x i1> %icmp, <3 x i16> zeroinitializer, <3 x i16> %tmp
 ; CHECK: select <3 x i1>
   %tmp2 = bitcast <3 x i16> %select to i48
@@ -705,7 +705,7 @@ define i48 @test51(<3 x i1> %icmp, <3 x i16> %tmp) {
 ; PR8575
 
 define i32 @test52(i32 %n, i32 %m) nounwind {
-; CHECK: @test52
+; CHECK-LABEL: @test52(
   %cmp = icmp sgt i32 %n, %m
   %. = select i1 %cmp, i32 1, i32 3
   %add = add nsw i32 %., 3
@@ -720,7 +720,7 @@ define i32 @test53(i32 %x) nounwind {
   %cmp = icmp eq i32 %and, %x
   %sel = select i1 %cmp, i32 2, i32 1
   ret i32 %sel
-; CHECK: @test53
+; CHECK-LABEL: @test53(
 ; CHECK: select i1 %cmp
 ; CHECK: ret
 }
@@ -730,7 +730,7 @@ define i32 @test54(i32 %X, i32 %Y) {
   %B = icmp eq i32 %A, 0
   %C = select i1 %B, i32 %A, i32 1
   ret i32 %C
-; CHECK: @test54
+; CHECK-LABEL: @test54(
 ; CHECK-NOT: ashr
 ; CHECK-NOT: select
 ; CHECK: icmp ne i32 %X, 0
@@ -743,7 +743,7 @@ define i1 @test55(i1 %X, i32 %Y, i32 %Z) {
   %B = select i1 %X, i32 %Y, i32 %A
   %C = icmp eq i32 %B, 0
   ret i1 %C
-; CHECK: @test55
+; CHECK-LABEL: @test55(
 ; CHECK-NOT: ashr
 ; CHECK-NOT: select
 ; CHECK: icmp eq
@@ -755,7 +755,7 @@ define i32 @test56(i16 %x) nounwind {
   %conv = zext i16 %x to i32
   %cond = select i1 %tobool, i32 0, i32 %conv
   ret i32 %cond
-; CHECK: @test56
+; CHECK-LABEL: @test56(
 ; CHECK-NEXT: zext
 ; CHECK-NEXT: ret
 }
@@ -765,7 +765,7 @@ define i32 @test57(i32 %x, i32 %y) nounwind {
   %tobool = icmp eq i32 %x, 0
   %.and = select i1 %tobool, i32 0, i32 %and
   ret i32 %.and
-; CHECK: @test57
+; CHECK-LABEL: @test57(
 ; CHECK-NEXT: and i32 %x, %y
 ; CHECK-NEXT: ret
 }
@@ -775,7 +775,7 @@ define i32 @test58(i16 %x) nounwind {
   %conv = zext i16 %x to i32
   %cond = select i1 %tobool, i32 %conv, i32 1
   ret i32 %cond
-; CHECK: @test58
+; CHECK-LABEL: @test58(
 ; CHECK-NEXT: zext
 ; CHECK-NEXT: ret
 }
@@ -785,7 +785,7 @@ define i32 @test59(i32 %x, i32 %y) nounwind {
   %tobool = icmp ne i32 %x, %y
   %.and = select i1 %tobool, i32 %and, i32 %y
   ret i32 %.and
-; CHECK: @test59
+; CHECK-LABEL: @test59(
 ; CHECK-NEXT: and i32 %x, %y
 ; CHECK-NEXT: ret
 }
@@ -796,7 +796,7 @@ define i1 @test60(i32 %x, i1* %y) nounwind {
   %cmp1 = icmp slt i32 %x, 1
   %sel = select i1 %cmp, i1 %load, i1 %cmp1
   ret i1 %sel
-; CHECK: @test60
+; CHECK-LABEL: @test60(
 ; CHECK: select
 }
 
@@ -806,7 +806,7 @@ define i32 @test61(i32* %ptr) {
   %B = icmp eq i32* %ptr, @glbl
   %C = select i1 %B, i32 %A, i32 10
   ret i32 %C
-; CHECK: @test61
+; CHECK-LABEL: @test61(
 ; CHECK: ret i32 10
 }
 
@@ -814,7 +814,7 @@ define i1 @test62(i1 %A, i1 %B) {
         %not = xor i1 %A, true
         %C = select i1 %A, i1 %not, i1 %B             
         ret i1 %C
-; CHECK: @test62
+; CHECK-LABEL: @test62(
 ; CHECK: %not = xor i1 %A, true
 ; CHECK: %C = and i1 %not, %B
 ; CHECK: ret i1 %C
@@ -824,7 +824,7 @@ define i1 @test63(i1 %A, i1 %B) {
         %not = xor i1 %A, true
         %C = select i1 %A, i1 %B, i1 %not         
         ret i1 %C
-; CHECK: @test63
+; CHECK-LABEL: @test63(
 ; CHECK: %not = xor i1 %A, true
 ; CHECK: %C = or i1 %B, %not
 ; CHECK: ret i1 %C
@@ -860,11 +860,11 @@ cond.end17:
 
 while.body:
   br label %while.body
-; CHECK: @test64
+; CHECK-LABEL: @test64(
 ; CHECK-NOT: select
 }
 
-; CHECK: @select_icmp_eq_and_1_0_or_2
+; CHECK-LABEL: @select_icmp_eq_and_1_0_or_2(
 ; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 %x, 1
 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], 2
 ; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y
@@ -877,7 +877,7 @@ define i32 @select_icmp_eq_and_1_0_or_2(i32 %x, i32 %y) {
   ret i32 %select
 }
 
-; CHECK: @select_icmp_eq_and_32_0_or_8
+; CHECK-LABEL: @select_icmp_eq_and_32_0_or_8(
 ; CHECK-NEXT: [[LSHR:%[a-z0-9]+]] = lshr i32 %x, 2
 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[LSHR]], 8
 ; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y
@@ -890,7 +890,7 @@ define i32 @select_icmp_eq_and_32_0_or_8(i32 %x, i32 %y) {
   ret i32 %select
 }
 
-; CHECK: @select_icmp_ne_0_and_4096_or_4096
+; CHECK-LABEL: @select_icmp_ne_0_and_4096_or_4096(
 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 4096
 ; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 4096
 ; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y
@@ -903,7 +903,7 @@ define i32 @select_icmp_ne_0_and_4096_or_4096(i32 %x, i32 %y) {
   ret i32 %select
 }
 
-; CHECK: @select_icmp_eq_and_4096_0_or_4096
+; CHECK-LABEL: @select_icmp_eq_and_4096_0_or_4096(
 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 4096
 ; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y
 ; CHECK-NEXT: ret i32 [[OR]]
@@ -915,7 +915,7 @@ define i32 @select_icmp_eq_and_4096_0_or_4096(i32 %x, i32 %y) {
   ret i32 %select
 }
 
-; CHECK: @select_icmp_eq_0_and_1_or_1
+; CHECK-LABEL: @select_icmp_eq_0_and_1_or_1(
 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i64 %x, 1
 ; CHECK-NEXT: [[ZEXT:%[a-z0-9]+]] = trunc i64 [[AND]] to i32
 ; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y
@@ -928,7 +928,7 @@ define i32 @select_icmp_eq_0_and_1_or_1(i64 %x, i32 %y) {
   ret i32 %select
 }
 
-; CHECK: @select_icmp_ne_0_and_4096_or_32
+; CHECK-LABEL: @select_icmp_ne_0_and_4096_or_32(
 ; CHECK-NEXT: [[LSHR:%[a-z0-9]+]] = lshr i32 %x, 7
 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[LSHR]], 32
 ; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 32
@@ -942,7 +942,7 @@ define i32 @select_icmp_ne_0_and_4096_or_32(i32 %x, i32 %y) {
   ret i32 %select
 }
 
-; CHECK: @select_icmp_ne_0_and_32_or_4096
+; CHECK-LABEL: @select_icmp_ne_0_and_32_or_4096(
 ; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 %x, 7
 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], 4096
 ; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 4096
@@ -956,7 +956,7 @@ define i32 @select_icmp_ne_0_and_32_or_4096(i32 %x, i32 %y) {
   ret i32 %select
 }
 
-; CHECK: @select_icmp_ne_0_and_1073741824_or_8
+; CHECK-LABEL: @select_icmp_ne_0_and_1073741824_or_8(
 ; CHECK-NEXT: [[LSHR:%[a-z0-9]+]] = lshr i32 %x, 27
 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[LSHR]], 8
 ; CHECK-NEXT: [[TRUNC:%[a-z0-9]+]] = trunc i32 [[AND]] to i8
@@ -971,7 +971,7 @@ define i8 @select_icmp_ne_0_and_1073741824_or_8(i32 %x, i8 %y) {
   ret i8 %select
 }
 
-; CHECK: @select_icmp_ne_0_and_8_or_1073741824
+; CHECK-LABEL: @select_icmp_ne_0_and_8_or_1073741824(
 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i8 %x, 8
 ; CHECK-NEXT: [[ZEXT:%[a-z0-9]+]] = zext i8 [[AND]] to i32
 ; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl nuw nsw i32 [[ZEXT]], 27
@@ -985,3 +985,39 @@ define i32 @select_icmp_ne_0_and_8_or_1073741824(i8 %x, i32 %y) {
   %select = select i1 %cmp, i32 %y, i32 %or
   ret i32 %select
 }
+
+define i32 @test65(i64 %x) {
+  %1 = and i64 %x, 16
+  %2 = icmp ne i64 %1, 0
+  %3 = select i1 %2, i32 40, i32 42
+  ret i32 %3
+
+; CHECK-LABEL: @test65(
+; CHECK: and i64 %x, 16
+; CHECK: trunc i64 %1 to i32
+; CHECK: lshr exact i32 %2, 3
+; CHECK: xor i32 %3, 42
+}
+
+define i32 @test66(i64 %x) {
+  %1 = and i64 %x, 4294967296
+  %2 = icmp ne i64 %1, 0
+  %3 = select i1 %2, i32 40, i32 42
+  ret i32 %3
+
+; CHECK-LABEL: @test66(
+; CHECK: select
+}
+
+define i32 @test67(i16 %x) {
+  %1 = and i16 %x, 4
+  %2 = icmp ne i16 %1, 0
+  %3 = select i1 %2, i32 40, i32 42
+  ret i32 %3
+
+; CHECK-LABEL: @test67(
+; CHECK: and i16 %x, 4
+; CHECK: zext i16 %1 to i32
+; CHECK: lshr exact i32 %2, 1
+; CHECK: xor i32 %3, 42
+}
diff --git a/test/Transforms/InstCombine/sext.ll b/test/Transforms/InstCombine/sext.ll
index 968f37c..b8dfe22 100644
--- a/test/Transforms/InstCombine/sext.ll
+++ b/test/Transforms/InstCombine/sext.ll
@@ -11,7 +11,7 @@ define i64 @test1(i32 %x) {
   %s = sext i32 %t to i64
   ret i64 %s
   
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: zext i32 %t
 }
 
@@ -20,7 +20,7 @@ define i64 @test2(i32 %x) {
   %s = sext i32 %t to i64
   ret i64 %s
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: zext i32 %t
 }
 
@@ -29,7 +29,7 @@ define i64 @test3(i32 %x) {
   %s = sext i32 %t to i64
   ret i64 %s
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: zext i32 %t
 }
 
@@ -38,7 +38,7 @@ define i64 @test4(i32 %x) {
   %s = sext i32 %t to i64
   ret i64 %s
 
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: zext i32 %t
 }
 
@@ -46,7 +46,7 @@ define i64 @test5(i32 %x) {
   %t = urem i32 %x, 30000
   %s = sext i32 %t to i64
   ret i64 %s
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: zext i32 %t
 }
 
@@ -55,7 +55,7 @@ define i64 @test6(i32 %x) {
   %t = mul i32 %u, 3
   %s = sext i32 %t to i64
   ret i64 %s
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: zext i32 %t
 }
 
@@ -64,7 +64,7 @@ define i64 @test7(i32 %x) {
   %u = sub i32 20000, %t
   %s = sext i32 %u to i64
   ret i64 %s
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: zext i32 %u to i64
 }
 
@@ -74,7 +74,7 @@ define i32 @test8(i8 %a, i32 %f, i1 %p, i32* %z) {
   %s = trunc i32 %e to i16
   %n = sext i16 %s to i32
   ret i32 %n
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: %d = lshr i32 %f, 24
 ; CHECK: %n = select i1 %p, i32 %d, i32 0
 ; CHECK: ret i32 %n
@@ -92,7 +92,7 @@ F:
 	%V = phi i32 [%t2, %T], [42, %entry]
 	%W = trunc i32 %V to i16
 	ret i16 %W
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK: T:
 ; CHECK-NEXT: br label %F
 ; CHECK: F:
@@ -108,7 +108,7 @@ entry:
         %a = ashr i8 %tmp16, 6 
         %b = sext i8 %a to i32 
         ret i32 %b
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK:  shl i32 %i, 30
 ; CHECK-NEXT: ashr exact i32
 ; CHECK-NEXT: ret i32
@@ -120,7 +120,7 @@ define void @test11(<2 x i16> %srcA, <2 x i16> %srcB, <2 x i16>* %dst) {
   %tmask = ashr <2 x i16> %sext, <i16 15, i16 15> 
   store <2 x i16> %tmask, <2 x i16>* %dst
   ret void                                                                                                                      
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK-NEXT: icmp eq
 ; CHECK-NEXT: sext <2 x i1>
 ; CHECK-NEXT: store <2 x i16>
@@ -132,7 +132,7 @@ define i64 @test12(i32 %x) nounwind {
   %sub = sub nsw i32 0, %shr
   %conv = sext i32 %sub to i64
   ret i64 %conv
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK: sext
 ; CHECK: ret
 }
@@ -142,7 +142,7 @@ define i32 @test13(i32 %x) nounwind {
   %cmp = icmp eq i32 %and, 0
   %ext = sext i1 %cmp to i32
   ret i32 %ext
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK-NEXT: %and = lshr i32 %x, 3
 ; CHECK-NEXT: %1 = and i32 %and, 1
 ; CHECK-NEXT: %sext = add i32 %1, -1
@@ -154,7 +154,7 @@ define i32 @test14(i16 %x) nounwind {
   %cmp = icmp ne i16 %and, 16
   %ext = sext i1 %cmp to i32
   ret i32 %ext
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK-NEXT: %and = lshr i16 %x, 4
 ; CHECK-NEXT: %1 = and i16 %and, 1
 ; CHECK-NEXT: %sext = add i16 %1, -1
@@ -167,7 +167,7 @@ define i32 @test15(i32 %x) nounwind {
   %cmp = icmp ne i32 %and, 0
   %ext = sext i1 %cmp to i32
   ret i32 %ext
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 ; CHECK-NEXT: %1 = shl i32 %x, 27
 ; CHECK-NEXT: %sext = ashr i32 %1, 31
 ; CHECK-NEXT: ret i32 %sext
@@ -178,7 +178,7 @@ define i32 @test16(i16 %x) nounwind {
   %cmp = icmp eq i16 %and, 8
   %ext = sext i1 %cmp to i32
   ret i32 %ext
-; CHECK: @test16
+; CHECK-LABEL: @test16(
 ; CHECK-NEXT: %1 = shl i16 %x, 12
 ; CHECK-NEXT: %sext = ashr i16 %1, 15
 ; CHECK-NEXT: %ext = sext i16 %sext to i32
@@ -189,7 +189,7 @@ define i32 @test17(i1 %x) nounwind {
   %c1 = sext i1 %x to i32
   %c2 = sub i32 0, %c1
   ret i32 %c2
-; CHECK: @test17
+; CHECK-LABEL: @test17(
 ; CHECK-NEXT: [[TEST17:%.*]] = zext i1 %x to i32
 ; CHECK-NEXT: ret i32 [[TEST17]]
 }
diff --git a/test/Transforms/InstCombine/shift-sra.ll b/test/Transforms/InstCombine/shift-sra.ll
index a578bbe..7523550 100644
--- a/test/Transforms/InstCombine/shift-sra.ll
+++ b/test/Transforms/InstCombine/shift-sra.ll
@@ -7,7 +7,7 @@ define i32 @test1(i32 %X, i8 %A) {
         %Y = ashr i32 %X, %shift.upgrd.1                ; <i32> [#uses=1]
         %Z = and i32 %Y, 1              ; <i32> [#uses=1]
         ret i32 %Z
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: lshr i32 %X, %shift.upgrd.1 
 }
 
@@ -16,7 +16,7 @@ define i32 @test2(i8 %tmp) {
         %tmp4 = add i32 %tmp3, 7                ; <i32> [#uses=1]
         %tmp5 = ashr i32 %tmp4, 3               ; <i32> [#uses=1]
         ret i32 %tmp5
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: lshr i32 %tmp4, 3
 }
 
@@ -33,7 +33,7 @@ C:
   %S = ashr i64 %P, 12
   ret i64 %S
   
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: %P = phi i64
 ; CHECK-NEXT: ret i64 %P
 }
@@ -52,7 +52,7 @@ C:
   %S = ashr i64 %R, 12
   ret i64 %S
   
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: %P = phi i64
 ; CHECK-NEXT: ret i64 %P
 }
@@ -70,7 +70,7 @@ D:
   %P = phi i32 [0, %A], [0, %B], [%Y, %C] 
   %S = ashr i32 %P, 16
   ret i32 %S
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: %P = phi i32
 ; CHECK-NEXT: ashr i32 %P, 16
 E:
diff --git a/test/Transforms/InstCombine/shift.ll b/test/Transforms/InstCombine/shift.ll
index 41f8aa9..0bdab13 100644
--- a/test/Transforms/InstCombine/shift.ll
+++ b/test/Transforms/InstCombine/shift.ll
@@ -3,14 +3,14 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i32 @test1(i32 %A) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret i32 %A
         %B = shl i32 %A, 0              ; <i32> [#uses=1]
         ret i32 %B
 }
 
 define i32 @test2(i8 %A) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: ret i32 0
         %shift.upgrd.1 = zext i8 %A to i32              ; <i32> [#uses=1]
         %B = shl i32 0, %shift.upgrd.1          ; <i32> [#uses=1]
@@ -18,14 +18,14 @@ define i32 @test2(i8 %A) {
 }
 
 define i32 @test3(i32 %A) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: ret i32 %A
         %B = ashr i32 %A, 0             ; <i32> [#uses=1]
         ret i32 %B
 }
 
 define i32 @test4(i8 %A) {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: ret i32 0
         %shift.upgrd.2 = zext i8 %A to i32              ; <i32> [#uses=1]
         %B = ashr i32 0, %shift.upgrd.2         ; <i32> [#uses=1]
@@ -34,35 +34,35 @@ define i32 @test4(i8 %A) {
 
 
 define i32 @test5(i32 %A) {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: ret i32 undef
         %B = lshr i32 %A, 32  ;; shift all bits out 
         ret i32 %B
 }
 
 define i32 @test5a(i32 %A) {
-; CHECK: @test5a
+; CHECK-LABEL: @test5a(
 ; CHECK: ret i32 undef
         %B = shl i32 %A, 32     ;; shift all bits out 
         ret i32 %B
 }
 
 define i32 @test5b() {
-; CHECK: @test5b
+; CHECK-LABEL: @test5b(
 ; CHECK: ret i32 -1
         %B = ashr i32 undef, 2  ;; top two bits must be equal, so not undef
         ret i32 %B
 }
 
 define i32 @test5b2(i32 %A) {
-; CHECK: @test5b2
+; CHECK-LABEL: @test5b2(
 ; CHECK: ret i32 -1
         %B = ashr i32 undef, %A  ;; top %A bits must be equal, so not undef
         ret i32 %B
 }
 
 define i32 @test6(i32 %A) {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: mul i32 %A, 6
 ; CHECK-NEXT: ret i32
         %B = shl i32 %A, 1      ;; convert to an mul instruction
@@ -71,7 +71,7 @@ define i32 @test6(i32 %A) {
 }
 
 define i32 @test6a(i32 %A) {
-; CHECK: @test6a
+; CHECK-LABEL: @test6a(
 ; CHECK-NEXT: mul i32 %A, 6
 ; CHECK-NEXT: ret i32
         %B = mul i32 %A, 3
@@ -80,7 +80,7 @@ define i32 @test6a(i32 %A) {
 }
 
 define i32 @test7(i8 %A) {
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NEXT: ret i32 -1
         %shift.upgrd.3 = zext i8 %A to i32 
         %B = ashr i32 -1, %shift.upgrd.3  ;; Always equal to -1
@@ -89,7 +89,7 @@ define i32 @test7(i8 %A) {
 
 ;; (A << 5) << 3 === A << 8 == 0
 define i8 @test8(i8 %A) {
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: ret i8 0
         %B = shl i8 %A, 5               ; <i8> [#uses=1]
         %C = shl i8 %B, 3               ; <i8> [#uses=1]
@@ -98,7 +98,7 @@ define i8 @test8(i8 %A) {
 
 ;; (A << 7) >> 7 === A & 1
 define i8 @test9(i8 %A) {
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NEXT: and i8 %A, 1
 ; CHECK-NEXT: ret i8
         %B = shl i8 %A, 7               ; <i8> [#uses=1]
@@ -110,7 +110,7 @@ define i8 @test9(i8 %A) {
 ;; (A >> 7) << 7 === A & 128
 ;; The shl may be valuable to scalar evolution.
 define i8 @test10(i8 %A) {
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK-NEXT: and i8 %A, -128
 ; CHECK-NEXT: ret i8
         %B = lshr i8 %A, 7              ; <i8> [#uses=1]
@@ -120,7 +120,7 @@ define i8 @test10(i8 %A) {
 
 ;; Allow the simplification when the lshr shift is exact.
 define i8 @test10a(i8 %A) {
-; CHECK: @test10a
+; CHECK-LABEL: @test10a(
 ; CHECK-NEXT: ret i8 %A
         %B = lshr exact i8 %A, 7
         %C = shl i8 %B, 7
@@ -131,7 +131,7 @@ define i8 @test10a(i8 %A) {
 ;; (A >> 3) << 4 === (A & 0x1F) << 1
 ;; The shl may be valuable to scalar evolution.
 define i8 @test11(i8 %A) {
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK: shl i8
 ; CHECK-NEXT: ret i8
         %a = mul i8 %A, 3               ; <i8> [#uses=1]
@@ -142,7 +142,7 @@ define i8 @test11(i8 %A) {
 
 ;; Allow the simplification in InstCombine when the lshr shift is exact.
 define i8 @test11a(i8 %A) {
-; CHECK: @test11a
+; CHECK-LABEL: @test11a(
 ; CHECK-NEXT: mul i8 %A, 6
 ; CHECK-NEXT: ret i8
         %a = mul i8 %A, 3
@@ -154,7 +154,7 @@ define i8 @test11a(i8 %A) {
 ;; This is deferred to DAGCombine unless %B is single-use.
 ;; (A >> 8) << 8 === A & -256
 define i32 @test12(i32 %A) {
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK-NEXT: and i32 %A, -256
 ; CHECK-NEXT: ret i32
         %B = ashr i32 %A, 8             ; <i32> [#uses=1]
@@ -166,7 +166,7 @@ define i32 @test12(i32 %A) {
 ;; (A >> 3) << 4 === (A & -8) * 2
 ;; The shl may be valuable to scalar evolution.
 define i8 @test13(i8 %A) {
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK: shl i8
 ; CHECK-NEXT: ret i8
         %a = mul i8 %A, 3               ; <i8> [#uses=1]
@@ -176,7 +176,7 @@ define i8 @test13(i8 %A) {
 }
 
 define i8 @test13a(i8 %A) {
-; CHECK: @test13a
+; CHECK-LABEL: @test13a(
 ; CHECK-NEXT: mul i8 %A, 6
 ; CHECK-NEXT: ret i8
         %a = mul i8 %A, 3
@@ -187,7 +187,7 @@ define i8 @test13a(i8 %A) {
 
 ;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4)
 define i32 @test14(i32 %A) {
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK-NEXT: %B = and i32 %A, -19760
 ; CHECK-NEXT: or i32 %B, 19744
 ; CHECK-NEXT: ret i32
@@ -199,7 +199,7 @@ define i32 @test14(i32 %A) {
 
 ;; D = ((B | 1234) << 4) === ((B << 4)|(1234 << 4)
 define i32 @test14a(i32 %A) {
-; CHECK: @test14a
+; CHECK-LABEL: @test14a(
 ; CHECK-NEXT: and i32 %A, 77
 ; CHECK-NEXT: ret i32
         %B = shl i32 %A, 4              ; <i32> [#uses=1]
@@ -209,7 +209,7 @@ define i32 @test14a(i32 %A) {
 }
 
 define i32 @test15(i1 %C) {
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 ; CHECK-NEXT: select i1 %C, i32 12, i32 4
 ; CHECK-NEXT: ret i32
         %A = select i1 %C, i32 3, i32 1         ; <i32> [#uses=1]
@@ -218,7 +218,7 @@ define i32 @test15(i1 %C) {
 }
 
 define i32 @test15a(i1 %C) {
-; CHECK: @test15a
+; CHECK-LABEL: @test15a(
 ; CHECK-NEXT: select i1 %C, i32 512, i32 128
 ; CHECK-NEXT: ret i32
         %A = select i1 %C, i8 3, i8 1           ; <i8> [#uses=1]
@@ -228,7 +228,7 @@ define i32 @test15a(i1 %C) {
 }
 
 define i1 @test16(i32 %X) {
-; CHECK: @test16
+; CHECK-LABEL: @test16(
 ; CHECK-NEXT: and i32 %X, 16
 ; CHECK-NEXT: icmp ne i32
 ; CHECK-NEXT: ret i1
@@ -239,7 +239,7 @@ define i1 @test16(i32 %X) {
 }
 
 define i1 @test17(i32 %A) {
-; CHECK: @test17
+; CHECK-LABEL: @test17(
 ; CHECK-NEXT: and i32 %A, -8
 ; CHECK-NEXT: icmp eq i32
 ; CHECK-NEXT: ret i1
@@ -250,7 +250,7 @@ define i1 @test17(i32 %A) {
 
 
 define i1 @test18(i8 %A) {
-; CHECK: @test18
+; CHECK-LABEL: @test18(
 ; CHECK: ret i1 false
 
         %B = lshr i8 %A, 7              ; <i8> [#uses=1]
@@ -260,7 +260,7 @@ define i1 @test18(i8 %A) {
 }
 
 define i1 @test19(i32 %A) {
-; CHECK: @test19
+; CHECK-LABEL: @test19(
 ; CHECK-NEXT: icmp ult i32 %A, 4
 ; CHECK-NEXT: ret i1
         %B = ashr i32 %A, 2             ; <i32> [#uses=1]
@@ -271,18 +271,17 @@ define i1 @test19(i32 %A) {
 
 
 define i1 @test19a(i32 %A) {
-; CHECK: @test19a
-; CHECK-NEXT: and i32 %A, -4
-; CHECK-NEXT: icmp eq i32
+; CHECK-LABEL: @test19a(
+; CHECK-NEXT: icmp ugt i32 %A, -5
 ; CHECK-NEXT: ret i1
         %B = ashr i32 %A, 2             ; <i32> [#uses=1]
-        ;; (X & -4) == -4
+        ;; X >u ~4
         %C = icmp eq i32 %B, -1         ; <i1> [#uses=1]
         ret i1 %C
 }
 
 define i1 @test20(i8 %A) {
-; CHECK: @test20
+; CHECK-LABEL: @test20(
 ; CHECK: ret i1 false
         %B = ashr i8 %A, 7              ; <i8> [#uses=1]
         ;; false
@@ -291,7 +290,7 @@ define i1 @test20(i8 %A) {
 }
 
 define i1 @test21(i8 %A) {
-; CHECK: @test21
+; CHECK-LABEL: @test21(
 ; CHECK-NEXT: and i8 %A, 15
 ; CHECK-NEXT: icmp eq i8
 ; CHECK-NEXT: ret i1
@@ -301,7 +300,7 @@ define i1 @test21(i8 %A) {
 }
 
 define i1 @test22(i8 %A) {
-; CHECK: @test22
+; CHECK-LABEL: @test22(
 ; CHECK-NEXT: and i8 %A, 15
 ; CHECK-NEXT: icmp eq i8
 ; CHECK-NEXT: ret i1
@@ -311,7 +310,7 @@ define i1 @test22(i8 %A) {
 }
 
 define i8 @test23(i32 %A) {
-; CHECK: @test23
+; CHECK-LABEL: @test23(
 ; CHECK-NEXT: trunc i32 %A to i8
 ; CHECK-NEXT: ret i8
 
@@ -323,7 +322,7 @@ define i8 @test23(i32 %A) {
 }
 
 define i8 @test24(i8 %X) {
-; CHECK: @test24
+; CHECK-LABEL: @test24(
 ; CHECK-NEXT: and i8 %X, 3
 ; CHECK-NEXT: ret i8
         %Y = and i8 %X, -5              ; <i8> [#uses=1]
@@ -333,7 +332,7 @@ define i8 @test24(i8 %X) {
 }
 
 define i32 @test25(i32 %tmp.2, i32 %AA) {
-; CHECK: @test25
+; CHECK-LABEL: @test25(
 ; CHECK-NEXT: and i32 %tmp.2, -131072
 ; CHECK-NEXT: add i32 %{{[^,]*}}, %AA
 ; CHECK-NEXT: and i32 %{{[^,]*}}, -131072
@@ -347,7 +346,7 @@ define i32 @test25(i32 %tmp.2, i32 %AA) {
 
 ;; handle casts between shifts.
 define i32 @test26(i32 %A) {
-; CHECK: @test26
+; CHECK-LABEL: @test26(
 ; CHECK-NEXT: and i32 %A, -2
 ; CHECK-NEXT: ret i32
         %B = lshr i32 %A, 1             ; <i32> [#uses=1]
@@ -358,7 +357,7 @@ define i32 @test26(i32 %A) {
 
 
 define i1 @test27(i32 %x) nounwind {
-; CHECK: @test27
+; CHECK-LABEL: @test27(
 ; CHECK-NEXT: and i32 %x, 8
 ; CHECK-NEXT: icmp ne i32
 ; CHECK-NEXT: ret i1
@@ -369,7 +368,7 @@ define i1 @test27(i32 %x) nounwind {
  
 define i8 @test28(i8 %x) {
 entry:
-; CHECK: @test28
+; CHECK-LABEL: @test28(
 ; CHECK:     icmp slt i8 %x, 0
 ; CHECK-NEXT:     br i1 
 	%tmp1 = lshr i8 %x, 7
@@ -386,7 +385,7 @@ bb2:
 define i8 @test28a(i8 %x, i8 %y) {
 entry:
 ; This shouldn't be transformed.
-; CHECK: @test28a
+; CHECK-LABEL: @test28a(
 ; CHECK:     %tmp1 = lshr i8 %x, 7
 ; CHECK:     %cond1 = icmp eq i8 %tmp1, 0
 ; CHECK:     br i1 %cond1, label %bb2, label %bb1
@@ -407,7 +406,7 @@ entry:
 	%tmp917 = trunc i64 %tmp916 to i32
 	%tmp10 = lshr i32 %tmp917, 31
 	ret i32 %tmp10
-; CHECK: @test29
+; CHECK-LABEL: @test29(
 ; CHECK:  %tmp916 = lshr i64 %d18, 63
 ; CHECK:  %tmp10 = trunc i64 %tmp916 to i32
 }
@@ -418,7 +417,7 @@ define i32 @test30(i32 %A, i32 %B, i32 %C) {
 	%Y = shl i32 %B, %C
 	%Z = and i32 %X, %Y
 	ret i32 %Z
-; CHECK: @test30
+; CHECK-LABEL: @test30(
 ; CHECK: %X1 = and i32 %A, %B
 ; CHECK: %Z = shl i32 %X1, %C
 }
@@ -428,7 +427,7 @@ define i32 @test31(i32 %A, i32 %B, i32 %C) {
 	%Y = lshr i32 %B, %C
 	%Z = or i32 %X, %Y
 	ret i32 %Z
-; CHECK: @test31
+; CHECK-LABEL: @test31(
 ; CHECK: %X1 = or i32 %A, %B
 ; CHECK: %Z = lshr i32 %X1, %C
 }
@@ -438,7 +437,7 @@ define i32 @test32(i32 %A, i32 %B, i32 %C) {
 	%Y = ashr i32 %B, %C
 	%Z = xor i32 %X, %Y
 	ret i32 %Z
-; CHECK: @test32
+; CHECK-LABEL: @test32(
 ; CHECK: %X1 = xor i32 %A, %B
 ; CHECK: %Z = ashr i32 %X1, %C
 ; CHECK: ret i32 %Z
@@ -448,7 +447,7 @@ define i1 @test33(i32 %X) {
         %tmp1 = shl i32 %X, 7
         %tmp2 = icmp slt i32 %tmp1, 0
         ret i1 %tmp2
-; CHECK: @test33
+; CHECK-LABEL: @test33(
 ; CHECK: %tmp1.mask = and i32 %X, 16777216
 ; CHECK: %tmp2 = icmp ne i32 %tmp1.mask, 0
 }
@@ -457,7 +456,7 @@ define i1 @test34(i32 %X) {
         %tmp1 = lshr i32 %X, 7
         %tmp2 = icmp slt i32 %tmp1, 0
         ret i1 %tmp2
-; CHECK: @test34
+; CHECK-LABEL: @test34(
 ; CHECK: ret i1 false
 }
 
@@ -465,7 +464,7 @@ define i1 @test35(i32 %X) {
         %tmp1 = ashr i32 %X, 7
         %tmp2 = icmp slt i32 %tmp1, 0
         ret i1 %tmp2
-; CHECK: @test35
+; CHECK-LABEL: @test35(
 ; CHECK: %tmp2 = icmp slt i32 %X, 0
 ; CHECK: ret i1 %tmp2
 }
@@ -478,7 +477,7 @@ entry:
   %tmp45 = lshr i128 %ins, 64
   ret i128 %tmp45
   
-; CHECK: @test36
+; CHECK-LABEL: @test36(
 ; CHECK:  %tmp231 = or i128 %B, %A
 ; CHECK:  %ins = and i128 %tmp231, 18446744073709551615
 ; CHECK:  ret i128 %ins
@@ -494,7 +493,7 @@ entry:
   %tmp46 = trunc i128 %tmp45 to i64
   ret i64 %tmp46
   
-; CHECK: @test37
+; CHECK-LABEL: @test37(
 ; CHECK:  %tmp23 = shl nuw nsw i128 %tmp22, 32
 ; CHECK:  %ins = or i128 %tmp23, %A
 ; CHECK:  %tmp46 = trunc i128 %ins to i64
@@ -504,14 +503,14 @@ define i32 @test38(i32 %x) nounwind readnone {
   %rem = srem i32 %x, 32
   %shl = shl i32 1, %rem
   ret i32 %shl
-; CHECK: @test38
+; CHECK-LABEL: @test38(
 ; CHECK-NEXT: and i32 %x, 31
 ; CHECK-NEXT: shl i32 1
 ; CHECK-NEXT: ret i32
 }
 
 ; <rdar://problem/8756731>
-; CHECK: @test39
+; CHECK-LABEL: @test39(
 define i8 @test39(i32 %a0) {
 entry:
   %tmp4 = trunc i32 %a0 to i8
@@ -537,7 +536,7 @@ define i32 @test40(i32 %a, i32 %b) nounwind {
   %shl2 = shl i32 %shl1, 2
   %div = udiv i32 %a, %shl2
   ret i32 %div
-; CHECK: @test40
+; CHECK-LABEL: @test40(
 ; CHECK-NEXT: add i32 %b, 2
 ; CHECK-NEXT: lshr i32 %a
 ; CHECK-NEXT: ret i32
@@ -547,7 +546,7 @@ define i32 @test41(i32 %a, i32 %b) nounwind {
   %1 = shl i32 1, %b
   %2 = shl i32 %1, 3
   ret i32 %2
-; CHECK: @test41
+; CHECK-LABEL: @test41(
 ; CHECK-NEXT: shl i32 8, %b
 ; CHECK-NEXT: ret i32
 }
@@ -556,7 +555,7 @@ define i32 @test42(i32 %a, i32 %b) nounwind {
   %div = lshr i32 4096, %b    ; must be exact otherwise we'd divide by zero
   %div2 = udiv i32 %a, %div
   ret i32 %div2
-; CHECK: @test42
+; CHECK-LABEL: @test42(
 ; CHECK-NEXT: lshr exact i32 4096, %b
 }
 
@@ -564,7 +563,7 @@ define i32 @test43(i32 %a, i32 %b) nounwind {
   %div = shl i32 4096, %b    ; must be exact otherwise we'd divide by zero
   %div2 = udiv i32 %a, %div
   ret i32 %div2
-; CHECK: @test43
+; CHECK-LABEL: @test43(
 ; CHECK-NEXT: add i32 %b, 12
 ; CHECK-NEXT: lshr
 ; CHECK-NEXT: ret
@@ -574,7 +573,7 @@ define i32 @test44(i32 %a) nounwind {
   %y = shl nuw i32 %a, 1
   %z = shl i32 %y, 4
   ret i32 %z
-; CHECK: @test44
+; CHECK-LABEL: @test44(
 ; CHECK-NEXT: %y = shl i32 %a, 5
 ; CHECK-NEXT: ret i32 %y
 }
@@ -583,7 +582,7 @@ define i32 @test45(i32 %a) nounwind {
   %y = lshr exact i32 %a, 1
   %z = lshr i32 %y, 4
   ret i32 %z
-; CHECK: @test45
+; CHECK-LABEL: @test45(
 ; CHECK-NEXT: %y = lshr i32 %a, 5
 ; CHECK-NEXT: ret i32 %y
 }
@@ -592,7 +591,7 @@ define i32 @test46(i32 %a) {
   %y = ashr exact i32 %a, 3
   %z = shl i32 %y, 1
   ret i32 %z
-; CHECK: @test46
+; CHECK-LABEL: @test46(
 ; CHECK-NEXT: %z = ashr exact i32 %a, 2
 ; CHECK-NEXT: ret i32 %z
 }
@@ -601,7 +600,7 @@ define i32 @test47(i32 %a) {
   %y = lshr exact i32 %a, 3
   %z = shl i32 %y, 1
   ret i32 %z
-; CHECK: @test47
+; CHECK-LABEL: @test47(
 ; CHECK-NEXT: %z = lshr exact i32 %a, 2
 ; CHECK-NEXT: ret i32 %z
 }
@@ -610,7 +609,7 @@ define i32 @test48(i32 %x) {
   %A = lshr exact i32 %x, 1
   %B = shl i32 %A, 3
   ret i32 %B
-; CHECK: @test48
+; CHECK-LABEL: @test48(
 ; CHECK-NEXT: %B = shl i32 %x, 2
 ; CHECK-NEXT: ret i32 %B
 }
@@ -619,7 +618,7 @@ define i32 @test49(i32 %x) {
   %A = ashr exact i32 %x, 1
   %B = shl i32 %A, 3
   ret i32 %B
-; CHECK: @test49
+; CHECK-LABEL: @test49(
 ; CHECK-NEXT: %B = shl i32 %x, 2
 ; CHECK-NEXT: ret i32 %B
 }
@@ -628,7 +627,7 @@ define i32 @test50(i32 %x) {
   %A = shl nsw i32 %x, 1
   %B = ashr i32 %A, 3
   ret i32 %B
-; CHECK: @test50
+; CHECK-LABEL: @test50(
 ; CHECK-NEXT: %B = ashr i32 %x, 2
 ; CHECK-NEXT: ret i32 %B
 }
@@ -637,7 +636,7 @@ define i32 @test51(i32 %x) {
   %A = shl nuw i32 %x, 1
   %B = lshr i32 %A, 3
   ret i32 %B
-; CHECK: @test51
+; CHECK-LABEL: @test51(
 ; CHECK-NEXT: %B = lshr i32 %x, 2
 ; CHECK-NEXT: ret i32 %B
 }
@@ -646,7 +645,7 @@ define i32 @test52(i32 %x) {
   %A = shl nsw i32 %x, 3
   %B = ashr i32 %A, 1
   ret i32 %B
-; CHECK: @test52
+; CHECK-LABEL: @test52(
 ; CHECK-NEXT: %B = shl nsw i32 %x, 2
 ; CHECK-NEXT: ret i32 %B
 }
@@ -655,7 +654,7 @@ define i32 @test53(i32 %x) {
   %A = shl nuw i32 %x, 3
   %B = lshr i32 %A, 1
   ret i32 %B
-; CHECK: @test53
+; CHECK-LABEL: @test53(
 ; CHECK-NEXT: %B = shl nuw i32 %x, 2
 ; CHECK-NEXT: ret i32 %B
 }
@@ -665,7 +664,7 @@ define i32 @test54(i32 %x) {
   %shl = shl i32 %shr2, 4
   %and = and i32 %shl, 16
   ret i32 %and
-; CHECK: @test54
+; CHECK-LABEL: @test54(
 ; CHECK: shl i32 %x, 3
 }
 
@@ -675,7 +674,7 @@ define i32 @test55(i32 %x) {
   %shl = shl i32 %shr2, 4
   %or = or i32 %shl, 8
   ret i32 %or
-; CHECK: @test55
+; CHECK-LABEL: @test55(
 ; CHECK: shl i32 %x, 3
 }
 
@@ -684,7 +683,7 @@ define i32 @test56(i32 %x) {
   %shl = shl i32 %shr2, 4
   %or = or i32 %shl, 7
   ret i32 %or
-; CHECK: @test56
+; CHECK-LABEL: @test56(
 ; CHECK: shl i32 %shr2, 4
 }
 
@@ -694,7 +693,7 @@ define i32 @test57(i32 %x) {
   %shl = shl i32 %shr, 4
   %and = and i32 %shl, 16
   ret i32 %and
-; CHECK: @test57
+; CHECK-LABEL: @test57(
 ; CHECK: shl i32 %x, 3
 }
 
@@ -703,7 +702,7 @@ define i32 @test58(i32 %x) {
   %shl = shl i32 %shr, 4
   %or = or i32 %shl, 8
   ret i32 %or
-; CHECK: @test58
+; CHECK-LABEL: @test58(
 ; CHECK: shl i32 %x, 3
 }
 
@@ -712,7 +711,7 @@ define i32 @test59(i32 %x) {
   %shl = shl i32 %shr, 4
   %or = or i32 %shl, 7
   ret i32 %or
-; CHECK: @test59
+; CHECK-LABEL: @test59(
 ; CHECK: %shl = shl i32 %shr1, 4
 }
 
@@ -722,7 +721,7 @@ define i32 @test60(i32 %x) {
   %shl = shl i32 %shr, 1
   %or = or i32 %shl, 1
   ret i32 %or
-; CHECK: @test60
+; CHECK-LABEL: @test60(
 ; CHECK: ashr i32 %x, 3
 }
 
@@ -732,7 +731,7 @@ define i32 @test61(i32 %x) {
   %shl = shl i32 %shr, 1
   %or = or i32 %shl, 2
   ret i32 %or
-; CHECK: @test61
+; CHECK-LABEL: @test61(
 ; CHECK: ashr i32 %x, 4
 }
 
@@ -742,6 +741,6 @@ define i32 @test62(i32 %x) {
   %shl = shl i32 %shr, 1
   %or = or i32 %shl, 1
   ret i32 %or
-; CHECK: @test62
+; CHECK-LABEL: @test62(
 ; CHECK: ashr exact i32 %x, 3
 }
diff --git a/test/Transforms/InstCombine/sign-test-and-or.ll b/test/Transforms/InstCombine/sign-test-and-or.ll
index a6066d8..95ed9b9 100644
--- a/test/Transforms/InstCombine/sign-test-and-or.ll
+++ b/test/Transforms/InstCombine/sign-test-and-or.ll
@@ -8,7 +8,7 @@ define void @test1(i32 %a, i32 %b) nounwind {
   %or.cond = or i1 %1, %2
   br i1 %or.cond, label %if.then, label %if.end
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: %1 = or i32 %a, %b
 ; CHECK-NEXT: %2 = icmp slt i32 %1, 0
 ; CHECK-NEXT: br
@@ -27,7 +27,7 @@ define void @test2(i32 %a, i32 %b) nounwind {
   %or.cond = or i1 %1, %2
   br i1 %or.cond, label %if.then, label %if.end
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: %1 = and i32 %a, %b
 ; CHECK-NEXT: %2 = icmp sgt i32 %1, -1
 ; CHECK-NEXT: br
@@ -46,7 +46,7 @@ define void @test3(i32 %a, i32 %b) nounwind {
   %or.cond = and i1 %1, %2
   br i1 %or.cond, label %if.then, label %if.end
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: %1 = and i32 %a, %b
 ; CHECK-NEXT: %2 = icmp slt i32 %1, 0
 ; CHECK-NEXT: br
@@ -65,7 +65,7 @@ define void @test4(i32 %a, i32 %b) nounwind {
   %or.cond = and i1 %1, %2
   br i1 %or.cond, label %if.then, label %if.end
 
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: %1 = or i32 %a, %b
 ; CHECK-NEXT: %2 = icmp sgt i32 %1, -1
 ; CHECK-NEXT: br
@@ -85,7 +85,7 @@ define void @test5(i32 %a) nounwind {
   %or.cond = and i1 %1, %2
   br i1 %or.cond, label %if.then, label %if.end
 
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NEXT: %1 = and i32 %a, -2013265920
 ; CHECK-NEXT: %2 = icmp eq i32 %1, 0
 ; CHECK-NEXT: br i1 %2, label %if.then, label %if.end
@@ -105,7 +105,7 @@ define void @test6(i32 %a) nounwind {
   %or.cond = and i1 %1, %2
   br i1 %or.cond, label %if.then, label %if.end
 
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: %1 = and i32 %a, -2013265920
 ; CHECK-NEXT: %2 = icmp eq i32 %1, 0
 ; CHECK-NEXT: br i1 %2, label %if.then, label %if.end
@@ -125,7 +125,7 @@ define void @test7(i32 %a) nounwind {
   %or.cond = or i1 %1, %2
   br i1 %or.cond, label %if.then, label %if.end
 
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NEXT: %1 = and i32 %a, -2013265920
 ; CHECK-NEXT: %2 = icmp eq i32 %1, 0
 ; CHECK-NEXT: br i1 %2, label %if.end, label %if.the
@@ -145,7 +145,7 @@ define void @test8(i32 %a) nounwind {
   %or.cond = or i1 %1, %2
   br i1 %or.cond, label %if.then, label %if.end
 
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK-NEXT: %1 = and i32 %a, -2013265920
 ; CHECK-NEXT: %2 = icmp eq i32 %1, 0
 ; CHECK-NEXT: br i1 %2, label %if.end, label %if.the
@@ -165,7 +165,7 @@ define void @test9(i32 %a) nounwind {
   %or.cond = and i1 %2, %3
   br i1 %or.cond, label %if.then, label %if.end
 
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NEXT: %1 = and i32 %a, -1073741824
 ; CHECK-NEXT: %2 = icmp eq i32 %1, 1073741824
 ; CHECK-NEXT: br i1 %2, label %if.then, label %if.end
diff --git a/test/Transforms/InstCombine/signext.ll b/test/Transforms/InstCombine/signext.ll
index 5ed1cd5..d700497 100644
--- a/test/Transforms/InstCombine/signext.ll
+++ b/test/Transforms/InstCombine/signext.ll
@@ -7,7 +7,7 @@ define i32 @test1(i32 %x) {
         %tmp.2 = xor i32 %tmp.1, -32768         ; <i32> [#uses=1]
         %tmp.3 = add i32 %tmp.2, 32768          ; <i32> [#uses=1]
         ret i32 %tmp.3
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %sext = shl i32 %x, 16
 ; CHECK: %tmp.3 = ashr exact i32 %sext, 16
 ; CHECK: ret i32 %tmp.3
@@ -18,7 +18,7 @@ define i32 @test2(i32 %x) {
         %tmp.2 = xor i32 %tmp.1, 32768          ; <i32> [#uses=1]
         %tmp.3 = add i32 %tmp.2, -32768         ; <i32> [#uses=1]
         ret i32 %tmp.3
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: %sext = shl i32 %x, 16
 ; CHECK: %tmp.3 = ashr exact i32 %sext, 16
 ; CHECK: ret i32 %tmp.3
@@ -29,7 +29,7 @@ define i32 @test3(i16 %P) {
         %tmp.4 = xor i32 %tmp.1, 32768          ; <i32> [#uses=1]
         %tmp.5 = add i32 %tmp.4, -32768         ; <i32> [#uses=1]
         ret i32 %tmp.5
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: %tmp.5 = sext i16 %P to i32
 ; CHECK: ret i32 %tmp.5
 }
@@ -39,7 +39,7 @@ define i32 @test4(i16 %P) {
         %tmp.4 = xor i32 %tmp.1, 32768          ; <i32> [#uses=1]
         %tmp.5 = add i32 %tmp.4, -32768         ; <i32> [#uses=1]
         ret i32 %tmp.5
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: %tmp.5 = sext i16 %P to i32
 ; CHECK: ret i32 %tmp.5
 }
@@ -49,7 +49,7 @@ define i32 @test5(i32 %x) {
         %tmp.2 = xor i32 %tmp.1, 128            ; <i32> [#uses=1]
         %tmp.3 = add i32 %tmp.2, -128           ; <i32> [#uses=1]
         ret i32 %tmp.3
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: %sext = shl i32 %x, 24
 ; CHECK: %tmp.3 = ashr exact i32 %sext, 24
 ; CHECK: ret i32 %tmp.3
@@ -59,7 +59,7 @@ define i32 @test6(i32 %x) {
         %tmp.2 = shl i32 %x, 16         ; <i32> [#uses=1]
         %tmp.4 = ashr i32 %tmp.2, 16            ; <i32> [#uses=1]
         ret i32 %tmp.4
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: %tmp.2 = shl i32 %x, 16
 ; CHECK: %tmp.4 = ashr exact i32 %tmp.2, 16
 ; CHECK: ret i32 %tmp.4
@@ -70,7 +70,7 @@ define i32 @test7(i16 %P) {
   %sext1 = shl i32 %tmp.1, 16                     ; <i32> [#uses=1]
   %tmp.5 = ashr i32 %sext1, 16                    ; <i32> [#uses=1]
   ret i32 %tmp.5
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: %tmp.5 = sext i16 %P to i32
 ; CHECK: ret i32 %tmp.5
 }
@@ -81,7 +81,7 @@ entry:
   %xor = xor i32 %shr, 67108864                   ; <i32> [#uses=1]
   %sub = add i32 %xor, -67108864                  ; <i32> [#uses=1]
   ret i32 %sub
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: %sub = ashr i32 %x, 5
 ; CHECK: ret i32 %sub
 }
diff --git a/test/Transforms/InstCombine/simplify-libcalls.ll b/test/Transforms/InstCombine/simplify-libcalls.ll
index 4f3a506..fae3e6e 100644
--- a/test/Transforms/InstCombine/simplify-libcalls.ll
+++ b/test/Transforms/InstCombine/simplify-libcalls.ll
@@ -18,7 +18,7 @@ define i8* @test1() {
         %tmp3 = tail call i8* @strchr( i8* getelementptr ([5 x i8]* @str, i32 0, i32 2), i32 103 )              ; <i8*> [#uses=1]
         ret i8* %tmp3
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret i8* getelementptr inbounds ([5 x i8]* @str, i32 0, i64 3)
 }
 
@@ -28,7 +28,7 @@ define i8* @test2() {
         %tmp3 = tail call i8* @strchr( i8* getelementptr ([8 x i8]* @str1, i32 0, i32 2), i32 0 )               ; <i8*> [#uses=1]
         ret i8* %tmp3
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: ret i8* getelementptr inbounds ([8 x i8]* @str1, i32 0, i64 7)
 }
 
@@ -37,7 +37,7 @@ entry:
         %tmp3 = tail call i8* @strchr( i8* getelementptr ([5 x i8]* @str2, i32 0, i32 1), i32 80 )              ; <i8*> [#uses=1]
         ret i8* %tmp3
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: ret i8* null
 }
 
@@ -52,7 +52,7 @@ entry:
 	%tmp6 = icmp eq i32 %tmp5, 0		; <i1> [#uses=1]
 	ret i1 %tmp6
 
-; CHECK: @PR2341
+; CHECK-LABEL: @PR2341(
 ; CHECK: i32
 }
 
@@ -65,7 +65,7 @@ entry:
 	%call = call i32 @memcmp(i8* %c0, i8* %c2, i32 1)		; <i32> [#uses=1]
 	ret i32 %call
 
-; CHECK: @PR4284
+; CHECK-LABEL: @PR4284(
 ; CHECK: ret i32 -65
 }
 
@@ -124,9 +124,21 @@ define i32 @MemCpy() {
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %target_p, i8* %hello_u_p, i32 8, i32 8, i1 false)
   ret i32 0
 
-; CHECK: @MemCpy
+; CHECK-LABEL: @MemCpy(
 ; CHECK-NOT: llvm.memcpy
 ; CHECK: ret i32 0
 }
 
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
+
+declare i32 @strcmp(i8*, i8*) #0
+
+define void @test9(i8* %x) {
+; CHECK-LABEL: @test9(
+; CHECK-NOT: strcmp
+  %y = call i32 @strcmp(i8* %x, i8* %x) #1
+  ret void
+}
+
+attributes #0 = { nobuiltin }
+attributes #1 = { builtin }
diff --git a/test/Transforms/InstCombine/sink_instruction.ll b/test/Transforms/InstCombine/sink_instruction.ll
index 5c4019a..1bbd6b7 100644
--- a/test/Transforms/InstCombine/sink_instruction.ll
+++ b/test/Transforms/InstCombine/sink_instruction.ll
@@ -4,7 +4,7 @@
 ;; arm of the 'if'.
 
 define i32 @test1(i1 %C, i32 %A, i32 %B) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 entry:
         %tmp.2 = sdiv i32 %A, %B                ; <i32> [#uses=1]
         %tmp.9 = add i32 %B, %A         ; <i32> [#uses=1]
@@ -22,7 +22,7 @@ endif:          ; preds = %entry
 
 ;; PHI use, sink divide before call.
 define i32 @test2(i32 %x) nounwind ssp {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NOT: sdiv i32
 entry:
   br label %bb
diff --git a/test/Transforms/InstCombine/sprintf-1.ll b/test/Transforms/InstCombine/sprintf-1.ll
index 9b8c8b1..6d0ab13 100644
--- a/test/Transforms/InstCombine/sprintf-1.ll
+++ b/test/Transforms/InstCombine/sprintf-1.ll
@@ -19,7 +19,7 @@ declare i32 @sprintf(i8*, i8*, ...)
 ; Check sprintf(dst, fmt) -> llvm.memcpy(str, fmt, strlen(fmt) + 1, 1).
 
 define void @test_simplify1(i8* %dst) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %fmt = getelementptr [13 x i8]* @hello_world, i32 0, i32 0
   call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt)
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* getelementptr inbounds ([13 x i8]* @hello_world, i32 0, i32 0), i32 13, i32 1, i1 false)
@@ -28,7 +28,7 @@ define void @test_simplify1(i8* %dst) {
 }
 
 define void @test_simplify2(i8* %dst) {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %fmt = getelementptr [1 x i8]* @null, i32 0, i32 0
   call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt)
 ; CHECK-NEXT: store i8 0, i8* %dst, align 1
@@ -37,7 +37,7 @@ define void @test_simplify2(i8* %dst) {
 }
 
 define void @test_simplify3(i8* %dst) {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %fmt = getelementptr [7 x i8]* @null_hello, i32 0, i32 0
   call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt)
 ; CHECK-NEXT: store i8 0, i8* %dst, align 1
@@ -48,7 +48,7 @@ define void @test_simplify3(i8* %dst) {
 ; Check sprintf(dst, "%c", chr) -> *(i8*)dst = chr; *((i8*)dst + 1) = 0.
 
 define void @test_simplify4(i8* %dst) {
-; CHECK: @test_simplify4
+; CHECK-LABEL: @test_simplify4(
   %fmt = getelementptr [3 x i8]* @percent_c, i32 0, i32 0
   call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt, i8 104)
 ; CHECK-NEXT: store i8 104, i8* %dst, align 1
@@ -61,7 +61,7 @@ define void @test_simplify4(i8* %dst) {
 ; Check sprintf(dst, "%s", str) -> llvm.memcpy(dest, str, strlen(str) + 1, 1).
 
 define void @test_simplify5(i8* %dst, i8* %str) {
-; CHECK: @test_simplify5
+; CHECK-LABEL: @test_simplify5(
   %fmt = getelementptr [3 x i8]* @percent_s, i32 0, i32 0
   call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt, i8* %str)
 ; CHECK-NEXT: [[STRLEN:%[a-z0-9]+]] = call i32 @strlen(i8* %str)
@@ -74,7 +74,7 @@ define void @test_simplify5(i8* %dst, i8* %str) {
 ; Check sprintf(dst, format, ...) -> siprintf(str, format, ...) if no floating.
 
 define void @test_simplify6(i8* %dst) {
-; CHECK-IPRINTF: @test_simplify6
+; CHECK-IPRINTF-LABEL: @test_simplify6(
   %fmt = getelementptr [3 x i8]* @percent_d, i32 0, i32 0
   call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt, i32 187)
 ; CHECK-NEXT-IPRINTF: call i32 (i8*, i8*, ...)* @siprintf(i8* %dst, i8* getelementptr inbounds ([3 x i8]* @percent_d, i32 0, i32 0), i32 187)
@@ -83,7 +83,7 @@ define void @test_simplify6(i8* %dst) {
 }
 
 define void @test_no_simplify1(i8* %dst) {
-; CHECK-IPRINTF: @test_no_simplify1
+; CHECK-IPRINTF-LABEL: @test_no_simplify1(
   %fmt = getelementptr [3 x i8]* @percent_f, i32 0, i32 0
   call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt, double 1.87)
 ; CHECK-NEXT-IPRINTF: call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* getelementptr inbounds ([3 x i8]* @percent_f, i32 0, i32 0), double 1.870000e+00)
@@ -92,7 +92,7 @@ define void @test_no_simplify1(i8* %dst) {
 }
 
 define void @test_no_simplify2(i8* %dst, i8* %fmt, double %d) {
-; CHECK: @test_no_simplify2
+; CHECK-LABEL: @test_no_simplify2(
   call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt, double %d)
 ; CHECK-NEXT: call i32 (i8*, i8*, ...)* @sprintf(i8* %dst, i8* %fmt, double %d)
   ret void
diff --git a/test/Transforms/InstCombine/sqrt.ll b/test/Transforms/InstCombine/sqrt.ll
index 440b974..650b10c 100644
--- a/test/Transforms/InstCombine/sqrt.ll
+++ b/test/Transforms/InstCombine/sqrt.ll
@@ -2,7 +2,7 @@
 
 define float @test1(float %x) nounwind readnone ssp {
 entry:
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NOT: fpext
 ; CHECK-NOT: sqrt(
 ; CHECK: sqrtf(
@@ -17,7 +17,7 @@ entry:
 ; PR8096
 define float @test2(float %x) nounwind readnone ssp {
 entry:
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NOT: fpext
 ; CHECK-NOT: sqrt(
 ; CHECK: sqrtf(
@@ -34,7 +34,7 @@ entry:
 ; use of sqrt result.
 define float @test3(float* %v) nounwind uwtable ssp {
 entry:
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: sqrt(
 ; CHECK-NOT: sqrtf(
 ; CHECK: fptrunc
diff --git a/test/Transforms/InstCombine/store.ll b/test/Transforms/InstCombine/store.ll
index 164ba76..9b666b9 100644
--- a/test/Transforms/InstCombine/store.ll
+++ b/test/Transforms/InstCombine/store.ll
@@ -5,7 +5,7 @@ define void @test1(i32* %P) {
         store i32 123, i32* undef
         store i32 124, i32* null
         ret void
-; CHECK: @test1(
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: store i32 123, i32* undef
 ; CHECK-NEXT: store i32 undef, i32* null
 ; CHECK-NEXT: ret void
@@ -16,7 +16,7 @@ define void @test2(i32* %P) {
         %Y = add i32 %X, 0              ; <i32> [#uses=1]
         store i32 %Y, i32* %P
         ret void
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: ret void
 }
 
@@ -38,7 +38,7 @@ Cond2:
 Cont:
 	%V = load i32* %A
 	ret i32 %V
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NOT: alloca
 ; CHECK: Cont:
 ; CHECK-NEXT:  %storemerge = phi i32 [ 47, %Cond2 ], [ -987654321, %Cond ]
@@ -58,7 +58,7 @@ Cond:
 Cont:
 	%V = load i32* %A
 	ret i32 %V
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NOT: alloca
 ; CHECK: Cont:
 ; CHECK-NEXT:  %storemerge = phi i32 [ -987654321, %Cond ], [ 47, %0 ]
@@ -76,7 +76,7 @@ Cond:
 
 Cont:
 	ret void
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: Cont:
 ; CHECK-NEXT:  %storemerge = phi i32
 ; CHECK-NEXT:  store i32 %storemerge, i32* %P, align 1
@@ -107,7 +107,7 @@ for.body:                                         ; preds = %for.cond
 
 for.end:                                          ; preds = %for.cond
   ret void
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: for.cond:
 ; CHECK-NEXT: phi i32 [ 42
 ; CHECK-NEXT: store i32 %storemerge, i32* %gi, align 4, !tbaa !0
diff --git a/test/Transforms/InstCombine/stpcpy-1.ll b/test/Transforms/InstCombine/stpcpy-1.ll
index 8b6bb0e..b918c9e 100644
--- a/test/Transforms/InstCombine/stpcpy-1.ll
+++ b/test/Transforms/InstCombine/stpcpy-1.ll
@@ -12,7 +12,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 declare i8* @stpcpy(i8*, i8*)
 
 define i8* @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
 
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
   %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
@@ -24,7 +24,7 @@ define i8* @test_simplify1() {
 }
 
 define i8* @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
 
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
 
@@ -35,7 +35,7 @@ define i8* @test_simplify2() {
 }
 
 define i8* @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
 
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
   %src = getelementptr [32 x i8]* @b, i32 0, i32 0
diff --git a/test/Transforms/InstCombine/stpcpy-2.ll b/test/Transforms/InstCombine/stpcpy-2.ll
index 2e92c08..6a0f753 100644
--- a/test/Transforms/InstCombine/stpcpy-2.ll
+++ b/test/Transforms/InstCombine/stpcpy-2.ll
@@ -11,7 +11,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 declare i16* @stpcpy(i8*, i8*)
 
 define void @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
 
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
   %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
diff --git a/test/Transforms/InstCombine/stpcpy_chk-1.ll b/test/Transforms/InstCombine/stpcpy_chk-1.ll
index 0560391..a6d5585 100644
--- a/test/Transforms/InstCombine/stpcpy_chk-1.ll
+++ b/test/Transforms/InstCombine/stpcpy_chk-1.ll
@@ -12,7 +12,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 ; Check cases where slen >= strlen (src).
 
 define void @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
 
@@ -22,7 +22,7 @@ define void @test_simplify1() {
 }
 
 define void @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
 
@@ -32,7 +32,7 @@ define void @test_simplify2() {
 }
 
 define void @test_simplify3() {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
 
@@ -44,7 +44,7 @@ define void @test_simplify3() {
 ; Check cases where there are no string constants.
 
 define void @test_simplify4() {
-; CHECK: @test_simplify4
+; CHECK-LABEL: @test_simplify4(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [60 x i8]* @b, i32 0, i32 0
 
@@ -56,7 +56,7 @@ define void @test_simplify4() {
 ; Check case where the string length is not constant.
 
 define i8* @test_simplify5() {
-; CHECK: @test_simplify5
+; CHECK-LABEL: @test_simplify5(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
 
@@ -70,7 +70,7 @@ define i8* @test_simplify5() {
 ; Check case where the source and destination are the same.
 
 define i8* @test_simplify6() {
-; CHECK: @test_simplify6
+; CHECK-LABEL: @test_simplify6(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
 
 ; CHECK: [[LEN:%[a-z]+]] = call i32 @strlen
@@ -83,7 +83,7 @@ define i8* @test_simplify6() {
 ; Check case where slen < strlen (src).
 
 define void @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [60 x i8]* @b, i32 0, i32 0
 
diff --git a/test/Transforms/InstCombine/stpcpy_chk-2.ll b/test/Transforms/InstCombine/stpcpy_chk-2.ll
index 46c2139..b503da9 100644
--- a/test/Transforms/InstCombine/stpcpy_chk-2.ll
+++ b/test/Transforms/InstCombine/stpcpy_chk-2.ll
@@ -9,7 +9,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 @.str = private constant [8 x i8] c"abcdefg\00"
 
 define void @test_no_simplify() {
-; CHECK: @test_no_simplify
+; CHECK-LABEL: @test_no_simplify(
   %dst = getelementptr inbounds [60 x i16]* @a, i32 0, i32 0
   %src = getelementptr inbounds [8 x i8]* @.str, i32 0, i32 0
 
diff --git a/test/Transforms/InstCombine/strcat-1.ll b/test/Transforms/InstCombine/strcat-1.ll
index 3c05d6b..131ad48 100644
--- a/test/Transforms/InstCombine/strcat-1.ll
+++ b/test/Transforms/InstCombine/strcat-1.ll
@@ -13,7 +13,7 @@ declare i8* @strcat(i8*, i8*)
 declare i32 @puts(i8*)
 
 define i32 @main() {
-; CHECK: @main
+; CHECK-LABEL: @main(
 ; CHECK-NOT: call i8* @strcat
 ; CHECK: call i32 @puts
 
diff --git a/test/Transforms/InstCombine/strcat-2.ll b/test/Transforms/InstCombine/strcat-2.ll
index 379ee74..48f8267 100644
--- a/test/Transforms/InstCombine/strcat-2.ll
+++ b/test/Transforms/InstCombine/strcat-2.ll
@@ -11,7 +11,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 declare i8* @strcat(i8*, i8*)
 
 define void @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
 ; CHECK-NOT: call i8* @strcat
 ; CHECK: ret void
 
@@ -22,7 +22,7 @@ define void @test_simplify1() {
 }
 
 define void @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
 ; CHECK-NEXT: ret void
 
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
diff --git a/test/Transforms/InstCombine/strcat-3.ll b/test/Transforms/InstCombine/strcat-3.ll
index 15aff2f..e3396df 100644
--- a/test/Transforms/InstCombine/strcat-3.ll
+++ b/test/Transforms/InstCombine/strcat-3.ll
@@ -11,7 +11,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 declare i16* @strcat(i8*, i8*)
 
 define void @test_nosimplify1() {
-; CHECK: @test_nosimplify1
+; CHECK-LABEL: @test_nosimplify1(
 ; CHECK: call i16* @strcat
 ; CHECK: ret void
 
diff --git a/test/Transforms/InstCombine/strcmp-1.ll b/test/Transforms/InstCombine/strcmp-1.ll
index 0679246..fc58ffc 100644
--- a/test/Transforms/InstCombine/strcmp-1.ll
+++ b/test/Transforms/InstCombine/strcmp-1.ll
@@ -12,7 +12,7 @@ declare i32 @strcmp(i8*, i8*)
 
 ; strcmp("", x) -> -*x
 define i32 @test1(i8* %str2) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %strcmpload = load i8* %str
 ; CHECK: %1 = zext i8 %strcmpload to i32
 ; CHECK: %2 = sub i32 0, %1
@@ -26,7 +26,7 @@ define i32 @test1(i8* %str2) {
 
 ; strcmp(x, "") -> *x
 define i32 @test2(i8* %str1) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: %strcmpload = load i8* %str
 ; CHECK: %1 = zext i8 %strcmpload to i32
 ; CHECK: ret i32 %1
@@ -38,7 +38,7 @@ define i32 @test2(i8* %str1) {
 
 ; strcmp(x, y)  -> cnst
 define i32 @test3() {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: ret i32 -1
 
   %str1 = getelementptr inbounds [5 x i8]* @hell, i32 0, i32 0
@@ -48,7 +48,7 @@ define i32 @test3() {
 }
 
 define i32 @test4() {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: ret i32 1
 
   %str1 = getelementptr inbounds [5 x i8]* @hell, i32 0, i32 0
@@ -60,7 +60,7 @@ define i32 @test4() {
 ; strcmp(x, y)   -> memcmp(x, y, <known length>)
 ; (This transform is rather difficult to trigger in a useful manner)
 define i32 @test5(i1 %b) {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: %memcmp = call i32 @memcmp(i8* getelementptr inbounds ([6 x i8]* @hello, i32 0, i32 0), i8* %str2, i32 5)
 ; CHECK: ret i32 %memcmp
 
@@ -74,7 +74,7 @@ define i32 @test5(i1 %b) {
 
 ; strcmp(x,x)  -> 0
 define i32 @test6(i8* %str) {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: ret i32 0
 
   %temp1 = call i32 @strcmp(i8* %str, i8* %str)
diff --git a/test/Transforms/InstCombine/strcmp-2.ll b/test/Transforms/InstCombine/strcmp-2.ll
index 2051896..f0ef516 100644
--- a/test/Transforms/InstCombine/strcmp-2.ll
+++ b/test/Transforms/InstCombine/strcmp-2.ll
@@ -9,7 +9,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 declare i16 @strcmp(i8*, i8*)
 
 define i16 @test_nosimplify() {
-; CHECK: @test_nosimplify
+; CHECK-LABEL: @test_nosimplify(
 ; CHECK: call i16 @strcmp
 ; CHECK: ret i16 %temp1
 
diff --git a/test/Transforms/InstCombine/strcpy-1.ll b/test/Transforms/InstCombine/strcpy-1.ll
index b6cf048..7c253f6 100644
--- a/test/Transforms/InstCombine/strcpy-1.ll
+++ b/test/Transforms/InstCombine/strcpy-1.ll
@@ -13,7 +13,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 declare i8* @strcpy(i8*, i8*)
 
 define void @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
 
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
   %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
@@ -24,7 +24,7 @@ define void @test_simplify1() {
 }
 
 define i8* @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
 
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
 
@@ -34,7 +34,7 @@ define i8* @test_simplify2() {
 }
 
 define i8* @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
 
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
   %src = getelementptr [32 x i8]* @b, i32 0, i32 0
diff --git a/test/Transforms/InstCombine/strcpy-2.ll b/test/Transforms/InstCombine/strcpy-2.ll
index 779e9fd..bad392d 100644
--- a/test/Transforms/InstCombine/strcpy-2.ll
+++ b/test/Transforms/InstCombine/strcpy-2.ll
@@ -11,7 +11,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 declare i16* @strcpy(i8*, i8*)
 
 define void @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
 
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
   %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
diff --git a/test/Transforms/InstCombine/strcpy_chk-1.ll b/test/Transforms/InstCombine/strcpy_chk-1.ll
index 3e48f4f..5b98cf8 100644
--- a/test/Transforms/InstCombine/strcpy_chk-1.ll
+++ b/test/Transforms/InstCombine/strcpy_chk-1.ll
@@ -12,7 +12,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 ; Check cases where slen >= strlen (src).
 
 define void @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
 
@@ -22,7 +22,7 @@ define void @test_simplify1() {
 }
 
 define void @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
 
@@ -32,7 +32,7 @@ define void @test_simplify2() {
 }
 
 define void @test_simplify3() {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
 
@@ -44,7 +44,7 @@ define void @test_simplify3() {
 ; Check cases where there are no string constants.
 
 define void @test_simplify4() {
-; CHECK: @test_simplify4
+; CHECK-LABEL: @test_simplify4(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [60 x i8]* @b, i32 0, i32 0
 
@@ -56,7 +56,7 @@ define void @test_simplify4() {
 ; Check case where the string length is not constant.
 
 define void @test_simplify5() {
-; CHECK: @test_simplify5
+; CHECK-LABEL: @test_simplify5(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
 
@@ -69,7 +69,7 @@ define void @test_simplify5() {
 ; Check case where the source and destination are the same.
 
 define i8* @test_simplify6() {
-; CHECK: @test_simplify6
+; CHECK-LABEL: @test_simplify6(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
 
 ; CHECK: getelementptr inbounds ([60 x i8]* @a, i32 0, i32 0)
@@ -81,7 +81,7 @@ define i8* @test_simplify6() {
 ; Check case where slen < strlen (src).
 
 define void @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [60 x i8]* @b, i32 0, i32 0
 
diff --git a/test/Transforms/InstCombine/strcpy_chk-2.ll b/test/Transforms/InstCombine/strcpy_chk-2.ll
index d76ea5d..1eff5a8 100644
--- a/test/Transforms/InstCombine/strcpy_chk-2.ll
+++ b/test/Transforms/InstCombine/strcpy_chk-2.ll
@@ -9,7 +9,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 @.str = private constant [8 x i8] c"abcdefg\00"
 
 define void @test_no_simplify() {
-; CHECK: @test_no_simplify
+; CHECK-LABEL: @test_no_simplify(
   %dst = getelementptr inbounds [60 x i16]* @a, i32 0, i32 0
   %src = getelementptr inbounds [8 x i8]* @.str, i32 0, i32 0
 
diff --git a/test/Transforms/InstCombine/strcpy_chk-64.ll b/test/Transforms/InstCombine/strcpy_chk-64.ll
index 036fcbe..31447d9 100644
--- a/test/Transforms/InstCombine/strcpy_chk-64.ll
+++ b/test/Transforms/InstCombine/strcpy_chk-64.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-apple-darwin10.0.0"
 
 define void @func(i8* %i) nounwind ssp {
-; CHECK: @func
+; CHECK-LABEL: @func(
 ; CHECK: @__strcpy_chk(i8* %arraydecay, i8* %i, i64 32)
 entry:
   %s = alloca [32 x i8], align 16
diff --git a/test/Transforms/InstCombine/strcspn-1.ll b/test/Transforms/InstCombine/strcspn-1.ll
index 60fad89..b3b52b5 100644
--- a/test/Transforms/InstCombine/strcspn-1.ll
+++ b/test/Transforms/InstCombine/strcspn-1.ll
@@ -13,7 +13,7 @@ declare i64 @strcspn(i8*, i8*)
 ; Check strcspn(s, "") -> strlen(s).
 
 define i64 @test_simplify1(i8* %str) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %pat = getelementptr [1 x i8]* @null, i32 0, i32 0
 
   %ret = call i64 @strcspn(i8* %str, i8* %pat)
@@ -25,7 +25,7 @@ define i64 @test_simplify1(i8* %str) {
 ; Check strcspn("", s) -> 0.
 
 define i64 @test_simplify2(i8* %pat) {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %str = getelementptr [1 x i8]* @null, i32 0, i32 0
 
   %ret = call i64 @strcspn(i8* %str, i8* %pat)
@@ -36,7 +36,7 @@ define i64 @test_simplify2(i8* %pat) {
 ; Check strcspn(s1, s2), where s1 and s2 are constants.
 
 define i64 @test_simplify3() {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %str = getelementptr [6 x i8]* @abcba, i32 0, i32 0
   %pat = getelementptr [4 x i8]* @abc, i32 0, i32 0
 
@@ -48,7 +48,7 @@ define i64 @test_simplify3() {
 ; Check cases that shouldn't be simplified.
 
 define i64 @test_no_simplify1(i8* %str, i8* %pat) {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
 
   %ret = call i64 @strcspn(i8* %str, i8* %pat)
 ; CHECK-NEXT: %ret = call i64 @strcspn(i8* %str, i8* %pat)
diff --git a/test/Transforms/InstCombine/strcspn-2.ll b/test/Transforms/InstCombine/strcspn-2.ll
index 4e23936..ecfa27d 100644
--- a/test/Transforms/InstCombine/strcspn-2.ll
+++ b/test/Transforms/InstCombine/strcspn-2.ll
@@ -11,7 +11,7 @@ declare double @strcspn(i8*, i8*)
 ; Check that strcspn functions with the wrong prototype aren't simplified.
 
 define double @test_no_simplify1(i8* %pat) {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %str = getelementptr [1 x i8]* @null, i32 0, i32 0
 
   %ret = call double @strcspn(i8* %str, i8* %pat)
diff --git a/test/Transforms/InstCombine/strlen-1.ll b/test/Transforms/InstCombine/strlen-1.ll
index 6d7464a..4fa5b4f 100644
--- a/test/Transforms/InstCombine/strlen-1.ll
+++ b/test/Transforms/InstCombine/strlen-1.ll
@@ -15,7 +15,7 @@ declare i32 @strlen(i8*)
 ; Check strlen(string constant) -> integer constant.
 
 define i32 @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %hello_p = getelementptr [6 x i8]* @hello, i32 0, i32 0
   %hello_l = call i32 @strlen(i8* %hello_p)
   ret i32 %hello_l
@@ -23,7 +23,7 @@ define i32 @test_simplify1() {
 }
 
 define i32 @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %null_p = getelementptr [1 x i8]* @null, i32 0, i32 0
   %null_l = call i32 @strlen(i8* %null_p)
   ret i32 %null_l
@@ -31,7 +31,7 @@ define i32 @test_simplify2() {
 }
 
 define i32 @test_simplify3() {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %null_hello_p = getelementptr [7 x i8]* @null_hello, i32 0, i32 0
   %null_hello_l = call i32 @strlen(i8* %null_hello_p)
   ret i32 %null_hello_l
@@ -39,7 +39,7 @@ define i32 @test_simplify3() {
 }
 
 define i32 @test_simplify4() {
-; CHECK: @test_simplify4
+; CHECK-LABEL: @test_simplify4(
   %len = tail call i32 @strlen(i8* @nullstring) nounwind
   ret i32 %len
 ; CHECK-NEXT: ret i32 0
@@ -48,7 +48,7 @@ define i32 @test_simplify4() {
 ; Check strlen(x) == 0 --> *x == 0.
 
 define i1 @test_simplify5() {
-; CHECK: @test_simplify5
+; CHECK-LABEL: @test_simplify5(
   %hello_p = getelementptr [6 x i8]* @hello, i32 0, i32 0
   %hello_l = call i32 @strlen(i8* %hello_p)
   %eq_hello = icmp eq i32 %hello_l, 0
@@ -57,7 +57,7 @@ define i1 @test_simplify5() {
 }
 
 define i1 @test_simplify6() {
-; CHECK: @test_simplify6
+; CHECK-LABEL: @test_simplify6(
   %null_p = getelementptr [1 x i8]* @null, i32 0, i32 0
   %null_l = call i32 @strlen(i8* %null_p)
   %eq_null = icmp eq i32 %null_l, 0
@@ -68,7 +68,7 @@ define i1 @test_simplify6() {
 ; Check strlen(x) != 0 --> *x != 0.
 
 define i1 @test_simplify7() {
-; CHECK: @test_simplify7
+; CHECK-LABEL: @test_simplify7(
   %hello_p = getelementptr [6 x i8]* @hello, i32 0, i32 0
   %hello_l = call i32 @strlen(i8* %hello_p)
   %ne_hello = icmp ne i32 %hello_l, 0
@@ -77,7 +77,7 @@ define i1 @test_simplify7() {
 }
 
 define i1 @test_simplify8() {
-; CHECK: @test_simplify8
+; CHECK-LABEL: @test_simplify8(
   %null_p = getelementptr [1 x i8]* @null, i32 0, i32 0
   %null_l = call i32 @strlen(i8* %null_p)
   %ne_null = icmp ne i32 %null_l, 0
@@ -88,7 +88,7 @@ define i1 @test_simplify8() {
 ; Check cases that shouldn't be simplified.
 
 define i32 @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %a_p = getelementptr [32 x i8]* @a, i32 0, i32 0
   %a_l = call i32 @strlen(i8* %a_p)
 ; CHECK-NEXT: %a_l = call i32 @strlen
diff --git a/test/Transforms/InstCombine/strlen-2.ll b/test/Transforms/InstCombine/strlen-2.ll
index c4fd54c..6652a31 100644
--- a/test/Transforms/InstCombine/strlen-2.ll
+++ b/test/Transforms/InstCombine/strlen-2.ll
@@ -9,7 +9,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 declare i32 @strlen(i8*, i32)
 
 define i32 @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %hello_p = getelementptr [6 x i8]* @hello, i32 0, i32 0
   %hello_l = call i32 @strlen(i8* %hello_p, i32 187)
 ; CHECK-NEXT: %hello_l = call i32 @strlen
diff --git a/test/Transforms/InstCombine/strncat-1.ll b/test/Transforms/InstCombine/strncat-1.ll
index ad2a18b..8eae3da 100644
--- a/test/Transforms/InstCombine/strncat-1.ll
+++ b/test/Transforms/InstCombine/strncat-1.ll
@@ -12,7 +12,7 @@ declare i8* @strncat(i8*, i8*, i32)
 declare i32 @puts(i8*)
 
 define i32 @main() {
-; CHECK: @main
+; CHECK-LABEL: @main(
 ; CHECK-NOT: call i8* @strncat
 ; CHECK: call i32 @puts
 
diff --git a/test/Transforms/InstCombine/strncat-2.ll b/test/Transforms/InstCombine/strncat-2.ll
index c56deac..b09fa12 100644
--- a/test/Transforms/InstCombine/strncat-2.ll
+++ b/test/Transforms/InstCombine/strncat-2.ll
@@ -11,7 +11,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 declare i8* @strncat(i8*, i8*, i32)
 
 define void @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
 ; CHECK-NOT: call i8* @strncat
 ; CHECK: ret void
 
@@ -22,7 +22,7 @@ define void @test_simplify1() {
 }
 
 define void @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
 ; CHECK-NEXT: ret void
 
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
@@ -32,7 +32,7 @@ define void @test_simplify2() {
 }
 
 define void @test_simplify3() {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
 ; CHECK-NEXT: ret void
 
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
@@ -42,7 +42,7 @@ define void @test_simplify3() {
 }
 
 define void @test_nosimplify1() {
-; CHECK: @test_nosimplify1
+; CHECK-LABEL: @test_nosimplify1(
 ; CHECK: call i8* @strncat
 ; CHECK: ret void
 
diff --git a/test/Transforms/InstCombine/strncat-3.ll b/test/Transforms/InstCombine/strncat-3.ll
index 3cd7971..1b25b4a 100644
--- a/test/Transforms/InstCombine/strncat-3.ll
+++ b/test/Transforms/InstCombine/strncat-3.ll
@@ -11,7 +11,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 declare i16* @strncat(i8*, i8*, i32)
 
 define void @test_nosimplify1() {
-; CHECK: @test_nosimplify1
+; CHECK-LABEL: @test_nosimplify1(
 ; CHECK: call i16* @strncat
 ; CHECK: ret void
 
diff --git a/test/Transforms/InstCombine/strncmp-1.ll b/test/Transforms/InstCombine/strncmp-1.ll
index 187c2fa..df30dd1 100644
--- a/test/Transforms/InstCombine/strncmp-1.ll
+++ b/test/Transforms/InstCombine/strncmp-1.ll
@@ -12,7 +12,7 @@ declare i32 @strncmp(i8*, i8*, i32)
 
 ; strncmp("", x, n) -> -*x
 define i32 @test1(i8* %str2) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %strcmpload = load i8* %str
 ; CHECK: %1 = zext i8 %strcmpload to i32
 ; CHECK: %2 = sub i32 0, %1
@@ -25,7 +25,7 @@ define i32 @test1(i8* %str2) {
 
 ; strncmp(x, "", n) -> *x
 define i32 @test2(i8* %str1) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: %strcmpload = load i8* %str1
 ; CHECK: %1 = zext i8 %strcmpload to i32
 ; CHECK: ret i32 %1
@@ -37,7 +37,7 @@ define i32 @test2(i8* %str1) {
 
 ; strncmp(x, y, n)  -> cnst
 define i32 @test3() {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: ret i32 -1
 
   %str1 = getelementptr inbounds [5 x i8]* @hell, i32 0, i32 0
@@ -47,7 +47,7 @@ define i32 @test3() {
 }
 
 define i32 @test4() {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: ret i32 1
 
   %str1 = getelementptr inbounds [5 x i8]* @hell, i32 0, i32 0
@@ -57,7 +57,7 @@ define i32 @test4() {
 }
 
 define i32 @test5() {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: ret i32 0
 
   %str1 = getelementptr inbounds [5 x i8]* @hell, i32 0, i32 0
@@ -68,7 +68,7 @@ define i32 @test5() {
 
 ; strncmp(x,y,1) -> memcmp(x,y,1)
 define i32 @test6(i8* %str1, i8* %str2) {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: [[LOAD1:%[a-z]+]] = load i8* %str1, align 1
 ; CHECK: [[ZEXT1:%[a-z]+]] = zext i8 [[LOAD1]] to i32
 ; CHECK: [[LOAD2:%[a-z]+]] = load i8* %str2, align 1
@@ -82,7 +82,7 @@ define i32 @test6(i8* %str1, i8* %str2) {
 
 ; strncmp(x,y,0)   -> 0
 define i32 @test7(i8* %str1, i8* %str2) {
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: ret i32 0
 
   %temp1 = call i32 @strncmp(i8* %str1, i8* %str2, i32 0)
@@ -91,7 +91,7 @@ define i32 @test7(i8* %str1, i8* %str2) {
 
 ; strncmp(x,x,n)  -> 0
 define i32 @test8(i8* %str, i32 %n) {
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: ret i32 0
 
   %temp1 = call i32 @strncmp(i8* %str, i8* %str, i32 %n)
diff --git a/test/Transforms/InstCombine/strncmp-2.ll b/test/Transforms/InstCombine/strncmp-2.ll
index 3fc43a6..16ad8a4 100644
--- a/test/Transforms/InstCombine/strncmp-2.ll
+++ b/test/Transforms/InstCombine/strncmp-2.ll
@@ -9,7 +9,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 declare i16 @strncmp(i8*, i8*, i32)
 
 define i16 @test_nosimplify() {
-; CHECK: @test_nosimplify
+; CHECK-LABEL: @test_nosimplify(
 ; CHECK: call i16 @strncmp
 ; CHECK: ret i16 %temp1
 
diff --git a/test/Transforms/InstCombine/strncpy-1.ll b/test/Transforms/InstCombine/strncpy-1.ll
index 3ce2b9b..c70197f 100644
--- a/test/Transforms/InstCombine/strncpy-1.ll
+++ b/test/Transforms/InstCombine/strncpy-1.ll
@@ -16,7 +16,7 @@ declare i32 @puts(i8*)
 ; Check a bunch of strncpy invocations together.
 
 define i32 @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
 ; CHECK-NOT: call i8* @strncpy
 ; CHECK: call i32 @puts
   %target = alloca [1024 x i8]
@@ -39,7 +39,7 @@ define i32 @test_simplify1() {
 ; Check strncpy(x, "", y) -> memset(x, '\0', y, 1).
 
 define void @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
   %src = getelementptr [1 x i8]* @null, i32 0, i32 0
 
@@ -51,7 +51,7 @@ define void @test_simplify2() {
 ; Check strncpy(x, y, 0) -> x.
 
 define i8* @test_simplify3() {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
   %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
 
@@ -63,7 +63,7 @@ define i8* @test_simplify3() {
 ; Check  strncpy(x, s, c) -> memcpy(x, s, c, 1) [s and c are constant].
 
 define void @test_simplify4() {
-; CHECK: @test_simplify4
+; CHECK-LABEL: @test_simplify4(
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
   %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
 
@@ -75,7 +75,7 @@ define void @test_simplify4() {
 ; Check cases that shouldn't be simplified.
 
 define void @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
   %src = getelementptr [32 x i8]* @b, i32 0, i32 0
 
@@ -85,7 +85,7 @@ define void @test_no_simplify1() {
 }
 
 define void @test_no_simplify2() {
-; CHECK: @test_no_simplify2
+; CHECK-LABEL: @test_no_simplify2(
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
   %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
 
diff --git a/test/Transforms/InstCombine/strncpy-2.ll b/test/Transforms/InstCombine/strncpy-2.ll
index ac28ea6..acc2878 100644
--- a/test/Transforms/InstCombine/strncpy-2.ll
+++ b/test/Transforms/InstCombine/strncpy-2.ll
@@ -12,7 +12,7 @@ declare i16* @strncpy(i8*, i8*, i32)
 ; Check that 'strncpy' functions with the wrong prototype aren't simplified.
 
 define void @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %dst = getelementptr [32 x i8]* @a, i32 0, i32 0
   %src = getelementptr [6 x i8]* @hello, i32 0, i32 0
 
diff --git a/test/Transforms/InstCombine/strncpy_chk-1.ll b/test/Transforms/InstCombine/strncpy_chk-1.ll
index aadff42..90b4173 100644
--- a/test/Transforms/InstCombine/strncpy_chk-1.ll
+++ b/test/Transforms/InstCombine/strncpy_chk-1.ll
@@ -12,7 +12,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 ; Check cases where dstlen >= len
 
 define void @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
 
@@ -22,7 +22,7 @@ define void @test_simplify1() {
 }
 
 define void @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
 
@@ -32,7 +32,7 @@ define void @test_simplify2() {
 }
 
 define void @test_simplify3() {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [60 x i8]* @b, i32 0, i32 0
 
@@ -44,7 +44,7 @@ define void @test_simplify3() {
 ; Check cases where dstlen < len
 
 define void @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [12 x i8]* @.str, i32 0, i32 0
 
@@ -54,7 +54,7 @@ define void @test_no_simplify1() {
 }
 
 define void @test_no_simplify2() {
-; CHECK: @test_no_simplify2
+; CHECK-LABEL: @test_no_simplify2(
   %dst = getelementptr inbounds [60 x i8]* @a, i32 0, i32 0
   %src = getelementptr inbounds [60 x i8]* @b, i32 0, i32 0
 
diff --git a/test/Transforms/InstCombine/strncpy_chk-2.ll b/test/Transforms/InstCombine/strncpy_chk-2.ll
index a0f132e..829a479 100644
--- a/test/Transforms/InstCombine/strncpy_chk-2.ll
+++ b/test/Transforms/InstCombine/strncpy_chk-2.ll
@@ -9,7 +9,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 @b = common global [60 x i16] zeroinitializer, align 1
 
 define void @test_no_simplify() {
-; CHECK: @test_no_simplify
+; CHECK-LABEL: @test_no_simplify(
   %dst = getelementptr inbounds [60 x i16]* @a, i32 0, i32 0
   %src = getelementptr inbounds [60 x i16]* @b, i32 0, i32 0
 
diff --git a/test/Transforms/InstCombine/strpbrk-1.ll b/test/Transforms/InstCombine/strpbrk-1.ll
index a5d0d86..58b2d9e 100644
--- a/test/Transforms/InstCombine/strpbrk-1.ll
+++ b/test/Transforms/InstCombine/strpbrk-1.ll
@@ -13,7 +13,7 @@ declare i8* @strpbrk(i8*, i8*)
 ; Check strpbrk(s, "") -> NULL.
 
 define i8* @test_simplify1(i8* %str) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %pat = getelementptr [1 x i8]* @null, i32 0, i32 0
 
   %ret = call i8* @strpbrk(i8* %str, i8* %pat)
@@ -24,7 +24,7 @@ define i8* @test_simplify1(i8* %str) {
 ; Check strpbrk("", s) -> NULL.
 
 define i8* @test_simplify2(i8* %pat) {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %str = getelementptr [1 x i8]* @null, i32 0, i32 0
 
   %ret = call i8* @strpbrk(i8* %str, i8* %pat)
@@ -35,7 +35,7 @@ define i8* @test_simplify2(i8* %pat) {
 ; Check strpbrk(s1, s2), where s1 and s2 are constants.
 
 define i8* @test_simplify3() {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %str = getelementptr [12 x i8]* @hello, i32 0, i32 0
   %pat = getelementptr [2 x i8]* @w, i32 0, i32 0
 
@@ -47,7 +47,7 @@ define i8* @test_simplify3() {
 ; Check strpbrk(s, "a") -> strchr(s, 'a').
 
 define i8* @test_simplify4(i8* %str) {
-; CHECK: @test_simplify4
+; CHECK-LABEL: @test_simplify4(
   %pat = getelementptr [2 x i8]* @w, i32 0, i32 0
 
   %ret = call i8* @strpbrk(i8* %str, i8* %pat)
@@ -59,7 +59,7 @@ define i8* @test_simplify4(i8* %str) {
 ; Check cases that shouldn't be simplified.
 
 define i8* @test_no_simplify1(i8* %str, i8* %pat) {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
 
   %ret = call i8* @strpbrk(i8* %str, i8* %pat)
 ; CHECK-NEXT: %ret = call i8* @strpbrk(i8* %str, i8* %pat)
diff --git a/test/Transforms/InstCombine/strpbrk-2.ll b/test/Transforms/InstCombine/strpbrk-2.ll
index 31ac290..b797d7a 100644
--- a/test/Transforms/InstCombine/strpbrk-2.ll
+++ b/test/Transforms/InstCombine/strpbrk-2.ll
@@ -12,7 +12,7 @@ declare i16* @strpbrk(i8*, i8*)
 ; Check that 'strpbrk' functions with the wrong prototype aren't simplified.
 
 define i16* @test_no_simplify1() {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %str = getelementptr [12 x i8]* @hello, i32 0, i32 0
   %pat = getelementptr [2 x i8]* @w, i32 0, i32 0
 
diff --git a/test/Transforms/InstCombine/strrchr-1.ll b/test/Transforms/InstCombine/strrchr-1.ll
index 854ce45..a0bdb22 100644
--- a/test/Transforms/InstCombine/strrchr-1.ll
+++ b/test/Transforms/InstCombine/strrchr-1.ll
@@ -43,7 +43,7 @@ define void @test_simplify3() {
 }
 
 define void @test_nosimplify1(i32 %chr) {
-; CHECK: @test_nosimplify1
+; CHECK-LABEL: @test_nosimplify1(
 ; CHECK: call i8* @strrchr
 ; CHECK: ret void
 
diff --git a/test/Transforms/InstCombine/strspn-1.ll b/test/Transforms/InstCombine/strspn-1.ll
index 393f887..ac940cc 100644
--- a/test/Transforms/InstCombine/strspn-1.ll
+++ b/test/Transforms/InstCombine/strspn-1.ll
@@ -13,7 +13,7 @@ declare i64 @strspn(i8*, i8*)
 ; Check strspn(s, "") -> 0.
 
 define i64 @test_simplify1(i8* %str) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %pat = getelementptr [1 x i8]* @null, i32 0, i32 0
 
   %ret = call i64 @strspn(i8* %str, i8* %pat)
@@ -24,7 +24,7 @@ define i64 @test_simplify1(i8* %str) {
 ; Check strspn("", s) -> 0.
 
 define i64 @test_simplify2(i8* %pat) {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %str = getelementptr [1 x i8]* @null, i32 0, i32 0
 
   %ret = call i64 @strspn(i8* %str, i8* %pat)
@@ -35,7 +35,7 @@ define i64 @test_simplify2(i8* %pat) {
 ; Check strspn(s1, s2), where s1 and s2 are constants.
 
 define i64 @test_simplify3() {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %str = getelementptr [6 x i8]* @abcba, i32 0, i32 0
   %pat = getelementptr [4 x i8]* @abc, i32 0, i32 0
 
@@ -47,7 +47,7 @@ define i64 @test_simplify3() {
 ; Check cases that shouldn't be simplified.
 
 define i64 @test_no_simplify1(i8* %str, i8* %pat) {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
 
   %ret = call i64 @strspn(i8* %str, i8* %pat)
 ; CHECK-NEXT: %ret = call i64 @strspn(i8* %str, i8* %pat)
diff --git a/test/Transforms/InstCombine/strstr-1.ll b/test/Transforms/InstCombine/strstr-1.ll
index 81f5271..a946dd3 100644
--- a/test/Transforms/InstCombine/strstr-1.ll
+++ b/test/Transforms/InstCombine/strstr-1.ll
@@ -14,7 +14,7 @@ declare i8* @strstr(i8*, i8*)
 ; Check strstr(str, "") -> str.
 
 define i8* @test_simplify1(i8* %str) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %pat = getelementptr inbounds [1 x i8]* @.str, i32 0, i32 0
   %ret = call i8* @strstr(i8* %str, i8* %pat)
   ret i8* %ret
@@ -24,7 +24,7 @@ define i8* @test_simplify1(i8* %str) {
 ; Check strstr(str, "a") -> strchr(str, 'a').
 
 define i8* @test_simplify2(i8* %str) {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %pat = getelementptr inbounds [2 x i8]* @.str1, i32 0, i32 0
   %ret = call i8* @strstr(i8* %str, i8* %pat)
   ret i8* %ret
@@ -34,7 +34,7 @@ define i8* @test_simplify2(i8* %str) {
 ; Check strstr("abcde", "bcd") -> "abcde" + 1.
 
 define i8* @test_simplify3() {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %str = getelementptr inbounds [6 x i8]* @.str2, i32 0, i32 0
   %pat = getelementptr inbounds [4 x i8]* @.str3, i32 0, i32 0
   %ret = call i8* @strstr(i8* %str, i8* %pat)
@@ -45,7 +45,7 @@ define i8* @test_simplify3() {
 ; Check strstr(str, str) -> str.
 
 define i8* @test_simplify4(i8* %str) {
-; CHECK: @test_simplify4
+; CHECK-LABEL: @test_simplify4(
   %ret = call i8* @strstr(i8* %str, i8* %str)
   ret i8* %ret
 ; CHECK-NEXT: ret i8* %str
@@ -54,7 +54,7 @@ define i8* @test_simplify4(i8* %str) {
 ; Check strstr(str, pat) == str -> strncmp(str, pat, strlen(str)) == 0.
 
 define i1 @test_simplify5(i8* %str, i8* %pat) {
-; CHECK: @test_simplify5
+; CHECK-LABEL: @test_simplify5(
   %ret = call i8* @strstr(i8* %str, i8* %pat)
   %cmp = icmp eq i8* %ret, %str
   ret i1 %cmp
diff --git a/test/Transforms/InstCombine/strstr-2.ll b/test/Transforms/InstCombine/strstr-2.ll
index 5092f9b..7b28ed0 100644
--- a/test/Transforms/InstCombine/strstr-2.ll
+++ b/test/Transforms/InstCombine/strstr-2.ll
@@ -9,7 +9,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 declare i8 @strstr(i8*, i8*)
 
 define i8 @test_no_simplify1(i8* %str) {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   %pat = getelementptr inbounds [1 x i8]* @null, i32 0, i32 0
   %ret = call i8 @strstr(i8* %str, i8* %pat)
 ; CHECK-NEXT: call i8 @strstr
diff --git a/test/Transforms/InstCombine/strto-1.ll b/test/Transforms/InstCombine/strto-1.ll
index 7139972..fc35ddd 100644
--- a/test/Transforms/InstCombine/strto-1.ll
+++ b/test/Transforms/InstCombine/strto-1.ll
@@ -5,77 +5,77 @@
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 
 declare i64 @strtol(i8* %s, i8** %endptr, i32 %base)
-; CHECK: declare i64 @strtol(i8*, i8** nocapture, i32)
+; CHECK: declare i64 @strtol(i8* readonly, i8** nocapture, i32)
 
 declare double @strtod(i8* %s, i8** %endptr, i32 %base)
-; CHECK: declare double @strtod(i8*, i8** nocapture, i32)
+; CHECK: declare double @strtod(i8* readonly, i8** nocapture, i32)
 
 declare float @strtof(i8* %s, i8** %endptr, i32 %base)
-; CHECK: declare float @strtof(i8*, i8** nocapture, i32)
+; CHECK: declare float @strtof(i8* readonly, i8** nocapture, i32)
 
 declare i64 @strtoul(i8* %s, i8** %endptr, i32 %base)
-; CHECK: declare i64 @strtoul(i8*, i8** nocapture, i32)
+; CHECK: declare i64 @strtoul(i8* readonly, i8** nocapture, i32)
 
 declare i64 @strtoll(i8* %s, i8** %endptr, i32 %base)
-; CHECK: declare i64 @strtoll(i8*, i8** nocapture, i32)
+; CHECK: declare i64 @strtoll(i8* readonly, i8** nocapture, i32)
 
 declare double @strtold(i8* %s, i8** %endptr)
-; CHECK: declare double @strtold(i8*, i8** nocapture)
+; CHECK: declare double @strtold(i8* readonly, i8** nocapture)
 
 declare i64 @strtoull(i8* %s, i8** %endptr, i32 %base)
-; CHECK: declare i64 @strtoull(i8*, i8** nocapture, i32)
+; CHECK: declare i64 @strtoull(i8* readonly, i8** nocapture, i32)
 
 define void @test_simplify1(i8* %x, i8** %endptr) {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   call i64 @strtol(i8* %x, i8** null, i32 10)
 ; CHECK-NEXT: call i64 @strtol(i8* nocapture %x, i8** null, i32 10)
   ret void
 }
 
 define void @test_simplify2(i8* %x, i8** %endptr) {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   call double @strtod(i8* %x, i8** null, i32 10)
 ; CHECK-NEXT: call double @strtod(i8* nocapture %x, i8** null, i32 10)
   ret void
 }
 
 define void @test_simplify3(i8* %x, i8** %endptr) {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   call float @strtof(i8* %x, i8** null, i32 10)
 ; CHECK-NEXT: call float @strtof(i8* nocapture %x, i8** null, i32 10)
   ret void
 }
 
 define void @test_simplify4(i8* %x, i8** %endptr) {
-; CHECK: @test_simplify4
+; CHECK-LABEL: @test_simplify4(
   call i64 @strtoul(i8* %x, i8** null, i32 10)
 ; CHECK-NEXT: call i64 @strtoul(i8* nocapture %x, i8** null, i32 10)
   ret void
 }
 
 define void @test_simplify5(i8* %x, i8** %endptr) {
-; CHECK: @test_simplify5
+; CHECK-LABEL: @test_simplify5(
   call i64 @strtoll(i8* %x, i8** null, i32 10)
 ; CHECK-NEXT: call i64 @strtoll(i8* nocapture %x, i8** null, i32 10)
   ret void
 }
 
 define void @test_simplify6(i8* %x, i8** %endptr) {
-; CHECK: @test_simplify6
+; CHECK-LABEL: @test_simplify6(
   call double @strtold(i8* %x, i8** null)
 ; CHECK-NEXT: call double @strtold(i8* nocapture %x, i8** null)
   ret void
 }
 
 define void @test_simplify7(i8* %x, i8** %endptr) {
-; CHECK: @test_simplify7
+; CHECK-LABEL: @test_simplify7(
   call i64 @strtoull(i8* %x, i8** null, i32 10)
 ; CHECK-NEXT: call i64 @strtoull(i8* nocapture %x, i8** null, i32 10)
   ret void
 }
 
 define void @test_no_simplify1(i8* %x, i8** %endptr) {
-; CHECK: @test_no_simplify1
+; CHECK-LABEL: @test_no_simplify1(
   call i64 @strtol(i8* %x, i8** %endptr, i32 10)
 ; CHECK-NEXT: call i64 @strtol(i8* %x, i8** %endptr, i32 10)
   ret void
diff --git a/test/Transforms/InstCombine/struct-assign-tbaa.ll b/test/Transforms/InstCombine/struct-assign-tbaa.ll
index 33a771e..d7a26fa 100644
--- a/test/Transforms/InstCombine/struct-assign-tbaa.ll
+++ b/test/Transforms/InstCombine/struct-assign-tbaa.ll
@@ -24,7 +24,7 @@ entry:
 %struct.test2 = type { i32 (i8*, i32*, double*)** }
 
 define i32 (i8*, i32*, double*)*** @test2() {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NOT: memcpy
 ; CHECK: ret
   %tmp = alloca %struct.test2, align 8
diff --git a/test/Transforms/InstCombine/sub-xor.ll b/test/Transforms/InstCombine/sub-xor.ll
index 1d14852..e7aff00 100644
--- a/test/Transforms/InstCombine/sub-xor.ll
+++ b/test/Transforms/InstCombine/sub-xor.ll
@@ -5,7 +5,7 @@ define i32 @test1(i32 %x) nounwind {
   %sub = sub i32 63, %and
   ret i32 %sub
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: and i32 %x, 31
 ; CHECK-NEXT: xor i32 %and, 63
 ; CHECK-NEXT: ret
@@ -18,7 +18,7 @@ define i32 @test2(i32 %x) nounwind {
   %sub = sub i32 31, %count
   ret i32 %sub
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: ctlz
 ; CHECK-NEXT: xor i32 %count, 31
 ; CHECK-NEXT: ret
@@ -30,7 +30,7 @@ define i32 @test3(i32 %x) nounwind {
   %add = add i32 %sub, 42
   ret i32 %add
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: and i32 %x, 31
 ; CHECK-NEXT: sub i32 73, %and
 ; CHECK-NEXT: ret
@@ -41,7 +41,7 @@ define i32 @test4(i32 %x) nounwind {
   %add = add i32 %sub, 42
   ret i32 %add
 
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: add i32 %x, -2147483606
 ; CHECK-NEXT: ret
 }
diff --git a/test/Transforms/InstCombine/sub.ll b/test/Transforms/InstCombine/sub.ll
index b71ec8c..5449656 100644
--- a/test/Transforms/InstCombine/sub.ll
+++ b/test/Transforms/InstCombine/sub.ll
@@ -7,14 +7,14 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 define i32 @test1(i32 %A) {
 	%B = sub i32 %A, %A	
 	ret i32 %B
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret i32 0
 }
 
 define i32 @test2(i32 %A) {
 	%B = sub i32 %A, 0	
 	ret i32 %B
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: ret i32 %A
 }
 
@@ -22,7 +22,7 @@ define i32 @test3(i32 %A) {
 	%B = sub i32 0, %A	
 	%C = sub i32 0, %B	
 	ret i32 %C
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: ret i32 %A
 }
 
@@ -30,7 +30,7 @@ define i32 @test4(i32 %A, i32 %x) {
 	%B = sub i32 0, %A	
 	%C = sub i32 %x, %B	
 	ret i32 %C
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: %C = add i32 %x, %A
 ; CHECK: ret i32 %C
 }
@@ -39,7 +39,7 @@ define i32 @test5(i32 %A, i32 %B, i32 %C) {
 	%D = sub i32 %B, %C	
 	%E = sub i32 %A, %D	
 	ret i32 %E
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: %D1 = sub i32 %C, %B
 ; CHECK: %E = add
 ; CHECK: ret i32 %E
@@ -49,7 +49,7 @@ define i32 @test6(i32 %A, i32 %B) {
 	%C = and i32 %A, %B	
 	%D = sub i32 %A, %C	
 	ret i32 %D
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: xor i32 %B, -1
 ; CHECK-NEXT: %D = and i32 
 ; CHECK-NEXT: ret i32 %D
@@ -58,7 +58,7 @@ define i32 @test6(i32 %A, i32 %B) {
 define i32 @test7(i32 %A) {
 	%B = sub i32 -1, %A	
 	ret i32 %B
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: %B = xor i32 %A, -1
 ; CHECK: ret i32 %B
 }
@@ -67,7 +67,7 @@ define i32 @test8(i32 %A) {
 	%B = mul i32 9, %A	
 	%C = sub i32 %B, %A	
 	ret i32 %C
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: %C = shl i32 %A, 3
 ; CHECK: ret i32 %C
 }
@@ -76,7 +76,7 @@ define i32 @test9(i32 %A) {
 	%B = mul i32 3, %A	
 	%C = sub i32 %A, %B	
 	ret i32 %C
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK: %C = mul i32 %A, -2
 ; CHECK: ret i32 %C
 }
@@ -86,7 +86,7 @@ define i32 @test10(i32 %A, i32 %B) {
 	%D = sub i32 0, %B	
 	%E = mul i32 %C, %D	
 	ret i32 %E
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK: %E = mul i32 %A, %B
 ; CHECK: ret i32 %E
 }
@@ -95,7 +95,7 @@ define i32 @test10a(i32 %A) {
 	%C = sub i32 0, %A	
 	%E = mul i32 %C, 7	
 	ret i32 %E
-; CHECK: @test10a
+; CHECK-LABEL: @test10a(
 ; CHECK: %E = mul i32 %A, -7
 ; CHECK: ret i32 %E
 }
@@ -104,7 +104,7 @@ define i1 @test11(i8 %A, i8 %B) {
 	%C = sub i8 %A, %B	
 	%cD = icmp ne i8 %C, 0	
 	ret i1 %cD
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK: %cD = icmp ne i8 %A, %B
 ; CHECK: ret i1 %cD
 }
@@ -113,7 +113,7 @@ define i32 @test12(i32 %A) {
 	%B = ashr i32 %A, 31	
 	%C = sub i32 0, %B	
 	ret i32 %C
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK: %C = lshr i32 %A, 31
 ; CHECK: ret i32 %C
 }
@@ -122,7 +122,7 @@ define i32 @test13(i32 %A) {
 	%B = lshr i32 %A, 31	
 	%C = sub i32 0, %B	
 	ret i32 %C
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK: %C = ashr i32 %A, 31
 ; CHECK: ret i32 %C
 }
@@ -132,7 +132,7 @@ define i32 @test14(i32 %A) {
 	%C = bitcast i32 %B to i32	
 	%D = sub i32 0, %C	
 	ret i32 %D
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK: %D = ashr i32 %A, 31
 ; CHECK: ret i32 %D
 }
@@ -141,7 +141,7 @@ define i32 @test15(i32 %A, i32 %B) {
 	%C = sub i32 0, %A	
 	%D = srem i32 %B, %C	
 	ret i32 %D
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 ; CHECK: %D = srem i32 %B, %A 
 ; CHECK: ret i32 %D
 }
@@ -150,7 +150,7 @@ define i32 @test16(i32 %A) {
 	%X = sdiv i32 %A, 1123	
 	%Y = sub i32 0, %X	
 	ret i32 %Y
-; CHECK: @test16
+; CHECK-LABEL: @test16(
 ; CHECK: %Y = sdiv i32 %A, -1123
 ; CHECK: ret i32 %Y
 }
@@ -161,7 +161,7 @@ define i32 @test17(i32 %A) {
 	%B = sub i32 0, %A	
 	%C = sdiv i32 %B, 1234	
 	ret i32 %C
-; CHECK: @test17
+; CHECK-LABEL: @test17(
 ; CHECK: %B = sub i32 0, %A
 ; CHECK: %C = sdiv i32 %B, 1234
 ; CHECK: ret i32 %C
@@ -172,7 +172,7 @@ define i64 @test18(i64 %Y) {
 	%tmp.12 = shl i64 %Y, 2	
 	%tmp.8 = sub i64 %tmp.4, %tmp.12	
 	ret i64 %tmp.8
-; CHECK: @test18
+; CHECK-LABEL: @test18(
 ; CHECK: ret i64 0
 }
 
@@ -180,7 +180,7 @@ define i32 @test19(i32 %X, i32 %Y) {
 	%Z = sub i32 %X, %Y	
 	%Q = add i32 %Z, %Y	
 	ret i32 %Q
-; CHECK: @test19
+; CHECK-LABEL: @test19(
 ; CHECK: ret i32 %X
 }
 
@@ -188,7 +188,7 @@ define i1 @test20(i32 %g, i32 %h) {
 	%tmp.2 = sub i32 %g, %h	
 	%tmp.4 = icmp ne i32 %tmp.2, %g	
 	ret i1 %tmp.4
-; CHECK: @test20
+; CHECK-LABEL: @test20(
 ; CHECK: %tmp.4 = icmp ne i32 %h, 0
 ; CHECK: ret i1 %tmp.4
 }
@@ -197,7 +197,7 @@ define i1 @test21(i32 %g, i32 %h) {
 	%tmp.2 = sub i32 %g, %h	
 	%tmp.4 = icmp ne i32 %tmp.2, %g		
         ret i1 %tmp.4
-; CHECK: @test21
+; CHECK-LABEL: @test21(
 ; CHECK: %tmp.4 = icmp ne i32 %h, 0
 ; CHECK: ret i1 %tmp.4
 }
@@ -208,7 +208,7 @@ define zeroext i1 @test22(i32 %a, i32 %b)  nounwind  {
 	%tmp4 = sub i32 0, %b	
 	%tmp5 = icmp eq i32 %tmp2, %tmp4	
 	ret i1 %tmp5
-; CHECK: @test22
+; CHECK-LABEL: @test22(
 ; CHECK: %tmp5 = icmp eq i32 %b, %a
 ; CHECK: ret i1 %tmp5
 }
@@ -222,7 +222,7 @@ define i32 @test23(i8* %P, i64 %A){
   %F = trunc i64 %E to i32
   %G = sub i32 %D, %F
   ret i32 %G
-; CHECK: @test23
+; CHECK-LABEL: @test23(
 ; CHECK-NEXT: = trunc i64 %A to i32
 ; CHECK-NEXT: ret i32
 }
@@ -233,7 +233,7 @@ define i64 @test24(i8* %P, i64 %A){
   %E = ptrtoint i8* %P to i64
   %G = sub i64 %C, %E
   ret i64 %G
-; CHECK: @test24
+; CHECK-LABEL: @test24(
 ; CHECK-NEXT: ret i64 %A
 }
 
@@ -243,7 +243,7 @@ define i64 @test24a(i8* %P, i64 %A){
   %E = ptrtoint i8* %P to i64
   %G = sub i64 %E, %C
   ret i64 %G
-; CHECK: @test24a
+; CHECK-LABEL: @test24a(
 ; CHECK-NEXT: sub i64 0, %A
 ; CHECK-NEXT: ret i64 
 }
@@ -255,7 +255,7 @@ define i64 @test24b(i8* %P, i64 %A){
   %C = ptrtoint i16* %B to i64
   %G = sub i64 %C, ptrtoint ([42 x i16]* @Arr to i64)
   ret i64 %G
-; CHECK: @test24b
+; CHECK-LABEL: @test24b(
 ; CHECK-NEXT: shl nuw i64 %A, 1
 ; CHECK-NEXT: ret i64 
 }
@@ -266,7 +266,7 @@ define i64 @test25(i8* %P, i64 %A){
   %C = ptrtoint i16* %B to i64
   %G = sub i64 %C, ptrtoint (i16* getelementptr ([42 x i16]* @Arr, i64 1, i64 0) to i64)
   ret i64 %G
-; CHECK: @test25
+; CHECK-LABEL: @test25(
 ; CHECK-NEXT: shl nuw i64 %A, 1
 ; CHECK-NEXT: add i64 {{.*}}, -84
 ; CHECK-NEXT: ret i64 
@@ -276,7 +276,7 @@ define i32 @test26(i32 %x) {
   %shl = shl i32 3, %x
   %neg = sub i32 0, %shl
   ret i32 %neg
-; CHECK: @test26
+; CHECK-LABEL: @test26(
 ; CHECK-NEXT: shl i32 -3
 ; CHECK-NEXT: ret i32
 }
@@ -285,7 +285,7 @@ define i32 @test27(i32 %x, i32 %y) {
   %mul = mul i32 %y, -8
   %sub = sub i32 %x, %mul
   ret i32 %sub
-; CHECK: @test27
+; CHECK-LABEL: @test27(
 ; CHECK-NEXT: shl i32 %y, 3
 ; CHECK-NEXT: add i32
 ; CHECK-NEXT: ret i32
@@ -296,7 +296,7 @@ define i32 @test28(i32 %x, i32 %y, i32 %z) {
   %mul = mul i32 %neg, %y
   %sub = sub i32 %x, %mul
   ret i32 %sub
-; CHECK: @test28
+; CHECK-LABEL: @test28(
 ; CHECK-NEXT: mul i32 %z, %y
 ; CHECK-NEXT: add i32
 ; CHECK-NEXT: ret i32
@@ -309,7 +309,7 @@ define i64 @test29(i8* %foo, i64 %i, i64 %j) {
   %cast2 = ptrtoint i8* %gep2 to i64
   %sub = sub i64 %cast1, %cast2
   ret i64 %sub
-; CHECK: @test29
+; CHECK-LABEL: @test29(
 ; CHECK-NEXT: sub i64 %i, %j
 ; CHECK-NEXT: ret i64
 }
@@ -322,7 +322,7 @@ define i64 @test30(i8* %foo, i64 %i, i64 %j) {
   %cast2 = ptrtoint i8* %gep2 to i64
   %sub = sub i64 %cast1, %cast2
   ret i64 %sub
-; CHECK: @test30
+; CHECK-LABEL: @test30(
 ; CHECK-NEXT: %gep1.idx = shl nuw i64 %i, 2
 ; CHECK-NEXT: sub i64 %gep1.idx, %j
 ; CHECK-NEXT: ret i64
diff --git a/test/Transforms/InstCombine/toascii-1.ll b/test/Transforms/InstCombine/toascii-1.ll
index c4a13e2..f5e1898 100644
--- a/test/Transforms/InstCombine/toascii-1.ll
+++ b/test/Transforms/InstCombine/toascii-1.ll
@@ -9,49 +9,49 @@ declare i32 @toascii(i32)
 ; Check isascii(c) -> c & 0x7f.
 
 define i32 @test_simplify1() {
-; CHECK: @test_simplify1
+; CHECK-LABEL: @test_simplify1(
   %ret = call i32 @toascii(i32 0)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 0
 }
 
 define i32 @test_simplify2() {
-; CHECK: @test_simplify2
+; CHECK-LABEL: @test_simplify2(
   %ret = call i32 @toascii(i32 1)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 1
 }
 
 define i32 @test_simplify3() {
-; CHECK: @test_simplify3
+; CHECK-LABEL: @test_simplify3(
   %ret = call i32 @toascii(i32 127)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 127
 }
 
 define i32 @test_simplify4() {
-; CHECK: @test_simplify4
+; CHECK-LABEL: @test_simplify4(
   %ret = call i32 @toascii(i32 128)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 0
 }
 
 define i32 @test_simplify5() {
-; CHECK: @test_simplify5
+; CHECK-LABEL: @test_simplify5(
   %ret = call i32 @toascii(i32 255)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 127
 }
 
 define i32 @test_simplify6() {
-; CHECK: @test_simplify6
+; CHECK-LABEL: @test_simplify6(
   %ret = call i32 @toascii(i32 256)
   ret i32 %ret
 ; CHECK-NEXT: ret i32 0
 }
 
 define i32 @test_simplify7(i32 %x) {
-; CHECK: @test_simplify7
+; CHECK-LABEL: @test_simplify7(
   %ret = call i32 @toascii(i32 %x)
 ; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 127
   ret i32 %ret
diff --git a/test/Transforms/InstCombine/trunc.ll b/test/Transforms/InstCombine/trunc.ll
index cbbad7f..ee81cf8 100644
--- a/test/Transforms/InstCombine/trunc.ll
+++ b/test/Transforms/InstCombine/trunc.ll
@@ -11,7 +11,7 @@ define i64 @test1(i64 %a) {
   %d = zext i32 %c to i64
   call void @use(i32 %b)
   ret i64 %d
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NOT: ext
 ; CHECK: ret
 }
@@ -22,7 +22,7 @@ define i64 @test2(i64 %a) {
   %d = sext i32 %q to i64
   call void @use(i32 %b)
   ret i64 %d
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: shl i64 %a, 36
 ; CHECK: %d = ashr exact i64 {{.*}}, 36
 ; CHECK: ret i64 %d
@@ -33,7 +33,7 @@ define i64 @test3(i64 %a) {
   %d = zext i32 %c to i64
   call void @use(i32 %b)
   ret i64 %d
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NOT: ext
 ; CHECK: ret
 }
@@ -44,7 +44,7 @@ define i64 @test4(i64 %a) {
   %d = zext i32 %x to i64
   call void @use(i32 %b)
   ret i64 %d
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: = and i64 %a, 8
 ; CHECK: = xor i64 {{.*}}, 8
 ; CHECK-NOT: ext
@@ -56,7 +56,7 @@ define i32 @test5(i32 %A) {
   %C = lshr i128 %B, 16
   %D = trunc i128 %C to i32
   ret i32 %D
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: %C = lshr i32 %A, 16
 ; CHECK: ret i32 %C
 }
@@ -66,7 +66,7 @@ define i32 @test6(i64 %A) {
   %C = lshr i128 %B, 32
   %D = trunc i128 %C to i32
   ret i32 %D
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: %C = lshr i64 %A, 32
 ; CHECK: %D = trunc i64 %C to i32
 ; CHECK: ret i32 %D
@@ -77,7 +77,7 @@ define i92 @test7(i64 %A) {
   %C = lshr i128 %B, 32
   %D = trunc i128 %C to i92
   ret i92 %D
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: %B = zext i64 %A to i92
 ; CHECK: %C = lshr i92 %B, 32
 ; CHECK: ret i92 %C
@@ -90,7 +90,7 @@ define i64 @test8(i32 %A, i32 %B) {
   %ins35 = or i128 %tmp33, %tmp38
   %tmp42 = trunc i128 %ins35 to i64
   ret i64 %tmp42
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK:   %tmp38 = zext i32 %A to i64
 ; CHECK:   %tmp32 = zext i32 %B to i64
 ; CHECK:   %tmp33 = shl nuw i64 %tmp32, 32
@@ -102,7 +102,7 @@ define i8 @test9(i32 %X) {
   %Y = and i32 %X, 42
   %Z = trunc i32 %Y to i8
   ret i8 %Z
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK: trunc
 ; CHECK: and
 ; CHECK: ret
@@ -113,7 +113,7 @@ define i8 @test10(i32 %X) {
   %Y = trunc i32 %X to i8
   %Z = and i8 %Y, 42
   ret i8 %Z
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK: trunc
 ; CHECK: and
 ; CHECK: ret
diff --git a/test/Transforms/InstCombine/udivrem-change-width.ll b/test/Transforms/InstCombine/udivrem-change-width.ll
index b388a3b..478e9ca 100644
--- a/test/Transforms/InstCombine/udivrem-change-width.ll
+++ b/test/Transforms/InstCombine/udivrem-change-width.ll
@@ -9,7 +9,7 @@ define i8 @udiv_i8(i8 %a, i8 %b) nounwind {
   %div = udiv i32 %conv, %conv2   
   %conv3 = trunc i32 %div to i8   
   ret i8 %conv3
-; CHECK: @udiv_i8
+; CHECK-LABEL: @udiv_i8(
 ; CHECK: udiv i8 %a, %b
 }
 
@@ -19,7 +19,7 @@ define i8 @urem_i8(i8 %a, i8 %b) nounwind {
   %div = urem i32 %conv, %conv2   
   %conv3 = trunc i32 %div to i8   
   ret i8 %conv3
-; CHECK: @urem_i8
+; CHECK-LABEL: @urem_i8(
 ; CHECK: urem i8 %a, %b
 }
 
@@ -28,7 +28,7 @@ define i32 @udiv_i32(i8 %a, i8 %b) nounwind {
   %conv2 = zext i8 %b to i32
   %div = udiv i32 %conv, %conv2
   ret i32 %div
-; CHECK: @udiv_i32
+; CHECK-LABEL: @udiv_i32(
 ; CHECK: udiv i8 %a, %b
 ; CHECK: zext
 }
@@ -38,7 +38,7 @@ define i32 @urem_i32(i8 %a, i8 %b) nounwind {
   %conv2 = zext i8 %b to i32
   %div = urem i32 %conv, %conv2
   ret i32 %div
-; CHECK: @urem_i32
+; CHECK-LABEL: @urem_i32(
 ; CHECK: urem i8 %a, %b
 ; CHECK: zext
 }
@@ -47,7 +47,7 @@ define i32 @udiv_i32_c(i8 %a) nounwind {
   %conv = zext i8 %a to i32
   %div = udiv i32 %conv, 10
   ret i32 %div
-; CHECK: @udiv_i32_c
+; CHECK-LABEL: @udiv_i32_c(
 ; CHECK: udiv i8 %a, 10
 ; CHECK: zext
 }
@@ -56,7 +56,7 @@ define i32 @urem_i32_c(i8 %a) nounwind {
   %conv = zext i8 %a to i32
   %div = urem i32 %conv, 10
   ret i32 %div
-; CHECK: @urem_i32_c
+; CHECK-LABEL: @urem_i32_c(
 ; CHECK: urem i8 %a, 10
 ; CHECK: zext
 }
diff --git a/test/Transforms/InstCombine/vec_demanded_elts.ll b/test/Transforms/InstCombine/vec_demanded_elts.ll
index 0019a57..d12412a 100644
--- a/test/Transforms/InstCombine/vec_demanded_elts.ll
+++ b/test/Transforms/InstCombine/vec_demanded_elts.ll
@@ -2,7 +2,7 @@
 
 define i16 @test1(float %f) {
 entry:
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: fmul float
 ; CHECK-NOT: insertelement {{.*}} 0.00
 ; CHECK-NOT: call {{.*}} @llvm.x86.sse.mul
@@ -22,7 +22,7 @@ entry:
 }
 
 define i32 @test2(float %f) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NOT: insertelement
 ; CHECK-NOT: extractelement
 ; CHECK: ret
@@ -37,7 +37,7 @@ define i32 @test2(float %f) {
 }
 
 define i64 @test3(float %f, double %d) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NOT: insertelement {{.*}} 0.00
 ; CHECK: ret
 entry:
@@ -85,7 +85,7 @@ entry:
 }
 
 define void @get_image() nounwind {
-; CHECK: @get_image
+; CHECK-LABEL: @get_image(
 ; CHECK-NOT: extractelement
 ; CHECK: unreachable
 entry:
@@ -105,7 +105,7 @@ bb3:            ; preds = %bb2, %entry
 
 ; PR4340
 define void @vac(<4 x float>* nocapture %a) nounwind {
-; CHECK: @vac
+; CHECK-LABEL: @vac(
 ; CHECK-NOT: load
 ; CHECK: ret
 entry:
@@ -155,7 +155,7 @@ declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone
 
 define <4 x float> @dead_shuffle_elt(<4 x float> %x, <2 x float> %y) nounwind {
 entry:
-; CHECK: define <4 x float> @dead_shuffle_elt
+; CHECK-LABEL: define <4 x float> @dead_shuffle_elt(
 ; CHECK: shufflevector <2 x float> %y, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   %shuffle.i = shufflevector <2 x float> %y, <2 x float> %y, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
   %shuffle9.i = shufflevector <4 x float> %x, <4 x float> %shuffle.i, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
@@ -163,7 +163,7 @@ entry:
 }
 
 define <2 x float> @test_fptrunc(double %f) {
-; CHECK: @test_fptrunc
+; CHECK-LABEL: @test_fptrunc(
 ; CHECK: insertelement
 ; CHECK: insertelement
 ; CHECK-NOT: insertelement
@@ -177,7 +177,7 @@ define <2 x float> @test_fptrunc(double %f) {
 }
 
 define <2 x double> @test_fpext(float %f) {
-; CHECK: @test_fpext
+; CHECK-LABEL: @test_fpext(
 ; CHECK: insertelement
 ; CHECK: insertelement
 ; CHECK-NOT: insertelement
@@ -191,7 +191,7 @@ define <2 x double> @test_fpext(float %f) {
 }
 
 define <4 x float> @test_select(float %f, float %g) {
-; CHECK: @test_select
+; CHECK-LABEL: @test_select(
 ; CHECK: %a0 = insertelement <4 x float> undef, float %f, i32 0
 ; CHECK-NOT: insertelement
 ; CHECK: %a3 = insertelement <4 x float> %a0, float 3.000000e+00, i32 3
diff --git a/test/Transforms/InstCombine/vec_shuffle.ll b/test/Transforms/InstCombine/vec_shuffle.ll
index 5ffe6c0..738e05b 100644
--- a/test/Transforms/InstCombine/vec_shuffle.ll
+++ b/test/Transforms/InstCombine/vec_shuffle.ll
@@ -1,21 +1,21 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define <4 x float> @test1(<4 x float> %v1) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret <4 x float> %v1
   %v2 = shufflevector <4 x float> %v1, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x float> %v2
 }
 
 define <4 x float> @test2(<4 x float> %v1) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: ret <4 x float> %v1
   %v2 = shufflevector <4 x float> %v1, <4 x float> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
   ret <4 x float> %v2
 }
 
 define float @test3(<4 x float> %A, <4 x float> %B, float %f) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: ret float %f
         %C = insertelement <4 x float> %A, float %f, i32 0
         %D = shufflevector <4 x float> %C, <4 x float> %B, <4 x i32> <i32 5, i32 0, i32 2, i32 7>
@@ -24,7 +24,7 @@ define float @test3(<4 x float> %A, <4 x float> %B, float %f) {
 }
 
 define i32 @test4(<4 x i32> %X) {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: extractelement
 ; CHECK-NEXT: ret 
         %tmp152.i53899.i = shufflevector <4 x i32> %X, <4 x i32> undef, <4 x i32> zeroinitializer
@@ -33,7 +33,7 @@ define i32 @test4(<4 x i32> %X) {
 }
 
 define i32 @test5(<4 x i32> %X) {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NEXT: extractelement
 ; CHECK-NEXT: ret 
         %tmp152.i53899.i = shufflevector <4 x i32> %X, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 undef, i32 undef>
@@ -42,7 +42,7 @@ define i32 @test5(<4 x i32> %X) {
 }
 
 define float @test6(<4 x float> %X) {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: extractelement
 ; CHECK-NEXT: ret 
         %X1 = bitcast <4 x float> %X to <4 x i32>
@@ -53,7 +53,7 @@ define float @test6(<4 x float> %X) {
 }
 
 define <4 x float> @test7(<4 x float> %tmp45.i) {
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NEXT: ret <4 x float> %tmp45.i
         %tmp1642.i = shufflevector <4 x float> %tmp45.i, <4 x float> undef, <4 x i32> < i32 0, i32 1, i32 6, i32 7 >
         ret <4 x float> %tmp1642.i
@@ -61,7 +61,7 @@ define <4 x float> @test7(<4 x float> %tmp45.i) {
 
 ; This should turn into a single shuffle.
 define <4 x float> @test8(<4 x float> %tmp, <4 x float> %tmp1) {
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK-NEXT: shufflevector
 ; CHECK-NEXT: ret
         %tmp4 = extractelement <4 x float> %tmp, i32 1
@@ -77,7 +77,7 @@ define <4 x float> @test8(<4 x float> %tmp, <4 x float> %tmp1) {
 ; Test fold of two shuffles where the first shuffle vectors inputs are a
 ; different length then the second.
 define <4 x i8> @test9(<16 x i8> %tmp6) nounwind {
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NEXT: shufflevector
 ; CHECK-NEXT: ret
 	%tmp7 = shufflevector <16 x i8> %tmp6, <16 x i8> undef, <4 x i32> < i32 13, i32 9, i32 4, i32 13 >		; <<4 x i8>> [#uses=1]
@@ -89,7 +89,7 @@ define <4 x i8> @test9(<16 x i8> %tmp6) nounwind {
 ; mask values of 2*N, where N is the mask length.  These shuffles should not
 ; be folded (because [8,9,4,8] may not be a mask supported by the target).
 define <4 x i8> @test9a(<16 x i8> %tmp6) nounwind {
-; CHECK: @test9a
+; CHECK-LABEL: @test9a(
 ; CHECK-NEXT: shufflevector
 ; CHECK-NEXT: shufflevector
 ; CHECK-NEXT: ret
@@ -101,7 +101,7 @@ define <4 x i8> @test9a(<16 x i8> %tmp6) nounwind {
 ; Test fold of two shuffles where the first shuffle vectors inputs are a
 ; different length then the second.
 define <4 x i8> @test9b(<4 x i8> %tmp6, <4 x i8> %tmp7) nounwind {
-; CHECK: @test9
+; CHECK-LABEL: @test9b(
 ; CHECK-NEXT: shufflevector
 ; CHECK-NEXT: ret
   %tmp1 = shufflevector <4 x i8> %tmp6, <4 x i8> %tmp7, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 4, i32 5, i32 2, i32 3>		; <<4 x i8>> [#uses=1]
@@ -111,7 +111,7 @@ define <4 x i8> @test9b(<4 x i8> %tmp6, <4 x i8> %tmp7) nounwind {
 
 ; Redundant vector splats should be removed.  Radar 8597790.
 define <4 x i32> @test10(<4 x i32> %tmp5) nounwind {
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK-NEXT: shufflevector
 ; CHECK-NEXT: ret
   %tmp6 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
@@ -122,7 +122,7 @@ define <4 x i32> @test10(<4 x i32> %tmp5) nounwind {
 ; Test fold of two shuffles where the two shufflevector inputs's op1 are
 ; the same
 define <8 x i8> @test11(<16 x i8> %tmp6) nounwind {
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK-NEXT: shufflevector <16 x i8> %tmp6, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
 ; CHECK-NEXT: ret
   %tmp1 = shufflevector <16 x i8> %tmp6, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>		; <<4 x i8>> [#uses=1]
@@ -134,7 +134,7 @@ define <8 x i8> @test11(<16 x i8> %tmp6) nounwind {
 ; Test fold of two shuffles where the first shufflevector's inputs are
 ; the same as the second
 define <8 x i8> @test12(<8 x i8> %tmp6, <8 x i8> %tmp2) nounwind {
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK-NEXT: shufflevector <8 x i8> %tmp6, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 9, i32 8, i32 11, i32 12>
 ; CHECK-NEXT: ret
   %tmp1 = shufflevector <8 x i8> %tmp6, <8 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 undef, i32 7>	; <<8 x i8>> [#uses=1]
@@ -145,7 +145,7 @@ define <8 x i8> @test12(<8 x i8> %tmp6, <8 x i8> %tmp2) nounwind {
 ; Test fold of two shuffles where the first shufflevector's inputs are
 ; the same as the second
 define <8 x i8> @test12a(<8 x i8> %tmp6, <8 x i8> %tmp2) nounwind {
-; CHECK: @test12a
+; CHECK-LABEL: @test12a(
 ; CHECK-NEXT: shufflevector <8 x i8> %tmp2, <8 x i8> %tmp6, <8 x i32> <i32 0, i32 3, i32 1, i32 4, i32 8, i32 9, i32 10, i32 11>
 ; CHECK-NEXT: ret
   %tmp1 = shufflevector <8 x i8> %tmp6, <8 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 undef, i32 7>	; <<8 x i8>> [#uses=1]
@@ -154,7 +154,7 @@ define <8 x i8> @test12a(<8 x i8> %tmp6, <8 x i8> %tmp2) nounwind {
 }
 
 define <2 x i8> @test13a(i8 %x1, i8 %x2) {
-; CHECK: @test13a
+; CHECK-LABEL: @test13a(
 ; CHECK-NEXT: insertelement {{.*}} undef, i8 %x1, i32 1
 ; CHECK-NEXT: insertelement {{.*}} i8 %x2, i32 0
 ; CHECK-NEXT: add {{.*}} <i8 7, i8 5>
@@ -167,7 +167,7 @@ define <2 x i8> @test13a(i8 %x1, i8 %x2) {
 }
 
 define <2 x i8> @test13b(i8 %x) {
-; CHECK: @test13b
+; CHECK-LABEL: @test13b(
 ; CHECK-NEXT: insertelement <2 x i8> undef, i8 %x, i32 1
 ; CHECK-NEXT: ret
   %A = insertelement <2 x i8> undef, i8 %x, i32 0
@@ -176,7 +176,7 @@ define <2 x i8> @test13b(i8 %x) {
 }
 
 define <2 x i8> @test13c(i8 %x1, i8 %x2) {
-; CHECK: @test13c
+; CHECK-LABEL: @test13c(
 ; CHECK-NEXT: insertelement <2 x i8> {{.*}}, i32 0
 ; CHECK-NEXT: insertelement <2 x i8> {{.*}}, i32 1
 ; CHECK-NEXT: ret
@@ -185,3 +185,18 @@ define <2 x i8> @test13c(i8 %x1, i8 %x2) {
   %C = shufflevector <4 x i8> %B, <4 x i8> undef, <2 x i32> <i32 0, i32 2>
   ret <2 x i8> %C
 }
+
+define void @test14(i16 %conv10) {
+  %tmp = alloca <4 x i16>, align 8
+  %vecinit6 = insertelement <4 x i16> undef, i16 23, i32 3
+  store <4 x i16> %vecinit6, <4 x i16>* undef
+  %tmp1 = load <4 x i16>* undef
+  %vecinit11 = insertelement <4 x i16> undef, i16 %conv10, i32 3
+  %div = udiv <4 x i16> %tmp1, %vecinit11
+  store <4 x i16> %div, <4 x i16>* %tmp
+  %tmp4 = load <4 x i16>* %tmp
+  %tmp5 = shufflevector <4 x i16> %tmp4, <4 x i16> undef, <2 x i32> <i32 2, i32 0>
+  %cmp = icmp ule <2 x i16> %tmp5, undef
+  %sext = sext <2 x i1> %cmp to <2 x i16>
+  ret void
+}
diff --git a/test/Transforms/InstCombine/vector-casts.ll b/test/Transforms/InstCombine/vector-casts.ll
index 2f2990b..ca97b34 100644
--- a/test/Transforms/InstCombine/vector-casts.ll
+++ b/test/Transforms/InstCombine/vector-casts.ll
@@ -5,7 +5,7 @@ define <2 x i1> @test1(<2 x i64> %a) {
   %t = trunc <2 x i64> %a to <2 x i1>
   ret <2 x i1> %t
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK:   and <2 x i64> %a, <i64 1, i64 1>
 ; CHECK:   icmp ne <2 x i64> %1, zeroinitializer
 }
@@ -16,7 +16,7 @@ define <2 x i64> @test2(<2 x i64> %a) {
   %t = ashr <2 x i64> %b, <i64 1, i64 1>
   ret <2 x i64> %t
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK:   and <2 x i64> %a, <i64 65535, i64 65535>
 ; CHECK:   lshr <2 x i64> %b, <i64 1, i64 1>
 }
@@ -33,7 +33,7 @@ entry:
 	%conv = bitcast <4 x i32> %and to <2 x i64>
 	ret <2 x i64> %conv
         
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK:   fcmp ord <4 x float> %a, %b
 }
 
@@ -46,7 +46,7 @@ entry:
 	%or = or <4 x i32> %sext, %sext5
 	%conv = bitcast <4 x i32> %or to <2 x i64>
 	ret <2 x i64> %conv
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK:   fcmp uno <4 x float> %a, %b
 }
 
@@ -62,7 +62,7 @@ entry:
 	%conv = bitcast <4 x i32> %and to <2 x i64>
 	ret <2 x i64> %conv
         
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK:   sext <4 x i1> %cmp to <4 x i32>	
 ; The sext-and pair is canonicalized to a select.
 ; CHECK:   select <4 x i1> %cmp4, <4 x i32>	%sext, <4 x i32> zeroinitializer
@@ -126,7 +126,7 @@ define <2 x double> @fc(<2 x double> %t) {
 ; PR9228
 ; This was a crasher, so no CHECK statements.
 define <4 x float> @f(i32 %a) nounwind alwaysinline {
-; CHECK: @f
+; CHECK-LABEL: @f(
 entry:
   %dim = insertelement <4 x i32> undef, i32 %a, i32 0
   %dim30 = insertelement <4 x i32> %dim, i32 %a, i32 1
diff --git a/test/Transforms/InstCombine/vector-mul.ll b/test/Transforms/InstCombine/vector-mul.ll
index 4e4417f..284d407 100644
--- a/test/Transforms/InstCombine/vector-mul.ll
+++ b/test/Transforms/InstCombine/vector-mul.ll
@@ -9,7 +9,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @Zero_i8
+; CHECK-LABEL: @Zero_i8(
 ; CHECK: ret <4 x i8> zeroinitializer
 
 define <4 x i8> @Identity_i8(<4 x i8> %InVec)  {
@@ -18,7 +18,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @Identity_i8
+; CHECK-LABEL: @Identity_i8(
 ; CHECK: ret <4 x i8> %InVec
 
 define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec)  {
@@ -27,7 +27,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @AddToSelf_i8
+; CHECK-LABEL: @AddToSelf_i8(
 ; CHECK: shl <4 x i8> %InVec, <i8 1, i8 1, i8 1, i8 1>
 ; CHECK: ret
 
@@ -37,7 +37,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @SplatPow2Test1_i8
+; CHECK-LABEL: @SplatPow2Test1_i8(
 ; CHECK: shl <4 x i8> %InVec, <i8 2, i8 2, i8 2, i8 2>
 ; CHECK: ret
 
@@ -47,7 +47,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @SplatPow2Test2_i8
+; CHECK-LABEL: @SplatPow2Test2_i8(
 ; CHECK: shl <4 x i8> %InVec, <i8 3, i8 3, i8 3, i8 3>
 ; CHECK: ret
 
@@ -57,7 +57,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @MulTest1_i8
+; CHECK-LABEL: @MulTest1_i8(
 ; CHECK: shl <4 x i8> %InVec, <i8 0, i8 1, i8 2, i8 3>
 ; CHECK: ret
 
@@ -67,7 +67,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @MulTest2_i8
+; CHECK-LABEL: @MulTest2_i8(
 ; CHECK: mul <4 x i8> %InVec, <i8 3, i8 3, i8 3, i8 3>
 ; CHECK: ret
 
@@ -77,7 +77,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @MulTest3_i8
+; CHECK-LABEL: @MulTest3_i8(
 ; CHECK: shl <4 x i8> %InVec, <i8 2, i8 2, i8 1, i8 1>
 ; CHECK: ret
 
@@ -88,7 +88,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @MulTest4_i8
+; CHECK-LABEL: @MulTest4_i8(
 ; CHECK: mul <4 x i8> %InVec, <i8 4, i8 4, i8 0, i8 1>
 ; CHECK: ret
 
@@ -98,7 +98,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @Zero_i16
+; CHECK-LABEL: @Zero_i16(
 ; CHECK: ret <4 x i16> zeroinitializer
 
 define <4 x i16> @Identity_i16(<4 x i16> %InVec)  {
@@ -107,7 +107,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @Identity_i16
+; CHECK-LABEL: @Identity_i16(
 ; CHECK: ret <4 x i16> %InVec
 
 define <4 x i16> @AddToSelf_i16(<4 x i16> %InVec)  {
@@ -116,7 +116,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @AddToSelf_i16
+; CHECK-LABEL: @AddToSelf_i16(
 ; CHECK: shl <4 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1>
 ; CHECK: ret
 
@@ -126,7 +126,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @SplatPow2Test1_i16
+; CHECK-LABEL: @SplatPow2Test1_i16(
 ; CHECK: shl <4 x i16> %InVec, <i16 2, i16 2, i16 2, i16 2>
 ; CHECK: ret
 
@@ -136,7 +136,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @SplatPow2Test2_i16
+; CHECK-LABEL: @SplatPow2Test2_i16(
 ; CHECK: shl <4 x i16> %InVec, <i16 3, i16 3, i16 3, i16 3>
 ; CHECK: ret
 
@@ -146,7 +146,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @MulTest1_i16
+; CHECK-LABEL: @MulTest1_i16(
 ; CHECK: shl <4 x i16> %InVec, <i16 0, i16 1, i16 2, i16 3>
 ; CHECK: ret
 
@@ -156,7 +156,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @MulTest2_i16
+; CHECK-LABEL: @MulTest2_i16(
 ; CHECK: mul <4 x i16> %InVec, <i16 3, i16 3, i16 3, i16 3>
 ; CHECK: ret
 
@@ -166,7 +166,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @MulTest3_i16
+; CHECK-LABEL: @MulTest3_i16(
 ; CHECK: shl <4 x i16> %InVec, <i16 2, i16 2, i16 1, i16 1>
 ; CHECK: ret
 
@@ -176,7 +176,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @MulTest4_i16
+; CHECK-LABEL: @MulTest4_i16(
 ; CHECK: mul <4 x i16> %InVec, <i16 4, i16 4, i16 0, i16 2>
 ; CHECK: ret
 
@@ -186,7 +186,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @Zero_i32
+; CHECK-LABEL: @Zero_i32(
 ; CHECK: ret <4 x i32> zeroinitializer
 
 define <4 x i32> @Identity_i32(<4 x i32> %InVec)  {
@@ -195,7 +195,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @Identity_i32
+; CHECK-LABEL: @Identity_i32(
 ; CHECK: ret <4 x i32> %InVec
 
 define <4 x i32> @AddToSelf_i32(<4 x i32> %InVec)  {
@@ -204,7 +204,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @AddToSelf_i32
+; CHECK-LABEL: @AddToSelf_i32(
 ; CHECK: shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
 ; CHECK: ret
 
@@ -215,7 +215,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @SplatPow2Test1_i32
+; CHECK-LABEL: @SplatPow2Test1_i32(
 ; CHECK: shl <4 x i32> %InVec, <i32 2, i32 2, i32 2, i32 2>
 ; CHECK: ret
 
@@ -225,7 +225,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @SplatPow2Test2_i32
+; CHECK-LABEL: @SplatPow2Test2_i32(
 ; CHECK: shl <4 x i32> %InVec, <i32 3, i32 3, i32 3, i32 3>
 ; CHECK: ret
 
@@ -235,7 +235,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @MulTest1_i32
+; CHECK-LABEL: @MulTest1_i32(
 ; CHECK: shl <4 x i32> %InVec, <i32 0, i32 1, i32 2, i32 3>
 ; CHECK: ret
 
@@ -245,7 +245,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @MulTest2_i32
+; CHECK-LABEL: @MulTest2_i32(
 ; CHECK: mul <4 x i32> %InVec, <i32 3, i32 3, i32 3, i32 3>
 ; CHECK: ret
 
@@ -255,7 +255,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @MulTest3_i32
+; CHECK-LABEL: @MulTest3_i32(
 ; CHECK: shl <4 x i32> %InVec, <i32 2, i32 2, i32 1, i32 1>
 ; CHECK: ret
 
@@ -266,7 +266,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @MulTest4_i32
+; CHECK-LABEL: @MulTest4_i32(
 ; CHECK: mul <4 x i32> %InVec, <i32 4, i32 4, i32 0, i32 1>
 ; CHECK: ret
 
@@ -276,7 +276,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @Zero_i64
+; CHECK-LABEL: @Zero_i64(
 ; CHECK: ret <4 x i64> zeroinitializer
 
 define <4 x i64> @Identity_i64(<4 x i64> %InVec)  {
@@ -285,7 +285,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @Identity_i64
+; CHECK-LABEL: @Identity_i64(
 ; CHECK: ret <4 x i64> %InVec
 
 define <4 x i64> @AddToSelf_i64(<4 x i64> %InVec)  {
@@ -294,7 +294,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @AddToSelf_i64
+; CHECK-LABEL: @AddToSelf_i64(
 ; CHECK: shl <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
 ; CHECK: ret
 
@@ -304,7 +304,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @SplatPow2Test1_i64
+; CHECK-LABEL: @SplatPow2Test1_i64(
 ; CHECK: shl <4 x i64> %InVec, <i64 2, i64 2, i64 2, i64 2>
 ; CHECK: ret
 
@@ -314,7 +314,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @SplatPow2Test2_i64
+; CHECK-LABEL: @SplatPow2Test2_i64(
 ; CHECK: shl <4 x i64> %InVec, <i64 3, i64 3, i64 3, i64 3>
 ; CHECK: ret
 
@@ -324,7 +324,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @MulTest1_i64
+; CHECK-LABEL: @MulTest1_i64(
 ; CHECK: shl <4 x i64> %InVec, <i64 0, i64 1, i64 2, i64 3>
 ; CHECK: ret
 
@@ -334,7 +334,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @MulTest2_i64
+; CHECK-LABEL: @MulTest2_i64(
 ; CHECK: mul <4 x i64> %InVec, <i64 3, i64 3, i64 3, i64 3>
 ; CHECK: ret
 
@@ -344,7 +344,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @MulTest3_i64
+; CHECK-LABEL: @MulTest3_i64(
 ; CHECK: shl <4 x i64> %InVec, <i64 2, i64 2, i64 1, i64 1>
 ; CHECK: ret
 
@@ -354,7 +354,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @MulTest4_i64
+; CHECK-LABEL: @MulTest4_i64(
 ; CHECK: mul <4 x i64> %InVec, <i64 4, i64 4, i64 0, i64 1>
 ; CHECK: ret
 
@@ -369,7 +369,7 @@ entry:
   ret <4 x i8> %mul
 }
 
-; CHECK: @ShiftMulTest1
+; CHECK-LABEL: @ShiftMulTest1(
 ; CHECK: mul <4 x i8> %InVec, <i8 12, i8 12, i8 12, i8 12>
 ; CHECK: ret
 
@@ -380,7 +380,7 @@ entry:
   ret <4 x i16> %mul
 }
 
-; CHECK: @ShiftMulTest2
+; CHECK-LABEL: @ShiftMulTest2(
 ; CHECK: mul <4 x i16> %InVec, <i16 12, i16 12, i16 12, i16 12>
 ; CHECK: ret
 
@@ -391,7 +391,7 @@ entry:
   ret <4 x i32> %mul
 }
 
-; CHECK: @ShiftMulTest3
+; CHECK-LABEL: @ShiftMulTest3(
 ; CHECK: mul <4 x i32> %InVec, <i32 12, i32 12, i32 12, i32 12>
 ; CHECK: ret
 
@@ -402,7 +402,7 @@ entry:
   ret <4 x i64> %mul
 }
 
-; CHECK: @ShiftMulTest4
+; CHECK-LABEL: @ShiftMulTest4(
 ; CHECK: mul <4 x i64> %InVec, <i64 12, i64 12, i64 12, i64 12>
 ; CHECK: ret
 
diff --git a/test/Transforms/InstCombine/vector_gep2.ll b/test/Transforms/InstCombine/vector_gep2.ll
index 20165b1..42057d6 100644
--- a/test/Transforms/InstCombine/vector_gep2.ll
+++ b/test/Transforms/InstCombine/vector_gep2.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-unknown-linux-gnu"
 
 define <2 x i8*> @testa(<2 x i8*> %a) {
-; CHECK: @testa
+; CHECK-LABEL: @testa(
   %g = getelementptr <2 x i8*> %a, <2 x i32> <i32 0, i32 1>
 ; CHECK: getelementptr <2 x i8*> %a, <2 x i64> <i64 0, i64 1>
   ret <2 x i8*> %g
diff --git a/test/Transforms/InstCombine/weak-symbols.ll b/test/Transforms/InstCombine/weak-symbols.ll
index 0039b59..ec946ea 100644
--- a/test/Transforms/InstCombine/weak-symbols.ll
+++ b/test/Transforms/InstCombine/weak-symbols.ll
@@ -8,7 +8,7 @@
 @.str = private constant [2 x i8] c"y\00"
 
 define i32 @foo() nounwind {
-; CHECK: define i32 @foo
+; CHECK-LABEL: define i32 @foo(
 ; CHECK: call i32 @strcmp
 ; CHECK: ret i32 %temp1
 
@@ -20,7 +20,7 @@ entry:
 }
 
 define i32 @bar() nounwind {
-; CHECK: define i32 @bar
+; CHECK-LABEL: define i32 @bar(
 ; CHECK: ret i32 0
 
 entry:
diff --git a/test/Transforms/InstCombine/win-math.ll b/test/Transforms/InstCombine/win-math.ll
index 367e5b8..df3ac93 100644
--- a/test/Transforms/InstCombine/win-math.ll
+++ b/test/Transforms/InstCombine/win-math.ll
@@ -9,7 +9,7 @@
 
 declare double @acos(double %x)
 define float @float_acos(float %x) nounwind readnone {
-; WIN32: @float_acos
+; WIN32-LABEL: @float_acos(
 ; WIN32-NOT: float @acosf
 ; WIN32: double @acos
     %1 = fpext float %x to double
@@ -20,7 +20,7 @@ define float @float_acos(float %x) nounwind readnone {
 
 declare double @asin(double %x)
 define float @float_asin(float %x) nounwind readnone {
-; WIN32: @float_asin
+; WIN32-LABEL: @float_asin(
 ; WIN32-NOT: float @asinf
 ; WIN32: double @asin
     %1 = fpext float %x to double
@@ -31,7 +31,7 @@ define float @float_asin(float %x) nounwind readnone {
 
 declare double @atan(double %x)
 define float @float_atan(float %x) nounwind readnone {
-; WIN32: @float_atan
+; WIN32-LABEL: @float_atan(
 ; WIN32-NOT: float @atanf
 ; WIN32: double @atan
     %1 = fpext float %x to double
@@ -42,7 +42,7 @@ define float @float_atan(float %x) nounwind readnone {
 
 declare double @atan2(double %x, double %y)
 define float @float_atan2(float %x, float %y) nounwind readnone {
-; WIN32: @float_atan2
+; WIN32-LABEL: @float_atan2(
 ; WIN32-NOT: float @atan2f
 ; WIN32: double @atan2
     %1 = fpext float %x to double
@@ -54,16 +54,16 @@ define float @float_atan2(float %x, float %y) nounwind readnone {
 
 declare double @ceil(double %x)
 define float @float_ceil(float %x) nounwind readnone {
-; WIN32: @float_ceil
+; WIN32-LABEL: @float_ceil(
 ; WIN32-NOT: float @ceilf
 ; WIN32: double @ceil
-; WIN64: @float_ceil
+; WIN64-LABEL: @float_ceil(
 ; WIN64: float @ceilf
 ; WIN64-NOT: double @ceil
-; MINGW32: @float_ceil
+; MINGW32-LABEL: @float_ceil(
 ; MINGW32: float @ceilf
 ; MINGW32-NOT: double @ceil
-; MINGW64: @float_ceil
+; MINGW64-LABEL: @float_ceil(
 ; MINGW64: float @ceilf
 ; MINGW64-NOT: double @ceil
     %1 = fpext float %x to double
@@ -74,7 +74,7 @@ define float @float_ceil(float %x) nounwind readnone {
 
 declare double @_copysign(double %x)
 define float @float_copysign(float %x) nounwind readnone {
-; WIN32: @float_copysign
+; WIN32-LABEL: @float_copysign(
 ; WIN32-NOT: float @copysignf
 ; WIN32-NOT: float @_copysignf
 ; WIN32: double @_copysign
@@ -86,7 +86,7 @@ define float @float_copysign(float %x) nounwind readnone {
 
 declare double @cos(double %x)
 define float @float_cos(float %x) nounwind readnone {
-; WIN32: @float_cos
+; WIN32-LABEL: @float_cos(
 ; WIN32-NOT: float @cosf
 ; WIN32: double @cos
     %1 = fpext float %x to double
@@ -97,7 +97,7 @@ define float @float_cos(float %x) nounwind readnone {
 
 declare double @cosh(double %x)
 define float @float_cosh(float %x) nounwind readnone {
-; WIN32: @float_cosh
+; WIN32-LABEL: @float_cosh(
 ; WIN32-NOT: float @coshf
 ; WIN32: double @cosh
     %1 = fpext float %x to double
@@ -108,7 +108,7 @@ define float @float_cosh(float %x) nounwind readnone {
 
 declare double @exp(double %x, double %y)
 define float @float_exp(float %x, float %y) nounwind readnone {
-; WIN32: @float_exp
+; WIN32-LABEL: @float_exp(
 ; WIN32-NOT: float @expf
 ; WIN32: double @exp
     %1 = fpext float %x to double
@@ -120,10 +120,10 @@ define float @float_exp(float %x, float %y) nounwind readnone {
 
 declare double @fabs(double %x, double %y)
 define float @float_fabs(float %x, float %y) nounwind readnone {
-; WIN32: @float_fabs
+; WIN32-LABEL: @float_fabs(
 ; WIN32-NOT: float @fabsf
 ; WIN32: double @fabs
-; WIN64: @float_fabs
+; WIN64-LABEL: @float_fabs(
 ; WIN64-NOT: float @fabsf
 ; WIN64: double @fabs
     %1 = fpext float %x to double
@@ -135,16 +135,16 @@ define float @float_fabs(float %x, float %y) nounwind readnone {
 
 declare double @floor(double %x)
 define float @float_floor(float %x) nounwind readnone {
-; WIN32: @float_floor
+; WIN32-LABEL: @float_floor(
 ; WIN32-NOT: float @floorf
 ; WIN32: double @floor
-; WIN64: @float_floor
+; WIN64-LABEL: @float_floor(
 ; WIN64: float @floorf
 ; WIN64-NOT: double @floor
-; MINGW32: @float_floor
+; MINGW32-LABEL: @float_floor(
 ; MINGW32: float @floorf
 ; MINGW32-NOT: double @floor
-; MINGW64: @float_floor
+; MINGW64-LABEL: @float_floor(
 ; MINGW64: float @floorf
 ; MINGW64-NOT: double @floor
     %1 = fpext float %x to double
@@ -155,7 +155,7 @@ define float @float_floor(float %x) nounwind readnone {
 
 declare double @fmod(double %x, double %y)
 define float @float_fmod(float %x, float %y) nounwind readnone {
-; WIN32: @float_fmod
+; WIN32-LABEL: @float_fmod(
 ; WIN32-NOT: float @fmodf
 ; WIN32: double @fmod
     %1 = fpext float %x to double
@@ -167,7 +167,7 @@ define float @float_fmod(float %x, float %y) nounwind readnone {
 
 declare double @log(double %x)
 define float @float_log(float %x) nounwind readnone {
-; WIN32: @float_log
+; WIN32-LABEL: @float_log(
 ; WIN32-NOT: float @logf
 ; WIN32: double @log
     %1 = fpext float %x to double
@@ -178,7 +178,7 @@ define float @float_log(float %x) nounwind readnone {
 
 declare double @pow(double %x, double %y)
 define float @float_pow(float %x, float %y) nounwind readnone {
-; WIN32: @float_pow
+; WIN32-LABEL: @float_pow(
 ; WIN32-NOT: float @powf
 ; WIN32: double @pow
     %1 = fpext float %x to double
@@ -190,7 +190,7 @@ define float @float_pow(float %x, float %y) nounwind readnone {
 
 declare double @sin(double %x)
 define float @float_sin(float %x) nounwind readnone {
-; WIN32: @float_sin
+; WIN32-LABEL: @float_sin(
 ; WIN32-NOT: float @sinf
 ; WIN32: double @sin
     %1 = fpext float %x to double
@@ -201,7 +201,7 @@ define float @float_sin(float %x) nounwind readnone {
 
 declare double @sinh(double %x)
 define float @float_sinh(float %x) nounwind readnone {
-; WIN32: @float_sinh
+; WIN32-LABEL: @float_sinh(
 ; WIN32-NOT: float @sinhf
 ; WIN32: double @sinh
     %1 = fpext float %x to double
@@ -212,16 +212,16 @@ define float @float_sinh(float %x) nounwind readnone {
 
 declare double @sqrt(double %x)
 define float @float_sqrt(float %x) nounwind readnone {
-; WIN32: @float_sqrt
+; WIN32-LABEL: @float_sqrt(
 ; WIN32-NOT: float @sqrtf
 ; WIN32: double @sqrt
-; WIN64: @float_sqrt
+; WIN64-LABEL: @float_sqrt(
 ; WIN64: float @sqrtf
 ; WIN64-NOT: double @sqrt
-; MINGW32: @float_sqrt
+; MINGW32-LABEL: @float_sqrt(
 ; MINGW32: float @sqrtf
 ; MINGW32-NOT: double @sqrt
-; MINGW64: @float_sqrt
+; MINGW64-LABEL: @float_sqrt(
 ; MINGW64: float @sqrtf
 ; MINGW64-NOT: double @sqrt
     %1 = fpext float %x to double
@@ -232,7 +232,7 @@ define float @float_sqrt(float %x) nounwind readnone {
 
 declare double @tan(double %x)
 define float @float_tan(float %x) nounwind readnone {
-; WIN32: @float_tan
+; WIN32-LABEL: @float_tan(
 ; WIN32-NOT: float @tanf
 ; WIN32: double @tan
     %1 = fpext float %x to double
@@ -243,7 +243,7 @@ define float @float_tan(float %x) nounwind readnone {
 
 declare double @tanh(double %x)
 define float @float_tanh(float %x) nounwind readnone {
-; WIN32: @float_tanh
+; WIN32-LABEL: @float_tanh(
 ; WIN32-NOT: float @tanhf
 ; WIN32: double @tanh
     %1 = fpext float %x to double
@@ -255,16 +255,16 @@ define float @float_tanh(float %x) nounwind readnone {
 ; win32 does not have round; mingw32 does
 declare double @round(double %x)
 define float @float_round(float %x) nounwind readnone {
-; WIN32: @float_round
+; WIN32-LABEL: @float_round(
 ; WIN32-NOT: float @roundf
 ; WIN32: double @round
-; WIN64: @float_round
+; WIN64-LABEL: @float_round(
 ; WIN64-NOT: float @roundf
 ; WIN64: double @round
-; MINGW32: @float_round
+; MINGW32-LABEL: @float_round(
 ; MINGW32: float @roundf
 ; MINGW32-NOT: double @round
-; MINGW64: @float_round
+; MINGW64-LABEL: @float_round(
 ; MINGW64: float @roundf
 ; MINGW64-NOT: double @round
     %1 = fpext float %x to double
diff --git a/test/Transforms/InstCombine/xor2.ll b/test/Transforms/InstCombine/xor2.ll
index be06d79..d153e03 100644
--- a/test/Transforms/InstCombine/xor2.ll
+++ b/test/Transforms/InstCombine/xor2.ll
@@ -4,7 +4,7 @@
 
 ; PR1253
 define i1 @test0(i32 %A) {
-; CHECK: @test0
+; CHECK-LABEL: @test0(
 ; CHECK: %C = icmp slt i32 %A, 0
 	%B = xor i32 %A, -2147483648
 	%C = icmp sgt i32 %B, -1
@@ -12,7 +12,7 @@ define i1 @test0(i32 %A) {
 }
 
 define i1 @test1(i32 %A) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %C = icmp slt i32 %A, 0
 	%B = xor i32 %A, 12345
 	%C = icmp slt i32 %B, 0
@@ -21,7 +21,7 @@ define i1 @test1(i32 %A) {
 
 ; PR1014
 define i32 @test2(i32 %tmp1) {
-; CHECK:      @test2
+; CHECK-LABEL:      @test2(
 ; CHECK-NEXT:   and i32 %tmp1, 32
 ; CHECK-NEXT:   or i32 %ovm, 8 
 ; CHECK-NEXT:   ret i32
@@ -32,7 +32,7 @@ define i32 @test2(i32 %tmp1) {
 }
 
 define i32 @test3(i32 %tmp1) {
-; CHECK:      @test3
+; CHECK-LABEL:      @test3(
 ; CHECK-NEXT:   and i32 %tmp1, 32
 ; CHECK-NEXT:   or i32 %ovm, 8
 ; CHECK-NEXT:   ret i32
@@ -47,7 +47,7 @@ define i32 @test4(i32 %A, i32 %B) {
 	%2 = ashr i32 %1, %B
 	%3 = xor i32 %2, -1
 	ret i32 %3
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: %1 = ashr i32 %A, %B
 ; CHECK: ret i32 %1
 }
@@ -62,7 +62,7 @@ test5:
   %xor1 = xor i32 %shr, 1
   %add = add i32 %xor1, %xor
   ret i32 %add
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: lshr i32 %val1, 8
 ; CHECK: ret
 }
@@ -78,7 +78,7 @@ define i32 @test6(i32 %x) {
   %shr = lshr i32 %xor, 16
   %add = add i32 %shr, %xor
   ret i32 %add
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: lshr i32 %x, 16
 ; CHECK: ret
 }
diff --git a/test/Transforms/InstCombine/zext-bool-add-sub.ll b/test/Transforms/InstCombine/zext-bool-add-sub.ll
index b531057..d7f338b 100644
--- a/test/Transforms/InstCombine/zext-bool-add-sub.ll
+++ b/test/Transforms/InstCombine/zext-bool-add-sub.ll
@@ -3,7 +3,7 @@
 
 define i32 @a(i1 zeroext %x, i1 zeroext %y) {
 entry:
-; CHECK: @a
+; CHECK-LABEL: @a(
 ; CHECK: [[TMP1:%.*]] = sext i1 %y to i32
 ; CHECK: [[TMP2:%.*]] = select i1 %x, i32 2, i32 1
 ; CHECK-NEXT: add i32 [[TMP2]], [[TMP1]]
diff --git a/test/Transforms/InstSimplify/2010-12-20-Boolean.ll b/test/Transforms/InstSimplify/2010-12-20-Boolean.ll
index 3aa1bd6..28c25c0 100644
--- a/test/Transforms/InstSimplify/2010-12-20-Boolean.ll
+++ b/test/Transforms/InstSimplify/2010-12-20-Boolean.ll
@@ -1,28 +1,28 @@
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 define i1 @add(i1 %x) {
-; CHECK: @add
+; CHECK-LABEL: @add(
   %z = add i1 %x, %x
   ret i1 %z
 ; CHECK: ret i1 false
 }
 
 define i1 @sub(i1 %x) {
-; CHECK: @sub
+; CHECK-LABEL: @sub(
   %z = sub i1 false, %x
   ret i1 %z
 ; CHECK: ret i1 %x
 }
 
 define i1 @mul(i1 %x) {
-; CHECK: @mul
+; CHECK-LABEL: @mul(
   %z = mul i1 %x, %x
   ret i1 %z
 ; CHECK: ret i1 %x
 }
 
 define i1 @ne(i1 %x) {
-; CHECK: @ne
+; CHECK-LABEL: @ne(
   %z = icmp ne i1 %x, 0
   ret i1 %z
 ; CHECK: ret i1 %x
diff --git a/test/Transforms/InstSimplify/2010-12-20-Distribute.ll b/test/Transforms/InstSimplify/2010-12-20-Distribute.ll
index d20abd6..9ea0a5e 100644
--- a/test/Transforms/InstSimplify/2010-12-20-Distribute.ll
+++ b/test/Transforms/InstSimplify/2010-12-20-Distribute.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 define i32 @factorize(i32 %x, i32 %y) {
-; CHECK: @factorize
+; CHECK-LABEL: @factorize(
 ; (X | 1) & (X | 2) -> X | (1 & 2) -> X
   %l = or i32 %x, 1
   %r = or i32 %x, 2
@@ -11,7 +11,7 @@ define i32 @factorize(i32 %x, i32 %y) {
 }
 
 define i32 @factorize2(i32 %x) {
-; CHECK: @factorize2
+; CHECK-LABEL: @factorize2(
 ; 3*X - 2*X -> X
   %l = mul i32 3, %x
   %r = mul i32 2, %x
@@ -21,7 +21,7 @@ define i32 @factorize2(i32 %x) {
 }
 
 define i32 @factorize3(i32 %x, i32 %a, i32 %b) {
-; CHECK: @factorize3
+; CHECK-LABEL: @factorize3(
 ; (X | (A|B)) & (X | B) -> X | ((A|B) & B) -> X | B
   %aORb = or i32 %a, %b
   %l = or i32 %x, %aORb
@@ -32,7 +32,7 @@ define i32 @factorize3(i32 %x, i32 %a, i32 %b) {
 }
 
 define i32 @factorize4(i32 %x, i32 %y) {
-; CHECK: @factorize4
+; CHECK-LABEL: @factorize4(
   %sh = shl i32 %y, 1
   %ml = mul i32 %sh, %x
   %mr = mul i32 %x, %y
@@ -42,7 +42,7 @@ define i32 @factorize4(i32 %x, i32 %y) {
 }
 
 define i32 @factorize5(i32 %x, i32 %y) {
-; CHECK: @factorize5
+; CHECK-LABEL: @factorize5(
   %sh = mul i32 %y, 2
   %ml = mul i32 %sh, %x
   %mr = mul i32 %x, %y
@@ -52,7 +52,7 @@ define i32 @factorize5(i32 %x, i32 %y) {
 }
 
 define i32 @expand(i32 %x) {
-; CHECK: @expand
+; CHECK-LABEL: @expand(
 ; ((X & 1) | 2) & 1 -> ((X & 1) & 1) | (2 & 1) -> (X & 1) | 0 -> X & 1
   %a = and i32 %x, 1
   %b = or i32 %a, 2
diff --git a/test/Transforms/InstSimplify/2011-01-14-Thread.ll b/test/Transforms/InstSimplify/2011-01-14-Thread.ll
index 8fc4dc5..9de0660 100644
--- a/test/Transforms/InstSimplify/2011-01-14-Thread.ll
+++ b/test/Transforms/InstSimplify/2011-01-14-Thread.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 define i32 @shift_select(i1 %cond) {
-; CHECK: @shift_select
+; CHECK-LABEL: @shift_select(
   %s = select i1 %cond, i32 0, i32 1
   %r = lshr i32 %s, 1
   ret i32 %r
diff --git a/test/Transforms/InstSimplify/2011-02-01-Vector.ll b/test/Transforms/InstSimplify/2011-02-01-Vector.ll
index 3039a66..3cbbf35 100644
--- a/test/Transforms/InstSimplify/2011-02-01-Vector.ll
+++ b/test/Transforms/InstSimplify/2011-02-01-Vector.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 define <2 x i32> @sdiv(<2 x i32> %x) {
-; CHECK: @sdiv
+; CHECK-LABEL: @sdiv(
   %div = sdiv <2 x i32> %x, <i32 1, i32 1>
   ret <2 x i32> %div
 ; CHECK: ret <2 x i32> %x
diff --git a/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll b/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll
index d10c61f..3514b34 100644
--- a/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll
+++ b/test/Transforms/InstSimplify/2011-09-05-InsertExtractValue.ll
@@ -14,7 +14,7 @@ lpad:
   %exc_ptr2 = insertvalue { i8*, i32 } undef, i8* %exc_ptr, 0
   %filter2 = insertvalue { i8*, i32 } %exc_ptr2, i32 %filter, 1
   resume { i8*, i32 } %filter2
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NOT: extractvalue
 ; CHECK-NOT: insertvalue
 }
@@ -25,5 +25,5 @@ define { i8, i32 } @test2({ i8*, i32 } %x) {
   %ex = extractvalue { i8*, i32 } %x, 1
   %ins = insertvalue { i8, i32 } undef, i32 %ex, 1
   ret { i8, i32 } %ins
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 }
diff --git a/test/Transforms/InstSimplify/AndOrXor.ll b/test/Transforms/InstSimplify/AndOrXor.ll
index 33a4d6b..c59d6c9 100644
--- a/test/Transforms/InstSimplify/AndOrXor.ll
+++ b/test/Transforms/InstSimplify/AndOrXor.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 define i64 @pow2(i32 %x) {
-; CHECK: @pow2
+; CHECK-LABEL: @pow2(
   %negx = sub i32 0, %x
   %x2 = and i32 %x, %negx
   %e = zext i32 %x2 to i64
@@ -12,7 +12,7 @@ define i64 @pow2(i32 %x) {
 }
 
 define i64 @pow2b(i32 %x) {
-; CHECK: @pow2b
+; CHECK-LABEL: @pow2b(
   %sh = shl i32 2, %x
   %e = zext i32 %sh to i64
   %nege = sub i64 0, %e
diff --git a/test/Transforms/InstSimplify/call.ll b/test/Transforms/InstSimplify/call.ll
index cf2f847..3e1621c 100644
--- a/test/Transforms/InstSimplify/call.ll
+++ b/test/Transforms/InstSimplify/call.ll
@@ -3,7 +3,7 @@
 declare {i8, i1} @llvm.uadd.with.overflow.i8(i8 %a, i8 %b)
 
 define i1 @test_uadd1() {
-; CHECK: @test_uadd1
+; CHECK-LABEL: @test_uadd1(
   %x = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 254, i8 3)
   %overflow = extractvalue {i8, i1} %x, 1
   ret i1 %overflow
@@ -11,7 +11,7 @@ define i1 @test_uadd1() {
 }
 
 define i8 @test_uadd2() {
-; CHECK: @test_uadd2
+; CHECK-LABEL: @test_uadd2(
   %x = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 254, i8 44)
   %result = extractvalue {i8, i1} %x, 0
   ret i8 %result
@@ -21,7 +21,7 @@ define i8 @test_uadd2() {
 declare i256 @llvm.cttz.i256(i256 %src, i1 %is_zero_undef)
 
 define i256 @test_cttz() {
-; CHECK: @test_cttz
+; CHECK-LABEL: @test_cttz(
   %x = call i256 @llvm.cttz.i256(i256 10, i1 false)
   ret i256 %x
 ; CHECK-NEXT: ret i256 1
@@ -30,7 +30,7 @@ define i256 @test_cttz() {
 declare i256 @llvm.ctpop.i256(i256 %src)
 
 define i256 @test_ctpop() {
-; CHECK: @test_ctpop
+; CHECK-LABEL: @test_ctpop(
   %x = call i256 @llvm.ctpop.i256(i256 10)
   ret i256 %x
 ; CHECK-NEXT: ret i256 2
@@ -40,7 +40,7 @@ define i256 @test_ctpop() {
 declare float @fabs(float %x)
 
 define float @test_fabs_libcall() {
-; CHECK: @test_fabs_libcall
+; CHECK-LABEL: @test_fabs_libcall(
 
   %x = call float @fabs(float -42.0)
 ; This is still a real function call, so instsimplify won't nuke it -- other
@@ -61,7 +61,7 @@ declare float @llvm.nearbyint.f32(float) nounwind readnone
 
 ; Test idempotent intrinsics
 define float @test_idempotence(float %a) {
-; CHECK: @test_idempotence
+; CHECK-LABEL: @test_idempotence(
 
 ; CHECK: fabs
 ; CHECK-NOT: fabs
diff --git a/test/Transforms/InstSimplify/compare.ll b/test/Transforms/InstSimplify/compare.ll
index b764c76..0957949 100644
--- a/test/Transforms/InstSimplify/compare.ll
+++ b/test/Transforms/InstSimplify/compare.ll
@@ -2,7 +2,7 @@
 target datalayout = "p:32:32"
 
 define i1 @ptrtoint() {
-; CHECK: @ptrtoint
+; CHECK-LABEL: @ptrtoint(
   %a = alloca i8
   %tmp = ptrtoint i8* %a to i32
   %r = icmp eq i32 %tmp, 0
@@ -11,7 +11,7 @@ define i1 @ptrtoint() {
 }
 
 define i1 @bitcast() {
-; CHECK: @bitcast
+; CHECK-LABEL: @bitcast(
   %a = alloca i32
   %b = alloca i64
   %x = bitcast i32* %a to i8*
@@ -22,7 +22,7 @@ define i1 @bitcast() {
 }
 
 define i1 @gep() {
-; CHECK: @gep
+; CHECK-LABEL: @gep(
   %a = alloca [3 x i8], align 8
   %x = getelementptr inbounds [3 x i8]* %a, i32 0, i32 0
   %cmp = icmp eq i8* %x, null
@@ -31,7 +31,7 @@ define i1 @gep() {
 }
 
 define i1 @gep2() {
-; CHECK: @gep2
+; CHECK-LABEL: @gep2(
   %a = alloca [3 x i8], align 8
   %x = getelementptr inbounds [3 x i8]* %a, i32 0, i32 0
   %y = getelementptr inbounds [3 x i8]* %a, i32 0, i32 0
@@ -46,7 +46,7 @@ define i1 @gep2() {
 @gepz = extern_weak global %gept
 
 define i1 @gep3() {
-; CHECK: @gep3
+; CHECK-LABEL: @gep3(
   %x = alloca %gept, align 8
   %a = getelementptr %gept* %x, i64 0, i32 0
   %b = getelementptr %gept* %x, i64 0, i32 1
@@ -56,7 +56,7 @@ define i1 @gep3() {
 }
 
 define i1 @gep4() {
-; CHECK: @gep4
+; CHECK-LABEL: @gep4(
   %x = alloca %gept, align 8
   %a = getelementptr %gept* @gepy, i64 0, i32 0
   %b = getelementptr %gept* @gepy, i64 0, i32 1
@@ -66,7 +66,7 @@ define i1 @gep4() {
 }
 
 define i1 @gep5() {
-; CHECK: @gep5
+; CHECK-LABEL: @gep5(
   %x = alloca %gept, align 8
   %a = getelementptr inbounds %gept* %x, i64 0, i32 1
   %b = getelementptr %gept* @gepy, i64 0, i32 0
@@ -77,7 +77,7 @@ define i1 @gep5() {
 
 define i1 @gep6(%gept* %x) {
 ; Same as @gep3 but potentially null.
-; CHECK: @gep6
+; CHECK-LABEL: @gep6(
   %a = getelementptr %gept* %x, i64 0, i32 0
   %b = getelementptr %gept* %x, i64 0, i32 1
   %equal = icmp eq i32* %a, %b
@@ -86,7 +86,7 @@ define i1 @gep6(%gept* %x) {
 }
 
 define i1 @gep7(%gept* %x) {
-; CHECK: @gep7
+; CHECK-LABEL: @gep7(
   %a = getelementptr %gept* %x, i64 0, i32 0
   %b = getelementptr %gept* @gepz, i64 0, i32 0
   %equal = icmp eq i32* %a, %b
@@ -95,7 +95,7 @@ define i1 @gep7(%gept* %x) {
 }
 
 define i1 @gep8(%gept* %x) {
-; CHECK: @gep8
+; CHECK-LABEL: @gep8(
   %a = getelementptr %gept* %x, i32 1
   %b = getelementptr %gept* %x, i32 -1
   %equal = icmp ugt %gept* %a, %b
@@ -104,7 +104,7 @@ define i1 @gep8(%gept* %x) {
 }
 
 define i1 @gep9(i8* %ptr) {
-; CHECK: @gep9
+; CHECK-LABEL: @gep9(
 ; CHECK-NOT: ret
 ; CHECK: ret i1 true
 
@@ -124,7 +124,7 @@ entry:
 }
 
 define i1 @gep10(i8* %ptr) {
-; CHECK: @gep10
+; CHECK-LABEL: @gep10(
 ; CHECK-NOT: ret
 ; CHECK: ret i1 true
 
@@ -140,7 +140,7 @@ entry:
 }
 
 define i1 @gep11(i8* %ptr) {
-; CHECK: @gep11
+; CHECK-LABEL: @gep11(
 ; CHECK-NOT: ret
 ; CHECK: ret i1 true
 
@@ -153,7 +153,7 @@ entry:
 }
 
 define i1 @gep12(i8* %ptr) {
-; CHECK: @gep12
+; CHECK-LABEL: @gep12(
 ; CHECK-NOT: ret
 ; CHECK: ret i1 %cmp
 
@@ -166,7 +166,7 @@ entry:
 }
 
 define i1 @gep13(i8* %ptr) {
-; CHECK: @gep13
+; CHECK-LABEL: @gep13(
 ; We can prove this GEP is non-null because it is inbounds.
   %x = getelementptr inbounds i8* %ptr, i32 1
   %cmp = icmp eq i8* %x, null
@@ -175,7 +175,7 @@ define i1 @gep13(i8* %ptr) {
 }
 
 define i1 @gep14({ {}, i8 }* %ptr) {
-; CHECK: @gep14
+; CHECK-LABEL: @gep14(
 ; We can't simplify this because the offset of one in the GEP actually doesn't
 ; move the pointer.
   %x = getelementptr inbounds { {}, i8 }* %ptr, i32 0, i32 1
@@ -185,7 +185,7 @@ define i1 @gep14({ {}, i8 }* %ptr) {
 }
 
 define i1 @gep15({ {}, [4 x {i8, i8}]}* %ptr, i32 %y) {
-; CHECK: @gep15
+; CHECK-LABEL: @gep15(
 ; We can prove this GEP is non-null even though there is a user value, as we
 ; would necessarily violate inbounds on one side or the other.
   %x = getelementptr inbounds { {}, [4 x {i8, i8}]}* %ptr, i32 0, i32 1, i32 %y, i32 1
@@ -195,7 +195,7 @@ define i1 @gep15({ {}, [4 x {i8, i8}]}* %ptr, i32 %y) {
 }
 
 define i1 @gep16(i8* %ptr, i32 %a) {
-; CHECK: @gep16
+; CHECK-LABEL: @gep16(
 ; We can prove this GEP is non-null because it is inbounds and because we know
 ; %b is non-zero even though we don't know its value.
   %b = or i32 %a, 1
@@ -206,7 +206,7 @@ define i1 @gep16(i8* %ptr, i32 %a) {
 }
 
 define i1 @zext(i32 %x) {
-; CHECK: @zext
+; CHECK-LABEL: @zext(
   %e1 = zext i32 %x to i64
   %e2 = zext i32 %x to i64
   %r = icmp eq i64 %e1, %e2
@@ -215,7 +215,7 @@ define i1 @zext(i32 %x) {
 }
 
 define i1 @zext2(i1 %x) {
-; CHECK: @zext2
+; CHECK-LABEL: @zext2(
   %e = zext i1 %x to i32
   %c = icmp ne i32 %e, 0
   ret i1 %c
@@ -223,7 +223,7 @@ define i1 @zext2(i1 %x) {
 }
 
 define i1 @zext3() {
-; CHECK: @zext3
+; CHECK-LABEL: @zext3(
   %e = zext i1 1 to i32
   %c = icmp ne i32 %e, 0
   ret i1 %c
@@ -231,7 +231,7 @@ define i1 @zext3() {
 }
 
 define i1 @sext(i32 %x) {
-; CHECK: @sext
+; CHECK-LABEL: @sext(
   %e1 = sext i32 %x to i64
   %e2 = sext i32 %x to i64
   %r = icmp eq i64 %e1, %e2
@@ -240,7 +240,7 @@ define i1 @sext(i32 %x) {
 }
 
 define i1 @sext2(i1 %x) {
-; CHECK: @sext2
+; CHECK-LABEL: @sext2(
   %e = sext i1 %x to i32
   %c = icmp ne i32 %e, 0
   ret i1 %c
@@ -248,7 +248,7 @@ define i1 @sext2(i1 %x) {
 }
 
 define i1 @sext3() {
-; CHECK: @sext3
+; CHECK-LABEL: @sext3(
   %e = sext i1 1 to i32
   %c = icmp ne i32 %e, 0
   ret i1 %c
@@ -256,7 +256,7 @@ define i1 @sext3() {
 }
 
 define i1 @add(i32 %x, i32 %y) {
-; CHECK: @add
+; CHECK-LABEL: @add(
   %l = lshr i32 %x, 1
   %q = lshr i32 %y, 1
   %r = or i32 %q, 1
@@ -267,7 +267,7 @@ define i1 @add(i32 %x, i32 %y) {
 }
 
 define i1 @add2(i8 %x, i8 %y) {
-; CHECK: @add2
+; CHECK-LABEL: @add2(
   %l = or i8 %x, 128
   %r = or i8 %y, 129
   %s = add i8 %l, %r
@@ -277,7 +277,7 @@ define i1 @add2(i8 %x, i8 %y) {
 }
 
 define i1 @add3(i8 %x, i8 %y) {
-; CHECK: @add3
+; CHECK-LABEL: @add3(
   %l = zext i8 %x to i32
   %r = zext i8 %y to i32
   %s = add i32 %l, %r
@@ -287,7 +287,7 @@ define i1 @add3(i8 %x, i8 %y) {
 }
 
 define i1 @add4(i32 %x, i32 %y) {
-; CHECK: @add4
+; CHECK-LABEL: @add4(
   %z = add nsw i32 %y, 1
   %s1 = add nsw i32 %x, %y
   %s2 = add nsw i32 %x, %z
@@ -297,7 +297,7 @@ define i1 @add4(i32 %x, i32 %y) {
 }
 
 define i1 @add5(i32 %x, i32 %y) {
-; CHECK: @add5
+; CHECK-LABEL: @add5(
   %z = add nuw i32 %y, 1
   %s1 = add nuw i32 %x, %z
   %s2 = add nuw i32 %x, %y
@@ -307,7 +307,7 @@ define i1 @add5(i32 %x, i32 %y) {
 }
 
 define i1 @add6(i64 %A, i64 %B) {
-; CHECK: @add6
+; CHECK-LABEL: @add6(
   %s1 = add i64 %A, %B
   %s2 = add i64 %B, %A
   %cmp = icmp eq i64 %s1, %s2
@@ -316,7 +316,7 @@ define i1 @add6(i64 %A, i64 %B) {
 }
 
 define i1 @addpowtwo(i32 %x, i32 %y) {
-; CHECK: @addpowtwo
+; CHECK-LABEL: @addpowtwo(
   %l = lshr i32 %x, 1
   %r = shl i32 1, %y
   %s = add i32 %l, %r
@@ -326,7 +326,7 @@ define i1 @addpowtwo(i32 %x, i32 %y) {
 }
 
 define i1 @or(i32 %x) {
-; CHECK: @or
+; CHECK-LABEL: @or(
   %o = or i32 %x, 1
   %c = icmp eq i32 %o, 0
   ret i1 %c
@@ -334,7 +334,7 @@ define i1 @or(i32 %x) {
 }
 
 define i1 @shl(i32 %x) {
-; CHECK: @shl
+; CHECK-LABEL: @shl(
   %s = shl i32 1, %x
   %c = icmp eq i32 %s, 0
   ret i1 %c
@@ -342,7 +342,7 @@ define i1 @shl(i32 %x) {
 }
 
 define i1 @lshr1(i32 %x) {
-; CHECK: @lshr1
+; CHECK-LABEL: @lshr1(
   %s = lshr i32 -1, %x
   %c = icmp eq i32 %s, 0
   ret i1 %c
@@ -350,15 +350,23 @@ define i1 @lshr1(i32 %x) {
 }
 
 define i1 @lshr2(i32 %x) {
-; CHECK: @lshr2
+; CHECK-LABEL: @lshr2(
   %s = lshr i32 %x, 30
   %c = icmp ugt i32 %s, 8
   ret i1 %c
 ; CHECK: ret i1 false
 }
 
+define i1 @lshr3(i32 %x) {
+; CHECK-LABEL: @lshr3(
+  %s = lshr i32 %x, %x
+  %c = icmp eq i32 %s, 0
+  ret i1 %c
+; CHECK: ret i1 true
+}
+
 define i1 @ashr1(i32 %x) {
-; CHECK: @ashr1
+; CHECK-LABEL: @ashr1(
   %s = ashr i32 -1, %x
   %c = icmp eq i32 %s, 0
   ret i1 %c
@@ -366,15 +374,23 @@ define i1 @ashr1(i32 %x) {
 }
 
 define i1 @ashr2(i32 %x) {
-; CHECK: @ashr2
+; CHECK-LABEL: @ashr2(
   %s = ashr i32 %x, 30
   %c = icmp slt i32 %s, -5
   ret i1 %c
 ; CHECK: ret i1 false
 }
 
+define i1 @ashr3(i32 %x) {
+; CHECK-LABEL: @ashr3(
+  %s = ashr i32 %x, %x
+  %c = icmp eq i32 %s, 0
+  ret i1 %c
+; CHECK: ret i1 true
+}
+
 define i1 @select1(i1 %cond) {
-; CHECK: @select1
+; CHECK-LABEL: @select1(
   %s = select i1 %cond, i32 1, i32 0
   %c = icmp eq i32 %s, 1
   ret i1 %c
@@ -382,7 +398,7 @@ define i1 @select1(i1 %cond) {
 }
 
 define i1 @select2(i1 %cond) {
-; CHECK: @select2
+; CHECK-LABEL: @select2(
   %x = zext i1 %cond to i32
   %s = select i1 %cond, i32 %x, i32 0
   %c = icmp ne i32 %s, 0
@@ -391,7 +407,7 @@ define i1 @select2(i1 %cond) {
 }
 
 define i1 @select3(i1 %cond) {
-; CHECK: @select3
+; CHECK-LABEL: @select3(
   %x = zext i1 %cond to i32
   %s = select i1 %cond, i32 1, i32 %x
   %c = icmp ne i32 %s, 0
@@ -400,7 +416,7 @@ define i1 @select3(i1 %cond) {
 }
 
 define i1 @select4(i1 %cond) {
-; CHECK: @select4
+; CHECK-LABEL: @select4(
   %invert = xor i1 %cond, 1
   %s = select i1 %invert, i32 0, i32 1
   %c = icmp ne i32 %s, 0
@@ -409,7 +425,7 @@ define i1 @select4(i1 %cond) {
 }
 
 define i1 @select5(i32 %x) {
-; CHECK: @select5
+; CHECK-LABEL: @select5(
   %c = icmp eq i32 %x, 0
   %s = select i1 %c, i32 1, i32 %x
   %c2 = icmp eq i32 %s, 0
@@ -418,7 +434,7 @@ define i1 @select5(i32 %x) {
 }
 
 define i1 @select6(i32 %x) {
-; CHECK: @select6
+; CHECK-LABEL: @select6(
   %c = icmp sgt i32 %x, 0
   %s = select i1 %c, i32 %x, i32 4
   %c2 = icmp eq i32 %s, 0
@@ -427,7 +443,7 @@ define i1 @select6(i32 %x) {
 }
 
 define i1 @urem1(i32 %X, i32 %Y) {
-; CHECK: @urem1
+; CHECK-LABEL: @urem1(
   %A = urem i32 %X, %Y
   %B = icmp ult i32 %A, %Y
   ret i1 %B
@@ -435,7 +451,7 @@ define i1 @urem1(i32 %X, i32 %Y) {
 }
 
 define i1 @urem2(i32 %X, i32 %Y) {
-; CHECK: @urem2
+; CHECK-LABEL: @urem2(
   %A = urem i32 %X, %Y
   %B = icmp eq i32 %A, %Y
   ret i1 %B
@@ -443,7 +459,7 @@ define i1 @urem2(i32 %X, i32 %Y) {
 }
 
 define i1 @urem3(i32 %X) {
-; CHECK: @urem3
+; CHECK-LABEL: @urem3(
   %A = urem i32 %X, 10
   %B = icmp ult i32 %A, 15
   ret i1 %B
@@ -451,7 +467,7 @@ define i1 @urem3(i32 %X) {
 }
 
 define i1 @urem4(i32 %X) {
-; CHECK: @urem4
+; CHECK-LABEL: @urem4(
   %A = urem i32 %X, 15
   %B = icmp ult i32 %A, 10
   ret i1 %B
@@ -459,24 +475,32 @@ define i1 @urem4(i32 %X) {
 }
 
 define i1 @urem5(i16 %X, i32 %Y) {
-; CHECK: @urem5
+; CHECK-LABEL: @urem5(
   %A = zext i16 %X to i32
   %B = urem i32 %A, %Y
   %C = icmp slt i32 %B, %Y
   ret i1 %C
-; CHECK: ret i1 true
+; CHECK-NOT: ret i1 true
 }
 
 define i1 @urem6(i32 %X, i32 %Y) {
-; CHECK: @urem6
+; CHECK-LABEL: @urem6(
   %A = urem i32 %X, %Y
   %B = icmp ugt i32 %Y, %A
   ret i1 %B
 ; CHECK: ret i1 true
 }
 
+define i1 @urem7(i32 %X) {
+; CHECK-LABEL: @urem7(
+  %A = urem i32 1, %X
+  %B = icmp sgt i32 %A, %X
+  ret i1 %B
+; CHECK-NOT: ret i1 false
+}
+
 define i1 @srem1(i32 %X) {
-; CHECK: @srem1
+; CHECK-LABEL: @srem1(
   %A = srem i32 %X, -5
   %B = icmp sgt i32 %A, 5
   ret i1 %B
@@ -484,7 +508,7 @@ define i1 @srem1(i32 %X) {
 }
 
 ; PR9343 #15
-; CHECK: @srem2
+; CHECK-LABEL: @srem2(
 ; CHECK: ret i1 false
 define i1 @srem2(i16 %X, i32 %Y) {
   %A = zext i16 %X to i32
@@ -494,7 +518,7 @@ define i1 @srem2(i16 %X, i32 %Y) {
   ret i1 %D
 }
 
-; CHECK: @srem3
+; CHECK-LABEL: @srem3(
 ; CHECK-NEXT: ret i1 false
 define i1 @srem3(i16 %X, i32 %Y) {
   %A = zext i16 %X to i32
@@ -506,7 +530,7 @@ define i1 @srem3(i16 %X, i32 %Y) {
 }
 
 define i1 @udiv1(i32 %X) {
-; CHECK: @udiv1
+; CHECK-LABEL: @udiv1(
   %A = udiv i32 %X, 1000000
   %B = icmp ult i32 %A, 5000
   ret i1 %B
@@ -514,7 +538,7 @@ define i1 @udiv1(i32 %X) {
 }
 
 define i1 @udiv2(i32 %X, i32 %Y, i32 %Z) {
-; CHECK: @udiv2
+; CHECK-LABEL: @udiv2(
   %A = udiv exact i32 10, %Z
   %B = udiv exact i32 20, %Z
   %C = icmp ult i32 %A, %B
@@ -523,7 +547,7 @@ define i1 @udiv2(i32 %X, i32 %Y, i32 %Z) {
 }
 
 define i1 @udiv3(i32 %X, i32 %Y) {
-; CHECK: @udiv3
+; CHECK-LABEL: @udiv3(
   %A = udiv i32 %X, %Y
   %C = icmp ugt i32 %A, %X
   ret i1 %C
@@ -531,7 +555,7 @@ define i1 @udiv3(i32 %X, i32 %Y) {
 }
 
 define i1 @udiv4(i32 %X, i32 %Y) {
-; CHECK: @udiv4
+; CHECK-LABEL: @udiv4(
   %A = udiv i32 %X, %Y
   %C = icmp ule i32 %A, %X
   ret i1 %C
@@ -539,7 +563,7 @@ define i1 @udiv4(i32 %X, i32 %Y) {
 }
 
 define i1 @udiv5(i32 %X) {
-; CHECK: @udiv5
+; CHECK-LABEL: @udiv5(
   %A = udiv i32 123, %X
   %C = icmp ugt i32 %A, 124
   ret i1 %C
@@ -548,7 +572,7 @@ define i1 @udiv5(i32 %X) {
 
 ; PR11340
 define i1 @udiv6(i32 %X) nounwind {
-; CHECK: @udiv6
+; CHECK-LABEL: @udiv6(
   %A = udiv i32 1, %X
   %C = icmp eq i32 %A, 0
   ret i1 %C
@@ -557,7 +581,7 @@ define i1 @udiv6(i32 %X) nounwind {
 
 
 define i1 @sdiv1(i32 %X) {
-; CHECK: @sdiv1
+; CHECK-LABEL: @sdiv1(
   %A = sdiv i32 %X, 1000000
   %B = icmp slt i32 %A, 3000
   ret i1 %B
@@ -565,7 +589,7 @@ define i1 @sdiv1(i32 %X) {
 }
 
 define i1 @or1(i32 %X) {
-; CHECK: @or1
+; CHECK-LABEL: @or1(
   %A = or i32 %X, 62
   %B = icmp ult i32 %A, 50
   ret i1 %B
@@ -573,7 +597,7 @@ define i1 @or1(i32 %X) {
 }
 
 define i1 @and1(i32 %X) {
-; CHECK: @and1
+; CHECK-LABEL: @and1(
   %A = and i32 %X, 62
   %B = icmp ugt i32 %A, 70
   ret i1 %B
@@ -581,7 +605,7 @@ define i1 @and1(i32 %X) {
 }
 
 define i1 @mul1(i32 %X) {
-; CHECK: @mul1
+; CHECK-LABEL: @mul1(
 ; Square of a non-zero number is non-zero if there is no overflow.
   %Y = or i32 %X, 1
   %M = mul nuw i32 %Y, %Y
@@ -591,7 +615,7 @@ define i1 @mul1(i32 %X) {
 }
 
 define i1 @mul2(i32 %X) {
-; CHECK: @mul2
+; CHECK-LABEL: @mul2(
 ; Square of a non-zero number is positive if there is no signed overflow.
   %Y = or i32 %X, 1
   %M = mul nsw i32 %Y, %Y
@@ -601,7 +625,7 @@ define i1 @mul2(i32 %X) {
 }
 
 define i1 @mul3(i32 %X, i32 %Y) {
-; CHECK: @mul3
+; CHECK-LABEL: @mul3(
 ; Product of non-negative numbers is non-negative if there is no signed overflow.
   %XX = mul nsw i32 %X, %X
   %YY = mul nsw i32 %Y, %Y
@@ -612,7 +636,7 @@ define i1 @mul3(i32 %X, i32 %Y) {
 }
 
 define <2 x i1> @vectorselect1(<2 x i1> %cond) {
-; CHECK: @vectorselect1
+; CHECK-LABEL: @vectorselect1(
   %invert = xor <2 x i1> %cond, <i1 1, i1 1>
   %s = select <2 x i1> %invert, <2 x i32> <i32 0, i32 0>, <2 x i32> <i32 1, i32 1>
   %c = icmp ne <2 x i32> %s, <i32 0, i32 0>
@@ -684,7 +708,7 @@ define zeroext i1 @external_compare(i32* noalias %x) {
 }
 
 define i1 @alloca_gep(i64 %a, i64 %b) {
-; CHECK: @alloca_gep
+; CHECK-LABEL: @alloca_gep(
 ; We can prove this GEP is non-null because it is inbounds and the pointer
 ; is non-null.
   %strs = alloca [1000 x [1001 x i8]], align 16
diff --git a/test/Transforms/InstSimplify/exact-nsw-nuw.ll b/test/Transforms/InstSimplify/exact-nsw-nuw.ll
index f3a804e..a0e326b 100644
--- a/test/Transforms/InstSimplify/exact-nsw-nuw.ll
+++ b/test/Transforms/InstSimplify/exact-nsw-nuw.ll
@@ -2,7 +2,7 @@
 
 ; PR8862
 
-; CHECK: @shift1
+; CHECK-LABEL: @shift1(
 ; CHECK: ret i32 %A
 define i32 @shift1(i32 %A, i32 %B) {
   %C = lshr exact i32 %A, %B
@@ -10,7 +10,7 @@ define i32 @shift1(i32 %A, i32 %B) {
   ret i32 %D
 }
 
-; CHECK: @shift2
+; CHECK-LABEL: @shift2(
 ; CHECK: lshr
 ; CHECK: ret i32 %D
 define i32 @shift2(i32 %A, i32 %B) {
@@ -19,7 +19,7 @@ define i32 @shift2(i32 %A, i32 %B) {
   ret i32 %D
 }
 
-; CHECK: @shift3
+; CHECK-LABEL: @shift3(
 ; CHECK: ret i32 %A
 define i32 @shift3(i32 %A, i32 %B) {
   %C = ashr exact i32 %A, %B
@@ -27,7 +27,7 @@ define i32 @shift3(i32 %A, i32 %B) {
   ret i32 %D
 }
 
-; CHECK: @shift4
+; CHECK-LABEL: @shift4(
 ; CHECK: ret i32 %A
 define i32 @shift4(i32 %A, i32 %B) {
   %C = shl nuw i32 %A, %B
@@ -35,7 +35,7 @@ define i32 @shift4(i32 %A, i32 %B) {
   ret i32 %D
 }
 
-; CHECK: @shift5
+; CHECK-LABEL: @shift5(
 ; CHECK: ret i32 %A
 define i32 @shift5(i32 %A, i32 %B) {
   %C = shl nsw i32 %A, %B
diff --git a/test/Transforms/InstSimplify/fast-math.ll b/test/Transforms/InstSimplify/fast-math.ll
index 154b967..71d1ed8 100644
--- a/test/Transforms/InstSimplify/fast-math.ll
+++ b/test/Transforms/InstSimplify/fast-math.ll
@@ -71,7 +71,7 @@ define float @fadd_fsub_0(float %a) {
 }
 
 ; fsub nnan ninf x, x ==> 0.0
-; CHECK: @fsub_x_x
+; CHECK-LABEL: @fsub_x_x(
 define float @fsub_x_x(float %a) {
 ; X - X ==> 0
   %zero1 = fsub nnan ninf float %a, %a
@@ -92,7 +92,7 @@ define float @fsub_x_x(float %a) {
 }
 
 ; fadd nsz X, 0 ==> X
-; CHECK: @nofold_fadd_x_0
+; CHECK-LABEL: @nofold_fadd_x_0(
 define float @nofold_fadd_x_0(float %a) {
 ; Dont fold
 ; CHECK: %no_zero1 = fadd
diff --git a/test/Transforms/InstSimplify/fdiv.ll b/test/Transforms/InstSimplify/fdiv.ll
index 9d85154..53ad25d 100644
--- a/test/Transforms/InstSimplify/fdiv.ll
+++ b/test/Transforms/InstSimplify/fdiv.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 define double @fdiv_of_undef(double %X) {
-; CHECK: @fdiv_of_undef
+; CHECK-LABEL: @fdiv_of_undef(
 ; undef / X -> undef
   %r = fdiv double undef, %X
   ret double %r
@@ -9,7 +9,7 @@ define double @fdiv_of_undef(double %X) {
 }
 
 define double @fdiv_by_undef(double %X) {
-; CHECK: @fdiv_by_undef
+; CHECK-LABEL: @fdiv_by_undef(
 ; X / undef -> undef
   %r = fdiv double %X, undef
   ret double %r
diff --git a/test/Transforms/InstSimplify/floating-point-arithmetic.ll b/test/Transforms/InstSimplify/floating-point-arithmetic.ll
index 91ce263..8177440 100644
--- a/test/Transforms/InstSimplify/floating-point-arithmetic.ll
+++ b/test/Transforms/InstSimplify/floating-point-arithmetic.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 ; fsub 0, (fsub 0, X) ==> X
-; CHECK: @fsub_0_0_x
+; CHECK-LABEL: @fsub_0_0_x(
 define float @fsub_0_0_x(float %a) {
   %t1 = fsub float -0.0, %a
   %ret = fsub float -0.0, %t1
@@ -11,7 +11,7 @@ define float @fsub_0_0_x(float %a) {
 }
 
 ; fsub X, 0 ==> X
-; CHECK: @fsub_x_0
+; CHECK-LABEL: @fsub_x_0(
 define float @fsub_x_0(float %a) {
   %ret = fsub float %a, 0.0
 ; CHECK: ret float %a
@@ -19,7 +19,7 @@ define float @fsub_x_0(float %a) {
 }
 
 ; fadd X, -0 ==> X
-; CHECK: @fadd_x_n0
+; CHECK-LABEL: @fadd_x_n0(
 define float @fadd_x_n0(float %a) {
   %ret = fadd float %a, -0.0
 ; CHECK: ret float %a
@@ -27,7 +27,7 @@ define float @fadd_x_n0(float %a) {
 }
 
 ; fmul X, 1.0 ==> X
-; CHECK: @fmul_X_1
+; CHECK-LABEL: @fmul_X_1(
 define double @fmul_X_1(double %a) {
   %b = fmul double 1.000000e+00, %a                ; <double> [#uses=1]
   ; CHECK: ret double %a
diff --git a/test/Transforms/InstSimplify/maxmin.ll b/test/Transforms/InstSimplify/maxmin.ll
index e921214..3c643ed 100644
--- a/test/Transforms/InstSimplify/maxmin.ll
+++ b/test/Transforms/InstSimplify/maxmin.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 define i1 @max1(i32 %x, i32 %y) {
-; CHECK: @max1
+; CHECK-LABEL: @max1(
   %c = icmp sgt i32 %x, %y
   %m = select i1 %c, i32 %x, i32 %y
   %r = icmp slt i32 %m, %x
@@ -10,7 +10,7 @@ define i1 @max1(i32 %x, i32 %y) {
 }
 
 define i1 @max2(i32 %x, i32 %y) {
-; CHECK: @max2
+; CHECK-LABEL: @max2(
   %c = icmp sge i32 %x, %y
   %m = select i1 %c, i32 %x, i32 %y
   %r = icmp sge i32 %m, %x
@@ -19,7 +19,7 @@ define i1 @max2(i32 %x, i32 %y) {
 }
 
 define i1 @max3(i32 %x, i32 %y) {
-; CHECK: @max3
+; CHECK-LABEL: @max3(
   %c = icmp ugt i32 %x, %y
   %m = select i1 %c, i32 %x, i32 %y
   %r = icmp ult i32 %m, %x
@@ -28,7 +28,7 @@ define i1 @max3(i32 %x, i32 %y) {
 }
 
 define i1 @max4(i32 %x, i32 %y) {
-; CHECK: @max4
+; CHECK-LABEL: @max4(
   %c = icmp uge i32 %x, %y
   %m = select i1 %c, i32 %x, i32 %y
   %r = icmp uge i32 %m, %x
@@ -37,7 +37,7 @@ define i1 @max4(i32 %x, i32 %y) {
 }
 
 define i1 @max5(i32 %x, i32 %y) {
-; CHECK: @max5
+; CHECK-LABEL: @max5(
   %c = icmp sgt i32 %x, %y
   %m = select i1 %c, i32 %x, i32 %y
   %r = icmp sgt i32 %x, %m
@@ -46,7 +46,7 @@ define i1 @max5(i32 %x, i32 %y) {
 }
 
 define i1 @max6(i32 %x, i32 %y) {
-; CHECK: @max6
+; CHECK-LABEL: @max6(
   %c = icmp sge i32 %x, %y
   %m = select i1 %c, i32 %x, i32 %y
   %r = icmp sle i32 %x, %m
@@ -55,7 +55,7 @@ define i1 @max6(i32 %x, i32 %y) {
 }
 
 define i1 @max7(i32 %x, i32 %y) {
-; CHECK: @max7
+; CHECK-LABEL: @max7(
   %c = icmp ugt i32 %x, %y
   %m = select i1 %c, i32 %x, i32 %y
   %r = icmp ugt i32 %x, %m
@@ -64,7 +64,7 @@ define i1 @max7(i32 %x, i32 %y) {
 }
 
 define i1 @max8(i32 %x, i32 %y) {
-; CHECK: @max8
+; CHECK-LABEL: @max8(
   %c = icmp uge i32 %x, %y
   %m = select i1 %c, i32 %x, i32 %y
   %r = icmp ule i32 %x, %m
@@ -73,7 +73,7 @@ define i1 @max8(i32 %x, i32 %y) {
 }
 
 define i1 @min1(i32 %x, i32 %y) {
-; CHECK: @min1
+; CHECK-LABEL: @min1(
   %c = icmp sgt i32 %x, %y
   %m = select i1 %c, i32 %y, i32 %x
   %r = icmp sgt i32 %m, %x
@@ -82,7 +82,7 @@ define i1 @min1(i32 %x, i32 %y) {
 }
 
 define i1 @min2(i32 %x, i32 %y) {
-; CHECK: @min2
+; CHECK-LABEL: @min2(
   %c = icmp sge i32 %x, %y
   %m = select i1 %c, i32 %y, i32 %x
   %r = icmp sle i32 %m, %x
@@ -91,7 +91,7 @@ define i1 @min2(i32 %x, i32 %y) {
 }
 
 define i1 @min3(i32 %x, i32 %y) {
-; CHECK: @min3
+; CHECK-LABEL: @min3(
   %c = icmp ugt i32 %x, %y
   %m = select i1 %c, i32 %y, i32 %x
   %r = icmp ugt i32 %m, %x
@@ -100,7 +100,7 @@ define i1 @min3(i32 %x, i32 %y) {
 }
 
 define i1 @min4(i32 %x, i32 %y) {
-; CHECK: @min4
+; CHECK-LABEL: @min4(
   %c = icmp uge i32 %x, %y
   %m = select i1 %c, i32 %y, i32 %x
   %r = icmp ule i32 %m, %x
@@ -109,7 +109,7 @@ define i1 @min4(i32 %x, i32 %y) {
 }
 
 define i1 @min5(i32 %x, i32 %y) {
-; CHECK: @min5
+; CHECK-LABEL: @min5(
   %c = icmp sgt i32 %x, %y
   %m = select i1 %c, i32 %y, i32 %x
   %r = icmp slt i32 %x, %m
@@ -118,7 +118,7 @@ define i1 @min5(i32 %x, i32 %y) {
 }
 
 define i1 @min6(i32 %x, i32 %y) {
-; CHECK: @min6
+; CHECK-LABEL: @min6(
   %c = icmp sge i32 %x, %y
   %m = select i1 %c, i32 %y, i32 %x
   %r = icmp sge i32 %x, %m
@@ -127,7 +127,7 @@ define i1 @min6(i32 %x, i32 %y) {
 }
 
 define i1 @min7(i32 %x, i32 %y) {
-; CHECK: @min7
+; CHECK-LABEL: @min7(
   %c = icmp ugt i32 %x, %y
   %m = select i1 %c, i32 %y, i32 %x
   %r = icmp ult i32 %x, %m
@@ -136,7 +136,7 @@ define i1 @min7(i32 %x, i32 %y) {
 }
 
 define i1 @min8(i32 %x, i32 %y) {
-; CHECK: @min8
+; CHECK-LABEL: @min8(
   %c = icmp uge i32 %x, %y
   %m = select i1 %c, i32 %y, i32 %x
   %r = icmp uge i32 %x, %m
@@ -145,7 +145,7 @@ define i1 @min8(i32 %x, i32 %y) {
 }
 
 define i1 @maxmin1(i32 %x, i32 %y, i32 %z) {
-; CHECK: @maxmin1
+; CHECK-LABEL: @maxmin1(
   %c1 = icmp sge i32 %x, %y
   %max = select i1 %c1, i32 %x, i32 %y
   %c2 = icmp sge i32 %x, %z
@@ -156,7 +156,7 @@ define i1 @maxmin1(i32 %x, i32 %y, i32 %z) {
 }
 
 define i1 @maxmin2(i32 %x, i32 %y, i32 %z) {
-; CHECK: @maxmin2
+; CHECK-LABEL: @maxmin2(
   %c1 = icmp sge i32 %x, %y
   %max = select i1 %c1, i32 %x, i32 %y
   %c2 = icmp sge i32 %x, %z
@@ -167,7 +167,7 @@ define i1 @maxmin2(i32 %x, i32 %y, i32 %z) {
 }
 
 define i1 @maxmin3(i32 %x, i32 %y, i32 %z) {
-; CHECK: @maxmin3
+; CHECK-LABEL: @maxmin3(
   %c1 = icmp sge i32 %x, %y
   %max = select i1 %c1, i32 %x, i32 %y
   %c2 = icmp sge i32 %x, %z
@@ -178,7 +178,7 @@ define i1 @maxmin3(i32 %x, i32 %y, i32 %z) {
 }
 
 define i1 @maxmin4(i32 %x, i32 %y, i32 %z) {
-; CHECK: @maxmin4
+; CHECK-LABEL: @maxmin4(
   %c1 = icmp sge i32 %x, %y
   %max = select i1 %c1, i32 %x, i32 %y
   %c2 = icmp sge i32 %x, %z
@@ -189,7 +189,7 @@ define i1 @maxmin4(i32 %x, i32 %y, i32 %z) {
 }
 
 define i1 @maxmin5(i32 %x, i32 %y, i32 %z) {
-; CHECK: @maxmin5
+; CHECK-LABEL: @maxmin5(
   %c1 = icmp uge i32 %x, %y
   %max = select i1 %c1, i32 %x, i32 %y
   %c2 = icmp uge i32 %x, %z
@@ -200,7 +200,7 @@ define i1 @maxmin5(i32 %x, i32 %y, i32 %z) {
 }
 
 define i1 @maxmin6(i32 %x, i32 %y, i32 %z) {
-; CHECK: @maxmin6
+; CHECK-LABEL: @maxmin6(
   %c1 = icmp uge i32 %x, %y
   %max = select i1 %c1, i32 %x, i32 %y
   %c2 = icmp uge i32 %x, %z
@@ -211,7 +211,7 @@ define i1 @maxmin6(i32 %x, i32 %y, i32 %z) {
 }
 
 define i1 @maxmin7(i32 %x, i32 %y, i32 %z) {
-; CHECK: @maxmin7
+; CHECK-LABEL: @maxmin7(
   %c1 = icmp uge i32 %x, %y
   %max = select i1 %c1, i32 %x, i32 %y
   %c2 = icmp uge i32 %x, %z
@@ -222,7 +222,7 @@ define i1 @maxmin7(i32 %x, i32 %y, i32 %z) {
 }
 
 define i1 @maxmin8(i32 %x, i32 %y, i32 %z) {
-; CHECK: @maxmin8
+; CHECK-LABEL: @maxmin8(
   %c1 = icmp uge i32 %x, %y
   %max = select i1 %c1, i32 %x, i32 %y
   %c2 = icmp uge i32 %x, %z
@@ -233,7 +233,7 @@ define i1 @maxmin8(i32 %x, i32 %y, i32 %z) {
 }
 
 define i1 @eqcmp1(i32 %x, i32 %y) {
-; CHECK: @eqcmp1
+; CHECK-LABEL: @eqcmp1(
   %c = icmp sge i32 %x, %y
   %max = select i1 %c, i32 %x, i32 %y
   %r = icmp eq i32 %max, %x
@@ -242,7 +242,7 @@ define i1 @eqcmp1(i32 %x, i32 %y) {
 }
 
 define i1 @eqcmp2(i32 %x, i32 %y) {
-; CHECK: @eqcmp2
+; CHECK-LABEL: @eqcmp2(
   %c = icmp sge i32 %x, %y
   %max = select i1 %c, i32 %x, i32 %y
   %r = icmp eq i32 %x, %max
@@ -251,7 +251,7 @@ define i1 @eqcmp2(i32 %x, i32 %y) {
 }
 
 define i1 @eqcmp3(i32 %x, i32 %y) {
-; CHECK: @eqcmp3
+; CHECK-LABEL: @eqcmp3(
   %c = icmp uge i32 %x, %y
   %max = select i1 %c, i32 %x, i32 %y
   %r = icmp eq i32 %max, %x
@@ -260,7 +260,7 @@ define i1 @eqcmp3(i32 %x, i32 %y) {
 }
 
 define i1 @eqcmp4(i32 %x, i32 %y) {
-; CHECK: @eqcmp4
+; CHECK-LABEL: @eqcmp4(
   %c = icmp uge i32 %x, %y
   %max = select i1 %c, i32 %x, i32 %y
   %r = icmp eq i32 %x, %max
diff --git a/test/Transforms/InstSimplify/phi.ll b/test/Transforms/InstSimplify/phi.ll
index 05cd40d..5b7aaa9 100644
--- a/test/Transforms/InstSimplify/phi.ll
+++ b/test/Transforms/InstSimplify/phi.ll
@@ -2,7 +2,7 @@
 
 ; PR12189
 define i1 @test1(i32 %x) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
   br i1 true, label %a, label %b
 
 a:
diff --git a/test/Transforms/InstSimplify/ptr_diff.ll b/test/Transforms/InstSimplify/ptr_diff.ll
index 8b4aa79..6a3f652 100644
--- a/test/Transforms/InstSimplify/ptr_diff.ll
+++ b/test/Transforms/InstSimplify/ptr_diff.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-unknown-linux-gnu"
 
 define i64 @ptrdiff1(i8* %ptr) {
-; CHECK: @ptrdiff1
+; CHECK-LABEL: @ptrdiff1(
 ; CHECK-NEXT: ret i64 42
 
   %first = getelementptr inbounds i8* %ptr, i32 0
@@ -15,7 +15,7 @@ define i64 @ptrdiff1(i8* %ptr) {
 }
 
 define i64 @ptrdiff2(i8* %ptr) {
-; CHECK: @ptrdiff2
+; CHECK-LABEL: @ptrdiff2(
 ; CHECK-NEXT: ret i64 42
 
   %first1 = getelementptr inbounds i8* %ptr, i32 0
@@ -34,7 +34,7 @@ define i64 @ptrdiff2(i8* %ptr) {
 
 define i64 @ptrdiff3(i8* %ptr) {
 ; Don't bother with non-inbounds GEPs.
-; CHECK: @ptrdiff3
+; CHECK-LABEL: @ptrdiff3(
 ; CHECK: getelementptr
 ; CHECK: sub
 ; CHECK: ret
@@ -49,7 +49,7 @@ define i64 @ptrdiff3(i8* %ptr) {
 
 define <4 x i32> @ptrdiff4(<4 x i8*> %arg) nounwind {
 ; Handle simple cases of vectors of pointers.
-; CHECK: @ptrdiff4
+; CHECK-LABEL: @ptrdiff4(
 ; CHECK: ret <4 x i32> zeroinitializer
   %p1 = ptrtoint <4 x i8*> %arg to <4 x i32>
   %bc = bitcast <4 x i8*> %arg to <4 x i32*>
@@ -73,6 +73,6 @@ bb:
   %tmp6 = ptrtoint [2 x i32]* %tmp5 to i32
   %tmp7 = sub i32 %tmp3, %tmp6
   ret i32 %tmp7
-; CHECK: @ptrdiff5
+; CHECK-LABEL: @ptrdiff5(
 ; CHECK: ret i32 0
 }
diff --git a/test/Transforms/InstSimplify/reassociate.ll b/test/Transforms/InstSimplify/reassociate.ll
index e659e6f..d44f715 100644
--- a/test/Transforms/InstSimplify/reassociate.ll
+++ b/test/Transforms/InstSimplify/reassociate.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 define i32 @add1(i32 %x) {
-; CHECK: @add1
+; CHECK-LABEL: @add1(
 ; (X + -1) + 1 -> X
   %l = add i32 %x, -1
   %r = add i32 %l, 1
@@ -10,7 +10,7 @@ define i32 @add1(i32 %x) {
 }
 
 define i32 @and1(i32 %x, i32 %y) {
-; CHECK: @and1
+; CHECK-LABEL: @and1(
 ; (X & Y) & X -> X & Y
   %l = and i32 %x, %y
   %r = and i32 %l, %x
@@ -19,7 +19,7 @@ define i32 @and1(i32 %x, i32 %y) {
 }
 
 define i32 @and2(i32 %x, i32 %y) {
-; CHECK: @and2
+; CHECK-LABEL: @and2(
 ; X & (X & Y) -> X & Y
   %r = and i32 %x, %y
   %l = and i32 %x, %r
@@ -28,7 +28,7 @@ define i32 @and2(i32 %x, i32 %y) {
 }
 
 define i32 @or1(i32 %x, i32 %y) {
-; CHECK: @or1
+; CHECK-LABEL: @or1(
 ; (X | Y) | X -> X | Y
   %l = or i32 %x, %y
   %r = or i32 %l, %x
@@ -37,7 +37,7 @@ define i32 @or1(i32 %x, i32 %y) {
 }
 
 define i32 @or2(i32 %x, i32 %y) {
-; CHECK: @or2
+; CHECK-LABEL: @or2(
 ; X | (X | Y) -> X | Y
   %r = or i32 %x, %y
   %l = or i32 %x, %r
@@ -46,7 +46,7 @@ define i32 @or2(i32 %x, i32 %y) {
 }
 
 define i32 @xor1(i32 %x, i32 %y) {
-; CHECK: @xor1
+; CHECK-LABEL: @xor1(
 ; (X ^ Y) ^ X = Y
   %l = xor i32 %x, %y
   %r = xor i32 %l, %x
@@ -55,7 +55,7 @@ define i32 @xor1(i32 %x, i32 %y) {
 }
 
 define i32 @xor2(i32 %x, i32 %y) {
-; CHECK: @xor2
+; CHECK-LABEL: @xor2(
 ; X ^ (X ^ Y) = Y
   %r = xor i32 %x, %y
   %l = xor i32 %x, %r
@@ -64,7 +64,7 @@ define i32 @xor2(i32 %x, i32 %y) {
 }
 
 define i32 @sub1(i32 %x, i32 %y) {
-; CHECK: @sub1
+; CHECK-LABEL: @sub1(
   %d = sub i32 %x, %y
   %r = sub i32 %x, %d
   ret i32 %r
@@ -72,7 +72,7 @@ define i32 @sub1(i32 %x, i32 %y) {
 }
 
 define i32 @sub2(i32 %x) {
-; CHECK: @sub2
+; CHECK-LABEL: @sub2(
 ; X - (X + 1) -> -1
   %xp1 = add i32 %x, 1
   %r = sub i32 %x, %xp1
@@ -81,7 +81,7 @@ define i32 @sub2(i32 %x) {
 }
 
 define i32 @sub3(i32 %x, i32 %y) {
-; CHECK: @sub3
+; CHECK-LABEL: @sub3(
 ; ((X + 1) + Y) - (Y + 1) -> X
   %xp1 = add i32 %x, 1
   %lhs = add i32 %xp1, %y
@@ -92,7 +92,7 @@ define i32 @sub3(i32 %x, i32 %y) {
 }
 
 define i32 @sdiv1(i32 %x, i32 %y) {
-; CHECK: @sdiv1
+; CHECK-LABEL: @sdiv1(
 ; (no overflow X * Y) / Y -> X
   %mul = mul nsw i32 %x, %y
   %r = sdiv i32 %mul, %y
@@ -101,7 +101,7 @@ define i32 @sdiv1(i32 %x, i32 %y) {
 }
 
 define i32 @sdiv2(i32 %x, i32 %y) {
-; CHECK: @sdiv2
+; CHECK-LABEL: @sdiv2(
 ; (((X / Y) * Y) / Y) -> X / Y
   %div = sdiv i32 %x, %y
   %mul = mul i32 %div, %y
@@ -111,7 +111,7 @@ define i32 @sdiv2(i32 %x, i32 %y) {
 }
 
 define i32 @sdiv3(i32 %x, i32 %y) {
-; CHECK: @sdiv3
+; CHECK-LABEL: @sdiv3(
 ; (X rem Y) / Y -> 0
   %rem = srem i32 %x, %y
   %div = sdiv i32 %rem, %y
@@ -120,7 +120,7 @@ define i32 @sdiv3(i32 %x, i32 %y) {
 }
 
 define i32 @sdiv4(i32 %x, i32 %y) {
-; CHECK: @sdiv4
+; CHECK-LABEL: @sdiv4(
 ; (X / Y) * Y -> X if the division is exact
   %div = sdiv exact i32 %x, %y
   %mul = mul i32 %div, %y
@@ -129,7 +129,7 @@ define i32 @sdiv4(i32 %x, i32 %y) {
 }
 
 define i32 @sdiv5(i32 %x, i32 %y) {
-; CHECK: @sdiv5
+; CHECK-LABEL: @sdiv5(
 ; Y * (X / Y) -> X if the division is exact
   %div = sdiv exact i32 %x, %y
   %mul = mul i32 %y, %div
@@ -139,7 +139,7 @@ define i32 @sdiv5(i32 %x, i32 %y) {
 
 
 define i32 @udiv1(i32 %x, i32 %y) {
-; CHECK: @udiv1
+; CHECK-LABEL: @udiv1(
 ; (no overflow X * Y) / Y -> X
   %mul = mul nuw i32 %x, %y
   %r = udiv i32 %mul, %y
@@ -148,7 +148,7 @@ define i32 @udiv1(i32 %x, i32 %y) {
 }
 
 define i32 @udiv2(i32 %x, i32 %y) {
-; CHECK: @udiv2
+; CHECK-LABEL: @udiv2(
 ; (((X / Y) * Y) / Y) -> X / Y
   %div = udiv i32 %x, %y
   %mul = mul i32 %div, %y
@@ -158,7 +158,7 @@ define i32 @udiv2(i32 %x, i32 %y) {
 }
 
 define i32 @udiv3(i32 %x, i32 %y) {
-; CHECK: @udiv3
+; CHECK-LABEL: @udiv3(
 ; (X rem Y) / Y -> 0
   %rem = urem i32 %x, %y
   %div = udiv i32 %rem, %y
@@ -167,7 +167,7 @@ define i32 @udiv3(i32 %x, i32 %y) {
 }
 
 define i32 @udiv4(i32 %x, i32 %y) {
-; CHECK: @udiv4
+; CHECK-LABEL: @udiv4(
 ; (X / Y) * Y -> X if the division is exact
   %div = udiv exact i32 %x, %y
   %mul = mul i32 %div, %y
@@ -176,7 +176,7 @@ define i32 @udiv4(i32 %x, i32 %y) {
 }
 
 define i32 @udiv5(i32 %x, i32 %y) {
-; CHECK: @udiv5
+; CHECK-LABEL: @udiv5(
 ; Y * (X / Y) -> X if the division is exact
   %div = udiv exact i32 %x, %y
   %mul = mul i32 %y, %div
@@ -185,7 +185,7 @@ define i32 @udiv5(i32 %x, i32 %y) {
 }
 
 define i16 @trunc1(i32 %x) {
-; CHECK: @trunc1
+; CHECK-LABEL: @trunc1(
   %y = add i32 %x, 1
   %tx = trunc i32 %x to i16
   %ty = trunc i32 %y to i16
diff --git a/test/Transforms/InstSimplify/rem.ll b/test/Transforms/InstSimplify/rem.ll
index 4c8f87c..80fa8e7 100644
--- a/test/Transforms/InstSimplify/rem.ll
+++ b/test/Transforms/InstSimplify/rem.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 define i32 @select1(i32 %x, i1 %b) {
-; CHECK: @select1
+; CHECK-LABEL: @select1(
   %rhs = select i1 %b, i32 %x, i32 1
   %rem = srem i32 %x, %rhs
   ret i32 %rem
@@ -9,7 +9,7 @@ define i32 @select1(i32 %x, i1 %b) {
 }
 
 define i32 @select2(i32 %x, i1 %b) {
-; CHECK: @select2
+; CHECK-LABEL: @select2(
   %rhs = select i1 %b, i32 %x, i32 1
   %rem = urem i32 %x, %rhs
   ret i32 %rem
diff --git a/test/Transforms/Internalize/2008-05-09-AllButMain.ll b/test/Transforms/Internalize/2008-05-09-AllButMain.ll
index c07abb0..f75e80d 100644
--- a/test/Transforms/Internalize/2008-05-09-AllButMain.ll
+++ b/test/Transforms/Internalize/2008-05-09-AllButMain.ll
@@ -27,29 +27,29 @@
 ; MERGE: @j = global
 @j = global i32 0
 
-; NOARGS: define internal void @main
-; LIST: define internal void @main
-; EMPTYFILE: define internal void @main
-; LIST2: define internal void @main
-; MERGE: define internal void @main
+; NOARGS-LABEL: define internal void @main(
+; LIST-LABEL: define internal void @main(
+; EMPTYFILE-LABEL: define internal void @main(
+; LIST2-LABEL: define internal void @main(
+; MERGE-LABEL: define internal void @main(
 define void @main() {
         ret void
 }
 
-; NOARGS: define internal void @foo
-; LIST: define void @foo
-; EMPTYFILE: define internal void @foo
-; LIST2: define void @foo
-; MERGE: define void @foo
+; NOARGS-LABEL: define internal void @foo(
+; LIST-LABEL: define void @foo(
+; EMPTYFILE-LABEL: define internal void @foo(
+; LIST2-LABEL: define void @foo(
+; MERGE-LABEL: define void @foo(
 define void @foo() {
         ret void
 }
 
-; NOARGS: define internal void @bar
-; LIST: define internal void @bar
-; EMPTYFILE: define internal void @bar
-; LIST2: define void @bar
-; MERGE: define void @bar
+; NOARGS-LABEL: define internal void @bar(
+; LIST-LABEL: define internal void @bar(
+; EMPTYFILE-LABEL: define internal void @bar(
+; LIST2-LABEL: define void @bar(
+; MERGE-LABEL: define void @bar(
 define void @bar() {
         ret void
 }
diff --git a/test/Transforms/Internalize/available_externally.ll b/test/Transforms/Internalize/available_externally.ll
index a2cf23f..bb89603 100644
--- a/test/Transforms/Internalize/available_externally.ll
+++ b/test/Transforms/Internalize/available_externally.ll
@@ -1,16 +1,16 @@
 ; RUN: opt < %s -internalize -internalize-public-api-list foo -S | FileCheck %s
 
-; CHECK: define void @foo
+; CHECK-LABEL: define void @foo(
 define void @foo() {
   ret void
 }
 
-; CHECK: define internal void @zed
+; CHECK-LABEL: define internal void @zed(
 define void @zed() {
   ret void
 }
 
-; CHECK: define available_externally void @bar
+; CHECK-LABEL: define available_externally void @bar(
 define available_externally void @bar() {
   ret void
 }
diff --git a/test/Transforms/Internalize/used.ll b/test/Transforms/Internalize/used.ll
new file mode 100644
index 0000000..85b85ac
--- /dev/null
+++ b/test/Transforms/Internalize/used.ll
@@ -0,0 +1,20 @@
+; RUN: opt < %s -internalize -S | FileCheck %s
+
+@llvm.used = appending global [1 x void ()*] [void ()* @f], section "llvm.metadata"
+
+@llvm.compiler.used = appending global [1 x void ()*] [void ()* @g], section "llvm.metadata"
+
+; CHECK: define void @f()
+define void @f() {
+  ret void
+}
+
+; CHECK: define internal void @g()
+define void @g() {
+  ret void
+}
+
+; CHECK: define internal void @h()
+define void @h() {
+  ret void
+}
diff --git a/test/Transforms/JumpThreading/basic.ll b/test/Transforms/JumpThreading/basic.ll
index fe3dc77..32cc4de 100644
--- a/test/Transforms/JumpThreading/basic.ll
+++ b/test/Transforms/JumpThreading/basic.ll
@@ -5,7 +5,7 @@ declare i32 @f2()
 declare void @f3()
 
 define i32 @test1(i1 %cond) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 
 	br i1 %cond, label %T1, label %F1
 
@@ -37,7 +37,7 @@ F2:
 
 ;; cond is known false on Entry -> F1 edge!
 define i32 @test2(i1 %cond) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 Entry:
 	br i1 %cond, label %T1, label %F1
 
@@ -62,7 +62,7 @@ F2:
 
 ; Undef handling.
 define i32 @test3(i1 %cond) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: T1:
 ; CHECK-NEXT: ret i32 42
 	br i1 undef, label %T1, label %F1
@@ -75,7 +75,7 @@ F1:
 }
 
 define i32 @test4(i1 %cond, i1 %cond2) {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 
 	br i1 %cond, label %T1, label %F1
 
@@ -108,7 +108,7 @@ F2:
 
 ;; This tests that the branch in 'merge' can be cloned up into T1.
 define i32 @test5(i1 %cond, i1 %cond2) {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 
 	br i1 %cond, label %T1, label %F1
 
@@ -144,7 +144,7 @@ F2:
 
 
 define i32 @test6(i32 %A) {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 	%tmp455 = icmp eq i32 %A, 42
 	br i1 %tmp455, label %BB1, label %BB2
 
@@ -180,7 +180,7 @@ BB4:
 ;; rdar://7367025
 define i32 @test7(i1 %cond, i1 %cond2) {
 Entry:
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 	%v1 = call i32 @f1()
 	br i1 %cond, label %Merge, label %F1
 
@@ -213,7 +213,7 @@ F2:
 declare i1 @test8a()
 
 define i32 @test8b(i1 %cond, i1 %cond2) {
-; CHECK: @test8b
+; CHECK-LABEL: @test8b(
 T0:
         %A = call i1 @test8a()
 	br i1 %A, label %T1, label %F1
@@ -255,7 +255,7 @@ Y:
 ;;; Verify that we can handle constraint propagation through "xor x, 1".
 define i32 @test9(i1 %cond, i1 %cond2) {
 Entry:
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 	%v1 = call i32 @f1()
 	br i1 %cond, label %Merge, label %F1
 
@@ -298,7 +298,7 @@ declare void @test10f3()
 
 ;; Non-local condition threading.
 define i32 @test10g(i1 %cond) {
-; CHECK: @test10g
+; CHECK-LABEL: @test10g(
 ; CHECK-NEXT:   br i1 %cond, label %T2, label %F2
         br i1 %cond, label %T1, label %F1
 
@@ -329,7 +329,7 @@ F2:
 
 ; Impossible conditional constraints should get threaded.  BB3 is dead here.
 define i32 @test11(i32 %A) {
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK-NEXT: icmp
 ; CHECK-NEXT: br i1 %tmp455, label %BB4, label %BB2
 	%tmp455 = icmp eq i32 %A, 42
@@ -357,7 +357,7 @@ BB4:
 
 ;; Correlated value through boolean expression.  GCC PR18046.
 define void @test12(i32 %A) {
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 entry:
   %cond = icmp eq i32 %A, 0
   br i1 %cond, label %bb, label %bb1
@@ -393,7 +393,7 @@ return:
 ;; rdar://7391699
 define i32 @test13(i1 %cond, i1 %cond2) {
 Entry:
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 	%v1 = call i32 @f1()
 	br i1 %cond, label %Merge, label %F1
 
@@ -421,7 +421,7 @@ F2:
 ; CHECK-NEXT:   br i1 %N, label %T2, label %F2
 }
 
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 define i32 @test14(i32 %in) {
 entry:
 	%A = icmp eq i32 %in, 0
@@ -453,7 +453,7 @@ right_ret:
 }
 
 ; PR5652
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 define i32 @test15(i32 %len) {
 entry:
 ; CHECK: icmp ult i32 %len, 13
diff --git a/test/Transforms/JumpThreading/indirectbr.ll b/test/Transforms/JumpThreading/indirectbr.ll
index 141277f..b87fb6c 100644
--- a/test/Transforms/JumpThreading/indirectbr.ll
+++ b/test/Transforms/JumpThreading/indirectbr.ll
@@ -67,7 +67,7 @@ L2:                                               ; preds = %indirectgoto
 ; Don't merge address-taken blocks.
 @.str = private unnamed_addr constant [4 x i8] c"%p\0A\00"
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: __here:
 ; CHECK: blockaddress(@test3, %__here)
 ; CHECK: __here1:
diff --git a/test/Transforms/JumpThreading/select.ll b/test/Transforms/JumpThreading/select.ll
index 9676efe..201e604 100644
--- a/test/Transforms/JumpThreading/select.ll
+++ b/test/Transforms/JumpThreading/select.ll
@@ -10,7 +10,7 @@ declare void @quux()
 ; Mostly theoretical since instruction combining simplifies all selects of
 ; booleans where at least one operand is true/false/undef.
 
-; CHECK: @test_br
+; CHECK-LABEL: @test_br(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: br i1 %cond, label %L1,
 define void @test_br(i1 %cond, i1 %value) nounwind {
@@ -34,7 +34,7 @@ L3:
 
 ; Jump threading of switch with select as condition.
 
-; CHECK: @test_switch
+; CHECK-LABEL: @test_switch(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: br i1 %cond, label %L1,
 define void @test_switch(i1 %cond, i8 %value) nounwind {
@@ -69,7 +69,7 @@ L4:
 
 ; Jump threading of indirectbr with select as address.
 
-; CHECK: @test_indirectbr
+; CHECK-LABEL: @test_indirectbr(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: br i1 %cond, label %L1, label %L3
 define void @test_indirectbr(i1 %cond, i8* %address) nounwind {
@@ -93,7 +93,7 @@ L3:
 
 ; A more complicated case: the condition is a select based on a comparison.
 
-; CHECK: @test_switch_cmp
+; CHECK-LABEL: @test_switch_cmp(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: br i1 %cond, label %L0, label %[[THREADED:[A-Za-z.0-9]+]]
 ; CHECK: [[THREADED]]:
@@ -157,3 +157,66 @@ L3:
 L4:
   ret void
 }
+
+define void @unfold1(double %x, double %y) nounwind {
+entry:
+  %sub = fsub double %x, %y
+  %cmp = fcmp ogt double %sub, 1.000000e+01
+  br i1 %cmp, label %cond.end4, label %cond.false
+
+cond.false:                                       ; preds = %entry
+  %add = fadd double %x, %y
+  %cmp1 = fcmp ogt double %add, 1.000000e+01
+  %add. = select i1 %cmp1, double %add, double 0.000000e+00
+  br label %cond.end4
+
+cond.end4:                                        ; preds = %entry, %cond.false
+  %cond5 = phi double [ %add., %cond.false ], [ %sub, %entry ]
+  %cmp6 = fcmp oeq double %cond5, 0.000000e+00
+  br i1 %cmp6, label %if.then, label %if.end
+
+if.then:                                          ; preds = %cond.end4
+  call void @foo()
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %cond.end4
+  ret void
+
+; CHECK-LABEL: @unfold1
+; CHECK: br i1 %cmp, label %cond.end4, label %cond.false
+; CHECK: br i1 %cmp1, label %cond.end4, label %if.then
+; CHECK: br i1 %cmp6, label %if.then, label %if.end
+; CHECK: br label %if.end
+}
+
+
+define void @unfold2(i32 %x, i32 %y) nounwind {
+entry:
+  %sub = sub nsw i32 %x, %y
+  %cmp = icmp sgt i32 %sub, 10
+  br i1 %cmp, label %cond.end4, label %cond.false
+
+cond.false:                                       ; preds = %entry
+  %add = add nsw i32 %x, %y
+  %cmp1 = icmp sgt i32 %add, 10
+  %add. = select i1 %cmp1, i32 0, i32 %add
+  br label %cond.end4
+
+cond.end4:                                        ; preds = %entry, %cond.false
+  %cond5 = phi i32 [ %add., %cond.false ], [ %sub, %entry ]
+  %cmp6 = icmp eq i32 %cond5, 0
+  br i1 %cmp6, label %if.then, label %if.end
+
+if.then:                                          ; preds = %cond.end4
+  call void @foo()
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %cond.end4
+  ret void
+
+; CHECK-LABEL: @unfold2
+; CHECK: br i1 %cmp, label %if.end, label %cond.false
+; CHECK: br i1 %cmp1, label %if.then, label %cond.end4
+; CHECK: br i1 %cmp6, label %if.then, label %if.end
+; CHECK: br label %if.end
+}
diff --git a/test/Transforms/JumpThreading/thread-loads.ll b/test/Transforms/JumpThreading/thread-loads.ll
index 78d36e7..e651f9a 100644
--- a/test/Transforms/JumpThreading/thread-loads.ll
+++ b/test/Transforms/JumpThreading/thread-loads.ll
@@ -6,7 +6,7 @@ target triple = "i386-apple-darwin7"
 ; Test that we can thread through the block with the partially redundant load (%2).
 ; rdar://6402033
 define i32 @test1(i32* %P) nounwind {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 entry:
 	%0 = tail call i32 (...)* @f1() nounwind		; <i32> [#uses=1]
 	%1 = icmp eq i32 %0, 0		; <i1> [#uses=1]
@@ -45,7 +45,7 @@ declare i32 @f2(...)
 ; rdar://11039258
 
 define i32 @test2(i32* %P) nounwind {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 entry:
 	%0 = tail call i32 (...)* @f1() nounwind		; <i32> [#uses=1]
 	%1 = icmp eq i32 %0, 0		; <i1> [#uses=1]
diff --git a/test/Transforms/LICM/atomics.ll b/test/Transforms/LICM/atomics.ll
index 3902152..acf605d 100644
--- a/test/Transforms/LICM/atomics.ll
+++ b/test/Transforms/LICM/atomics.ll
@@ -14,7 +14,7 @@ loop:
 
 end:
   ret i32 %val
-; CHECK: define i32 @test1(
+; CHECK-LABEL: define i32 @test1(
 ; CHECK: load atomic
 ; CHECK-NEXT: br label %loop
 }
@@ -33,7 +33,7 @@ loop:
 
 end:
   ret i32 %val
-; CHECK: define i32 @test2(
+; CHECK-LABEL: define i32 @test2(
 ; CHECK: load atomic
 ; CHECK-NEXT: %exitcond = icmp ne
 ; CHECK-NEXT: br i1 %exitcond, label %end, label %loop
@@ -54,7 +54,7 @@ loop:
 
 end:
   ret i32 %vala
-; CHECK: define i32 @test3(
+; CHECK-LABEL: define i32 @test3(
 ; CHECK: load atomic i32* %x unordered
 ; CHECK-NEXT: br label %loop
 }
@@ -73,7 +73,7 @@ loop:
 
 end:
   ret i32 %vala
-; CHECK: define i32 @test4(
+; CHECK-LABEL: define i32 @test4(
 ; CHECK: load atomic i32* %y monotonic
 ; CHECK-NEXT: store atomic
 }
diff --git a/test/Transforms/LICM/debug-value.ll b/test/Transforms/LICM/debug-value.ll
index 889d4e2..3c70064 100644
--- a/test/Transforms/LICM/debug-value.ll
+++ b/test/Transforms/LICM/debug-value.ll
@@ -35,28 +35,29 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.sp = !{!0, !6, !9, !10}
 
-!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"idamax", metadata !"idamax", metadata !"", metadata !1, i32 112, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, null} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 589865, metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/Benchmarks/CoyoteBench/lpbench.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/Benchmarks/CoyoteBench/lpbench.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 127169)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 589870, metadata !25, metadata !1, metadata !"idamax", metadata !"idamax", metadata !"", i32 112, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 589865, metadata !25} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 589841, metadata !25, i32 12, metadata !"clang version 2.9 (trunk 127169)", i1 true, metadata !"", i32 0, metadata !8, metadata !8, metadata !8, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 589845, metadata !25, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!6 = metadata !{i32 589870, i32 0, metadata !1, metadata !"dscal", metadata !"dscal", metadata !"", metadata !1, i32 206, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, null} ; [ DW_TAG_subprogram ]
-!7 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!5 = metadata !{i32 589860, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 589870, metadata !25, metadata !1, metadata !"dscal", metadata !"dscal", metadata !"", i32 206, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!7 = metadata !{i32 589845, metadata !25, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !8 = metadata !{null}
-!9 = metadata !{i32 589870, i32 0, metadata !1, metadata !"daxpy", metadata !"daxpy", metadata !"", metadata !1, i32 230, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, null} ; [ DW_TAG_subprogram ]
-!10 = metadata !{i32 589870, i32 0, metadata !1, metadata !"dgefa", metadata !"dgefa", metadata !"", metadata !1, i32 267, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, null} ; [ DW_TAG_subprogram ]
+!9 = metadata !{i32 589870, metadata !25, metadata !1, metadata !"daxpy", metadata !"daxpy", metadata !"", i32 230, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!10 = metadata !{i32 589870, metadata !25, metadata !1, metadata !"dgefa", metadata !"dgefa", metadata !"", i32 267, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
 !11 = metadata !{i32 281, i32 9, metadata !12, null}
-!12 = metadata !{i32 589835, metadata !13, i32 272, i32 5, metadata !1, i32 32} ; [ DW_TAG_lexical_block ]
-!13 = metadata !{i32 589835, metadata !14, i32 271, i32 5, metadata !1, i32 31} ; [ DW_TAG_lexical_block ]
-!14 = metadata !{i32 589835, metadata !10, i32 267, i32 1, metadata !1, i32 30} ; [ DW_TAG_lexical_block ]
+!12 = metadata !{i32 589835, metadata !25, metadata !13, i32 272, i32 5, i32 32} ; [ DW_TAG_lexical_block ]
+!13 = metadata !{i32 589835, metadata !25, metadata !14, i32 271, i32 5, i32 31} ; [ DW_TAG_lexical_block ]
+!14 = metadata !{i32 589835, metadata !25, metadata !10, i32 267, i32 1, i32 30} ; [ DW_TAG_lexical_block ]
 !15 = metadata !{i32 271, i32 5, metadata !14, null}
 !16 = metadata !{i32 284, i32 10, metadata !17, null}
-!17 = metadata !{i32 589835, metadata !12, i32 282, i32 9, metadata !1, i32 33} ; [ DW_TAG_lexical_block ]
+!17 = metadata !{i32 589835, metadata !25, metadata !12, i32 282, i32 9, i32 33} ; [ DW_TAG_lexical_block ]
 !18 = metadata !{double undef}
 !19 = metadata !{i32 590080, metadata !14, metadata !"temp", metadata !1, i32 268, metadata !20, i32 0} ; [ DW_TAG_auto_variable ]
-!20 = metadata !{i32 589860, metadata !2, metadata !"double", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
+!20 = metadata !{i32 589860, null, metadata !2, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
 !21 = metadata !{i32 286, i32 14, metadata !22, null}
-!22 = metadata !{i32 589835, metadata !17, i32 285, i32 13, metadata !1, i32 34} ; [ DW_TAG_lexical_block ]
+!22 = metadata !{i32 589835, metadata !25, metadata !17, i32 285, i32 13, i32 34} ; [ DW_TAG_lexical_block ]
 !23 = metadata !{i32 296, i32 13, metadata !17, null}
 !24 = metadata !{i32 313, i32 1, metadata !14, null}
+!25 = metadata !{metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/Benchmarks/CoyoteBench/lpbench.c", metadata !"/private/tmp"}
diff --git a/test/Transforms/LICM/hoisting.ll b/test/Transforms/LICM/hoisting.ll
index 1ca377e..b4d297a 100644
--- a/test/Transforms/LICM/hoisting.ll
+++ b/test/Transforms/LICM/hoisting.ll
@@ -7,7 +7,7 @@ declare void @foo()
 ; This testcase tests for a problem where LICM hoists 
 ; potentially trapping instructions when they are not guaranteed to execute.
 define i32 @test1(i1 %c) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 	%A = load i32* @X		; <i32> [#uses=2]
 	br label %Loop
 Loop:		; preds = %LoopTail, %0
@@ -34,7 +34,7 @@ declare void @foo2(i32) nounwind
 
 ;; It is ok and desirable to hoist this potentially trapping instruction.
 define i32 @test2(i1 %c) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: load i32* @X
 ; CHECK-NEXT: %B = sdiv i32 4, %A
 	%A = load i32* @X		; <i32> [#uses=2]
@@ -52,7 +52,7 @@ Out:		; preds = %Loop
 
 ; This loop invariant instruction should be constant folded, not hoisted.
 define i32 @test3(i1 %c) {
-; CHECK: define i32 @test3
+; CHECK-LABEL: define i32 @test3(
 ; CHECK: call void @foo2(i32 6)
 	%A = load i32* @X		; <i32> [#uses=2]
 	br label %Loop
@@ -65,7 +65,7 @@ Out:		; preds = %Loop
 	ret i32 %C
 }
 
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: call
 ; CHECK: sdiv
 ; CHECK: ret
@@ -91,7 +91,7 @@ for.end:                                          ; preds = %for.body
 declare void @foo_may_call_exit(i32)
 
 ; PR14854
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: extractvalue
 ; CHECK: br label %tailrecurse
 ; CHECK: tailrecurse:
diff --git a/test/Transforms/LICM/scalar_promote.ll b/test/Transforms/LICM/scalar_promote.ll
index e7eab92..b3e45c5 100644
--- a/test/Transforms/LICM/scalar_promote.ll
+++ b/test/Transforms/LICM/scalar_promote.ll
@@ -6,7 +6,7 @@ target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:1
 define void @test1(i32 %i) {
 Entry:
   br label %Loop
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: Entry:
 ; CHECK-NEXT:   load i32* @X
 ; CHECK-NEXT:   br label %Loop
@@ -32,7 +32,7 @@ Out:
 define void @test2(i32 %i) {
 Entry:
   br label %Loop
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: Entry:
 ; CHECK-NEXT:    %.promoted = load i32* getelementptr inbounds (i32* @X, i64 1)
 ; CHECK-NEXT:    br label %Loop
@@ -55,7 +55,7 @@ Exit:   ; preds = %Loop
 
 
 define void @test3(i32 %i) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
   br label %Loop
 Loop:
         ; Should not promote this to a register
@@ -73,7 +73,7 @@ Out:    ; preds = %Loop
 
 ; PR8041
 define void @test4(i8* %x, i8 %n) {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
   %handle1 = alloca i8*
   %handle2 = alloca i8*
   store i8* %x, i8** %handle1
@@ -121,7 +121,7 @@ exit:
 define void @test5(i32 %i, i32** noalias %P2) {
 Entry:
   br label %Loop
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: Entry:
 ; CHECK-NEXT:   load i32* @X
 ; CHECK-NEXT:   br label %Loop
diff --git a/test/Transforms/LICM/sinking.ll b/test/Transforms/LICM/sinking.ll
index 68e4b64..b503f96 100644
--- a/test/Transforms/LICM/sinking.ll
+++ b/test/Transforms/LICM/sinking.ll
@@ -14,7 +14,7 @@ Loop:		; preds = %Loop, %0
 
 Out:		; preds = %Loop
 	ret i32 %A
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: Out:
 ; CHECK-NEXT: call i32 @strlen
 ; CHECK-NEXT: ret i32 %A
@@ -33,7 +33,7 @@ Loop:		; preds = %Loop, %0
 
 Out:		; preds = %Loop
 	ret double %A
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: Out:
 ; CHECK-NEXT: call double @sin
 ; CHECK-NEXT: ret double %A
@@ -51,7 +51,7 @@ Exit:
 	%Y = phi i32 [ 0, %Entry ], [ %X, %Loop ]
 	ret void
         
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK:     Exit.loopexit:
 ; CHECK-NEXT:  %X = add i32 0, 1
 ; CHECK-NEXT:  br label %Exit
@@ -74,7 +74,7 @@ Loop:		; preds = %Loop, %Entry
 	br i1 %tmp.1, label %Loop, label %Out
 Out:		; preds = %Loop
 	ret i32 %tmp.7
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK:     Out:
 ; CHECK-NEXT:  mul i32 %N, %N_addr.0.pn
 ; CHECK-NEXT:  sub i32 %tmp.6, %N
@@ -98,7 +98,7 @@ Loop:		; preds = %Loop, %Entry
 	br i1 %tmp.1, label %Loop, label %Out
 Out:		; preds = %Loop
 	ret i32 %tmp.6
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK:     Out:
 ; CHECK-NEXT:  %tmp.6 = load i32* @X
 ; CHECK-NEXT:  ret i32 %tmp.6
@@ -122,7 +122,7 @@ Loop:
 	br i1 false, label %Loop, label %Out
 Out:		; preds = %Loop
 	ret i32 %sunk2
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK:     Out:
 ; CHECK-NEXT:  %dead = getelementptr %Ty* @X2, i64 0, i32 0
 ; CHECK-NEXT:  %sunk2 = load i32* %dead
@@ -150,7 +150,7 @@ Out1:		; preds = %Loop
 	ret i32 %tmp.7
 Out2:		; preds = %ContLoop
 	ret i32 %tmp.7
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK:     Out1:
 ; CHECK-NEXT:  mul i32 %N, %N_addr.0.pn
 ; CHECK-NEXT:  sub i32 %tmp.6, %N
@@ -179,7 +179,7 @@ exit1:		; preds = %Loop
 	ret i32 0
 exit2:		; preds = %Cont
 	ret i32 %V
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK:     exit1:
 ; CHECK-NEXT:  ret i32 0
 ; CHECK:     exit2:
@@ -206,7 +206,7 @@ loopentry.3.i.preheader:		; preds = %loopentry.3.i.preheader.loopexit, %loopentr
 return.i:		; preds = %no_exit.1.i
 	ret void
 
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK: loopentry.3.i.preheader.loopexit:
 ; CHECK-NEXT:  %inc.1.i = add i32 0, 1
 ; CHECK-NEXT:  br label %loopentry.3.i.preheader
@@ -227,7 +227,7 @@ Loop:		; preds = %Loop, %Entry
 Out:		; preds = %Loop
 	ret i32 %tmp.6
         
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK: Out: 
 ; CHECK-NEXT:  %tmp.6 = sdiv i32 %N, %N_addr.0.pn
 ; CHECK-NEXT:  ret i32 %tmp.6
@@ -241,7 +241,7 @@ Loop:
 	br i1 false, label %Loop, label %Out
 Out:
 	ret void
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK:     Out:
 ; CHECK-NEXT:  ret void
 }
diff --git a/test/Transforms/LICM/speculate.ll b/test/Transforms/LICM/speculate.ll
index 4c4d036..4244f15 100644
--- a/test/Transforms/LICM/speculate.ll
+++ b/test/Transforms/LICM/speculate.ll
@@ -2,7 +2,7 @@
 
 ; UDiv is safe to speculate if the denominator is known non-zero.
 
-; CHECK: @safe_udiv
+; CHECK-LABEL: @safe_udiv(
 ; CHECK:      %div = udiv i64 %x, %or
 ; CHECK-NEXT: br label %for.body
 
@@ -35,7 +35,7 @@ for.end:                                          ; preds = %for.inc, %entry
 
 ; UDiv is unsafe to speculate if the denominator is not known non-zero.
 
-; CHECK: @unsafe_udiv
+; CHECK-LABEL: @unsafe_udiv(
 ; CHECK-NOT:  udiv
 ; CHECK: for.body:
 
@@ -68,7 +68,7 @@ for.end:                                          ; preds = %for.inc, %entry
 ; SDiv is safe to speculate if the denominator is known non-zero and
 ; known to have at least one zero bit.
 
-; CHECK: @safe_sdiv
+; CHECK-LABEL: @safe_sdiv(
 ; CHECK:      %div = sdiv i64 %x, %or
 ; CHECK-NEXT: br label %for.body
 
@@ -102,7 +102,7 @@ for.end:                                          ; preds = %for.inc, %entry
 
 ; SDiv is unsafe to speculate if the denominator is not known non-zero.
 
-; CHECK: @unsafe_sdiv_a
+; CHECK-LABEL: @unsafe_sdiv_a(
 ; CHECK-NOT:  sdiv
 ; CHECK: for.body:
 
@@ -135,7 +135,7 @@ for.end:                                          ; preds = %for.inc, %entry
 
 ; SDiv is unsafe to speculate if the denominator is not known to have a zero bit.
 
-; CHECK: @unsafe_sdiv_b
+; CHECK-LABEL: @unsafe_sdiv_b(
 ; CHECK-NOT:  sdiv
 ; CHECK: for.body:
 
diff --git a/test/Transforms/LoopIdiom/basic.ll b/test/Transforms/LoopIdiom/basic.ll
index 06a5bd9..835a9f6 100644
--- a/test/Transforms/LoopIdiom/basic.ll
+++ b/test/Transforms/LoopIdiom/basic.ll
@@ -16,7 +16,7 @@ for.body:                                         ; preds = %bb.nph, %for.body
 
 for.end:                                          ; preds = %for.body, %entry
   ret void
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %Base, i8 0, i64 %Size, i32 1, i1 false)
 ; CHECK-NOT: store
 }
@@ -39,7 +39,7 @@ for.body.cont:
 
 for.end:                                          ; preds = %for.body, %entry
   ret void
-; CHECK: @test1a
+; CHECK-LABEL: @test1a(
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %Base, i8 0, i64 %Size, i32 1, i1 false)
 ; CHECK-NOT: store
 }
@@ -60,7 +60,7 @@ for.body:                                         ; preds = %entry, %for.body
 
 for.end:                                          ; preds = %for.body, %entry
   ret void
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: br i1 %cmp10,
 ; CHECK: %0 = mul i64 %Size, 4
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %Base1, i8 1, i64 %0, i32 4, i1 false)
@@ -85,7 +85,7 @@ for.body:                                         ; preds = %entry, %for.body
 
 for.end:                                          ; preds = %entry
   ret void
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NOT: memset
 ; CHECK: ret void
 }
@@ -111,7 +111,7 @@ for.body:                                         ; preds = %bb.nph, %for.body
 
 for.end:                                          ; preds = %for.body, %entry
   ret void
-; CHECK-TODO: @test4
+; CHECK-TODO-LABEL: @test4(
 ; CHECK-TODO: call void @llvm.memset.p0i8.i64(i8* %Base, i8 0, i64 100, i32 1, i1 false)
 ; CHECK-TODO-NOT: store
 }
@@ -133,7 +133,7 @@ for.body:                                         ; preds = %bb.nph, %for.body
 
 for.end:                                          ; preds = %for.body, %entry
   ret void
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NOT: memset
 ; CHECK: ret void
 }
@@ -158,7 +158,7 @@ for.body:                                         ; preds = %bb.nph, %for.body
 
 for.end:                                          ; preds = %for.body, %entry
   ret void
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %Dest, i8* %Base, i64 %Size, i32 1, i1 false)
 ; CHECK-NOT: store
 ; CHECK: ret void
@@ -183,7 +183,7 @@ for.body.cont:
 
 for.end:                                          ; preds = %for.body, %entry
   ret void
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %Base, i8 0, i64 %Size, i32 1, i1 false)
 ; CHECK-NOT: store
 }
@@ -203,7 +203,7 @@ for.body:                                         ; preds = %bb.nph, %for.body
 
 for.end:                                          ; preds = %for.body, %entry
   ret void
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: store i64 0, i64* %PI
 }
 
@@ -235,7 +235,7 @@ for.body:                                         ; preds = %bb.nph, %for.body
 
 for.end:                                          ; preds = %for.body, %entry
   ret void
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NOT: llvm.memcpy
 ; CHECK: ret void
 }
@@ -267,7 +267,7 @@ for.inc10:                                        ; preds = %for.body5
 
 for.end13:                                        ; preds = %for.inc10
   ret void
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK: entry:
 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %X, i8 0, i64 10000, i32 1, i1 false)
 ; CHECK-NOT: store
@@ -291,7 +291,7 @@ for.body:                                         ; preds = %entry, %for.body
 
 for.end:                                          ; preds = %for.body
   ret void
-; CHECK: @test11_pattern
+; CHECK-LABEL: @test11_pattern(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: bitcast
 ; CHECK-NEXT: memset_pattern
@@ -314,7 +314,7 @@ for.body:                                         ; preds = %entry, %for.body
 
 for.end:                                          ; preds = %for.body
   ret void
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: bitcast
 ; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* %P1, i8 0, i64 80000, i32 4, i1 false)
@@ -340,7 +340,7 @@ for.body:                                         ; preds = %entry, %for.body
 
 for.end:                                          ; preds = %for.body
   ret void
-; CHECK: @test13_pattern
+; CHECK-LABEL: @test13_pattern(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: bitcast
 ; CHECK-NEXT: memset_pattern
@@ -375,7 +375,7 @@ for.body:                                         ; preds = %for.inc, %for.body.
 for.end:                                          ; preds = %for.inc
   %tmp8 = load i32* getelementptr inbounds ([7 x i32]* @g_50, i32 0, i64 6), align 4
   ret i32 %tmp8
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK: for.body:
 ; CHECK: load i32
 ; CHECK: store i32
@@ -389,7 +389,7 @@ define void @PR14241(i32* %s, i64 %size) {
 ; instead of a memmove. If we get the memmove transform back, this will catch
 ; regressions.
 ;
-; CHECK: @PR14241
+; CHECK-LABEL: @PR14241(
 
 entry:
   %end.idx = add i64 %size, -1
diff --git a/test/Transforms/LoopIdiom/debug-line.ll b/test/Transforms/LoopIdiom/debug-line.ll
index d31662d..2337590 100644
--- a/test/Transforms/LoopIdiom/debug-line.ll
+++ b/test/Transforms/LoopIdiom/debug-line.ll
@@ -29,21 +29,22 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.sp = !{!0}
 
-!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (double*)* @foo} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 589865, metadata !"li.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"li.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 127165:127174)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 589870, metadata !18, metadata !1, metadata !"foo", metadata !"foo", metadata !"", i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (double*)* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 589865, metadata !18} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 589841, metadata !18, i32 12, metadata !"clang version 2.9 (trunk 127165:127174)", i1 true, metadata !"", i32 0, metadata !9, metadata !9, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 589845, metadata !18, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{null}
 !5 = metadata !{i32 590081, metadata !0, metadata !"a", metadata !1, i32 16777218, metadata !6, i32 0} ; [ DW_TAG_arg_variable ]
-!6 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ]
-!7 = metadata !{i32 589860, metadata !2, metadata !"double", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 589839, null, metadata !2, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ]
+!7 = metadata !{i32 589860, null, metadata !2, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
 !8 = metadata !{i32 2, i32 18, metadata !0, null}
 !9 = metadata !{i32 0}
 !10 = metadata !{i32 590080, metadata !11, metadata !"i", metadata !1, i32 3, metadata !13, i32 0} ; [ DW_TAG_auto_variable ]
-!11 = metadata !{i32 589835, metadata !12, i32 3, i32 3, metadata !1, i32 1} ; [ DW_TAG_lexical_block ]
-!12 = metadata !{i32 589835, metadata !0, i32 2, i32 21, metadata !1, i32 0} ; [ DW_TAG_lexical_block ]
-!13 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!11 = metadata !{i32 589835, metadata !18, metadata !12, i32 3, i32 3, i32 1} ; [ DW_TAG_lexical_block ]
+!12 = metadata !{i32 589835, metadata !18, metadata !0, i32 2, i32 21, i32 0} ; [ DW_TAG_lexical_block ]
+!13 = metadata !{i32 589860, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !14 = metadata !{i32 3, i32 3, metadata !12, null}
 !15 = metadata !{i32 4, i32 5, metadata !11, null}
 !16 = metadata !{i32 3, i32 29, metadata !11, null}
 !17 = metadata !{i32 5, i32 1, metadata !12, null}
+!18 = metadata !{metadata !"li.c", metadata !"/private/tmp"}
diff --git a/test/Transforms/LoopIdiom/memset_noidiom.ll b/test/Transforms/LoopIdiom/memset_noidiom.ll
index 168eb95..f2b55ae 100644
--- a/test/Transforms/LoopIdiom/memset_noidiom.ll
+++ b/test/Transforms/LoopIdiom/memset_noidiom.ll
@@ -2,7 +2,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10.0.0"
 
-; CHECK: @memset
+; CHECK-LABEL: @memset(
 ; CHECK-NOT: llvm.memset
 define i8* @memset(i8* %b, i32 %c, i64 %len) nounwind uwtable ssp {
 entry:
diff --git a/test/Transforms/LoopRotate/basic.ll b/test/Transforms/LoopRotate/basic.ll
index 78878f9..6b92a6e 100644
--- a/test/Transforms/LoopRotate/basic.ll
+++ b/test/Transforms/LoopRotate/basic.ll
@@ -5,7 +5,7 @@ target triple = "x86_64-apple-darwin10.0.0"
 ; PR5319 - The "arrayidx" gep should be hoisted, not duplicated.  We should
 ; end up with one phi node.
 define void @test1() nounwind ssp {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 entry:
   %array = alloca [20 x i32], align 16
   br label %for.cond
@@ -33,7 +33,7 @@ for.end:                                          ; preds = %for.cond
 
 declare void @g(i32*)
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 define void @test2() nounwind ssp {
 entry:
   %array = alloca [20 x i32], align 16
diff --git a/test/Transforms/LoopRotate/dbgvalue.ll b/test/Transforms/LoopRotate/dbgvalue.ll
index 6a8d308..3434cdc 100644
--- a/test/Transforms/LoopRotate/dbgvalue.ll
+++ b/test/Transforms/LoopRotate/dbgvalue.ll
@@ -4,7 +4,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 define i32 @tak(i32 %x, i32 %y, i32 %z) nounwind ssp {
-; CHECK: define i32 @tak
+; CHECK-LABEL: define i32 @tak(
 ; CHECK: entry
 ; CHECK-NEXT: call void @llvm.dbg.value(metadata !{i32 %x}
 
@@ -43,7 +43,7 @@ return:                                           ; preds = %if.end
 define void @FindFreeHorzSeg(i64 %startCol, i64 %row, i64* %rowStart) {
 ; Ensure that the loop increment basic block is rotated into the tail of the
 ; body, even though it contains a debug intrinsic call.
-; CHECK: define void @FindFreeHorzSeg
+; CHECK-LABEL: define void @FindFreeHorzSeg(
 ; CHECK: %dec = add
 ; CHECK-NEXT: tail call void @llvm.dbg.value
 ; CHECK-NEXT: br i1 %tobool, label %for.cond, label %for.end
@@ -68,7 +68,7 @@ for.body:
 
 for.inc:
   %dec = add i64 %i.0, -1
-  tail call void @llvm.dbg.value(metadata !{i64 %dec}, i64 0, metadata undef)
+  tail call void @llvm.dbg.value(metadata !{i64 %dec}, i64 0, metadata !{metadata !"undef"})
   br label %for.cond
 
 for.end:
@@ -79,12 +79,12 @@ for.end:
 
 !llvm.dbg.sp = !{!0}
 
-!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"tak", metadata !"tak", metadata !"", metadata !1, i32 32, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32, i32, i32)* @tak} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 589865, metadata !"/Volumes/Lalgate/cj/llvm/projects/llvm-test/SingleSource/Benchmarks/BenchmarkGame/recursive.c", metadata !"/Volumes/Lalgate/cj/D/projects/llvm-test/SingleSource/Benchmarks/BenchmarkGame", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/Volumes/Lalgate/cj/llvm/projects/llvm-test/SingleSource/Benchmarks/BenchmarkGame/recursive.c", metadata !"/Volumes/Lalgate/cj/D/projects/llvm-test/SingleSource/Benchmarks/BenchmarkGame", metadata !"clang version 2.9 (trunk 125492)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 589870, metadata !18, metadata !1, metadata !"tak", metadata !"tak", metadata !"", i32 32, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32, i32, i32)* @tak, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 589865, metadata !18} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 589841, metadata !18, i32 12, metadata !"clang version 2.9 (trunk 125492)", i1 true, metadata !"", i32 0, metadata !19, metadata !19, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 589845, metadata !18, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 589860, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !6 = metadata !{i32 590081, metadata !0, metadata !"x", metadata !1, i32 32, metadata !5, i32 0} ; [ DW_TAG_arg_variable ]
 !7 = metadata !{i32 32, i32 13, metadata !0, null}
 !8 = metadata !{i32 590081, metadata !0, metadata !"y", metadata !1, i32 32, metadata !5, i32 0} ; [ DW_TAG_arg_variable ]
@@ -92,8 +92,10 @@ for.end:
 !10 = metadata !{i32 590081, metadata !0, metadata !"z", metadata !1, i32 32, metadata !5, i32 0} ; [ DW_TAG_arg_variable ]
 !11 = metadata !{i32 32, i32 27, metadata !0, null}
 !12 = metadata !{i32 33, i32 3, metadata !13, null}
-!13 = metadata !{i32 589835, metadata !0, i32 32, i32 30, metadata !1, i32 6} ; [ DW_TAG_lexical_block ]
+!13 = metadata !{i32 589835, metadata !18, metadata !0, i32 32, i32 30, i32 6} ; [ DW_TAG_lexical_block ]
 !14 = metadata !{i32 34, i32 5, metadata !15, null}
-!15 = metadata !{i32 589835, metadata !13, i32 33, i32 14, metadata !1, i32 7} ; [ DW_TAG_lexical_block ]
+!15 = metadata !{i32 589835, metadata !18, metadata !13, i32 33, i32 14, i32 7} ; [ DW_TAG_lexical_block ]
 !16 = metadata !{i32 36, i32 3, metadata !13, null}
 !17 = metadata !{i32 37, i32 1, metadata !13, null}
+!18 = metadata !{metadata !"/Volumes/Lalgate/cj/llvm/projects/llvm-test/SingleSource/Benchmarks/BenchmarkGame/recursive.c", metadata !"/Volumes/Lalgate/cj/D/projects/llvm-test/SingleSource/Benchmarks/BenchmarkGame"}
+!19 = metadata !{i32 0}
diff --git a/test/Transforms/LoopRotate/multiple-exits.ll b/test/Transforms/LoopRotate/multiple-exits.ll
index 675d71f..cc8738e 100644
--- a/test/Transforms/LoopRotate/multiple-exits.ll
+++ b/test/Transforms/LoopRotate/multiple-exits.ll
@@ -32,7 +32,7 @@ return:                                           ; preds = %for.cond, %land.rhs
   %retval.0 = phi i32 [ 1000, %land.rhs ], [ %sum.0, %for.cond ]
   ret i32 %retval.0
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: for.cond1.preheader:
 ; CHECK: %sum.04 = phi i32 [ 0, %entry ], [ %sum.1.lcssa, %for.cond.loopexit ]
 ; CHECK: br label %for.cond1
@@ -73,7 +73,7 @@ return.loopexit:                                  ; preds = %for.cond
 return:                                           ; preds = %return.loopexit, %a
   ret void
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: if.end:
 ; CHECK: %inc = add i32 %i.02, 1
 ; CHECK: %cmp = icmp eq i32 %inc, %x
diff --git a/test/Transforms/LoopRotate/phi-duplicate.ll b/test/Transforms/LoopRotate/phi-duplicate.ll
index 8ad2dce..86a4f2a 100644
--- a/test/Transforms/LoopRotate/phi-duplicate.ll
+++ b/test/Transforms/LoopRotate/phi-duplicate.ll
@@ -29,7 +29,7 @@ for.end:                                          ; preds = %for.cond
 }
 
 ; Should only end up with one phi.
-; CHECK:      define void @test
+; CHECK-LABEL:      define void @test(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   br label %for.body
 ; CHECK:      for.body:
diff --git a/test/Transforms/LoopRotate/simplifylatch.ll b/test/Transforms/LoopRotate/simplifylatch.ll
index 037bb20..d646cb9 100644
--- a/test/Transforms/LoopRotate/simplifylatch.ll
+++ b/test/Transforms/LoopRotate/simplifylatch.ll
@@ -3,7 +3,7 @@
 
 @mode_table = global [4 x i32] zeroinitializer		; <[4 x i32]*> [#uses=1]
 
-; CHECK: @f
+; CHECK-LABEL: @f(
 ; CHECK-NOT: bb4
 define i8 @f() {
 entry:
diff --git a/test/Transforms/LoopSimplify/preserve-scev.ll b/test/Transforms/LoopSimplify/preserve-scev.ll
index 854c612..89626b2 100644
--- a/test/Transforms/LoopSimplify/preserve-scev.ll
+++ b/test/Transforms/LoopSimplify/preserve-scev.ll
@@ -50,7 +50,7 @@ return:                                           ; preds = %for.body18, %for.bo
 declare void @foo() nounwind
 
 ; Notify SCEV when removing an ExitingBlock.
-; CHECK: @mergeExit
+; CHECK-LABEL: @mergeExit(
 ; CHECK: while.cond191:
 ; CHECK: br i1 %or.cond, label %while.body197
 ; CHECK-NOT: land.rhs:
diff --git a/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll b/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll
index af3a537..ccf8ebd 100644
--- a/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll
+++ b/test/Transforms/LoopStrengthReduce/2011-10-03-CritEdgeMerge.ll
@@ -5,7 +5,7 @@
 target triple = "x86-apple-darwin"
 
 ; Verify that identical edges are merged. rdar://problem/6453893
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: bb89:
 ; CHECK: phi i8* [ %lsr.iv.next1, %bbA.bb89_crit_edge ], [ %lsr.iv.next1, %bbB.bb89_crit_edge ]{{$}}
 
@@ -43,7 +43,7 @@ exit:
 }
 
 ; Handle single-predecessor phis: PR13756
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: bb89:
 ; CHECK: phi i8* [ %lsr.iv.next1, %bbA ], [ %lsr.iv.next1, %bbA ], [ %lsr.iv.next1, %bbA ]{{$}}
 define i8* @test2() {
diff --git a/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll b/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll
index 1ee9bb4..83963e3 100644
--- a/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll
+++ b/test/Transforms/LoopStrengthReduce/2011-10-06-ReusePhi.ll
@@ -5,7 +5,7 @@
 
 target triple = "x86-apple-darwin"
 
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; multiplies are hoisted out of the loop
 ; CHECK: while.body.lr.ph:
 ; CHECK: mul i64
diff --git a/test/Transforms/LoopStrengthReduce/2011-10-13-SCEVChain.ll b/test/Transforms/LoopStrengthReduce/2011-10-13-SCEVChain.ll
index 4718529..484fefa 100644
--- a/test/Transforms/LoopStrengthReduce/2011-10-13-SCEVChain.ll
+++ b/test/Transforms/LoopStrengthReduce/2011-10-13-SCEVChain.ll
@@ -8,7 +8,7 @@ target triple = "x86_64-apple-darwin"
 
 ; Verify that -loop-reduce runs without "hanging" and reuses post-inc
 ; expansions.
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK: icmp
 ; CHECK: icmp
 ; CHECK: icmp
diff --git a/test/Transforms/LoopStrengthReduce/2011-10-14-IntPtr.ll b/test/Transforms/LoopStrengthReduce/2011-10-14-IntPtr.ll
index 60cc7a5..068b716 100644
--- a/test/Transforms/LoopStrengthReduce/2011-10-14-IntPtr.ll
+++ b/test/Transforms/LoopStrengthReduce/2011-10-14-IntPtr.ll
@@ -5,7 +5,7 @@
 
 target triple = "x86_64-apple-darwin"
 
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK: phi
 ; CHECK-NOT: phi
 define void @test(i32 %rowStride) ssp align 2 {
diff --git a/test/Transforms/LoopStrengthReduce/2011-12-19-PostincQuadratic.ll b/test/Transforms/LoopStrengthReduce/2011-12-19-PostincQuadratic.ll
index 392a8bc..6c128fe 100644
--- a/test/Transforms/LoopStrengthReduce/2011-12-19-PostincQuadratic.ll
+++ b/test/Transforms/LoopStrengthReduce/2011-12-19-PostincQuadratic.ll
@@ -9,7 +9,7 @@ target triple = "i386-unknown-freebsd10.0"
 
 @b = external global [121 x i32]
 
-; CHECK: @vb
+; CHECK-LABEL: @vb(
 ;   Outer recurrence:
 ; CHECK: %lsr.iv1 = phi [121 x i32]*
 ;   Inner recurrence:
diff --git a/test/Transforms/LoopStrengthReduce/2012-01-02-nopreheader.ll b/test/Transforms/LoopStrengthReduce/2012-01-02-nopreheader.ll
index d7f5723..87dd397 100644
--- a/test/Transforms/LoopStrengthReduce/2012-01-02-nopreheader.ll
+++ b/test/Transforms/LoopStrengthReduce/2012-01-02-nopreheader.ll
@@ -11,7 +11,7 @@ target triple = "i386-apple-darwin"
 ; cannot find a preheader, so they should be expanded in the loop header
 ; (bb7.lr.ph.us) below the existing phi i.12.us.
 ; Currently, LSR won't kick in on such loops.
-; CHECK: @nopreheader
+; CHECK-LABEL: @nopreheader(
 ; CHECK: bb7.us:
 ; CHECK-NOT: phi float*
 ; CHECK: %j.01.us = phi i32
@@ -54,7 +54,7 @@ return:                                           ; preds = %bb9, %bb9.us, %bb10
 ; In this case, SCEVExpander simply cannot materialize the AddRecExpr
 ; that LSR picks. We must detect that %bb8.preheader does not have a
 ; preheader and avoid performing LSR on %bb7.
-; CHECK: @nopreheader2
+; CHECK-LABEL: @nopreheader2(
 ; CHECK: bb7:
 ; CHECK: %indvar = phi i32
 define fastcc void @nopreheader2([200 x i32]* nocapture %Array2) nounwind {
diff --git a/test/Transforms/LoopStrengthReduce/2012-01-16-nopreheader.ll b/test/Transforms/LoopStrengthReduce/2012-01-16-nopreheader.ll
index 3036a7e..94a037e 100644
--- a/test/Transforms/LoopStrengthReduce/2012-01-16-nopreheader.ll
+++ b/test/Transforms/LoopStrengthReduce/2012-01-16-nopreheader.ll
@@ -8,7 +8,7 @@ target triple = "x86_64-apple-darwin10.0.0"
 ; while.cond197 is a dominates the simplified loop while.cond238 but
 ; has no with no preheader.
 ;
-; CHECK: @nopreheader
+; CHECK-LABEL: @nopreheader(
 ; CHECK: %while.cond238
 ; CHECK: phi i64
 ; CHECK-NOT: phi
diff --git a/test/Transforms/LoopStrengthReduce/2012-03-15-nopreheader.ll b/test/Transforms/LoopStrengthReduce/2012-03-15-nopreheader.ll
index 0172492..5fa3838 100644
--- a/test/Transforms/LoopStrengthReduce/2012-03-15-nopreheader.ll
+++ b/test/Transforms/LoopStrengthReduce/2012-03-15-nopreheader.ll
@@ -7,7 +7,7 @@ target triple = "x86_64-apple-darwin10.0.0"
 
 ; IVUsers should not consider tmp128 a valid user because it is not in a
 ; simplified loop nest.
-; CHECK: @nopreheader
+; CHECK-LABEL: @nopreheader(
 ; CHECK: for.cond:
 ; CHECK: %tmp128 = add i64 %0, %indvar65
 define void @nopreheader(i8* %cmd) nounwind ssp {
diff --git a/test/Transforms/LoopStrengthReduce/2012-07-13-ExpandUDiv.ll b/test/Transforms/LoopStrengthReduce/2012-07-13-ExpandUDiv.ll
index 8bac639..ea1d65b 100644
--- a/test/Transforms/LoopStrengthReduce/2012-07-13-ExpandUDiv.ll
+++ b/test/Transforms/LoopStrengthReduce/2012-07-13-ExpandUDiv.ll
@@ -10,7 +10,7 @@ target triple = "x86_64-apple-darwin"
 @g_3 = global i32 0, align 4
 
 ; Ensure that %div.i.i.us is not hoisted.
-; CHECK: @main
+; CHECK-LABEL: @main(
 ; CHECK: for.body.i.i.us:
 ; CHECK: %div.i.i.i.us
 ; CHECK: %cmp5.i.i.us
diff --git a/test/Transforms/LoopStrengthReduce/2013-01-05-IndBr.ll b/test/Transforms/LoopStrengthReduce/2013-01-05-IndBr.ll
index bce234c..8a5a0a4 100644
--- a/test/Transforms/LoopStrengthReduce/2013-01-05-IndBr.ll
+++ b/test/Transforms/LoopStrengthReduce/2013-01-05-IndBr.ll
@@ -5,7 +5,7 @@
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128"
 
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK: bb8:
 ; CHECK-NEXT: phi i8
 ; CHECK-NEXT: phi i8
diff --git a/test/Transforms/LoopStrengthReduce/2013-01-14-ReuseCast.ll b/test/Transforms/LoopStrengthReduce/2013-01-14-ReuseCast.ll
index 652eb06..79dbf0d 100644
--- a/test/Transforms/LoopStrengthReduce/2013-01-14-ReuseCast.ll
+++ b/test/Transforms/LoopStrengthReduce/2013-01-14-ReuseCast.ll
@@ -8,7 +8,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 
 ; Verify that nothing uses the "dead" ptrtoint from "undef".
-; CHECK: @VerifyDiagnosticConsumerTest
+; CHECK-LABEL: @VerifyDiagnosticConsumerTest(
 ; CHECK: bb:
 ; "dead" ptrpoint not emitted (or dead code eliminated) with
 ; current LSR cost model.
diff --git a/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll b/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll
index ee3cc4d..ab7f20f 100644
--- a/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll
+++ b/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll
@@ -138,7 +138,7 @@ for.end:                                          ; preds = %for.body, %entry
 ; Consequently, we should *not* form any chains.
 ;
 ; A9: foldedidx:
-; A9: ldrb.w {{r[0-9]|lr}}, [{{r[0-9]|lr}}, #3]
+; A9: ldrb{{(.w)?}} {{r[0-9]|lr}}, [{{r[0-9]|lr}}, #3]
 define void @foldedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c) nounwind ssp {
 entry:
   br label %for.body
diff --git a/test/Transforms/LoopStrengthReduce/X86/2011-07-20-DoubleIV.ll b/test/Transforms/LoopStrengthReduce/X86/2011-07-20-DoubleIV.ll
index a932b47..2fe62e3 100644
--- a/test/Transforms/LoopStrengthReduce/X86/2011-07-20-DoubleIV.ll
+++ b/test/Transforms/LoopStrengthReduce/X86/2011-07-20-DoubleIV.ll
@@ -5,7 +5,7 @@
 ; rdar://9786536
 
 ; First, make sure LSR doesn't crash on an empty IVUsers list.
-; CHECK: @dummyIV
+; CHECK-LABEL: @dummyIV(
 ; CHECK-NOT: phi
 ; CHECK-NOT: sitofp
 ; CHECK: br
@@ -24,7 +24,7 @@ for.end:
 }
 
 ; Now check that the computed double constant is correct.
-; CHECK: @doubleIV
+; CHECK-LABEL: @doubleIV(
 ; CHECK: phi double [ -3.900000e+01, %entry ]
 ; CHECK: br
 define void @doubleIV() nounwind {
diff --git a/test/Transforms/LoopStrengthReduce/X86/2011-12-04-loserreg.ll b/test/Transforms/LoopStrengthReduce/X86/2011-12-04-loserreg.ll
index eedfc20..fad5241 100644
--- a/test/Transforms/LoopStrengthReduce/X86/2011-12-04-loserreg.ll
+++ b/test/Transforms/LoopStrengthReduce/X86/2011-12-04-loserreg.ll
@@ -14,7 +14,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-darwin"
 
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK: for.body:
 ; CHECK: %lsr.iv
 ; CHECK-NOT: %dummyout
diff --git a/test/Transforms/LoopStrengthReduce/ivchain.ll b/test/Transforms/LoopStrengthReduce/ivchain.ll
index ce7ad19..233800b 100644
--- a/test/Transforms/LoopStrengthReduce/ivchain.ll
+++ b/test/Transforms/LoopStrengthReduce/ivchain.ll
@@ -6,7 +6,7 @@
 
 %struct = type { i8*, i8*, i16, i64, i16, i16, i16, i64, i64, i16, i8*, i64, i64, i64 }
 
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK: for.body:
 ; CHECK: lsr.iv = phi %struct
 ; CHECK: br
diff --git a/test/Transforms/LoopStrengthReduce/scaling_factor_cost_crash.ll b/test/Transforms/LoopStrengthReduce/scaling_factor_cost_crash.ll
new file mode 100644
index 0000000..a652a76
--- /dev/null
+++ b/test/Transforms/LoopStrengthReduce/scaling_factor_cost_crash.ll
@@ -0,0 +1,68 @@
+; RUN: opt -loop-reduce %s -S -o - | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"
+target triple = "i686-pc-win32"
+
+; <rdar://problem/14199725> Assertion failed: (CurScaleCost >= 0 && "Legal addressing mode has an illegal cost!")
+; CHECK-LABEL: @scalingFactorCrash(
+define void @scalingFactorCrash() {
+  br i1 undef, label %1, label %24
+
+; <label>:1                                       ; preds = %0
+  br i1 undef, label %2, label %24
+
+; <label>:2                                       ; preds = %1
+  br i1 undef, label %3, label %24
+
+; <label>:3                                       ; preds = %2
+  br i1 undef, label %4, label %24
+
+; <label>:4                                       ; preds = %3
+  br i1 undef, label %24, label %6
+
+; <label>:5                                       ; preds = %6
+  br i1 undef, label %24, label %7
+
+; <label>:6                                       ; preds = %6, %4
+  br i1 undef, label %6, label %5
+
+; <label>:7                                       ; preds = %9, %5
+  br label %8
+
+; <label>:8                                       ; preds = %8, %7
+  br i1 undef, label %9, label %8
+
+; <label>:9                                       ; preds = %8
+  br i1 undef, label %7, label %10
+
+; <label>:10                                      ; preds = %9
+  br i1 undef, label %24, label %11
+
+; <label>:11                                      ; preds = %10
+  br i1 undef, label %15, label %13
+
+; <label>:12                                      ; preds = %14
+  br label %15
+
+; <label>:13                                      ; preds = %11
+  br label %14
+
+; <label>:14                                      ; preds = %14, %13
+  br i1 undef, label %14, label %12
+
+; <label>:15                                      ; preds = %12, %11
+  br i1 undef, label %16, label %24
+
+; <label>:16                                      ; preds = %16, %15
+  %17 = phi i32 [ %21, %16 ], [ undef, %15 ]
+  %18 = sub i32 %17, 1623127498
+  %19 = getelementptr inbounds i32* undef, i32 %18
+  store i32 undef, i32* %19, align 4
+  %20 = add i32 %17, 1623127499
+  %21 = add i32 %20, -1623127498
+  %22 = add i32 %21, -542963121
+  %23 = icmp ult i32 %22, undef
+  br i1 undef, label %16, label %24
+
+; <label>:24                                      ; preds = %16, %15, %10, %5, %4, %3, %2, %1, %0
+  ret void
+}
diff --git a/test/Transforms/LoopStrengthReduce/uglygep.ll b/test/Transforms/LoopStrengthReduce/uglygep.ll
index 10c77d5..4562d29 100644
--- a/test/Transforms/LoopStrengthReduce/uglygep.ll
+++ b/test/Transforms/LoopStrengthReduce/uglygep.ll
@@ -6,7 +6,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 
 define void @Z4() nounwind {
-; CHECK: define void @Z4
+; CHECK-LABEL: define void @Z4(
 bb:
   br label %bb3
 
@@ -52,7 +52,7 @@ bb14:                                             ; preds = %bb14, %bb10
 }
 
 define fastcc void @TransformLine() nounwind {
-; CHECK: @TransformLine
+; CHECK-LABEL: @TransformLine(
 bb:
   br label %loop0
 
diff --git a/test/Transforms/LoopUnroll/2011-08-08-PhiUpdate.ll b/test/Transforms/LoopUnroll/2011-08-08-PhiUpdate.ll
index cd954c8..bf6d6d5 100644
--- a/test/Transforms/LoopUnroll/2011-08-08-PhiUpdate.ll
+++ b/test/Transforms/LoopUnroll/2011-08-08-PhiUpdate.ll
@@ -30,7 +30,7 @@ if.then:                                          ; preds = %if.else, %entry
 
 ; PR7318: assertion failure after doing a simple loop unroll
 ;
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: bb1.bb2_crit_edge:
 ; CHECK: %.lcssa = phi i32 [ %{{[2468]}}, %bb1{{.*}} ], [ %{{[2468]}}, %bb1{{.*}} ], [ %{{[2468]}}, %bb1{{.*}} ], [ %{{[2468]}}, %bb1{{.*}} ]
 ; CHECK: bb1.3:
@@ -67,7 +67,7 @@ bb2:                                              ; preds = %bb1.bb2_crit_edge,
 
 ; Check phi update for loop with an early-exit.
 ;
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: return.loopexit:
 ; CHECK: %tmp7.i.lcssa = phi i32 [ %tmp7.i{{.*}}, %land.lhs.true{{.*}} ], [ %tmp7.i{{.*}}, %land.lhs.true{{.*}} ], [ %tmp7.i{{.*}}, %land.lhs.true{{.*}} ], [ %tmp7.i{{.*}}, %land.lhs.true{{.*}} ]
 ; CHECK: exit.3:
diff --git a/test/Transforms/LoopUnroll/2011-08-09-PhiUpdate.ll b/test/Transforms/LoopUnroll/2011-08-09-PhiUpdate.ll
index c1221f5..8344993 100644
--- a/test/Transforms/LoopUnroll/2011-08-09-PhiUpdate.ll
+++ b/test/Transforms/LoopUnroll/2011-08-09-PhiUpdate.ll
@@ -12,10 +12,10 @@ declare i32 @getval() nounwind
 ; Check that the loop exit merges values from all the iterations. This
 ; could be a tad fragile, but it's a good test.
 ;
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK: return:
 ; CHECK: %retval.0 = phi i32 [ %tmp7.i, %land.lhs.true ], [ 0, %do.cond ], [ %tmp7.i.1, %land.lhs.true.1 ], [ 0, %do.cond.1 ], [ %tmp7.i.2, %land.lhs.true.2 ], [ 0, %do.cond.2 ], [ %tmp7.i.3, %land.lhs.true.3 ], [ 0, %do.cond.3 ]
-; CHECK-NOT: @bar
+; CHECK-NOT: @bar(
 ; CHECK: bar.exit.3
 define i32 @foo() uwtable ssp align 2 {
 entry:
diff --git a/test/Transforms/LoopUnroll/2011-10-01-NoopTrunc.ll b/test/Transforms/LoopUnroll/2011-10-01-NoopTrunc.ll
index 7fb471e..617d4db 100644
--- a/test/Transforms/LoopUnroll/2011-10-01-NoopTrunc.ll
+++ b/test/Transforms/LoopUnroll/2011-10-01-NoopTrunc.ll
@@ -8,7 +8,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 
 ; Check that for.body was unrolled 19 times.
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK: %0 = load
 ; CHECK: %conv = sext i8 %0 to i32
 ; CHECK: %add.1 = add nsw i32 %conv.1, %conv
diff --git a/test/Transforms/LoopUnroll/basic.ll b/test/Transforms/LoopUnroll/basic.ll
index ab5bc56..2bfd3e6 100644
--- a/test/Transforms/LoopUnroll/basic.ll
+++ b/test/Transforms/LoopUnroll/basic.ll
@@ -3,7 +3,7 @@
 
 ; This should not unroll since the address of the loop header is taken.
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: store i8* blockaddress(@test1, %l1), i8** %P
 ; CHECK: l1:
 ; CHECK-NEXT: phi i32
@@ -25,7 +25,7 @@ l2:                                               ; preds = %l1
 
 ; This should not unroll since the call is 'noduplicate'.
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 define i32 @test2(i8** %P) nounwind ssp {
 entry:
   br label %l1
diff --git a/test/Transforms/LoopUnroll/pr14167.ll b/test/Transforms/LoopUnroll/pr14167.ll
index 205ae44..9aac701 100644
--- a/test/Transforms/LoopUnroll/pr14167.ll
+++ b/test/Transforms/LoopUnroll/pr14167.ll
@@ -4,7 +4,7 @@ target triple = "powerpc64-bgq-linux"
 
 define void @test1() nounwind {
 ; Ensure that we don't crash when the trip count == -1.
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 entry:
   br label %for.cond2.preheader
 
diff --git a/test/Transforms/LoopUnroll/scevunroll.ll b/test/Transforms/LoopUnroll/scevunroll.ll
index 308a036..c3086e8 100644
--- a/test/Transforms/LoopUnroll/scevunroll.ll
+++ b/test/Transforms/LoopUnroll/scevunroll.ll
@@ -7,7 +7,7 @@
 
 ; Completely unroll loops without a canonical IV.
 ;
-; CHECK: @sansCanonical
+; CHECK-LABEL: @sansCanonical(
 ; CHECK-NOT: phi
 ; CHECK-NOT: icmp
 ; CHECK: ret
@@ -35,7 +35,7 @@ exit:
 ; latch block. Canonical unrolling incorrectly unrolls it, but SCEV
 ; unrolling does not.
 ;
-; CHECK: @earlyLoopTest
+; CHECK-LABEL: @earlyLoopTest(
 ; CHECK: tail:
 ; CHECK-NOT: br
 ; CHECK: br i1 %cmp2, label %loop, label %exit2
@@ -69,7 +69,7 @@ exit2:
 ; SCEV cannot currently unroll this loop.
 ; It should ideally detect a trip count of 5.
 ; rdar:14038809 [SCEV]: Optimize trip count computation for multi-exit loops.
-; CHECK: @multiExit
+; CHECK-LABEL: @multiExit(
 ; CHECKFIXME: getelementptr i32* %base, i32 10
 ; CHECKFIXME-NEXT: load i32*
 ; CHECKFIXME: br i1 false, label %l2.10, label %exit1
@@ -103,7 +103,7 @@ exit2:
 ; LoopUnroll utility uses this assumption to optimize the latch
 ; block's branch.
 ;
-; CHECK: @multiExit
+; CHECK-LABEL: @multiExitIncomplete(
 ; CHECK: l3:
 ; CHECK-NOT: br
 ; CHECK:   br i1 %cmp3, label %l1, label %exit3
@@ -137,7 +137,7 @@ exit3:
 ; When loop unroll merges a loop exit with one of its parent loop's
 ; exits, SCEV must forget its ExitNotTaken info.
 ;
-; CHECK: @nestedUnroll
+; CHECK-LABEL: @nestedUnroll(
 ; CHECK-NOT: br i1
 ; CHECK: for.body87:
 define void @nestedUnroll() nounwind {
@@ -183,7 +183,7 @@ for.body87:
 ; the loop latch's exit count of zero is an upper bound on the number
 ; of iterations.
 ;
-; CHECK: @nsw_latch
+; CHECK-LABEL: @nsw_latch(
 ; CHECK: for.body:
 ; CHECK: %b.03 = phi i32 [ 0, %entry ], [ %add, %for.cond ]
 ; CHECK: return:
diff --git a/test/Transforms/LoopUnroll/unloop.ll b/test/Transforms/LoopUnroll/unloop.ll
index 9a938cc..b98b4a3 100644
--- a/test/Transforms/LoopUnroll/unloop.ll
+++ b/test/Transforms/LoopUnroll/unloop.ll
@@ -7,7 +7,7 @@ declare i1 @check() nounwind
 ; Ensure that tail->inner is removed and rely on verify-loopinfo to
 ; check soundness.
 ;
-; CHECK: @skiplevelexit
+; CHECK-LABEL: @skiplevelexit(
 ; CHECK: tail:
 ; CHECK-NOT: br
 ; CHECK: ret void
@@ -38,7 +38,7 @@ exit:
 ; Ensure that only the middle loop is removed and rely on verify-loopinfo to
 ; check soundness.
 ;
-; CHECK: @unloopNested
+; CHECK-LABEL: @unloopNested(
 ; Outer loop control.
 ; CHECK: while.body:
 ; CHECK: br i1 %cmp3, label %if.then, label %if.end
@@ -128,7 +128,7 @@ return:
 ;
 ; This test must be disabled until trip count computation can be optimized...
 ; rdar:14038809 [SCEV]: Optimize trip count computation for multi-exit loops.
-; CHECKFIXME: @unloopDeepNested
+; CHECKFIXME-LABEL: @unloopDeepNested(
 ; Inner-inner loop control.
 ; CHECKFIXME: while.cond.us.i:
 ; CHECKFIXME: br i1 %cmp.us.i, label %next_data.exit, label %while.body.us.i
@@ -248,7 +248,7 @@ while.end:
 ; Ensure that only the middle loop is removed and rely on verify-loopinfo to
 ; check soundness.
 ;
-; CHECK: @unloopIrreducible
+; CHECK-LABEL: @unloopIrreducible(
 ; Irreducible loop.
 ; CHECK: for.inc117:
 ; CHECK: br label %for.cond103t
@@ -326,7 +326,7 @@ for.end166:
 ; Ensure that only the loop is removed and rely on verify-loopinfo to
 ; check soundness.
 ;
-; CHECK: @unloopCriticalEdge
+; CHECK-LABEL: @unloopCriticalEdge(
 ; CHECK: while.cond.outer.i.loopexit.split:
 ; CHECK: br label %while.body
 ; CHECK: while.body:
@@ -431,7 +431,7 @@ return:                                           ; preds = %sw.bb304
 }
 
 ; PR11335: the most deeply nested block should be removed from the outer loop.
-; CHECK: @removeSubloopBlocks2
+; CHECK-LABEL: @removeSubloopBlocks2(
 ; CHECK: for.cond3:
 ; CHECK-NOT: br
 ; CHECK: ret void
diff --git a/test/Transforms/LoopUnswitch/basictest.ll b/test/Transforms/LoopUnswitch/basictest.ll
index e98d82b..85e44ec 100644
--- a/test/Transforms/LoopUnswitch/basictest.ll
+++ b/test/Transforms/LoopUnswitch/basictest.ll
@@ -32,7 +32,7 @@ return:		; preds = %endif, %then
 ; This simple test would normally unswitch, but should be inhibited by the presence of
 ; the noduplicate call.
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 define i32 @test2(i32* %var) {
   %mem = alloca i32
   store i32 2, i32* %mem
diff --git a/test/Transforms/LoopUnswitch/infinite-loop.ll b/test/Transforms/LoopUnswitch/infinite-loop.ll
index 8261e38..e79d874 100644
--- a/test/Transforms/LoopUnswitch/infinite-loop.ll
+++ b/test/Transforms/LoopUnswitch/infinite-loop.ll
@@ -11,7 +11,7 @@
 ; STATS: 2 loop-unswitch - Number of branches unswitched
 ; STATS: 1 loop-unswitch - Number of unswitches that are trivial
 
-; CHECK: @func_16
+; CHECK-LABEL: @func_16(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: br i1 %a, label %entry.split, label %abort0.split
 
diff --git a/test/Transforms/LoopVectorize/12-12-11-if-conv.ll b/test/Transforms/LoopVectorize/12-12-11-if-conv.ll
index bab6300..1e1396f 100644
--- a/test/Transforms/LoopVectorize/12-12-11-if-conv.ll
+++ b/test/Transforms/LoopVectorize/12-12-11-if-conv.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
-;CHECK: @foo
+;CHECK-LABEL: @foo(
 ;CHECK: icmp eq <4 x i32>
 ;CHECK: select <4 x i1>
 ;CHECK: ret i32
@@ -30,7 +30,7 @@ if.then:                                          ; preds = %for.body
 if.end:                                           ; preds = %for.body, %if.then
   %z.0 = phi i32 [ %add1, %if.then ], [ 9, %for.body ]
   store i32 %z.0, i32* %arrayidx, align 4
-  %indvars.iv.next = add i64 %indvars.iv, 1
+  %indvars.iv.next = add nsw i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
   %exitcond = icmp eq i32 %lftr.wideiv, %x
   br i1 %exitcond, label %for.end, label %for.body
diff --git a/test/Transforms/LoopVectorize/ARM/arm-unroll.ll b/test/Transforms/LoopVectorize/ARM/arm-unroll.ll
index c8d307f..39363ab 100644
--- a/test/Transforms/LoopVectorize/ARM/arm-unroll.ll
+++ b/test/Transforms/LoopVectorize/ARM/arm-unroll.ll
@@ -4,11 +4,11 @@
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
 target triple = "thumbv7-apple-ios3.0.0"
 
-;CHECK: @foo
+;CHECK-LABEL: @foo(
 ;CHECK: load <4 x i32>
 ;CHECK-NOT: load <4 x i32>
 ;CHECK: ret
-;SWIFT: @foo
+;SWIFT-LABEL: @foo(
 ;SWIFT: load <4 x i32>
 ;SWIFT: load <4 x i32>
 ;SWIFT: ret
diff --git a/test/Transforms/LoopVectorize/ARM/gather-cost.ll b/test/Transforms/LoopVectorize/ARM/gather-cost.ll
new file mode 100644
index 0000000..239a28f
--- /dev/null
+++ b/test/Transforms/LoopVectorize/ARM/gather-cost.ll
@@ -0,0 +1,88 @@
+; RUN: opt -loop-vectorize -mtriple=thumbv7s-apple-ios6.0.0 -S < %s | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
+
+@kernel = global [512 x float] zeroinitializer, align 4
+@kernel2 = global [512 x float] zeroinitializer, align 4
+@kernel3 = global [512 x float] zeroinitializer, align 4
+@kernel4 = global [512 x float] zeroinitializer, align 4
+@src_data = global [1536 x float] zeroinitializer, align 4
+@r_ = global i8 0, align 4
+@g_ = global i8 0, align 4
+@b_ = global i8 0, align 4
+
+; We don't want to vectorize most loops containing gathers because they are
+; expensive. This function represents a point where vectorization starts to
+; become beneficial.
+; Make sure we are conservative and don't vectorize it.
+; CHECK-NOT: <2 x float>
+; CHECK-NOT: <4 x float>
+
+define void @_Z4testmm(i32 %size, i32 %offset) {
+entry:
+  %cmp53 = icmp eq i32 %size, 0
+  br i1 %cmp53, label %for.end, label %for.body.lr.ph
+
+for.body.lr.ph:
+  br label %for.body
+
+for.body:
+  %r.057 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add10, %for.body ]
+  %g.056 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add20, %for.body ]
+  %v.055 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
+  %b.054 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add30, %for.body ]
+  %add = add i32 %v.055, %offset
+  %mul = mul i32 %add, 3
+  %arrayidx = getelementptr inbounds [1536 x float]* @src_data, i32 0, i32 %mul
+  %0 = load float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds [512 x float]* @kernel, i32 0, i32 %v.055
+  %1 = load float* %arrayidx2, align 4
+  %mul3 = fmul fast float %0, %1
+  %arrayidx4 = getelementptr inbounds [512 x float]* @kernel2, i32 0, i32 %v.055
+  %2 = load float* %arrayidx4, align 4
+  %mul5 = fmul fast float %mul3, %2
+  %arrayidx6 = getelementptr inbounds [512 x float]* @kernel3, i32 0, i32 %v.055
+  %3 = load float* %arrayidx6, align 4
+  %mul7 = fmul fast float %mul5, %3
+  %arrayidx8 = getelementptr inbounds [512 x float]* @kernel4, i32 0, i32 %v.055
+  %4 = load float* %arrayidx8, align 4
+  %mul9 = fmul fast float %mul7, %4
+  %add10 = fadd fast float %r.057, %mul9
+  %arrayidx.sum = add i32 %mul, 1
+  %arrayidx11 = getelementptr inbounds [1536 x float]* @src_data, i32 0, i32 %arrayidx.sum
+  %5 = load float* %arrayidx11, align 4
+  %mul13 = fmul fast float %1, %5
+  %mul15 = fmul fast float %2, %mul13
+  %mul17 = fmul fast float %3, %mul15
+  %mul19 = fmul fast float %4, %mul17
+  %add20 = fadd fast float %g.056, %mul19
+  %arrayidx.sum52 = add i32 %mul, 2
+  %arrayidx21 = getelementptr inbounds [1536 x float]* @src_data, i32 0, i32 %arrayidx.sum52
+  %6 = load float* %arrayidx21, align 4
+  %mul23 = fmul fast float %1, %6
+  %mul25 = fmul fast float %2, %mul23
+  %mul27 = fmul fast float %3, %mul25
+  %mul29 = fmul fast float %4, %mul27
+  %add30 = fadd fast float %b.054, %mul29
+  %inc = add i32 %v.055, 1
+  %exitcond = icmp ne i32 %inc, %size
+  br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge
+
+for.cond.for.end_crit_edge:
+  %add30.lcssa = phi float [ %add30, %for.body ]
+  %add20.lcssa = phi float [ %add20, %for.body ]
+  %add10.lcssa = phi float [ %add10, %for.body ]
+  %phitmp = fptoui float %add10.lcssa to i8
+  %phitmp60 = fptoui float %add20.lcssa to i8
+  %phitmp61 = fptoui float %add30.lcssa to i8
+  br label %for.end
+
+for.end:
+  %r.0.lcssa = phi i8 [ %phitmp, %for.cond.for.end_crit_edge ], [ 0, %entry ]
+  %g.0.lcssa = phi i8 [ %phitmp60, %for.cond.for.end_crit_edge ], [ 0, %entry ]
+  %b.0.lcssa = phi i8 [ %phitmp61, %for.cond.for.end_crit_edge ], [ 0, %entry ]
+  store i8 %r.0.lcssa, i8* @r_, align 4
+  store i8 %g.0.lcssa, i8* @g_, align 4
+  store i8 %b.0.lcssa, i8* @b_, align 4
+  ret void
+}
diff --git a/test/Transforms/LoopVectorize/ARM/gcc-examples.ll b/test/Transforms/LoopVectorize/ARM/gcc-examples.ll
index 6a68e81..f2bd0ac 100644
--- a/test/Transforms/LoopVectorize/ARM/gcc-examples.ll
+++ b/test/Transforms/LoopVectorize/ARM/gcc-examples.ll
@@ -8,7 +8,7 @@ target triple = "thumbv7-apple-ios3.0.0"
 @a = common global [2048 x i32] zeroinitializer, align 16
 
 ; Select VF = 8;
-;CHECK: @example1
+;CHECK-LABEL: @example1(
 ;CHECK: load <4 x i32>
 ;CHECK: add nsw <4 x i32>
 ;CHECK: store <4 x i32>
@@ -34,7 +34,7 @@ define void @example1() nounwind uwtable ssp {
   ret void
 }
 
-;CHECK: @example10b
+;CHECK-LABEL: @example10b(
 ;CHECK: load <4 x i16>
 ;CHECK: sext <4 x i16>
 ;CHECK: store <4 x i32>
diff --git a/test/Transforms/LoopVectorize/X86/avx1.ll b/test/Transforms/LoopVectorize/X86/avx1.ll
index 6c0366e..01c9125 100644
--- a/test/Transforms/LoopVectorize/X86/avx1.ll
+++ b/test/Transforms/LoopVectorize/X86/avx1.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
-;CHECK: @read_mod_write_single_ptr
+;CHECK-LABEL: @read_mod_write_single_ptr(
 ;CHECK: load <8 x float>
 ;CHECK: ret i32
 define i32 @read_mod_write_single_ptr(float* nocapture %a, i32 %n) nounwind uwtable ssp {
@@ -26,7 +26,7 @@ define i32 @read_mod_write_single_ptr(float* nocapture %a, i32 %n) nounwind uwta
 }
 
 
-;CHECK: @read_mod_i64
+;CHECK-LABEL: @read_mod_i64(
 ;CHECK: load <2 x i64>
 ;CHECK: ret i32
 define i32 @read_mod_i64(i64* nocapture %a, i32 %n) nounwind uwtable ssp {
diff --git a/test/Transforms/LoopVectorize/X86/conversion-cost.ll b/test/Transforms/LoopVectorize/X86/conversion-cost.ll
index 760d28d..0af562d 100644
--- a/test/Transforms/LoopVectorize/X86/conversion-cost.ll
+++ b/test/Transforms/LoopVectorize/X86/conversion-cost.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
-;CHECK: @conversion_cost1
+;CHECK-LABEL: @conversion_cost1(
 ;CHECK: store <32 x i8>
 ;CHECK: ret
 define i32 @conversion_cost1(i32 %n, i8* nocapture %A, float* nocapture %B) nounwind uwtable ssp {
@@ -24,7 +24,7 @@ define i32 @conversion_cost1(i32 %n, i8* nocapture %A, float* nocapture %B) noun
   ret i32 undef
 }
 
-;CHECK: @conversion_cost2
+;CHECK-LABEL: @conversion_cost2(
 ;CHECK: <2 x float>
 ;CHECK: ret
 define i32 @conversion_cost2(i32 %n, i8* nocapture %A, float* nocapture %B) nounwind uwtable ssp {
diff --git a/test/Transforms/LoopVectorize/X86/gather-cost.ll b/test/Transforms/LoopVectorize/X86/gather-cost.ll
new file mode 100644
index 0000000..09363d6
--- /dev/null
+++ b/test/Transforms/LoopVectorize/X86/gather-cost.ll
@@ -0,0 +1,86 @@
+; RUN: opt -loop-vectorize -mtriple=x86_64-apple-macosx -S -mcpu=corei7-avx < %s | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+@kernel = global [512 x float] zeroinitializer, align 16
+@kernel2 = global [512 x float] zeroinitializer, align 16
+@kernel3 = global [512 x float] zeroinitializer, align 16
+@kernel4 = global [512 x float] zeroinitializer, align 16
+@src_data = global [1536 x float] zeroinitializer, align 16
+@r_ = global i8 0, align 1
+@g_ = global i8 0, align 1
+@b_ = global i8 0, align 1
+
+; We don't want to vectorize most loops containing gathers because they are
+; expensive. This function represents a point where vectorization starts to
+; become beneficial.
+; Make sure we are conservative and don't vectorize it.
+; CHECK-NOT: x float>
+
+define void @_Z4testmm(i64 %size, i64 %offset) {
+entry:
+  %cmp53 = icmp eq i64 %size, 0
+  br i1 %cmp53, label %for.end, label %for.body.lr.ph
+
+for.body.lr.ph:
+  br label %for.body
+
+for.body:
+  %r.057 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add10, %for.body ]
+  %g.056 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add20, %for.body ]
+  %v.055 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
+  %b.054 = phi float [ 0.000000e+00, %for.body.lr.ph ], [ %add30, %for.body ]
+  %add = add i64 %v.055, %offset
+  %mul = mul i64 %add, 3
+  %arrayidx = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %mul
+  %0 = load float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds [512 x float]* @kernel, i64 0, i64 %v.055
+  %1 = load float* %arrayidx2, align 4
+  %mul3 = fmul fast float %0, %1
+  %arrayidx4 = getelementptr inbounds [512 x float]* @kernel2, i64 0, i64 %v.055
+  %2 = load float* %arrayidx4, align 4
+  %mul5 = fmul fast float %mul3, %2
+  %arrayidx6 = getelementptr inbounds [512 x float]* @kernel3, i64 0, i64 %v.055
+  %3 = load float* %arrayidx6, align 4
+  %mul7 = fmul fast float %mul5, %3
+  %arrayidx8 = getelementptr inbounds [512 x float]* @kernel4, i64 0, i64 %v.055
+  %4 = load float* %arrayidx8, align 4
+  %mul9 = fmul fast float %mul7, %4
+  %add10 = fadd fast float %r.057, %mul9
+  %arrayidx.sum = add i64 %mul, 1
+  %arrayidx11 = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum
+  %5 = load float* %arrayidx11, align 4
+  %mul13 = fmul fast float %1, %5
+  %mul15 = fmul fast float %2, %mul13
+  %mul17 = fmul fast float %3, %mul15
+  %mul19 = fmul fast float %4, %mul17
+  %add20 = fadd fast float %g.056, %mul19
+  %arrayidx.sum52 = add i64 %mul, 2
+  %arrayidx21 = getelementptr inbounds [1536 x float]* @src_data, i64 0, i64 %arrayidx.sum52
+  %6 = load float* %arrayidx21, align 4
+  %mul23 = fmul fast float %1, %6
+  %mul25 = fmul fast float %2, %mul23
+  %mul27 = fmul fast float %3, %mul25
+  %mul29 = fmul fast float %4, %mul27
+  %add30 = fadd fast float %b.054, %mul29
+  %inc = add i64 %v.055, 1
+  %exitcond = icmp ne i64 %inc, %size
+  br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge
+
+for.cond.for.end_crit_edge:
+  %add30.lcssa = phi float [ %add30, %for.body ]
+  %add20.lcssa = phi float [ %add20, %for.body ]
+  %add10.lcssa = phi float [ %add10, %for.body ]
+  %phitmp = fptoui float %add10.lcssa to i8
+  %phitmp60 = fptoui float %add20.lcssa to i8
+  %phitmp61 = fptoui float %add30.lcssa to i8
+  br label %for.end
+
+for.end:
+  %r.0.lcssa = phi i8 [ %phitmp, %for.cond.for.end_crit_edge ], [ 0, %entry ]
+  %g.0.lcssa = phi i8 [ %phitmp60, %for.cond.for.end_crit_edge ], [ 0, %entry ]
+  %b.0.lcssa = phi i8 [ %phitmp61, %for.cond.for.end_crit_edge ], [ 0, %entry ]
+  store i8 %r.0.lcssa, i8* @r_, align 1
+  store i8 %g.0.lcssa, i8* @g_, align 1
+  store i8 %b.0.lcssa, i8* @b_, align 1
+  ret void
+}
diff --git a/test/Transforms/LoopVectorize/X86/gcc-examples.ll b/test/Transforms/LoopVectorize/X86/gcc-examples.ll
index d2d0eac..e1113fd 100644
--- a/test/Transforms/LoopVectorize/X86/gcc-examples.ll
+++ b/test/Transforms/LoopVectorize/X86/gcc-examples.ll
@@ -9,13 +9,13 @@ target triple = "x86_64-apple-macosx10.8.0"
 @a = common global [2048 x i32] zeroinitializer, align 16
 
 ; Select VF = 8;
-;CHECK: @example1
+;CHECK-LABEL: @example1(
 ;CHECK: load <4 x i32>
 ;CHECK: add nsw <4 x i32>
 ;CHECK: store <4 x i32>
 ;CHECK: ret void
 
-;UNROLL: @example1
+;UNROLL-LABEL: @example1(
 ;UNROLL: load <4 x i32>
 ;UNROLL: load <4 x i32>
 ;UNROLL: add nsw <4 x i32>
@@ -45,12 +45,12 @@ define void @example1() nounwind uwtable ssp {
 }
 
 ; Select VF=4 because sext <8 x i1> to <8 x i32> is expensive.
-;CHECK: @example10b
+;CHECK-LABEL: @example10b(
 ;CHECK: load <4 x i16>
 ;CHECK: sext <4 x i16>
 ;CHECK: store <4 x i32>
 ;CHECK: ret void
-;UNROLL: @example10b
+;UNROLL-LABEL: @example10b(
 ;UNROLL: load <4 x i16>
 ;UNROLL: load <4 x i16>
 ;UNROLL: store <4 x i32>
diff --git a/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll b/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll
index 30579ce..d6120e7 100644
--- a/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll
+++ b/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
-;CHECK: @foo
+;CHECK-LABEL: @foo(
 ;CHECK-NOT: <4 x i32>
 ;CHECK: ret void
 
diff --git a/test/Transforms/LoopVectorize/X86/parallel-loops.ll b/test/Transforms/LoopVectorize/X86/parallel-loops.ll
index 681a815..7e156a9 100644
--- a/test/Transforms/LoopVectorize/X86/parallel-loops.ll
+++ b/test/Transforms/LoopVectorize/X86/parallel-loops.ll
@@ -12,7 +12,7 @@ target triple = "x86_64-unknown-linux-gnu"
 ;    }
 ;}
 
-;CHECK: @loop
+;CHECK-LABEL: @loop(
 ;CHECK-NOT: <4 x i32>
 define void @loop(i32* nocapture %a, i32* nocapture %b) nounwind uwtable {
 entry:
@@ -42,7 +42,7 @@ for.end:                                          ; preds = %for.body
 ; The same loop with parallel loop metadata added to the loop branch
 ; and the memory instructions.
 
-;CHECK: @parallel_loop
+;CHECK-LABEL: @parallel_loop(
 ;CHECK: <4 x i32>
 define void @parallel_loop(i32* nocapture %a, i32* nocapture %b) nounwind uwtable {
 entry:
@@ -74,7 +74,7 @@ for.end:                                          ; preds = %for.body
 ; The same loop with an illegal parallel loop metadata: the memory
 ; accesses refer to a different loop's identifier.
 
-;CHECK: @mixed_metadata
+;CHECK-LABEL: @mixed_metadata(
 ;CHECK-NOT: <4 x i32>
 
 define void @mixed_metadata(i32* nocapture %a, i32* nocapture %b) nounwind uwtable {
diff --git a/test/Transforms/LoopVectorize/X86/reduction-crash.ll b/test/Transforms/LoopVectorize/X86/reduction-crash.ll
index f580846..3957a55 100644
--- a/test/Transforms/LoopVectorize/X86/reduction-crash.ll
+++ b/test/Transforms/LoopVectorize/X86/reduction-crash.ll
@@ -5,7 +5,7 @@ target triple = "i386-apple-darwin"
 
 ; PR15344
 define void @test1(float* nocapture %arg, i32 %arg1) nounwind {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: preheader
 ; CHECK: insertelement <2 x double> zeroinitializer, double %tmp, i32 0
 ; CHECK: vector.memcheck
diff --git a/test/Transforms/LoopVectorize/X86/small-size.ll b/test/Transforms/LoopVectorize/X86/small-size.ll
index f390b33..14ac417 100644
--- a/test/Transforms/LoopVectorize/X86/small-size.ll
+++ b/test/Transforms/LoopVectorize/X86/small-size.ll
@@ -20,7 +20,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 @dj = common global [1024 x i32] zeroinitializer, align 16
 
 ; We can optimize this test without a tail.
-;CHECK: @example1
+;CHECK-LABEL: @example1(
 ;CHECK: load <4 x i32>
 ;CHECK: add nsw <4 x i32>
 ;CHECK: store <4 x i32>
@@ -47,7 +47,7 @@ define void @example1() optsize {
 }
 
 ; Can't vectorize in 'optsize' mode because we need a tail.
-;CHECK: @example2
+;CHECK-LABEL: @example2(
 ;CHECK-NOT: store <4 x i32>
 ;CHECK: ret void
 define void @example2(i32 %n, i32 %x) optsize {
@@ -92,7 +92,7 @@ define void @example2(i32 %n, i32 %x) optsize {
 }
 
 ; N is unknown, we need a tail. Can't vectorize.
-;CHECK: @example3
+;CHECK-LABEL: @example3(
 ;CHECK-NOT: <4 x i32>
 ;CHECK: ret void
 define void @example3(i32 %n, i32* noalias nocapture %p, i32* noalias nocapture %q) optsize {
@@ -117,7 +117,7 @@ define void @example3(i32 %n, i32* noalias nocapture %p, i32* noalias nocapture
 
 
 ; We can't vectorize this one because we need a runtime ptr check.
-;CHECK: @example23
+;CHECK-LABEL: @example23(
 ;CHECK-NOT: <4 x i32>
 ;CHECK: ret void
 define void @example23(i16* nocapture %src, i32* nocapture %dst) optsize {
@@ -143,7 +143,7 @@ define void @example23(i16* nocapture %src, i32* nocapture %dst) optsize {
 
 
 ; We CAN vectorize this example because the pointers are marked as noalias.
-;CHECK: @example23b
+;CHECK-LABEL: @example23b(
 ;CHECK: <4 x i32>
 ;CHECK: ret void
 define void @example23b(i16* noalias nocapture %src, i32* noalias nocapture %dst) optsize {
diff --git a/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll b/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll
index ef63a14..ea107dc 100644
--- a/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll
+++ b/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll
@@ -2,7 +2,7 @@
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
-;CHECK: @foo
+;CHECK-LABEL: @foo(
 ;CHECK: load <4 x i32>
 ;CHECK-NOT: load <4 x i32>
 ;CHECK: store <4 x i32>
@@ -26,7 +26,7 @@ define i32 @foo(i32* nocapture %A) nounwind uwtable ssp {
   ret i32 undef
 }
 
-;CHECK: @bar
+;CHECK-LABEL: @bar(
 ;CHECK: store <4 x i32>
 ;CHECK: store <4 x i32>
 ;CHECK: ret
diff --git a/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll b/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll
index b66119f..efc93d9 100644
--- a/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll
+++ b/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll
@@ -5,7 +5,7 @@ target triple = "x86_64-apple-macosx10.7.0"
 
 @x = common global [1024 x x86_fp80] zeroinitializer, align 16
 
-;CHECK: @example
+;CHECK-LABEL: @example(
 ;CHECK-NOT: bitcast x86_fp80* {{%[^ ]+}} to <{{[2-9][0-9]*}} x x86_fp80>*
 ;CHECK: store
 ;CHECK: ret void
diff --git a/test/Transforms/LoopVectorize/cast-induction.ll b/test/Transforms/LoopVectorize/cast-induction.ll
index 2aa29ed..255ce9c 100644
--- a/test/Transforms/LoopVectorize/cast-induction.ll
+++ b/test/Transforms/LoopVectorize/cast-induction.ll
@@ -7,7 +7,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 @a = common global [2048 x i32] zeroinitializer, align 16
 
-;CHECK: @example12
+;CHECK-LABEL: @example12(
 ;CHECK: trunc i64
 ;CHECK: store <4 x i32>
 ;CHECK: ret void
diff --git a/test/Transforms/LoopVectorize/cpp-new-array.ll b/test/Transforms/LoopVectorize/cpp-new-array.ll
index da0fb05..c8215a1 100644
--- a/test/Transforms/LoopVectorize/cpp-new-array.ll
+++ b/test/Transforms/LoopVectorize/cpp-new-array.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
-;CHECK: @cpp_new_arrays
+;CHECK-LABEL: @cpp_new_arrays(
 ;CHECK: sext i32
 ;CHECK: load <4 x float>
 ;CHECK: fadd <4 x float>
diff --git a/test/Transforms/LoopVectorize/dbg.value.ll b/test/Transforms/LoopVectorize/dbg.value.ll
index 127d479..b69e72f 100644
--- a/test/Transforms/LoopVectorize/dbg.value.ll
+++ b/test/Transforms/LoopVectorize/dbg.value.ll
@@ -8,7 +8,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 @B = global [1024 x i32] zeroinitializer, align 16
 @C = global [1024 x i32] zeroinitializer, align 16
 
-; CHECK: @test
+; CHECK-LABEL: @test(
 define i32 @test() #0 {
 entry:
   tail call void @llvm.dbg.value(metadata !1, i64 0, metadata !9), !dbg !18
@@ -38,22 +38,22 @@ declare void @llvm.dbg.declare(metadata, metadata) #1
 
 declare void @llvm.dbg.value(metadata, i64, metadata) #1
 
-attributes #0 = { nounwind ssp uwtable "fp-contract-model"="standard" "no-frame-pointer-elim" "no-frame-pointer-elim-non-leaf" "realign-stack" "relocation-model"="pic" "ssp-buffers-size"="8" }
+attributes #0 = { nounwind ssp uwtable "fp-contract-model"="standard" "no-frame-pointer-elim" "no-frame-pointer-elim-non-leaf" "relocation-model"="pic" "ssp-buffers-size"="8" }
 attributes #1 = { nounwind readnone }
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"test", metadata !"/path/to/somewhere", metadata !"clang", i1 true, i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !2, metadata !11, metadata !""}
+!0 = metadata !{i32 786449, metadata !25, i32 4, metadata !"clang", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !2, metadata !11, null, metadata !""}
 !1 = metadata !{i32 0}
 !2 = metadata !{metadata !3}
-!3 = metadata !{i32 786478, i32 0, metadata !4, metadata !"test", metadata !"test", metadata !"test", metadata !4, i32 5, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 ()* @test, null, null, metadata !8, i32 5}
-!4 = metadata !{i32 786473, metadata !"test", metadata !"/path/to/somewhere", null}
+!3 = metadata !{i32 786478, metadata !25, metadata !4, metadata !"test", metadata !"test", metadata !"test", i32 5, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 ()* @test, null, null, metadata !8, i32 5}
+!4 = metadata !{i32 786473, metadata !25}
 !5 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, i32 0}
 !6 = metadata !{metadata !7}
-!7 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}
+!7 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}
 !8 = metadata !{metadata !9}
 !9 = metadata !{i32 786688, metadata !10, metadata !"i", metadata !4, i32 6, metadata !7, i32 0, i32 0}
-!10 = metadata !{i32 786443, metadata !3, i32 6, i32 0, metadata !4, i32 0}
+!10 = metadata !{i32 786443, metadata !25, metadata !3, i32 6, i32 0, i32 0}
 !11 = metadata !{metadata !12, metadata !16, metadata !17}
 !12 = metadata !{i32 786484, i32 0, null, metadata !"A", metadata !"A", metadata !"", metadata !4, i32 1, metadata !13, i32 0, i32 1, [1024 x i32]* @A, null}
 !13 = metadata !{i32 786433, null, metadata !"", null, i32 0, i64 32768, i64 32, i32 0, i32 0, metadata !7, metadata !14, i32 0, i32 0}
@@ -63,5 +63,6 @@ attributes #1 = { nounwind readnone }
 !17 = metadata !{i32 786484, i32 0, null, metadata !"C", metadata !"C", metadata !"", metadata !4, i32 3, metadata !13, i32 0, i32 1, [1024 x i32]* @C, null} 
 !18 = metadata !{i32 6, i32 0, metadata !10, null}
 !19 = metadata !{i32 7, i32 0, metadata !20, null}
-!20 = metadata !{i32 786443, metadata !10, i32 6, i32 0, metadata !4, i32 1}
+!20 = metadata !{i32 786443, metadata !25, metadata !10, i32 6, i32 0, i32 1}
 !24 = metadata !{i32 9, i32 0, metadata !3, null}
+!25 = metadata !{metadata !"test", metadata !"/path/to/somewhere"}
diff --git a/test/Transforms/LoopVectorize/debugloc.ll b/test/Transforms/LoopVectorize/debugloc.ll
new file mode 100644
index 0000000..0a6fc4e
--- /dev/null
+++ b/test/Transforms/LoopVectorize/debugloc.ll
@@ -0,0 +1,92 @@
+; RUN: opt -S < %s -loop-vectorize -force-vector-unroll=1 -force-vector-width=2 | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+; Make sure we are preserving debug info in the vectorized code.
+
+; CHECK: for.body.lr.ph
+; CHECK:   cmp.zero = icmp eq i64 {{.*}}, 0, !dbg !21
+; CHECK: vector.body
+; CHECK:   index {{.*}}, !dbg !21
+; CHECK:   getelementptr inbounds i32* %a, {{.*}}, !dbg !22
+; CHECK:   load <2 x i32>* {{.*}}, !dbg !22
+; CHECK:   add <2 x i32> {{.*}}, !dbg !22
+; CHECK:   add i64 %index, 2, !dbg !21
+; CHECK:   icmp eq i64 %index.next, %end.idx.rnd.down, !dbg !21
+; CHECK: middle.block
+; CHECK:   add <2 x i32> %rdx.vec.exit.phi, %rdx.shuf, !dbg !22
+; CHECK:   extractelement <2 x i32> %bin.rdx, i32 0, !dbg !22
+
+define i32 @f(i32* nocapture %a, i32 %size) #0 {
+entry:
+  tail call void @llvm.dbg.value(metadata !{i32* %a}, i64 0, metadata !13), !dbg !19
+  tail call void @llvm.dbg.value(metadata !{i32 %size}, i64 0, metadata !14), !dbg !19
+  tail call void @llvm.dbg.value(metadata !2, i64 0, metadata !15), !dbg !20
+  tail call void @llvm.dbg.value(metadata !2, i64 0, metadata !16), !dbg !21
+  %cmp4 = icmp eq i32 %size, 0, !dbg !21
+  br i1 %cmp4, label %for.end, label %for.body.lr.ph, !dbg !21
+
+for.body.lr.ph:                                   ; preds = %entry
+  br label %for.body, !dbg !21
+
+for.body:                                         ; preds = %for.body.lr.ph, %for.body
+  %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]
+  %sum.05 = phi i32 [ 0, %for.body.lr.ph ], [ %add, %for.body ]
+  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv, !dbg !22
+  %0 = load i32* %arrayidx, align 4, !dbg !22, !tbaa !23
+  %add = add i32 %0, %sum.05, !dbg !22
+  tail call void @llvm.dbg.value(metadata !{i32 %add.lcssa}, i64 0, metadata !15), !dbg !22
+  %indvars.iv.next = add i64 %indvars.iv, 1, !dbg !21
+  tail call void @llvm.dbg.value(metadata !{null}, i64 0, metadata !16), !dbg !21
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32, !dbg !21
+  %exitcond = icmp ne i32 %lftr.wideiv, %size, !dbg !21
+  br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge, !dbg !21
+
+for.cond.for.end_crit_edge:                       ; preds = %for.body
+  %add.lcssa = phi i32 [ %add, %for.body ]
+  br label %for.end, !dbg !21
+
+for.end:                                          ; preds = %entry, %for.cond.for.end_crit_edge
+  %sum.0.lcssa = phi i32 [ %add.lcssa, %for.cond.for.end_crit_edge ], [ 0, %entry ]
+  ret i32 %sum.0.lcssa, !dbg !26
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata) #1
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.value(metadata, i64, metadata) #1
+
+attributes #0 = { nounwind readonly ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "unsafe-fp-math"="true" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!18}
+
+!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.4 (trunk 185038) (llvm/trunk 185097)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/Volumes/Data/backedup/dev/os/llvm/debug/-] [DW_LANG_C99]
+!1 = metadata !{metadata !"-", metadata !"/Volumes/Data/backedup/dev/os/llvm/debug"}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786478, metadata !5, metadata !6, metadata !"f", metadata !"f", metadata !"", i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32*, i32)* @f, null, null, metadata !12, i32 3} ; [ DW_TAG_subprogram ] [line 3] [def] [f]
+!5 = metadata !{metadata !"<stdin>", metadata !"/Volumes/Data/backedup/dev/os/llvm/debug"}
+!6 = metadata !{i32 786473, metadata !5}          ; [ DW_TAG_file_type ] [/Volumes/Data/backedup/dev/os/llvm/debug/<stdin>]
+!7 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!8 = metadata !{metadata !9, metadata !10, metadata !11}
+!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!10 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int]
+!11 = metadata !{i32 786468, null, null, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] [unsigned int] [line 0, size 32, align 32, offset 0, enc DW_ATE_unsigned]
+!12 = metadata !{metadata !13, metadata !14, metadata !15, metadata !16}
+!13 = metadata !{i32 786689, metadata !4, metadata !"a", metadata !6, i32 16777219, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [a] [line 3]
+!14 = metadata !{i32 786689, metadata !4, metadata !"size", metadata !6, i32 33554435, metadata !11, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [size] [line 3]
+!15 = metadata !{i32 786688, metadata !4, metadata !"sum", metadata !6, i32 4, metadata !11, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [sum] [line 4]
+!16 = metadata !{i32 786688, metadata !17, metadata !"i", metadata !6, i32 5, metadata !11, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 5]
+!17 = metadata !{i32 786443, metadata !5, metadata !4, i32 5, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [/Volumes/Data/backedup/dev/os/llvm/debug/<stdin>]
+!18 = metadata !{i32 2, metadata !"Dwarf Version", i32 3}
+!19 = metadata !{i32 3, i32 0, metadata !4, null}
+!20 = metadata !{i32 4, i32 0, metadata !4, null}
+!21 = metadata !{i32 5, i32 0, metadata !17, null}
+!22 = metadata !{i32 6, i32 0, metadata !17, null}
+!23 = metadata !{metadata !"int", metadata !24}
+!24 = metadata !{metadata !"omnipotent char", metadata !25}
+!25 = metadata !{metadata !"Simple C/C++ TBAA"}
+!26 = metadata !{i32 7, i32 0, metadata !4, null}
diff --git a/test/Transforms/LoopVectorize/flags.ll b/test/Transforms/LoopVectorize/flags.ll
index 656912e..a4ebb42 100644
--- a/test/Transforms/LoopVectorize/flags.ll
+++ b/test/Transforms/LoopVectorize/flags.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
-;CHECK: @flags1
+;CHECK-LABEL: @flags1(
 ;CHECK: load <4 x i32>
 ;CHECK: mul nsw <4 x i32>
 ;CHECK: store <4 x i32>
@@ -28,7 +28,7 @@ define i32 @flags1(i32 %n, i32* nocapture %A) nounwind uwtable ssp {
 }
 
 
-;CHECK: @flags2
+;CHECK-LABEL: @flags2(
 ;CHECK: load <4 x i32>
 ;CHECK: mul <4 x i32>
 ;CHECK: store <4 x i32>
diff --git a/test/Transforms/LoopVectorize/float-reduction.ll b/test/Transforms/LoopVectorize/float-reduction.ll
index 54ca172..c45098d 100644
--- a/test/Transforms/LoopVectorize/float-reduction.ll
+++ b/test/Transforms/LoopVectorize/float-reduction.ll
@@ -2,7 +2,7 @@
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
-;CHECK: @foo
+;CHECK-LABEL: @foo(
 ;CHECK: fadd <4 x float>
 ;CHECK: ret
 define float @foo(float* nocapture %A, i32* nocapture %n) nounwind uwtable readonly ssp {
diff --git a/test/Transforms/LoopVectorize/funcall.ll b/test/Transforms/LoopVectorize/funcall.ll
new file mode 100644
index 0000000..0fb929f
--- /dev/null
+++ b/test/Transforms/LoopVectorize/funcall.ll
@@ -0,0 +1,32 @@
+; RUN: opt -S -loop-vectorize -force-vector-width=2 -force-vector-unroll=1 < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+; Make sure we can vectorize loops with functions to math library functions.
+; They might read the rounding mode but we are only vectorizing loops that
+; contain a limited set of function calls and none of them sets the rounding
+; mode, so vectorizing them is safe.
+
+; CHECK: test
+; CHECK: <2 x double>
+
+define void @test(double* %d, double %t) {
+entry:
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %arrayidx = getelementptr inbounds double* %d, i64 %indvars.iv
+  %0 = load double* %arrayidx, align 8
+  %1 = tail call double @llvm.pow.f64(double %0, double %t)
+  store double %1, double* %arrayidx, align 8
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp ne i32 %lftr.wideiv, 128
+  br i1 %exitcond, label %for.body, label %for.end
+
+for.end:
+  ret void
+}
+
+declare double @llvm.pow.f64(double, double)
diff --git a/test/Transforms/LoopVectorize/gcc-examples.ll b/test/Transforms/LoopVectorize/gcc-examples.ll
index f335557..d8959d4 100644
--- a/test/Transforms/LoopVectorize/gcc-examples.ll
+++ b/test/Transforms/LoopVectorize/gcc-examples.ll
@@ -20,12 +20,12 @@ target triple = "x86_64-apple-macosx10.8.0"
 @dd = common global [1024 x float] zeroinitializer, align 16
 @dj = common global [1024 x i32] zeroinitializer, align 16
 
-;CHECK: @example1
+;CHECK-LABEL: @example1(
 ;CHECK: load <4 x i32>
 ;CHECK: add nsw <4 x i32>
 ;CHECK: store <4 x i32>
 ;CHECK: ret void
-;UNROLL: @example1
+;UNROLL-LABEL: @example1(
 ;UNROLL: load <4 x i32>
 ;UNROLL: load <4 x i32>
 ;UNROLL: load <4 x i32>
@@ -60,10 +60,10 @@ define void @example1() nounwind uwtable ssp {
   ret void
 }
 
-;CHECK: @example2
+;CHECK-LABEL: @example2(
 ;CHECK: store <4 x i32>
 ;CHECK: ret void
-;UNROLL: @example2
+;UNROLL-LABEL: @example2(
 ;UNROLL: store <4 x i32>
 ;UNROLL: store <4 x i32>
 ;UNROLL: store <4 x i32>
@@ -110,10 +110,10 @@ define void @example2(i32 %n, i32 %x) nounwind uwtable ssp {
   ret void
 }
 
-;CHECK: @example3
+;CHECK-LABEL: @example3(
 ;CHECK: <4 x i32>
 ;CHECK: ret void
-;UNROLL: @example3
+;UNROLL-LABEL: @example3(
 ;UNROLL: <4 x i32>
 ;UNROLL: <4 x i32>
 ;UNROLL: <4 x i32>
@@ -139,10 +139,10 @@ define void @example3(i32 %n, i32* noalias nocapture %p, i32* noalias nocapture
   ret void
 }
 
-;CHECK: @example4
+;CHECK-LABEL: @example4(
 ;CHECK: load <4 x i32>
 ;CHECK: ret void
-;UNROLL: @example4
+;UNROLL-LABEL: @example4(
 ;UNROLL: load <4 x i32>
 ;UNROLL: load <4 x i32>
 ;UNROLL: load <4 x i32>
@@ -205,10 +205,10 @@ define void @example4(i32 %n, i32* noalias nocapture %p, i32* noalias nocapture
   ret void
 }
 
-;CHECK: @example8
+;CHECK-LABEL: @example8(
 ;CHECK: store <4 x i32>
 ;CHECK: ret void
-;UNROLL: @example8
+;UNROLL-LABEL: @example8(
 ;UNROLL: store <4 x i32>
 ;UNROLL: store <4 x i32>
 ;UNROLL: store <4 x i32>
@@ -240,7 +240,7 @@ define void @example8(i32 %x) nounwind uwtable ssp {
   ret void
 }
 
-;CHECK: @example9
+;CHECK-LABEL: @example9(
 ;CHECK: phi <4 x i32>
 ;CHECK: ret i32
 define i32 @example9() nounwind uwtable readonly ssp {
@@ -264,7 +264,7 @@ define i32 @example9() nounwind uwtable readonly ssp {
   ret i32 %7
 }
 
-;CHECK: @example10a
+;CHECK-LABEL: @example10a(
 ;CHECK: load <4 x i32>
 ;CHECK: add nsw <4 x i32>
 ;CHECK: load <4 x i16>
@@ -299,7 +299,7 @@ define void @example10a(i16* noalias nocapture %sa, i16* noalias nocapture %sb,
   ret void
 }
 
-;CHECK: @example10b
+;CHECK-LABEL: @example10b(
 ;CHECK: load <4 x i16>
 ;CHECK: sext <4 x i16>
 ;CHECK: store <4 x i32>
@@ -323,7 +323,7 @@ define void @example10b(i16* noalias nocapture %sa, i16* noalias nocapture %sb,
   ret void
 }
 
-;CHECK: @example11
+;CHECK-LABEL: @example11(
 ;CHECK: load i32
 ;CHECK: load i32
 ;CHECK: load i32
@@ -367,7 +367,7 @@ define void @example11() nounwind uwtable ssp {
   ret void
 }
 
-;CHECK: @example12
+;CHECK-LABEL: @example12(
 ;CHECK: trunc i64
 ;CHECK: store <4 x i32>
 ;CHECK: ret void
@@ -389,7 +389,7 @@ define void @example12() nounwind uwtable ssp {
 }
 
 ; Can't vectorize because of reductions.
-;CHECK: @example13
+;CHECK-LABEL: @example13(
 ;CHECK-NOT: <4 x i32>
 ;CHECK: ret void
 define void @example13(i32** nocapture %A, i32** nocapture %B, i32* nocapture %out) nounwind uwtable ssp {
@@ -430,7 +430,7 @@ define void @example13(i32** nocapture %A, i32** nocapture %B, i32* nocapture %o
 }
 
 ; Can vectorize.
-;CHECK: @example14
+;CHECK-LABEL: @example14(
 ;CHECK: <4 x i32>
 ;CHECK: ret void
 define void @example14(i32** nocapture %in, i32** nocapture %coeff, i32* nocapture %out) nounwind uwtable ssp {
@@ -575,7 +575,7 @@ define void @example14(i32** nocapture %in, i32** nocapture %coeff, i32* nocaptu
   ret void
 }
 
-;CHECK: @example21
+;CHECK-LABEL: @example21(
 ;CHECK: load <4 x i32>
 ;CHECK: shufflevector {{.*}} <i32 3, i32 2, i32 1, i32 0>
 ;CHECK: ret i32
@@ -603,7 +603,7 @@ define i32 @example21(i32* nocapture %b, i32 %n) nounwind uwtable readonly ssp {
   ret i32 %a.0.lcssa
 }
 
-;CHECK: @example23
+;CHECK-LABEL: @example23(
 ;CHECK: <4 x i32>
 ;CHECK: ret void
 define void @example23(i16* nocapture %src, i32* nocapture %dst) nounwind uwtable ssp {
@@ -627,7 +627,7 @@ define void @example23(i16* nocapture %src, i32* nocapture %dst) nounwind uwtabl
   ret void
 }
 
-;CHECK: @example24
+;CHECK-LABEL: @example24(
 ;CHECK: shufflevector <4 x i16>
 ;CHECK: ret void
 define void @example24(i16 signext %x, i16 signext %y) nounwind uwtable ssp {
@@ -653,7 +653,7 @@ define void @example24(i16 signext %x, i16 signext %y) nounwind uwtable ssp {
   ret void
 }
 
-;CHECK: @example25
+;CHECK-LABEL: @example25(
 ;CHECK: and <4 x i1>
 ;CHECK: zext <4 x i1>
 ;CHECK: ret void
diff --git a/test/Transforms/LoopVectorize/global_alias.ll b/test/Transforms/LoopVectorize/global_alias.ll
index 121da8b..ae72d3c 100644
--- a/test/Transforms/LoopVectorize/global_alias.ll
+++ b/test/Transforms/LoopVectorize/global_alias.ll
@@ -22,7 +22,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ;     Foo.A[i] = Foo.B[i] + a;
 ;   return Foo.A[a];
 ; }
-; CHECK: define i32 @noAlias01
+; CHECK-LABEL: define i32 @noAlias01(
 ; CHECK: add nsw <4 x i32>
 ; CHECK: ret
 
@@ -70,7 +70,7 @@ for.end:                                          ; preds = %for.cond
 ;     Foo.A[i] = Foo.B[i+10] + a;
 ;   return Foo.A[a];
 ; }
-; CHECK: define i32 @noAlias02
+; CHECK-LABEL: define i32 @noAlias02(
 ; CHECK: add nsw <4 x i32>
 ; CHECK: ret
 
@@ -119,7 +119,7 @@ for.end:                                          ; preds = %for.cond
 ;     Foo.A[i+10] = Foo.B[i] + a;
 ;   return Foo.A[a];
 ; }
-; CHECK: define i32 @noAlias03
+; CHECK-LABEL: define i32 @noAlias03(
 ; CHECK: add nsw <4 x i32>
 ; CHECK: ret
 
@@ -168,7 +168,7 @@ for.end:                                          ; preds = %for.cond
 ;     *(PA+i) = *(PB+i) + a;
 ;   return *(PA+a);
 ; }
-; CHECK: define i32 @noAlias04
+; CHECK-LABEL: define i32 @noAlias04(
 ; CHECK-NOT: add nsw <4 x i32>
 ; CHECK: ret
 ;
@@ -222,7 +222,7 @@ for.end:                                          ; preds = %for.cond
 ;     Bar.A[N][i] = Bar.B[N][i] + a;
 ;   return Bar.A[N][a];
 ; }
-; CHECK: define i32 @noAlias05
+; CHECK-LABEL: define i32 @noAlias05(
 ; CHECK: add nsw <4 x i32>
 ; CHECK: ret
 
@@ -278,7 +278,7 @@ for.end:                                          ; preds = %for.cond
 ;     Bar.A[N][i] = Bar.A[N+1][i] + a;
 ;   return Bar.A[N][a];
 ; }
-; CHECK: define i32 @noAlias06
+; CHECK-LABEL: define i32 @noAlias06(
 ; CHECK: add nsw <4 x i32>
 ; CHECK: ret
 
@@ -335,7 +335,7 @@ for.end:                                          ; preds = %for.cond
 ;     Foo.A[SIZE-i-1] = Foo.B[SIZE-i-1] + a;
 ;   return Foo.A[a];
 ; }
-; CHECK: define i32 @noAlias07
+; CHECK-LABEL: define i32 @noAlias07(
 ; CHECK: sub nsw <4 x i32>
 ; CHECK: ret
 
@@ -387,7 +387,7 @@ for.end:                                          ; preds = %for.cond
 ;     Foo.A[SIZE-i-1] = Foo.B[SIZE-i-10] + a;
 ;   return Foo.A[a];
 ; }
-; CHECK: define i32 @noAlias08
+; CHECK-LABEL: define i32 @noAlias08(
 ; CHECK: sub nsw <4 x i32>
 ; CHECK: ret
 
@@ -439,7 +439,7 @@ for.end:                                          ; preds = %for.cond
 ;     Foo.A[SIZE-i-10] = Foo.B[SIZE-i-1] + a;
 ;   return Foo.A[a];
 ; }
-; CHECK: define i32 @noAlias09
+; CHECK-LABEL: define i32 @noAlias09(
 ; CHECK: sub nsw <4 x i32>
 ; CHECK: ret
 
@@ -491,7 +491,7 @@ for.end:                                          ; preds = %for.cond
 ;     *(PA+SIZE-i-1) = *(PB+SIZE-i-1) + a;
 ;   return *(PA+a);
 ; }
-; CHECK: define i32 @noAlias10
+; CHECK-LABEL: define i32 @noAlias10(
 ; CHECK-NOT: sub nsw <4 x i32>
 ; CHECK: ret
 ;
@@ -551,7 +551,7 @@ for.end:                                          ; preds = %for.cond
 ;     Bar.A[N][SIZE-i-1] = Bar.B[N][SIZE-i-1] + a;
 ;   return Bar.A[N][a];
 ; }
-; CHECK: define i32 @noAlias11
+; CHECK-LABEL: define i32 @noAlias11(
 ; CHECK: sub nsw <4 x i32>
 ; CHECK: ret
 
@@ -611,7 +611,7 @@ for.end:                                          ; preds = %for.cond
 ;     Bar.A[N][SIZE-i-1] = Bar.A[N+1][SIZE-i-1] + a;
 ;   return Bar.A[N][a];
 ; }
-; CHECK: define i32 @noAlias12
+; CHECK-LABEL: define i32 @noAlias12(
 ; CHECK: sub nsw <4 x i32>
 ; CHECK: ret
 
@@ -672,7 +672,7 @@ for.end:                                          ; preds = %for.cond
 ;     Foo.A[i] = Foo.A[i+4] + a;
 ;   return Foo.A[a];
 ; }
-; CHECK: define i32 @noAlias13
+; CHECK-LABEL: define i32 @noAlias13(
 ; CHECK: add nsw <4 x i32>
 ; CHECK: ret
 
@@ -721,7 +721,7 @@ for.end:                                          ; preds = %for.cond
 ;     Foo.A[SIZE-i-1] = Foo.A[SIZE-i-5] + a;
 ;   return Foo.A[a];
 ; }
-; CHECK: define i32 @noAlias14
+; CHECK-LABEL: define i32 @noAlias14(
 ; CHECK: sub nsw <4 x i32>
 ; CHECK: ret
 
@@ -777,7 +777,7 @@ for.end:                                          ; preds = %for.cond
 ;     Foo.A[i] = Foo.B[SIZE-i-1] + a;
 ;   return Foo.A[a];
 ; }
-; CHECK: define i32 @mayAlias01
+; CHECK-LABEL: define i32 @mayAlias01(
 ; CHECK-NOT: add nsw <4 x i32>
 ; CHECK: ret
 
@@ -827,7 +827,7 @@ for.end:                                          ; preds = %for.cond
 ;     Foo.A[SIZE-i-1] = Foo.B[i] + a;
 ;   return Foo.A[a];
 ; }
-; CHECK: define i32 @mayAlias02
+; CHECK-LABEL: define i32 @mayAlias02(
 ; CHECK-NOT: add nsw <4 x i32>
 ; CHECK: ret
 
@@ -877,7 +877,7 @@ for.end:                                          ; preds = %for.cond
 ;     *(PA+i) = *(PB+SIZE-i-1) + a;
 ;   return *(PA+a);
 ; }
-; CHECK: define i32 @mayAlias03
+; CHECK-LABEL: define i32 @mayAlias03(
 ; CHECK-NOT: add nsw <4 x i32>
 ; CHECK: ret
 
@@ -934,7 +934,7 @@ for.end:                                          ; preds = %for.cond
 ;     Foo.A[i+10] = Foo.B[SIZE-i-1] + a;
 ;   return Foo.A[a];
 ; }
-; CHECK: define i32 @mustAlias01
+; CHECK-LABEL: define i32 @mustAlias01(
 ; CHECK-NOT: add nsw <4 x i32>
 ; CHECK: ret
 
@@ -984,7 +984,7 @@ for.end:                                          ; preds = %for.cond
 ;     Foo.A[i] = Foo.B[SIZE-i-10] + a;
 ;   return Foo.A[a];
 ; }
-; CHECK: define i32 @mustAlias02
+; CHECK-LABEL: define i32 @mustAlias02(
 ; CHECK-NOT: add nsw <4 x i32>
 ; CHECK: ret
 
@@ -1033,7 +1033,7 @@ for.end:                                          ; preds = %for.cond
 ;     Foo.A[i+10] = Foo.B[SIZE-i-10] + a;
 ;   return Foo.A[a];
 ; }
-; CHECK: define i32 @mustAlias03
+; CHECK-LABEL: define i32 @mustAlias03(
 ; CHECK-NOT: add nsw <4 x i32>
 ; CHECK: ret
 
diff --git a/test/Transforms/LoopVectorize/if-conversion-edgemasks.ll b/test/Transforms/LoopVectorize/if-conversion-edgemasks.ll
new file mode 100644
index 0000000..27c274d
--- /dev/null
+++ b/test/Transforms/LoopVectorize/if-conversion-edgemasks.ll
@@ -0,0 +1,243 @@
+; RUN: opt -S -loop-vectorize < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.9.0"
+
+@a = global i32* null, align 8
+@b = global i32* null, align 8
+@c = global i32* null, align 8
+
+; Don't create an exponetial IR for the edge masks needed when if-converting
+; this code.
+
+; PR16472
+
+; CHECK-NOT: %6000000 =
+
+define void @_Z3fn4i(i32 %p1) {
+entry:
+  %cmp88 = icmp sgt i32 %p1, 0
+  br i1 %cmp88, label %for.body.lr.ph, label %for.end
+
+for.body.lr.ph:
+  %0 = load i32** @b, align 8  %1 = load i32** @a, align 8  %2 = load i32** @c, align 8  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %_ZL3fn3ii.exit58 ]
+  %arrayidx = getelementptr inbounds i32* %0, i64 %indvars.iv
+  %3 = load i32* %arrayidx, align 4  %4 = trunc i64 %indvars.iv to i32
+  %and.i = and i32 %4, 1
+  %tobool.i.i = icmp eq i32 %and.i, 0
+  br i1 %tobool.i.i, label %if.end.i, label %if.then.i
+
+if.then.i:
+  %and.i.i = lshr i32 %3, 2
+  %and.lobit.i.i = and i32 %and.i.i, 1
+  %5 = xor i32 %and.lobit.i.i, 1
+  %or.i.i = or i32 %5, %3
+  %cmp.i = icmp sgt i32 %or.i.i, 0
+  %conv.i = zext i1 %cmp.i to i32
+  br label %if.end.i
+
+if.end.i:
+  %tobool.i87 = phi i1 [ true, %if.then.i ], [ false, %for.body ]
+  %p1.addr.0.i = phi i32 [ %conv.i, %if.then.i ], [ %3, %for.body ]
+  %6 = trunc i64 %indvars.iv to i32
+  %and1.i = and i32 %6, 7
+  %tobool2.i = icmp eq i32 %and1.i, 0
+  br i1 %tobool2.i, label %if.end7.i, label %if.then3.i
+
+if.then3.i:
+  %p1.addr.0.lobit.i = lshr i32 %p1.addr.0.i, 31
+  %and6.i = and i32 %p1.addr.0.i, 1
+  %or.i = or i32 %p1.addr.0.lobit.i, %and6.i
+  br label %if.end7.i
+
+if.end7.i:
+  %p1.addr.1.i = phi i32 [ %or.i, %if.then3.i ], [ %p1.addr.0.i, %if.end.i ]
+  br i1 %tobool.i87, label %if.then10.i, label %if.end13.i
+
+if.then10.i:
+  %cmp11.i = icmp sgt i32 %p1.addr.1.i, 0
+  %conv12.i = zext i1 %cmp11.i to i32
+  br label %if.end13.i
+
+if.end13.i:
+  %p1.addr.2.i = phi i32 [ %conv12.i, %if.then10.i ], [ %p1.addr.1.i, %if.end7.i ]
+  br i1 %tobool.i.i, label %_Z3fn2iii.exit, label %if.then16.i
+
+if.then16.i:
+  %and17.i = lshr i32 %p1.addr.2.i, 3
+  %and17.lobit.i = and i32 %and17.i, 1
+  br label %_Z3fn2iii.exit
+
+_Z3fn2iii.exit:
+  %p1.addr.3.i = phi i32 [ %and17.lobit.i, %if.then16.i ], [ %p1.addr.2.i, %if.end13.i ]
+  %7 = trunc i64 %indvars.iv to i32
+  %shr.i = ashr i32 %7, 1
+  %and.i18.i = and i32 %shr.i, 1
+  %tobool.i19.i = icmp ne i32 %and.i18.i, 0
+  br i1 %tobool.i19.i, label %if.then.i20.i, label %if.end.i.i
+
+if.then.i20.i:
+  %cmp.i.i = icmp sgt i32 %p1.addr.3.i, 0
+  %conv.i.i = zext i1 %cmp.i.i to i32
+  br label %if.end.i.i
+
+if.end.i.i:
+  %p1.addr.0.i21.i = phi i32 [ %conv.i.i, %if.then.i20.i ], [ %p1.addr.3.i, %_Z3fn2iii.exit ]
+  %and1.i.i = and i32 %shr.i, 7
+  %tobool2.i.i = icmp eq i32 %and1.i.i, 0
+  br i1 %tobool2.i.i, label %if.end7.i.i, label %if.then3.i.i
+
+if.then3.i.i:
+  %p1.addr.0.lobit.i.i = lshr i32 %p1.addr.0.i21.i, 31
+  %and6.i.i = and i32 %p1.addr.0.i21.i, 1
+  %or.i22.i = or i32 %p1.addr.0.lobit.i.i, %and6.i.i
+  br label %if.end7.i.i
+
+if.end7.i.i:
+  %p1.addr.1.i.i = phi i32 [ %or.i22.i, %if.then3.i.i ], [ %p1.addr.0.i21.i, %if.end.i.i ]
+  br i1 %tobool.i19.i, label %if.then10.i.i, label %if.end13.i.i
+
+if.then10.i.i:
+  %cmp11.i.i = icmp sgt i32 %p1.addr.1.i.i, 0
+  %conv12.i.i = zext i1 %cmp11.i.i to i32
+  br label %if.end13.i.i
+
+if.end13.i.i:
+  %p1.addr.2.i.i = phi i32 [ %conv12.i.i, %if.then10.i.i ], [ %p1.addr.1.i.i, %if.end7.i.i ]
+  %and14.i.i = and i32 %shr.i, 5
+  %tobool15.i.i = icmp eq i32 %and14.i.i, 0
+  br i1 %tobool15.i.i, label %_Z3fn2iii.exit.i, label %if.then16.i.i
+
+if.then16.i.i:
+  %and17.i.i = lshr i32 %p1.addr.2.i.i, 3
+  %and17.lobit.i.i = and i32 %and17.i.i, 1
+  br label %_Z3fn2iii.exit.i
+
+_Z3fn2iii.exit.i:
+  %p1.addr.3.i.i = phi i32 [ %and17.lobit.i.i, %if.then16.i.i ], [ %p1.addr.2.i.i, %if.end13.i.i ]
+  %8 = trunc i64 %indvars.iv to i32
+  %tobool.i11.i = icmp eq i32 %8, 0
+  br i1 %tobool.i11.i, label %_ZL3fn3ii.exit, label %if.then.i15.i
+
+if.then.i15.i:
+  %and.i12.i = lshr i32 %p1.addr.3.i.i, 2
+  %and.lobit.i13.i = and i32 %and.i12.i, 1
+  %9 = xor i32 %and.lobit.i13.i, 1
+  %or.i14.i = or i32 %9, %p1.addr.3.i.i
+  br label %_ZL3fn3ii.exit
+
+_ZL3fn3ii.exit:
+  %p1.addr.0.i16.i = phi i32 [ %or.i14.i, %if.then.i15.i ], [ %p1.addr.3.i.i, %_Z3fn2iii.exit.i ]
+  %arrayidx2 = getelementptr inbounds i32* %1, i64 %indvars.iv
+  store i32 %p1.addr.0.i16.i, i32* %arrayidx2, align 4  %arrayidx4 = getelementptr inbounds i32* %0, i64 %indvars.iv
+  %10 = load i32* %arrayidx4, align 4  br i1 %tobool.i.i, label %_Z3fn1ii.exit.i26, label %if.then.i.i21
+
+if.then.i.i21:
+  %and.i.i18 = lshr i32 %10, 2
+  %and.lobit.i.i19 = and i32 %and.i.i18, 1
+  %11 = xor i32 %and.lobit.i.i19, 1
+  %or.i.i20 = or i32 %11, %10
+  br label %_Z3fn1ii.exit.i26
+
+_Z3fn1ii.exit.i26:
+  %p1.addr.0.i.i22 = phi i32 [ %or.i.i20, %if.then.i.i21 ], [ %10, %_ZL3fn3ii.exit ]
+  br i1 %tobool.i87, label %if.then.i63, label %if.end.i67
+
+if.then.i63:
+  %cmp.i61 = icmp sgt i32 %p1.addr.0.i.i22, 0
+  %conv.i62 = zext i1 %cmp.i61 to i32
+  br label %if.end.i67
+
+if.end.i67:
+  %p1.addr.0.i64 = phi i32 [ %conv.i62, %if.then.i63 ], [ %p1.addr.0.i.i22, %_Z3fn1ii.exit.i26 ]
+  br i1 %tobool2.i, label %if.end7.i73, label %if.then3.i71
+
+if.then3.i71:
+  %p1.addr.0.lobit.i68 = lshr i32 %p1.addr.0.i64, 31
+  %and6.i69 = and i32 %p1.addr.0.i64, 1
+  %or.i70 = or i32 %p1.addr.0.lobit.i68, %and6.i69
+  br label %if.end7.i73
+
+if.end7.i73:
+  %p1.addr.1.i72 = phi i32 [ %or.i70, %if.then3.i71 ], [ %p1.addr.0.i64, %if.end.i67 ]
+  br i1 %tobool.i87, label %if.then10.i76, label %if.end13.i80
+
+if.then10.i76:
+  %cmp11.i74 = icmp sgt i32 %p1.addr.1.i72, 0
+  %conv12.i75 = zext i1 %cmp11.i74 to i32
+  br label %if.end13.i80
+
+if.end13.i80:
+  %p1.addr.2.i77 = phi i32 [ %conv12.i75, %if.then10.i76 ], [ %p1.addr.1.i72, %if.end7.i73 ]
+  br i1 %tobool.i.i, label %_Z3fn2iii.exit85, label %if.then16.i83
+
+if.then16.i83:
+  %and17.i81 = lshr i32 %p1.addr.2.i77, 3
+  %and17.lobit.i82 = and i32 %and17.i81, 1
+  br label %_Z3fn2iii.exit85
+
+_Z3fn2iii.exit85:
+  %p1.addr.3.i84 = phi i32 [ %and17.lobit.i82, %if.then16.i83 ], [ %p1.addr.2.i77, %if.end13.i80 ]
+  br i1 %tobool.i19.i, label %if.then.i20.i29, label %if.end.i.i33
+
+if.then.i20.i29:
+  %cmp.i.i27 = icmp sgt i32 %p1.addr.3.i84, 0
+  %conv.i.i28 = zext i1 %cmp.i.i27 to i32
+  br label %if.end.i.i33
+
+if.end.i.i33:
+  %p1.addr.0.i21.i30 = phi i32 [ %conv.i.i28, %if.then.i20.i29 ], [ %p1.addr.3.i84, %_Z3fn2iii.exit85 ]
+  br i1 %tobool2.i.i, label %if.end7.i.i39, label %if.then3.i.i37
+
+if.then3.i.i37:
+  %p1.addr.0.lobit.i.i34 = lshr i32 %p1.addr.0.i21.i30, 31
+  %and6.i.i35 = and i32 %p1.addr.0.i21.i30, 1
+  %or.i22.i36 = or i32 %p1.addr.0.lobit.i.i34, %and6.i.i35
+  br label %if.end7.i.i39
+
+if.end7.i.i39:
+  %p1.addr.1.i.i38 = phi i32 [ %or.i22.i36, %if.then3.i.i37 ], [ %p1.addr.0.i21.i30, %if.end.i.i33 ]
+  br i1 %tobool.i19.i, label %if.then10.i.i42, label %if.end13.i.i46
+
+if.then10.i.i42:
+  %cmp11.i.i40 = icmp sgt i32 %p1.addr.1.i.i38, 0
+  %conv12.i.i41 = zext i1 %cmp11.i.i40 to i32
+  br label %if.end13.i.i46
+
+if.end13.i.i46:
+  %p1.addr.2.i.i43 = phi i32 [ %conv12.i.i41, %if.then10.i.i42 ], [ %p1.addr.1.i.i38, %if.end7.i.i39 ]
+  br i1 %tobool15.i.i, label %_Z3fn2iii.exit.i52, label %if.then16.i.i49
+
+if.then16.i.i49:
+  %and17.i.i47 = lshr i32 %p1.addr.2.i.i43, 3
+  %and17.lobit.i.i48 = and i32 %and17.i.i47, 1
+  br label %_Z3fn2iii.exit.i52
+
+_Z3fn2iii.exit.i52:
+  %p1.addr.3.i.i50 = phi i32 [ %and17.lobit.i.i48, %if.then16.i.i49 ], [ %p1.addr.2.i.i43, %if.end13.i.i46 ]
+  br i1 %tobool.i11.i, label %_ZL3fn3ii.exit58, label %if.then.i15.i56
+
+if.then.i15.i56:
+  %and.i12.i53 = lshr i32 %p1.addr.3.i.i50, 2
+  %and.lobit.i13.i54 = and i32 %and.i12.i53, 1
+  %12 = xor i32 %and.lobit.i13.i54, 1
+  %or.i14.i55 = or i32 %12, %p1.addr.3.i.i50
+  br label %_ZL3fn3ii.exit58
+
+_ZL3fn3ii.exit58:
+  %p1.addr.0.i16.i57 = phi i32 [ %or.i14.i55, %if.then.i15.i56 ], [ %p1.addr.3.i.i50, %_Z3fn2iii.exit.i52 ]
+  %arrayidx7 = getelementptr inbounds i32* %2, i64 %indvars.iv
+  store i32 %p1.addr.0.i16.i57, i32* %arrayidx7, align 4  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp ne i32 %lftr.wideiv, %p1
+  br i1 %exitcond, label %for.body, label %for.cond.for.end_crit_edge
+
+for.cond.for.end_crit_edge:
+  br label %for.end
+
+for.end:
+  ret void
+}
diff --git a/test/Transforms/LoopVectorize/if-conversion-nest.ll b/test/Transforms/LoopVectorize/if-conversion-nest.ll
index f44862a..92cb06e 100644
--- a/test/Transforms/LoopVectorize/if-conversion-nest.ll
+++ b/test/Transforms/LoopVectorize/if-conversion-nest.ll
@@ -2,7 +2,7 @@
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 
-;CHECK: @foo
+;CHECK-LABEL: @foo(
 ;CHECK: icmp sgt
 ;CHECK: icmp sgt
 ;CHECK: icmp slt
diff --git a/test/Transforms/LoopVectorize/if-conversion-reduction.ll b/test/Transforms/LoopVectorize/if-conversion-reduction.ll
index 3a2d82e..8cb703c 100644
--- a/test/Transforms/LoopVectorize/if-conversion-reduction.ll
+++ b/test/Transforms/LoopVectorize/if-conversion-reduction.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.9.0"
 
-;CHECK: @reduction_func
+;CHECK-LABEL: @reduction_func(
 ;CHECK-NOT: load <4 x i32>
 ;CHECK: ret i32
 define i32 @reduction_func(i32* nocapture %A, i32 %n) nounwind uwtable readonly ssp {
diff --git a/test/Transforms/LoopVectorize/if-conversion.ll b/test/Transforms/LoopVectorize/if-conversion.ll
index 6e7c03a..88e56b2 100644
--- a/test/Transforms/LoopVectorize/if-conversion.ll
+++ b/test/Transforms/LoopVectorize/if-conversion.ll
@@ -17,7 +17,7 @@ target triple = "x86_64-apple-macosx10.9.0"
 ;  }
 ;}
 
-;CHECK: @function0
+;CHECK-LABEL: @function0(
 ;CHECK: load <4 x i32>
 ;CHECK: icmp sgt <4 x i32>
 ;CHECK: mul <4 x i32>
@@ -70,7 +70,7 @@ for.end:
 ;   return sum;
 ; }
 
-;CHECK: @reduction_func
+;CHECK-LABEL: @reduction_func(
 ;CHECK: load <4 x i32>
 ;CHECK: icmp sgt <4 x i32>
 ;CHECK: add <4 x i32>
diff --git a/test/Transforms/LoopVectorize/increment.ll b/test/Transforms/LoopVectorize/increment.ll
index 3fa6b19..d35bd58 100644
--- a/test/Transforms/LoopVectorize/increment.ll
+++ b/test/Transforms/LoopVectorize/increment.ll
@@ -9,7 +9,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 ;  for (i=0; i<n; i++){
 ;    a[i] += i;
 ;  }
-;CHECK: @inc
+;CHECK-LABEL: @inc(
 ;CHECK: load <4 x i32>
 ;CHECK: add nsw <4 x i32>
 ;CHECK: store <4 x i32>
@@ -39,7 +39,7 @@ define void @inc(i32 %n) nounwind uwtable noinline ssp {
 ;  for (i = 0; i < n; ++i) {
 ;    A[B[i]]++;
 ;
-;CHECK: @histogram
+;CHECK-LABEL: @histogram(
 ;CHECK-NOT: <4 x i32>
 ;CHECK: ret i32
 define i32 @histogram(i32* nocapture noalias %A, i32* nocapture noalias %B, i32 %n) nounwind uwtable ssp {
diff --git a/test/Transforms/LoopVectorize/induction_plus.ll b/test/Transforms/LoopVectorize/induction_plus.ll
index 96595cd..6141c39 100644
--- a/test/Transforms/LoopVectorize/induction_plus.ll
+++ b/test/Transforms/LoopVectorize/induction_plus.ll
@@ -5,7 +5,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 @array = common global [1024 x i32] zeroinitializer, align 16
 
-;CHECK: @array_at_plus_one
+;CHECK-LABEL: @array_at_plus_one(
 ;CHECK: trunc i64
 ;CHECK: add i64 %index, 12
 ;CHECK: ret i32
diff --git a/test/Transforms/LoopVectorize/intrinsic.ll b/test/Transforms/LoopVectorize/intrinsic.ll
index defbb5b..95b53b7 100644
--- a/test/Transforms/LoopVectorize/intrinsic.ll
+++ b/test/Transforms/LoopVectorize/intrinsic.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
-;CHECK: @sqrt_f32
+;CHECK-LABEL: @sqrt_f32(
 ;CHECK: llvm.sqrt.v4f32
 ;CHECK: ret void
 define void @sqrt_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
@@ -29,7 +29,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.sqrt.f32(float) nounwind readnone
 
-;CHECK: @sqrt_f64
+;CHECK-LABEL: @sqrt_f64(
 ;CHECK: llvm.sqrt.v4f64
 ;CHECK: ret void
 define void @sqrt_f64(i32 %n, double* noalias %y, double* noalias %x) nounwind uwtable {
@@ -55,7 +55,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.sqrt.f64(double) nounwind readnone
 
-;CHECK: @sin_f32
+;CHECK-LABEL: @sin_f32(
 ;CHECK: llvm.sin.v4f32
 ;CHECK: ret void
 define void @sin_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
@@ -81,7 +81,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.sin.f32(float) nounwind readnone
 
-;CHECK: @sin_f64
+;CHECK-LABEL: @sin_f64(
 ;CHECK: llvm.sin.v4f64
 ;CHECK: ret void
 define void @sin_f64(i32 %n, double* noalias %y, double* noalias %x) nounwind uwtable {
@@ -107,7 +107,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.sin.f64(double) nounwind readnone
 
-;CHECK: @cos_f32
+;CHECK-LABEL: @cos_f32(
 ;CHECK: llvm.cos.v4f32
 ;CHECK: ret void
 define void @cos_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
@@ -133,7 +133,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.cos.f32(float) nounwind readnone
 
-;CHECK: @cos_f64
+;CHECK-LABEL: @cos_f64(
 ;CHECK: llvm.cos.v4f64
 ;CHECK: ret void
 define void @cos_f64(i32 %n, double* noalias %y, double* noalias %x) nounwind uwtable {
@@ -159,7 +159,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.cos.f64(double) nounwind readnone
 
-;CHECK: @exp_f32
+;CHECK-LABEL: @exp_f32(
 ;CHECK: llvm.exp.v4f32
 ;CHECK: ret void
 define void @exp_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
@@ -185,7 +185,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.exp.f32(float) nounwind readnone
 
-;CHECK: @exp_f64
+;CHECK-LABEL: @exp_f64(
 ;CHECK: llvm.exp.v4f64
 ;CHECK: ret void
 define void @exp_f64(i32 %n, double* noalias %y, double* noalias %x) nounwind uwtable {
@@ -211,7 +211,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.exp.f64(double) nounwind readnone
 
-;CHECK: @exp2_f32
+;CHECK-LABEL: @exp2_f32(
 ;CHECK: llvm.exp2.v4f32
 ;CHECK: ret void
 define void @exp2_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
@@ -237,7 +237,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.exp2.f32(float) nounwind readnone
 
-;CHECK: @exp2_f64
+;CHECK-LABEL: @exp2_f64(
 ;CHECK: llvm.exp2.v4f64
 ;CHECK: ret void
 define void @exp2_f64(i32 %n, double* noalias %y, double* noalias %x) nounwind uwtable {
@@ -263,7 +263,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.exp2.f64(double) nounwind readnone
 
-;CHECK: @log_f32
+;CHECK-LABEL: @log_f32(
 ;CHECK: llvm.log.v4f32
 ;CHECK: ret void
 define void @log_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
@@ -289,7 +289,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.log.f32(float) nounwind readnone
 
-;CHECK: @log_f64
+;CHECK-LABEL: @log_f64(
 ;CHECK: llvm.log.v4f64
 ;CHECK: ret void
 define void @log_f64(i32 %n, double* noalias %y, double* noalias %x) nounwind uwtable {
@@ -315,7 +315,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.log.f64(double) nounwind readnone
 
-;CHECK: @log10_f32
+;CHECK-LABEL: @log10_f32(
 ;CHECK: llvm.log10.v4f32
 ;CHECK: ret void
 define void @log10_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
@@ -341,7 +341,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.log10.f32(float) nounwind readnone
 
-;CHECK: @log10_f64
+;CHECK-LABEL: @log10_f64(
 ;CHECK: llvm.log10.v4f64
 ;CHECK: ret void
 define void @log10_f64(i32 %n, double* noalias %y, double* noalias %x) nounwind uwtable {
@@ -367,7 +367,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.log10.f64(double) nounwind readnone
 
-;CHECK: @log2_f32
+;CHECK-LABEL: @log2_f32(
 ;CHECK: llvm.log2.v4f32
 ;CHECK: ret void
 define void @log2_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
@@ -393,7 +393,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.log2.f32(float) nounwind readnone
 
-;CHECK: @log2_f64
+;CHECK-LABEL: @log2_f64(
 ;CHECK: llvm.log2.v4f64
 ;CHECK: ret void
 define void @log2_f64(i32 %n, double* noalias %y, double* noalias %x) nounwind uwtable {
@@ -419,7 +419,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.log2.f64(double) nounwind readnone
 
-;CHECK: @fabs_f32
+;CHECK-LABEL: @fabs_f32(
 ;CHECK: llvm.fabs.v4f32
 ;CHECK: ret void
 define void @fabs_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
@@ -468,7 +468,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.fabs(double) nounwind readnone
 
-;CHECK: @floor_f32
+;CHECK-LABEL: @floor_f32(
 ;CHECK: llvm.floor.v4f32
 ;CHECK: ret void
 define void @floor_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
@@ -494,7 +494,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.floor.f32(float) nounwind readnone
 
-;CHECK: @floor_f64
+;CHECK-LABEL: @floor_f64(
 ;CHECK: llvm.floor.v4f64
 ;CHECK: ret void
 define void @floor_f64(i32 %n, double* noalias %y, double* noalias %x) nounwind uwtable {
@@ -520,7 +520,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.floor.f64(double) nounwind readnone
 
-;CHECK: @ceil_f32
+;CHECK-LABEL: @ceil_f32(
 ;CHECK: llvm.ceil.v4f32
 ;CHECK: ret void
 define void @ceil_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
@@ -546,7 +546,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.ceil.f32(float) nounwind readnone
 
-;CHECK: @ceil_f64
+;CHECK-LABEL: @ceil_f64(
 ;CHECK: llvm.ceil.v4f64
 ;CHECK: ret void
 define void @ceil_f64(i32 %n, double* noalias %y, double* noalias %x) nounwind uwtable {
@@ -572,7 +572,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.ceil.f64(double) nounwind readnone
 
-;CHECK: @trunc_f32
+;CHECK-LABEL: @trunc_f32(
 ;CHECK: llvm.trunc.v4f32
 ;CHECK: ret void
 define void @trunc_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
@@ -598,7 +598,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.trunc.f32(float) nounwind readnone
 
-;CHECK: @trunc_f64
+;CHECK-LABEL: @trunc_f64(
 ;CHECK: llvm.trunc.v4f64
 ;CHECK: ret void
 define void @trunc_f64(i32 %n, double* noalias %y, double* noalias %x) nounwind uwtable {
@@ -624,7 +624,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.trunc.f64(double) nounwind readnone
 
-;CHECK: @rint_f32
+;CHECK-LABEL: @rint_f32(
 ;CHECK: llvm.rint.v4f32
 ;CHECK: ret void
 define void @rint_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
@@ -650,7 +650,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.rint.f32(float) nounwind readnone
 
-;CHECK: @rint_f64
+;CHECK-LABEL: @rint_f64(
 ;CHECK: llvm.rint.v4f64
 ;CHECK: ret void
 define void @rint_f64(i32 %n, double* noalias %y, double* noalias %x) nounwind uwtable {
@@ -676,7 +676,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.rint.f64(double) nounwind readnone
 
-;CHECK: @nearbyint_f32
+;CHECK-LABEL: @nearbyint_f32(
 ;CHECK: llvm.nearbyint.v4f32
 ;CHECK: ret void
 define void @nearbyint_f32(i32 %n, float* noalias %y, float* noalias %x) nounwind uwtable {
@@ -702,7 +702,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.nearbyint.f32(float) nounwind readnone
 
-;CHECK: @nearbyint_f64
+;CHECK-LABEL: @nearbyint_f64(
 ;CHECK: llvm.nearbyint.v4f64
 ;CHECK: ret void
 define void @nearbyint_f64(i32 %n, double* noalias %y, double* noalias %x) nounwind uwtable {
@@ -728,7 +728,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.nearbyint.f64(double) nounwind readnone
 
-;CHECK: @fma_f32
+;CHECK-LABEL: @fma_f32(
 ;CHECK: llvm.fma.v4f32
 ;CHECK: ret void
 define void @fma_f32(i32 %n, float* noalias %y, float* noalias %x, float* noalias %z, float* noalias %w) nounwind uwtable {
@@ -758,7 +758,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.fma.f32(float, float, float) nounwind readnone
 
-;CHECK: @fma_f64
+;CHECK-LABEL: @fma_f64(
 ;CHECK: llvm.fma.v4f64
 ;CHECK: ret void
 define void @fma_f64(i32 %n, double* noalias %y, double* noalias %x, double* noalias %z, double* noalias %w) nounwind uwtable {
@@ -788,7 +788,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.fma.f64(double, double, double) nounwind readnone
 
-;CHECK: @fmuladd_f32
+;CHECK-LABEL: @fmuladd_f32(
 ;CHECK: llvm.fmuladd.v4f32
 ;CHECK: ret void
 define void @fmuladd_f32(i32 %n, float* noalias %y, float* noalias %x, float* noalias %z, float* noalias %w) nounwind uwtable {
@@ -818,7 +818,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.fmuladd.f32(float, float, float) nounwind readnone
 
-;CHECK: @fmuladd_f64
+;CHECK-LABEL: @fmuladd_f64(
 ;CHECK: llvm.fmuladd.v4f64
 ;CHECK: ret void
 define void @fmuladd_f64(i32 %n, double* noalias %y, double* noalias %x, double* noalias %z, double* noalias %w) nounwind uwtable {
@@ -848,7 +848,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare double @llvm.fmuladd.f64(double, double, double) nounwind readnone
 
-;CHECK: @pow_f32
+;CHECK-LABEL: @pow_f32(
 ;CHECK: llvm.pow.v4f32
 ;CHECK: ret void
 define void @pow_f32(i32 %n, float* noalias %y, float* noalias %x, float* noalias %z) nounwind uwtable {
@@ -876,7 +876,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 declare float @llvm.pow.f32(float, float) nounwind readnone
 
-;CHECK: @pow_f64
+;CHECK-LABEL: @pow_f64(
 ;CHECK: llvm.pow.v4f64
 ;CHECK: ret void
 define void @pow_f64(i32 %n, double* noalias %y, double* noalias %x, double* noalias %z) nounwind uwtable {
diff --git a/test/Transforms/LoopVectorize/lifetime.ll b/test/Transforms/LoopVectorize/lifetime.ll
new file mode 100644
index 0000000..87006ed
--- /dev/null
+++ b/test/Transforms/LoopVectorize/lifetime.ll
@@ -0,0 +1,96 @@
+; RUN: opt -S -loop-vectorize -force-vector-width=2 -force-vector-unroll=1 < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+; Make sure we can vectorize loops which contain lifetime markers.
+
+; CHECK-LABEL: test
+; CHECK: call void @llvm.lifetime.end
+; CHECK: store <2 x i32>
+; CHECK: call void @llvm.lifetime.start
+
+define void @test(i32 *%d) {
+entry:
+  %arr = alloca [1024 x i32], align 16
+  %0 = bitcast [1024 x i32]* %arr to i8*
+  call void @llvm.lifetime.start(i64 4096, i8* %0) #1
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  call void @llvm.lifetime.end(i64 4096, i8* %0) #1
+  %arrayidx = getelementptr inbounds i32* %d, i64 %indvars.iv
+  %1 = load i32* %arrayidx, align 8
+  store i32 100, i32* %arrayidx, align 8
+  call void @llvm.lifetime.start(i64 4096, i8* %0) #1
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp ne i32 %lftr.wideiv, 128
+  br i1 %exitcond, label %for.body, label %for.end
+
+for.end:
+  call void @llvm.lifetime.end(i64 4096, i8* %0) #1
+  ret void
+}
+
+; CHECK-LABEL: testbitcast
+; CHECK: call void @llvm.lifetime.end
+; CHECK: store <2 x i32>
+; CHECK: call void @llvm.lifetime.start
+
+define void @testbitcast(i32 *%d) {
+entry:
+  %arr = alloca [1024 x i32], align 16
+  %0 = bitcast [1024 x i32]* %arr to i8*
+  call void @llvm.lifetime.start(i64 4096, i8* %0) #1
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %1 = bitcast [1024 x i32]* %arr to i8*
+  call void @llvm.lifetime.end(i64 4096, i8* %1) #1
+  %arrayidx = getelementptr inbounds i32* %d, i64 %indvars.iv
+  %2 = load i32* %arrayidx, align 8
+  store i32 100, i32* %arrayidx, align 8
+  call void @llvm.lifetime.start(i64 4096, i8* %1) #1
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp ne i32 %lftr.wideiv, 128
+  br i1 %exitcond, label %for.body, label %for.end
+
+for.end:
+  call void @llvm.lifetime.end(i64 4096, i8* %0) #1
+  ret void
+}
+
+; CHECK-LABEL: testloopvariant
+; CHECK: call void @llvm.lifetime.end
+; CHECK: store <2 x i32>
+; CHECK: call void @llvm.lifetime.start
+
+define void @testloopvariant(i32 *%d) {
+entry:
+  %arr = alloca [1024 x i32], align 16
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %0 = getelementptr [1024 x i32]* %arr, i32 0, i64 %indvars.iv
+  %1 = bitcast [1024 x i32]* %arr to i8*
+  call void @llvm.lifetime.end(i64 4096, i8* %1) #1
+  %arrayidx = getelementptr inbounds i32* %d, i64 %indvars.iv
+  %2 = load i32* %arrayidx, align 8
+  store i32 100, i32* %arrayidx, align 8
+  call void @llvm.lifetime.start(i64 4096, i8* %1) #1
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp ne i32 %lftr.wideiv, 128
+  br i1 %exitcond, label %for.body, label %for.end
+
+for.end:
+  ret void
+}
+
+declare void @llvm.lifetime.start(i64, i8* nocapture) #1
+
+declare void @llvm.lifetime.end(i64, i8* nocapture) #1
diff --git a/test/Transforms/LoopVectorize/memdep.ll b/test/Transforms/LoopVectorize/memdep.ll
new file mode 100644
index 0000000..b6d9e2e
--- /dev/null
+++ b/test/Transforms/LoopVectorize/memdep.ll
@@ -0,0 +1,222 @@
+; RUN: opt < %s -loop-vectorize -force-vector-width=2 -force-vector-unroll=1 -S | FileCheck %s
+; RUN: opt < %s -loop-vectorize -force-vector-width=4 -force-vector-unroll=1 -S | FileCheck %s -check-prefix=WIDTH
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+; Vectorization with dependence checks.
+
+; No plausible dependence - can be vectorized.
+;  for (i = 0; i < 1024; ++i)
+;    A[i] = A[i + 1] + 1;
+
+; CHECK: f1_vec
+; CHECK: <2 x i32>
+
+define void @f1_vec(i32* %A) {
+entry:
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i32 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %indvars.iv.next = add i32 %indvars.iv, 1
+  %arrayidx = getelementptr inbounds i32* %A, i32 %indvars.iv.next
+  %0 = load i32* %arrayidx, align 4
+  %add1 = add nsw i32 %0, 1
+  %arrayidx3 = getelementptr inbounds i32* %A, i32 %indvars.iv
+  store i32 %add1, i32* %arrayidx3, align 4
+  %exitcond = icmp ne i32 %indvars.iv.next, 1024
+  br i1 %exitcond, label %for.body, label %for.end
+
+for.end:
+  ret void
+}
+
+; Plausible dependence of distance 1 - can't be vectorized.
+;  for (i = 0; i < 1024; ++i)
+;    A[i+1] = A[i] + 1;
+
+; CHECK: f2_novec
+; CHECK-NOT: <2 x i32>
+
+define void @f2_novec(i32* %A) {
+entry:
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i32 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %arrayidx = getelementptr inbounds i32* %A, i32 %indvars.iv
+  %0 = load i32* %arrayidx, align 4
+  %add = add nsw i32 %0, 1
+  %indvars.iv.next = add i32 %indvars.iv, 1
+  %arrayidx3 = getelementptr inbounds i32* %A, i32 %indvars.iv.next
+  store i32 %add, i32* %arrayidx3, align 4
+  %exitcond = icmp ne i32 %indvars.iv.next, 1024
+  br i1 %exitcond, label %for.body, label %for.end
+
+for.end:
+  ret void
+}
+
+; Plausible dependence of distance 2 - can be vectorized with a width of 2.
+;  for (i = 0; i < 1024; ++i)
+;    A[i+2] = A[i] + 1;
+
+; CHECK: f3_vec_len
+; CHECK: <2 x i32>
+
+; WIDTH: f3_vec_len
+; WIDTH-NOT: <4 x i32>
+
+define void @f3_vec_len(i32* %A) {
+entry:
+  br label %for.body
+
+for.body:
+  %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %idxprom = sext i32 %i.01 to i64
+  %arrayidx = getelementptr inbounds i32* %A, i64 %idxprom
+  %0 = load i32* %arrayidx, align 4
+  %add = add nsw i32 %0, 1
+  %add1 = add nsw i32 %i.01, 2
+  %idxprom2 = sext i32 %add1 to i64
+  %arrayidx3 = getelementptr inbounds i32* %A, i64 %idxprom2
+  store i32 %add, i32* %arrayidx3, align 4
+  %inc = add nsw i32 %i.01, 1
+  %cmp = icmp slt i32 %inc, 1024
+  br i1 %cmp, label %for.body, label %for.end
+
+for.end:
+  ret void
+}
+
+; Plausible dependence of distance 1 - cannot be vectorized (without reordering
+; accesses).
+;   for (i = 0; i < 1024; ++i) {
+;     B[i] = A[i];
+;     A[i] = B[i + 1];
+;   }
+
+; CHECK: f5
+; CHECK-NOT: <2 x i32>
+
+define void @f5(i32*  %A, i32* %B) {
+entry:
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv
+  %0 = load i32* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds i32* %B, i64 %indvars.iv
+  store i32 %0, i32* %arrayidx2, align 4
+  %indvars.iv.next = add nsw i64 %indvars.iv, 1
+  %arrayidx4 = getelementptr inbounds i32* %B, i64 %indvars.iv.next
+  %1 = load i32* %arrayidx4, align 4
+  store i32 %1, i32* %arrayidx, align 4
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp ne i32 %lftr.wideiv, 1024
+  br i1 %exitcond, label %for.body, label %for.end
+
+for.end:
+  ret void
+}
+
+; Dependence through a phi node - must not vectorize.
+;   for (i = 0; i < 1024; ++i) {
+;     a[i+1] = tmp;
+;     tmp = a[i];
+;   }
+
+; CHECK: f6
+; CHECK-NOT: <2 x i32>
+
+define i32 @f6(i32* %a, i32 %tmp) {
+entry:
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %tmp.addr.08 = phi i32 [ %tmp, %entry ], [ %0, %for.body ]
+  %indvars.iv.next = add nsw i64 %indvars.iv, 1
+  %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv.next
+  store i32 %tmp.addr.08, i32* %arrayidx, align 4
+  %arrayidx3 = getelementptr inbounds i32* %a, i64 %indvars.iv
+  %0 = load i32* %arrayidx3, align 4
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp ne i32 %lftr.wideiv, 1024
+  br i1 %exitcond, label %for.body, label %for.end
+
+for.end:
+  ret i32 undef
+}
+
+; Don't vectorize true loop carried dependencies that are not a multiple of the
+; vector width.
+; Example:
+;   for (int i = ...; ++i) {
+;     a[i] = a[i-3] + ...;
+; It is a bad idea to vectorize this loop because store-load forwarding will not
+; happen.
+;
+
+; CHECK-LABEL: @nostoreloadforward(
+; CHECK-NOT: <2 x i32>
+
+define void @nostoreloadforward(i32* %A) {
+entry:
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ 16, %entry ], [ %indvars.iv.next, %for.body ]
+  %0 = add nsw i64 %indvars.iv, -3
+  %arrayidx = getelementptr inbounds i32* %A, i64 %0
+  %1 = load i32* %arrayidx, align 4
+  %2 = add nsw i64 %indvars.iv, 4
+  %arrayidx2 = getelementptr inbounds i32* %A, i64 %2
+  %3 = load i32* %arrayidx2, align 4
+  %add3 = add nsw i32 %3, %1
+  %arrayidx5 = getelementptr inbounds i32* %A, i64 %indvars.iv
+  store i32 %add3, i32* %arrayidx5, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp ne i32 %lftr.wideiv, 128
+  br i1 %exitcond, label %for.body, label %for.end
+
+for.end:
+  ret void
+}
+
+; Example:
+;   for (int i = ...; ++i) {
+;     a[i] = b[i];
+;     c[i] = a[i-3] + ...;
+; It is a bad idea to vectorize this loop because store-load forwarding will not
+; happen.
+;
+
+; CHECK-LABEL: @nostoreloadforward2(
+; CHECK-NOT: <2 x i32>
+
+define void @nostoreloadforward2(i32* noalias %A, i32* noalias %B, i32* noalias %C) {
+entry:
+  br label %for.body
+
+for.body:
+  %indvars.iv = phi i64 [ 16, %entry ], [ %indvars.iv.next, %for.body ]
+  %arrayidx = getelementptr inbounds i32* %B, i64 %indvars.iv
+  %0 = load i32* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds i32* %A, i64 %indvars.iv
+  store i32 %0, i32* %arrayidx2, align 4
+  %1 = add nsw i64 %indvars.iv, -3
+  %arrayidx4 = getelementptr inbounds i32* %A, i64 %1
+  %2 = load i32* %arrayidx4, align 4
+  %arrayidx6 = getelementptr inbounds i32* %C, i64 %indvars.iv
+  store i32 %2, i32* %arrayidx6, align 4
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp ne i32 %lftr.wideiv, 128
+  br i1 %exitcond, label %for.body, label %for.end
+
+for.end:
+  ret void
+}
diff --git a/test/Transforms/LoopVectorize/metadata-unroll.ll b/test/Transforms/LoopVectorize/metadata-unroll.ll
index 0112fee..7f10372 100644
--- a/test/Transforms/LoopVectorize/metadata-unroll.ll
+++ b/test/Transforms/LoopVectorize/metadata-unroll.ll
@@ -9,7 +9,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 ;  for (i=0; i<n; i++){
 ;    a[i] += i;
 ;  }
-;CHECK: @inc
+;CHECK-LABEL: @inc(
 ;CHECK: load <4 x i32>
 ;CHECK: load <4 x i32>
 ;CHECK: add nsw <4 x i32>
diff --git a/test/Transforms/LoopVectorize/metadata-width.ll b/test/Transforms/LoopVectorize/metadata-width.ll
index b06d442..1960c0b 100644
--- a/test/Transforms/LoopVectorize/metadata-width.ll
+++ b/test/Transforms/LoopVectorize/metadata-width.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: store <8 x i32>
 ; CHECK: ret void
 define void @test1(i32* nocapture %a, i32 %n) #0 {
diff --git a/test/Transforms/LoopVectorize/minmax_reduction.ll b/test/Transforms/LoopVectorize/minmax_reduction.ll
index 502fd8b..bade561 100644
--- a/test/Transforms/LoopVectorize/minmax_reduction.ll
+++ b/test/Transforms/LoopVectorize/minmax_reduction.ll
@@ -10,7 +10,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 ; Turn this into a max reduction. Make sure we use a splat to initialize the
 ; vector for the reduction.
-; CHECK: @max_red
+; CHECK-LABEL: @max_red(
 ; CHECK: %[[VAR:.*]] = insertelement <2 x i32> undef, i32 %max, i32 0
 ; CHECK: {{.*}} = shufflevector <2 x i32> %[[VAR]], <2 x i32> undef, <2 x i32> zeroinitializer
 ; CHECK: icmp sgt <2 x i32>
@@ -41,7 +41,7 @@ for.end:
 
 ; Turn this into a max reduction. The select has its inputs reversed therefore
 ; this is a max reduction.
-; CHECK: @max_red_inverse_select
+; CHECK-LABEL: @max_red_inverse_select(
 ; CHECK: icmp slt <2 x i32>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -69,7 +69,7 @@ for.end:
 }
 
 ; Turn this into a min reduction.
-; CHECK: @min_red
+; CHECK-LABEL: @min_red(
 ; CHECK: icmp slt <2 x i32>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -98,7 +98,7 @@ for.end:
 
 ; Turn this into a min reduction. The select has its inputs reversed therefore
 ; this is a min reduction.
-; CHECK: @min_red_inverse_select
+; CHECK-LABEL: @min_red_inverse_select(
 ; CHECK: icmp sgt <2 x i32>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -128,7 +128,7 @@ for.end:
 ; Unsigned tests.
 
 ; Turn this into a max reduction.
-; CHECK: @umax_red
+; CHECK-LABEL: @umax_red(
 ; CHECK: icmp ugt <2 x i32>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -157,7 +157,7 @@ for.end:
 
 ; Turn this into a max reduction. The select has its inputs reversed therefore
 ; this is a max reduction.
-; CHECK: @umax_red_inverse_select
+; CHECK-LABEL: @umax_red_inverse_select(
 ; CHECK: icmp ult <2 x i32>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -185,7 +185,7 @@ for.end:
 }
 
 ; Turn this into a min reduction.
-; CHECK: @umin_red
+; CHECK-LABEL: @umin_red(
 ; CHECK: icmp ult <2 x i32>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -214,7 +214,7 @@ for.end:
 
 ; Turn this into a min reduction. The select has its inputs reversed therefore
 ; this is a min reduction.
-; CHECK: @umin_red_inverse_select
+; CHECK-LABEL: @umin_red_inverse_select(
 ; CHECK: icmp ugt <2 x i32>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -243,7 +243,7 @@ for.end:
 
 ; SGE -> SLT
 ; Turn this into a min reduction (select inputs are reversed).
-; CHECK: @sge_min_red
+; CHECK-LABEL: @sge_min_red(
 ; CHECK: icmp sge <2 x i32>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -272,7 +272,7 @@ for.end:
 
 ; SLE -> SGT
 ; Turn this into a max reduction (select inputs are reversed).
-; CHECK: @sle_min_red
+; CHECK-LABEL: @sle_min_red(
 ; CHECK: icmp sle <2 x i32>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -301,7 +301,7 @@ for.end:
 
 ; UGE -> ULT
 ; Turn this into a min reduction (select inputs are reversed).
-; CHECK: @uge_min_red
+; CHECK-LABEL: @uge_min_red(
 ; CHECK: icmp uge <2 x i32>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -330,7 +330,7 @@ for.end:
 
 ; ULE -> UGT
 ; Turn this into a max reduction (select inputs are reversed).
-; CHECK: @ule_min_red
+; CHECK-LABEL: @ule_min_red(
 ; CHECK: icmp ule <2 x i32>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -358,7 +358,7 @@ for.end:
 }
 
 ; No reduction.
-; CHECK: @no_red_1
+; CHECK-LABEL: @no_red_1(
 ; CHECK-NOT: icmp <2 x i32>
 define i32 @no_red_1(i32 %max) {
 entry:
@@ -382,7 +382,7 @@ for.end:
   ret i32 %max.red.0
 }
 
-; CHECK: @no_red_2
+; CHECK-LABEL: @no_red_2(
 ; CHECK-NOT: icmp <2 x i32>
 define i32 @no_red_2(i32 %max) {
 entry:
@@ -411,7 +411,7 @@ for.end:
 ; Maximum.
 
 ; Turn this into a max reduction in the presence of a no-nans-fp-math attribute.
-; CHECK: @max_red_float
+; CHECK-LABEL: @max_red_float(
 ; CHECK: fcmp ogt <2 x float>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -437,7 +437,7 @@ for.end:
   ret float %max.red.0
 }
 
-; CHECK: @max_red_float_ge
+; CHECK-LABEL: @max_red_float_ge(
 ; CHECK: fcmp oge <2 x float>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -463,7 +463,7 @@ for.end:
   ret float %max.red.0
 }
 
-; CHECK: @inverted_max_red_float
+; CHECK-LABEL: @inverted_max_red_float(
 ; CHECK: fcmp olt <2 x float>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -489,7 +489,7 @@ for.end:
   ret float %max.red.0
 }
 
-; CHECK: @inverted_max_red_float_le
+; CHECK-LABEL: @inverted_max_red_float_le(
 ; CHECK: fcmp ole <2 x float>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -541,7 +541,7 @@ for.end:
   ret float %max.red.0
 }
 
-; CHECK: @unordered_max_red_float_ge
+; CHECK-LABEL: @unordered_max_red_float_ge(
 ; CHECK: fcmp uge <2 x float>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -593,7 +593,7 @@ for.end:
   ret float %max.red.0
 }
 
-; CHECK: @inverted_unordered_max_red_float_le
+; CHECK-LABEL: @inverted_unordered_max_red_float_le(
 ; CHECK: fcmp ule <2 x float>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -622,7 +622,7 @@ for.end:
 ; Minimum.
 
 ; Turn this into a min reduction in the presence of a no-nans-fp-math attribute.
-; CHECK: @min_red_float
+; CHECK-LABEL: @min_red_float(
 ; CHECK: fcmp olt <2 x float>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -648,7 +648,7 @@ for.end:
   ret float %min.red.0
 }
 
-; CHECK: @min_red_float_le
+; CHECK-LABEL: @min_red_float_le(
 ; CHECK: fcmp ole <2 x float>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -674,7 +674,7 @@ for.end:
   ret float %min.red.0
 }
 
-; CHECK: @inverted_min_red_float
+; CHECK-LABEL: @inverted_min_red_float(
 ; CHECK: fcmp ogt <2 x float>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -700,7 +700,7 @@ for.end:
   ret float %min.red.0
 }
 
-; CHECK: @inverted_min_red_float_ge
+; CHECK-LABEL: @inverted_min_red_float_ge(
 ; CHECK: fcmp oge <2 x float>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -752,7 +752,7 @@ for.end:
   ret float %min.red.0
 }
 
-; CHECK: @unordered_min_red_float_le
+; CHECK-LABEL: @unordered_min_red_float_le(
 ; CHECK: fcmp ule <2 x float>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -804,7 +804,7 @@ for.end:
   ret float %min.red.0
 }
 
-; CHECK: @inverted_unordered_min_red_float_ge
+; CHECK-LABEL: @inverted_unordered_min_red_float_ge(
 ; CHECK: fcmp uge <2 x float>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -831,7 +831,7 @@ for.end:
 }
 
 ; Make sure we handle doubles, too.
-; CHECK: @min_red_double
+; CHECK-LABEL: @min_red_double(
 ; CHECK: fcmp olt <2 x double>
 ; CHECK: select <2 x i1>
 ; CHECK: middle.block
@@ -859,7 +859,7 @@ for.end:
 
 
 ; Don't this into a max reduction. The no-nans-fp-math attribute is missing
-; CHECK: @max_red_float_nans
+; CHECK-LABEL: @max_red_float_nans(
 ; CHECK-NOT: <2 x float>
 
 define float @max_red_float_nans(float %max) {
diff --git a/test/Transforms/LoopVectorize/multiple-address-spaces.ll b/test/Transforms/LoopVectorize/multiple-address-spaces.ll
new file mode 100644
index 0000000..6906195
--- /dev/null
+++ b/test/Transforms/LoopVectorize/multiple-address-spaces.ll
@@ -0,0 +1,47 @@
+; RUN: opt < %s  -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine -S | FileCheck %s
+
+; From a simple program with two address spaces:
+; char Y[4*10000] __attribute__((address_space(1)));
+; char X[4*10000];
+; int main() {
+;    for (int i = 0; i < 4*10000; ++i)
+;        X[i] = Y[i] + 1;
+;    return 0;
+;}
+
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+@Y = common addrspace(1) global [40000 x i8] zeroinitializer, align 16
+@X = common global [40000 x i8] zeroinitializer, align 16
+
+;CHECK-LABEL: @main(
+;CHECK: bitcast i8 addrspace(1)* %{{.*}} to <4 x i8> addrspace(1)*
+;CHECK: bitcast i8* %{{.*}} to <4 x i8>*
+
+; Function Attrs: nounwind uwtable
+define i32 @main() #0 {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %arrayidx = getelementptr inbounds [40000 x i8] addrspace(1)* @Y, i64 0, i64 %indvars.iv
+  %0 = load i8 addrspace(1)* %arrayidx, align 1, !tbaa !0
+  %add = add i8 %0, 1
+  %arrayidx3 = getelementptr inbounds [40000 x i8]* @X, i64 0, i64 %indvars.iv
+  store i8 %add, i8* %arrayidx3, align 1, !tbaa !0
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %lftr.wideiv = trunc i64 %indvars.iv.next to i32
+  %exitcond = icmp eq i32 %lftr.wideiv, 40000
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  ret i32 0
+}
+
+attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!0 = metadata !{metadata !"omnipotent char", metadata !1}
+!1 = metadata !{metadata !"Simple C/C++ TBAA"}
diff --git a/test/Transforms/LoopVectorize/no_idiv_reduction.ll b/test/Transforms/LoopVectorize/no_idiv_reduction.ll
index cdfb3fd..295fcab 100644
--- a/test/Transforms/LoopVectorize/no_idiv_reduction.ll
+++ b/test/Transforms/LoopVectorize/no_idiv_reduction.ll
@@ -7,7 +7,7 @@ entry:
   br label %for.body
 
 for.body:
-  ; CHECK: @g
+  ; CHECK-LABEL: @g(
   ; CHECK-NOT: sdiv <2 x i32>
   %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
   %r.05 = phi i32 [ 80, %entry ], [ %div, %for.body ]
diff --git a/test/Transforms/LoopVectorize/no_int_induction.ll b/test/Transforms/LoopVectorize/no_int_induction.ll
index 45aa8c7..66d5301 100644
--- a/test/Transforms/LoopVectorize/no_int_induction.ll
+++ b/test/Transforms/LoopVectorize/no_int_induction.ll
@@ -7,7 +7,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
-;CHECK: @sum_array
+;CHECK-LABEL: @sum_array(
 ;CHECK: phi <4 x i32>
 ;CHECK: load <4 x i32>
 ;CHECK: add nsw <4 x i32>
diff --git a/test/Transforms/LoopVectorize/nofloat.ll b/test/Transforms/LoopVectorize/nofloat.ll
index de23bf0..c3c81b6 100644
--- a/test/Transforms/LoopVectorize/nofloat.ll
+++ b/test/Transforms/LoopVectorize/nofloat.ll
@@ -7,7 +7,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 
 @a = common global [2048 x i32] zeroinitializer, align 16
 
-;CHECK: @example12
+;CHECK-LABEL: @example12(
 ;CHECK-NOT: store <4 x i32>
 ;CHECK: ret void
 define void @example12() noimplicitfloat { ;           <--------- "noimplicitfloat" attribute here!
diff --git a/test/Transforms/LoopVectorize/non-const-n.ll b/test/Transforms/LoopVectorize/non-const-n.ll
index 8262a18..0c54a2b 100644
--- a/test/Transforms/LoopVectorize/non-const-n.ll
+++ b/test/Transforms/LoopVectorize/non-const-n.ll
@@ -7,7 +7,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 @c = common global [2048 x i32] zeroinitializer, align 16
 @a = common global [2048 x i32] zeroinitializer, align 16
 
-;CHECK: @example1
+;CHECK-LABEL: @example1(
 ;CHECK: shl i32
 ;CHECK: zext i32
 ;CHECK: load <4 x i32>
diff --git a/test/Transforms/LoopVectorize/read-only.ll b/test/Transforms/LoopVectorize/read-only.ll
index bfaa6d4..fc8f0a5 100644
--- a/test/Transforms/LoopVectorize/read-only.ll
+++ b/test/Transforms/LoopVectorize/read-only.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
-;CHECK: @read_only_func
+;CHECK-LABEL: @read_only_func(
 ;CHECK: load <4 x i32>
 ;CHECK: ret i32
 define i32 @read_only_func(i32* nocapture %A, i32* nocapture %B, i32 %n) nounwind uwtable readonly ssp {
diff --git a/test/Transforms/LoopVectorize/reduction.ll b/test/Transforms/LoopVectorize/reduction.ll
index 286b736..18a0a93 100644
--- a/test/Transforms/LoopVectorize/reduction.ll
+++ b/test/Transforms/LoopVectorize/reduction.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
-;CHECK: @reduction_sum
+;CHECK-LABEL: @reduction_sum(
 ;CHECK: phi <4 x i32>
 ;CHECK: load <4 x i32>
 ;CHECK: add <4 x i32>
@@ -38,7 +38,7 @@ define i32 @reduction_sum(i32 %n, i32* noalias nocapture %A, i32* noalias nocapt
   ret i32 %sum.0.lcssa
 }
 
-;CHECK: @reduction_prod
+;CHECK-LABEL: @reduction_prod(
 ;CHECK: phi <4 x i32>
 ;CHECK: load <4 x i32>
 ;CHECK: mul <4 x i32>
@@ -73,7 +73,7 @@ define i32 @reduction_prod(i32 %n, i32* noalias nocapture %A, i32* noalias nocap
   ret i32 %prod.0.lcssa
 }
 
-;CHECK: @reduction_mix
+;CHECK-LABEL: @reduction_mix(
 ;CHECK: phi <4 x i32>
 ;CHECK: load <4 x i32>
 ;CHECK: mul nsw <4 x i32>
@@ -108,7 +108,7 @@ define i32 @reduction_mix(i32 %n, i32* noalias nocapture %A, i32* noalias nocapt
   ret i32 %sum.0.lcssa
 }
 
-;CHECK: @reduction_mul
+;CHECK-LABEL: @reduction_mul(
 ;CHECK: mul <4 x i32>
 ;CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
 ;CHECK: mul <4 x i32>
@@ -141,7 +141,7 @@ define i32 @reduction_mul(i32 %n, i32* noalias nocapture %A, i32* noalias nocapt
   ret i32 %sum.0.lcssa
 }
 
-;CHECK: @start_at_non_zero
+;CHECK-LABEL: @start_at_non_zero(
 ;CHECK: phi <4 x i32>
 ;CHECK: <i32 120, i32 0, i32 0, i32 0>
 ;CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
@@ -174,7 +174,7 @@ for.end:                                          ; preds = %for.body, %entry
   ret i32 %sum.0.lcssa
 }
 
-;CHECK: @reduction_and
+;CHECK-LABEL: @reduction_and(
 ;CHECK: and <4 x i32>
 ;CHECK: <i32 -1, i32 -1, i32 -1, i32 -1>
 ;CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
@@ -207,7 +207,7 @@ for.end:                                          ; preds = %for.body, %entry
   ret i32 %result.0.lcssa
 }
 
-;CHECK: @reduction_or
+;CHECK-LABEL: @reduction_or(
 ;CHECK: or <4 x i32>
 ;CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
 ;CHECK: or <4 x i32>
@@ -239,7 +239,7 @@ for.end:                                          ; preds = %for.body, %entry
   ret i32 %result.0.lcssa
 }
 
-;CHECK: @reduction_xor
+;CHECK-LABEL: @reduction_xor(
 ;CHECK: xor <4 x i32>
 ;CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
 ;CHECK: xor <4 x i32>
@@ -272,7 +272,7 @@ for.end:                                          ; preds = %for.body, %entry
 }
 
 ; In this code the subtracted variable is on the RHS and this is not an induction variable.
-;CHECK: @reduction_sub_rhs
+;CHECK-LABEL: @reduction_sub_rhs(
 ;CHECK-NOT: phi <4 x i32>
 ;CHECK-NOT: sub nsw <4 x i32>
 ;CHECK: ret i32
@@ -299,7 +299,7 @@ for.end:                                          ; preds = %for.body, %entry
 
 
 ; In this test the reduction variable is on the LHS and we can vectorize it.
-;CHECK: @reduction_sub_lhs
+;CHECK-LABEL: @reduction_sub_lhs(
 ;CHECK: phi <4 x i32>
 ;CHECK: sub nsw <4 x i32>
 ;CHECK: ret i32
@@ -442,3 +442,28 @@ for.end:
   %add2 = fadd fast float %add.lcssa, %add1.lcssa
   ret float %add2
 }
+
+
+; When vectorizing a reduction whose loop header phi value is used outside the
+; loop special care must be taken. Otherwise, the reduced value feeding into the
+; outside user misses a few iterations (VF-1) of the loop.
+; PR16522
+
+; CHECK-LABEL: @phivalueredux(
+; CHECK-NOT: x i32>
+
+define i32 @phivalueredux(i32 %p) {
+entry:
+  br label %for.body
+
+for.body:
+  %t.03 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %p.addr.02 = phi i32 [ %p, %entry ], [ %xor, %for.body ]
+  %xor = xor i32 %p.addr.02, -1
+  %inc = add nsw i32 %t.03, 1
+  %exitcond = icmp eq i32 %inc, 16
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:
+  ret i32 %p.addr.02
+}
diff --git a/test/Transforms/LoopVectorize/reverse_iter.ll b/test/Transforms/LoopVectorize/reverse_iter.ll
index 6ff4f1f..f803120 100644
--- a/test/Transforms/LoopVectorize/reverse_iter.ll
+++ b/test/Transforms/LoopVectorize/reverse_iter.ll
@@ -13,7 +13,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 ; }
 ;
 
-;CHECK: @foo
+;CHECK-LABEL: @foo(
 ;CHECK:  <i64 0, i64 -1, i64 -2, i64 -3>
 ;CHECK: ret
 define i32 @foo(i32 %n, i32* nocapture %A) {
diff --git a/test/Transforms/LoopVectorize/runtime-check.ll b/test/Transforms/LoopVectorize/runtime-check.ll
index 014c4fc..4772256 100644
--- a/test/Transforms/LoopVectorize/runtime-check.ll
+++ b/test/Transforms/LoopVectorize/runtime-check.ll
@@ -12,7 +12,7 @@ target triple = "x86_64-apple-macosx10.9.0"
 ;CHECK: for.body.preheader:
 ;CHECK: br i1 %cmp.zero, label %middle.block, label %vector.memcheck
 ;CHECK: vector.memcheck:
-;CHECK: br i1 %found.conflict, label %middle.block, label %vector.ph
+;CHECK: br i1 %memcheck.conflict, label %middle.block, label %vector.ph
 ;CHECK: load <4 x float>
 define i32 @foo(float* nocapture %a, float* nocapture %b, i32 %n) nounwind uwtable ssp {
 entry:
diff --git a/test/Transforms/LoopVectorize/safegep.ll b/test/Transforms/LoopVectorize/safegep.ll
new file mode 100644
index 0000000..46ec28b
--- /dev/null
+++ b/test/Transforms/LoopVectorize/safegep.ll
@@ -0,0 +1,61 @@
+; RUN: opt -S -loop-vectorize -force-vector-width=4 -force-vector-unroll=1  < %s |  FileCheck %s
+target datalayout = "e-p:32:32:32-S128-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f16:16:16-f32:32:32-f64:32:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32"
+
+
+; We can vectorize this code because if the address computation would wrap then
+; a load from 0 would take place which is undefined behaviour in address space 0
+; according to LLVM IR semantics.
+
+; PR16592
+
+; CHECK: safe
+; CHECK: <4 x float>
+
+define void @safe(float* %A, float* %B, float %K) {
+entry:
+  br label %"<bb 3>"
+
+"<bb 3>":
+  %i_15 = phi i32 [ 0, %entry ], [ %i_19, %"<bb 3>" ]
+  %pp3 = getelementptr float* %A, i32 %i_15
+  %D.1396_10 = load float* %pp3, align 4
+  %pp24 = getelementptr float* %B, i32 %i_15
+  %D.1398_15 = load float* %pp24, align 4
+  %D.1399_17 = fadd float %D.1398_15, %K
+  %D.1400_18 = fmul float %D.1396_10, %D.1399_17
+  store float %D.1400_18, float* %pp3, align 4
+  %i_19 = add nsw i32 %i_15, 1
+  %exitcond = icmp ne i32 %i_19, 64
+  br i1 %exitcond, label %"<bb 3>", label %return
+
+return:
+  ret void
+}
+
+; In a non-default address space we don't have this rule.
+
+; CHECK: notsafe
+; CHECK-NOT: <4 x float>
+
+define void @notsafe(float addrspace(5) * %A, float* %B, float %K) {
+entry:
+  br label %"<bb 3>"
+
+"<bb 3>":
+  %i_15 = phi i32 [ 0, %entry ], [ %i_19, %"<bb 3>" ]
+  %pp3 = getelementptr float addrspace(5) * %A, i32 %i_15
+  %D.1396_10 = load float addrspace(5) * %pp3, align 4
+  %pp24 = getelementptr float* %B, i32 %i_15
+  %D.1398_15 = load float* %pp24, align 4
+  %D.1399_17 = fadd float %D.1398_15, %K
+  %D.1400_18 = fmul float %D.1396_10, %D.1399_17
+  store float %D.1400_18, float addrspace(5) * %pp3, align 4
+  %i_19 = add nsw i32 %i_15, 1
+  %exitcond = icmp ne i32 %i_19, 64
+  br i1 %exitcond, label %"<bb 3>", label %return
+
+return:
+  ret void
+}
+
+
diff --git a/test/Transforms/LoopVectorize/same-base-access.ll b/test/Transforms/LoopVectorize/same-base-access.ll
index 1573893..d623a34 100644
--- a/test/Transforms/LoopVectorize/same-base-access.ll
+++ b/test/Transforms/LoopVectorize/same-base-access.ll
@@ -11,7 +11,7 @@ target triple = "x86_64-apple-macosx10.9.0"
 ;     x[k] = x[k-1] + y[k];
 ; }
 
-; CHECK: @kernel11
+; CHECK-LABEL: @kernel11(
 ; CHECK-NOT: <4 x double>
 ; CHECK: ret
 define i32 @kernel11(double* %x, double* %y, i32 %n) nounwind uwtable ssp {
@@ -77,7 +77,7 @@ define i32 @kernel11(double* %x, double* %y, i32 %n) nounwind uwtable ssp {
 ;   }
 ; }
 
-; CHECK: @func2
+; CHECK-LABEL: @func2(
 ; CHECK-NOT: <4 x i32>
 ; CHECK: ret
 define i32 @func2(i32* nocapture %a) nounwind uwtable ssp {
diff --git a/test/Transforms/LoopVectorize/scalar-select.ll b/test/Transforms/LoopVectorize/scalar-select.ll
index 7a14d24..257c7be 100644
--- a/test/Transforms/LoopVectorize/scalar-select.ll
+++ b/test/Transforms/LoopVectorize/scalar-select.ll
@@ -7,7 +7,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 @b = common global [2048 x i32] zeroinitializer, align 16
 @c = common global [2048 x i32] zeroinitializer, align 16
 
-;CHECK: @example1
+;CHECK-LABEL: @example1(
 ;CHECK: load <4 x i32>
 ; make sure that we have a scalar condition and a vector operand.
 ;CHECK: select i1 %cond, <4 x i32>
diff --git a/test/Transforms/LoopVectorize/scev-exitlim-crash.ll b/test/Transforms/LoopVectorize/scev-exitlim-crash.ll
new file mode 100644
index 0000000..7687738
--- /dev/null
+++ b/test/Transforms/LoopVectorize/scev-exitlim-crash.ll
@@ -0,0 +1,113 @@
+; RUN: opt < %s -loop-vectorize -force-vector-unroll=2 -force-vector-width=8 -S | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx"
+
+@b = common global i32 0, align 4
+@f = common global i32 0, align 4
+@a = common global i32 0, align 4
+@d = common global i32* null, align 8
+@e = common global i32* null, align 8
+@c = common global i32 0, align 4
+
+; CHECK-LABEL-LABEL: @fn1(
+; CHECK: vector.body
+define void @fn1() #0 {
+entry:
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.cond, %entry
+  %i.0 = phi i32 [ undef, %entry ], [ %inc, %for.cond ]
+  %cmp = icmp slt i32 %i.0, 0
+  %call = tail call i32 @fn2(double fadd (double fsub (double undef, double undef), double 1.000000e+00)) #2
+  %inc = add nsw i32 %i.0, 1
+  br i1 %cmp, label %for.cond, label %for.cond4.preheader
+
+for.cond4.preheader:                              ; preds = %for.cond
+  %call.lcssa = phi i32 [ %call, %for.cond ]
+  %cmp514 = icmp sgt i32 %call.lcssa, 0
+  br i1 %cmp514, label %for.cond7.preheader.lr.ph, label %for.end26
+
+for.cond7.preheader.lr.ph:                        ; preds = %for.cond4.preheader
+  %0 = load i32** @e, align 8, !tbaa !0
+  br label %for.cond7.preheader
+
+for.cond7.preheader:                              ; preds = %for.cond7.preheader.lr.ph, %for.inc23
+  %y.017 = phi i32 [ 0, %for.cond7.preheader.lr.ph ], [ %inc24, %for.inc23 ]
+  %i.116 = phi i32 [ 0, %for.cond7.preheader.lr.ph ], [ %i.2.lcssa, %for.inc23 ]
+  %n.015 = phi i32 [ undef, %for.cond7.preheader.lr.ph ], [ %inc25, %for.inc23 ]
+  %1 = load i32* @b, align 4, !tbaa !3
+  %tobool11 = icmp eq i32 %1, 0
+  br i1 %tobool11, label %for.inc23, label %for.body8.lr.ph
+
+for.body8.lr.ph:                                  ; preds = %for.cond7.preheader
+  %add9 = add i32 %n.015, 1
+  br label %for.body8
+
+for.body8:                                        ; preds = %for.body8.lr.ph, %for.inc19
+  %indvars.iv19 = phi i64 [ 0, %for.body8.lr.ph ], [ %indvars.iv.next20, %for.inc19 ]
+  %i.213 = phi i32 [ %i.116, %for.body8.lr.ph ], [ 0, %for.inc19 ]
+  %2 = trunc i64 %indvars.iv19 to i32
+  %add10 = add i32 %add9, %2
+  store i32 %add10, i32* @f, align 4, !tbaa !3
+  %idx.ext = sext i32 %add10 to i64
+  %add.ptr = getelementptr inbounds i32* @a, i64 %idx.ext
+  %tobool129 = icmp eq i32 %i.213, 0
+  br i1 %tobool129, label %for.inc19, label %for.body13.lr.ph
+
+for.body13.lr.ph:                                 ; preds = %for.body8
+  %3 = sext i32 %i.213 to i64
+  br label %for.body13
+
+for.body13:                                       ; preds = %for.body13.lr.ph, %for.body13
+  %indvars.iv = phi i64 [ %3, %for.body13.lr.ph ], [ %indvars.iv.next, %for.body13 ]
+  %add.ptr.sum = add i64 %idx.ext, %indvars.iv
+  %arrayidx = getelementptr inbounds i32* @a, i64 %add.ptr.sum
+  %4 = load i32* %arrayidx, align 4, !tbaa !3
+  %arrayidx15 = getelementptr inbounds i32* %0, i64 %indvars.iv
+  store i32 %4, i32* %arrayidx15, align 4, !tbaa !3
+  %indvars.iv.next = add i64 %indvars.iv, 1
+  %5 = trunc i64 %indvars.iv.next to i32
+  %tobool12 = icmp eq i32 %5, 0
+  br i1 %tobool12, label %for.cond11.for.inc19_crit_edge, label %for.body13
+
+for.cond11.for.inc19_crit_edge:                   ; preds = %for.body13
+  br label %for.inc19
+
+for.inc19:                                        ; preds = %for.cond11.for.inc19_crit_edge, %for.body8
+  %6 = load i32* @c, align 4, !tbaa !3
+  %inc20 = add nsw i32 %6, 1
+  store i32 %inc20, i32* @c, align 4, !tbaa !3
+  %indvars.iv.next20 = add i64 %indvars.iv19, 1
+  %7 = load i32* @b, align 4, !tbaa !3
+  %tobool = icmp eq i32 %7, 0
+  br i1 %tobool, label %for.cond7.for.inc23_crit_edge, label %for.body8
+
+for.cond7.for.inc23_crit_edge:                    ; preds = %for.inc19
+  %add.ptr.lcssa = phi i32* [ %add.ptr, %for.inc19 ]
+  store i32* %add.ptr.lcssa, i32** @d, align 8, !tbaa !0
+  br label %for.inc23
+
+for.inc23:                                        ; preds = %for.cond7.for.inc23_crit_edge, %for.cond7.preheader
+  %i.2.lcssa = phi i32 [ 0, %for.cond7.for.inc23_crit_edge ], [ %i.116, %for.cond7.preheader ]
+  %inc24 = add nsw i32 %y.017, 1
+  %inc25 = add nsw i32 %n.015, 1
+  %exitcond = icmp ne i32 %inc24, %call.lcssa
+  br i1 %exitcond, label %for.cond7.preheader, label %for.cond4.for.end26_crit_edge
+
+for.cond4.for.end26_crit_edge:                    ; preds = %for.inc23
+  br label %for.end26
+
+for.end26:                                        ; preds = %for.cond4.for.end26_crit_edge, %for.cond4.preheader
+  ret void
+}
+declare i32 @fn2(double) #1
+
+attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!0 = metadata !{metadata !"int", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA"}
+!3 = metadata !{metadata !"double", metadata !1}
+!4 = metadata !{metadata !"any pointer", metadata !1}
diff --git a/test/Transforms/LoopVectorize/simple-unroll.ll b/test/Transforms/LoopVectorize/simple-unroll.ll
index 7e2dd5f..83f35ff 100644
--- a/test/Transforms/LoopVectorize/simple-unroll.ll
+++ b/test/Transforms/LoopVectorize/simple-unroll.ll
@@ -9,7 +9,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 ;  for (i=0; i<n; i++){
 ;    a[i] += i;
 ;  }
-;CHECK: @inc
+;CHECK-LABEL: @inc(
 ;CHECK: load <4 x i32>
 ;CHECK: load <4 x i32>
 ;CHECK: add nsw <4 x i32>
diff --git a/test/Transforms/LoopVectorize/small-loop.ll b/test/Transforms/LoopVectorize/small-loop.ll
index fa83dba..49ce5c5 100644
--- a/test/Transforms/LoopVectorize/small-loop.ll
+++ b/test/Transforms/LoopVectorize/small-loop.ll
@@ -7,7 +7,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 @b = common global [2048 x i32] zeroinitializer, align 16
 @c = common global [2048 x i32] zeroinitializer, align 16
 
-;CHECK: @example1
+;CHECK-LABEL: @example1(
 ;CHECK-NOT: load <4 x i32>
 ;CHECK: ret void
 define void @example1() nounwind uwtable ssp {
diff --git a/test/Transforms/LoopVectorize/start-non-zero.ll b/test/Transforms/LoopVectorize/start-non-zero.ll
index e8a089a..8f675af 100644
--- a/test/Transforms/LoopVectorize/start-non-zero.ll
+++ b/test/Transforms/LoopVectorize/start-non-zero.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
-;CHECK: @start_at_nonzero
+;CHECK-LABEL: @start_at_nonzero(
 ;CHECK: mul nuw <4 x i32>
 ;CHECK: ret i32
 define i32 @start_at_nonzero(i32* nocapture %a, i32 %start, i32 %end) nounwind uwtable ssp {
diff --git a/test/Transforms/LoopVectorize/store-shuffle-bug.ll b/test/Transforms/LoopVectorize/store-shuffle-bug.ll
new file mode 100644
index 0000000..0ec8010
--- /dev/null
+++ b/test/Transforms/LoopVectorize/store-shuffle-bug.ll
@@ -0,0 +1,55 @@
+; RUN: opt -S -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+@uf = common global [100 x i32] zeroinitializer, align 16
+@xi = common global [100 x i32] zeroinitializer, align 16
+@q = common global [100 x i32] zeroinitializer, align 16
+
+; PR16455
+
+
+; Due to a bug in the way we handled reverse induction stores we would generate
+; a shuffle too many.
+
+define void @t()  {
+entry:
+  br label %for.body
+
+; CHECK-LABEL: @t(
+; CHECK: vector.body:
+; CHECK: load <4 x i32>
+; CHECK: [[VAR1:%[a-zA-Z0-9]+]] = shufflevector
+; CHECK: load <4 x i32>
+; CHECK: [[VAR2:%[a-zA-Z0-9]+]] = shufflevector
+; CHECK: [[VAR3:%[a-zA-Z0-9]+]] = add nsw <4 x i32> [[VAR2]], [[VAR1]]
+; CHECK: [[VAR4:%[a-zA-Z0-9]+]] = shufflevector <4 x i32> [[VAR3]]
+; CHECK: store <4 x i32> [[VAR4]]
+; CHECK: load <4 x i32>
+; CHECK: [[VAR5:%[a-zA-Z0-9]+]] = shufflevector
+; CHECK-NOT: add nsw <4 x i32> [[VAR4]], [[VAR5]]
+; CHECK-NOT: add nsw <4 x i32> [[VAR5]], [[VAR4]]
+; CHECK: add nsw <4 x i32> [[VAR3]], [[VAR5]]
+
+for.body:
+  %indvars.iv = phi i64 [ 93, %entry ], [ %indvars.iv.next, %for.body ]
+  %0 = add i64 %indvars.iv, 1
+  %arrayidx = getelementptr inbounds [100 x i32]* @uf, i64 0, i64 %0
+  %arrayidx3 = getelementptr inbounds [100 x i32]* @xi, i64 0, i64 %0
+  %1 = load i32* %arrayidx3, align 4
+  %2 = load i32* %arrayidx, align 4
+  %add4 = add nsw i32 %2, %1
+  store i32 %add4, i32* %arrayidx, align 4
+  %arrayidx7 = getelementptr inbounds [100 x i32]* @q, i64 0, i64 %0
+  %3 = load i32* %arrayidx7, align 4
+  %add8 = add nsw i32 %add4, %3
+  store i32 %add8, i32* %arrayidx, align 4
+  %indvars.iv.next = add i64 %indvars.iv, -1
+  %4 = trunc i64 %indvars.iv.next to i32
+  %cmp = icmp ugt i32 %4, 2
+  br i1 %cmp, label %for.body, label %for.end
+
+for.end:
+  ret void
+}
diff --git a/test/Transforms/LoopVectorize/struct_access.ll b/test/Transforms/LoopVectorize/struct_access.ll
index 573480d..0cfaabe 100644
--- a/test/Transforms/LoopVectorize/struct_access.ll
+++ b/test/Transforms/LoopVectorize/struct_access.ll
@@ -21,7 +21,7 @@ target triple = "x86_64-apple-macosx10.9.0"
 ;   return sum;
 ; }
 
-;CHECK: @foo
+;CHECK-LABEL: @foo(
 ;CHECK-NOT: load <4 x i32>
 ;CHECK: ret
 define i32 @foo(%struct.coordinate* nocapture %A, i32 %n) nounwind uwtable readonly ssp {
diff --git a/test/Transforms/LoopVectorize/undef-inst-bug.ll b/test/Transforms/LoopVectorize/undef-inst-bug.ll
new file mode 100644
index 0000000..ed60e80
--- /dev/null
+++ b/test/Transforms/LoopVectorize/undef-inst-bug.ll
@@ -0,0 +1,36 @@
+; RUN: opt -S -loop-vectorize -force-vector-width=4 -force-vector-unroll=1 < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+; We use to fail on this loop because we did not properly handle the loop
+; invariant instruction anchored in the loop when used as a getelementptr index.
+; We would use the index from the original loop resulting in a use not dominated
+; by the definition.
+
+; PR16452
+
+; Verify that we don't miscompile this loop.
+
+; CHECK-LABEL: @t(
+; CHECK: <4 x i32>
+
+define void @t() {
+entry:
+  br label %for.body
+
+for.body:
+  %indvars.iv17 = phi i64 [ %indvars.next, %for.body ], [ 128, %entry ]
+
+  ; Loop invariant anchored in loop.
+  %idxprom21 = zext i32 undef to i64
+
+  %arrayidx23 = getelementptr inbounds [100 x [100 x i32]]* undef, i64 0, i64 %idxprom21, i64 %indvars.iv17
+  store i32 undef, i32* %arrayidx23, align 4
+  %indvars.next= add i64 %indvars.iv17, -1
+  %0 = trunc i64 %indvars.next to i32
+  %cmp15 = icmp ugt i32 %0, undef
+  br i1 %cmp15, label %for.body, label %loopexit
+
+loopexit:
+  ret void
+}
diff --git a/test/Transforms/LoopVectorize/write-only.ll b/test/Transforms/LoopVectorize/write-only.ll
index 54cbe8d..71a9cd0 100644
--- a/test/Transforms/LoopVectorize/write-only.ll
+++ b/test/Transforms/LoopVectorize/write-only.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
-;CHECK: @read_mod_write_single_ptr
+;CHECK-LABEL: @read_mod_write_single_ptr(
 ;CHECK: load <4 x float>
 ;CHECK: ret i32
 define i32 @read_mod_write_single_ptr(float* nocapture %a, i32 %n) nounwind uwtable ssp {
diff --git a/test/Transforms/LowerAtomic/atomic-load.ll b/test/Transforms/LowerAtomic/atomic-load.ll
index bc04e88..1279bf7 100644
--- a/test/Transforms/LowerAtomic/atomic-load.ll
+++ b/test/Transforms/LowerAtomic/atomic-load.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -loweratomic -S | FileCheck %s
 
 define i8 @add() {
-; CHECK: @add
+; CHECK-LABEL: @add(
   %i = alloca i8
   %j = atomicrmw add i8* %i, i8 42 monotonic
 ; CHECK: [[INST:%[a-z0-9]+]] = load
@@ -12,7 +12,7 @@ define i8 @add() {
 }
 
 define i8 @nand() {
-; CHECK: @nand
+; CHECK-LABEL: @nand(
   %i = alloca i8
   %j = atomicrmw nand i8* %i, i8 42 monotonic
 ; CHECK: [[INST:%[a-z0-9]+]] = load
@@ -24,7 +24,7 @@ define i8 @nand() {
 }
 
 define i8 @min() {
-; CHECK: @min
+; CHECK-LABEL: @min(
   %i = alloca i8
   %j = atomicrmw min i8* %i, i8 42 monotonic
 ; CHECK: [[INST:%[a-z0-9]+]] = load
diff --git a/test/Transforms/LowerAtomic/atomic-swap.ll b/test/Transforms/LowerAtomic/atomic-swap.ll
index 5e2f034..4331677 100644
--- a/test/Transforms/LowerAtomic/atomic-swap.ll
+++ b/test/Transforms/LowerAtomic/atomic-swap.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -loweratomic -S | FileCheck %s
 
 define i8 @cmpswap() {
-; CHECK: @cmpswap
+; CHECK-LABEL: @cmpswap(
   %i = alloca i8
   %j = cmpxchg i8* %i, i8 0, i8 42 monotonic
 ; CHECK: [[INST:%[a-z0-9]+]] = load
@@ -13,7 +13,7 @@ define i8 @cmpswap() {
 }
 
 define i8 @swap() {
-; CHECK: @swap
+; CHECK-LABEL: @swap(
   %i = alloca i8
   %j = atomicrmw xchg i8* %i, i8 42 monotonic
 ; CHECK: [[INST:%[a-z0-9]+]] = load
diff --git a/test/Transforms/LowerAtomic/barrier.ll b/test/Transforms/LowerAtomic/barrier.ll
index 814d7af..665f9d7 100644
--- a/test/Transforms/LowerAtomic/barrier.ll
+++ b/test/Transforms/LowerAtomic/barrier.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -loweratomic -S | FileCheck %s
 
 define void @barrier() {
-; CHECK: @barrier
+; CHECK-LABEL: @barrier(
   fence seq_cst
 ; CHECK-NEXT: ret
   ret void
diff --git a/test/Transforms/LowerExpectIntrinsic/basic.ll b/test/Transforms/LowerExpectIntrinsic/basic.ll
index c00127e..955209a 100644
--- a/test/Transforms/LowerExpectIntrinsic/basic.ll
+++ b/test/Transforms/LowerExpectIntrinsic/basic.ll
@@ -1,6 +1,6 @@
 ; RUN: opt -lower-expect -strip-dead-prototypes -S -o - < %s | FileCheck %s
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 define i32 @test1(i32 %x) nounwind uwtable ssp {
 entry:
   %retval = alloca i32, align 4
@@ -34,7 +34,7 @@ declare i64 @llvm.expect.i64(i64, i64) nounwind readnone
 
 declare i32 @f(...)
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 define i32 @test2(i32 %x) nounwind uwtable ssp {
 entry:
   %retval = alloca i32, align 4
@@ -62,7 +62,7 @@ return:                                           ; preds = %if.end, %if.then
   ret i32 %0
 }
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 define i32 @test3(i32 %x) nounwind uwtable ssp {
 entry:
   %retval = alloca i32, align 4
@@ -93,7 +93,7 @@ return:                                           ; preds = %if.end, %if.then
   ret i32 %0
 }
 
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 define i32 @test4(i32 %x) nounwind uwtable ssp {
 entry:
   %retval = alloca i32, align 4
@@ -125,7 +125,7 @@ return:                                           ; preds = %if.end, %if.then
   ret i32 %0
 }
 
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 define i32 @test5(i32 %x) nounwind uwtable ssp {
 entry:
   %retval = alloca i32, align 4
@@ -155,7 +155,7 @@ return:                                           ; preds = %if.end, %if.then
   ret i32 %0
 }
 
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 define i32 @test6(i32 %x) nounwind uwtable ssp {
 entry:
   %retval = alloca i32, align 4
@@ -184,7 +184,7 @@ return:                                           ; preds = %sw.epilog, %sw.bb
   ret i32 %0
 }
 
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 define i32 @test7(i32 %x) nounwind uwtable ssp {
 entry:
   %retval = alloca i32, align 4
@@ -214,7 +214,7 @@ return:                                           ; preds = %sw.epilog, %sw.bb
   ret i32 %0
 }
 
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 define i32 @test8(i32 %x) nounwind uwtable ssp {
 entry:
   %retval = alloca i32, align 4
diff --git a/test/Transforms/Mem2Reg/ConvertDebugInfo.ll b/test/Transforms/Mem2Reg/ConvertDebugInfo.ll
index c0eaaa4..5754fcd 100644
--- a/test/Transforms/Mem2Reg/ConvertDebugInfo.ll
+++ b/test/Transforms/Mem2Reg/ConvertDebugInfo.ll
@@ -35,15 +35,16 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 !llvm.dbg.cu = !{!3}
 
 !0 = metadata !{i32 786689, metadata !1, metadata !"i", metadata !2, i32 2, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"testfunc", metadata !"testfunc", metadata !"testfunc", metadata !2, i32 2, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, double (i32, double)* @testfunc, null, null, null, i32 2} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786478, metadata !12, metadata !2, metadata !"testfunc", metadata !"testfunc", metadata !"testfunc", i32 2, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, double (i32, double)* @testfunc, null, null, null, i32 2} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !12} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786449, i32 0, i32 1, metadata !"testfunc.c", metadata !"/tmp", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!3 = metadata !{i32 786449, metadata !12, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !13, metadata !13, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!4 = metadata !{i32 786453, metadata !12, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{metadata !6, metadata !7, metadata !6}
-!6 = metadata !{i32 786468, metadata !2, metadata !"double", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
-!7 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786468, metadata !12, metadata !2, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
+!7 = metadata !{i32 786468, metadata !12, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !8 = metadata !{i32 2, i32 0, metadata !1, null}
 !9 = metadata !{i32 786689, metadata !1, metadata !"j", metadata !2, i32 2, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ]
 !10 = metadata !{i32 3, i32 0, metadata !11, null}
-!11 = metadata !{i32 786443, metadata !1, i32 2, i32 0} ; [ DW_TAG_lexical_block ]
+!11 = metadata !{i32 786443, metadata !12, metadata !1, i32 2, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !12 = metadata !{metadata !"testfunc.c", metadata !"/tmp"}
+!13 = metadata !{i32 0}
diff --git a/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll b/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll
index f6119f8..49dcb04 100644
--- a/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll
+++ b/test/Transforms/Mem2Reg/ConvertDebugInfo2.ll
@@ -30,24 +30,26 @@ return:                                           ; preds = %entry
   ret void, !dbg !19
 }
 
+!llvm.dbg.cu = !{!3}
 !0 = metadata !{i32 786689, metadata !1, metadata !"a", metadata !2, i32 8, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"baz", metadata !"baz", metadata !"baz", metadata !2, i32 8, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void (i32)* @baz, null, null, null, i32 8} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 786478, metadata !20, metadata !2, metadata !"baz", metadata !"baz", metadata !"baz", i32 8, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void (i32)* @baz, null, null, null, i32 8} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !20} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786449, i32 0, i32 1, metadata !"bar.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!3 = metadata !{i32 786449, metadata !20, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !21, metadata !21, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!4 = metadata !{i32 786453, metadata !20, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !5 = metadata !{null, metadata !6}
-!6 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 786468, metadata !20, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !7 = metadata !{i32 8, i32 0, metadata !1, null}
 !8 = metadata !{i32 9, i32 0, metadata !1, null}
 !9 = metadata !{i32 786689, metadata !10, metadata !"x", metadata !2, i32 4, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ]
-!10 = metadata !{i32 786478, metadata !2, metadata !"bar", metadata !"bar", metadata !"bar", metadata !2, i32 4, metadata !11, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 4} ; [ DW_TAG_subprogram ]
-!11 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!10 = metadata !{i32 786478, metadata !20, metadata !2, metadata !"bar", metadata !"bar", metadata !"bar", i32 4, metadata !11, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 4} ; [ DW_TAG_subprogram ]
+!11 = metadata !{i32 786453, metadata !20, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !12 = metadata !{null, metadata !6, metadata !13, metadata !14}
-!13 = metadata !{i32 786468, metadata !2, metadata !"long int", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!14 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
+!13 = metadata !{i32 786468, metadata !20, metadata !2, metadata !"long int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!14 = metadata !{i32 786447, metadata !20, metadata !2, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
 !15 = metadata !{i32 4, i32 0, metadata !10, metadata !8}
 !16 = metadata !{i32 786689, metadata !10, metadata !"y", metadata !2, i32 4, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ]
 !17 = metadata !{i32 786689, metadata !10, metadata !"z", metadata !2, i32 4, metadata !14, i32 0, null} ; [ DW_TAG_arg_variable ]
 !18 = metadata !{i32 5, i32 0, metadata !10, metadata !8}
 !19 = metadata !{i32 10, i32 0, metadata !1, null}
 !20 = metadata !{metadata !"bar.c", metadata !"/tmp/"}
+!21 = metadata !{i32 0}
diff --git a/test/Transforms/Mem2Reg/atomic.ll b/test/Transforms/Mem2Reg/atomic.ll
index 982c413..5bc9e92 100644
--- a/test/Transforms/Mem2Reg/atomic.ll
+++ b/test/Transforms/Mem2Reg/atomic.ll
@@ -3,7 +3,7 @@
 ; mem2reg is allowed with arbitrary atomic operations (although we only support
 ; it for atomic load and store at the moment).
 define i32 @test1(i32 %x) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret i32 %x
   %a = alloca i32
   store atomic i32 %x, i32* %a seq_cst, align 4
diff --git a/test/Transforms/Mem2Reg/ignore-lifetime.ll b/test/Transforms/Mem2Reg/ignore-lifetime.ll
deleted file mode 100644
index 5e4f9bf..0000000
--- a/test/Transforms/Mem2Reg/ignore-lifetime.ll
+++ /dev/null
@@ -1,26 +0,0 @@
-; RUN: opt -mem2reg -S -o - < %s | FileCheck %s
-
-declare void @llvm.lifetime.start(i64 %size, i8* nocapture %ptr)
-declare void @llvm.lifetime.end(i64 %size, i8* nocapture %ptr)
-
-define void @test1() {
-; CHECK: test1
-; CHECK-NOT: alloca
-  %A = alloca i32
-  %B = bitcast i32* %A to i8*
-  call void @llvm.lifetime.start(i64 2, i8* %B)
-  store i32 1, i32* %A
-  call void @llvm.lifetime.end(i64 2, i8* %B)
-  ret void
-}
-
-define void @test2() {
-; CHECK: test2
-; CHECK-NOT: alloca
-  %A = alloca {i8, i16}
-  %B = getelementptr {i8, i16}* %A, i32 0, i32 0
-  call void @llvm.lifetime.start(i64 2, i8* %B)
-  store {i8, i16} zeroinitializer, {i8, i16}* %A
-  call void @llvm.lifetime.end(i64 2, i8* %B)
-  ret void
-}
diff --git a/test/Transforms/Mem2Reg/use-analysis.ll b/test/Transforms/Mem2Reg/use-analysis.ll
new file mode 100644
index 0000000..b08b1f1
--- /dev/null
+++ b/test/Transforms/Mem2Reg/use-analysis.ll
@@ -0,0 +1,70 @@
+; RUN: opt -mem2reg -S -o - < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
+
+declare void @llvm.lifetime.start(i64 %size, i8* nocapture %ptr)
+declare void @llvm.lifetime.end(i64 %size, i8* nocapture %ptr)
+
+define void @test1() {
+; Ensure we can look through a bitcast to i8* and the addition of lifetime
+; markers.
+;
+; CHECK-LABEL: @test1(
+; CHECK-NOT: alloca
+; CHECK: ret void
+
+  %A = alloca i32
+  %B = bitcast i32* %A to i8*
+  call void @llvm.lifetime.start(i64 2, i8* %B)
+  store i32 1, i32* %A
+  call void @llvm.lifetime.end(i64 2, i8* %B)
+  ret void
+}
+
+define void @test2() {
+; Ensure we can look through a GEP to i8* and the addition of lifetime
+; markers.
+;
+; CHECK-LABEL: @test2(
+; CHECK-NOT: alloca
+; CHECK: ret void
+
+  %A = alloca {i8, i16}
+  %B = getelementptr {i8, i16}* %A, i32 0, i32 0
+  call void @llvm.lifetime.start(i64 2, i8* %B)
+  store {i8, i16} zeroinitializer, {i8, i16}* %A
+  call void @llvm.lifetime.end(i64 2, i8* %B)
+  ret void
+}
+
+define i32 @test3(i32 %x) {
+; CHECK-LABEL: @test3(
+;
+; Check that we recursively walk the uses of the alloca and thus can see
+; through round trip bitcasts, dead bitcasts, GEPs, multiple GEPs, and lifetime
+; markers.
+entry:
+  %a = alloca i32
+; CHECK-NOT: alloca
+
+  %b = bitcast i32* %a to i8*
+  %b2 = getelementptr inbounds i8* %b, i32 0
+  %b3 = getelementptr inbounds i8* %b2, i32 0
+  call void @llvm.lifetime.start(i64 -1, i8* %b3)
+; CHECK-NOT: call void @llvm.lifetime.start
+
+  store i32 %x, i32* %a
+; CHECK-NOT: store
+
+  %dead = bitcast i32* %a to i4096*
+  %dead1 = bitcast i4096* %dead to i42*
+  %dead2 = getelementptr inbounds i32* %a, i32 %x
+; CHECK-NOT: bitcast
+; CHECK-NOT: getelementptr
+
+  %ret = load i32* %a
+; CHECK-NOT: load
+
+  ret i32 %ret
+; CHECK: ret i32 %x
+}
diff --git a/test/Transforms/MemCpyOpt/align.ll b/test/Transforms/MemCpyOpt/align.ll
index 1b98f6a..5d5bfbd 100644
--- a/test/Transforms/MemCpyOpt/align.ll
+++ b/test/Transforms/MemCpyOpt/align.ll
@@ -8,7 +8,7 @@ declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
 ; a 16-byte aligned store in the middle.
 
 define void @foo(i32* %p) {
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* {{.*}}, i8 0, i64 16, i32 4, i1 false)
   %a0 = getelementptr i32* %p, i64 0
   store i32 0, i32* %a0, align 4
@@ -24,7 +24,7 @@ define void @foo(i32* %p) {
 ; Replacing %a8 with %a4 in the memset requires boosting the alignment of %a4.
 
 define void @bar() {
-; CHECK: @bar
+; CHECK-LABEL: @bar(
 ; CHECK: %a4 = alloca i32, align 8
 ; CHECK-NOT: memcpy
   %a4 = alloca i32, align 4
diff --git a/test/Transforms/MemCpyOpt/form-memset.ll b/test/Transforms/MemCpyOpt/form-memset.ll
index f63b1dc..7c7b4fc 100644
--- a/test/Transforms/MemCpyOpt/form-memset.ll
+++ b/test/Transforms/MemCpyOpt/form-memset.ll
@@ -48,7 +48,7 @@ entry:
 	store i8 %c, i8* %tmp73, align 1
 	%tmp76 = call i32 (...)* @bar( [19 x i8]* %x ) nounwind
 	ret void
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NOT: store
 ; CHECK: call void @llvm.memset.p0i8.i64
 ; CHECK-NOT: store
@@ -150,7 +150,7 @@ entry:
 	call void @foo( %struct.MV* %up_mvd252, %struct.MV* %left_mvd253, i8* %tmp41 ) nounwind 
 	ret void
         
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NOT: store
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %tmp41, i8 -1, i64 8, i32 1, i1 false)
 ; CHECK-NOT: store
@@ -173,7 +173,7 @@ entry:
   %0 = bitcast i32* %add.ptr to i8*
   tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 11, i32 1, i1 false)
   ret void
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NOT: store
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 15, i32 4, i1 false)
 }
@@ -186,7 +186,7 @@ entry:
   %0 = bitcast i32* %add.ptr to i8*
   tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 11, i32 1, i1 false)
   ret void
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NOT: store
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 15, i32 4, i1 false)
 }
@@ -202,7 +202,7 @@ entry:
   %arrayidx = getelementptr inbounds i32* %P, i64 1
   store i32 0, i32* %arrayidx, align 4
   ret void
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NOT: store
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 15, i32 4, i1 false)
 }
@@ -216,7 +216,7 @@ entry:
   %1 = bitcast i32* %add.ptr to i8*
   tail call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 12, i32 1, i1 false)
   ret void
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %2, i8 0, i64 24, i32 1, i1 false)
 }
 
@@ -232,7 +232,7 @@ define void @test7(i32* nocapture %c) nounwind optsize {
   store i32 -1, i32* %3, align 4
   %4 = getelementptr inbounds i32* %c, i32 4
   store i32 -1, i32* %4, align 4
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* %5, i8 -1, i64 20, i32 4, i1 false)
   ret void
 }
@@ -245,7 +245,7 @@ entry:
   %0 = bitcast %struct.test8* %memtmp to <4 x i32>*
   store <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32>* %0, align 16
   ret void
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: store <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32>* %0, align 16
 }
 
@@ -269,6 +269,6 @@ define void @test9() nounwind {
   store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 14), align 2
   store i8 -1, i8* getelementptr (i8* bitcast ([16 x i64]* @test9buf to i8*), i64 15), align 1
   ret void
-; CHECK: @test9(
+; CHECK-LABEL: @test9(
 ; CHECK: call void @llvm.memset.p0i8.i64(i8* bitcast ([16 x i64]* @test9buf to i8*), i8 -1, i64 16, i32 16, i1 false)
 }
diff --git a/test/Transforms/MemCpyOpt/loadstore-sret.ll b/test/Transforms/MemCpyOpt/loadstore-sret.ll
index 67e7137..89eabca 100644
--- a/test/Transforms/MemCpyOpt/loadstore-sret.ll
+++ b/test/Transforms/MemCpyOpt/loadstore-sret.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-apple-darwin10.0.0"
 
 %"class.std::auto_ptr" = type { i32* }
 
-; CHECK: @_Z3foov
+; CHECK-LABEL: @_Z3foov(
 define void @_Z3foov(%"class.std::auto_ptr"* noalias nocapture sret %agg.result) ssp {
 _ZNSt8auto_ptrIiED1Ev.exit:
   %temp.lvalue = alloca %"class.std::auto_ptr", align 8
diff --git a/test/Transforms/MemCpyOpt/memcpy-to-memset.ll b/test/Transforms/MemCpyOpt/memcpy-to-memset.ll
index b18d176..8409de7 100644
--- a/test/Transforms/MemCpyOpt/memcpy-to-memset.ll
+++ b/test/Transforms/MemCpyOpt/memcpy-to-memset.ll
@@ -12,7 +12,7 @@ define void @test1() nounwind {
   %arraydecay = getelementptr inbounds [3 x i32]* %arr, i64 0, i64 0
   call void @foo(i32* %arraydecay) nounwind
   ret void
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: call void @llvm.memset
 ; CHECK-NOT: call void @llvm.memcpy
 ; CHECK: ret void
diff --git a/test/Transforms/MemCpyOpt/memcpy.ll b/test/Transforms/MemCpyOpt/memcpy.ll
index 148623a..2417cd1 100644
--- a/test/Transforms/MemCpyOpt/memcpy.ll
+++ b/test/Transforms/MemCpyOpt/memcpy.ll
@@ -22,7 +22,7 @@ entry:
 ; Check that one of the memcpy's are removed.
 ;; FIXME: PR 8643 We should be able to eliminate the last memcpy here.
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: call void @ccoshl
 ; CHECK: call void @llvm.memcpy
 ; CHECK-NOT: llvm.memcpy
@@ -41,7 +41,7 @@ define void @test2(i8* %P, i8* %Q) nounwind  {
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %Q, i8* %R, i32 32, i32 16, i1 false)
   ret void
         
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: call void @llvm.memmove{{.*}}(i8* %Q, i8* %P
 ; CHECK-NEXT: ret void
 }
@@ -58,7 +58,7 @@ define void @test3(%0* noalias sret %agg.result) nounwind  {
   %agg.result2 = bitcast %0* %agg.result to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %agg.result2, i8* %x.01, i32 32, i32 16, i1 false)
   ret void
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: %agg.result1 = bitcast 
 ; CHECK-NEXT: call void @llvm.memcpy
 ; CHECK-NEXT: ret void
@@ -72,7 +72,7 @@ define void @test4(i8 *%P) {
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %P, i64 8, i32 4, i1 false)
   call void @test4a(i8* align 1 byval %a)
   ret void
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NEXT: call void @test4a(
 }
 
@@ -96,7 +96,7 @@ entry:
   store i8 4, i8* %a
   call void @test5a(%struct.S* align 16 byval %y)
   ret i32 0
-  ; CHECK: @test5(
+  ; CHECK-LABEL: @test5(
   ; CHECK: store i8 4
   ; CHECK: call void @test5a(%struct.S* byval align 16 %y)
 }
@@ -105,7 +105,7 @@ entry:
 define void @test6(i8 *%P) {
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %P, i8* %P, i64 8, i32 4, i1 false)
   ret void
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: ret void
 }
 
@@ -122,7 +122,7 @@ entry:
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp, i8* %tmp1, i64 48, i32 4, i1 false)
   %call = call i32 @g(%struct.p* align 8 byval %agg.tmp) nounwind
   ret i32 %call
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: call i32 @g(%struct.p* byval align 8 %q) [[NUW:#[0-9]+]]
 }
 
diff --git a/test/Transforms/MemCpyOpt/memmove.ll b/test/Transforms/MemCpyOpt/memmove.ll
index 7f1667a..2057760 100644
--- a/test/Transforms/MemCpyOpt/memmove.ll
+++ b/test/Transforms/MemCpyOpt/memmove.ll
@@ -8,7 +8,7 @@ declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32,
 
 define i8* @test1(i8* nocapture %src) nounwind {
 entry:
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: call void @llvm.memcpy
 
   %malloccall = tail call i8* @malloc(i32 trunc (i64 mul nuw (i64 ptrtoint (i8* getelementptr (i8* null, i32 1) to i64), i64 13) to i32))
@@ -22,7 +22,7 @@ declare noalias i8* @malloc(i32)
 
 define void @test2(i8* %P) nounwind {
 entry:
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: call void @llvm.memcpy
   %add.ptr = getelementptr i8* %P, i64 16
   tail call void @llvm.memmove.p0i8.p0i8.i64(i8* %P, i8* %add.ptr, i64 16, i32 1, i1 false)
@@ -32,7 +32,7 @@ entry:
 ; This cannot be optimize because the src/dst really do overlap.
 define void @test3(i8* %P) nounwind {
 entry:
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: call void @llvm.memmove
   %add.ptr = getelementptr i8* %P, i64 16
   tail call void @llvm.memmove.p0i8.p0i8.i64(i8* %P, i8* %add.ptr, i64 17, i32 1, i1 false)
diff --git a/test/Transforms/ObjCARC/arc-annotations.ll b/test/Transforms/ObjCARC/arc-annotations.ll
index c0dea4b..f76ba3b 100644
--- a/test/Transforms/ObjCARC/arc-annotations.ll
+++ b/test/Transforms/ObjCARC/arc-annotations.ll
@@ -27,7 +27,7 @@ declare i8* @returner()
 ; Simple retain+release pair deletion, with some intervening control
 ; flow and harmless instructions.
 
-; CHECK: define void @test0(
+; CHECK-LABEL: define void @test0(
 ; CHECK: entry:
 ; CHECK:   call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_None)
 ; CHECK:   %0 = tail call i8* @objc_retain(i8* %a) #0, !llvm.arc.annotation.bottomup ![[ANN0:[0-9]+]], !llvm.arc.annotation.topdown ![[ANN1:[0-9]+]]
diff --git a/test/Transforms/ObjCARC/basic.ll b/test/Transforms/ObjCARC/basic.ll
index ca12792..12af354 100644
--- a/test/Transforms/ObjCARC/basic.ll
+++ b/test/Transforms/ObjCARC/basic.ll
@@ -177,7 +177,7 @@ if.end5:                                          ; preds = %if.then3, %if.end
   ret void
 }
 
-; CHECK: define void @test1b_imprecise(
+; CHECK-LABEL: define void @test1b_imprecise(
 ; CHECK: entry:
 ; CHECK:   tail call i8* @objc_retain(i8* %x) [[NUW:#[0-9]+]]
 ; CHECK-NOT: @objc_
@@ -210,7 +210,7 @@ if.end5:                                          ; preds = %if.then3, %if.end
 ; Like test0 but the pointer is passed to an intervening call,
 ; so the optimization is not safe.
 
-; CHECK: define void @test2_precise(
+; CHECK-LABEL: define void @test2_precise(
 ; CHECK: @objc_retain(i8* %a)
 ; CHECK: @objc_release
 ; CHECK: }
@@ -239,7 +239,7 @@ return:
   ret void
 }
 
-; CHECK: define void @test2_imprecise(
+; CHECK-LABEL: define void @test2_imprecise(
 ; CHECK: @objc_retain(i8* %a)
 ; CHECK: @objc_release
 ; CHECK: }
@@ -273,7 +273,7 @@ return:
 
 ; TODO: For now, assume this can't happen.
 
-; CHECK: define void @test3_precise(
+; CHECK-LABEL: define void @test3_precise(
 ; TODO: @objc_retain(i8* %a)
 ; TODO: @objc_release
 ; CHECK: }
@@ -293,7 +293,7 @@ return:
   ret void
 }
 
-; CHECK: define void @test3_imprecise(
+; CHECK-LABEL: define void @test3_imprecise(
 ; TODO: @objc_retain(i8* %a)
 ; TODO: @objc_release
 ; CHECK: }
@@ -319,7 +319,7 @@ return:
 ; Like test0 but the retain is in a loop,
 ; so the optimization is not safe.
 
-; CHECK: define void @test4_precise(
+; CHECK-LABEL: define void @test4_precise(
 ; TODO: @objc_retain(i8* %a)
 ; TODO: @objc_release
 ; CHECK: }
@@ -339,7 +339,7 @@ return:
   ret void
 }
 
-; CHECK: define void @test4_imprecise(
+; CHECK-LABEL: define void @test4_imprecise(
 ; TODO: @objc_retain(i8* %a)
 ; TODO: @objc_release
 ; CHECK: }
@@ -363,7 +363,7 @@ return:
 ; Like test0 but the pointer is conditionally passed to an intervening call,
 ; so the optimization is not safe.
 
-; CHECK: define void @test5a(
+; CHECK-LABEL: define void @test5a(
 ; CHECK: @objc_retain(i8*
 ; CHECK: @objc_release
 ; CHECK: }
@@ -379,7 +379,7 @@ entry:
   ret void
 }
 
-; CHECK: define void @test5b(
+; CHECK-LABEL: define void @test5b(
 ; CHECK: @objc_retain(i8*
 ; CHECK: @objc_release
 ; CHECK: }
@@ -399,7 +399,7 @@ entry:
 ; retain+release pair deletion, where the release happens on two different
 ; flow paths.
 
-; CHECK: define void @test6a(
+; CHECK-LABEL: define void @test6a(
 ; CHECK: entry:
 ; CHECK:   tail call i8* @objc_retain(
 ; CHECK: t:
@@ -433,7 +433,7 @@ return:
   ret void
 }
 
-; CHECK: define void @test6b(
+; CHECK-LABEL: define void @test6b(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test6b(i32* %x, i1 %p) nounwind {
@@ -461,7 +461,7 @@ return:
   ret void
 }
 
-; CHECK: define void @test6c(
+; CHECK-LABEL: define void @test6c(
 ; CHECK: entry:
 ; CHECK:   tail call i8* @objc_retain(
 ; CHECK: t:
@@ -495,7 +495,7 @@ return:
   ret void
 }
 
-; CHECK: define void @test6d(
+; CHECK-LABEL: define void @test6d(
 ; CHECK: entry:
 ; CHECK:   tail call i8* @objc_retain(
 ; CHECK: t:
@@ -533,7 +533,7 @@ return:
 ; retain+release pair deletion, where the retain happens on two different
 ; flow paths.
 
-; CHECK:     define void @test7(
+; CHECK-LABEL:     define void @test7(
 ; CHECK:     entry:
 ; CHECK-NOT:   objc_
 ; CHECK:     t:
@@ -567,7 +567,7 @@ return:
   ret void
 }
 
-; CHECK: define void @test7b(
+; CHECK-LABEL: define void @test7b(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test7b(i32* %x, i1 %p) nounwind {
@@ -596,7 +596,7 @@ return:
 
 ; Like test7, but there's a retain/retainBlock mismatch. Don't delete!
 
-; CHECK: define void @test7c
+; CHECK-LABEL: define void @test7c(
 ; CHECK: t:
 ; CHECK:   call i8* @objc_retainBlock
 ; CHECK: f:
@@ -631,7 +631,7 @@ return:
 ; retain+release pair deletion, where the retain and release both happen on
 ; different flow paths. Wild!
 
-; CHECK: define void @test8a(
+; CHECK-LABEL: define void @test8a(
 ; CHECK: entry:
 ; CHECK: t:
 ; CHECK:   @objc_retain
@@ -679,7 +679,7 @@ return:
   ret void
 }
 
-; CHECK: define void @test8b(
+; CHECK-LABEL: define void @test8b(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test8b(i32* %x, i1 %p, i1 %q) nounwind {
@@ -717,7 +717,7 @@ return:
   ret void
 }
 
-; CHECK: define void @test8c(
+; CHECK-LABEL: define void @test8c(
 ; CHECK: entry:
 ; CHECK: t:
 ; CHECK:   @objc_retain
@@ -765,7 +765,7 @@ return:
   ret void
 }
 
-; CHECK: define void @test8d(
+; CHECK-LABEL: define void @test8d(
 ; CHECK: entry:
 ; CHECK: t:
 ; CHECK:   @objc_retain
@@ -815,7 +815,7 @@ return:
 
 ; Trivial retain+release pair deletion.
 
-; CHECK: define void @test9(
+; CHECK-LABEL: define void @test9(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test9(i8* %x) nounwind {
@@ -827,7 +827,7 @@ entry:
 
 ; Retain+release pair, but on an unknown pointer relationship. Don't delete!
 
-; CHECK: define void @test9b
+; CHECK-LABEL: define void @test9b(
 ; CHECK: @objc_retain(i8* %x)
 ; CHECK: @objc_release(i8* %s)
 ; CHECK: }
@@ -841,7 +841,7 @@ entry:
 
 ; Trivial retain+release pair with intervening calls - don't delete!
 
-; CHECK: define void @test10(
+; CHECK-LABEL: define void @test10(
 ; CHECK: @objc_retain(i8* %x)
 ; CHECK: @callee
 ; CHECK: @use_pointer
@@ -860,7 +860,7 @@ entry:
 ; Also, add a tail keyword, since objc_retain can never be passed
 ; a stack argument.
 
-; CHECK: define void @test11(
+; CHECK-LABEL: define void @test11(
 ; CHECK: tail call i8* @objc_retain(i8* %x) [[NUW]]
 ; CHECK: call i8* @objc_autorelease(i8* %0) [[NUW]]
 ; CHECK: }
@@ -874,7 +874,7 @@ entry:
 
 ; Same as test11 but with no use_pointer call. Delete the pair!
 
-; CHECK: define void @test11a(
+; CHECK-LABEL: define void @test11a(
 ; CHECK: entry:
 ; CHECK-NEXT: ret void
 ; CHECK: }
@@ -889,7 +889,7 @@ entry:
 ; since if the frontend emitted code for an __autoreleasing variable, we may
 ; want it to be in the autorelease pool.
 
-; CHECK: define i8* @test11b(
+; CHECK-LABEL: define i8* @test11b(
 ; CHECK: tail call i8* @objc_retain(i8* %x) [[NUW]]
 ; CHECK: call i8* @objc_autorelease(i8* %0) [[NUW]]
 ; CHECK: }
@@ -903,7 +903,7 @@ entry:
 ; Trivial retain,release pair with intervening call, but it's dominated
 ; by another retain - delete!
 
-; CHECK: define void @test12(
+; CHECK-LABEL: define void @test12(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: @objc_retain(i8* %x)
 ; CHECK-NOT: @objc_
@@ -920,7 +920,7 @@ entry:
 
 ; Trivial retain,autorelease pair. Don't delete!
 
-; CHECK: define void @test13(
+; CHECK-LABEL: define void @test13(
 ; CHECK: tail call i8* @objc_retain(i8* %x) [[NUW]]
 ; CHECK: tail call i8* @objc_retain(i8* %x) [[NUW]]
 ; CHECK: @use_pointer(i8* %x)
@@ -937,7 +937,7 @@ entry:
 
 ; Delete the retain+release pair.
 
-; CHECK: define void @test13b
+; CHECK-LABEL: define void @test13b(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: @objc_retain(i8* %x)
 ; CHECK-NEXT: @use_pointer
@@ -957,7 +957,7 @@ entry:
 ; Don't delete the retain+release pair because there's an
 ; autoreleasePoolPop in the way.
 
-; CHECK: define void @test13c
+; CHECK-LABEL: define void @test13c(
 ; CHECK: @objc_retain(i8* %x)
 ; CHECK: @objc_autoreleasePoolPop
 ; CHECK: @objc_retain(i8* %x)
@@ -978,7 +978,7 @@ entry:
 ; Like test13c, but there's an autoreleasePoolPush in the way, but that
 ; doesn't matter.
 
-; CHECK: define void @test13d
+; CHECK-LABEL: define void @test13d(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: @objc_retain(i8* %x)
 ; CHECK-NEXT: @objc_autoreleasePoolPush
@@ -1000,7 +1000,7 @@ entry:
 ; Trivial retain,release pair with intervening call, but it's post-dominated
 ; by another release - delete!
 
-; CHECK: define void @test14(
+; CHECK-LABEL: define void @test14(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: @use_pointer
 ; CHECK-NEXT: @use_pointer
@@ -1020,7 +1020,7 @@ entry:
 ; Trivial retain,autorelease pair with intervening call, but it's post-dominated
 ; by another release. Don't delete anything.
 
-; CHECK: define void @test15(
+; CHECK-LABEL: define void @test15(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: @objc_retain(i8* %x)
 ; CHECK-NEXT: @use_pointer
@@ -1040,7 +1040,7 @@ entry:
 ; Trivial retain,autorelease pair, post-dominated
 ; by another release. Delete the retain and release.
 
-; CHECK: define void @test15b
+; CHECK-LABEL: define void @test15b(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: @objc_retain
 ; CHECK-NEXT: @objc_autorelease
@@ -1055,7 +1055,7 @@ entry:
   ret void
 }
 
-; CHECK: define void @test15c
+; CHECK-LABEL: define void @test15c(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: @objc_autorelease
 ; CHECK-NEXT: ret void
@@ -1070,7 +1070,7 @@ entry:
 
 ; Retain+release pairs in diamonds, all dominated by a retain.
 
-; CHECK: define void @test16a(
+; CHECK-LABEL: define void @test16a(
 ; CHECK: @objc_retain(i8* %x)
 ; CHECK-NOT: @objc
 ; CHECK: }
@@ -1104,7 +1104,7 @@ purple:
   ret void
 }
 
-; CHECK: define void @test16b(
+; CHECK-LABEL: define void @test16b(
 ; CHECK: @objc_retain(i8* %x)
 ; CHECK-NOT: @objc
 ; CHECK: }
@@ -1138,7 +1138,7 @@ purple:
   ret void
 }
 
-; CHECK: define void @test16c(
+; CHECK-LABEL: define void @test16c(
 ; CHECK: @objc_retain(i8* %x)
 ; CHECK-NOT: @objc
 ; CHECK: }
@@ -1172,7 +1172,7 @@ purple:
   ret void
 }
 
-; CHECK: define void @test16d(
+; CHECK-LABEL: define void @test16d(
 ; CHECK: @objc_retain(i8* %x)
 ; CHECK-NOT: @objc
 ; CHECK: }
@@ -1209,7 +1209,7 @@ purple:
 
 ; Retain+release pairs in diamonds, all post-dominated by a release.
 
-; CHECK: define void @test17(
+; CHECK-LABEL: define void @test17(
 ; CHECK-NOT: @objc_
 ; CHECK: purple:
 ; CHECK: @objc_release
@@ -1246,7 +1246,7 @@ purple:
 
 ; Delete no-ops.
 
-; CHECK: define void @test18(
+; CHECK-LABEL: define void @test18(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test18() {
@@ -1258,7 +1258,7 @@ define void @test18() {
 
 ; Delete no-ops where undef can be assumed to be null.
 
-; CHECK: define void @test18b
+; CHECK-LABEL: define void @test18b(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test18b() {
@@ -1294,7 +1294,7 @@ entry:
 
 ; Bitcast insertion
 
-; CHECK: define void @test20(
+; CHECK-LABEL: define void @test20(
 ; CHECK: %tmp1 = tail call i8* @objc_retain(i8* %tmp) [[NUW]]
 ; CHECK-NEXT: invoke
 ; CHECK: }
@@ -1322,7 +1322,7 @@ if.end:                                           ; preds = %invoke.cont23
 ; Delete a redundant retain,autorelease when forwaring a call result
 ; directly to a return value.
 
-; CHECK: define i8* @test21(
+; CHECK-LABEL: define i8* @test21(
 ; CHECK: call i8* @returner()
 ; CHECK-NEXT: ret i8* %call
 ; CHECK-NEXT: }
@@ -1336,7 +1336,7 @@ entry:
 
 ; Move an objc call up through a phi that has null operands.
 
-; CHECK: define void @test22(
+; CHECK-LABEL: define void @test22(
 ; CHECK: B:
 ; CHECK:   %1 = bitcast double* %p to i8*
 ; CHECK:   call void @objc_release(i8* %1)
@@ -1359,7 +1359,7 @@ C:
 
 ; Optimize objc_retainBlock.
 
-; CHECK: define void @test23(
+; CHECK-LABEL: define void @test23(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 %block0 = type { i64, i64, i8*, i8* }
@@ -1393,7 +1393,7 @@ entry:
 
 ; Don't optimize objc_retainBlock, because there's no copy_on_escape metadata.
 
-; CHECK: define void @test23c(
+; CHECK-LABEL: define void @test23c(
 ; CHECK: @objc_retainBlock
 ; CHECK: @objc_release
 ; CHECK: }
@@ -1408,7 +1408,7 @@ entry:
 
 ; Any call can decrement a retain count.
 
-; CHECK: define void @test24(
+; CHECK-LABEL: define void @test24(
 ; CHECK: @objc_retain(i8* %a)
 ; CHECK: @objc_release
 ; CHECK: }
@@ -1423,7 +1423,7 @@ define void @test24(i8* %r, i8* %a) {
 ; Don't move a retain/release pair if the release can be moved
 ; but the retain can't be moved to balance it.
 
-; CHECK: define void @test25(
+; CHECK-LABEL: define void @test25(
 ; CHECK: entry:
 ; CHECK:   call i8* @objc_retain(i8* %p)
 ; CHECK: true:
@@ -1448,7 +1448,7 @@ done:
 ; Don't move a retain/release pair if the retain can be moved
 ; but the release can't be moved to balance it.
 
-; CHECK: define void @test26(
+; CHECK-LABEL: define void @test26(
 ; CHECK: entry:
 ; CHECK:   call i8* @objc_retain(i8* %p)
 ; CHECK: true:
@@ -1472,7 +1472,7 @@ done:
 
 ; Don't sink the retain,release into the loop.
 
-; CHECK: define void @test27(
+; CHECK-LABEL: define void @test27(
 ; CHECK: entry:
 ; CHECK: call i8* @objc_retain(i8* %p)
 ; CHECK: loop:
@@ -1497,7 +1497,7 @@ done:
 
 ; Trivial code motion case: Triangle.
 
-; CHECK: define void @test28(
+; CHECK-LABEL: define void @test28(
 ; CHECK-NOT: @objc_
 ; CHECK: true:
 ; CHECK: call i8* @objc_retain(
@@ -1525,7 +1525,7 @@ done:
 ; Trivial code motion case: Triangle, but no metadata. Don't move past
 ; unrelated memory references!
 
-; CHECK: define void @test28b
+; CHECK-LABEL: define void @test28b(
 ; CHECK: call i8* @objc_retain(
 ; CHECK: true:
 ; CHECK-NOT: @objc_
@@ -1555,7 +1555,7 @@ done:
 ; Trivial code motion case: Triangle, with metadata. Do move past
 ; unrelated memory references! And preserve the metadata.
 
-; CHECK: define void @test28c
+; CHECK-LABEL: define void @test28c(
 ; CHECK-NOT: @objc_
 ; CHECK: true:
 ; CHECK: call i8* @objc_retain(
@@ -1583,7 +1583,7 @@ done:
 
 ; Like test28. but with two releases.
 
-; CHECK: define void @test29(
+; CHECK-LABEL: define void @test29(
 ; CHECK-NOT: @objc_
 ; CHECK: true:
 ; CHECK: call i8* @objc_retain(
@@ -1618,7 +1618,7 @@ ohno:
 ; Basic case with the use and call in a diamond
 ; with an extra release.
 
-; CHECK: define void @test30(
+; CHECK-LABEL: define void @test30(
 ; CHECK-NOT: @objc_
 ; CHECK: true:
 ; CHECK: call i8* @objc_retain(
@@ -1657,7 +1657,7 @@ ohno:
 
 ; Basic case with a mergeable release.
 
-; CHECK: define void @test31(
+; CHECK-LABEL: define void @test31(
 ; CHECK: call i8* @objc_retain(i8* %p)
 ; CHECK: call void @callee()
 ; CHECK: store
@@ -1686,7 +1686,7 @@ false:
 
 ; Don't consider bitcasts or getelementptrs direct uses.
 
-; CHECK: define void @test32(
+; CHECK-LABEL: define void @test32(
 ; CHECK-NOT: @objc_
 ; CHECK: true:
 ; CHECK: call i8* @objc_retain(
@@ -1715,7 +1715,7 @@ done:
 
 ; Do consider icmps to be direct uses.
 
-; CHECK: define void @test33(
+; CHECK-LABEL: define void @test33(
 ; CHECK-NOT: @objc_
 ; CHECK: true:
 ; CHECK: call i8* @objc_retain(
@@ -1745,7 +1745,7 @@ done:
 ; Delete retain,release if there's just a possible dec and we have imprecise
 ; releases.
 
-; CHECK: define void @test34a(
+; CHECK-LABEL: define void @test34a(
 ; CHECK:   call i8* @objc_retain
 ; CHECK: true:
 ; CHECK: done:
@@ -1767,7 +1767,7 @@ done:
   ret void
 }
 
-; CHECK: define void @test34b(
+; CHECK-LABEL: define void @test34b(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test34b(i8* %p, i1 %x, i8* %y) {
@@ -1791,7 +1791,7 @@ done:
 ; release.
 
 ; Precise.
-; CHECK: define void @test35a(
+; CHECK-LABEL: define void @test35a(
 ; CHECK: entry:
 ; CHECK:   call i8* @objc_retain
 ; CHECK: true:
@@ -1815,7 +1815,7 @@ done:
 }
 
 ; Imprecise.
-; CHECK: define void @test35b(
+; CHECK-LABEL: define void @test35b(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test35b(i8* %p, i1 %x, i8* %y) {
@@ -1836,7 +1836,7 @@ done:
 
 ; Delete a retain,release if there's no actual use and we have precise release.
 
-; CHECK: define void @test36a(
+; CHECK-LABEL: define void @test36a(
 ; CHECK: @objc_retain
 ; CHECK: call void @callee()
 ; CHECK-NOT: @objc_
@@ -1854,7 +1854,7 @@ entry:
 
 ; Like test36, but with metadata.
 
-; CHECK: define void @test36b(
+; CHECK-LABEL: define void @test36b(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test36b(i8* %p) {
@@ -1868,7 +1868,7 @@ entry:
 
 ; Be aggressive about analyzing phis to eliminate possible uses.
 
-; CHECK: define void @test38(
+; CHECK-LABEL: define void @test38(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test38(i8* %p, i1 %u, i1 %m, i8* %z, i8* %y, i8* %x, i8* %w) {
@@ -1902,7 +1902,7 @@ g:
 
 ; Delete retain,release pairs around loops.
 
-; CHECK: define void @test39(
+; CHECK-LABEL: define void @test39(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test39(i8* %p) {
@@ -1920,7 +1920,7 @@ exit:                                             ; preds = %loop
 
 ; Delete retain,release pairs around loops containing uses.
 
-; CHECK: define void @test39b(
+; CHECK-LABEL: define void @test39b(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test39b(i8* %p) {
@@ -1939,7 +1939,7 @@ exit:                                             ; preds = %loop
 
 ; Delete retain,release pairs around loops containing potential decrements.
 
-; CHECK: define void @test39c(
+; CHECK-LABEL: define void @test39c(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test39c(i8* %p) {
@@ -1959,7 +1959,7 @@ exit:                                             ; preds = %loop
 ; Delete retain,release pairs around loops even if
 ; the successors are in a different order.
 
-; CHECK: define void @test40(
+; CHECK-LABEL: define void @test40(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test40(i8* %p) {
@@ -1979,7 +1979,7 @@ exit:                                             ; preds = %loop
 ; Do the known-incremented retain+release elimination even if the pointer
 ; is also autoreleased.
 
-; CHECK: define void @test42(
+; CHECK-LABEL: define void @test42(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: call i8* @objc_retain(i8* %p)
 ; CHECK-NEXT: call i8* @objc_autorelease(i8* %p)
@@ -2001,7 +2001,7 @@ entry:
 ; Don't the known-incremented retain+release elimination if the pointer is
 ; autoreleased and there's an autoreleasePoolPop.
 
-; CHECK: define void @test43(
+; CHECK-LABEL: define void @test43(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: call i8* @objc_retain(i8* %p)
 ; CHECK-NEXT: call i8* @objc_autorelease(i8* %p)
@@ -2027,7 +2027,7 @@ entry:
 ; Do the known-incremented retain+release elimination if the pointer is
 ; autoreleased and there's an autoreleasePoolPush.
 
-; CHECK: define void @test43b
+; CHECK-LABEL: define void @test43b(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: call i8* @objc_retain(i8* %p)
 ; CHECK-NEXT: call i8* @objc_autorelease(i8* %p)
@@ -2050,7 +2050,7 @@ entry:
 
 ; Do retain+release elimination for non-provenance pointers.
 
-; CHECK: define void @test44(
+; CHECK-LABEL: define void @test44(
 ; CHECK-NOT: objc_
 ; CHECK: }
 define void @test44(i8** %pp) {
@@ -2063,7 +2063,7 @@ define void @test44(i8** %pp) {
 ; Don't delete retain+release with an unknown-provenance
 ; may-alias objc_release between them.
 
-; CHECK: define void @test45(
+; CHECK-LABEL: define void @test45(
 ; CHECK: call i8* @objc_retain(i8* %p)
 ; CHECK: call void @objc_release(i8* %q)
 ; CHECK: call void @use_pointer(i8* %p)
@@ -2081,7 +2081,7 @@ define void @test45(i8** %pp, i8** %qq) {
 
 ; Don't delete retain and autorelease here.
 
-; CHECK: define void @test46(
+; CHECK-LABEL: define void @test46(
 ; CHECK: tail call i8* @objc_retain(i8* %p) [[NUW]]
 ; CHECK: true:
 ; CHECK: call i8* @objc_autorelease(i8* %p) [[NUW]]
@@ -2102,7 +2102,7 @@ false:
 
 ; Delete no-op cast calls.
 
-; CHECK: define i8* @test47(
+; CHECK-LABEL: define i8* @test47(
 ; CHECK-NOT: call
 ; CHECK: ret i8* %p
 ; CHECK: }
@@ -2113,7 +2113,7 @@ define i8* @test47(i8* %p) nounwind {
 
 ; Delete no-op cast calls.
 
-; CHECK: define i8* @test48(
+; CHECK-LABEL: define i8* @test48(
 ; CHECK-NOT: call
 ; CHECK: ret i8* %p
 ; CHECK: }
@@ -2124,7 +2124,7 @@ define i8* @test48(i8* %p) nounwind {
 
 ; Delete no-op cast calls.
 
-; CHECK: define i8* @test49(
+; CHECK-LABEL: define i8* @test49(
 ; CHECK-NOT: call
 ; CHECK: ret i8* %p
 ; CHECK: }
@@ -2136,7 +2136,7 @@ define i8* @test49(i8* %p) nounwind {
 ; Do delete retain+release with intervening stores of the address value if we
 ; have imprecise release attached to objc_release.
 
-; CHECK:      define void @test50a(
+; CHECK-LABEL:      define void @test50a(
 ; CHECK-NEXT:   call i8* @objc_retain
 ; CHECK-NEXT:   call void @callee
 ; CHECK-NEXT:   store
@@ -2151,7 +2151,7 @@ define void @test50a(i8* %p, i8** %pp) {
   ret void
 }
 
-; CHECK: define void @test50b(
+; CHECK-LABEL: define void @test50b(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test50b(i8* %p, i8** %pp) {
@@ -2166,7 +2166,7 @@ define void @test50b(i8* %p, i8** %pp) {
 ; Don't delete retain+release with intervening stores through the
 ; address value.
 
-; CHECK: define void @test51a(
+; CHECK-LABEL: define void @test51a(
 ; CHECK: call i8* @objc_retain(i8* %p)
 ; CHECK: call void @objc_release(i8* %p)
 ; CHECK: ret void
@@ -2179,7 +2179,7 @@ define void @test51a(i8* %p) {
   ret void
 }
 
-; CHECK: define void @test51b(
+; CHECK-LABEL: define void @test51b(
 ; CHECK: call i8* @objc_retain(i8* %p)
 ; CHECK: call void @objc_release(i8* %p)
 ; CHECK: ret void
@@ -2195,7 +2195,7 @@ define void @test51b(i8* %p) {
 ; Don't delete retain+release with intervening use of a pointer of
 ; unknown provenance.
 
-; CHECK: define void @test52a(
+; CHECK-LABEL: define void @test52a(
 ; CHECK: call i8* @objc_retain
 ; CHECK: call void @callee()
 ; CHECK: call void @use_pointer(i8* %z)
@@ -2212,7 +2212,7 @@ define void @test52a(i8** %zz, i8** %pp) {
   ret void
 }
 
-; CHECK: define void @test52b(
+; CHECK-LABEL: define void @test52b(
 ; CHECK: call i8* @objc_retain
 ; CHECK: call void @callee()
 ; CHECK: call void @use_pointer(i8* %z)
@@ -2234,7 +2234,7 @@ define void @test52b(i8** %zz, i8** %pp) {
 ; Oops. That's wrong. Clang sometimes uses function types gratuitously.
 ; See rdar://10551239.
 
-; CHECK: define void @test53(
+; CHECK-LABEL: define void @test53(
 ; CHECK: @objc_
 ; CHECK: }
 define void @test53(void ()** %zz, i8** %pp) {
@@ -2249,7 +2249,7 @@ define void @test53(void ()** %zz, i8** %pp) {
 
 ; Convert autorelease to release if the value is unused.
 
-; CHECK: define void @test54(
+; CHECK-LABEL: define void @test54(
 ; CHECK: call i8* @returner()
 ; CHECK-NEXT: call void @objc_release(i8* %t) [[NUW]], !clang.imprecise_release !0
 ; CHECK-NEXT: ret void
@@ -2262,7 +2262,7 @@ define void @test54() {
 
 ; Nested retain+release pairs. Delete them both.
 
-; CHECK: define void @test55(
+; CHECK-LABEL: define void @test55(
 ; CHECK-NOT: @objc
 ; CHECK: }
 define void @test55(i8* %x) { 
@@ -2279,7 +2279,7 @@ entry:
 ; can be partially eliminated. Plus an extra outer pair to
 ; eliminate, for fun.
 
-; CHECK: define void @test56(
+; CHECK-LABEL: define void @test56(
 ; CHECK-NOT: @objc
 ; CHECK: if.then:
 ; CHECK-NEXT: %0 = tail call i8* @objc_retain(i8* %x) [[NUW]]
@@ -2313,7 +2313,7 @@ if.end:                                           ; preds = %entry, %if.then
 ; known unnecessary because the presence of the second one means that
 ; the first one won't be deleting the object.
 
-; CHECK:      define void @test57(
+; CHECK-LABEL:      define void @test57(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   call void @use_pointer(i8* %x)
 ; CHECK-NEXT:   call void @use_pointer(i8* %x)
@@ -2339,7 +2339,7 @@ entry:
 ; An adjacent retain+release pair is sufficient even if it will be
 ; removed itself.
 
-; CHECK:      define void @test58(
+; CHECK-LABEL:      define void @test58(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   call void @use_pointer(i8* %x)
 ; CHECK-NEXT:   call void @use_pointer(i8* %x)
@@ -2358,7 +2358,7 @@ entry:
 
 ; Don't delete the second retain+release pair in an adjacent set.
 
-; CHECK:      define void @test59(
+; CHECK-LABEL:      define void @test59(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   %0 = tail call i8* @objc_retain(i8* %x) [[NUW]]
 ; CHECK-NEXT:   call void @use_pointer(i8* %x)
@@ -2385,7 +2385,7 @@ entry:
 ; We have a precise lifetime retain/release here. We can not remove them since
 ; @something is not constant.
 
-; CHECK: define void @test60a(
+; CHECK-LABEL: define void @test60a(
 ; CHECK: call i8* @objc_retain
 ; CHECK: call void @objc_release
 ; CHECK: }
@@ -2399,7 +2399,7 @@ define void @test60a() {
   ret void
 }
 
-; CHECK: define void @test60b(
+; CHECK-LABEL: define void @test60b(
 ; CHECK: call i8* @objc_retain
 ; CHECK-NOT: call i8* @objc_retain
 ; CHECK-NOT: call i8* @objc_rrelease
@@ -2415,7 +2415,7 @@ define void @test60b() {
   ret void
 }
 
-; CHECK: define void @test60c(
+; CHECK-LABEL: define void @test60c(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test60c() {
@@ -2428,7 +2428,7 @@ define void @test60c() {
   ret void
 }
 
-; CHECK: define void @test60d(
+; CHECK-LABEL: define void @test60d(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test60d() {
@@ -2441,7 +2441,7 @@ define void @test60d() {
   ret void
 }
 
-; CHECK: define void @test60e(
+; CHECK-LABEL: define void @test60e(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test60e() {
@@ -2457,7 +2457,7 @@ define void @test60e() {
 ; Constant pointers to objects don't need to be considered related to other
 ; pointers.
 
-; CHECK: define void @test61(
+; CHECK-LABEL: define void @test61(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test61() {
@@ -2472,7 +2472,7 @@ define void @test61() {
 ; Delete a retain matched by releases when one is inside the loop and the
 ; other is outside the loop.
 
-; CHECK: define void @test62(
+; CHECK-LABEL: define void @test62(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test62(i8* %x, i1* %p) nounwind {
@@ -2496,7 +2496,7 @@ exit:
 ; Like test62 but with no release in exit.
 ; Don't delete anything!
 
-; CHECK: define void @test63(
+; CHECK-LABEL: define void @test63(
 ; CHECK: loop:
 ; CHECK:   tail call i8* @objc_retain(i8* %x)
 ; CHECK: loop.more:
@@ -2522,7 +2522,7 @@ exit:
 ; Like test62 but with no release in loop.more.
 ; Don't delete anything!
 
-; CHECK: define void @test64(
+; CHECK-LABEL: define void @test64(
 ; CHECK: loop:
 ; CHECK:   tail call i8* @objc_retain(i8* %x)
 ; CHECK: exit:
@@ -2547,7 +2547,7 @@ exit:
 
 ; Move an autorelease past a phi with a null.
 
-; CHECK: define i8* @test65(
+; CHECK-LABEL: define i8* @test65(
 ; CHECK: if.then:
 ; CHECK:   call i8* @objc_autorelease(
 ; CHECK: return:
@@ -2570,7 +2570,7 @@ return:                                           ; preds = %if.then, %entry
 
 ; Don't move an autorelease past an autorelease pool boundary.
 
-; CHECK: define i8* @test65b(
+; CHECK-LABEL: define i8* @test65b(
 ; CHECK: if.then:
 ; CHECK-NOT: @objc_autorelease
 ; CHECK: return:
@@ -2596,7 +2596,7 @@ return:                                           ; preds = %if.then, %entry
 ; Don't move an autoreleaseReuturnValue, which would break
 ; the RV optimization.
 
-; CHECK: define i8* @test65c(
+; CHECK-LABEL: define i8* @test65c(
 ; CHECK: if.then:
 ; CHECK-NOT: @objc_autorelease
 ; CHECK: return:
@@ -2620,7 +2620,7 @@ return:                                           ; preds = %if.then, %entry
 ; An objc_retain can serve as a may-use for a different pointer.
 ; rdar://11931823
 
-; CHECK: define void @test66a(
+; CHECK-LABEL: define void @test66a(
 ; CHECK:   tail call i8* @objc_retain(i8* %cond) [[NUW]]
 ; CHECK:   tail call void @objc_release(i8* %call) [[NUW]]
 ; CHECK:   tail call i8* @objc_retain(i8* %tmp8) [[NUW]]
@@ -2643,7 +2643,7 @@ cond.end:                                         ; preds = %cond.true, %entry
   ret void
 }
 
-; CHECK: define void @test66b(
+; CHECK-LABEL: define void @test66b(
 ; CHECK:   tail call i8* @objc_retain(i8* %cond) [[NUW]]
 ; CHECK:   tail call void @objc_release(i8* %call) [[NUW]]
 ; CHECK:   tail call i8* @objc_retain(i8* %tmp8) [[NUW]]
@@ -2666,7 +2666,7 @@ cond.end:                                         ; preds = %cond.true, %entry
   ret void
 }
 
-; CHECK: define void @test66c(
+; CHECK-LABEL: define void @test66c(
 ; CHECK:   tail call i8* @objc_retain(i8* %cond) [[NUW]]
 ; CHECK:   tail call void @objc_release(i8* %call) [[NUW]]
 ; CHECK:   tail call i8* @objc_retain(i8* %tmp8) [[NUW]]
@@ -2689,7 +2689,7 @@ cond.end:                                         ; preds = %cond.true, %entry
   ret void
 }
 
-; CHECK: define void @test66d(
+; CHECK-LABEL: define void @test66d(
 ; CHECK:   tail call i8* @objc_retain(i8* %cond) [[NUW]]
 ; CHECK:   tail call void @objc_release(i8* %call) [[NUW]]
 ; CHECK:   tail call i8* @objc_retain(i8* %tmp8) [[NUW]]
@@ -3037,9 +3037,28 @@ end:                                              ; preds = %if.end125, %if.end1
   ret void
 }
 
-!0 = metadata !{}
-
 declare i32 @__gxx_personality_v0(...)
 
+declare i32 @objc_sync_enter(i8*)
+declare i32 @objc_sync_exit(i8*)
+
+; Make sure that we understand that objc_sync_{enter,exit} are IC_User not
+; IC_Call/IC_CallOrUser.
+
+; CHECK-LABEL:      define void @test67(
+; CHECK-NEXT:   call i32 @objc_sync_enter(i8* %x)
+; CHECK-NEXT:   call i32 @objc_sync_exit(i8* %x)
+; CHECK-NEXT:   ret void
+; CHECK-NEXT: }
+define void @test67(i8* %x) {
+  call i8* @objc_retain(i8* %x)
+  call i32 @objc_sync_enter(i8* %x)
+  call i32 @objc_sync_exit(i8* %x)
+  call void @objc_release(i8* %x), !clang.imprecise_release !0
+  ret void
+}
+
+!0 = metadata !{}
+
 ; CHECK: attributes #0 = { nounwind readnone }
 ; CHECK: attributes [[NUW]] = { nounwind }
diff --git a/test/Transforms/ObjCARC/cfg-hazards.ll b/test/Transforms/ObjCARC/cfg-hazards.ll
index 0156d5b..61e5a3b 100644
--- a/test/Transforms/ObjCARC/cfg-hazards.ll
+++ b/test/Transforms/ObjCARC/cfg-hazards.ll
@@ -10,7 +10,7 @@ declare void @objc_release(i8*)
 declare void @callee()
 declare void @block_callee(void ()*)
 
-; CHECK: define void @test0(
+; CHECK-LABEL: define void @test0(
 ; CHECK:   call i8* @objc_retain(
 ; CHECK: for.body:
 ; CHECK-NOT: @objc
@@ -35,7 +35,7 @@ for.end:                                          ; preds = %for.body
   ret void
 }
 
-; CHECK: define void @test1(
+; CHECK-LABEL: define void @test1(
 ; CHECK:   call i8* @objc_retain(
 ; CHECK: for.body:
 ; CHECK-NOT: @objc
@@ -60,7 +60,7 @@ for.end:                                          ; preds = %for.body
   ret void
 }
 
-; CHECK: define void @test2(
+; CHECK-LABEL: define void @test2(
 ; CHECK:   call i8* @objc_retain(
 ; CHECK: for.body:
 ; CHECK-NOT: @objc
diff --git a/test/Transforms/ObjCARC/contract-storestrong.ll b/test/Transforms/ObjCARC/contract-storestrong.ll
index 023604e..50a2d97 100644
--- a/test/Transforms/ObjCARC/contract-storestrong.ll
+++ b/test/Transforms/ObjCARC/contract-storestrong.ll
@@ -8,7 +8,7 @@ declare void @use_pointer(i8*)
 
 @x = external global i8*
 
-; CHECK: define void @test0(
+; CHECK-LABEL: define void @test0(
 ; CHECK: entry:
 ; CHECK-NEXT: tail call void @objc_storeStrong(i8** @x, i8* %p) [[NUW:#[0-9]+]]
 ; CHECK-NEXT: ret void
@@ -137,7 +137,7 @@ entry:
 
 ; Like test0, but there's no store, so don't form an objc_storeStrong.
 
-;      CHECK: define void @test7(
+;      CHECK-LABEL: define void @test7(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   %0 = tail call i8* @objc_retain(i8* %p) [[NUW]]
 ; CHECK-NEXT:   %tmp = load i8** @x, align 8
@@ -154,7 +154,7 @@ entry:
 
 ; Like test0, but there's no retain, so don't form an objc_storeStrong.
 
-;      CHECK: define void @test8(
+;      CHECK-LABEL: define void @test8(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   %tmp = load i8** @x, align 8
 ; CHECK-NEXT:   store i8* %p, i8** @x, align 8
diff --git a/test/Transforms/ObjCARC/contract-testcases.ll b/test/Transforms/ObjCARC/contract-testcases.ll
index fc023f8..0bf63a6 100644
--- a/test/Transforms/ObjCARC/contract-testcases.ll
+++ b/test/Transforms/ObjCARC/contract-testcases.ll
@@ -18,7 +18,7 @@ declare i32 @__gxx_personality_sj0(...)
 
 ; Don't get in trouble on bugpointed code.
 
-; CHECK: define void @test0(
+; CHECK-LABEL: define void @test0(
 define void @test0() {
 bb:
   %tmp = bitcast %4* undef to i8*
@@ -45,7 +45,7 @@ bb6:                                              ; preds = %bb5, %bb4, %bb4, %b
 ; When rewriting operands for a phi which has multiple operands
 ; for the same block, use the exactly same value in each block.
 
-; CHECK: define void @test1(
+; CHECK-LABEL: define void @test1(
 ; CHECK: %0 = bitcast i8* %tmp3 to %0* 
 ; CHECK: br i1 undef, label %bb7, label %bb7
 ; CHECK: bb7:
diff --git a/test/Transforms/ObjCARC/contract.ll b/test/Transforms/ObjCARC/contract.ll
index 3544f88..2259e17 100644
--- a/test/Transforms/ObjCARC/contract.ll
+++ b/test/Transforms/ObjCARC/contract.ll
@@ -12,7 +12,7 @@ declare void @use_pointer(i8*)
 declare i8* @returner()
 declare void @callee()
 
-; CHECK: define void @test0
+; CHECK-LABEL: define void @test0(
 ; CHECK: call void @use_pointer(i8* %0)
 ; CHECK: }
 define void @test0(i8* %x) nounwind {
@@ -22,7 +22,7 @@ entry:
   ret void
 }
 
-; CHECK: define void @test1
+; CHECK-LABEL: define void @test1(
 ; CHECK: call void @use_pointer(i8* %0)
 ; CHECK: }
 define void @test1(i8* %x) nounwind {
@@ -34,7 +34,7 @@ entry:
 
 ; Merge objc_retain and objc_autorelease into objc_retainAutorelease.
 
-; CHECK: define void @test2(
+; CHECK-LABEL: define void @test2(
 ; CHECK: tail call i8* @objc_retainAutorelease(i8* %x) [[NUW:#[0-9]+]]
 ; CHECK: }
 define void @test2(i8* %x) nounwind {
@@ -47,7 +47,7 @@ entry:
 
 ; Same as test2 but the value is returned. Do an RV optimization.
 
-; CHECK: define i8* @test2b(
+; CHECK-LABEL: define i8* @test2b(
 ; CHECK: tail call i8* @objc_retainAutoreleaseReturnValue(i8* %x) [[NUW]]
 ; CHECK: }
 define i8* @test2b(i8* %x) nounwind {
@@ -59,7 +59,7 @@ entry:
 
 ; Merge a retain,autorelease pair around a call.
 
-; CHECK: define void @test3(
+; CHECK-LABEL: define void @test3(
 ; CHECK: tail call i8* @objc_retainAutorelease(i8* %x) [[NUW]]
 ; CHECK: @use_pointer(i8* %0)
 ; CHECK: }
@@ -74,7 +74,7 @@ entry:
 ; Trivial retain,autorelease pair with intervening call, but it's post-dominated
 ; by another release. The retain and autorelease can be merged.
 
-; CHECK: define void @test4(
+; CHECK-LABEL: define void @test4(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: @objc_retainAutorelease(i8* %x) [[NUW]]
 ; CHECK-NEXT: @use_pointer
@@ -92,7 +92,7 @@ entry:
 
 ; Don't merge retain and autorelease if they're not control-equivalent.
 
-; CHECK: define void @test5(
+; CHECK-LABEL: define void @test5(
 ; CHECK: tail call i8* @objc_retain(i8* %p) [[NUW]]
 ; CHECK: true:
 ; CHECK: call i8* @objc_autorelease(i8* %0) [[NUW]]
@@ -119,7 +119,7 @@ false:
 ; into objc_retainAutoreleasedReturnValueAutoreleaseReturnValue?
 ; Those entrypoints don't exist yet though.
 
-; CHECK: define i8* @test6(
+; CHECK-LABEL: define i8* @test6(
 ; CHECK: call i8* @objc_retainAutoreleasedReturnValue(i8* %p) [[NUW]]
 ; CHECK: %t = tail call i8* @objc_autoreleaseReturnValue(i8* %1) [[NUW]]
 ; CHECK: }
@@ -148,7 +148,7 @@ define i8* @test7(i8* %p) {
 
 ; Do the return value substitution for PHI nodes too.
 
-; CHECK: define i8* @test8(
+; CHECK-LABEL: define i8* @test8(
 ; CHECK: %retval = phi i8* [ %p, %if.then ], [ null, %entry ]
 ; CHECK: }
 define i8* @test8(i1 %x, i8* %c) {
@@ -165,7 +165,7 @@ return:                                           ; preds = %if.then, %entry
 }
 
 ; Kill calls to @clang.arc.use(...)
-; CHECK: define void @test9(
+; CHECK-LABEL: define void @test9(
 ; CHECK-NOT: clang.arc.use
 ; CHECK: }
 define void @test9(i8* %a, i8* %b) {
@@ -188,7 +188,7 @@ define void @test10() {
 ; Convert objc_retain to objc_retainAutoreleasedReturnValue if its
 ; argument is a return value.
 
-; CHECK: define void @test11(
+; CHECK-LABEL: define void @test11(
 ; CHECK-NEXT: %y = call i8* @returner()
 ; CHECK-NEXT: tail call i8* @objc_retainAutoreleasedReturnValue(i8* %y) [[NUW]]
 ; CHECK-NEXT: ret void
@@ -201,7 +201,7 @@ define void @test11() {
 ; Don't convert objc_retain to objc_retainAutoreleasedReturnValue if its
 ; argument is not a return value.
 
-; CHECK: define void @test12(
+; CHECK-LABEL: define void @test12(
 ; CHECK-NEXT: tail call i8* @objc_retain(i8* %y) [[NUW]]
 ; CHECK-NEXT: ret void
 ; CHECK-NEXT: }
@@ -213,7 +213,7 @@ define void @test12(i8* %y) {
 ; Don't Convert objc_retain to objc_retainAutoreleasedReturnValue if it
 ; isn't next to the call providing its return value.
 
-; CHECK: define void @test13(
+; CHECK-LABEL: define void @test13(
 ; CHECK-NEXT: %y = call i8* @returner()
 ; CHECK-NEXT: call void @callee()
 ; CHECK-NEXT: tail call i8* @objc_retain(i8* %y) [[NUW]]
diff --git a/test/Transforms/ObjCARC/empty-block.ll b/test/Transforms/ObjCARC/empty-block.ll
index ca55413..0440ab8 100644
--- a/test/Transforms/ObjCARC/empty-block.ll
+++ b/test/Transforms/ObjCARC/empty-block.ll
@@ -11,7 +11,7 @@ declare i8* @objc_autoreleaseReturnValue(i8*)
 
 ; Don't delete the autorelease.
 
-; CHECK: define %0* @test0(
+; CHECK-LABEL: define %0* @test0(
 ; CHECK:   @objc_retain
 ; CHECK: .lr.ph:
 ; CHECK-NOT: @objc_r
@@ -35,7 +35,7 @@ define %0* @test0(%0* %buffer) nounwind {
 
 ; Do delete the autorelease, even with the retain in a different block.
 
-; CHECK: define %0* @test1(
+; CHECK-LABEL: define %0* @test1(
 ; CHECK-NOT: @objc
 ; CHECK: }
 define %0* @test1() nounwind {
diff --git a/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll b/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll
index 05257d1..96a7d3e 100644
--- a/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll
+++ b/test/Transforms/ObjCARC/ensure-that-exception-unwind-path-is-visited.ll
@@ -113,34 +113,32 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!33, !34, !35, !36}
 
-!0 = metadata !{i32 786449, i32 0, i32 16, metadata !"test.m", metadata !"/Volumes/Files/gottesmmcab/Radar/12906997", metadata !"clang version 3.3 ", i1 true, i1 true, metadata !"", i32 2, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m] [DW_LANG_ObjC]
-!1 = metadata !{metadata !2}
-!2 = metadata !{i32 0}
-!3 = metadata !{metadata !4}
-!4 = metadata !{metadata !5, metadata !27}
-!5 = metadata !{i32 786478, i32 0, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 9, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, i32 ()* @main, null, null, metadata !10, i32 10} ; [ DW_TAG_subprogram ] [line 9] [def] [scope 10] [main]
-!6 = metadata !{i32 786473, metadata !"test.m", metadata !"/Volumes/Files/gottesmmcab/Radar/12906997", null} ; [ DW_TAG_file_type ]
+!0 = metadata !{i32 786449, metadata !60, i32 16, metadata !"clang version 3.3 ", i1 true, metadata !"", i32 2, metadata !1, metadata !1, metadata !3, metadata !1, null, metadata !""} ; [ DW_TAG_compile_unit ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m] [DW_LANG_ObjC]
+!1 = metadata !{i32 0}
+!3 = metadata !{metadata !5, metadata !27}
+!5 = metadata !{i32 786478, metadata !60, metadata !6, metadata !"main", metadata !"main", metadata !"", i32 9, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, i32 ()* @main, null, null, metadata !10, i32 10} ; [ DW_TAG_subprogram ] [line 9] [def] [scope 10] [main]
+!6 = metadata !{i32 786473, metadata !60} ; [ DW_TAG_file_type ]
 !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !8 = metadata !{metadata !9}
-!9 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
 !10 = metadata !{metadata !11}
 !11 = metadata !{metadata !12, metadata !21, metadata !25}
 !12 = metadata !{i32 786688, metadata !13, metadata !"obj", metadata !6, i32 11, metadata !14, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [obj] [line 11]
-!13 = metadata !{i32 786443, metadata !5, i32 10, i32 0, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
-!14 = metadata !{i32 786454, null, metadata !"id", metadata !6, i32 11, i64 0, i64 0, i64 0, i32 0, metadata !15} ; [ DW_TAG_typedef ] [id] [line 11, size 0, align 0, offset 0] [from ]
-!15 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !16} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from objc_object]
-!16 = metadata !{i32 786451, null, metadata !"objc_object", metadata !6, i32 0, i64 0, i64 0, i32 0, i32 0, null, metadata !17, i32 0, i32 0, i32 0} ; [ DW_TAG_structure_type ] [objc_object] [line 0, size 0, align 0, offset 0] [from ]
+!13 = metadata !{i32 786443, metadata !60, metadata !5, i32 10, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
+!14 = metadata !{i32 786454, metadata !60, null, metadata !"id", i32 11, i64 0, i64 0, i64 0, i32 0, metadata !15} ; [ DW_TAG_typedef ] [id] [line 11, size 0, align 0, offset 0] [from ]
+!15 = metadata !{i32 786447, metadata !60, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !16} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from objc_object]
+!16 = metadata !{i32 786451, metadata !60, null, metadata !"objc_object", i32 0, i64 0, i64 0, i32 0, i32 0, null, metadata !17, i32 0, i32 0, i32 0} ; [ DW_TAG_structure_type ] [objc_object] [line 0, size 0, align 0, offset 0] [from ]
 !17 = metadata !{metadata !18}
-!18 = metadata !{i32 786445, metadata !16, metadata !"isa", metadata !6, i32 0, i64 64, i64 0, i64 0, i32 0, metadata !19} ; [ DW_TAG_member ] [isa] [line 0, size 64, align 0, offset 0] [from ]
-!19 = metadata !{i32 786447, null, metadata !"", null, i32 0, i64 64, i64 0, i64 0, i32 0, metadata !20} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from objc_class]
-!20 = metadata !{i32 786451, null, metadata !"objc_class", metadata !6, i32 0, i64 0, i64 0, i32 0, i32 4, null, null, i32 0} ; [ DW_TAG_structure_type ] [objc_class] [line 0, size 0, align 0, offset 0] [fwd] [from ]
+!18 = metadata !{i32 786445, metadata !60, metadata !16, metadata !"isa", i32 0, i64 64, i64 0, i64 0, i32 0, metadata !19} ; [ DW_TAG_member ] [isa] [line 0, size 64, align 0, offset 0] [from ]
+!19 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 0, i64 0, i32 0, metadata !20} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from objc_class]
+!20 = metadata !{i32 786451, metadata !60, null, metadata !"objc_class", i32 0, i64 0, i64 0, i32 0, i32 4, null, null, i32 0} ; [ DW_TAG_structure_type ] [objc_class] [line 0, size 0, align 0, offset 0] [fwd] [from ]
 !21 = metadata !{i32 786688, metadata !22, metadata !"ok", metadata !6, i32 13, metadata !23, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [ok] [line 13]
-!22 = metadata !{i32 786443, metadata !13, i32 12, i32 0, metadata !6, i32 1} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
-!23 = metadata !{i32 786454, null, metadata !"BOOL", metadata !6, i32 62, i64 0, i64 0, i64 0, i32 0, metadata !24} ; [ DW_TAG_typedef ] [BOOL] [line 62, size 0, align 0, offset 0] [from signed char]
-!24 = metadata !{i32 786468, null, metadata !"signed char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] [signed char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
+!22 = metadata !{i32 786443, metadata !60, metadata !13, i32 12, i32 0, i32 1} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
+!23 = metadata !{i32 786454, metadata !60, null, metadata !"BOOL", i32 62, i64 0, i64 0, i64 0, i32 0, metadata !24} ; [ DW_TAG_typedef ] [BOOL] [line 62, size 0, align 0, offset 0] [from signed char]
+!24 = metadata !{i32 786468, null, null, metadata !"signed char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] [signed char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char]
 !25 = metadata !{i32 786688, metadata !26, metadata !"obj2", metadata !6, i32 15, metadata !14, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [obj2] [line 15]
-!26 = metadata !{i32 786443, metadata !22, i32 14, i32 0, metadata !6, i32 2} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
-!27 = metadata !{i32 786478, i32 0, metadata !6, metadata !"ThrowFunc", metadata !"ThrowFunc", metadata !"", metadata !6, i32 4, metadata !28, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, void (i8*)* @ThrowFunc, null, null, metadata !30, i32 5} ; [ DW_TAG_subprogram ] [line 4] [local] [def] [scope 5] [ThrowFunc]
+!26 = metadata !{i32 786443, metadata !60, metadata !22, i32 14, i32 0, i32 2} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
+!27 = metadata !{i32 786478, metadata !60, metadata !6, metadata !"ThrowFunc", metadata !"ThrowFunc", metadata !"", i32 4, metadata !28, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, void (i8*)* @ThrowFunc, null, null, metadata !30, i32 5} ; [ DW_TAG_subprogram ] [line 4] [local] [def] [scope 5] [ThrowFunc]
 !28 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !29, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
 !29 = metadata !{null, metadata !14}
 !30 = metadata !{metadata !31}
@@ -154,21 +152,22 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 !38 = metadata !{}
 !39 = metadata !{i32 15, i32 0, metadata !26, null}
 !40 = metadata !{i32 17, i32 0, metadata !41, null}
-!41 = metadata !{i32 786443, metadata !26, i32 16, i32 0, metadata !6, i32 3} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
+!41 = metadata !{i32 786443, metadata !60, metadata !26, i32 16, i32 0, i32 3} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
 !42 = metadata !{i32 22, i32 0, metadata !26, null}
 !43 = metadata !{i32 23, i32 0, metadata !22, null}
 !44 = metadata !{i32 19, i32 0, metadata !41, null}
 !45 = metadata !{i8 0}
 !46 = metadata !{i32 20, i32 0, metadata !47, null}
-!47 = metadata !{i32 786443, metadata !48, i32 19, i32 0, metadata !6, i32 5} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
-!48 = metadata !{i32 786443, metadata !26, i32 19, i32 0, metadata !6, i32 4} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
+!47 = metadata !{i32 786443, metadata !60, metadata !48, i32 19, i32 0, i32 5} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
+!48 = metadata !{i32 786443, metadata !60, metadata !26, i32 19, i32 0, i32 4} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
 !49 = metadata !{i32 21, i32 0, metadata !47, null}
 !50 = metadata !{i32 24, i32 0, metadata !51, null}
-!51 = metadata !{i32 786443, metadata !22, i32 23, i32 0, metadata !6, i32 6} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
+!51 = metadata !{i32 786443, metadata !60, metadata !22, i32 23, i32 0, i32 6} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
 !52 = metadata !{i32 25, i32 0, metadata !51, null}
 !53 = metadata !{i32 27, i32 0, metadata !13, null}
 !54 = metadata !{i32 28, i32 0, metadata !13, null}
 !55 = metadata !{i32 4, i32 0, metadata !27, null}
 !56 = metadata !{i32 6, i32 0, metadata !57, null}
-!57 = metadata !{i32 786443, metadata !27, i32 5, i32 0, metadata !6, i32 7} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
+!57 = metadata !{i32 786443, metadata !60, metadata !27, i32 5, i32 0, i32 7} ; [ DW_TAG_lexical_block ] [/Volumes/Files/gottesmmcab/Radar/12906997/test.m]
 !58 = metadata !{i32 7, i32 0, metadata !57, null}
+!60 = metadata !{metadata !"test.m", metadata !"/Volumes/Files/gottesmmcab/Radar/12906997"}
diff --git a/test/Transforms/ObjCARC/escape.ll b/test/Transforms/ObjCARC/escape.ll
index 8f252a0..28f2e80 100644
--- a/test/Transforms/ObjCARC/escape.ll
+++ b/test/Transforms/ObjCARC/escape.ll
@@ -9,7 +9,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; Don't optimize away the retainBlock, because the object's address "escapes"
 ; with the objc_storeWeak call.
 
-; CHECK: define void @test0(
+; CHECK-LABEL: define void @test0(
 ; CHECK: %tmp7 = call i8* @objc_retainBlock(i8* %tmp6) [[NUW:#[0-9]+]], !clang.arc.copy_on_escape !0
 ; CHECK: call void @objc_release(i8* %tmp7) [[NUW]], !clang.imprecise_release !0
 ; CHECK: }
@@ -65,7 +65,7 @@ entry:
 ; Like test0, but it makes a regular call instead of a storeWeak call,
 ; so the optimization is valid.
 
-; CHECK: define void @test1(
+; CHECK-LABEL: define void @test1(
 ; CHECK-NOT: @objc_retainBlock
 ; CHECK: }
 define void @test1() nounwind {
diff --git a/test/Transforms/ObjCARC/gvn.ll b/test/Transforms/ObjCARC/gvn.ll
index a828b54..2d120e7 100644
--- a/test/Transforms/ObjCARC/gvn.ll
+++ b/test/Transforms/ObjCARC/gvn.ll
@@ -3,20 +3,39 @@
 @x = common global i8* null, align 8
 
 declare i8* @objc_retain(i8*)
+declare i32 @objc_sync_enter(i8*)
+declare i32 @objc_sync_exit(i8*)
 
 ; GVN should be able to eliminate this redundant load, with ARC-specific
 ; alias analysis.
 
-; CHECK: define i8* @foo(i32 %n)
+; CHECK: define i8* @test0(i32 %n)
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: %s = load i8** @x
 ; CHECK-NOT: load
 ; CHECK: ret i8* %s
 ; CHECK-NEXT: }
-define i8* @foo(i32 %n) nounwind {
+define i8* @test0(i32 %n) nounwind {
 entry:
   %s = load i8** @x
   %0 = tail call i8* @objc_retain(i8* %s) nounwind
   %t = load i8** @x
-  ret i8* %s
+  ret i8* %t
+}
+
+; GVN should not be able to eliminate this redundant load, with ARC-specific
+; alias analysis.
+
+; CHECK-LABEL: define i8* @test1(
+; CHECK: load
+; CHECK: load
+; CHECK: ret i8* %t
+; CHECK: }
+define i8* @test1(i32 %n) nounwind {
+entry:
+  %s = load i8** @x
+  %0 = call i32 @objc_sync_enter(i8* %s)
+  %t = load i8** @x
+  %1 = call i32 @objc_sync_exit(i8* %s)
+  ret i8* %t
 }
diff --git a/test/Transforms/ObjCARC/intrinsic-use-isolated.ll b/test/Transforms/ObjCARC/intrinsic-use-isolated.ll
index 4215b5c..f5c31fd 100644
--- a/test/Transforms/ObjCARC/intrinsic-use-isolated.ll
+++ b/test/Transforms/ObjCARC/intrinsic-use-isolated.ll
@@ -6,7 +6,7 @@
 declare void @clang.arc.use(...) nounwind
 
 ; Kill calls to @clang.arc.use(...)
-; CHECK: define void @test0(
+; CHECK-LABEL: define void @test0(
 ; CHECK-NOT: clang.arc.use
 ; CHECK: }
 define void @test0(i8* %a, i8* %b) {
diff --git a/test/Transforms/ObjCARC/intrinsic-use.ll b/test/Transforms/ObjCARC/intrinsic-use.ll
index 60370c1..f3833cb 100644
--- a/test/Transforms/ObjCARC/intrinsic-use.ll
+++ b/test/Transforms/ObjCARC/intrinsic-use.ll
@@ -17,7 +17,7 @@ declare void @test0_helper(i8*, i8**)
 ; FIXME: the fact that we re-order retains w.r.t. @clang.arc.use could
 ; be problematic if we get run twice, e.g. under LTO.
 ;
-; CHECK:      define void @test0(
+; CHECK-LABEL:      define void @test0(
 ; CHECK:        @objc_retain(i8* %x)
 ; CHECK-NEXT:   store i8* %y, i8** %temp0
 ; CHECK-NEXT:   @objc_retain(i8* %y)
@@ -65,7 +65,7 @@ entry:
   ret void
 }
 
-; CHECK:      define void @test0a(
+; CHECK-LABEL:      define void @test0a(
 ; CHECK:        @objc_retain(i8* %x)
 ; CHECK-NEXT:   store i8* %y, i8** %temp0
 ; CHECK-NEXT:   @objc_retain(i8* %y)
diff --git a/test/Transforms/ObjCARC/invoke.ll b/test/Transforms/ObjCARC/invoke.ll
index 9510f2e..04d057b 100644
--- a/test/Transforms/ObjCARC/invoke.ll
+++ b/test/Transforms/ObjCARC/invoke.ll
@@ -10,7 +10,7 @@ declare i8* @returner()
 
 ; ARCOpt shouldn't try to move the releases to the block containing the invoke.
 
-; CHECK: define void @test0(
+; CHECK-LABEL: define void @test0(
 ; CHECK: invoke.cont:
 ; CHECK:   call void @objc_release(i8* %zipFile) [[NUW:#[0-9]+]], !clang.imprecise_release !0
 ; CHECK:   ret void
@@ -38,7 +38,7 @@ lpad:                                             ; preds = %entry
 
 ; ARCOpt should move the release before the callee calls.
 
-; CHECK: define void @test1(
+; CHECK-LABEL: define void @test1(
 ; CHECK: invoke.cont:
 ; CHECK:   call void @objc_release(i8* %zipFile) [[NUW]], !clang.imprecise_release !0
 ; CHECK:   call void @callee()
@@ -108,7 +108,7 @@ finally.rethrow:                                  ; preds = %invoke.cont, %entry
 
 ; Don't try to place code on invoke critical edges.
 
-; CHECK: define void @test3(
+; CHECK-LABEL: define void @test3(
 ; CHECK: if.end:
 ; CHECK-NEXT: call void @objc_release(i8* %p) [[NUW]]
 ; CHECK-NEXT: ret void
@@ -139,7 +139,7 @@ if.end:
 
 ; Like test3, but with ARC-relevant exception handling.
 
-; CHECK: define void @test4(
+; CHECK-LABEL: define void @test4(
 ; CHECK: lpad:
 ; CHECK-NEXT: %r = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__objc_personality_v0 to i8*)
 ; CHECK-NEXT: cleanup
@@ -177,7 +177,7 @@ if.end:
 ; Don't turn the retainAutoreleaseReturnValue into retain, because it's
 ; for an invoke which we can assume codegen will put immediately prior.
 
-; CHECK: define void @test5(
+; CHECK-LABEL: define void @test5(
 ; CHECK: call i8* @objc_retainAutoreleasedReturnValue(i8* %z)
 ; CHECK: }
 define void @test5() {
@@ -197,7 +197,7 @@ if.end:
 
 ; Like test5, but there's intervening code.
 
-; CHECK: define void @test6(
+; CHECK-LABEL: define void @test6(
 ; CHECK: call i8* @objc_retain(i8* %z)
 ; CHECK: }
 define void @test6() {
diff --git a/test/Transforms/ObjCARC/nested.ll b/test/Transforms/ObjCARC/nested.ll
index ca9c58b..2eeb4fc 100644
--- a/test/Transforms/ObjCARC/nested.ll
+++ b/test/Transforms/ObjCARC/nested.ll
@@ -25,7 +25,7 @@ declare void @__crasher_block_invoke1(i8* nocapture)
 
 ; Delete a nested retain+release pair.
 
-; CHECK: define void @test0(
+; CHECK-LABEL: define void @test0(
 ; CHECK: call i8* @objc_retain
 ; CHECK-NOT: @objc_retain
 ; CHECK: }
@@ -89,7 +89,7 @@ forcoll.empty:
 
 ; Delete a nested retain+release pair.
 
-; CHECK: define void @test2(
+; CHECK-LABEL: define void @test2(
 ; CHECK: call i8* @objc_retain
 ; CHECK-NOT: @objc_retain
 ; CHECK: }
@@ -154,7 +154,7 @@ forcoll.empty:
 
 ; Delete a nested retain+release pair.
 
-; CHECK: define void @test4(
+; CHECK-LABEL: define void @test4(
 ; CHECK: call i8* @objc_retain
 ; CHECK-NOT: @objc_retain
 ; CHECK: }
@@ -219,7 +219,7 @@ forcoll.empty:
 
 ; Delete a nested retain+release pair.
 
-; CHECK: define void @test5(
+; CHECK-LABEL: define void @test5(
 ; CHECK: call i8* @objc_retain
 ; CHECK-NOT: @objc_retain
 ; CHECK: }
@@ -287,7 +287,7 @@ forcoll.empty:
 ; The optimizer currently can't do this, because isn't isn't sophisticated enough in
 ; reasnoning about nesting.
 
-; CHECK: define void @test6(
+; CHECK-LABEL: define void @test6(
 ; CHECK: call i8* @objc_retain
 ; CHECK: @objc_retain
 ; CHECK: }
@@ -355,7 +355,7 @@ forcoll.empty:
 ; The optimizer currently can't do this, because isn't isn't sophisticated enough in
 ; reasnoning about nesting.
 
-; CHECK: define void @test7(
+; CHECK-LABEL: define void @test7(
 ; CHECK: call i8* @objc_retain
 ; CHECK: @objc_retain
 ; CHECK: }
@@ -422,7 +422,7 @@ forcoll.empty:
 
 ; Delete a nested retain+release pair.
 
-; CHECK: define void @test8(
+; CHECK-LABEL: define void @test8(
 ; CHECK: call i8* @objc_retain
 ; CHECK-NOT: @objc_retain
 ; CHECK: }
@@ -496,7 +496,7 @@ forcoll.empty:
 ; The optimizer currently can't do this, because of a split loop backedge.
 ; See test9b for the same testcase without a split backedge.
 
-; CHECK: define void @test9(
+; CHECK-LABEL: define void @test9(
 ; CHECK: call i8* @objc_retain
 ; CHECK: call i8* @objc_retain
 ; CHECK: call i8* @objc_retain
@@ -563,7 +563,7 @@ forcoll.empty:
 
 ; Like test9, but without a split backedge. TODO: optimize this.
 
-; CHECK: define void @test9b(
+; CHECK-LABEL: define void @test9b(
 ; CHECK: call i8* @objc_retain
 ; CHECK: call i8* @objc_retain
 ; CHECK: @objc_retain
@@ -629,7 +629,7 @@ forcoll.empty:
 ; The optimizer currently can't do this, because of a split loop backedge.
 ; See test10b for the same testcase without a split backedge.
 
-; CHECK: define void @test10(
+; CHECK-LABEL: define void @test10(
 ; CHECK: call i8* @objc_retain
 ; CHECK: call i8* @objc_retain
 ; CHECK: call i8* @objc_retain
@@ -697,7 +697,7 @@ forcoll.empty:
 
 ; Like test10, but without a split backedge. TODO: optimize this.
 
-; CHECK: define void @test10b(
+; CHECK-LABEL: define void @test10b(
 ; CHECK: call i8* @objc_retain
 ; CHECK: call i8* @objc_retain
 ; CHECK: @objc_retain
@@ -769,7 +769,7 @@ forcoll.empty:
 @__block_d_tmp = external hidden constant { i64, i64, i8*, i8*, i8*, i8* }
 @__block_d_tmp5 = external hidden constant { i64, i64, i8*, i8*, i8*, i8* }
 
-; CHECK: define void @test11(
+; CHECK-LABEL: define void @test11(
 ; CHECK: tail call i8* @objc_retain(i8* %call) [[NUW:#[0-9]+]]
 ; CHECK: tail call i8* @objc_retain(i8* %call) [[NUW]]
 ; CHECK: call void @objc_release(i8* %call) [[NUW]], !clang.imprecise_release !0
diff --git a/test/Transforms/ObjCARC/no-objc-arc-exceptions.ll b/test/Transforms/ObjCARC/no-objc-arc-exceptions.ll
index 58b5bbe..2a56371 100644
--- a/test/Transforms/ObjCARC/no-objc-arc-exceptions.ll
+++ b/test/Transforms/ObjCARC/no-objc-arc-exceptions.ll
@@ -10,7 +10,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 ; metadata and eliminate the retainBlock+release pair here.
 ; rdar://10803830.
 
-; CHECK: define void @test0(
+; CHECK-LABEL: define void @test0(
 ; CHECK-NOT: @objc
 ; CHECK: }
 define void @test0() {
@@ -63,7 +63,7 @@ lpad:                                             ; preds = %entry
 ; shouldn't eliminate anything, but *CAN* strength reduce the objc_retainBlock
 ; to an objc_retain.
 
-; CHECK: define void @test0_no_metadata(
+; CHECK-LABEL: define void @test0_no_metadata(
 ; CHECK: call i8* @objc_retain(
 ; CHECK: invoke
 ; CHECK: call void @objc_release(
diff --git a/test/Transforms/ObjCARC/pointer-types.ll b/test/Transforms/ObjCARC/pointer-types.ll
index 6abc939..257560d 100644
--- a/test/Transforms/ObjCARC/pointer-types.ll
+++ b/test/Transforms/ObjCARC/pointer-types.ll
@@ -5,7 +5,7 @@
 ; in dubious ways.
 ; rdar://10551239
 
-; CHECK: define void @test0(
+; CHECK-LABEL: define void @test0(
 ; CHECK: %otherBlock = phi void ()* [ %b1, %if.then ], [ null, %entry ]
 ; CHECK-NEXT: call void @use_fptr(void ()* %otherBlock)
 ; CHECK-NEXT: %tmp11 = bitcast void ()* %otherBlock to i8*
diff --git a/test/Transforms/ObjCARC/post-inlining.ll b/test/Transforms/ObjCARC/post-inlining.ll
index ad69ccd..b2d6112 100644
--- a/test/Transforms/ObjCARC/post-inlining.ll
+++ b/test/Transforms/ObjCARC/post-inlining.ll
@@ -8,7 +8,7 @@ declare i8* @objc_retainAutoreleasedReturnValue(i8*)
 
 ; Clean up residue left behind after inlining.
 
-; CHECK: define void @test0(
+; CHECK-LABEL: define void @test0(
 ; CHECK: entry:
 ; CHECK-NEXT: ret void
 ; CHECK-NEXT: }
@@ -21,7 +21,7 @@ entry:
 
 ; Same as test0, but with slightly different use arrangements.
 
-; CHECK: define void @test1(
+; CHECK-LABEL: define void @test1(
 ; CHECK: entry:
 ; CHECK-NEXT: ret void
 ; CHECK-NEXT: }
@@ -34,7 +34,7 @@ entry:
 
 ; Delete a retainRV+autoreleaseRV even if the pointer is used.
 
-; CHECK: define void @test24(
+; CHECK-LABEL: define void @test24(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   call void @use_pointer(i8* %p)
 ; CHECK-NEXT:   ret void
diff --git a/test/Transforms/ObjCARC/retain-block-alloca.ll b/test/Transforms/ObjCARC/retain-block-alloca.ll
index f40be23..6b1578a 100644
--- a/test/Transforms/ObjCARC/retain-block-alloca.ll
+++ b/test/Transforms/ObjCARC/retain-block-alloca.ll
@@ -8,7 +8,7 @@
 @__block_descriptor_tmp = external hidden constant { i64, i64, i8*, i8*, i8*, i8* }
 @"\01L_OBJC_SELECTOR_REFERENCES_" = external hidden global i8*, section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
 
-; CHECK: define void @test(
+; CHECK-LABEL: define void @test(
 ; CHECK: %3 = call i8* @objc_retainBlock(i8* %2) [[NUW:#[0-9]+]]
 ; CHECK: @objc_msgSend
 ; CHECK-NEXT: @objc_release(i8* %3)
@@ -43,7 +43,7 @@ entry:
 ; Same as test, but the objc_retainBlock has a clang.arc.copy_on_escape
 ; tag so it's safe to delete.
 
-; CHECK: define void @test_with_COE(
+; CHECK-LABEL: define void @test_with_COE(
 ; CHECK-NOT: @objc_retainBlock
 ; CHECK: @objc_msgSend
 ; CHECK: @objc_release
diff --git a/test/Transforms/ObjCARC/retain-block-escape-analysis.ll b/test/Transforms/ObjCARC/retain-block-escape-analysis.ll
index 8df05ad..7914bb8 100644
--- a/test/Transforms/ObjCARC/retain-block-escape-analysis.ll
+++ b/test/Transforms/ObjCARC/retain-block-escape-analysis.ll
@@ -20,7 +20,7 @@ declare i8* @objc_retainBlock(i8*)
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 define void @bitcasttest(i8* %storage, void (...)* %block)  {
-; CHECK: define void @bitcasttest
+; CHECK-LABEL: define void @bitcasttest(
 entry:
   %t1 = bitcast void (...)* %block to i8*
 ; CHECK: tail call i8* @objc_retain
@@ -37,7 +37,7 @@ entry:
 }
 
 define void @bitcasttest_a(i8* %storage, void (...)* %block)  {
-; CHECK: define void @bitcasttest_a
+; CHECK-LABEL: define void @bitcasttest_a(
 entry:
   %t1 = bitcast void (...)* %block to i8*
 ; CHECK-NOT: tail call i8* @objc_retain
@@ -54,7 +54,7 @@ entry:
 }
 
 define void @geptest(void (...)** %storage_array, void (...)* %block)  {
-; CHECK: define void @geptest
+; CHECK-LABEL: define void @geptest(
 entry:
   %t1 = bitcast void (...)* %block to i8*
 ; CHECK: tail call i8* @objc_retain
@@ -73,7 +73,7 @@ entry:
 }
 
 define void @geptest_a(void (...)** %storage_array, void (...)* %block)  {
-; CHECK: define void @geptest_a
+; CHECK-LABEL: define void @geptest_a(
 entry:
   %t1 = bitcast void (...)* %block to i8*
 ; CHECK-NOT: tail call i8* @objc_retain
@@ -93,7 +93,7 @@ entry:
 
 define void @selecttest(void (...)** %store1, void (...)** %store2,
                         void (...)* %block) {
-; CHECK: define void @selecttest
+; CHECK-LABEL: define void @selecttest(
 entry:
   %t1 = bitcast void (...)* %block to i8*
 ; CHECK: tail call i8* @objc_retain
@@ -111,7 +111,7 @@ entry:
 
 define void @selecttest_a(void (...)** %store1, void (...)** %store2,
                           void (...)* %block) {
-; CHECK: define void @selecttest_a
+; CHECK-LABEL: define void @selecttest_a(
 entry:
   %t1 = bitcast void (...)* %block to i8*
 ; CHECK-NOT: tail call i8* @objc_retain
@@ -130,7 +130,7 @@ entry:
 define void @phinodetest(void (...)** %storage1,
                          void (...)** %storage2,
                          void (...)* %block) {
-; CHECK: define void @phinodetest
+; CHECK-LABEL: define void @phinodetest(
 entry:
   %t1 = bitcast void (...)* %block to i8*
 ; CHECK: tail call i8* @objc_retain
@@ -160,7 +160,7 @@ end:
 define void @phinodetest_a(void (...)** %storage1,
                            void (...)** %storage2,
                            void (...)* %block) {
-; CHECK: define void @phinodetest_a
+; CHECK-LABEL: define void @phinodetest_a(
 entry:
   %t1 = bitcast void (...)* %block to i8*
 ; CHECK-NOT: tail call i8* @objc_retain
diff --git a/test/Transforms/ObjCARC/retain-not-declared.ll b/test/Transforms/ObjCARC/retain-not-declared.ll
index 165829f..3a2bd03 100644
--- a/test/Transforms/ObjCARC/retain-not-declared.ll
+++ b/test/Transforms/ObjCARC/retain-not-declared.ll
@@ -28,7 +28,7 @@ entry:
 ; Properly create the @objc_retain declaration when it doesn't already exist.
 ; rdar://9825114
 
-; CHECK: @test1(
+; CHECK-LABEL: @test1(
 ; CHECK: @objc_retain(
 ; CHECK: @objc_retainAutoreleasedReturnValue(
 ; CHECK: @objc_release(
diff --git a/test/Transforms/ObjCARC/rv.ll b/test/Transforms/ObjCARC/rv.ll
index e857c9f..85a1612 100644
--- a/test/Transforms/ObjCARC/rv.ll
+++ b/test/Transforms/ObjCARC/rv.ll
@@ -26,7 +26,7 @@ declare i8* @returner()
 ; retain is an objc_retainAutoreleasedReturnValue, since it's
 ; better to do the RV optimization.
 
-; CHECK:      define void @test0(
+; CHECK-LABEL:      define void @test0(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   %x = call i8* @returner
 ; CHECK-NEXT:   %0 = tail call i8* @objc_retainAutoreleasedReturnValue(i8* %x) [[NUW:#[0-9]+]]
@@ -54,7 +54,7 @@ return:
 
 ; Delete no-ops.
 
-; CHECK: define void @test2
+; CHECK-LABEL: define void @test2(
 ; CHECK-NOT: @objc_
 ; CHECK: }
 define void @test2() {
@@ -67,7 +67,7 @@ define void @test2() {
 ; Delete a redundant retainRV,autoreleaseRV when forwaring a call result
 ; directly to a return value.
 
-; CHECK: define i8* @test3
+; CHECK-LABEL: define i8* @test3(
 ; CHECK: call i8* @returner()
 ; CHECK-NEXT: ret i8* %call
 define i8* @test3() {
@@ -81,7 +81,7 @@ entry:
 ; Delete a redundant retain,autoreleaseRV when forwaring a call result
 ; directly to a return value.
 
-; CHECK: define i8* @test4
+; CHECK-LABEL: define i8* @test4(
 ; CHECK: call i8* @returner()
 ; CHECK-NEXT: ret i8* %call
 define i8* @test4() {
@@ -114,7 +114,7 @@ entry:
 ; into objc_retainAutoreleasedReturnValueAutoreleaseReturnValue?
 ; Those entrypoints don't exist yet though.
 
-; CHECK: define i8* @test7(
+; CHECK-LABEL: define i8* @test7(
 ; CHECK: call i8* @objc_retainAutoreleasedReturnValue(i8* %p)
 ; CHECK: %t = tail call i8* @objc_autoreleaseReturnValue(i8* %p)
 define i8* @test7() {
@@ -125,7 +125,7 @@ define i8* @test7() {
   ret i8* %t
 }
 
-; CHECK: define i8* @test7b(
+; CHECK-LABEL: define i8* @test7b(
 ; CHECK: call i8* @objc_retain(i8* %p)
 ; CHECK: %t = tail call i8* @objc_autoreleaseReturnValue(i8* %p)
 define i8* @test7b() {
@@ -188,7 +188,7 @@ define i8* @test12(i8* %p) {
 
 ; Don't zap the objc_retainAutoreleasedReturnValue.
 
-; CHECK: define i8* @test13(
+; CHECK-LABEL: define i8* @test13(
 ; CHECK: tail call i8* @objc_retainAutoreleasedReturnValue(i8* %p)
 ; CHECK: call i8* @objc_autorelease(i8* %p)
 ; CHECK: ret i8* %p
@@ -203,7 +203,7 @@ define i8* @test13() {
 ; Convert objc_retainAutoreleasedReturnValue to objc_retain if its
 ; argument is not a return value.
 
-; CHECK: define void @test14(
+; CHECK-LABEL: define void @test14(
 ; CHECK-NEXT: tail call i8* @objc_retain(i8* %p) [[NUW]]
 ; CHECK-NEXT: ret void
 define void @test14(i8* %p) {
@@ -214,7 +214,7 @@ define void @test14(i8* %p) {
 ; Don't convert objc_retainAutoreleasedReturnValue to objc_retain if its
 ; argument is a return value.
 
-; CHECK: define void @test15(
+; CHECK-LABEL: define void @test15(
 ; CHECK-NEXT: %y = call i8* @returner()
 ; CHECK-NEXT: tail call i8* @objc_retainAutoreleasedReturnValue(i8* %y) [[NUW]]
 ; CHECK-NEXT: ret void
@@ -272,7 +272,7 @@ define i8* @test22(i8* %p) {
 
 ; Convert autoreleaseRV to autorelease.
 
-; CHECK: define void @test23(
+; CHECK-LABEL: define void @test23(
 ; CHECK: call i8* @objc_autorelease(i8* %p) [[NUW]]
 define void @test23(i8* %p) {
   store i8 0, i8* %p
@@ -283,7 +283,7 @@ define void @test23(i8* %p) {
 ; Don't convert autoreleaseRV to autorelease if the result is returned,
 ; even through a bitcast.
 
-; CHECK: define {}* @test24(
+; CHECK-LABEL: define {}* @test24(
 ; CHECK: tail call i8* @objc_autoreleaseReturnValue(i8* %p)
 define {}* @test24(i8* %p) {
   %t = call i8* @objc_autoreleaseReturnValue(i8* %p)
diff --git a/test/Transforms/ObjCARC/split-backedge.ll b/test/Transforms/ObjCARC/split-backedge.ll
index 5ac278a..1b7cf44 100644
--- a/test/Transforms/ObjCARC/split-backedge.ll
+++ b/test/Transforms/ObjCARC/split-backedge.ll
@@ -3,7 +3,7 @@
 ; Handle a retain+release pair entirely contained within a split loop backedge.
 ; rdar://11256239
 
-; CHECK: define void @test0
+; CHECK-LABEL: define void @test0(
 ; CHECK: call i8* @objc_retain(i8* %call) [[NUW:#[0-9]+]]
 ; CHECK: call i8* @objc_retain(i8* %call) [[NUW]]
 ; CHECK: call i8* @objc_retain(i8* %cond) [[NUW]]
diff --git a/test/Transforms/ObjCARC/weak.ll b/test/Transforms/ObjCARC/weak.ll
index 85a290c..119aa82 100644
--- a/test/Transforms/ObjCARC/weak.ll
+++ b/test/Transforms/ObjCARC/weak.ll
@@ -10,7 +10,7 @@ declare void @objc_copyWeak(i8**, i8**)
 
 ; If the pointer-to-weak-pointer is null, it's undefined behavior.
 
-; CHECK: define void @test0(
+; CHECK-LABEL: define void @test0(
 ; CHECK: store i8* undef, i8** null
 ; CHECK: store i8* undef, i8** null
 ; CHECK: store i8* undef, i8** null
diff --git a/test/Transforms/PhaseOrdering/PR6627.ll b/test/Transforms/PhaseOrdering/PR6627.ll
index 58b762a..cf95363 100644
--- a/test/Transforms/PhaseOrdering/PR6627.ll
+++ b/test/Transforms/PhaseOrdering/PR6627.ll
@@ -42,7 +42,7 @@ if.then:                                          ; preds = %land.lhs.true17
 if.end:
   ret void
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: %x1 = load i32* %xx, align 4
 ; CHECK-NEXT: icmp eq i32 %x1, 1179403647
 ; CHECK-NEXT: br i1 {{.*}}, label %if.then, label %if.end 
@@ -86,7 +86,7 @@ if.then:                                          ; preds = %land.lhs.true17
 if.end:
   ret void
 
-; CHECK: @test2a
+; CHECK-LABEL: @test2a(
 ; CHECK: %x1 = load i32* {{.*}}, align 4
 ; CHECK-NEXT: icmp eq i32 %x1, 1179403647
 ; CHECK-NEXT: br i1 {{.*}}, label %if.then, label %if.end 
diff --git a/test/Transforms/PhaseOrdering/basic.ll b/test/Transforms/PhaseOrdering/basic.ll
index 8fbe8c5..2deefa6 100644
--- a/test/Transforms/PhaseOrdering/basic.ll
+++ b/test/Transforms/PhaseOrdering/basic.ll
@@ -19,7 +19,7 @@ define void @test1() nounwind ssp {
   call void @free(i8* %tmp1)
   ret void
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: ret void
 }
 
@@ -44,7 +44,7 @@ entry:
   %sub = sub i32 %0, %mul
   ret i32 %sub
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: %div = lshr i32 %a, 2
 ; CHECK: %add = shl nuw nsw i32 %div, 1
 ; CHECK: ret i32 0
diff --git a/test/Transforms/Reassociate/2012-05-08-UndefLeak.ll b/test/Transforms/Reassociate/2012-05-08-UndefLeak.ll
index 2f5a53e..c563fe2 100644
--- a/test/Transforms/Reassociate/2012-05-08-UndefLeak.ll
+++ b/test/Transforms/Reassociate/2012-05-08-UndefLeak.ll
@@ -5,7 +5,7 @@
 ; Transform disabled until PR13021 is fixed.
 
 define i64 @f(i64 %x0) {
-; CHECK: @f
+; CHECK-LABEL: @f(
 ; CHECK-NEXT: mul i64 %x0, 208
 ; CHECK-NEXT: add i64 %{{.*}}, 1617
 ; CHECK-NEXT: ret i64
diff --git a/test/Transforms/Reassociate/absorption.ll b/test/Transforms/Reassociate/absorption.ll
index 2ccc2b5..40b3d80 100644
--- a/test/Transforms/Reassociate/absorption.ll
+++ b/test/Transforms/Reassociate/absorption.ll
@@ -6,6 +6,6 @@ define i8 @foo(i8 %x) {
   %tmp1 = or i8 %x, 127
   %tmp2 = or i8 %tmp1, 128
   ret i8 %tmp2
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK: ret i8 -1
 }
diff --git a/test/Transforms/Reassociate/basictest.ll b/test/Transforms/Reassociate/basictest.ll
index 0864740..fda0ca6 100644
--- a/test/Transforms/Reassociate/basictest.ll
+++ b/test/Transforms/Reassociate/basictest.ll
@@ -6,7 +6,7 @@ define i32 @test1(i32 %arg) {
 	%tmp1 = sub i32 -12, %arg
 	%tmp2 = add i32 %tmp1, 12
 	ret i32 %tmp2
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: sub i32 0, %arg
 ; CHECK-NEXT: ret i32
 }
@@ -16,7 +16,7 @@ define i32 @test2(i32 %reg109, i32 %reg1111) {
 	%reg116 = add i32 %reg115, %reg1111		; <i32> [#uses=1]
 	%reg117 = add i32 %reg116, 30		; <i32> [#uses=1]
 	ret i32 %reg117
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: add i32 %reg1111, %reg109
 ; CHECK-NEXT: ret i32
 }
@@ -40,7 +40,7 @@ define void @test3() {
         ; f = (a+c)+b
 	store i32 %t4, i32* @f
 	ret void
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: add i32
 ; CHECK: add i32
 ; CHECK-NOT: add i32
@@ -60,7 +60,7 @@ define void @test4() {
         ; f = (c+a)+b
 	store i32 %t4, i32* @f
 	ret void
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: add i32
 ; CHECK: add i32
 ; CHECK-NOT: add i32
@@ -80,7 +80,7 @@ define void @test5() {
         ; f = (c+a)+b
 	store i32 %t4, i32* @f
 	ret void
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: add i32
 ; CHECK: add i32
 ; CHECK-NOT: add i32
@@ -102,7 +102,7 @@ define i32 @test6() {
 	; X ^ X = 0
         %RV = xor i32 %tmp.5, %tmp.11
 	ret i32 %RV
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: ret i32 0
 }
 
@@ -115,7 +115,7 @@ define i32 @test7(i32 %A, i32 %B, i32 %C) {
 	%aac = mul i32 %ac, %A
 	%r = add i32 %aab, %aac
 	ret i32 %r
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NEXT: add i32 %C, %B
 ; CHECK-NEXT: mul i32 
 ; CHECK-NEXT: mul i32 
@@ -129,7 +129,7 @@ define i32 @test8(i32 %X, i32 %Y, i32 %Z) {
         ; (-X)*Y + Z -> Z-X*Y
 	%C = add i32 %B, %Z
 	ret i32 %C
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK-NEXT: %A = mul i32 %Y, %X
 ; CHECK-NEXT: %C = sub i32 %Z, %A
 ; CHECK-NEXT: ret i32 %C
@@ -141,7 +141,7 @@ define i32 @test9(i32 %X) {
   %Y = mul i32 %X, 47
   %Z = add i32 %Y, %Y
   ret i32 %Z
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NEXT: mul i32 %X, 94
 ; CHECK-NEXT: ret i32
 }
@@ -150,7 +150,7 @@ define i32 @test10(i32 %X) {
   %Y = add i32 %X ,%X
   %Z = add i32 %Y, %X
   ret i32 %Z
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK-NEXT: mul i32 %X, 3
 ; CHECK-NEXT: ret i32
 }
@@ -160,7 +160,7 @@ define i32 @test11(i32 %W) {
   %Y = add i32 %X ,%X
   %Z = add i32 %Y, %X
   ret i32 %Z
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK-NEXT: mul i32 %W, 381
 ; CHECK-NEXT: ret i32
 }
@@ -173,7 +173,7 @@ define i32 @test12(i32 %X) {
   %Y = add i32 %A ,%B
   %Z = add i32 %Y, %C
   ret i32 %Z
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK-NEXT: mul i32 %X, -3
 ; CHECK-NEXT: add i32{{.*}}, 6
 ; CHECK-NEXT: ret i32
@@ -185,7 +185,7 @@ define i32 @test13(i32 %X1, i32 %X2, i32 %X3) {
   %C = mul i32 %X1, %X3  ; X1*X3
   %D = add i32 %B, %C    ; -X1*X2 + X1*X3 -> X1*(X3-X2)
   ret i32 %D
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK-NEXT: sub i32 %X3, %X2
 ; CHECK-NEXT: mul i32 {{.*}}, %X1
 ; CHECK-NEXT: ret i32
@@ -197,7 +197,7 @@ define i32 @test14(i32 %X1, i32 %X2) {
   %C = mul i32 %X2, -47  ; X2*-47
   %D = add i32 %B, %C    ; X1*47 + X2*-47 -> 47*(X1-X2)
   ret i32 %D
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK-NEXT: sub i32 %X1, %X2
 ; CHECK-NEXT: mul i32 {{.*}}, 47
 ; CHECK-NEXT: ret i32
@@ -210,7 +210,7 @@ define i32 @test15(i32 %X1, i32 %X2, i32 %X3) {
   %C = and i1 %A, %B
   %D = select i1 %C, i32 %X1, i32 0
   ret i32 %D
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 ; CHECK: and i1 %A, %B
 }
 
diff --git a/test/Transforms/Reassociate/inverses.ll b/test/Transforms/Reassociate/inverses.ll
index 34abdc7..afe076c 100644
--- a/test/Transforms/Reassociate/inverses.ll
+++ b/test/Transforms/Reassociate/inverses.ll
@@ -6,7 +6,7 @@ define i32 @test1(i32 %a, i32 %b) {
         ; (A&B)&~A == 0
 	%tmp.5 = and i32 %tmp.2, %tmp.4
 	ret i32 %tmp.5
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret i32 0
 }
 
@@ -17,7 +17,7 @@ define i32 @test2(i32 %a, i32 %b) {
 	; A&~A == 0
         %tmp.5 = and i32 %tmp.2, %tmp.4
 	ret i32 %tmp.5
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: ret i32 0
 }
 
@@ -28,7 +28,7 @@ define i32 @test3(i32 %b, i32 %a) {
         ; (b+(a+1234))+-a -> b+1234
   	%tmp.5 = add i32 %tmp.2, %tmp.4
 	ret i32 %tmp.5
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: %tmp.5 = add i32 %b, 1234
 ; CHECK: ret i32 %tmp.5
 }
diff --git a/test/Transforms/Reassociate/mulfactor.ll b/test/Transforms/Reassociate/mulfactor.ll
index 6c099b4..951228e 100644
--- a/test/Transforms/Reassociate/mulfactor.ll
+++ b/test/Transforms/Reassociate/mulfactor.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -reassociate -S | FileCheck %s
 
 define i32 @test1(i32 %a, i32 %b) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: mul i32 %a, %a
 ; CHECK-NEXT: mul i32 %a, 2
 ; CHECK-NEXT: add
@@ -20,7 +20,7 @@ entry:
 }
 
 define i32 @test2(i32 %t) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: mul
 ; CHECK-NEXT: add
 ; CHECK-NEXT: ret
@@ -35,7 +35,7 @@ entry:
 
 define i32 @test3(i32 %x) {
 ; (x^8)
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
@@ -54,7 +54,7 @@ entry:
 
 define i32 @test4(i32 %x) {
 ; (x^7)
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
@@ -73,7 +73,7 @@ entry:
 
 define i32 @test5(i32 %x, i32 %y) {
 ; (x^4) * (y^2)
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
@@ -90,7 +90,7 @@ entry:
 
 define i32 @test6(i32 %x, i32 %y, i32 %z) {
 ; (x^5) * (y^3) * z
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
@@ -113,7 +113,7 @@ entry:
 
 define i32 @test7(i32 %x, i32 %y, i32 %z) {
 ; (x^4) * (y^3) * (z^2)
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
diff --git a/test/Transforms/Reassociate/multistep.ll b/test/Transforms/Reassociate/multistep.ll
index 7466d2e..d794647 100644
--- a/test/Transforms/Reassociate/multistep.ll
+++ b/test/Transforms/Reassociate/multistep.ll
@@ -2,7 +2,7 @@
 
 define i64 @multistep1(i64 %a, i64 %b, i64 %c) {
 ; Check that a*a*b+a*a*c is turned into a*(a*(b+c)).
-; CHECK: @multistep1
+; CHECK-LABEL: @multistep1(
   %t0 = mul i64 %a, %b
   %t1 = mul i64 %a, %t0 ; a*(a*b)
   %t2 = mul i64 %a, %c
@@ -17,7 +17,7 @@ define i64 @multistep1(i64 %a, i64 %b, i64 %c) {
 
 define i64 @multistep2(i64 %a, i64 %b, i64 %c, i64 %d) {
 ; Check that a*b+a*c+d is turned into a*(b+c)+d.
-; CHECK: @multistep2
+; CHECK-LABEL: @multistep2(
   %t0 = mul i64 %a, %b
   %t1 = mul i64 %a, %c
   %t2 = add i64 %t1, %d ; a*c+d
diff --git a/test/Transforms/Reassociate/no-op.ll b/test/Transforms/Reassociate/no-op.ll
index 0444cf0..7b02df9 100644
--- a/test/Transforms/Reassociate/no-op.ll
+++ b/test/Transforms/Reassociate/no-op.ll
@@ -8,7 +8,7 @@ declare void @use(i32)
 define void @test1(i32 %a, i32 %b) {
 ; Shouldn't change or move any of the add instructions.  Should commute but
 ; otherwise not change or move any of the mul instructions.
-; CHECK: @test1
+; CHECK-LABEL: @test1(
   %a0 = add nsw i32 %a, 1
 ; CHECK-NEXT: %a0 = add nsw i32 %a, 1
   %m0 = mul nsw i32 3, %a
@@ -25,7 +25,7 @@ define void @test1(i32 %a, i32 %b) {
 
 define void @test2(i32 %a, i32 %b, i32 %c, i32 %d) {
 ; The initial add doesn't change so should not lose the nsw flag.
-; CHECK: @test2
+; CHECK-LABEL: @test2(
   %a0 = add nsw i32 %b, %a
 ; CHECK-NEXT: %a0 = add nsw i32 %b, %a
   %a1 = add nsw i32 %a0, %d
diff --git a/test/Transforms/Reassociate/optional-flags.ll b/test/Transforms/Reassociate/optional-flags.ll
index 40f7d5b..bf599be 100644
--- a/test/Transforms/Reassociate/optional-flags.ll
+++ b/test/Transforms/Reassociate/optional-flags.ll
@@ -3,7 +3,7 @@
 
 ; Reassociate should clear optional flags like nsw when reassociating.
 
-; CHECK: @test0
+; CHECK-LABEL: @test0(
 ; CHECK: %y = add i64 %b, %a
 ; CHECK: %z = add i64 %y, %c
 define i64 @test0(i64 %a, i64 %b, i64 %c) {
@@ -12,7 +12,7 @@ define i64 @test0(i64 %a, i64 %b, i64 %c) {
   ret i64 %z
 }
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %y = add i64 %b, %a
 ; CHECK: %z = add i64 %y, %c
 define i64 @test1(i64 %a, i64 %b, i64 %c) {
diff --git a/test/Transforms/Reassociate/repeats.ll b/test/Transforms/Reassociate/repeats.ll
index 6a02047..547cb0a 100644
--- a/test/Transforms/Reassociate/repeats.ll
+++ b/test/Transforms/Reassociate/repeats.ll
@@ -3,14 +3,14 @@
 ; Tests involving repeated operations on the same value.
 
 define i8 @nilpotent(i8 %x) {
-; CHECK: @nilpotent
+; CHECK-LABEL: @nilpotent(
   %tmp = xor i8 %x, %x
   ret i8 %tmp
 ; CHECK: ret i8 0
 }
 
 define i2 @idempotent(i2 %x) {
-; CHECK: @idempotent
+; CHECK-LABEL: @idempotent(
   %tmp1 = and i2 %x, %x
   %tmp2 = and i2 %tmp1, %x
   %tmp3 = and i2 %tmp2, %x
@@ -19,7 +19,7 @@ define i2 @idempotent(i2 %x) {
 }
 
 define i2 @add(i2 %x) {
-; CHECK: @add
+; CHECK-LABEL: @add(
   %tmp1 = add i2 %x, %x
   %tmp2 = add i2 %tmp1, %x
   %tmp3 = add i2 %tmp2, %x
@@ -28,7 +28,7 @@ define i2 @add(i2 %x) {
 }
 
 define i2 @cst_add() {
-; CHECK: @cst_add
+; CHECK-LABEL: @cst_add(
   %tmp1 = add i2 1, 1
   %tmp2 = add i2 %tmp1, 1
   ret i2 %tmp2
@@ -36,7 +36,7 @@ define i2 @cst_add() {
 }
 
 define i8 @cst_mul() {
-; CHECK: @cst_mul
+; CHECK-LABEL: @cst_mul(
   %tmp1 = mul i8 3, 3
   %tmp2 = mul i8 %tmp1, 3
   %tmp3 = mul i8 %tmp2, 3
@@ -47,7 +47,7 @@ define i8 @cst_mul() {
 
 define i3 @foo3x5(i3 %x) {
 ; Can be done with two multiplies.
-; CHECK: @foo3x5
+; CHECK-LABEL: @foo3x5(
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: ret
@@ -60,7 +60,7 @@ define i3 @foo3x5(i3 %x) {
 
 define i3 @foo3x6(i3 %x) {
 ; Can be done with two multiplies.
-; CHECK: @foo3x6
+; CHECK-LABEL: @foo3x6(
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: ret
@@ -74,7 +74,7 @@ define i3 @foo3x6(i3 %x) {
 
 define i3 @foo3x7(i3 %x) {
 ; Can be done with two multiplies.
-; CHECK: @foo3x7
+; CHECK-LABEL: @foo3x7(
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: ret
@@ -89,7 +89,7 @@ define i3 @foo3x7(i3 %x) {
 
 define i4 @foo4x8(i4 %x) {
 ; Can be done with two multiplies.
-; CHECK: @foo4x8
+; CHECK-LABEL: @foo4x8(
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: ret
@@ -105,7 +105,7 @@ define i4 @foo4x8(i4 %x) {
 
 define i4 @foo4x9(i4 %x) {
 ; Can be done with three multiplies.
-; CHECK: @foo4x9
+; CHECK-LABEL: @foo4x9(
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
@@ -123,7 +123,7 @@ define i4 @foo4x9(i4 %x) {
 
 define i4 @foo4x10(i4 %x) {
 ; Can be done with three multiplies.
-; CHECK: @foo4x10
+; CHECK-LABEL: @foo4x10(
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
@@ -142,7 +142,7 @@ define i4 @foo4x10(i4 %x) {
 
 define i4 @foo4x11(i4 %x) {
 ; Can be done with four multiplies.
-; CHECK: @foo4x11
+; CHECK-LABEL: @foo4x11(
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
@@ -163,7 +163,7 @@ define i4 @foo4x11(i4 %x) {
 
 define i4 @foo4x12(i4 %x) {
 ; Can be done with two multiplies.
-; CHECK: @foo4x12
+; CHECK-LABEL: @foo4x12(
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: ret
@@ -183,7 +183,7 @@ define i4 @foo4x12(i4 %x) {
 
 define i4 @foo4x13(i4 %x) {
 ; Can be done with three multiplies.
-; CHECK: @foo4x13
+; CHECK-LABEL: @foo4x13(
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
@@ -205,7 +205,7 @@ define i4 @foo4x13(i4 %x) {
 
 define i4 @foo4x14(i4 %x) {
 ; Can be done with three multiplies.
-; CHECK: @foo4x14
+; CHECK-LABEL: @foo4x14(
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
@@ -228,7 +228,7 @@ define i4 @foo4x14(i4 %x) {
 
 define i4 @foo4x15(i4 %x) {
 ; Can be done with four multiplies.
-; CHECK: @foo4x15
+; CHECK-LABEL: @foo4x15(
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
 ; CHECK-NEXT: mul
diff --git a/test/Transforms/Reassociate/xor_reassoc.ll b/test/Transforms/Reassociate/xor_reassoc.ll
index b9353c7..a226898 100644
--- a/test/Transforms/Reassociate/xor_reassoc.ll
+++ b/test/Transforms/Reassociate/xor_reassoc.ll
@@ -14,7 +14,7 @@ define i32 @xor1(i32 %x) {
   %xor = xor i32 %or, %or1
   ret i32 %xor
 
-;CHECK: @xor1
+;CHECK-LABEL: @xor1(
 ;CHECK: %and.ra = and i32 %x, 435
 ;CHECK: %xor = xor i32 %and.ra, 435
 }
@@ -28,7 +28,7 @@ define i32 @xor2(i32 %x, i32 %y) {
   %xor2 = xor i32 %xor, %and1
   ret i32 %xor2
 
-;CHECK: @xor2
+;CHECK-LABEL: @xor2(
 ;CHECK: %and.ra = and i32 %x, 435
 ;CHECK: %xor2 = xor i32 %and.ra, %y
 }
@@ -42,7 +42,7 @@ define i32 @xor3(i32 %x, i32 %y) {
   %xor1 = xor i32 %xor, %and
   ret i32 %xor1
 
-;CHECK: @xor3
+;CHECK-LABEL: @xor3(
 ;CHECK: %and.ra = and i32 %x, -436
 ;CHECK: %xor = xor i32 %y, 123
 ;CHECK: %xor1 = xor i32 %xor, %and.ra
@@ -54,7 +54,7 @@ define i32 @xor4(i32 %x, i32 %y) {
   %xor = xor i32 %y, 435
   %xor1 = xor i32 %xor, %and
   ret i32 %xor1
-; CHECK: @xor4
+; CHECK-LABEL: @xor4(
 ; CHECK: %and = and i32 %x, -124
 ; CHECK: %xor = xor i32 %y, 435
 ; CHECK: %xor1 = xor i32 %xor, %and
@@ -74,7 +74,7 @@ define i32 @xor_special1(i32 %x, i32 %y) {
   %and = and i32 %x, -124
   %xor1 = xor i32 %xor, %and
   ret i32 %xor1
-; CHECK: @xor_special1
+; CHECK-LABEL: @xor_special1(
 ; CHECK: %xor1 = xor i32 %y, 123
 ; CHECK: ret i32 %xor1
 }
@@ -87,7 +87,7 @@ define i32 @xor_special2(i32 %x, i32 %y) {
   %and = and i32 %x, 123
   %xor1 = xor i32 %xor, %and
   ret i32 %xor1
-; CHECK: @xor_special2
+; CHECK-LABEL: @xor_special2(
 ; CHECK: %xor = xor i32 %y, 123
 ; CHECK: %xor1 = xor i32 %xor, %x
 ; CHECK: ret i32 %xor1
@@ -99,7 +99,7 @@ define i32 @xor_special3(i32 %x) {
   %or1 = or i32 %x, 123
   %xor = xor i32 %or, %or1
   ret i32 %xor
-;CHECK: @xor_special3
+;CHECK-LABEL: @xor_special3(
 ;CHECK: ret i32 0
 }
 
@@ -109,7 +109,7 @@ define i32 @xor_special4(i32 %x) {
   %or1 = and i32 123, %x
   %xor = xor i32 %or, %or1
   ret i32 %xor
-;CHECK: @xor_special4
+;CHECK-LABEL: @xor_special4(
 ;CHECK: ret i32 0
 }
 
@@ -129,7 +129,7 @@ define i32 @xor_ra_size1(i32 %x) {
 
   %add = add i32 %xor, %or
   ret i32 %add
-;CHECK: @xor_ra_size1
+;CHECK-LABEL: @xor_ra_size1(
 ;CHECK: %xor = xor i32 %and.ra, 435
 }
 
@@ -145,7 +145,7 @@ define i32 @xor_ra_size2(i32 %x) {
   %add2 = add i32 %add, %or1
   ret i32 %add2
 
-;CHECK: @xor_ra_size2
+;CHECK-LABEL: @xor_ra_size2(
 ;CHECK: %or1 = or i32 %x, 456
 ;CHECK: %xor = xor i32 %or, %or1
 }
@@ -188,6 +188,6 @@ define i32 @xor_bug2(i32, i32, i32, i32) {
   %19 = add i32 %18, %12
   %20 = add i32 %19, %15
   ret i32 %20
-;CHECK: @xor_bug2
+;CHECK-LABEL: @xor_bug2(
 ;CHECK: xor i32 %5, 891034567
 }
diff --git a/test/Transforms/SCCP/atomic-load-store.ll b/test/Transforms/SCCP/atomic-load-store.ll
index 09061f0..53e4c10 100644
--- a/test/Transforms/SCCP/atomic-load-store.ll
+++ b/test/Transforms/SCCP/atomic-load-store.ll
@@ -16,7 +16,7 @@ F:
 	store atomic i32 123, i32* @G seq_cst, align 4
 	ret i32 0
 }
-; CHECK: define i32 @test1
+; CHECK-LABEL: define i32 @test1(
 ; CHECK-NOT: store
 ; CHECK: ret i32 17
 
@@ -25,6 +25,6 @@ define i32 @test2() {
 	ret i32 %V
 }
 
-; CHECK: define i32 @test2
+; CHECK-LABEL: define i32 @test2(
 ; CHECK-NOT: load
 ; CHECK: ret i32 222
diff --git a/test/Transforms/SCCP/ipsccp-addr-taken.ll b/test/Transforms/SCCP/ipsccp-addr-taken.ll
index b49da97..ca586a0 100644
--- a/test/Transforms/SCCP/ipsccp-addr-taken.ll
+++ b/test/Transforms/SCCP/ipsccp-addr-taken.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-apple-darwin10.0.0"
 define internal i32 @foo() nounwind noinline ssp {
 entry:
   ret i32 0
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK: entry:
 ; CHECK: ret i32 0
 }
diff --git a/test/Transforms/SCCP/ipsccp-basic.ll b/test/Transforms/SCCP/ipsccp-basic.ll
index 8340f0c..c1c6c92 100644
--- a/test/Transforms/SCCP/ipsccp-basic.ll
+++ b/test/Transforms/SCCP/ipsccp-basic.ll
@@ -6,14 +6,14 @@ define internal i32 @test1a(i32 %A) {
 	%X = add i32 1, 2
 	ret i32 %A
 }
-; CHECK: define internal i32 @test1a
+; CHECK-LABEL: define internal i32 @test1a(
 ; CHECK: ret i32 undef
 
 define i32 @test1b() {
 	%X = call i32 @test1a( i32 17 )
 	ret i32 %X
 
-; CHECK: define i32 @test1b
+; CHECK-LABEL: define i32 @test1b(
 ; CHECK: ret i32 17
 }
 
@@ -31,7 +31,7 @@ F:
 	%C.upgrd.1 = call i32 @test2a(i32 1)
 	ret i32 %C.upgrd.1
 }
-; CHECK: define internal i32 @test2a
+; CHECK-LABEL: define internal i32 @test2a(
 ; CHECK-NEXT: br label %T
 ; CHECK: ret i32 undef
 
@@ -40,7 +40,7 @@ define i32 @test2b() {
 	%X = call i32 @test2a(i32 0)
 	ret i32 %X
 }
-; CHECK: define i32 @test2b
+; CHECK-LABEL: define i32 @test2b(
 ; CHECK-NEXT: %X = call i32 @test2a(i32 0)
 ; CHECK-NEXT: ret i32 0
 
@@ -54,7 +54,7 @@ define void @test3a() {
 	store i32 %X, i32* @G
 	ret void
 }
-; CHECK: define void @test3a
+; CHECK-LABEL: define void @test3a(
 ; CHECK-NEXT: ret void
 
 
@@ -69,7 +69,7 @@ F:
 	store i32 123, i32* @G
 	ret i32 0
 }
-; CHECK: define i32 @test3b
+; CHECK-LABEL: define i32 @test3b(
 ; CHECK-NOT: store
 ; CHECK: ret i32 0
 
@@ -102,7 +102,7 @@ B:
 define internal i64 @test4c(i64 %a) {
   ret i64 %a
 }
-; CHECK: define internal i64 @test4c
+; CHECK-LABEL: define internal i64 @test4c(
 ; CHECK: ret i64 undef
 
 
@@ -149,7 +149,7 @@ define i64 @test6b() {
   %a = call i64 @test6a()
   ret i64 %a
 }
-; CHECK: define i64 @test6b
+; CHECK-LABEL: define i64 @test6b(
 ; CHECK: ret i64 0
 
 ;;======================== test7
@@ -162,7 +162,7 @@ define internal %T @test7a(i32 %A) {
   %mrv0 = insertvalue %T undef, i32 %X, 0
   %mrv1 = insertvalue %T %mrv0, i32 %A, 1
   ret %T %mrv1
-; CHECK: @test7a
+; CHECK-LABEL: @test7a(
 ; CHECK-NEXT: %mrv0 = insertvalue %T undef, i32 18, 0
 ; CHECK-NEXT: %mrv1 = insertvalue %T %mrv0, i32 17, 1
 }
@@ -172,7 +172,7 @@ define i32 @test7b() {
         %Y = extractvalue %T %X, 0
 	%Z = add i32 %Y, %Y
 	ret i32 %Z
-; CHECK: define i32 @test7b
+; CHECK-LABEL: define i32 @test7b(
 ; CHECK-NEXT: call %T @test7a(i32 17)
 ; CHECK-NEXT: ret i32 36
 }
@@ -183,7 +183,7 @@ define i32 @test7b() {
 define internal {} @test8a(i32 %A, i32* %P) {
   store i32 %A, i32* %P
   ret {} {}
-; CHECK: @test8a
+; CHECK-LABEL: @test8a(
 ; CHECK-NEXT: store i32 5, 
 ; CHECK-NEXT: ret 
 }
@@ -191,7 +191,7 @@ define internal {} @test8a(i32 %A, i32* %P) {
 define void @test8b(i32* %P) {
     %X = call {} @test8a(i32 5, i32* %P)
     ret void
-; CHECK: define void @test8b
+; CHECK-LABEL: define void @test8b(
 ; CHECK-NEXT: call {} @test8a
 ; CHECK-NEXT: ret void
 }
@@ -216,7 +216,7 @@ define i32 @test10a() nounwind {
 entry:
   %call = call i32 @test10b(i32 undef)
   ret i32 %call
-; CHECK: define i32 @test10a
+; CHECK-LABEL: define i32 @test10a(
 ; CHECK: ret i32 0
 }
 
@@ -224,6 +224,6 @@ define internal i32 @test10b(i32 %x) nounwind {
 entry:
   %r = and i32 %x, 1
   ret i32 %r
-; CHECK: define internal i32 @test10b
+; CHECK-LABEL: define internal i32 @test10b(
 ; CHECK: ret i32 undef
 }
diff --git a/test/Transforms/SCCP/sccptest.ll b/test/Transforms/SCCP/sccptest.ll
index a719f6c..5cc5087 100644
--- a/test/Transforms/SCCP/sccptest.ll
+++ b/test/Transforms/SCCP/sccptest.ll
@@ -14,7 +14,7 @@ BB3:		; preds = %BB2, %BB1
 	%Ret = phi i32 [ %Val, %BB1 ], [ 1, %BB2 ]		; <i32> [#uses=1]
 	ret i32 %Ret
         
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %Ret = phi i32 [ 0, %BB1 ], [ 1, %BB2 ]
 }
 
@@ -22,7 +22,7 @@ BB3:		; preds = %BB2, %BB1
 ; that SCCP gets right.
 ;
 define i32 @test2(i32 %i0, i32 %j0) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 BB1:
 	br label %BB2
 BB2:
diff --git a/test/Transforms/SCCP/switch.ll b/test/Transforms/SCCP/switch.ll
index 9f93423..155faa5 100644
--- a/test/Transforms/SCCP/switch.ll
+++ b/test/Transforms/SCCP/switch.ll
@@ -4,7 +4,7 @@
 ; with no cases.
 declare void @foo()
 define void @test1() {
-; CHECK: define void @test1
+; CHECK-LABEL: define void @test1(
 ; CHECK: call void @foo()
   switch i32 undef, label %d []
 d:
diff --git a/test/Transforms/SCCP/undef-resolve.ll b/test/Transforms/SCCP/undef-resolve.ll
index a1a600c..2b40183 100644
--- a/test/Transforms/SCCP/undef-resolve.ll
+++ b/test/Transforms/SCCP/undef-resolve.ll
@@ -5,7 +5,7 @@
 define double @test1() {
   %t = sitofp i32 undef to double
   ret double %t
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: ret double 0.0
 }
 
@@ -13,7 +13,7 @@ define double @test1() {
 ; rdar://7832370
 ; Check that lots of stuff doesn't get turned into undef.
 define i32 @test2() nounwind readnone ssp {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 init:
   br label %control.outer.outer
 
@@ -110,7 +110,7 @@ bb1:                                              ; preds = %bb1.us-lcssa, %bb1.
 define i32 @test3() {
   %t = xor i32 undef, undef
   ret i32 %t
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: ret i32 0
 }
 
@@ -118,7 +118,7 @@ define i32 @test3() {
 define double @test4(double %x) {
   %t = fadd double %x, undef
   ret double %t
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: fadd double %x, undef
 }
 
@@ -126,7 +126,7 @@ define double @test4(double %x) {
 define i32 @test5() {
   %t = sext i8 undef to i32
   ret i32 %t
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: ret i32 0
 }
 
@@ -134,7 +134,7 @@ define i32 @test5() {
 define i32 @test6() {
   %t = ashr i32 undef, 31
   ret i32 %t
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: ret i32 -1
 }
 
@@ -142,7 +142,7 @@ define i32 @test6() {
 define i32 @test7() {
   %t = lshr i32 undef, 31
   ret i32 %t
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: ret i32 0
 }
 
@@ -150,7 +150,7 @@ define i32 @test7() {
 define i1 @test8() {
   %t = icmp eq i32 undef, -1
   ret i1 %t
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: ret i1 undef
 }
 
@@ -158,7 +158,7 @@ define i1 @test8() {
 define i1 @test9() {
   %t = icmp ugt i32 undef, -1
   ret i1 %t
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK: icmp ugt
 }
 
@@ -167,6 +167,6 @@ define i64 @test10() {
 entry:
   %e = extractvalue { i64, i64 } undef, 1
   ret i64 %e
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK: ret i64 undef
 }
diff --git a/test/Transforms/SLPVectorizer/X86/barriercall.ll b/test/Transforms/SLPVectorizer/X86/barriercall.ll
index 04eb8f9..bba2855 100644
--- a/test/Transforms/SLPVectorizer/X86/barriercall.ll
+++ b/test/Transforms/SLPVectorizer/X86/barriercall.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
-;CHECK: @foo
+;CHECK-LABEL: @foo(
 ;CHECK: store <4 x i32>
 ;CHECK: ret
 define i32 @foo(i32* nocapture %A, i32 %n) {
diff --git a/test/Transforms/SLPVectorizer/X86/cast.ll b/test/Transforms/SLPVectorizer/X86/cast.ll
index 344dbbc..e340fba 100644
--- a/test/Transforms/SLPVectorizer/X86/cast.ll
+++ b/test/Transforms/SLPVectorizer/X86/cast.ll
@@ -9,7 +9,7 @@ target triple = "x86_64-apple-macosx10.9.0"
 ;     A[2] = B[2];
 ;     A[3] = B[3];
 ; }
-;CHECK: @foo
+;CHECK-LABEL: @foo(
 ;CHECK: load <4 x i8>
 ;CHECK: sext
 ;CHECK: store <4 x i32>
diff --git a/test/Transforms/SLPVectorizer/X86/cmp_sel.ll b/test/Transforms/SLPVectorizer/X86/cmp_sel.ll
new file mode 100644
index 0000000..0c124a7
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/cmp_sel.ll
@@ -0,0 +1,32 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+; int foo(double * restrict A, double * restrict B, double G) {
+;   A[0] = (B[10] ? G : 1);
+;   A[1] = (B[11] ? G : 1);
+; }
+
+;CHECK-LABEL: @foo(
+;CHECK: load <2 x double>
+;CHECK: fcmp une <2 x double>
+;CHECK: select <2 x i1>
+;CHECK: store <2 x double>
+;CHECK: ret i32 undef
+define i32 @foo(double* noalias nocapture %A, double* noalias nocapture %B, double %G) {
+entry:
+  %arrayidx = getelementptr inbounds double* %B, i64 10
+  %0 = load double* %arrayidx, align 8
+  %tobool = fcmp une double %0, 0.000000e+00
+  %cond = select i1 %tobool, double %G, double 1.000000e+00
+  store double %cond, double* %A, align 8
+  %arrayidx2 = getelementptr inbounds double* %B, i64 11
+  %1 = load double* %arrayidx2, align 8
+  %tobool3 = fcmp une double %1, 0.000000e+00
+  %cond7 = select i1 %tobool3, double %G, double 1.000000e+00
+  %arrayidx8 = getelementptr inbounds double* %A, i64 1
+  store double %cond7, double* %arrayidx8, align 8
+  ret i32 undef
+}
+
diff --git a/test/Transforms/SLPVectorizer/X86/compare-reduce.ll b/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
index 05f8e61..9653d18 100644
--- a/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
+++ b/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
@@ -5,7 +5,7 @@ target triple = "x86_64-apple-macosx10.7.0"
 
 @.str = private unnamed_addr constant [6 x i8] c"bingo\00", align 1
 
-;CHECK: @reduce_compare
+;CHECK-LABEL: @reduce_compare(
 ;CHECK: load <2 x double>
 ;CHECK: fmul <2 x double>
 ;CHECK: fmul <2 x double>
diff --git a/test/Transforms/SLPVectorizer/X86/crash_7zip.ll b/test/Transforms/SLPVectorizer/X86/crash_7zip.ll
new file mode 100644
index 0000000..51b1c08
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/crash_7zip.ll
@@ -0,0 +1,38 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+%struct.CLzmaDec.1.28.55.82.103.124.145.166.181.196.229.259.334 = type { %struct._CLzmaProps.0.27.54.81.102.123.144.165.180.195.228.258.333, i16*, i8*, i8*, i32, i32, i64, i64, i32, i32, i32, [4 x i32], i32, i32, i32, i32, i32, [20 x i8] }
+%struct._CLzmaProps.0.27.54.81.102.123.144.165.180.195.228.258.333 = type { i32, i32, i32, i32 }
+
+define fastcc void @LzmaDec_DecodeReal2(%struct.CLzmaDec.1.28.55.82.103.124.145.166.181.196.229.259.334* %p) {
+entry:
+  %range20.i = getelementptr inbounds %struct.CLzmaDec.1.28.55.82.103.124.145.166.181.196.229.259.334* %p, i64 0, i32 4
+  %code21.i = getelementptr inbounds %struct.CLzmaDec.1.28.55.82.103.124.145.166.181.196.229.259.334* %p, i64 0, i32 5
+  br label %do.body66.i
+
+do.body66.i:                                      ; preds = %do.cond.i, %entry
+  %range.2.i = phi i32 [ %range.4.i, %do.cond.i ], [ undef, %entry ]
+  %code.2.i = phi i32 [ %code.4.i, %do.cond.i ], [ undef, %entry ]
+  %.range.2.i = select i1 undef, i32 undef, i32 %range.2.i
+  %.code.2.i = select i1 undef, i32 undef, i32 %code.2.i
+  br i1 undef, label %do.cond.i, label %if.else.i
+
+if.else.i:                                        ; preds = %do.body66.i
+  %sub91.i = sub i32 %.range.2.i, undef
+  %sub92.i = sub i32 %.code.2.i, undef
+  br label %do.cond.i
+
+do.cond.i:                                        ; preds = %if.else.i, %do.body66.i
+  %range.4.i = phi i32 [ %sub91.i, %if.else.i ], [ undef, %do.body66.i ]
+  %code.4.i = phi i32 [ %sub92.i, %if.else.i ], [ %.code.2.i, %do.body66.i ]
+  br i1 undef, label %do.body66.i, label %do.end1006.i
+
+do.end1006.i:                                     ; preds = %do.cond.i
+  %.range.4.i = select i1 undef, i32 undef, i32 %range.4.i
+  %.code.4.i = select i1 undef, i32 undef, i32 %code.4.i
+  store i32 %.range.4.i, i32* %range20.i, align 4
+  store i32 %.code.4.i, i32* %code21.i, align 4
+  ret void
+}
diff --git a/test/Transforms/SLPVectorizer/X86/crash_bullet.ll b/test/Transforms/SLPVectorizer/X86/crash_bullet.ll
new file mode 100644
index 0000000..3898921
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/crash_bullet.ll
@@ -0,0 +1,128 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+%"struct.btTypedConstraint::btConstraintInfo1.17.157.357.417.477.960" = type { i32, i32 }
+
+define void @_ZN23btGeneric6DofConstraint8getInfo1EPN17btTypedConstraint17btConstraintInfo1E(%"struct.btTypedConstraint::btConstraintInfo1.17.157.357.417.477.960"* nocapture %info) {
+entry:
+  br i1 undef, label %if.else, label %if.then
+
+if.then:                                          ; preds = %entry
+  ret void
+
+if.else:                                          ; preds = %entry
+  %m_numConstraintRows4 = getelementptr inbounds %"struct.btTypedConstraint::btConstraintInfo1.17.157.357.417.477.960"* %info, i64 0, i32 0
+  %nub5 = getelementptr inbounds %"struct.btTypedConstraint::btConstraintInfo1.17.157.357.417.477.960"* %info, i64 0, i32 1
+  br i1 undef, label %land.lhs.true.i.1, label %if.then7.1
+
+land.lhs.true.i.1:                                ; preds = %if.else
+  br i1 undef, label %for.inc.1, label %if.then7.1
+
+if.then7.1:                                       ; preds = %land.lhs.true.i.1, %if.else
+  %inc.1 = add nsw i32 0, 1
+  store i32 %inc.1, i32* %m_numConstraintRows4, align 4
+  %dec.1 = add nsw i32 6, -1
+  store i32 %dec.1, i32* %nub5, align 4
+  br label %for.inc.1
+
+for.inc.1:                                        ; preds = %if.then7.1, %land.lhs.true.i.1
+  %0 = phi i32 [ %dec.1, %if.then7.1 ], [ 6, %land.lhs.true.i.1 ]
+  %1 = phi i32 [ %inc.1, %if.then7.1 ], [ 0, %land.lhs.true.i.1 ]
+  %inc.2 = add nsw i32 %1, 1
+  store i32 %inc.2, i32* %m_numConstraintRows4, align 4
+  %dec.2 = add nsw i32 %0, -1
+  store i32 %dec.2, i32* %nub5, align 4
+  unreachable
+}
+
+%class.GIM_TRIANGLE_CALCULATION_CACHE.9.34.69.94.119.144.179.189.264.284.332 = type { float, [3 x %class.btVector3.5.30.65.90.115.140.175.185.260.280.330], [3 x %class.btVector3.5.30.65.90.115.140.175.185.260.280.330], %class.btVector4.7.32.67.92.117.142.177.187.262.282.331, %class.btVector4.7.32.67.92.117.142.177.187.262.282.331, %class.btVector3.5.30.65.90.115.140.175.185.260.280.330, %class.btVector3.5.30.65.90.115.140.175.185.260.280.330, %class.btVector3.5.30.65.90.115.140.175.185.260.280.330, %class.btVector3.5.30.65.90.115.140.175.185.260.280.330, [4 x float], float, float, [4 x float], float, float, [16 x %class.btVector3.5.30.65.90.115.140.175.185.260.280.330], [16 x %class.btVector3.5.30.65.90.115.140.175.185.260.280.330], [16 x %class.btVector3.5.30.65.90.115.140.175.185.260.280.330] }
+%class.btVector3.5.30.65.90.115.140.175.185.260.280.330 = type { [4 x float] }
+%class.btVector4.7.32.67.92.117.142.177.187.262.282.331 = type { %class.btVector3.5.30.65.90.115.140.175.185.260.280.330 }
+
+define void @_ZN30GIM_TRIANGLE_CALCULATION_CACHE18triangle_collisionERK9btVector3S2_S2_fS2_S2_S2_fR25GIM_TRIANGLE_CONTACT_DATA(%class.GIM_TRIANGLE_CALCULATION_CACHE.9.34.69.94.119.144.179.189.264.284.332* %this) {
+entry:
+  %arrayidx26 = getelementptr inbounds %class.GIM_TRIANGLE_CALCULATION_CACHE.9.34.69.94.119.144.179.189.264.284.332* %this, i64 0, i32 2, i64 0, i32 0, i64 1
+  %arrayidx36 = getelementptr inbounds %class.GIM_TRIANGLE_CALCULATION_CACHE.9.34.69.94.119.144.179.189.264.284.332* %this, i64 0, i32 2, i64 0, i32 0, i64 2
+  %0 = load float* %arrayidx36, align 4
+  %add587 = fadd float undef, undef
+  %sub600 = fsub float %add587, undef
+  store float %sub600, float* undef, align 4
+  %sub613 = fsub float %add587, %sub600
+  store float %sub613, float* %arrayidx26, align 4
+  %add626 = fadd float %0, undef
+  %sub639 = fsub float %add626, undef
+  %sub652 = fsub float %add626, %sub639
+  store float %sub652, float* %arrayidx36, align 4
+  br i1 undef, label %if.else1609, label %if.then1595
+
+if.then1595:                                      ; preds = %entry
+  br i1 undef, label %return, label %for.body.lr.ph.i.i1702
+
+for.body.lr.ph.i.i1702:                           ; preds = %if.then1595
+  unreachable
+
+if.else1609:                                      ; preds = %entry
+  unreachable
+
+return:                                           ; preds = %if.then1595
+  ret void
+}
+
+define void @_Z8dBoxBox2RK9btVector3PKfS1_S1_S3_S1_RS_PfPiiP12dContactGeomiRN36btDiscreteCollisionDetectorInterface6ResultE() {
+entry:
+  %add8.i2343 = fadd float undef, undef
+  %add8.i2381 = fadd float undef, undef
+  br i1 undef, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  br i1 undef, label %return, label %if.end111
+
+if.end111:                                        ; preds = %if.end
+  br i1 undef, label %return, label %if.end136
+
+if.end136:                                        ; preds = %if.end111
+  br i1 undef, label %return, label %if.end162
+
+if.end162:                                        ; preds = %if.end136
+  br i1 undef, label %return, label %if.end189
+
+if.end189:                                        ; preds = %if.end162
+  br i1 undef, label %return, label %if.end216
+
+if.end216:                                        ; preds = %if.end189
+  br i1 undef, label %if.then218, label %if.end225
+
+if.then218:                                       ; preds = %if.end216
+  br label %if.end225
+
+if.end225:                                        ; preds = %if.then218, %if.end216
+  br i1 undef, label %return, label %if.end248
+
+if.end248:                                        ; preds = %if.end225
+  br i1 undef, label %return, label %if.end304
+
+if.end304:                                        ; preds = %if.end248
+  %mul341 = fmul float undef, %add8.i2343
+  %mul344 = fmul float undef, %add8.i2381
+  %sub345 = fsub float %mul341, %mul344
+  br i1 undef, label %return, label %if.end361
+
+if.end361:                                        ; preds = %if.end304
+  %mul364 = fmul float %add8.i2381, %add8.i2381
+  br i1 undef, label %if.then370, label %if.end395
+
+if.then370:                                       ; preds = %if.end361
+  br i1 undef, label %if.then374, label %if.end395
+
+if.then374:                                       ; preds = %if.then370
+  %cmp392 = fcmp olt float %sub345, 0.000000e+00
+  br label %if.end395
+
+if.end395:                                        ; preds = %if.then374, %if.then370, %if.end361
+  unreachable
+
+return:                                           ; preds = %if.end304, %if.end248, %if.end225, %if.end189, %if.end162, %if.end136, %if.end111, %if.end, %entry
+  ret void
+}
diff --git a/test/Transforms/SLPVectorizer/X86/crash_bullet3.ll b/test/Transforms/SLPVectorizer/X86/crash_bullet3.ll
new file mode 100644
index 0000000..931195e
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/crash_bullet3.ll
@@ -0,0 +1,88 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+%class.btVector3.23.221.463.485.507.573.595.683.727.749.815.837.991.1585.1607.1629.1651.1849.2047.2069.2091.2113 = type { [4 x float] }
+
+; Function Attrs: ssp uwtable
+define void @_ZN11HullLibrary15CleanupVerticesEjPK9btVector3jRjPS0_fRS0_(%class.btVector3.23.221.463.485.507.573.595.683.727.749.815.837.991.1585.1607.1629.1651.1849.2047.2069.2091.2113* %vertices) #0 align 2 {
+entry:
+  br i1 undef, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  br label %for.body
+
+for.body:                                         ; preds = %if.end22.2, %if.end
+  br i1 undef, label %if.then17.1, label %if.end22.1
+
+for.end36:                                        ; preds = %if.end22.2
+  br label %for.body144
+
+for.body144:                                      ; preds = %for.body144, %for.end36
+  br i1 undef, label %for.end227, label %for.body144
+
+for.end227:                                       ; preds = %for.body144
+  br i1 undef, label %for.end271, label %for.body233
+
+for.body233:                                      ; preds = %for.body233, %for.end227
+  br i1 undef, label %for.body233, label %for.end271
+
+for.end271:                                       ; preds = %for.body233, %for.end227
+  %0 = phi float [ 0x47EFFFFFE0000000, %for.end227 ], [ undef, %for.body233 ]
+  %1 = phi float [ 0x47EFFFFFE0000000, %for.end227 ], [ undef, %for.body233 ]
+  %sub275 = fsub float undef, %1
+  %sub279 = fsub float undef, %0
+  br i1 undef, label %if.then291, label %return
+
+if.then291:                                       ; preds = %for.end271
+  %mul292 = fmul float %sub275, 5.000000e-01
+  %add294 = fadd float %1, %mul292
+  %mul295 = fmul float %sub279, 5.000000e-01
+  %add297 = fadd float %0, %mul295
+  br i1 undef, label %if.end332, label %if.else319
+
+if.else319:                                       ; preds = %if.then291
+  br i1 undef, label %if.then325, label %if.end327
+
+if.then325:                                       ; preds = %if.else319
+  br label %if.end327
+
+if.end327:                                        ; preds = %if.then325, %if.else319
+  br i1 undef, label %if.then329, label %if.end332
+
+if.then329:                                       ; preds = %if.end327
+  br label %if.end332
+
+if.end332:                                        ; preds = %if.then329, %if.end327, %if.then291
+  %dx272.1 = phi float [ %sub275, %if.then329 ], [ %sub275, %if.end327 ], [ 0x3F847AE140000000, %if.then291 ]
+  %dy276.1 = phi float [ undef, %if.then329 ], [ undef, %if.end327 ], [ 0x3F847AE140000000, %if.then291 ]
+  %sub334 = fsub float %add294, %dx272.1
+  %sub338 = fsub float %add297, %dy276.1
+  %arrayidx.i.i606 = getelementptr inbounds %class.btVector3.23.221.463.485.507.573.595.683.727.749.815.837.991.1585.1607.1629.1651.1849.2047.2069.2091.2113* %vertices, i64 0, i32 0, i64 0
+  store float %sub334, float* %arrayidx.i.i606, align 4, !tbaa !0
+  %arrayidx3.i607 = getelementptr inbounds %class.btVector3.23.221.463.485.507.573.595.683.727.749.815.837.991.1585.1607.1629.1651.1849.2047.2069.2091.2113* %vertices, i64 0, i32 0, i64 1
+  store float %sub338, float* %arrayidx3.i607, align 4, !tbaa !0
+  br label %return
+
+return:                                           ; preds = %if.end332, %for.end271, %entry
+  ret void
+
+if.then17.1:                                      ; preds = %for.body
+  br label %if.end22.1
+
+if.end22.1:                                       ; preds = %if.then17.1, %for.body
+  br i1 undef, label %if.then17.2, label %if.end22.2
+
+if.then17.2:                                      ; preds = %if.end22.1
+  br label %if.end22.2
+
+if.end22.2:                                       ; preds = %if.then17.2, %if.end22.1
+  br i1 undef, label %for.end36, label %for.body
+}
+
+attributes #0 = { ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!0 = metadata !{metadata !"float", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA"}
diff --git a/test/Transforms/SLPVectorizer/X86/crash_dequeue.ll b/test/Transforms/SLPVectorizer/X86/crash_dequeue.ll
new file mode 100644
index 0000000..ce01590
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/crash_dequeue.ll
@@ -0,0 +1,40 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+%"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731" = type { double*, double*, double*, double** }
+
+; Function Attrs: nounwind ssp uwtable
+define void @_ZSt6uniqueISt15_Deque_iteratorIdRdPdEET_S4_S4_(%"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* %__first, %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* nocapture %__last) {
+entry:
+  %_M_cur2.i.i = getelementptr inbounds %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* %__first, i64 0, i32 0
+  %0 = load double** %_M_cur2.i.i, align 8
+  %_M_first3.i.i = getelementptr inbounds %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* %__first, i64 0, i32 1
+  %_M_cur2.i.i81 = getelementptr inbounds %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* %__last, i64 0, i32 0
+  %1 = load double** %_M_cur2.i.i81, align 8
+  %_M_first3.i.i83 = getelementptr inbounds %"struct.std::_Deque_iterator.4.157.174.208.259.276.344.731"* %__last, i64 0, i32 1
+  %2 = load double** %_M_first3.i.i83, align 8
+  br i1 undef, label %_ZSt13adjacent_findISt15_Deque_iteratorIdRdPdEET_S4_S4_.exit, label %while.cond.i.preheader
+
+while.cond.i.preheader:                           ; preds = %entry
+  br label %while.cond.i
+
+while.cond.i:                                     ; preds = %while.body.i, %while.cond.i.preheader
+  br i1 undef, label %_ZSt13adjacent_findISt15_Deque_iteratorIdRdPdEET_S4_S4_.exit, label %while.body.i
+
+while.body.i:                                     ; preds = %while.cond.i
+  br i1 undef, label %_ZSt13adjacent_findISt15_Deque_iteratorIdRdPdEET_S4_S4_.exit, label %while.cond.i
+
+_ZSt13adjacent_findISt15_Deque_iteratorIdRdPdEET_S4_S4_.exit: ; preds = %while.body.i, %while.cond.i, %entry
+  %3 = phi double* [ %2, %entry ], [ %2, %while.cond.i ], [ undef, %while.body.i ]
+  %4 = phi double* [ %0, %entry ], [ %1, %while.cond.i ], [ undef, %while.body.i ]
+  store double* %4, double** %_M_cur2.i.i, align 8
+  store double* %3, double** %_M_first3.i.i, align 8
+  br i1 undef, label %if.then.i55, label %while.cond
+
+if.then.i55:                                      ; preds = %_ZSt13adjacent_findISt15_Deque_iteratorIdRdPdEET_S4_S4_.exit
+  br label %while.cond
+
+while.cond:                                       ; preds = %while.cond, %if.then.i55, %_ZSt13adjacent_findISt15_Deque_iteratorIdRdPdEET_S4_S4_.exit
+  br label %while.cond
+}
diff --git a/test/Transforms/SLPVectorizer/X86/crash_flop7.ll b/test/Transforms/SLPVectorizer/X86/crash_flop7.ll
new file mode 100644
index 0000000..e11be48
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/crash_flop7.ll
@@ -0,0 +1,46 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+; Function Attrs: nounwind ssp uwtable
+define void @main() #0 {
+entry:
+  br i1 undef, label %while.body, label %while.end
+
+while.body:                                       ; preds = %entry
+  unreachable
+
+while.end:                                        ; preds = %entry
+  br i1 undef, label %for.end80, label %for.body75.lr.ph
+
+for.body75.lr.ph:                                 ; preds = %while.end
+  br label %for.body75
+
+for.body75:                                       ; preds = %for.body75, %for.body75.lr.ph
+  br label %for.body75
+
+for.end80:                                        ; preds = %while.end
+  br i1 undef, label %for.end300, label %for.body267.lr.ph
+
+for.body267.lr.ph:                                ; preds = %for.end80
+  br label %for.body267
+
+for.body267:                                      ; preds = %for.body267, %for.body267.lr.ph
+  %s.71010 = phi double [ 0.000000e+00, %for.body267.lr.ph ], [ %add297, %for.body267 ]
+  %mul269 = fmul double undef, undef
+  %mul270 = fmul double %mul269, %mul269
+  %add282 = fadd double undef, undef
+  %mul283 = fmul double %mul269, %add282
+  %add293 = fadd double undef, undef
+  %mul294 = fmul double %mul270, %add293
+  %add295 = fadd double undef, %mul294
+  %div296 = fdiv double %mul283, %add295
+  %add297 = fadd double %s.71010, %div296
+  br i1 undef, label %for.body267, label %for.end300
+
+for.end300:                                       ; preds = %for.body267, %for.end80
+  unreachable
+}
+
+attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/Transforms/SLPVectorizer/X86/crash_lencod.ll b/test/Transforms/SLPVectorizer/X86/crash_lencod.ll
new file mode 100644
index 0000000..c02e1fa
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/crash_lencod.ll
@@ -0,0 +1,91 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+; Function Attrs: nounwind ssp uwtable
+define void @RCModelEstimator() {
+entry:
+  br i1 undef, label %for.body.lr.ph, label %for.end.thread
+
+for.end.thread:                                   ; preds = %entry
+  unreachable
+
+for.body.lr.ph:                                   ; preds = %entry
+  br i1 undef, label %for.end, label %for.body
+
+for.body:                                         ; preds = %for.body, %for.body.lr.ph
+  br i1 undef, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %for.body.lr.ph
+  br i1 undef, label %for.body3, label %if.end103
+
+for.cond14.preheader:                             ; preds = %for.inc11
+  br i1 undef, label %for.body16.lr.ph, label %if.end103
+
+for.body16.lr.ph:                                 ; preds = %for.cond14.preheader
+  br label %for.body16
+
+for.body3:                                        ; preds = %for.inc11, %for.end
+  br i1 undef, label %if.then7, label %for.inc11
+
+if.then7:                                         ; preds = %for.body3
+  br label %for.inc11
+
+for.inc11:                                        ; preds = %if.then7, %for.body3
+  br i1 false, label %for.cond14.preheader, label %for.body3
+
+for.body16:                                       ; preds = %for.body16, %for.body16.lr.ph
+  br i1 undef, label %for.end39, label %for.body16
+
+for.end39:                                        ; preds = %for.body16
+  br i1 undef, label %if.end103, label %for.cond45.preheader
+
+for.cond45.preheader:                             ; preds = %for.end39
+  br i1 undef, label %if.then88, label %if.else
+
+if.then88:                                        ; preds = %for.cond45.preheader
+  %mul89 = fmul double 0.000000e+00, 0.000000e+00
+  %mul90 = fmul double 0.000000e+00, 0.000000e+00
+  %sub91 = fsub double %mul89, %mul90
+  %div92 = fdiv double %sub91, undef
+  %mul94 = fmul double 0.000000e+00, 0.000000e+00
+  %mul95 = fmul double 0.000000e+00, 0.000000e+00
+  %sub96 = fsub double %mul94, %mul95
+  %div97 = fdiv double %sub96, undef
+  br label %if.end103
+
+if.else:                                          ; preds = %for.cond45.preheader
+  br label %if.end103
+
+if.end103:                                        ; preds = %if.else, %if.then88, %for.end39, %for.cond14.preheader, %for.end
+  %0 = phi double [ 0.000000e+00, %for.end39 ], [ %div97, %if.then88 ], [ 0.000000e+00, %if.else ], [ 0.000000e+00, %for.cond14.preheader ], [ 0.000000e+00, %for.end ]
+  %1 = phi double [ undef, %for.end39 ], [ %div92, %if.then88 ], [ undef, %if.else ], [ 0.000000e+00, %for.cond14.preheader ], [ 0.000000e+00, %for.end ]
+  ret void
+}
+
+
+define void @intrapred_luma() {
+entry:
+  %conv153 = trunc i32 undef to i16
+  %arrayidx154 = getelementptr inbounds [13 x i16]* undef, i64 0, i64 12
+  store i16 %conv153, i16* %arrayidx154, align 8
+  %arrayidx155 = getelementptr inbounds [13 x i16]* undef, i64 0, i64 11
+  store i16 %conv153, i16* %arrayidx155, align 2
+  %arrayidx156 = getelementptr inbounds [13 x i16]* undef, i64 0, i64 10
+  store i16 %conv153, i16* %arrayidx156, align 4
+  ret void
+}
+
+define fastcc void @dct36(double* %inbuf) {
+entry:
+  %arrayidx41 = getelementptr inbounds double* %inbuf, i64 2
+  %arrayidx44 = getelementptr inbounds double* %inbuf, i64 1
+  %0 = load double* %arrayidx44, align 8
+  %add46 = fadd double %0, undef
+  store double %add46, double* %arrayidx41, align 8
+  %1 = load double* %inbuf, align 8
+  %add49 = fadd double %1, %0
+  store double %add49, double* %arrayidx44, align 8
+  ret void
+}
diff --git a/test/Transforms/SLPVectorizer/X86/crash_mandeltext.ll b/test/Transforms/SLPVectorizer/X86/crash_mandeltext.ll
new file mode 100644
index 0000000..d6915e2
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/crash_mandeltext.ll
@@ -0,0 +1,107 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+define void @main() {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %for.end44, %entry
+  br label %for.cond4.preheader
+
+for.cond4.preheader:                              ; preds = %if.then25, %for.body
+  br label %for.body6
+
+for.body6:                                        ; preds = %for.inc21, %for.cond4.preheader
+  br label %for.body12
+
+for.body12:                                       ; preds = %if.end, %for.body6
+  %fZImg.069 = phi double [ undef, %for.body6 ], [ %add19, %if.end ]
+  %fZReal.068 = phi double [ undef, %for.body6 ], [ %add20, %if.end ]
+  %mul13 = fmul double %fZReal.068, %fZReal.068
+  %mul14 = fmul double %fZImg.069, %fZImg.069
+  %add15 = fadd double %mul13, %mul14
+  %cmp16 = fcmp ogt double %add15, 4.000000e+00
+  br i1 %cmp16, label %for.inc21, label %if.end
+
+if.end:                                           ; preds = %for.body12
+  %mul18 = fmul double undef, %fZImg.069
+  %add19 = fadd double undef, %mul18
+  %sub = fsub double %mul13, %mul14
+  %add20 = fadd double undef, %sub
+  br i1 undef, label %for.body12, label %for.inc21
+
+for.inc21:                                        ; preds = %if.end, %for.body12
+  br i1 undef, label %for.end23, label %for.body6
+
+for.end23:                                        ; preds = %for.inc21
+  br i1 undef, label %if.then25, label %if.then26
+
+if.then25:                                        ; preds = %for.end23
+  br i1 undef, label %for.end44, label %for.cond4.preheader
+
+if.then26:                                        ; preds = %for.end23
+  unreachable
+
+for.end44:                                        ; preds = %if.then25
+  br i1 undef, label %for.end48, label %for.body
+
+for.end48:                                        ; preds = %for.end44
+  ret void
+}
+
+%struct.hoge = type { double, double, double}
+
+define void @zot(%struct.hoge* %arg) {
+bb:
+  %tmp = load double* undef, align 8
+  %tmp1 = fsub double %tmp, undef
+  %tmp2 = load double* undef, align 8
+  %tmp3 = fsub double %tmp2, undef
+  %tmp4 = fmul double %tmp3, undef
+  %tmp5 = fmul double %tmp3, undef
+  %tmp6 = fsub double %tmp5, undef
+  %tmp7 = getelementptr inbounds %struct.hoge* %arg, i64 0, i32 1
+  store double %tmp6, double* %tmp7, align 8
+  %tmp8 = fmul double %tmp1, undef
+  %tmp9 = fsub double %tmp8, undef
+  %tmp10 = getelementptr inbounds %struct.hoge* %arg, i64 0, i32 2
+  store double %tmp9, double* %tmp10, align 8
+  br i1 undef, label %bb11, label %bb12
+
+bb11:                                             ; preds = %bb
+  br label %bb14
+
+bb12:                                             ; preds = %bb
+  %tmp13 = fmul double undef, %tmp2
+  br label %bb14
+
+bb14:                                             ; preds = %bb12, %bb11
+  ret void
+}
+
+
+%struct.rc4_state.0.24 = type { i32, i32, [256 x i32] }
+
+define void @rc4_crypt(%struct.rc4_state.0.24* nocapture %s) {
+entry:
+  %x1 = getelementptr inbounds %struct.rc4_state.0.24* %s, i64 0, i32 0
+  %y2 = getelementptr inbounds %struct.rc4_state.0.24* %s, i64 0, i32 1
+  br i1 undef, label %for.body, label %for.end
+
+for.body:                                         ; preds = %for.body, %entry
+  %x.045 = phi i32 [ %conv4, %for.body ], [ undef, %entry ]
+  %conv4 = and i32 undef, 255
+  %conv7 = and i32 undef, 255
+  %idxprom842 = zext i32 %conv7 to i64
+  br i1 undef, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  %x.0.lcssa = phi i32 [ undef, %entry ], [ %conv4, %for.body ]
+  %y.0.lcssa = phi i32 [ undef, %entry ], [ %conv7, %for.body ]
+  store i32 %x.0.lcssa, i32* %x1, align 4
+  store i32 %y.0.lcssa, i32* %y2, align 4
+  ret void
+}
+
diff --git a/test/Transforms/SLPVectorizer/X86/crash_povray.ll b/test/Transforms/SLPVectorizer/X86/crash_povray.ll
deleted file mode 100644
index 7ef8df4..0000000
--- a/test/Transforms/SLPVectorizer/X86/crash_povray.ll
+++ /dev/null
@@ -1,34 +0,0 @@
-; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
-target triple = "x86_64-apple-macosx10.8.0"
-
-%struct.hoge = type { double, double, double}
-
-define void @zot(%struct.hoge* %arg) {
-bb:
-  %tmp = load double* undef, align 8
-  %tmp1 = fsub double %tmp, undef
-  %tmp2 = load double* undef, align 8
-  %tmp3 = fsub double %tmp2, undef
-  %tmp4 = fmul double %tmp3, undef
-  %tmp5 = fmul double %tmp3, undef
-  %tmp6 = fsub double %tmp5, undef
-  %tmp7 = getelementptr inbounds %struct.hoge* %arg, i64 0, i32 1
-  store double %tmp6, double* %tmp7, align 8
-  %tmp8 = fmul double %tmp1, undef
-  %tmp9 = fsub double %tmp8, undef
-  %tmp10 = getelementptr inbounds %struct.hoge* %arg, i64 0, i32 2
-  store double %tmp9, double* %tmp10, align 8
-  br i1 undef, label %bb11, label %bb12
-
-bb11:                                             ; preds = %bb
-  br label %bb14
-
-bb12:                                             ; preds = %bb
-  %tmp13 = fmul double undef, %tmp2
-  br label %bb14
-
-bb14:                                             ; preds = %bb12, %bb11
-  ret void
-}
diff --git a/test/Transforms/SLPVectorizer/X86/crash_sim4b1.ll b/test/Transforms/SLPVectorizer/X86/crash_sim4b1.ll
new file mode 100644
index 0000000..0541545
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/crash_sim4b1.ll
@@ -0,0 +1,113 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+%struct._exon_t.12.103.220.363.480.649.740.857.1039.1065.1078.1091.1117.1130.1156.1169.1195.1221.1234.1286.1299.1312.1338.1429.1455.1468.1494.1520.1884.1897.1975.2066.2105.2170.2171 = type { i32, i32, i32, i32, i32, i32, [8 x i8] }
+
+define void @SIM4() {
+entry:
+  br i1 undef, label %return, label %lor.lhs.false
+
+lor.lhs.false:                                    ; preds = %entry
+  br i1 undef, label %return, label %if.end
+
+if.end:                                           ; preds = %lor.lhs.false
+  br i1 undef, label %for.end605, label %for.body.lr.ph
+
+for.body.lr.ph:                                   ; preds = %if.end
+  br label %for.body
+
+for.body:                                         ; preds = %for.inc603, %for.body.lr.ph
+  br i1 undef, label %for.inc603, label %if.end12
+
+if.end12:                                         ; preds = %for.body
+  br i1 undef, label %land.lhs.true, label %land.lhs.true167
+
+land.lhs.true:                                    ; preds = %if.end12
+  br i1 undef, label %if.then17, label %land.lhs.true167
+
+if.then17:                                        ; preds = %land.lhs.true
+  br i1 undef, label %if.end98, label %land.rhs.lr.ph
+
+land.rhs.lr.ph:                                   ; preds = %if.then17
+  unreachable
+
+if.end98:                                         ; preds = %if.then17
+  %from299 = getelementptr inbounds %struct._exon_t.12.103.220.363.480.649.740.857.1039.1065.1078.1091.1117.1130.1156.1169.1195.1221.1234.1286.1299.1312.1338.1429.1455.1468.1494.1520.1884.1897.1975.2066.2105.2170.2171* undef, i64 0, i32 1
+  br i1 undef, label %land.lhs.true167, label %if.then103
+
+if.then103:                                       ; preds = %if.end98
+  %.sub100 = select i1 undef, i32 250, i32 undef
+  %mul114 = shl nsw i32 %.sub100, 2
+  %from1115 = getelementptr inbounds %struct._exon_t.12.103.220.363.480.649.740.857.1039.1065.1078.1091.1117.1130.1156.1169.1195.1221.1234.1286.1299.1312.1338.1429.1455.1468.1494.1520.1884.1897.1975.2066.2105.2170.2171* undef, i64 0, i32 0
+  %cond125 = select i1 undef, i32 undef, i32 %mul114
+  br label %for.cond.i
+
+for.cond.i:                                       ; preds = %land.rhs.i874, %if.then103
+  %row.0.i = phi i32 [ undef, %land.rhs.i874 ], [ %.sub100, %if.then103 ]
+  %col.0.i = phi i32 [ undef, %land.rhs.i874 ], [ %cond125, %if.then103 ]
+  br i1 undef, label %land.rhs.i874, label %for.end.i
+
+land.rhs.i874:                                    ; preds = %for.cond.i
+  br i1 undef, label %for.cond.i, label %for.end.i
+
+for.end.i:                                        ; preds = %land.rhs.i874, %for.cond.i
+  br i1 undef, label %if.then.i, label %if.end.i
+
+if.then.i:                                        ; preds = %for.end.i
+  %add14.i = add nsw i32 %row.0.i, undef
+  %add15.i = add nsw i32 %col.0.i, undef
+  br label %extend_bw.exit
+
+if.end.i:                                         ; preds = %for.end.i
+  %add16.i = add i32 %cond125, %.sub100
+  %cmp26514.i = icmp slt i32 %add16.i, 0
+  br i1 %cmp26514.i, label %for.end33.i, label %for.body28.lr.ph.i
+
+for.body28.lr.ph.i:                               ; preds = %if.end.i
+  br label %for.end33.i
+
+for.end33.i:                                      ; preds = %for.body28.lr.ph.i, %if.end.i
+  br i1 undef, label %for.end58.i, label %for.body52.lr.ph.i
+
+for.body52.lr.ph.i:                               ; preds = %for.end33.i
+  br label %for.end58.i
+
+for.end58.i:                                      ; preds = %for.body52.lr.ph.i, %for.end33.i
+  br label %while.cond260.i
+
+while.cond260.i:                                  ; preds = %land.rhs263.i, %for.end58.i
+  br i1 undef, label %land.rhs263.i, label %while.end275.i
+
+land.rhs263.i:                                    ; preds = %while.cond260.i
+  br i1 undef, label %while.cond260.i, label %while.end275.i
+
+while.end275.i:                                   ; preds = %land.rhs263.i, %while.cond260.i
+  br label %extend_bw.exit
+
+extend_bw.exit:                                   ; preds = %while.end275.i, %if.then.i
+  %add14.i1262 = phi i32 [ %add14.i, %if.then.i ], [ undef, %while.end275.i ]
+  %add15.i1261 = phi i32 [ %add15.i, %if.then.i ], [ undef, %while.end275.i ]
+  br i1 false, label %if.then157, label %land.lhs.true167
+
+if.then157:                                       ; preds = %extend_bw.exit
+  %add158 = add nsw i32 %add14.i1262, 1
+  store i32 %add158, i32* %from299, align 4
+  %add160 = add nsw i32 %add15.i1261, 1
+  store i32 %add160, i32* %from1115, align 4
+  br label %land.lhs.true167
+
+land.lhs.true167:                                 ; preds = %if.then157, %extend_bw.exit, %if.end98, %land.lhs.true, %if.end12
+  unreachable
+
+for.inc603:                                       ; preds = %for.body
+  br i1 undef, label %for.body, label %for.end605
+
+for.end605:                                       ; preds = %for.inc603, %if.end
+  unreachable
+
+return:                                           ; preds = %lor.lhs.false, %entry
+  ret void
+}
+
diff --git a/test/Transforms/SLPVectorizer/X86/crash_smallpt.ll b/test/Transforms/SLPVectorizer/X86/crash_smallpt.ll
new file mode 100644
index 0000000..915c41b
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/crash_smallpt.ll
@@ -0,0 +1,105 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+%struct.Ray.5.11.53.113.119.137.149.185.329.389.416 = type { %struct.Vec.0.6.48.108.114.132.144.180.324.384.414, %struct.Vec.0.6.48.108.114.132.144.180.324.384.414 }
+%struct.Vec.0.6.48.108.114.132.144.180.324.384.414 = type { double, double, double }
+
+; Function Attrs: ssp uwtable
+define void @main() #0 {
+entry:
+  br i1 undef, label %cond.true, label %cond.end
+
+cond.true:                                        ; preds = %entry
+  unreachable
+
+cond.end:                                         ; preds = %entry
+  br label %invoke.cont
+
+invoke.cont:                                      ; preds = %invoke.cont, %cond.end
+  br i1 undef, label %arrayctor.cont, label %invoke.cont
+
+arrayctor.cont:                                   ; preds = %invoke.cont
+  %agg.tmp99208.sroa.0.0.idx = getelementptr inbounds %struct.Ray.5.11.53.113.119.137.149.185.329.389.416* undef, i64 0, i32 0, i32 0
+  %agg.tmp99208.sroa.1.8.idx388 = getelementptr inbounds %struct.Ray.5.11.53.113.119.137.149.185.329.389.416* undef, i64 0, i32 0, i32 1
+  %agg.tmp101211.sroa.0.0.idx = getelementptr inbounds %struct.Ray.5.11.53.113.119.137.149.185.329.389.416* undef, i64 0, i32 1, i32 0
+  %agg.tmp101211.sroa.1.8.idx390 = getelementptr inbounds %struct.Ray.5.11.53.113.119.137.149.185.329.389.416* undef, i64 0, i32 1, i32 1
+  br label %for.cond36.preheader
+
+for.cond36.preheader:                             ; preds = %_Z5clampd.exit.1, %arrayctor.cont
+  br i1 undef, label %for.body42.lr.ph.us, label %_Z5clampd.exit.1
+
+cond.false51.us:                                  ; preds = %for.body42.lr.ph.us
+  unreachable
+
+cond.true48.us:                                   ; preds = %for.body42.lr.ph.us
+  br i1 undef, label %cond.true63.us, label %cond.false66.us
+
+cond.false66.us:                                  ; preds = %cond.true48.us
+  %add.i276.us = fadd double 0.000000e+00, undef
+  %add.i264.us = fadd double %add.i276.us, 0.000000e+00
+  %add4.i267.us = fadd double undef, 0xBFA5CC2D1960285F
+  %mul.i254.us = fmul double %add.i264.us, 1.400000e+02
+  %mul2.i256.us = fmul double %add4.i267.us, 1.400000e+02
+  %add.i243.us = fadd double %mul.i254.us, 5.000000e+01
+  %add4.i246.us = fadd double %mul2.i256.us, 5.200000e+01
+  %mul.i.i.us = fmul double undef, %add.i264.us
+  %mul2.i.i.us = fmul double undef, %add4.i267.us
+  store double %add.i243.us, double* %agg.tmp99208.sroa.0.0.idx, align 8
+  store double %add4.i246.us, double* %agg.tmp99208.sroa.1.8.idx388, align 8
+  store double %mul.i.i.us, double* %agg.tmp101211.sroa.0.0.idx, align 8
+  store double %mul2.i.i.us, double* %agg.tmp101211.sroa.1.8.idx390, align 8
+  unreachable
+
+cond.true63.us:                                   ; preds = %cond.true48.us
+  unreachable
+
+for.body42.lr.ph.us:                              ; preds = %for.cond36.preheader
+  br i1 undef, label %cond.true48.us, label %cond.false51.us
+
+_Z5clampd.exit.1:                                 ; preds = %for.cond36.preheader
+  br label %for.cond36.preheader
+}
+
+
+%struct.Ray.5.11.53.95.137.191.197.203.239.257.263.269.275.281.287.293.383.437.443.455.461.599.601 = type { %struct.Vec.0.6.48.90.132.186.192.198.234.252.258.264.270.276.282.288.378.432.438.450.456.594.600, %struct.Vec.0.6.48.90.132.186.192.198.234.252.258.264.270.276.282.288.378.432.438.450.456.594.600 }
+%struct.Vec.0.6.48.90.132.186.192.198.234.252.258.264.270.276.282.288.378.432.438.450.456.594.600 = type { double, double, double }
+
+define void @_Z8radianceRK3RayiPt() #0 {
+entry:
+  br i1 undef, label %if.then78, label %if.then38
+
+if.then38:                                        ; preds = %entry
+  %mul.i.i790 = fmul double undef, undef
+  %mul3.i.i792 = fmul double undef, undef
+  %mul.i764 = fmul double undef, %mul3.i.i792
+  %mul4.i767 = fmul double undef, undef
+  %sub.i768 = fsub double %mul.i764, %mul4.i767
+  %mul6.i770 = fmul double undef, %mul.i.i790
+  %mul9.i772 = fmul double undef, %mul3.i.i792
+  %sub10.i773 = fsub double %mul6.i770, %mul9.i772
+  %mul.i736 = fmul double undef, %sub.i768
+  %mul2.i738 = fmul double undef, %sub10.i773
+  %mul.i727 = fmul double undef, %mul.i736
+  %mul2.i729 = fmul double undef, %mul2.i738
+  %add.i716 = fadd double undef, %mul.i727
+  %add4.i719 = fadd double undef, %mul2.i729
+  %add.i695 = fadd double undef, %add.i716
+  %add4.i698 = fadd double undef, %add4.i719
+  %mul.i.i679 = fmul double undef, %add.i695
+  %mul2.i.i680 = fmul double undef, %add4.i698
+  %agg.tmp74663.sroa.0.0.idx = getelementptr inbounds %struct.Ray.5.11.53.95.137.191.197.203.239.257.263.269.275.281.287.293.383.437.443.455.461.599.601* undef, i64 0, i32 1, i32 0
+  store double %mul.i.i679, double* %agg.tmp74663.sroa.0.0.idx, align 8
+  %agg.tmp74663.sroa.1.8.idx943 = getelementptr inbounds %struct.Ray.5.11.53.95.137.191.197.203.239.257.263.269.275.281.287.293.383.437.443.455.461.599.601* undef, i64 0, i32 1, i32 1
+  store double %mul2.i.i680, double* %agg.tmp74663.sroa.1.8.idx943, align 8
+  br label %return
+
+if.then78:                                        ; preds = %entry
+  br label %return
+
+return:                                           ; preds = %if.then78, %if.then38
+  ret void
+}
+
+attributes #0 = { ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/Transforms/SLPVectorizer/X86/cross_block_slp.ll b/test/Transforms/SLPVectorizer/X86/cross_block_slp.ll
new file mode 100644
index 0000000..06c4b52
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/cross_block_slp.ll
@@ -0,0 +1,54 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+; int foo(double *A, float *B, int g) {
+;   float B0 = B[0];
+;   float B1 = B[1]; <----- BasicBlock #1
+;   B0 += 5;
+;   B1 += 8;
+;
+;   if (g) bar();
+;
+;   A[0] += B0;     <------- BasicBlock #3
+;   A[1] += B1;
+; }
+
+
+;CHECK-LABEL: @foo(
+;CHECK: load <2 x float>
+;CHECK: fadd <2 x float>
+;CHECK: call i32
+;CHECK: load <2 x double>
+;CHECK: fadd <2 x double>
+;CHECK: store <2 x double>
+;CHECK: ret
+define i32 @foo(double* nocapture %A, float* nocapture %B, i32 %g) {
+entry:
+  %0 = load float* %B, align 4
+  %arrayidx1 = getelementptr inbounds float* %B, i64 1
+  %1 = load float* %arrayidx1, align 4
+  %add = fadd float %0, 5.000000e+00
+  %add2 = fadd float %1, 8.000000e+00
+  %tobool = icmp eq i32 %g, 0
+  br i1 %tobool, label %if.end, label %if.then
+
+if.then:
+  %call = tail call i32 (...)* @bar()
+  br label %if.end
+
+if.end:
+  %conv = fpext float %add to double
+  %2 = load double* %A, align 8
+  %add4 = fadd double %conv, %2
+  store double %add4, double* %A, align 8
+  %conv5 = fpext float %add2 to double
+  %arrayidx6 = getelementptr inbounds double* %A, i64 1
+  %3 = load double* %arrayidx6, align 8
+  %add7 = fadd double %conv5, %3
+  store double %add7, double* %arrayidx6, align 8
+  ret i32 undef
+}
+
+declare i32 @bar(...)
diff --git a/test/Transforms/SLPVectorizer/X86/cse.ll b/test/Transforms/SLPVectorizer/X86/cse.ll
new file mode 100644
index 0000000..bbfd6f2
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/cse.ll
@@ -0,0 +1,219 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -S -mtriple=i386-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128"
+target triple = "i386-apple-macosx10.8.0"
+
+;int test(double *G) {
+;  G[0] = 1+G[5]*4;
+;  G[1] = 6+G[6]*3;
+;  G[2] = 7+G[5]*4;
+;  G[3] = 8+G[6]*4;
+;}
+
+;CHECK-LABEL: @test(
+;CHECK: load <2 x double>
+;CHECK: fadd <2 x double>
+;CHECK: store <2 x double>
+;CHECK: insertelement <2 x double>
+;CHECK: fadd <2 x double>
+;CHECK: store <2 x double>
+;CHECK: ret i32
+
+define i32 @test(double* nocapture %G) {
+entry:
+  %arrayidx = getelementptr inbounds double* %G, i64 5
+  %0 = load double* %arrayidx, align 8
+  %mul = fmul double %0, 4.000000e+00
+  %add = fadd double %mul, 1.000000e+00
+  store double %add, double* %G, align 8
+  %arrayidx2 = getelementptr inbounds double* %G, i64 6
+  %1 = load double* %arrayidx2, align 8
+  %mul3 = fmul double %1, 3.000000e+00
+  %add4 = fadd double %mul3, 6.000000e+00
+  %arrayidx5 = getelementptr inbounds double* %G, i64 1
+  store double %add4, double* %arrayidx5, align 8
+  %add8 = fadd double %mul, 7.000000e+00
+  %arrayidx9 = getelementptr inbounds double* %G, i64 2
+  store double %add8, double* %arrayidx9, align 8
+  %mul11 = fmul double %1, 4.000000e+00
+  %add12 = fadd double %mul11, 8.000000e+00
+  %arrayidx13 = getelementptr inbounds double* %G, i64 3
+  store double %add12, double* %arrayidx13, align 8
+  ret i32 undef
+}
+
+;int foo(double *A, int n) {
+;  A[0] = A[0] * 7.9 * n + 6.0;
+;  A[1] = A[1] * 7.7 * n + 2.0;
+;  A[2] = A[2] * 7.6 * n + 3.0;
+;  A[3] = A[3] * 7.4 * n + 4.0;
+;}
+;CHECK-LABEL: @foo(
+;CHECK: insertelement <2 x double>
+;CHECK: insertelement <2 x double>
+;CHECK-NOT: insertelement <2 x double>
+;CHECK: ret
+define i32 @foo(double* nocapture %A, i32 %n) {
+entry:
+  %0 = load double* %A, align 8
+  %mul = fmul double %0, 7.900000e+00
+  %conv = sitofp i32 %n to double
+  %mul1 = fmul double %conv, %mul
+  %add = fadd double %mul1, 6.000000e+00
+  store double %add, double* %A, align 8
+  %arrayidx3 = getelementptr inbounds double* %A, i64 1
+  %1 = load double* %arrayidx3, align 8
+  %mul4 = fmul double %1, 7.700000e+00
+  %mul6 = fmul double %conv, %mul4
+  %add7 = fadd double %mul6, 2.000000e+00
+  store double %add7, double* %arrayidx3, align 8
+  %arrayidx9 = getelementptr inbounds double* %A, i64 2
+  %2 = load double* %arrayidx9, align 8
+  %mul10 = fmul double %2, 7.600000e+00
+  %mul12 = fmul double %conv, %mul10
+  %add13 = fadd double %mul12, 3.000000e+00
+  store double %add13, double* %arrayidx9, align 8
+  %arrayidx15 = getelementptr inbounds double* %A, i64 3
+  %3 = load double* %arrayidx15, align 8
+  %mul16 = fmul double %3, 7.400000e+00
+  %mul18 = fmul double %conv, %mul16
+  %add19 = fadd double %mul18, 4.000000e+00
+  store double %add19, double* %arrayidx15, align 8
+  ret i32 undef
+}
+
+; int test2(double *G, int k) {
+;   if (k) {
+;     G[0] = 1+G[5]*4;
+;     G[1] = 6+G[6]*3;
+;   } else {
+;     G[2] = 7+G[5]*4;
+;     G[3] = 8+G[6]*3;
+;   }
+; }
+
+; We can't merge the gather sequences because one does not dominate the other.
+; CHECK: test2
+; CHECK: insertelement
+; CHECK: insertelement
+; CHECK: insertelement
+; CHECK: insertelement
+; CHECK: ret
+define i32 @test2(double* nocapture %G, i32 %k) {
+  %1 = icmp eq i32 %k, 0
+  %2 = getelementptr inbounds double* %G, i64 5
+  %3 = load double* %2, align 8
+  %4 = fmul double %3, 4.000000e+00
+  br i1 %1, label %12, label %5
+
+; <label>:5                                       ; preds = %0
+  %6 = fadd double %4, 1.000000e+00
+  store double %6, double* %G, align 8
+  %7 = getelementptr inbounds double* %G, i64 6
+  %8 = load double* %7, align 8
+  %9 = fmul double %8, 3.000000e+00
+  %10 = fadd double %9, 6.000000e+00
+  %11 = getelementptr inbounds double* %G, i64 1
+  store double %10, double* %11, align 8
+  br label %20
+
+; <label>:12                                      ; preds = %0
+  %13 = fadd double %4, 7.000000e+00
+  %14 = getelementptr inbounds double* %G, i64 2
+  store double %13, double* %14, align 8
+  %15 = getelementptr inbounds double* %G, i64 6
+  %16 = load double* %15, align 8
+  %17 = fmul double %16, 3.000000e+00
+  %18 = fadd double %17, 8.000000e+00
+  %19 = getelementptr inbounds double* %G, i64 3
+  store double %18, double* %19, align 8
+  br label %20
+
+; <label>:20                                      ; preds = %12, %5
+  ret i32 undef
+}
+
+
+;int foo(double *A, int n) {
+;  A[0] = A[0] * 7.9 * n + 6.0;
+;  A[1] = A[1] * 7.9 * n + 6.0;
+;  A[2] = A[2] * 7.9 * n + 6.0;
+;  A[3] = A[3] * 7.9 * n + 6.0;
+;}
+;CHECK-LABEL: @foo4(
+;CHECK: insertelement <2 x double>
+;CHECK: insertelement <2 x double>
+;CHECK-NOT: insertelement <2 x double>
+;CHECK: ret
+define i32 @foo4(double* nocapture %A, i32 %n) {
+entry:
+  %0 = load double* %A, align 8
+  %mul = fmul double %0, 7.900000e+00
+  %conv = sitofp i32 %n to double
+  %mul1 = fmul double %conv, %mul
+  %add = fadd double %mul1, 6.000000e+00
+  store double %add, double* %A, align 8
+  %arrayidx3 = getelementptr inbounds double* %A, i64 1
+  %1 = load double* %arrayidx3, align 8
+  %mul4 = fmul double %1, 7.900000e+00
+  %mul6 = fmul double %conv, %mul4
+  %add7 = fadd double %mul6, 6.000000e+00
+  store double %add7, double* %arrayidx3, align 8
+  %arrayidx9 = getelementptr inbounds double* %A, i64 2
+  %2 = load double* %arrayidx9, align 8
+  %mul10 = fmul double %2, 7.900000e+00
+  %mul12 = fmul double %conv, %mul10
+  %add13 = fadd double %mul12, 6.000000e+00
+  store double %add13, double* %arrayidx9, align 8
+  %arrayidx15 = getelementptr inbounds double* %A, i64 3
+  %3 = load double* %arrayidx15, align 8
+  %mul16 = fmul double %3, 7.900000e+00
+  %mul18 = fmul double %conv, %mul16
+  %add19 = fadd double %mul18, 6.000000e+00
+  store double %add19, double* %arrayidx15, align 8
+  ret i32 undef
+}
+
+;int partial_mrg(double *A, int n) {
+;  A[0] = A[0] * n;
+;  A[1] = A[1] * n;
+;  if (n < 4) return 0;
+;  A[2] = A[2] * n;
+;  A[3] = A[3] * (n+4);
+;}
+;CHECK-LABEL: @partial_mrg(
+;CHECK: insertelement <2 x double>
+;CHECK: insertelement <2 x double>
+;CHECK: insertelement <2 x double>
+;CHECK-NOT: insertelement <2 x double>
+;CHECK: ret
+define i32 @partial_mrg(double* nocapture %A, i32 %n) {
+entry:
+  %0 = load double* %A, align 8
+  %conv = sitofp i32 %n to double
+  %mul = fmul double %conv, %0
+  store double %mul, double* %A, align 8
+  %arrayidx2 = getelementptr inbounds double* %A, i64 1
+  %1 = load double* %arrayidx2, align 8
+  %mul4 = fmul double %conv, %1
+  store double %mul4, double* %arrayidx2, align 8
+  %cmp = icmp slt i32 %n, 4
+  br i1 %cmp, label %return, label %if.end
+
+if.end:                                           ; preds = %entry
+  %arrayidx7 = getelementptr inbounds double* %A, i64 2
+  %2 = load double* %arrayidx7, align 8
+  %mul9 = fmul double %conv, %2
+  store double %mul9, double* %arrayidx7, align 8
+  %arrayidx11 = getelementptr inbounds double* %A, i64 3
+  %3 = load double* %arrayidx11, align 8
+  %add = add nsw i32 %n, 4
+  %conv12 = sitofp i32 %add to double
+  %mul13 = fmul double %conv12, %3
+  store double %mul13, double* %arrayidx11, align 8
+  br label %return
+
+return:                                           ; preds = %entry, %if.end
+  ret i32 0
+}
+
diff --git a/test/Transforms/SLPVectorizer/X86/cycle_dup.ll b/test/Transforms/SLPVectorizer/X86/cycle_dup.ll
new file mode 100644
index 0000000..fba3549
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/cycle_dup.ll
@@ -0,0 +1,64 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.9.0"
+
+; int foo(int *A) {
+;   int r = A[0], g = A[1], b = A[2], a = A[3];
+;   for (int i=0; i < A[13]; i++) {
+;     r*=18; g*=19; b*=12; a *=9;
+;   }
+;   A[0] = r; A[1] = g; A[2] = b; A[3] = a;
+; }
+
+;CHECK-LABEL: @foo
+;CHECK: bitcast i32* %A to <4 x i32>*
+;CHECK-NEXT: load <4 x i32>
+;CHECK: phi <4 x i32>
+;CHECK-NEXT: mul <4 x i32>
+;CHECK-NOT: mul
+;CHECK: phi <4 x i32>
+;CHECK: bitcast i32* %A to <4 x i32>*
+;CHECK-NEXT: store <4 x i32>
+;CHECK-NEXT:ret i32 undef
+define i32 @foo(i32* nocapture %A) #0 {
+entry:
+  %0 = load i32* %A, align 4
+  %arrayidx1 = getelementptr inbounds i32* %A, i64 1
+  %1 = load i32* %arrayidx1, align 4
+  %arrayidx2 = getelementptr inbounds i32* %A, i64 2
+  %2 = load i32* %arrayidx2, align 4
+  %arrayidx3 = getelementptr inbounds i32* %A, i64 3
+  %3 = load i32* %arrayidx3, align 4
+  %arrayidx4 = getelementptr inbounds i32* %A, i64 13
+  %4 = load i32* %arrayidx4, align 4
+  %cmp24 = icmp sgt i32 %4, 0
+  br i1 %cmp24, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %i.029 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
+  %a.028 = phi i32 [ %mul7, %for.body ], [ %3, %entry ]
+  %b.027 = phi i32 [ %mul6, %for.body ], [ %2, %entry ]
+  %g.026 = phi i32 [ %mul5, %for.body ], [ %1, %entry ]
+  %r.025 = phi i32 [ %mul, %for.body ], [ %0, %entry ]
+  %mul = mul nsw i32 %r.025, 18
+  %mul5 = mul nsw i32 %g.026, 19
+  %mul6 = mul nsw i32 %b.027, 12
+  %mul7 = mul nsw i32 %a.028, 9
+  %inc = add nsw i32 %i.029, 1
+  %cmp = icmp slt i32 %inc, %4
+  br i1 %cmp, label %for.body, label %for.end
+
+for.end:                                          ; preds = %for.body, %entry
+  %a.0.lcssa = phi i32 [ %3, %entry ], [ %mul7, %for.body ]
+  %b.0.lcssa = phi i32 [ %2, %entry ], [ %mul6, %for.body ]
+  %g.0.lcssa = phi i32 [ %1, %entry ], [ %mul5, %for.body ]
+  %r.0.lcssa = phi i32 [ %0, %entry ], [ %mul, %for.body ]
+  store i32 %r.0.lcssa, i32* %A, align 4
+  store i32 %g.0.lcssa, i32* %arrayidx1, align 4
+  store i32 %b.0.lcssa, i32* %arrayidx2, align 4
+  store i32 %a.0.lcssa, i32* %arrayidx3, align 4
+  ret i32 undef
+}
+
+
diff --git a/test/Transforms/SLPVectorizer/X86/debug_info.ll b/test/Transforms/SLPVectorizer/X86/debug_info.ll
new file mode 100644
index 0000000..b408913
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/debug_info.ll
@@ -0,0 +1,91 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.7.0"
+
+; int depth(double *A, int m) {
+;   double y0 = 0; double y1 = 1;
+;   for (int i=0; i < m; i++) {
+;     y0 = A[4];
+;     y1 = A[5];
+;   }
+;   A[8] = y0; A[8+1] = y1;
+; }
+
+;CHECK: @depth
+;CHECK: getelementptr inbounds {{.*}}, !dbg !24
+;CHECK: bitcast double* {{.*}}, !dbg !24
+;CHECK: load <2 x double>* {{.*}}, !dbg !24
+;CHECK: store <2 x double> {{.*}}, !dbg !26
+;CHECK: ret
+;CHECK: !24 = metadata !{i32 4, i32 0,
+;CHECK: !26 = metadata !{i32 7, i32 0,
+
+define i32 @depth(double* nocapture %A, i32 %m) #0 {
+entry:
+  tail call void @llvm.dbg.value(metadata !{double* %A}, i64 0, metadata !12), !dbg !19
+  tail call void @llvm.dbg.value(metadata !{i32 %m}, i64 0, metadata !13), !dbg !19
+  tail call void @llvm.dbg.value(metadata !20, i64 0, metadata !14), !dbg !21
+  tail call void @llvm.dbg.value(metadata !22, i64 0, metadata !15), !dbg !21
+  tail call void @llvm.dbg.value(metadata !2, i64 0, metadata !16), !dbg !23
+  %cmp8 = icmp sgt i32 %m, 0, !dbg !23
+  br i1 %cmp8, label %for.body.lr.ph, label %for.end, !dbg !23
+
+for.body.lr.ph:                                   ; preds = %entry
+  %arrayidx = getelementptr inbounds double* %A, i64 4, !dbg !24
+  %0 = load double* %arrayidx, align 8, !dbg !24, !tbaa !26
+  %arrayidx1 = getelementptr inbounds double* %A, i64 5, !dbg !29
+  %1 = load double* %arrayidx1, align 8, !dbg !29, !tbaa !26
+  br label %for.end, !dbg !23
+
+for.end:                                          ; preds = %for.body.lr.ph, %entry
+  %y1.0.lcssa = phi double [ %1, %for.body.lr.ph ], [ 1.000000e+00, %entry ]
+  %y0.0.lcssa = phi double [ %0, %for.body.lr.ph ], [ 0.000000e+00, %entry ]
+  %arrayidx2 = getelementptr inbounds double* %A, i64 8, !dbg !30
+  store double %y0.0.lcssa, double* %arrayidx2, align 8, !dbg !30, !tbaa !26
+  %arrayidx3 = getelementptr inbounds double* %A, i64 9, !dbg !30
+  store double %y1.0.lcssa, double* %arrayidx3, align 8, !dbg !30, !tbaa !26
+  ret i32 undef, !dbg !31
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.value(metadata, i64, metadata) #1
+
+attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!18}
+
+!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.4 (trunk 187335) (llvm/trunk 187335:187340M)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/Users/nadav/file.c] [DW_LANG_C99]
+!1 = metadata !{metadata !"file.c", metadata !"/Users/nadav"}
+!2 = metadata !{i32 0}
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"depth", metadata !"depth", metadata !"", i32 1, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (double*, i32)* @depth, null, null, metadata !11, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [depth]
+!5 = metadata !{i32 786473, metadata !1}          ; [ DW_TAG_file_type ] [/Users/nadav/file.c]
+!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
+!7 = metadata !{metadata !8, metadata !9, metadata !8}
+!8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
+!9 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from double]
+!10 = metadata !{i32 786468, null, null, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float]
+!11 = metadata !{metadata !12, metadata !13, metadata !14, metadata !15, metadata !16}
+!12 = metadata !{i32 786689, metadata !4, metadata !"A", metadata !5, i32 16777217, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [A] [line 1]
+!13 = metadata !{i32 786689, metadata !4, metadata !"m", metadata !5, i32 33554433, metadata !8, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [m] [line 1]
+!14 = metadata !{i32 786688, metadata !4, metadata !"y0", metadata !5, i32 2, metadata !10, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [y0] [line 2]
+!15 = metadata !{i32 786688, metadata !4, metadata !"y1", metadata !5, i32 2, metadata !10, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [y1] [line 2]
+!16 = metadata !{i32 786688, metadata !17, metadata !"i", metadata !5, i32 3, metadata !8, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [i] [line 3]
+!17 = metadata !{i32 786443, metadata !1, metadata !4, i32 3, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [/Users/nadav/file.c]
+!18 = metadata !{i32 2, metadata !"Dwarf Version", i32 2}
+!19 = metadata !{i32 1, i32 0, metadata !4, null}
+!20 = metadata !{double 0.000000e+00}
+!21 = metadata !{i32 2, i32 0, metadata !4, null}
+!22 = metadata !{double 1.000000e+00}
+!23 = metadata !{i32 3, i32 0, metadata !17, null}
+!24 = metadata !{i32 4, i32 0, metadata !25, null}
+!25 = metadata !{i32 786443, metadata !1, metadata !17, i32 3, i32 0, i32 1} ; [ DW_TAG_lexical_block ] [/Users/nadav/file.c]
+!26 = metadata !{metadata !"double", metadata !27}
+!27 = metadata !{metadata !"omnipotent char", metadata !28}
+!28 = metadata !{metadata !"Simple C/C++ TBAA"}
+!29 = metadata !{i32 5, i32 0, metadata !25, null}
+!30 = metadata !{i32 7, i32 0, metadata !4, null}
+!31 = metadata !{i32 8, i32 0, metadata !4, null} ; [ DW_TAG_imported_declaration ]
diff --git a/test/Transforms/SLPVectorizer/X86/diamond.ll b/test/Transforms/SLPVectorizer/X86/diamond.ll
index 8959b0d..5135a92 100644
--- a/test/Transforms/SLPVectorizer/X86/diamond.ll
+++ b/test/Transforms/SLPVectorizer/X86/diamond.ll
@@ -11,7 +11,7 @@ target triple = "x86_64-apple-macosx10.8.0"
 ;   return 0;
 ; }
 
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 ; CHECK: load <4 x i32>
 ; CHECK: mul <4 x i32>
 ; CHECK: store <4 x i32>
@@ -49,10 +49,11 @@ entry:
 ;   return A[0];
 ; }
 
-; CHECK: @extr_user
+; CHECK-LABEL: @extr_user(
+; CHECK: load <4 x i32>
 ; CHECK: store <4 x i32>
-; CHECK-NEXT: extractelement <4 x i32>
-; CHECK: ret
+; CHECK: extractelement <4 x i32>
+; CHECK-NEXT: ret
 define i32 @extr_user(i32* noalias nocapture %B, i32* noalias nocapture %A, i32 %n, i32 %m) {
 entry:
   %0 = load i32* %A, align 4
@@ -78,10 +79,11 @@ entry:
 }
 
 ; In this example we have an external user that is not the first element in the vector.
-; CHECK: @extr_user1
+; CHECK-LABEL: @extr_user1(
+; CHECK: load <4 x i32>
 ; CHECK: store <4 x i32>
-; CHECK-NEXT: extractelement <4 x i32>
-; CHECK: ret
+; CHECK: extractelement <4 x i32>
+; CHECK-NEXT: ret
 define i32 @extr_user1(i32* noalias nocapture %B, i32* noalias nocapture %A, i32 %n, i32 %m) {
 entry:
   %0 = load i32* %A, align 4
diff --git a/test/Transforms/SLPVectorizer/X86/external_user.ll b/test/Transforms/SLPVectorizer/X86/external_user.ll
new file mode 100644
index 0000000..22f0e64
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/external_user.ll
@@ -0,0 +1,61 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+; double foo(double * restrict b,  double * restrict a, int n, int m) {
+;   double r=a[1];
+;   double g=a[0];
+;   double x;
+;   for (int i=0; i < 100; i++) {
+;     r += 10;
+;     g += 10;
+;     r *= 4;
+;     g *= 4;
+;     x = g; <----- external user!
+;     r += 4;
+;     g += 4;
+;   }
+;   b[0] = g;
+;   b[1] = r;
+;
+;   return x; <-- must extract here!
+; }
+
+;CHECK: ext_user
+;CHECK: phi <2 x double>
+;CHECK: fadd <2 x double>
+;CHECK: fmul <2 x double>
+;CHECK: br
+;CHECK: store <2 x double>
+;CHECK: extractelement <2 x double>
+;CHECK: ret double
+
+define double @ext_user(double* noalias nocapture %B, double* noalias nocapture %A, i32 %n, i32 %m) {
+entry:
+  %arrayidx = getelementptr inbounds double* %A, i64 1
+  %0 = load double* %arrayidx, align 8
+  %1 = load double* %A, align 8
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.020 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %G.019 = phi double [ %1, %entry ], [ %add5, %for.body ]
+  %R.018 = phi double [ %0, %entry ], [ %add4, %for.body ]
+  %add = fadd double %R.018, 1.000000e+01
+  %add2 = fadd double %G.019, 1.000000e+01
+  %mul = fmul double %add, 4.000000e+00
+  %mul3 = fmul double %add2, 4.000000e+00
+  %add4 = fadd double %mul, 4.000000e+00
+  %add5 = fadd double %mul3, 4.000000e+00
+  %inc = add nsw i32 %i.020, 1
+  %exitcond = icmp eq i32 %inc, 100
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  store double %add5, double* %B, align 8
+  %arrayidx7 = getelementptr inbounds double* %B, i64 1
+  store double %add4, double* %arrayidx7, align 8
+  ret double %mul3
+}
+
diff --git a/test/Transforms/SLPVectorizer/X86/extract.ll b/test/Transforms/SLPVectorizer/X86/extract.ll
new file mode 100644
index 0000000..f611fd4
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/extract.ll
@@ -0,0 +1,59 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+;CHECK: fextr
+;CHECK-NOT: insertelement
+;CHECK-NOT: extractelement
+;CHECK: fadd <2 x double>
+;CHECK: ret void
+define void @fextr(double* %ptr) {
+entry:
+  %LD = load <2 x double>* undef
+  %V0 = extractelement <2 x double> %LD, i32 0
+  %V1 = extractelement <2 x double> %LD, i32 1
+  %P0 = getelementptr inbounds double* %ptr, i64 0
+  %P1 = getelementptr inbounds double* %ptr, i64 1
+  %A0 = fadd double %V0, 0.0
+  %A1 = fadd double %V1, 1.1
+  store double %A0, double* %P0, align 4
+  store double %A1, double* %P1, align 4
+  ret void
+}
+
+;CHECK: fextr1
+;CHECK: insertelement
+;CHECK: insertelement
+;CHECK: ret void
+define void @fextr1(double* %ptr) {
+entry:
+  %LD = load <2 x double>* undef
+  %V0 = extractelement <2 x double> %LD, i32 0
+  %V1 = extractelement <2 x double> %LD, i32 1
+  %P0 = getelementptr inbounds double* %ptr, i64 1  ; <--- incorrect order
+  %P1 = getelementptr inbounds double* %ptr, i64 0
+  %A0 = fadd double %V0, 1.2
+  %A1 = fadd double %V1, 3.4
+  store double %A0, double* %P0, align 4
+  store double %A1, double* %P1, align 4
+  ret void
+}
+
+;CHECK: fextr2
+;CHECK: insertelement
+;CHECK: insertelement
+;CHECK: ret void
+define void @fextr2(double* %ptr) {
+entry:
+  %LD = load <4 x double>* undef
+  %V0 = extractelement <4 x double> %LD, i32 0  ; <--- invalid size.
+  %V1 = extractelement <4 x double> %LD, i32 1
+  %P0 = getelementptr inbounds double* %ptr, i64 0
+  %P1 = getelementptr inbounds double* %ptr, i64 1
+  %A0 = fadd double %V0, 5.5
+  %A1 = fadd double %V1, 6.6
+  store double %A0, double* %P0, align 4
+  store double %A1, double* %P1, align 4
+  ret void
+}
+
diff --git a/test/Transforms/SLPVectorizer/X86/implicitfloat.ll b/test/Transforms/SLPVectorizer/X86/implicitfloat.ll
new file mode 100644
index 0000000..f63f268
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/implicitfloat.ll
@@ -0,0 +1,25 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+; Don't vectorize when noimplicitfloat is used.
+; CHECK: test1
+; CHECK-NOT: store <2 x double>
+; CHECK: ret
+define void @test1(double* %a, double* %b, double* %c) noimplicitfloat { ; <------ noimplicitfloat attribute here!
+entry:
+  %i0 = load double* %a, align 8
+  %i1 = load double* %b, align 8
+  %mul = fmul double %i0, %i1
+  %arrayidx3 = getelementptr inbounds double* %a, i64 1
+  %i3 = load double* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds double* %b, i64 1
+  %i4 = load double* %arrayidx4, align 8
+  %mul5 = fmul double %i3, %i4
+  store double %mul, double* %c, align 8
+  %arrayidx5 = getelementptr inbounds double* %c, i64 1
+  store double %mul5, double* %arrayidx5, align 8
+  ret void
+}
+
diff --git a/test/Transforms/SLPVectorizer/X86/in-tree-user.ll b/test/Transforms/SLPVectorizer/X86/in-tree-user.ll
index 69dc889..3115232 100644
--- a/test/Transforms/SLPVectorizer/X86/in-tree-user.ll
+++ b/test/Transforms/SLPVectorizer/X86/in-tree-user.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-apple-macosx10.7.0"
 @.str = private unnamed_addr constant [6 x i8] c"bingo\00", align 1
 
 ; We can't vectorize when the roots are used inside the tree.
-;CHECK: @in_tree_user
+;CHECK-LABEL: @in_tree_user(
 ;CHECK-NOT: load <2 x double>
 ;CHECK: ret
 define void @in_tree_user(double* nocapture %A, i32 %n) {
diff --git a/test/Transforms/SLPVectorizer/X86/long_chains.ll b/test/Transforms/SLPVectorizer/X86/long_chains.ll
new file mode 100644
index 0000000..5af3e6d
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/long_chains.ll
@@ -0,0 +1,47 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+; At this point we can't vectorize only parts of the tree.
+
+; CHECK: test
+; CHECK: insertelement <2 x i8>
+; CHECK: insertelement <2 x i8>
+; CHECK: sitofp <2 x i8>
+; CHECK: fmul <2 x double>
+; CHECK: ret
+define i32 @test(double* nocapture %A, i8* nocapture %B) {
+entry:
+  %0 = load i8* %B, align 1
+  %arrayidx1 = getelementptr inbounds i8* %B, i64 1
+  %1 = load i8* %arrayidx1, align 1
+  %add = add i8 %0, 3
+  %add4 = add i8 %1, 3
+  %conv6 = sitofp i8 %add to double
+  %conv7 = sitofp i8 %add4 to double 
+  %mul = fmul double %conv6, %conv6
+  %add8 = fadd double %mul, 1.000000e+00
+  %mul9 = fmul double %conv7, %conv7
+  %add10 = fadd double %mul9, 1.000000e+00
+  %mul11 = fmul double %add8, %add8
+  %add12 = fadd double %mul11, 1.000000e+00
+  %mul13 = fmul double %add10, %add10
+  %add14 = fadd double %mul13, 1.000000e+00
+  %mul15 = fmul double %add12, %add12
+  %add16 = fadd double %mul15, 1.000000e+00
+  %mul17 = fmul double %add14, %add14
+  %add18 = fadd double %mul17, 1.000000e+00
+  %mul19 = fmul double %add16, %add16
+  %add20 = fadd double %mul19, 1.000000e+00
+  %mul21 = fmul double %add18, %add18
+  %add22 = fadd double %mul21, 1.000000e+00
+  %mul23 = fmul double %add20, %add20
+  %add24 = fadd double %mul23, 1.000000e+00
+  %mul25 = fmul double %add22, %add22
+  %add26 = fadd double %mul25, 1.000000e+00
+  store double %add24, double* %A, align 8
+  %arrayidx28 = getelementptr inbounds double* %A, i64 1
+  store double %add26, double* %arrayidx28, align 8
+  ret i32 undef
+}
diff --git a/test/Transforms/SLPVectorizer/X86/loopinvariant.ll b/test/Transforms/SLPVectorizer/X86/loopinvariant.ll
index 4a37fce..aef2479 100644
--- a/test/Transforms/SLPVectorizer/X86/loopinvariant.ll
+++ b/test/Transforms/SLPVectorizer/X86/loopinvariant.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.8.0"
 
-;CHECK: @foo
+;CHECK-LABEL: @foo(
 ;CHECK: load <4 x i32>
 ;CHECK: add <4 x i32>
 ;CHECK: store <4 x i32>
diff --git a/test/Transforms/SLPVectorizer/X86/multi_block.ll b/test/Transforms/SLPVectorizer/X86/multi_block.ll
new file mode 100644
index 0000000..2f1cc74
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/multi_block.ll
@@ -0,0 +1,55 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.7.0"
+
+; int bar(double *A, int d) {
+;   double A0 = A[0];
+;   double A1 = A[1];
+;   float F0 = A0;
+;   float F1 = A1;
+;   if (d) foo(); <----- This splits the blocks
+;   F0+=4.0;
+;   F1+=5.0;
+;   A[8] = 9.0 + F0;
+;   A[9] = 5.0 + F1;
+; }
+
+
+;CHECK-LABEL: @bar(
+;CHECK: load <2 x double>
+;CHECK: fptrunc <2 x double>
+;CHECK: call i32
+;CHECK: fadd <2 x float>
+;CHECK: fpext <2 x float>
+;CHECK: store <2 x double>
+;CHECK: ret
+define i32 @bar(double* nocapture %A, i32 %d) {
+  %1 = load double* %A, align 8
+  %2 = getelementptr inbounds double* %A, i64 1
+  %3 = load double* %2, align 8
+  %4 = fptrunc double %1 to float
+  %5 = fptrunc double %3 to float
+  %6 = icmp eq i32 %d, 0
+  br i1 %6, label %9, label %7
+
+; <label>:7                                       ; preds = %0
+  %8 = tail call i32 (...)* @foo()
+  br label %9
+
+; <label>:9                                       ; preds = %0, %7
+  %10 = fadd float %4, 4.000000e+00
+  %11 = fadd float %5, 5.000000e+00
+  %12 = fpext float %10 to double
+  %13 = fadd double %12, 9.000000e+00
+  %14 = getelementptr inbounds double* %A, i64 8
+  store double %13, double* %14, align 8
+  %15 = fpext float %11 to double
+  %16 = fadd double %15, 5.000000e+00
+  %17 = getelementptr inbounds double* %A, i64 9
+  store double %16, double* %17, align 8
+  ret i32 undef
+}
+
+declare i32 @foo(...)
+
diff --git a/test/Transforms/SLPVectorizer/X86/multi_user.ll b/test/Transforms/SLPVectorizer/X86/multi_user.ll
index d4d4d28..cab9994 100644
--- a/test/Transforms/SLPVectorizer/X86/multi_user.ll
+++ b/test/Transforms/SLPVectorizer/X86/multi_user.ll
@@ -11,9 +11,9 @@ target triple = "x86_64-apple-macosx10.7.0"
 ;  A[4] += n * 5 + 11;
 ;}
 
-;CHECK: @foo
-;CHECK: load <4 x i32>
+;CHECK-LABEL: @foo(
 ;CHECK: insertelement <4 x i32>
+;CHECK: load <4 x i32>
 ;CHECK: add <4 x i32>
 ;CHECK: store <4 x i32>
 ;CHECK: ret
diff --git a/test/Transforms/SLPVectorizer/X86/odd_store.ll b/test/Transforms/SLPVectorizer/X86/odd_store.ll
new file mode 100644
index 0000000..027f601
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/odd_store.ll
@@ -0,0 +1,46 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+;int foo(char * restrict A, float * restrict B, float T) {
+;  A[0] = (T * B[10] + 4.0);
+;  A[1] = (T * B[11] + 5.0);
+;  A[2] = (T * B[12] + 6.0);
+;}
+
+;CHECK-LABEL: @foo(
+;CHECK-NOT: load <3 x float>
+;CHECK-NOT: fmul <3 x float>
+;CHECK-NOT: fpext <3 x float>
+;CHECK-NOT: fadd <3 x double>
+;CHECK-NOT: fptosi <3 x double>
+;CHECK-NOT: store <3 x i8>
+;CHECK: ret
+define i32 @foo(i8* noalias nocapture %A, float* noalias nocapture %B, float %T) {
+  %1 = getelementptr inbounds float* %B, i64 10
+  %2 = load float* %1, align 4
+  %3 = fmul float %2, %T
+  %4 = fpext float %3 to double
+  %5 = fadd double %4, 4.000000e+00
+  %6 = fptosi double %5 to i8
+  store i8 %6, i8* %A, align 1
+  %7 = getelementptr inbounds float* %B, i64 11
+  %8 = load float* %7, align 4
+  %9 = fmul float %8, %T
+  %10 = fpext float %9 to double
+  %11 = fadd double %10, 5.000000e+00
+  %12 = fptosi double %11 to i8
+  %13 = getelementptr inbounds i8* %A, i64 1
+  store i8 %12, i8* %13, align 1
+  %14 = getelementptr inbounds float* %B, i64 12
+  %15 = load float* %14, align 4
+  %16 = fmul float %15, %T
+  %17 = fpext float %16 to double
+  %18 = fadd double %17, 6.000000e+00
+  %19 = fptosi double %18 to i8
+  %20 = getelementptr inbounds i8* %A, i64 2
+  store i8 %19, i8* %20, align 1
+  ret i32 undef
+}
+
diff --git a/test/Transforms/SLPVectorizer/X86/phi.ll b/test/Transforms/SLPVectorizer/X86/phi.ll
new file mode 100644
index 0000000..1c7f9cc
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/phi.ll
@@ -0,0 +1,97 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=i386-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128"
+target triple = "i386-apple-macosx10.9.0"
+
+;int foo(double *A, int k) {
+;  double A0;
+;  double A1;
+;  if (k) {
+;    A0 = 3;
+;    A1 = 5;
+;  } else {
+;    A0 = A[10];
+;    A1 = A[11];
+;  }
+;  A[0] = A0;
+;  A[1] = A1;
+;}
+
+
+;CHECK: i32 @foo
+;CHECK: load <2 x double>
+;CHECK: phi <2 x double>
+;CHECK: store <2 x double>
+;CHECK: ret i32 undef
+define i32 @foo(double* nocapture %A, i32 %k) {
+entry:
+  %tobool = icmp eq i32 %k, 0
+  br i1 %tobool, label %if.else, label %if.end
+
+if.else:                                          ; preds = %entry
+  %arrayidx = getelementptr inbounds double* %A, i64 10
+  %0 = load double* %arrayidx, align 8
+  %arrayidx1 = getelementptr inbounds double* %A, i64 11
+  %1 = load double* %arrayidx1, align 8
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.else
+  %A0.0 = phi double [ %0, %if.else ], [ 3.000000e+00, %entry ]
+  %A1.0 = phi double [ %1, %if.else ], [ 5.000000e+00, %entry ]
+  store double %A0.0, double* %A, align 8
+  %arrayidx3 = getelementptr inbounds double* %A, i64 1
+  store double %A1.0, double* %arrayidx3, align 8
+  ret i32 undef
+}
+
+
+;int foo(double * restrict B,  double * restrict A, int n, int m) {
+;  double R=A[1];
+;  double G=A[0];
+;  for (int i=0; i < 100; i++) {
+;    R += 10;
+;    G += 10;
+;    R *= 4;
+;    G *= 4;
+;    R += 4;
+;    G += 4;
+;  }
+;  B[0] = G;
+;  B[1] = R;
+;  return 0;
+;}
+
+;CHECK: foo2
+;CHECK: load <2 x double>
+;CHECK: phi <2 x double>
+;CHECK: fmul <2 x double>
+;CHECK: store <2 x double>
+;CHECK: ret
+define i32 @foo2(double* noalias nocapture %B, double* noalias nocapture %A, i32 %n, i32 %m) #0 {
+entry:
+  %arrayidx = getelementptr inbounds double* %A, i64 1
+  %0 = load double* %arrayidx, align 8
+  %1 = load double* %A, align 8
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %entry
+  %i.019 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %G.018 = phi double [ %1, %entry ], [ %add5, %for.body ]
+  %R.017 = phi double [ %0, %entry ], [ %add4, %for.body ]
+  %add = fadd double %R.017, 1.000000e+01
+  %add2 = fadd double %G.018, 1.000000e+01
+  %mul = fmul double %add, 4.000000e+00
+  %mul3 = fmul double %add2, 4.000000e+00
+  %add4 = fadd double %mul, 4.000000e+00
+  %add5 = fadd double %mul3, 4.000000e+00
+  %inc = add nsw i32 %i.019, 1
+  %exitcond = icmp eq i32 %inc, 100
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body
+  store double %add5, double* %B, align 8
+  %arrayidx7 = getelementptr inbounds double* %B, i64 1
+  store double %add4, double* %arrayidx7, align 8
+  ret i32 0
+}
+
diff --git a/test/Transforms/SLPVectorizer/X86/phi3.ll b/test/Transforms/SLPVectorizer/X86/phi3.ll
new file mode 100644
index 0000000..fd8d361
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/phi3.ll
@@ -0,0 +1,35 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+%struct.GPar.0.16.26 = type { [0 x double], double }
+
+@d = external global double, align 8
+
+declare %struct.GPar.0.16.26* @Rf_gpptr(...)
+
+define void @Rf_GReset() {
+entry:
+  %sub = fsub double -0.000000e+00, undef
+  %0 = load double* @d, align 8
+  %sub1 = fsub double -0.000000e+00, %0
+  br i1 icmp eq (%struct.GPar.0.16.26* (...)* inttoptr (i64 115 to %struct.GPar.0.16.26* (...)*), %struct.GPar.0.16.26* (...)* @Rf_gpptr), label %if.then, label %if.end7
+
+if.then:                                          ; preds = %entry
+  %sub2 = fsub double %sub, undef
+  %div.i = fdiv double %sub2, undef
+  %sub4 = fsub double %sub1, undef
+  %div.i16 = fdiv double %sub4, undef
+  %cmp = fcmp ogt double %div.i, %div.i16
+  br i1 %cmp, label %if.then6, label %if.end7
+
+if.then6:                                         ; preds = %if.then
+  br label %if.end7
+
+if.end7:                                          ; preds = %if.then6, %if.then, %entry
+  %g.0 = phi double [ 0.000000e+00, %if.then6 ], [ %sub, %if.then ], [ %sub, %entry ]
+  ret void
+}
+
+
diff --git a/test/Transforms/SLPVectorizer/X86/pr16571.ll b/test/Transforms/SLPVectorizer/X86/pr16571.ll
new file mode 100644
index 0000000..13d8214
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/pr16571.ll
@@ -0,0 +1,22 @@
+; RUN: opt < %s -slp-vectorizer -S -mtriple=i686-pc-win32 -mcpu=corei7-avx
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"
+target triple = "i686-pc-win32"
+
+define hidden fastcc void @"System.PrimitiveTypesParser.TryParseIEEE754<char>(char*,uint,double&)"() unnamed_addr {
+"@0":
+  br i1 undef, label %"@38.lr.ph", label %"@37"
+
+"@37":                                            ; preds = %"@38.lr.ph", %"@44", %"@0"
+  ret void
+
+"@44":                                            ; preds = %"@38.lr.ph"
+  %0 = add i64 undef, undef
+  %1 = add i32 %mainPartDigits.loc.0.ph45, 1
+  br i1 undef, label %"@38.lr.ph", label %"@37"
+
+"@38.lr.ph":                                      ; preds = %"@44", %"@0"
+  %mainDoublePart.loc.0.ph46 = phi i64 [ %0, %"@44" ], [ 0, %"@0" ]
+  %mainPartDigits.loc.0.ph45 = phi i32 [ %1, %"@44" ], [ 0, %"@0" ]
+  br i1 undef, label %"@44", label %"@37"
+}
diff --git a/test/Transforms/SLPVectorizer/X86/pr16628.ll b/test/Transforms/SLPVectorizer/X86/pr16628.ll
new file mode 100644
index 0000000..3f9d775
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/pr16628.ll
@@ -0,0 +1,27 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.9.0"
+
+@c = common global i32 0, align 4
+@a = common global i16 0, align 2
+@b = common global i16 0, align 2
+
+; Function Attrs: nounwind ssp uwtable
+define void @f() {
+entry:
+  %call = tail call i32 (...)* @g()
+  %0 = load i32* @c, align 4
+  %lnot = icmp eq i32 %0, 0
+  %lnot.ext = zext i1 %lnot to i32
+  %1 = load i16* @a, align 2
+  %lnot2 = icmp eq i16 %1, 0
+  %lnot.ext3 = zext i1 %lnot2 to i32
+  %or = or i32 %lnot.ext3, %lnot.ext
+  %cmp = icmp eq i32 %call, %or
+  %conv4 = zext i1 %cmp to i16
+  store i16 %conv4, i16* @b, align 2
+  ret void
+}
+
+declare i32 @g(...)
diff --git a/test/Transforms/SLPVectorizer/X86/reduction2.ll b/test/Transforms/SLPVectorizer/X86/reduction2.ll
index 7aa7d7e..f21e86c 100644
--- a/test/Transforms/SLPVectorizer/X86/reduction2.ll
+++ b/test/Transforms/SLPVectorizer/X86/reduction2.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128"
 target triple = "i386-apple-macosx10.8.0"
 
-;CHECK: @foo
+;CHECK-LABEL: @foo(
 ;CHECK: load <2 x double>
 ;CHECK: ret
 define double @foo(double* nocapture %D) {
@@ -16,11 +16,13 @@ define double @foo(double* nocapture %D) {
   %3 = getelementptr inbounds double* %D, i32 %2
   %4 = load double* %3, align 4
   %A4 = fmul double %4, %4
+  %A42 = fmul double %A4, %A4
   %5 = or i32 %2, 1
   %6 = getelementptr inbounds double* %D, i32 %5
   %7 = load double* %6, align 4
   %A7 = fmul double %7, %7
-  %8 = fadd double %A4, %A7
+  %A72 = fmul double %A7, %A7
+  %8 = fadd double %A42, %A72
   %9 = fadd double %sum.01, %8
   %10 = add nsw i32 %i.02, 1
   %exitcond = icmp eq i32 %10, 100
diff --git a/test/Transforms/SLPVectorizer/X86/rgb_phi.ll b/test/Transforms/SLPVectorizer/X86/rgb_phi.ll
new file mode 100644
index 0000000..3235fd9
--- /dev/null
+++ b/test/Transforms/SLPVectorizer/X86/rgb_phi.ll
@@ -0,0 +1,74 @@
+; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=i386-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128"
+target triple = "i386-apple-macosx10.9.0"
+
+; float foo(float *A) {
+;
+;   float R = A[0];
+;   float G = A[1];
+;   float B = A[2];
+;   for (int i=0; i < 121; i+=3) {
+;     R+=A[i+0]*7;
+;     G+=A[i+1]*8;
+;     B+=A[i+2]*9;
+;   }
+;
+;   return R+G+B;
+; }
+
+;CHECK-LABEL: @foo(
+;CHECK: br
+;CHECK: phi <3 x float>
+;CHECK: fmul <3 x float>
+;CHECK: fadd <3 x float>
+; At the moment we don't sink extractelements.
+;CHECK: br
+;CHECK: extractelement
+;CHECK: extractelement
+;CHECK: extractelement
+;CHECK: ret
+
+define float @foo(float* nocapture readonly %A) {
+entry:
+  %0 = load float* %A, align 4
+  %arrayidx1 = getelementptr inbounds float* %A, i64 1
+  %1 = load float* %arrayidx1, align 4
+  %arrayidx2 = getelementptr inbounds float* %A, i64 2
+  %2 = load float* %arrayidx2, align 4
+  br label %for.body
+
+for.body:                                         ; preds = %for.body.for.body_crit_edge, %entry
+  %3 = phi float [ %0, %entry ], [ %.pre, %for.body.for.body_crit_edge ]
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body.for.body_crit_edge ]
+  %B.032 = phi float [ %2, %entry ], [ %add14, %for.body.for.body_crit_edge ]
+  %G.031 = phi float [ %1, %entry ], [ %add9, %for.body.for.body_crit_edge ]
+  %R.030 = phi float [ %0, %entry ], [ %add4, %for.body.for.body_crit_edge ]
+  %mul = fmul float %3, 7.000000e+00
+  %add4 = fadd float %R.030, %mul
+  %4 = add nsw i64 %indvars.iv, 1
+  %arrayidx7 = getelementptr inbounds float* %A, i64 %4
+  %5 = load float* %arrayidx7, align 4
+  %mul8 = fmul float %5, 8.000000e+00
+  %add9 = fadd float %G.031, %mul8
+  %6 = add nsw i64 %indvars.iv, 2
+  %arrayidx12 = getelementptr inbounds float* %A, i64 %6
+  %7 = load float* %arrayidx12, align 4
+  %mul13 = fmul float %7, 9.000000e+00
+  %add14 = fadd float %B.032, %mul13
+  %indvars.iv.next = add i64 %indvars.iv, 3
+  %8 = trunc i64 %indvars.iv.next to i32
+  %cmp = icmp slt i32 %8, 121
+  br i1 %cmp, label %for.body.for.body_crit_edge, label %for.end
+
+for.body.for.body_crit_edge:                      ; preds = %for.body
+  %arrayidx3.phi.trans.insert = getelementptr inbounds float* %A, i64 %indvars.iv.next
+  %.pre = load float* %arrayidx3.phi.trans.insert, align 4
+  br label %for.body
+
+for.end:                                          ; preds = %for.body
+  %add16 = fadd float %add4, %add9
+  %add17 = fadd float %add16, %add14
+  ret float %add17
+}
+
diff --git a/test/Transforms/SLPVectorizer/X86/saxpy.ll b/test/Transforms/SLPVectorizer/X86/saxpy.ll
index b520913..4626341 100644
--- a/test/Transforms/SLPVectorizer/X86/saxpy.ll
+++ b/test/Transforms/SLPVectorizer/X86/saxpy.ll
@@ -43,3 +43,19 @@ define void @SAXPY(i32* noalias nocapture %x, i32* noalias nocapture %y, i32 %a,
   ret void
 }
 
+; Make sure we don't crash on this one.
+define void @SAXPY_crash(i32* noalias nocapture %x, i32* noalias nocapture %y, i64 %i) {
+  %1 = add i64 %i, 1
+  %2 = getelementptr inbounds i32* %x, i64 %1
+  %3 = getelementptr inbounds i32* %y, i64 %1
+  %4 = load i32* %3, align 4
+  %5 = add nsw i32 undef, %4
+  store i32 %5, i32* %2, align 4
+  %6 = add i64 %i, 2
+  %7 = getelementptr inbounds i32* %x, i64 %6
+  %8 = getelementptr inbounds i32* %y, i64 %6
+  %9 = load i32* %8, align 4
+  %10 = add nsw i32 undef, %9
+  store i32 %10, i32* %7, align 4
+  ret void
+}
diff --git a/test/Transforms/SROA/alignment.ll b/test/Transforms/SROA/alignment.ll
index ad5fb6c..5fa78766 100644
--- a/test/Transforms/SROA/alignment.ll
+++ b/test/Transforms/SROA/alignment.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
 
 define void @test1({ i8, i8 }* %a, { i8, i8 }* %b) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %[[gep_a0:.*]] = getelementptr inbounds { i8, i8 }* %a, i64 0, i32 0
 ; CHECK: %[[a0:.*]] = load i8* %[[gep_a0]], align 16
 ; CHECK: %[[gep_a1:.*]] = getelementptr inbounds { i8, i8 }* %a, i64 0, i32 1
@@ -29,7 +29,7 @@ entry:
 }
 
 define void @test2() {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: alloca i16
 ; CHECK: load i8* %{{.*}}
 ; CHECK: store i8 42, i8* %{{.*}}
@@ -48,7 +48,7 @@ entry:
 
 define void @PR13920(<2 x i64>* %a, i16* %b) {
 ; Test that alignments on memcpy intrinsics get propagated to loads and stores.
-; CHECK: @PR13920
+; CHECK-LABEL: @PR13920(
 ; CHECK: load <2 x i64>* %a, align 2
 ; CHECK: store <2 x i64> {{.*}}, <2 x i64>* {{.*}}, align 2
 ; CHECK: ret void
@@ -68,7 +68,7 @@ define void @test3(i8* %x) {
 ; provide the needed explicit alignment that code using the alloca may be
 ; expecting. However, also check that any offset within an alloca can in turn
 ; reduce the alignment.
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: alloca [22 x i8], align 8
 ; CHECK: alloca [18 x i8], align 2
 ; CHECK: ret void
@@ -86,7 +86,7 @@ entry:
 
 define void @test5() {
 ; Test that we preserve underaligned loads and stores when splitting.
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: alloca [9 x i8]
 ; CHECK: alloca [9 x i8]
 ; CHECK: store volatile double 0.0{{.*}}, double* %{{.*}}, align 1
@@ -119,7 +119,7 @@ entry:
 define void @test6() {
 ; Test that we promote alignment when the underlying alloca switches to one
 ; that innately provides it.
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: alloca double
 ; CHECK: alloca double
 ; CHECK-NOT: align
@@ -142,7 +142,7 @@ entry:
 define void @test7(i8* %out) {
 ; Test that we properly compute the destination alignment when rewriting
 ; memcpys as direct loads or stores.
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NOT: alloca
 
 entry:
diff --git a/test/Transforms/SROA/basictest.ll b/test/Transforms/SROA/basictest.ll
index 8340322..458b0df 100644
--- a/test/Transforms/SROA/basictest.ll
+++ b/test/Transforms/SROA/basictest.ll
@@ -7,7 +7,7 @@ declare void @llvm.lifetime.start(i64, i8* nocapture)
 declare void @llvm.lifetime.end(i64, i8* nocapture)
 
 define i32 @test0() {
-; CHECK: @test0
+; CHECK-LABEL: @test0(
 ; CHECK-NOT: alloca
 ; CHECK: ret i32
 
@@ -37,7 +37,7 @@ entry:
 }
 
 define i32 @test1() {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NOT: alloca
 ; CHECK: ret i32 0
 
@@ -50,7 +50,7 @@ entry:
 }
 
 define i64 @test2(i64 %X) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NOT: alloca
 ; CHECK: ret i64 %X
 
@@ -66,7 +66,7 @@ L2:
 }
 
 define void @test3(i8* %dst, i8* %src) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 
 entry:
   %a = alloca [300 x i8]
@@ -302,7 +302,7 @@ entry:
 }
 
 define void @test4(i8* %dst, i8* %src) {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 
 entry:
   %a = alloca [100 x i8]
@@ -408,7 +408,7 @@ declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32,
 declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
 
 define i16 @test5() {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NOT: alloca float
 ; CHECK:      %[[cast:.*]] = bitcast float 0.0{{.*}} to i32
 ; CHECK-NEXT: %[[shr:.*]] = lshr i32 %[[cast]], 16
@@ -426,7 +426,7 @@ entry:
 }
 
 define i32 @test6() {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: alloca i32
 ; CHECK-NEXT: store volatile i32
 ; CHECK-NEXT: load i32*
@@ -442,7 +442,7 @@ entry:
 }
 
 define void @test7(i8* %src, i8* %dst) {
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK: alloca i32
 ; CHECK-NEXT: bitcast i8* %src to i32*
 ; CHECK-NEXT: load volatile i32*
@@ -465,7 +465,7 @@ entry:
 %S2 = type { %S1*, %S2* }
 
 define %S2 @test8(%S2* %s2) {
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 entry:
   %new = alloca %S2
 ; CHECK-NOT: alloca
@@ -503,7 +503,7 @@ define i64 @test9() {
 ; weird bit casts and types. This is valid IR due to the alignment and masking
 ; off the bits past the end of the alloca.
 ;
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NOT: alloca
 ; CHECK:      %[[b2:.*]] = zext i8 26 to i64
 ; CHECK-NEXT: %[[s2:.*]] = shl i64 %[[b2]], 16
@@ -535,7 +535,7 @@ entry:
 }
 
 define %S2* @test10() {
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK-NOT: alloca %S2*
 ; CHECK: ret %S2* null
 
@@ -549,7 +549,7 @@ entry:
 }
 
 define i32 @test11() {
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK-NOT: alloca
 ; CHECK: ret i32 0
 
@@ -574,7 +574,7 @@ define i8 @test12() {
 ; We fully promote these to the i24 load or store size, resulting in just masks
 ; and other operations that instcombine will fold, but no alloca.
 ;
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 
 entry:
   %a = alloca [3 x i8]
@@ -630,7 +630,7 @@ entry:
 define i32 @test13() {
 ; Ensure we don't crash and handle undefined loads that straddle the end of the
 ; allocation.
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK:      %[[value:.*]] = zext i8 0 to i16
 ; CHECK-NEXT: %[[ret:.*]] = zext i16 %[[value]] to i32
 ; CHECK-NEXT: ret i32 %[[ret]]
@@ -657,7 +657,7 @@ define void @test14(...) nounwind uwtable {
 ; also gain enough data to prove they must be dead allocas due to GEPs that walk
 ; across two adjacent allocas. Test that we don't try to promote or otherwise
 ; do bad things to these dead allocas, they should just be removed.
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: ret void
 
@@ -688,7 +688,7 @@ define i32 @test15(i1 %flag) nounwind uwtable {
 ; Ensure that when there are dead instructions using an alloca that are not
 ; loads or stores we still delete them during partitioning and rewriting.
 ; Otherwise we'll go to promote them while thy still have unpromotable uses.
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT:   br label %loop
 ; CHECK:      loop:
@@ -731,7 +731,7 @@ loop:
 
 define void @test16(i8* %src, i8* %dst) {
 ; Ensure that we can promote an alloca of [3 x i8] to an i24 SSA value.
-; CHECK: @test16
+; CHECK-LABEL: @test16(
 ; CHECK-NOT: alloca
 ; CHECK:      %[[srccast:.*]] = bitcast i8* %src to i24*
 ; CHECK-NEXT: load i24* %[[srccast]]
@@ -752,7 +752,7 @@ entry:
 define void @test17(i8* %src, i8* %dst) {
 ; Ensure that we can rewrite unpromotable memcpys which extend past the end of
 ; the alloca.
-; CHECK: @test17
+; CHECK-LABEL: @test17(
 ; CHECK:      %[[a:.*]] = alloca [3 x i8]
 ; CHECK-NEXT: %[[ptr:.*]] = getelementptr [3 x i8]* %[[a]], i32 0, i32 0
 ; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %[[ptr]], i8* %src,
@@ -771,7 +771,7 @@ define void @test18(i8* %src, i8* %dst, i32 %size) {
 ; Preserve transfer instrinsics with a variable size, even if they overlap with
 ; fixed size operations. Further, continue to split and promote allocas preceding
 ; the variable sized intrinsic.
-; CHECK: @test18
+; CHECK-LABEL: @test18(
 ; CHECK:      %[[a:.*]] = alloca [34 x i8]
 ; CHECK:      %[[srcgep1:.*]] = getelementptr inbounds i8* %src, i64 4
 ; CHECK-NEXT: %[[srccast1:.*]] = bitcast i8* %[[srcgep1]] to i32*
@@ -810,7 +810,7 @@ define i32 @test19(%opaque* %x) {
 ; pointers in such a way that we try to GEP through the opaque type. Previously,
 ; a check for an unsized type was missing and this crashed. Ensure it behaves
 ; reasonably now.
-; CHECK: @test19
+; CHECK-LABEL: @test19(
 ; CHECK-NOT: alloca
 ; CHECK: ret i32 undef
 
@@ -827,7 +827,7 @@ entry:
 define i32 @test20() {
 ; Ensure we can track negative offsets (before the beginning of the alloca) and
 ; negative relative offsets from offsets starting past the end of the alloca.
-; CHECK: @test20
+; CHECK-LABEL: @test20(
 ; CHECK-NOT: alloca
 ; CHECK: %[[sum1:.*]] = add i32 1, 2
 ; CHECK: %[[sum2:.*]] = add i32 %[[sum1]], 3
@@ -858,7 +858,7 @@ define i8 @test21() {
 ; Test allocations and offsets which border on overflow of the int64_t used
 ; internally. This is really awkward to really test as LLVM doesn't really
 ; support such extreme constructs cleanly.
-; CHECK: @test21
+; CHECK-LABEL: @test21(
 ; CHECK-NOT: alloca
 ; CHECK: or i8 -1, -1
 
@@ -926,7 +926,7 @@ define void @PR13990() {
 ; Ensure we can handle cases where processing one alloca causes the other
 ; alloca to become dead and get deleted. This might crash or fail under
 ; Valgrind if we regress.
-; CHECK: @PR13990
+; CHECK-LABEL: @PR13990(
 ; CHECK-NOT: alloca
 ; CHECK: unreachable
 ; CHECK: unreachable
@@ -955,7 +955,7 @@ define double @PR13969(double %x) {
 ; Check that we detect when promotion will un-escape an alloca and iterate to
 ; re-try running SROA over that alloca. Without that, the two allocas that are
 ; stored into a dead alloca don't get rewritten and promoted.
-; CHECK: @PR13969
+; CHECK-LABEL: @PR13969(
 
 entry:
   %a = alloca double
@@ -982,7 +982,7 @@ define void @PR14034() {
 ; This test case tries to form GEPs into the empty leading struct members, and
 ; subsequently crashed (under valgrind) before we fixed the PR. The important
 ; thing is to handle empty structs gracefully.
-; CHECK: @PR14034
+; CHECK-LABEL: @PR14034(
 
 entry:
   %a = alloca %PR14034.struct
@@ -998,7 +998,7 @@ entry:
 define i32 @test22(i32 %x) {
 ; Test that SROA and promotion is not confused by a grab bax mixture of pointer
 ; types involving wrapper aggregates and zero-length aggregate members.
-; CHECK: @test22
+; CHECK-LABEL: @test22(
 
 entry:
   %a1 = alloca { { [1 x { i32 }] } }
@@ -1134,7 +1134,7 @@ define void @PR14105({ [16 x i8] }* %ptr) {
 ; Ensure that when rewriting the GEP index '-1' for this alloca we preserve is
 ; sign as negative. We use a volatile memcpy to ensure promotion never actually
 ; occurs.
-; CHECK: @PR14105
+; CHECK-LABEL: @PR14105(
 
 entry:
   %a = alloca { [16 x i8] }, align 8
@@ -1153,7 +1153,7 @@ entry:
 define void @PR14465() {
 ; Ensure that we don't crash when analyzing a alloca larger than the maximum
 ; integer type width (MAX_INT_BITS) supported by llvm (1048576*32 > (1<<23)-1).
-; CHECK: @PR14465
+; CHECK-LABEL: @PR14465(
 
   %stack = alloca [1048576 x i32], align 16
 ; CHECK: alloca [1048576 x i32]
@@ -1170,7 +1170,7 @@ define void @PR14548(i1 %x) {
 ; iteratively.
 ; Note that we don't do a particularly good *job* of handling these mixtures,
 ; but the hope is that this is very rare.
-; CHECK: @PR14548
+; CHECK-LABEL: @PR14548(
 
 entry:
   %a = alloca <{ i1 }>, align 8
@@ -1232,7 +1232,7 @@ entry:
 define i32 @PR14601(i32 %x) {
 ; Don't try to form a promotable integer alloca when there is a variable length
 ; memory intrinsic.
-; CHECK: @PR14601
+; CHECK-LABEL: @PR14601(
 
 entry:
   %a = alloca i32
@@ -1250,7 +1250,7 @@ define void @PR15674(i8* %data, i8* %src, i32 %size) {
 ; beginning of the array. Ensure that the final integer store, despite being
 ; convertable to the integer type that we end up promoting this alloca toward,
 ; doesn't get widened to a full alloca store.
-; CHECK: @PR15674
+; CHECK-LABEL: @PR15674(
 
 entry:
   %tmp = alloca [4 x i8], align 1
@@ -1307,8 +1307,8 @@ end:
 }
 
 define void @PR15805(i1 %a, i1 %b) {
-; CHECK: @PR15805
-; CHECK: select i1 undef, i64* %c, i64* %c
+; CHECK-LABEL: @PR15805(
+; CHECK-NOT: alloca
 ; CHECK: ret void
 
   %c = alloca i64, align 8
@@ -1317,3 +1317,43 @@ define void @PR15805(i1 %a, i1 %b) {
   %cond = load i64* %cond.in, align 8
   ret void
 }
+
+define void @PR16651.1(i8* %a) {
+; This test case caused a crash due to the volatile memcpy in combination with
+; lowering to integer loads and stores of a width other than that of the original
+; memcpy.
+;
+; CHECK-LABEL: @PR16651.1(
+; CHECK: alloca i16
+; CHECK: alloca i8
+; CHECK: alloca i8
+; CHECK: unreachable
+
+entry:
+  %b = alloca i32, align 4
+  %b.cast = bitcast i32* %b to i8*
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %b.cast, i8* %a, i32 4, i32 4, i1 true)
+  %b.gep = getelementptr inbounds i8* %b.cast, i32 2
+  load i8* %b.gep, align 2
+  unreachable
+}
+
+define void @PR16651.2() {
+; This test case caused a crash due to failing to promote given a select that
+; can't be speculated. It shouldn't be promoted, but we missed that fact when
+; analyzing whether we could form a vector promotion because that code didn't
+; bail on select instructions.
+;
+; CHECK-LABEL: @PR16651.2(
+; CHECK: alloca <2 x float>
+; CHECK: ret void
+
+entry:
+  %tv1 = alloca { <2 x float>, <2 x float> }, align 8
+  %0 = getelementptr { <2 x float>, <2 x float> }* %tv1, i64 0, i32 1
+  store <2 x float> undef, <2 x float>* %0, align 8
+  %1 = getelementptr inbounds { <2 x float>, <2 x float> }* %tv1, i64 0, i32 1, i64 0
+  %cond105.in.i.i = select i1 undef, float* null, float* %1
+  %cond105.i.i = load float* %cond105.in.i.i, align 8
+  ret void
+}
diff --git a/test/Transforms/SROA/big-endian.ll b/test/Transforms/SROA/big-endian.ll
index 64a0cc7..9e87a9f 100644
--- a/test/Transforms/SROA/big-endian.ll
+++ b/test/Transforms/SROA/big-endian.ll
@@ -9,7 +9,7 @@ define i8 @test1() {
 ; the same as test12 in basictest.ll, but here we assert big-endian byte
 ; ordering.
 ;
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 
 entry:
   %a = alloca [3 x i8]
@@ -66,7 +66,7 @@ define i64 @test2() {
 ; Test for various mixed sizes of integer loads and stores all getting
 ; promoted.
 ;
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 
 entry:
   %a = alloca [7 x i8]
diff --git a/test/Transforms/SROA/fca.ll b/test/Transforms/SROA/fca.ll
index c30a5cc..e8b4c6c 100644
--- a/test/Transforms/SROA/fca.ll
+++ b/test/Transforms/SROA/fca.ll
@@ -3,7 +3,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
 
 define { i32, i32 } @test0(i32 %x, i32 %y) {
-; CHECK: @test0
+; CHECK-LABEL: @test0(
 ; CHECK-NOT: alloca
 ; CHECK: insertvalue { i32, i32 }
 ; CHECK: insertvalue { i32, i32 }
@@ -27,7 +27,7 @@ define { i32, i32 } @test1(i32 %x, i32 %y) {
 ; FIXME: This may be too conservative. Duncan argues that we are allowed to
 ; split the volatile load and store here but must produce volatile scalar loads
 ; and stores from them.
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: alloca
 ; CHECK: alloca
 ; CHECK: load volatile { i32, i32 }*
diff --git a/test/Transforms/SROA/phi-and-select.ll b/test/Transforms/SROA/phi-and-select.ll
index b993180..8d82964 100644
--- a/test/Transforms/SROA/phi-and-select.ll
+++ b/test/Transforms/SROA/phi-and-select.ll
@@ -2,7 +2,7 @@
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
 
 define i32 @test1() {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 entry:
 	%a = alloca [2 x i32]
 ; CHECK-NOT: alloca
@@ -31,7 +31,7 @@ exit:
 }
 
 define i32 @test2() {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 entry:
 	%a = alloca [2 x i32]
 ; CHECK-NOT: alloca
@@ -54,7 +54,7 @@ entry:
 }
 
 define i32 @test3(i32 %x) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 entry:
 	%a = alloca [2 x i32]
 ; CHECK-NOT: alloca
@@ -105,7 +105,7 @@ exit:
 }
 
 define i32 @test4() {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 entry:
 	%a = alloca [2 x i32]
 ; CHECK-NOT: alloca
@@ -129,7 +129,7 @@ entry:
 }
 
 define i32 @test5(i32* %b) {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 entry:
 	%a = alloca [2 x i32]
 ; CHECK-NOT: alloca
@@ -151,7 +151,7 @@ entry:
 declare void @f(i32*, i32*)
 
 define i32 @test6(i32* %b) {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 entry:
 	%a = alloca [2 x i32]
   %c = alloca i32
@@ -182,7 +182,7 @@ entry:
 }
 
 define i32 @test7() {
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NOT: alloca
 
 entry:
@@ -210,7 +210,7 @@ exit:
 define i32 @test8(i32 %b, i32* %ptr) {
 ; Ensure that we rewrite allocas to the used type when that use is hidden by
 ; a PHI that can be speculated.
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK-NOT: alloca
 ; CHECK-NOT: load
 ; CHECK: %[[value:.*]] = load i32* %ptr
@@ -238,7 +238,7 @@ exit:
 
 define i32 @test9(i32 %b, i32* %ptr) {
 ; Same as @test8 but for a select rather than a PHI node.
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK-NOT: alloca
 ; CHECK-NOT: load
 ; CHECK: %[[value:.*]] = load i32* %ptr
@@ -260,7 +260,7 @@ define float @test10(i32 %b, float* %ptr) {
 ; Don't try to promote allocas which are not elligible for it even after
 ; rewriting due to the necessity of inserting bitcasts when speculating a PHI
 ; node.
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK: %[[alloca:.*]] = alloca
 ; CHECK: %[[argvalue:.*]] = load float* %ptr
 ; CHECK: %[[cast:.*]] = bitcast double* %[[alloca]] to float*
@@ -289,7 +289,7 @@ exit:
 
 define float @test11(i32 %b, float* %ptr) {
 ; Same as @test10 but for a select rather than a PHI node.
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK: %[[alloca:.*]] = alloca
 ; CHECK: %[[cast:.*]] = bitcast double* %[[alloca]] to float*
 ; CHECK: %[[allocavalue:.*]] = load float* %[[cast]]
@@ -311,7 +311,7 @@ entry:
 define i32 @test12(i32 %x, i32* %p) {
 ; Ensure we don't crash or fail to nuke dead selects of allocas if no load is
 ; never found.
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 ; CHECK-NOT: alloca
 ; CHECK-NOT: select
 ; CHECK: ret i32 %x
@@ -327,7 +327,7 @@ entry:
 define i32 @test13(i32 %x, i32* %p) {
 ; Ensure we don't crash or fail to nuke dead phis of allocas if no load is ever
 ; found.
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK-NOT: alloca
 ; CHECK-NOT: phi
 ; CHECK: ret i32 %x
@@ -346,10 +346,47 @@ exit:
   ret i32 %load
 }
 
+define i32 @test14(i1 %b1, i1 %b2, i32* %ptr) {
+; Check for problems when there are both selects and phis and one is
+; speculatable toward promotion but the other is not. That should block all of
+; the speculation.
+; CHECK-LABEL: @test14(
+; CHECK: alloca
+; CHECK: alloca
+; CHECK: select
+; CHECK: phi
+; CHECK: phi
+; CHECK: select
+; CHECK: ret i32
+
+entry:
+  %f = alloca i32
+  %g = alloca i32
+  store i32 0, i32* %f
+  store i32 0, i32* %g
+  %f.select = select i1 %b1, i32* %f, i32* %ptr
+  br i1 %b2, label %then, label %else
+
+then:
+  br label %exit
+
+else:
+  br label %exit
+
+exit:
+  %f.phi = phi i32* [ %f, %then ], [ %f.select, %else ]
+  %g.phi = phi i32* [ %g, %then ], [ %ptr, %else ]
+  %f.loaded = load i32* %f.phi
+  %g.select = select i1 %b1, i32* %g, i32* %g.phi
+  %g.loaded = load i32* %g.select
+  %result = add i32 %f.loaded, %g.loaded
+  ret i32 %result
+}
+
 define i32 @PR13905() {
 ; Check a pattern where we have a chain of dead phi nodes to ensure they are
 ; deleted and promotion can proceed.
-; CHECK: @PR13905
+; CHECK-LABEL: @PR13905(
 ; CHECK-NOT: alloca i32
 ; CHECK: ret i32 undef
 
@@ -374,7 +411,7 @@ define i32 @PR13906() {
 ; Another pattern which can lead to crashes due to failing to clear out dead
 ; PHI nodes or select nodes. This triggers subtly differently from the above
 ; cases because the PHI node is (recursively) alive, but the select is dead.
-; CHECK: @PR13906
+; CHECK-LABEL: @PR13906(
 ; CHECK-NOT: alloca
 
 entry:
@@ -392,7 +429,7 @@ if.then:
 }
 
 define i64 @PR14132(i1 %flag) {
-; CHECK: @PR14132
+; CHECK-LABEL: @PR14132(
 ; Here we form a PHI-node by promoting the pointer alloca first, and then in
 ; order to promote the other two allocas, we speculate the load of the
 ; now-phi-node-pointer. In doing so we end up loading a 64-bit value from an i8
@@ -427,3 +464,40 @@ if.end:
   ret i64 %result
 ; CHECK-NEXT: ret i64 %[[result]]
 }
+
+define float @PR16687(i64 %x, i1 %flag) {
+; CHECK-LABEL: @PR16687(
+; Check that even when we try to speculate the same phi twice (in two slices)
+; on an otherwise promotable construct, we don't get ahead of ourselves and try
+; to promote one of the slices prior to speculating it.
+
+entry:
+  %a = alloca i64, align 8
+  store i64 %x, i64* %a
+  br i1 %flag, label %then, label %else
+; CHECK-NOT: alloca
+; CHECK-NOT: store
+; CHECK: %[[lo:.*]] = trunc i64 %x to i32
+; CHECK: %[[shift:.*]] = lshr i64 %x, 32
+; CHECK: %[[hi:.*]] = trunc i64 %[[shift]] to i32
+
+then:
+  %a.f = bitcast i64* %a to float*
+  br label %end
+; CHECK: %[[lo_cast:.*]] = bitcast i32 %[[lo]] to float
+
+else:
+  %a.raw = bitcast i64* %a to i8*
+  %a.raw.4 = getelementptr i8* %a.raw, i64 4
+  %a.raw.4.f = bitcast i8* %a.raw.4 to float*
+  br label %end
+; CHECK: %[[hi_cast:.*]] = bitcast i32 %[[hi]] to float
+
+end:
+  %a.phi.f = phi float* [ %a.f, %then ], [ %a.raw.4.f, %else ]
+  %f = load float* %a.phi.f
+  ret float %f
+; CHECK: %[[phi:.*]] = phi float [ %[[lo_cast]], %then ], [ %[[hi_cast]], %else ]
+; CHECK-NOT: load
+; CHECK: ret float %[[phi]]
+}
diff --git a/test/Transforms/SROA/vector-promotion.ll b/test/Transforms/SROA/vector-promotion.ll
index 3336515..4f08421 100644
--- a/test/Transforms/SROA/vector-promotion.ll
+++ b/test/Transforms/SROA/vector-promotion.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 %S1 = type { i64, [42 x float] }
 
 define i32 @test1(<4 x i32> %x, <4 x i32> %y) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 entry:
 	%a = alloca [2 x <4 x i32>]
 ; CHECK-NOT: alloca
@@ -35,7 +35,7 @@ entry:
 }
 
 define i32 @test2(<4 x i32> %x, <4 x i32> %y) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 entry:
 	%a = alloca [2 x <4 x i32>]
 ; CHECK-NOT: alloca
@@ -69,7 +69,7 @@ entry:
 }
 
 define i32 @test3(<4 x i32> %x, <4 x i32> %y) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 entry:
 	%a = alloca [2 x <4 x i32>]
 ; CHECK-NOT: alloca
@@ -107,7 +107,7 @@ entry:
 }
 
 define i32 @test4(<4 x i32> %x, <4 x i32> %y, <4 x i32>* %z) {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 entry:
 	%a = alloca [2 x <4 x i32>]
 ; CHECK-NOT: alloca
@@ -151,7 +151,7 @@ entry:
 }
 
 define i32 @test5(<4 x i32> %x, <4 x i32> %y, <4 x i32>* %z) {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; The same as the above, but with reversed source and destination for the
 ; element memcpy, and a self copy.
 entry:
@@ -199,7 +199,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32,
 declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
 
 define i64 @test6(<4 x i64> %x, <4 x i64> %y, i64 %n) {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; The old scalarrepl pass would wrongly drop the store to the second alloca.
 ; PR13254
   %tmp = alloca { <4 x i64>, <4 x i64> }
@@ -215,7 +215,7 @@ define i64 @test6(<4 x i64> %x, <4 x i64> %y, i64 %n) {
 }
 
 define <4 x i32> @test_subvec_store() {
-; CHECK: @test_subvec_store
+; CHECK-LABEL: @test_subvec_store(
 entry:
   %a = alloca <4 x i32>
 ; CHECK-NOT: alloca
@@ -247,7 +247,7 @@ entry:
 }
 
 define <4 x i32> @test_subvec_load() {
-; CHECK: @test_subvec_load
+; CHECK-LABEL: @test_subvec_load(
 entry:
   %a = alloca <4 x i32>
 ; CHECK-NOT: alloca
@@ -282,7 +282,7 @@ entry:
 declare void @llvm.memset.p0i32.i32(i32* nocapture, i32, i32, i32, i1) nounwind
 
 define <4 x float> @test_subvec_memset() {
-; CHECK: @test_subvec_memset
+; CHECK-LABEL: @test_subvec_memset(
 entry:
   %a = alloca <4 x float>
 ; CHECK-NOT: alloca
@@ -315,7 +315,7 @@ entry:
 }
 
 define <4 x float> @test_subvec_memcpy(i8* %x, i8* %y, i8* %z, i8* %f, i8* %out) {
-; CHECK: @test_subvec_memcpy
+; CHECK-LABEL: @test_subvec_memcpy(
 entry:
   %a = alloca <4 x float>
 ; CHECK-NOT: alloca
@@ -363,7 +363,7 @@ entry:
 }
 
 define i32 @PR14212() {
-; CHECK: @PR14212
+; CHECK-LABEL: @PR14212(
 ; This caused a crash when "splitting" the load of the i32 in order to promote
 ; the store of <3 x i8> properly. Heavily reduced from an OpenCL test case.
 entry:
diff --git a/test/Transforms/ScalarRepl/2008-09-22-vector-gep.ll b/test/Transforms/ScalarRepl/2008-09-22-vector-gep.ll
index e7a58f1..7554b7f 100644
--- a/test/Transforms/ScalarRepl/2008-09-22-vector-gep.ll
+++ b/test/Transforms/ScalarRepl/2008-09-22-vector-gep.ll
@@ -22,4 +22,4 @@ entry:
         ret void
 }
 
-declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
\ No newline at end of file
+declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
diff --git a/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll b/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll
index 1993e4f..1f92191 100644
--- a/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll
+++ b/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll
@@ -10,7 +10,7 @@ target triple = "thumbv7-apple-darwin10"
 %union..0anon = type { %struct.int16x8x2_t }
 
 define void @test(<8 x i16> %tmp.0, %struct.int16x8x2_t* %dst) nounwind {
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK-NOT: alloca
 ; CHECK: "alloca point"
 ; CHECK: store <8 x i16>
@@ -82,7 +82,7 @@ cond.true:                                        ; preds = %entry
 cond.false:                                       ; preds = %entry
   ret void
 
-; CHECK: @test_memcpy_self
+; CHECK-LABEL: @test_memcpy_self(
 ; CHECK-NOT: alloca
 ; CHECK: br i1
 }
diff --git a/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll b/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll
index 52df6d5..b926b02 100644
--- a/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll
+++ b/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll
@@ -6,7 +6,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 %struct.test = type { [3 x double] }
 
 define void @test_memcpy_self() nounwind {
-; CHECK: @test_memcpy_self
+; CHECK-LABEL: @test_memcpy_self(
 ; CHECK-NOT: alloca
 ; CHECK: ret void
   %1 = alloca %struct.test
diff --git a/test/Transforms/ScalarRepl/2011-09-22-PHISpeculateInvoke.ll b/test/Transforms/ScalarRepl/2011-09-22-PHISpeculateInvoke.ll
index f98f3e8..5f4d0fc 100644
--- a/test/Transforms/ScalarRepl/2011-09-22-PHISpeculateInvoke.ll
+++ b/test/Transforms/ScalarRepl/2011-09-22-PHISpeculateInvoke.ll
@@ -36,5 +36,5 @@ unwind:                                           ; preds = %then
   unreachable
 }
 
-; CHECK: define void @odd_fn
+; CHECK-LABEL: define void @odd_fn(
 ; CHECK: %storemerge.in = phi i32* [ %retptr2, %else ], [ %retptr1, %then ]
diff --git a/test/Transforms/ScalarRepl/2011-10-22-VectorCrash.ll b/test/Transforms/ScalarRepl/2011-10-22-VectorCrash.ll
index cd21ff5..e445636 100644
--- a/test/Transforms/ScalarRepl/2011-10-22-VectorCrash.ll
+++ b/test/Transforms/ScalarRepl/2011-10-22-VectorCrash.ll
@@ -4,7 +4,7 @@ target triple = "thumbv7-apple-ios5.0.0"
 
 %union.anon = type { <4 x float> }
 
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK-NOT: alloca
 
 define void @test() nounwind {
diff --git a/test/Transforms/ScalarRepl/address-space.ll b/test/Transforms/ScalarRepl/address-space.ll
index 318d4e7..d8efc17 100644
--- a/test/Transforms/ScalarRepl/address-space.ll
+++ b/test/Transforms/ScalarRepl/address-space.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-apple-darwin10"
 
 %struct.anon = type { [1 x float] }
 
-; CHECK: define void @Test(
+; CHECK-LABEL: define void @Test(
 ; CHECK: load float addrspace(2)*
 ; CHECK-NEXT: fsub float
 ; CHECK: store float {{.*}}, float addrspace(2)* 
diff --git a/test/Transforms/ScalarRepl/badarray.ll b/test/Transforms/ScalarRepl/badarray.ll
index 768fec6..480e12b 100644
--- a/test/Transforms/ScalarRepl/badarray.ll
+++ b/test/Transforms/ScalarRepl/badarray.ll
@@ -7,7 +7,7 @@ target triple = "i386-pc-linux-gnu"
 ; PR3466
 ; Off end of array, don't transform.
 define i32 @test1() {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NOT: = alloca
 	%X = alloca [4 x i32]
 	%Y = getelementptr [4 x i32]* %X, i64 0, i64 6		; <i32*> [#uses=2]
@@ -20,7 +20,7 @@ define i32 @test1() {
 ; Off end of array, don't transform.
 define i32 @test2() nounwind {
 entry:
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NOT: = alloca
         %yx2.i = alloca float, align 4          ; <float*> [#uses=1]            
         %yx26.i = bitcast float* %yx2.i to i64*         ; <i64*> [#uses=1]      
@@ -34,7 +34,7 @@ entry:
 ; PR5436
 define void @test3() {
 entry:
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NOT: = alloca
 ; CHECK: store i64
   %var_1 = alloca %padded, align 8                ; <%padded*> [#uses=3]
diff --git a/test/Transforms/ScalarRepl/basictest.ll b/test/Transforms/ScalarRepl/basictest.ll
index 9676873..af3c237 100644
--- a/test/Transforms/ScalarRepl/basictest.ll
+++ b/test/Transforms/ScalarRepl/basictest.ll
@@ -7,7 +7,7 @@ define i32 @test1() {
 	store i32 0, i32* %Y
 	%Z = load i32* %Y		; <i32> [#uses=1]
 	ret i32 %Z
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NOT: alloca
 ; CHECK: ret i32 0
 }
@@ -23,7 +23,7 @@ define i64 @test2(i64 %X) {
 L2:
 	%Z = load i64* %B		; <i32> [#uses=1]
 	ret i64 %Z
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NOT: alloca
 ; CHECK: ret i64 %X
 }
diff --git a/test/Transforms/ScalarRepl/debuginfo-preserved.ll b/test/Transforms/ScalarRepl/debuginfo-preserved.ll
index 7d3bcea..27e6670 100644
--- a/test/Transforms/ScalarRepl/debuginfo-preserved.ll
+++ b/test/Transforms/ScalarRepl/debuginfo-preserved.ll
@@ -41,18 +41,18 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!0}
 
-!0 = metadata !{i32 786449, i32 0, i32 12, metadata !2, metadata !"clang version 3.0 (trunk 131941)", i1 false, metadata !"", i32 0, null, null, metadata !17, null, null} ; [ DW_TAG_compile_unit ]
-!1 = metadata !{i32 786478, metadata !2, metadata !"f", metadata !"f", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32, i32)* @f, null, null, null, i32 1} ; [ DW_TAG_subprogram ]
+!0 = metadata !{i32 786449, metadata !18, i32 12, metadata !"clang version 3.0 (trunk 131941)", i1 false, metadata !"", i32 0, metadata !19, metadata !19, metadata !17, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 786478, metadata !18, metadata !2, metadata !"f", metadata !"f", metadata !"", i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32, i32)* @f, null, null, null, i32 1} ; [ DW_TAG_subprogram ]
 !2 = metadata !{i32 786473, metadata !18} ; [ DW_TAG_file_type ]
-!3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!3 = metadata !{i32 786453, metadata !18, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 786468, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 786468, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !6 = metadata !{i32 786689, metadata !1, metadata !"a", metadata !2, i32 16777217, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !7 = metadata !{i32 1, i32 11, metadata !1, null}
 !8 = metadata !{i32 786689, metadata !1, metadata !"b", metadata !2, i32 33554433, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ]
 !9 = metadata !{i32 1, i32 18, metadata !1, null}
 !10 = metadata !{i32 786688, metadata !11, metadata !"c", metadata !2, i32 2, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ]
-!11 = metadata !{i32 786443, metadata !1, i32 1, i32 21, metadata !2, i32 0} ; [ DW_TAG_lexical_block ]
+!11 = metadata !{i32 786443, metadata !18, metadata !1, i32 1, i32 21, i32 0} ; [ DW_TAG_lexical_block ]
 !12 = metadata !{i32 2, i32 9, metadata !11, null}
 !13 = metadata !{i32 2, i32 14, metadata !11, null}
 !14 = metadata !{i32 3, i32 5, metadata !11, null}
@@ -60,3 +60,4 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
 !16 = metadata !{i32 5, i32 5, metadata !11, null}
 !17 = metadata !{metadata !1}
 !18 = metadata !{metadata !"/d/j/debug-test.c", metadata !"/Volumes/Data/b"}
+!19 = metadata !{i32 0}
diff --git a/test/Transforms/ScalarRepl/inline-vector.ll b/test/Transforms/ScalarRepl/inline-vector.ll
index 2f51cc7..f7c70dc 100644
--- a/test/Transforms/ScalarRepl/inline-vector.ll
+++ b/test/Transforms/ScalarRepl/inline-vector.ll
@@ -6,7 +6,7 @@ target triple = "thumbv7-apple-darwin10.0.0"
 %struct.Vector4 = type { float, float, float, float }
 @f.vector = internal constant %struct.Vector4 { float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00 }, align 16
 
-; CHECK: define void @f
+; CHECK-LABEL: define void @f(
 ; CHECK-NOT: alloca
 ; CHECK: phi <4 x float>
 
diff --git a/test/Transforms/ScalarRepl/lifetime.ll b/test/Transforms/ScalarRepl/lifetime.ll
index 3f558a1..47cb854 100644
--- a/test/Transforms/ScalarRepl/lifetime.ll
+++ b/test/Transforms/ScalarRepl/lifetime.ll
@@ -9,7 +9,7 @@ declare void @llvm.lifetime.end(i64, i8*)
 %t1 = type {i32, i32, i32}
 
 define void @test1() {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
   %A = alloca %t1
   %A1 = getelementptr %t1* %A, i32 0, i32 0
   %A2 = getelementptr %t1* %A, i32 0, i32 1
@@ -22,7 +22,7 @@ define void @test1() {
 }
 
 define void @test2() {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
   %A = alloca %t1
   %A1 = getelementptr %t1* %A, i32 0, i32 0
   %A2 = getelementptr %t1* %A, i32 0, i32 1
@@ -36,7 +36,7 @@ define void @test2() {
 }
 
 define void @test3() {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
   %A = alloca %t1
   %A1 = getelementptr %t1* %A, i32 0, i32 0
   %A2 = getelementptr %t1* %A, i32 0, i32 1
@@ -50,7 +50,7 @@ define void @test3() {
 }
 
 define void @test4() {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
   %A = alloca %t1
   %A1 = getelementptr %t1* %A, i32 0, i32 0
   %A2 = getelementptr %t1* %A, i32 0, i32 1
@@ -66,7 +66,7 @@ define void @test4() {
 %t2 = type {i32, [4 x i8], i32}
 
 define void @test5() {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
   %A = alloca %t2
 ; CHECK: alloca{{.*}}i8
 ; CHECK: alloca{{.*}}i8
@@ -97,7 +97,7 @@ define void @test5() {
 %t3 = type {[4 x i16], [4 x i8]}
 
 define void @test6() {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
   %A = alloca %t3
 ; CHECK: alloca i8
 ; CHECK: alloca i8
diff --git a/test/Transforms/ScalarRepl/memset-aggregate.ll b/test/Transforms/ScalarRepl/memset-aggregate.ll
index 95ecf17..3a5c37c 100644
--- a/test/Transforms/ScalarRepl/memset-aggregate.ll
+++ b/test/Transforms/ScalarRepl/memset-aggregate.ll
@@ -64,4 +64,4 @@ entry:
 }
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
 
-declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
\ No newline at end of file
+declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
diff --git a/test/Transforms/ScalarRepl/nonzero-first-index.ll b/test/Transforms/ScalarRepl/nonzero-first-index.ll
index 60f414b..b2e93fe 100644
--- a/test/Transforms/ScalarRepl/nonzero-first-index.ll
+++ b/test/Transforms/ScalarRepl/nonzero-first-index.ll
@@ -8,7 +8,7 @@ target triple = "i386-pc-linux-gnu"
 ; Check that a GEP with a non-zero first index does not prevent SROA as long
 ; as the resulting offset corresponds to an element in the alloca.
 define i32 @test1() {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NOT: = i160
 ; CHECK: ret i32 undef
 	%A = alloca %nested
@@ -20,7 +20,7 @@ define i32 @test1() {
 
 ; But, if the offset is out of range, then it should not be transformed.
 define i32 @test2() {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: i160
 	%A = alloca %nested
 	%B = getelementptr %nested* %A, i32 0, i32 1, i32 0
@@ -31,7 +31,7 @@ define i32 @test2() {
 
 ; Try it with a bitcast and single GEP....
 define i32 @test3() {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NOT: = i160
 ; CHECK: ret i32 undef
 	%A = alloca %nested
@@ -43,7 +43,7 @@ define i32 @test3() {
 
 ; ...and again make sure that out-of-range accesses are not transformed.
 define i32 @test4() {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: i160
 	%A = alloca %nested
 	%B = bitcast %nested* %A to i32*
diff --git a/test/Transforms/ScalarRepl/only-memcpy-uses.ll b/test/Transforms/ScalarRepl/only-memcpy-uses.ll
index cfb88bd..935c289 100644
--- a/test/Transforms/ScalarRepl/only-memcpy-uses.ll
+++ b/test/Transforms/ScalarRepl/only-memcpy-uses.ll
@@ -4,7 +4,7 @@ target triple = "x86_64-apple-darwin10.0.0"
 
 %struct.S = type { [12 x i32] }
 
-; CHECK: @bar4
+; CHECK-LABEL: @bar4(
 define void @bar4(%struct.S* byval %s) nounwind ssp {
 entry:
 ; CHECK: alloca
diff --git a/test/Transforms/ScalarRepl/phi-select.ll b/test/Transforms/ScalarRepl/phi-select.ll
index 5c21c3b..a5da2dc 100644
--- a/test/Transforms/ScalarRepl/phi-select.ll
+++ b/test/Transforms/ScalarRepl/phi-select.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-apple-darwin10.2"
 %struct.X = type { i32 }
 %PairTy = type {i32, i32}
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %a.0 = alloca i32
 ; CHECK: %b.0 = alloca i32
 define i32 @test1(i32 %x) nounwind readnone ssp {
@@ -24,7 +24,7 @@ entry:
   ret i32 %4
 }
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: %X.ld = phi i32 [ 1, %entry ], [ 2, %T ]
 ; CHECK-NEXT: ret i32 %X.ld
 define i32 @test2(i1 %c) {
@@ -43,7 +43,7 @@ F:
   ret i32 %Q
 }
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: %Q = select i1 %c, i32 1, i32 2
 ; CHECK-NEXT: ret i32 %Q
 ; rdar://8904039
@@ -63,7 +63,7 @@ define i32 @test3(i1 %c) {
 define i64 @test4(i1 %c) {
 entry:
   %A = alloca %PairTy
-  ; CHECK: @test4
+  ; CHECK-LABEL: @test4(
   ; CHECK: %A = alloca %PairTy
   %B = getelementptr %PairTy* %A, i32 0, i32 0
   store i32 1, i32* %B
@@ -94,7 +94,7 @@ entry:
   %r = load i32* %b, align 8
   ret i32 %r
   
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: store i32 123, i32* %P
 ; CHECK: ret i32 2
 }
@@ -107,7 +107,7 @@ define i32 @test6(i32 %x, i1 %c) nounwind readnone ssp {
   %p.0 = select i1 %c, i32* %b, i32* %a
   %r = load i32* %p.0, align 8
   ret i32 %r
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK-NEXT: %r = select i1 %c, i32 2, i32 1
 ; CHECK-NEXT: ret i32 %r
 }
@@ -124,7 +124,7 @@ define i32 @test7(i32 %x, i1 %c) nounwind readnone ssp {
   
   %r = load i32* %p.0, align 8
   ret i32 %r
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NOT: alloca i32
 ; CHECK: %r = select i1 %c, i32 2, i32 0
 ; CHECK: ret i32 %r
@@ -132,7 +132,7 @@ define i32 @test7(i32 %x, i1 %c) nounwind readnone ssp {
 
 ;; Promote allocs that are PHI'd together by moving the loads.
 define i32 @test8(i32 %x) nounwind readnone ssp {
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK-NOT: load i32
 ; CHECK-NOT: store i32
 ; CHECK: %p.0.ld = phi i32 [ 2, %entry ], [ 1, %T ]
diff --git a/test/Transforms/ScalarRepl/vector_promote.ll b/test/Transforms/ScalarRepl/vector_promote.ll
index 5c82ae4..8ca1ed5 100644
--- a/test/Transforms/ScalarRepl/vector_promote.ll
+++ b/test/Transforms/ScalarRepl/vector_promote.ll
@@ -14,7 +14,7 @@ entry:
 	%tmp6 = fadd <4 x float> %tmp4, %tmp4		; <<4 x float>> [#uses=1]
 	store <4 x float> %tmp6, <4 x float>* %F
 	ret void
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NOT: alloca
 ; CHECK: %tmp = load <4 x float>* %F
 ; CHECK: fadd <4 x float> %tmp, %tmp
@@ -33,7 +33,7 @@ entry:
 	%tmp6 = fadd <4 x float> %tmp4, %tmp4		; <<4 x float>> [#uses=1]
 	store <4 x float> %tmp6, <4 x float>* %F
 	ret void
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NOT: alloca
 ; CHECK: %tmp = load <4 x float>* %F
 ; CHECK: fadd <4 x float> %tmp, %tmp
@@ -50,7 +50,7 @@ entry:
 	%tmp.upgrd.4 = load float* %tmp.upgrd.3		; <float> [#uses=1]
 	store float %tmp.upgrd.4, float* %f
 	ret void
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NOT: alloca
 ; CHECK: %tmp = load <4 x float>* %F
 ; CHECK: fadd <4 x float> %tmp, %tmp
@@ -67,7 +67,7 @@ entry:
 	%tmp.upgrd.6 = load float* %G.upgrd.5		; <float> [#uses=1]
 	store float %tmp.upgrd.6, float* %f
 	ret void
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NOT: alloca
 ; CHECK: %tmp = load <4 x float>* %F
 ; CHECK: fadd <4 x float> %tmp, %tmp
@@ -81,7 +81,7 @@ define i32 @test5(float %X) {  ;; should turn into bitcast.
 	%a = bitcast float* %X1 to i32*
 	%tmp = load i32* %a
 	ret i32 %tmp
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NEXT: bitcast float %X to i32
 ; CHECK-NEXT: ret i32
 }
@@ -92,7 +92,7 @@ define i64 @test6(<2 x float> %X) {
 	%P = bitcast <2 x float>* %X_addr to i64*
 	%tmp = load i64* %P
 	ret i64 %tmp
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: bitcast <2 x float> %X to i64
 ; CHECK: ret i64
 }
@@ -107,7 +107,31 @@ entry:
   %1 = getelementptr inbounds %struct.test7* %memtmp, i64 0, i32 0, i64 5
   store i32 0, i32* %1, align 4
   ret void
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK-NOT: alloca
 ; CHECK: and i192
 }
+
+; When promoting an alloca to a 1-element vector type, instructions that
+; produce that same vector type should not be changed to insert one element
+; into a new vector. <rdar://problem/14249078>
+define <1 x i64> @test8(<1 x i64> %a) {
+entry:
+  %a.addr = alloca <1 x i64>, align 8
+  %__a = alloca <1 x i64>, align 8
+  %tmp = alloca <1 x i64>, align 8
+  store <1 x i64> %a, <1 x i64>* %a.addr, align 8
+  %0 = load <1 x i64>* %a.addr, align 8
+  store <1 x i64> %0, <1 x i64>* %__a, align 8
+  %1 = load <1 x i64>* %__a, align 8
+  %2 = bitcast <1 x i64> %1 to <8 x i8>
+  %3 = bitcast <8 x i8> %2 to <1 x i64>
+  %vshl_n = shl <1 x i64> %3, <i64 4>
+  store <1 x i64> %vshl_n, <1 x i64>* %tmp
+  %4 = load <1 x i64>* %tmp
+  ret <1 x i64> %4
+; CHECK-LABEL: @test8(
+; CHECK-NOT: alloca
+; CHECK-NOT: insertelement
+; CHECK: ret <1 x i64>
+}
diff --git a/test/Transforms/SimplifyCFG/2009-01-19-UnconditionalTrappingConstantExpr.ll b/test/Transforms/SimplifyCFG/2009-01-19-UnconditionalTrappingConstantExpr.ll
index e2765e5..740ea25 100644
--- a/test/Transforms/SimplifyCFG/2009-01-19-UnconditionalTrappingConstantExpr.ll
+++ b/test/Transforms/SimplifyCFG/2009-01-19-UnconditionalTrappingConstantExpr.ll
@@ -4,7 +4,7 @@
 
 @G = extern_weak global i32
 
-; CHECK: @test(
+; CHECK-LABEL: @test(
 ; CHECK: br i1 %tmp25
 ; CHECK: bb1:
 ; CHECK: sdiv
@@ -23,7 +23,7 @@ bb6:
 	ret i32 927
 }
 
-; CHECK: @test2(
+; CHECK-LABEL: @test2(
 ; CHECK: br i1 %tmp34
 ; CHECK: bb5:
 ; CHECK: sdiv
diff --git a/test/Transforms/SimplifyCFG/EqualPHIEdgeBlockMerge.ll b/test/Transforms/SimplifyCFG/EqualPHIEdgeBlockMerge.ll
index 912c755..b07ef97 100644
--- a/test/Transforms/SimplifyCFG/EqualPHIEdgeBlockMerge.ll
+++ b/test/Transforms/SimplifyCFG/EqualPHIEdgeBlockMerge.ll
@@ -1,8 +1,18 @@
 ; Test merging of blocks with phi nodes.
 ;
-; RUN: opt < %s -simplifycfg -S | not grep N:
+; RUN: opt < %s -simplifycfg -S > %t
+; RUN: not grep N: %t
+; RUN: not grep X: %t
+; RUN: not grep 'switch i32[^U]+%U' %t
+; RUN: not grep "^BB.tomerge" %t
+; RUN: grep "^BB.nomerge" %t | count 2
 ;
 
+; ModuleID = '<stdin>'
+declare i1 @foo()
+
+declare i1 @bar(i32)
+
 define i32 @test(i1 %a) {
 Q:
         br i1 %a, label %N, label %M
@@ -16,3 +26,231 @@ M:              ; preds = %N, %Q
         ret i32 %R
 }
 
+; Test merging of blocks with phi nodes where at least one incoming value
+; in the successor is undef.
+define i8 @testundef(i32 %u) {
+R:
+  switch i32 %u, label %U [
+    i32 0, label %S
+    i32 1, label %T
+    i32 2, label %T
+  ]
+
+S:                                            ; preds = %R
+  br label %U
+
+T:                                           ; preds = %R, %R
+  br label %U
+
+U:                                        ; preds = %T, %S, %R
+  ; We should be able to merge either the S or T block into U by rewriting
+  ; R's incoming value with the incoming value of that predecessor since
+  ; R's incoming value is undef and both of those predecessors are simple
+  ; unconditional branches.
+  %val.0 = phi i8 [ undef, %R ], [ 1, %T ], [ 0, %S ]
+  ret i8 %val.0
+}
+
+; Test merging of blocks with phi nodes where at least one incoming value
+; in the successor is undef.
+define i8 @testundef2(i32 %u, i32* %A) {
+V:
+  switch i32 %u, label %U [
+    i32 0, label %W
+    i32 1, label %X
+    i32 2, label %X
+    i32 3, label %Z
+  ]
+
+W:                                            ; preds = %V
+  br label %U
+
+Z:
+  store i32 0, i32* %A, align 4
+  br label %X
+
+X:                                           ; preds = %V, %V, %Z
+  br label %U
+
+U:                                        ; preds = %X, %W, %V
+  ; We should be able to merge either the W or X block into U by rewriting
+  ; V's incoming value with the incoming value of that predecessor since
+  ; V's incoming value is undef and both of those predecessors are simple
+  ; unconditional branches. Note that X has predecessors beyond
+  ; the direct predecessors of U.
+  %val.0 = phi i8 [ undef, %V ], [ 1, %X ], [ 1, %W ]
+  ret i8 %val.0
+}
+
+define i8 @testmergesome(i32 %u, i32* %A) {
+V:
+  switch i32 %u, label %Y [
+    i32 0, label %W
+    i32 1, label %X
+    i32 2, label %X
+    i32 3, label %Z
+  ]
+
+W:                                            ; preds = %V
+  store i32 1, i32* %A, align 4
+  br label %Y
+
+Z:
+  store i32 0, i32* %A, align 4
+  br label %X
+
+X:                                           ; preds = %V, %Z
+  br label %Y
+
+Y:                                        ; preds = %X, %W, %V
+  ; After merging X into Y, we should have 5 predecessors
+  ; and thus 5 incoming values to the phi.
+  %val.0 = phi i8 [ 1, %V ], [ 1, %X ], [ 2, %W ]
+  ret i8 %val.0
+}
+
+
+define i8 @testmergesome2(i32 %u, i32* %A) {
+V:
+  switch i32 %u, label %W [
+    i32 0, label %W
+    i32 1, label %Y
+    i32 2, label %X
+    i32 4, label %Y
+  ]
+
+W:                                            ; preds = %V
+  store i32 1, i32* %A, align 4
+  br label %Y
+
+X:                                           ; preds = %V, %Z
+  br label %Y
+
+Y:                                        ; preds = %X, %W, %V
+  ; Ensure that we deal with both undef inputs for V when we merge in X.
+  %val.0 = phi i8 [ undef, %V ], [ 1, %X ], [ 2, %W ], [ undef, %V ]
+  ret i8 %val.0
+}
+
+; This function can't be merged
+define void @a() {
+entry:
+	br label %BB.nomerge
+
+BB.nomerge:		; preds = %Common, %entry
+        ; This phi has a conflicting value (0) with below phi (2), so blocks
+        ; can't be merged.
+	%a = phi i32 [ 1, %entry ], [ 0, %Common ]		; <i32> [#uses=1]
+	br label %Succ
+
+Succ:		; preds = %Common, %BB.nomerge
+	%b = phi i32 [ %a, %BB.nomerge ], [ 2, %Common ]		; <i32> [#uses=0]
+	%conde = call i1 @foo( )		; <i1> [#uses=1]
+	br i1 %conde, label %Common, label %Exit
+
+Common:		; preds = %Succ
+	%cond = call i1 @foo( )		; <i1> [#uses=1]
+	br i1 %cond, label %BB.nomerge, label %Succ
+
+Exit:		; preds = %Succ
+	ret void
+}
+
+; This function can't be merged
+define void @b() {
+entry:
+	br label %BB.nomerge
+
+BB.nomerge:		; preds = %Common, %entry
+	br label %Succ
+
+Succ:		; preds = %Common, %BB.nomerge
+        ; This phi has confliction values for Common and (through BB) Common,
+        ; blocks can't be merged
+	%b = phi i32 [ 1, %BB.nomerge ], [ 2, %Common ]		; <i32> [#uses=0]
+	%conde = call i1 @foo( )		; <i1> [#uses=1]
+	br i1 %conde, label %Common, label %Exit
+
+Common:		; preds = %Succ
+	%cond = call i1 @foo( )		; <i1> [#uses=1]
+	br i1 %cond, label %BB.nomerge, label %Succ
+
+Exit:		; preds = %Succ
+	ret void
+}
+
+; This function can be merged
+define void @c() {
+entry:
+	br label %BB.tomerge
+
+BB.tomerge:		; preds = %Common, %entry
+	br label %Succ
+
+Succ:		; preds = %Common, %BB.tomerge, %Pre-Exit
+        ; This phi has identical values for Common and (through BB) Common,
+        ; blocks can't be merged
+	%b = phi i32 [ 1, %BB.tomerge ], [ 1, %Common ], [ 2, %Pre-Exit ]
+	%conde = call i1 @foo( )		; <i1> [#uses=1]
+	br i1 %conde, label %Common, label %Pre-Exit
+
+Common:		; preds = %Succ
+	%cond = call i1 @foo( )		; <i1> [#uses=1]
+	br i1 %cond, label %BB.tomerge, label %Succ
+
+Pre-Exit:       ; preds = %Succ
+        ; This adds a backedge, so the %b phi node gets a third branch and is
+        ; not completely trivial
+	%cond2 = call i1 @foo( )		; <i1> [#uses=1]
+	br i1 %cond2, label %Succ, label %Exit
+
+Exit:		; preds = %Pre-Exit
+	ret void
+}
+
+; This function can be merged
+define void @d() {
+entry:
+	br label %BB.tomerge
+
+BB.tomerge:		; preds = %Common, %entry
+        ; This phi has a matching value (0) with below phi (0), so blocks
+        ; can be merged.
+	%a = phi i32 [ 1, %entry ], [ 0, %Common ]		; <i32> [#uses=1]
+	br label %Succ
+
+Succ:		; preds = %Common, %BB.tomerge
+	%b = phi i32 [ %a, %BB.tomerge ], [ 0, %Common ]		; <i32> [#uses=0]
+	%conde = call i1 @foo( )		; <i1> [#uses=1]
+	br i1 %conde, label %Common, label %Exit
+
+Common:		; preds = %Succ
+	%cond = call i1 @foo( )		; <i1> [#uses=1]
+	br i1 %cond, label %BB.tomerge, label %Succ
+
+Exit:		; preds = %Succ
+	ret void
+}
+
+; This function can be merged
+define void @e() {
+entry:
+	br label %BB.tomerge
+
+BB.tomerge:		; preds = %Use, %entry
+        ; This phi is used somewhere else than Succ, but this should not prevent
+        ; merging this block
+	%a = phi i32 [ 1, %entry ], [ 0, %Use ]		; <i32> [#uses=1]
+	br label %Succ
+
+Succ:		; preds = %BB.tomerge
+	%conde = call i1 @foo( )		; <i1> [#uses=1]
+	br i1 %conde, label %Use, label %Exit
+
+Use:		; preds = %Succ
+	%cond = call i1 @bar( i32 %a )		; <i1> [#uses=1]
+	br i1 %cond, label %BB.tomerge, label %Exit
+
+Exit:		; preds = %Use, %Succ
+	ret void
+}
diff --git a/test/Transforms/SimplifyCFG/R600/lit.local.cfg b/test/Transforms/SimplifyCFG/R600/lit.local.cfg
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/test/Transforms/SimplifyCFG/R600/lit.local.cfg
diff --git a/test/Transforms/SimplifyCFG/R600/parallelandifcollapse.ll b/test/Transforms/SimplifyCFG/R600/parallelandifcollapse.ll
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/test/Transforms/SimplifyCFG/R600/parallelandifcollapse.ll
diff --git a/test/Transforms/SimplifyCFG/R600/parallelorifcollapse.ll b/test/Transforms/SimplifyCFG/R600/parallelorifcollapse.ll
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/test/Transforms/SimplifyCFG/R600/parallelorifcollapse.ll
diff --git a/test/Transforms/SimplifyCFG/SPARC/switch_to_lookup_table.ll b/test/Transforms/SimplifyCFG/SPARC/switch_to_lookup_table.ll
index 9d15685..bb48c80 100644
--- a/test/Transforms/SimplifyCFG/SPARC/switch_to_lookup_table.ll
+++ b/test/Transforms/SimplifyCFG/SPARC/switch_to_lookup_table.ll
@@ -26,7 +26,7 @@ return:
   %retval.0 = phi i32 [ 15, %sw.default ], [ 1, %sw.bb6 ], [ 62, %sw.bb5 ], [ 27, %sw.bb4 ], [ -1, %sw.bb3 ], [ 0, %sw.bb2 ], [ 123, %sw.bb1 ], [ 55, %entry ]
   ret i32 %retval.0
 
-; CHECK: @f
+; CHECK-LABEL: @f(
 ; CHECK-NOT: getelementptr
 ; CHECK: switch i32 %c
 }
diff --git a/test/Transforms/SimplifyCFG/SpeculativeExec.ll b/test/Transforms/SimplifyCFG/SpeculativeExec.ll
index dd2e5d1..83fa419 100644
--- a/test/Transforms/SimplifyCFG/SpeculativeExec.ll
+++ b/test/Transforms/SimplifyCFG/SpeculativeExec.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @test1(i32 %a, i32 %b, i32 %c) nounwind  {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 entry:
         %tmp1 = icmp eq i32 %b, 0
         br i1 %tmp1, label %bb1, label %bb3
@@ -31,7 +31,7 @@ bb3:		; preds = %bb2, %entry
 declare i8 @llvm.cttz.i8(i8, i1)
 
 define i8 @test2(i8 %a) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
   br i1 undef, label %bb_true, label %bb_false
 bb_true:
   %b = tail call i8 @llvm.cttz.i8(i8 %a, i1 false)
@@ -47,7 +47,7 @@ join:
 define i8* @test4(i1* %dummy, i8* %a, i8* %b) {
 ; Test that we don't speculate an arbitrarily large number of unfolded constant
 ; expressions.
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 
 entry:
   %cond1 = load volatile i1* %dummy
diff --git a/test/Transforms/SimplifyCFG/UnreachableEliminate.ll b/test/Transforms/SimplifyCFG/UnreachableEliminate.ll
index 4a692f3..e1635f4 100644
--- a/test/Transforms/SimplifyCFG/UnreachableEliminate.ll
+++ b/test/Transforms/SimplifyCFG/UnreachableEliminate.ll
@@ -1,7 +1,7 @@
 ; RUN: opt < %s -simplifycfg -S | FileCheck %s
 
 define void @test1(i1 %C, i1* %BP) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: entry:
 ; CHECK-NEXT: ret void
 entry:
@@ -14,7 +14,7 @@ F:
 }
 
 define void @test2() {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: entry:
 ; CHECK-NEXT: call void @test2()
 ; CHECK-NEXT: ret void
@@ -28,7 +28,7 @@ N:
 }
 
 define i32 @test3(i32 %v) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: entry:
 ; CHECK-NEXT: [[CMP:%[A-Za-z0-9]+]] = icmp eq i32 %v, 2
 ; CHECK-NEXT: select i1 [[CMP]], i32 2, i32 1
diff --git a/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll b/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
index 5f70465..71259c9 100644
--- a/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
+++ b/test/Transforms/SimplifyCFG/X86/switch_to_lookup_table.ll
@@ -52,7 +52,7 @@ return:
   %retval.0 = phi i32 [ 15, %sw.default ], [ 1, %sw.bb6 ], [ 62, %sw.bb5 ], [ 27, %sw.bb4 ], [ -1, %sw.bb3 ], [ 0, %sw.bb2 ], [ 123, %sw.bb1 ], [ 55, %entry ]
   ret i32 %retval.0
 
-; CHECK: @f
+; CHECK-LABEL: @f(
 ; CHECK: entry:
 ; CHECK-NEXT: %switch.tableidx = sub i32 %c, 42
 ; CHECK-NEXT: %0 = icmp ult i32 %switch.tableidx, 7
@@ -88,7 +88,7 @@ sw.epilog:
   call void @dummy(i8 signext %a.0, float %b.0)
   ret void
 
-; CHECK: @h
+; CHECK-LABEL: @h(
 ; CHECK: entry:
 ; CHECK-NEXT: %switch.tableidx = sub i32 %x, 0
 ; CHECK-NEXT: %0 = icmp ult i32 %switch.tableidx, 4
@@ -138,7 +138,7 @@ return:
                       [ getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), %entry ]
   ret i8* %retval.0
 
-; CHECK: @foostring
+; CHECK-LABEL: @foostring(
 ; CHECK: entry:
 ; CHECK-NEXT: %switch.tableidx = sub i32 %x, 0
 ; CHECK-NEXT: %0 = icmp ult i32 %switch.tableidx, 4
@@ -171,7 +171,7 @@ sw.epilog:
   %b.0 = phi i32 [ 10, %sw.default ], [ 5, %sw.bb3 ], [ 1, %sw.bb2 ], [ 4, %sw.bb1 ], [ 3, %entry ]
   ret i32 %a.0
 
-; CHECK: @earlyreturncrash
+; CHECK-LABEL: @earlyreturncrash(
 ; CHECK: switch.lookup:
 ; CHECK-NEXT: %switch.gep = getelementptr inbounds [4 x i32]* @switch.table3, i32 0, i32 %switch.tableidx
 ; CHECK-NEXT: %switch.load = load i32* %switch.gep
@@ -221,7 +221,7 @@ lor.end:
   %lor.ext = zext i1 %0 to i32
   ret i32 %lor.ext
 
-; CHECK: @crud
+; CHECK-LABEL: @crud(
 ; CHECK: entry:
 ; CHECK-NEXT: %cmp = icmp ult i8 %c, 33
 ; CHECK-NEXT: br i1 %cmp, label %lor.end, label %switch.early.test
@@ -263,7 +263,7 @@ if.else: br label %if.end
 if.end:
   %dirent_type.0 = phi i32 [ 3, %sw.default ], [ 6, %sw.bb3 ], [ 5, %sw.bb2 ], [ 0, %sw.bb1 ], [ 3, %sw.bb ], [ 0, %if.else ]
   ret i32 %dirent_type.0
-; CHECK: define i32 @overflow
+; CHECK-LABEL: define i32 @overflow(
 ; CHECK: switch
 ; CHECK: phi
 }
@@ -284,7 +284,7 @@ bb2: br label %bb3
 bb3:
   %tmp4 = phi i1 [ undef, %bb ], [ false, %bb2 ], [ true, %bb1 ]
   ret i1 %tmp4
-; CHECK: define i1 @undef
+; CHECK-LABEL: define i1 @undef(
 ; CHECK: %switch.cast = trunc i32 %switch.tableidx to i9
 ; CHECK: %switch.downshift = lshr i9 3, %switch.shiftamt
 }
@@ -744,7 +744,7 @@ return:
   %retval.0 = phi i32 [ 123, %sw.default ], [ %sext, %sw.bb3 ], [ %sub, %sw.bb2 ], [ 42, %sw.bb1 ], [ 5, %entry ]
   ret i32 %retval.0
 
-; CHECK: @cprop
+; CHECK-LABEL: @cprop(
 ; CHECK: switch.lookup:
 ; CHECK: %switch.gep = getelementptr inbounds [7 x i32]* @switch.table5, i32 0, i32 %switch.tableidx
 }
@@ -773,7 +773,7 @@ return:
   %retval.0 = phi i32 [ 1, %sw.bb3 ], [ -1, %sw.bb2 ], [ 0, %sw.bb ]
   ret i32 %retval.0
 
-; CHECK: @unreachable
+; CHECK-LABEL: @unreachable(
 ; CHECK: switch.lookup:
 ; CHECK: getelementptr inbounds [5 x i32]* @switch.table6, i32 0, i32 %switch.tableidx
 }
@@ -799,7 +799,7 @@ return:
   %retval.0 = phi i96 [ 15, %sw.default ], [ 27, %sw.bb4 ], [ -1, %sw.bb3 ], [ 0, %sw.bb2 ], [ 123, %sw.bb1 ], [ 55, %entry ]
   ret i96 %retval.0
 
-; CHECK: @illegaltype
+; CHECK-LABEL: @illegaltype(
 ; CHECK-NOT: @switch.table
 ; CHECK: switch i32 %c
 }
diff --git a/test/Transforms/SimplifyCFG/basictest.ll b/test/Transforms/SimplifyCFG/basictest.ll
index 052e106..9c4edd6 100644
--- a/test/Transforms/SimplifyCFG/basictest.ll
+++ b/test/Transforms/SimplifyCFG/basictest.ll
@@ -5,14 +5,14 @@
 define void @test1() {
         br label %1
         ret void
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: ret void
 }
 
 define void @test2() {
         ret void
         ret void
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK-NEXT: ret void
 ; CHECK-NEXT: }
 }
@@ -20,7 +20,7 @@ define void @test2() {
 define void @test3(i1 %T) {
         br i1 %T, label %1, label %1
         ret void
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NEXT: ret void
 }
 
@@ -38,6 +38,6 @@ define void @test5(i32 %A) {
 
 return:                                           ; preds = %entry
   ret void
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK-NEXT: ret void
 }
diff --git a/test/Transforms/SimplifyCFG/branch-fold-dbg.ll b/test/Transforms/SimplifyCFG/branch-fold-dbg.ll
index 0526883..7fc0cbd 100644
--- a/test/Transforms/SimplifyCFG/branch-fold-dbg.ll
+++ b/test/Transforms/SimplifyCFG/branch-fold-dbg.ll
@@ -41,18 +41,19 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.sp = !{!0}
 
-!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 231, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (i32)* @foo, null} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 589865, metadata !"a.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"a.i", metadata !"/private/tmp", metadata !"clang (trunk 129006)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 589870, metadata !15, metadata !1, metadata !"foo", metadata !"foo", metadata !"", i32 231, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (i32)* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 589865, metadata !15} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 589841, metadata !15, i32 12, metadata !"clang (trunk 129006)", i1 true, metadata !"", i32 0, metadata !4, metadata !4, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 589845, metadata !15, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{null}
 !5 = metadata !{i32 131, i32 2, metadata !0, null}
 !6 = metadata !{i32 134, i32 2, metadata !0, null}
 !7 = metadata !{i32 590080, metadata !8, metadata !"bar", metadata !1, i32 232, metadata !9, i32 0} ; [ DW_TAG_auto_variable ]
-!8 = metadata !{i32 589835, metadata !0, i32 231, i32 1, metadata !1, i32 3} ; [ DW_TAG_lexical_block ]
-!9 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ]
-!10 = metadata !{i32 589862, metadata !2, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !11} ; [ DW_TAG_const_type ]
-!11 = metadata !{i32 589860, metadata !2, metadata !"unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!8 = metadata !{i32 589835, metadata !15, metadata !0, i32 231, i32 1, i32 3} ; [ DW_TAG_lexical_block ]
+!9 = metadata !{i32 589839, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ]
+!10 = metadata !{i32 589862, null, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, metadata !11} ; [ DW_TAG_const_type ]
+!11 = metadata !{i32 589860, null, metadata !2, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
 !12 = metadata !{i32 232, i32 40, metadata !8, null}
 !13 = metadata !{i32 234, i32 2, metadata !8, null}
 !14 = metadata !{i32 274, i32 1, metadata !8, null}
+!15 = metadata !{metadata !"a.c", metadata !"/private/tmp"}
diff --git a/test/Transforms/SimplifyCFG/dce-cond-after-folding-terminator.ll b/test/Transforms/SimplifyCFG/dce-cond-after-folding-terminator.ll
index 3996efd..036a615 100644
--- a/test/Transforms/SimplifyCFG/dce-cond-after-folding-terminator.ll
+++ b/test/Transforms/SimplifyCFG/dce-cond-after-folding-terminator.ll
@@ -2,7 +2,7 @@
 
 define void @test_br(i32 %x) {
 entry:
-; CHECK: @test_br
+; CHECK-LABEL: @test_br(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: ret void
   %cmp = icmp eq i32 %x, 10
@@ -17,7 +17,7 @@ if.end:                                           ; preds = %if.else, %if.then
 
 define void @test_switch(i32 %x) nounwind {
 entry:
-; CHECK: @test_switch
+; CHECK-LABEL: @test_switch(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: ret void
   %rem = srem i32 %x, 3
@@ -35,7 +35,7 @@ sw.epilog:                                        ; preds = %sw.bb
 
 define void @test_indirectbr(i32 %x) {
 entry:
-; CHECK: @test_indirectbr
+; CHECK-LABEL: @test_indirectbr(
 ; CHECK-NEXT: entry:
 ; Ideally this should now check:
 ;   CHK-NEXT: ret void
diff --git a/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll b/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll
index 03053f0..0e36066 100644
--- a/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll
+++ b/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll
@@ -31,23 +31,24 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
 !llvm.dbg.sp = !{!0}
 
-!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32)* @foo} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 589865, metadata !"b.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"b.c", metadata !"/private/tmp", metadata !"clang", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 589870, metadata !20, metadata !1, metadata !"foo", metadata !"foo", metadata !"", i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32)* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 589865, metadata !20} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 589841, metadata !20, i32 12, metadata !"clang", i1 true, metadata !"", i32 0, metadata !8, metadata !8, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 589845, metadata !20, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 589860, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !6 = metadata !{i32 590081, metadata !0, metadata !"i", metadata !1, i32 16777218, metadata !5, i32 0} ; [ DW_TAG_arg_variable ]
 !7 = metadata !{i32 2, i32 13, metadata !0, null}
 !8 = metadata !{i32 0}
 !9 = metadata !{i32 590080, metadata !10, metadata !"k", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ]
-!10 = metadata !{i32 589835, metadata !0, i32 2, i32 16, metadata !1, i32 0} ; [ DW_TAG_lexical_block ]
+!10 = metadata !{i32 589835, metadata !20, metadata !0, i32 2, i32 16, i32 0} ; [ DW_TAG_lexical_block ]
 !11 = metadata !{i32 3, i32 12, metadata !10, null}
 !12 = metadata !{i32 4, i32 3, metadata !10, null}
 !13 = metadata !{i32 5, i32 5, metadata !14, null}
-!14 = metadata !{i32 589835, metadata !10, i32 4, i32 10, metadata !1, i32 1} ; [ DW_TAG_lexical_block ]
+!14 = metadata !{i32 589835, metadata !20, metadata !10, i32 4, i32 10, i32 1} ; [ DW_TAG_lexical_block ]
 !15 = metadata !{i32 6, i32 3, metadata !14, null}
 !16 = metadata !{i32 7, i32 5, metadata !17, null}
-!17 = metadata !{i32 589835, metadata !10, i32 6, i32 10, metadata !1, i32 2} ; [ DW_TAG_lexical_block ]
+!17 = metadata !{i32 589835, metadata !20, metadata !10, i32 6, i32 10, i32 2} ; [ DW_TAG_lexical_block ]
 !18 = metadata !{i32 8, i32 3, metadata !17, null}
 !19 = metadata !{i32 9, i32 3, metadata !10, null}
+!20 = metadata !{metadata !"b.c", metadata !"/private/tmp"}
diff --git a/test/Transforms/SimplifyCFG/indirectbr.ll b/test/Transforms/SimplifyCFG/indirectbr.ll
index 7853e9a..d0020d0 100644
--- a/test/Transforms/SimplifyCFG/indirectbr.ll
+++ b/test/Transforms/SimplifyCFG/indirectbr.ll
@@ -77,7 +77,7 @@ BB0:
 ; SimplifyCFG should turn the indirectbr into a conditional branch on the
 ; condition of the select.
 
-; CHECK: @indbrtest3
+; CHECK-LABEL: @indbrtest3(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: br i1 %cond, label %L1, label %L2
 ; CHECK-NOT: indirectbr
@@ -104,7 +104,7 @@ L3:
 ; As in @indbrtest1, it should really remove the branch entirely, but it doesn't
 ; because it's in the entry block.
 
-; CHECK: @indbrtest4
+; CHECK-LABEL: @indbrtest4(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: br label %L1
 define void @indbrtest4(i1 %cond) nounwind {
@@ -126,7 +126,7 @@ L3:
 ; SimplifyCFG should turn the indirectbr into an unreachable because neither
 ; destination is listed as a successor.
 
-; CHECK: @indbrtest5
+; CHECK-LABEL: @indbrtest5(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: unreachable
 ; CHECK-NEXT: }
@@ -156,7 +156,7 @@ L4:
 
 ; The same as above, except the selected addresses are equal.
 
-; CHECK: @indbrtest6
+; CHECK-LABEL: @indbrtest6(
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: unreachable
 ; CHECK-NEXT: }
diff --git a/test/Transforms/SimplifyCFG/invoke.ll b/test/Transforms/SimplifyCFG/invoke.ll
index 10dc41b..5f513ac 100644
--- a/test/Transforms/SimplifyCFG/invoke.ll
+++ b/test/Transforms/SimplifyCFG/invoke.ll
@@ -9,7 +9,7 @@ declare i32 @nounwind_fn() nounwind
 declare i32 @fn()
 
 
-; CHECK: @f1
+; CHECK-LABEL: @f1(
 define i8* @f1() nounwind uwtable ssp {
 entry:
 ; CHECK: call void @llvm.trap()
@@ -28,7 +28,7 @@ lpad:
   unreachable
 }
 
-; CHECK: @f2
+; CHECK-LABEL: @f2(
 define i8* @f2() nounwind uwtable ssp {
 entry:
 ; CHECK: call void @llvm.trap()
@@ -47,7 +47,7 @@ lpad:
   unreachable
 }
 
-; CHECK: @f3
+; CHECK-LABEL: @f3(
 define i32 @f3() nounwind uwtable ssp {
 ; CHECK-NEXT: entry
 entry:
@@ -66,7 +66,7 @@ lpad:
   unreachable
 }
 
-; CHECK: @f4
+; CHECK-LABEL: @f4(
 define i32 @f4() nounwind uwtable ssp {
 ; CHECK-NEXT: entry
 entry:
@@ -86,7 +86,7 @@ lpad:
   unreachable
 }
 
-; CHECK: @f5
+; CHECK-LABEL: @f5(
 define i32 @f5(i1 %cond, i8* %a, i8* %b) {
 entry:
   br i1 %cond, label %x, label %y
@@ -117,7 +117,7 @@ lpad:
   unreachable
 }
 
-; CHECK: @f6
+; CHECK-LABEL: @f6(
 define void @f6() {
 entry:
   invoke void @purefn()
diff --git a/test/Transforms/SimplifyCFG/invoke_unwind.ll b/test/Transforms/SimplifyCFG/invoke_unwind.ll
index ed7ff82..435bed0 100644
--- a/test/Transforms/SimplifyCFG/invoke_unwind.ll
+++ b/test/Transforms/SimplifyCFG/invoke_unwind.ll
@@ -5,7 +5,7 @@ declare void @bar()
 ; This testcase checks to see if the simplifycfg pass is converting invoke
 ; instructions to call instructions if the handler just rethrows the exception.
 define i32 @test1() {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NEXT: call void @bar()
 ; CHECK-NEXT: ret i32 0
         invoke void @bar( )
diff --git a/test/Transforms/SimplifyCFG/lit.local.cfg b/test/Transforms/SimplifyCFG/lit.local.cfg
index 19eebc0..e69de29 100644
--- a/test/Transforms/SimplifyCFG/lit.local.cfg
+++ b/test/Transforms/SimplifyCFG/lit.local.cfg
@@ -1 +0,0 @@
-config.suffixes = ['.ll', '.c', '.cpp']
diff --git a/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll b/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll
index 028fb07..f34aec5 100644
--- a/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll
+++ b/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll
@@ -24,7 +24,7 @@ if.end7:                                          ; preds = %if.else, %if.then4,
   %tmp9 = load i32* %x.0
   ret i32 %tmp9
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: if.else:
 ; CHECK: br label %if.end7
 
@@ -52,7 +52,7 @@ if.end7:                                          ; preds = %if.else, %if.then4,
   %x.0 = phi i32* [ %a, %if.then ], [ null, %if.then4 ], [ null, %if.else ]
   %tmp9 = load i32* %x.0
   ret i32 %tmp9
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: if.else:
 ; CHECK: unreachable
 
@@ -81,7 +81,7 @@ if.end7:                                          ; preds = %if.else, %if.then4,
   tail call void @bar() nounwind
   %tmp9 = load i32* %x.0
   ret i32 %tmp9
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: if.end7:
 ; CHECK: phi i32* [ %a, %if.then ], [ null, %if.then4 ], [ null, %if.else ]
 }
@@ -110,6 +110,6 @@ if.end7:                                          ; preds = %if.else, %if.then4,
   %tmp10 = or i32 %tmp9, 1
   store i32 %tmp10, i32* %gep
   ret i32 %tmp9
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NOT: phi
 }
diff --git a/test/Transforms/SimplifyCFG/preserve-branchweights-partial.ll b/test/Transforms/SimplifyCFG/preserve-branchweights-partial.ll
index 53d5448..8cc07e3 100644
--- a/test/Transforms/SimplifyCFG/preserve-branchweights-partial.ll
+++ b/test/Transforms/SimplifyCFG/preserve-branchweights-partial.ll
@@ -13,7 +13,7 @@
 declare void @foo() nounwind uwtable
 
 define void @func(i32 %A) nounwind uwtable {
-; CHECK: define void @func
+; CHECK-LABEL: define void @func(
 entry:
   %cmp11 = icmp eq i32 %A, 1
   br i1 %cmp11, label %if.then, label %if.else, !prof !0
diff --git a/test/Transforms/SimplifyCFG/preserve-branchweights.ll b/test/Transforms/SimplifyCFG/preserve-branchweights.ll
index beef527..4022ed6 100644
--- a/test/Transforms/SimplifyCFG/preserve-branchweights.ll
+++ b/test/Transforms/SimplifyCFG/preserve-branchweights.ll
@@ -3,7 +3,7 @@
 declare void @helper(i32)
 
 define void @test1(i1 %a, i1 %b) {
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 entry:
   br i1 %a, label %Y, label %X, !prof !0
 ; CHECK: br i1 %or.cond, label %Z, label %Y, !prof !0
@@ -22,7 +22,7 @@ Z:
 }
 
 define void @test2(i1 %a, i1 %b) {
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 entry:
   br i1 %a, label %X, label %Y, !prof !1
 ; CHECK: br i1 %or.cond, label %Z, label %Y, !prof !1
@@ -42,7 +42,7 @@ Z:
 }
 
 define void @test3(i1 %a, i1 %b) {
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK-NOT: !prof
 entry:
   br i1 %a, label %X, label %Y, !prof !1
@@ -61,7 +61,7 @@ Z:
 }
 
 define void @test4(i1 %a, i1 %b) {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK-NOT: !prof
 entry:
   br i1 %a, label %X, label %Y
@@ -156,7 +156,7 @@ sw.epilog:
 
 ;; This test is based on test1 but swapped the targets of the second branch.
 define void @test1_swap(i1 %a, i1 %b) {
-; CHECK: @test1_swap
+; CHECK-LABEL: @test1_swap(
 entry:
   br i1 %a, label %Y, label %X, !prof !0
 ; CHECK: br i1 %or.cond, label %Y, label %Z, !prof !4
@@ -175,7 +175,7 @@ Z:
 }
 
 define void @test7(i1 %a, i1 %b) {
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 entry:
   %c = or i1 %b, false
   br i1 %a, label %Y, label %X, !prof !0
@@ -195,7 +195,7 @@ Z:
 
 ; Test basic folding to a conditional branch.
 define void @test8(i64 %x, i64 %y) nounwind {
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 entry:
     %lt = icmp slt i64 %x, %y
 ; CHECK: br i1 %lt, label %a, label %b, !prof !6
@@ -219,7 +219,7 @@ bees:
 ; Test edge splitting when the default target has icmp and unconditinal
 ; branch
 define i1 @test9(i32 %x, i32 %y) nounwind {
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 entry:
     switch i32 %x, label %bees [
         i32 0, label %a
diff --git a/test/Transforms/SimplifyCFG/select-gep.ll b/test/Transforms/SimplifyCFG/select-gep.ll
index 3e2a623..96c214c 100644
--- a/test/Transforms/SimplifyCFG/select-gep.ll
+++ b/test/Transforms/SimplifyCFG/select-gep.ll
@@ -14,7 +14,7 @@ if.end:
   %x.addr = phi i8* [ %incdec.ptr, %if.then ], [ %x, %entry ]
   ret i8* %x.addr
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK-NOT: select
 ; CHECK: ret i8* %x.addr
 }
@@ -34,7 +34,7 @@ if.end:
   %x.addr = phi i8* [ %incdec.ptr, %if.then ], [ %y, %entry ]
   ret i8* %x.addr
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: %incdec.ptr.y = select i1 %cmp, i8* %incdec.ptr, i8* %y
 ; CHECK: ret i8* %incdec.ptr.y
 }
diff --git a/test/Transforms/SimplifyCFG/speculate-store.ll b/test/Transforms/SimplifyCFG/speculate-store.ll
index 8d7fe79..e241901 100644
--- a/test/Transforms/SimplifyCFG/speculate-store.ll
+++ b/test/Transforms/SimplifyCFG/speculate-store.ll
@@ -17,7 +17,7 @@ entry:
 
 ; Make sure we speculate stores like the following one. It is cheap compared to
 ; a mispredicated branch.
-; CHECK: @ifconvertstore
+; CHECK-LABEL: @ifconvertstore(
 ; CHECK: %add5.add = select i1 %cmp6, i32 %add5, i32 %add
 ; CHECK: store i32 %add5.add, i32* %arrayidx2, align 4
 if.then:
@@ -43,7 +43,7 @@ entry:
   %cmp6 = icmp sgt i32 %add5, %C
   br i1 %cmp6, label %if.then, label %ret.end
 
-; CHECK: @noifconvertstore1
+; CHECK-LABEL: @noifconvertstore1(
 ; CHECK-NOT: select
 if.then:
   store i32 %add5, i32* %arrayidx2, align 4
@@ -71,7 +71,7 @@ entry:
   %cmp6 = icmp sgt i32 %add5, %C
   br i1 %cmp6, label %if.then, label %ret.end
 
-; CHECK: @noifconvertstore2
+; CHECK-LABEL: @noifconvertstore2(
 ; CHECK-NOT: select
 if.then:
   store i32 %add5, i32* %arrayidx2, align 4
@@ -97,7 +97,7 @@ entry:
   br i1 %cmp6, label %if.then, label %ret.end
 
 ; Make sure we don't speculate volatile stores.
-; CHECK: @noifconvertstore_volatile
+; CHECK-LABEL: @noifconvertstore_volatile(
 ; CHECK-NOT: select
 if.then:
   store volatile i32 %add5, i32* %arrayidx2, align 4
diff --git a/test/Transforms/SimplifyCFG/speculate-with-offset.ll b/test/Transforms/SimplifyCFG/speculate-with-offset.ll
index a737d56..64fed85 100644
--- a/test/Transforms/SimplifyCFG/speculate-with-offset.ll
+++ b/test/Transforms/SimplifyCFG/speculate-with-offset.ll
@@ -3,7 +3,7 @@
 ; This load is safe to speculate, as it's from a safe offset
 ; within an alloca.
 
-; CHECK: @yes
+; CHECK-LABEL: @yes(
 ; CHECK-NOT: br
 
 define void @yes(i1 %c) nounwind {
@@ -25,7 +25,7 @@ return:                                           ; preds = %if.end, %if.then
   ret void
 }
 
-; CHECK: @no0
+; CHECK-LABEL: @no0(
 ; CHECK: br i1 %c
 
 define void @no0(i1 %c) nounwind {
@@ -47,7 +47,7 @@ return:                                           ; preds = %if.end, %if.then
   ret void
 }
 
-; CHECK: @no1
+; CHECK-LABEL: @no1(
 ; CHECK: br i1 %c
 
 define void @no1(i1 %c, i64 %n) nounwind {
@@ -69,7 +69,7 @@ return:                                           ; preds = %if.end, %if.then
   ret void
 }
 
-; CHECK: @no2
+; CHECK-LABEL: @no2(
 ; CHECK: br i1 %c
 
 define void @no2(i1 %c, i64 %n) nounwind {
diff --git a/test/Transforms/SimplifyCFG/switch-masked-bits.ll b/test/Transforms/SimplifyCFG/switch-masked-bits.ll
index 3b0c48b..692973c 100644
--- a/test/Transforms/SimplifyCFG/switch-masked-bits.ll
+++ b/test/Transforms/SimplifyCFG/switch-masked-bits.ll
@@ -13,7 +13,7 @@ b:
   ret i32 3
 c:
   ret i32 5
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %cond = icmp eq i32 %i, 24
 ; CHECK: %. = select i1 %cond, i32 5, i32 0
 ; CHECK: ret i32 %.
@@ -33,6 +33,6 @@ b:
   ret i32 3
 c:
   ret i32 5
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: ret i32 0
 }
diff --git a/test/Transforms/SimplifyCFG/switch-on-const-select.ll b/test/Transforms/SimplifyCFG/switch-on-const-select.ll
index 9cd709f..dec5f80 100644
--- a/test/Transforms/SimplifyCFG/switch-on-const-select.ll
+++ b/test/Transforms/SimplifyCFG/switch-on-const-select.ll
@@ -2,7 +2,7 @@
 
 ; Test basic folding to a conditional branch.
 define i32 @foo(i64 %x, i64 %y) nounwind {
-; CHECK: @foo
+; CHECK-LABEL: @foo(
 entry:
     %eq = icmp eq i64 %x, %y
     br i1 %eq, label %b, label %switch
@@ -32,7 +32,7 @@ bees:
 
 ; Test basic folding to an unconditional branch.
 define i32 @bar(i64 %x, i64 %y) nounwind {
-; CHECK: @bar
+; CHECK-LABEL: @bar(
 entry:
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: tail call void @bees.a() [[NUW:#[0-9]+]]
@@ -58,7 +58,7 @@ bees:
 
 ; Test the edge case where both values from the select are the default case.
 define void @bazz(i64 %x, i64 %y) nounwind {
-; CHECK: @bazz
+; CHECK-LABEL: @bazz(
 entry:
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: tail call void @bees.b() [[NUW]]
@@ -83,7 +83,7 @@ bees:
 
 ; Test the edge case where both values from the select are equal.
 define void @quux(i64 %x, i64 %y) nounwind {
-; CHECK: @quux
+; CHECK-LABEL: @quux(
 entry:
 ; CHECK-NEXT: entry:
 ; CHECK-NEXT: tail call void @bees.a() [[NUW]]
@@ -108,7 +108,7 @@ bees:
 
 ; A final test, for phi node munging.
 define i32 @xyzzy(i64 %x, i64 %y) {
-; CHECK: @xyzzy
+; CHECK-LABEL: @xyzzy(
 entry:
     %eq = icmp eq i64 %x, %y
     br i1 %eq, label %r, label %cont
diff --git a/test/Transforms/SimplifyCFG/switch-to-icmp.ll b/test/Transforms/SimplifyCFG/switch-to-icmp.ll
index e9a6db4..bfacf25 100644
--- a/test/Transforms/SimplifyCFG/switch-to-icmp.ll
+++ b/test/Transforms/SimplifyCFG/switch-to-icmp.ll
@@ -15,7 +15,7 @@ lor.end:
  %0 = phi i1 [ true, %entry ], [ false, %lor.rhs ], [ true, %entry ], [ true, %entry ]
  ret i1 %0
 
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: %x.off = add i32 %x, -1
 ; CHECK: %switch = icmp ult i32 %x.off, 3
 }
@@ -34,7 +34,7 @@ lor.end:
  %0 = phi i1 [ true, %entry ], [ false, %lor.rhs ], [ true, %entry ]
  ret i1 %0
 
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: %switch = icmp ult i32 %x, 2
 }
 
@@ -51,7 +51,7 @@ good:
 bad:
  ret i32 1
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: entry:
 ; CHECK-NEXT: ret i32 0
 }
diff --git a/test/Transforms/SimplifyCFG/switch_create.ll b/test/Transforms/SimplifyCFG/switch_create.ll
index 546cc75..5500ba2 100644
--- a/test/Transforms/SimplifyCFG/switch_create.ll
+++ b/test/Transforms/SimplifyCFG/switch_create.ll
@@ -15,7 +15,7 @@ T:              ; preds = %0
 F:              ; preds = %0
         call void @foo2( )
         ret void
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK:  switch i32 %V, label %F [
 ; CHECK:    i32 17, label %T
 ; CHECK:    i32 4, label %T
@@ -33,7 +33,7 @@ T:              ; preds = %0
 F:              ; preds = %0
         call void @foo2( )
         ret void
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK:  switch i32 %V, label %T [
 ; CHECK:    i32 17, label %F
 ; CHECK:    i32 4, label %F
@@ -53,7 +53,7 @@ F:              ; preds = %N
         call void @foo2( )
         ret void
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: switch i32 %V, label %F [
 ; CHECK:     i32 4, label %T
 ; CHECK:     i32 17, label %T
@@ -80,7 +80,7 @@ lor.end:                                          ; preds = %lor.rhs, %lor.lhs.f
   %lor.ext = zext i1 %0 to i32
   ret i32 %lor.ext
   
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK:  switch i8 %c, label %lor.rhs [
 ; CHECK:    i8 62, label %lor.end
 ; CHECK:    i8 34, label %lor.end
@@ -104,7 +104,7 @@ lor.end:                                          ; preds = %entry, %entry, %ent
   %0 = phi i1 [ true, %entry ], [ %V, %lor.rhs ], [ true, %entry ], [ true, %entry ]
   %lor.ext = zext i1 %0 to i32
   ret i32 %lor.ext
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK:  switch i8 %c, label %lor.rhs [
 ; CHECK:    i8 62, label %lor.end
 ; CHECK:    i8 34, label %lor.end
@@ -140,7 +140,7 @@ UnifiedReturnBlock:             ; preds = %shortcirc_done.4, %shortcirc_next.4
         %UnifiedRetVal = phi i1 [ %tmp.26, %shortcirc_next.4 ], [ true, %shortcirc_done.4 ]             ; <i1> [#uses=1]
         ret i1 %UnifiedRetVal
         
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: %tmp.2.i.off = add i32 %tmp.2.i, -14
 ; CHECK: %switch = icmp ult i32 %tmp.2.i.off, 6
 }
@@ -161,7 +161,7 @@ if.then:                                          ; preds = %entry
 if.end:                                           ; preds = %entry
   ret void
   
-; CHECK: @test7
+; CHECK-LABEL: @test7(
 ; CHECK:   %cmp = icmp ult i32 %x, 32
 ; CHECK:   br i1 %cmp, label %if.then, label %switch.early.test
 ; CHECK: switch.early.test:
@@ -190,7 +190,7 @@ if.then:                                          ; preds = %entry
 if.end:                                           ; preds = %entry
   ret i32 0
   
-; CHECK: @test8
+; CHECK-LABEL: @test8(
 ; CHECK: switch.early.test:
 ; CHECK:   switch i8 %c, label %if.end [
 ; CHECK:     i8 99, label %if.then
@@ -246,7 +246,7 @@ lor.end:                                          ; preds = %lor.rhs, %lor.lhs.f
   %conv46 = zext i1 %0 to i32
   ret i32 %conv46
   
-; CHECK: @test9
+; CHECK-LABEL: @test9(
 ; CHECK:   %cmp = icmp ult i8 %c, 33
 ; CHECK:   br i1 %cmp, label %lor.end, label %switch.early.test
 
@@ -275,7 +275,7 @@ T:
 F:
   ret i32 324
 
-; CHECK: @test10
+; CHECK-LABEL: @test10(
 ; CHECK:  br i1 %Cond, label %switch.early.test, label %F
 ; CHECK:switch.early.test:
 ; CHECK:  switch i32 %mode, label %T [
@@ -314,7 +314,7 @@ return:                                           ; preds = %if.end, %if.then
   %retval.0 = phi i32 [ 1, %if.then ], [ 0, %if.end ]
   ret i32 %retval.0
 
-; CHECK: @test11
+; CHECK-LABEL: @test11(
 ; CHECK: switch i32 %bar, label %if.end [
 ; CHECK:   i32 55, label %return
 ; CHECK:   i32 53, label %return
@@ -343,7 +343,7 @@ bb55.us.us:
 
 malformed:
   ret void
-; CHECK: @test12
+; CHECK-LABEL: @test12(
 
 }
 
@@ -371,7 +371,7 @@ if.then:                                          ; preds = %lor.lhs.false9, %lo
 
 if.end:                                           ; preds = %if.then, %lor.lhs.false9
   ret void
-; CHECK: @test13
+; CHECK-LABEL: @test13(
 ; CHECK:  switch i32 %x, label %if.end [
 ; CHECK:     i32 6, label %if.then
 ; CHECK:     i32 4, label %if.then
@@ -405,7 +405,7 @@ if.then:                                          ; preds = %lor.lhs.false9, %lo
 
 if.end:                                           ; preds = %if.then, %lor.lhs.false9
   ret void
-; CHECK: @test14
+; CHECK-LABEL: @test14(
 ; CHECK:  switch i32 %x, label %if.end [
 ; CHECK:     i32 6, label %if.then
 ; CHECK:     i32 4, label %if.then
@@ -431,7 +431,7 @@ if.then:
 if.end:
   ret void
 
-; CHECK: @test15
+; CHECK-LABEL: @test15(
 ; CHECK-NOT: switch
 ; CHECK: ret void
 }
@@ -440,7 +440,7 @@ if.end:
 ; rdar://5134905
 define zeroext i1 @test16(i32 %x) nounwind {
 entry:
-; CHECK: @test16
+; CHECK-LABEL: @test16(
 ; CHECK: %x.off = add i32 %x, -1
 ; CHECK: %switch = icmp ult i32 %x.off, 3
   %cmp.i = icmp eq i32 %x, 1
@@ -473,9 +473,45 @@ lor.lhs.false8:
 return:
   ret void
 
-; CHECK: @test17
+; CHECK-LABEL: @test17(
 ; CHECK-NOT: switch.early.test
 ; CHECK-NOT: switch i32
 ; CHECK: ret void
 }
 
+define void @test18(i32 %arg) {
+bb:
+  %tmp = and i32 %arg, -2
+  %tmp1 = icmp eq i32 %tmp, 8
+  %tmp2 = icmp eq i32 %arg, 10
+  %tmp3 = or i1 %tmp1, %tmp2
+  %tmp4 = icmp eq i32 %arg, 11
+  %tmp5 = or i1 %tmp3, %tmp4
+  %tmp6 = icmp eq i32 %arg, 12
+  %tmp7 = or i1 %tmp5, %tmp6
+  br i1 %tmp7, label %bb19, label %bb8
+
+bb8:                                              ; preds = %bb
+  %tmp9 = add i32 %arg, -13
+  %tmp10 = icmp ult i32 %tmp9, 2
+  %tmp11 = icmp eq i32 %arg, 16
+  %tmp12 = or i1 %tmp10, %tmp11
+  %tmp13 = icmp eq i32 %arg, 17
+  %tmp14 = or i1 %tmp12, %tmp13
+  %tmp15 = icmp eq i32 %arg, 18
+  %tmp16 = or i1 %tmp14, %tmp15
+  %tmp17 = icmp eq i32 %arg, 15
+  %tmp18 = or i1 %tmp16, %tmp17
+  br i1 %tmp18, label %bb19, label %bb20
+
+bb19:                                             ; preds = %bb8, %bb
+  tail call void @foo1()
+  br label %bb20
+
+bb20:                                             ; preds = %bb19, %bb8
+  ret void
+
+; CHECK-LABEL: @test18(
+; CHECK: %arg.off = add i32 %arg, -8
+; CHECK: icmp ult i32 %arg.off, 11
+}
diff --git a/test/Transforms/SimplifyCFG/trap-debugloc.ll b/test/Transforms/SimplifyCFG/trap-debugloc.ll
index 24540e5..953557ff 100644
--- a/test/Transforms/SimplifyCFG/trap-debugloc.ll
+++ b/test/Transforms/SimplifyCFG/trap-debugloc.ll
@@ -7,13 +7,16 @@ define void @foo() nounwind ssp {
   ret void, !dbg !7
 }
 
+!llvm.dbg.cu = !{!2}
 !llvm.dbg.sp = !{!0}
 
-!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, void ()* @foo} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 589865, metadata !"foo.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"foo.c", metadata !"/private/tmp", metadata !"Apple clang version 3.0 (tags/Apple/clang-206.1) (based on LLVM 3.0svn)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 589870, metadata !8, metadata !1, metadata !"foo", metadata !"foo", metadata !"", i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, void ()* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 589865, metadata !8} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 589841, metadata !8, i32 12, metadata !"Apple clang version 3.0 (tags/Apple/clang-206.1) (based on LLVM 3.0svn)", i1 true, metadata !"", i32 0, metadata !4, metadata !4, metadata !9, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 589845, metadata !8, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{null}
 !5 = metadata !{i32 4, i32 2, metadata !6, null}
-!6 = metadata !{i32 589835, metadata !0, i32 3, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ]
+!6 = metadata !{i32 589835, metadata !8, metadata !0, i32 3, i32 12, i32 0} ; [ DW_TAG_lexical_block ]
 !7 = metadata !{i32 5, i32 1, metadata !6, null}
+!8 = metadata !{metadata !"foo.c", metadata !"/private/tmp"}
+!9 = metadata !{metadata !0}
diff --git a/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll b/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
index 10d6981..e9d93e8 100644
--- a/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
+++ b/test/Transforms/SimplifyCFG/trapping-load-unreachable.ll
@@ -17,7 +17,7 @@ bb:             ; preds = %entry
         br label %return
 return:         ; preds = %entry
         ret void
-; CHECK: @test1
+; CHECK-LABEL: @test1(
 ; CHECK: load volatile
 }
 
@@ -27,7 +27,7 @@ entry:
         store i32 4,i32* null
         ret void
         
-; CHECK: @test2
+; CHECK-LABEL: @test2(
 ; CHECK: call void @llvm.trap
 ; CHECK: unreachable
 }
@@ -38,14 +38,14 @@ entry:
         store volatile i32 4, i32* null
         ret void
 
-; CHECK: @test3
+; CHECK-LABEL: @test3(
 ; CHECK: store volatile i32 4, i32* null
 ; CHECK: ret
 }
 
 ; Check store before unreachable.
 define void @test4(i1 %C, i32* %P) {
-; CHECK: @test4
+; CHECK-LABEL: @test4(
 ; CHECK: entry:
 ; CHECK-NEXT: br i1 %C
 entry:
@@ -59,7 +59,7 @@ F:
 
 ; Check cmpxchg before unreachable.
 define void @test5(i1 %C, i32* %P) {
-; CHECK: @test5
+; CHECK-LABEL: @test5(
 ; CHECK: entry:
 ; CHECK-NEXT: br i1 %C
 entry:
@@ -73,7 +73,7 @@ F:
 
 ; Check atomicrmw before unreachable.
 define void @test6(i1 %C, i32* %P) {
-; CHECK: @test6
+; CHECK-LABEL: @test6(
 ; CHECK: entry:
 ; CHECK-NEXT: br i1 %C
 entry:
diff --git a/test/Transforms/SimplifyCFG/volatile-phioper.ll b/test/Transforms/SimplifyCFG/volatile-phioper.ll
index 1648988..1ef3a7c 100644
--- a/test/Transforms/SimplifyCFG/volatile-phioper.ll
+++ b/test/Transforms/SimplifyCFG/volatile-phioper.ll
@@ -7,7 +7,7 @@
 ; it can no longer use language standard as an excuse. The compiler
 ; needs to expose the volatile access to the platform.
 ;
-; CHECK: @test
+; CHECK-LABEL: @test(
 ; CHECK: entry:
 ; CHECK: @Trace
 ; CHECK: while.body:
@@ -41,8 +41,8 @@ end:
 }
 declare i32 @Trace(...) #1
 
-attributes #0 = { nounwind ssp uwtable "fp-contract-model"="standard" "no-frame-pointer-elim" "no-frame-pointer-elim-non-leaf" "realign-stack" "relocation-model"="pic" "ssp-buffers-size"="8" }
-attributes #1 = { "fp-contract-model"="standard" "no-frame-pointer-elim" "no-frame-pointer-elim-non-leaf" "realign-stack" "relocation-model"="pic" "ssp-buffers-size"="8" }
+attributes #0 = { nounwind ssp uwtable "fp-contract-model"="standard" "no-frame-pointer-elim" "no-frame-pointer-elim-non-leaf" "relocation-model"="pic" "ssp-buffers-size"="8" }
+attributes #1 = { "fp-contract-model"="standard" "no-frame-pointer-elim" "no-frame-pointer-elim-non-leaf" "relocation-model"="pic" "ssp-buffers-size"="8" }
 attributes #2 = { nounwind }
 
 !0 = metadata !{i32 1039}
diff --git a/test/Transforms/Sink/basic.ll b/test/Transforms/Sink/basic.ll
index 1d0b6b5..85ab376 100644
--- a/test/Transforms/Sink/basic.ll
+++ b/test/Transforms/Sink/basic.ll
@@ -6,7 +6,7 @@
 ; Sink should sink the load past the store (which doesn't overlap) into
 ; the block that uses it.
 
-;      CHECK: @foo
+;      CHECK-LABEL: @foo(
 ;      CHECK: true:
 ; CHECK-NEXT: %l = load i32* @A
 ; CHECK-NEXT: ret i32 %l
@@ -23,7 +23,7 @@ false:
 
 ; But don't sink load volatiles...
 
-;      CHECK: @foo2
+;      CHECK-LABEL: @foo2(
 ;      CHECK: load volatile
 ; CHECK-NEXT: store i32
 
@@ -39,7 +39,7 @@ false:
 
 ; Sink to the nearest post-dominator
 
-;      CHECK: @diamond
+;      CHECK-LABEL: @diamond(
 ;      CHECK: X:
 ; CHECK-NEXT: phi
 ; CHECK-NEXT: mul nsw
diff --git a/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll b/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll
index f5899d2..0181c9b 100644
--- a/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll
+++ b/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll
@@ -10,19 +10,21 @@ entry:
 
 declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
 
+!llvm.dbg.cu = !{!2}
 !llvm.dbg.sp = !{!0}
 !llvm.dbg.lv.foo = !{!5}
 !llvm.dbg.gv = !{!8}
 
-!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, void ()* @foo} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 524329, metadata !"b.c", metadata !"/tmp", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 524305, i32 0, i32 1, metadata !"b.c", metadata !"/tmp", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 524334, metadata !12, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, void ()* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 524329, metadata !12} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 524305, metadata !12, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !4, metadata !4, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 524309, metadata !12, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{null}
 !5 = metadata !{i32 524544, metadata !6, metadata !"y", metadata !1, i32 3, metadata !7} ; [ DW_TAG_auto_variable ]
-!6 = metadata !{i32 524299, metadata !0, i32 2, i32 0} ; [ DW_TAG_lexical_block ]
-!7 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 524299, metadata !12, metadata !0, i32 2, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!7 = metadata !{i32 524324, metadata !12, metadata !1, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !8 = metadata !{i32 524340, i32 0, metadata !1, metadata !"x", metadata !"x", metadata !"", metadata !1, i32 1, metadata !7, i1 false, i1 true, i32* @x} ; [ DW_TAG_variable ]
 !9 = metadata !{i32 0}
 !10 = metadata !{i32 3, i32 0, metadata !6, null}
 !11 = metadata !{i32 4, i32 0, metadata !6, null}
+!12 = metadata !{metadata !"b.c", metadata !"/tmp"}
diff --git a/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll b/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll
index 1df0351..b893410 100644
--- a/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll
+++ b/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll
@@ -18,30 +18,32 @@ entry:
   ret i32 %.0, !dbg !20
 }
 
+!llvm.dbg.cu = !{!2}
 !llvm.dbg.sp = !{!0, !5, !9}
 !llvm.dbg.lv.bar = !{!12}
 !llvm.dbg.lv.foo = !{!14}
 !llvm.dbg.gv = !{!15, !16}
 
-!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"", metadata !1, i32 5, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 true, null} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 524329, metadata !"g.c", metadata !"/tmp/", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 524305, i32 0, i32 1, metadata !"g.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 524334, metadata !22, null, metadata !"bar", metadata !"bar", metadata !"", i32 5, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 true, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 524329, metadata !22} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 524305, metadata !22, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, metadata !4, metadata !4, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 524309, metadata !22, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{null}
-!5 = metadata !{i32 524334, i32 0, metadata !1, metadata !"fn", metadata !"fn", metadata !"fn", metadata !1, i32 6, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @fn} ; [ DW_TAG_subprogram ]
-!6 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!5 = metadata !{i32 524334, metadata !22, null, metadata !"fn", metadata !"fn", metadata !"fn", i32 6, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @fn, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 524309, metadata !22, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !7 = metadata !{metadata !8}
-!8 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 7, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32)* @foo} ; [ DW_TAG_subprogram ]
-!10 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!8 = metadata !{i32 524324, metadata !22, metadata !1, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 524334, metadata !22, null, metadata !"foo", metadata !"foo", metadata !"foo", i32 7, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32)* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!10 = metadata !{i32 524309, metadata !22, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !11 = metadata !{metadata !8, metadata !8}
 !12 = metadata !{i32 524544, metadata !13, metadata !"bb", metadata !1, i32 5, metadata !8} ; [ DW_TAG_auto_variable ]
-!13 = metadata !{i32 524299, metadata !0, i32 5, i32 0} ; [ DW_TAG_lexical_block ]
+!13 = metadata !{i32 524299, metadata !22, metadata !0, i32 5, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !14 = metadata !{i32 524545, metadata !9, metadata !"i", metadata !1, i32 7, metadata !8} ; [ DW_TAG_arg_variable ]
 !15 = metadata !{i32 524340, i32 0, metadata !1, metadata !"abcd", metadata !"abcd", metadata !"", metadata !1, i32 2, metadata !8, i1 true, i1 true, null} ; [ DW_TAG_variable ]
 !16 = metadata !{i32 524340, i32 0, metadata !1, metadata !"xyz", metadata !"xyz", metadata !"", metadata !1, i32 3, metadata !8, i1 false, i1 true, i32* @xyz} ; [ DW_TAG_variable ]
 !17 = metadata !{i32 6, i32 0, metadata !18, null}
-!18 = metadata !{i32 524299, metadata !5, i32 6, i32 0} ; [ DW_TAG_lexical_block ]
+!18 = metadata !{i32 524299, metadata !22, metadata !5, i32 6, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
 !19 = metadata !{i32 7, i32 0, metadata !9, null}
 !20 = metadata !{i32 10, i32 0, metadata !21, null}
-!21 = metadata !{i32 524299, metadata !9, i32 7, i32 0} ; [ DW_TAG_lexical_block ]
+!21 = metadata !{i32 524299, metadata !22, metadata !9, i32 7, i32 0, i32 0} ; [ DW_TAG_lexical_block ]
+!22 = metadata !{metadata !"g.c", metadata !"/tmp/"}
diff --git a/test/Transforms/StripSymbols/2010-08-25-crash.ll b/test/Transforms/StripSymbols/2010-08-25-crash.ll
index 7de5a02..e480f43 100644
--- a/test/Transforms/StripSymbols/2010-08-25-crash.ll
+++ b/test/Transforms/StripSymbols/2010-08-25-crash.ll
@@ -4,16 +4,19 @@ entry:
   ret i32 0, !dbg !8
 }
 
+!llvm.dbg.cu = !{!2}
 !llvm.dbg.sp = !{!0}
 !llvm.dbg.gv = !{!6}
 
-!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @foo} ; [ DW_TAG_subprogram ]
-!1 = metadata !{i32 524329, metadata !"/tmp/a.c", metadata !"/Volumes/Lalgate/clean/D.CW", metadata !2} ; [ DW_TAG_file_type ]
-!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"/tmp/a.c", metadata !"/Volumes/Lalgate/clean/D.CW", metadata !"clang version 2.8 (trunk 112062)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!0 = metadata !{i32 524334, metadata !10, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 524329, metadata !10} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 524305, metadata !10, i32 12, metadata !"clang version 2.8 (trunk 112062)", i1 true, metadata !"", i32 0, metadata !11, metadata !11, null, null, null, metadata !""} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 524309, metadata !10, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
 !4 = metadata !{metadata !5}
-!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!5 = metadata !{i32 524324, metadata !10, metadata !1, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
 !6 = metadata !{i32 524340, i32 0, metadata !1, metadata !"i", metadata !"i", metadata !"i", metadata !1, i32 2, metadata !7, i1 true, i1 true, i32 0} ; [ DW_TAG_variable ]
-!7 = metadata !{i32 524326, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !5} ; [ DW_TAG_const_type ]
+!7 = metadata !{i32 524326, metadata !10, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, metadata !5} ; [ DW_TAG_const_type ]
 !8 = metadata !{i32 3, i32 13, metadata !9, null}
-!9 = metadata !{i32 524299, metadata !0, i32 3, i32 11, metadata !1, i32 0} ; [ DW_TAG_lexical_block ]
+!9 = metadata !{i32 524299, metadata !10, metadata !0, i32 3, i32 11, i32 0} ; [ DW_TAG_lexical_block ]
+!10 = metadata !{metadata !"/tmp/a.c", metadata !"/Volumes/Lalgate/clean/D.CW"}
+!11 = metadata !{i32 0}
diff --git a/test/Archive/lit.local.cfg b/test/Transforms/StructurizeCFG/lit.local.cfg
index 19eebc0..19eebc0 100644
--- a/test/Archive/lit.local.cfg
+++ b/test/Transforms/StructurizeCFG/lit.local.cfg
diff --git a/test/Transforms/StructurizeCFG/loop-multiple-exits.ll b/test/Transforms/StructurizeCFG/loop-multiple-exits.ll
new file mode 100644
index 0000000..45f3165
--- /dev/null
+++ b/test/Transforms/StructurizeCFG/loop-multiple-exits.ll
@@ -0,0 +1,50 @@
+; RUN: opt -S -structurizecfg %s -o - | FileCheck %s
+;
+; void loop(int *out, int cond_a, int cond_b) {
+;
+;   unsigned i;
+;   for (i = 0; i < cond_a; i++) {
+;     out[i] = i;
+;     if (i > cond_b) {
+;       break;
+;     }
+;     out[i + cond_a] = i;
+;   }
+; }
+
+define void @loop(i32 addrspace(1)* %out, i32 %cond_a, i32 %cond_b) nounwind uwtable {
+entry:
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.inc, %entry
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
+  %cmp = icmp ult i32 %i.0, %cond_a
+  br i1 %cmp, label %for.body, label %for.end
+
+; CHECK: for.body:
+for.body:                                         ; preds = %for.cond
+  %arrayidx = getelementptr inbounds i32 addrspace(1)* %out, i32 %i.0
+  store i32 %i.0, i32 addrspace(1)* %arrayidx, align 4
+  %cmp1 = icmp ugt i32 %i.0, %cond_b
+; CHECK: br i1 %{{[0-9a-zA-Z_]+}}, label %for.inc, label %[[FLOW1:[0-9a-zA-Z_]+]]
+  br i1 %cmp1, label %for.end, label %for.inc
+
+; CHECK: [[FLOW:[0-9a-zA-Z]+]]:
+; CHECK: br i1 %{{[0-9a-zA-Z_]+}}, label %for.end, label %for.cond
+
+; CHECK: for.inc:
+; CHECK: br label %[[FLOW1]]
+
+for.inc:                                          ; preds = %for.body
+  %0 = add i32 %cond_a, %i.0
+  %arrayidx3 = getelementptr inbounds i32 addrspace(1)* %out, i32 %0
+  store i32 %i.0, i32 addrspace(1)* %arrayidx3, align 4
+  %inc = add i32 %i.0, 1
+  br label %for.cond
+
+; CHECK: [[FLOW1]]
+; CHECK: br label %[[FLOW]]
+
+for.end:                                          ; preds = %for.cond, %for.body
+  ret void
+}
diff --git a/test/Transforms/TailCallElim/2010-06-26-MultipleReturnValues.ll b/test/Transforms/TailCallElim/2010-06-26-MultipleReturnValues.ll
index 0626592..053fc95 100644
--- a/test/Transforms/TailCallElim/2010-06-26-MultipleReturnValues.ll
+++ b/test/Transforms/TailCallElim/2010-06-26-MultipleReturnValues.ll
@@ -2,7 +2,7 @@
 ; PR7328
 ; PR7506
 define i32 @foo(i32 %x) {
-; CHECK: define i32 @foo
+; CHECK-LABEL: define i32 @foo(
 ; CHECK: %accumulator.tr = phi i32 [ 1, %entry ], [ 0, %body ]
 entry:
   %cond = icmp ugt i32 %x, 0                      ; <i1> [#uses=1]
diff --git a/test/Transforms/TailCallElim/accum_recursion.ll b/test/Transforms/TailCallElim/accum_recursion.ll
index 9475f87..c95bfe6 100644
--- a/test/Transforms/TailCallElim/accum_recursion.ll
+++ b/test/Transforms/TailCallElim/accum_recursion.ll
@@ -13,7 +13,7 @@ else:		; preds = %entry
 	ret i32 1
 }
 
-; CHECK: define i32 @test1_factorial
+; CHECK-LABEL: define i32 @test1_factorial(
 ; CHECK: phi i32
 ; CHECK-NOT: call i32
 ; CHECK: else:
@@ -34,14 +34,14 @@ return:		; preds = %entry
 	ret i32 %x
 }
 
-; CHECK: define i32 @test2_mul
+; CHECK-LABEL: define i32 @test2_mul(
 ; CHECK: phi i32
 ; CHECK-NOT: call i32
 ; CHECK: return:
 
 
 define i64 @test3_fib(i64 %n) nounwind readnone {
-; CHECK: @test3_fib
+; CHECK-LABEL: @test3_fib(
 entry:
 ; CHECK: tailrecurse:
 ; CHECK: %accumulator.tr = phi i64 [ %n, %entry ], [ %3, %bb1 ]
diff --git a/test/Transforms/TailCallElim/basic.ll b/test/Transforms/TailCallElim/basic.ll
new file mode 100644
index 0000000..35420ab
--- /dev/null
+++ b/test/Transforms/TailCallElim/basic.ll
@@ -0,0 +1,145 @@
+; RUN: opt < %s -tailcallelim -S | FileCheck %s
+
+declare void @noarg()
+declare void @use(i32*)
+declare void @use_nocapture(i32* nocapture)
+declare void @use2_nocapture(i32* nocapture, i32* nocapture)
+
+; Trivial case. Mark @noarg with tail call.
+define void @test0() {
+; CHECK: tail call void @noarg()
+	call void @noarg()
+	ret void
+}
+
+; PR615. Make sure that we do not move the alloca so that it interferes with the tail call.
+define i32 @test1() {
+; CHECK: i32 @test1()
+; CHECK-NEXT: alloca
+	%A = alloca i32		; <i32*> [#uses=2]
+	store i32 5, i32* %A
+	call void @use(i32* %A)
+; CHECK: tail call i32 @test1
+	%X = tail call i32 @test1()		; <i32> [#uses=1]
+	ret i32 %X
+}
+
+; This function contains intervening instructions which should be moved out of the way
+define i32 @test2(i32 %X) {
+; CHECK: i32 @test2
+; CHECK-NOT: call
+; CHECK: ret i32
+entry:
+	%tmp.1 = icmp eq i32 %X, 0		; <i1> [#uses=1]
+	br i1 %tmp.1, label %then.0, label %endif.0
+then.0:		; preds = %entry
+	%tmp.4 = add i32 %X, 1		; <i32> [#uses=1]
+	ret i32 %tmp.4
+endif.0:		; preds = %entry
+	%tmp.10 = add i32 %X, -1		; <i32> [#uses=1]
+	%tmp.8 = call i32 @test2(i32 %tmp.10)		; <i32> [#uses=1]
+	%DUMMY = add i32 %X, 1		; <i32> [#uses=0]
+	ret i32 %tmp.8
+}
+
+; Though this case seems to be fairly unlikely to occur in the wild, someone
+; plunked it into the demo script, so maybe they care about it.
+define i32 @test3(i32 %c) {
+; CHECK: i32 @test3
+; CHECK-NOT: call
+; CHECK: ret i32 0
+entry:
+	%tmp.1 = icmp eq i32 %c, 0		; <i1> [#uses=1]
+	br i1 %tmp.1, label %return, label %else
+else:		; preds = %entry
+	%tmp.5 = add i32 %c, -1		; <i32> [#uses=1]
+	%tmp.3 = call i32 @test3(i32 %tmp.5)		; <i32> [#uses=0]
+	ret i32 0
+return:		; preds = %entry
+	ret i32 0
+}
+
+; Make sure that a nocapture pointer does not stop adding a tail call marker to
+; an unrelated call and additionally that we do not mark the nocapture call with
+; a tail call.
+;
+; rdar://14324281
+define void @test4() {
+; CHECK: void @test4
+; CHECK-NOT: tail call void @use_nocapture
+; CHECK: tail call void @noarg()
+; CHECK: ret void
+  %a = alloca i32
+  call void @use_nocapture(i32* %a)
+  call void @noarg()
+  ret void
+}
+
+; Make sure that we do not perform TRE even with a nocapture use. This is due to
+; bad codegen caused by PR962.
+;
+; rdar://14324281.
+define i32* @test5(i32* nocapture %A, i1 %cond) {
+; CHECK: i32* @test5
+; CHECK-NOT: tailrecurse:
+; CHECK: ret i32* null
+  %B = alloca i32
+  br i1 %cond, label %cond_true, label %cond_false
+cond_true:
+  call i32* @test5(i32* %B, i1 false)
+  ret i32* null
+cond_false:
+  call void @use2_nocapture(i32* %A, i32* %B)
+  call void @noarg()
+  ret i32* null
+}
+
+; PR14143: Make sure that we do not mark functions with nocapture allocas with tail.
+;
+; rdar://14324281.
+define void @test6(i32* %a, i32* %b) {
+; CHECK-LABEL: @test6(
+; CHECK-NOT: tail call
+; CHECK: ret void
+  %c = alloca [100 x i8], align 16
+  %tmp = bitcast [100 x i8]* %c to i32*
+  call void @use2_nocapture(i32* %b, i32* %tmp)
+  ret void
+}
+
+; PR14143: Make sure that we do not mark functions with nocapture allocas with tail.
+;
+; rdar://14324281
+define void @test7(i32* %a, i32* %b) nounwind uwtable {
+entry:
+; CHECK-LABEL: @test7(
+; CHECK-NOT: tail call
+; CHECK: ret void
+  %c = alloca [100 x i8], align 16
+  %0 = bitcast [100 x i8]* %c to i32*
+  call void @use2_nocapture(i32* %0, i32* %a)
+  call void @use2_nocapture(i32* %b, i32* %0)
+  ret void
+}
+
+; If we have a mix of escaping captured/non-captured allocas, ensure that we do
+; not do anything including marking callsites with the tail call marker.
+;
+; rdar://14324281.
+define i32* @test8(i32* nocapture %A, i1 %cond) {
+; CHECK: i32* @test8
+; CHECK-NOT: tailrecurse:
+; CHECK-NOT: tail call
+; CHECK: ret i32* null
+  %B = alloca i32
+  %B2 = alloca i32
+  br i1 %cond, label %cond_true, label %cond_false
+cond_true:
+  call void @use(i32* %B2)
+  call i32* @test8(i32* %B, i1 false)
+  ret i32* null
+cond_false:
+  call void @use2_nocapture(i32* %A, i32* %B)
+  call void @noarg()
+  ret i32* null
+}
diff --git a/test/Transforms/TailCallElim/dont-tce-tail-marked-call.ll b/test/Transforms/TailCallElim/dont-tce-tail-marked-call.ll
deleted file mode 100644
index 97e67b2..0000000
--- a/test/Transforms/TailCallElim/dont-tce-tail-marked-call.ll
+++ /dev/null
@@ -1,13 +0,0 @@
-; RUN: opt < %s -tailcallelim -S | FileCheck %s
-
-declare void @bar(i32*)
-
-define i32 @foo(i32 %N) {
-	%A = alloca i32, i32 %N		; <i32*> [#uses=2]
-	store i32 17, i32* %A
-	call void @bar( i32* %A )
-; CHECK: tail call i32 @foo
-	%X = tail call i32 @foo( i32 %N )		; <i32> [#uses=1]
-	ret i32 %X
-}
-
diff --git a/test/Transforms/TailCallElim/inf-recursion.ll b/test/Transforms/TailCallElim/inf-recursion.ll
index c427869..157226f 100644
--- a/test/Transforms/TailCallElim/inf-recursion.ll
+++ b/test/Transforms/TailCallElim/inf-recursion.ll
@@ -14,7 +14,7 @@ entry:
 
 ; Do turn other calls into infinite loops though.
 
-; CHECK: define double @foo
+; CHECK-LABEL: define double @foo(
 ; CHECK-NOT: call
 ; CHECK: }
 define double @foo(double %f) {
@@ -22,7 +22,7 @@ define double @foo(double %f) {
         ret double %t
 }
 
-; CHECK: define float @fabsf
+; CHECK-LABEL: define float @fabsf(
 ; CHECK-NOT: call
 ; CHECK: }
 define float @fabsf(float %f) {
diff --git a/test/Transforms/TailCallElim/intervening-inst.ll b/test/Transforms/TailCallElim/intervening-inst.ll
deleted file mode 100644
index 10dffbd..0000000
--- a/test/Transforms/TailCallElim/intervening-inst.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; This function contains intervening instructions which should be moved out of the way
-; RUN: opt < %s -tailcallelim -S | FileCheck %s
-
-define i32 @Test(i32 %X) {
-entry:
-	%tmp.1 = icmp eq i32 %X, 0		; <i1> [#uses=1]
-	br i1 %tmp.1, label %then.0, label %endif.0
-then.0:		; preds = %entry
-	%tmp.4 = add i32 %X, 1		; <i32> [#uses=1]
-	ret i32 %tmp.4
-endif.0:		; preds = %entry
-	%tmp.10 = add i32 %X, -1		; <i32> [#uses=1]
-; CHECK-NOT: call
-	%tmp.8 = call i32 @Test( i32 %tmp.10 )		; <i32> [#uses=1]
-	%DUMMY = add i32 %X, 1		; <i32> [#uses=0]
-	ret i32 %tmp.8
-}
-
diff --git a/test/Transforms/TailCallElim/move_alloca_for_tail_call.ll b/test/Transforms/TailCallElim/move_alloca_for_tail_call.ll
deleted file mode 100644
index 741f584..0000000
--- a/test/Transforms/TailCallElim/move_alloca_for_tail_call.ll
+++ /dev/null
@@ -1,15 +0,0 @@
-; RUN: opt -tailcallelim -S < %s | FileCheck %s
-; PR615
-
-declare void @bar(i32*)
-
-define i32 @foo() {
-; CHECK: i32 @foo()
-; CHECK-NEXT: alloca
-	%A = alloca i32		; <i32*> [#uses=2]
-	store i32 17, i32* %A
-	call void @bar( i32* %A )
-	%X = tail call i32 @foo( )		; <i32> [#uses=1]
-	ret i32 %X
-}
-
diff --git a/test/Transforms/TailCallElim/nocapture.ll b/test/Transforms/TailCallElim/nocapture.ll
deleted file mode 100644
index e49d87c..0000000
--- a/test/Transforms/TailCallElim/nocapture.ll
+++ /dev/null
@@ -1,25 +0,0 @@
-; RUN: opt -tailcallelim -S < %s | FileCheck %s
-; XFAIL: *
-
-declare void @use(i8* nocapture, i8* nocapture)
-
-define i8* @foo(i8* nocapture %A, i1 %cond) {
-; CHECK: tailrecurse:
-; CHECK: %A.tr = phi i8* [ %A, %0 ], [ %B, %cond_true ]
-; CHECK: %cond.tr = phi i1 [ %cond, %0 ], [ false, %cond_true ]
-  %B = alloca i8
-; CHECK: %B = alloca i8
-  br i1 %cond, label %cond_true, label %cond_false
-; CHECK: br i1 %cond.tr, label %cond_true, label %cond_false
-cond_true:
-; CHECK: cond_true:
-; CHECK: br label %tailrecurse
-  call i8* @foo(i8* %B, i1 false)
-  ret i8* null
-cond_false:
-; CHECK: cond_false
-  call void @use(i8* %A, i8* %B)
-; CHECK: tail call void @use(i8* %A.tr, i8* %B)
-  ret i8* null
-; CHECK: ret i8* null
-}
diff --git a/test/Transforms/TailCallElim/return_constant.ll b/test/Transforms/TailCallElim/return_constant.ll
deleted file mode 100644
index e99e57e..0000000
--- a/test/Transforms/TailCallElim/return_constant.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; Though this case seems to be fairly unlikely to occur in the wild, someone
-; plunked it into the demo script, so maybe they care about it.
-;
-; RUN: opt < %s -tailcallelim -S | FileCheck %s
-
-define i32 @aaa(i32 %c) {
-entry:
-	%tmp.1 = icmp eq i32 %c, 0		; <i1> [#uses=1]
-	br i1 %tmp.1, label %return, label %else
-else:		; preds = %entry
-	%tmp.5 = add i32 %c, -1		; <i32> [#uses=1]
-; CHECK-NOT: call
-	%tmp.3 = call i32 @aaa( i32 %tmp.5 )		; <i32> [#uses=0]
-	ret i32 0
-return:		; preds = %entry
-	ret i32 0
-}
-
diff --git a/test/Transforms/TailCallElim/trivial_codegen_tailcall.ll b/test/Transforms/TailCallElim/trivial_codegen_tailcall.ll
deleted file mode 100644
index 7049e4d..0000000
--- a/test/Transforms/TailCallElim/trivial_codegen_tailcall.ll
+++ /dev/null
@@ -1,11 +0,0 @@
-; RUN: opt < %s -tailcallelim -S | FileCheck %s
-
-
-declare void @foo()
-
-define void @bar() {
-; CHECK: tail call void @foo()
-	call void @foo()
-	ret void
-}
-
diff --git a/test/Verifier/bitcast-address-space-nested-global-cycle.ll b/test/Verifier/bitcast-address-space-nested-global-cycle.ll
new file mode 100644
index 0000000..0cee726
--- /dev/null
+++ b/test/Verifier/bitcast-address-space-nested-global-cycle.ll
@@ -0,0 +1,8 @@
+; RUN: not llvm-as -verify -disable-output %s
+
+target datalayout = "e-p:32:32:32-p1:16:16:16-p2:8:8:8-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n8:16:32"
+
+%struct.Self1 = type { %struct.Self1 addrspace(1)* }
+
+@cycle1 = addrspace(1) constant %struct.Self1 { %struct.Self1 addrspace(1)* bitcast (%struct.Self1 addrspace(0)* @cycle0 to %struct.Self1 addrspace(1)*) }
+@cycle0 = addrspace(0) constant %struct.Self1 { %struct.Self1 addrspace(1)* @cycle1 }
diff --git a/test/Verifier/bitcast-address-space-nested-global.ll b/test/Verifier/bitcast-address-space-nested-global.ll
new file mode 100644
index 0000000..abe9d94
--- /dev/null
+++ b/test/Verifier/bitcast-address-space-nested-global.ll
@@ -0,0 +1,11 @@
+; RUN: not llvm-as -verify -disable-output %s
+
+target datalayout = "e-p:32:32:32-p1:16:16:16-p2:8:8:8-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n8:16:32"
+
+
+%struct.Self1 = type { %struct.Self1 addrspace(1)* }
+
+@nestedD = constant %struct.Self1 { %struct.Self1 addrspace(1)* bitcast (%struct.Self1 addrspace(0)* @nestedC to %struct.Self1 addrspace(1)*) }
+@nestedC = constant %struct.Self1 { %struct.Self1 addrspace(1)* bitcast (%struct.Self1 addrspace(0)* @nestedB to %struct.Self1 addrspace(1)*) }
+@nestedB = constant %struct.Self1 { %struct.Self1 addrspace(1)* bitcast (%struct.Self1 addrspace(0)* @nestedA to %struct.Self1 addrspace(1)*) }
+@nestedA = constant %struct.Self1 { %struct.Self1 addrspace(1)* null }
diff --git a/test/Verifier/bitcast-address-space-through-constant-inttoptr-inside-gep-instruction.ll b/test/Verifier/bitcast-address-space-through-constant-inttoptr-inside-gep-instruction.ll
new file mode 100644
index 0000000..ed71afa
--- /dev/null
+++ b/test/Verifier/bitcast-address-space-through-constant-inttoptr-inside-gep-instruction.ll
@@ -0,0 +1,10 @@
+; RUN: not llvm-as -verify -disable-output < %s
+target datalayout = "e-p:32:32:32-p1:16:16:16-p2:8:8:8-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n8:16:32"
+
+; Check that we can find inttoptr -> illegal bitcasts when hidden
+; inside constantexpr pointer operands
+define i32 addrspace(2)* @illegal_bitcast_inttoptr_as_1_to_2_inside_gep() {
+  %cast = getelementptr i32 addrspace(2)* bitcast (i32 addrspace(1)* inttoptr (i32 1234 to i32 addrspace(1)*) to i32 addrspace(2)*), i32 3
+  ret i32 addrspace(2)* %cast
+}
+
diff --git a/test/Verifier/bitcast-address-space-through-constant-inttoptr.ll b/test/Verifier/bitcast-address-space-through-constant-inttoptr.ll
new file mode 100644
index 0000000..e65c71e
--- /dev/null
+++ b/test/Verifier/bitcast-address-space-through-constant-inttoptr.ll
@@ -0,0 +1,11 @@
+; RUN: not llvm-as -verify -disable-output %s
+
+target datalayout = "e-p:32:32:32-p1:16:16:16-p2:8:8:8-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n8:16:32"
+
+
+%struct.Foo = type { i32 addrspace(1)* }
+
+; Make sure we still reject the bitcast when the source is a inttoptr (constant int) in a global initializer
+@bitcast_after_constant_inttoptr_initializer = global %struct.Foo { i32 addrspace(1)* bitcast (i32 addrspace(2)* inttoptr (i8 7 to i32 addrspace(2)*) to i32 addrspace(1)*) }
+
+
diff --git a/test/Verifier/bitcast-address-space-through-gep-2.ll b/test/Verifier/bitcast-address-space-through-gep-2.ll
new file mode 100644
index 0000000..3b77d9a
--- /dev/null
+++ b/test/Verifier/bitcast-address-space-through-gep-2.ll
@@ -0,0 +1,17 @@
+; RUN: not llvm-as -verify -disable-output %s
+
+target datalayout = "e-p:32:32:32-p1:16:16:16-p2:8:8:8-p3:8:8:8-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n8:16:32"
+
+
+%struct.Foo1 = type { i32 addrspace(1)* }
+
+@as2_array = addrspace(2) global [32 x i32] zeroinitializer
+
+; gep -> legal bitcast (2 -> 3) -> gep -> illegal bitcast (3 -> 1)
+@bitcast_after_gep_bitcast_gep =
+         global %struct.Foo1 { i32 addrspace(1)* bitcast
+                                    (i32 addrspace(3)* getelementptr
+                                         (i32 addrspace(3)* bitcast
+                                              (i32 addrspace(2)* getelementptr
+                                                   ([32 x i32] addrspace(2)* @as2_array, i32 0, i32 8) to i32 addrspace(3)*), i32 3) to i32 addrspace(1)*) }
+
diff --git a/test/Verifier/bitcast-address-space-through-gep.ll b/test/Verifier/bitcast-address-space-through-gep.ll
new file mode 100644
index 0000000..8e950dc
--- /dev/null
+++ b/test/Verifier/bitcast-address-space-through-gep.ll
@@ -0,0 +1,13 @@
+; RUN: not llvm-as -verify -disable-output %s
+
+target datalayout = "e-p:32:32:32-p1:16:16:16-p2:8:8:8-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n8:16:32"
+
+%struct.Foo = type { i32 addrspace(1)* }
+
+
+@as2_array = addrspace(2) global [32 x i32] zeroinitializer
+
+; Make sure we still reject the bitcast after the value is accessed through a GEP
+@bitcast_after_gep = global %struct.Foo { i32 addrspace(1)* bitcast (i32 addrspace(2)* getelementptr ([32 x i32] addrspace(2)* @as2_array, i32 0, i32 8) to i32 addrspace(1)*) }
+
+
diff --git a/test/Verifier/bitcast-address-space-through-inttoptr.ll b/test/Verifier/bitcast-address-space-through-inttoptr.ll
new file mode 100644
index 0000000..bec4048
--- /dev/null
+++ b/test/Verifier/bitcast-address-space-through-inttoptr.ll
@@ -0,0 +1,9 @@
+; RUN: not llvm-as -verify -disable-output %s
+
+target datalayout = "e-p:32:32:32-p1:16:16:16-p2:8:8:8-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n8:16:32"
+
+define i32 addrspace(2)* @illegal_bitcast_as_1_to_2_inttoptr() {
+   %cast = bitcast i32 addrspace(1)* inttoptr (i32 5 to i32 addrspace(1)*) to i32 addrspace(2)*
+   ret i32 addrspace(2)* %cast
+}
+
diff --git a/test/Verifier/bitcast-address-spaces.ll b/test/Verifier/bitcast-address-spaces.ll
new file mode 100644
index 0000000..4508417
--- /dev/null
+++ b/test/Verifier/bitcast-address-spaces.ll
@@ -0,0 +1,9 @@
+; RUN: not llvm-as -verify -disable-output %s
+
+target datalayout = "e-p:32:32:32-p1:16:16:16-p2:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n8:16:32"
+
+define i32 addrspace(1)* @illegal_bitcast_as_0_to_1(i32 addrspace(0) *%p) {
+  %cast = bitcast i32 addrspace(0)* %p to i32 addrspace(1)*
+  ret i32 addrspace(1)* %cast
+}
+
diff --git a/test/Verifier/bitcast-alias-address-space.ll b/test/Verifier/bitcast-alias-address-space.ll
new file mode 100644
index 0000000..9cad8ab
--- /dev/null
+++ b/test/Verifier/bitcast-alias-address-space.ll
@@ -0,0 +1,8 @@
+; RUN: not llvm-as -verify -disable-output %s
+
+target datalayout = "e-p:32:32:32-p1:16:16:16-p2:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n8:16:32"
+
+
+@data = addrspace(2) global i32 27
+
+@illegal_alias_data = alias bitcast (i32 addrspace(2)* @data to i32 addrspace(1)*)
diff --git a/test/Verifier/bitcast-vector-pointer-as.ll b/test/Verifier/bitcast-vector-pointer-as.ll
new file mode 100644
index 0000000..89070e5
--- /dev/null
+++ b/test/Verifier/bitcast-vector-pointer-as.ll
@@ -0,0 +1,9 @@
+; RUN: not llvm-as -verify -disable-output %s
+
+target datalayout = "e-p:32:32:32-p1:16:16:16-p2:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n8:16:32"
+
+define <4 x i32 addrspace(1)*> @vector_illegal_bitcast_as_0_to_1(<4 x i32 addrspace(0)*> %p) {
+   %cast = bitcast <4 x i32 addrspace(0)*> %p to <4 x i32 addrspace(1)*>
+   ret <4 x i32 addrspace(1)*> %cast
+}
+
diff --git a/test/Verifier/llvm.compiler_used-invalid-type.ll b/test/Verifier/llvm.compiler_used-invalid-type.ll
index 0913027..ef533b5 100644
--- a/test/Verifier/llvm.compiler_used-invalid-type.ll
+++ b/test/Verifier/llvm.compiler_used-invalid-type.ll
@@ -1,6 +1,6 @@
 ; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s
 
-@llvm.compiler_used = appending global [1 x i32] [i32 0], section "llvm.metadata"
+@llvm.compiler.used = appending global [1 x i32] [i32 0], section "llvm.metadata"
 
 ; CHECK:       wrong type for intrinsic global variable
-; CHECK-NEXT: [1 x i32]* @llvm.compiler_used
+; CHECK-NEXT: [1 x i32]* @llvm.compiler.used
diff --git a/test/Verifier/llvm.used-invalid-type2.ll b/test/Verifier/llvm.used-invalid-type2.ll
index bff3f2d..4bd0aa4 100644
--- a/test/Verifier/llvm.used-invalid-type2.ll
+++ b/test/Verifier/llvm.used-invalid-type2.ll
@@ -2,4 +2,4 @@
 @llvm.used = appending global i32 0, section "llvm.metadata"
 
 ; CHECK: Only global arrays can have appending linkage!
-; CHEKC-NEXT: i32* @llvm.used
+; CHECK-NEXT: i32* @llvm.used
diff --git a/test/lit.cfg b/test/lit.cfg
index 8272e97..c018674 100644
--- a/test/lit.cfg
+++ b/test/lit.cfg
@@ -201,9 +201,14 @@ if os.pathsep == ';':
     pathext = os.environ.get('PATHEXT', '').split(';')
 else:
     pathext = ['']
+# Regex to reject matching a hyphen
+NOHYPHEN = r"(?<!-)"
+
 for pattern in [r"\bbugpoint\b(?!-)",   r"(?<!/|-)\bclang\b(?!-)",
                 r"\bgold\b",
-                r"\bllc\b",             r"\blli\b",
+                # Match llc but not -llc
+                NOHYPHEN + r"\bllc\b",
+                r"\blli\b",
                 r"\bllvm-ar\b",         r"\bllvm-as\b",
                 r"\bllvm-bcanalyzer\b", r"\bllvm-config\b",
                 r"\bllvm-cov\b",        r"\bllvm-diff\b",
@@ -211,11 +216,11 @@ for pattern in [r"\bbugpoint\b(?!-)",   r"(?<!/|-)\bclang\b(?!-)",
                 r"\bllvm-extract\b",    r"\bllvm-jistlistener\b",
                 r"\bllvm-link\b",       r"\bllvm-mc\b",
                 r"\bllvm-nm\b",         r"\bllvm-objdump\b",
-                r"\bllvm-prof\b",       r"\bllvm-ranlib\b",
+                r"\bllvm-prof\b",       r"\bllvm-size\b",
                 r"\bllvm-rtdyld\b",     r"\bllvm-shlib\b",
-                r"\bllvm-size\b",
-                # Don't match '-llvmc'.
-                r"(?<!-)\bllvmc\b",     r"\blto\b",
+                # Match llvmc but not -llvmc
+                NOHYPHEN + r"\bllvmc\b",
+                r"\blto\b",
                                         # Don't match '.opt', '-opt',
                                         # '^opt' or '/opt'.
                 r"\bmacho-dump\b",      r"(?<!\.|-|\^|/)\bopt\b",
@@ -245,6 +250,10 @@ for pattern in [r"\bbugpoint\b(?!-)",   r"(?<!/|-)\bclang\b(?!-)",
 if execute_external:
     config.available_features.add('shell')
 
+# Others/can-execute.txt
+if sys.platform not in ['win32']:
+    config.available_features.add('can-execute')
+
 # Loadable module
 # FIXME: This should be supplied by Makefile or autoconf.
 if sys.platform in ['win32', 'cygwin']:
@@ -255,10 +264,6 @@ else:
 if loadable_module:
     config.available_features.add('loadable_module')
 
-# LTO on OS X
-if config.lto_is_enabled == "1" and platform.system() == "Darwin":
-    config.available_features.add('lto_on_osx')
-
 # Sanitizers.
 if config.llvm_use_sanitizer == "Address":
     config.available_features.add("asan")
@@ -285,3 +290,23 @@ except OSError, why:
 if re.search(r'with assertions', llc_cmd.stdout.read()):
     config.available_features.add('asserts')
 llc_cmd.wait()
+
+# Check if we should use gmalloc.
+use_gmalloc_str = lit.params.get('use_gmalloc', None)
+if use_gmalloc_str is not None:
+    if use_gmalloc_str.lower() in ('1', 'true'):
+        use_gmalloc = True
+    elif use_gmalloc_str.lower() in ('', '0', 'false'):
+        use_gmalloc = False
+    else:
+        lit.fatal('user parameter use_gmalloc should be 0 or 1')
+else:
+    # Default to not using gmalloc
+    use_gmalloc = False
+
+# Allow use of an explicit path for gmalloc library.
+# Will default to '/usr/lib/libgmalloc.dylib' if not set.
+gmalloc_path_str = lit.params.get('gmalloc_path', '/usr/lib/libgmalloc.dylib')
+
+if use_gmalloc:
+     config.environment.update({'DYLD_INSERT_LIBRARIES' : gmalloc_path_str})
diff --git a/test/tools/llvm-readobj/Inputs/relocs.py b/test/tools/llvm-readobj/Inputs/relocs.py
index 232d080..af9459d 100644
--- a/test/tools/llvm-readobj/Inputs/relocs.py
+++ b/test/tools/llvm-readobj/Inputs/relocs.py
@@ -533,30 +533,6 @@ class Relocs_Elf_i386(Enum):
   R_386_IRELATIVE     = 42
   R_386_NUM           = 43
 
-class Relocs_Elf_MBlaze(Enum):
-  R_MICROBLAZE_NONE           = 0
-  R_MICROBLAZE_32             = 1
-  R_MICROBLAZE_32_PCREL       = 2
-  R_MICROBLAZE_64_PCREL       = 3
-  R_MICROBLAZE_32_PCREL_LO    = 4
-  R_MICROBLAZE_64             = 5
-  R_MICROBLAZE_32_LO          = 6
-  R_MICROBLAZE_SRO32          = 7
-  R_MICROBLAZE_SRW32          = 8
-  R_MICROBLAZE_64_NONE        = 9
-  R_MICROBLAZE_32_SYM_OP_SYM  = 10
-  R_MICROBLAZE_GNU_VTINHERIT  = 11
-  R_MICROBLAZE_GNU_VTENTRY    = 12
-  R_MICROBLAZE_GOTPC_64       = 13
-  R_MICROBLAZE_GOT_64         = 14
-  R_MICROBLAZE_PLT_64         = 15
-  R_MICROBLAZE_REL            = 16
-  R_MICROBLAZE_JUMP_SLOT      = 17
-  R_MICROBLAZE_GLOB_DAT       = 18
-  R_MICROBLAZE_GOTOFF_64      = 19
-  R_MICROBLAZE_GOTOFF_32      = 20
-  R_MICROBLAZE_COPY           = 21
-
 class Relocs_Elf_PPC32(Enum):
   R_PPC_NONE                  = 0
   R_PPC_ADDR32                = 1
@@ -1071,7 +1047,6 @@ craftElf("relocs.obj.elf-aarch64",  "aarch64",                     Relocs_Elf_AA
 craftElf("relocs.obj.elf-arm",      "arm-unknown-unknown",         Relocs_Elf_ARM.entries(), "b sym")
 craftElf("relocs.obj.elf-mips",     "mips-unknown-linux",          Relocs_Elf_Mips.entries(), "lui $2, %hi(sym)")
 craftElf("relocs.obj.elf-mips64el", "mips64el-unknown-linux",        Relocs_Elf_Mips.entries(), "lui $2, %hi(sym)")
-#craftElf("relocs.obj.elf-mblaze",   "mblaze-unknown-unknown",      Relocs_Elf_MBlaze.entries(), ...)
 #craftElf("relocs.obj.elf-hexagon",  "hexagon-unknown-unknown",     Relocs_Elf_Hexagon.entries(), ...)
 
 craftCoff("relocs.obj.coff-i386",   "i386-pc-win32",   Relocs_Coff_i386.entries(),   "mov foo@imgrel(%ebx, %ecx, 4), %eax")
diff --git a/test/tools/llvm-readobj/Inputs/trivial.exe.coff-i386 b/test/tools/llvm-readobj/Inputs/trivial.exe.coff-i386
new file mode 100644
index 0000000..1558d24
--- /dev/null
+++ b/test/tools/llvm-readobj/Inputs/trivial.exe.coff-i386
diff --git a/test/tools/llvm-readobj/file-headers.test b/test/tools/llvm-readobj/file-headers.test
index 226eb93..b900e36 100644
--- a/test/tools/llvm-readobj/file-headers.test
+++ b/test/tools/llvm-readobj/file-headers.test
@@ -2,6 +2,8 @@ RUN: llvm-readobj -h %p/Inputs/trivial.obj.coff-i386 \
 RUN:   | FileCheck %s -check-prefix COFF32
 RUN: llvm-readobj -h %p/Inputs/trivial.obj.coff-x86-64 \
 RUN:   | FileCheck %s -check-prefix COFF64
+RUN: llvm-readobj -h %p/Inputs/trivial.exe.coff-i386 \
+RUN:   | FileCheck %s -check-prefix PE32
 RUN: llvm-readobj -h %p/Inputs/trivial.obj.elf-i386 \
 RUN:   | FileCheck %s -check-prefix ELF32
 RUN: llvm-readobj -h %p/Inputs/trivial.obj.elf-x86-64 \
@@ -98,3 +100,86 @@ ELF64-NEXT:   SectionHeaderEntrySize: 64
 ELF64-NEXT:   SectionHeaderCount: 10
 ELF64-NEXT:   StringTableSectionIndex: 7
 ELF64-NEXT: }
+
+PE32:      File: {{(.*[/\\])?}}trivial.exe.coff-i386
+PE32-NEXT: Format: COFF-i386
+PE32-NEXT: Arch: i386
+PE32-NEXT: AddressSize: 32bit
+PE32-NEXT: ImageFileHeader {
+PE32-NEXT:   Machine: IMAGE_FILE_MACHINE_I386 (0x14C)
+PE32-NEXT:   SectionCount: 3
+PE32-NEXT:   TimeDateStamp: 2013-07-16 00:39:15 (0x51E49633)
+PE32-NEXT:   PointerToSymbolTable: 0x0
+PE32-NEXT:   SymbolCount: 0
+PE32-NEXT:   OptionalHeaderSize: 224
+PE32-NEXT:   Characteristics [ (0x102)
+PE32-NEXT:     IMAGE_FILE_32BIT_MACHINE (0x100)
+PE32-NEXT:     IMAGE_FILE_EXECUTABLE_IMAGE (0x2)
+PE32-NEXT:   ]
+PE32-NEXT: }
+PE32-NEXT: ImageOptionalHeader {
+PE32-NEXT:   MajorLinkerVersion: 11
+PE32-NEXT:   MinorLinkerVersion: 0
+PE32-NEXT:   SizeOfCode: 512
+PE32-NEXT:   SizeOfInitializedData: 1024
+PE32-NEXT:   SizeOfUninitializedData: 0
+PE32-NEXT:   AddressOfEntryPoint: 0x1000
+PE32-NEXT:   BaseOfCode: 0x1000
+PE32-NEXT:   BaseOfData: 0x2000
+PE32-NEXT:   ImageBase: 0x400000
+PE32-NEXT:   SectionAlignment: 4096
+PE32-NEXT:   FileAlignment: 512
+PE32-NEXT:   MajorOperatingSystemVersion: 6
+PE32-NEXT:   MinorOperatingSystemVersion: 0
+PE32-NEXT:   MajorImageVersion: 0
+PE32-NEXT:   MinorImageVersion: 0
+PE32-NEXT:   MajorSubsystemVersion: 6
+PE32-NEXT:   MinorSubsystemVersion: 0
+PE32-NEXT:   SizeOfImage: 16384
+PE32-NEXT:   SizeOfHeaders: 1024
+PE32-NEXT:   Subsystem: IMAGE_SUBSYSTEM_WINDOWS_CUI (0x3)
+PE32-NEXT:   Subsystem [ (0x8140)
+PE32-NEXT:     IMAGE_DLL_CHARACTERISTICS_DYNAMIC_BASE (0x40)
+PE32-NEXT:     IMAGE_DLL_CHARACTERISTICS_NX_COMPAT (0x100)
+PE32-NEXT:     IMAGE_DLL_CHARACTERISTICS_TERMINAL_SERVER_AWARE (0x8000)
+PE32-NEXT:   ]
+PE32-NEXT:   SizeOfStackReserve: 1048576
+PE32-NEXT:   SizeOfStackCommit: 4096
+PE32-NEXT:   SizeOfHeapReserve: 1048576
+PE32-NEXT:   SizeOfHeapCommit: 4096
+PE32-NEXT:   NumberOfRvaAndSize: 16
+PE32-NEXT:   DataDirectory {
+PE32-NEXT:     ExportTableRVA: 0x0
+PE32-NEXT:     ExportTableSize: 0x0
+PE32-NEXT:     ImportTableRVA: 0x0
+PE32-NEXT:     ImportTableSize: 0x0
+PE32-NEXT:     ResourceTableRVA: 0x0
+PE32-NEXT:     ResourceTableSize: 0x0
+PE32-NEXT:     ExceptionTableRVA: 0x0
+PE32-NEXT:     ExceptionTableSize: 0x0
+PE32-NEXT:     CertificateTableRVA: 0x0
+PE32-NEXT:     CertificateTableSize: 0x0
+PE32-NEXT:     BaseRelocationTableRVA: 0x3000
+PE32-NEXT:     BaseRelocationTableSize: 0xC
+PE32-NEXT:     DebugRVA: 0x0
+PE32-NEXT:     DebugSize: 0x0
+PE32-NEXT:     ArchitectureRVA: 0x0
+PE32-NEXT:     ArchitectureSize: 0x0
+PE32-NEXT:     GlobalPtrRVA: 0x0
+PE32-NEXT:     GlobalPtrSize: 0x0
+PE32-NEXT:     TLSTableRVA: 0x0
+PE32-NEXT:     TLSTableSize: 0x0
+PE32-NEXT:     LoadConfigTableRVA: 0x0
+PE32-NEXT:     LoadConfigTableSize: 0x0
+PE32-NEXT:     BoundImportRVA: 0x0
+PE32-NEXT:     BoundImportSize: 0x0
+PE32-NEXT:     IATRVA: 0x0
+PE32-NEXT:     IATSize: 0x0
+PE32-NEXT:     DelayImportDescriptorRVA: 0x0
+PE32-NEXT:     DelayImportDescriptorSize: 0x0
+PE32-NEXT:     CLRRuntimeHeaderRVA: 0x0
+PE32-NEXT:     CLRRuntimeHeaderSize: 0x0
+PE32-NEXT:     ReservedRVA: 0x0
+PE32-NEXT:     ReservedSize: 0x0
+PE32-NEXT:   }
+PE32-NEXT: }
diff --git a/test/tools/llvm-readobj/reloc-types.test b/test/tools/llvm-readobj/reloc-types.test
index 08603bc..0c8b54d 100644
--- a/test/tools/llvm-readobj/reloc-types.test
+++ b/test/tools/llvm-readobj/reloc-types.test
@@ -460,29 +460,6 @@ ELF-MIPS64EL: Type: R_MIPS_COPY/R_MIPS_COPY/R_MIPS_COPY (8289918)
 ELF-MIPS64EL: Type: R_MIPS_JUMP_SLOT/R_MIPS_JUMP_SLOT/R_MIPS_JUMP_SLOT (8355711)
 ELF-MIPS64EL: Type: R_MIPS_NUM/R_MIPS_NUM/R_MIPS_NUM (14342874)
 
-ELF-MBLAZE: Type: R_MICROBLAZE_NONE (0)
-ELF-MBLAZE: Type: R_MICROBLAZE_32 (1)
-ELF-MBLAZE: Type: R_MICROBLAZE_32_PCREL (2)
-ELF-MBLAZE: Type: R_MICROBLAZE_64_PCREL (3)
-ELF-MBLAZE: Type: R_MICROBLAZE_32_PCREL_LO (4)
-ELF-MBLAZE: Type: R_MICROBLAZE_64 (5)
-ELF-MBLAZE: Type: R_MICROBLAZE_32_LO (6)
-ELF-MBLAZE: Type: R_MICROBLAZE_SRO32 (7)
-ELF-MBLAZE: Type: R_MICROBLAZE_SRW32 (8)
-ELF-MBLAZE: Type: R_MICROBLAZE_64_NONE (9)
-ELF-MBLAZE: Type: R_MICROBLAZE_32_SYM_OP_SYM (10)
-ELF-MBLAZE: Type: R_MICROBLAZE_GNU_VTINHERIT (11)
-ELF-MBLAZE: Type: R_MICROBLAZE_GNU_VTENTRY (12)
-ELF-MBLAZE: Type: R_MICROBLAZE_GOTPC_64 (13)
-ELF-MBLAZE: Type: R_MICROBLAZE_GOT_64 (14)
-ELF-MBLAZE: Type: R_MICROBLAZE_PLT_64 (15)
-ELF-MBLAZE: Type: R_MICROBLAZE_REL (16)
-ELF-MBLAZE: Type: R_MICROBLAZE_JUMP_SLOT (17)
-ELF-MBLAZE: Type: R_MICROBLAZE_GLOB_DAT (18)
-ELF-MBLAZE: Type: R_MICROBLAZE_GOTOFF_64 (19)
-ELF-MBLAZE: Type: R_MICROBLAZE_GOTOFF_32 (20)
-ELF-MBLAZE: Type: R_MICROBLAZE_COPY (21)
-
 ELF-HEXAGON: Type: R_HEX_NONE (0)
 ELF-HEXAGON: Type: R_HEX_B22_PCREL (1)
 ELF-HEXAGON: Type: R_HEX_B15_PCREL (2)