diff options
Diffstat (limited to 'test/CodeGen/SystemZ/int-sub-06.ll')
| -rw-r--r-- | test/CodeGen/SystemZ/int-sub-06.ll | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/test/CodeGen/SystemZ/int-sub-06.ll b/test/CodeGen/SystemZ/int-sub-06.ll index 0e04d51..395d584 100644 --- a/test/CodeGen/SystemZ/int-sub-06.ll +++ b/test/CodeGen/SystemZ/int-sub-06.ll @@ -5,7 +5,7 @@ ; Check register additions. The XOR ensures that we don't instead zero-extend ; %b into a register and use memory addition. define void @f1(i128 *%aptr, i32 %b) { -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK: slgfr {{%r[0-5]}}, %r3 ; CHECK: slbgr ; CHECK: br %r14 @@ -19,7 +19,7 @@ define void @f1(i128 *%aptr, i32 %b) { ; Like f1, but using an "in-register" extension. define void @f2(i128 *%aptr, i64 %b) { -; CHECK: f2: +; CHECK-LABEL: f2: ; CHECK: slgfr {{%r[0-5]}}, %r3 ; CHECK: slbgr ; CHECK: br %r14 @@ -35,7 +35,7 @@ define void @f2(i128 *%aptr, i64 %b) { ; Test register addition in cases where the second operand is zero extended ; from i64 rather than i32, but is later masked to i32 range. define void @f3(i128 *%aptr, i64 %b) { -; CHECK: f3: +; CHECK-LABEL: f3: ; CHECK: slgfr {{%r[0-5]}}, %r3 ; CHECK: slbgr ; CHECK: br %r14 @@ -50,7 +50,7 @@ define void @f3(i128 *%aptr, i64 %b) { ; Test SLGF with no offset. define void @f4(i128 *%aptr, i32 *%bsrc) { -; CHECK: f4: +; CHECK-LABEL: f4: ; CHECK: slgf {{%r[0-5]}}, 0(%r3) ; CHECK: slbgr ; CHECK: br %r14 @@ -65,7 +65,7 @@ define void @f4(i128 *%aptr, i32 *%bsrc) { ; Check the high end of the SLGF range. define void @f5(i128 *%aptr, i32 *%bsrc) { -; CHECK: f5: +; CHECK-LABEL: f5: ; CHECK: slgf {{%r[0-5]}}, 524284(%r3) ; CHECK: slbgr ; CHECK: br %r14 @@ -82,7 +82,7 @@ define void @f5(i128 *%aptr, i32 *%bsrc) { ; Check the next word up, which must use separate address logic. ; Other sequences besides this one would be OK. define void @f6(i128 *%aptr, i32 *%bsrc) { -; CHECK: f6: +; CHECK-LABEL: f6: ; CHECK: agfi %r3, 524288 ; CHECK: slgf {{%r[0-5]}}, 0(%r3) ; CHECK: slbgr @@ -99,7 +99,7 @@ define void @f6(i128 *%aptr, i32 *%bsrc) { ; Check the high end of the negative aligned SLGF range. define void @f7(i128 *%aptr, i32 *%bsrc) { -; CHECK: f7: +; CHECK-LABEL: f7: ; CHECK: slgf {{%r[0-5]}}, -4(%r3) ; CHECK: slbgr ; CHECK: br %r14 @@ -115,7 +115,7 @@ define void @f7(i128 *%aptr, i32 *%bsrc) { ; Check the low end of the SLGF range. define void @f8(i128 *%aptr, i32 *%bsrc) { -; CHECK: f8: +; CHECK-LABEL: f8: ; CHECK: slgf {{%r[0-5]}}, -524288(%r3) ; CHECK: slbgr ; CHECK: br %r14 @@ -132,7 +132,7 @@ define void @f8(i128 *%aptr, i32 *%bsrc) { ; Check the next word down, which needs separate address logic. ; Other sequences besides this one would be OK. define void @f9(i128 *%aptr, i32 *%bsrc) { -; CHECK: f9: +; CHECK-LABEL: f9: ; CHECK: agfi %r3, -524292 ; CHECK: slgf {{%r[0-5]}}, 0(%r3) ; CHECK: slbgr @@ -149,7 +149,7 @@ define void @f9(i128 *%aptr, i32 *%bsrc) { ; Check that SLGF allows an index. define void @f10(i128 *%aptr, i64 %src, i64 %index) { -; CHECK: f10: +; CHECK-LABEL: f10: ; CHECK: slgf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}}) ; CHECK: br %r14 %a = load i128 *%aptr |