diff options
Diffstat (limited to 'test/CodeGen/ARM')
30 files changed, 131 insertions, 73 deletions
diff --git a/test/CodeGen/ARM/2009-10-30.ll b/test/CodeGen/ARM/2009-10-30.ll index 87d1a8b..e46ab1e 100644 --- a/test/CodeGen/ARM/2009-10-30.ll +++ b/test/CodeGen/ARM/2009-10-30.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s +; RUN: llc < %s -mtriple=armv6-linux-gnueabi | FileCheck %s ; This test checks that the address of the varg arguments is correctly ; computed when there are 5 or more regular arguments. diff --git a/test/CodeGen/ARM/2009-11-01-NeonMoves.ll b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll index 34f7519..a18a830 100644 --- a/test/CodeGen/ARM/2009-11-01-NeonMoves.ll +++ b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll @@ -19,7 +19,7 @@ entry: %5 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %3, <2 x float> %4) nounwind ; <<2 x float>> [#uses=2] %6 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %5, <2 x float> %5) nounwind ; <<2 x float>> [#uses=2] %7 = shufflevector <2 x float> %6, <2 x float> %6, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=2] -;CHECK: vmov +;CHECK: vorr %8 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %7) nounwind ; <<4 x float>> [#uses=3] %9 = fmul <4 x float> %8, %8 ; <<4 x float>> [#uses=1] %10 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %9, <4 x float> %7) nounwind ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll index ee443fe..99db637 100644 --- a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll +++ b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll @@ -1,7 +1,7 @@ ; RUN: llc %s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \ ; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=BASIC %s ; RUN: llc %s -mtriple=armv7-linux-gnueabi -march=arm -mcpu=cortex-a8 \ -; RUN: -mattr=-neon -mattr=+vfp2 \ +; RUN: -mattr=-neon,-vfp3,+vfp2 \ ; RUN: -arm-reserve-r9 -filetype=obj -o - | \ ; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=CORTEXA8 %s diff --git a/test/CodeGen/ARM/2011-07-10-GlobalMergeBug.ll b/test/CodeGen/ARM/2011-07-10-GlobalMergeBug.ll new file mode 100644 index 0000000..2970cd2 --- /dev/null +++ b/test/CodeGen/ARM/2011-07-10-GlobalMergeBug.ll @@ -0,0 +1,8 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +; CHECK-NOT: MergedGlobals + +@a = internal unnamed_addr global i1 false +@b = internal global [64 x i8] zeroinitializer, align 64 diff --git a/test/CodeGen/ARM/armv4.ll b/test/CodeGen/ARM/armv4.ll index ef722de..6b213d5 100644 --- a/test/CodeGen/ARM/armv4.ll +++ b/test/CodeGen/ARM/armv4.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=arm-unknown-eabi | FileCheck %s -check-prefix=THUMB -; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB -; RUN: llc < %s -mtriple=arm-unknown-eabi -mattr=+v6 | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -mtriple=armv4-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -mtriple=armv7-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -mtriple=armv6-unknown-eabi | FileCheck %s -check-prefix=THUMB ; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM ; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB diff --git a/test/CodeGen/ARM/bfx.ll b/test/CodeGen/ARM/bfx.ll index fcca191..519c135 100644 --- a/test/CodeGen/ARM/bfx.ll +++ b/test/CodeGen/ARM/bfx.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s define i32 @sbfx1(i32 %a) { ; CHECK: sbfx1 diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll index c460f7a..e01750b 100644 --- a/test/CodeGen/ARM/call-tc.ll +++ b/test/CodeGen/ARM/call-tc.ll @@ -15,11 +15,11 @@ define void @t1() { define void @t2() { ; CHECKV6: t2: -; CHECKV6: bx r0 @ TAILCALL +; CHECKV6: bx r0 ; CHECKT2D: t2: ; CHECKT2D: ldr ; CHECKT2D-NEXT: ldr -; CHECKT2D-NEXT: bx r0 @ TAILCALL +; CHECKT2D-NEXT: bx r0 %tmp = load i32 ()** @t ; <i32 ()*> [#uses=1] %tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0] ret void @@ -27,11 +27,11 @@ define void @t2() { define void @t3() { ; CHECKV6: t3: -; CHECKV6: b _t2 @ TAILCALL +; CHECKV6: b _t2 ; CHECKELF: t3: -; CHECKELF: b t2(PLT) @ TAILCALL +; CHECKELF: b t2(PLT) ; CHECKT2D: t3: -; CHECKT2D: b.w _t2 @ TAILCALL +; CHECKT2D: b.w _t2 tail call void @t2( ) ; <i32> [#uses=0] ret void @@ -41,9 +41,9 @@ define void @t3() { define double @t4(double %a) nounwind readonly ssp { entry: ; CHECKV6: t4: -; CHECKV6: b _sin @ TAILCALL +; CHECKV6: b _sin ; CHECKELF: t4: -; CHECKELF: b sin(PLT) @ TAILCALL +; CHECKELF: b sin(PLT) %0 = tail call double @sin(double %a) nounwind readonly ; <double> [#uses=1] ret double %0 } @@ -51,9 +51,9 @@ entry: define float @t5(float %a) nounwind readonly ssp { entry: ; CHECKV6: t5: -; CHECKV6: b _sinf @ TAILCALL +; CHECKV6: b _sinf ; CHECKELF: t5: -; CHECKELF: b sinf(PLT) @ TAILCALL +; CHECKELF: b sinf(PLT) %0 = tail call float @sinf(float %a) nounwind readonly ; <float> [#uses=1] ret float %0 } @@ -65,9 +65,9 @@ declare double @sin(double) nounwind readonly define i32 @t6(i32 %a, i32 %b) nounwind readnone { entry: ; CHECKV6: t6: -; CHECKV6: b ___divsi3 @ TAILCALL +; CHECKV6: b ___divsi3 ; CHECKELF: t6: -; CHECKELF: b __aeabi_idiv(PLT) @ TAILCALL +; CHECKELF: b __aeabi_idiv(PLT) %0 = sdiv i32 %a, %b ret i32 %0 } diff --git a/test/CodeGen/ARM/call.ll b/test/CodeGen/ARM/call.ll index c020b6f..0f9543f 100644 --- a/test/CodeGen/ARM/call.ll +++ b/test/CodeGen/ARM/call.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECKV4 +; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s -check-prefix=CHECKV4 ; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5 -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\ +; RUN: llc < %s -mtriple=armv6-linux-gnueabi\ ; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF @t = weak global i32 ()* null ; <i32 ()**> [#uses=1] diff --git a/test/CodeGen/ARM/constants.ll b/test/CodeGen/ARM/constants.ll index 7b6c9d4..f4c1b5a 100644 --- a/test/CodeGen/ARM/constants.ll +++ b/test/CodeGen/ARM/constants.ll @@ -14,31 +14,31 @@ define i32 @f2() { define i32 @f3() { ; CHECK: f3 -; CHECK: mov r0, #1, #24 +; CHECK: mov r0, #256 ret i32 256 } define i32 @f4() { ; CHECK: f4 -; CHECK: orr{{.*}}#1, #24 +; CHECK: orr{{.*}}#256 ret i32 257 } define i32 @f5() { ; CHECK: f5 -; CHECK: mov r0, #255, #2 +; CHECK: mov r0, #-1073741761 ret i32 -1073741761 } define i32 @f6() { ; CHECK: f6 -; CHECK: mov r0, #63, #28 +; CHECK: mov r0, #1008 ret i32 1008 } define void @f7(i32 %a) { ; CHECK: f7 -; CHECK: cmp r0, #1, #16 +; CHECK: cmp r0, #65536 %b = icmp ugt i32 %a, 65536 br i1 %b, label %r, label %r r: diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll index 499c97f..eb0c5c8 100644 --- a/test/CodeGen/ARM/fast-isel.ll +++ b/test/CodeGen/ARM/fast-isel.ll @@ -43,7 +43,7 @@ b1: br label %b2 ; THUMB: add.w {{.*}} #4096 -; ARM: add {{.*}} #1, #20 +; ARM: add {{.*}} #4096 b2: %b = add i32 %tmp, 4095 diff --git a/test/CodeGen/ARM/fold-const.ll b/test/CodeGen/ARM/fold-const.ll new file mode 100644 index 0000000..227e4e8 --- /dev/null +++ b/test/CodeGen/ARM/fold-const.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s + +define i32 @f(i32 %a) nounwind readnone optsize ssp { +entry: + %conv = zext i32 %a to i64 + %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %conv) +; CHECK: clz +; CHECK-NOT: adds + %cast = trunc i64 %tmp1 to i32 + %sub = sub nsw i32 63, %cast + ret i32 %sub +} + +declare i64 @llvm.ctlz.i64(i64) nounwind readnone diff --git a/test/CodeGen/ARM/fp.ll b/test/CodeGen/ARM/fp.ll index 8ef45f2..ac023d1 100644 --- a/test/CodeGen/ARM/fp.ll +++ b/test/CodeGen/ARM/fp.ll @@ -42,7 +42,7 @@ entry: define double @h(double* %v) { ;CHECK: h: -;CHECK: vldr.64 +;CHECK: vldr.64 ;CHECK-NEXT: vmov entry: %tmp = load double* %v ; <double> [#uses=1] @@ -51,7 +51,7 @@ entry: define float @h2() { ;CHECK: h2: -;CHECK: mov r0, #254, #10 +;CHECK: mov r0, #1065353216 entry: ret float 1.000000e+00 } diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll index ccb1428..5e7e3f2 100644 --- a/test/CodeGen/ARM/globals.ll +++ b/test/CodeGen/ARM/globals.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic -; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic -; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC -; RUN: llc < %s -mtriple=arm-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC +; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic +; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic +; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC @G = external global i32 diff --git a/test/CodeGen/ARM/hello.ll b/test/CodeGen/ARM/hello.ll index bfed7a6..9f46ae0 100644 --- a/test/CodeGen/ARM/hello.ll +++ b/test/CodeGen/ARM/hello.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=arm -; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | count 1 -; RUN: llc < %s -mtriple=arm-linux-gnu --disable-fp-elim | \ +; RUN: llc < %s -mtriple=armv6-linux-gnueabi | grep mov | count 1 +; RUN: llc < %s -mtriple=armv6-linux-gnu --disable-fp-elim | \ ; RUN: grep mov | count 2 -; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | count 2 +; RUN: llc < %s -mtriple=armv6-apple-darwin | grep mov | count 2 @str = internal constant [12 x i8] c"Hello World\00" diff --git a/test/CodeGen/ARM/iabs.ll b/test/CodeGen/ARM/iabs.ll index 63808b2..c01c041 100644 --- a/test/CodeGen/ARM/iabs.ll +++ b/test/CodeGen/ARM/iabs.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s ;; Integer absolute value, should produce something as good as: ARM: ;; add r3, r0, r0, asr #31 diff --git a/test/CodeGen/ARM/ifcvt1.ll b/test/CodeGen/ARM/ifcvt1.ll index e6aa044..b073a05 100644 --- a/test/CodeGen/ARM/ifcvt1.ll +++ b/test/CodeGen/ARM/ifcvt1.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm -; RUN: llc < %s -march=arm | grep bx | count 1 +; RUN: llc < %s -march=arm -mattr=+v4t +; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 1 define i32 @t1(i32 %a, i32 %b) { %tmp2 = icmp eq i32 %a, 0 diff --git a/test/CodeGen/ARM/ifcvt2.ll b/test/CodeGen/ARM/ifcvt2.ll index 7b9d0cf..1bca10a 100644 --- a/test/CodeGen/ARM/ifcvt2.ll +++ b/test/CodeGen/ARM/ifcvt2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK: t1: diff --git a/test/CodeGen/ARM/ifcvt3.ll b/test/CodeGen/ARM/ifcvt3.ll index f7ebac6..3e2c578 100644 --- a/test/CodeGen/ARM/ifcvt3.ll +++ b/test/CodeGen/ARM/ifcvt3.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=arm -; RUN: llc < %s -march=arm | grep cmpne | count 1 -; RUN: llc < %s -march=arm | grep bx | count 2 +; RUN: llc < %s -march=arm -mattr=+v4t +; RUN: llc < %s -march=arm -mattr=+v4t | grep cmpne | count 1 +; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 2 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { switch i32 %c, label %cond_next [ diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll index f0ab9dd..25a0f93 100644 --- a/test/CodeGen/ARM/indirectbr.ll +++ b/test/CodeGen/ARM/indirectbr.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -relocation-model=pic -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -relocation-model=pic -mtriple=thumb-apple-darwin | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -relocation-model=pic -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -relocation-model=pic -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=THUMB ; RUN: llc < %s -relocation-model=static -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=THUMB2 @nextaddr = global i8* null ; <i8**> [#uses=2] diff --git a/test/CodeGen/ARM/ldr_frame.ll b/test/CodeGen/ARM/ldr_frame.ll index a3abdb6..f071b89 100644 --- a/test/CodeGen/ARM/ldr_frame.ll +++ b/test/CodeGen/ARM/ldr_frame.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | not grep mov +; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov define i32 @f1() { %buf = alloca [32 x i32], align 4 diff --git a/test/CodeGen/ARM/long.ll b/test/CodeGen/ARM/long.ll index e401dca..0f1c7be 100644 --- a/test/CodeGen/ARM/long.ll +++ b/test/CodeGen/ARM/long.ll @@ -14,14 +14,14 @@ entry: define i64 @f3() { ; CHECK: f3: -; CHECK: mvn r0, #2, #2 +; CHECK: mvn r0, #-2147483648 entry: ret i64 2147483647 } define i64 @f4() { ; CHECK: f4: -; CHECK: mov r0, #2, #2 +; CHECK: mov r0, #-2147483648 entry: ret i64 2147483648 } @@ -29,7 +29,7 @@ entry: define i64 @f5() { ; CHECK: f5: ; CHECK: mvn r0, #0 -; CHECK: mvn r1, #2, #2 +; CHECK: mvn r1, #-2147483648 entry: ret i64 9223372036854775807 } diff --git a/test/CodeGen/ARM/lsr-unfolded-offset.ll b/test/CodeGen/ARM/lsr-unfolded-offset.ll index e3e6eae..61b25bb 100644 --- a/test/CodeGen/ARM/lsr-unfolded-offset.ll +++ b/test/CodeGen/ARM/lsr-unfolded-offset.ll @@ -4,12 +4,13 @@ ; register pressure and therefore spilling. There is more room for improvement ; here. -; CHECK: sub sp, #{{32|24}} +; CHECK: sub sp, #{{32|28|24}} -; CHECK: ldr r{{.*}}, [sp, #4] -; CHECK-NEXT: ldr r{{.*}}, [sp, #16] -; CHECK-NEXT: ldr r{{.*}}, [sp, #12] -; CHECK-NEXT: adds +; CHECK: %for.inc +; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, # +; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, # +; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, # +; CHECK: add target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target triple = "thumbv7-apple-macosx10.7.0" diff --git a/test/CodeGen/ARM/phi.ll b/test/CodeGen/ARM/phi.ll index 29e17c0..dc1a95b 100644 --- a/test/CodeGen/ARM/phi.ll +++ b/test/CodeGen/ARM/phi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=arm < %s | FileCheck %s +; RUN: llc -march=arm -mattr=+v4t < %s | FileCheck %s ; <rdar://problem/8686347> define i32 @test1(i1 %a, i32* %b) { @@ -20,4 +20,4 @@ end: %r = load i32* %gep ; CHECK-NEXT: bx lr ret i32 %r -}
\ No newline at end of file +} diff --git a/test/CodeGen/ARM/prefetch.ll b/test/CodeGen/ARM/prefetch.ll index 250a34e..9c8ff2b 100644 --- a/test/CodeGen/ARM/prefetch.ll +++ b/test/CodeGen/ARM/prefetch.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld -; RUN: llc < %s -march=thumb -mattr=+v7a | FileCheck %s -check-prefix=THUMB2 -; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -march=thumb -mattr=+v7 | FileCheck %s -check-prefix=THUMB2 +; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s -check-prefix=ARM ; RUN: llc < %s -march=arm -mcpu=cortex-a9-mp | FileCheck %s -check-prefix=ARM-MP ; rdar://8601536 diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index d350937..3a19211 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -124,7 +124,7 @@ return1: return2: ; CHECK: %return2 ; CHECK: vadd.i32 -; CHECK: vmov {{q[0-9]+}}, {{q[0-9]+}} +; CHECK: vorr {{q[0-9]+}}, {{q[0-9]+}} ; CHECK-NOT: vmov ; CHECK: vst2.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}} %tmp100 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1] @@ -139,7 +139,7 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { ; CHECK: t5: ; CHECK: vldmia ; How can FileCheck match Q and D registers? We need a lisp interpreter. -; CHECK: vmov {{q[0-9]+}}, {{q[0-9]+}} +; CHECK: vorr {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} ; CHECK-NOT: vmov ; CHECK: vld2.16 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0] ; CHECK-NOT: vmov @@ -156,7 +156,7 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { ; CHECK: t6: ; CHECK: vldr.64 -; CHECK: vmov d[[D0:[0-9]+]], d[[D1:[0-9]+]] +; CHECK: vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]] ; CHECK-NEXT: vld2.8 {d[[D1]][1], d[[D0]][1]} %tmp1 = load <8 x i8>* %B ; <<8 x i8>> [#uses=2] %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2] @@ -172,7 +172,7 @@ entry: ; CHECK: vld2.32 ; CHECK: vst2.32 ; CHECK: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, -; CHECK: vmov q[[Q0:[0-9]+]], q[[Q1:[0-9]+]] +; CHECK: vorr q[[Q0:[0-9]+]], q[[Q1:[0-9]+]], q[[Q1:[0-9]+]] ; CHECK-NOT: vmov ; CHECK: vuzp.32 q[[Q1]], q[[Q0]] ; CHECK: vst1.32 @@ -272,8 +272,8 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { define arm_aapcs_vfpcc i32 @t10() nounwind { entry: ; CHECK: t10: -; CHECK: vmul.f32 q8, q8, d0[0] ; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3F000000 +; CHECK: vmul.f32 q8, q8, d0[0] ; CHECK: vadd.f32 q8, q8, q8 %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %1 = insertelement <4 x float> %0, float undef, i32 1 ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/ARM/section.ll b/test/CodeGen/ARM/section.ll index 7a566d4..2762056 100644 --- a/test/CodeGen/ARM/section.ll +++ b/test/CodeGen/ARM/section.ll @@ -1,7 +1,6 @@ -; RUN: llc < %s -mtriple=arm-linux | \ -; RUN: grep {__DTOR_END__:} -; RUN: llc < %s -mtriple=arm-linux | \ -; RUN: grep {\\.section.\\.dtors,"aw",.progbits} +; RUN: llc < %s -mtriple=arm-linux | FileCheck %s +; CHECK: .section .dtors,"aw",%progbits +; CHECK: __DTOR_END__: @__DTOR_END__ = internal global [1 x i32] zeroinitializer, section ".dtors" ; <[1 x i32]*> [#uses=0] diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll index 43f8a66..f43dde5 100644 --- a/test/CodeGen/ARM/select-imm.ll +++ b/test/CodeGen/ARM/select-imm.ll @@ -6,7 +6,7 @@ define i32 @t1(i32 %c) nounwind readnone { entry: ; ARM: t1: ; ARM: mov [[R1:r[0-9]+]], #101 -; ARM: orr [[R1b:r[0-9]+]], [[R1]], #1, #24 +; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256 ; ARM: movgt r0, #123 ; ARMT2: t1: @@ -27,7 +27,7 @@ entry: ; ARM: t2: ; ARM: mov r0, #123 ; ARM: movgt r0, #101 -; ARM: orrgt r0, r0, #1, #24 +; ARM: orrgt r0, r0, #256 ; ARMT2: t2: ; ARMT2: mov r0, #123 @@ -76,3 +76,39 @@ entry: %1 = select i1 %0, i32 4283826005, i32 %x ret i32 %1 } + +; rdar://9758317 +define i32 @t5(i32 %a) nounwind { +entry: +; ARM: t5: +; ARM-NOT: mov +; ARM: cmp r0, #1 +; ARM-NOT: mov +; ARM: movne r0, #0 + +; THUMB2: t5: +; THUMB2-NOT: mov +; THUMB2: cmp r0, #1 +; THUMB2: it ne +; THUMB2: movne r0, #0 + %cmp = icmp eq i32 %a, 1 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define i32 @t6(i32 %a) nounwind { +entry: +; ARM: t6: +; ARM-NOT: mov +; ARM: cmp r0, #0 +; ARM: movne r0, #1 + +; THUMB2: t6: +; THUMB2-NOT: mov +; THUMB2: cmp r0, #0 +; THUMB2: it ne +; THUMB2: movne r0, #1 + %tobool = icmp ne i32 %a, 0 + %lnot.ext = zext i1 %tobool to i32 + ret i32 %lnot.ext +} diff --git a/test/CodeGen/ARM/select_xform.ll b/test/CodeGen/ARM/select_xform.ll index 4211797..8a3133a 100644 --- a/test/CodeGen/ARM/select_xform.ll +++ b/test/CodeGen/ARM/select_xform.ll @@ -4,7 +4,7 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { ; ARM: t1: -; ARM: sub r0, r1, #6, #2 +; ARM: sub r0, r1, #-2147483647 ; ARM: movgt r0, r1 ; T2: t1: diff --git a/test/CodeGen/ARM/sub.ll b/test/CodeGen/ARM/sub.ll index 555b18e..06ea703 100644 --- a/test/CodeGen/ARM/sub.ll +++ b/test/CodeGen/ARM/sub.ll @@ -12,7 +12,7 @@ define i64 @f1(i64 %a) { ; 66846720 = 0x03fc0000 define i64 @f2(i64 %a) { ; CHECK: f2 -; CHECK: subs r0, r0, #255, #14 +; CHECK: subs r0, r0, #66846720 ; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 66846720 ret i64 %tmp diff --git a/test/CodeGen/ARM/truncstore-dag-combine.ll b/test/CodeGen/ARM/truncstore-dag-combine.ll index 2da08b6..5665440 100644 --- a/test/CodeGen/ARM/truncstore-dag-combine.ll +++ b/test/CodeGen/ARM/truncstore-dag-combine.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm | not grep orr -; RUN: llc < %s -march=arm | not grep mov +; RUN: llc < %s -march=arm -mattr=+v4t | not grep orr +; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov define void @bar(i8* %P, i16* %Q) { entry: |