diff options
Diffstat (limited to 'test/CodeGen/Hexagon')
122 files changed, 3017 insertions, 570 deletions
diff --git a/test/CodeGen/Hexagon/BranchPredict.ll b/test/CodeGen/Hexagon/BranchPredict.ll index 5d56449..0cd616b 100644 --- a/test/CodeGen/Hexagon/BranchPredict.ll +++ b/test/CodeGen/Hexagon/BranchPredict.ll @@ -53,7 +53,7 @@ return: ; preds = %if.else, %if.then define i32 @foo_bar(i32 %a, i16 signext %b) nounwind { ; CHECK: if{{ *}}(!cmp.eq(r{{[0-9]*}}.new, #0)) jump:nt entry: - %0 = load i32* @j, align 4 + %0 = load i32, i32* @j, align 4 %tobool = icmp eq i32 %0, 0 br i1 %tobool, label %if.else, label %if.then, !prof !0 diff --git a/test/CodeGen/Hexagon/absaddr-store.ll b/test/CodeGen/Hexagon/absaddr-store.ll index 5c2554d..3be4b1c 100644 --- a/test/CodeGen/Hexagon/absaddr-store.ll +++ b/test/CodeGen/Hexagon/absaddr-store.ll @@ -9,7 +9,7 @@ define zeroext i8 @absStoreByte() nounwind { ; CHECK: memb(##b){{ *}}={{ *}}r{{[0-9]+}} entry: - %0 = load i8* @b, align 1 + %0 = load i8, i8* @b, align 1 %conv = zext i8 %0 to i32 %mul = mul nsw i32 100, %conv %conv1 = trunc i32 %mul to i8 @@ -20,7 +20,7 @@ entry: define signext i16 @absStoreHalf() nounwind { ; CHECK: memh(##c){{ *}}={{ *}}r{{[0-9]+}} entry: - %0 = load i16* @c, align 2 + %0 = load i16, i16* @c, align 2 %conv = sext i16 %0 to i32 %mul = mul nsw i32 100, %conv %conv1 = trunc i32 %mul to i16 @@ -31,7 +31,7 @@ entry: define i32 @absStoreWord() nounwind { ; CHECK: memw(##a){{ *}}={{ *}}r{{[0-9]+}} entry: - %0 = load i32* @a, align 4 + %0 = load i32, i32* @a, align 4 %mul = mul nsw i32 100, %0 store i32 %mul, i32* @a, align 4 ret i32 %mul diff --git a/test/CodeGen/Hexagon/absimm.ll b/test/CodeGen/Hexagon/absimm.ll index b8f5edc..07adb3f 100644 --- a/test/CodeGen/Hexagon/absimm.ll +++ b/test/CodeGen/Hexagon/absimm.ll @@ -12,7 +12,7 @@ entry: define i32* @f2(i32* nocapture %i) nounwind { entry: ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(##786432) - %0 = load volatile i32* inttoptr (i32 786432 to i32*), align 262144 + %0 = load volatile i32, i32* inttoptr (i32 786432 to i32*), align 262144 %1 = inttoptr i32 %0 to i32* ret i32* %1 } diff --git a/test/CodeGen/Hexagon/always-ext.ll b/test/CodeGen/Hexagon/always-ext.ll index 93f4240..8b4b2f5 100644 --- a/test/CodeGen/Hexagon/always-ext.ll +++ b/test/CodeGen/Hexagon/always-ext.ll @@ -24,8 +24,8 @@ entry: br i1 undef, label %for.body.us, label %for.end for.body.us: ; preds = %entry - %0 = load %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111** null, align 4 - %1 = load i32* undef, align 4 + %0 = load %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111*, %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111** null, align 4 + %1 = load i32, i32* undef, align 4 %cmp.i.us = icmp slt i32 %1, 1024 br i1 %cmp.i.us, label %CuSuiteAdd.exit.us, label %cond.false6.i.us @@ -34,7 +34,7 @@ cond.false6.i.us: ; preds = %for.body.us unreachable CuSuiteAdd.exit.us: ; preds = %for.body.us - %arrayidx.i.us = getelementptr inbounds %struct.CuSuite.2.29.32.38.41.44.53.56.68.86.112* null, i32 0, i32 1, i32 %1 + %arrayidx.i.us = getelementptr inbounds %struct.CuSuite.2.29.32.38.41.44.53.56.68.86.112, %struct.CuSuite.2.29.32.38.41.44.53.56.68.86.112* null, i32 0, i32 1, i32 %1 store %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111* %0, %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111** %arrayidx.i.us, align 4 call void @llvm.trap() unreachable diff --git a/test/CodeGen/Hexagon/block-addr.ll b/test/CodeGen/Hexagon/block-addr.ll index dc0d6e6..902765e 100644 --- a/test/CodeGen/Hexagon/block-addr.ll +++ b/test/CodeGen/Hexagon/block-addr.ll @@ -10,7 +10,7 @@ entry: br label %while.body while.body: - %ret.0.load17 = load volatile i32* %ret, align 4 + %ret.0.load17 = load volatile i32, i32* %ret, align 4 switch i32 %ret.0.load17, label %label6 [ i32 0, label %label0 i32 1, label %label1 @@ -21,37 +21,37 @@ while.body: ] label0: - %ret.0.load18 = load volatile i32* %ret, align 4 + %ret.0.load18 = load volatile i32, i32* %ret, align 4 %inc = add nsw i32 %ret.0.load18, 1 store volatile i32 %inc, i32* %ret, align 4 br label %while.body label1: - %ret.0.load19 = load volatile i32* %ret, align 4 + %ret.0.load19 = load volatile i32, i32* %ret, align 4 %inc2 = add nsw i32 %ret.0.load19, 1 store volatile i32 %inc2, i32* %ret, align 4 br label %while.body label2: - %ret.0.load20 = load volatile i32* %ret, align 4 + %ret.0.load20 = load volatile i32, i32* %ret, align 4 %inc4 = add nsw i32 %ret.0.load20, 1 store volatile i32 %inc4, i32* %ret, align 4 br label %while.body label3: - %ret.0.load21 = load volatile i32* %ret, align 4 + %ret.0.load21 = load volatile i32, i32* %ret, align 4 %inc6 = add nsw i32 %ret.0.load21, 1 store volatile i32 %inc6, i32* %ret, align 4 br label %while.body label4: - %ret.0.load22 = load volatile i32* %ret, align 4 + %ret.0.load22 = load volatile i32, i32* %ret, align 4 %inc8 = add nsw i32 %ret.0.load22, 1 store volatile i32 %inc8, i32* %ret, align 4 br label %while.body label5: - %ret.0.load23 = load volatile i32* %ret, align 4 + %ret.0.load23 = load volatile i32, i32* %ret, align 4 %inc10 = add nsw i32 %ret.0.load23, 1 store volatile i32 %inc10, i32* %ret, align 4 br label %while.body diff --git a/test/CodeGen/Hexagon/brev_ld.ll b/test/CodeGen/Hexagon/brev_ld.ll new file mode 100644 index 0000000..12edb4c --- /dev/null +++ b/test/CodeGen/Hexagon/brev_ld.ll @@ -0,0 +1,140 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s +; Testing bitreverse load intrinsics: +; Q6_bitrev_load_update_D(inputLR, pDelay, nConvLength); +; Q6_bitrev_load_update_W(inputLR, pDelay, nConvLength); +; Q6_bitrev_load_update_H(inputLR, pDelay, nConvLength); +; Q6_bitrev_load_update_UH(inputLR, pDelay, nConvLength); +; Q6_bitrev_load_update_UB(inputLR, pDelay, nConvLength); +; Q6_bitrev_load_update_B(inputLR, pDelay, nConvLength); +; producing these instructions: +; r3:2 = memd(r0++m0:brev) +; r1 = memw(r0++m0:brev) +; r1 = memh(r0++m0:brev) +; r1 = memuh(r0++m0:brev) +; r1 = memub(r0++m0:brev) +; r1 = memb(r0++m0:brev) + +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +define i64 @foo(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %inputLR = alloca i64, align 8 + %conv = zext i16 %filtMemLen to i32 + %shr1 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %1 = bitcast i64* %inputLR to i8* + %sub = sub i32 13, %shr1 + %shl = shl i32 1, %sub +; CHECK: memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev) + %2 = call i8* @llvm.hexagon.brev.ldd(i8* %0, i8* %1, i32 %shl) + %3 = bitcast i8* %2 to i64* + %4 = load i64, i64* %3, align 8, !tbaa !0 + ret i64 %4 +} + +declare i8* @llvm.hexagon.brev.ldd(i8*, i8*, i32) nounwind + +define i32 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %inputLR = alloca i32, align 4 + %conv = zext i16 %filtMemLen to i32 + %shr1 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %1 = bitcast i32* %inputLR to i8* + %sub = sub i32 14, %shr1 + %shl = shl i32 1, %sub +; CHECK: memw(r{{[0-9]*}} ++ m{{[0-1]}}:brev) + %2 = call i8* @llvm.hexagon.brev.ldw(i8* %0, i8* %1, i32 %shl) + %3 = bitcast i8* %2 to i32* + %4 = load i32, i32* %3, align 4, !tbaa !2 + ret i32 %4 +} + +declare i8* @llvm.hexagon.brev.ldw(i8*, i8*, i32) nounwind + +define signext i16 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %inputLR = alloca i16, align 2 + %conv = zext i16 %filtMemLen to i32 + %shr1 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %1 = bitcast i16* %inputLR to i8* + %sub = sub i32 15, %shr1 + %shl = shl i32 1, %sub +; CHECK: memh(r{{[0-9]*}} ++ m0:brev) + %2 = call i8* @llvm.hexagon.brev.ldh(i8* %0, i8* %1, i32 %shl) + %3 = bitcast i8* %2 to i16* + %4 = load i16, i16* %3, align 2, !tbaa !3 + ret i16 %4 +} + +declare i8* @llvm.hexagon.brev.ldh(i8*, i8*, i32) nounwind + +define zeroext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %inputLR = alloca i16, align 2 + %conv = zext i16 %filtMemLen to i32 + %shr1 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %1 = bitcast i16* %inputLR to i8* + %sub = sub i32 15, %shr1 + %shl = shl i32 1, %sub +; CHECK: memuh(r{{[0-9]*}} ++ m0:brev) + %2 = call i8* @llvm.hexagon.brev.lduh(i8* %0, i8* %1, i32 %shl) + %3 = bitcast i8* %2 to i16* + %4 = load i16, i16* %3, align 2, !tbaa !3 + ret i16 %4 +} + +declare i8* @llvm.hexagon.brev.lduh(i8*, i8*, i32) nounwind + +define zeroext i8 @foo4(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %inputLR = alloca i8, align 1 + %conv = zext i16 %filtMemLen to i32 + %shr1 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %sub = sub nsw i32 16, %shr1 + %shl = shl i32 1, %sub +; CHECK: memub(r{{[0-9]*}} ++ m{{[0-1]}}:brev) + %1 = call i8* @llvm.hexagon.brev.ldub(i8* %0, i8* %inputLR, i32 %shl) + %2 = load i8, i8* %1, align 1, !tbaa !0 + ret i8 %2 +} + +declare i8* @llvm.hexagon.brev.ldub(i8*, i8*, i32) nounwind + +define zeroext i8 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %inputLR = alloca i8, align 1 + %conv = zext i16 %filtMemLen to i32 + %shr1 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %sub = sub nsw i32 16, %shr1 + %shl = shl i32 1, %sub +; CHECK: memb(r{{[0-9]*}} ++ m{{[0-1]}}:brev) + %1 = call i8* @llvm.hexagon.brev.ldb(i8* %0, i8* %inputLR, i32 %shl) + %2 = load i8, i8* %1, align 1, !tbaa !0 + ret i8 %2 +} + +declare i8* @llvm.hexagon.brev.ldb(i8*, i8*, i32) nounwind + +!0 = !{!"omnipotent char", !1} +!1 = !{!"Simple C/C++ TBAA"} +!2 = !{!"int", !0} +!3 = !{!"short", !0} diff --git a/test/CodeGen/Hexagon/brev_st.ll b/test/CodeGen/Hexagon/brev_st.ll new file mode 100644 index 0000000..b805791 --- /dev/null +++ b/test/CodeGen/Hexagon/brev_st.ll @@ -0,0 +1,112 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s +; Test these 5 bitreverse store intrinsics: +; Q6_bitrev_store_update_D(inputLR, pDelay, nConvLength); +; Q6_bitrev_store_update_W(inputLR, pDelay, nConvLength); +; Q6_bitrev_store_update_HL(inputLR, pDelay, nConvLength); +; Q6_bitrev_store_update_HH(inputLR, pDelay, nConvLength); +; Q6_bitrev_store_update_B(inputLR, pDelay, nConvLength); +; producing these instructions: +; memd(r0++m0:brev) = r1:0 +; memw(r0++m0:brev) = r0 +; memh(r0++m0:brev) = r3 +; memh(r0++m0:brev) = r3.h +; memb(r0++m0:brev) = r3 + +; ModuleID = 'brev_st.i' +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +define i64 @foo(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %conv = zext i16 %filtMemLen to i32 + %shr2 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %sub = sub i32 13, %shr2 + %shl = shl i32 1, %sub +; CHECK: memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev) + %1 = tail call i8* @llvm.hexagon.brev.std(i8* %0, i64 undef, i32 %shl) + %2 = bitcast i8* %1 to i64* + %3 = load i64, i64* %2, align 8, !tbaa !0 + ret i64 %3 +} + +declare i8* @llvm.hexagon.brev.std(i8*, i64, i32) nounwind + +define i32 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %conv = zext i16 %filtMemLen to i32 + %shr1 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %sub = sub i32 14, %shr1 + %shl = shl i32 1, %sub +; CHECK: memw(r{{[0-9]*}} ++ m{{[0-1]}}:brev) + %1 = tail call i8* @llvm.hexagon.brev.stw(i8* %0, i32 undef, i32 %shl) + %2 = bitcast i8* %1 to i32* + %3 = load i32, i32* %2, align 4, !tbaa !2 + ret i32 %3 +} + +declare i8* @llvm.hexagon.brev.stw(i8*, i32, i32) nounwind + +define signext i16 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %conv = zext i16 %filtMemLen to i32 + %shr2 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %sub = sub i32 15, %shr2 + %shl = shl i32 1, %sub +; CHECK: memh(r{{[0-9]*}} ++ m{{[0-1]}}:brev) + %1 = tail call i8* @llvm.hexagon.brev.sth(i8* %0, i32 0, i32 %shl) + %2 = bitcast i8* %1 to i16* + %3 = load i16, i16* %2, align 2, !tbaa !3 + ret i16 %3 +} + +declare i8* @llvm.hexagon.brev.sth(i8*, i32, i32) nounwind + +define signext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %conv = zext i16 %filtMemLen to i32 + %shr2 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %sub = sub i32 15, %shr2 + %shl = shl i32 1, %sub +; CHECK: memh(r{{[0-9]*}} ++ m{{[0-1]}}:brev){{ *}}={{ *}}r{{[0-9]*}}.h + %1 = tail call i8* @llvm.hexagon.brev.sthhi(i8* %0, i32 0, i32 %shl) + %2 = bitcast i8* %1 to i16* + %3 = load i16, i16* %2, align 2, !tbaa !3 + ret i16 %3 +} + +declare i8* @llvm.hexagon.brev.sthhi(i8*, i32, i32) nounwind + +define zeroext i8 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %conv = zext i16 %filtMemLen to i32 + %shr2 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %sub = sub nsw i32 16, %shr2 + ; CHECK: memb(r{{[0-9]*}} ++ m{{[0-1]}}:brev) + %shl = shl i32 1, %sub + %1 = tail call i8* @llvm.hexagon.brev.stb(i8* %0, i32 0, i32 %shl) + %2 = load i8, i8* %1, align 1, !tbaa !0 + ret i8 %2 +} + +declare i8* @llvm.hexagon.brev.stb(i8*, i32, i32) nounwind + +!0 = !{!"omnipotent char", !1} +!1 = !{!"Simple C/C++ TBAA"} +!2 = !{!"int", !0} +!3 = !{!"short", !0} diff --git a/test/CodeGen/Hexagon/cext-check.ll b/test/CodeGen/Hexagon/cext-check.ll index b7181d8..19b91c5 100644 --- a/test/CodeGen/Hexagon/cext-check.ll +++ b/test/CodeGen/Hexagon/cext-check.ll @@ -7,19 +7,19 @@ define i32 @cext_test1(i32* %a) nounwind { ; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}##4092) ; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300) entry: - %0 = load i32* %a, align 4 + %0 = load i32, i32* %a, align 4 %tobool = icmp ne i32 %0, 0 br i1 %tobool, label %if.then, label %if.end if.then: - %arrayidx1 = getelementptr inbounds i32* %a, i32 2000 - %1 = load i32* %arrayidx1, align 4 + %arrayidx1 = getelementptr inbounds i32, i32* %a, i32 2000 + %1 = load i32, i32* %arrayidx1, align 4 %add = add nsw i32 %1, 300000 br label %return if.end: - %arrayidx2 = getelementptr inbounds i32* %a, i32 1023 - %2 = load i32* %arrayidx2, align 4 + %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 1023 + %2 = load i32, i32* %arrayidx2, align 4 %add3 = add nsw i32 %2, 300 br label %return @@ -38,15 +38,15 @@ entry: br i1 %tobool, label %if.then, label %if.end if.then: - %arrayidx = getelementptr inbounds i8* %a, i32 1023 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %a, i32 1023 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 300000 br label %return if.end: - %arrayidx1 = getelementptr inbounds i8* %a, i32 1024 - %1 = load i8* %arrayidx1, align 1 + %arrayidx1 = getelementptr inbounds i8, i8* %a, i32 1024 + %1 = load i8, i8* %arrayidx1, align 1 %conv2 = zext i8 %1 to i32 %add3 = add nsw i32 %conv2, 6000 br label %return diff --git a/test/CodeGen/Hexagon/cext-valid-packet2.ll b/test/CodeGen/Hexagon/cext-valid-packet2.ll index 2788a6b..2eba743 100644 --- a/test/CodeGen/Hexagon/cext-valid-packet2.ll +++ b/test/CodeGen/Hexagon/cext-valid-packet2.ll @@ -10,31 +10,31 @@ define i32 @test(i32* nocapture %a, i32* nocapture %b, i32 %c) nounwind { entry: %add = add nsw i32 %c, 200002 - %0 = load i32* %a, align 4 + %0 = load i32, i32* %a, align 4 %add1 = add nsw i32 %0, 200000 - %arrayidx2 = getelementptr inbounds i32* %a, i32 3000 + %arrayidx2 = getelementptr inbounds i32, i32* %a, i32 3000 store i32 %add1, i32* %arrayidx2, align 4 - %1 = load i32* %b, align 4 + %1 = load i32, i32* %b, align 4 %add4 = add nsw i32 %1, 200001 - %arrayidx5 = getelementptr inbounds i32* %a, i32 1 + %arrayidx5 = getelementptr inbounds i32, i32* %a, i32 1 store i32 %add4, i32* %arrayidx5, align 4 - %arrayidx7 = getelementptr inbounds i32* %b, i32 1 - %2 = load i32* %arrayidx7, align 4 + %arrayidx7 = getelementptr inbounds i32, i32* %b, i32 1 + %2 = load i32, i32* %arrayidx7, align 4 %cmp = icmp sgt i32 %add4, %2 br i1 %cmp, label %if.then, label %if.else if.then: ; preds = %entry - %arrayidx8 = getelementptr inbounds i32* %a, i32 2 - %3 = load i32* %arrayidx8, align 4 - %arrayidx9 = getelementptr inbounds i32* %b, i32 2000 - %4 = load i32* %arrayidx9, align 4 + %arrayidx8 = getelementptr inbounds i32, i32* %a, i32 2 + %3 = load i32, i32* %arrayidx8, align 4 + %arrayidx9 = getelementptr inbounds i32, i32* %b, i32 2000 + %4 = load i32, i32* %arrayidx9, align 4 %sub = sub nsw i32 %3, %4 - %arrayidx10 = getelementptr inbounds i32* %a, i32 4000 + %arrayidx10 = getelementptr inbounds i32, i32* %a, i32 4000 store i32 %sub, i32* %arrayidx10, align 4 br label %if.end if.else: ; preds = %entry - %arrayidx11 = getelementptr inbounds i32* %b, i32 3200 + %arrayidx11 = getelementptr inbounds i32, i32* %b, i32 3200 store i32 %add, i32* %arrayidx11, align 4 br label %if.end diff --git a/test/CodeGen/Hexagon/circ_ld.ll b/test/CodeGen/Hexagon/circ_ld.ll new file mode 100644 index 0000000..6d37240 --- /dev/null +++ b/test/CodeGen/Hexagon/circ_ld.ll @@ -0,0 +1,135 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; Testing for these 6 variants of circular load: +; Q6_circ_load_update_B(inputLR, pDelay, -1, nConvLength, 4); +; Q6_circ_load_update_D(inputLR, pDelay, -1, nConvLength, 4); +; Q6_circ_load_update_H(inputLR, pDelay, -1, nConvLength, 4); +; Q6_circ_load_update_UB(inputLR, pDelay, -1, nConvLength, 4); +; Q6_circ_load_update_UH(inputLR, pDelay, -1, nConvLength, 4); +; Q6_circ_load_update_W(inputLR, pDelay, -1, nConvLength, 4); +; producing these: +; r0 = memb(r1++#-1:circ(m0)) +; r3:2 = memd(r1++#-8:circ(m0)) +; r0 = memh(r1++#-2:circ(m0)) +; r0 = memub(r1++#-1:circ(m0)) +; r0 = memuh(r1++#-2:circ(m0)) +; r0 = memw(r1++#-4:circ(m0)) + +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +define zeroext i8 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %inputLR = alloca i8, align 1 + %conv = zext i16 %filtMemLen to i32 + %shr1 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %or = or i32 %shr1, 33554432 +; CHECK: memb(r{{[0-9]*.}}++{{.}}#-1:circ(m{{[0-1]}})) + %1 = call i8* @llvm.hexagon.circ.ldb(i8* %0, i8* %inputLR, i32 %or, i32 -1) + %2 = load i8, i8* %1, align 1, !tbaa !0 + ret i8 %2 +} + +declare i8* @llvm.hexagon.circ.ldb(i8*, i8*, i32, i32) nounwind + +define i64 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %inputLR = alloca i64, align 8 + %conv = zext i16 %filtMemLen to i32 + %shr1 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %1 = bitcast i64* %inputLR to i8* + %shl = shl nuw nsw i32 %shr1, 3 + %or = or i32 %shl, 83886080 +; CHECK: memd(r{{[0-9]*.}}++{{.}}#-8:circ(m{{[0-1]}})) + %2 = call i8* @llvm.hexagon.circ.ldd(i8* %0, i8* %1, i32 %or, i32 -8) + %3 = bitcast i8* %2 to i64* + %4 = load i64, i64* %3, align 8, !tbaa !0 + ret i64 %4 +} + +declare i8* @llvm.hexagon.circ.ldd(i8*, i8*, i32, i32) nounwind + +define signext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %inputLR = alloca i16, align 2 + %conv = zext i16 %filtMemLen to i32 + %shr1 = and i32 %conv, 65534 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %1 = bitcast i16* %inputLR to i8* + %or = or i32 %shr1, 50331648 +; CHECK: memh(r{{[0-9]*.}}++{{.}}#-2:circ(m{{[0-1]}})) + %2 = call i8* @llvm.hexagon.circ.ldh(i8* %0, i8* %1, i32 %or, i32 -2) + %3 = bitcast i8* %2 to i16* + %4 = load i16, i16* %3, align 2, !tbaa !2 + ret i16 %4 +} + +declare i8* @llvm.hexagon.circ.ldh(i8*, i8*, i32, i32) nounwind + +define zeroext i8 @foo4(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %inputLR = alloca i8, align 1 + %conv = zext i16 %filtMemLen to i32 + %shr1 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %or = or i32 %shr1, 33554432 +; CHECK: memub(r{{[0-9]*.}}++{{.}}#-1:circ(m{{[0-1]}})) + %1 = call i8* @llvm.hexagon.circ.ldub(i8* %0, i8* %inputLR, i32 %or, i32 -1) + %2 = load i8, i8* %1, align 1, !tbaa !0 + ret i8 %2 +} + +declare i8* @llvm.hexagon.circ.ldub(i8*, i8*, i32, i32) nounwind + +define zeroext i16 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %inputLR = alloca i16, align 2 + %conv = zext i16 %filtMemLen to i32 + %shr1 = and i32 %conv, 65534 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %1 = bitcast i16* %inputLR to i8* + %or = or i32 %shr1, 50331648 +; CHECK: memuh(r{{[0-9]*.}}++{{.}}#-2:circ(m{{[0-1]}})) + %2 = call i8* @llvm.hexagon.circ.lduh(i8* %0, i8* %1, i32 %or, i32 -2) + %3 = bitcast i8* %2 to i16* + %4 = load i16, i16* %3, align 2, !tbaa !2 + ret i16 %4 +} + +declare i8* @llvm.hexagon.circ.lduh(i8*, i8*, i32, i32) nounwind + +define i32 @foo6(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %inputLR = alloca i32, align 4 + %conv = zext i16 %filtMemLen to i32 + %shr1 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %1 = bitcast i32* %inputLR to i8* + %shl = shl nuw nsw i32 %shr1, 2 + %or = or i32 %shl, 67108864 +; CHECK: memw(r{{[0-9]*.}}++{{.}}#-4:circ(m{{[0-1]}})) + %2 = call i8* @llvm.hexagon.circ.ldw(i8* %0, i8* %1, i32 %or, i32 -4) + %3 = bitcast i8* %2 to i32* + %4 = load i32, i32* %3, align 4, !tbaa !3 + ret i32 %4 +} + +declare i8* @llvm.hexagon.circ.ldw(i8*, i8*, i32, i32) nounwind + +!0 = !{!"omnipotent char", !1} +!1 = !{!"Simple C/C++ TBAA"} +!2 = !{!"short", !0} +!3 = !{!"int", !0} diff --git a/test/CodeGen/Hexagon/circ_ldd_bug.ll b/test/CodeGen/Hexagon/circ_ldd_bug.ll new file mode 100644 index 0000000..d15b5c9 --- /dev/null +++ b/test/CodeGen/Hexagon/circ_ldd_bug.ll @@ -0,0 +1,255 @@ +; RUN: llc -O2 < %s +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +; We would fail on this file with: +; Unimplemented +; UNREACHABLE executed at llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp:615! +; This happened because after unrolling a loop with a ldd_circ instruction we +; would have several TFCR and ldd_circ instruction sequences. +; %vreg0 (CRRegs) = TFCR %vreg0 (IntRegs) +; = ldd_circ( , , vreg0) +; %vreg1 (CRRegs) = TFCR %vreg1 (IntRegs) +; = ldd_circ( , , vreg0) +; The scheduler would move the CRRegs to the top of the loop. The allocator +; would try to spill the CRRegs after running out of them. We don't have code to +; spill CRRegs and the above assertion would be triggered. +declare i8* @llvm.hexagon.circ.ldd(i8*, i8*, i32, i32) nounwind + +define i32 @test(i16 zeroext %var0, i16* %var1, i16 signext %var2, i16* nocapture %var3) nounwind { +entry: + %var4 = alloca i64, align 8 + %conv = zext i16 %var0 to i32 + %shr5 = lshr i32 %conv, 1 + %idxprom = sext i16 %var2 to i32 + %arrayidx = getelementptr inbounds i16, i16* %var1, i32 %idxprom + %0 = bitcast i16* %var3 to i64* + %1 = load i64, i64* %0, align 8, !tbaa !1 + %2 = bitcast i16* %arrayidx to i8* + %3 = bitcast i64* %var4 to i8* + %shl = shl nuw nsw i32 %shr5, 3 + %or = or i32 %shl, 83886080 + %4 = call i8* @llvm.hexagon.circ.ldd(i8* %2, i8* %3, i32 %or, i32 -8) + %sub = add nsw i32 %shr5, -1 + %cmp6 = icmp sgt i32 %sub, 0 + %5 = load i64, i64* %var4, align 8, !tbaa !1 + %6 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 0, i64 %1, i64 %5) + br i1 %cmp6, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + %incdec.ptr = getelementptr inbounds i16, i16* %var3, i32 4 + %7 = bitcast i16* %incdec.ptr to i64* + %8 = zext i16 %var0 to i32 + %9 = lshr i32 %8, 1 + %10 = add i32 %9, -1 + %xtraiter = urem i32 %10, 8 + %lcmp = icmp ne i32 %xtraiter, 0 + br i1 %lcmp, label %unr.cmp60, label %for.body.lr.ph.split.split + +unr.cmp60: ; preds = %for.body.lr.ph + %un.tmp61 = icmp eq i32 %xtraiter, 1 + br i1 %un.tmp61, label %for.body.unr53, label %unr.cmp51 + +unr.cmp51: ; preds = %unr.cmp60 + %un.tmp52 = icmp eq i32 %xtraiter, 2 + br i1 %un.tmp52, label %for.body.unr44, label %unr.cmp42 + +unr.cmp42: ; preds = %unr.cmp51 + %un.tmp43 = icmp eq i32 %xtraiter, 3 + br i1 %un.tmp43, label %for.body.unr35, label %unr.cmp33 + +unr.cmp33: ; preds = %unr.cmp42 + %un.tmp34 = icmp eq i32 %xtraiter, 4 + br i1 %un.tmp34, label %for.body.unr26, label %unr.cmp24 + +unr.cmp24: ; preds = %unr.cmp33 + %un.tmp25 = icmp eq i32 %xtraiter, 5 + br i1 %un.tmp25, label %for.body.unr17, label %unr.cmp + +unr.cmp: ; preds = %unr.cmp24 + %un.tmp = icmp eq i32 %xtraiter, 6 + br i1 %un.tmp, label %for.body.unr13, label %for.body.unr + +for.body.unr: ; preds = %unr.cmp + %11 = call i8* @llvm.hexagon.circ.ldd(i8* %4, i8* %3, i32 %or, i32 -8) + %12 = load i64, i64* %7, align 8, !tbaa !1 + %inc.unr = add nsw i32 0, 1 + %incdec.ptr4.unr = getelementptr inbounds i64, i64* %7, i32 1 + %cmp.unr = icmp slt i32 %inc.unr, %sub + %13 = load i64, i64* %var4, align 8, !tbaa !1 + %14 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %6, i64 %12, i64 %13) + br label %for.body.unr13 + +for.body.unr13: ; preds = %for.body.unr, %unr.cmp + %15 = phi i64 [ %6, %unr.cmp ], [ %14, %for.body.unr ] + %pvar6.09.unr = phi i64* [ %7, %unr.cmp ], [ %incdec.ptr4.unr, %for.body.unr ] + %var8.0.in8.unr = phi i8* [ %4, %unr.cmp ], [ %11, %for.body.unr ] + %i.07.unr = phi i32 [ 0, %unr.cmp ], [ %inc.unr, %for.body.unr ] + %16 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr, i8* %3, i32 %or, i32 -8) + %17 = load i64, i64* %pvar6.09.unr, align 8, !tbaa !1 + %inc.unr14 = add nsw i32 %i.07.unr, 1 + %incdec.ptr4.unr15 = getelementptr inbounds i64, i64* %pvar6.09.unr, i32 1 + %cmp.unr16 = icmp slt i32 %inc.unr14, %sub + %18 = load i64, i64* %var4, align 8, !tbaa !1 + %19 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %15, i64 %17, i64 %18) + br label %for.body.unr17 + +for.body.unr17: ; preds = %for.body.unr13, %unr.cmp24 + %20 = phi i64 [ %6, %unr.cmp24 ], [ %19, %for.body.unr13 ] + %pvar6.09.unr18 = phi i64* [ %7, %unr.cmp24 ], [ %incdec.ptr4.unr15, %for.body.unr13 ] + %var8.0.in8.unr19 = phi i8* [ %4, %unr.cmp24 ], [ %16, %for.body.unr13 ] + %i.07.unr20 = phi i32 [ 0, %unr.cmp24 ], [ %inc.unr14, %for.body.unr13 ] + %21 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr19, i8* %3, i32 %or, i32 -8) + %22 = load i64, i64* %pvar6.09.unr18, align 8, !tbaa !1 + %inc.unr21 = add nsw i32 %i.07.unr20, 1 + %incdec.ptr4.unr22 = getelementptr inbounds i64, i64* %pvar6.09.unr18, i32 1 + %cmp.unr23 = icmp slt i32 %inc.unr21, %sub + %23 = load i64, i64* %var4, align 8, !tbaa !1 + %24 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %20, i64 %22, i64 %23) + br label %for.body.unr26 + +for.body.unr26: ; preds = %for.body.unr17, %unr.cmp33 + %25 = phi i64 [ %6, %unr.cmp33 ], [ %24, %for.body.unr17 ] + %pvar6.09.unr27 = phi i64* [ %7, %unr.cmp33 ], [ %incdec.ptr4.unr22, %for.body.unr17 ] + %var8.0.in8.unr28 = phi i8* [ %4, %unr.cmp33 ], [ %21, %for.body.unr17 ] + %i.07.unr29 = phi i32 [ 0, %unr.cmp33 ], [ %inc.unr21, %for.body.unr17 ] + %26 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr28, i8* %3, i32 %or, i32 -8) + %27 = load i64, i64* %pvar6.09.unr27, align 8, !tbaa !1 + %inc.unr30 = add nsw i32 %i.07.unr29, 1 + %incdec.ptr4.unr31 = getelementptr inbounds i64, i64* %pvar6.09.unr27, i32 1 + %cmp.unr32 = icmp slt i32 %inc.unr30, %sub + %28 = load i64, i64* %var4, align 8, !tbaa !1 + %29 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %25, i64 %27, i64 %28) + br label %for.body.unr35 + +for.body.unr35: ; preds = %for.body.unr26, %unr.cmp42 + %30 = phi i64 [ %6, %unr.cmp42 ], [ %29, %for.body.unr26 ] + %pvar6.09.unr36 = phi i64* [ %7, %unr.cmp42 ], [ %incdec.ptr4.unr31, %for.body.unr26 ] + %var8.0.in8.unr37 = phi i8* [ %4, %unr.cmp42 ], [ %26, %for.body.unr26 ] + %i.07.unr38 = phi i32 [ 0, %unr.cmp42 ], [ %inc.unr30, %for.body.unr26 ] + %31 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr37, i8* %3, i32 %or, i32 -8) + %32 = load i64, i64* %pvar6.09.unr36, align 8, !tbaa !1 + %inc.unr39 = add nsw i32 %i.07.unr38, 1 + %incdec.ptr4.unr40 = getelementptr inbounds i64, i64* %pvar6.09.unr36, i32 1 + %cmp.unr41 = icmp slt i32 %inc.unr39, %sub + %33 = load i64, i64* %var4, align 8, !tbaa !1 + %34 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %30, i64 %32, i64 %33) + br label %for.body.unr44 + +for.body.unr44: ; preds = %for.body.unr35, %unr.cmp51 + %35 = phi i64 [ %6, %unr.cmp51 ], [ %34, %for.body.unr35 ] + %pvar6.09.unr45 = phi i64* [ %7, %unr.cmp51 ], [ %incdec.ptr4.unr40, %for.body.unr35 ] + %var8.0.in8.unr46 = phi i8* [ %4, %unr.cmp51 ], [ %31, %for.body.unr35 ] + %i.07.unr47 = phi i32 [ 0, %unr.cmp51 ], [ %inc.unr39, %for.body.unr35 ] + %36 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr46, i8* %3, i32 %or, i32 -8) + %37 = load i64, i64* %pvar6.09.unr45, align 8, !tbaa !1 + %inc.unr48 = add nsw i32 %i.07.unr47, 1 + %incdec.ptr4.unr49 = getelementptr inbounds i64, i64* %pvar6.09.unr45, i32 1 + %cmp.unr50 = icmp slt i32 %inc.unr48, %sub + %38 = load i64, i64* %var4, align 8, !tbaa !1 + %39 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %35, i64 %37, i64 %38) + br label %for.body.unr53 + +for.body.unr53: ; preds = %for.body.unr44, %unr.cmp60 + %40 = phi i64 [ %6, %unr.cmp60 ], [ %39, %for.body.unr44 ] + %pvar6.09.unr54 = phi i64* [ %7, %unr.cmp60 ], [ %incdec.ptr4.unr49, %for.body.unr44 ] + %var8.0.in8.unr55 = phi i8* [ %4, %unr.cmp60 ], [ %36, %for.body.unr44 ] + %i.07.unr56 = phi i32 [ 0, %unr.cmp60 ], [ %inc.unr48, %for.body.unr44 ] + %41 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8.unr55, i8* %3, i32 %or, i32 -8) + %42 = load i64, i64* %pvar6.09.unr54, align 8, !tbaa !1 + %inc.unr57 = add nsw i32 %i.07.unr56, 1 + %incdec.ptr4.unr58 = getelementptr inbounds i64, i64* %pvar6.09.unr54, i32 1 + %cmp.unr59 = icmp slt i32 %inc.unr57, %sub + %43 = load i64, i64* %var4, align 8, !tbaa !1 + %44 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %40, i64 %42, i64 %43) + br label %for.body.lr.ph.split + +for.body.lr.ph.split: ; preds = %for.body.unr53 + %45 = icmp ult i32 %10, 8 + br i1 %45, label %for.end.loopexit, label %for.body.lr.ph.split.split + +for.body.lr.ph.split.split: ; preds = %for.body.lr.ph.split, %for.body.lr.ph + %.unr = phi i64 [ %44, %for.body.lr.ph.split ], [ %6, %for.body.lr.ph ] + %pvar6.09.unr62 = phi i64* [ %incdec.ptr4.unr58, %for.body.lr.ph.split ], [ %7, %for.body.lr.ph ] + %var8.0.in8.unr63 = phi i8* [ %41, %for.body.lr.ph.split ], [ %4, %for.body.lr.ph ] + %i.07.unr64 = phi i32 [ %inc.unr57, %for.body.lr.ph.split ], [ 0, %for.body.lr.ph ] + %.lcssa12.unr = phi i64 [ %44, %for.body.lr.ph.split ], [ 0, %for.body.lr.ph ] + br label %for.body + +for.body: ; preds = %for.body, %for.body.lr.ph.split.split + %46 = phi i64 [ %.unr, %for.body.lr.ph.split.split ], [ %78, %for.body ] + %pvar6.09 = phi i64* [ %pvar6.09.unr62, %for.body.lr.ph.split.split ], [ %scevgep71, %for.body ] + %var8.0.in8 = phi i8* [ %var8.0.in8.unr63, %for.body.lr.ph.split.split ], [ %75, %for.body ] + %i.07 = phi i32 [ %i.07.unr64, %for.body.lr.ph.split.split ], [ %inc.7, %for.body ] + %47 = call i8* @llvm.hexagon.circ.ldd(i8* %var8.0.in8, i8* %3, i32 %or, i32 -8) + %48 = load i64, i64* %pvar6.09, align 8, !tbaa !1 + %inc = add nsw i32 %i.07, 1 + %49 = load i64, i64* %var4, align 8, !tbaa !1 + %50 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %46, i64 %48, i64 %49) + %51 = call i8* @llvm.hexagon.circ.ldd(i8* %47, i8* %3, i32 %or, i32 -8) + %scevgep = getelementptr i64, i64* %pvar6.09, i32 1 + %52 = load i64, i64* %scevgep, align 8, !tbaa !1 + %inc.1 = add nsw i32 %inc, 1 + %53 = load i64, i64* %var4, align 8, !tbaa !1 + %54 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %50, i64 %52, i64 %53) + %55 = call i8* @llvm.hexagon.circ.ldd(i8* %51, i8* %3, i32 %or, i32 -8) + %scevgep65 = getelementptr i64, i64* %scevgep, i32 1 + %56 = load i64, i64* %scevgep65, align 8, !tbaa !1 + %inc.2 = add nsw i32 %inc.1, 1 + %57 = load i64, i64* %var4, align 8, !tbaa !1 + %58 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %54, i64 %56, i64 %57) + %59 = call i8* @llvm.hexagon.circ.ldd(i8* %55, i8* %3, i32 %or, i32 -8) + %scevgep66 = getelementptr i64, i64* %scevgep65, i32 1 + %60 = load i64, i64* %scevgep66, align 8, !tbaa !1 + %inc.3 = add nsw i32 %inc.2, 1 + %61 = load i64, i64* %var4, align 8, !tbaa !1 + %62 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %58, i64 %60, i64 %61) + %63 = call i8* @llvm.hexagon.circ.ldd(i8* %59, i8* %3, i32 %or, i32 -8) + %scevgep67 = getelementptr i64, i64* %scevgep66, i32 1 + %64 = load i64, i64* %scevgep67, align 8, !tbaa !1 + %inc.4 = add nsw i32 %inc.3, 1 + %65 = load i64, i64* %var4, align 8, !tbaa !1 + %66 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %62, i64 %64, i64 %65) + %67 = call i8* @llvm.hexagon.circ.ldd(i8* %63, i8* %3, i32 %or, i32 -8) + %scevgep68 = getelementptr i64, i64* %scevgep67, i32 1 + %68 = load i64, i64* %scevgep68, align 8, !tbaa !1 + %inc.5 = add nsw i32 %inc.4, 1 + %69 = load i64, i64* %var4, align 8, !tbaa !1 + %70 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %66, i64 %68, i64 %69) + %71 = call i8* @llvm.hexagon.circ.ldd(i8* %67, i8* %3, i32 %or, i32 -8) + %scevgep69 = getelementptr i64, i64* %scevgep68, i32 1 + %72 = load i64, i64* %scevgep69, align 8, !tbaa !1 + %inc.6 = add nsw i32 %inc.5, 1 + %73 = load i64, i64* %var4, align 8, !tbaa !1 + %74 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %70, i64 %72, i64 %73) + %75 = call i8* @llvm.hexagon.circ.ldd(i8* %71, i8* %3, i32 %or, i32 -8) + %scevgep70 = getelementptr i64, i64* %scevgep69, i32 1 + %76 = load i64, i64* %scevgep70, align 8, !tbaa !1 + %inc.7 = add nsw i32 %inc.6, 1 + %77 = load i64, i64* %var4, align 8, !tbaa !1 + %78 = call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %74, i64 %76, i64 %77) + %cmp.7 = icmp slt i32 %inc.7, %sub + %scevgep71 = getelementptr i64, i64* %scevgep70, i32 1 + br i1 %cmp.7, label %for.body, label %for.end.loopexit.unr-lcssa + +for.end.loopexit.unr-lcssa: ; preds = %for.body + %.lcssa12.ph = phi i64 [ %78, %for.body ] + br label %for.end.loopexit + +for.end.loopexit: ; preds = %for.end.loopexit.unr-lcssa, %for.body.lr.ph.split + %.lcssa12 = phi i64 [ %44, %for.body.lr.ph.split ], [ %.lcssa12.ph, %for.end.loopexit.unr-lcssa ] + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry + %.lcssa = phi i64 [ %6, %entry ], [ %.lcssa12, %for.end.loopexit ] + %79 = call i32 @llvm.hexagon.S2.vrndpackwhs(i64 %.lcssa) + ret i32 %79 +} + +declare i64 @llvm.hexagon.M2.vdmacs.s1(i64, i64, i64) nounwind readnone + +declare i32 @llvm.hexagon.S2.vrndpackwhs(i64) nounwind readnone + +!0 = !{!"long long", !1} +!1 = !{!"omnipotent char", !2} +!2 = !{!"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/circ_ldw.ll b/test/CodeGen/Hexagon/circ_ldw.ll new file mode 100644 index 0000000..4511a9c --- /dev/null +++ b/test/CodeGen/Hexagon/circ_ldw.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; CHECK: r{{[0-9]*}} = memw(r{{[0-9]*.}}++{{.}}#-4:circ(m0)) + + +%union.vect64 = type { i64 } +%union.vect32 = type { i32 } + +define i32* @HallowedBeThyName(%union.vect64* nocapture %pRx, %union.vect32* %pLut, %union.vect64* nocapture %pOut, i64 %dc.coerce, i32 %shift, i32 %numSamples) nounwind { +entry: + %vLutNext = alloca i32, align 4 + %0 = bitcast %union.vect32* %pLut to i8* + %1 = bitcast i32* %vLutNext to i8* + %2 = call i8* @llvm.hexagon.circ.ldw(i8* %0, i8* %1, i32 83886144, i32 -4) + %3 = bitcast i8* %2 to i32* + ret i32* %3 +} + +declare i8* @llvm.hexagon.circ.ldw(i8*, i8*, i32, i32) nounwind diff --git a/test/CodeGen/Hexagon/circ_st.ll b/test/CodeGen/Hexagon/circ_st.ll new file mode 100644 index 0000000..244ca3b --- /dev/null +++ b/test/CodeGen/Hexagon/circ_st.ll @@ -0,0 +1,108 @@ +; RUN: llc -march=hexagon -verify-machineinstrs=true < %s | FileCheck %s +; Testing for these 5 variants of circular store: +; Q6_circ_store_update_B(inputLR, pDelay, -1, nConvLength, 4); +; Q6_circ_store_update_D(inputLR, pDelay, -1, nConvLength, 4); +; Q6_circ_store_update_HL(inputLR, pDelay, -1, nConvLength, 4); +; Q6_circ_store_update_HH(inputLR, pDelay, -1, nConvLength, 4); +; Q6_circ_store_update_W(inputLR, pDelay, -1, nConvLength, 4); +; producing these +; memb(r1++#-1:circ(m0)) = r3 +; memd(r1++#-8:circ(m0)) = r1:0 +; memh(r1++#-2:circ(m0)) = r3 +; memh(r1++#-2:circ(m0)) = r3.h +; memw(r1++#-4:circ(m0)) = r0 + +; ModuleID = 'circ_st.i' +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +define zeroext i8 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %conv = zext i16 %filtMemLen to i32 + %shr2 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %or = or i32 %shr2, 33554432 +; CHECK: memb(r{{[0-9]*}}{{.}}++{{.}}#-1:circ(m{{[0-1]}})) + %1 = tail call i8* @llvm.hexagon.circ.stb(i8* %0, i32 0, i32 %or, i32 -1) + %2 = load i8, i8* %1, align 1, !tbaa !0 + ret i8 %2 +} + +declare i8* @llvm.hexagon.circ.stb(i8*, i32, i32, i32) nounwind + +define i64 @foo2(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %conv = zext i16 %filtMemLen to i32 + %shr1 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %shl = shl nuw nsw i32 %shr1, 3 + %or = or i32 %shl, 83886080 +; CHECK: memd(r{{[0-9]*}}{{.}}++{{.}}#-8:circ(m{{[0-1]}})) + %1 = tail call i8* @llvm.hexagon.circ.std(i8* %0, i64 undef, i32 %or, i32 -8) + %2 = bitcast i8* %1 to i64* + %3 = load i64, i64* %2, align 8, !tbaa !0 + ret i64 %3 +} + +declare i8* @llvm.hexagon.circ.std(i8*, i64, i32, i32) nounwind + +define signext i16 @foo3(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %conv = zext i16 %filtMemLen to i32 + %shr2 = and i32 %conv, 65534 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %or = or i32 %shr2, 50331648 +; CHECK: memh(r{{[0-9]*}}{{.}}++{{.}}#-2:circ(m{{[0-1]}})) + %1 = tail call i8* @llvm.hexagon.circ.sth(i8* %0, i32 0, i32 %or, i32 -2) + %2 = bitcast i8* %1 to i16* + %3 = load i16, i16* %2, align 2, !tbaa !2 + ret i16 %3 +} + +declare i8* @llvm.hexagon.circ.sth(i8*, i32, i32, i32) nounwind + +define signext i16 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %conv = zext i16 %filtMemLen to i32 + %shr2 = and i32 %conv, 65534 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %or = or i32 %shr2, 50331648 +; CHECK: memh(r{{[0-9]*}}{{.}}++{{.}}#-2:circ(m{{[0-1]}})){{ *}}={{ *}}r{{[0-9]*}}.h + %1 = tail call i8* @llvm.hexagon.circ.sthhi(i8* %0, i32 0, i32 %or, i32 -2) + %2 = bitcast i8* %1 to i16* + %3 = load i16, i16* %2, align 2, !tbaa !2 + ret i16 %3 +} + +declare i8* @llvm.hexagon.circ.sthhi(i8*, i32, i32, i32) nounwind + +define i32 @foo6(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +entry: + %conv = zext i16 %filtMemLen to i32 + %shr1 = lshr i32 %conv, 1 + %idxprom = sext i16 %filtMemIndex to i32 + %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom + %0 = bitcast i16* %arrayidx to i8* + %shl = shl nuw nsw i32 %shr1, 2 + %or = or i32 %shl, 67108864 +; CHECK: memw(r{{[0-9]*}}{{.}}++{{.}}#-4:circ(m{{[0-1]}})) + %1 = tail call i8* @llvm.hexagon.circ.stw(i8* %0, i32 undef, i32 %or, i32 -4) + %2 = bitcast i8* %1 to i32* + %3 = load i32, i32* %2, align 4, !tbaa !3 + ret i32 %3 +} + +declare i8* @llvm.hexagon.circ.stw(i8*, i32, i32, i32) nounwind + +!0 = !{!"omnipotent char", !1} +!1 = !{!"Simple C/C++ TBAA"} +!2 = !{!"short", !0} +!3 = !{!"int", !0} diff --git a/test/CodeGen/Hexagon/clr_set_toggle.ll b/test/CodeGen/Hexagon/clr_set_toggle.ll new file mode 100644 index 0000000..87c5295 --- /dev/null +++ b/test/CodeGen/Hexagon/clr_set_toggle.ll @@ -0,0 +1,160 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; Optimized bitwise operations. + +define i32 @my_clrbit(i32 %x) nounwind { +entry: +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31) + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %0 = load i32, i32* %x.addr, align 4 + %and = and i32 %0, 2147483647 + ret i32 %and +} + +define i64 @my_clrbit2(i64 %x) nounwind { +entry: +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31) + %x.addr = alloca i64, align 8 + store i64 %x, i64* %x.addr, align 8 + %0 = load i64, i64* %x.addr, align 8 + %and = and i64 %0, -2147483649 + ret i64 %and +} + +define i64 @my_clrbit3(i64 %x) nounwind { +entry: +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31) + %x.addr = alloca i64, align 8 + store i64 %x, i64* %x.addr, align 8 + %0 = load i64, i64* %x.addr, align 8 + %and = and i64 %0, 9223372036854775807 + ret i64 %and +} + +define i32 @my_clrbit4(i32 %x) nounwind { +entry: +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13) + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %0 = load i32, i32* %x.addr, align 4 + %and = and i32 %0, -8193 + ret i32 %and +} + +define i64 @my_clrbit5(i64 %x) nounwind { +entry: +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13) + %x.addr = alloca i64, align 8 + store i64 %x, i64* %x.addr, align 8 + %0 = load i64, i64* %x.addr, align 8 + %and = and i64 %0, -8193 + ret i64 %and +} + +define i64 @my_clrbit6(i64 %x) nounwind { +entry: +; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #27) + %x.addr = alloca i64, align 8 + store i64 %x, i64* %x.addr, align 8 + %0 = load i64, i64* %x.addr, align 8 + %and = and i64 %0, -576460752303423489 + ret i64 %and +} + +define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind { +entry: +; CHECK: memh(r{{[0-9]+}}+#0){{ *}}={{ *}}setbit(#15) + %crc.addr = alloca i16, align 2 + store i16 %crc, i16* %crc.addr, align 2 + %0 = load i16, i16* %crc.addr, align 2 + %conv = zext i16 %0 to i32 + %or = or i32 %conv, 32768 + %conv1 = trunc i32 %or to i16 + store i16 %conv1, i16* %crc.addr, align 2 + %1 = load i16, i16* %crc.addr, align 2 + ret i16 %1 +} + +define i32 @my_setbit2(i32 %x) nounwind { +entry: +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15) + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %0 = load i32, i32* %x.addr, align 4 + %or = or i32 %0, 32768 + ret i32 %or +} + +define i64 @my_setbit3(i64 %x) nounwind { +entry: +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15) + %x.addr = alloca i64, align 8 + store i64 %x, i64* %x.addr, align 8 + %0 = load i64, i64* %x.addr, align 8 + %or = or i64 %0, 32768 + ret i64 %or +} + +define i32 @my_setbit4(i32 %x) nounwind { +entry: +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #31) + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %0 = load i32, i32* %x.addr, align 4 + %or = or i32 %0, -2147483648 + ret i32 %or +} + +define i64 @my_setbit5(i64 %x) nounwind { +entry: +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #13) + %x.addr = alloca i64, align 8 + store i64 %x, i64* %x.addr, align 8 + %0 = load i64, i64* %x.addr, align 8 + %or = or i64 %0, 35184372088832 + ret i64 %or +} + +define zeroext i16 @my_togglebit(i16 zeroext %crc) nounwind { +entry: +; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15) + %crc.addr = alloca i16, align 2 + store i16 %crc, i16* %crc.addr, align 2 + %0 = load i16, i16* %crc.addr, align 2 + %conv = zext i16 %0 to i32 + %xor = xor i32 %conv, 32768 + %conv1 = trunc i32 %xor to i16 + store i16 %conv1, i16* %crc.addr, align 2 + %1 = load i16, i16* %crc.addr, align 2 + ret i16 %1 +} + +define i32 @my_togglebit2(i32 %x) nounwind { +entry: +; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15) + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %0 = load i32, i32* %x.addr, align 4 + %xor = xor i32 %0, 32768 + ret i32 %xor +} + +define i64 @my_togglebit3(i64 %x) nounwind { +entry: +; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15) + %x.addr = alloca i64, align 8 + store i64 %x, i64* %x.addr, align 8 + %0 = load i64, i64* %x.addr, align 8 + %xor = xor i64 %0, 32768 + ret i64 %xor +} + +define i64 @my_togglebit4(i64 %x) nounwind { +entry: +; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #20) + %x.addr = alloca i64, align 8 + store i64 %x, i64* %x.addr, align 8 + %0 = load i64, i64* %x.addr, align 8 + %xor = xor i64 %0, 4503599627370496 + ret i64 %xor +} diff --git a/test/CodeGen/Hexagon/cmp_pred.ll b/test/CodeGen/Hexagon/cmp_pred.ll index 37db3b4..39549a1 100644 --- a/test/CodeGen/Hexagon/cmp_pred.ll +++ b/test/CodeGen/Hexagon/cmp_pred.ll @@ -1,3 +1,4 @@ +; XFAIL: ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Generate various cmpb instruction followed by if (p0) .. if (!p0)... target triple = "hexagon" diff --git a/test/CodeGen/Hexagon/cmp_pred2.ll b/test/CodeGen/Hexagon/cmp_pred2.ll index a20b9f0..28f3e1b 100644 --- a/test/CodeGen/Hexagon/cmp_pred2.ll +++ b/test/CodeGen/Hexagon/cmp_pred2.ll @@ -11,7 +11,7 @@ entry: br i1 %cmp, label %if.then, label %entry.if.end_crit_edge entry.if.end_crit_edge: - %.pre = load i32* @c, align 4 + %.pre = load i32, i32* @c, align 4 br label %if.end if.then: @@ -32,7 +32,7 @@ entry: br i1 %cmp, label %entry.if.end_crit_edge, label %if.then entry.if.end_crit_edge: - %.pre = load i32* @c, align 4 + %.pre = load i32, i32* @c, align 4 br label %if.end if.then: @@ -53,7 +53,7 @@ entry: br i1 %cmp, label %entry.if.end_crit_edge, label %if.then entry.if.end_crit_edge: - %.pre = load i32* @c, align 4 + %.pre = load i32, i32* @c, align 4 br label %if.end if.then: @@ -73,7 +73,7 @@ entry: br i1 %cmp, label %if.then, label %entry.if.end_crit_edge entry.if.end_crit_edge: - %.pre = load i32* @c, align 4 + %.pre = load i32, i32* @c, align 4 br label %if.end if.then: diff --git a/test/CodeGen/Hexagon/cmp_pred_reg.ll b/test/CodeGen/Hexagon/cmp_pred_reg.ll index 37db3b4..39549a1 100644 --- a/test/CodeGen/Hexagon/cmp_pred_reg.ll +++ b/test/CodeGen/Hexagon/cmp_pred_reg.ll @@ -1,3 +1,4 @@ +; XFAIL: ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Generate various cmpb instruction followed by if (p0) .. if (!p0)... target triple = "hexagon" diff --git a/test/CodeGen/Hexagon/cmpb_pred.ll b/test/CodeGen/Hexagon/cmpb_pred.ll index 0960da1..1a43e62 100644 --- a/test/CodeGen/Hexagon/cmpb_pred.ll +++ b/test/CodeGen/Hexagon/cmpb_pred.ll @@ -1,3 +1,4 @@ +; XFAIL: ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s ; Generate various cmpb instruction followed by if (p0) .. if (!p0)... target triple = "hexagon" @@ -16,7 +17,7 @@ entry: define i32 @Func_3b(i32) nounwind readonly { entry: ; CHECK-NOT: mux - %1 = load i8* @Enum_global, align 1 + %1 = load i8, i8* @Enum_global, align 1 %2 = trunc i32 %0 to i8 %cmp = icmp ne i8 %1, %2 %selv = zext i1 %cmp to i32 @@ -35,7 +36,7 @@ entry: define i32 @Func_3d(i32) nounwind readonly { entry: ; CHECK-NOT: mux - %1 = load i8* @Enum_global, align 1 + %1 = load i8, i8* @Enum_global, align 1 %2 = trunc i32 %0 to i8 %cmp = icmp eq i8 %1, %2 %selv = zext i1 %cmp to i32 @@ -45,7 +46,7 @@ entry: define i32 @Func_3e(i32) nounwind readonly { entry: ; CHECK-NOT: mux - %1 = load i8* @Enum_global, align 1 + %1 = load i8, i8* @Enum_global, align 1 %2 = trunc i32 %0 to i8 %cmp = icmp eq i8 %1, %2 %selv = zext i1 %cmp to i32 diff --git a/test/CodeGen/Hexagon/combine.ll b/test/CodeGen/Hexagon/combine.ll index 7219985..2e320d9 100644 --- a/test/CodeGen/Hexagon/combine.ll +++ b/test/CodeGen/Hexagon/combine.ll @@ -6,8 +6,8 @@ define void @foo() nounwind { entry: - %0 = load i32* @j, align 4 - %1 = load i64* @k, align 8 + %0 = load i32, i32* @j, align 4 + %1 = load i64, i64* @k, align 8 %conv = trunc i64 %1 to i32 %2 = call i64 @llvm.hexagon.A2.combinew(i32 %0, i32 %conv) store i64 %2, i64* @k, align 8 diff --git a/test/CodeGen/Hexagon/combine_ir.ll b/test/CodeGen/Hexagon/combine_ir.ll index e100cf7..634a5c8 100644 --- a/test/CodeGen/Hexagon/combine_ir.ll +++ b/test/CodeGen/Hexagon/combine_ir.ll @@ -4,7 +4,7 @@ define void @word(i32* nocapture %a) nounwind { entry: - %0 = load i32* %a, align 4 + %0 = load i32, i32* %a, align 4 %1 = zext i32 %0 to i64 tail call void @bar(i64 %1) nounwind ret void @@ -17,10 +17,10 @@ declare void @bar(i64) define void @halfword(i16* nocapture %a) nounwind { entry: - %0 = load i16* %a, align 2 + %0 = load i16, i16* %a, align 2 %1 = zext i16 %0 to i64 - %add.ptr = getelementptr inbounds i16* %a, i32 1 - %2 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %a, i32 1 + %2 = load i16, i16* %add.ptr, align 2 %3 = zext i16 %2 to i64 %4 = shl nuw nsw i64 %3, 16 %ins = or i64 %4, %1 @@ -33,10 +33,10 @@ entry: define void @byte(i8* nocapture %a) nounwind { entry: - %0 = load i8* %a, align 1 + %0 = load i8, i8* %a, align 1 %1 = zext i8 %0 to i64 - %add.ptr = getelementptr inbounds i8* %a, i32 1 - %2 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %a, i32 1 + %2 = load i8, i8* %add.ptr, align 1 %3 = zext i8 %2 to i64 %4 = shl nuw nsw i64 %3, 8 %ins = or i64 %4, %1 diff --git a/test/CodeGen/Hexagon/convertdptoint.ll b/test/CodeGen/Hexagon/convertdptoint.ll index fa068c4..a09c2fd 100644 --- a/test/CodeGen/Hexagon/convertdptoint.ll +++ b/test/CodeGen/Hexagon/convertdptoint.ll @@ -14,13 +14,13 @@ entry: store i32 0, i32* %retval store double 1.540000e+01, double* %a, align 8 store double 9.100000e+00, double* %b, align 8 - %0 = load double* %a, align 8 - %1 = load double* %b, align 8 + %0 = load double, double* %a, align 8 + %1 = load double, double* %b, align 8 %add = fadd double %0, %1 store double %add, double* %c, align 8 - %2 = load double* %c, align 8 + %2 = load double, double* %c, align 8 %conv = fptosi double %2 to i32 store i32 %conv, i32* %i, align 4 - %3 = load i32* %i, align 4 + %3 = load i32, i32* %i, align 4 ret i32 %3 } diff --git a/test/CodeGen/Hexagon/convertdptoll.ll b/test/CodeGen/Hexagon/convertdptoll.ll index 1b4dd86..f46d46c 100644 --- a/test/CodeGen/Hexagon/convertdptoll.ll +++ b/test/CodeGen/Hexagon/convertdptoll.ll @@ -14,14 +14,14 @@ entry: store i32 0, i32* %retval store double 1.540000e+01, double* %a, align 8 store double 9.100000e+00, double* %b, align 8 - %0 = load double* %a, align 8 - %1 = load double* %b, align 8 + %0 = load double, double* %a, align 8 + %1 = load double, double* %b, align 8 %add = fadd double %0, %1 store double %add, double* %c, align 8 - %2 = load double* %c, align 8 + %2 = load double, double* %c, align 8 %conv = fptosi double %2 to i64 store i64 %conv, i64* %i, align 8 - %3 = load i64* %i, align 8 + %3 = load i64, i64* %i, align 8 %conv1 = trunc i64 %3 to i32 ret i32 %conv1 } diff --git a/test/CodeGen/Hexagon/convertsptoint.ll b/test/CodeGen/Hexagon/convertsptoint.ll index b8a9d6c..7593e57 100644 --- a/test/CodeGen/Hexagon/convertsptoint.ll +++ b/test/CodeGen/Hexagon/convertsptoint.ll @@ -14,13 +14,13 @@ entry: store i32 0, i32* %retval store float 0x402ECCCCC0000000, float* %a, align 4 store float 0x4022333340000000, float* %b, align 4 - %0 = load float* %a, align 4 - %1 = load float* %b, align 4 + %0 = load float, float* %a, align 4 + %1 = load float, float* %b, align 4 %add = fadd float %0, %1 store float %add, float* %c, align 4 - %2 = load float* %c, align 4 + %2 = load float, float* %c, align 4 %conv = fptosi float %2 to i32 store i32 %conv, i32* %i, align 4 - %3 = load i32* %i, align 4 + %3 = load i32, i32* %i, align 4 ret i32 %3 } diff --git a/test/CodeGen/Hexagon/convertsptoll.ll b/test/CodeGen/Hexagon/convertsptoll.ll index 1c4df94..d8432cb 100644 --- a/test/CodeGen/Hexagon/convertsptoll.ll +++ b/test/CodeGen/Hexagon/convertsptoll.ll @@ -14,14 +14,14 @@ entry: store i32 0, i32* %retval store float 0x402ECCCCC0000000, float* %a, align 4 store float 0x4022333340000000, float* %b, align 4 - %0 = load float* %a, align 4 - %1 = load float* %b, align 4 + %0 = load float, float* %a, align 4 + %1 = load float, float* %b, align 4 %add = fadd float %0, %1 store float %add, float* %c, align 4 - %2 = load float* %c, align 4 + %2 = load float, float* %c, align 4 %conv = fptosi float %2 to i64 store i64 %conv, i64* %i, align 8 - %3 = load i64* %i, align 8 + %3 = load i64, i64* %i, align 8 %conv1 = trunc i64 %3 to i32 ret i32 %conv1 } diff --git a/test/CodeGen/Hexagon/dadd.ll b/test/CodeGen/Hexagon/dadd.ll index a86a90c..5fcd705 100644 --- a/test/CodeGen/Hexagon/dadd.ll +++ b/test/CodeGen/Hexagon/dadd.ll @@ -11,8 +11,8 @@ entry: %c = alloca double, align 8 store double 1.540000e+01, double* %a, align 8 store double 9.100000e+00, double* %b, align 8 - %0 = load double* %a, align 8 - %1 = load double* %b, align 8 + %0 = load double, double* %a, align 8 + %1 = load double, double* %b, align 8 %add = fadd double %0, %1 store double %add, double* %c, align 8 ret i32 0 diff --git a/test/CodeGen/Hexagon/dmul.ll b/test/CodeGen/Hexagon/dmul.ll index cbe0d7f..1b79e0a 100644 --- a/test/CodeGen/Hexagon/dmul.ll +++ b/test/CodeGen/Hexagon/dmul.ll @@ -10,8 +10,8 @@ entry: %c = alloca double, align 8 store double 1.540000e+01, double* %a, align 8 store double 9.100000e+00, double* %b, align 8 - %0 = load double* %b, align 8 - %1 = load double* %a, align 8 + %0 = load double, double* %b, align 8 + %1 = load double, double* %a, align 8 %mul = fmul double %0, %1 store double %mul, double* %c, align 8 ret i32 0 diff --git a/test/CodeGen/Hexagon/double.ll b/test/CodeGen/Hexagon/double.ll index c3b6f37..b4d025c 100644 --- a/test/CodeGen/Hexagon/double.ll +++ b/test/CodeGen/Hexagon/double.ll @@ -10,13 +10,13 @@ entry: store double* %acc, double** %acc.addr, align 4 store double %num, double* %num.addr, align 8 store double %num2, double* %num2.addr, align 8 - %0 = load double** %acc.addr, align 4 - %1 = load double* %0 - %2 = load double* %num.addr, align 8 + %0 = load double*, double** %acc.addr, align 4 + %1 = load double, double* %0 + %2 = load double, double* %num.addr, align 8 %add = fadd double %1, %2 - %3 = load double* %num2.addr, align 8 + %3 = load double, double* %num2.addr, align 8 %sub = fsub double %add, %3 - %4 = load double** %acc.addr, align 4 + %4 = load double*, double** %acc.addr, align 4 store double %sub, double* %4 ret void } diff --git a/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll b/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll index 54e7ce3..6bf8224 100644 --- a/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll +++ b/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll @@ -14,13 +14,13 @@ entry: store i32 0, i32* %retval store double 1.540000e+01, double* %a, align 8 store double 9.100000e+00, double* %b, align 8 - %0 = load double* %a, align 8 - %1 = load double* %b, align 8 + %0 = load double, double* %a, align 8 + %1 = load double, double* %b, align 8 %add = fadd double %0, %1 store double %add, double* %c, align 8 - %2 = load double* %c, align 8 + %2 = load double, double* %c, align 8 %conv = fptosi double %2 to i32 store i32 %conv, i32* %i, align 4 - %3 = load i32* %i, align 4 + %3 = load i32, i32* %i, align 4 ret i32 %3 } diff --git a/test/CodeGen/Hexagon/dsub.ll b/test/CodeGen/Hexagon/dsub.ll index f271492..8b37301 100644 --- a/test/CodeGen/Hexagon/dsub.ll +++ b/test/CodeGen/Hexagon/dsub.ll @@ -10,8 +10,8 @@ entry: %c = alloca double, align 8 store double 1.540000e+01, double* %a, align 8 store double 9.100000e+00, double* %b, align 8 - %0 = load double* %b, align 8 - %1 = load double* %a, align 8 + %0 = load double, double* %b, align 8 + %1 = load double, double* %a, align 8 %sub = fsub double %0, %1 store double %sub, double* %c, align 8 ret i32 0 diff --git a/test/CodeGen/Hexagon/extload-combine.ll b/test/CodeGen/Hexagon/extload-combine.ll index b3b8bf0..519177f 100644 --- a/test/CodeGen/Hexagon/extload-combine.ll +++ b/test/CodeGen/Hexagon/extload-combine.ll @@ -19,7 +19,7 @@ define i64 @short_test1() #0 { ; CHECK: combine(#0, [[VAR]]) entry: store i16 0, i16* @a, align 2 - %0 = load i16* @b, align 2 + %0 = load i16, i16* @b, align 2 %conv2 = zext i16 %0 to i64 ret i64 %conv2 } @@ -30,7 +30,7 @@ define i64 @short_test2() #0 { ; CHECK: sxtw([[VAR1]]) entry: store i16 0, i16* @a, align 2 - %0 = load i16* @c, align 2 + %0 = load i16, i16* @c, align 2 %conv2 = sext i16 %0 to i64 ret i64 %conv2 } @@ -41,7 +41,7 @@ define i64 @char_test1() #0 { ; CHECK: combine(#0, [[VAR2]]) entry: store i8 0, i8* @char_a, align 1 - %0 = load i8* @char_b, align 1 + %0 = load i8, i8* @char_b, align 1 %conv2 = zext i8 %0 to i64 ret i64 %conv2 } @@ -52,7 +52,7 @@ define i64 @char_test2() #0 { ; CHECK: sxtw([[VAR3]]) entry: store i8 0, i8* @char_a, align 1 - %0 = load i8* @char_c, align 1 + %0 = load i8, i8* @char_c, align 1 %conv2 = sext i8 %0 to i64 ret i64 %conv2 } @@ -63,7 +63,7 @@ define i64 @int_test1() #0 { ; CHECK: combine(#0, [[VAR4]]) entry: store i32 0, i32* @int_a, align 4 - %0 = load i32* @int_b, align 4 + %0 = load i32, i32* @int_b, align 4 %conv = zext i32 %0 to i64 ret i64 %conv } @@ -74,7 +74,7 @@ define i64 @int_test2() #0 { ; CHECK: sxtw([[VAR5]]) entry: store i32 0, i32* @int_a, align 4 - %0 = load i32* @int_c, align 4 + %0 = load i32, i32* @int_c, align 4 %conv = sext i32 %0 to i64 ret i64 %conv } diff --git a/test/CodeGen/Hexagon/fadd.ll b/test/CodeGen/Hexagon/fadd.ll index b95e147..6cf0fbb 100644 --- a/test/CodeGen/Hexagon/fadd.ll +++ b/test/CodeGen/Hexagon/fadd.ll @@ -10,8 +10,8 @@ entry: %c = alloca float, align 4 store float 0x402ECCCCC0000000, float* %a, align 4 store float 0x4022333340000000, float* %b, align 4 - %0 = load float* %a, align 4 - %1 = load float* %b, align 4 + %0 = load float, float* %a, align 4 + %1 = load float, float* %b, align 4 %add = fadd float %0, %1 store float %add, float* %c, align 4 ret i32 0 diff --git a/test/CodeGen/Hexagon/fcmp.ll b/test/CodeGen/Hexagon/fcmp.ll index e7b649e..5cf3c57 100644 --- a/test/CodeGen/Hexagon/fcmp.ll +++ b/test/CodeGen/Hexagon/fcmp.ll @@ -8,7 +8,7 @@ entry: %retval = alloca i32, align 4 %y.addr = alloca float, align 4 store float %y, float* %y.addr, align 4 - %0 = load float* %y.addr, align 4 + %0 = load float, float* %y.addr, align 4 %cmp = fcmp ogt float %0, 0x406AD7EFA0000000 br i1 %cmp, label %if.then, label %if.else @@ -21,7 +21,7 @@ if.else: ; preds = %entry br label %return return: ; preds = %if.else, %if.then - %1 = load i32* %retval + %1 = load i32, i32* %retval ret i32 %1 } @@ -31,7 +31,7 @@ entry: %a = alloca float, align 4 store i32 0, i32* %retval store float 0x40012E0A00000000, float* %a, align 4 - %0 = load float* %a, align 4 + %0 = load float, float* %a, align 4 %call = call i32 @foo(float %0) ret i32 %call } diff --git a/test/CodeGen/Hexagon/float.ll b/test/CodeGen/Hexagon/float.ll index bec9f58..03d1fbf 100644 --- a/test/CodeGen/Hexagon/float.ll +++ b/test/CodeGen/Hexagon/float.ll @@ -10,13 +10,13 @@ entry: store float* %acc, float** %acc.addr, align 4 store float %num, float* %num.addr, align 4 store float %num2, float* %num2.addr, align 4 - %0 = load float** %acc.addr, align 4 - %1 = load float* %0 - %2 = load float* %num.addr, align 4 + %0 = load float*, float** %acc.addr, align 4 + %1 = load float, float* %0 + %2 = load float, float* %num.addr, align 4 %add = fadd float %1, %2 - %3 = load float* %num2.addr, align 4 + %3 = load float, float* %num2.addr, align 4 %sub = fsub float %add, %3 - %4 = load float** %acc.addr, align 4 + %4 = load float*, float** %acc.addr, align 4 store float %sub, float* %4 ret void } diff --git a/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll b/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll index bec9f58..03d1fbf 100644 --- a/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll +++ b/test/CodeGen/Hexagon/floatconvert-ieee-rnd-near.ll @@ -10,13 +10,13 @@ entry: store float* %acc, float** %acc.addr, align 4 store float %num, float* %num.addr, align 4 store float %num2, float* %num2.addr, align 4 - %0 = load float** %acc.addr, align 4 - %1 = load float* %0 - %2 = load float* %num.addr, align 4 + %0 = load float*, float** %acc.addr, align 4 + %1 = load float, float* %0 + %2 = load float, float* %num.addr, align 4 %add = fadd float %1, %2 - %3 = load float* %num2.addr, align 4 + %3 = load float, float* %num2.addr, align 4 %sub = fsub float %add, %3 - %4 = load float** %acc.addr, align 4 + %4 = load float*, float** %acc.addr, align 4 store float %sub, float* %4 ret void } diff --git a/test/CodeGen/Hexagon/fmul.ll b/test/CodeGen/Hexagon/fmul.ll index 4766845..4f55d0b 100644 --- a/test/CodeGen/Hexagon/fmul.ll +++ b/test/CodeGen/Hexagon/fmul.ll @@ -11,8 +11,8 @@ entry: %c = alloca float, align 4 store float 0x402ECCCCC0000000, float* %a, align 4 store float 0x4022333340000000, float* %b, align 4 - %0 = load float* %b, align 4 - %1 = load float* %a, align 4 + %0 = load float, float* %b, align 4 + %1 = load float, float* %a, align 4 %mul = fmul float %0, %1 store float %mul, float* %c, align 4 ret i32 0 diff --git a/test/CodeGen/Hexagon/frame.ll b/test/CodeGen/Hexagon/frame.ll index dc87c73..e87acb8 100644 --- a/test/CodeGen/Hexagon/frame.ll +++ b/test/CodeGen/Hexagon/frame.ll @@ -10,14 +10,14 @@ define i32 @foo() nounwind { entry: %i = alloca i32, align 4 - %0 = load i32* @num, align 4 + %0 = load i32, i32* @num, align 4 store i32 %0, i32* %i, align 4 - %1 = load i32* %i, align 4 - %2 = load i32* @acc, align 4 + %1 = load i32, i32* %i, align 4 + %2 = load i32, i32* @acc, align 4 %mul = mul nsw i32 %1, %2 - %3 = load i32* @num2, align 4 + %3 = load i32, i32* @num2, align 4 %add = add nsw i32 %mul, %3 store i32 %add, i32* %i, align 4 - %4 = load i32* %i, align 4 + %4 = load i32, i32* %i, align 4 ret i32 %4 } diff --git a/test/CodeGen/Hexagon/fsub.ll b/test/CodeGen/Hexagon/fsub.ll index 07c866f..ca7bdc4 100644 --- a/test/CodeGen/Hexagon/fsub.ll +++ b/test/CodeGen/Hexagon/fsub.ll @@ -10,8 +10,8 @@ entry: %c = alloca float, align 4 store float 0x402ECCCCC0000000, float* %a, align 4 store float 0x4022333340000000, float* %b, align 4 - %0 = load float* %b, align 4 - %1 = load float* %a, align 4 + %0 = load float, float* %b, align 4 + %1 = load float, float* %a, align 4 %sub = fsub float %0, %1 store float %sub, float* %c, align 4 ret i32 0 diff --git a/test/CodeGen/Hexagon/fusedandshift.ll b/test/CodeGen/Hexagon/fusedandshift.ll index 022b3c6..59a1e1d 100644 --- a/test/CodeGen/Hexagon/fusedandshift.ll +++ b/test/CodeGen/Hexagon/fusedandshift.ll @@ -5,7 +5,7 @@ define i32 @main(i16* %a, i16* %b) nounwind { entry: - %0 = load i16* %a, align 2 + %0 = load i16, i16* %a, align 2 %conv1 = sext i16 %0 to i32 %shr1 = ashr i32 %conv1, 3 %and1 = and i32 %shr1, 15 diff --git a/test/CodeGen/Hexagon/gp-plus-offset-load.ll b/test/CodeGen/Hexagon/gp-plus-offset-load.ll index a1b80a6..cd1aacc 100644 --- a/test/CodeGen/Hexagon/gp-plus-offset-load.ll +++ b/test/CodeGen/Hexagon/gp-plus-offset-load.ll @@ -12,7 +12,7 @@ entry: br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry - %0 = load i32* getelementptr inbounds (%struct.struc* @foo, i32 0, i32 3), align 4 + %0 = load i32, i32* getelementptr inbounds (%struct.struc, %struct.struc* @foo, i32 0, i32 3), align 4 store i32 %0, i32* %ival, align 4 br label %if.end @@ -27,7 +27,7 @@ entry: br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry - %0 = load i8* getelementptr inbounds (%struct.struc* @foo, i32 0, i32 1), align 1 + %0 = load i8, i8* getelementptr inbounds (%struct.struc, %struct.struc* @foo, i32 0, i32 1), align 1 store i8 %0, i8* %ival, align 1 br label %if.end @@ -42,7 +42,7 @@ entry: br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry - %0 = load i16* getelementptr inbounds (%struct.struc* @foo, i32 0, i32 2), align 2 + %0 = load i16, i16* getelementptr inbounds (%struct.struc, %struct.struc* @foo, i32 0, i32 2), align 2 store i16 %0, i16* %ival, align 2 br label %if.end diff --git a/test/CodeGen/Hexagon/gp-plus-offset-store.ll b/test/CodeGen/Hexagon/gp-plus-offset-store.ll index c782b30..6b181ca 100644 --- a/test/CodeGen/Hexagon/gp-plus-offset-store.ll +++ b/test/CodeGen/Hexagon/gp-plus-offset-store.ll @@ -12,7 +12,7 @@ entry: br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry - store i8 %ival, i8* getelementptr inbounds (%struct.struc* @foo, i32 0, i32 1), align 1 + store i8 %ival, i8* getelementptr inbounds (%struct.struc, %struct.struc* @foo, i32 0, i32 1), align 1 br label %if.end if.end: ; preds = %if.then, %entry @@ -26,7 +26,7 @@ entry: br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry - store i16 %ival, i16* getelementptr inbounds (%struct.struc* @foo, i32 0, i32 2), align 2 + store i16 %ival, i16* getelementptr inbounds (%struct.struc, %struct.struc* @foo, i32 0, i32 2), align 2 br label %if.end if.end: ; preds = %if.then, %entry diff --git a/test/CodeGen/Hexagon/gp-rel.ll b/test/CodeGen/Hexagon/gp-rel.ll index 561869e..bb7cb18 100644 --- a/test/CodeGen/Hexagon/gp-rel.ll +++ b/test/CodeGen/Hexagon/gp-rel.ll @@ -10,14 +10,14 @@ entry: ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(#a) ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(#b) ; CHECK: if{{ *}}(p{{[0-3]}}) memw(##c){{ *}}={{ *}}r{{[0-9]+}} - %0 = load i32* @a, align 4 - %1 = load i32* @b, align 4 + %0 = load i32, i32* @a, align 4 + %1 = load i32, i32* @b, align 4 %add = add nsw i32 %1, %0 %cmp = icmp eq i32 %0, %1 br i1 %cmp, label %if.then, label %entry.if.end_crit_edge entry.if.end_crit_edge: - %.pre = load i32* @c, align 4 + %.pre = load i32, i32* @c, align 4 br label %if.end if.then: diff --git a/test/CodeGen/Hexagon/hwloop-cleanup.ll b/test/CodeGen/Hexagon/hwloop-cleanup.ll index 6456ebf..c04966a 100644 --- a/test/CodeGen/Hexagon/hwloop-cleanup.ll +++ b/test/CodeGen/Hexagon/hwloop-cleanup.ll @@ -1,4 +1,5 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; RUN: llc -march=hexagon -mcpu=hexagonv4 -no-phi-elim-live-out-early-exit \ +; RUN: < %s | FileCheck %s ; Check that we remove the compare and induction variable instructions ; after generating hardware loops. ; Bug 6685. @@ -20,11 +21,11 @@ for.body: ; preds = %for.body.preheader, %sum.03 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ] %arrayidx.phi = phi i32* [ %arrayidx.inc, %for.body ], [ %b, %for.body.preheader ] %i.02 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ] - %0 = load i32* %arrayidx.phi, align 4 + %0 = load i32, i32* %arrayidx.phi, align 4 %add = add nsw i32 %0, %sum.03 %inc = add nsw i32 %i.02, 1 %exitcond = icmp eq i32 %inc, %n - %arrayidx.inc = getelementptr i32* %arrayidx.phi, i32 1 + %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1 br i1 %exitcond, label %for.end.loopexit, label %for.body for.end.loopexit: @@ -50,11 +51,11 @@ for.body: %sum.02 = phi i32 [ 0, %entry ], [ %add, %for.body ] %arrayidx.phi = phi i32* [ %b, %entry ], [ %arrayidx.inc, %for.body ] %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ] - %0 = load i32* %arrayidx.phi, align 4 + %0 = load i32, i32* %arrayidx.phi, align 4 %add = add nsw i32 %0, %sum.02 %inc = add nsw i32 %i.01, 1 %exitcond = icmp eq i32 %inc, 40 - %arrayidx.inc = getelementptr i32* %arrayidx.phi, i32 1 + %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1 br i1 %exitcond, label %for.end, label %for.body for.end: @@ -76,7 +77,7 @@ for.body: store i32 %i.01, i32* %arrayidx.phi, align 4 %inc = add nsw i32 %i.01, 1 %exitcond = icmp eq i32 %inc, 40 - %arrayidx.inc = getelementptr i32* %arrayidx.phi, i32 1 + %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1 br i1 %exitcond, label %for.end, label %for.body for.end: diff --git a/test/CodeGen/Hexagon/hwloop-const.ll b/test/CodeGen/Hexagon/hwloop-const.ll index 8204dde..d549c1f 100644 --- a/test/CodeGen/Hexagon/hwloop-const.ll +++ b/test/CodeGen/Hexagon/hwloop-const.ll @@ -14,9 +14,9 @@ entry: ; CHECK: endloop for.body: ; preds = %for.body, %entry %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds [25000 x i32]* @b, i32 0, i32 %i.02 + %arrayidx = getelementptr inbounds [25000 x i32], [25000 x i32]* @b, i32 0, i32 %i.02 store i32 %i.02, i32* %arrayidx, align 4 - %arrayidx1 = getelementptr inbounds [25000 x i32]* @a, i32 0, i32 %i.02 + %arrayidx1 = getelementptr inbounds [25000 x i32], [25000 x i32]* @a, i32 0, i32 %i.02 store i32 %i.02, i32* %arrayidx1, align 4 %inc = add nsw i32 %i.02, 1 %exitcond = icmp eq i32 %inc, 25000 diff --git a/test/CodeGen/Hexagon/hwloop-dbg.ll b/test/CodeGen/Hexagon/hwloop-dbg.ll index 3c05884..2fa7f52 100644 --- a/test/CodeGen/Hexagon/hwloop-dbg.ll +++ b/test/CodeGen/Hexagon/hwloop-dbg.ll @@ -5,9 +5,9 @@ target triple = "hexagon" define void @foo(i32* nocapture %a, i32* nocapture %b) nounwind { entry: - tail call void @llvm.dbg.value(metadata i32* %a, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !17 - tail call void @llvm.dbg.value(metadata i32* %b, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !18 - tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !19 + tail call void @llvm.dbg.value(metadata i32* %a, i64 0, metadata !13, metadata !MDExpression()), !dbg !17 + tail call void @llvm.dbg.value(metadata i32* %b, i64 0, metadata !14, metadata !MDExpression()), !dbg !18 + tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !15, metadata !MDExpression()), !dbg !19 br label %for.body, !dbg !19 for.body: ; preds = %for.body, %entry @@ -17,14 +17,14 @@ for.body: ; preds = %for.body, %entry %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ] %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ] %b.addr.01 = phi i32* [ %b, %entry ], [ %incdec.ptr, %for.body ] - %incdec.ptr = getelementptr inbounds i32* %b.addr.01, i32 1, !dbg !21 - tail call void @llvm.dbg.value(metadata i32* %incdec.ptr, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !21 - %0 = load i32* %b.addr.01, align 4, !dbg !21 + %incdec.ptr = getelementptr inbounds i32, i32* %b.addr.01, i32 1, !dbg !21 + tail call void @llvm.dbg.value(metadata i32* %incdec.ptr, i64 0, metadata !14, metadata !MDExpression()), !dbg !21 + %0 = load i32, i32* %b.addr.01, align 4, !dbg !21 store i32 %0, i32* %arrayidx.phi, align 4, !dbg !21 %inc = add nsw i32 %i.02, 1, !dbg !26 - tail call void @llvm.dbg.value(metadata i32 %inc, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !26 + tail call void @llvm.dbg.value(metadata i32 %inc, i64 0, metadata !15, metadata !MDExpression()), !dbg !26 %exitcond = icmp eq i32 %inc, 10, !dbg !19 - %arrayidx.inc = getelementptr i32* %arrayidx.phi, i32 1 + %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1 br i1 %exitcond, label %for.end, label %for.body, !dbg !19 for.end: ; preds = %for.body @@ -37,28 +37,28 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!29} -!0 = !{!"0x11\0012\00QuIC LLVM Hexagon Clang version 6.1-pre-unknown, (git://git-hexagon-aus.quicinc.com/llvm/clang-mainline.git e9382867661454cdf44addb39430741578e9765c) (llvm/llvm-mainline.git 36412bb1fcf03ed426d4437b41198bae066675ac)\001\00\000\00\001", !28, !2, !2, !3, !2, null} ; [ DW_TAG_compile_unit ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c] [DW_LANG_C99] +!0 = !MDCompileUnit(language: DW_LANG_C99, producer: "QuIC LLVM Hexagon Clang version 6.1-pre-unknown, (git://git-hexagon-aus.quicinc.com/llvm/clang-mainline.git e9382867661454cdf44addb39430741578e9765c) (llvm/llvm-mainline.git 36412bb1fcf03ed426d4437b41198bae066675ac)", isOptimized: true, emissionKind: 1, file: !28, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2) !2 = !{} !3 = !{!5} -!5 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\00256\001\001", !28, null, !7, null, void (i32*, i32*)* @foo, null, null, !11} ; [ DW_TAG_subprogram ] [line 1] [def] [foo] -!6 = !{!"0x29", !28} ; [ DW_TAG_file_type ] -!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!5 = !MDSubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !28, scope: null, type: !7, function: void (i32*, i32*)* @foo, variables: !11) +!6 = !MDFile(filename: "hwloop-dbg.c", directory: "/usr2/kparzysz/s.hex/t") +!7 = !MDSubroutineType(types: !8) !8 = !{null, !9, !9} -!9 = !{!"0xf\00\000\0032\0032\000\000", null, null, !10} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from int] -!10 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!9 = !MDDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, baseType: !10) +!10 = !MDBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !11 = !{!13, !14, !15} -!13 = !{!"0x101\00a\0016777217\000", !5, !6, !9} ; [ DW_TAG_arg_variable ] [a] [line 1] -!14 = !{!"0x101\00b\0033554433\000", !5, !6, !9} ; [ DW_TAG_arg_variable ] [b] [line 1] -!15 = !{!"0x100\00i\002\000", !16, !6, !10} ; [ DW_TAG_auto_variable ] [i] [line 2] -!16 = !{!"0xb\001\0026\000", !28, !5} ; [ DW_TAG_lexical_block ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c] +!13 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "a", line: 1, arg: 1, scope: !5, file: !6, type: !9) +!14 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "b", line: 1, arg: 2, scope: !5, file: !6, type: !9) +!15 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "i", line: 2, scope: !16, file: !6, type: !10) +!16 = distinct !MDLexicalBlock(line: 1, column: 26, file: !28, scope: !5) !17 = !MDLocation(line: 1, column: 15, scope: !5) !18 = !MDLocation(line: 1, column: 23, scope: !5) !19 = !MDLocation(line: 3, column: 8, scope: !20) -!20 = !{!"0xb\003\003\001", !28, !16} ; [ DW_TAG_lexical_block ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c] +!20 = distinct !MDLexicalBlock(line: 3, column: 3, file: !28, scope: !16) !21 = !MDLocation(line: 4, column: 5, scope: !22) -!22 = !{!"0xb\003\0028\002", !28, !20} ; [ DW_TAG_lexical_block ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c] +!22 = distinct !MDLexicalBlock(line: 3, column: 28, file: !28, scope: !20) !26 = !MDLocation(line: 3, column: 23, scope: !20) !27 = !MDLocation(line: 6, column: 1, scope: !16) -!28 = !{!"hwloop-dbg.c", !"/usr2/kparzysz/s.hex/t"} -!29 = !{i32 1, !"Debug Info Version", i32 2} +!28 = !MDFile(filename: "hwloop-dbg.c", directory: "/usr2/kparzysz/s.hex/t") +!29 = !{i32 1, !"Debug Info Version", i32 3} !30 = !{i32 0} diff --git a/test/CodeGen/Hexagon/hwloop-le.ll b/test/CodeGen/Hexagon/hwloop-le.ll index 9c8cec7..85a1b3d 100644 --- a/test/CodeGen/Hexagon/hwloop-le.ll +++ b/test/CodeGen/Hexagon/hwloop-le.ll @@ -14,8 +14,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ 28395, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -43,8 +43,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ 9073, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -72,8 +72,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ 21956, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -101,8 +101,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ 16782, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -130,8 +130,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ 19097, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -159,8 +159,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -188,8 +188,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -217,8 +217,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -246,8 +246,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -275,8 +275,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -304,8 +304,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -333,8 +333,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -362,8 +362,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -391,8 +391,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -420,8 +420,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 diff --git a/test/CodeGen/Hexagon/hwloop-lt.ll b/test/CodeGen/Hexagon/hwloop-lt.ll index 7e43733..804f764 100644 --- a/test/CodeGen/Hexagon/hwloop-lt.ll +++ b/test/CodeGen/Hexagon/hwloop-lt.ll @@ -14,8 +14,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ 8531, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -43,8 +43,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ 9152, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -72,8 +72,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ 18851, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -101,8 +101,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ 25466, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -130,8 +130,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ 9295, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -159,8 +159,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -188,8 +188,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -217,8 +217,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -246,8 +246,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -275,8 +275,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -304,8 +304,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -333,8 +333,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -362,8 +362,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -391,8 +391,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -420,8 +420,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 diff --git a/test/CodeGen/Hexagon/hwloop-lt1.ll b/test/CodeGen/Hexagon/hwloop-lt1.ll index cf58740..16fe728 100644 --- a/test/CodeGen/Hexagon/hwloop-lt1.ll +++ b/test/CodeGen/Hexagon/hwloop-lt1.ll @@ -19,10 +19,10 @@ polly.loop_body: ; preds = %entry, %polly.loop_ %p_vector_iv14 = or i32 %polly.loopiv16, 1 %p_vector_iv3 = add i32 %p_vector_iv14, 1 %p_vector_iv415 = or i32 %polly.loopiv16, 3 - %p_arrayidx = getelementptr [400 x i8]* @A, i32 0, i32 %polly.loopiv16 - %p_arrayidx5 = getelementptr [400 x i8]* @A, i32 0, i32 %p_vector_iv14 - %p_arrayidx6 = getelementptr [400 x i8]* @A, i32 0, i32 %p_vector_iv3 - %p_arrayidx7 = getelementptr [400 x i8]* @A, i32 0, i32 %p_vector_iv415 + %p_arrayidx = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %polly.loopiv16 + %p_arrayidx5 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %p_vector_iv14 + %p_arrayidx6 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %p_vector_iv3 + %p_arrayidx7 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %p_vector_iv415 store i8 123, i8* %p_arrayidx, align 1 store i8 123, i8* %p_arrayidx5, align 1 store i8 123, i8* %p_arrayidx6, align 1 diff --git a/test/CodeGen/Hexagon/hwloop-ne.ll b/test/CodeGen/Hexagon/hwloop-ne.ll index bceef2a..12ef3b5 100644 --- a/test/CodeGen/Hexagon/hwloop-ne.ll +++ b/test/CodeGen/Hexagon/hwloop-ne.ll @@ -14,8 +14,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ 32623, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -43,8 +43,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ 29554, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -72,8 +72,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ 15692, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -101,8 +101,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ 10449, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -130,8 +130,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ 32087, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -159,8 +159,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -188,8 +188,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -217,8 +217,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -246,8 +246,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -275,8 +275,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -304,8 +304,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -333,8 +333,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -362,8 +362,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -391,8 +391,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 @@ -420,8 +420,8 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %i.04 = phi i32 [ %a, %for.body.lr.ph ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i8* %p, i32 %i.04 - %0 = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, i8* %p, i32 %i.04 + %0 = load i8, i8* %arrayidx, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 1 %conv1 = trunc i32 %add to i8 diff --git a/test/CodeGen/Hexagon/i16_VarArg.ll b/test/CodeGen/Hexagon/i16_VarArg.ll index c5d05a5..41cecec 100644 --- a/test/CodeGen/Hexagon/i16_VarArg.ll +++ b/test/CodeGen/Hexagon/i16_VarArg.ll @@ -20,8 +20,8 @@ declare i32 @printf(i8*, ...) define i32 @main() { - %a = load double* @A - %b = load double* @B + %a = load double, double* @A + %b = load double, double* @B %lt_r = fcmp olt double %a, %b %le_r = fcmp ole double %a, %b %gt_r = fcmp ogt double %a, %b @@ -29,12 +29,12 @@ define i32 @main() { %eq_r = fcmp oeq double %a, %b %ne_r = fcmp une double %a, %b %val1 = zext i1 %lt_r to i16 - %lt_s = getelementptr [12 x i8]* @lt_str, i64 0, i64 0 - %le_s = getelementptr [13 x i8]* @le_str, i64 0, i64 0 - %gt_s = getelementptr [12 x i8]* @gt_str, i64 0, i64 0 - %ge_s = getelementptr [13 x i8]* @ge_str, i64 0, i64 0 - %eq_s = getelementptr [13 x i8]* @eq_str, i64 0, i64 0 - %ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0 + %lt_s = getelementptr [12 x i8], [12 x i8]* @lt_str, i64 0, i64 0 + %le_s = getelementptr [13 x i8], [13 x i8]* @le_str, i64 0, i64 0 + %gt_s = getelementptr [12 x i8], [12 x i8]* @gt_str, i64 0, i64 0 + %ge_s = getelementptr [13 x i8], [13 x i8]* @ge_str, i64 0, i64 0 + %eq_s = getelementptr [13 x i8], [13 x i8]* @eq_str, i64 0, i64 0 + %ne_s = getelementptr [13 x i8], [13 x i8]* @ne_str, i64 0, i64 0 call i32 (i8*, ...)* @printf( i8* %lt_s, i16 %val1 ) ret i32 0 } diff --git a/test/CodeGen/Hexagon/i1_VarArg.ll b/test/CodeGen/Hexagon/i1_VarArg.ll index 37f2778..8b5625c 100644 --- a/test/CodeGen/Hexagon/i1_VarArg.ll +++ b/test/CodeGen/Hexagon/i1_VarArg.ll @@ -20,20 +20,20 @@ declare i32 @printf(i8*, ...) define i32 @main() { - %a = load double* @A - %b = load double* @B + %a = load double, double* @A + %b = load double, double* @B %lt_r = fcmp olt double %a, %b %le_r = fcmp ole double %a, %b %gt_r = fcmp ogt double %a, %b %ge_r = fcmp oge double %a, %b %eq_r = fcmp oeq double %a, %b %ne_r = fcmp une double %a, %b - %lt_s = getelementptr [12 x i8]* @lt_str, i64 0, i64 0 - %le_s = getelementptr [13 x i8]* @le_str, i64 0, i64 0 - %gt_s = getelementptr [12 x i8]* @gt_str, i64 0, i64 0 - %ge_s = getelementptr [13 x i8]* @ge_str, i64 0, i64 0 - %eq_s = getelementptr [13 x i8]* @eq_str, i64 0, i64 0 - %ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0 + %lt_s = getelementptr [12 x i8], [12 x i8]* @lt_str, i64 0, i64 0 + %le_s = getelementptr [13 x i8], [13 x i8]* @le_str, i64 0, i64 0 + %gt_s = getelementptr [12 x i8], [12 x i8]* @gt_str, i64 0, i64 0 + %ge_s = getelementptr [13 x i8], [13 x i8]* @ge_str, i64 0, i64 0 + %eq_s = getelementptr [13 x i8], [13 x i8]* @eq_str, i64 0, i64 0 + %ne_s = getelementptr [13 x i8], [13 x i8]* @ne_str, i64 0, i64 0 call i32 (i8*, ...)* @printf( i8* %lt_s, i1 %lt_r ) call i32 (i8*, ...)* @printf( i8* %le_s, i1 %le_r ) call i32 (i8*, ...)* @printf( i8* %gt_s, i1 %gt_r ) diff --git a/test/CodeGen/Hexagon/i8_VarArg.ll b/test/CodeGen/Hexagon/i8_VarArg.ll index 6f056ff..7283ba4 100644 --- a/test/CodeGen/Hexagon/i8_VarArg.ll +++ b/test/CodeGen/Hexagon/i8_VarArg.ll @@ -20,8 +20,8 @@ declare i32 @printf(i8*, ...) define i32 @main() { - %a = load double* @A - %b = load double* @B + %a = load double, double* @A + %b = load double, double* @B %lt_r = fcmp olt double %a, %b %le_r = fcmp ole double %a, %b %gt_r = fcmp ogt double %a, %b @@ -29,12 +29,12 @@ define i32 @main() { %eq_r = fcmp oeq double %a, %b %ne_r = fcmp une double %a, %b %val1 = zext i1 %lt_r to i8 - %lt_s = getelementptr [12 x i8]* @lt_str, i64 0, i64 0 - %le_s = getelementptr [13 x i8]* @le_str, i64 0, i64 0 - %gt_s = getelementptr [12 x i8]* @gt_str, i64 0, i64 0 - %ge_s = getelementptr [13 x i8]* @ge_str, i64 0, i64 0 - %eq_s = getelementptr [13 x i8]* @eq_str, i64 0, i64 0 - %ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0 + %lt_s = getelementptr [12 x i8], [12 x i8]* @lt_str, i64 0, i64 0 + %le_s = getelementptr [13 x i8], [13 x i8]* @le_str, i64 0, i64 0 + %gt_s = getelementptr [12 x i8], [12 x i8]* @gt_str, i64 0, i64 0 + %ge_s = getelementptr [13 x i8], [13 x i8]* @ge_str, i64 0, i64 0 + %eq_s = getelementptr [13 x i8], [13 x i8]* @eq_str, i64 0, i64 0 + %ne_s = getelementptr [13 x i8], [13 x i8]* @ne_str, i64 0, i64 0 call i32 (i8*, ...)* @printf( i8* %lt_s, i8 %val1 ) ret i32 0 } diff --git a/test/CodeGen/Hexagon/idxload-with-zero-offset.ll b/test/CodeGen/Hexagon/idxload-with-zero-offset.ll index fbf1a3a..f1a9d38 100644 --- a/test/CodeGen/Hexagon/idxload-with-zero-offset.ll +++ b/test/CodeGen/Hexagon/idxload-with-zero-offset.ll @@ -7,8 +7,8 @@ define i32 @load_w(i32* nocapture %a, i32 %n, i32 %m) nounwind { ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#2) entry: %tmp = add i32 %n, %m - %scevgep9 = getelementptr i32* %a, i32 %tmp - %val = load i32* %scevgep9, align 4 + %scevgep9 = getelementptr i32, i32* %a, i32 %tmp + %val = load i32, i32* %scevgep9, align 4 ret i32 %val } @@ -18,8 +18,8 @@ define i16 @load_uh(i16* nocapture %a, i32 %n, i32 %m) nounwind { ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1) entry: %tmp = add i32 %n, %m - %scevgep9 = getelementptr i16* %a, i32 %tmp - %val = load i16* %scevgep9, align 2 + %scevgep9 = getelementptr i16, i16* %a, i32 %tmp + %val = load i16, i16* %scevgep9, align 2 ret i16 %val } @@ -29,8 +29,8 @@ define i32 @load_h(i16* nocapture %a, i32 %n, i32 %m) nounwind { ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1) entry: %tmp = add i32 %n, %m - %scevgep9 = getelementptr i16* %a, i32 %tmp - %val = load i16* %scevgep9, align 2 + %scevgep9 = getelementptr i16, i16* %a, i32 %tmp + %val = load i16, i16* %scevgep9, align 2 %conv = sext i16 %val to i32 ret i32 %conv } @@ -41,8 +41,8 @@ define i8 @load_ub(i8* nocapture %a, i32 %n, i32 %m) nounwind { ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#0) entry: %tmp = add i32 %n, %m - %scevgep9 = getelementptr i8* %a, i32 %tmp - %val = load i8* %scevgep9, align 1 + %scevgep9 = getelementptr i8, i8* %a, i32 %tmp + %val = load i8, i8* %scevgep9, align 1 ret i8 %val } @@ -52,8 +52,8 @@ define i32 @foo_2(i8* nocapture %a, i32 %n, i32 %m) nounwind { ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#0) entry: %tmp = add i32 %n, %m - %scevgep9 = getelementptr i8* %a, i32 %tmp - %val = load i8* %scevgep9, align 1 + %scevgep9 = getelementptr i8, i8* %a, i32 %tmp + %val = load i8, i8* %scevgep9, align 1 %conv = sext i8 %val to i32 ret i32 %conv } @@ -64,7 +64,7 @@ define i64 @load_d(i64* nocapture %a, i32 %n, i32 %m) nounwind { ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#3) entry: %tmp = add i32 %n, %m - %scevgep9 = getelementptr i64* %a, i32 %tmp - %val = load i64* %scevgep9, align 8 + %scevgep9 = getelementptr i64, i64* %a, i32 %tmp + %val = load i64, i64* %scevgep9, align 8 ret i64 %val } diff --git a/test/CodeGen/Hexagon/macint.ll b/test/CodeGen/Hexagon/macint.ll index b3b9d0e..458a537 100644 --- a/test/CodeGen/Hexagon/macint.ll +++ b/test/CodeGen/Hexagon/macint.ll @@ -5,7 +5,7 @@ define i32 @main(i32* %a, i32* %b) nounwind { entry: - %0 = load i32* %a, align 4 + %0 = load i32, i32* %a, align 4 %div = udiv i32 %0, 10000 %rem = urem i32 %div, 10 store i32 %rem, i32* %b, align 4 diff --git a/test/CodeGen/Hexagon/memops.ll b/test/CodeGen/Hexagon/memops.ll index fca1a73..e4a8bf7 100644 --- a/test/CodeGen/Hexagon/memops.ll +++ b/test/CodeGen/Hexagon/memops.ll @@ -4,7 +4,7 @@ define void @memop_unsigned_char_add5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %0 = load i8* %p, align 1 + %0 = load i8, i8* %p, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 5 %conv1 = trunc i32 %add to i8 @@ -16,7 +16,7 @@ define void @memop_unsigned_char_add(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 - %0 = load i8* %p, align 1 + %0 = load i8, i8* %p, align 1 %conv1 = zext i8 %0 to i32 %add = add nsw i32 %conv1, %conv %conv2 = trunc i32 %add to i8 @@ -28,7 +28,7 @@ define void @memop_unsigned_char_sub(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 - %0 = load i8* %p, align 1 + %0 = load i8, i8* %p, align 1 %conv1 = zext i8 %0 to i32 %sub = sub nsw i32 %conv1, %conv %conv2 = trunc i32 %sub to i8 @@ -39,7 +39,7 @@ entry: define void @memop_unsigned_char_or(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %0 = load i8* %p, align 1 + %0 = load i8, i8* %p, align 1 %or3 = or i8 %0, %x store i8 %or3, i8* %p, align 1 ret void @@ -48,7 +48,7 @@ entry: define void @memop_unsigned_char_and(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %0 = load i8* %p, align 1 + %0 = load i8, i8* %p, align 1 %and3 = and i8 %0, %x store i8 %and3, i8* %p, align 1 ret void @@ -57,7 +57,7 @@ entry: define void @memop_unsigned_char_clrbit(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %0 = load i8* %p, align 1 + %0 = load i8, i8* %p, align 1 %conv = zext i8 %0 to i32 %and = and i32 %conv, 223 %conv1 = trunc i32 %and to i8 @@ -68,7 +68,7 @@ entry: define void @memop_unsigned_char_setbit(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %0 = load i8* %p, align 1 + %0 = load i8, i8* %p, align 1 %conv = zext i8 %0 to i32 %or = or i32 %conv, 128 %conv1 = trunc i32 %or to i8 @@ -79,8 +79,8 @@ entry: define void @memop_unsigned_char_add5_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i + %0 = load i8, i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 5 %conv1 = trunc i32 %add to i8 @@ -92,8 +92,8 @@ define void @memop_unsigned_char_add_index(i8* nocapture %p, i32 %i, i8 zeroext entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 - %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i + %0 = load i8, i8* %add.ptr, align 1 %conv1 = zext i8 %0 to i32 %add = add nsw i32 %conv1, %conv %conv2 = trunc i32 %add to i8 @@ -105,8 +105,8 @@ define void @memop_unsigned_char_sub_index(i8* nocapture %p, i32 %i, i8 zeroext entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 - %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i + %0 = load i8, i8* %add.ptr, align 1 %conv1 = zext i8 %0 to i32 %sub = sub nsw i32 %conv1, %conv %conv2 = trunc i32 %sub to i8 @@ -117,8 +117,8 @@ entry: define void @memop_unsigned_char_or_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i + %0 = load i8, i8* %add.ptr, align 1 %or3 = or i8 %0, %x store i8 %or3, i8* %add.ptr, align 1 ret void @@ -127,8 +127,8 @@ entry: define void @memop_unsigned_char_and_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i + %0 = load i8, i8* %add.ptr, align 1 %and3 = and i8 %0, %x store i8 %and3, i8* %add.ptr, align 1 ret void @@ -137,8 +137,8 @@ entry: define void @memop_unsigned_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i + %0 = load i8, i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 %and = and i32 %conv, 223 %conv1 = trunc i32 %and to i8 @@ -149,8 +149,8 @@ entry: define void @memop_unsigned_char_setbit_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i + %0 = load i8, i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 %or = or i32 %conv, 128 %conv1 = trunc i32 %or to i8 @@ -161,8 +161,8 @@ entry: define void @memop_unsigned_char_add5_index5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5 - %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 + %0 = load i8, i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 %add = add nsw i32 %conv, 5 %conv1 = trunc i32 %add to i8 @@ -174,8 +174,8 @@ define void @memop_unsigned_char_add_index5(i8* nocapture %p, i8 zeroext %x) nou entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 - %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 + %0 = load i8, i8* %add.ptr, align 1 %conv1 = zext i8 %0 to i32 %add = add nsw i32 %conv1, %conv %conv2 = trunc i32 %add to i8 @@ -187,8 +187,8 @@ define void @memop_unsigned_char_sub_index5(i8* nocapture %p, i8 zeroext %x) nou entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 - %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 + %0 = load i8, i8* %add.ptr, align 1 %conv1 = zext i8 %0 to i32 %sub = sub nsw i32 %conv1, %conv %conv2 = trunc i32 %sub to i8 @@ -199,8 +199,8 @@ entry: define void @memop_unsigned_char_or_index5(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 + %0 = load i8, i8* %add.ptr, align 1 %or3 = or i8 %0, %x store i8 %or3, i8* %add.ptr, align 1 ret void @@ -209,8 +209,8 @@ entry: define void @memop_unsigned_char_and_index5(i8* nocapture %p, i8 zeroext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 + %0 = load i8, i8* %add.ptr, align 1 %and3 = and i8 %0, %x store i8 %and3, i8* %add.ptr, align 1 ret void @@ -219,8 +219,8 @@ entry: define void @memop_unsigned_char_clrbit_index5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 + %0 = load i8, i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 %and = and i32 %conv, 223 %conv1 = trunc i32 %and to i8 @@ -231,8 +231,8 @@ entry: define void @memop_unsigned_char_setbit_index5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 + %0 = load i8, i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 %or = or i32 %conv, 128 %conv1 = trunc i32 %or to i8 @@ -243,7 +243,7 @@ entry: define void @memop_signed_char_add5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %0 = load i8* %p, align 1 + %0 = load i8, i8* %p, align 1 %conv2 = zext i8 %0 to i32 %add = add nsw i32 %conv2, 5 %conv1 = trunc i32 %add to i8 @@ -255,7 +255,7 @@ define void @memop_signed_char_add(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 - %0 = load i8* %p, align 1 + %0 = load i8, i8* %p, align 1 %conv13 = zext i8 %0 to i32 %add = add nsw i32 %conv13, %conv4 %conv2 = trunc i32 %add to i8 @@ -267,7 +267,7 @@ define void @memop_signed_char_sub(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 - %0 = load i8* %p, align 1 + %0 = load i8, i8* %p, align 1 %conv13 = zext i8 %0 to i32 %sub = sub nsw i32 %conv13, %conv4 %conv2 = trunc i32 %sub to i8 @@ -278,7 +278,7 @@ entry: define void @memop_signed_char_or(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %0 = load i8* %p, align 1 + %0 = load i8, i8* %p, align 1 %or3 = or i8 %0, %x store i8 %or3, i8* %p, align 1 ret void @@ -287,7 +287,7 @@ entry: define void @memop_signed_char_and(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %0 = load i8* %p, align 1 + %0 = load i8, i8* %p, align 1 %and3 = and i8 %0, %x store i8 %and3, i8* %p, align 1 ret void @@ -296,7 +296,7 @@ entry: define void @memop_signed_char_clrbit(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %0 = load i8* %p, align 1 + %0 = load i8, i8* %p, align 1 %conv2 = zext i8 %0 to i32 %and = and i32 %conv2, 223 %conv1 = trunc i32 %and to i8 @@ -307,7 +307,7 @@ entry: define void @memop_signed_char_setbit(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %0 = load i8* %p, align 1 + %0 = load i8, i8* %p, align 1 %conv2 = zext i8 %0 to i32 %or = or i32 %conv2, 128 %conv1 = trunc i32 %or to i8 @@ -318,8 +318,8 @@ entry: define void @memop_signed_char_add5_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i + %0 = load i8, i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 %add = add nsw i32 %conv2, 5 %conv1 = trunc i32 %add to i8 @@ -331,8 +331,8 @@ define void @memop_signed_char_add_index(i8* nocapture %p, i32 %i, i8 signext %x entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 - %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i + %0 = load i8, i8* %add.ptr, align 1 %conv13 = zext i8 %0 to i32 %add = add nsw i32 %conv13, %conv4 %conv2 = trunc i32 %add to i8 @@ -344,8 +344,8 @@ define void @memop_signed_char_sub_index(i8* nocapture %p, i32 %i, i8 signext %x entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 - %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i + %0 = load i8, i8* %add.ptr, align 1 %conv13 = zext i8 %0 to i32 %sub = sub nsw i32 %conv13, %conv4 %conv2 = trunc i32 %sub to i8 @@ -356,8 +356,8 @@ entry: define void @memop_signed_char_or_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i + %0 = load i8, i8* %add.ptr, align 1 %or3 = or i8 %0, %x store i8 %or3, i8* %add.ptr, align 1 ret void @@ -366,8 +366,8 @@ entry: define void @memop_signed_char_and_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i + %0 = load i8, i8* %add.ptr, align 1 %and3 = and i8 %0, %x store i8 %and3, i8* %add.ptr, align 1 ret void @@ -376,8 +376,8 @@ entry: define void @memop_signed_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i + %0 = load i8, i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 %and = and i32 %conv2, 223 %conv1 = trunc i32 %and to i8 @@ -388,8 +388,8 @@ entry: define void @memop_signed_char_setbit_index(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %add.ptr = getelementptr inbounds i8* %p, i32 %i - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i + %0 = load i8, i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 %or = or i32 %conv2, 128 %conv1 = trunc i32 %or to i8 @@ -400,8 +400,8 @@ entry: define void @memop_signed_char_add5_index5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5 - %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 + %0 = load i8, i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 %add = add nsw i32 %conv2, 5 %conv1 = trunc i32 %add to i8 @@ -413,8 +413,8 @@ define void @memop_signed_char_add_index5(i8* nocapture %p, i8 signext %x) nounw entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 - %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 + %0 = load i8, i8* %add.ptr, align 1 %conv13 = zext i8 %0 to i32 %add = add nsw i32 %conv13, %conv4 %conv2 = trunc i32 %add to i8 @@ -426,8 +426,8 @@ define void @memop_signed_char_sub_index5(i8* nocapture %p, i8 signext %x) nounw entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 - %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 + %0 = load i8, i8* %add.ptr, align 1 %conv13 = zext i8 %0 to i32 %sub = sub nsw i32 %conv13, %conv4 %conv2 = trunc i32 %sub to i8 @@ -438,8 +438,8 @@ entry: define void @memop_signed_char_or_index5(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 + %0 = load i8, i8* %add.ptr, align 1 %or3 = or i8 %0, %x store i8 %or3, i8* %add.ptr, align 1 ret void @@ -448,8 +448,8 @@ entry: define void @memop_signed_char_and_index5(i8* nocapture %p, i8 signext %x) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 + %0 = load i8, i8* %add.ptr, align 1 %and3 = and i8 %0, %x store i8 %and3, i8* %add.ptr, align 1 ret void @@ -458,8 +458,8 @@ entry: define void @memop_signed_char_clrbit_index5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 + %0 = load i8, i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 %and = and i32 %conv2, 223 %conv1 = trunc i32 %and to i8 @@ -470,8 +470,8 @@ entry: define void @memop_signed_char_setbit_index5(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %add.ptr = getelementptr inbounds i8* %p, i32 5 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 + %0 = load i8, i8* %add.ptr, align 1 %conv2 = zext i8 %0 to i32 %or = or i32 %conv2, 128 %conv1 = trunc i32 %or to i8 @@ -482,7 +482,7 @@ entry: define void @memop_unsigned_short_add5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %0 = load i16* %p, align 2 + %0 = load i16, i16* %p, align 2 %conv = zext i16 %0 to i32 %add = add nsw i32 %conv, 5 %conv1 = trunc i32 %add to i16 @@ -494,7 +494,7 @@ define void @memop_unsigned_short_add(i16* nocapture %p, i16 zeroext %x) nounwin entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 - %0 = load i16* %p, align 2 + %0 = load i16, i16* %p, align 2 %conv1 = zext i16 %0 to i32 %add = add nsw i32 %conv1, %conv %conv2 = trunc i32 %add to i16 @@ -506,7 +506,7 @@ define void @memop_unsigned_short_sub(i16* nocapture %p, i16 zeroext %x) nounwin entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 - %0 = load i16* %p, align 2 + %0 = load i16, i16* %p, align 2 %conv1 = zext i16 %0 to i32 %sub = sub nsw i32 %conv1, %conv %conv2 = trunc i32 %sub to i16 @@ -517,7 +517,7 @@ entry: define void @memop_unsigned_short_or(i16* nocapture %p, i16 zeroext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %0 = load i16* %p, align 2 + %0 = load i16, i16* %p, align 2 %or3 = or i16 %0, %x store i16 %or3, i16* %p, align 2 ret void @@ -526,7 +526,7 @@ entry: define void @memop_unsigned_short_and(i16* nocapture %p, i16 zeroext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %0 = load i16* %p, align 2 + %0 = load i16, i16* %p, align 2 %and3 = and i16 %0, %x store i16 %and3, i16* %p, align 2 ret void @@ -535,7 +535,7 @@ entry: define void @memop_unsigned_short_clrbit(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %0 = load i16* %p, align 2 + %0 = load i16, i16* %p, align 2 %conv = zext i16 %0 to i32 %and = and i32 %conv, 65503 %conv1 = trunc i32 %and to i16 @@ -546,7 +546,7 @@ entry: define void @memop_unsigned_short_setbit(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %0 = load i16* %p, align 2 + %0 = load i16, i16* %p, align 2 %conv = zext i16 %0 to i32 %or = or i32 %conv, 128 %conv1 = trunc i32 %or to i16 @@ -557,8 +557,8 @@ entry: define void @memop_unsigned_short_add5_index(i16* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i + %0 = load i16, i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 %add = add nsw i32 %conv, 5 %conv1 = trunc i32 %add to i16 @@ -570,8 +570,8 @@ define void @memop_unsigned_short_add_index(i16* nocapture %p, i32 %i, i16 zeroe entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 - %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i + %0 = load i16, i16* %add.ptr, align 2 %conv1 = zext i16 %0 to i32 %add = add nsw i32 %conv1, %conv %conv2 = trunc i32 %add to i16 @@ -583,8 +583,8 @@ define void @memop_unsigned_short_sub_index(i16* nocapture %p, i32 %i, i16 zeroe entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 - %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i + %0 = load i16, i16* %add.ptr, align 2 %conv1 = zext i16 %0 to i32 %sub = sub nsw i32 %conv1, %conv %conv2 = trunc i32 %sub to i16 @@ -595,8 +595,8 @@ entry: define void @memop_unsigned_short_or_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i + %0 = load i16, i16* %add.ptr, align 2 %or3 = or i16 %0, %x store i16 %or3, i16* %add.ptr, align 2 ret void @@ -605,8 +605,8 @@ entry: define void @memop_unsigned_short_and_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i + %0 = load i16, i16* %add.ptr, align 2 %and3 = and i16 %0, %x store i16 %and3, i16* %add.ptr, align 2 ret void @@ -615,8 +615,8 @@ entry: define void @memop_unsigned_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i + %0 = load i16, i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 %and = and i32 %conv, 65503 %conv1 = trunc i32 %and to i16 @@ -627,8 +627,8 @@ entry: define void @memop_unsigned_short_setbit_index(i16* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i + %0 = load i16, i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 %or = or i32 %conv, 128 %conv1 = trunc i32 %or to i16 @@ -639,8 +639,8 @@ entry: define void @memop_unsigned_short_add5_index5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5 - %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 + %0 = load i16, i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 %add = add nsw i32 %conv, 5 %conv1 = trunc i32 %add to i16 @@ -652,8 +652,8 @@ define void @memop_unsigned_short_add_index5(i16* nocapture %p, i16 zeroext %x) entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 - %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 + %0 = load i16, i16* %add.ptr, align 2 %conv1 = zext i16 %0 to i32 %add = add nsw i32 %conv1, %conv %conv2 = trunc i32 %add to i16 @@ -665,8 +665,8 @@ define void @memop_unsigned_short_sub_index5(i16* nocapture %p, i16 zeroext %x) entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 - %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 + %0 = load i16, i16* %add.ptr, align 2 %conv1 = zext i16 %0 to i32 %sub = sub nsw i32 %conv1, %conv %conv2 = trunc i32 %sub to i16 @@ -677,8 +677,8 @@ entry: define void @memop_unsigned_short_or_index5(i16* nocapture %p, i16 zeroext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 + %0 = load i16, i16* %add.ptr, align 2 %or3 = or i16 %0, %x store i16 %or3, i16* %add.ptr, align 2 ret void @@ -687,8 +687,8 @@ entry: define void @memop_unsigned_short_and_index5(i16* nocapture %p, i16 zeroext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 + %0 = load i16, i16* %add.ptr, align 2 %and3 = and i16 %0, %x store i16 %and3, i16* %add.ptr, align 2 ret void @@ -697,8 +697,8 @@ entry: define void @memop_unsigned_short_clrbit_index5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 + %0 = load i16, i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 %and = and i32 %conv, 65503 %conv1 = trunc i32 %and to i16 @@ -709,8 +709,8 @@ entry: define void @memop_unsigned_short_setbit_index5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 + %0 = load i16, i16* %add.ptr, align 2 %conv = zext i16 %0 to i32 %or = or i32 %conv, 128 %conv1 = trunc i32 %or to i16 @@ -721,7 +721,7 @@ entry: define void @memop_signed_short_add5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %0 = load i16* %p, align 2 + %0 = load i16, i16* %p, align 2 %conv2 = zext i16 %0 to i32 %add = add nsw i32 %conv2, 5 %conv1 = trunc i32 %add to i16 @@ -733,7 +733,7 @@ define void @memop_signed_short_add(i16* nocapture %p, i16 signext %x) nounwind entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 - %0 = load i16* %p, align 2 + %0 = load i16, i16* %p, align 2 %conv13 = zext i16 %0 to i32 %add = add nsw i32 %conv13, %conv4 %conv2 = trunc i32 %add to i16 @@ -745,7 +745,7 @@ define void @memop_signed_short_sub(i16* nocapture %p, i16 signext %x) nounwind entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 - %0 = load i16* %p, align 2 + %0 = load i16, i16* %p, align 2 %conv13 = zext i16 %0 to i32 %sub = sub nsw i32 %conv13, %conv4 %conv2 = trunc i32 %sub to i16 @@ -756,7 +756,7 @@ entry: define void @memop_signed_short_or(i16* nocapture %p, i16 signext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %0 = load i16* %p, align 2 + %0 = load i16, i16* %p, align 2 %or3 = or i16 %0, %x store i16 %or3, i16* %p, align 2 ret void @@ -765,7 +765,7 @@ entry: define void @memop_signed_short_and(i16* nocapture %p, i16 signext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %0 = load i16* %p, align 2 + %0 = load i16, i16* %p, align 2 %and3 = and i16 %0, %x store i16 %and3, i16* %p, align 2 ret void @@ -774,7 +774,7 @@ entry: define void @memop_signed_short_clrbit(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %0 = load i16* %p, align 2 + %0 = load i16, i16* %p, align 2 %conv2 = zext i16 %0 to i32 %and = and i32 %conv2, 65503 %conv1 = trunc i32 %and to i16 @@ -785,7 +785,7 @@ entry: define void @memop_signed_short_setbit(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %0 = load i16* %p, align 2 + %0 = load i16, i16* %p, align 2 %conv2 = zext i16 %0 to i32 %or = or i32 %conv2, 128 %conv1 = trunc i32 %or to i16 @@ -796,8 +796,8 @@ entry: define void @memop_signed_short_add5_index(i16* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i + %0 = load i16, i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 %add = add nsw i32 %conv2, 5 %conv1 = trunc i32 %add to i16 @@ -809,8 +809,8 @@ define void @memop_signed_short_add_index(i16* nocapture %p, i32 %i, i16 signext entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 - %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i + %0 = load i16, i16* %add.ptr, align 2 %conv13 = zext i16 %0 to i32 %add = add nsw i32 %conv13, %conv4 %conv2 = trunc i32 %add to i16 @@ -822,8 +822,8 @@ define void @memop_signed_short_sub_index(i16* nocapture %p, i32 %i, i16 signext entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 - %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i + %0 = load i16, i16* %add.ptr, align 2 %conv13 = zext i16 %0 to i32 %sub = sub nsw i32 %conv13, %conv4 %conv2 = trunc i32 %sub to i16 @@ -834,8 +834,8 @@ entry: define void @memop_signed_short_or_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i + %0 = load i16, i16* %add.ptr, align 2 %or3 = or i16 %0, %x store i16 %or3, i16* %add.ptr, align 2 ret void @@ -844,8 +844,8 @@ entry: define void @memop_signed_short_and_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i + %0 = load i16, i16* %add.ptr, align 2 %and3 = and i16 %0, %x store i16 %and3, i16* %add.ptr, align 2 ret void @@ -854,8 +854,8 @@ entry: define void @memop_signed_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i + %0 = load i16, i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 %and = and i32 %conv2, 65503 %conv1 = trunc i32 %and to i16 @@ -866,8 +866,8 @@ entry: define void @memop_signed_short_setbit_index(i16* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %add.ptr = getelementptr inbounds i16* %p, i32 %i - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i + %0 = load i16, i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 %or = or i32 %conv2, 128 %conv1 = trunc i32 %or to i16 @@ -878,8 +878,8 @@ entry: define void @memop_signed_short_add5_index5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5 - %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 + %0 = load i16, i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 %add = add nsw i32 %conv2, 5 %conv1 = trunc i32 %add to i16 @@ -891,8 +891,8 @@ define void @memop_signed_short_add_index5(i16* nocapture %p, i16 signext %x) no entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 - %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 + %0 = load i16, i16* %add.ptr, align 2 %conv13 = zext i16 %0 to i32 %add = add nsw i32 %conv13, %conv4 %conv2 = trunc i32 %add to i16 @@ -904,8 +904,8 @@ define void @memop_signed_short_sub_index5(i16* nocapture %p, i16 signext %x) no entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 - %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 + %0 = load i16, i16* %add.ptr, align 2 %conv13 = zext i16 %0 to i32 %sub = sub nsw i32 %conv13, %conv4 %conv2 = trunc i32 %sub to i16 @@ -916,8 +916,8 @@ entry: define void @memop_signed_short_or_index5(i16* nocapture %p, i16 signext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 + %0 = load i16, i16* %add.ptr, align 2 %or3 = or i16 %0, %x store i16 %or3, i16* %add.ptr, align 2 ret void @@ -926,8 +926,8 @@ entry: define void @memop_signed_short_and_index5(i16* nocapture %p, i16 signext %x) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 + %0 = load i16, i16* %add.ptr, align 2 %and3 = and i16 %0, %x store i16 %and3, i16* %add.ptr, align 2 ret void @@ -936,8 +936,8 @@ entry: define void @memop_signed_short_clrbit_index5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 + %0 = load i16, i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 %and = and i32 %conv2, 65503 %conv1 = trunc i32 %and to i16 @@ -948,8 +948,8 @@ entry: define void @memop_signed_short_setbit_index5(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %add.ptr = getelementptr inbounds i16* %p, i32 5 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 + %0 = load i16, i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 %or = or i32 %conv2, 128 %conv1 = trunc i32 %or to i16 @@ -960,7 +960,7 @@ entry: define void @memop_signed_int_add5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %0 = load i32* %p, align 4 + %0 = load i32, i32* %p, align 4 %add = add i32 %0, 5 store i32 %add, i32* %p, align 4 ret void @@ -969,7 +969,7 @@ entry: define void @memop_signed_int_add(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4 + %0 = load i32, i32* %p, align 4 %add = add i32 %0, %x store i32 %add, i32* %p, align 4 ret void @@ -978,7 +978,7 @@ entry: define void @memop_signed_int_sub(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4 + %0 = load i32, i32* %p, align 4 %sub = sub i32 %0, %x store i32 %sub, i32* %p, align 4 ret void @@ -987,7 +987,7 @@ entry: define void @memop_signed_int_or(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4 + %0 = load i32, i32* %p, align 4 %or = or i32 %0, %x store i32 %or, i32* %p, align 4 ret void @@ -996,7 +996,7 @@ entry: define void @memop_signed_int_and(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4 + %0 = load i32, i32* %p, align 4 %and = and i32 %0, %x store i32 %and, i32* %p, align 4 ret void @@ -1005,7 +1005,7 @@ entry: define void @memop_signed_int_clrbit(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %0 = load i32* %p, align 4 + %0 = load i32, i32* %p, align 4 %and = and i32 %0, -33 store i32 %and, i32* %p, align 4 ret void @@ -1014,7 +1014,7 @@ entry: define void @memop_signed_int_setbit(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %0 = load i32* %p, align 4 + %0 = load i32, i32* %p, align 4 %or = or i32 %0, 128 store i32 %or, i32* %p, align 4 ret void @@ -1023,8 +1023,8 @@ entry: define void @memop_signed_int_add5_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i + %0 = load i32, i32* %add.ptr, align 4 %add = add i32 %0, 5 store i32 %add, i32* %add.ptr, align 4 ret void @@ -1033,8 +1033,8 @@ entry: define void @memop_signed_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i + %0 = load i32, i32* %add.ptr, align 4 %add = add i32 %0, %x store i32 %add, i32* %add.ptr, align 4 ret void @@ -1043,8 +1043,8 @@ entry: define void @memop_signed_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i + %0 = load i32, i32* %add.ptr, align 4 %sub = sub i32 %0, %x store i32 %sub, i32* %add.ptr, align 4 ret void @@ -1053,8 +1053,8 @@ entry: define void @memop_signed_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i + %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, %x store i32 %or, i32* %add.ptr, align 4 ret void @@ -1063,8 +1063,8 @@ entry: define void @memop_signed_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i + %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, %x store i32 %and, i32* %add.ptr, align 4 ret void @@ -1073,8 +1073,8 @@ entry: define void @memop_signed_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i + %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, -33 store i32 %and, i32* %add.ptr, align 4 ret void @@ -1083,8 +1083,8 @@ entry: define void @memop_signed_int_setbit_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i + %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, 128 store i32 %or, i32* %add.ptr, align 4 ret void @@ -1093,8 +1093,8 @@ entry: define void @memop_signed_int_add5_index5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5 - %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 + %0 = load i32, i32* %add.ptr, align 4 %add = add i32 %0, 5 store i32 %add, i32* %add.ptr, align 4 ret void @@ -1103,8 +1103,8 @@ entry: define void @memop_signed_int_add_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 + %0 = load i32, i32* %add.ptr, align 4 %add = add i32 %0, %x store i32 %add, i32* %add.ptr, align 4 ret void @@ -1113,8 +1113,8 @@ entry: define void @memop_signed_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 + %0 = load i32, i32* %add.ptr, align 4 %sub = sub i32 %0, %x store i32 %sub, i32* %add.ptr, align 4 ret void @@ -1123,8 +1123,8 @@ entry: define void @memop_signed_int_or_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 + %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, %x store i32 %or, i32* %add.ptr, align 4 ret void @@ -1133,8 +1133,8 @@ entry: define void @memop_signed_int_and_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 + %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, %x store i32 %and, i32* %add.ptr, align 4 ret void @@ -1143,8 +1143,8 @@ entry: define void @memop_signed_int_clrbit_index5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 + %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, -33 store i32 %and, i32* %add.ptr, align 4 ret void @@ -1153,8 +1153,8 @@ entry: define void @memop_signed_int_setbit_index5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 + %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, 128 store i32 %or, i32* %add.ptr, align 4 ret void @@ -1163,7 +1163,7 @@ entry: define void @memop_unsigned_int_add5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %0 = load i32* %p, align 4 + %0 = load i32, i32* %p, align 4 %add = add nsw i32 %0, 5 store i32 %add, i32* %p, align 4 ret void @@ -1172,7 +1172,7 @@ entry: define void @memop_unsigned_int_add(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4 + %0 = load i32, i32* %p, align 4 %add = add nsw i32 %0, %x store i32 %add, i32* %p, align 4 ret void @@ -1181,7 +1181,7 @@ entry: define void @memop_unsigned_int_sub(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4 + %0 = load i32, i32* %p, align 4 %sub = sub nsw i32 %0, %x store i32 %sub, i32* %p, align 4 ret void @@ -1190,7 +1190,7 @@ entry: define void @memop_unsigned_int_or(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4 + %0 = load i32, i32* %p, align 4 %or = or i32 %0, %x store i32 %or, i32* %p, align 4 ret void @@ -1199,7 +1199,7 @@ entry: define void @memop_unsigned_int_and(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %0 = load i32* %p, align 4 + %0 = load i32, i32* %p, align 4 %and = and i32 %0, %x store i32 %and, i32* %p, align 4 ret void @@ -1208,7 +1208,7 @@ entry: define void @memop_unsigned_int_clrbit(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %0 = load i32* %p, align 4 + %0 = load i32, i32* %p, align 4 %and = and i32 %0, -33 store i32 %and, i32* %p, align 4 ret void @@ -1217,7 +1217,7 @@ entry: define void @memop_unsigned_int_setbit(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %0 = load i32* %p, align 4 + %0 = load i32, i32* %p, align 4 %or = or i32 %0, 128 store i32 %or, i32* %p, align 4 ret void @@ -1226,8 +1226,8 @@ entry: define void @memop_unsigned_int_add5_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 - %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i + %0 = load i32, i32* %add.ptr, align 4 %add = add nsw i32 %0, 5 store i32 %add, i32* %add.ptr, align 4 ret void @@ -1236,8 +1236,8 @@ entry: define void @memop_unsigned_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i + %0 = load i32, i32* %add.ptr, align 4 %add = add nsw i32 %0, %x store i32 %add, i32* %add.ptr, align 4 ret void @@ -1246,8 +1246,8 @@ entry: define void @memop_unsigned_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i + %0 = load i32, i32* %add.ptr, align 4 %sub = sub nsw i32 %0, %x store i32 %sub, i32* %add.ptr, align 4 ret void @@ -1256,8 +1256,8 @@ entry: define void @memop_unsigned_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i + %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, %x store i32 %or, i32* %add.ptr, align 4 ret void @@ -1266,8 +1266,8 @@ entry: define void @memop_unsigned_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i + %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, %x store i32 %and, i32* %add.ptr, align 4 ret void @@ -1276,8 +1276,8 @@ entry: define void @memop_unsigned_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i + %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, -33 store i32 %and, i32* %add.ptr, align 4 ret void @@ -1286,8 +1286,8 @@ entry: define void @memop_unsigned_int_setbit_index(i32* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %add.ptr = getelementptr inbounds i32* %p, i32 %i - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i + %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, 128 store i32 %or, i32* %add.ptr, align 4 ret void @@ -1296,8 +1296,8 @@ entry: define void @memop_unsigned_int_add5_index5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5 - %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 + %0 = load i32, i32* %add.ptr, align 4 %add = add nsw i32 %0, 5 store i32 %add, i32* %add.ptr, align 4 ret void @@ -1306,8 +1306,8 @@ entry: define void @memop_unsigned_int_add_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 + %0 = load i32, i32* %add.ptr, align 4 %add = add nsw i32 %0, %x store i32 %add, i32* %add.ptr, align 4 ret void @@ -1316,8 +1316,8 @@ entry: define void @memop_unsigned_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 + %0 = load i32, i32* %add.ptr, align 4 %sub = sub nsw i32 %0, %x store i32 %sub, i32* %add.ptr, align 4 ret void @@ -1326,8 +1326,8 @@ entry: define void @memop_unsigned_int_or_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 + %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, %x store i32 %or, i32* %add.ptr, align 4 ret void @@ -1336,8 +1336,8 @@ entry: define void @memop_unsigned_int_and_index5(i32* nocapture %p, i32 %x) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}} - %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 + %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, %x store i32 %and, i32* %add.ptr, align 4 ret void @@ -1346,8 +1346,8 @@ entry: define void @memop_unsigned_int_clrbit_index5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) - %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 + %0 = load i32, i32* %add.ptr, align 4 %and = and i32 %0, -33 store i32 %and, i32* %add.ptr, align 4 ret void @@ -1356,8 +1356,8 @@ entry: define void @memop_unsigned_int_setbit_index5(i32* nocapture %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) - %add.ptr = getelementptr inbounds i32* %p, i32 5 - %0 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 + %0 = load i32, i32* %add.ptr, align 4 %or = or i32 %0, 128 store i32 %or, i32* %add.ptr, align 4 ret void diff --git a/test/CodeGen/Hexagon/memops1.ll b/test/CodeGen/Hexagon/memops1.ll index 2babdc8..37e885b 100644 --- a/test/CodeGen/Hexagon/memops1.ll +++ b/test/CodeGen/Hexagon/memops1.ll @@ -7,9 +7,9 @@ entry: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#40){{ *}}-={{ *}}#1 %p.addr = alloca i32*, align 4 store i32* %p, i32** %p.addr, align 4 - %0 = load i32** %p.addr, align 4 - %add.ptr = getelementptr inbounds i32* %0, i32 10 - %1 = load i32* %add.ptr, align 4 + %0 = load i32*, i32** %p.addr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %0, i32 10 + %1 = load i32, i32* %add.ptr, align 4 %sub = sub nsw i32 %1, 1 store i32 %sub, i32* %add.ptr, align 4 ret void @@ -22,11 +22,11 @@ entry: %i.addr = alloca i32, align 4 store i32* %p, i32** %p.addr, align 4 store i32 %i, i32* %i.addr, align 4 - %0 = load i32** %p.addr, align 4 - %1 = load i32* %i.addr, align 4 - %add.ptr = getelementptr inbounds i32* %0, i32 %1 - %add.ptr1 = getelementptr inbounds i32* %add.ptr, i32 10 - %2 = load i32* %add.ptr1, align 4 + %0 = load i32*, i32** %p.addr, align 4 + %1 = load i32, i32* %i.addr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %0, i32 %1 + %add.ptr1 = getelementptr inbounds i32, i32* %add.ptr, i32 10 + %2 = load i32, i32* %add.ptr1, align 4 %sub = sub nsw i32 %2, 1 store i32 %sub, i32* %add.ptr1, align 4 ret void diff --git a/test/CodeGen/Hexagon/memops2.ll b/test/CodeGen/Hexagon/memops2.ll index d6d1a50..f9f8a24 100644 --- a/test/CodeGen/Hexagon/memops2.ll +++ b/test/CodeGen/Hexagon/memops2.ll @@ -5,8 +5,8 @@ define void @f(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}#1 - %add.ptr = getelementptr inbounds i16* %p, i32 10 - %0 = load i16* %add.ptr, align 2 + %add.ptr = getelementptr inbounds i16, i16* %p, i32 10 + %0 = load i16, i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 %sub = add nsw i32 %conv2, 65535 %conv1 = trunc i32 %sub to i16 @@ -18,8 +18,8 @@ define void @g(i16* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}#1 %add.ptr.sum = add i32 %i, 10 - %add.ptr1 = getelementptr inbounds i16* %p, i32 %add.ptr.sum - %0 = load i16* %add.ptr1, align 2 + %add.ptr1 = getelementptr inbounds i16, i16* %p, i32 %add.ptr.sum + %0 = load i16, i16* %add.ptr1, align 2 %conv3 = zext i16 %0 to i32 %sub = add nsw i32 %conv3, 65535 %conv2 = trunc i32 %sub to i16 diff --git a/test/CodeGen/Hexagon/memops3.ll b/test/CodeGen/Hexagon/memops3.ll index d9e4e8f..6cd7fdc 100644 --- a/test/CodeGen/Hexagon/memops3.ll +++ b/test/CodeGen/Hexagon/memops3.ll @@ -5,8 +5,8 @@ define void @f(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}#1 - %add.ptr = getelementptr inbounds i8* %p, i32 10 - %0 = load i8* %add.ptr, align 1 + %add.ptr = getelementptr inbounds i8, i8* %p, i32 10 + %0 = load i8, i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 %sub = add nsw i32 %conv, 255 %conv1 = trunc i32 %sub to i8 @@ -18,8 +18,8 @@ define void @g(i8* nocapture %p, i32 %i) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}#1 %add.ptr.sum = add i32 %i, 10 - %add.ptr1 = getelementptr inbounds i8* %p, i32 %add.ptr.sum - %0 = load i8* %add.ptr1, align 1 + %add.ptr1 = getelementptr inbounds i8, i8* %p, i32 %add.ptr.sum + %0 = load i8, i8* %add.ptr1, align 1 %conv = zext i8 %0 to i32 %sub = add nsw i32 %conv, 255 %conv2 = trunc i32 %sub to i8 diff --git a/test/CodeGen/Hexagon/misaligned-access.ll b/test/CodeGen/Hexagon/misaligned-access.ll index 4dafb44..f4b0cb9 100644 --- a/test/CodeGen/Hexagon/misaligned-access.ll +++ b/test/CodeGen/Hexagon/misaligned-access.ll @@ -7,10 +7,10 @@ declare i32 @_hi(i64) #1 define i32 @CSDRSEARCH_executeSearchManager() #0 { entry: %temp = alloca i32, align 4 - %0 = load i32* @temp1, align 4 + %0 = load i32, i32* @temp1, align 4 store i32 %0, i32* %temp, align 4 %1 = bitcast i32* %temp to i64* - %2 = load i64* %1, align 8 + %2 = load i64, i64* %1, align 8 %call = call i32 @_hi(i64 %2) ret i32 %call } diff --git a/test/CodeGen/Hexagon/mpy.ll b/test/CodeGen/Hexagon/mpy.ll index d5c5ae3..3ecf7d4 100644 --- a/test/CodeGen/Hexagon/mpy.ll +++ b/test/CodeGen/Hexagon/mpy.ll @@ -9,10 +9,10 @@ entry: store i32 %acc, i32* %acc.addr, align 4 store i32 %num, i32* %num.addr, align 4 store i32 %num2, i32* %num2.addr, align 4 - %0 = load i32* %num.addr, align 4 - %1 = load i32* %acc.addr, align 4 + %0 = load i32, i32* %num.addr, align 4 + %1 = load i32, i32* %acc.addr, align 4 %mul = mul nsw i32 %0, %1 - %2 = load i32* %num2.addr, align 4 + %2 = load i32, i32* %num2.addr, align 4 %add = add nsw i32 %mul, %2 store i32 %add, i32* %num.addr, align 4 ret void diff --git a/test/CodeGen/Hexagon/newvaluejump.ll b/test/CodeGen/Hexagon/newvaluejump.ll index 9c7ca55..3e1ee17 100644 --- a/test/CodeGen/Hexagon/newvaluejump.ll +++ b/test/CodeGen/Hexagon/newvaluejump.ll @@ -9,10 +9,10 @@ entry: ; CHECK: if (cmp.eq(r{{[0-9]+}}.new, #0)) jump{{.}} %addr1 = alloca i32, align 4 %addr2 = alloca i32, align 4 - %0 = load i32* @i, align 4 + %0 = load i32, i32* @i, align 4 store i32 %0, i32* %addr1, align 4 call void @bar(i32 1, i32 2) - %1 = load i32* @j, align 4 + %1 = load i32, i32* @j, align 4 %tobool = icmp ne i32 %1, 0 br i1 %tobool, label %if.then, label %if.else diff --git a/test/CodeGen/Hexagon/newvaluejump2.ll b/test/CodeGen/Hexagon/newvaluejump2.ll index 3d50ea5..36a0db1 100644 --- a/test/CodeGen/Hexagon/newvaluejump2.ll +++ b/test/CodeGen/Hexagon/newvaluejump2.ll @@ -7,9 +7,9 @@ define i32 @main() nounwind { entry: ; CHECK: if (cmp.gt(r{{[0-9]+}}.new, r{{[0-9]+}})) jump:{{[t|nt]}} .LBB{{[0-9]+}}_{{[0-9]+}} %Reg2 = alloca i8, align 1 - %0 = load i8* %Reg2, align 1 + %0 = load i8, i8* %Reg2, align 1 %conv0 = zext i8 %0 to i32 - %1 = load i8* @Reg, align 1 + %1 = load i8, i8* @Reg, align 1 %conv1 = zext i8 %1 to i32 %tobool = icmp sle i32 %conv0, %conv1 br i1 %tobool, label %if.then, label %if.else diff --git a/test/CodeGen/Hexagon/newvaluestore.ll b/test/CodeGen/Hexagon/newvaluestore.ll index 93cf347..13cbba2 100644 --- a/test/CodeGen/Hexagon/newvaluestore.ll +++ b/test/CodeGen/Hexagon/newvaluestore.ll @@ -11,11 +11,11 @@ entry: %number1 = alloca i32, align 4 %number2 = alloca i32, align 4 %number3 = alloca i32, align 4 - %0 = load i32 * @i, align 4 + %0 = load i32 , i32 * @i, align 4 store i32 %0, i32* %number1, align 4 - %1 = load i32 * @j, align 4 + %1 = load i32 , i32 * @j, align 4 store i32 %1, i32* %number2, align 4 - %2 = load i32 * @k, align 4 + %2 = load i32 , i32 * @k, align 4 store i32 %2, i32* %number3, align 4 ret i32 %0 } diff --git a/test/CodeGen/Hexagon/opt-fabs.ll b/test/CodeGen/Hexagon/opt-fabs.ll index 31b56fd..da657e4 100644 --- a/test/CodeGen/Hexagon/opt-fabs.ll +++ b/test/CodeGen/Hexagon/opt-fabs.ll @@ -7,7 +7,7 @@ define float @my_fabsf(float %x) nounwind { entry: %x.addr = alloca float, align 4 store float %x, float* %x.addr, align 4 - %0 = load float* %x.addr, align 4 + %0 = load float, float* %x.addr, align 4 %call = call float @fabsf(float %0) readnone ret float %call } diff --git a/test/CodeGen/Hexagon/opt-fneg.ll b/test/CodeGen/Hexagon/opt-fneg.ll index 479b4b6..9789578 100644 --- a/test/CodeGen/Hexagon/opt-fneg.ll +++ b/test/CodeGen/Hexagon/opt-fneg.ll @@ -6,7 +6,7 @@ entry: ; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #31) %x.addr = alloca float, align 4 store float %x, float* %x.addr, align 4 - %0 = load float* %x.addr, align 4 + %0 = load float, float* %x.addr, align 4 %sub = fsub float -0.000000e+00, %0 ret float %sub } diff --git a/test/CodeGen/Hexagon/postinc-load.ll b/test/CodeGen/Hexagon/postinc-load.ll index 855a347..a9d9879 100644 --- a/test/CodeGen/Hexagon/postinc-load.ll +++ b/test/CodeGen/Hexagon/postinc-load.ll @@ -12,13 +12,13 @@ for.body: %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ] %arrayidx1.phi = phi i16* [ %b, %entry ], [ %arrayidx1.inc, %for.body ] %sum.03 = phi i32 [ 0, %entry ], [ %add2, %for.body ] - %0 = load i32* %arrayidx.phi, align 4 - %1 = load i16* %arrayidx1.phi, align 2 + %0 = load i32, i32* %arrayidx.phi, align 4 + %1 = load i16, i16* %arrayidx1.phi, align 2 %conv = sext i16 %1 to i32 %add = add i32 %0, %sum.03 %add2 = add i32 %add, %conv - %arrayidx.inc = getelementptr i32* %arrayidx.phi, i32 1 - %arrayidx1.inc = getelementptr i16* %arrayidx1.phi, i32 1 + %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1 + %arrayidx1.inc = getelementptr i16, i16* %arrayidx1.phi, i32 1 %lsr.iv.next = add i32 %lsr.iv, -1 %exitcond = icmp eq i32 %lsr.iv.next, 0 br i1 %exitcond, label %for.end, label %for.body diff --git a/test/CodeGen/Hexagon/postinc-store.ll b/test/CodeGen/Hexagon/postinc-store.ll index 99a3a58..6315ca1 100644 --- a/test/CodeGen/Hexagon/postinc-store.ll +++ b/test/CodeGen/Hexagon/postinc-store.ll @@ -11,15 +11,15 @@ for.body: ; preds = %for.body, %entry %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ 10, %entry ] %arrayidx.phi = phi i32* [ %a, %entry ], [ %arrayidx.inc, %for.body ] %arrayidx1.phi = phi i16* [ %b, %entry ], [ %arrayidx1.inc, %for.body ] - %0 = load i32* %arrayidx.phi, align 4 - %1 = load i16* %arrayidx1.phi, align 2 + %0 = load i32, i32* %arrayidx.phi, align 4 + %1 = load i16, i16* %arrayidx1.phi, align 2 %conv = sext i16 %1 to i32 %factor = mul i32 %0, 2 %add3 = add i32 %factor, %conv store i32 %add3, i32* %arrayidx.phi, align 4 - %arrayidx.inc = getelementptr i32* %arrayidx.phi, i32 1 - %arrayidx1.inc = getelementptr i16* %arrayidx1.phi, i32 1 + %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1 + %arrayidx1.inc = getelementptr i16, i16* %arrayidx1.phi, i32 1 %lsr.iv.next = add i32 %lsr.iv, -1 %exitcond = icmp eq i32 %lsr.iv.next, 0 br i1 %exitcond, label %for.end, label %for.body diff --git a/test/CodeGen/Hexagon/pred-absolute-store.ll b/test/CodeGen/Hexagon/pred-absolute-store.ll index 64635b1..3e5e982 100644 --- a/test/CodeGen/Hexagon/pred-absolute-store.ll +++ b/test/CodeGen/Hexagon/pred-absolute-store.ll @@ -1,8 +1,7 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; RUN: llc -march=hexagon < %s | FileCheck %s ; Check that we are able to predicate instructions with abosolute ; addressing mode. - -; CHECK: if{{ *}}(p{{[0-3]+}}.new){{ *}}memw(##gvar){{ *}}={{ *}}r{{[0-9]+}} +; CHECK: if ({{!*}}p{{[0-2]}}.new) memw(##gvar) = r{{[0-9]+}} @gvar = external global i32 define i32 @test2(i32 %a, i32 %b) nounwind { diff --git a/test/CodeGen/Hexagon/pred-gp.ll b/test/CodeGen/Hexagon/pred-gp.ll index 299bd86..3868e09 100644 --- a/test/CodeGen/Hexagon/pred-gp.ll +++ b/test/CodeGen/Hexagon/pred-gp.ll @@ -14,11 +14,11 @@ entry: br i1 %cmp, label %if.then, label %entry.if.end_crit_edge entry.if.end_crit_edge: - %.pre = load i32* @c, align 4 + %.pre = load i32, i32* @c, align 4 br label %if.end if.then: - %0 = load i32* @d, align 4 + %0 = load i32, i32* @d, align 4 store i32 %0, i32* @c, align 4 br label %if.end diff --git a/test/CodeGen/Hexagon/pred-instrs.ll b/test/CodeGen/Hexagon/pred-instrs.ll index 800073e..e0a75f1 100644 --- a/test/CodeGen/Hexagon/pred-instrs.ll +++ b/test/CodeGen/Hexagon/pred-instrs.ll @@ -25,6 +25,6 @@ if.else: ; preds = %entry if.end: ; preds = %if.else, %if.then %storemerge = phi i32 [ %and, %if.else ], [ %shl, %if.then ] store i32 %storemerge, i32* @a, align 4 - %0 = load i32* @d, align 4 + %0 = load i32, i32* @d, align 4 ret i32 %0 } diff --git a/test/CodeGen/Hexagon/remove_lsr.ll b/test/CodeGen/Hexagon/remove_lsr.ll index 3128dbb..3b85c48 100644 --- a/test/CodeGen/Hexagon/remove_lsr.ll +++ b/test/CodeGen/Hexagon/remove_lsr.ll @@ -21,11 +21,11 @@ define void @foo(%union.vect64* nocapture %sss_extracted_bit_rx_data_ptr, i8* nocapture %scr_s_even_code_ptr, i8* nocapture %scr_s_odd_code_ptr) nounwind { entry: - %scevgep = getelementptr %union.vect64* %sss_extracted_bit_rx_data_ptr, i32 1 - %scevgep28 = getelementptr %union.vect32* %s_odd, i32 1 - %scevgep32 = getelementptr %union.vect32* %s_even, i32 1 - %scevgep36 = getelementptr i8* %scr_s_odd_code_ptr, i32 1 - %scevgep39 = getelementptr i8* %scr_s_even_code_ptr, i32 1 + %scevgep = getelementptr %union.vect64, %union.vect64* %sss_extracted_bit_rx_data_ptr, i32 1 + %scevgep28 = getelementptr %union.vect32, %union.vect32* %s_odd, i32 1 + %scevgep32 = getelementptr %union.vect32, %union.vect32* %s_even, i32 1 + %scevgep36 = getelementptr i8, i8* %scr_s_odd_code_ptr, i32 1 + %scevgep39 = getelementptr i8, i8* %scr_s_even_code_ptr, i32 1 br label %for.body for.body: ; preds = %for.body, %entry @@ -54,16 +54,16 @@ for.body: ; preds = %for.body, %entry %7 = trunc i64 %6 to i32 %8 = tail call i32 @llvm.hexagon.C2.mux(i32 %conv8, i32 %5, i32 %7) store i32 %8, i32* %lsr.iv2931, align 4 - %srcval = load i64* %lsr.iv27, align 8 - %9 = load i8* %lsr.iv40, align 1 - %10 = load i8* %lsr.iv37, align 1 + %srcval = load i64, i64* %lsr.iv27, align 8 + %9 = load i8, i8* %lsr.iv40, align 1 + %10 = load i8, i8* %lsr.iv37, align 1 %lftr.wideiv = trunc i32 %lsr.iv42 to i8 %exitcond = icmp eq i8 %lftr.wideiv, 32 - %scevgep26 = getelementptr %union.vect64* %lsr.iv, i32 1 - %scevgep30 = getelementptr %union.vect32* %lsr.iv29, i32 1 - %scevgep34 = getelementptr %union.vect32* %lsr.iv33, i32 1 - %scevgep38 = getelementptr i8* %lsr.iv37, i32 1 - %scevgep41 = getelementptr i8* %lsr.iv40, i32 1 + %scevgep26 = getelementptr %union.vect64, %union.vect64* %lsr.iv, i32 1 + %scevgep30 = getelementptr %union.vect32, %union.vect32* %lsr.iv29, i32 1 + %scevgep34 = getelementptr %union.vect32, %union.vect32* %lsr.iv33, i32 1 + %scevgep38 = getelementptr i8, i8* %lsr.iv37, i32 1 + %scevgep41 = getelementptr i8, i8* %lsr.iv40, i32 1 %lsr.iv.next = add i32 %lsr.iv42, 1 br i1 %exitcond, label %for.end, label %for.body diff --git a/test/CodeGen/Hexagon/static.ll b/test/CodeGen/Hexagon/static.ll index 683a4c2..760b8b5 100644 --- a/test/CodeGen/Hexagon/static.ll +++ b/test/CodeGen/Hexagon/static.ll @@ -10,10 +10,10 @@ define void @foo() nounwind { entry: - %0 = load i32* @num, align 4 - %1 = load i32* @acc, align 4 + %0 = load i32, i32* @num, align 4 + %1 = load i32, i32* @acc, align 4 %mul = mul nsw i32 %0, %1 - %2 = load i32* @val, align 4 + %2 = load i32, i32* @val, align 4 %add = add nsw i32 %mul, %2 store i32 %add, i32* @num, align 4 ret void diff --git a/test/CodeGen/Hexagon/struct_args.ll b/test/CodeGen/Hexagon/struct_args.ll index f91300b..95b76c7 100644 --- a/test/CodeGen/Hexagon/struct_args.ll +++ b/test/CodeGen/Hexagon/struct_args.ll @@ -8,7 +8,7 @@ define void @foo() nounwind { entry: - %0 = load i64* bitcast (%struct.small* @s1 to i64*), align 1 + %0 = load i64, i64* bitcast (%struct.small* @s1 to i64*), align 1 call void @bar(i64 %0) ret void } diff --git a/test/CodeGen/Hexagon/struct_args_large.ll b/test/CodeGen/Hexagon/struct_args_large.ll index db87d9e..1438d73 100644 --- a/test/CodeGen/Hexagon/struct_args_large.ll +++ b/test/CodeGen/Hexagon/struct_args_large.ll @@ -1,4 +1,5 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; XFAIL: +; RUN: llc -march=hexagon < %s | FileCheck %s ; CHECK: r[[T0:[0-9]+]] = CONST32(#s2) ; CHECK: memw(r29+#0) = r{{.}} ; CHECK: memw(r29+#8) = r{{.}} diff --git a/test/CodeGen/Hexagon/tfr-to-combine.ll b/test/CodeGen/Hexagon/tfr-to-combine.ll index e3057cd..d22d685 100644 --- a/test/CodeGen/Hexagon/tfr-to-combine.ll +++ b/test/CodeGen/Hexagon/tfr-to-combine.ll @@ -20,7 +20,7 @@ define i64 @test2() #0 { ; CHECK: combine(#0, r{{[0-9]+}}) entry: store i16 0, i16* @a, align 2 - %0 = load i16* @c, align 2 + %0 = load i16, i16* @c, align 2 %conv2 = zext i16 %0 to i64 ret i64 %conv2 } diff --git a/test/CodeGen/Hexagon/union-1.ll b/test/CodeGen/Hexagon/union-1.ll index fe79f95..1d93797 100644 --- a/test/CodeGen/Hexagon/union-1.ll +++ b/test/CodeGen/Hexagon/union-1.ll @@ -2,13 +2,15 @@ ; CHECK: word ; CHECK-NOT: combine(#0 ; CHECK: jump bar +; XFAIL: * +; Disable this test temporarily. define void @word(i32* nocapture %a) nounwind { entry: - %0 = load i32* %a, align 4 + %0 = load i32, i32* %a, align 4 %1 = zext i32 %0 to i64 - %add.ptr = getelementptr inbounds i32* %a, i32 1 - %2 = load i32* %add.ptr, align 4 + %add.ptr = getelementptr inbounds i32, i32* %a, i32 1 + %2 = load i32, i32* %add.ptr, align 4 %3 = zext i32 %2 to i64 %4 = shl nuw i64 %3, 32 %ins = or i64 %4, %1 diff --git a/test/CodeGen/Hexagon/vaddh.ll b/test/CodeGen/Hexagon/vaddh.ll index 01d2041..88194b7 100644 --- a/test/CodeGen/Hexagon/vaddh.ll +++ b/test/CodeGen/Hexagon/vaddh.ll @@ -6,8 +6,8 @@ define void @foo() nounwind { entry: - %0 = load i32* @j, align 4 - %1 = load i32* @k, align 4 + %0 = load i32, i32* @j, align 4 + %1 = load i32, i32* @k, align 4 %2 = call i32 @llvm.hexagon.A2.svaddh(i32 %0, i32 %1) store i32 %2, i32* @k, align 4 ret void diff --git a/test/CodeGen/Hexagon/validate-offset.ll b/test/CodeGen/Hexagon/validate-offset.ll index 9e7d0aa..8de006c 100644 --- a/test/CodeGen/Hexagon/validate-offset.ll +++ b/test/CodeGen/Hexagon/validate-offset.ll @@ -11,26 +11,26 @@ entry: %b.addr = alloca i32, align 4 store i32 %a, i32* %a.addr, align 4 store i32 %b, i32* %b.addr, align 4 - %0 = load i32* %a.addr, align 4 - %1 = load i32* %b.addr, align 4 + %0 = load i32, i32* %a.addr, align 4 + %1 = load i32, i32* %b.addr, align 4 %cmp = icmp sgt i32 %0, %1 br i1 %cmp, label %if.then, label %if.else if.then: - %2 = load i32* %a.addr, align 4 - %3 = load i32* %b.addr, align 4 + %2 = load i32, i32* %a.addr, align 4 + %3 = load i32, i32* %b.addr, align 4 %add = add nsw i32 %2, %3 store i32 %add, i32* %retval br label %return if.else: - %4 = load i32* %a.addr, align 4 - %5 = load i32* %b.addr, align 4 + %4 = load i32, i32* %a.addr, align 4 + %5 = load i32, i32* %b.addr, align 4 %sub = sub nsw i32 %4, %5 store i32 %sub, i32* %retval br label %return return: - %6 = load i32* %retval + %6 = load i32, i32* %retval ret i32 %6 } diff --git a/test/CodeGen/Hexagon/vect/vect-anyextend.ll b/test/CodeGen/Hexagon/vect/vect-anyextend.ll new file mode 100644 index 0000000..fe5fe84 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-anyextend.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=hexagon < %s +; Used to fail with "Cannot select: 0x17300f0: v2i32 = any_extend" + +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = +"e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" +target triple = "hexagon-unknown-linux-gnu" + +define void @foo() nounwind { +entry: + %_p_vec_full48 = load <4 x i8>, <4 x i8>* undef, align 8 + %0 = zext <4 x i8> %_p_vec_full48 to <4 x i32> + store <4 x i32> %0, <4 x i32>* undef, align 8 + unreachable +} diff --git a/test/CodeGen/Hexagon/vect/vect-apint-truncate.ll b/test/CodeGen/Hexagon/vect/vect-apint-truncate.ll new file mode 100644 index 0000000..eb94ddf --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-apint-truncate.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=hexagon < %s +; Used to fail with "Invalid APInt Truncate request". +; Used to fail with "Cannot select: 0x596010: v2i32 = sign_extend_inreg". + +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" +target triple = "hexagon-unknown-linux-gnu" + +define void @foo() nounwind { +entry: + br label %polly.loop_header + +polly.loop_after: ; preds = %polly.loop_header + unreachable + +polly.loop_header: ; preds = %polly.loop_body, %entry + %0 = icmp sle i32 undef, 63 + br i1 %0, label %polly.loop_body, label %polly.loop_after + +polly.loop_body: ; preds = %polly.loop_header + %_p_vec_full = load <4 x i8>, <4 x i8>* undef, align 8 + %1 = sext <4 x i8> %_p_vec_full to <4 x i32> + %p_vec = mul <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3> + %mulp_vec = add <4 x i32> %p_vec, <i32 21, i32 21, i32 21, i32 21> + store <4 x i32> %mulp_vec, <4 x i32>* undef, align 8 + br label %polly.loop_header +} diff --git a/test/CodeGen/Hexagon/vect/vect-bad-bitcast.ll b/test/CodeGen/Hexagon/vect/vect-bad-bitcast.ll new file mode 100644 index 0000000..1672a78 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-bad-bitcast.ll @@ -0,0 +1,61 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s +; REQUIRES: asserts +; Check for successful compilation. + +target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32" +target triple = "hexagon" + +@input_buf = internal unnamed_addr constant [256 x i16] [i16 0, i16 0, i16 0, i16 1280, i16 2560, i16 4864, i16 7168, i16 9472, i16 11776, i16 12672, i16 13568, i16 14080, i16 15360, i16 15360, i16 15360, i16 15360, i16 15360, i16 15104, i16 14848, i16 14592, i16 14336, i16 14080, i16 14080, i16 13952, i16 13824, i16 13696, i16 13568, i16 13440, i16 13312, i16 13184, i16 13056, i16 12928, i16 12800, i16 12800, i16 12800, i16 12800, i16 12800, i16 12672, i16 12544, i16 12544, i16 12544, i16 12544, i16 12672, i16 12800, i16 12800, i16 12928, i16 13056, i16 13184, i16 13312, i16 13440, i16 13568, i16 13696, i16 13824, i16 14208, i16 14592, i16 14976, i16 15104, i16 15360, i16 15616, i16 15872, i16 16128, i16 16512, i16 16896, i16 17152, i16 17408, i16 17536, i16 17664, i16 17792, i16 17920, i16 18304, i16 18688, i16 19072, i16 19456, i16 19712, i16 19968, i16 20224, i16 20480, i16 20608, i16 20864, i16 20992, i16 21248, i16 21248, i16 21248, i16 21248, i16 21248, i16 21248, i16 21376, i16 21504, i16 21760, i16 21760, i16 21632, i16 21504, i16 21504, i16 21632, i16 21632, i16 21504, i16 21504, i16 21376, i16 21248, i16 21120, i16 20992, i16 20992, i16 20864, i16 20736, i16 20736, i16 20736, i16 20480, i16 20352, i16 20224, i16 20224, i16 20224, i16 20224, i16 20352, i16 20352, i16 20480, i16 20352, i16 20352, i16 20352, i16 20352, i16 20224, i16 20224, i16 20224, i16 20096, i16 20096, i16 19968, i16 19840, i16 19712, i16 19584, i16 19456, i16 19584, i16 19584, i16 19456, i16 19456, i16 19328, i16 19328, i16 19456, i16 19456, i16 19328, i16 19328, i16 19200, i16 19200, i16 19200, i16 19072, i16 19072, i16 18944, i16 18816, i16 18688, i16 18560, i16 18432, i16 18304, i16 18304, i16 18176, i16 18176, i16 18176, i16 18304, i16 18304, i16 18432, i16 18560, i16 18432, i16 18176, i16 17920, i16 17920, i16 17792, i16 17792, i16 17664, i16 17664, i16 17536, i16 17536, i16 17408, i16 17408, i16 17280, i16 17280, i16 17280, i16 17152, i16 17152, i16 17152, i16 17152, i16 17024, i16 17024, i16 16896, i16 16896, i16 16896, i16 16768, i16 16768, i16 16640, i16 16640, i16 16512, i16 16512, i16 16384, i16 16256, i16 16128, i16 16000, i16 15872, i16 15744, i16 15616, i16 15488, i16 15360, i16 15488, i16 15360, i16 15232, i16 15360, i16 15232, i16 15104, i16 14976, i16 14336, i16 14336, i16 14592, i16 14464, i16 13824, i16 13824, i16 13568, i16 13568, i16 13440, i16 13312, i16 13184, i16 13056, i16 13056, i16 13056, i16 12928, i16 12800, i16 12672, i16 12672, i16 12544, i16 12416, i16 12288, i16 12160, i16 11904, i16 11776, i16 11571, i16 11520, i16 11392, i16 11136, i16 10905, i16 10752, i16 10624, i16 10444, i16 10240, i16 9984, i16 9728, i16 9472, i16 9216, i16 8960, i16 8704, i16 8448, i16 8192, i16 7936, i16 7680, i16 7424, i16 7168, i16 6400, i16 5632, i16 4864, i16 3584, i16 1536, i16 0, i16 0], align 8 + +; Function Attrs: nounwind +define i32 @t_run_test() #0 { +entry: + %WaterLeveldB_out = alloca i16, align 2 + br label %polly.stmt.for.body + +for.body8: ; preds = %for.body8, %polly.loop_exit.loopexit + %i.120 = phi i32 [ 0, %polly.loop_exit.loopexit ], [ %inc11.24, %for.body8 ] + %call = call i32 bitcast (i32 (...)* @fxpBitAllocation to i32 (i32, i32, i32, i32, i16*, i32, i32, i32)*)(i32 0, i32 0, i32 256, i32 %conv9, i16* %WaterLeveldB_out, i32 0, i32 1920, i32 %i.120) #2 + %inc11.24 = add i32 %i.120, 25 + %exitcond.24 = icmp eq i32 %inc11.24, 500 + br i1 %exitcond.24, label %for.end12, label %for.body8 + +for.end12: ; preds = %for.body8 + ret i32 0 + +polly.loop_exit.loopexit: ; preds = %polly.stmt.for.body + %WaterLeveldB.1p_vsel.lcssa = phi <4 x i16> [ %WaterLeveldB.1p_vsel, %polly.stmt.for.body ] + %_low_half = shufflevector <4 x i16> %WaterLeveldB.1p_vsel.lcssa, <4 x i16> undef, <2 x i32> <i32 0, i32 1> + %_high_half = shufflevector <4 x i16> %WaterLeveldB.1p_vsel.lcssa, <4 x i16> undef, <2 x i32> <i32 2, i32 3> + %0 = icmp sgt <2 x i16> %_low_half, %_high_half + %1 = select <2 x i1> %0, <2 x i16> %_low_half, <2 x i16> %_high_half + %2 = extractelement <2 x i16> %1, i32 0 + %3 = extractelement <2 x i16> %1, i32 1 + %4 = icmp sgt i16 %2, %3 + %5 = select i1 %4, i16 %2, i16 %3 + %conv9 = sext i16 %5 to i32 + br label %for.body8 + +polly.stmt.for.body: ; preds = %entry, %polly.stmt.for.body + %WaterLeveldB.1p_vsel35 = phi <4 x i16> [ <i16 -32768, i16 -32768, i16 -32768, i16 -32768>, %entry ], [ %WaterLeveldB.1p_vsel, %polly.stmt.for.body ] + %scevgep.phi = phi i16* [ getelementptr inbounds ([256 x i16], [256 x i16]* @input_buf, i32 0, i32 0), %entry ], [ %scevgep.inc, %polly.stmt.for.body ] + %polly.indvar = phi i32 [ 0, %entry ], [ %polly.indvar_next, %polly.stmt.for.body ] + %vector_ptr = bitcast i16* %scevgep.phi to <4 x i16>* + %_p_vec_full = load <4 x i16>, <4 x i16>* %vector_ptr, align 8 + %cmp2p_vicmp = icmp sgt <4 x i16> %_p_vec_full, %WaterLeveldB.1p_vsel35 + %WaterLeveldB.1p_vsel = select <4 x i1> %cmp2p_vicmp, <4 x i16> %_p_vec_full, <4 x i16> %WaterLeveldB.1p_vsel35 + %polly.indvar_next = add nsw i32 %polly.indvar, 4 + %polly.loop_cond = icmp slt i32 %polly.indvar, 252 + %scevgep.inc = getelementptr i16, i16* %scevgep.phi, i32 4 + br i1 %polly.loop_cond, label %polly.stmt.for.body, label %polly.loop_exit.loopexit +} + +declare i32 @fxpBitAllocation(...) #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind } + +!llvm.ident = !{!0} + +!0 = !{!"QuIC LLVM Hexagon Clang version 3.1"} diff --git a/test/CodeGen/Hexagon/vect/vect-bitcast-1.ll b/test/CodeGen/Hexagon/vect/vect-bitcast-1.ll new file mode 100644 index 0000000..b834744 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-bitcast-1.ll @@ -0,0 +1,68 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts +; Used to fail with: Assertion `VT.getSizeInBits() == Operand.getValueType().getSizeInBits() && "Cannot BITCAST between types of different sizes!"' failed. + +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" +target triple = "hexagon-unknown-linux-gnu" + +define void @foo() nounwind { +entry: + br label %while.body + +while.body: ; preds = %if.then155, %if.then12, %entry + %cmp.i = icmp eq i8* undef, null + br i1 %cmp.i, label %lab_ci.exit, label %if.end.i + +if.end.i: ; preds = %while.body + unreachable + +lab_ci.exit: ; preds = %while.body + br i1 false, label %if.then, label %if.else + +if.then: ; preds = %lab_ci.exit + unreachable + +if.else: ; preds = %lab_ci.exit + br i1 undef, label %if.then12, label %if.else17 + +if.then12: ; preds = %if.else + br label %while.body + +if.else17: ; preds = %if.else + br i1 false, label %if.then22, label %if.else35 + +if.then22: ; preds = %if.else17 + unreachable + +if.else35: ; preds = %if.else17 + br i1 false, label %if.then40, label %if.else83 + +if.then40: ; preds = %if.else35 + unreachable + +if.else83: ; preds = %if.else35 + br i1 false, label %if.then88, label %if.else150 + +if.then88: ; preds = %if.else83 + unreachable + +if.else150: ; preds = %if.else83 + %cmp154 = icmp eq i32 undef, 0 + br i1 %cmp154, label %if.then155, label %if.else208 + +if.then155: ; preds = %if.else150 + %call191 = call i32 @strtol() nounwind + %conv192 = trunc i32 %call191 to i16 + %_p_splat_one = insertelement <1 x i16> undef, i16 %conv192, i32 0 + %_p_splat = shufflevector <1 x i16> %_p_splat_one, <1 x i16> undef, <2 x i32> zeroinitializer + %0 = sext <2 x i16> %_p_splat to <2 x i32> + %mul198p_vec = shl <2 x i32> %0, <i32 2, i32 2> + %1 = extractelement <2 x i32> %mul198p_vec, i32 0 + store i32 %1, i32* null, align 4 + br label %while.body + +if.else208: ; preds = %if.else150 + unreachable +} + +declare i32 @strtol() nounwind diff --git a/test/CodeGen/Hexagon/vect/vect-bitcast.ll b/test/CodeGen/Hexagon/vect/vect-bitcast.ll new file mode 100644 index 0000000..2d6b0b8 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-bitcast.ll @@ -0,0 +1,56 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts +; Used to fail with "Cannot BITCAST between types of different sizes!" + +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +define void @foo() nounwind { +entry: + br label %while.body + +while.body: ; preds = %if.then155, %if.then12, %if.then, %entry + br i1 undef, label %if.then, label %if.else + +if.then: ; preds = %while.body + br label %while.body + +if.else: ; preds = %while.body + br i1 undef, label %if.then12, label %if.else17 + +if.then12: ; preds = %if.else + br label %while.body + +if.else17: ; preds = %if.else + br i1 false, label %if.then22, label %if.else35 + +if.then22: ; preds = %if.else17 + unreachable + +if.else35: ; preds = %if.else17 + br i1 false, label %if.then40, label %if.else83 + +if.then40: ; preds = %if.else35 + unreachable + +if.else83: ; preds = %if.else35 + br i1 false, label %if.then88, label %if.else150 + +if.then88: ; preds = %if.else83 + unreachable + +if.else150: ; preds = %if.else83 + %cmp154 = icmp eq i32 undef, 0 + br i1 %cmp154, label %if.then155, label %if.else208 + +if.then155: ; preds = %if.else150 + %_p_splat.1 = shufflevector <1 x i16> zeroinitializer, <1 x i16> undef, <2 x i32> zeroinitializer + %0 = sext <2 x i16> %_p_splat.1 to <2 x i32> + %mul198p_vec.1 = mul <2 x i32> %0, <i32 4, i32 4> + %1 = extractelement <2 x i32> %mul198p_vec.1, i32 0 + store i32 %1, i32* undef, align 4 + br label %while.body + +if.else208: ; preds = %if.else150 + unreachable +} diff --git a/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll b/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll new file mode 100644 index 0000000..f5ee5d0 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-cst-v4i32.ll @@ -0,0 +1,29 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; This one should generate a combine with two immediates. +; CHECK: combine(#7, #7) +@B = common global [400 x i32] zeroinitializer, align 8 +@A = common global [400 x i32] zeroinitializer, align 8 +@C = common global [400 x i32] zeroinitializer, align 8 + +define void @run() nounwind { +entry: + br label %polly.loop_body + +polly.loop_after: ; preds = %polly.loop_body + ret void + +polly.loop_body: ; preds = %entry, %polly.loop_body + %polly.loopiv23 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ] + %polly.next_loopiv = add nsw i32 %polly.loopiv23, 4 + %p_arrayidx1 = getelementptr [400 x i32], [400 x i32]* @A, i32 0, i32 %polly.loopiv23 + %p_arrayidx = getelementptr [400 x i32], [400 x i32]* @B, i32 0, i32 %polly.loopiv23 + %vector_ptr = bitcast i32* %p_arrayidx to <4 x i32>* + %_p_vec_full = load <4 x i32>, <4 x i32>* %vector_ptr, align 8 + %mulp_vec = mul <4 x i32> %_p_vec_full, <i32 7, i32 7, i32 7, i32 7> + %vector_ptr12 = bitcast i32* %p_arrayidx1 to <4 x i32>* + %_p_vec_full13 = load <4 x i32>, <4 x i32>* %vector_ptr12, align 8 + %addp_vec = add <4 x i32> %_p_vec_full13, %mulp_vec + store <4 x i32> %addp_vec, <4 x i32>* %vector_ptr12, align 8 + %0 = icmp slt i32 %polly.next_loopiv, 400 + br i1 %0, label %polly.loop_body, label %polly.loop_after +} diff --git a/test/CodeGen/Hexagon/vect/vect-cst-v4i8.ll b/test/CodeGen/Hexagon/vect/vect-cst-v4i8.ll new file mode 100644 index 0000000..de3e14e --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-cst-v4i8.ll @@ -0,0 +1,30 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; Make sure we can build the constant vector <1, 2, 3, 4> +; CHECK-DAG: ##B +; CHECK-DAG: ##A +@B = common global [400 x i8] zeroinitializer, align 8 +@A = common global [400 x i8] zeroinitializer, align 8 +@C = common global [400 x i8] zeroinitializer, align 8 + +define void @run() nounwind { +entry: + br label %polly.loop_body + +polly.loop_after: ; preds = %polly.loop_body + ret void + +polly.loop_body: ; preds = %entry, %polly.loop_body + %polly.loopiv25 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ] + %polly.next_loopiv = add i32 %polly.loopiv25, 4 + %p_arrayidx1 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %polly.loopiv25 + %p_arrayidx = getelementptr [400 x i8], [400 x i8]* @B, i32 0, i32 %polly.loopiv25 + %vector_ptr = bitcast i8* %p_arrayidx to <4 x i8>* + %_p_vec_full = load <4 x i8>, <4 x i8>* %vector_ptr, align 8 + %mulp_vec = mul <4 x i8> %_p_vec_full, <i8 1, i8 2, i8 3, i8 4> + %vector_ptr14 = bitcast i8* %p_arrayidx1 to <4 x i8>* + %_p_vec_full15 = load <4 x i8>, <4 x i8>* %vector_ptr14, align 8 + %addp_vec = add <4 x i8> %_p_vec_full15, %mulp_vec + store <4 x i8> %addp_vec, <4 x i8>* %vector_ptr14, align 8 + %0 = icmp slt i32 %polly.next_loopiv, 400 + br i1 %0, label %polly.loop_body, label %polly.loop_after +} diff --git a/test/CodeGen/Hexagon/vect/vect-cst.ll b/test/CodeGen/Hexagon/vect/vect-cst.ll new file mode 100644 index 0000000..370fa5c --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-cst.ll @@ -0,0 +1,29 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; Make sure we can build the constant vector <7, 7, 7, 7> +; CHECK: vaddub +@B = common global [400 x i8] zeroinitializer, align 8 +@A = common global [400 x i8] zeroinitializer, align 8 +@C = common global [400 x i8] zeroinitializer, align 8 + +define void @run() nounwind { +entry: + br label %polly.loop_body + +polly.loop_after: ; preds = %polly.loop_body + ret void + +polly.loop_body: ; preds = %entry, %polly.loop_body + %polly.loopiv25 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ] + %polly.next_loopiv = add i32 %polly.loopiv25, 4 + %p_arrayidx1 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %polly.loopiv25 + %p_arrayidx = getelementptr [400 x i8], [400 x i8]* @B, i32 0, i32 %polly.loopiv25 + %vector_ptr = bitcast i8* %p_arrayidx to <4 x i8>* + %_p_vec_full = load <4 x i8>, <4 x i8>* %vector_ptr, align 8 + %mulp_vec = mul <4 x i8> %_p_vec_full, <i8 7, i8 7, i8 7, i8 7> + %vector_ptr14 = bitcast i8* %p_arrayidx1 to <4 x i8>* + %_p_vec_full15 = load <4 x i8>, <4 x i8>* %vector_ptr14, align 8 + %addp_vec = add <4 x i8> %_p_vec_full15, %mulp_vec + store <4 x i8> %addp_vec, <4 x i8>* %vector_ptr14, align 8 + %0 = icmp slt i32 %polly.next_loopiv, 400 + br i1 %0, label %polly.loop_body, label %polly.loop_after +} diff --git a/test/CodeGen/Hexagon/vect/vect-extract.ll b/test/CodeGen/Hexagon/vect/vect-extract.ll new file mode 100644 index 0000000..75dc685 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-extract.ll @@ -0,0 +1,96 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s + +; Check that we do not generate extract. +; CHECK-NOT: extractu +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +define void @foo(i32 %N, i32* nocapture %C, i16* nocapture %A, i16 signext %val) #0 { +entry: + %cmp14 = icmp eq i32 %N, 0 + br i1 %cmp14, label %for.end11, label %for.cond1.preheader.single_entry.preheader + +for.cond1.preheader.single_entry.preheader: ; preds = %entry + %0 = add i32 %N, -1 + %leftover_lb = and i32 %0, -2 + %p_conv4 = sext i16 %val to i32 + br label %for.cond1.preheader.single_entry + +for.cond1.preheader.single_entry: ; preds = %for.inc9, %for.cond1.preheader.single_entry.preheader + %indvar = phi i32 [ %indvar.next, %for.inc9 ], [ 0, %for.cond1.preheader.single_entry.preheader ] + %1 = mul i32 %indvar, %N + %.not = icmp slt i32 %N, 2 + %.not41 = icmp slt i32 %leftover_lb, 1 + %brmerge = or i1 %.not, %.not41 + %.mux = select i1 %.not, i32 0, i32 %leftover_lb + br i1 %brmerge, label %polly.loop_header26.preheader, label %polly.loop_body.lr.ph + +for.inc9.loopexit: ; preds = %polly.stmt.for.body331 + br label %for.inc9 + +for.inc9: ; preds = %for.inc9.loopexit, %polly.loop_header26.preheader + %indvar.next = add i32 %indvar, 1 + %exitcond40 = icmp eq i32 %indvar.next, %N + br i1 %exitcond40, label %for.end11.loopexit, label %for.cond1.preheader.single_entry + +for.end11.loopexit: ; preds = %for.inc9 + br label %for.end11 + +for.end11: ; preds = %for.end11.loopexit, %entry + ret void + +polly.loop_body.lr.ph: ; preds = %for.cond1.preheader.single_entry + %2 = call i64 @llvm.hexagon.A2.combinew(i32 %1, i32 %1) + %3 = bitcast i64 %2 to <2 x i32> + %4 = extractelement <2 x i32> %3, i32 0 + %5 = call i64 @llvm.hexagon.A2.combinew(i32 %p_conv4, i32 %p_conv4) + %6 = bitcast i64 %5 to <2 x i32> + %p_arrayidx8.gep = getelementptr i32, i32* %C, i32 %4 + %p_arrayidx.gep = getelementptr i16, i16* %A, i32 %4 + br label %polly.loop_body + +polly.loop_body: ; preds = %polly.loop_body.lr.ph, %polly.loop_body + %p_arrayidx8.phi = phi i32* [ %p_arrayidx8.gep, %polly.loop_body.lr.ph ], [ %p_arrayidx8.inc, %polly.loop_body ] + %p_arrayidx.phi = phi i16* [ %p_arrayidx.gep, %polly.loop_body.lr.ph ], [ %p_arrayidx.inc, %polly.loop_body ] + %polly.loopiv38 = phi i32 [ 0, %polly.loop_body.lr.ph ], [ %polly.next_loopiv, %polly.loop_body ] + %polly.next_loopiv = add nsw i32 %polly.loopiv38, 2 + %vector_ptr = bitcast i16* %p_arrayidx.phi to <2 x i16>* + %_p_vec_full = load <2 x i16>, <2 x i16>* %vector_ptr, align 2 + %7 = sext <2 x i16> %_p_vec_full to <2 x i32> + %mul5p_vec = mul <2 x i32> %7, %6 + %vector_ptr21 = bitcast i32* %p_arrayidx8.phi to <2 x i32>* + store <2 x i32> %mul5p_vec, <2 x i32>* %vector_ptr21, align 4 + %8 = icmp slt i32 %polly.next_loopiv, %leftover_lb + %p_arrayidx8.inc = getelementptr i32, i32* %p_arrayidx8.phi, i32 2 + %p_arrayidx.inc = getelementptr i16, i16* %p_arrayidx.phi, i32 2 + br i1 %8, label %polly.loop_body, label %polly.loop_header26.preheader.loopexit + +polly.loop_header26.preheader.loopexit: ; preds = %polly.loop_body + br label %polly.loop_header26.preheader + +polly.loop_header26.preheader: ; preds = %polly.loop_header26.preheader.loopexit, %for.cond1.preheader.single_entry + %polly.loopiv29.ph = phi i32 [ %.mux, %for.cond1.preheader.single_entry ], [ %leftover_lb, %polly.loop_header26.preheader.loopexit ] + %9 = icmp slt i32 %polly.loopiv29.ph, %N + br i1 %9, label %polly.stmt.for.body331.preheader, label %for.inc9 + +polly.stmt.for.body331.preheader: ; preds = %polly.loop_header26.preheader + br label %polly.stmt.for.body331 + +polly.stmt.for.body331: ; preds = %polly.stmt.for.body331.preheader, %polly.stmt.for.body331 + %polly.loopiv2939 = phi i32 [ %polly.next_loopiv30, %polly.stmt.for.body331 ], [ %polly.loopiv29.ph, %polly.stmt.for.body331.preheader ] + %polly.next_loopiv30 = add nsw i32 %polly.loopiv2939, 1 + %p_32 = add i32 %polly.loopiv2939, %1 + %p_arrayidx833 = getelementptr i32, i32* %C, i32 %p_32 + %p_arrayidx34 = getelementptr i16, i16* %A, i32 %p_32 + %_p_scalar_ = load i16, i16* %p_arrayidx34, align 2 + %p_conv = sext i16 %_p_scalar_ to i32 + %p_mul5 = mul nsw i32 %p_conv, %p_conv4 + store i32 %p_mul5, i32* %p_arrayidx833, align 4 + %exitcond = icmp eq i32 %polly.next_loopiv30, %N + br i1 %exitcond, label %for.inc9.loopexit, label %polly.stmt.for.body331 +} + +declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/Hexagon/vect/vect-fma.ll b/test/CodeGen/Hexagon/vect/vect-fma.ll new file mode 100644 index 0000000..c35e015 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-fma.ll @@ -0,0 +1,26 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s +; REQUIRES: asserts +; Used to fail with "SplitVectorResult #0: 0x16cbe60: v4f64 = fma" + +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" +target triple = "hexagon-unknown-linux-gnu" + +define void @run() nounwind { +entry: + br label %polly.loop_header + +polly.loop_after: ; preds = %polly.loop_header + ret void + +polly.loop_header: ; preds = %polly.loop_body, %entry + %0 = icmp sle i32 undef, 399 + br i1 %0, label %polly.loop_body, label %polly.loop_after + +polly.loop_body: ; preds = %polly.loop_header + %_p_vec_full = load <4 x double>, <4 x double>* undef, align 8 + %mulp_vec = fmul <4 x double> %_p_vec_full, <double 7.000000e+00, double 7.000000e+00, double 7.000000e+00, double 7.000000e+00> + %addp_vec = fadd <4 x double> undef, %mulp_vec + store <4 x double> %addp_vec, <4 x double>* undef, align 8 + br label %polly.loop_header +} diff --git a/test/CodeGen/Hexagon/vect/vect-illegal-type.ll b/test/CodeGen/Hexagon/vect/vect-illegal-type.ll new file mode 100644 index 0000000..3d3bf88 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-illegal-type.ll @@ -0,0 +1,50 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts +; Used to fail with "Unexpected illegal type!" +; Used to fail with "Cannot select: ch = store x,x,x,<ST4[undef](align=8), trunc to v4i8>" + +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" +target triple = "hexagon-unknown-linux-gnu" + +define void @foo() nounwind { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + br i1 undef, label %for.end, label %for.body + +for.end: ; preds = %for.body + br label %for.body71 + +for.body71: ; preds = %for.body71, %for.end + br i1 undef, label %for.end96, label %for.body71 + +for.end96: ; preds = %for.body71 + switch i32 undef, label %sw.epilog [ + i32 1, label %for.cond375.preheader + i32 8, label %for.cond591 + ] + +for.cond375.preheader: ; preds = %for.end96 + br label %polly.loop_header228 + +for.cond591: ; preds = %for.end96 + br label %for.body664 + +for.body664: ; preds = %for.body664, %for.cond591 + br i1 undef, label %for.end670, label %for.body664 + +for.end670: ; preds = %for.body664 + br label %sw.epilog + +sw.epilog: ; preds = %for.end670, %for.end96 + ret void + +polly.loop_header228: ; preds = %polly.loop_header228, %for.cond375.preheader + %_p_splat_one = load <1 x i16>, <1 x i16>* undef, align 8 + %_p_splat = shufflevector <1 x i16> %_p_splat_one, <1 x i16> %_p_splat_one, <4 x i32> zeroinitializer + %0 = trunc <4 x i16> %_p_splat to <4 x i8> + store <4 x i8> %0, <4 x i8>* undef, align 8 + br label %polly.loop_header228 +} diff --git a/test/CodeGen/Hexagon/vect/vect-insert-extract-elt.ll b/test/CodeGen/Hexagon/vect/vect-insert-extract-elt.ll new file mode 100644 index 0000000..baf0cd7 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-insert-extract-elt.ll @@ -0,0 +1,71 @@ +; RUN: llc -march=hexagon < %s +; Used to fail with an infinite recursion in the insn selection. +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon-unknown-linux-gnu" + +%struct.elt = type { [2 x [4 x %struct.block]] } +%struct.block = type { [2 x i16] } + +define void @foo(%struct.elt* noalias nocapture %p0, %struct.elt* noalias nocapture %p1) nounwind { +entry: + %arrayidx1 = getelementptr inbounds %struct.elt, %struct.elt* %p1, i32 0, i32 0, i32 0, i32 3 + %arrayidx4 = getelementptr inbounds %struct.elt, %struct.elt* %p1, i32 0, i32 0, i32 0, i32 2 + %arrayidx7 = getelementptr inbounds %struct.elt, %struct.elt* %p0, i32 0, i32 0, i32 0, i32 3 + %0 = bitcast %struct.block* %arrayidx7 to i32* + %1 = bitcast %struct.block* %arrayidx4 to i32* + %2 = load i32, i32* %0, align 4 + store i32 %2, i32* %1, align 4 + %3 = bitcast %struct.block* %arrayidx1 to i32* + store i32 %2, i32* %3, align 4 + %arrayidx10 = getelementptr inbounds %struct.elt, %struct.elt* %p1, i32 0, i32 0, i32 0, i32 1 + %arrayidx16 = getelementptr inbounds %struct.elt, %struct.elt* %p0, i32 0, i32 0, i32 0, i32 2 + %4 = bitcast %struct.block* %arrayidx16 to i32* + %5 = bitcast %struct.elt* %p1 to i32* + %6 = load i32, i32* %4, align 4 + store i32 %6, i32* %5, align 4 + %7 = bitcast %struct.block* %arrayidx10 to i32* + store i32 %6, i32* %7, align 4 + %p_arrayidx26 = getelementptr %struct.elt, %struct.elt* %p0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1 + %p_arrayidx2632 = getelementptr %struct.elt, %struct.elt* %p0, i32 0, i32 0, i32 0, i32 1, i32 0, i32 1 + %p_arrayidx2633 = getelementptr %struct.elt, %struct.elt* %p0, i32 0, i32 0, i32 0, i32 2, i32 0, i32 1 + %p_arrayidx2634 = getelementptr %struct.elt, %struct.elt* %p0, i32 0, i32 0, i32 0, i32 3, i32 0, i32 1 + %p_arrayidx20 = getelementptr %struct.elt, %struct.elt* %p1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1 + %p_arrayidx2035 = getelementptr %struct.elt, %struct.elt* %p1, i32 0, i32 0, i32 0, i32 1, i32 0, i32 1 + %p_arrayidx2036 = getelementptr %struct.elt, %struct.elt* %p1, i32 0, i32 0, i32 0, i32 2, i32 0, i32 1 + %p_arrayidx2037 = getelementptr %struct.elt, %struct.elt* %p1, i32 0, i32 0, i32 0, i32 3, i32 0, i32 1 + %8 = lshr i32 %6, 16 + %9 = trunc i32 %8 to i16 + %_p_vec_ = insertelement <4 x i16> undef, i16 %9, i32 0 + %_p_vec_39 = insertelement <4 x i16> %_p_vec_, i16 %9, i32 1 + %10 = lshr i32 %2, 16 + %11 = trunc i32 %10 to i16 + %_p_vec_41 = insertelement <4 x i16> %_p_vec_39, i16 %11, i32 2 + %_p_vec_43 = insertelement <4 x i16> %_p_vec_41, i16 %11, i32 3 + %shlp_vec = shl <4 x i16> %_p_vec_43, <i16 1, i16 1, i16 1, i16 1> + %12 = extractelement <4 x i16> %shlp_vec, i32 0 + store i16 %12, i16* %p_arrayidx20, align 2 + %13 = extractelement <4 x i16> %shlp_vec, i32 1 + store i16 %13, i16* %p_arrayidx2035, align 2 + %14 = extractelement <4 x i16> %shlp_vec, i32 2 + store i16 %14, i16* %p_arrayidx2036, align 2 + %15 = extractelement <4 x i16> %shlp_vec, i32 3 + store i16 %15, i16* %p_arrayidx2037, align 2 + %_p_scalar_44 = load i16, i16* %p_arrayidx26, align 2 + %_p_vec_45 = insertelement <4 x i16> undef, i16 %_p_scalar_44, i32 0 + %_p_scalar_46 = load i16, i16* %p_arrayidx2632, align 2 + %_p_vec_47 = insertelement <4 x i16> %_p_vec_45, i16 %_p_scalar_46, i32 1 + %_p_scalar_48 = load i16, i16* %p_arrayidx2633, align 2 + %_p_vec_49 = insertelement <4 x i16> %_p_vec_47, i16 %_p_scalar_48, i32 2 + %_p_scalar_50 = load i16, i16* %p_arrayidx2634, align 2 + %_p_vec_51 = insertelement <4 x i16> %_p_vec_49, i16 %_p_scalar_50, i32 3 + %shl28p_vec = shl <4 x i16> %_p_vec_51, <i16 1, i16 1, i16 1, i16 1> + %16 = extractelement <4 x i16> %shl28p_vec, i32 0 + store i16 %16, i16* %p_arrayidx26, align 2 + %17 = extractelement <4 x i16> %shl28p_vec, i32 1 + store i16 %17, i16* %p_arrayidx2632, align 2 + %18 = extractelement <4 x i16> %shl28p_vec, i32 2 + store i16 %18, i16* %p_arrayidx2633, align 2 + %19 = extractelement <4 x i16> %shl28p_vec, i32 3 + store i16 %19, i16* %p_arrayidx2634, align 2 + ret void +} diff --git a/test/CodeGen/Hexagon/vect/vect-load-1.ll b/test/CodeGen/Hexagon/vect/vect-load-1.ll new file mode 100644 index 0000000..fbaf61d --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-load-1.ll @@ -0,0 +1,26 @@ +; RUN: llc -march=hexagon < %s +; Used to fail with "Cannot select: v2i32,ch = load 0x16c5890, 0x16f76e0, 0x16f76e0<LD2[undef](align=8), sext from v2i8>", 0x16c5890, 0x16f76e0, 0x16f76e0<LD2[undef](align=8), sext from v2i8>" + +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" +target triple = "hexagon-unknown-linux-gnu" + +define void @foo() nounwind { +entry: + br label %polly.loop_header + +polly.loop_after: ; preds = %polly.loop_header + unreachable + +polly.loop_header: ; preds = %polly.loop_body, %entry + %0 = icmp sle i32 undef, 63 + br i1 %0, label %polly.loop_body, label %polly.loop_after + +polly.loop_body: ; preds = %polly.loop_header + %_p_vec_full = load <2 x i8>, <2 x i8>* undef, align 8 + %1 = sext <2 x i8> %_p_vec_full to <2 x i32> + %p_vec = mul <2 x i32> %1, <i32 3, i32 3> + %mulp_vec = add <2 x i32> %p_vec, <i32 21, i32 21> + store <2 x i32> %mulp_vec, <2 x i32>* undef, align 8 + br label %polly.loop_header +} diff --git a/test/CodeGen/Hexagon/vect/vect-load.ll b/test/CodeGen/Hexagon/vect/vect-load.ll new file mode 100644 index 0000000..6bdcc6d --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-load.ll @@ -0,0 +1,76 @@ +; RUN: llc -march=hexagon < %s +; Used to fail with "Cannot select: 0x16cf370: v2i16,ch = load" + +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" +target triple = "hexagon-unknown-linux-gnu" + +%struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958 = type { i8, i8, i8, i8, i8, i8, i16, i32, [8 x %struct.hcdc_ext_vec.9.64.141.273.306.317.328.680.691.702.713.724.735.757.790.801.845.856.867.878.889.900.944.955.957] } +%struct.hcdc_ext_vec.9.64.141.273.306.317.328.680.691.702.713.724.735.757.790.801.845.856.867.878.889.900.944.955.957 = type { i8, i8, i16 } + +define void @foo(%struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958* %hc_ext_info) nounwind { +entry: + br i1 undef, label %if.end, label %if.then + +if.then: ; preds = %entry + unreachable + +if.end: ; preds = %entry + br i1 undef, label %if.end5, label %if.then3 + +if.then3: ; preds = %if.end + br label %if.end5 + +if.end5: ; preds = %if.then3, %if.end + %add.ptr = getelementptr inbounds %struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958, %struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958* %hc_ext_info, i32 0, i32 8, i32 0 + %add.ptr22 = getelementptr inbounds %struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958, %struct.ext_hdrs.10.65.142.274.307.318.329.681.692.703.714.725.736.758.791.802.846.857.868.879.890.901.945.956.958* null, i32 0, i32 8, i32 undef + br label %while.cond + +while.cond: ; preds = %if.end419, %if.end5 + %gre_chksum.0 = phi <2 x i8> [ undef, %if.end5 ], [ %gre_chksum.2, %if.end419 ] + %cmp23 = icmp ult %struct.hcdc_ext_vec.9.64.141.273.306.317.328.680.691.702.713.724.735.757.790.801.845.856.867.878.889.900.944.955.957* null, %add.ptr + %cmp25 = icmp ult %struct.hcdc_ext_vec.9.64.141.273.306.317.328.680.691.702.713.724.735.757.790.801.845.856.867.878.889.900.944.955.957* null, %add.ptr22 + %sel1 = and i1 %cmp23, %cmp25 + br i1 %sel1, label %while.body, label %while.end422 + +while.body: ; preds = %while.cond + switch i8 undef, label %if.end419 [ + i8 5, label %if.then70 + i8 3, label %if.then70 + i8 2, label %if.then70 + i8 1, label %if.then70 + i8 0, label %if.then70 + i8 4, label %if.then93 + i8 6, label %if.then195 + ] + +if.then70: ; preds = %while.body, %while.body, %while.body, %while.body, %while.body + unreachable + +if.then93: ; preds = %while.body + unreachable + +if.then195: ; preds = %while.body + br i1 undef, label %if.end274, label %if.then202 + +if.then202: ; preds = %if.then195 + br label %while.body222 + +while.body222: ; preds = %while.body222, %if.then202 + br i1 undef, label %if.end240, label %while.body222 + +if.end240: ; preds = %while.body222 + %_p_vec_full100 = load <2 x i8>, <2 x i8>* undef, align 8 + br label %if.end274 + +if.end274: ; preds = %if.end240, %if.then195 + %gre_chksum.1 = phi <2 x i8> [ %gre_chksum.0, %if.then195 ], [ %_p_vec_full100, %if.end240 ] + br label %if.end419 + +if.end419: ; preds = %if.end274, %while.body + %gre_chksum.2 = phi <2 x i8> [ %gre_chksum.0, %while.body ], [ %gre_chksum.1, %if.end274 ] + br label %while.cond + +while.end422: ; preds = %while.cond + ret void +} diff --git a/test/CodeGen/Hexagon/vect/vect-loadv4i16.ll b/test/CodeGen/Hexagon/vect/vect-loadv4i16.ll new file mode 100644 index 0000000..16591ef --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-loadv4i16.ll @@ -0,0 +1,73 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s + +; Check that store is post-incremented. +; CHECK: memuh(r{{[0-9]+}} + {{ *}}#6{{ *}}) +; CHECK: combine(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}{{ *}}) +; CHECK: vaddh + +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +define void @matrix_add_const(i32 %N, i16* nocapture %A, i16 signext %val) #0 { +entry: + %cmp5 = icmp eq i32 %N, 0 + br i1 %cmp5, label %for.end, label %polly.cond + +for.end.loopexit: ; preds = %polly.stmt.for.body29 + br label %for.end + +for.end: ; preds = %for.end.loopexit, %polly.loop_header24.preheader, %entry + ret void + +polly.cond: ; preds = %entry + %0 = icmp sgt i32 %N, 3 + br i1 %0, label %polly.then, label %polly.loop_header24.preheader + +polly.then: ; preds = %polly.cond + %1 = add i32 %N, -1 + %leftover_lb = and i32 %1, -4 + %2 = icmp sgt i32 %leftover_lb, 0 + br i1 %2, label %polly.loop_body.lr.ph, label %polly.loop_header24.preheader + +polly.loop_body.lr.ph: ; preds = %polly.then + %3 = insertelement <4 x i16> undef, i16 %val, i32 0 + %4 = insertelement <4 x i16> %3, i16 %val, i32 1 + %5 = insertelement <4 x i16> %4, i16 %val, i32 2 + %6 = insertelement <4 x i16> %5, i16 %val, i32 3 + br label %polly.loop_body + +polly.loop_header24.preheader.loopexit: ; preds = %polly.loop_body + br label %polly.loop_header24.preheader + +polly.loop_header24.preheader: ; preds = %polly.loop_header24.preheader.loopexit, %polly.then, %polly.cond + %polly.loopiv27.ph = phi i32 [ 0, %polly.cond ], [ %leftover_lb, %polly.then ], [ %leftover_lb, %polly.loop_header24.preheader.loopexit ] + %7 = icmp slt i32 %polly.loopiv27.ph, %N + br i1 %7, label %polly.stmt.for.body29.preheader, label %for.end + +polly.stmt.for.body29.preheader: ; preds = %polly.loop_header24.preheader + br label %polly.stmt.for.body29 + +polly.loop_body: ; preds = %polly.loop_body.lr.ph, %polly.loop_body + %p_arrayidx.phi = phi i16* [ %A, %polly.loop_body.lr.ph ], [ %p_arrayidx.inc, %polly.loop_body ] + %polly.loopiv34 = phi i32 [ 0, %polly.loop_body.lr.ph ], [ %polly.next_loopiv, %polly.loop_body ] + %polly.next_loopiv = add nsw i32 %polly.loopiv34, 4 + %vector_ptr = bitcast i16* %p_arrayidx.phi to <4 x i16>* + %_p_vec_full = load <4 x i16>, <4 x i16>* %vector_ptr, align 2 + %addp_vec = add <4 x i16> %_p_vec_full, %6 + store <4 x i16> %addp_vec, <4 x i16>* %vector_ptr, align 2 + %8 = icmp slt i32 %polly.next_loopiv, %leftover_lb + %p_arrayidx.inc = getelementptr i16, i16* %p_arrayidx.phi, i32 4 + br i1 %8, label %polly.loop_body, label %polly.loop_header24.preheader.loopexit + +polly.stmt.for.body29: ; preds = %polly.stmt.for.body29.preheader, %polly.stmt.for.body29 + %polly.loopiv2733 = phi i32 [ %polly.next_loopiv28, %polly.stmt.for.body29 ], [ %polly.loopiv27.ph, %polly.stmt.for.body29.preheader ] + %polly.next_loopiv28 = add nsw i32 %polly.loopiv2733, 1 + %p_arrayidx30 = getelementptr i16, i16* %A, i32 %polly.loopiv2733 + %_p_scalar_ = load i16, i16* %p_arrayidx30, align 2 + %p_add = add i16 %_p_scalar_, %val + store i16 %p_add, i16* %p_arrayidx30, align 2 + %exitcond = icmp eq i32 %polly.next_loopiv28, %N + br i1 %exitcond, label %for.end.loopexit, label %polly.stmt.for.body29 +} + +attributes #0 = { nounwind "fp-contract-model"="standard" "no-frame-pointer-elim-non-leaf" "realign-stack" "relocation-model"="static" "ssp-buffers-size"="8" } diff --git a/test/CodeGen/Hexagon/vect/vect-mul-v2i16.ll b/test/CodeGen/Hexagon/vect/vect-mul-v2i16.ll new file mode 100644 index 0000000..f1a8011 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-mul-v2i16.ll @@ -0,0 +1,9 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: vmpyh +; CHECK: vtrunewh + +define <2 x i16> @t_i2x16(<2 x i16> %a, <2 x i16> %b) nounwind { +entry: + %0 = mul <2 x i16> %a, %b + ret <2 x i16> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-mul-v2i32.ll b/test/CodeGen/Hexagon/vect/vect-mul-v2i32.ll new file mode 100644 index 0000000..1d439dd --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-mul-v2i32.ll @@ -0,0 +1,9 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: mpyi +; CHECK: mpyi + +define <2 x i32> @t_i2x32(<2 x i32> %a, <2 x i32> %b) nounwind { +entry: + %0 = mul <2 x i32> %a, %b + ret <2 x i32> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-mul-v4i16.ll b/test/CodeGen/Hexagon/vect/vect-mul-v4i16.ll new file mode 100644 index 0000000..a50d7f8 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-mul-v4i16.ll @@ -0,0 +1,10 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: vmpyh +; CHECK: vmpyh +; CHECK: vtrunewh + +define <4 x i16> @t_i4x16(<4 x i16> %a, <4 x i16> %b) nounwind { +entry: + %0 = mul <4 x i16> %a, %b + ret <4 x i16> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-mul-v4i8.ll b/test/CodeGen/Hexagon/vect/vect-mul-v4i8.ll new file mode 100644 index 0000000..d60d014 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-mul-v4i8.ll @@ -0,0 +1,9 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; CHECK: vmpybsu +; CHECK: vtrunehb + +define <4 x i8> @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind { +entry: + %0 = mul <4 x i8> %a, %b + ret <4 x i8> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-mul-v8i8.ll b/test/CodeGen/Hexagon/vect/vect-mul-v8i8.ll new file mode 100644 index 0000000..a84cd00 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-mul-v8i8.ll @@ -0,0 +1,9 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; CHECK: vmpybsu +; CHECK: vmpybsu + +define <8 x i8> @t_i8x8(<8 x i8> %a, <8 x i8> %b) nounwind { +entry: + %0 = mul <8 x i8> %a, %b + ret <8 x i8> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-no-tfrs-1.ll b/test/CodeGen/Hexagon/vect/vect-no-tfrs-1.ll new file mode 100644 index 0000000..550b0f8 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-no-tfrs-1.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK-NOT: r1:0 = r1:0 + +define <4 x i16> @t_i4x16(<4 x i16> %a, <4 x i16> %b) nounwind { +entry: + %0 = mul <4 x i16> %a, %b + ret <4 x i16> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-no-tfrs.ll b/test/CodeGen/Hexagon/vect/vect-no-tfrs.ll new file mode 100644 index 0000000..9081f18 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-no-tfrs.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK-NOT: r1:0 = combine(r1, r0) + +define <4 x i8> @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind { +entry: + %0 = mul <4 x i8> %a, %b + ret <4 x i8> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-packhl.ll b/test/CodeGen/Hexagon/vect/vect-packhl.ll new file mode 100644 index 0000000..dfdb019 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-packhl.ll @@ -0,0 +1,10 @@ +; Extracted from test/CodeGen/Generic/vector-casts.ll: used to loop indefinitely. +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: packhl + +define void @a(<2 x double>* %p, <2 x i8>* %q) { + %t = load <2 x double>, <2 x double>* %p + %r = fptosi <2 x double> %t to <2 x i8> + store <2 x i8> %r, <2 x i8>* %q + ret void +} diff --git a/test/CodeGen/Hexagon/vect/vect-shift-imm.ll b/test/CodeGen/Hexagon/vect/vect-shift-imm.ll new file mode 100644 index 0000000..4861181 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-shift-imm.ll @@ -0,0 +1,41 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLW +; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRW +; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRW +; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLH +; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRH +; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRH +; +; Make sure that the instructions with immediate operands are generated. +; CHECK-ASLW: vaslw({{.*}}, #9) +; CHECK-ASRW: vasrw({{.*}}, #8) +; CHECK-LSRW: vlsrw({{.*}}, #7) +; CHECK-ASLH: vaslh({{.*}}, #6) +; CHECK-ASRH: vasrh({{.*}}, #5) +; CHECK-LSRH: vlsrh({{.*}}, #4) + +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +define i64 @foo(i64 %x) nounwind readnone { +entry: + %0 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %x, i32 9) + %1 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %x, i32 8) + %2 = tail call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %x, i32 7) + %3 = tail call i64 @llvm.hexagon.S2.asl.i.vh(i64 %x, i32 6) + %4 = tail call i64 @llvm.hexagon.S2.asr.i.vh(i64 %x, i32 5) + %5 = tail call i64 @llvm.hexagon.S2.lsr.i.vh(i64 %x, i32 4) + %add = add i64 %1, %0 + %add1 = add i64 %add, %2 + %add2 = add i64 %add1, %3 + %add3 = add i64 %add2, %4 + %add4 = add i64 %add3, %5 + ret i64 %add4 +} + +declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) nounwind readnone +declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) nounwind readnone +declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32) nounwind readnone +declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) nounwind readnone +declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32) nounwind readnone +declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32) nounwind readnone + diff --git a/test/CodeGen/Hexagon/vect/vect-shuffle.ll b/test/CodeGen/Hexagon/vect/vect-shuffle.ll new file mode 100644 index 0000000..9d80df2 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-shuffle.ll @@ -0,0 +1,47 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s + +; Check that store is post-incremented. +; CHECK-NOT: extractu +; CHECK-NOT: insert +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +define i32 @foo(i16* noalias nocapture %src, i16* noalias nocapture %dstImg, i32 %width, i32 %idx, i32 %flush) #0 { +entry: + %0 = tail call i64 @llvm.hexagon.A2.combinew(i32 %flush, i32 %flush) + %1 = bitcast i64 %0 to <2 x i32> + br label %polly.loop_body + +polly.loop_after: ; preds = %polly.loop_body + ret i32 0 + +polly.loop_body: ; preds = %entry, %polly.loop_body + %p_arrayidx35.phi = phi i16* [ %dstImg, %entry ], [ %p_arrayidx35.inc, %polly.loop_body ] + %p_arrayidx.phi = phi i16* [ %src, %entry ], [ %p_arrayidx.inc, %polly.loop_body ] + %polly.loopiv56 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ] + %polly.next_loopiv = add nsw i32 %polly.loopiv56, 4 + %vector_ptr = bitcast i16* %p_arrayidx.phi to <4 x i16>* + %_p_vec_full = load <4 x i16>, <4 x i16>* %vector_ptr, align 2 + %_high_half = shufflevector <4 x i16> %_p_vec_full, <4 x i16> undef, <2 x i32> <i32 2, i32 3> + %_low_half = shufflevector <4 x i16> %_p_vec_full, <4 x i16> undef, <2 x i32> <i32 0, i32 1> + %2 = zext <2 x i16> %_low_half to <2 x i32> + %3 = zext <2 x i16> %_high_half to <2 x i32> + %add33p_vec = add <2 x i32> %2, %1 + %add33p_vec48 = add <2 x i32> %3, %1 + %4 = trunc <2 x i32> %add33p_vec to <2 x i16> + %5 = trunc <2 x i32> %add33p_vec48 to <2 x i16> + %_combined_vec = shufflevector <2 x i16> %4, <2 x i16> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + %vector_ptr49 = bitcast i16* %p_arrayidx35.phi to <4 x i16>* + store <4 x i16> %_combined_vec, <4 x i16>* %vector_ptr49, align 2 + %6 = icmp slt i32 %polly.next_loopiv, 1024 + %p_arrayidx35.inc = getelementptr i16, i16* %p_arrayidx35.phi, i32 4 + %p_arrayidx.inc = getelementptr i16, i16* %p_arrayidx.phi, i32 4 + br i1 %6, label %polly.loop_body, label %polly.loop_after +} + +declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } + + diff --git a/test/CodeGen/Hexagon/vect/vect-splat.ll b/test/CodeGen/Hexagon/vect/vect-splat.ll new file mode 100644 index 0000000..3613dbf --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-splat.ll @@ -0,0 +1,16 @@ +; Extracted from test/CodeGen/Generic/vector.ll: used to loop indefinitely. +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; CHECK: combine + +%i4 = type <4 x i32> + +define void @splat_i4(%i4* %P, %i4* %Q, i32 %X) { + %tmp = insertelement %i4 undef, i32 %X, i32 0 ; <%i4> [#uses=1] + %tmp2 = insertelement %i4 %tmp, i32 %X, i32 1 ; <%i4> [#uses=1] + %tmp4 = insertelement %i4 %tmp2, i32 %X, i32 2 ; <%i4> [#uses=1] + %tmp6 = insertelement %i4 %tmp4, i32 %X, i32 3 ; <%i4> [#uses=1] + %q = load %i4, %i4* %Q ; <%i4> [#uses=1] + %R = add %i4 %q, %tmp6 ; <%i4> [#uses=1] + store %i4 %R, %i4* %P + ret void +} diff --git a/test/CodeGen/Hexagon/vect/vect-store-v2i16.ll b/test/CodeGen/Hexagon/vect/vect-store-v2i16.ll new file mode 100644 index 0000000..1de3058 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-store-v2i16.ll @@ -0,0 +1,51 @@ +; RUN: llc -march=hexagon < %s +; Used to fail with: "Cannot select: 0x3bab680: ch = store <ST4[%lsr.iv522525], trunc to v2i16> +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" +target triple = "hexagon-unknown-linux-gnu" + +define void @foobar() nounwind { +entry: + br label %for.cond7.preheader.single_entry.i + +for.cond7.preheader.single_entry.i: ; preds = %for.cond7.preheader.single_entry.i, %entry + %exitcond72.i = icmp eq i32 undef, 64 + br i1 %exitcond72.i, label %foo_32.exit, label %for.cond7.preheader.single_entry.i + +foo_32.exit: ; preds = %for.cond7.preheader.single_entry.i + br label %for.body.i428 + +for.body.i428: ; preds = %for.body.i428, %foo_32.exit + br i1 undef, label %foo_12.exit, label %for.body.i428 + +foo_12.exit: ; preds = %for.body.i428 + br label %for.body.i.i + +for.body.i.i: ; preds = %for.body.i.i, %foo_12.exit + br i1 undef, label %foo_14.exit, label %for.body.i.i + +foo_14.exit: ; preds = %for.body.i.i + br label %for.body + +for.body: ; preds = %for.body, %foo_14.exit + br i1 undef, label %for.end, label %for.body + +for.end: ; preds = %for.body + %storemerge294 = select i1 undef, i32 32767, i32 undef + %_p_splat_one386 = insertelement <1 x i32> undef, i32 %storemerge294, i32 0 + %_p_splat387 = shufflevector <1 x i32> %_p_splat_one386, <1 x i32> undef, <2 x i32> zeroinitializer + br label %polly.loop_body377 + +polly.loop_after378: ; preds = %polly.loop_body377 + unreachable + +polly.loop_body377: ; preds = %polly.loop_body377, %for.end + %_p_vec_full384 = load <2 x i16>, <2 x i16>* undef, align 4 + %0 = sext <2 x i16> %_p_vec_full384 to <2 x i32> + %mulp_vec = mul <2 x i32> %0, %_p_splat387 + %shr100293p_vec = lshr <2 x i32> %mulp_vec, <i32 15, i32 15> + %1 = trunc <2 x i32> %shr100293p_vec to <2 x i16> + store <2 x i16> %1, <2 x i16>* undef, align 4 + br i1 undef, label %polly.loop_body377, label %polly.loop_after378 +} + diff --git a/test/CodeGen/Hexagon/vect/vect-truncate.ll b/test/CodeGen/Hexagon/vect/vect-truncate.ll new file mode 100644 index 0000000..fd75bbd --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-truncate.ll @@ -0,0 +1,42 @@ +; RUN: llc -march=hexagon < %s +; Used to fail with "Cannot select: 0x16cb7f0: v2i16 = truncate" + +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" +target triple = "hexagon-unknown-linux-gnu" + +define void @Autocorr() nounwind { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + br i1 undef, label %polly.loop_header43, label %for.body + +do.cond: ; preds = %polly.loop_header + unreachable + +do.end: ; preds = %polly.loop_after45 + ret void + +polly.loop_header: ; preds = %polly.loop_after45, %polly.loop_body + %0 = icmp sle i32 undef, 239 + br i1 %0, label %polly.loop_body, label %do.cond + +polly.loop_body: ; preds = %polly.loop_header + %p_25 = call i32 @llvm.hexagon.SI.to.SXTHI.asrh(i32 undef) + %1 = insertelement <4 x i32> undef, i32 %p_25, i32 3 + %2 = trunc <4 x i32> %1 to <4 x i16> + store <4 x i16> %2, <4 x i16>* undef, align 8 + br label %polly.loop_header + +polly.loop_after45: ; preds = %polly.loop_header43 + br i1 undef, label %polly.loop_header, label %do.end + +polly.loop_header43: ; preds = %polly.loop_body44, %for.body + br i1 undef, label %polly.loop_body44, label %polly.loop_after45 + +polly.loop_body44: ; preds = %polly.loop_header43 + br label %polly.loop_header43 +} + +declare i32 @llvm.hexagon.SI.to.SXTHI.asrh(i32) nounwind readnone diff --git a/test/CodeGen/Hexagon/vect/vect-vaddb-1.ll b/test/CodeGen/Hexagon/vect/vect-vaddb-1.ll new file mode 100644 index 0000000..e646f8e --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-vaddb-1.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: vaddub + +define <4 x i8> @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind { +entry: + %0 = add <4 x i8> %a, %b + ret <4 x i8> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-vaddb.ll b/test/CodeGen/Hexagon/vect/vect-vaddb.ll new file mode 100644 index 0000000..4595469 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-vaddb.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: vaddub + +define <8 x i8> @t_i8x8(<8 x i8> %a, <8 x i8> %b) nounwind { +entry: + %0 = add <8 x i8> %a, %b + ret <8 x i8> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-vaddh-1.ll b/test/CodeGen/Hexagon/vect/vect-vaddh-1.ll new file mode 100644 index 0000000..1b43d4f --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-vaddh-1.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: vaddh + +define <4 x i16> @t_i4x16(<4 x i16> %a, <4 x i16> %b) nounwind { +entry: + %0 = add <4 x i16> %a, %b + ret <4 x i16> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-vaddh.ll b/test/CodeGen/Hexagon/vect/vect-vaddh.ll new file mode 100644 index 0000000..32bf3ca --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-vaddh.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: vaddh + +define <2 x i16> @t_i2x16(<2 x i16> %a, <2 x i16> %b) nounwind { +entry: + %0 = add <2 x i16> %a, %b + ret <2 x i16> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-vaddw.ll b/test/CodeGen/Hexagon/vect/vect-vaddw.ll new file mode 100644 index 0000000..a840134 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-vaddw.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: vaddw + +define <2 x i32> @t_i2x32(<2 x i32> %a, <2 x i32> %b) nounwind { +entry: + %0 = add <2 x i32> %a, %b + ret <2 x i32> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-vaslw.ll b/test/CodeGen/Hexagon/vect/vect-vaslw.ll new file mode 100644 index 0000000..c662b0b --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-vaslw.ll @@ -0,0 +1,33 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: vaslw + +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon-unknown-linux-gnu" + +define void @foo(i16* nocapture %v) nounwind { +entry: + %p_arrayidx = getelementptr i16, i16* %v, i32 4 + %vector_ptr = bitcast i16* %p_arrayidx to <4 x i16>* + %_p_vec_full = load <4 x i16>, <4 x i16>* %vector_ptr, align 2 + %_high_half = shufflevector <4 x i16> %_p_vec_full, <4 x i16> undef, <2 x i32> <i32 2, i32 3> + %_low_half = shufflevector <4 x i16> %_p_vec_full, <4 x i16> undef, <2 x i32> <i32 0, i32 1> + %0 = sext <2 x i16> %_low_half to <2 x i32> + %1 = sext <2 x i16> %_high_half to <2 x i32> + %shr6p_vec = shl <2 x i32> %0, <i32 2, i32 2> + %shr6p_vec19 = shl <2 x i32> %1, <i32 2, i32 2> + %addp_vec = add <2 x i32> %shr6p_vec, <i32 34, i32 34> + %addp_vec20 = add <2 x i32> %shr6p_vec19, <i32 34, i32 34> + %vector_ptr21 = bitcast i16* %v to <4 x i16>* + %_p_vec_full22 = load <4 x i16>, <4 x i16>* %vector_ptr21, align 2 + %_high_half23 = shufflevector <4 x i16> %_p_vec_full22, <4 x i16> undef, <2 x i32> <i32 2, i32 3> + %_low_half24 = shufflevector <4 x i16> %_p_vec_full22, <4 x i16> undef, <2 x i32> <i32 0, i32 1> + %2 = zext <2 x i16> %_low_half24 to <2 x i32> + %3 = zext <2 x i16> %_high_half23 to <2 x i32> + %add3p_vec = add <2 x i32> %addp_vec, %2 + %add3p_vec25 = add <2 x i32> %addp_vec20, %3 + %4 = trunc <2 x i32> %add3p_vec to <2 x i16> + %5 = trunc <2 x i32> %add3p_vec25 to <2 x i16> + %_combined_vec = shufflevector <2 x i16> %4, <2 x i16> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + store <4 x i16> %_combined_vec, <4 x i16>* %vector_ptr21, align 2 + ret void +} diff --git a/test/CodeGen/Hexagon/vect/vect-vshifts.ll b/test/CodeGen/Hexagon/vect/vect-vshifts.ll new file mode 100644 index 0000000..49ff812 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-vshifts.ll @@ -0,0 +1,279 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s + +; Check that store is post-incremented. +; CHECK: r{{[0-9]+:[0-9]+}} = vasrw(r{{[0-9]+:[0-9]+}}, r{{[0-9]+}}) +; CHECK: r{{[0-9]+:[0-9]+}} = vaslw(r{{[0-9]+:[0-9]+}}, r{{[0-9]+}}) +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +define void @foo(i32* nocapture %buf, i32* nocapture %dest, i32 %offset, i32 %oddBlock, i32 %gb) #0 { +entry: + %0 = load i32, i32* %buf, align 4, !tbaa !0 + %shr = ashr i32 %0, %gb + store i32 %shr, i32* %buf, align 4, !tbaa !0 + %not.tobool = icmp eq i32 %oddBlock, 0 + %1 = sub i32 %offset, %oddBlock + %2 = zext i1 %not.tobool to i32 + %3 = and i32 %1, 7 + %4 = add i32 %2, %3 + %5 = add i32 %4, 8 + %p_sub8 = sub nsw i32 31, %gb + %6 = insertelement <2 x i32> undef, i32 %p_sub8, i32 0 + %7 = insertelement <2 x i32> %6, i32 %p_sub8, i32 1 + %8 = bitcast <2 x i32> %7 to i64 + %9 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %8, i32 1) + %10 = bitcast i64 %9 to <2 x i32> + %11 = tail call i64 @llvm.hexagon.A2.combinew(i32 -1, i32 -1) + %12 = bitcast i64 %11 to <2 x i32> + %sub12p_vec = add <2 x i32> %10, %12 + %p_22 = add i32 %4, 64 + %p_d.018 = getelementptr i32, i32* %dest, i32 %4 + %p_d.01823 = getelementptr i32, i32* %dest, i32 %p_22 + %p_25 = add i32 %4, 72 + %p_arrayidx14 = getelementptr i32, i32* %dest, i32 %5 + %p_arrayidx1426 = getelementptr i32, i32* %dest, i32 %p_25 + %_p_scalar_ = load i32, i32* %p_d.018, align 4 + %_p_vec_ = insertelement <2 x i32> undef, i32 %_p_scalar_, i32 0 + %_p_scalar_27 = load i32, i32* %p_d.01823, align 4 + %_p_vec_28 = insertelement <2 x i32> %_p_vec_, i32 %_p_scalar_27, i32 1 + %13 = bitcast <2 x i32> %_p_vec_28 to i64 + %14 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %13, i32 31) + %15 = bitcast i64 %14 to <2 x i32> + %shr9p_vec = ashr <2 x i32> %_p_vec_28, %7 + %xorp_vec = xor <2 x i32> %15, %sub12p_vec + %16 = bitcast <2 x i32> %shr9p_vec to i64 + %17 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %14, i64 %16) + %18 = bitcast <2 x i32> %xorp_vec to i64 + %19 = tail call i64 @llvm.hexagon.C2.vmux(i32 %17, i64 %13, i64 %18) + %20 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %19, i32 %gb) + %21 = bitcast i64 %20 to <2 x i32> + %22 = extractelement <2 x i32> %21, i32 0 + store i32 %22, i32* %p_arrayidx14, align 4 + %23 = extractelement <2 x i32> %21, i32 1 + store i32 %23, i32* %p_arrayidx1426, align 4 + store i32 %22, i32* %p_d.018, align 4 + store i32 %23, i32* %p_d.01823, align 4 + %p_21.1 = add i32 %4, 128 + %p_22.1 = add i32 %4, 192 + %p_d.018.1 = getelementptr i32, i32* %dest, i32 %p_21.1 + %p_d.01823.1 = getelementptr i32, i32* %dest, i32 %p_22.1 + %p_24.1 = add i32 %4, 136 + %p_25.1 = add i32 %4, 200 + %p_arrayidx14.1 = getelementptr i32, i32* %dest, i32 %p_24.1 + %p_arrayidx1426.1 = getelementptr i32, i32* %dest, i32 %p_25.1 + %_p_scalar_.1 = load i32, i32* %p_d.018.1, align 4 + %_p_vec_.1 = insertelement <2 x i32> undef, i32 %_p_scalar_.1, i32 0 + %_p_scalar_27.1 = load i32, i32* %p_d.01823.1, align 4 + %_p_vec_28.1 = insertelement <2 x i32> %_p_vec_.1, i32 %_p_scalar_27.1, i32 1 + %24 = bitcast <2 x i32> %_p_vec_28.1 to i64 + %25 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %24, i32 31) + %26 = bitcast i64 %25 to <2 x i32> + %shr9p_vec.1 = ashr <2 x i32> %_p_vec_28.1, %7 + %xorp_vec.1 = xor <2 x i32> %26, %sub12p_vec + %27 = bitcast <2 x i32> %shr9p_vec.1 to i64 + %28 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %25, i64 %27) + %29 = bitcast <2 x i32> %xorp_vec.1 to i64 + %30 = tail call i64 @llvm.hexagon.C2.vmux(i32 %28, i64 %24, i64 %29) + %31 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %30, i32 %gb) + %32 = bitcast i64 %31 to <2 x i32> + %33 = extractelement <2 x i32> %32, i32 0 + store i32 %33, i32* %p_arrayidx14.1, align 4 + %34 = extractelement <2 x i32> %32, i32 1 + store i32 %34, i32* %p_arrayidx1426.1, align 4 + store i32 %33, i32* %p_d.018.1, align 4 + store i32 %34, i32* %p_d.01823.1, align 4 + %p_21.2 = add i32 %4, 256 + %p_22.2 = add i32 %4, 320 + %p_d.018.2 = getelementptr i32, i32* %dest, i32 %p_21.2 + %p_d.01823.2 = getelementptr i32, i32* %dest, i32 %p_22.2 + %p_24.2 = add i32 %4, 264 + %p_25.2 = add i32 %4, 328 + %p_arrayidx14.2 = getelementptr i32, i32* %dest, i32 %p_24.2 + %p_arrayidx1426.2 = getelementptr i32, i32* %dest, i32 %p_25.2 + %_p_scalar_.2 = load i32, i32* %p_d.018.2, align 4 + %_p_vec_.2 = insertelement <2 x i32> undef, i32 %_p_scalar_.2, i32 0 + %_p_scalar_27.2 = load i32, i32* %p_d.01823.2, align 4 + %_p_vec_28.2 = insertelement <2 x i32> %_p_vec_.2, i32 %_p_scalar_27.2, i32 1 + %35 = bitcast <2 x i32> %_p_vec_28.2 to i64 + %36 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %35, i32 31) + %37 = bitcast i64 %36 to <2 x i32> + %shr9p_vec.2 = ashr <2 x i32> %_p_vec_28.2, %7 + %xorp_vec.2 = xor <2 x i32> %37, %sub12p_vec + %38 = bitcast <2 x i32> %shr9p_vec.2 to i64 + %39 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %36, i64 %38) + %40 = bitcast <2 x i32> %xorp_vec.2 to i64 + %41 = tail call i64 @llvm.hexagon.C2.vmux(i32 %39, i64 %35, i64 %40) + %42 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %41, i32 %gb) + %43 = bitcast i64 %42 to <2 x i32> + %44 = extractelement <2 x i32> %43, i32 0 + store i32 %44, i32* %p_arrayidx14.2, align 4 + %45 = extractelement <2 x i32> %43, i32 1 + store i32 %45, i32* %p_arrayidx1426.2, align 4 + store i32 %44, i32* %p_d.018.2, align 4 + store i32 %45, i32* %p_d.01823.2, align 4 + %p_21.3 = add i32 %4, 384 + %p_22.3 = add i32 %4, 448 + %p_d.018.3 = getelementptr i32, i32* %dest, i32 %p_21.3 + %p_d.01823.3 = getelementptr i32, i32* %dest, i32 %p_22.3 + %p_24.3 = add i32 %4, 392 + %p_25.3 = add i32 %4, 456 + %p_arrayidx14.3 = getelementptr i32, i32* %dest, i32 %p_24.3 + %p_arrayidx1426.3 = getelementptr i32, i32* %dest, i32 %p_25.3 + %_p_scalar_.3 = load i32, i32* %p_d.018.3, align 4 + %_p_vec_.3 = insertelement <2 x i32> undef, i32 %_p_scalar_.3, i32 0 + %_p_scalar_27.3 = load i32, i32* %p_d.01823.3, align 4 + %_p_vec_28.3 = insertelement <2 x i32> %_p_vec_.3, i32 %_p_scalar_27.3, i32 1 + %46 = bitcast <2 x i32> %_p_vec_28.3 to i64 + %47 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %46, i32 31) + %48 = bitcast i64 %47 to <2 x i32> + %shr9p_vec.3 = ashr <2 x i32> %_p_vec_28.3, %7 + %xorp_vec.3 = xor <2 x i32> %48, %sub12p_vec + %49 = bitcast <2 x i32> %shr9p_vec.3 to i64 + %50 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %47, i64 %49) + %51 = bitcast <2 x i32> %xorp_vec.3 to i64 + %52 = tail call i64 @llvm.hexagon.C2.vmux(i32 %50, i64 %46, i64 %51) + %53 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %52, i32 %gb) + %54 = bitcast i64 %53 to <2 x i32> + %55 = extractelement <2 x i32> %54, i32 0 + store i32 %55, i32* %p_arrayidx14.3, align 4 + %56 = extractelement <2 x i32> %54, i32 1 + store i32 %56, i32* %p_arrayidx1426.3, align 4 + store i32 %55, i32* %p_d.018.3, align 4 + store i32 %56, i32* %p_d.01823.3, align 4 + %p_21.4 = add i32 %4, 512 + %p_22.4 = add i32 %4, 576 + %p_d.018.4 = getelementptr i32, i32* %dest, i32 %p_21.4 + %p_d.01823.4 = getelementptr i32, i32* %dest, i32 %p_22.4 + %p_24.4 = add i32 %4, 520 + %p_25.4 = add i32 %4, 584 + %p_arrayidx14.4 = getelementptr i32, i32* %dest, i32 %p_24.4 + %p_arrayidx1426.4 = getelementptr i32, i32* %dest, i32 %p_25.4 + %_p_scalar_.4 = load i32, i32* %p_d.018.4, align 4 + %_p_vec_.4 = insertelement <2 x i32> undef, i32 %_p_scalar_.4, i32 0 + %_p_scalar_27.4 = load i32, i32* %p_d.01823.4, align 4 + %_p_vec_28.4 = insertelement <2 x i32> %_p_vec_.4, i32 %_p_scalar_27.4, i32 1 + %57 = bitcast <2 x i32> %_p_vec_28.4 to i64 + %58 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %57, i32 31) + %59 = bitcast i64 %58 to <2 x i32> + %shr9p_vec.4 = ashr <2 x i32> %_p_vec_28.4, %7 + %xorp_vec.4 = xor <2 x i32> %59, %sub12p_vec + %60 = bitcast <2 x i32> %shr9p_vec.4 to i64 + %61 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %58, i64 %60) + %62 = bitcast <2 x i32> %xorp_vec.4 to i64 + %63 = tail call i64 @llvm.hexagon.C2.vmux(i32 %61, i64 %57, i64 %62) + %64 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %63, i32 %gb) + %65 = bitcast i64 %64 to <2 x i32> + %66 = extractelement <2 x i32> %65, i32 0 + store i32 %66, i32* %p_arrayidx14.4, align 4 + %67 = extractelement <2 x i32> %65, i32 1 + store i32 %67, i32* %p_arrayidx1426.4, align 4 + store i32 %66, i32* %p_d.018.4, align 4 + store i32 %67, i32* %p_d.01823.4, align 4 + %p_21.5 = add i32 %4, 640 + %p_22.5 = add i32 %4, 704 + %p_d.018.5 = getelementptr i32, i32* %dest, i32 %p_21.5 + %p_d.01823.5 = getelementptr i32, i32* %dest, i32 %p_22.5 + %p_24.5 = add i32 %4, 648 + %p_25.5 = add i32 %4, 712 + %p_arrayidx14.5 = getelementptr i32, i32* %dest, i32 %p_24.5 + %p_arrayidx1426.5 = getelementptr i32, i32* %dest, i32 %p_25.5 + %_p_scalar_.5 = load i32, i32* %p_d.018.5, align 4 + %_p_vec_.5 = insertelement <2 x i32> undef, i32 %_p_scalar_.5, i32 0 + %_p_scalar_27.5 = load i32, i32* %p_d.01823.5, align 4 + %_p_vec_28.5 = insertelement <2 x i32> %_p_vec_.5, i32 %_p_scalar_27.5, i32 1 + %68 = bitcast <2 x i32> %_p_vec_28.5 to i64 + %69 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %68, i32 31) + %70 = bitcast i64 %69 to <2 x i32> + %shr9p_vec.5 = ashr <2 x i32> %_p_vec_28.5, %7 + %xorp_vec.5 = xor <2 x i32> %70, %sub12p_vec + %71 = bitcast <2 x i32> %shr9p_vec.5 to i64 + %72 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %69, i64 %71) + %73 = bitcast <2 x i32> %xorp_vec.5 to i64 + %74 = tail call i64 @llvm.hexagon.C2.vmux(i32 %72, i64 %68, i64 %73) + %75 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %74, i32 %gb) + %76 = bitcast i64 %75 to <2 x i32> + %77 = extractelement <2 x i32> %76, i32 0 + store i32 %77, i32* %p_arrayidx14.5, align 4 + %78 = extractelement <2 x i32> %76, i32 1 + store i32 %78, i32* %p_arrayidx1426.5, align 4 + store i32 %77, i32* %p_d.018.5, align 4 + store i32 %78, i32* %p_d.01823.5, align 4 + %p_21.6 = add i32 %4, 768 + %p_22.6 = add i32 %4, 832 + %p_d.018.6 = getelementptr i32, i32* %dest, i32 %p_21.6 + %p_d.01823.6 = getelementptr i32, i32* %dest, i32 %p_22.6 + %p_24.6 = add i32 %4, 776 + %p_25.6 = add i32 %4, 840 + %p_arrayidx14.6 = getelementptr i32, i32* %dest, i32 %p_24.6 + %p_arrayidx1426.6 = getelementptr i32, i32* %dest, i32 %p_25.6 + %_p_scalar_.6 = load i32, i32* %p_d.018.6, align 4 + %_p_vec_.6 = insertelement <2 x i32> undef, i32 %_p_scalar_.6, i32 0 + %_p_scalar_27.6 = load i32, i32* %p_d.01823.6, align 4 + %_p_vec_28.6 = insertelement <2 x i32> %_p_vec_.6, i32 %_p_scalar_27.6, i32 1 + %79 = bitcast <2 x i32> %_p_vec_28.6 to i64 + %80 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %79, i32 31) + %81 = bitcast i64 %80 to <2 x i32> + %shr9p_vec.6 = ashr <2 x i32> %_p_vec_28.6, %7 + %xorp_vec.6 = xor <2 x i32> %81, %sub12p_vec + %82 = bitcast <2 x i32> %shr9p_vec.6 to i64 + %83 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %80, i64 %82) + %84 = bitcast <2 x i32> %xorp_vec.6 to i64 + %85 = tail call i64 @llvm.hexagon.C2.vmux(i32 %83, i64 %79, i64 %84) + %86 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %85, i32 %gb) + %87 = bitcast i64 %86 to <2 x i32> + %88 = extractelement <2 x i32> %87, i32 0 + store i32 %88, i32* %p_arrayidx14.6, align 4 + %89 = extractelement <2 x i32> %87, i32 1 + store i32 %89, i32* %p_arrayidx1426.6, align 4 + store i32 %88, i32* %p_d.018.6, align 4 + store i32 %89, i32* %p_d.01823.6, align 4 + %p_21.7 = add i32 %4, 896 + %p_22.7 = add i32 %4, 960 + %p_d.018.7 = getelementptr i32, i32* %dest, i32 %p_21.7 + %p_d.01823.7 = getelementptr i32, i32* %dest, i32 %p_22.7 + %p_24.7 = add i32 %4, 904 + %p_25.7 = add i32 %4, 968 + %p_arrayidx14.7 = getelementptr i32, i32* %dest, i32 %p_24.7 + %p_arrayidx1426.7 = getelementptr i32, i32* %dest, i32 %p_25.7 + %_p_scalar_.7 = load i32, i32* %p_d.018.7, align 4 + %_p_vec_.7 = insertelement <2 x i32> undef, i32 %_p_scalar_.7, i32 0 + %_p_scalar_27.7 = load i32, i32* %p_d.01823.7, align 4 + %_p_vec_28.7 = insertelement <2 x i32> %_p_vec_.7, i32 %_p_scalar_27.7, i32 1 + %90 = bitcast <2 x i32> %_p_vec_28.7 to i64 + %91 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %90, i32 31) + %92 = bitcast i64 %91 to <2 x i32> + %shr9p_vec.7 = ashr <2 x i32> %_p_vec_28.7, %7 + %xorp_vec.7 = xor <2 x i32> %92, %sub12p_vec + %93 = bitcast <2 x i32> %shr9p_vec.7 to i64 + %94 = tail call i32 @llvm.hexagon.A2.vcmpweq(i64 %91, i64 %93) + %95 = bitcast <2 x i32> %xorp_vec.7 to i64 + %96 = tail call i64 @llvm.hexagon.C2.vmux(i32 %94, i64 %90, i64 %95) + %97 = tail call i64 @llvm.hexagon.S2.asl.r.vw(i64 %96, i32 %gb) + %98 = bitcast i64 %97 to <2 x i32> + %99 = extractelement <2 x i32> %98, i32 0 + store i32 %99, i32* %p_arrayidx14.7, align 4 + %100 = extractelement <2 x i32> %98, i32 1 + store i32 %100, i32* %p_arrayidx1426.7, align 4 + store i32 %99, i32* %p_d.018.7, align 4 + store i32 %100, i32* %p_d.01823.7, align 4 + ret void +} + +declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) #1 + +declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) #1 + +declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1 + +declare i32 @llvm.hexagon.A2.vcmpweq(i64, i64) #1 + +declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64) #1 + +declare i64 @llvm.hexagon.S2.asl.r.vw(i64, i32) #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } + +!0 = !{!"int", !1} +!1 = !{!"omnipotent char", !2} +!2 = !{!"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/vect/vect-vsplatb.ll b/test/CodeGen/Hexagon/vect/vect-vsplatb.ll new file mode 100644 index 0000000..6996dd1 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-vsplatb.ll @@ -0,0 +1,29 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; Make sure we build the constant vector <7, 7, 7, 7> with a vsplatb. +; CHECK: vsplatb +@B = common global [400 x i8] zeroinitializer, align 8 +@A = common global [400 x i8] zeroinitializer, align 8 +@C = common global [400 x i8] zeroinitializer, align 8 + +define void @run() nounwind { +entry: + br label %polly.loop_body + +polly.loop_after: ; preds = %polly.loop_body + ret void + +polly.loop_body: ; preds = %entry, %polly.loop_body + %polly.loopiv25 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ] + %polly.next_loopiv = add i32 %polly.loopiv25, 4 + %p_arrayidx1 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %polly.loopiv25 + %p_arrayidx = getelementptr [400 x i8], [400 x i8]* @B, i32 0, i32 %polly.loopiv25 + %vector_ptr = bitcast i8* %p_arrayidx to <4 x i8>* + %_p_vec_full = load <4 x i8>, <4 x i8>* %vector_ptr, align 8 + %mulp_vec = mul <4 x i8> %_p_vec_full, <i8 7, i8 7, i8 7, i8 7> + %vector_ptr14 = bitcast i8* %p_arrayidx1 to <4 x i8>* + %_p_vec_full15 = load <4 x i8>, <4 x i8>* %vector_ptr14, align 8 + %addp_vec = add <4 x i8> %_p_vec_full15, %mulp_vec + store <4 x i8> %addp_vec, <4 x i8>* %vector_ptr14, align 8 + %0 = icmp slt i32 %polly.next_loopiv, 400 + br i1 %0, label %polly.loop_body, label %polly.loop_after +} diff --git a/test/CodeGen/Hexagon/vect/vect-vsplath.ll b/test/CodeGen/Hexagon/vect/vect-vsplath.ll new file mode 100644 index 0000000..f520710 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-vsplath.ll @@ -0,0 +1,29 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; Make sure we build the constant vector <7, 7, 7, 7> with a vsplath. +; CHECK: vsplath +@B = common global [400 x i16] zeroinitializer, align 8 +@A = common global [400 x i16] zeroinitializer, align 8 +@C = common global [400 x i16] zeroinitializer, align 8 + +define void @run() nounwind { +entry: + br label %polly.loop_body + +polly.loop_after: ; preds = %polly.loop_body + ret void + +polly.loop_body: ; preds = %entry, %polly.loop_body + %polly.loopiv26 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ] + %polly.next_loopiv = add nsw i32 %polly.loopiv26, 4 + %p_arrayidx1 = getelementptr [400 x i16], [400 x i16]* @A, i32 0, i32 %polly.loopiv26 + %p_arrayidx = getelementptr [400 x i16], [400 x i16]* @B, i32 0, i32 %polly.loopiv26 + %vector_ptr = bitcast i16* %p_arrayidx to <4 x i16>* + %_p_vec_full = load <4 x i16>, <4 x i16>* %vector_ptr, align 8 + %mulp_vec = mul <4 x i16> %_p_vec_full, <i16 7, i16 7, i16 7, i16 7> + %vector_ptr15 = bitcast i16* %p_arrayidx1 to <4 x i16>* + %_p_vec_full16 = load <4 x i16>, <4 x i16>* %vector_ptr15, align 8 + %addp_vec = add <4 x i16> %_p_vec_full16, %mulp_vec + store <4 x i16> %addp_vec, <4 x i16>* %vector_ptr15, align 8 + %0 = icmp slt i32 %polly.next_loopiv, 400 + br i1 %0, label %polly.loop_body, label %polly.loop_after +} diff --git a/test/CodeGen/Hexagon/vect/vect-vsubb-1.ll b/test/CodeGen/Hexagon/vect/vect-vsubb-1.ll new file mode 100644 index 0000000..8ac76a0 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-vsubb-1.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: vsubub + +define <4 x i8> @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind { +entry: + %0 = sub <4 x i8> %a, %b + ret <4 x i8> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-vsubb.ll b/test/CodeGen/Hexagon/vect/vect-vsubb.ll new file mode 100644 index 0000000..73cfc74 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-vsubb.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: vsubub + +define <8 x i8> @t_i8x8(<8 x i8> %a, <8 x i8> %b) nounwind { +entry: + %0 = sub <8 x i8> %a, %b + ret <8 x i8> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-vsubh-1.ll b/test/CodeGen/Hexagon/vect/vect-vsubh-1.ll new file mode 100644 index 0000000..c1f87bf --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-vsubh-1.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: vsubh + +define <4 x i16> @t_i4x16(<4 x i16> %a, <4 x i16> %b) nounwind { +entry: + %0 = sub <4 x i16> %a, %b + ret <4 x i16> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-vsubh.ll b/test/CodeGen/Hexagon/vect/vect-vsubh.ll new file mode 100644 index 0000000..cc7e595 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-vsubh.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: vsubh + +define <2 x i16> @t_i2x16(<2 x i16> %a, <2 x i16> %b) nounwind { +entry: + %0 = sub <2 x i16> %a, %b + ret <2 x i16> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-vsubw.ll b/test/CodeGen/Hexagon/vect/vect-vsubw.ll new file mode 100644 index 0000000..ba326a3 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-vsubw.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: vsubw + +define <2 x i32> @t_i2x32(<2 x i32> %a, <2 x i32> %b) nounwind { +entry: + %0 = sub <2 x i32> %a, %b + ret <2 x i32> %0 +} diff --git a/test/CodeGen/Hexagon/vect/vect-xor.ll b/test/CodeGen/Hexagon/vect/vect-xor.ll new file mode 100644 index 0000000..9611855 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-xor.ll @@ -0,0 +1,38 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s + +; Check that the parsing succeeded. +; CHECK: r{{[0-9]+:[0-9]+}} = xor(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}}) +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +@window_size = global i32 65536, align 4 +@prev = external global [0 x i16], align 8 +@block_start = common global i32 0, align 4 +@prev_length = common global i32 0, align 4 +@strstart = common global i32 0, align 4 +@match_start = common global i32 0, align 4 +@max_chain_length = common global i32 0, align 4 +@good_match = common global i32 0, align 4 + +define void @fill_window() #0 { +entry: + br label %polly.loop_body + +polly.loop_after: ; preds = %polly.loop_body + ret void + +polly.loop_body: ; preds = %entry, %polly.loop_body + %polly.loopiv36 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ] + %polly.next_loopiv = add nsw i32 %polly.loopiv36, 4 + %p_arrayidx4 = getelementptr [0 x i16], [0 x i16]* @prev, i32 0, i32 %polly.loopiv36 + %vector_ptr = bitcast i16* %p_arrayidx4 to <4 x i16>* + %_p_vec_full = load <4 x i16>, <4 x i16>* %vector_ptr, align 2 + %cmp1p_vicmp = icmp slt <4 x i16> %_p_vec_full, zeroinitializer + %subp_vec = xor <4 x i16> %_p_vec_full, <i16 -32768, i16 -32768, i16 -32768, i16 -32768> + %sel1p_vsel = select <4 x i1> %cmp1p_vicmp, <4 x i16> %subp_vec, <4 x i16> zeroinitializer + store <4 x i16> %sel1p_vsel, <4 x i16>* %vector_ptr, align 2 + %0 = icmp slt i32 %polly.next_loopiv, 32768 + br i1 %0, label %polly.loop_body, label %polly.loop_after +} + +attributes #0 = { nounwind "fp-contract-model"="standard" "no-frame-pointer-elim-non-leaf" "realign-stack" "relocation-model"="static" "ssp-buffers-size"="8" } diff --git a/test/CodeGen/Hexagon/vect/vect-zeroextend.ll b/test/CodeGen/Hexagon/vect/vect-zeroextend.ll new file mode 100644 index 0000000..3d0b794 --- /dev/null +++ b/test/CodeGen/Hexagon/vect/vect-zeroextend.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=hexagon < %s +; Used to fail with "Cannot select: 0x16cb2d0: v4i16 = zero_extend" + +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-a0:0-n32" +target triple = "hexagon-unknown-linux-gnu" + +define void @foo() nounwind { +entry: + br i1 undef, label %for.cond30.preheader.lr.ph, label %for.end425 + +for.cond30.preheader.lr.ph: ; preds = %entry + br label %for.cond37.preheader + +for.cond37.preheader: ; preds = %for.cond37.preheader, %for.cond30.preheader.lr.ph + %_p_vec_full = load <3 x i8>, <3 x i8>* undef, align 8 + %0 = zext <3 x i8> %_p_vec_full to <3 x i16> + store <3 x i16> %0, <3 x i16>* undef, align 8 + br label %for.cond37.preheader + +for.end425: ; preds = %entry + ret void +} diff --git a/test/CodeGen/Hexagon/zextloadi1.ll b/test/CodeGen/Hexagon/zextloadi1.ll index b58d933..9ce7bea 100644 --- a/test/CodeGen/Hexagon/zextloadi1.ll +++ b/test/CodeGen/Hexagon/zextloadi1.ll @@ -13,13 +13,13 @@ @i129_s = external global i129 define void @i129_ls() nounwind { - %tmp = load i129* @i129_l + %tmp = load i129, i129* @i129_l store i129 %tmp, i129* @i129_s ret void } define void @i65_ls() nounwind { - %tmp = load i65* @i65_l + %tmp = load i65, i65* @i65_l store i65 %tmp, i65* @i65_s ret void } |